PIC18F25J10T-L/P [MICROCHIP]
28/40/44-Pin High-Performance RISC Microcontrollers with nanoWatt Technology; 28 /40/ 44引脚高性能RISC微控制器采用纳瓦技术
| 型号： | PIC18F25J10T-L/P |
| 厂家： | 
MICROCHIP |
| 描述： | 28/40/44-Pin High-Performance RISC Microcontrollers with nanoWatt Technology |
| 文件： | 总358页 (文件大小：5699K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PIC18F45J10 Family
Data Sheet
28/40/44-Pin High-Performance
RISC Microcontrollers
with nanoWatt Technology
© 2007 Microchip Technology Inc.
Preliminary
DS39682C
Note the following details of the code protection feature on Microchip devices:
•
Microchip products meet the specification contained in their particular Microchip Data Sheet.
•
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
•
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
•
•
Microchip is willing to work with the customer who is concerned about the integrity of their code.
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION,
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
QUALITY, PERFORMANCE, MERCHANTABILITY OR
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hold harmless Microchip from any and all damages, claims,
suits, or expenses resulting from such use. No licenses are
conveyed, implicitly or otherwise, under any Microchip
intellectual property rights.
Trademarks
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DS39682C-page ii
Preliminary
© 2007 Microchip Technology Inc.
PIC18F45J10 FAMILY
28/40/44-Pin High-Performance, RISC Microcontrollers
with nanoWatt Technology
Special Microcontroller Features:
Peripheral Highlights:
• Operating voltage range: 2.0V to 3.6V
• 5.5V tolerant input (digital pins only)
• On-chip 2.5V regulator
• High-current sink/source 25 mA/25 mA
(PORTB and PORTC)
• Three programmable external interrupts
• Four input change interrupts
• Low-power, high-speed CMOS Flash technology
• C compiler optimized architecture:
• One Capture/Compare/PWM (CCP) module
• One Enhanced Capture/Compare/PWM (ECCP)
module:
- Optional extended instruction set designed to
optimize re-entrant code
- One, two or four PWM outputs
- Selectable polarity
• Priority levels for interrupts
• 8 x 8 Single-Cycle Hardware Multiplier
• Extended Watchdog Timer (WDT):
- Programmable period from 4 ms to 131s
- Programmable dead time
- Auto-Shutdown and Auto-Restart
• Two Master Synchronous Serial Port (MSSP)
modules supporting 3-wire SPI™ (all 4 modes)
and I2C™ Master and Slave modes
• Single-Supply In-Circuit Serial Programming™
(ICSP™) via two pins
• In-Circuit Debug (ICD) with three Break points via
two pins
• One Enhanced Addressable USART module:
- Supports RS-485, RS-232 and LIN 1.2
- Auto-Wake-up on Start bit
• Power-Managed modes:
- Run: CPU on, peripherals on
- Idle: CPU off, peripherals on
- Sleep: CPU off, peripherals off
- Auto-Baud Detect
• 10-bit, up to 13-channel Analog-to-Digital
Converter module (A/D):
- Auto-acquisition capability
Flexible Oscillator Structure:
- Conversion available during Sleep
- Self-calibration feature
• Two Crystal modes, up to 40 MHz
• Two External Clock modes, up to 40 MHz
• Internal 31 kHz oscillator
• Dual analog comparators with input multiplexing
• Secondary oscillator using Timer1 @ 32 kHz
• Two-Speed Oscillator Start-up
• Fail-Safe Clock Monitor:
- Allows for safe shutdown if peripheral clock
stops
Program Memory
SRAMData
MSSP
CCP/
10-bit
A/D (ch)
Device
Memory
(bytes)
I/O
ECCP
Flash # Single-Word
(bytes) Instructions
Master
I C™
SPI™
2
(PWM)
PIC18F24J10
PIC18F25J10
PIC18F44J10
PIC18F45J10
16K
32K
16K
32K
8192
16384
8192
1024
1024
1024
1024
21
21
32
32
10
10
13
13
2/0
2/0
1/1
1/1
1
1
2
2
Y
Y
Y
Y
Y
Y
Y
Y
1
1
1
1
2
2
2
2
1/2
1/2
1/2
1/2
16384
© 2007 Microchip Technology Inc.
Preliminary
DS39682C-page 1
PIC18F45J10 FAMILY
Pin Diagrams
28-Pin SPDIP, SOIC, SSOP (300 MIL)
28
27
26
25
24
23
22
21
20
19
18
17
16
15
1
2
3
4
5
RB7/KBI3/PGD
RB6/KBI2/PGC
RB5/KBI1/T0CKI/C1OUT
RB4/KBI0/AN11
RB3/AN9/CCP2*
RB2/INT2/AN8
RB1/INT1/AN10
RB0/INT0/FLT0/AN12
VDD
VSS
RC7/RX/DT
RC6/TX/CK
RC5/SDO1
MCLR
RA0/AN0
RA1/AN1
RA2/AN2/VREF-/CVREF
RA3/AN3/VREF+
VDDCORE/VCAP
RA5/AN4/SS1/C2OUT
VSS
6
7
8
9
OSC1/CLKI
OSC2/CLKO
RC0/T1OSO/T1CKI
RC1/T1OSI/CCP2*
RC2/CCP1
10
11
12
13
14
RC4/SDI1/SDA1
RC3/SCK1/SCL1
* Pin feature is dependent on device configuration.
28-Pin QFN
28272625242322
RA2/AN2/VREF-/CVREF
RA3/AN3/VREF+
VDDCORE/VCAP
RA5/AN4/SS1/C2OUT
VSS
1
21
20
19
18
17
16
15
RB3/AN9/CCP2*
RB2/INT2/AN8
RB1/INT1/AN10
RB0/INT0/FLT0/AN12
VDD
2
3
4
5
6
7
PIC18F24J10
PIC18F25J10
OSC1/CLKI
OSC2/CLKO
VSS
RC7/RX/DT
8
9 1011 121314
* Pin feature is dependent on device configuration.
DS39682C-page 2
Preliminary
© 2007 Microchip Technology Inc.
PIC18F45J10 FAMILY
Pin Diagrams (Continued)
40-Pin PDIP (600 MIL)
MCLR
RA0/AN0
1
2
3
4
5
6
7
8
RB7/KBI3/PGD
RB6/KBI2/PGC
RB5/KBI1/T0CKI/C1OUT
RB4/KBI0/AN11
RB3/AN9/CCP2*
RB2/INT2/AN8
40
39
RA1/AN1
RA2/AN2/VREF-/CVREF
38
37
RA3/AN3/VREF+
VDDCORE/VCAP
36
35
RA5/AN4/SS1/C2OUT
RE0/RD/AN5
RE1/WR/AN6
RE2/CS/AN7
VDD
VSS
OSC1/CLKI
OSC2/CLKO
RC0/T1OSO/T1CKI
RC1/T1OSI/CCP2*
RC2/CCP1/P1A
RB1/INT1/AN10
RB0/INT0/FLT0/AN12
VDD
32
VSS
31
34
33
9
10
11
12
13
14
15
16
17
18
RD7/PSP7/P1D
RD6/PSP6/P1C
RD5/PSP5/P1B
RD4/PSP4
RC7/RX/DT
RC6/TX/CK
RC5/SDO1
30
29
28
27
26
25
24
RC3/SCK1/SCL1
RC4/SDI1/SDA1
23
RD0/PSP0/SCK2/SCL2
RD3/PSP3/SS2
19
20
22
RD1/PSP1/SDI2/SDA2
RD2/PSP2/SDO2
21
* Pin feature is dependent on device configuration.
44-Pin QFN
OSC2/CLKO
OSC1/CLKI
VSS
AVSS
VDD
RC7/RX/DT
RD4/PSP4
RD5/PSP5/P1B
RD6/PSP6/P1C
1
2
3
4
5
6
7
8
9
33
32
31
30
29
28
27
26
RD7/PSP7/P1D
PIC18F44J10
PIC18F45J10
AVDD
VSS
AVDD
VDD
RE2/CS/AN7
RE1/WR/AN6
RE0/RD/AN5
RA5/AN4/SS1/C2OUT
VDDCORE/VCAP
RB0/INT0/FLT0/AN12
RB1/INT1/AN10
RB2/INT2/AN8
25
24
23
10
11
* Pin feature is dependent on device configuration.
© 2007 Microchip Technology Inc.
Preliminary
DS39682C-page 3
PIC18F45J10 FAMILY
Pin Diagrams (Continued)
44-Pin TQFP
33
32
31
30
29
28
27
26
25
24
23
NC
1
2
3
4
5
6
7
8
9
10
11
RC7/RX/DT
RD4/PSP4
RD5/PSP5/P1B
RD6/PSP6/P1C
RD7/PSP7/P1D
VSS
RC0/T1OSO/T1CKI
OSC2/CLKO
OSC1/CLKI
VSS
VDD
RE2/CS/AN7
RE1/WR/AN6
RE0/RD/AN5
RA5/AN4/SS1/C2OUT
VDDCORE/VCAP
PIC18F44J10
PIC18F45J10
VDD
RB0/INT0/FLT0/AN12
RB1/INT1/AN10
RB2/INT2/AN8
RB3/AN9/CCP2*
* Pin feature is dependent on device configuration.
DS39682C-page 4
Preliminary
© 2007 Microchip Technology Inc.
PIC18F45J10 FAMILY
Table of Contents
1.0 Device Overview .......................................................................................................................................................................... 7
2.0 Oscillator Configurations ............................................................................................................................................................ 23
3.0 Power-Managed Modes ............................................................................................................................................................. 31
4.0 Reset.......................................................................................................................................................................................... 37
5.0 Memory Organization................................................................................................................................................................. 47
6.0 Flash Program Memory.............................................................................................................................................................. 67
7.0 8 x 8 Hardware Multiplier............................................................................................................................................................ 77
8.0 Interrupts .................................................................................................................................................................................... 79
9.0 I/O Ports ..................................................................................................................................................................................... 93
10.0 Timer0 Module ......................................................................................................................................................................... 111
11.0 Timer1 Module ......................................................................................................................................................................... 115
12.0 Timer2 Module ......................................................................................................................................................................... 121
13.0 Capture/Compare/PWM (CCP) Modules ................................................................................................................................. 123
14.0 Enhanced Capture/Compare/PWM (ECCP) Module................................................................................................................ 131
15.0 Master Synchronous Serial Port (MSSP) Module .................................................................................................................... 145
16.0 Enhanced Universal Synchronous Asynchronous Receiver Transmitter (EUSART)............................................................... 187
17.0 10-Bit Analog-to-Digital Converter (A/D) Module ..................................................................................................................... 209
18.0 Comparator Module.................................................................................................................................................................. 219
19.0 Comparator Voltage Reference Module................................................................................................................................... 225
20.0 Special Features of the CPU.................................................................................................................................................... 229
21.0 Instruction Set Summary.......................................................................................................................................................... 241
22.0 Development Support............................................................................................................................................................... 291
23.0 Electrical Characteristics.......................................................................................................................................................... 295
24.0 DC and AC Characteristics Graphs and Tables....................................................................................................................... 329
25.0 Packaging Information.............................................................................................................................................................. 331
Appendix A: Revision History............................................................................................................................................................. 341
Appendix B: Migration Between High-End Device Families............................................................................................................... 341
The Microchip Web Site..................................................................................................................................................................... 353
Customer Change Notification Service .............................................................................................................................................. 353
Customer Support.............................................................................................................................................................................. 353
Reader Response.............................................................................................................................................................................. 354
PIC18F45J10 family Product Identification System........................................................................................................................... 355
© 2007 Microchip Technology Inc.
Preliminary
DS39682C-page 5
PIC18F45J10 FAMILY
TO OUR VALUED CUSTOMERS
It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip
products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and
enhanced as new volumes and updates are introduced.
If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via
E-mail at docerrors@microchip.com or fax the Reader Response Form in the back of this data sheet to (480) 792-4150. We
welcome your feedback.
Most Current Data Sheet
To obtain the most up-to-date version of this data sheet, please register at our Worldwide Web site at:
http://www.microchip.com
You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page.
The last character of the literature number is the version number, (e.g., DS30000A is version A of document DS30000).
Errata
An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current
devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision
of silicon and revision of document to which it applies.
To determine if an errata sheet exists for a particular device, please check with one of the following:
•
•
Microchip’s Worldwide Web site; http://www.microchip.com
Your local Microchip sales office (see last page)
When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are
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DS39682C-page 6
Preliminary
© 2007 Microchip Technology Inc.
PIC18F45J10 FAMILY
1.1.2
MULTIPLE OSCILLATOR OPTIONS
AND FEATURES
1.0
DEVICE OVERVIEW
This document contains device specific information for
the following devices:
All of the devices in the PIC18F45J10 family offer three
different oscillator options. These include:
• PIC18F24J10
• PIC18F25J10
• PIC18F44J10
• PIC18F45J10
• PIC18LF24J10
• PIC18LF25J10
• PIC18LF44J10
• PIC18LF45J10
• One Crystal mode, using crystals or ceramic
resonators
• One External Clock mode
• INTRC source (approximately 31 kHz)
This family offers the advantages of all PIC18
microcontrollers – namely, high computational perfor-
mance at an economical price. The PIC18F45J10 family
introduces design enhancements that make these micro-
controllers a logical choice for many high-performance,
power sensitive applications.
Besides its availability as a clock source, the internal
oscillator block provides a stable reference source that
gives the family additional features for robust
operation:
• Fail-Safe Clock Monitor: This option constantly
monitors the main clock source against a refer-
ence signal provided by the internal oscillator. If a
clock failure occurs, the controller is switched to
the internal oscillator block, allowing for continued
low-speed operation or a safe application
shutdown.
1.1
New Core Features
1.1.1
nanoWatt TECHNOLOGY
All of the devices in the PIC18F45J10 family
incorporate a range of features that can significantly
reduce power consumption during operation. Key
items include:
• Two-Speed Start-up: This option allows the
internal oscillator to serve as the clock source
from Power-on Reset, or wake-up from Sleep
mode, until the primary clock source is available.
• Alternate Run Modes: By clocking the controller
from the Timer1 source or the internal oscillator
block, power consumption during code execution
can be reduced by as much as 90%.
• Multiple Idle Modes: The controller can also run
with its CPU core disabled but the peripherals still
active. In these states, power consumption can be
reduced even further, to as little as 4% of normal
operation requirements.
• On-the-fly Mode Switching: The power-managed
modes are invoked by user code during operation,
allowing the user to incorporate power-saving
ideas into their application’s software design.
• Low Consumption in Key Modules: The
power requirements for both Timer1 and the
Watchdog Timer are minimized. See
Section 23.0 “Electrical Characteristics”
for values.
© 2007 Microchip Technology Inc.
Preliminary
DS39682C-page 7
PIC18F45J10 FAMILY
1.2
Other Special Features
1.3
Details on Individual Family
Members
• Communications: The PIC18F45J10 family
incorporates a range of serial communication
peripherals, including 1 independent Enhanced
USART and 2 Master SSP modules capable of
both SPI and I2C (Master and Slave) modes of
operation. Also, one of the general purpose I/O
ports can be reconfigured as an 8-bit Parallel
Slave Port for direct processor-to-processor
communications.
Devices in the PIC18F45J10 family are available in
28-pin and 40/44-pin packages. Block diagrams for the
two groups are shown in Figure 1-1 and Figure 1-2.
The devices are differentiated from each other in five
ways:
1. Flash program memory (16 Kbytes for
PIC18F24J10/44J10 devices and 32 Kbytes for
PIC18F25J10/45J10).
• Self-programmability: These devices can write
to their own program memory spaces under
internal software control. By using a bootloader
routine, it becomes possible to create an
2. A/D channels (10 for 28-pin devices, 13 for
40/44-pin devices).
3. I/O ports (3 bidirectional ports on 28-pin devices,
5 bidirectional ports on 40/44-pin devices).
application that can update itself in the field.
• Extended Instruction Set: The PIC18F45J10
family introduces an optional extension to the
PIC18 instruction set, which adds 8 new instruc-
tions and an Indexed Addressing mode. This
extension, enabled as a device configuration
option, has been specifically designed to optimize
re-entrant application code originally developed in
high-level languages, such as C.
4. CCP and Enhanced CCP implementation
(28-pin devices have 2 standard CCP mod-
ules, 40/44-pin devices have one standard CCP
module and one ECCP module).
5. Parallel Slave Port (present only on 40/44-pin
devices).
6. One MSSP module for PIC18F24J10/25J10
devices
and
2
MSSP
modules
for
• Enhanced CCP module: In PWM mode, this
module provides 1, 2 or 4 modulated outputs for
controlling half-bridge and full-bridge drivers.
Other features include Auto-Shutdown, for
disabling PWM outputs on interrupt or other select
conditions and Auto-Restart, to reactivate outputs
once the condition has cleared.
PIC18F44J10/45J10 devices
7. Parts designated with an “F” part number (i.e.,
PIC18F25J10) have a minimum VDD of 2.8 volts,
whereas parts designated with an “LF” part
number (i.e., PIC18LF25J10) can operate
between 2.0-3.6 volts on VDD; however,
VDDCORE should never exceed VDD.
• Enhanced Addressable USART: This serial
communication module is capable of standard
RS-232 operation and provides support for the LIN
bus protocol. Other enhancements include
automatic baud rate detection and a 16-bit Baud
Rate Generator for improved resolution.
All other features for devices in this family are identical.
These are summarized in Table 1-1.
The pinouts for all devices are listed in Table 1-2 and
Table 1-3.
The PIC18F45J10 family of devices provides an on-chip
voltage regulator to supply the correct voltage levels to
the core. Parts designated with an “F” part number (such
as PIC18F25J10) have the voltage regulator enabled.
These parts can run from 2.7-3.6 volts on VDD but should
have the VDDCORE pin connected to VSS through a low-
ESR capacitor. Parts designated with an “LF” part
number (such as PIC18LF24J10) do not enable the
voltage regulator. An external supply of 2.0-2.7 Volts has
to be supplied to the VDDCORE pin while 2.0-3.6 Volts
can be supplied to VDD ( VDDCORE should never exceed
VDD). See Section 20.3 “On-Chip Voltage Regulator”
for more details about the internal voltage regulator.
• 10-bit A/D Converter: This module incorporates
programmable acquisition time, allowing for a
channel to be selected and a conversion to be
initiated without waiting for a sampling period and
thus, reduce code overhead.
• Extended Watchdog Timer (WDT): This
enhanced version incorporates a 16-bit prescaler,
allowing an extended time-out range that is stable
across operating voltage and temperature. See
Section 23.0 “Electrical Characteristics” for
time-out periods.
DS39682C-page 8
Preliminary
© 2007 Microchip Technology Inc.
PIC18F45J10 FAMILY
TABLE 1-1:
DEVICE FEATURES
Features
PIC18F24J10
PIC18F25J10
PIC18F44J10
PIC18F45J10
Operating Frequency
DC – 40 MHz
16384
DC – 40 MHz
32768
DC – 40 MHz
16384
DC – 40 MHz
32768
Program Memory (Bytes)
Program Memory
(Instructions)
8192
16384
8192
16384
Data Memory (Bytes)
Interrupt Sources
I/O Ports
768
1536
768
1536
19
19
20
20
Ports A, B, C
Ports A, B, C
Ports A, B, C, D, E
Ports A, B, C, D, E
Timers
3
2
0
3
2
0
3
1
1
3
1
1
Capture/Compare/PWM Modules
Enhanced
Capture/Compare/PWM Modules
Serial Communications
MSSP,
MSSP,
MSSP,
MSSP,
Enhanced USART
Enhanced USART
Enhanced USART
Enhanced USART
Parallel Communications (PSP)
10-bit Analog-to-Digital Module
Resets (and Delays)
No
No
Yes
Yes
10 Input Channels
10 Input Channels
13 Input Channels
13 Input Channels
(1)
(1)
(1)
(1)
POR, BOR
,
POR, BOR
,
POR, BOR
,
POR, BOR ,
RESETInstruction,
Stack Full, Stack
Underflow (PWRT,
OST),
RESETInstruction,
Stack Full, Stack
Underflow (PWRT,
OST),
RESETInstruction,
Stack Full, Stack
Underflow (PWRT,
OST),
RESETInstruction,
Stack Full, Stack
Underflow (PWRT,
OST),
MCLR, WDT
MCLR, WDT
MCLR, WDT
MCLR, WDT
Programmable Brown-out Reset
Instruction Set
Yes
Yes
Yes
Yes
75 Instructions;
75 Instructions;
75 Instructions;
75 Instructions;
83 with Extended
83 with Extended
83 with Extended
83 with Extended
Instruction Set enabled Instruction Set enabled Instruction Set enabled Instruction Set enabled
Packages
28-pin SPDIP
28-pin SOIC
28-pin SSOP
28-pin QFN
28-pin SPDIP
28-pin SOIC
28-pin SSOP
28-pin QFN
40-pin PDIP
44-pin QFN
44-pin TQFP
40-pin PDIP
44-pin QFN
44-pin TQFP
Note 1: BOR is not available in PIC18LF2XJ10/4XJ10 devices.
© 2007 Microchip Technology Inc.
Preliminary
DS39682C-page 9
PIC18F45J10 FAMILY
FIGURE 1-1:
PIC18F24J10/25J10 (28-PIN) BLOCK DIAGRAM
Data Bus<8>
Table Pointer<21>
Data Latch
PORTA
8
8
inc/dec logic
21
RA0/AN0
RA1/AN1
Data Memory
(1 Kbyte)
PCLATH
PCLATU
RA2/AN2/VREF-/CVREF
RA3/AN3/VREF+
Address Latch
20
PCU PCH PCL
Program Counter
RA5/AN4/SS1/C2OUT
12
Data Address<12>
31 Level Stack
STKPTR
4
BSR
12
FSR0
FSR1
FSR2
4
Address Latch
Access
Bank
Program Memory
(16/32 Kbytes)
12
Data Latch
PORTB
RB0/INT0/FLT0/AN12
RB1/INT1/AN10
inc/dec
logic
8
Table Latch
RB2/INT2/AN8
RB3/AN9/CCP2(1)
RB4/KBI0/AN11
Address
Decode
ROM Latch
IR
RB5/KBI1/T0CKI/C1OUT
RB6/KBI2/PGC
RB7/KBI3/PGD
Instruction Bus <16>
8
State Machine
Control Signals
Instruction
Decode and
Control
PRODH PRODL
8 x 8 Multiply
PORTC
RC0/T1OSO/T1CKI
RC1/T1OSI/CCP2(1)
RC2/CCP1
3
8
W
BITOP
8
RC3/SCK1/SCL1
RC4/SDI1/SDA1
8
8
RC5/SDO1
RC6/TX/CK
RC7/RX/DT
VDDCORE
OSC1
Internal
Oscillator
Block
Power-up
Timer
8
8
Oscillator
Start-up Timer
ALU<8>
8
INTRC
Oscillator
OSC2
Power-on
Reset
T1OSI
T1OSO
Watchdog
Timer
Brown-out(2)
Reset
Fail-Safe
Precision
Band Gap
Reference
Single-Supply
Programming
MCLR
In-Circuit
Debugger
VDD, VSS
Clock Monitor
ADC
10-bit
BOR(2)
Timer0
CCP1
Timer1
CCP2
Timer2
MSSP
Comparator
EUSART
Note 1: CCP2 is multiplexed with RC1 when configuration bit CCP2MX is set, or RB3 when CCP2MX is not set.
2: BOR is not available in PIC18LF2XJ10/4XJ10 devices.
DS39682C-page 10
Preliminary
© 2007 Microchip Technology Inc.
PIC18F45J10 FAMILY
FIGURE 1-2:
PIC18F44J10/45J10 (40/44-PIN) BLOCK DIAGRAM
Data Bus<8>
PORTA
Table Pointer<21>
RA0/AN0
RA1/AN1
Data Latch
8
8
inc/dec logic
21
RA2/AN2/VREF-/CVREF
RA3/AN3/VREF+
Data Memory
(3.9 Kbytes)
PCLATU PCLATH
RA5/AN4/SS1/C2OUT
Address Latch
20
PCU PCH PCL
Program Counter
12
Data Address<12>
PORTB
31 Level Stack
STKPTR
RB0/INT0/FLT0/AN12
RB1/INT1/AN10
4
BSR
12
FSR0
FSR1
FSR2
4
Address Latch
Access
Bank
RB2/INT2/AN8
Program Memory
(16/32 Kbytes)
RB3/AN9/CCP2(1)
RB4/KBI0/AN11
12
Data Latch
RB5/KBI1/T0CKI/C1OUT
RB6/KBI2/PGC
RB7/KBI3/PGD
inc/dec
logic
8
Table Latch
PORTC
Address
Decode
ROM Latch
IR
RC0/T1OSO/T1CKI
RC1/T1OSI/CCP2(1)
RC2/CCP1/P1A
Instruction Bus <16>
RC3/SCK1/SCL1
RC4/SDI1/SDA1
RC5/SDO1
8
RC6/TX/CK
State Machine
Control Signals
Instruction
Decode and
Control
RC7/RX/DT
PRODH PRODL
8 x 8 Multiply
PORTD
3
RD0/PSP0/SCK2/SCL2
RD1/PSP1/SDI2/SDA2
RD2/PSP2/SDO2
RD3/PSP3/SS2
RD4/PSP4
RD5/PSP5/P1B
RD6/PSP6/P1C
RD7/PSP7/P1D
8
W
BITOP
8
8
8
VDDCORE
OSC1
Internal
Oscillator
Block
Power-up
Timer
8
8
Oscillator
Start-up Timer
ALU<8>
8
INTRC
Oscillator
OSC2
T1OSI
T1OSO
Power-on
Reset
Watchdog
Timer
Brown-out(2)
Reset
Fail-Safe
PORTE
RE0/RD/AN5
RE1/WR/AN6
RE2/CS/AN7
Precision
Band Gap
Reference
Single-Supply
Programming
In-Circuit
MCLR
VDD, VSS
Clock Monitor
Debugger
ADC
10-bit
BOR(2)
Timer0
ECCP1
Timer1
CCP2
Timer2
MSSP
Comparator
EUSART
Note 1: CCP2 is multiplexed with RC1 when configuration bit CCP2MX is set, or RB3 when CCP2MX is not set.
2: BOR is not available in PIC18LF2XJ10/4XJ10 devices.
© 2007 Microchip Technology Inc.
Preliminary
DS39682C-page 11
PIC18F45J10 FAMILY
TABLE 1-2:
PIC18F24J10/25J10 PINOUT I/O DESCRIPTIONS
Pin Number
Pin Buffer
Type Type
SPDIP,
SOIC, QFN
SSOP
Pin Name
Description
MCLR
MCLR
1
26
Master Clear (input) or programming voltage (input).
Master Clear (Reset) input. This pin is an active-low
Reset to the device.
I
ST
OSC1/CLKI
OSC1
9
6
Oscillator crystal or external clock input.
I
I
—
CMOS
Oscillator crystal input or external clock source input.
External clock source input. Always associated with pin
function OSC1. See related OSC2/CLKO pins.
CLKI
OSC2/CLKO
OSC2
10
7
Oscillator crystal or clock output.
O
O
—
—
Oscillator crystal output. Connects to crystal or
resonator in Crystal Oscillator mode.
In EC mode, OSC2 pin outputs CLKO which has 1/4 the
frequency of OSC1 and denotes the instruction cycle rate.
CLKO
Legend: TTL = TTL compatible input
ST = Schmitt Trigger input with CMOS levels
= Output
CMOS = CMOS compatible input or output
I
= Input
O
P
= Power
Note 1: Default assignment for CCP2 when configuration bit CCP2MX is set.
2: Alternate assignment for CCP2 when configuration bit CCP2MX is cleared.
DS39682C-page 12
Preliminary
© 2007 Microchip Technology Inc.
PIC18F45J10 FAMILY
TABLE 1-2:
PIC18F24J10/25J10 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number
Pin Buffer
Type Type
SPDIP,
SOIC, QFN
SSOP
Pin Name
Description
PORTA is a bidirectional I/O port.
RA0/AN0
RA0
2
3
4
27
28
1
I/O
I
TTL
Analog
Digital I/O.
Analog input 0.
AN0
RA1/AN1
RA1
I/O
I
TTL
Analog
Digital I/O.
Analog input 1.
AN1
RA2/AN2/VREF-/CVREF
RA2
I/O
TTL
Digital I/O.
AN2
VREF-
CVREF
I
I
O
Analog
Analog
Analog
Analog input 2.
A/D reference voltage (low) input.
Comparator reference voltage output.
RA3/AN3/VREF+
RA3
5
7
2
4
I/O
I
I
TTL
Analog
Analog
Digital I/O.
Analog input 3.
A/D reference voltage (high) input.
AN3
VREF+
RA5/AN4/SS1/C2OUT
RA5
AN4
SS1
C2OUT
I/O
I
I
TTL
Analog
TTL
Digital I/O.
Analog input 4.
SPI™ slave select input.
Comparator 2 output.
O
—
Legend: TTL = TTL compatible input
ST = Schmitt Trigger input with CMOS levels
= Output
CMOS = CMOS compatible input or output
I
= Input
O
P
= Power
Note 1: Default assignment for CCP2 when configuration bit CCP2MX is set.
2: Alternate assignment for CCP2 when configuration bit CCP2MX is cleared.
© 2007 Microchip Technology Inc.
Preliminary
DS39682C-page 13
PIC18F45J10 FAMILY
TABLE 1-2:
PIC18F24J10/25J10 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number
Pin Buffer
Type Type
SPDIP,
SOIC, QFN
SSOP
Pin Name
Description
PORTB is a bidirectional I/O port. PORTB can be software
programmed for internal weak pull-ups on all inputs.
RB0/INT0/FLT0/AN12
21
18
RB0
I/O
TTL
ST
ST
Digital I/O.
INT0
FLT0
AN12
I
I
I
External interrupt 0.
PWM Fault input for CCP1.
Analog input 12.
Analog
RB1/INT1/AN10
RB1
22
23
24
25
26
19
20
21
22
23
I/O
I
I
TTL
ST
Analog
Digital I/O.
External interrupt 1.
Analog input 10.
INT1
AN10
RB2/INT2/AN8
RB2
I/O
I
I
TTL
ST
Analog
Digital I/O.
External interrupt 2.
Analog input 8.
INT2
AN8
RB3/AN9/CCP2
RB3
I/O
I
I/O
TTL
Analog
ST
Digital I/O.
Analog input 9.
Capture 2 input/Compare 2 output/PWM 2 output.
AN9
CCP2(1)
RB4/KBI0/AN11
RB4
I/O
I
I
TTL
TTL
Analog
Digital I/O.
Interrupt-on-change pin.
Analog input 11.
KBI0
AN11
RB5/KBI1/T0CKI/
C1OUT
RB5
I/O
I
I
TTL
TTL
ST
Digital I/O.
Interrupt-on-change pin.
Timer0 external clock input.
Comparator 1 output.
KBI1
T0CKI
O
—
C1OUT
RB6/KBI2/PGC
RB6
27
28
24
25
I/O
I
I/O
TTL
TTL
ST
Digital I/O.
Interrupt-on-change pin.
In-Circuit Debugger and ICSP™ programming clock pin.
KBI2
PGC
RB7/KBI3/PGD
RB7
I/O
I
I/O
TTL
TTL
ST
Digital I/O.
Interrupt-on-change pin.
In-Circuit Debugger and ICSP programming data pin.
KBI3
PGD
Legend: TTL = TTL compatible input
ST = Schmitt Trigger input with CMOS levels
= Output
CMOS = CMOS compatible input or output
I
= Input
O
P
= Power
Note 1: Default assignment for CCP2 when configuration bit CCP2MX is set.
2: Alternate assignment for CCP2 when configuration bit CCP2MX is cleared.
DS39682C-page 14
Preliminary
© 2007 Microchip Technology Inc.
PIC18F45J10 FAMILY
TABLE 1-2:
PIC18F24J10/25J10 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number
Pin Buffer
Type Type
SPDIP,
SOIC, QFN
SSOP
Pin Name
Description
PORTC is a bidirectional I/O port.
RC0/T1OSO/T1CKI
RC0
11
8
I/O
O
I
ST
—
ST
Digital I/O.
Timer1 oscillator output.
Timer1 external clock input.
T1OSO
T1CKI
RC1/T1OSI/CCP2
RC1
12
9
I/O
I
I/O
ST
Analog
ST
Digital I/O.
Timer1 oscillator input.
Capture 2 input/Compare 2 output/PWM 2 output.
T1OSI
CCP2(2)
RC2/CCP1
RC2
13
14
10
11
I/O
I/O
ST
ST
Digital I/O.
CCP1
Capture 1 input/Compare 1 output/PWM 1 output.
RC3/SCK1/SCL1
RC3
I/O
I/O
I/O
ST
ST
ST
Digital I/O.
SCK1
SCL1
Synchronous serial clock input/output for SPI™ mode.
Synchronous serial clock input/output for I2C™ mode.
RC4/SDI1/SDA1
RC4
15
12
I/O
I
I/O
ST
ST
ST
Digital I/O.
SDI1
SDA1
SPI data in.
I2C data I/O.
RC5/SDO1
RC5
16
17
13
14
I/O
O
ST
—
Digital I/O.
SPI data out.
SDO1
RC6/TX/CK
RC6
I/O
O
I/O
ST
—
ST
Digital I/O.
TX
CK
EUSART asynchronous transmit.
EUSART synchronous clock (see related RX/DT).
RC7/RX/DT
RC7
18
15
I/O
I
I/O
ST
ST
ST
Digital I/O.
RX
DT
EUSART asynchronous receive.
EUSART synchronous data (see related TX/CK).
VSS
VDD
8, 19 5, 16
P
P
—
—
Ground reference for logic and I/O pins.
Positive supply for logic and I/O pins.
20
6
17
3
VDDCORE/VCAP
VDDCORE
VCAP
P
P
—
—
Positive supply for logic and I/O pins.
Ground reference for logic and I/O pins.
Legend: TTL = TTL compatible input
ST = Schmitt Trigger input with CMOS levels
= Output
CMOS = CMOS compatible input or output
I
= Input
O
P
= Power
Note 1: Default assignment for CCP2 when configuration bit CCP2MX is set.
2: Alternate assignment for CCP2 when configuration bit CCP2MX is cleared.
© 2007 Microchip Technology Inc.
Preliminary
DS39682C-page 15
PIC18F45J10 FAMILY
TABLE 1-3:
Pin Name
PIC18F44J10/45J10 PINOUT I/O DESCRIPTIONS
Pin Number
Pin Buffer
Type Type
Description
PDIP QFN TQFP
MCLR
MCLR
1
18
32
18
Master Clear (input) or programming voltage (input).
Master Clear (Reset) input. This pin is an active-low
Reset to the device.
I
ST
OSC1/CLKI
OSC1
13
30
Oscillator crystal or external clock input.
I
I
—
CMOS
Oscillator crystal input or external clock source input.
External clock source input. Always associated with
pin function OSC1. See related OSC2/CLKO pins.
CLKI
OSC2/CLKO
OSC2
14
33
31
Oscillator crystal or clock output.
O
O
—
—
Oscillator crystal output. Connects to crystal
or resonator in Crystal Oscillator mode.
In RC mode, OSC2 pin outputs CLKO which
has 1/4 the frequency of OSC1 and denotes
the instruction cycle rate.
CLKO
Legend: TTL = TTL compatible input
ST = Schmitt Trigger input with CMOS levels
= Output
CMOS = CMOS compatible input or output
I
= Input
O
P
= Power
Note 1: Default assignment for CCP2 when configuration bit CCP2MX is set.
2: Alternate assignment for CCP2 when configuration bit CCP2MX is cleared.
DS39682C-page 16
Preliminary
© 2007 Microchip Technology Inc.
PIC18F45J10 FAMILY
TABLE 1-3:
Pin Name
PIC18F44J10/45J10 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number
Pin Buffer
Type Type
Description
PDIP QFN TQFP
PORTA is a bidirectional I/O port.
RA0/AN0
RA0
2
3
4
19
20
21
19
20
21
I/O
I
TTL
Analog
Digital I/O.
Analog input 0.
AN0
RA1/AN1
RA1
I/O
I
TTL
Analog
Digital I/O.
Analog input 1.
AN1
RA2/AN2/VREF-/CVREF
RA2
I/O
TTL
Digital I/O.
AN2
VREF-
CVREF
I
I
O
Analog
Analog
Analog
Analog input 2.
A/D reference voltage (low) input.
Comparator reference voltage output.
RA3/AN3/VREF+
RA3
5
7
22
24
22
24
I/O
I
I
TTL
Analog
Analog
Digital I/O.
Analog input 3.
A/D reference voltage (high) input.
AN3
VREF+
RA5/AN4/SS1/C2OUT
RA5
AN4
SS1
C2OUT
I/O
I
I
TTL
Analog
TTL
Digital I/O.
Analog input 4.
SPI™ slave select input.
Comparator 2 output.
O
—
Legend: TTL = TTL compatible input
ST = Schmitt Trigger input with CMOS levels
= Output
CMOS = CMOS compatible input or output
I
= Input
O
P
= Power
Note 1: Default assignment for CCP2 when configuration bit CCP2MX is set.
2: Alternate assignment for CCP2 when configuration bit CCP2MX is cleared.
© 2007 Microchip Technology Inc.
Preliminary
DS39682C-page 17
PIC18F45J10 FAMILY
TABLE 1-3:
Pin Name
PIC18F44J10/45J10 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number
Pin Buffer
Type Type
Description
PDIP QFN TQFP
PORTB is a bidirectional I/O port. PORTB can be
software programmed for internal weak pull-ups on
all inputs.
RB0/INT0/FLT0/AN12
33
9
8
RB0
I/O
TTL
ST
ST
Digital I/O.
INT0
FLT0
AN12
I
I
I
External interrupt 0.
PWM Fault input for Enhanced CCP1.
Analog input 12.
Analog
RB1/INT1/AN10
RB1
34
35
36
37
38
39
10
11
12
14
15
16
9
I/O
I
I
TTL
ST
Analog
Digital I/O.
External interrupt 1.
Analog input 10.
INT1
AN10
RB2/INT2/AN8
RB2
10
11
14
15
16
I/O
I
I
TTL
ST
Analog
Digital I/O.
External interrupt 2.
Analog input 8.
INT2
AN8
RB3/AN9/CCP2
RB3
I/O
I
I/O
TTL
Analog
ST
Digital I/O.
Analog input 9.
Capture 2 input/Compare 2 output/PWM 2 output.
AN9
CCP2(1)
RB4/KBI0/AN11
RB4
I/O
I
I
TTL
TTL
Analog
Digital I/O.
Interrupt-on-change pin.
Analog input 11.
KBI0
AN11
RB5/KBI1/C1OUT
RB5
I/O
I
O
TTL
TTL
—
Digital I/O.
Interrupt-on-change pin.
Comparator 1 output.
KBI1
C1OUT
RB6/KBI2/PGC
RB6
I/O
I
I/O
TTL
TTL
ST
Digital I/O.
Interrupt-on-change pin.
In-Circuit Debugger and ICSP™ programming
clock pin.
KBI2
PGC
RB7/KBI3/PGD
RB7
40
17
17
I/O
I
I/O
TTL
TTL
ST
Digital I/O.
KBI3
PGD
Interrupt-on-change pin.
In-Circuit Debugger and ICSP programming
data pin.
Legend: TTL = TTL compatible input
ST = Schmitt Trigger input with CMOS levels
= Output
CMOS = CMOS compatible input or output
I
= Input
O
P
= Power
Note 1: Default assignment for CCP2 when configuration bit CCP2MX is set.
2: Alternate assignment for CCP2 when configuration bit CCP2MX is cleared.
DS39682C-page 18
Preliminary
© 2007 Microchip Technology Inc.
PIC18F45J10 FAMILY
TABLE 1-3:
Pin Name
PIC18F44J10/45J10 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number
Pin Buffer
Type Type
Description
PDIP QFN TQFP
PORTC is a bidirectional I/O port.
RC0/T1OSO/T1CKI
RC0
15
16
17
18
34
35
36
37
32
35
36
37
I/O
O
I
ST
—
ST
Digital I/O.
Timer1 oscillator output.
Timer1 external clock input.
T1OSO
T1CKI
RC1/T1OSI/CCP2
RC1
I/O
I
I/O
ST
CMOS
ST
Digital I/O.
Timer1 oscillator input.
Capture 2 input/Compare 2 output/PWM 2 output.
T1OSI
CCP2(2)
RC2/CCP1/P1A
RC2
I/O
I/O
O
ST
ST
—
Digital I/O.
CCP1
P1A
Capture 1 input/Compare 1 output/PWM 1 output.
Enhanced CCP1 output.
RC3/SCK1/SCL1
RC3
I/O
I/O
ST
ST
Digital I/O.
Synchronous serial clock input/output for
SPI™ mode.
SCK1
SCL1
I/O
ST
Synchronous serial clock input/output for
I2C™ mode.
RC4/SDI1/SDA1
RC4
23
42
42
I/O
I
I/O
ST
ST
ST
Digital I/O.
SPI data in.
I2C data I/O.
SDI1
SDA1
RC5/SDO1
RC5
24
25
43
44
43
44
I/O
O
ST
—
Digital I/O.
SPI data out.
SDO1
RC6/TX/CK
RC6
I/O
O
I/O
ST
—
ST
Digital I/O.
TX
CK
EUSART asynchronous transmit.
EUSART synchronous clock (see related RX/DT).
RC7/RX/DT
RC7
26
1
1
I/O
I
I/O
ST
ST
ST
Digital I/O.
RX
DT
EUSART asynchronous receive.
EUSART synchronous data (see related TX/CK).
Legend: TTL = TTL compatible input
ST = Schmitt Trigger input with CMOS levels
= Output
CMOS = CMOS compatible input or output
I
= Input
O
P
= Power
Note 1: Default assignment for CCP2 when configuration bit CCP2MX is set.
2: Alternate assignment for CCP2 when configuration bit CCP2MX is cleared.
© 2007 Microchip Technology Inc.
Preliminary
DS39682C-page 19
PIC18F45J10 FAMILY
TABLE 1-3:
Pin Name
PIC18F44J10/45J10 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number
Pin Buffer
Type Type
Description
PDIP QFN TQFP
PORTD is a bidirectional I/O port or a Parallel Slave
Port (PSP) for interfacing to a microprocessor port.
These pins have TTL input buffers when PSP module
is enabled.
RD0/PSP0/SCK2/
SCL2
19
38
38
RD0
PSP0
SCK2
I/O
I/O
I/O
ST
TTL
ST
Digital I/O.
Parallel Slave Port data.
Synchronous serial clock input/output for
SPI™ mode.
SCL2
I/O
ST
Synchronous serial clock input/output for
I
2C™ mode.
RD1/PSP1/SDI2/SDA2 20
39
39
RD1
I/O
I/O
I
ST
TTL
ST
Digital I/O.
PSP1
SDI2
SDA2
Parallel Slave Port data.
SPI data in.
I/O
ST
I2C data I/O.
RD2/PSP2/SDO2
RD2
21
22
40
41
40
41
I/O
I/O
O
ST
TTL
—
Digital I/O.
Parallel Slave Port data.
SPI data out.
PSP2
SDO2
RD3/PSP3/SS2
RD3
I/O
I/O
I
ST
TTL
TTL
Digital I/O.
Parallel Slave Port data.
SPI slave select input.
PSP3
SS2
RD4/PSP4
RD4
27
28
2
3
2
3
I/O
I/O
ST
TTL
Digital I/O.
Parallel Slave Port data.
PSP4
RD5/PSP5/P1B
RD5
I/O
I/O
O
ST
TTL
—
Digital I/O.
Parallel Slave Port data.
Enhanced CCP1 output.
PSP5
P1B
RD6/PSP6/P1C
RD6
29
30
4
5
4
5
I/O
I/O
O
ST
TTL
—
Digital I/O.
Parallel Slave Port data.
Enhanced CCP1 output.
PSP6
P1C
RD7/PSP7/P1D
RD7
I/O
I/O
O
ST
TTL
—
Digital I/O.
Parallel Slave Port data.
Enhanced CCP1 output.
PSP7
P1D
Legend: TTL = TTL compatible input
ST = Schmitt Trigger input with CMOS levels
= Output
CMOS = CMOS compatible input or output
I
= Input
O
P
= Power
Note 1: Default assignment for CCP2 when configuration bit CCP2MX is set.
2: Alternate assignment for CCP2 when configuration bit CCP2MX is cleared.
DS39682C-page 20
Preliminary
© 2007 Microchip Technology Inc.
PIC18F45J10 FAMILY
TABLE 1-3:
Pin Name
PIC18F44J10/45J10 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number
Pin Buffer
Type Type
Description
PDIP QFN TQFP
PORTE is a bidirectional I/O port.
RE0/RD/AN5
RE0
8
9
25
26
27
25
26
27
I/O
I
ST
TTL
Digital I/O.
RD
Read control for Parallel Slave Port
(see also WR and CS pins).
Analog input 5.
AN5
I
Analog
RE1/WR/AN6
RE1
I/O
I
ST
TTL
Digital I/O.
WR
Write control for Parallel Slave Port
(see CS and RD pins).
Analog input 6.
AN6
I
Analog
RE2/CS/AN7
RE2
10
I/O
I
ST
TTL
Digital I/O.
CS
Chip Select control for Parallel Slave Port
(see related RD and WR pins).
Analog input 7.
AN7
VSS
I
Analog
—
12, 31 6, 30, 6, 29
31
P
Ground reference for logic and I/O pins.
VDD
11, 32 7, 8, 7, 28
28, 29
P
—
Positive supply for logic and I/O pins.
VDDCORE/VCAP
VDDCORE
VCAP
6
23
23
P
P
—
—
Positive supply for logic and I/O pins.
Ground reference for logic and I/O pins.
NC
—
13 12,13,
33, 34
—
—
No connect.
Legend: TTL = TTL compatible input
ST = Schmitt Trigger input with CMOS levels
= Output
CMOS = CMOS compatible input or output
I
= Input
O
P
= Power
Note 1: Default assignment for CCP2 when configuration bit CCP2MX is set.
2: Alternate assignment for CCP2 when configuration bit CCP2MX is cleared.
© 2007 Microchip Technology Inc.
Preliminary
DS39682C-page 21
PIC18F45J10 FAMILY
NOTES:
DS39682C-page 22
Preliminary
© 2007 Microchip Technology Inc.
PIC18F45J10 FAMILY
FIGURE 2-1:
CRYSTAL/CERAMIC
RESONATOROPERATION
(HS OR HSPLL
2.0
2.1
OSCILLATOR
CONFIGURATIONS
CONFIGURATION)
Oscillator Types
(1)
C1
The PIC18F45J10 family of devices can be operated in
five different oscillator modes:
OSC1
To
Internal
Logic
1. HS
High-Speed Crystal/Resonator
(3)
RF
XTAL
2. HSPLL High-Speed Crystal/Resonator
with Software PLL Control
Sleep
OSC2
3. EC
External Clock with FOSC/4 Output
(1)
(2)
RS
PIC18F45J10
C2
4. ECPLL External Clock with Software PLL
Control
Note 1: See Table 2-1 and Table 2-2 for initial values of
5. INTRC Internal 31 kHz Oscillator
C1 and C2.
Four of these are selected by the user by programming
the FOSC2:FOSC0 configuration bits. The fifth mode
(INTRC) may be invoked under software control; it can
also be configured as the default mode on device
Resets.
2: A series resistor (RS) may be required for AT
strip cut crystals.
3: RF varies with the oscillator mode chosen.
TABLE 2-1:
CAPACITOR SELECTION FOR
CERAMIC RESONATORS
2.2
Crystal Oscillator/Ceramic
Resonators (HS Modes)
Typical Capacitor Values Used:
In HS or HSPLL Oscillator modes, a crystal or ceramic
resonator is connected to the OSC1 and OSC2 pins to
establish oscillation. Figure 2-1 shows the pin
connections.
Mode
Freq.
OSC1
OSC2
HS
8.0 MHz
16.0 MHz
27 pF
22 pF
27 pF
22 pF
The oscillator design requires the use of a parallel cut
crystal.
Capacitor values are for design guidance only.
These capacitors were tested with the resonators
listed below for basic start-up and operation. These
values are not optimized.
Note:
Use of a series cut crystal may give a fre-
quency out of the crystal manufacturer’s
specifications.
Different capacitor values may be required to produce
acceptable oscillator operation. The user should test
the performance of the oscillator over the expected
VDD and temperature range for the application.
See the notes following Table 2-2 for additional
information.
Resonators Used:
4.0 MHz
8.0 MHz
16.0 MHz
© 2007 Microchip Technology Inc.
Preliminary
DS39682C-page 23
PIC18F45J10 FAMILY
TABLE 2-2:
CAPACITOR SELECTION FOR
CRYSTAL OSCILLATOR
2.3
External Clock Input (EC Modes)
The EC and ECPLL Oscillator modes require an exter-
nal clock source to be connected to the OSC1 pin.
There is no oscillator start-up time required after a
Power-on Reset or after an exit from Sleep mode.
Typical Capacitor Values
Crystal
Freq.
Tested:
Osc Type
C1
C2
In the EC Oscillator mode, the oscillator frequency
divided by 4 is available on the OSC2 pin. This signal
may be used for test purposes or to synchronize other
logic. Figure 2-2 shows the pin connections for the EC
Oscillator mode.
HS
4 MHz
8 MHz
20 MHz
27 pF
22 pF
15 pF
27 pF
22 pF
15 pF
Capacitor values are for design guidance only.
These capacitors were tested with the crystals listed
below for basic start-up and operation. These values
are not optimized.
FIGURE 2-2:
EXTERNAL CLOCK
INPUT OPERATION
(EC CONFIGURATION)
Different capacitor values may be required to produce
acceptable oscillator operation. The user should test
the performance of the oscillator over the expected
VDD and temperature range for the application.
OSC1/CLKI
Clock from
Ext. System
PIC18F45J10
OSC2/CLKO
See the notes following this table for additional
information.
FOSC/4
Crystals Used:
4 MHz
8 MHz
20 MHz
An external clock source may also be connected to the
OSC1 pin in the HS mode, as shown in Figure 2-3. In
this configuration, the divide-by-4 output on OSC2 is
not available.
FIGURE 2-3:
EXTERNAL CLOCK INPUT
OPERATION (HS OSC
CONFIGURATION)
Note 1: Higher capacitance increases the stability
of oscillator but also increases the
start-up time.
2: Since each resonator/crystal has its own
characteristics, the user should consult
the resonator/crystal manufacturer for
OSC1
Clock from
appropriate
components.
values
of
external
Ext. System
PIC18F45J10
(HS Mode)
OSC2
Open
3: Rs may be required to avoid overdriving
crystals with low drive level specification.
4: Always verify oscillator performance over
the VDD and temperature range that is
expected for the application.
DS39682C-page 24
Preliminary
© 2007 Microchip Technology Inc.
PIC18F45J10 FAMILY
FIGURE 2-4:
PLL BLOCK DIAGRAM
2.4
PLL Frequency Multiplier
A Phase Locked Loop (PLL) circuit is provided as an
option for users who want to use a lower frequency
oscillator circuit, or to clock the device up to its highest
rated frequency from a crystal oscillator. This may be
useful for customers who are concerned with EMI due
to high-frequency crystals, or users who require higher
clock speeds from an internal oscillator. For these
reasons, the HSPLL and ECPLL modes are available.
HSPLL or ECPLL (CONFIG2L)
PLL Enable (OSCTUNE)
OSC2
Phase
Comparator
FIN
HS or EC
OSC1 Mode
FOUT
The HSPLL and ECPLL modes provide the ability to
selectively run the device at 4 times the external oscil-
lating source to produce frequencies up to 40 MHz.
The PLL is enabled by setting the PLLEN bit in the
OSCTUNE register (Register 2-1).
Loop
Filter
÷4
VCO
SYSCLK
REGISTER 2-1:
OSCTUNE: PLL CONTROL REGISTER
U-0
—
R/W-0(1)
PLLEN(1)
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
bit 7
bit 0
bit 7
bit 6
Unimplemented: Read as ‘0’
PLLEN: Frequency Multiplier PLL Enable bit(1)
1= PLL enabled
0= PLL disabled
Note 1: Available only for ECPLL and HSPLL oscillator configurations; otherwise, this bit is
unavailable and read as ‘0’.
bit 5-0
Unimplemented: Read as ‘0’
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
© 2007 Microchip Technology Inc.
Preliminary
DS39682C-page 25
PIC18F45J10 FAMILY
The primary oscillators include the External Crystal
and Resonator modes and the External Clock modes.
The particular mode is defined by the FOSC2:FOSC0
configuration bits. The details of these modes are
covered earlier in this chapter.
2.5
Internal Oscillator Block
The PIC18F45J10 family of devices includes an inter-
nal oscillator source (INTRC) which provides a nominal
31 kHz output. The INTRC is enabled on device
power-up and clocks the device during its configuration
cycle until it enters operating mode. INTRC is also
enabled if it is selected as the device clock source or if
any of the following are enabled:
The secondary oscillators are those external sources
not connected to the OSC1 or OSC2 pins. These
sources may continue to operate even after the
controller is placed in a power-managed mode.
• Fail-Safe Clock Monitor
• Watchdog Timer
PIC18F45J10 family devices offer the Timer1 oscillator
as a secondary oscillator. This oscillator, in all
power-managed modes, is often the time base for
functions such as a real-time clock.
• Two-Speed Start-up
These features are discussed in greater detail in
Section 20.0 “Special Features of the CPU”.
Most often, a 32.768 kHz watch crystal is connected
between the RC0/T1OSO/T13CKI and RC1/T1OSI
pins. Loading capacitors are also connected from each
pin to ground.
The INTRC can also be optionally configured as the
default clock source on device start-up by setting the
FOSC2 configuration bit. This is discussed in
Section 2.6.1 “Oscillator Control Register”.
The Timer1 oscillator is discussed in greater detail in
Section 11.3 “Timer1 Oscillator”.
2.6
Clock Sources and
Oscillator Switching
In addition to being a primary clock source, the internal
oscillator is available as a power-managed mode
clock source. The INTRC source is also used as the
clock source for several special features, such as the
WDT and Fail-Safe Clock Monitor.
The PIC18F45J10 family includes a feature that allows
the device clock source to be switched from the main
oscillator to an alternate clock source. PIC18F45J10
family devices offer two alternate clock sources. When
an alternate clock source is enabled, the various
power-managed operating modes are available.
The clock sources for the PIC18F45J10 family devices
are shown in Figure 2-5. See Section 20.0 “Special
Features of the CPU” for Configuration register
details.
Essentially, there are three clock sources for these
devices:
• Primary oscillators
• Secondary oscillators
• Internal oscillator
FIGURE 2-5:
PIC18F45J10 FAMILY CLOCK DIAGRAM
PIC18F45J10 Family
Primary Oscillator
HS, EC
OSC2
Sleep
HSPLL, ECPLL
4 x PLL
OSC1
Peripherals
Secondary Oscillator
T1OSC
T1OSO
T1OSCEN
Enable
Oscillator
T1OSI
Internal Oscillator
INTRC
Source
CPU
IDLEN
Clock
Control
FOSC2:FOSC0 OSCCON<1:0>
Clock Source Option
for other Modules
WDT, PWRT, FSCM
and Two-Speed Start-up
DS39682C-page 26
Preliminary
© 2007 Microchip Technology Inc.
PIC18F45J10 FAMILY
2.6.1
OSCILLATOR CONTROL REGISTER
2.6.1.1
System Clock Selection and the
FOSC2 Configuration Bit
The OSCCON register (Register 2-2) controls several
aspects of the device clock’s operation, both in full
power operation and in power-managed modes.
The SCS bits are cleared on all forms of Reset. In the
device’s default configuration, this means the primary
oscillator defined by FOSC1:FOSC0 (that is, one of the
HC or EC modes) is used as the primary clock source
on device Resets.
The System Clock Select bits, SCS1:SCS0, select the
clock source. The available clock sources are the
primary clock (defined by the FOSC2:FOSC0 configu-
ration bits), the secondary clock (Timer1 oscillator) and
the internal oscillator. The clock source changes after
one or more of the bits are written to, following a brief
clock transition interval.
The default clock configuration on Reset can be changed
with the FOSC2 configuration bit. The effect of this bit is
to set the clock source selected when SCS1:SCS0 = 00.
When FOSC2 = 1 (default), the oscillator source
defined by FOSC1:FOSC0 is selected whenever
SCS1:SCS0 = 00. When FOSC2 = 0, the INTRC oscilla-
tor is selected whenever SCS1:SCS2 = 00. Because the
SCS bits are cleared on Reset, the FOSC2 setting also
changes the default oscillator mode on Reset.
The OSTS (OSCCON<3>) and T1RUN (T1CON<6>)
bits indicate which clock source is currently providing
the device clock. The OSTS bit indicates that the
Oscillator Start-up Timer (OST) has timed out and the
primary clock is providing the device clock in primary
clock modes. The T1RUN bit indicates when the
Timer1 oscillator is providing the device clock in sec-
ondary clock modes. In power-managed modes, only
one of these bits will be set at any time. If neither of
these bits are set, the INTRC is providing the clock, or
the internal oscillator has just started and is not yet
stable.
Regardless of the setting of FOSC2, INTRC will always
be enabled on device power-up. It will serve as the
clock source until the device has loaded its configura-
tion values from memory. It is at this point that the
FOSC configuration bits are read and the oscillator
selection of operational mode is made.
Note that either the primary clock or the internal
oscillator will have two bit setting options, at any given
time, depending on the setting of FOSC2.
The IDLEN bit determines if the device goes into Sleep
mode or one of the Idle modes when the SLEEP
instruction is executed.
2.6.2
OSCILLATOR TRANSITIONS
The use of the flag and control bits in the OSCCON
register is discussed in more detail in Section 3.0
“Power-Managed Modes”.
PIC18F45J10 family devices contain circuitry to
prevent clock “glitches” when switching between clock
sources. A short pause in the device clock occurs dur-
ing the clock switch. The length of this pause is the sum
of two cycles of the old clock source and three to four
cycles of the new clock source. This formula assumes
that the new clock source is stable.
Note 1: The Timer1 oscillator must be enabled to
select the secondary clock source. The
Timer1 oscillator is enabled by setting the
T1OSCEN bit in the Timer1 Control regis-
ter (T1CON<3>). If the Timer1 oscillator is
not enabled, then any attempt to select a
secondary clock source when executing a
SLEEPinstruction will be ignored.
Clock transitions are discussed in greater detail in
Section 3.1.2 “Entering Power-Managed Modes”.
2: It is recommended that the Timer1
oscillator be operating and stable before
executing the SLEEPinstruction or a very
long delay may occur while the Timer1
oscillator starts.
© 2007 Microchip Technology Inc.
Preliminary
DS39682C-page 27
PIC18F45J10 FAMILY
REGISTER 2-2:
OSCCON: OSCILLATOR CONTROL REGISTER
R/W-0
IDLEN
U-0
—
U-0
—
U-0
—
R-q(1)
U-0
—
R/W-0
SCS1
R/W-0
SCS0
OSTS
bit 7
bit 0
bit 7
IDLEN: Idle Enable bit
1= Device enters Idle mode on SLEEPinstruction
0= Device enters Sleep mode on SLEEPinstruction
bit 6-4 Unimplemented: Read as ‘0’
bit 3
OSTS: Oscillator Start-up Time-out Status bit(1)
1= Oscillator Start-up Timer time-out has expired; primary oscillator is running
0= Oscillator Start-up Timer time-out is running; primary oscillator is not ready
Note 1: The Reset value is ‘0’ when HS mode and Two-Speed Start-up are both enabled;
otherwise, it is ‘1’.
bit 2
Unimplemented: Read as ‘0’
bit 1-0 SCS1:SCS0: System Clock Select bits
11= Internal oscillator
10= Primary oscillator
01= Timer1 oscillator
When FOSC2 = 1:
00= Primary oscillator
When FOSC2 = 0:
00= Internal oscillator
Legend:
U = Unimplemented, read as ‘0’
‘q’ = Value determined by configuration
‘0’ = Bit is cleared W = Writable bit
-n = Value at POR
R = Readable bit
If the Sleep mode is selected, all clock sources are
stopped. Since all the transistor switching currents
have been stopped, Sleep mode achieves the lowest
current consumption of the device (only leakage
currents).
2.7
Effects of Power-Managed Modes
on the Various Clock Sources
When PRI_IDLE mode is selected, the designated pri-
mary oscillator continues to run without interruption.
For all other power-managed modes, the oscillator
using the OSC1 pin is disabled. The OSC1 pin (and
OSC2 pin if used by the oscillator) will stop oscillating.
Enabling any on-chip feature that will operate during
Sleep will increase the current consumed during Sleep.
The INTRC is required to support WDT operation. The
Timer1 oscillator may be operating to support a
real-time clock. Other features may be operating that
do not require a device clock source (i.e., MSSP slave,
PSP, INTn pins and others). Peripherals that may add
significant current consumption are listed in
Section 23.2 “DC Characteristics: Power-Down and
Supply Current”.
In Secondary Clock modes (SEC_RUN and
SEC_IDLE), the Timer1 oscillator is operating and
providing the device clock. The Timer1 oscillator may
also run in all power-managed modes if required to
clock Timer1 or Timer3.
In RC_RUN and RC_IDLE modes, the internal oscilla-
tor provides the device clock source. The 31 kHz
INTRC output can be used directly to provide the clock
and may be enabled to support various special
features, regardless of the power-managed mode (see
Section 20.2 “Watchdog Timer (WDT)” through
Section 20.5 “Fail-Safe Clock Monitor” for more
information on WDT, Fail-Safe Clock Monitor and
Two-Speed Start-up).
DS39682C-page 28
Preliminary
© 2007 Microchip Technology Inc.
PIC18F45J10 FAMILY
The second timer is the Oscillator Start-up Timer
(OST), intended to keep the chip in Reset until the
crystal oscillator is stable (HS modes). The OST does
this by counting 1024 oscillator cycles before allowing
the oscillator to clock the device.
2.8
Power-up Delays
Power-up delays are controlled by two timers, so that
no external Reset circuitry is required for most applica-
tions. The delays ensure that the device is kept in
Reset until the device power supply is stable under nor-
mal circumstances and the primary clock is operating
and stable. For additional information on power-up
delays, see Section 4.5 “Power-up Timer (PWRT)”.
There is a delay of interval TCSD (parameter 38,
Table 23-10), following POR, while the controller
becomes ready to execute instructions.
The first timer is the Power-up Timer (PWRT), which
provides a fixed delay on power-up (parameter 33,
Table 23-10). It is always enabled.
TABLE 2-3:
OSC1 AND OSC2 PIN STATES IN SLEEP MODE
Oscillator Mode
OSC1 Pin
OSC2 Pin
EC, ECPLL
HS, HSPLL
Floating, pulled by external clock
At logic low (clock/4 output)
Feedback inverter disabled at quiescent
voltage level
Feedback inverter disabled at quiescent
voltage level
Note:
See Table 4-2 in Section 4.0 “Reset” for time-outs due to Sleep and MCLR Reset.
© 2007 Microchip Technology Inc.
Preliminary
DS39682C-page 29
PIC18F45J10 FAMILY
NOTES:
DS39682C-page 30
Preliminary
© 2007 Microchip Technology Inc.
PIC18F45J10 FAMILY
3.1.1
CLOCK SOURCES
3.0
POWER-MANAGED MODES
The SCS1:SCS0 bits allow the selection of one of three
clock sources for power-managed modes. They are:
The PIC18F45J10 family devices provide the ability to
manage power consumption by simply managing clock-
ing to the CPU and the peripherals. In general, a lower
clock frequency and a reduction in the number of circuits
being clocked constitutes lower consumed power. For
the sake of managing power in an application, there are
three primary modes of operation:
• the primary clock, as defined by the
FOSC1:FOSC0 configuration bits
• the secondary clock (Timer1 oscillator)
• the internal oscillator
3.1.2
ENTERING POWER-MANAGED
MODES
• Run mode
• Idle mode
• Sleep mode
Switching from one power-managed mode to another
begins by loading the OSCCON register. The
SCS1:SCS0 bits select the clock source and determine
which Run or Idle mode is to be used. Changing these
bits causes an immediate switch to the new clock
source, assuming that it is running. The switch may
also be subject to clock transition delays. These are
discussed in Section 3.1.3 “Clock Transitions and
Status Indicators” and subsequent sections.
These modes define which portions of the device are
clocked and at what speed. The Run and Idle modes
may use any of the three available clock sources
(primary, secondary or internal oscillator block); the
Sleep mode does not use a clock source.
The power-managed modes include several
power-saving features offered on previous PIC®
devices. One is the clock switching feature, offered in
other PIC18 devices, allowing the controller to use the
Timer1 oscillator in place of the primary oscillator. Also
included is the Sleep mode, offered by all PIC devices,
where all device clocks are stopped.
Entry to the power-managed Idle or Sleep modes is
triggered by the execution of a SLEEPinstruction. The
actual mode that results depends on the status of the
IDLEN bit.
Depending on the current mode and the mode being
switched to, a change to a power-managed mode does
not always require setting all of these bits. Many
transitions may be done by changing the oscillator
select bits, or changing the IDLEN bit, prior to issuing a
SLEEP instruction. If the IDLEN bit is already
configured correctly, it may only be necessary to
perform a SLEEP instruction to switch to the desired
mode.
3.1
Selecting Power-Managed Modes
Selecting
a power-managed mode requires two
decisions: if the CPU is to be clocked or not and which
clock source is to be used. The IDLEN bit
(OSCCON<7>) controls CPU clocking, while the
SCS1:SCS0 bits (OSCCON<1:0>) select the clock
source. The individual modes, bit settings, clock
sources and affected modules are summarized in
Table 3-1.
TABLE 3-1:
Mode
POWER-MANAGED MODES
OSCCON bits Module Clocking
IDLEN<7>(1) SCS1:SCS0<1:0> CPU Peripherals
Available Clock and Oscillator Source
Sleep
0
N/A
Off
Clocked Clocked Primary – HS, EC;
this is the normal full power execution mode
Off
None – All clocks are disabled
PRI_RUN
N/A
10
SEC_RUN
RC_RUN
PRI_IDLE
SEC_IDLE
RC_IDLE
N/A
N/A
1
01
11
10
01
11
Clocked Clocked Secondary – Timer1 Oscillator
Clocked Clocked Internal Oscillator
Off
Off
Off
Clocked Primary – HS, EC
1
Clocked Secondary – Timer1 Oscillator
Clocked Internal Oscillator
1
Note 1: IDLEN reflects its value when the SLEEPinstruction is executed.
© 2007 Microchip Technology Inc.
Preliminary
DS39682C-page 31
PIC18F45J10 FAMILY
3.1.3
CLOCK TRANSITIONS AND STATUS
INDICATORS
3.2.2
SEC_RUN MODE
The SEC_RUN mode is the compatible mode to the
“clock switching” feature offered in other PIC18
devices. In this mode, the CPU and peripherals are
clocked from the Timer1 oscillator. This gives users the
option of lower power consumption while still using a
high-accuracy clock source.
The length of the transition between clock sources is
the sum of two cycles of the old clock source and three
to four cycles of the new clock source. This formula
assumes that the new clock source is stable.
Two bits indicate the current clock source and its
SEC_RUN mode is entered by setting the SCS1:SCS0
bits to ‘01’. The device clock source is switched to the
Timer1 oscillator (see Figure 3-1), the primary oscilla-
tor is shut down, the T1RUN bit (T1CON<6>) is set and
the OSTS bit is cleared.
status:
OSTS
(OSCCON<3>)
and
T1RUN
(T1CON<6>). In general, only one of these bits will be
set while in a given power-managed mode. When the
OSTS bit is set, the primary clock is providing the
device clock. When the T1RUN bit is set, the Timer1
oscillator is providing the clock. If neither of these bits
is set, INTRC is clocking the device.
Note:
The Timer1 oscillator should already be
running prior to entering SEC_RUN mode.
If the T1OSCEN bit is not set when the
SCS1:SCS0 bits are set to ‘01’, entry to
SEC_RUN mode will not occur. If the
Timer1 oscillator is enabled, but not yet
running, device clocks will be delayed until
the oscillator has started. In such situa-
tions, initial oscillator operation is far from
stable and unpredictable operation may
result.
Note:
Executing a SLEEP instruction does not
necessarily place the device into Sleep
mode. It acts as the trigger to place the
controller into either the Sleep mode or
one of the Idle modes, depending on the
setting of the IDLEN bit.
3.1.4
MULTIPLE SLEEP COMMANDS
The power-managed mode that is invoked with the
SLEEP instruction is determined by the setting of the
IDLEN bit at the time the instruction is executed. If
another SLEEP instruction is executed, the device will
enter the power-managed mode specified by IDLEN at
that time. If IDLEN has changed, the device will enter the
new power-managed mode specified by the new setting.
On transitions from SEC_RUN mode to PRI_RUN
mode, the peripherals and CPU continue to be clocked
from the Timer1 oscillator while the primary clock is
started. When the primary clock becomes ready, a
clock switch back to the primary clock occurs (see
Figure 3-2). When the clock switch is complete, the
T1RUN bit is cleared, the OSTS bit is set and the
primary clock is providing the clock. The IDLEN and
SCS bits are not affected by the wake-up; the Timer1
oscillator continues to run.
3.2
Run Modes
In the Run modes, clocks to both the core and
peripherals are active. The difference between these
modes is the clock source.
3.2.1
PRI_RUN MODE
The PRI_RUN mode is the normal, full power execution
mode of the microcontroller. This is also the default
mode upon a device Reset unless Two-Speed Start-up
is enabled (see Section 20.4 “Two-Speed Start-up”
for details). In this mode, the OSTS bit is set. (see
Section 2.6.1 “Oscillator Control Register”).
FIGURE 3-1:
TRANSITION TIMING FOR ENTRY TO SEC_RUN MODE
Q1 Q2 Q3 Q4 Q1
Q2
Q3
Q4
Q1
Q2
Q3
1
2
3
n-1
n
T1OSI
OSC1
Clock Transition
CPU
Clock
Peripheral
Clock
Program
Counter
PC
PC + 2
PC + 4
DS39682C-page 32
Preliminary
© 2007 Microchip Technology Inc.
PIC18F45J10 FAMILY
On transitions from RC_RUN mode to PRI_RUN mode,
the device continues to be clocked from the INTRC
while the primary clock is started. When the primary
clock becomes ready, a clock switch to the primary
clock occurs (see Figure 3-3). When the clock switch is
complete, the OSTS bit is set and the primary clock is
providing the device clock. The IDLEN and SCS bits
are not affected by the switch. The INTRC source will
continue to run if either the WDT or the Fail-Safe Clock
Monitor is enabled.
3.2.3
RC_RUN MODE
In RC_RUN mode, the CPU and peripherals are
clocked from the internal oscillator; the primary clock is
shut down. This mode provides the best power conser-
vation of all the Run modes, while still executing code.
It works well for user applications which are not highly
timing-sensitive or do not require high-speed clocks at
all times.
This mode is entered by setting SCS to ‘11’. When the
clock source is switched to the INTRC (see Figure 3-2),
the primary oscillator is shut down and the OSTS bit is
cleared.
FIGURE 3-2:
TRANSITION TIMING TO RC_RUN MODE
Q1 Q2 Q3 Q4 Q1
Q2
Q3
Q4
Q1
Q2
Q3
1
2
3
n-1
n
INTRC
OSC1
Clock Transition
CPU
Clock
Peripheral
Clock
Program
Counter
PC
PC + 2
PC + 4
FIGURE 3-3:
TRANSITION TIMING FROM RC_RUN MODE TO PRI_RUN MODE
Q3
Q4
Q1
Q2 Q3 Q4 Q1 Q2 Q3
Q1
Q2
INTRC
OSC1
(1)
TOST
CPU Clock
Peripheral
Clock
Program
Counter
PC + 2
PC + 4
PC
SCS1:SCS0 bits Changed
OSTS bit Set
Note 1: TOST = 1024 TOSC. These intervals are not shown to scale.
© 2007 Microchip Technology Inc.
Preliminary
DS39682C-page 33
PIC18F45J10 FAMILY
3.3
Sleep Mode
3.4
Idle Modes
The power-managed Sleep mode is identical to the leg-
acy Sleep mode offered in all other PIC devices. It is
entered by clearing the IDLEN bit (the default state on
device Reset) and executing the SLEEP instruction.
This shuts down the selected oscillator (Figure 3-4). All
clock source status bits are cleared.
The Idle modes allow the controller’s CPU to be
selectively shut down while the peripherals continue to
operate. Selecting a particular Idle mode allows users
to further manage power consumption.
If the IDLEN bit is set to a ‘1’ when a SLEEPinstruction is
executed, the peripherals will be clocked from the clock
source selected using the SCS1:SCS0 bits; however, the
CPU will not be clocked. The clock source status bits are
not affected. Setting IDLEN and executing a SLEEP
instruction provides a quick method of switching from a
given Run mode to its corresponding Idle mode.
Entering the Sleep mode from any other mode does not
require a clock switch. This is because no clocks are
needed once the controller has entered Sleep. If the
WDT is selected, the INTRC source will continue to
operate. If the Timer1 oscillator is enabled, it will also
continue to run.
If the WDT is selected, the INTRC source will continue
to operate. If the Timer1 oscillator is enabled, it will also
continue to run.
When a wake event occurs in Sleep mode (by interrupt,
Reset or WDT time-out), the device will not be clocked
until the clock source selected by the SCS1:SCS0 bits
becomes ready (see Figure 3-5), or it will be clocked
from the internal oscillator if either the Two-Speed
Start-up or the Fail-Safe Clock Monitor are enabled
(see Section 20.0 “Special Features of the CPU”). In
either case, the OSTS bit is set when the primary clock
is providing the device clocks. The IDLEN and SCS bits
are not affected by the wake-up.
Since the CPU is not executing instructions, the only
exits from any of the Idle modes are by interrupt, WDT
time-out or a Reset. When a wake event occurs, CPU
execution is delayed by an interval of TCSD
(parameter 38, Table 23-10) while it becomes ready to
execute code. When the CPU begins executing code,
it resumes with the same clock source for the current
Idle mode. For example, when waking from RC_IDLE
mode, the internal oscillator block will clock the CPU
and peripherals (in other words, RC_RUN mode). The
IDLEN and SCS bits are not affected by the wake-up.
While in any Idle mode or the Sleep mode, a WDT
time-out will result in a WDT wake-up to the Run mode
currently specified by the SCS1:SCS0 bits.
FIGURE 3-4:
TRANSITION TIMING FOR ENTRY TO SLEEP MODE
Q1 Q2 Q3 Q4 Q1
OSC1
CPU
Clock
Peripheral
Clock
Sleep
Program
Counter
PC
PC + 2
FIGURE 3-5:
TRANSITION TIMING FOR WAKE FROM SLEEP
Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
Q2 Q3 Q4 Q1 Q2
Q1
OSC1
(1)
TOST
CPU Clock
Peripheral
Clock
Program
Counter
PC
OSTS bit Set
PC + 2
PC + 4
PC + 6
Wake Event
Note1: TOST = 1024 TOSC. These intervals are not shown to scale.
DS39682C-page 34
Preliminary
© 2007 Microchip Technology Inc.
PIC18F45J10 FAMILY
3.4.1
PRI_IDLE MODE
3.4.2
SEC_IDLE MODE
This mode is unique among the three low-power Idle
modes, in that it does not disable the primary device
clock. For timing-sensitive applications, this allows for
the fastest resumption of device operation with its more
accurate primary clock source, since the clock source
does not have to “warm up” or transition from another
oscillator.
In SEC_IDLE mode, the CPU is disabled but the
peripherals continue to be clocked from the Timer1
oscillator. This mode is entered from SEC_RUN by set-
ting the IDLEN bit and executing a SLEEPinstruction. If
the device is in another Run mode, set IDLEN first, then
set SCS1:SCS0 to ‘01’ and execute SLEEP. When the
clock source is switched to the Timer1 oscillator, the
primary oscillator is shut-down, the OSTS bit is cleared
and the T1RUN bit is set.
PRI_IDLE mode is entered from PRI_RUN mode by
setting the IDLEN bit and executing a SLEEP instruc-
tion. If the device is in another Run mode, set IDLEN
first, then set the SCS bits to ‘10’ and execute SLEEP.
Although the CPU is disabled, the peripherals continue
to be clocked from the primary clock source specified
by the FOSC0 configuration bit. The OSTS bit remains
set (see Figure 3-6).
When a wake event occurs, the peripherals continue to
be clocked from the Timer1 oscillator. After an interval
of TCSD following the wake event, the CPU begins exe-
cuting code being clocked by the Timer1 oscillator. The
IDLEN and SCS bits are not affected by the wake-up;
the Timer1 oscillator continues to run (see Figure 3-7).
When a wake event occurs, the CPU is clocked from the
primary clock source. A delay of interval TCSD is
required between the wake event and when code
execution starts. This is required to allow the CPU to
become ready to execute instructions. After the
wake-up, the OSTS bit remains set. The IDLEN and
SCS bits are not affected by the wake-up (see
Figure 3-7).
Note:
The Timer1 oscillator should already be
running prior to entering SEC_IDLE mode.
If the T1OSCEN bit is not set when the
SLEEPinstruction is executed, the SLEEP
instruction will be ignored and entry to
SEC_IDLE mode will not occur. If the
Timer1 oscillator is enabled, but not yet
running, peripheral clocks will be delayed
until the oscillator has started. In such
situations, initial oscillator operation is far
from stable and unpredictable operation
may result.
FIGURE 3-6:
TRANSITION TIMING FOR ENTRY TO IDLE MODE
Q3
Q4
Q1
Q1
Q2
OSC1
CPU Clock
Peripheral
Clock
Program
Counter
PC
PC + 2
FIGURE 3-7:
TRANSITION TIMING FOR WAKE FROM IDLE TO RUN MODE
Q1
Q3
Q4
Q2
OSC1
TCSD
CPU Clock
Peripheral
Clock
Program
Counter
PC
Wake Event
© 2007 Microchip Technology Inc.
Preliminary
DS39682C-page 35
PIC18F45J10 FAMILY
3.4.3
RC_IDLE MODE
3.5.2
EXIT BY WDT TIME-OUT
In RC_IDLE mode, the CPU is disabled but the periph-
erals continue to be clocked from the internal oscillator.
This mode allows for controllable power conservation
during Idle periods.
A WDT time-out will cause different actions depending
on which power-managed mode the device is in when
the time-out occurs.
If the device is not executing code (all Idle modes and
Sleep mode), the time-out will result in an exit from the
power-managed mode (see Section 3.2 “Run
Modes” and Section 3.3 “Sleep Mode”). If the device
is executing code (all Run modes), the time-out will
result in a WDT Reset (see Section 20.2 “Watchdog
Timer (WDT)”).
From RC_RUN, this mode is entered by setting the
IDLEN bit and executing a SLEEP instruction. If the
device is in another Run mode, first set IDLEN, then
clear the SCS bits and execute SLEEP. When the clock
source is switched to the INTRC, the primary oscillator
is shut down and the OSTS bit is cleared.
When a wake event occurs, the peripherals continue to
be clocked from the INTRC. After a delay of TCSD
following the wake event, the CPU begins executing
code being clocked by the INTRC. The IDLEN and
SCS bits are not affected by the wake-up. The INTRC
source will continue to run if either the WDT or the
Fail-Safe Clock Monitor is enabled.
The WDT timer and postscaler are cleared by one of
the following events:
• executing a SLEEPor CLRWDTinstruction
• the loss of a currently selected clock source (if the
Fail-Safe Clock Monitor is enabled)
3.5.3
EXIT BY RESET
Exiting an Idle or Sleep mode by Reset automatically
forces the device to run from the INTRC.
3.5
Exiting Idle and Sleep Modes
An exit from Sleep mode, or any of the Idle modes, is
triggered by an interrupt, a Reset or a WDT time-out.
This section discusses the triggers that cause exits
from power-managed modes. The clocking subsystem
actions are discussed in each of the power-managed
modes sections (see Section 3.2 “Run Modes”,
Section 3.3 “Sleep Mode” and Section 3.4 “Idle
Modes”).
3.5.4
EXIT WITHOUT AN OSCILLATOR
START-UP DELAY
Certain exits from power-managed modes do not
invoke the OST at all. There are two cases:
• PRI_IDLE mode where the primary clock source
is not stopped; and
• the primary clock source is the EC mode.
3.5.1
EXIT BY INTERRUPT
In these instances, the primary clock source either
does not require an oscillator start-up delay, since it is
already running (PRI_IDLE), or normally does not
require an oscillator start-up delay (EC). However, a
fixed delay of interval TCSD following the wake event is
still required when leaving Sleep and Idle modes to
allow the CPU to prepare for execution. Instruction
execution resumes on the first clock cycle following this
delay.
Any of the available interrupt sources can cause the
device to exit from an Idle mode, or the Sleep mode, to
a Run mode. To enable this functionality, an interrupt
source must be enabled by setting its enable bit in one
of the INTCON or PIE registers. The exit sequence is
initiated when the corresponding interrupt flag bit is set.
On all exits from Idle or Sleep modes by interrupt, code
execution branches to the interrupt vector if the
GIE/GIEH bit (INTCON<7>) is set. Otherwise, code
execution continues or resumes without branching
(see Section 8.0 “Interrupts”).
A fixed delay of interval TCSD following the wake event
is required when leaving Sleep and Idle modes. This
delay is required for the CPU to prepare for execution.
Instruction execution resumes on the first clock cycle
following this delay.
DS39682C-page 36
Preliminary
© 2007 Microchip Technology Inc.
PIC18F45J10 FAMILY
4.1
RCON Register
4.0
RESET
Device Reset events are tracked through the RCON
register (Register 4-1). The lower five bits of the
register indicate that a specific Reset event has
occurred. In most cases, these bits can only be set by
the event and must be cleared by the application after
the event. The state of these flag bits, taken together,
can be read to indicate the type of Reset that just
occurred. This is described in more detail in
Section 4.6 “Reset State of Registers”.
The PIC18F45J10 family of devices differentiate
between various kinds of Reset:
a) Power-on Reset (POR)
b) MCLR Reset during normal operation
c) MCLR Reset during power-managed modes
d) Watchdog Timer (WDT) Reset (during
execution)
e) Brown-out Reset (BOR)
f) RESETInstruction
The RCON register also has a control bit for setting
interrupt priority (IPEN). Interrupt priority is discussed
in Section 8.0 “Interrupts”.
g) Stack Full Reset
h) Stack Underflow Reset
This section discusses Resets generated by MCLR,
POR and BOR and covers the operation of the various
start-up timers. Stack Reset events are covered in
Section 5.1.2.4 “Stack Full and Underflow Resets”.
WDT Resets are covered in Section 20.2 “Watchdog
Timer (WDT)”.
A simplified block diagram of the On-Chip Reset Circuit
is shown in Figure 4-1.
FIGURE 4-1:
SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT
RESET
Instruction
Stack
Pointer
Stack Full/Underflow Reset
External Reset
MCLR
( )_IDLE
Sleep
WDT
Time-out
VDD Rise
Detect
POR Pulse
VDD
Brown-out
(1)
Reset
S
PWRT
32 μs
Chip_Reset
65.5 ms
PWRT
11-bit Ripple Counter
Q
R
INTRC
Note 1: The Brown-out Reset is not available in PIC18LF2XJ10/4XJ10 devices.
© 2007 Microchip Technology Inc.
Preliminary
DS39682C-page 37
PIC18F45J10 FAMILY
REGISTER 4-1:
RCON: RESET CONTROL REGISTER
R/W-0
IPEN
U-0
—
U-0
—
R/W-1
RI
R-1
TO
R-1
PD
R/W-0
POR
R/W-0
BOR
bit 7
bit 0
bit 7
IPEN: Interrupt Priority Enable bit
1= Enable priority levels on interrupts
0= Disable priority levels on interrupts (PIC16CXXX Compatibility mode)
bit 6-5 Unimplemented: Read as ‘0’
bit 4
RI: RESETInstruction Flag bit
1= The RESETinstruction was not executed (set by firmware only)
0= The RESETinstruction was executed causing a device Reset (must be set in software after
a Brown-out Reset occurs)
bit 3
bit 2
bit 1
bit 0
TO: Watchdog Time-out Flag bit
1= Set by power-up, CLRWDTinstruction or SLEEPinstruction
0= A WDT time-out occurred
PD: Power-Down Detection Flag bit
1= Set by power-up or by the CLRWDTinstruction
0= Set by execution of the SLEEPinstruction
POR: Power-on Reset Status bit
1= A Power-on Reset has not occurred (set by firmware only)
0= A Power-on Reset occurred (must be set in software after a Power-on Reset occurs)
BOR: Brown-out Reset Status bit
1= A Brown-out Reset has not occurred (set by firmware only)
0= A Brown-out Reset occurred (must be set in software after a Brown-out Reset occurs)
Note:
BOR is not available in PIC18LF2XJ10/4XJ10 devices.
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
Note 1: It is recommended that the POR bit be set after a Power-on Reset has been
detected, so that subsequent Power-on Resets may be detected.
2: If the on-chip voltage regulator is disabled, BOR remains ‘0’ at all times. See
Section 4.4.1 “Detecting BOR” for more information.
3: Brown-out Reset is said to have occurred when BOR is ‘0’ and POR is ‘1’
(assuming that POR was set to ‘1’ by software immediately after POR).
DS39682C-page 38
Preliminary
© 2007 Microchip Technology Inc.
PIC18F45J10 FAMILY
FIGURE 4-2:
EXTERNAL POWER-ON
RESET CIRCUIT (FOR
SLOW VDD POWER-UP)
4.2
Master Clear (MCLR)
The MCLR pin provides a method for triggering a hard
external Reset of the device. A Reset is generated by
holding the pin low. PIC18 extended microcontroller
devices have a noise filter in the MCLR Reset path
which detects and ignores small pulses.
VDD
VDD
D
R
The MCLR pin is not driven low by any internal Resets,
including the WDT.
R1
MCLR
PIC18F45J10
C
4.3
Power-on Reset (POR)
A Power-on Reset condition is generated on-chip
whenever VDD rises above a certain threshold. This
allows the device to start in the initialized state when
VDD is adequate for operation.
Note 1: External Power-on Reset circuit is required
only if the VDD power-up slope is too slow.
The diode D helps discharge the capacitor
quickly when VDD powers down.
To take advantage of the POR circuitry, tie the MCLR
pin through a resistor (1 kΩ to 10 kΩ) to VDD. This will
eliminate external RC components usually needed to
create a Power-on Reset delay. A minimum rise rate for
VDD is specified (parameter D004). For a slow rise
time, see Figure 4-2.
2: R < 40 kΩ is recommended to make sure that
the voltage drop across R does not violate
the device’s electrical specification.
3: R1 ≥ 1 kΩ will limit any current flowing into
MCLR from external capacitor C, in the event
of MCLR pin breakdown, due to Electrostatic
Discharge (ESD) or Electrical Overstress
(EOS).
When the device starts normal operation (i.e., exits the
Reset condition), device operating parameters
(voltage, frequency, temperature, etc.) must be met to
ensure operation. If these conditions are not met, the
device must be held in Reset until the operating
conditions are met.
4.4.1
DETECTING BOR
The BOR bit always resets to ‘0’ on any BOR or POR
event. This makes it difficult to determine if a BOR
event has occurred just by reading the state of BOR
alone. A more reliable method is to simultaneously
check the state of both POR and BOR. This assumes
that the POR bit is reset to ‘1’ in software immediately
after any POR event. If BOR is ‘0’ while POR is ‘1’, it
can be reliably assumed that a BOR event has
occurred.
POR events are captured by the POR bit (RCON<1>).
The state of the bit is set to ‘0’ whenever a POR occurs;
it does not change for any other Reset event. POR is
not reset to ‘1’ by any hardware event. To capture
multiple events, the user manually resets the bit to ‘1’
in software following any POR.
4.4
Brown-out Reset (BOR)
(PIC18F2X1X/4X1X Devices Only)
In devices designated with an “LF” part number (such
as PIC18LF25J10), Brown-out Reset functionality is
disabled. In this case, the BOR bit cannot be used to
determine a BOR event. The BOR bit is still cleared by
a POR event.
Once a BOR has occurred, the Power-up Timer will
keep the chip in Reset for TPWRT (parameter 33). If
VDD drops below VBOR while the Power-up Timer is
running, the chip will go back into a Brown-out Reset
and the Power-up Timer will be initialized. Once VDD
rises above VBOR, the Power-up Timer will execute the
additional time delay.
© 2007 Microchip Technology Inc.
Preliminary
DS39682C-page 39
PIC18F45J10 FAMILY
4.5.1
TIME-OUT SEQUENCE
4.5
Power-up Timer (PWRT)
If enabled, the PWRT time-out is invoked after the POR
pulse has cleared. The total time-out will vary based on
the status of the PWRT. Figure 4-3, Figure 4-4,
Figure 4-5 and Figure 4-6 all depict time-out
sequences on power-up with the Power-up Timer
enabled.
PIC18F45J10 family devices incorporate an on-chip
Power-up Timer (PWRT) to help regulate the Power-on
Reset process. The PWRT is always enabled. The
main function is to ensure that the device voltage is
stable before code is executed.
The Power-up Timer (PWRT) of the PIC18F45J10
family devices is an 11-bit counter which uses the
INTRC source as the clock input. This yields an
approximate time interval of 2048 x 32 μs = 65.6 ms.
While the PWRT is counting, the device is held in
Reset.
Since the time-outs occur from the POR pulse, if MCLR
is kept low long enough, the PWRT will expire. Bringing
MCLR high will begin execution immediately
(Figure 4-5). This is useful for testing purposes, or to
synchronize more than one PIC18F device operating in
parallel.
The power-up time delay depends on the INTRC clock
and will vary from chip to chip due to temperature and
process variation. See DC parameter 33 for details.
FIGURE 4-3:
TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD, VDD RISE < TPWRT)
VDD
MCLR
INTERNAL POR
TPWRT
PWRT TIME-OUT
INTERNAL RESET
FIGURE 4-4:
TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 1
VDD
MCLR
INTERNAL POR
TPWRT
PWRT TIME-OUT
INTERNAL RESET
DS39682C-page 40
Preliminary
© 2007 Microchip Technology Inc.
PIC18F45J10 FAMILY
FIGURE 4-5:
TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 2
VDD
MCLR
INTERNAL POR
TPWRT
PWRT TIME-OUT
INTERNAL RESET
FIGURE 4-6:
SLOW RISE TIME (MCLR TIED TO VDD, VDD RISE > TPWRT)
3.3V
0V
1V
VDD
MCLR
INTERNAL POR
TPWRT
PWRT TIME-OUT
INTERNAL RESET
© 2007 Microchip Technology Inc.
Preliminary
DS39682C-page 41
PIC18F45J10 FAMILY
Table 4-2 describes the Reset states for all of the
Special Function Registers. These are categorized by
Power-on and Brown-out Resets, Master Clear and
WDT Resets and WDT wake-ups.
4.6
Reset State of Registers
Most registers are unaffected by a Reset. Their status
is unknown on POR and unchanged by all other
Resets. The other registers are forced to a “Reset
state” depending on the type of Reset that occurred.
Most registers are not affected by a WDT wake-up,
since this is viewed as the resumption of normal
operation. Status bits from the RCON register, RI, TO,
PD, POR and BOR, are set or cleared differently in
different Reset situations, as indicated in Table 4-1.
These bits are used in software to determine the nature
of the Reset.
TABLE 4-1:
STATUS BITS, THEIR SIGNIFICANCE AND THE INITIALIZATION CONDITION FOR
RCON REGISTER
RCON Register
STKPTR Register
Program
Condition
Counter(1)
RI
TO
PD
POR BOR(2) STKFUL STKUNF
Power-on Reset
RESETinstruction
Brown-out
0000h
0000h
0000h
0000h
1
0
1
u
1
u
1
1
1
u
1
u
0
u
u
u
0
u
0
u
0
u
u
u
0
u
u
u
MCLR during power-managed
Run modes
MCLR during power-managed
Idle modes and Sleep mode
0000h
0000h
0000h
u
u
u
1
0
u
0
u
u
u
u
u
u
u
u
u
u
u
u
u
u
WDT time-out during full power
or power-managed Run modes
MCLR during full power
execution
Stack Full Reset (STVREN = 1)
0000h
0000h
u
u
u
u
u
u
u
u
u
u
1
u
u
1
Stack Underflow Reset
(STVREN = 1)
Stack Underflow Error (not an
actual Reset, STVREN = 0)
0000h
u
u
u
0
u
0
u
u
u
u
u
u
1
u
WDT time-out during
power-managed Idle or Sleep
modes
PC + 2
Interrupt exit from
PC + 2
u
u
0
u
u
u
u
power-managed modes
Legend: u= unchanged
Note 1: When the wake-up is due to an interrupt and the GIEH or GIEL bits are set, the PC is loaded with the
interrupt vector (0008h or 0018h).
2: BOR is not available in PIC18LF2X1X/4X1X devices.
DS39682C-page 42
Preliminary
© 2007 Microchip Technology Inc.
PIC18F45J10 FAMILY
TABLE 4-2:
Register
INITIALIZATION CONDITIONS FOR ALL REGISTERS
MCLR Resets
WDT Reset
Power-on Reset,
Brown-out Reset
Wake-up via WDT
or Interrupt
Applicable Devices
RESET Instruction
Stack Resets
TOSU
PIC18F2XJ10 PIC18F4XJ10
PIC18F2XJ10 PIC18F4XJ10
PIC18F2XJ10 PIC18F4XJ10
PIC18F2XJ10 PIC18F4XJ10
PIC18F2XJ10 PIC18F4XJ10
PIC18F2XJ10 PIC18F4XJ10
PIC18F2XJ10 PIC18F4XJ10
PIC18F2XJ10 PIC18F4XJ10
PIC18F2XJ10 PIC18F4XJ10
PIC18F2XJ10 PIC18F4XJ10
PIC18F2XJ10 PIC18F4XJ10
PIC18F2XJ10 PIC18F4XJ10
PIC18F2XJ10 PIC18F4XJ10
PIC18F2XJ10 PIC18F4XJ10
PIC18F2XJ10 PIC18F4XJ10
PIC18F2XJ10 PIC18F4XJ10
PIC18F2XJ10 PIC18F4XJ10
PIC18F2XJ10 PIC18F4XJ10
PIC18F2XJ10 PIC18F4XJ10
PIC18F2XJ10 PIC18F4XJ10
PIC18F2XJ10 PIC18F4XJ10
PIC18F2XJ10 PIC18F4XJ10
PIC18F2XJ10 PIC18F4XJ10
PIC18F2XJ10 PIC18F4XJ10
PIC18F2XJ10 PIC18F4XJ10
PIC18F2XJ10 PIC18F4XJ10
PIC18F2XJ10 PIC18F4XJ10
PIC18F2XJ10 PIC18F4XJ10
PIC18F2XJ10 PIC18F4XJ10
PIC18F2XJ10 PIC18F4XJ10
PIC18F2XJ10 PIC18F4XJ10
PIC18F2XJ10 PIC18F4XJ10
---0 0000
0000 0000
0000 0000
00-0 0000
---0 0000
0000 0000
0000 0000
--00 0000
0000 0000
0000 0000
0000 0000
xxxx xxxx
xxxx xxxx
0000 000x
1111 -1-1
11-0 0-00
N/A
---0 0000
0000 0000
0000 0000
uu-0 0000
---0 0000
0000 0000
0000 0000
--00 0000
0000 0000
0000 0000
0000 0000
uuuu uuuu
uuuu uuuu
0000 000u
1111 -1-1
11-0 0-00
N/A
---0 uuuu(1)
uuuu uuuu(1)
uuuu uuuu(1)
uu-u uuuu(1)
---u uuuu
uuuu uuuu
PC + 2(2)
--uu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu(3)
uuuu -u-u(3)
uu-u u-uu(3)
N/A
TOSH
TOSL
STKPTR
PCLATU
PCLATH
PCL
TBLPTRU
TBLPTRH
TBLPTRL
TABLAT
PRODH
PRODL
INTCON
INTCON2
INTCON3
INDF0
POSTINC0
POSTDEC0
PREINC0
PLUSW0
FSR0H
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
---- xxxx
xxxx xxxx
xxxx xxxx
N/A
---- uuuu
uuuu uuuu
uuuu uuuu
N/A
---- uuuu
uuuu uuuu
uuuu uuuu
N/A
FSR0L
WREG
INDF1
POSTINC1
POSTDEC1
PREINC1
PLUSW1
FSR1H
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
---- xxxx
xxxx xxxx
---- 0000
---- uuuu
uuuu uuuu
---- 0000
---- uuuu
uuuu uuuu
---- uuuu
FSR1L
BSR
Legend: u= unchanged, x= unknown, -= unimplemented bit, read as ‘0’, q= value depends on condition.
Shaded cells indicate conditions do not apply for the designated device.
Note 1: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are
updated with the current value of the PC. The STKPTR is modified to point to the next location in the
hardware stack.
2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt
vector (0008h or 0018h).
3: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).
4: See Table 4-1 for Reset value for specific condition.
© 2007 Microchip Technology Inc.
Preliminary
DS39682C-page 43
PIC18F45J10 FAMILY
TABLE 4-2:
INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)
MCLR Resets
WDT Reset
RESET Instruction
Stack Resets
Power-on Reset,
Brown-out Reset
Wake-up via WDT
or Interrupt
Register
Applicable Devices
INDF2
PIC18F2XJ10 PIC18F4XJ10
PIC18F2XJ10 PIC18F4XJ10
PIC18F2XJ10 PIC18F4XJ10
PIC18F2XJ10 PIC18F4XJ10
PIC18F2XJ10 PIC18F4XJ10
PIC18F2XJ10 PIC18F4XJ10
PIC18F2XJ10 PIC18F4XJ10
PIC18F2XJ10 PIC18F4XJ10
PIC18F2XJ10 PIC18F4XJ10
PIC18F2XJ10 PIC18F4XJ10
PIC18F2XJ10 PIC18F4XJ10
PIC18F2XJ10 PIC18F4XJ10
PIC18F2XJ10 PIC18F4XJ10
PIC18F2XJ10 PIC18F4XJ10
PIC18F2XJ10 PIC18F4XJ10
PIC18F2XJ10 PIC18F4XJ10
PIC18F2XJ10 PIC18F4XJ10
PIC18F2XJ10 PIC18F4XJ10
PIC18F2XJ10 PIC18F4XJ10
PIC18F2XJ10 PIC18F4XJ10
PIC18F2XJ10 PIC18F4XJ10
PIC18F2XJ10 PIC18F4XJ10
PIC18F2XJ10 PIC18F4XJ10
PIC18F2XJ10 PIC18F4XJ10
PIC18F2XJ10 PIC18F4XJ10
PIC18F2XJ10 PIC18F4XJ10
PIC18F2XJ10 PIC18F4XJ10
PIC18F2XJ10 PIC18F4XJ10
PIC18F2XJ10 PIC18F4XJ10
PIC18F2XJ10 PIC18F4XJ10
N/A
N/A
N/A
POSTINC2
POSTDEC2
PREINC2
PLUSW2
FSR2H
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
---- xxxx
xxxx xxxx
---x xxxx
0000 0000
xxxx xxxx
1111 1111
0--- q-00
---- ---0
0--1 11q0
xxxx xxxx
xxxx xxxx
0000 0000
0000 0000
1111 1111
-000 0000
xxxx xxxx
0000 0000
0000 0000
0000 0000
0000 0000
xxxx xxxx
xxxx xxxx
0-00 0000
--00 0qqq
0-00 0000
---- uuuu
uuuu uuuu
---u uuuu
0000 0000
uuuu uuuu
1111 1111
0--- q-00
---- ---0
0--q qquu
uuuu uuuu
uuuu uuuu
u0uu uuuu
0000 0000
1111 1111
-000 0000
uuuu uuuu
0000 0000
0000 0000
0000 0000
0000 0000
uuuu uuuu
uuuu uuuu
0-00 0000
--00 0qqq
0-00 0000
---- uuuu
uuuu uuuu
---u uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
u--- q-uu
---- ---u
u--u qquu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
1111 1111
-uuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
u-uu uuuu
--uu uqqq
u-uu uuuu
FSR2L
STATUS
TMR0H
TMR0L
T0CON
OSCCON
WDTCON
RCON(4)
TMR1H
TMR1L
T1CON
TMR2
PR2
T2CON
SSP1BUF
SSP1ADD
SSP1STAT
SSP1CON1
SSP1CON2
ADRESH
ADRESL
ADCON0
ADCON1
ADCON2
Legend: u= unchanged, x= unknown, -= unimplemented bit, read as ‘0’, q= value depends on condition.
Shaded cells indicate conditions do not apply for the designated device.
Note 1: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are
updated with the current value of the PC. The STKPTR is modified to point to the next location in the
hardware stack.
2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt
vector (0008h or 0018h).
3: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).
4: See Table 4-1 for Reset value for specific condition.
DS39682C-page 44
Preliminary
© 2007 Microchip Technology Inc.
PIC18F45J10 FAMILY
TABLE 4-2:
Register
INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)
MCLR Resets
WDT Reset
Power-on Reset,
Brown-out Reset
Wake-up via WDT
or Interrupt
Applicable Devices
RESET Instruction
Stack Resets
CCPR1H
CCPR1L
CCP1CON
CCPR2H
CCPR2L
CCP2CON
BAUDCON
ECCP1DEL
ECCP1AS
CVRCON
CMCON
SPBRGH
SPBRG
RCREG
TXREG
TXSTA
PIC18F2XJ10 PIC18F4XJ10
PIC18F2XJ10 PIC18F4XJ10
PIC18F2XJ10 PIC18F4XJ10
PIC18F2XJ10 PIC18F4XJ10
PIC18F2XJ10 PIC18F4XJ10
PIC18F2XJ10 PIC18F4XJ10
PIC18F2XJ10 PIC18F4XJ10
PIC18F2XJ10 PIC18F4XJ10
PIC18F2XJ10 PIC18F4XJ10
PIC18F2XJ10 PIC18F4XJ10
PIC18F2XJ10 PIC18F4XJ10
PIC18F2XJ10 PIC18F4XJ10
PIC18F2XJ10 PIC18F4XJ10
PIC18F2XJ10 PIC18F4XJ10
PIC18F2XJ10 PIC18F4XJ10
PIC18F2XJ10 PIC18F4XJ10
PIC18F2XJ10 PIC18F4XJ10
PIC18F2XJ10 PIC18F4XJ10
PIC18F2XJ10 PIC18F4XJ10
PIC18F2XJ10 PIC18F4XJ10
PIC18F2XJ10 PIC18F4XJ10
PIC18F2XJ10 PIC18F4XJ10
PIC18F2XJ10 PIC18F4XJ10
PIC18F2XJ10 PIC18F4XJ10
PIC18F2XJ10 PIC18F4XJ10
PIC18F2XJ10 PIC18F4XJ10
PIC18F2XJ10 PIC18F4XJ10
PIC18F2XJ10 PIC18F4XJ10
xxxx xxxx
xxxx xxxx
0000 0000
xxxx xxxx
xxxx xxxx
--00 0000
01-0 0-00
0000 0000
0000 0000
0000 0000
0000 0111
0000 0000
0000 0000
0000 0000
xxxx xxxx
0000 0010
0000 000x
0000 0000
---0 x00-
11-- ----
00-- ----
00-- ----
11-- 1--1
00-- 0--0
00-- 0--0
1111 1111
0000 0000
0000 0000
uuuu uuuu
uuuu uuuu
0000 0000
uuuu uuuu
uuuu uuuu
--00 0000
01-0 0-00
0000 0000
0000 0000
0000 0000
0000 0111
0000 0000
0000 0000
0000 0000
uuuu uuuu
0000 0010
0000 000x
0000 0000
---0 x00-
11-- ----
00-- ----
00-- ----
11-- 1--1
00-- 0--0
00-- 0--0
1111 1111
0000 0000
0000 0000
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
--uu uuuu
uu-u u-uu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
---u uuu-
uu-- ----
uu-- ----(3)
uu-- ----
uu-- u--u
uu-- u--u(3)
uu-- u--u
uuuu uuuu
uuuu uuuu(3)
uuuu uuuu
RCSTA
EECON2
EECON1
IPR3
PIR3
PIE3
IPR2
PIR2
PIE2
IPR1
PIR1
PIE1
Legend: u= unchanged, x= unknown, -= unimplemented bit, read as ‘0’, q= value depends on condition.
Shaded cells indicate conditions do not apply for the designated device.
Note 1: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are
updated with the current value of the PC. The STKPTR is modified to point to the next location in the
hardware stack.
2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt
vector (0008h or 0018h).
3: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).
4: See Table 4-1 for Reset value for specific condition.
© 2007 Microchip Technology Inc.
Preliminary
DS39682C-page 45
PIC18F45J10 FAMILY
TABLE 4-2:
INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)
MCLR Resets
WDT Reset
RESET Instruction
Stack Resets
Power-on Reset,
Brown-out Reset
Wake-up via WDT
or Interrupt
Register
Applicable Devices
TRISE
PIC18F2XJ10 PIC18F4XJ10
PIC18F2XJ10 PIC18F4XJ10
PIC18F2XJ10 PIC18F4XJ10
PIC18F2XJ10 PIC18F4XJ10
PIC18F2XJ10 PIC18F4XJ10
PIC18F2XJ10 PIC18F4XJ10
PIC18F2XJ10 PIC18F4XJ10
PIC18F2XJ10 PIC18F4XJ10
PIC18F2XJ10 PIC18F4XJ10
PIC18F2XJ10 PIC18F4XJ10
PIC18F2XJ10 PIC18F4XJ10
PIC18F2XJ10 PIC18F4XJ10
PIC18F2XJ10 PIC18F4XJ10
PIC18F2XJ10 PIC18F4XJ10
PIC18F2XJ10 PIC18F4XJ10
PIC18F2XJ10 PIC18F4XJ10
PIC18F2XJ10 PIC18F4XJ10
PIC18F2XJ10 PIC18F4XJ10
PIC18F2XJ10 PIC18F4XJ10
PIC18F2XJ10 PIC18F4XJ10
0000 -111
1111 1111
1111 1111
1111 1111
--1- 1111
xxxx xxxx
---- -xxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
--x- xxxx
0000 0000
0000 0000
0000 0000
0000 0000
---- -xxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
--0- 0000
1111 -111
1111 1111
1111 1111
1111 1111
--1- 1111
uuuu uuuu
---- -uuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
--u- uuuu
0000 0000
0000 0000
0000 0000
0000 0000
---- -uuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
--0- 0000
uuuu -uuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
--u- uuuu
uuuu uuuu
---- -uuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
--u- uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
---- -uuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
--u- uuuu
TRISD
TRISC
TRISB
TRISA
SSP2BUF
LATE
LATD
LATC
LATB
LATA
SSP2ADD
SSP2STAT
SSP2CON1
SSP2CON2
PORTE
PORTD
PORTC
PORTB
PORTA
Legend: u= unchanged, x= unknown, -= unimplemented bit, read as ‘0’, q= value depends on condition.
Shaded cells indicate conditions do not apply for the designated device.
Note 1: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are
updated with the current value of the PC. The STKPTR is modified to point to the next location in the
hardware stack.
2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt
vector (0008h or 0018h).
3: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).
4: See Table 4-1 for Reset value for specific condition.
DS39682C-page 46
Preliminary
© 2007 Microchip Technology Inc.
PIC18F45J10 FAMILY
5.1
Program Memory Organization
5.0
MEMORY ORGANIZATION
PIC18 microcontrollers implement a 21-bit program
counter, which is capable of addressing a 2-Mbyte
program memory space. Accessing a location between
the upper boundary of the physically implemented
memory and the 2-Mbyte address will return all ‘0’s (a
NOPinstruction).
There are two types of memory in PIC18 Enhanced
microcontroller devices:
• Program Memory
• Data RAM
As Harvard architecture devices, the data and program
memories use separate busses; this allows for
concurrent access of the two memory spaces.
The PIC18F24J10 and PIC18F44J10 each have
16 Kbytes of Flash memory and can store up to 8,192
single-word instructions. The PIC18F25J10 and
PIC18F45J10 each have 32 Kbytes of Flash memory
and can store up to 16,384 single-word instructions.
Additional detailed information on the operation of the
Flash program memory is provided in Section 6.0
“Flash Program Memory”.
PIC18 devices have two interrupt vectors. The Reset
vector address is at 0000h and the interrupt vector
addresses are at 0008h and 0018h.
The program memory map for the PIC18F45J10 family
devices is shown in Figure 5-1.
FIGURE 5-1:
PROGRAM MEMORY MAP AND STACK FOR PIC18F45J10 FAMILY DEVICES
PC<20:0>
21
CALL,RCALL,RETURN
RETFIE,RETLW
Stack Level 1
•
•
•
Stack Level 31
0000h
Reset Vector
High Priority Interrupt Vector
Low Priority Interrupt Vector
0008h
0018h
On-Chip
Program Memory
On-Chip
Program Memory
3FFFh
4000h
PIC18FX4J10
7FFFh
8000h
PIC18FX5J10
Read ‘0’
Read ‘0’
1FFFFFh
200000h
© 2007 Microchip Technology Inc.
Preliminary
DS39682C-page 47
PIC18F45J10 FAMILY
The stack operates as a 31-word by 21-bit RAM and a
5-bit Stack Pointer, STKPTR. The stack space is not
part of either program or data space. The Stack Pointer
is readable and writable and the address on the top of
the stack is readable and writable through the top-of-
stack Special File Registers. Data can also be pushed
to, or popped from the stack, using these registers.
5.1.1
PROGRAM COUNTER
The Program Counter (PC) specifies the address of the
instruction to fetch for execution. The PC is 21 bits wide
and is contained in three separate 8-bit registers. The
low byte, known as the PCL register, is both readable
and writable. The high byte, or PCH register, contains
the PC<15:8> bits; it is not directly readable or writable.
Updates to the PCH register are performed through the
PCLATH register. The upper byte is called PCU. This
register contains the PC<20:16> bits; it is also not
directly readable or writable. Updates to the PCU
register are performed through the PCLATU register.
A CALLtype instruction causes a push onto the stack;
the Stack Pointer is first incremented and the location
pointed to by the Stack Pointer is written with the
contents of the PC (already pointing to the instruction
following the CALL). A RETURNtype instruction causes
a pop from the stack; the contents of the location
pointed to by the STKPTR are transferred to the PC
and then the Stack Pointer is decremented.
The contents of PCLATH and PCLATU are transferred
to the program counter by any operation that writes
PCL. Similarly, the upper two bytes of the program
counter are transferred to PCLATH and PCLATU by an
operation that reads PCL. This is useful for computed
offsets to the PC (see Section 5.1.4.1 “Computed
GOTO”).
The Stack Pointer is initialized to ‘00000’ after all
Resets. There is no RAM associated with the location
corresponding to a Stack Pointer value of ‘00000’; this
is only a Reset value. Status bits indicate if the stack is
full or has overflowed or has underflowed.
The PC addresses bytes in the program memory. To
prevent the PC from becoming misaligned with word
instructions, the Least Significant bit of PCL is fixed to
a value of ‘0’. The PC increments by 2 to address
sequential instructions in the program memory.
5.1.2.1
Top-of-Stack Access
Only the top of the return address stack (TOS) is
readable and writable. A set of three registers,
TOSU:TOSH:TOSL, hold the contents of the stack loca-
tion pointed to by the STKPTR register (Figure 5-2). This
allows users to implement a software stack if necessary.
After a CALL, RCALLor interrupt, the software can read
the pushed value by reading the TOSU:TOSH:TOSL
registers. These values can be placed on a user-defined
software stack. At return time, the software can return
these values to TOSU:TOSH:TOSL and do a return.
The CALL, RCALL, GOTO and program branch
instructions write to the program counter directly. For
these instructions, the contents of PCLATH and
PCLATU are not transferred to the program counter.
5.1.2
RETURN ADDRESS STACK
The return address stack allows any combination of up
to 31 program calls and interrupts to occur. The PC is
pushed onto the stack when a CALLor RCALLinstruc-
tion is executed or an interrupt is Acknowledged. The
PC value is pulled off the stack on a RETURN, RETLW
or RETFIE instruction. PCLATU and PCLATH are not
affected by any of the RETURNor CALLinstructions.
The user must disable the global interrupt enable bits
while accessing the stack to prevent inadvertent stack
corruption.
FIGURE 5-2:
RETURN ADDRESS STACK AND ASSOCIATED REGISTERS
Return Address Stack <20:0>
11111
11110
11101
Top-of-Stack Registers
Stack Pointer
STKPTR<4:0>
TOSU
00h
TOSH
1Ah
TOSL
34h
00010
00011
00010
00001
00000
001A34h
000D58h
Top-of-Stack
DS39682C-page 48
Preliminary
© 2007 Microchip Technology Inc.
PIC18F45J10 FAMILY
When the stack has been popped enough times to
unload the stack, the next pop will return a value of zero
to the PC and sets the STKUNF bit, while the Stack
Pointer remains at zero. The STKUNF bit will remain
set until cleared by software or until a POR occurs.
5.1.2.2
Return Stack Pointer (STKPTR)
The STKPTR register (Register 5-1) contains the Stack
Pointer value, the STKFUL (Stack Overflow) status bit
and the STKUNF (Stack Underflow) status bits. The
value of the Stack Pointer can be 0 through 31. The
Stack Pointer increments before values are pushed
onto the stack and decrements after values are popped
off the stack. On Reset, the Stack Pointer value will be
zero. The user may read and write the Stack Pointer
value. This feature can be used by a Real-Time
Operating System (RTOS) for return stack
maintenance.
Note:
Returning a value of zero to the PC on an
underflow has the effect of vectoring the
program to the Reset vector, where the
stack conditions can be verified and
appropriate actions can be taken. This is
not the same as a Reset, as the contents
of the SFRs are not affected.
After the PC is pushed onto the stack 31 times (without
popping any values off the stack), the STKFUL bit is
set. The STKFUL bit is cleared by software or by a
POR.
5.1.2.3
PUSH and POP Instructions
Since the Top-of-Stack is readable and writable, the
ability to push values onto the stack and pull values off
the stack without disturbing normal program execution
is a desirable feature. The PIC18 instruction set
includes two instructions, PUSH and POP, that permit
the TOS to be manipulated under software control.
TOSU, TOSH and TOSL can be modified to place data
or a return address on the stack.
The action that takes place when the stack becomes
full depends on the state of the STVREN (Stack Over-
flow Reset Enable) configuration bit. (Refer to
Section 20.1 “Configuration Bits” for a description of
the device configuration bits.) If STVREN is set
(default), the 31st push will push the (PC + 2) value
onto the stack, set the STKFUL bit and reset the
device. The STKFUL bit will remain set and the Stack
Pointer will be set to zero.
The PUSHinstruction places the current PC value onto
the stack. This increments the Stack Pointer and loads
the current PC value onto the stack.
If STVREN is cleared, the STKFUL bit will be set on the
31st push and the Stack Pointer will increment to 31.
Any additional pushes will not overwrite the 31st push
and the STKPTR will remain at 31.
The POPinstruction discards the current TOS by decre-
menting the Stack Pointer. The previous value pushed
onto the stack then becomes the TOS value.
REGISTER 5-1:
STKPTR: STACK POINTER REGISTER
R/C-0
R/C-0
U-0
—
R/W-0
SP4
R/W-0
SP3
R/W-0
SP2
R/W-0
SP1
R/W-0
SP0
STKFUL(1) STKUNF(1)
bit 7
bit 0
bit 7
bit 6
STKFUL: Stack Overflow Flag bit(1)
1= Stack became full or overflowed
0= Stack has not become full or overflowed
STKUNF: Stack Underflow Flag bit(1)
1= Stack underflow occurred
0= Stack underflow did not occur
bit 5
Unimplemented: Read as ‘0’
bit 4-0
SP4:SP0: Stack Pointer Location bits
Note 1: Bit 7 and bit 6 are cleared by user software or by a POR.
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented
‘0’ = Bit is cleared
C = Clearable only bit
x = Bit is unknown
© 2007 Microchip Technology Inc.
Preliminary
DS39682C-page 49
PIC18F45J10 FAMILY
5.1.2.4
Stack Full and Underflow Resets
5.1.4
LOOK-UP TABLES IN PROGRAM
MEMORY
Device Resets on stack overflow and stack underflow
conditions are enabled by setting the STVREN bit in
Configuration Register 4L. When STVREN is set, a full
or underflow will set the appropriate STKFUL or
STKUNF bit and then cause a device Reset. When
STVREN is cleared, a full or underflow condition will set
the appropriate STKFUL or STKUNF bit but not cause
a device Reset. The STKFUL or STKUNF bits are
cleared by the user software or a Power-on Reset.
There may be programming situations that require the
creation of data structures, or look-up tables, in
program memory. For PIC18 devices, look-up tables
can be implemented in two ways:
• Computed GOTO
• Table Reads
5.1.4.1
Computed GOTO
5.1.3
FAST REGISTER STACK
A computed GOTOis accomplished by adding an offset
to the program counter. An example is shown in
Example 5-2.
A fast register stack is provided for the STATUS,
WREG and BSR registers, to provide a “fast return”
option for interrupts. The stack for each register is only
one level deep and is neither readable nor writable. It is
loaded with the current value of the corresponding
register when the processor vectors for an interrupt. All
interrupt sources will push values into the stack regis-
ters. The values in the registers are then loaded back
into their associated registers if the RETFIE, FAST
instruction is used to return from the interrupt.
A look-up table can be formed with an ADDWF PCL
instruction and a group of RETLW nninstructions. The
W register is loaded with an offset into the table before
executing a call to that table. The first instruction of the
called routine is the ADDWF PCLinstruction. The next
instruction executed will be one of the RETLW nn
instructions that returns the value ‘nn’ to the calling
function.
If both low and high priority interrupts are enabled, the
stack registers cannot be used reliably to return from
low priority interrupts. If a high priority interrupt occurs
while servicing a low priority interrupt, the stack register
values stored by the low priority interrupt will be
overwritten. In these cases, users must save the key
registers in software during a low priority interrupt.
The offset value (in WREG) specifies the number of
bytes that the program counter should advance and
should be multiples of 2 (LSb = 0).
In this method, only one data byte may be stored in
each instruction location and room on the return
address stack is required.
If interrupt priority is not used, all interrupts may use the
fast register stack for returns from interrupt. If no inter-
rupts are used, the fast register stack can be used to
restore the STATUS, WREG and BSR registers at the
end of a subroutine call. To use the fast register stack
for a subroutine call, a CALLlabel, FASTinstruction
must be executed to save the STATUS, WREG and
EXAMPLE 5-2:
COMPUTED GOTO USING
AN OFFSET VALUE
OFFSET, W
TABLE
MOVF
CALL
ORG
TABLE
nn00h
ADDWF
RETLW
RETLW
RETLW
.
PCL
nnh
nnh
nnh
BSR registers to the fast register stack.
A
RETURN, FASTinstruction is then executed to restore
these registers from the fast register stack.
.
Example 5-1 shows a source code example that uses
the fast register stack during a subroutine call and
return.
.
5.1.4.2
Table Reads and Table Writes
A better method of storing data in program memory
allows two bytes of data to be stored in each instruction
location.
EXAMPLE 5-1:
FAST REGISTER STACK
CODE EXAMPLE
CALL SUB1, FAST
;STATUS, WREG, BSR
;SAVED IN FAST REGISTER
;STACK
Look-up table data may be stored two bytes per pro-
gram word by using table reads and writes. The Table
Pointer (TBLPTR) register specifies the byte address
and the Table Latch (TABLAT) register contains the
data that is read from or written to program memory.
Data is transferred to or from program memory one
byte at a time.
•
•
SUB1
•
•
RETURN, FAST
;RESTORE VALUES SAVED
;IN FAST REGISTER STACK
Table read and table write operations are discussed
further in Section 6.1 “Table Reads and Table
Writes”.
DS39682C-page 50
Preliminary
© 2007 Microchip Technology Inc.
PIC18F45J10 FAMILY
5.2.2
INSTRUCTION FLOW/PIPELINING
5.2
PIC18 Instruction Cycle
An “Instruction Cycle” consists of four Q cycles: Q1
through Q4. The instruction fetch and execute are
pipelined in such a manner that a fetch takes one
instruction cycle, while the decode and execute take
another instruction cycle. However, due to the pipe-
lining, each instruction effectively executes in one
cycle. If an instruction causes the program counter to
change (e.g., GOTO), then two cycles are required to
complete the instruction (Example 5-3).
5.2.1
CLOCKING SCHEME
The microcontroller clock input, whether from an
internal or external source, is internally divided by four
to generate four non-overlapping quadrature clocks
(Q1, Q2, Q3 and Q4). Internally, the program counter is
incremented on every Q1; the instruction is fetched
from the program memory and latched into the instruc-
tion register during Q4. The instruction is decoded and
executed during the following Q1 through Q4. The
clocks and instruction execution flow are shown in
Figure 5-3.
A fetch cycle begins with the Program Counter (PC)
incrementing in Q1.
In the execution cycle, the fetched instruction is latched
into the Instruction Register (IR) in cycle Q1. This
instruction is then decoded and executed during the
Q2, Q3 and Q4 cycles. Data memory is read during Q2
(operand read) and written during Q4 (destination
write).
FIGURE 5-3:
CLOCK/INSTRUCTION CYCLE
Q2
Q3
Q4
Q2
Q3
Q4
Q2
Q3
Q4
Q1
Q1
Q1
OSC1
Q1
Q2
Q3
Q4
Internal
Phase
Clock
PC
PC
PC + 2
PC + 4
OSC2/CLKO
(RC mode)
Execute INST (PC – 2)
Fetch INST (PC)
Execute INST (PC)
Fetch INST (PC + 2)
Execute INST (PC + 2)
Fetch INST (PC + 4)
EXAMPLE 5-3:
INSTRUCTION PIPELINE FLOW
TCY0
TCY1
TCY2
TCY3
TCY4
TCY5
1. MOVLW 55h
2. MOVWF PORTB
3. BRA SUB_1
Fetch 1
Execute 1
Fetch 2
Execute 2
Fetch 3
Execute 3
Fetch 4
4. BSF
PORTA, BIT3 (Forced NOP)
Flush (NOP)
5. Instruction @ address SUB_1
Fetch SUB_1 Execute SUB_1
All instructions are single cycle, except for any program branches. These take two cycles since the fetch instruction
is “flushed” from the pipeline while the new instruction is being fetched and then executed.
© 2007 Microchip Technology Inc.
Preliminary
DS39682C-page 51
PIC18F45J10 FAMILY
The CALLand GOTOinstructions have the absolute pro-
gram memory address embedded into the instruction.
Since instructions are always stored on word bound-
aries, the data contained in the instruction is a word
address. The word address is written to PC<20:1>,
which accesses the desired byte address in program
memory. Instruction #2 in Figure 5-4 shows how the
instruction, GOTO 0006h, is encoded in the program
memory. Program branch instructions, which encode a
relative address offset, operate in the same manner. The
offset value stored in a branch instruction represents the
number of single-word instructions that the PC will be
offset by. Section 21.0 “Instruction Set Summary”
provides further details of the instruction set.
5.2.3
INSTRUCTIONS IN PROGRAM
MEMORY
The program memory is addressed in bytes. Instruc-
tions are stored as two bytes or four bytes in program
memory. The Least Significant Byte of an instruction
word is always stored in a program memory location
with an even address (LSb = 0). To maintain alignment
with instruction boundaries, the PC increments in steps
of 2 and the LSb will always read ‘0’ (see Section 5.1.1
“Program Counter”).
Figure 5-4 shows an example of how instruction words
are stored in the program memory.
FIGURE 5-4:
INSTRUCTIONS IN PROGRAM MEMORY
Word Address
LSB = 1
LSB = 0
↓
Program Memory
Byte Locations →
000000h
000002h
000004h
000006h
000008h
00000Ah
00000Ch
00000Eh
000010h
000012h
000014h
Instruction 1:
Instruction 2:
MOVLW
GOTO
055h
0006h
0Fh
EFh
F0h
C1h
F4h
55h
03h
00h
23h
56h
Instruction 3:
MOVFF
123h, 456h
the instruction sequence. If the first word is skipped for
some reason and the second word is executed by itself,
a NOPis executed instead. This is necessary for cases
when the two-word instruction is preceded by a condi-
tional instruction that changes the PC. Example 5-4
shows how this works.
5.2.4
TWO-WORD INSTRUCTIONS
The standard PIC18 instruction set has four two-word
instructions: CALL, MOVFF, GOTO and LSFR. In all
cases, the second word of the instructions always has
‘1111’ as its four Most Significant bits; the other 12 bits
are literal data, usually a data memory address.
Note:
See Section 5.6 “PIC18 Instruction
Execution and the Extended Instruc-
tion Set” for information on two-word
instructions in the extended instruction set.
The use of ‘1111’ in the 4 MSbs of an instruction spec-
ifies a special form of NOP. If the instruction is executed
in proper sequence – immediately after the first word –
the data in the second word is accessed and used by
EXAMPLE 5-4:
CASE 1:
TWO-WORD INSTRUCTIONS
Source Code
Object Code
0110 0110 0000 0000 TSTFSZ
REG1
REG1, REG2 ; No, skip this word
; Execute this word as a NOP
; continue code
; is RAM location 0?
1100 0001 0010 0011
1111 0100 0101 0110
0010 0100 0000 0000
CASE 2:
MOVFF
ADDWF
REG3
Object Code
Source Code
TSTFSZ
0110 0110 0000 0000
1100 0001 0010 0011
1111 0100 0101 0110
0010 0100 0000 0000
REG1
; is RAM location 0?
MOVFF
REG1, REG2 ; Yes, execute this word
; 2nd word of instruction
ADDWF
REG3
; continue code
DS39682C-page 52
Preliminary
© 2007 Microchip Technology Inc.
PIC18F45J10 FAMILY
5.3.1
BANK SELECT REGISTER (BSR)
5.3
Data Memory Organization
Large areas of data memory require an efficient
addressing scheme to make rapid access to any
address possible. Ideally, this means that an entire
address does not need to be provided for each read or
write operation. For PIC18 devices, this is accom-
plished with a RAM banking scheme. This divides the
memory space into 16 contiguous banks of 256 bytes.
Depending on the instruction, each location can be
addressed directly by its full 12-bit address, or an 8-bit
low-order address and a 4-bit bank pointer.
Note:
The operation of some aspects of data
memory are changed when the PIC18
extended instruction set is enabled. See
Section 5.5 “Data Memory and the
Extended Instruction Set” for more
information.
The data memory in PIC18 devices is implemented as
static RAM. Each register in the data memory has a
12-bit address, allowing up to 4096 bytes of data
memory. The memory space is divided into as many as
16 banks that contain 256 bytes each; PIC18F45J10
family devices implement all 16 banks. Figure 5-5
shows the data memory organization for the
PIC18F45J10 family devices.
Most instructions in the PIC18 instruction set make use
of the bank pointer, known as the Bank Select Register
(BSR). This SFR holds the 4 Most Significant bits of a
location’s address; the instruction itself includes the
8 Least Significant bits. Only the four lower bits of the
BSR are implemented (BSR3:BSR0). The upper four
bits are unused; they will always read ‘0’ and cannot be
written to. The BSR can be loaded directly by using the
MOVLBinstruction.
The data memory contains Special Function Registers
(SFRs) and General Purpose Registers (GPRs). The
SFRs are used for control and status of the controller
and peripheral functions, while GPRs are used for data
storage and scratchpad operations in the user’s
application. Any read of an unimplemented location will
read as ‘0’s.
The value of the BSR indicates the bank in data
memory. The 8 bits in the instruction show the location
in the bank and can be thought of as an offset from the
bank’s lower boundary. The relationship between the
BSR’s value and the bank division in data memory is
shown in Figure 5-6.
The instruction set and architecture allow operations
across all banks. The entire data memory may be
accessed by Direct, Indirect or Indexed Addressing
modes. Addressing modes are discussed later in this
subsection.
Since up to 16 registers may share the same low-order
address, the user must always be careful to ensure that
the proper bank is selected before performing a data
read or write. For example, writing what should be
program data to an 8-bit address of F9h while the BSR
is 0Fh will end up resetting the program counter.
To ensure that commonly used registers (SFRs and
select GPRs) can be accessed in a single cycle, PIC18
devices implement an Access Bank. This is a 256-byte
memory space that provides fast access to SFRs and
the lower portion of GPR Bank 0 without using the
BSR. Section 5.3.2 “Access Bank” provides a
detailed description of the Access RAM.
While any bank can be selected, only those banks that
are actually implemented can be read or written to.
Writes to unimplemented banks are ignored, while
reads from unimplemented banks will return ‘0’s. Even
so, the STATUS register will still be affected as if the
operation was successful. The data memory map in
Figure 5-5 indicates which banks are implemented.
In the core PIC18 instruction set, only the MOVFF
instruction fully specifies the 12-bit address of the
source and target registers. This instruction ignores the
BSR completely when it executes. All other instructions
include only the low-order address as an operand and
must use either the BSR or the Access Bank to locate
their target registers.
© 2007 Microchip Technology Inc.
Preliminary
DS39682C-page 53
PIC18F45J10 FAMILY
FIGURE 5-5:
DATA MEMORY MAP FOR PIC18F24J10/44J10 DEVICES
When ‘a’ = 0:
The BSR is ignored and the
BSR<3:0>
Data Memory Map
Access Bank is used.
000h
07Fh
080h
0FFh
100h
00h
Access RAM
GPR
= 0000
= 0001
= 0010
The first 128 bytes are
general purpose RAM
(from Bank 0).
Bank 0
FFh
00h
The second 128 bytes are
Special Function Registers
(from Bank 15).
GPR
GPR
GPR
Bank 1
Bank 2
1FFh
200h
FFh
00h
FFh
00h
2FFh
300h
When ‘a’ = 1:
= 0011
The BSR specifies the Bank
used by the instruction.
Bank 3
Bank 4
Bank 5
Bank 6
Bank 7
Bank 8
Bank 9
Bank 10
Bank 11
Bank 12
Bank 13
3FFh
400h
FFh
00h
= 0100
= 0101
4FFh
500h
FFh
00h
5FFh
600h
FFh
00h
= 0110
= 0111
Access Bank
FFh
00h
6FFh
700h
00h
Access RAM Low
7Fh
80h
FFh
00h
7FFh
800h
Access RAM High
(SFRs)
= 1000
= 1001
FFh
8FFh
900h
FFh
00h
Unused
Read 00h
9FFh
A00h
FFh
00h
= 1010
= 1011
= 1100
= 1101
AFFh
B00h
FFh
00h
BFFh
C00h
FFh
00h
CFFh
D00h
FFh
00h
DFFh
E00h
FFh
00h
= 1110
= 1111
Bank 14
Bank 15
EFFh
F00h
F7Fh
F80h
FFFh
FFh
00h
Unused
SFR
FFh
DS39682C-page 54
Preliminary
© 2007 Microchip Technology Inc.
PIC18F45J10 FAMILY
FIGURE 5-6:
USE OF THE BANK SELECT REGISTER (DIRECT ADDRESSING)
Memory
Data
(2)
(1)
From Opcode
BSR
000h
100h
7
0
7
0
00h
Bank 0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
1
1
FFh
00h
Bank 1
Bank 2
(2)
Bank Select
FFh
00h
200h
300h
FFh
00h
Bank 3
through
Bank 13
FFh
00h
E00h
Bank 14
Bank 15
FFh
00h
F00h
FFFh
FFh
Note 1: The Access RAM bit of the instruction can be used to force an override of the selected bank (BSR<3:0>) to
the registers of the Access Bank.
2: The MOVFF instruction embeds the entire 12-bit address in the instruction.
however, the instruction is forced to use the Access
Bank address map; the current value of the BSR is
ignored entirely.
5.3.2
ACCESS BANK
While the use of the BSR with an embedded 8-bit
address allows users to address the entire range of
data memory, it also means that the user must always
ensure that the correct bank is selected. Otherwise,
data may be read from or written to the wrong location.
This can be disastrous if a GPR is the intended target
of an operation but an SFR is written to instead.
Verifying and/or changing the BSR for each read or
write to data memory can become very inefficient.
Using this “forced” addressing allows the instruction to
operate on a data address in a single cycle without
updating the BSR first. For 8-bit addresses of 80h and
above, this means that users can evaluate and operate
on SFRs more efficiently. The Access RAM below 80h
is a good place for data values that the user might need
to access rapidly, such as immediate computational
results or common program variables. Access RAM
also allows for faster and more code efficient context
saving and switching of variables.
To streamline access for the most commonly used data
memory locations, the data memory is configured with
an Access Bank, which allows users to access a
mapped block of memory without specifying a BSR.
The Access Bank consists of the first 128 bytes of
memory (00h-7Fh) in Bank 0 and the last 128 bytes of
memory (80h-FFh) in Block 15. The lower half is known
as the “Access RAM” and is composed of GPRs. This
upper half is also where the device’s SFRs are
mapped. These two areas are mapped contiguously in
the Access Bank and can be addressed in a linear
fashion by an 8-bit address (Figure 5-5).
The mapping of the Access Bank is slightly different
when the extended instruction set is enabled (XINST
configuration bit = 1). This is discussed in more detail
in Section 5.5.3 “Mapping the Access Bank in
Indexed Literal Offset Mode”.
5.3.3
GENERAL PURPOSE REGISTER
FILE
PIC18 devices may have banked memory in the GPR
area. This is data RAM which is available for use by all
instructions. GPRs start at the bottom of Bank 0
(address 000h) and grow upwards towards the bottom of
the SFR area. GPRs are not initialized by a Power-on
Reset and are unchanged on all other Resets.
The Access Bank is used by core PIC18 instructions
that include the Access RAM bit (the ‘a’ parameter in
the instruction). When ‘a’ is equal to ‘1’, the instruction
uses the BSR and the 8-bit address included in the
opcode for the data memory address. When ‘a’ is ‘0’,
© 2007 Microchip Technology Inc.
Preliminary
DS39682C-page 55
PIC18F45J10 FAMILY
The SFRs can be classified into two sets: those
associated with the “core” device functionality (ALU,
Resets and interrupts) and those related to the periph-
eral functions. The reset and interrupt registers are
described in their respective chapters, while the ALU’s
STATUS register is described later in this section.
Registers related to the operation of a peripheral feature
are described in the chapter for that peripheral.
5.3.4
SPECIAL FUNCTION REGISTERS
The Special Function Registers (SFRs) are registers
used by the CPU and peripheral modules for controlling
the desired operation of the device. These registers are
implemented as static RAM. SFRs start at the top of
data memory (FFFh) and extend downward to occupy
the top half of Bank 15 (F80h to FFFh). A list of these
registers is given in Table 5-1 and Table 5-2.
The SFRs are typically distributed among the
peripherals whose functions they control. Unused SFR
locations are unimplemented and read as ‘0’s.
TABLE 5-1:
Address
SPECIAL FUNCTION REGISTER MAP FOR PIC18F45J10 FAMILY DEVICES
Name
Address
Name
Address
FBFh
FBEh
Name
Address
F9Fh
Name
FFFh
FFEh
FFDh
FFCh
FFBh
FFAh
FF9h
FF8h
FF7h
FF6h
FF5h
FF4h
FF3h
FF2h
FF1h
FF0h
FEFh
TOSU
TOSH
FDFh
INDF2(1)
CCPR1H
CCPR1L
IPR1
PIR1
PIE1
FDEh POSTINC2(1)
FDDh POSTDEC2(1)
FDCh PREINC2(1)
FDBh PLUSW2(1)
F9Eh
F9Dh
F9Ch
F9Bh
F9Ah
F99h
F98h
F97h
F96h
F95h
F94h
F93h
F92h
F91h
F90h
F8Fh
F8Eh
F8Dh
F8Ch
F8Bh
F8Ah
F89h
TOSL
FBDh CCP1CON
(2)
STKPTR
PCLATU
PCLATH
PCL
FBCh
FBBh
CCPR2H
CCPR2L
—
(2)
—
(2)
FDAh
FD9h
FD8h
FD7h
FD6h
FD5h
FD4h
FD3h
FD2h
FD1h
FD0h
FCFh
FCEh
FCDh
FCCh
FCBh
FCAh
FC9h
FC8h
FSR2H
FSR2L
FBAh CCP2CON
—
(2)
(2)
FB9h
—
—
(2)
TBLPTRU
TBLPTRH
TBLPTRL
TABLAT
PRODH
PRODL
INTCON
INTCON2
INTCON3
INDF0(1)
STATUS
TMR0H
TMR0L
T0CON
FB8h BAUDCON
FB7h ECCP1DEL(3)
FB6h ECCP1AS(3)
—
(2)
—
TRISE(3)
TRISD(3)
TRISC
FB5h
FB4h
FB3h
FB2h
FB1h
FB0h
FAFh
FAEh
FADh
FACh
FABh
FAAh
FA9h
FA8h
CVRCON
CMCON
(2)
—
(2)
OSCCON
—
TRISB
(2)
(2)
—
—
TRISA
(2)
(2)
WDTCON
RCON
—
—
(2)
SPBRGH
SPBRG
RCREG
TXREG
TXSTA
—
(2)
TMR1H
TMR1L
T1CON
TMR2
—
FEEh POSTINC0(1)
FEDh POSTDEC0(1)
FECh PREINC0(1)
FEBh PLUSW0(1)
SSP2BUF
LATE(3)
LATD(3)
LATC
PR2
RCSTA
(2)
FEAh
FE9h
FE8h
FE7h
FE6h POSTINC1(1)
FE5h POSTDEC1(1)
FE4h PREINC1(1)
FE3h PLUSW1(1)
FSR0H
FSR0L
WREG
INDF1(1)
T2CON
SSP1BUF
SSP1ADD
—
LATB
(2)
—
LATA
(2)
—
F88h SSP2ADD(3)
F87h SSP2STAT(3)
F86h SSP2CON1(3)
F85h SSP2CON2(3)
FC7h SSP1STAT
FC6h SSP1CON1
FC5h SSP1CON2
FA7h EECON2(1)
FA6h
FA5h
FA4h
FA3h
FA2h
FA1h
FA0h
EECON1
IPR3
FC4h
FC3h
FC2h
FC1h
FC0h
ADRESH
ADRESL
ADCON0
ADCON1
ADCON2
PIR3
F84h
F83h
F82h
F81h
F80h
PORTE(3)
PORTD(3)
PORTC
PORTB
PIE3
FE2h
FE1h
FE0h
FSR1H
FSR1L
BSR
IPR2
PIR2
PIE2
PORTA
Note 1: This is not a physical register.
2: Unimplemented registers are read as ‘0’.
3: This register is not available in 28-pin devices.
DS39682C-page 56
Preliminary
© 2007 Microchip Technology Inc.
PIC18F45J10 FAMILY
TABLE 5-2:
File Name
TOSU
REGISTER FILE SUMMARY (PIC18F24J10/25J10/44J10/45J10)
Value on
POR, BOR on page:
Details
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
—
—
—
Top-of-Stack Upper Byte (TOS<20:16>)
---0 0000 43, 48
0000 0000 43, 48
0000 0000 43, 48
00-0 0000 43, 49
---0 0000 43, 48
0000 0000 43, 48
0000 0000 43, 48
--00 0000 43, 70
0000 0000 43, 70
0000 0000 43, 70
0000 0000 43, 70
xxxx xxxx 43, 77
xxxx xxxx 43, 77
0000 000x 43, 81
1111 -1-1 43, 82
11-0 0-00 43, 83
TOSH
Top-of-Stack High Byte (TOS<15:8>)
Top-of-Stack Low Byte (TOS<7:0>)
TOSL
STKPTR
PCLATU
PCLATH
PCL
STKFUL
—
STKUNF
—
—
—
Return Stack Pointer
Holding Register for PC<20:16>
Holding Register for PC<15:8>
PC Low Byte (PC<7:0>)
TBLPTRU
TBLPTRH
TBLPTRL
TABLAT
PRODH
PRODL
INTCON
INTCON2
INTCON3
INDF0
—
—
bit 21
Program Memory Table Pointer Upper Byte (TBLPTR<20:16>)
Program Memory Table Pointer High Byte (TBLPTR<15:8>)
Program Memory Table Pointer Low Byte (TBLPTR<7:0>)
Program Memory Table Latch
Product Register High Byte
Product Register Low Byte
GIE/GIEH
RBPU
PEIE/GIEL
INTEDG0
INT1IP
TMR0IE
INTEDG1
—
INT0IE
INTEDG2
INT2IE
RBIE
—
TMR0IF
TMR0IP
—
INT0IF
—
RBIF
RBIP
INT2IP
INT1IE
INT2IF
INT1IF
Uses contents of FSR0 to address data memory – value of FSR0 not changed (not a physical register)
N/A
N/A
N/A
N/A
N/A
43, 62
43, 62
43, 62
43, 62
43, 62
POSTINC0 Uses contents of FSR0 to address data memory – value of FSR0 post-incremented (not a physical register)
POSTDEC0 Uses contents of FSR0 to address data memory – value of FSR0 post-decremented (not a physical register)
PREINC0
PLUSW0
Uses contents of FSR0 to address data memory – value of FSR0 pre-incremented (not a physical register)
Uses contents of FSR0 to address data memory – value of FSR0 pre-incremented (not a physical register) –
value of FSR0 offset by W
FSR0H
FSR0L
WREG
INDF1
—
—
—
—
Indirect Data Memory Address Pointer 0 High Byte
---- xxxx 43, 62
xxxx xxxx 43, 62
Indirect Data Memory Address Pointer 0 Low Byte
Working Register
xxxx xxxx
N/A
43
Uses contents of FSR1 to address data memory – value of FSR1 not changed (not a physical register)
43, 62
43, 62
43, 62
43, 62
43, 62
POSTINC1 Uses contents of FSR1 to address data memory – value of FSR1 post-incremented (not a physical register)
POSTDEC1 Uses contents of FSR1 to address data memory – value of FSR1 post-decremented (not a physical register)
N/A
N/A
PREINC1
PLUSW1
Uses contents of FSR1 to address data memory – value of FSR1 pre-incremented (not a physical register)
N/A
Uses contents of FSR1 to address data memory – value of FSR1 pre-incremented (not a physical register) –
value of FSR1 offset by W
N/A
FSR1H
FSR1L
BSR
—
—
—
—
Indirect Data Memory Address Pointer 1 High Byte
---- xxxx 43, 62
xxxx xxxx 43, 62
---- 0000 43, 53
Indirect Data Memory Address Pointer 1 Low Byte
—
—
—
—
Bank Select Register
INDF2
Uses contents of FSR2 to address data memory – value of FSR2 not changed (not a physical register)
N/A
N/A
N/A
N/A
N/A
44, 62
44, 62
44, 62
44, 62
44, 62
POSTINC2 Uses contents of FSR2 to address data memory – value of FSR2 post-incremented (not a physical register)
POSTDEC2 Uses contents of FSR2 to address data memory – value of FSR2 post-decremented (not a physical register)
PREINC2
PLUSW2
Uses contents of FSR2 to address data memory – value of FSR2 pre-incremented (not a physical register)
Uses contents of FSR2 to address data memory – value of FSR2 pre-incremented (not a physical register) –
value of FSR2 offset by W
FSR2H
FSR2L
STATUS
—
—
—
—
Indirect Data Memory Address Pointer 2 High Byte
---- xxxx 44, 62
xxxx xxxx 44, 62
---x xxxx 44, 60
Indirect Data Memory Address Pointer 2 Low Byte
—
—
—
N
OV
Z
DC
C
Legend:
Note 1:
2:
x= unknown, u= unchanged, -= unimplemented, q= value depends on condition
See Section 4.4 “Brown-out Reset (BOR) (PIC18F2X1X/4X1X Devices Only)”.
These registers and/or bits are not implemented on 28-pin devices and are read as ‘0’. Reset values are shown for 40/44-pin devices;
individual unimplemented bits should be interpreted as ‘-’.
© 2007 Microchip Technology Inc.
Preliminary
DS39682C-page 57
PIC18F45J10 FAMILY
TABLE 5-2:
REGISTER FILE SUMMARY (PIC18F24J10/25J10/44J10/45J10) (CONTINUED)
Value on
POR, BOR on page:
Details
File Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
TMR0H
TMR0L
T0CON
OSCCON
WDTCON
RCON
Timer0 Register High Byte
Timer0 Register Low Byte
0000 0000 44, 113
xxxx xxxx 44, 113
1111 1111 44, 111
0--- q-00 28, 44
--- ---0 44, 235
0--1 11q0 38, 42, 90
xxxx xxxx 44, 119
xxxx xxxx 44, 119
TMR0ON
IDLEN
—
T08BIT
—
T0CS
—
T0SE
—
PSA
OSTS
—
T0PS2
—
T0PS1
SCS1
—
T0PS0
SCS0
—
—
—
—
SWDTEN
BOR(1)
IPEN
—
—
RI
TO
PD
POR
TMR1H
TMR1L
T1CON
TMR2
Timer1 Register High Byte
Timer1 Register Low Byte
RD16
T1RUN
T1CKPS1
T1CKPS0
T1OSCEN
T1SYNC
TMR2ON
TMR1CS
T2CKPS1
TMR1ON 0000 0000 44, 115
0000 0000 44, 122
Timer2 Register
PR2
Timer2 Period Register
T2OUTPS3 T2OUTPS2 T2OUTPS1 T2OUTPS0
MSSP1 Receive Buffer/Transmit Register
1111 1111 44, 122
T2CON
SSP1BUF
SSP1ADD
—
T2CKPS0 -000 0000 44, 121
xxxx xxxx 44, 154
MSSP1 Address Register in I2C™ Slave mode. MSSP1 Baud Rate Reload Register in I2C Master mode.
0000 0000 44, 155
SSP1STAT
SMP
WCOL
GCEN
CKE
D/A
P
S
R/W
SSPM2
PEN
UA
BF
0000 0000 44, 146,
156
SSP1CON1
SSPOV
SSPEN
ACKDT
CKP
SSPM3
RCEN
SSPM1
RSEN
SSPM0
SEN
0000 0000 44, 147,
157
SSP1CON2
ADRESH
ADRESL
ACKSTAT
ACKEN
0000 0000 44, 158
xxxx xxxx 44, 218
xxxx xxxx 44, 218
A/D Result Register High Byte
A/D Result Register Low Byte
ADCON0
ADCON1
ADCON2
CCPR1H
CCPR1L
ADCAL
—
—
—
—
CHS3
VCFG1
ACQT2
CHS2
VCFG0
ACQT1
CHS1
PCFG3
ACQT0
CHS0
PCFG2
ADCS2
GO/DONE
PCFG1
ADON
PCFG0
ADCS0
0-00 0000 44, 209
--00 0qqq 44, 210
0-00 0000 44, 211
xxxx xxxx 45, 124
xxxx xxxx 45, 124
ADFM
ADCS1
Capture/Compare/PWM Register 1 High Byte
Capture/Compare/PWM Register 1 Low Byte
CCP1CON
CCPR2H
CCPR2L
P1M1(2)
P1M0(2)
DC1B1
DC1B0
CCP1M3
CCP1M2
CCP1M1
CCP1M0 0000 0000 45, 123,
xxxx xxxx 45, 124
Capture/Compare/PWM Register 2 High Byte
Capture/Compare/PWM Register 2 Low Byte
xxxx xxxx 45, 124
CCP2CON
BAUDCON
ECCP1DEL
ECCP1AS
CVRCON
CMCON
—
—
DC2B1
—
PDC5(2)
ECCPAS1
CVRR
DC2B0
SCKP
PDC4(2)
ECCPAS0
CVRSS
C1INV
CCP2M3
BRG16
PDC3(2)
PSSAC1
CVR3
CCP2M2
—
PDC2(2)
PSSAC0
CVR2
CM2
CCP2M1
WUE
PDC1(2)
CCP2M0 --00 0000 45, 123
ABDOVF
PRSEN
ECCPASE
CVREN
C2OUT
RCIDL
ABDEN
PDC0(2)
01-0 0-00 45, 190
PDC6(2)
ECCPAS2
CVROE
C1OUT
0000 0000 45, 140
PSSBD1(2) PSSBD0(2) 0000 0000 45, 141
CVR1
CM1
CVR0
CM0
0000 0000 45, 225
0000 0111 45, 219
C2INV
CIS
Legend:
Note 1:
2:
x= unknown, u= unchanged, -= unimplemented, q= value depends on condition
See Section 4.4 “Brown-out Reset (BOR) (PIC18F2X1X/4X1X Devices Only)”.
These registers and/or bits are not implemented on 28-pin devices and are read as ‘0’. Reset values are shown for 40/44-pin devices;
individual unimplemented bits should be interpreted as ‘-’.
DS39682C-page 58
Preliminary
© 2007 Microchip Technology Inc.
PIC18F45J10 FAMILY
TABLE 5-2:
REGISTER FILE SUMMARY (PIC18F24J10/25J10/44J10/45J10) (CONTINUED)
Value on
POR, BOR on page:
Details
File Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
SPBRGH
SPBRG
RCREG
TXREG
TXSTA
RCSTA
EECON2
EECON1
IPR3
EUSART Baud Rate Generator Register High Byte
EUSART Baud Rate Generator Register Low Byte
EUSART Receive Register
0000 0000 45, 192
0000 0000 45, 192
0000 0000 45, 199
xxxx xxxx 45, 197
0000 0010 45, 188
0000 000x 45, 189
0000 0000 45, 68
---0 x00- 45, 69
11-- ---- 45, 89
00-- ---- 45, 85
00-- ---- 45, 87
11-- 1--1 45, 89
00-- 0--0 45, 85
00-- 0--0 45, 87
1111 1111 45, 88
0000 0000 45, 84
0000 0000 45, 86
1111 -111 46, 107
1111 1111 46, 103
1111 1111 46, 100
1111 1111 46, 97
--1- 1111 46, 94
xxxx xxxx 46, 154
---- -xxx 46, 106
EUSART Transmit Register
CSRC
SPEN
TX9
RX9
TXEN
SREN
SYNC
CREN
SENDB
ADDEN
BRGH
FERR
TRMT
OERR
TX9D
RX9D
EEPROM Control Register 2 (not a physical register)
—
—
—
—
FREE
WRERR
—
WREN
—
WR
—
—
SSP2IP
SSP2IF
SSP2IE
OSCFIP
OSCFIF
OSCFIE
PSPIP(2)
PSPIF(2)
PSPIE(2)
IBF
BCL2IP
BCL2IF
BCL2IE
CMIP
CMIF
CMIE
ADIP
—
—
—
PIR3
—
—
—
—
—
PIE3
—
—
—
—
—
—
IPR2
—
—
BCL1IP
BCL1IF
BCL1IE
SSP1IP
SSP1IF
SSP1IE
—
—
—
CCP2IP
CCP2IF
CCP2IE
TMR1IP
TMR1IF
TMR1IE
TRISE0
PIR2
—
—
—
—
PIE2
—
—
—
—
IPR1
RCIP
RCIF
RCIE
IBOV
TXIP
TXIF
TXIE
PSPMODE
CCP1IP
CCP1IF
CCP1IE
TRISE2
TMR2IP
TMR2IF
TMR2IE
TRISE1
PIR1
ADIF
PIE1
ADIE
TRISE(2)
TRISD(2)
TRISC
TRISB
TRISA
SSP2BUF
LATE(2)
OBF
PORTD Data Direction Control Register
PORTC Data Direction Control Register
PORTB Data Direction Control Register
—
—
TRISA5
—
—
TRISA3
—
TRISA2
TRISA1
TRISA0
MSSP2 Receive Buffer/Transmit Register
—
—
—
PORTE Data Latch Register
(Read and Write to Data Latch)
LATD(2)
LATC
PORTD Data Latch Register (Read and Write to Data Latch)
PORTC Data Latch Register (Read and Write to Data Latch)
PORTB Data Latch Register (Read and Write to Data Latch)
xxxx xxxx 46, 103
xxxx xxxx 46, 100
xxxx xxxx 46, 97
--xx xxxx 46, 94
0000 0000 46, 154
LATB
LATA
—
—
PORTA Data Latch Register (Read and Write to Data Latch)
SSP2ADD
SSP2STAT
MSSP2 Address Register in I2C™ Slave mode. MSSP2 Baud Rate Reload Register in I2C Master mode.
SMP
CKE
D/A
P
S
R/W
UA
BF
0000 0000 46, 146,
156
SSP2CON1
WCOL
SSPOV
SSPEN
CKP
SSPM3
SSPM2
SSPM1
SSPM0
0000 0000 46, 147,
157
SSP2CON2
PORTE(2)
PORTD(2)
PORTC
GCEN
—
ACKSTAT
—
ACKDT
—
ACKEN
—
RCEN
—
PEN
RE2(2)
RD2
RSEN
RE1(2)
RD1
SEN
RE0(2)
RD0
0000 0000 46, 158
---- -xxx 46, 106
xxxx xxxx 46, 103
xxxx xxxx 46, 100
xxxx xxxx 46, 97
--0- 0000 46, 94
RD7
RC7
RB7
—
RD6
RC6
RB6
—
RD5
RC5
RB5
RA5
RD4
RC4
RB4
—
RD3
RC3
RB3
RA3
RC2
RC1
RC0
PORTB
RB2
RB1
RB0
PORTA
RA2
RA1
RA0
Legend:
Note 1:
2:
x= unknown, u= unchanged, -= unimplemented, q= value depends on condition
See Section 4.4 “Brown-out Reset (BOR) (PIC18F2X1X/4X1X Devices Only)”.
These registers and/or bits are not implemented on 28-pin devices and are read as ‘0’. Reset values are shown for 40/44-pin devices;
individual unimplemented bits should be interpreted as ‘-’.
© 2007 Microchip Technology Inc.
Preliminary
DS39682C-page 59
PIC18F45J10 FAMILY
It is recommended that only BCF, BSF, SWAPF, MOVFF
and MOVWFinstructions are used to alter the STATUS
register, because these instructions do not affect the Z,
C, DC, OV or N bits in the STATUS register.
5.3.5
STATUS REGISTER
The STATUS register, shown in Register 5-2, contains
the arithmetic status of the ALU. As with any other SFR,
it can be the operand for any instruction.
For other instructions that do not affect Status bits, see
the instruction set summaries in Table 21-2 and
Table 21-3.
If the STATUS register is the destination for an instruc-
tion that affects the Z, DC, C, OV or N bits, the results
of the instruction are not written; instead, the STATUS
register is updated according to the instruction
performed. Therefore, the result of an instruction with
the STATUS register as its destination may be different
than intended. As an example, CLRF STATUSwill set
the Z bit and leave the remaining status bits unchanged
(‘000u u1uu’).
Note:
The C and DC bits operate as the borrow
and digit borrow bits, respectively, in
subtraction.
REGISTER 5-2:
STATUS REGISTER
U-0
—
U-0
—
U-0
—
R/W-x
R/W-x
OV
R/W-x
Z
R/W-x
DC
R/W-x
C
N
bit 7
bit 0
bit 7-5
bit 4
Unimplemented: Read as ‘0’
N: Negative bit
This bit is used for signed arithmetic (2’s complement). It indicates whether the result was
negative (ALU MSB = 1).
1= Result was negative
0= Result was positive
bit 3
OV: Overflow bit
This bit is used for signed arithmetic (2’s complement). It indicates an overflow of the 7-bit
magnitude which causes the sign bit (bit 7 of the result) to change state.
1= Overflow occurred for signed arithmetic (in this arithmetic operation)
0= No overflow occurred
bit 2
bit 1
Z: Zero bit
1= The result of an arithmetic or logic operation is zero
0= The result of an arithmetic or logic operation is not zero
DC: Digit Carry/borrow bit
For ADDWF, ADDLW, SUBLWand SUBWFinstructions:
1= A carry-out from the 4th low-order bit of the result occurred
0= No carry-out from the 4th low-order bit of the result
Note:
For borrow, the polarity is reversed. A subtraction is executed by adding the 2’s
complement of the second operand. For rotate (RRF, RLF) instructions, this bit is
loaded with either bit 4 or bit 3 of the source register.
bit 0
C: Carry/borrow bit
For ADDWF, ADDLW, SUBLWand SUBWFinstructions:
1= A carry-out from the Most Significant bit of the result occurred
0= No carry-out from the Most Significant bit of the result occurred
Note:
For borrow, the polarity is reversed. A subtraction is executed by adding the 2’s
complement of the second operand. For rotate (RRF, RLF) instructions, this bit is
loaded with either the high or low-order bit of the source register.
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
DS39682C-page 60
Preliminary
© 2007 Microchip Technology Inc.
PIC18F45J10 FAMILY
The Access RAM bit ‘a’ determines how the address is
interpreted. When ‘a’ is ‘1’, the contents of the BSR
(Section 5.3.1 “Bank Select Register (BSR)”) are
used with the address to determine the complete 12-bit
address of the register. When ‘a’ is ‘0’, the address is
interpreted as being a register in the Access Bank.
Addressing that uses the Access RAM is sometimes
also known as Direct Forced Addressing mode.
5.4
Data Addressing Modes
Note:
The execution of some instructions in the
core PIC18 instruction set are changed
when the PIC18 extended instruction set is
enabled. See Section 5.5 “Data Memory
and the Extended Instruction Set” for
more information.
A few instructions, such as MOVFF, include the entire
12-bit address (either source or destination) in their
opcodes. In these cases, the BSR is ignored entirely.
While the program memory can be addressed in only
one way – through the program counter – information
in the data memory space can be addressed in several
ways. For most instructions, the addressing mode is
fixed. Other instructions may use up to three modes,
depending on which operands are used and whether or
not the extended instruction set is enabled.
The destination of the operation’s results is determined
by the destination bit ‘d’. When ‘d’ is ‘1’, the results are
stored back in the source register, overwriting its origi-
nal contents. When ‘d’ is ‘0’, the results are stored in
the W register. Instructions without the ‘d’ argument
have a destination that is implicit in the instruction; their
destination is either the target register being operated
on or the W register.
The addressing modes are:
• Inherent
• Literal
• Direct
5.4.3
INDIRECT ADDRESSING
• Indirect
Indirect addressing allows the user to access a location
in data memory without giving a fixed address in the
instruction. This is done by using File Select Registers
(FSRs) as pointers to the locations to be read or written
to. Since the FSRs are themselves located in RAM as
Special File Registers, they can also be directly manip-
ulated under program control. This makes FSRs very
useful in implementing data structures, such as tables
and arrays in data memory.
An additional addressing mode, Indexed Literal Offset,
is available when the extended instruction set is
enabled (XINST configuration bit = 1). Its operation is
discussed in greater detail in Section 5.5.1 “Indexed
Addressing with Literal Offset”.
5.4.1
INHERENT AND LITERAL
ADDRESSING
Many PIC18 control instructions do not need any
argument at all; they either perform an operation that
globally affects the device or they operate implicitly on
one register. This addressing mode is known as Inherent
Addressing. Examples include SLEEP, RESETand DAW.
The registers for indirect addressing are also
implemented with Indirect File Operands (INDFs) that
permit automatic manipulation of the pointer value with
auto-incrementing, auto-decrementing or offsetting
with another value. This allows for efficient code, using
loops, such as the example of clearing an entire RAM
bank in Example 5-5.
Other instructions work in a similar way but require an
additional explicit argument in the opcode. This is
known as Literal Addressing mode because they
require some literal value as an argument. Examples
include ADDLWand MOVLW, which respectively, add or
move a literal value to the W register. Other examples
include CALL and GOTO, which include a 20-bit
program memory address.
EXAMPLE 5-5:
HOW TO CLEAR RAM
(BANK 1) USING
INDIRECT ADDRESSING
LFSR
FSR0, 100h
;
NEXT
CLRF
POSTINC0
; Clear INDF
; register then
; inc pointer
; All done with
; Bank1?
5.4.2
DIRECT ADDRESSING
Direct addressing specifies all or part of the source
and/or destination address of the operation within the
opcode itself. The options are specified by the
arguments accompanying the instruction.
BTFSS
BRA
FSR0H, 1
NEXT
; NO, clear next
; YES, continue
CONTINUE
In the core PIC18 instruction set, bit-oriented and byte-
oriented instructions use some version of direct
addressing by default. All of these instructions include
some 8-bit literal address as their Least Significant
Byte. This address specifies either a register address in
one of the banks of data RAM (Section 5.3.3 “General
Purpose Register File”) or a location in the Access
Bank (Section 5.3.2 “Access Bank”) as the data
source for the instruction.
© 2007 Microchip Technology Inc.
Preliminary
DS39682C-page 61
PIC18F45J10 FAMILY
5.4.3.1
FSR Registers and the INDF
Operand
5.4.3.2
FSR Registers and POSTINC,
POSTDEC, PREINC and PLUSW
At the core of indirect addressing are three sets of reg-
isters: FSR0, FSR1 and FSR2. Each represents a pair
of 8-bit registers, FSRnH and FSRnL. The four upper
bits of the FSRnH register are not used, so each FSR
pair holds a 12-bit value. This represents a value that
can address the entire range of the data memory in a
linear fashion. The FSR register pairs, then, serve as
pointers to data memory locations.
In addition to the INDF operand, each FSR register pair
also has four additional indirect operands. Like INDF,
these are “virtual” registers that cannot be indirectly
read or written to. Accessing these registers actually
accesses the associated FSR register pair, but also
performs a specific action on it stored value. They are:
• POSTDEC: accesses the FSR value, then
automatically decrements it by 1 afterwards
Indirect addressing is accomplished with a set of
Indirect File Operands, INDF0 through INDF2. These
can be thought of as “virtual” registers; they are
mapped in the SFR space but are not physically imple-
mented. Reading or writing to a particular INDF register
actually accesses its corresponding FSR register pair.
A read from INDF1, for example, reads the data at the
address indicated by FSR1H:FSR1L. Instructions that
use the INDF registers as operands actually use the
contents of their corresponding FSR as a pointer to the
instruction’s target. The INDF operand is just a
convenient way of using the pointer.
• POSTINC: accesses the FSR value, then
automatically increments it by 1 afterwards
• PREINC: increments the FSR value by 1, then
uses it in the operation
• PLUSW: adds the signed value of the W register
(range of -127 to 128) to that of the FSR and uses
the new value in the operation.
In this context, accessing an INDF register uses the
value in the FSR registers without changing them. Sim-
ilarly, accessing a PLUSW register gives the FSR value
offset by that in the W register; neither value is actually
changed in the operation. Accessing the other virtual
registers changes the value of the FSR registers.
Because indirect addressing uses a full 12-bit address,
data RAM banking is not necessary. Thus, the current
contents of the BSR and the Access RAM bit have no
effect on determining the target address.
Operations on the FSRs with POSTDEC, POSTINC
and PREINC affect the entire register pair; that is, roll-
overs of the FSRnL register, from FFh to 00h, carry
over to the FSRnH register. On the other hand, results
of these operations do not change the value of any
flags in the STATUS register (e.g., Z, N, OV, etc.).
FIGURE 5-7:
INDIRECT ADDRESSING
000h
Using an instruction with one of the
indirect addressing registers as the
operand....
Bank 0
Bank 1
ADDWF, INDF1, 1
100h
200h
300h
Bank 2
FSR1H:FSR1L
...uses the 12-bit address stored in
the FSR pair associated with that
register....
7
0
7
0
Bank 3
through
Bank 13
x x x x 1 1 1 0
1 1 0 0 1 1 0 0
...to determine the data memory
location to be used in that operation.
E00h
In this case, the FSR1 pair contains
ECCh. This means the contents of
location ECCh will be added to that
of the W register and stored back in
ECCh.
Bank 14
Bank 15
F00h
FFFh
Data Memory
DS39682C-page 62
Preliminary
© 2007 Microchip Technology Inc.
PIC18F45J10 FAMILY
The PLUSW register can be used to implement a form
of indexed addressing in the data memory space. By
manipulating the value in the W register, users can
reach addresses that are fixed offsets from pointer
addresses. In some applications, this can be used to
implement some powerful program control structure,
such as software stacks, inside of data memory.
5.5.1
INDEXED ADDRESSING WITH
LITERAL OFFSET
Enabling the PIC18 extended instruction set changes
the behavior of indirect addressing using the FSR2
register pair within Access RAM. Under the proper
conditions, instructions that use the Access Bank – that
is, most bit-oriented and byte-oriented instructions –
can invoke a form of indexed addressing using an
offset specified in the instruction. This special address-
ing mode is known as Indexed Addressing with Literal
Offset, or Indexed Literal Offset mode.
5.4.3.3
Operations by FSRs on FSRs
Indirect addressing operations that target other FSRs
or virtual registers represent special cases. For exam-
ple, using an FSR to point to one of the virtual registers
will not result in successful operations. As a specific
case, assume that FSR0H:FSR0L contains FE7h, the
address of INDF1. Attempts to read the value of the
INDF1 using INDF0 as an operand will return 00h.
Attempts to write to INDF1 using INDF0 as the operand
will result in a NOP.
When using the extended instruction set, this
addressing mode requires the following:
• The use of the Access Bank is forced (‘a’ = 0) and
• The file address argument is less than or equal to
5Fh.
Under these conditions, the file address of the instruc-
tion is not interpreted as the lower byte of an address
(used with the BSR in direct addressing), or as an 8-bit
address in the Access Bank. Instead, the value is
interpreted as an offset value to an address pointer,
specified by FSR2. The offset and the contents of
FSR2 are added to obtain the target address of the
operation.
On the other hand, using the virtual registers to write to
an FSR pair may not occur as planned. In these cases,
the value will be written to the FSR pair but without any
incrementing or decrementing. Thus, writing to INDF2
or POSTDEC2 will write the same value to the
FSR2H:FSR2L.
Since the FSRs are physical registers mapped in the
SFR space, they can be manipulated through all direct
operations. Users should proceed cautiously when
working on these registers, particularly if their code
uses indirect addressing.
5.5.2
INSTRUCTIONS AFFECTED BY
INDEXED LITERAL OFFSET MODE
Any of the core PIC18 instructions that can use direct
addressing are potentially affected by the Indexed
Literal Offset Addressing mode. This includes all
byte-oriented and bit-oriented instructions, or almost
one-half of the standard PIC18 instruction set.
Instructions that only use Inherent or Literal Addressing
modes are unaffected.
Similarly, operations by indirect addressing are gener-
ally permitted on all other SFRs. Users should exercise
the appropriate caution that they do not inadvertently
change settings that might affect the operation of the
device.
Additionally, byte-oriented and bit-oriented instructions
are not affected if they do not use the Access Bank
(Access RAM bit is ‘1’), or include a file address of 60h
or above. Instructions meeting these criteria will
continue to execute as before. A comparison of the
different possible addressing modes when the
extended instruction set is enabled in shown in
Figure 5-8.
5.5
Data Memory and the Extended
Instruction Set
Enabling the PIC18 extended instruction set (XINST
configuration bit = 1) significantly changes certain
aspects of data memory and its addressing. Specifi-
cally, the use of the Access Bank for many of the core
PIC18 instructions is different; this is due to the
introduction of a new addressing mode for the data
memory space.
Those who desire to use byte-oriented or bit-oriented
instructions in the Indexed Literal Offset mode should
note the changes to assembler syntax for this mode.
This is described in more detail in Section 21.2.1
“Extended Instruction Syntax”.
What does not change is just as important. The size of
the data memory space is unchanged, as well as its
linear addressing. The SFR map remains the same.
Core PIC18 instructions can still operate in both Direct
and Indirect Addressing mode; inherent and literal
instructions do not change at all. Indirect addressing
with FSR0 and FSR1 also remain unchanged.
© 2007 Microchip Technology Inc.
Preliminary
DS39682C-page 63
PIC18F45J10 FAMILY
FIGURE 5-8:
COMPARING ADDRESSING OPTIONS FOR BIT-ORIENTED AND
BYTE-ORIENTED INSTRUCTIONS (EXTENDED INSTRUCTION SET ENABLED)
Example Instruction: ADDWF, f, d, a (Opcode: 0010 01da ffff ffff)
000h
When ‘a’ = 0 and f ≥ 60h:
The instruction executes in
Direct Forced mode. ‘f’ is inter-
060h
080h
Bank 0
preted as a location in the
Access RAM between 060h
and 0FFh. This is the same as
locations 060h to 07Fh
(Bank 0) and F80h to FFFh
(Bank 15) of data memory.
100h
00h
Bank 1
through
Bank 14
60h
80h
Valid range
for ‘f’
FFh
F00h
Access RAM
Locations below 60h are not
available in this addressing
mode.
Bank 15
SFRs
F80h
FFFh
Data Memory
When ‘a’ = 0 and f ≤ 5Fh:
000h
080h
100h
Bank 0
The instruction executes in
Indexed Literal Offset mode. ‘f’
is interpreted as an offset to the
address value in FSR2. The
two are added together to
obtain the address of the target
register for the instruction. The
address can be anywhere in
the data memory space.
001001da ffffffff
Bank 1
through
Bank 14
FSR2H
FSR2L
F00h
F80h
Note that in this mode, the
correct syntax is now:
ADDWF [k], d
Bank 15
SFRs
where ‘k’ is the same as ‘f’.
FFFh
Data Memory
BSR
000h
080h
100h
00000000
When ‘a’ = 1 (all values of f):
Bank 0
The instruction executes in
Direct mode (also known as
Direct Long mode). ‘f’ is inter-
preted as a location in one of
the 16 banks of the data
memory space. The bank is
designated by the Bank Select
Register (BSR). The address
can be in any implemented
bank in the data memory
space.
001001da ffffffff
Bank 1
through
Bank 14
F00h
F80h
Bank 15
SFRs
FFFh
Data Memory
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Preliminary
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Remapping of the Access Bank applies only to opera-
tions using the Indexed Literal Offset mode. Operations
that use the BSR (Access RAM bit is ‘1’) will continue
to use direct addressing as before.
5.5.3
MAPPING THE ACCESS BANK IN
INDEXED LITERAL OFFSET MODE
The use of Indexed Literal Offset Addressing mode
effectively changes how the first 96 locations of Access
RAM (00h to 5Fh) are mapped. Rather than containing
just the contents of the bottom half of Bank 0, this mode
maps the contents from Bank 0 and a user-defined
“window” that can be located anywhere in the data
memory space. The value of FSR2 establishes the
lower boundary of the addresses mapped into the
window, while the upper boundary is defined by FSR2
plus 95 (5Fh). Addresses in the Access RAM above
5Fh are mapped as previously described (see
Section 5.3.2 “Access Bank”). An example of Access
Bank remapping in this addressing mode is shown in
Figure 5-9.
5.6
PIC18 Instruction Execution and
the Extended Instruction Set
Enabling the extended instruction set adds eight
additional commands to the existing PIC18 instruction
set. These instructions are executed as described in
Section 21.2 “Extended Instruction Set”.
FIGURE 5-9:
REMAPPING THE ACCESS BANK WITH INDEXED LITERAL OFFSET
ADDRESSING
Example Situation:
ADDWF f, d, a
000h
05Fh
07Fh
Bank 0
Bank 0
FSR2H:FSR2L = 120h
Locations in the region
from the FSR2 pointer
(120h) to the pointer plus
05Fh (17Fh) are mapped
to the bottom of the
Access RAM (000h-05Fh).
100h
120h
17Fh
Bank 1
Window
00h
Bank 1
Bank 1 “Window”
200h
5Fh
Locations in Bank 0 from
060h to 07Fh are mapped,
as usual, to the middle half
of the Access Bank.
Bank 0
7Fh
80h
Bank 2
through
Bank 14
SFRs
Special File Registers at
F80h through FFFh are
mapped to 80h through
FFh, as usual.
FFh
Access Bank
F00h
Bank 15
SFRs
Bank 0 addresses below
5Fh can still be addressed
by using the BSR.
F80h
FFFh
Data Memory
© 2007 Microchip Technology Inc.
Preliminary
DS39682C-page 65
PIC18F45J10 FAMILY
NOTES:
DS39682C-page 66
Preliminary
© 2007 Microchip Technology Inc.
PIC18F45J10 FAMILY
6.1
Table Reads and Table Writes
6.0
FLASH PROGRAM MEMORY
In order to read and write program memory, there are
two operations that allow the processor to move bytes
between the program memory space and the data RAM:
The Flash program memory is readable, writable and
erasable during normal operation over the entire VDD
range.
• Table Read (TBLRD)
• Table Write (TBLWT)
A read from program memory is executed on one byte
at a time. A write to program memory is executed on
blocks of 64 bytes at a time. Program memory is
erased in blocks of 1024 bytes at a time. A bulk erase
operation may not be issued from user code.
The program memory space is 16 bits wide, while the
data RAM space is 8 bits wide. Table reads and table
writes move data between these two memory spaces
through an 8-bit register (TABLAT).
Writing or erasing program memory will cease
instruction fetches until the operation is complete. The
program memory cannot be accessed during the write
or erase; therefore, code cannot execute. An internal
programming timer terminates program memory writes
and erases.
Table read operations retrieve data from program
memory and place it into the data RAM space.
Figure 6-1 shows the operation of a table read with
program memory and data RAM.
Table write operations store data from the data memory
space into holding registers in program memory. The
procedure to write the contents of the holding registers
into program memory is detailed in Section 6.5 “Writing
to Flash Program Memory”. Figure 6-2 shows the
operation of a table write with program memory and data
RAM.
A value written to program memory does not need to be
a valid instruction. Executing a program memory
location that forms an invalid instruction results in a
NOP.
Table operations work with byte entities. A table block
containing data, rather than program instructions, is not
required to be word aligned. Therefore, a table block can
start and end at any byte address. If a table write is being
used to write executable code into program memory,
program instructions will need to be word aligned.
FIGURE 6-1:
TABLE READ OPERATION
Instruction: TBLRD*
Program Memory
(1)
Table Pointer
Table Latch (8-bit)
TABLAT
TBLPTRU TBLPTRH TBLPTRL
Program Memory
(TBLPTR)
Note 1: Table Pointer register points to a byte in program memory.
© 2007 Microchip Technology Inc.
Preliminary
DS39682C-page 67
PIC18F45J10 FAMILY
FIGURE 6-2:
TABLE WRITE OPERATION
Instruction: TBLWT*
Program Memory
Holding Registers
(1)
Table Pointer
Table Latch (8-bit)
TABLAT
TBLPTRU TBLPTRH TBLPTRL
Program Memory
(TBLPTR)
Note 1: Table Pointer actually points to one of 64 holding registers, the address of which is determined by
TBLPTRL<5:0>. The process for physically writing data to the program memory array is discussed in
Section 6.5 “Writing to Flash Program Memory”.
The WREN bit, when set, will allow a write operation.
On power-up, the WREN bit is clear. The WRERR bit is
set in hardware when the WR bit is set and cleared
when the internal programming timer expires and the
write operation is complete.
6.2
Control Registers
Several control registers are used in conjunction with
the TBLRDand TBLWTinstructions. These include the:
• EECON1 register
• EECON2 register
• TABLAT register
• TBLPTR registers
Note:
During normal operation, the WRERR is
read as ‘1’. This can indicate that a write
operation was prematurely terminated by
a
Reset, or
a write operation was
6.2.1
EECON1 AND EECON2 REGISTERS
attempted improperly.
The EECON1 register (Register 6-1) is the control
register for memory accesses. The EECON2 register is
not a physical register; it is used exclusively in the
memory write and erase sequences. Reading
EECON2 will read all ‘0’s.
The WR control bit initiates write operations. The bit
cannot be cleared, only set, in software; it is cleared in
hardware at the completion of the write operation.
The FREE bit, when set, will allow a program memory
erase operation. When FREE is set, the erase
operation is initiated on the next WR command. When
FREE is clear, only writes are enabled.
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REGISTER 6-1:
EECON1: DATA EEPROM CONTROL REGISTER 1
U-0
—
U-0
—
U-0
—
R/W-0
FREE
R/W-x
R/W-0
WREN
R/S-0
WR
U-0
—
WRERR
bit 7
bit 0
bit 7-5
bit 4
Unimplemented: Read as ‘0’
FREE: Flash Row Erase Enable bit
1= Erase the program memory row addressed by TBLPTR on the next WR command
(cleared by completion of erase operation)
0= Perform write only
bit 3
WRERR: Flash Program/Data EEPROM Error Flag bit
1= A write operation is prematurely terminated (any Reset during self-timed programming in
normal operation, or an improper write attempt)
0= The write operation completed
bit 2
bit 1
WREN: Flash Program/Data EEPROM Write Enable bit
1= Allows write cycles to Flash program/data EEPROM
0= Inhibits write cycles to Flash program/data EEPROM
WR: Write Control bit
1= Initiates a data EEPROM erase/write cycle or a program memory erase cycle or write cycle.
(The operation is self-timed and the bit is cleared by hardware once write is complete.
The WR bit can only be set (not cleared) in software.)
0= Write cycle to the EEPROM is complete
bit 0
Unimplemented: Read as ‘0’
Legend:
R = Readable bit
W = Writable bit
S = Bit can be set by software, but not cleared U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
© 2007 Microchip Technology Inc.
Preliminary
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PIC18F45J10 FAMILY
6.2.2
TABLAT – TABLE LATCH REGISTER
6.2.4
TABLE POINTER BOUNDARIES
The Table Latch (TABLAT) is an 8-bit register mapped
into the SFR space. The Table Latch register is used to
hold 8-bit data during data transfers between program
memory and data RAM.
TBLPTR is used in reads, writes and erases of the
Flash program memory.
When a TBLRDis executed, all 22 bits of the TBLPTR
determine which byte is read from program memory
into TABLAT.
6.2.3
TBLPTR – TABLE POINTER
REGISTER
When a TBLWTis executed, the six LSbs of the Table
Pointer register (TBLPTR<5:0>) determine which of the
64 program memory holding registers is written to.
When the timed write to program memory begins (via
the WR bit), the 16 MSbs of the TBLPTR
(TBLPTR<21:6>) determine which program memory
block of 64 bytes is written to. For more detail, see
Section 6.5 “Writing to Flash Program Memory”.
The Table Pointer (TBLPTR) register addresses a byte
within the program memory. The TBLPTR is comprised
of three SFR registers: Table Pointer Upper Byte, Table
Pointer High Byte and Table Pointer Low Byte
(TBLPTRU:TBLPTRH:TBLPTRL). These three regis-
ters join to form a 22-bit wide pointer. The low-order
21 bits allow the device to address up to 2 Mbytes of
program memory space. The 22nd bit allows access to
the device ID, the user ID and the configuration bits.
When an erase of program memory is executed, the
7 MSbs of the Table Pointer register (TBLPTR<21:10>)
point to the 1024-byte block that will be erased. The
Least Significant bits (TBLPTR<9:0>) are ignored.
The Table Pointer register, TBLPTR, is used by the
TBLRDand TBLWTinstructions. These instructions can
update the TBLPTR in one of four ways based on the
table operation. These operations are shown in
Table 6-1. These operations on the TBLPTR only affect
the low-order 21 bits.
Figure 6-3 describes the relevant boundaries of
TBLPTR based on Flash program memory operations.
TABLE 6-1:
Example
TABLE POINTER OPERATIONS WITH TBLRD AND TBLWT INSTRUCTIONS
Operation on Table Pointer
TBLRD*
TBLWT*
TBLPTR is not modified
TBLRD*+
TBLWT*+
TBLPTR is incremented after the read/write
TBLPTR is decremented after the read/write
TBLPTR is incremented before the read/write
TBLRD*-
TBLWT*-
TBLRD+*
TBLWT+*
FIGURE 6-3:
TABLE POINTER BOUNDARIES BASED ON OPERATION
21
16 15
TBLPTRH
8
7
TBLPTRL
0
TBLPTRU
Table Erase
TBLPTR<21:10>
Table Write
TBLPTR<21:6>
Table Write
TBLPTR<5:0>
Table Read – TBLPTR<21:0>
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Preliminary
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TBLPTR points to a byte address in program space.
Executing TBLRD places the byte pointed to into
TABLAT. In addition, TBLPTR can be modified
automatically for the next table read operation.
6.3
Reading the Flash Program
Memory
The TBLRD instruction is used to retrieve data from
program memory and places it into data RAM. Table
reads from program memory are performed one byte at
a time.
The internal program memory is typically organized by
words. The Least Significant bit of the address selects
between the high and low bytes of the word. Figure 6-4
shows the interface between the internal program
memory and the TABLAT.
FIGURE 6-4:
READS FROM FLASH PROGRAM MEMORY
Program Memory
(Even Byte Address)
(Odd Byte Address)
TBLPTR = xxxxx1
TBLPTR = xxxxx0
Instruction Register
TABLAT
Read Register
FETCH
TBLRD
(IR)
EXAMPLE 6-1:
READING A FLASH PROGRAM MEMORY WORD
MOVLW
CODE_ADDR_UPPER
TBLPTRU
CODE_ADDR_HIGH
TBLPTRH
CODE_ADDR_LOW
TBLPTRL
; Load TBLPTR with the base
; address of the word
MOVWF
MOVLW
MOVWF
MOVLW
MOVWF
READ_WORD
TBLRD*+
MOVF
MOVWF
TBLRD*+
MOVFW
MOVF
; read into TABLAT and increment
; get data
TABLAT, W
WORD_EVEN
; read into TABLAT and increment
; get data
TABLAT, W
WORD_ODD
© 2007 Microchip Technology Inc.
Preliminary
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6.4.1
FLASH PROGRAM MEMORY
ERASE SEQUENCE
6.4
Erasing Flash Program Memory
The minimum erase block is 1024 bytes. Only through
the use of an external programmer, or through ICSP
control, can larger blocks of program memory be bulk
erased. Word erase in the Flash array is not supported.
The sequence of events for erasing a block of internal
program memory location is:
1. Load Table Pointer register with address of row
being erased.
When initiating an erase sequence from the micro-
controller itself, a block of 1024 bytes of program
memory is erased. The Most Significant 7 bits of the
TBLPTR<21:10> point to the block being erased.
TBLPTR<9:0> are ignored.
2. Set the EECON1 register for the erase operation:
• set WREN bit to enable writes;
• set FREE bit to enable the erase.
3. Disable interrupts.
The EECON1 register commands the erase operation.
The WREN bit must be set to enable write operations.
The FREE bit is set to select an erase operation.
4. Write 55h to EECON2.
5. Write 0AAh to EECON2.
6. Set the WR bit. This will begin the row erase
cycle.
For protection, the write initiate sequence for EECON2
must be used.
7. The CPU will stall for duration of the erase
(about 2 ms using internal timer).
A long write is necessary for erasing the internal Flash.
Instruction execution is halted while in a long write
cycle. The long write will be terminated by the internal
programming timer.
8. Re-enable interrupts.
EXAMPLE 6-2:
ERASING A FLASH PROGRAM MEMORY ROW
MOVLW
MOVWF
MOVLW
MOVWF
MOVLW
MOVWF
CODE_ADDR_UPPER
TBLPTRU
CODE_ADDR_HIGH
TBLPTRH
CODE_ADDR_LOW
TBLPTRL
; load TBLPTR with the base
; address of the memory block
ERASE_ROW
BSF
BSF
BCF
MOVLW
MOVWF
MOVLW
MOVWF
BSF
EECON1, WREN
EECON1, FREE
INTCON, GIE
55h
EECON2
0AAh
EECON2
EECON1, WR
INTCON, GIE
; enable write to memory
; enable Row Erase operation
; disable interrupts
Required
Sequence
; write 55h
; write 0AAh
; start erase (CPU stall)
; re-enable interrupts
BSF
DS39682C-page 72
Preliminary
© 2007 Microchip Technology Inc.
PIC18F45J10 FAMILY
The EEPROM on-chip timer controls the write time.
The write/erase voltages are generated by an on-chip
charge pump, rated to operate over the voltage range
of the device.
6.5
Writing to Flash Program Memory
The minimum programming block is 32 words or
64 bytes. Word or byte programming is not supported.
Table writes are used internally to load the holding
registers needed to program the Flash memory. There
are 64 holding registers used by the table writes for
programming.
Note:
Unlike previous devices, the PIC18F45J10
family of devices does not reset the holding
registers after a write occurs. The holding
registers must be cleared or overwritten
before a programming sequence.
Since the Table Latch (TABLAT) is only a single byte, the
TBLWTinstruction may need to be executed 64 times for
each programming operation. All of the table write
operations will essentially be short writes because only
the holding registers are written. At the end of updating
the 64 holding registers, the EECON1 register must be
written to in order to start the programming operation
with a long write.
In order to maintain the endurance of the
cells, each Flash byte should not be
programmed more then twice between
erase operations. Either a bulk or row
erase of the target row is required before
attempting to modify the contents a third
time.
The long write is necessary for programming the inter-
nal Flash. Instruction execution is halted while in a long
write cycle. The long write will be terminated by the
internal programming timer.
FIGURE 6-5:
TABLE WRITES TO FLASH PROGRAM MEMORY
TABLAT
Write Register
8
8
8
8
TBLPTR = xxxxx0
TBLPTR = xxxxx1
TBLPTR = xxxxx2
TBLPTR = xxxx3F
Holding Register
Holding Register
Holding Register
Holding Register
Program Memory
5. Write 55h to EECON2.
6. Write 0AAh to EECON2.
6.5.1
FLASH PROGRAM MEMORY WRITE
SEQUENCE
7. Set the WR bit. This will begin the write cycle.
The sequence of events for programming an internal
program memory location should be:
8. The CPU will stall for duration of the write (about
2 ms using internal timer).
1. If the section of program memory to be written to
has been programmed previously, then the
memory will need to be erased before the write
occurs (see 6.4.1 “Flash Program Memory
Erase Sequence”).
9. Re-enable interrupts.
10. Verify the memory (table read).
An example of the required code is shown in
Example 6-3.
2. Write the 64 bytes into the holding registers with
auto-increment.
Note:
Before setting the WR bit, the Table
Pointer address needs to be within the
intended address range of the 64 bytes in
the holding register.
3. Set the EECON1 register for the write operation:
• set WREN to enable byte writes.
4. Disable interrupts.
© 2007 Microchip Technology Inc.
Preliminary
DS39682C-page 73
PIC18F45J10 FAMILY
EXAMPLE 6-3:
WRITING TO FLASH PROGRAM MEMORY
MOVLW
MOVWF
MOVLW
MOVWF
MOVLW
MOVWF
CODE_ADDR_UPPER
TBLPTRU
CODE_ADDR_HIGH
TBLPTRH
CODE_ADDR_LOW
TBLPTRL
; Load TBLPTR with the base
; address of the memory block
ERASE_BLOCK
BSF
BSF
BCF
EECON1, WREN
EECON1, FREE
INTCON, GIE
55h
EECON2
0AAh
; enable write to memory
; enable Row Erase operation
; disable interrupts
MOVLW
MOVWF
MOVLW
MOVWF
BSF
BSF
MOVLW
MOVWF
; write 55h
EECON2
; write 0AAh
; start erase (CPU stall)
; re-enable interrupts
EECON1, WR
INTCON, GIE
D'16'
WRITE_COUNTER
; Need to write 16 blocks of 64 to write
; one erase block of 1024
RESTART_BUFFER
MOVLW
MOVWF
MOVLW
MOVWF
MOVLW
MOVWF
D'64'
COUNTER
BUFFER_ADDR_HIGH
FSR0H
BUFFER_ADDR_LOW
FSR0L
; point to buffer
FILL_BUFFER
...
; read the new data from I2C, SPI,
; PSP, USART, etc.
WRITE_BUFFER
MOVLW
MOVWF
D’64
COUNTER
; number of bytes in holding register
WRITE_BYTE_TO_HREGS
MOVFF
MOVWF
TBLWT+*
POSTINC0, WREG
TABLAT
; get low byte of buffer data
; present data to table latch
; write data, perform a short write
; to internal TBLWT holding register.
; loop until buffers are full
DECFSZ COUNTER
BRA WRITE_WORD_TO_HREGS
PROGRAM_MEMORY
BSF
BCF
EECON1, WREN
INTCON, GIE
55h
EECON2
0AAh
; enable write to memory
; disable interrupts
MOVLW
MOVWF
MOVLW
MOVWF
BSF
Required
Sequence
; write 55h
EECON2
; write 0AAh
EECON1, WR
INTCON, GIE
EECON1, WREN
; start program (CPU stall)
; re-enable interrupts
; disable write to memory
BSF
BCF
DECFSZ WRITE_COUNTER
BRA RESTART_BUFFER
; done with one write cycle
; if not done replacing the erase block
DS39682C-page 74
Preliminary
© 2007 Microchip Technology Inc.
PIC18F45J10 FAMILY
6.5.2
WRITE VERIFY
6.5.4
PROTECTION AGAINST
SPURIOUS WRITES
Depending on the application, good programming
practice may dictate that the value written to the
memory should be verified against the original value.
This should be used in applications where excessive
writes can stress bits near the specification limit.
To protect against spurious writes to Flash program
memory, the write initiate sequence must also be
followed. See Section 20.0 “Special Features of the
CPU” for more detail.
6.5.3
UNEXPECTED TERMINATION OF
WRITE OPERATION
6.6
Flash Program Operation During
Code Protection
If a write is terminated by an unplanned event, such as
loss of power or an unexpected Reset, the memory
location just programmed should be verified and repro-
grammed if needed. If the write operation is interrupted
by a MCLR Reset or a WDT Time-out Reset during
normal operation, the user can check the WRERR bit
and rewrite the location(s) as needed.
See Section 20.6 “Program Verification and Code
Protection” for details on code protection of Flash
program memory.
TABLE 6-2:
Name
REGISTERS ASSOCIATED WITH PROGRAM FLASH MEMORY
Reset
Valueson
page
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
TBLPTRU
—
—
bit 21 Program Memory Table Pointer Upper Byte (TBLPTR<20:16>)
43
43
43
43
43
45
45
45
45
45
TBPLTRH Program Memory Table Pointer High Byte (TBLPTR<15:8>)
TBLPTRL Program Memory Table Pointer Low Byte (TBLPTR<7:0>)
TABLAT
INTCON
Program Memory Table Latch
GIE/GIEH PEIE/GIEL TMR0IE INT0IE
RBIE
TMR0IF
INT0IF
RBIF
EECON2 EEPROM Control Register 2 (not a physical register)
EECON1
IPR2
—
—
—
—
—
—
FREE
—
WRERR
BCL1IP
BCL1IF
BCL1IE
WREN
—
WR
—
—
OSCFIP
OSCFIF
OSCFIE
CMIP
CMIF
CMIE
CCP2IP
CCP2IF
CCP2IE
PIR2
—
—
—
PIE2
—
—
—
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used during Flash/EEPROM access.
© 2007 Microchip Technology Inc.
Preliminary
DS39682C-page 75
PIC18F45J10 FAMILY
NOTES:
DS39682C-page 76
Preliminary
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EXAMPLE 7-1:
8 x 8 UNSIGNED
MULTIPLY ROUTINE
7.0
7.1
8 x 8 HARDWARE MULTIPLIER
Introduction
MOVF
MULWF
ARG1, W
ARG2
;
; ARG1 * ARG2 ->
; PRODH:PRODL
All PIC18 devices include an 8 x 8 hardware multiplier
as part of the ALU. The multiplier performs an unsigned
operation and yields a 16-bit result that is stored in the
product register pair, PRODH:PRODL. The multiplier’s
operation does not affect any flags in the STATUS
register.
EXAMPLE 7-2:
8 x 8 SIGNED MULTIPLY
ROUTINE
Making multiplication a hardware operation allows it to
be completed in a single instruction cycle. This has the
advantages of higher computational throughput and
reduced code size for multiplication algorithms and
allows the PIC18 devices to be used in many applica-
tions previously reserved for digital signal processors.
A comparison of various hardware and software
multiply operations, along with the savings in memory
and execution time, is shown in Table 7-1.
MOVF
MULWF
ARG1, W
ARG2
; ARG1 * ARG2 ->
; PRODH:PRODL
; Test Sign Bit
; PRODH = PRODH
BTFSC
SUBWF
ARG2, SB
PRODH, F
;
- ARG1
MOVF
BTFSC
SUBWF
ARG2, W
ARG1, SB
PRODH, F
; Test Sign Bit
; PRODH = PRODH
;
- ARG2
7.2
Operation
Example 7-1 shows the instruction sequence for an 8 x 8
unsigned multiplication. Only one instruction is required
when one of the arguments is already loaded in the
WREG register.
Example 7-2 shows the sequence to do an 8 x 8 signed
multiplication. To account for the sign bits of the
arguments, each argument’s Most Significant bit (MSb)
is tested and the appropriate subtractions are done.
TABLE 7-1:
Routine
PERFORMANCE COMPARISON FOR VARIOUS MULTIPLY OPERATIONS
Program
Memory
(Words)
Time
Cycles
(Max)
Multiply Method
@ 40 MHz @ 10 MHz @ 4 MHz
Without hardware multiply
Hardware multiply
13
1
69
1
6.9 μs
100 ns
9.1 μs
600 ns
24.2 μs
2.8 μs
25.4 μs
4.0 μs
27.6 μs
400 ns
36.4 μs
2.4 μs
69 μs
1 μs
8 x 8 unsigned
8 x 8 signed
Without hardware multiply
Hardware multiply
33
6
91
6
91 μs
6 μs
Without hardware multiply
Hardware multiply
21
28
52
35
242
28
254
40
96.8 μs
11.2 μs
102.6 μs
16.0 μs
242 μs
28 μs
254 μs
40 μs
16 x 16 unsigned
16 x 16 signed
Without hardware multiply
Hardware multiply
© 2007 Microchip Technology Inc.
Preliminary
DS39682C-page 77
PIC18F45J10 FAMILY
Example 7-3 shows the sequence to do a 16 x 16
unsigned multiplication. Equation 7-1 shows the
algorithm that is used. The 32-bit result is stored in four
registers (RES3:RES0).
EQUATION 7-2:
16 x 16 SIGNED
MULTIPLICATION
ALGORITHM
RES3:RES0 = ARG1H:ARG1L • ARG2H:ARG2L
16
= (ARG1H • ARG2H • 2 ) +
(ARG1H • ARG2L • 2 ) +
(ARG1L • ARG2H • 2 ) +
(ARG1L • ARG2L) +
(-1 • ARG2H<7> • ARG1H:ARG1L • 2 ) +
(-1 • ARG1H<7> • ARG2H:ARG2L • 2
8
EQUATION 7-1:
16 x 16 UNSIGNED
MULTIPLICATION
ALGORITHM
8
16
RES3:RES0
=
=
ARG1H:ARG1L • ARG2H:ARG2L
16
)
16
(ARG1H • ARG2H • 2 ) +
8
(ARG1H • ARG2L • 2 ) +
8
(ARG1L • ARG2H • 2 ) +
EXAMPLE 7-4:
16 x 16 SIGNED
MULTIPLY ROUTINE
(ARG1L • ARG2L)
MOVF
MULWF
ARG1L, W
ARG2L
; ARG1L * ARG2L ->
; PRODH:PRODL
;
;
EXAMPLE 7-3:
16 x 16 UNSIGNED
MULTIPLY ROUTINE
MOVFF
MOVFF
PRODH, RES1
PRODL, RES0
MOVF
MULWF
ARG1L, W
ARG2L
; ARG1L * ARG2L->
; PRODH:PRODL
;
;
;
;
MOVF
MULWF
ARG1H, W
ARG2H
MOVFF
MOVFF
PRODH, RES1
PRODL, RES0
; ARG1H * ARG2H ->
; PRODH:PRODL
;
;
;
;
MOVFF
MOVFF
PRODH, RES3
PRODL, RES2
MOVF
MULWF
ARG1H, W
ARG2H
; ARG1H * ARG2H->
; PRODH:PRODL
;
;
MOVF
MULWF
ARG1L, W
ARG2H
MOVFF
MOVFF
PRODH, RES3
PRODL, RES2
; ARG1L * ARG2H ->
; PRODH:PRODL
;
; Add cross
; products
;
;
;
MOVF
ADDWF
MOVF
ADDWFC RES2, F
CLRF WREG
ADDWFC RES3, F
PRODL, W
RES1, F
PRODH, W
MOVF
MULWF
ARG1L, W
ARG2H
; ARG1L * ARG2H->
; PRODH:PRODL
;
; Add cross
; products
;
;
;
MOVF
ADDWF
MOVF
PRODL, W
RES1, F
PRODH, W
;
ADDWFC RES2, F
CLRF WREG
ADDWFC RES3, F
MOVF
MULWF
ARG1H, W
ARG2L
;
; ARG1H * ARG2L ->
; PRODH:PRODL
;
; Add cross
; products
;
;
;
;
MOVF
ADDWF
MOVF
ADDWFC RES2, F
CLRF WREG
ADDWFC RES3, F
PRODL, W
RES1, F
PRODH, W
MOVF
MULWF
ARG1H, W
ARG2L
;
; ARG1H * ARG2L->
; PRODH:PRODL
;
; Add cross
; products
MOVF
ADDWF
MOVF
PRODL, W
RES1, F
PRODH, W
;
;
ADDWFC RES2, F
CLRF WREG
ADDWFC RES3, F
;
;
;
BTFSS
BRA
MOVF
SUBWF
MOVF
ARG2H, 7
SIGN_ARG1
ARG1L, W
RES2
; ARG2H:ARG2L neg?
; no, check ARG1
;
;
;
Example 7-4 shows the sequence to do a 16 x 16
signed multiply. Equation 7-2 shows the algorithm
used. The 32-bit result is stored in four registers
(RES3:RES0). To account for the sign bits of the
arguments, the MSb for each argument pair is tested
and the appropriate subtractions are done.
ARG1H, W
SUBWFB RES3
SIGN_ARG1
BTFSS
BRA
ARG1H, 7
CONT_CODE
ARG2L, W
RES2
; ARG1H:ARG1L neg?
; no, done
;
;
;
MOVF
SUBWF
MOVF
ARG2H, W
SUBWFB RES3
;
CONT_CODE
:
DS39682C-page 78
Preliminary
© 2007 Microchip Technology Inc.
PIC18F45J10 FAMILY
When the IPEN bit is cleared (default state), the
interrupt priority feature is disabled and interrupts are
compatible with PIC® mid-range devices. In
Compatibility mode, the interrupt priority bits for each
source have no effect. INTCON<6> is the PEIE bit
which enables/disables all peripheral interrupt sources.
INTCON<7> is the GIE bit which enables/disables all
interrupt sources. All interrupts branch to address
0008h in Compatibility mode.
8.0
INTERRUPTS
Members of the PIC18F45J10 family of devices have
multiple interrupt sources and an interrupt priority fea-
ture that allows most interrupt sources to be assigned
a high priority level or a low priority level. The high
priority interrupt vector is at 0008h and the low priority
interrupt vector is at 0018h. High priority interrupt
events will interrupt any low priority interrupts that may
be in progress.
When an interrupt is responded to, the global interrupt
enable bit is cleared to disable further interrupts. If the
IPEN bit is cleared, this is the GIE bit. If interrupt priority
levels are used, this will be either the GIEH or GIEL bit.
High priority interrupt sources can interrupt a low
priority interrupt. Low priority interrupts are not
processed while high priority interrupts are in progress.
There are thirteen registers which are used to control
interrupt operation. These registers are:
• RCON
• INTCON
• INTCON2
• INTCON3
The return address is pushed onto the stack and the
PC is loaded with the interrupt vector address (0008h
or 0018h). Once in the Interrupt Service Routine, the
source(s) of the interrupt can be determined by polling
the interrupt flag bits. The interrupt flag bits must be
cleared in software before re-enabling interrupts to
avoid recursive interrupts.
• PIR1, PIR2, PIR3
• PIE1, PIE2, PIE3
• IPR1, IPR2, IPR3
It is recommended that the Microchip header files
supplied with MPLAB® IDE be used for the symbolic bit
names in these registers. This allows the
assembler/compiler to automatically take care of the
placement of these bits within the specified register.
The “return from interrupt” instruction, RETFIE, exits
the interrupt routine and sets the GIE bit (GIEH or GIEL
if priority levels are used) which re-enables interrupts.
In general, interrupt sources have three bits to control
their operation. They are:
For external interrupt events, such as the INT pins or
the PORTB input change interrupt, the interrupt latency
will be three to four instruction cycles. The exact
latency is the same for one or two-cycle instructions.
Individual interrupt flag bits are set regardless of the
status of their corresponding enable bit or the GIE bit.
• Flag bit to indicate that an interrupt event
occurred
• Enable bit that allows program execution to
branch to the interrupt vector address when the
flag bit is set
Note:
Do not use the MOVFFinstruction to modify
any of the interrupt control registers while
any interrupt is enabled. Doing so may
cause erratic microcontroller behavior.
• Priority bit to select high priority or low priority
The interrupt priority feature is enabled by setting the
IPEN bit (RCON<7>). When interrupt priority is
enabled, there are two bits which enable interrupts
globally. Setting the GIEH bit (INTCON<7>) enables all
interrupts that have the priority bit set (high priority).
Setting the GIEL bit (INTCON<6>) enables all
interrupts that have the priority bit cleared (low priority).
When the interrupt flag, enable bit and appropriate
global interrupt enable bit are set, the interrupt will
vector immediately to address 0008h or 0018h,
depending on the priority bit setting. Individual
interrupts can be disabled through their corresponding
enable bits.
© 2007 Microchip Technology Inc.
Preliminary
DS39682C-page 79
PIC18F45J10 FAMILY
FIGURE 8-1:
PIC18F24J10/25J10/44J10/45J10 INTERRUPT LOGIC
Wake-up if in
Idle or Sleep modes
TMR0IF
TMR0IE
TMR0IP
RBIF
RBIE
RBIP
INT0IF
INT0IE
INT1IF
INT1IE
INT1IP
INT2IF
INT2IE
INT2IP
Interrupt to CPU
Vector to Location
0008h
PIR1<7:0>
PIE1<7:0>
IPR1<7:0>
GIE/GIEH
PIR2<7:6, 3, 0>
PIE2<7:6, 3, 0>
IPR2<7:6, 3, 0>
IPEN
PIR3<7:6>
PIE3<7:6>
IPR3<7:6>
IPEN
PEIE/GIEL
IPEN
High Priority Interrupt Generation
Low Priority Interrupt Generation
PIR1<7:0>
PIE1<7:0>
IPR1<7:0>
PIR2<7:6, 3, 0>
PIE2<7:6, 3, 0>
IPR2<7:6, 3, 0>
Interrupt to CPU
Vector to Location
0018h
TMR0IF
TMR0IE
TMR0IP
IPEN
PIR3<7:6>
PIE3<7:6>
IPR3<7:6>
RBIF
RBIE
RBIP
GIE/GIEH
PEIE/GIEL
INT1IF
INT1IE
INT1IP
INT2IF
INT2IE
INT2IP
DS39682C-page 80
Preliminary
© 2007 Microchip Technology Inc.
PIC18F45J10 FAMILY
8.1
INTCON Registers
Note:
Interrupt flag bits are set when an interrupt
condition occurs regardless of the state of
its corresponding enable bit or the global
interrupt enable bit. User software should
ensure the appropriate interrupt flag bits
are clear prior to enabling an interrupt.
This feature allows for software polling.
The INTCON registers are readable and writable
registers which contain various enable, priority and flag
bits.
REGISTER 8-1:
INTCON: INTERRUPT CONTROL REGISTER
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
RBIE
R/W-0
R/W-0
INT0IF
R/W-x
RBIF
GIE/GIEH PEIE/GIEL TMR0IE
bit 7
INT0IE
TMR0IF
bit 0
bit 7
GIE/GIEH: Global Interrupt Enable bit
When IPEN = 0:
1= Enables all unmasked interrupts
0= Disables all interrupts
When IPEN = 1:
1= Enables all high priority interrupts
0= Disables all interrupts
bit 6
PEIE/GIEL: Peripheral Interrupt Enable bit
When IPEN = 0:
1= Enables all unmasked peripheral interrupts
0= Disables all peripheral interrupts
When IPEN = 1:
1= Enables all low priority peripheral interrupts
0= Disables all low priority peripheral interrupts
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
TMR0IE: TMR0 Overflow Interrupt Enable bit
1= Enables the TMR0 overflow interrupt
0= Disables the TMR0 overflow interrupt
INT0IE: INT0 External Interrupt Enable bit
1= Enables the INT0 external interrupt
0= Disables the INT0 external interrupt
RBIE: RB Port Change Interrupt Enable bit
1= Enables the RB port change interrupt
0= Disables the RB port change interrupt
TMR0IF: TMR0 Overflow Interrupt Flag bit
1= TMR0 register has overflowed (must be cleared in software)
0= TMR0 register did not overflow
INT0IF: INT0 External Interrupt Flag bit
1= The INT0 external interrupt occurred (must be cleared in software)
0= The INT0 external interrupt did not occur
RBIF: RB Port Change Interrupt Flag bit
1= At least one of the RB7:RB4 pins changed state (must be cleared in software)
0= None of the RB7:RB4 pins have changed state
Note:
A mismatch condition will continue to set this bit. Reading PORTB will end the
mismatch condition and allow the bit to be cleared.
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
© 2007 Microchip Technology Inc.
Preliminary
DS39682C-page 81
PIC18F45J10 FAMILY
REGISTER 8-2:
INTCON2: INTERRUPT CONTROL REGISTER 2
R/W-1
RBPU
R/W-1
R/W-1
R/W-1
U-0
—
R/W-1
U-0
—
R/W-1
RBIP
INTEDG0 INTEDG1 INTEDG2
TMR0IP
bit 7
bit 0
bit 7
bit 6
bit 5
bit 4
RBPU: PORTB Pull-up Enable bit
1= All PORTB pull-ups are disabled
0= PORTB pull-ups are enabled by individual port latch values
INTEDG0: External Interrupt 0 Edge Select bit
1= Interrupt on rising edge
0= Interrupt on falling edge
INTEDG1: External Interrupt 1 Edge Select bit
1= Interrupt on rising edge
0= Interrupt on falling edge
INTEDG2: External Interrupt 2 Edge Select bit
1= Interrupt on rising edge
0= Interrupt on falling edge
bit 3
bit 2
Unimplemented: Read as ‘0’
TMR0IP: TMR0 Overflow Interrupt Priority bit
1= High priority
0= Low priority
bit 1
bit 0
Unimplemented: Read as ‘0’
RBIP: RB Port Change Interrupt Priority bit
1= High priority
0= Low priority
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
Note:
Interrupt flag bits are set when an interrupt condition occurs regardless of the state
of its corresponding enable bit or the global interrupt enable bit. User software should
ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. This
feature allows for software polling.
DS39682C-page 82
Preliminary
© 2007 Microchip Technology Inc.
PIC18F45J10 FAMILY
REGISTER 8-3:
INTCON3: INTERRUPT CONTROL REGISTER 3
R/W-1
R/W-1
U-0
—
R/W-0
R/W-0
U-0
—
R/W-0
INT2IF
R/W-0
INT1IF
INT2IP
INT1IP
INT2IE
INT1IE
bit 7
bit 0
bit 7
bit 6
INT2IP: INT2 External Interrupt Priority bit
1= High priority
0= Low priority
INT1IP: INT1 External Interrupt Priority bit
1= High priority
0= Low priority
bit 5
bit 4
Unimplemented: Read as ‘0’
INT2IE: INT2 External Interrupt Enable bit
1= Enables the INT2 external interrupt
0= Disables the INT2 external interrupt
bit 3
INT1IE: INT1 External Interrupt Enable bit
1= Enables the INT1 external interrupt
0= Disables the INT1 external interrupt
bit 2
bit 1
Unimplemented: Read as ‘0’
INT2IF: INT2 External Interrupt Flag bit
1= The INT2 external interrupt occurred (must be cleared in software)
0= The INT2 external interrupt did not occur
bit 0
INT1IF: INT1 External Interrupt Flag bit
1= The INT1 external interrupt occurred (must be cleared in software)
0= The INT1 external interrupt did not occur
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
Note:
Interrupt flag bits are set when an interrupt condition occurs regardless of the state
of its corresponding enable bit or the global interrupt enable bit. User software
should ensure the appropriate interrupt flag bits are clear prior to enabling an
interrupt. This feature allows for software polling.
© 2007 Microchip Technology Inc.
Preliminary
DS39682C-page 83
PIC18F45J10 FAMILY
8.2
PIR Registers
Note 1: Interrupt flag bits are set when an interrupt
condition occurs regardless of the state of
its corresponding enable bit or the Global
Interrupt Enable bit, GIE (INTCON<7>).
The PIR registers contain the individual flag bits for the
peripheral interrupts. Due to the number of peripheral
interrupt sources, there are three Peripheral Interrupt
Request (Flag) registers (PIR1, PIR2, PIR3).
2: User software should ensure the
appropriate interrupt flag bits are cleared
prior to enabling an interrupt and after
servicing that interrupt.
REGISTER 8-4:
PIR1: PERIPHERAL INTERRUPT REQUEST (FLAG) REGISTER 1
R/W-0
PSPIF(1)
bit 7
R/W-0
ADIF
R-0
R-0
R/W-0
R/W-0
R/W-0
R/W-0
RCIF
TXIF
SSP1IF
CCP1IF
TMR2IF
TMR1IF
bit 0
bit 7
PSPIF: Parallel Slave Port Read/Write Interrupt Flag bit(1)
1= A read or a write operation has taken place (must be cleared in software)
0= No read or write has occurred
Note:
This bit is not implemented on 28-pin devices and should be read as ‘0’.
bit 6
bit 5
bit 4
bit 3
bit 2
ADIF: A/D Converter Interrupt Flag bit
1= An A/D conversion completed (must be cleared in software)
0= The A/D conversion is not complete
RCIF: EUSART Receive Interrupt Flag bit
1= The EUSART receive buffer, RCREG, is full (cleared when RCREG is read)
0= The EUSART receive buffer is empty
TXIF: EUSART Transmit Interrupt Flag bit
1= The EUSART transmit buffer, TXREG, is empty (cleared when TXREG is written)
0= The EUSART transmit buffer is full
SSP1IF: Master Synchronous Serial Port 1 Interrupt Flag bit
1= The transmission/reception is complete (must be cleared in software)
0= Waiting to transmit/receive
CCP1IF: ECCP1/CCP1 Interrupt Flag bit
Capture mode:
1= A TMR1 register capture occurred (must be cleared in software)
0= No TMR1 register capture occurred
Compare mode:
1= A TMR1 register compare match occurred (must be cleared in software)
0= No TMR1 register compare match occurred
PWM mode:
Unused in this mode.
bit 1
bit 0
TMR2IF: TMR2 to PR2 Match Interrupt Flag bit
1= TMR2 to PR2 match occurred (must be cleared in software)
0= No TMR2 to PR2 match occurred
TMR1IF: TMR1 Overflow Interrupt Flag bit
1= TMR1 register overflowed (must be cleared in software)
0= TMR1 register did not overflow
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
DS39682C-page 84
Preliminary
© 2007 Microchip Technology Inc.
PIC18F45J10 FAMILY
REGISTER 8-5:
PIR2: PERIPHERAL INTERRUPT REQUEST (FLAG) REGISTER 2
R/W-0
OSCFIF
bit 7
R/W-0
CMIF
U-0
—
U-0
—
R/W-0
U-0
—
U-0
—
R/W-0
BCL1IF
CCP2IF
bit 0
bit 7
bit 6
OSCFIF: Oscillator Fail Interrupt Flag bit
1= Device oscillator failed, clock input has changed to INTOSC (must be cleared in software)
0= Device clock operating
CMIF: Comparator Interrupt Flag bit
1= Comparator input has changed (must be cleared in software)
0= Comparator input has not changed
bit 5-4 Unimplemented: Read as ‘0’
bit 3
BCL1IF: Bus Collision Interrupt Flag bit (MSSP1 module)
1= A bus collision occurred (must be cleared in software)
0= No bus collision occurred
bit 2-1 Unimplemented: Read as ‘0’
bit 0
CCP2IF: CCP2 Interrupt Flag bit
Capture mode:
1= A TMR1 register capture occurred (must be cleared in software)
0= No TMR1 register capture occurred
Compare mode:
1= A TMR1 register compare match occurred (must be cleared in software)
0= No TMR1 register compare match occurred
PWM mode:
Unused in this mode.
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
REGISTER 8-6:
PIR3: PERIPHERAL INTERRUPT REQUEST (FLAG) REGISTER 3
R/W-0
R/W-0
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
SSP2IF
BCL2IF
bit 7
bit 0
bit 7
bit 6
SSP2IF: Master Synchronous Serial Port 2 Interrupt Flag bit
1= The transmission/reception is complete (must be cleared in software)
0= Waiting to transmit/receive
BCL2IF: Bus Collision Interrupt Flag bit (MSSP2 module)
1= A bus collision occurred (must be cleared in software)
0= No bus collision occurred
bit 5-0 Unimplemented: Read as ‘0’
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
U = Unimplemented bit, read as ‘0’
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
© 2007 Microchip Technology Inc.
Preliminary
DS39682C-page 85
PIC18F45J10 FAMILY
8.3
PIE Registers
The PIE registers contain the individual enable bits for
the peripheral interrupts. Due to the number of
peripheral interrupt sources, there are three Peripheral
Interrupt Enable registers (PIE1, PIE2, PIE3). When
IPEN = 0, the PEIE bit must be set to enable any of
these peripheral interrupts.
REGISTER 8-7:
PIE1: PERIPHERAL INTERRUPT ENABLE REGISTER 1
R/W-0
PSPIE(1)
bit 7
R/W-0
ADIE
R/W-0
RCIE
R/W-0
TXIE
R/W-0
R/W-0
R/W-0
R/W-0
TMR1IE
bit 0
SSP1IE
CCP1IE
TMR2IE
bit 7
PSPIE: Parallel Slave Port Read/Write Interrupt Enable bit(1)
1= Enables the PSP read/write interrupt
0= Disables the PSP read/write interrupt
Note:
This bit is not implemented on 28-pin devices and should be read as ‘0’.
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
ADIE: A/D Converter Interrupt Enable bit
1= Enables the A/D interrupt
0= Disables the A/D interrupt
RCIE: EUSART Receive Interrupt Enable bit
1= Enables the EUSART receive interrupt
0= Disables the EUSART receive interrupt
TXIE: EUSART Transmit Interrupt Enable bit
1= Enables the EUSART transmit interrupt
0= Disables the EUSART transmit interrupt
SSP1IE: Master Synchronous Serial Port 1 Interrupt Enable bit
1= Enables the MSSP1 interrupt
0= Disables the MSSP1 interrupt
CCP1IE: ECCP1/CCP1 Interrupt Enable bit
1= Enables the ECCP1/CCP1 interrupt
0= Disables the ECCP1/CCP1 interrupt
TMR2IE: TMR2 to PR2 Match Interrupt Enable bit
1= Enables the TMR2 to PR2 match interrupt
0= Disables the TMR2 to PR2 match interrupt
TMR1IE: TMR1 Overflow Interrupt Enable bit
1= Enables the TMR1 overflow interrupt
0= Disables the TMR1 overflow interrupt
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
DS39682C-page 86
Preliminary
© 2007 Microchip Technology Inc.
PIC18F45J10 FAMILY
REGISTER 8-8:
PIE2: PERIPHERAL INTERRUPT ENABLE REGISTER 2
R/W-0
OSCFIE
bit 7
R/W-0
CMIE
U-0
—
U-0
—
R/W-0
U-0
—
U-0
—
R/W-0
BCL1IE
CCP2IE
bit 0
bit 7
bit 6
OSCFIE: Oscillator Fail Interrupt Enable bit
1= Enabled
0= Disabled
CMIE: Comparator Interrupt Enable bit
1= Enabled
0= Disabled
bit 5-4
bit 3
Unimplemented: Read as ‘0’
BCL1IE: Bus Collision Interrupt Enable bit (MSSP1 module)
1= Enabled
0= Disabled
bit 2-1
bit 0
Unimplemented: Read as ‘0’
CCP2IE: CCP2 Interrupt Enable bit
1= Enabled
0= Disabled
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
REGISTER 8-9:
PIE3: PERIPHERAL INTERRUPT ENABLE REGISTER 3
R/W-0
R/W-0
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
SSP2IE
BCL2IE
bit 7
bit 0
bit 7
bit 6
SSP2IE: Master Synchronous Serial Port 2 Interrupt Enable bit
1= Enabled
0= Disabled
BCL2IE: Bus Collision Interrupt Enable bit (MSSP2 module)
1= Enabled
0= Disabled
bit 5-0 Unimplemented: Read as ‘0’
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
‘1’ = Bit is set
© 2007 Microchip Technology Inc.
Preliminary
DS39682C-page 87
PIC18F45J10 FAMILY
8.4
IPR Registers
The IPR registers contain the individual priority bits for
the peripheral interrupts. Due to the number of
peripheral interrupt sources, there are three Peripheral
Interrupt Priority registers (IPR1, IPR2, IPR3). Using
the priority bits requires that the Interrupt Priority
Enable (IPEN) bit be set.
REGISTER 8-10: IPR1: PERIPHERAL INTERRUPT PRIORITY REGISTER 1
R/W-1
PSPIP(1)
bit 7
R/W-1
ADIP
R/W-1
RCIP
R/W-1
TXIP
R/W-1
R/W-1
R/W-1
R/W-1
TMR1IP
bit 0
SSP1IP
CCP1IP
TMR2IP
bit 7
PSPIP: Parallel Slave Port Read/Write Interrupt Priority bit(1)
1= High priority
0= Low priority
Note:
This bit is not implemented on 28-pin devices and should be read as ‘0’.
bit 6
bit 5
bit 4
ADIP: A/D Converter Interrupt Priority bit
1= High priority
0= Low priority
RCIP: EUSART Receive Interrupt Priority bit
1= High priority
0= Low priority
TXIP: EUSART Transmit Interrupt Priority bit
1= High priority
0= Low priority
bit 3
bit 2
bit 1
bit 0
SSP1IP: Master Synchronous Serial Port 1 Interrupt Priority bit
1= High priority
0= Low priority
CCP1IP: ECCP1/CCP1 Interrupt Priority bit
1= High priority
0= Low priority
TMR2IP: TMR2 to PR2 Match Interrupt Priority bit
1= High priority
0= Low priority
TMR1IP: TMR1 Overflow Interrupt Priority bit
1= High priority
0= Low priority
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
DS39682C-page 88
Preliminary
© 2007 Microchip Technology Inc.
PIC18F45J10 FAMILY
REGISTER 8-11: IPR2: PERIPHERAL INTERRUPT PRIORITY REGISTER 2
R/W-1
OSCFIP
bit 7
R/W1
CMIP
U-0
—
U-0
—
R/W-1
U-0
—
U-0
—
R/W-1
BCL1IP
CCP2IP
bit 0
bit 7
bit 6
OSCFIP: Oscillator Fail Interrupt Priority bit
1= High priority
0= Low priority
CMIP: Comparator Interrupt Priority bit
1= High priority
0= Low priority
bit 5-4
bit 3
Unimplemented: Read as ‘0’
BCL1IP: Bus Collision Interrupt Priority bit (MSSP1 module)
1= High priority
0= Low priority
bit 2-1
bit 0
Unimplemented: Read as ‘0’
CCP2IP: CCP2 Interrupt Priority bit
1= High priority
0= Low priority
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
REGISTER 8-12: IPR3: PERIPHERAL INTERRUPT PRIORITY REGISTER 3
R/W-1
R/W-1
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
SSP2IP
BCL2IP
bit 7
bit 0
bit 7
bit 6
SSP2IP: Master Synchronous Serial Port 2 Interrupt Priority bit
1= High priority
0= Low priority
BCL2IP: Bus Collision Interrupt Priority bit (MSSP2 module)
1= High priority
0= Low priority
bit 5-0 Unimplemented: Read as ‘0’
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
‘1’ = Bit is set
© 2007 Microchip Technology Inc.
Preliminary
DS39682C-page 89
PIC18F45J10 FAMILY
8.5
RCON Register
The RCON register contains bits used to determine the
cause of the last Reset or wake-up from Idle or Sleep
modes. RCON also contains the bit that enables
interrupt priorities (IPEN).
REGISTER 8-13: RCON: RESET CONTROL REGISTER
R/W-0
IPEN
U-0
—
U-0
—
R/W-1
RI
R-1
TO
R-1
PD
R/W-0
POR
R/W-0
BOR
bit 7
bit 0
bit 7
IPEN: Interrupt Priority Enable bit
1= Enable priority levels on interrupts
0= Disable priority levels on interrupts (PIC16CXXX Compatibility mode)
bit 6-5 Unimplemented: Read as ‘0’
bit 4
bit 3
bit 2
bit 1
bit 0
RI: RESETInstruction Flag bit
For details of bit operation, see Register 4-1.
TO: Watchdog Timer Time-out Flag bit
For details of bit operation, see Register 4-1.
PD: Power-Down Detection Flag bit
For details of bit operation, see Register 4-1.
POR: Power-on Reset Status bit
For details of bit operation, see Register 4-1.
BOR: Brown-out Reset Status bit
For details of bit operation, see Register 4-1.
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
DS39682C-page 90
Preliminary
© 2007 Microchip Technology Inc.
PIC18F45J10 FAMILY
8.6
INTn Pin Interrupts
8.7
TMR0 Interrupt
External interrupts on the RB0/INT0, RB1/INT1 and
RB2/INT2 pins are edge-triggered. If the corresponding
INTEDGx bit in the INTCON2 register is set (= 1), the
interrupt is triggered by a rising edge; if the bit is clear,
the trigger is on the falling edge. When a valid edge
appears on the RBx/INTx pin, the corresponding flag
bit, INTxIF, is set. This interrupt can be disabled by
clearing the corresponding enable bit, INTxIE. Flag bit,
INTxIF, must be cleared in software in the Interrupt
Service Routine before re-enabling the interrupt.
In 8-bit mode (which is the default), an overflow in the
TMR0 register (FFh → 00h) will set flag bit, TMR0IF. In
16-bit mode, an overflow in the TMR0H:TMR0L register
pair (FFFFh → 0000h) will set TMR0IF. The interrupt
can be enabled/disabled by setting/clearing enable bit,
TMR0IE (INTCON<5>). Interrupt priority for Timer0 is
determined by the value contained in the interrupt prior-
ity bit, TMR0IP (INTCON2<2>). See Section 10.0
“Timer0 Module” for further details on the Timer0
module.
All external interrupts (INT0, INT1 and INT2) can
wake-up the processor from the power-managed
modes if bit INTxIE was set prior to going into the
power-managed modes. If the Global Interrupt Enable
bit, GIE, is set, the processor will branch to the interrupt
vector following wake-up.
8.8
PORTB Interrupt-on-Change
An input change on PORTB<7:4> sets flag bit, RBIF
(INTCON<0>). The interrupt can be enabled/disabled
by setting/clearing enable bit, RBIE (INTCON<3>).
Interrupt priority for PORTB interrupt-on-change is
determined by the value contained in the interrupt
priority bit, RBIP (INTCON2<0>).
Interrupt priority for INT1 and INT2 is determined by the
value contained in the interrupt priority bits, INT1IP
(INTCON3<6>) and INT2IP (INTCON3<7>). There is
no priority bit associated with INT0. It is always a high
priority interrupt source.
8.9
Context Saving During Interrupts
During interrupts, the return PC address is saved on
the stack. Additionally, the WREG, STATUS and BSR
registers are saved on the fast return stack. If a fast
return from interrupt is not used (see Section 5.3
“Data Memory Organization”), the user may need to
save the WREG, STATUS and BSR registers on entry
to the Interrupt Service Routine. Depending on the
user’s application, other registers may also need to be
saved. Example 8-1 saves and restores the WREG,
STATUS and BSR registers during an Interrupt Service
Routine.
EXAMPLE 8-1:
SAVING STATUS, WREG AND BSR REGISTERS IN RAM
MOVWF
MOVFF
MOVFF
;
W_TEMP
STATUS, STATUS_TEMP
BSR, BSR_TEMP
; W_TEMP is in virtual bank
; STATUS_TEMP located anywhere
; BSR_TMEP located anywhere
; USER ISR CODE
;
MOVFF
MOVF
MOVFF
BSR_TEMP, BSR
W_TEMP, W
STATUS_TEMP, STATUS
; Restore BSR
; Restore WREG
; Restore STATUS
© 2007 Microchip Technology Inc.
Preliminary
DS39682C-page 91
PIC18F45J10 FAMILY
NOTES:
DS39682C-page 92
Preliminary
© 2007 Microchip Technology Inc.
PIC18F45J10 FAMILY
9.1
I/O Port Pin Capabilities
9.0
I/O PORTS
When developing an application, the capabilities of the
port pins must be considered. Outputs on some pins
have higher output drive strength than others. Similarly,
some pins can tolerate higher than VDD input levels.
Depending on the device selected and features
enabled, there are up to five ports available. Some pins
of the I/O ports are multiplexed with an alternate
function from the peripheral features on the device. In
general, when a peripheral is enabled, that pin may not
be used as a general purpose I/O pin.
9.1.1
PIN OUTPUT DRIVE
The output pin drive strengths vary for groups of pins
intended to meet the needs for a variety of applications.
PORTB and PORTC are designed to drive higher
loads, such as LEDs. All other ports are designed for
small loads, typically indication only. Table 9-1 sum-
marizes the output capabilities. Refer to Section 23.0
“Electrical Characteristics” for more details.
Each port has three registers for its operation. These
registers are:
• TRIS register (data direction register)
• Port register (reads the levels on the pins of the
device)
• LAT register (output latch)
The Data Latch (LAT register) is useful for read-modify-
write operations on the value that the I/O pins are
driving.
TABLE 9-1:
Port
OUTPUT DRIVE LEVELS
Drive
Description
A simplified model of a generic I/O port, without the
interfaces to other peripherals, is shown in Figure 9-1.
PORTA
PORTD
PORTE
PORTB
PORTC
Minimum Intended for indication.
FIGURE 9-1:
GENERIC I/O PORT
OPERATION
Suitable for direct LED drive
High
levels.
RD LAT
9.1.2
INPUT PINS AND VOLTAGE
CONSIDERATIONS
Data
Bus
D
Q
The voltage tolerance of pins used as device inputs is
dependent on the pin’s input function. Pins that are used
as digital only inputs are able to handle DC voltages up
to 5.5V; a level typical for digital logic circuits. In contrast,
pins that also have analog input functions of any kind
can only tolerate voltages up to VDD. Voltage excursions
beyond VDD on these pins should be avoided. Table 9-2
summarizes the input capabilities. Refer to
Section 23.0 “Electrical Characteristics” for more
details.
WR LAT
or Port
I/O pin(1)
CK
Data Latch
D
Q
WR TRIS
RD TRIS
CK
TRIS Latch
Input
Buffer
TABLE 9-2:
Port or Pin
INPUT VOLTAGE LEVELS
Tolerated
Description
Input
Q
D
EN
PORTA<5:0>
PORTB<5:0>
PORTC<1:0>
PORTE<2:0>
PORTB<7:6>
PORTC<7:2>
PORTD<7:0>
RD Port
Only VDD input levels
tolerated.
VDD
Note 1: I/O pins have diode protection to VDD and VSS.
Tolerates input levels
5.5V
above VDD, useful for
most standard logic.
© 2007 Microchip Technology Inc.
Preliminary
DS39682C-page 93
PIC18F45J10 FAMILY
9.1.3
INTERFACING TO A 5V SYSTEM
9.2
PORTA, TRISA and LATA Registers
Though the VDDMAX of the PIC18F45J10 family is 3.6V,
these devices are still capable of interfacing with 5V
systems, even if the VIH of the target system is above
3.6V. This is accomplished by adding a pull-up resistor
to the port pin (Figure 9-2), clearing the LAT bit for that
pin and manipulating the corresponding TRIS bit
(Figure 9-1) to either allow the line to be pulled high or
to drive the pin low. Only port pins that are tolerant of
voltages up to 5.5V can be used for this type of
interface (refer to Section 9.1.2 “Input Pins and
Voltage Considerations”).
PORTA is a 5-bit wide, bidirectional port. The corre-
sponding data direction register is TRISA. Setting a
TRISA bit (= 1) will make the corresponding PORTA pin
an input (i.e., put the corresponding output driver in a
high-impedance mode). Clearing a TRISA bit (= 0) will
make the corresponding PORTA pin an output (i.e., put
the contents of the output latch on the selected pin).
Reading the PORTA register reads the status of the
pins, whereas writing to it, will write to the port latch.
The Data Latch (LATA) register is also memory mapped.
Read-modify-write operations on the LATA register read
and write the latched output value for PORTA.
FIGURE 9-2:
+5V SYSTEM HARDWARE
INTERFACE
The other PORTA pins are multiplexed with analog
inputs, the analog VREF+ and VREF- inputs and the com-
parator voltage reference output. The operation of pins
RA3:RA0 and RA5 as A/D converter inputs is selected
by clearing or setting the control bits in the ADCON1
register (A/D Control Register 1).
+5V
+5V Device
PIC18F45J10
Pins RA0 and RA3 may also be used as comparator
inputs and RA5 may be used as the C2 comparator
output by setting the appropriate bits in the CMCON
register. To use RA3:RA0 as digital inputs, it is also
necessary to turn off the comparators.
RD7
Note:
On a Power-on Reset, RA5 and RA3:RA0
are configured as analog inputs and read
as ‘0’.
EXAMPLE 9-1:
COMMUNICATING WITH
THE +5V SYSTEM
All PORTA pins have TTL input levels and full CMOS
output drivers.
BCF LATD, 7
; set up LAT register so
; changing TRIS bit will
; drive line low
The TRISA register controls the direction of the PORTA
pins, even when they are being used as analog inputs.
The user must ensure the bits in the TRISA register are
maintained set when using them as analog inputs.
BCF TRISD, 7 ; send a 0 to the 5V system
BCF TRISD, 7 ; send a 1 to the 5V system
EXAMPLE 9-2:
INITIALIZING PORTA
CLRF
PORTA
; Initialize PORTA by
; clearing output
; data latches
CLRF
LATA
; Alternate method
; to clear output
; data latches
MOVLW
MOVWF
MOVWF
MOVWF
MOVLW
07h
ADCON1
07h
CMCON
0CFh
; Configure A/D
; for digital inputs
; Configure comparators
; for digital input
; Value used to
; initialize data
; direction
MOVWF
TRISA
; Set RA<3:0> as inputs
; RA<5:4> as outputs
DS39682C-page 94
Preliminary
© 2007 Microchip Technology Inc.
PIC18F45J10 FAMILY
TABLE 9-3:
Pin
PORTA I/O SUMMARY
TRIS
I/O
Type
Function
I/O
Description
Setting
RA0/AN0
RA0
0
1
1
O
I
DIG LATA<0> data output; not affected by analog input.
TTL PORTA<0> data input; disabled when analog input enabled.
AN0
RA1
I
ANA A/D input channel 0 and Comparator C1- input. Default input
configuration on POR; does not affect digital output.
RA1/AN1
0
1
1
O
I
DIG LATA<1> data output; not affected by analog input.
TTL PORTA<1> data input; disabled when analog input enabled.
AN1
RA2
I
ANA A/D input channel 1 and Comparator C2- input. Default input
configuration on POR; does not affect digital output.
RA2/AN2/
VREF-/CVREF
0
1
1
O
I
DIG LATA<2> data output; not affected by analog input. Disabled when
CVREF output enabled.
TTL PORTA<2> data input. Disabled when analog functions enabled;
disabled when CVREF output enabled.
AN2
I
ANA A/D input channel 2 and Comparator C2+ input. Default input
configuration on POR; not affected by analog output.
VREF-
1
x
I
ANA A/D and comparator voltage reference low input.
CVREF
O
ANA Comparator voltage reference output. Enabling this feature disables
digital I/O.
RA3/AN3/VREF+
RA3
AN3
0
1
1
O
I
DIG LATA<3> data output; not affected by analog input.
TTL PORTA<3> data input; disabled when analog input enabled.
I
ANA A/D input channel 3 and Comparator C1+ input. Default input
configuration on POR.
VREF+
RA5
1
0
1
1
1
0
x
x
x
x
I
O
I
ANA A/D and comparator voltage reference high input.
DIG LATA<5> data output; not affected by analog input.
TTL PORTA<5> data input; disabled when analog input enabled.
ANA A/D input channel 4. Default configuration on POR.
TTL Slave select input for MSSP1 (MSSP1 module).
DIG Comparator 2 output; takes priority over port data.
ANA Main oscillator feedback output connection (HS mode).
DIG System cycle clock output (FOSC/4) in RC and EC Oscillator modes.
ANA Main oscillator input connection.
RA5/AN4/SS1/
C2OUT
AN4
SS1
I
I
C2OUT
OSC2
CLKO
OSC1
CLKI
O
O
O
I
OSC2/CLKO
OSC1/CLKI
I
ANA Main clock input connection.
Legend:
DIG = Digital level output; TTL = TTL input buffer; ST = Schmitt Trigger input buffer; ANA = Analog level input/output;
x= Don’t care (TRIS bit does not affect port direction or is overridden for this option).
© 2007 Microchip Technology Inc.
Preliminary
DS39682C-page 95
PIC18F45J10 FAMILY
TABLE 9-4:
SUMMARY OF REGISTERS ASSOCIATED WITH PORTA
Reset
Values
on page
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PORTA
LATA
—
—
—
—
RA5
—
RA3
RA2
RA1
RA0
46
46
46
44
45
45
PORTA Data Latch Register (Read and Write to Data Latch)
TRISA
—
—
TRISA5
VCFG1
C2INV
CVRR
—
TRISA3
PCFG3
CIS
TRISA2
PCFG2
CM2
TRISA1
PCFG1
CM1
TRISA0
PCFG0
CM0
ADCON1
CMCON
CVRCON
—
—
VCFG0
C1INV
CVRSS
C2OUT
CVREN
C1OUT
CVROE
CVR3
CVR2
CVR1
CVR0
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PORTA.
DS39682C-page 96
Preliminary
© 2007 Microchip Technology Inc.
PIC18F45J10 FAMILY
Four of the PORTB pins (RB7:RB4) have an interrupt-
on-change feature. Only pins configured as inputs can
cause this interrupt to occur (i.e., any RB7:RB4 pin
configured as an output is excluded from the interrupt-
on-change comparison). The input pins (of RB7:RB4)
are compared with the old value latched on the last
read of PORTB. The “mismatch” outputs of RB7:RB4
are ORed together to generate the RB Port Change
Interrupt with Flag bit, RBIF (INTCON<0>).
9.3
PORTB, TRISB and LATB
Registers
PORTB is an 8-bit wide, bidirectional port. The corre-
sponding data direction register is TRISB. Setting a
TRISB bit (= 1) will make the corresponding PORTB
pin an input (i.e., put the corresponding output driver in
a high-impedance mode). Clearing a TRISB bit (= 0)
will make the corresponding PORTB pin an output (i.e.,
put the contents of the output latch on the selected pin).
This interrupt can wake the device from Sleep mode or
any of the Idle modes. The user, in the Interrupt Service
Routine, can clear the interrupt in the following manner:
The Data Latch register (LATB) is also memory
mapped. Read-modify-write operations on the LATB
register read and write the latched output value for
PORTB.
a) Any read or write of PORTB (except with the
MOVFF (ANY), PORTBinstruction).
b) Clear flag bit, RBIF.
EXAMPLE 9-3:
INITIALIZING PORTB
A mismatch condition will continue to set flag bit, RBIF.
Reading PORTB will end the mismatch condition and
allow flag bit, RBIF, to be cleared.
CLRF
PORTB
; Initialize PORTB by
; clearing output
; data latches
CLRF
LATB
; Alternate method
; to clear output
; data latches
The interrupt-on-change feature is recommended for
wake-up on key depression operation and operations
where PORTB is only used for the interrupt-on-change
feature. Polling of PORTB is not recommended while
using the interrupt-on-change feature.
MOVLW 0Fh
; Set RB<4:0> as
MOVWF ADCON1 ; digital I/O pins
; (required if config bit
; PBADEN is set)
; Value used to
; initialize data
; direction
; Set RB<3:0> as inputs
; RB<5:4> as outputs
; RB<7:6> as inputs
RB3 can be configured by the configuration bit,
CCP2MX, as the alternate peripheral pin for the CCP2
module (CCP2MX = 0).
MOVLW 0CFh
MOVWF TRISB
The RB5 pin is multiplexed with the Timer0 module
clock input and one of the comparator outputs to
become the RB5/KBI1/T0CKI/C1OUT pin.
Each of the PORTB pins has a weak internal pull-up. A
single control bit can turn on all the pull-ups. This is
performed by clearing bit, RBPU (INTCON2<7>). The
weak pull-up is automatically turned off when the port
pin is configured as an output. The pull-ups are
disabled on a Power-on Reset.
Note:
On a Power-on Reset, RB4:RB0 are
configured as analog inputs by default and
read as ‘0’; RB7:RB5 are configured as
digital inputs.
By programming the configuration bit,
PBADEN, RB4:RB0 will alternatively be
configured as digital inputs on POR.
© 2007 Microchip Technology Inc.
Preliminary
DS39682C-page 97
PIC18F45J10 FAMILY
TABLE 9-5:
PORTB I/O SUMMARY
TRIS
Setting
I/O
Type
Pin
Function
I/O
Description
RB0/INT0/FLT0/
AN12
RB0
0
1
O
I
DIG
TTL
LATB<0> data output; not affected by analog input.
PORTB<0> data input; weak pull-up when RBPU bit is cleared.
(1)
Disabled when analog input enabled.
INT0
FLT0
1
1
I
I
ST
ST
External interrupt 0 input.
PWM Fault input (ECCP1/CCP1 module); enabled in
software.
(1)
AN12
RB1
1
0
1
I
O
I
ANA
DIG
TTL
A/D input channel 12.
RB1/INT1/AN10
RB2/INT2/AN8
RB3/AN9/CCP2
LATB<1> data output; not affected by analog input.
PORTB<1> data input; weak pull-up when RBPU bit is cleared.
Disabled when analog input enabled.
(1)
INT1
AN10
RB2
1
1
0
1
I
I
ST
ANA
DIG
TTL
External interrupt 1 input.
(1)
A/D input channel 10.
O
I
LATB<2> data output; not affected by analog input.
PORTB<2> data input; weak pull-up when RBPU bit is cleared.
Disabled when analog input enabled.
(1)
INT2
AN8
RB3
1
1
0
1
I
I
ST
ANA
DIG
TTL
External interrupt 2 input.
(1)
A/D input channel 8.
O
I
LATB<3> data output; not affected by analog input.
PORTB<3> data input; weak pull-up when RBPU bit is cleared.
Disabled when analog input enabled.
(1)
(1)
AN9
1
0
1
0
1
I
O
I
ANA
DIG
ST
A/D input channel 9.
(2)
CCP2
CCP2 compare and PWM output.
CCP2 capture input
RB4/KBI0/AN11
RB4
O
I
DIG
TTL
LATB<4> data output; not affected by analog input.
PORTB<4> data input; weak pull-up when RBPU bit is cleared.
Disabled when analog input enabled.
(1)
KBI0
AN11
RB5
1
1
0
1
1
1
0
I
I
TTL
ANA
DIG
TTL
TTL
ST
Interrupt-on-change pin.
(1)
A/D input channel 11.
RB5/KBI1/T0CKI/
C1OUT
O
I
LATB<5> data output.
PORTB<5> data input; weak pull-up when RBPU bit is cleared.
Interrupt-on-change pin.
KBI1
T0CKI
C1OUT
I
I
Timer0 clock input.
O
DIG
Comparator 1 output; takes priority over port data.
RB6/KBI2/PGC
RB7/KBI3/PGD
RB6
0
1
1
x
0
1
1
x
x
O
I
DIG
TTL
TTL
ST
LATB<6> data output.
PORTB<6> data input; weak pull-up when RBPU bit is cleared.
Interrupt-on-change pin.
KBI2
PGC
RB7
I
(3)
I
Serial execution (ICSP™) clock input for ICSP and ICD operation.
LATB<7> data output.
O
I
DIG
TTL
TTL
DIG
ST
PORTB<7> data input; weak pull-up when RBPU bit is cleared.
Interrupt-on-change pin.
KBI3
PGD
I
(3)
O
I
Serial execution data output for ICSP and ICD operation.
(3)
Serial execution data input for ICSP and ICD operation.
Legend:
DIG = Digital level output; TTL = TTL input buffer; ST = Schmitt Trigger input buffer; ANA = Analog level input/output;
x= Don’t care (TRIS bit does not affect port direction or is overridden for this option).
Note 1: Configuration on POR is determined by the PBADEN configuration bit. Pins are configured as analog inputs by default
when PBADEN is set and digital inputs when PBADEN is cleared.
2: Alternate assignment for CCP2 when the CCP2MX configuration bit is ‘0’. Default assignment is RC1.
3: All other pin functions are disabled when ICSP or ICD are enabled.
DS39682C-page 98
Preliminary
© 2007 Microchip Technology Inc.
PIC18F45J10 FAMILY
TABLE 9-6:
Name
SUMMARY OF REGISTERS ASSOCIATED WITH PORTB
Reset
Values
on page
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PORTB
LATB
RB7
RB6
RB5
RB4
RB3
RB2
RB1
RB0
46
46
46
43
43
43
44
PORTB Data Latch Register (Read and Write to Data Latch)
PORTB Data Direction Control Register
TRISB
INTCON
INTCON2
INTCON3
ADCON1
GIE/GIEH PEIE/GIEL TMR0IE
INT0IE
RBIE
—
TMR0IF
TMR0IP
—
INT0IF
—
RBIF
RBIP
RBPU
INT2IP
—
INTEDG0 INTEDG1 INTEDG2
INT1IP
—
—
INT2IE
VCFG0
INT1IE
PCFG3
INT2IF
PCFG1
INT1IF
PCFG0
VCFG1
PCFG2
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PORTB.
© 2007 Microchip Technology Inc.
Preliminary
DS39682C-page 99
PIC18F45J10 FAMILY
9.4
PORTC, TRISC and LATC
Registers
Note:
On a Power-on Reset, these pins are
configured as digital inputs.
PORTC is an 8-bit wide, bidirectional port. The corre-
sponding data direction register is TRISC. Setting a
TRISC bit (= 1) will make the corresponding PORTC
pin an input (i.e., put the corresponding output driver in
a high-impedance mode). Clearing a TRISC bit (= 0)
will make the corresponding PORTC pin an output (i.e.,
put the contents of the output latch on the selected pin).
The contents of the TRISC register are affected by
peripheral overrides. Reading TRISC always returns
the current contents, even though a peripheral device
may be overriding one or more of the pins.
EXAMPLE 9-4:
INITIALIZING PORTC
CLRF PORTC
; Initialize PORTC by
; clearing output
; data latches
The Data Latch register (LATC) is also memory
mapped. Read-modify-write operations on the LATC
register read and write the latched output value for
PORTC.
CLRF LATC
MOVLW 0CFh
MOVWF TRISC
; Alternate method
; to clear output
; data latches
; Value used to
; initialize data
; direction
; Set RC<3:0> as inputs
; RC<5:4> as outputs
; RC<7:6> as inputs
PORTC is multiplexed with several peripheral functions
(Table 9-7). The pins have Schmitt Trigger input
buffers. RC1 is normally configured by configuration
bit, CCP2MX, as the default peripheral pin of the CCP2
module (default/erased state, CCP2MX = 1).
When enabling peripheral functions, care should be
taken in defining TRIS bits for each PORTC pin. Some
peripherals override the TRIS bit to make a pin an output,
while other peripherals override the TRIS bit to make a
pin an input. The user should refer to the corresponding
peripheral section for additional information.
DS39682C-page 100
Preliminary
© 2007 Microchip Technology Inc.
PIC18F45J10 FAMILY
TABLE 9-7:
PORTC I/O SUMMARY
TRIS
Setting
I/O
Type
Pin
Function
I/O
Description
RC0/T1OSO/
T1CKI
RC0
0
1
x
O
I
DIG
ST
LATC<0> data output.
PORTC<0> data input.
T1OSO
O
ANA
Timer1 oscillator output; enabled when Timer1 oscillator enabled.
Disables digital I/O.
T1CKI
RC1
1
0
1
x
I
O
I
ST
DIG
ST
Timer1 counter input.
LATC<1> data output.
PORTC<1> data input.
RC1/T1OSI/CCP2
T1OSI
I
ANA
Timer1 oscillator input; enabled when Timer1 oscillator enabled.
Disables digital I/O.
(1)
CCP2
0
1
0
1
0
1
0
O
I
DIG
ST
CCP2 compare and PWM output; takes priority over port data.
CCP2 capture input.
RC2/CCP1/P1A
RC2
O
I
DIG
ST
LATC<2> data output.
PORTC<2> data input.
CCP1
O
I
DIG
ST
ECCP1/CCP1 compare or PWM output; takes priority over port data.
ECCP1/CCP1 capture input.
(2)
P1A
O
DIG
ECCP1 Enhanced PWM output, channel A. May be configured for
tri-state during Enhanced PWM shutdown events. Takes priority over
port data.
RC3/SCK1/SCL1
RC3
SCK1
SCL1
RC4
0
1
0
1
0
1
0
1
1
1
1
0
1
0
0
1
1
O
I
DIG
ST
LATC<3> data output.
PORTC<3> data input.
O
I
DIG
ST
SPI™ clock output (MSSP1 module); takes priority over port data.
SPI clock input (MSSP1 module).
2
O
I
DIG
I C™ clock output (MSSP1 module); takes priority over port data.
2
2
I C/SMB I C clock input (MSSP1 module); input type depends on module setting.
RC4/SDI1/SDA1
O
I
DIG
ST
LATC<4> data output.
PORTC<4> data input.
SDI1
I
ST
SPI data input (MSSP1 module).
2
SDA1
O
I
DIG
I C data output (MSSP1 module); takes priority over port data.
2
2
I C/SMB I C data input (MSSP1 module); input type depends on module setting.
RC5/SDO1
RC6/TX/CK
RC5
O
I
DIG
ST
LATC<5> data output.
PORTC<5> data input.
SDO1
RC6
O
O
I
DIG
DIG
ST
SPI data output (MSSP1 module); takes priority over port data.
LATC<6> data output.
PORTC<6> data input.
TX
CK
O
DIG
Asynchronous serial transmit data output (EUSART module);
takes priority over port data. User must configure as output.
1
O
DIG
Synchronous serial clock output (EUSART module); takes priority
over port data.
1
0
1
1
1
I
O
I
ST
DIG
ST
Synchronous serial clock input (EUSART module).
LATC<7> data output.
RC7/RX/DT
RC7
PORTC<7> data input.
RX
DT
I
ST
Asynchronous serial receive data input (EUSART module).
O
DIG
Synchronous serial data output (EUSART module); takes priority over
port data.
1
I
ST
Synchronous serial data input (EUSART module). User must
configure as an input.
Legend:
DIG = Digital level output; TTL = TTL input buffer; ST = Schmitt Trigger input buffer; ANA = Analog level input/output;
I C/SMB = I C/SMBus input buffer; x= Don’t care (TRIS bit does not affect port direction or is overridden for this option).
2
2
Note 1: Default assignment for CCP2 when the CCP2MX configuration bit is set. Alternate assignment is RB3.
2: Enhanced PWM output is available only on PIC18F44J10/45J10 devices.
© 2007 Microchip Technology Inc.
Preliminary
DS39682C-page 101
PIC18F45J10 FAMILY
TABLE 9-8:
SUMMARY OF REGISTERS ASSOCIATED WITH PORTC
Reset
Values
on page
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PORTC
LATC
RC7
RC6
RC5
RC4
RC3
RC2
RC1
RC0
46
46
46
PORTC Data Latch Register (Read and Write to Data Latch)
PORTC Data Direction Control Register
TRISC
DS39682C-page 102
Preliminary
© 2007 Microchip Technology Inc.
PIC18F45J10 FAMILY
PORTD can also be configured as an 8-bit wide micro-
processor port (Parallel Slave Port) by setting control
bit, PSPMODE (TRISE<4>). In this mode, the input
buffers are TTL. See Section 9.7 “Parallel Slave
Port” for additional information on the Parallel Slave
Port (PSP).
9.5
PORTD, TRISD and LATD
Registers
Note:
PORTD is only available in 40/44-pin
devices.
PORTD is an 8-bit wide, bidirectional port. The corre-
sponding data direction register is TRISD. Setting a
TRISD bit (= 1) will make the corresponding PORTD
pin an input (i.e., put the corresponding output driver in
a high-impedance mode). Clearing a TRISD bit (= 0)
will make the corresponding PORTD pin an output (i.e.,
put the contents of the output latch on the selected pin).
Note:
When the Enhanced PWM mode is used
with either dual or quad outputs, the PSP
functions of PORTD are automatically
disabled.
EXAMPLE 9-5:
INITIALIZING PORTD
The Data Latch register (LATD) is also memory
mapped. Read-modify-write operations on the LATD
register read and write the latched output value for
PORTD.
CLRF
PORTD
; Initialize PORTD by
; clearing output
; data latches
; Alternate method
; to clear output
; data latches
; Value used to
; initialize data
; direction
CLRF
LATD
All pins on PORTD are implemented with Schmitt Trigger
input buffers. Each pin is individually configurable as an
input or output.
MOVLW 0CFh
MOVWF TRISD
Three of the PORTD pins are multiplexed with outputs
P1B, P1C and P1D of the Enhanced CCP module. The
operation of these additional PWM output pins is
covered in greater detail in Section 14.0 “Enhanced
Capture/Compare/PWM (ECCP) Module”.
; Set RD<3:0> as inputs
; RD<5:4> as outputs
; RD<7:6> as inputs
Note:
On a Power-on Reset, these pins are
configured as digital inputs.
© 2007 Microchip Technology Inc.
Preliminary
DS39682C-page 103
PIC18F45J10 FAMILY
TABLE 9-9:
PORTD I/O SUMMARY
TRIS
Setting
I/O
Type
Pin
Function
I/O
Description
RD0/PSP0/SCK2/
SCL2
RD0
0
1
x
x
0
1
0
1
O
I
DIG
ST
LATD<0> data output.
PORTD<0> data input.
PSP0
SCK2
SCL2
O
I
DIG
TTL
DIG
ST
PSP read data output (LATD<0>); takes priority over port data.
PSP write data input.
O
I
SPI™ clock output (MSSP2 module); takes priority over port data.
SPI clock input (MSSP2 module).
2
O
I
DIG
I C™ clock output (MSSP2 module); takes priority over port data.
2
2
I C/SMB I C clock input (MSSP2 module); input type depends on module setting.
RD1/PSP1/SDI2/
SDA2
RD1
0
1
x
x
1
1
1
0
1
x
x
0
0
1
x
x
1
0
1
x
x
0
1
x
x
0
O
I
DIG
ST
LATD<1> data output.
PORTD<1> data input.
PSP1
O
I
DIG
TTL
ST
PSP read data output (LATD<1>); takes priority over port data.
PSP write data input.
SDI2
I
SPI data input (MSSP2 module).
2
SDA2
O
I
DIG
I C data output (MSSP2 module); takes priority over port data.
2
2
I C/SMB I C data input (MSSP2 module); input type depends on module setting.
RD2/PSP2/SDO2
RD3/PSP3/SS2
RD2
O
I
DIG
ST
LATD<2> data output.
PORTD<2> data input.
PSP2
O
I
DIG
TTL
DIG
DIG
ST
PSP read data output (LATD<2>); takes priority over port data.
PSP write data input.
SDO2
RD3
O
O
I
SPI data output (MSSP2 module); takes priority over port data.
LATD<3> data output.
PORTD<3> data input.
PSP3
O
I
DIG
TTL
TTL
DIG
ST
PSP read data output (LATD<3>); takes priority over port data.
PSP write data input.
SS2
RD4
I
Slave select input for MSSP2 (MSSP2 module).
LATD<4> data output.
RD4/PSP4
O
I
PORTD<4> data input.
PSP4
RD5
O
I
DIG
TTL
DIG
ST
PSP read data output (LATD<4>); takes priority over port data.
PSP write data input.
RD5/PSP5/P1B
O
I
LATD<5> data output.
PORTD<5> data input.
PSP5
O
I
DIG
TTL
DIG
PSP read data output (LATD<5>); takes priority over port data.
PSP write data input.
P1B
RD6
O
ECCP1 Enhanced PWM output, channel B; takes priority over port and PSP
data. May be configured for tri-state during Enhanced PWM shutdown events.
RD6/PSP6/P1C
RD7/PSP7/P1D
0
1
x
x
0
O
I
DIG
ST
LATD<6> data output.
PORTD<6> data input.
PSP6
O
I
DIG
TTL
DIG
PSP read data output (LATD<6>); takes priority over port data.
PSP write data input.
P1C
RD7
O
ECCP1 Enhanced PWM output, channel C; takes priority over port and PSP
data. May be configured for tri-state during Enhanced PWM shutdown events.
0
1
x
x
0
O
I
DIG
ST
LATD<7> data output.
PORTD<7> data input.
PSP7
P1D
O
I
DIG
TTL
DIG
PSP read data output (LATD<7>); takes priority over port data.
PSP write data input.
O
ECCP1 Enhanced PWM output, channel D; takes priority over port and PSP
data. May be configured for tri-state during Enhanced PWM shutdown events.
2
2
Legend:
DIG = Digital level output; TTL = TTL input buffer; ST = Schmitt Trigger input buffer; I C/SMB = I C/SMBus input buffer;
x= Don’t care (TRIS bit does not affect port direction or is overridden for this option).
DS39682C-page 104
Preliminary
© 2007 Microchip Technology Inc.
PIC18F45J10 FAMILY
TABLE 9-10: SUMMARY OF REGISTERS ASSOCIATED WITH PORTD
Reset
Values
on page
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PORTD(1)
LATD(1)
TRISD(1)
TRISE(1)
CCP1CON
RD7
RD6
RD5
RD4
RD3
RD2
RD1
RD0
46
46
46
46
45
PORTD Data Latch Register (Read and Write to Data Latch)
PORTD Data Direction Control Register
IBF
OBF
IBOV
PSPMODE
—
TRISE2
TRISE1
TRISE0
P1M1
P1M0
DC1B1
DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PORTD.
Note 1: These registers are not available in 28-pin devices.
© 2007 Microchip Technology Inc.
Preliminary
DS39682C-page 105
PIC18F45J10 FAMILY
The upper four bits of the TRISE register also control
the operation of the Parallel Slave Port. Their operation
is explained in Register 9-1.
9.6
PORTE, TRISE and LATE
Registers
Note:
PORTE is only available in 40/44-pin
devices.
The Data Latch register (LATE) is also memory
mapped. Read-modify-write operations on the LATE
register read and write the latched output value for
PORTE.
Depending on the particular PIC18F45J10 family
device selected, PORTE is implemented in two
different ways.
EXAMPLE 9-6:
INITIALIZING PORTE
For 40/44-pin devices, PORTE is a 4-bit wide port.
Three pins (RE0/RD/AN5, RE1/WR/AN6 and RE2/CS/
AN7) are individually configurable as inputs or outputs.
These pins have Schmitt Trigger input buffers. When
selected as analog inputs, these pins will read as ‘0’s.
CLRF
PORTE
; Initialize PORTE by
; clearing output
; data latches
CLRF
LATE
; Alternate method
; to clear output
; data latches
The corresponding data direction register is TRISE.
Setting a TRISE bit (= 1) will make the corresponding
PORTE pin an input (i.e., put the corresponding output
driver in a high-impedance mode). Clearing a TRISE bit
(= 0) will make the corresponding PORTE pin an output
(i.e., put the contents of the output latch on the selected
pin).
MOVLW 0Ah
; Configure A/D
MOVWF ADCON1 ; for digital inputs
MOVLW 03h
; Value used to
; initialize data
; direction
MOVWF TRISE
; Set RE<0> as inputs
; RE<1> as outputs
; RE<2> as inputs
TRISE controls the direction of the RE pins, even when
they are being used as analog inputs. The user must
make sure to keep the pins configured as inputs when
using them as analog inputs.
Note:
On a Power-on Reset, RE2:RE0 are
configured as analog inputs.
DS39682C-page 106
Preliminary
© 2007 Microchip Technology Inc.
PIC18F45J10 FAMILY
REGISTER 9-1:
TRISE REGISTER (40/44-PIN DEVICES ONLY)
R-0
IBF
R-0
R/W-0
IBOV
R/W-0
U-0
—
R/W-1
R/W-1
R/W-1
OBF
PSPMODE
TRISE2
TRISE1
TRISE0
bit 7
bit 0
bit 7
bit 6
bit 5
bit 4
IBF: Input Buffer Full Status bit
1= A word has been received and waiting to be read by the CPU
0= No word has been received
OBF: Output Buffer Full Status bit
1= The output buffer still holds a previously written word
0= The output buffer has been read
IBOV: Input Buffer Overflow Detect bit (in Microprocessor mode)
1= A write occurred when a previously input word has not been read (must be cleared in software)
0= No overflow occurred
PSPMODE: Parallel Slave Port Mode Select bit
1= Parallel Slave Port mode
0= General purpose I/O mode
bit 3
bit 2
Unimplemented: Read as ‘0’
TRISE2: RE2 Direction Control bit
1= Input
0= Output
bit 1
bit 0
TRISE1: RE1 Direction Control bit
1= Input
0= Output
TRISE0: RE0 Direction Control bit
1= Input
0= Output
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
© 2007 Microchip Technology Inc.
Preliminary
DS39682C-page 107
PIC18F45J10 FAMILY
TABLE 9-11: PORTE I/O SUMMARY
TRIS
Setting
I/O
Type
Pin
Function
I/O
Description
RE0/RD/AN5
RE0
0
1
1
1
0
1
1
1
0
1
1
1
O
I
DIG
ST
LATE<0> data output; not affected by analog input.
PORTE<0> data input; disabled when analog input enabled.
PSP read enable input (PSP enabled).
RD
I
TTL
ANA
DIG
ST
AN5
RE1
I
A/D input channel 5; default input configuration on POR.
LATE<1> data output; not affected by analog input.
PORTE<1> data input; disabled when analog input enabled.
PSP write enable input (PSP enabled).
RE1/WR/AN6
RE2/CS/AN7
O
I
WR
AN6
RE2
I
TTL
ANA
DIG
ST
I
A/D input channel 6; default input configuration on POR.
LATE<2> data output; not affected by analog input.
PORTE<2> data input; disabled when analog input enabled.
PSP write enable input (PSP enabled).
O
I
CS
I
TTL
ANA
AN7
I
A/D input channel 7; default input configuration on POR.
Legend:
DIG = Digital level output; TTL = TTL input buffer; ST = Schmitt Trigger input buffer; ANA = Analog level input/output;
x= Don’t care (TRIS bit does not affect port direction or is overridden for this option).
TABLE 9-12: SUMMARY OF REGISTERS ASSOCIATED WITH PORTE
Reset
Values
on page
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PORTE(1)
LATE(1)
—
—
—
—
—
—
—
—
—
—
RE2
RE1
RE0
46
46
PORTE Data Latch Register
(Read and Write to Data Latch)
TRISE(1)
ADCON1
IBF
—
OBF
—
IBOV
PSPMODE
VCFG0
—
TRISE2
PCFG2
TRISE1
PCFG1
TRISE0
PCFG0
46
44
VCFG1
PCFG3
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PORTE.
Note 1: These registers are not available in 28-pin devices.
DS39682C-page 108
Preliminary
© 2007 Microchip Technology Inc.
PIC18F45J10 FAMILY
The timing for the control signals in Write and Read
modes is shown in Figure 9-4 and Figure 9-5,
respectively.
9.7
Parallel Slave Port
Note:
The Parallel Slave Port is only available in
40/44-pin devices.
FIGURE 9-3:
PORTD AND PORTE
BLOCK DIAGRAM
(PARALLEL SLAVE PORT)
In addition to its function as a general I/O port, PORTD
can also operate as an 8-bit wide Parallel Slave Port
(PSP) or microprocessor port. PSP operation is
controlled by the 4 upper bits of the TRISE register
(Register 9-1). Setting control bit, PSPMODE
(TRISE<4>), enables PSP operation as long as the
Enhanced CCP module is not operating in dual output
or quad output PWM mode. In Slave mode, the port is
asynchronously readable and writable by the external
world.
One bit of PORTD
Data Bus
D
Q
RDx pin
WR LATD
or
WR PORTD
CK
Data Latch
TTL
The PSP can directly interface to an 8-bit micro-
processor data bus. The external microprocessor can
read or write the PORTD latch as an 8-bit latch. Setting
the control bit, PSPMODE, enables the PORTE I/O
pins to become control inputs for the microprocessor
port. When set, port pin RE0 is the RD input, RE1 is the
WR input and RE2 is the CS (Chip Select) input. For
this functionality, the corresponding data direction bits
of the TRISE register (TRISE<2:0>) must be config-
ured as inputs (set). The A/D port configuration bits,
PFCG3:PFCG0 (ADCON1<3:0>), must also be set to a
value in the range of ‘1010’ through ‘1111’.
Q
D
RD PORTD
RD LATD
EN
Set Interrupt Flag
PSPIF (PIR1<7>)
A write to the PSP occurs when both the CS and WR
lines are first detected low and ends when either are
detected high. The PSPIF and IBF flag bits are both set
when the write ends.
PORTE Pins
Read
RD
CS
WR
TTL
Chip Select
TTL
A read from the PSP occurs when both the CS and RD
lines are first detected low. The data in PORTD is read
out and the OBF bit is clear. If the user writes new data
to PORTD to set OBF, the data is immediately read out;
however, the OBF bit is not set.
Write
TTL
Note:
I/O pins have diode protection to VDD and VSS.
When either the CS or RD lines are detected high, the
PORTD pins return to the input state and the PSPIF bit
is set. User applications should wait for PSPIF to be set
before servicing the PSP; when this happens, the IBF
and OBF bits can be polled and the appropriate action
taken.
© 2007 Microchip Technology Inc.
Preliminary
DS39682C-page 109
PIC18F45J10 FAMILY
FIGURE 9-4:
PARALLEL SLAVE PORT WRITE WAVEFORMS
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
CS
WR
RD
PORTD<7:0>
IBF
OBF
PSPIF
FIGURE 9-5:
PARALLEL SLAVE PORT READ WAVEFORMS
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
CS
WR
RD
PORTD<7:0>
IBF
OBF
PSPIF
TABLE 9-13: REGISTERS ASSOCIATED WITH PARALLEL SLAVE PORT
Reset
Values
on page
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PORTD(1)
LATD(1)
RD7
RD6
RD5
RD4
RD3
RD2
RD1
RD0
RE0
46
46
46
46
46
PORTD Data Latch Register (Read and Write to Data Latch)
TRISD(1) PORTD Data Direction Control Register
PORTE(1)
LATE(1)
—
—
—
—
—
—
—
—
—
—
RE2
RE1
PORTE Data Latch Register
(Read and Write to Data Latch)
TRISE(1)
INTCON
PIR1
IBF
OBF
IBOV
PSPMODE
INT0IE
TXIF
—
TRISE2
TMR0IF
CCP1IF
TRISE1
INT0IF
TRISE0
RBIF
46
43
45
45
45
44
GIE/GIEH PEIE/GIEL TMR0IE
RBIE
PSPIF(1)
PSPIE(1)
PSPIP(1)
—
ADIF
ADIE
ADIP
—
RCIF
RCIE
SSP1IF
SSP1IE
SSP1IP
PCFG3
TMR2IF
TMR1IF
PIE1
TXIE
CCP1IE TMR2IE TMR1IE
CCP1IP TMR2IP TMR1IP
IPR1
RCIP
TXIP
ADCON1
VCFG1
VCFG0
PCFG2
PCFG1
PCFG0
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the Parallel Slave Port.
Note 1: These registers and/or bits are not implemented on 28-pin devices and should be read as ‘0’.
DS39682C-page 110
Preliminary
© 2007 Microchip Technology Inc.
PIC18F45J10 FAMILY
The T0CON register (Register 10-1) controls all
aspects of the module’s operation, including the
prescale selection. It is both readable and writable.
10.0 TIMER0 MODULE
The Timer0 module incorporates the following features:
• Software selectable operation as a timer or
counter in both 8-bit or 16-bit modes
A simplified block diagram of the Timer0 module in 8-bit
mode is shown in Figure 10-1. Figure 10-2 shows a
simplified block diagram of the Timer0 module in 16-bit
mode.
• Readable and writable registers
• Dedicated 8-bit, software programmable
prescaler
• Selectable clock source (internal or external)
• Edge select for external clock
• Interrupt-on-overflow
REGISTER 10-1: T0CON: TIMER0 CONTROL REGISTER
R/W-1
TMR0ON
bit 7
R/W-1
R/W-1
T0CS
R/W-1
T0SE
R/W-1
PSA
R/W-1
T0PS2
R/W-1
T0PS1
R/W-1
T0PS0
T08BIT
bit 0
bit 7
bit 6
bit 5
bit 4
bit 3
TMR0ON: Timer0 On/Off Control bit
1= Enables Timer0
0= Stops Timer0
T08BIT: Timer0 8-Bit/16-Bit Control bit
1= Timer0 is configured as an 8-bit timer/counter
0= Timer0 is configured as a 16-bit timer/counter
T0CS: Timer0 Clock Source Select bit
1= Transition on T0CKI pin
0= Internal instruction cycle clock (CLKO)
T0SE: Timer0 Source Edge Select bit
1= Increment on high-to-low transition on T0CKI pin
0= Increment on low-to-high transition on T0CKI pin
PSA: Timer0 Prescaler Assignment bit
1= TImer0 prescaler is not assigned. Timer0 clock input bypasses prescaler.
0= Timer0 prescaler is assigned. Timer0 clock input comes from prescaler output.
bit 2-0 T0PS2:T0PS0: Timer0 Prescaler Select bits
111= 1:256 Prescale value
110= 1:128 Prescale value
101= 1:64 Prescale value
100= 1:32 Prescale value
011= 1:16 Prescale value
010= 1:8 Prescale value
001= 1:4 Prescale value
000= 1:2 Prescale value
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
© 2007 Microchip Technology Inc.
Preliminary
DS39682C-page 111
PIC18F45J10 FAMILY
internal phase clock (TOSC). There is a delay between
synchronization and the onset of incrementing the
timer/counter.
10.1 Timer0 Operation
Timer0 can operate as either a timer or a counter; the
mode is selected with the T0CS bit (T0CON<5>). In
Timer mode (T0CS = 0), the module increments on
every clock by default unless a different prescaler value
is selected (see Section 10.3 “Prescaler”). If the
TMR0 register is written to, the increment is inhibited
for the following two instruction cycles. The user can
work around this by writing an adjusted value to the
TMR0 register.
10.2 Timer0 Reads and Writes in
16-Bit Mode
TMR0H is not the actual high byte of Timer0 in 16-bit
mode. It is actually a buffered version of the real high
byte of Timer0 which is not directly readable nor
writable (refer to Figure 10-2). TMR0H is updated with
the contents of the high byte of Timer0 during a read of
TMR0L. This provides the ability to read all 16 bits of
Timer0 without having to verify that the read of the high
and low byte were valid, due to a rollover between
successive reads of the high and low byte.
The Counter mode is selected by setting the T0CS bit
(= 1). In this mode, Timer0 increments either on every
rising or falling edge of pin RB5/T0CKI. The increment-
ing edge is determined by the Timer0 Source Edge
Select bit, T0SE (T0CON<4>); clearing this bit selects
the rising edge. Restrictions on the external clock input
are discussed below.
Similarly, a write to the high byte of Timer0 must also
take place through the TMR0H Buffer register. The high
byte is updated with the contents of TMR0H when a
write occurs to TMR0L. This allows all 16 bits of Timer0
to be updated at once.
An external clock source can be used to drive Timer0;
however, it must meet certain requirements to ensure
that the external clock can be synchronized with the
FIGURE 10-1:
TIMER0 BLOCK DIAGRAM (8-BIT MODE)
FOSC/4
0
1
1
0
Set
TMR0IF
on Overflow
Sync with
Internal
Clocks
TMR0L
8
Programmable
Prescaler
T0CKI pin
(2 TCY Delay)
T0SE
T0CS
3
T0PS2:T0PS0
PSA
8
Internal Data Bus
Note: Upon Reset, Timer0 is enabled in 8-bit mode with clock input from T0CKI max. prescale.
FIGURE 10-2:
TIMER0 BLOCK DIAGRAM (16-BIT MODE)
FOSC/4
0
1
Sync with
Internal
Clocks
Set
TMR0
High Byte
1
TMR0L
TMR0IF
Programmable
Prescaler
on Overflow
T0CKI pin
0
8
(2 TCY Delay)
T0SE
T0CS
3
Read TMR0L
Write TMR0L
T0PS2:T0PS0
PSA
8
8
TMR0H
8
8
Internal Data Bus
Note: Upon Reset, Timer0 is enabled in 8-bit mode with clock input from T0CKI max. prescale.
DS39682C-page 112
Preliminary
© 2007 Microchip Technology Inc.
PIC18F45J10 FAMILY
10.3.1
SWITCHING PRESCALER
ASSIGNMENT
10.3 Prescaler
An 8-bit counter is available as a prescaler for the Timer0
module. The prescaler is not directly readable or writable.
Its value is set by the PSA and T0PS2:T0PS0 bits
(T0CON<3:0>) which determine the prescaler
assignment and prescale ratio.
The prescaler assignment is fully under software
control and can be changed “on-the-fly” during program
execution.
10.4 Timer0 Interrupt
Clearing the PSA bit assigns the prescaler to the
Timer0 module. When it is assigned, prescale values
from 1:2 through 1:256 in power-of-2 increments are
selectable.
The TMR0 interrupt is generated when the TMR0
register overflows from FFh to 00h in 8-bit mode, or
from FFFFh to 0000h in 16-bit mode. This overflow sets
the TMR0IF flag bit. The interrupt can be masked by
clearing the TMR0IE bit (INTCON<5>). Before
re-enabling the interrupt, the TMR0IF bit must be
cleared in software by the Interrupt Service Routine.
When assigned to the Timer0 module, all instructions
writing to the TMR0 register (e.g., CLRF TMR0, MOVWF
TMR0, BSF TMR0, etc.) clear the prescaler count.
Note:
Writing to TMR0 when the prescaler is
assigned to Timer0 will clear the prescaler
count but will not change the prescaler
assignment.
Since Timer0 is shut down in Sleep mode, the TMR0
interrupt cannot awaken the processor from Sleep.
TABLE 10-1: REGISTERS ASSOCIATED WITH TIMER0
Reset
Values
on page
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
TMR0L
Timer0 Register Low Byte
Timer0 Register High Byte
44
44
43
44
46
TMR0H
INTCON
T0CON
TRISA
GIE/GIEH PEIE/GIEL TMR0IE
INT0IE
T0SE
—
RBIE
PSA
TMR0IF
T0PS2
INT0IF
T0PS1
TRISA1
RBIF
T0PS0
TRISA0
TMR0ON
—
T08BIT
—
T0CS
TRISA5
TRISA3
TRISA2
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by Timer0.
© 2007 Microchip Technology Inc.
Preliminary
DS39682C-page 113
PIC18F45J10 FAMILY
NOTES:
DS39682C-page 114
Preliminary
© 2007 Microchip Technology Inc.
PIC18F45J10 FAMILY
A simplified block diagram of the Timer1 module is
shown in Figure 11-1. A block diagram of the module’s
operation in Read/Write mode is shown in Figure 11-2.
11.0 TIMER1 MODULE
The Timer1 timer/counter module incorporates these
features:
The module incorporates its own low-power oscillator
to provide an additional clocking option. The Timer1
oscillator can also be used as a low-power clock source
for the microcontroller in power-managed operation.
• Software selectable operation as a 16-bit timer or
counter
• Readable and writable 8-bit registers (TMR1H
and TMR1L)
Timer1 can also be used to provide Real-Time Clock
(RTC) functionality to applications with only a minimal
addition of external components and code overhead.
• Selectable clock source (internal or external) with
device clock or Timer1 oscillator internal options
• Interrupt-on-overflow
Timer1 is controlled through the T1CON Control
register (Register 11-1). It also contains the Timer1
Oscillator Enable bit (T1OSCEN). Timer1 can be
enabled or disabled by setting or clearing control bit,
TMR1ON (T1CON<0>).
• Reset on CCP Special Event Trigger
• Device clock status flag (T1RUN)
REGISTER 11-1: T1CON: TIMER1 CONTROL REGISTER
R/W-0
RD16
R-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
T1RUN T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON
bit 0
bit 7
bit 7
bit 6
RD16: 16-Bit Read/Write Mode Enable bit
1= Enables register read/write of TImer1 in one 16-bit operation
0= Enables register read/write of Timer1 in two 8-bit operations
T1RUN: Timer1 System Clock Status bit
1= Device clock is derived from Timer1 oscillator
0= Device clock is derived from another source
bit 5-4 T1CKPS1:T1CKPS0: Timer1 Input Clock Prescale Select bits
11= 1:8 Prescale value
10= 1:4 Prescale value
01= 1:2 Prescale value
00= 1:1 Prescale value
bit 3
bit 2
T1OSCEN: Timer1 Oscillator Enable bit
1= Timer1 oscillator is enabled
0= Timer1 oscillator is shut off
The oscillator inverter and feedback resistor are turned off to eliminate power drain.
T1SYNC: Timer1 External Clock Input Synchronization Select bit
When TMR1CS = 1:
1= Do not synchronize external clock input
0= Synchronize external clock input
When TMR1CS = 0:
This bit is ignored. Timer1 uses the internal clock when TMR1CS = 0.
bit 1
bit 0
TMR1CS: Timer1 Clock Source Select bit
1= External clock from pin RC0/T1OSO/T1CKI (on the rising edge)
0= Internal clock (FOSC/4)
TMR1ON: Timer1 On bit
1= Enables Timer1
0= Stops Timer1
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
© 2007 Microchip Technology Inc.
Preliminary
DS39682C-page 115
PIC18F45J10 FAMILY
cycle (FOSC/4). When the bit is set, Timer1 increments
on every rising edge of the Timer1 external clock input
or the Timer1 oscillator, if enabled.
11.1 Timer1 Operation
Timer1 can operate in one of these modes:
• Timer
When Timer1 is enabled, the RC1/T1OSI and
RC0/T1OSO/T1CKI pins become inputs. This means
the values of TRISC<1:0> are ignored and the pins are
read as ‘0’.
• Synchronous Counter
• Asynchronous Counter
The operating mode is determined by the clock select
bit, TMR1CS (T1CON<1>). When TMR1CS is cleared
(= 0), Timer1 increments on every internal instruction
FIGURE 11-1:
TIMER1 BLOCK DIAGRAM
Timer1 Clock Input
Timer1 Oscillator
1
0
On/Off
T1OSO/T1CKI
T1OSI
1
Synchronize
Detect
Prescaler
1, 2, 4, 8
FOSC/4
Internal
Clock
0
2
Sleep Input
T1OSCEN(1)
T1CKPS1:T1CKPS0
T1SYNC
Timer1
On/Off
TMR1CS
TMR1ON
Set
TMR1
High Byte
Clear TMR1
(CCP Special Event Trigger)
TMR1L
TMR1IF
on Overflow
Note 1: When enable bit, T1OSCEN, is cleared, the inverter and feedback resistor are turned off to eliminate power drain.
FIGURE 11-2:
TIMER1 BLOCK DIAGRAM (16-BIT READ/WRITE MODE)
Timer1 Oscillator
Timer1 Clock Input
1
0
T1OSO/T1CKI
T1OSI
1
0
Synchronize
Detect
Prescaler
1, 2, 4, 8
FOSC/4
Internal
Clock
2
Sleep Input
T1OSCEN(1)
T1CKPS1:T1CKPS0
T1SYNC
Timer1
On/Off
TMR1CS
TMR1ON
Set
TMR1IF
on Overflow
TMR1
High Byte
Clear TMR1
(CCP Special Event Trigger)
TMR1L
8
Read TMR1L
Write TMR1L
8
8
TMR1H
8
8
Internal Data Bus
Note 1: When enable bit, T1OSCEN, is cleared, the inverter and feedback resistor are turned off to eliminate power drain.
DS39682C-page 116
Preliminary
© 2007 Microchip Technology Inc.
PIC18F45J10 FAMILY
TABLE 11-1: CAPACITOR SELECTION FOR
THETIMEROSCILLATOR(2,3,4)
11.2 Timer1 16-Bit Read/Write Mode
Timer1 can be configured for 16-bit reads and writes
(see Figure 11-2). When the RD16 control bit
(T1CON<7>) is set, the address for TMR1H is mapped
to a buffer register for the high byte of Timer1. A read
from TMR1L will load the contents of the high byte of
Timer1 into the Timer1 High Byte Buffer register. This
provides the user with the ability to accurately read all
16 bits of Timer1 without having to determine whether
a read of the high byte, followed by a read of the low
byte, has become invalid due to a rollover between
reads.
Oscillator
Freq.
C1
C2
Type
LP
32 kHz
27 pF(1)
27 pF(1)
Note 1: Microchip suggests these values as a
starting point in validating the oscillator
circuit.
2: Higher capacitance increases the stability
of the oscillator but also increases the
start-up time.
A write to the high byte of Timer1 must also take place
through the TMR1H Buffer register. The Timer1 high
byte is updated with the contents of TMR1H when a
write occurs to TMR1L. This allows a user to write all
16 bits to both the high and low bytes of Timer1 at once.
3: Since each resonator/crystal has its own
characteristics, the user should consult
the resonator/crystal manufacturer for
appropriate
values
of
external
components.
The high byte of Timer1 is not directly readable or
writable in this mode. All reads and writes must take
place through the Timer1 High Byte Buffer register.
Writes to TMR1H do not clear the Timer1 prescaler.
The prescaler is only cleared on writes to TMR1L.
4: Capacitor values are for design guidance
only.
11.3.1
USING TIMER1 AS A
CLOCK SOURCE
11.3 Timer1 Oscillator
The Timer1 oscillator is also available as a clock source
in power-managed modes. By setting the clock select
bits, SCS1:SCS0 (OSCCON<1:0>), to ‘01’, the device
switches to SEC_RUN mode; both the CPU and
peripherals are clocked from the Timer1 oscillator. If the
IDLEN bit (OSCCON<7>) is cleared and a SLEEP
instruction is executed, the device enters SEC_IDLE
mode. Additional details are available in Section 3.0
“Power-Managed Modes”.
An on-chip crystal oscillator circuit is incorporated
between pins T1OSI (input) and T1OSO (amplifier
output). It is enabled by setting the Timer1 Oscillator
Enable bit, T1OSCEN (T1CON<3>). The oscillator is a
low-power circuit rated for 32 kHz crystals. It will
continue to run during all power-managed modes. The
circuit for a typical oscillator is shown in Figure 11-3.
Table 11-1 shows the capacitor selection for the Timer1
oscillator.
Whenever the Timer1 oscillator is providing the clock
source, the Timer1 system clock status flag, T1RUN
(T1CON<6>), is set. This can be used to determine the
controller’s current clocking mode. It can also indicate
the clock source being currently used by the Fail-Safe
Clock Monitor. If the Clock Monitor is enabled and the
Timer1 oscillator fails while providing the clock, polling
the T1RUN bit will indicate whether the clock is being
provided by the Timer1 oscillator or another source.
The user must provide a software time delay to ensure
proper start-up of the Timer1 oscillator.
FIGURE 11-3:
EXTERNAL
COMPONENTS FOR THE
TIMER1 OSCILLATOR
C1
27 pF
PIC18F45J10
T1OSI
XTAL
32.768 kHz
T1OSO
C2
27 pF
Note:
See the Notes with Table 11-1 for additional
information about capacitor selection.
© 2007 Microchip Technology Inc.
Preliminary
DS39682C-page 117
PIC18F45J10 FAMILY
11.3.2
TIMER1 OSCILLATOR LAYOUT
CONSIDERATIONS
11.5 Resetting Timer1 Using the
ECCP/CCP Special Event Trigger
The Timer1 oscillator circuit draws very little power
during operation. Due to the low-power nature of the
oscillator, it may also be sensitive to rapidly changing
signals in close proximity.
If ECCP1/CCP1 or CCP2 are configured to generate a
Special
Event
Trigger
in Compare
mode
(CCPxM3:CCPxM0 = 1011), this signal will reset
Timer1. The trigger from CCP2 will also start an A/D
conversion if the A/D module is enabled (see
Section 14.2.1 “Special Event Trigger” for more
information).
The oscillator circuit, shown in Figure 11-3, should be
located as close as possible to the microcontroller.
There should be no circuits passing within the oscillator
circuit boundaries other than VSS or VDD.
The module must be configured as either a timer or a
synchronous counter to take advantage of this feature.
When used this way, the CCPRH:CCPRL register pair
effectively becomes a period register for Timer1.
If a high-speed circuit must be located near the oscilla-
tor (such as the CCP1 pin in Output Compare or PWM
mode, or the primary oscillator using the OSC2 pin), a
grounded guard ring around the oscillator circuit, as
shown in Figure 11-4, may be helpful when used on a
single-sided PCB or in addition to a ground plane.
If Timer1 is running in Asynchronous Counter mode,
this Reset operation may not work.
In the event that a write to Timer1 coincides with a
Special Event Trigger, the write operation will take
precedence.
FIGURE 11-4:
OSCILLATOR CIRCUIT
WITH GROUNDED
GUARD RING
Note:
The Special Event Triggers from the
ECCP1/CCPx module will not set the
TMR1IF interrupt flag bit (PIR1<0>).
VDD
VSS
11.6 Using Timer1 as a Real-Time Clock
OSC1
OSC2
Adding an external LP oscillator to Timer1 (such as the
one described in Section 11.3 “Timer1 Oscillator”
above) gives users the option to include RTC function-
ality to their applications. This is accomplished with an
inexpensive watch crystal to provide an accurate time
base and several lines of application code to calculate
the time. When operating in Sleep mode and using a
battery or supercapacitor as a power source, it can
completely eliminate the need for a separate RTC
device and battery backup.
RC0
RC1
RC2
The application code routine, RTCisr, shown in
Example 11-1, demonstrates a simple method to
increment a counter at one-second intervals using an
Interrupt Service Routine. Incrementing the TMR1
register pair to overflow triggers the interrupt and calls
the routine which increments the seconds counter by
one. Additional counters for minutes and hours are
incremented as the previous counter overflows.
Note: Not drawn to scale.
11.4 Timer1 Interrupt
The TMR1 register pair (TMR1H:TMR1L) increments
from 0000h to FFFFh and rolls over to 0000h. The
Timer1 interrupt, if enabled, is generated on overflow
which is latched in interrupt flag bit, TMR1IF
(PIR1<0>). This interrupt can be enabled or disabled
by setting or clearing the Timer1 Interrupt Enable bit,
TMR1IE (PIE1<0>).
Since the register pair is 16 bits wide, counting up to
overflow the register directly from a 32.768 kHz clock
would take 2 seconds. To force the overflow at the
required one-second intervals, it is necessary to
preload it. The simplest method is to set the MSb of
TMR1H with a BSF instruction. Note that the TMR1L
register is never preloaded or altered; doing so may
introduce cumulative error over many cycles.
For this method to be accurate, Timer1 must operate in
Asynchronous mode and the Timer1 overflow interrupt
must be enabled (PIE1<0> = 1) as shown in the
routine, RTCinit. The Timer1 oscillator must also be
enabled and running at all times.
DS39682C-page 118
Preliminary
© 2007 Microchip Technology Inc.
PIC18F45J10 FAMILY
EXAMPLE 11-1:
IMPLEMENTING A REAL-TIME CLOCK USING A TIMER1 INTERRUPT SERVICE
RTCinit
MOVLW
MOVWF
CLRF
80h
TMR1H
TMR1L
; Preload TMR1 register pair
; for 1 second overflow
MOVLW
MOVWF
CLRF
b’00001111’
T1CON
secs
; Configure for external clock,
; Asynchronous operation, external oscillator
; Initialize timekeeping registers
;
CLRF
mins
MOVLW
MOVWF
BSF
.12
hours
PIE1, TMR1IE
; Enable Timer1 interrupt
RETURN
RTCisr
BSF
BCF
INCF
MOVLW
CPFSGT
RETURN
CLRF
TMR1H, 7
PIR1, TMR1IF
secs, F
.59
; Preload for 1 sec overflow
; Clear interrupt flag
; Increment seconds
; 60 seconds elapsed?
secs
; No, done
secs
mins, F
.59
; Clear seconds
; Increment minutes
; 60 minutes elapsed?
INCF
MOVLW
CPFSGT
RETURN
CLRF
mins
; No, done
mins
hours, F
.23
; clear minutes
; Increment hours
; 24 hours elapsed?
INCF
MOVLW
CPFSGT
RETURN
CLRF
hours
; No, done
; Reset hours
; Done
hours
RETURN
TABLE 11-2: REGISTERS ASSOCIATED WITH TIMER1 AS A TIMER/COUNTER
Reset
Values
on page
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
INTCON
PIR1
GIE/GIEH PEIE/GIEL TMR0IE
INT0IE
TXIF
RBIE
TMR0IF
CCP1IF
CCP1IE
CCP1IP
INT0IF
TMR2IF
TMR2IE
TMR2IP
RBIF
43
45
45
45
44
44
44
PSPIF(1)
PSPIE(1)
PSPIP(1)
ADIF
ADIE
ADIP
RCIF
RCIE
RCIP
SSP1IF
SSP1IE
SSP1IP
TMR1IF
TMR1IE
TMR1IP
PIE1
TXIE
TXIP
IPR1
TMR1L
TMR1H
T1CON
Timer1 Register Low Byte
Timer1 Register High Byte
RD16
T1RUN T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON
Legend: Shaded cells are not used by the Timer1 module.
Note 1: These bits are not implemented on 28-pin devices and should be read as ‘0’.
© 2007 Microchip Technology Inc.
Preliminary
DS39682C-page 119
PIC18F45J10 FAMILY
NOTES:
DS39682C-page 120
Preliminary
© 2007 Microchip Technology Inc.
PIC18F45J10 FAMILY
12.1 Timer2 Operation
12.0 TIMER2 MODULE
In normal operation, TMR2 is incremented from 00h on
each clock (FOSC/4). A 4-bit counter/prescaler on the
clock input gives direct input, divide-by-4 and
divide-by-16 prescale options; these are selected by
the prescaler control bits, T2CKPS1:T2CKPS0
(T2CON<1:0>). The value of TMR2 is compared to that
of the period register, PR2, on each clock cycle. When
the two values match, the comparator generates a
match signal as the timer output. This signal also resets
the value of TMR2 to 00h on the next cycle and drives
the output counter/postscaler (see Section 12.2
“Timer2 Interrupt”).
The Timer2 timer module incorporates the following
features:
• 8-bit timer and period registers (TMR2 and PR2,
respectively)
• Readable and writable (both registers)
• Software programmable prescaler
(1:1, 1:4 and 1:16)
• Software programmable postscaler
(1:1 through 1:16)
• Interrupt on TMR2-to-PR2 match
• Optional use as the shift clock for the
MSSP module
The TMR2 and PR2 registers are both directly readable
and writable. The TMR2 register is cleared on any
device Reset, while the PR2 register initializes at FFh.
Both the prescaler and postscaler counters are cleared
on the following events:
The module is controlled through the T2CON register
(Register 12-1) which enables or disables the timer and
configures the prescaler and postscaler. Timer2 can be
shut off by clearing control bit, TMR2ON (T2CON<2>),
to minimize power consumption.
• a write to the TMR2 register
• a write to the T2CON register
A simplified block diagram of the module is shown in
Figure 12-1.
• any device Reset (Power-on Reset, MCLR Reset,
Watchdog Timer Reset or Brown-out Reset)
TMR2 is not cleared when T2CON is written.
REGISTER 12-1: T2CON: TIMER2 CONTROL REGISTER
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
T2OUTPS3 T2OUTPS2 T2OUTPS1 T2OUTPS0 TMR2ON T2CKPS1 T2CKPS0
bit 0
bit 7
bit 7
Unimplemented: Read as ‘0’
bit 6-3 T2OUTPS3:T2OUTPS0: Timer2 Output Postscale Select bits
0000= 1:1 Postscale
0001= 1:2 Postscale
•
•
•
1111= 1:16 Postscale
bit 2
TMR2ON: Timer2 On bit
1= Timer2 is on
0= Timer2 is off
bit 1-0 T2CKPS1:T2CKPS0: Timer2 Clock Prescale Select bits
00= Prescaler is 1
01= Prescaler is 4
1x= Prescaler is 16
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
© 2007 Microchip Technology Inc.
Preliminary
DS39682C-page 121
PIC18F45J10 FAMILY
12.2 Timer2 Interrupt
12.3 Timer2 Output
Timer2 can also generate an optional device interrupt.
The Timer2 output signal (TMR2-to-PR2 match) pro-
vides the input for the 4-bit output counter/postscaler.
This counter generates the TMR2 match interrupt flag
which is latched in TMR2IF (PIR1<1>). The interrupt is
enabled by setting the TMR2 Match Interrupt Enable
bit, TMR2IE (PIE1<1>).
The unscaled output of TMR2 is available primarily to
the CCP modules, where it is used as a time base for
operations in PWM mode.
Timer2 can be optionally used as the shift clock source
for the MSSP module operating in SPI mode.
Additional information is provided in Section 15.0
“Master Synchronous Serial Port (MSSP) Module”.
A range of 16 postscale options (from 1:1 through 1:16
inclusive) can be selected with the postscaler control
bits, T2OUTPS3:T2OUTPS0 (T2CON<6:3>).
FIGURE 12-1:
TIMER2 BLOCK DIAGRAM
4
1:1 to 1:16
Set TMR2IF
Postscaler
T2OUTPS3:T2OUTPS0
2
TMR2 Output
T2CKPS1:T2CKPS0
(to PWM or MSSP)
TMR2/PR2
Match
Reset
TMR2
1:1, 1:4, 1:16
Prescaler
PR2
FOSC/4
Comparator
8
8
8
Internal Data Bus
TABLE 12-1: REGISTERS ASSOCIATED WITH TIMER2 AS A TIMER/COUNTER
Reset
Values
on page
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
INTCON GIE/GIEH PEIE/GIEL TMR0IE
INT0IE
TXIF
RBIE
TMR0IF
CCP1IF
CCP1IE
CCP1IP
INT0IF
TMR2IF
TMR2IE
TMR2IP
RBIF
43
45
45
45
44
44
44
PIR1
PSPIF(1)
PSPIE(1)
PSPIP(1)
ADIF
ADIE
ADIP
RCIF
RCIE
RCIP
SSP1IF
SSP1IE
SSP1IP
TMR1IF
TMR1IE
TMR1IP
PIE1
TXIE
TXIP
IPR1
TMR2
T2CON
PR2
Timer2 Register
T2OUTPS3 T2OUTPS2 T2OUTPS1 T2OUTPS0 TMR2ON T2CKPS1 T2CKPS0
Timer2 Period Register
—
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the Timer2 module.
Note 1: These bits are not implemented on 28-pin devices and should be read as ‘0’.
DS39682C-page 122
Preliminary
© 2007 Microchip Technology Inc.
PIC18F45J10 FAMILY
The Capture and Compare operations described in this
chapter apply to all standard and Enhanced CCP
modules.
13.0 CAPTURE/COMPARE/PWM
(CCP) MODULES
PIC18F45J10 family devices all have two CCP
(Capture/Compare/PWM) modules. Each module
contains a 16-bit register which can operate as a 16-bit
Capture register, a 16-bit Compare register or a PWM
Master/Slave Duty Cycle register.
Note: Throughout this section and Section 14.0
“Enhanced Capture/Compare/PWM (ECCP)
Module”, references to the register and bit
names for CCP modules are referred to gener-
ically by the use of ‘x’ or ‘y’ in place of the
specific module number. Thus, “CCPxCON”
might refer to the control register for CCP1,
CCP2 or ECCP1. “CCPxCON” is used
throughout these sections to refer to the
module control register regardless of whether
the CCP module is a standard or Enhanced
implementation.
In 28-pin devices, the two standard CCP modules
(CCP1 and CCP2) operate as described in this chapter.
In 40/44-pin devices, CCP1 is implemented as an
Enhanced CCP module (ECCP1) with standard Capture
and Compare modes and Enhanced PWM modes. The
Enhanced CCP implementation is discussed in
Section 14.0 “Enhanced Capture/Compare/PWM
(ECCP) Module”.
REGISTER 13-1: CCPxCON REGISTER (CCP1, CCP2 MODULES IN 28-PIN DEVICES)
U-0
—
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
DCxB1
DCxB0
CCPxM3 CCPxM2 CCPxM1 CCPxM0
bit 0
bit 7
bit 7-6 Unimplemented: Read as ‘0’
bit 5-4 DCxB1:DCxB0: PWM Duty Cycle bit 1 and bit 0
Capture mode:
Unused.
Compare mode:
Unused.
PWM mode:
These bits are the two LSbs (bit 1 and bit 0) of the 10-bit PWM duty cycle. The eight MSbs
(DCx9:DCx2) of the duty cycle are found in CCPRxL.
bit 3-0 CCPxM3:CCPxM0: CCPx Mode Select bits
0000= Capture/Compare/PWM disabled (resets CCPx module)
0001= Reserved
0010= Compare mode, toggle output on match (CCPxIF bit is set)
0011= Reserved
0100= Capture mode, every falling edge
0101= Capture mode, every rising edge
0110= Capture mode, every 4th rising edge
0111= Capture mode, every 16th rising edge
1000= Compare mode: initialize CCPx pin low; on compare match, force CCPx pin high
(CCPxIF bit is set)
1001= Compare mode: initialize CCPx pin high; on compare match, force CCPx pin low
(CCPxIF bit is set)
1010= Compare mode: generate software interrupt on compare match (CCPxIF bit is set,
CCPx pin reflects I/O state)
1011= Compare mode: trigger special event, reset timer, start A/D conversion on
CCPx match (CCPxIF bit is set)
11xx= PWM mode
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
© 2007 Microchip Technology Inc.
Preliminary
DS39682C-page 123
PIC18F45J10 FAMILY
Both modules may be active at any given time and may
share the same timer resource if they are configured to
operate in the same mode (Capture/Compare or PWM)
at the same time. The interactions between the two
modules are summarized in Figure 13-1 and
Figure 13-2. In Timer1 in Asynchronous Counter mode,
the capture operation will not work.
13.1 CCP Module Configuration
Each Capture/Compare/PWM module is associated
with a control register (generically, CCPxCON) and a
data register (CCPRx). The data register, in turn, is
comprised of two 8-bit registers: CCPRxL (low byte)
and CCPRxH (high byte). All registers are both
readable and writable.
13.1.2
CCP2 PIN ASSIGNMENT
13.1.1
CCP MODULES AND TIMER
RESOURCES
The pin assignment for CCP2 (Capture input, Compare
and PWM output) can change, based on device config-
uration. The CCP2MX configuration bit determines
which pin CCP2 is multiplexed to. By default, it is
assigned to RC1 (CCP2MX = 1). If the configuration bit
is cleared, CCP2 is multiplexed with RB3.
The CCP modules utilize Timers 1 or 2, depending on
the mode selected. Timer1 is available to modules in
Capture or Compare modes, while Timer2 is available
for modules in PWM mode.
Changing the pin assignment of CCP2 does not auto-
matically change any requirements for configuring the
port pin. Users must always verify that the appropriate
TRIS register is configured correctly for CCP2
operation regardless of where it is located.
TABLE 13-1: ECCP/CCP MODE – TIMER
RESOURCE
ECCP/CCP Mode
Timer Resource
Capture
Compare
PWM
Timer1
Timer1
Timer2
TABLE 13-2: INTERACTIONS BETWEEN ECCP1/CCP1 AND CCP2 FOR TIMER RESOURCES
CCP1 Mode CCP2 Mode Interaction
Each module uses TMR1 as the time base.
Capture
Capture
Capture
Compare CCP2 can be configured for the Special Event Trigger to reset TMR1. Automatic A/D
conversions on the trigger event can also be done. Operation of ECCP1/CCP1 will be
affected.
Compare
Compare
Capture
ECCP1/CCP1 can be configured for the Special Event Trigger to reset TMR1. Operation
of CCP2 will be affected.
Compare Either module can be configured for the Special Event Trigger to reset TMR1. Automatic
A/D conversions on the CCP2 trigger event can be done.
Capture
Compare
PWM(1)
PWM(1)
PWM(1)
PWM(1)
PWM(1)
Capture
None
None
None
Compare None
PWM Both PWMs will have the same frequency and update rate (TMR2 interrupt).
Note 1: Includes standard and Enhanced PWM operation.
DS39682C-page 124
Preliminary
© 2007 Microchip Technology Inc.
PIC18F45J10 FAMILY
13.2.3
CCP PRESCALER
13.2 Capture Mode
There are four prescaler settings in Capture mode; they
are specified as part of the operating mode selected by
the mode select bits (CCPxM3:CCPxM0). Whenever
the CCP module is turned off or Capture mode is
disabled, the prescaler counter is cleared. This means
that any Reset will clear the prescaler counter.
In Capture mode, the CCPRxH:CCPRxL register pair
captures the 16-bit value of the TMR1 register when an
event occurs on the corresponding CCPx pin. An event
is defined as one of the following:
• every falling edge
• every rising edge
Switching from one capture prescaler to another may
generate an interrupt. Also, the prescaler counter will
not be cleared; therefore, the first capture may be from
• every 4th rising edge
• every 16th rising edge
a
non-zero prescaler. Example 13-1 shows the
The event is selected by the mode select bits,
CCPxM3:CCPxM0 (CCPxCON<3:0>). When a capture
is made, the interrupt request flag bit, CCPxIF, is set; it
must be cleared in software. If another capture occurs
before the value in register CCPRx is read, the old
captured value is overwritten by the new captured value.
recommended method for switching between capture
prescalers. This example also clears the prescaler
counter and will not generate the “false” interrupt.
EXAMPLE 13-1:
CHANGING BETWEEN
CAPTURE PRESCALERS
(CCP2 SHOWN)
13.2.1
CCP PIN CONFIGURATION
In Capture mode, the appropriate CCPx pin should be
configured as an input by setting the corresponding
TRIS direction bit.
CLRF
CCP2CON
; Turn CCP module off
MOVLW NEW_CAPT_PS ; Load WREG with the
; new prescaler mode
; value and CCP ON
; Load CCP2CON with
; this value
Note:
If RB3/CCP2 or RC1/CCP2 is configured
as an output, a write to the port can cause
a capture condition.
MOVWF CCP2CON
13.2.2
SOFTWARE INTERRUPT
When the Capture mode is changed, a false capture
interrupt may be generated. The user should keep the
CCPxIE interrupt enable bit clear to avoid false inter-
rupts. The interrupt flag bit, CCPxIF, should also be
cleared following any such change in operating mode.
FIGURE 13-1:
CAPTURE MODE OPERATION BLOCK DIAGRAM
Set CCP1IF
CCPR1H
CCPR1L
TMR1L
CCP1 pin
Prescaler
÷ 1, 4, 16
and
Edge Detect
TMR1H
4
4
CCP1CON<3:0>
Q1:Q4
Set CCP2IF
4
CCP2CON<3:0>
CCPR2H
TMR1H
CCPR2L
TMR1L
CCP2 pin
Prescaler
÷ 1, 4, 16
and
Edge Detect
© 2007 Microchip Technology Inc.
Preliminary
DS39682C-page 125
PIC18F45J10 FAMILY
13.3.2
TIMER1 MODE SELECTION
13.3 Compare Mode
Timer1 must be running in Timer mode or Synchro-
nized Counter mode if the CCP module is using the
compare feature. In Asynchronous Counter mode, the
compare operation may not work.
In Compare mode, the 16-bit CCPRx register value is
constantly compared against the TMR1 register value.
When a match occurs, the CCPx pin can be:
• driven high
• driven low
13.3.3
SOFTWARE INTERRUPT MODE
• toggled (high-to-low or low-to-high)
When the Generate Software Interrupt mode is chosen
(CCPxM3:CCPxM0 = 1010), the corresponding CCPx
pin is not affected. Only a CCP interrupt is generated,
if enabled and the CCPxIE bit is set.
• remain unchanged (that is, reflects the state of the
I/O latch)
The action on the pin is based on the value of the mode
select bits (CCPxM3:CCPxM0). At the same time, the
interrupt flag bit, CCPxIF, is set.
13.3.4
SPECIAL EVENT TRIGGER
Both CCP modules are equipped with a Special Event
Trigger. This is an internal hardware signal generated
in Compare mode to trigger actions by other modules.
The Special Event Trigger is enabled by selecting
the Compare Special Event Trigger mode
(CCPxM3:CCPxM0 = 1011).
13.3.1
CCP PIN CONFIGURATION
The user must configure the CCPx pin as an output by
clearing the appropriate TRIS bit.
Note:
Clearing the CCP2CON register will force
the RB3 or RC1 compare output latch
(depending on device configuration) to the
default low level. This is not the PORTB or
PORTC I/O data latch.
For either CCP module, the Special Event Trigger resets
the Timer register pair for whichever timer resource is
currently assigned as the module’s time base. This
allows the CCPRx registers to serve as a programmable
period register for either timer.
The Special Event Trigger for CCP2 can also start an
A/D conversion. In order to do this, the A/D converter
must already be enabled.
FIGURE 13-2:
COMPARE MODE OPERATION BLOCK DIAGRAM
Special Event Trigger
(Timer1 Reset)
Set CCP1IF
CCPR1H
CCPR1L
CCP1 pin
S
R
Q
Output
Logic
Compare
Match
Comparator
TRIS
Output Enable
4
CCP1CON<3:0>
TMR1H
TMR1L
Special Event Trigger
(Timer1 Reset, A/D Trigger)
Set CCP2IF
CCP2 pin
S
Q
Compare
Match
Output
Logic
Comparator
R
TRIS
Output Enable
4
CCPR2H
CCPR2L
CCP2CON<3:0>
DS39682C-page 126
Preliminary
© 2007 Microchip Technology Inc.
PIC18F45J10 FAMILY
TABLE 13-3: REGISTERS ASSOCIATED WITH CAPTURE, COMPARE AND TIMER1
Reset
Values
on page
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
INTCON
RCON
GIE/GIEH PEIE/GIEL TMR0IE
INT0IE
RI
RBIE
TO
TMR0IF
PD
INT0IF
POR
RBIF
BOR
43
42
45
45
45
45
45
45
46
46
44
44
44
45
45
45
45
45
45
IPEN
—
—
RCIF
RCIE
RCIP
—
PIR1
PSPIF(1)
PSPIE(1)
PSPIP(1)
OSCFIF
OSCFIE
OSCFIP
ADIF
ADIE
ADIP
CMIF
CMIE
CMIP
TXIF
TXIE
TXIP
—
SSP1IF
SSP1IE
SSP1IP
BCL1IF
BCL1IE
BCL1IP
CCP1IF
TMR2IF TMR1IF
PIE1
CCP1IE TMR2IE TMR1IE
CCP1IP TMR2IP TMR1IP
IPR1
PIR2
—
—
—
—
—
—
CCP2IF
CCP2IE
CCP2IP
PIE2
—
—
IPR2
—
—
TRISB
PORTB Data Direction Control Register
PORTC Data Direction Control Register
Timer1 Register Low Byte
TRISC
TMR1L
TMR1H
T1CON
CCPR1L
CCPR1H
CCP1CON
CCPR2L
CCPR2H
CCP2CON
Timer1 Register High Byte
RD16
T1RUN T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON
Capture/Compare/PWM Register 1 Low Byte
Capture/Compare/PWM Register 1 High Byte
P1M1(1)
P1M0(1)
DC1B1
DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0
Capture/Compare/PWM Register 2 Low Byte
Capture/Compare/PWM Register 2 High Byte
—
—
DC2B1
DC2B0 CCP2M3 CCP2M2 CCP2M1 CCP2M0
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by Capture/Compare or Timer1.
Note 1: These bits are not implemented on 28-pin devices and should be read as ‘0’.
© 2007 Microchip Technology Inc.
Preliminary
DS39682C-page 127
PIC18F45J10 FAMILY
13.4.1
PWM PERIOD
13.4 PWM Mode
The PWM period is specified by writing to the PR2
register. The PWM period can be calculated using the
following formula:
In Pulse-Width Modulation (PWM) mode, the CCPx pin
produces up to a 10-bit resolution PWM output. Since
the CCP2 pin is multiplexed with a PORTB or PORTC
data latch, the appropriate TRIS bit must be cleared to
make the CCP2 pin an output.
EQUATION 13-1:
PWM Period = [(PR2) + 1] • 4 • TOSC •
(TMR2 Prescale Value)
Note:
Clearing the CCP2CON register will force
the RB3 or RC1 output latch (depending on
device configuration) to the default low
level. This is not the PORTB or PORTC I/O
data latch.
PWM frequency is defined as 1/[PWM period].
When TMR2 is equal to PR2, the following three events
occur on the next increment cycle:
Figure 13-3 shows a simplified block diagram of the
CCP module in PWM mode.
• TMR2 is cleared
For a step-by-step procedure on how to set up the CCP
module for PWM operation, see Section 13.4.4
“Setup for PWM Operation”.
• The CCPx pin is set (exception: if PWM duty
cycle = 0%, the CCPx pin will not be set)
• The PWM duty cycle is latched from CCPRxL into
CCPRxH
FIGURE 13-3:
SIMPLIFIED PWM BLOCK
DIAGRAM
Note:
The Timer2 postscalers (see Section 12.0
“Timer2 Module”) are not used in the
determination of the PWM frequency. The
postscaler could be used to have a servo
update rate at a different frequency than
the PWM output.
CCPxCON<5:4>
Duty Cycle Registers
CCPRxL
13.4.2
PWM DUTY CYCLE
CCPRxH (Slave)
Comparator
CCPx Output
The PWM duty cycle is specified by writing to the
CCPRxL register and to the CCPxCON<5:4> bits. Up
to 10-bit resolution is available. The CCPRxL contains
the eight MSbs and the CCPxCON<5:4> contains the
two LSbs. This 10-bit value is represented by
CCPRxL:CCPxCON<5:4>. The following equation is
used to calculate the PWM duty cycle in time:
Q
R
S
(Note 1)
TMR2
Corresponding
TRIS bit
Comparator
PR2
Clear Timer,
CCP1 pin and
latch D.C.
EQUATION 13-2:
PWM Duty Cycle = (CCPRXL:CCPXCON<5:4>) •
TOSC • (TMR2 Prescale Value)
Note 1: The 8-bit TMR2 value is concatenated with the 2-bit
internal Q clock, or 2 bits of the prescaler, to create the
10-bit time base.
CCPRxL and CCPxCON<5:4> can be written to at any
time, but the duty cycle value is not latched into
CCPRxH until after a match between PR2 and TMR2
occurs (i.e., the period is complete). In PWM mode,
CCPRxH is a read-only register.
A PWM output (Figure 13-4) has a time base (period)
and a time that the output stays high (duty cycle).
The frequency of the PWM is the inverse of the
period (1/period).
FIGURE 13-4:
PWM OUTPUT
Period
Duty Cycle
TMR2 = PR2
TMR2 = Duty Cycle
TMR2 = PR2
DS39682C-page 128
Preliminary
© 2007 Microchip Technology Inc.
PIC18F45J10 FAMILY
The CCPRxH register and a 2-bit internal latch are
used to double-buffer the PWM duty cycle. This
double-buffering is essential for glitchless PWM
operation.
EQUATION 13-3:
FOSC
⎛
⎝
⎞
⎠
---------------
log
FPWM
PWM Resolution (max)
= ----------------------------- b i t s
log(2)
When the CCPRxH and 2-bit latch match TMR2,
concatenated with an internal 2-bit Q clock or 2 bits of
the TMR2 prescaler, the CCPx pin is cleared.
Note:
If the PWM duty cycle value is longer than
the PWM period, the CCP2 pin will not be
cleared.
The maximum PWM resolution (bits) for a given PWM
frequency is given by the equation:
TABLE 13-4: EXAMPLE PWM FREQUENCIES AND RESOLUTIONS AT 40 MHz
PWM Frequency
2.44 kHz
9.77 kHz
39.06 kHz 156.25 kHz 312.50 kHz 416.67 kHz
Timer Prescaler (1, 4, 16)
PR2 Value
16
FFh
10
4
1
1
3Fh
8
1
1Fh
7
1
FFh
10
FFh
10
17h
6.58
Maximum Resolution (bits)
13.4.3
PWM AUTO-SHUTDOWN
(CCP1 ONLY)
13.4.4
SETUP FOR PWM OPERATION
The following steps should be taken when configuring
the CCP module for PWM operation:
The PWM auto-shutdown features of the Enhanced CCP
module are also available to CCP1 in 28-pin devices. The
operation of this feature is discussed in detail in
Section 14.4.7 “Enhanced PWM Auto-Shutdown”.
1. Set the PWM period by writing to the PR2
register.
2. Set the PWM duty cycle by writing to the
CCPRxL register and CCPxCON<5:4> bits.
Auto-shutdown features are not available for CCP2.
3. Make the CCPx pin an output by clearing the
appropriate TRIS bit.
4. Set the TMR2 prescale value, then enable
Timer2 by writing to T2CON.
5. Configure the CCPx module for PWM operation.
© 2007 Microchip Technology Inc.
Preliminary
DS39682C-page 129
PIC18F45J10 FAMILY
TABLE 13-5: REGISTERS ASSOCIATED WITH PWM AND TIMER2
Reset
Values
on page
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
INTCON
RCON
PIR1
GIE/GIEH PEIE/GIEL TMR0IE
INT0IE
RI
RBIE
TO
TMR0IF
PD
INT0IF
POR
RBIF
BOR
43
42
45
45
45
46
46
44
44
44
45
45
45
45
45
45
45
45
IPEN
—
—
PSPIF(1)
PSPIE(1)
PSPIP(1)
ADIF
ADIE
ADIP
RCIF
RCIE
RCIP
TXIF
TXIE
TXIP
SSP1IF
SSP1IE
SSP1IP
CCP1IF
TMR2IF
TMR1IF
TMR1IE
TMR1IP
PIE1
CCP1IE TMR2IE
CCP1IP TMR2IP
IPR1
TRISB
TRISC
TMR2
PR2
PORTB Data Direction Control Register
PORTC Data Direction Control Register
Timer2 Register
Timer2 Period Register
T2CON
CCPR1L
—
T2OUTPS3 T2OUTPS2 T2OUTPS1 T2OUTPS0 TMR2ON T2CKPS1 T2CKPS0
Capture/Compare/PWM Register 1 Low Byte
CCPR1H Capture/Compare/PWM Register 1 High Byte
CCP1CON P1M1(1) P1M0(1)
DC1B1 DC1B0
CCPR2L Capture/Compare/PWM Register 2 Low Byte
CCPR2H Capture/Compare/PWM Register 2 High Byte
CCP2CON DC2B1 DC2B0
ECCP1AS ECCPASE ECCPAS2 ECCPAS1 ECCPAS0 PSSAC1 PSSAC0 PSSBD1(1) PSSBD0(1)
ECCP1DEL PRSEN
PDC6(1) PDC5(1) PDC4(1) PDC3(1) PDC2(1) PDC1(1) PDC0(1)
CCP1M3 CCP1M2 CCP1M1 CCP1M0
CCP2M3 CCP2M2 CCP2M1 CCP2M0
—
—
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PWM or Timer2.
Note 1: These bits are not implemented on 28-pin devices and should be read as ‘0’.
DS39682C-page 130
Preliminary
© 2007 Microchip Technology Inc.
PIC18F45J10 FAMILY
and restart. The Enhanced features are discussed in
detail in Section 14.4 “Enhanced PWM Mode”.
Capture, Compare and single output PWM functions of
the ECCP module are the same as described for the
standard CCP module.
14.0 ENHANCED CAPTURE/
COMPARE/PWM (ECCP)
MODULE
Note:
The ECCP module is implemented only in
40/44-pin devices.
The control register for the Enhanced CCP module is
shown in Register 14-1. It differs from the CCP1CON
register in PIC18F24J10/25J10 devices in that the two
Most Significant bits are implemented to control PWM
functionality.
In
PIC18F44J10/45J10
devices,
ECCP1
is
implemented as
a
standard CCP module with
Enhanced PWM capabilities. These include the
provisions for 2 or 4 output channels, user-selectable
polarity, dead-band control and automatic shutdown
REGISTER 14-1: CCP1CON REGISTER (ECCP1 MODULE, 40/44-PIN DEVICES)
R/W-0
P1M1
R/W-0
P1M0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
DC1B1
DC1B0
CCP1M3 CCP1M2 CCP1M1 CCP1M0
bit 0
bit 7
bit 7-6
P1M1:P1M0: Enhanced PWM Output Configuration bits
If CCP1M3:CCP1M2 = 00, 01, 10:
xx= P1A assigned as Capture/Compare input/output; P1B, P1C, P1D assigned as port pins
If CCP1M3:CCP1M2 = 11:
00= Single output: P1A modulated; P1B, P1C, P1D assigned as port pins
01= Full-bridge output forward: P1D modulated; P1A active; P1B, P1C inactive
10= Half-bridge output: P1A, P1B modulated with dead-band control; P1C, P1D assigned
as port pins
11= Full-bridge output reverse: P1B modulated; P1C active; P1A, P1D inactive
bit 5-4
DC1B1:DC1B0: PWM Duty Cycle bit 1 and bit 0
Capture mode:
Unused.
Compare mode:
Unused.
PWM mode:
These bits are the two LSbs of the 10-bit PWM duty cycle. The eight MSbs of the duty cycle are
found in CCPR1L.
bit 3-0
CCP1M3:CCP1M0: Enhanced CCP Mode Select bits
0000= Capture/Compare/PWM off (resets ECCP module)
0001= Reserved
0010= Compare mode, toggle output on match
0011= Capture mode
0100= Capture mode, every falling edge
0101= Capture mode, every rising edge
0110= Capture mode, every 4th rising edge
0111= Capture mode, every 16th rising edge
1000= Compare mode, initialize CCP1 pin low, set output on compare match (set CCP1IF)
1001= Compare mode, initialize CCP1 pin high, clear output on compare match (set CCP1IF)
1010= Compare mode, generate software interrupt only, CCP1 pin reverts to I/O state
1011= Compare mode, trigger special event (ECCP resets TMR1, sets CCP1IF bit)
1100= PWM mode; P1A, P1C active-high; P1B, P1D active-high
1101= PWM mode; P1A, P1C active-high; P1B, P1D active-low
1110= PWM mode; P1A, P1C active-low; P1B, P1D active-high
1111= PWM mode; P1A, P1C active-low; P1B, P1D active-low
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
© 2007 Microchip Technology Inc.
Preliminary
DS39682C-page 131
PIC18F45J10 FAMILY
In addition to the expanded range of modes available
through the CCP1CON register and ECCP1AS
register, the ECCP module has an additional register
associated with Enhanced PWM operation and
auto-shutdown features. It is:
14.2 Capture and Compare Modes
Except for the operation of the Special Event Trigger
discussed below, the Capture and Compare modes of
the ECCP module are identical in operation to that of
CCP2. These are discussed in detail in Section 13.2
“Capture Mode” and Section 13.3 “Compare
Mode”. No changes are required when moving
between 28-pin and 40/44-pin devices.
• ECCP1DEL (Dead-Band Delay)
14.1 ECCP Outputs and Configuration
The Enhanced CCP module may have up to four PWM
outputs, depending on the selected operating mode.
These outputs, designated P1A through P1D, are
multiplexed with I/O pins on PORTC and PORTD. The
outputs that are active depend on the ECCP operating
mode selected. The pin assignments are summarized
in Table 14-1.
14.2.1
SPECIAL EVENT TRIGGER
The Special Event Trigger output of ECCP1 resets the
TMR1 register pair. This allows the CCPR1 register to
effectively be a 16-bit programmable period register for
Timer1.
14.3 Standard PWM Mode
To configure the I/O pins as PWM outputs, the proper
PWM mode must be selected by setting the
P1M1:P1M0 and CCP1M3:CCP1M0 bits. The
appropriate TRISC and TRISD direction bits for the port
pins must also be set as outputs.
When configured in Single Output mode, the ECCP
module functions identically to the standard CCP
module in PWM mode, as described in Section 13.4
“PWM Mode”. This is also sometimes referred to as
“Compatible CCP” mode, as in Table 14-1.
14.1.1
ECCP MODULES AND TIMER
RESOURCES
Note:
When setting up single output PWM
operations, users are free to use either of
the processes described in Section 13.4.4
“Setup for PWM Operation” or
Section 14.4.9 “Setup for PWM Opera-
tion”. The latter is more generic and will
work for either single or multi-output PWM.
Like the standard CCP modules, the ECCP module can
utilize Timers 1 or 2, depending on the mode selected.
Timer1 is available for modules in Capture or Compare
modes, while Timer2 is available for modules in PWM
mode. Interactions between the standard and
Enhanced CCP modules are identical to those
described for standard CCP modules. Additional
details on timer resources are provided in
Section 13.1.1
“CCP
Modules
and
Timer
Resources”.
TABLE 14-1: PIN ASSIGNMENTS FOR VARIOUS ECCP1 MODES
CCP1CON
ECCP Mode
RC2
RD5
RD6
RD7
Configuration
All 40/44-pin Devices:
Compatible CCP
Dual PWM
00xx 11xx
10xx 11xx
x1xx 11xx
CCP1
P1A
RD5/PSP5
P1B
RD6/PSP6
RD6/PSP6
P1C
RD7/PSP7
RD7/PSP7
P1D
Quad PWM
P1A
P1B
Legend: x= Don’t care. Shaded cells indicate pin assignments not used by ECCP1 in a given mode.
DS39682C-page 132
Preliminary
© 2007 Microchip Technology Inc.
PIC18F45J10 FAMILY
14.4.1
PWM PERIOD
14.4 Enhanced PWM Mode
The PWM period is specified by writing to the PR2
register. The PWM period can be calculated using the
following equation.
The Enhanced PWM mode provides additional PWM
output options for a broader range of control applica-
tions. The module is a backward compatible version of
the standard CCP module and offers up to four outputs,
designated P1A through P1D. Users are also able to
select the polarity of the signal (either active-high or
active-low). The module’s output mode and polarity are
configured by setting the P1M1:P1M0 and
CCP1M3:CCP1M0 bits of the CCP1CON register.
EQUATION 14-1:
PWM Period = [(PR2) + 1] • 4 • TOSC •
(TMR2 Prescale Value)
PWM frequency is defined as 1/[PWM period]. When
TMR2 is equal to PR2, the following three events occur
on the next increment cycle:
Figure 14-1 shows a simplified block diagram of PWM
operation. All control registers are double-buffered and
are loaded at the beginning of a new PWM cycle (the
period boundary when Timer2 resets) in order to pre-
vent glitches on any of the outputs. The exception is the
PWM Delay register, ECCP1DEL, which is loaded at
either the duty cycle boundary or the period boundary
(whichever comes first). Because of the buffering, the
module waits until the assigned timer resets instead of
starting immediately. This means that Enhanced PWM
waveforms do not exactly match the standard PWM
waveforms, but are instead offset by one full instruction
cycle (4 TOSC).
• TMR2 is cleared
• The CCP1 pin is set (if PWM duty cycle = 0%, the
CCP1 pin will not be set)
• The PWM duty cycle is copied from CCPR1L into
CCPR1H
Note:
The Timer2 postscaler (see Section 12.0
“Timer2 Module”) is not used in the
determination of the PWM frequency. The
postscaler could be used to have a servo
update rate at a different frequency than
the PWM output.
As before, the user must manually configure the
appropriate TRIS bits for output.
FIGURE 14-1:
SIMPLIFIED BLOCK DIAGRAM OF THE ENHANCED PWM MODULE
CCP1CON<5:4>
P1M1<1:0>
CCP1M<3:0>
4
Duty Cycle Registers
2
CCPR1L
CCP1/P1A
CCP1/P1A
P1B
TRISx<x>
TRISx<x>
TRISx<x>
TRISx<x>
CCPR1H (Slave)
Comparator
P1B
Output
Controller
R
S
Q
P1C
P1C
P1D
(Note 1)
TMR2
P1D
Comparator
PR2
Clear Timer,
set CCP1 pin and
latch D.C.
ECCP1DEL
Note: The 8-bit TMR2 register is concatenated with the 2-bit internal Q clock, or 2 bits of the prescaler, to create the 10-bit
time base.
© 2007 Microchip Technology Inc.
Preliminary
DS39682C-page 133
PIC18F45J10 FAMILY
14.4.2
PWM DUTY CYCLE
Note:
If the PWM duty cycle value is longer than
the PWM period, the CCP1 pin will not be
cleared.
The PWM duty cycle is specified by writing to the
CCPR1L register and to the CCP1CON<5:4> bits. Up
to 10-bit resolution is available. The CCPR1L register
contains the eight MSbs and the CCP1CON<5:4>
contains the two LSbs. This 10-bit value is represented
by CCPR1L:CCP1CON<5:4>. The PWM duty cycle is
calculated by the following equation:
14.4.3
PWM OUTPUT CONFIGURATIONS
The P1M1:P1M0 bits in the CCP1CON register allow
one of four configurations:
• Single Output
EQUATION 14-2:
• Half-Bridge Output
• Full-Bridge Output, Forward mode
• Full-Bridge Output, Reverse mode
PWM Duty Cycle = (CCPR1L:CCP1CON<5:4>) •
TOSC • (TMR2 Prescale Value)
The Single Output mode is the standard PWM mode
discussed in Section 14.4 “Enhanced PWM Mode”.
The Half-Bridge and Full-Bridge Output modes are
covered in detail in the sections that follow.
CCPR1L and CCP1CON<5:4> can be written to at any
time, but the duty cycle value is not copied into
CCPR1H until a match between PR2 and TMR2 occurs
(i.e., the period is complete). In PWM mode, CCPR1H
is a read-only register.
The general relationship of the outputs in all
configurations is summarized in Figure 14-2.
The CCPR1H register and a 2-bit internal latch are
used to double-buffer the PWM duty cycle. This
double-buffering is essential for glitchless PWM opera-
tion. When the CCPR1H and 2-bit latch match TMR2,
concatenated with an internal 2-bit Q clock or two bits
of the TMR2 prescaler, the CCP1 pin is cleared. The
maximum PWM resolution (bits) for a given PWM
frequency is given by the following equation:
EQUATION 14-3:
FOSC
log
(
)
FPWM
bits
PWM Resolution (max) =
log(2)
TABLE 14-2: EXAMPLE PWM FREQUENCIES AND RESOLUTIONS AT 40 MHz
PWM Frequency
2.44 kHz
9.77 kHz
39.06 kHz 156.25 kHz 312.50 kHz 416.67 kHz
Timer Prescaler (1, 4, 16)
PR2 Value
16
FFh
10
4
1
1
3Fh
8
1
1Fh
7
1
FFh
10
FFh
10
17h
6.58
Maximum Resolution (bits)
DS39682C-page 134
Preliminary
© 2007 Microchip Technology Inc.
PIC18F45J10 FAMILY
FIGURE 14-2:
PWM OUTPUT RELATIONSHIPS (ACTIVE-HIGH STATE)
0
PR2 + 1
Duty
Cycle
SIGNAL
CCP1CON
<7:6>
Period
P1A Modulated
P1A Modulated
P1B Modulated
P1A Active
(Single Output)
00
10
(1)
(1)
Delay
Delay
(Half-Bridge)
P1B Inactive
P1C Inactive
P1D Modulated
P1A Inactive
P1B Modulated
P1C Active
(Full-Bridge,
Forward)
01
(Full-Bridge,
Reverse)
11
P1D Inactive
FIGURE 14-3:
PWM OUTPUT RELATIONSHIPS (ACTIVE-LOW STATE)
0
PR2 + 1
SIGNAL
CCP1CON
Duty
Cycle
<7:6>
Period
P1A Modulated
P1A Modulated
P1B Modulated
P1A Active
(Single Output)
00
10
(1)
(1)
Delay
Delay
(Half-Bridge)
P1B Inactive
P1C Inactive
P1D Modulated
P1A Inactive
P1B Modulated
P1C Active
(Full-Bridge,
Forward)
01
(Full-Bridge,
Reverse)
11
P1D Inactive
Relationships:
•
•
•
Period = 4 * TOSC * (PR2 + 1) * (TMR2 Prescale Value)
Duty Cycle = TOSC * (CCPR1L<7:0>:CCP1CON<5:4>) * (TMR2 Prescale Value)
Delay = 4 * TOSC * (ECCP1DEL<6:0>)
Note 1: Dead-band delay is programmed using the ECCP1DEL register (see Section 14.4.6 “Programmable
Dead-Band Delay”).
© 2007 Microchip Technology Inc.
Preliminary
DS39682C-page 135
PIC18F45J10 FAMILY
14.4.4
HALF-BRIDGE MODE
FIGURE 14-4:
HALF-BRIDGE PWM
OUTPUT
In the Half-Bridge Output mode, two pins are used as
outputs to drive push-pull loads. The PWM output signal
is output on the P1A pin, while the complementary PWM
output signal is output on the P1B pin (Figure 14-4). This
mode can be used for half-bridge applications, as shown
in Figure 14-5, or for full-bridge applications where four
power switches are being modulated with two PWM
signals.
Period
Period
Duty Cycle
(2)
(2)
P1A
td
td
P1B
In Half-Bridge Output mode, the programmable dead-
band delay can be used to prevent shoot-through
current in half-bridge power devices. The value of bits,
PDC6:PDC0, sets the number of instruction cycles
before the output is driven active. If the value is greater
than the duty cycle, the corresponding output remains
inactive during the entire cycle. See Section 14.4.6
“Programmable Dead-Band Delay” for more details
of the dead-band delay operations.
(1)
(1)
(1)
td = Dead-Band Delay
Note 1: At this time, the TMR2 register is equal to the
PR2 register.
2: Output signals are shown as active-high.
Since the P1A and P1B outputs are multiplexed with
the PORTC<2> and PORTD<5> data latches, the
TRISC<2> and TRISD<5> bits must be cleared to
configure P1A and P1B as outputs.
FIGURE 14-5:
EXAMPLES OF HALF-BRIDGE OUTPUT MODE APPLICATIONS
V+
Standard Half-Bridge Circuit (“Push-Pull”)
PIC18F4XJ10
FET
Driver
+
V
-
P1A
Load
FET
Driver
+
V
-
P1B
V-
Half-Bridge Output Driving a Full-Bridge Circuit
V+
PIC18F4X5J10
FET
FET
Driver
Driver
P1A
Load
FET
FET
Driver
Driver
P1B
V-
DS39682C-page 136
Preliminary
© 2007 Microchip Technology Inc.
PIC18F45J10 FAMILY
P1A, P1B, P1C and P1D outputs are multiplexed with
the PORTC<2> and PORTD<7:5> data latches. The
TRISC<2> and TRISD<7:5> bits must be cleared to
make the P1A, P1B, P1C and P1D pins outputs.
14.4.5
FULL-BRIDGE MODE
In Full-Bridge Output mode, four pins are used as
outputs; however, only two outputs are active at a time.
In the Forward mode, pin P1A is continuously active
and pin P1D is modulated. In the Reverse mode, pin
P1C is continuously active and pin P1B is modulated.
These are illustrated in Figure 14-6.
FIGURE 14-6:
FULL-BRIDGE PWM OUTPUT
Forward Mode
Period
(2)
P1A
Duty Cycle
(2)
(2)
P1B
P1C
(2)
P1D
(1)
(1)
Reverse Mode
Period
Duty Cycle
(2)
P1A
(2)
P1B
(2)
P1C
(2)
P1D
(1)
(1)
Note 1: At this time, the TMR2 register is equal to the PR2 register.
Note 2: Output signal is shown as active-high.
© 2007 Microchip Technology Inc.
Preliminary
DS39682C-page 137
PIC18F45J10 FAMILY
FIGURE 14-7:
EXAMPLE OF FULL-BRIDGE APPLICATION
V+
PIC18F4XJ10
QC
QA
FET
Driver
FET
Driver
P1A
Load
P1B
FET
Driver
FET
Driver
P1C
P1D
QD
QB
V-
Figure 14-9 shows an example where the PWM
direction changes from forward to reverse at a near
100% duty cycle. At time t1, the outputs P1A and P1D
become inactive while output P1C becomes active. In
this example, since the turn-off time of the power
devices is longer than the turn-on time, a shoot-through
current may flow through power devices, QC and QD
(see Figure 14-7), for the duration of ‘t’. The same
phenomenon will occur to power devices, QA and QB,
for PWM direction change from reverse to forward.
14.4.5.1
Direction Change in Full-Bridge Mode
In the Full-Bridge Output mode, the P1M1 bit in the
CCP1CON register allows the user to control the
forward/reverse direction. When the application firm-
ware changes this direction control bit, the module will
assume the new direction on the next PWM cycle.
Just before the end of the current PWM period, the
modulated outputs (P1B and P1D) are placed in their
inactive state, while the unmodulated outputs (P1A and
P1C) are switched to drive in the opposite direction.
This occurs in the time interval, 4 TOSC * (Timer2
Prescale Value), before the next PWM period begins.
The Timer2 prescaler will be either 1, 4 or 16, depend-
ing on the value of the T2CKPS1:T2CKPS0 bits
(T2CON<1:0>). During the interval from the switch of
the unmodulated outputs to the beginning of the next
period, the modulated outputs (P1B and P1D) remain
inactive. This relationship is shown in Figure 14-8.
If changing PWM direction at high duty cycle is required
for an application, one of the following requirements
must be met:
1. Reduce PWM for
changing directions.
a PWM period before
2. Use switch drivers that can drive the switches off
faster than they can drive them on.
Other options to prevent shoot-through current may
exist.
Note that in the Full-Bridge Output mode, the ECCP1
module does not provide any dead-band delay. In
general, since only one output is modulated at all times,
dead-band delay is not required. However, there is a
situation where a dead-band delay might be required.
This situation occurs when both of the following
conditions are true:
1. The direction of the PWM output changes when
the duty cycle of the output is at or near 100%.
2. The turn-off time of the power switch, including
the power device and driver circuit, is greater
than the turn-on time.
DS39682C-page 138
Preliminary
© 2007 Microchip Technology Inc.
PIC18F45J10 FAMILY
FIGURE 14-8:
PWM DIRECTION CHANGE
(1)
Period
Period
SIGNAL
P1A (Active-High)
P1B (Active-High)
DC
P1C (Active-High)
P1D (Active-High)
(Note 2)
DC
Note 1: The direction bit in the ECCP1 Control register (CCP1CON<7>) is written any time during the PWM cycle.
2: When changing directions, the P1A and P1C signals switch before the end of the current PWM cycle at intervals
of 4 TOSC, 16 TOSC or 64 TOSC, depending on the Timer2 prescaler value. The modulated P1B and P1D signals
are inactive at this time.
FIGURE 14-9:
PWM DIRECTION CHANGE AT NEAR 100% DUTY CYCLE
Forward Period
Reverse Period
t1
(1)
(1)
P1A
P1B
DC
(1)
(1)
P1C
P1D
DC
(2)
t
ON
(1)
(1)
External Switch C
External Switch D
(3)
t
OFF
(2,3)
Potential
t = t
– t
ON
OFF
Shoot-Through
(1)
Current
Note 1: All signals are shown as active-high.
2: t is the turn-on delay of power switch QC and its driver.
ON
3: t
is the turn-off delay of power switch QD and its driver.
OFF
© 2007 Microchip Technology Inc.
Preliminary
DS39682C-page 139
PIC18F45J10 FAMILY
A shutdown event can be caused by either of the
comparator modules, a low level on the Fault input pin
(FLT0) or any combination of these three sources. The
comparators may be used to monitor a voltage input
proportional to a current being monitored in the bridge
14.4.6
PROGRAMMABLE DEAD-BAND
DELAY
Note:
Programmable dead-band delay is not
implemented in 28-pin devices with
standard CCP modules.
circuit. If the voltage exceeds
a threshold, the
comparator switches state and triggers a shutdown.
Alternatively, a low digital signal on FLT0 can also trigger
a shutdown. The auto-shutdown feature can be disabled
by not selecting any auto-shutdown sources. The auto-
shutdown sources to be used are selected using the
ECCPAS2:ECCPAS0 bits (bits<6:4> of the ECCP1AS
register).
In half-bridge applications, where all power switches
are modulated at the PWM frequency at all times, the
power switches normally require more time to turn off
than to turn on. If both the upper and lower power
switches are switched at the same time (one turned on
and the other turned off), both switches may be on for
a short period of time until one switch completely turns
off. During this brief interval, a very high current (shoot-
through current) may flow through both power
switches, shorting the bridge supply. To avoid this
potentially destructive shoot-through current from
flowing during switching, turning on either of the power
switches is normally delayed to allow the other switch
to completely turn off.
When a shutdown occurs, the output pins are
asynchronously placed in their shutdown states, spec-
ified by the PSSAC1:PSSAC0 and PSSBD1:PSSBD0
bits (ECCPAS3:ECCPAS0). Each pin pair (P1A/P1C
and P1B/P1D) may be set to drive high, drive low or be
tri-stated (not driving). The ECCPASE bit
(ECCP1AS<7>) is also set to hold the Enhanced PWM
outputs in their shutdown states.
In the Half-Bridge Output mode, a digitally programmable
dead-band delay is available to avoid shoot-through
current from destroying the bridge power switches. The
delay occurs at the signal transition from the nonactive
state to the active state. See Figure 14-4 for an
illustration. Bits PDC6:PDC0 of the ECCP1DEL register
(Register 14-2) set the delay period in terms of microcon-
troller instruction cycles (TCY or 4 TOSC). These bits are
not available in 28-pin devices as the standard CCP
module does not support half-bridge operation.
The ECCPASE bit is set by hardware when a shutdown
event occurs. If automatic restarts are not enabled, the
ECCPASE bit is cleared by firmware when the cause of
the shutdown clears. If automatic restarts are enabled,
the ECCPASE bit is automatically cleared when the
cause of the auto-shutdown has cleared.
If the ECCPASE bit is set when a PWM period begins,
the PWM outputs remain in their shutdown state for that
entire PWM period. When the ECCPASE bit is cleared,
the PWM outputs will return to normal operation at the
beginning of the next PWM period.
14.4.7
ENHANCED PWM AUTO-SHUTDOWN
When the ECCP1 is programmed for any of the
Enhanced PWM modes, the active output pins may be
configured for auto-shutdown. Auto-shutdown immedi-
ately places the Enhanced PWM output pins into a
defined shutdown state when a shutdown event occurs.
Note:
Writing to the ECCPASE bit is disabled
while a shutdown condition is active.
REGISTER 14-2: ECCP1DEL: PWM DEAD-BAND DELAY REGISTER
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
PRSEN
PDC6(1)
PDC5(1)
PDC4(1)
PDC3(1)
PDC2(1)
PDC1(1)
PDC0(1)
bit 7
bit 0
bit 7
PRSEN: PWM Restart Enable bit
1= Upon auto-shutdown, the ECCPASE bit clears automatically once the shutdown event
goes away; the PWM restarts automatically
0= Upon auto-shutdown, ECCPASE must be cleared in software to restart the PWM
bit 6-0
PDC6:PDC0: PWM Delay Count bits(1)
Delay time, in number of FOSC/4 (4 * TOSC) cycles, between the scheduled and actual time for
a PWM signal to transition to active.
Note 1: Reserved on 28-pin devices; maintain these bits clear.
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
DS39682C-page 140
Preliminary
© 2007 Microchip Technology Inc.
PIC18F45J10 FAMILY
REGISTER 14-3: ECCP1AS: ENHANCED CAPTURE/COMPARE/PWM AUTO-SHUTDOWN
CONTROL REGISTER
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
ECCPASE ECCPAS2 ECCPAS1 ECCPAS0 PSSAC1 PSSAC0 PSSBD1(1) PSSBD0(1)
bit 7
bit 0
bit 7
ECCPASE: ECCP Auto-Shutdown Event Status bit
1= A shutdown event has occurred; ECCP outputs are in shutdown state
0= ECCP outputs are operating
bit 6-4
ECCPAS2:ECCPAS0: ECCP Auto-Shutdown Source Select bits
111= FLT0, Comparator 1 or Comparator 2
110= FLT0 or Comparator 2
101= FLT0 or Comparator 1
100= FLT0
011= Either Comparator 1 or 2
010= Comparator 2 output
001= Comparator 1 output
000= Auto-shutdown is disabled
bit 3-2
bit 1-0
PSSAC1:PSSAC0: Pins A and C Shutdown State Control bits
1x= Pins A and C are tri-state (40/44-pin devices);
PWM output is tri-state (28-pin devices)
01= Drive Pins A and C to ‘1’
00= Drive Pins A and C to ‘0’
PSSBD1:PSSBD0: Pins B and D Shutdown State Control bits(1)
1x= Pins B and D tri-state
01= Drive Pins B and D to ‘1’
00= Drive Pins B and D to ‘0’
Note 1: Reserved on 28-pin devices; maintain these bits clear.
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
© 2007 Microchip Technology Inc.
Preliminary
DS39682C-page 141
PIC18F45J10 FAMILY
14.4.7.1
Auto-Shutdown and Automatic
Restart
14.4.8
START-UP CONSIDERATIONS
When the ECCP module is used in the PWM mode, the
application hardware must use the proper external pull-
up and/or pull-down resistors on the PWM output pins.
When the microcontroller is released from Reset, all of
the I/O pins are in the high-impedance state. The
external circuits must keep the power switch devices in
the OFF state until the microcontroller drives the I/O
pins with the proper signal levels, or activates the PWM
output(s).
The auto-shutdown feature can be configured to allow
automatic restarts of the module following a shutdown
event. This is enabled by setting the PRSEN bit of the
ECCP1DEL register (ECCP1DEL<7>).
In Shutdown mode with PRSEN = 1(Figure 14-10), the
ECCPASE bit will remain set for as long as the cause
of the shutdown continues. When the shutdown condi-
tion clears, the ECCPASE bit is cleared. If PRSEN = 0
(Figure 14-11), once a shutdown condition occurs, the
ECCPASE bit will remain set until it is cleared by firm-
ware. Once ECCPASE is cleared, the Enhanced PWM
will resume at the beginning of the next PWM period.
The CCP1M1:CCP1M0 bits (CCP1CON<1:0>) allow
the user to choose whether the PWM output signals are
active-high or active-low for each pair of PWM output
pins (P1A/P1C and P1B/P1D). The PWM output
polarities must be selected before the PWM pins are
configured as outputs. Changing the polarity configura-
tion while the PWM pins are configured as outputs is
not recommended, since it may result in damage to the
application circuits.
Note:
Writing to the ECCPASE bit is disabled
while a shutdown condition is active.
Independent of the PRSEN bit setting, if the auto-
shutdown source is one of the comparators, the
shutdown condition is a level. The ECCPASE bit
cannot be cleared as long as the cause of the shutdown
persists.
The P1A, P1B, P1C and P1D output latches may not be
in the proper states when the PWM module is initialized.
Enabling the PWM pins for output at the same time as
the ECCP module may cause damage to the applica-
tion circuit. The ECCP module must be enabled in the
proper output mode and complete a full PWM cycle
before configuring the PWM pins as outputs. The com-
pletion of a full PWM cycle is indicated by the TMR2IF
bit being set as the second PWM period begins.
The Auto-Shutdown mode can be forced by writing a ‘1’
to the ECCPASE bit.
FIGURE 14-10:
PWM AUTO-SHUTDOWN (PRSEN = 1, AUTO-RESTART ENABLED)
PWM Period
Shutdown Event
ECCPASE bit
PWM Activity
Normal PWM
Start of
PWM Period
PWM
Resumes
Shutdown
Event Occurs Event Clears
Shutdown
FIGURE 14-11:
PWM AUTO-SHUTDOWN (PRSEN = 0, AUTO-RESTART DISABLED)
PWM Period
Shutdown Event
ECCPASE bit
PWM Activity
Normal PWM
ECCPASE
Cleared by
Firmware
Start of
PWM Period
Shutdown
Shutdown
PWM
Resumes
Event Occurs Event Clears
DS39682C-page 142
Preliminary
© 2007 Microchip Technology Inc.
PIC18F45J10 FAMILY
14.4.9
SETUP FOR PWM OPERATION
14.4.10 OPERATION IN POWER-MANAGED
MODES
The following steps should be taken when configuring
the ECCP module for PWM operation:
In Sleep mode, all clock sources are disabled. Timer2
will not increment and the state of the module will not
change. If the CCP1 pin is driving a value, it will con-
tinue to drive that value. When the device wakes up, it
will continue from this state. If Two-Speed Start-ups are
enabled, the initial start-up frequency from INTOSC
and the postscaler may not be stable immediately.
1. Configure the PWM pins, P1A and P1B (and
P1C and P1D, if used), as inputs by setting the
corresponding TRIS bits.
2. Set the PWM period by loading the PR2 register.
3. If auto-shutdown is required:
• Disable auto-shutdown (ECCPASE = 0)
In PRI_IDLE mode, the primary clock will continue to
clock the ECCP module without change. In all other
power-managed modes, the selected power-managed
mode clock will clock Timer2. Other power-managed
mode clocks will most likely be different than the
primary clock frequency.
• Configure source (FLT0, Comparator 1 or
Comparator 2)
• Wait for non-shutdown condition
4. Configure the ECCP module for the desired
PWM mode and configuration by loading the
CCP1CON register with the appropriate values:
14.4.10.1 Operation with Fail-Safe
Clock Monitor
• Select one of the available output
configurations and direction with the
P1M1:P1M0 bits.
If the Fail-Safe Clock Monitor is enabled, a clock failure
will force the device into the power-managed RC_RUN
mode and the OSCFIF bit (PIR2<7>) will be set. The
ECCP will then be clocked from the internal oscillator
clock source, which may have a different clock
frequency than the primary clock.
• Select the polarities of the PWM output
signals with the CCP1M3:CCP1M0 bits.
5. Set the PWM duty cycle by loading the CCPR1L
register and CCP1CON<5:4> bits.
6. For Half-Bridge Output mode, set the dead-
band delay by loading ECCP1DEL<6:0> with
the appropriate value.
See the previous section for additional details.
14.4.11 EFFECTS OF A RESET
7. If auto-shutdown operation is required, load the
ECCP1AS register:
Both Power-on Reset and subsequent Resets will force
all ports to Input mode and the CCP registers to their
Reset states.
• Select the auto-shutdown sources using the
ECCPAS2:ECCPAS0 bits.
• Select the shutdown states of the PWM
output pins using the PSSAC1:PSSAC0 and
PSSBD1:PSSBD0 bits.
This forces the Enhanced CCP module to reset to a
state compatible with the standard CCP module.
• Set the ECCPASE bit (ECCP1AS<7>).
• Configure the comparators using the CMCON
register.
• Configure the comparator inputs as analog
inputs.
8. If auto-restart operation is required, set the
PRSEN bit (ECCP1DEL<7>).
9. Configure and start TMR2:
• Clear the TMR2 interrupt flag bit by clearing
the TMR2IF bit (PIR1<1>).
• Set the TMR2 prescale value by loading the
T2CKPS bits (T2CON<1:0>).
• Enable Timer2 by setting the TMR2ON bit
(T2CON<2>).
10. Enable PWM outputs after a new PWM cycle
has started:
• Wait until TMRn overflows (TMRnIF bit is set).
• Enable the CCP1/P1A, P1B, P1C and/or P1D
pin outputs by clearing the respective TRIS
bits.
• Clear the ECCPASE bit (ECCP1AS<7>).
© 2007 Microchip Technology Inc.
Preliminary
DS39682C-page 143
PIC18F45J10 FAMILY
TABLE 14-3: REGISTERS ASSOCIATED WITH ECCP1 MODULE AND TIMER1
Reset
Values
on page
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
INTCON
RCON
PIR1
GIE/GIEH PEIE/GIEL
TMR0IE
—
INT0IE
RI
RBIE
TO
TMR0IF
PD
INT0IF
POR
RBIF
43
42
45
45
45
45
45
45
46
46
46
44
44
44
44
44
44
45
45
45
45
45
IPEN
—
BOR
(1)
PSPIF
PSPIE
PSPIP
ADIF
ADIE
ADIP
CMIF
CMIE
CMIP
RCIF
RCIE
RCIP
—
TXIF
TXIE
TXIP
—
SSP1IF
SSP1IE
SSP1IP
BCL1IF
BCL1IE
BCL1IP
CCP1IF
CCP1IE
CCP1IP
—
TMR2IF
TMR2IE
TMR2IP
—
TMR1IF
TMR1IE
TMR1IP
CCP2IF
CCP2IE
CCP2IP
(1)
(1)
PIE1
IPR1
PIR2
OSCFIF
OSCFIE
OSCFIP
PIE2
—
—
—
—
IPR2
—
—
—
—
TRISB
TRISC
PORTB Data Direction Control Register
PORTC Data Direction Control Register
PORTD Data Direction Control Register
Timer1 Register Low Byte
(1)
TRISD
TMR1L
TMR1H
T1CON
TMR2
Timer1 Register High Byte
RD16
Timer2 Register
T2OUTPS3 T2OUTPS2 T2OUTPS1 T2OUTPS0 TMR2ON T2CKPS1 T2CKPS0
T1RUN
T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON
T2CON
PR2
—
Timer2 Period Register
CCPR1L
CCPR1H
CCP1CON
Capture/Compare/PWM Register 1 Low Byte
Capture/Compare/PWM Register 1 High Byte
(1)
(1)
P1M1
P1M0
DC1B1
DC1B0
CCP1M3
PSSAC1
CCP1M2 CCP1M1 CCP1M0
(1)
(1)
ECCP1AS ECCPASE ECCPAS2 ECCPAS1 ECCPAS0
PSSAC0 PSSBD1
PSSBD0
(1)
(1)
(1)
(1)
(1)
(1)
(1)
ECCP1DEL
PRSEN
PDC6
PDC5
PDC4
PDC3
PDC2
PDC1
PDC0
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used during ECCP operation.
Note 1: These registers and/or bits are not implemented on 28-pin devices and should be read as ‘0’.
DS39682C-page 144
Preliminary
© 2007 Microchip Technology Inc.
PIC18F45J10 FAMILY
15.3 SPI Mode
15.0 MASTER SYNCHRONOUS
SERIAL PORT (MSSP)
MODULE
The SPI mode allows 8 bits of data to be synchronously
transmitted and received simultaneously. All four
modes of SPI are supported. To accomplish
communication, typically three pins are used:
15.1 Master SSP (MSSP) Module
Overview
• Serial Data Out (SDOx) – RC5/SDO1 or
RD2/PSP2/SDO2
The Master Synchronous Serial Port (MSSP) module is
a serial interface, useful for communicating with other
peripheral or microcontroller devices. These peripheral
devices may be serial EEPROMs, shift registers,
display drivers, A/D converters, etc. The MSSP module
can operate in one of two modes:
• Serial Data In (SDIx) – RC4/SDI1/SDA1 or
RD1/PSP1/SDI2/SDA2
• Serial Clock (SCKx) – RC3/SCK1/SCL1 or
RD0/PSP0/SCK2/SCL2
Additionally, a fourth pin may be used when in a Slave
mode of operation:
• Serial Peripheral Interface (SPI™)
• Inter-Integrated Circuit (I2C™)
- Full Master mode
• Slave Select (SSx) – RA5/AN4/SS1/C2OUT or
RD3/PSP3/SS2
- Slave mode (with general address call)
The I2C interface supports the following modes in
hardware:
Figure 15-1 shows the block diagram of the MSSP
module when operating in SPI mode.
FIGURE 15-1:
MSSP BLOCK DIAGRAM
(SPI™ MODE)
• Master mode
• Multi-Master mode
• Slave mode
Internal
Data Bus
PIC18F24J10/25J10 (28-pin) devices have one MSSP
module designated as MSSP1. PIC18F44J10/45J10
(40/44-pin) devices have two MSSP modules,
designated as MSSP1 and MSSP2. Each module
operates independently of the other.
Read
Write
SSPxBUF reg
SSPxSR reg
RC4 or RD1
RC5 or RD2
Note:
Throughout this section, generic refer-
ences to an MSSP module in any of its
operating modes may be interpreted as
being equally applicable to MSSP1 or
MSSP2. Register names and module I/O
signals use the generic designator ‘x’ to
indicate the use of a numeral to distinguish
Shift
Clock
bit 0
a
particular module, when required.
RA5 or RD3
SSx Control
Enable
Control bit names are not individuated.
Edge
Select
15.2 Control Registers
Each MSSP module has three associated control
registers. These include a status register (SSPxSTAT)
and two control registers (SSPxCON1 and
SSPxCON2). The use of these registers and their indi-
vidual configuration bits differ significantly depending
on whether the MSSP module is operated in SPI or I2C
mode.
2
Clock Select
SSPM3:SSPM0
SMP:CKE
4
TMR2 Output
(
)
2
2
Edge
Select
TOSC
Additional details are provided under the individual
sections.
Prescaler
4, 16, 64
RC3 or RD0
Note:
In devices with more than one MSSP
module, it is very important to pay close
attention to SSPCON register names.
SSP1CON1 and SSP1CON2 control
different operational aspects of the same
Data to TX/RX in SSPxSR
TRIS bit
Note: Only port I/O names are used in this diagram for
the sake of brevity. Refer to the text for a full list
of multiplexed functions.
module,
while
SSP1CON1
and
SSP2CON1 control the same features for
two different modules.
© 2007 Microchip Technology Inc.
Preliminary
DS39682C-page 145
PIC18F45J10 FAMILY
SSPxSR is the shift register used for shifting data in or
out. SSPxBUF is the buffer register to which data
bytes are written to or read from.
15.3.1
REGISTERS
Each MSSP module has four registers for SPI mode
operation. These are:
In receive operations, SSPxSR and SSPxBUF
together create a double-buffered receiver. When
SSPxSR receives a complete byte, it is transferred to
SSPxBUF and the SSPxIF interrupt is set.
• MSSP Control Register 1 (SSPxCON1)
• MSSP Status Register (SSPxSTAT)
• Serial Receive/Transmit Buffer Register
(SSPxBUF)
During transmission, the SSPxBUF is not
double-buffered. A write to SSPxBUF will write to both
SSPxBUF and SSPxSR.
• MSSP Shift Register (SSPxSR) – Not directly
accessible
SSPxCON1 and SSPxSTAT are the control and status
registers in SPI mode operation. The SSPxCON1
register is readable and writable. The lower 6 bits of
the SSPxSTAT are read-only. The upper two bits of the
SSPxSTAT are read/write.
REGISTER 15-1: SSPxSTAT: MSSPx STATUS REGISTER (SPI™ MODE)
R/W-0
SMP
R/W-0
CKE
R-0
D/A
R-0
P
R-0
S
R-0
R-0
UA
R-0
BF
R/W
bit 7
bit 0
bit 7
bit 6
SMP: Sample bit
SPI Master mode:
1= Input data sampled at end of data output time
0= Input data sampled at middle of data output time
SPI Slave mode:
SMP must be cleared when SPI is used in Slave mode.
CKE: SPI Clock Select bit
1= Transmit occurs on transition from active to Idle clock state
0= Transmit occurs on transition from Idle to active clock state
Note:
Polarity of clock state is set by the CKP bit (SSPxCON1<4>).
bit 5
bit 4
D/A: Data/Address bit
Used in I2C mode only.
P: Stop bit
Used in I2C mode only. This bit is cleared when the MSSP module is disabled, SSPEN is
cleared.
bit 3
bit 2
bit 1
bit 0
S: Start bit
Used in I2C mode only.
R/W: Read/Write Information bit
Used in I2C mode only.
UA: Update Address bit
Used in I2C mode only.
BF: Buffer Full Status bit (Receive mode only)
1= Receive complete, SSPxBUF is full
0= Receive not complete, SSPxBUF is empty
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
DS39682C-page 146
Preliminary
© 2007 Microchip Technology Inc.
PIC18F45J10 FAMILY
REGISTER 15-2: SSPxCON1: MSSPx CONTROL REGISTER 1 (SPI™ MODE)
R/W-0
WCOL
R/W-0
R/W-0
R/W-0
CKP
R/W-0
R/W-0
R/W-0
R/W-0
SSPOV
SSPEN
SSPM3
SSPM2
SSPM1
SSPM0
bit 7
bit 0
bit 7
bit 6
WCOL: Write Collision Detect bit (Transmit mode only)
1= The SSPxBUF register is written while it is still transmitting the previous word
(must be cleared in software)
0= No collision
SSPOV: Receive Overflow Indicator bit
SPI Slave mode:
1= A new byte is received while the SSPxBUF register is still holding the previous data. In case
of overflow, the data in SSPxSR is lost. Overflow can only occur in Slave mode. The user
must read the SSPxBUF, even if only transmitting data, to avoid setting overflow (must be
cleared in software).
0= No overflow
Note:
In Master mode, the overflow bit is not set since each new reception (and
transmission) is initiated by writing to the SSPxBUF register.
bit 5
bit 4
SSPEN: Master Synchronous Serial Port Enable bit
1= Enables serial port and configures SCKx, SDOx, SDIx and SSx as serial port pins
0= Disables serial port and configures these pins as I/O port pins
Note:
When enabled, these pins must be properly configured as input or output.
CKP: Clock Polarity Select bit
1= Idle state for clock is a high level
0= Idle state for clock is a low level
bit 3-0 SSPM3:SSPM0: Master Synchronous Serial Port Mode Select bits
0101= SPI Slave mode, clock = SCKx pin, SSx pin control disabled, SSx can be used as I/O pin
0100= SPI Slave mode, clock = SCKx pin, SSx pin control enabled
0011= SPI Master mode, clock = TMR2 output/2
0010= SPI Master mode, clock = FOSC/64
0001= SPI Master mode, clock = FOSC/16
0000= SPI Master mode, clock = FOSC/4
Note:
Bit combinations not specifically listed here are either reserved or implemented in
I2C mode only.
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
© 2007 Microchip Technology Inc.
Preliminary
DS39682C-page 147
PIC18F45J10 FAMILY
SSPxBUF register during transmission/reception of data
will be ignored and the Write Collision detect bit, WCOL
(SSPxCON1<7>), will be set. User software must clear
the WCOL bit so that it can be determined if the following
write(s) to the SSPxBUF register completed
successfully.
15.3.2
OPERATION
When initializing the SPI, several options need to be
specified. This is done by programming the appropriate
control bits (SSPxCON1<5:0> and SSPxSTAT<7:6>).
These control bits allow the following to be specified:
• Master mode (SCKx is the clock output)
• Slave mode (SCKx is the clock input)
• Clock Polarity (Idle state of SCKx)
When the application software is expecting to receive
valid data, the SSPxBUF should be read before the next
byte of data to transfer is written to the SSPxBUF. The
Buffer Full bit, BF (SSPxSTAT<0>), indicates when
SSPxBUF has been loaded with the received data
(transmission is complete). When the SSPxBUF is read,
the BF bit is cleared. This data may be irrelevant if the
SPI is only a transmitter. Generally, the MSSP interrupt
is used to determine when the transmission/reception
has completed. The SSPxBUF must be read and/or
written. If the interrupt method is not going to be used,
then software polling can be done to ensure that a write
collision does not occur. Example 15-1 shows the
loading of the SSP1BUF (SSP1SR) for data
transmission.
• Data Input Sample Phase (middle or end of data
output time)
• Clock Edge (output data on rising/falling edge of
SCKx)
• Clock Rate (Master mode only)
• Slave Select mode (Slave mode only)
Each MSSP consists of a transmit/receive shift register
(SSPxSR) and a buffer register (SSPxBUF). The
SSPxSR shifts the data in and out of the device, MSb
first. The SSPxBUF holds the data that was written to the
SSPxSR until the received data is ready. Once the 8 bits
of data have been received, that byte is moved to the
SSPxBUF register. Then, the Buffer Full detect bit BF
(SSPxSTAT<0>) and the interrupt flag bit SSPxIF are
set. This double-buffering of the received data
(SSPxBUF) allows the next byte to start reception before
reading the data that was just received. Any write to the
The SSPxSR is not directly readable or writable and
can only be accessed by addressing the SSPxBUF
register. Additionally, the SSPxSTAT register indicates
the various status conditions.
EXAMPLE 15-1:
LOADING THE SSP1BUF (SSP1SR) REGISTER
LOOP
BTFSS
BRA
SSP1STAT, BF
LOOP
;Has data been received (transmit complete)?
;No
MOVF
SSP1BUF, W
;WREG reg = contents of SSP1BUF
MOVWF
RXDATA
;Save in user RAM, if data is meaningful
MOVF
MOVWF
TXDATA, W
SSP1BUF
;W reg = contents of TXDATA
;New data to xmit
DS39682C-page 148
Preliminary
© 2007 Microchip Technology Inc.
PIC18F45J10 FAMILY
Any serial port function that is not desired may be
overridden by programming the corresponding data
direction (TRIS) register to the opposite value.
15.3.3
ENABLING SPI I/O
To enable the serial port, MSSP Enable bit, SSPEN
(SSPxCON1<5>), must be set. To reset or reconfigure
SPI mode, clear the SSPEN bit, reinitialize the
SSPxCON registers and then set the SSPEN bit. This
configures the SDIx, SDOx, SCKx and SSx pins as
serial port pins. For the pins to behave as the serial port
function, some must have their data direction bits (in
the TRIS register) appropriately programmed as
follows:
15.3.4
TYPICAL CONNECTION
Figure 15-2 shows a typical connection between two
microcontrollers. The master controller (Processor 1)
initiates the data transfer by sending the SCKx signal.
Data is shifted out of both shift registers on their pro-
grammed clock edge and latched on the opposite edge
of the clock. Both processors should be programmed to
the same Clock Polarity (CKP), then both controllers
would send and receive data at the same time.
Whether the data is meaningful (or dummy data)
depends on the application software. This leads to
three scenarios for data transmission:
• SDIx is automatically controlled by the SPI module
• SDOx must have TRISC<5> (or TRISD<2>) bit
cleared
• SCKx (Master mode) must have TRISC<3> (or
TRISD<0>) bit cleared
• SCKx (Slave mode) must have TRISC<3> (or
TRISD<0>) bit set
• Master sends data – Slave sends dummy data
• Master sends data – Slave sends data
• SSx must have TRISA<5> (or TRISD<3>) bit set
• Master sends dummy data – Slave sends data
FIGURE 15-2:
SPI™ MASTER/SLAVE CONNECTION
SPI™ Master SSPM3:SSPM0 = 00xxb
SPI™ Slave SSPM3:SSPM0 = 010xb
SDIx
SDOx
Serial Input Buffer
(SSPxBUF)
Serial Input Buffer
(SSPxBUF)
SDIx
SDOx
Shift Register
(SSPxSR)
Shift Register
(SSPxSR)
LSb
MSb
MSb
LSb
Serial Clock
SCKx
SCKx
PROCESSOR 1
PROCESSOR 2
© 2007 Microchip Technology Inc.
Preliminary
DS39682C-page 149
PIC18F45J10 FAMILY
The clock polarity is selected by appropriately
programming the CKP bit (SSPxCON1<4>). This then,
would give waveforms for SPI communication as
shown in Figure 15-3, Figure 15-5 and Figure 15-6,
where the MSB is transmitted first. In Master mode, the
SPI clock rate (bit rate) is user-programmable to be one
of the following:
15.3.5
MASTER MODE
The master can initiate the data transfer at any time
because it controls the SCKx. The master determines
when the slave (Processor 2, Figure 15-2) will
broadcast data by the software protocol.
In Master mode, the data is transmitted/received as
soon as the SSPxBUF register is written to. If the SPI
is only going to receive, the SDOx output could be dis-
abled (programmed as an input). The SSPxSR register
will continue to shift in the signal present on the SDIx
pin at the programmed clock rate. As each byte is
received, it will be loaded into the SSPxBUF register as
if a normal received byte (interrupts and status bits
appropriately set). This could be useful in receiver
applications as a “Line Activity Monitor” mode.
• FOSC/4 (or TCY)
• FOSC/16 (or 4 • TCY)
• FOSC/64 (or 16 • TCY)
• Timer2 output/2
This allows a maximum data rate (at 40 MHz) of
10.00 Mbps.
Figure 15-3 shows the waveforms for Master mode.
When the CKE bit is set, the SDOx data is valid before
there is a clock edge on SCKx. The change of the input
sample is shown based on the state of the SMP bit. The
time when the SSPxBUF is loaded with the received
data is shown.
FIGURE 15-3:
SPI™ MODE WAVEFORM (MASTER MODE)
Write to
SSPxBUF
SCKx
(CKP = 0
CKE = 0)
SCKx
(CKP = 1
CKE = 0)
4 Clock
Modes
SCKx
(CKP = 0
CKE = 1)
SCKx
(CKP = 1
CKE = 1)
bit 6
bit 6
bit 2
bit 2
bit 5
bit 5
bit 4
bit 4
bit 1
bit 1
bit 0
bit 0
SDOx
(CKE = 0)
bit 7
bit 7
bit 3
bit 3
SDOx
(CKE = 1)
SDIx
(SMP = 0)
bit 0
bit 7
Input
Sample
(SMP = 0)
SDIx
(SMP = 1)
bit 0
bit 7
Input
Sample
(SMP = 1)
SSPxIF
Next Q4 Cycle
after Q2↓
SSPxSR to
SSPxBUF
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© 2007 Microchip Technology Inc.
PIC18F45J10 FAMILY
SDOx pin is driven. When the SSx pin goes high, the
SDOx pin is no longer driven, even if in the middle of a
transmitted byte and becomes a floating output.
External pull-up/pull-down resistors may be desirable
depending on the application.
15.3.6
SLAVE MODE
In Slave mode, the data is transmitted and received as
the external clock pulses appear on SCKx. When the
last bit is latched, the SSPxIF interrupt flag bit is set.
Before enabling the module in SPI Slave mode, the
clock line must match the proper Idle state. The clock
line can be observed by reading the SCKx pin. The Idle
state is determined by the CKP bit (SSPxCON1<4>).
Note 1: When the SPI is in Slave mode with SSx pin
control enabled (SSPxCON1<3:0> = 0100),
the SPI module will reset if the SSx pin is set
to VDD.
While in Slave mode, the external clock is supplied by
the external clock source on the SCKx pin. This
external clock must meet the minimum high and low
times as specified in the electrical specifications.
2: If the SPI is used in Slave mode with CKE
set, then the SSx pin control must be
enabled.
When the SPI module resets, the bit counter is forced
to ‘0’. This can be done by either forcing the SSx pin to
a high level or clearing the SSPEN bit.
While in Sleep mode, the slave can transmit/receive
data. When a byte is received, the device will wake-up
from Sleep.
To emulate two-wire communication, the SDOx pin can
be connected to the SDIx pin. When the SPI needs to
operate as a receiver, the SDOx pin can be configured
as an input. This disables transmissions from the
SDOx. The SDIx can always be left as an input (SDIx
function) since it cannot create a bus conflict.
15.3.7
SLAVE SELECT
SYNCHRONIZATION
The SSx pin allows a Synchronous Slave mode. The
SPI must be in Slave mode with SSx pin control
enabled (SSPxCON1<3:0> = 04h). When the SSx pin
is low, transmission and reception are enabled and the
FIGURE 15-4:
SLAVE SYNCHRONIZATION WAVEFORM
SSx
SCKx
(CKP = 0
CKE = 0)
SCKx
(CKP = 1
CKE = 0)
Write to
SSPxBUF
bit 6
bit 7
bit 7
bit 0
SDOx
bit 7
SDIx
(SMP = 0)
bit 0
bit 7
Input
Sample
(SMP = 0)
SSPxIF
Interrupt
Flag
Next Q4 Cycle
after Q2
↓
SSPxSR to
SSPxBUF
© 2007 Microchip Technology Inc.
Preliminary
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PIC18F45J10 FAMILY
FIGURE 15-5:
SPI™ MODE WAVEFORM (SLAVE MODE WITH CKE = 0)
SSx
Optional
SCKx
(CKP = 0
CKE = 0)
SCKx
(CKP = 1
CKE = 0)
Write to
SSPxBUF
bit 6
bit 2
bit 5
bit 4
bit 3
bit 1
bit 0
SDOx
bit 7
SDIx
(SMP = 0)
bit 0
bit 7
Input
Sample
(SMP = 0)
SSPxIF
Interrupt
Flag
Next Q4 Cycle
after Q2↓
SSPxSR to
SSPxBUF
FIGURE 15-6:
SPI™ MODE WAVEFORM (SLAVE MODE WITH CKE = 1)
SSx
Not Optional
SCKx
(CKP = 0
CKE = 1)
SCKx
(CKP = 1
CKE = 1)
Write to
SSPxBUF
bit 6
bit 3
bit 2
bit 5
bit 4
bit 1
bit 0
SDOx
bit 7
bit 7
SDIx
(SMP = 0)
bit 0
Input
Sample
(SMP = 0)
SSPxIF
Interrupt
Flag
Next Q4 Cycle
after Q2↓
SSPxSR to
SSPxBUF
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Preliminary
© 2007 Microchip Technology Inc.
PIC18F45J10 FAMILY
15.3.8
OPERATION IN POWER-MANAGED
MODES
15.3.10 BUS MODE COMPATIBILITY
Table 15-1 shows the compatibility between the
standard SPI modes and the states of the CKP and
CKE control bits.
In SPI Master mode, module clocks may be operating
at a different speed than when in full power mode; in
the case of Sleep mode, all clocks are halted.
TABLE 15-1: SPI™ BUS MODES
In Idle modes, a clock is provided to the peripherals.
That clock should be from the primary clock source, the
secondary clock (Timer1 oscillator at 32.768 kHz) or
the INTOSC source. See Section 2.6 “Clock Sources
and Oscillator Switching” for additional information.
Control Bits State
Standard SPI™ Mode
Terminology
CKP
CKE
0, 0
0, 1
1, 0
1, 1
0
0
1
1
1
0
1
0
In most cases, the speed that the master clocks SPI
data is not important; however, this should be
evaluated for each system.
If MSSP interrupts are enabled, they can wake the con-
troller from Sleep mode, or one of the Idle modes, when
the master completes sending data. If an exit from
Sleep or Idle mode is not desired, MSSP interrupts
should be disabled.
There is also an SMP bit which controls when the data
is sampled.
15.3.11 SPI CLOCK SPEED AND MODULE
INTERACTIONS
If the Sleep mode is selected, all module clocks are
halted and the transmission/reception will remain in
that state until the devices wakes. After the device
returns to Run mode, the module will resume
transmitting and receiving data.
Because MSSP1 and MSSP2 are independent
modules, they can operate simultaneously at different
data rates. Setting the SSPM3:SSPM0 bits of the
SSPxCON1 register determines the rate for the
corresponding module.
In SPI Slave mode, the SPI Transmit/Receive Shift
register operates asynchronously to the device. This
allows the device to be placed in any power-managed
mode and data to be shifted into the SPI
Transmit/Receive Shift register. When all 8 bits have
been received, the MSSP interrupt flag bit will be set
and if enabled, will wake the device.
An exception is when both modules use Timer2 as a
time base in Master mode. In this instance, any
changes to the Timer2 operation will affect both MSSP
modules equally. If different bit rates are required for
each module, the user should select one of the other
three time base options for one of the modules.
15.3.9
EFFECTS OF A RESET
A Reset disables the MSSP module and terminates the
current transfer.
© 2007 Microchip Technology Inc.
Preliminary
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TABLE 15-2: REGISTERS ASSOCIATED WITH SPI™ OPERATION
Reset
Values
on page
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
INTCON
PIR1
GIE/GIEH PEIE/GIEL TMR0IE
INT0IE
TXIF
TXIE
TXIP
—
RBIE
SSP1IF
SSP1IE
SSP1IP
—
TMR0IF
CCP1IF
CCP1IE
CCP1IP
—
INT0IF
RBIF
43
45
45
45
45
45
45
46
46
46
44
44
44
46
46
46
PSPIF(1)
PSPIE(1)
PSPIP(1)
SSP2IF
SSP2IE
SSP2IP
—
ADIF
ADIE
RCIF
RCIE
RCIP
—
TMR2IF
TMR1IF
PIE1
TMR2IE TMR1IE
TMR2IP TMR1IP
IPR1
ADIP
PIR3
BCL2IF
BCL2IE
BCL2IP
—
—
—
—
—
PIE3
—
—
—
—
IPR3
—
—
—
—
—
—
TRISA
TRISC
TRISD(1)
TRISA5
TRISC5
TRISD5
—
TRISA3
TRISC3
TRISD3
TRISA2
TRISC2
TRISD2
TRISA1
TRISC1
TRISD1
TRISA0
TRISC0
TRISD0
TRISC7
TRISD7
TRISC6
TRISD6
TRISC4
TRISD4
SSP1BUF MSSP1 Receive Buffer/Transmit Register
SSP1CON1 WCOL
SSP1STAT SMP
SSPOV
CKE
SSPEN
D/A
CKP
P
SSPM3
S
SSPM2
R/W
SSPM1
UA
SSPM0
BF
SSP2BUF MSSP2 Receive Buffer/Transmit Register
SSP2CON1 WCOL
SSP2STAT SMP
SSPOV
CKE
SSPEN
D/A
CKP
P
SSPM3
S
SSPM2
R/W
SSPM1
UA
SSPM0
BF
Legend: Shaded cells are not used by the MSSP module in SPI™ mode.
Note 1: These registers and/or bits are not implemented on 28-pin devices and should be read as ‘0’.
DS39682C-page 154
Preliminary
© 2007 Microchip Technology Inc.
PIC18F45J10 FAMILY
2
15.4.1
REGISTERS
15.4 I C Mode
The MSSP module has six registers for I2C operation.
These are:
The MSSP module in I2C mode fully implements all
master and slave functions (including general call
support) and provides interrupts on Start and Stop bits
in hardware to determine a free bus (multi-master
function). The MSSP module implements the standard
mode specifications as well as 7-bit and 10-bit
addressing.
• MSSP Control Register 1 (SSPxCON1)
• MSSP Control Register 2 (SSPxCON2)
• MSSP Status Register (SSPxSTAT)
• Serial Receive/Transmit Buffer Register
(SSPxBUF)
Two pins are used for data transfer:
• MSSP Shift Register (SSPxSR) – Not directly
accessible
• Serial clock (SCLx) – RC3/SCK1/SCL1 or
RD0/PSP0/SCK2/SCL2
• MSSP Address Register (SSPxADD)
• Serial data (SDAx) – RC4/SDI1/SDA1 or
RD1/PSP1/SDI2/SDA2
SSPxCON1, SSPxCON2 and SSPxSTAT are the
control and status registers in I2C mode operation. The
SSPxCON1 and SSPxCON2 registers are readable and
writable. The lower 6 bits of the SSPxSTAT are
read-only. The upper 2 bits of the SSPxSTAT are
read/write.
The user must configure these pins as inputs by setting
the TRISC<4:3> or TRISD<1:0> bits.
FIGURE 15-7:
MSSP BLOCK DIAGRAM
(I2C™ MODE)
SSPxSR is the shift register used for shifting data in or
out. SSPxBUF is the buffer register to which data
bytes are written to or read from.
Internal
Data Bus
SSPxADD register holds the slave device address
when the MSSP is configured in I2C Slave mode.
When the MSSP is configured in Master mode, the
lower seven bits of SSPxADD act as the Baud Rate
Generator reload value.
Read
Write
RC3 or
RD0
SSPxBUF reg
Shift
Clock
In receive operations, SSPxSR and SSPxBUF
together create a double-buffered receiver. When
SSPxSR receives a complete byte, it is transferred to
SSPxBUF and the SSPxIF interrupt is set.
SSPxSR reg
LSb
RC4 or
RD1
MSb
During transmission, the SSPxBUF is not
double-buffered. A write to SSPxBUF will write to both
SSPxBUF and SSPxSR.
Match Detect
Addr Match
SSPxADD reg
Start and
Stop bit Detect
Set, Reset
S, P bits
(SSPxSTAT reg)
Note: Only port I/O names are used in this diagram for
the sake of brevity. Refer to the text for a full list
of multiplexed functions.
© 2007 Microchip Technology Inc.
Preliminary
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REGISTER 15-3: SSPxSTAT: MSSPx STATUS REGISTER (I2C™ MODE)
R/W-0
SMP
R/W-0
CKE
R-0
D/A
R-0
P
R-0
S
R-0
R-0
UA
R-0
BF
R/W
bit 7
bit 0
bit 7
bit 6
bit 5
SMP: Slew Rate Control bit
In Master or Slave mode:
1 = Slew rate control disabled for Standard Speed mode (100 kHz and 1 MHz)
0 = Slew rate control enabled for High-Speed mode (400 kHz)
CKE: SMBus Select bit
In Master or Slave mode:
1= Enable SMBus specific inputs
0= Disable SMBus specific inputs
D/A: Data/Address bit
In Master mode:
Reserved.
In Slave mode:
1= Indicates that the last byte received or transmitted was data
0= Indicates that the last byte received or transmitted was address
bit 4
bit 3
bit 2
P: Stop bit
1= Indicates that a Stop bit has been detected last
0= Stop bit was not detected last
Note:
This bit is cleared on Reset and when SSPEN is cleared.
S: Start bit
1= Indicates that a Start bit has been detected last
0= Start bit was not detected last
Note:
This bit is cleared on Reset and when SSPEN is cleared.
R/W: Read/Write Information bit (I2C mode only)
In Slave mode:
1= Read
0= Write
Note:
This bit holds the R/W bit information following the last address match. This bit is
only valid from the address match to the next Start bit, Stop bit or not ACK bit.
In Master mode:
1= Transmit is in progress
0= Transmit is not in progress
Note:
ORing this bit with SEN, RSEN, PEN, RCEN or ACKEN will indicate if the MSSP is
in Active mode.
bit 1
bit 0
UA: Update Address bit (10-bit Slave mode only)
1= Indicates that the user needs to update the address in the SSPxADD register
0= Address does not need to be updated
BF: Buffer Full Status bit
In Transmit mode:
1= SSPxBUF is full
0= SSPxBUF is empty
In Receive mode:
1= SSPxBUF is full (does not include the ACK and Stop bits)
0= SSPxBUF is empty (does not include the ACK and Stop bits)
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
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Preliminary
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REGISTER 15-4: SSPxCON1: MSSPx CONTROL REGISTER 1 (I2C™ MODE)
R/W-0
WCOL
R/W-0
R/W-0
R/W-0
CKP
R/W-0
R/W-0
R/W-0
R/W-0
SSPOV
SSPEN
SSPM3
SSPM2
SSPM1
SSPM0
bit 7
bit 0
bit 7
WCOL: Write Collision Detect bit
In Master Transmit mode:
1= A write to the SSPxBUF register was attempted while the I2C conditions were not valid for a
transmission to be started (must be cleared in software)
0= No collision
In Slave Transmit mode:
1= The SSPxBUF register is written while it is still transmitting the previous word (must be
cleared in software)
0= No collision
In Receive mode (Master or Slave modes):
This is a “don’t care” bit.
bit 6
SSPOV: Receive Overflow Indicator bit
In Receive mode:
1= A byte is received while the SSPxBUF register is still holding the previous byte (must be
cleared in software)
0= No overflow
In Transmit mode:
This is a “don’t care” bit in Transmit mode.
bit 5
bit 4
SSPEN: Master Synchronous Serial Port Enable bit
1= Enables the serial port and configures the SDAx and SCLx pins as the serial port pins
0= Disables serial port and configures these pins as I/O port pins
Note:
When enabled, the SDAx and SCLx pins must be properly configured as input or
output.
CKP: SCKx Release Control bit
In Slave mode:
1= Release clock
0= Holds clock low (clock stretch), used to ensure data setup time
In Master mode:
Unused in this mode.
bit 3-0 SSPM3:SSPM0: Master Synchronous Serial Port Mode Select bits
1111= I2C Slave mode, 10-bit address with Start and Stop bit interrupts enabled
1110= I2C Slave mode, 7-bit address with Start and Stop bit interrupts enabled
1011= I2C Firmware Controlled Master mode (Slave Idle)
1000= I2C Master mode, clock = FOSC/(4 * (SSPxADD + 1))
0111= I2C Slave mode, 10-bit address
0110= I2C Slave mode, 7-bit address
Bit combinations not specifically listed here are either reserved or implemented in SPI mode only.
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
© 2007 Microchip Technology Inc.
Preliminary
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PIC18F45J10 FAMILY
REGISTER 15-5: SSPxCON2: MSSPx CONTROL REGISTER 2 (I2C™ MODE)
R/W-0
GCEN
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
SEN(1)
ACKSTAT
ACKDT
ACKEN(1) RCEN(1) PEN(1) RSEN(1)
bit 7
bit 0
bit 7
bit 6
bit 5
GCEN: General Call Enable bit (Slave mode only)
1= Enable interrupt when a general call address (0000h) is received in the SSPxSR
0= General call address disabled
ACKSTAT: Acknowledge Status bit (Master Transmit mode only)
1= Acknowledge was not received from slave
0= Acknowledge was received from slave
ACKDT: Acknowledge Data bit (Master Receive mode only)
1= Not Acknowledge
0= Acknowledge
Note:
Value that will be transmitted when the user initiates an Acknowledge sequence at
the end of a receive.
bit 4
ACKEN: Acknowledge Sequence Enable bit (Master Receive mode only)(1)
1= Initiate Acknowledge sequence on SDAx and SCLx pins and transmit ACKDT data bit.
Automatically cleared by hardware.
0= Acknowledge sequence Idle
bit 3
bit 2
RCEN: Receive Enable bit (Master mode only)(1)
1= Enables Receive mode for I2C
0= Receive Idle
PEN: Stop Condition Enable bit (Master mode only)(1)
1= Initiate Stop condition on SDAx and SCLx pins. Automatically cleared by hardware.
0= Stop condition Idle
bit 1
bit 0
RSEN: Repeated Start Condition Enable bit (Master mode only)(1)
1= Initiate Repeated Start condition on SDAx and SCLx pins. Automatically cleared by
hardware.
0= Repeated Start condition Idle
SEN: Start Condition Enable/Stretch Enable bit(1)
In Master mode:
1= Initiate Start condition on SDAx and SCLx pins. Automatically cleared by hardware.
0= Start condition Idle
In Slave mode:
1= Clock stretching is enabled for both slave transmit and slave receive (stretch enabled)
0= Clock stretching is disabled
Note 1: For bits ACKEN, RCEN, PEN, RSEN, SEN: If the I2C module is not in the Idle mode,
these bits may not be set (no spooling) and the SSPxBUF may not be written (or
writes to the SSPxBUF are disabled).
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
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Preliminary
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PIC18F45J10 FAMILY
15.4.2
OPERATION
15.4.3.1
Addressing
The MSSP module functions are enabled by setting the
MSSP Enable bit, SSPEN (SSPxCON1<5>).
The SSPxCON1 register allows control of the I2C
Once the MSSP module has been enabled, it waits for
a Start condition to occur. Following the Start condition,
the 8 bits are shifted into the SSPxSR register. All
incoming bits are sampled with the rising edge of the
clock (SCLx) line. The value of register SSPxSR<7:1>
is compared to the value of the SSPxADD register. The
address is compared on the falling edge of the eighth
clock (SCLx) pulse. If the addresses match and the BF
and SSPOV bits are clear, the following events occur:
operation.
Four
mode
selection
bits
(SSPxCON1<3:0>) allow one of the following I2C
modes to be selected:
• I2C Master mode,
clock = (FOSC/4) x (SSPxADD + 1)
• I2C Slave mode (7-bit address)
• I2C Slave mode (10-bit address)
• I2C Slave mode (7-bit address) with Start and
Stop bit interrupts enabled
• I2C Slave mode (10-bit address) with Start and
Stop bit interrupts enabled
• I2C Firmware Controlled Master mode,
slave is Idle
1. The SSPxSR register value is loaded into the
SSPxBUF register.
2. The Buffer Full bit, BF, is set.
3. An ACK pulse is generated.
4. The MSSP Interrupt Flag bit, SSPxIF, is set (and
interrupt is generated, if enabled) on the falling
edge of the ninth SCLx pulse.
In 10-bit Address mode, two address bytes need to be
received by the slave. The five Most Significant bits
(MSbs) of the first address byte specify if this is a 10-bit
address. Bit R/W (SSPxSTAT<2>) must specify a write
so the slave device will receive the second address byte.
For a 10-bit address, the first byte would equal ‘11110
A9 A8 0’, where ‘A9’ and ‘A8’ are the two MSbs of the
address. The sequence of events for 10-bit address is as
follows, with steps 7 through 9 for the slave-transmitter:
Selection of any I2C mode, with the SSPEN bit set,
forces the SCLx and SDAx pins to be open-drain,
provided these pins are programmed to inputs by
setting the appropriate TRISC or TRISD bits. To ensure
proper operation of the module, pull-up resistors must
be provided externally to the SCLx and SDAx pins.
15.4.3
SLAVE MODE
In Slave mode, the SCLx and SDAx pins must be
configured as inputs (TRISC<4:3> or TRISD<1:0> set).
The MSSP module will override the input state with the
output data when required (slave-transmitter).
The I2C Slave mode hardware will always generate an
interrupt on an address match. Through the mode
select bits, the user can also choose to interrupt on
Start and Stop bits
1. Receive first (high) byte of address (bits SSPxIF,
BF and UA (SSPxSTAT<1>) are set).
2. Update the SSPxADD register with second (low)
byte of address (clears bit UA and releases the
SCLx line).
3. Read the SSPxBUF register (clears bit BF) and
clear flag bit SSPxIF.
4. Receive second (low) byte of address (bits
SSPxIF, BF and UA are set).
When an address is matched, or the data transfer after
an address match is received, the hardware auto-
matically will generate the Acknowledge (ACK) pulse
and load the SSPxBUF register with the received value
currently in the SSPxSR register.
5. Update the SSPxADD register with the first
(high) byte of address. If match releases SCLx
line, this will clear bit UA.
6. Read the SSPxBUF register (clears bit BF) and
clear flag bit SSPxIF.
Any combination of the following conditions will cause
the MSSP module not to give this ACK pulse:
7. Receive Repeated Start condition.
• The Buffer Full bit, BF (SSPxSTAT<0>), was set
before the transfer was received.
8. Receive first (high) byte of address (bits SSPxIF
and BF are set).
• The overflow bit, SSPOV (SSPxCON1<6>), was
set before the transfer was received.
9. Read the SSPxBUF register (clears bit BF) and
clear flag bit SSPxIF.
In this case, the SSPxSR register value is not loaded
into the SSPxBUF, but bit SSPxIF is set. The BF bit is
cleared by reading the SSPxBUF register, while bit
SSPOV is cleared through software.
The SCLx clock input must have a minimum high and
low for proper operation. The high and low times of the
I2C specification, as well as the requirement of the
MSSP module, are shown in timing parameter 100 and
parameter 101.
© 2007 Microchip Technology Inc.
Preliminary
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PIC18F45J10 FAMILY
15.4.3.2
Reception
15.4.3.3
Transmission
When the R/W bit of the address byte is clear and an
address match occurs, the R/W bit of the SSPxSTAT
register is cleared. The received address is loaded into
the SSPxBUF register and the SDAx line is held low
(ACK).
When the R/W bit of the incoming address byte is set
and an address match occurs, the R/W bit of the
SSPxSTAT register is set. The received address is
loaded into the SSPxBUF register. The ACK pulse will
be sent on the ninth bit and pin RC3 or RD6 is held low,
regardless of SEN (see Section 15.4.4 “Clock
Stretching” for more details). By stretching the clock,
the master will be unable to assert another clock pulse
until the slave is done preparing the transmit data. The
transmit data must be loaded into the SSPxBUF regis-
ter which also loads the SSPxSR register. Then pin
RC3 or RD0 should be enabled by setting bit, CKP
(SSPxCON1<4>). The eight data bits are shifted out on
the falling edge of the SCLx input. This ensures that the
SDAx signal is valid during the SCLx high time
(Figure 15-9).
When the address byte overflow condition exists, then
the no Acknowledge (ACK) pulse is given. An overflow
condition is defined as either bit BF (SSPxSTAT<0>) is
set, or bit SSPOV (SSPxCON1<6>) is set.
An MSSP interrupt is generated for each data transfer
byte. The interrupt flag bit, SSPxIF, must be cleared in
software. The SSPxSTAT register is used to determine
the status of the byte.
If SEN is enabled (SSPxCON2<0> = 1), SCKx/SCLx
(RC3 or RD0) will be held low (clock stretch) following
each data transfer. The clock must be released by
setting bit, CKP (SSPxCON1<4>). See Section 15.4.4
“Clock Stretching” for more details.
The ACK pulse from the master-receiver is latched on
the rising edge of the ninth SCLx input pulse. If the
SDAx line is high (not ACK), then the data transfer is
complete. In this case, when the ACK is latched by the
slave, the slave logic is reset (resets SSPxSTAT
register) and the slave monitors for another occurrence
of the Start bit. If the SDAx line was low (ACK), the next
transmit data must be loaded into the SSPxBUF regis-
ter. Again, pin RC3 or RD0 must be enabled by setting
bit CKP.
An MSSP interrupt is generated for each data transfer
byte. The SSPxIF bit must be cleared in software and
the SSPxSTAT register is used to determine the status
of the byte. The SSPxIF bit is set on the falling edge of
the ninth clock pulse.
DS39682C-page 160
Preliminary
© 2007 Microchip Technology Inc.
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2
FIGURE 15-8:
I C™ SLAVE MODE TIMING WITH SEN = 0 (RECEPTION, 7-BIT ADDRESS)
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Preliminary
DS39682C-page 161
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2
FIGURE 15-9:
I C™ SLAVE MODE TIMING (TRANSMISSION, 7-BIT ADDRESS)
DS39682C-page 162
Preliminary
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FIGURE 15-10:
I2C™ SLAVE MODE TIMING WITH SEN = 0 (RECEPTION, 10-BIT ADDRESS)
© 2007 Microchip Technology Inc.
Preliminary
DS39682C-page 163
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2
FIGURE 15-11:
I C™ SLAVE MODE TIMING (TRANSMISSION, 10-BIT ADDRESS)
DS39682C-page 164
Preliminary
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15.4.4
CLOCK STRETCHING
15.4.4.3
Clock Stretching for 7-bit Slave
Transmit Mode
Both 7-bit and 10-bit Slave modes implement
automatic clock stretching during a transmit sequence.
The 7-bit Slave Transmit mode implements clock
stretching by clearing the CKP bit after the falling edge
of the ninth clock, if the BF bit is clear. This occurs
regardless of the state of the SEN bit.
The SEN bit (SSPxCON2<0>) allows clock stretching
to be enabled during receives. Setting SEN will cause
the SCLx pin to be held low at the end of each data
receive sequence.
The user’s ISR must set the CKP bit before transmis-
sion is allowed to continue. By holding the SCLx line
low, the user has time to service the ISR and load the
contents of the SSPxBUF before the master device
can initiate another transmit sequence (see
Figure 15-9).
15.4.4.1
Clock Stretching for 7-bit Slave
Receive Mode (SEN = 1)
In 7-bit Slave Receive mode, on the falling edge of the
ninth clock at the end of the ACK sequence, if the BF
bit is set, the CKP bit in the SSPxCON1 register is
automatically cleared, forcing the SCLx output to be
held low. The CKP being cleared to ‘0’ will assert the
SCLx line low. The CKP bit must be set in the user’s
ISR before reception is allowed to continue. By holding
the SCLx line low, the user has time to service the ISR
and read the contents of the SSPxBUF before the
master device can initiate another receive sequence.
This will prevent buffer overruns from occurring (see
Figure 15-13).
Note 1: If the user loads the contents of
SSPxBUF, setting the BF bit before the
falling edge of the ninth clock, the CKP bit
will not be cleared and clock stretching
will not occur.
2: The CKP bit can be set in software
regardless of the state of the BF bit.
15.4.4.4
Clock Stretching for 10-bit Slave
Transmit Mode
Note 1: If the user reads the contents of the
SSPxBUF before the falling edge of the
ninth clock, thus clearing the BF bit, the
CKP bit will not be cleared and clock
stretching will not occur.
In 10-bit Slave Transmit mode, clock stretching is con-
trolled during the first two address sequences by the
state of the UA bit, just as it is in 10-bit Slave Receive
mode. The first two addresses are followed by a third
address sequence which contains the high-order bits
of the 10-bit address and the R/W bit set to ‘1’. After
the third address sequence is performed, the UA bit is
not set, the module is now configured in Transmit
mode and clock stretching is controlled by the BF flag
as in 7-bit Slave Transmit mode (see Figure 15-11).
2: The CKP bit can be set in software
regardless of the state of the BF bit. The
user should be careful to clear the BF bit
in the ISR before the next receive
sequence in order to prevent an overflow
condition.
15.4.4.2
Clock Stretching for 10-bit Slave
Receive Mode (SEN = 1)
In 10-bit Slave Receive mode during the address
sequence, clock stretching automatically takes place
but CKP is not cleared. During this time, if the UA bit is
set after the ninth clock, clock stretching is initiated.
The UA bit is set after receiving the upper byte of the
10-bit address and following the receive of the second
byte of the 10-bit address with the R/W bit cleared to
‘0’. The release of the clock line occurs upon updating
SSPxADD. Clock stretching will occur on each data
receive sequence as described in 7-bit mode.
Note:
If the user polls the UA bit and clears it by
updating the SSPxADD register before the
falling edge of the ninth clock occurs and if
the user hasn’t cleared the BF bit by read-
ing the SSPxBUF register before that time,
then the CKP bit will still NOT be asserted
low. Clock stretching on the basis of the
state of the BF bit only occurs during a
data sequence, not an address sequence.
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Preliminary
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already asserted the SCLx line. The SCLx output will
remain low until the CKP bit is set and all other
devices on the I2C bus have deasserted SCLx. This
ensures that a write to the CKP bit will not violate the
minimum high time requirement for SCLx (see
Figure 15-12).
15.4.4.5
Clock Synchronization and
the CKP bit
When the CKP bit is cleared, the SCLx output is forced
to ‘0’. However, clearing the CKP bit will not assert the
SCLx output low until the SCLx output is already sam-
pled low. Therefore, the CKP bit will not assert the
SCLx line until an external I2C master device has
FIGURE 15-12:
CLOCK SYNCHRONIZATION TIMING
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
SDAx
SCLx
DX
DX – 1
Master device
asserts clock
CKP
Master device
deasserts clock
WR
SSPxCON
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Preliminary
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2
FIGURE 15-13:
I C™ SLAVE MODE TIMING WITH SEN = 1 (RECEPTION, 7-BIT ADDRESS)
© 2007 Microchip Technology Inc.
Preliminary
DS39682C-page 167
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FIGURE 15-14:
I2C™ SLAVE MODE TIMING WITH SEN = 1 (RECEPTION, 10-BIT ADDRESS)
DS39682C-page 168
Preliminary
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If the general call address matches, the SSPxSR is
transferred to the SSPxBUF, the BF flag bit is set
(eighth bit) and on the falling edge of the ninth bit (ACK
bit), the SSPxIF interrupt flag bit is set.
15.4.5
GENERAL CALL ADDRESS
SUPPORT
The addressing procedure for the I2C bus is such that
the first byte after the Start condition usually
determines which device will be the slave addressed by
the master. The exception is the general call address
which can address all devices. When this address is
used, all devices should, in theory, respond with an
Acknowledge.
When the interrupt is serviced, the source for the
interrupt can be checked by reading the contents of the
SSPxBUF. The value can be used to determine if the
address was device specific or a general call address.
In 10-bit mode, the SSPxADD is required to be updated
for the second half of the address to match and the UA
bit is set (SSPxSTAT<1>). If the general call address is
sampled when the GCEN bit is set, while the slave is
configured in 10-bit Address mode, then the second
half of the address is not necessary, the UA bit will not
be set and the slave will begin receiving data after the
Acknowledge (Figure 15-15).
The general call address is one of eight addresses
reserved for specific purposes by the I2C protocol. It
consists of all ‘0’s with R/W = 0.
The general call address is recognized when the
General Call Enable bit, GCEN, is enabled
(SSPxCON2<7> set). Following a Start bit detect, 8 bits
are shifted into the SSPxSR and the address is
compared against the SSPxADD. It is also compared to
the general call address and fixed in hardware.
FIGURE 15-15:
SLAVE MODE GENERAL CALL ADDRESS SEQUENCE
(7 OR 10-BIT ADDRESS MODE)
Address is compared to General Call Address
after ACK, set interrupt
Receiving Data
ACK
R/W = 0
ACK D7 D6
General Call Address
SDAx
SCLx
D5 D4 D3 D2 D1 D0
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
9
S
SSPxIF
BF (SSPxSTAT<0>)
Cleared in software
SSPxBUF is read
SSPOV (SSPxCON1<6>)
GCEN (SSPxCON2<7>)
‘0’
‘1’
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Preliminary
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15.4.6
MASTER MODE
Note:
The MSSP module, when configured in
I2C Master mode, does not allow queueing
of events. For instance, the user is not
allowed to initiate a Start condition and
immediately write the SSPxBUF register to
initiate transmission before the Start con-
dition is complete. In this case, the
SSPxBUF will not be written to and the
WCOL bit will be set, indicating that a write
to the SSPxBUF did not occur.
Master mode is enabled by setting and clearing the
appropriate SSPM bits in SSPxCON1 and by setting
the SSPEN bit. In Master mode, the SCLx and SDAx
lines are manipulated by the MSSP hardware.
Master mode of operation is supported by interrupt
generation on the detection of the Start and Stop
conditions. The Stop (P) and Start (S) bits are cleared
from a Reset or when the MSSP module is disabled.
Control of the I2C bus may be taken when the P bit is
set, or the bus is Idle, with both the S and P bits clear.
The following events will cause the MSSP Interrupt
Flag bit, SSPxIF, to be set (and MSSP interrupt, if
enabled):
In Firmware Controlled Master mode, user code
conducts all I2C bus operations based on Start and
Stop bit conditions.
• Start condition
Once Master mode is enabled, the user has six
options.
• Stop condition
• Data transfer byte transmitted/received
• Acknowledge transmit
• Repeated Start
1. Assert a Start condition on SDAx and SCLx.
2. Assert a Repeated Start condition on SDAx and
SCLx.
3. Write to the SSPxBUF register initiating
transmission of data/address.
4. Configure the I2C port to receive data.
5. Generate an Acknowledge condition at the end
of a received byte of data.
6. Generate a Stop condition on SDAx and SCLx.
2
FIGURE 15-16:
MSSP BLOCK DIAGRAM (I C™ MASTER MODE)
Internal
Data Bus
SSPM3:SSPM0
SSPxADD<6:0>
Read
Write
SSPxBUF
SSPxSR
Baud
Rate
Generator
SDAx
Shift
Clock
SDAx In
MSb
LSb
Start bit, Stop bit,
Acknowledge
Generate
SCLx
Start bit Detect
Stop bit Detect
Write Collision Detect
Clock Arbitration
State Counter for
End of XMIT/RCV
SCLx In
Bus Collision
Set/Reset S, P, WCOL (SSPxSTAT, SSPxCON1)
Set SSPxIF, BCLxIF
Reset ACKSTAT, PEN (SSPxCON2)
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Preliminary
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I2C Master Mode Operation
A typical transmit sequence would go as follows:
15.4.6.1
1. The user generates a Start condition by setting
the Start Enable bit, SEN (SSPxCON2<0>).
The master device generates all of the serial clock
pulses and the Start and Stop conditions. A transfer is
ended with a Stop condition or with a Repeated Start
condition. Since the Repeated Start condition is also
the beginning of the next serial transfer, the I2C bus will
not be released.
2. SSPxIF is set. The MSSP module will wait the
required start time before any other operation
takes place.
3. The user loads the SSPxBUF with the slave
address to transmit.
In Master Transmitter mode, serial data is output
through SDAx, while SCLx outputs the serial clock. The
first byte transmitted contains the slave address of the
receiving device (7 bits) and the Read/Write (R/W) bit.
In this case, the R/W bit will be logic ‘0’. Serial data is
transmitted 8 bits at a time. After each byte is transmit-
ted, an Acknowledge bit is received. Start and Stop
conditions are output to indicate the beginning and the
end of a serial transfer.
4. Address is shifted out the SDAx pin until all 8 bits
are transmitted.
5. The MSSP module shifts in the ACK bit from the
slave device and writes its value into the
SSPxCON2 register (SSPxCON2<6>).
6. The MSSP module generates an interrupt at the
end of the ninth clock cycle by setting the
SSPxIF bit.
In Master Receive mode, the first byte transmitted
contains the slave address of the transmitting device
(7 bits) and the R/W bit. In this case, the R/W bit will be
logic ‘1’. Thus, the first byte transmitted is a 7-bit slave
address followed by a ‘1’ to indicate the receive bit.
Serial data is received via SDAx, while SCLx outputs
the serial clock. Serial data is received 8 bits at a time.
After each byte is received, an Acknowledge bit is
transmitted. Start and Stop conditions indicate the
beginning and end of transmission.
7. The user loads the SSPxBUF with eight bits of
data.
8. Data is shifted out the SDAx pin until all 8 bits
are transmitted.
9. The MSSP module shifts in the ACK bit from the
slave device and writes its value into the
SSPxCON2 register (SSPxCON2<6>).
10. The MSSP module generates an interrupt at the
end of the ninth clock cycle by setting the
SSPxIF bit.
The Baud Rate Generator used for the SPI mode
operation is used to set the SCLx clock frequency for
either 100 kHz, 400 kHz or 1 MHz I2C operation. See
Section 15.4.7 “Baud Rate” for more detail.
11. The user generates a Stop condition by setting
the Stop Enable bit, PEN (SSPxCON2<2>).
12. Interrupt is generated once the Stop condition is
complete.
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Table 15-3 demonstrates clock rates based on
instruction cycles and the BRG value loaded into
SSPxADD.
15.4.7
BAUD RATE
In I2C Master mode, the Baud Rate Generator (BRG)
reload value is placed in the lower 7 bits of the
SSPxADD register (Figure 15-17). When a write
occurs to SSPxBUF, the Baud Rate Generator will
automatically begin counting. The BRG counts down to
‘0’ and stops until another reload has taken place. The
BRG count is decremented twice per instruction cycle
(TCY) on the Q2 and Q4 clocks. In I2C Master mode, the
BRG is reloaded automatically.
15.4.7.1
Baud Rate and Module
Interdependence
Because MSSP1 and MSSP2 are independent, they
can operate simultaneously in I2C Master mode at
different baud rates. This is done by using different
BRG reload values for each module.
Because this mode derives its basic clock source from
the system clock, any changes to the clock will affect
both modules in the same proportion. It may be pos-
sible to change one or both baud rates back to a
previous value by changing the BRG reload value.
Once the given operation is complete (i.e., transmis-
sion of the last data bit is followed by ACK), the internal
clock will automatically stop counting and the SCLx pin
will remain in its last state.
FIGURE 15-17:
BAUD RATE GENERATOR BLOCK DIAGRAM
SSPM3:SSPM0
SSPxADD<6:0>
SSPM3:SSPM0
SCLx
Reload
Control
Reload
BRG Down Counter
CLKO
FOSC/4
TABLE 15-3: I2C™ CLOCK RATE w/BRG
FSCL
FCY
FCY * 2
BRG Value
(2 Rollovers of BRG)
10 MHz
10 MHz
10 MHz
4 MHz
4 MHz
4 MHz
1 MHz
1 MHz
1 MHz
20 MHz
20 MHz
20 MHz
8 MHz
8 MHz
8 MHz
2 MHz
2 MHz
2 MHz
18h
1Fh
63h
09h
0Ch
27h
02h
09h
00h
400 kHz(1)
312.5 kHz
100 kHz
400 kHz(1)
308 kHz
100 kHz
333 kHz(1)
100 kHz
1 MHz(1)
Note 1: The I2C™ interface does not conform to the 400 kHz I2C specification (which applies to rates greater than
100 kHz) in all details, but may be used with care where higher rates are required by the application.
DS39682C-page 172
Preliminary
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SCLx pin is sampled high, the Baud Rate Generator is
reloaded with the contents of SSPxADD<6:0> and
begins counting. This ensures that the SCLx high time
will always be at least one BRG rollover count in the
event that the clock is held low by an external device
(Figure 15-18).
15.4.7.2
Clock Arbitration
Clock arbitration occurs when the master, during any
receive, transmit or Repeated Start/Stop condition,
deasserts the SCLx pin (SCLx allowed to float high).
When the SCLx pin is allowed to float high, the Baud
Rate Generator (BRG) is suspended from counting
until the SCLx pin is actually sampled high. When the
FIGURE 15-18:
BAUD RATE GENERATOR TIMING WITH CLOCK ARBITRATION
SDAx
DX
DX – 1
SCLx allowed to transition high
SCLx deasserted but slave holds
SCLx low (clock arbitration)
SCLx
BRG decrements on
Q2 and Q4 cycles
BRG
Value
03h
02h
01h
00h (hold off)
03h
02h
SCLx is sampled high, reload takes
place and BRG starts its count
BRG
Reload
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15.4.8
I2C MASTER MODE START
CONDITION TIMING
Note:
If at the beginning of the Start condition,
the SDAx and SCLx pins are already sam-
pled low, or if during the Start condition, the
SCLx line is sampled low before the SDAx
line is driven low, a bus collision occurs.
The Bus Collision Interrupt Flag, BCLxIF,
is set, the Start condition is aborted and
the I2C module is reset into its Idle state.
To initiate a Start condition, the user sets the Start
Enable bit, SEN (SSPxCON2<0>). If the SDAx and
SCLx pins are sampled high, the Baud Rate Generator
is reloaded with the contents of SSPxADD<6:0> and
starts its count. If SCLx and SDAx are both sampled
high when the Baud Rate Generator times out (TBRG),
the SDAx pin is driven low. The action of the SDAx
being driven low while SCLx is high is the Start condi-
tion and causes the S bit (SSPxSTAT<3>) to be set.
Following this, the Baud Rate Generator is reloaded
with the contents of SSPxADD<6:0> and resumes its
count. When the Baud Rate Generator times out
(TBRG), the SEN bit (SSPxCON2<0>) will be automati-
cally cleared by hardware. The Baud Rate Generator is
suspended, leaving the SDAx line held low and the
Start condition is complete.
15.4.8.1
WCOL Status Flag
If the user writes the SSPxBUF when a Start sequence
is in progress, the WCOL is set and the contents of the
buffer are unchanged (the write doesn’t occur).
Note:
Because queueing of events is not
allowed, writing to the lower 5 bits of
SSPxCON2 is disabled until the Start
condition is complete.
FIGURE 15-19:
FIRST START BIT TIMING
Set S bit (SSPxSTAT<3>)
Write to SEN bit occurs here
SDAx = 1,
At completion of Start bit,
hardware clears SEN bit
and sets SSPxIF bit
SCLx = 1
TBRG
TBRG
Write to SSPxBUF occurs here
2nd bit
1st bit
SDAx
TBRG
SCLx
TBRG
S
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15.4.9
I2C MASTER MODE REPEATED
START CONDITION TIMING
Note 1: If RSEN is programmed while any other
event is in progress, it will not take effect.
A Repeated Start condition occurs when the RSEN bit
(SSPxCON2<1>) is programmed high and the I2C logic
module is in the Idle state. When the RSEN bit is set,
the SCLx pin is asserted low. When the SCLx pin is
sampled low, the Baud Rate Generator is loaded with
the contents of SSPxADD<6:0> and begins counting.
The SDAx pin is released (brought high) for one Baud
Rate Generator count (TBRG). When the Baud Rate
Generator times out, if SDAx is sampled high, the SCLx
pin will be deasserted (brought high). When SCLx is
sampled high, the Baud Rate Generator is reloaded
with the contents of SSPxADD<6:0> and begins count-
ing. SDAx and SCLx must be sampled high for one
TBRG. This action is then followed by assertion of the
SDAx pin (SDAx = 0) for one TBRG while SCLx is high.
Following this, the RSEN bit (SSPxCON2<1>) will be
automatically cleared and the Baud Rate Generator will
not be reloaded, leaving the SDAx pin held low. As
soon as a Start condition is detected on the SDAx and
SCLx pins, the S bit (SSPxSTAT<3>) will be set. The
SSPxIF bit will not be set until the Baud Rate Generator
has timed out.
2: A bus collision during the Repeated Start
condition occurs if:
• SDAx is sampled low when SCLx
goes from low-to-high.
• SCLx goes low before SDAx is
asserted low. This may indicate that
another master is attempting to
transmit a data ‘1’.
Immediately following the SSPxIF bit getting set, the
user may write the SSPxBUF with the 7-bit address in
7-bit mode or the default first address in 10-bit mode.
After the first eight bits are transmitted and an ACK is
received, the user may then transmit an additional eight
bits of address (10-bit mode) or eight bits of data (7-bit
mode).
15.4.9.1
WCOL Status Flag
If the user writes the SSPxBUF when a Repeated Start
sequence is in progress, the WCOL is set and the
contents of the buffer are unchanged (the write doesn’t
occur).
Note:
Because queueing of events is not
allowed, writing of the lower 5 bits of
SSPxCON2 is disabled until the Repeated
Start condition is complete.
FIGURE 15-20:
REPEATED START CONDITION WAVEFORM
S bit set by hardware
SDAx = 1,
SCLx = 1
At completion of Start bit,
hardware clears RSEN bit
and sets SSPxIF
Write to SSPxCON2 occurs here:
SDAx = 1,
SCLx (no change)
TBRG
TBRG
TBRG
1st bit
SDAx
RSEN bit set by hardware
on falling edge of ninth clock,
end of Xmit
Write to SSPxBUF occurs here
TBRG
SCLx
TBRG
Sr = Repeated Start
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15.4.10 I2C MASTER MODE
TRANSMISSION
The user should verify that the WCOL is clear after
each write to SSPxBUF to ensure the transfer is
correct. In all cases, WCOL must be cleared in
software.
Transmission of a data byte, a 7-bit address or the
other half of a 10-bit address is accomplished by simply
writing a value to the SSPxBUF register. This action will
set the Buffer Full flag bit, BF and allow the Baud Rate
Generator to begin counting and start the next trans-
mission. Each bit of address/data will be shifted out
onto the SDAx pin after the falling edge of SCLx is
asserted (see data hold time specification
parameter 106). SCLx is held low for one Baud Rate
Generator rollover count (TBRG). Data should be valid
before SCLx is released high (see data setup time
specification parameter 107). When the SCLx pin is
released high, it is held that way for TBRG. The data on
the SDAx pin must remain stable for that duration and
some hold time after the next falling edge of SCLx.
After the eighth bit is shifted out (the falling edge of the
eighth clock), the BF flag is cleared and the master
releases SDAx. This allows the slave device being
addressed to respond with an ACK bit during the ninth
bit time if an address match occurred, or if data was
received properly. The status of ACK is written into the
ACKDT bit on the falling edge of the ninth clock. If the
master receives an Acknowledge, the Acknowledge
Status bit, ACKSTAT, is cleared; if not, the bit is set.
After the ninth clock, the SSPxIF bit is set and the
master clock (Baud Rate Generator) is suspended until
the next data byte is loaded into the SSPxBUF, leaving
SCLx low and SDAx unchanged (Figure 15-21).
15.4.10.3 ACKSTAT Status Flag
In Transmit mode, the ACKSTAT bit (SSPxCON2<6>)
is cleared when the slave has sent an Acknowledge
(ACK = 0) and is set when the slave does not Acknowl-
edge (ACK = 1). A slave sends an Acknowledge when
it has recognized its address (including a general call),
or when the slave has properly received its data.
15.4.11 I2C MASTER MODE RECEPTION
Master mode reception is enabled by programming the
Receive Enable bit, RCEN (SSPxCON2<3>).
Note:
The MSSP module must be in an Idle state
before the RCEN bit is set or the RCEN bit
will be disregarded.
The Baud Rate Generator begins counting and on each
rollover, the state of the SCLx pin changes
(high-to-low/low-to-high) and data is shifted into the
SSPxSR. After the falling edge of the eighth clock, the
receive enable flag is automatically cleared, the con-
tents of the SSPxSR are loaded into the SSPxBUF, the
BF flag bit is set, the SSPxIF flag bit is set and the Baud
Rate Generator is suspended from counting, holding
SCLx low. The MSSP is now in Idle state awaiting the
next command. When the buffer is read by the CPU,
the BF flag bit is automatically cleared. The user can
then send an Acknowledge bit at the end of reception
by setting the Acknowledge Sequence Enable bit,
ACKEN (SSPxCON2<4>).
After the write to the SSPxBUF, each bit of the address
will be shifted out on the falling edge of SCLx until all
seven address bits and the R/W bit are completed. On
the falling edge of the eighth clock, the master will
deassert the SDAx pin, allowing the slave to respond
with an Acknowledge. On the falling edge of the ninth
clock, the master will sample the SDAx pin to see if the
address was recognized by a slave. The status of the
ACK bit is loaded into the ACKSTAT status bit
(SSPxCON2<6>). Following the falling edge of the
ninth clock transmission of the address, the SSPxIF is
set, the BF flag is cleared and the Baud Rate Generator
is turned off until another write to the SSPxBUF takes
place, holding SCLx low and allowing SDAx to float.
15.4.11.1 BF Status Flag
In receive operation, the BF bit is set when an address
or data byte is loaded into SSPxBUF from SSPxSR. It
is cleared when the SSPxBUF register is read.
15.4.11.2 SSPOV Status Flag
In receive operation, the SSPOV bit is set when 8 bits
are received into the SSPxSR and the BF flag bit is
already set from a previous reception.
15.4.10.1 BF Status Flag
15.4.11.3 WCOL Status Flag
In Transmit mode, the BF bit (SSPxSTAT<0>) is set
when the CPU writes to SSPxBUF and is cleared when
all 8 bits are shifted out.
If the user writes the SSPxBUF when a receive is
already in progress (i.e., SSPxSR is still shifting in a
data byte), the WCOL bit is set and the contents of the
buffer are unchanged (the write doesn’t occur).
15.4.10.2 WCOL Status Flag
If the user writes to the SSPxBUF when a transmit is
already in progress (i.e., SSPxSR is still shifting out a
data byte), the WCOL is set and the contents of the
buffer are unchanged (the write doesn’t occur) after
2 TCY after the SSPxBUF write. If SSPxBUF is rewritten
within 2 TCY, the WCOL bit is set and SSPxBUF is
updated. This may result in a corrupted transfer.
DS39682C-page 176
Preliminary
© 2007 Microchip Technology Inc.
PIC18F45J10 FAMILY
2
FIGURE 15-21:
I C™ MASTER MODE WAVEFORM (TRANSMISSION, 7 OR 10-BIT ADDRESS)
© 2007 Microchip Technology Inc.
Preliminary
DS39682C-page 177
PIC18F45J10 FAMILY
2
FIGURE 15-22:
I C™ MASTER MODE WAVEFORM (RECEPTION, 7-BIT ADDRESS)
DS39682C-page 178
Preliminary
© 2007 Microchip Technology Inc.
PIC18F45J10 FAMILY
15.4.12 ACKNOWLEDGE SEQUENCE
TIMING
15.4.13 STOP CONDITION TIMING
A Stop bit is asserted on the SDAx pin at the end of a
receive/transmit by setting the Stop Sequence Enable
bit, PEN (SSPxCON2<2>). At the end of
An Acknowledge sequence is enabled by setting the
Acknowledge Sequence Enable bit, ACKEN
(SSPxCON2<4>). When this bit is set, the SCLx pin is
pulled low and the contents of the Acknowledge data bit
are presented on the SDAx pin. If the user wishes to
generate an Acknowledge, then the ACKDT bit should
be cleared. If not, the user should set the ACKDT bit
before starting an Acknowledge sequence. The Baud
Rate Generator then counts for one rollover period
(TBRG) and the SCLx pin is deasserted (pulled high).
When the SCLx pin is sampled high (clock arbitration),
the Baud Rate Generator counts for TBRG. The SCLx pin
is then pulled low. Following this, the ACKEN bit is auto-
matically cleared, the Baud Rate Generator is turned off
and the MSSP module then goes into Idle mode
(Figure 15-23).
a
receive/transmit, the SCLx line is held low after the fall-
ing edge of the ninth clock. When the PEN bit is set, the
master will assert the SDAx line low. When the SDAx
line is sampled low, the Baud Rate Generator is
reloaded and counts down to ‘0’. When the Baud Rate
Generator times out, the SCLx pin will be brought high
and one TBRG (Baud Rate Generator rollover count)
later, the SDAx pin will be deasserted. When the SDAx
pin is sampled high while SCLx is high, the P bit
(SSPxSTAT<4>) is set. A TBRG later, the PEN bit is
cleared and the SSPxIF bit is set (Figure 15-24).
15.4.13.1 WCOL Status Flag
If the user writes the SSPxBUF when a Stop sequence
is in progress, then the WCOL bit is set and the
contents of the buffer are unchanged (the write doesn’t
occur).
15.4.12.1 WCOL Status Flag
If the user writes the SSPxBUF when an Acknowledge
sequence is in progress, then WCOL is set and the
contents of the buffer are unchanged (the write doesn’t
occur).
FIGURE 15-23:
ACKNOWLEDGE SEQUENCE WAVEFORM
Acknowledge sequence starts here,
write to SSPxCON2
ACKEN automatically cleared
ACKEN = 1, ACKDT = 0
TBRG
ACK
TBRG
SDAx
SCLx
D0
8
9
SSPxIF
Cleared in
software
SSPxIF set at the end
of Acknowledge sequence
SSPxIF set at
the end of receive
Cleared in
software
Note: TBRG = one Baud Rate Generator period.
FIGURE 15-24:
STOP CONDITION RECEIVE OR TRANSMIT MODE
SCLx = 1for TBRG, followed by SDAx = 1for TBRG
after SDAx sampled high. P bit (SSPxSTAT<4>) is set.
Write to SSPxCON2,
set PEN
PEN bit (SSPxCON2<2>) is cleared by
hardware and the SSPxIF bit is set
Falling edge of
9th clock
TBRG
SCLx
SDAx
ACK
P
TBRG
TBRG
TBRG
SCLx brought high after TBRG
SDAx asserted low before rising edge of clock
to set up Stop condition
Note: TBRG = one Baud Rate Generator period.
© 2007 Microchip Technology Inc.
Preliminary
DS39682C-page 179
PIC18F45J10 FAMILY
15.4.14 SLEEP OPERATION
15.4.17 MULTI -MASTER COMMUNICATION,
BUS COLLISION AND BUS
While in Sleep mode, the I2C module can receive
addresses or data and when an address match or
complete byte transfer occurs, wake the processor
from Sleep (if the MSSP interrupt is enabled).
ARBITRATION
Multi-Master mode support is achieved by bus arbitra-
tion. When the master outputs address/data bits onto
the SDAx pin, arbitration takes place when the master
outputs a ‘1’ on SDAx, by letting SDAx float high and
another master asserts a ‘0’. When the SCLx pin floats
high, data should be stable. If the expected data on
SDAx is a ‘1’ and the data sampled on the SDAx
pin = 0, then a bus collision has taken place. The
master will set the Bus Collision Interrupt Flag, BCLxIF
and reset the I2C port to its Idle state (Figure 15-25).
15.4.15 EFFECTS OF A RESET
A Reset disables the MSSP module and terminates the
current transfer.
15.4.16 MULTI-MASTER MODE
In Multi-Master mode, the interrupt generation on the
detection of the Start and Stop conditions allows the
determination of when the bus is free. The Stop (P) and
Start (S) bits are cleared from a Reset or when the
MSSP module is disabled. Control of the I2C bus may
be taken when the P bit (SSPxSTAT<4>) is set, or the
bus is Idle, with both the S and P bits clear. When the
bus is busy, enabling the MSSP interrupt will generate
the interrupt when the Stop condition occurs.
If a transmit was in progress when the bus collision
occurred, the transmission is halted, the BF flag is
cleared, the SDAx and SCLx lines are deasserted and
the SSPxBUF can be written to. When the user services
the bus collision Interrupt Service Routine and if the I2C
bus is free, the user can resume communication by
asserting a Start condition.
In multi-master operation, the SDAx line must be
monitored for arbitration to see if the signal level is the
expected output level. This check is performed in
hardware with the result placed in the BCLxIF bit.
If a Start, Repeated Start, Stop or Acknowledge condition
was in progress when the bus collision occurred, the
condition is aborted, the SDAx and SCLx lines are deas-
serted and the respective control bits in the SSPxCON2
register are cleared. When the user services the bus
collision Interrupt Service Routine and if the I2C bus is
free, the user can resume communication by asserting a
Start condition.
The states where arbitration can be lost are:
• Address Transfer
• Data Transfer
• A Start Condition
The master will continue to monitor the SDAx and SCLx
pins. If a Stop condition occurs, the SSPxIF bit will be set.
• A Repeated Start Condition
• An Acknowledge Condition
A write to the SSPxBUF will start the transmission of
data at the first data bit regardless of where the
transmitter left off when the bus collision occurred.
In Multi-Master mode, the interrupt generation on the
detection of Start and Stop conditions allows the deter-
mination of when the bus is free. Control of the I2C bus
can be taken when the P bit is set in the SSPxSTAT
register, or the bus is Idle and the S and P bits are
cleared.
FIGURE 15-25:
BUS COLLISION TIMING FOR TRANSMIT AND ACKNOWLEDGE
Sample SDAx. While SCLx is high,
data doesn’t match what is driven
by the master.
Data changes
while SCLx = 0
SDAx line pulled low
by another source
Bus collision has occurred.
SDAx released
by master
SDAx
SCLx
Set bus collision
interrupt (BCLxIF)
BCLxIF
DS39682C-page 180
Preliminary
© 2007 Microchip Technology Inc.
PIC18F45J10 FAMILY
If the SDAx pin is sampled low during this count, the
BRG is reset and the SDAx line is asserted early
(Figure 15-28). If, however, a ‘1’ is sampled on the
SDAx pin, the SDAx pin is asserted low at the end of
the BRG count. The Baud Rate Generator is then
reloaded and counts down to ‘0’. If the SCLx pin is
sampled as ‘0’ during this time, a bus collision does not
occur. At the end of the BRG count, the SCLx pin is
asserted low.
15.4.17.1 Bus Collision During a Start
Condition
During a Start condition, a bus collision occurs if:
a) SDAx or SCLx are sampled low at the beginning
of the Start condition (Figure 15-26).
b) SCLx is sampled low before SDAx is asserted
low (Figure 15-27).
During a Start condition, both the SDAx and the SCLx
pins are monitored.
Note:
The reason that bus collision is not a factor
during a Start condition is that no two bus
masters can assert a Start condition at the
exact same time. Therefore, one master
will always assert SDAx before the other.
This condition does not cause a bus colli-
sion because the two masters must be
allowed to arbitrate the first address
following the Start condition. If the address
is the same, arbitration must be allowed to
continue into the data portion, Repeated
Start or Stop conditions.
If the SDAx pin is already low, or the SCLx pin is
already low, then all of the following occur:
• the Start condition is aborted;
• the BCLxIF flag is set; and
• the MSSP module is reset to its Idle state
(Figure 15-26).
The Start condition begins with the SDAx and SCLx
pins deasserted. When the SDAx pin is sampled high,
the Baud Rate Generator is loaded from
SSPxADD<6:0> and counts down to ‘0’. If the SCLx pin
is sampled low while SDAx is high, a bus collision
occurs, because it is assumed that another master is
attempting to drive a data ‘1’ during the Start condition.
FIGURE 15-26:
BUS COLLISION DURING START CONDITION (SDAx ONLY)
SDAx goes low before the SEN bit is set.
Set BCLxIF,
S bit and SSPxIF set because
SDAx = 0, SCLx = 1.
SDAx
SCLx
SEN
Set SEN, enable Start
condition if SDAx = 1, SCLx = 1
SEN cleared automatically because of bus collision.
MSSP module reset into Idle state.
SDAx sampled low before
Start condition. Set BCLxIF.
S bit and SSPxIF set because
SDAx = 0, SCLx = 1.
BCLxIF
SSPxIF and BCLxIF are
cleared in software
S
SSPxIF
SSPxIF and BCLxIF are
cleared in software
© 2007 Microchip Technology Inc.
Preliminary
DS39682C-page 181
PIC18F45J10 FAMILY
FIGURE 15-27:
BUS COLLISION DURING START CONDITION (SCLx = 0)
SDAx = 0, SCLx = 1
TBRG
TBRG
SDAx
Set SEN, enable Start
sequence if SDAx = 1, SCLx = 1
SCLx
SEN
SCLx = 0before SDAx = 0,
bus collision occurs. Set BCLxIF.
SCLx = 0before BRG time-out,
bus collision occurs. Set BCLxIF.
BCLxIF
Interrupt cleared
in software
S
‘0’
‘0’
‘0’
‘0’
SSPxIF
FIGURE 15-28:
BRG RESET DUE TO SDAx ARBITRATION DURING START CONDITION
SDAx = 0, SCLx = 1
Set S
Set SSPxIF
Less than TBRG
TBRG
SDAx pulled low by other master.
Reset BRG and assert SDAx.
SDAx
SCLx
S
SCLx pulled low after BRG
time-out
SEN
Set SEN, enable Start
sequence if SDAx = 1, SCLx = 1
‘0’
BCLxIF
S
SSPxIF
Interrupts cleared
in software
SDAx = 0, SCLx = 1,
set SSPxIF
DS39682C-page 182
Preliminary
© 2007 Microchip Technology Inc.
PIC18F45J10 FAMILY
If SDAx is low, a bus collision has occurred (i.e., another
master is attempting to transmit a data ‘0’, see
Figure 15-29). If SDAx is sampled high, the BRG is
reloaded and begins counting. If SDAx goes from
high-to-low before the BRG times out, no bus collision
occurs because no two masters can assert SDAx at
exactly the same time.
15.4.17.2 Bus Collision During a Repeated
Start Condition
During a Repeated Start condition, a bus collision
occurs if:
a) A low level is sampled on SDAx when SCLx
goes from low level to high level.
b) SCLx goes low before SDAx is asserted low,
indicating that another master is attempting to
transmit a data ‘1’.
If SCLx goes from high-to-low before the BRG times
out and SDAx has not already been asserted, a bus
collision occurs. In this case, another master is
attempting to transmit a data ‘1’ during the Repeated
Start condition (see Figure 15-30).
When the user deasserts SDAx and the pin is allowed
to float high, the BRG is loaded with SSPxADD<6:0>
and counts down to ‘0’. The SCLx pin is then
deasserted and when sampled high, the SDAx pin is
sampled.
If, at the end of the BRG time-out, both SCLx and SDAx
are still high, the SDAx pin is driven low and the BRG
is reloaded and begins counting. At the end of the
count, regardless of the status of the SCLx pin, the
SCLx pin is driven low and the Repeated Start
condition is complete.
FIGURE 15-29:
BUS COLLISION DURING A REPEATED START CONDITION (CASE 1)
SDAx
SCLx
Sample SDAx when SCLx goes high.
If SDAx = 0, set BCLxIF and release SDAx and SCLx.
RSEN
BCLxIF
Cleared in software
‘0’
S
‘0’
SSPxIF
FIGURE 15-30:
BUS COLLISION DURING REPEATED START CONDITION (CASE 2)
TBRG
TBRG
SDAx
SCLx
SCLx goes low before SDAx,
BCLxIF
RSEN
set BCLxIF. Release SDAx and SCLx.
Interrupt cleared
in software
‘0’
S
SSPxIF
© 2007 Microchip Technology Inc.
Preliminary
DS39682C-page 183
PIC18F45J10 FAMILY
The Stop condition begins with SDAx asserted low.
When SDAx is sampled low, the SCLx pin is allowed to
float. When the pin is sampled high (clock arbitration),
the Baud Rate Generator is loaded with
SSPxADD<6:0> and counts down to ‘0’. After the BRG
times out, SDAx is sampled. If SDAx is sampled low, a
bus collision has occurred. This is due to another
master attempting to drive a data ‘0’ (Figure 15-31). If
the SCLx pin is sampled low before SDAx is allowed to
float high, a bus collision occurs. This is another case
of another master attempting to drive a data ‘0’
(Figure 15-32).
15.4.17.3 Bus Collision During a Stop
Condition
Bus collision occurs during a Stop condition if:
a) After the SDAx pin has been deasserted and
allowed to float high, SDAx is sampled low after
the BRG has timed out.
b) After the SCLx pin is deasserted, SCLx is
sampled low before SDAx goes high.
FIGURE 15-31:
BUS COLLISION DURING A STOP CONDITION (CASE 1)
SDAx sampled
low after TBRG,
set BCLxIF
TBRG
TBRG
TBRG
SDAx
SDAx asserted low
SCLx
PEN
BCLxIF
P
‘0’
‘0’
SSPxIF
FIGURE 15-32:
BUS COLLISION DURING A STOP CONDITION (CASE 2)
TBRG
TBRG
TBRG
SDAx
SCLx goes low before SDAx goes high,
set BCLxIF
Assert SDAx
SCLx
PEN
BCLxIF
P
‘0’
‘0’
SSPxIF
DS39682C-page 184
Preliminary
© 2007 Microchip Technology Inc.
PIC18F45J10 FAMILY
TABLE 15-4: REGISTERS ASSOCIATED WITH I2C™ OPERATION
Reset
Values
on Page
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
INTCON
PIR1
GIE/GIEH PEIE/GIEL TMR0IE
INT0IE
TXIF
TXIE
TXIP
—
RBIE
SSP1IF
SSP1IE
SSP1IP
BCL1IF
BCL1IE
BCL1IP
—
TMR0IF
CCP1IF
CCP1IE
CCP1IP
—
INT0IF
RBIF
43
45
45
45
45
45
45
45
45
45
46
46
44
44
PSPIF(1)
PSPIE(1)
PSPIP(1)
OSCFIF
OSCFIE
OSCFIP
SSP2IF
SSP2IE
SSP2IP
TRISC7
TRISD7
ADIF
ADIE
RCIF
RCIE
RCIP
—
TMR2IF
TMR1IF
PIE1
TMR2IE TMR1IE
TMR2IP TMR1IP
IPR1
ADIP
PIR2
CMIF
—
—
CCP2IF
CCP2IE
CCP2IP
—
PIE2
CMIE
—
—
—
IPR2
CMIP
—
—
—
—
PIR3
BCL2IF
BCL2IE
BCL2IP
TRISC6
TRISD6
—
—
—
—
PIE3
—
—
—
—
—
—
IPR3
—
—
—
—
—
—
TRISC
TRISD(1)
TRISC5
TRISD5
TRISC4
TRISD4
TRISC3
TRISD3
TRISC2
TRISD2
TRISC1
TRISD1
TRISC0
TRISD0
SSP1BUF MSSP1 Receive Buffer/Transmit Register
SSP1ADD MSSP1 Address Register (I2C™ Slave mode).
MSSP1 Baud Rate Reload Register (I2C Master mode).
SSP1CON1 WCOL
SSP1CON2 GCEN
SSPOV
ACKSTAT ACKDT
CKE D/A
SSPEN
CKP
ACKEN
P
SSPM3
RCEN
S
SSPM2
PEN
SSPM1
RSEN
UA
SSPM0
SEN
BF
44
44
44
46
46
SSP1STAT
SMP
R/W
SSP2BUF MSSP2 Receive Buffer/Transmit Register
SSP2ADD MSSP2 Address Register (I2C Slave mode).
MSSP2 Baud Rate Reload Register (I2C Master mode).
SSP2CON1 WCOL
SSP2CON2 GCEN
SSPOV
ACKSTAT ACKDT
CKE D/A
SSPEN
CKP
ACKEN
P
SSPM3
RCEN
S
SSPM2
PEN
SSPM1
RSEN
UA
SSPM0
SEN
BF
46
46
46
SSP2STAT
SMP
R/W
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the MSSP module in I2C™ mode.
Note 1: These registers and/or bits are not implemented on 28-pin devices and should be read as ‘0’.
© 2007 Microchip Technology Inc.
Preliminary
DS39682C-page 185
PIC18F45J10 FAMILY
NOTES:
DS39682C-page 186
Preliminary
© 2007 Microchip Technology Inc.
PIC18F45J10 FAMILY
The pins of the Enhanced USART are multiplexed
with PORTC. In order to configure RC6/TX/CK and
RC7/RX/DT as an EUSART:
16.0 ENHANCED UNIVERSAL
SYNCHRONOUS
ASYNCHRONOUS RECEIVER
TRANSMITTER (EUSART)
• bit SPEN (RCSTA<7>) must be set (= 1)
• bit TRISC<7> must be set (= 1)
• bit TRISC<6> must be set (= 1)
The Enhanced Universal Synchronous Asynchronous
Receiver Transmitter (EUSART) module is one of the
two serial I/O modules. (Generically, the USART is also
known as a Serial Communications Interface or SCI.)
The EUSART can be configured as a full-duplex
asynchronous system that can communicate with
peripheral devices, such as CRT terminals and
personal computers. It can also be configured as a half-
duplex synchronous system that can communicate
with peripheral devices, such as A/D or D/A integrated
circuits, serial EEPROMs, etc.
Note:
The EUSART control will automatically
reconfigure the pin from input to output as
needed.
The operation of the Enhanced USART module is
controlled through three registers:
• Transmit Status and Control (TXSTA)
• Receive Status and Control (RCSTA)
• Baud Rate Control (BAUDCON)
These are detailed on the following pages in
Register 16-1, Register 16-2 and Register 16-3,
respectively.
The Enhanced USART module implements additional
features, including automatic baud rate detection and
calibration, automatic wake-up on Sync Break recep-
tion and 12-bit Break character transmit. These make it
ideally suited for use in Local Interconnect Network bus
(LIN bus) systems.
The EUSART can be configured in the following
modes:
• Asynchronous (full duplex) with:
- Auto-wake-up on character reception
- Auto-baud calibration
- 12-bit Break character transmission
• Synchronous – Master (half duplex) with
selectable clock polarity
• Synchronous – Slave (half duplex) with selectable
clock polarity
© 2007 Microchip Technology Inc.
Preliminary
DS39682C-page 187
PIC18F45J10 FAMILY
REGISTER 16-1: TXSTA: TRANSMIT STATUS AND CONTROL REGISTER
R/W-0
CSRC
R/W-0
TX9
R/W-0
TXEN
R/W-0
SYNC
R/W-0
R/W-0
BRGH
R-1
R/W-0
TX9D
SENDB
TRMT
bit 7
bit 0
bit 7
CSRC: Clock Source Select bit
Asynchronous mode:
Don’t care.
Synchronous mode:
1= Master mode (clock generated internally from BRG)
0= Slave mode (clock from external source)
bit 6
bit 5
TX9: 9-bit Transmit Enable bit
1= Selects 9-bit transmission
0= Selects 8-bit transmission
TXEN: Transmit Enable bit
1= Transmit enabled
0= Transmit disabled
Note:
SREN/CREN overrides TXEN in Sync mode.
bit 4
bit 3
SYNC: EUSART Mode Select bit
1= Synchronous mode
0= Asynchronous mode
SENDB: Send Break Character bit
Asynchronous mode:
1= Send Sync Break on next transmission (cleared by hardware upon completion)
0= Sync Break transmission completed
Synchronous mode:
Don’t care.
bit 2
BRGH: High Baud Rate Select bit
Asynchronous mode:
1= High speed
0= Low speed
Synchronous mode:
Unused in this mode.
bit 1
bit 0
TRMT: Transmit Shift Register Status bit
1= TSR empty
0= TSR full
TX9D: 9th bit of Transmit Data
Can be address/data bit or a parity bit.
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
DS39682C-page 188
Preliminary
© 2007 Microchip Technology Inc.
PIC18F45J10 FAMILY
REGISTER 16-2: RCSTA: RECEIVE STATUS AND CONTROL REGISTER
R/W-0
SPEN
R/W-0
RX9
R/W-0
SREN
R/W-0
CREN
R/W-0
R-0
R-0
R-x
ADDEN
FERR
OERR
RX9D
bit 7
bit 0
bit 7
bit 6
bit 5
SPEN: Serial Port Enable bit
1= Serial port enabled (configures RX/DT and TX/CK pins as serial port pins)
0= Serial port disabled (held in Reset)
RX9: 9-bit Receive Enable bit
1= Selects 9-bit reception
0= Selects 8-bit reception
SREN: Single Receive Enable bit
Asynchronous mode:
Don’t care.
Synchronous mode – Master:
1= Enables single receive
0= Disables single receive
This bit is cleared after reception is complete.
Synchronous mode – Slave:
Don’t care.
bit 4
CREN: Continuous Receive Enable bit
Asynchronous mode:
1= Enables receiver
0= Disables receiver
Synchronous mode:
1= Enables continuous receive until enable bit CREN is cleared (CREN overrides SREN)
0= Disables continuous receive
bit 3
ADDEN: Address Detect Enable bit
Asynchronous mode 9-bit (RX9 = 1):
1= Enables address detection, enables interrupt and loads the receive buffer when RSR<8>
is set
0= Disables address detection, all bytes are received and ninth bit can be used as parity bit
Asynchronous mode 9-bit (RX9 = 0):
Don’t care.
bit 2
bit 1
bit 0
FERR: Framing Error bit
1= Framing error (can be updated by reading RCREG register and receiving next valid byte)
0= No framing error
OERR: Overrun Error bit
1= Overrun error (can be cleared by clearing bit CREN)
0= No overrun error
RX9D: 9th bit of Received Data
This can be address/data bit or a parity bit and must be calculated by user firmware.
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
© 2007 Microchip Technology Inc.
Preliminary
DS39682C-page 189
PIC18F45J10 FAMILY
REGISTER 16-3: BAUDCON: BAUD RATE CONTROL REGISTER
R/W-0
ABDOVF
bit 7
R-1
U-0
—
R/W-0
SCKP
R/W-0
U-0
—
R/W-0
WUE
R/W-0
RCIDL
BRG16
ABDEN
bit 0
bit 7
bit 6
ABDOVF: Auto-Baud Acquisition Rollover Status bit
1= A BRG rollover has occurred during Auto-Baud Rate Detect mode
(must be cleared in software)
0= No BRG rollover has occurred
RCIDL: Receive Operation Idle Status bit
1= Receive operation is Idle
0= Receive operation is active
bit 5
bit 4
Unimplemented: Read as ‘0’
SCKP: Synchronous Clock Polarity Select bit
Asynchronous mode:
Unused in this mode.
Synchronous mode:
1= Idle state for clock (CK) is a high level
0= Idle state for clock (CK) is a low level
bit 3
BRG16: 16-bit Baud Rate Register Enable bit
1= 16-bit Baud Rate Generator – SPBRGH and SPBRG
0= 8-bit Baud Rate Generator – SPBRG only (Compatible mode), SPBRGH value ignored
bit 2
bit 1
Unimplemented: Read as ‘0’
WUE: Wake-up Enable bit
Asynchronous mode:
1= EUSART will continue to sample the RX pin – interrupt generated on falling edge; bit
cleared in hardware on following rising edge
0= RX pin not monitored or rising edge detected
Synchronous mode:
Unused in this mode.
bit 0
ABDEN: Auto-Baud Detect Enable bit
Asynchronous mode:
1= Enable baud rate measurement on the next character. Requires reception of a Sync field
(55h); cleared in hardware upon completion
0= Baud rate measurement disabled or completed
Synchronous mode:
Unused in this mode.
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
DS39682C-page 190
Preliminary
© 2007 Microchip Technology Inc.
PIC18F45J10 FAMILY
tageous to use the high baud rate (BRGH = 1) or the
16-bit BRG to reduce the baud rate error, or achieve a
slow baud rate for a fast oscillator frequency.
16.1
Baud Rate Generator (BRG)
The BRG is a dedicated 8-bit or 16-bit generator that
supports both the Asynchronous and Synchronous
modes of the EUSART. By default, the BRG operates
in 8-bit mode; setting the BRG16 bit (BAUDCON<3>)
selects 16-bit mode.
Writing a new value to the SPBRGH:SPBRG registers
causes the BRG timer to be reset (or cleared). This
ensures the BRG does not wait for a timer overflow
before outputting the new baud rate.
The SPBRGH:SPBRG register pair controls the period
of a free running timer. In Asynchronous mode, bits
BRGH (TXSTA<2>) and BRG16 (BAUDCON<3>) also
control the baud rate. In Synchronous mode, BRGH is
ignored. Table 16-1 shows the formula for computation
of the baud rate for different EUSART modes which
only apply in Master mode (internally generated clock).
16.1.1
OPERATION IN POWER-MANAGED
MODES
The device clock is used to generate the desired baud
rate. When one of the power-managed modes is
entered, the new clock source may be operating at a
different frequency. This may require an adjustment to
the value in the SPBRG register pair.
Given the desired baud rate and FOSC, the nearest
integer value for the SPBRGH:SPBRG registers can be
calculated using the formulas in Table 16-1. From this,
the error in baud rate can be determined. An example
calculation is shown in Example 16-1. Typical baud
rates and error values for the various Asynchronous
modes are shown in Table 16-2. It may be advan-
16.1.2
SAMPLING
The data on the RX pin is sampled three times by a
majority detect circuit to determine if a high or a low
level is present at the RX pin.
TABLE 16-1: BAUD RATE FORMULAS
Configuration Bits
BRG/EUSART Mode
Baud Rate Formula
SYNC
BRG16
BRGH
0
0
0
0
1
1
0
0
1
1
0
1
0
1
0
1
x
x
8-bit/Asynchronous
8-bit/Asynchronous
16-bit/Asynchronous
16-bit/Asynchronous
8-bit/Synchronous
16-bit/Synchronous
FOSC/[64 (n + 1)]
FOSC/[16 (n + 1)]
FOSC/[4 (n + 1)]
Legend: x= Don’t care, n = value of SPBRGH:SPBRG register pair
© 2007 Microchip Technology Inc.
Preliminary
DS39682C-page 191
PIC18F45J10 FAMILY
EXAMPLE 16-1:
CALCULATING BAUD RATE ERROR
For a device with FOSC of 16 MHz, desired baud rate of 9600, Asynchronous mode, 8-bit BRG:
Desired Baud Rate FOSC/(64 ([SPBRGH:SPBRG] + 1))
Solving for SPBRGH:SPBRG:
=
X
=
=
=
=
=
=
=
((FOSC/Desired Baud Rate)/64) – 1
((16000000/9600)/64) – 1
[25.042] = 25
16000000/(64 (25 + 1))
9615
Calculated Baud Rate
Error
(Calculated Baud Rate – Desired Baud Rate)/Desired Baud Rate
(9615 – 9600)/9600 = 0.16%
TABLE 16-2: REGISTERS ASSOCIATED WITH BAUD RATE GENERATOR
Reset Values
on page
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
TXSTA
RCSTA
CSRC
SPEN
TX9
RX9
TXEN
SREN
—
SYNC
CREN
SCKP
SENDB
ADDEN
BRG16
BRGH
FERR
—
TRMT
OERR
WUE
TX9D
RX9D
45
45
45
45
45
BAUDCON ABDOVF RCIDL
ABDEN
SPBRGH EUSART Baud Rate Generator Register High Byte
SPBRG EUSART Baud Rate Generator Register Low Byte
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the BRG.
DS39682C-page 192
Preliminary
© 2007 Microchip Technology Inc.
PIC18F45J10 FAMILY
TABLE 16-3: BAUD RATES FOR ASYNCHRONOUS MODES
SYNC = 0, BRGH = 0, BRG16 = 0
BAUD
RATE
(K)
FOSC = 40.000 MHz
FOSC = 20.000 MHz FOSC = 10.000 MHz
FOSC = 8.000 MHz
Actual
Rate
(K)
SPBRG Actual
value
SPBRG Actual
SPBRG Actual
value
(decimal)
SPBRG
value
(decimal)
%
%
Error
%
Error
%
Error
Rate
(K)
value
Rate
(K)
Rate
(K)
Error
(decimal)
(decimal)
0.3
1.2
—
—
—
—
—
—
—
255
129
31
15
4
—
—
—
129
64
15
7
—
1201
2403
9615
—
—
-0.16
-0.16
-0.16
—
—
103
51
12
—
—
—
1.221
1.73
0.16
1.73
1.73
8.51
-9.58
1.202
2.404
9.766
19.531
52.083
78.125
0.16
0.16
1.73
1.73
-9.58
-32.18
2.4
2.441
9.615
19.531
56.818
125.000
1.73
0.16
1.73
-1.36
8.51
255
64
31
10
4
2.404
9.6
9.766
19.2
57.6
115.2
19.531
62.500
104.167
2
—
—
—
2
1
—
—
—
SYNC = 0, BRGH = 0, BRG16 = 0
BAUD
RATE
(K)
FOSC = 4.000 MHz
FOSC = 2.000 MHz
FOSC = 1.000 MHz
Actual
Rate
(K)
SPBRG Actual
value
SPBRG Actual
value
(decimal)
SPBRG
value
(decimal)
%
%
Error
%
Error
Rate
(K)
Rate
(K)
Error
(decimal)
0.3
1.2
0.300
1.202
0.16
0.16
207
51
25
6
300
1201
2403
—
-0.16
-0.16
-0.16
—
103
25
12
—
300
1201
—
-0.16
-0.16
—
51
12
—
—
—
—
—
2.4
2.404
0.16
9.6
8.929
-6.99
8.51
—
—
19.2
57.6
115.2
20.833
62.500
62.500
2
—
—
—
—
—
8.51
0
—
—
—
—
—
-45.75
0
—
—
—
—
—
SYNC = 0, BRGH = 1, BRG16 = 0
BAUD
RATE
(K)
FOSC = 40.000 MHz
FOSC = 20.000 MHz
FOSC = 10.000 MHz
FOSC = 8.000 MHz
Actual
Rate
(K)
SPBRG Actual
value
(decimal)
SPBRG Actual
value
(decimal)
SPBRG Actual
value
(decimal)
SPBRG
value
%
Error
%
Error
%
Error
%
Error
Rate
(K)
Rate
(K)
Rate
(K)
(decimal)
0.3
1.2
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
2.4
—
—
—
—
—
—
2.441
9.615
19.531
56.818
125.000
1.73
0.16
1.73
-1.36
8.51
255
64
31
10
4
2403
9615
19230
55555
—
-0.16
-0.16
-0.16
3.55
—
207
51
25
8
9.6
9.766
19.231
58.140
113.636
1.73
0.16
0.94
-1.36
255
129
42
9.615
19.231
56.818
113.636
0.16
0.16
-1.36
-1.36
129
64
21
10
19.2
57.6
115.2
21
—
SYNC = 0, BRGH = 1, BRG16 = 0
BAUD
RATE
(K)
FOSC = 4.000 MHz
FOSC = 2.000 MHz
FOSC = 1.000 MHz
Actual
Rate
(K)
SPBRG Actual
value
SPBRG Actual
value
(decimal)
SPBRG
value
(decimal)
%
%
Error
%
Error
Rate
(K)
Rate
(K)
Error
(decimal)
0.3
1.2
—
—
—
207
103
25
12
3
—
1201
2403
9615
—
—
-0.16
-0.16
-0.16
—
—
103
51
12
—
300
1201
2403
—
-0.16
-0.16
-0.16
—
207
51
25
—
1.202
0.16
0.16
0.16
0.16
8.51
8.51
2.4
2.404
9.6
9.615
19.2
57.6
115.2
19.231
62.500
125.000
—
—
—
—
—
—
—
—
—
1
—
—
—
—
—
—
© 2007 Microchip Technology Inc.
Preliminary
DS39682C-page 193
PIC18F45J10 FAMILY
TABLE 16-3: BAUD RATES FOR ASYNCHRONOUS MODES (CONTINUED)
SYNC = 0, BRGH = 0, BRG16 = 1
BAUD
RATE
(K)
FOSC = 40.000 MHz
FOSC = 20.000 MHz
FOSC = 10.000 MHz
FOSC = 8.000 MHz
Actual
Rate
(K)
SPBRG Actual
value
SPBRG Actual
value
(decimal)
SPBRG Actual
value
(decimal)
SPBRG
value
(decimal)
%
%
Error
%
Error
%
Error
Rate
(K)
Rate
(K)
Rate
(K)
Error
(decimal)
0.3
1.2
0.300
1.200
0.00
0.02
0.06
0.16
0.16
0.94
-1.36
8332
2082
1040
259
129
42
0.300
1.200
0.02
-0.03
-0.03
0.16
4165
1041
520
129
64
0.300
1.200
0.02
-0.03
0.16
0.16
1.73
-1.36
8.51
2082
520
259
64
300
1201
2403
9615
19230
55555
—
-0.04
-0.16
-0.16
-0.16
-0.16
3.55
—
1665
415
207
51
2.4
2.402
2.399
2.404
9.6
9.615
9.615
9.615
19.2
57.6
115.2
19.231
58.140
113.636
19.231
56.818
113.636
0.16
19.531
56.818
125.000
31
25
-1.36
-1.36
21
10
8
21
10
4
—
SYNC = 0, BRGH = 0, BRG16 = 1
BAUD
RATE
(K)
FOSC = 4.000 MHz
FOSC = 2.000 MHz
FOSC = 1.000 MHz
Actual
Rate
(K)
SPBRG Actual
value
SPBRG Actual
value
(decimal)
SPBRG
value
(decimal)
%
%
Error
%
Error
Rate
(K)
Rate
(K)
Error
(decimal)
0.3
1.2
0.300
1.202
0.04
0.16
0.16
0.16
0.16
8.51
8.51
832
207
103
25
12
3
300
1201
2403
9615
—
-0.16
-0.16
-0.16
-0.16
—
415
103
51
12
—
300
1201
2403
—
-0.16
-0.16
-0.16
—
207
51
25
—
2.4
2.404
9.6
9.615
19.2
57.6
115.2
19.231
62.500
125.000
—
—
—
—
—
—
—
—
—
1
—
—
—
—
—
—
SYNC = 0, BRGH = 1, BRG16 = 1 or SYNC = 1, BRG16 = 1
FOSC = 20.000 MHz FOSC = 10.000 MHz
BAUD
RATE
(K)
FOSC = 40.000 MHz
FOSC = 8.000 MHz
Actual
Rate
(K)
SPBRG Actual
SPBRG Actual
SPBRG Actual
value
SPBRG
value
(decimal)
%
Error
%
%
%
Error
value
(decimal)
Rate
(K)
value
Rate
(K)
Rate
(K)
Error
Error
(decimal)
(decimal)
0.3
1.2
0.300
1.200
0.00
0.00
0.02
0.06
-0.03
0.35
-0.22
33332
8332
4165
1040
520
0.300
1.200
0.00
0.02
0.02
-0.03
0.16
-0.22
0.94
16665
4165
2082
520
259
86
0.300
1.200
0.00
0.02
0.06
0.16
0.16
0.94
-1.36
8332
2082
1040
259
129
42
300
1200
-0.01
-0.04
-0.04
-0.16
-0.16
0.79
6665
1665
832
207
103
34
2.4
2.400
2.400
2.402
2400
9.6
9.606
9.596
9.615
9615
19.2
57.6
115.2
19.193
57.803
114.943
19.231
57.471
116.279
19.231
58.140
113.636
19230
57142
117647
172
86
42
21
-2.12
16
SYNC = 0, BRGH = 1, BRG16 = 1 or SYNC = 1, BRG16 = 1
FOSC = 4.000 MHz FOSC = 2.000 MHz FOSC = 1.000 MHz
BAUD
RATE
(K)
Actual
Rate
(K)
SPBRG Actual
SPBRG Actual
SPBRG
value
(decimal)
%
Error
%
Error
%
Error
value
Rate
(K)
value
Rate
(K)
(decimal)
(decimal)
0.3
1.2
0.300
1.200
0.01
0.04
0.16
0.16
0.16
2.12
-3.55
3332
832
415
103
51
300
1201
2403
9615
19230
55555
—
-0.04
-0.16
-0.16
-0.16
-0.16
3.55
—
1665
415
207
51
300
1201
2403
9615
19230
—
-0.04
-0.16
-0.16
-0.16
-0.16
—
832
207
103
25
2.4
2.404
9.6
9.615
19.2
57.6
115.2
19.231
58.824
111.111
25
12
16
8
—
8
—
—
—
—
DS39682C-page 194
Preliminary
© 2007 Microchip Technology Inc.
PIC18F45J10 FAMILY
16.1.3
AUTO-BAUD RATE DETECT
Note 1: If the WUE bit is set with the ABDEN bit,
Auto-Baud Rate Detection will occur on
the byte following the Break character.
The Enhanced USART module supports the automatic
detection and calibration of baud rate. This feature is
active only in Asynchronous mode and while the WUE
bit is clear.
2: It is up to the user to determine that the
incoming character baud rate is within the
range of the selected BRG clock source.
Some combinations of oscillator frequency
and EUSART baud rates are not possible
due to bit error rates. Overall system tim-
ing and communication baud rates must
be taken into consideration when using the
Auto-Baud Rate Detection feature.
The automatic baud rate measurement sequence
(Figure 16-1) begins whenever a Start bit is received
and the ABDEN bit is set. The calculation is
self-averaging.
In the Auto-Baud Rate Detect (ABD) mode, the clock to
the BRG is reversed. Rather than the BRG clocking the
incoming RX signal, the RX signal is timing the BRG. In
ABD mode, the internal Baud Rate Generator is used
as a counter to time the bit period of the incoming serial
byte stream.
TABLE 16-4: BRG COUNTER
CLOCK RATES
Once the ABDEN bit is set, the state machine will clear
the BRG and look for a Start bit. The Auto-Baud Rate
Detect must receive a byte with the value 55h (ASCII
“U”, which is also the LIN bus Sync character) in order to
calculate the proper bit rate. The measurement is taken
over both a low and a high bit time in order to minimize
any effects caused by asymmetry of the incoming signal.
After a Start bit, the SPBRG begins counting up, using
the preselected clock source on the first rising edge of
RX. After eight bits on the RX pin or the fifth rising edge,
an accumulated value totalling the proper BRG period is
left in the SPBRGH:SPBRG register pair. Once the 5th
edge is seen (this should correspond to the Stop bit), the
ABDEN bit is automatically cleared.
BRG16 BRGH
BRG Counter Clock
0
0
1
1
0
1
0
1
FOSC/512
FOSC/128
FOSC/128
FOSC/32
Note: During the ABD sequence, SPBRG and
SPBRGH are both used as a 16-bit counter,
independent of BRG16 setting.
16.1.3.1
ABD and EUSART Transmission
Since the BRG clock is reversed during ABD acquisi-
tion, the EUSART transmitter cannot be used during
ABD. This means that whenever the ABDEN bit is set,
TXREG cannot be written to. Users should also ensure
that ABDEN does not become set during a transmit
sequence. Failing to do this may result in unpredictable
EUSART operation.
If a rollover of the BRG occurs (an overflow from FFFFh
to 0000h), the event is trapped by the ABDOVF status
bit (BAUDCON<7>). It is set in hardware by BRG roll-
overs and can be set or cleared by the user in software.
ABD mode remains active after rollover events and the
ABDEN bit remains set (Figure 16-2).
While calibrating the baud rate period, the BRG regis-
ters are clocked at 1/8th the preconfigured clock rate.
Note that the BRG clock will be configured by the
BRG16 and BRGH bits. Independent of the BRG16 bit
setting, both the SPBRG and SPBRGH will be used as
a 16-bit counter. This allows the user to verify that no
carry occurred for 8-bit modes by checking for 00h in
the SPBRGH register. Refer to Table 16-4 for counter
clock rates to the BRG.
While the ABD sequence takes place, the EUSART
state machine is held in Idle. The RCIF interrupt is set
once the fifth rising edge on RX is detected. The value
in the RCREG needs to be read to clear the RCIF
interrupt. ThecontentsofRCREG shouldbediscarded.
© 2007 Microchip Technology Inc.
Preliminary
DS39682C-page 195
PIC18F45J10 FAMILY
FIGURE 16-1:
AUTOMATIC BAUD RATE CALCULATION
BRG Value
RX pin
XXXXh
0000h
001Ch
Edge #5
Stop Bit
Edge #2
Bit 3
Edge #3
Bit 5
Edge #4
Bit 7
Bit 6
Edge #1
Bit 1
Start
Bit 0
Bit 2
Bit 4
BRG Clock
Auto-Cleared
Set by User
ABDEN bit
RCIF bit
(Interrupt)
Read
RCREG
XXXXh
XXXXh
1Ch
00h
SPBRG
SPBRGH
Note: The ABD sequence requires the EUSART module to be configured in Asynchronous mode and WUE = 0.
FIGURE 16-2:
BRG OVERFLOW SEQUENCE
BRG Clock
ABDEN bit
RX pin
Start
Bit 0
ABDOVF bit
BRG Value
FFFFh
XXXXh
0000h
0000h
DS39682C-page 196
Preliminary
© 2007 Microchip Technology Inc.
PIC18F45J10 FAMILY
Once the TXREG register transfers the data to the TSR
register (occurs in one TCY), the TXREG register is empty
and the TXIF flag bit (PIR1<4>) is set. This interrupt can
be enabled or disabled by setting or clearing the interrupt
enable bit, TXIE (PIE1<4>). TXIF will be set regardless of
the state of TXIE; it cannot be cleared in software. TXIF
is also not cleared immediately upon loading TXREG, but
becomes valid in the second instruction cycle following
the load instruction. Polling TXIF immediately following a
load of TXREG will return invalid results.
16.2 EUSART Asynchronous Mode
The Asynchronous mode of operation is selected by
clearing the SYNC bit (TXSTA<4>). In this mode, the
EUSART uses standard Non-Return-to-Zero (NRZ) for-
mat (one Start bit, eight or nine data bits and one Stop
bit). The most common data format is 8 bits. An on-chip
dedicated 8-bit/16-bit Baud Rate Generator can be used
to derive standard baud rate frequencies from the
oscillator.
The EUSART transmits and receives the LSb first. The
EUSART’s transmitter and receiver are functionally
independent but use the same data format and baud
rate. The Baud Rate Generator produces a clock, either
x16 or x64 of the bit shift rate depending on the BRGH
and BRG16 bits (TXSTA<2> and BAUDCON<3>). Parity
is not supported by the hardware but can be
implemented in software and stored as the 9th data bit.
While TXIF indicates the status of the TXREG register,
another bit, TRMT (TXSTA<1>), shows the status of
the TSR register. TRMT is a read-only bit which is set
when the TSR register is empty. No interrupt logic is
tied to this bit so the user has to poll this bit in order to
determine if the TSR register is empty.
Note 1: The TSR register is not mapped in data
When operating in Asynchronous mode, the EUSART
module consists of the following important elements:
memory so it is not available to the user.
2: Flag bit TXIF is set when enable bit TXEN
• Baud Rate Generator
is set.
• Sampling Circuit
To set up an Asynchronous Transmission:
• Asynchronous Transmitter
• Asynchronous Receiver
1. Initialize the SPBRGH:SPBRG registers for the
appropriate baud rate. Set or clear the BRGH
and BRG16 bits, as required, to achieve the
desired baud rate.
• Auto-Wake-up on Sync Break Character
• 12-bit Break Character Transmit
• Auto-Baud Rate Detection
2. Enable the asynchronous serial port by clearing
bit SYNC and setting bit SPEN.
16.2.1
EUSART ASYNCHRONOUS
TRANSMITTER
3. If interrupts are desired, set enable bit TXIE.
4. If 9-bit transmission is desired, set transmit bit
TX9. Can be used as address/data bit.
The EUSART transmitter block diagram is shown in
Figure 16-3. The heart of the transmitter is the Transmit
(Serial) Shift Register (TSR). The Shift register obtains
its data from the Read/Write Transmit Buffer register,
TXREG. The TXREG register is loaded with data in
software. The TSR register is not loaded until the Stop
bit has been transmitted from the previous load. As
soon as the Stop bit is transmitted, the TSR is loaded
with new data from the TXREG register (if available).
5. Enable the transmission by setting bit TXEN
which will also set bit TXIF.
6. If 9-bit transmission is selected, the ninth bit
should be loaded in bit TX9D.
7. Load data to the TXREG register (starts
transmission).
8. If using interrupts, ensure that the GIE and PEIE
bits in the INTCON register (INTCON<7:6>) are
set.
FIGURE 16-3:
EUSART TRANSMIT BLOCK DIAGRAM
Data Bus
TXREG Register
TXIF
TXIE
8
MSb
(8)
LSb
0
Pin Buffer
and Control
•
•
•
TSR Register
TX pin
Interrupt
Baud Rate CLK
SPBRG
TXEN
TRMT
SPEN
BRG16
SPBRGH
TX9
Baud Rate Generator
TX9D
© 2007 Microchip Technology Inc.
Preliminary
DS39682C-page 197
PIC18F45J10 FAMILY
FIGURE 16-4:
ASYNCHRONOUS TRANSMISSION
Write to TXREG
Word 1
BRG Output
(Shift Clock)
TX (pin)
Start bit
bit 0
bit 1
Word 1
bit 7/8
Stop bit
TXIF bit
(Transmit Buffer
Reg. Empty Flag)
1 TCY
Word 1
Transmit Shift Reg
TRMT bit
(Transmit Shift
Reg. Empty Flag)
FIGURE 16-5:
ASYNCHRONOUS TRANSMISSION (BACK TO BACK)
Write to TXREG
Word 2
Start bit
Word 1
BRG Output
(Shift Clock)
TX (pin)
Start bit
Word 2
bit 0
bit 1
bit 7/8
bit 0
Stop bit
1 TCY
Word 1
TXIF bit
(Interrupt Reg. Flag)
1 TCY
Word 1
Transmit Shift Reg.
Word 2
Transmit Shift Reg.
TRMT bit
(Transmit Shift
Reg. Empty Flag)
Note: This timing diagram shows two consecutive transmissions.
TABLE 16-5: REGISTERS ASSOCIATED WITH ASYNCHRONOUS TRANSMISSION
Reset
Values
on page
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
INTCON
PIR1
GIE/GIEH PEIE/GIEL TMR0IE
INT0IE
TXIF
RBIE
TMR0IF
CCP1IF
INT0IF
RBIF
43
45
45
45
45
45
45
45
45
45
PSPIF(1)
PSPIE(1)
PSPIP(1)
SPEN
ADIF
ADIE
ADIP
RX9
RCIF
RCIE
RCIP
SREN
SSP1IF
SSP1IE
SSP1IP
ADDEN
TMR2IF
TMR1IF
PIE1
TXIE
CCP1IE TMR2IE TMR1IE
CCP1IP TMR2IP TMR1IP
IPR1
TXIP
RCSTA
TXREG
TXSTA
BAUDCON
SPBRGH
SPBRG
CREN
FERR
OERR
RX9D
EUSART Transmit Register
CSRC
TX9
TXEN
—
SYNC
SCKP
SENDB
BRG16
BRGH
—
TRMT
WUE
TX9D
ABDOVF
RCIDL
ABDEN
EUSART Baud Rate Generator Register High Byte
EUSART Baud Rate Generator Register Low Byte
Legend: — = unimplemented locations read as ‘0’. Shaded cells are not used for asynchronous transmission.
Note 1: These bits are not implemented on 28-pin devices and should be read as ‘0’.
DS39682C-page 198
Preliminary
© 2007 Microchip Technology Inc.
PIC18F45J10 FAMILY
16.2.2
EUSART ASYNCHRONOUS
RECEIVER
16.2.3
SETTING UP 9-BIT MODE WITH
ADDRESS DETECT
The receiver block diagram is shown in Figure 16-6.
The data is received on the RX pin and drives the data
recovery block. The data recovery block is actually a
high-speed shifter operating at x16 times the baud rate,
whereas the main receive serial shifter operates at the
bit rate or at FOSC. This mode would typically be used
in RS-232 systems.
This mode would typically be used in RS-485 systems.
To set up an Asynchronous Reception with Address
Detect Enable:
1. Initialize the SPBRGH:SPBRG registers for the
appropriate baud rate. Set or clear the BRGH
and BRG16 bits, as required, to achieve the
desired baud rate.
To set up an Asynchronous Reception:
2. Enable the asynchronous serial port by clearing
the SYNC bit and setting the SPEN bit.
1. Initialize the SPBRGH:SPBRG registers for the
appropriate baud rate. Set or clear the BRGH
and BRG16 bits, as required, to achieve the
desired baud rate.
3. If interrupts are required, set the RCEN bit and
select the desired priority level with the RCIP bit.
4. Set the RX9 bit to enable 9-bit reception.
5. Set the ADDEN bit to enable address detect.
6. Enable reception by setting the CREN bit.
2. Enable the asynchronous serial port by clearing
bit SYNC and setting bit SPEN.
3. If interrupts are desired, set enable bit RCIE.
4. If 9-bit reception is desired, set bit RX9.
5. Enable the reception by setting bit CREN.
7. The RCIF bit will be set when reception is
complete. The interrupt will be Acknowledged if
the RCIE and GIE bits are set.
6. Flag bit, RCIF, will be set when reception is
complete and an interrupt will be generated if
enable bit, RCIE, was set.
8. Read the RCSTA register to determine if any
error occurred during reception, as well as read
bit 9 of data (if applicable).
7. Read the RCSTA register to get the 9th bit (if
enabled) and determine if any error occurred
during reception.
9. Read RCREG to determine if the device is being
addressed.
10. If any error occurred, clear the CREN bit.
8. Read the 8-bit received data by reading the
RCREG register.
11. If the device has been addressed, clear the
ADDEN bit to allow all received data into the
receive buffer and interrupt the CPU.
9. If any error occurred, clear the error by clearing
enable bit CREN.
10. If using interrupts, ensure that the GIE and PEIE
bits in the INTCON register (INTCON<7:6>) are
set.
FIGURE 16-6:
EUSART RECEIVE BLOCK DIAGRAM
CREN
OERR
FERR
x64 Baud Rate CLK
SPBRGH SPBRG
÷ 64
RSR Register
• • •
MSb
Stop
LSb
Start
BRG16
or
÷ 16
(8)
7
1
0
or
Baud Rate Generator
÷ 4
RX9
Pin Buffer
and Control
Data
Recovery
RX
RX9D
RCREG Register
FIFO
SPEN
8
Interrupt
RCIF
RCIE
Data Bus
© 2007 Microchip Technology Inc.
Preliminary
DS39682C-page 199
PIC18F45J10 FAMILY
FIGURE 16-7:
ASYNCHRONOUS RECEPTION
Start
bit
Start
bit
Start
bit
RX (pin)
Stop
bit
Stop
bit
Stop
bit
bit 0 bit 1
bit 7/8
bit 0
bit 7/8
bit 7/8
Rcv Shift Reg
Rcv Buffer Reg
Word 2
RCREG
Word 1
RCREG
Read Rcv
Buffer Reg
RCREG
RCIF
(Interrupt Flag)
OERR bit
CREN
Note: This timing diagram shows three words appearing on the RX input. The RCREG (receive buffer) is read after the third word
causing the OERR (Overrun) bit to be set.
TABLE 16-6: REGISTERS ASSOCIATED WITH ASYNCHRONOUS RECEPTION
Reset
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Values
on page
INTCON
PIR1
GIE/GIEH PEIE/GIEL TMR0IE
INT0IE
TXIF
RBIE
TMR0IF
INT0IF
RBIF
43
45
45
45
45
45
45
45
45
45
PSPIF(1)
PSPIE(1)
PSPIP(1)
SPEN
ADIF
ADIE
ADIP
RX9
RCIF
RCIE
RCIP
SREN
SSP1IF
SSP1IE
SSP1IP
ADDEN
CCP1IF TMR2IF TMR1IF
CCP1IE TMR2IE TMR1IE
CCP1IP TMR2IP TMR1IP
PIE1
TXIE
IPR1
TXIP
RCSTA
RCREG
TXSTA
CREN
FERR
OERR
RX9D
EUSART Receive Register
CSRC
TX9
TXEN
—
SYNC
SCKP
SENDB
BRG16
BRGH
—
TRMT
WUE
TX9D
BAUDCON ABDOVF
RCIDL
ABDEN
SPBRGH
SPBRG
EUSART Baud Rate Generator Register High Byte
EUSART Baud Rate Generator Register Low Byte
Legend: — = unimplemented locations read as ‘0’. Shaded cells are not used for asynchronous reception.
Note 1: These bits are not implemented on 28-pin devices and should be read as ‘0’.
Following a wake-up event, the module generates an
RCIF interrupt. The interrupt is generated synchro-
nously to the Q clocks in normal operating modes
(Figure 16-8) and asynchronously, if the device is in
Sleep mode (Figure 16-9). The interrupt condition is
cleared by reading the RCREG register.
16.2.4
AUTO-WAKE-UP ON SYNC BREAK
CHARACTER
During Sleep mode, all clocks to the EUSART are
suspended. Because of this, the Baud Rate Generator
is inactive and a proper byte reception cannot be per-
formed. The auto-wake-up feature allows the controller
to wake-up due to activity on the RX/DT line while the
EUSART is operating in Asynchronous mode.
The WUE bit is automatically cleared once a low-to-
high transition is observed on the RX line following the
wake-up event. At this point, the EUSART module is in
Idle mode and returns to normal operation. This signals
to the user that the Sync Break event is over.
The auto-wake-up feature is enabled by setting the
WUE bit (BAUDCON<1>). Once set, the typical receive
sequence on RX/DT is disabled and the EUSART
remains in an Idle state, monitoring for a wake-up event
independent of the CPU mode. A wake-up event con-
sists of a high-to-low transition on the RX/DT line. (This
coincides with the start of a Sync Break or a Wake-up
Signal character for the LIN protocol.)
DS39682C-page 200
Preliminary
© 2007 Microchip Technology Inc.
PIC18F45J10 FAMILY
16.2.4.1
Special Considerations Using
Auto-Wake-up
16.2.4.2
Special Considerations Using
the WUE Bit
Since auto-wake-up functions by sensing rising edge
transitions on RX/DT, information with any state
changes before the Stop bit may signal a false end-of-
character and cause data or framing errors. To work
properly, therefore, the initial character in the transmis-
sion must be all ‘0’s. This can be 00h (8 bytes) for
standard RS-232 devices or 000h (12 bits) for LIN bus.
The timing of WUE and RCIF events may cause some
confusion when it comes to determining the validity of
received data. As noted, setting the WUE bit places the
EUSART in an Idle mode. The wake-up event causes a
receive interrupt by setting the RCIF bit. The WUE bit is
cleared after this when a rising edge is seen on RX/DT.
The interrupt condition is then cleared by reading the
RCREG register. Ordinarily, the data in RCREG will be
dummy data and should be discarded.
Oscillator start-up time must also be considered,
especially in applications using oscillators with longer
start-up intervals (i.e., HS mode). The Sync Break (or
Wake-up Signal) character must be of sufficient length
and be followed by a sufficient interval to allow enough
time for the selected oscillator to start and provide
proper initialization of the EUSART.
The fact that the WUE bit has been cleared (or is still
set) and the RCIF flag is set should not be used as an
indicator of the integrity of the data in RCREG. Users
should consider implementing a parallel method in
firmware to verify received data integrity.
To assure that no actual data is lost, check the RCIDL
bit to verify that a receive operation is not in process. If
a receive operation is not occurring, the WUE bit may
then be set just prior to entering the Sleep mode.
FIGURE 16-8:
AUTO-WAKE-UP BIT (WUE) TIMINGS DURING NORMAL OPERATION
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
Bit set by user
Auto-Cleared
OSC1
WUE bit(1)
RX/DT Line
RCIF
Cleared due to user read of RCREG
Note 1: The EUSART remains in Idle while the WUE bit is set.
FIGURE 16-9:
AUTO-WAKE-UP BIT (WUE) TIMINGS DURING SLEEP
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
Bit set by user
Q1
Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
Auto-Cleared
OSC1
WUE bit(2)
RX/DT Line
RCIF
Note 1
Cleared due to user read of RCREG
Sleep Ends
Sleep Command Executed
Note 1: If the wake-up event requires long oscillator warm-up time, the auto-clear of the WUE bit can occur before the oscillator is ready. This
sequence should not depend on the presence of Q clocks.
2: The EUSART remains in Idle while the WUE bit is set.
© 2007 Microchip Technology Inc.
Preliminary
DS39682C-page 201
PIC18F45J10 FAMILY
1. Configure the EUSART for the desired mode.
16.2.5
BREAK CHARACTER SEQUENCE
2. Set the TXEN and SENDB bits to set up the
Break character.
The EUSART module has the capability of sending the
special Break character sequences that are required by
the LIN bus standard. The Break character transmit
consists of a Start bit, followed by twelve ‘0’ bits and a
Stop bit. The frame Break character is sent whenever
the SENDB and TXEN bits (TXSTA<3> and
TXSTA<5>) are set while the Transmit Shift register is
loaded with data. Note that the value of data written to
TXREG will be ignored and all ‘0’s will be transmitted.
3. Load the TXREG with a dummy character to
initiate transmission (the value is ignored).
4. Write ‘55h’ to TXREG to load the Sync character
into the transmit FIFO buffer.
5. After the Break has been sent, the SENDB bit is
reset by hardware. The Sync character now
transmits in the preconfigured mode.
The SENDB bit is automatically reset by hardware after
the corresponding Stop bit is sent. This allows the user
to preload the transmit FIFO with the next transmit byte
following the Break character (typically, the Sync
character in the LIN specification).
When the TXREG becomes empty, as indicated by the
TXIF, the next data byte can be written to TXREG.
16.2.6
RECEIVING A BREAK CHARACTER
The Enhanced USART module can receive a Break
character in two ways.
Note that the data value written to the TXREG for the
Break character is ignored. The write simply serves the
purpose of initiating the proper sequence.
The first method forces configuration of the baud rate
at a frequency of 9/13 the typical speed. This allows for
the Stop bit transition to be at the correct sampling loca-
tion (13 bits for Break versus Start bit and 8 data bits for
typical data).
The TRMT bit indicates when the transmit operation is
active or Idle, just as it does during normal transmis-
sion. See Figure 16-10 for the timing of the Break
character sequence.
The second method uses the auto-wake-up feature
described in Section 16.2.4 “Auto-Wake-up on Sync
Break Character”. By enabling this feature, the
EUSART will sample the next two transitions on RX/DT,
cause an RCIF interrupt and receive the next data byte
followed by another interrupt.
16.2.5.1
Break and Sync Transmit Sequence
The following sequence will send a message frame
header made up of a Break, followed by an Auto-Baud
Sync byte. This sequence is typical of a LIN bus
master.
Note that following a Break character, the user will
typically want to enable the Auto-Baud Rate Detect
feature. For both methods, the user can set the ABD bit
once the TXIF interrupt is observed.
FIGURE 16-10:
SEND BREAK CHARACTER SEQUENCE
Write to TXREG
Dummy Write
BRG Output
(Shift Clock)
TX (pin)
Start Bit
Bit 0
Bit 1
Break
Bit 11
Stop Bit
TXIF bit
(Transmit Buffer
Reg. Empty Flag)
TRMT bit
(Transmit Shift
Reg. Empty Flag)
SENDB sampled here
Auto-Cleared
SENDB
(Transmit Shift
Reg. Empty Flag)
DS39682C-page 202
Preliminary
© 2007 Microchip Technology Inc.
PIC18F45J10 FAMILY
Once the TXREG register transfers the data to the TSR
register (occurs in one TCY), the TXREG is empty and
the TXIF flag bit (PIR1<4>) is set. The interrupt can be
enabled or disabled by setting or clearing the interrupt
enable bit, TXIE (PIE1<4>). TXIF is set regardless of
the state of enable bit TXIE; it cannot be cleared in
software. It will reset only when new data is loaded into
the TXREG register.
16.3 EUSART Synchronous
Master Mode
The Synchronous Master mode is entered by setting
the CSRC bit (TXSTA<7>). In this mode, the data is
transmitted in a half-duplex manner (i.e., transmission
and reception do not occur at the same time). When
transmitting data, the reception is inhibited and vice
versa. Synchronous mode is entered by setting bit
SYNC (TXSTA<4>). In addition, enable bit SPEN
(RCSTA<7>) is set in order to configure the TX and RX
pins to CK (clock) and DT (data) lines, respectively.
While flag bit TXIF indicates the status of the TXREG
register, another bit, TRMT (TXSTA<1>), shows the
status of the TSR register. TRMT is a read-only bit which
is set when the TSR is empty. No interrupt logic is tied to
this bit so the user has to poll this bit in order to deter-
mine if the TSR register is empty. The TSR is not
mapped in data memory so it is not available to the user.
The Master mode indicates that the processor trans-
mits the master clock on the CK line. Clock polarity is
selected with the SCKP bit (BAUDCON<4>). Setting
SCKP sets the Idle state on CK as high, while clearing
the bit sets the Idle state as low. This option is provided
to support Microwire devices with this module.
To set up a Synchronous Master Transmission:
1. Initialize the SPBRGH:SPBRG registers for the
appropriate baud rate. Set or clear the BRG16
bit, as required, to achieve the desired baud rate.
16.3.1
EUSART SYNCHRONOUS MASTER
TRANSMISSION
2. Enable the synchronous master serial port by
setting bits SYNC, SPEN and CSRC.
The EUSART transmitter block diagram is shown in
Figure 16-3. The heart of the transmitter is the Transmit
(Serial) Shift Register (TSR). The Shift register obtains
its data from the Read/Write Transmit Buffer register,
TXREG. The TXREG register is loaded with data in
software. The TSR register is not loaded until the last
bit has been transmitted from the previous load. As
soon as the last bit is transmitted, the TSR is loaded
with new data from the TXREG (if available).
3. If interrupts are desired, set enable bit TXIE.
4. If 9-bit transmission is desired, set bit TX9.
5. Enable the transmission by setting bit TXEN.
6. If 9-bit transmission is selected, the ninth bit
should be loaded in bit TX9D.
7. Start transmission by loading data to the TXREG
register.
8. If using interrupts, ensure that the GIE and PEIE
bits in the INTCON register (INTCON<7:6>) are
set.
FIGURE 16-11:
SYNCHRONOUS TRANSMISSION
Q1 Q2 Q3Q4 Q1 Q2 Q3 Q4 Q1Q2 Q3 Q4 Q1Q2 Q3 Q4 Q1 Q2 Q3 Q4
Q3 Q4 Q1 Q2 Q3Q4 Q1Q2 Q3Q4 Q1 Q2Q3Q4 Q1 Q2Q3 Q4Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
RC7/RX/DT
bit 0
bit 1
bit 2
bit 7
bit 0
bit 1
bit 7
Word 2
Word 1
RC6/TX/CK pin
(SCKP = 0)
RC6/TX/CK pin
(SCKP = 1)
Write to
TXREG Reg
Write Word 1
Write Word 2
TXIF bit
(Interrupt Flag)
TRMT bit
‘1’
‘1’
TXEN bit
Note: Sync Master mode, SPBRG = 0, continuous transmission of two 8-bit words.
© 2007 Microchip Technology Inc.
Preliminary
DS39682C-page 203
PIC18F45J10 FAMILY
FIGURE 16-12:
SYNCHRONOUS TRANSMISSION (THROUGH TXEN)
RC7/RX/DT pin
bit 0
bit 2
bit 1
bit 6
bit 7
RC6/TX/CK pin
Write to
TXREG reg
TXIF bit
TRMT bit
TXEN bit
TABLE 16-7: REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER TRANSMISSION
Reset
Values
on page
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
INTCON
PIR1
GIE/GIEH PEIE/GIEL TMR0IE
INT0IE
TXIF
RBIE
TMR0IF
INT0IF
RBIF
43
45
45
45
45
45
45
45
45
45
PSPIF(1)
PSPIE(1)
PSPIP(1)
SPEN
ADIF
ADIE
ADIP
RX9
RCIF
RCIE
RCIP
SREN
SSP1IF
SSP1IE
SSP1IP
ADDEN
CCP1IF TMR2IF TMR1IF
CCP1IE TMR2IE TMR1IE
CCP1IP TMR2IP TMR1IP
PIE1
TXIE
IPR1
TXIP
RCSTA
TXREG
TXSTA
CREN
FERR
OERR
RX9D
EUSART Transmit Register
CSRC
TX9
TXEN
—
SYNC
SCKP
SENDB
BRG16
BRGH
—
TRMT
WUE
TX9D
BAUDCON ABDOVF
RCIDL
ABDEN
SPBRGH
SPBRG
EUSART Baud Rate Generator Register High Byte
EUSART Baud Rate Generator Register Low Byte
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used for synchronous master transmission.
Note 1: These bits are not implemented on 28-pin devices and should be read as ‘0’.
DS39682C-page 204
Preliminary
© 2007 Microchip Technology Inc.
PIC18F45J10 FAMILY
3. Ensure bits CREN and SREN are clear.
4. If interrupts are desired, set enable bit RCIE.
5. If 9-bit reception is desired, set bit RX9.
16.3.2
EUSART SYNCHRONOUS
MASTER RECEPTION
Once Synchronous mode is selected, reception is
enabled by setting either the Single Receive Enable bit,
SREN (RCSTA<5>), or the Continuous Receive
Enable bit, CREN (RCSTA<4>). Data is sampled on the
RX pin on the falling edge of the clock.
6. If a single reception is required, set bit SREN.
For continuous reception, set bit CREN.
7. Interrupt flag bit, RCIF, will be set when reception
is complete and an interrupt will be generated if
the enable bit, RCIE, was set.
If enable bit SREN is set, only a single word is received.
If enable bit CREN is set, the reception is continuous
until CREN is cleared. If both bits are set, then CREN
takes precedence.
8. Read the RCSTA register to get the 9th bit (if
enabled) and determine if any error occurred
during reception.
9. Read the 8-bit received data by reading the
RCREG register.
To set up a Synchronous Master Reception:
1. Initialize the SPBRGH:SPBRG registers for the
appropriate baud rate. Set or clear the BRG16
bit, as required, to achieve the desired baud rate.
10. If any error occurred, clear the error by clearing
bit CREN.
11. If using interrupts, ensure that the GIE and PEIE bits
in the INTCON register (INTCON<7:6>) are set.
2. Enable the synchronous master serial port by
setting bits SYNC, SPEN and CSRC.
FIGURE 16-13:
SYNCHRONOUS RECEPTION (MASTER MODE, SREN)
Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4Q1 Q2 Q3 Q4 Q1Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
RC7/RX/DT
pin
bit 0
bit 1
bit 2
bit 3
bit 4
bit 5
bit 6
bit 7
RC6/TX/CK pin
(SCKP = 0)
RC6/TX/CK pin
(SCKP = 1)
Write to
bit SREN
SREN bit
CREN bit
‘0’
‘0’
RCIF bit
(Interrupt)
Read
RXREG
Note: Timing diagram demonstrates Sync Master mode with bit SREN = 1and bit BRGH = 0.
TABLE 16-8: REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER RECEPTION
Reset
Values
on page
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
INTCON
PIR1
GIE/GIEH PEIE/GIEL TMR0IE
INT0IE
TXIF
RBIE
TMR0IF
CCP1IF
CCP1IE
CCP1IP
FERR
INT0IF
RBIF
43
45
45
45
45
45
45
45
45
45
PSPIF(1)
PSPIE(1)
PSPIP(1)
SPEN
ADIF
ADIE
ADIP
RX9
RCIF
RCIE
RCIP
SREN
SSP1IF
SSP1IE
SSP1IP
ADDEN
TMR2IF TMR1IF
TMR2IE TMR1IE
TMR2IP TMR1IP
PIE1
TXIE
IPR1
TXIP
RCSTA
RCREG
TXSTA
CREN
OERR
RX9D
EUSART Receive Register
CSRC
TX9
TXEN
—
SYNC
SCKP
SENDB
BRG16
BRGH
—
TRMT
WUE
TX9D
BAUDCON ABDOVF
RCIDL
ABDEN
SPBRGH EUSART Baud Rate Generator Register High Byte
SPBRG EUSART Baud Rate Generator Register Low Byte
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used for synchronous master reception.
Note 1: These bits are not implemented on 28-pin devices and should be read as ‘0’.
© 2007 Microchip Technology Inc.
Preliminary
DS39682C-page 205
PIC18F45J10 FAMILY
To set up a Synchronous Slave Transmission:
16.4 EUSART Synchronous
Slave Mode
1. Enable the synchronous slave serial port by
setting bits SYNC and SPEN and clearing bit
CSRC.
Synchronous Slave mode is entered by clearing bit,
CSRC (TXSTA<7>). This mode differs from the
Synchronous Master mode in that the shift clock is sup-
plied externally at the CK pin (instead of being supplied
internally in Master mode). This allows the device to
transfer or receive data while in any low-power mode.
2. Clear bits CREN and SREN.
3. If interrupts are desired, set enable bit TXIE.
4. If 9-bit transmission is desired, set bit TX9.
5. Enable the transmission by setting enable bit
TXEN.
16.4.1
EUSART SYNCHRONOUS
SLAVE TRANSMISSION
6. If 9-bit transmission is selected, the ninth bit
should be loaded in bit TX9D.
The operation of the Synchronous Master and Slave
modes is identical, except in the case of the Sleep
mode.
7. Start transmission by loading data to the TXREG
register.
8. If using interrupts, ensure that the GIE and PEIE
bits in the INTCON register (INTCON<7:6>) are
set.
If two words are written to the TXREG and then the
SLEEPinstruction is executed, the following will occur:
a) The first word will immediately transfer to the
TSR register and transmit.
b) The second word will remain in the TXREG
register.
c) Flag bit, TXIF, will not be set.
d) When the first word has been shifted out of TSR,
the TXREG register will transfer the second
word to the TSR and flag bit, TXIF, will now be
set.
e) If enable bit TXIE is set, the interrupt will wake the
chip from Sleep. If the global interrupt is enabled,
the program will branch to the interrupt vector.
TABLE 16-9: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE TRANSMISSION
Reset
Values
on page
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
INTCON
PIR1
GIE/GIEH PEIE/GIEL TMR0IE
INT0IE
TXIF
RBIE
TMR0IF
CCP1IF
INT0IF
RBIF
43
45
45
45
45
45
45
45
45
45
PSPIF(1)
PSPIE(1)
PSPIP(1)
SPEN
ADIF
ADIE
ADIP
RX9
RCIF
RCIE
RCIP
SREN
SSP1IF
SSP1IE
SSP1IP
ADDEN
TMR2IF TMR1IF
PIE1
TXIE
CCP1IE TMR2IE TMR1IE
CCP1IP TMR2IP TMR1IP
IPR1
TXIP
RCSTA
TXREG
TXSTA
CREN
FERR
OERR
RX9D
EUSART Transmit Register
CSRC
TX9
TXEN
—
SYNC
SCKP
SENDB
BRG16
BRGH
—
TRMT
WUE
TX9D
BAUDCON ABDOVF
RCIDL
ABDEN
SPBRGH
SPBRG
EUSART Baud Rate Generator Register High Byte
EUSART Baud Rate Generator Register Low Byte
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used for synchronous slave transmission.
Note 1: These bits are not implemented on 28-pin devices and should be read as ‘0’.
DS39682C-page 206
Preliminary
© 2007 Microchip Technology Inc.
PIC18F45J10 FAMILY
To set up a Synchronous Slave Reception:
16.4.2
EUSART SYNCHRONOUS SLAVE
RECEPTION
1. Enable the synchronous master serial port by
setting bits SYNC and SPEN and clearing bit
CSRC.
The operation of the Synchronous Master and Slave
modes is identical, except in the case of Sleep, or any
Idle mode and bit SREN, which is a “don’t care” in
Slave mode.
2. If interrupts are desired, set enable bit RCIE.
3. If 9-bit reception is desired, set bit RX9.
4. To enable reception, set enable bit CREN.
If receive is enabled by setting the CREN bit prior to
entering Sleep or any Idle mode, then a word may be
received while in this low-power mode. Once the word
is received, the RSR register will transfer the data to the
RCREG register; if the RCIE enable bit is set, the inter-
rupt generated will wake the chip from the low-power
mode. If the global interrupt is enabled, the program will
branch to the interrupt vector.
5. Flag bit, RCIF, will be set when reception is
complete. An interrupt will be generated if
enable bit, RCIE, was set.
6. Read the RCSTA register to get the 9th bit (if
enabled) and determine if any error occurred
during reception.
7. Read the 8-bit received data by reading the
RCREG register.
8. If any error occurred, clear the error by clearing
bit CREN.
9. If using interrupts, ensure that the GIE and PEIE
bits in the INTCON register (INTCON<7:6>) are
set.
TABLE 16-10: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE RECEPTION
Reset
Values
on page
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
INTCON
PIR1
GIE/GIEH PEIE/GIEL TMR0IE
INT0IE
TXIF
RBIE
TMR0IF
CCP1IF
INT0IF
RBIF
43
45
45
45
45
45
45
45
45
45
PSPIF(1)
PSPIE(1)
PSPIP(1)
SPEN
ADIF
ADIE
ADIP
RX9
RCIF
RCIE
RCIP
SREN
SSP1IF
SSP1IE
SSP1IP
ADDEN
TMR2IF TMR1IF
PIE1
TXIE
CCP1IE TMR2IE TMR1IE
CCP1IP TMR2IP TMR1IP
IPR1
TXIP
RCSTA
RCREG
TXSTA
CREN
FERR
OERR
RX9D
EUSART Receive Register
CSRC
TX9
TXEN
—
SYNC
SCKP
SENDB
BRG16
BRGH
—
TRMT
WUE
TX9D
BAUDCON ABDOVF
RCIDL
ABDEN
SPBRGH
SPBRG
EUSART Baud Rate Generator Register High Byte
EUSART Baud Rate Generator Register Low Byte
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used for synchronous slave reception.
Note 1: These bits are not implemented on 28-pin devices and should be read as ‘0’.
© 2007 Microchip Technology Inc.
Preliminary
DS39682C-page 207
PIC18F45J10 FAMILY
NOTES:
DS39682C-page 208
Preliminary
© 2007 Microchip Technology Inc.
PIC18F45J10 FAMILY
The ADCON0 register, shown in Register 17-1,
controls the operation of the A/D module. The
ADCON1 register, shown in Register 17-2, configures
the functions of the port pins. The ADCON2 register,
shown in Register 17-3, configures the A/D clock
source, programmed acquisition time and justification.
17.0 10-BIT ANALOG-TO-DIGITAL
CONVERTER (A/D) MODULE
The Analog-to-Digital (A/D) converter module has
10 inputs for the 28-pin devices and 13 for the 40/44-pin
devices. This module allows conversion of an analog
input signal to a corresponding 10-bit digital number.
The module has five registers:
• A/D Result High Register (ADRESH)
• A/D Result Low Register (ADRESL)
• A/D Control Register 0 (ADCON0)
• A/D Control Register 1 (ADCON1)
• A/D Control Register 2 (ADCON2)
REGISTER 17-1: ADCON0: A/D CONTROL REGISTER 0
R/W-0
U-0
—
R/W-0
CHS3
R/W-0
CHS2
R/W-0
CHS1
R/W-0
CHS0
R/W-0
R/W-0
ADON
ADCAL
GO/DONE
bit 7
bit 0
bit 7
ADCAL: A/D Calibration bit
1= Calibration is performed on next A/D conversion
0= Normal A/D converter operation
bit 6
Unimplemented: Read as ‘0’
bit 5-2
CHS3:CHS0: Analog Channel Select bits
0000= Channel 0 (AN0)
0001= Channel 1 (AN1)
0010= Channel 2 (AN2)
0011= Channel 3 (AN3)
0100= Channel 4 (AN4)
0101= Channel 5 (AN5)(1,2)
0110= Channel 6 (AN6)(1,2)
0111= Channel 7 (AN7)(1,2)
1000= Channel 8 (AN8)
1001= Channel 9 (AN9)
1010= Channel 10 (AN10)
1011= Channel 11 (AN11)
1100= Channel 12 (AN12
1101= Unimplemented(2)
1110= Unimplemented(2)
1111= Unimplemented(2)
Note 1: These channels are not implemented on 28-pin devices.
2: Performing a conversion on unimplemented channels will return a floating input
measurement.
bit 1
bit 0
GO/DONE: A/D Conversion Status bit
When ADON = 1:
1= A/D conversion in progress
0= A/D Idle
ADON: A/D On bit
1= A/D converter module is enabled
0= A/D converter module is disabled
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
© 2007 Microchip Technology Inc.
Preliminary
DS39682C-page 209
PIC18F45J10 FAMILY
REGISTER 17-2: ADCON1: A/D CONTROL REGISTER 1
U-0
—
U-0
—
R/W-0
R/W-0
R/W-0(1)
PCFG3
R/W(1)
R/W(1)
R/W(1)
VCFG1
VCFG0
PCFG2
PCFG1
PCFG0
bit 7
bit 0
bit 7-6
bit 5
Unimplemented: Read as ‘0’
VCFG1: Voltage Reference Configuration bit (VREF- source)
1= VREF- (AN2)
0= VSS
bit 4
VCFG0: Voltage Reference Configuration bit (VREF+ source)
1= VREF+ (AN3)
0= VDD
bit 3-0
PCFG3:PCFG0: A/D Port Configuration Control bits:
PCFG3:
PCFG0
0000(1)
0001
0010
0011
0100
0101
0110
A
A
A
D
D
D
D
D
A
A
A
A
D
D
D
D
A
A
A
A
A
D
D
D
A
A
A
A
A
A
D
D
A
A
A
A
A
A
A
D
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
0111(1)
1000
1001
1010
1011
1100
1101
1110
1111
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
A
D
D
D
D
D
D
D
A
A
D
D
D
D
D
D
A
A
A
D
D
D
D
D
A
A
A
A
D
D
D
D
A
A
A
A
A
D
D
D
A
A
A
A
A
A
D
D
A
A
A
A
A
A
A
D
A = Analog input
D = Digital I/O
Note 1: The POR value of the PCFG bits depends on the value of the PBADEN con-
figuration bit. When PBADEN = 1, PCFG<3:0> = 0000; when PBADEN = 0,
PCFG<3:0> = 0111.
2: AN5 through AN7 are available only on 40/44-pin devices.
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
DS39682C-page 210
Preliminary
© 2007 Microchip Technology Inc.
PIC18F45J10 FAMILY
REGISTER 17-3: ADCON2: A/D CONTROL REGISTER 2
R/W-0
ADFM
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
ACQT2
ACQT1
ACQT0
ADCS2
ADCS1
ADCS0
bit 7
bit 0
bit 7
ADFM: A/D Result Format Select bit
1= Right justified
0= Left justified
bit 6
Unimplemented: Read as ‘0’
bit 5-3
ACQT2:ACQT0: A/D Acquisition Time Select bits
111= 20 TAD
110= 16 TAD
101= 12 TAD
100= 8 TAD
011= 6 TAD
010= 4 TAD
001= 2 TAD
(1)
000= 0 TAD
bit 2-0
ADCS2:ADCS0: A/D Conversion Clock Select bits
111= FRC (clock derived from A/D RC oscillator)(1)
110= FOSC/64
101= FOSC/16
100= FOSC/4
011= FRC (clock derived from A/D RC oscillator)(1)
010= FOSC/32
001= FOSC/8
000= FOSC/2
Note 1: If the A/D FRC clock source is selected, a delay of one TCY (instruction cycle) is
added before the A/D clock starts. This allows the SLEEPinstruction to be executed
before starting a conversion.
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
© 2007 Microchip Technology Inc.
Preliminary
DS39682C-page 211
PIC18F45J10 FAMILY
The analog reference voltage is software selectable to
either the device’s positive and negative supply voltage
(VDD and VSS), or the voltage level on the RA3/AN3/
VREF+ and RA2/AN2/VREF-/CVREF pins.
A device Reset forces all registers to their Reset state.
This forces the A/D module to be turned off and any
conversion in progress is aborted.
Each port pin associated with the A/D converter can be
configured as an analog input, or as a digital I/O. The
ADRESH and ADRESL registers contain the result of
the A/D conversion. When the A/D conversion is com-
plete, the result is loaded into the ADRESH:ADRESL
register pair, the GO/DONE bit (ADCON0 register) is
cleared and A/D Interrupt Flag bit, ADIF, is set. The block
diagram of the A/D module is shown in Figure 17-1.
The A/D converter has a unique feature of being able
to operate while the device is in Sleep mode. To oper-
ate in Sleep, the A/D conversion clock must be derived
from the A/D’s internal RC oscillator.
The output of the sample and hold is the input into the
converter, which generates the result via successive
approximation.
FIGURE 17-1:
A/D BLOCK DIAGRAM
CHS3:CHS0
1100
AN12
1011
AN11
1010
AN10
1001
AN9
1000
AN8
0111
AN7(1)
0110
AN6(1)
0101
AN5(1)
0100
AN4
VAIN
0011
(Input Voltage)
10-Bit
Converter
A/D
AN3
0010
AN2
0001
VCFG1:VCFG0
AN1
(2)
0000
VDD
AN0
X0
X1
1X
VREF+
VREF-
Reference
Voltage
0X
(2)
VSS
Note 1: Channels AN5 through AN7 are not available in 28-pin devices.
2: I/O pins have diode protection to VDD and VSS.
DS39682C-page 212
Preliminary
© 2007 Microchip Technology Inc.
PIC18F45J10 FAMILY
The value in the ADRESH:ADRESL registers is not
modified for a Power-on Reset. The ADRESH:ADRESL
registers will contain unknown data after a Power-on
Reset.
5. Wait for A/D conversion to complete, by either:
• Polling for the GO/DONE bit to be cleared
OR
• Waiting for the A/D interrupt
After the A/D module has been configured as desired,
the selected channel must be acquired before the
conversion is started. The analog input channels must
have their corresponding TRIS bits selected as an
input. To determine acquisition time, see Section 17.1
“A/D Acquisition Requirements”. After this acquisi-
tion time has elapsed, the A/D conversion can be
started. An acquisition time can be programmed to
occur between setting the GO/DONE bit and the actual
start of the conversion.
6. Read A/D Result registers (ADRESH:ADRESL);
clear bit ADIF, if required.
7. For next conversion, go to step 1 or step 2, as
required. The A/D conversion time per bit is
defined as TAD. A minimum wait of 2 TAD is
required before the next acquisition starts.
FIGURE 17-2:
A/D TRANSFER FUNCTION
The following steps should be followed to perform an A/D
conversion:
3FFh
3FEh
1. Configure the A/D module:
• Configure analog pins, voltage reference and
digital I/O (ADCON1)
• Select A/D input channel (ADCON0)
• Select A/D acquisition time (ADCON2)
• Select A/D conversion clock (ADCON2)
• Turn on A/D module (ADCON0)
2. Configure A/D interrupt (if desired):
• Clear ADIF bit
003h
002h
001h
000h
• Set ADIE bit
• Set GIE bit
3. Wait the required acquisition time (if required).
4. Start conversion:
Analog Input Voltage
• Set GO/DONE bit (ADCON0 register)
FIGURE 17-3:
ANALOG INPUT MODEL
VDD
Sampling
Switch
VT = 0.6V
ANx
SS
RIC ≤ 1k
RSS
Rs
CPIN
VAIN
ILEAKAGE
± 100 nA
CHOLD = 25 pF
VT = 0.6V
5 pF
VSS
Legend: CPIN
= Input Capacitance
= Threshold Voltage
VT
6 V
5 V
4 V
3 V
2 V
ILEAKAGE = Leakage Current at the pin due to
various junctions
VDD
RIC
= Interconnect Resistance
SS
= Sampling Switch
CHOLD
RSS
= Sample/Hold Capacitance (from DAC)
= Sampling Switch Resistance
1
2
3
4
(kΩ)
Sampling Switch
© 2007 Microchip Technology Inc.
Preliminary
DS39682C-page 213
PIC18F45J10 FAMILY
To calculate the minimum acquisition time,
Equation 17-1 may be used. This equation assumes
that 1/2 LSb error is used (1024 steps for the A/D). The
1/2 LSb error is the maximum error allowed for the A/D
to meet its specified resolution.
17.1 A/D Acquisition Requirements
For the A/D converter to meet its specified accuracy,
the charge holding capacitor (CHOLD) must be allowed
to fully charge to the input channel voltage level. The
analog input model is shown in Figure 17-3. The
source impedance (RS) and the internal sampling
switch (RSS) impedance directly affect the time
required to charge the capacitor CHOLD. The sampling
switch (RSS) impedance varies over the device voltage
(VDD). The source impedance affects the offset voltage
at the analog input (due to pin leakage current). The
maximum recommended impedance for analog
sources is 2.5 kΩ. After the analog input channel is
selected (changed), the channel must be sampled for
at least the minimum acquisition time before starting a
conversion.
Example 17-3 shows the calculation of the minimum
required acquisition time TACQ. This calculation is
based on the following application system
assumptions:
CHOLD
Rs
Conversion Error
VDD
Temperature
=
=
≤
=
=
25 pF
2.5 kΩ
1/2 LSb
5V → Rss = 2 kΩ
85°C (system max.)
Note:
When the conversion is started, the
holding capacitor is disconnected from the
input pin.
EQUATION 17-1: ACQUISITION TIME
TACQ
=
=
Amplifier Settling Time + Holding Capacitor Charging Time + Temperature Coefficient
TAMP + TC + TCOFF
EQUATION 17-2: A/D MINIMUM CHARGING TIME
VHOLD
or
TC
=
=
(VREF – (VREF/2048)) • (1 – e(-TC/CHOLD(RIC + RSS + RS))
)
-(CHOLD)(RIC + RSS + RS) ln(1/2048)
EQUATION 17-3: CALCULATING THE MINIMUM REQUIRED ACQUISITION TIME
TACQ
TAMP
TCOFF
=
=
=
TAMP + TC + TCOFF
0.2 μs
(Temp – 25°C)(0.02 μs/°C)
(85°C – 25°C)(0.02 μs/°C)
1.2 μs
Temperature coefficient is only required for temperatures > 25°C. Below 25°C, TCOFF = 0 ms.
TC
=
-(CHOLD)(RIC + RSS + RS) ln(1/2047) μs
-(25 pF) (1 kΩ + 2 kΩ + 2.5 kΩ) ln(0.0004883) μs
1.05 μs
TACQ
=
0.2 μs + 1 μs + 1.2 μs
2.4 μs
DS39682C-page 214
Preliminary
© 2007 Microchip Technology Inc.
PIC18F45J10 FAMILY
17.2 Selecting and Configuring
Acquisition Time
17.3 Selecting the A/D Conversion
Clock
The ADCON2 register allows the user to select an
acquisition time that occurs each time the GO/DONE
bit is set. It also gives users the option to use an
automatically determined acquisition time.
The A/D conversion time per bit is defined as TAD. The
A/D conversion requires 11 TAD per 10-bit conversion.
The source of the A/D conversion clock is software
selectable. There are seven possible options for TAD:
Acquisition time may be set with the ACQT2:ACQT0
bits (ADCON2<5:3>), which provides a range of 2 to
20 TAD. When the GO/DONE bit is set, the A/D module
continues to sample the input for the selected acquisi-
tion time, then automatically begins a conversion.
Since the acquisition time is programmed, there may
be no need to wait for an acquisition time between
selecting a channel and setting the GO/DONE bit.
• 2 TOSC
• 4 TOSC
• 8 TOSC
• 16 TOSC
• 32 TOSC
• 64 TOSC
• Internal RC Oscillator
Manual
acquisition
is
selected
when
For correct A/D conversions, the A/D conversion clock
(TAD) must be as short as possible, but greater than the
minimum TAD (see parameter 130 for more
information).
ACQT2:ACQT0 = 000. When the GO/DONE bit is set,
sampling is stopped and a conversion begins. The user
is responsible for ensuring the required acquisition time
has passed between selecting the desired input
channel and setting the GO/DONE bit. This option is
also the default Reset state of the ACQT2:ACQT0 bits
and is compatible with devices that do not offer
programmable acquisition times.
Table 17-1 shows the resultant TAD times derived from
the device operating frequencies and the A/D clock
source selected.
In either case, when the conversion is completed, the
GO/DONE bit is cleared, the ADIF flag is set and the
A/D begins sampling the currently selected channel
again. If an acquisition time is programmed, there is
nothing to indicate if the acquisition time has ended or
if the conversion has begun.
TABLE 17-1: TAD vs. DEVICE OPERATING FREQUENCIES
AD Clock Source (TAD)
Maximum Device Frequency
Operation
ADCS2:ADCS0
PIC18F2X1X/4X1X
PIC18LF2XJ10/4XJ10(4)
2 TOSC
4 TOSC
8 TOSC
16 TOSC
32 TOSC
64 TOSC
RC(3)
000
100
001
101
010
110
x11
2.86 MHz
5.71 MHz
11.43 MHz
22.86 MHz
40.0 MHz
40.0 MHz
1.00 MHz(1)
1.43 MHz
2.86 MHz
5.72 MHz
11.43 MHz
22.86 MHz
40.0 MHz
1.00 MHz(2)
Note 1: The RC source has a typical TAD time of 1.2 μs.
2: The RC source has a typical TAD time of 2.5 μs.
3: For device frequencies above 1 MHz, the device must be in Sleep for the entire conversion or the A/D
accuracy may be out of specification.
4: Low-power (PIC18LF2XJ10/4XJ10) devices only.
© 2007 Microchip Technology Inc.
Preliminary
DS39682C-page 215
PIC18F45J10 FAMILY
17.4 Operation in Power-Managed
Modes
17.6 Configuring Analog Port Pins
The ADCON1, TRISA, TRISB and TRISE registers all
configure the A/D port pins. The port pins needed as
analog inputs must have their corresponding TRIS bits
set (input). If the TRIS bit is cleared (output), the digital
output level (VOH or VOL) will be converted.
The selection of the automatic acquisition time and A/D
conversion clock is determined in part by the clock
source and frequency while in a power-managed mode.
If the A/D is expected to operate while the device is in
a power-managed mode, the ACQT2:ACQT0 and
ADCS2:ADCS0 bits in ADCON2 should be updated in
accordance with the clock source to be used in that
mode. After entering the mode, an A/D acquisition or
conversion may be started. Once started, the device
should continue to be clocked by the same clock
source until the conversion has been completed.
The A/D operation is independent of the state of the
CHS3:CHS0 bits and the TRIS bits.
Note 1: When reading the Port register, all pins
configured as analog input channels will
read as cleared (a low level). Pins con-
figured as digital inputs will convert as
analog inputs. Analog levels on a digitally
configured input will be accurately
converted.
If desired, the device may be placed into the
corresponding Idle mode during the conversion. If the
device clock frequency is less than 1 MHz, the A/D RC
clock source should be selected.
2: Analog levels on any pin defined as a dig-
ital input may cause the digital input buffer
to consume current out of the device’s
specification limits.
Operation in the Sleep mode requires the A/D FRC
clock to be selected. If bits ACQT2:ACQT0 are set to
‘000’ and a conversion is started, the conversion will be
delayed one instruction cycle to allow execution of the
SLEEPinstruction and entry to Sleep mode. The IDLEN
bit (OSCCON<7>) must have already been cleared
prior to starting the conversion.
3: The PBADEN bit in Configuration
Register 3H configures PORTB pins to
reset as analog or digital pins by control-
ling how the PCFG0 bits in ADCON1 are
reset.
17.5 A/D Converter Calibration
The A/D converter in the PIC18F45J10 family of
devices includes a self-calibration feature which com-
pensates for any offset generated within the module.
The calibration process is automated and is initiated by
setting the ADCAL bit (ADCON0<7>). The next time
the GO/DONE bit is set, the module will perform a
“dummy” conversion (that is, with reading none of the
input channels) and store the resulting value internally
to compensate for offset. Thus, subsequent offsets will
be compensated.
The calibration process assumes that the device is in a
relatively steady-state operating condition. If A/D
calibration is used, it should be performed after each
device Reset, or if there are other major changes in
operating conditions.
DS39682C-page 216
Preliminary
© 2007 Microchip Technology Inc.
PIC18F45J10 FAMILY
Clearing the GO/DONE bit during a conversion will abort
the current conversion. The A/D Result register pair will
NOT be updated with the partially completed A/D
conversion sample. This means the ADRESH:ADRESL
registers will continue to contain the value of the last
completed conversion (or the last value written to the
ADRESH:ADRESL registers).
17.7 A/D Conversions
Figure 17-4 shows the operation of the A/D converter
after the GO/DONE bit has been set and the
ACQT2:ACQT0 bits are cleared. A conversion is
started after the following instruction to allow entry into
Sleep mode before the conversion begins.
Figure 17-5 shows the operation of the A/D converter
after the GO/DONE bit has been set and the
ACQT2:ACQT0 bits are set to ‘010’ and selecting a 4
TAD acquisition time before the conversion starts.
After the A/D conversion is completed or aborted, a
2 TAD wait is required before the next acquisition can
be started. After this wait, acquisition on the selected
channel is automatically started.
Note:
The GO/DONE bit should NOT be set in
the same instruction that turns on the A/D.
FIGURE 17-4:
A/D CONVERSION TAD CYCLES (ACQT<2:0> = 000, TACQ = 0)
TCY - TAD
TAD7 TAD8 TAD9 TAD10 TAD11
TAD1
TAD1 TAD2 TAD3 TAD4 TAD5 TAD6
b7
b6
b4
b1
b0
b2
b9
b8
b5
b3
Conversion starts
Discharge
Holding capacitor is disconnected from analog input (typically 100 ns)
Set GO/DONE bit
On the following cycle:
ADRESH:ADRESL is loaded, GO/DONE bit is cleared,
ADIF bit is set, holding capacitor is connected to analog input.
FIGURE 17-5:
A/D CONVERSION TAD CYCLES (ACQT<2:0> = 010, TACQ = 4 TAD)
TAD Cycles
TACQT Cycles
1
2
3
4
1
2
3
4
5
6
7
8
9
10
b1
11 TAD1
b0
b7
b6
b3
b2
b8
b5
b4
b9
Automatic
Acquisition
Time
Discharge
Conversion starts
(Holding capacitor is disconnected)
Set GO/DONE bit
(Holding capacitor continues
acquiring input)
On the following cycle:
ADRESH:ADRESL is loaded, GO/DONE bit is cleared,
ADIF bit is set, holding capacitor is connected to analog input.
© 2007 Microchip Technology Inc.
Preliminary
DS39682C-page 217
PIC18F45J10 FAMILY
(moving ADRESH:ADRESL to the desired location).
The appropriate analog input channel must be selected
and the minimum acquisition period is either timed by
the user, or an appropriate TACQ time selected before
the Special Event Trigger sets the GO/DONE bit (starts
a conversion).
17.8 Use of the CCP2 Trigger
An A/D conversion can be started by the Special Event
Trigger of the CCP2 module. This requires that the
CCP2M3:CCP2M0
bits
(CCP2CON<3:0>)
be
programmed as ‘1011’ and that the A/D module is
enabled (ADON bit is set). When the trigger occurs, the
GO/DONE bit will be set, starting the A/D acquisition
and conversion and the Timer1 counter will be reset to
zero. Timer1 is reset to automatically repeat the A/D
acquisition period with minimal software overhead
If the A/D module is not enabled (ADON is cleared), the
Special Event Trigger will be ignored by the A/D
module, but will still reset the Timer1 counter.
TABLE 17-2: REGISTERS ASSOCIATED WITH A/D OPERATION
Reset
Values
on page
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
INTCON
PIR1
PIE1
GIE/GIEH PEIE/GIEL TMR0IE
INT0IE
TXIF
TXIE
TXIP
—
RBIE
TMR0IF
CCP1IF
CCP1IE
CCP1IP
—
INT0IF
TMR2IF
TMR2IE
TMR2IP
—
RBIF
43
45
45
45
45
45
45
44
44
44
44
44
46
46
46
46
46
46
46
46
PSPIF(1)
PSPIE(1)
PSPIP(1)
OSCFIF
OSCFIE
OSCFIP
ADIF
ADIE
ADIP
CMIF
CMIE
CMIP
RCIF
RCIE
RCIP
—
SSP1IF
SSP1IE
SSP1IP
BCL1IF
BCL1IE
BCL1IP
TMR1IF
TMR1IE
TMR1IP
CCP2IF
CCP2IE
CCP2IP
IPR1
PIR2
PIE2
—
—
—
—
IPR2
—
—
—
—
ADRESH A/D Result Register High Byte
ADRESL A/D Result Register Low Byte
ADCON0
ADCON1
ADCON2
PORTA
TRISA
ADCAL
—
—
—
CHS3
VCFG1
ACQT2
RA5
CHS2
VCFG0
ACQT1
—
CHS1
PCFG3
ACQT0
RA3
CHS0 GO/DONE ADON
PCFG2
ADCS2
RA2
PCFG1
ADCS1
RA1
PCFG0
ADCS0
RA0
ADFM
—
—
—
—
—
TRISA5
RB5
—
TRISA3
RB3
TRISA2
RB2
TRISA1
RB1
TRISA0
RB0
PORTB
TRISB
RB7
RB6
RB4
PORTB Data Direction Control Register
PORTB Data Latch Register (Read and Write to Data Latch)
LATB
PORTE(1)
TRISE(1)
LATE(1)
—
IBF
—
—
OBF
—
—
IBOV
—
—
PSPMODE
—
—
—
—
RE2
RE1
RE0
TRISE2
TRISE1
TRISE0
PORTE Data Latch Register
(Read and Write to Data Latch)
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used for A/D conversion.
Note 1: These registers and/or bits are not implemented on 28-pin devices and should be read as ‘0’.
DS39682C-page 218
Preliminary
© 2007 Microchip Technology Inc.
PIC18F45J10 FAMILY
The CMCON register (Register 18-1) selects the
comparator input and output configuration. Block
diagrams of the various comparator configurations are
shown in Figure 18-1.
18.0 COMPARATOR MODULE
The analog comparator module contains two
comparators that can be configured in a variety of
ways. The inputs can be selected from the analog
inputs multiplexed with pins RA0 through RA5, as well
as the on-chip voltage reference (see Section 19.0
“Comparator Voltage Reference Module”). The digi-
tal outputs (normal or inverted) are available at the pin
level and can also be read through the control register.
REGISTER 18-1: CMCON: COMPARATOR CONTROL REGISTER
R-0
R-0
R/W-0
C2INV
R/W-0
C1INV
R/W-0
CIS
R/W-1
CM2
R/W-1
CM1
R/W-1
CM0
C2OUT
C1OUT
bit 7
bit 0
bit 7
C2OUT: Comparator 2 Output bit
When C2INV = 0:
1= C2 VIN+ > C2 VIN-
0= C2 VIN+ < C2 VIN-
When C2INV = 1:
1= C2 VIN+ < C2 VIN-
0= C2 VIN+ > C2 VIN-
bit 6
C1OUT: Comparator 1 Output bit
When C1INV = 0:
1= C1 VIN+ > C1 VIN-
0= C1 VIN+ < C1 VIN-
When C1INV = 1:
1= C1 VIN+ < C1 VIN-
0= C1 VIN+ > C1 VIN-
bit 5
bit 4
bit 3
C2INV: Comparator 2 Output Inversion bit
1= C2 output inverted
0= C2 output not inverted
C1INV: Comparator 1 Output Inversion bit
1= C1 output inverted
0= C1 output not inverted
CIS: Comparator Input Switch bit
When CM2:CM0 = 110:
1= C1 VIN- connects to RA3/AN3/VREF+
C2 VIN- connects to RA2/AN2/VREF-/CVREF
0= C1 VIN- connects to RA0/AN0
C2 VIN- connects to RA1/AN1
bit 2-0
CM2:CM0: Comparator Mode bits
Figure 18-1 shows the Comparator modes and the CM2:CM0 bit settings.
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
© 2007 Microchip Technology Inc.
Preliminary
DS39682C-page 219
PIC18F45J10 FAMILY
changed, the comparator output level may not be valid
for the specified mode change delay shown in
Section 23.0 “Electrical Characteristics”.
18.1 Comparator Configuration
There are eight modes of operation for the compara-
tors, shown in Figure 18-1. Bits CM2:CM0 of the
CMCON register are used to select these modes. The
TRISA register controls the data direction of the com-
parator pins for each mode. If the Comparator mode is
Note:
Comparator interrupts should be disabled
during Comparator mode change;
otherwise, a false interrupt may occur.
a
FIGURE 18-1:
COMPARATOR I/O OPERATING MODES
Comparators Reset
Comparators Off (POR Default Value)
CM2:CM0 = 000
CM2:CM0 = 111
A
D
VIN-
VIN-
RA0/AN0
RA0/AN0
Off (Read as ‘0’)
Off (Read as ‘0’)
Off (Read as ‘0’)
Off (Read as ‘0’)
C1
C2
C1
C2
VIN+
VIN+
A
D
RA3/AN3/
VREF+
RA3/AN3/
VREF+
A
D
VIN-
VIN-
RA1/AN1
RA1/AN1
VIN+
VIN+
A
D
RA2/AN2/
VREF-/CVREF
RA2/AN2/
VREF-/CVREF
Two Independent Comparators
Two Independent Comparators with Outputs
CM2:CM0 = 010
CM2:CM0 = 011
A
A
VIN-
VIN-
RA0/AN0
RA0/AN0
C1OUT
C2OUT
C1OUT
C2OUT
C1
C2
C1
C2
VIN+
VIN+
A
A
RA3/AN3/
VREF+
RA3/AN3/
VREF+
RB5/KBI1/
T0CKI/C1OUT*
A
A
VIN-
RA1/AN1
RA2/AN2/
A
VIN-
RA1/AN1
VIN+
VIN+
A
RA2/AN2/
VREF-/CVREF
VREF-/CVREF
RA5/AN4/SS1/C2OUT*
Two Common Reference Comparators
Two Common Reference Comparators with Outputs
CM2:CM0 = 100
CM2:CM0 = 101
A
A
VIN-
VIN-
RA0/AN0
RA0/AN0
C1OUT
C2OUT
C1OUT
C2OUT
C1
C2
C1
C2
VIN+
VIN+
A
A
RA3/AN3/
VREF+
RA3/AN3/
VREF+
RB5/KBI1/
T0CKI/C1OUT*
A
D
VIN-
RA1/AN1
RA2/AN2/
A
VIN-
RA1/AN1
VIN+
VIN+
D
RA2/AN2/
VREF-/CVREF
VREF-/CVREF
RA5/AN4/SS1/C2OUT*
Four Inputs Multiplexed to Two Comparators
One Independent Comparator with Output
CM2:CM0 = 110
CM2:CM0 = 001
A
A
A
VIN-
RA0/AN0
RA0/AN0
CIS = 0
CIS = 1
VIN-
A
C1OUT
C1
C2
VIN+
RA3/AN3/
VREF+
RA3/AN3/
VREF+
C1OUT
C2OUT
C1
C2
VIN+
A
A
RB5/KBI1/T0CKI/C1OUT*
RA1/AN1
RA2/AN2/
VIN-
CIS = 0
CIS = 1
D
D
VIN-
VIN+
RA1/AN1
RA2/AN2/
VREF-/CVREF/
Off (Read as ‘0’)
VIN+
CVREF
VREF-/CVREF/
From VREF Module
A = Analog Input, port reads zeros always
D = Digital Input
CIS (CMCON<3>) is the Comparator Input Switch
* Setting the TRISA<5> bit will disable the comparator outputs by configuring the pins as inputs.
DS39682C-page 220
Preliminary
© 2007 Microchip Technology Inc.
PIC18F45J10 FAMILY
18.3.2
INTERNAL REFERENCE SIGNAL
18.2 Comparator Operation
The comparator module also allows the selection of an
internally generated voltage reference from the
comparator voltage reference module. This module is
described in more detail in Section 19.0 “Comparator
Voltage Reference Module”.
A single comparator is shown in Figure 18-2, along with
the relationship between the analog input levels and
the digital output. When the analog input at VIN+ is less
than the analog input VIN-, the output of the comparator
is a digital low level. When the analog input at VIN+ is
greater than the analog input VIN-, the output of the
comparator is a digital high level. The shaded areas of
the output of the comparator in Figure 18-2 represent
the uncertainty, due to input offsets and response time.
The internal reference is only available in the mode
where four inputs are multiplexed to two comparators
(CM2:CM0 = 110). In this mode, the internal voltage
reference is applied to the VIN+ pin of both
comparators.
18.3 Comparator Reference
18.4 Comparator Response Time
Depending on the comparator operating mode, either
an external or internal voltage reference may be used.
The analog signal present at VIN- is compared to the
signal at VIN+ and the digital output of the comparator
is adjusted accordingly (Figure 18-2).
Response time is the minimum time, after selecting a
new reference voltage or input source, before the
comparator output has a valid level. If the internal ref-
erence is changed, the maximum delay of the internal
voltage reference must be considered when using the
comparator outputs. Otherwise, the maximum delay of
the comparators should be used (see Section 23.0
“Electrical Characteristics”).
FIGURE 18-2:
SINGLE COMPARATOR
VIN+
VIN-
+
18.5 Comparator Outputs
Output
–
The comparator outputs are read through the CMCON
register. These bits are read-only. The comparator
outputs may also be directly output to the RB5 and RA5
I/O pins. When enabled, multiplexors in the output path
of the RB5 and RA5 pins will switch and the output of
each pin will be the unsynchronized output of the
comparator. The uncertainty of each of the
comparators is related to the input offset voltage and
the response time given in the specifications.
Figure 18-3 shows the comparator output block
diagram.
VIN-
VIN+
Output
The TRISA bits will still function as an output enable/
disable for the RB5 and RA5 pins while in this mode.
The polarity of the comparator outputs can be changed
using the C2INV and C1INV bits (CMCON<5:4>).
18.3.1
EXTERNAL REFERENCE SIGNAL
Note 1: When reading the Port register, all pins
configured as analog inputs will read as a
‘0’. Pins configured as digital inputs will
convert an analog input according to the
Schmitt Trigger input specification.
When external voltage references are used, the
comparator module can be configured to have the com-
parators operate from the same or different reference
sources. However, threshold detector applications may
require the same reference. The reference signal must
be between VSS and VDD and can be applied to either
pin of the comparator(s).
2: Analog levels on any pin defined as a
digital input may cause the input buffer to
consume more current than is specified.
© 2007 Microchip Technology Inc.
Preliminary
DS39682C-page 221
PIC18F45J10 FAMILY
FIGURE 18-3:
COMPARATOR OUTPUT BLOCK DIAGRAM
Port pins
To RB5 or
RA5 pin
D
Q
Bus
Data
CxINV
EN
Read CMCON
D
Q
Set
CMIF
bit
EN
CL
From
other
Comparator
Reset
18.6 Comparator Interrupts
18.7 Comparator Operation
During Sleep
The comparator interrupt flag is set whenever there is
a change in the output value of either comparator.
Software will need to maintain information about the
status of the output bits, as read from CMCON<7:6>, to
determine the actual change that occurred. The CMIF
bit (PIR2<6>) is the Comparator Interrupt Flag. The
CMIF bit must be reset by clearing it. Since it is also
possible to write a ‘1’ to this register, a simulated
interrupt may be initiated.
When a comparator is active and the device is placed
in Sleep mode, the comparator remains active and the
interrupt is functional if enabled. This interrupt will
wake-up the device from Sleep mode, when enabled.
Each operational comparator will consume additional
current, as shown in the comparator specifications. To
minimize power consumption while in Sleep mode, turn
off the comparators (CM2:CM0 = 111) before entering
Sleep. If the device wakes up from Sleep, the contents
of the CMCON register are not affected.
Both the CMIE bit (PIE2<6>) and the PEIE bit
(INTCON<6>) must be set to enable the interrupt. In
addition, the GIE bit (INTCON<7>) must also be set. If
any of these bits are clear, the interrupt is not enabled,
though the CMIF bit will still be set if an interrupt
condition occurs.
18.8 Effects of a Reset
A device Reset forces the CMCON register to its Reset
state, causing the comparator modules to be turned off
(CM2:CM0 = 111). However, the input pins (RA0
through RA3) are configured as analog inputs by
default on device Reset. The I/O configuration for these
pins is determined by the setting of the PCFG3:PCFG0
bits (ADCON1<3:0>). Therefore, device current is
minimized when analog inputs are present at Reset
time.
Note:
If a change in the CMCON register
(C1OUT or C2OUT) should occur when a
read operation is being executed (start of
the Q2 cycle), then the CMIF (PIR2
register) interrupt flag may not get set.
The user, in the Interrupt Service Routine, can clear the
interrupt in the following manner:
a) Any read or write of CMCON will end the
mismatch condition.
b) Clear flag bit CMIF.
A mismatch condition will continue to set flag bit CMIF.
Reading CMCON will end the mismatch condition and
allow flag bit CMIF to be cleared.
DS39682C-page 222
Preliminary
© 2007 Microchip Technology Inc.
PIC18F45J10 FAMILY
range by more than 0.6V in either direction, one of the
diodes is forward biased and a latch-up condition may
occur. A maximum source impedance of 10 kΩ is
recommended for the analog sources. Any external
component connected to an analog input pin, such as
a capacitor or a Zener diode, should have very little
leakage current.
18.9 Analog Input Connection
Considerations
A simplified circuit for an analog input is shown in
Figure 18-4. Since the analog pins are connected to a
digital output, they have reverse biased diodes to VDD
and VSS. The analog input, therefore, must be between
VSS and VDD. If the input voltage deviates from this
FIGURE 18-4:
COMPARATOR ANALOG INPUT MODEL
VDD
VT = 0.6V
RIC
RS < 10k
AIN
Comparator
Input
ILEAKAGE
±500 nA
CPIN
5 pF
VA
VT = 0.6V
VSS
Legend: CPIN
=
=
Input Capacitance
Threshold Voltage
VT
ILEAKAGE = Leakage Current at the pin due to various junctions
RIC
RS
VA
=
=
=
Interconnect Resistance
Source Impedance
Analog Voltage
TABLE 18-1: REGISTERS ASSOCIATED WITH COMPARATOR MODULE
Reset
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Values
on page
CMCON
CVRCON
INTCON
PIR2
C2OUT
CVREN
C1OUT
CVROE
C2INV
CVRR
C1INV
CVRSS
INT0IE
—
CIS
CM2
CVR2
TMR0IF
—
CM1
CVR1
INT0IF
—
CM0
CVR0
RBIF
45
45
46
45
45
45
46
46
46
CVR3
RBIE
GIE/GIEH PEIE/GIEL TMR0IE
OSCFIF
OSCFIE
OSCFIP
—
CMIF
CMIE
CMIP
—
—
—
BCL1IF
BCL1IE
BCL1IP
RA3
CCP2IF
CCP2IE
CCP2IP
RA0
PIE2
—
—
—
IPR2
—
—
—
—
PORTA
LATA
RA5
—
RA2
RA1
—
—
PORTA Data Latch Register (Read and Write to Data Latch)
TRISA5 TRISA3 TRISA2 TRISA1 TRISA0
TRISA
—
—
—
Legend: — = unimplemented, read as ‘0’. Shaded cells are unused by the comparator module.
© 2007 Microchip Technology Inc.
Preliminary
DS39682C-page 223
PIC18F45J10 FAMILY
NOTES:
DS39682C-page 224
Preliminary
© 2007 Microchip Technology Inc.
PIC18F45J10 FAMILY
used is selected by the CVRR bit (CVRCON<5>). The
primary difference between the ranges is the size of the
steps selected by the CVREF Selection bits
(CVR3:CVR0), with one range offering finer resolution.
The equations used to calculate the output of the
comparator voltage reference are as follows:
19.0 COMPARATOR VOLTAGE
REFERENCE MODULE
The comparator voltage reference is a 16-tap resistor
ladder network that provides a selectable reference
voltage. Although its primary purpose is to provide a
reference for the analog comparators, it may also be
used independently of them.
If CVRR = 1:
CVREF = ((CVR3:CVR0)/24) x CVRSRC
A block diagram of the module is shown in Figure 19-1.
The resistor ladder is segmented to provide two ranges
of CVREF values and has a power-down function to
conserve power when the reference is not being used.
The module’s supply reference can be provided from
either device VDD/VSS or an external voltage reference.
If CVRR = 0:
CVREF = (CVRSRC x 1/4) + (((CVR3:CVR0)/32) x
CVRSRC)
The comparator reference supply voltage can come
from either VDD and VSS, or the external VREF+ and
VREF- that are multiplexed with RA2 and RA3. The
voltage source is selected by the CVRSS bit
(CVRCON<4>).
19.1 Configuring the Comparator
Voltage Reference
The settling time of the comparator voltage reference
must be considered when changing the CVREF
output (see Table 23-3 in Section 23.0 “Electrical
Characteristics”).
The voltage reference module is controlled through the
CVRCON register (Register 19-1). The comparator
voltage reference provides two ranges of output
voltage, each with 16 distinct levels. The range to be
REGISTER 19-1: CVRCON: COMPARATOR VOLTAGE REFERENCE CONTROL REGISTER
R/W-0
CVREN CVROE(1)
bit 7
R/W-0
R/W-0
CVRR
R/W-0
R/W-0
CVR3
R/W-0
CVR2
R/W-0
CVR1
R/W-0
CVR0
CVRSS
bit 0
bit 7
bit 6
CVREN: Comparator Voltage Reference Enable bit
1= CVREF circuit powered on
0= CVREF circuit powered down
CVROE: Comparator VREF Output Enable bit(1)
1= CVREF voltage level is also output on the RA2/AN2/VREF-/CVREF pin
0= CVREF voltage is disconnected from the RA2/AN2/VREF-/CVREF pin
Note 1: CVROE overrides the TRISA<2> bit setting.
bit 5
CVRR: Comparator VREF Range Selection bit
1= 0 to 0.667 CVRSRC, with CVRSRC/24 step size (low range)
0= 0.25 CVRSRC to 0.75 CVRSRC, with CVRSRC/32 step size (high range)
bit 4
CVRSS: Comparator VREF Source Selection bit
1= Comparator reference source, CVRSRC = (VREF+) – (VREF-)
0= Comparator reference source, CVRSRC = VDD – VSS
bit 3-0
CVR3:CVR0: Comparator VREF Value Selection bits (0 ≤ (CVR3:CVR0) ≤ 15)
When CVRR = 1:
CVREF = ((CVR3:CVR0)/24) • (CVRSRC)
When CVRR = 0:
CVREF = (CVRSRC/4) + ((CVR3:CVR0)/32) • (CVRSRC)
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
© 2007 Microchip Technology Inc.
Preliminary
DS39682C-page 225
PIC18F45J10 FAMILY
FIGURE 19-1:
COMPARATOR VOLTAGE REFERENCE BLOCK DIAGRAM
CVRSS = 1
CVRSS = 0
VREF+
VDD
8R
CVR3:CVR0
R
CVREN
R
R
R
16 Steps
CVREF
R
R
R
CVRR
VREF-
8R
CVRSS = 1
CVRSS = 0
19.2 Voltage Reference Accuracy/Error
19.4 Effects of a Reset
The full range of voltage reference cannot be realized
due to the construction of the module. The transistors
on the top and bottom of the resistor ladder network
(Figure 19-1) keep CVREF from approaching the refer-
ence source rails. The voltage reference is derived
from the reference source; therefore, the CVREF output
changes with fluctuations in that source. The tested
absolute accuracy of the voltage reference can be
found in Section 23.0 “Electrical Characteristics”.
A device Reset disables the voltage reference by
clearing bit, CVREN (CVRCON<7>). This Reset also
disconnects the reference from the RA2 pin by clearing
bit, CVROE (CVRCON<6>) and selects the high-voltage
range by clearing bit, CVRR (CVRCON<5>). The CVR
value select bits are also cleared.
19.5 Connection Considerations
The voltage reference module operates independently
of the comparator module. The output of the reference
generator may be connected to the RA2 pin if the
CVROE bit is set. Enabling the voltage reference out-
put onto RA2 when it is configured as a digital input will
increase current consumption. Connecting RA2 as a
digital output with CVRSS enabled will also increase
current consumption.
19.3 Operation During Sleep
When the device wakes up from Sleep through an
interrupt or a Watchdog Timer time-out, the contents of
the CVRCON register are not affected. To minimize
current consumption in Sleep mode, the voltage
reference should be disabled.
The RA2 pin can be used as a simple D/A output with
limited drive capability. Due to the limited current drive
capability, a buffer must be used on the voltage
reference output for external connections to VREF.
Figure 19-2 shows an example buffering technique.
DS39682C-page 226
Preliminary
© 2007 Microchip Technology Inc.
PIC18F45J10 FAMILY
FIGURE 19-2:
COMPARATOR VOLTAGE REFERENCE OUTPUT BUFFER EXAMPLE
PIC18F45J10
CVREF
Module
(1)
R
+
–
CVREF Output
RA2
Voltage
Reference
Output
Impedance
Note 1: R is dependent upon the voltage reference configuration bits, CVRCON<3:0> and CVRCON<5>.
TABLE 19-1: REGISTERS ASSOCIATED WITH COMPARATOR VOLTAGE REFERENCE
Reset
Values
on page
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
CVRCON
CMCON
TRISA
CVREN
C2OUT
—
CVROE
C1OUT
—
CVRR
C2INV
TRISA5
CVRSS
C1INV
—
CVR3
CIS
CVR2
CM2
CVR1
CM1
CVR0
CM0
45
45
46
TRISA3
TRISA2
TRISA1
TRISA0
Legend: Shaded cells are not used with the comparator voltage reference.
© 2007 Microchip Technology Inc.
Preliminary
DS39682C-page 227
PIC18F45J10 FAMILY
NOTES:
DS39682C-page 228
Preliminary
© 2007 Microchip Technology Inc.
PIC18F45J10 FAMILY
20.1.1
CONSIDERATIONS FOR
CONFIGURING THE PIC18F45J10
FAMILY DEVICES
20.0 SPECIAL FEATURES OF THE
CPU
PIC18F45J10 family devices include several features
intended to maximize reliability and minimize cost
through elimination of external components. These are:
Unlike most PIC18 microcontrollers, devices of the
PIC18F45J10 family do not use persistent memory
registers to store configuration information. The config-
uration bytes are implemented as volatile memory
which means that configuration data must be
programmed each time the device is powered up.
• Oscillator Selection
• Resets:
- Power-on Reset (POR)
- Power-up Timer (PWRT)
- Oscillator Start-up Timer (OST)
- Brown-out Reset (BOR)
• Interrupts
Configuration data is stored in the four words at the top
of the on-chip program memory space, known as the
Flash Configuration Words. It is stored in program
memory in the same order shown in Table 20-1, with
CONFIG1L at the lowest address and CONFIG3H at
the highest. The data is automatically loaded in the
proper Configuration registers during device power-up.
• Watchdog Timer (WDT)
• Fail-Safe Clock Monitor
• Two-Speed Start-up
• Code Protection
When creating applications for these devices, users
should always specifically allocate the location of the
Flash Configuration Word for configuration data; this is
to make certain that program code is not stored in this
address when the code is compiled.
• In-Circuit Serial Programming
The oscillator can be configured for the application
depending on frequency, power, accuracy and cost. All
of the options are discussed in detail in Section 2.0
“Oscillator Configurations”.
The volatile memory cells used for the configuration
bits always reset to ‘1’ on Power-on Resets. For all
other type of Reset events, the previously programmed
values are maintained and used without reloading from
program memory.
A complete discussion of device Resets and interrupts
is available in previous sections of this data sheet.
In addition to their Power-up and Oscillator Start-up
Timers provided for Resets, the PIC18F45J10 family of
devices have a configurable Watchdog Timer which is
controlled in software.
The four Most Significant bits of CONFIG1H,
CONFIG2H and CONFIG3H in program memory
should also be ‘1111’. This makes these Configuration
Words appear to be NOP instructions in the remote
event that their locations are ever executed by
accident. Since configuration bits are not implemented
in the corresponding locations, writing ‘1’s to these
locations has no effect on device operation.
The inclusion of an internal RC oscillator also provides
the additional benefits of a Fail-Safe Clock Monitor
(FSCM) and Two-Speed Start-up. FSCM provides for
background monitoring of the peripheral clock and
automatic switchover in the event of its failure.
Two-Speed Start-up enables code to be executed
almost immediately on start-up, while the primary clock
source completes its start-up delays.
To prevent inadvertent configuration changes during
code execution, all programmable configuration bits
are write-once. After a bit is initially programmed during
a power cycle, it cannot be written to again. Changing
a device configuration requires a device Reset.
All of these features are enabled and configured by
setting the appropriate Configuration register bits.
20.1 Configuration Bits
The configuration bits can be programmed (read as ‘0’)
or left unprogrammed (read as ‘1’) to select various
device configurations. These bits are mapped starting
at program memory location 300000h. A complete list
is shown in Table 20-1. A detailed explanation of the
various bit functions is provided in Register 20-1
through Register 20-6.
Note that address 300000h is beyond the user program
memory space. In fact, it belongs to the configuration
memory space (300000h-3FFFFFh) which can only be
accessed using table reads and table writes.
© 2007 Microchip Technology Inc.
Preliminary
DS39682C-page 229
PIC18F45J10 FAMILY
TABLE 20-1: CONFIGURATION BITS AND DEVICE IDs
Default/
File Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Unprogrammed
(1)
Value
300000h CONFIG1L DEBUG
XINST STVREN
—
—
—
—
—
WDTEN
—
111- ---1
---- x1--
11-- -111
(2)
(2)
(2)
(2)
(3)
300001h CONFIG1H
300002h CONFIG2L
300003h CONFIG2H
300004h CONFIG3L
300005h CONFIG3H
3FFFFEh DEVID1
—
—
—
—
—
—
—
CP0
IESO
(2)
FCMEN
—
(2)
—
—
FOSC2
FOSC1
FOSC0
(2)
(2)
—
—
—
WDTPS3 WDTPS2 WDTPS1 WDTPS0 ---- 1111
—
(2)
—
(2)
—
(2)
—
—
—
—
—
---- ----
(2)
—
—
—
—
—
—
CCP2MX ---- ---1
(4)
(4)
DEV2
DEV1
DEV9
DEV0
DEV8
REV4
DEV7
REV3
DEV6
REV2
DEV5
REV1
DEV4
REV0
DEV3
xxxx xxxx
0001 110x
3FFFFFh DEVID2
DEV10
Legend:
x= unknown, u= unchanged, -= unimplemented. Shaded cells are unimplemented, read as ‘0’.
Note 1: Values reflect the unprogrammed state as received from the factory and following Power-on Resets. In all other Reset
states, the configuration bytes maintain their previously programmed states.
2: The value of these bits in program memory should always be ‘1’. This ensures that the location is executed as a NOPif it
is accidentally executed.
3: This bit should always be maintained as ‘0’.
4: See Register 20-7 and Register 20-8 for DEVID values. These registers are read-only and cannot be programmed by
the user.
DS39682C-page 230
Preliminary
© 2007 Microchip Technology Inc.
PIC18F45J10 FAMILY
REGISTER 20-1: CONFIG1L: CONFIGURATION REGISTER 1 LOW (BYTE ADDRESS 300000h)
R/WO-1
DEBUG
R/WO-1
XINST
R/WO-1
U-0
—
U-0
—
U-0
—
U-0
—
R/WO-1
WDTEN
STVREN
bit 7
bit 0
bit 7
bit 6
bit 5
DEBUG: Background Debugger Enable bit
1= Background debugger disabled; RB6 and RB7 configured as general purpose I/O pins
0= Background debugger enabled; RB6 and RB7 are dedicated to In-Circuit Debug
XINST: Extended Instruction Set Enable bit
1= Instruction set extension and Indexed Addressing mode enabled
0= Instruction set extension and Indexed Addressing mode disabled (Legacy mode)
STVREN: Stack Overflow/Underflow Reset Enable bit
1= Reset on stack overflow/underflow enabled
0= Reset on stack overflow/underflow disabled
bit 4-1
bit 0
Unimplemented: Read as ‘0’
WDTEN: Watchdog Timer Enable bit
1= WDT enabled
0= WDT disabled (control is placed on SWDTEN bit)
Legend:
R = Readable bit
WO = Write-once bit
U = Unimplemented bit, read as ‘0’
‘1’ = Bit is set ‘0’ = Bit is cleared
-n = Value when device is unprogrammed
REGISTER 20-2: CONFIG1H:CONFIGURATIONREGISTER1HIGH(BYTEADDRESS300001h)
U-0
—
U-0
—
U-0
—
U-0
—
U-0
R/WO-1
CP0
U-0
—
U-0
—
(1)
—
bit 7
bit 0
bit 7-3 Unimplemented: Read as ‘0’
bit 2 CP0: Code Protection bit
1= Program memory is not code-protected
0= Program memory is code-protected
bit 1-0 Unimplemented: Read as ‘0’
Note 1: This bit should always be maintained as ‘0’.
Legend:
R = Readable bit
WO = Write-once bit
U = Unimplemented bit, read as ‘0’
‘1’ = Bit is set ‘0’ = Bit is cleared
-n = Value when device is unprogrammed
© 2007 Microchip Technology Inc.
Preliminary
DS39682C-page 231
PIC18F45J10 FAMILY
REGISTER 20-3: CONFIG2L: CONFIGURATION REGISTER 2 LOW (BYTE ADDRESS 300002h)
R/WO-1
IESO
R/WO-1
FCMEN
U-0
—
U-0
—
U-0
—
R/WO-1
FOSC2
R/WO-1
FOSC1
R/WO-1
FOSC0
bit 7
bit 0
bit 7
bit 6
IESO: Two-Speed Start-up (Internal/External Oscillator Switchover) Control bit
1= Two-Speed Start-up enabled
0= Two-Speed Start-up disabled
FCMEN: Fail-Safe Clock Monitor Enable bit
1= Fail-Safe Clock Monitor enabled
0= Fail-Safe Clock Monitor disabled
bit 5-3 Unimplemented: Read as ‘0’
bit 2 FOSC2: Default/Reset System Clock Select bit
1= Clock selected by FOSC1:FOSC0 as system clock is enabled when OSCCON<1:0> = 00
0= INTRC enabled as system clock when OSCCON<1:0> = 00
bit 1-0 FOSC1:FOSC0: Oscillator Selection bits
11= EC oscillator, PLL enabled and under software control, CLKO function on OSC2
10= EC oscillator, CLKO function on OSC2
01= HS oscillator, PLL enabled and under software control
00= HS oscillator
Legend:
R = Readable bit
WO = Write-once bit
U = Unimplemented bit, read as ‘0’
‘1’ = Bit is set ‘0’ = Bit is cleared
-n = Value when device is unprogrammed
REGISTER 20-4: CONFIG2H:CONFIGURATIONREGISTER 2HIGH (BYTEADDRESS 300003h)
U-0
—
U-0
—
U-0
—
U-0
—
R/WO-1
R/WO-1
R/WO-1
R/WO-1
WDTPS3 WDTPS2 WDTPS1 WDTPS0
bit 0
bit 7
bit 7-4
bit 3-0
Unimplemented: Read as ‘0’
WDTPS3:WDTPS0: Watchdog Timer Postscale Select bits
1111= 1:32,768
1110= 1:16,384
1101= 1:8,192
1100= 1:4,096
1011= 1:2,048
1010= 1:1,024
1001= 1:512
1000= 1:256
0111= 1:128
0110= 1:64
0101= 1:32
0100= 1:16
0011= 1:8
0010= 1:4
0001= 1:2
0000= 1:1
Legend:
R = Readable bit
WO = Write-once bit
U = Unimplemented bit, read as ‘0’
‘1’ = Bit is set ‘0’ = Bit is cleared
-n = Value when device is unprogrammed
DS39682C-page 232
Preliminary
© 2007 Microchip Technology Inc.
PIC18F45J10 FAMILY
REGISTER 20-5: CONFIG3L: CONFIGURATION REGISTER 3 LOW (BYTE ADDRESS 300004h)
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
bit 7
bit 0
bit 7-0 Unimplemented: Read as ‘0’
Legend:
R = Readable bit
U = Unimplemented bit, read as ‘0’
‘1’ = Bit is set
-n = Value when device is unprogrammed
‘0’ = Bit is cleared
REGISTER 20-6: CONFIG3H: CONFIGURATION REGISTER 3 HIGH (BYTE ADDRESS 300005h)
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
R/WO-1
CCP2MX
bit 0
bit 7
bit 7-1 Unimplemented: Read as ‘0’
bit 0
CCP2MX: CCP2 Mux bit
1= CCP2 is multiplexed with RC1
0= CCP2 is multiplexed with RB3
Legend:
R = Readable bit
WO = Write-once bit
U = Unimplemented bit, read as ‘0’
‘1’ = Bit is set ‘0’ = Bit is cleared
-n = Value when device is unprogrammed
© 2007 Microchip Technology Inc.
Preliminary
DS39682C-page 233
PIC18F45J10 FAMILY
REGISTER 20-7: DEVICE ID REGISTER 1 FOR PIC18F45J10 FAMILY DEVICES
R
R
R
R
R
R
R
R
DEV2
DEV1
DEV0
REV4
REV3
REV2
REV1
REV0
bit 7
bit 0
bit 7-5 DEV2:DEV0: Device ID bits
011= PIC18F4XJ10
010= PIC18F2XJ10
001= PIC18F4XJ10
000= PIC18F2XJ10
Note:
Where values for DEV2:DEV0 are shared by more than one device number, the
specific device is always identified by using the entire DEV10:DEV0 bit sequence.
bit 4-0 REV4:REV0: Revision ID bits
These bits are used to indicate the device revision.
Legend:
R = Read-only bit
U = Unimplemented bit, read as ‘0’
-n = Value when device is unprogrammed
u = Unchanged from programmed state
REGISTER 20-8: DEVICE ID REGISTER 2 FOR PIC18F45J10 FAMILY DEVICES
R
R
R
R
R
R
R
R
DEV10
DEV9
DEV8
DEV7
DEV6
DEV5
DEV4
DEV3
bit 7
bit 0
bit 7-0 DEV10:DEV3: Device ID bits
These bits are used with the DEV2:DEV0 bits in the Device ID Register 1 to identify the
part number.
0001 1100= PIC18FX5J10 devices
0001 1101= PIC18FX4J10 devices
Note:
The values for DEV10:DEV3 may be shared with other device families. The specific
device is always identified by using the entire DEV10:DEV0 bit sequence.
Legend:
R = Read-only bit
U = Unimplemented bit, read as ‘0’
-n = Value when device is unprogrammed
u = Unchanged from programmed state
DS39682C-page 234
Preliminary
© 2007 Microchip Technology Inc.
PIC18F45J10 FAMILY
20.2 Watchdog Timer (WDT)
Note 1: The CLRWDT and SLEEP instructions
clear the WDT and postscaler counts
when executed.
For PIC18F45J10 family devices, the WDT is driven by
the INTRC oscillator. When the WDT is enabled, the
clock source is also enabled. The nominal WDT period
is 4 ms and has the same stability as the INTRC
oscillator.
2: When a CLRWDTinstruction is executed,
the postscaler count will be cleared.
20.2.1
CONTROL REGISTER
The 4 ms period of the WDT is multiplied by a 16-bit
postscaler. Any output of the WDT postscaler is
selected by a multiplexor, controlled by the WDTPS bits
in Configuration Register 2H. Available periods range
from 4 ms to 131.072 seconds (2.18 minutes). The
WDT and postscaler are cleared whenever a SLEEPor
CLRWDT instruction is executed, or a clock failure
(primary or Timer1 oscillator) has occurred.
The WDTCON register (Register 20-9) is a readable
and writable register. The SWDTEN bit enables or
disables WDT operation.
FIGURE 20-1:
WDT BLOCK DIAGRAM
Enable WDT
INTRC Control
SWDTEN
WDT Counter
Wake-up from
Power-Managed
Modes
÷128
INTRC Oscillator
WDT
Reset
Reset
CLRWDT
All Device Resets
Programmable Postscaler
1:1 to 1:32,768
WDT
4
WDTPS3:WDTPD0
Sleep
REGISTER 20-9: WDTCON: WATCHDOG TIMER CONTROL REGISTER
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
R/W-0
SWDTEN(1)
bit 0
—
bit 7
bit 7-1 Unimplemented: Read as ‘0’
bit 0
SWDTEN: Software Controlled Watchdog Timer Enable bit(1)
1= Watchdog Timer is on
0= Watchdog Timer is off
Note 1: This bit has no effect if the configuration bit, WDTEN, is enabled.
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
TABLE 20-2: SUMMARY OF WATCHDOG TIMER REGISTERS
ResetValues
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
on page
RCON
WDTCON
IPEN
—
—
—
—
—
RI
—
TO
—
PD
—
POR
—
BOR
44
44
SWDTEN
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the Watchdog Timer.
© 2007 Microchip Technology Inc.
Preliminary
DS39682C-page 235
PIC18F45J10 FAMILY
20.3.1
ON-CHIP REGULATOR AND BOR
20.3 On-Chip Voltage Regulator
PIC18F45J10 family devices (designated with an “F”
part number) also have a simple brown-out capability.
If the voltage supplied to the regulator is inadequate to
maintain a regulated level, the regulator Reset circuitry
will generate a BOR Reset. This event is captured by
the BOR flag bit (RCON<0>).
Note:
The on-chip voltage regulator is only
available in parts designated with an “F”,
such as PIC18F45J10.
In parts designated “LF”, the microcontroller core can
be powered from an external source that is separate
from VDD, or it can be powered from an on-chip regula-
tor which derives power from VDD. Both sources use
the common VDDCORE/VCAP pin.
The operation of the BOR is described in more detail in
Section 4.4
“Brown-out
Reset
(BOR)
(PIC18F2X1X/4X1X Devices Only)” and Section 4.4.1
“Detecting BOR”. The brown-out voltage levels are
specific in Section 23.1 “DC Characteristics”.
In “F” devices, a low ESR capacitor must be connected
to the VDDCORE/VCAP pin for proper device operation.
In parts designated with an “LF” part number (i.e.,
PIC18LF45J10), power to the core must be supplied on
VDDCORE/VCAP. It is always good design practice to
have sufficient capacitance on all supply pins.
Examples are shown in Figure 20-2.
20.3.2
POWER-UP REQUIREMENTS
The on-chip regulator is designed to meet the power-up
requirements for the device. While powering up,
VDDCORE must never exceed VDD by 0.3 volts.
Note:
In parts designated with an “LF”, such as
PIC18LF45J10, VDDCORE must never
exceed VDD.
The specifications for core voltage and capacitance are
listed in Section 23.4 “AC (Timing) Characteristics”.
FIGURE 20-2:
CONNECTIONS FOR THE
ON-CHIP REGULATOR
PIC18FXXJ10 Devices (Regulator Enabled):
3.3V
PIC18FXXJ10
VDD
VDDCORE/VCAP
CF
VSS
PIC18LFXXJ10 Devices (Regulator Disabled):
2.5V
PIC18LFXXJ10
VDD
VDDCORE/VCAP
VSS
OR
3.3V
2.5V
PIC18LFXXJ10
VDD
VDDCORE/VCAP
VSS
DS39682C-page 236
Preliminary
© 2007 Microchip Technology Inc.
PIC18F45J10 FAMILY
In all other power-managed modes, Two-Speed
Start-up is not used. The device will be clocked by the
currently selected clock source until the primary clock
source becomes available. The setting of the IESO bit
is ignored.
20.4 Two-Speed Start-up
The Two-Speed Start-up feature helps to minimize the
latency period, from oscillator start-up to code execu-
tion, by allowing the microcontroller to use the INTRC
oscillator as a clock source until the primary clock
source is available. It is enabled by setting the IESO
configuration bit.
20.4.1
SPECIAL CONSIDERATIONS FOR
USING TWO-SPEED START-UP
Two-Speed Start-up should be enabled only if the
primary oscillator mode is HS (Crystal-based) modes.
Since the EC mode does not require an OST start-up
delay, Two-Speed Start-up should be disabled.
While using the INTRC oscillator in Two-Speed
Start-up, the device still obeys the normal command
sequences for entering power-managed modes,
including serial SLEEP instructions (refer to
Section 3.1.4 “Multiple Sleep Commands”). In
practice, this means that user code can change the
SCS1:SCS0 bit settings or issue SLEEP instructions
before the OST times out. This would allow an applica-
tion to briefly wake-up, perform routine “housekeeping”
tasks and return to Sleep before the device starts to
operate from the primary oscillator.
When enabled, Resets and wake-ups from Sleep mode
cause the device to configure itself to run from the inter-
nal oscillator block as the clock source, following the
time-out of the Power-up Timer after a POR Reset is
enabled. This allows almost immediate code execution
while the primary oscillator starts and the OST is
running. Once the OST times out, the device
automatically switches to PRI_RUN mode.
User code can also check if the primary clock source is
currently providing the device clocking by checking the
status of the OSTS bit (OSCCON<3>). If the bit is set,
the primary oscillator is providing the clock. Otherwise,
the internal oscillator block is providing the clock during
wake-up from Reset or Sleep mode.
FIGURE 20-3:
TIMING TRANSITION FOR TWO-SPEED START-UP (INTRC)
Q3
Q4
Q1
Q2 Q3 Q4 Q1 Q2 Q3
Q1
Q2
INTOSC
OSC1
(1)
TOST
CPU Clock
Peripheral
Clock
Program
Counter
PC + 4
PC + 6
PC
PC + 2
OSTS bit Set
Wake from Interrupt Event
Note 1: TOST = 1024 TOSC. These intervals are not shown to scale.
© 2007 Microchip Technology Inc.
Preliminary
DS39682C-page 237
PIC18F45J10 FAMILY
To use a higher clock speed on wake-up, the INTOSC
or postscaler clock sources can be selected to provide
a higher clock speed by setting bits IRCF2:IRCF0
immediately after Reset. For wake-ups from Sleep, the
INTOSC or postscaler clock sources can be selected
by setting IRCF2:IRCF0 prior to entering Sleep mode.
20.5 Fail-Safe Clock Monitor
The Fail-Safe Clock Monitor (FSCM) allows the
microcontroller to continue operation in the event of an
external oscillator failure by automatically switching the
device clock to the internal oscillator block. The FSCM
function is enabled by setting the FCMEN configuration
bit.
The FSCM will detect failures of the primary or second-
ary clock sources only. If the internal oscillator block
fails, no failure would be detected, nor would any action
be possible.
When FSCM is enabled, the INTRC oscillator runs at
all times to monitor clocks to peripherals and provide a
backup clock in the event of a clock failure. Clock
monitoring (shown in Figure 20-4) is accomplished by
creating a sample clock signal which is the INTRC out-
put divided by 64. This allows ample time between
FSCM sample clocks for a peripheral clock edge to
occur. The peripheral device clock and the sample
clock are presented as inputs to the Clock Monitor latch
(CM). The CM is set on the falling edge of the device
clock source but cleared on the rising edge of the
sample clock.
20.5.1
FSCM AND THE WATCHDOG TIMER
Both the FSCM and the WDT are clocked by the
INTRC oscillator. Since the WDT operates with a
separate divider and counter, disabling the WDT has
no effect on the operation of the INTRC oscillator when
the FSCM is enabled.
As already noted, the clock source is switched to the
INTRC clock when a clock failure is detected; this may
mean a substantial change in the speed of code execu-
tion. If the WDT is enabled with a small prescale value,
a decrease in clock speed allows a WDT time-out to
occur and a subsequent device Reset. For this reason,
Fail-Safe Clock Monitor events also reset the WDT and
postscaler, allowing it to start timing from when execu-
tion speed was changed and decreasing the likelihood
of an erroneous time-out.
FIGURE 20-4:
FSCM BLOCK DIAGRAM
Clock Monitor
Latch (CM)
(edge-triggered)
Peripheral
Clock
S
C
Q
Q
INTRC
Source
20.5.2
EXITING FAIL-SAFE OPERATION
÷ 64
The fail-safe condition is terminated by either a device
Reset or by entering a power-managed mode. On
Reset, the controller starts the primary clock source
specified in Configuration Register 2H (with the OST
oscillator, start-up delays if running in HS mode). The
INTRC oscillator provides the device clock until the
primary clock source becomes ready (similar to a
Two-Speed Start-up). The clock source is then
switched to the primary clock (indicated by the OSTS
bit in the OSCCON register becoming set). The
Fail-Safe Clock Monitor then resumes monitoring the
peripheral clock.
488 Hz
(2.048 ms)
(32 μs)
Clock
Failure
Detected
Clock failure is tested for on the falling edge of the
sample clock. If a sample clock falling edge occurs
while CM is still set, a clock failure has been detected
(Figure 20-5). This causes the following:
• the FSCM generates an oscillator fail interrupt by
setting bit OSCFIF (PIR2<7>);
The primary clock source may never become ready
during start-up. In this case, operation is clocked by the
INTRC oscillator. The OSCCON register will remain in
its Reset state until a power-managed mode is entered.
• the device clock source is switched to the internal
oscillator block (OSCCON is not updated to show
the current clock source – this is the fail-safe
condition); and
• the WDT is reset.
During switchover, the postscaler frequency from the
internal oscillator block may not be sufficiently stable
for timing sensitive applications. In these cases, it may
be desirable to select another clock configuration and
enter an alternate power-managed mode. This can be
done to attempt a partial recovery or execute a
controlled shutdown. See Section 3.1.4 “Multiple
Sleep Commands” and Section 20.4.1 “Special
Considerations for Using Two-Speed Start-up” for
more details.
DS39682C-page 238
Preliminary
© 2007 Microchip Technology Inc.
PIC18F45J10 FAMILY
FIGURE 20-5:
FSCM TIMING DIAGRAM
Sample Clock
Oscillator
Failure
Device
Clock
Output
CM Output
(Q)
Failure
Detected
OSCFIF
CM Test
CM Test
CM Test
Note:
The device clock is normally at a much higher frequency than the sample clock. The relative frequencies in
this example have been chosen for clarity.
20.5.3
FSCM INTERRUPTS IN
20.5.4
POR OR WAKE-UP FROM SLEEP
POWER-MANAGED MODES
The FSCM is designed to detect oscillator failure at any
point after the device has exited Power-on Reset
(POR) or low-power Sleep mode. When the primary
device clock is either EC or INTRC modes, monitoring
can begin immediately following these events.
By entering a power-managed mode, the clock
multiplexor selects the clock source selected by the
OSCCON register. Fail-Safe Monitoring of the
power-managed clock source resumes in the
power-managed mode.
For HS mode, the situation is somewhat different.
Since the oscillator may require a start-up time consid-
erably longer than the FSCM sample clock time, a false
clock failure may be detected. To prevent this, the
internal oscillator block is automatically configured as
the device clock and functions until the primary clock is
stable (the OST timer has timed out). This is identical
to Two-Speed Start-up mode. Once the primary clock is
stable, the INTRC returns to its role as the FSCM
source.
If an oscillator failure occurs during power-managed
operation, the subsequent events depend on whether
or not the oscillator failure interrupt is enabled. If
enabled (OSCFIF = 1), code execution will be clocked
by the INTOSC multiplexor. An automatic transition
back to the failed clock source will not occur.
If the interrupt is disabled, subsequent interrupts while
in Idle mode will cause the CPU to begin executing
instructions while being clocked by the INTOSC
source.
Note:
The same logic that prevents false oscilla-
tor failure interrupts on POR, or wake from
Sleep, will also prevent the detection of
the oscillator’s failure to start at all
following these events. This can be
avoided by monitoring the OSTS bit and
using a timing routine to determine if the
oscillator is taking too long to start. Even
so, no oscillator failure interrupt will be
flagged.
As noted in Section 20.4.1 “Special Considerations
for Using Two-Speed Start-up”, it is also possible to
select another clock configuration and enter an alternate
power-managed mode while waiting for the primary
clock to become stable. When the new power-managed
mode is selected, the primary clock is disabled.
© 2007 Microchip Technology Inc.
Preliminary
DS39682C-page 239
PIC18F45J10 FAMILY
20.6 Program Verification and
Code Protection
20.7
In-Circuit Serial Programming
PIC18F45J10 family microcontrollers can be serially
programmed while in the end application circuit. This is
simply done with two lines for clock and data and three
other lines for power, ground and the programming
voltage. This allows customers to manufacture boards
with unprogrammed devices and then program the
microcontroller just before shipping the product. This
also allows the most recent firmware or a custom
firmware to be programmed.
For all devices in the PIC18F45J10 family of devices,
the on-chip program memory space is treated as a
single block. Code protection for this block is controlled
by one configuration bit, CP0. This bit inhibits external
reads and writes to the program memory space. It has
no direct effect in normal execution mode.
20.6.1
CONFIGURATION REGISTER
PROTECTION
20.8 In-Circuit Debugger
The Configuration registers are protected against
untoward changes or reads in two ways. The primary
protection is the write-once feature of the configuration
bits which prevents reconfiguration once the bit has
been programmed during a power cycle. To safeguard
against unpredictable events, configuration bit changes
resulting from individual cell-level disruptions (such as
ESD events) will cause a parity error and trigger a
device Reset.
When the DEBUG configuration bit is programmed to a
‘0’, the In-Circuit Debugger functionality is enabled.
This function allows simple debugging functions when
used with MPLAB® IDE. When the microcontroller has
this feature enabled, some resources are not available
for general use. Table 20-3 shows which resources are
required by the background debugger.
The data for the Configuration registers is derived from
the Flash Configuration Words in program memory.
When the CP0 bit is set, the source data for device
configuration is also protected as a consequence.
TABLE 20-3: DEBUGGER RESOURCES
I/O pins:
RB6, RB7
2 levels
Stack:
Program Memory:
Data Memory:
512 bytes
32 bytes
DS39682C-page 240
Preliminary
© 2007 Microchip Technology Inc.
PIC18F45J10 FAMILY
The literal instructions may use some of the following
operands:
21.0 INSTRUCTION SET SUMMARY
PIC18F45J10 family devices incorporate the standard
set of 75 PIC18 core instructions, as well as an extended
set of 8 new instructions, for the optimization of code that
is recursive or that utilizes a software stack. The
extended set is discussed later in this section.
• A literal value to be loaded into a file register
(specified by ‘k’)
• The desired FSR register to load the literal value
into (specified by ‘f’)
• No operand required
(specified by ‘—’)
21.1 Standard Instruction Set
The control instructions may use some of the following
operands:
The standard PIC18 instruction set adds many
enhancements to the previous PIC® instruction sets,
while maintaining an easy migration from these PIC
instruction sets. Most instructions are a single program
memory word (16 bits), but there are four instructions
that require two program memory locations.
• A program memory address (specified by ‘n’)
• The mode of the CALLor RETURNinstructions
(specified by ‘s’)
• The mode of the table read and table write
instructions (specified by ‘m’)
Each single-word instruction is a 16-bit word divided
into an opcode, which specifies the instruction type and
one or more operands, which further specify the
operation of the instruction.
• No operand required
(specified by ‘—’)
All instructions are a single word, except for four
double-word instructions. These instructions were
made double-word to contain the required information
in 32 bits. In the second word, the 4 MSbs are ‘1’s. If
this second word is executed as an instruction (by
itself), it will execute as a NOP.
The instruction set is highly orthogonal and is grouped
into four basic categories:
• Byte-oriented operations
• Bit-oriented operations
• Literal operations
All single-word instructions are executed in a single
instruction cycle, unless a conditional test is true or the
program counter is changed as a result of the instruc-
tion. In these cases, the execution takes two instruction
cycles, with the additional instruction cycle(s) executed
as a NOP.
• Control operations
The PIC18 instruction set summary in Table 21-2 lists
byte-oriented, bit-oriented, literal and control
operations. Table 21-1 shows the opcode field
descriptions.
Most byte-oriented instructions have three operands:
The double-word instructions execute in two instruction
cycles.
1. The file register (specified by ‘f’)
One instruction cycle consists of four oscillator periods.
Thus, for an oscillator frequency of 4 MHz, the normal
instruction execution time is 1 μs. If a conditional test is
true, or the program counter is changed as a result of
an instruction, the instruction execution time is 2 μs.
Two-word branch instructions (if true) would take 3 μs.
2. The destination of the result (specified by ‘d’)
3. The accessed memory (specified by ‘a’)
The file register designator ‘f’ specifies which file
register is to be used by the instruction. The destination
designator ‘d’ specifies where the result of the opera-
tion is to be placed. If ‘d’ is zero, the result is placed in
the WREG register. If ‘d’ is one, the result is placed in
the file register specified in the instruction.
Figure 21-1 shows the general formats that the instruc-
tions can have. All examples use the convention ‘nnh’
to represent a hexadecimal number.
All bit-oriented instructions have three operands:
The Instruction Set Summary, shown in Table 21-2,
lists the standard instructions recognized by the
Microchip Assembler (MPASMTM).
1. The file register (specified by ‘f’)
2. The bit in the file register (specified by ‘b’)
3. The accessed memory (specified by ‘a’)
Section 21.1.1 “Standard Instruction Set” provides
The bit field designator ‘b’ selects the number of the bit
affected by the operation, while the file register
designator ‘f’ represents the number of the file in which
the bit is located.
a description of each instruction.
© 2007 Microchip Technology Inc.
Preliminary
DS39682C-page 241
PIC18F45J10 FAMILY
TABLE 21-1: OPCODE FIELD DESCRIPTIONS
Field
Description
a
RAM access bit
a = 0: RAM location in Access RAM (BSR register is ignored)
a = 1: RAM bank is specified by BSR register
bbb
Bit address within an 8-bit file register (0 to 7).
BSR
Bank Select Register. Used to select the current RAM bank.
ALU Status bits: Carry, Digit Carry, Zero, Overflow, Negative.
C, DC, Z, OV, N
d
Destination select bit
d = 0: store result in WREG
d = 1: store result in file register f
dest
f
Destination: either the WREG register or the specified register file location.
8-bit Register file address (00h to FFh) or 2-bit FSR designator (0h to 3h).
12-bit Register file address (000h to FFFh). This is the source address.
12-bit Register file address (000h to FFFh). This is the destination address.
Global Interrupt Enable bit.
f
f
s
d
GIE
k
Literal field, constant data or label (may be either an 8-bit, 12-bit or a 20-bit value).
Label name.
label
mm
The mode of the TBLPTR register for the table read and table write instructions.
Only used with table read and table write instructions:
*
No change to register (such as TBLPTR with table reads and writes)
Post-Increment register (such as TBLPTR with table reads and writes)
Post-Decrement register (such as TBLPTR with table reads and writes)
Pre-Increment register (such as TBLPTR with table reads and writes)
*+
*-
+*
n
The relative address (2’s complement number) for relative branch instructions or the direct address for
Call/Branch and Return instructions.
PC
Program Counter.
PCL
Program Counter Low Byte.
Program Counter High Byte.
Program Counter High Byte Latch.
Program Counter Upper Byte Latch.
Power-down bit.
PCH
PCLATH
PCLATU
PD
PRODH
PRODL
s
Product of Multiply High Byte.
Product of Multiply Low Byte.
Fast Call/Return mode select bit
s = 0: do not update into/from shadow registers
s = 1: certain registers loaded into/from shadow registers (Fast mode)
TBLPTR
TABLAT
TO
21-bit Table Pointer (points to a Program Memory location).
8-bit Table Latch.
Time-out bit.
TOS
u
Top-of-Stack.
Unused or unchanged.
Watchdog Timer.
WDT
WREG
x
Working register (accumulator).
Don’t care (‘0’ or ‘1’). The assembler will generate code with x = 0. It is the recommended form of use for
compatibility with all Microchip software tools.
z
z
{
7-bit offset value for indirect addressing of register files (source).
7-bit offset value for indirect addressing of register files (destination).
Optional argument.
s
d
}
[text]
(text)
[expr]<n>
→
Indicates an indexed address.
The contents of text.
Specifies bit nof the register indicated by the pointer expr.
Assigned to.
< >
Register bit field.
∈
In the set of.
italics
User defined term (font is Courier).
DS39682C-page 242
Preliminary
© 2007 Microchip Technology Inc.
PIC18F45J10 FAMILY
FIGURE 21-1:
GENERAL FORMAT FOR INSTRUCTIONS
Byte-oriented file register operations
15 10
OPCODE f (FILE #)
Example Instruction
9
8
7
0
ADDWF MYREG, W, B
d
a
d = 0for result destination to be WREG register
d = 1for result destination to be file register (f)
a = 0to force Access Bank
a = 1for BSR to select bank
f = 8-bit file register address
Byte to Byte move operations (2-word)
15
12 11
0
0
OPCODE
f (Source FILE #)
MOVFF MYREG1, MYREG2
15
12 11
1111
f (Destination FILE #)
f = 12-bit file register address
Bit-oriented file register operations
15 12 11 9 8
OPCODE b (BIT #)
7
0
BSF MYREG, bit, B
a
f (FILE #)
b = 3-bit position of bit in file register (f)
a = 0to force Access Bank
a = 1for BSR to select bank
f = 8-bit file register address
Literal operations
15
8
7
0
MOVLW 7Fh
OPCODE
k (literal)
k = 8-bit immediate value
Control operations
CALL, GOTO and Branch operations
15
8 7
0
GOTO Label
OPCODE
12 11
n<7:0> (literal)
15
0
1111
n<19:8> (literal)
n = 20-bit immediate value
15
15
8
7
0
CALL MYFUNC
OPCODE
12 11
n<7:0> (literal)
S
0
1111
n<19:8> (literal)
S = Fast bit
15
11 10
0
0
BRA MYFUNC
BC MYFUNC
OPCODE
n<10:0> (literal)
15
OPCODE
8 7
n<7:0> (literal)
© 2007 Microchip Technology Inc.
Preliminary
DS39682C-page 243
PIC18F45J10 FAMILY
TABLE 21-2: PIC18FXXXX INSTRUCTION SET
16-Bit Instruction Word
MSb LSb
Mnemonic,
Operands
Status
Affected
Description
Cycles
Notes
BYTE-ORIENTED OPERATIONS
ADDWF f, d, a Add WREG and f
ADDWFC f, d, a Add WREG and CARRY bit to f
1
1
1
1
1
0010 01da
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff C, DC, Z, OV, N
ffff C, DC, Z, OV, N
ffff Z, N
1, 2
1, 2
1,2
2
1, 2
4
4
1, 2
1, 2, 3, 4
1, 2, 3, 4
1, 2
1, 2, 3, 4
4
1, 2
1, 2
1
0010 00da
0001 01da
0110 101a
0001 11da
ANDWF
CLRF
COMF
f, d, a AND WREG with f
f, a Clear f
f, d, a Complement f
ffff
Z
ffff Z, N
ffff None
ffff None
ffff None
ffff C, DC, Z, OV, N
ffff None
ffff None
ffff C, DC, Z, OV, N
ffff None
ffff None
ffff Z, N
ffff Z, N
ffff None
ffff
ffff None
ffff None
CPFSEQ
CPFSGT
CPFSLT
DECF
f, a
f, a
f, a
Compare f with WREG, skip =
Compare f with WREG, skip >
Compare f with WREG, skip <
1 (2 or 3) 0110 001a
1 (2 or 3) 0110 010a
1 (2 or 3) 0110 000a
f, d, a Decrement f
1
0000 01da
DECFSZ
DCFSNZ
INCF
f, d, a Decrement f, Skip if 0
f, d, a Decrement f, Skip if Not 0
f, d, a Increment f
1 (2 or 3) 0010 11da
1 (2 or 3) 0100 11da
1
1 (2 or 3) 0011 11da
1 (2 or 3) 0100 10da
1
1
2
0010 10da
INCFSZ
INFSNZ
IORWF
MOVF
f, d, a Increment f, Skip if 0
f, d, a Increment f, Skip if Not 0
f, d, a Inclusive OR WREG with f
f, d, a Move f
0001 00da
0101 00da
1100 ffff
1111 ffff
0110 111a
0000 001a
0110 110a
0011 01da
0100 01da
0011 00da
0100 00da
0110 100a
0101 01da
MOVFF
f , f
Move f (source) to 1st word
s
d
s
f (destination) 2nd word
d
MOVWF
MULWF
NEGF
f, a
f, a
f, a
Move WREG to f
Multiply WREG with f
Negate f
1
1
1
1
1
1
1
1
1
1, 2
1, 2
ffff C, DC, Z, OV, N
ffff C, Z, N
ffff Z, N
ffff C, Z, N
ffff Z, N
RLCF
RLNCF
RRCF
RRNCF
SETF
f, d, a Rotate Left f through Carry
f, d, a Rotate Left f (No Carry)
f, d, a Rotate Right f through Carry
f, d, a Rotate Right f (No Carry)
f, a
Set f
ffff None
ffff C, DC, Z, OV, N
1, 2
1, 2
SUBFWB f, d, a Subtract f from WREG with
borrow
SUBWF
f, d, a Subtract WREG from f
1
1
0101 11da
0101 10da
ffff
ffff
ffff C, DC, Z, OV, N
ffff C, DC, Z, OV, N
SUBWFB f, d, a Subtract WREG from f with
borrow
SWAPF
TSTFSZ
XORWF
f, d, a Swap nibbles in f
f, a Test f, skip if 0
f, d, a Exclusive OR WREG with f
1
0011 10da
ffff
ffff
ffff
ffff None
ffff None
ffff Z, N
4
1, 2
1 (2 or 3) 0110 011a
0001 10da
1
Note 1: When a Port register is modified as a function of itself (e.g., MOVF PORTB, 1, 0), the value used will be that value
present on the pins themselves. For example, if the data latch is ‘1’ for a pin configured as input and is driven low by an
external device, the data will be written back with a ‘0’.
2: If this instruction is executed on the TMR0 register (and where applicable, ‘d’ = 1), the prescaler will be cleared if
assigned.
3: If Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The second cycle is
executed as a NOP.
4: Some instructions are two-word instructions. The second word of these instructions will be executed as a NOPunless the
first word of the instruction retrieves the information embedded in these 16 bits. This ensures that all program memory
locations have a valid instruction.
DS39682C-page 244
Preliminary
© 2007 Microchip Technology Inc.
PIC18F45J10 FAMILY
TABLE 21-2: PIC18FXXXX INSTRUCTION SET (CONTINUED)
16-Bit Instruction Word
Mnemonic,
Operands
Status
Affected
Description
Cycles
Notes
MSb LSb
BIT-ORIENTED OPERATIONS
BCF
BSF
BTFSC
BTFSS
BTG
f, b, a Bit Clear f
f, b, a Bit Set f
f, b, a Bit Test f, Skip if Clear
f, b, a Bit Test f, Skip if Set
f, d, a Bit Toggle f
1
1
1001 bbba
1000 bbba
ffff
ffff
ffff
ffff
ffff
ffff None
ffff None
ffff None
ffff None
ffff None
1, 2
1, 2
3, 4
3, 4
1, 2
1 (2 or 3) 1011 bbba
1 (2 or 3) 1010 bbba
1
0111 bbba
CONTROL OPERATIONS
BC
BN
n
n
n
n
n
n
n
n
Branch if Carry
1 (2)
1 (2)
1 (2)
1 (2)
1 (2)
1 (2)
1 (2)
2
1110 0010
1110 0110
1110 0011
1110 0111
1110 0101
1110 0001
1110 0100
1101 0nnn
1110 0000
1110 110s
1111 kkkk
0000 0000
0000 0000
1110 1111
1111 kkkk
0000 0000
1111 xxxx
0000 0000
0000 0000
1101 1nnn
0000 0000
0000 0000
nnnn
nnnn
nnnn
nnnn
nnnn
nnnn
nnnn
nnnn
nnnn
kkkk
kkkk
0000
0000
kkkk
kkkk
0000
xxxx
0000
0000
nnnn
1111
0001
nnnn None
nnnn None
nnnn None
nnnn None
nnnn None
nnnn None
nnnn None
nnnn None
nnnn None
kkkk None
kkkk
Branch if Negative
Branch if Not Carry
Branch if Not Negative
Branch if Not Overflow
Branch if Not Zero
Branch if Overflow
Branch Unconditionally
Branch if Zero
Call subroutine 1st word
2nd word
Clear Watchdog Timer
Decimal Adjust WREG
Go to address 1st word
2nd word
BNC
BNN
BNOV
BNZ
BOV
BRA
BZ
n
n, s
1 (2)
2
CALL
CLRWDT
DAW
GOTO
—
—
n
1
1
2
0100 TO, PD
0111
C
kkkk None
kkkk
NOP
NOP
POP
PUSH
RCALL
RESET
RETFIE
—
—
—
—
n
No Operation
No Operation
1
1
1
1
2
1
2
0000 None
xxxx None
0110 None
0101 None
nnnn None
1111 All
4
Pop top of return stack (TOS)
Push top of return stack (TOS)
Relative Call
Software device Reset
Return from interrupt enable
s
000s GIE/GIEH,
PEIE/GIEL
RETLW
RETURN
SLEEP
k
s
—
Return with literal in WREG
Return from Subroutine
Go into Standby mode
2
2
1
0000 1100
0000 0000
0000 0000
kkkk
0001
0000
kkkk None
001s None
0011 TO, PD
Note 1: When a Port register is modified as a function of itself (e.g., MOVF PORTB, 1, 0), the value used will be that value
present on the pins themselves. For example, if the data latch is ‘1’ for a pin configured as input and is driven low by an
external device, the data will be written back with a ‘0’.
2: If this instruction is executed on the TMR0 register (and where applicable, ‘d’ = 1), the prescaler will be cleared if
assigned.
3: If Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The second cycle is
executed as a NOP.
4: Some instructions are two-word instructions. The second word of these instructions will be executed as a NOPunless the
first word of the instruction retrieves the information embedded in these 16 bits. This ensures that all program memory
locations have a valid instruction.
© 2007 Microchip Technology Inc.
Preliminary
DS39682C-page 245
PIC18F45J10 FAMILY
TABLE 21-2: PIC18FXXXX INSTRUCTION SET (CONTINUED)
16-Bit Instruction Word
Mnemonic,
Operands
Status
Affected
Description
Cycles
Notes
MSb
LSb
LITERAL OPERATIONS
ADDLW
ANDLW
IORLW
LFSR
k
k
k
f, k
Add literal and WREG
AND literal with WREG
Inclusive OR literal with WREG
Move literal (12-bit) 2nd word
1
1
1
2
0000 1111 kkkk
0000 1011 kkkk
0000 1001 kkkk
1110 1110 00ff
1111 0000 kkkk
0000 0001 0000
0000 1110 kkkk
0000 1101 kkkk
0000 1100 kkkk
0000 1000 kkkk
0000 1010 kkkk
kkkk C, DC, Z, OV, N
kkkk Z, N
kkkk Z, N
kkkk None
kkkk
kkkk None
kkkk None
kkkk None
kkkk None
kkkk C, DC, Z, OV, N
kkkk Z, N
to FSR(f)
1st word
MOVLB
MOVLW
MULLW
RETLW
SUBLW
XORLW
k
k
k
k
k
k
Move literal to BSR<3:0>
Move literal to WREG
Multiply literal with WREG
Return with literal in WREG
Subtract WREG from literal
Exclusive OR literal with WREG
1
1
1
2
1
1
DATA MEMORY ↔ PROGRAM MEMORY OPERATIONS
TBLRD*
Table Read
2
0000 0000 0000
0000 0000 0000
0000 0000 0000
0000 0000 0000
0000 0000 0000
0000 0000 0000
0000 0000 0000
0000 0000 0000
1000 None
1001 None
1010 None
1011 None
1100 None
1101 None
1110 None
1111 None
TBLRD*+
TBLRD*-
TBLRD+*
TBLWT*
TBLWT*+
TBLWT*-
TBLWT+*
Table Read with post-increment
Table Read with post-decrement
Table Read with pre-increment
Table Write
Table Write with post-increment
Table Write with post-decrement
Table Write with pre-increment
2
Note 1: When a Port register is modified as a function of itself (e.g., MOVF PORTB, 1, 0), the value used will be that value
present on the pins themselves. For example, if the data latch is ‘1’ for a pin configured as input and is driven low by an
external device, the data will be written back with a ‘0’.
2: If this instruction is executed on the TMR0 register (and where applicable, ‘d’ = 1), the prescaler will be cleared if
assigned.
3: If Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The second cycle is
executed as a NOP.
4: Some instructions are two-word instructions. The second word of these instructions will be executed as a NOPunless the
first word of the instruction retrieves the information embedded in these 16 bits. This ensures that all program memory
locations have a valid instruction.
DS39682C-page 246
Preliminary
© 2007 Microchip Technology Inc.
PIC18F45J10 FAMILY
21.1.1
STANDARD INSTRUCTION SET
ADDLW
ADD Literal to W
ADDWF
ADD W to f
Syntax:
ADDLW
k
Syntax:
ADDWF
f {,d {,a}}
Operands:
Operation:
Status Affected:
Encoding:
Description:
0 ≤ k ≤ 255
Operands:
0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
(W) + k → W
N, OV, C, DC, Z
Operation:
(W) + (f) → dest
0000
1111
kkkk
kkkk
Status Affected:
Encoding:
N, OV, C, DC, Z
The contents of W are added to the
8-bit literal ‘k’ and the result is placed in
W.
0010
01da
ffff
ffff
Description:
Add W to register ‘f’. If ‘d’ is ‘0’, the
result is stored in W. If ‘d’ is ‘1’, the
result is stored back in register ‘f’
(default).
Words:
Cycles:
1
1
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank (default).
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f ≤ 95 (5Fh). See
Section 21.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
literal ‘k’
Process
Data
Write to W
Example:
ADDLW
15h
Before Instruction
10h
After Instruction
25h
W
=
Words:
Cycles:
1
1
W
=
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
register ‘f’
Process
Data
Write to
destination
Example:
ADDWF
REG, 0, 0
Before Instruction
W
=
17h
REG
=
0C2h
After Instruction
W
REG
=
=
0D9h
0C2h
Note:
All PIC18 instructions may take an optional label argument preceding the instruction mnemonic for use in
symbolic addressing. If a label is used, the instruction format then becomes: {label} instruction argument(s).
© 2007 Microchip Technology Inc.
Preliminary
DS39682C-page 247
PIC18F45J10 FAMILY
ADDWFC
ADD W and Carry bit to f
ANDLW
AND Literal with W
Syntax:
ADDWFC
f {,d {,a}}
Syntax:
ANDLW
k
Operands:
0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
Operands:
Operation:
Status Affected:
Encoding:
Description:
0 ≤ k ≤ 255
(W) .AND. k → W
N, Z
Operation:
(W) + (f) + (C) → dest
0000
1011
kkkk
kkkk
Status Affected:
Encoding:
N,OV, C, DC, Z
The contents of W are ANDed with the
8-bit literal ‘k’. The result is placed in W.
0010
00da
ffff
ffff
Description:
Add W, the Carry flag and data memory
location ‘f’. If ‘d’ is ‘0’, the result is
placed in W. If ‘d’ is ‘1’, the result is
placed in data memory location ‘f’.
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank (default).
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f ≤ 95 (5Fh). See
Section 21.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
Words:
1
1
Cycles:
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read literal
‘k’
Process
Data
Write to W
Example:
ANDLW
05Fh
Before Instruction
W
=
A3h
03h
After Instruction
W
=
Words:
Cycles:
1
1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
register ‘f’
Process
Data
Write to
destination
Example:
ADDWFC
REG, 0, 1
Before Instruction
Carry bit
REG
W
=
=
=
1
02h
4Dh
After Instruction
Carry bit
REG
W
=
=
=
0
02h
50h
DS39682C-page 248
Preliminary
© 2007 Microchip Technology Inc.
PIC18F45J10 FAMILY
ANDWF
AND W with f
BC
Branch if Carry
Syntax:
ANDWF
f {,d {,a}}
Syntax:
BC
n
Operands:
0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
Operands:
Operation:
-128 ≤ n ≤ 127
if Carry bit is ‘1’
(PC) + 2 + 2n → PC
Operation:
(W) .AND. (f) → dest
Status Affected:
Encoding:
None
Status Affected:
Encoding:
N, Z
1110
0010
nnnn
nnnn
0001
01da
ffff
ffff
Description:
If the Carry bit is ‘1’, then the program
will branch.
Description:
The contents of W are ANDed with
register ‘f’. If ‘d’ is ‘0’, the result is stored
in W. If ‘d’ is ‘1’, the result is stored back
in register ‘f’ (default).
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank (default).
The 2’s complement number ‘2n’ is
added to the PC. Since the PC will have
incremented to fetch the next
instruction, the new address will be
PC + 2 + 2n. This instruction is then a
two-cycle instruction.
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f ≤ 95 (5Fh). See
Section 21.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
Words:
Cycles:
1
1(2)
Q Cycle Activity:
If Jump:
Q1
Q2
Q3
Q4
Decode
Read literal
‘n’
Process
Data
Write to PC
Words:
1
1
Cycles:
No
No
No
No
operation
operation
operation
operation
Q Cycle Activity:
Q1
If No Jump:
Q1
Q2
Q3
Q4
Q2
Q3
Q4
Decode
Read
register ‘f’
Process
Data
Write to
destination
Decode
Read literal
‘n’
Process
Data
No
operation
Example:
ANDWF
REG, 0, 0
Example:
HERE
BC
5
Before Instruction
Before Instruction
W
REG
=
=
17h
C2h
PC
=
address (HERE)
After Instruction
After Instruction
If Carry
PC
If Carry
PC
=
=
=
=
1;
address (HERE + 12)
0;
address (HERE + 2)
W
REG
=
=
02h
C2h
© 2007 Microchip Technology Inc.
Preliminary
DS39682C-page 249
PIC18F45J10 FAMILY
BCF
Bit Clear f
BN
Branch if Negative
Syntax:
BCF f, b {,a}
Syntax:
BN
n
Operands:
0 ≤ f ≤ 255
0 ≤ b ≤ 7
a ∈ [0,1]
Operands:
Operation:
-128 ≤ n ≤ 127
if Negative bit is ‘1’
(PC) + 2 + 2n → PC
Operation:
0 → f<b>
Status Affected:
Encoding:
None
Status Affected:
Encoding:
None
1110
0110
nnnn
nnnn
1001
bbba
ffff
ffff
Description:
If the Negative bit is ‘1’, then the
Description:
Bit ‘b’ in register ‘f’ is cleared.
program will branch.
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank (default).
The 2’s complement number ‘2n’ is
added to the PC. Since the PC will have
incremented to fetch the next
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f ≤ 95 (5Fh). See
Section 21.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
instruction, the new address will be
PC + 2 + 2n. This instruction is then a
two-cycle instruction.
Words:
Cycles:
1
1(2)
Q Cycle Activity:
If Jump:
Words:
Cycles:
1
1
Q1
Q2
Q3
Q4
Decode
Read literal
‘n’
Process
Data
Write to PC
Q Cycle Activity:
Q1
Q2
Q3
Q4
No
No
No
No
Decode
Read
register ‘f’
Process
Data
Write
register ‘f’
operation
operation
operation
operation
If No Jump:
Q1
Q2
Q3
Q4
Example:
BCF
FLAG_REG, 7, 0
C7h
47h
Decode
Read literal
‘n’
Process
Data
No
operation
Before Instruction
FLAG_REG =
After Instruction
FLAG_REG =
Example:
HERE
BN Jump
Before Instruction
PC
=
address (HERE)
After Instruction
If Negative
PC
If Negative
PC
=
=
=
=
1;
address (Jump)
0;
address (HERE + 2)
DS39682C-page 250
Preliminary
© 2007 Microchip Technology Inc.
PIC18F45J10 FAMILY
BNC
Branch if Not Carry
BNN
Branch if Not Negative
Syntax:
BNC
n
Syntax:
BNN
n
Operands:
Operation:
-128 ≤ n ≤ 127
Operands:
Operation:
-128 ≤ n ≤ 127
if Carry bit is ‘0’
(PC) + 2 + 2n → PC
if Negative bit is ‘0’
(PC) + 2 + 2n → PC
Status Affected:
Encoding:
None
Status Affected:
Encoding:
None
1110
0011
nnnn
nnnn
1110
0111
nnnn
nnnn
Description:
If the Carry bit is ‘0’, then the program
will branch.
Description:
If the Negative bit is ‘0’, then the
program will branch.
The 2’s complement number ‘2n’ is
added to the PC. Since the PC will have
incremented to fetch the next
instruction, the new address will be
PC + 2 + 2n. This instruction is then a
two-cycle instruction.
The 2’s complement number ‘2n’ is
added to the PC. Since the PC will have
incremented to fetch the next
instruction, the new address will be
PC + 2 + 2n. This instruction is then a
two-cycle instruction.
Words:
Cycles:
1
Words:
Cycles:
1
1(2)
1(2)
Q Cycle Activity:
If Jump:
Q Cycle Activity:
If Jump:
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Decode
Read literal
‘n’
Process
Data
Write to PC
Decode
Read literal
‘n’
Process
Data
Write to PC
No
No
No
No
No
No
No
No
operation
operation
operation
operation
operation
operation
operation
operation
If No Jump:
Q1
If No Jump:
Q1
Q2
Q3
Q4
Q2
Q3
Q4
Decode
Read literal
‘n’
Process
Data
No
operation
Decode
Read literal
‘n’
Process
Data
No
operation
Example:
HERE
BNC Jump
Example:
HERE
BNN Jump
Before Instruction
Before Instruction
PC
=
address (HERE)
PC
=
address (HERE)
After Instruction
After Instruction
If Carry
PC
If Carry
PC
=
=
=
=
0;
If Negative
PC
If Negative
PC
=
=
=
=
0;
address (Jump)
address (Jump)
1;
1;
address (HERE + 2)
address (HERE + 2)
© 2007 Microchip Technology Inc.
Preliminary
DS39682C-page 251
PIC18F45J10 FAMILY
BNOV
Branch if Not Overflow
BNZ
Branch if Not Zero
Syntax:
BNOV
n
Syntax:
BNZ
n
Operands:
Operation:
-128 ≤ n ≤ 127
Operands:
Operation:
-128 ≤ n ≤ 127
if Overflow bit is ‘0’
(PC) + 2 + 2n → PC
if Zero bit is ‘0’
(PC) + 2 + 2n → PC
Status Affected:
Encoding:
None
Status Affected:
Encoding:
None
1110
0101
nnnn
nnnn
1110
0001
nnnn
nnnn
Description:
If the Overflow bit is ‘0’, then the
program will branch.
Description:
If the Zero bit is ‘0’, then the program
will branch.
The 2’s complement number ‘2n’ is
added to the PC. Since the PC will have
incremented to fetch the next
instruction, the new address will be
PC + 2 + 2n. This instruction is then a
two-cycle instruction.
The 2’s complement number ‘2n’ is
added to the PC. Since the PC will have
incremented to fetch the next
instruction, the new address will be
PC + 2 + 2n. This instruction is then a
two-cycle instruction.
Words:
Cycles:
1
Words:
Cycles:
1
1(2)
1(2)
Q Cycle Activity:
If Jump:
Q Cycle Activity:
If Jump:
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Decode
Read literal
‘n’
Process
Data
Write to PC
Decode
Read literal
‘n’
Process
Data
Write to PC
No
No
No
No
No
No
No
No
operation
operation
operation
operation
operation
operation
operation
operation
If No Jump:
Q1
If No Jump:
Q1
Q2
Q3
Q4
Q2
Q3
Q4
Decode
Read literal
‘n’
Process
Data
No
operation
Decode
Read literal
‘n’
Process
Data
No
operation
Example:
HERE
BNOV Jump
Example:
HERE
BNZ Jump
Before Instruction
Before Instruction
PC
=
address (HERE)
PC
=
address (HERE)
After Instruction
After Instruction
If Overflow
PC
If Overflow
PC
=
=
=
=
0;
If Zero
PC
If Zero
PC
=
=
=
=
0;
address (Jump)
address (Jump)
1;
1;
address (HERE + 2)
address (HERE + 2)
DS39682C-page 252
Preliminary
© 2007 Microchip Technology Inc.
PIC18F45J10 FAMILY
BRA
Unconditional Branch
BSF
Bit Set f
Syntax:
BRA
n
Syntax:
BSF f, b {,a}
Operands:
Operation:
-1024 ≤ n ≤ 1023
Operands:
0 ≤ f ≤ 255
0 ≤ b ≤ 7
a ∈ [0,1]
(PC) + 2 + 2n → PC
Status Affected: None
Operation:
1 → f<b>
Encoding:
1101
0nnn
nnnn
nnnn
Status Affected:
Encoding:
None
Description:
Add the 2’s complement number ‘2n’ to
the PC. Since the PC will have
1000
bbba
ffff
ffff
incremented to fetch the next instruction,
the new address will be PC + 2 + 2n. This
instruction is a two-cycle instruction.
Description:
Bit ‘b’ in register ‘f’ is set.
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank (default).
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f ≤ 95 (5Fh). See
Section 21.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
Words:
Cycles:
1
2
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read literal
‘n’
Process
Data
Write to PC
No
operation
No
operation
No
operation
No
operation
Words:
Cycles:
1
1
Q Cycle Activity:
Q1
Example:
HERE
BRA Jump
Q2
Q3
Q4
Before Instruction
Decode
Read
register ‘f’
Process
Data
Write
register ‘f’
PC
=
=
address (HERE)
address (Jump)
After Instruction
PC
Example:
BSF
FLAG_REG, 7, 1
0Ah
8Ah
Before Instruction
FLAG_REG
After Instruction
FLAG_REG
=
=
© 2007 Microchip Technology Inc.
Preliminary
DS39682C-page 253
PIC18F45J10 FAMILY
BTFSC
Bit Test File, Skip if Clear
BTFSS
Bit Test File, Skip if Set
Syntax:
BTFSC f, b {,a}
Syntax:
BTFSS f, b {,a}
Operands:
0 ≤ f ≤ 255
0 ≤ b ≤ 7
a ∈ [0,1]
Operands:
0 ≤ f ≤ 255
0 ≤ b < 7
a ∈ [0,1]
Operation:
skip if (f<b>) = 0
Operation:
skip if (f<b>) = 1
Status Affected:
Encoding:
None
Status Affected:
Encoding:
None
1011
bbba
ffff
ffff
1010
bbba
ffff
ffff
Description:
If bit ‘b’ in register ‘f’ is ‘0’, then the next
instruction is skipped. If bit ‘b’ is ‘0’, then
the next instruction fetched during the
current instruction execution is discarded
and a NOPis executed instead, making
this a two-cycle instruction.
Description:
If bit ‘b’ in register ‘f’ is ‘1’, then the next
instruction is skipped. If bit ‘b’ is ‘1’, then
the next instruction fetched during the
current instruction execution is discarded
and a NOPis executed instead, making
this a two-cycle instruction.
If ‘a’ is ‘0’, the Access Bank is selected. If
‘a’ is ‘1’, the BSR is used to select the
GPR bank (default).
If ‘a’ is ‘0’, the Access Bank is selected. If
‘a’ is ‘1’, the BSR is used to select the
GPR bank (default).
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates in
Indexed Literal Offset Addressing
mode whenever f ≤ 95 (5Fh).
See Section 21.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f ≤ 95 (5Fh).
See Section 21.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
Words:
Cycles:
1
Words:
Cycles:
1
1(2)
1(2)
Note: 3 cycles if skip and followed
by a 2-word instruction.
Note: 3 cycles if skip and followed
by a 2-word instruction.
Q Cycle Activity:
Q1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Q2
Q3
Q4
Decode
Read
register ‘f’
Process
Data
No
operation
Decode
Read
register ‘f’
Process
Data
No
operation
If skip:
Q1
If skip:
Q1
Q2
Q3
Q4
Q2
Q3
Q4
No
No
No
No
No
No
No
No
operation
operation
operation
operation
operation
operation
operation
operation
If skip and followed by 2-word instruction:
If skip and followed by 2-word instruction:
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
No
No
No
No
No
No
No
No
operation
operation
operation
operation
operation
operation
operation
operation
No
No
No
No
No
No
No
No
operation
operation
operation
operation
operation
operation
operation
operation
Example:
HERE
FALSE
TRUE
BTFSC
:
:
FLAG, 1, 0
Example:
HERE
FALSE
TRUE
BTFSS
:
:
FLAG, 1, 0
Before Instruction
PC
Before Instruction
PC
=
address (HERE)
=
address (HERE)
After Instruction
After Instruction
If FLAG<1>
PC
If FLAG<1>
PC
=
=
=
=
0;
If FLAG<1>
PC
If FLAG<1>
PC
=
=
=
=
0;
address (TRUE)
1;
address (FALSE)
1;
address (FALSE)
address (TRUE)
DS39682C-page 254
Preliminary
© 2007 Microchip Technology Inc.
PIC18F45J10 FAMILY
BTG
Bit Toggle f
BOV
Branch if Overflow
Syntax:
BTG f, b {,a}
Syntax:
BOV
n
Operands:
0 ≤ f ≤ 255
0 ≤ b < 7
a ∈ [0,1]
Operands:
Operation:
-128 ≤ n ≤ 127
if Overflow bit is ‘1’
(PC) + 2 + 2n → PC
Operation:
(f<b>) → f<b>
Status Affected:
Encoding:
None
Status Affected:
Encoding:
None
1110
0100
nnnn
nnnn
0111
bbba
ffff
ffff
Description:
If the Overflow bit is ‘1’, then the
Description:
Bit ‘b’ in data memory location ‘f’ is
inverted.
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank (default).
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f ≤ 95 (5Fh). See
Section 21.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
program will branch.
The 2’s complement number ‘2n’ is
added to the PC. Since the PC will have
incremented to fetch the next
instruction, the new address will be
PC + 2 + 2n. This instruction is then a
two-cycle instruction.
Words:
Cycles:
1
1(2)
Q Cycle Activity:
If Jump:
Words:
Cycles:
1
1
Q1
Q2
Q3
Q4
Decode
Read literal
‘n’
Process
Data
Write to PC
Q Cycle Activity:
Q1
No
operation
No
operation
No
operation
No
operation
Q2
Q3
Q4
Decode
Read
register ‘f’
Process
Data
Write
register ‘f’
If No Jump:
Q1
Q2
Q3
Q4
Decode
Read literal
‘n’
Process
Data
No
operation
Example:
BTG
PORTC, 4, 0
Before Instruction:
PORTC
After Instruction:
PORTC
=
0111 0101 [75h]
0110 0101 [65h]
Example:
HERE
BOV Jump
Before Instruction
=
PC
=
address (HERE)
After Instruction
If Overflow
PC
If Overflow
PC
=
=
=
=
1;
address (Jump)
0;
address (HERE + 2)
© 2007 Microchip Technology Inc.
Preliminary
DS39682C-page 255
PIC18F45J10 FAMILY
BZ
Branch if Zero
CALL
Subroutine Call
Syntax:
BZ
n
Syntax:
CALL k {,s}
Operands:
Operation:
-128 ≤ n ≤ 127
Operands:
0 ≤ k ≤ 1048575
s ∈ [0,1]
if Zero bit is ‘1’
(PC) + 2 + 2n → PC
Operation:
(PC) + 4 → TOS,
k → PC<20:1>,
if s = 1
Status Affected:
Encoding:
None
1110
0000
nnnn
nnnn
(W) → WS,
(STATUS) → STATUSS,
(BSR) → BSRS
Description:
If the Zero bit is ‘1’, then the program
will branch.
The 2’s complement number ‘2n’ is
added to the PC. Since the PC will
have incremented to fetch the next
instruction, the new address will be
PC + 2 + 2n. This instruction is then a
two-cycle instruction.
Status Affected:
None
Encoding:
1st word (k<7:0>)
2nd word(k<19:8>)
1110
1111
110s
k kkk
kkkk
kkkk
7
0
8
k
kkk kkkk
19
Description:
Subroutine call of entire 2-Mbyte
memory range. First, return address
(PC + 4) is pushed onto the return
stack. If ‘s’ = 1, the W, STATUS and
Words:
Cycles:
1
1(2)
BSR registers are also pushed into their
respective shadow registers, WS,
STATUSS and BSRS. If ‘s’ = 0, no
update occurs (default). Then, the
20-bit value ‘k’ is loaded into PC<20:1>.
CALLis a two-cycle instruction.
Q Cycle Activity:
If Jump:
Q1
Q2
Q3
Q4
Decode
Read literal
‘n’
Process
Data
Write to PC
No
operation
No
operation
No
operation
No
operation
Words:
Cycles:
2
2
If No Jump:
Q1
Q2
Q3
Q4
Q Cycle Activity:
Q1
Decode
Read literal
‘n’
Process
Data
No
operation
Q2
Q3
Q4
Decode
Read literal PUSH PC to Read literal
‘k’<7:0>,
stack
‘k’<19:8>,
Write to PC
Example:
HERE
BZ Jump
No
operation
No
operation
No
operation
No
operation
Before Instruction
PC
=
address (HERE)
After Instruction
If Zero
PC
If Zero
PC
=
=
=
=
1;
Example:
HERE
CALL THERE, 1
address (Jump)
Before Instruction
PC
After Instruction
0;
address (HERE + 2)
=
address (HERE)
PC
TOS
WS
BSRS
STATUSS =
=
address (THERE)
=
=
=
address (HERE + 4)
W
BSR
STATUS
DS39682C-page 256
Preliminary
© 2007 Microchip Technology Inc.
PIC18F45J10 FAMILY
CLRF
Clear f
CLRWDT
Clear Watchdog Timer
Syntax:
CLRF f {,a}
Syntax:
CLRWDT
None
Operands:
0 ≤ f ≤ 255
a ∈ [0,1]
Operands:
Operation:
000h → WDT,
000h → WDT postscaler,
1 → TO,
Operation:
000h → f
1 → Z
1 → PD
Status Affected:
Encoding:
Z
Status Affected:
Encoding:
TO, PD
0110
101a
ffff
ffff
0000
0000
0000
0100
Description:
Clears the contents of the specified
register.
Description:
CLRWDTinstruction resets the
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank (default).
Watchdog Timer. It also resets the
postscaler of the WDT. Status bits, TO
and PD, are set.
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f ≤ 95 (5Fh). See
Section 21.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
Words:
Cycles:
1
1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
No
Process
Data
No
operation
operation
Words:
Cycles:
1
1
Example:
CLRWDT
Q Cycle Activity:
Q1
Before Instruction
Q2
Q3
Q4
WDT Counter
After Instruction
WDT Counter
WDT Postscaler
TO
=
?
Decode
Read
register ‘f’
Process
Data
Write
register ‘f’
=
=
=
=
00h
0
1
Example:
CLRF
FLAG_REG, 1
PD
1
Before Instruction
FLAG_REG
After Instruction
FLAG_REG
=
=
5Ah
00h
© 2007 Microchip Technology Inc.
Preliminary
DS39682C-page 257
PIC18F45J10 FAMILY
CPFSEQ
Compare f with W, Skip if f = W
COMF
Complement f
Syntax:
CPFSEQ f {,a}
Syntax:
COMF f {,d {,a}}
Operands:
0 ≤ f ≤ 255
a ∈ [0,1]
Operands:
0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
Operation:
(f) – (W),
skip if (f) = (W)
(unsigned comparison)
Operation:
(f) → dest
Status Affected:
Encoding:
N, Z
Status Affected:
Encoding:
None
0001
11da
ffff
ffff
0110
001a
ffff
ffff
Description:
The contents of register ‘f’ are
Description:
Compares the contents of data memory
location ‘f’ to the contents of W by
performing an unsigned subtraction.
If ‘f’ = W, then the fetched instruction is
discarded and a NOPis executed
instead, making this a two-cycle
instruction.
complemented. If ‘d’ is ‘0’, the result is
stored in W. If ‘d’ is ‘1’, the result is
stored back in register ‘f’ (default).
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank (default).
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f ≤ 95 (5Fh). See
Section 21.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank (default).
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f ≤ 95 (5Fh). See
Section 21.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
Words:
Cycles:
1
1
Q Cycle Activity:
Q1
Words:
Cycles:
1
Q2
Q3
Q4
1(2)
Decode
Read
register ‘f’
Process
Data
Write to
destination
Note: 3 cycles if skip and followed
by a 2-word instruction.
Q Cycle Activity:
Q1
Example:
COMF
REG, 0, 0
Q2
Q3
Q4
Before Instruction
Decode
Read
register ‘f’
Process
Data
No
operation
REG
=
13h
After Instruction
If skip:
REG
W
=
=
13h
ECh
Q1
No
Q2
No
Q3
No
Q4
No
operation
operation
operation
operation
If skip and followed by 2-word instruction:
Q1
No
Q2
No
Q3
No
Q4
No
operation
No
operation
No
operation
No
operation
No
operation
operation
operation
operation
Example:
HERE
CPFSEQ REG, 0
NEQUAL
EQUAL
:
:
Before Instruction
PC Address
=
HERE
W
REG
=
=
?
?
After Instruction
If REG
PC
=
=
W;
Address (EQUAL)
If REG
PC
≠
=
W;
Address (NEQUAL)
DS39682C-page 258
Preliminary
© 2007 Microchip Technology Inc.
PIC18F45J10 FAMILY
CPFSGT
Compare f with W, Skip if f > W
CPFSLT
Compare f with W, Skip if f < W
Syntax:
CPFSGT f {,a}
Syntax:
CPFSLT f {,a}
Operands:
0 ≤ f ≤ 255
a ∈ [0,1]
Operands:
0 ≤ f ≤ 255
a ∈ [0,1]
Operation:
(f) – (W),
skip if (f) > (W)
(unsigned comparison)
Operation:
(f) – (W),
skip if (f) < (W)
(unsigned comparison)
Status Affected:
Encoding:
None
Status Affected:
Encoding:
None
0110
010a
ffff
ffff
0110
000a
ffff
ffff
Description:
Compares the contents of data memory
location ‘f’ to the contents of the W by
performing an unsigned subtraction.
If the contents of ‘f’ are greater than the
contents of WREG, then the fetched
instruction is discarded and a NOPis
executed instead, making this a
Description:
Compares the contents of data memory
location ‘f’ to the contents of W by
performing an unsigned subtraction.
If the contents of ‘f’ are less than the
contents of W, then the fetched
instruction is discarded and a NOPis
executed instead, making this a
two-cycle instruction.
two-cycle instruction.
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank (default).
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f ≤ 95 (5Fh). See
Section 21.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank (default).
Words:
Cycles:
1
1(2)
Note: 3 cycles if skip and followed
by a 2-word instruction.
Q Cycle Activity:
Q1
Q2
Q3
Q4
Words:
Cycles:
1
Decode
Read
register ‘f’
Process
Data
No
operation
1(2)
Note: 3 cycles if skip and followed
by a 2-word instruction.
If skip:
Q1
Q2
Q3
Q4
Q Cycle Activity:
Q1
No
operation
No
operation
No
operation
No
operation
Q2
Q3
Q4
No
operation
Decode
Read
register ‘f’
Process
Data
If skip and followed by 2-word instruction:
If skip:
Q1
Q2
Q3
Q4
Q1
No
Q2
No
Q3
No
Q4
No
No
operation
No
operation
No
operation
No
operation
operation
operation
operation
operation
No
No
No
No
If skip and followed by 2-word instruction:
operation
operation
operation
operation
Q1
No
operation
No
Q2
No
operation
No
Q3
No
operation
No
Q4
No
operation
No
Example:
HERE
NLESS
LESS
CPFSLT REG, 1
:
:
operation
operation
operation
operation
Before Instruction
PC
W
=
=
Address (HERE)
Example:
HERE
NGREATER
GREATER
CPFSGT REG, 0
:
:
?
After Instruction
If REG
PC
If REG
PC
<
=
≥
=
W;
Address (LESS)
W;
Before Instruction
PC
W
=
=
Address (HERE)
Address (NLESS)
?
After Instruction
If REG
PC
>
=
W;
Address (GREATER)
If REG
PC
≤
=
W;
Address (NGREATER)
© 2007 Microchip Technology Inc.
Preliminary
DS39682C-page 259
PIC18F45J10 FAMILY
DAW
Decimal Adjust W Register
DECF
Decrement f
Syntax:
DAW
None
Syntax:
DECF f {,d {,a}}
Operands:
Operation:
Operands:
0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
If [W<3:0> > 9] or [DC = 1] then
(W<3:0>) + 6 → W<3:0>;
else
Operation:
(f) – 1 → dest
(W<3:0>) → W<3:0>
Status Affected:
Encoding:
C, DC, N, OV, Z
0000
01da
ffff
ffff
If [W<7:4> + DC > 9] or [C = 1] then
(W<7:4>) + 6 + DC → W<7:4> ;
else
Description:
Decrement register ‘f’. If ‘d’ is ‘0’, the
result is stored in W. If ‘d’ is ‘1’, the
result is stored back in register ‘f’
(default).
(W<7:4>) + DC → W<7:4>
Status Affected:
Encoding:
C
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank (default).
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f ≤ 95 (5Fh). See
Section 21.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
0000
0000
0000
0111
Description:
DAWadjusts the eight-bit value in W,
resulting from the earlier addition of two
variables (each in packed BCD format)
and produces a correct packed BCD
result.
Words:
Cycles:
1
1
Q Cycle Activity:
Q1
Words:
Cycles:
1
1
Q2
Q3
Q4
Decode
Read
register W
Process
Data
Write
W
Q Cycle Activity:
Q1
Q2
Q3
Q4
Example 1:
Decode
Read
register ‘f’
Process
Data
Write to
destination
DAW
Before Instruction
W
C
DC
=
=
=
A5h
0
0
Example:
DECF
CNT,
1, 0
Before Instruction
After Instruction
CNT
Z
After Instruction
=
01h
0
=
W
=
05h
1
0
C
DC
=
=
CNT
Z
=
=
00h
1
Example 2:
Before Instruction
W
=
CEh
C
DC
=
=
0
0
After Instruction
W
=
34h
C
DC
=
=
1
0
DS39682C-page 260
Preliminary
© 2007 Microchip Technology Inc.
PIC18F45J10 FAMILY
DECFSZ
Decrement f, Skip if 0
DCFSNZ
Decrement f, Skip if not 0
Syntax:
DECFSZ f {,d {,a}}
Syntax:
DCFSNZ f {,d {,a}}
Operands:
0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
Operands:
0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
Operation:
(f) – 1 → dest,
Operation:
(f) – 1 → dest,
skip if result = 0
skip if result ≠ 0
Status Affected:
Encoding:
None
Status Affected:
Encoding:
None
0010
11da
ffff
ffff
0100
11da
ffff
ffff
Description:
The contents of register ‘f’ are
Description:
The contents of register ‘f’ are
decremented. If ‘d’ is ‘0’, the result is
placed in W. If ‘d’ is ‘1’, the result is
placed back in register ‘f’ (default).
If the result is ‘0’, the next instruction,
which is already fetched, is discarded
and a NOPis executed instead, making
it a two-cycle instruction.
decremented. If ‘d’ is ‘0’, the result is
placed in W. If ‘d’ is ‘1’, the result is
placed back in register ‘f’ (default).
If the result is not ‘0’, the next
instruction, which is already fetched, is
discarded and a NOPis executed
instead, making it a two-cycle
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank (default).
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f ≤ 95 (5Fh). See
Section 21.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
instruction.
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank (default).
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f ≤ 95 (5Fh). See
Section 21.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
Words:
Cycles:
1
Words:
Cycles:
1
1(2)
Note: 3 cycles if skip and followed
by a 2-word instruction.
1(2)
Note: 3 cycles if skip and followed
by a 2-word instruction.
Q Cycle Activity:
Q1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Q2
Q3
Q4
Decode
Read
register ‘f’
Process
Data
Write to
destination
Decode
Read
Process
Data
Write to
destination
register ‘f’
If skip:
Q1
If skip:
Q1
Q2
Q3
Q4
Q2
Q3
Q4
No
No
No
No
operation
operation
operation
operation
No
No
No
No
operation
operation
operation
operation
If skip and followed by 2-word instruction:
If skip and followed by 2-word instruction:
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
No
No
No
No
operation
operation
operation
operation
No
No
No
No
operation
operation
operation
operation
No
No
No
No
operation
operation
operation
operation
No
No
No
No
operation
operation
operation
operation
Example:
HERE
DECFSZ
GOTO
CNT, 1, 1
LOOP
Example:
HERE
ZERO
NZERO
DCFSNZ TEMP, 1, 0
:
:
CONTINUE
Before Instruction
PC
After Instruction
Before Instruction
TEMP
After Instruction
=
Address (HERE)
=
?
CNT
=
CNT – 1
0;
If CNT
=
=
≠
=
TEMP
If TEMP
PC
If TEMP
PC
=
=
=
≠
=
TEMP – 1,
0;
Address (ZERO)
0;
Address (NZERO)
PC
Address (CONTINUE)
0;
If CNT
PC
Address (HERE + 2)
© 2007 Microchip Technology Inc.
Preliminary
DS39682C-page 261
PIC18F45J10 FAMILY
GOTO
Unconditional Branch
INCF
Increment f
Syntax:
GOTO
k
Syntax:
INCF f {,d {,a}}
Operands:
Operation:
Status Affected:
0 ≤ k ≤ 1048575
k → PC<20:1>
None
Operands:
0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
Operation:
(f) + 1 → dest
Encoding:
1st word (k<7:0>)
2nd word(k<19:8>)
Status Affected:
Encoding:
C, DC, N, OV, Z
1110
1111
1111
kkk
k kkk
kkkk
kkkk
kkkk
7
0
8
k
0010
10da
ffff
ffff
19
Description:
GOTOallows an unconditional branch
anywhere within entire
2-Mbyte memory range. The 20-bit
value ‘k’ is loaded into PC<20:1>. GOTO
is always a two-cycle instruction.
Description:
The contents of register ‘f’ are
incremented. If ‘d’ is ‘0’, the result is
placed in W. If ‘d’ is ‘1’, the result is
placed back in register ‘f’ (default).
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank (default).
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f ≤ 95 (5Fh). See
Section 21.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
Words:
Cycles:
2
2
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read literal
‘k’<7:0>,
No
operation
Read literal
‘k’<19:8>,
Write to PC
No
operation
No
operation
No
operation
No
operation
Words:
Cycles:
1
1
Q Cycle Activity:
Q1
Example:
GOTO THERE
Q2
Q3
Q4
After Instruction
Decode
Read
register ‘f’
Process
Data
Write to
destination
PC
=
Address (THERE)
Example:
INCF
CNT, 1, 0
Before Instruction
CNT
Z
=
FFh
0
=
=
=
C
?
DC
?
After Instruction
CNT
Z
=
00h
1
=
=
=
C
1
DC
1
DS39682C-page 262
Preliminary
© 2007 Microchip Technology Inc.
PIC18F45J10 FAMILY
INFSNZ
Increment f, Skip if not 0
INCFSZ
Increment f, Skip if 0
Syntax:
INFSNZ f {,d {,a}}
Syntax:
INCFSZ f {,d {,a}}
Operands:
0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
Operands:
0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
Operation:
(f) + 1 → dest,
skip if result ≠ 0
Operation:
(f) + 1 → dest,
skip if result = 0
Status Affected:
Encoding:
None
Status Affected:
Encoding:
None
0100
10da
ffff
ffff
0011
11da
ffff
ffff
Description:
The contents of register ‘f’ are
Description:
The contents of register ‘f’ are
incremented. If ‘d’ is ‘0’, the result is
placed in W. If ‘d’ is ‘1’, the result is
placed back in register ‘f’ (default).
If the result is not ‘0’, the next
instruction, which is already fetched, is
discarded and a NOPis executed
instead, making it a two-cycle
incremented. If ‘d’ is ‘0’, the result is
placed in W. If ‘d’ is ‘1’, the result is
placed back in register ‘f’ (default).
If the result is ‘0’, the next instruction,
which is already fetched, is discarded
and a NOPis executed instead, making
it a two-cycle instruction.
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank (default).
instruction.
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank (default).
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f ≤ 95 (5Fh). See
Section 21.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f ≤ 95 (5Fh). See
Section 21.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
Words:
Cycles:
1
Words:
Cycles:
1
1(2)
1(2)
Note: 3 cycles if skip and followed
by a 2-word instruction.
Note: 3 cycles if skip and followed
by a 2-word instruction.
Q Cycle Activity:
Q1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Q2
Q3
Q4
Decode
Read
register ‘f’
Process
Data
Write to
destination
Decode
Read
register ‘f’
Process
Data
Write to
destination
If skip:
Q1
If skip:
Q1
Q2
Q3
Q4
Q2
Q3
Q4
No
No
No
No
No
No
No
No
operation
operation
operation
operation
operation
operation
operation
operation
If skip and followed by 2-word instruction:
If skip and followed by 2-word instruction:
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
No
No
No
No
No
No
No
No
operation
operation
operation
operation
operation
operation
operation
operation
No
No
No
No
No
No
No
No
operation
operation
operation
operation
operation
operation
operation
operation
Example:
HERE
NZERO
ZERO
INCFSZ
:
:
CNT, 1, 0
Example:
HERE
ZERO
NZERO
INFSNZ REG, 1, 0
Before Instruction
PC
After Instruction
Before Instruction
PC
After Instruction
=
Address (HERE)
=
Address (HERE)
REG
If REG
PC
If REG
PC
=
REG + 1
0;
Address (NZERO)
0;
Address (ZERO)
CNT
If CNT
PC
If CNT
PC
=
CNT + 1
≠
=
=
=
=
=
≠
=
0;
Address (ZERO)
0;
Address (NZERO)
© 2007 Microchip Technology Inc.
Preliminary
DS39682C-page 263
PIC18F45J10 FAMILY
IORLW
Inclusive OR Literal with W
IORWF
Inclusive OR W with f
Syntax:
IORLW
k
Syntax:
IORWF f {,d {,a}}
Operands:
Operation:
Status Affected:
Encoding:
Description:
0 ≤ k ≤ 255
(W) .OR. k → W
N, Z
Operands:
0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
Operation:
(W) .OR. (f) → dest
0000
1001
kkkk
kkkk
Status Affected:
Encoding:
N, Z
The contents of W are ORed with the
eight-bit literal ‘k’. The result is placed in
W.
0001
00da
ffff
ffff
Description:
Inclusive OR W with register ‘f’. If ‘d’ is
‘0’, the result is placed in W. If ‘d’ is ‘1’,
the result is placed back in register ‘f’
(default).
Words:
Cycles:
1
1
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank (default).
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f ≤ 95 (5Fh). See
Section 21.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
literal ‘k’
Process
Data
Write to W
Example:
IORLW
35h
Before Instruction
W
=
9Ah
BFh
After Instruction
Words:
Cycles:
1
1
W
=
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
register ‘f’
Process
Data
Write to
destination
Example:
IORWF RESULT, 0, 1
Before Instruction
RESULT =
13h
91h
W
=
After Instruction
RESULT =
13h
93h
W
=
DS39682C-page 264
Preliminary
© 2007 Microchip Technology Inc.
PIC18F45J10 FAMILY
LFSR
Load FSR
MOVF
Move f
Syntax:
LFSR f, k
Syntax:
MOVF f {,d {,a}}
Operands:
0 ≤ f ≤ 2
0 ≤ k ≤ 4095
Operands:
0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
Operation:
k → FSRf
Operation:
f → dest
Status Affected:
Encoding:
None
Status Affected:
Encoding:
N, Z
1110
1111
1110
0000
00ff
k kkk
k kkk
11
kkkk
0101
00da
ffff
ffff
7
Description:
The 12-bit literal ‘k’ is loaded into the
File Select Register pointed to by ‘f’.
Description:
The contents of register ‘f’ are moved to
a destination dependent upon the
status of ‘d’. If ‘d’ is ‘0’, the result is
placed in W. If ‘d’ is ‘1’, the result is
placed back in register ‘f’ (default).
Location ‘f’ can be anywhere in the
256-byte bank.
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank (default).
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f ≤ 95 (5Fh). See
Section 21.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
Words:
Cycles:
2
2
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read literal
‘k’ MSB
Process
Data
Write
literal ‘k’
MSB to
FSRfH
Decode
Read literal
‘k’ LSB
Process
Data
Write literal
‘k’ to FSRfL
Example:
LFSR 2, 3ABh
After Instruction
Words:
Cycles:
1
1
FSR2H
FSR2L
=
=
03h
ABh
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
register ‘f’
Process
Data
Write W
Example:
MOVF
REG, 0, 0
Before Instruction
REG
W
=
=
22h
FFh
After Instruction
REG
W
=
=
22h
22h
© 2007 Microchip Technology Inc.
Preliminary
DS39682C-page 265
PIC18F45J10 FAMILY
MOVFF
Move f to f
MOVLB
Move Literal to Low Nibble in BSR
Syntax:
MOVFF f ,f
Syntax:
MOVLW k
s
d
Operands:
0 ≤ f ≤ 4095
Operands:
Operation:
Status Affected:
Encoding:
Description:
0 ≤ k ≤ 255
k → BSR
None
s
0 ≤ f ≤ 4095
d
Operation:
(f ) → f
s
d
Status Affected:
None
0000
0001
kkkk
kkkk
Encoding:
1st word (source)
2nd word (destin.)
The eight-bit literal ‘k’ is loaded into the
Bank Select Register (BSR). The value
of BSR<7:4> always remains ‘0’,
1100
1111
ffff
ffff
ffff
ffff
ffffs
ffffd
Description:
The contents of source register ‘f ’ are
regardless of the value of k :k .
7 4
s
moved to destination register ‘f ’.
d
Words:
Cycles:
1
1
Location of source ‘f ’ can be anywhere
s
in the 4096-byte data space (000h to
FFFh) and location of destination ‘f ’
can also be anywhere from 000h to
FFFh.
Either source or destination can be W
(a useful special situation).
d
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
literal ‘k’
Process
Data
Write literal
‘k’ to BSR
MOVFFis particularly useful for
transferring a data memory location to a
peripheral register (such as the transmit
buffer or an I/O port).
The MOVFFinstruction cannot use the
PCL, TOSU, TOSH or TOSL as the
destination register.
Example:
MOVLB
5
Before Instruction
BSR Register =
After Instruction
BSR Register =
02h
05h
Words:
Cycles:
2
2 (3)
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
register ‘f’
(src)
Process
Data
No
operation
Decode
No
operation
No
operation
Write
register ‘f’
(dest)
No dummy
read
Example:
MOVFF
REG1, REG2
Before Instruction
REG1
REG2
=
=
33h
11h
After Instruction
REG1
REG2
=
=
33h
33h
DS39682C-page 266
Preliminary
© 2007 Microchip Technology Inc.
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MOVLW
Move Literal to W
MOVWF
Move W to f
Syntax:
MOVLW
k
Syntax:
MOVWF f {,a}
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
0 ≤ k ≤ 255
k → W
None
Operands:
0 ≤ f ≤ 255
a ∈ [0,1]
Operation:
(W) → f
Status Affected:
Encoding:
None
0000
1110
kkkk
kkkk
0110
111a
ffff
ffff
The eight-bit literal ‘k’ is loaded into W.
Description:
Move data from W to register ‘f’.
Location ‘f’ can be anywhere in the
256-byte bank.
1
1
Cycles:
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank (default).
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f ≤ 95 (5Fh). See
Section 21.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
literal ‘k’
Process
Data
Write to W
Example:
MOVLW
5Ah
After Instruction
W
=
5Ah
Words:
Cycles:
1
1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
register ‘f’
Process
Data
Write
register ‘f’
Example:
MOVWF
REG, 0
Before Instruction
W
REG
=
=
4Fh
FFh
After Instruction
W
REG
=
=
4Fh
4Fh
© 2007 Microchip Technology Inc.
Preliminary
DS39682C-page 267
PIC18F45J10 FAMILY
MULLW
Multiply Literal with W
MULWF
Multiply W with f
Syntax:
MULLW
k
Syntax:
MULWF f {,a}
Operands:
Operation:
Status Affected:
Encoding:
Description:
0 ≤ k ≤ 255
Operands:
0 ≤ f ≤ 255
a ∈ [0,1]
(W) x k → PRODH:PRODL
Operation:
(W) x (f) → PRODH:PRODL
None
Status Affected:
Encoding:
None
0000
1101
kkkk
kkkk
0000
001a
ffff
ffff
An unsigned multiplication is carried
out between the contents of W and the
8-bit literal ‘k’. The 16-bit result is
placed in the PRODH:PRODL register
pair. PRODH contains the high byte.
W is unchanged.
None of the Status flags are affected.
Note that neither overflow nor carry is
possible in this operation. A zero result
is possible but not detected.
Description:
An unsigned multiplication is carried
out between the contents of W and the
register file location ‘f’. The 16-bit
result is stored in the PRODH:PRODL
register pair. PRODH contains the
high byte. Both W and ‘f’ are
unchanged.
None of the Status flags are affected.
Note that neither overflow nor carry is
possible in this operation. A zero
result is possible but not detected.
If ‘a’ is ‘0’, the Access Bank is
selected. If ‘a’ is ‘1’, the BSR is used
to select the GPR bank (default).
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction
operates in Indexed Literal Offset
Addressing mode whenever
Words:
Cycles:
1
1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
literal ‘k’
Process
Data
Write
registers
PRODH:
PRODL
f ≤ 95 (5Fh). See Section 21.2.3
“Byte-Oriented and Bit-Oriented
Instructions in Indexed Literal Offset
Mode” for details.
Example:
MULLW
0C4h
Before Instruction
Words:
Cycles:
1
1
W
PRODH
PRODL
=
=
=
E2h
?
?
Q Cycle Activity:
Q1
After Instruction
Q2
Q3
Q4
W
PRODH
PRODL
=
=
=
E2h
ADh
08h
Decode
Read
register ‘f’
Process
Data
Write
registers
PRODH:
PRODL
Example:
MULWF
REG, 1
Before Instruction
W
REG
PRODH
PRODL
=
C4h
B5h
?
?
=
=
=
After Instruction
W
=
C4h
REG
PRODH
PRODL
=
=
=
B5h
8Ah
94h
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Preliminary
© 2007 Microchip Technology Inc.
PIC18F45J10 FAMILY
NEGF
Negate f
NOP
No Operation
Syntax:
NEGF f {,a}
Syntax:
NOP
Operands:
0 ≤ f ≤ 255
a ∈ [0,1]
Operands:
Operation:
Status Affected:
Encoding:
None
No operation
None
Operation:
( f ) + 1→ f
Status Affected:
Encoding:
N, OV, C, DC, Z
0000
1111
0000
xxxx
0000
xxxx
0000
xxxx
0110
110a
ffff
ffff
Description:
Location ‘f’ is negated using two’s
complement. The result is placed in the
data memory location ‘f’.
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank (default).
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f ≤ 95 (5Fh). See
Section 21.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
Description:
Words:
No operation.
1
1
Cycles:
Q Cycle Activity:
Q1
Q2
Q3
No
Q4
Decode
No
operation
No
operation
operation
Example:
None.
Words:
Cycles:
1
1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
register ‘f’
Process
Data
Write
register ‘f’
Example:
NEGF
REG, 1
Before Instruction
REG
After Instruction
REG
=
0011 1010 [3Ah]
1100 0110 [C6h]
=
© 2007 Microchip Technology Inc.
Preliminary
DS39682C-page 269
PIC18F45J10 FAMILY
POP
Pop Top of Return Stack
PUSH
Push Top of Return Stack
Syntax:
POP
Syntax:
PUSH
Operands:
Operation:
Status Affected:
Encoding:
Description:
None
Operands:
Operation:
Status Affected:
Encoding:
Description:
None
(TOS) → bit bucket
(PC + 2) → TOS
None
None
0000
0000
0000
0110
0000
0000
0000
0101
The TOS value is pulled off the return
stack and is discarded. The TOS value
then becomes the previous value that
was pushed onto the return stack.
This instruction is provided to enable
the user to properly manage the return
stack to incorporate a software stack.
The PC + 2 is pushed onto the top of
the return stack. The previous TOS
value is pushed down on the stack.
This instruction allows implementing a
software stack by modifying TOS and
then pushing it onto the return stack.
Words:
Cycles:
1
1
Words:
Cycles:
1
1
Q Cycle Activity:
Q1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Q2
Q3
Q4
Decode
PUSH
No
No
Decode
No
operation
POP TOS
value
No
operation
PC + 2 onto
return stack
operation
operation
Example:
POP
Example:
PUSH
GOTO
NEW
Before Instruction
Before Instruction
TOS
Stack (1 level down)
TOS
PC
=
=
345Ah
0124h
=
=
0031A2h
014332h
After Instruction
After Instruction
PC
=
=
=
0126h
0126h
345Ah
TOS
TOS
PC
=
=
014332h
NEW
Stack (1 level down)
DS39682C-page 270
Preliminary
© 2007 Microchip Technology Inc.
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RCALL
Relative Call
RESET
Reset
Syntax:
RCALL
n
Syntax:
RESET
None
Operands:
Operation:
-1024 ≤ n ≤ 1023
Operands:
Operation:
(PC) + 2 → TOS,
(PC) + 2 + 2n → PC
Reset all registers and flags that are
affected by a MCLR Reset.
Status Affected:
Encoding:
None
Status Affected:
Encoding:
All
1101
1nnn
nnnn
nnnn
0000
0000
1111
1111
Description:
Subroutine call with a jump up to 1K
from the current location. First, return
address (PC + 2) is pushed onto the
stack. Then, add the 2’s complement
number ‘2n’ to the PC. Since the PC will
have incremented to fetch the next
instruction, the new address will be
PC + 2 + 2n. This instruction is a
two-cycle instruction.
Description:
This instruction provides a way to
execute a MCLR Reset in software.
Words:
Cycles:
1
1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Start
No
No
Reset
operation
operation
Words:
Cycles:
1
2
Example:
RESET
Q Cycle Activity:
Q1
After Instruction
Registers =
Q2
Q3
Q4
Reset Value
Reset Value
Flags*
=
Decode
Read literal
‘n’
Process
Data
Write to PC
PUSH PCto
stack
No
No
No
No
operation
operation
operation
operation
Example:
HERE
RCALL Jump
Before Instruction
PC
After Instruction
PC
TOS =
=
Address (HERE)
=
Address (Jump)
Address (HERE + 2)
© 2007 Microchip Technology Inc.
Preliminary
DS39682C-page 271
PIC18F45J10 FAMILY
RETFIE
Return from Interrupt
RETLW
Return Literal to W
Syntax:
RETFIE {s}
Syntax:
RETLW k
Operands:
Operation:
s ∈ [0,1]
Operands:
Operation:
0 ≤ k ≤ 255
(TOS) → PC,
k → W,
1 → GIE/GIEH or PEIE/GIEL,
if s = 1
(TOS) → PC,
PCLATU, PCLATH are unchanged
(WS) → W;
(STATUSS) → STATUS;
(BSRS) → BSR;
Status Affected:
Encoding:
None
0000
1100
kkkk
kkkk
PCLATU, PCLATH are unchanged
Description:
W is loaded with the eight-bit literal ‘k’.
The program counter is loaded from the
top of the stack (the return address).
The high address latch (PCLATH)
remains unchanged.
Status Affected:
Encoding:
GIE/GIEH, PEIE/GIEL.
0000
0000
0001
000s
Description:
Return from interrupt. Stack is popped
and Top-of-Stack (TOS) is loaded into
the PC. Interrupts are enabled by
setting either the high or low priority
global interrupt enable bit. If ‘s’ = 1, the
contents of the shadow registers, WS,
STATUSS and BSRS, are loaded into
their corresponding registers, W,
Words:
Cycles:
1
2
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
literal ‘k’
Process
Data
POP PC
from stack,
Write to W
STATUS and BSR. If ‘s’ = 0, no update
of these registers occurs (default).
No
operation
No
operation
No
operation
No
operation
Words:
Cycles:
1
2
Q Cycle Activity:
Q1
Example:
Q2
Q3
Q4
CALL TABLE ; W contains table
; offset value
Decode
No
operation
No
operation
POP PC
from stack
; W now has
; table value
Set GIEH or
GIEL
:
No
operation
No
operation
No
operation
No
operation
TABLE
ADDWF PCL ; W = offset
RETLW k0
RETLW k1
:
; Begin table
;
Example:
RETFIE
1
After Interrupt
:
PC
=
=
=
=
=
TOS
WS
RETLW kn
; End of table
W
BSR
STATUS
BSRS
STATUSS
1
Before Instruction
GIE/GIEH, PEIE/GIEL
W
=
07h
After Instruction
W
=
value of kn
DS39682C-page 272
Preliminary
© 2007 Microchip Technology Inc.
PIC18F45J10 FAMILY
RETURN
Return from Subroutine
RLCF
Rotate Left f through Carry
Syntax:
RETURN {s}
Syntax:
RLCF f {,d {,a}}
Operands:
Operation:
s ∈ [0,1]
Operands:
0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
(TOS) → PC,
if s = 1
(WS) → W;
Operation:
(f<n>) → dest<n + 1>,
(f<7>) → C,
(C) → dest<0>
(STATUSS) → STATUS;
(BSRS) → BSR;
PCLATU, PCLATH are unchanged
Status Affected:
Encoding:
C, N, Z
Status Affected:
Encoding:
None
0011
01da
ffff
ffff
0000
0000
0001
001s
Description:
The contents of register ‘f’ are rotated
one bit to the left through the Carry
flag. If ‘d’ is ‘0’, the result is placed in
W. If ‘d’ is ‘1’, the result is stored back
in register ‘f’ (default).
If ‘a’ is ‘0’, the Access Bank is
selected. If ‘a’ is ‘1’, the BSR is used to
select the GPR bank (default).
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction
operates in Indexed Literal Offset
Addressing mode whenever
Description:
Return from subroutine. The stack is
popped and the top of the stack (TOS)
is loaded into the program counter. If
‘s’= 1, the contents of the shadow
registers, WS, STATUSS and BSRS,
are loaded into their corresponding
registers, W, STATUS and BSR. If
‘s’ = 0, no update of these registers
occurs (default).
Words:
Cycles:
1
2
f ≤ 95 (5Fh). See Section 21.2.3
“Byte-Oriented and Bit-Oriented
Instructions in Indexed Literal Offset
Mode” for details.
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
No
operation
Process
Data
POP PC
from stack
register f
C
No
No
No
No
Words:
Cycles:
1
1
operation
operation
operation
operation
Q Cycle Activity:
Q1
Example:
RETURN
Q2
Q3
Q4
After Instruction:
PC = TOS
Decode
Read
register ‘f’
Process
Data
Write to
destination
Example:
RLCF
REG, 0, 0
Before Instruction
REG
C
=
=
1110 0110
0
After Instruction
REG
W
C
=
=
=
1110 0110
1100 1100
1
© 2007 Microchip Technology Inc.
Preliminary
DS39682C-page 273
PIC18F45J10 FAMILY
RLNCF
Rotate Left f (No Carry)
RRCF
Rotate Right f through Carry
Syntax:
RLNCF f {,d {,a}}
Syntax:
RRCF f {,d {,a}}
Operands:
0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
Operands:
0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
Operation:
(f<n>) → dest<n + 1>,
(f<7>) → dest<0>
Operation:
(f<n>) → dest<n – 1>,
(f<0>) → C,
(C) → dest<7>
Status Affected:
Encoding:
N, Z
Status Affected:
Encoding:
C, N, Z
0100
01da
ffff
ffff
0011
00da
ffff
ffff
Description:
The contents of register ‘f’ are rotated
one bit to the left. If ‘d’ is ‘0’, the result
is placed in W. If ‘d’ is ‘1’, the result is
stored back in register ‘f’ (default).
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank (default).
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f ≤ 95 (5Fh). See
Section 21.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
Description:
The contents of register ‘f’ are rotated
one bit to the right through the Carry
flag. If ‘d’ is ‘0’, the result is placed in W.
If ‘d’ is ‘1’, the result is placed back in
register ‘f’ (default).
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank (default).
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f ≤ 95 (5Fh). See
Section 21.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
register f
register f
C
Words:
Cycles:
1
1
Words:
Cycles:
1
1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Q Cycle Activity:
Q1
Decode
Read
register ‘f’
Process
Data
Write to
destination
Q2
Q3
Q4
Decode
Read
register ‘f’
Process
Data
Write to
destination
Example:
RLNCF
REG, 1, 0
Before Instruction
REG
After Instruction
Example:
RRCF
REG, 0, 0
=
1010 1011
0101 0111
Before Instruction
REG
=
REG
C
=
=
1110 0110
0
After Instruction
REG
W
C
=
=
=
1110 0110
0111 0011
0
DS39682C-page 274
Preliminary
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PIC18F45J10 FAMILY
RRNCF
Rotate Right f (No Carry)
SETF
Set f
Syntax:
RRNCF f {,d {,a}}
Syntax:
SETF f {,a}
Operands:
0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
Operands:
0 ≤ f ≤ 255
a ∈ [0,1]
Operation:
FFh → f
Operation:
(f<n>) → dest<n – 1>,
(f<0>) → dest<7>
Status Affected:
Encoding:
None
0110
100a
ffff
ffff
Status Affected:
Encoding:
N, Z
Description:
The contents of the specified register
are set to FFh.
0100
00da
ffff
ffff
Description:
The contents of register ‘f’ are rotated
one bit to the right. If ‘d’ is ‘0’, the result
is placed in W. If ‘d’ is ‘1’, the result is
placed back in register ‘f’ (default).
If ‘a’ is ‘0’, the Access Bank will be
selected, overriding the BSR value. If ‘a’
is ‘1’, then the bank will be selected as
per the BSR value (default).
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f ≤ 95 (5Fh). See
Section 21.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank (default).
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f ≤ 95 (5Fh). See
Section 21.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
Words:
Cycles:
1
1
Q Cycle Activity:
Q1
Q2
Q3
Q4
register f
Decode
Read
register ‘f’
Process
Data
Write
register ‘f’
Words:
Cycles:
1
1
Example:
SETF
REG, 1
Q Cycle Activity:
Q1
Before Instruction
REG
After Instruction
REG
=
=
5Ah
FFh
Q2
Q3
Q4
Decode
Read
register ‘f’
Process
Data
Write to
destination
Example 1:
RRNCF
REG, 1, 0
Before Instruction
REG
After Instruction
REG
=
1101 0111
1110 1011
RRNCF REG, 0, 0
=
Example 2:
Before Instruction
W
REG
=
=
?
1101 0111
After Instruction
W
REG
=
=
1110 1011
1101 0111
© 2007 Microchip Technology Inc.
Preliminary
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PIC18F45J10 FAMILY
SLEEP
Enter Sleep mode
SUBFWB
Subtract f from W with Borrow
Syntax:
SLEEP
None
Syntax:
SUBFWB f {,d {,a}}
Operands:
Operation:
Operands:
0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
00h → WDT,
0 → WDT postscaler,
1 → TO,
Operation:
(W) – (f) – (C) → dest
0 → PD
Status Affected:
Encoding:
N, OV, C, DC, Z
Status Affected:
Encoding:
TO, PD
0101
01da
ffff
ffff
0000
0000
0000
0011
Description:
Subtract register ‘f’ and Carry flag
(borrow) from W (2’s complement
method). If ‘d’ is ‘0’, the result is stored
in W. If ‘d’ is ‘1’, the result is stored in
register ‘f’ (default).
Description:
The Power-Down status bit (PD) is
cleared. The Time-out status bit (TO)
is set. Watchdog Timer and its
postscaler are cleared.
The processor is put into Sleep mode
with the oscillator stopped.
If ‘a’ is ‘0’, the Access Bank is
selected. If ‘a’ is ‘1’, the BSR is used
to select the GPR bank (default).
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction
operates in Indexed Literal Offset
Addressing mode whenever
f ≤ 95 (5Fh). See Section 21.2.3
“Byte-Oriented and Bit-Oriented
Instructions in Indexed Literal Offset
Mode” for details.
Words:
Cycles:
1
1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
No
operation
Process
Data
Go to
Sleep
Example:
SLEEP
Words:
Cycles:
1
1
Before Instruction
TO
PD
=
=
?
?
Q Cycle Activity:
Q1
Q2
Q3
Q4
After Instruction
Decode
Read
register ‘f’
Process
Data
Write to
destination
TO
PD
=
=
1 †
0
Example 1:
SUBFWB
REG, 1, 0
†
If WDT causes wake-up, this bit is cleared.
Before Instruction
REG
W
C
=
=
=
3
2
1
After Instruction
REG
W
C
=
FF
2
=
=
=
=
0
Z
0
1
N
; result is negative
Example 2:
Before Instruction
SUBFWB
REG, 0, 0
REG
W
=
=
=
2
5
1
C
After Instruction
REG
W
C
=
2
3
1
0
=
=
=
=
Z
N
0
; result is positive
Example 3:
Before Instruction
SUBFWB
REG, 1, 0
REG
W
=
=
=
1
2
0
C
After Instruction
REG
W
C
=
0
2
1
1
0
=
=
=
=
Z
; result is zero
N
DS39682C-page 276
Preliminary
© 2007 Microchip Technology Inc.
PIC18F45J10 FAMILY
SUBLW
Subtract W from Literal
SUBWF
Subtract W from f
Syntax:
SUBLW
k
Syntax:
SUBWF f {,d {,a}}
Operands:
Operation:
Status Affected:
Encoding:
Description
0 ≤ k ≤ 255
Operands:
0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
k – (W) → W
N, OV, C, DC, Z
Operation:
(f) – (W) → dest
0000
1000
kkkk
kkkk
Status Affected:
Encoding:
N, OV, C, DC, Z
W is subtracted from the eight-bit
literal ‘k’. The result is placed in W.
0101
11da
ffff
ffff
Description:
Subtract W from register ‘f’ (2’s
complement method). If ‘d’ is ‘0’, the
result is stored in W. If ‘d’ is ‘1’, the
result is stored back in register ‘f’
(default).
Words:
1
1
Cycles:
Q Cycle Activity:
Q1
Q2
Q3
Q4
If ‘a’ is ‘0’, the Access Bank is
selected. If ‘a’ is ‘1’, the BSR is used
to select the GPR bank (default).
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction
operates in Indexed Literal Offset
Addressing mode whenever
f ≤ 95 (5Fh). See Section 21.2.3
“Byte-Oriented and Bit-Oriented
Instructions in Indexed Literal Offset
Mode” for details.
Decode
Read
literal ‘k’
Process
Data
Write to W
Example 1:
SUBLW 02h
Before Instruction
W
C
=
=
01h
?
After Instruction
W
C
Z
=
01h
=
=
=
1
0
0
; result is positive
N
Words:
Cycles:
1
1
Example 2:
SUBLW 02h
Before Instruction
Q Cycle Activity:
Q1
W
C
=
=
02h
?
Q2
Q3
Q4
After Instruction
Decode
Read
register ‘f’
Process
Data
Write to
destination
W
C
Z
=
00h
=
=
=
1
1
0
; result is zero
N
Example 1:
SUBWF
REG, 1, 0
Before Instruction
Example 3:
Before Instruction
SUBLW 02h
REG
W
C
=
3
2
?
=
=
W
C
=
=
03h
?
After Instruction
After Instruction
REG
W
C
=
1
2
1
0
0
W
C
Z
=
FFh ; (2’s complement)
=
=
=
=
=
=
=
0
0
1
; result is negative
; result is positive
Z
N
N
Example 2:
SUBWF
REG, 0, 0
Before Instruction
REG
W
=
=
=
2
2
?
C
After Instruction
REG
W
C
=
2
0
1
1
0
=
=
=
=
; result is zero
Z
N
Example 3:
Before Instruction
SUBWF
REG, 1, 0
REG
W
=
=
=
1
2
?
C
After Instruction
REG
W
C
=
FFh ;(2’s complement)
2
0
0
1
=
=
=
=
; result is negative
Z
N
© 2007 Microchip Technology Inc.
Preliminary
DS39682C-page 277
PIC18F45J10 FAMILY
SUBWFB
Subtract W from f with Borrow
SWAPF
Swap f
Syntax:
SUBWFB f {,d {,a}}
Syntax:
SWAPF f {,d {,a}}
Operands:
0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
Operands:
0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
Operation:
(f) – (W) – (C) → dest
Operation:
(f<3:0>) → dest<7:4>,
(f<7:4>) → dest<3:0>
Status Affected:
Encoding:
N, OV, C, DC, Z
0101
10da
ffff
ffff
Status Affected:
Encoding:
None
Description:
Subtract W and the Carry flag (borrow)
from register ‘f’ (2’s complement
method). If ‘d’ is ‘0’, the result is stored
in W. If ‘d’ is ‘1’, the result is stored back
in register ‘f’ (default).
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank (default).
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f ≤ 95 (5Fh). See
Section 21.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
0011
10da
ffff
ffff
Description:
The upper and lower nibbles of register
‘f’ are exchanged. If ‘d’ is ‘0’, the result
is placed in W. If ‘d’ is ‘1’, the result is
placed in register ‘f’ (default).
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank (default).
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f ≤ 95 (5Fh). See
Section 21.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
Words:
Cycles:
1
1
Words:
1
1
Cycles:
Q Cycle Activity:
Q1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Q2
Q3
Q4
Decode
Read
register ‘f’
Process
Data
Write to
destination
Decode
Read
register ‘f’
Process
Data
Write to
destination
Example 1:
SUBWFB REG, 1, 0
Before Instruction
REG
W
=
=
=
19h
0Dh
1
(0001 1001)
(0000 1101)
Example:
SWAPF
REG, 1, 0
C
Before Instruction
After Instruction
REG
After Instruction
=
53h
35h
REG
W
=
0Ch
0Dh
1
(0000 1011)
(0000 1101)
=
=
=
=
REG
=
C
Z
0
N
0
; result is positive
Example 2:
Before Instruction
SUBWFB REG, 0, 0
REG
=
=
=
1Bh
1Ah
0
(0001 1011)
(0001 1010)
W
C
After Instruction
REG
W
C
=
1Bh
00h
1
(0001 1011)
=
=
=
=
Z
1
; result is zero
N
0
Example 3:
SUBWFB REG, 1, 0
Before Instruction
REG
W
=
=
=
03h
0Eh
1
(0000 0011)
(0000 1101)
C
After Instruction
REG
=
F5h
(1111 0100)
; [2’s comp]
W
=
=
=
=
0Eh
0
0
1
(0000 1101)
C
Z
N
; result is negative
DS39682C-page 278
Preliminary
© 2007 Microchip Technology Inc.
PIC18F45J10 FAMILY
TBLRD
Table Read
TBLRD
Table Read (Continued)
Syntax:
TBLRD ( *; *+; *-; +*)
None
Example 1:
TBLRD *+ ;
Operands:
Operation:
Before Instruction
TABLAT
TBLPTR
MEMORY (00A356h)
=
=
=
55h
00A356h
34h
if TBLRD *,
(Prog Mem (TBLPTR)) → TABLAT;
TBLPTR – No Change
if TBLRD *+,
(Prog Mem (TBLPTR)) → TABLAT;
(TBLPTR) + 1→ TBLPTR
if TBLRD *-,
(Prog Mem (TBLPTR)) → TABLAT;
(TBLPTR) – 1→ TBLPTR
if TBLRD +*,
(TBLPTR) + 1→ TBLPTR;
(Prog Mem (TBLPTR)) → TABLAT
After Instruction
TABLAT
TBLPTR
=
=
34h
00A357h
Example 2:
TBLRD +* ;
Before Instruction
TABLAT
TBLPTR
MEMORY (01A357h)
MEMORY (01A358h)
After Instruction
=
=
=
=
AAh
01A357h
12h
34h
TABLAT
TBLPTR
=
=
34h
01A358h
Status Affected: None
Encoding:
0000
0000
0000
10nn
nn=0 *
=1 *+
=2 *-
=3 +*
Description:
This instruction is used to read the contents
of Program Memory (P.M.). To address the
program memory, a pointer called Table
Pointer (TBLPTR) is used.
The TBLPTR (a 21-bit pointer) points to
each byte in the program memory. TBLPTR
has a 2-Mbyte address range.
TBLPTR[0] = 0: LeastSignificantByte
of Program Memory
Word
TBLPTR[0] = 1: Most Significant Byte
of Program Memory
Word
The TBLRDinstruction can modify the value
of TBLPTR as follows:
•
•
•
•
no change
post-increment
post-decrement
pre-increment
Words:
Cycles:
1
2
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
No
No
No
operation
operation
operation
No
No operation
No
No operation
operation (Read Program operation (Write TABLAT)
Memory)
© 2007 Microchip Technology Inc.
Preliminary
DS39682C-page 279
PIC18F45J10 FAMILY
TBLWT
Table Write
TBLWT
Table Write (Continued)
Syntax:
TBLWT ( *; *+; *-; +*)
None
Example 1:
TBLWT *+;
Operands:
Operation:
Before Instruction
if TBLWT *,
TABLAT
TBLPTR
HOLDING REGISTER
(00A356h)
=
=
55h
00A356h
(TABLAT) → Holding Register;
TBLPTR – No Change
if TBLWT *+,
(TABLAT) → Holding Register;
(TBLPTR) + 1→ TBLPTR
if TBLWT *-,
(TABLAT) → Holding Register;
(TBLPTR) – 1→ TBLPTR
if TBLWT +*,
(TBLPTR) + 1→ TBLPTR;
(TABLAT) → Holding Register
=
FFh
After Instructions (table write completion)
TABLAT
TBLPTR
HOLDING REGISTER
(00A356h)
=
=
55h
00A357h
=
55h
Example 2:
TBLWT +*;
Before Instruction
TABLAT
TBLPTR
HOLDING REGISTER
(01389Ah)
HOLDING REGISTER
(01389Bh)
=
=
34h
01389Ah
Status Affected: None
=
FFh
Encoding:
0000
0000
0000
11nn
nn=0 *
=1 *+
=2 *-
=3 +*
=
FFh
After Instruction (table write completion)
TABLAT
TBLPTR
HOLDING REGISTER
(01389Ah)
HOLDING REGISTER
(01389Bh)
=
=
34h
01389Bh
Description:
This instruction uses the 3 LSBs of
TBLPTR to determine which of the
8 holding registers the TABLAT is written
to. The holding registers are used to
program the contents of Program
Memory (P.M.). (Refer to Section 6.0
“Flash Program Memory” for additional
details on programming Flash memory.)
The TBLPTR (a 21-bit pointer) points to
each byte in the program memory.
TBLPTR has a 2-MByte address range.
The LSb of the TBLPTR selects which
byte of the program memory location to
access.
=
=
FFh
34h
TBLPTR[0] = 0: Least Significant
Byte of Program
Memory Word
TBLPTR[0] = 1: Most Significant
Byte of Program
Memory Word
The TBLWT instruction can modify the
value of TBLPTR as follows:
•
•
•
•
no change
post-increment
post-decrement
pre-increment
Words:
1
2
Cycles:
Q Cycle Activity:
Q1
Q2
No
Q3
No
Q4
No
Decode
operation operation operation
No
No No No
operation operation operation operation
(Read
TABLAT)
(Write to
Holding
Register )
DS39682C-page 280
Preliminary
© 2007 Microchip Technology Inc.
PIC18F45J10 FAMILY
TSTFSZ
Test f, Skip if 0
XORLW
Exclusive OR Literal with W
Syntax:
TSTFSZ f {,a}
Syntax:
XORLW k
Operands:
0 ≤ f ≤ 255
a ∈ [0,1]
Operands:
Operation:
Status Affected:
Encoding:
Description:
0 ≤ k ≤ 255
(W) .XOR. k → W
N, Z
Operation:
skip if f = 0
Status Affected:
Encoding:
None
0000
1010
kkkk
kkkk
0110
011a
ffff
ffff
The contents of W are XORed with
the 8-bit literal ‘k’. The result is placed
in W.
Description:
If ‘f’ = 0, the next instruction fetched
during the current instruction execution
is discarded and a NOPis executed,
making this a two-cycle instruction.
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank (default).
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f ≤ 95 (5Fh). See
Section 21.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
Words:
1
1
Cycles:
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
literal ‘k’
Process
Data
Write to W
Example:
XORLW
0AFh
Before Instruction
W
=
B5h
1Ah
Words:
Cycles:
1
After Instruction
1(2)
W
=
Note: 3 cycles if skip and followed
by a 2-word instruction.
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
register ‘f’
Process
Data
No
operation
If skip:
Q1
Q2
Q3
Q4
No
No
No
No
operation
operation
operation
operation
If skip and followed by 2-word instruction:
Q1
Q2
Q3
Q4
No
No
No
No
operation
operation
operation
operation
No
No
No
No
operation
operation
operation
operation
Example:
HERE
NZERO
ZERO
TSTFSZ CNT, 1
:
:
Before Instruction
PC
=
Address (HERE)
After Instruction
If CNT
PC
If CNT
PC
=
=
≠
=
00h,
Address (ZERO)
00h,
Address (NZERO)
© 2007 Microchip Technology Inc.
Preliminary
DS39682C-page 281
PIC18F45J10 FAMILY
XORWF
Exclusive OR W with f
Syntax:
XORWF f {,d {,a}}
Operands:
0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
Operation:
(W) .XOR. (f) → dest
Status Affected:
Encoding:
N, Z
0001
10da
ffff
ffff
Description:
Exclusive OR the contents of W with
register ‘f’. If ‘d’ is ‘0’, the result is stored
in W. If ‘d’ is ‘1’, the result is stored back
in the register ‘f’ (default).
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank (default).
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f ≤ 95 (5Fh). See
Section 21.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
Words:
1
1
Cycles:
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
register ‘f’
Process
Data
Write to
destination
Example:
XORWF
REG, 1, 0
Before Instruction
REG
W
=
=
AFh
B5h
After Instruction
REG
W
=
=
1Ah
B5h
DS39682C-page 282
Preliminary
© 2007 Microchip Technology Inc.
PIC18F45J10 FAMILY
A summary of the instructions in the extended instruc-
tion set is provided in Table 21-3. Detailed descriptions
are provided in Section 21.2.2 “Extended Instruction
Set”. The opcode field descriptions in Table 21-1
(page 242) apply to both the standard and extended
PIC18 instruction sets.
21.2 Extended Instruction Set
In addition to the standard 75 instructions of the PIC18
instruction set, PIC18F45J10 family devices also
provide an optional extension to the core CPU function-
ality. The added features include eight additional
instructions that augment indirect and indexed
addressing operations and the implementation of
Indexed Literal Offset Addressing mode for many of the
standard PIC18 instructions.
Note:
The instruction set extension and the
Indexed Literal Offset Addressing mode
were designed for optimizing applications
written in C; the user may likely never use
these instructions directly in assembler.
The syntax for these commands is pro-
vided as a reference for users who may be
reviewing code that has been generated
by a compiler.
The additional features of the extended instruction set
are disabled by default. To enable them, users must set
the XINST configuration bit.
The instructions in the extended set can all be
classified as literal operations, which either manipulate
the File Select Registers, or use them for indexed
addressing. Two of the instructions, ADDFSR and
SUBFSR, each have an additional special instantiation
for using FSR2. These versions (ADDULNK and
SUBULNK) allow for automatic return after execution.
21.2.1
EXTENDED INSTRUCTION SYNTAX
Most of the extended instructions use indexed argu-
ments, using one of the File Select Registers and some
offset to specify a source or destination register. When
an argument for an instruction serves as part of
indexed addressing, it is enclosed in square brackets
(“[ ]”). This is done to indicate that the argument is used
as an index or offset. MPASM™ Assembler will flag an
error if it determines that an index or offset value is not
bracketed.
The extended instructions are specifically implemented
to optimize re-entrant program code (that is, code that
is recursive or that uses a software stack) written in
high-level languages, particularly C. Among other
things, they allow users working in high-level
languages to perform certain operations on data
structures more efficiently. These include:
When the extended instruction set is enabled, brackets
are also used to indicate index arguments in byte-
oriented and bit-oriented instructions. This is in addition
to other changes in their syntax. For more details, see
Section 21.2.3.1 “Extended Instruction Syntax with
Standard PIC18 Commands”.
• dynamic allocation and deallocation of software
stack space when entering and leaving
subroutines
• function pointer invocation
• software stack pointer manipulation
• manipulation of variables located in a software
stack
Note:
In the past, square brackets have been
used to denote optional arguments in the
PIC18 and earlier instruction sets. In this
text and going forward, optional
arguments are denoted by braces (“{ }”).
TABLE 21-3: EXTENSIONS TO THE PIC18 INSTRUCTION SET
16-Bit Instruction Word
MSb LSb
Mnemonic,
Operands
Status
Affected
Description
Cycles
ADDFSR
ADDULNK
CALLW
f, k
k
Add literal to FSR
Add literal to FSR2 and return
Call subroutine using WREG
1
2
2
2
1110 1000 ffkk kkkk
1110 1000 11kk kkkk
0000 0000 0001 0100
1110 1011 0zzz zzzz
1111 ffff ffff ffff
1110 1011 1zzz zzzz
1111 xxxx xzzz zzzz
1110 1010 kkkk kkkk
None
None
None
None
MOVSF
zs, fd Move zs (source) to 1st word
fd (destination) 2nd word
zs, zd Move zs (source) to 1st word
MOVSS
PUSHL
2
1
None
None
zd (destination)
Store literal at FSR2,
decrement FSR2
2nd word
k
SUBFSR
SUBULNK
f, k
k
Subtract literal from FSR
Subtract literal from FSR2 and
return
1
2
1110 1001 ffkk kkkk
1110 1001 11kk kkkk
None
None
© 2007 Microchip Technology Inc.
Preliminary
DS39682C-page 283
PIC18F45J10 FAMILY
21.2.2
EXTENDED INSTRUCTION SET
ADDFSR
Add Literal to FSR
ADDULNK
Add Literal to FSR2 and Return
Syntax:
ADDFSR f, k
Syntax:
ADDULNK k
Operands:
0 ≤ k ≤ 63
f ∈ [ 0, 1, 2 ]
FSR(f) + k → FSR(f)
None
Operands:
Operation:
0 ≤ k ≤ 63
FSR2 + k → FSR2,
(TOS) → PC
None
Operation:
Status Affected:
Encoding:
Status Affected:
Encoding:
1110
1000
ffkk
kkkk
1110
1000
11kk
kkkk
Description:
The 6-bit literal ‘k’ is added to the
contents of the FSR specified by ‘f’.
Description:
The 6-bit literal ‘k’ is added to the
contents of FSR2. A RETURNis then
executed by loading the PC with the
TOS.
Words:
1
1
Cycles:
The instruction takes two cycles to
execute; a NOPis performed during
the second cycle.
This may be thought of as a special
case of the ADDFSRinstruction,
where f = 3 (binary ‘11’); it operates
only on FSR2.
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
literal ‘k’
Process
Data
Write to
FSR
Example:
ADDFSR 2, 23h
Words:
Cycles:
1
2
Before Instruction
FSR2
After Instruction
FSR2
=
03FFh
0422h
Q Cycle Activity:
Q1
=
Q2
Q3
Q4
Decode
Read
literal ‘k’
Process
Data
Write to
FSR
No
No
No
No
Operation
Operation
Operation
Operation
Example:
ADDULNK 23h
Before Instruction
FSR2
PC
=
=
03FFh
0100h
After Instruction
FSR2
PC
=
=
0422h
(TOS)
Note:
All PIC18 instructions may take an optional label argument preceding the instruction mnemonic for use in
symbolic addressing. If a label is used, the instruction syntax then becomes: {label} instruction argument(s).
DS39682C-page 284
Preliminary
© 2007 Microchip Technology Inc.
PIC18F45J10 FAMILY
CALLW
Subroutine Call Using WREG
MOVSF
Move Indexed to f
Syntax:
CALLW
None
Syntax:
MOVSF [z ], f
s
d
Operands:
Operation:
Operands:
0 ≤ z ≤ 127
s
0 ≤ f ≤ 4095
d
(PC + 2) → TOS,
(W) → PCL,
Operation:
((FSR2) + z ) → f
s
d
(PCLATH) → PCH,
(PCLATU) → PCU
Status Affected:
None
Encoding:
1st word (source)
2nd word (destin.)
Status Affected:
Encoding:
None
1110
1111
1011
ffff
0zzz
ffff
zzzz
ffff
s
0000
0000
0001
0100
d
Description
First, the return address (PC + 2) is
pushed onto the return stack. Next, the
contents of W are written to PCL; the
existing value is discarded. Then, the
contents of PCLATH and PCLATU are
latched into PCH and PCU,
respectively. The second cycle is
executed as a NOPinstruction while the
new next instruction is fetched.
Description:
The contents of the source register are
moved to destination register ‘f ’. The
d
actual address of the source register is
determined by adding the 7-bit literal
offset ‘z ’ in the first word to the value of
s
FSR2. The address of the destination
register is specified by the 12-bit literal
‘f ’ in the second word. Both addresses
d
can be anywhere in the 4096-byte data
space (000h to FFFh).
The MOVSFinstruction cannot use the
PCL, TOSU, TOSH or TOSL as the
destination register.
If the resultant source address points to
an indirect addressing register, the
value returned will be 00h.
Unlike CALL, there is no option to
update W, STATUS or BSR.
Words:
Cycles:
1
2
Q Cycle Activity:
Q1
Q2
Q3
Q4
Words:
Cycles:
2
2
Decode
Read
WREG
PUSH PC to
stack
No
operation
No
operation
No
operation
No
operation
No
operation
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Determine
Determine
Read
source addr source addr source reg
Example:
HERE
CALLW
Decode
No
operation
No
operation
Write
register ‘f’
(dest)
Before Instruction
PC
=
address (HERE)
PCLATH =
PCLATU =
10h
00h
06h
No dummy
read
W
=
After Instruction
PC
TOS
=
=
001006h
address (HERE + 2)
Example:
MOVSF
[05h], REG2
PCLATH =
PCLATU =
10h
00h
06h
Before Instruction
FSR2
=
80h
33h
W
=
Contents
of 85h
REG2
=
=
11h
After Instruction
FSR2
=
80h
Contents
of 85h
REG2
=
=
33h
33h
© 2007 Microchip Technology Inc.
Preliminary
DS39682C-page 285
PIC18F45J10 FAMILY
MOVSS
Move Indexed to Indexed
PUSHL
Store Literal at FSR2, Decrement FSR2
Syntax:
MOVSS [z ], [z ]
Syntax:
PUSHL k
s
d
Operands:
0 ≤ z ≤ 127
s
Operands:
Operation:
0 ≤ k ≤ 255
0 ≤ z ≤ 127
d
k → (FSR2),
FSR2 – 1→ FSR2
Operation:
((FSR2) + z ) → ((FSR2) + z )
s d
Status Affected:
None
Status Affected: None
Encoding:
1st word (source)
2nd word (dest.)
Encoding:
1111
1010
kkkk
kkkk
1110
1111
1011
xxxx
1zzz
xzzz
zzzz
zzzz
s
d
Description:
The 8-bit literal ‘k’ is written to the data
memory address specified by FSR2. FSR2
is decremented by 1 after the operation.
This instruction allows users to push values
onto a software stack.
Description
The contents of the source register are
moved to the destination register. The
addresses of the source and destination
registers are determined by adding the
7-bit literal offsets ‘z ’ or ‘z ’,
Words:
Cycles:
1
1
s
d
respectively, to the value of FSR2. Both
registers can be located anywhere in
the 4096-byte data memory space
(000h to FFFh).
Q Cycle Activity:
Q1
Q2
Q3
Q4
The MOVSSinstruction cannot use the
PCL, TOSU, TOSH or TOSL as the
destination register.
Decode
Read ‘k’
Process
data
Write to
destination
If the resultant source address points to
an indirect addressing register, the
value returned will be 00h. If the
resultant destination address points to
an indirect addressing register, the
instruction will execute as a NOP.
Example:
PUSHL 08h
Before Instruction
FSR2H:FSR2L
Memory (01ECh)
=
=
01ECh
00h
Words:
2
2
After Instruction
FSR2H:FSR2L
Memory (01ECh)
=
=
01EBh
08h
Cycles:
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Determine
Determine
Read
source addr source addr source reg
Decode
Determine
dest addr
Determine
dest addr
Write
to dest reg
Example:
MOVSS [05h], [06h]
Before Instruction
FSR2
=
=
=
80h
33h
11h
Contents
of 85h
Contents
of 86h
After Instruction
FSR2
=
=
=
80h
33h
33h
Contents
of 85h
Contents
of 86h
DS39682C-page 286
Preliminary
© 2007 Microchip Technology Inc.
PIC18F45J10 FAMILY
SUBFSR
Subtract Literal from FSR
SUBULNK
Subtract Literal from FSR2 and Return
Syntax:
SUBFSR f, k
0 ≤ k ≤ 63
f ∈ [ 0, 1, 2 ]
FSR(f) – k → FSRf
None
Syntax:
SUBULNK k
Operands:
Operands:
Operation:
0 ≤ k ≤ 63
FSR2 – k → FSR2
(TOS) → PC
Operation:
Status Affected:
Encoding:
Status Affected: None
1110
1001
ffkk
kkkk
Encoding:
1110
1001
11kk
kkkk
Description:
The 6-bit literal ‘k’ is subtracted from
the contents of the FSR specified by
‘f’.
Description:
The 6-bit literal ‘k’ is subtracted from the
contents of the FSR2. A RETURNis then
executed by loading the PC with the TOS.
The instruction takes two cycles to
execute; a NOPis performed during the
second cycle.
This may be thought of as a special case of
the SUBFSRinstruction, where f = 3 (binary
‘11’); it operates only on FSR2.
Words:
1
1
Cycles:
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
register ‘f’
Process
Data
Write to
destination
Words:
1
2
Cycles:
Q Cycle Activity:
Q1
Example:
SUBFSR 2, 23h
03FFh
Q2
Q3
Q4
Before Instruction
FSR2
After Instruction
FSR2
Decode
Read
register ‘f’
Process
Data
Write to
destination
=
No
Operation
No
Operation
No
Operation
No
Operation
=
03DCh
Example:
SUBULNK 23h
Before Instruction
FSR2
PC
=
=
03FFh
0100h
After Instruction
FSR2
PC
=
=
03DCh
(TOS)
© 2007 Microchip Technology Inc.
Preliminary
DS39682C-page 287
PIC18F45J10 FAMILY
21.2.3
BYTE-ORIENTED AND
BIT-ORIENTED INSTRUCTIONS IN
INDEXED LITERAL OFFSET MODE
21.2.3.1
Extended Instruction Syntax with
Standard PIC18 Commands
When the extended instruction set is enabled, the file
register argument, ‘f’, in the standard byte-oriented and
bit-oriented commands is replaced with the literal offset
value, ‘k’. As already noted, this occurs only when ‘f’ is
less than or equal to 5Fh. When an offset value is used,
it must be indicated by square brackets (“[ ]”). As with
the extended instructions, the use of brackets indicates
to the compiler that the value is to be interpreted as an
index or an offset. Omitting the brackets, or using a
value greater than 5Fh within brackets, will generate an
error in the MPASM Assembler.
Note: Enabling the PIC18 instruction set
extension may cause legacy applications
to behave erratically or fail entirely.
In addition to eight new commands in the extended set,
enabling the extended instruction set also enables
Indexed Literal Offset Addressing mode (Section 5.5.1
“Indexed Addressing with Literal Offset”). This has
a significant impact on the way that many commands of
the standard PIC18 instruction set are interpreted.
When the extended set is disabled, addresses embed-
ded in opcodes are treated as literal memory locations:
either as a location in the Access Bank (‘a’ = 0), or in a
GPR bank designated by the BSR (‘a’ = 1). When the
extended instruction set is enabled and ‘a’ = 0, how-
ever, a file register argument of 5Fh or less is
interpreted as an offset from the pointer value in FSR2
and not as a literal address. For practical purposes, this
means that all instructions that use the Access RAM bit
as an argument – that is, all byte-oriented and bit-
oriented instructions, or almost half of the core PIC18
instructions – may behave differently when the
extended instruction set is enabled.
If the index argument is properly bracketed for Indexed
Literal Offset Addressing, the Access RAM argument is
never specified; it will automatically be assumed to be
‘0’. This is in contrast to standard operation (extended
instruction set disabled) when ‘a’ is set on the basis of
the target address. Declaring the Access RAM bit in
this mode will also generate an error in the MPASM
Assembler.
The destination argument, ‘d’, functions as before.
Refer to the MPLAB® IDE, MPASM™ or MPLAB C18
documentation for information on enabling Extended
Instruction set support
When the content of FSR2 is 00h, the boundaries of the
Access RAM are essentially remapped to their original
values. This may be useful in creating backward
compatible code. If this technique is used, it may be
necessary to save the value of FSR2 and restore it
when moving back and forth between C and assembly
routines in order to preserve the stack pointer. Users
must also keep in mind the syntax requirements of the
extended instruction set (see Section 21.2.3.1
“Extended Instruction Syntax with Standard PIC18
Commands”).
21.2.4
CONSIDERATIONS WHEN
ENABLING THE EXTENDED
INSTRUCTION SET
It is important to note that the extensions to the instruc-
tion set may not be beneficial to all users. In particular,
users who are not writing code that uses a software
stack may not benefit from using the extensions to the
instruction set.
Additionally, the Indexed Literal Offset Addressing
mode may create issues with legacy applications
written to the PIC18 assembler. This is because
instructions in the legacy code may attempt to address
registers in the Access Bank below 5Fh. Since these
addresses are interpreted as literal offsets to FSR2
when the instruction set extension is enabled, the
application may read or write to the wrong data
addresses.
Although the Indexed Literal Offset Addressing mode
can be very useful for dynamic stack and pointer
manipulation, it can also be very annoying if a simple
arithmetic operation is carried out on the wrong
register. Users who are accustomed to the PIC18 pro-
gramming must keep in mind that, when the extended
instruction set is enabled, register addresses of 5Fh or
less are used for Indexed Literal Offset Addressing.
When porting an application to the PIC18F45J10
family, it is very important to consider the type of code.
A large, re-entrant application that is written in ‘C’ and
would benefit from efficient compilation will do well
when using the instruction set extensions. Legacy
applications that heavily use the Access Bank will most
likely not benefit from using the extended instruction
set.
Representative examples of typical byte-oriented and
bit-oriented instructions in the Indexed Literal Offset
Addressing mode are provided on the following page to
show how execution is affected. The operand condi-
tions shown in the examples are applicable to all
instructions of these types.
DS39682C-page 288
Preliminary
© 2007 Microchip Technology Inc.
PIC18F45J10 FAMILY
ADD W to Indexed
(Indexed Literal Offset mode)
Bit Set Indexed
BSF
ADDWF
(Indexed Literal Offset mode)
Syntax:
ADDWF
[k] {,d}
Syntax:
BSF [k], b
Operands:
0 ≤ k ≤ 95
d ∈ [0,1]
Operands:
0 ≤ f ≤ 95
0 ≤ b ≤ 7
Operation:
(W) + ((FSR2) + k) → dest
Operation:
1 → ((FSR2) + k)<b>
Status Affected:
Encoding:
N, OV, C, DC, Z
Status Affected:
Encoding:
None
0010
01d0
kkkk
kkkk
1000
bbb0
kkkk
kkkk
Description:
The contents of W are added to the
contents of the register indicated by
FSR2, offset by the value ‘k’.
If ‘d’ is ‘0’, the result is stored in W. If ‘d’
is ‘1’, the result is stored back in
register ‘f’ (default).
Description:
Bit ‘b’ of the register indicated by FSR2,
offset by the value ‘k’, is set.
Words:
1
1
Cycles:
Q Cycle Activity:
Q1
Words:
Cycles:
1
1
Q2
Q3
Q4
Decode
Read
register ‘f’
Process
Data
Write to
destination
Q Cycle Activity:
Q1
Q2
Q3
Q4
Example:
BSF
[FLAG_OFST], 7
Decode
Read ‘k’
Process
Data
Write to
destination
Before Instruction
FLAG_OFST
FSR2
Contents
of 0A0Ah
=
=
0Ah
0A00h
Example:
ADDWF
[OFST], 0
=
55h
D5h
Before Instruction
After Instruction
W
OFST
FSR2
=
=
=
17h
2Ch
0A00h
Contents
of 0A0Ah
=
Contents
of 0A2Ch
=
20h
After Instruction
W
=
=
37h
20h
Set Indexed
(Indexed Literal Offset mode)
Contents
of 0A2Ch
SETF
Syntax:
SETF [k]
Operands:
Operation:
Status Affected:
Encoding:
Description:
0 ≤ k ≤ 95
FFh → ((FSR2) + k)
None
0110
1000
kkkk
kkkk
The contents of the register indicated by
FSR2, offset by ‘k’, are set to FFh.
Words:
Cycles:
1
1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read ‘k’
Process
Data
Write
register
Example:
SETF
[OFST]
2Ch
Before Instruction
OFST
=
=
FSR2
0A00h
Contents
of 0A2Ch
=
00h
After Instruction
Contents
of 0A2Ch
=
FFh
© 2007 Microchip Technology Inc.
Preliminary
DS39682C-page 289
PIC18F45J10 FAMILY
To develop software for the extended instruction set,
the user must enable support for the instructions and
the Indexed Addressing mode in their language tool(s).
Depending on the environment being used, this may be
done in several ways:
21.2.5
SPECIAL CONSIDERATIONS WITH
MICROCHIP MPLAB® IDE TOOLS
The latest versions of Microchip’s software tools have
been designed to fully support the extended instruction
set of the PIC18F45J10 family of devices. This includes
the MPLAB C18 C compiler, MPASM assembly lan-
guage and MPLAB Integrated Development
Environment (IDE).
• A menu option, or dialog box within the
environment, that allows the user to configure the
language tool and its settings for the project
• A command line option
When selecting
a
target device for software
• A directive in the source code
development, MPLAB IDE will automatically set default
configuration bits for that device. The default setting for
the XINST configuration bit is ‘0’, disabling the
extended instruction set and Indexed Literal Offset
Addressing mode. For proper execution of applications
developed to take advantage of the extended
instruction set, XINST must be set during
programming.
These options vary between different compilers,
assemblers and development environments. Users are
encouraged to review the documentation accompany-
ing their development systems for the appropriate
information.
DS39682C-page 290
Preliminary
© 2007 Microchip Technology Inc.
PIC18F45J10 FAMILY
22.1 MPLAB Integrated Development
Environment Software
22.0 DEVELOPMENT SUPPORT
The PIC® microcontrollers are supported with a full
range of hardware and software development tools:
The MPLAB IDE software brings an ease of software
development previously unseen in the 8/16-bit micro-
controller market. The MPLAB IDE is a Windows®
operating system-based application that contains:
• Integrated Development Environment
- MPLAB® IDE Software
• Assemblers/Compilers/Linkers
- MPASMTM Assembler
• A single graphical interface to all debugging tools
- Simulator
- MPLAB C18 and MPLAB C30 C Compilers
- MPLINKTM Object Linker/
MPLIBTM Object Librarian
- Programmer (sold separately)
- Emulator (sold separately)
- In-Circuit Debugger (sold separately)
• A full-featured editor with color-coded context
• A multiple project manager
- MPLAB ASM30 Assembler/Linker/Library
• Simulators
- MPLAB SIM Software Simulator
• Emulators
• Customizable data windows with direct edit of
contents
- MPLAB ICE 2000 In-Circuit Emulator
- MPLAB ICE 4000 In-Circuit Emulator
• In-Circuit Debugger
• High-level source code debugging
• Visual device initializer for easy register
initialization
- MPLAB ICD 2
• Mouse over variable inspection
• Device Programmers
• Drag and drop variables from source to watch
windows
- PICSTART® Plus Development Programmer
- MPLAB PM3 Device Programmer
- PICkit™ 2 Development Programmer
• Extensive on-line help
• Integration of select third party tools, such as
HI-TECH Software C Compilers and IAR
C Compilers
• Low-Cost Demonstration and Development
Boards and Evaluation Kits
The MPLAB IDE allows you to:
• Edit your source files (either assembly or C)
• One touch assemble (or compile) and download
to PIC MCU emulator and simulator tools
(automatically updates all project information)
• Debug using:
- Source files (assembly or C)
- Mixed assembly and C
- Machine code
MPLAB IDE supports multiple debugging tools in a
single development paradigm, from the cost-effective
simulators, through low-cost in-circuit debuggers, to
full-featured emulators. This eliminates the learning
curve when upgrading to tools with increased flexibility
and power.
© 2007 Microchip Technology Inc.
PreliminaryAdvance Information
DS39682C-page 291
PIC18F45J10 FAMILY
22.2 MPASM Assembler
22.5 MPLAB ASM30 Assembler, Linker
and Librarian
The MPASM Assembler is a full-featured, universal
macro assembler for all PIC MCUs.
MPLAB ASM30 Assembler produces relocatable
machine code from symbolic assembly language for
dsPIC30F devices. MPLAB C30 C Compiler uses the
assembler to produce its object file. The assembler
generates relocatable object files that can then be
archived or linked with other relocatable object files and
archives to create an executable file. Notable features
of the assembler include:
The MPASM Assembler generates relocatable object
files for the MPLINK Object Linker, Intel® standard HEX
files, MAP files to detail memory usage and symbol
reference, absolute LST files that contain source lines
and generated machine code and COFF files for
debugging.
The MPASM Assembler features include:
• Integration into MPLAB IDE projects
• Support for the entire dsPIC30F instruction set
• Support for fixed-point and floating-point data
• Command line interface
• User-defined macros to streamline
assembly code
• Rich directive set
• Conditional assembly for multi-purpose
source files
• Flexible macro language
• MPLAB IDE compatibility
• Directives that allow complete control over the
assembly process
22.6 MPLAB SIM Software Simulator
22.3 MPLAB C18 and MPLAB C30
C Compilers
The MPLAB SIM Software Simulator allows code
development in a PC-hosted environment by simulat-
ing the PIC MCUs and dsPIC® DSCs on an instruction
level. On any given instruction, the data areas can be
examined or modified and stimuli can be applied from
a comprehensive stimulus controller. Registers can be
logged to files for further run-time analysis. The trace
buffer and logic analyzer display extend the power of
the simulator to record and track program execution,
actions on I/O, most peripherals and internal registers.
The MPLAB C18 and MPLAB C30 Code Development
Systems are complete ANSI
C
compilers for
Microchip’s PIC18 family of microcontrollers and the
dsPIC30, dsPIC33 and PIC24 family of digital signal
controllers. These compilers provide powerful integra-
tion capabilities, superior code optimization and ease
of use not found with other compilers.
For easy source level debugging, the compilers provide
symbol information that is optimized to the MPLAB IDE
debugger.
The MPLAB SIM Software Simulator fully supports
symbolic debugging using the MPLAB C18 and
MPLAB C30 C Compilers, and the MPASM and
MPLAB ASM30 Assemblers. The software simulator
offers the flexibility to develop and debug code outside
of the hardware laboratory environment, making it an
excellent, economical software development tool.
22.4 MPLINK Object Linker/
MPLIB Object Librarian
The MPLINK Object Linker combines relocatable
objects created by the MPASM Assembler and the
MPLAB C18 C Compiler. It can link relocatable objects
from precompiled libraries, using directives from a
linker script.
The MPLIB Object Librarian manages the creation and
modification of library files of precompiled code. When
a routine from a library is called from a source file, only
the modules that contain that routine will be linked in
with the application. This allows large libraries to be
used efficiently in many different applications.
The object linker/library features include:
• Efficient linking of single libraries instead of many
smaller files
• Enhanced code maintainability by grouping
related modules together
• Flexible creation of libraries with easy module
listing, replacement, deletion and extraction
DS39682C-page 292
Advance InformationPreliminary
© 2007 Microchip Technology Inc.
PIC18F45J10 FAMILY
22.7 MPLAB ICE 2000
High-Performance
22.9 MPLAB ICD 2 In-Circuit Debugger
Microchip’s In-Circuit Debugger, MPLAB ICD 2, is a
powerful, low-cost, run-time development tool,
connecting to the host PC via an RS-232 or high-speed
USB interface. This tool is based on the Flash PIC
MCUs and can be used to develop for these and other
PIC MCUs and dsPIC DSCs. The MPLAB ICD 2 utilizes
the in-circuit debugging capability built into the Flash
devices. This feature, along with Microchip’s In-Circuit
Serial ProgrammingTM (ICSPTM) protocol, offers cost-
effective, in-circuit Flash debugging from the graphical
user interface of the MPLAB Integrated Development
Environment. This enables a designer to develop and
debug source code by setting breakpoints, single step-
ping and watching variables, and CPU status and
peripheral registers. Running at full speed enables
testing hardware and applications in real time. MPLAB
ICD 2 also serves as a development programmer for
selected PIC devices.
In-Circuit Emulator
The MPLAB ICE 2000 In-Circuit Emulator is intended
to provide the product development engineer with a
complete microcontroller design tool set for PIC micro-
controllers. Software control of the MPLAB ICE 2000
In-Circuit Emulator is advanced by the MPLAB Inte-
grated Development Environment, which allows edit-
ing, building, downloading and source debugging from
a single environment.
The MPLAB ICE 2000 is a full-featured emulator
system with enhanced trace, trigger and data monitor-
ing features. Interchangeable processor modules allow
the system to be easily reconfigured for emulation of
different processors. The architecture of the MPLAB
ICE 2000 In-Circuit Emulator allows expansion to
support new PIC microcontrollers.
The MPLAB ICE 2000 In-Circuit Emulator system has
been designed as a real-time emulation system with
advanced features that are typically found on more
expensive development tools. The PC platform and
Microsoft® Windows® 32-bit operating system were
chosen to best make these features available in a
simple, unified application.
22.10 MPLAB PM3 Device Programmer
The MPLAB PM3 Device Programmer is a universal,
CE compliant device programmer with programmable
voltage verification at VDDMIN and VDDMAX for
maximum reliability. It features a large LCD display
(128 x 64) for menus and error messages and a modu-
lar, detachable socket assembly to support various
package types. The ICSP™ cable assembly is included
as a standard item. In Stand-Alone mode, the MPLAB
PM3 Device Programmer can read, verify and program
PIC devices without a PC connection. It can also set
code protection in this mode. The MPLAB PM3
connects to the host PC via an RS-232 or USB cable.
The MPLAB PM3 has high-speed communications and
optimized algorithms for quick programming of large
memory devices and incorporates an SD/MMC card for
file storage and secure data applications.
22.8 MPLAB ICE 4000
High-Performance
In-Circuit Emulator
The MPLAB ICE 4000 In-Circuit Emulator is intended to
provide the product development engineer with a
complete microcontroller design tool set for high-end
PIC MCUs and dsPIC DSCs. Software control of the
MPLAB ICE 4000 In-Circuit Emulator is provided by the
MPLAB Integrated Development Environment, which
allows editing, building, downloading and source
debugging from a single environment.
The MPLAB ICE 4000 is a premium emulator system,
providing the features of MPLAB ICE 2000, but with
increased emulation memory and high-speed perfor-
mance for dsPIC30F and PIC18XXXX devices. Its
advanced emulator features include complex triggering
and timing, and up to 2 Mb of emulation memory.
The MPLAB ICE 4000 In-Circuit Emulator system has
been designed as a real-time emulation system with
advanced features that are typically found on more
expensive development tools. The PC platform and
Microsoft Windows 32-bit operating system were
chosen to best make these features available in a
simple, unified application.
© 2007 Microchip Technology Inc.
PreliminaryAdvance Information
DS39682C-page 293
PIC18F45J10 FAMILY
22.11 PICSTART Plus Development
Programmer
22.13 Demonstration, Development and
Evaluation Boards
The PICSTART Plus Development Programmer is an
easy-to-use, low-cost, prototype programmer. It
connects to the PC via a COM (RS-232) port. MPLAB
Integrated Development Environment software makes
using the programmer simple and efficient. The
PICSTART Plus Development Programmer supports
most PIC devices in DIP packages up to 40 pins.
Larger pin count devices, such as the PIC16C92X and
PIC17C76X, may be supported with an adapter socket.
The PICSTART Plus Development Programmer is CE
compliant.
A wide variety of demonstration, development and
evaluation boards for various PIC MCUs and dsPIC
DSCs allows quick application development on fully func-
tional systems. Most boards include prototyping areas for
adding custom circuitry and provide application firmware
and source code for examination and modification.
The boards support a variety of features, including LEDs,
temperature sensors, switches, speakers, RS-232
interfaces, LCD displays, potentiometers and additional
EEPROM memory.
The demonstration and development boards can be
used in teaching environments, for prototyping custom
circuits and for learning about various microcontroller
applications.
22.12 PICkit 2 Development Programmer
The PICkit™ 2 Development Programmer is a low-cost
programmer with an easy-to-use interface for pro-
gramming many of Microchip’s baseline, mid-range
and PIC18F families of Flash memory microcontrollers.
The PICkit 2 Starter Kit includes a prototyping develop-
ment board, twelve sequential lessons, software and
HI-TECH’s PICC Lite C compiler, and is designed to
help get up to speed quickly using PIC® micro-
controllers. The kit provides everything needed to
program, evaluate and develop applications using
Microchip’s powerful, mid-range Flash memory family
of microcontrollers.
In addition to the PICDEM™ and dsPICDEM™ demon-
stration/development board series of circuits, Microchip
has a line of evaluation kits and demonstration software
®
for analog filter design, KEELOQ security ICs, CAN,
IrDA®, PowerSmart® battery management, SEEVAL®
evaluation system, Sigma-Delta ADC, flow rate
sensing, plus many more.
Check the Microchip web page (www.microchip.com)
and the latest “Product Selector Guide” (DS00148) for
the complete list of demonstration, development and
evaluation kits.
DS39682C-page 294
Advance InformationPreliminary
© 2007 Microchip Technology Inc.
PIC18F45J10 FAMILY
23.0 ELECTRICAL CHARACTERISTICS
(†)
Absolute Maximum Ratings
Ambient temperature under bias.............................................................................................................-40°C to +100°C
Storage temperature .............................................................................................................................. -65°C to +150°C
Voltage on any digital-only input MCLR I/O pin with respect to VSS ........................................................... -0.3V to 6.0V
Voltage on any combined digital and analog pin with respect to VSS ............................................ -0.3V to (VDD + 0.3V)
Voltage on VDDCORE with respect to VSS................................................................................................... -0.3V to 2.75V
Voltage on VDD with respect to VSS ........................................................................................................... -0.3V to 4.0V
Total power dissipation (Note 1) ...............................................................................................................................1.0W
Maximum current out of VSS pin ...........................................................................................................................300 mA
Maximum current into VDD pin ..............................................................................................................................250 mA
Input clamp current, IIK (VI < 0 or VI > VDD)..............................................................................................................0 mA
Output clamp current, IOK (VO < 0 or VO > VDD) ........................................................................................................TBD
Maximum output current sunk by any PORTB and PORTC I/O pin........................................................................25 mA
Maximum output current sunk by any PORTA, PORTD, and PORTE I/O pin...........................................................4 mA
Maximum output current sourced by any PORTB and PORTC I/O pin ..................................................................25 mA
Maximum output current sourced by any PORTA, PORTD, and PORTE I/O pin .....................................................4 mA
Maximum current sunk by all ports combined.......................................................................................................200 mA
Maximum current sourced by all ports combined..................................................................................................200 mA
Note 1: Power dissipation is calculated as follows:
Pdis = VDD x {IDD – ∑ IOH} + ∑ {(VDD – VOH) x IOH} + ∑(VOL x IOL)
† NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at those or any other conditions above those
indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for
extended periods may affect device reliability.
© 2007 Microchip Technology Inc.
Preliminary
DS39682C-page 295
PIC18F45J10 FAMILY
FIGURE 23-1:
PIC18LF45J10 FAMILY VOLTAGE-FREQUENCY GRAPH (INDUSTRIAL)
3.00V
2.75V
2.50V
2.25V
2.00V
2.7V
PIC18LF24J10/25J10/44J10/45J10
2.35V
4 MHz
40 MHz
Frequency
For frequencies between 4 MHz and 40 MHz, FMAX = (102.85 MHz/V) * (VDDCORE – 2V) + 4 MHz
Note 1: For devices without the voltage regulator, VDD and VDDCORE must be maintained so
that VDDCORE ≤ VDD ≤ 3.6V.
FIGURE 23-2:
PIC18F45J10 FAMILY VOLTAGE-FREQUENCY GRAPH (INDUSTRIAL)
4.0V
3.6V
3.5V
PIC18F2XJ10/4XJ10
3.0V
2.5V
2.7V
40 MHz
4 MHz
Frequency
Preliminary
DS39682C-page 296
© 2007 Microchip Technology Inc.
PIC18F45J10 FAMILY
23.1 DC Characteristics: Supply Voltage
PIC18F24J10/25J10/44J10/45J10 (Industrial)
PIC18LF24J10/25J10/44J10/45J10 (Industrial)
PIC18F45J10 Family
Standard Operating Conditions (unless otherwise stated)
(Industrial)
Operating temperature
-40°C ≤ TA ≤ +85°C for industrial
Param
Symbol
No.
Characteristic
Min
Typ Max Units
Conditions
D001
D001
D001B
VDD
VDD
Supply Voltage
Supply Voltage
VDDCORE
2.7(1)
—
—
—
3.6
3.6
2.7
V
V
V
PIC18LF4XJ10, PIC18LF2XJ10
PIC18F4X/2XJ10
VDDCORE External Supply for
2.0
Valid only in parts designated “LF”.
See Section 20.3 “On-Chip
Voltage Regulator” for details.
Microcontroller Core
D002
D003
VDR
RAM Data Retention
Voltage(1)
1.5
—
—
—
—
V
V
VPOR
VDD Start Voltage
to ensure internal
TBD
See Section 4.3 “Power-on
Reset (POR)” for details
Power-on Reset signal
D004
SVDD
VDD Rise Rate
to ensure internal
Power-on Reset signal
0.05
—
—
V/ms See Section 4.3 “Power-on
Reset (POR)” for details
Legend: TBD = To Be Determined
Note 1: This is the limit to which VDD can be lowered in Sleep mode, or during a device Reset, without losing RAM
data.
© 2007 Microchip Technology Inc.
Preliminary
DS39682C-page 297
PIC18F45J10 FAMILY
23.2 DC Characteristics: Power-Down and Supply Current
PIC18F24J10/25J10/44J10/45J10 (Industrial)
PIC18LF24J10/25J10/44J10/45J10 (Industrial)
PIC18F45J10 Family
Standard Operating Conditions (unless otherwise stated)
(Industrial)
Operating temperature
-40°C ≤ TA ≤ +85°C for industrial
Param
No.
Device
Power-Down Current (IPD)
Typ
Max Units
Conditions
(1)
All devices
19
25
40
20
25
45
104
104
184
203
203
289
μA
μA
μA
μA
μA
μA
-40°C
+25°C
+85°C
-40°C
+25°C
+85°C
VDD = 2.5V,
(Sleep mode)
All devices
VDD = 3.3V,
(Sleep mode)
Note 1: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with
the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS and all features that add delta
current disabled (such as WDT, Timer1 oscillator, etc.).
2: The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading
and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on
the current consumption.
The test conditions for all IDD measurements in active operation mode are:
OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD;
MCLR = VDD; WDT enabled/disabled as specified.
3: Standard, low-cost 32 kHz crystals have an operating temperature range of -10°C to +70°C. Extended temperature
crystals are available at a much higher cost.
DS39682C-page 298
Preliminary
© 2007 Microchip Technology Inc.
PIC18F45J10 FAMILY
23.2 DC Characteristics: Power-Down and Supply Current
PIC18F24J10/25J10/44J10/45J10 (Industrial)
PIC18LF24J10/25J10/44J10/45J10 (Industrial) (Continued)
PIC18F45J10 Family
Standard Operating Conditions (unless otherwise stated)
(Industrial)
Operating temperature
-40°C ≤ TA ≤ +85°C for industrial
Param
No.
Device
Supply Current (IDD)
Typ Max Units
Conditions
(2)
All devices 3.8
7.7
7.5
mA
mA
mA
mA
mA
mA
μA
μA
μA
μA
μA
μA
-40°C
3.7
+25°C
+85°C
-40°C
+25°C
+85°C
-40°C
+25°C
+85°C
-40°C
+25°C
+85°C
VDD = 2.5V
VDD = 3.3V
VDD = 2.5V
VDD = 3.3V
FOSC = 31 kHz
(RC_RUN mode,
Internal oscillator source)
3.7
7.5
All devices 3.9
7.9
3.7
3.7
7.5
7.5
All devices
All devices
64
77
95
65
79
98
167
193
269
266
294
360
FOSC = 31 kHz
(RC_IDLE mode,
Internal oscillator source)
Note 1: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with
the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS and all features that add delta
current disabled (such as WDT, Timer1 oscillator, etc.).
2: The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading
and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on
the current consumption.
The test conditions for all IDD measurements in active operation mode are:
OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD;
MCLR = VDD; WDT enabled/disabled as specified.
3: Standard, low-cost 32 kHz crystals have an operating temperature range of -10°C to +70°C. Extended temperature
crystals are available at a much higher cost.
© 2007 Microchip Technology Inc.
Preliminary
DS39682C-page 299
PIC18F45J10 FAMILY
23.2 DC Characteristics: Power-Down and Supply Current
PIC18F24J10/25J10/44J10/45J10 (Industrial)
PIC18LF24J10/25J10/44J10/45J10 (Industrial) (Continued)
PIC18F45J10 Family
Standard Operating Conditions (unless otherwise stated)
(Industrial)
Operating temperature
-40°C ≤ TA ≤ +85°C for industrial
Param
No.
Device
Supply Current (IDD)
Typ Max Units
Conditions
(2)
All devices 4.2
8.5
8.0
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
-40°C
3.9
+25°C
+85°C
-40°C
+25°C
+85°C
-40°C
+25°C
+85°C
-40°C
+25°C
+85°C
-40°C
+25°C
+85°C
-40°C
+25°C
+85°C
VDD = 2.5V
VDD = 3.3V
VDD = 2.5V
VDD = 3.3V
VDD = 2.5V
VDD = 3.3V
FOSC = 1 MHz
(PRI_RUN mode,
EC oscillator)
3.6
7.3
All devices 4.3
8.6
4.0
8.1
3.7
7.6
All devices 4.6
9.3
4.3
8.7
FOSC = 4 MHz
(PRI_RUN mode,
EC oscillator)
4.0
8.1
All devices 4.7
9.4
4.4
8.8
4.1
8.2
All devices 11.0
22.0
21.0
20.0
24.0
23.0
22.0
10.5
FOSC = 40 MHz
(PRI_RUN mode,
EC oscillator)
10.0
All devices 12.0
11.5
11.0
Note 1: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with
the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS and all features that add delta
current disabled (such as WDT, Timer1 oscillator, etc.).
2: The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading
and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on
the current consumption.
The test conditions for all IDD measurements in active operation mode are:
OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD;
MCLR = VDD; WDT enabled/disabled as specified.
3: Standard, low-cost 32 kHz crystals have an operating temperature range of -10°C to +70°C. Extended temperature
crystals are available at a much higher cost.
DS39682C-page 300
Preliminary
© 2007 Microchip Technology Inc.
PIC18F45J10 FAMILY
23.2 DC Characteristics: Power-Down and Supply Current
PIC18F24J10/25J10/44J10/45J10 (Industrial)
PIC18LF24J10/25J10/44J10/45J10 (Industrial) (Continued)
PIC18F45J10 Family
Standard Operating Conditions (unless otherwise stated)
(Industrial)
Operating temperature
-40°C ≤ TA ≤ +85°C for industrial
Param
No.
Device
Supply Current (IDD)
Typ Max Units
Conditions
(2)
All devices 6.2
14
13
13
15
14
14
22
21
20
24
23
22
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
-40°C
FOSC = 4 MHZ.
16 MHZ internal
(PRI_RUN HS+PLL)
5.7
+25°C
+85°C
-40°C
+25°C
+85°C
-40°C
+25°C
+85°C
-40°C
+25°C
+85°C
VDD = 2.5V
VDD = 3.3V
VDD = 2.5V
VDD = 3.3V
5.7
All devices 6.6
FOSC = 4 MHZ
16 MHZ internal
(PRI_RUN HS+PLL)
6.1
6.1
All devices 11.0
FOSC = 10 MHZ
40 MHZ internal
(PRI_RUN HS+PLL)
10.5
10.0
All devices 12.0
11.5
FOSC = 10 MHZ
40 MHZ internal
(PRI_RUN HS+PLL)
11.0
Note 1: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with
the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS and all features that add delta
current disabled (such as WDT, Timer1 oscillator, etc.).
2: The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading
and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on
the current consumption.
The test conditions for all IDD measurements in active operation mode are:
OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD;
MCLR = VDD; WDT enabled/disabled as specified.
3: Standard, low-cost 32 kHz crystals have an operating temperature range of -10°C to +70°C. Extended temperature
crystals are available at a much higher cost.
© 2007 Microchip Technology Inc.
Preliminary
DS39682C-page 301
PIC18F45J10 FAMILY
23.2 DC Characteristics: Power-Down and Supply Current
PIC18F24J10/25J10/44J10/45J10 (Industrial)
PIC18LF24J10/25J10/44J10/45J10 (Industrial) (Continued)
PIC18F45J10 Family
Standard Operating Conditions (unless otherwise stated)
(Industrial)
Operating temperature
-40°C ≤ TA ≤ +85°C for industrial
Param
No.
Device
Supply Current (IDD)
Typ Max Units
Conditions
(2)
All devices 150
337
355
512
518
528
647
737
787
917
954
μA
μA
μA
μA
μA
μA
μA
μA
μA
μA
mA
mA
mA
mA
mA
mA
mA
mA
-40°C
160
+25°C
+85°C
-40°C
+25°C
+85°C
-40°C
+25°C
+85°C
-40°C
+25°C
+85°C
-40°C
+25°C
+85°C
-40°C
+25°C
+85°C
VDD = 2.5V
VDD = 3.3V
VDD = 2.5V
VDD = 3.3V
VDD = 2.5V
VDD = 3.3V
FOSC = 1 MHz
(PRI_IDLE mode,
EC oscillator)
220
All devices 190
200
250
All devices 350
375
FOSC = 4 MHz
(PRI_IDLE mode,
EC oscillator)
420
All devices 410
0.450 1.03
0.475 1.13
All devices 5.0
10.1
10.6
11.1
11.1
12.1
13.1
5.2
FOSC = 40 MHz
(PRI_IDLE mode,
EC oscillator)
5.5
All devices 5.5
6.0
6.5
Note 1: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with
the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS and all features that add delta
current disabled (such as WDT, Timer1 oscillator, etc.).
2: The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading
and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on
the current consumption.
The test conditions for all IDD measurements in active operation mode are:
OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD;
MCLR = VDD; WDT enabled/disabled as specified.
3: Standard, low-cost 32 kHz crystals have an operating temperature range of -10°C to +70°C. Extended temperature
crystals are available at a much higher cost.
DS39682C-page 302
Preliminary
© 2007 Microchip Technology Inc.
PIC18F45J10 FAMILY
23.2 DC Characteristics: Power-Down and Supply Current
PIC18F24J10/25J10/44J10/45J10 (Industrial)
PIC18LF24J10/25J10/44J10/45J10 (Industrial) (Continued)
PIC18F45J10 Family
Standard Operating Conditions (unless otherwise stated)
(Industrial)
Operating temperature
-40°C ≤ TA ≤ +85°C for industrial
Param
No.
Device
Supply Current (IDD)
Typ Max Units
Conditions
(2)
All devices 4.1
8.3
7.7
mA
mA
mA
mA
mA
mA
μA
μA
μA
μA
μA
μA
-40°C
3.8
+25°C
+85°C
-40°C
+25°C
+85°C
-40°C
+25°C
+85°C
-40°C
+25°C
+85°C
VDD = 2.5V
VDD = 3.3V
VDD = 2.5V
VDD = 3.3V
FOSC = 32 kHz
(SEC_RUN mode,
Timer1 as clock)
3.8
7.7
All devices 4.1
8.3
3.8
3.8
7.7
7.7
All devices
All devices
66
79
169
195
271
268
296
362
FOSC = 32 kHz
(SEC_IDLE mode,
Timer1 as clock)
97
67
81
100
Note 1: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with
the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS and all features that add delta
current disabled (such as WDT, Timer1 oscillator, etc.).
2: The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading
and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on
the current consumption.
The test conditions for all IDD measurements in active operation mode are:
OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD;
MCLR = VDD; WDT enabled/disabled as specified.
3: Standard, low-cost 32 kHz crystals have an operating temperature range of -10°C to +70°C. Extended temperature
crystals are available at a much higher cost.
© 2007 Microchip Technology Inc.
Preliminary
DS39682C-page 303
PIC18F45J10 FAMILY
23.2 DC Characteristics: Power-Down and Supply Current
PIC18F24J10/25J10/44J10/45J10 (Industrial)
PIC18LF24J10/25J10/44J10/45J10 (Industrial) (Continued)
PIC18F45J10 Family
Standard Operating Conditions (unless otherwise stated)
(Industrial)
Operating temperature
Typ Max Units
Module Differential Currents (ΔIWDT, ΔIOSCB, ΔIAD)
-40°C ≤ TA ≤ +85°C for industrial
Param
No.
Device
Conditions
D022
(ΔIWDT)
3.2
3.2
5.1
3.5
3.5
5.5
6.5
6.5
10.3
7.1
7.1
11.2
17
μA
μA
μA
μA
μA
μA
μA
μA
μA
μA
μA
μA
μA
μA
-40°C
Watchdog Timer
VDD = 2.5V
VDD = 3.3V
VDD = 2.5V
VDD = 3.3V
+25°C
+85°C
-40°C
+25°C
+85°C
D025
(ΔIOSCB)
Timer1 Oscillator 8.4
-40°C
(3)
(3)
32 kHz on Timer1
32 kHz on Timer1
11.5
24
+25°C
13.2
30
+85°C
9.6
20
-40°C
12.4
25
+25°C
14.1
A/D Converter 1.0
1.2
29
+85°C
D026
(ΔIAD)
5
-40°C to +85°C
-40°C to +85°C
VDD = 2.5V
VDD = 3.3V
A/D on, not converting
5
Note 1: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with
the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS and all features that add delta
current disabled (such as WDT, Timer1 oscillator, etc.).
2: The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading
and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on
the current consumption.
The test conditions for all IDD measurements in active operation mode are:
OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD;
MCLR = VDD; WDT enabled/disabled as specified.
3: Standard, low-cost 32 kHz crystals have an operating temperature range of -10°C to +70°C. Extended temperature
crystals are available at a much higher cost.
DS39682C-page 304
Preliminary
© 2007 Microchip Technology Inc.
PIC18F45J10 FAMILY
23.3 DC Characteristics: PIC18F45J10 family (Industrial)
Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C ≤ TA ≤ +85°C for industrial
DC CHARACTERISTICS
Param
Symbol
No.
Characteristic
Min
Max
Units
Conditions
VIL
Input Low Voltage
All I/O ports:
with TTL buffer
D030
D030A
D031
D032
D033
D033A
VSS
—
0.15 VDD
0.8
V
V
V
V
V
V
VDD < 3.3V
3.3V ≤ VDD ≤ 3.6V
with Schmitt Trigger buffer
MCLR
VSS
VSS
VSS
VSS
0.2 VDD
0.2 VDD
0.3 VDD
0.2 VDD
OSC1
OSC1
HS, HSPLL modes
EC, ECPLL modes(1)
D034
T1CKI
VSS
0.3
V
VIH
Input High Voltage
I/O ports with analog functions:
with TTL buffer
D040
D040A
D041
0.25 VDD + 0.8V
2.0
VDD
VDD
VDD
V
V
V
VDD < 3.3V
3.3V ≤ VDD ≤ 3.6V
with Schmitt Trigger buffer
Digital-only I/O ports:
with TTL buffer
0.8 VDD
Dxxx
0.25 VDD + 0.8V
2.0
5.5
5.5
V
V
V
V
V
V
VDD < 3.3V
DxxxA
Dxxx
3.3V ≤ VDD ≤ 3.6V
with Schmitt Trigger buffer
0.8 VDD
0.8 VDD
0.7 VDD
0.8 VDD
5.5
D042
D043
D043A
MCLR
OSC1
OSC1
VDD
VDD
VDD
HS, HSPLL modes
EC, ECPLL modes
D044
T1CKI
1.6
VDD
V
IIL
Input Leakage Current(2,3)
D060
I/O ports
—
1
μA VSS ≤ VPIN ≤ VDD,
Pin at high-impedance
D061
D063
MCLR
—
—
1
5
μA Vss ≤ VPIN ≤ VDD
μA Vss ≤ VPIN ≤ VDD
OSC1
IPU
Weak Pull-up Current
PORTB weak pull-up current
D070
IPURB
30
240
μA VDD = 3.3V, VPIN = VSS
Note 1: In RC oscillator configuration, the OSC1/CLKI pin is a Schmitt Trigger input. It is not recommended that the
PIC® device be driven with an external clock while in RC mode.
2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified
levels represent normal operating conditions. Higher leakage current may be measured at different input
voltages.
3: Negative current is defined as current sourced by the pin.
© 2007 Microchip Technology Inc.
Preliminary
DS39682C-page 305
PIC18F45J10 FAMILY
23.3 DC Characteristics: PIC18F45J10 family (Industrial) (Continued)
Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C ≤ TA ≤ +85°C for industrial
DC CHARACTERISTICS
Param
Symbol
No.
Characteristic
Min
Max
Units
Conditions
VOL
Output Low Voltage
D080
I/O ports (PORTB, PORTC)
—
—
—
0.4
0.4
0.4
V
V
V
IOL = 3.4 mA, VDD 3.3V
-40°C to +85°C
I/O ports (PORTA, PORTD,
PORTE)
IOL = 3.4 mA, VDD 3.3V
-40°C to +85°C
D083
D090
OSC2/CLKO
(EC mode)
Output High Voltage(3)
IOL = 1.6 mA, VDD 3.3V
-40°C to +85°C
VOH
I/O ports (PORTB, PORTC)
2.4
2.4
2.4
—
—
—
V
V
V
IOH = -2 mA, VDD 3.3V
-40°C to +85°C
I/O ports (PORTA, PORTD,
PORTE)
IOH = -2 mA, VDD 3.3V
-40°C to +85°C
D092
OSC2/CLKO
(EC mode)
IOH = 1.0 mA, VDD 3.3V
-40°C to +85°C
Capacitive Loading Specs
on Output Pins
D100(4) COSC2 OSC2 pin
15
pF In HS mode when
external clock is used to drive
OSC1
—
D101
D102
CIO
CB
All I/O pins
—
—
50
pF To meet the AC Timing
Specifications
pF I2C™ Specification
SCLx, SDAx
400
Note 1: In RC oscillator configuration, the OSC1/CLKI pin is a Schmitt Trigger input. It is not recommended that the
PIC® device be driven with an external clock while in RC mode.
2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified
levels represent normal operating conditions. Higher leakage current may be measured at different input
voltages.
3: Negative current is defined as current sourced by the pin.
DS39682C-page 306
Preliminary
© 2007 Microchip Technology Inc.
PIC18F45J10 FAMILY
TABLE 23-1: MEMORY PROGRAMMING REQUIREMENTS
Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C ≤ TA ≤ +85°C for industrial
DC CHARACTERISTICS
Param
Sym
No.
Characteristic
Min
Typ†
Max
Units
Conditions
Program Flash Memory
Cell Endurance
D130
D131
EP
100
1K
—
—
E/W -40°C to +85°C
VPR
VDD for Read
VMIN
3.6
V
VMIN = Minimum operating
voltage
D132B VPEW VDD for Self-Timed Write
VMIN
—
3.6
V
VMIN = Minimum operating
voltage
D133A TIW
Self-Timed Write Cycle Time
—
2.8
—
—
—
ms
D134 TRETD Characteristic Retention
20
Year Provided no other
specifications are violated
D135
IDDP
Supply Current during
Programming
—
10
—
mA
†
Data in “Typ” column is at 3.3V, 25°C unless otherwise stated. These parameters are for design guidance
only and are not tested.
© 2007 Microchip Technology Inc.
Preliminary
DS39682C-page 307
PIC18F45J10 FAMILY
TABLE 23-2: COMPARATOR SPECIFICATIONS
Operating Conditions: 3.0V < VDD < 3.6V, -40°C < TA < +85°C (unless otherwise stated)
Param
No.
Sym
Characteristics
Input Offset Voltage
Min
Typ
Max
Units
Comments
D300
VIOFF
—
0
±5.0
—
±10
VDD – 1.5
—
mV
V
D301
D302
300
VICM
Input Common Mode Voltage*
Common Mode Rejection Ratio*
Response Time(1)*
CMRR
TRESP
55
—
—
—
dB
ns
μs
150
—
400
301
TMC2OV Comparator Mode Change to
10
Output Valid*
*
These parameters are characterized but not tested.
Note 1: Response time measured with one comparator input at (VDD – 1.5)/2, while the other input transitions
from VSS to VDD.
TABLE 23-3: VOLTAGE REFERENCE SPECIFICATIONS
Operating Conditions: 3.0V < VDD < 3.6V, -40°C < TA < +85°C (unless otherwise stated)
Param
No.
Sym
Characteristics
Resolution
Min
Typ
Max
Units
Comments
D310
VRES
VDD/24
—
—
—
2k
—
VDD/32
1/2
LSb
LSb
Ω
D311
D312
310
VRAA
VRUR
TSET
Absolute Accuracy
Unit Resistor Value (R)
Settling Time(1)
—
—
—
10
μs
Note 1: Settling time measured while CVRR = 1and CVR3:CVR0 transitions from ‘0000’ to ‘1111’.
TABLE 23-4: INTERNAL VOLTAGE REGULATOR SPECIFICATIONS
Operating Conditions: -40°C < TA < +85°C (unless otherwise stated)
Param
No.
Sym
Characteristics
Min
Typ
Max
Units
Comments
VRGOUT Regulator Output Voltage
—
2.5
10
—
—
V
CEFC
External Filter Capacitor
Value
4.7
μF
Capacitor must be low ESR
*
These parameters are characterized but not tested. Parameter numbers not yet assigned for these
specifications.
DS39682C-page 308
Preliminary
© 2007 Microchip Technology Inc.
PIC18F45J10 FAMILY
23.4 AC (Timing) Characteristics
23.4.1 TIMING PARAMETER SYMBOLOGY
The timing parameter symbols have been created
following one of the following formats:
1. TppS2ppS
2. TppS
T
3. TCC:ST
4. Ts
(I2C specifications only)
(I2C specifications only)
F
Frequency
T
Time
Lowercase letters (pp) and their meanings:
pp
cc
ck
cs
di
CCP1
CLKO
CS
osc
rd
OSC1
RD
rw
sc
ss
t0
RD or WR
SCK
SDI
do
dt
SDO
SS
Data in
I/O port
MCLR
T0CKI
T1CKI
WR
io
t1
mc
wr
Uppercase letters and their meanings:
S
F
Fall
P
R
V
Z
Period
H
High
Rise
I
Invalid (High-impedance)
Low
Valid
L
High-impedance
I2C only
AA
output access
Bus free
High
Low
High
Low
BUF
TCC:ST (I2C specifications only)
CC
HD
Hold
SU
Setup
ST
DAT
STA
DATA input hold
Start condition
STO
Stop condition
© 2007 Microchip Technology Inc.
Preliminary
DS39682C-page 309
PIC18F45J10 FAMILY
23.4.2
TIMING CONDITIONS
The temperature and voltages specified in Table 23-5
apply to all timing specifications unless otherwise
noted. Figure 23-3 specifies the load conditions for the
timing specifications.
TABLE 23-5: TEMPERATURE AND VOLTAGE SPECIFICATIONS – AC
Standard Operating Conditions (unless otherwise stated)
Operating temperature
Operating voltage VDD range as described in DC spec Section 23.1 and
Section 23.3.
-40°C ≤ TA ≤ +85°C for industrial
AC CHARACTERISTICS
FIGURE 23-3:
LOAD CONDITIONS FOR DEVICE TIMING SPECIFICATIONS
Load Condition 1 Load Condition 2
VDD/2
CL
RL
Pin
VSS
CL
Pin
RL = 464Ω
CL = 50 pF for all pins except OSC2/CLKO
and including D and E outputs as ports
VSS
CL = 15 pF for OSC2/CLK0
DS39682C-page 310
Preliminary
© 2007 Microchip Technology Inc.
PIC18F45J10 FAMILY
23.4.3
TIMING DIAGRAMS AND SPECIFICATIONS
FIGURE 23-4:
EXTERNAL CLOCK TIMING (ALL MODES EXCEPT PLL)
Q4
Q1
1
Q2
Q3
Q4
Q1
OSC1
CLKO
3
4
3
4
2
TABLE 23-6: EXTERNAL CLOCK TIMING REQUIREMENTS
Param.
Symbol
Characteristic
Min
Max
Units
Conditions
No.
1A
1
FOSC
External CLKI Frequency(1)
Oscillator Frequency(1)
External CLKI Period(1)
DC
4
40
25
MHz EC Oscillator mode
MHz HS Oscillator mode
TOSC
25
25
—
ns
ns
EC Oscillator mode
HS Oscillator mode
Oscillator Period(1)
250
2
3
TCY
Instruction Cycle Time(1)
100
10
—
—
ns
ns
TCY = 4/FOSC, Industrial
EC Oscillator mode
TOSL,
TOSH
External Clock in (OSC1)
High or Low Time
4
TOSR,
TOSF
External Clock in (OSC1)
Rise or Fall Time
—
7.5
ns
EC Oscillator mode
Note 1: Instruction cycle period (TCY) equals four times the input oscillator time base period for all configurations.
All specified values are based on characterization data for that particular oscillator type under standard
operating conditions with the device executing code. Exceeding these specified limits may result in an
unstable oscillator operation and/or higher than expected current consumption. All devices are tested to
operate at “min.” values with an external clock applied to the OSC1/CLKI pin. When an external clock input
is used, the “max.” cycle time limit is “DC” (no clock) for all devices.
© 2007 Microchip Technology Inc.
Preliminary
DS39682C-page 311
PIC18F45J10 FAMILY
TABLE 23-7: PLL CLOCK TIMING SPECIFICATIONS (VDD = 2.5V TO 3.6V)
Param
Sym
Characteristic
Min
Typ†
Max
Units Conditions
No.
F10
FOSC Oscillator Frequency Range
4
—
—
—
—
10
40
MHz
MHz
F11
F12
F13
FSYS On-Chip VCO System Frequency
20
—
-2
ΤRC
PLL Start-up Time (lock time)
2 ms
+2
ΔCLK CLKO Stability (Jitter)
%
†
Data in “Typ” column is at 5V, 25°C, unless otherwise stated. These parameters are for design guidance
only and are not tested.
TABLE 23-8: AC CHARACTERISTICS: INTERNAL RC ACCURACY
PIC18F24J10/25J10/44J10/45J10 (INDUSTRIAL)
Param
No.
Characteristic
Min
Typ
Max
Units
Conditions
INTRC Accuracy @ Freq = 31 kHz(1) 21.7
—
40.3
kHz
Note 1: Change of INTRC frequency as VDD core changes.
DS39682C-page 312
Preliminary
© 2007 Microchip Technology Inc.
PIC18F45J10 FAMILY
FIGURE 23-5:
CLKO AND I/O TIMING
Q1
Q2
Q3
Q4
OSC1
11
10
CLKO
13
14
12
19
18
16
I/O pin
(Input)
15
17
I/O pin
(Output)
New Value
Old Value
20, 21
Refer to Figure 23-3 for load conditions.
Note:
TABLE 23-9: CLKO AND I/O TIMING REQUIREMENTS
Param
Symbol
Characteristic
Min
Typ
Max
Units Conditions
No.
10
TOSH2CKL OSC1 ↑ to CLKO ↓
TOSH2CKH OSC1 ↑ to CLKO ↑
—
75
75
15
15
—
—
—
50
—
—
—
200
200
30
ns
ns
ns
ns
11
—
12
13
14
15
16
17
18
18A
19
TCKR
TCKF
CLKO Rise Time
CLKO Fall Time
—
—
30
TCKL2IOV CLKO ↓ to Port Out Valid
TIOV2CKH Port In Valid before CLKO ↑
TCKH2IOI Port In Hold after CLKO ↑
TOSH2IOV OSC1 ↑ (Q1 cycle) to Port Out Valid
—
0.5 TCY + 20 ns
0.25 TCY + 25
—
—
ns
ns
ns
ns
ns
ns
0
—
150
—
TOSH2IOI OSC1 ↑ (Q2 cycle) to Port Input Invalid
100
200
0
(I/O in hold time)
—
TIOV2OSH Port Input Valid to OSC1 ↑
—
(I/O in setup time)
20
TIOR
TIOF
TINP
TRBP
Port Output Rise Time
—
—
TBD
TBD
—
6
5
ns
ns
ns
ns
21
Port Output Fall Time
22†
23†
INT pin High or Low Time
RB7:RB4 Change INT High or Low Time
TCY
TCY
—
—
—
Legend: TBD = To Be Determined
These parameters are asynchronous events not related to any internal clock edges.
†
© 2007 Microchip Technology Inc.
Preliminary
DS39682C-page 313
PIC18F45J10 FAMILY
FIGURE 23-6:
RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND
POWER-UP TIMER TIMING
VDD
MCLR
30
Internal
POR
33
PWRT
Time-out
32
Oscillator
Time-out
Internal
Reset
Watchdog
Timer
Reset
31
34
34
I/O pins
Note:
Refer to Figure 23-3 for load conditions.
FIGURE 23-7:
BROWN-OUT RESET TIMING
BVDD
VDD
VBGAP = 1.2V
VIRVST
Enable Internal
Reference Voltage
Internal Reference
Voltage Stable
TABLE 23-10: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER
AND BROWN-OUT RESET REQUIREMENTS
Param.
No.
Symbol
Characteristic
Min
Typ
Max
Units
Conditions
30
TMCL
TWDT
MCLR Pulse Width (low)
2
—
—
μs
ms
31
Watchdog Timer Time-out Period
(no postscaler)
2.8
4.1
5.4
32
33
34
TOST
Oscillation Start-up Timer Period
1024 TOSC
46.2
—
66
2
1024 TOSC
85.8
—
ms
μs
TOSC = OSC1 period
TPWRT Power-up Timer Period
TIOZ
I/O High-Impedance from MCLR
Low or Watchdog Timer Reset
—
—
38
TCSD
CPU Start-up Time
—
200
—
μs
DS39682C-page 314
Preliminary
© 2007 Microchip Technology Inc.
PIC18F45J10 FAMILY
FIGURE 23-8:
TIMER0 AND TIMER1 EXTERNAL CLOCK TIMINGS
T0CKI
41
40
42
T1OSO/T1CKI
46
45
47
48
TMR0 or
TMR1
Note:
Refer to Figure 23-3 for load conditions.
TABLE 23-11: TIMER0 AND TIMER1 EXTERNAL CLOCK REQUIREMENTS
Param
Symbol
Characteristic
Min
Max Units
Conditions
No.
40
TT0H
T0CKI High Pulse Width
No prescaler
With prescaler
No prescaler
With prescaler
No prescaler
With prescaler
0.5 TCY + 20
10
—
—
—
—
—
—
ns
ns
ns
ns
ns
41
42
TT0L
TT0P
T0CKI Low Pulse Width
T0CKI Period
0.5 TCY + 20
10
TCY + 10
Greater of:
20 ns or
ns N = prescale
value
(TCY + 40)/N
(1, 2, 4,..., 256)
45
46
47
TT1H
TT1L
TT1P
T1CKI High Synchronous, no prescaler
0.5 TCY + 20
—
—
—
—
—
—
—
ns
ns
ns
ns
ns
ns
Time
Synchronous, with prescaler
10
Asynchronous
30
0.5 TCY + 5
10
T1CKI Low Synchronous, no prescaler
Time
Synchronous, with prescaler
Asynchronous
30
T1CKI Input Synchronous
Period
Greater of:
20 ns or
ns N = prescale
value
(TCY + 40)/N
(1, 2, 4, 8)
Asynchronous
60
DC
—
50
ns
kHz
—
FT1
T1CKI Oscillator Input Frequency Range
48
TCKE2TMRI Delay from External T1CKI Clock Edge to
Timer Increment
2 TOSC
7 TOSC
© 2007 Microchip Technology Inc.
Preliminary
DS39682C-page 315
PIC18F45J10 FAMILY
FIGURE 23-9:
CAPTURE/COMPARE/PWM TIMINGS (INCLUDING ECCP MODULE)
CCPx
(Capture Mode)
50
51
52
54
CCPx
(Compare or PWM Mode)
53
Refer to Figure 23-3 for load conditions.
Note:
TABLE 23-12: CAPTURE/COMPARE/PWM REQUIREMENTS (INCLUDING ECCP MODULE)
Param
Symbol
Characteristic
Min
Max
Units
Conditions
No.
50
TCCL
CCPx Input Low No prescaler
0.5 TCY + 20
—
—
—
—
—
ns
ns
ns
ns
ns
Time
With prescaler
10
0.5 TCY + 20
10
51
52
TCCH
TCCP
CCPx Input
High Time
No prescaler
With prescaler
CCPx Input Period
3 TCY + 40
N
N = prescale
value (1, 4 or 16)
53
54
TCCR
TCCF
CCPx Output Fall Time
CCPx Output Fall Time
—
—
25
25
ns
ns
TABLE 23-13: PARALLEL SLAVE PORT REQUIREMENTS
Param.
Symbol
Characteristic
Min
Max Units
Conditions
No.
62
TdtV2wrH
TwrH2dtI
TrdL2dtV
TrdH2dtI
TibfINH
Data In Valid before WR ↑ or CS ↑ (setup time)
WR ↑ or CS ↑ to Data–In Invalid (hold time)
RD ↓ and CS ↓ to Data–Out Valid
20
20
—
10
—
—
—
ns
ns
ns
ns
63
64
65
66
80
RD ↑ or CS ↓ to Data–Out Invalid
30
Inhibit of the IBF Flag bit being Cleared from
3 TCY
WR ↑ or CS ↑
DS39682C-page 316
Preliminary
© 2007 Microchip Technology Inc.
PIC18F45J10 FAMILY
FIGURE 23-10:
EXAMPLE SPI™ MASTER MODE TIMING (CKE = 0)
SSx
70
SCKx
(CKP = 0)
71
72
78
79
79
SCKx
(CKP = 1)
78
80
MSb
bit 6 - - - - - - 1
LSb
SDOx
SDIx
75, 76
MSb In
74
bit 6 - - - - 1
LSb In
73
Note: Refer to Figure 23-3 for load conditions.
TABLE 23-14: EXAMPLE SPI™ MODE REQUIREMENTS (MASTER MODE, CKE = 0)
Param
No.
Symbol
Characteristic
Min
Max Units Conditions
70
TSSL2SCH, SSx ↓ to SCKx ↓ or SCKx ↑ Input
TSSL2SCL
TCY
—
ns
71
TSCH
SCKx Input High Time
(Slave mode)
Continuous
Single Byte
Continuous
Single Byte
1.25 TCY + 30
—
—
—
—
—
ns
71A
72
40
1.25 TCY + 30
40
ns (Note 1)
TSCL
SCKx Input Low Time
(Slave mode)
ns
72A
73
ns (Note 1)
TDIV2SCH, Setup Time of SDIx Data Input to SCKx Edge
TDIV2SCL
100
ns
73A
74
TB2B
Last Clock Edge of Byte 1 to the 1st Clock Edge 1.5 TCY + 40
of Byte 2
—
—
ns (Note 2)
TSCH2DIL, Hold Time of SDIx Data Input to SCKx Edge
TSCL2DIL
100
ns
75
76
78
79
80
TDOR
TDOF
TSCR
TSCF
SDOx Data Output Rise Time
—
—
—
—
—
25
25
25
25
50
ns
ns
ns
ns
ns
SDOx Data Output Fall Time
SCKx Output Rise Time (Master mode)
SCKx Output Fall Time (Master mode)
TSCH2DOV, SDOx Data Output Valid after SCKx Edge
TSCL2DOV
Note 1: Requires the use of Parameter #73A.
2: Only if Parameter #71A and #72A are used.
© 2007 Microchip Technology Inc.
Preliminary
DS39682C-page 317
PIC18F45J10 FAMILY
FIGURE 23-11:
EXAMPLE SPI™ MASTER MODE TIMING (CKE = 1)
SSx
81
SCKx
(CKP = 0)
71
72
79
78
73
SCKx
(CKP = 1)
80
LSb
MSb
bit 6 - - - - - - 1
SDOx
SDIx
75, 76
MSb In
74
bit 6 - - - - 1
LSb In
Note: Refer to Figure 23-3 for load conditions.
TABLE 23-15: EXAMPLE SPI™ MODE REQUIREMENTS (MASTER MODE, CKE = 1)
Param.
No.
Symbol
TSCH
Characteristic
Min
Max Units Conditions
71
SCKx Input High Time
Continuous
Single Byte
Continuous
Single Byte
1.25 TCY + 30
—
—
—
—
—
ns
(Slave mode)
71A
72
40
1.25 TCY + 30
40
ns (Note 1)
TSCL
SCKx Input Low Time
(Slave mode)
ns
72A
73
ns (Note 1)
TDIV2SCH, Setup Time of SDIx Data Input to SCKx Edge
TDIV2SCL
100
ns
73A
74
TB2B
Last Clock Edge of Byte 1 to the 1st Clock Edge 1.5 TCY + 40
of Byte 2
—
—
ns (Note 2)
TSCH2DIL, Hold Time of SDIx Data Input to SCKx Edge
TSCL2DIL
100
ns
75
76
78
79
80
TDOR
TDOF
TSCR
TSCF
SDOx Data Output Rise Time
—
—
—
—
—
25
25
25
25
50
ns
ns
ns
ns
ns
SDOx Data Output Fall Time
SCKx Output Rise Time (Master mode)
SCKx Output Fall Time (Master mode)
TSCH2DOV, SDOx Data Output Valid after SCKx Edge
TSCL2DOV
81
TDOV2SCH, SDOx Data Output Setup to SCKx Edge
TDOV2SCL
TCY
—
ns
Note 1: Requires the use of Parameter #73A.
2: Only if Parameter #71A and #72A are used.
DS39682C-page 318
Preliminary
© 2007 Microchip Technology Inc.
PIC18F45J10 FAMILY
FIGURE 23-12:
EXAMPLE SPI™ SLAVE MODE TIMING (CKE = 0)
SSx
70
SCKx
(CKP = 0)
83
71
72
78
79
79
78
SCKx
(CKP = 1)
80
MSb
LSb
SDOx
SDIx
bit 6 - - - - - - 1
75, 76
77
MSb In
74
bit 6 - - - - 1
LSb In
73
Note:
Refer to Figure 23-3 for load conditions.
TABLE 23-16: EXAMPLE SPI™ MODE REQUIREMENTS (SLAVE MODE TIMING, CKE = 0)
Param
No.
Symbol
Characteristic
Min
Max Units Conditions
70
TSSL2SCH, SSx ↓ to SCKx ↓ or SCKx ↑ Input
TSSL2SCL
TCY
—
ns
71
TSCH
SCKx Input High Time
(Slave mode)
Continuous
Single Byte
Continuous
Single Byte
1.25 TCY + 30
—
—
—
—
—
ns
71A
72
40
1.25 TCY + 30
40
ns (Note 1)
TSCL
SCKx Input Low Time
(Slave mode)
ns
72A
73
ns (Note 1)
TDIV2SCH, Setup Time of SDIx Data Input to SCKx Edge
TDIV2SCL
100
ns
73A
74
TB2B
Last Clock Edge of Byte 1 to the First Clock Edge of Byte 2 1.5 TCY + 40
—
—
ns (Note 2)
TSCH2DIL, Hold Time of SDIx Data Input to SCKx Edge
TSCL2DIL
100
ns
75
76
77
78
79
80
TDOR
TDOF
SDOx Data Output Rise Time
SDOx Data Output Fall Time
—
—
10
—
—
—
25
25
50
25
25
50
ns
ns
ns
ns
ns
ns
TSSH2DOZ SSx ↑ to SDOx Output High-Impedance
TSCR
TSCF
SCKx Output Rise Time (Master mode)
SCKx Output Fall Time (Master mode)
TSCH2DOV, SDOx Data Output Valid after SCKx Edge
TSCL2DOV
83
TSCH2SSH, SSx ↑ after SCKx Edge
TSCL2SSH
1.5 TCY + 40
—
ns
Note 1: Requires the use of Parameter #73A.
2: Only if Parameter #71A and #72A are used.
© 2007 Microchip Technology Inc.
Preliminary
DS39682C-page 319
PIC18F45J10 FAMILY
FIGURE 23-13:
EXAMPLE SPI™ SLAVE MODE TIMING (CKE = 1)
82
SSx
70
SCKx
83
(CKP = 0)
71
72
SCKx
(CKP = 1)
80
MSb
bit 6 - - - - - - 1
LSb
SDOx
SDIx
75, 76
77
MSb In
74
bit 6 - - - - 1
LSb In
Note: Refer to Figure 23-3 for load conditions.
TABLE 23-17: EXAMPLE SPI™ SLAVE MODE REQUIREMENTS (CKE = 1)
Param
No.
Symbol
Characteristic
Min
Max Units Conditions
70
TSSL2SCH, SSx ↓ to SCKx ↓ or SCKx ↑ Input
TSSL2SCL
TCY
—
ns
71
TSCH
TSCL
TB2B
SCKx Input High Time
(Slave mode)
Continuous
Single Byte
Continuous
Single Byte
1.25 TCY + 30
—
—
—
—
—
—
ns
71A
72
40
1.25 TCY + 30
40
ns (Note 1)
ns
SCKx Input Low Time
(Slave mode)
72A
73A
74
ns (Note 1)
ns (Note 2)
ns
Last Clock Edge of Byte 1 to the First Clock Edge of Byte 2 1.5 TCY + 40
TSCH2DIL, Hold Time of SDIx Data Input to SCKx Edge
TSCL2DIL
100
75
76
77
78
79
80
TDOR
TDOF
SDOx Data Output Rise Time
SDOx Data Output Fall Time
—
—
10
—
—
—
25
25
50
25
25
50
ns
ns
ns
ns
ns
ns
TSSH2DOZ SSx ↑ to SDOx Output High-Impedance
TSCR
TSCF
SCKx Output Rise Time (Master mode)
SCKx Output Fall Time (Master mode)
TSCH2DOV, SDOx Data Output Valid after SCKx Edge
TSCL2DOV
82
83
TSSL2DOV SDOx Data Output Valid after SSx ↓ Edge
—
50
—
ns
ns
TSCH2SSH, SSx ↑ after SCKx Edge
TSCL2SSH
1.5 TCY + 40
Note 1: Requires the use of Parameter #73A.
2: Only if Parameter #71A and #72A are used.
DS39682C-page 320
Preliminary
© 2007 Microchip Technology Inc.
PIC18F45J10 FAMILY
FIGURE 23-14:
SCLx
I2C™ BUS START/STOP BITS TIMING
91
93
90
92
SDAx
Stop
Condition
Start
Condition
Note: Refer to Figure 23-3 for load conditions.
TABLE 23-18: I2C™ BUS START/STOP BITS REQUIREMENTS (SLAVE MODE)
Param.
Symbol
Characteristic
Min
Max
Units
Conditions
No.
90
TSU:STA Start Condition
Setup Time
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
4700
600
—
—
—
—
—
—
—
—
ns
Only relevant for Repeated
Start condition
91
92
93
THD:STA Start Condition
Hold Time
4000
600
ns
ns
ns
After this period, the first
clock pulse is generated
TSU:STO Stop Condition
Setup Time
4700
600
THD:STO Stop Condition
Hold Time
4000
600
FIGURE 23-15:
I2C™ BUS DATA TIMING
103
102
100
101
SCLx
90
106
107
91
92
SDAx
In
110
109
109
SDAx
Out
Note: Refer to Figure 23-3 for load conditions.
© 2007 Microchip Technology Inc.
Preliminary
DS39682C-page 321
PIC18F45J10 FAMILY
TABLE 23-19: I2C™ BUS DATA REQUIREMENTS (SLAVE MODE)
Param.
No.
Symbol
Characteristic
100 kHz mode
Min
Max
Units
Conditions
100
THIGH
Clock High Time
Clock Low Time
4.0
0.6
—
—
μs
μs
400 kHz mode
MSSP Module
100 kHz mode
400 kHz mode
MSSP Module
1.5 TCY
4.7
—
101
TLOW
—
μs
μs
1.3
—
1.5 TCY
—
—
102
103
TR
SDAx and SCLx Rise Time 100 kHz mode
400 kHz mode
1000
300
ns
ns
20 + 0.1 CB
CB is specified to be from
10 to 400 pF
TF
SDAx and SCLx Fall Time 100 kHz mode
400 kHz mode
—
300
300
ns
ns
20 + 0.1 CB
CB is specified to be from
10 to 400 pF
90
TSU:STA
Start Condition Setup Time 100 kHz mode
400 kHz mode
4.7
0.6
4.0
0.6
0
—
—
μs
μs
μs
μs
ns
μs
ns
ns
μs
μs
ns
ns
μs
μs
Only relevant for Repeated
Start condition
91
THD:STA Start Condition Hold Time 100 kHz mode
400 kHz mode
—
After this period, the first clock
pulse is generated
—
106
107
92
THD:DAT Data Input Hold Time
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
—
0
0.9
—
TSU:DAT Data Input Setup Time
250
100
4.7
0.6
—
(Note 2)
—
TSU:STO Stop Condition Setup Time 100 kHz mode
400 kHz mode
—
—
109
110
TAA
Output Valid from Clock
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
3500
—
(Note 1)
—
TBUF
Bus Free Time
4.7
1.3
—
Time the bus must be free
before a new transmission can
start
—
D102
CB
Bus Capacitive Loading
—
400
pF
Note 1: As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region (min. 300 ns)
of the falling edge of SCLx to avoid unintended generation of Start or Stop conditions.
2
2
2: A Fast mode I C™ bus device can be used in a Standard mode I C bus system, but the requirement, TSU:DAT ≥ 250 ns,
must then be met. This will automatically be the case if the device does not stretch the LOW period of the SCLx signal.
If such a device does stretch the LOW period of the SCLx signal, it must output the next data bit to the SDAx line,
2
TR max. + TSU:DAT = 1000 + 250 = 1250 ns (according to the Standard mode I C bus specification), before the SCLx
line is released.
DS39682C-page 322
Preliminary
© 2007 Microchip Technology Inc.
PIC18F45J10 FAMILY
FIGURE 23-16:
SCLx
MASTER SSP I2C™ BUS START/STOP BITS TIMING WAVEFORMS
93
91
90
92
SDAx
Stop
Condition
Start
Condition
Note: Refer to Figure 23-3 for load conditions.
TABLE 23-20: MASTER SSP I2C™ BUS START/STOP BITS REQUIREMENTS
Param.
Symbol
Characteristic
Min
Max Units
Conditions
No.
90
TSU:STA Start Condition
Setup Time
100 kHz mode
400 kHz mode
1 MHz mode(1) 2(TOSC)(BRG + 1)
2(TOSC)(BRG + 1)
2(TOSC)(BRG + 1)
—
—
—
—
—
—
—
—
—
—
—
—
ns Only relevant for
Repeated Start
condition
91
92
93
THD:STA Start Condition
Hold Time
100 kHz mode
2(TOSC)(BRG + 1)
ns After this period, the
first clock pulse is
generated
400 kHz mode
1 MHz mode(1) 2(TOSC)(BRG + 1)
2(TOSC)(BRG + 1)
TSU:STO Stop Condition
Setup Time
100 kHz mode
2(TOSC)(BRG + 1)
ns
400 kHz mode
1 MHz mode(1) 2(TOSC)(BRG + 1)
2(TOSC)(BRG + 1)
THD:STO Stop Condition
Hold Time
100 kHz mode
2(TOSC)(BRG + 1)
ns
400 kHz mode
2(TOSC)(BRG + 1)
1 MHz mode(1) 2(TOSC)(BRG + 1)
Note 1: Maximum pin capacitance = 10 pF for all I2C™ pins.
FIGURE 23-17:
MASTER SSP I2C™ BUS DATA TIMING
103
102
100
101
SCLx
90
106
91
92
107
SDAx
In
110
109
109
SDAx
Out
Note: Refer to Figure 23-3 for load conditions.
© 2007 Microchip Technology Inc.
Preliminary
DS39682C-page 323
PIC18F45J10 FAMILY
TABLE 23-21: MASTER SSP I2C™ BUS DATA REQUIREMENTS
Param.
Symbol
Characteristic
Min
Max Units
Conditions
No.
100
THIGH
Clock High Time 100 kHz mode
400 kHz mode
2(TOSC)(BRG + 1)
2(TOSC)(BRG + 1)
—
—
ms
ms
ms
ms
ms
ms
ns
1 MHz mode(1) 2(TOSC)(BRG + 1)
—
101
102
103
90
TLOW
TR
Clock Low Time 100 kHz mode
400 kHz mode
2(TOSC)(BRG + 1)
—
2(TOSC)(BRG + 1)
—
1 MHz mode(1) 2(TOSC)(BRG + 1)
—
SDAx and SCLx 100 kHz mode
—
1000
300
300
300
300
100
—
CB is specified to be from
10 to 400 pF
Rise Time
400 kHz mode
1 MHz mode(1)
20 + 0.1 CB
ns
—
—
ns
TF
SDAx and SCLx 100 kHz mode
ns
CB is specified to be from
10 to 400 pF
Fall Time
400 kHz mode
20 + 0.1 CB
—
ns
1 MHz mode(1)
ns
TSU:STA Start Condition 100 kHz mode
2(TOSC)(BRG + 1)
ms Only relevant for
Setup Time
Repeated Start
condition
ms
400 kHz mode
1 MHz mode(1) 2(TOSC)(BRG + 1)
2(TOSC)(BRG + 1)
—
ms
—
91
THD:STA Start Condition 100 kHz mode
2(TOSC)(BRG + 1)
—
ms After this period, the first
Hold Time
clock pulse is generated
400 kHz mode
2(TOSC)(BRG + 1)
—
ms
1 MHz mode(1) 2(TOSC)(BRG + 1)
—
ms
ns
106
107
92
THD:DAT Data Input
Hold Time
100 kHz mode
400 kHz mode
1 MHz mode(1)
100 kHz mode
400 kHz mode
1 MHz mode(1)
100 kHz mode
400 kHz mode
0
—
0
0.9
—
ms
ns
TBD
250
TSU:DAT Data Input
Setup Time
—
ns
ns
(Note 2)
100
—
TBD
—
ns
TSU:STO Stop Condition
Setup Time
2(TOSC)(BRG + 1)
—
ms
ms
ms
ns
2(TOSC)(BRG + 1)
—
1 MHz mode(1) 2(TOSC)(BRG + 1)
—
109
110
D102
TAA
TBUF
CB
Output Valid
from Clock
100 kHz mode
400 kHz mode
1 MHz mode(1)
100 kHz mode
400 kHz mode
1 MHz mode(1)
—
—
3500
1000
—
ns
—
ns
Bus Free Time
4.7
1.3
TBD
—
—
ms Time the bus must be free
before a new transmission
—
ms
can start
ms
—
Bus Capacitive Loading
400
pF
Legend: TBD = To Be Determined
Note 1: Maximum pin capacitance = 10 pF for all I2C™ pins.
2: A Fast mode I2C bus device can be used in a Standard mode I2C bus system, but parameter #107 ≥ 250 ns
must then be met. This will automatically be the case if the device does not stretch the LOW period of the
SCLx signal. If such a device does stretch the LOW period of the SCLx signal, it must output the next data
bit to the SDAx line, parameter #102 + parameter #107 = 1000 + 250 = 1250 ns (for 100 kHz mode), before
the SCLx line is released.
DS39682C-page 324
Preliminary
© 2007 Microchip Technology Inc.
PIC18F45J10 FAMILY
FIGURE 23-18:
EUSART SYNCHRONOUS TRANSMISSION (MASTER/SLAVE) TIMING
TX/CK
pin
121
121
RX/DT
pin
120
Note: Refer to Figure 23-3 for load conditions.
122
TABLE 23-22: EUSART SYNCHRONOUS TRANSMISSION REQUIREMENTS
Param
Symbol
Characteristic
Min
Max
Units Conditions
No.
120
TCKH2DTV SYNC XMIT (MASTER and SLAVE)
Clock High to Data Out Valid
—
—
—
40
20
20
ns
ns
ns
121
122
TCKRF
TDTRF
Clock Out Rise Time and Fall Time (Master mode)
Data Out Rise Time and Fall Time
FIGURE 23-19:
EUSART SYNCHRONOUS RECEIVE (MASTER/SLAVE) TIMING
TX/CK
pin
125
RX/DT
pin
126
Note: Refer to Figure 23-3 for load conditions.
TABLE 23-23: EUSART SYNCHRONOUS RECEIVE REQUIREMENTS
Param.
Symbol
Characteristic
Min
Max
Units
Conditions
No.
125
TDTV2CKL SYNC RCV (MASTER and SLAVE)
Data Hold before CK ↓ (DT hold time)
10
15
—
—
ns
ns
126
TCKL2DTL Data Hold after CK ↓ (DT hold time)
© 2007 Microchip Technology Inc.
Preliminary
DS39682C-page 325
PIC18F45J10 FAMILY
TABLE 23-24: A/D CONVERTER CHARACTERISTICS: PIC18F24J10/25J10/44J10/45J10 (INDUSTRIAL)
Param
Symbol
Characteristic
Min
Typ
Max
Units
Conditions
No.
A01
NR
Resolution
—
—
—
—
—
—
10
bit ΔVREF ≥ 3.0V
A03
A04
A06
A07
A10
A20
EIL
Integral Linearity Error
Differential Linearity Error
Offset Error
—
<±1
<±1
<±3
<±3
LSb ΔVREF ≥ 3.0V
LSb ΔVREF ≥ 3.0V
LSb ΔVREF ≥ 3.0V
LSb ΔVREF ≥ 3.0V
EDL
EOFF
EGN
—
—
—
Gain Error
—
Monotonicity
Guaranteed(1)
—
VSS ≤ VAIN ≤ VREF
VDD < 3.0V
VDD ≥ 3.0V
ΔVREF Reference Voltage Range
1.8
3
—
—
—
—
V
V
(VREFH – VREFL)
A21
A22
A25
A30
VREFH Reference Voltage High
VSS
—
VREFH
VDD – 3.0V
VREFH
V
V
VREFL
VAIN
Reference Voltage Low
Analog Input Voltage
VSS – 0.3V
VREFL
—
—
—
—
V
ZAIN
Recommended Impedance of
Analog Voltage Source
2.2
kΩ
A50
IREF
VREF Input Current(2)
—
—
—
—
5
150
μA During VAIN acquisition.
μA During A/D conversion
cycle.
Note 1: The A/D conversion result never decreases with an increase in the input voltage and has no missing codes.
2: VREFH current is from RA3/AN3/VREF+ pin or VDD, whichever is selected as the VREFH source.
VREFL current is from RA2/AN2/VREF- pin or VSS, whichever is selected as the VREFL source.
3: Maximum allowed impedance is 8.8 kΩ. This requires higher acquisition time than described in the A/D
chapter.
FIGURE 23-20:
A/D CONVERSION TIMING
BSF ADCON0, GO
(Note 2)
131
130
Q4
132
A/D CLK
. . .
. . .
9
8
7
2
1
0
A/D DATA
ADRES
NEW_DATA
TCY
OLD_DATA
ADIF
GO
DONE
SAMPLING STOPPED
SAMPLE
Note 1: If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts.
This allows the SLEEPinstruction to be executed.
2: This is a minimal RC delay (typically 100 ns), which also disconnects the holding capacitor from the analog input.
DS39682C-page 326
Preliminary
© 2007 Microchip Technology Inc.
PIC18F45J10 FAMILY
TABLE 23-25: A/D CONVERSION REQUIREMENTS
Param
Symbol
Characteristic
Min
Max
Units
Conditions
No.
130
TAD
A/D Clock Period
0.7
TBD
11
25.0(1)
μs TOSC based, VREF ≥ 2.0V
μs A/D RC mode
TAD
1
131
132
135
TCNV
TACQ
TSWC
Conversion Time
(not including acquisition time) (Note 2)
12
Acquisition Time (Note 3)
1.4
TBD
—
—
μs -40°C to +85°C
μs
0°C ≤ to ≤ +85°C
Switching Time from Convert → Sample
—
(Note 4)
Legend: TBD = To Be Determined
Note 1: The time of the A/D clock period is dependent on the device frequency and the TAD clock divider.
2: ADRES registers may be read on the following TCY cycle.
3: The time for the holding capacitor to acquire the “New” input voltage when the voltage changes full scale
after the conversion (VDD to VSS or VSS to VDD). The source impedance (RS) on the input channels is 50Ω.
4: On the following cycle of the device clock.
© 2007 Microchip Technology Inc.
Preliminary
DS39682C-page 327
PIC18F45J10 FAMILY
NOTES:
DS39682C-page 328
Preliminary
© 2007 Microchip Technology Inc.
PIC18F45J10 FAMILY
24.0 DC AND AC
CHARACTERISTICS GRAPHS
AND TABLES
Graphs and tables are not available at this time.
© 2007 Microchip Technology Inc.
Preliminary
DS39682C-page 329
PIC18F45J10 FAMILY
NOTES:
DS39682C-page 330
Preliminary
© 2007 Microchip Technology Inc.
PIC18F45J10 FAMILY
25.0 PACKAGING INFORMATION
25.1 Package Marking Information
28-Lead SPDIP
Example
PIC18F24J10
XXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXX
e
3
-I/SP
YYWWNNN
0710017
28-Lead SOIC
Example
XXXXXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXXXXX
PIC18F24J10-I/SO
0710017
e
3
YYWWNNN
28-Lead SSOP
Example
PIC18F24J10
XXXXXXXXXXXX
XXXXXXXXXXXX
e
3
-I/SS
YYWWNNN
0710017
28-Lead QFN
Example
XXXXXXXX
XXXXXXXX
YYWWNNN
18F24J10
-I/ML
0710017
e
3
Legend: XX...X Customer-specific information
Y
Year code (last digit of calendar year)
YY
WW
NNN
Year code (last 2 digits of calendar year)
Week code (week of January 1 is week ‘01’)
Alphanumeric traceability code
e
3
Pb-free JEDEC designator for Matte Tin (Sn)
*
This package is Pb-free. The Pb-free JEDEC designator (
can be found on the outer packaging for this package.
)
e3
Note: In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
© 2007 Microchip Technology Inc.
Preliminary
DS39682C-page 331
PIC18F45J10 FAMILY
Package Marking Information (Continued)
40-Lead PDIP
Example
XXXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXXX
e3
PIC18F44J10-I/P
0710017
YYWWNNN
44-Lead QFN
Example
XXXXXXXXXX
XXXXXXXXXX
XXXXXXXXXX
YYWWNNN
18F44J10
3
e
-I/ML
0710017
44-Lead TQFP
Example
XXXXXXXXXX
XXXXXXXXXX
XXXXXXXXXX
YYWWNNN
18F45J10
I/PT
0710017
e
3
DS39682C-page 332
Preliminary
© 2007 Microchip Technology Inc.
PIC18F45J10 FAMILY
25.2 Package Details
The following sections give the technical details of the packages.
28-Lead Skinny Plastic Dual In-Line (SP) – 300 mil Body [SPDIP]
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
N
NOTE 1
E1
1
2 3
D
E
A2
A
L
c
b1
A1
b
e
eB
Units
INCHES
NOM
28
Dimension Limits
MIN
MAX
Number of Pins
Pitch
N
e
.100 BSC
–
Top to Seating Plane
A
–
.200
.150
–
Molded Package Thickness
Base to Seating Plane
Shoulder to Shoulder Width
Molded Package Width
Overall Length
A2
A1
E
.120
.015
.290
.240
1.345
.110
.008
.040
.014
–
.135
–
.310
.285
1.365
.130
.010
.050
.018
–
.335
.295
1.400
.150
.015
.070
.022
.430
E1
D
Tip to Seating Plane
Lead Thickness
L
c
Upper Lead Width
b1
b
Lower Lead Width
Overall Row Spacing §
eB
Notes:
1. Pin 1 visual index feature may vary, but must be located within the hatched area.
2. § Significant Characteristic.
3. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" per side.
4. Dimensioning and tolerancing per ASME Y14.5M.
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
Microchip Technology Drawing C04-070B
© 2007 Microchip Technology Inc.
Preliminary
DS39682C-page 333
PIC18F45J10 FAMILY
28-Lead Plastic Small Outline (SO) – Wide, 7.50 mm Body [SOIC]
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
D
N
E
E1
NOTE 1
1
2
3
e
b
h
α
h
c
φ
A2
A
L
A1
L1
β
Units
MILLMETERS
Dimension Limits
MIN
NOM
MAX
Number of Pins
Pitch
N
e
28
1.27 BSC
Overall Height
A
–
–
2.65
–
Molded Package Thickness
Standoff §
A2
A1
E
2.05
0.10
–
–
0.30
Overall Width
10.30 BSC
Molded Package Width
Overall Length
Chamfer (optional)
Foot Length
E1
D
h
7.50 BSC
17.90 BSC
0.25
0.40
–
0.75
1.27
L
–
Footprint
L1
φ
1.40 REF
Foot Angle Top
Lead Thickness
Lead Width
0°
0.18
0.31
5°
–
–
–
–
–
8°
c
0.33
0.51
15°
b
Mold Draft Angle Top
Mold Draft Angle Bottom
α
β
5°
15°
Notes:
1. Pin 1 visual index feature may vary, but must be located within the hatched area.
2. § Significant Characteristic.
3. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.15 mm per side.
4. Dimensioning and tolerancing per ASME Y14.5M.
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
REF: Reference Dimension, usually without tolerance, for information purposes only.
Microchip Technology Drawing C04-052B
DS39682C-page 334
Preliminary
© 2007 Microchip Technology Inc.
PIC18F45J10 FAMILY
28-Lead Plastic Shrink Small Outline (SS) – 5.30 mm Body [SSOP]
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
D
N
E
E1
1
2
b
NOTE 1
e
c
A2
A
φ
A1
L
L1
Units
MILLIMETERS
Dimension Limits
MIN
NOM
MAX
Number of Pins
Pitch
N
e
28
0.65 BSC
Overall Height
Molded Package Thickness
Standoff
A
–
–
1.75
–
2.00
1.85
–
A2
A1
E
1.65
0.05
7.40
5.00
9.90
0.55
Overall Width
Molded Package Width
Overall Length
Foot Length
7.80
5.30
10.20
0.75
1.25 REF
–
8.20
5.60
10.50
0.95
E1
D
L
Footprint
L1
c
Lead Thickness
Foot Angle
0.09
0°
0.25
8°
φ
4°
Lead Width
b
0.22
–
0.38
Notes:
1. Pin 1 visual index feature may vary, but must be located within the hatched area.
2. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.20 mm per side.
3. Dimensioning and tolerancing per ASME Y14.5M.
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
REF: Reference Dimension, usually without tolerance, for information purposes only.
Microchip Technology Drawing C04-073B
© 2007 Microchip Technology Inc.
Preliminary
DS39682C-page 335
PIC18F45J10 FAMILY
28-Lead Plastic Quad Flat, No Lead Package (ML) – 6x6 mm Body [QFN]
with 0.55 mm Contact Length
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
D
D2
EXPOSED
PAD
e
E
b
E2
2
1
2
1
K
N
N
NOTE 1
L
BOTTOM VIEW
TOP VIEW
A
A3
A1
Units
MILLIMETERS
NOM
Dimension Limits
MIN
MAX
Number of Pins
N
e
28
Pitch
0.65 BSC
0.90
Overall Height
Standoff
A
0.80
0.00
1.00
0.05
A1
A3
E
0.02
Contact Thickness
Overall Width
0.20 REF
6.00 BSC
3.70
Exposed Pad Width
Overall Length
Exposed Pad Length
Contact Width
Contact Length
Contact-to-Exposed Pad
E2
D
3.65
4.20
6.00 BSC
3.70
D2
b
3.65
0.23
0.50
0.20
4.20
0.35
0.70
–
0.30
L
0.55
K
–
Notes:
1. Pin 1 visual index feature may vary, but must be located within the hatched area.
2. Package is saw singulated.
3. Dimensioning and tolerancing per ASME Y14.5M.
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
REF: Reference Dimension, usually without tolerance, for information purposes only.
Microchip Technology Drawing C04-105B
DS39682C-page 336
Preliminary
© 2007 Microchip Technology Inc.
PIC18F45J10 FAMILY
40-Lead Plastic Dual In-Line (P) – 600 mil Body [PDIP]
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
N
NOTE 1
E1
1 2 3
D
E
A2
A
L
c
b1
b
A1
e
eB
Units
INCHES
Dimension Limits
MIN
NOM
MAX
Number of Pins
Pitch
N
e
40
.100 BSC
Top to Seating Plane
Molded Package Thickness
Base to Seating Plane
Shoulder to Shoulder Width
Molded Package Width
Overall Length
A
–
–
–
–
–
–
–
–
–
–
–
–
.250
.195
–
A2
A1
E
.125
.015
.590
.485
1.980
.115
.008
.030
.014
–
.625
.580
2.095
.200
.015
.070
.023
.700
E1
D
Tip to Seating Plane
Lead Thickness
L
c
Upper Lead Width
b1
b
Lower Lead Width
Overall Row Spacing §
eB
Notes:
1. Pin 1 visual index feature may vary, but must be located within the hatched area.
2. § Significant Characteristic.
3. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" per side.
4. Dimensioning and tolerancing per ASME Y14.5M.
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
Microchip Technology Drawing C04-016B
© 2007 Microchip Technology Inc.
Preliminary
DS39682C-page 337
PIC18F45J10 FAMILY
44-Lead Plastic Quad Flat, No Lead Package (ML) – 8x8 mm Body [QFN]
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
D2
D
EXPOSED
PAD
e
b
K
E
E2
2
1
2
1
N
N
NOTE 1
L
TOP VIEW
BOTTOM VIEW
A
A3
A1
Units
MILLIMETERS
Dimension Limits
MIN
NOM
44
MAX
Number of Pins
N
e
Pitch
0.65 BSC
0.90
Overall Height
Standoff
A
0.80
0.00
1.00
0.05
A1
A3
E
0.02
Contact Thickness
Overall Width
0.20 REF
8.00 BSC
6.45
Exposed Pad Width
Overall Length
Exposed Pad Length
Contact Width
Contact Length
Contact-to-Exposed Pad
E2
D
6.30
6.80
8.00 BSC
6.45
D2
b
6.30
0.25
0.30
0.20
6.80
0.38
0.50
–
0.30
L
0.40
K
–
Notes:
1. Pin 1 visual index feature may vary, but must be located within the hatched area.
2. Package is saw singulated.
3. Dimensioning and tolerancing per ASME Y14.5M.
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
REF: Reference Dimension, usually without tolerance, for information purposes only.
Microchip Technology Drawing C04-103B
DS39682C-page 338
Preliminary
© 2007 Microchip Technology Inc.
PIC18F45J10 FAMILY
44-Lead Plastic Thin Quad Flatpack (PT) – 10x10x1 mm Body, 2.00 mm Footprint [TQFP]
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
D
D1
E
e
E1
N
b
NOTE 1
1 2 3
NOTE 2
α
A
c
φ
A2
β
A1
L
L1
Units
MILLIMETERS
Dimension Limits
MIN
NOM
44
MAX
Number of Leads
Lead Pitch
N
e
0.80 BSC
–
Overall Height
A
–
1.20
1.05
0.15
0.75
Molded Package Thickness
Standoff
A2
A1
L
0.95
0.05
0.45
1.00
–
Foot Length
0.60
Footprint
L1
φ
1.00 REF
3.5°
Foot Angle
0°
7°
Overall Width
E
12.00 BSC
12.00 BSC
10.00 BSC
10.00 BSC
–
Overall Length
D
Molded Package Width
Molded Package Length
Lead Thickness
Lead Width
E1
D1
c
0.09
0.30
11°
0.20
0.45
13°
b
0.37
Mold Draft Angle Top
Mold Draft Angle Bottom
α
β
12°
11°
12°
13°
Notes:
1. Pin 1 visual index feature may vary, but must be located within the hatched area.
2. Chamfers at corners are optional; size may vary.
3. Dimensions D1 and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.25 mm per side.
4. Dimensioning and tolerancing per ASME Y14.5M.
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
REF: Reference Dimension, usually without tolerance, for information purposes only.
Microchip Technology Drawing C04-076B
© 2007 Microchip Technology Inc.
Preliminary
DS39682C-page 339
PIC18F45J10 FAMILY
NOTES:
DS39682C-page 340
Preliminary
© 2007 Microchip Technology Inc.
PIC18F45J10 FAMILY
APPENDIX A: REVISION HISTORY
APPENDIX B: MIGRATION
BETWEEN HIGH-END
DEVICE FAMILIES
Revision A (March 2005)
Original data sheet for PIC18F45J10 family devices.
Devices in the PIC18F45J10 family and PIC18F4520
families are very similar in their functions and feature
sets. However, there are some potentially important
differences which should be considered when
migrating an application across device families to
achieve a new design goal. These are summarized in
Table B-1. The areas of difference which could be a
major impact on migration are discussed in greater
detail later in this section.
Revision C (January 2007)
This revision includes updates to the packaging
diagrams.
TABLE B-1:
NOTABLE DIFFERENCES BETWEEN PIC18F4520 AND PIC18FXXXX FAMILIES
Characteristic
PIC18FXXXX Family
PIC18F4520 Family
Operating Frequency
Supply Voltage
40 MHz @ 2.15V
40 MHz @ 4.2V
2.0V-3.6V
2.0V-5.5V
Operating Current
Program Memory Endurance
I/O Sink/Source at 25 mA
Input Voltage Tolerance on I/O pins
I/O
Low
1,000 write/erase cycles (typical)
PORTB and PORTC only
5.5V on digital only pins
32
Lower
100,000 write/erase cycles (typical)
All ports
VDD on all I/O pins
36
Pull-ups
PORTB
PORTB
Oscillator Options
Limited options
(EC, HS, fixed 32 kHz INTRC)
More options (EC, HS, XT, LP, RC,
PLL, flexible INTRC)
Program Memory Retention
Programming Time (Normalized)
Programming Entry
10 years (minimum)
156 μs/byte (10 ms/64-byte block)
Low Voltage, Key Sequence
Single block, all or nothing
40 years (minimum)
15.6 μs/byte (1 ms/64-byte block)
VPP and LVP
Code Protection
Multiple code protection blocks
Configuration Words
Stored in last 4 words of
Program Memory space
Stored in Configuration Space,
starting at 300000h
Start-up Time from Sleep
Power-up Timer
Data EEPROM
BOR
200 μs (typical)
Always on
10 μs (typical)
Configurable
Available
Not available
Simple BOR(1)
Not available
Required
Programmable BOR
Available
LVD
A/D Calibration
In-Circuit Emulation
TMR3
Not required
Available
Not available
Not available
Available(2)
Available
Second MSSP
Not available
Note 1: BOR is not available on PIC18LFXXJ10 devices.
2: Available on 40/44-pin devices only.
© 2007 Microchip Technology Inc.
Preliminary
DS39682C-page 341
PIC18F45J10 FAMILY
B.1
Power Requirement Differences
B.3
Oscillator Differences
The most significant difference between the
PIC18F45J10 family and PIC18F4520 device families
is the power requirements. PIC18F45J10 family
devices are designed on a smaller process; this results
in lower maximum voltage and higher leakage current.
PIC18F4520 family devices have a greater range of
oscillator options than PIC18F45J10 family devices.
The latter family is limited primarily to operating modes
that support HS and EC oscillators.
In addition, the PIC18F45J10 family has an internal RC
oscillator with only a fixed 32 kHz output. The higher
frequency RC modes of the PIC18F4520 family are not
available.
The operating voltage range for PIC18F45J10 family
devices is 2.0V to 3.6V. One of the VDD pins is separated
for the core logic supply (VDDCORE). This pin has specific
voltage and capacitor requirements as described in
Section 23.0 “Electrical Characteristics”.
B.4
Peripherals
The current specifications for PIC18F45J10 family
devices are yet to be determined.
The PIC18F45J10 family is able to operate at 40 MHz
down to 2.15 volts unlike the PIC18F4520 family where
40 MHz operation is limited to 4.2 +V applications.
B.2
Pin Differences
Peripherals must also be considered when making a
conversion between the PIC18F45J10 family and the
PIC18F4520 families:
There are several differences in the pinouts between
the PIC18F45J10 family and the PIC18F4520 families:
• Input voltage tolerance
• Output current capabilities
• Available I/O
• Data EEPROM: PIC18F45J10 family devices do
not have this module.
• BOR: PIC18F45J10 family devices do not have a
programmable BOR. Simple brown-out capability
is provided through the use of the internal voltage
regulator (not available in PIC18LFXXJ10
devices).
Pins on the PIC18F45J10 family that have digital only
input capability will tolerate voltages up to 5.5V and are
thus tolerant to voltages above VDD. Table 9-1 in
Section 9.0 “I/O Ports” contains the complete list.
• LVD: PIC18F45J10 family devices do not have
In addition to input differences, there are output differ-
ences as well. Not all I/O pins can source or sink equal
levels of current. Only PORTB and PORTC support the
25 mA source/sink capability that is supported by all
output pins on the PIC18F4520. Table 9-2 in
Section 9.0 “I/O Ports” contains the complete list of
output capabilities.
this module.
• Timer3 (TMR3) has been removed from the
PIC18F45J10 family.
• The T0CKI/C1OUT pins have been moved from
RA4 to RB5.
• The 40/44-pin devices in the PIC18F45J10 family
have a second MSSP module available on pins
RD0:RD3
There are additional differences in how some pin func-
tions are implemented on PIC18F45J10 family
devices. First, the OSC1/OSC2 oscillator pins are
strictly dedicated to the external oscillator function;
there is no option to re-allocate these pins to I/O (RA6
or RA7) as on PIC18F4520 devices. Second, the
MCLR pin is dedicated only to MCLR and cannot be
configured as an input (RE3). Finally, RA4 does not
exist on PIC18F45J10 family devices.
All of these pin differences (including power pin
differences) should be accounted for when making a
conversion between PIC18F4520 and PIC18F45J10
family devices.
DS39682C-page 342
Preliminary
© 2007 Microchip Technology Inc.
PIC18F45J10 FAMILY
Comparator Analog Input Model............................... 223
Comparator I/O Operating Modes ............................ 220
Comparator Output................................................... 222
Comparator Voltage Reference................................ 226
Comparator Voltage Reference Output Buffer
Example ........................................................... 227
Compare Mode Operation........................................ 126
Device Clock............................................................... 26
Enhanced PWM........................................................ 133
EUSART Receive..................................................... 199
EUSART Transmit.................................................... 197
External Power-on Reset Circuit (Slow VDD
A
A/D.................................................................................... 209
A/D Converter Interrupt, Configuring ........................ 213
Acquisition Requirements ......................................... 214
ADCAL Bit................................................................. 216
ADCON0 Register..................................................... 209
ADCON1 Register..................................................... 209
ADCON2 Register..................................................... 209
ADRESH Register............................................. 209, 212
ADRESL Register ..................................................... 209
Analog Port Pins, Configuring................................... 216
Associated Registers ................................................ 218
Calculating the Minimum Required Acquisition Time 214
Calibration................................................................. 216
Configuring the Module............................................. 213
Conversion Clock (TAD) ............................................ 215
Conversion Status (GO/DONE Bit)........................... 212
Conversions.............................................................. 217
Converter Characteristics ......................................... 326
Operation in Power-Managed Modes ....................... 216
Selecting and Configuring Acquisition Time ............. 215
Special Event Trigger (CCP)..................................... 218
Special Event Trigger (ECCP) .................................. 132
Use of the CCP2 Trigger........................................... 218
Absolute Maximum Ratings .............................................. 295
AC (Timing) Characteristics.............................................. 309
Load Conditions for Device Timing Specifications.... 310
Parameter Symbology .............................................. 309
Temperature and Voltage Specifications.................. 310
Timing Conditions ..................................................... 310
Access Bank
Mapping with Indexed Literal Offset Mode.................. 65
ACKSTAT ......................................................................... 176
ACKSTAT Status Flag ...................................................... 176
ADCAL Bit......................................................................... 216
ADCON0 Register............................................................. 209
GO/DONE Bit............................................................ 212
ADCON1 Register............................................................. 209
ADCON2 Register............................................................. 209
ADDFSR ........................................................................... 284
ADDLW ............................................................................. 247
ADDULNK......................................................................... 284
ADDWF............................................................................. 247
ADDWFC .......................................................................... 248
ADRESH Register............................................................. 209
ADRESL Register ..................................................... 209, 212
Analog-to-Digital Converter. See A/D.
Power-up)........................................................... 39
Fail-Safe Clock Monitor ............................................ 238
Generic I/O Port Operation......................................... 93
Interrupt Logic............................................................. 80
2
MSSP (I C Master Mode)......................................... 170
2
MSSP (I C Mode)..................................................... 155
MSSP (SPI Mode) .................................................... 145
On-Chip Reset Circuit................................................. 37
PIC18F24J10/25J10................................................... 10
PIC18F44J10/45J10................................................... 11
PLL ............................................................................. 25
PORTD and PORTE (Parallel Slave Port)................ 109
PWM Operation (Simplified)..................................... 128
Reads from Flash Program Memory .......................... 71
Single Comparator.................................................... 221
Table Read Operation ................................................ 67
Table Write Operation ................................................ 68
Table Writes to Flash Program Memory..................... 73
Timer0 in 16-Bit Mode .............................................. 112
Timer0 in 8-Bit Mode ................................................ 112
Timer1 ...................................................................... 116
Timer1 (16-Bit Read/Write Mode)............................. 116
Timer2 ...................................................................... 122
Watchdog Timer ....................................................... 235
BN..................................................................................... 250
BNC .................................................................................. 251
BNN .................................................................................. 251
BNOV ............................................................................... 252
BNZ .................................................................................. 252
BOR. See Brown-out Reset.
BOV .................................................................................. 255
BRA .................................................................................. 253
Break Character (12-Bit) Transmit and Receive............... 202
BRG. See Baud Rate Generator.
Brown-out Reset (BOR)...................................................... 39
and On-Chip Voltage Regulator ............................... 236
Disabling in Sleep Mode............................................. 39
BSF................................................................................... 253
BTFSC.............................................................................. 254
BTFSS .............................................................................. 254
BTG .................................................................................. 255
BZ ..................................................................................... 256
ANDLW ............................................................................. 248
ANDWF............................................................................. 249
Assembler
MPASM Assembler................................................... 292
Auto-Wake-up on Sync Break Character.......................... 200
B
Bank Select Register (BSR)................................................ 53
Baud Rate Generator........................................................ 172
BC ..................................................................................... 249
BCF................................................................................... 250
BF ..................................................................................... 176
BF Status Flag .................................................................. 176
Block Diagrams
C
C Compilers
MPLAB C18.............................................................. 292
MPLAB C30.............................................................. 292
Calibration (A/D Converter) .............................................. 216
CALL................................................................................. 256
CALLW ............................................................................. 285
Capture (CCP Module) ..................................................... 125
Associated Registers................................................ 127
CCP Pin Configuration ............................................. 125
CCPRxH:CCPRxL Registers.................................... 125
A/D............................................................................ 212
Analog Input Model................................................... 213
Baud Rate Generator................................................ 172
Capture Mode Operation .......................................... 125
© 2007 Microchip Technology Inc.
Preliminary
DS39682C-page 343
PIC18F45J10 FAMILY
Prescaler...................................................................125
Software Interrupt .....................................................125
Capture (ECCP Module) ...................................................132
Capture/Compare/PWM (CCP).........................................123
Capture Mode. See Capture.
Pin Configuration ...................................................... 126
Software Interrupt ..................................................... 126
Special Event Trigger ....................................... 126, 218
Timer1 Mode Selection............................................. 126
Compare (ECCP Module)................................................. 132
Special Event Trigger ............................................... 132
Computed GOTO................................................................ 50
Configuration Bits ............................................................. 229
Configuration Register Protection..................................... 240
Context Saving During Interrupts........................................ 91
CPFSEQ........................................................................... 258
CPFSGT ........................................................................... 259
CPFSLT............................................................................ 259
Crystal Oscillator/Ceramic Resonator................................. 23
Customer Change Notification Service............................. 353
Customer Notification Service .......................................... 353
Customer Support............................................................. 353
CCP Modules and Timer Resources ........................124
CCPRxH Register.....................................................124
CCPRxL Register......................................................124
Compare Mode. See Compare.
Interactions Between ECCP1/CCP1 and CCP2 for
Timer Resources...............................................124
Module Configuration................................................124
Clock Sources.....................................................................26
Default System Clock on Reset ..................................27
Selection Using OSCCON Register............................27
CLRF.................................................................................257
CLRWDT...........................................................................257
Code Examples
D
16 x 16 Signed Multiply Routine .................................78
16 x 16 Unsigned Multiply Routine .............................78
8 x 8 Signed Multiply Routine .....................................77
8 x 8 Unsigned Multiply Routine .................................77
Changing Between Capture Prescalers....................125
Computed GOTO Using an Offset Value....................50
Erasing a Flash Program Memory Row ......................72
Fast Register Stack.....................................................50
How to Clear RAM (Bank 1) Using Indirect
Data Addressing Modes ..................................................... 61
Comparing Addressing Modes with the
Extended Instruction Set Enabled ...................... 64
Direct .......................................................................... 61
Indexed Literal Offset ................................................. 63
Instructions Affected........................................... 63
Indirect........................................................................ 61
Inherent and Literal..................................................... 61
Data Memory ...................................................................... 53
Access Bank............................................................... 55
and the Extended Instruction Set ............................... 63
Bank Select Register (BSR) ....................................... 53
General Purpose Registers ........................................ 55
Map for PIC18F24J10/44J10...................................... 54
Special Function Registers......................................... 56
DAW ................................................................................. 260
DC and AC Characteristics
Graphs and Tables ................................................... 329
DC Characteristics............................................................ 305
Power-Down and Supply Current ............................. 298
Supply Voltage ......................................................... 297
DCFSNZ ........................................................................... 261
DECF................................................................................ 260
DECFSZ ........................................................................... 261
Default System Clock ......................................................... 27
Development Support....................................................... 291
Device Overview................................................................... 7
Details on Individual Family Members.......................... 8
Features (table) ............................................................ 9
New Core Features....................................................... 7
Other Special Features................................................. 8
Direct Addressing ............................................................... 62
Addressing..........................................................61
Implementing a Real-Time Clock Using a
Timer1 Interrupt Service ...................................119
Initializing PORTA.......................................................94
Initializing PORTB.......................................................97
Initializing PORTC.....................................................100
Initializing PORTD.....................................................103
Initializing PORTE.....................................................106
Loading the SSP1BUF (SSP1SR) Register..............148
Reading a Flash Program Memory Word ...................71
Saving STATUS, WREG and BSR Registers in RAM 91
Writing to Flash Program Memory ..............................74
Code Protection ................................................................229
COMF................................................................................258
Comparator .......................................................................219
Analog Input Connection Considerations..................223
Associated Registers ................................................223
Configuration.............................................................220
Effects of a Reset......................................................222
Interrupts...................................................................222
Operation ..................................................................221
Operation During Sleep ............................................222
Outputs .....................................................................221
Reference .................................................................221
External Signal..................................................221
Internal Signal...................................................221
Response Time.........................................................221
Comparator Specifications................................................308
Comparator Voltage Reference ........................................225
Accuracy and Error ...................................................226
Associated Registers ................................................227
Configuring................................................................225
Connection Considerations.......................................226
Effects of a Reset......................................................226
Operation During Sleep ............................................226
Compare (CCP Module)....................................................126
Associated Registers ................................................127
CCPRx Register........................................................126
E
Effect on Standard PIC Instructions.................................. 288
Effects of Power-Managed Modes on Various
Clock Sources............................................................. 28
Electrical Characteristics .................................................. 295
Enhanced Capture/Compare/PWM (ECCP)..................... 131
Associated Registers................................................ 144
Capture and Compare Modes .................................. 132
Capture Mode. See Capture (ECCP Module).
Outputs and Configuration........................................ 132
Pin Configurations for ECCP1 Modes ...................... 132
PWM Mode. See PWM (ECCP Module).
Standard PWM Mode ............................................... 132
Timer Resources ...................................................... 132
DS39682C-page 344
Preliminary
© 2007 Microchip Technology Inc.
PIC18F45J10 FAMILY
Enhanced PWM Mode. See PWM (ECCP Module).......... 133
Enhanced Universal Synchronous Asynchronous
Receiver Transmitter (EUSART). See EUSART.
Equations
A/D Acquisition Time................................................. 214
A/D Minimum Charging Time.................................... 214
Errata .................................................................................... 6
EUSART
Reading ...................................................................... 71
Table Pointer
Boundaries Based on Operation ........................ 70
Table Pointer Boundaries........................................... 70
Table Reads and Table Writes................................... 67
Write Sequence.......................................................... 73
Writing To ................................................................... 73
Protection Against Spurious Writes.................... 75
Unexpected Termination .................................... 75
Write Verify......................................................... 75
FSCM. See Fail-Safe Clock Monitor.
Asynchronous Mode ................................................. 197
12-Bit Break Transmit and Receive .................. 202
Associated Registers, Receive ......................... 200
Associated Registers, Transmit ........................ 198
Auto-Wake-up on Sync Break .......................... 200
Receiver............................................................ 199
Setting Up 9-Bit Mode with Address Detect...... 199
Transmitter........................................................ 197
Baud Rate Generator
G
GOTO ............................................................................... 262
H
Hardware Multiplier............................................................. 77
Introduction................................................................. 77
Operation.................................................................... 77
Performance Comparison........................................... 77
Operation in Power-Managed Mode................. 191
Baud Rate Generator (BRG)..................................... 191
Associated Registers........................................ 192
Auto-Baud Rate Detect..................................... 195
Baud Rate Error, Calculating ............................ 192
Baud Rates, Asynchronous Modes .................. 193
High Baud Rate Select (BRGH Bit) .................. 191
Sampling........................................................... 191
Synchronous Master Mode....................................... 203
Associated Registers, Receive ......................... 205
Associated Registers, Transmit ........................ 204
Reception.......................................................... 205
Transmission .................................................... 203
Synchronous Slave Mode......................................... 206
Associated Registers, Receive ......................... 207
Associated Registers, Transmit ........................ 206
Reception.......................................................... 207
Transmission .................................................... 206
Extended Instruction Set
ADDFSR ................................................................... 284
ADDULNK................................................................. 284
and Using MPLAB Tools........................................... 290
CALLW...................................................................... 285
Considerations for Use ............................................. 288
MOVSF ..................................................................... 285
MOVSS..................................................................... 286
PUSHL...................................................................... 286
SUBFSR ................................................................... 287
SUBULNK................................................................. 287
Syntax....................................................................... 283
External Clock Input (EC Modes)........................................ 24
I
I/O Ports ............................................................................. 93
I C Mode (MSSP)
2
Acknowledge Sequence Timing ............................... 179
Associated Registers................................................ 185
Baud Rate Generator ............................................... 172
Bus Collision
During a Repeated Start Condition................... 183
During a Stop Condition ................................... 184
Clock Arbitration ....................................................... 173
Clock Stretching ....................................................... 165
10-Bit Slave Receive Mode (SEN = 1) ............. 165
10-Bit Slave Transmit Mode ............................. 165
7-Bit Slave Receive Mode (SEN = 1) ............... 165
7-Bit Slave Transmit Mode ............................... 165
Clock Synchronization and the CKP Bit ................... 166
Effects of a Reset ..................................................... 180
General Call Address Support.................................. 169
2
I C Clock Rate w/BRG ............................................. 172
Master Mode............................................................. 170
Baud Rate Generator ....................................... 172
Operation.......................................................... 171
Reception ......................................................... 176
Repeated Start Condition Timing ..................... 175
Start Condition Timing...................................... 174
Transmission .................................................... 176
Multi-Master Communication, Bus Collision and
Arbitration ......................................................... 180
Multi-Master Mode.................................................... 180
Operation.................................................................. 159
Read/Write Bit Information (R/W Bit)................ 159, 160
Registers .................................................................. 155
Serial Clock (SCKx/SCLx)........................................ 160
Slave Mode............................................................... 159
Addressing ....................................................... 159
Reception ......................................................... 160
Transmission .................................................... 160
Sleep Operation........................................................ 180
Stop Condition Timing .............................................. 179
INCF ................................................................................. 262
INCFSZ............................................................................. 263
In-Circuit Debugger........................................................... 240
In-Circuit Serial Programming (ICSP)....................... 229, 240
Indexed Literal Offset Addressing
F
Fail-Safe Clock Monitor............................................. 229, 238
Interrupts in Power-Managed Modes........................ 239
POR or Wake-up from Sleep .................................... 239
WDT During Oscillator Failure .................................. 238
Fast Register Stack............................................................. 50
Firmware Instructions........................................................ 241
Flash Configuration Words ............................................... 229
Flash Program Memory ...................................................... 67
Associated Registers .................................................. 75
Control Registers ........................................................ 68
EECON1 and EECON2 ...................................... 68
TABLAT (Table Latch) ........................................ 70
TBLPTR (Table Pointer) ..................................... 70
Erase Sequence ......................................................... 72
Erasing........................................................................ 72
Operation During Code-Protect .................................. 75
and Standard PIC18 Instructions.............................. 288
© 2007 Microchip Technology Inc.
Preliminary
DS39682C-page 345
PIC18F45J10 FAMILY
Indexed Literal Offset Mode..............................................288
Indirect Addressing .............................................................62
INFSNZ .............................................................................263
Initialization Conditions for All Registers....................... 43–46
Instruction Cycle..................................................................51
Clocking Scheme ........................................................51
Instruction Flow/Pipelining ..................................................51
Instruction Set ...................................................................241
ADDLW .....................................................................247
ADDWF.....................................................................247
ADDWF (Indexed Literal Offset Mode) .....................289
ADDWFC ..................................................................248
ANDLW .....................................................................248
ANDWF.....................................................................249
BC .............................................................................249
BCF...........................................................................250
BN .............................................................................250
BNC ..........................................................................251
BNN ..........................................................................251
BNOV........................................................................252
BNZ...........................................................................252
BOV ..........................................................................255
BRA...........................................................................253
BSF...........................................................................253
BSF (Indexed Literal Offset Mode) ...........................289
BTFSC ......................................................................254
BTFSS ......................................................................254
BTG...........................................................................255
BZ .............................................................................256
CALL .........................................................................256
CLRF.........................................................................257
CLRWDT...................................................................257
COMF .......................................................................258
CPFSEQ ...................................................................258
CPFSGT ...................................................................259
CPFSLT ....................................................................259
DAW..........................................................................260
DCFSNZ ...................................................................261
DECF ........................................................................260
DECFSZ....................................................................261
Extended Instruction Set...........................................283
General Format.........................................................243
GOTO .......................................................................262
INCF..........................................................................262
INCFSZ.....................................................................263
INFSNZ.....................................................................263
IORLW ......................................................................264
IORWF ......................................................................264
LFSR.........................................................................265
MOVF........................................................................265
MOVFF .....................................................................266
MOVLB .....................................................................266
MOVLW ....................................................................267
MOVWF ....................................................................267
MULLW .....................................................................268
MULWF.....................................................................268
NEGF ........................................................................269
NOP ..........................................................................269
Opcode Field Descriptions........................................242
POP ..........................................................................270
PUSH ........................................................................270
RCALL ......................................................................271
RESET ......................................................................271
RETFIE .....................................................................272
RETLW .....................................................................272
RETURN................................................................... 273
RLCF ........................................................................ 273
RLNCF...................................................................... 274
RRCF........................................................................ 274
RRNCF ..................................................................... 275
SETF ........................................................................ 275
SETF (Indexed Literal Offset Mode)......................... 289
SLEEP ...................................................................... 276
Standard Instructions................................................ 241
SUBFWB .................................................................. 276
SUBLW..................................................................... 277
SUBWF..................................................................... 277
SUBWFB .................................................................. 278
SWAPF..................................................................... 278
TBLRD...................................................................... 279
TBLWT ..................................................................... 280
TSTFSZ .................................................................... 281
XORLW .................................................................... 281
XORWF .................................................................... 282
INTCON Registers.............................................................. 81
2
Inter-Integrated Circuit. See I C Mode.
Internal Oscillator Block...................................................... 26
Internal RC Oscillator
Use with WDT........................................................... 235
Internet Address ............................................................... 353
Interrupt Sources .............................................................. 229
A/D Conversion Complete ........................................ 213
Capture Complete (CCP).......................................... 125
Compare Complete (CCP)........................................ 126
Interrupt-on-Change (RB7:RB4)................................. 97
INTn Pin...................................................................... 91
PORTB, Interrupt-on-Change..................................... 91
TMR0.......................................................................... 91
TMR0 Overflow......................................................... 113
TMR1 Overflow......................................................... 115
TMR2-to-PR2 Match (PWM)............................. 128, 133
Interrupts............................................................................. 79
Interrupts, Flag Bits
Interrupt-on-Change (RB7:RB4) Flag (RBIF Bit) ........ 97
INTOSC, INTRC. See Internal Oscillator Block.
IORLW.............................................................................. 264
IORWF.............................................................................. 264
IPR Registers...................................................................... 88
L
LFSR................................................................................. 265
M
Master Clear (MCLR).......................................................... 39
Master Synchronous Serial Port (MSSP). See MSSP.
Memory Organization ......................................................... 47
Data Memory .............................................................. 53
Program Memory........................................................ 47
Memory Programming Requirements............................... 307
Microchip Internet Web Site.............................................. 353
MOVF ............................................................................... 265
MOVFF ............................................................................. 266
MOVLB ............................................................................. 266
MOVLW ............................................................................ 267
MOVSF............................................................................. 285
MOVSS............................................................................. 286
MOVWF............................................................................ 267
MPLAB ASM30 Assembler, Linker, Librarian................... 292
MPLAB ICD 2 In-Circuit Debugger ................................... 293
MPLAB ICE 2000 High-Performance Universal
In-Circuit Emulator.................................................... 293
DS39682C-page 346
Preliminary
© 2007 Microchip Technology Inc.
PIC18F45J10 FAMILY
MPLAB ICE 4000 High-Performance Universal
RB5/KBI1/C1OUT....................................................... 18
RB5/KBI1/T0CKI/C1OUT ........................................... 14
RB6/KBI2/PGC..................................................... 14, 18
RB7/KBI3/PGD..................................................... 14, 18
RC0/T1OSO/T1CKI.............................................. 15, 19
RC1/T1OSI/CCP2 ................................................ 15, 19
RC2/CCP1.................................................................. 15
RC2/CCP1/P1A.......................................................... 19
RC3/SCK1/SCL1.................................................. 15, 19
RC4/SDI1/SDA1................................................... 15, 19
RC5/SDO1............................................................ 15, 19
RC6/TX/CK........................................................... 15, 19
RC7/RX/DT........................................................... 15, 19
RD0/PSP0/SCK2/SCL2.............................................. 20
RD1/PSP1/SDI2/SDA2............................................... 20
RD2/PSP2/SDO2 ....................................................... 20
RD3/PSP3/SS2 .......................................................... 20
RD4/PSP4 .................................................................. 20
RD5/PSP5/P1B .......................................................... 20
RD6/PSP6/P1C .......................................................... 20
RD7/PSP7/P1D .......................................................... 20
RE0/RD/AN5 .............................................................. 21
RE1/WR/AN6.............................................................. 21
RE2/CS/AN7............................................................... 21
VDD ....................................................................... 15, 21
VDDCORE/VCAP ..................................................... 15, 21
VSS ....................................................................... 15, 21
Pinout I/O Descriptions
In-Circuit Emulator .................................................... 293
MPLAB Integrated Development Environment Software .. 291
MPLAB PM3 Device Programmer .................................... 293
MPLINK Object Linker/MPLIB Object Librarian ................ 292
MSSP
ACK Pulse......................................................... 159, 160
Control Registers (general)....................................... 145
Module Overview ...................................................... 145
SPI Master/Slave Connection................................... 149
SSPxBUF Register ................................................... 150
SSPxSR Register...................................................... 150
MULLW ............................................................................. 268
MULWF............................................................................. 268
N
NEGF ................................................................................ 269
NOP .................................................................................. 269
Notable Differences Between PIC18F4520 and
PIC18F45J10 Families.............................................. 341
Oscillator Options...................................................... 342
Peripherals................................................................ 342
Pinouts...................................................................... 342
Power Requirements ................................................ 342
O
Oscillator Configuration....................................................... 23
EC............................................................................... 23
ECPLL......................................................................... 23
HS............................................................................... 23
HS Modes ................................................................... 23
HSPLL......................................................................... 23
Internal Oscillator Block .............................................. 26
INTRC......................................................................... 23
Oscillator Selection ........................................................... 229
Oscillator Start-up Timer (OST) .......................................... 29
Oscillator Switching............................................................. 26
Oscillator Transitions .......................................................... 27
Oscillator, Timer1.............................................................. 115
PIC18F24J10/25J10................................................... 12
PIC18F44J10/45J10................................................... 16
PIR Registers...................................................................... 84
PLL Frequency Multiplier.................................................... 25
ECPLL Oscillator Mode .............................................. 25
HSPLL Oscillator Mode .............................................. 25
POP .................................................................................. 270
POR. See Power-on Reset.
PORTA
Associated Registers.................................................. 96
LATA Register ............................................................ 94
PORTA Register......................................................... 94
TRISA Register........................................................... 94
PORTB
Associated Registers.................................................. 99
LATB Register ............................................................ 97
PORTB Register......................................................... 97
RB7:RB4 Interrupt-on-Change Flag (RBIF Bit) .......... 97
TRISB Register........................................................... 97
PORTC
Associated Registers................................................ 102
LATC Register.......................................................... 100
PORTC Register....................................................... 100
RC3/SCK1/SCL1 Pin................................................ 160
TRISC Register ........................................................ 100
PORTD
Associated Registers................................................ 105
LATD Register.......................................................... 103
Parallel Slave Port (PSP) Function........................... 103
PORTD Register....................................................... 103
TRISD Register ........................................................ 103
PORTE
P
Packaging Information ...................................................... 331
Marking ..................................................................... 331
Parallel Slave Port (PSP).......................................... 103, 109
Associated Registers ................................................ 110
CS (Chip Select) ....................................................... 109
PORTD ..................................................................... 109
RD (Read Input)........................................................ 109
Select (PSPMODE Bit) ..................................... 103, 109
WR (Write Input) ....................................................... 109
PICSTART Plus Development Programmer ..................... 294
PIE Registers...................................................................... 86
Pin Functions
MCLR.................................................................... 12, 16
OSC1/CLKI ........................................................... 12, 16
OSC2/CLKO ......................................................... 12, 16
RA0/AN0............................................................... 13, 17
RA1/AN1............................................................... 13, 17
RA2/AN2/VREF-/CVREF......................................... 13, 17
RA3/AN3/VREF+.................................................... 13, 17
RA5/AN4/SS1/C2OUT.......................................... 13, 17
RB0/INT0/FLT0/AN12........................................... 14, 18
RB1/INT1/AN10 .................................................... 14, 18
RB2/INT2/AN8 ...................................................... 14, 18
RB3/AN9/CCP2 .................................................... 14, 18
RB4/KBI0/AN11 .................................................... 14, 18
Associated Registers................................................ 108
LATE Register .......................................................... 106
PORTE Register....................................................... 106
PSP Mode Select (PSPMODE Bit)........................... 103
TRISE Register......................................................... 106
© 2007 Microchip Technology Inc.
Preliminary
DS39682C-page 347
PIC18F45J10 FAMILY
Power-Managed Modes......................................................31
and A/D Operation ....................................................216
and EUSART Operation............................................191
and Multiple Sleep Commands...................................32
and PWM Operation .................................................143
and SPI Operation ....................................................153
Clock Transitions and Status Indicators......................32
Entering.......................................................................31
Exiting Idle and Sleep Modes .....................................36
by Reset..............................................................36
by WDT Time-out................................................36
Without an Oscillator Start-up Delay...................36
Idle Modes ..................................................................34
PRI_IDLE............................................................35
RC_IDLE.............................................................36
SEC_IDLE...........................................................35
Run Modes..................................................................32
PRI_RUN ............................................................32
RC_RUN.............................................................33
SEC_RUN...........................................................32
Selecting .....................................................................31
Sleep Mode.................................................................34
Summary (table) .........................................................31
Power-on Reset (POR) .......................................................39
Power-up Timer (PWRT) ............................................40
Time-out Sequence.....................................................40
Power-up Delays.................................................................29
Power-up Timer (PWRT)...............................................29, 40
Prescaler
Timer2.......................................................................134
Prescaler, Timer0..............................................................113
Prescaler, Timer2..............................................................129
PRI_IDLE Mode ..................................................................35
PRI_RUN Mode ..................................................................32
Program Counter.................................................................48
PCL, PCH and PCU Registers....................................48
PCLATH and PCLATU Registers ...............................48
Program Memory
and Extended Instruction Set......................................65
Instructions..................................................................52
Two-Word ...........................................................52
Interrupt Vector ...........................................................47
Look-up Tables ...........................................................50
Map and Stack (diagram)............................................47
Reset Vector ...............................................................47
Program Verification and Code Protection........................240
Programming, Device Instructions ....................................241
PSP. See Parallel Slave Port.
Enhanced PWM Auto-Shutdown .............................. 140
Full-Bridge Application Example............................... 138
Full-Bridge Mode ...................................................... 137
Half-Bridge Mode...................................................... 136
Half-Bridge Output Mode Applications Example....... 136
Operation in Power-Managed Modes....................... 143
Operation with Fail-Safe Clock Monitor .................... 143
Output Configurations............................................... 134
Output Relationships (Active-High)........................... 135
Output Relationships (Active-Low) ........................... 135
Programmable Dead-Band Delay............................. 140
Setup for PWM Operation......................................... 143
Start-up Considerations............................................ 142
Q
Q Clock..................................................................... 129, 134
R
RAM. See Data Memory.
RBIF Bit .............................................................................. 97
RC_IDLE Mode................................................................... 36
RC_RUN Mode................................................................... 33
RCALL .............................................................................. 271
RCON Register
Bit Status During Initialization..................................... 42
Reader Response............................................................. 354
Register File........................................................................ 55
Register File Summary ................................................. 57–59
Registers
ADCON0 (A/D Control 0).......................................... 209
ADCON1 (A/D Control 1).......................................... 210
ADCON2 (A/D Control 2).......................................... 211
BAUDCON (Baud Rate Control)............................... 190
CCP1CON (Enhanced Capture/Compare/PWM Control
1) ...................................................................... 131
CCPxCON (Standard Capture/Compare/
PWM Control)................................................... 123
CMCON (Comparator Control) ................................. 219
CONFIG1H (Configuration 1 High)........................... 231
CONFIG1L (Configuration 1 Low) ............................ 231
CONFIG2H (Configuration 2 High)........................... 232
CONFIG2L (Configuration 2 Low) ............................ 232
CONFIG3H (Configuration 3 High)........................... 233
CONFIG3H (Configuration 3 Low)............................ 233
CVRCON (Comparator Voltage Reference Control) 225
Device ID Register 1................................................. 234
Device ID Register 2................................................. 234
ECCP1AS (ECCP Auto-Shutdown Control) ............. 141
ECCP1DEL (PWM Dead-Band Delay) ..................... 140
EECON1 (Data EEPROM Control 1).......................... 69
INTCON (Interrupt Control)......................................... 81
INTCON2 (Interrupt Control 2).................................... 82
INTCON3 (Interrupt Control 3).................................... 83
IPR1 (Peripheral Interrupt Priority 1) .......................... 88
IPR2 (Peripheral Interrupt Priority 2) .......................... 89
IPR3 (Peripheral Interrupt Priority 3) .......................... 89
OSCCON (Oscillator Control)..................................... 28
OSCTUNE (PLL Control)............................................ 25
PIE1 (Peripheral Interrupt Enable 1)........................... 86
PIE2 (Peripheral Interrupt Enable 2)........................... 87
PIE3 (Peripheral Interrupt Enable 3)........................... 87
PIR1 (Peripheral Interrupt Request (Flag) 1).............. 84
PIR2 (Peripheral Interrupt Request (Flag) 2).............. 85
PIR3 (Peripheral Interrupt Request (Flag) 3).............. 85
RCON (Reset Control).......................................... 38, 90
RCSTA (Receive Status and Control) ...................... 189
Pulse-Width Modulation. See PWM (CCP Module) and
PWM (ECCP Module).
PUSH ................................................................................270
PUSH and POP Instructions ...............................................49
PUSHL ..............................................................................286
PWM (CCP Module)
Associated Registers ................................................130
Auto-Shutdown (CCP1 Only)....................................129
CCPR1H:CCPR1L Registers....................................133
Duty Cycle......................................................... 128, 134
Example Frequencies/Resolutions ................... 129, 134
Period................................................................128, 133
Setup for Operation...................................................129
TMR2-to-PR2 Match .........................................128, 133
PWM (ECCP Module) .......................................................133
Direction Change in Full-Bridge Output Mode ..........138
Effects of a Reset......................................................143
DS39682C-page 348
Preliminary
© 2007 Microchip Technology Inc.
PIC18F45J10 FAMILY
2
SSPxCON1 (MSSPx Control 1, I C Mode)............... 157
Master Mode............................................................. 150
Master/Slave Connection ......................................... 149
Operation.................................................................. 148
Operation in Power-Managed Modes....................... 153
Serial Clock .............................................................. 145
Serial Data In............................................................ 145
Serial Data Out......................................................... 145
Slave Mode............................................................... 151
Slave Select.............................................................. 145
Slave Select Synchronization................................... 151
SPI Clock.................................................................. 150
Typical Connection................................................... 149
SSPOV ............................................................................. 176
SSPOV Status Flag .......................................................... 176
SSPxSTAT Register
R/W Bit ............................................................. 159, 160
SSx ................................................................................... 145
Stack Full/Underflow Resets............................................... 50
SUBFSR ........................................................................... 287
SUBFWB .......................................................................... 276
SUBLW............................................................................. 277
SUBULNK......................................................................... 287
SUBWF............................................................................. 277
SUBWFB .......................................................................... 278
SWAPF............................................................................. 278
SSPxCON1 (MSSPx Control 1, SPI Mode) .............. 147
2
SSPxCON2 (MSSPx Control 2, I C Mode)............... 158
2
SSPxSTAT (MSSPx Status, I C Mode).................... 156
SSPxSTAT (MSSPx Status, SPI Mode) ................... 146
STATUS...................................................................... 60
STKPTR (Stack Pointer)............................................. 49
T0CON (Timer0 Control)........................................... 111
T1CON (Timer1 Control)........................................... 115
T2CON (Timer2 Control)........................................... 121
TRISE (PORTE/PSP Control)................................... 107
TXSTA (Transmit Status and Control) ...................... 188
WDTCON (Watchdog Timer Control) ....................... 235
RESET .............................................................................. 271
Reset................................................................................... 37
MCLR Reset, During Power-Managed Modes............ 37
MCLR Reset, Normal Operation................................. 37
Power-on Reset (POR)............................................... 37
Programmable Brown-out Reset (BOR) ..................... 37
Reset Instruction......................................................... 37
Stack Full Reset.......................................................... 37
Stack Underflow Reset ............................................... 37
Watchdog Timer (WDT) Reset.................................... 37
Resets............................................................................... 229
Brown-out Reset (BOR)............................................ 229
Oscillator Start-up Timer (OST) ................................ 229
Power-on Reset (POR)............................................. 229
Power-up Timer (PWRT) .......................................... 229
RETFIE ............................................................................. 272
RETLW ............................................................................. 272
RETURN ........................................................................... 273
Return Address Stack......................................................... 48
Return Stack Pointer (STKPTR) ......................................... 49
Revision History................................................................ 341
RLCF................................................................................. 273
RLNCF .............................................................................. 274
RRCF ................................................................................ 274
RRNCF ............................................................................. 275
T
Table Pointer Operations (table)......................................... 70
Table Reads/Table Writes .................................................. 50
TBLRD.............................................................................. 279
TBLWT ............................................................................. 280
Timer0 .............................................................................. 111
Associated Registers................................................ 113
Clock Source Select (T0CS Bit) ............................... 112
Operation.................................................................. 112
Overflow Interrupt..................................................... 113
Prescaler .................................................................. 113
Prescaler Assignment (PSA Bit)............................... 113
Prescaler Select (T0PS2:T0PS0 Bits)...................... 113
Prescaler. See Prescaler, Timer0.
S
SCKx................................................................................. 145
SDIx .................................................................................. 145
SDOx ................................................................................ 145
SEC_IDLE Mode................................................................. 35
SEC_RUN Mode................................................................. 32
Serial Clock, SCKx............................................................ 145
Serial Data In (SDIx)......................................................... 145
Serial Data Out (SDOx) .................................................... 145
Serial Peripheral Interface. See SPI Mode.
SETF................................................................................. 275
Slave Select (SSx) ............................................................ 145
SLEEP .............................................................................. 276
Sleep
Reads and Writes in 16-Bit Mode............................. 112
Source Edge Select (T0SE Bit) ................................ 112
Switching Prescaler Assignment .............................. 113
Timer1 .............................................................................. 115
16-Bit Read/Write Mode ........................................... 117
Associated Registers................................................ 119
Interrupt .................................................................... 118
Operation.................................................................. 116
Oscillator........................................................... 115, 117
Layout Considerations...................................... 118
Oscillator, as Secondary Clock................................... 26
Overflow Interrupt..................................................... 115
Resetting, Using the ECCP/CCP Special Event
OSC1 and OSC2 Pin States....................................... 29
Software Simulator (MPLAB SIM)..................................... 292
Special Event Trigger. See Compare (ECCP Module).
Special Event Trigger. See Compare (ECCP/CCP Modules).
Special Features of the CPU ............................................ 229
Special Function Registers ................................................. 56
Map............................................................................. 56
SPI Mode (MSSP)
Trigger.............................................................. 118
Special Event Trigger (ECCP).................................. 132
TMR1H Register....................................................... 115
TMR1L Register ....................................................... 115
Use as a Clock Source............................................. 117
Use as a Real-Time Clock........................................ 118
Timer2 .............................................................................. 121
Associated Registers................................................ 122
Interrupt .................................................................... 122
Operation.................................................................. 121
Output....................................................................... 122
PR2 Register .................................................... 128, 133
TMR2-to-PR2 Match Interrupt .......................... 128, 133
Associated Registers ................................................ 154
Bus Mode Compatibility ............................................ 153
Clock Speed and Module Interactions ...................... 153
Effects of a Reset...................................................... 153
Enabling SPI I/O ....................................................... 149
© 2007 Microchip Technology Inc.
Preliminary
DS39682C-page 349
PIC18F45J10 FAMILY
Timing Diagrams
Reset, Watchdog Timer (WDT), Oscillator Start-up Timer
(OST) and Power-up Timer (PWRT) ................ 314
Send Break Character Sequence............................. 202
Slave Synchronization .............................................. 151
Slow Rise Time (MCLR Tied to VDD,
VDD Rise > TPWRT)............................................. 41
SPI Mode (Master Mode).......................................... 150
SPI Mode (Slave Mode, CKE = 0)............................ 152
SPI Mode (Slave Mode, CKE = 1)............................ 152
Synchronous Reception (Master Mode, SREN) ....... 205
Synchronous Transmission ...................................... 203
Synchronous Transmission (Through TXEN)........... 204
Time-out Sequence on Power-up (MCLR Not
A/D Conversion.........................................................326
Acknowledge Sequence ...........................................179
Asynchronous Reception ..........................................200
Asynchronous Transmission.....................................198
Asynchronous Transmission (Back to Back) ............198
Automatic Baud Rate Calculation .............................196
Auto-Wake-up Bit (WUE) During Normal Operation .201
Auto-Wake-up Bit (WUE) During Sleep ....................201
Baud Rate Generator with Clock Arbitration .............173
BRG Overflow Sequence..........................................196
BRG Reset Due to SDAx Arbitration During Start
Condition...........................................................182
Brown-out Reset (BOR)............................................314
Bus Collision During a Repeated Start Condition
Tied to VDD), Case 1 .......................................... 40
Time-out Sequence on Power-up (MCLR Not
(Case 1) ............................................................183
Bus Collision During a Repeated Start Condition
Tied to VDD), Case 2 .......................................... 41
Time-out Sequence on Power-up (MCLR Tied to
VDD, VDD Rise Tpwrt)......................................... 40
Timer0 and Timer1 External Clock ........................... 315
Transition for Entry to Idle Mode................................. 35
Transition for Entry to SEC_RUN Mode ..................... 32
Transition for Entry to Sleep Mode ............................. 34
Transition for Two-Speed Start-up (INTRC) ............. 237
Transition for Wake from Idle to Run Mode................ 35
Transition for Wake from Sleep .................................. 34
Transition from RC_RUN Mode to PRI_RUN Mode... 33
Transition to RC_RUN Mode...................................... 33
Timing Diagrams and Specifications
(Case 2) ............................................................183
Bus Collision During a Start Condition (SCLx = 0)....182
Bus Collision During a Stop Condition (Case 1) .......184
Bus Collision During a Stop Condition (Case 2) .......184
Bus Collision During Start Condition (SDAx Only)....181
Bus Collision for Transmit and Acknowledge............180
Capture/Compare/PWM (Including ECCP Module) ..316
CLKO and I/O ...........................................................313
Clock Synchronization ..............................................166
Clock/Instruction Cycle ...............................................51
EUSART Synchronous Receive (Master/Slave) .......325
EUSART Synchronous Transmission
A/D Conversion Requirements ................................. 327
AC Characteristics
(Master/Slave)...................................................325
Example SPI Master Mode (CKE = 0) ......................317
Example SPI Master Mode (CKE = 1) ......................318
Example SPI Slave Mode (CKE = 0) ........................319
Example SPI Slave Mode (CKE = 1) ........................320
External Clock (All Modes Except PLL) ....................311
Fail-Safe Clock Monitor.............................................239
First Start Bit Timing .................................................174
Full-Bridge PWM Output ...........................................137
Half-Bridge PWM Output ..........................................136
Internal RC Accuracy........................................ 312
Capture/Compare/PWM Requirements (Including
ECCP Module).................................................. 316
CLKO and I/O Requirements.................................... 313
EUSART Synchronous Receive Requirements........ 325
EUSART Synchronous Transmission Requirements 325
Example SPI Mode Requirements (Master Mode,
CKE = 0)........................................................... 317
Example SPI Mode Requirements (Master Mode,
CKE = 1)........................................................... 318
Example SPI Mode Requirements (Slave Mode,
CKE = 0)........................................................... 319
Example SPI Slave Mode Requirements (CKE = 1). 320
External Clock Requirements ................................... 311
2
I C Bus Data.............................................................321
2
I C Bus Start/Stop Bits..............................................321
2
I C Master Mode (7 or 10-Bit Transmission) ............177
2
I C Master Mode (7-Bit Reception)...........................178
2
I C Slave Mode (10-Bit Reception, SEN = 0) ...........163
2
2
I C Slave Mode (10-Bit Reception, SEN = 1) ...........168
I C Bus Data Requirements (Slave Mode)............... 322
2
2
I C Slave Mode (10-Bit Transmission)......................164
I C Bus Start/Stop Bits Requirements (Slave Mode) 321
2
2
I C Slave Mode (7-bit Reception, SEN = 0)..............161
Master SSP I C Bus Data Requirements ................. 324
2
2
I C Slave Mode (7-Bit Reception, SEN = 1) .............167
Master SSP I C Bus Start/Stop Bits Requirements.. 323
2
I C Slave Mode (7-Bit Transmission)........................162
Parallel Slave Port Requirements............................. 316
PLL Clock ................................................................. 312
Reset, Watchdog Timer, Oscillator Start-up Timer,
Power-up Timer and Brown-out Reset
2
I C Slave Mode General Call Address Sequence (7 or
10-Bit Address Mode) .......................................169
2
I C Stop Condition Receive or Transmit Mode .........179
2
Master SSP I C Bus Data.........................................323
Requirements ................................................... 314
Timer0 and Timer1 External Clock Requirements.... 315
Top-of-Stack Access........................................................... 48
TRISE Register
PSPMODE Bit........................................................... 103
TSTFSZ ............................................................................ 281
Two-Speed Start-up.................................................. 229, 237
Two-Word Instructions
2
Master SSP I C Bus Start/Stop Bits .........................323
Parallel Slave Port (PSP) Read ................................110
Parallel Slave Port (PSP) Write ................................110
PWM Auto-Shutdown (PRSEN = 0, Auto-Restart Dis-
abled)................................................................142
PWM Auto-Shutdown (PRSEN = 1, Auto-Restart En-
abled)................................................................142
PWM Direction Change ............................................139
PWM Direction Change at Near 100% Duty Cycle ...139
PWM Output .............................................................128
Repeated Start Condition..........................................175
Example Cases........................................................... 52
TXSTA Register
BRGH Bit .................................................................. 191
DS39682C-page 350
Preliminary
© 2007 Microchip Technology Inc.
PIC18F45J10 FAMILY
V
Voltage Reference Specifications..................................... 308
Voltage Regulator (On-Chip) ............................................ 236
W
Watchdog Timer (WDT) ............................................ 229, 235
Associated Registers ................................................ 235
Control Register........................................................ 235
During Oscillator Failure ........................................... 238
Programming Considerations ................................... 235
WCOL ....................................................... 174, 175, 176, 179
WCOL Status Flag .................................... 174, 175, 176, 179
WWW Address.................................................................. 353
WWW, On-Line Support ....................................................... 6
X
XORLW............................................................................. 281
XORWF............................................................................. 282
© 2007 Microchip Technology Inc.
Preliminary
DS39682C-page 351
PIC18F45J10 FAMILY
THE MICROCHIP WEB SITE
CUSTOMER SUPPORT
Microchip provides online support via our WWW site at
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to make files and information easily available to
customers. Accessible by using your favorite Internet
browser, the web site contains the following
information:
Users of Microchip products can receive assistance
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Customers
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support. Local sales offices are also available to help
customers. A listing of sales offices and locations is
included in the back of this document.
• General Technical Support – Frequently Asked
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Technical support is available through the web site
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Microchip’s customer notification service helps keep
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To register, access the Microchip web site at
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DS39682C-page 352
PreliminaryAdvance Information
© 2007 Microchip Technology Inc.
PIC18F45J10 FAMILY
READER RESPONSE
It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip prod-
uct. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation
can better serve you, please FAX your comments to the Technical Publications Manager at (480) 792-4150.
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PIC18F45J10 family
DS39682C
Literature Number:
Device:
Questions:
1. What are the best features of this document?
2. How does this document meet your hardware and software development needs?
3. Do you find the organization of this document easy to follow? If not, why?
4. What additions to the document do you think would enhance the structure and subject?
5. What deletions from the document could be made without affecting the overall usefulness?
6. Is there any incorrect or misleading information (what and where)?
7. How would you improve this document?
© 2007 Microchip Technology Inc.
PreliminaryAdvance Information
DS39682C-page 353
PIC18F45J10 FAMILY
PIC18F45J10 FAMILY PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
PART NO.
Device
X
/XX
XXX
Examples:
Temperature
Range
Package
Pattern
a)
PIC18LF45J10-I/P 301 = Industrial temp.,
PDIP package, Extended VDD limits, QTP
pattern #301.
b)
c)
PIC18LF24J10-I/SO = Industrial temp., SOIC
package, Extended VDD limits.
Device
PIC18F24J10/25J10(1), PIC18F44J10/45J10(1)
,
PIC18LF44J10-I/P = Industrial temp., PDIP
package, normal VDD limits.
PIC18F24J10/25J10T(2), PIC18F44J10/45J10T(2)
VDD range 4.2V to 5.5V
;
PIC18LF24J10/25J10(1), PIC18LF44J10/45J10(1)
,
PIC18LF24J10/25J10T(2), PIC18LF44J10/45J10T(2)
VDD range 2.0V to 5.5V
;
Temperature Range
Package
I
E
=
=
-40°C to +85°C (Industrial)
-40°C to +125°C (Extended)
PT
SO
SP
P
=
=
=
=
=
TQFP (Thin Quad Flatpack)
Note 1:
2:
F
LF
T
=
=
=
Standard Voltage Range
Wide Voltage Range
in tape and reel TQFP
packages only.
SOIC
Skinny Plastic DIP
PDIP
QFN
ML
Pattern
QTP, SQTP, Code or Special Requirements
(blank otherwise)
DS39682C-page 354
Preliminary
© 2007 Microchip Technology Inc.
WORLDWIDE SALES AND SERVICE
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Toronto
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Canada
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Fax: 905-673-6509
China - Xian
Tel: 86-29-8833-7250
Fax: 86-29-8833-7256
12/08/06
DS39682C-page 355
Preliminary
© 2007 Microchip Technology Inc.
PIC18F45J10 FAMILY
DS39682C-page 356
Advance Information
© 2007 Microchip Technology Inc.
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