PIC18F4539_技术文档

PIC18FXX39

Data Sheet

Enhanced FLASH Microcontrollers

with Single Phase Induction

Motor Control Kernel

 2002 Microchip Technology Inc.

Preliminary

DS30485A

Note the following details of the code protection feature on Microchip devices:

•

Microchip products meet the specification contained in their particular Microchip Data Sheet.

•

Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the

intended manner and under normal conditions.

•

There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowl-

edge, require using the Microchip products in a manner outside the operating specifications contained in Microchip's Data

Sheets. Most likely, the person doing so is engaged in theft of intellectual property.

•

Microchip is willing to work with the customer who is concerned about the integrity of their code.

Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not

mean that we are guaranteeing the product as “unbreakable.”

Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our

products.

Information contained in this publication regarding device

applications and the like is intended through suggestion only

and may be superseded by updates. It is your responsibility to

ensure that your application meets with your specifications.

No representation or warranty is given and no liability is

assumed by Microchip Technology Incorporated with respect

to the accuracy or use of such information, or infringement of

patents or other intellectual property rights arising from such

use or otherwise. Use of Microchip’s products as critical com-

ponents in life support systems is not authorized except with

express written approval by Microchip. No licenses are con-

veyed, implicitly or otherwise, under any intellectual property

rights.

Trademarks

The Microchip name and logo, the Microchip logo, KEELOQ,

MPLAB, PIC, PICmicro, PICSTART and PRO MATE are

registered trademarks of Microchip Technology Incorporated

in the U.S.A. and other countries.

FilterLab, microID, MXDEV, MXLAB, PICMASTER, SEEVAL

and The Embedded Control Solutions Company are

registered trademarks of Microchip Technology Incorporated

in the U.S.A.

dsPIC, dsPICDEM.net, ECONOMONITOR, FanSense,

FlexROM, fuzzyLAB, In-Circuit Serial Programming, ICSP,

ICEPIC, microPort, Migratable Memory, MPASM, MPLIB,

MPLINK, MPSIM, PICC, PICDEM, PICDEM.net, rfPIC, Select

Mode and Total Endurance are trademarks of Microchip

Technology Incorporated in the U.S.A. and other countries.

Serialized Quick Turn Programming (SQTP) is a service mark

of Microchip Technology Incorporated in the U.S.A.

All other trademarks mentioned herein are property of their

respective companies.

Printed on recycled paper.

Microchip received QS-9000 quality system

certification for its worldwide headquarters,

design and wafer fabrication facilities in

Chandler and Tempe, Arizona in July 1999

and Mountain View, California in March 2002.

The Company’s quality system processes and

procedures are QS-9000 compliant for its

®

PICmicro 8-bit MCUs, KEELOQ^®code hopping

devices, Serial EEPROMs, microperipherals,

non-volatile memory and analog products. In

addition, Microchip’s quality system for the

design and manufacture of development

systems is ISO 9001 certified.

DS30485A - page ii

Preliminary

 2002 Microchip Technology Inc.

PIC18FXX39

Enhanced FLASH Microcontrollers with

Single Phase Induction Motor Control Kernel

High Performance RISC CPU:

Peripheral Features:

• Linear program memory addressing to 24 Kbytes

• Linear data memory addressing to 1.4 Kbytes

• 20 MHz operation (5 MIPs):

• High current sink/source 25 mA/25 mA

• Three external interrupt pins

• Timer0 module: 8-bit/16-bit timer/counter with

8-bit programmable prescaler

- 20 MHz oscillator/clock input

• Timer1 module: 16-bit timer/counter

• Timer3 module: 16-bit timer/counter

• Secondary oscillator clock option - Timer1/Timer3

• Two PWM modules:

- 5 MHz oscillator/clock input with PLL active

• 16-bit wide instructions, 8-bit wide data path

• 8 x 8 Single Cycle Hardware Multiplier

Special Microcontroller Features:

- Resolution is 1- to 10-bit,

Max. PWM freq. @ 8-bit resolution = 156 kHz

10-bit resolution = 39 kHz

• 100,000 erase/write cycle Enhanced FLASH

program memory typical

• 1,000,000 erase/write cycle Data EEPROM memory

• FLASH/Data EEPROM Retention: > 100 years

• Single Phase Induction Motor Control kernel

- Programmable Motor Control Technology

(ProMPT™) provides open loop Variable

Frequency (VF) control

• Power-on Reset (POR), Power-up Timer (PWRT)

and Oscillator Start-up Timer (OST)

• Programmable code protection

• Power saving SLEEP mode

- User programmable Voltage vs. Frequency

curve

• Single supply 5V In-Circuit Serial Programming™

- Most suitable for shaded pole and permanent

split capacitor type motors

(ICSP™) via two pins

• In-Circuit Debug (ICD) via two pins

• Master Synchronous Serial Port (MSSP) module

with two modes of operation:

Analog Features:

- 3-wire SPI™ (supports all 4 SPI modes)

- I²C™ Master and Slave mode

• Addressable USART module:

• Compatible 10-bit Analog-to-Digital Converter

module (A/D) with:

- Fast sampling rate

- Supports RS-485 and RS-232

• Parallel Slave Port (PSP) module

- Conversion available during SLEEP

- DNL = ±1 LSb, INL = ±1 LSb

• Programmable Low Voltage Detection (PLVD)

- Supports interrupt on Low Voltage Detection

• Programmable Brown-out Reset (BOR)

CMOS Technology:

• Low power, high speed FLASH/EEPROM

technology

• Fully static design

• Wide operating voltage range (2.0V to 5.5V)

• Industrial and Extended temperature ranges

Program Memory

Bytes Words

Data Memory

MSSP

I/O

10-bit

PWM

Timers

Device

AUSART

SRAM EEPROM

Master

Pins A/D (ch) 10-bit

16-bit/WDT

SPI

2

(Bytes)

640

(Bytes)

256

I C

PIC18F2439

PIC18F2539

PIC18F4439

PIC18F4539

12K

24K

12K

24K

6144

12288

6144

21

32

5

8

2

Yes

3/1

1408

640

256

12288

1408

256

 2002 Microchip Technology Inc.

Preliminary

DS30485A-page 1

PIC18FXX39

Pin Diagrams

44-Pin TQFP

NC

33

32

31

30

29

28

RC7/RX/DT

1

2

3

4

5

RC0/T13CKI

OSC2/CLKO/RA6

OSC1/CLKI

VSS

RD4/PSP4

RD5/PSP5

RD6/PSP6

RD7/PSP7

VSS

PIC18F4439

PIC18F4539

VDD

6

RE2/AN7/CS

RE1/AN6/WR

RE0/AN5/RD

RA5/AN4/SS/LVDIN

RA4/T0CKI

27

26

VDD

7

RB0/INT0

RB1/INT1

RB2/INT2

RB3

8

9

25

24

23

10

11

44-Pin QFN

RC7/RX/DT

RD4/PSP4

RD5/PSP5

RD6/PSP6

RD7/PSP7

VSS

1

OSC2/CLKO/RA6

33

2

OSC1/CLKI

VSS

32

31

30

29

28

3

4

AVSS

5

PIC18F4439

PIC18F4539

VDD

6

VDD

7

RE2/AN7/CS

RE1/AN6/WR

RE0/AN5/RD

RA5/AN4/SS/LVDIN

RA4/T0CKI

27

26

25

24

23

AVDD

8

RB0/INT0

RB1/INT1

RB2/INT2

9

10

11

DS30485A-page 2

Preliminary

 2002 Microchip Technology Inc.

PIC18FXX39

Pin Diagrams (Cont.’d)

40-Pin DIP

MCLR/VPP

RA0/AN0

1

RB7/PGD

RB6/PGC

RB5/PGM

RB4

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

24

23

22

21

2

RA1/AN1

3

RA2/AN2/VREF-

4

RA3/AN3/VREF+

RB3

5

RA4/T0CKI

RB2/INT2

6

RA5/AN4/SS/LVDIN

RE0/AN5/RD

RE1/AN6/WR

RE2/AN7/CS

VDD

7

RB1/INT1

RB0/INT0

VDD

8

9

10

11

12

13

14

15

16

17

18

19

20

VSS

RD7/PSP7

RD6/PSP6

RD5/PSP5

RD4/PSP4

VSS

OSC1/CLKI

OSC2/CLKO/RA6

RC0/T13CKI

PWM2

RC7/RX/DT

RC6/TX/CK

RC5/SDO

PWM1

RC3/SCK/SCL

RC4/SDI/SDA

RD0/PSP0

RD3/PSP3

RD1/PSP1

RD2/PSP2

28-Pin DIP, SOIC

28

27

26

1

RB7/PGD

RB6/PGC

RB5/PGM

RB4

MCLR/VPP

RA0/AN0

2

3

4

5

6

7

8

9

RA1/AN1

RA2/AN2/VREF-

RA3/AN3/VREF+

RA4/T0CKI

25

24

23

22

21

20

19

18

17

16

15

RB3

RB2/INT2

RB1/INT1

RB0/INT0

VDD

RA5/AN4/SS/LVDIN

VSS

OSC1/CLKI

OSC2/CLKO/RA6

RC0/T13CKI

PWM2

VSS

10

11

12

13

14

RC7/RX/DT

RC6/TX/CK

RC5/SDO

RC4/SDI/SDA

PWM1

RC3/SCK/SCL

 2002 Microchip Technology Inc.

Preliminary

DS30485A-page 3

PIC18FXX39

Table of Contents

1.0 Device Overview .......................................................................................................................................................................... 7

2.0 Oscillator Configurations ............................................................................................................................................................ 19

3.0 Reset.......................................................................................................................................................................................... 23

4.0 Memory Organization................................................................................................................................................................. 33

5.0 FLASH Program Memory........................................................................................................................................................... 51

6.0 Data EEPROM Memory ............................................................................................................................................................. 61

7.0 8 X 8 Hardware Multiplier........................................................................................................................................................... 67

8.0 Interrupts .................................................................................................................................................................................... 69

9.0 I/O Ports ..................................................................................................................................................................................... 83

10.0 Timer0 Module ........................................................................................................................................................................... 99

11.0 Timer1 Module ......................................................................................................................................................................... 103

12.0 Timer2 Module ......................................................................................................................................................................... 107

13.0 Timer3 Module ......................................................................................................................................................................... 109

14.0 Single Phase Induction Motor Control Kernel .......................................................................................................................... 113

15.0 Pulse Width Modulation (PWM) Modules................................................................................................................................. 123

16.0 Master Synchronous Serial Port (MSSP) Module .................................................................................................................... 125

17.0 Addressable Universal Synchronous Asynchronous Receiver Transmitter (USART).............................................................. 165

18.0 Compatible 10-bit Analog-to-Digital Converter (A/D) Module................................................................................................... 181

19.0 Low Voltage Detect .................................................................................................................................................................. 189

20.0 Special Features of the CPU.................................................................................................................................................... 195

21.0 Instruction Set Summary.......................................................................................................................................................... 211

22.0 Development Support............................................................................................................................................................... 253

23.0 Electrical Characteristics .......................................................................................................................................................... 259

24.0 DC and AC Characteristics Graphs and Tables....................................................................................................................... 287

25.0 Packaging Information.............................................................................................................................................................. 297

Appendix A: Revision History............................................................................................................................................................. 305

Appendix B: Device Differences......................................................................................................................................................... 305

Appendix C: Conversion Considerations ........................................................................................................................................... 306

Appendix D: Migration from High-End to Enhanced Devices............................................................................................................. 307

Index .................................................................................................................................................................................................. 309

On-Line Support................................................................................................................................................................................. 317

Systems Information and Upgrade Hot Line ...................................................................................................................................... 317

Reader Response .............................................................................................................................................................................. 318

PIC18FXX39 Product Identification System....................................................................................................................................... 319

DS30485A-page 4

Preliminary

 2002 Microchip Technology Inc.

PIC18FXX39

TO OUR VALUED CUSTOMERS

It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip

products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and

enhanced as new volumes and updates are introduced.

If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via

E-mail at docerrors@mail.microchip.com or fax the Reader Response Form in the back of this data sheet to (480) 792-4150.

We welcome your feedback.

Most Current Data Sheet

To obtain the most up-to-date version of this data sheet, please register at our Worldwide Web site at:

http://www.microchip.com

You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page.

The last character of the literature number is the version number, (e.g., DS30000A is version A of document DS30000).

Errata

An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current

devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision

of silicon and revision of document to which it applies.

To determine if an errata sheet exists for a particular device, please check with one of the following:

•

Microchip’s Worldwide Web site; http://www.microchip.com

Your local Microchip sales office (see last page)

The Microchip Corporate Literature Center; U.S. FAX: (480) 792-7277

When contacting a sales office or the literature center, please specify which device, revision of silicon and data sheet (include liter-

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Register on our web site at www.microchip.com/cn to receive the most current information on all of our products.

 2002 Microchip Technology Inc.

Preliminary

DS30485A-page 5

PIC18FXX39

NOTES:

DS30485A-page 6

Preliminary

 2002 Microchip Technology Inc.

PIC18FXX39

1.2

Details on Individual Family

1.0

DEVICE OVERVIEW

Members

This document contains device specific information for

the following devices:

Devices in the PIC18FXX39 family are available in

28-pin (PIC18F2X39) and 40/44-pin (PIC18F4X39)

packages. Block diagrams for the two groups are

shown in Figure 1-1 and Figure 1-2.

• PIC18F2439

• PIC18F2539

• PIC18F4439

• PIC18F4539

This family offers the advantages of all PIC18 micro-

controllers - namely, high computational performance

at an economical price - with the addition of high-endur-

ance Enhanced FLASH program memory. The

PIC18FXX39 family also provides an off-the-shelf solu-

tion for simple motor control applications, allowing

users to create speed control solutions with small part

counts and short development times.

The devices are differentiated from each other in four

ways:

1. FLASH program memory and data RAM

(12 Kbytes and 640 bytes for PIC18FX439

devices, 24 Kbytes and 1408 bytes for

PIC18FX539)

2. A/D channels (5 for PIC18F2X39 devices, 8 for

PIC18F4X39)

3. I/O ports (3 ports on PIC18F2X39, 5 ports on

PIC18F4X39 devices)

1.1

Key Features

1.1.1

PROGRAMMABLE MOTOR

PROCESSOR TECHNOLOGY

(ProMPT™) MOTOR CONTROL

4. Parallel Slave Port (present only on

PIC18F4X39 devices)

All other features for devices in this family are identical.

These are summarized in Table 1-1.

The pinouts for all devices are listed in Table 1-2 and

Table 1-3.

The integrated motor control kernel uses on-chip Pulse

Width Modulation (PWM) to provide speed control for

single phase induction motors. Through a convenient

set of Application Program Interfaces (APIs) and vari-

able frequency technology for open loop control, users

can develop applications with little or no previous expe-

rience in motor control techniques. ProMPT motor con-

trol provides modulated output over a range of 0 to

127 Hz, and has a pre-defined V/F curve that can be

reprogrammed to suit the application.

1.1.2

OTHER PIC18FXX39 FEATURES

• Memory Endurance: The Enhanced FLASH cells

for both program memory and data EEPROM are

rated to last for many thousands of erase/write

cycles - up to 100,000 for program memory, and

1,000,000 for EEPROM. Data retention without

refresh is conservatively estimated to be greater

than 100 years at 25°C.

• Self-programmability: These devices can write to

their own program memory spaces under internal

software control. By using a bootloader routine

located in the protected Boot Block at the top of pro-

gram memory, it becomes possible to create an

application that can update itself in the field.

• Addressable USART: This serial communication

module is capable of standard RS-232 operation

using the internal oscillator block, removing the

need for an external crystal (and its accompanying

power requirement) in applications that talk to the

outside world.

• 10-bit A/D Converter: This module offers up to

8 conversion channels for flexibility in sensor

monitoring and control, as well as the ability to do

conversions while the device is in SLEEP mode.

 2002 Microchip Technology Inc.

Preliminary

DS30485A-page 7

PIC18FXX39

TABLE 1-1:

PIC18FXX39 DEVICE FEATURES

Features

PIC18F2439

PIC18F2539

PIC18F4439

PIC18F4539

Operating Frequency

Program Memory (Bytes)

Program Memory (Instructions)

Data Memory (Bytes)

Data EEPROM Memory (Bytes)

Interrupt Sources

DC - 40 MHz

24K

12K

6144

640

256

24K

12288

1408

256

12K

6144

640

256

16

12288

1408

256

15

16

I/O Ports

Ports A, B, C

Ports A, B, C, D, E Ports A, B, C, D, E

Timers

3

2

3

2

3

2

3

2

PWM Modules⁽¹⁾

Single Phase Induction

Motor Control

Yes

MSSP,

Addressable

USART

MSSP,

Addressable

USART

MSSP,

Addressable

USART

MSSP,

Addressable

USART

Serial Communications

Parallel Communications

—

PSP

10-bit Analog-to-Digital Module

5 input channels

POR, BOR,

5 input channels

POR, BOR,

8 input channels

POR, BOR,

8 input channels

POR, BOR,

RESETInstruction, RESETInstruction, RESETInstruction, RESETInstruction,

RESETS (and Delays)

Stack Full,

Stack Underflow

(PWRT, OST)

Stack Full,

Stack Underflow

(PWRT, OST)

Stack Full,

Stack Underflow

(PWRT, OST)

Stack Full,

Stack Underflow

(PWRT, OST)

Programmable Low Voltage

Detect

Yes

Programmable Brown-out Reset

Instruction Set

Yes

75 Instructions

Yes

75 Instructions

Yes

75 Instructions

Yes

75 Instructions

40-pin DIP

44-pin TQFP

44-pin QFN

40-pin DIP

44-pin TQFP

44-pin QFN

28-pin DIP

28-pin SOIC

28-pin DIP

28-pin SOIC

Packages

Note 1: PWM modules are used exclusively in conjunction with the motor control kernel, and are not available for

other applications.

DS30485A-page 8

Preliminary

 2002 Microchip Technology Inc.

PIC18FXX39

FIGURE 1-1:

PIC18F2X39 BLOCK DIAGRAM

Data Bus<8>

PORTA

Table Pointer

Data Latch

21

RA0/AN0

RA1/AN1

8

Data RAM

RA2/AN2/VREF-

RA3/AN3/VREF+

RA4/T0CKI

RA5/AN4/SS/LVDIN

RA6

inc/dec logic

21

Address Latch

12⁽²⁾

Address<12>

PCLATU PCLATH

Address Latch

Program Memory

(up to 2 Mbytes)

PCU PCH PCL

Program Counter

4

12

4

Data Latch

BSR

Bank0, F

FSR0

FSR1

FSR2

31 Level Stack

12

PORTB

16

inc/dec

logic

Decode

RB0/INT0

RB1/INT1

RB2/INT2

RB3

Table Latch

8

ROM Latch

RB4

RB5/PGM

RB6/PGC

RB7/PGD

Instruction

Register

8

Instruction

Decode &

Control

PRODH PRODL

8 x 8 Multiply

OSC2/CLKO

OSC1/CLKI

3

Power-up

Timer

8

Timing

PORTC

Oscillator

T1OSCI

WREG

8

BIT OP

8

Generation

Start-up Timer

8

T1OSCO

RC0/T13CKI

RC3/SCK/SCL

RC4/SDI/SDA

RC5/SDO

RC6/TX/CK

RC7/RX/DT

Power-on

Reset

8

Watchdog

Timer

4X PLL

ALU<8>

Brown-out

Reset

8

Precision

Voltage

Reference

Low Voltage

Programming

MCLR

PWM1

PWM2

In-Circuit

Debugger

VDD, VSS

A/D Converter

Data EEPROM

Timer0

PWM1

Timer1

Timer2

Master

Timer3

Addressable

USART

Synchronous

Serial Port

PWM2

Note 1: The high order bits of the Direct Address for the RAM are from the BSR register (except for the MOVFFinstruction).

2: Many of the general purpose I/O pins are multiplexed with one or more peripheral module functions. The multiplexing combinations

are device dependent.

 2002 Microchip Technology Inc.

Preliminary

DS30485A-page 9

PIC18FXX39

FIGURE 1-2:

PIC18F4X39 BLOCK DIAGRAM

Data Bus<8>

PORTA

PORTB

RA0/AN0

RA1/AN1

Table Pointer

inc/dec logic

21

Data Latch

21

RA2/AN2/VREF-

RA3/AN3/VREF+

RA4/T0CKI

RA5/AN4/SS/LVDIN

RA6

Data RAM

(up to 4K

8

21

address reach)

Address Latch

12⁽²⁾

Address<12>

PCLATU

PCLATH

Address Latch

Program Memory

(up to 2 Mbytes)

PCH PCL

PCU

RB0/INT0

RB1/INT1

RB2/INT2

RB3

Program Counter

4

12

4

Data Latch

BSR

Bank0, F

FSR0

FSR1

FSR2

31 Level Stack

RB4

12

RB5/PGM

RB6/PGC

RB7/PGD

16

inc/dec

logic

Decode

Table Latch

PORTC

8

ROM Latch

RC0/T13CKI

RC3/SCK/SCL

RC4/SDI/SDA

RC5/SDO

RC6/TX/CK

RC7/RX/DT

Instruction

Register

8

Instruction

Decode &

Control

PRODH PRODL

8 x 8 Multiply

PORTD

PORTE

OSC2/CLKO

OSC1/CLKI

3

RD0/PSP0

RD1/PSP1

RD2/PSP2

RD3/PSP3

RD4/PSP4

Power-up

Timer

8

Timing

Oscillator

T1OSCI

BIT OP

8

WREG

8

Generation

Start-up Timer

8

T1OSCO

RD5/PSP5

RD6/PSP6

RD7/PSP7

Power-on

Reset

8

Watchdog

Timer

4X PLL

ALU<8>

Brown-out

Reset

8

Precision

RE0/AN5/RD

Voltage

Reference

Low Voltage

Programming

RE1/AN6/WR

RE2/AN7/CS

MCLR

In-Circuit

VDD, VSS

Debugger

PWM1

PWM2

A/D Converter

Timer0

PWM1

Timer1

PWM2

Timer2

Timer3

Master

Addressable

USART

Synchronous

Parallel Slave Port

Data EEPROM

Serial Port

Note 1: The high order bits of the Direct Address for the RAM are from the BSR register (except for the MOVFFinstruction).

2: Many of the general purpose I/O pins are multiplexed with one or more peripheral module functions. The multiplexing combinations

are device dependent.

DS30485A-page 10

Preliminary

 2002 Microchip Technology Inc.

PIC18FXX39

TABLE 1-2:

Pin Name

PIC18F2X39 PINOUT I/O DESCRIPTIONS

Pin Number

Buffer

Type

Description

Type

DIP SOIC

MCLR/VPP

MCLR

1

Master Clear (input) or high voltage ICSP programming

enable pin.

I

ST

Master Clear (Reset) input. This pin is an active low

RESET to the device.

VPP

NC

I

—

ST

—

High voltage ICSP programming enable pin.

These pins should be left unconnected.

Oscillator crystal or external clock input.

Oscillator crystal input or external clock source input.

External clock source input. Always associated with

pin function OSC1. (See related OSC1/CLKI,

OSC2/CLKO pins.)

—

9

—

9

OSC1/CLKI

OSC1

I

CMOS

CLKI

OSC2/CLKO/RA6

OSC2

10

Oscillator crystal or clock output.

O

—

Oscillator crystal output. Connects to crystal or

resonator in Crystal Oscillator mode.

In EC mode, OSC2 pin outputs CLKO which has 1/4

the frequency of OSC1, and denotes the instruction

cycle rate.

CLKO

RA6

I/O

TTL

General purpose I/O pin.

PORTA is a bi-directional I/O port.

RA0/AN0

RA0

2

3

4

2

3

4

I/O

I

TTL

Digital I/O.

AN0

Analog

Analog input 0.

RA1/AN1

RA1

I/O

I

TTL

Analog

Digital I/O.

Analog input 1.

AN1

RA2/AN2/VREF-

RA2

I/O

I

TTL

Analog

Digital I/O.

AN2

Analog input 2.

VREF-

A/D Reference Voltage (Low) input.

RA3/AN3/VREF+

5

RA3

I/O

I

TTL

Analog

Digital I/O.

AN3

Analog input 3.

VREF+

A/D Reference Voltage (High) input.

RA4/T0CKI

6

7

6

7

RA4

I/O

I

ST/OD

ST

Digital I/O. Open drain when configured as output.

Timer0 external clock input.

T0CKI

RA5/AN4/SS/LVDIN

RA5

AN4

SS

I/O

TTL

Analog

ST

Digital I/O.

I

Analog input 4.

SPI Slave Select input.

LVDIN

Analog

Low Voltage Detect input.

RA6

See the OSC2/CLKO/RA6 pin.

Legend: TTL = TTL compatible input

ST = Schmitt Trigger input with CMOS levels

= Output

OD = Open Drain (no P diode to VDD)

CMOS = CMOS compatible input or output

I

= Input

O

P

= Power

 2002 Microchip Technology Inc.

Preliminary

DS30485A-page 11

PIC18FXX39

TABLE 1-2:

PIC18F2X39 PINOUT I/O DESCRIPTIONS (CONTINUED)

Pin Number

DIP SOIC

Buffer

Type

Pin Name

Description

Type

PORTB is a bi-directional I/O port. PORTB can be software

programmed for internal weak pull-ups on all inputs.

RB0/INT0

RB0

21

22

23

21

22

23

I/O

I

TTL

ST

Digital I/O.

INT0

External interrupt 0.

RB1/INT1

RB1

I/O

I

TTL

ST

Digital I/O.

External interrupt 1.

INT1

RB2/INT2

RB2

I/O

I

TTL

ST

Digital I/O.

External interrupt 2.

INT2

RB3

RB4

24

25

24

25

I/O

TTL

Digital I/O.

Interrupt-on-change pin.

RB5/PGM

RB5

26

27

28

26

27

28

I/O

TTL

ST

Digital I/O. Interrupt-on-change pin.

PGM

Low Voltage ICSP programming enable pin.

RB6/PGC

RB6

I/O

TTL

ST

Digital I/O. Interrupt-on-change pin.

In-Circuit Debugger and ICSP programming clock pin.

PGC

RB7/PGD

RB7

I/O

TTL

ST

Digital I/O. Interrupt-on-change pin.

In-Circuit Debugger and ICSP programming data pin.

PGD

Legend: TTL = TTL compatible input

ST = Schmitt Trigger input with CMOS levels

= Output

OD = Open Drain (no P diode to VDD)

CMOS = CMOS compatible input or output

I

= Input

O

P

= Power

DS30485A-page 12

Preliminary

 2002 Microchip Technology Inc.

PIC18FXX39

TABLE 1-2:

Pin Name

PIC18F2X39 PINOUT I/O DESCRIPTIONS (CONTINUED)

Pin Number

Buffer

Type

Description

Type

DIP SOIC

PORTC is a bi-directional I/O port.

RC0/T13CKI

RC0

11

14

11

14

I/O

I

ST

Digital I/O.

T13CKI

Timer1/Timer3 external clock input.

RC3/SCK/SCL

RC3

I/O

ST

Digital I/O.

SCK

Synchronous serial clock input/output for SPI mode.

SCL

Synchronous serial clock input/output for I²C mode.

RC4/SDI/SDA

15

RC4

I/O

I

I/O

ST

Digital I/O.

SDI

SDA

SPI Data in.

I²C Data I/O.

RC5/SDO

16

17

16

17

RC5

I/O

O

ST

—

Digital I/O.

SDO

SPI Data out.

RC6/TX/CK

RC6

TX

I/O

O

I/O

ST

—

ST

Digital I/O.

USART Asynchronous Transmit.

USART Synchronous Clock (see related RX/DT).

CK

RC7/RX/DT

18

RC7

RX

I/O

I

I/O

ST

Digital I/O.

USART Asynchronous Receive.

DT

USART Synchronous Data (see related TX/CK).

PWM1

PWM2

VSS

13

12

13

12

O

P

—

PWM Channel 1 (motor control) output.

PWM Channel 2 (motor control) output.

Ground reference for logic and I/O pins.

Positive supply for logic and I/O pins.

CMOS = CMOS compatible input or output

8, 19 8, 19

20 20

VDD

Legend: TTL = TTL compatible input

ST = Schmitt Trigger input with CMOS levels

= Output

OD = Open Drain (no P diode to VDD)

I

= Input

O

P

= Power

 2002 Microchip Technology Inc.

Preliminary

DS30485A-page 13

PIC18FXX39

TABLE 1-3:

PIC18F4X39 PINOUT I/O DESCRIPTIONS

Pin Number

Buffer

Type

Pin Name

Description

Type

DIP QFN TQFP

MCLR/VPP

MCLR

1

18

32

18

Master Clear (input) or high voltage ICSP

programming enable pin.

I

ST

Master Clear (Reset) input. This pin is an active

low RESET to the device.

VPP

High voltage ICSP programming enable pin.

OSC1/CLKI

13

30

Oscillator crystal or external clock input.

Oscillator crystal input or external clock source

input.

OSC1

I

CMOS

CLKI

External clock source input. Always associated

with pin function OSC1. (See related OSC1/CLKI,

OSC2/CLKO pins.)

OSC2/CLKO/RA6

OSC2

14

33

31

Oscillator crystal or clock output.

O

—

Oscillator crystal output. Connects to crystal

or resonator in Crystal Oscillator mode.

In EC mode, OSC2 pin outputs CLKO,

which has 1/4 the frequency of OSC1 and

denotes the instruction cycle rate.

General purpose I/O pin.

CLKO

RA6

I/O

TTL

PORTA is a bi-directional I/O port.

RA0/AN0

RA0

2

3

4

19

20

21

19

20

21

I/O

I

TTL

Digital I/O.

AN0

Analog

Analog input 0.

RA1/AN1

RA1

I/O

I

TTL

Analog

Digital I/O.

Analog input 1.

AN1

RA2/AN2/VREF-

RA2

I/O

I

TTL

Analog

Digital I/O.

AN2

Analog input 2.

VREF-

A/D Reference Voltage (Low) input.

RA3/AN3/VREF+

5

22

RA3

I/O

I

TTL

Analog

Digital I/O.

AN3

VREF+

Analog input 3.

A/D Reference Voltage (High) input.

RA4/T0CKI

6

7

23

24

23

24

RA4

I/O

I

ST/OD

ST

Digital I/O. Open drain when configured as output.

Timer0 external clock input.

T0CKI

RA5/AN4/SS/LVDIN

RA5

AN4

SS

I/O

TTL

Analog

ST

Digital I/O.

I

Analog input 4.

SPI Slave Select input.

Low Voltage Detect input.

LVDIN

Analog

RA6

(See the OSC2/CLKO/RA6 pin.)

Legend: TTL = TTL compatible input

ST = Schmitt Trigger input with CMOS levels

= Output

OD = Open Drain (no P diode to VDD)

CMOS = CMOS compatible input or output

I

= Input

O

P

= Power

DS30485A-page 14

Preliminary

 2002 Microchip Technology Inc.

PIC18FXX39

TABLE 1-3:

Pin Name

PIC18F4X39 PINOUT I/O DESCRIPTIONS (CONTINUED)

Pin Number

Buffer

Type

Description

Type

DIP QFN TQFP

PORTB is a bi-directional I/O port. PORTB can be

software programmed for internal weak pull-ups on all

inputs.

RB0/INT0

RB0

33

34

35

9

8

9

I/O

I

TTL

ST

Digital I/O.

INT0

External interrupt 0.

RB1/INT1

10

11

RB1

I/O

I

TTL

ST

Digital I/O.

External interrupt 1.

INT1

RB2/INT2

10

RB2

I/O

I

TTL

ST

Digital I/O.

External interrupt 2.

INT2

RB3

RB4

36

37

38

12

14

15

11

14

15

I/O

TTL

Digital I/O.

Digital I/O. Interrupt-on-change pin.

RB5/PGM

RB5

I/O

TTL

ST

Digital I/O. Interrupt-on-change pin.

Low Voltage ICSP programming enable pin.

PGM

RB6/PGC

39

40

16

17

16

17

RB6

I/O

TTL

ST

Digital I/O. Interrupt-on-change pin.

In-Circuit Debugger and ICSP programming

clock pin.

PGC

RB7/PGD

RB7

I/O

TTL

ST

Digital I/O. Interrupt-on-change pin.

In-Circuit Debugger and ICSP programming

data pin.

PGD

Legend: TTL = TTL compatible input

ST = Schmitt Trigger input with CMOS levels

= Output

OD = Open Drain (no P diode to VDD)

CMOS = CMOS compatible input or output

I

= Input

O

P

= Power

 2002 Microchip Technology Inc.

Preliminary

DS30485A-page 15

PIC18FXX39

TABLE 1-3:

PIC18F4X39 PINOUT I/O DESCRIPTIONS (CONTINUED)

Pin Number

Buffer

Type

Pin Name

Description

Type

DIP QFN TQFP

PORTC is a bi-directional I/O port.

RC0/T13CKI

RC0

15

18

34

37

32

37

I/O

I

ST

Digital I/O.

T13CKI

Timer1/Timer3 external clock input.

RC3/SCK/SCL

RC3

SCK

I/O

ST

Digital I/O.

Synchronous serial clock input/output for

SPI mode.

SCL

I/O

ST

Synchronous serial clock input/output for

I²C mode.

RC4/SDI/SDA

RC4

23

42

I/O

I

I/O

ST

Digital I/O.

SDI

SPI Data in.

SDA

I²C Data I/O.

RC5/SDO

24

25

43

44

43

44

RC5

I/O

O

ST

—

Digital I/O.

SDO

SPI Data out.

RC6/TX/CK

RC6

TX

I/O

O

I/O

ST

—

ST

Digital I/O.

USART Asynchronous Transmit.

USART Synchronous Clock (see related RX/DT).

CK

RC7/RX/DT

26

1

RC7

RX

I/O

I

I/O

ST

Digital I/O.

USART Asynchronous Receive.

USART Synchronous Data (see related TX/CK).

DT

PWM1

PWM2

17

16

35

36

35

O

—

PWM Channel 1 (motor control) output.

PWM Channel 2 (motor control) output.

CMOS = CMOS compatible input or output

Legend: TTL = TTL compatible input

ST = Schmitt Trigger input with CMOS levels

= Output

OD = Open Drain (no P diode to VDD)

I

= Input

O

P

= Power

DS30485A-page 16

Preliminary

 2002 Microchip Technology Inc.

PIC18FXX39

TABLE 1-3:

Pin Name

PIC18F4X39 PINOUT I/O DESCRIPTIONS (CONTINUED)

Pin Number

Buffer

Type

Description

Type

DIP QFN TQFP

PORTD is a bi-directional I/O port, or a Parallel Slave

Port (PSP) for interfacing to a microprocessor port.

These pins have TTL input buffers when PSP module

is enabled.

RD0/PSP0

RD0

19

20

21

22

27

28

29

30

38

39

40

41

2

38

39

40

41

2

I/O

ST

Digital I/O.

PSP0

TTL

Parallel Slave Port Data.

RD1/PSP1

RD1

ST

TTL

Digital I/O.

Parallel Slave Port Data.

PSP1

RD2/PSP2

RD2

ST

TTL

Digital I/O.

Parallel Slave Port Data.

PSP2

RD3/PSP3

RD3

ST

TTL

Digital I/O.

Parallel Slave Port Data.

PSP3

RD4/PSP4

RD4

ST

TTL

Digital I/O.

Parallel Slave Port Data.

PSP4

RD5/PSP5

3

RD5

ST

TTL

Digital I/O.

Parallel Slave Port Data.

PSP5

RD6/PSP6

4

RD6

ST

TTL

Digital I/O.

Parallel Slave Port Data.

PSP6

RD7/PSP7

5

RD7

ST

TTL

Digital I/O.

Parallel Slave Port Data.

PSP7

Legend: TTL = TTL compatible input

ST = Schmitt Trigger input with CMOS levels

= Output

OD = Open Drain (no P diode to VDD)

CMOS = CMOS compatible input or output

I

= Input

O

P

= Power

 2002 Microchip Technology Inc.

Preliminary

DS30485A-page 17

PIC18FXX39

TABLE 1-3:

PIC18F4X39 PINOUT I/O DESCRIPTIONS (CONTINUED)

Pin Number

Buffer

Type

Pin Name

Description

Type

DIP QFN TQFP

PORTE is a bi-directional I/O port.

RE0/RD/AN5

RE0

8

9

25

26

27

25

26

27

I/O

ST

Digital I/O.

RD

TTL

Read control for parallel slave port

(see also WR and CS pins).

Analog input 5.

AN5

Analog

RE1/WR/AN6

RE1

ST

TTL

Digital I/O.

WR

Write control for parallel slave port

(see CS and RD pins).

Analog input 6.

AN6

Analog

RE2/CS/AN7

10

RE2

ST

TTL

Digital I/O.

CS

Chip Select control for parallel slave port

(see related RD and WR).

Analog input 7.

AN7

VSS

VDD

Analog

—

12, 31 6, 31 6, 29

11, 32 7, 28, 7, 28

P

Ground reference for logic and I/O pins.

Positive supply for logic and I/O pins.

29

AVSS

AVDD

NC

—

30

8

—

P

—

Ground reference for analog modules.

Positive supply for analog modules.

These pins should be left unconnected.

13 12, 13,

33, 34

Legend: TTL = TTL compatible input

ST = Schmitt Trigger input with CMOS levels

= Output

OD = Open Drain (no P diode to VDD)

CMOS = CMOS compatible input or output

I

= Input

O

P

= Power

DS30485A-page 18

Preliminary

 2002 Microchip Technology Inc.

PIC18FXX39

FIGURE 2-1:

CRYSTAL/CERAMIC

2.0

2.1

OSCILLATOR

RESONATOROPERATION

(HS CONFIGURATION)

CONFIGURATIONS

(1)

Oscillator Types

C1

OSC1

The PIC18FXX39 can be operated in four different

Oscillator modes at a frequency of 20 MHz. The user

can program three configuration bits (FOSC2, FOSC1,

and FOSC0) to select one of these four modes:

To

Internal

Logic

(3)

RF

XTAL

SLEEP

(2)

RS

1. HS

2. HS + PLL

High Speed Crystal/Resonator

(1)

PIC18FXX39

C2

OSC2

High Speed Crystal/Resonator

with PLL enabled using 5 MHz

crystal

Note 1: See Table 2-1 for recommended values of

C1 and C2.

3. EC

4. ECIO

External Clock

External Clock with I/O pin

enabled

2: A series resistor (RS) may be required for

AT strip cut crystals.

3: RF varies with the Oscillator mode chosen.

Note: The operation of the Motor Control kernel

and its APIs (Section 14.0) is based on an

assumed clock frequency of 20 MHz.

Changing the oscillator frequency will

change the timing used in the Motor Con-

trol kernel accordingly. To achieve the best

results in motor control applications, a

clock frequency of 20 MHz is highly

recommended.

An external clock source may also be connected to the

OSC1 pin in the HS mode, as shown in Figure 2-2.

FIGURE 2-2:

EXTERNAL CLOCK INPUT

OPERATION (HS OSC

CONFIGURATION)

OSC1

PIC18FXX39

OSC2

Clock from

Ext. System

2.2

Crystal Oscillator/Ceramic

Resonators

Open

In HS or HS+PLL Oscillator modes, a crystal or ceramic

resonator is connected to the OSC1 and OSC2 pins to

establish oscillation. Figure 2-1 shows the pin

connections.

The PIC18FXX39 oscillator design requires the use of

a parallel cut crystal.

Note 1: Higher capacitance increases the stability

of the oscillator, but also increases the

start-up time.

2: Since each resonator/crystal has its own

characteristics, the user should consult the

resonator/crystal manufacturer for appro-

priate values of external components, or

verify oscillator performance.

Note: Use of a series cut crystal may give a fre-

quency out of the crystal manufacturers

specifications.

 2002 Microchip Technology Inc.

Preliminary

DS30485A-page 19

PIC18FXX39

TABLE 2-1:

CAPACITOR SELECTION FOR

FIGURE 2-3:

EXTERNAL CLOCK INPUT

OPERATION

CRYSTAL OSCILLATOR

(EC CONFIGURATION)

Ranges Tested:

Mode

Freq

C1

C2

OSC1

PIC18FXX39

OSC2

Clock from

Ext. System

HS

20.0 MHz

15-33 pF

FOSC/4

These values are for design guidance only.

See notes following this table.

Crystals Used

The ECIO Oscillator mode functions like the EC mode,

except that the OSC2 pin becomes an additional gen-

eral purpose I/O pin. The I/O pin becomes bit 6 of

PORTA (RA6). Figure 2-4 shows the pin connections

for the ECIO Oscillator mode.

20.0 MHz Epson CA-301 20.000M-C ± 30 PPM

Note 1: Higher capacitance increases the stability

of the oscillator, but also increases the

start-up time.

FIGURE 2-4:

EXTERNAL CLOCK INPUT

OPERATION

2: Rs may be required in HS mode to avoid

overdriving crystals with low drive level

specification.

(ECIOCONFIGURATION)

3: Since each resonator/crystal has its own

characteristics, the user should consult the

resonator/crystal manufacturer for appro-

priate values of external components, or

verify oscillator performance.

OSC1

PIC18FXX39

I/O (OSC2)

Clock from

Ext. System

RA6

2.4

HS/PLL

2.3

External Clock Input

A Phase Locked Loop circuit is provided as a program-

mable option for users that want to multiply the fre-

quency of the incoming crystal oscillator signal by 4.

For an input clock frequency of 5 MHz, the internal

clock frequency will be multiplied to 20 MHz. This is

useful for customers who are concerned with EMI due

to high frequency crystals.

The PLL can only be enabled when the oscillator con-

figuration bits are programmed for HS mode. If they are

programmed for any other mode, the PLL is not

enabled and the system clock will come directly from

OSC1.

The EC and ECIO Oscillator modes require an external

clock source to be connected to the OSC1 pin. The

feedback device between OSC1 and OSC2 is turned

off in these modes to save current. There is no oscilla-

tor start-up time required after a Power-on Reset or

after a recovery from SLEEP mode.

In the EC Oscillator mode, the oscillator frequency

divided by 4 is available on the OSC2 pin. This signal

may be used for test purposes or to synchronize other

logic. Figure 2-3 shows the pin connections for the EC

Oscillator mode.

The PLL is one of the modes specified by the

FOSC<2:0> configuration bits. The Oscillator mode is

specified during device programming.

A PLL lock timer is used to ensure that the PLL has

locked before device execution starts. The PLL lock

timer has a time-out that is called TPLL.

DS30485A-page 20

Preliminary

 2002 Microchip Technology Inc.

PIC18FXX39

FIGURE 2-5:

PLL BLOCK DIAGRAM

HS Osc

(from Configuration

bit Register)

PLL Enable

Phase

Comparator

OSC2

FIN

Loop

Filter

VCO

Crystal

Osc

FOUT

SYSCLK

OSC1

÷4

The first timer is the Power-up Timer (PWRT), which

optionally provides a fixed delay of 72 ms (nominal) on

power-up only (POR and BOR). The second timer is

the Oscillator Start-up Timer (OST), intended to keep

the chip in RESET until the crystal oscillator is stable.

With the PLL enabled (HS/PLL Oscillator mode), the

time-out sequence following a Power-on Reset is differ-

ent from other Oscillator modes. The time-out

sequence is as follows:

2.5

Effects of SLEEP Mode on the

On-Chip Oscillator

When the device executes a SLEEP instruction, the

oscillator is turned off and the device is held at the

beginning of an instruction cycle (Q1 state). With the

oscillator off, the OSC1 and OSC2 signals will stop

oscillating. Since all the transistor switching currents

have been removed, SLEEP mode achieves the lowest

current consumption of the device (only leakage cur-

rents). Enabling any on-chip feature that will operate

during SLEEP will increase the current consumed dur-

ing SLEEP. The user can wake from SLEEP through

external RESET, Watchdog Timer Reset, or through an

interrupt.

1. The PWRT time-out is invoked after a POR time

delay has expired.

2. The Oscillator Start-up Timer (OST) is invoked.

However, this is still not a sufficient amount of

time to allow the PLL to lock at high frequencies.

3. The PWRT timer is used to provide an additional

fixed 2 ms (nominal) time-out to allow the PLL

ample time to lock to the incoming clock

frequency.

2.6

Power-up Delays

Power-up delays are controlled by two timers, so that

no external RESET circuitry is required for most appli-

cations. The delays ensure that the device is kept in

RESET, until the device power supply and clock are

stable. For additional information on RESET operation,

see Section 3.0.

TABLE 2-2:

OSC Mode

OSC1 AND OSC2 PIN STATES IN SLEEP MODE

OSC1 Pin

OSC2 Pin

ECIO

EC

HS

Floating

Configured as PORTA, bit 6

At logic low

Feedback inverter disabled, at quiescent

voltage level

Note: See Table 3-1 in the “Reset” section, for time-outs due to SLEEP and MCLR Reset.

 2002 Microchip Technology Inc.

Preliminary

DS30485A-page 21

PIC18FXX39

NOTES:

DS30485A-page 22

Preliminary

 2002 Microchip Technology Inc.

PIC18FXX39

Most registers are not affected by a WDT wake-up,

since this is viewed as the resumption of normal oper-

ation. Status bits from the RCON register, RI, TO, PD,

POR and BOR, are set or cleared differently in different

RESET situations, as indicated in Table 3-2. These bits

are used in software to determine the nature of the

RESET. See Table 3-3 for a full description of the

RESET states of all registers.

A simplified block diagram of the On-Chip Reset Circuit

is shown in Figure 3-1.

The Enhanced MCU devices have a MCLR noise filter

in the MCLR Reset path. The filter will detect and

ignore small pulses.

3.0

RESET

The PIC18FXX39 differentiates between various kinds

of RESET:

a) Power-on Reset (POR)

b) MCLR Reset during normal operation

c) MCLR Reset during SLEEP

d) Watchdog Timer (WDT) Reset (during normal

operation)

e) Programmable Brown-out Reset (BOR)

f) RESETInstruction

g) Stack Full Reset

h) Stack Underflow Reset

The MCLR pin is not driven low by any internal

RESETS, including the WDT.

Most registers are unaffected by a RESET. Their status

is unknown on POR and unchanged by all other

RESETS. The other registers are forced to a “RESET

state” on Power-on Reset, MCLR, WDT Reset, Brown-

out Reset, MCLR Reset during SLEEP and by the

RESETinstruction.

FIGURE 3-1:

SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT

RESET

Instruction

Stack

Stack Full/Underflow Reset

External Reset

Pointer

MCLR

VDD

SLEEP

WDT

Module

Time-out

Reset

VDD Rise

Detect

Power-on Reset

Brown-out

Reset

S

BOREN

OST/PWRT

OST

10-bit Ripple Counter

Chip_Reset

Q

R

OSC1

PWRT

10-bit Ripple Counter

On-chip

RC OSC⁽¹⁾

Enable PWRT

(2)

Enable OST

Note 1: This is a separate oscillator from the RC oscillator of the CLKI pin.

2: See Table 3-1 for time-out situations.

 2002 Microchip Technology Inc.

Preliminary

DS30485A-page 23

PIC18FXX39

3.1

Power-on Reset (POR)

3.3

Oscillator Start-up Timer (OST)

A Power-on Reset pulse is generated on-chip when

VDD rise is detected. To take advantage of the POR cir-

cuitry, just tie the MCLR pin directly (or through a resis-

tor) to VDD. This will eliminate external RC components

usually needed to create a Power-on Reset delay. A

The Oscillator Start-up Timer (OST) provides a 1024

oscillator cycle (from OSC1 input) delay after the

PWRT delay is over (parameter 32). This ensures that

the crystal oscillator or resonator has started and

stabilized.

The OST time-out is invoked only for XT, LP and HS

modes and only on Power-on Reset or wake-up from

SLEEP.

minimum rise rate for

VDD

is specified

(parameter D004). For a slow rise time, see Figure 3-2.

When the device starts normal operation (i.e., exits the

RESET condition), device operating parameters (volt-

age, frequency, temperature, etc.) must be met to

ensure operation. If these conditions are not met, the

device must be held in RESET until the operating

conditions are met.

3.4

PLL Lock Time-out

With the PLL enabled, the time-out sequence following

a Power-on Reset is different from other Oscillator

modes. A portion of the Power-up Timer is used to pro-

vide a fixed time-out that is sufficient for the PLL to lock

to the main oscillator frequency. This PLL lock time-out

(TPLL) is typically 2 ms and follows the Oscillator

Start-up Time-out (OST).

FIGURE 3-2:

EXTERNAL POWER-ON

RESET CIRCUIT (FOR

SLOW VDD POWER-UP)

3.5

Brown-out Reset (BOR)

VDD

A configuration bit, BOREN, can disable (if clear/

programmed), or enable (if set) the Brown-out Reset

circuitry. If VDD falls below parameter D005 for greater

than parameter 35, the brown-out situation will reset

the chip. A RESET may not occur if VDD falls below

parameter D005 for less than parameter 35. The chip

will remain in Brown-out Reset until VDD rises above

BVDD. If the Power-up Timer is enabled, it will be

invoked after VDD rises above BVDD; it then will keep

the chip in RESET for an additional time delay

(parameter 33). If VDD drops below BVDD while the

Power-up Timer is running, the chip will go back into a

Brown-out Reset and the Power-up Timer will be initial-

ized. Once VDD rises above BVDD, the Power-up Timer

will execute the additional time delay.

D

R

R1

MCLR

PIC18FXXXX

C

Note 1: External Power-on Reset circuit is required

only if the VDD power-up slope is too slow.

The diode D helps discharge the capacitor

quickly when VDD powers down.

2: R < 40 kΩ is recommended to make sure that

the voltage drop across R does not violate

the device’s electrical specification.

3: R1 = 100Ω to 1 kΩ will limit any current flow-

ing into MCLR from external capacitor C, in

the event of MCLR/VPP pin breakdown due to

Electrostatic Discharge (ESD) or Electrical

Overstress (EOS).

3.6

Time-out Sequence

On power-up, the time-out sequence is as follows:

First, PWRT time-out is invoked after the POR time

delay has expired. Then, OST is activated. The total

time-out will vary based on oscillator configuration and

the status of the PWRT. For example, in RC mode with

the PWRT disabled, there will be no time-out at all.

Figure 3-3, Figure 3-4, Figure 3-5, Figure 3-6 and

Figure 3-7 depict time-out sequences on power-up.

Since the time-outs occur from the POR pulse, if MCLR

is kept low long enough, the time-outs will expire.

Bringing MCLR high will begin execution immediately

(Figure 3-5). This is useful for testing purposes or to

synchronize more than one PIC18FXXX device

operating in parallel.

3.2

Power-up Timer (PWRT)

The Power-up Timer provides a fixed nominal time-out

(parameter 33) only on power-up from the POR. The

Power-up Timer operates on an internal RC oscillator.

The chip is kept in RESET as long as the PWRT is

active. The PWRT’s time delay allows VDD to rise to an

acceptable level. A configuration bit is provided to

enable/disable the PWRT.

The power-up time delay will vary from chip-to-chip due

to VDD, temperature and process variation. See DC

parameter D033 for details.

Table 3-2 shows the RESET conditions for some

Special Function Registers, while Table 3-3 shows the

RESET conditions for all the registers.

DS30485A-page 24

Preliminary

 2002 Microchip Technology Inc.

PIC18FXX39

TABLE 3-1:

TIME-OUT IN VARIOUS SITUATIONS

Power-up⁽²⁾

Wake-up from

Oscillator

Brown-out

SLEEP or

Configuration

PWRTE = 0

PWRTE = 1

Oscillator Switch

72 ms + 1024 TOSC

+ 2ms

1024 TOSC

+ 2 ms

72 ms⁽²⁾+ 1024 TOSC

+ 2 ms

HS with PLL enabled⁽¹⁾

1024 TOSC + 2 ms

HS, XT, LP

EC

External RC

72 ms + 1024 TOSC

72 ms

1024 TOSC

72 ms⁽²⁾+ 1024 TOSC

1024 TOSC

—

72 ms⁽²⁾

—

72 ms

72 ms⁽²⁾

Note 1: 2 ms is the nominal time required for the 4x PLL to lock.

2: 72 ms is the nominal power-up timer delay, if implemented.

REGISTER 3-1:

RCON REGISTER BITS AND POSITIONS

R/W-0

IPEN

U-0

—

U-0

—

R/W-1

RI

R-1

TO

R-1

PD

R/W-0

POR

R/W-0

BOR

bit 7

bit 0

Note 1: Refer to Section 4.14 (page 50) for bit definitions.

TABLE 3-2:

STATUS BITS, THEIR SIGNIFICANCE AND THE INITIALIZATION CONDITION FOR

RCON REGISTER

Program

Counter

RCON

Condition

RI TO PD POR BOR STKFUL STKUNF

Register

Power-on Reset

MCLR Reset during normal

operation

0000h

0--1 1100

0--u uuuu

1

u

1

u

1

u

0

u

0

u

Software Reset during normal

operation

Stack Full Reset during normal

operation

Stack Underflow Reset during

normal operation

0000h

0--0 uuuu

0--u uu11

0

u

1

u

1

u

MCLR Reset during SLEEP

WDT Reset

WDT Wake-up

Brown-out Reset

Interrupt wake-up from SLEEP

0000h

0--u 10uu

0--u 01uu

u--u 00uu

0--1 11u0

u--u 00uu

u

1

u

1

u

1

0

1

0

1

0

1

0

u

1

u

0

u

PC + 2

0000h

PC + 2⁽¹⁾

Legend: u= unchanged, x= unknown, - = unimplemented bit, read as '0'

Note 1: When the wake-up is due to an interrupt and the GIEH or GIEL bits are set, the PC is loaded with the

interrupt vector (0x000008h or 0x000018h).

 2002 Microchip Technology Inc.

Preliminary

DS30485A-page 25

PIC18FXX39

TABLE 3-3:

INITIALIZATION CONDITIONS FOR ALL REGISTERS

MCLR Resets

WDT Reset

Power-on Reset,

Brown-out Reset

Wake-up via WDT

or Interrupt

Register

Applicable Devices

RESET Instruction

Stack Resets

TOSU

TOSH

TOSL

STKPTR

PCLATU

PCLATH

PCL

TBLPTRU

TBLPTRH

TBLPTRL

TABLAT

PRODH

PRODL

INTCON

INTCON2

INTCON3

INDF0

2439 4439 2539 4539

---0 0000

0000 0000

00-0 0000

---0 0000

0000 0000

--00 0000

0000 0000

xxxx xxxx

0000 000x

1111 -1-1

11-0 0-00

N/A

---0 0000

0000 0000

uu-0 0000

---0 0000

0000 0000

--00 0000

0000 0000

uuuu uuuu

0000 000u

1111 -1-1

11-0 0-00

N/A

---0 uuuu⁽¹⁾

uuuu uuuu⁽¹⁾

uu-u uuuu⁽¹⁾

---u uuuu

uuuu uuuu

PC + 2⁽²⁾

--uu uuuu

uuuu uuuu

uuuu uuuu⁽³⁾

uuuu -u-u⁽³⁾

uu-u u-uu⁽³⁾

N/A

POSTINC0

N/A

POSTDEC0 2439 4439 2539 4539

N/A

PREINC0

PLUSW0

FSR0H

FSR0L

WREG

2439 4439 2539 4539

N/A

---- xxxx

xxxx xxxx

N/A

---- uuuu

uuuu uuuu

N/A

---- uuuu

uuuu uuuu

N/A

INDF1

POSTINC1

N/A

POSTDEC1 2439 4439 2539 4539

N/A

PREINC1

PLUSW1

2439 4439 2539 4539

N/A

Legend: u= unchanged, x= unknown, -= unimplemented bit, read as '0', q= value depends on condition.

Shaded cells indicate conditions do not apply for the designated device.

* These registers are retained to maintain compatibility with PIC18FXX2 devices; however, one or more bits

are reserved. Users should not modify the value of these bits. See Section 4.9.2 for details.

Note 1: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are

updated with the current value of the PC. The STKPTR is modified to point to the next location in the

hardware stack.

2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt

vector (0008h or 0018h).

3: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).

4: See Table 3-2 for RESET value for specific condition.

5: Bit 6 of PORTA, LATA, and TRISA are enabled in ECIO and RCIO Oscillator modes only. In all other

Oscillator modes, they are disabled and read ‘0’.

6: Bit 6 of PORTA, LATA and TRISA are not available on all devices. When unimplemented, they are read ‘0’.

DS30485A-page 26

Preliminary

 2002 Microchip Technology Inc.

PIC18FXX39

TABLE 3-3:

Register

INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)

MCLR Resets

WDT Reset

Power-on Reset,

Brown-out Reset

Wake-up via WDT

or Interrupt

Applicable Devices

RESET Instruction

Stack Resets

FSR1H

FSR1L

BSR

INDF2

POSTINC2

2439 4439 2539 4539

---- xxxx

xxxx xxxx

---- 0000

N/A

---- uuuu

uuuu uuuu

---- 0000

N/A

---- uuuu

uuuu uuuu

---- uuuu

N/A

POSTDEC2 2439 4439 2539 4539

N/A

PREINC2

PLUSW2

FSR2H

2439 4439 2539 4539

N/A

---- xxxx

xxxx xxxx

---x xxxx

0000 0000

xxxx xxxx

1111 1111

---- ---0

--00 0101

---- ---0

0--q 11qq

xxxx xxxx

0-00 0000

0000 0000

1111 1111

-000 0000

xxxx xxxx

0000 0000

---- uuuu

uuuu uuuu

---u uuuu

uuuu uuuu

1111 1111

---- ---0

--00 0101

---- ---0

0--q qquu

uuuu uuuu

u-uu uuuu

0000 0000

1111 1111

-000 0000

uuuu uuuu

0000 0000

---- uuuu

uuuu uuuu

---u uuuu

uuuu uuuu

---- ---u

--uu uuuu

---- ---u

u--u qquu

uuuu uuuu

u-uu uuuu

uuuu uuuu

1111 1111

-uuu uuuu

uuuu uuuu

FSR2L

STATUS

TMR0H

TMR0L

T0CON

OSCCON^*

LVDCON

WDTCON

RCON⁽⁴⁾

TMR1H

TMR1L

T1CON

TMR2^*

PR2^*

T2CON^*

SSPBUF

SSPADD

SSPSTAT

SSPCON1

SSPCON2

Legend: u= unchanged, x= unknown, -= unimplemented bit, read as '0', q= value depends on condition.

Shaded cells indicate conditions do not apply for the designated device.

* These registers are retained to maintain compatibility with PIC18FXX2 devices; however, one or more bits

are reserved. Users should not modify the value of these bits. See Section 4.9.2 for details.

Note 1: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are

updated with the current value of the PC. The STKPTR is modified to point to the next location in the

hardware stack.

2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt

vector (0008h or 0018h).

3: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).

4: See Table 3-2 for RESET value for specific condition.

5: Bit 6 of PORTA, LATA, and TRISA are enabled in ECIO and RCIO Oscillator modes only. In all other

Oscillator modes, they are disabled and read ‘0’.

6: Bit 6 of PORTA, LATA and TRISA are not available on all devices. When unimplemented, they are read ‘0’.

 2002 Microchip Technology Inc.

Preliminary

DS30485A-page 27

PIC18FXX39

TABLE 3-3:

INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)

MCLR Resets

WDT Reset

Power-on Reset,

Brown-out Reset

Wake-up via WDT

or Interrupt

Register

Applicable Devices

RESET Instruction

Stack Resets

ADRESH

ADRESL

ADCON0

ADCON1

CCPR1H

CCPR1L^*

2439 4439 2539 4539

xxxx xxxx

0000 00-0

00-- 0000

xxxx xxxx

--00 0000

xxxx xxxx

--00 0000

xxxx xxxx

0000 0000

0000 -010

0000 000x

0000 0000

xx-0 x000

---- ----

uuuu uuuu

0000 00-0

00-- 0000

uuuu uuuu

--00 0000

uuuu uuuu

--00 0000

uuuu uuuu

0000 0000

0000 -010

0000 000x

0000 0000

uu-0 u000

---- ----

uuuu uuuu

uuuu uu-u

uu-- uuuu

uuuu uuuu

--uu uuuu

uuuu uuuu

--uu uuuu

uuuu uuuu

uuuu -uuu

uuuu uuuu

uu-0 u000

---- ----

CCP1CON^*2439 4439 2539 4539

CCPR2H

2439 4439 2539 4539

CCPR2L^*

CCP2CON^*2439 4439 2539 4539

TMR3H

TMR3L

T3CON

SPBRG

RCREG

TXREG

TXSTA

RCSTA

EEADR

EEDATA

EECON1

EECON2

2439 4439 2539 4539

Legend: u= unchanged, x= unknown, -= unimplemented bit, read as '0', q= value depends on condition.

Shaded cells indicate conditions do not apply for the designated device.

* These registers are retained to maintain compatibility with PIC18FXX2 devices; however, one or more bits

are reserved. Users should not modify the value of these bits. See Section 4.9.2 for details.

Note 1: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are

updated with the current value of the PC. The STKPTR is modified to point to the next location in the

hardware stack.

2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt

vector (0008h or 0018h).

3: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).

4: See Table 3-2 for RESET value for specific condition.

5: Bit 6 of PORTA, LATA, and TRISA are enabled in ECIO and RCIO Oscillator modes only. In all other

Oscillator modes, they are disabled and read ‘0’.

6: Bit 6 of PORTA, LATA and TRISA are not available on all devices. When unimplemented, they are read ‘0’.

DS30485A-page 28

Preliminary

 2002 Microchip Technology Inc.

PIC18FXX39

TABLE 3-3:

Register

INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)

MCLR Resets

WDT Reset

Power-on Reset,

Brown-out Reset

Wake-up via WDT

or Interrupt

Applicable Devices

RESET Instruction

Stack Resets

IPR2

PIR2

PIE2

2439 4439 2539 4539

---1 1111

---0 0000

1111 1111

-111 1111

0000 0000

-000 0000

0000 0000

-000 0000

0000 -111

1111 1111

-111 1111⁽⁵⁾

---- -xxx

xxxx xxxx

-xxx xxxx⁽⁵⁾

---- -000

xxxx xxxx

-x0x 0000⁽⁵⁾

---1 1111

---0 0000

1111 1111

-111 1111

0000 0000

-000 0000

0000 0000

-000 0000

0000 -111

1111 1111

-111 1111⁽⁵⁾

---- -uuu

uuuu uuuu

-uuu uuuu⁽⁵⁾

---- -000

uuuu uuuu

-u0u 0000⁽⁵⁾

---u uuuu

---u uuuu⁽³⁾

---u uuuu

uuuu uuuu

-uuu uuuu

uuuu uuuu⁽³⁾

-uuu uuuu⁽³⁾

uuuu uuuu

-uuu uuuu

uuuu -uuu

uuuu uuuu

-uuu uuuu⁽⁵⁾

---- -uuu

uuuu uuuu

-uuu uuuu⁽⁵⁾

---- -uuu

uuuu uuuu

-uuu uuuu⁽⁵⁾

IPR1

PIR1

PIE1

TRISE

TRISD

TRISC*

TRISB

TRISA^(5,6)

LATE

LATD

LATC*

LATB

LATA^(5,6)

PORTE

PORTD

PORTC*

PORTB

PORTA^(5,6)

Legend: u= unchanged, x= unknown, -= unimplemented bit, read as '0', q= value depends on condition.

Shaded cells indicate conditions do not apply for the designated device.

* These registers are retained to maintain compatibility with PIC18FXX2 devices; however, one or more bits

are reserved. Users should not modify the value of these bits. See Section 4.9.2 for details.

Note 1: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are

updated with the current value of the PC. The STKPTR is modified to point to the next location in the

hardware stack.

2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt

vector (0008h or 0018h).

3: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).

4: See Table 3-2 for RESET value for specific condition.

5: Bit 6 of PORTA, LATA, and TRISA are enabled in ECIO and RCIO Oscillator modes only. In all other

Oscillator modes, they are disabled and read ‘0’.

6: Bit 6 of PORTA, LATA and TRISA are not available on all devices. When unimplemented, they are read ‘0’.

 2002 Microchip Technology Inc.

Preliminary

DS30485A-page 29

PIC18FXX39

FIGURE 3-3:

TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD)

VDD

MCLR

INTERNAL POR

TPWRT

PWRT TIME-OUT

OST TIME-OUT

TOST

INTERNAL RESET

FIGURE 3-4:

TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 1

VDD

MCLR

INTERNAL POR

TPWRT

PWRT TIME-OUT

OST TIME-OUT

TOST

INTERNAL RESET

FIGURE 3-5:

TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 2

VDD

MCLR

INTERNAL POR

TPWRT

PWRT TIME-OUT

OST TIME-OUT

TOST

INTERNAL RESET

DS30485A-page 30

Preliminary

 2002 Microchip Technology Inc.

PIC18FXX39

FIGURE 3-6:

SLOW RISE TIME (MCLR TIED TO VDD)

5V

1V

0V

VDD

MCLR

INTERNAL POR

TPWRT

PWRT TIME-OUT

TOST

OST TIME-OUT

INTERNAL RESET

FIGURE 3-7:

TIME-OUT SEQUENCE ON POR W/ PLL ENABLED (MCLR TIED TO VDD)

VDD

MCLR

IINTERNAL POR

TPWRT

PWRT TIME-OUT

OST TIME-OUT

TOST

TPLL

PLL TIME-OUT

INTERNAL RESET

Note: TOST = 1024 clock cycles.

TPLL ≈ 2 ms max. First three stages of the PWRT timer.

 2002 Microchip Technology Inc.

Preliminary

DS30485A-page 31

PIC18FXX39

NOTES:

DS30485A-page 32

Preliminary

 2002 Microchip Technology Inc.

PIC18FXX39

The PIC18F2539 and PIC18F4539 each have a total of

24 Kbytes, or 12K of single word instructions of FLASH

memory, from addresses 0000h to 5FFFh. The next

8 Kbytes beyond this space (from 6000h to 7FFFh) are

reserved for the Motor Control kernel; accessing

locations in this range will return random information.

4.0

MEMORY ORGANIZATION

There are three memory blocks in Enhanced MCU

devices. These memory blocks are:

• Program Memory

• Data RAM

The PIC18F2439 and PIC18F4439 each have

12 Kbytes, or 6K of single word instructions of FLASH

memory, from addresses 0000h to 2FFFh. The next

4 Kbytes of this space (from 3000h to 3FFFh) are

reserved for the Motor Control kernel; accessing

locations in this range will return random information.

The RESET vector address for all devices is at 0000h,

and the interrupt vector addresses are at 0008h and

0018h.

• Data EEPROM

Data and program memory use separate busses,

which allows for concurrent access of these blocks.

Additional detailed information for FLASH program

memory and Data EEPROM is provided in Section 5.0

and Section 6.0, respectively.

4.1

Program Memory Organization

A 21-bit program counter is capable of addressing the

2-Mbyte program memory space. Accessing a location

between the physically implemented memory and the

top of the 2-MByte range will cause a read of all ‘0’s (a

NOPinstruction).

The memory maps for the PIC18FX439 and

PIC18FX539 devices are shown in Figure 4-1.

Note: The ProMPT Motor Control kernel is iden-

tical for all PIC18FXX39 devices, regard-

less of the difference in reserved block size

between PIC18FX439 and PIC18FX539

devices

FIGURE 4-1:

PROGRAM MEMORY MAP AND STACK FOR PIC18FXX39 DEVICES

PC<20:0>

CALL,RCALL,RETURN

RETFIE,RETLW

21

Stack Level 1

•

Stack Level 31

PIC18FX439 Devices

RESET Vector

High Priority Interrupt Vector

PIC18FX539 Devices

0000h

0008h

RESET Vector

High Priority Interrupt Vector

Low Priority Interrupt Vector

0008h

0018h

Low Priority Interrupt Vector 0018h

On-Chip

Program Memory

On-Chip

Program Memory

2FFFh

3000h

Reserved

3FFFh

4000h

5FFFh

6000h

Reserved

Read '0'

7FFFh

8000h

Read '0'

1FFFFFh

200000h

Note:

Size of memory areas not to scale.

 2002 Microchip Technology Inc.

Preliminary

DS30485A-page 33

PIC18FXX39

4.2.2

RETURN STACK POINTER

(STKPTR)

4.2

Return Address Stack

The return address stack allows any combination of up

to 31 program calls and interrupts to occur. The PC

(Program Counter) is pushed onto the stack when a

CALLor RCALLinstruction is executed, or an interrupt

is acknowledged. The PC value is pulled off the stack

on a RETURN, RETLW or a RETFIE instruction.

PCLATU and PCLATH are not affected by any of the

RETURNor CALLinstructions.

The stack operates as a 31-word by 21-bit RAM and a

5-bit stack pointer, with the stack pointer initialized to

00000b after all RESETS. There is no RAM associated

with stack pointer 00000b. This is only a RESET value.

During a CALLtype instruction, causing a push onto the

stack, the stack pointer is first incremented and the

RAM location pointed to by the stack pointer is written

with the contents of the PC. During a RETURN type

instruction, causing a pop from the stack, the contents

of the RAM location pointed to by the STKPTR are

transferred to the PC and then the stack pointer is

decremented.

The STKPTR register contains the stack pointer value,

the STKFUL (stack full) status bit, and the STKUNF

(stack underflow) status bits. Register 4-1 shows the

STKPTR register. The value of the stack pointer can be

0 through 31. The stack pointer increments when val-

ues are pushed onto the stack and decrements when

values are popped off the stack. At RESET, the stack

pointer value will be ‘0’. The user may read and write

the stack pointer value. This feature can be used by a

Real-Time Operating System for return stack

maintenance.

After the PC is pushed onto the stack 31 times (without

popping any values off the stack), the STKFUL bit is

set. The STKFUL bit can only be cleared in software or

by a POR.

The action that takes place when the stack becomes

full depends on the state of the STVREN (Stack Over-

flow Reset Enable) configuration bit. Refer to

Section 21.0 for a description of the device configura-

tion bits. If STVREN is set (default), the 31st push will

push the (PC + 2) value onto the stack, set the STKFUL

bit, and reset the device. The STKFUL bit will remain

set and the stack pointer will be set to ‘0’.

The stack space is not part of either program or data

space. The stack pointer is readable and writable, and

the address on the top of the stack is readable and writ-

able through SFR registers. Data can also be pushed

to, or popped from the stack using the top-of-stack

SFRs. Status bits indicate if the stack pointer is at, or

beyond the 31 levels provided.

If STVREN is cleared, the STKFUL bit will be set on the

31st push and the stack pointer will increment to 31.

Any additional pushes will not overwrite the 31st push,

and STKPTR will remain at 31.

When the stack has been popped enough times to

unload the stack, the next pop will return a value of zero

to the PC and sets the STKUNF bit, while the stack

pointer remains at ‘0’. The STKUNF bit will remain set

until cleared in software or a POR occurs.

4.2.1

TOP-OF-STACK ACCESS

The top of the stack is readable and writable. Three

register locations, TOSU, TOSH and TOSL hold the

contents of the stack location pointed to by the

STKPTR register. This allows users to implement a

software stack if necessary. After a CALL, RCALLor

interrupt, the software can read the pushed value by

reading the TOSU, TOSH and TOSL registers. These

values can be placed on a user defined software stack.

At return time, the software can replace the TOSU,

TOSH and TOSL and do a return.

Note: Returning a value of zero to the PC on an

underflow has the effect of vectoring the

program to the RESET vector, where the

stack conditions can be verified and

appropriate actions can be taken.

The user must disable the global interrupt enable bits

during this time to prevent inadvertent stack

operations.

DS30485A-page 34

Preliminary

 2002 Microchip Technology Inc.

PIC18FXX39

REGISTER 4-1:

STKPTR REGISTER

R/C-0 R/C-0

U-0

—

R/W-0

SP4

R/W-0

SP3

R/W-0

SP2

R/W-0

SP1

R/W-0

SP0

STKFUL STKUNF

bit 7

bit 0

bit 7⁽¹⁾

bit 6⁽¹⁾

STKFUL: Stack Full Flag bit

1= Stack became full or overflowed

0= Stack has not become full or overflowed

STKUNF: Stack Underflow Flag bit

1= Stack underflow occurred

0= Stack underflow did not occur

bit 5

Unimplemented: Read as '0'

bit 4-0

SP4:SP0: Stack Pointer Location bits

Note 1: Bit 7 and bit 6 can only be cleared in user software or by a POR.

Legend:

R = Readable bit

- n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

FIGURE 4-2:

RETURN ADDRESS STACK AND ASSOCIATED REGISTERS

Return Address Stack

11111

11110

11101

STKPTR<4:0>

00010

TOSU

0x00

TOSH

0x1A

TOSL

0x34

00011

0x001A34 00010

0x000D58 00001

00000

Top-of-Stack

4.2.3

PUSHAND POPINSTRUCTIONS

4.2.4

STACK FULL/UNDERFLOW RESETS

Since the Top-of-Stack (TOS) is readable and writable,

the ability to push values onto the stack and pull values

off the stack, without disturbing normal program execu-

tion, is a desirable option. To push the current PC value

onto the stack, a PUSH instruction can be executed.

This will increment the stack pointer and load the cur-

rent PC value onto the stack. TOSU, TOSH and TOSL

can then be modified to place a return address on the

stack.

These RESETS are enabled by programming the

STVREN configuration bit. When the STVREN bit is

disabled, a full or underflow condition will set the appro-

priate STKFUL or STKUNF bit, but not cause a device

RESET. When the STVREN bit is enabled, a full or

underflow condition will set the appropriate STKFUL or

STKUNF bit and then cause a device RESET. The

STKFUL or STKUNF bits are only cleared by the user

software or a POR Reset.

The ability to pull the TOS value off of the stack and

replace it with the value that was previously pushed

onto the stack, without disturbing normal execution, is

achieved by using the POPinstruction. The POPinstruc-

tion discards the current TOS by decrementing the

stack pointer. The previous value pushed onto the

stack then becomes the TOS value.

 2002 Microchip Technology Inc.

Preliminary

DS30485A-page 35

PIC18FXX39

The PC addresses bytes in the program memory. To

prevent the PC from becoming misaligned with word

instructions, the LSB of PCL is fixed to a value of ‘0’.

The PC increments by 2 to address sequential

instructions in the program memory.

The CALL, RCALL, GOTO and program branch

instructions write to the program counter directly. For

these instructions, the contents of PCLATH and

PCLATU are not transferred to the program counter.

The contents of PCLATH and PCLATU will be trans-

ferred to the program counter by an operation that

writes PCL. Similarly, the upper two bytes of the pro-

gram counter will be transferred to PCLATH and

PCLATU by an operation that reads PCL. This is useful

for computed offsets to the PC (see Section 4.8.1).

4.3

Fast Register Stack

For PIC18FXX39 devices, a “fast interrupt return”

option is available for high priority interrupts. A single

level Fast Register Stack is provided for the STATUS,

WREG and BSR registers; it is not readable or writable.

When the processor vectors for an interrupt, the stack

is loaded with the current value of the corresponding

register. If the FAST RETURN instruction is used to

return from the interrupt, the values in the registers are

then loaded back into the working registers.

Note: The fast interrupt return for PIC18FXX39

devices is reserved for use by the ProMPT

kernel and the Timer2 match interrupt. It is

not available to the user for any other

interrupts or returns from subroutines.

4.5

Clocking Scheme/Instruction

Cycle

4.4

PCL, PCLATH and PCLATU

The program counter (PC) specifies the address of the

instruction to fetch for execution. The PC is 21-bits

wide. The low byte is called the PCL register. This reg-

ister is readable and writable. The high byte is called

the PCH register. This register contains the PC<15:8>

bits and is not directly readable or writable. Updates to

the PCH register may be performed through the

PCLATH register. The upper byte is called PCU. This

register contains the PC<20:16> bits and is not directly

readable or writable. Updates to the PCU register may

be performed through the PCLATU register.

The clock input (from OSC1) is internally divided by

four to generate four non-overlapping quadrature

clocks, namely Q1, Q2, Q3 and Q4. Internally, the pro-

gram counter (PC) is incremented every Q1, the

instruction is fetched from the program memory and

latched into the instruction register in Q4. The instruc-

tion is decoded and executed during the following Q1

through Q4. The clocks and instruction execution flow

are shown in Figure 4-3.

FIGURE 4-3:

CLOCK/INSTRUCTION CYCLE

Q2

Q3

Q4

Q2

Q3

Q4

Q2

Q3

Q4

Q1

OSC1

Q1

Q2

Q3

Internal

Phase

Clock

Q4

PC

PC+2

PC+4

PC

OSC2/CLKO

(RC mode)

Execute INST (PC-2)

Fetch INST (PC)

Execute INST (PC)

Fetch INST (PC+2)

Execute INST (PC+2)

Fetch INST (PC+4)

DS30485A-page 36

Preliminary

 2002 Microchip Technology Inc.

PIC18FXX39

A fetch cycle begins with the program counter (PC)

incrementing in Q1.

4.6

Instruction Flow/Pipelining

An “Instruction Cycle” consists of four Q cycles (Q1,

Q2, Q3 and Q4). The instruction fetch and execute are

pipelined such that fetch takes one instruction cycle,

while decode and execute takes another instruction

cycle. However, due to the pipelining, each instruction

effectively executes in one cycle. If an instruction

causes the program counter to change (e.g., GOTO),

then two cycles are required to complete the instruction

(Example 4-1).

In the execution cycle, the fetched instruction is latched

into the “Instruction Register” (IR) in cycle Q1. This

instruction is then decoded and executed during the

Q2, Q3, and Q4 cycles. Data memory is read during Q2

(operand read) and written during Q4 (destination

write).

EXAMPLE 4-1:

INSTRUCTION PIPELINE FLOW

TCY0

TCY1

TCY2

TCY3

TCY4

TCY5

1. MOVLW 55h

2. MOVWF PORTB

3. BRA SUB_1

Fetch 1

Execute 1

Fetch 2

Execute 2

Fetch 3

Execute 3

Fetch 4

4. BSF

PORTA, BIT3 (Forced NOP)

Flush (NOP)

5. Instruction @ address SUB_1

Fetch SUB_1 Execute SUB_1

All instructions are single cycle, except for any program branches. These take two cycles since the fetch instruction

is “flushed” from the pipeline while the new instruction is being fetched and then executed.

The CALLand GOTOinstructions have an absolute pro-

4.7

Instructions in Program Memory

gram memory address embedded into the instruction.

Since instructions are always stored on word bound-

aries, the data contained in the instruction is a word

address. The word address is written to PC<20:1>,

which accesses the desired byte address in program

memory. Instruction #2 in Figure 4-4 shows how the

instruction, ‘GOTO 000006h’, is encoded in the pro-

gram memory. Program branch instructions, which

encode a relative address offset, operate in the same

manner. The offset value stored in a branch instruction

represents the number of single word instructions that

the PC will be offset by. Section 21.0 provides further

details of the instruction set.

The program memory is addressed in bytes. Instruc-

tions are stored as two bytes or four bytes in program

memory. The Least Significant Byte of an instruction

word is always stored in a program memory location

with an even address (LSB = 0). Figure 4-4 shows an

example of how instruction words are stored in the pro-

gram memory. To maintain alignment with instruction

boundaries, the PC increments in steps of 2 and the

LSB will always read ‘0’ (see Section 4.4).

FIGURE 4-4:

INSTRUCTIONS IN PROGRAM MEMORY

Word Address

LSB = 1

LSB = 0

↓

Program Memory

000000h

000002h

000004h

000006h

000008h

00000Ah

00000Ch

00000Eh

000010h

000012h

000014h

Byte Locations →

Instruction 1:

Instruction 2:

0Fh

EFh

F0h

C1h

F4h

55h

03h

00h

23h

56h

MOVLW

GOTO

055h

000006h

Instruction 3:

MOVFF

123h, 456h

 2002 Microchip Technology Inc.

Preliminary

DS30485A-page 37

PIC18FXX39

second word of the instruction is executed by itself (first

word was skipped), it will execute as a NOP. This action

is necessary when the two-word instruction is preceded

by a conditional instruction that changes the PC. A pro-

gram example that demonstrates this concept is shown

in Example 4-2. Refer to Section 21.0 for further details

of the instruction set.

4.7.1

TWO-WORD INSTRUCTIONS

The PIC18FXX39 devices have four two-word instruc-

tions: MOVFF, CALL, GOTOand LFSR. The second

word of these instructions has the 4 MSBs set to ‘1’s

and is a special kind of NOPinstruction. The lower 12

bits of the second word contain data to be used by the

instruction. If the first word of the instruction is exe-

cuted, the data in the second word is accessed. If the

EXAMPLE 4-2:

TWO-WORD INSTRUCTIONS

CASE 1:

Object Code

Source Code

0110 0110 0000 0000 TSTFSZ

REG1

; is RAM location 0?

1100 0001 0010 0011

1111 0100 0101 0110

0010 0100 0000 0000

MOVFF

REG1, REG2 ; No, execute 2-word instruction

; 2nd operand holds address of REG2

ADDWF

REG3

; continue code

CASE 2:

Object Code

Source Code

TSTFSZ

0110 0110 0000 0000

1100 0001 0010 0011

1111 0100 0101 0110

0010 0100 0000 0000

REG1

; is RAM location 0?

MOVFF

REG1, REG2 ; Yes

; 2nd operand becomes NOP

; continue code

ADDWF

REG3

4.8.2

TABLE READS/TABLE WRITES

4.8

Lookup Tables

A better method of storing data in program memory

allows 2 bytes of data to be stored in each instruction

location.

Lookup table data may be stored 2 bytes per program

word by using table reads and writes. The table pointer

(TBLPTR) specifies the byte address and the table

latch (TABLAT) contains the data that is read from, or

written to program memory. Data is transferred to/from

program memory, one byte at a time.

Lookup tables are implemented two ways. These are:

• Computed GOTO

• Table Reads

4.8.1

COMPUTED GOTO

A computed GOTOis accomplished by adding an offset

to the program counter (ADDWF PCL).

A lookup table can be formed with an ADDWF PCL

instruction and a group of RETLW 0xnn instructions.

WREG is loaded with an offset into the table before

executing a call to that table. The first instruction of the

called routine is the ADDWF PCLinstruction. The next

instruction executed will be one of the RETLW 0xnn

instructions, that returns the value 0xnnto the calling

function.

A description of the Table Read/Table Write operation

is shown in Section 5.1.

The offset value (value in WREG) specifies the number

of bytes that the program counter should advance.

In this method, only one data byte may be stored in

each instruction location and room on the return

address stack is required.

Note: The ADDWF PCL instruction does not

update PCLATH and PCLATU. A read

operation on PCL must be performed to

update PCLATH and PCLATU.

DS30485A-page 38

Preliminary

 2002 Microchip Technology Inc.

PIC18FXX39

4.9.1

GENERAL PURPOSE REGISTER

FILE

4.9

Data Memory Organization

The data memory is implemented as static RAM. Each

register in the data memory has a 12-bit address,

allowing up to 4096 bytes of data memory. The data

memory map is divided into 16 banks that contain 256

bytes each. The lower 4 bits of the Bank Select Regis-

ter (BSR<3:0>) select which bank will be accessed.

The upper 4 bits for the BSR are not implemented.

The data memory contains Special Function Registers

(SFRs) and General Purpose Registers (GPRs). The

SFRs are used for control and status of the controller

and peripheral functions, while GPRs are used for data

storage and scratch pad operations in the user’s appli-

cation. The SFRs start at the last location of Bank 15

(FFFh) and extend downwards. Any remaining space

beyond the SFRs in the Bank may be implemented as

GPRs. GPRs start at the first location of Bank 0 and

grow upwards. Any read of an unimplemented location

will read as ‘0’s.

The organization of the data memory space for these

devices is shown in Figure 4-5 and Figure 4-6.

PIC18FX439 devices have 640 bytes of data RAM,

extending from Bank 0 to Bank 2 (000h through 27Fh).

The block of 128 bytes above this to the top of the bank

(280h to 2FFh) is used as data memory for the Motor

Control kernel, and is not available to the user. Reading

these locations will return random information that

reflects the kernel’s “scratch” data. Modifying the data

in these locations may disrupt the operation of the

ProMPT kernel.

PIC18FX539 devices have 1408 bytes of data RAM,

extending from Bank 0 to Bank 5 (000h through 57Fh).

As with the PIC18FX439 devices, the block of

128 bytes above this to the end of the bank (580h to

5FFh) is used by the Motor Control kernel.

The register file can be accessed either directly or indi-

rectly. Indirect addressing operates using a File Select

Register and corresponding Indirect File Operand. The

operation of indirect addressing is shown in

Section 4.12.

Enhanced MCU devices may have banked memory in

the GPR area. GPRs are not initialized by a Power-on

Reset and are unchanged on all other RESETS.

Data RAM is available for use as GPR registers by all

instructions. The top half of Bank 15 (F80h to FFFh)

contains SFRs. All other banks of data memory contain

GPR registers, starting with Bank 0.

4.9.2

SPECIAL FUNCTION REGISTERS

The Special Function Registers (SFRs) are registers

used by the CPU and Peripheral Modules for control-

ling the desired operation of the device. These regis-

ters are implemented as static RAM. A list of these

registers is given in Table 4-1 and Table 4-2.

The SFRs can be classified into two sets; those asso-

ciated with the “core” function and those related to the

peripheral functions. Those registers related to the

“core” are described in this section, while those related

to the operation of the peripheral features are

described in the section of that peripheral feature.

The SFRs are typically distributed among the

peripherals whose functions they control. The unused

SFR locations will be unimplemented and read as '0's.

See Table 4-1 for addresses for the SFRs.

Note: In this chapter and throughout this docu-

ment, certain SFR names and individual

bits are marked with an asterisk (*). This

denotes registers that are not implemented

in PIC18FXX39 devices, but whose names

are retained to maintain compatibility with

PIC18FXX2 devices. The designated bits

within these registers are reserved and

may be used by certain modules or the

Motor Control kernel. Users should not

write to these registers or alter these bit

values. Failure to do this may result in

erratic microcontroller operation.

The entire data memory may be accessed directly or

indirectly. Direct addressing may require the use of the

BSR register. Indirect addressing requires the use of a

File Select Register (FSRn) and a corresponding Indi-

rect File Operand (INDFn). Each FSR holds a 12-bit

address value that can be used to access any location

in the Data Memory map without banking.

The instruction set and architecture allow operations

across all banks. This may be accomplished by indirect

addressing, or by the use of the MOVFFinstruction. The

MOVFF instruction is a two-word/two-cycle instruction

that moves a value from one register to another.

To ensure that commonly used registers (SFRs and

select GPRs) can be accessed in a single cycle,

regardless of the current BSR values, an Access Bank

is implemented. A segment of Bank 0 and a segment of

Bank 15 comprise the Access RAM. Section 4.10

provides a detailed description of the Access RAM.

 2002 Microchip Technology Inc.

Preliminary

DS30485A-page 39

PIC18FXX39

FIGURE 4-5:

DATA MEMORY MAP FOR PIC18FX439

BSR<3:0>

Data Memory Map

000h

00h

Access RAM

GPR

= 0000

07Fh

Bank 0

080h

FFh

00h

0FFh

100h

= 0001

= 0010

= 0011

GPR

Bank 1

Bank 2

FFh

00h

1FFh

200h

GPR

27Fh

280h

ProMPT Memory

FFh

2FFh

300h

Access Bank

00h

•

Access RAM Low

7Fh

80h

Access RAM High

(SFRs)

Bank 3

to

Unused

FFh

Read ‘00h’

Bank 14

When a = 0,

the BSR is ignored and the

Access Bank is used.

The first 128 bytes are General

Purpose RAM (from Bank 0).

The second 128 bytes are

Special Function Registers

(from Bank 15).

= 1110

= 1111

EFFh

F00h

00h

FFh

Unused

SFR

F7Fh

Bank 15

F80h

FFFh

When a = 1,

the BSR is used to specify the

RAM location that the

instruction uses.

DS30485A-page 40

Preliminary

 2002 Microchip Technology Inc.

PIC18FXX39

FIGURE 4-6:

BSR<3:0>

DATA MEMORY MAP FOR PIC18FX539

Data Memory Map

000h

00h

Access RAM

GPR

= 0000

07Fh

Bank 0

080h

FFh

00h

0FFh

100h

= 0001

= 0010

= 0011

= 0100

= 0101

= 0110

GPR

Bank 1

Bank 2

Bank 3

FFh

00h

1FFh

200h

FFh

00h

2FFh

300h

GPR

FFh

3FFh

400h

Bank 4

Bank 5

GPR

Access Bank

4FFh

500h

00h

Access RAM Low

7Fh

00h

FFh

GPR

80h

FFh

Access RAM High

(SFRs)

ProMPT Memory

5FFh

600h

•

When a = 0,

the BSR is ignored and the

Access Bank is used.

Bank 6

to

Unused

Read ‘00h’

Bank 14

The first 128 bytes are General

Purpose RAM (from Bank 0).

The second 128 bytes are

Special Function Registers

(from Bank 15).

= 1110

= 1111

EFFh

F00h

00h

FFh

Unused

SFR

F7Fh

Bank 15

F80h

FFFh

When a = 1,

the BSR is used to specify the

RAM location that the

instruction uses.

 2002 Microchip Technology Inc.

Preliminary

DS30485A-page 41

PIC18FXX39

TABLE 4-1:

SPECIAL FUNCTION REGISTER MAP

Address

FFFh

FFEh

FFDh

FFCh

FFBh

FFAh

FF9h

FF8h

FF7h

FF6h

FF5h

FF4h

FF3h

FF2h

FF1h

FF0h

FEFh

Name

TOSU

TOSH

Address

FDFh

Name

INDF2⁽³⁾

Address

FBFh

FBEh

FBDh

FBCh

FBBh

FBAh

FB9h

FB8h

FB7h

FB6h

FB5h

FB4h

FB3h

FB2h

FB1h

FB0h

FAFh

FAEh

FADh

FACh

FABh

FAAh

FA9h

FA8h

FA7h

FA6h

FA5h

FA4h

FA3h

FA2h

FA1h

FA0h

Name

CCPR1H

CCPR1L^*

CCP1CON^*

CCPR2H

CCPR2L^*

CCP2CON^*

—

Address

F9Fh

F9Eh

F9Dh

F9Ch

F9Bh

F9Ah

F99h

F98h

F97h

F96h

F95h

F94h

F93h

F92h

F91h

F90h

F8Fh

F8Eh

F8Dh

F8Ch

F8Bh

F8Ah

F89h

F88h

F87h

F86h

F85h

F84h

F83h

F82h

F81h

F80h

Name

IPR1

PIR1

PIE1

—

FDEh

POSTINC2⁽³⁾

TOSL

FDDh POSTDEC2⁽³⁾

STKPTR

PCLATU

PCLATH

PCL

FDCh

FDBh

FDAh

FD9h

FD8h

FD7h

FD6h

FD5h

FD4h

FD3h

FD2h

FD1h

FD0h

FCFh

FCEh

FCDh

FCCh

FCBh

FCAh

FC9h

FC8h

FC7h

FC6h

FC5h

FC4h

FC3h

FC2h

FC1h

FC0h

PREINC2⁽³⁾

PLUSW2⁽³⁾

FSR2H

FSR2L

TBLPTRU

TBLPTRH

TBLPTRL

TABLAT

PRODH

PRODL

INTCON

INTCON2

INTCON3

INDF0⁽³⁾

STATUS

TMR0H

TMR0L

T0CON

—

TRISE⁽²⁾

TRISD⁽²⁾

TRISC⁽⁴⁾

TRISB

TRISA

—

OSCCON^*

LVDCON

WDTCON

RCON

TMR1H

TMR1L

TMR3H

TMR3L

T3CON

—

SPBRG

RCREG

TXREG

TXSTA

RCSTA

—

EEADR

EEDATA

EECON2

EECON1

—

FEEh POSTINC0⁽³⁾

FEDh POSTDEC0⁽³⁾

T1CON

LATE⁽²⁾

LATD⁽²⁾

LATC⁽⁴⁾

LATB

LATA

—

FECh

FEBh

FEAh

FE9h

FE8h

FE7h

PREINC0⁽³⁾

PLUSW0⁽³⁾

FSR0H

TMR2^*

PR2^*

T2CON^*

SSPBUF

SSPADD

SSPSTAT

SSPCON1

SSPCON2

ADRESH

ADRESL

ADCON0

ADCON1

—

FSR0L

WREG

INDF1⁽³⁾

—

FE6h POSTINC1⁽³⁾

FE5h POSTDEC1⁽³⁾

FE4h

FE3h

FE2h

FE1h

FE0h

PREINC1⁽³⁾

PLUSW1⁽³⁾

FSR1H

FSR1L

BSR

—

IPR2

PIR2

PORTE⁽²⁾

PORTD⁽²⁾

PORTC⁽⁴⁾

PORTB

PORTA

PIE2

*

These registers are retained to maintain compatibility with PIC18FXX2 devices; however, one or more bits

are reserved in PIC18FXX39 devices. Users should not alter the values of these bits.

Note 1: Unimplemented registers are read as ‘0’.

2: This register is not available on PIC18F2X39 devices.

3: This is not a physical register.

4: Bits 1 and 2 are reserved; users should not alter their values.

DS30485A-page 42

Preliminary

 2002 Microchip Technology Inc.

PIC18FXX39

TABLE 4-2:

REGISTER FILE SUMMARY

Value on

Details

File Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

POR, BOR on page:

TOSU

TOSH

TOSL

STKPTR

PCLATU

PCLATH

PCL

—

Top-of-Stack Upper Byte (TOS<20:16>)

---0 0000 26, 34

0000 0000 26, 34

00-0 0000 26, 35

---0 0000 26, 36

0000 0000 26, 36

Top-of-Stack High Byte (TOS<15:8>)

Top-of-Stack Low Byte (TOS<7:0>)

STKFUL

—

Holding Register for PC<15:8>

PC Low Byte (PC<7:0>)

STKUNF

—

Return Stack Pointer

Holding Register for PC<20:16>

(2)

TBLPTRU

TBLPTRH

TBLPTRL

TABLAT

PRODH

PRODL

INTCON

INTCON2

INTCON3

INDF0

—

bit21

Program Memory Table Pointer Upper Byte (TBLPTR<20:16>) --00 0000 26, 54

Program Memory Table Pointer High Byte (TBLPTR<15:8>)

Program Memory Table Pointer Low Byte (TBLPTR<7:0>)

Program Memory Table Latch

0000 0000 26, 54

xxxx xxxx 26, 67

0000 000x 26, 71

1111 -1-1 26, 72

11-0 0-00 26, 73

Product Register High Byte

Product Register Low Byte

GIE/GIEH PEIE/GIEL

RBPU

TMR0IE

INTEDG0 INTEDG1 INTEDG2

INT1IP INT2IE

INT0IE

RBIE

—

INT1IE

TMR0IF

TMR0IP

—

INT0IF

—

INT2IF

RBIF

RBIP

INT1IF

INT2IP

—

Uses contents of FSR0 to address data memory - value of FSR0 not changed (not a physical register)

Uses contents of FSR0 to address data memory - value of FSR0 post-incremented (not a physical register)

POSTDEC0 Uses contents of FSR0 to address data memory - value of FSR0 post-decremented (not a physical register)

n/a

26, 47

POSTINC0

PREINC0

PLUSW0

Uses contents of FSR0 to address data memory - value of FSR0 pre-incremented (not a physical register)

Uses contents of FSR0 to address data memory - value of FSR0 (not a physical register).

Offset by value in WREG.

FSR0H

FSR0L

—

Indirect Data Memory Address Pointer 0 High Byte ---- 0000 26, 47

xxxx xxxx 26, 47

Indirect Data Memory Address Pointer 0 Low Byte

WREG

Working Register

xxxx xxxx

26

INDF1

POSTINC1

Uses contents of FSR1 to address data memory - value of FSR1 not changed (not a physical register)

Uses contents of FSR1 to address data memory - value of FSR1 post-incremented (not a physical register)

n/a

26, 47

POSTDEC1 Uses contents of FSR1 to address data memory - value of FSR1 post-decremented (not a physical register)

PREINC1

PLUSW1

Uses contents of FSR1 to address data memory - value of FSR1 pre-incremented (not a physical register)

Uses contents of FSR1 to address data memory - value of FSR1 (not a physical register).

Offset by value in WREG.

FSR1H

FSR1L

BSR

—

Indirect Data Memory Address Pointer 1 High Byte ---- 0000 27, 47

xxxx xxxx 27, 47

Indirect Data Memory Address Pointer 1 Low Byte

—

Bank Select Register

---- 0000 27, 46

INDF2

POSTINC2

Uses contents of FSR2 to address data memory - value of FSR2 not changed (not a physical register)

Uses contents of FSR2 to address data memory - value of FSR2 post-incremented (not a physical register)

n/a

27, 47

POSTDEC2 Uses contents of FSR2 to address data memory - value of FSR2 post-decremented (not a physical register)

PREINC2

PLUSW2

Uses contents of FSR2 to address data memory - value of FSR2 pre-incremented (not a physical register)

Uses contents of FSR2 to address data memory - value of FSR2 (not a physical register).

Offset by value in WREG.

FSR2H

FSR2L

STATUS

—

Indirect Data Memory Address Pointer 2 High Byte ---- 0000 27, 47

xxxx xxxx 27, 47

Indirect Data Memory Address Pointer 2 Low Byte

—

N

OV

Z

DC

C

---x xxxx 27, 49

Legend: x= unknown, u= unchanged, - = unimplemented, q= value depends on condition

*

These registers (or individual bits) are retained to maintain compatibility with PIC18FXX2 devices; however, the indicated bits are

reserved in PIC18FXX39 devices. Users should not alter the values of these bits. See Section 4.9.2 for details.

Note 1: RA6 and associated bits are configured as port pins in RCIO and ECIO Oscillator mode only and read '0' in all other Oscillator modes.

2: Bit 21 of the TBLPTRU allows access to the device configuration bits.

3: These registers and bits are reserved on the PIC18F2X39 devices; always maintain these clear.

 2002 Microchip Technology Inc.

Preliminary

DS30485A-page 43

PIC18FXX39

TABLE 4-2:

REGISTER FILE SUMMARY (CONTINUED)

Value on

Details

File Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

POR, BOR on page:

TMR0H

TMR0L

T0CON

Timer0 Register High Byte

Timer0 Register Low Byte

0000 0000 27, 101

xxxx xxxx 27, 101

1111 1111 27, 99

TMR0ON

T08BIT

—

T0CS

—

IRVST

—

T0SE

—

LVDEN

—

PSA

—

LVDL3

—

T0PS2

—

LVDL2

—

T0PS1

—

LVDL1

—

T0PS0

*

OSCCON

—

---- ---0

27

LVDCON

WDTCON

RCON

TMR1H

TMR1L

LVDL0

--00 0101 27, 191

—

SWDTE ---- ---0 27, 203

IPEN

—

RI

TO

PD

POR

BOR

0--1 11qq 25, 50, 80

xxxx xxxx 27, 103

Timer1 Register High Byte

Timer1 Register Low Byte

—

*

T1CON

RD16

—

*

T1CKPS1 T1CKPS0

T1SYNC

TMR1CS TMR1ON 0-00 0000 27, 103

*

TMR2

*

0000 0000

1111 1111

-000 0000

27

*

PR2

*

T2CON

*

SSPBUF

SSPADD

SSPSTAT

SSPCON1

SSPCON2

ADRESH

ADRESL

ADCON0

ADCON1

CCPR1H

SSP Receive Buffer/Transmit Register

2

xxxx xxxx 27, 125

0000 0000 27, 134

0000 0000 27, 126

2

SSP Address Register in I C Slave mode. SSP Baud Rate Reload Register in I C Master mode.

SMP

WCOL

GCEN

CKE

SSPOV

ACKSTAT

D/A

SSPEN

ACKDT

P

CKP

ACKEN

S

R/W

SSPM2

PEN

UA

SSPM1

RSEN

BF

SSPM3

RCEN

SSPM0 0000 0000 27, 127

SEN

0000 0000 27, 137

xxxx xxxx 187,188

0000 00-0 28, 181

A/D Result Register High Byte

A/D Result Register Low Byte

ADCS1

ADFM

ADCS0

ADCS2

CHS2

—

CHS1

—

CHS0

PCFG3

GO/DONE

PCFG2

—

PCFG1

ADON

PCFG0 00-- 0000 28, 182

xxxx xxxx 28, 124

PWM Register1 High Byte (Read only)

*

CCPR1L

CCP1CON

*

—

*

—

*

xxxx xxxx 28, 124

--00 0000 28, 124

xxxx xxxx 28, 124

--00 0000 28, 124

xxxx xxxx 28, 109

*

CCPR2H

PWM Register2 High Byte (Read only)

*

CCPR2L

*

—

*

—

*

CCP2CON

TMR3H

TMR3L

T3CON

SPBRG

RCREG

Timer3 Register High Byte

Timer3 Register Low Byte

—

RD16

T3CKPS1 T3CKPS0

T3SYNC

TMR3CS TMR3ON 0000 0000 28, 109

0000 0000 28, 168

USART1 Baud Rate Generator

USART1 Receive Register

0000 0000 28, 175,

178

TXREG

USART1 Transmit Register

0000 0000 28, 173,

176

TXSTA

RCSTA

EEADR

CSRC

SPEN

TX9

RX9

TXEN

SREN

SYNC

CREN

—

ADDEN

BRGH

FERR

TRMT

OERR

TX9D

RX9D

0000 -010 28, 166

0000 000x 28, 167

Data EEPROM Address Register

0000 0000 28, 61,

65

EEDATA

EECON2

Data EEPROM Data Register

0000 0000 28, 65

Data EEPROM Control Register 2 (not a physical register)

EEPGD CFGS FREE WRERR

---- ---- 28, 61,

65

EECON1

—

WREN

WR

RD

xx-0 x000 28, 62

Legend: x= unknown, u= unchanged, - = unimplemented, q= value depends on condition

*

These registers (or individual bits) are retained to maintain compatibility with PIC18FXX2 devices; however, the indicated bits are

reserved in PIC18FXX39 devices. Users should not alter the values of these bits. See Section 4.9.2 for details.

Note 1: RA6 and associated bits are configured as port pins in RCIO and ECIO Oscillator mode only and read '0' in all other Oscillator modes.

2: Bit 21 of the TBLPTRU allows access to the device configuration bits.

3: These registers and bits are reserved on the PIC18F2X39 devices; always maintain these clear.

DS30485A-page 44

Preliminary

 2002 Microchip Technology Inc.

PIC18FXX39

TABLE 4-2:

REGISTER FILE SUMMARY (CONTINUED)

Value on

Details

File Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

POR, BOR on page:

IPR2

PIR2

PIE2

IPR1

PIR1

PIE1

—

EEIP

EEIF

EEIE

BCLIP

BCLIF

BCLIE

SSPIP

SSPIF

SSPIE

—

LVDIP

LVDIF

LVDIE

—

TMR3IP

TMR3IF

TMR3IE

TMR2IP

TMR2IF

TMR2IE

—

---1 1111 29, 79

---0 0000 29, 75

---0 0000 29, 77

(3)

PSPIP

PSPIF

PSPIE

IBF

ADIP

ADIF

ADIE

OBF

RCIP

RCIF

RCIE

IBOV

TXIP

TMR1IP 1111 1111 29, 78

TMR1IF 0000 0000 29, 74

TMR1IE 0000 0000 29, 76

(3)

—

TXIF

—

TXIE

(3)

TRISE

PSPMODE

Data Direction bits for PORTE

0000 -111 29, 94

1111 1111 29, 92

(3)

TRISD

Data Direction Control Register for PORTD

TRISC7 TRISC6 TRISC5 TRISC4

Data Direction Control Register for PORTB

TRISC

TRISB

TRISA

TRISC3

*

TRISC0 1111 1111 29, 89

1111 1111 29, 86

(1)

—

TRISA6

—

Data Direction Control Register for PORTA

-111 1111 29, 83

(3)

LATE

—

Read PORTE Data Latch,

Write PORTE Data Latch

---- -xxx 29, 95

(3)

LATD

Read PORTD Data Latch, Write PORTD Data Latch

LATC7 LATC6 LATC5 LATC4

Read PORTB Data Latch, Write PORTB Data Latch

xxxx xxxx 29, 91

LATC

LATB

LATA

LATC3

*

LATC0

RC0

xxxx xxxx 29, 89

xxxx xxxx 29, 86

-xxx xxxx 29, 83

---- -000 29, 95

xxxx xxxx 29, 91

xxxx xxxx 29, 89

xxxx xxxx 29, 86

-x0x 0000 29, 83

(1)

—

LATA6

Read PORTA Data Latch, Write PORTA Data Latch

(3)

PORTE

Read PORTE pins, Write PORTE Data Latch

Read PORTD pins, Write PORTD Data Latch

(3)

PORTD

PORTC

PORTB

PORTA

RC7

RC6

RC5

RC4

RC3

*

Read PORTB pins, Write PORTB Data Latch

(1)

—

RA6

Read PORTA pins, Write PORTA Data Latch

Legend: x= unknown, u= unchanged, - = unimplemented, q= value depends on condition

*

These registers (or individual bits) are retained to maintain compatibility with PIC18FXX2 devices; however, the indicated bits are

reserved in PIC18FXX39 devices. Users should not alter the values of these bits. See Section 4.9.2 for details.

Note 1: RA6 and associated bits are configured as port pins in RCIO and ECIO Oscillator mode only and read '0' in all other Oscillator modes.

2: Bit 21 of the TBLPTRU allows access to the device configuration bits.

3: These registers and bits are reserved on the PIC18F2X39 devices; always maintain these clear.

 2002 Microchip Technology Inc.

Preliminary

DS30485A-page 45

PIC18FXX39

4.10

Access Bank

4.11 Bank Select Register (BSR)

The Access Bank is an architectural enhancement

which is very useful for C compiler code optimization.

The techniques used by the C compiler may also be

useful for programs written in assembly.

This data memory region can be used for:

• Intermediate computational values

• Local variables of subroutines

• Faster context saving/switching of variables

• Common variables

• Faster evaluation/control of SFRs (no banking)

The Access Bank is comprised of the upper 128 bytes

in Bank 15 (SFRs) and the lower 128 bytes in Bank 0.

These two sections will be referred to as Access RAM

High and Access RAM Low, respectively. Figure 4-5

and Figure 4-6 indicate the Access RAM areas.

A bit in the instruction word specifies if the operation is

to occur in the bank specified by the BSR register, or in

the Access Bank. This bit is denoted by the ‘a’ bit (for

access bit).

When forced in the Access Bank (a = 0), the last

address in Access RAM Low is followed by the first

address in Access RAM High. Access RAM High maps

the Special Function registers, so that these registers

can be accessed without any software overhead. This is

useful for testing status flags and modifying control bits.

The need for a large general purpose memory space

dictates a RAM banking scheme. The data memory is

partitioned into sixteen banks. When using direct

addressing, the BSR should be configured for the

desired bank.

BSR<3:0> holds the upper 4 bits of the 12-bit RAM

address. The BSR<7:4> bits will always read ‘0’s, and

writes will have no effect.

A

MOVLB instruction has been provided in the

instruction set to assist in selecting banks.

If the currently selected bank is not implemented, any

read will return all ‘0’s and all writes are ignored. The

STATUS register bits will be set/cleared as appropriate

for the instruction performed.

Each Bank extends up to FFh (256 bytes). All data

memory is implemented as static RAM.

A MOVFFinstruction ignores the BSR, since the 12-bit

addresses are embedded into the instruction word.

Section 4.12 provides a description of indirect address-

ing, which allows linear addressing of the entire RAM

space.

FIGURE 4-7:

DIRECT ADDRESSING

Direct Addressing

(3)

From Opcode

BSR<3:0>

7

0

(2)

(3)

Bank Select

Location Select

00h

01h

100h

0Eh

E00h

0Fh

F00h

000h

Data

Memory⁽¹⁾

0FFh

1FFh

EFFh

FFFh

Bank 0

Bank 1

Bank 14 Bank 15

Note 1: For register file map detail, see Table 4-1.

2: The access bit of the instruction can be used to force an override of the selected bank (BSR<3:0>) to the

registers of the Access Bank.

3: The MOVFFinstruction embeds the entire 12-bit address in the instruction.

DS30485A-page 46

Preliminary

 2002 Microchip Technology Inc.

PIC18FXX39

the data from the address pointed to by

FSR1H:FSR1L. INDFn can be used in code anywhere

an operand can be used.

If INDF0, INDF1 or INDF2 are read indirectly via an

FSR, all '0's are read (zero bit is set). Similarly, if

INDF0, INDF1 or INDF2 are written to indirectly, the

operation will be equivalent to a NOPinstruction and the

STATUS bits are not affected.

4.12 Indirect Addressing, INDF and

FSR Registers

Indirect addressing is a mode of addressing data mem-

ory, where the data memory address in the instruction

is not fixed. An FSR register is used as a pointer to the

data memory location that is to be read or written. Since

this pointer is in RAM, the contents can be modified by

the program. This can be useful for data tables in the

data memory and for software stacks. Figure 4-8

shows the operation of indirect addressing. This shows

the moving of the value to the data memory address

specified by the value of the FSR register.

Indirect addressing is possible by using one of the

INDF registers. Any instruction using the INDF register

actually accesses the register pointed to by the File

Select Register, FSR. Reading the INDF register itself,

indirectly (FSR = 0), will read 00h. Writing to the INDF

register indirectly, results in a NOPoperation. The FSR

register contains a 12-bit address, which is shown in

Figure 4-9.

The INDFn register is not a physical register. Address-

ing INDFn actually addresses the register whose

address is contained in the FSRn register (FSRn is a

pointer). This is indirect addressing.

Example 4-3 shows a simple use of indirect addressing

to clear the RAM in Bank 1 (locations 100h-1FFh) in a

minimum number of instructions.

4.12.1

INDIRECT ADDRESSING

OPERATION

Each FSR register has an INDF register associated

with it, plus four additional register addresses. Perform-

ing an operation on one of these five registers deter-

mines how the FSR will be modified during indirect

addressing.

When data access is done to one of the five INDFn

locations, the address selected will configure the FSRn

register to:

• Do nothing to FSRn after an indirect access (no

change) - INDFn

• Auto-decrement FSRn after an indirect access

(post-decrement) - POSTDECn

• Auto-increment FSRn after an indirect access

(post-increment) - POSTINCn

• Auto-increment FSRn before an indirect access

(pre-increment) - PREINCn

• Use the value in the WREG register as an offset

to FSRn. Do not modify the value of the WREG or

the FSRn register after an indirect access (no

change) - PLUSWn

When using the auto-increment or auto-decrement fea-

tures, the effect on the FSR is not reflected in the

STATUS register. For example, if the indirect address

causes the FSR to equal '0', the Z bit will not be set.

EXAMPLE 4-3:

HOW TO CLEAR RAM

(BANK 1) USING

INDIRECT ADDRESSING

LFSR FSR0 ,0x100

CLRF POSTINC0

;

; register and

; inc pointer

; All done with

; Bank1?

BTFSS FSR0H, 1

GOTO NEXT

Incrementing or decrementing an FSR affects all 12

bits. That is, when FSRnL overflows from an increment,

FSRnH will be incremented automatically.

; NO, clear next

; YES, continue

CONTINUE

Adding these features allows the FSRn to be used as a

stack pointer, in addition to its uses for table operations

in data memory.

Each FSR has an address associated with it that per-

forms an indexed indirect access. When a data access

to this INDFn location (PLUSWn) occurs, the FSRn is

configured to add the signed value in the WREG regis-

ter and the value in FSR to form the address, before an

indirect access. The FSR value is not changed.

There are three indirect addressing registers. To

address the entire data memory space (4096 bytes),

these registers are 12-bits wide. To store the 12 bits of

addressing information, two 8-bit registers are

required. These indirect addressing registers are:

1. FSR0: composed of FSR0H:FSR0L

2. FSR1: composed of FSR1H:FSR1L

3. FSR2: composed of FSR2H:FSR2L

If an FSR register contains a value that points to one of

the INDFn, an indirect read will read 00h (zero bit is

set), while an indirect write will be equivalent to a NOP

(STATUS bits are not affected).

If an indirect addressing operation is done where the

target address is an FSRnH or FSRnL register, the

write operation will dominate over the pre- or

post-increment/decrement functions.

In addition, there are registers INDF0, INDF1 and

INDF2, which are not physically implemented. Reading

or writing to these registers activates indirect address-

ing, with the value in the corresponding FSR register

being the address of the data. If an instruction writes a

value to INDF0, the value will be written to the address

pointed to by FSR0H:FSR0L. A read from INDF1 reads

 2002 Microchip Technology Inc.

Preliminary

DS30485A-page 47

PIC18FXX39

FIGURE 4-8:

INDIRECT ADDRESSING OPERATION

0h

RAM

Instruction

Executed

Opcode

Address

12

FFFh

File Address = Access of an Indirect Addressing Register

BSR<3:0>

4

12

Instruction

Fetched

8

Opcode

File

FSR

FIGURE 4-9:

INDIRECT ADDRESSING

Indirect Addressing

11

FSR Register

0

Location Select

0000h

Data

Memory⁽¹⁾

0FFFh

Note 1: For register file map detail, see Table 4-1.

DS30485A-page 48

Preliminary

 2002 Microchip Technology Inc.

PIC18FXX39

For example, CLRF STATUSwill clear the upper three

bits and set the Z bit. This leaves the STATUS register

as 000u u1uu(where u= unchanged).

It is recommended, therefore, that only BCF, BSF,

SWAPF, MOVFF and MOVWF instructions are used to

alter the STATUS register, because these instructions

do not affect the Z, C, DC, OV, or N bits from the

STATUS register. For other instructions not affecting

any status bits, see Table 21-2.

4.13 STATUS Register

The STATUS register, shown in Register 4-2, contains

the arithmetic status of the ALU. The STATUS register

can be the destination for any instruction, as with any

other register. If the STATUS register is the destination

for an instruction that affects the Z, DC, C, OV, or N bits,

then the write to these five bits is disabled. These bits

are set or cleared according to the device logic. There-

fore, the result of an instruction with the STATUS

register as destination may be different than intended.

Note: The C and DC bits operate as a borrow and

digit borrow bit respectively, in subtraction.

REGISTER 4-2:

STATUS REGISTER

U-0

—

U-0

—

U-0

—

R/W-x

N

R/W-x

OV

R/W-x

Z

R/W-x

DC

R/W-x

C

bit 7

bit 0

bit 7-5

bit 4

Unimplemented: Read as '0'

N: Negative bit

This bit is used for signed arithmetic (2’s complement). It indicates whether the result was

negative (ALU MSB = 1).

1= Result was negative

0= Result was positive

bit 3

OV: Overflow bit

This bit is used for signed arithmetic (2’s complement). It indicates an overflow of the

7-bit magnitude, which causes the sign bit (bit 7) to change state.

1= Overflow occurred for signed arithmetic (in this arithmetic operation)

0= No overflow occurred

bit 2

bit 1

Z: Zero bit

1= The result of an arithmetic or logic operation is zero

0= The result of an arithmetic or logic operation is not zero

DC: Digit carry/borrow bit

For ADDWF, ADDLW, SUBLW, and SUBWFinstructions

1= A carry-out from the 4th low order bit of the result occurred

0= No carry-out from the 4th low order bit of the result

Note:

For borrow, the polarity is reversed. A subtraction is executed by adding the two’s

complement of the second operand. For rotate (RRF, RLF) instructions, this bit is

loaded with either the bit 4 or bit 3 of the source register.

bit 0

C: Carry/borrow bit

For ADDWF, ADDLW, SUBLW, and SUBWFinstructions

1= A carry-out from the Most Significant bit of the result occurred

0= No carry-out from the Most Significant bit of the result occurred

Note: For borrow, the polarity is reversed. A subtraction is executed by adding the two’s

complement of the second operand. For rotate (RRF, RLF) instructions, this bit is

loaded with either the high or low order bit of the source register.

Legend:

R = Readable bit

- n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

 2002 Microchip Technology Inc.

Preliminary

DS30485A-page 49

PIC18FXX39

4.14 RCON Register

Note 1: If the BOREN configuration bit is set

(Brown-out Reset enabled), the BOR bit is

‘1’ on a Power-on Reset. After a Brown-

out Reset has occurred, the BOR bit will

be cleared, and must be set by firmware to

indicate the occurrence of the next

Brown-out Reset.

The Reset Control (RCON) register contains flag bits

that allow differentiation between the sources of a

device RESET. These flags include the TO, PD, POR,

BOR and RI bits. This register is readable and writable.

For PIC18FXX39 devices, the IPEN bit must always be

set (= 1) for the ProMPT kernel to function correctly.

Refer to Section 8.0 (page 69) for a more detailed

discussion.

2: It is recommended that the POR bit be set

after

a Power-on Reset has been

detected, so that subsequent Power-on

Resets may be detected.

REGISTER 4-3:

RCON REGISTER

R/W-0

IPEN

U-0

—

U-0

—

R/W-1

RI

R-1

TO

R-1

PD

R/W-0

POR

R/W-0

BOR

bit 7

bit 0

bit 7

IPEN: Interrupt Priority Enable bit

Always maintain this bit set for proper operation of ProMPT kernel.

Unimplemented: Read as '0'

bit 6-5

bit 4

RI: RESETInstruction Flag bit

1= The RESETinstruction was not executed

0= The RESETinstruction was executed causing a device RESET

(must be set in software after a Brown-out Reset occurs)

bit 3

bit 2

bit 1

TO: Watchdog Time-out Flag bit

1= After power-up, CLRWDTinstruction, or SLEEPinstruction

0= A WDT time-out occurred

PD: Power-down Detection Flag bit

1= After power-up or by the CLRWDTinstruction

0= By execution of the SLEEPinstruction

POR: Power-on Reset Status bit

1= A Power-on Reset has not occurred

0= A Power-on Reset occurred

(must be set in software after a Power-on Reset occurs)

bit 0

BOR: Brown-out Reset Status bit

1= A Brown-out Reset has not occurred

0= A Brown-out Reset occurred

(must be set in software after a Brown-out Reset occurs)

Legend:

R = Readable bit

- n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

DS30485A-page 50

Preliminary

 2002 Microchip Technology Inc.

PIC18FXX39

5.1

Table Reads and Table Writes

5.0

FLASH PROGRAM MEMORY

In order to read and write program memory, there are

two operations that allow the processor to move bytes

between the program memory space and the data

RAM:

• Table Read (TBLRD)

• Table Write (TBLWT)

The program memory space is 16-bits wide, while the

data RAM space is 8-bits wide. Table Reads and Table

Writes move data between these two memory spaces

through an 8-bit register (TABLAT).

Table Read operations retrieve data from program

memory and places it into the data RAM space.

Figure 5-1 shows the operation of a Table Read with

program memory and data RAM.

Table Write operations store data from the data mem-

ory space into holding registers in program memory.

The procedure to write the contents of the holding reg-

isters into program memory is detailed in Section 5.5,

“Writing to FLASH Program Memory”. Figure 5-2

shows the operation of a Table Write with program

memory and data RAM.

The FLASH Program Memory is readable, writable,

and erasable during normal operation over the entire

VDD range.

A read from program memory is executed on one byte

at a time. A write to program memory is executed on

blocks of 8 bytes at a time. Program memory is erased

in blocks of 64 bytes at a time. A bulk erase operation

may not be issued from user code.

Writing or erasing program memory will cease instruc-

tion fetches until the operation is complete. The pro-

gram memory cannot be accessed during the write or

erase, therefore, code cannot execute. An internal pro-

gramming timer terminates program memory writes

and erases.

A value written to program memory does not need to be

a valid instruction. Executing a program memory

location that forms an invalid instruction results in a

NOP.

Table operations work with byte entities. A table block

containing data, rather than program instructions, is not

required to be word aligned. Therefore, a table block

can start and end at any byte address. If a Table Write

is being used to write executable code into program

memory, program instructions will need to be word

aligned.

FIGURE 5-1:

TABLE READ OPERATION

Instruction: TBLRD*

Program Memory

(1)

Table Pointer

Table Latch (8-bit)

TABLAT

TBLPTRU TBLPTRH TBLPTRL

Program Memory

(TBLPTR)

Note 1: Table Pointer points to a byte in program memory.

 2002 Microchip Technology Inc.

Preliminary

DS30485A-page 51

PIC18FXX39

FIGURE 5-2:

TABLE WRITE OPERATION

Instruction: TBLWT*

Program Memory

Holding Registers

(1)

Table Pointer

TBLPTRU TBLPTRH TBLPTRL

Table Latch (8-bit)

TABLAT

Program Memory

(TBLPTR)

Note 1: Table Pointer actually points to one of eight holding registers, the address of which is determined by

TBLPTRL<2:0>. The process for physically writing data to the Program Memory Array is discussed in

Section 5.5.

The FREE bit, when set, will allow a program memory

5.2

Control Registers

erase operation. When the FREE bit is set, the erase

Several control registers are used in conjunction with

the TBLRDand TBLWTinstructions. These include the:

operation is initiated on the next WR command. When

FREE is clear, only writes are enabled.

• EECON1 register

• EECON2 register

• TABLAT register

• TBLPTR registers

The WREN bit, when set, will allow a write operation.

On power-up, the WREN bit is clear. The WRERR bit is

set when a write operation is interrupted by a MCLR

Reset, or a WDT Time-out Reset, during normal oper-

ation. In these situations, the user can check the

WRERR bit and rewrite the location. It is necessary to

reload the data and address registers (EEDATA and

EEADR), due to RESETvalues of zero.

5.2.1

EECON1 AND EECON2 REGISTERS

EECON1 is the control register for memory accesses.

EECON2 is not a physical register. Reading EECON2

will read all '0's. The EECON2 register is used

exclusively in the memory write and erase sequences.

Control bit EEPGD determines if the access will be a

program or data EEPROM memory access. When

clear, any subsequent operations will operate on the

data EEPROM memory. When set, any subsequent

operations will operate on the program memory.

Control bit CFGS determines if the access will be to the

configuration registers or to program memory/data

EEPROM memory. When set, subsequent operations

will operate on configuration registers, regardless of

EEPGD (see Section 20.0, “Special Features of the

CPU”). When clear, memory selection access is

determined by EEPGD.

Control bit WR initiates write operations. This bit cannot

be cleared, only set, in software. It is cleared in hard-

ware at the completion of the write operation. The

inability to clear the WR bit in software prevents the

accidental or premature termination of

operation.

a write

Note: Interrupt flag bit, EEIF in the PIR2 register,

is set when the write is complete. It must

be cleared in software.

DS30485A-page 52

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 2002 Microchip Technology Inc.

PIC18FXX39

REGISTER 5-1:

EECON1 REGISTER (ADDRESS FA6h)

R/W-x

EEPGD

R/W-x

CFGS

U-0

—

R/W-0

FREE

R/W-x

WRERR

R/W-0

WREN

R/S-0

WR

R/S-0

RD

bit 7

bit 0

bit 7

bit 6

EEPGD: FLASH Program or Data EEPROM Memory Select bit

1= Access FLASH program memory

0= Access data EEPROM memory

CFGS: FLASH Program/Data EE or Configuration Select bit

1= Access configuration registers

0= Access FLASH program or data EEPROM memory

bit 5

bit 4

Unimplemented: Read as '0'

FREE: FLASH Row Erase Enable bit

1= Erase the program memory row addressed by TBLPTR on the next WR command

(cleared by completion of erase operation)

0= Perform write only

bit 3

WRERR: FLASH Program/Data EE Error Flag bit

1= A write operation is prematurely terminated

(any RESET during self-timed programming in normal operation)

0= The write operation completed

Note: When a WRERR occurs, the EEPGD and CFGS bits are not cleared. This allows

tracing of the error condition.

bit 2

bit 1

WREN: FLASH Program/Data EE Write Enable bit

1= Allows write cycles

0= Inhibits write to the EEPROM

WR: Write Control bit

1= Initiates a data EEPROM erase/write cycle or a program memory erase cycle or write cycle.

(The operation is self-timed and the bit is cleared by hardware once write is complete. The

WR bit can only be set (not cleared) in software.)

0= Write cycle to the EEPROM is complete

bit 0

RD: Read Control bit

1= Initiates an EEPROM read

(Read takes one cycle. RD is cleared in hardware. The RD bit can only be set (not cleared)

in software. RD bit cannot be set when EEPGD = 1.)

0= Does not initiate an EEPROM read

Legend:

R = Readable bit

- n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

 2002 Microchip Technology Inc.

Preliminary

DS30485A-page 53

PIC18FXX39

5.2.2

TABLAT - TABLE LATCH REGISTER

5.2.4

TABLE POINTER BOUNDARIES

The Table Latch (TABLAT) is an 8-bit register mapped

into the SFR space. The Table Latch is used to hold

8-bit data during data transfers between program

memory and data RAM.

TBLPTR is used in reads, writes, and erases of the

FLASH program memory.

When a TBLRD is executed, all 22 bits of the Table

Pointer determine which byte is read from program

memory into TABLAT.

When a TBLWTis executed, the three LSbs of the Table

Pointer (TBLPTR<2:0>) determine which of the eight

program memory holding registers is written to. When

the timed write to program memory (long write) begins,

the 19 MSbs of the Table Pointer, TBLPTR

(TBLPTR<21:3>), will determine which program mem-

ory block of 8 bytes is written to. For more detail, see

Section 5.5 (“Writing to FLASH Program Memory”).

When an erase of program memory is executed, the

16 MSbs of the Table Pointer (TBLPTR<21:6>) point to

the 64-byte block that will be erased. The Least

Significant bits (TBLPTR<5:0>) are ignored.

5.2.3

TBLPTR - TABLE POINTER

REGISTER

The Table Pointer (TBLPTR) addresses a byte within

the program memory. The TBLPTR is comprised of

three SFR registers: Table Pointer Upper Byte, Table

Pointer High Byte and Table Pointer Low Byte

(TBLPTRU:TBLPTRH:TBLPTRL). These three regis-

ters join to form a 22-bit wide pointer. The low order 21

bits allow the device to address up to 2 Mbytes of pro-

gram memory space. The 22nd bit allows access to the

Device ID, the User ID and the Configuration bits.

The table pointer, TBLPTR, is used by the TBLRDand

TBLWTinstructions. These instructions can update the

TBLPTR in one of four ways based on the table opera-

tion. These operations are shown in Table 5-1. These

operations on the TBLPTR only affect the low order

21 bits.

Figure 5-3 describes the relevant boundaries of

TBLPTR based on FLASH program memory

operations.

TABLE 5-1:

Example

TABLE POINTER OPERATIONS WITH TBLRD AND TBLWT INSTRUCTIONS

Operation on Table Pointer

TBLRD*

TBLWT*

TBLPTR is not modified

TBLRD*+

TBLWT*+

TBLPTR is incremented after the read/write

TBLPTR is decremented after the read/write

TBLPTR is incremented before the read/write

TBLRD*-

TBLWT*-

TBLRD+*

TBLWT+*

FIGURE 5-3:

TABLE POINTER BOUNDARIES BASED ON OPERATION

21

16 15

TBLPTRH

8

7

TBLPTRL

0

TBLPTRU

ERASE - TBLPTR<21:6>

WRITE - TBLPTR<21:3>

READ - TBLPTR<21:0>

DS30485A-page 54

Preliminary

 2002 Microchip Technology Inc.

PIC18FXX39

TBLPTR points to a byte address in program space.

Executing TBLRD places the byte pointed to into

TABLAT. In addition, TBLPTR can be modified

automatically for the next Table Read operation.

The internal program memory is typically organized by

words. The Least Significant bit of the address selects

between the high and low bytes of the word. Figure 5-4

shows the interface between the internal program

memory and the TABLAT.

5.3

Reading the FLASH Program

Memory

The TBLRDinstruction is used to retrieve data from pro-

gram memory and place into data RAM. Table Reads

from program memory are performed one byte at a

time.

FIGURE 5-4:

READS FROM FLASH PROGRAM MEMORY

Program Memory

(Even Byte Address)

(Odd Byte Address)

TBLPTR = xxxxx1

TBLPTR = xxxxx0

Instruction Register

(IR)

TABLAT

Read Register

FETCH

TBLRD

EXAMPLE 5-1:

READING A FLASH PROGRAM MEMORY WORD

MOVLW CODE_ADDR_UPPER

MOVWF TBLPTRU

; Load TBLPTR with the base

; address of the word

MOVLW CODE_ADDR_HIGH

MOVWF TBLPTRH

MOVLW CODE_ADDR_LOW

MOVWF TBLPTRL

READ_WORD

TBLRD*+

; read into TABLAT and increment

; get data

MOVF TABLAT, W

MOVWF WORD_EVEN

TBLRD*+

MOVF TABLAT, W

MOVWF WORD_ODD

; read into TABLAT and increment

; get data

 2002 Microchip Technology Inc.

Preliminary

DS30485A-page 55

PIC18FXX39

5.4.1

FLASH PROGRAM MEMORY

ERASE SEQUENCE

5.4

Erasing FLASH Program memory

The minimum erase block is 32 words or 64 bytes. Only

through the use of an external programmer, or through

ICSP control can larger blocks of program memory be

bulk erased. Word erase in the FLASH array is not

supported.

The sequence of events for erasing a block of internal

program memory location is:

1. Load table pointer with address of row being

erased.

When initiating an erase sequence from the micro-

controller itself, a block of 64 bytes of program memory

is erased. The Most Significant 16 bits of the

TBLPTR<21:6> point to the block being erased;

TBLPTR<5:0> are ignored.

2. Set EEPGD bit to point to program memory,

clear CFGS bit to access program memory, set

WREN bit to enable writes, and set FREE bit to

enable the erase.

3. Disable interrupts.

The EECON1 register commands the erase operation.

The EEPGD bit must be set to point to the FLASH pro-

gram memory. The WREN bit must be set to enable

write operations. The FREE bit is set to select an erase

operation.

For protection, the write initiate sequence for EECON2

must be used.

A long write is necessary for erasing the internal

FLASH. Instruction execution is halted while in a long

write cycle. The long write will be terminated by the

internal programming timer.

4. Write 55h to EECON2.

5. Write AAh to EECON2.

6. Set the WR bit. This will begin the row erase

cycle.

7. The CPU will stall for duration of the erase

(about 2 ms using internal timer).

8. Re-enable interrupts.

EXAMPLE 5-2:

ERASING A FLASH PROGRAM MEMORY ROW

MOVLW

MOVWF

MOVLW

MOVWF

MOVLW

MOVWF

CODE_ADDR_UPPER

; load TBLPTR with the base

TBLPTRU

CODE_ADDR_HIGH

TBLPTRH

CODE_ADDR_LOW

TBLPTRL

; address of the memory block

ERASE_ROW

BSF

BCF

BSF

EECON1,EEPGD

EECON1,CFGS

EECON1,WREN

EECON1,FREE

INTCON,GIE

55h

EECON2

AAh

EECON2

EECON1,WR

INTCON,GIE

; point to FLASH program memory

; access FLASH program memory

; enable write to memory

; enable Row Erase operation

; disable interrupts

BCF

MOVLW

MOVWF

MOVLW

MOVWF

BSF

Required

Sequence

; write 55h

; write AAh

; start erase (CPU stall)

; re-enable interrupts

BSF

DS30485A-page 56

Preliminary

 2002 Microchip Technology Inc.

PIC18FXX39

operations will essentially be short writes, because only

the holding registers are written. At the end of updating

8 registers, the EECON1 register must be written to, to

start the programming operation with a long write.

The long write is necessary for programming the inter-

nal FLASH. Instruction execution is halted while in a

long write cycle. The long write will be terminated by

the internal programming timer.

The EEPROM on-chip timer controls the write time.

The write/erase voltages are generated by an on-chip

charge pump rated to operate over the voltage range of

the device for byte or word operations.

5.5

Writing to FLASH Program

Memory

The minimum programming block is 4 words or 8 bytes.

Word or byte programming is not supported.

Table Writes are used internally to load the holding reg-

isters needed to program the FLASH memory. There

are 8 holding registers used by the Table Writes for

programming.

Since the Table Latch (TABLAT) is only a single byte,

the TBLWT instruction has to be executed 8 times for

each programming operation. All of the Table Write

FIGURE 5-5:

TABLE WRITES TO FLASH PROGRAM MEMORY

TABLAT

Write Register

8

TBLPTR = xxxxx0

TBLPTR = xxxxx2

TBLPTR = xxxxx7

Holding Register

TBLPTR = xxxxx1

Holding Register

Program Memory

10. Write AAh to EECON2.

11. Set the WR bit. This will begin the write cycle.

5.5.1

FLASH PROGRAM MEMORY WRITE

SEQUENCE

12. The CPU will stall for duration of the write (about

The sequence of events for programming an internal

program memory location should be:

1. Read 64 bytes into RAM.

2. Update data values in RAM as necessary.

3. Load Table Pointer with address being erased.

4. Do the row erase procedure.

2 ms using internal timer).

13. Re-enable interrupts.

14. Repeat steps 6-14 seven times, to write

64 bytes.

15. Verify the memory (Table Read).

This procedure will require about 18 ms to update one

row of 64 bytes of memory. An example of the required

code is given in Example 5-3.

5. Load Table Pointer with address of first byte

being written.

6. Write the first 8 bytes into the holding registers

Note: Before setting the WR bit, the table pointer

address needs to be within the intended

address range of the 8 bytes in the holding

registers.

with auto-increment (TBLWT*+or TBLWT+*).

7. Set EEPGD bit to point to program memory,

clear the CFGS bit to access program memory,

and set WREN to enable byte writes.

8. Disable interrupts.

9. Write 55h to EECON2.

 2002 Microchip Technology Inc.

Preliminary

DS30485A-page 57

PIC18FXX39

EXAMPLE 5-3:

WRITING TO FLASH PROGRAM MEMORY

MOVLW

D'64

; number of bytes in erase block

MOVWF

MOVLW

MOVWF

MOVLW

MOVWF

MOVLW

MOVWF

MOVLW

MOVWF

MOVLW

MOVWF

COUNTER

BUFFER_ADDR_HIGH

FSR0H

BUFFER_ADDR_LOW

FSR0L

CODE_ADDR_UPPER

TBLPTRU

CODE_ADDR_HIGH

TBLPTRH

CODE_ADDR_LOW

TBLPTRL

; point to buffer

; Load TBLPTR with the base

; address of the memory block

READ_BLOCK

TBLRD*+

MOVF

MOVWF

; read into TABLAT, and inc

; get data

; store data

; done?

TABLAT, W

POSTINC0

DECFSZ COUNTER

BRA

READ_BLOCK

; repeat

MODIFY_WORD

MOVLW

MOVWF

MOVLW

MOVWF

MOVLW

MOVWF

MOVLW

MOVWF

DATA_ADDR_HIGH

FSR0H

DATA_ADDR_LOW

FSR0L

NEW_DATA_LOW

POSTINC0

NEW_DATA_HIGH

INDF0

; point to buffer

; update buffer word

ERASE_BLOCK

MOVLW

MOVWF

MOVLW

MOVWF

MOVLW

MOVWF

BSF

BCF

BSF

BCF

MOVLW

MOVWF

MOVLW

MOVWF

BSF

CODE_ADDR_UPPER

TBLPTRU

CODE_ADDR_HIGH

TBLPTRH

CODE_ADDR_LOW

TBLPTRL

EECON1,EEPGD

EECON1,CFGS

EECON1,WREN

EECON1,FREE

INTCON,GIE

55h

EECON2

AAh

EECON2

EECON1,WR

INTCON,GIE

; load TBLPTR with the base

; address of the memory block

; point to FLASH program memory

; access FLASH program memory

; enable write to memory

; enable Row Erase operation

; disable interrupts

; write 55h

; write AAh

; start erase (CPU stall)

; re-enable interrupts

; dummy read decrement

BSF

TBLRD*-

WRITE_BUFFER_BACK

MOVLW

8

; number of write buffer groups of 8 bytes

; point to buffer

MOVWF

MOVLW

MOVWF

COUNTER_HI

BUFFER_ADDR_HIGH

FSR0H

MOVLW

MOVWF

BUFFER_ADDR_LOW

FSR0L

PROGRAM_LOOP

MOVLW

8

; number of bytes in holding register

MOVWF

COUNTER

WRITE_WORD_TO_HREGS

MOVF

POSTINC0, W

TABLAT

; get low byte of buffer data

; present data to table latch

; write data, perform a short write

; to internal TBLWT holding register.

; loop until buffers are full

MOVWF

TBLWT+*

DECFSZ COUNTER

BRA

WRITE_WORD_TO_HREGS

DS30485A-page 58

Preliminary

 2002 Microchip Technology Inc.

PIC18FXX39

EXAMPLE 5-3:

PROGRAM_MEMORY

WRITING TO FLASH PROGRAM MEMORY (CONTINUED)

BSF

BCF

BSF

BCF

EECON1,EEPGD

EECON1,CFGS

EECON1,WREN

INTCON,GIE

55h

; point to FLASH program memory

; access FLASH program memory

; enable write to memory

; disable interrupts

MOVLW

Required

Sequence

MOVWF

MOVLW

MOVWF

BSF

EECON2

AAh

EECON2

EECON1,WR

INTCON,GIE

; write 55h

; write AAh

; start program (CPU stall)

; re-enable interrupts

; loop until done

BSF

DECFSZ COUNTER_HI

BRA

BCF

PROGRAM_LOOP

EECON1,WREN

; disable write to memory

5.5.2

WRITE VERIFY

5.5.4

PROTECTION AGAINST SPURIOUS

WRITES

Depending on the application, good programming

practice may dictate that the value written to the mem-

ory should be verified against the original value. This

should be used in applications where excessive writes

can stress bits near the specification limit.

To protect against spurious writes to FLASH program

memory, the write initiate sequence must also be fol-

lowed. See “Special Features of the CPU”

(Section 20.0) for more detail.

5.5.3

UNEXPECTED TERMINATION OF

WRITE OPERATION

5.6

FLASH Program Operation During

Code Protection

If a write is terminated by an unplanned event, such as

loss of power or an unexpected RESET, the memory

location just programmed should be verified and repro-

grammed if needed.The WRERR bit is set when a write

operation is interrupted by a MCLR Reset, or a WDT

Time-out Reset during normal operation. In these situ-

ations, users can check the WRERR bit and rewrite the

location.

See “Special Features of the CPU” (Section 20.0) for

details on code protection of FLASH program memory.

TABLE 5-2:

REGISTERS ASSOCIATED WITH PROGRAM FLASH MEMORY

Value on

Value on:

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

All Other

RESETS

POR, BOR

TBLPTRU

—

bit 21

Program Memory Table Pointer Upper Byte

(TBLPTR<20:16>)

--00 0000 --00 0000

TBPLTRH Program Memory Table Pointer High Byte (TBLPTR<15:8>)

TBLPTRL Program Memory Table Pointer High Byte (TBLPTR<7:0>)

0000 0000 0000 0000

0000 000x 0000 000u

TABLAT

INTCON

Program Memory Table Latch

GIE/GIEH PEIE/GIEL TMR0IE

INTE

RBIE

TMR0IF

INTF

RBIF

EECON2 EEPROM Control Register2 (not a physical register)

—

EECON1

IPR2

EEPGD

—

CFGS

—

FREE

EEIP

WRERR

BCLIP

WREN

LVDIP

WR

RD

—

xx-0 x000 uu-0 u000

---1 1111 ---1 1111

TMR3IP

PIR2

PIE2

—

EEIF

EEIE

BCLIF

BCLIE

LVDIF

LVDIE

TMR3IF

TMR3IE

—

---0 0000 ---0 0000

Legend: x= unknown, u= unchanged, - = unimplemented read as '0'. Shaded cells are not used during FLASH/EEPROM access.

 2002 Microchip Technology Inc.

Preliminary

DS30485A-page 59

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NOTES:

DS30485A-page 60

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 2002 Microchip Technology Inc.

PIC18FXX39

6.1

EEADR

6.0

DATA EEPROM MEMORY

The address register can address up to a maximum of

256 bytes of data EEPROM.

The Data EEPROM is readable and writable during

normal operation over the entire VDD range. The data

memory is not directly mapped in the register file

space. Instead, it is indirectly addressed through the

Special Function Registers (SFR).

There are four SFRs used to read and write the

program and data EEPROM memory. These registers

are:

• EECON1

• EECON2

• EEDATA

• EEADR

The EEPROM data memory allows byte read and write.

When interfacing to the data memory block, EEDATA

holds the 8-bit data for read/write and EEADR holds the

address of the EEPROM location being accessed.

These devices have 256 bytes of data EEPROM with

an address range from 0h to FFh.

The EEPROM data memory is rated for high erase/

write cycles. A byte write automatically erases the loca-

tion and writes the new data (erase-before-write). The

write time is controlled by an on-chip timer. The write

time will vary with voltage and temperature, as well as

from chip to chip. Please refer to parameter D122

(Electrical Characteristics, Section 23.0) for exact

limits.

6.2

EECON1 and EECON2 Registers

EECON1 is the control register for EEPROM memory

accesses.

EECON2 is not a physical register. Reading EECON2

will read all '0's. The EECON2 register is used

exclusively in the EEPROM write sequence.

Control bits RD and WR initiate read and write opera-

tions, respectively. These bits cannot be cleared, only

set, in software. They are cleared in hardware at the

completion of the read or write operation. The inability

to clear the WR bit in software prevents the accidental

or premature termination of a write operation.

The WREN bit, when set, will allow a write operation.

On power-up, the WREN bit is clear. The WRERR bit is

set when a write operation is interrupted by a MCLR

Reset, or a WDT Time-out Reset during normal opera-

tion. In these situations, the user can check the

WRERR bit and rewrite the location. It is necessary to

reload the data and address registers (EEDATA and

EEADR), due to the RESET condition forcing the

contents of the registers to zero.

Note: Interrupt flag bit, EEIF in the PIR2 register,

is set when write is complete. It must be

cleared in software.

 2002 Microchip Technology Inc.

Preliminary

DS30485A-page 61

PIC18FXX39

REGISTER 6-1:

EECON1 REGISTER (ADDRESS FA6h)

R/W-x

EEPGD

R/W-x

CFGS

U-0

—

R/W-0

FREE

R/W-x

WRERR

R/W-0

WREN

R/S-0

WR

R/S-0

RD

bit 7

bit 0

bit 7

bit 6

EEPGD: FLASH Program or Data EEPROM Memory Select bit

1= Access FLASH program memory

0= Access data EEPROM memory

CFGS: FLASH Program/Data EE or Configuration Select bit

1= Access configuration or calibration registers

0= Access FLASH program or data EEPROM memory

bit 5

bit 4

Unimplemented: Read as '0'

FREE: FLASH Row Erase Enable bit

1= Erase the program memory row addressed by TBLPTR on the next WR command

(cleared by completion of erase operation)

0= Perform write only

bit 3

WRERR: FLASH Program/Data EE Error Flag bit

1= A write operation is prematurely terminated

(any MCLR or any WDT Reset during self-timed programming in normal operation)

0= The write operation completed

Note: When a WRERR occurs, the EEPGD or FREE bits are not cleared. This allows tracing

of the error condition.

bit 2

bit 1

WREN: FLASH Program/Data EE Write Enable bit

1= Allows write cycles

0= Inhibits write to the EEPROM

WR: Write Control bit

1= Initiates a data EEPROM erase/write cycle or a program memory erase cycle or write cycle.

(The operation is self-timed and the bit is cleared by hardware once write is complete. The

WR bit can only be set (not cleared) in software.)

0= Write cycle to the EEPROM is complete

bit 0

RD: Read Control bit

1= Initiates an EEPROM read

(Read takes one cycle. RD is cleared in hardware. The RD bit can only be set (not cleared)

in software. RD bit cannot be set when EEPGD = 1.)

0= Does not initiate an EEPROM read

Legend:

R = Readable bit

- n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

DS30485A-page 62

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PIC18FXX39

(EECON1<6>), and then set control bit RD

(EECON1<0>). The data is available for the very next

instruction cycle; therefore, the EEDATA register can

be read by the next instruction. EEDATA will hold this

value until another read operation, or until it is written to

by the user (during a write operation).

6.3

Reading the Data EEPROM

Memory

To read a data memory location, the user must write the

address to the EEADR register, clear the EEPGD con-

trol bit (EECON1<7>), clear the CFGS control bit

EXAMPLE 6-1:

DATA EEPROM READ

MOVLW

MOVWF

BCF

DATA_EE_ADDR

EEADR

EECON1, EEPGD ; Point to DATA memory

;

; Data Memory Address to read

BCF

BSF

MOVF

EECON1, CFGS

EECON1, RD

EEDATA, W

; Access program FLASH or Data EEPROM memory

; EEPROM Read

; W = EEDATA

cution (i.e., runaway programs). The WREN bit should

be kept clear at all times, except when updating the

EEPROM. The WREN bit is not cleared by hardware.

After a write sequence has been initiated, EECON1,

EEADR and EDATA cannot be modified. The WR bit

will be inhibited from being set unless the WREN bit is

set. The WREN bit must be set on a previous instruc-

tion. Both WR and WREN cannot be set with the same

instruction.

At the completion of the write cycle, the WR bit is

cleared in hardware and the EEPROM Write Complete

Interrupt Flag bit (EEIF) is set. The user may either

enable this interrupt, or poll this bit. EEIF must be

cleared by software.

6.4

Writing to the Data EEPROM

Memory

To write an EEPROM data location, the address must

first be written to the EEADR register and the data writ-

ten to the EEDATA register. Then, the sequence in

Example 6-2 must be followed to initiate the write cycle.

The write will not initiate if the above sequence is not

exactly followed (write 55h to EECON2, write AAh to

EECON2, then set WR bit) for each byte. It is strongly

recommended that interrupts be disabled during this

code segment.

Additionally, the WREN bit in EECON1 must be set to

enable writes. This mechanism prevents accidental

writes to data EEPROM due to unexpected code exe-

EXAMPLE 6-2:

DATA EEPROM WRITE

MOVLW

MOVWF

MOVLW

MOVWF

BCF

DATA_EE_ADDR

;

EEADR

DATA_EE_DATA

EEDATA

; Data Memory Address to read

;

; Data Memory Value to write

EECON1, EEPGD ; Point to DATA memory

BCF

BSF

EECON1, CFGS

EECON1, WREN

; Access program FLASH or Data EEPROM memory

; Enable writes

BCF

INTCON, GIE

55h

EECON2

AAh

EECON2

; Disable interrupts

;

; Write 55h

;

; Write AAh

; Set WR bit to begin write

; Enable interrupts

Required

Sequence

MOVLW

MOVWF

MOVLW

MOVWF

BSF

EECON1, WR

INTCON, GIE

BSF

.

; user code execution

.

BCF

EECON1, WREN

; Disable writes on write complete (EEIF set)

 2002 Microchip Technology Inc.

Preliminary

DS30485A-page 63

PIC18FXX39

6.5

Write Verify

6.7

Operation During Code Protect

Depending on the application, good programming

practice may dictate that the value written to the mem-

ory should be verified against the original value. This

should be used in applications where excessive writes

can stress bits near the specification limit.

Data EEPROM memory has its own code protect

mechanism. External read and write operations are

disabled if either of these mechanisms are enabled.

The microcontroller itself can both read and write to the

internal Data EEPROM, regardless of the state of the

code protect configuration bit. Refer to “Special Features

of the CPU” (Section 20.0) for additional information.

6.6

Protection Against Spurious Write

There are conditions when the device may not want to

write to the data EEPROM memory. To protect against

spurious EEPROM writes, various mechanisms have

been built-in. On power-up, the WREN bit is cleared.

Also, the Power-up Timer (72 ms duration) prevents

EEPROM write.

The write initiate sequence and the WREN bit together

help prevent an accidental write during brown-out,

power glitch, or software malfunction.

6.8

Using the Data EEPROM

The data EEPROM is a high endurance, byte address-

able array that has been optimized for the storage of

frequently changing information (e.g., program vari-

ables or other data that are updated often). Frequently

changing values will typically be updated more often

than specification D124. If this is not the case, an array

refresh must be performed. For this reason, variables

that change infrequently (such as constants, IDs, cali-

bration, etc.) should be stored in FLASH program

memory.

A simple data EEPROM refresh routine is shown in

Example 6-3.

Note: If data EEPROM is only used to store con-

stants and/or data that changes rarely, an

array refresh is likely not required. See

specification D124.

EXAMPLE 6-3:

DATA EEPROM REFRESH ROUTINE

clrf

bcf

EEADR

; Start at address 0

EECON1,CFGS

EECON1,EEPGD

INTCON,GIE

EECON1,WREN

; Set for memory

; Set for Data EEPROM

; Disable interrupts

; Enable writes

; Loop to refresh array

; Read current address

;

bcf

bsf

Loop

bsf

EECON1,RD

55h

movlw

movwf

movlw

movwf

bsf

EECON2

AAh

; Write 55h

;

EECON2

EECON1,WR

$-2

; Write AAh

; Set WR bit to begin write

; Wait for write to complete

btfsc

bra

incfsz EEADR,F

; Increment address

bra

Loop

; Not zero, do it again

bcf

bsf

EECON1,WREN

INTCON,GIE

; Disable writes

; Enable interrupts

DS30485A-page 64

Preliminary

 2002 Microchip Technology Inc.

PIC18FXX39

TABLE 6-1:

REGISTERS ASSOCIATED WITH DATA EEPROM MEMORY

Value on

All Other

RESETS

Value on:

POR, BOR

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

FF2h

INTCON

EEADR

GIE/

PEIE/

GIEL

T0IE

INTE

RBIE

T0IF

INTF

RBIF

0000 000x 0000 000u

GIEH

FA9h

FA8h

FA7h

FA6h

FA2h

FA1h

FA0h

EEPROM Address Register

0000 0000 0000 0000

EEDATA EEPROM Data Register

EECON2 EEPROM Control Register2 (not a physical register)

EECON1 EEPGD CFGS

IPR2

PIR2

PIE2

—

FREE WRERR WREN

WR

RD

—

xx-0 x000 uu-0 u000

---1 1111 ---1 1111

---0 0000 ---0 0000

—

EEIP

EEIF

EEIE

BCLIP

BCLIF

BCLIE

LVDIP TMR3IP

LVDIF TMR3IF

LVDIE TMR3IE

—

Legend: x= unknown, u= unchanged, - = unimplemented, read as '0'.

Shaded cells are not used during FLASH/EEPROM access.

 2002 Microchip Technology Inc.

Preliminary

DS30485A-page 65

PIC18FXX39

NOTES:

DS30485A-page 66

Preliminary

 2002 Microchip Technology Inc.

PIC18FXX39

7.2

Operation

7.0

7.1

8 X 8 HARDWARE MULTIPLIER

Introduction

Example 7-1 shows the sequence to do an 8 x 8

unsigned multiply. Only one instruction is required

when one argument of the multiply is already loaded in

the WREG register.

Example 7-2 shows the sequence to do an 8 x 8 signed

multiply. To account for the sign bits of the arguments,

each argument’s Most Significant bit (MSb) is tested

and the appropriate subtractions are done.

An 8 x 8 hardware multiplier is included in the ALU of

the PIC18FXX39 devices. By making the multiply a

hardware operation, it completes in a single instruction

cycle. This is an unsigned multiply that gives a 16-bit

result. The result is stored into the 16-bit product regis-

ter pair (PRODH:PRODL). The multiplier does not

affect any flags in the ALUSTA register.

Making the 8 x 8 multiplier execute in a single cycle

gives the following advantages:

• Higher computational throughput

• Reduces code size requirements for multiply

algorithms

EXAMPLE 7-1:

8 x 8 UNSIGNED

MULTIPLY ROUTINE

MOVF

ARG1, W

ARG2

;

MULWF

; ARG1 * ARG2 ->

; PRODH:PRODL

The performance increase allows the device to be used

in applications previously reserved for Digital Signal

Processors.

Table 7-1 shows a performance comparison between

enhanced devices using the single cycle hardware mul-

tiply, and performing the same function without the

hardware multiply.

EXAMPLE 7-2:

8 x 8 SIGNED MULTIPLY

ROUTINE

MOVF

MULWF

ARG1,

ARG2

W

; ARG1 * ARG2 ->

; PRODH:PRODL

; Test Sign Bit

; PRODH = PRODH

BTFSC

SUBWF

ARG2, SB

PRODH, F

;

- ARG1

MOVF

ARG2,

W

BTFSC

SUBWF

ARG1, SB

PRODH, F

; Test Sign Bit

; PRODH = PRODH

;

- ARG2

TABLE 7-1:

Routine

PERFORMANCE COMPARISON

Program

Time

@ 40 MHz @ 10 MHz @ 4 MHz

Cycles

Multiply Method

Memory

(Words)

(Max)

Without hardware multiply

Hardware multiply

Without hardware multiply

Hardware multiply

Without hardware multiply

Hardware multiply

Without hardware multiply

Hardware multiply

13

1

33

6

21

28

52

35

69

1

91

6

242

28

254

40

6.9 µs

100 ns

9.1 µs

600 ns

24.2 µs

2.8 µs

25.4 µs

4.0 µs

27.6 µs

400 ns

36.4 µs

2.4 µs

96.8 µs

11.2 µs

102.6 µs

16.0 µs

69 µs

1 µs

91 µs

6 µs

242 µs

28 µs

254 µs

40 µs

8 x 8 unsigned

8 x 8 signed

16 x 16 unsigned

16 x 16 signed

 2002 Microchip Technology Inc.

Preliminary

DS30485A-page 67

PIC18FXX39

Example 7-3 shows the sequence to do a 16 x 16

unsigned multiply. Equation 7-1 shows the algorithm

that is used. The 32-bit result is stored in four registers,

RES3:RES0.

EQUATION 7-2:

16 x 16 SIGNED

MULTIPLICATION

ALGORITHM

RES3:RES0

=

ARG1H:ARG1L • ARG2H:ARG2L

(ARG1H • ARG2H • 2¹⁶) +

EQUATION 7-1:

16 x 16 UNSIGNED

MULTIPLICATION

ALGORITHM

(ARG1H • ARG2L • 2⁸) +

(ARG1L • ARG2H • 2⁸) +

(ARG1L • ARG2L) +

RES3:RES0

=

ARG1H:ARG1L • ARG2H:ARG2L

(ARG1H • ARG2H • 2¹⁶) +

(ARG1H • ARG2L • 2⁸) +

(ARG1L • ARG2H • 2⁸) +

(ARG1L • ARG2L)

(-1 • ARG2H<7> • ARG1H:ARG1L • 2¹⁶) +

(-1 • ARG1H<7> • ARG2H:ARG2L • 2¹⁶)

EXAMPLE 7-4:

16 x 16 SIGNED

MULTIPLY ROUTINE

MOVF

MULWF

ARG1L,

ARG2L

W

EXAMPLE 7-3:

16 x 16 UNSIGNED

MULTIPLY ROUTINE

; ARG1L * ARG2L ->

; PRODH:PRODL

;

MOVF

ARG1L, W

ARG2L

MOVFF

PRODH, RES1

PRODL, RES0

MULWF

; ARG1L * ARG2L ->

; PRODH:PRODL

;

MOVFF

PRODH, RES1

PRODL, RES0

MOVF

MULWF

ARG1H,

ARG2H

W

; ARG1H * ARG2H ->

;

; PRODH:PRODL

;

MOVF

MULWF

ARG1H,

ARG2H

W

MOVFF

PRODH, RES3

PRODL, RES2

; ARG1H * ARG2H ->

; PRODH:PRODL

MOVFF

PRODH, RES3

PRODL, RES2

;

MOVF

MULWF

ARG1L,

ARG2H

W

; ARG1L * ARG2H ->

; PRODH:PRODL

MOVF

MULWF

ARG1L,

ARG2H

W

MOVF

ADDWF

MOVF

ADDWFC RES2,

CLRF WREG

ADDWFC RES3,

PRODL,

RES1,

PRODH,

W

F

W

F

;

; ARG1L * ARG2H ->

; PRODH:PRODL

;

; Add cross

; products

;

; Add cross

; products

;

MOVF

ADDWF

MOVF

ADDWFC RES2,

CLRF WREG

ADDWFC RES3,

PRODL,

RES1,

PRODH,

W

F

W

F

W

;

MOVF

MULWF

ARG1H,

ARG2L

;

F

W

; ARG1H * ARG2L ->

; PRODH:PRODL

;

; Add cross

; products

;

MOVF

MULWF

ARG1H,

ARG2L

;

MOVF

ADDWF

MOVF

ADDWFC RES2,

CLRF WREG

ADDWFC RES3,

PRODL,

RES1,

PRODH,

W

F

W

F

; ARG1H * ARG2L ->

; PRODH:PRODL

;

; Add cross

; products

;

MOVF

ADDWF

MOVF

ADDWFC RES2,

CLRF WREG

ADDWFC RES3,

PRODL,

RES1,

PRODH,

W

F

W

F

7

;

BTFSS

BRA

MOVF

SUBWF

MOVF

ARG2H,

SIGN_ARG1

ARG1L,

RES2

ARG1H,

; ARG2H:ARG2L neg?

; no, check ARG1

;

F

W

Example 7-4 shows the sequence to do a 16 x 16

signed multiply. Equation 7-2 shows the algorithm

used. The 32-bit result is stored in four registers,

RES3:RES0. To account for the sign bits of the argu-

ments, each argument pairs Most Significant bit (MSb)

is tested and the appropriate subtractions are done.

SUBWFB RES3

SIGN_ARG1

BTFSS

BRA

ARG1H,

CONT_CODE

ARG2L,

RES2

ARG2H,

7

; ARG1H:ARG1L neg?

; no, done

;

MOVF

SUBWF

MOVF

W

SUBWFB RES3

;

CONT_CODE

:

DS30485A-page 68

Preliminary

 2002 Microchip Technology Inc.

PIC18FXX39

While PIC18FXX39 devices have two interrupt priority

levels like other PIC18 microcontrollers, their allocation

is different. In these devices, the high priority interrupt

is used exclusively by the ProMPT kernel via the

Timer2 match interrupt. In order for the kernel to func-

tion properly, it is imperative that all other interrupts

either set as low priority (IPR bit = 0), or disabled.

8.0

INTERRUPTS

The PIC18FXX39 devices have multiple interrupt

sources and an interrupt priority feature that allows

each interrupt source to be assigned a high priority

level or a low priority level. The high priority interrupt

vector is at 000008h and the low priority interrupt vector

is at 000018h. High priority interrupt events will

override any low priority interrupts that may be in

progress.

There are ten registers which are used to control

interrupt operation. These registers are:

• RCON

Note: Disabling interrupts, or setting interrupts as

low priority, is not the same as disabling

interrupt priorities. The interrupt priority

levels must remain enabled (IPEN = 1).

Clearing the IPEN bit will result in erratic

operation of the ProMPT kernel.

• INTCON

When an interrupt is responded to, the Global Interrupt

Enable bit is cleared to disable further interrupts. If the

IPEN bit is cleared, this is the GIE bit. If interrupt priority

levels are used, this will be either the GIEH or GIEL bit.

High priority interrupt sources can interrupt a low

priority interrupt.

The return address is pushed onto the stack and the

PC is loaded with the interrupt vector address

(000008h or 000018h). Once in the Interrupt Service

Routine, the source(s) of the interrupt can be deter-

mined by polling the interrupt flag bits. The interrupt

flag bits must be cleared in software before re-enabling

interrupts to avoid recursive interrupts.

• INTCON2

• INTCON3

• PIR1, PIR2

• PIE1, PIE2

• IPR1, IPR2

It is recommended that the Microchip header files sup-

plied with MPLAB^®IDE be used for the symbolic bit

names in these registers. This allows the assembler/

compiler to automatically take care of the placement of

these bits within the specified register.

Each interrupt source, except INT0, has three bits to

control its operation. The functions of these bits are:

The “return from interrupt” instruction, RETFIE, exits

the interrupt routine and sets the GIEH or GIEL bits (as

applicable), which re-enables interrupts.

• Flag bit to indicate that an interrupt event

occurred

• Enable bit that allows program execution to

branch to the interrupt vector address when the

flag bit is set

For external interrupt events, such as the INT pins or

the PORTB input change interrupt, the interrupt latency

will be three to four instruction cycles. The exact

latency is the same for one or two-cycle instructions.

Individual interrupt flag bits are set, regardless of the

status of their corresponding enable bit or the GIE bit.

• Priority bit to select high priority or low priority

The interrupt priority feature is enabled by setting the

IPEN bit (RCON<7>). When interrupt priority is

enabled, there are two bits which enable interrupts glo-

bally. Setting the GIEH bit (INTCON<7>) enables all

interrupts that have the priority bit set. Setting the GIEL

bit (INTCON<6>) enables all interrupts that have the

priority bit cleared. When the interrupt flag, enable bit

and appropriate global interrupt enable bit are set, the

interrupt will vector immediately to address 000008h or

000018h, depending on the priority level. Individual

interrupts can be disabled through their corresponding

enable bits.

Note: Do not use the MOVFFinstruction to modify

any of the Interrupt control registers while

any interrupt is enabled. Doing so may

cause erratic microcontroller behavior.

 2002 Microchip Technology Inc.

Preliminary

DS30485A-page 69

PIC18FXX39

FIGURE 8-1:

INTERRUPT LOGIC

Wake-up if in SLEEP mode

TMR0IF

TMR0IE

TMR0IP

RBIF

RBIE

RBIP

INT0IF

INT0IE

Interrupt to CPU

Vector to location

0008h

INT1IF

INT1IE

INT1IP

INT2IF

INT2IE

INT2IP

Peripheral Interrupt Flag bit

Peripheral Interrupt Enable bit

Peripheral Interrupt Priority bit

GIEH/GIE

TMR2IF

TMR2IE

TMR2IP

XXXXIF

XXXXIE

XXXXIP

Additional Peripheral Interrupts

High Priority Interrupt Generation

Low Priority Interrupt Generation

Peripheral Interrupt Flag bit

Peripheral Interrupt Enable bit

Peripheral Interrupt Priority bit

Interrupt to CPU

Vector to Location

0018h

TMR0IF

TMR0IE

TMR0IP

TMR1IF

TMR1IE

TMR1IP

RBIF

RBIE

RBIP

GIEL/PEIE

GIE/GIEH

XXXXIF

XXXXIE

XXXXIP

INT1IF

INT1IE

INT1IP

INT2IF

INT2IE

INT2IP

Additional Peripheral Interrupts

DS30485A-page 70

Preliminary

 2002 Microchip Technology Inc.

PIC18FXX39

8.1

INTCON Registers

Note: Interrupt flag bits are set when an interrupt

condition occurs, regardless of the state of

its corresponding enable bit or the global

enable bit. User software should ensure

the appropriate interrupt flag bits are clear

prior to enabling an interrupt. This feature

allows for software polling.

The INTCON Registers are readable and writable

registers, which contain various enable, priority and

flag bits.

REGISTER 8-1:

INTCON REGISTER

R/W-0 R/W-0

R/W-0

RBIE

R/W-0

TMR0IF

R/W-0

INT0IF

R/W-x

RBIF⁽²⁾

bit 0

GIE/GIEH PEIE/GIEL TMR0IE INT0IE⁽¹⁾

bit 7

bit 6

GIE/GIEH: Global Interrupt Enable bit

1= Enables all high priority interrupts

0= Disables all interrupts

PEIE/GIEL: Peripheral Interrupt Enable bit

1= Enables all low priority peripheral interrupts

0= Disables all low priority peripheral interrupts

bit 5

bit 4

bit 3

TMR0IE: TMR0 Overflow Interrupt Enable bit

1= Enables the TMR0 overflow interrupt

0= Disables the TMR0 overflow interrupt

INT0IE⁽¹⁾: INT0 External Interrupt Enable bit

1= Enables the INT0 external interrupt

0= Disables the INT0 external interrupt

RBIE: RB Port Change Interrupt Enable bit

1= Enables the RB port change interrupt

0= Disables the RB port change interrupt

bit 2

bit 1

bit 0

TMR0IF: TMR0 Overflow Interrupt Flag bit

1= TMR0 register has overflowed (must be cleared in software)

0= TMR0 register did not overflow

INT0IF: INT0 External Interrupt Flag bit

1= The INT0 external interrupt occurred (must be cleared in software)

0= The INT0 external interrupt did not occur

RBIF⁽²⁾: RB Port Change Interrupt Flag bit

1= At least one of the RB7:RB4 pins changed state (must be cleared in software)

0= None of the RB7:RB4 pins have changed state

Note 1: Maintain this bit cleared (= 0).

2: A mismatch condition will continue to set this bit. Reading PORTB will end the

mismatch condition and allow the bit to be cleared.

Legend:

R = Readable bit

- n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

 2002 Microchip Technology Inc.

Preliminary

DS30485A-page 71

PIC18FXX39

REGISTER 8-2:

INTCON2 REGISTER

R/W-1

RBPU

bit 7

R/W-1

U-0

—

R/W-1

TMR0IP

U-0

—

R/W-1

RBIP⁽¹⁾

bit 0

INTEDG0 INTEDG1 INTEDG2

bit 7

bit 6

bit 5

bit 4

RBPU: PORTB Pull-up Enable bit

1= All PORTB pull-ups are disabled

0= PORTB pull-ups are enabled by individual port latch values

INTEDG0: External Interrupt 0 Edge Select bit

1= Interrupt on rising edge

0= Interrupt on falling edge

INTEDG1: External Interrupt 1 Edge Select bit

1= Interrupt on rising edge

0= Interrupt on falling edge

INTEDG2: External Interrupt 2 Edge Select bit

1= Interrupt on rising edge

0= Interrupt on falling edge

bit 3

bit 2

Unimplemented: Read as '0'

TMR0IP⁽¹⁾: TMR0 Overflow Interrupt Priority bit

1= High priority

0= Low priority

bit 1

bit 0

Unimplemented: Read as '0'

RBIP⁽¹⁾: RB Port Change Interrupt Priority bit

1= High priority

0= Low priority

Note 1: Maintain this bit cleared (= 0).

Legend:

R = Readable bit

- n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

Note: Interrupt flag bits are set when an interrupt condition occurs, regardless of the state

of its corresponding enable bit or the global enable bit. User software should ensure

the appropriate interrupt flag bits are clear prior to enabling an interrupt. This feature

allows for software polling.

DS30485A-page 72

Preliminary

 2002 Microchip Technology Inc.

PIC18FXX39

REGISTER 8-3:

INTCON3 REGISTER

R/W-1

U-0

—

R/W-0

INT2IE

R/W-0

INT1IE

U-0

—

R/W-0

INT2IF

R/W-0

INT1IF

INT2IP⁽¹⁾INT1IP⁽¹⁾

bit 7

bit 0

bit 7

bit 6

INT2IP⁽¹⁾: INT2 External Interrupt Priority bit

1= High priority

0= Low priority

INT1IP⁽¹⁾: INT1 External Interrupt Priority bit

1= High priority

0= Low priority

bit 5

bit 4

Unimplemented: Read as '0'

INT2IE: INT2 External Interrupt Enable bit

1= Enables the INT2 external interrupt

0= Disables the INT2 external interrupt

bit 3

INT1IE: INT1 External Interrupt Enable bit

1= Enables the INT1 external interrupt

0= Disables the INT1 external interrupt

bit 2

bit 1

Unimplemented: Read as '0'

INT2IF: INT2 External Interrupt Flag bit

1= The INT2 external interrupt occurred (must be cleared in software)

0= The INT2 external interrupt did not occur

bit 0

INT1IF: INT1 External Interrupt Flag bit

1= The INT1 external interrupt occurred (must be cleared in software)

0= The INT1 external interrupt did not occur

Note

1: Maintain this bit cleared (= 0).

Legend:

R = Readable bit

- n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared

x = Bit is unknown

Note: Interrupt flag bits are set when an interrupt condition occurs, regardless of the state

of its corresponding enable bit or the global enable bit. User software should ensure

the appropriate interrupt flag bits are clear prior to enabling an interrupt. This feature

allows for software polling.

 2002 Microchip Technology Inc.

Preliminary

DS30485A-page 73

PIC18FXX39

8.2

PIR Registers

Note 1: Interrupt flag bits are set when an interrupt

condition occurs, regardless of the state of

its corresponding enable bit or the global

enable bit, GIE (INTCON<7>).

The PIR registers contain the individual flag bits for the

peripheral interrupts. Due to the number of peripheral

interrupt sources, there are two Peripheral Interrupt

Flag registers (PIR1, PIR2).

2: User software should ensure the appropri-

ate interrupt flag bits are cleared prior to

enabling an interrupt, and after servicing

that interrupt.

REGISTER 8-4:

PIR1: PERIPHERAL INTERRUPT REQUEST (FLAG) REGISTER 1

R/W-0

PSPIF⁽¹⁾

bit 7

R/W-0

ADIF

R-0

RCIF

R-0

TXIF

R/W-0

SSPIF

U-0

—

R/W-0

TMR2IF⁽²⁾TMR1IF

bit 0

bit 7

bit 6

bit 5

bit 4

bit 3

PSPIF⁽¹⁾: Parallel Slave Port Read/Write Interrupt Flag bit

1= A read or a write operation has taken place (must be cleared in software)

0= No read or write has occurred

ADIF: A/D Converter Interrupt Flag bit

1= An A/D conversion completed (must be cleared in software)

0= The A/D conversion is not complete

RCIF: USART Receive Interrupt Flag bit

1= The USART receive buffer, RCREG, is full (cleared when RCREG is read)

0= The USART receive buffer is empty

TXIF: USART Transmit Interrupt Flag bit (see Section 17.0 for details on TXIF functionality)

1= The USART transmit buffer, TXREG, is empty (cleared when TXREG is written)

0= The USART transmit buffer is full

SSPIF: Master Synchronous Serial Port Interrupt Flag bit

1= The transmission/reception is complete (must be cleared in software)

0= Waiting to transmit/receive

bit 2

bit 1

Unimplemented: Read as ‘0’

TMR2IF⁽²⁾: TMR2 to PR2 Match Interrupt Flag bit

1= TMR2 to PR2 match occurred (must be cleared in software)

0= No TMR2 to PR2 match occurred

bit 0

TMR1IF: TMR1 Overflow Interrupt Flag bit

1= TMR1 register overflowed (must be cleared in software)

0= MR1 register did not overflow

Note 1: This bit is reserved on PIC18F2X39 devices; always maintain this bit clear.

2: This bit is reserved for use by the ProMPT kernel; do not alter its value.

Legend:

R = Readable bit

- n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

DS30485A-page 74

Preliminary

 2002 Microchip Technology Inc.

PIC18FXX39

REGISTER 8-5:

PIR2: PERIPHERAL INTERRUPT REQUEST (FLAG) REGISTER 2

U-0

—

U-0

—

U-0

—

R/W-0

EEIF

R/W-0

BCLIF

R/W-0

LVDIF

R/W-0

TMR3IF

U-0

—

bit 7

bit 0

bit 7-5

bit 4

Unimplemented: Read as '0'

EEIF: Data EEPROM/FLASH Write Operation Interrupt Flag bit

1= The write operation is complete (must be cleared in software)

0= The write operation is not complete, or has not been started

bit 3

bit 2

bit 1

bit 0

BCLIF: Bus Collision Interrupt Flag bit

1= A bus collision occurred (must be cleared in software)

0= No bus collision occurred

LVDIF: Low Voltage Detect Interrupt Flag bit

1= A low voltage condition occurred (must be cleared in software)

0= The device voltage is above the Low Voltage Detect trip point

TMR3IF: TMR3 Overflow Interrupt Flag bit

1= TMR3 register overflowed (must be cleared in software)

0= TMR3 register did not overflow

Unimplemented: Read as ‘0’

Legend:

R = Readable bit

- n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

 2002 Microchip Technology Inc.

Preliminary

DS30485A-page 75

PIC18FXX39

8.3

PIE Registers

The PIE registers contain the individual enable bits for

the peripheral interrupts. Due to the number of periph-

eral interrupt sources, there are two Peripheral Inter-

rupt Enable registers (PIE1, PIE2). When IPEN = 0, the

PEIE bit must be set to enable any of these peripheral

interrupts.

REGISTER 8-6:

PIE1: PERIPHERAL INTERRUPT ENABLE REGISTER 1

R/W-0

PSPIE⁽¹⁾

bit 7

R/W-0

ADIE

R/W-0

RCIE

R/W-0

TXIE

R/W-0

SSPIE

U-0

—

R/W-0

TMR2IE⁽²⁾TMR1IE

bit 0

bit 7

bit 6

bit 5

bit 4

bit 3

PSPIE⁽¹⁾: Parallel Slave Port Read/Write Interrupt Enable bit

1= Enables the PSP read/write interrupt

0= Disables the PSP read/write interrupt

ADIE: A/D Converter Interrupt Enable bit

1= Enables the A/D interrupt

0= Disables the A/D interrupt

RCIE: USART Receive Interrupt Enable bit

1= Enables the USART receive interrupt

0= Disables the USART receive interrupt

TXIE: USART Transmit Interrupt Enable bit

1= Enables the USART transmit interrupt

0= Disables the USART transmit interrupt

SSPIE: Master Synchronous Serial Port Interrupt Enable bit

1= Enables the MSSP interrupt

0= Disables the MSSP interrupt

bit 2

bit 1

Unimplemented: Read as ‘0’

TMR2IE⁽²⁾: TMR2 to PR2 Match Interrupt Enable bit

1= Enables the TMR2 to PR2 match interrupt

0= Disables the TMR2 to PR2 match interrupt

bit 0

TMR1IE: TMR1 Overflow Interrupt Enable bit

1= Enables the TMR1 overflow interrupt

0= Disables the TMR1 overflow interrupt

Note 1: This bit is reserved on PIC18F2X39 devices; always maintain this bit clear.

2: This bit is reserved for use by the ProMPT kernel; do not alter its value.

Legend:

R = Readable bit

- n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

DS30485A-page 76

Preliminary

 2002 Microchip Technology Inc.

PIC18FXX39

REGISTER 8-7:

PIE2: PERIPHERAL INTERRUPT ENABLE REGISTER 2

U-0

—

U-0

—

U-0

—

R/W-0

EEIE

R/W-0

BCLIE

R/W-0

LVDIE

R/W-0

TMR3IE

U-0

—

bit 7

bit 0

bit 7-5

bit 4

Unimplemented: Read as '0'

EEIE: Data EEPROM/FLASH Write Operation Interrupt Enable bit

1= Enabled

0= Disabled

bit 3

bit 2

bit 1

bit 0

BCLIE: Bus Collision Interrupt Enable bit

1= Enabled

0= Disabled

LVDIE: Low Voltage Detect Interrupt Enable bit

1= Enabled

0= Disabled

TMR3IE: TMR3 Overflow Interrupt Enable bit

1= Enables the TMR3 overflow interrupt

0= Disables the TMR3 overflow interrupt

Unimplemented: Read as ‘0’

Legend:

R = Readable bit

- n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

 2002 Microchip Technology Inc.

Preliminary

DS30485A-page 77

PIC18FXX39

In practical terms, this means:

• Interrupt priority levels are enabled (IPEN = 1);

• High priority interrupts are enabled

(INTCON<7> = 1);

• Timer2 interrupt is enabled and set as high priority

(PIE1<1> and IPR<1> = 1); and

• all other interrupts are disabled (INTCON or PIR

bits = 0), or set as low priority (IPR bits = 0).

Note: Configuring the interrupts is automatically

done by the API method void

ProMPT_Init(PWMfrequency). It is the

user’s responsibility to make certain that

this method is called at the very beginning

of the application.

8.4

IPR Registers

The IPR registers contain the individual priority bits for

the peripheral interrupts. Due to the number of periph-

eral interrupt sources, there are two Peripheral Inter-

rupt Priority registers (IPR1, IPR2). The operation of

the priority bits requires that the Interrupt Priority

Enable (IPEN) bit be set.

For PIC18FXX39 devices, the Motor Control kernel

requires that the Timer2 to PR2 match interrupt be the

only high priority interrupt. Failure to do this may result

in unpredictable operation of the kernel or the entire

microcontroller.

REGISTER 8-8:

IPR1: PERIPHERAL INTERRUPT PRIORITY REGISTER 1

R/W-1

U-1

—

R/W-1

PSPIP^(1,2)ADIP⁽²⁾

bit 7

RCIP⁽²⁾

TXIP⁽²⁾

SSPIP⁽²⁾

TMR2IP⁽³⁾TMR1IP⁽²⁾

bit 0

bit 7

bit 6

bit 5

bit 4

bit 3

PSPIP^(1,2): Parallel Slave Port Read/Write Interrupt Priority bit

1= High priority

0= Low priority

ADIP⁽²⁾: A/D Converter Interrupt Priority bit

1= High priority

0= Low priority

RCIP⁽²⁾: USART Receive Interrupt Priority bit

1= High priority

0= Low priority

TXIP⁽²⁾: USART Transmit Interrupt Priority bit

1= High priority

0= Low priority

SSPIP⁽²⁾: Master Synchronous Serial Port Interrupt Priority bit

1= High priority

0= Low priority

bit 2

bit 1

Unimplemented: Read as ‘1’

TMR2IP⁽³⁾: TMR2 to PR2 Match Interrupt Priority bit

1= High priority

0= Low priority

bit 0

TMR1IP⁽²⁾: TMR1 Overflow Interrupt Priority bit

1= High priority

0= Low priority

Note 1: This bit is reserved on PIC18F2X39 devices.

2: Maintain this bit cleared (= 0).

3: This bit is reserved for use by the ProMPT kernel; always maintain this bit set (= 1).

Legend:

R = Readable bit

- n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

DS30485A-page 78

Preliminary

 2002 Microchip Technology Inc.

PIC18FXX39

REGISTER 8-9:

IPR2: PERIPHERAL INTERRUPT PRIORITY REGISTER 2

U-0

—

U-0

—

U-0

—

R/W-1

U-1

—

EEIP⁽¹⁾

BCLIP⁽¹⁾LVDIP⁽¹⁾TMR3IP⁽¹⁾

bit 7

bit 0

bit 7-5

bit 4

Unimplemented: Read as '0'

EEIP⁽¹⁾: Data EEPROM/FLASH Write Operation Interrupt Priority bit

1= High priority

0= Low priority

bit 3

bit 2

bit 1

bit 0

BCLIP⁽¹⁾: Bus Collision Interrupt Priority bit

1= High priority

0= Low priority

LVDIP⁽¹⁾: Low Voltage Detect Interrupt Priority bit

1= High priority

0= Low priority

TMR3IP⁽¹⁾: TMR3 Overflow Interrupt Priority bit

1= High priority

0= Low priority

Unimplemented: Read as ‘1’

Note 1: Maintain this bit cleared (= 0).

Legend:

R = Readable bit

- n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

 2002 Microchip Technology Inc.

Preliminary

DS30485A-page 79

PIC18FXX39

8.5

RCON Register

The RCON register contains the bit which is used to

enable prioritized interrupts (IPEN). For PIC18FXX39

devices, the IPEN bit must always be set (= 1) for the

ProMPT kernel to function correctly. Refer to page 69

for a more detailed discussion on interrupt priorities.

REGISTER 8-10: RCON REGISTER

R/W-0

IPEN⁽¹⁾

bit 7

U-0

—

U-0

—

R/W-1

RI

R-1

TO

R-1

PD

R/W-0

POR

R/W-0

BOR

bit 0

bit 7

IPEN⁽¹⁾: Interrupt Priority Enable bit

1= Enable priority levels on interrupts

0= Disable priority levels on interrupts (not used)

bit 6-5

bit 4

Unimplemented: Read as '0'

RI: RESETInstruction Flag bit

For details of bit operation, see Register 4-3

TO: Watchdog Time-out Flag bit

For details of bit operation, see Register 4-3

PD: Power-down Detection Flag bit

For details of bit operation, see Register 4-3

POR: Power-on Reset Status bit

bit 3

bit 2

bit 1

bit 0

For details of bit operation, see Register 4-3

BOR: Brown-out Reset Status bit

For details of bit operation, see Register 4-3

Note 1: Maintain this bit set (= 1).

Legend:

R = Readable bit

- n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

DS30485A-page 80

Preliminary

 2002 Microchip Technology Inc.

PIC18FXX39

8.6

INT0 Interrupt

8.7

TMR0 Interrupt

External interrupts on the RB0/INT0, RB1/INT1 and

RB2/INT2 pins are edge triggered: either rising, if the

corresponding INTEDGx bit is set in the INTCON2 reg-

ister, or falling, if the INTEDGx bit is clear. When a valid

edge appears on the RBx/INTx pin, the corresponding

flag bit INTxF is set. This interrupt can be disabled by

clearing the corresponding enable bit INTxE. Flag bit

INTxF must be cleared in software in the Interrupt Ser-

vice Routine before re-enabling the interrupt. All exter-

nal interrupts (INT0, INT1 and INT2) can wake-up the

processor from SLEEP, if bit INTxE was set prior to

going into SLEEP. If the global interrupt enable bit GIE

is set, the processor will branch to the interrupt vector

following wake-up.

In 8-bit mode (which is the default), an overflow in the

TMR0 register (FFh → 00h) will set flag bit TMR0IF. In

16-bit mode, an overflow in the TMR0H:TMR0L regis-

ter pair (FFFFh → 0000h) will set flag bit TMR0IF. The

interrupt can be enabled or disabled by setting or

clearing enable bit TMR0IE (INTCON<5>). Interrupt

priority for Timer0 is determined by the value contained

in the interrupt priority bit TMR0IP (INTCON2<2>). See

Section 10.0 for further details on the Timer0 module.

8.8

PORTB Interrupt-on-Change

An input change on PORTB<7:4> sets flag bit RBIF

(INTCON<0>). The interrupt can be enabled or dis-

abled by setting or clearing the enable bit RBIE

(INTCON<3>). Interrupt priority for PORTB interrupt-

on-change is determined by the value contained in the

interrupt priority bit RBIP (INTCON2<0>).

The INT0 interrupt is always configured as a high prior-

ity interrupt, and cannot be reconfigured. Interrupt pri-

ority for INT1 and INT2 is determined by the value

contained in the interrupt priority bits, INT1IP

(INTCON3<6>) and INT2IP (INTCON3<7>).

8.9

Context Saving During Interrupts

Because it is always configured as a high priority inter-

rupt, INT0 cannot be used in conjunction with the

ProMPT kernel; it must always be disabled

(INTCON<4> = 0). Failure to do this may result in

erratic operation of the motor control.

During an interrupt, the return PC value is saved on the

stack. Additionally, the WREG, STATUS and BSR regis-

ters are saved on the fast return stack. If a fast return

from interrupt is not used (see Section 4.3), the user

may need to save the WREG, STATUS and BSR regis-

ters in software. Depending on the user’s application,

other registers may also need to be saved. Example 8-1

saves and restores the WREG, STATUS and BSR

registers during an Interrupt Service Routine.

EXAMPLE 8-1:

SAVING STATUS, WREG AND BSR REGISTERS IN RAM

MOVWF

MOVFF

;

W_TEMP

; W_TEMP is in virtual bank

STATUS,STATUS_TEMP

BSR,

; STATUS_TEMP located anywhere

; BSR located anywhere

BSR_TEMP

; USER ISR CODE

;

MOVFF

MOVF

MOVFF

BSR_TEMP, BSR

W_TEMP,

STATUS_TEMP,STATUS

; Restore BSR

; Restore WREG

; Restore STATUS

W

 2002 Microchip Technology Inc.

Preliminary

DS30485A-page 81

PIC18FXX39

NOTES:

DS30485A-page 82

Preliminary

 2002 Microchip Technology Inc.

PIC18FXX39

EXAMPLE 9-1:

INITIALIZING PORTA

9.0

I/O PORTS

CLRF PORTA

; Initialize PORTA by

; clearing output

; data latches

Depending on the device selected, there are either

three or five ports available. Some pins of the I/O ports

are multiplexed with an alternate function from the

peripheral features on the device. In general, when a

peripheral is enabled, that pin may not be used as a

general purpose I/O pin.

Each port has three registers for its operation. These

registers are:

• TRIS register (data direction register)

CLRF LATA

; Alternate method

; to clear output

; data latches

MOVLW 0x07

MOVWF ADCON1

MOVLW 0xCF

; Configure A/D

; for digital inputs

; Value used to

; initialize data

; direction

; Set RA<3:0> as inputs

; RA<5:4> as outputs

MOVWF TRISA

• PORT register (reads the levels on the pins of the

device)

• LAT register (output latch)

The data latch (LAT register) is useful for read-modify-

write operations on the value that the I/O pins are

driving.

FIGURE 9-1:

BLOCK DIAGRAM OF

RA3:RA0AND RA5PINS

9.1

PORTA, TRISA and LATA

Registers

RD LATA

Data

PORTA is a 7-bit wide, bi-directional port. The corre-

sponding Data Direction register is TRISA. Setting a

TRISA bit (= 1) will make the corresponding PORTA pin

an input (i.e., put the corresponding output driver in a

High Impedance mode). Clearing a TRISA bit (= 0) will

make the corresponding PORTA pin an output (i.e., put

the contents of the output latch on the selected pin).

Bus

D

Q

WR LATA

or

VDD

PORTA

Q

CK

Data Latch

P

I/O pin⁽¹⁾

N

D

Q

Reading the PORTA register reads the status of the

pins, whereas writing to it will write to the port latch.

The Data Latch register (LATA) is also memory

mapped. Read-modify-write operations on the LATA

register reads and writes the latched output value for

PORTA.

The RA4 pin is multiplexed with the Timer0 module

clock input to become the RA4/T0CKI pin. The RA4/

T0CKI pin is a Schmitt Trigger input and an open drain

output. All other RA port pins have TTL input levels and

full CMOS output drivers.

WR TRISA

RD TRISA

VSS

Q

CK

Analog

Input

TRIS Latch

Mode

TTL

Input

Buffer

Q

D

EN

The other PORTA pins are multiplexed with analog

inputs and the analog VREF+ and VREF- inputs. The

operation of each pin is selected by clearing/setting the

control bits in the ADCON1 register (A/D Control

Register1).

RD PORTA

SS Input (RA5 only)

To A/D Converter and LVD Modules

Note: On a Power-on Reset, RA5 and RA3:RA0

are configured as analog inputs and read

as ‘0’. RA6 and RA4 are configured as

digital inputs.

Note 1: I/O pins have protection diodes to VDD and VSS.

The TRISA register controls the direction of the RA

pins, even when they are being used as analog inputs.

The user must ensure the bits in the TRISA register are

maintained set when using them as analog inputs.

 2002 Microchip Technology Inc.

Preliminary

DS30485A-page 83

PIC18FXX39

FIGURE 9-2:

BLOCK DIAGRAM OF

RA4/T0CKI PIN

FIGURE 9-3:

BLOCK DIAGRAM OF

RA6 PIN

ECRA6 or

RCRA6 Enable

Data

Bus

RD LATA

Data

Bus

RD LATA

D

Q

WR LATA

or PORTA

I/O pin⁽¹⁾

Q

CK

D

Q

VDD

P

N

WR LATA

or

Data Latch

PORTA

CK

D

Q

VSS

Data Latch

WR TRISA

RD TRISA

Schmitt

Trigger

Input

I/O pin⁽¹⁾

Q

CK

N

D

Q

TRIS Latch

WR

Buffer

TRISA

VSS

CK

Q

TRIS Latch

Q

D

TTL

RD TRISA

Input

Buffer

EN

ECRA6 or

RCRA6

Enable

RD PORTA

Q

D

TMR0 Clock Input

EN

RD PORTA

Note 1: I/O pin has protection diode to VSS only.

Note 1: I/O pins have protection diodes to VDD and VSS.

DS30485A-page 84

Preliminary

 2002 Microchip Technology Inc.

PIC18FXX39

TABLE 9-1:

Name

PORTA FUNCTIONS

Bit#

Buffer

Function

RA0/AN0

RA1/AN1

RA2/AN2/VREF-

RA3/AN3/VREF+

RA4/T0CKI

bit0

bit1

bit2

bit3

bit4

TTL

ST

Input/output or analog input.

Input/output or analog input or VREF-.

Input/output or analog input or VREF+.

Input/output or external clock input for Timer0.

Output is open drain type.

RA5/SS/AN4/LVDIN

OSC2/CLKO/RA6

bit5

bit6

TTL

Input/output or slave select input for synchronous serial port or analog

input, or low voltage detect input.

OSC2 or clock output or I/O pin.

Legend: TTL = TTL input, ST = Schmitt Trigger input

TABLE 9-2:

SUMMARY OF REGISTERS ASSOCIATED WITH PORTA

Value on

All Other

RESETS

Value on

POR, BOR

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

PORTA

LATA

TRISA

ADCON1

—

RA6

RA5

RA4

RA3

RA2

RA1

RA0

-x0x 0000 -u0u 0000

-xxx xxxx -uuu uuuu

-111 1111 -111 1111

LATA Data Output Register

PORTA Data Direction Register

ADCS2

ADFM

—

PCFG3

PCFG2

PCFG1

PCFG0 00-- 0000 00-- 0000

Legend: x= unknown, u= unchanged, - = unimplemented locations read as '0'. Shaded cells are not used by PORTA.

 2002 Microchip Technology Inc.

Preliminary

DS30485A-page 85

PIC18FXX39

The interrupt-on-change feature is recommended for

wake-up on key depression operation and operations

where PORTB is only used for the interrupt-on-change

feature. Polling of PORTB is not recommended while

using the interrupt-on-change feature.

9.2

PORTB, TRISB and LATB

Registers

PORTB is an 8-bit wide, bi-directional port. The corre-

sponding Data Direction register is TRISB. Setting a

TRISB bit (= 1) will make the corresponding PORTB pin

an input (i.e., put the corresponding output driver in a

High Impedance mode). Clearing a TRISB bit (= 0) will

make the corresponding PORTB pin an output (i.e., put

the contents of the output latch on the selected pin).

The Data Latch register (LATB) is also memory

mapped. Read-modify-write operations on the LATB

register reads and writes the latched output value for

PORTB.

FIGURE 9-4:

BLOCK DIAGRAM OF

RB7:RB4 PINS

VDD

RBPU⁽²⁾

Weak

P

Pull-up

Data Latch

Data Bus

D

Q

I/O pin⁽¹⁾

WR LATB

or PORTB

CK

TRIS Latch

EXAMPLE 9-2:

CLRF

INITIALIZING PORTB

; Initialize PORTB by

; clearing output

; data latches

D

Q

PORTB

WR TRISB

TTL

CK

Input

Buffer

ST

Buffer

CLRF

LATB

; Alternate method

; to clear output

; data latches

RD TRISB

RD LATB

MOVLW 0xCF

; Value used to

; initialize data

; direction

; Set RB<3:0> as inputs

; RB<5:4> as outputs

; RB<7:6> as inputs

Latch

MOVWF TRISB

Q

D

RD PORTB

Set RBIF

EN

Q1

Each of the PORTB pins has a weak internal pull-up. A

single control bit can turn on all the pull-ups. This is per-

formed by clearing bit RBPU (INTCON2<7>). The

weak pull-up is automatically turned off when the port

pin is configured as an output. The pull-ups are

disabled on a Power-on Reset.

D

RD PORTB

Q3

From other

EN

RB7:RB4 pins

RB7:RB5 in Serial Programming mode

Note 1: I/O pins have diode protection to VDD and VSS.

Note: On a Power-on Reset, these pins are

2: To enable weak pull-ups, set the appropriate TRIS bit(s)

configured as digital inputs.

and clear the RBPU bit (INTCON2<7>).

Four of the PORTB pins, RB7:RB4, have an interrupt-

on-change feature. Only pins configured as inputs can

cause this interrupt to occur (i.e., any RB7:RB4 pin

configured as an output is excluded from the interrupt-

on-change comparison). The input pins (of RB7:RB4)

are compared with the old value latched on the last

read of PORTB. The “mismatch” outputs of RB7:RB4

are OR’ed together to generate the RB Port Change

Interrupt with flag bit, RBIF (INTCON<0>).

This interrupt can wake the device from SLEEP. The

user, in the Interrupt Service Routine, can clear the

interrupt in the following manner:

a) Any read or write of PORTB (except with the

MOVFF instruction). This will end the mismatch

condition.

Note 1: While in Low Voltage ICSP mode, the

RB5 pin can no longer be used as a gen-

eral purpose I/O pin, and should be held

low during normal operation to protect

against inadvertent ICSP mode entry.

2: When using Low Voltage ICSP program-

ming (LVP), the pull-up on RB5 becomes

disabled. If TRISB bit 5 is cleared,

thereby setting RB5 as an output, LATB

bit 5 must also be cleared for proper

operation.

b) Clear flag bit RBIF.

A mismatch condition will continue to set flag bit RBIF.

Reading PORTB will end the mismatch condition and

allow flag bit RBIF to be cleared.

DS30485A-page 86

Preliminary

 2002 Microchip Technology Inc.

PIC18FXX39

FIGURE 9-5:

BLOCK DIAGRAM OF RB2:RB0 PINS

VDD

RBPU⁽²⁾

Weak

P

Pull-up

Data Latch

Data Bus

D

Q

I/O pin⁽¹⁾

WR Port

CK

TRIS Latch

D

Q

TTL

WR TRIS

RD TRIS

Input

CK

Buffer

Q

D

RD Port

RB0/INT

EN

Schmitt Trigger

Buffer

Note 1: I/O pins have diode protection to VDD and VSS.

2: To enable weak pull-ups, set the appropriate TRIS bit(s) and clear the RBPU bit (OPTION_REG<7>).

FIGURE 9-6:

BLOCK DIAGRAM OF RB3 PIN

VDD

P

RBPU⁽²⁾

Weak

Pull-up

‘1’

Data Latch

Data Bus

VDD

P

D

Q

WR LATB or

WR PORTB

CK

I/O pin⁽¹⁾

TRIS Latch

D

N

WR TRISB

Q

CK

VSS

TTL

Input

Buffer

RD TRISB

RD LATB

D

Q

EN

RD PORTB

Note 1: I/O pin has diode protection to VDD and VSS.

2: To enable weak pull-ups, set the appropriate DDR bit(s) and clear the RBPU bit (INTCON2<7>).

 2002 Microchip Technology Inc.

Preliminary

DS30485A-page 87

PIC18FXX39

TABLE 9-3:

PORTB FUNCTIONS

Name

Bit#

Buffer

Function

RB0/INT0

bit0

TTL/ST⁽¹⁾Input/output pin or external interrupt input0.

Internal software programmable weak pull-up.

RB1/INT1

RB2/INT2

RB3

bit1

bit2

bit3

bit4

bit5

TTL/ST⁽¹⁾Input/output pin or external interrupt input1.

Internal software programmable weak pull-up.

TTL/ST⁽¹⁾Input/output pin or external interrupt input2.

Internal software programmable weak pull-up.

TTL

Input/output pin.

Internal software programmable weak pull-up.

RB4

TTL

Input/output pin (with interrupt-on-change).

Internal software programmable weak pull-up.

RB5/PGM⁽⁴⁾

TTL/ST⁽²⁾Input/output pin (with interrupt-on-change).

Internal software programmable weak pull-up.

Low voltage ICSP enable pin.

RB6/PGC

RB7/PGD

bit6

bit7

TTL/ST⁽²⁾Input/output pin (with interrupt-on-change).

Internal software programmable weak pull-up.

Serial programming clock.

TTL/ST⁽²⁾Input/output pin (with interrupt-on-change).

Internal software programmable weak pull-up.

Serial programming data.

Legend:

TTL = TTL input, ST = Schmitt Trigger input

Note 1: This buffer is a Schmitt Trigger input when configured as the external interrupt.

2: This buffer is a Schmitt Trigger input when used in Serial Programming mode.

3: A device configuration bit selects which I/O pin the CCP2 pin is multiplexed on.

4: Low Voltage ICSP Programming (LVP) is enabled by default, which disables the RB5 I/O function. LVP

must be disabled to enable RB5 as an I/O pin and allow maximum compatibility to the other 28-pin and

40-pin mid-range devices.

TABLE 9-4:

SUMMARY OF REGISTERS ASSOCIATED WITH PORTB

Value on

All Other

RESETS

Value on

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

POR, BOR

PORTB

LATB

TRISB

INTCON

RB7

RB6

RB5

RB4

RB3

RB2

RB1

RB0

xxxx xxxx uuuu uuuu

1111 1111 1111 1111

0000 000x 0000 000u

LATB Data Output Register

PORTB Data Direction Register

GIE/

GIEH

PEIE/

GIEL

TMR0IE

INT0IE

RBIE

TMR0IF

INT0IF

RBIF

INTCON2

INTCON3

RBPU INTEDG0 INTEDG1 INTEDG2

INT2IP INT1IP INT2IE

—

INT1IE

TMR0IP

—

INT2IF

RBIP

INT1IF

1111 -1-1 1111 -1-1

11-0 0-00 11-0 0-00

—

Legend: x= unknown, u= unchanged. Shaded cells are not used by PORTB.

DS30485A-page 88

Preliminary

 2002 Microchip Technology Inc.

PIC18FXX39

EXAMPLE 9-3:

INITIALIZING PORTC

9.3

PORTC, TRISC and LATC

Registers

CLRF

PORTC

; Initialize PORTC by

; clearing output

; data latches

PORTC is a 6-bit wide, bi-directional port. The corre-

sponding Data Direction register is TRISC. Setting a

TRISC bit (= 1) will make the corresponding PORTC

pin an input (i.e., put the corresponding output driver in

a High Impedance mode). Clearing a TRISC bit (= 0)

will make the corresponding PORTC pin an output (i.e.,

put the contents of the output latch on the selected pin).

The Data Latch register (LATC) is also memory

mapped. Read-modify-write operations on the LATC

register reads and writes the latched output value for

PORTC.

PORTC is multiplexed with the serial communication

functions (Table 9-5). PORTC pins have Schmitt

Trigger input buffers.

When enabling peripheral functions, care should be

taken in defining TRIS bits for each PORTC pin. Some

peripherals override the TRIS bit to make a pin an out-

put, while other peripherals override the TRIS bit to

make a pin an input. The user should refer to the corre-

sponding peripheral section for the correct TRIS bit

settings.

CLRF

LATC

; Alternate method

; to clear output

; data latches

; Value used to

; initialize data

; direction

; Set RC<3>,RC<0> as inputs,

; RC<5:4> as outputs, and

; RC<7:6> as inputs

MOVLW 0xC9

MOVWF TRISC

PIC18FXX39 devices differ from other PIC18 micro-

controllers in allocation of PORTC pins. For most

PIC18 devices, PORTC is an 8-bit-wide port. For the

PIC18FXX39 family, two of the PORTC pins (RC1 and

RC2) are re-allocated as PWM output only pins for use

with the Motor Control kernel. To maintain pinout com-

patibility with other PICmicro^®devices, the remaining

PORTC pins are assigned in a manner consistent with

other PIC18 devices. For this reason, PORTC has pins

RC0 and RC3 through RC7, but not RC1 and RC2.

To maintain compatibility with PIC18FXX2 devices, the

individual port and corresponding latch and direction

bits for RC1 and RC2 are present in the appropriate

registers, but are not available to the user. To avoid

erratic device operation, the values of these bits should

not be modified.

Note: On a Power-on Reset, these pins are

configured as digital inputs.

The pin override value is not loaded into the TRIS reg-

ister. This allows read-modify-write of the TRIS register,

without concern due to peripheral overrides.

FIGURE 9-7:

PORTC BLOCK DIAGRAM (PERIPHERAL OUTPUT OVERRIDE)

Port/Peripheral Select⁽²⁾

VDD

Peripheral Data Out

RD LATC

Data Bus

0

Data Latch

D

Q

P

WR LATC or

I/O pin⁽¹⁾

WR PORTC

1

CK

Q

TRIS Latch

D

Q

WR TRISC

RD TRISC

Q

CK

N

Schmitt

VSS

Trigger

Peripheral Output

Enable⁽³⁾

D

Q

EN

RD PORTC

Peripheral Data In

Note 1: I/O pins have diode protection to VDD and VSS.

2: Port/Peripheral Select signal selects between port data (input) and peripheral output.

3: Peripheral Output Enable is only active if Peripheral Select is active.

 2002 Microchip Technology Inc.

Preliminary

DS30485A-page 89

PIC18FXX39

TABLE 9-5:

PORTC FUNCTIONS

Name

Bit# Buffer Type

Function

RC0/T13CKI

RC3/SCK/SCL

bit0

bit3

ST

Input/output port pin or Timer1 oscillator output/Timer1 clock input.

RC3 can also be the synchronous serial clock for both SPI and I²C

modes.

RC4/SDI/SDA

RC5/SDO

RC6/TX/CK

bit4

bit5

bit6

ST

RC4 can also be the SPI Data In (SPI mode) or Data I/O (I²C mode).

Input/output port pin or Synchronous Serial Port data output.

Input/output port pin, Addressable USART Asynchronous Transmit, or

Addressable USART Synchronous Clock.

RC7/RX/DT

bit7

ST

Input/output port pin, Addressable USART Asynchronous Receive, or

Addressable USART Synchronous Data.

Legend: ST = Schmitt Trigger input

TABLE 9-6:

SUMMARY OF REGISTERS ASSOCIATED WITH PORTC

Value on

All Other

RESETS

Value on

POR, BOR

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

PORTC

LATC

RC7

LATC7

RC6

LATC6

RC5

LATC5

RC4

LATC4

RC3

LATC3

*

RC0

LATC0

xxxx xxxx uuuu uuuu

TRISC

TRISC7 TRISC6 TRISC5 TRISC4 TRISC3

TRISC0 1111 1111 1111 1111

Legend: x= unknown, u= unchanged. Shaded cells are not used by PORTC.

Reserved bits; do not modify.

*

DS30485A-page 90

Preliminary

 2002 Microchip Technology Inc.

PIC18FXX39

FIGURE 9-8:

PORTD BLOCK DIAGRAM

IN I/O PORT MODE

9.4

PORTD, TRISD and LATD

Registers

This section is applicable only to the PIC18F4X39

devices.

RD LATD

PORTD is an 8-bit wide, bi-directional port. The corre-

sponding Data Direction register is TRISD. Setting a

TRISD bit (= 1) will make the corresponding PORTD

pin an input (i.e., put the corresponding output driver in

a High Impedance mode). Clearing a TRISD bit (= 0)

will make the corresponding PORTD pin an output (i.e.,

put the contents of the output latch on the selected pin).

Data

Bus

D

Q

I/O pin⁽¹⁾

WR LATD

or PORTD

CK

Data Latch

D

Q

The Data Latch register (LATD) is also memory

mapped. Read-modify-write operations on the LATD

register reads and writes the latched output value for

PORTD.

PORTD is an 8-bit port with Schmitt Trigger input buff-

ers. Each pin is individually configurable as an input or

output.

WR TRISD

RD TRISD

Schmitt

Trigger

Input

CK

TRIS Latch

Buffer

Q

D

Note: On a Power-on Reset, these pins are

configured as digital inputs.

EN

PORTD can be configured as an 8-bit wide micropro-

cessor port (parallel slave port) by setting control bit

PSPMODE (TRISE<4>). In this mode, the input buffers

are TTL. See Section 9.6 for additional information on

the Parallel Slave Port (PSP).

RD PORTD

Note 1: I/O pins have diode protection to VDD and VSS.

EXAMPLE 9-4:

INITIALIZING PORTD

CLRF

PORTD ; Initialize PORTD by

; clearing output

; data latches

CLRF

LATD

; Alternate method

; to clear output

; data latches

MOVLW 0xCF

; Value used to

; initialize data

; direction

MOVWF TRISD

; Set RD<3:0> as inputs

; RD<5:4> as outputs

; RD<7:6> as inputs

 2002 Microchip Technology Inc.

Preliminary

DS30485A-page 91

PIC18FXX39

TABLE 9-7:

PORTD FUNCTIONS

Name

Bit#

Buffer Type

Function

RD0/PSP0

RD1/PSP1

RD2/PSP2

RD3/PSP3

RD4/PSP4

RD5/PSP5

RD6/PSP6

RD7/PSP7

bit0

bit1

bit2

bit3

bit4

bit5

bit6

bit7

ST/TTL⁽¹⁾

Input/output port pin or parallel slave port bit0.

Input/output port pin or parallel slave port bit1.

Input/output port pin or parallel slave port bit2.

Input/output port pin or parallel slave port bit3.

Input/output port pin or parallel slave port bit4.

Input/output port pin or parallel slave port bit5.

Input/output port pin or parallel slave port bit6.

Input/output port pin or parallel slave port bit7.

Legend: ST = Schmitt Trigger input, TTL = TTL input

Note 1: Input buffers are Schmitt Triggers when in I/O mode and TTL buffers when in Parallel Slave Port mode.

TABLE 9-8:

SUMMARY OF REGISTERS ASSOCIATED WITH PORTD

Value on

All Other

RESETS

Value on

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

POR, BOR

PORTD

LATD

TRISD

TRISE

RD7

RD6

RD5

RD4

RD3

RD2

RD1

RD0

xxxx xxxx

1111 1111

0000 -111

uuuu uuuu

1111 1111

0000 -111

LATD Data Output Register

PORTD Data Direction Register

IBF

OBF

IBOV

PSPMODE

—

PORTE Data Direction bits

Legend: x= unknown, u= unchanged, - = unimplemented, read as '0'. Shaded cells are not used by PORTD.

DS30485A-page 92

Preliminary

 2002 Microchip Technology Inc.

PIC18FXX39

FIGURE 9-9:

PORTEBLOCKDIAGRAM

IN I/O PORT MODE

9.5

PORTE, TRISE and LATE

Registers

This section is only applicable to the PIC18F4X39

devices.

RD LATE

PORTE is a 3-bit wide, bi-directional port. The corre-

sponding Data Direction register is TRISE. Setting a

TRISE bit (= 1) will make the corresponding PORTE pin

an input (i.e., put the corresponding output driver in a

High Impedance mode). Clearing a TRISE bit (= 0) will

make the corresponding PORTE pin an output (i.e., put

the contents of the output latch on the selected pin).

Data

Bus

D

Q

I/O pin⁽¹⁾

WR LATE

or PORTE

CK

Data Latch

D

Q

The Data Latch register (LATE) is also memory

mapped. Read-modify-write operations on the LATE

register reads and writes the latched output value for

PORTE.

WR TRISE

Schmitt

Trigger

Input

CK

TRIS Latch

Buffer

PORTE has three pins (RE0/AN5/RD, RE1/AN6/WR

and RE2/AN7/CS) which are individually configurable

as inputs or outputs. These pins have Schmitt Trigger

input buffers.

RD TRISE

Q

D

Register 9-1 shows the TRISE register, which also

controls the parallel slave port operation.

EN

PORTE pins are multiplexed with analog inputs. When

selected as an analog input, these pins will read as '0's.

TRISE controls the direction of the RE pins, even when

they are being used as analog inputs. The user must

make sure to keep the pins configured as inputs when

using them as analog inputs.

RD PORTE

To Analog Converter

Note 1: I/O pins have diode protection to VDD and VSS.

Note: On a Power-on Reset, these pins are

configured as analog inputs.

EXAMPLE 9-5:

INITIALIZING PORTE

; Initialize PORTE by

; clearing output

; data latches

CLRF

PORTE

CLRF

LATE

; Alternate method

; to clear output

; data latches

MOVLW 0x07

; Configure A/D

MOVWF ADCON1 ; for digital inputs

MOVLW 0x05

; Value used to

; initialize data

; direction

MOVWF TRISE

; Set RE<0> as inputs

; RE<1> as outputs

; RE<2> as inputs

 2002 Microchip Technology Inc.

Preliminary

DS30485A-page 93

PIC18FXX39

REGISTER 9-1:

TRISE REGISTER

R-0

IBF

R-0

OBF

R/W-0

IBOV

R/W-0

PSPMODE

U-0

—

R/W-1

TRISE2

R/W-1

TRISE1

R/W-1

TRISE0

bit 7

bit 0

bit 7

bit 6

bit 5

IBF: Input Buffer Full Status bit

1= A word has been received and waiting to be read by the CPU

0= No word has been received

OBF: Output Buffer Full Status bit

1= The output buffer still holds a previously written word

0= The output buffer has been read

IBOV: Input Buffer Overflow Detect bit (in Microprocessor mode)

1= A write occurred when a previously input word has not been read

(must be cleared in software)

0= No overflow occurred

bit 4

PSPMODE: Parallel Slave Port Mode Select bit

1= Parallel Slave Port mode

0= General Purpose I/O mode

bit 3

bit 2

Unimplemented: Read as '0'

TRISE2: RE2 Direction Control bit

1= Input

0= Output

bit 1

bit 0

TRISE1: RE1 Direction Control bit

1= Input

0= Output

TRISE0: RE0 Direction Control bit

1= Input

0= Output

Legend:

R = Readable bit

- n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

DS30485A-page 94

Preliminary

 2002 Microchip Technology Inc.

PIC18FXX39

TABLE 9-9:

Name

PORTE FUNCTIONS

Bit#

Buffer Type

Function

Input/output port pin or analog input or read control input in Parallel

Slave Port mode

For RD (PSP mode):

1= Not a read operation

0= Read operation. Reads PORTD register (if chip selected).

Input/output port pin or analog input or write control input in Parallel

Slave Port mode

For WR (PSP mode):

1= Not a write operation

0= Write operation. Writes PORTD register (if chip selected).

Input/output port pin or analog input or chip select control input in

Parallel Slave Port mode

RE0/AN5/RD

RE1/AN6/WR

RE2/AN7/CS

bit0

ST/TTL⁽¹⁾

bit1

bit2

ST/TTL⁽¹⁾

For CS (PSP mode):

1= Device is not selected

0= Device is selected

Legend: ST = Schmitt Trigger input, TTL = TTL input

Note 1: Input buffers are Schmitt Triggers when in I/O mode and TTL buffers when in Parallel Slave Port mode.

TABLE 9-10: SUMMARY OF REGISTERS ASSOCIATED WITH PORTE

Value on

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

All Other

RESETS

POR, BOR

PORTE

LATE

TRISE

ADCON1

—

IBF

—

OBF

ADCS2

—

IBOV

—

RE2

RE1

RE0

---- -000 ---- -000

---- -xxx ---- -uuu

—

PSPMODE

—

LATE Data Output Register

PORTE Data Direction bits

0000 -111 0000 -111

ADFM

PCFG3 PCFG2

PCFG1

PCFG0 00-- 0000 00-- 0000

Legend: x= unknown, u= unchanged, - = unimplemented, read as '0'. Shaded cells are not used by PORTE.

 2002 Microchip Technology Inc.

Preliminary

DS30485A-page 95

PIC18FXX39

FIGURE 9-10:

PORTD AND PORTE

BLOCK DIAGRAM

(PARALLEL SLAVE

PORT)

9.6

Parallel Slave Port

The Parallel Slave Port is implemented on the 40-pin

devices only (PIC18F4X39).

PORTD also operates as an 8-bit wide Parallel Slave

Port, or microprocessor port, when control bit

PSPMODE (TRISE<4>) is set. It is asynchronously

readable and writable by the external world through RD

control input pin, RE0/AN5/RD and WR control input

pin, RE1/AN6/WR.

Data Bus

D

Q

RDx

WR LATD

or

CK

Data Latch

PORTD

TTL

The PSP can directly interface to an 8-bit microproces-

sor data bus. The external microprocessor can read or

write the PORTD latch as an 8-bit latch. Setting bit

PSPMODE enables port pin RE0/AN5/RD to be the RD

input, RE1/AN6/WR to be the WR input and RE2/AN7/

CS to be the CS (chip select) input. For this functional-

ity, the corresponding data direction bits of the TRISE

register (TRISE<2:0>) must be configured as inputs

(set). The A/D port configuration bits, PCFG2:PCFG0

(ADCON1<2:0>), must be set, which will configure pins

RE2:RE0 as digital I/O.

Q

D

RD PORTD

EN

TRIS Latch

RD LATD

One bit of PORTD

A write to the PSP occurs when both the CS and WR

lines are first detected low. A read from the PSP occurs

when both the CS and RD lines are first detected low.

Set Interrupt Flag

PSPIF (PIR1<7>)

The PORTE I/O pins become control inputs for the

microprocessor port when bit PSPMODE (TRISE<4>)

is set. In this mode, the user must make sure that the

TRISE<2:0> bits are set (pins are configured as digital

inputs), and the ADCON1 is configured for digital I/O.

In this mode, the input buffers are TTL.

Read

RD

CS

TTL

Chip Select

TTL

Write

WR

TTL

Note: I/O pin has protection diodes to VDD and VSS.

FIGURE 9-11:

PARALLEL SLAVE PORT WRITE WAVEFORMS

Q1

Q2

Q3

Q4

Q1

Q2

Q3

Q4

Q1

Q2

Q3

Q4

CS

WR

RD

PORTD<7:0>

IBF

OBF

PSPIF

DS30485A-page 96

Preliminary

 2002 Microchip Technology Inc.

PIC18FXX39

FIGURE 9-12:

PARALLEL SLAVE PORT READ WAVEFORMS

Q1

Q2

Q3

Q4

Q1

Q2

Q3

Q4

Q1

Q2

Q3

Q4

CS

WR

RD

PORTD<7:0>

IBF

OBF

PSPIF

TABLE 9-11: REGISTERS ASSOCIATED WITH PARALLEL SLAVE PORT

Value on

All Other

RESETS

Value on

POR, BOR

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

PORTD

LATD

TRISD

PORTE

LATE

Port Data Latch when written; Port pins when read

LATD Data Output bits

PORTD Data Direction bits

xxxx xxxx uuuu uuuu

1111 1111 1111 1111

---- -000 ---- -000

---- -xxx ---- -uuu

0000 -111 0000 -111

0000 000x 0000 000u

—

RE2

RE1

RE0

LATE Data Output bits

PORTE Data Direction bits

TMR0IF

TRISE

INTCON

IBF

GIE/

GIEH

OBF

PEIE/

GIEL

IBOV

TMR0IF

PSPMODE

INT0IE

—

RBIE

INT0IF

RBIF

PIR1

PIE1

IPR1

ADCON1

PSPIF

PSPIE

PSPIP

ADFM

ADIF

ADIE

ADIP

RCIF

RCIE

RCIP

—

TXIF

TXIE

TXIP

—

SSPIF

SSPIE

SSPIP

—

TMR2IF

TMR1IF 0000 0000 0000 0000

TMR2IE TMR1IE 0000 0000 0000 0000

TMR2IP TMR1IP 0000 0000 0000 0000

PCFG1

ADCS2

PCFG3 PCFG2

PCFG0

00-- 0000 00-- 0000

Legend: x= unknown, u= unchanged, - = unimplemented, read as '0'. Shaded cells are not used by the Parallel Slave Port.

 2002 Microchip Technology Inc.

Preliminary

DS30485A-page 97

PIC18FXX39

NOTES:

DS30485A-page 98

Preliminary

 2002 Microchip Technology Inc.

PIC18FXX39

Figure 10-1 shows a simplified block diagram of the

Timer0 module in 8-bit mode and Figure 10-2 shows a

simplified block diagram of the Timer0 module in 16-bit

mode.

The T0CON register (Register 10-1) is a readable and

writable register that controls all the aspects of Timer0,

including the prescale selection.

10.0 TIMER0 MODULE

The Timer0 module has the following features:

• Software selectable as an 8-bit or 16-bit

timer/counter

• Readable and writable

• Dedicated 8-bit software programmable prescaler

• Clock source selectable to be external or internal

• Interrupt-on-overflow from FFh to 00h in 8-bit

mode and FFFFh to 0000h in 16-bit mode

• Edge select for external clock

REGISTER 10-1: T0CON: TIMER0 CONTROL REGISTER

R/W-1

TMR0ON

bit 7

R/W-1

T08BIT

R/W-1

T0CS

R/W-1

T0SE

R/W-1

PSA

R/W-1

T0PS2

R/W-1

T0PS1

R/W-1

T0PS0

bit 0

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2-0

TMR0ON: Timer0 On/Off Control bit

1= Enables Timer0

0= Stops Timer0

T08BIT: Timer0 8-bit/16-bit Control bit

1= Timer0 is configured as an 8-bit timer/counter

0= Timer0 is configured as a 16-bit timer/counter

T0CS: Timer0 Clock Source Select bit

1= Transition on T0CKI pin

0= Internal instruction cycle clock (CLKO)

T0SE: Timer0 Source Edge Select bit

1= Increment on high-to-low transition on T0CKI pin

0= Increment on low-to-high transition on T0CKI pin

PSA: Timer0 Prescaler Assignment bit

1= TImer0 prescaler is NOT assigned. Timer0 clock input bypasses prescaler.

0= Timer0 prescaler is assigned. Timer0 clock input comes from prescaler output.

T0PS2:T0PS0: Timer0 Prescaler Select bits

111= 1:256 prescale value

110= 1:128 prescale value

101= 1:64 prescale value

100= 1:32 prescale value

011= 1:16 prescale value

010= 1:8 prescale value

001= 1:4 prescale value

000= 1:2 prescale value

Legend:

R = Readable bit

- n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

 2002 Microchip Technology Inc.

Preliminary

DS30485A-page 99

PIC18FXX39

FIGURE 10-1:

TIMER0 BLOCK DIAGRAM IN 8-BIT MODE

Data Bus

TMR0L

FOSC/4

0

1

8

1

Sync with

Internal

Clocks

RA4/T0CKI pin

Programmable

Prescaler

0

(2 TCY delay)

T0SE

3

PSA

Set Interrupt

Flag bit TMR0IF

on Overflow

T0PS2, T0PS1, T0PS0

T0CS

Note: Upon RESET, Timer0 is enabled in 8-bit mode with clock input from T0CKI max. prescale.

FIGURE 10-2:

TIMER0 BLOCK DIAGRAM IN 16-BIT MODE

FOSC/4

0

1

Sync with

Set Interrupt

Flag bit TMR0IF

on Overflow

TMR0

1

Internal

Clocks

TMR0L

High Byte

Programmable

Prescaler

T0CKI pin

0

8

(2 TCY delay)

T0SE

Read TMR0L

Write TMR0L

3

T0CS

PSA

T0PS2, T0PS1, T0PS0

8

TMR0H

8

Data Bus<7:0>

Note: Upon RESET, Timer0 is enabled in 8-bit mode with clock input from T0CKI max. prescale.

DS30485A-page 100

Preliminary

 2002 Microchip Technology Inc.

PIC18FXX39

10.2.1

SWITCHING PRESCALER

ASSIGNMENT

10.1 Timer0 Operation

Timer0 can operate as a timer or as a counter.

The prescaler assignment is fully under software

control; it can be changed “on-the-fly” during program

execution.

Timer mode is selected by clearing the T0CS bit. In

Timer mode, the Timer0 module will increment every

instruction cycle (without prescaler). If the TMR0L reg-

ister is written, the increment is inhibited for the follow-

ing two instruction cycles. The user can work around

this by writing an adjusted value to the TMR0L register.

Counter mode is selected by setting the T0CS bit. In

Counter mode, Timer0 will increment, either on every

rising or falling edge of pin RA4/T0CKI. The increment-

ing edge is determined by the Timer0 Source Edge

Select bit (T0SE). Clearing the T0SE bit selects the ris-

ing edge. Restrictions on the external clock input are

discussed below.

10.3 Timer0 Interrupt

The TMR0 interrupt is generated when the TMR0 reg-

ister overflows from FFh to 00h in 8-bit mode, or FFFFh

to 0000h in 16-bit mode. This overflow sets the TMR0IF

bit. The interrupt can be masked by clearing the

TMR0IE bit. The TMR0IE bit must be cleared in soft-

ware by the Timer0 module Interrupt Service Routine

before re-enabling this interrupt. The TMR0 interrupt

cannot awaken the processor from SLEEP, since the

timer is shut-off during SLEEP.

When an external clock input is used for Timer0, it must

meet certain requirements. The requirements ensure

the external clock can be synchronized with the internal

phase clock (TOSC). Also, there is a delay in the actual

incrementing of Timer0 after synchronization.

10.4 16-bit Mode Timer Reads and

Writes

TMR0H is not the high byte of the timer/counter in

16-bit mode, but is actually a buffered version of the

high byte of Timer0 (see Figure 10-2). The high byte of

the Timer0 counter/timer is not directly readable nor

writable. TMR0H is updated with the contents of the

high byte of Timer0 during a read of TMR0L. This pro-

vides the ability to read all 16 bits of Timer0 without

having to verify that the read of the high and low byte

were valid, due to a rollover between successive reads

of the high and low byte.

A write to the high byte of Timer0 must also take place

through the TMR0H buffer register. Timer0 high byte is

updated with the contents of TMR0H when a write

occurs to TMR0L. This allows all 16 bits of Timer0 to be

updated at once.

10.2 Prescaler

An 8-bit counter is available as a prescaler for the Timer0

module. The prescaler is not readable or writable.

The PSA and T0PS2:T0PS0 bits determine the

prescaler assignment and prescale ratio.

Clearing bit PSA will assign the prescaler to the Timer0

module. When the prescaler is assigned to the Timer0

module, prescale values in power-of-2 increments,

from 1:2 through 1:256, are selectable.

When assigned to the Timer0 module, all instructions

writing to the TMR0L register (e.g., CLRF TMR0,

MOVWF TMR0, BSF TMR0,etc.) will clear the prescaler

count.

Note: Writing to TMR0L when the prescaler is

assigned to Timer0 will clear the prescaler

count, but will not change the prescaler

assignment.

TABLE 10-1: REGISTERS ASSOCIATED WITH TIMER0

Value on

All Other

RESETS

Value on

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

POR, BOR

TMR0L

TMR0H

INTCON

T0CON

TRISA

Timer0 Module Low Byte Register

Timer0 Module High Byte Register

GIE/GIEH PEIE/GIEL TMR0IE INT0IE

xxxx xxxx uuuu uuuu

0000 0000 0000 0000

0000 000x 0000 000u

1111 1111 1111 1111

-111 1111 -111 1111

RBIE

PSA

TMR0IF INT0IF

T0PS2 T0PS1

RBIF

T0PS0

TMR0ON

—

T08BIT

T0CS

T0SE

PORTA Data Direction Register

Legend: x= unknown, u= unchanged, - = unimplemented locations read as '0'. Shaded cells are not used by Timer0.

 2002 Microchip Technology Inc.

Preliminary

DS30485A-page 101

PIC18FXX39

NOTES:

DS30485A-page 102

Preliminary

 2002 Microchip Technology Inc.

PIC18FXX39

Figure 11-1 is a simplified block diagram of the Timer1

module.

Register 11-1 details the Timer1 control register, which

sets the Operating mode of the Timer1 module. Timer1

can be enabled or disabled by setting or clearing

control bit TMR1ON (T1CON<0>).

11.0 TIMER1 MODULE

The Timer1 module timer/counter has the following

features:

• 16-bit timer/counter

(two 8-bit registers, TMR1H and TMR1L)

• Readable and writable (both registers)

• Internal or external clock select

• Interrupt-on-overflow from FFFFh to 0000h

REGISTER 11-1: T1CON: TIMER1 CONTROL REGISTER

R/W-0

RD16

bit 7

U-0

—

R/W-0

T1CKPS1 T1CKPS0

R/W-0

U-0

—

R/W-0

T1SYNC TMR1CS TMR1ON

bit 0

bit 7

RD16: 16-bit Read/Write Mode Enable bit

1= Enables register read/write of Timer1 in one 16-bit operation

0= Enables register read/write of Timer1 in two 8-bit operations

bit 6

Unimplemented: Read as '0'

bit 5-4

T1CKPS1:T1CKPS0: Timer1 Input Clock Prescale Select bits

11= 1:8 Prescale value

10= 1:4 Prescale value

01= 1:2 Prescale value

00= 1:1 Prescale value

bit 3

bit 2

Unimplemented: Maintain as '0'

T1SYNC: Timer1 External Clock Input Synchronization Select bit

When TMR1CS = 1:

1= Do not synchronize external clock input

0= Synchronize external clock input

When TMR1CS = 0:

This bit is ignored. Timer1 uses the internal clock when TMR1CS = 0.

bit 1

bit 0

TMR1CS: Timer1 Clock Source Select bit

1= External clock from pin RC0/T13CKI (on the rising edge)

0= Internal clock (FOSC/4)

TMR1ON: Timer1 On bit

1= Enables Timer1

0= Stops Timer1

Legend:

R = Readable bit

- n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

 2002 Microchip Technology Inc.

Preliminary

DS30485A-page 103

PIC18FXX39

The Operating mode is determined by the clock select

bit, TMR1CS (T1CON<1>). When TMR1CS = 0,

Timer1 increments every instruction cycle. When

TMR1CS = 1, Timer1 increments on every rising edge

of the external clock input.

11.1 Timer1 Operation

Timer1 can operate in one of these modes:

• As a timer

• As a synchronous counter

• As an asynchronous counter

FIGURE 11-1:

TIMER1 BLOCK DIAGRAM

TMR1IF

Overflow

Interrupt

Flag bit

Synchronized

Clock Input

TMR1

TMR1L

0

TMR1H

1

TMR1ON

On/Off

T1SYNC

1

T13CKI

Synchronize

det

Prescaler

1, 2, 4, 8

FOSC/4

Internal

Clock

0

2

SLEEP Input

T1CKPS1:T1CKPS0

TMR1CS

FIGURE 11-2:

TIMER1 BLOCK DIAGRAM: 16-BIT READ/WRITE MODE

Data Bus<7:0>

8

TMR1H

8

Write TMR1L

Read TMR1L

TMR1IF

Overflow

Interrupt

Synchronized

Clock Input

TMR1

8

0

Timer 1

TMR1L

Flag bit

High Byte

1

TMR1ON

on/off

T1SYNC

T13CKI

1

Synchronize

det

Prescaler

1, 2, 4, 8

FOSC/4

Internal

0

Clock

2

SLEEP Input

TMR1CS

T1CKPS1:T1CKPS0

DS30485A-page 104

Preliminary

 2002 Microchip Technology Inc.

PIC18FXX39

the user with the ability to accurately read all 16-bits of

Timer1 without having to determine whether a read of

the high byte, followed by a read of the low byte is valid,

due to a rollover between reads.

A write to the high byte of Timer1 must also take place

through the TMR1H buffer register. Timer1 high byte is

updated with the contents of TMR1H when a write

occurs to TMR1L. This allows a user to write all 16 bits

to both the high and low bytes of Timer1 at once.

11.2 Timer1 Interrupt

The TMR1 register pair (TMR1H:TMR1L) increments

from 0000h to FFFFh and rolls over to 0000h. The

TMR1 interrupt, if enabled, is generated on overflow,

which is latched in interrupt flag bit TMR1IF (PIR1<0>).

This interrupt can be enabled/disabled by

setting/clearing TMR1 interrupt enable bit, TMR1IE

(PIE1<0>).

11.3 Timer1 16-bit Read/Write Mode

The high byte of Timer1 is not directly readable or writ-

able in this mode. All reads and writes must take place

through the Timer1 high byte buffer register. Writes to

TMR1H do not clear the Timer1 prescaler. The

prescaler is only cleared on writes to TMR1L.

Timer1 can be configured for 16-bit reads and writes

(see Figure 11-2). When the RD16 control bit

(T1CON<7>) is set, the address for TMR1H is mapped

to a buffer register for the high byte of Timer1. A read

from TMR1L will load the contents of the high byte of

Timer1 into the Timer1 high byte buffer. This provides

TABLE 11-1: REGISTERS ASSOCIATED WITH TIMER1 AS A TIMER/COUNTER

Value on

All Other

RESETS

Value on

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

POR, BOR

INTCON GIE/GIEH PEIE/GIEL TMR0IE

INT0IE

TXIF

RBIE

SSPIF

SSPIE

SSPIP

TMR0IF

INT0IF

RBIF

0000 000x 0000 000u

(1)

—

PIR1

PSPIF

PSPIE

PSPIP

ADIF

ADIE

ADIP

RCIF

RCIE

RCIP

TMR2IF TMR1IF 0000 0000 0000 0000

TMR2IE TMR1IE 0000 0000 0000 0000

TMR2IP TMR1IP 0000 0000 0000 0000

xxxx xxxx uuuu uuuu

(1)

PIE1

TXIE

TXIP

IPR1

TMR1L

Holding Register for the Least Significant Byte of the 16-bit TMR1 Register

TMR1H Holding Register for the Most Significant Byte of the 16-bit TMR1 Register

xxxx xxxx uuuu uuuu

T1CON RD16 T1CKPS1 T1CKPS0 T1SYNC TMR1CS TMR1ON 0-00 0000 u-uu uuuu

—

Legend: x= unknown, u= unchanged, - = unimplemented, read as '0'. Shaded cells are not used by the Timer1 module.

Note 1: The PSPIF, PSPIE and PSPIP bits are reserved on the PIC18F2X39 devices; always maintain these bits clear.

 2002 Microchip Technology Inc.

Preliminary

DS30485A-page 105

PIC18FXX39

NOTES:

DS30485A-page 106

Preliminary

 2002 Microchip Technology Inc.

PIC18FXX39

12.0 TIMER2 MODULE

The Timer2 module is an 8-bit timer with a selectable

8-bit period. It has the following features:

• Input from system clock at FOSC/4 with

programmable input prescaler

• Interrupt on timer-to-period match with

programmable postscaler

The module has three registers: the TMR2 counter, the

PR2 period register, and the T2CON control register.

The general operation of Timer2 is shown in

Figure 12-1.

Note: In PIC18FXX39 devices, Timer2 is used

exclusively as a time-base for the PWM

modules in motor control applications. As

such, it is not available to users as a

resource. Although their locations are

shown on the device data memory maps,

none of the Timer2 registers are directly

accessible. Users should not alter the

values of these registers.

Additional information on the use of Timer2 as a

time-base is available in Section 15.0 (PWM Modules).

FIGURE 12-1:

TIMER2 BLOCK DIAGRAM

Prescaler

1:1, 1:4, 1:16

TMR2

FOSC/4

Output

RESET

(TMR2 = PR2)

Postscaler

1:1 to 1:16

Sets Flag

bit TMR2IF

Comparator

(ProMPT Module)

PR2

(ProMPT Module)

 2002 Microchip Technology Inc.

Preliminary

DS30485A-page 107

PIC18FXX39

NOTES:

DS30485A-page 108

Preliminary

 2002 Microchip Technology Inc.

PIC18FXX39

Figure 13-1 is a simplified block diagram of the Timer3

module.

Register 13-1 shows the Timer1 control register, which

sets the Operating mode of the Timer1 module.

13.0 TIMER3 MODULE

The Timer3 module timer/counter has the following

features:

• 16-bit timer/counter

(two 8-bit registers: TMR3H and TMR3L)

• Readable and writable (both registers)

• Internal or external clock select

• Interrupt-on-overflow from FFFFh to 0000h

REGISTER 13-1: T3CON: TIMER3 CONTROL REGISTER

R/W-0

RD16

bit 7

R/W-0

—

R/W-0

T3CKPS1 T3CKPS0

R/W-0

—

R/W-0

T3SYNC TMR3CS TMR3ON

bit 0

bit 7

RD16: 16-bit Read/Write Mode Enable bit

1= Enables register read/write of Timer3 in one 16-bit operation

0= Enables register read/write of Timer3 in two 8-bit operations

bit 6, 3

bit 5, 4

Unimplemented: Maintain as ‘0’

T3CKPS1:T3CKPS0: Timer3 Input Clock Prescale Select bits

11= 1:8 Prescale value

10= 1:4 Prescale value

01= 1:2 Prescale value

00= 1:1 Prescale value

bit 2

T3SYNC: Timer3 External Clock Input Synchronization Control bit

(Not usable if the system clock comes from Timer1/Timer3)

When TMR3CS = 1:

1= Do not synchronize external clock input

0= Synchronize external clock input

When TMR3CS = 0:

This bit is ignored. Timer3 uses the internal clock when TMR3CS = 0.

bit 1

bit 0

TMR3CS: Timer3 Clock Source Select bit

1= External clock input from T13CKI

(on the rising edge after the first falling edge)

0= Internal clock (FOSC/4)

TMR3ON: Timer3 On bit

1= Enables Timer3

0= Stops Timer3

Legend:

R = Readable bit

- n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

 2002 Microchip Technology Inc.

Preliminary

DS30485A-page 109

PIC18FXX39

The Operating mode is determined by the clock select

bit, TMR3CS (T3CON<1>). When TMR3CS = 0,

Timer3 increments every instruction cycle. When

TMR3CS = 1, Timer3 increments on every rising edge

of the Timer1 external clock input.

13.1 Timer3 Operation

Timer3 can operate in one of these modes:

• As a timer

• As a synchronous counter

• As an asynchronous counter

FIGURE 13-1:

TIMER3 BLOCK DIAGRAM

TMR3IF

Overflow

Interrupt

Synchronized

0

Flag bit

Clock Input

TMR3H

TMR3L

1

TMR3ON

On/Off

T3SYNC

1

T13CKI

Synchronize

det

Prescaler

1, 2, 4, 8

FOSC/4

Internal

Clock

0

2

SLEEP Input

TMR3CS

T3CKPS1:T3CKPS0

FIGURE 13-2:

TIMER3 BLOCK DIAGRAM CONFIGURED IN 16-BIT READ/WRITE MODE

Data Bus<7:0>

8

TMR3H

8

Write TMR3L

Read TMR3L

Synchronized

Clock Input

8

TMR3

Set TMR3IF Flag bit

on Overflow

0

Timer3

TMR3L

High Byte

1

TMR3ON

On/Off

T3SYNC

1

T13CKI

Synchronize

det

Prescaler

1, 2, 4, 8

FOSC/4

Internal

Clock

0

2

SLEEP Input

T3CKPS1:T3CKPS0

To Timer1 Clock Input

TMR3CS

DS30485A-page 110

Preliminary

 2002 Microchip Technology Inc.

PIC18FXX39

(PIR2<1>). This interrupt can be enabled/disabled by

setting/clearing TMR3 interrupt enable bit, TMR3IE

(PIE2<1>).

13.2 Timer3 Interrupt

The TMR3 Register pair (TMR3H:TMR3L) increments

from 0000h to FFFFh and rolls over to 0000h. The

TMR3 Interrupt, if enabled, is generated on overflow,

which is latched in interrupt flag bit, TMR3IF

TABLE 13-1: REGISTERS ASSOCIATED WITH TIMER3 AS A TIMER/COUNTER

Value on

All Other

RESETS

Value on

POR, BOR

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

INTCON

PIR2

PIE2

GIE/GIEH PEIE/GIEL TMR0IE

INT0IE

EEIF

EEIE

EEIP

RBIE

BCLIF

BCLIE

BCLIP

TMR0IF

LVDIF

LVDIE

LVDIP

INT0IF

TMR3IF

TMR3IE

TMR3IP

RBIF

—

0000 000x 0000 000u

---0 0000 ---0 0000

---1 1111 ---1 1111

xxxx xxxx uuuu uuuu

—

IPR2

—

TMR3L

TMR3H

T1CON

T3CON

Holding Register for the Least Significant Byte of the 16-bit TMR3 Register

Holding Register for the Most Significant Byte of the 16-bit TMR3 Register

—

RD16

—

T1CKPS1 T1CKPS0

T3CKPS1 T3CKPS0

T1SYNC TMR1CS TMR1ON 0-00 0000 u-uu uuuu

T3SYNC TMR3CS TMR3ON 0000 0000 uuuu uuuu

Legend: x= unknown, u= unchanged, - = unimplemented, read as '0'. Shaded cells are not used by the Timer1 module.

 2002 Microchip Technology Inc.

Preliminary

DS30485A-page 111

PIC18FXX39

NOTES:

DS30485A-page 112

Preliminary

 2002 Microchip Technology Inc.

PIC18FXX39

ratio, the motor’s speed can be varied with constant

current. Maintaining this constant ratio is the function of

the Motor Control kernel.

14.0 SINGLE PHASE INDUCTION

MOTOR CONTROL KERNEL

The Motor Control kernel of the PIC18FXX39 family

uses Programmable Motor Processor Technology

(ProMPT) to control the speed of a single phase induc-

tion motor, with variable frequency technology. The

controller’s two PWM modules are used to synthesize

a sine wave current through the motor windings. The

kernel provides open loop control for a continuous

frequency range of 15 Hz to 127 Hz.

EQUATION 14-1: KEY RELATIONSHIPS IN

SINGLE PHASE MOTORS

V ∝ φ × ω

(1-1)

or:

V ∝ 2πfφ

(1-2)

V

(1-3)

---

I ∝ φ ∝

f

where: V is applied voltage

I is motor current

14.1 Theory of Operation

The speed of an induction motor is a function of fre-

quency, slip and the number of poles in the motor. They

are related by the equation:

φ is stator flux

f is input frequency

Speed = (F × 120 ⁄ P) – Slip

14.2 Typical Hardware Interface

A block diagram for a recommended single phase

induction motor control using the PIC18FXX39 is

shown in Figure 14-1.

where Speed and Slip are in RPM, F is the frequency of

the input voltage (in Hertz), and P represents the number

of motor poles (for this equation, either 2, 4, 6 or 8).

The single phase AC supply is rectified, using a diode

bridge and filtered, using a capacitor. The PWM out-

puts from the PIC18FXX39 synthesize the AC to drive

the motor from this DC bus by switching Insulated Gate

Bipolar Transistors (IGBTs) on and off. The IGBT gate

driver converts the TTL level of PWMs to the required

IGBT gate voltage level, and supplies the gate charging

current when the IGBT turns on.

The I/O ports of the microcontroller can be used for the

external logic controls. The A/D channels can be used

for monitoring the DC bus voltage and motor current; a

potentiometer can also be connected to one of these

channels to provide a variable frequency reference for

the motor.

For the purpose of this discussion, slip is assumed to

be constant across the motor’s useful operating range.

Since the rated speed is based on the number of poles

(which is fixed at the time of manufacture), this leaves

changing the frequency of the supplied voltage as the

only way to vary the motor’s speed. When the fre-

quency controlling a motor is reduced, however, its

impedance is also reduced, resulting in a higher motor

current draw.

It can be shown that the voltage applied to the motor is

proportional to both the frequency and the current

(Equation 14-1). So to keep the current constant at, or

below the Full Load Amp rating, the RMS voltage to the

motor must be reduced as the frequency is reduced. By

varying the supply voltage and frequency at a constant

FIGURE 14-1:

TYPICAL MOTOR CONTROL SYSTEM USING THE PIC18FXX39

+

+15V

+5V

Rectifier

L

N

G

Single Phase

AC Input

Power

Supply

-

GND

MOV

Voltage

Monitor

A/D

Gate

Drives

PWM1

I/OPorts

A/D

M1

M2

G

Digital

PWM2

A/D

IGBT

Motor

PIC18FXX39

Driver

I/O Interface

IGBT

H-Bridge

Analog

Current

Monitor

 2002 Microchip Technology Inc.

Preliminary

DS30485A-page 113

PIC18FXX39

Acceleration rate: The rate of increase of motor

speed, achieved by ramping up the supply frequency.

Expressed in Hz/s.

Deceleration rate: The rate of decrease of motor

speed, achieved by ramping down the supply

frequency. Expressed in Hz/s.

Boost: The mode for starting a stopped motor by vary-

ing the supply current frequency and modulation until

steady state speed is reached. Boost is defined in

terms of a frequency, a starting and ending modulation,

and a time interval for the transition between the two.

14.3 Software Interface

A sine table, stored in the ProMPT kernel, is used as

the basis for synthesizing the DC bus using the PWM

modules. The table values are accessed in sequence

and scaled based on the frequency or the speed at

which the motor is intended to run. The intended fre-

quency input can be from an A/D channel or a digital

value.

Parameters in the ProMPT modules can be accessed

using the pre-defined Application Program Interface

(API) methods. A list of the APIs is given in

Section 14.3.3.

PWM Frequency: The sampling rate (in kHz) at which

the PWM module operates.

For example, to run the motor at 40 Hz, the user would

invoke the PromMPT_SetFrequencyAPI:

i = ProMPT_SetFrequency(40);

FIGURE 14-2:

DEFAULT V/F CURVE FOR

THE ProMPT KERNEL

where iis an unsigned character variable. In this case,

if i= 0 on return, the command has been successfully

executed. If the frequency input is out of range, or if

there is an error in setting the frequency, iis returned

with a value of FFh.

Similarly, to check the frequency set by the ProMPT

kernel, use the ProMPT_GetFrequencyAPI:

150

V_ratedof motor

should equal

at 100% modulation

125

100

75

50

25

0

i = ProMPT_GetFrequency(void);

where iis an unsigned character variable. Upon return

from the ProMPT kernel, i will contain the frequency

value in the ProMPT kernel.

f_ratedof motor

should equal f at

100% modulation

14.3.1

THE V/F CURVE

0

20

40

60

80

100

120

140

The ProMPT kernel contains a default V/F curve stored

in memory. The default curve is linear, as shown in

Figure 14-2. Table 14-1 shows the data points used to

construct the curve.

Input Frequency (Hz)

TABLE 14-1: DATA POINTS FOR THE

DEFAULT V/F CURVE

Users may require a different V/F curve for their appli-

cation, based on the load on the motor, or based on the

characteristics of the motor used. The curve can be

changed in the application program using the API

method SetVFCurve(X,Y),where Xis the frequency

and Yis the level of modulation of the DC bus voltage.

As a rule, in customizing the curve, the input frequency

corresponding to the point on the V/F curve that gives

100% modulation should match the motor’s rated fre-

quency. Similarly, full modulation should occur at the

motor’s rated input voltage. (See Figure 14-2 for

details.)

Frequency (Hz)

% Modulation

0

8

0

14

28

42

57

71

86

16

24

32

40

48

56

64

72

80

88

96

104

112

120

128

100

110

133

Examples of the characteristics for V/F curves for typi-

cal motor applications are shown in Section 14-2

(page 115).

14.3.2

PARAMETERS DEFINED BY THE

ProMPT API METHODS

Frequency: The frequency (in Hz) of the supply

current for steady state motor operation.

Modulation: The level of modulation (in percentage)

applied to the DC supply voltage by the PWM through

the H-bridge to produce AC drive current.

DS30485A-page 114

Preliminary

 2002 Microchip Technology Inc.

PIC18FXX39

TABLE 14-2: ProMPT OUTPUT CHARACTERISTICS FOR VARIOUS V/F CURVES

Motor Type:

Shaded Pole Blower

115V

Rated Voltage:

Full Load Current:

Rated Frequency:

Rated Speed:

3.5/3.25A

50/60 Hz

1570 RPM

1/10 HP

Rated Power:

Measured

Output

Measured

Motor Speed

Output

Input

Measured

Deviation (%)

Frequency (Hz) Frequency (Hz)

(RPM)

Voltage (RMS)

Current (A)

Linear V/F Curve (Pre-programmed)

15

18

20

25

30

35

40

45

50

55

60

65

70

75

14.8

17.8

19.8

24.7

29.7

34.6

39.6

44.5

49.5

54.4

59.4

64.3

69.3

74.2

1.3

1.1

1.0

1.2

1.0

1.1

1.0

1.1

1.0

1.1

1.0

1.1

1.0

1.1

22.8

28.2

33.5

42.0

52.6

62.0

72.3

81.3

90.7

99.6

107.8

112.3

111.5

111.3

1.59

1.75

1.92

2.08

2.26

2.40

2.57

2.70

2.79

2.96

3.10

3.26

3.53

3.69

348

445

505

651

794

926

1060

1185

1305

1421

1536

1565

1450

1070

Pump V/F Curve

15

18

20

25

30

35

40

45

50

55

60

65

70

75

14.8

17.8

19.8

24.7

29.7

34.6

39.6

44.5

49.5

54.4

59.4

64.3

69.3

74.3

1.3

1.1

1.0

1.2

1.0

1.1

1.0

1.1

1.0

1.1

1.0

1.1

1.0

0.9

15.0

18.4

21.4

29.5

36.6

44.7

53.9

62.9

73.4

88.2

102.0

108.8

108.0

109.1

1.00

1.10

1.23

1.44

1.60

1.79

2.01

2.21

2.47

2.79

3.05

3.25

3.50

3.58

3.5

396

456

602

722

852

979

1092

1221

1367

1488

1538

1385

994

 2002 Microchip Technology Inc.

Preliminary

DS30485A-page 115

PIC18FXX39

TABLE 14-2: ProMPT OUTPUT CHARACTERISTICS FOR VARIOUS V/F CURVES (CONTINUED)

Motor Type:

Shaded Pole Blower

115V

Rated Voltage:

Full Load Current:

Rated Frequency:

Rated Speed:

3.5/3.25A

50/60 Hz

1570 RPM

1/10 HP

Rated Power:

Measured

Output

Measured

Output

Input

Measured

Motor Speed

(RPM)

Deviation (%)

Frequency (Hz) Frequency (Hz)

Voltage (RMS)

Current (A)

Strong Fan V/F Curve

15

18

20

25

30

35

40

45

50

55

60

65

70

75

14.8

17.8

19.8

24.7

29.7

34.6

39.6

44.5

49.5

54.4

59.4

64.3

69.3

74.2

1.3%

1.1%

1.0%

1.2%

1.0%

1.1%

1.0%

1.1%

1.0%

1.1%

1.0%

1.1%

1.0%

1.1%

6.2

8.5

0.45

0.57

0.69

0.94

1.17

1.43

1.66

1.96

2.26

2.56

2.94

3.24

3.49

3.58

100

193

264

408

538

654

720

888

1040

1162

1410

1534

1401

1016

11.3

17.3

24.0

31.5

38.9

49.5

61.6

73.5

93.8

106.8

108.9

109.5

Weak Fan V/F Curve

15

18

20

25

30

35

40

45

50

55

60

65

70

75

14.8

17.8

19.8

24.7

29.7

34.6

39.6

44.5

49.4

54.4

59.4

64.3

69.3

74.2

1.3%

1.1%

1.0%

1.2%

1.0%

1.1%

1.0%

1.1%

1.2%

1.1%

1.0%

1.1%

1.0%

1.1%

14.9

19.1

23.5

32.8

41.2

51.5

62.2

73.7

83.0

92.5

103.5

108.0

107.8

108.1

0.99

1.15

1.31

1.56

1.79

2.01

2.23

2.47

2.64

2.86

3.06

3.22

3.50

3.55

306

405

475

619

759

893

1018

1155

1277

1397

1498

1500

1348

949

DS30485A-page 116

Preliminary

 2002 Microchip Technology Inc.

PIC18FXX39

14.3.3

ProMPT API METHODS

There are 27 separate API methods for the ProMPT kernel:

Note: The operation of the Motor Control kernel and its APIs is based on an assumed clock frequency of 20 MHz.

Changing the oscillator frequency will change the timing used in the Motor Control kernel accordingly. To

achieve the best results in motor control applications, a clock frequency of 20 MHz is highly recommended.

void ProMPT_ClearTick(void)

Resources used: 0 stack levels

Description: This function clears the Tick (62.5 ms) timer flag returned by ProMPT_tick(). This function must be

called by any routine that is used for timing purposes.

void ProMPT_DisableBoostMode(void)

Resources used: 0 stack levels

Description: This function disables the Boost mode logic. This method should be called before changing any of the

Boost mode parameters.

void ProMPT_EnableBoostMode(void)

Resources used: 0 stack levels

Description: This function enables the Boost mode logic. Boost mode is entered when a stopped drive is commanded

to start. The drive will immediately go to Boost Frequency and ramp from Start Modulation to End Modulation over the

time period, Boost Time.

unsigned char ProMPT_GetAccelRate(void)

Resources used: 1 stack level

Range of values: 0 to 255

Description: Returns the current Acceleration Rate in Hz/second.

unsigned char ProMPT_GetBoostEndModulation(void)

Resources used: 1 stack level

Range of values: 0 to 200

Description: Returns the current End Modulation (in %) used in the boost logic.

unsigned char ProMPT_GetBoostFrequency(void)

Resources used: 1 stack level

Range of values: 0 to 127

Description: Returns the current Boost Frequency in Hz.

unsigned char ProMPT_GetBoostStartModulation(void)

Resources used: 1 stack level

Range of values: 0 to BoostEndModulation

Description: Returns the Start Modulation (in %) used in the Boost logic.

 2002 Microchip Technology Inc.

Preliminary

DS30485A-page 117

PIC18FXX39

unsigned char ProMPT_GetBoostTime()

Resources used: 1 stack level

Range of values: 0 to 255

Description: Returns the time in seconds for Boost mode.

unsigned char ProMPT_GetDecelRate()

Resources used: 1 stack level

Range of values: 0 to 255

Description: Returns the current deceleration rate in Hz/second.

unsigned char ProMPT_GetFrequency(void)

Resources used: 1 stack level

Range of values: 0 to 127

Description: Returns the current output frequency in Hz. This may not be the frequency commanded due to Boost or

Accel/Decel logic.

unsigned char ProMPT_GetModulation(void)

Resources used: Hardware Multiplier; 1 stack level

Range of values: 0 to 200

Description: Returns the current output modulation in %.

unsigned char ProMPT_GetParameter(unsigned char parameter)

Resources used: 1 stack level

Description: In addition to its pre-defined API methods, the ProMPT kernel allows the user to custom define up to 16

functions for control or communication purposes not covered by the ProMPT APIs. These parameters are used to com-

municate with motor control GUI evaluation tools, such as Microchip’s DashDriveMP^TM. This method returns the current

value of any one of the parameters.

unsigned char ProMPT_GetVFCurve(unsigned char point)

Resources used: Hardware Multiplier; 1 stack level

Description: This function returns one of the 17 modulation values (in %) of the V/F curve. Each point represents a

frequency increment of 8 Hz, ranging from point 0 (0 Hz) to point 16 (128 Hz).

void ProMPT_Init(unsigned char PWMfrequency)

Resources used: 64 Bytes RAM; Timer2; PWM1 and PWM2; High Priority Interrupt Vector; Hardware Multiplier; fast

call/return; FSR 0; TBLPTR; 2 stack levels

PWMfrequencyvalues: 0 or 1

Description: This function must be called before all other ProMPT methods, and it must be called only once. This

routine configures Timer2 and the PWM outputs.

When PWMfrequencyis ‘0’, the module’s operating frequency is 9.75 kHz. When PWMfrequencyis ‘1’, the module’s

operating frequency is 19.53 kHz.

Note:

Since the high priority interrupt is used, the fast call/return cannot be used by other routines.

DS30485A-page 118

Preliminary

 2002 Microchip Technology Inc.

PIC18FXX39

void ProMPT_SetAccelRate(unsigned char rate)

Resources used: 0 stack level

raterange: 0 to 255

Description: Sets the acceleration to the value of rate in Hz/second. The default setting is 10 Hz/s.

void ProMPT_SetBoostEndModulation(unsigned char modulation)

Resources used: Hardware Multiplier; 0 stack levels

modulationrange: 0 to 200

Description: Sets the End Modulation (in %) for the Boost logic. Boost mode operates at Boost Frequency, and the

modulation ramps from BoostStartModulationto BoostEndModulation. This function should not be called while

Boost is enabled.

unsigned char ProMPT_SetBoostFrequency(unsigned char frequency)

Resources used: 0 stack levels

frequencyrange: 0 to 127

Description: Sets the frequency the drive goes to in Boost mode. Frequency must be < 128. On exit, w = 0 if the

command is successful, or w = FFh if the frequency is out of range. This function should not be called while Boost is

enabled.

void ProMPT_SetBoostStartModulation(unsigned char modulation)

Resources used: Hardware Multiplier; 0 stack levels

modulationrange: 0 to BoostEndModulation

Description: Sets the Start Modulation (in %) for the Boost logic. Boost mode operates at Boost Frequency, and the

modulation ramps from BoostStartModulationto BoostEndModulation. This function should not be called while

Boost is enabled.

void ProMPT_SetBoostTime(unsigned char time)

Resources used: Hardware Multiplier; 0 stack levels

timerange: 0 to 255

Description: Sets the amount of time in seconds for the Boost mode. Boost mode operates at Boost Frequency, and

the modulation ramps from BoostStartModulation to BoostEndModulation over BoostTime. This function

should not be called while Boost is enabled.

void ProMPT_SetDecelRate(unsigned char rate)

Resources used: 0 stack levels

raterange: 0 to 255

Description: Sets the deceleration to the value of ratein Hz per second. The default setting is 5 Hz/s.

unsigned char ProMPT_SetFrequency(unsigned char frequency)

Resources used: 2 stack levels

frequencyrange: 0 to 127

Description: Sets the output frequency of the drive if the drive is running. Frequency is limited to 0 to 127, but should

be controlled within the valid operational range of the motor. Modulation is determined from the V/F curve, which is set

up with the ProMPT_SetVFCurvemethod. If frequency = 0, the drive will stop. If the drive is stopped and frequency > 0,

the drive will start.

 2002 Microchip Technology Inc.

Preliminary

DS30485A-page 119

PIC18FXX39

void ProMPT_SetLineVoltage(unsigned char voltage)

Resources used: Hardware Multiplier; 0 stack levels

voltagerange: 0 to 255

Description: Sets the line voltage for Automatic Voltage Compensation. The units for SetLineVoltage and

SetMotorVoltage must be the same for accurate operation. The values passed to SetMotorVoltage and

SetLineVoltagecan be the same to disable voltage compensation.

void ProMPT_SetMotorVoltage(unsigned char voltage)

Resources used: Hardware Multiplier; 0 stack levels

voltagerange: 0 to 255

Description: Sets the motor rating for Automatic Voltage Compensation. The units for SetLineVoltage and

SetMotorVoltage must be the same for accurate operation. The values passed to SetMotorVoltage and

SetLineVoltagecan be the same to disable voltage compensation.

void ProMPT_SetParameter(unsigned char parameter, unsigned char value)

Resources used: 0 stack levels

parameterrange:

Description: In addition to its pre-defined API methods, the ProMPT kernel allows the user to custom define up to 16

functions for control or communication purposes not covered by the ProMPT APIs. This function sets the value of the

specified user defined function.

void ProMPT_SetPWMfrequency(unsigned char PWMfrequency)

PWMfrequencyvalues: 0 or 1

Resources used: Timer2; 1 stack level

Description: This sets and changes the PWM switching frequency. Typically, this is set with the Init()function.

When PWMfrequencyis ‘0’, the module’s operating frequency is 9.75 kHz. When PWMfrequencyis ‘1’, the module’s

operating frequency is 19.53 kHz.

void ProMPT_SetVFCurve(unsigned char point, unsigned char value)

Resources used: Hardware Multiplier; 0 stack level

pointrange: 0 to 16 (0 = 0 Hz, 1 = 8 Hz, 2 = 16 Hz……. 17 = 128 Hz)

valuerange: 0 to 200

Description: This sets one of the 17 modulation values (in %) for the V/F curve. Each point represents a frequency

increment of 8 Hz, ranging from point 0 (0 Hz) to point 16 (128 Hz).

unsigned char ProMPT_Tick(void)

Resources used: 1 stack level

Description: The value of the Tick timer flag becomes ‘1’ every 62.5 ms (1/16 second). This can be used for timing

applications. clearTickmust be called in the timing routine when this is serviced.

DS30485A-page 120

Preliminary

 2002 Microchip Technology Inc.

PIC18FXX39

FIGURE 14-3:

LAYERS OF THE

14.4 Developing Applications Using

the Motor Control Kernel

The Motor Control kernel allows users to develop their

applications without having knowledge of motor con-

trol. The key parameters of the motor control kernel can

be set and read through the Application Program Inter-

face (API) methods discussed in the previous section.

MOTOR CONTROL

ARCHITECTURE STACK

Application Software

and User Interface

The overall application can be thought of as a protocol

stack, as shown in Figure 14-3. In this case, the API

methods reside between the user’s application and the

ProMPT kernel, and are used to exchange parameter

values. The motor control kernel sets the PWM duty

cycles based on the inputs from the application

software.

Application Program

Interface (API)

Methods

Parameters

A

typical motor control routine is shown in

Example 14-1. In this case, the motor will run at 20 Hz

for 10 seconds, accelerate to 60 Hz at the rate of

10 Hz/s, remain at 60 Hz for 20 seconds, and finally

stop.

ProMPT Motor

Control Kernel

Hardware

EXAMPLE 14-1:

Void main()

{

MOTOR CONTROL ROUTINE USING THE ProMPT APIs

unsigned char i;

unsigned char j;

ProMPT_Init(0);

i = ProMPT_SetFrequency(10);

// Initialize the ProMPT block

// Set motor frequency to 10Hz

for (i=0;i<161;i++)

// Set counter for 10 sec @ 1/16 sec per tick

{

j = ProMPT_Tick(void);

// Tick of 1/16 sec

ProMPT_ClearTick(void);

}

// Clearing the Tick flag

ProMPT_SetAccelRate(10);

// Set acceleration rate to 10 Hz/sec

// Set motor frequency to 60 Hz

i = ProMPT_SetFrequency(60);

for (i=0;i<161;i++)

{

// Set counter for 20 Sec @ 1/16 sec per tick

// (2 loops of 10 Sec each)

// Tick of 1/16 Sec

// Clearing the Tick flag

// Tick of 1/16 Sec

j = ProMPT_Tick(void);

ProMPT_ClearTick(void);

j = ProMPT_Tick(void);

ProMPT_ClearTick(void);

}

// Clearing the Tick flag

i = ProMPT_SetFrequency(0);

while(1);

// Set motor frequency to 0 Hz (stop)

// End of the task

}

 2002 Microchip Technology Inc.

Preliminary

DS30485A-page 121

PIC18FXX39

NOTES:

DS30485A-page 122

Preliminary

 2002 Microchip Technology Inc.

PIC18FXX39

FIGURE 15-2:

PWM OUTPUT

15.0 PULSE WIDTH MODULATION

(PWM) MODULES

Period

PIC18FXX39 devices are equipped with two 10-bit

PWM modules. Each contains

a register pair

(CCPxH:CCPxL), which operates as a Master/Slave

Duty Cycle register, and a control register (CCPxCON).

The modules use Timer2 (Section 12.0) as their time-

base reference. Figure 15-1 shows a simplified block

diagram of the module’s operation.

Duty Cycle

TMR2 = PR2

TMR2 = Duty Cycle

This section gives a brief overview of PWM operation

as controlled by the Motor Control module

(Section 14.0). Operation is described with respect to

PWM1, but is equally applicable to PWM2.

TMR2 = PR2

15.1.1

PWM PERIOD

The PWM period is specified when the Motor Control

module is initialized. The PWM period can be

calculated using the formula:

PWM period = [(PR2) + 1] • 4 • TOSC •

(TMR2 prescale value)

PWM frequency is defined as 1 / [PWM period].

The API method void ProMPT_Init (page 118)

sets the required PWM frequency in the application.

The parameter PWMfrequencydetermines the operat-

ing frequency of the module. When it is ‘0’, the PWM

frequency set in the Motor Control module is 9.75 kHz;

when it is ‘1’, the set PWM frequency is 19.53 kHz.

When TMR2 is equal to PR2, the following three events

occur on the next increment cycle:

• TMR2 is cleared

Note: The PWM modules are used exclusively

by the Motor Control module. As such, they

are not available to users as a separate

resource. Although their locations are

shown on the device data memory maps,

users should not modify the values of

these registers.

15.1 PWM Mode

In Pulse Width Modulation, each PWM pin produces a

PWM output with a resolution of up to 10 bits.

A PWM output (Figure 15-2) has a time-base (period)

and a time that the output stays high (duty cycle). The

frequency of the PWM is the inverse of the period

(1/period).

• The PWM1 pin is set (exception: if PWM duty

FIGURE 15-1:

SIMPLIFIED PWM BLOCK

DIAGRAM

cycle = 0%, the PWM1 pin will not be set)

• The PWM duty cycle is latched from CCPR1L into

CCPR1H

CCP1CON<5:4>

Duty Cycle Registers

Note: The Timer2 postscaler (see Section 12.0)

is not used in the determination of the

PWM frequency. The postscaler could be

used to have a servo update rate at a

different frequency than the PWM output.

CCPR1L

CCPR1H (Slave)

Comparator

TMR2

R

S

Q

PWM1

(1)

Comparator

PR2

Clear Timer,

PWM1 pin and

latch Duty Cycle

Note 1: 8-bit timer is concatenated with 2-bit internal Q

clock, or 2 bits of the prescaler to create a

10-bit time-base.

 2002 Microchip Technology Inc.

Preliminary

DS30485A-page 123

PIC18FXX39

either an internal 2-bit Q clock, or 2 bits of the TMR2

prescaler. When the CCPR1H:latch pair value matches

that of the TMR2:latch pair, the PWM1 pin is cleared.

The maximum PWM resolution (bits) for a given PWM

frequency is given by the equation:

15.1.2

PWM DUTY CYCLE

The PWM duty cycle is set by the Motor Control module

when it writes a 10-bit value to the CCPR1L and

CCP1CON registers, where CCPR1L contains the

eight Most Significant bits and CCP1CON<5:4> con-

tains the two Least Significant bits. The duty cycle time

is given by the equation:



^FOSC

FPWM

---------------

log





PWM Resolution (max)

= ----------------------------- b i t s

log(2)

PWM duty cycle = (10-bit CCP register value) •

TOSC • (TMR2 prescale value)

where FPWM is the PWM frequency, or (1/PWM period).

where TOSC and the duty cycle are in the same unit of

time.

The CCPR1H register and a 2-bit internal latch are

used to double-buffer the PWM duty cycle. This buffer-

ing is essential for glitchless PWM operation. At the

same time, the value of TMR2 is concatenated with

Note: If the PWM duty cycle value is longer than

the PWM period, the PWM1 pin will not be

cleared.

TABLE 15-1: REGISTERS ASSOCIATED WITH PWM AND TIMER2

Value on

All Other

RESETS

Value on

POR, BOR

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

INTCON

PIR1

GIE/GIEH PEIE/GIEL TMR0IE

INT0IE

RBIE

TMR0IF

INT0IF

RBIF

0000 000x 0000 000u

(1)

—

*

PSPIF

ADIF

RCIF

TXIF

SSPIF

TMR2IF TMR1IF 0000 0000 0000 0000

TMR2IE TMR1IE 0000 0000 0000 0000

TMR2IP TMR1IP 0000 0000 0000 0000

(1)

PIE1

PSPIE

ADIE

RCIE

TXIE

SSPIE

IPR1

PSPIP

ADIP

RCIP

TXIP

SSPIP

*

TMR2

*

0000 0000 0000 0000

1111 1111 1111 1111

-000 0000 -000 0000

xxxx xxxx uuuu uuuu

--00 0000 --00 0000

xxxx xxxx uuuu uuuu

--00 0000 --00 0000

*

PR2

*

T2CON

*

CCPR1L

CCPR1H

CCP1CON

CCPR2L

CCPR2H

CCP2CON

*

PWM Register1 (MSB) (read-only)

*

—

*

—

*

PWM Register2 (MSB) (read-only)

—

*

Legend: x= unknown, u= unchanged, - = unimplemented, read as '0' unless otherwise noted. Shaded cells are not used by PWM

and Timer2.

*

These registers are retained to maintain compatibility with PIC18FXX2 devices; however, the indicated bits are reserved in

PIC18FXX39 devices. Users should not alter the values of these bits.

Note 1: The PSPIF, PSPIE and PSPIP bits are reserved on the PIC18F2X39 devices; always maintain these bits clear.

DS30485A-page 124

Preliminary

 2002 Microchip Technology Inc.

PIC18FXX39

16.3 SPI Mode

16.0 MASTER SYNCHRONOUS

SERIAL PORT (MSSP)

MODULE

The SPI mode allows 8 bits of data to be synchronously

transmitted and received, simultaneously. All four modes

of SPI are supported. To accomplish communication,

typically three pins are used:

• Serial Data Out (SDO) - RC5/SDO

• Serial Data In (SDI) - RC4/SDI/SDA

• Serial Clock (SCK) - RC3/SCK/SCL

Additionally, a fourth pin may be used when in a Slave

mode of operation:

• Slave Select (SS) - RA5/AN4/SS/LVDIN

16.1 Master SSP (MSSP) Module

Overview

The Master Synchronous Serial Port (MSSP) module is

a serial interface useful for communicating with other

peripheral or microcontroller devices. These peripheral

devices may be serial EEPROMs, shift registers, dis-

play drivers, A/D converters, etc. The MSSP module

can operate in one of two modes:

• Serial Peripheral Interface (SPI)

• Inter-Integrated Circuit (I²C)

- Full Master mode

- Slave mode (with general address call)

The I²C interface supports the following modes in

hardware:

Figure 16-1 shows the block diagram of the MSSP

module when operating in SPI mode.

FIGURE 16-1:

MSSP BLOCK DIAGRAM

(SPI MODE)

Internal

Data Bus

• Master mode

• Multi-Master mode

• Slave mode

Read

Write

SSPBUF reg

SSPSR reg

16.2 Control Registers

RC4/SDI/SDA

RC5/SDO

The MSSP module has three associated registers.

These include a status register (SSPSTAT) and two

control registers (SSPCON1 and SSPCON2). The use

of these registers and their individual configuration bits

differ significantly, depending on whether the MSSP

module is operated in SPI or I C mode.

Additional details are provided under the individual

sections.

shift

clock

bit0

2

RA5/AN4/SS/

LVDIN

Control

Enable

SS

Edge

Select

2

Clock Select

SSPM3:SSPM0

4

SMP:CKE

2

RC3/SCK/

SCL

Edge

TOSC

Prescaler

Select

÷4 / 16 / 64

Data to TX/RX in SSPSR

TRIS bit

 2002 Microchip Technology Inc.

Preliminary

DS30485A-page 125

PIC18FXX39

SSPSR is the shift register used for shifting data in or

out. SSPBUF is the buffer register to which data bytes

are written to or read from.

In receive operations, SSPSR and SSPBUF together

create a double-buffered receiver. When SSPSR

receives a complete byte, it is transferred to SSPBUF

and the SSPIF interrupt is set.

16.3.1

REGISTERS

The MSSP module has four registers for SPI mode

operation. These are:

• MSSP Control Register1 (SSPCON1)

• MSSP Status Register (SSPSTAT)

• Serial Receive/Transmit Buffer (SSPBUF)

• MSSP Shift Register (SSPSR) - Not directly

During

transmission,

the

SSPBUF

is

not

accessible

double-buffered. A write to SSPBUF will write to both

SSPBUF and SSPSR.

SSPCON1 and SSPSTAT are the control and status

registers in SPI mode operation. The SSPCON1 regis-

ter is readable and writable. The lower 6 bits of the

SSPSTAT are read only. The upper two bits of the

SSPSTAT are read/write.

REGISTER 16-1: SSPSTAT: MSSP STATUS REGISTER (SPI MODE)

R/W-0

SMP

R/W-0

CKE

R-0

D/A

R-0

P

R-0

S

R-0

R/W

R-0

UA

R-0

BF

bit 7

bit 0

bit 7

bit 6

SMP: Sample bit

SPI Master mode:

1= Input data sampled at end of data output time

0= Input data sampled at middle of data output time

SPI Slave mode:

SMP must be cleared when SPI is used in Slave mode

CKE: SPI Clock Edge Select bit

When CKP = 0:

1= Data transmitted on rising edge of SCK

0= Data transmitted on falling edge of SCK

When CKP = 1:

1= Data transmitted on falling edge of SCK

0= Data transmitted on rising edge of SCK

bit 5

bit 4

D/A: Data/Address bit

Used in I C mode only

2

P: STOP bit

2

Used in I C mode only. This bit is cleared when the MSSP module is disabled, SSPEN is

cleared.

bit 3

bit 2

bit 1

bit 0

S: START bit

Used in I C mode only

2

R/W: Read/Write bit information

2

Used in I C mode only

UA: Update Address

2

Used in I C mode only

BF: Buffer Full Status bit (Receive mode only)

1= Receive complete, SSPBUF is full

0= Receive not complete, SSPBUF is empty

Legend:

R = Readable bit

- n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

DS30485A-page 126

Preliminary

 2002 Microchip Technology Inc.

PIC18FXX39

REGISTER 16-2: SSPCON1: MSSP CONTROL REGISTER 1 (SPI MODE)

R/W-0

WCOL

R/W-0

SSPOV

R/W-0

SSPEN

R/W-0

CKP

R/W-0

SSPM3

R/W-0

SSPM2

R/W-0

SSPM1

R/W-0

SSPM0

bit 7

bit 0

bit 7

bit 6

WCOL: Write Collision Detect bit (Transmit mode only)

1= The SSPBUF register is written while it is still transmitting the previous word

(must be cleared in software)

0= No collision

SSPOV: Receive Overflow Indicator bit

SPI Slave mode:

1= A new byte is received while the SSPBUF register is still holding the previous data. In case

of overflow, the data in SSPSR is lost. Overflow can only occur in Slave mode.The user

must read the SSPBUF, even if only transmitting data, to avoid setting overflow (must be

cleared in software).

0= No overflow

Note: In Master mode, the overflow bit is not set since each new reception (and

transmission) is initiated by writing to the SSPBUF register.

bit 5

bit 4

SSPEN: Synchronous Serial Port Enable bit

1= Enables serial port and configures SCK, SDO, SDI, and SS as serial port pins

0= Disables serial port and configures these pins as I/O port pins

Note:

When enabled, these pins must be properly configured as input or output.

CKP: Clock Polarity Select bit

1= IDLE state for clock is a high level

0= IDLE state for clock is a low level

bit 3-0 SSPM3:SSPM0: Synchronous Serial Port Mode Select bits

0101= SPI Slave mode, clock = SCK pin, SS pin control disabled, SS can be used as I/O pin

0100= SPI Slave mode, clock = SCK pin, SS pin control enabled

0011= Reserved

0010= SPI Master mode, clock = FOSC/64

0001= SPI Master mode, clock = FOSC/16

0000= SPI Master mode, clock = FOSC/4

Note: Bit combinations not specifically listed here are either reserved, or implemented in

2

I C mode only.

Legend:

R = Readable bit

- n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

 2002 Microchip Technology Inc.

Preliminary

DS30485A-page 127

PIC18FXX39

SSPBUF register during transmission/reception of data

will be ignored, and the write collision detect bit, WCOL

(SSPCON1<7>), will be set. User software must clear

the WCOL bit so that it can be determined if the follow-

ing write(s) to the SSPBUF register completed

successfully.

When the application software is expecting to receive

valid data, the SSPBUF should be read before the next

byte of data to transfer is written to the SSPBUF. Buffer

full bit, BF (SSPSTAT<0>), indicates when SSPBUF

has been loaded with the received data (transmission

is complete). When the SSPBUF is read, the BF bit is

cleared. This data may be irrelevant if the SPI is only a

transmitter. Generally, the MSSP Interrupt is used to

determine when the transmission/reception has com-

pleted. The SSPBUF must be read and/or written. If the

interrupt method is not going to be used, then software

polling can be done to ensure that a write collision does

not occur. Example 16-1 shows the loading of the

SSPBUF (SSPSR) for data transmission.

16.3.2

OPERATION

When initializing the SPI, several options need to be

specified. This is done by programming the appropriate

control bits (SSPCON1<5:0>) and SSPSTAT<7:6>.

These control bits allow the following to be specified:

• Master mode (SCK is the clock output)

• Slave mode (SCK is the clock input)

• Clock Polarity (IDLE state of SCK)

• Data input sample phase (middle or end of data

output time)

• Clock edge (output data on rising/falling edge of

SCK)

• Clock Rate (Master mode only)

• Slave Select mode (Slave mode only)

The MSSP consists of a transmit/receive Shift Register

(SSPSR) and a buffer register (SSPBUF). The SSPSR

shifts the data in and out of the device, MSb first. The

SSPBUF holds the data that was written to the SSPSR,

until the received data is ready. Once the 8 bits of data

have been received, that byte is moved to the SSPBUF

register. Then, the buffer full detect bit, BF

(SSPSTAT<0>), and the interrupt flag bit, SSPIF, are

set. This double-buffering of the received data

(SSPBUF) allows the next byte to start reception before

reading the data that was just received. Any write to the

The SSPSR is not directly readable or writable, and

can only be accessed by addressing the SSPBUF reg-

ister. Additionally, the MSSP status register (SSPSTAT)

indicates the various status conditions.

EXAMPLE 16-1:

LOADING THE SSPBUF (SSPSR) REGISTER

LOOP BTFSS SSPSTAT, BF

;Has data been received(transmit complete)?

BRA

LOOP

;No

MOVF SSPBUF, W

;WREG reg = contents of SSPBUF

MOVWF RXDATA

;Save in user RAM, if data is meaningful

MOVF TXDATA, W

MOVWF SSPBUF

;W reg = contents of TXDATA

;New data to xmit

DS30485A-page 128

Preliminary

 2002 Microchip Technology Inc.

PIC18FXX39

16.3.3

ENABLING SPI I/O

16.3.4

TYPICAL CONNECTION

To enable the serial port, SSP Enable bit, SSPEN

(SSPCON1<5>), must be set. To reset or reconfigure

SPI mode, clear the SSPEN bit, re-initialize the

SSPCON registers, and then set the SSPEN bit. This

configures the SDI, SDO, SCK, and SS pins as serial

port pins. For the pins to behave as the serial port func-

tion, some must have their data direction bits (in the

TRIS register) appropriately programmed. That is:

• SDI is automatically controlled by the SPI module

• SDO must have TRISC<5> bit cleared

• SCK (Master mode) must have TRISC<3> bit

cleared

Figure 16-2 shows a typical connection between two

microcontrollers. The master controller (Processor 1)

initiates the data transfer by sending the SCK signal.

Data is shifted out of both shift registers on their pro-

grammed clock edge, and latched on the opposite

edge of the clock. Both processors should be pro-

grammed to the same Clock Polarity (CKP), then both

controllers would send and receive data at the same

time. Whether the data is meaningful (or dummy data)

depends on the application software. This leads to

three scenarios for data transmission:

• Master sends data — Slave sends dummy data

• Master sends data — Slave sends data

• Master sends dummy data — Slave sends data

• SCK (Slave mode) must have TRISC<3> bit set

• SS must have TRISC<4> bit set

Any serial port function that is not desired may be

overridden by programming the corresponding data

direction (TRIS) register to the opposite value.

FIGURE 16-2:

SPI MASTER/SLAVE CONNECTION

SPI Master SSPM3:SSPM0 = 00xxb

SPI Slave SSPM3:SSPM0 = 010xb

SDO

SDI

Serial Input Buffer

(SSPBUF)

Serial Input Buffer

(SSPBUF)

SDI

SDO

Shift Register

(SSPSR)

Shift Register

(SSPSR)

LSb

MSb

LSb

Serial Clock

SCK

PROCESSOR 1

PROCESSOR 2

 2002 Microchip Technology Inc.

Preliminary

DS30485A-page 129

PIC18FXX39

Figure 16-3, Figure 16-5, and Figure 16-6, where the

MSB is transmitted first. In Master mode, the SPI clock

rate (bit rate) is user-programmable to be one of the

following:

• FOSC/4 (or TCY)

• FOSC/16 (or 4 • TCY)

• FOSC/64 (or 16 • TCY)

16.3.5

MASTER MODE

The master can initiate the data transfer at any time

because it controls the SCK. The master determines

when the slave (Processor 2, Figure 16-2) is to

broadcast data by the software protocol.

In Master mode, the data is transmitted/received as

soon as the SSPBUF register is written to. If the SPI is

only going to receive, the SDO output could be dis-

abled (programmed as an input). The SSPSR register

will continue to shift in the signal present on the SDI pin

at the programmed clock rate. As each byte is

received, it will be loaded into the SSPBUF register as

if a normal received byte (interrupts and status bits

appropriately set). This could be useful in receiver

applications as a “Line Activity Monitor” mode.

This allows a maximum data rate (at 40 MHz) of

10.00 Mbps.

Figure 16-3 shows the waveforms for Master mode.

When the CKE bit is set, the SDO data is valid before

there is a clock edge on SCK. The change of the input

sample is shown based on the state of the SMP bit. The

time when the SSPBUF is loaded with the received

data is shown.

The clock polarity is selected by appropriately program-

ming the CKP bit (SSPCON1<4>). This then, would

give waveforms for SPI communication as shown in

FIGURE 16-3:

SPI MODE WAVEFORM (MASTER MODE)

Write to

SSPBUF

SCK

(CKP = 0

CKE = 0)

SCK

(CKP = 1

CKE = 0)

4 Clock

Modes

SCK

(CKP = 0

CKE = 1)

SCK

(CKP = 1

CKE = 1)

bit6

bit2

bit5

bit4

bit1

bit0

SDO

bit7

bit3

(CKE = 0)

SDO

(CKE = 1)

SDI

(SMP = 0)

bit0

bit7

Input

Sample

(SMP = 0)

SDI

(SMP = 1)

bit0

bit7

Input

Sample

(SMP = 1)

SSPIF

Next Q4 cycle

SSPSR to

SSPBUF

after Q2↓

DS30485A-page 130

Preliminary

 2002 Microchip Technology Inc.

PIC18FXX39

longer driven, even if in the middle of a transmitted

byte, and becomes a floating output. External pull-up/

pull-down resistors may be desirable, depending on the

application.

16.3.6

SLAVE MODE

In Slave mode, the data is transmitted and received as

the external clock pulses appear on SCK. When the

last bit is latched, the SSPIF interrupt flag bit is set.

While in Slave mode, the external clock is supplied by

the external clock source on the SCK pin. This external

clock must meet the minimum high and low times, as

specified in the electrical specifications.

While in SLEEP mode, the slave can transmit/receive

data. When a byte is received, the device will wake-up

from SLEEP.

Note 1: When the SPI is in Slave mode with SS

pin control enabled (SSPCON<3:0> =

0100), the SPI module will reset if the SS

pin is set to VDD.

2: If the SPI is used in Slave mode with CKE

set, then the SS pin control must be

enabled.

When the SPI module resets, the bit counter is forced

to ‘0’. This can be done by either forcing the SS pin to

a high level or clearing the SSPEN bit.

16.3.7

SLAVE SELECT

SYNCHRONIZATION

To emulate two-wire communication, the SDO pin can

be connected to the SDI pin. When the SPI needs to

operate as a receiver, the SDO pin can be configured

as an input. This disables transmissions from the SDO.

The SDI can always be left as an input (SDI function),

since it cannot create a bus conflict.

The SS pin allows a Synchronous Slave mode. The

SPI must be in Slave mode with SS pin control enabled

(SSPCON1<3:0> = 04h). The pin must not be driven

low for the SS pin to function as an input. The Data

Latch must be high. When the SS pin is low, transmis-

sion and reception are enabled and the SDO pin is

driven. When the SS pin goes high, the SDO pin is no

FIGURE 16-4:

SLAVE SYNCHRONIZATION WAVEFORM

SS

SCK

(CKP = 0

CKE = 0)

SCK

(CKP = 1

CKE = 0)

Write to

SSPBUF

bit6

bit7

bit0

SDO

bit7

SDI

bit0

(SMP = 0)

bit7

Input

Sample

(SMP = 0)

SSPIF

Interrupt

Flag

Next Q4 cycle

SSPSR to

SSPBUF

after Q2↓

 2002 Microchip Technology Inc.

Preliminary

DS30485A-page 131

PIC18FXX39

FIGURE 16-5:

SPI MODE WAVEFORM (SLAVE MODE WITH CKE = 0)

SS

Optional

SCK

(CKP = 0

CKE = 0)

SCK

(CKP = 1

CKE = 0)

Write to

SSPBUF

bit6

bit2

bit5

bit4

bit1

bit0

SDO

bit7

bit3

SDI

(SMP = 0)

bit0

bit7

Input

Sample

(SMP = 0)

SSPIF

Interrupt

Flag

Next Q4 cycle

SSPSR to

after Q2↓

SSPBUF

FIGURE 16-6:

SPI MODE WAVEFORM (SLAVE MODE WITH CKE = 1)

SS

Not Optional

SCK

(CKP = 0

CKE = 1)

SCK

(CKP = 1

CKE = 1)

Write to

SSPBUF

bit6

bit2

bit5

bit4

bit1

bit0

SDO

bit7

bit3

SDI

(SMP = 0)

bit0

Input

Sample

(SMP = 0)

SSPIF

Interrupt

Flag

Next Q4 cycle

after Q2↓

SSPSR to

SSPBUF

DS30485A-page 132

Preliminary

 2002 Microchip Technology Inc.

PIC18FXX39

16.3.8

SLEEP OPERATION

16.3.10 BUS MODE COMPATIBILITY

In Master mode, all module clocks are halted and the

transmission/reception will remain in that state until the

device wakes from SLEEP. After the device returns to

Normal mode, the module will continue to transmit/

receive data.

Table 16-1 shows the compatibility between the

standard SPI modes and the states the CKP and CKE

control bits.

TABLE 16-1: SPI BUS MODES

In Slave mode, the SPI transmit/receive shift register

operates asynchronously to the device. This allows the

device to be placed in SLEEP mode and data to be

shifted into the SPI transmit/receive shift register.

When all 8 bits have been received, the MSSP interrupt

flag bit will be set and if enabled, will wake the device

from SLEEP.

Control Bits State

Standard SPI Mode

Terminology

CKP

CKE

0, 0

0, 1

1, 0

1, 1

0

1

0

1

0

16.3.9

EFFECTS OF A RESET

There is also an SMP bit which controls when the data

is sampled.

A RESET disables the MSSP module and terminates

the current transfer.

TABLE 16-2: REGISTERS ASSOCIATED WITH SPI OPERATION

Value on

All Other

RESETS

Value on

POR, BOR

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

INTCON

GIE/GIEH

PEIE/

GIEL

TMR0IE INT0IE

RBIE

TMR0IF

INT0IF

RBIF

0000 000x 0000 000u

(1)

—

*

PIR1

PSPIF

ADIF

ADIE

ADIP

RCIF

RCIE

RCIP

TXIF

TXIE

TXIP

SSPIF

SSPIE

SSPIP

TMR2IF TMR1IF 0000 0000 0000 0000

TMR2IE TMR1IE 0000 0000 0000 0000

TMR2IP TMR1IP 0000 0000 0000 0000

(1)

PIE1

PSPIE

(1)

IPR1

PSPIP

TRISC

SSPBUF

SSPCON

TRISA

SSPSTAT

TRISC7

TRISC6 TRISC5 TRISC4 TRISC3

TRISC0 1111 1111 1111 1111

xxxx xxxx uuuu uuuu

*

Synchronous Serial Port Receive Buffer/Transmit Register

WCOL

—

SSPOV SSPEN

PORTA Data Direction Register

CKE D/A

CKP

SSPM3

SSPM2

SSPM1

SSPM0 0000 0000 0000 0000

-111 1111 -111 1111

SMP

P

S

R/W

UA

BF

0000 0000 0000 0000

Legend: x= unknown, u= unchanged, - = unimplemented, read as '0'. Shaded cells are not used by the MSSP in SPI mode.

Reserved bits; do not modify.

Note 1: The PSPIF, PSPIE and PSPIP bits are reserved on the PIC18C2X2 devices; always maintain these bits clear.

*

 2002 Microchip Technology Inc.

Preliminary

DS30485A-page 133

PIC18FXX39

2

16.4.1

REGISTERS

16.4 I C Mode

2

The MSSP module has six registers for I C operation.

These are:

• MSSP Control Register1 (SSPCON1)

• MSSP Control Register2 (SSPCON2)

• MSSP Status Register (SSPSTAT)

• Serial Receive/Transmit Buffer (SSPBUF)

• MSSP Shift Register (SSPSR) - Not directly

accessible

• MSSP Address Register (SSPADD)

SSPCON, SSPCON2 and SSPSTAT are the control

and status registers in I C mode operation. The

SSPCON and SSPCON2 registers are readable and

writable. The lower 6 bits of the SSPSTAT are read

only. The upper two bits of the SSPSTAT are

read/write.

The MSSP module in I C mode fully implements all

master and slave functions (including general call sup-

port) and provides interrupts on START and STOP bits

in hardware to determine a free bus (multi-master func-

tion). The MSSP module implements the Standard

mode specifications, as well as 7-bit and 10-bit

addressing.

Two pins are used for data transfer:

• Serial clock (SCL) - RC3/SCK/SCL

• Serial data (SDA) - RC4/SDI/SDA

The user must configure these pins as inputs or outputs

through the TRISC<4:3> bits.

2

FIGURE 16-7:

MSSP BLOCK DIAGRAM

(I²C MODE)

SSPSR is the shift register used for shifting data in or

out. SSPBUF is the buffer register to which data bytes

are written to or read from.

Internal

Data Bus

Read

Write

SSPADD register holds the slave device address

2

when the SSP is configured in I C Slave mode. When

SSPBUF reg

RC3/SCK/SCL

the SSP is configured in Master mode, the lower

seven bits of SSPADD act as the baud rate generator

reload value.

Shift

Clock

In receive operations, SSPSR and SSPBUF together,

create a double-buffered receiver. When SSPSR

receives a complete byte, it is transferred to SSPBUF

and the SSPIF interrupt is set.

During transmission, the SSPBUF is not double-

buffered. A write to SSPBUF will write to both SSPBUF

and SSPSR.

SSPSR reg

RC4/

SDI/

SDA

MSb

LSb

Addr Match

Match Detect

SSPADD reg

START and

Set, Reset

S, P bits

STOP bit Detect

(SSPSTAT reg)

DS30485A-page 134

Preliminary

 2002 Microchip Technology Inc.

PIC18FXX39

REGISTER 16-3: SSPSTAT: MSSP STATUS REGISTER (I²C MODE)

R/W-0

SMP

R/W-0

CKE

R-0

D/A

R-0

P

R-0

S

R-0

R/W

R-0

UA

R-0

BF

bit 7

bit 0

bit 7

bit 6

bit 5

SMP: Slew Rate Control bit

In Master or Slave mode:

1 = Slew rate control disabled for Standard Speed mode (100 kHz and 1 MHz)

0 = Slew rate control enabled for High Speed mode (400 kHz)

CKE: SMBus Select bit

In Master or Slave mode:

1= Enable SMBus specific inputs

0= Disable SMBus specific inputs

D/A: Data/Address bit

In Master mode:

Reserved

In Slave mode:

1= Indicates that the last byte received or transmitted was data

0= Indicates that the last byte received or transmitted was address

bit 4

bit 3

P: STOP bit

1= Indicates that a STOP bit has been detected last

0= STOP bit was not detected last

Note:

This bit is cleared on RESET and when SSPEN is cleared.

S: START bit

1= Indicates that a START bit has been detected last

0= START bit was not detected last

Note:

This bit is cleared on RESET and when SSPEN is cleared.

2

bit 2

R/W: Read/Write bit Information (I C mode only)

In Slave mode:

1= Read

0= Write

Note: This bit holds the R/W bit information following the last address match. This bit is only

valid from the address match to the next START bit, STOP bit, or not ACK bit.

In Master mode:

1= Transmit is in progress

0= Transmit is not in progress

Note:

ORing this bit with SEN, RSEN, PEN, RCEN, or ACKEN will indicate if the MSSP is

in IDLE mode.

bit 1

bit 0

UA: Update Address (10-bit Slave mode only)

1= Indicates that the user needs to update the address in the SSPADD register

0= Address does not need to be updated

BF: Buffer Full Status bit

In Transmit mode:

1= Receive complete, SSPBUF is full

0= Receive not complete, SSPBUF is empty

In Receive mode:

1= Data transmit in progress (does not include the ACK and STOP bits), SSPBUF is full

0= Data transmit complete (does not include the ACK and STOP bits), SSPBUF is empty

Legend:

R = Readable bit

- n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

 2002 Microchip Technology Inc.

Preliminary

DS30485A-page 135

PIC18FXX39

REGISTER 16-4: SSPCON1: MSSP CONTROL REGISTER 1 (I²C MODE)

R/W-0

WCOL

R/W-0

SSPOV

R/W-0

SSPEN

R/W-0

CKP

R/W-0

SSPM3

R/W-0

SSPM2

R/W-0

SSPM1

R/W-0

SSPM0

bit 7

bit 0

bit 7

WCOL: Write Collision Detect bit

In Master Transmit mode:

2

1= A write to the SSPBUF register was attempted while the I C conditions were not valid for

a transmission to be started (must be cleared in software)

0= No collision

In Slave Transmit mode:

1= The SSPBUF register is written while it is still transmitting the previous word (must be

cleared in software)

0= No collision

In Receive mode (Master or Slave modes):

This is a “don’t care” bit

bit 6

SSPOV: Receive Overflow Indicator bit

In Receive mode:

1= A byte is received while the SSPBUF register is still holding the previous byte (must

be cleared in software)

0= No overflow

In Transmit mode:

This is a “don’t care” bit in Transmit mode

bit 5

bit 4

SSPEN: Synchronous Serial Port Enable bit

1= Enables the serial port and configures the SDA and SCL pins as the serial port pins

0= Disables serial port and configures these pins as I/O port pins

Note: When enabled, the SDA and SCL pins must be properly configured as input or output.

CKP: SCK Release Control bit

In Slave mode:

1= Release clock

0= Holds clock low (clock stretch), used to ensure data setup time

In Master mode:

Unused in this mode

bit 3-0 SSPM3:SSPM0: Synchronous Serial Port Mode Select bits

2

1111= I C Slave mode, 10-bit address with START and STOP bit interrupts enabled

1110= I C Slave mode, 7-bit address with START and STOP bit interrupts enabled

1011= I C Firmware Controlled Master mode (Slave IDLE)

1000= I C Master mode, clock = FOSC / (4 * (SSPADD+1))

0111= I C Slave mode, 10-bit address

0110= I C Slave mode, 7-bit address

Note: Bit combinations not specifically listed here are either reserved, or implemented in

SPI mode only.

Legend:

R = Readable bit

- n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

DS30485A-page 136

Preliminary

 2002 Microchip Technology Inc.

PIC18FXX39

REGISTER 16-5: SSPCON2: MSSP CONTROL REGISTER 2 (I²C MODE)

R/W-0

GCEN

R/W-0

ACKSTAT

R/W-0

ACKDT

R/W-0

ACKEN

R/W-0

RCEN

R/W-0

PEN

R/W-0

RSEN

R/W-0

SEN

bit 7

bit 0

bit 7

bit 6

bit 5

GCEN: General Call Enable bit (Slave mode only)

1= Enable interrupt when a general call address (0000h) is received in the SSPSR

0= General call address disabled

ACKSTAT: Acknowledge Status bit (Master Transmit mode only)

1= Acknowledge was not received from slave

0= Acknowledge was received from slave

ACKDT: Acknowledge Data bit (Master Receive mode only)

1= Not Acknowledge

0= Acknowledge

Note: Value that will be transmitted when the user initiates an Acknowledge sequence at

the end of a receive.

bit 4

ACKEN: Acknowledge Sequence Enable bit (Master Receive mode only)

1= Initiate Acknowledge sequence on SDA and SCL pins, and transmit ACKDT data bit.

Automatically cleared by hardware.

0= Acknowledge sequence IDLE

bit 3

bit 2

bit 1

RCEN: Receive Enable bit (Master mode only)

1= Enables Receive mode for I²C

0= Receive IDLE

PEN: STOP Condition Enable bit (Master mode only)

1= Initiate STOP condition on SDA and SCL pins. Automatically cleared by hardware.

0= STOP condition IDLE

RSEN: Repeated START Condition Enabled bit (Master mode only)

1= Initiate Repeated START condition on SDA and SCL pins.

Automatically cleared by hardware.

0= Repeated START condition IDLE

bit 0

SEN: START Condition Enabled/Stretch Enabled bit

In Master mode:

1= Initiate START condition on SDA and SCL pins. Automatically cleared by hardware.

0= START condition IDLE

In Slave mode:

1= Clock stretching is enabled for both Slave Transmit and Slave Receive (stretch enabled)

0= Clock stretching is enabled for slave transmit only (Legacy mode)

2

Note: For bits ACKEN, RCEN, PEN, RSEN, SEN: If the I C module is not in the IDLE

mode, this bit may not be set (no spooling) and the SSPBUF may not be written (or

writes to the SSPBUF are disabled).

Legend:

R = Readable bit

- n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

 2002 Microchip Technology Inc.

Preliminary

DS30485A-page 137

PIC18FXX39

16.4.2

OPERATION

16.4.3.1

Addressing

Once the MSSP module has been enabled, it waits for

a START condition to occur. Following the START con-

dition, the 8-bits are shifted into the SSPSR register. All

incoming bits are sampled with the rising edge of the

clock (SCL) line. The value of register SSPSR<7:1> is

compared to the value of the SSPADD register. The

address is compared on the falling edge of the eighth

clock (SCL) pulse. If the addresses match, and the BF

and SSPOV bits are clear, the following events occur:

The MSSP module functions are enabled by setting

MSSP Enable bit, SSPEN (SSPCON<5>).

2

The SSPCON1 register allows control of the I C oper-

ation. Four mode selection bits (SSPCON<3:0>) allow

2

one of the following I C modes to be selected:

2

• I C Master mode, clock = OSC/4 (SSPADD +1)

2

• I C Slave mode (7-bit address)

2

• I C Slave mode (10-bit address)

2

1. The SSPSR register value is loaded into the

• I C Slave mode (7-bit address), with START and

SSPBUF register.

STOP bit interrupts enabled

2

2. The buffer full bit BF is set.

3. An ACK pulse is generated.

4. MSSP interrupt flag bit, SSPIF (PIR1<3>) is set

(interrupt is generated if enabled) on the falling

edge of the ninth SCL pulse.

• I C Slave mode (10-bit address), with START and

STOP bit interrupts enabled

2

• I C Firmware controlled master operation, slave

is IDLE

2

Selection of any I C mode, with the SSPEN bit set,

forces the SCL and SDA pins to be open drain, pro-

vided these pins are programmed to inputs by setting

the appropriate TRISC bits. To ensure proper operation

of the module, pull-up resistors must be provided

externally to the SCL and SDA pins.

In 10-bit Address mode, two address bytes need to be

received by the slave. The five Most Significant bits

(MSbs) of the first address byte specify if this is a 10-bit

address. Bit R/W (SSPSTAT<2>) must specify a write

so the slave device will receive the second address

byte. For a 10-bit address, the first byte would equal

‘11110 A9 A8 0’, where ‘A9’ and ‘A8’ are the two

MSbs of the address. The sequence of events for 10-bit

address is as follows, with steps 7 through 9 for the

slave-transmitter:

16.4.3

SLAVE MODE

In Slave mode, the SCL and SDA pins must be config-

ured as inputs (TRISC<4:3> set). The MSSP module

will override the input state with the output data when

required (slave-transmitter).

1. Receive first (high) byte of Address (bits SSPIF,

BF and bit UA (SSPSTAT<1>) are set).

2

The I C Slave mode hardware will always generate an

2. Update the SSPADD register with second (low)

byte of Address (clears bit UA and releases the

SCL line).

interrupt on an address match. Through the mode

select bits, the user can also choose to interrupt on

START and STOP bits

3. Read the SSPBUF register (clears bit BF) and

When an address is matched, or the data transfer after

an address match is received, the hardware automati-

cally will generate the Acknowledge (ACK) pulse and

load the SSPBUF register with the received value

currently in the SSPSR register.

Any combination of the following conditions will cause

the MSSP module not to give this ACK pulse:

clear flag bit SSPIF.

4. Receive second (low) byte of Address (bits

SSPIF, BF, and UA are set).

5. Update the SSPADD register with the first (high)

byte of Address. If match releases SCL line, this

will clear bit UA.

6. Read the SSPBUF register (clears bit BF) and

• The buffer full bit BF (SSPSTAT<0>) was set

before the transfer was received.

clear flag bit SSPIF.

7. Receive Repeated START condition.

• The overflow bit SSPOV (SSPCON<6>) was set

before the transfer was received.

In this case, the SSPSR register value is not loaded

into the SSPBUF, but bit SSPIF (PIR1<3>) is set. The

BF bit is cleared by reading the SSPBUF register, while

bit SSPOV is cleared through software.

8. Receive first (high) byte of Address (bits SSPIF

and BF are set).

9. Read the SSPBUF register (clears bit BF) and

clear flag bit SSPIF.

The SCL clock input must have a minimum high and

low for proper operation. The high and low times of the

2

I C specification, as well as the requirement of the

MSSP module, are shown in timing parameter 100 and

parameter 101.

DS30485A-page 138

Preliminary

 2002 Microchip Technology Inc.

PIC18FXX39

The ACK pulse from the master-receiver is latched on

the rising edge of the ninth SCL input pulse. If the SDA

line is high (not ACK), then the data transfer is com-

plete. In this case, when the ACK is latched by the

slave, the slave logic is reset (resets SSPSTAT regis-

ter) and the slave monitors for another occurrence of

the START bit. If the SDA line was low (ACK), the next

transmit data must be loaded into the SSPBUF register.

Again, pin RC3/SCK/SCL must be enabled by setting

bit CKP.

An MSSP interrupt is generated for each data transfer

byte. The SSPIF bit must be cleared in software and

the SSPSTAT register is used to determine the status

of the byte. The SSPIF bit is set on the falling edge of

the ninth clock pulse.

16.4.3.2

Reception

When the R/W bit of the address byte is clear and an

address match occurs, the R/W bit of the SSPSTAT

register is cleared. The received address is loaded into

the SSPBUF register and the SDA line is held low

(ACK).

When the address byte overflow condition exists, then

the no Acknowledge (ACK) pulse is given. An overflow

condition is defined as either bit BF (SSPSTAT<0>) is

set, or bit SSPOV (SSPCON1<6>) is set.

An MSSP interrupt is generated for each data transfer

byte. Flag bit SSPIF (PIR1<3>) must be cleared in soft-

ware. The SSPSTAT register is used to determine the

status of the byte.

If SEN is enabled (SSPCON1<0> = 1), RC3/SCK/SCL

will be held low (clock stretch) following each data trans-

fer. The clock must be released by setting bit CKP

(SSPCON<4>). See Section 16.4.4 (“Clock Stretching”),

for more detail.

16.4.3.3

Transmission

When the R/W bit of the incoming address byte is set

and an address match occurs, the R/W bit of the

SSPSTAT register is set. The received address is

loaded into the SSPBUF register. The ACK pulse will

be sent on the ninth bit and pin RC3/SCK/SCL is held

low, regardless of SEN (see “Clock Stretching”,

Section 16.4.4, for more detail). By stretching the clock,

the master will be unable to assert another clock pulse

until the slave is done preparing the transmit data. The

transmit data must be loaded into the SSPBUF register,

which also loads the SSPSR register. Then, pin RC3/

SCK/SCL should be enabled by setting bit CKP

(SSPCON1<4>). The eight data bits are shifted out on

the falling edge of the SCL input. This ensures that the

SDA signal is valid during the SCL high time

(Figure 16-9).

 2002 Microchip Technology Inc.

Preliminary

DS30485A-page 139

PIC18FXX39

2

FIGURE 16-8:

I C SLAVE MODE TIMING WITH SEN = 0 (RECEPTION, 7-BIT ADDRESS)

DS30485A-page 140

Preliminary

 2002 Microchip Technology Inc.

PIC18FXX39

I C SLAVE MODE TIMING (TRANSMISSION, 7-BIT ADDRESS)

2

FIGURE 16-9:

 2002 Microchip Technology Inc.

Preliminary

DS30485A-page 141

PIC18FXX39

FIGURE 16-10:

I²C SLAVE MODE TIMING WITH SEN = 0 (RECEPTION, 10-BIT ADDRESS)

DS30485A-page 142

Preliminary

 2002 Microchip Technology Inc.

PIC18FXX39

I C SLAVE MODE TIMING (TRANSMISSION, 10-BIT ADDRESS)

2

FIGURE 16-11:

 2002 Microchip Technology Inc.

Preliminary

DS30485A-page 143

PIC18FXX39

16.4.4

CLOCK STRETCHING

16.4.4.3

Clock Stretching for 7-bit Slave

Transmit Mode

Both 7- and 10-bit Slave modes implement automatic

clock stretching during a transmit sequence.

The SEN bit (SSPCON2<0>) allows clock stretching to

be enabled during receives. Setting SEN will cause

the SCL pin to be held low at the end of each data

receive sequence.

7-bit Slave Transmit mode implements clock stretching

by clearing the CKP bit after the falling edge of the

ninth clock, if the BF bit is clear. This occurs,

regardless of the state of the SEN bit.

The user’s ISR must set the CKP bit before transmis-

sion is allowed to continue. By holding the SCL line

low, the user has time to service the ISR and load the

contents of the SSPBUF before the master device can

initiate another transmit sequence (see Figure 16-9).

16.4.4.1

Clock Stretching for 7-bit Slave

Receive Mode (SEN = 1)

In 7-bit Slave Receive mode, on the falling edge of the

ninth clock at the end of the ACK sequence, if the BF

bit is set, the CKP bit in the SSPCON1 register is auto-

matically cleared, forcing the SCL output to be held

low. The CKP being cleared to ‘0’ will assert the SCL

line low. The CKP bit must be set in the user’s ISR

before reception is allowed to continue. By holding the

SCL line low, the user has time to service the ISR and

read the contents of the SSPBUF before the master

device can initiate another receive sequence. This will

prevent buffer overruns from occurring (see

Figure 16-13).

Note 1: If the user loads the contents of SSPBUF,

setting the BF bit before the falling edge of

the ninth clock, the CKP bit will not be

cleared and clock stretching will not occur.

2: The CKP bit can be set in software,

regardless of the state of the BF bit.

16.4.4.4

Clock Stretching for 10-bit Slave

Transmit Mode

In 10-bit Slave Transmit mode, clock stretching is con-

trolled during the first two address sequences by the

state of the UA bit, just as it is in 10-bit Slave Receive

mode. The first two addresses are followed by a third

address sequence, which contains the high order bits

of the 10-bit address and the R/W bit set to ‘1’. After

the third address sequence is performed, the UA bit is

not set, the module is now configured in Transmit

mode, and clock stretching is controlled by the BF flag,

as in 7-bit Slave Transmit mode (see Figure 16-11).

Note 1: If the user reads the contents of the

SSPBUF before the falling edge of the

ninth clock, thus clearing the BF bit, the

CKP bit will not be cleared and clock

stretching will not occur.

2: The CKP bit can be set in software,

regardless of the state of the BF bit. The

user should be careful to clear the BF bit

in the ISR before the next receive

sequence, in order to prevent an overflow

condition.

16.4.4.2

Clock Stretching for 10-bit Slave

Receive Mode (SEN = 1)

In 10-bit Slave Receive mode, during the address

sequence, clock stretching automatically takes place

but CKP is not cleared. During this time, if the UA bit is

set after the ninth clock, clock stretching is initiated.

The UA bit is set after receiving the upper byte of the

10-bit address, and following the receive of the second

byte of the 10-bit address with the R/W bit cleared to

‘0’. The release of the clock line occurs upon updating

SSPADD. Clock stretching will occur on each data

receive sequence, as described in 7-bit mode.

Note: If the user polls the UA bit and clears it by

updating the SSPADD register before the

falling edge of the ninth clock occurs, and if

the user hasn’t cleared the BF bit by read-

ing the SSPBUF register before that time,

then the CKP bit will still NOT be asserted

low. Clock stretching on the basis of the

state of the BF bit only occurs during a data

sequence, not an address sequence.

DS30485A-page 144

Preliminary

 2002 Microchip Technology Inc.

PIC18FXX39

16.4.4.5

Clock Synchronization and

the CKP bit

If a user clears the CKP bit, the SCL output is forced to

‘0’. Setting the CKP bit will not assert the SCL output

low until the SCL output is already sampled low. If the

user attempts to drive SCL low, the CKP bit will not

2

assert the SCL line until an external I C master device

has already asserted the SCL line. The SCL output will

remain low until the CKP bit is set, and all other

2

devices on the I C bus have de-asserted SCL. This

ensures that a write to the CKP bit will not violate the

minimum high time requirement for SCL (see

Figure 16-12).

FIGURE 16-12:

CLOCK SYNCHRONIZATION TIMING

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

SDA

SCL

DX

DX-1

Master device

asserts clock

CKP

Master device

de-asserts clock

WR

SSPCON

 2002 Microchip Technology Inc.

Preliminary

DS30485A-page 145

PIC18FXX39

2

FIGURE 16-13:

I C SLAVE MODE TIMING WITH SEN = 1 (RECEPTION, 7-BIT ADDRESS)

DS30485A-page 146

Preliminary

 2002 Microchip Technology Inc.

PIC18FXX39

FIGURE 16-14:

I²C SLAVE MODE TIMING WITH SEN = 1 (RECEPTION, 10-BIT ADDRESS)

 2002 Microchip Technology Inc.

Preliminary

DS30485A-page 147

PIC18FXX39

If the general call address matches, the SSPSR is

transferred to the SSPBUF, the BF flag bit is set (eighth

bit), and on the falling edge of the ninth bit (ACK bit),

the SSPIF interrupt flag bit is set.

When the interrupt is serviced, the source for the inter-

rupt can be checked by reading the contents of the

SSPBUF. The value can be used to determine if the

address was device specific or a general call address.

In 10-bit mode, the SSPADD is required to be updated

for the second half of the address to match, and the UA

bit is set (SSPSTAT<1>). If the general call address is

sampled when the GCEN bit is set, while the slave is

configured in 10-bit Address mode, then the second

half of the address is not necessary, the UA bit will not

be set, and the slave will begin receiving data after the

Acknowledge (Figure 16-15).

16.4.5

GENERAL CALL ADDRESS

SUPPORT

The addressing procedure for the I²C bus is such that,

the first byte after the START condition usually deter-

mines which device will be the slave addressed by the

master. The exception is the general call address,

which can address all devices. When this address is

used, all devices should, in theory, respond with an

Acknowledge.

The general call address is one of eight addresses

reserved for specific purposes by the I²C protocol. It

consists of all ‘0’s with R/W = 0.

The general call address is recognized when the Gen-

eral Call Enable bit (GCEN) is enabled (SSPCON2<7>

set). Following a START bit detect, 8-bits are shifted

into the SSPSR and the address is compared against

the SSPADD. It is also compared to the general call

address and fixed in hardware.

FIGURE 16-15:

SLAVE MODE GENERAL CALL ADDRESS SEQUENCE

(7 OR 10-BIT ADDRESS MODE)

Address is compared to General Call Address

after ACK, set interrupt

Receiving data

D5 D4 D3 D2 D1

ACK

9

R/W = 0

General Call Address

ACK

SDA

SCL

D7 D6

D0

8

1

2

3

4

5

6

7

8

9

1

2

3

4

5

6

7

S

SSPIF

BF (SSPSTAT<0>)

Cleared in software

SSPBUF is read

SSPOV (SSPCON1<6>)

GCEN (SSPCON2<7>)

'0'

'1'

DS30485A-page 148

Preliminary

 2002 Microchip Technology Inc.

PIC18FXX39

2

16.4.6

MASTER MODE

Note: The MSSP Module, when configured in I C

Master mode, does not allow queueing of

events. For instance, the user is not

allowed to initiate a START condition and

immediately write the SSPBUF register to

initiate transmission before the START

condition is complete. In this case, the

SSPBUF will not be written to and the

WCOL bit will be set, indicating that a write

to the SSPBUF did not occur.

Master mode is enabled by setting and clearing the

appropriate SSPM bits in SSPCON1 and by setting the

SSPEN bit. In Master mode, the SCL and SDA lines

are manipulated by the MSSP hardware.

Master mode of operation is supported by interrupt

generation on the detection of the START and STOP

conditions. The STOP (P) and START (S) bits are

cleared from a RESET or when the MSSP module is

2

disabled. Control of the I C bus may be taken when the

P bit is set or the bus is IDLE, with both the S and P bits

clear.

The following events will cause SSP interrupt flag bit,

SSPIF, to be set (SSP interrupt if enabled):

In Firmware Controlled Master mode, user code con-

• START condition

• STOP condition

• Data transfer byte transmitted/received

• Acknowledge Transmit

• Repeated START

2

ducts all I C bus operations based on START and

STOP bit conditions.

Once Master mode is enabled, the user has six

options.

1. Assert a START condition on SDA and SCL.

2. Assert a Repeated START condition on SDA

and SCL.

3. Write to the SSPBUF register initiating

transmission of data/address.

2

4. Configure the I C port to receive data.

5. Generate an Acknowledge condition at the end

of a received byte of data.

6. Generate a STOP condition on SDA and SCL.

2

FIGURE 16-16:

MSSP BLOCK DIAGRAM (I C MASTER MODE)

Internal

SSPM3:SSPM0

SSPADD<6:0>

Data Bus

Read

Write

SSPBUF

SSPSR

Baud

Rate

Generator

SDA

SCL

Shift

Clock

SDA in

MSb

LSb

START bit, STOP bit,

Acknowledge

Generate

START bit Detect

STOP bit Detect

SCL in

Bus Collision

Set/Reset, S, P, WCOL (SSPSTAT)

Write Collision Detect

Clock Arbitration

State Counter for

end of XMIT/RCV

Set SSPIF, BCLIF

Reset ACKSTAT, PEN (SSPCON2)

 2002 Microchip Technology Inc.

Preliminary

DS30485A-page 149

PIC18FXX39

16.4.6.1

I²C Master Mode Operation

A typical transmit sequence would go as follows:

1. The user generates a START condition by set-

The master device generates all of the serial clock

pulses and the START and STOP conditions. A trans-

fer is ended with a STOP condition, or with a Repeated

START condition. Since the Repeated START condi-

tion is also the beginning of the next serial transfer, the

ting

the

START

enable

bit,

SEN

(SSPCON2<0>).

2. SSPIF is set. The MSSP module will wait the

required start time before any other operation

takes place.

2

I C bus will not be released.

3. The user loads the SSPBUF with the slave

In Master Transmitter mode, serial data is output

through SDA, while SCL outputs the serial clock. The

first byte transmitted contains the slave address of the

receiving device (7 bits) and the Read/Write (R/W) bit.

In this case, the R/W bit will be logic '0'. Serial data is

transmitted 8 bits at a time. After each byte is transmit-

ted, an Acknowledge bit is received. START and STOP

conditions are output to indicate the beginning and the

end of a serial transfer.

In Master Receive mode, the first byte transmitted con-

tains the slave address of the transmitting device

(7 bits) and the R/W bit. In this case, the R/W bit will be

logic '1'. Thus, the first byte transmitted is a 7-bit slave

address followed by a '1' to indicate the receive bit.

Serial data is received via SDA, while SCL outputs the

serial clock. Serial data is received 8 bits at a time. After

each byte is received, an Acknowledge bit is transmit-

ted. START and STOP conditions indicate the

beginning and end of transmission.

address to transmit.

4. Address is shifted out the SDA pin until all 8 bits

are transmitted.

5. The MSSP module shifts in the ACK bit from the

slave device and writes its value into the

SSPCON2 register (SSPCON2<6>).

6. The MSSP module generates an interrupt at the

end of the ninth clock cycle by setting the SSPIF

bit.

7. The user loads the SSPBUF with eight bits of

data.

8. Data is shifted out the SDA pin until all 8 bits are

transmitted.

9. The MSSP module shifts in the ACK bit from the

slave device and writes its value into the

SSPCON2 register (SSPCON2<6>).

10. The MSSP module generates an interrupt at the

end of the ninth clock cycle by setting the SSPIF

bit.

The baud rate generator used for the SPI mode opera-

tion is used to set the SCL clock frequency for either

11. The user generates a STOP condition by setting

2

100 kHz, 400 kHz or 1 MHz I C operation. See

the STOP enable bit PEN (SSPCON2<2>).

Section 16.4.7 (“Baud Rate Generator”), for more

detail.

12. Interrupt is generated once the STOP condition

is complete.

DS30485A-page 150

Preliminary

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PIC18FXX39

Once the given operation is complete (i.e., transmis-

sion of the last data bit is followed by ACK), the internal

clock will automatically stop counting and the SCL pin

will remain in its last state.

Table 15-3 demonstrates clock rates based on

instruction cycles and the BRG value loaded into

SSPADD.

16.4.7

BAUD RATE GENERATOR

2

In I C Master mode, the baud rate generator (BRG)

reload value is placed in the lower 7 bits of the

SSPADD register (Figure 16-17). When a write occurs

to SSPBUF, the baud rate generator will automatically

begin counting. The BRG counts down to ‘0’ and stops

until another reload has taken place. The BRG count is

decremented twice per instruction cycle (TCY) on the

2

Q2 and Q4 clocks. In I C Master mode, the BRG is

reloaded automatically.

FIGURE 16-17:

BAUD RATE GENERATOR BLOCK DIAGRAM

SSPM3:SSPM0

SSPADD<6:0>

SSPM3:SSPM0

SCL

Reload

Control

Reload

BRG Down Counter

CLKO

FOSC/4

TABLE 16-3: I²C CLOCK RATE W/BRG

(2)

FSCL

FCY

FCY*2

BRG Value

(2 Rollovers of BRG)

(1)

10 MHz

4 MHz

1 MHz

20 MHz

8 MHz

2 MHz

19h

20h

3Fh

0Ah

0Dh

28h

03h

0Ah

400 kHz

312.5 kHz

100 kHz

(1)

400 kHz

308 kHz

100 kHz

(1)

333 kHz

100kHz

(1)

1 MHz

00h

1 MHz

2

Note 1: The I C interface does not conform to the 400 kHz I C specification (which applies to rates greater than

100 kHz) in all details, but may be used with care where higher rates are required by the application.

2: Actual frequency will depend on bus conditions. Theoretically, bus conditions will add rise time and extend

low time of clock period, producing the effective frequency.

 2002 Microchip Technology Inc.

Preliminary

DS30485A-page 151

PIC18FXX39

sampled high, the baud rate generator is reloaded with

the contents of SSPADD<6:0> and begins counting.

This ensures that the SCL high time will always be at

least one BRG rollover count, in the event that the clock

is held low by an external device (Figure 16-18).

16.4.7.1

Clock Arbitration

Clock arbitration occurs when the master, during any

receive, transmit or Repeated START/STOP condition,

de-asserts the SCL pin (SCL allowed to float high).

When the SCL pin is allowed to float high, the baud rate

generator (BRG) is suspended from counting until the

SCL pin is actually sampled high. When the SCL pin is

FIGURE 16-18:

BAUD RATE GENERATOR TIMING WITH CLOCK ARBITRATION

SDA

DX

DX-1

SCL allowed to transition high

SCL de-asserted but slave holds

SCL low (clock arbitration)

SCL

BRG decrements on

Q2 and Q4 cycles

BRG

Value

03h

02h

01h

00h (hold off)

03h

02h

SCL is sampled high, reload takes

place and BRG starts its count

BRG

Reload

DS30485A-page 152

Preliminary

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PIC18FXX39

WCOL Status Flag

If the user writes the SSPBUF when a START

sequence is in progress, the WCOL is set and the con-

tents of the buffer are unchanged (the write doesn’t

occur).

16.4.8

I²C MASTER MODE START

CONDITION TIMING

16.4.8.1

To initiate a START condition, the user sets the START

condition enable bit, SEN (SSPCON2<0>). If the SDA

and SCL pins are sampled high, the baud rate genera-

tor is reloaded with the contents of SSPADD<6:0> and

starts its count. If SCL and SDA are both sampled high

when the baud rate generator times out (TBRG), the

SDA pin is driven low. The action of the SDA being

driven low, while SCL is high, is the START condition

and causes the S bit (SSPSTAT<3>) to be set. Follow-

ing this, the baud rate generator is reloaded with the

contents of SSPADD<6:0> and resumes its count.

When the baud rate generator times out (TBRG), the

SEN bit (SSPCON2<0>) will be automatically cleared

by hardware, the baud rate generator is suspended,

leaving the SDA line held low and the START condition

is complete.

Note: Because queueing of events is not

allowed, writing to the lower 5 bits of

SSPCON2 is disabled until the START

condition is complete.

Note: If at the beginning of the START condition,

the SDA and SCL pins are already sam-

pled low, or if during the START condition

the SCL line is sampled low before the

SDA line is driven low, a bus collision

occurs, the Bus Collision Interrupt Flag,

BCLIF is set, the START condition is

2

aborted, and the I C module is reset into its

IDLE state.

FIGURE 16-19:

FIRST START BIT TIMING

Set S bit (SSPSTAT<3>)

Write to SEN bit occurs here

SDA = 1,

At completion of START bit,

Hardware clears SEN bit

and sets SSPIF bit

SCL = 1

TBRG

Write to SSPBUF occurs here

2nd bit

1st bit

SDA

TBRG

SCL

TBRG

S

 2002 Microchip Technology Inc.

Preliminary

DS30485A-page 153

PIC18FXX39

I²C MASTER MODE REPEATED

Immediately following the SSPIF bit getting set, the

user may write the SSPBUF with the 7-bit address in

7-bit mode, or the default first address in 10-bit mode.

After the first eight bits are transmitted and an ACK is

received, the user may then transmit an additional eight

bits of address (10-bit mode) or eight bits of data (7-bit

mode).

16.4.9

START CONDITION TIMING

A Repeated START condition occurs when the RSEN

bit (SSPCON2<1>) is programmed high and the I C

2

logic module is in the IDLE state. When the RSEN bit is

set, the SCL pin is asserted low. When the SCL pin is

sampled low, the baud rate generator is loaded with the

contents of SSPADD<5:0> and begins counting. The

SDA pin is released (brought high) for one baud rate

generator count (TBRG). When the baud rate generator

times out, if SDA is sampled high, the SCL pin will be

de-asserted (brought high). When SCL is sampled

high, the baud rate generator is reloaded with the con-

tents of SSPADD<6:0> and begins counting. SDA and

SCL must be sampled high for one TBRG. This action is

then followed by assertion of the SDA pin (SDA = 0) for

16.4.9.1

WCOL Status Flag

If the user writes the SSPBUF when a Repeated

START sequence is in progress, the WCOL is set and

the contents of the buffer are unchanged (the write

doesn’t occur).

Note: Because queueing of events is not

allowed, writing of the lower 5 bits of

SSPCON2 is disabled until the Repeated

START condition is complete.

one TBRG while SCL is high. Following this, the RSEN

,

bit (SSPCON2<1>) will be automatically cleared and

the baud rate generator will not be reloaded, leaving

the SDA pin held low. As soon as a START condition is

detected on the SDA and SCL pins, the S bit

(SSPSTAT<3>) will be set. The SSPIF bit will not be set

until the baud rate generator has timed out.

Note 1: If RSEN is programmed while any other

event is in progress, it will not take effect.

2: A bus collision during the Repeated

START condition occurs if:

• SDA is sampled low when SCL goes

from low to high.

• SCL goes low before SDA is

asserted low. This may indicate that

another master is attempting to

transmit a data "1".

FIGURE 16-20:

REPEAT START CONDITION WAVEFORM

Set S (SSPSTAT<3>)

Write to SSPCON2

occurs here.

SDA = 1,

SCL = 1

At completion of START bit,

hardware clears RSEN bit

and sets SSPIF

SDA = 1,

SCL (no change).

TBRG

1st bit

SDA

Write to SSPBUF occurs here

TBRG

Falling edge of ninth clock

End of Xmit

SCL

TBRG

Sr = Repeated START

DS30485A-page 154

Preliminary

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PIC18FXX39

16.4.10.3 ACKSTAT Status Flag

In Transmit mode, the ACKSTAT bit (SSPCON2<6>) is

cleared when the slave has sent an Acknowledge

(ACK = 0), and is set when the slave does not Acknowl-

edge (ACK = 1). A slave sends an Acknowledge when

it has recognized its address (including a general call),

or when the slave has properly received its data.

16.4.10 I²C MASTER MODE

TRANSMISSION

Transmission of a data byte, a 7-bit address, or the

other half of a 10-bit address is accomplished by simply

writing a value to the SSPBUF register. This action will

set the buffer full flag bit, BF, and allow the baud rate

generator to begin counting and start the next transmis-

sion. Each bit of address/data will be shifted out onto

the SDA pin after the falling edge of SCL is asserted

(see data hold time specification parameter 106). SCL

is held low for one baud rate generator rollover count

(TBRG). Data should be valid before SCL is released

high (see data setup time specification parameter 107).

When the SCL pin is released high, it is held that way

for TBRG. The data on the SDA pin must remain stable

for that duration and some hold time after the next fall-

ing edge of SCL. After the eighth bit is shifted out (the

falling edge of the eighth clock), the BF flag is cleared

and the master releases SDA. This allows the slave

device being addressed to respond with an ACK bit

during the ninth bit time, if an address match occurred,

or if data was received properly. The status of ACK is

written into the ACKDT bit on the falling edge of the

ninth clock. If the master receives an Acknowledge, the

Acknowledge status bit, ACKSTAT, is cleared. If not,

the bit is set. After the ninth clock, the SSPIF bit is set

and the master clock (baud rate generator) is sus-

pended until the next data byte is loaded into the

SSPBUF, leaving SCL low and SDA unchanged

(Figure 16-21).

After the write to the SSPBUF, each bit of address will

be shifted out on the falling edge of SCL until all seven

address bits and the R/W bit are completed. On the fall-

ing edge of the eighth clock, the master will de-assert

the SDA pin, allowing the slave to respond with an

Acknowledge. On the falling edge of the ninth clock, the

master will sample the SDA pin to see if the address

was recognized by a slave. The status of the ACK bit is

loaded into the ACKSTAT status bit (SSPCON2<6>).

Following the falling edge of the ninth clock transmis-

sion of the address, the SSPIF is set, the BF flag is

cleared and the baud rate generator is turned off until

another write to the SSPBUF takes place, holding SCL

low and allowing SDA to float.

16.4.11 I²C MASTER MODE RECEPTION

Master mode reception is enabled by programming the

receive enable bit, RCEN (SSPCON2<3>).

Note: In the MSSP module, the RCEN bit must

be set after the ACK sequence or the

RCEN bit will be disregarded.

The baud rate generator begins counting, and on each

rollover, the state of the SCL pin changes (high to low/

low to high) and data is shifted into the SSPSR. After

the falling edge of the eighth clock, the receive enable

flag is automatically cleared, the contents of the

SSPSR are loaded into the SSPBUF, the BF flag bit is

set, the SSPIF flag bit is set and the baud rate genera-

tor is suspended from counting, holding SCL low. The

MSSP is now in IDLE state, awaiting the next com-

mand. When the buffer is read by the CPU, the BF flag

bit is automatically cleared. The user can then send an

Acknowledge bit at the end of reception, by setting the

Acknowledge sequence enable bit, ACKEN

(SSPCON2<4>).

16.4.11.1 BF Status Flag

In receive operation, the BF bit is set when an address

or data byte is loaded into SSPBUF from SSPSR. It is

cleared when the SSPBUF register is read.

16.4.11.2 SSPOV Status Flag

In receive operation, the SSPOV bit is set when 8 bits

are received into the SSPSR and the BF flag bit is

already set from a previous reception.

16.4.11.3 WCOL Status Flag

If the user writes the SSPBUF when a receive is

already in progress (i.e., SSPSR is still shifting in a data

byte), the WCOL bit is set and the contents of the buffer

are unchanged (the write doesn’t occur).

16.4.10.1 BF Status Flag

In Transmit mode, the BF bit (SSPSTAT<0>) is set

when the CPU writes to SSPBUF and is cleared when

all 8 bits are shifted out.

16.4.10.2 WCOL Status Flag

If the user writes the SSPBUF when a transmit is

already in progress (i.e., SSPSR is still shifting out a

data byte), the WCOL is set and the contents of the

buffer are unchanged (the write doesn’t occur).

WCOL must be cleared in software.

 2002 Microchip Technology Inc.

Preliminary

DS30485A-page 155

PIC18FXX39

2

FIGURE 16-21:

I C MASTER MODE WAVEFORM (TRANSMISSION, 7 OR 10-BIT ADDRESS)

DS30485A-page 156

Preliminary

 2002 Microchip Technology Inc.

PIC18FXX39

I C MASTER MODE WAVEFORM (RECEPTION, 7-BIT ADDRESS)

2

FIGURE 16-22:

 2002 Microchip Technology Inc.

Preliminary

DS30485A-page 157

PIC18FXX39

16.4.12 ACKNOWLEDGE SEQUENCE

TIMING

16.4.13 STOP CONDITION TIMING

A STOP bit is asserted on the SDA pin at the end of a

receive/transmit by setting the STOP sequence enable

bit, PEN (SSPCON2<2>). At the end of a receive/

transmit the SCL line is held low after the falling edge

of the ninth clock. When the PEN bit is set, the master

will assert the SDA line low. When the SDA line is sam-

pled low, the baud rate generator is reloaded and

counts down to ‘0’. When the baud rate generator times

out, the SCL pin will be brought high, and one TBRG

(baud rate generator rollover count) later, the SDA pin

will be de-asserted. When the SDA pin is sampled high

while SCL is high, the P bit (SSPSTAT<4>) is set. A

TBRG later, the PEN bit is cleared and the SSPIF bit is

set (Figure 16-24).

An Acknowledge sequence is enabled by setting the

Acknowledge

sequence

enable

bit,

ACKEN

(SSPCON2<4>). When this bit is set, the SCL pin is

pulled low and the contents of the Acknowledge data bit

are presented on the SDA pin. If the user wishes to gen-

erate an Acknowledge, then the ACKDT bit should be

cleared. If not, the user should set the ACKDT bit before

starting an Acknowledge sequence. The baud rate gen-

erator then counts for one rollover period (TBRG) and the

SCL pin is de-asserted (pulled high). When the SCL pin

is sampled high (clock arbitration), the baud rate gener-

ator counts for TBRG. The SCL pin is then pulled low. Fol-

lowing this, the ACKEN bit is automatically cleared, the

baud rate generator is turned off and the MSSP module

then goes into IDLE mode (Figure 16-23).

16.4.13.1 WCOL Status Flag

If the user writes the SSPBUF when a STOP sequence

is in progress, then the WCOL bit is set and the con-

tents of the buffer are unchanged (the write doesn’t

occur).

16.4.12.1 WCOL Status Flag

If the user writes the SSPBUF when an Acknowledge

sequence is in progress, then WCOL is set and the con-

tents of the buffer are unchanged (the write doesn’t occur).

FIGURE 16-23:

ACKNOWLEDGE SEQUENCE WAVEFORM

Acknowledge sequence starts here,

Write to SSPCON2

ACKEN automatically cleared

ACKEN = 1, ACKDT = 0

TBRG

ACK

TBRG

SDA

SCL

D0

8

9

SSPIF

Cleared in

Set SSPIF at the end

of receive

Cleared in

software

Set SSPIF at the end

of Acknowledge sequence

Note: TBRG = one baud rate generator period.

FIGURE 16-24:

STOP CONDITION RECEIVE OR TRANSMIT MODE

SCL = 1 for TBRG, followed by SDA = 1 for TBRG

Write to SSPCON2

Set PEN

after SDA sampled high. P bit (SSPSTAT<4>) is set.

PEN bit (SSPCON2<2>) is cleared by

hardware and the SSPIF bit is set

Falling edge of

9th clock

TBRG

SCL

SDA

ACK

P

TBRG

SCL brought high after TBRG

SDA asserted low before rising edge of clock

to setup STOP condition.

Note: TBRG = one baud rate generator period.

DS30485A-page 158

Preliminary

 2002 Microchip Technology Inc.

PIC18FXX39

16.4.14 SLEEP OPERATION

16.4.17 MULTI -MASTER COMMUNICATION,

BUS COLLISION, AND BUS

ARBITRATION

2

While in SLEEP mode, the I C module can receive

addresses or data, and when an address match or

complete byte transfer occurs, wake the processor

from SLEEP (if the MSSP interrupt is enabled).

Multi-Master mode support is achieved by bus arbitra-

tion. When the master outputs address/data bits onto

the SDA pin, arbitration takes place when the master

outputs a '1' on SDA, by letting SDA float high and

another master asserts a '0'. When the SCL pin floats

high, data should be stable. If the expected data on

SDA is a '1' and the data sampled on the SDA pin = '0',

then a bus collision has taken place. The master will set

16.4.15 EFFECT OF A RESET

A RESET disables the MSSP module and terminates

the current transfer.

16.4.16 MULTI-MASTER MODE

2

the Bus Collision Interrupt Flag BCLIF and reset the I C

In Multi-Master mode, the interrupt generation on the

detection of the START and STOP conditions allows the

determination of when the bus is free. The STOP (P)

and START (S) bits are cleared from a RESET, or when

port to its IDLE state (Figure 16-25).

If a transmit was in progress when the bus collision

occurred, the transmission is halted, the BF flag is

cleared, the SDA and SCL lines are de-asserted, and

the SSPBUF can be written to. When the user services

the bus collision Interrupt Service Routine, and if the

2

the MSSP module is disabled. Control of the I C bus

may be taken when the P bit (SSPSTAT<4>) is set, or

the bus is IDLE, with both the S and P bits clear. When

the bus is busy, enabling the SSP interrupt will generate

the interrupt when the STOP condition occurs.

2

I C bus is free, the user can resume communication by

asserting a START condition.

If a START, Repeated START, STOP, or Acknowledge

condition was in progress when the bus collision

occurred, the condition is aborted, the SDA and SCL

lines are de-asserted, and the respective control bits in

the SSPCON2 register are cleared. When the user ser-

vices the bus collision Interrupt Service Routine, and if

the I²C bus is free, the user can resume communication

by asserting a START condition.

In multi-master operation, the SDA line must be moni-

tored for arbitration, to see if the signal level is the

expected output level. This check is performed in

hardware, with the result placed in the BCLIF bit.

The states where arbitration can be lost are:

• Address Transfer

• Data Transfer

The master will continue to monitor the SDA and SCL

pins. If a STOP condition occurs, the SSPIF bit will be set.

A write to the SSPBUF will start the transmission of

data at the first data bit, regardless of where the

transmitter left off when the bus collision occurred.

• A START Condition

• A Repeated START Condition

• An Acknowledge Condition

In Multi-Master mode, the interrupt generation on the

detection of START and STOP conditions allows the

2

determination of when the bus is free. Control of the I C

bus can be taken when the P bit is set in the SSPSTAT

register, or the bus is IDLE and the S and P bits are

cleared.

FIGURE 16-25:

BUS COLLISION TIMING FOR TRANSMIT AND ACKNOWLEDGE

Sample SDA. While SCL is high,

data doesn’t match what is driven

by the master.

SDA line pulled low

by another source

Data changes

while SCL = 0

Bus collision has occurred.

SDA released

by master

SDA

SCL

Set bus collision

interrupt (BCLIF)

BCLIF

 2002 Microchip Technology Inc.

Preliminary

DS30485A-page 159

PIC18FXX39

If the SDA pin is sampled low during this count, the

BRG is reset and the SDA line is asserted early

(Figure 16-28). If, however, a '1' is sampled on the SDA

pin, the SDA pin is asserted low at the end of the BRG

count. The baud rate generator is then reloaded and

counts down to ‘0’, and during this time, if the SCL pins

are sampled as '0', a bus collision does not occur. At

the end of the BRG count, the SCLpin is asserted low.

16.4.17.1 Bus Collision During a START

Condition

During a START condition, a bus collision occurs if:

a) SDA or SCL are sampled low at the beginning of

the START condition (Figure 16-26).

b) SCL is sampled low before SDA is asserted low

(Figure 16-27).

During a START condition, both the SDA and the SCL

pins are monitored.

If the SDA pin is already low, or the SCL pin is already

low, then all of the following occur:

• the START condition is aborted,

• the BCLIF flag is set, and

• the MSSP module is reset to its IDLE state

(Figure 16-26).

The START condition begins with the SDA and SCL

pins de-asserted. When the SDA pin is sampled high,

the baud rate generator is loaded from SSPADD<6:0>

and counts down to ‘0’. If the SCL pin is sampled low

while SDA is high, a bus collision occurs, because it is

assumed that another master is attempting to drive a

data '1' during the START condition.

Note: The reason that bus collision is not a factor

during a START condition, is that no two

bus masters can assert a START condition

at the exact same time. Therefore, one

master will always assert SDA before the

other. This condition does not cause a bus

collision, because the two masters must be

allowed to arbitrate the first address follow-

ing the START condition. If the address is

the same, arbitration must be allowed to

continue into the data portion, Repeated

START or STOP conditions.

FIGURE 16-26:

BUS COLLISION DURING START CONDITION (SDA ONLY)

SDA goes low before the SEN bit is set.

Set BCLIF,

S bit and SSPIF set because

SDA = 0, SCL = 1.

SDA

SCL

SEN

Set SEN, enable START

condition if SDA = 1, SCL = 1

SEN cleared automatically because of bus collision.

SSP module reset into IDLE state.

SDA sampled low before

START condition. Set BCLIF.

S bit and SSPIF set because

SDA = 0, SCL = 1.

BCLIF

SSPIF and BCLIF are

cleared in software.

S

SSPIF

SSPIF and BCLIF are

cleared in software.

DS30485A-page 160

Preliminary

 2002 Microchip Technology Inc.

PIC18FXX39

FIGURE 16-27:

BUS COLLISION DURING START CONDITION (SCL = 0)

SDA = 0, SCL = 1

TBRG

SDA

Set SEN, enable START

SCL

SEN

sequence if SDA = 1, SCL = 1

SCL = 0 before SDA = 0,

bus collision occurs. Set BCLIF.

SCL = 0 before BRG time-out,

bus collision occurs. Set BCLIF.

BCLIF

Interrupt cleared

in software

S

'0'

SSPIF

FIGURE 16-28:

BRG RESET DUE TO SDA ARBITRATION DURING START CONDITION

SDA = 0, SCL = 1

Set S

Set SSPIF

Less than TBRG

TBRG

SDA pulled low by other master.

Reset BRG and assert SDA.

SDA

SCL

S

SCL pulled low after BRG

Time-out

SEN

Set SEN, enable START

sequence if SDA = 1, SCL = 1

'0'

BCLIF

S

SSPIF

Interrupts cleared

in software

SDA = 0, SCL = 1

Set SSPIF

 2002 Microchip Technology Inc.

Preliminary

DS30485A-page 161

PIC18FXX39

reloaded and begins counting. If SDA goes from high to

low before the BRG times out, no bus collision occurs

because no two masters can assert SDA at exactly the

same time.

If SCL goes from high to low before the BRG times out

and SDA has not already been asserted, a bus collision

occurs. In this case, another master is attempting to

transmit a data ‘1’ during the Repeated START

condition, see Figure 16-30.

If, at the end of the BRG time-out, both SCL and SDA

are still high, the SDA pin is driven low and the BRG is

reloaded and begins counting. At the end of the count,

regardless of the status of the SCL pin, the SCL pin is

driven low and the Repeated START condition is

complete.

16.4.17.2 Bus Collision During a Repeated

START Condition

During a Repeated START condition, a bus collision

occurs if:

a) A low level is sampled on SDA when SCL goes

from low level to high level.

b) SCL goes low before SDA is asserted low, indi-

cating that another master is attempting to

transmit a data ‘1’.

When the user de-asserts SDA and the pin is allowed to

float high, the BRG is loaded with SSPADD<6:0> and

counts down to ‘0’. The SCL pin is then de-asserted,

and when sampled high, the SDA pin is sampled.

If SDA is low, a bus collision has occurred (i.e., another

master is attempting to transmit

a

data ’0’,

Figure 16-29). If SDA is sampled high, the BRG is

FIGURE 16-29:

BUS COLLISION DURING A REPEATED START CONDITION (CASE 1)

SDA

SCL

Sample SDA when SCL goes high.

If SDA = 0, set BCLIF and release SDA and SCL.

RSEN

BCLIF

Cleared in software

'0'

S

'0'

SSPIF

FIGURE 16-30:

BUS COLLISION DURING REPEATED START CONDITION (CASE 2)

TBRG

SDA

SCL

SCL goes low before SDA,

BCLIF

RSEN

Set BCLIF. Release SDA and SCL.

Interrupt cleared

in software

'0'

S

SSPIF

DS30485A-page 162

Preliminary

 2002 Microchip Technology Inc.

PIC18FXX39

The STOP condition begins with SDA asserted low.

When SDA is sampled low, the SCL pin is allowed to

float. When the pin is sampled high (clock arbitration),

the baud rate generator is loaded with SSPADD<6:0>

and counts down to ‘0’. After the BRG times out, SDA

is sampled. If SDA is sampled low, a bus collision has

occurred. This is due to another master attempting to

drive a data '0' (Figure 16-31). If the SCL pin is sampled

low before SDA is allowed to float high, a bus collision

occurs. This is another case of another master

attempting to drive a data '0' (Figure 16-32).

16.4.17.3 Bus Collision During a STOP

Condition

Bus collision occurs during a STOP condition if:

a) After the SDA pin has been de-asserted and

allowed to float high, SDA is sampled low after

the BRG has timed out.

b) After the SCL pin is de-asserted, SCL is

sampled low before SDA goes high.

FIGURE 16-31:

BUS COLLISION DURING A STOP CONDITION (CASE 1)

SDA sampled

low after TBRG,

Set BCLIF

TBRG

SDA

SDA asserted low

SCL

PEN

BCLIF

P

'0'

SSPIF

FIGURE 16-32:

BUS COLLISION DURING A STOP CONDITION (CASE 2)

TBRG

SDA

SCL goes low before SDA goes high,

Set BCLIF

Assert SDA

SCL

PEN

BCLIF

P

'0'

SSPIF

 2002 Microchip Technology Inc.

Preliminary

DS30485A-page 163

PIC18FXX39

NOTES:

DS30485A-page 164

Preliminary

 2002 Microchip Technology Inc.

PIC18FXX39

17.0 ADDRESSABLE UNIVERSAL

SYNCHRONOUS

ASYNCHRONOUS RECEIVER

TRANSMITTER (USART)

The Universal Synchronous Asynchronous Receiver

Transmitter (USART) module is one of the two serial

I/O modules. (USART is also known as a Serial Com-

munications Interface or SCI.) The USART can be con-

figured as a full-duplex asynchronous system that can

communicate with peripheral devices, such as CRT ter-

minals and personal computers, or it can be configured

as a half-duplex synchronous system that can commu-

nicate with peripheral devices, such as A/D or D/A

integrated circuits, serial EEPROMs, etc.

The USART can be configured in the following modes:

• Asynchronous (full-duplex)

• Synchronous - Master (half-duplex)

• Synchronous - Slave (half-duplex)

In order to configure pins RC6/TX/CK and RC7/RX/DT

as the Universal Synchronous Asynchronous Receiver

Transmitter:

• bit SPEN (RCSTA<7>) must be set (= 1),

• bit TRISC<6> must be cleared (= 0), and

• bit TRISC<7> must be set (= 1).

Register 17-1 shows the Transmit Status and Control

Register (TXSTA) and Register 17-2 shows the

Receive Status and Control Register (RCSTA).

 2002 Microchip Technology Inc.

Preliminary

DS30485A-page 165

PIC18FXX39

REGISTER 17-1: TXSTA: TRANSMIT STATUS AND CONTROL REGISTER

R/W-0

CSRC

bit 7

R/W-0

TX9

R/W-0

TXEN

R/W-0

SYNC

U-0

—

R/W-0

BRGH

R-1

TRMT

R/W-0

TX9D

bit 0

bit 7

CSRC: Clock Source Select bit

Asynchronous mode:

Don’t care

Synchronous mode:

1= Master mode (clock generated internally from BRG)

0= Slave mode (clock from external source)

bit 6

bit 5

TX9: 9-bit Transmit Enable bit

1= Selects 9-bit transmission

0= Selects 8-bit transmission

TXEN: Transmit Enable bit

1= Transmit enabled

0= Transmit disabled

Note:

SREN/CREN overrides TXEN in SYNC mode.

bit 4

SYNC: USART Mode Select bit

1= Synchronous mode

0= Asynchronous mode

bit 3

bit 2

Unimplemented: Read as '0'

BRGH: High Baud Rate Select bit

Asynchronous mode:

1= High speed

0= Low speed

Synchronous mode:

Unused in this mode

bit 1

bit 0

TRMT: Transmit Shift Register Status bit

1= TSR empty

0= TSR full

TX9D: 9th bit of Transmit Data

Can be Address/Data bit or a parity bit

Legend:

R = Readable bit

- n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

DS30485A-page 166

Preliminary

 2002 Microchip Technology Inc.

PIC18FXX39

REGISTER 17-2: RCSTA: RECEIVE STATUS AND CONTROL REGISTER

R/W-0

SPEN

bit 7

R/W-0

RX9

R/W-0

SREN

R/W-0

CREN

R/W-0

ADDEN

R-0

FERR

R-0

OERR

R-x

RX9D

bit 0

bit 7

bit 6

bit 5

SPEN: Serial Port Enable bit

1= Serial port enabled (configures RX/DT and TX/CK pins as serial port pins)

0= Serial port disabled

RX9: 9-bit Receive Enable bit

1= Selects 9-bit reception

0= Selects 8-bit reception

SREN: Single Receive Enable bit

Asynchronous mode:

Don’t care

Synchronous mode - Master:

1= Enables single receive

0= Disables single receive

This bit is cleared after reception is complete.

Synchronous mode - Slave:

Don’t care

bit 4

bit 3

CREN: Continuous Receive Enable bit

Asynchronous mode:

1= Enables receiver

0= Disables receiver

Synchronous mode:

1= Enables continuous receive until enable bit CREN is cleared (CREN overrides SREN)

0= Disables continuous receive

ADDEN: Address Detect Enable bit

Asynchronous mode 9-bit (RX9 = 1):

1= Enables address detection, enables interrupt and load of the receive buffer

when RSR<8> is set

0= Disables address detection, all bytes are received, and ninth bit can be used as parity bit

bit 2

bit 1

bit 0

FERR: Framing Error bit

1= Framing error (can be updated by reading RCREG register and receive next valid byte)

0= No framing error

OERR: Overrun Error bit

1= Overrun error (can be cleared by clearing bit CREN)

0= No overrun error

RX9D: 9th bit of Received Data

This can be Address/Data bit or a parity bit, and must be calculated by user firmware

Legend:

R = Readable bit

- n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

 2002 Microchip Technology Inc.

Preliminary

DS30485A-page 167

PIC18FXX39

Example 17-1 shows the calculation of the baud rate

error for the following conditions:

• FOSC = 16 MHz

• Desired Baud Rate = 9600

• BRGH = 0

17.1 USART Baud Rate Generator

(BRG)

The BRG supports both the Asynchronous and Syn-

chronous modes of the USART. It is a dedicated 8-bit

baud rate generator. The SPBRG register controls the

period of a free running 8-bit timer. In Asynchronous

mode, bit BRGH (TXSTA<2>) also controls the baud

rate. In Synchronous mode, bit BRGH is ignored.

Table 17-1 shows the formula for computation of the

baud rate for different USART modes, which only apply

in Master mode (internal clock).

Given the desired baud rate and FOSC, the nearest

integer value for the SPBRG register can be calculated

using the formula in Table 17-1. From this, the error in

baud rate can be determined.

• SYNC = 0

It may be advantageous to use the high baud rate

(BRGH = 1) even for slower baud clocks. This is

because the FOSC/(16(X + 1)) equation can reduce the

baud rate error in some cases.

Writing a new value to the SPBRG register causes the

BRG timer to be reset (or cleared). This ensures the

BRG does not wait for a timer overflow before

outputting the new baud rate.

17.1.1

SAMPLING

The data on the RC7/RX/DT pin is sampled three times

by a majority detect circuit to determine if a high or a

low level is present at the RX pin.

EXAMPLE 17-1:

Desired Baud Rate

Solving for X:

CALCULATING BAUD RATE ERROR

=

FOSC / (64 (X + 1))

X

=

( (FOSC / Desired Baud Rate) / 64 ) – 1

((16000000 / 9600) / 64) – 1

[25.042] = 25

Calculated Baud Rate

=

16000000 / (64 (25 + 1))

9615

Error

=

(Calculated Baud Rate – Desired Baud Rate)

Desired Baud Rate

(9615 – 9600) / 9600

0.16%

=

TABLE 17-1: BAUD RATE FORMULA

SYNC

BRGH = 0 (Low Speed)

BRGH = 1 (High Speed)

0

1

(Asynchronous) Baud Rate = FOSC/(64(X+1))

(Synchronous) Baud Rate = FOSC/(4(X+1))

Baud Rate = FOSC/(16(X+1))

N/A

Legend: X = value in SPBRG (0 to 255)

TABLE 17-2: REGISTERS ASSOCIATED WITH BAUD RATE GENERATOR

Value on

All Other

RESETS

Value on

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

POR, BOR

TXSTA

RCSTA

SPBRG

CSRC

SPEN

TX9

RX9

TXEN SYNC

—

BRGH TRMT TX9D 0000 -010

0000 -010

0000 -00x

0000 0000

SREN CREN ADDEN FERR OERR RX9D 0000 -00x

0000 0000

Baud Rate Generator Register

Legend: x= unknown, - = unimplemented, read as '0'. Shaded cells are not used by the BRG.

DS30485A-page 168

Preliminary

 2002 Microchip Technology Inc.

PIC18FXX39

TABLE 17-3: BAUD RATES FOR SYNCHRONOUS MODE

FOSC = 40 MHz

33 MHz

25 MHz

20 MHz

BAUD

RATE

SPBRG

value

SPBRG

value

SPBRG

value

%

(Kbps)

(decimal)

KBAUD ERROR

KBAUD

ERROR

KBAUD ERROR

0.3

1.2

NA

-

NA

-

NA

-

NA

-

2.4

NA

-

NA

-

NA

-

NA

-

9.6

NA

-

NA

-

NA

-

NA

-

64

51

16

9

19.2

76.8

96

300

500

HIGH

LOW

76.92

96.15

303.03

500

10000

39.06

+0.16

+1.01

0

-

129

103

32

19

0

77.10

95.93

294.64

485.30

8250

32.23

+0.39

-0.07

-1.79

-2.94

-

106

85

27

16

0

77.16

96.15

297.62

480.77

6250

24.41

+0.47

+0.16

-0.79

-3.85

-

80

64

20

12

0

76.92

96.15

294.12

500

5000

19.53

+0.16

-1.96

0

-

0

255

-

255

-

255

-

255

-

FOSC = 16 MHz

10 MHz

7.15909 MHz

5.0688 MHz

BAUD

RATE

SPBRG

value

SPBRG

value

SPBRG

value

SPBRG

value

%

(Kbps)

(decimal)

KBAUD ERROR

KBAUD

ERROR

KBAUD ERROR

0.3

1.2

NA

-

NA

-

NA

-

NA

-

2.4

NA

-

NA

-

NA

-

NA

-

9.6

NA

-

+0.16

-0.79

+2.56

0

-

NA

-

+0.16

-1.36

+0.16

+4.17

0

-

9.62

+0.23

+1.32

-1.88

-0.57

-10.51

-

185

92

22

18

5

3

0

255

9.60

0

131

65

16

12

3

2

0

255

19.2

76.8

96

300

500

HIGH

LOW

19.23

76.92

95.24

307.70

500

207

51

41

12

7

19.23

75.76

96.15

312.50

500

129

32

25

7

4

0

19.24

77.82

94.20

298.35

447.44

1789.80

6.99

19.20

74.54

97.48

316.80

422.40

1267.20

4.95

-2.94

+1.54

+5.60

-15.52

-

4000

15.63

-

0

255

2500

9.77

-

255

-

FOSC = 4 MHz

3.579545 MHz

1 MHz

32.768 kHz

BAUD

RATE

SPBRG

value

SPBRG

value

SPBRG

value

SPBRG

value

%

(Kbps)

(decimal)

KBAUD ERROR

KBAUD

ERROR

KBAUD ERROR

0.3

1.2

2.4

NA

9.62

19.23

76.92

1000

333.33

500

-

NA

-

92

46

11

8

2

1

0

255

NA

1.20

2.40

9.62

19.23

83.33

250

-

207

103

25

12

2

0

-

0

0.30

1.17

2.73

8.20

NA

+1.14

-2.48

+13.78

-14.67

-

26

6

2

0

-

+0.16

+8.51

-13.19

-16.67

-

9.6

+0.16

+4.17

+11.11

0

103

51

12

9

2

1

9.62

+0.23

-0.83

-2.90

+3.57

-0.57

-10.51

-

19.2

76.8

96

300

500

HIGH

LOW

19.04

74.57

99.43

298.30

447.44

894.89

3.50

NA

250

0.98

1000

3.91

-

0

255

-

8.20

0.03

0

255

-

255

 2002 Microchip Technology Inc.

Preliminary

DS30485A-page 169

PIC18FXX39

TABLE 17-4: BAUD RATES FOR ASYNCHRONOUS MODE (BRGH = 0)

FOSC = 40 MHz

33 MHz

25 MHz

20 MHz

BAUD

RATE

SPBRG

value

SPBRG

value

SPBRG

value

SPBRG

value

%

(Kbps)

(decimal)

KBAUD ERROR

KBAUD

ERROR

KBAUD

ERROR

KBAUD ERROR

0.3

1.2

NA

-

NA

-

NA

-

NA

-

2.4

9.6

NA

-

2.40

9.55

-0.07

-0.54

-4.09

+7.42

-14.06

-

214

53

26

6

4

1

-

0

255

2.40

9.53

19.53

78.13

97.66

NA

390.63

1.53

-0.15

-0.76

+1.73

162

40

19

4

3

-

0

255

2.40

9.47

+0.16

-1.36

+1.73

+8.51

+4.17

-

129

32

15

3

2

0

-

0

255

9.62

18.94

78.13

89.29

312.50

625

+0.16

-1.36

+1.73

-6.99

+4.17

+25.00

-

64

32

7

6

1

0

255

19.2

76.8

96

300

500

HIGH

LOW

19.10

73.66

103.13

257.81

NA

19.53

78.13

104.17

312.50

NA

+1.73

-

625

2.44

515.63

2.01

-

312.50

1.22

-

FOSC = 16 MHz

10 MHz

7.15909 MHz

5.0688 MHz

BAUD

RATE

SPBRG

value

SPBRG

value

SPBRG

value

SPBRG

value

%

(Kbps)

(decimal)

KBAUD ERROR

KBAUD

ERROR

KBAUD

ERROR

KBAUD ERROR

0.3

1.2

2.4

NA

1.20

2.40

9.62

19.23

83.33

250

-

207

103

25

12

2

0

-

0

NA

1.20

2.40

-

129

64

15

7

1

0

-

NA

1.20

2.38

9.32

18.64

111.86

NA

111.86

0.44

-

92

46

11

5

0

-

NA

1.20

2.40

9.90

19.80

79.20

NA

79.20

0.31

-

0

-

65

32

7

3

0

-

0

+0.16

+8.51

-13.19

-16.67

-

+0.16

+1.73

-18.62

-47.92

-

+0.23

-0.83

-2.90

9.6

9.77

+3.13

-

19.2

76.8

96

300

500

HIGH

LOW

19.53

78.13

156.25

NA

+45.65

-

NA

250

0.98

-

156.25

0.61

-

0

255

0

255

FOSC = 4 MHz

3.579545 MHz

%

1 MHz

32.768 kHz

BAUD

RATE

SPBRG

value

SPBRG

value

SPBRG

value

SPBRG

value

%

(Kbps)

(decimal)

KBAUD ERROR

KBAUD

ERROR

KBAUD

ERROR

KBAUD ERROR

0.3

1.2

2.4

0.30

1.20

2.40

8.93

20.83

62.50

NA

62.50

0.24

-0.16

+1.67

-6.99

+8.51

-18.62

-

207

51

25

6

2

0

-

0

0.30

1.19

2.43

9.32

18.64

55.93

NA

55.93

0.22

+0.23

-0.83

+1.32

-2.90

-27.17

-

185

46

22

5

2

0

-

0

0.30

1.20

2.23

7.81

15.63

NA

15.63

0.06

+0.16

-6.99

-18.62

51

12

6

1

0

-

0.26

NA

-14.67

1

-

9.6

19.2

76.8

96

300

500

HIGH

LOW

-18.62

-

0

255

0.51

0.002

0

255

DS30485A-page 170

Preliminary

 2002 Microchip Technology Inc.

PIC18FXX39

TABLE 17-5: BAUD RATES FOR ASYNCHRONOUS MODE (BRGH = 1)

FOSC = 40 MHz

33 MHz

25 MHz

20 MHz

BAUD

RATE

SPBRG

value

SPBRG

value

SPBRG

value

%

(Kbps)

(decimal)

KBAUD ERROR

0.3

1.2

NA

-

NA

-

NA

-

NA

-

2.4

NA

-

NA

-

NA

-

NA

-

9.6

NA

-

+0.16

-1.36

+0.16

+4.17

0

-

9.60

-0.07

+0.39

-0.54

+2.31

-1.79

+3.13

-

214

106

26

20

6

3

0

255

9.59

-0.15

+0.47

+1.73

+4.17

-

162

80

19

15

4

2

0

255

9.62

+0.16

+1.73

+0.16

+4.17

-16.67

-

129

64

15

12

3

2

0

255

19.2

76.8

96

300

500

HIGH

LOW

19.23

75.76

96.15

312.50

500

129

32

25

7

4

0

19.28

76.39

98.21

294.64

515.63

2062.50

8,06

19.30

78.13

97.66

312.50

520.83

1562.50

6.10

19.23

78.13

96.15

312.50

416.67

1250

4.88

2500

9.77

-

255

-

FOSC = 16 MHz

10 MHz

7.15909 MHz

5.0688 MHz

BAUD

RATE

SPBRG

value

SPBRG

value

SPBRG

value

SPBRG

value

%

(Kbps)

(decimal)

KBAUD ERROR

0.3

1.2

NA

-

NA

-

NA

-

NA

-

2.4

9.6

NA

-

+0.16

+4.17

+11.11

0

-

NA

-

2.41

9.52

+0.23

-0.83

+1.32

-2.90

-6.78

+49.15

-10.51

-

185

46

22

5

4

0

255

2.40

9.60

0

131

32

16

3

2

0

-

0

255

9.62

19.23

76.92

100

333.33

500

103

51

12

9

2

1

9.62

18.94

78.13

89.29

312.50

625

+0.16

-1.36

+1.73

-6.99

+4.17

+25.00

-

64

32

7

6

1

0

255

0

-2.94

+3.13

+10.00

+5.60

-

19.2

76.8

96

300

500

HIGH

LOW

19.45

74.57

89.49

447.44

1.75

18.64

79.20

105.60

316.80

NA

1000

3.91

-

0

255

625

2.44

316.80

1.24

-

FOSC = 4 MHz

3.579545 MHz

1 MHz

32.768 kHz

BAUD

RATE

SPBRG

value

SPBRG

value

SPBRG

value

SPBRG

value

%

(Kbps)

(decimal)

KBAUD ERROR

0.3

1.2

2.4

NA

1.20

2.40

9.62

19.23

NA

250

0.98

-

207

103

25

12

-

0

NA

1.20

2.41

-

+0.23

+1.32

-2.90

+16.52

-25.43

-

185

92

22

11

2

1

0

-

0

0.30

1.20

2.40

8.93

20.83

62.50

NA

62.50

0.24

+0.16

-6.99

+8.51

-18.62

-

207

51

25

6

2

0

-

0

0.29

1.02

2.05

NA

2.05

0.008

-2.48

-14.67

6

1

0

-

+0.16

-

9.6

9.73

-

19.2

76.8

96

300

500

HIGH

LOW

18.64

74.57

111.86

223.72

NA

55.93

0.22

-

0

255

 2002 Microchip Technology Inc.

Preliminary

DS30485A-page 171

PIC18FXX39

flag bit TXIF (PIR1<4>) is set. This interrupt can be

enabled/disabled by setting/clearing enable bit TXIE

( PIE1<4>). Flag bit TXIF will be set, regardless of the

state of enable bit TXIE and cannot be cleared in soft-

ware. It will reset only when new data is loaded into the

TXREG register. While flag bit TXIF indicated the sta-

tus of the TXREG register, another bit, TRMT

(TXSTA<1>), shows the status of the TSR register. Sta-

tus bit TRMT is a read only bit, which is set when the

TSR register is empty. No interrupt logic is tied to this

bit, so the user has to poll this bit in order to determine

if the TSR register is empty.

17.2 USART Asynchronous Mode

In this mode, the USART uses standard non-return-to-

zero (NRZ) format (one START bit, eight or nine data

bits and one STOP bit). The most common data format

is 8-bits. An on-chip dedicated 8-bit baud rate genera-

tor can be used to derive standard baud rate frequen-

cies from the oscillator. The USART transmits and

receives the LSb first. The USART’s transmitter and

receiver are functionally independent, but use the

same data format and baud rate. The baud rate gener-

ator produces a clock, either x16 or x64 of the bit shift

rate, depending on bit BRGH (TXSTA<2>). Parity is not

supported by the hardware, but can be implemented in

software (and stored as the ninth data bit).

Asynchronous mode is stopped during SLEEP.

Note 1: The TSR register is not mapped in data

memory, so it is not available to the user.

2: Flag bit TXIF is set when enable bit TXEN

is set.

Asynchronous mode is selected by clearing bit SYNC

(TXSTA<4>).

To set up an asynchronous transmission:

The USART Asynchronous module consists of the

following important elements:

• Baud Rate Generator

• Sampling Circuit

• Asynchronous Transmitter

• Asynchronous Receiver

1. Initialize the SPBRG register for the appropriate

baud rate. If a high speed baud rate is desired,

set bit BRGH (Section 17.1).

2. Enable the asynchronous serial port by clearing

bit SYNC and setting bit SPEN.

3. If interrupts are desired, set enable bit TXIE.

4. If 9-bit transmission is desired, set transmit bit

TX9. Can be used as address/data bit.

17.2.1

USART ASYNCHRONOUS

TRANSMITTER

5. Enable the transmission by setting bit TXEN,

which will also set bit TXIF.

The USART transmitter block diagram is shown in

Figure 17-1. The heart of the transmitter is the Transmit

(serial) Shift Register (TSR). The shift register obtains

its data from the read/write transmit buffer, TXREG. The

TXREG register is loaded with data in software. The

TSR register is not loaded until the STOP bit has been

transmitted from the previous load. As soon as the

STOP bit is transmitted, the TSR is loaded with new

data from the TXREG register (if available). Once the

TXREG register transfers the data to the TSR register

(occurs in one TCY), the TXREG register is empty and

6. If 9-bit transmission is selected, the ninth bit

should be loaded in bit TX9D.

7. Load data to the TXREG register (starts

transmission).

Note: TXIF is not cleared immediately upon load-

ing data into the transmit buffer TXREG.

The flag bit becomes valid in the second

instruction cycle following the load

instruction.

FIGURE 17-1:

USART TRANSMIT BLOCK DIAGRAM

Data Bus

TXIF

TXREG Register

8

TXIE

MSb

(8)

LSb

0

Pin Buffer

•

• •

and Control

TSR Register

RC6/TX/CK pin

Interrupt

TXEN

Baud Rate CLK

TRMT

SPEN

SPBRG

Baud Rate Generator

TX9

TX9D

DS30485A-page 172

Preliminary

 2002 Microchip Technology Inc.

PIC18FXX39

FIGURE 17-2:

ASYNCHRONOUS TRANSMISSION

Write to TXREG

Word 1

BRG Output

(Shift Clock)

RC6/TX/CK (pin)

START bit

bit 0

bit 1

Word 1

bit 7/8

STOP bit

TXIF bit

(Transmit Buffer

Reg. Empty Flag)

Word 1

Transmit Shift Reg

TRMT bit

(Transmit Shift

Reg. Empty Flag)

FIGURE 17-3:

ASYNCHRONOUS TRANSMISSION (BACK TO BACK)

Write to TXREG

Word 2

Word 1

BRG Output

(Shift Clock)

RC6/TX/CK (pin)

START bit

Word 2

bit 0

bit 1

Word 1

bit 7/8

bit 0

STOP bit

TXIF bit

(Interrupt Reg. Flag)

TRMT bit

(Transmit Shift

Word 1

Transmit Shift Reg.

Word 2

Transmit Shift Reg.

Reg. Empty Flag)

Note: This timing diagram shows two consecutive transmissions.

TABLE 17-6: REGISTERS ASSOCIATED WITH ASYNCHRONOUS TRANSMISSION

Value on

All Other

RESETS

Value on

POR, BOR

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF

RBIF

0000 000x 0000 000u

(1)

—

PIR1

PIE1

IPR1

RCSTA

PSPIF

PSPIE

PSPIP

ADIF

ADIE

ADIP

RX9

RCIF

RCIE

RCIP

TXIF SSPIF

TXIE SSPIE

TXIP SSPIP

TMR2IF TMR1IF 0000 0000 0000 0000

TMR2IE TMR1IE 0000 0000 0000 0000

TMR2IP TMR1IP 0000 0000 0000 0000

SPEN

SREN CREN ADDEN FERR

OERR

RX9D 0000 -00x 0000 -00x

0000 0000 0000 0000

TXREG USART Transmit Register

TXSTA CSRC TX9 TXEN SYNC

SPBRG Baud Rate Generator Register

—

BRGH TRMT

TX9D 0000 -010 0000 -010

0000 0000 0000 0000

Legend: x= unknown, - = unimplemented locations read as '0'.

Shaded cells are not used for Asynchronous Transmission.

Note 1: The PSPIF, PSPIE and PSPIP bits are reserved on the PIC18F2X39 devices; always maintain these bits

clear.

 2002 Microchip Technology Inc.

Preliminary

DS30485A-page 173

PIC18FXX39

17.2.2

USART ASYNCHRONOUS

RECEIVER

17.2.3

SETTING UP 9-BIT MODE WITH

ADDRESS DETECT

The receiver block diagram is shown in Figure 17-4.

The data is received on the RC7/RX/DT pin and drives

the data recovery block. The data recovery block is

actually a high speed shifter operating at x16 times the

baud rate, whereas the main receive serial shifter oper-

ates at the bit rate or at FOSC. This mode would

typically be used in RS-232 systems.

This mode would typically be used in RS-485 systems.

To set up an Asynchronous Reception with Address

Detect Enable:

1. Initialize the SPBRG register for the appropriate

baud rate. If a high speed baud rate is required,

set the BRGH bit.

2. Enable the asynchronous serial port by clearing

To set up an Asynchronous Reception:

the SYNC bit and setting the SPEN bit.

1. Initialize the SPBRG register for the appropriate

baud rate. If a high speed baud rate is desired,

set bit BRGH (Section 17.1).

3. If interrupts are required, set the RCEN bit and

select the desired priority level with the RCIP bit.

4. Set the RX9 bit to enable 9-bit reception.

5. Set the ADDEN bit to enable address detect.

6. Enable reception by setting the CREN bit.

7. The RCIF bit will be set when reception is com-

plete. The interrupt will be acknowledged if the

RCIE and GIE bits are set.

2. Enable the asynchronous serial port by clearing

bit SYNC and setting bit SPEN.

3. If interrupts are desired, set enable bit RCIE.

4. If 9-bit reception is desired, set bit RX9.

5. Enable the reception by setting bit CREN.

6. Flag bit RCIF will be set when reception is com-

plete and an interrupt will be generated if enable

bit RCIE was set.

7. Read the RCSTA register to get the ninth bit (if

enabled) and determine if any error occurred

during reception.

8. Read the RCSTA register to determine if any

error occurred during reception, as well as read

bit 9 of data (if applicable).

9. Read RCREG to determine if the device is being

addressed.

10. If any error occurred, clear the CREN bit.

8. Read the 8-bit received data by reading the

11. If the device has been addressed, clear the

ADDEN bit to allow all received data into the

receive buffer and interrupt the CPU.

RCREG register.

9. If any error occurred, clear the error by clearing

enable bit CREN.

10. If using interrupts, ensure that the GIE and PEIE

bits in the INTCON register (INTCON<7:6>) are

set.

FIGURE 17-4:

USART RECEIVE BLOCK DIAGRAM

FERR

OERR

CREN

x64 Baud Rate CLK

÷ 64

or

RSR Register

MSb

LSb

SPBRG

÷ 16

0

7

1

STOP (8)

START

• • •

Baud Rate Generator

RX9

RC7/RX/DT

Pin Buffer

Data

and Control

Recovery

RX9D

RCREG Register

FIFO

SPEN

8

Interrupt

RCIF

RCIE

Data Bus

DS30485A-page 174

Preliminary

 2002 Microchip Technology Inc.

PIC18FXX39

FIGURE 17-5:

ASYNCHRONOUS RECEPTION

START

RX (pin)

bit

bit0

bit1

STOP

bit

STOP

bit

bit7/8 STOP bit

bit

bit0

bit7/8

Rcv Shift

Reg

Rcv Buffer Reg

Word 2

Word 1

RCREG

Read Rcv

Buffer Reg

RCREG

RCIF

(Interrupt Flag)

OERR bit

CREN

Note: This timing diagram shows three words appearing on the RX input. The RCREG (receive buffer) is read after the third word, causing

the OERR (overrun) bit to be set.

TABLE 17-7: REGISTERS ASSOCIATED WITH ASYNCHRONOUS RECEPTION

Value on

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

All Other

RESETS

POR, BOR

INTCON GIE/GIEH PEIE/ TMR0IE INT0IE RBIE TMR0IF INT0IF

GIEL

RBIF

0000 000x 0000 000u

(1)

—

PIR1

PIE1

IPR1

RCSTA

PSPIF

PSPIE

PSPIP

ADIF

ADIE

ADIP

RX9

RCIF

RCIE

RCIP

TXIF

TXIE SSPIE

TXIP SSPIP

SSPIF

TMR2IF TMR1IF 0000 0000 0000 0000

TMR2IE TMR1IE 0000 0000 0000 0000

TMR2IP TMR1IP 0000 0000 0000 0000

SPEN

SREN CREN ADDEN FERR OERR RX9D 0000 -00x 0000 -00x

RCREG USART Receive Register

0000 0000 0000 0000

TX9D 0000 -010 0000 -010

0000 0000 0000 0000

TXSTA

CSRC

TX9

TXEN SYNC

—

BRGH TRMT

SPBRG

Baud Rate Generator Register

Legend: x= unknown, - = unimplemented locations read as '0'.

Shaded cells are not used for Asynchronous Reception.

Note 1: The PSPIF, PSPIE and PSPIP bits are reserved on the PIC18F2X39 devices; always maintain these bits

clear.

 2002 Microchip Technology Inc.

Preliminary

DS30485A-page 175

PIC18FXX39

(PIE1<4>). Flag bit TXIF will be set, regardless of the

state of enable bit TXIE, and cannot be cleared in soft-

ware. It will reset only when new data is loaded into the

TXREG register. While flag bit TXIF indicates the status

of the TXREG register, another bit TRMT (TXSTA<1>)

shows the status of the TSR register. TRMT is a read

only bit, which is set when the TSR is empty. No inter-

rupt logic is tied to this bit, so the user has to poll this

bit in order to determine if the TSR register is empty.

The TSR is not mapped in data memory, so it is not

available to the user.

17.3 USART Synchronous Master

Mode

In Synchronous Master mode, the data is transmitted in

a half-duplex manner (i.e., transmission and reception

do not occur at the same time). When transmitting data,

the reception is inhibited and vice versa. Synchronous

mode is entered by setting bit SYNC (TXSTA<4>). In

addition, enable bit SPEN (RCSTA<7>) is set in order

to configure the RC6/TX/CK and RC7/RX/DT I/O pins

to CK (clock) and DT (data) lines, respectively. The

Master mode indicates that the processor transmits the

master clock on the CK line. The Master mode is

entered by setting bit CSRC (TXSTA<7>).

To set up a Synchronous Master Transmission:

1. Initialize the SPBRG register for the appropriate

baud rate (Section 17.1).

17.3.1

USART SYNCHRONOUS MASTER

TRANSMISSION

2. Enable the synchronous master serial port by

setting bits SYNC, SPEN, and CSRC.

3. If interrupts are desired, set enable bit TXIE.

4. If 9-bit transmission is desired, set bit TX9.

5. Enable the transmission by setting bit TXEN.

The USART transmitter block diagram is shown in

Figure 17-1. The heart of the transmitter is the Transmit

(serial) Shift Register (TSR). The shift register obtains

its data from the read/write transmit buffer register

TXREG. The TXREG register is loaded with data in

software. The TSR register is not loaded until the last

bit has been transmitted from the previous load. As

soon as the last bit is transmitted, the TSR is loaded

with new data from the TXREG (if available). Once the

TXREG register transfers the data to the TSR register

(occurs in one TCYCLE), the TXREG is empty and inter-

rupt bit TXIF (PIR1<4>) is set. The interrupt can be

enabled/disabled by setting/clearing enable bit TXIE

6. If 9-bit transmission is selected, the ninth bit

should be loaded in bit TX9D.

7. Start transmission by loading data to the TXREG

register.

Note: TXIF is not cleared immediately upon load-

ing data into the transmit buffer TXREG.

The flag bit becomes valid in the second

instruction cycle following the load

instruction.

TABLE 17-8: REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER TRANSMISSION

Value on

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

All Other

RESETS

POR, BOR

INTCON

GIE/

PEIE/ TMR0IE INT0IE RBIE TMR0IF INT0IF

GIEL

RBIF

0000 000x 0000 000u

GIEH

(1)

—

PIR1

PIE1

IPR1

RCSTA

PSPIF

PSPIE

PSPIP

ADIF

ADIE

ADIP

RX9

RCIF

RCIE

RCIP

TXIF

TXIE SSPIE

TXIP SSPIP

SSPIF

TMR2IF TMR1IF 0000 0000 0000 0000

TMR2IE TMR1IE 0000 0000 0000 0000

TMR2IP TMR1IP 0000 0000 0000 0000

(1)

SPEN

SREN CREN ADDEN FERR

OERR

RX9D

0000 -00x 0000 -00x

0000 0000 0000 0000

0000 -010 0000 -010

0000 0000 0000 0000

TXREG USART Transmit Register

TXSTA CSRC TX9 TXEN SYNC

SPBRG Baud Rate Generator Register

Legend: x= unknown, - = unimplemented, read as '0'.

—

BRGH

TRMT

TX9D

Shaded cells are not used for Synchronous Master Transmission.

Note 1: The PSPIF, PSPIE and PSPIP bits are reserved on the PIC18F2X39 devices; always maintain these bits

clear.

DS30485A-page 176

Preliminary

 2002 Microchip Technology Inc.

PIC18FXX39

FIGURE 17-6:

SYNCHRONOUS TRANSMISSION

Q1Q2 Q3Q4 Q1 Q2Q3 Q4Q1 Q2Q3 Q4Q1 Q2Q3 Q4Q1 Q2 Q3Q4

Q3Q4 Q1Q2 Q3Q4 Q1Q2 Q3Q4 Q1Q2 Q3 Q4Q1 Q2Q3 Q4Q1 Q2Q3 Q4Q1 Q2Q3 Q4

RC7/RX/DT

bit 0

bit 1

Word 1

bit 2

bit 7

bit 0

bit 1

Word 2

bit 7

RC6/TX/CK

Write to

TXREG Reg

Write Word1

Write Word2

TXIF bit

(Interrupt Flag)

TRMT

TRMT bit

'1'

TXEN bit

Note: Sync Master mode; SPBRG = '0'. Continuous transmission of two 8-bit words.

FIGURE 17-7:

SYNCHRONOUS TRANSMISSION (THROUGH TXEN)

RC7/RX/DT pin

bit0

bit2

bit1

bit6

bit7

RC6/TX/CK pin

Write to

TXREG reg

TXIF bit

TRMT bit

TXEN bit

 2002 Microchip Technology Inc.

Preliminary

DS30485A-page 177

PIC18FXX39

4. If interrupts are desired, set enable bit RCIE.

5. If 9-bit reception is desired, set bit RX9.

17.3.2

USART SYNCHRONOUS MASTER

RECEPTION

6. If a single reception is required, set bit SREN.

Once Synchronous mode is selected, reception is

enabled by setting either enable bit SREN

(RCSTA<5>), or enable bit CREN (RCSTA<4>). Data is

sampled on the RC7/RX/DT pin on the falling edge of

the clock. If enable bit SREN is set, only a single word

is received. If enable bit CREN is set, the reception is

continuous until CREN is cleared. If both bits are set,

then CREN takes precedence.

For continuous reception, set bit CREN.

7. Interrupt flag bit RCIF will be set when reception

is complete and an interrupt will be generated if

the enable bit RCIE was set.

8. Read the RCSTA register to get the ninth bit (if

enabled) and determine if any error occurred

during reception.

9. Read the 8-bit received data by reading the

To set up a Synchronous Master Reception:

RCREG register.

1. Initialize the SPBRG register for the appropriate

10. If any error occurred, clear the error by clearing

bit CREN.

11. If using interrupts, ensure that the GIE and PEIE

bits in the INTCON register (INTCON<7:6>) are

set.

baud rate (Section 17.1).

2. Enable the synchronous master serial port by

setting bits SYNC, SPEN and CSRC.

3. Ensure bits CREN and SREN are clear.

TABLE 17-9: REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER RECEPTION

Value on

All Other

RESETS

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

POR, BOR

INTCON

GIE/

PEIE/ TMR0IE INT0IE RBIE TMR0IF INT0IF

GIEL

RBIF

0000 000x 0000 000u

GIEH

(1)

—

PIR1

PIE1

IPR1

RCSTA

PSPIF

PSPIE

PSPIP

ADIF

ADIE

ADIP

RX9

RCIF

RCIE

RCIP

TXIF

TXIE

TXIP

SSPIF

SSPIE

SSPIP

TMR2IF TMR1IF 0000 0000 0000 0000

TMR2IE TMR1IE 0000 0000 0000 0000

TMR2IP TMR1IP 0000 0000 0000 0000

(1)

SPEN

SREN CREN ADDEN FERR

OERR

RX9D 0000 -00x 0000 -00x

0000 0000 0000 0000

RCREG USART Receive Register

TXSTA CSRC TX9 TXEN SYNC

SPBRG Baud Rate Generator Register

—

BRGH

TRMT

TX9D 0000 -010 0000 -010

0000 0000 0000 0000

Legend: x= unknown, - = unimplemented, read as '0'. Shaded cells are not used for Synchronous Master Reception.

Note 1: The PSPIF, PSPIE and PSPIP bits are reserved on the PIC18F2X39 devices; always maintain these bits clear.

FIGURE 17-8:

SYNCHRONOUS RECEPTION (MASTER MODE, SREN)

Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

RC7/RX/DT pin

RC6/TX/CK pin

bit0

bit1

bit2

bit3

bit4

bit5

bit6

bit7

Write to

bit SREN

SREN bit

CREN bit

'0'

RCIF bit

(Interrupt)

Read

RXREG

Note: Timing diagram demonstrates Sync Master mode with bit SREN = '1' and bit BRGH = '0'.

DS30485A-page 178

Preliminary

 2002 Microchip Technology Inc.

PIC18FXX39

To set up a Synchronous Slave Transmission:

17.4 USART Synchronous Slave Mode

1. Enable the synchronous slave serial port by set-

ting bits SYNC and SPEN and clearing bit

CSRC.

2. Clear bits CREN and SREN.

3. If interrupts are desired, set enable bit TXIE.

4. If 9-bit transmission is desired, set bit TX9.

Synchronous Slave mode differs from the Master mode

in the fact that the shift clock is supplied externally at

the RC6/TX/CK pin (instead of being supplied internally

in Master mode). This allows the device to transfer or

receive data while in SLEEP mode. Slave mode is

entered by clearing bit CSRC (TXSTA<7>).

5. Enable the transmission by setting enable bit

17.4.1

USART SYNCHRONOUS SLAVE

TRANSMIT

TXEN.

6. If 9-bit transmission is selected, the ninth bit

should be loaded in bit TX9D.

The operation of the Synchronous Master and Slave

modes are identical, except in the case of the SLEEP

mode.

7. Start transmission by loading data to the TXREG

register.

If two words are written to the TXREG and then the

8. If using interrupts, ensure that the GIE and PEIE

bits in the INTCON register (INTCON<7:6>) are

set.

SLEEPinstruction is executed, the following will occur:

a) The first word will immediately transfer to the

TSR register and transmit.

b) The second word will remain in TXREG register.

c) Flag bit TXIF will not be set.

d) When the first word has been shifted out of TSR,

the TXREG register will transfer the second

word to the TSR and flag bit TXIF will now be

set.

e) If enable bit TXIE is set, the interrupt will wake

the chip from SLEEP. If the global interrupt is

enabled, the program will branch to the interrupt

vector.

TABLE 17-10: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE TRANSMISSION

Value on

All Other

RESETS

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

POR, BOR

INTCON

GIE/

PEIE/ TMR0IE INT0IE RBIE TMR0IF INT0IF

GIEL

RBIF 0000 000x 0000 000u

GIEH

(1)

—

PIR1

PIE1

IPR1

RCSTA

PSPIF

PSPIE

PSPIP

ADIF

ADIE

ADIP

RX9

RCIF

RCIE

RCIP

TXIF SSPIF

TXIE SSPIE

TXIP SSPIP

TMR2IF TMR1IF 0000 0000 0000 0000

TMR2IE TMR1IE 0000 0000 0000 0000

TMR2IP TMR1IP 0000 0000 0000 0000

(1)

SPEN

SREN CREN ADDEN FERR

OERR

RX9D 0000 -00x 0000 -00x

0000 0000 0000 0000

TXREG USART Transmit Register

TXSTA CSRC TX9 TXEN SYNC

SPBRG Baud Rate Generator Register

Legend: x= unknown, - = unimplemented, read as '0'.

—

BRGH

TRMT

TX9D 0000 -010 0000 -010

0000 0000 0000 0000

Shaded cells are not used for Synchronous Slave Transmission.

Note 1: The PSPIF, PSPIE and PSPIP bits are reserved on the PIC18F2X39 devices; always maintain these bits

clear.

 2002 Microchip Technology Inc.

Preliminary

DS30485A-page 179

PIC18FXX39

To set up a Synchronous Slave Reception:

17.4.2

USART SYNCHRONOUS SLAVE

RECEPTION

1. Enable the synchronous master serial port by

setting bits SYNC and SPEN and clearing bit

CSRC.

2. If interrupts are desired, set enable bit RCIE.

3. If 9-bit reception is desired, set bit RX9.

4. To enable reception, set enable bit CREN.

5. Flag bit RCIF will be set when reception is com-

plete. An interrupt will be generated if enable bit

RCIE was set.

6. Read the RCSTA register to get the ninth bit (if

enabled) and determine if any error occurred

during reception.

The operation of the Synchronous Master and Slave

modes is identical, except in the case of the SLEEP

mode and bit SREN, which is a “don't care” in Slave

mode.

If receive is enabled by setting bit CREN prior to the

SLEEPinstruction, then a word may be received during

SLEEP. On completely receiving the word, the RSR

register will transfer the data to the RCREG register,

and if enable bit RCIE bit is set, the interrupt generated

will wake the chip from SLEEP. If the global interrupt is

enabled, the program will branch to the interrupt vector.

7. Read the 8-bit received data by reading the

RCREG register.

8. If any error occurred, clear the error by clearing

bit CREN.

9. If using interrupts, ensure that the GIE and PEIE

bits in the INTCON register (INTCON<7:6>) are

set.

TABLE 17-11: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE RECEPTION

Value on

All Other

RESETS

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

POR, BOR

INTCON

GIE/

PEIE/ TMR0IE INT0IE RBIE TMR0IF INT0IF

GIEL

RBIF 0000 000x 0000 000u

GIEH

(1)

—

PIR1

PIE1

IPR1

RCSTA

PSPIF

PSPIE

PSPIP

ADIF

ADIE

ADIP

RX9

RCIF

RCIE

RCIP

TXIF

TXIE

TXIP

SSPIF

SSPIE

SSPIP

TMR2IF TMR1IF 0000 0000 0000 0000

TMR2IE TMR1IE 0000 0000 0000 0000

TMR2IP TMR1IP 0000 0000 0000 0000

(1)

SPEN

SREN CREN ADDEN FERR

OERR

RX9D 0000 -00x 0000 -00x

0000 0000 0000 0000

RCREG USART Receive Register

TXSTA CSRC TX9 TXEN

SPBRG Baud Rate Generator Register

Legend: x= unknown, - = unimplemented, read as '0'.

SYNC

—

BRGH TRMT

TX9D 0000 -010 0000 -010

0000 0000 0000 0000

Shaded cells are not used for Synchronous Slave Reception.

Note 1: The PSPIF, PSPIE and PSPIP bits are reserved on the PIC18F2X39 devices; always maintain these bits

clear.

DS30485A-page 180

Preliminary

 2002 Microchip Technology Inc.

PIC18FXX39

The A/D module has four registers:

18.0 COMPATIBLE 10-BIT

ANALOG-TO-DIGITAL

• A/D Result High Register (ADRESH)

• A/D Result Low Register (ADRESL)

• A/D Control Register 0 (ADCON0)

• A/D Control Register 1 (ADCON1)

The ADCON0 register, shown in Register 18-1, con-

trols the operation of the A/D module. The ADCON1

register, shown in Register 18-2, configures the

functions of the port pins.

CONVERTER (A/D) MODULE

The Analog-to-Digital (A/D) converter module has five

inputs for the PIC18F2X39 devices and eight for the

PIC18F4X39 devices. This module has the ADCON0

and ADCON1 register definitions that are compatible

with the mid-range A/D module.

The A/D allows conversion of an analog input signal to

a corresponding 10-bit digital number.

REGISTER 18-1: ADCON0 REGISTER

R/W-0

ADCS1

bit 7

R/W-0

ADCS0

R/W-0

CHS2

R/W-0

CHS1

R/W-0

CHS0

R/W-0

GO/DONE

U-0

—

R/W-0

ADON

bit 0

bit 7-6

ADCS1:ADCS0: A/D Conversion Clock Select bits (ADCON0 bits in bold)

ADCON1

ADCON0

Clock Conversion

0

1

00

01

10

11

00

01

10

11

FOSC/2

FOSC/8

FOSC/32

FRC (clock derived from the internal A/D RC oscillator)

FOSC/4

FOSC/16

FOSC/64

FRC (clock derived from the internal A/D RC oscillator)

bit 5-3

CHS2:CHS0: Analog Channel Select bits

000= Channel 0 (AN0)

001= Channel 1 (AN1)

010= Channel 2 (AN2)

011= Channel 3 (AN3)

100= Channel 4 (AN4)

(1)

101= Channel 5 (AN5)

110= Channel 6 (AN6)

111= Channel 7 (AN7)

Note 1: These channels are unimplemented on PIC18F2X39 devices. Do not select any

unimplemented channel.

bit 2

GO/DONE: A/D Conversion Status bit

When ADON = 1:

1= A/D conversion in progress (setting this bit starts the A/D conversion, which is

automatically cleared by hardware when the A/D conversion is complete)

0= A/D conversion not in progress

bit 1

bit 0

Unimplemented: Read as '0'

ADON: A/D On bit

1= A/D converter module is powered up

0= A/D converter module is shut-off and consumes no operating current

Legend:

R = Readable bit

- n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

 2002 Microchip Technology Inc.

Preliminary

DS30485A-page 181

PIC18FXX39

REGISTER 18-2: ADCON1 REGISTER

R/W-0

ADFM

R/W-0

ADCS2

U-0

—

U-0

—

R/W-0

PCFG3

R/W-0

PCFG2

R/W-0

PCFG1

R/W-0

PCFG0

bit 7

bit 0

bit 7

bit 6

ADFM: A/D Result Format Select bit

1= Right justified. Six (6) Most Significant bits of ADRESH are read as ’0’.

0= Left justified. Six (6) Least Significant bits of ADRESL are read as ’0’.

ADCS2: A/D Conversion Clock Select bit (ADCON1 bits in bold)

ADCON1

ADCON0

Clock Conversion

0

1

00

01

10

11

00

01

10

11

FOSC/2

FOSC/8

FOSC/32

FRC (clock derived from the internal A/D RC oscillator)

FOSC/4

FOSC/16

FOSC/64

FRC (clock derived from the internal A/D RC oscillator)

bit 5-4

bit 3-0

Unimplemented: Read as '0'

PCFG3:PCFG0: A/D Port Configuration Control bits

PCFG

AN7

AN6

AN5

AN4

AN3

AN2

AN1

AN0

VREF+

VREF-

C / R

<3:0>

0000

0001

0010

0011

0100

0101

011x

1000

1001

1010

1011

1100

1101

1110

1111

A

D

A

D

A

D

A

D

A

D

A

D

A

D

A

D

A

D

VREF-

A

D

A

D

A

D

A

VDD

AN3

VDD

AN3

VDD

AN3

—

AN3

VDD

AN3

VDD

AN3

VSS

—

AN2

VSS

AN2

VSS

AN2

8 / 0

7 / 1

5 / 0

4 / 1

3 / 0

2 / 1

0 / 0

6 / 2

6 / 0

5 / 1

4 / 2

3 / 2

2 / 2

1 / 0

1 / 2

VREF+

A

VREF+

A

VREF+

D

VREF+

A

VREF+

D

VREF-

D

VREF+

VREF-

A = Analog input D = Digital I/O

C/R = # of analog input channels / # of A/D voltage references

Legend:

R = Readable bit

- n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

Note: On any device RESET, the port pins that are multiplexed with analog functions (ANx) are

forced to be an analog input.

DS30485A-page 182

Preliminary

 2002 Microchip Technology Inc.

PIC18FXX39

The analog reference voltage is software selectable to

either the device’s positive and negative supply voltage

(VDD and VSS), or the voltage level on the RA3/AN3/

VREF+ pin and RA2/AN2/VREF- pin.

The A/D converter has a unique feature of being able

to operate while the device is in SLEEP mode. To oper-

ate in SLEEP, the A/D conversion clock must be

derived from the A/D’s internal RC oscillator.

Each port pin associated with the A/D converter can be

configured as an analog input (RA3 can also be a

voltage reference) or as a digital I/O.

The ADRESH and ADRESL registers contain the result

of the A/D conversion. When the A/D conversion is

complete, the result is loaded into the ADRESH/

ADRESL registers, the GO/DONE bit (ADCON0<2>) is

cleared, and A/D interrupt flag bit, ADIF is set. The block

diagram of the A/D module is shown in Figure 18-1.

The output of the sample and hold is the input into the

converter, which generates the result via successive

approximation.

A device RESET forces all registers to their RESET

state. This forces the A/D module to be turned off and

any conversion is aborted.

FIGURE 18-1:

A/D BLOCK DIAGRAM

CHS<2:0>

111

AN7*

110

AN6*

101

AN5*

100

AN4

VAIN

(Input Voltage)

011

AN3

010

AN2

10-bit

Converter

A/D

001

AN1

PCFG<3:0>

000

AN0

VDD

VREF+

VREF-

Reference

Voltage

VSS

* These channels are implemented only on the PIC18F4X39 devices.

 2002 Microchip Technology Inc.

Preliminary

DS30485A-page 183

PIC18FXX39

The value that is in the ADRESH/ADRESL registers is

not modified for a Power-on Reset. The ADRESH/

ADRESL registers will contain unknown data after a

Power-on Reset.

5. Wait for A/D conversion to complete, by either:

• Polling for the GO/DONE bit to be cleared

(interrupts disabled)

OR

After the A/D module has been configured as desired,

the selected channel must be acquired before the con-

version is started. The analog input channels must

have their corresponding TRIS bits selected as an

input. To determine acquisition time, see Section 18.1.

After this acquisition time has elapsed, the A/D conver-

sion can be started. The following steps should be

followed for doing an A/D conversion:

• Waiting for the A/D interrupt

6. Read A/D Result registers (ADRESH/ADRESL);

clear bit ADIF if required.

7. For next conversion, go to step 1 or step 2 as

required. The A/D conversion time per bit is

defined as TAD. A minimum wait of 2 TAD is

required before the next acquisition starts.

1. Configure the A/D module:

18.1 A/D Acquisition Requirements

• Configure analog pins, voltage reference and

digital I/O (ADCON1)

For the A/D converter to meet its specified accuracy,

the charge holding capacitor (CHOLD) must be allowed

to fully charge to the input channel voltage level. The

analog input model is shown in Figure 18-2. The

source impedance (RS) and the internal sampling

switch (RSS) impedance directly affect the time

required to charge the capacitor CHOLD. The sampling

switch (RSS) impedance varies over the device voltage

(VDD). The source impedance affects the offset voltage

at the analog input (due to pin leakage current). The

maximum recommended impedance for analog

sources is 2.5 kΩ. After the analog input channel is

selected (changed), this acquisition must be done

before the conversion can be started.

• Select A/D input channel (ADCON0)

• Select A/D conversion clock (ADCON0)

• Turn on A/D module (ADCON0)

2. Configure A/D interrupt (if desired):

• Clear ADIF bit

• Set ADIE bit

• Set GIE bit

• Set PEIE bit

3. Wait the required acquisition time.

4. Start conversion:

• Set GO/DONE bit (ADCON0)

Note: When the conversion is started, the hold-

ing capacitor is disconnected from the

input pin.

FIGURE 18-2:

ANALOG INPUT MODEL

VDD

Sampling

Switch

VT = 0.6V

ANx

SS

RIC ≤ 1k

RSS

Rs

CPIN

5 pF

I LEAKAGE

VAIN

CHOLD = 120 pF

VT = 0.6V

± 500 nA

VSS

Legend: CPIN

VT

= input capacitance

= threshold voltage

6V

5V

I LEAKAGE = leakage current at the pin due to

VDD 4V

3V

various junctions

= interconnect resistance

= sampling switch

RIC

SS

2V

CHOLD

= sample/hold capacitance (from DAC)

5

6 7 8 9 10 11

Sampling Switch (kΩ)

DS30485A-page 184

Preliminary

 2002 Microchip Technology Inc.

PIC18FXX39

To calculate the minimum acquisition time,

Equation 18-1 may be used. This equation assumes

that 1/2 LSb error is used (1024 steps for the A/D). The

1/2 LSb error is the maximum error allowed for the A/D

to meet its specified resolution.

EQUATION 18-1: ACQUISITION TIME

TACQ

=

Amplifier Settling Time + Holding Capacitor Charging Time + Temperature Coefficient

TAMP + TC + TCOFF

EQUATION 18-2: A/D MINIMUM CHARGING TIME

VHOLD =

or

(VREF – (VREF/2048)) • (1 – e^{(-Tc/CHOLD(RIC + RSS + RS))}

)

TC

=

-(120 pF)(1 kΩ + RSS + RS) ln(1/2048)

Example 18-1 shows the calculation of the minimum

required acquisition time, TACQ. This calculation is

based on the following application system

assumptions:

• CHOLD

• Rs

• Conversion Error

• VDD

• Temperature

• VHOLD

=

≤

=

120 pF

2.5 kΩ

1/2 LSb

5V → Rss = 7 kΩ

50°C (system max.)

0V @ time = 0

EXAMPLE 18-1:

CALCULATING THE MINIMUM REQUIRED ACQUISITION TIME

TACQ

=

TAMP + TC + TCOFF

Temperature coefficient is only required for temperatures > 25°C.

TACQ

TC

=

2 µs + TC + [(Temp – 25°C)(0.05 µs/°C)]

-CHOLD (RIC + RSS + RS) ln(1/2048)

-120 pF (1 kΩ + 7 kΩ + 2.5 kΩ) ln(0.0004883)

-120 pF (10.5 kΩ) ln(0.0004883)

-1.26 µs (-7.6246)

9.61 µs

TACQ

=

2 µs + 9.61 µs + [(50°C – 25°C)(0.05 µs/°C)]

11.61 µs + 1.25 µs

12.86 µs

 2002 Microchip Technology Inc.

Preliminary

DS30485A-page 185

PIC18FXX39

18.2 Selecting the A/D Conversion Clock

18.3 Configuring Analog Port Pins

The A/D conversion time per bit is defined as TAD. The

A/D conversion requires 12 TAD per 10-bit conversion.

The source of the A/D conversion clock is software

selectable. The seven possible options for TAD are:

• 2 TOSC

• 4 TOSC

The ADCON1, TRISA and TRISE registers control the

operation of the A/D port pins. The port pins, that are

desired as analog inputs, must have their corresponding

TRIS bits set (input). If the TRIS bit is cleared (output),

the digital output level (VOH or VOL) will be converted.

The A/D operation is independent of the state of the

CHS2:CHS0 bits and the TRIS bits.

• 8 TOSC

• 16 TOSC

• 32 TOSC

• 64 TOSC

Note 1: When reading the port register, all pins

configured as analog input channels will

read as cleared (a low level). Pins config-

ured as digital inputs will convert an analog

input. Analog levels on a digitally config-

ured input will not affect the conversion

accuracy.

• Internal A/D module RC oscillator (2-6 µs)

For correct A/D conversions, the A/D conversion clock

(TAD) must be selected to ensure a minimum TAD time

of 1.6 µs.

Table 18-1 shows the resultant TAD times derived from

the device operating frequencies and the A/D clock

source selected.

2: Analog levels on any pin that is defined as

a digital input (including the AN4:AN0

pins) may cause the input buffer to con-

sume current that is out of the device’s

specification.

TABLE 18-1: TAD vs. DEVICE OPERATING FREQUENCIES

AD Clock Source (TAD)

Maximum Device Frequency

Operation

ADCS2:ADCS0

PIC18FXX39

PIC18LFXX39

2 TOSC

4 TOSC

8 TOSC

16 TOSC

32 TOSC

64 TOSC

RC

000

100

001

101

010

110

011

1.25 MHz

2.50 MHz

5.00 MHz

10.00 MHz

20.00 MHz

40.00 MHz

—

666 kHz

1.33 MHz

2.67 MHz

5.33 MHz

10.67 MHz

21.33 MHz

—

DS30485A-page 186

Preliminary

 2002 Microchip Technology Inc.

PIC18FXX39

(or the last value written to the ADRESH:ADRESL reg-

isters). After the A/D conversion is aborted, a 2 TAD wait

is required before the next acquisition is started. After

this 2 TAD wait, acquisition on the selected channel is

automatically started. The GO/DONE bit can then be

set to start the conversion.

18.4 A/D Conversions

Figure 18-3 shows the operation of the A/D converter

after the GO bit has been set. Clearing the GO/DONE

bit during a conversion will abort the current conver-

sion. The A/D result register pair will NOT be updated

with the partially completed A/D conversion sample.

That is, the ADRESH:ADRESL registers will continue

to contain the value of the last completed conversion

Note: The GO/DONE bit should NOT be set in

the same instruction that turns on the A/D.

FIGURE 18-3:

A/D CONVERSION TAD CYCLES

TCY - TAD

TAD1

TAD2 TAD3

TAD4

TAD5

TAD6

TAD7 TAD8

TAD9

b1

TAD10

b0

TAD11

b0

b4

b3

b2

b7

b6

b5

b8

b9

Conversion Starts

Holding capacitor is disconnected from analog input (typically 100 ns)

Set GO bit

Next Q4: ADRESH/ADRESL is loaded, GO bit is cleared,

ADIF bit is set, holding capacitor is connected to analog input.

Format Select bit (ADFM) controls this justification.

Figure 18-4 shows the operation of the A/D result justi-

fication. The extra bits are loaded with ‘0’s. When an

A/D result will not overwrite these locations (A/D

disable), these registers may be used as two general

purpose 8-bit registers.

18.4.1

A/D RESULT REGISTERS

The ADRESH:ADRESL register pair is the location

where the 10-bit A/D result is loaded at the completion

of the A/D conversion. This register pair is 16-bits wide.

The A/D module gives the flexibility to left or right justify

the 10-bit result in the 16-bit result register. The A/D

FIGURE 18-4:

A/D RESULT JUSTIFICATION

10-bit Result

ADFM = 0

0 7 6 5

ADFM = 1

0

7

2 1 0 7

0

0000 00

ADRESH

ADRESL

ADRESH

10-bit Result

Left Justified

ADRESL

10-bit Result

Right Justified

 2002 Microchip Technology Inc.

Preliminary

DS30485A-page 187

PIC18FXX39

TABLE 18-2: SUMMARY OF A/D REGISTERS

Value on

All Other

RESETS

Value on

POR, BOR

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

INTCON

GIE/

PEIE/

GIEL

TMR0IE

INT0IE

RBIE

TMR0IF

INT0IF

RBIF

0000 000x 0000 000u

GIEH

(1)

—

PIR1

PIE1

IPR1

PIR2

PIE2

IPR2

PSPIF

PSPIE

PSPIP

—

ADIF

ADIE

ADIP

—

RCIF

RCIE

RCIP

—

TXIF

TXIE

TXIP

EEIF

EEIE

EEIP

SSPIF

SSPIE

SSPIP

BCLIF

BCLIE

BCLIP

TMR2IF TMR1IF 0000 0000 0000 0000

TMR2IE TMR1IE 0000 0000 0000 0000

TMR2IP TMR1IP 0000 0000 0000 0000

TMR3IF

TMR3IE

TMR3IP

(1)

—

LVDIF

LVDIE

LVDIP

—

---0 0000 ---0 0000

---1 1111 ---1 0000

xxxx xxxx uuuu uuuu

—

ADRESH A/D Result Register

ADRESL A/D Result Register

ADCON0

ADCON1

PORTA

TRISA

PORTE

LATE

ADCS1

ADFM

—

ADCS0

ADCS2

RA6

CHS2

—

RA5

CHS1

—

RA4

CHS0 GO/DONE

—

PCFG1

RA1

ADON 0000 00-0 0000 00-0

PCFG0 ---- -000 ---- -000

PCFG3

RA3

PCFG2

RA2

RA0

--0x 0000 --0u 0000

--11 1111 --11 1111

---- -000 ---- -000

PORTA Data Direction Register

—

OBF

—

IBOV

—

RE2

LATE2

PORTE Data Direction bits

RE1

LATE1

RE0

—

IBF

LATE0 ---- -xxx ---- -uuu

TRISE

PSPMODE

0000 -111 0000 -111

Legend: x= unknown, u= unchanged, - = unimplemented, read as '0'. Shaded cells are not used for A/D conversion.

Note 1: The PSPIF, PSPIE and PSPIP bits are reserved on the PIC18F2X39 devices; always maintain these bits clear.

DS30485A-page 188

Preliminary

 2002 Microchip Technology Inc.

PIC18FXX39

The Low Voltage Detect circuitry is completely under

software control. This allows the circuitry to be “turned

off” by the software, which minimizes the current

consumption for the device.

Figure 19-1 shows a possible application voltage curve

(typically for batteries). Over time, the device voltage

decreases. When the device voltage equals voltage VA,

the LVD logic generates an interrupt. This occurs at

time TA. The application software then has the time,

until the device voltage is no longer in valid operating

range, to shutdown the system. Voltage point VB is the

minimum valid operating voltage specification. This

occurs at time TB. The difference TB – TA is the total

time for shutdown.

19.0 LOW VOLTAGE DETECT

In many applications, the ability to determine if the

device voltage (VDD) is below a specified voltage level

is a desirable feature. A window of operation for the

application can be created, where the application soft-

ware can do “housekeeping tasks” before the device

voltage exits the valid operating range. This can be

done using the Low Voltage Detect module.

This module is a software programmable circuitry,

where a device voltage trip point can be specified.

When the voltage of the device becomes lower then the

specified point, an interrupt flag is set. If the interrupt is

enabled, the program execution will branch to the inter-

rupt vector address and the software can then respond

to that interrupt source.

FIGURE 19-1:

TYPICAL LOW VOLTAGE DETECT APPLICATION

VA

VB

Legend:

VA = LVD trip point

VB = Minimum valid device

operating voltage

TB

TA

Time

The block diagram for the LVD module is shown in

Figure 19-2. A comparator uses an internally gener-

ated reference voltage as the set point. When the

selected tap output of the device voltage crosses the

set point (is lower than), the LVDIF bit is set.

Each node in the resistor divider represents a “trip

point” voltage. The “trip point” voltage is the minimum

supply voltage level at which the device can operate

before the LVD module asserts an interrupt. When the

supply voltage is equal to the trip point, the voltage

tapped off of the resistor array is equal to the 1.2V

internal reference voltage generated by the voltage

reference module. The comparator then generates an

interrupt signal setting the LVDIF bit. This voltage is

software programmable to any one of 16 values (see

Figure 19-2). The trip point is selected by

programming the LVDL3:LVDL0 bits (LVDCON<3:0>).

 2002 Microchip Technology Inc.

Preliminary

DS30485A-page 189

PIC18FXX39

FIGURE 19-2:

LOW VOLTAGE DETECT (LVD) BLOCK DIAGRAM

VDD

LVDIN

LVD Control

Register

–

+

LVDIF

Internally Generated

Reference Voltage

1.2V Typical

LVDEN

The LVD module has an additional feature that allows

the user to supply the trip voltage to the module from

an external source. This mode is enabled when bits

LVDL3:LVDL0 are set to ‘1111’. In this state, the com-

parator input is multiplexed from the external input pin,

LVDIN (Figure 19-3). This gives users flexibility,

because it allows them to configure the Low Voltage

Detect interrupt to occur at any voltage in the valid

operating range.

FIGURE 19-3:

LOW VOLTAGE DETECT (LVD) WITH EXTERNAL INPUT BLOCK DIAGRAM

VDD

LVD Control

Register

LVDIN

LVDEN

Externally Generated

Trip Point

–

+

LVD

VxEN

BODEN

EN

BGAP

DS30485A-page 190

Preliminary

 2002 Microchip Technology Inc.

PIC18FXX39

19.1 Control Register

The Low Voltage Detect Control register controls the

operation of the Low Voltage Detect circuitry.

REGISTER 19-1: LVDCON REGISTER

U-0

—

U-0

—

R-0

IRVST

R/W-0

LVDEN

R/W-0

LVDL3

R/W-1

LVDL2

R/W-0

LVDL1

R/W-1

LVDL0

bit 7

bit 0

bit 7-6

bit 5

Unimplemented: Read as '0'

IRVST: Internal Reference Voltage Stable Flag bit

1= Indicates that the Low Voltage Detect logic will generate the interrupt flag at the

specified voltage range

0= Indicates that the Low Voltage Detect logic will not generate the interrupt flag at the

specified voltage range and the LVD interrupt should not be enabled

bit 4

LVDEN: Low Voltage Detect Power Enable bit

1= Enables LVD, powers up LVD circuit

0= Disables LVD, powers down LVD circuit

bit 3-0

LVDL3:LVDL0: Low Voltage Detection Limit bits

1111= External analog input is used (input comes from the LVDIN pin)

1110= 4.5V - 4.77V

1101= 4.2V - 4.45V

1100= 4.0V - 4.24V

1011= 3.8V - 4.03V

1010= 3.6V - 3.82V

1001= 3.5V - 3.71V

1000= 3.3V - 3.50V

0111= 3.0V - 3.18V

0110= 2.8V - 2.97V

0101= 2.7V - 2.86V

0100= 2.5V - 2.65V

0011= 2.4V - 2.54V

0010= 2.2V - 2.33V

0001= 2.0V - 2.12V

0000= Reserved

Note:

LVDL3:LVDL0 modes, which result in a trip point below the valid operating voltage

of the device, are not tested.

Legend:

R = Readable bit

- n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

 2002 Microchip Technology Inc.

Preliminary

DS30485A-page 191

PIC18FXX39

The following steps are needed to set up the LVD

module:

1. Write the value to the LVDL3:LVDL0 bits

(LVDCON register), which selects the desired

LVD Trip Point.

19.2 Operation

Depending on the power source for the device voltage,

the voltage normally decreases relatively slowly. This

means that the LVD module does not need to be con-

stantly operating. To decrease the current require-

ments, the LVD circuitry only needs to be enabled for

short periods, where the voltage is checked. After

doing the check, the LVD module may be disabled.

Each time that the LVD module is enabled, the circuitry

requires some time to stabilize. After the circuitry has

stabilized, all status flags may be cleared. The module

will then indicate the proper state of the system.

2. Ensure that LVD interrupts are disabled (the

LVDIE bit is cleared or the GIE bit is cleared).

3. Enable the LVD module (set the LVDEN bit in

the LVDCON register).

4. Wait for the LVD module to stabilize (the IRVST

bit to become set).

5. Clear the LVD interrupt flag, which may have

falsely become set until the LVD module has

stabilized (clear the LVDIF bit).

6. Enable the LVD interrupt (set the LVDIE and the

GIE bits).

Figure 19-4 shows typical waveforms that the LVD

module may be used to detect.

FIGURE 19-4:

LOW VOLTAGE DETECT WAVEFORMS

CASE 1:

LVDIF may not be set

VDD

VLVD

LVDIF

Enable LVD

Internally Generated

Reference Stable

TIVRST

LVDIF cleared in software

CASE 2:

VDD

VLVD

LVDIF

Enable LVD

TIVRST

Internally Generated

Reference Stable

LVDIF cleared in software

LVDIF cleared in software,

LVDIF remains set since LVD condition still exists

DS30485A-page 192

Preliminary

 2002 Microchip Technology Inc.

PIC18FXX39

19.2.1

REFERENCE VOLTAGE SET POINT

19.3 Operation During SLEEP

The Internal Reference Voltage of the LVD module may

be used by other internal circuitry (the Programmable

Brown-out Reset). If these circuits are disabled (lower

current consumption), the reference voltage circuit

requires a time to become stable before a low voltage

condition can be reliably detected. This time is invariant

of system clock speed. This start-up time is specified in

electrical specification parameter 36. The low voltage

interrupt flag will not be enabled until a stable reference

voltage is reached. Refer to the waveform in Figure 19-4.

When enabled, the LVD circuitry continues to operate

during SLEEP. If the device voltage crosses the trip

point, the LVDIF bit will be set and the device will wake-

up from SLEEP. Device execution will continue from

the interrupt vector address if interrupts have been

globally enabled.

19.4 Effects of a RESET

A device RESET forces all registers to their RESET

state. This forces the LVD module to be turned off.

19.2.2

CURRENT CONSUMPTION

When the module is enabled, the LVD comparator and

voltage divider are enabled and will consume static cur-

rent. The voltage divider can be tapped from multiple

places in the resistor array. Total current consumption,

when enabled, is specified in electrical specification

parameter #D022B.

 2002 Microchip Technology Inc.

Preliminary

DS30485A-page 193

PIC18FXX39

NOTES:

DS30485A-page 194

Preliminary

 2002 Microchip Technology Inc.

PIC18FXX39

20.1 Configuration Bits

20.0 SPECIAL FEATURES OF THE

CPU

There are several features intended to maximize sys-

tem reliability, minimize cost through elimination of

external components, provide power saving Operating

modes and offer code protection. These are:

• OSC Selection

• RESET

- Power-on Reset (POR)

- Power-up Timer (PWRT)

- Oscillator Start-up Timer (OST)

- Brown-out Reset (BOR)

• Interrupts

The configuration bits can be programmed (read as '0'),

or left unprogrammed (read as '1'), to select various

device configurations. These bits are mapped starting

at program memory location 300000h.

The user will note that address 300000h is beyond the

user program memory space. In fact, it belongs to the

configuration memory space (300000h - 3FFFFFh),

which can only be accessed using Table Reads and

Table Writes.

Programming the configuration registers is done in a

manner similar to programming the FLASH memory

(see Section 5.5.1). The only difference is the configu-

ration registers are written a byte at a time. The

sequence of events for programming configuration

registers is:

• Watchdog Timer (WDT)

• SLEEP

• Code Protection

• ID Locations

1. Load table pointer with address of configuration

register being written.

2. Write a single byte using the TBLWTinstruction.

• In-Circuit Serial Programming

3. Set EEPGD to point to program memory, set the

CFGS bit to access configuration registers, and

set WREN to enable byte writes.

4. Disable interrupts.

5. Write 55h to EECON2.

6. Write AAh to EECON2.

7. Set the WR bit. This will begin the write cycle.

All PIC18FXX39 devices have a Watchdog Timer,

which is permanently enabled via the configuration bits,

or software controlled. It runs off its own RC oscillator

for added reliability. There are two timers that offer nec-

essary delays on power-up. One is the Oscillator

Start-up Timer (OST), intended to keep the chip in

RESET until the crystal oscillator is stable. The other is

the Power-up Timer (PWRT), which provides a fixed

delay on power-up only, designed to keep the part in

RESET while the power supply stabilizes. With these

two timers on-chip, most applications need no external

RESET circuitry.

8. CPU will stall for duration of write (approximately

2 ms using internal timer).

9. Execute a NOP.

10. Re-enable interrupts.

SLEEP mode is designed to offer a very low current

Power-down mode. The user can wake-up from

SLEEP through external RESET, Watchdog Timer

Wake-up or through an interrupt. Several oscillator

options are also made available to allow the part to fit

the application. The RC oscillator option saves system

cost, while the LP crystal option saves power. A set of

configuration bits are used to select various options.

 2002 Microchip Technology Inc.

Preliminary

DS30485A-page 195

PIC18FXX39

TABLE 20-1: CONFIGURATION BITS AND DEVICE IDS

Default/

Unprogrammed

Value

File Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

(1)

—

FOSC2

BORV0

FOSC1

FOSC0

300001h

CONFIG1H

CONFIG2L

CONFIG2H

CONFIG3H

CONFIG4L

CONFIG5L

CONFIG5H

CONFIG6L

CONFIG6H

CONFIG7L

CONFIG7H

—

--1- -010

300002h

300003h

300005h

300006h

300008h

300009h

30000Ah

30000Bh

30000Ch

30000Dh

—

BORV1

BOREN PWRTEN

---- 1111

---- ---1

1--- -1-1

---- 1111

11-- ----

---- 1111

111- ----

---- 1111

-1-- ----

(2)

WDTPS2 WDTPS1 WDTPS0

WDTEN

(1)

—

LVP

—

DEBUG

—

STVREN

CP0

(1)

—

CP2

—

CP1

—

CPD

—

CPB

—

(1)

—

WRT2

—

WRT1

—

WRT0

—

WRTD

—

WRTB

—

WRTC

—

(1)

—

EBTR2

—

EBTR1

—

EBTR0

—

EBTRB

DEV1

DEV9

—

3FFFFEh DEVID1

3FFFFFh DEVID2

DEV2

DEV10

DEV0

DEV8

REV4

DEV7

REV3

DEV6

REV2

DEV5

REV1

DEV4

REV0

DEV3

0000 0100

Legend: x= unknown, u= unchanged, - = unimplemented. Shaded cells are unimplemented, read as ‘0’.

Note 1: Unimplemented, but reserved; maintain this bit set.

2: See Register 20-11 for DEVID1 values.

REGISTER 20-1: CONFIG1H:CONFIGURATIONREGISTER1HIGH(BYTEADDRESS300001h)

U-0

—

bit 7

U-0

—

U-1

—

U-0

—

U-0

—

R/P-0

FOSC2

R/P-1

FOSC1

R/P-0

FOSC0

bit 0

bit 7-6

bit 5

bit 4-3

bit 2-0

Unimplemented: Read as ‘0’

Unimplemented and reserved: Maintain as ‘1’

Unimplemented: Read as ‘0’

FOSC2:FOSC0: Oscillator Selection bits

111= Reserved

110= HS oscillator with PLL enabled; clock frequency = (4 x FOSC)

101= EC oscillator w/ OSC2 configured as RA6

100= EC oscillator w/ OSC2 configured as divide-by-4 clock output

011= Reserved

010= HS oscillator

001= Reserved

000= Reserved

Legend:

R = Readable bit

P = Programmable bit U = Unimplemented bit, read as ‘0’

- n = Value when device is unprogrammed

u = Unchanged from programmed state

DS30485A-page 196

Preliminary

 2002 Microchip Technology Inc.

PIC18FXX39

REGISTER 20-2: CONFIG2L: CONFIGURATION REGISTER 2 LOW (BYTE ADDRESS 300002h)

U-0

—

bit 7

U-0

—

U-0

—

U-0

—

R/P-1

BORV1

R/P-1

BORV0

R/P-1

BOREN PWRTEN

bit 0

R/P-1

bit 7-4

bit 3-2

Unimplemented: Read as ‘0’

BORV1:BORV0: Brown-out Reset Voltage bits

11= VBOR set to 2.5V

10= VBOR set to 2.7V

01= VBOR set to 4.2V

00= VBOR set to 4.5V

bit 1

bit 0

BOREN: Brown-out Reset Enable bit

1= Brown-out Reset enabled

0= Brown-out Reset disabled

PWRTEN: Power-up Timer Enable bit

1= PWRT disabled

0= PWRT enabled

Legend:

R = Readable bit

P = Programmable bit

U = Unimplemented bit, read as ‘0’

- n = Value when device is unprogrammed

u = Unchanged from programmed state

REGISTER 20-3: CONFIG2H: CONFIGURATION REGISTER 2 HIGH (BYTE ADDRESS 300003h)

U-0

—

bit 7

U-0

—

U-0

—

U-0

—

R/P-1

WDTPS2 WDTPS1 WDTPS0 WDTEN

bit 0

bit 7-4

bit 3-1

Unimplemented: Read as ‘0’

WDTPS2:WDTPS0: Watchdog Timer Postscale Select bits

111= 1:128

110= 1:64

101= 1:32

100= 1:16

011= 1:8

010= 1:4

001= 1:2

000= 1:1

bit 0

WDTEN: Watchdog Timer Enable bit

1= WDT enabled

0= WDT disabled (control is placed on the SWDTEN bit)

Legend:

R = Readable bit

P = Programmable bit

U = Unimplemented bit, read as ‘0’

- n = Value when device is unprogrammed

u = Unchanged from programmed state

 2002 Microchip Technology Inc.

Preliminary

DS30485A-page 197

PIC18FXX39

REGISTER 20-4: CONFIG4L:CONFIGURATION REGISTER 4 LOW (BYTE ADDRESS300006h)

R/P-1

DEBUG

bit 7

U-0

—

U-0

—

U-0

—

U-0

—

R/P-1

LVP

U-0

—

R/P-1

STVREN

bit 0

bit 7

DEBUG: Background Debugger Enable bit

1= Background Debugger disabled. RB6 and RB7 configured as general purpose I/O pins.

0= Background Debugger enabled. RB6 and RB7 are dedicated to In-Circuit Debug.

bit 6-3

bit 2

Unimplemented: Read as ‘0’

LVP: Low Voltage ICSP Enable bit

1= Low Voltage ICSP enabled

0= Low Voltage ICSP disabled

bit 1

bit 0

Unimplemented: Read as ‘0’

STVREN: Stack Full/Underflow Reset Enable bit

1= Stack Full/Underflow will cause RESET

0= Stack Full/Underflow will not cause RESET

Legend:

R = Readable bit

C = Clearable bit

U = Unimplemented bit, read as ‘0’

- n = Value when device is unprogrammed

u = Unchanged from programmed state

DS30485A-page 198

Preliminary

 2002 Microchip Technology Inc.

PIC18FXX39

REGISTER 20-5: CONFIG5L: CONFIGURATION REGISTER 5 LOW (BYTE ADDRESS 300008h)

U-0

—

U-0

—

U-0

—

U-0

—

U-1

—

R/C-1

CP2

R/C-1

CP1

R/C-1

CP0

(1)

bit 7

bit 0

bit 7-4

bit 3

bit 2

Unimplemented: Read as ‘0’

Unimplemented and reserved: Maintain as ‘1’

(1)

CP2: Code Protection bit

1= Block 2 (004000-005FFFh) not code protected

0= Block 2 (004000-005FFFh) code protected

bit 1

bit 0

CP1: Code Protection bit

1= Block 1 (002000-003FFFh) not code protected

0= Block 1 (002000-003FFFh) code protected

CP0: Code Protection bit

1= Block 0 (000200-001FFFh) not code protected

0= Block 0 (000200-001FFFh) code protected

Note 1: Unimplemented in PIC18FX439 devices; maintain this bit set.

Legend:

R = Readable bit

- n = Value when device is unprogrammed

C = Clearable bit

U = Unimplemented bit, read as ‘0’

u = Unchanged from programmed state

REGISTER 20-6: CONFIG5H:CONFIGURATIONREGISTER5HIGH(BYTEADDRESS300009h)

R/C-1

CPD

R/C-1

CPB

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

bit 7

bit 0

bit 7

CPD: Data EEPROM Code Protection bit

1= Data EEPROM not code protected

0= Data EEPROM code protected

bit 6

CPB: Boot Block Code Protection bit

1= Boot block (000000-0001FFh) not code protected

0= Boot block (000000-0001FFh) code protected

bit 5-0

Unimplemented: Read as ‘0’

Legend:

R = Readable bit

- n = Value when device is unprogrammed

C = Clearable bit

U = Unimplemented bit, read as ‘0’

u = Unchanged from programmed state

 2002 Microchip Technology Inc.

Preliminary

DS30485A-page 199

PIC18FXX39

REGISTER 20-7: CONFIG6L:CONFIGURATIONREGISTER6LOW(BYTE ADDRESS30000Ah)

U-0

—

U-0

—

U-0

—

U-0

—

U-1

—

R/C-1

WRT2

R/C-1

WRT1

R/C-1

WRT0

(1)

bit 7

bit 0

bit 7-4

bit 3

bit 2

Unimplemented: Read as ‘0’

Unimplemented and reserved: Maintain as ‘1’

(1)

WRT2: Write Protection bit

1= Block 2 (004000-005FFFh) not write protected

0= Block 2 (004000-005FFFh) write protected

bit 1

bit 0

WRT1: Write Protection bit

1= Block 1 (002000-003FFFh) not write protected

0= Block 1 (002000-003FFFh) write protected

WRT0: Write Protection bit

1= Block 0 (000200h-001FFFh) not write protected

0= Block 0 (000200h-001FFFh) write protected

Note 1: Unimplemented in PIC18FX439 devices; maintain this bit set.

Legend:

R = Readable bit

- n = Value when device is unprogrammed

C = Clearable bit

U = Unimplemented bit, read as ‘0’

u = Unchanged from programmed state

REGISTER 20-8: CONFIG6H:CONFIGURATION REGISTER6 HIGH(BYTE ADDRESS30000Bh)

R/C-1

WRTD

R/C-1

WRTB

C-1

WRTC

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

bit 7

bit 0

bit 7

bit 6

bit 5

WRTD: Data EEPROM Write Protection bit

1= Data EEPROM not write protected

0= Data EEPROM write protected

WRTB: Boot Block Write Protection bit

1= Boot block (000000-0001FFh) not write protected

0= Boot block (000000-0001FFh) write protected

WRTC: Configuration Register Write Protection bit

1= Configuration registers (300000-3000FFh) not write protected

0= Configuration registers (300000-3000FFh) write protected

Note: This bit is read only, and cannot be changed in User mode.

Unimplemented: Read as ‘0’

bit 4-0

Legend:

R = Readable bit

C = Clearable bit

U = Unimplemented bit, read as ‘0’

- n = Value when device is unprogrammed

u = Unchanged from programmed state

DS30485A-page 200

Preliminary

 2002 Microchip Technology Inc.

PIC18FXX39

REGISTER 20-9: CONFIG7L:CONFIGURATIONREGISTER7LOW (BYTE ADDRESS30000Ch)

U-0

—

U-0

—

U-0

—

U-0

—

U-1

—

R/C-1

EBTR2

R/C-1

EBTR1

R/C-1

EBTR0

(1)

bit 7

bit 0

bit 7-4

bit 3

bit 2

Unimplemented: Read as ‘0’

Unimplemented and reserved: Maintain as ‘1’

EBTR2: Table Read Protection bit

(1)

1= Block 2 (004000-005FFFh) not protected from Table Reads executed in other blocks

0= Block 2 (004000-005FFFh) protected from Table Reads executed in other blocks

bit 1

bit 0

EBTR1: Table Read Protection bit

1= Block 1 (002000-003FFFh) not protected from Table Reads executed in other blocks

0= Block 1 (002000-003FFFh) protected from Table Reads executed in other blocks

EBTR0: Table Read Protection bit

1= Block 0 (000200h-001FFFh) not protected from Table Reads executed in other blocks

0= Block 0 (000200h-001FFFh) protected from Table Reads executed in other blocks

Note 1: Unimplemented in PIC18FX439 devices; maintain this bit set.

Legend:

R = Readable bit

C = Clearable bit

U = Unimplemented bit, read as ‘0’

- n = Value when device is unprogrammed

u = Unchanged from programmed state

REGISTER 20-10: CONFIG7H:CONFIGURATION REGISTER7 HIGH(BYTE ADDRESS30000Dh)

U-0

—

R/C-1

EBTRB

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

bit 7

bit 0

bit 7

bit 6

Unimplemented: Read as ‘0’

EBTRB: Boot Block Table Read Protection bit

1= Boot block (000000-0001FFh) not protected from Table Reads executed in other blocks

0= Boot block (000000-0001FFh) protected from Table Reads executed in other blocks

bit 5-0

Unimplemented: Read as ‘0’

Legend:

R = Readable bit

C = Clearable bit

U = Unimplemented bit, read as ‘0’

- n = Value when device is unprogrammed

u = Unchanged from programmed state

 2002 Microchip Technology Inc.

Preliminary

DS30485A-page 201

PIC18FXX39

REGISTER 20-11: DEVID1:DEVICEIDREGISTER1FORPIC18FXX39(BYTEADDRESS3FFFFEh)

R

DEV2

DEV1

DEV0

REV4

REV3

REV2

REV1

REV0

bit 7

bit 0

bit 7-5

bit 4-0

DEV2:DEV0: Device ID bits

000= PIC18F2539

001= PIC18F4539

100= PIC18F2439

101= PIC18F4439

REV4:REV0: Revision ID bits

These bits are used to indicate the device revision.

Legend:

R = Readable bit

- n = Value when device is unprogrammed

P = Programmable bit U = Unimplemented bit, read as ‘0’

u = Unchanged from programmed state

REGISTER 20-12: DEVID2:DEVICEIDREGISTER2FORPIC18FXX39(BYTEADDRESS3FFFFFh)

R

DEV10

DEV9

DEV8

DEV7

DEV6

DEV5

DEV4

DEV3

bit 7

bit 0

bit 7-0

DEV10:DEV3: Device ID bits

These bits are used with the DEV2:DEV0 bits in the Device ID Register 1 to identify the

part number.

Legend:

R = Readable bit

P = Programmable bit U = Unimplemented bit, read as ‘0’

- n = Value when device is unprogrammed

u = Unchanged from programmed state

DS30485A-page 202

Preliminary

 2002 Microchip Technology Inc.

PIC18FXX39

The WDT time-out period values may be found in the

Electrical Specifications (Section 23.0) under parame-

ter D031. Values for the WDT postscaler may be

assigned using the configuration bits.

20.2 Watchdog Timer (WDT)

The Watchdog Timer is a free running on-chip RC

oscillator, which does not require any external compo-

nents. This RC oscillator is separate from the RC

oscillator of the OSC1/CLKI pin. That means that the

WDT will run, even if the clock on the OSC1/CLKI and

OSC2/CLKO/RA6 pins of the device has been stopped,

for example, by execution of a SLEEPinstruction.

During normal operation, a WDT time-out generates a

device RESET (Watchdog Timer Reset). If the device is

in SLEEP mode, a WDT time-out causes the device to

wake-up and continue with normal operation (Watch-

dog Timer Wake-up). The TO bit in the RCON register

will be cleared upon a WDT time-out.

Note 1: The CLRWDT and SLEEP instructions

clear the WDT and the postscaler, if

assigned to the WDT and prevent it from

timing out and generating

RESET condition.

a device

2: When a CLRWDT instruction is executed

and the postscaler is assigned to the

WDT, the postscaler count will be cleared,

but the postscaler assignment is not

changed.

The Watchdog Timer is enabled/disabled by a device

configuration bit. If the WDT is enabled, software exe-

cution may not disable this function. When the WDTEN

configuration bit is cleared, the SWDTEN bit enables/

disables the operation of the WDT.

20.2.1

CONTROL REGISTER

Register 20-13 shows the WDTCON register. This is a

readable and writable register, which contains a control

bit that allows software to override the WDT enable

configuration bit, only when the configuration bit has

disabled the WDT.

REGISTER 20-13: WDTCON REGISTER

U-0

—

bit 7

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

R/W-0

SWDTEN

bit 0

bit 7-1

bit 0

Unimplemented: Read as ’0’

SWDTEN: Software Controlled Watchdog Timer Enable bit

1= Watchdog Timer is on

0= Watchdog Timer is turned off if the WDTEN configuration bit in the

configuration register = 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

- n = Value at POR

 2002 Microchip Technology Inc.

Preliminary

DS30485A-page 203

PIC18FXX39

20.2.2

WDT POSTSCALER

The WDT has a postscaler that can extend the WDT

Reset period. The postscaler is selected at the time of

the device programming, by the value written to the

CONFIG2H configuration register.

FIGURE 20-1:

WATCHDOG TIMER BLOCK DIAGRAM

WDT Timer

Postscaler

8

8 - to - 1 MUX

WDTPS2:WDTPS0

WDTEN

Configuration bit

SWDTEN bit

WDT

Time-out

Note:

WDPS2:WDPS0 are bits in register CONFIG2H.

TABLE 20-2: SUMMARY OF WATCHDOG TIMER REGISTERS

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

CONFIG2H

RCON

WDTCON

—

IPEN

—

RI

—

WDTPS2 WDTPS2 WDTPS0

WDTEN

BOR

SWDTEN

TO

—

PD

—

POR

—

Legend: Shaded cells are not used by the Watchdog Timer.

DS30485A-page 204

Preliminary

 2002 Microchip Technology Inc.

PIC18FXX39

External MCLR Reset will cause a device RESET. All

other events are considered a continuation of program

execution and will cause a “wake-up”. The TO and PD

bits in the RCON register can be used to determine the

cause of the device RESET. The PD bit, which is set on

power-up, is cleared when SLEEP is invoked. The TO

bit is cleared, if a WDT time-out occurred (and caused

wake-up).

When the SLEEPinstruction is being executed, the next

instruction (PC + 2) is pre-fetched. For the device to

wake-up through an interrupt event, the corresponding

interrupt enable bit must be set (enabled). Wake-up is

regardless of the state of the GIE bit. If the GIE bit is

clear (disabled), the device continues execution at the

instruction after the SLEEPinstruction. If the GIE bit is

set (enabled), the device executes the instruction after

the SLEEP instruction and then branches to the inter-

rupt address. In cases where the execution of the

instruction following SLEEP is not desirable, the user

should have a NOPafter the SLEEPinstruction.

20.3 Power-down Mode (SLEEP)

Power-down mode is entered by executing a SLEEP

instruction.

If enabled, the Watchdog Timer will be cleared, but

keeps running, the PD bit (RCON<3>) is cleared, the

TO (RCON<4>) bit is set, and the oscillator driver is

turned off. The I/O ports maintain the status they had

before the SLEEP instruction was executed (driving

high, low or hi-impedance).

For lowest current consumption in this mode, place all

I/O pins at either VDD or VSS, ensure no external cir-

cuitry is drawing current from the I/O pin, power-down

the A/D and disable external clocks. Pull all I/O pins

that are hi-impedance inputs, high or low externally, to

avoid switching currents caused by floating inputs. The

T0CKI input should also be at VDD or VSS for lowest

current consumption. The contribution from on-chip

pull-ups on PORTB should be considered.

The MCLR pin must be at a logic high level (VIHMC).

20.3.2

WAKE-UP USING INTERRUPTS

20.3.1

WAKE-UP FROM SLEEP

When global interrupts are disabled (GIE cleared) and

any interrupt source has both its interrupt enable bit

and interrupt flag bit set, one of the following will occur:

• If an interrupt condition (interrupt flag bit and inter-

rupt enable bits are set) occurs before the execu-

tion of a SLEEPinstruction, the SLEEPinstruction

will complete as a NOP. Therefore, the WDT and

WDT postscaler will not be cleared, the TO bit will

not be set and PD bits will not be cleared.

• If the interrupt condition occurs during or after

the execution of a SLEEPinstruction, the device

will immediately wake-up from SLEEP. The

SLEEPinstruction will be completely executed

before the wake-up. Therefore, the WDT and

WDT postscaler will be cleared, the TO bit will be

set and the PD bit will be cleared.

Even if the flag bits were checked before executing a

SLEEP instruction, it may be possible for flag bits to

become set before the SLEEPinstruction completes. To

determine whether a SLEEPinstruction executed, test

the PD bit. If the PD bit is set, the SLEEP instruction

was executed as a NOP.

The device can wake-up from SLEEP through one of

the following events:

1. External RESET input on MCLR pin.

2. Watchdog Timer Wake-up (if WDT was

enabled).

3. Interrupt from INT pin, RB port change or a

Peripheral Interrupt.

The following peripheral interrupts can wake the device

from SLEEP:

1. PSP read or write.

2. TMR1 interrupt. Timer1 must be operating as

an asynchronous counter.

3. TMR3 interrupt. Timer3 must be operating as

an asynchronous counter.

4. CCP Capture mode interrupt.

5. Special event trigger (Timer1 in Asynchronous

mode using an external clock).

6. MSSP (START/STOP) bit detect interrupt.

7. MSSP transmit or receive in Slave mode

2

(SPI/I C).

8. USART RX or TX (Synchronous Slave mode).

9. A/D conversion (when A/D clock source is RC).

10. EEPROM write operation complete.

11. LVD interrupt.

To ensure that the WDT is cleared, a CLRWDTinstruction

should be executed before a SLEEPinstruction.

Other peripherals cannot generate interrupts, since

during SLEEP, no on-chip clocks are present.

 2002 Microchip Technology Inc.

Preliminary

DS30485A-page 205

PIC18FXX39

FIGURE 20-2:

WAKE-UP FROM SLEEP THROUGH INTERRUPT^(1,2)

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

OSC1

CLKO⁽⁴⁾

INT pin

(2)

TOST

INTF Flag

Interrupt Latency⁽³⁾

(INTCON<1>)

GIEH bit

Processor in

SLEEP

(INTCON<7>)

INSTRUCTION FLOW

PC

PC+2

PC+4

PC + 4

0008h

000Ah

Instruction

Inst(0008h)

Inst(PC + 2)

Inst(PC + 4)

Inst(000Ah)

Inst(PC) = SLEEP

Fetched

Instruction

Executed

Inst(PC + 2)

Dummy Cycle

Inst(0008h)

SLEEP

Inst(PC - 1)

Note 1: XT, HS or LP Oscillator mode assumed.

2: GIE = 1 assumed. In this case, after wake-up, the processor jumps to the interrupt routine. If GIE = 0, execution will continue in-line.

3: TOST = 1024 TOSC (drawing not to scale). This delay will not occur for RC and EC Osc modes.

4: CLKO is not available in these Osc modes, but shown here for timing reference.

For PIC18FX439 devices, program memory is divided

20.4 Program Verification and

into three blocks: a boot block, Block 0 (7.5 Kbytes)

Code Protection

and Block 1 (8 Kbytes). Block 1 is further divided in

The overall structure of the code protection on the

PIC18 FLASH devices differs significantly from other

PICmicro devices. The user program memory is

divided on binary boundaries into individual blocks,

each of which has three separate code protection bits

associated with it:

• Code Protect bit (CPn)

• Write Protect bit (WRTn)

• External Block Table Read bit (EBTRn)

half; the upper portion above 3000h is reserved, and

unavailable to user applications. The entire block can

be protected as a whole by bits CP1, WRT1 and

EBTR1. By default, Block 1 is not code protected.

For PIC18FX539 devices, program memory is divided

into five blocks: the boot block, Block 0 (7.5 Kbytes),

and Blocks 1 through 3 (8 Kbytes). Code protection is

implemented for the boot block and Blocks 0 through 2.

There is no provision for code protection for Block 3.

Note: The reserved segments of the program

memory space are used by the Motor Con-

trol kernel. For the kernel to function prop-

erly, this area must not be write protected.

If users are developing applications that

require code protection for PIC18FX439

devices, they should restrict program code

(or at least those sections requiring protec-

tion) to below the 1FFFh memory

boundary.

The code protection bits are located in Configuration

Registers 5L through 7H. Their locations within the

registers are summarized in Table 20-3.

In the PIC18FXX39 family, program memory is divided

into segments of 8 Kbytes. The first block in turn

divided into a boot block of 512 bytes and a separately

protected remainder (Block 0) of 7.5 Kbytes. This

means for PIC18FXX39 devices, that there may be up

to five blocks, depending on the program memory size.

The organization of the blocks and their associated

code protection bits are shown in Figure 20-3.

DS30485A-page 206

Preliminary

 2002 Microchip Technology Inc.

PIC18FXX39

FIGURE 20-3:

CODE PROTECTED PROGRAM MEMORY FOR PIC18FXX39

MEMORY SIZE/DEVICE

Block Code Protection

Controlled By:

16 Kbytes

32 Kbytes

Address

Range

(PIC18FX439)

(PIC18FX539)

000000h

0001FFh

Boot Block

Block 0

CPB, WRTB, EBTRB

CP0, WRT0, EBTR0

000200h

Block 0

001FFFh

002000h

002FFFh

Block 1

Block 2

CP1, WRT1, EBTR1

CP2, WRT2, EBTR2

—

003000h

003FFFh

Reserved

004000h

Unimplemented

Read ‘0’s

005FFFh

006000h

Unimplemented

Read ‘0’s

Reserved

007FFFh

008000h

Unimplemented

Read ‘0’s

Unimplemented

Read ‘0’s

(Unimplemented Memory Space)

1FFFFFh

TABLE 20-3: SUMMARY OF CODE PROTECTION REGISTERS

File Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

(1)

300008h

CONFIG5L

CONFIG5H

CONFIG6L

CONFIG6H

CONFIG7L

CONFIG7H

—

CPD

—

WRTD

—

CPB

—

WRTB

—

WRTC

—

CP2

—

WRT2

—

EBTR2

—

CP1

—

WRT1

—

EBTR1

—

CP0

—

WRT0

—

EBTR0

—

300009h

30000Ah

30000Bh

30000Ch

30000Dh

—

(1)

—

(1)

—

EBTRB

—

Legend: Shaded cells are unimplemented.

Note 1: Unimplemented, but reserved; maintain this bit set.

 2002 Microchip Technology Inc.

Preliminary

DS30485A-page 207

PIC18FXX39

Read instruction that executes from a location outside

of that block is not allowed to read, and will result in

reading ‘0’s. Figures 20-4 through 20-6 illustrate Table

Write and Table Read protection.

20.4.1

PROGRAM MEMORY

CODE PROTECTION

The user memory may be read to, or written from, any

location using the Table Read and Table Write instruc-

tions. The device ID may be read with Table Reads.

The configuration registers may be read and written

with the Table Read and Table Write instructions.

In User mode, the CPn bits have no direct effect. CPn

bits inhibit external reads and writes. A block of user

memory may be protected from Table Writes if the

WRTn configuration bit is ‘0’. The EBTRn bits control

Table Reads. For a block of user memory with the

EBTRn bit set to ‘0’, a Table Read instruction that exe-

cutes from within that block is allowed to read. A Table

Note: Code protection bits may only be written to

a ‘0’ from a ‘1’ state. It is not possible to

write a ‘1’ to a bit in the ‘0’ state. Code pro-

tection bits are only set to ‘1’ by a block

erase function. The block erase function

can only be initiated via ICSP or an

external programmer.

FIGURE 20-4:

TABLE WRITE (WRTn) DISALLOWED

Program Memory

Register Values

Configuration Bit Settings

000000h

WRTB,EBTRB = 11

0001FFh

000200h

TBLPTR = 000FFF

PC = 001FFE

WRT0,EBTR0 = 01

TBLWT *

001FFFh

002000h

WRT1,EBTR1 = 11

WRT2,EBTR2 = 11

003FFFh

004000h

PC = 004FFE

005FFFh

Results: All Table Writes disabled to Blockn whenever WRTn = 0.

DS30485A-page 208

Preliminary

 2002 Microchip Technology Inc.

PIC18FXX39

FIGURE 20-5:

EXTERNAL BLOCK TABLE READ (EBTRn) DISALLOWED

Register Values

Program Memory

Configuration Bit Settings

000000h

WRTB,EBTRB = 11

0001FFh

000200h

TBLPTR = 000FFF

PC = 002FFE

WRT0,EBTR0 = 10

001FFFh

002000h

TBLRD *

WRT1,EBTR1 = 11

WRT2,EBTR2 = 11

003FFFh

004000h

005FFFh

Results: All Table Reads from external blocks to Blockn are disabled whenever EBTRn = 0.

TABLAT register returns a value of ‘0’.

FIGURE 20-6:

EXTERNAL BLOCK TABLE READ (EBTRn) ALLOWED

Register Values

Program Memory

Configuration Bit Settings

000000h

WRTB,EBTRB = 11

0001FFh

000200h

TBLPTR = 000FFF

PC = 001FFE

WRT0,EBTR0 = 10

TBLRD *

001FFFh

002000h

WRT1,EBTR1 = 11

WRT2,EBTR2 = 11

003FFFh

004000h

005FFFh

Results: Table Reads permitted within Blockn, even when EBTRBn = 0.

TABLAT register returns the value of the data at the location TBLPTR.

 2002 Microchip Technology Inc.

Preliminary

DS30485A-page 209

PIC18FXX39

To use the In-Circuit Debugger function of the micro-

controller, the design must implement In-Circuit Serial

Programming connections to MCLR/VPP, VDD, GND,

RB7 and RB6. This will interface to the In-Circuit

Debugger module available from Microchip, or one of

the third party development tool companies.

20.4.2

DATA EEPROM

CODE PROTECTION

The entire Data EEPROM is protected from external

reads and writes by two bits: CPD and WRTD. CPD

inhibits external reads and writes of Data EEPROM.

WRTD inhibits external writes to Data EEPROM. The

CPU can continue to read and write Data EEPROM,

regardless of the protection bit settings.

20.8 Low Voltage ICSP Programming

The LVP bit configuration register CONFIG4L enables

low voltage ICSP programming. This mode allows the

microcontroller to be programmed via ICSP using a

VDD source in the operating voltage range. This only

means that VPP does not have to be brought to VIHH,

but can instead be left at the normal operating voltage.

In this mode, the RB5/PGM pin is dedicated to the pro-

gramming function and ceases to be a general purpose

I/O pin. During programming, VDD is applied to the

MCLR/VPP pin. To enter Programming mode, VDD must

be applied to the RB5/PGM, provided the LVP bit is set.

The LVP bit defaults to a ‘1’ from the factory.

20.4.3

CONFIGURATION REGISTER

PROTECTION

The configuration registers can be write protected. The

WRTC bit controls protection of the configuration regis-

ters. In User mode, the WRTC bit is readable only. WRTC

can only be written via ICSP or an external programmer.

20.5 ID Locations

Eight memory locations (200000h - 200007h) are des-

ignated as ID locations, where the user can store

checksum or other code identification numbers. These

locations are accessible during normal execution

through the TBLRD and TBLWT instructions, or during

program/verify. The ID locations can be read when the

device is code protected.

The sequence for programming the ID locations is sim-

ilar to programming the FLASH memory (see

Section 5.5.1).

Note 1: The High Voltage Programming mode is

always available, regardless of the state

of the LVP bit, by applying VIHH to the

MCLR pin.

2: While in low voltage ICSP mode, the RB5

pin can no longer be used as a general

purpose I/O pin, and should be held low

during normal operation to protect

against inadvertent ICSP mode entry.

3: When using low voltage ICSP program-

ming (LVP), the pull-up on RB5 becomes

disabled. If TRISB bit 5 is cleared,

thereby setting RB5 as an output, LATB

bit 5 must also be cleared for proper

operation.

20.6

In-Circuit Serial Programming

PIC18FXXX microcontrollers can be serially pro-

grammed while in the end application circuit. This is

simply done with two lines for clock and data, and three

other lines for power, ground and the programming

voltage. This allows customers to manufacture boards

with unprogrammed devices, and then program the

microcontroller just before shipping the product. This

also allows the most recent firmware, or a custom

firmware to be programmed.

If Low Voltage Programming mode is not used, the LVP

bit can be programmed to a '0' and RB5/PGM becomes

a digital I/O pin. However, the LVP bit may only be pro-

grammed when programming is entered with VIHH on

MCLR/VPP.

It should be noted that once the LVP bit is programmed

to ‘0’, only the High Voltage Programming mode is

available and only High Voltage Programming mode

can be used to program the device.

When using low voltage ICSP, the part must be sup-

plied 4.5V to 5.5V, if a bulk erase will be executed. This

includes reprogramming of the code protect bits from

an on-state to an off-state. For all other cases of low

voltage ICSP, the part may be programmed at the nor-

mal operating voltage. This means unique user IDs, or

user code can be reprogrammed or added.

20.7 In-Circuit Debugger

When the DEBUG bit in configuration register

CONFIG4L is programmed to a '0', the In-Circuit

Debugger functionality is enabled. This function allows

simple debugging functions when used with MPLAB^®

IDE. When the microcontroller has this feature

enabled, some of the resources are not available for

general use. Table 20-4 shows which features are

consumed by the background debugger.

TABLE 20-4: DEBUGGER RESOURCES

I/O pins

RB6, RB7

Stack

Program Memory

Data Memory

2 levels

512 bytes

10 bytes

DS30485A-page 210

Preliminary

 2002 Microchip Technology Inc.

PIC18FXX39

The literal instructions may use some of the following

21.0 INSTRUCTION SET SUMMARY

operands:

The PIC18FXXX instruction set adds many enhance-

ments to the previous PICmicro instruction sets, while

maintaining an easy migration from these PICmicro

instruction sets.

Most instructions are a single program memory word

(16-bits), but there are three instructions that require

two program memory locations.

Each single word instruction is a 16-bit word divided

into an OPCODE, which specifies the instruction type

and one or more operands, which further specify the

operation of the instruction.

The instruction set is highly orthogonal and is grouped

into four basic categories:

• A literal value to be loaded into a file register

(specified by ‘k’)

• The desired FSR register to load the literal value

into (specified by ‘f’)

• No operand required

(specified by ‘—’)

The control instructions may use some of the following

operands:

• A program memory address (specified by ‘n’)

• The mode of the Call or Return instructions

(specified by ‘s’)

• The mode of the Table Read and Table Write

instructions (specified by ‘m’)

• No operand required

(specified by ‘—’)

All instructions are a single word, except for three dou-

ble-word instructions. These three instructions were

made double-word instructions, so that all the required

information is available in these 32 bits. In the second

word, the 4 MSbs are ‘1’s. If this second word is exe-

cuted as an instruction (by itself), it will execute as a

NOP.

• Byte-oriented operations

• Bit-oriented operations

• Literal operations

• Control operations

The PIC18FXXX instruction set summary in Table 21-2

lists byte-oriented, bit-oriented, literal and control

operations. Table 21-1 shows the opcode field

descriptions.

Most byte-oriented instructions have three operands:

All single word instructions are executed in a single

instruction cycle, unless a conditional test is true or the

program counter is changed as a result of the instruc-

tion. In these cases, the execution takes two instruction

cycles with the additional instruction cycle(s) executed

as a NOP.

1. The file register (specified by ‘f’)

2. The destination of the result

(specified by ‘d’)

3. The accessed memory

(specified by ‘a’)

The file register designator 'f' specifies which file

register is to be used by the instruction.

The destination designator ‘d’ specifies where the

result of the operation is to be placed. If 'd' is zero, the

result is placed in the WREG register. If 'd' is one, the

result is placed in the file register specified in the

instruction.

The double-word instructions execute in two instruction

cycles.

One instruction cycle consists of four oscillator periods.

Thus, for an oscillator frequency of 4 MHz, the normal

instruction execution time is 1 µs. If a conditional test is

true, or the program counter is changed as a result of

an instruction, the instruction execution time is 2 µs.

Two-word branch instructions (if true) would take 3 µs.

All bit-oriented instructions have three operands:

1. The file register (specified by ‘f’)

Figure 21-1 shows the general formats that the

instructions can have.

All examples use the format ‘nnh’ to represent a hexa-

decimal number, where ‘h’ signifies a hexadecimal

digit.

2. The bit in the file register

(specified by ‘b’)

3. The accessed memory

(specified by ‘a’)

The bit field designator 'b' selects the number of the bit

affected by the operation, while the file register desig-

nator 'f' represents the number of the file in which the

bit is located.

The Instruction Set Summary, shown in Table 21-2,

lists the instructions recognized by the Microchip

Assembler (MPASM^TM).

Section 21.1 provides a description of each instruction.

 2002 Microchip Technology Inc.

Preliminary

DS30485A-page 211

PIC18FXX39

TABLE 21-1: OPCODE FIELD DESCRIPTIONS

Field

Description

a

RAM access bit

a = 0: RAM location in Access RAM (BSR register is ignored)

a = 1: RAM bank is specified by BSR register

bbb

BSR

d

Bit address within an 8-bit file register (0 to 7).

Bank Select Register. Used to select the current RAM bank.

Destination select bit

d = 0: store result in WREG,

d = 1: store result in file register f.

dest

f

Destination, either the WREG register or the specified register file location.

8-bit Register file address (0x00 to 0xFF).

fs

12-bit Register file address (0x000 to 0xFFF). This is the source address.

12-bit Register file address (0x000 to 0xFFF). This is the destination address.

Literal field, constant data or label (may be either an 8-bit, 12-bit or a 20-bit value).

Label name.

The mode of the TBLPTR register for the Table Read and Table Write instructions.

Only used with Table Read and Table Write instructions:

fd

k

label

mm

*

No Change to register (such as TBLPTR with Table Reads and Writes).

Post-Increment register (such as TBLPTR with Table Reads and Writes).

Post-Decrement register (such as TBLPTR with Table Reads and Writes).

Pre-Increment register (such as TBLPTR with Table Reads and Writes).

*+

*-

+*

n

The relative address (2’s complement number) for relative branch instructions, or the direct address for

Call/Branch and Return instructions.

PRODH

PRODL

s

Product of Multiply high byte.

Product of Multiply low byte.

Fast Call/Return mode select bit

s = 0: do not update into/from shadow registers

s = 1: certain registers loaded into/from shadow registers (Fast mode)

u

Unused or Unchanged.

WREG

x

Working register (accumulator).

Don't care (0 or 1).

The assembler will generate code with x = 0. It is the recommended form of use for compatibility with all

Microchip software tools.

TBLPTR

TABLAT

TOS

21-bit Table Pointer (points to a Program Memory location).

8-bit Table Latch.

Top-of-Stack.

PC

Program Counter.

PCL

Program Counter Low Byte.

Program Counter High Byte.

Program Counter High Byte Latch.

Program Counter Upper Byte Latch.

Global Interrupt Enable bit.

Watchdog Timer.

PCH

PCLATH

PCLATU

GIE

WDT

TO

Time-out bit.

PD

Power-down bit.

C, DC, Z, OV, N ALU status bits Carry, Digit Carry, Zero, Overflow, Negative.

[

]

Optional.

(

)

Contents.

→

< >

∈

Assigned to.

Register bit field.

In the set of.

italics

User defined term (font is courier).

DS30485A-page 212

Preliminary

 2002 Microchip Technology Inc.

PIC18FXX39

FIGURE 21-1:

GENERAL FORMAT FOR INSTRUCTIONS

Byte-oriented file register operations

Example Instruction

15

10

OPCODE

9

8

a

7

0

d

f (FILE #)

ADDWF MYREG, W, B

d = 0 for result destination to be WREG register

d = 1 for result destination to be file register (f)

a = 0 to force Access Bank

a = 1 for BSR to select bank

f = 8-bit file register address

Byte to Byte move operations (2-word)

15

OPCODE

12 11

0

f (Source FILE #)

MOVFF MYREG1, MYREG2

15

12 11

1111

f (Destination FILE #)

f = 12-bit file register address

Bit-oriented file register operations

15 12 11 9 8

OPCODE b (BIT #)

7

0

BSF MYREG, bit, B

a

f (FILE #)

b = 3-bit position of bit in file register (f)

a = 0 to force Access Bank

a = 1 for BSR to select bank

f = 8-bit file register address

Literal operations

15

8

7

0

MOVLW 0x7F

OPCODE

k (literal)

k = 8-bit immediate value

Control operations

CALL, GOTO and Branch operations

15

8 7

0

GOTO Label

OPCODE

12 11

n<7:0> (literal)

15

0

1111

n<19:8> (literal)

n = 20-bit immediate value

15

8

7

0

CALL MYFUNC

OPCODE

12 11

n<7:0> (literal)

S

0

n<19:8> (literal)

S = Fast bit

11 10

15

0

BRA MYFUNC

BC MYFUNC

OPCODE

n<10:0> (literal)

15

OPCODE

8 7

n<7:0> (literal)

 2002 Microchip Technology Inc.

Preliminary

DS30485A-page 213

PIC18FXX39

TABLE 21-2: PIC18FXXX INSTRUCTION SET

16-Bit Instruction Word

MSb LSb

Mnemonic,

Status

Description

Cycles

Notes

Operands

Affected

BYTE-ORIENTED FILE REGISTER OPERATIONS

ADDWF

ADDWFC

ANDWF

CLRF

f, d, a Add WREG and f

1

0010 01da0 ffff

0010 0da

ffff C, DC, Z, OV, N 1, 2

f, d, a Add WREG and Carry bit to f

f, d, a AND WREG with f

ffff

0001 01da

0110 101a

0001 11da

ffff Z, N

ffff

1,2

2

f, a

Clear f

Z

COMF

f, d, a Complement f

ffff Z, N

ffff None

1, 2

4

CPFSEQ

CPFSGT

CPFSLT

DECF

DECFSZ

DCFSNZ

INCF

f, a

Compare f with WREG, skip =

Compare f with WREG, skip >

Compare f with WREG, skip <

1 (2 or 3) 0110 001a

1 (2 or 3) 0110 010a

1 (2 or 3) 0110 000a

4

1, 2

f, d, a Decrement f

1

0000 01da

ffff C, DC, Z, OV, N 1, 2, 3, 4

f, d, a Decrement f, Skip if 0

f, d, a Decrement f, Skip if Not 0

f, d, a Increment f

f, d, a Increment f, Skip if 0

f, d, a Increment f, Skip if Not 0

f, d, a Inclusive OR WREG with f

f, d, a Move f

1 (2 or 3) 0010 11da

1 (2 or 3) 0100 11da

ffff None

1, 2, 3, 4

1, 2

1

0010 10da

ffff C, DC, Z, OV, N 1, 2, 3, 4

INCFSZ

INFSNZ

IORWF

MOVF

1 (2 or 3) 0011 11da

1 (2 or 3) 0100 10da

ffff None

ffff Z, N

ffff None

ffff

4

1, 2

1

2

0001 00da

0101 00da

1100 ffff

1111 ffff

0110 111a

0000 001a

0110 110a

0011 01da

0100 01da

0011 00da

0100 00da

0110 100a

0101 01da

MOVFF

f , f

Move f (source) to 1st word

s

d

f (destination) 2nd word

d

MOVWF

MULWF

NEGF

f, a

Move WREG to f

1

ffff None

ffff C, DC, Z, OV, N 1, 2

ffff C, Z, N

Multiply WREG with f

Negate f

RLCF

f, d, a Rotate Left f through Carry

f, d, a Rotate Left f (No Carry)

f, d, a Rotate Right f through Carry

f, d, a Rotate Right f (No Carry)

RLNCF

RRCF

ffff Z, N

ffff C, Z, N

ffff Z, N

ffff None

1, 2

RRNCF

SETF

f, a

Set f

SUBFWB

f, d, a Subtract f from WREG with

borrow

ffff C, DC, Z, OV, N 1, 2

SUBWF

SUBWFB

f, d, a Subtract WREG from f

f, d, a Subtract WREG from f with

borrow

1

0101 11da

0101 10da

ffff

ffff C, DC, Z, OV, N

ffff C, DC, Z, OV, N 1, 2

SWAPF

TSTFSZ

XORWF

f, d, a Swap nibbles in f

1

0011 10da

ffff

ffff None

ffff Z, N

4

1, 2

f, a

Test f, skip if 0

1 (2 or 3) 0110 011a

f, d, a Exclusive OR WREG with f

1

0001 10da

BIT-ORIENTED FILE REGISTER OPERATIONS

BCF

f, b, a Bit Clear f

1

1001 bbba

1000 bbba

ffff

ffff None

1, 2

3, 4

1, 2

BSF

f, b, a Bit Set f

BTFSC

BTFSS

BTG

f, b, a Bit Test f, Skip if Clear

f, b, a Bit Test f, Skip if Set

f, d, a Bit Toggle f

1 (2 or 3) 1011 bbba

1 (2 or 3) 1010 bbba

1

0111 bbba

Note 1: When a PORT register is modified as a function of itself (e.g., MOVF PORTB, 1, 0), the value used will be that value

present on the pins themselves. For example, if the data latch is '1' for a pin configured as input and is driven low by an

external device, the data will be written back with a '0'.

2: If this instruction is executed on the TMR0 register (and, where applicable, d = 1), the prescaler will be cleared if assigned.

3: If Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The second cycle is

executed as a NOP.

4: Some instructions are 2-word instructions. The second word of these instructions will be executed as a NOP, unless the

first word of the instruction retrieves the information embedded in these 16-bits. This ensures that all program memory

locations have a valid instruction.

5: If the Table Write starts the write cycle to internal memory, the write will continue until terminated.

DS30485A-page 214

Preliminary

 2002 Microchip Technology Inc.

PIC18FXX39

TABLE 21-2: PIC18FXXX INSTRUCTION SET (CONTINUED)

16-Bit Instruction Word

Mnemonic,

Status

Description

Cycles

Notes

Operands

Affected

MSb

LSb

CONTROL OPERATIONS

BC

n

Branch if Carry

1 (2)

1110 0010

1110 0110

1110 0011

1110 0111

1110 0101

1110 0001

1110 0100

1101 0nnn

1110 0000

1110 110s

1111 kkkk

0000 0000

1110 1111

1111 kkkk

0000 0000

1111 xxxx

0000 0000

1101 1nnn

0000 0000

nnnn

kkkk

0000

kkkk

0000

xxxx

0000

nnnn

1111

0001

nnnn None

kkkk None

kkkk

BN

n

Branch if Negative

Branch if Not Carry

Branch if Not Negative

Branch if Not Overflow

Branch if Not Zero

Branch if Overflow

Branch Unconditionally

Branch if Zero

1 (2)

2

BNC

BNN

BNOV

BNZ

BOV

BRA

BZ

n

1 (2)

2

n

CALL

n, s

Call subroutine 1st word

2nd word

CLRWDT

DAW

GOTO

—

n

Clear Watchdog Timer

Decimal Adjust WREG

Go to address 1st word

2nd word

1

2

0100 TO, PD

0111

kkkk None

kkkk

C

NOP

—

n

No Operation

1

2

1

2

0000 None

xxxx None

0110 None

0101 None

nnnn None

1111 All

000s GIE/GIEH,

PEIE/GIEL

kkkk None

001s None

0011 TO, PD

NOP

4

POP

Pop top of return stack (TOS)

Push top of return stack (TOS)

Relative Call

PUSH

RCALL

RESET

RETFIE

Software device RESET

Return from interrupt enable

s

RETLW

RETURN

SLEEP

k

Return with literal in WREG

Return from Subroutine

Go into Standby mode

2

1

0000 1100

0000 0000

kkkk

0001

0000

s

—

Note 1: When a PORT register is modified as a function of itself (e.g., MOVF PORTB, 1, 0), the value used will be that value

present on the pins themselves. For example, if the data latch is '1' for a pin configured as input and is driven low by an

external device, the data will be written back with a '0'.

2: If this instruction is executed on the TMR0 register (and, where applicable, d = 1), the prescaler will be cleared if assigned.

3: If Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The second cycle is

executed as a NOP.

4: Some instructions are 2-word instructions. The second word of these instructions will be executed as a NOP, unless the

first word of the instruction retrieves the information embedded in these 16-bits. This ensures that all program memory

locations have a valid instruction.

5: If the Table Write starts the write cycle to internal memory, the write will continue until terminated.

 2002 Microchip Technology Inc.

Preliminary

DS30485A-page 215

PIC18FXX39

TABLE 21-2: PIC18FXXX INSTRUCTION SET (CONTINUED)

16-Bit Instruction Word

Mnemonic,

Operands

Status

Description

Cycles

Notes

Affected

MSb

LSb

LITERAL OPERATIONS

ADDLW

ANDLW

IORLW

LFSR

k

Add literal and WREG

1

2

0000 1111 kkkk

0000 1011 kkkk

0000 1001 kkkk

1110 1110 00ff

1111 0000 kkkk

0000 0001 0000

0000 1110 kkkk

0000 1101 kkkk

0000 1100 kkkk

0000 1000 kkkk

0000 1010 kkkk

kkkk C, DC, Z, OV, N

kkkk Z, N

k

AND literal with WREG

k

f, k

Inclusive OR literal with WREG

Move literal (12-bit) 2nd word

to FSRx 1st word

Move literal to BSR<3:0>

Move literal to WREG

Multiply literal with WREG

Return with literal in WREG

Subtract WREG from literal

Exclusive OR literal with WREG

kkkk Z, N

kkkk None

kkkk

MOVLB

MOVLW

MULLW

RETLW

SUBLW

XORLW

k

1

2

1

kkkk None

kkkk C, DC, Z, OV, N

kkkk Z, N

DATA MEMORY ↔ PROGRAM MEMORY OPERATIONS

TBLRD*

Table Read

2

0000 0000 0000

1000 None

1001 None

1010 None

1011 None

1100 None

1101 None

1110 None

1111 None

TBLRD*+

TBLRD*-

TBLRD+*

TBLWT*

TBLWT*+

TBLWT*-

TBLWT+*

Table Read with post-increment

Table Read with post-decrement

Table Read with pre-increment

Table Write

2 (5)

Table Write with post-increment

Table Write with post-decrement

Table Write with pre-increment

Note 1: When a PORT register is modified as a function of itself (e.g., MOVF PORTB, 1, 0), the value used will be that value

present on the pins themselves. For example, if the data latch is '1' for a pin configured as input and is driven low by an

external device, the data will be written back with a '0'.

2: If this instruction is executed on the TMR0 register (and, where applicable, d = 1), the prescaler will be cleared if assigned.

3: If Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The second cycle is

executed as a NOP.

4: Some instructions are 2-word instructions. The second word of these instructions will be executed as a NOP, unless the

first word of the instruction retrieves the information embedded in these 16-bits. This ensures that all program memory

locations have a valid instruction.

5: If the Table Write starts the write cycle to internal memory, the write will continue until terminated.

DS30485A-page 216

Preliminary

 2002 Microchip Technology Inc.

PIC18FXX39

21.1 Instruction Set

ADDLW

ADD literal to W

ADDWF

ADD W to f

Syntax:

[ label ] ADDLW

0 ≤ k ≤ 255

(W) + k → W

N, OV, C, DC, Z

k

Syntax:

Operands:

[ label ] ADDWF

f [,d [,a]

Operands:

Operation:

Status Affected:

Encoding:

0 ≤ f ≤ 255

d ∈ [0,1]

a ∈ [0,1]

(W) + (f) → dest

N, OV, C, DC, Z

Operation:

Status Affected:

Encoding:

0000

1111

kkkk

Description:

The contents of W are added to the

8-bit literal 'k' and the result is

placed in W.

1

0010

01da

ffff

Description:

Add W to register 'f'. If 'd' is 0, the

result is stored in W. If 'd' is 1, the

result is stored back in register 'f'

(default). If ‘a’ is 0, the Access

Bank will be selected. If ‘a’ is 1, the

BSR is used.

1

Words:

Cycles:

Q Cycle Activity:

Q1

Q2

Q3

Q4

Write to W

Decode

Read

Process

Words:

Cycles:

literal 'k'

Data

Q Cycle Activity:

Q1

ADDLW

0x15

Example:

Q2

Q3

Process

Data

Q4

Before Instruction

Decode

Read

Write to

W

=

0x10

register 'f'

destination

After Instruction

W

=

0x25

ADDWF

REG, 0, 0

Example:

Before Instruction

W

=

0x17

0xC2

REG

=

After Instruction

W

=

0xD9

0xC2

REG

=

 2002 Microchip Technology Inc.

Preliminary

DS30485A-page 217

PIC18FXX39

ADDWFC

ADD W and Carry bit to f

ANDLW

AND literal with W

Syntax:

Operands:

[ label ] ADDWFC

f [,d [,a]

Syntax:

[ label ] ANDLW

0 ≤ k ≤ 255

(W) .AND. k → W

N,Z

k

0 ≤ f ≤ 255

d ∈ [0,1]

a ∈ [0,1]

(W) + (f) + (C) → dest

N,OV, C, DC, Z

Operands:

Operation:

Status Affected:

Encoding:

Operation:

Status Affected:

Encoding:

0000

1011

kkkk

Description:

The contents of W are ANDed with

the 8-bit literal 'k'. The result is

placed in W.

1

0010

00da

ffff

Description:

Add W, the Carry Flag and data

memory location 'f'. If 'd' is 0, the

result is placed in W. If 'd' is 1, the

result is placed in data memory loca-

tion 'f'. If ‘a’ is 0, the Access Bank

will be selected. If ‘a’ is 1, the BSR

will not be overridden.

Words:

Cycles:

Q Cycle Activity:

Q1

Q2

Read literal

'k'

Q3

Process

Data

Q4

Write to W

Decode

Words:

Cycles:

1

ANDLW

0x5F

Example:

Q Cycle Activity:

Q1

Before Instruction

Q2

Q3

Process

Data

Q4

W

=

0xA3

0x03

Decode

Read

Write to

register 'f'

destination

After Instruction

W

=

ADDWFC

REG, 0, 1

Example:

Before Instruction

Carry bit =

1

REG

W

=

0x02

0x4D

After Instruction

Carry bit =

0

REG

W

=

0x02

0x50

DS30485A-page 218

Preliminary

 2002 Microchip Technology Inc.

PIC18FXX39

ANDWF

AND W with f

BC

Branch if Carry

Syntax:

[ label ] ANDWF

f [,d [,a]

Syntax:

[ label ] BC

n

Operands:

0 ≤ f ≤ 255

d ∈ [0,1]

a ∈ [0,1]

(W) .AND. (f) → dest

N,Z

Operands:

Operation:

-128 ≤ n ≤ 127

if carry bit is ‘1’

(PC) + 2 + 2n → PC

Operation:

Status Affected:

Encoding:

Status Affected:

Encoding:

Description:

None

1110

0010

nnnn

0001

01da

ffff

If the Carry bit is ‘1’, then the

program will branch.

Description:

The contents of W are AND’ed with

register 'f'. If 'd' is 0, the result is

stored in W. If 'd' is 1, the result is

stored back in register 'f' (default). If

‘a’ is 0, the Access Bank will be

selected. If ‘a’ is 1, the BSR will not

be overridden (default).

The 2’s complement number ‘2n’ is

added to the PC. Since the PC will

have incremented to fetch the next

instruction, the new address will be

PC+2+2n. This instruction is then

a two-cycle instruction.

Words:

Cycles:

1

Words:

Cycles:

1

1(2)

Q Cycle Activity:

Q1

Q Cycle Activity:

If Jump:

Q2

Q3

Process

Data

Q4

Q1

Decode

Q2

Q3

Q4

Write to PC

Decode

Read

Write to

register 'f'

destination

Read literal

Process

'n'

Data

No

ANDWF

REG, 0, 0

Example:

operation

Before Instruction

If No Jump:

Q1

W

=

0x17

0xC2

Q2

Q3

Q4

REG

=

Decode

Read literal

Process

No

After Instruction

'n'

Data

operation

W

=

0x02

0xC2

REG

=

HERE

BC

5

Example:

Before Instruction

PC

=

address (HERE)

After Instruction

If Carry

PC

=

1;

address (HERE+12)

0;

If Carry

PC

address (HERE+2)

 2002 Microchip Technology Inc.

Preliminary

DS30485A-page 219

PIC18FXX39

BCF

Bit Clear f

BN

Branch if Negative

[ label ] BN

Syntax:

[ label ] BCF f,b[,a]

Syntax:

n

Operands:

0 ≤ f ≤ 255

0 ≤ b ≤ 7

a ∈ [0,1]

0 → f

None

Operands:

Operation:

-128 ≤ n ≤ 127

if negative bit is ‘1’

(PC) + 2 + 2n → PC

Operation:

Status Affected:

Encoding:

Status Affected:

Encoding:

Description:

None

1110

0110

nnnn

1001

bbba

ffff

If the Negative bit is ‘1’, then the

program will branch.

Description:

Bit 'b' in register 'f' is cleared. If ‘a’

is 0, the Access Bank will be

selected, overriding the BSR value.

If ‘a’ = 1, then the bank will be

selected as per the BSR value

(default).

1

The 2’s complement number ‘2n’ is

added to the PC. Since the PC will

have incremented to fetch the next

instruction, the new address will be

PC+2+2n. This instruction is then

a two-cycle instruction.

Words:

Cycles:

Words:

Cycles:

1

1(2)

Q Cycle Activity:

Q1

Q Cycle Activity:

Q2

Q3

Q4

Write

If Jump:

Decode

Read

Process

Q1

Q2

Q3

Q4

register 'f'

Data

register 'f'

Decode

Read literal

Process

Data

Write to PC

'n'

BCF

FLAG_REG, 7, 0

Example:

No

operation

No

operation

No

operation

Before Instruction

operation

FLAG_REG = 0xC7

If No Jump:

Q1

After Instruction

Q2

Q3

Q4

FLAG_REG = 0x47

Decode

Read literal

Process

Data

No

'n'

operation

HERE

BN Jump

Example:

Before Instruction

PC

=

address (HERE)

After Instruction

If Negative

PC

=

1;

address (Jump)

If Negative

PC

0;

address (HERE+2)

DS30485A-page 220

Preliminary

 2002 Microchip Technology Inc.

PIC18FXX39

BNC

Branch if Not Carry

BNN

Branch if Not Negative

Syntax:

Operands:

Operation:

[ label ] BNC

-128 ≤ n ≤ 127

if carry bit is ‘0’

n

Syntax:

Operands:

Operation:

[ label ] BNN

-128 ≤ n ≤ 127

if negative bit is ‘0’

(PC) + 2 + 2n → PC

n

(PC) + 2 + 2n → PC

Status Affected:

Encoding:

None

1110

Status Affected:

Encoding:

None

1110

0011

nnnn

0111

nnnn

Description:

If the Carry bit is ‘0’, then the

program will branch.

Description:

If the Negative bit is ‘0’, then the

program will branch.

The 2’s complement number ‘2n’ is

added to the PC. Since the PC will

have incremented to fetch the next

instruction, the new address will be

PC+2+2n. This instruction is then

a two-cycle instruction.

The 2’s complement number ‘2n’ is

added to the PC. Since the PC will

have incremented to fetch the next

instruction, the new address will be

PC+2+2n. This instruction is then

a two-cycle instruction.

Words:

Cycles:

1

1(2)

Words:

Cycles:

1

1(2)

Q Cycle Activity:

If Jump:

Q Cycle Activity:

If Jump:

Q1

Decode

Q2

Q3

Q4

Write to PC

Q1

Decode

Q2

Q3

Q4

Write to PC

Read literal

Process

Read literal

Process

'n'

Data

'n'

Data

No

operation

No

operation

No

operation

No

operation

No

operation

No

operation

No

operation

No

operation

If No Jump:

Q1

If No Jump:

Q1

Q2

Q3

Q4

Q2

Q3

Q4

Decode

Read literal

Process

No

Decode

Read literal

Process

No

'n'

Data

operation

'n'

Data

operation

HERE

BNC Jump

HERE

BNN Jump

Example:

Before Instruction

PC

=

address (HERE)

PC

=

address (HERE)

After Instruction

If Carry

PC

=

0;

If Negative

PC

=

0;

address (Jump)

If Carry

PC

1;

If Negative

PC

1;

address (HERE+2)

 2002 Microchip Technology Inc.

Preliminary

DS30485A-page 221

PIC18FXX39

BNOV

Branch if Not Overflow

BNZ

Branch if Not Zero

Syntax:

Operands:

Operation:

[ label ] BNOV

-128 ≤ n ≤ 127

if overflow bit is ‘0’

(PC) + 2 + 2n → PC

n

Syntax:

Operands:

Operation:

[ label ] BNZ

-128 ≤ n ≤ 127

if zero bit is ‘0’

n

(PC) + 2 + 2n → PC

Status Affected:

Encoding:

None

1110

Status Affected:

Encoding:

None

1110

0101

nnnn

0001

nnnn

Description:

If the Overflow bit is ‘0’, then the

program will branch.

Description:

If the Zero bit is ‘0’, then the

program will branch.

The 2’s complement number ‘2n’ is

added to the PC. Since the PC will

have incremented to fetch the next

instruction, the new address will be

PC+2+2n. This instruction is then

a two-cycle instruction.

The 2’s complement number ‘2n’ is

added to the PC. Since the PC will

have incremented to fetch the next

instruction, the new address will be

PC+2+2n. This instruction is then

a two-cycle instruction.

Words:

Cycles:

1

1(2)

Words:

Cycles:

1

1(2)

Q Cycle Activity:

If Jump:

Q Cycle Activity:

If Jump:

Q1

Decode

Q2

Q3

Q4

Write to PC

Q1

Decode

Q2

Q3

Q4

Write to PC

Read literal

Process

Read literal

Process

'n'

Data

'n'

Data

No

operation

No

operation

No

operation

No

operation

No

operation

No

operation

No

operation

No

operation

If No Jump:

Q1

If No Jump:

Q1

Q2

Q3

Q4

Q2

Q3

Q4

Decode

Read literal

Process

No

Decode

Read literal

Process

No

'n'

Data

operation

'n'

Data

operation

HERE

BNOV Jump

HERE

BNZ Jump

Example:

Before Instruction

PC

=

address (HERE)

PC

=

address (HERE)

After Instruction

If Overflow

PC

=

0;

If Zero

PC

=

0;

address (Jump)

If Overflow

PC

1;

If Zero

PC

1;

address (HERE+2)

DS30485A-page 222

Preliminary

 2002 Microchip Technology Inc.

PIC18FXX39

BRA

Unconditional Branch

[ label ] BRA

BSF

Bit Set f

Syntax:

n

Syntax:

[ label ] BSF f,b[,a]

Operands:

Operation:

Status Affected:

Encoding:

-1024 ≤ n ≤ 1023

(PC) + 2 + 2n → PC

None

Operands:

0 ≤ f ≤ 255

0 ≤ b ≤ 7

a ∈ [0,1]

1 → f

None

Operation:

Status Affected:

Encoding:

1101

0nnn

nnnn

Description:

Add the 2’s complement number

‘2n’ to the PC. Since the PC will

have incremented to fetch the next

instruction, the new address will be

PC+2+2n. This instruction is a

two-cycle instruction.

1

2

1000

bbba

ffff

Description:

Bit 'b' in register 'f' is set. If ‘a’ is 0

Access Bank will be selected, over-

riding the BSR value. If ‘a’ = 1, then

the bank will be selected as per the

BSR value.

1

Words:

Cycles:

Words:

Cycles:

Q Cycle Activity:

Q1

Q Cycle Activity:

Q1

Q2

Q3

Q4

Write to PC

Q2

Q3

Q4

Write

Decode

Read literal

Process

'n'

Data

Decode

Read

Process

register 'f'

Data

register 'f'

No

operation

No

operation

No

operation

No

operation

BSF

FLAG_REG, 7, 1

Example:

Before Instruction

HERE

BRA Jump

Example:

FLAG_REG

=

0x0A

0x8A

Before Instruction

After Instruction

PC

=

address (HERE)

address (Jump)

FLAG_REG

After Instruction

PC

 2002 Microchip Technology Inc.

Preliminary

DS30485A-page 223

PIC18FXX39

BTFSC

Bit Test File, Skip if Clear

BTFSS

Bit Test File, Skip if Set

Syntax:

[ label ] BTFSC f,b[,a]

Syntax:

[ label ] BTFSS f,b[,a]

Operands:

0 ≤ f ≤ 255

0 ≤ b ≤ 7

a ∈ [0,1]

Operands:

0 ≤ f ≤ 255

0 ≤ b ≤ 7

a ∈ [0,1]

Operation:

Status Affected:

Encoding:

skip if (f) = 0

None

Operation:

Status Affected:

Encoding:

skip if (f) = 1

None

1011

bbba

ffff

1010

bbba

ffff

Description:

If bit 'b' in register ’f' is 0, then the

next instruction is skipped.

Description:

If bit 'b' in register 'f' is 1, then the

next instruction is skipped.

If bit 'b' is 0, then the next instruction

fetched during the current instruction

execution is discarded, and a NOPis

executed instead, making this a two-

cycle instruction. If ‘a’ is 0, the

Access Bank will be selected, over-

riding the BSR value. If ‘a’ = 1, then

the bank will be selected as per the

BSR value (default).

If bit 'b' is 1, then the next instruction

fetched during the current instruc-

tion execution, is discarded and a

NOPis executed instead, making this

a two-cycle instruction. If ‘a’ is 0, the

Access Bank will be selected, over-

riding the BSR value. If ‘a’ = 1, then

the bank will be selected as per the

BSR value (default).

Words:

Cycles:

1

1(2)

Words:

Cycles:

1

1(2)

Note: 3 cycles if skip and followed

by a 2-word instruction.

Note: 3 cycles if skip and followed

by a 2-word instruction.

Q Cycle Activity:

Q1

Q Cycle Activity:

Q1

Q2

Q3

Process Data

Q4

Q2

Q3

Process Data

Q4

Decode

Read

No

Decode

Read

No

register 'f'

operation

register 'f'

operation

If skip:

Q1

If skip:

Q1

Q2

Q3

Q4

Q2

Q3

Q4

No

operation

If skip and followed by 2-word instruction:

Q1

Q2

Q3

Q4

Q1

Q2

Q3

Q4

No

operation

No

operation

No

operation

No

operation

No

operation

No

operation

No

operation

No

operation

No

operation

No

operation

HERE

FALSE

TRUE

BTFSC

:

FLAG, 1, 0

Example:

HERE

FALSE

TRUE

BTFSS

:

FLAG, 1, 0

Example:

Before Instruction

PC

Before Instruction

PC

=

address (HERE)

=

address (HERE)

After Instruction

If FLAG<1>

PC

=

0;

If FLAG<1>

PC

=

0;

address (TRUE)

1;

address (FALSE)

1;

If FLAG<1>

PC

If FLAG<1>

PC

address (FALSE)

address (TRUE)

DS30485A-page 224

Preliminary

 2002 Microchip Technology Inc.

PIC18FXX39

BTG

Bit Toggle f

BOV

Branch if Overflow

Syntax:

Operands:

[ label ] BTG f,b[,a]

Syntax:

Operands:

Operation:

[ label ] BOV

-128 ≤ n ≤ 127

if overflow bit is ‘1’

(PC) + 2 + 2n → PC

n

0 ≤ f ≤ 255

0 ≤ b ≤ 7

a ∈ [0,1]

(f) → f

None

Operation:

Status Affected:

Encoding:

Status Affected:

Encoding:

Description:

None

1110

0100

nnnn

0111

bbba

ffff

If the Overflow bit is ‘1’, then the

program will branch.

Description:

Bit 'b' in data memory location 'f' is

inverted. If ‘a’ is 0, the Access Bank

will be selected, overriding the BSR

value. If ‘a’ = 1, then the bank will be

selected as per the BSR value

(default).

1

The 2’s complement number ‘2n’ is

added to the PC. Since the PC will

have incremented to fetch the next

instruction, the new address will be

PC+2+2n. This instruction is then

a two-cycle instruction.

Words:

Cycles:

Words:

Cycles:

Q Cycle Activity:

If Jump:

1

1(2)

Q Cycle Activity:

Q1

Q2

Q3

Q4

Write

Decode

Read

Process

Q1

Q2

Q3

Q4

register 'f'

Data

register 'f'

Decode

Read literal

Process

Data

Write to PC

'n'

BTG

PORTC, 4, 0

Example:

No

operation

No

operation

Before Instruction:

operation

PORTC

=

0111 0101 [0x75]

If No Jump:

Q1

After Instruction:

Q2

Q3

Q4

PORTC

=

0110 0101 [0x65]

Decode

Read literal

Process

Data

No

'n'

operation

HERE

BOV Jump

Example:

Before Instruction

PC

=

address (HERE)

After Instruction

If Overflow

PC

=

1;

address (Jump)

If Overflow

PC

0;

address (HERE+2)

 2002 Microchip Technology Inc.

Preliminary

DS30485A-page 225

PIC18FXX39

BZ

Branch if Zero

[ label ] BZ

CALL

Subroutine Call

Syntax:

n

Syntax:

[ label ] CALL k [,s]

Operands:

Operation:

-128 ≤ n ≤ 127

if Zero bit is ‘1’

(PC) + 2 + 2n → PC

Operands:

0 ≤ k ≤ 1048575

s ∈ [0,1]

Operation:

(PC) + 4 → TOS,

k → PC<20:1>,

if s = 1

Status Affected:

Encoding:

Description:

None

1110

0000

nnnn

(W) → WS,

(STATUS) → STATUSS,

(BSR) → BSRS

If the Zero bit is ‘1’, then the pro-

gram will branch.

The 2’s complement number ‘2n’ is

added to the PC. Since the PC will

have incremented to fetch the next

instruction, the new address will be

PC+2+2n. This instruction is then

a two-cycle instruction.

1

1(2)

Status Affected:

None

Encoding:

1st word (k<7:0>)

2nd word(k<19:8>)

1110

1111

110s

k kkk

kkkk

7

0

8

k

kkk kkkk

19

Description:

Subroutine call of entire 2 Mbyte

memory range. First, return

address (PC+ 4) is pushed onto the

return stack. If ‘s’ = 1, the W,

Words:

Cycles:

STATUS and BSR registers are

also pushed into their respective

shadow registers, WS, STATUSS

and BSRS. If 's' = 0, no update

occurs (default). Then, the 20-bit

value ‘k’ is loaded into PC<20:1>.

CALLis a two-cycle instruction.

Q Cycle Activity:

If Jump:

Q1

Decode

Q2

Q3

Q4

Read literal

Process

Write to PC

'n'

No

operation

Data

No

operation

No

operation

No

operation

Words:

Cycles:

2

If No Jump:

Q1

Q2

Q3

Q4

Decode

Read literal

Process

No

Q Cycle Activity:

Q1

'n'

Data

operation

Q2

Q3

Q4

Decode

Read literal Push PC to Read literal

'k'<7:0>,

HERE

BZ Jump

Example:

stack

’k’<19:8>,

Write to PC

No

operation

Before Instruction

No

operation

PC

=

address (HERE)

operation

After Instruction

If Zero

PC

=

1;

address (Jump)

HERE

CALL THERE,1

Example:

If Zero

PC

0;

address (HERE+2)

Before Instruction

PC

=

address (HERE)

After Instruction

PC

=

address (THERE)

TOS

WS

address (HERE + 4)

W

BSRS

BSR

STATUSS=

STATUS

DS30485A-page 226

Preliminary

 2002 Microchip Technology Inc.

PIC18FXX39

CLRF

Clear f

CLRWDT

Clear Watchdog Timer

Syntax:

[ label ] CLRF f [,a]

Syntax:

[ label ] CLRWDT

Operands:

0 ≤ f ≤ 255

a ∈ [0,1]

000h → f

1 → Z

Operands:

Operation:

None

000h → WDT,

000h → WDT postscaler,

1 → TO,

1 → PD

TO, PD

Operation:

Status Affected:

Encoding:

Description:

Z

Status Affected:

Encoding:

Description:

0110

101a

ffff

0000

0100

Clears the contents of the specified

register. If ‘a’ is 0, the Access Bank

will be selected, overriding the BSR

value. If ‘a’ = 1, then the bank will

be selected as per the BSR value

(default).

1

CLRWDTinstruction resets the

Watchdog Timer. It also resets the

postscaler of the WDT. Status bits

TO and PD are set.

1

Words:

Cycles:

Words:

Cycles:

Q Cycle Activity:

Q1

Q Cycle Activity:

Q1

Q2

Q3

Q4

Q2

Q3

Q4

Write

Decode

No

Process

No

operation

Data

operation

Decode

Read

Process

register 'f'

Data

register 'f'

CLRWDT

Example:

CLRF

FLAG_REG,1

Example:

Before Instruction

WDT Counter

=

?

Before Instruction

FLAG_REG

=

0x5A

0x00

After Instruction

WDT Counter

=

0x00

After Instruction

WDT Postscaler

0

1

FLAG_REG

TO

PD

 2002 Microchip Technology Inc.

Preliminary

DS30485A-page 227

PIC18FXX39

COMF

Complement f

CPFSEQ

Compare f with W, skip if f = W

Syntax:

[ label ] COMF f [,d [,a]

Syntax:

[ label ] CPFSEQ f [,a]

Operands:

0 ≤ f ≤ 255

d ∈ [0,1]

a ∈ [0,1]

(f) → dest

N, Z

Operands:

0 ≤ f ≤ 255

a ∈ [0,1]

(f) – (W),

skip if (f) = (W)

(unsigned comparison)

Operation:

Status Affected:

Encoding:

Status Affected:

Encoding:

Description:

None

0110

0001

11da

ffff

001a

ffff

Description:

The contents of register 'f' are com-

plemented. If 'd' is 0, the result is

stored in W. If 'd' is 1, the result is

stored back in register 'f' (default). If

‘a’ is 0, the Access Bank will be

selected, overriding the BSR value.

If ‘a’ = 1, then the bank will be

selected as per the BSR value

(default).

Compares the contents of data

memory location 'f' to the contents

of W by performing an unsigned

subtraction.

If 'f' = W, then the fetched instruc-

tion is discarded and a NOPis

executed instead, making this a

two-cycle instruction. If ‘a’ is 0, the

Access Bank will be selected, over-

riding the BSR value. If ‘a’ = 1, then

the bank will be selected as per the

BSR value (default).

Words:

Cycles:

1

Q Cycle Activity:

Q1

Q2

Q3

Q4

Write to

Words:

Cycles:

1

1(2)

Decode

Read

Process

register 'f'

Data

destination

Note: 3 cycles if skip and followed

by a 2-word instruction.

COMF

REG, 0, 0

Example:

Before Instruction

Q Cycle Activity:

Q1

REG

=

0x13

Q2

Q3

Q4

After Instruction

Decode

Read

Process

No

REG

W

=

0x13

0xEC

register 'f'

Data

operation

If skip:

Q1

Q2

No

operation

Q3

No

operation

Q4

No

operation

No

operation

If skip and followed by 2-word instruction:

Q1

Q2

No

Q3

No

Q4

No

operation

No

operation

No

operation

No

operation

No

operation

No

operation

HERE

NEQUAL

EQUAL

CPFSEQ REG, 0

:

Example:

Before Instruction

PC Address

=

HERE

W

=

?

REG

=

After Instruction

If REG

=

W;

PC

Address (EQUAL)

If REG

PC

≠

W;

=

Address (NEQUAL)

DS30485A-page 228

Preliminary

 2002 Microchip Technology Inc.

PIC18FXX39

CPFSGT

Compare f with W, skip if f > W

CPFSLT

Compare f with W, skip if f < W

Syntax:

[ label ] CPFSGT f [,a]

Syntax:

[ label ] CPFSLT f [,a]

Operands:

0 ≤ f ≤ 255

a ∈ [0,1]

Operands:

0 ≤ f ≤ 255

a ∈ [0,1]

Operation:

(f) − (W),

skip if (f) > (W)

(unsigned comparison)

Operation:

(f) – (W),

skip if (f) < (W)

(unsigned comparison)

Status Affected:

Encoding:

None

0110

Status Affected:

Encoding:

None

0110

010a

ffff

000a

ffff

Description:

Compares the contents of data

memory location 'f' to the contents

of the W by performing an

Description:

Compares the contents of data

memory location 'f' to the contents

of W by performing an unsigned

subtraction.

unsigned subtraction.

If the contents of 'f' are greater than

the contents of WREG, then the

fetched instruction is discarded and

a NOPis executed instead, making

this a two-cycle instruction. If ‘a’ is

0, the Access Bank will be

selected, overriding the BSR value.

If ‘a’ = 1, then the bank will be

selected as per the BSR value

(default).

If the contents of 'f' are less than

the contents of W, then the fetched

instruction is discarded and a NOP

is executed instead, making this a

two-cycle instruction. If ‘a’ is 0, the

Access Bank will be selected. If ‘a’

is 1, the BSR will not be overridden

(default).

Words:

Cycles:

1

1(2)

Words:

Cycles:

1

1(2)

Note: 3 cycles if skip and followed

by a 2-word instruction.

Note: 3 cycles if skip and followed

by a 2-word instruction.

Q Cycle Activity:

Q1

Q2

Q3

Q4

Q Cycle Activity:

Q1

Decode

Read

Process

No

Q2

Q3

Q4

register 'f'

Data

operation

Decode

Read

Process

No

If skip:

Q1

register 'f'

Data

operation

Q2

Q3

Q4

If skip:

Q1

No

Q2

Q3

Q4

operation

No

If skip and followed by 2-word instruction:

operation

Q1

No

Q2

Q3

No

Q4

If skip and followed by 2-word instruction:

No

operation

No

Q1

No

Q2

Q3

No

Q4

operation

No

operation

No

operation

No

operation

No

operation

No

operation

No

operation

No

operation

No

operation

HERE

NLESS

LESS

CPFSLT REG, 1

:

Example:

HERE

NGREATER

GREATER

CPFSGT REG, 0

:

Example:

Before Instruction

PC

=

Address (HERE)

W

?

Before Instruction

After Instruction

PC

W

=

Address (HERE)

?

If REG

<

=

W;

PC

Address (LESS)

After Instruction

If REG

PC

≥

W;

If REG

>

W;

=

Address (NLESS)

PC

=

≤

=

Address (GREATER)

If REG

PC

W;

Address (NGREATER)

 2002 Microchip Technology Inc.

Preliminary

DS30485A-page 229

PIC18FXX39

DAW

Decimal Adjust W Register

DECF

Decrement f

Syntax:

[ label ] DAW

Syntax:

[ label ] DECF f [,d [,a]

Operands:

Operation:

None

Operands:

0 ≤ f ≤ 255

d ∈ [0,1]

a ∈ [0,1]

(f) – 1 → dest

C, DC, N, OV, Z

If [W<3:0> >9] or [DC = 1] then

(W<3:0>) + 6 → W<3:0>;

else

(W<3:0>) → W<3:0>;

Operation:

Status Affected:

Encoding:

0000

01da

ffff

If [W<7:4> >9] or [C = 1] then

(W<7:4>) + 6 → W<7:4>;

else

(W<7:4>) → W<7:4>;

C

Description:

Decrement register 'f'. If 'd' is 0, the

result is stored in W. If 'd' is 1, the

result is stored back in register 'f'

(default). If ‘a’ is 0, the Access

Bank will be selected, overriding

the BSR value. If ‘a’ = 1, then the

bank will be selected as per the

BSR value (default).

Status Affected:

Encoding:

Description:

0000

0111

DAWadjusts the eight-bit value in

W, resulting from the earlier addi-

tion of two variables (each in

packed BCD format) and produces

a correct packed BCD result.

Words:

Cycles:

1

Q Cycle Activity:

Q1

Words:

Cycles:

1

Q2

Q3

Q4

Decode

Read

Process

Write to

Q Cycle Activity:

Q1

register 'f'

Data

destination

Q2

Q3

Q4

Decode

Read

register W

Process

Write

DECF

CNT,

1, 0

Example:

Data

W

Before Instruction

DAW

Example1:

CNT

=

0x01

0

Z

=

Before Instruction

After Instruction

W

=

0xA5

CNT

Z

=

0x00

1

C

=

0

DC

=

After Instruction

W

=

0x05

C

DC

=

1

0

Example 2:

Before Instruction

W

=

0xCE

C

=

0

DC

=

After Instruction

W

=

0x34

C

=

1

0

DC

DS30485A-page 230

Preliminary

 2002 Microchip Technology Inc.

PIC18FXX39

DECFSZ

Decrement f, skip if 0

DCFSNZ

Decrement f, skip if not 0

Syntax:

[ label ] DECFSZ f [,d [,a]]

Syntax:

[ label ] DCFSNZ f [,d [,a]

Operands:

0 ≤ f ≤ 255

d ∈ [0,1]

a ∈ [0,1]

Operands:

0 ≤ f ≤ 255

d ∈ [0,1]

a ∈ [0,1]

Operation:

(f) – 1 → dest,

skip if result = 0

Operation:

(f) – 1 → dest,

skip if result ≠ 0

Status Affected:

Encoding:

None

0010

Status Affected:

Encoding:

None

0100

11da

ffff

11da

ffff

Description:

The contents of register 'f' are dec-

remented. If 'd' is 0, the result is

placed in W. If 'd' is 1, the result is

placed back in register 'f' (default).

If the result is 0, the next instruc-

tion, which is already fetched, is

discarded, and a NOPis executed

instead, making it a two-cycle

instruction. If ‘a’ is 0, the Access

Bank will be selected, overriding

the BSR value. If ‘a’ = 1, then the

bank will be selected as per the

BSR value (default).

Description:

The contents of register 'f' are dec-

remented. If 'd' is 0, the result is

placed in W. If 'd' is 1, the result is

placed back in register 'f' (default).

If the result is not 0, the next

instruction, which is already

fetched, is discarded, and a NOPis

executed instead, making it a two-

cycle instruction. If ‘a’ is 0, the

Access Bank will be selected,

overriding the BSR value. If ‘a’ = 1,

then the bank will be selected as

per the BSR value (default).

Words:

Cycles:

1

1(2)

Words:

Cycles:

1

1(2)

Note: 3 cycles if skip and followed

by a 2-word instruction.

Note: 3 cycles if skip and followed

by a 2-word instruction.

Q Cycle Activity:

Q1

Q Cycle Activity:

Q1

Q2

Q3

Process

Data

Q4

Q2

Q3

Process

Data

Q4

Decode

Read

Write to

Decode

Read

Write to

register 'f'

destination

register 'f'

destination

If skip:

Q1

If skip:

Q1

Q2

Q3

Q4

Q2

Q3

Q4

No

operation

If skip and followed by 2-word instruction:

Q1

Q2

No

Q3

No

Q4

Q1

Q2

No

Q3

No

Q4

No

operation

No

operation

No

operation

No

operation

No

operation

No

operation

No

operation

No

operation

No

operation

No

operation

No

operation

HERE

DECFSZ

GOTO

CNT, 1, 1

LOOP

HERE

ZERO

NZERO

DCFSNZ TEMP, 1, 0

:

Example:

CONTINUE

Before Instruction

TEMP

PC

=

Address (HERE)

=

?

After Instruction

CNT

=

≠

=

CNT - 1

0;

TEMP

If TEMP

PC

=

≠

=

TEMP - 1,

If CNT

0;

PC

Address (CONTINUE)

0;

Address (ZERO)

0;

If CNT

PC

If TEMP

PC

Address (HERE+2)

Address (NZERO)

 2002 Microchip Technology Inc.

Preliminary

DS30485A-page 231

PIC18FXX39

GOTO

Unconditional Branch

INCF

Increment f

Syntax:

[ label ] GOTO k

0 ≤ k ≤ 1048575

k → PC<20:1>

None

Syntax:

Operands:

[ label ] INCF f [,d [,a]

Operands:

Operation:

Status Affected:

Encoding:

1st word (k<7:0>)

2nd word(k<19:8>)

0 ≤ f ≤ 255

d ∈ [0,1]

a ∈ [0,1]

(f) + 1 → dest

C, DC, N, OV, Z

Operation:

Status Affected:

Encoding:

1110

1111

k kkk

kkkk

7

0

8

k

kkk kkkk

0010

10da

ffff

19

Description:

GOTOallows an unconditional

Description:

The contents of register 'f' are

incremented. If 'd' is 0, the result is

placed in W. If 'd' is 1, the result is

placed back in register 'f' (default).

If ‘a’ is 0, the Access Bank will be

selected, overriding the BSR value.

If ‘a’ = 1, then the bank will be

selected as per the BSR value

(default).

branch anywhere within entire

2 Mbyte memory range. The 20-bit

value ‘k’ is loaded into PC<20:1>.

GOTOis always a two-cycle

instruction.

2

Words:

Cycles:

Q Cycle Activity:

Q1

Words:

Cycles:

1

Q2

Q3

Q4

Decode

Read literal

No

Read literal

Q Cycle Activity:

Q1

'k'<7:0>,

operation

’k’<19:8>,

Write to PC

No

operation

Q2

Q3

Q4

No

operation

No

operation

No

operation

Decode

Read

register 'f'

Process

Write to

Data

destination

GOTO THERE

Example:

INCF

CNT, 1, 0

Example:

After Instruction

Before Instruction

PC

=

Address (THERE)

CNT

Z

=

0xFF

=

0

?

C

DC

After Instruction

CNT

Z

=

0x00

1

C

DC

DS30485A-page 232

Preliminary

 2002 Microchip Technology Inc.

PIC18FXX39

INCFSZ

Increment f, skip if 0

INFSNZ

Increment f, skip if not 0

Syntax:

[ label ] INCFSZ f [,d [,a]

Syntax:

[ label ] INFSNZ f [,d [,a]

Operands:

0 ≤ f ≤ 255

d ∈ [0,1]

a ∈ [0,1]

Operands:

0 ≤ f ≤ 255

d ∈ [0,1]

a ∈ [0,1]

Operation:

(f) + 1 → dest,

skip if result = 0

Operation:

(f) + 1 → dest,

skip if result ≠ 0

Status Affected:

Encoding:

None

0011

Status Affected:

Encoding:

None

0100

11da

ffff

10da

ffff

Description:

The contents of register 'f' are

incremented. If 'd' is 0, the result is

placed in W. If 'd' is 1, the result is

placed back in register 'f'. (default)

If the result is 0, the next instruc-

tion, which is already fetched, is

discarded, and a NOPis executed

instead, making it a two-cycle

instruction. If ‘a’ is 0, the Access

Bank will be selected, overriding

the BSR value. If ‘a’ = 1, then the

bank will be selected as per the

BSR value (default).

Description:

The contents of register 'f' are

incremented. If 'd' is 0, the result is

placed in W. If 'd' is 1, the result is

placed back in register 'f' (default).

If the result is not 0, the next

instruction, which is already

fetched, is discarded, and a NOPis

executed instead, making it a two-

cycle instruction. If ‘a’ is 0, the

Access Bank will be selected, over-

riding the BSR value. If ‘a’ = 1, then

the bank will be selected as per the

BSR value (default).

Words:

Cycles:

1

1(2)

Words:

Cycles:

1

1(2)

Note: 3 cycles if skip and followed

by a 2-word instruction.

Note: 3 cycles if skip and followed

by a 2-word instruction.

Q Cycle Activity:

Q1

Q Cycle Activity:

Q1

Q2

Q3

Process

Data

Q4

Q2

Q3

Process

Data

Q4

Decode

Read

Write to

Decode

Read

Write to

register 'f'

destination

register 'f'

destination

If skip:

Q1

If skip:

Q1

Q2

Q3

Q4

Q2

Q3

Q4

No

operation

If skip and followed by 2-word instruction:

Q1

Q2

No

Q3

No

Q4

Q1

Q2

No

Q3

No

Q4

No

operation

No

operation

No

operation

No

operation

No

operation

No

operation

No

operation

No

operation

No

operation

No

operation

No

operation

HERE

NZERO

ZERO

INCFSZ

:

CNT, 1, 0

HERE

ZERO

NZERO

INFSNZ REG, 1, 0

Example:

Before Instruction

PC

=

Address (HERE)

PC

=

Address (HERE)

After Instruction

CNT

If CNT

PC

=

≠

=

CNT + 1

REG

If REG

PC

=

≠

=

REG + 1

0;

Address (ZERO)

0;

Address (NZERO)

0;

If CNT

PC

If REG

PC

Address (NZERO)

Address (ZERO)

 2002 Microchip Technology Inc.

Preliminary

DS30485A-page 233

PIC18FXX39

IORLW

Inclusive OR literal with W

IORWF

Inclusive OR W with f

Syntax:

[ label ] IORLW k

0 ≤ k ≤ 255

(W) .OR. k → W

N, Z

Syntax:

Operands:

[ label ] IORWF f [,d [,a]

Operands:

Operation:

Status Affected:

Encoding:

0 ≤ f ≤ 255

d ∈ [0,1]

a ∈ [0,1]

(W) .OR. (f) → dest

N, Z

Operation:

Status Affected:

Encoding:

0000

1001

kkkk

Description:

The contents of W are OR’ed with

the eight-bit literal 'k'. The result is

placed in W.

1

0001

00da

ffff

Description:

Inclusive OR W with register 'f'. If 'd'

is 0, the result is placed in W. If 'd'

is 1, the result is placed back in

register 'f' (default). If ‘a’ is 0, the

Access Bank will be selected, over-

riding the BSR value. If ‘a’ = 1, then

the bank will be selected as per the

BSR value (default).

Words:

Cycles:

Q Cycle Activity:

Q1

Q2

Q3

Process

Data

Q4

Write to W

Decode

Read

literal 'k'

Words:

Cycles:

1

IORLW

0x35

Example:

Before Instruction

Q Cycle Activity:

Q1

W

=

0x9A

Q2

Q3

Q4

Decode

Read

Process

Write to

After Instruction

register 'f'

Data

destination

W

=

0xBF

IORWF RESULT, 0, 1

Example:

Before Instruction

RESULT =

0x13

0x91

W

=

After Instruction

RESULT =

0x13

0x93

W

=

DS30485A-page 234

Preliminary

 2002 Microchip Technology Inc.

PIC18FXX39

LFSR

Load FSR

MOVF

Move f

Syntax:

[ label ] LFSR f,k

Syntax:

[ label ] MOVF f [,d [,a]

Operands:

0 ≤ f ≤ 2

Operands:

0 ≤ f ≤ 255

d ∈ [0,1]

a ∈ [0,1]

f → dest

N, Z

0 ≤ k ≤ 4095

Operation:

Status Affected:

Encoding:

k → FSRf

None

1110

1111

Operation:

Status Affected:

Encoding:

1110

0000

00ff

k kkk

11

kkkk

k kkk

0101

00da

ffff

7

Description:

The 12-bit literal 'k' is loaded into

the file select register pointed to

by 'f'.

2

Description:

The contents of register 'f' are

moved to a destination dependent

upon the status of ‘d’. If 'd' is 0, the

result is placed in W. If 'd' is 1, the

result is placed back in register 'f'

(default). Location 'f' can be any-

where in the 256 byte bank. If ‘a’ is

0, the Access Bank will be

selected, overriding the BSR value.

If ‘a’ = 1, then the bank will be

selected as per the BSR value

(default).

Words:

Cycles:

Q Cycle Activity:

Q1

Q2

Q3

Q4

Decode

Read literal

Process

Write

literal 'k'

MSB to

FSRfH

'k' MSB

Data

Decode

Read literal

'k' LSB

Process

Data

Write literal

'k' to FSRfL

Words:

Cycles:

1

Q Cycle Activity:

Q1

LFSR 2, 0x3AB

Example:

Q2

Q3

Q4

Write W

After Instruction

Decode

Read

Process

FSR2H

FSR2L

=

0x03

0xAB

register 'f'

Data

MOVF

REG, 0, 0

Example:

Before Instruction

REG

W

=

0x22

0xFF

After Instruction

REG

W

=

0x22

 2002 Microchip Technology Inc.

Preliminary

DS30485A-page 235

PIC18FXX39

MOVFF

Move f to f

[ label ] MOVFF f ,f

MOVLB

Move literal to low nibble in BSR

Syntax:

Operands:

Syntax:

[ label ] MOVLB k

0 ≤ k ≤ 255

k → BSR

s d

0 ≤ f ≤ 4095

Operands:

Operation:

Status Affected:

Encoding:

s

0 ≤ f ≤ 4095

d

Operation:

Status Affected:

Encoding:

1st word (source)

2nd word (destin.)

(f ) → f

s

d

None

0000

0001

kkkk

Description:

The 8-bit literal 'k' is loaded into

the Bank Select Register (BSR).

1

1100

1111

ffff

ffff_s

ffff_d

Words:

Cycles:

Description:

The contents of source register 'f '

s

are moved to destination register

'f '. Location of source 'f ' can be

Q Cycle Activity:

Q1

d

s

anywhere in the 4096 byte data

Q2

Q3

Q4

Write

literal 'k' to

BSR

space (000h to FFFh), and location

Decode

Read literal

Process

of destination 'f ' can also be any-

d

'k'

Data

where from 000h to FFFh.

Either source or destination can be

W (a useful special situation).

MOVFFis particularly useful for

transferring a data memory location

to a peripheral register (such as the

transmit buffer or an I/O port).

The MOVFFinstruction cannot use

the PCL, TOSU, TOSH or TOSL as

the destination register.

MOVLB

5

Example:

Before Instruction

BSR register

=

0x02

0x05

After Instruction

BSR register

Note: The MOVFFinstruction

should not be used to mod-

ify interrupt settings while

any interrupt is enabled.

See Section 8.0 for more

information.

Words:

Cycles:

2

2 (3)

Q Cycle Activity:

Q1

Q2

Read

register 'f'

(src)

Q3

Q4

Decode

Process

No

Data

operation

Decode

No

operation

Write

register 'f'

(dest)

operation

No dummy

read

MOVFF

REG1, REG2

Example:

Before Instruction

REG1

=

0x33

REG2

0x11

After Instruction

REG1

REG2

=

0x33,

0x33

DS30485A-page 236

Preliminary

 2002 Microchip Technology Inc.

PIC18FXX39

MOVLW

Move literal to W

MOVWF

Move W to f

Syntax:

[ label ] MOVLW k

0 ≤ k ≤ 255

k → W

Syntax:

Operands:

[ label ] MOVWF f [,a]

0 ≤ f ≤ 255

a ∈ [0,1]

(W) → f

None

Operands:

Operation:

Status Affected:

Encoding:

Operation:

Status Affected:

Encoding:

None

0000

1110

kkkk

0110

111a

ffff

Description:

The eight-bit literal 'k' is loaded

into W.

1

Description:

Move data from W to register 'f'.

Location 'f' can be anywhere in the

256 byte bank. If ‘a’ is 0, the

Access Bank will be selected, over-

riding the BSR value. If ‘a’ = 1, then

the bank will be selected as per the

BSR value (default).

Words:

Cycles:

Q Cycle Activity:

Q1

Q2

Q3

Q4

Write to W

Decode

Read

Process

literal 'k'

Data

Words:

Cycles:

1

MOVLW

0x5A

Example:

Q Cycle Activity:

Q1

After Instruction

Q2

Q3

Q4

Write

W

=

0x5A

Decode

Read

Process

register 'f'

Data

register 'f'

MOVWF

REG, 0

Example:

Before Instruction

W

=

0x4F

0xFF

REG

=

After Instruction

W

=

0x4F

REG

=

 2002 Microchip Technology Inc.

Preliminary

DS30485A-page 237

PIC18FXX39

MULLW

Multiply Literal with W

MULWF

Multiply W with f

Syntax:

[ label ] MULLW

0 ≤ k ≤ 255

(W) x k → PRODH:PRODL

k

Syntax:

Operands:

[ label ] MULWF f [,a]

0 ≤ f ≤ 255

a ∈ [0,1]

(W) x (f) → PRODH:PRODL

None

Operands:

Operation:

Status Affected:

Encoding:

Operation:

Status Affected:

Encoding:

None

0000

1101

kkkk

0000

001a

ffff

Description:

An unsigned multiplication is car-

ried out between the contents of

W and the 8-bit literal 'k'. The

16-bit result is placed in

PRODH:PRODL register pair.

PRODH contains the high byte.

W is unchanged.

None of the status flags are

affected.

Note that neither overflow nor

carry is possible in this opera-

tion. A zero result is possible but

not detected.

Description:

An unsigned multiplication is car-

ried out between the contents of

W and the register file location 'f'.

The 16-bit result is stored in the

PRODH:PRODL register pair.

PRODH contains the high byte.

Both W and 'f' are unchanged.

None of the status flags are

affected.

Note that neither overflow nor

carry is possible in this opera-

tion. A zero result is possible but

not detected. If ‘a’ is 0, the

Access Bank will be selected,

overriding the BSR value. If

‘a’ = 1, then the bank will be

selected as per the BSR value

(default).

Words:

Cycles:

1

Q Cycle Activity:

Q1

Q2

Q3

Q4

Write

registers

PRODH:

PRODL

Decode

Read

Process

literal 'k'

Data

Words:

Cycles:

1

Q Cycle Activity:

Q1

Q2

Q3

Q4

MULLW

0xC4

Example:

Decode

Read

Process

Write

Before Instruction

register 'f'

Data

registers

PRODH:

PRODL

W

=

0xE2

PRODH

=

?

PRODL

After Instruction

W

MULWF

REG, 1

Example:

=

0xE2

PRODH

PRODL

=

0xAD

0x08

Before Instruction

W

=

0xC4

REG

=

0xB5

PRODH

?

PRODL

After Instruction

W

=

0xC4

REG

=

0xB5

0x8A

0x94

PRODH

PRODL

DS30485A-page 238

Preliminary

 2002 Microchip Technology Inc.

PIC18FXX39

NEGF

Negate f

NOP

No Operation

Syntax:

Operands:

[ label ] NEGF f [,a]

0 ≤ f ≤ 255

a ∈ [0,1]

( f ) + 1 → f

N, OV, C, DC, Z

Syntax:

[ label ] NOP

None

No operation

None

Operands:

Operation:

Status Affected:

Encoding:

Operation:

Status Affected:

Encoding:

0000

1111

0000

xxxx

0000

xxxx

0000

xxxx

0110

110a

ffff

Description:

Words:

Cycles:

No operation.

1

Description:

Location ‘f’ is negated using two’s

complement. The result is placed in

the data memory location 'f'. If ‘a’ is

0, the Access Bank will be

Q Cycle Activity:

Q1

selected, overriding the BSR value.

If ‘a’ = 1, then the bank will be

selected as per the BSR value.

Q2

No

operation

Q3

No

Q4

Decode

No

operation

Words:

Cycles:

1

Example:

None.

Q Cycle Activity:

Q1

Q2

Q3

Q4

Decode

Read

Process

Write

register 'f'

Data

register 'f'

NEGF

REG, 1

Example:

Before Instruction

REG

=

0011 1010 [0x3A]

1100 0110 [0xC6]

After Instruction

REG

=

 2002 Microchip Technology Inc.

Preliminary

DS30485A-page 239

PIC18FXX39

POP

Pop Top of Return Stack

PUSH

Push Top of Return Stack

Syntax:

[ label ] POP

None

(TOS) → bit bucket

None

Syntax:

[ label ] PUSH

None

(PC+2) → TOS

None

Operands:

Operation:

Status Affected:

Encoding:

Operands:

Operation:

Status Affected:

Encoding:

0000

0110

0000

0101

Description:

The TOS value is pulled off the

return stack and is discarded. The

TOS value then becomes the previ-

ous value that was pushed onto the

return stack.

This instruction is provided to

enable the user to properly manage

the return stack to incorporate a

software stack.

Description:

The PC+2 is pushed onto the top of

the return stack. The previous TOS

value is pushed down on the stack.

This instruction allows to implement

a software stack by modifying TOS,

and then push it onto the return

stack.

Words:

Cycles:

1

Words:

Cycles:

1

Q Cycle Activity:

Q1

Q2

PUSH PC+2

onto return

stack

Q3

Q4

Q Cycle Activity:

Q1

Decode

No

Q2

Q3

Q4

operation

Decode

No

POP TOS

No

operation

value

operation

PUSH

Example:

POP

Example:

Before Instruction

GOTO

NEW

TOS

PC

=

00345Ah

000124h

Before Instruction

TOS

Stack (1 level down)

=

0031A2h

After Instruction

014332h

PC

=

000126h

00345Ah

TOS

After Instruction

Stack (1 level down)

TOS

PC

=

014332h

NEW

DS30485A-page 240

Preliminary

 2002 Microchip Technology Inc.

PIC18FXX39

RCALL

Relative Call

RESET

Reset

Syntax:

Operands:

Operation:

[ label ] RCALL

-1024 ≤ n ≤ 1023

(PC) + 2 → TOS,

n

Syntax:

Operands:

Operation:

[ label ] RESET

None

Reset all registers and flags that

are affected by a MCLR Reset.

(PC) + 2 + 2n → PC

Status Affected:

Encoding:

None

1101

Status Affected:

Encoding:

All

0000

1nnn

nnnn

0000

1111

Description:

Subroutine call with a jump up to

1K from the current location. First,

return address (PC+2) is pushed

onto the stack. Then, add the 2’s

complement number ‘2n’ to the PC.

Since the PC will have incremented

to fetch the next instruction, the

new address will be PC+2+2n.

This instruction is a two-cycle

instruction.

Description:

This instruction provides a way to

execute a MCLR Reset in software.

1

Words:

Cycles:

Q Cycle Activity:

Q1

Q2

Start

reset

Q3

Q4

Decode

No

operation

Words:

Cycles:

1

2

RESET

Example:

After Instruction

Registers =

Reset Value

Q Cycle Activity:

Q1

Flags*

=

Q2

Q3

Q4

Write to PC

Decode

Read literal

Process

'n'

Data

Push PC to

stack

No

operation

No

operation

No

operation

No

operation

HERE

RCALL

Jump

Example:

Before Instruction

PC

=

Address (HERE)

After Instruction

PC

=

Address (Jump)

TOS =

Address (HERE+2)

 2002 Microchip Technology Inc.

Preliminary

DS30485A-page 241

PIC18FXX39

RETFIE

Return from Interrupt

RETLW

Return Literal to W

Syntax:

Operands:

Operation:

[ label ] RETFIE [s]

s ∈ [0,1]

Syntax:

Operands:

Operation:

[ label ] RETLW k

0 ≤ k ≤ 255

(TOS) → PC,

k → W,

1 → GIE/GIEH or PEIE/GIEL,

if s = 1

(TOS) → PC,

PCLATU, PCLATH are unchanged

(WS) → W,

Status Affected:

Encoding:

Description:

None

(STATUSS) → STATUS,

(BSRS) → BSR,

0000

1100

kkkk

PCLATU, PCLATH are unchanged.

W is loaded with the eight-bit literal

'k'. The program counter is loaded

from the top of the stack (the return

address). The high address latch

(PCLATH) remains unchanged.

1

2

Status Affected:

Encoding:

Description:

GIE/GIEH, PEIE/GIEL.

0000

0001

000s

Return from Interrupt. Stack is

popped and Top-of-Stack (TOS) is

loaded into the PC. Interrupts are

enabled by setting either the high

or low priority global interrupt

enable bit. If ‘s’ = 1, the contents of

the shadow registers WS,

STATUSS and BSRS are loaded

into their corresponding registers,

W, STATUS and BSR. If ‘s’ = 0, no

update of these registers occurs

(default).

Words:

Cycles:

Q Cycle Activity:

Q1

Q2

Q3

Q4

pop PC from

stack, Write

to W

No

operation

Decode

Read

Process

literal 'k'

Data

No

operation

No

operation

Words:

Cycles:

1

2

Example:

CALL TABLE ; W contains table

; offset value

Q Cycle Activity:

Q1

Q2

Q3

Q4

; W now has

; table value

Decode

No

pop PC from

:

operation

stack

Set GIEH or

GIEL

No

operation

TABLE

ADDWF PCL ; W = offset

RETLW k0

RETLW k1

:

; Begin table

;

No

operation

:

RETLW kn

; End of table

RETFIE

1

Example:

After Interrupt

Before Instruction

PC

=

TOS

WS

W

=

0x07

BSR

STATUS

BSRS

STATUSS

1

After Instruction

GIE/GIEH, PEIE/GIEL

W

=

value of kn

DS30485A-page 242

Preliminary

 2002 Microchip Technology Inc.

PIC18FXX39

RETURN

Return from Subroutine

RLCF

Rotate Left f through Carry

Syntax:

Operands:

Operation:

[ label ] RETURN [s]

s ∈ [0,1]

Syntax:

Operands:

[ label ] RLCF f [,d [,a]

0 ≤ f ≤ 255

d ∈ [0,1]

a ∈ [0,1]

(f<n>) → dest<n+1>,

(f<7>) → C,

(C) → dest<0>

(TOS) → PC,

if s = 1

(WS) → W,

Operation:

(STATUSS) → STATUS,

(BSRS) → BSR,

PCLATU, PCLATH are unchanged

Status Affected:

Encoding:

Description:

C, N, Z

Status Affected:

Encoding:

Description:

None

0011

01da

ffff

0000

0001

001s

The contents of register 'f' are

rotated one bit to the left through

the Carry Flag. If 'd' is 0, the result

is placed in W. If 'd' is 1, the result

is stored back in register 'f'

(default). If ‘a’ is 0, the Access

Bank will be selected, overriding

the BSR value. If ‘a’ = 1, then the

bank will be selected as per the

BSR value (default).

Return from subroutine. The stack

is popped and the top of the stack

(TOS) is loaded into the program

counter. If ‘s’= 1, the contents of the

shadow registers WS, STATUSS

and BSRS are loaded into their cor-

responding registers, W, STATUS

and BSR. If ‘s’ = 0, no update of

these registers occurs (default).

Words:

Cycles:

1

2

register f

C

Words:

Cycles:

1

Q Cycle Activity:

Q1

Q2

Q3

Q4

Q Cycle Activity:

Q1

Decode

No

Process

pop PC from

operation

Data

No

operation

stack

No

operation

Q2

Q3

Q4

No

Decode

Read

Process

Write to

operation

register 'f'

Data

destination

RLCF

REG, 0, 0

Example:

RETURN

Example:

Before Instruction

REG

=

1110 0110

0

After Interrupt

C

=

PC = TOS

After Instruction

REG

=

1110 0110

W

=

1100 1100

1

C

=

 2002 Microchip Technology Inc.

Preliminary

DS30485A-page 243

PIC18FXX39

RLNCF

Rotate Left f (no carry)

RRCF

Rotate Right f through Carry

Syntax:

[ label ] RLNCF f [,d [,a]

Syntax:

[ label ] RRCF f [,d [,a]

Operands:

0 ≤ f ≤ 255

d ∈ [0,1]

a ∈ [0,1]

Operands:

0 ≤ f ≤ 255

d ∈ [0,1]

a ∈ [0,1]

Operation:

(f<n>) → dest<n+1>,

(f<7>) → dest<0>

N, Z

Operation:

(f<n>) → dest<n-1>,

(f<0>) → C,

(C) → dest<7>

Status Affected:

Encoding:

Description:

Status Affected:

Encoding:

Description:

C, N, Z

0100

01da

ffff

0011

00da

ffff

The contents of register 'f' are

rotated one bit to the left. If 'd' is 0,

the result is placed in W. If 'd' is 1,

the result is stored back in register

'f' (default). If ‘a’ is 0, the Access

Bank will be selected, overriding

the BSR value. If ‘a’ is 1, then the

bank will be selected as per the

BSR value (default).

The contents of register 'f' are

rotated one bit to the right through

the Carry Flag. If 'd' is 0, the result

is placed in W. If 'd' is 1, the result

is placed back in register 'f'

(default). If ‘a’ is 0, the Access

Bank will be selected, overriding

the BSR value. If ‘a’ is 1, then the

bank will be selected as per the

BSR value (default).

register f

Words:

Cycles:

1

register f

C

Words:

Cycles:

1

Q Cycle Activity:

Q1

Q2

Q3

Q4

Q Cycle Activity:

Q1

Decode

Read

register 'f'

Process

Write to

Data

destination

Q2

Q3

Q4

Decode

Read

register 'f'

Process

Write to

Data

destination

RLNCF

REG, 1, 0

Example:

Before Instruction

RRCF

REG, 0, 0

Example:

REG

=

1010 1011

0101 0111

After Instruction

Before Instruction

REG

=

REG

=

1110 0110

C

=

0

After Instruction

REG

=

1110 0110

W

=

0111 0011

0

C

=

DS30485A-page 244

Preliminary

 2002 Microchip Technology Inc.

PIC18FXX39

RRNCF

Rotate Right f (no carry)

SETF

Set f

Syntax:

[ label ] RRNCF f [,d [,a]

Syntax:

[ label ] SETF f [,a]

Operands:

0 ≤ f ≤ 255

d ∈ [0,1]

a ∈ [0,1]

(f<n>) → dest<n-1>,

(f<0>) → dest<7>

Operands:

0 ≤ f ≤ 255

a ∈ [0,1]

FFh → f

None

0110

Operation:

Status Affected:

Encoding:

Operation:

100a

ffff

Status Affected:

Encoding:

Description:

N, Z

0100

Description:

The contents of the specified regis-

ter are set to FFh. If ‘a’ is 0, the

Access Bank will be selected, over-

riding the BSR value. If ‘a’ is 1, then

the bank will be selected as per the

BSR value (default).

1

00da

ffff

The contents of register 'f' are

rotated one bit to the right. If 'd' is 0,

the result is placed in W. If 'd' is 1,

the result is placed back in register

'f' (default). If ‘a’ is 0, the Access

Bank will be selected, overriding

the BSR value. If ‘a’ is 1, then the

bank will be selected as per the

BSR value (default).

Words:

Cycles:

Q Cycle Activity:

Q1

Q2

Q3

Q4

Write

register f

Decode

Read

Process

register 'f'

Data

register 'f'

Words:

Cycles:

1

SETF

REG,1

Example:

Before Instruction

Q Cycle Activity:

Q1

REG

=

0x5A

0xFF

Q2

Q3

Q4

After Instruction

Decode

Read

register 'f'

Process

Write to

REG

=

Data

destination

RRNCF

REG, 1, 0

Example 1:

Before Instruction

REG

=

1101 0111

1110 1011

RRNCF REG, 0, 0

After Instruction

REG

=

Example 2:

Before Instruction

W

=

?

REG

=

1101 0111

After Instruction

W

=

1110 1011

1101 0111

REG

=

 2002 Microchip Technology Inc.

Preliminary

DS30485A-page 245

PIC18FXX39

SLEEP

Enter SLEEP mode

SUBFWB

Subtract f from W with borrow

Syntax:

[ label ] SLEEP

Syntax:

[ label ] SUBFWB f [,d [,a]

Operands:

Operation:

None

Operands:

0 ≤ f ≤ 255

d ∈ [0,1]

a ∈ [0,1]

(W) – (f) – (C) → dest

N, OV, C, DC, Z

00h → WDT,

0 → WDT postscaler,

1 → TO,

0 → PD

TO, PD

Operation:

Status Affected:

Encoding:

Status Affected:

Encoding:

0101

01da

ffff

0000

0011

Description:

Subtract register 'f' and carry flag

(borrow) from W (2’s complement

method). If 'd' is 0, the result is

stored in W. If 'd' is 1, the result is

stored in register 'f' (default). If ‘a’ is

0, the Access Bank will be selected,

overriding the BSR value. If ‘a’ is 1,

then the bank will be selected as

per the BSR value (default).

Description:

The power-down status bit (PD) is

cleared. The time-out status bit

(TO) is set. Watchdog Timer and

its postscaler are cleared.

The processor is put into SLEEP

mode with the oscillator stopped.

1

Words:

Cycles:

Words:

Cycles:

1

Q Cycle Activity:

Q1

Q2

Q3

Q4

Q Cycle Activity:

Q1

Decode

No

Process

Go to

Q2

Q3

Q4

Write to

operation

Data

sleep

Decode

Read

Process

register 'f'

Data

destination

SLEEP

Example:

SUBFWB

REG, 1, 0

Example 1:

Before Instruction

TO

PD

=

?

Before Instruction

REG

=

3

W

=

2

After Instruction

C

=

1

TO

PD

=

1 †

0

After Instruction

REG

W

=

FF

2

† If WDT causes wake-up, this bit is cleared.

C

Z

=

0

1

N

; result is negative

SUBFWB

REG, 0, 0

Example 2:

Before Instruction

REG

=

2

W

=

5

C

=

1

After Instruction

REG

W

=

2

3

C

Z

=

1

0

N

; result is positive

SUBFWB

REG, 1, 0

Example 3:

Before Instruction

REG

=

1

W

=

2

C

=

0

After Instruction

REG

W

=

0

2

C

Z

=

1

0

; result is zero

N

DS30485A-page 246

Preliminary

 2002 Microchip Technology Inc.

PIC18FXX39

SUBLW

Subtract W from literal

SUBWF

Syntax:

Subtract W from f

Syntax:

[ label ] SUBLW k

0 ≤ k ≤ 255

k – (W) → W

[ label ] SUBWF f [,d [,a]

Operands:

Operation:

Status Affected:

Encoding:

Operands:

0 ≤ f ≤ 255

d ∈ [0,1]

a ∈ [0,1]

(f) – (W) → dest

N, OV, C, DC, Z

Operation:

Status Affected:

Encoding:

0000

1000

kkkk

Description:

W is subtracted from the eight-bit

literal 'k'. The result is placed

in W.

1

0101

11da

ffff

Description:

Subtract W from register 'f' (2’s

complement method). If 'd' is 0,

the result is stored in W. If 'd' is 1,

the result is stored back in regis-

ter 'f' (default). If ‘a’ is 0, the

Access Bank will be selected,

overriding the BSR value. If ‘a’ is

1, then the bank will be selected

as per the BSR value (default).

Words:

Cycles:

Q Cycle Activity:

Q1

Q2

Q3

Q4

Decode

Read

Process

Write to W

literal 'k'

Data

SUBLW 0x02

Example 1:

Words:

Cycles:

1

Before Instruction

W

=

1

?

Q Cycle Activity:

Q1

C

=

Q2

Q3

Process

Data

Q4

After Instruction

Decode

Read

Write to

W

=

1

register 'f'

destination

C

Z

=

1

0

; result is positive

SUBWF

REG, 1, 0

Example 1:

N

SUBLW 0x02

Example 2:

Before Instruction

REG

=

3

Before Instruction

W

=

2

W

=

2

?

C

=

?

C

=

After Instruction

REG

W

=

1

2

W

=

0

C

Z

=

1

0

; result is positive

C

Z

=

1

0

; result is zero

N

SUBWF

REG, 0, 0

Example 2:

SUBLW 0x02

Example 3:

Before Instruction

REG

=

2

W

=

3

?

W

=

2

C

=

C

=

?

After Instruction

W

=

FF ; (2’s complement)

REG

W

=

2

0

C

Z

=

0

1

; result is negative

C

Z

=

1

0

; result is zero

N

SUBWF

REG, 1, 0

Example 3:

Before Instruction

REG

=

1

W

=

2

C

=

?

After Instruction

REG

W

=

FFh ;(2’s complement)

2

C

Z

=

0

1

; result is negative

N

 2002 Microchip Technology Inc.

Preliminary

DS30485A-page 247

PIC18FXX39

SUBWFB

Syntax:

Subtract W from f with Borrow

SWAPF

Swap f

Syntax:

[ label ] SWAPF f [,d [,a]

[ label ] SUBWFB f [,d [,a]

Operands:

0 ≤ f ≤ 255

d ∈ [0,1]

a ∈ [0,1]

Operands:

0 ≤ f ≤ 255

d ∈ [0,1]

a ∈ [0,1]

Operation:

(f<3:0>) → dest<7:4>,

(f<7:4>) → dest<3:0>

None

Operation:

Status Affected: N, OV, C, DC, Z

Encoding:

Description:

(f) – (W) – (C) → dest

Status Affected:

Encoding:

Description:

0101

10da

ffff

0011

10da

ffff

Subtract W and the carry flag (bor-

row) from register 'f' (2’s complement

method). If 'd' is 0, the result is stored

in W. If 'd' is 1, the result is stored

back in register 'f' (default). If ‘a’ is 0,

the Access Bank will be selected,

overriding the BSR value. If ‘a’ is 1,

then the bank will be selected as per

the BSR value (default).

The upper and lower nibbles of reg-

ister 'f' are exchanged. If 'd' is 0, the

result is placed in W. If 'd' is 1, the

result is placed in register 'f'

(default). If ‘a’ is 0, the Access

Bank will be selected, overriding

the BSR value. If ‘a’ is 1, then the

bank will be selected as per the

BSR value (default).

Words:

Cycles:

1

Words:

Cycles:

1

Q Cycle Activity:

Q1

Q Cycle Activity:

Q1

Q2

Q3

Process

Data

Q4

Q2

Q3

Process

Data

Q4

Decode

Read

Write to

Decode

Read

Write to

register 'f'

destination

register 'f'

destination

SUBWFB REG, 1, 0

Example 1:

Before Instruction

SWAPF

REG, 1, 0

Example:

REG

=

0x19

(0001 1001)

(0000 1101)

Before Instruction

W

=

0x0D

REG

=

0x53

0x35

C

=

1

After Instruction

REG

=

REG

W

=

0x0C

0x0D

(0000 1011)

(0000 1101)

C

Z

=

1

0

N

; result is positive

SUBWFB REG, 0, 0

Example 2:

Before Instruction

REG

=

0x1B

(0001 1011)

(0001 1010)

W

=

0x1A

C

=

0

After Instruction

REG

W

=

0x1B

0x00

(0001 1011)

C

Z

=

1

0

; result is zero

N

SUBWFB REG, 1, 0

Example 3:

Before Instruction

REG

=

0x03

(0000 0011)

(0000 1101)

W

=

0x0E

C

=

1

After Instruction

REG

=

0xF5

0x0E

(1111 0100)

; [2’s comp]

(0000 1101)

W

=

C

Z

=

0

1

N

; result is negative

DS30485A-page 248

Preliminary

 2002 Microchip Technology Inc.

PIC18FXX39

TBLRD

Table Read

TBLRD

Table Read (cont’d)

TBLRD *+ ;

Syntax:

[ label ] TBLRD ( *; *+; *-; +*)

Example1:

Operands:

Operation:

None

if TBLRD *,

Before Instruction

TABLAT

=

0x55

TBLPTR

0x00A356

0x34

(Prog Mem (TBLPTR)) → TABLAT;

TBLPTR - No Change;

if TBLRD *+,

MEMORY(0x00A356)

After Instruction

TABLAT

TBLPTR

=

0x34

(Prog Mem (TBLPTR)) → TABLAT;

(TBLPTR) +1 → TBLPTR;

if TBLRD *-,

0x00A357

TBLRD +* ;

Example2:

(Prog Mem (TBLPTR)) → TABLAT;

(TBLPTR) -1 → TBLPTR;

if TBLRD +*,

Before Instruction

TABLAT

TBLPTR

=

0xAA

0x01A357

0x12

MEMORY(0x01A357)

(TBLPTR) +1 → TBLPTR;

(Prog Mem (TBLPTR)) → TABLAT;

MEMORY(0x01A358)

0x34

After Instruction

Status Affected:None

Encoding:

TABLAT

TBLPTR

=

0x34

0x01A358

0000

10nn

nn=0 *

=1 *+

=2 *-

=3 +*

Description:

This instruction is used to read the con-

tents of Program Memory (P.M.). To

address the program memory, a pointer

called Table Pointer (TBLPTR) is used.

The TBLPTR (a 21-bit pointer) points

to each byte in the program memory.

TBLPTR has a 2 Mbyte address range.

TBLPTR[0] = 0: Least Significant

Byte of Program

Memory Word

TBLPTR[0] = 1: Most Significant

Byte of Program

Memory Word

The TBLRDinstruction can modify the

value of TBLPTR as follows:

• no change

• post-increment

• post-decrement

• pre-increment

Words:

Cycles:

1

2

Q Cycle Activity:

Q1

Q2

Q3

Q4

Decode

No

operation

No

No operation

No

No operation

operation (Read Program operation (Write TABLAT)

Memory)

 2002 Microchip Technology Inc.

Preliminary

DS30485A-page 249

PIC18FXX39

TBLWT

Table Write

TBLWT

Table Write (Continued)

TBLWT *+;

Syntax:

[ label ]

TBLWT ( *; *+; *-; +*)

Example1:

Operands:

Operation:

None

if TBLWT*,

Before Instruction

TABLAT

=

0x55

TBLPTR

0x00A356

(TABLAT) → Holding Register;

TBLPTR - No Change;

if TBLWT*+,

HOLDING REGISTER

(0x00A356)

=

0xFF

After Instructions (table write completion)

(TABLAT) → Holding Register;

(TBLPTR) +1 → TBLPTR;

if TBLWT*-,

TABLAT

=

0x55

TBLPTR

0x00A357

HOLDING REGISTER

(0x00A356)

=

0x55

(TABLAT) → Holding Register;

(TBLPTR) -1 → TBLPTR;

if TBLWT+*,

TBLWT +*;

Example 2:

Before Instruction

(TBLPTR) +1 → TBLPTR;

(TABLAT) → Holding Register;

TABLAT

=

0x34

TBLPTR

0x01389A

HOLDING REGISTER

(0x01389A)

Status Affected: None

Encoding:

=

0xFF

HOLDING REGISTER

0000

11nn

nn=0 *

=1 *+

=2 *-

=3 +*

(0x01389B)

=

0xFF

After Instruction (table write completion)

TABLAT

=

0x34

TBLPTR

0x01389B

HOLDING REGISTER

(0x01389A)

=

0xFF

0x34

Description:

This instruction uses the 3 LSbs of the

TBLPTR to determine which of the 8

holding registers the TABLAT data is

written to. The 8 holding registers are

used to program the contents of Pro-

gram Memory (P.M.). See Section 5.0

for information on writing to FLASH

memory.

HOLDING REGISTER

(0x01389B)

The TBLPTR (a 21-bit pointer) points

to each byte in the program memory.

TBLPTR has a 2 MBtye address

range. The LSb of the TBLPTR selects

which byte of the program memory

location to access.

TBLPTR[0] = 0:Least Significant

Byte of Program

Memory Word

TBLPTR[0] = 1:Most Significant

Byte of Program

Memory Word

The TBLWT instruction can modify the

value of TBLPTR as follows:

• no change

• post-increment

• post-decrement

• pre-increment

Words:

Cycles:

1

2

Q Cycle Activity:

Q1

Q2

No

Q3

Q4

Decode

No

operation

No

operation

No

operation

No

operation

(Read

operation

(Write to Holding

Register or Memory)

TABLAT)

DS30485A-page 250

Preliminary

 2002 Microchip Technology Inc.

PIC18FXX39

TSTFSZ

Test f, skip if 0

XORLW

Exclusive OR literal with W

Syntax:

Operands:

[ label ] TSTFSZ f [,a]

0 ≤ f ≤ 255

a ∈ [0,1]

skip if f = 0

None

Syntax:

[ label ] XORLW k

0 ≤ k ≤ 255

(W) .XOR. k → W

N, Z

Operands:

Operation:

Status Affected:

Encoding:

Operation:

Status Affected:

Encoding:

0000

1010

kkkk

0110

011a

ffff

Description:

The contents of W are XORed

with the 8-bit literal 'k'. The result

is placed in W.

1

Description:

If 'f' = 0, the next instruction,

fetched during the current instruc-

tion execution, is discarded and a

NOPis executed, making this a two-

cycle instruction. If ‘a’ is 0, the

Access Bank will be selected, over-

riding the BSR value. If ‘a’ is 1,

then the bank will be selected as

per the BSR value (default).

Words:

Cycles:

Q Cycle Activity:

Q1

Q2

Q3

Q4

Write to W

Decode

Read

Process

literal 'k'

Data

Words:

Cycles:

1

1(2)

Example:

XORLW 0xAF

= 0xB5

Note: 3 cycles if skip and followed

by a 2-word instruction.

Before Instruction

W

Q Cycle Activity:

Q1

After Instruction

Q2

Q3

Process

Data

Q4

No

operation

W

=

0x1A

Decode

Read

register 'f'

If skip:

Q1

Q2

Q3

Q4

No

operation

If skip and followed by 2-word instruction:

Q1

Q2

No

Q3

No

Q4

No

operation

No

operation

No

operation

No

operation

No

operation

No

operation

HERE

NZERO

ZERO

TSTFSZ CNT, 1

:

Example:

:

Before Instruction

PC = Address (HERE)

After Instruction

If CNT

=

≠

=

0x00,

PC

Address (ZERO)

0x00,

If CNT

PC

Address (NZERO)

 2002 Microchip Technology Inc.

Preliminary

DS30485A-page 251

PIC18FXX39

XORWF

Exclusive OR W with f

Syntax:

[ label ] XORWF f [,d [,a]

Operands:

0 ≤ f ≤ 255

d ∈ [0,1]

a ∈ [0,1]

Operation:

(W) .XOR. (f) → dest

Status Affected:

Encoding:

N, Z

0001

10da

ffff

Description:

Exclusive OR the contents of W

with register 'f'. If 'd' is 0, the result

is stored in W. If 'd' is 1, the result is

stored back in the register 'f'

(default). If ‘a’ is 0, the Access

Bank will be selected, overriding

the BSR value. If ‘a’ is 1, then the

bank will be selected as per the

BSR value (default).

Words:

Cycles:

1

Q Cycle Activity:

Q1

Q2

Q3

Q4

Decode

Read

Process

Write to

register 'f'

Data

destination

XORWF

REG, 1, 0

Example:

Before Instruction

REG

W

=

0xAF

0xB5

=

After Instruction

REG

W

=

0x1A

0xB5

DS30485A-page 252

Preliminary

 2002 Microchip Technology Inc.

PIC18FXX39

The MPLAB IDE allows you to:

• Edit your source files (either assembly or ‘C’)

• One touch assemble (or compile) and download

to PICmicro emulator and simulator tools (auto-

matically updates all project information)

• Debug using:

- source files

- absolute listing file

- machine code

The ability to use MPLAB IDE with multiple debugging

tools allows users to easily switch from the cost-

effective simulator to a full-featured emulator with

minimal retraining.

22.0 DEVELOPMENT SUPPORT

The PICmicro^®microcontrollers are supported with a

full range of hardware and software development tools:

• Integrated Development Environment

- MPLAB^®IDE Software

• Assemblers/Compilers/Linkers

- MPASM^TMAssembler

- MPLAB C17 and MPLAB C18 C Compilers

- MPLINK^TMObject Linker/

MPLIB^TMObject Librarian

• Simulators

- MPLAB SIM Software Simulator

• Emulators

- MPLAB ICE 2000 In-Circuit Emulator

- ICEPIC™ In-Circuit Emulator

• In-Circuit Debugger

22.2 MPASM Assembler

The MPASM assembler is a full-featured universal

macro assembler for all PICmicro MCU’s.

- MPLAB ICD

The MPASM assembler has a command line interface

and a Windows shell. It can be used as a stand-alone

application on a Windows 3.x or greater system, or it

can be used through MPLAB IDE. The MPASM assem-

bler generates relocatable object files for the MPLINK

object linker, Intel^®standard HEX files, MAP files to

detail memory usage and symbol reference, an abso-

lute LST file that contains source lines and generated

machine code, and a COD file for debugging.

The MPASM assembler features include:

• Integration into MPLAB IDE projects.

• User-defined macros to streamline assembly

code.

• Device Programmers

- PRO MATE^®II Universal Device Programmer

- PICSTART^®Plus Entry-Level Development

Programmer

• Low Cost Demonstration Boards

- PICDEM^TM1 Demonstration Board

- PICDEM 2 Demonstration Board

- PICDEM 3 Demonstration Board

- PICDEM 17 Demonstration Board

- KEELOQ^®Demonstration Board

22.1 MPLAB Integrated Development

Environment Software

• Conditional assembly for multi-purpose source

files.

The MPLAB IDE software brings an ease of software

development previously unseen in the 8-bit microcon-

troller market. The MPLAB IDE is a Windows^®based

application that contains:

• An interface to debugging tools

- simulator

- programmer (sold separately)

- emulator (sold separately)

- in-circuit debugger (sold separately)

• A full-featured editor

• Directives that allow complete control over the

assembly process.

22.3 MPLAB C17 and MPLAB C18

C Compilers

The MPLAB C17 and MPLAB C18 Code Development

Systems are complete ANSI ‘C’ compilers for

Microchip’s PIC17CXXX and PIC18CXXX family of

microcontrollers, respectively. These compilers provide

powerful integration capabilities and ease of use not

found with other compilers.

• A project manager

• Customizable toolbar and key mapping

• A status bar

For easier source level debugging, the compilers pro-

vide symbol information that is compatible with the

MPLAB IDE memory display.

• On-line help

 2002 Microchip Technology Inc.

Preliminary

DS30485A-page 253

PIC18FXX39

22.4 MPLINK Object Linker/

22.6 MPLAB ICE High Performance

Universal In-Circuit Emulator with

MPLAB IDE

The MPLAB ICE universal in-circuit emulator is intended

to provide the product development engineer with a

complete microcontroller design tool set for PICmicro

microcontrollers (MCUs). Software control of the

MPLAB ICE in-circuit emulator is provided by the

MPLAB Integrated Development Environment (IDE),

which allows editing, building, downloading and source

debugging from a single environment.

The MPLAB ICE 2000 is a full-featured emulator sys-

tem with enhanced trace, trigger and data monitoring

features. Interchangeable processor modules allow the

system to be easily reconfigured for emulation of differ-

ent processors. The universal architecture of the

MPLAB ICE in-circuit emulator allows expansion to

support new PICmicro microcontrollers.

The MPLAB ICE in-circuit emulator system has been

designed as a real-time emulation system, with

advanced features that are generally found on more

expensive development tools. The PC platform and

Microsoft^®Windows environment were chosen to best

make these features available to you, the end user.

MPLIB Object Librarian

The MPLINK object linker combines relocatable

objects created by the MPASM assembler and the

MPLAB C17 and MPLAB C18 C compilers. It can also

link relocatable objects from pre-compiled libraries,

using directives from a linker script.

The MPLIB object librarian is a librarian for pre-

compiled code to be used with the MPLINK object

linker. When a routine from a library is called from

another source file, only the modules that contain that

routine will be linked in with the application. This allows

large libraries to be used efficiently in many different

applications. The MPLIB object librarian manages the

creation and modification of library files.

The MPLINK object linker features include:

• Integration with MPASM assembler and MPLAB

C17 and MPLAB C18 C compilers.

• Allows all memory areas to be defined as sections

to provide link-time flexibility.

The MPLIB object librarian features include:

• Easier linking because single libraries can be

included instead of many smaller files.

• Helps keep code maintainable by grouping

related modules together.

22.7 ICEPIC In-Circuit Emulator

• Allows libraries to be created and modules to be

The ICEPIC low cost, in-circuit emulator is a solution

for the Microchip Technology PIC16C5X, PIC16C6X,

PIC16C7X and PIC16CXXX families of 8-bit One-

Time-Programmable (OTP) microcontrollers. The mod-

ular system can support different subsets of PIC16C5X

or PIC16CXXX products through the use of inter-

changeable personality modules, or daughter boards.

The emulator is capable of emulating without target

application circuitry being present.

added, listed, replaced, deleted or extracted.

22.5 MPLAB SIM Software Simulator

The MPLAB SIM software simulator allows code devel-

opment in a PC-hosted environment by simulating the

PICmicro series microcontrollers on an instruction

level. On any given instruction, the data areas can be

examined or modified and stimuli can be applied from

a file, or user-defined key press, to any of the pins. The

execution can be performed in single step, execute

until break, or trace mode.

The MPLAB SIM simulator fully supports symbolic debug-

ging using the MPLAB C17 and the MPLAB C18 C com-

pilers and the MPASM assembler. The software simulator

offers the flexibility to develop and debug code outside of

the laboratory environment, making it an excellent multi-

project software development tool.

DS30485A-page 254

Preliminary

 2002 Microchip Technology Inc.

PIC18FXX39

22.8 MPLAB ICD In-Circuit Debugger

22.11 PICDEM 1 Low Cost PICmicro

Demonstration Board

Microchip's In-Circuit Debugger, MPLAB ICD, is a pow-

erful, low cost, run-time development tool. This tool is

based on the FLASH PICmicro MCUs and can be used

to develop for this and other PICmicro microcontrollers.

The MPLAB ICD utilizes the in-circuit debugging capa-

bility built into the FLASH devices. This feature, along

with Microchip's In-Circuit Serial Programming^TMproto-

col, offers cost-effective in-circuit FLASH debugging

from the graphical user interface of the MPLAB

Integrated Development Environment. This enables a

designer to develop and debug source code by watch-

ing variables, single-stepping and setting break points.

Running at full speed enables testing hardware in real-

time.

The PICDEM 1 demonstration board is a simple board

which demonstrates the capabilities of several of

Microchip’s microcontrollers. The microcontrollers sup-

ported are: PIC16C5X (PIC16C54 to PIC16C58A),

PIC16C61, PIC16C62X, PIC16C71, PIC16C8X,

PIC17C42, PIC17C43 and PIC17C44. All necessary

hardware and software is included to run basic demo

programs. The user can program the sample microcon-

trollers provided with the PICDEM 1 demonstration

board on a PRO MATE II device programmer, or a

PICSTART Plus development programmer, and easily

test firmware. The user can also connect the

PICDEM 1 demonstration board to the MPLAB ICE in-

circuit emulator and download the firmware to the emu-

lator for testing. A prototype area is available for the

user to build some additional hardware and connect it

to the microcontroller socket(s). Some of the features

include an RS-232 interface, a potentiometer for simu-

lated analog input, push button switches and eight

LEDs connected to PORTB.

22.9 PRO MATE II Universal Device

Programmer

The PRO MATE II universal device programmer is a

full-featured programmer, capable of operating in

stand-alone mode, as well as PC-hosted mode. The

PRO MATE II device programmer is CE compliant.

The PRO MATE II device programmer has program-

mable VDD and VPP supplies, which allow it to verify

programmed memory at VDD min and VDD max for max-

imum reliability. It has an LCD display for instructions

and error messages, keys to enter commands and a

modular detachable socket assembly to support various

package types. In stand-alone mode, the PRO MATE II

device programmer can read, verify, or program

PICmicro devices. It can also set code protection in this

mode.

22.12 PICDEM 2 Low Cost PIC16CXX

Demonstration Board

The PICDEM 2 demonstration board is a simple dem-

onstration board that supports the PIC16C62,

PIC16C64, PIC16C65, PIC16C73 and PIC16C74

microcontrollers. All the necessary hardware and soft-

ware is included to run the basic demonstration pro-

grams. The user can program the sample

microcontrollers provided with the PICDEM 2 demon-

stration board on a PRO MATE II device programmer,

or a PICSTART Plus development programmer, and

easily test firmware. The MPLAB ICE in-circuit emula-

tor may also be used with the PICDEM 2 demonstration

board to test firmware. A prototype area has been pro-

vided to the user for adding additional hardware and

connecting it to the microcontroller socket(s). Some of

the features include a RS-232 interface, push button

switches, a potentiometer for simulated analog input, a

22.10 PICSTART Plus Entry Level

Development Programmer

The PICSTART Plus development programmer is an

easy-to-use, low cost, prototype programmer. It con-

nects to the PC via a COM (RS-232) port. MPLAB

Integrated Development Environment software makes

using the programmer simple and efficient.

The PICSTART Plus development programmer sup-

ports all PICmicro devices with up to 40 pins. Larger pin

count devices, such as the PIC16C92X and

PIC17C76X, may be supported with an adapter socket.

The PICSTART Plus development programmer is CE

compliant.

2

serial EEPROM to demonstrate usage of the I C^TMbus

and separate headers for connection to an LCD

module and a keypad.

 2002 Microchip Technology Inc.

Preliminary

DS30485A-page 255

PIC18FXX39

22.13 PICDEM 3 Low Cost PIC16CXXX

22.14 PICDEM 17 Demonstration Board

Demonstration Board

The PICDEM 17 demonstration board is an evaluation

board that demonstrates the capabilities of several

Microchip microcontrollers, including PIC17C752,

PIC17C756A, PIC17C762 and PIC17C766. All neces-

sary hardware is included to run basic demo programs,

which are supplied on a 3.5-inch disk. A programmed

sample is included and the user may erase it and

program it with the other sample programs using the

PRO MATE II device programmer, or the PICSTART

Plus development programmer, and easily debug and

test the sample code. In addition, the PICDEM 17 dem-

onstration board supports downloading of programs to

and executing out of external FLASH memory on board.

The PICDEM 17 demonstration board is also usable

with the MPLAB ICE in-circuit emulator, or the

PICMASTER emulator and all of the sample programs

can be run and modified using either emulator. Addition-

ally, a generous prototype area is available for user

hardware.

The PICDEM 3 demonstration board is a simple dem-

onstration board that supports the PIC16C923 and

PIC16C924 in the PLCC package. It will also support

future 44-pin PLCC microcontrollers with an LCD Mod-

ule. All the necessary hardware and software is

included to run the basic demonstration programs. The

user can program the sample microcontrollers pro-

vided with the PICDEM 3 demonstration board on a

PRO MATE II device programmer, or a PICSTART Plus

development programmer with an adapter socket, and

easily test firmware. The MPLAB ICE in-circuit emula-

tor may also be used with the PICDEM 3 demonstration

board to test firmware. A prototype area has been pro-

vided to the user for adding hardware and connecting it

to the microcontroller socket(s). Some of the features

include a RS-232 interface, push button switches, a

potentiometer for simulated analog input, a thermistor

and separate headers for connection to an external

LCD module and a keypad. Also provided on the

PICDEM 3 demonstration board is a LCD panel, with 4

commons and 12 segments, that is capable of display-

ing time, temperature and day of the week. The

PICDEM 3 demonstration board provides an additional

RS-232 interface and Windows software for showing

the demultiplexed LCD signals on a PC. A simple serial

interface allows the user to construct a hardware

demultiplexer for the LCD signals.

22.15 KEELOQ Evaluation and

Programming Tools

KEELOQ evaluation and programming tools support

Microchip’s HCS Secure Data Products. The HCS eval-

uation kit includes a LCD display to show changing

codes, a decoder to decode transmissions and a pro-

gramming interface to program test transmitters.

DS30485A-page 256

Preliminary

 2002 Microchip Technology Inc.

PIC18FXX39

TABLE 22-1: DEVELOPMENT TOOLS FROM MICROCHIP

0 1 5 2 P M C

X X X C R M F

H C S X X X

X X C 9 3

/ X X C 2 5

/ X X C 2 4

X X X F 8 C 1 P I

X X C 8 2 C 1 P I

X 7 X 7 C 1 C I P

X 4 1 7 C I C P

X 9 X 6 C 1 C I P

X 8 X 6 F 1 C I P

8 X 6 1 F C I P

/ X 8 1 6 C I C P

X 7 X 6 C 1 C I P

X 7 1 6 C I C P

X 6 2 1 6 C I F P

X

X X C 6 C 1 P I

X 6 1 6 C I C P

X 5 1 6 C I C P

0 0 1 4 C I 0 P

X

X X C 2 C 1 P I

s o l T e o r a w f t S o s r o t a u l E m r e g g u b D e s r e m m a o g P r r

s t K l a i E d v n a s d r a B o o m D e

 2002 Microchip Technology Inc.

Preliminary

DS30485A-page 257

PIC18FXX39

NOTES:

DS30485A-page 258

Preliminary

 2002 Microchip Technology Inc.

PIC18FXX39

23.0 ELECTRICAL CHARACTERISTICS

(†)

Absolute Maximum Ratings

Ambient temperature under bias.............................................................................................................-55°C to +125°C

Storage temperature .............................................................................................................................. -65°C to +150°C

Voltage on any pin with respect to VSS (except VDD, MCLR, and RA4) ......................................... -0.3V to (VDD + 0.3V)

Voltage on VDD with respect to VSS ......................................................................................................... -0.3V to +7.5V

Voltage on MCLR with respect to VSS (Note 2) ......................................................................................... 0V to +13.25V

Voltage on RA4 with respect to Vss............................................................................................................... 0V to +8.5V

Total power dissipation (Note 1) ...............................................................................................................................1.0W

Maximum current out of VSS pin ...........................................................................................................................300 mA

Maximum current into VDD pin ..............................................................................................................................250 mA

Input clamp current, IIK (VI < 0 or VI > VDD)...................................................................................................................... ±20 mA

Output clamp current, IOK (VO < 0 or VO > VDD) .............................................................................................................. ±20 mA

Maximum output current sunk by any I/O pin..........................................................................................................25 mA

Maximum output current sourced by any I/O pin ....................................................................................................25 mA

Maximum current sunk by PORTA, PORTB, and PORTE (Note 3) (combined)...................................................200 mA

Maximum current sourced by PORTA, PORTB, and PORTE (Note 3) (combined)..............................................200 mA

Maximum current sunk by PORTC and PORTD (Note 3) (combined)..................................................................200 mA

Maximum current sourced by PORTC and PORTD (Note 3) (combined).............................................................200 mA

Note 1: Power dissipation is calculated as follows:

Pdis = VDD x {IDD - ∑ IOH} + ∑ {(VDD-VOH) x IOH} + ∑(VOl x IOL)

2: Voltage spikes below VSS at the MCLR/VPP pin, inducing currents greater than 80 mA, may cause latchup.

Thus, a series resistor of 50-100Ω should be used when applying a “low” level to the MCLR/VPP pin, rather

than pulling this pin directly to VSS.

3: PORTD and PORTE not available on the PIC18F2X39 devices.

† NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the

device. This is a stress rating only and functional operation of the device at those or any other conditions above those

indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for

extended periods may affect device reliability.

 2002 Microchip Technology Inc.

Preliminary

DS30485A-page 259

PIC18FXX39

FIGURE 23-1:

PIC18FXX39 VOLTAGE-FREQUENCY GRAPH (INDUSTRIAL)

6.0V

5.5V

5.0V

4.5V

4.0V

PIC18FXX39

4.2V

3.5V

3.0V

2.5V

2.0V

40 MHz

Frequency

FIGURE 23-2:

PIC18LFXX39 VOLTAGE-FREQUENCY GRAPH (INDUSTRIAL)

6.0V

5.5V

5.0V

4.5V

4.0V

PIC18LFXX39

4.2V

3.5V

3.0V

2.5V

2.0V

40 MHz

4 MHz

Frequency

FMAX = (16.36 MHz/V) (VDDAPPMIN – 2.0V) + 4 MHz

Note: VDDAPPMIN is the minimum voltage of the PICmicro device in the application.

®

DS30485A-page 260

Preliminary

 2002 Microchip Technology Inc.

PIC18FXX39

23.1 DC Characteristics: PIC18FXX39 (Industrial, Extended)

PIC18LFXX39 (Industrial)

PIC18LFXX39

Standard Operating Conditions (unless otherwise stated)

Operating temperature -40°C ≤ TA ≤ +85°C for industrial

(Industrial)

Standard Operating Conditions (unless otherwise stated)

PIC18FXX39

Operating temperature

-40°C ≤ TA ≤ +85°C for industrial

-40°C ≤ TA ≤ +125°C for extended

(Industrial, Extended)

Param

No.

Symbol

Characteristic

Supply Voltage

Min

Typ Max Units

Conditions

VDD

D001

D002

PIC18LFXX39 2.0

PIC18FXX39 4.2

—

5.5

—

V

HS Osc mode

VDR

RAM Data Retention

1.5

—

(1)

Voltage

D003

D004

VPOR

VDD Start Voltage

—

0.7

—

V

See Section 3.1 (Power-on Reset) for details

to ensure internal

Power-on Reset signal

SVDD

VBOR

VDD Rise Rate

0.05

V/ms See Section 3.1 (Power-on Reset) for details

to ensure internal

Power-on Reset signal

Brown-out Reset Voltage

PIC18LFXX39

D005

BORV1:BORV0 = 11 1.98

BORV1:BORV0 = 10 2.67

BORV1:BORV0 = 01 4.16

BORV1:BORV0 = 00 4.45

PIC18FXX39

—

2.14

2.89

4.5

V

85°C ≥ T ≥ 25°C

4.83

BORV1:BORV0 = 1x N.A.

BORV1:BORV0 = 01 4.16

BORV1:BORV0 = 00 4.45

—

N.A.

4.5

4.83

V

Not in operating voltage range of device

Legend: Shading of rows is to assist in readability of the table.

Note 1: This is the limit to which VDD can be lowered in SLEEP mode, or during a device RESET, without losing RAM data.

2: The supply current is mainly a function of the operating voltage and frequency. Other factors, such as I/O pin

loading and switching rate, oscillator type, internal code execution pattern and temperature, also have an

impact on the current consumption.

The test conditions for all IDD measurements in active Operation mode are:

OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD

MCLR = VDD; WDT enabled/disabled as specified.

3: The power-down current in SLEEP mode does not depend on the oscillator type. Power-down current is

measured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD or VSS, and all

features that add delta current disabled (such as WDT, Timer1 Oscillator, BOR, etc.).

4: The LVD and BOR modules share a large portion of circuitry. The ∆IBOR and ∆ILVD currents are not additive.

Once one of these modules is enabled, the other may also be enabled without further penalty.

 2002 Microchip Technology Inc.

Preliminary

DS30485A-page 261

PIC18FXX39

23.1 DC Characteristics: PIC18FXX39 (Industrial, Extended)

PIC18LFXX39 (Industrial) (Continued)

PIC18LFXX39

Standard Operating Conditions (unless otherwise stated)

Operating temperature -40°C ≤ TA ≤ +85°C for industrial

(Industrial)

Standard Operating Conditions (unless otherwise stated)

PIC18FXX39

Operating temperature

-40°C ≤ TA ≤ +85°C for industrial

-40°C ≤ TA ≤ +125°C for extended

(Industrial, Extended)

Param

No.

Symbol

Characteristic

Min

Typ Max Units

Conditions

(2)

IDD

Supply Current

D010C

D013

PIC18LFXX39

EC, ECIO osc configurations

—

10

25

mA VDD = 4.2V, -40°C to +85°C

PIC18FXX39

PIC18LFXX39

EC, ECIO osc configurations

mA VDD = 4.2V, -40°C to +125°C

HS osc configuration

—

10

15

25

mA FOSC = 25 MHz, VDD = 5.5V

HS + PLL osc configurations

mA FOSC = 10 MHz, VDD = 5.5V

D013

D020

PIC18FXX39

HS osc configuration

—

10

15

25

mA FOSC = 25 MHz, VDD = 5.5V

HS + PLL osc configurations

mA FOSC = 10 MHz, VDD = 5.5V

(3)

IPD

Power-down Current

—

0.08 0.9

0.1

3

µA VDD = 2.0V, +25°C

µA VDD = 2.0V, -40°C to +85°C

µA VDD = 4.2V, -40°C to +85°C

PIC18LFXX39

4

10

D020

PIC18FXX39

—

.1

.9

10

25

µA VDD = 4.2V, +25°C

µA VDD = 4.2V, -40°C to +85°C

µA VDD = 4.2V, -40°C to +125°C

3

D021B

15

Legend: Shading of rows is to assist in readability of the table.

Note 1: This is the limit to which VDD can be lowered in SLEEP mode, or during a device RESET, without losing RAM data.

2: The supply current is mainly a function of the operating voltage and frequency. Other factors, such as I/O pin

loading and switching rate, oscillator type, internal code execution pattern and temperature, also have an

impact on the current consumption.

The test conditions for all IDD measurements in active Operation mode are:

OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD

MCLR = VDD; WDT enabled/disabled as specified.

3: The power-down current in SLEEP mode does not depend on the oscillator type. Power-down current is

measured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD or VSS, and all

features that add delta current disabled (such as WDT, Timer1 Oscillator, BOR, etc.).

4: The LVD and BOR modules share a large portion of circuitry. The ∆IBOR and ∆ILVD currents are not additive.

Once one of these modules is enabled, the other may also be enabled without further penalty.

DS30485A-page 262

Preliminary

 2002 Microchip Technology Inc.

PIC18FXX39

23.1 DC Characteristics: PIC18FXX39 (Industrial, Extended)

PIC18LFXX39 (Industrial) (Continued)

PIC18LFXX39

Standard Operating Conditions (unless otherwise stated)

Operating temperature -40°C ≤ TA ≤ +85°C for industrial

(Industrial)

Standard Operating Conditions (unless otherwise stated)

PIC18FXX39

Operating temperature

-40°C ≤ TA ≤ +85°C for industrial

-40°C ≤ TA ≤ +125°C for extended

(Industrial, Extended)

Param

No.

Symbol

Characteristic

Min

Typ Max Units

Conditions

Module Differential Current

D022

∆IWDT

Watchdog Timer

—

0.75 1.5

µA VDD = 2.0V, +25°C

PIC18LFXX39

2

8

µA VDD = 2.0V, -40°C to +85°C

µA VDD = 4.2V, -40°C to +85°C

10

25

Watchdog Timer

7

15

25

40

µA VDD = 4.2V, +25°C

µA VDD = 4.2V, -40°C to +85°C

µA VDD = 4.2V, -40°C to +125°C

µA VDD = 2.0V, +25°C

µA VDD = 2.0V, -40°C to +85°C

µA VDD = 4.2V, -40°C to +85°C

µA VDD = 4.2V, +25°C

µA VDD = 4.2V, -40°C to +85°C

µA VDD = 4.2V, -40°C to +125°C

µA VDD = 2.0V, +25°C

µA VDD = 2.0V, -40°C to +85°C

µA VDD = 4.2V, -40°C to +85°C

PIC18FXX39

10

25

(4)

D022A ∆IBOR

D022A

Brown-out Reset

29

33

35

45

50

PIC18LFXX39

(4)

Brown-out Reset

36

40

50

65

PIC18FXX39

(4)

D022B ∆ILVD

D022B

Low Voltage Detect

29

33

35

45

50

PIC18LFXX39

(4)

Low Voltage Detect

33

40

50

65

µA VDD = 4.2V, +25°C

µA VDD = 4.2V, -40°C to +85°C

µA VDD = 4.2V, -40°C to +125°C

PIC18FXX39

Legend: Shading of rows is to assist in readability of the table.

Note 1: This is the limit to which VDD can be lowered in SLEEP mode, or during a device RESET, without losing RAM data.

2: The supply current is mainly a function of the operating voltage and frequency. Other factors, such as I/O pin

loading and switching rate, oscillator type, internal code execution pattern and temperature, also have an

impact on the current consumption.

The test conditions for all IDD measurements in active Operation mode are:

OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD

MCLR = VDD; WDT enabled/disabled as specified.

3: The power-down current in SLEEP mode does not depend on the oscillator type. Power-down current is

measured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD or VSS, and all

features that add delta current disabled (such as WDT, Timer1 Oscillator, BOR, etc.).

4: The LVD and BOR modules share a large portion of circuitry. The ∆IBOR and ∆ILVD currents are not additive.

Once one of these modules is enabled, the other may also be enabled without further penalty.

 2002 Microchip Technology Inc.

Preliminary

DS30485A-page 263

PIC18FXX39

23.2 DC Characteristics: PIC18FXX39 (Industrial, Extended)

PIC18LFXX39 (Industrial)

Standard Operating Conditions (unless otherwise stated)

DC CHARACTERISTICS

Operating temperature -40°C ≤ TA ≤ +85°C for industrial

-40°C ≤ TA ≤ +125°C for extended

Param

Symbol

No.

Characteristic

Input Low Voltage

Min

Max

Units

Conditions

VIL

I/O ports:

D030

D030A

D031

with TTL buffer

Vss

—

Vss

0.15 VDD

0.8

0.2 VDD

0.3 VDD

V

VDD < 4.5V

4.5V ≤ VDD ≤ 5.5V

with Schmitt Trigger buffer

RC3 and RC4

D032

D032A

D033

MCLR

VSS

0.2 VDD

0.3 VDD

0.2 VDD

V

OSC1 (HS mode)

OSC1 (EC mode)

Input High Voltage

I/O ports:

VIH

D040

with TTL buffer

0.25 VDD +

0.8V

2.0

0.8 VDD

0.7 VDD

VDD

V

VDD < 4.5V

D040A

D041

4.5V ≤ VDD ≤ 5.5V

with Schmitt Trigger buffer

RC3 and RC4

VDD

D042

D042A

MCLR, OSC1 (EC mode)

OSC1 (HS mode)

Input Leakage Current

0.8 VDD

0.7 VDD

VDD

V

(1,2)

IIL

D060

I/O ports

.02

±1

µA VSS ≤ VPIN ≤ VDD,

Pin at hi-impedance

D061

D063

MCLR

OSC1

—

±1

µA Vss ≤ VPIN ≤ VDD

IPU

IPURB

Weak Pull-up Current

PORTB weak pull-up current

D070

50

450

µA VDD = 5V, VPIN = VSS

Note 1: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified

levels represent normal operating conditions. Higher leakage current may be measured at different input

voltages.

2: Negative current is defined as current sourced by the pin.

3: Parameter is characterized but not tested.

DS30485A-page 264

Preliminary

 2002 Microchip Technology Inc.

PIC18FXX39

23.2 DC Characteristics: PIC18FXX39 (Industrial, Extended)

PIC18LFXX39 (Industrial) (Continued)

Standard Operating Conditions (unless otherwise stated)

Operating temperature -40°C ≤ TA ≤ +85°C for industrial

-40°C ≤ TA ≤ +125°C for extended

DC CHARACTERISTICS

Param

Symbol

No.

Characteristic

Min

Max

Units

Conditions

VOL

VOH

VOD

Output Low Voltage

I/O ports

D080

—

0.6

V

IOL = 8.5 mA, VDD = 4.5V,

-40°C to +85°C

D080A

IOL = 7.0 mA, VDD = 4.5V,

-40°C to +125°C

(2)

Output High Voltage

I/O ports

D090

D090A

D150

VDD – 0.7

—

V

IOH = -3.0 mA, VDD = 4.5V,

-40°C to +85°C

IOH = -2.5 mA, VDD = 4.5V,

-40°C to +125°C

Open Drain High Voltage

8.5

RA4 pin

Capacitive Loading Specs

on Output Pins

COSC2 OSC2 pin

(3)

—

D100

D101

D102

15

50

pF In HS mode when external

clock is used to drive OSC1

CIO

All I/O pins

SCL, SDA

pF To meet the AC Timing

Specifications

2

CB

400

pF In I C mode

Note 1: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified

levels represent normal operating conditions. Higher leakage current may be measured at different input

voltages.

2: Negative current is defined as current sourced by the pin.

3: Parameter is characterized but not tested.

 2002 Microchip Technology Inc.

Preliminary

DS30485A-page 265

PIC18FXX39

FIGURE 23-3:

LOW VOLTAGE DETECT CHARACTERISTICS

VDD

(LVDIF can be

cleared in software)

VLVD

(LVDIF set by hardware)

37

LVDIF

TABLE 23-1: LOW VOLTAGE DETECT CHARACTERISTICS

Standard Operating Conditions (unless otherwise stated)

Operating temperature -40°C ≤ TA ≤ +85°C for industrial

-40°C ≤ TA ≤ +125°C for extended

Param

No.

Symbol

Characteristic

Min

Typ

Max

Units

Conditions

T ≥ 25°C

D420

VLVD

LVDVoltageonVDD LVV = 0001

1.98

2.18

2.37

2.48

2.67

2.77

2.98

3.27

3.47

3.57

3.76

3.96

4.16

4.45

2.06

2.27

2.47

2.58

2.78

2.89

3.1

3.41

3.61

3.72

3.92

4.13

4.33

4.64

2.14

2.36

2.57

2.68

2.89

3.01

3.22

3.55

3.75

3.87

4.08

4.3

V

transition high to

LVV = 0010

low

LVV = 0011

LVV = 0100

LVV = 0101

LVV = 0110

LVV = 0111

LVV = 1000

LVV = 1001

LVV = 1010

LVV = 1011

LVV = 1100

LVV = 1101

LVV = 1110

4.5

4.83

DS30485A-page 266

Preliminary

 2002 Microchip Technology Inc.

PIC18FXX39

TABLE 23-2: MEMORY PROGRAMMING REQUIREMENTS

Standard Operating Conditions (unless otherwise stated)

Operating temperature -40°C ≤ TA ≤ +85°C for industrial

-40°C ≤ TA ≤ +125°C for extended

DC Characteristics

Param

Sym

No.

Characteristic

Min

Typ†

Max Units

Conditions

Internal Program Memory

Programming Specifications

D110

D113

VPP

9.00

—

13.25

10

V

Voltage on MCLR/VPP pin

IDDP

mA

Supply Current during

Programming

Data EEPROM Memory

Cell Endurance

D121 VDRW VDD for Read/Write

1M

—

D120

ED

100K

VMIN

E/W -40°C to +85°C

5.5

V

Using EECON to read/write

VMIN = Minimum operating

voltage

—

D122 TDEW Erase/Write Cycle Time

D123 TRETD Characteristic Retention

4

—

ms

40

—

Year Provided no other

specifications are violated

100

1M

—

D123A TRETD Characteristic Retention

—

10M

Year 25°C (Note 1)

E/W -40°C to +85°C

D124

TREF

Number of Total Erase/Write

—

(2)

Cycles before Refresh

Program FLASH Memory

Cell Endurance

VDD for Read

—

D130

D131

EP

VPR

10K

VMIN

100K

—

E/W -40°C to +85°C

5.5

V

VMIN = Minimum operating

voltage

—

D132

D132A VIW

VIE

VDD for Block Erase

VDD for Externally Timed Erase

or Write

4.5

5.5

V

Using ICSP port

—

D132B VPEW VDD for Self-timed Write

VMIN

5.5

V

VMIN = Minimum operating

voltage

—

1

—

D133

D133A TIW

TIE

ICSP Block Erase Cycle Time

ICSP Erase or Write Cycle Time

(externally timed)

4

—

ms VDD ≥ 4.5V

—

D133A TIW

Self-timed Write Cycle Time

2

ms

D134 TRETD Characteristic Retention

40

—

Year Provided no other

specifications are violated

100

—

D134A TRETD Characteristic Retention

—

Year 25°C (Note 1)

† Data in “Typ” column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance

only and are not tested.

Note 1: Retention time is valid, provided no other specifications are violated.

2: Refer to Section 6.8 for a more detailed discussion on data EEPROM endurance.

 2002 Microchip Technology Inc.

Preliminary

DS30485A-page 267

PIC18FXX39

23.3 AC (Timing) Characteristics

23.3.1

TIMING PARAMETER SYMBOLOGY

The timing parameter symbols have been created

following one of the following formats:

2

1. TppS2ppS

2. TppS

T

3. TCC:ST

4. Ts

(I C specifications only)

2

(I C specifications only)

F

Frequency

T

Time

Lowercase letters (pp) and their meanings:

pp

cc

ck

cs

di

do

dt

CCP1

CLKO

CS

SDI

SDO

Data in

I/O port

MCLR

osc

rd

rw

sc

ss

t0

OSC1

RD

RD or WR

SCK

SS

T0CKI

T13CKI

WR

io

mc

t1

wr

Uppercase letters and their meanings:

S

F

H

I

Fall

High

P

R

V

Z

Period

Rise

Valid

Hi-impedance

Invalid (Hi-impedance)

Low

L

2

I C only

AA

BUF

output access

Bus free

High

Low

High

Low

2

TCC:ST (I C specifications only)

CC

HD

Hold

SU

Setup

ST

DAT

STA

DATA input hold

START condition

STO

STOP condition

DS30485A-page 268

Preliminary

 2002 Microchip Technology Inc.

PIC18FXX39

23.3.2

TIMING CONDITIONS

The temperature and voltages specified in Table 23-3

apply to all timing specifications unless otherwise

noted. Figure 23-4 specifies the load conditions for the

timing specifications.

TABLE 23-3: TEMPERATURE AND VOLTAGE SPECIFICATIONS - AC

Standard Operating Conditions (unless otherwise stated)

Operating temperature

-40°C ≤ TA ≤ +85°C for industrial

-40°C ≤ TA ≤ +125°C for extended

AC CHARACTERISTICS

Operating voltage VDD range as described in DC spec Section 23.1 and

Section 23.2.

LC parts operate for industrial temperatures only.

FIGURE 23-4:

LOAD CONDITIONS FOR DEVICE TIMING SPECIFICATIONS

Load condition 1 Load condition 2

VDD/2

CL

RL

VSS

CL

RL = 464Ω

CL = 50 pF for all pins except OSC2/CLKO

and including D and E outputs as ports

VSS

 2002 Microchip Technology Inc.

Preliminary

DS30485A-page 269

PIC18FXX39

23.3.3

TIMING DIAGRAMS AND SPECIFICATIONS

FIGURE 23-5:

EXTERNAL CLOCK TIMING (ALL MODES EXCEPT PLL)

Q4

Q1

Q2

Q3

Q4

Q1

OSC1

CLKO

1

3

4

3

4

2

TABLE 23-4: EXTERNAL CLOCK TIMING REQUIREMENTS

Param.

Symbol

Characteristic

Min

Max

Units

Conditions

No.

(1)

1A

FOSC

External CLKI Frequency

DC

4

40

25

MHz EC, ECIO, -40°C to +85°C

MHz EC, ECIO, +85°C to +125°C

MHz HS osc

(1)

Oscillator Frequency

4

10

6.25

MHz HS + PLL osc, -40°C to +85°C

MHz HS + PLL osc, +85°C to +125°C

(1)

1

TOSC

TCY

External CLKI Period

25

—

ns

EC, ECIO, -40°C to +85°C

(1)

Oscillator Period

40

100

160

—

ns

EC, ECIO, +85°C to +125°C

HS osc

HS + PLL osc, -40°C to +85°C

HS + PLL osc, +85°C to +125°C

250

(1)

2

Instruction Cycle Time

100

160

10

—

ns

TCY = 4/FOSC, -40°C to +85°C

TCY = 4/FOSC, +85°C to +125°C

HS osc

3

4

TosL,

TosH

TosR,

TosF

External Clock in (OSC1)

High or Low Time

External Clock in (OSC1)

—

7.5

ns

HS osc

Rise or Fall Time

Note 1: Instruction cycle period (TCY) equals four times the input oscillator time-base period for all configurations

except PLL. All specified values are based on characterization data for that particular oscillator type under

standard operating conditions with the device executing code. Exceeding these specified limits may result in

an unstable oscillator operation and/or higher than expected current consumption. All devices are tested to

operate at “min.” values with an external clock applied to the OSC1/CLKI pin. When an external clock input

is used, the “max.” cycle time limit is “DC” (no clock) for all devices.

TABLE 23-5: PLL CLOCK TIMING SPECIFICATIONS (VDD = 4.2 TO 5.5V)

Param

Sym

Characteristic

Min

Typ†

Max

Units Conditions

No.

—

FOSC Oscillator Frequency Range

FSYS On-Chip VCO System Frequency

4

—

10

40

2

MHz HS mode only

ms

%

16

—

-2

t

PLL Start-up Time (Lock Time)

rc

∆CLK CLKO Stability (Jitter)

+2

†

Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only

and are not tested.

DS30485A-page 270

Preliminary

 2002 Microchip Technology Inc.

PIC18FXX39

FIGURE 23-6:

CLKO AND I/O TIMING

Q1

Q2

Q3

Q4

OSC1

11

10

CLKO

13

14

12

16

19

18

I/O Pin

(input)

15

17

I/O Pin

New Value

Old Value

(output)

20, 21

Refer to Figure 23-4 for load conditions.

Note:

TABLE 23-6: CLKO AND I/O TIMING REQUIREMENTS

Param.

Symbol

Characteristic

Min

Typ

Max

Units Conditions

No.

10

11

12

13

14

15

16

17

18

18A

19

20

20A

21

21A

22††

23††

24††

TosH2ckL OSC1↑ to CLKO↓

TosH2ckH OSC1↑ to CLKO↑

—

75

35

—

50

—

10

—

10

—

200

100

ns (Note 1)

TckR

TckF

CLKO rise time

CLKO fall time

TckL2ioV CLKO↓ to Port out valid

0.5 TCY + 20 ns (Note 1)

TioV2ckH Port in valid before CLKO ↑

TckH2ioI Port in hold after CLKO ↑

TosH2ioV OSC1↑ (Q1 cycle) to Port out valid

0.25 TCY + 25

—

150

—

25

60

25

60

—

ns (Note 1)

ns

ns VDD = 2V

ns

ns VDD = 2V

ns

0

—

100

200

0

—

TosH2ioI OSC1↑ (Q2 cycle) to Port

PIC18FXXXX

PIC18LFXXXX

input invalid (I/O in hold time)

TioV2osH Port input valid to OSC1↑ (I/O in setup time)

TioR

Port output rise time

Port output fall time

INT pin high or low time

PIC18FXXXX

PIC18LFXXXX

PIC18FXXXX

PIC18LFXXXX

TioF

TINP

TCY

20

TRBP

TRCP

RB7:RB4 change INT high or low time

RC7:RC4 change INT high or low time

—

†† These parameters are asynchronous events not related to any internal clock edges.

Note 1: Measurements are taken in RC mode, where CLKO output is 4 x TOSC.

 2002 Microchip Technology Inc.

Preliminary

DS30485A-page 271

PIC18FXX39

FIGURE 23-7:

RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP

TIMER TIMING

VDD

MCLR

30

Internal

POR

33

PWRT

Time-out

32

OSC

Time-out

Internal

Reset

Watchdog

Timer

Reset

31

34

I/O Pins

Note:

Refer to Figure 23-4 for load conditions.

FIGURE 23-8:

BROWN-OUT RESET TIMING

BVDD

VDD

35

VBGAP = 1.2V

Typical

VIRVST

Enable Internal Reference Voltage

Internal Reference Voltage stable

36

TABLE 23-7: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER

AND BROWN-OUT RESET REQUIREMENTS

Param.

Symbol

Characteristic

Min

Typ

Max

Units

Conditions

No.

30

31

TmcL

TWDT

MCLR Pulse Width (low)

Watchdog Timer Time-out Period (No

Postscaler)

2

7

—

18

—

33

µs

ms

32

33

34

TOST

TPWRT

Oscillation Start-up Timer Period

Power up Timer Period

1024 TOSC

—

72

2

1024 TOSC

—

ms

µs

TOSC = OSC1 period

28

—

132

—

TIOZ

I/O high impedance from MCLR Low

or Watchdog Timer Reset

35

36

TBOR

TIVRST

Brown-out Reset Pulse Width

Time for Internal Reference

Voltage to become stable

200

—

20

—

500

µs

VDD ≤ BVDD (see D005)

VDD ≤ VLVD (see D420)

37

TLVD

Low Voltage Detect Pulse Width

200

—

µs

DS30485A-page 272

Preliminary

 2002 Microchip Technology Inc.

PIC18FXX39

FIGURE 23-9:

TIMER0 AND TIMER1 EXTERNAL CLOCK TIMINGS

T0CKI

41

46

40

45

42

47

T13CKI

48

TMR0 or

TMR1

Note:

Refer to Figure 23-4 for load conditions.

TABLE 23-8: TIMER0 AND TIMER1 EXTERNAL CLOCK REQUIREMENTS

Param

Symbol

Characteristic

T0CKI High Pulse Width

Min

Max Units

Conditions

No.

40

Tt0H

No Prescaler

With Prescaler

No Prescaler

With Prescaler

No Prescaler

With Prescaler

0.5TCY + 20

10

0.5TCY + 20

10

—

ns

41

42

Tt0L

Tt0P

T0CKI Low Pulse Width

T0CKI Period

TCY + 10

Greater of:

20 nS or TCY + 40

N

ns N = prescale

value

(1, 2, 4,..., 256)

45

46

Tt1H

Tt1L

T13CKI High

Time

Synchronous, no prescaler

0.5TCY + 20

—

ns

Synchronous,

with prescaler

PIC18FXXXX

PIC18LFXXXX

PIC18FXXXX

PIC18LFXXXX

10

25

30

50

Asynchronous

T13CKI Low

Time

Synchronous, no prescaler

0.5TCY + 5

Synchronous,

with prescaler

PIC18FXXXX

10

25

30

50

PIC18LFXXXX

PIC18FXXXX

PIC18LFXXXX

Asynchronous

47

48

Tt1P

Ft1

T13CKI input

period

Synchronous

Greater of:

20 nS or TCY + 40

N

ns N = prescale

value

(1, 2, 4, 8)

Asynchronous

60

DC

2 TOSC

—

50

7 TOSC

ns

kHz

—

T13CKI oscillator input frequency range

Tcke2tmrI Delay from external T13CKI clock edge to timer

increment

 2002 Microchip Technology Inc.

Preliminary

DS30485A-page 273

PIC18FXX39

FIGURE 23-10:

PWM TIMINGS (PWM1 AND PWM2)

PWMx Output

54

53

Note:

Refer to Figure 23-4 for load conditions.

TABLE 23-9: PWM TIMING REQUIREMENTS (PWM1 AND PWM2)

Param.

Symbol

Characteristic

Min

Max

Units

Conditions

No.

53

TccR

PWMx Output Rise Time

PWMx Output Fall Time

PIC18FXXXX

PIC18LFXXXX

PIC18FXXXX

PIC18LFXXXX

—

25

60

25

60

ns

VDD = 2V

54

TccF

DS30485A-page 274

Preliminary

 2002 Microchip Technology Inc.

PIC18FXX39

FIGURE 23-11:

PARALLEL SLAVE PORT TIMING (PIC18F4X39)

RE2/CS

RE0/RD

RE1/WR

65

RD7:RD0

62

64

63

Note:

Refer to Figure 23-4 for load conditions.

TABLE 23-10: PARALLEL SLAVE PORT REQUIREMENTS (PIC18F4X39)

Param.

Symbol

Characteristic

Min

Max Units

Conditions

No.

62

TdtV2wrH Data in valid before WR↑ or CS↑

20

25

—

ns

(setup time)

ns Extended Temp. Range

63

64

TwrH2dtI WR↑ or CS↑ to data–in invalid PIC18FXXXX

20

35

—

80

90

ns

(hold time)

PIC18LFXXXX

ns VDD = 2V

TrdL2dtV RD↓ and CS↓ to data–out valid

ns

ns Extended Temp. Range

65

66

TrdH2dtI RD↑ or CS↓ to data–out invalid

10

—

30

3 TCY

ns

TibfINH

Inhibit of the IBF flag bit being cleared from

WR↑ or CS↑

 2002 Microchip Technology Inc.

Preliminary

DS30485A-page 275

PIC18FXX39

FIGURE 23-12:

EXAMPLE SPI MASTER MODE TIMING (CKE = 0)

SS

70

SCK

(CKP = 0)

71

72

78

79

SCK

(CKP = 1)

78

80

bit6 - - - - - -1

bit6 - - - -1

MSb

LSb

SDO

SDI

75, 76

MSb In

74

LSb In

73

Note: Refer to Figure 23-4 for load conditions.

TABLE 23-11: EXAMPLE SPI MODE REQUIREMENTS (MASTER MODE, CKE = 0)

Param.

Symbol

Characteristic

Min

Max Units Conditions

No.

70

TssL2scH, SS↓ to SCK↓ or SCK↑ input

TssL2scL

TCY

—

ns

71

71A

72

72A

73

TscH

SCK input high time

(Slave mode)

Continuous

Single Byte

Continuous

Single Byte

1.25 TCY + 30

—

ns

40

1.25 TCY + 30

40

ns (Note 1)

ns

ns (Note 1)

ns

TscL

SCK input low time

(Slave mode)

TdiV2scH, Setup time of SDI data input to SCK edge

TdiV2scL

100

73A

74

TB2B

Last clock edge of Byte 1 to the 1st clock edge of Byte 2 1.5 TCY + 40

—

ns (Note 2)

ns

TscH2diL, Hold time of SDI data input to SCK edge

TscL2diL

100

75

76

78

79

80

TdoR

TdoF

TscR

TscF

SDO data output rise time

SDO data output fall time

PIC18FXXXX

PIC18LFXXXX

PIC18FXXXX

PIC18LFXXXX

PIC18FXXXX

PIC18LFXXXX

—

25

60

25

60

25

60

25

60

50

150

ns

ns VDD = 2V

ns

ns VDD = 2V

ns

ns VDD = 2V

ns

ns VDD = 2V

ns

SCK output rise time

(Master mode)

SCK output fall time (Master mode) PIC18FXXXX

PIC18LFXXXX

TscH2doV, SDO data output valid after SCK PIC18FXXXX

TscL2doV edge

PIC18LFXXXX

ns VDD = 2V

Note 1: Requires the use of Parameter # 73A.

2: Only if Parameter # 71A and # 72A are used.

DS30485A-page 276

Preliminary

 2002 Microchip Technology Inc.

PIC18FXX39

FIGURE 23-13:

EXAMPLE SPI MASTER MODE TIMING (CKE = 1)

SS

81

SCK

(CKP = 0)

71

72

79

78

73

SCK

(CKP = 1)

80

LSb

MSb

bit6 - - - - - -1

bit6 - - - -1

SDO

SDI

75, 76

MSb In

74

LSb In

Note: Refer to Figure 23-4 for load conditions.

TABLE 23-12: EXAMPLE SPI MODE REQUIREMENTS (MASTER MODE, CKE = 1)

Param.

Symbol

TscH

Characteristic

Min

Max Units Conditions

No.

71

71A

72

72A

73

SCK input high time

Continuous

Single Byte

Continuous

Single Byte

1.25 TCY + 30

—

ns

(Slave mode)

40

1.25 TCY + 30

40

ns (Note 1)

ns

ns (Note 1)

ns

TscL

SCK input low time

(Slave mode)

TdiV2scH, Setup time of SDI data input to SCK edge

TdiV2scL

100

73A

74

TB2B

Last clock edge of Byte 1 to the 1st clock edge of Byte 2 1.5 TCY + 40

—

ns (Note 2)

ns

TscH2diL, Hold time of SDI data input to SCK edge

TscL2diL

100

75

76

78

79

80

81

TdoR

TdoF

TscR

TscF

SDO data output rise time

SDO data output fall time

PIC18FXXXX

PIC18LFXXXX

PIC18FXXXX

PIC18LFXXXX

—

TCY

25

60

25

60

25

60

25

60

50

150

—

ns

ns VDD = 2V

ns

ns VDD = 2V

ns

ns VDD = 2V

ns

ns VDD = 2V

ns

SCK output rise time (Master mode) PIC18FXXXX

PIC18LFXXXX

SCK output fall time (Master mode) PIC18FXXXX

PIC18LFXXXX

TscH2doV, SDO data output valid after SCK

TscL2doV edge

PIC18FXXXX

PIC18LFXXXX

ns VDD = 2V

ns

TdoV2scH, SDO data output setup to SCK edge

TdoV2scL

Note 1: Requires the use of Parameter # 73A.

2: Only if Parameter # 71A and # 72A are used.

 2002 Microchip Technology Inc.

Preliminary

DS30485A-page 277

PIC18FXX39

FIGURE 23-14:

EXAMPLE SPI SLAVE MODE TIMING (CKE = 0)

SS

70

SCK

83

(CKP = 0)

71

72

78

79

SCK

(CKP = 1)

78

80

MSb

LSb

SDO

SDI

bit6 - - - - - -1

bit6 - - - -1

77

75, 76

MSb In

74

LSb In

73

Note:

Refer to Figure 23-4 for load conditions.

TABLE 23-13: EXAMPLE SPI MODE REQUIREMENTS (SLAVE MODE TIMING (CKE = 0))

Param. No. Symbol

Characteristic

Min

Max Units Conditions

70

TssL2scH, SS↓ to SCK↓ or SCK↑ input

TCY

—

ns

TssL2scL

TscH

71

71A

72

72A

73

SCK input high time (Slave mode)

SCK input low time (Slave mode)

Continuous

Single Byte

Continuous

Single Byte

1.25 TCY + 30

—

ns

40

1.25 TCY + 30

40

ns (Note 1)

ns

ns (Note 1)

ns

TscL

TdiV2scH, Setup time of SDI data input to SCK edge

100

TdiV2scL

73A

74

TB2B

Last clock edge of Byte 1 to the first clock edge of Byte 2 1.5 TCY + 40

—

ns (Note 2)

ns

TscH2diL, Hold time of SDI data input to SCK edge

100

TscL2diL

75

76

TdoR

TdoF

SDO data output rise time

SDO data output fall time

PIC18FXXXX

PIC18LFXXXX

PIC18FXXXX

PIC18LFXXXX

—

25

60

25

60

ns

VDD = 2V

77

78

TssH2doZ SS↑ to SDO output hi-impedance

10

—

50

25

60

25

60

50

150

—

ns

TscR

SCK output rise time (Master mode)

PIC18FXXXX

PIC18LFXXXX

PIC18FXXXX

PIC18LFXXXX

VDD = 2V

79

80

83

TscF

SCK output fall time (Master mode)

TscH2doV, SDO data output valid after SCK edge PIC18FXXXX

TscL2doV

PIC18LFXXXX

TscH2ssH, SS ↑ after SCK edge

1.5 TCY + 40

ns

TscL2ssH

Note 1: Requires the use of Parameter # 73A.

2: Only if Parameter # 71A and # 72A are used.

DS30485A-page 278

Preliminary

 2002 Microchip Technology Inc.

PIC18FXX39

FIGURE 23-15:

EXAMPLE SPI SLAVE MODE TIMING (CKE = 1)

82

SS

70

SCK

83

(CKP = 0)

71

72

SCK

(CKP = 1)

80

MSb

bit6 - - - - - -1

bit6 - - - -1

LSb

SDO

SDI

75, 76

77

MSb In

74

LSb In

Note: Refer to Figure 23-4 for load conditions.

TABLE 23-14: EXAMPLE SPI SLAVE MODE REQUIREMENTS (CKE = 1)

Param. No.

70

Symbol

Characteristic

Min

Max Units Conditions

TssL2scH, SS↓ to SCK↓ or SCK↑ input

TssL2scL

TCY

—

ns

71

71A

72

72A

73A

74

TscH

TscL

TB2B

SCK input high time

(Slave mode)

Continuous

Single Byte

Continuous

Single Byte

1.25 TCY + 30

—

ns

40

1.25 TCY + 30

40

ns (Note 1)

ns

ns (Note 1)

ns (Note 2)

ns

SCK input low time

(Slave mode)

Last clock edge of Byte 1 to the first clock edge of Byte 2 1.5 TCY + 40

TscH2diL, Hold time of SDI data input to SCK edge

TscL2diL

100

75

76

TdoR

SDO data output rise time

PIC18FXXXX

PIC18LFXXXX

PIC18FXXXX

PIC18LFXXXX

—

25

60

25

60

ns

VDD = 2V

TdoF

SDO data output fall time

77

78

TssH2doZ SS↑ to SDO output hi-impedance

10

—

50

25

60

25

60

ns

TscR

SCK output rise time (Master mode) PIC18FXXXX

PIC18LFXXXX

VDD = 2V

79

80

82

83

TscF

SCK output fall time (Master mode)

PIC18FXXXX

PIC18LFXXXX

PIC18FXXXX

PIC18LFXXXX

TscH2doV, SDO data output valid after SCK

TscL2doV edge

50

150

TssL2doV SDO data output valid after SS↓ edge PIC18FXXXX

PIC18LFXXXX

—

50

150

ns

TscH2ssH, SS ↑ after SCK edge

TscL2ssH

1.5 TCY + 40

—

ns

Note 1: Requires the use of Parameter # 73A.

2: Only if Parameter # 71A and # 72A are used.

 2002 Microchip Technology Inc.

Preliminary

DS30485A-page 279

PIC18FXX39

FIGURE 23-16:

I²C BUS START/STOP BITS TIMING

SCL

SDA

91

93

90

92

STOP

Condition

START

Condition

Note: Refer to Figure 23-4 for load conditions.

TABLE 23-15: I²C BUS START/STOP BITS REQUIREMENTS (SLAVE MODE)

Param.

Symbol

Characteristic

Min

Max

Units

Conditions

No.

90

TSU:STA START condition

Setup time

THD:STA START condition

Hold time

TSU:STO STOP condition

Setup time

THD:STO STOP condition

Hold time

100 kHz mode

400 kHz mode

100 kHz mode

400 kHz mode

100 kHz mode

400 kHz mode

100 kHz mode

400 kHz mode

4700

600

4000

600

4700

600

4000

600

—

ns

Only relevant for Repeated

START condition

91

92

93

ns

After this period, the first

clock pulse is generated

FIGURE 23-17:

I²C BUS DATA TIMING

103

102

100

101

109

SCL

90

106

107

91

92

SDA

In

110

109

SDA

Out

Note: Refer to Figure 23-4 for load conditions.

DS30485A-page 280

Preliminary

 2002 Microchip Technology Inc.

PIC18FXX39

TABLE 23-16: I²C BUS DATA REQUIREMENTS (SLAVE MODE)

Param.

Symbol

Characteristic

100 kHz mode

Min

Max

Units

Conditions

No.

Clock high time

4.0

—

µs

PIC18FXXX must operate at a

minimum of 1.5 MHz

PIC18FXXX must operate at a

minimum of 10 MHz

100

THIGH

400 kHz mode

0.6

—

SSP Module

100 kHz mode

1.5 TCY

4.7

—

Clock low time

µs

PIC18FXXX must operate at a

minimum of 1.5 MHz

PIC18FXXX must operate at a

minimum of 10 MHz

101

102

TLOW

TR

400 kHz mode

1.3

—

SSP Module

100 kHz mode

400 kHz mode

1.5 TCY

—

20 + 0.1 CB

—

1000

300

SDA and SCL rise

time

ns

CB is specified to be from

10 to 400 pF

SDA and SCL fall

time

100 kHz mode

400 kHz mode

100 kHz mode

400 kHz mode

—

1000

300

—

0.9

—

3500

—

ns

µs

ns

µs

ns

µs

ns

µs

VDD ≥ 4.2V

Only relevant for Repeated

START condition

103

90

TF

20 + 0.1 CB

START condition

setup time

4.7

0.6

4.0

0.6

0

TSU:STA

THD:STA

THD:DAT

TSU:DAT

TSU:STO

TAA

START condition hold 100 kHz mode

time

After this period, the first clock

pulse is generated

91

400 kHz mode

100 kHz mode

400 kHz mode

Data input hold time

106

107

92

0

Data input setup time 100 kHz mode

400 kHz mode

STOP condition

setup time

250

100

4.7

0.6

—

4.7

1.3

(Note 2)

100 kHz mode

400 kHz mode

100 kHz mode

400 kHz mode

100 kHz mode

400 kHz mode

Output valid from

clock

(Note 1)

109

110

Bus free time

Time the bus must be free

before a new transmission can

start

TBUF

—

CB

Bus capacitive loading

—

400

pF

D102

Note 1: As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region (min. 300 ns) of

the falling edge of SCL to avoid unintended generation of START or STOP conditions.

2

2: A Fast mode I C bus device can be used in a Standard mode I C bus system, but the requirement TSU:DAT ≥ 250 ns

must then be met. This will automatically be the case if the device does not stretch the LOW period of the SCL signal. If

such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line.

2

TR max. + TSU:DAT = 1000 + 250 = 1250 ns (according to the Standard mode I C bus specification) before the SCL line is

released.

 2002 Microchip Technology Inc.

Preliminary

DS30485A-page 281

PIC18FXX39

FIGURE 23-18:

MASTER SSP I²C BUS START/STOP BITS TIMING WAVEFORMS

SCL

SDA

93

91

90

92

STOP

Condition

START

Condition

Note: Refer to Figure 23-4 for load conditions.

TABLE 23-17: MASTER SSP I²C BUS START/STOP BITS REQUIREMENTS

Param.

Symbol

Characteristic

Min

Max Units

Conditions

No.

90

TSU:STA START condition

Setup time

100 kHz mode

400 kHz mode

1 MHz mode

2(TOSC)(BRG + 1)

—

ns Only relevant for

Repeated START

condition

(1)

91

92

93

THD:STA START condition

Hold time

100 kHz mode

400 kHz mode

ns After this period, the

first clock pulse is

generated

(1)

1 MHz mode

TSU:STO STOP condition

Setup time

100 kHz mode

400 kHz mode

ns

(1)

1 MHz mode

THD:STO STOP condition

Hold time

100 kHz mode

400 kHz mode

ns

(1)

1 MHz mode

2

Note 1: Maximum pin capacitance = 10 pF for all I C pins.

FIGURE 23-19:

MASTER SSP I²C BUS DATA TIMING

103

102

100

101

SCL

90

106

91

92

107

SDA

In

110

109

SDA

Out

Note: Refer to Figure 23-4 for load conditions.

DS30485A-page 282

Preliminary

 2002 Microchip Technology Inc.

PIC18FXX39

TABLE 23-18: MASTER SSP I²C BUS DATA REQUIREMENTS

Param.

Symbol

Characteristic

Min

Max Units

Conditions

No.

100

THIGH

Clock high time 100 kHz mode

400 kHz mode

2(TOSC)(BRG + 1)

—

ms

ns

(1)

1 MHz mode

101

102

TLOW

TR

Clock low time

100 kHz mode

400 kHz mode

1 MHz mode

2(TOSC)(BRG + 1)

(1)

—

SDA and SCL

rise time

100 kHz mode

400 kHz mode

—

1000

300

1000

300

—

CB is specified to be from

10 to 400 pF

20 + 0.1 CB

(1)

1 MHz mode

—

103

90

TF

SDA and SCL

fall time

100 kHz mode

400 kHz mode

—

VDD ≥ 4.2V

20 + 0.1 CB

2(TOSC)(BRG + 1)

TSU:STA START condition 100 kHz mode

ms Only relevant for

setup time

Repeated START

condition

400 kHz mode

—

ms

(1)

1 MHz mode

—

ms

91

THD:STA START condition 100 kHz mode

2(TOSC)(BRG + 1)

—

0.9

—

ms After this period, the first

hold time

clock pulse is generated

400 kHz mode

ms

ns

(1)

1 MHz mode

106

107

92

THD:DAT Data input

hold time

100 kHz mode

400 kHz mode

100 kHz mode

400 kHz mode

0

250

100

ms

ns

TSU:DAT Data input

setup time

(Note 2)

ns

TSU:STO STOP condition 100 kHz mode

2(TOSC)(BRG + 1)

ms

ns

setup time

400 kHz mode

1 MHz mode

(1)

—

109

TAA

Output validfrom 100 kHz mode

—

3500

1000

—

clock

400 kHz mode

(1)

1 MHz mode

110

TBUF

CB

Bus free time

100 kHz mode

400 kHz mode

4.7

1.3

—

ms Time the bus must be free

ms

before a new transmission

can start

D102

Bus capacitive loading

—

400

pF

2

Note 1: Maximum pin capacitance = 10 pF for all I C pins.

2

2: A Fast mode I C bus device can be used in a Standard mode I C bus system, but parameter #107 ≥ 250 ns

must then be met. This will automatically be the case if the device does not stretch the LOW period of the SCL

signal. If such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the

SDA line, parameter #102 + parameter #107 = 1000 + 250 = 1250 ns (for 100 kHz mode) before the SCL line

is released.

 2002 Microchip Technology Inc.

Preliminary

DS30485A-page 283

PIC18FXX39

FIGURE 23-20:

USART SYNCHRONOUS TRANSMISSION (MASTER/SLAVE) TIMING

RC6/TX/CK

121

RC7/RX/DT

120

Note: Refer to Figure 23-4 for load conditions.

122

TABLE 23-19: USART SYNCHRONOUS TRANSMISSION REQUIREMENTS

Param.

Symbol

Characteristic

Min

Max

Units Conditions

No.

120

TckH2dtV SYNC XMIT (MASTER & SLAVE)

Clock high to data out valid

PIC18FXXXX

PIC18LFXXXX

PIC18FXXXX

PIC18LFXXXX

PIC18FXXXX

PIC18LFXXXX

—

50

150

25

ns

ns VDD = 2V

ns

ns VDD = 2V

ns

121

122

Tckr

Tdtr

Clock out rise time and fall time

(Master mode)

60

25

60

Data out rise time and fall time

ns VDD = 2V

FIGURE 23-21:

USART SYNCHRONOUS RECEIVE (MASTER/SLAVE) TIMING

RC6/TX/CK

125

RC7/RX/DT

126

Note: Refer to Figure 23-4 for load conditions.

TABLE 23-20: USART SYNCHRONOUS RECEIVE REQUIREMENTS

Param.

Symbol

Characteristic

Min

Max Units Conditions

No.

125

TdtV2ckl SYNC RCV (MASTER & SLAVE)

Data hold before CK ↓ (DT hold time)

10

15

20

—

ns

126

TckL2dtl Data hold after CK ↓ (DT hold time)

PIC18FXXXX

PIC18LFXXXX

VDD = 2V

DS30485A-page 284

Preliminary

 2002 Microchip Technology Inc.

PIC18FXX39

TABLE 23-21: A/D CONVERTER CHARACTERISTICS: PIC18FXX39 (INDUSTRIAL, EXTENDED)

PIC18LFXX39 (INDUSTRIAL)

Param

Symbol

Characteristic

Resolution

Integral linearity error

Differential linearity error

Gain error

Min

Typ

Max

Units

Conditions

No.

A01

NR

EIL

EDL

EG

EOFF

—

10

<±1

<±1.5

bit

A03

A04

A05

A06

A10

LSb VREF = VDD = 5.0V

Offset error

(2)

—

Monotonicity

guaranteed

—

VSS ≤ VAIN ≤ VREF

A20

A20A

VREF

Reference Voltage

(VREFH – VREFL)

1.8V

3V

—

V

VDD < 3.0V

VDD ≥ 3.0V

A21

A22

A25

A30

VREFH

VREFL

VAIN

Reference voltage High

Reference voltage Low

Analog input voltage

Recommended impedance of

analog voltage source

AVSS

—

AVDD + 0.3V

VREFH

AVDD + 0.3V

2.5

V

AVSS – 0.3V

—

VDD ≥ 2.5V (Note 3)

ZAIN

kΩ (Note 4)

A50

IREF

VREF input current (Note 1)

—

5

150

µA During VAIN acquisition

µA During A/D conversion cycle

Note 1: Vss ≤ VAIN ≤ VREF

2: The A/D conversion result never decreases with an increase in the Input Voltage, and has no missing codes.

3: For VDD < 2.5V, VAIN should be limited to < .5 VDD.

4: Maximum allowed impedance for analog voltage source is 10 kΩ. This requires higher acquisition times.

FIGURE 23-22:

A/D CONVERSION TIMING

BSF ADCON0, GO

(Note 2)

131

130

Q4

132

A/D CLK

. . .

9

8

7

2

1

0

A/D DATA

ADRES

NEW_DATA

TCY

OLD_DATA

ADIF

GO

DONE

SAMPLING STOPPED

SAMPLE

Note 1: If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts.

This allows the SLEEPinstruction to be executed.

2: This is a minimal RC delay (typically 100 ns), which also disconnects the holding capacitor from the analog input.

 2002 Microchip Technology Inc.

Preliminary

DS30485A-page 285

PIC18FXX39

TABLE 23-22: A/D CONVERSION REQUIREMENTS

Param

Symbol

Characteristic

Min

Max

Units

Conditions

No.

130

(4)

TAD

A/D clock period

PIC18FXXXX

PIC18LFXXXX

1.6

2.0

11

20

µs TOSC based

µs A/D RC mode

TAD

6.0

12

131

132

135

TCNV

TACQ

TSWC

Conversion time

(not including acquisition time) (Note 1)

Acquisition time (Note 2)

5

10

—

(Note 3)

µs VREF = VDD = 5.0V

µs VREF = VDD = 2.5V

Switching Time from convert → sample

Note 1: ADRES register may be read on the following TCY cycle.

2: The time for the holding capacitor to acquire the “New” input voltage, when the new input value has not

changed by more than 1 LSB from the last sampled voltage. The source impedance (RS) on the input channels

is 50Ω. See Section 18.0 for more information on acquisition time consideration.

3: On the next Q4 cycle of the device clock.

4: The time of the A/D clock period is dependent on the device frequency and the TAD clock divider.

DS30485A-page 286

Preliminary

 2002 Microchip Technology Inc.

PIC18FXX39

24.0 DC AND AC CHARACTERISTICS GRAPHS AND TABLES

Note: The graphs and tables provided following this note are a statistical summary based on a limited number of

samples and are provided for informational purposes only. The performance characteristics listed herein are

not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified

operating range (e.g., outside specified power supply range) and therefore, outside the warranted range.

“Typical” represents the mean of the distribution at 25°C. “Maximum” or “minimum” represents (mean + 3σ) or (mean - 3σ)

respectively, where σ is a standard deviation, over the whole temperature range.

FIGURE 24-1:

TYPICAL IDD vs. FOSC OVER VDD (HS MODE)

12

Typical:

statistical mean @ 25°C

5.5V

5.0V

4.5V

Maximum: mean + 3σ (-40°C to 125°C)

Minimum: mean – 3σ (-40°C to 125°C)

10

8

4.0V

3.5V

6

4

3.0V

2

2.5V

2.0V

0

4

6

8

10

12

14

16

18

20

22

24

26

FOSC (MHz)

FIGURE 24-2:

MAXIMUM IDD vs. FOSC OVER VDD (HS MODE)

12

5.5V

Typical:

statistical mean @ 25°C

5.0V

Maximum: mean + 3σ (-40°C to 125°C)

Minimum: mean – 3σ (-40°C to 125°C)

10

8

4.5V

4.0V

3.5V

6

3.0V

4

2.5V

2

2.0V

0

4

6

8

10

12

14

16

18

20

22

24

26

FOSC (MHz)

 2002 Microchip Technology Inc.

Preliminary

DS30485A-page 287

PIC18FXX39

FIGURE 24-3:

TYPICAL IDD vs. FOSC OVER VDD (HS/PLL MODE)

20

18

16

14

12

10

8

Typical:

statistical mean @ 25°C

Maximum: mean + 3σ (-40°C to 125°C)

Minimum: mean – 3σ (-40°C to 125°C)

5.5V

5.0V

4.5V

4.2V

6

4

2

0

4

5

6

7

8

9

10

FOSC (MHz)

FIGURE 24-4:

MAXIMUM IDD vs. FOSC OVER VDD (HS/PLL MODE)

20

18

16

14

12

10

8

Typical:

statistical mean @ 25°C

Maximum: mean + 3σ (-40°C to 125°C)

Minimum: mean – 3σ (-40°C to 125°C)

5.5V

5.0V

4.5V

4.2V

6

4

2

0

4

5

6

7

8

9

10

FOSC (MHz)

DS30485A-page 288

Preliminary

 2002 Microchip Technology Inc.

PIC18FXX39

FIGURE 24-5:

TYPICAL IDD vs. FOSC OVER VDD (EC MODE)

16

Typical:

statistical mean @ 25°C

5.5V

5.0V

Maximum: mean + 3σ (-40°C to 125°C)

Minimum: mean – 3σ (-40°C to 125°C)

14

12

10

8

4.5V

4.2V

4.0V

6

3.5V

4

3.0V

2

2.5V

2.0V

0

4

8

12

16

20

24

28

32

36

40

FOSC (MHz)

FIGURE 24-6:

MAXIMUM IDD vs. FOSC OVER VDD (EC MODE)

16

Typical:

statistical mean @ 25°C

5.5V

5.0V

Maximum: mean + 3σ (-40°C to 125°C)

Minimum: mean – 3σ (-40°C to 125°C)

14

12

10

8

4.5V

4.2V

4.0V

3.5V

6

4

3.0V

2

2.5V

2.0V

0

4

8

12

16

20

24

28

32

36

40

FOSC (MHz)

 2002 Microchip Technology Inc.

Preliminary

DS30485A-page 289

PIC18FXX39

FIGURE 24-7:

IPD vs. VDD, -40°C TO +125°C (SLEEP MODE, ALL PERIPHERALS DISABLED)

100

Max

(-40°C to +125°C)

10

1

Max

(+85°C)

Typ (+25°C)

0.1

Typical:

statistical mean @ 25°C

Maximum: mean + 3σ (-40°C to 125°C)

Minimum: mean – 3σ (-40°C to 125°C)

0.01

2.0

2.5

3.0

3.5

4.0

4.5

5.0

5.5

VDD (V)

FIGURE 24-8:

∆IBOR vs. VDD OVER TEMPERATURE (BOR ENABLED, VBOR = 2.00 - 2.16V)

90

80

70

60

50

40

30

20

10

Max (+125°C)

Max (125C)

Device

Held in

RESET

Reset

Max (+85°C)

Max (85C)

TTypyp(+(2255C°C) )

Device

in

SLEEP

Sleep

0

2.0

2.5

3.0

3.5

4.0

4.5

5.0

5.5

VDD (V)

DS30485A-page 290

Preliminary

 2002 Microchip Technology Inc.

PIC18FXX39

FIGURE 24-9:

TYPICAL AND MAXIMUM ∆IWDT vs. VDD OVER TEMPERATURE (WDT ENABLED)

70

Typical:

statistical mean @ 25°C

Maximum: mean + 3σ (-40°C to 125°C)

Minimum: mean – 3σ (-40°C to 125°C)

60

50

40

30

20

10

0

Max (+125°C)

Max (125C)

Max (+85°C)

Max (85C)

Typ (+25°C)

Typ (25C)

2.0

2.5

3.0

3.5

4.0

4.5

5.0

5.5

VDD (V)

FIGURE 24-10:

TYPICAL, MINIMUM AND MAXIMUM WDT PERIOD vs. VDD (-40°C TO +125°C)

50

Typical:

statistical mean @ 25°C

45

40

35

30

25

20

15

10

5

Maximum: mean + 3σ (-40°C to 125°C)

Minimum: mean – 3σ (-40°C to 125°C)

Max

(+125°C)

(125C)

Max

MAX

(+85°C)

(85C)

Typ

(+25°C)

(25C)

Min

(-40°C)

(-40C)

0

2.0

2.5

3.0

3.5

4.0

4.5

5.0

5.5

VDD (V)

 2002 Microchip Technology Inc.

Preliminary

DS30485A-page 291

PIC18FXX39

FIGURE 24-11:

∆ILVD vs. VDD OVER TEMPERATURE (LVD ENABLED, VLVD = 4.5 - 4.78V)

90

Typical:

statistical mean @ 25°C

Maximum: mean + 3σ (-40°C to 125°C)

Minimum: mean – 3σ (-40°C to 125°C)

80

70

60

50

40

30

20

10

0

Max (+125°C)

Max (125C)

Max (+125°C)

Max (125C)

Typ (+25°C)

Typ (25C)

TTyypp((+2255C°)C)

LVDIF can be

cleared by

firmware

LVDIF state

is unknown

LVDIF is set

by hardware

2.0

2.5

3.0

3.5

4.0

4.5

5.0

5.5

VDD (V)

FIGURE 24-12:

TYPICAL, MINIMUM AND MAXIMUM VOH vs. IOH (VDD = 5V, -40°C TO +125°C)

5.5

5.0

4.5

4.0

3.5

3.0

2.5

2.0

1.5

1.0

0.5

Max

Typ (+25°C)

Typ (25C)

MMiinn

0.0

0

5

10

15

20

25

IOH (-mA)

DS30485A-page 292

Preliminary

 2002 Microchip Technology Inc.

PIC18FXX39

FIGURE 24-13:

TYPICAL, MINIMUM AND MAXIMUM VOH vs. IOH (VDD = 3V, -40°C TO +125°C)

3.0

2.5

2.0

1.5

1.0

0.5

Max

Typ (+25°C)

Typ (25C)

Min

0.0

0

5

10

15

20

25

IOH (-mA)

FIGURE 24-14:

TYPICAL AND MAXIMUM VOL vs. IOL (VDD = 5V, -40°C TO +125°C)

1.8

1.6

Typical:

statistical mean @ 25°C

Maximum: mean + 3σ (-40°C to 125°C)

1.4

1.2

1.0

0.8

0.6

0.4

0.2

0.0

Minimum: mean – 3σ (-40°C to 125°C)

Max

Typ (+25°C)

Typ (25C)

0

5

10

15

20

25

IOL (-mA)

 2002 Microchip Technology Inc.

Preliminary

DS30485A-page 293

PIC18FXX39

FIGURE 24-15:

TYPICAL AND MAXIMUM VOL vs. IOL (VDD = 3V, -40°C TO +125°C)

2.5

Typical:

statistical mean @ 25°C

Maximum: mean + 3σ (-40°C to 125°C)

Minimum: mean – 3σ (-40°C to 125°C)

2.0

1.5

1.0

0.5

0.0

Max

Typ (+25°C)

Typ (25C)

0

5

10

15

20

25

IOL (-mA)

FIGURE 24-16:

MINIMUM AND MAXIMUM VIN vs. VDD (ST INPUT, -40°C TO +125°C)

4.0

Typical:

statistical mean @ 25°C

VIH Max

Maximum: mean + 3σ (-40°C to 125°C)

Minimum: mean – 3σ (-40°C to 125°C)

3.5

3.0

2.5

2.0

1.5

1.0

0.5

0.0

VIH Min

VIL Max

VIL Min

2.0

2.5

3.0

3.5

4.0

4.5

5.0

5.5

VDD (V)

DS30485A-page 294

Preliminary

 2002 Microchip Technology Inc.

PIC18FXX39

FIGURE 24-17:

MINIMUM AND MAXIMUM VIN vs. VDD (TTL INPUT, -40°C TO +125°C)

1.6

Typical:

statistical mean @ 25°C

Maximum: mean + 3σ (-40°C to 125°C)

Minimum: mean – 3σ (-40°C to 125°C)

1.4

1.2

1.0

0.8

0.6

0.4

0.2

0.0

VTH (Max)

VTH (Min)

2.0

2.5

3.0

3.5

4.0

4.5

5.0

5.5

VDD (V)

FIGURE 24-18:

MINIMUM AND MAXIMUM VIN vs. VDD (I²C INPUT, -40°C TO +125°C)

3.5

VIH Max

Typical:

statistical mean @ 25°C

Maximum: mean + 3σ (-40°C to 125°C)

Minimum: mean – 3σ (-40°C to 125°C)

3.0

2.5

2.0

1.5

1.0

0.5

0.0

VILMax

VIH Min

VIL Min

2.0

2.5

3.0

3.5

4.0

4.5

5.0

5.5

VDD (V)

 2002 Microchip Technology Inc.

Preliminary

DS30485A-page 295

PIC18FXX39

FIGURE 24-19:

A/D NON-LINEARITY vs. VREFH (VDD = VREFH, -40°C TO +125°C)

4

3.5

3

-40°C

-40C

+25°C

25C

2.5

2

+85°C

85C

1.5

1

0.5

0

+125°C

125C

2

2.5

3

3.5

4

4.5

5

5.5

VDD and VREFH (V)

FIGURE 24-20:

A/D NON-LINEARITY vs. VREFH (VDD = 5V, -40°C TO +125°C)

3

2.5

2

1.5

1

Max (-40°C to +125°C)

Max (-40C to 125C)

TTyypp((+2255C°)C)

0.5

0

2

2.5

3

3.5

4

4.5

5

5.5

VREFH (V)

DS30485A-page 296

Preliminary

 2002 Microchip Technology Inc.

PIC18FXX39

25.0 PACKAGING INFORMATION

25.1 Package Marking Information

28-Lead PDIP (Skinny DIP)

Example

XXXXXXXXXXXXXXXXX

YYWWNNN

PIC18F2439-I/SP

0217017

28-Lead SOIC

XXXXXXXXXXXXXXXXX

PIC18F2439-E/SO

YYWWNNN

0210017

Legend: XX...X Customer specific information*

Y

Year code (last digit of calendar year)

YY

Year code (last 2 digits of calendar year)

Week code (week of January 1 is week ‘01’)

Alphanumeric traceability code

WW

NNN

Note: In the event the full Microchip part number cannot be marked on one line, it will

be carried over to the next line thus limiting the number of available characters

for customer specific information.

*

Standard PICmicro device marking consists of Microchip part number, year code, week code, and

traceability code. For PICmicro device marking beyond this, certain price adders apply. Please check

with your Microchip Sales Office. For QTP devices, any special marking adders are included in QTP

price.

 2002 Microchip Technology Inc.

Preliminary

DS30485A-page 297

PIC18FXX39

Package Marking Information (Cont’d)

40-Lead PDIP

Example

XXXXXXXXXXXXXXXXXX

PIC18F4439-I/P

0212017

YYWWNNN

44-Lead TQFP

Example

PIC18F4539

-E/PT

XXXXXXXXXX

YYWWNNN

0220017

44-Lead QFN

XXXXXXXXXX

Example

PIC18F4439

-I/ML

XXXXXXXXXX

YYWWNNN

0220017

DS30485A-page 298

Preliminary

 2002 Microchip Technology Inc.

PIC18FXX39

25.2 Package Details

The following sections give the technical details of the packages.

28-Lead Skinny Plastic Dual In-line (SP) – 300 mil (PDIP)

E1

D

2

n

1

α

E

A2

A

L

c

B1

β

A1

eB

p

B

Units

Dimension Limits

INCHES*

NOM

MILLIMETERS

MIN

MAX

MIN

NOM

MAX

n

p

Number of Pins

Pitch

28

.100

.150

.130

2.54

3.81

3.30

Top to Seating Plane

Molded Package Thickness

Base to Seating Plane

Shoulder to Shoulder Width

Molded Package Width

Overall Length

Tip to Seating Plane

Lead Thickness

Upper Lead Width

A

A2

A1

E

E1

D

L

c

B1

B

eB

.140

.160

.135

3.56

4.06

3.43

.125

.015

.300

.275

1.345

.125

.008

.040

.016

.320

3.18

0.38

7.62

6.99

34.16

3.18

0.20

1.02

0.41

8.13

5

.310

.285

1.365

.130

.012

.053

.019

.350

10

.325

.295

1.385

.135

.015

.065

.022

.430

15

7.87

7.24

34.67

3.30

0.29

1.33

0.48

8.89

10

8.26

7.49

35.18

3.43

0.38

1.65

0.56

10.92

15

Lower Lead Width

Overall Row Spacing

Mold Draft Angle Top

Mold Draft Angle Bottom

§

α

5

β

5

10

15

5

10

15

* Controlling Parameter

§ Significant Characteristic

Notes:

Dimension D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed

.010” (0.254mm) per side.

JEDEC Equivalent: MO-095

Drawing No. C04-070

 2002 Microchip Technology Inc.

Preliminary

DS30485A-page 299

PIC18FXX39

28-Lead Plastic Small Outline (SO) – Wide, 300 mil (SOIC)

E

E1

p

D

B

2

1

n

h

α

45°

c

A2

A

φ

β

L

A1

Units

Dimension Limits

INCHES*

NOM

MILLIMETERS

NOM

MIN

MAX

MIN

MAX

n

p

A

A2

A1

E

E1

D

Number of Pins

Pitch

Overall Height

28

.050

.099

.091

.008

.407

.295

.704

.020

.033

4

1.27

2.50

2.31

0.20

10.34

7.49

17.87

0.50

0.84

4

.093

.104

2.36

2.64

Molded Package Thickness

Standoff

.088

.004

.394

.288

.695

.010

.016

0

.094

.012

.420

.299

.712

.029

.050

8

2.24

0.10

10.01

7.32

17.65

0.25

0.41

0

2.39

0.30

10.67

7.59

18.08

0.74

1.27

8

§

Overall Width

Molded Package Width

Overall Length

Chamfer Distance

Foot Length

Foot Angle Top

Lead Thickness

Lead Width

Mold Draft Angle Top

Mold Draft Angle Bottom

h

L

φ

c

B

α

.009

.014

0

.011

.017

12

.013

.020

15

0.23

0.36

0

0.28

0.42

12

0.33

0.51

15

β

0

12

15

0

12

15

* Controlling Parameter

§ Significant Characteristic

Notes:

Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed

.010” (0.254mm) per side.

JEDEC Equivalent: MS-013

Drawing No. C04-052

DS30485A-page 300

Preliminary

 2002 Microchip Technology Inc.

PIC18FXX39

40-Lead Plastic Dual In-line (P) – 600 mil (PDIP)

E1

D

2

1

α

n

E

A2

L

A

c

B1

B

β

A1

p

eB

Units

Dimension Limits

INCHES*

NOM

MILLIMETERS

MIN

MAX

MIN

NOM

MAX

n

p

A

A2

A1

E

E1

D

L

c

B1

B

Number of Pins

Pitch

Top to Seating Plane

Molded Package Thickness

Base to Seating Plane

Shoulder to Shoulder Width

Molded Package Width

Overall Length

Tip to Seating Plane

Lead Thickness

Upper Lead Width

Lower Lead Width

Overall Row Spacing

Mold Draft Angle Top

Mold Draft Angle Bottom

* Controlling Parameter

§ Significant Characteristic

40

.100

.175

.150

2.54

4.45

3.81

.160

.190

.160

4.06

4.83

4.06

.140

.015

.595

.530

2.045

.120

.008

.030

.014

.620

5

3.56

0.38

15.11

13.46

51.94

3.05

0.20

0.76

0.36

15.75

5

.600

.545

2.058

.130

.012

.050

.018

.650

10

.625

.560

2.065

.135

.015

.070

.022

.680

15

15.24

13.84

52.26

3.30

0.29

1.27

0.46

16.51

10

15.88

14.22

52.45

3.43

0.38

1.78

0.56

17.27

15

§

eB

α

β

5

10

15

5

10

15

Notes:

Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed

.010” (0.254mm) per side.

JEDEC Equivalent: MO-011

Drawing No. C04-016

 2002 Microchip Technology Inc.

Preliminary

DS30485A-page 301

PIC18FXX39

44-Lead Plastic Thin Quad Flatpack (PT) 10x10x1 mm Body, 1.0/0.10 mm Lead Form (TQFP)

E

E1

#leads=n1

p

D1

D

2

1

B

n

°

CH x 45

α

A

c

φ

β

A1

A2

L

(F)

Units

Dimension Limits

INCHES

NOM

MILLIMETERS*

MIN

MAX

MIN

NOM

44

MAX

n

p

n1

A

A2

A1

L

(F)

φ

Number of Pins

Pitch

Pins per Side

Overall Height

44

.031

11

0.80

11

1.10

1.00

0.10

0.60

.039

.037

.002

.018

.043

.039

.004

.024

.039

3.5

.472

.394

.006

.015

.035

10

.047

1.00

0.95

0.05

0.45

1.00

0

11.75

9.90

0.09

0.30

0.64

5

1.20

Molded Package Thickness

Standoff

.041

.006

.030

1.05

0.15

0.75

§

Foot Length

Footprint (Reference)

Foot Angle

Overall Width

Overall Length

Molded Package Width

Molded Package Length

Lead Thickness

0

.463

.390

.004

.012

.025

5

7

.482

.398

.008

.017

.045

15

3.5

12.00

10.00

0.15

0.38

0.89

10

7

12.25

10.10

0.20

0.44

1.14

15

E

D

E1

D1

c

B

CH

α

Lead Width

Pin 1 Corner Chamfer

Mold Draft Angle Top

Mold Draft Angle Bottom

β

5

10

15

5

10

15

* Controlling Parameter

§ Significant Characteristic

Notes:

Dimensions D1 and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed

.010” (0.254mm) per side.

JEDEC Equivalent: MS-026

Drawing No. C04-076

DS30485A-page 302

Preliminary

 2002 Microchip Technology Inc.

PIC18FXX39

44-Lead Plastic Quad Flat No Lead Package (ML) 8x8 mm Body (QFN)

EXPOSED

METAL

PAD

E

p

D

D2

2

1

B

n

PIN 1

INDEX ON

OPTIONAL PIN 1

INDEX ON

TOP MARKING

E2

L

EXPOSED PAD

TOP VIEW

BOTTOM VIEW

A

A1

A3

Units

INCHES

MILLIMETERS*

NOM

Dimension Limits

MIN

NOM

MAX

MIN

MAX

n

p

Number of Pins

Pitch

44

.026 BSC

.035

0.65 BSC

Overall Height

Standoff

A

A1

A3

E

.031

.000

.039

0.80

0.90

0.02

1.00

.001

.002

0

0.05

Base Thickness

Overall Width

Exposed Pad Width

Overall Length

Exposed Pad Length

Lead Width

.010 REF

.315 BSC

.268

0.25 REF

8.00 BSC

6.80

E2

D

.262

.274

6.65

6.95

.315 BSC

.268

8.00 BSC

6.80

D2

B

.262

.012

.014

.274

.013

.018

6.65

0.30

0.35

6.95

0.35

0.45

.013

0.33

Lead Length

L

.016

0.40

*Controlling Parameter

Notes:

Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not

exceed .010" (0.254mm) per side.

JEDEC equivalent: M0-220

Drawing No. C04-103

 2002 Microchip Technology Inc.

Preliminary

DS30485A-page 303

PIC18FXX39

44-Lead Quad Flat No Lead Package (ML) 8x8 mm Body (QFN)

Land Pattern and Solder Mask

B

M

p

PACKAGE

EDGE

SOLDER

MASK

Units

INCHES

NOM

.026 BSC

__

MILLIMETERS*

NOM

Dimension Limits

p

MIN

MAX

MIN

MAX

Pitch

0.65 BSC

Pad Width

B

L

__

0.13

__

Pad Length

__

Pad to Solder Mask

M

.005

.006

0.15

*Controlling Parameter

Drawing No. C04-2103

DS30485A-page 304

Preliminary

 2002 Microchip Technology Inc.

PIC18FXX39

APPENDIX A: REVISION HISTORY

APPENDIX B: DEVICE

DIFFERENCES

Revision A (November 2002)

Original data sheet for the PIC18FXX39 family.

The differences between the devices listed in this data

sheet are shown in Table B-1.

TABLE B-1:

DEVICE DIFFERENCES

Feature

PIC18F2439

PIC18F2539

PIC18F4439

PIC18F4539

Program Memory (Kbytes)

Data Memory (Bytes)

A/D Channels

12

640

5

24

1408

5

12

640

8

24

1408

8

Parallel Slave Port (PSP)

No

Yes

40-pin DIP

44-pin TQFP

44-pin QFN

40-pin DIP

44-pin TQFP

44-pin QFN

28-pin DIP

28-pin SOIC

28-pin DIP

28-pin SOIC

Package Types

 2002 Microchip Technology Inc.

Preliminary

DS30485A-page 305

PIC18FXX39

APPENDIX C: CONVERSION

CONSIDERATIONS

The considerations for converting applications from

previous versions of PIC18 microcontrollers (i.e.,

PIC18FXX2 devices) are listed in Table C-1.

A specific list of resources that are unavailable to

PIC18FXX2 applications in PIC18FXX39 devices is

presented in Table C-2.

TABLE C-1:

CONVERSION CONSIDERATIONS BETWEEN PIC18FXX2 AND PIC18FXX39 DEVICES

Characteristic

PIC18FXX2

PIC18FXX39

Pins

28/40/44

DIP, PDIP, SOIC, QFN, TQFP

2.0 - 5.5V

4 - 40 MHz (20 MHz optimal)

12K or 24K

Available Packages

Voltage Range

Frequency Range

Available Program Memory (bytes)

Available Data RAM (bytes)

Data EEPROM

DIP, PDIP, SOIC, PLCC, QFN, TQFP

2.0 - 5.5V

DC - 40 MHz

16K or 32K

768 or 1536

256

640 or 1408

256

Interrupt Sources

Interrupt Priority Levels

17 or 18

15 or 16

Two levels:

One level when using Motor Control:

vector at 0008h

low priority (vector at 0008h)

high priority (vector at 0018h)

Timers (available to users)

Timer1 Oscillator option

Oscillator Switching

4

yes

2 CCP

3

no

Capture/Compare/PWM

2 PWM only, available only through

Motor Control kernel

Motor Control Kernel

A/D

no

yes

10-bit, 5 or 8 channels,

7 conversion clock selects

PSP, AUSART, MSSP (SPI and I C)

By 8K block with separate 512-byte

boot block; protection from external

reads and writes, Table Read and

intra-block Table Read

10-bit, 5 or 8 channels,

7 conversion clock selects

PSP, AUSART, MSSP (SPI and I C)

By 8K block with separate 512-byte

boot block; protection from external

reads and writes, Table Read and intra-

block Table Read; Block 3 not protected

on PIC18FX539

2

Communications

Code Protection

TABLE C-2:

UNAVAILABLE RESOURCES (COMPARED TO PIC18FXX2)

Item(s)

Resource Type

I/O Resources

Registers

SFR bits

RC1; RC2; T1OSO; T1OSI

CCP1CON; CCP2CON; CCPR1L; CCPR2L; TMR2; PR2; T2CON; OSCCON

CCP1IE; CCP1IF; CCP1IP; CCP21E; CCP21F; CCP2IP; T1OSCEN; T3CCP1; TMR2ON;

TOUTPS<3:0>; T2CKPS<1:0>; T3CCP2; SFS; RC1; RC2; TRISC1; TRISC2; LATC1; LATC2

Interrupts and

Interrupt Resources

CCP1 Capture/Compare match; CCP2 Capture/Compare match; High priority interrupts

(when Motor Control is used; reserved for Timer2)

Timer Resources

Timer2 (available only through the Motor Control kernel); Timer2 as a clock source for

MSSP module (SPI mode)

CCP Resources

Capture and Compare functionality; Timer1 reset on special event; Timer3 reset on special

event; A/D conversion on special event; Interrupt on special event

Configuration Word bits OSCEN; CCP2MX; CP3; WRT3; EBTR3

DS30485A-page 306

Preliminary

 2002 Microchip Technology Inc.

PIC18FXX39

APPENDIX D: MIGRATION FROM

HIGH-END TO

ENHANCED DEVICES

A detailed discussion of the migration pathway and dif-

ferences between the high-end MCU devices (i.e.,

PIC17CXXX) and the enhanced devices (i.e.,

PIC18FXXX) is provided in AN726, “PIC17CXXX to

PIC18CXXX Migration”. This Application Note is

available as Literature Number DS00726.

 2002 Microchip Technology Inc.

Preliminary

DS30485A-page 307

PIC18FXX39

NOTES:

DS30485A-page 308

Preliminary

 2002 Microchip Technology Inc.

PIC18FXX39

INDEX

A

Block Diagrams

A/D Converter .......................................................... 183

Analog Input Model .................................................. 184

Baud Rate Generator .............................................. 151

Low Voltage Detect

A/D ................................................................................... 181

A/D Converter Flag (ADIF Bit) ................................. 183

A/D Converter Interrupt, Configuring ....................... 184

Acquisition Requirements ........................................ 184

ADCON0 Register .................................................... 181

ADCON1 Register .................................................... 181

ADRESH Register .................................................... 181

ADRESH/ADRESL Registers .................................. 183

ADRESL Register .................................................... 181

Analog Port Pins .................................................. 95, 96

Analog Port Pins, Configuring .................................. 186

Associated Registers ............................................... 188

Configuring the Module ............................................ 184

Conversion Clock (TAD) ........................................... 186

Conversion Status (GO/DONE Bit) .......................... 183

Conversions ............................................................. 187

Converter Characteristics ........................................ 285

Equations

External Reference Source ............................. 190

Internal Reference Source ............................... 190

2

MSSP (I C Mode) .................................................... 134

MSSP (SPI Mode) ................................................... 125

On-Chip Reset Circuit ................................................ 23

PIC18F2X39 ................................................................ 9

PIC18F4X39 .............................................................. 10

PLL ............................................................................ 21

PORTC (Peripheral Output Override) ........................ 89

PORTD (I/O Mode) .................................................... 91

PORTD and PORTE (Parallel Slave Port) ................. 96

PORTE (I/O Port Mode) ............................................. 93

PWM Operation (Simplified) .................................... 123

RA3:RA0 and RA5 Pins ............................................. 83

RA4/T0CKI Pin .......................................................... 84

RA6 Pin ..................................................................... 84

RB2:RB0 Pins ............................................................ 87

RB3 Pin ..................................................................... 87

RB7:RB4 Pins ............................................................ 86

Reads from FLASH Program Memory ....................... 55

Table Read Operation ............................................... 51

Table Write Operation ................................................ 52

Table Writes to FLASH Program Memory ................. 57

Timer0 in 16-bit Mode .............................................. 100

Timer0 in 8-bit Mode ................................................ 100

Timer1 ..................................................................... 104

Timer1 (16-bit R/W Mode) ....................................... 104

Timer2 ..................................................................... 107

Timer3 ..................................................................... 110

Timer3 (16-bit R/W Mode) ....................................... 110

Typical Motor Control System .................................. 113

USART Receive ....................................................... 174

USART Transmit ...................................................... 172

Watchdog Timer ...................................................... 204

BN .................................................................................... 220

BNC ................................................................................. 221

BNN ................................................................................. 221

BNOV ............................................................................... 222

BNZ .................................................................................. 222

BOR. See Brown-out Reset

Acquisition Time ............................................... 185

Minimum Charging Time .................................. 185

Examples

Calculating the Minimum Required

Acquisition Time ...................................... 185

Result Registers ....................................................... 187

TAD vs. Device Operating Frequencies .................... 186

Absolute Maximum Ratings ............................................. 259

AC (Timing) Characteristics ............................................. 268

Conditions ................................................................ 269

Load Conditions for Device

Timing Specifications ....................................... 269

Parameter Symbology ............................................. 268

Temperature and Voltage Specifications ................. 269

ACKSTAT Status Flag ..................................................... 155

ADCON0 Register ............................................................ 181

GO/DONE Bit ........................................................... 183

ADCON1 Register ............................................................ 181

ADDLW ............................................................................ 217

Addressable Universal Synchronous Asynchronous

Receiver Transmitter. See USART

ADDWF ............................................................................ 217

ADDWFC ......................................................................... 218

ADRESH Register ............................................................ 181

ADRESH/ADRESL Registers ........................................... 183

ADRESL Register ............................................................ 181

Analog-to-Digital Converter. See A/D

BOV ................................................................................. 225

BRA ................................................................................. 223

BRG. See Baud Rate Generator

Brown-out Reset (BOR) ..................................................... 24

BSF .................................................................................. 223

BTFSC ............................................................................. 224

BTFSS ............................................................................. 224

BTG ................................................................................. 225

BZ .................................................................................... 226

ANDLW ............................................................................ 218

ANDWF ............................................................................ 219

Assembler

MPASM Assembler .................................................. 253

B

Baud Rate Generator ....................................................... 151

BC .................................................................................... 219

BCF .................................................................................. 220

BF Status Flag ................................................................. 155

 2002 Microchip Technology Inc.

Preliminary

DS30485A-page 309

PIC18FXX39

Device Overview .................................................................. 7

Features ....................................................................... 8

Direct Addressing ............................................................... 48

Example ..................................................................... 46

C

CALL ................................................................................226

Clocking Scheme/Instruction Cycle ....................................36

CLRF ................................................................................227

CLRWDT ..........................................................................227

Code Examples

E

Electrical Characteristics .................................................. 259

Errata ................................................................................... 5

16 x 16 Signed Multiply Routine .................................68

16 x 16 Unsigned Multiply Routine .............................68

8 x 8 Signed Multiply Routine .....................................67

8 x 8 Unsigned Multiply Routine .................................67

Data EEPROM Read .................................................63

Data EEPROM Refresh Routine ................................64

Data EEPROM Write ..................................................63

Erasing a FLASH Program Memory Row ..................56

How to Clear RAM (Bank 1) Using

Indirect Addressing ............................................47

Initializing PORTA ......................................................83

Initializing PORTB ......................................................86

Initializing PORTC ......................................................89

Initializing PORTD ......................................................91

Initializing PORTE ......................................................93

Loading the SSPBUF (SSPSR) Register .................128

Motor Control Routine using ProMPT APIs ..............121

Reading a FLASH Program Memory Word ................55

Saving STATUS, WREG and

F

Firmware Instructions ....................................................... 211

FLASH Program Memory ................................................... 51

Associated Registers ................................................. 59

Control Registers ....................................................... 52

Erase Sequence ........................................................ 56

Erasing ....................................................................... 56

Operation During Code Protection ............................. 59

Reading ..................................................................... 55

TABLAT Register ....................................................... 54

Table Pointer ............................................................. 54

Boundaries Based on Operation ........................ 54

Table Pointer Boundaries .......................................... 54

Table Reads and Table Writes .................................. 51

Writing to .................................................................... 57

Protection Against Spurious Writes ................... 59

Unexpected Termination .................................... 59

Write Verify ........................................................ 59

BSR Registers in RAM .......................................81

Writing to FLASH Program Memory ..................... 58–59

Code Protection ...............................................................195

COMF ...............................................................................228

Configuration Bits .............................................................195

Context Saving During Interrupts .......................................81

Conversion Considerations ..............................................306

CPFSEQ ..........................................................................228

CPFSGT ...........................................................................229

CPFSLT ...........................................................................229

G

GOTO .............................................................................. 232

H

Hardware Interface .......................................................... 113

Hardware Multiplier ............................................................ 67

Introduction ................................................................ 67

Operation ................................................................... 67

Performance Comparison .......................................... 67

HS/PLL .............................................................................. 20

D

Data EEPROM Memory

I

Associated Registers .................................................65

EEADR Register ........................................................61

EECON1 Register ......................................................61

EECON2 Register ......................................................61

Operation During Code Protect ..................................64

Protection Against Spurious Write .............................64

Reading ......................................................................63

Using ..........................................................................64

Write Verify .................................................................64

Writing ........................................................................63

Data Memory ......................................................................39

General Purpose Registers ........................................39

Map for PIC18FX439 .................................................40

Map for PIC18FX539 .................................................41

Special Function Registers ........................................39

DAW .................................................................................230

DC and AC Characteristics

I/O Ports ............................................................................. 83

2

I C Mode

Bus Collision

During a STOP Condition ................................ 163

2

I C Mode .......................................................................... 134

ACK Pulse ........................................................138, 139

Acknowledge Sequence Timing .............................. 158

Baud Rate Generator ............................................... 151

Bus Collision

Repeated START Condition ............................ 162

START Condition ............................................. 160

Clock Arbitration ...................................................... 152

Clock Stretching ....................................................... 144

Effect of a RESET .................................................... 159

General Call Address Support ................................. 148

Master Mode ............................................................ 149

Operation ......................................................... 150

Reception ........................................................ 155

Repeated START Condition Timing ................ 154

START Condition Timing ................................. 153

Transmission ................................................... 155

Multi-Master Communication, Bus Collision

Graphs and Tables ...................................................287

DC Characteristics ................................................... 261, 264

DCFSNZ ...........................................................................231

DECF ...............................................................................230

DECFSZ ...........................................................................231

Developing Applications ...................................................121

Development Support ......................................................253

Device Differences ...........................................................305

and Arbitration ................................................. 159

DS30485A-page 310

Preliminary

 2002 Microchip Technology Inc.

PIC18FXX39

Multi-Master Mode ................................................... 159

Operation ................................................................. 138

Read/Write Bit Information (R/W Bit) ............... 138, 139

Registers .................................................................. 134

Serial Clock (RC3/SCK/SCL) ................................... 139

Slave Mode .............................................................. 138

Addressing ....................................................... 138

MOVFF .................................................................... 236

MOVLB .................................................................... 236

MOVLW ................................................................... 237

MOVWF ................................................................... 237

MULLW .................................................................... 238

MULWF .................................................................... 238

NEGF ....................................................................... 239

NOP ......................................................................... 239

POP ......................................................................... 240

PUSH ....................................................................... 240

RCALL ..................................................................... 241

RESET ..................................................................... 241

RETFIE .................................................................... 242

RETLW .................................................................... 242

RETURN .................................................................. 243

RLCF ....................................................................... 243

RLNCF ..................................................................... 244

RRCF ....................................................................... 244

RRNCF .................................................................... 245

SETF ....................................................................... 245

SLEEP ..................................................................... 246

SUBFWB ................................................................. 246

SUBLW .................................................................... 247

SUBWF .................................................................... 247

SUBWFB ................................................................. 248

SWAPF .................................................................... 248

TBLRD ..................................................................... 249

TBLWT .................................................................... 250

TSTFSZ ................................................................... 251

XORLW ................................................................... 251

XORWF ................................................................... 252

Summary Table ....................................................... 214

Instructions in Program Memory ........................................ 37

Two-Word Instructions ............................................... 38

INT Interrupt (RB0/INT). See Interrupt Sources

Reception ......................................................... 139

Transmission .................................................... 139

SLEEP Operation ..................................................... 159

STOP Condition Timing ........................................... 158

ICEPIC In-Circuit Emulator .............................................. 254

ID Locations ............................................................. 195, 210

INCF ................................................................................. 232

INCFSZ ............................................................................ 233

In-Circuit Debugger .......................................................... 210

In-Circuit Serial Programming (ICSP) ...................... 195, 210

Indirect Addressing ............................................................ 48

INDF and FSR Registers ........................................... 47

Operation ................................................................... 47

Indirect Addressing Operation ............................................ 48

Indirect File Operand .......................................................... 39

INFSNZ ............................................................................ 233

Instruction Cycle ................................................................. 36

Instruction Flow/Pipelining ................................................. 37

Instruction Format ............................................................ 213

Instruction Set .................................................................. 211

ADDLW .................................................................... 217

ADDWF .................................................................... 217

ADDWFC ................................................................. 218

ANDLW .................................................................... 218

ANDWF .................................................................... 219

BC ............................................................................ 219

BCF .......................................................................... 220

BN ............................................................................ 220

BNC ......................................................................... 221

BNN ......................................................................... 221

BNOV ....................................................................... 222

BNZ .......................................................................... 222

BOV ......................................................................... 225

BRA .......................................................................... 223

BSF .......................................................................... 223

BTFSC ..................................................................... 224

BTFSS ..................................................................... 224

BTG .......................................................................... 225

BZ ............................................................................ 226

CALL ........................................................................ 226

CLRF ........................................................................ 227

CLRWDT .................................................................. 227

COMF ...................................................................... 228

CPFSEQ .................................................................. 228

CPFSGT .................................................................. 229

CPFSLT ................................................................... 229

DAW ......................................................................... 230

DCFSNZ .................................................................. 231

DECF ....................................................................... 230

DECFSZ ................................................................... 231

GOTO ...................................................................... 232

INCF ......................................................................... 232

INCFSZ .................................................................... 233

INFSNZ .................................................................... 233

IORLW ..................................................................... 234

IORWF ..................................................................... 234

LFSR ........................................................................ 235

MOVF ....................................................................... 235

INTCON Register

RBIF Bit ..................................................................... 86

INTCON Registers ........................................................71–73

2

Inter-Integrated Circuit. See I C

Interrupt Sources ............................................................. 195

A/D Conversion Complete ....................................... 184

INT0 ........................................................................... 81

Interrupt-on-Change (RB7:RB4) ................................ 86

PORTB, Interrupt-on-Change .................................... 81

RB0/INT Pin, External ................................................ 81

TMR0 ......................................................................... 81

TMR0 Overflow ........................................................ 101

TMR1 Overflow .................................................103, 105

TMR2 to PR2 Match (PWM) .................................... 123

TMR3 Overflow .................................................109, 111

USART Receive/Transmit Complete ....................... 165

Interrupts ............................................................................ 69

Logic .......................................................................... 70

Interrupts, Flag Bits

A/D Converter Flag (ADIF Bit) ................................. 183

Interrupt-on-Change (RB7:RB4) Flag

(RBIF Bit) ........................................................... 86

IORLW ............................................................................. 234

IORWF ............................................................................. 234

IPR Registers ................................................................78–79

K

KEELOQ Evaluation and Programming Tools ................... 256

 2002 Microchip Technology Inc.

Preliminary

DS30485A-page 311

PIC18FXX39

L

O

LFSR ................................................................................235

Lookup Tables

Opcode Field Descriptions ............................................... 212

OPTION_REG Register

Computed GOTO .......................................................38

Table Reads, Table Writes .........................................38

Low Voltage Detect ..........................................................189

Characteristics .........................................................266

Effects of a RESET ..................................................193

Operation .................................................................192

Current Consumption .......................................193

During SLEEP ..................................................193

Reference Voltage Set Point ............................193

Typical Application ...................................................189

LVD. See Low Voltage Detect. .........................................189

PSA Bit .................................................................... 101

T0CS Bit .................................................................. 101

T0PS2:T0PS0 Bits ................................................... 101

T0SE Bit ................................................................... 101

Oscillator Configuration ...................................................... 19

EC .............................................................................. 19

ECIO .......................................................................... 19

HS .............................................................................. 19

HS + PLL ................................................................... 19

Oscillator Selection .......................................................... 195

Oscillator, Timer1 ............................................................. 103

Oscillator, Timer3 ............................................................. 109

Oscillator, WDT ................................................................ 203

M

Master SSP (MSSP) Module

P

Overview ..................................................................125

Master Synchronous Serial Port (MSSP). See MSSP.

Master Synchronous Serial Port. See MSSP

Packaging ........................................................................ 297

Details ...................................................................... 299

Marking Information ................................................. 297

Parallel Slave Port (PSP) ..............................................91, 96

Associated Registers ................................................. 97

PORTD ...................................................................... 96

RE0/AN5/RD Pin ....................................................... 95

RE1/AN6/WR Pin ..................................................95, 96

RE2/AN7/CS Pin ...................................................95, 96

Select (PSPMODE Bit) .........................................91, 96

PIC18F2X39 Pin Functions

Memory Organization

Data Memory ..............................................................39

Program Memory .......................................................33

Memory Programming Requirements ..............................267

Migration from High-End to Enhanced Devices ...............307

Motor Control ........................................................... 113, 121

ProMPT API Methods ...................................... 117–120

Defined Parameters .........................................121

Software Interface ....................................................114

Theory of Operation .................................................113

V/F Curve .................................................................114

MOVF ...............................................................................235

MOVFF .............................................................................236

MOVLB .............................................................................236

MOVLW ............................................................................237

MOVWF ...........................................................................237

MPLAB C17 and MPLAB C18 C Compilers .....................253

MPLAB ICD In-Circuit Debugger ......................................255

MPLAB ICE High Performance Universal In-Circuit

Emulator with MPLAB IDE .......................................254

MPLAB Integrated Development

MCLR/VPP ................................................................. 11

OSC1/CLKI ................................................................ 11

OSC2/CLKO/RA6 ...................................................... 11

PWM1 ........................................................................ 13

PWM2 ........................................................................ 13

RA0/AN0 .................................................................... 11

RA1/AN1 .................................................................... 11

RA2/AN2/VREF- ......................................................... 11

RA3/AN3/VREF+ ......................................................... 11

RA4/T0CKI ................................................................. 11

RA5/AN4/SS/LVDIN .................................................. 11

RB0/INT0 ................................................................... 12

RB1/INT1 ................................................................... 12

RB2/INT2 ................................................................... 12

RB3 ............................................................................ 12

RB4 ............................................................................ 12

RB5/PGM ................................................................... 12

RB6/PGC ................................................................... 12

RB7/PGD ................................................................... 12

RC0/T13CKI .............................................................. 13

RC3/SCK/SCL ........................................................... 13

RC4/SDI/SDA ............................................................ 13

RC5/SDO ................................................................... 13

RC6/TX/CK ................................................................ 13

RC7/RX/DT ................................................................ 13

VDD ............................................................................ 13

VSS ............................................................................. 13

Environment Software ..............................................253

MPLINK Object Linker/MPLIB Object Librarian ...............254

MSSP

Control Registers (general) ......................................125

Enabling SPI I/O .......................................................129

2

I C Mode. See I C ...................................................125

Operation .................................................................128

SPI Master Mode .....................................................130

SPI Master/Slave Connection ..................................129

SPI Mode .................................................................125

SPI Slave Mode .......................................................131

SSPBUF Register ....................................................130

SSPSR Register .......................................................130

Typical Connection ...................................................129

MULLW ............................................................................238

MULWF ............................................................................238

N

NEGF ...............................................................................239

NOP .................................................................................239

DS30485A-page 312

Preliminary

 2002 Microchip Technology Inc.

PIC18FXX39

Programming, Device Instructions ...................................211

PSP.See Parallel Slave Port.

TXSTA (Transmit Status and Control) ..................... 166

WDTCON (Watchdog Timer Control) ...................... 203

RESET ................................................................23, 195, 241

Brown-out Reset (BOR) ........................................... 195

MCLR Reset (During SLEEP) .................................... 23

MCLR Reset (Normal Operation) .............................. 23

Oscillator Start-up Timer (OST) ............................... 195

Power-on Reset (POR) .......................................23, 195

Power-up Timer (PWRT) ......................................... 195

Programmable Brown-out Reset (BOR) .................... 23

RESET Instruction ..................................................... 23

Stack Full Reset ......................................................... 23

Stack Underflow Reset .............................................. 23

Watchdog Timer (WDT) Reset .................................. 23

RETFIE ............................................................................ 242

RETLW ............................................................................ 242

RETURN .......................................................................... 243

Return Address Stack ........................................................ 34

Associated Registers ................................................. 35

Pointer (STKPTR) ...................................................... 34

Top-of-Stack Access .................................................. 34

Revision History ............................................................... 305

RLCF ............................................................................... 243

RLNCF ............................................................................. 244

RRCF ............................................................................... 244

RRNCF ............................................................................ 245

Pulse Width Modulation (PWM) .......................................123

Pulse Width Modulation. See PWM.

PUSH ...............................................................................240

PWM

Associated Registers ...............................................124

CCPR1H:CCPR1L Registers ...................................123

Duty Cycle ................................................................124

Period .......................................................................123

TMR2 to PR2 Match .................................................123

Q

Q Clock ............................................................................124

R

RAM. See Data Memory

RCALL ..............................................................................241

RCSTA Register

SPEN Bit ..................................................................165

Register File .......................................................................39

Registers

ADCON0 (A/D Control 0) .........................................181

ADCON1 (A/D Control 1) .........................................182

CCP1CON and CCP2CON (PWM Control) .............123

CONFIG1H (Configuration 1 High) ..........................196

CONFIG2H (Configuration 2 High) ..........................197

CONFIG2L (Configuration 2 Low) ............................197

CONFIG4L (Configuration 4 Low) ............................198

CONFIG5H (Configuration 5 High) ..........................199

CONFIG5L (Configuration 5 Low) ............................199

CONFIG6H (Configuration 6 High) ..........................200

CONFIG6L (Configuration 6 Low) ............................200

CONFIG7H (Configuration 7 High) ..........................201

CONFIG7L (Configuration 7 Low) ............................201

DEVID1 (Device ID 1) ..............................................202

DEVID2 (Device ID 2) ..............................................202

EECON1 (Data EEPROM Control 1) ................... 53, 62

File Summary ....................................................... 43–45

INTCON (Interrupt Control) ........................................71

INTCON2 (Interrupt Control 2) ...................................72

INTCON3 (Interrupt Control 3) ...................................73

IPR1 (Peripheral Interrupt Priority 1) ..........................78

IPR2 (Peripheral Interrupt Priority 2) ..........................79

LVDCON (LVD Control) ...........................................191

PIE1 (Peripheral Interrupt Enable 1) ..........................76

PIE2 (Peripheral Interrupt Enable 2) ..........................77

PIR1 (Peripheral Interrupt Request 1) ........................74

PIR2 (Peripheral Interrupt Request 2) ........................75

RCON (Register Control) ...........................................80

RCON (RESET Control) .............................................50

RCSTA (Receive Status and Control) ......................167

SSPCON1 (MSSP Control 1)

S

SCI. See USART

SCK ................................................................................. 125

SDI ................................................................................... 125

SDO ................................................................................. 125

Serial Clock, SCK ............................................................ 125

Serial Communication Interface. See USART

Serial Data In, SDI ........................................................... 125

Serial Data Out, SDO ....................................................... 125

Serial Peripheral Interface. See SPI Mode

SETF ................................................................................ 245

Single Phase Induction Motor Control Module.

See Motor Control. ................................................... 113

Slave Select Synchronization .......................................... 131

Slave Select, SS .............................................................. 125

SLEEP ..............................................................195, 205, 246

Software Simulator (MPLAB SIM) .................................... 254

Special Features of the CPU ........................................... 195

Configuration Registers ....................................196–201

Special Function Registers ................................................ 39

Map ............................................................................ 42

SPI Mode

Associated Registers ............................................... 133

Bus Mode Compatibility ........................................... 133

Effects of a RESET .................................................. 133

Master Mode ............................................................ 130

Master/Slave Connection ......................................... 129

Overview .................................................................. 125

Serial Clock .............................................................. 125

Serial Data In ........................................................... 125

Serial Data Out ........................................................ 125

Slave Mode .............................................................. 131

Slave Select ............................................................. 125

Slave Select Synchronization .................................. 131

Slave Synch Timing ................................................. 131

SLEEP Operation .................................................... 133

SPI Clock ................................................................. 130

SS .................................................................................... 125

SSPOV Status Flag ......................................................... 155

SPI Mode .........................................................127

2

SSPCON1 (MSSP Control 1), I C Mode ..................136

SSPCON2 (MSSP Control 2), I C Mode ..................137

SSPSTAT (MSSP Status)

SPI Mode .........................................................126

2

SSPSTAT (MSSP Status), I C Mode .......................135

STATUS .....................................................................49

STKPTR (Stack Pointer) ............................................35

T0CON (Timer0 Control) ............................................99

T1CON (Timer 1 Control) .........................................103

T2CON (Timer2 Control) ..........................................107

T3CON (Timer3 Control) ..........................................109

TRISE .........................................................................94

DS30485A-page 314

Preliminary

 2002 Microchip Technology Inc.

PIC18FXX39

SSPSTAT Register

R/W Bit ............................................................. 138, 139

Status Bits

Significance and the Initialization Condition

for RCON Register ............................................. 25

SUBFWB .......................................................................... 246

SUBLW ............................................................................ 247

SUBWF ............................................................................ 247

SUBWFB .......................................................................... 248

SWAPF ............................................................................ 248

CLKO and I/O .......................................................... 271

Clock Synchronization ............................................. 145

Clock/Instruction Cycle .............................................. 36

Example SPI Master Mode (CKE = 0) ..................... 276

Example SPI Master Mode (CKE = 1) ..................... 277

Example SPI Slave Mode (CKE = 0) ....................... 278

Example SPI Slave Mode (CKE = 1) ....................... 279

External Clock (All Modes except PLL) ................... 270

First START Bit Timing ............................................ 153

2

I C Bus Data ............................................................ 280

I C Bus START/STOP Bits ...................................... 280

T

I C Master Mode (7 or 10-bit Transmission) ............ 156

TABLAT Register ............................................................... 54

Table Pointer Operations (table) ........................................ 54

TBLPTR Register ............................................................... 54

TBLRD ............................................................................. 249

TBLWT ............................................................................. 250

Time-out Sequence ............................................................ 24

Time-out in Various Sitations ..................................... 25

Timer0 ................................................................................ 99

16-bit Mode Timer Reads and Writes ...................... 101

Associated Registers ............................................... 101

Clock Source Edge Select (T0SE Bit) ...................... 101

Clock Source Select (T0CS Bit) ............................... 101

Operation ................................................................. 101

Overflow Interrupt .................................................... 101

Prescaler. See Prescaler, Timer0

I C Master Mode (7-bit Reception) .......................... 157

I C Slave Mode (10-bit Transmission) ..................... 143

I C Slave Mode (7-bit Transmission) ....................... 141

I C Slave Mode with SEN = 0

(10-bit Reception) ............................................ 142

2

I C Slave Mode with SEN = 0

(7-bit Reception) .............................................. 140

2

I C Slave Mode with SEN = 1

(10-bit Reception) ............................................ 147

2

I C Slave Mode with SEN = 1

(7-bit Reception) .............................................. 146

Low Voltage Detect ................................................. 192

2

Master SSP I C Bus Data ........................................ 282

Master SSP I C Bus START/STOP Bits .................. 282

Parallel Slave Port (PIC18F4X39) ........................... 275

Parallel Slave Port (Read) ......................................... 97

Parallel Slave Port (Write) ......................................... 96

PWM (PWM1 and PWM2) ....................................... 274

PWM Output ............................................................ 123

Repeat START Condition ........................................ 154

RESET, Watchdog Timer (WDT), Oscillator

Timer1 .............................................................................. 103

16-bit Read/Write Mode ........................................... 105

Associated Registers ............................................... 105

Operation ................................................................. 104

Oscillator .................................................................. 103

Overflow Interrupt ............................................ 103, 105

TMR1H Register ...................................................... 103

TMR1L Register ....................................................... 103

Timer2 .............................................................................. 107

TMR2 to PR2 Match Interrupt .................................. 123

Timer3 .............................................................................. 109

Associated Registers ............................................... 111

Operation ................................................................. 110

Oscillator .................................................................. 109

Overflow Interrupt ............................................ 109, 111

TMR3H Register ...................................................... 109

TMR3L Register ....................................................... 109

Timing Diagrams

Start-up Timer (OST) and

Power-up Timer (PWRT) ................................. 272

Slave Mode General Call Address Sequence

(7 or 10-bit Address Mode) .............................. 148

Slave Synchronization ............................................. 131

Slow Rise Time (MCLR Tied to VDD) ......................... 31

SPI Mode (Master Mode) ......................................... 130

SPI Mode (Slave Mode with CKE = 0) ..................... 132

SPI Mode (Slave Mode with CKE = 1) ..................... 132

Stop Condition Receive or Transmit Mode .............. 158

Synchronous Reception (Master Mode, SREN) ...... 178

Synchronous Transmission ..................................... 177

Synchronous Transmission (Through TXEN) .......... 177

Time-out Sequence on POR w/PLL Enabled

A/D Conversion ........................................................ 285

Acknowledge Sequence .......................................... 158

Asynchronous Reception ......................................... 175

Asynchronous Transmission .................................... 173

Asynchronous Transmission (Back to Back) ........... 173

Baud Rate Generator with Clock Arbitration ............ 152

BRG Reset Due to SDA Arbitration

(MCLR Tied to VDD) .......................................... 31

Time-out Sequence on Power-up

(MCLR Not Tied to VDD)

Case 1 ............................................................... 30

Case 2 ............................................................... 30

Time-out Sequence on Power-up

During START Condition ................................. 161

Brown-out Reset (BOR) ........................................... 272

Bus Collision During a STOP Condition

(MCLR Tied to VDD) .......................................... 30

Timer0 and Timer1 External Clock .......................... 273

USART Synchronous Receive (Master/Slave) ........ 284

USART Synchronous Transmission

(Case 1) ........................................................... 163

Bus Collision During a STOP Condition

(Case 2) ........................................................... 163

Bus Collision During Repeated START

(Master/Slave) ................................................. 284

Wake-up from SLEEP via Interrupt .......................... 206

Timing Diagrams Requirements

Condition (Case 1) ........................................... 162

Bus Collision During Repeated START

2

Master SSP I C Bus START/STOP Bits .................. 282

Condition (Case 2) ........................................... 162

Bus Collision During START Condition

(SCL = 0) ......................................................... 161

Bus Collision During Start Condition

(SDA Only) ....................................................... 160

Bus Collision for Transmit and Acknowledge ........... 159

 2002 Microchip Technology Inc.

Preliminary

DS30485A-page 315

PIC18FXX39

Timing Requirements

W

A/D Conversion ........................................................286

CLKO and I/O ...........................................................271

Example SPI Mode (Master Mode, CKE = 0) ..........276

Example SPI Mode (Master Mode, CKE = 1) ..........277

Example SPI Mode (Slave Mode, CKE = 0) ............278

Example SPI Slave Mode (CKE = 1) .......................279

External Clock ..........................................................270

Wake-up from SLEEP ...............................................195, 205

Using Interrupts ....................................................... 205

Watchdog Timer (WDT) ............................................195, 203

Associated Registers ............................................... 204

Control Register ....................................................... 203

Postscaler .........................................................203, 204

Programming Considerations .................................. 203

RC Oscillator ............................................................ 203

Time-out Period ....................................................... 203

WCOL .............................................................................. 153

WCOL Status Flag ............................................153, 155, 158

WWW, On-Line Support ...................................................... 5

2

I C Bus Data (Slave Mode) ......................................281

2

Master SSP I C Bus Data ........................................283

Parallel Slave Port (PIC18F4X39) ............................275

PWM ........................................................................274

RESET, Watchdog Timer, Oscillator

Start-up Timer, Power-up Timer and

Brown-out Reset Requirements .......................272

Timer0 and Timer1 External Clock ...........................273

USART Synchronous Receive .................................284

USART Synchronous Transmission .........................284

Timing Specifications

PLL Clock .................................................................270

TRISE Register

X

XORLW ............................................................................ 251

XORWF ........................................................................... 252

PSPMODE Bit ...................................................... 91, 96

TSTFSZ ............................................................................251

Two-Word Instructions

Example Cases ..........................................................38

TXSTA Register

BRGH Bit ..................................................................168

U

USART .............................................................................165

Asynchronous Mode ................................................172

Associated Registers, Receive ........................175

Associated Registers, Transmit .......................173

Receiver ...........................................................174

Transmitter .......................................................172

Baud Rate Generator (BRG) ....................................168

Associated Registers .......................................168

Baud Rate Error, Calculating ...........................168

Baud Rate Formula ..........................................168

Baud Rates for Asynchronous Mode

(BRGH = 0) ..............................................170

Baud Rates for Asynchronous Mode

(BRGH = 1) ..............................................171

Baud Rates for Synchronous Mode .................169

High Baud Rate Select (BRGH Bit) ..................168

Sampling ..........................................................168

Serial Port Enable (SPEN Bit) ..................................165

Synchronous Master Mode ......................................176

Associated Registers, Reception .....................178

Associated Registers, Transmit .......................176

Reception .........................................................178

Transmission ....................................................176

Synchronous Slave Mode ........................................179

Associated Registers, Receive ........................180

Associated Registers, Transmit .......................179

Reception .........................................................180

Transmission ....................................................179

DS30485A-page 316

Preliminary

 2002 Microchip Technology Inc.

PIC18FXX39

ON-LINE SUPPORT

Microchip provides on-line support on the Microchip

World Wide Web site.

SYSTEMS INFORMATION AND

UPGRADE HOT LINE

The Systems Information and Upgrade Line provides

system users a listing of the latest versions of all of

Microchip's development systems software products.

Plus, this line provides information on how customers

can receive the most current upgrade kits.The Hot Line

Numbers are:

1-800-755-2345 for U.S. and most of Canada, and

1-480-792-7302 for the rest of the world.

The web site is used by Microchip as a means to make

files and information easily available to customers. To

view the site, the user must have access to the Internet

®

and a web browser, such as Netscape or Microsoft

Internet Explorer. Files are also available for FTP

download from our FTP site.

ConnectingtotheMicrochipInternetWebSite

The Microchip web site is available at the following

URL:

092002

www.microchip.com

The file transfer site is available by using an FTP ser-

vice to connect to:

ftp://ftp.microchip.com

The web site and file transfer site provide a variety of

services. Users may download files for the latest

Development Tools, Data Sheets, Application Notes,

User's Guides, Articles and Sample Programs. A vari-

ety of Microchip specific business information is also

available, including listings of Microchip sales offices,

distributors and factory representatives. Other data

available for consideration is:

• Latest Microchip Press Releases

• Technical Support Section with Frequently Asked

Questions

• Design Tips

• Device Errata

• Job Postings

• Microchip Consultant Program Member Listing

• Links to other useful web sites related to

Microchip Products

• Conferences for products, Development Systems,

technical information and more

• Listing of seminars and events

 2002 Microchip Technology Inc.

Preliminary

DS30485A-page 317

PIC18FXX39

READER RESPONSE

It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip prod-

uct. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation

can better serve you, please FAX your comments to the Technical Publications Manager at (480) 792-4150.

Please list the following information, and use this outline to provide us with your comments about this document.

To:

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Reader Response

Total Pages Sent ________

RE:

From:

Name

Company

Address

City / State / ZIP / Country

Telephone: (_______) _________ - _________

FAX: (______) _________ - _________

Application (optional):

Would you like a reply?

Y

N

Literature Number:

DS30485A

Device:

PIC18FXX39

Questions:

1. What are the best features of this document?

2. How does this document meet your hardware and software development needs?

3. Do you find the organization of this document easy to follow? If not, why?

4. What additions to the document do you think would enhance the structure and subject?

5. What deletions from the document could be made without affecting the overall usefulness?

6. Is there any incorrect or misleading information (what and where)?

7. How would you improve this document?

DS30485A-page 318

Preliminary

 2002 Microchip Technology Inc.

PIC18FXX39

PIC18FXX39 PRODUCT IDENTIFICATION SYSTEM

To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.

X

/XX

XXX

PART NO.

−

Examples:

Device

Temperature Package

Range

Pattern

a) PIC18LF4539 - I/P 301 = Industrial

temp., PDIP package, Extended VDD

limits, QTP pattern #301.

b) PIC18LF2439 - I/SO = Industrial temp.,

SOIC package, Extended VDD limits.

c) PIC18F4439 - E/P = Extended temp.,

PDIP package, normal VDD limits.

(1)

(2)

Device

PIC18FXX39 , PIC18FXX39T ;

VDD range 4.2V to 5.5V

(1)

(2)

PIC18LFXX39 , PIC18LFXX39T

VDD range 2.0V to 5.5V

;

Temperature

Range

I

E

=

-40°C to +85°C (Industrial)

-40°C to +125°C (Extended)

Note 1: F

LF

2: T

=

Standard Voltage range

Wide Voltage Range

in tape and reel - SOIC,

QFN, and TQFP

packages only.

Package

ML

P

PT

SO

SP

=

QFN (Quad Flatpack, No Leads)

PDIP

TQFP (Plastic Thin Quad Flatpack)

SOIC

Skinny Plastic DIP

Pattern

QTP, SQTP, Code or Special Requirements

(blank otherwise)

Sales and Support

Data Sheets

Products supported by a preliminary Data Sheet may have an errata sheet describing minor operational differences and recom-

mended workarounds. To determine if an errata sheet exists for a particular device, please contact one of the following:

1. Your local Microchip sales office

2. The Microchip Corporate Literature Center U.S. FAX: (480) 792-7277

3. The Microchip Worldwide Site (www.microchip.com)

Please specify which device, revision of silicon and Data Sheet (include Literature #) you are using.

New Customer Notification System

Register on our web site (www.microchip.com/cn) to receive the most current information on our products.

 2002 Microchip Technology Inc.

Preliminary

DS30485A-page 319

WORLDWIDE SALES AND SERVICE

Japan

AMERICAS

ASIA/PACIFIC

Microchip Technology Japan K.K.

Benex S-1 6F

Corporate Office

Australia

2355 West Chandler Blvd.

Microchip Technology Australia Pty Ltd

Suite 22, 41 Rawson Street

Epping 2121, NSW

3-18-20, Shinyokohama

Kohoku-Ku, Yokohama-shi

Kanagawa, 222-0033, Japan

Tel: 81-45-471- 6166 Fax: 81-45-471-6122

Chandler, AZ 85224-6199

Tel: 480-792-7200 Fax: 480-792-7277

Technical Support: 480-792-7627

Web Address: http://www.microchip.com

Australia

Tel: 61-2-9868-6733 Fax: 61-2-9868-6755

Korea

China - Beijing

Rocky Mountain

Microchip Technology Korea

168-1, Youngbo Bldg. 3 Floor

Samsung-Dong, Kangnam-Ku

Seoul, Korea 135-882

Microchip Technology Consulting (Shanghai)

Co., Ltd., Beijing Liaison Office

Unit 915

2355 West Chandler Blvd.

Chandler, AZ 85224-6199

Tel: 480-792-7966 Fax: 480-792-4338

Bei Hai Wan Tai Bldg.

Tel: 82-2-554-7200 Fax: 82-2-558-5934

Atlanta

No. 6 Chaoyangmen Beidajie

Beijing, 100027, No. China

Tel: 86-10-85282100 Fax: 86-10-85282104

Singapore

3780 Mansell Road, Suite 130

Alpharetta, GA 30022

Microchip Technology Singapore Pte Ltd.

200 Middle Road

Tel: 770-640-0034 Fax: 770-640-0307

China - Chengdu

#07-02 Prime Centre

Boston

Microchip Technology Consulting (Shanghai)

Co., Ltd., Chengdu Liaison Office

Rm. 2401-2402, 24th Floor,

Singapore, 188980

2 Lan Drive, Suite 120

Westford, MA 01886

Tel: 978-692-3848 Fax: 978-692-3821

Tel: 65-6334-8870 Fax: 65-6334-8850

Taiwan

Ming Xing Financial Tower

Microchip Technology (Barbados) Inc.,

Taiwan Branch

No. 88 TIDU Street

Chicago

Chengdu 610016, China

333 Pierce Road, Suite 180

Itasca, IL 60143

11F-3, No. 207

Tel: 86-28-86766200 Fax: 86-28-86766599

Tung Hua North Road

Taipei, 105, Taiwan

China - Fuzhou

Tel: 630-285-0071 Fax: 630-285-0075

Microchip Technology Consulting (Shanghai)

Co., Ltd., Fuzhou Liaison Office

Unit 28F, World Trade Plaza

Tel: 886-2-2717-7175 Fax: 886-2-2545-0139

Dallas

4570 Westgrove Drive, Suite 160

Addison, TX 75001

EUROPE

Austria

No. 71 Wusi Road

Tel: 972-818-7423 Fax: 972-818-2924

Fuzhou 350001, China

Microchip Technology Austria GmbH

Durisolstrasse 2

Detroit

Tel: 86-591-7503506 Fax: 86-591-7503521

Tri-Atria Office Building

China - Hong Kong SAR

A-4600 Wels

32255 Northwestern Highway, Suite 190

Farmington Hills, MI 48334

Tel: 248-538-2250 Fax: 248-538-2260

Microchip Technology Hongkong Ltd.

Unit 901-6, Tower 2, Metroplaza

223 Hing Fong Road

Austria

Tel: 43-7242-2244-399

Fax: 43-7242-2244-393

Denmark

Kwai Fong, N.T., Hong Kong

Kokomo

Tel: 852-2401-1200 Fax: 852-2401-3431

2767 S. Albright Road

Kokomo, Indiana 46902

Tel: 765-864-8360 Fax: 765-864-8387

Microchip Technology Nordic ApS

Regus Business Centre

Lautrup hoj 1-3

China - Shanghai

Microchip Technology Consulting (Shanghai)

Co., Ltd.

Ballerup DK-2750 Denmark

Los Angeles

Room 701, Bldg. B

Tel: 45 4420 9895 Fax: 45 4420 9910

18201 Von Karman, Suite 1090

Irvine, CA 92612

Far East International Plaza

No. 317 Xian Xia Road

France

Microchip Technology SARL

Parc d’Activite du Moulin de Massy

43 Rue du Saule Trapu

Tel: 949-263-1888 Fax: 949-263-1338

Shanghai, 200051

San Jose

Tel: 86-21-6275-5700 Fax: 86-21-6275-5060

Microchip Technology Inc.

2107 North First Street, Suite 590

San Jose, CA 95131

China - Shenzhen

Batiment A - ler Etage

Microchip Technology Consulting (Shanghai)

Co., Ltd., Shenzhen Liaison Office

91300 Massy, France

Tel: 33-1-69-53-63-20 Fax: 33-1-69-30-90-79

Tel: 408-436-7950 Fax: 408-436-7955

Rm. 1812, 18/F, Building A, United Plaza

No. 5022 Binhe Road, Futian District

Shenzhen 518033, China

Germany

Toronto

Microchip Technology GmbH

Steinheilstrasse 10

6285 Northam Drive, Suite 108

Mississauga, Ontario L4V 1X5, Canada

Tel: 905-673-0699 Fax: 905-673-6509

Tel: 86-755-82901380 Fax: 86-755-82966626

D-85737 Ismaning, Germany

Tel: 49-89-627-144 0 Fax: 49-89-627-144-44

China - Qingdao

Rm. B503, Fullhope Plaza,

Italy

No. 12 Hong Kong Central Rd.

Qingdao 266071, China

Microchip Technology SRL

Centro Direzionale Colleoni

Palazzo Taurus 1 V. Le Colleoni 1

20041 Agrate Brianza

Tel: 86-532-5027355 Fax: 86-532-5027205

India

Milan, Italy

Microchip Technology Inc.

India Liaison Office

Tel: 39-039-65791-1 Fax: 39-039-6899883

Divyasree Chambers

United Kingdom

1 Floor, Wing A (A3/A4)

No. 11, O’Shaugnessey Road

Bangalore, 560 025, India

Tel: 91-80-2290061 Fax: 91-80-2290062

Microchip Ltd.

505 Eskdale Road

Winnersh Triangle

Wokingham

Berkshire, England RG41 5TU

Tel: 44 118 921 5869 Fax: 44-118 921-5820

12/05/02

DS30485A-page 320

Preliminary

 2002 Microchip Technology Inc.


型号：	PIC18F4539
厂家：	MICROCHIP
描述：	Enhanced FLASH Microcontrollers with Single Phase Induction Motor Control Kernel 增强型闪存微控制器与单相感应电动机控制内核闪存微控制器电动机控制
文件：	总322页 (文件大小：5683K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

PIC18F4539 [MICROCHIP]

相关型号：

PIC18F4539-E/ML

PIC18F4539-E/MLQTP

PIC18F4539-E/MLSQTP

PIC18F4539-E/P

PIC18F4539-E/PQTP

PIC18F4539-E/PSQTP

PIC18F4539-E/PT

PIC18F4539-E/PTQTP

PIC18F4539-E/PTSQTP

PIC18F4539-E/SO

PIC18F4539-E/SOQTP

PIC18F4539-E/SOSQTP