PIC18F4685T-I/SP [MICROCHIP]
28/40/44-Pin Enhanced Flash Microcontrollers with ECAN Technology, 10-Bit A/D and nanoWatt Technology; 28 /40/ 44引脚增强型闪存微控制器与ECAN技术， 10位A / D和纳瓦技术
| 型号： | PIC18F4685T-I/SP |
| 厂家： | 
MICROCHIP |
| 描述： | 28/40/44-Pin Enhanced Flash Microcontrollers with ECAN Technology, 10-Bit A/D and nanoWatt Technology |
| 文件： | 总484页 (文件大小：8192K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PIC18F2682/2685/4682/4685
Data Sheet
28/40/44-Pin
Enhanced Flash Microcontrollers
with ECAN™ Technology, 10-Bit A/D
and nanoWatt Technology
© 2007 Microchip Technology Inc.
Preliminary
DS39761B
Note the following details of the code protection feature on Microchip devices:
•
Microchip products meet the specification contained in their particular Microchip Data Sheet.
•
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
•
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
•
•
Microchip is willing to work with the customer who is concerned about the integrity of their code.
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
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OTHERWISE, RELATED TO THE INFORMATION,
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
QUALITY, PERFORMANCE, MERCHANTABILITY OR
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conveyed, implicitly or otherwise, under any Microchip
intellectual property rights.
Trademarks
The Microchip name and logo, the Microchip logo, Accuron,
dsPIC, KEELOQ, KEELOQ logo, microID, MPLAB, PIC,
PICmicro, PICSTART, PRO MATE, PowerSmart, rfPIC, and
SmartShunt are registered trademarks of Microchip
Technology Incorporated in the U.S.A. and other countries.
AmpLab, FilterLab, Linear Active Thermistor, Migratable
Memory, MXDEV, MXLAB, PS logo, SEEVAL, SmartSensor
and The Embedded Control Solutions Company are
registered trademarks of Microchip Technology Incorporated
in the U.S.A.
Analog-for-the-Digital Age, Application Maestro, CodeGuard,
dsPICDEM, dsPICDEM.net, dsPICworks, ECAN,
ECONOMONITOR, FanSense, FlexROM, fuzzyLAB,
In-Circuit Serial Programming, ICSP, ICEPIC, Mindi, MiWi,
MPASM, MPLAB Certified logo, MPLIB, MPLINK, PICkit,
PICDEM, PICDEM.net, PICLAB, PICtail, PowerCal,
PowerInfo, PowerMate, PowerTool, REAL ICE, rfLAB,
rfPICDEM, Select Mode, Smart Serial, SmartTel, Total
Endurance, UNI/O, WiperLock and ZENA are trademarks of
Microchip Technology Incorporated in the U.S.A. and other
countries.
SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.
All other trademarks mentioned herein are property of their
respective companies.
© 2007, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.
Printed on recycled paper.
Microchip received ISO/TS-16949:2002 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona, Gresham, Oregon and Mountain View, California. The
Company’s quality system processes and procedures are for its PIC®
MCUs and dsPIC® DSCs, KEELOQ® code hopping devices, Serial
EEPROMs, microperipherals, nonvolatile memory and analog
products. In addition, Microchip’s quality system for the design and
manufacture of development systems is ISO 9001:2000 certified.
DS39761B-page ii
Preliminary
© 2007 Microchip Technology Inc.
PIC18F2682/2685/4682/4685
28/40/44-Pin Enhanced Flash Microcontrollers with
ECAN™ Technology, 10-Bit A/D and nanoWatt Technology
Power-Managed Modes:
Peripheral Highlights:
• Run: CPU on, peripherals on
• Idle: CPU off, peripherals on
• High-Current Sink/source 25 mA/25 mA
• Three External Interrupts
• Sleep: CPU off, peripherals off
• Idle mode currents down to 5.8 μA typical
• Sleep mode currents down to 0.1 μA typical
• Timer1 Oscillator: 1.1 μA, 32 kHz, 2V
• Watchdog Timer: 2.1 μA
• One Capture/Compare/PWM (CCP1) module
• Enhanced Capture/Compare/PWM (ECCP1) module
(40/44-pin devices only):
- One, two or four PWM outputs
- Selectable polarity
• Two-Speed Oscillator Start-up
- Programmable dead time
- Auto-shutdown and auto-restart
• Master Synchronous Serial Port (MSSP) module
supporting 3-Wire SPI (all 4 modes) and I2C™
Master and Slave modes
• Enhanced Addressable USART module:
- Supports RS-485, RS-232 and LIN 1.3
- RS-232 operation using internal oscillator
block (no external crystal required)
- Auto-wake-up on Start bit
Flexible Oscillator Structure:
• Four Crystal modes, up to 40 MHz
• 4x Phase Lock Loop (PLL) – available for crystal
and internal oscillators
• Two External RC modes, up to 4 MHz
• Two External Clock modes, up to 40 MHz
• Internal Oscillator Block:
- 8 user-selectable frequencies, from 31 kHz to 8 MHz
- Provides a complete range of clock speeds,
from 31 kHz to 32 MHz when used with PLL
- User-tunable to compensate for frequency drift
• Secondary Oscillator using Timer1 @ 32 kHz
• Fail-Safe Clock Monitor
- Auto-Baud Detect
• 10-Bit, up to 11-Channel Analog-to-Digital
Converter module (A/D), up to 100 ksps:
- Auto-acquisition capability
- Conversion available during Sleep
• Dual Analog Comparators with Input Multiplexing
- Allows for safe shutdown if peripheral clock stops
Special Microcontroller Features:
• C compiler Optimized Architecture with optional
Extended Instruction Set
• 100,000 Erase/Write Cycle Enhanced Flash
Program Memory typical
• 1,000,000 Erase/Write Cycle Data EEPROM
Memory typical
• Flash/Data EEPROM Retention: > 40 years
• Self-Programmable under Software Control
• Priority Levels for Interrupts
• 8 x 8 Single-Cycle Hardware Multiplier
• Extended Watchdog Timer (WDT):
- Programmable period from 41 ms to 131s
• Single-Supply 5V In-Circuit Serial
Programming™ (ICSP™) via two pins
• In-Circuit Debug (ICD) via two pins
• Wide operating voltage range: 2.0V to 5.5V
ECAN Module Features:
• Message bit rates up to 1 Mbps
• Conforms to CAN 2.0B ACTIVE Specification
• Fully Backward Compatible with PIC18XXX8 CAN
modules
• Three Modes of Operation:
- Legacy, Enhanced Legacy, FIFO
• Three Dedicated Transmit Buffers with Prioritization
• Two Dedicated Receive Buffers
• Six Programmable Receive/Transmit Buffers
• Three Full, 29-Bit Acceptance Masks
• 16 Full, 29-Bit Acceptance Filters w/Dynamic
Association
• DeviceNet™ Data Byte Filter Support
• Automatic Remote Frame Handling
• Advanced Error Management Features
Program Memory
Data Memory
MSSP
CCP1/
10-Bit
A/D (ch)
Timers
8/16-bit
Device
I/O
ECCP1
(PWM)
Comp.
Flash # Single-Word SRAM EEPROM
(bytes) Instructions (bytes) (bytes)
Master
I C™
SPI
2
PIC18F2682
PIC18F2685
PIC18F4682
PIC18F4685
80K
96K
80K
96K
40960
49152
40960
49152
3328
3328
3328
3328
1024
1024
1024
1024
28
28
8
8
1/0
1/0
1/1
1/1
Y
Y
Y
Y
Y
Y
Y
Y
1
1
1
1
0
0
2
2
1/3
1/3
1/3
1/3
40/44
40/44
11
11
© 2007 Microchip Technology Inc.
Preliminary
DS39761B-page 1
PIC18F2682/2685/4682/4685
Pin Diagrams
28-Pin PDIP, SOIC
1
28
27
26
25
24
23
22
21
20
19
18
17
16
15
RB7/KBI3/PGD
RB6/KBI2/PGC
RB5/KBI1/PGM
RB4/KBI0/AN9
RB3/CANRX
RB2/INT2/CANTX
RB1/INT1/AN8
RB0/INT0/AN10
VDD
MCLR/VPP/RE3
RA0/AN0
2
3
4
5
RA1/AN1
RA2/AN2/VREF-
RA3/AN3/VREF+
RA4/T0CKI
6
7
8
9
10
11
RA5/AN4/SS/HLVDIN
VSS
OSC1/CLKI/RA7
OSC2/CLKO/RA6
RC0/T1OSO/T13CKI
RC1/T1OSI
VSS
RC7/RX/DT
RC6/TX/CK
RC5/SDO
12
13
14
RC2/CCP1
RC3/SCK/SCL
RC4/SDI/SDA
40-Pin PDIP
MCLR/VPP/RE3
RA0/AN0/CVREF
1
2
3
4
5
6
7
8
RB7/KBI3/PGD
RB6/KBI2/PGC
RB5/KBI1/PGM
RB4/KBI0/AN9
RB3/CANRX
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
RA1/AN1
RA2/AN2/VREF-
RA3/AN3/VREF+
RA4/T0CKI
RB2/INT2/CANTX
RA5/AN4/SS/HLVDIN
RE0/RD/AN5
RE1/WR/AN6/C1OUT
RE2/CS/AN7/C2OUT
VDD
RB1/INT1/AN8
RB0/INT0/FLT0/AN10
VDD
VSS
RD7/PSP7/P1D
RD6/PSP6/P1C
RD5/PSP5/P1B
RD4/PSP4/ECCP1/P1A
9
10
11
12
13
14
15
16
17
18
19
20
VSS
OSC1/CLKI/RA7
OSC2/CLKO/RA6
RC0/T1OSO/T13CKI
RC1/T1OSI
RC7/RX/DT
RC6/TX/CK
RC5/SDO
RC2/CCP1
RC3/SCK/SCL
RD0/PSP0/C1IN+
RD1/PSP1/C1IN-
RC4/SDI/SDA
RD3/PSP3/C2IN-
RD2/PSP2/C2IN+
Note:
Pinouts are subject to change.
DS39761B-page 2
Preliminary
© 2007 Microchip Technology Inc.
PIC18F2682/2685/4682/4685
Pin Diagrams (Continued)
44-Pin TQFP
33
32
31
30
29
28
27
26
25
24
23
1
NC
RC7/RX/DT
RD4/PSP4/ECCP1/P1A
RD5/PSP5/P1B
RC0/T1OSO/T13CKI
OSC2/CLKO/RA6
OSC1/CLKI/RA7
VSS
2
3
4
5
6
RD6/PSP6/P1C
RD7/PSP7/P1D
VSS
PIC18F4682
PIC18F4685
VDD
RE2/CS/AN7/C2OUT
RE1/WR/AN6/C1OUT
RE0/RD/AN5
RA5/AN4/SS/HLVDIN
RA4/T0CKI
7
VDD
8
RB0/INT0/FLT0/AN10
RB1/INT1/AN8
RB2/INT2/CANTX
RB3/CANRX
9
10
11
44-Pin QFN
1
2
3
4
5
6
7
8
9
33
OSC2/CLKO/RA6
OSC1/CLKI/RA7
VSS
RC7/RX/DT
RD4/PSP4/ECCP1/P1A
32
31
30
29
28
27
26
25
24
23
RD5/PSP5/P1B
RD6/PSP6/P1C
RD7/PSP7/P1D
AVSS
VDD
AVDD
PIC18F4682
PIC18F4685
VSS
AVDD
VDD
RE2/CS/AN7/C2OUT
RE1/WR/AN6/C1OUT
RE0/RD/AN5
RA5/AN4/SS/HLVDIN
RA4/T0CKI
RB0/INT0/FLT0/AN10
RB1/INT1/AN8
10
11
RB2/INT2/CANTX
Note:
Pinouts are subject to change.
© 2007 Microchip Technology Inc.
Preliminary
DS39761B-page 3
PIC18F2682/2685/4682/4685
Table of Contents
1.0 Device Overview .......................................................................................................................................................................... 7
2.0 Oscillator Configurations ............................................................................................................................................................ 23
3.0 Power-Managed Modes ............................................................................................................................................................. 33
4.0 Reset.......................................................................................................................................................................................... 41
5.0 Memory Organization................................................................................................................................................................. 61
6.0 Flash Program Memory.............................................................................................................................................................. 95
7.0 Data EEPROM Memory ........................................................................................................................................................... 105
8.0 8 x 8 Hardware Multiplier.......................................................................................................................................................... 111
9.0 Interrupts .................................................................................................................................................................................. 113
10.0 I/O Ports ................................................................................................................................................................................... 129
11.0 Timer0 Module ......................................................................................................................................................................... 147
12.0 Timer1 Module ......................................................................................................................................................................... 151
13.0 Timer2 Module ......................................................................................................................................................................... 157
14.0 Timer3 Module ......................................................................................................................................................................... 159
15.0 Capture/Compare/PWM (CCP1) Modules ............................................................................................................................... 163
16.0 Enhanced Capture/Compare/PWM (ECCP1) Module.............................................................................................................. 173
17.0 Master Synchronous Serial Port (MSSP) Module .................................................................................................................... 187
18.0 Enhanced Universal Synchronous Receiver Transmitter (EUSART)....................................................................................... 227
19.0 10-Bit Analog-to-Digital Converter (A/D) Module ..................................................................................................................... 247
20.0 Comparator Module.................................................................................................................................................................. 257
21.0 Comparator Voltage Reference Module................................................................................................................................... 263
22.0 High/Low-Voltage Detect (HLVD)............................................................................................................................................. 267
23.0 ECAN™ Technology ................................................................................................................................................................ 273
24.0 Special Features of the CPU.................................................................................................................................................... 343
25.0 Instruction Set Summary.......................................................................................................................................................... 363
26.0 Development Support............................................................................................................................................................... 413
27.0 Electrical Characteristics.......................................................................................................................................................... 417
28.0 DC and AC Characteristics Graphs and Tables....................................................................................................................... 453
29.0 Packaging Information.............................................................................................................................................................. 455
Appendix A: Revision History............................................................................................................................................................. 463
Appendix B: Device Differences......................................................................................................................................................... 463
Appendix C: Conversion Considerations ........................................................................................................................................... 464
Appendix D: Migration From Baseline to Enhanced Devices............................................................................................................. 464
Appendix E: Migration from Mid-Range to Enhanced Devices .......................................................................................................... 465
Appendix F: Migration from High-End to Enhanced Devices............................................................................................................. 465
Index .................................................................................................................................................................................................. 467
The Microchip Web Site..................................................................................................................................................................... 479
Customer Change Notification Service .............................................................................................................................................. 479
Customer Support.............................................................................................................................................................................. 479
Reader Response .............................................................................................................................................................................. 480
PIC18F2682/2685/4682/4685 Product Identification System ............................................................................................................ 481
DS39761B-page 4
Preliminary
© 2007 Microchip Technology Inc.
PIC18F2682/2685/4682/4685
TO OUR VALUED CUSTOMERS
It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip
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If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via
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The last character of the literature number is the version number, (e.g., DS30000A is version A of document DS30000).
Errata
An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current
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To determine if an errata sheet exists for a particular device, please check with one of the following:
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© 2007 Microchip Technology Inc.
Preliminary
DS39761B-page 5
PIC18F2682/2685/4682/4685
NOTES:
DS39761B-page 6
Preliminary
© 2007 Microchip Technology Inc.
PIC18F2682/2685/4682/4685
1.1.2
MULTIPLE OSCILLATOR OPTIONS
AND FEATURES
1.0
DEVICE OVERVIEW
This document contains device-specific information for
the following devices:
All of the devices in the PIC18F2682/2685/4682/4685
family offer ten different oscillator options, allowing
users a wide range of choices in developing application
hardware. These options include:
• PIC18F2682
• PIC18F2685
• PIC18F4682
• PIC18F4685
• Four Crystal modes, using crystals or ceramic
resonators
This family of devices offers the advantages of all PIC18
• Two External Clock modes, offering the option of
using two pins (oscillator input and a divide-by-4
clock output) or one pin (oscillator input, with the
second pin reassigned as general I/O)
microcontrollers
–
namely, high computational
performance at an economical price – with the addition
of high-endurance, Enhanced Flash program memory.
In addition to these features, the PIC18F2682/2685/
4682/4685 family introduces design enhancements that
make these microcontrollers a logical choice for many
high-performance, power sensitive applications.
• Two External RC Oscillator modes with the same
pin options as the External Clock modes
• An internal oscillator block which provides an
8 MHz clock ( 2% accuracy) and an INTRC
source (approximately 31 kHz, stable over
temperature and VDD), as well as a range of
6 user selectable clock frequencies, between
125 kHz to 4 MHz, for a total of 8 clock
1.1
New Core Features
1.1.1
nanoWatt TECHNOLOGY
frequencies. This option frees the two oscillator
pins for use as additional general purpose I/O.
All of the devices in the PIC18F2682/2685/4682/4685
family incorporate a range of features that can signifi-
cantly reduce power consumption during operation.
Key items include:
• A Phase Lock Loop (PLL) frequency multiplier,
available to both the High-Speed Crystal and
Internal Oscillator modes, which allows clock
speeds of up to 40 MHz. Used with the internal
oscillator, the PLL gives users a complete
selection of clock speeds, from 31 kHz to
32 MHz – all without using an external crystal or
clock circuit.
• Alternate Run Modes: By clocking the controller
from the Timer1 source or the internal oscillator
block, power consumption during code execution
can be reduced by as much as 90%.
• Multiple Idle Modes: The controller can also run
with its CPU core disabled but the peripherals still
active. In these states, power consumption can be
reduced even further, to as little as 4% of normal
operation requirements.
Besides its availability as a clock source, the internal
oscillator block provides a stable reference source that
gives the family additional features for robust
operation:
• On-the-Fly Mode Switching: The power-
managed modes are invoked by user code during
operation, allowing the user to incorporate
power-saving ideas into their application’s
software design.
• Fail-Safe Clock Monitor: This option constantly
monitors the main clock source against a refer-
ence signal provided by the internal oscillator. If a
clock failure occurs, the controller is switched to
the internal oscillator block, allowing for continued
low-speed operation or a safe application
shutdown.
• Lower Consumption in Key Modules: The
power requirements for both Timer1 and the
Watchdog Timer have been reduced by up to
80%, with typical values of 1.1 and 2.1 μA,
respectively.
• Two-Speed Start-up: This option allows the
internal oscillator to serve as the clock source
from Power-on Reset, or wake-up from Sleep
mode, until the primary clock source is available.
• Extended Instruction Set: In addition to the
standard 75 instructions of the PIC18 instruction
set, PIC18F2682/2685/4682/4685 devices also
provide an optional extension to the core CPU
functionality. The added features include eight
additional instructions that augment indirect and
indexed addressing operations and the
implementation of Indexed Literal Offset
Addressing mode for many of the standard PIC18
instructions.
© 2007 Microchip Technology Inc.
Preliminary
DS39761B-page 7
PIC18F2682/2685/4682/4685
1.2
Other Special Features
1.3
Details on Individual Family
Members
• Memory Endurance: The Enhanced Flash cells
for both program memory and data EEPROM are
rated to last for many thousands of erase/write
cycles – up to 100,000 for program memory and
1,000,000 for EEPROM. Data retention without
refresh is conservatively estimated to be greater
than 40 years.
Devices in the PIC18F2682/2685/4682/4685 family are
available in 28-pin (PIC18F2682/2685) and 40/44-pin
(PIC18F4682/4685) packages. Block diagrams for the
two groups are shown in Figure 1-1 and Figure 1-2.
The devices are differentiated from each other in six
ways:
• Self-Programmability: These devices can write
to their own program memory spaces under inter-
nal software control. By using a bootloader rou-
tine located in the protected Boot Block at the top
of program memory, it becomes possible to create
an application that can update itself in the field.
1. Flash program memory (80 Kbytes for
PIC18F2682/4682 devices, 96 Kbytes for
PIC18F2685/4685 devices).
2. A/D channels (8 for PIC18F2682/2685 devices,
11 for PIC18F4682/4685 devices).
3. I/O ports (3 bidirectional ports and 1 input only
• Extended Instruction Set: The PIC18F2682/
2685/4682/4685 family introduces an optional
extension to the PIC18 instruction set, which adds
8 new instructions and an Indexed Addressing
mode. This extension, enabled as a device con-
figuration option, has been specifically designed
to optimize re-entrant application code originally
developed in high-level languages, such as C.
port
on
PIC18F2682/2685
devices,
5 bidirectional ports on PIC18F4682/4685
devices).
4. CCP1 and Enhanced CCP1 implementation
(PIC18F2682/2685 devices have 1 standard
CCP1 module, PIC18F4682/4685 devices have
one standard CCP1 module and one ECCP1
module).
• Enhanced CCP1 Module: In PWM mode, this
module provides 1, 2 or 4 modulated outputs for
controlling half-bridge and full-bridge drivers.
Other features include auto-shutdown, for
disabling PWM outputs on interrupt or other select
conditions, and auto-restart to reactivate outputs
once the condition has cleared.
5. Parallel Slave Port (present only on
PIC18F4682/4685 devices).
6. PIC18F4682/4685
comparators.
devices
provide
two
All other features for devices in this family are identical.
These are summarized in Table 1-1.
• Enhanced Addressable USART: This serial
communication module is capable of standard
RS-232 operation and provides support for the LIN
bus protocol. Other enhancements include
Auto-Baud Rate Detection and a 16-bit Baud Rate
Generator for improved resolution. When the
microcontroller is using the internal oscillator
block, the EUSART provides stable operation for
applications that talk to the outside world without
using an external crystal (or its accompanying
power requirement).
The pinouts for all devices are listed in Table 1-2 and
Table 1-3.
Like all Microchip PIC18 devices, members of the
PIC18F2682/2685/4682/4685 family are available as
both standard and low-voltage devices. Standard
devices with Enhanced Flash memory, designated with
an “F” in the part number (such as PIC18F2685),
accommodate an operating VDD range of 4.2V to 5.5V.
Low-voltage parts, designated by “LF” (such as
PIC18LF2685), function over an extended VDD range
of 2.0V to 5.5V.
• 10-Bit A/D Converter: This module incorporates
programmable acquisition time, allowing for a
channel to be selected and a conversion to be
initiated without waiting for a sampling period and
thus, reduce code overhead.
• Extended Watchdog Timer (WDT): This
enhanced version incorporates a 16-bit prescaler,
allowing a time-out range from 4 ms to over
131 seconds, that is stable across operating
voltage and temperature.
DS39761B-page 8
Preliminary
© 2007 Microchip Technology Inc.
PIC18F2682/2685/4682/4685
TABLE 1-1:
DEVICE FEATURES
Features
PIC18F2682
PIC18F2685
PIC18F4682
PIC18F4685
Operating Frequency
Program Memory (Bytes)
Program Memory (Instructions)
Data Memory (Bytes)
Data EEPROM Memory (Bytes)
Interrupt Sources
DC – 40 MHz
DC – 40 MHz
96K
DC – 40 MHz
80K
DC – 40 MHz
96K
80K
40960
49152
3328
40960
3328
49152
3328
3328
1024
1024
1024
1024
19
19
20
20
I/O Ports
Ports A, B, C, (E)
Ports A, B, C, (E) Ports A, B, C, D, E Ports A, B, C, D, E
Timers
4
1
0
4
1
0
4
1
1
4
1
1
Capture/Compare/PWM Modules
Enhanced Capture/
Compare/PWM Modules
ECAN Module
1
1
1
1
Serial Communications
MSSP,
MSSP,
MSSP,
MSSP,
Enhanced USART Enhanced USART Enhanced USART Enhanced USART
Parallel Slave Port
No
No
Yes
Yes
Communications (PSP)
10-bit Analog-to-Digital Module
Comparators
8 Input Channels
8 Input Channels 11 Input Channels 11 Input Channels
0
0
2
2
Resets (and Delays)
POR, BOR,
POR, BOR,
POR, BOR,
POR, BOR,
RESETInstruction, RESETInstruction, RESETInstruction, RESETInstruction,
Stack Full,
Stack Underflow
(PWRT, OST),
MCLR (optional),
WDT
Stack Full,
Stack Underflow
(PWRT, OST),
MCLR (optional),
WDT
Stack Full,
Stack Underflow
(PWRT, OST),
MCLR (optional),
WDT
Stack Full,
Stack Underflow
(PWRT, OST),
MCLR (optional),
WDT
Programmable High/Low-Voltage
Detect
Yes
Yes
Yes
Yes
Programmable Brown-out Reset
Instruction Set
Yes
Yes
Yes
Yes
75 Instructions;
83 with Extended
Instruction Set
Enabled
75 Instructions;
83 with Extended
Instruction Set
Enabled
75 Instructions;
83 with Extended
Instruction Set
Enabled
75 Instructions;
83 with Extended
Instruction Set
Enabled
Packages
28-pin PDIP
28-pin SOIC
28-pin PDIP
28-pin SOIC
40-pin PDIP
44-pin QFN
44-pin TQFP
40-pin PDIP
44-pin QFN
44-pin TQFP
© 2007 Microchip Technology Inc.
Preliminary
DS39761B-page 9
PIC18F2682/2685/4682/4685
FIGURE 1-1:
PIC18F2682/2685 (28-PIN) BLOCK DIAGRAM
Data Bus<8>
Table Pointer<21>
Data Latch
PORTA
8
8
inc/dec logic
21
RA0/AN0
RA1/AN1
Data Memory
(3.3 Kbytes)
RA2/AN2/VREF-
RA3/AN3/VREF+
RA4/T0CKI
RA5/AN4/SS/HLVDIN
OSC2/CLKO/RA6
OSC1/CLKI/RA7
PCLATU PCLATH
Address Latch
20
PCU PCH PCL
Program Counter
12
Data Address<12>
31 Level Stack
STKPTR
4
BSR
12
FSR0
FSR1
FSR2
4
Address Latch
Access
Bank
Program Memory
(80/96 Kbytes)
12
Data Latch
PORTB
RB0/INT0/AN10
RB1/INT1/AN8
RB2/INT2/CANTX
RB3/CANRX
inc/dec
logic
8
Table Latch
RB4/KBI0/AN9
RB5/KBI1/PGM
RB6/KBI2/PGC
RB7/KBI3/PGD
Address
Decode
ROM Latch
IR
Instruction Bus <16>
8
State Machine
Control Signals
Instruction
Decode &
Control
PRODH PRODL
8 x 8 Multiply
PORTC
RC0/T1OSO/T13CKI
RC1/T1OSI
3
8
RC2/CCP1
RC3/SCK/SCL
RC4/SDI/SDA
BITOP
8
W
8
8
RC5/SDO
RC6/TX/CK
RC7/RX/DT
Internal
OSC1(2)
OSC2(2)
T1OSI
Power-up
Timer
Oscillator
Block
8
8
Oscillator
Start-up Timer
ALU<8>
8
INTRC
Oscillator
Power-on
Reset
8 MHz
Oscillator
Watchdog
Timer
T1OSO
Band Gap
Reference
Brown-out
Reset
MCLR(1)
VDD, VSS
Single-Supply
Programming
In-Circuit
Debugger
PORTE
Fail-Safe
Clock Monitor
MCLR/VPP/RE3(1)
Data
EEPROM
BOR
HLVD
Timer0
ECCP1
Timer1
MSSP
Timer2
Timer3
ADC
10-bit
CCP1
EUSART
ECAN™
Note 1: RE3 is multiplexed with MCLR and is only available when the MCLR Resets are disabled.
2: OSC1/CLKI and OSC2/CLKO are only available in select oscillator modes and when these pins are not being used as digital I/O.
Refer to Section 2.0 “Oscillator Configurations” for additional information.
DS39761B-page 10
Preliminary
© 2007 Microchip Technology Inc.
PIC18F2682/2685/4682/4685
FIGURE 1-2:
PIC18F4682/4685 (40/44-PIN) BLOCK DIAGRAM
Data Bus<8>
PORTA
Table Pointer<21>
RA0/AN0/CVREF
RA1/AN1
RA2/AN2/VREF-
RA3/AN3/VREF+
RA4/T0CKI
Data Latch
8
8
inc/dec logic
21
Data Memory
(3.3 Kbytes)
PCLATU PCLATH
RA5/AN4/SS/HLVDIN
OSC2/CLKO/RA6
OSC1/CLKI/RA7
Address Latch
20
PCU PCH PCL
Program Counter
12
Data Address<12>
PORTB
31 Level Stack
STKPTR
RB0/INT0/FLT0/AN10
RB1/INT1/AN8
RB2/INT2/CANTX
RB3/CANRX
RB4/KBI0/AN9
RB5/KBI1/PGM
RB6/KBI2/PGC
RB7/KBI3/PGD
4
BSR
12
4
Address Latch
Access
Bank
FSR0
FSR1
FSR2
Program Memory
(80/96 Kbytes)
12
Data Latch
inc/dec
logic
8
Table Latch
PORTC
Address
Decode
ROM Latch
IR
RC0/T1OSO/T13CKI
RC1/T1OSI
Instruction Bus <16>
RC2/CCP1
RC3/SCK/SCL
RC4/SDI/SDA
RC5/SDO
8
RC6/TX/CK
State Machine
Control Signals
Instruction
Decode &
Control
RC7/RX/DT
PRODH PRODL
8 x 8 Multiply
PORTD
RD0/PSP0/C1IN+
RD1/PSP1/C1IN-
RD2/PSP2/C2IN+
RD3/PSP3/C2IN-
RD4/PSP4/ECCP1/P1A
RD5/PSP5/P1B
3
8
BITOP
8
W
8
8
Internal
Oscillator
Block
OSC1(2)
OSC2(2)
T1OSI
Power-up
Timer
8
8
RD6/PSP6/P1C
RD7/PSP7/P1D
Oscillator
Start-up Timer
ALU<8>
8
INTRC
Oscillator
Power-on
Reset
8 MHz
Oscillator
Watchdog
Timer
T1OSO
PORTE
RE0/RD/AN5
Band Gap
Reference
Brown-out
Reset
Fail-Safe
RE1/WR/AN6/C1OUT
RE2/CS/AN7/C2OUT
MCLR/VPP/RE3(1)
MCLR(1)
VDD, VSS
Single-Supply
Programming
In-Circuit
Debugger
Clock Monitor
Data
EEPROM
BOR
HLVD
Timer0
ECCP1
Timer1
MSSP
Timer2
Timer3
ADC
10-bit
Comparator
CCP1
EUSART
ECAN™
Note 1: RE3 is multiplexed with MCLR and is only available when the MCLR Resets are disabled.
2: OSC1/CLKI and OSC2/CLKO are only available in select oscillator modes and when these pins are not being used as digital I/O.
Refer to Section 2.0 “Oscillator Configurations” for additional information.
© 2007 Microchip Technology Inc.
Preliminary
DS39761B-page 11
PIC18F2682/2685/4682/4685
TABLE 1-2:
PIC18F2682/2685 PINOUT I/O DESCRIPTIONS
Pin
Number
Pin Buffer
Type Type
Pin Name
Description
PDIP,
SOIC
MCLR/VPP/RE3
MCLR
1
9
Master Clear (input) or programming voltage (input).
Master Clear (Reset) input. This pin is an active-low
Reset to the device.
I
ST
ST
VPP
RE3
P
I
Programming voltage input.
Digital input.
OSC1/CLKI/RA7
OSC1
Oscillator crystal or external clock input.
I
I
ST
CMOS
TTL
Oscillator crystal input or external clock source input.
ST buffer when configured in RC mode; CMOS otherwise.
External clock source input. Always associated with pin
function OSC1. (See related OSC2/CLKO pin.)
General purpose I/O pin.
CLKI
RA7
I/O
OSC2/CLKO/RA6
OSC2
10
Oscillator crystal or clock output.
O
O
—
—
Oscillator crystal output. Connects to crystal or resonator in
Crystal Oscillator mode.
In RC mode, OSC2 pin outputs CLKO which has 1/4 the
frequency of OSC1 and denotes the instruction cycle rate.
General purpose I/O pin.
CLKO
RA6
I/O
TTL
Legend: TTL = TTL compatible input
ST = Schmitt Trigger input with CMOS levels
= Output
CMOS = CMOS compatible input or output
I
= Input
O
P
= Power
DS39761B-page 12
Preliminary
© 2007 Microchip Technology Inc.
PIC18F2682/2685/4682/4685
TABLE 1-2:
PIC18F2682/2685 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin
Number
Pin Buffer
Type Type
Pin Name
Description
PDIP,
SOIC
PORTA is a bidirectional I/O port.
RA0/AN0
RA0
2
3
4
I/O
I
TTL
Analog
Digital I/O.
Analog input 0.
AN0
RA1/AN1
RA1
I/O
I
TTL
Analog
Digital I/O.
Analog input 1.
AN1
RA2/AN2/VREF-
RA2
I/O
TTL
Digital I/O.
AN2
VREF-
I
I
Analog
Analog
Analog input 2.
A/D reference voltage (low) input.
RA3/AN3/VREF+
RA3
5
I/O
TTL
Digital I/O.
AN3
VREF+
I
I
Analog
Analog
Analog input 3.
A/D reference voltage (high) input.
RA4/T0CKI
RA4
6
7
I/O
I
TTL
ST
Digital I/O.
Timer0 external clock input.
T0CKI
RA5/AN4/SS/HLVDIN
RA5
AN4
SS
HLVDIN
I/O
TTL
Analog
TTL
Digital I/O.
Analog input 4.
SPI slave select input.
High/Low-Voltage Detect input.
I
I
I
Analog
RA6
RA7
See the OSC2/CLKO/RA6 pin.
See the OSC1/CLKI/RA7 pin.
Legend: TTL = TTL compatible input
ST = Schmitt Trigger input with CMOS levels
= Output
CMOS = CMOS compatible input or output
I
= Input
O
P
= Power
© 2007 Microchip Technology Inc.
Preliminary
DS39761B-page 13
PIC18F2682/2685/4682/4685
TABLE 1-2:
PIC18F2682/2685 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin
Number
Pin Buffer
Type Type
Pin Name
Description
PDIP,
SOIC
PORTB is a bidirectional I/O port. PORTB can be software
programmed for internal weak pull-ups on all inputs.
RB0/INT0/AN10
RB0
21
22
23
I/O
I
I
TTL
ST
Analog
Digital I/O.
External interrupt 0.
Analog input 10.
INT0
AN10
RB1/INT1/AN8
RB1
I/O
I
I
TTL
ST
Analog
Digital I/O.
External interrupt 1.
Analog input 8.
INT1
AN8
RB2/INT2/CANTX
RB2
I/O
I
O
TTL
ST
TTL
Digital I/O.
External interrupt 2.
CAN bus TX.
INT2
CANTX
RB3/CANRX
RB3
24
25
I/O
I
TTL
TTL
Digital I/O.
CAN bus RX.
CANRX
RB4/KBI0/AN9
RB4
I/O
I
I
TTL
TTL
Analog
Digital I/O.
Interrupt-on-change pin.
Analog input 9.
KBI0
AN9
RB5/KBI1/PGM
RB5
26
27
28
I/O
I
I/O
TTL
TTL
ST
Digital I/O.
Interrupt-on-change pin.
Low-Voltage ICSP™ Programming enable pin.
KBI1
PGM
RB6/KBI2/PGC
RB6
I/O
I
I/O
TTL
TTL
ST
Digital I/O.
Interrupt-on-change pin.
In-Circuit Debugger and ICSP programming clock pin.
KBI2
PGC
RB7/KBI3/PGD
RB7
I/O
I
I/O
TTL
TTL
ST
Digital I/O.
Interrupt-on-change pin.
In-Circuit Debugger and ICSP programming data pin.
KBI3
PGD
Legend: TTL = TTL compatible input
ST = Schmitt Trigger input with CMOS levels
= Output
CMOS = CMOS compatible input or output
I
= Input
O
P
= Power
DS39761B-page 14
Preliminary
© 2007 Microchip Technology Inc.
PIC18F2682/2685/4682/4685
TABLE 1-2:
PIC18F2682/2685 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin
Number
Pin Buffer
Type Type
Pin Name
Description
PDIP,
SOIC
PORTC is a bidirectional I/O port.
RC0/T1OSO/T13CKI
RC0
11
I/O
O
I
ST
—
ST
Digital I/O.
Timer1 oscillator output.
Timer1/Timer3 external clock input.
T1OSO
T13CKI
RC1/T1OSI
RC1
12
13
14
I/O
I
ST
CMOS
Digital I/O.
Timer1 oscillator input.
T1OSI
RC2/CCP1
RC2
I/O
I/O
ST
ST
Digital I/O.
CCP1
Capture1 input/Compare1 output/PWM1 output.
RC3/SCK/SCL
RC3
I/O
I/O
I/O
ST
ST
ST
Digital I/O.
SCK
SCL
Synchronous serial clock input/output for SPI mode.
Synchronous serial clock input/output for I2C™ mode.
RC4/SDI/SDA
RC4
15
I/O
I
I/O
ST
ST
ST
Digital I/O.
SDI
SDA
SPI data in.
I2C data I/O.
RC5/SDO
RC5
16
17
I/O
O
ST
—
Digital I/O.
SPI data out.
SDO
RC6/TX/CK
RC6
TX
CK
I/O
O
I/O
ST
—
ST
Digital I/O.
EUSART asynchronous transmit.
EUSART synchronous clock (see related RX/DT).
RC7/RX/DT
RC7
18
I/O
I
I/O
ST
ST
ST
Digital I/O.
RX
DT
EUSART asynchronous receive.
EUSART synchronous data (see related TX/CK).
RE3
VSS
VDD
—
8, 19
20
—
P
—
—
—
See MCLR/VPP/RE3 pin.
Ground reference for logic and I/O pins.
Positive supply for logic and I/O pins.
CMOS = CMOS compatible input or output
P
Legend: TTL = TTL compatible input
ST = Schmitt Trigger input with CMOS levels
= Output
I
= Input
O
P
= Power
© 2007 Microchip Technology Inc.
Preliminary
DS39761B-page 15
PIC18F2682/2685/4682/4685
TABLE 1-3:
Pin Name
PIC18F4682/4685 PINOUT I/O DESCRIPTIONS
Pin Number
Pin Buffer
Type Type
Description
PDIP QFN TQFP
MCLR/VPP/RE3
MCLR
1
18
18
Master Clear (input) or programming voltage (input).
Master Clear (Reset) input. This pin is an
active-low Reset to the device.
Programming voltage input.
I
ST
VPP
RE3
P
I
ST
ST
Digital input.
OSC1/CLKI/RA7
OSC1
13
32
30
Oscillator crystal or external clock input.
Oscillator crystal input or external clock source input.
ST buffer when configured in RC mode;
CMOS otherwise.
I
CLKI
RA7
I
CMOS
TTL
External clock source input. Always associated with
pin function OSC1. (See related OSC2/CLKO pin.)
General purpose I/O pin.
I/O
OSC2/CLKO/RA6
OSC2
14
33
31
Oscillator crystal or clock output.
Oscillator crystal output. Connects to crystal or
resonator in Crystal Oscillator mode.
In RC mode, OSC2 pin outputs CLKO which has 1/4
the frequency of OSC1 and denotes the instruction
cycle rate.
O
O
—
—
CLKO
RA6
I/O
TTL
General purpose I/O pin.
Legend: TTL = TTL compatible input
ST = Schmitt Trigger input with CMOS levels
= Output
CMOS = CMOS compatible input or output
I
= Input
O
P
= Power
DS39761B-page 16
Preliminary
© 2007 Microchip Technology Inc.
PIC18F2682/2685/4682/4685
TABLE 1-3:
Pin Name
PIC18F4682/4685 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number
Pin Buffer
Type Type
Description
PDIP QFN TQFP
PORTA is a bidirectional I/O port.
RA0/AN0/CVREF
RA0
2
19
19
I/O
I
O
TTL
Analog
Analog
Digital I/O.
Analog input 0.
Analog comparator reference output.
AN0
CVREF
RA1/AN1
RA1
3
4
20
21
20
21
I/O
I
TTL
Analog
Digital I/O.
Analog input 1.
AN1
RA2/AN2/VREF-
RA2
I/O
TTL
Digital I/O.
AN2
VREF-
I
I
Analog
Analog
Analog input 2.
A/D reference voltage (low) input.
RA3/AN3/VREF+
RA3
5
22
22
I/O
TTL
Digital I/O.
AN3
VREF+
I
I
Analog
Analog
Analog input 3.
A/D reference voltage (high) input.
RA4/T0CKI
RA4
6
7
23
24
23
24
I/O
I
TTL
ST
Digital I/O.
Timer0 external clock input.
T0CKI
RA5/AN4/SS/HLVDIN
RA5
AN4
SS
HLVDIN
I/O
TTL
Analog
TTL
Digital I/O.
Analog input 4.
SPI slave select input.
High/Low-Voltage Detect input.
I
I
I
Analog
RA6
RA7
See the OSC2/CLKO/RA6 pin.
See the OSC1/CLKI/RA7 pin.
Legend: TTL = TTL compatible input
ST = Schmitt Trigger input with CMOS levels
= Output
CMOS = CMOS compatible input or output
I
= Input
O
P
= Power
© 2007 Microchip Technology Inc.
Preliminary
DS39761B-page 17
PIC18F2682/2685/4682/4685
TABLE 1-3:
Pin Name
PIC18F4682/4685 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number
Pin Buffer
Type Type
Description
PDIP QFN TQFP
PORTB is a bidirectional I/O port. PORTB can be
software programmed for internal weak pull-ups on all
inputs.
RB0/INT0/FLT0/AN10
33
9
8
RB0
I/O
TTL
ST
ST
Digital I/O.
External interrupt 0.
Enhanced PWM Fault input (ECCP1 module).
Analog input 10.
INT0
FLT0
AN10
I
I
I
Analog
RB1/INT1/AN8
RB1
34
35
10
11
9
I/O
I
I
TTL
ST
Analog
Digital I/O.
External interrupt 1.
Analog input 8.
INT1
AN8
RB2/INT2/CANTX
RB2
10
I/O
I
O
TTL
ST
TTL
Digital I/O.
External interrupt 2.
CAN bus TX.
INT2
CANTX
RB3/CANRX
RB3
36
37
12
14
11
14
I/O
I
TTL
TTL
Digital I/O.
CAN bus RX.
CANRX
RB4/KBI0/AN9
RB4
I/O
I
I
TTL
TTL
Analog
Digital I/O.
Interrupt-on-change pin.
Analog input 9.
KBI0
AN9
RB5/KBI1/PGM
RB5
38
39
15
16
15
16
I/O
I
I/O
TTL
TTL
ST
Digital I/O.
Interrupt-on-change pin.
Low-Voltage ICSP™ Programming enable pin.
KBI1
PGM
RB6/KBI2/PGC
RB6
I/O
I
I/O
TTL
TTL
ST
Digital I/O.
KBI2
PGC
Interrupt-on-change pin.
In-Circuit Debugger and ICSP programming
clock pin.
RB7/KBI3/PGD
RB7
40
17
17
I/O
I
I/O
TTL
TTL
ST
Digital I/O.
KBI3
PGD
Interrupt-on-change pin.
In-Circuit Debugger and ICSP programming
data pin.
Legend: TTL = TTL compatible input
ST = Schmitt Trigger input with CMOS levels
= Output
CMOS = CMOS compatible input or output
I
= Input
O
P
= Power
DS39761B-page 18
Preliminary
© 2007 Microchip Technology Inc.
PIC18F2682/2685/4682/4685
TABLE 1-3:
Pin Name
PIC18F4682/4685 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number
Pin Buffer
Type Type
Description
PDIP QFN TQFP
PORTC is a bidirectional I/O port.
RC0/T1OSO/T13CKI
RC0
15
34
32
I/O
O
I
ST
—
ST
Digital I/O.
Timer1 oscillator output.
Timer1/Timer3 external clock input.
T1OSO
T13CKI
RC1/T1OSI
RC1
16
17
18
35
36
37
35
36
37
I/O
I
ST
CMOS
Digital I/O.
Timer1 oscillator input.
T1OSI
RC2/CCP1
RC2
I/O
I/O
ST
ST
Digital I/O.
CCP1
Capture1 input/Compare1 output/PWM1 output.
RC3/SCK/SCL
RC3
I/O
I/O
ST
ST
Digital I/O.
Synchronous serial clock input/output for
SPI mode.
SCK
SCL
I/O
ST
Synchronous serial clock input/output for
I2C™ mode.
RC4/SDI/SDA
RC4
23
42
42
I/O
I
I/O
ST
ST
ST
Digital I/O.
SPI data in.
I2C data I/O.
SDI
SDA
RC5/SDO
RC5
24
25
43
44
43
44
I/O
O
ST
—
Digital I/O.
SPI data out.
SDO
RC6/TX/CK
RC6
TX
CK
I/O
O
I/O
ST
—
ST
Digital I/O.
EUSART asynchronous transmit.
EUSART synchronous clock (see related RX/DT
pin).
RC7/RX/DT
RC7
26
1
1
I/O
I
I/O
ST
ST
ST
Digital I/O.
RX
DT
EUSART asynchronous receive.
EUSART synchronous data (see related TX/CK
pin).
Legend: TTL = TTL compatible input
ST = Schmitt Trigger input with CMOS levels
= Output
CMOS = CMOS compatible input or output
I
= Input
O
P
= Power
© 2007 Microchip Technology Inc.
Preliminary
DS39761B-page 19
PIC18F2682/2685/4682/4685
TABLE 1-3:
Pin Name
PIC18F4682/4685 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number
Pin Buffer
Type Type
Description
PDIP QFN TQFP
PORTD is a bidirectional I/O port or a Parallel Slave
Port (PSP) for interfacing to a microprocessor port.
These pins have TTL input buffers when PSP module
is enabled.
RD0/PSP0/C1IN+
RD0
19
20
21
22
27
38
39
40
41
2
38
39
40
41
2
I/O
I/O
I
ST
TTL
Analog
Digital I/O.
Parallel Slave Port data.
Comparator 1 input (+).
PSP0
C1IN+
RD1/PSP1/C1IN-
RD1
I/O
I/O
I
ST
TTL
Analog
Digital I/O.
Parallel Slave Port data.
Comparator 1 input (-)
PSP1
C1IN-
RD2/PSP2/C2IN+
RD2
I/O
I/O
I
ST
TTL
Analog
Digital I/O.
Parallel Slave Port data.
Comparator 2 input (+).
PSP2
C2IN+
RD3/PSP3/C2IN-
RD3
I/O
I/O
I
ST
TTL
Analog
Digital I/O.
Parallel Slave Port data.
Comparator 2 input (-).
PSP3
C2IN-
RD4/PSP4/ECCP1/
P1A
RD4
I/O
I/O
I/O
O
ST
TTL
ST
Digital I/O.
PSP4
ECCP1
P1A
Parallel Slave Port data.
Capture2 input/Compare2 output/PWM2 output.
ECCP1 PWM output A.
TTL
RD5/PSP5/P1B
RD5
28
29
30
3
4
5
3
4
5
I/O
I/O
O
ST
TTL
TTL
Digital I/O.
Parallel Slave Port data.
ECCP1 PWM output B.
PSP5
P1B
RD6/PSP6/P1C
RD6
I/O
I/O
O
ST
TTL
TTL
Digital I/O.
Parallel Slave Port data.
ECCP1 PWM output C.
PSP6
P1C
RD7/PSP7/P1D
RD7
I/O
I/O
O
ST
TTL
TTL
Digital I/O.
Parallel Slave Port data.
ECCP1 PWM output D.
PSP7
P1D
Legend: TTL = TTL compatible input
ST = Schmitt Trigger input with CMOS levels
= Output
CMOS = CMOS compatible input or output
I
= Input
O
P
= Power
DS39761B-page 20
Preliminary
© 2007 Microchip Technology Inc.
PIC18F2682/2685/4682/4685
TABLE 1-3:
Pin Name
PIC18F4682/4685 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number
Pin Buffer
Type Type
Description
PDIP QFN TQFP
PORTE is a bidirectional I/O port.
RE0/RD/AN5
RE0
8
9
25
26
25
26
I/O
I
ST
TTL
Digital I/O.
RD
Read control for Parallel Slave Port
(see also WR and CS pins).
Analog input 5.
AN5
I
Analog
RE1/WR/AN6/C1OUT
RE1
WR
I/O
I
ST
TTL
Digital I/O.
Write control for Parallel Slave Port
(see CS and RD pins).
Analog input 6.
AN6
C1OUT
I
O
Analog
TTL
Comparator 1 output.
RE2/CS/AN7/C2OUT
10
27
27
RE2
CS
I/O
I
ST
TTL
Digital I/O.
Chip select control for Parallel Slave Port
(see related RD and WR pins).
Analog input 7.
AN7
C2OUT
I
O
Analog
TTL
Comparator 2 output.
RE3
VSS
—
—
—
—
P
—
—
See MCLR/VPP/RE3 pin.
12, 6, 30, 6, 29
31 31
Ground reference for logic and I/O pins.
VDD
NC
11, 32 7, 8, 7, 28
28, 29
P
—
—
Positive supply for logic and I/O pins.
No connect.
—
13 12, 13,
33, 34
—
Legend: TTL = TTL compatible input
ST = Schmitt Trigger input with CMOS levels
= Output
CMOS = CMOS compatible input or output
I
= Input
O
P
= Power
© 2007 Microchip Technology Inc.
Preliminary
DS39761B-page 21
PIC18F2682/2685/4682/4685
NOTES:
DS39761B-page 22
Preliminary
© 2007 Microchip Technology Inc.
PIC18F2682/2685/4682/4685
FIGURE 2-1:
CRYSTAL/CERAMIC
RESONATOROPERATION
(XT, LP, HS OR HSPLL
CONFIGURATION)
2.0
2.1
OSCILLATOR
CONFIGURATIONS
Oscillator Types
(1)
C1
OSC1
PIC18F2682/2685/4682/4685 devices can be operated
in ten different oscillator modes. The user can program
the Configuration bits, FOSC3:FOSC0, in Configuration
Register 1H to select one of these ten modes:
To
Internal
Logic
(3)
RF
XTAL
1. LP
2. XT
3. HS
Low-Power Crystal
Sleep
(2)
RS
Crystal/Resonator
(1)
PIC18FXXXX
C2
OSC2
High-Speed Crystal/Resonator
Note 1:See Table 2-1 and Table 2-2 for initial values of
C1 and C2.
4. HSPLL High-Speed Crystal/Resonator
with PLL enabled
2: A series resistor (RS) may be required for AT
strip cut crystals.
3: RF varies with the oscillator mode chosen.
5. RC
External Resistor/Capacitor with
FOSC/4 output on RA6
6. RCIO
External Resistor/Capacitor with I/O
on RA6
7. INTIO1 Internal Oscillator with FOSC/4 output
on RA6 and I/O on RA7
TABLE 2-1:
CAPACITOR SELECTION FOR
CERAMIC RESONATORS
8. INTIO2 Internal Oscillator with I/O on RA6
and RA7
Typical Capacitor Values Used:
9. EC
External Clock with FOSC/4 output
External Clock with I/O on RA6
Mode
Freq
OSC1
OSC2
10. ECIO
XT
455 kHz
2.0 MHz
4.0 MHz
56 pF
47 pF
33 pF
56 pF
47 pF
33 pF
2.2
Crystal Oscillator/Ceramic
Resonators
HS
8.0 MHz
16.0 MHz
27 pF
22 pF
27 pF
22 pF
In XT, LP, HS or HSPLL Oscillator modes, a crystal or
ceramic resonator is connected to the OSC1 and
OSC2 pins to establish oscillation. Figure 2-1 shows
the pin connections.
Capacitor values are for design guidance only.
These capacitors were tested with the resonators
listed below for basic start-up and operation. These
values are not optimized.
The oscillator design requires the use of a parallel cut
crystal.
Different capacitor values may be required to produce
acceptable oscillator operation. The user should test
the performance of the oscillator over the expected
VDD and temperature range for the application.
Note:
Use of a series cut crystal may give a
frequency out of the crystal manufacturer’s
specifications.
See the notes on page 24 for additional information.
Resonators Used:
455 kHz
2.0 MHz
4.0 MHz
8.0 MHz
16.0 MHz
Note:
When using resonators with frequencies
above 3.5 MHz, the use of HS mode,
rather than XT mode, is recommended.
HS mode may be used at any VDD for
which the controller is rated. If HS is
selected, it is possible that the gain of the
oscillator will overdrive the resonator.
Therefore, a series resistor should be
placed between the OSC2 pin and the
resonator. As a good starting point, the
recommended value of RS is 330Ω.
© 2007 Microchip Technology Inc.
Preliminary
DS39761B-page 23
PIC18F2682/2685/4682/4685
An external clock source may also be connected to the
OSC1 pin in the HS mode, as shown in Figure 2-2.
TABLE 2-2:
CAPACITOR SELECTION FOR
CRYSTAL OSCILLATOR
Typical Capacitor Values
FIGURE 2-2:
EXTERNAL CLOCK
INPUT OPERATION
(HS OSCILLATOR
CONFIGURATION)
Crystal
Freq
Tested:
Osc Type
C1
C2
LP
XT
HS
32 kHz
200 kHz
1 MHz
4 MHz
4 MHz
8 MHz
20 MHz
33 pF
15 pF
33 pF
27 pF
27 pF
22 pF
15 pF
33 pF
15 pF
33 pF
27 pF
27 pF
22 pF
15 pF
OSC1
Clock from
Ext. System
PIC18FXXXX
(HS Mode)
OSC2
Open
2.3
External Clock Input
Capacitor values are for design guidance only.
The EC and ECIO Oscillator modes require an external
clock source to be connected to the OSC1 pin. There is
no oscillator start-up time required after a Power-on
Reset or after an exit from Sleep mode.
These capacitors were tested with the crystals listed
below for basic start-up and operation. These values
are not optimized.
Different capacitor values may be required to produce
acceptable oscillator operation. The user should test
the performance of the oscillator over the expected
VDD and temperature range for the application.
In the EC Oscillator mode, the oscillator frequency
divided by 4 is available on the OSC2 pin. This signal
may be used for test purposes or to synchronize other
logic. Figure 2-3 shows the pin connections for the EC
Oscillator mode.
See the notes following this table for additional
information.
Crystals Used:
FIGURE 2-3:
EXTERNAL CLOCK
INPUT OPERATION
(EC CONFIGURATION)
32 kHz
200 kHz
1 MHz
4 MHz
8 MHz
20 MHz
OSC1/CLKI
Clock from
Ext. System
PIC18FXXXX
OSC2/CLKO
Note 1: Higher capacitance increases the stability
of the oscillator but also increases the
start-up time.
FOSC/4
The ECIO Oscillator mode functions like the EC mode,
except that the OSC2 pin becomes an additional
general purpose I/O pin. The I/O pin becomes bit 6 of
PORTA (RA6). Figure 2-4 shows the pin connections
for the ECIO Oscillator mode.
2: When operating below 3V VDD, or when
using certain ceramic resonators at any
voltage, it may be necessary to use the
HS mode or switch to a crystal oscillator.
3: Since each resonator/crystal has its own
characteristics, the user should consult
the resonator/crystal manufacturer for
FIGURE 2-4:
EXTERNAL CLOCK
INPUT OPERATION
(ECIO CONFIGURATION)
appropriate
values
of
external
components.
4: Rs may be required to avoid overdriving
crystals with low drive level specifications.
OSC1/CLKI
PIC18FXXXX
I/O (OSC2)
Clock from
Ext. System
5: Always verify oscillator performance over
the VDD and temperature range that is
expected for the application.
RA6
DS39761B-page 24
Preliminary
© 2007 Microchip Technology Inc.
PIC18F2682/2685/4682/4685
2.4
RC Oscillator
2.5
PLL Frequency Multiplier
For timing insensitive applications, the “RC” and
“RCIO” device options offer additional cost savings.
The actual oscillator frequency is a function of several
factors:
A Phase Locked Loop (PLL) circuit is provided as an
option for users who wish to use a lower frequency
oscillator circuit or to clock the device up to its highest
rated frequency from a crystal oscillator. This may be
useful for customers who are concerned with EMI due
to high-frequency crystals or users who require higher
clock speeds from an internal oscillator.
• supply voltage
• values of the external resistor (REXT) and
capacitor (CEXT)
• operating temperature
2.5.1
HSPLL OSCILLATOR MODE
Given the same device, operating voltage and tempera-
ture and component values, there will also be unit-to-unit
frequency variations. These are due to factors such as:
The HSPLL mode makes use of the HS mode oscillator
for frequencies up to 10 MHz. A PLL then multiplies the
oscillator output frequency by 4 to produce an internal
clock frequency up to 40 MHz.
• normal manufacturing variation
• difference in lead frame capacitance between
package types (especially for low CEXT values)
The PLL is only available to the crystal oscillator when
the FOSC3:FOSC0 Configuration bits are programmed
for HSPLL mode (= 0110).
• variations within the tolerance of limits of REXT
and CEXT
FIGURE 2-7:
PLL BLOCK DIAGRAM
(HS MODE)
In the RC Oscillator mode, the oscillator frequency
divided by 4 is available on the OSC2 pin. This signal
may be used for test purposes or to synchronize other
logic. Figure 2-5 shows how the R/C combination is
connected.
HS Osc Enable
PLL Enable
(from Configuration Register 1H)
FIGURE 2-5:
RC OSCILLATOR MODE
OSC2
OSC1
Phase
Comparator
VDD
HS Mode
Crystal
Osc
FIN
FOUT
REXT
Internal
OSC1
Clock
Loop
Filter
CEXT
VSS
PIC18FXXXX
OSC2/CLKO
÷4
VCO
FOSC/4
SYSCLK
Recommended values: 3 kΩ ≤ REXT ≤ 100 kΩ
CEXT > 20 pF
The RCIO Oscillator mode (Figure 2-6) functions like
the RC mode, except that the OSC2 pin becomes an
additional general purpose I/O pin. The I/O pin
becomes bit 6 of PORTA (RA6).
2.5.2
PLL AND INTOSC
The PLL is also available to the internal oscillator block
in selected oscillator modes. In this configuration, the
PLL is enabled in software and generates a clock
output of up to 32 MHz. The operation of INTOSC with
the PLL is described in Section 2.6.4 “PLL in INTOSC
Modes”.
FIGURE 2-6:
RCIO OSCILLATOR MODE
VDD
REXT
Internal
OSC1
Clock
CEXT
PIC18FXXXX
VSS
I/O (OSC2)
RA6
Recommended values: 3 kΩ ≤ REXT ≤ 100 kΩ
CEXT > 20 pF
© 2007 Microchip Technology Inc.
Preliminary
DS39761B-page 25
PIC18F2682/2685/4682/4685
When the OSCTUNE register is modified, the INTOSC
and INTRC frequencies will begin shifting to the new
frequency. The INTRC clock will reach the new
2.6
Internal Oscillator Block
The PIC18F2682/2685/4682/4685 devices include an
internal oscillator block which generates two different
clock signals; either can be used as the microcontroller’s
clock source. This may eliminate the need for external
oscillator circuits on the OSC1 and/or OSC2 pins.
frequency within
8 clock cycles (approximately
8 * 32 μs = 256 μs). The INTOSC clock will stabilize
within 1 ms. Code execution continues during this shift.
There is no indication that the shift has occurred.
The main output (INTOSC) is an 8 MHz clock source,
which can be used to directly drive the device clock. It
also drives a postscaler, which can provide a range of
clock frequencies from 31 kHz to 4 MHz. The INTOSC
output is enabled when a clock frequency from 125 kHz
to 8 MHz is selected.
The OSCTUNE register also implements the INTSRC
and PLLEN bits, which control certain features of the
internal oscillator block. The INTSRC bit allows users
to select which internal oscillator provides the clock
source when the 31 kHz frequency option is selected.
This is covered in greater detail in Section 2.7.1
“Oscillator Control Register”.
The other clock source is the internal RC oscillator
(INTRC), which provides a nominal 31 kHz output.
INTRC is enabled if it is selected as the device clock
source; it is also enabled automatically when any of the
following are enabled:
The PLLEN bit controls the operation of the frequency
multiplier, PLL, in internal oscillator modes.
2.6.4
PLL IN INTOSC MODES
• Power-up Timer
The 4x frequency multiplier can be used with the inter-
nal oscillator block to produce faster device clock
speeds than are normally possible with an internal
oscillator. When enabled, the PLL produces a clock
speed of up to 32 MHz.
• Fail-Safe Clock Monitor
• Watchdog Timer
• Two-Speed Start-up
These features are discussed in greater detail in
Section 24.0 “Special Features of the CPU”.
Unlike HSPLL mode, the PLL is controlled through soft-
ware. The control bit, PLLEN (OSCTUNE<6>), is used
to enable or disable its operation.
The clock source frequency (INTOSC direct, INTRC
direct or INTOSC postscaler) is selected by configuring
the IRCF bits of the OSCCON register (Register 2-2).
The PLL is available when the device is configured to use
the internal oscillator block as its primary clock source
(FOSC3:FOSC0 = 1001or 1000). Additionally, the PLL
will only function when the selected output frequency is
either 4 MHz or 8 MHz (OSCCON<6:4> = 111or 110). If
both of these conditions are not met, the PLL is disabled.
2.6.1
INTIO MODES
Using the internal oscillator as the clock source
eliminates the need for up to two external oscillator
pins, which can then be used for digital I/O. Two distinct
configurations are available:
The PLLEN control bit is only functional in those internal
oscillator modes where the PLL is available. In all other
modes, it is forced to ‘0’ and is effectively unavailable.
• In INTIO1 mode, the OSC2 pin outputs FOSC/4,
while OSC1 functions as RA7 for digital input and
output.
2.6.5
INTOSC FREQUENCY DRIFT
• In INTIO2 mode, OSC1 functions as RA7 and
OSC2 functions as RA6, both for digital input and
output.
The factory calibrates the internal oscillator block
output (INTOSC) for 8 MHz. However, this frequency
may drift as VDD or temperature changes, which can
affect the controller operation in a variety of ways. It is
possible to adjust the INTOSC frequency by modifying
the value in the OSCTUNE register. This has no effect
on the INTRC clock source frequency.
2.6.2
INTOSC OUTPUT FREQUENCY
The internal oscillator block is calibrated at the factory
to produce an INTOSC output frequency of 8.0 MHz.
The INTRC oscillator operates independently of the
INTOSC source. Any changes in INTOSC across
voltage and temperature are not necessarily reflected
by changes in INTRC and vice versa.
Tuning the INTOSC source requires knowing when to
make the adjustment, in which direction it should be
made and in some cases, how large a change is
needed. Three compensation techniques are
discussed in Section 2.6.5.1 “Compensating with
the EUSART”, Section 2.6.5.2 “Compensating with
the Timers” and Section 2.6.5.3 “Compensating
with the CCP1 Module in Capture Mode”, but other
techniques may be used.
2.6.3
OSCTUNE REGISTER
The internal oscillator’s output has been calibrated at
the factory but can be adjusted in the user’s applica-
tion. This is done by writing to the OSCTUNE register
(Register 2-1). The tuning sensitivity is constant
throughout the tuning range.
DS39761B-page 26
Preliminary
© 2007 Microchip Technology Inc.
PIC18F2682/2685/4682/4685
REGISTER 2-1:
OSCTUNE: OSCILLATOR TUNING REGISTER
R/W-0
INTSRC
bit 7
R/W-0(1)
PLLEN(1)
U-0
—
R/W-0
TUN4
R/W-0
TUN3
R/W-0
TUN2
R/W-0
TUN1
R/W-0
TUN0
bit 0
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
-n = Value at POR
bit 7
bit 6
INTSRC: Internal Oscillator Low-Frequency Source Select bit
1= 31.25 kHz device clock derived from 8 MHz INTOSC source (divide-by-256 enabled)
0= 31 kHz device clock derived directly from INTRC internal oscillator
PLLEN: Frequency Multiplier PLL for INTOSC Enable bit(1)
1= PLL enabled for INTOSC (4 MHz and 8 MHz only)
0= PLL disabled
bit 5
Unimplemented: Read as ‘0
TUN4:TUN0: Frequency Tuning bits
01111= Maximum frequency
bit 4-0
•
•
•
•
00001
00000= Center frequency. Oscillator module is running at the calibrated frequency.
11111
•
•
•
•
10000= Minimum frequency
Note 1: Available only in certain oscillator configurations; otherwise, this bit is unavailable and reads as ‘0’. See
text for details.
2.6.5.1
Compensating with the EUSART
2.6.5.3
Compensating with the CCP1
Module in Capture Mode
An adjustment may be required when the EUSART
begins to generate framing errors or receives data with
errors while in Asynchronous mode. Framing errors
indicate that the device clock frequency is too high. To
adjust for this, decrement the value in OSCTUNE to
reduce the clock frequency. On the other hand, errors
in data may suggest that the clock speed is too low. To
compensate, increment OSCTUNE to increase the
clock frequency.
The CCP1 module can use free running Timer1 (or
Timer3), clocked by the internal oscillator block and an
external event with a known period (i.e., AC power
frequency). The time of the first event is captured in the
CCPRxH:CCPRxL registers and is recorded for use
later. When the second event causes a capture, the
time of the first event is subtracted from the time of the
second event. Since the period of the external event is
known, the time difference between events can be
calculated.
2.6.5.2
Compensating with the Timers
This technique compares device clock speed to some
reference clock. Two timers may be used; one timer is
clocked by the peripheral clock, while the other is
clocked by a fixed reference source, such as the
Timer1 oscillator.
If the measured time is much greater than the
calculated time, the internal oscillator block is running
too fast. To compensate, decrement the OSCTUNE
register. If the measured time is much less than the
calculated time, the internal oscillator block is running
too slow. To compensate, increment the OSCTUNE
register.
Both timers are cleared, but the timer clocked by the
reference generates interrupts. When an interrupt
occurs, the internally clocked timer is read and both
timers are cleared. If the internally clocked timer value
is greater than expected, then the internal oscillator
block is running too fast. To adjust for this, decrement
the OSCTUNE register.
© 2007 Microchip Technology Inc.
Preliminary
DS39761B-page 27
PIC18F2682/2685/4682/4685
The secondary oscillators are those external sources
not connected to the OSC1 or OSC2 pins. These
sources may continue to operate even after the
controller is placed in a power-managed mode.
2.7
Clock Sources and Oscillator
Switching
Like previous PIC18 devices, the PIC18F2682/2685/
4682/4685 family includes a feature that allows the
device clock source to be switched from the main
oscillator to an alternate low-frequency clock source.
PIC18F2682/2685/4682/4685 devices offer two alter-
nate clock sources. When an alternate clock source is
enabled, the various power-managed operating modes
are available.
PIC18F2682/2685/4682/4685 devices offer the Timer1
oscillator as a secondary oscillator. In all power-
managed modes, this oscillator is often the time base
for functions such as a Real-Time Clock.
Most often, a 32.768 kHz watch crystal is connected
between the RC0/T1OSO/T13CKI and RC1/T1OSI
pins. Like the LP mode oscillator circuit, loading
capacitors are also connected from each pin to ground.
Essentially, there are three clock sources for these
devices:
The Timer1 oscillator is discussed in greater detail in
Section 12.3 “Timer1 Oscillator”.
• Primary oscillators
• Secondary oscillators
• Internal oscillator block
In addition to being a primary clock source, the internal
oscillator block is available as a power-managed
mode clock source. The INTRC source is also used as
the clock source for several special features, such as
the WDT and Fail-Safe Clock Monitor.
The primary oscillators include the External Crystal
and Resonator modes, the External RC modes, the
External Clock modes and the internal oscillator block.
The particular mode is defined by the FOSC3:FOSC0
Configuration bits. The details of these modes are
covered earlier in this chapter.
The clock sources for the PIC18F2682/2685/4682/4685
devices are shown in Figure 2-8. See Section 24.0
“Special Features of the CPU” for Configuration
register details.
FIGURE 2-8:
PIC18F2682/2685/4682/4685 CLOCK DIAGRAM
PIC18F2682/2685/4682/4685
Primary Oscillator
LP, XT, HS, RC, EC
OSC2
Sleep
HSPLL, INTOSC/PLL
4 x PLL
OSC1
OSCTUNE<6>
Secondary Oscillator
Peripherals
T1OSC
T1OSO
T1OSCEN
Enable
Oscillator
OSCCON<6:4>
T1OSI
Internal Oscillator
CPU
8 MHz
OSCCON<6:4>
111
110
4 MHz
Internal
Oscillator
Block
8 MHz
Source
2 MHz
1 MHz
IDLEN
101
100
011
010
001
000
Clock
Control
500 kHz
250 kHz
8 MHz
(INTOSC)
INTRC
Source
FOSC3:FOSC0 OSCCON<1:0>
125 kHz
31 kHz
Clock Source Option
for other Modules
1
0
31 kHz (INTRC)
OSCTUNE<7>
WDT, PWRT, FSCM
and Two-Speed Startup
DS39761B-page 28
Preliminary
© 2007 Microchip Technology Inc.
PIC18F2682/2685/4682/4685
The IDLEN bit determines if the device goes into Sleep
mode or one of the Idle modes when the SLEEP
instruction is executed.
2.7.1
OSCILLATOR CONTROL REGISTER
The OSCCON register (Register 2-2) controls several
aspects of the device clock’s operation, both in full
power operation and in power-managed modes.
The use of the flag and control bits in the OSCCON
register is discussed in more detail in Section 3.0
“Power-Managed Modes”.
The System Clock Select bits, SCS1:SCS0, select the
clock source. The available clock sources are the
primary clock (defined by the FOSC3:FOSC0 Configu-
ration bits), the secondary clock (Timer1 oscillator) and
the internal oscillator block. The clock source changes
immediately after one or more of the bits is written to,
following a brief clock transition interval. The SCS bits
are cleared on all forms of Reset.
Note 1: The Timer1 oscillator must be enabled to
select the secondary clock source. The
Timer1 oscillator is enabled by setting the
T1OSCEN bit in the Timer1 Control regis-
ter (T1CON<3>). If the Timer1 oscillator is
not enabled, then any attempt to select a
secondary clock source when executing a
SLEEPinstruction will be ignored.
The Internal Oscillator Frequency Select bits,
IRCF2:IRCF0, select the frequency output of the
internal oscillator block to drive the device clock. The
choices are the INTRC source, the INTOSC source
(8 MHz) or one of the frequencies derived from the
INTOSC postscaler (31 kHz to 4 MHz). If the internal
oscillator block is supplying the device clock, changing
the states of these bits will have an immediate change
on the internal oscillator’s output. On device Resets,
the default output frequency of the internal oscillator
block is set at 1 MHz.
2: It is recommended that the Timer1
oscillator be operating and stable before
executing the SLEEPinstruction, or a very
long delay may occur while the Timer1
oscillator starts.
2.7.2
OSCILLATOR TRANSITIONS
PIC18F2682/2685/4682/4685 devices contain circuitry
to prevent clock “glitches” when switching between
clock sources. A short pause in the device clock occurs
during the clock switch. The length of this pause is the
sum of two cycles of the old clock source and three to
four cycles of the new clock source. This formula
assumes that the new clock source is stable.
When an output frequency of 31 kHz is selected
(IRCF2:IRCF0 = 000), users may choose which
internal oscillator acts as the source. This is done with
the INTSRC bit in the OSCTUNE register
(OSCTUNE<7>). Setting this bit selects INTOSC as a
31.25 kHz clock source by enabling the divide-by-256
output of the INTOSC postscaler. Clearing INTSRC
selects INTRC (nominally 31 kHz) as the clock source.
Clock transitions are discussed in greater detail in
Section 3.1.2 “Entering Power-Managed Modes”.
This option allows users to select the tunable and more
precise INTOSC as a clock source, while maintaining
power savings with a very low clock speed. Regardless
of the setting of INTSRC, INTRC always remains the
clock source for features such as the Watchdog Timer
and the Fail-Safe Clock Monitor.
The OSTS, IOFS and T1RUN bits indicate which clock
source is currently providing the device clock. The
OSTS bit indicates that the Oscillator Start-up Timer
has timed out and the primary clock is providing the
device clock in primary clock modes. The IOFS bit
indicates when the internal oscillator block has
stabilized and is providing the device clock in RC Clock
modes. The T1RUN bit (T1CON<6>) indicates when
the Timer1 oscillator is providing the device clock in
secondary clock modes. In power-managed modes,
only one of these three bits will be set at any time. If
none of these bits are set, the INTRC is providing the
clock or the internal oscillator block has just started and
is not yet stable.
© 2007 Microchip Technology Inc.
Preliminary
DS39761B-page 29
PIC18F2682/2685/4682/4685
REGISTER 2-2:
OSCCON: OSCILLATOR CONTROL REGISTER
R/W-0
IDLEN
bit 7
R/W-1
IRCF2
R/W-0
IRCF1
R/W-0
IRCF0
R(1)
R-0
R/W-0
SCS1
R/W-0
SCS0
OSTS
IOFS
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7
IDLEN: Idle Enable bit
1= Device enters Idle mode on SLEEPinstruction
0= Device enters Sleep mode on SLEEPinstruction
bit 6-4
IRCF2:IRCF0: Internal Oscillator Frequency Select bits
111= 8 MHz (INTOSC drives clock directly)
110= 4 MHz
101= 2 MHz
100= 1 MHz(3)
011= 500 kHz
010= 250 kHz
001= 125 kHz
000= 31 kHz (from either INTOSC/256 or INTRC directly)(2)
bit 3
OSTS: Oscillator Start-up Time-out Status bit(1)
1= Oscillator Start-up Timer time-out has expired; primary oscillator is running
0= Oscillator Start-up Timer time-out is running; primary oscillator is not ready
bit 2
IOFS: INTOSC Frequency Stable bit
1= INTOSC frequency is stable and the frequency is provided by one of the RC modes
0= INTOSC frequency is not stable
bit 1-0
SCS1:SCS0: System Clock Select bits
1x= Internal oscillator block
01= Timer1 oscillator
00= Primary oscillator
Note 1: Depends on state of the IESO Configuration bit.
2: Source selected by the INTSRC bit (OSCTUNE<7>), see text.
3: Default output frequency of INTOSC on Reset.
DS39761B-page 30
Preliminary
© 2007 Microchip Technology Inc.
PIC18F2682/2685/4682/4685
a Real-Time Clock. Other features may be operating
2.8
Effects of Power-Managed Modes
on the Various Clock Sources
that do not require a device clock source (i.e., MSSP
slave, PSP, INTx pins and others). Peripherals that
may add significant current consumption are listed in
Section 27.2 “DC Characteristics: Power-Down
and Supply Current”.
When PRI_IDLE mode is selected, the designated
primary oscillator continues to run without interruption.
For all other power-managed modes, the oscillator
using the OSC1 pin is disabled. The OSC1 pin (and
OSC2 pin, if used by the oscillator) will stop oscillating.
2.9
Power-up Delays
In secondary clock modes (SEC_RUN and
SEC_IDLE), the Timer1 oscillator is operating and
providing the device clock. The Timer1 oscillator may
also run in all power-managed modes if required to
clock Timer1 or Timer3.
Power-up delays are controlled by two timers, so that no
external Reset circuitry is required for most applications.
The delays ensure that the device is kept in Reset until
the device power supply is stable under normal circum-
stances and the primary clock is operating and stable.
For additional information on power-up delays, see
Section 4.5 “Device Reset Timers”.
In internal oscillator modes (RC_RUN and RC_IDLE),
the internal oscillator block provides the device clock
source. The 31 kHz INTRC output can be used directly
to provide the clock and may be enabled to support
various special features, regardless of the power-
managed mode (see Section 24.2 “Watchdog Timer
(WDT)”, Section 24.3 “Two-Speed Start-up” and
Section 24.4 “Fail-Safe Clock Monitor” for more
information on WDT, Two-Speed Start-up and Fail-Safe
Clock Monitor). The INTOSC output at 8 MHz may be
used directly to clock the device or may be divided
down by the postscaler. The INTOSC output is disabled
if the clock is provided directly from the INTRC output.
The first timer is the Power-up Timer (PWRT), which
provides a fixed delay on power-up (parameter 33,
Table 27-10). It is enabled by clearing (= 0) the
PWRTEN Configuration bit.
The second timer is the Oscillator Start-up Timer
(OST), intended to keep the chip in Reset until the
crystal oscillator is stable (LP, XT and HS modes). The
OST does this by counting 1024 oscillator cycles
before allowing the oscillator to clock the device.
When the HSPLL Oscillator mode is selected, the
device is kept in Reset for an additional 2 ms, following
the HS mode OST delay, so the PLL can lock to the
incoming clock frequency.
If the Sleep mode is selected, all clock sources are
stopped. Since all the transistor switching currents
have been stopped, Sleep mode achieves the lowest
current consumption of the device (only leakage
currents).
There is a delay of interval TCSD (parameter 38,
Table 27-10), following POR, while the controller
becomes ready to execute instructions. This delay runs
concurrently with any other delays. This may be the
only delay that occurs when any of the EC, RC or INTIO
modes are used as the primary clock source.
Enabling any on-chip feature that will operate during
Sleep will increase the current consumed during
Sleep. The INTRC is required to support WDT opera-
tion. The Timer1 oscillator may be operating to support
TABLE 2-3:
OSC1 AND OSC2 PIN STATES IN SLEEP MODE
OSC1 Pin
OSC Mode
OSC2 Pin
RC, INTIO1
RCIO, INTIO2
ECIO
Floating, external resistor should pull high
Floating, external resistor should pull high
Floating, pulled by external clock
At logic low (clock/4 output)
Configured as PORTA, bit 6
Configured as PORTA, bit 6
At logic low (clock/4 output)
EC
Floating, pulled by external clock
LP, XT and HS
Feedback inverter disabled at quiescent
voltage level
Feedback inverter disabled at quiescent
voltage level
Note:
See Table 4-2 in Section 4.0 “Reset” for time-outs due to Sleep and MCLR Reset.
© 2007 Microchip Technology Inc.
Preliminary
DS39761B-page 31
PIC18F2682/2685/4682/4685
NOTES:
DS39761B-page 32
Preliminary
© 2007 Microchip Technology Inc.
PIC18F2682/2685/4682/4685
3.1.1
CLOCK SOURCES
3.0
POWER-MANAGED MODES
The SCS1:SCS0 bits allow the selection of one of three
clock sources for power-managed modes. They are:
PIC18F2682/2685/4682/4685 devices offer a total of
seven operating modes for more efficient power
management. These modes provide a variety of
options for selective power conservation in applications
where resources may be limited (i.e., battery-powered
devices).
• The primary clock as defined by the
FOSC3:FOSC0 Configuration bits
• The secondary clock (the Timer1 oscillator)
• The internal oscillator block (for RC modes)
There are three categories of power-managed modes:
3.1.2
ENTERING POWER-MANAGED
MODES
• Run modes
• Idle modes
• Sleep mode
Switching from one power-managed mode to another
begins by loading the OSCCON register. The
SCS1:SCS0 bits select the clock source and determine
which Run or Idle mode is to be used. Changing these
bits causes an immediate switch to the new clock
source, assuming that it is running. The switch may
also be subject to clock transition delays. These are
discussed in Section 3.1.3 “Clock Transitions And
Status Indicators” and subsequent sections.
These categories define which portions of the device
are clocked and sometimes, what speed. The Run and
Idle modes may use any of the three available clock
sources (primary, secondary or internal oscillator
block); the Sleep mode does not use a clock source.
The power-managed modes include several power
saving features offered on previous PIC® devices. One
is the clock switching feature, offered in other PIC18
devices, allowing the controller to use the Timer1
oscillator in place of the primary oscillator. Also
included is the Sleep mode, offered by all PIC devices,
where all device clocks are stopped.
Entry to the power-managed Idle or Sleep modes is
triggered by the execution of a SLEEPinstruction. The
actual mode that results depends on the status of the
IDLEN bit.
Depending on the current mode and the mode being
switched to, a change to a power-managed mode does
not always require setting all of these bits. Many
transitions may be done by changing the oscillator
select bits, or changing the IDLEN bit, prior to issuing a
SLEEP instruction. If the IDLEN bit is already
configured correctly, it may only be necessary to
perform a SLEEP instruction to switch to the desired
mode.
3.1
Selecting Power-Managed Modes
Selecting
a power-managed mode requires two
decisions: if the CPU is to be clocked or not and the
selection of clock source. The IDLEN bit
(OSCCON<7>) controls CPU clocking, while the
SCS1:SCS0 bits (OSCCON<1:0>) select the clock
source. The individual modes, bit settings, clock sources
and affected modules are summarized in Table 3-1.
a
TABLE 3-1:
Mode
POWER-MANAGED MODES
OSCCON Bits Module Clocking
IDLEN<7>(1) SCS1:SCS0<1:0> CPU Peripherals
Available Clock and Oscillator Source
Sleep
0
N/A
Off
Off
None – all clocks are disabled
PRI_RUN
N/A
00
Clocked Clocked Primary – LP, XT, HS, HSPLL, RC, EC, INTRC:
this is the normal full power execution mode(2)
SEC_RUN
RC_RUN
PRI_IDLE
SEC_IDLE
RC_IDLE
N/A
N/A
1
01
1x
00
01
1x
Clocked Clocked Secondary – Timer1 Oscillator
Clocked Clocked Internal Oscillator Block(2)
Off
Off
Off
Clocked Primary – LP, XT, HS, HSPLL, RC, EC
Clocked Secondary – Timer1 Oscillator
Clocked Internal Oscillator Block(2)
1
1
Note 1: IDLEN reflects its value when the SLEEPinstruction is executed.
2: Includes INTOSC and INTOSC postscaler, as well as the INTRC source.
© 2007 Microchip Technology Inc.
Preliminary
DS39761B-page 33
PIC18F2682/2685/4682/4685
3.1.3
CLOCK TRANSITIONS AND STATUS
INDICATORS
3.2
Run Modes
In the Run modes, clocks to both the core and
peripherals are active. The difference between these
modes is the clock source.
The length of the transition between clock sources is
the sum of two cycles of the old clock source and three
to four cycles of the new clock source. This formula
assumes that the new clock source is stable.
3.2.1
PRI_RUN MODE
Three bits indicate the current clock source and its
status. They are:
The PRI_RUN mode is the normal, full power execution
mode of the microcontroller. This is also the default
mode upon a device Reset, unless Two-Speed Start-up
is enabled (see Section 24.3 “Two-Speed Start-up”
for details). In this mode, the OSTS bit is set. The IOFS
bit may be set if the internal oscillator block is the
primary clock source (see Section 2.7.1 “Oscillator
Control Register”).
• OSTS (OSCCON<3>)
• IOFS (OSCCON<2>)
• T1RUN (T1CON<6>)
In general, only one of these bits will be set while in a
given power-managed mode. When the OSTS bit is
set, the primary clock is providing the device clock.
When the IOFS bit is set, the INTOSC output is provid-
ing a stable 8 MHz clock source to a divider that
actually drives the device clock. When the T1RUN bit is
set, the Timer1 oscillator is providing the clock. If none
of these bits are set, then either the INTRC clock
source is clocking the device, or the INTOSC source is
not yet stable.
3.2.2
SEC_RUN MODE
The SEC_RUN mode is the compatible mode to the
“clock switching” feature offered in other PIC18
devices. In this mode, the CPU and peripherals are
clocked from the Timer1 oscillator. This gives users the
option of lower power consumption while still using a
high accuracy clock source.
If the internal oscillator block is configured as the primary
clock source by the FOSC3:FOSC0 Configuration bits,
then both the OSTS and IOFS bits may be set when in
PRI_RUN or PRI_IDLE modes. This indicates that the
primary clock (INTOSC output) is generating a stable
8 MHz output. Entering another power-managed RC
mode at the same frequency would clear the OSTS bit.
SEC_RUN mode is entered by setting the SCS1:SCS0
bits to ‘01’. The device clock source is switched to the
Timer1 oscillator (see Figure 3-1), the primary
oscillator is shut down, the T1RUN bit (T1CON<6>) is
set and the OSTS bit is cleared.
Note:
The Timer1 oscillator should already be
running prior to entering SEC_RUN mode.
If the T1OSCEN bit is not set when the
SCS1:SCS0 bits are set to ‘01’, entry to
SEC_RUN mode will not occur. If the
Timer1 oscillator is enabled but not yet
running, device clocks will be delayed until
the oscillator has started. In such situa-
tions, initial oscillator operation is far from
stable and unpredictable operation may
result.
Note 1: Caution should be used when modifying a
single IRCF bit. If VDD is less than 3V, it is
possible to select a higher clock speed
than is supported by the low VDD.
Improper device operation may result if
the VDD/FOSC specifications are violated.
2: Executing a SLEEP instruction does not
necessarily place the device into Sleep
mode. It acts as the trigger to place the
controller into either the Sleep mode or
one of the Idle modes, depending on the
setting of the IDLEN bit.
On transitions from SEC_RUN to PRI_RUN mode, the
peripherals and CPU continue to be clocked from the
Timer1 oscillator while the primary clock is started.
When the primary clock becomes ready, a clock switch
back to the primary clock occurs (see Figure 3-2).
When the clock switch is complete, the T1RUN bit is
cleared, the OSTS bit is set and the primary clock is
providing the clock. The IDLEN and SCS bits are not
affected by the wake-up; the Timer1 oscillator
continues to run.
3.1.4
MULTIPLE SLEEP COMMANDS
The power-managed mode that is invoked with the
SLEEP instruction is determined by the setting of the
IDLEN bit at the time the instruction is executed. If
another SLEEPinstruction is executed, the device will
enter the power-managed mode specified by IDLEN at
that time. If IDLEN has changed, the device will enter
the new power-managed mode specified by the new
setting.
DS39761B-page 34
Preliminary
© 2007 Microchip Technology Inc.
PIC18F2682/2685/4682/4685
FIGURE 3-1:
TRANSITION TIMING FOR ENTRY TO SEC_RUN MODE
Q1 Q2 Q3 Q4 Q1
Q2
Q3
Q4
Q1
Q2
Q3
T1OSI
OSC1
1
2
3
n-1
n
Clock Transition
CPU
Clock
Peripheral
Clock
Program
Counter
PC
PC + 2
PC + 4
FIGURE 3-2:
TRANSITION TIMING FROM SEC_RUN MODE TO PRI_RUN MODE (HSPLL)
Q1
Q2
Q3
Q4
Q1
Q2 Q3 Q4 Q1 Q2 Q3
T1OSI
OSC1
(1)
TOST
(1)
TPLL
1
2
n-1
n
PLL Clock
Output
Clock
Transition
CPU Clock
Peripheral
Clock
Program
Counter
PC
PC + 2
PC + 4
SCS1:SCS0 bits Changed
OSTS bit Set
Note 1: TOST = 1024 TOSC; TPLL = 2 ms (approx). These intervals are not shown to scale.
the INTOSC multiplexer (see Figure 3-3), the primary
oscillator is shut down and the OSTS bit is cleared. The
IRCF bits may be modified at any time to immediately
change the clock speed.
3.2.3
RC_RUN MODE
In RC_RUN mode, the CPU and peripherals are
clocked from the internal oscillator block using the
INTOSC multiplexer; the primary clock is shut down.
When using the INTRC source, this mode provides the
best power conservation of all the Run modes, while
still executing code. It works well for user applications
which are not highly timing sensitive or do not require
high-speed clocks at all times.
Note:
Caution should be used when modifying a
single IRCF bit. If VDD is less than 3V, it is
possible to select a higher clock speed
than is supported by the low VDD.
Improper device operation may result if
the VDD/FOSC specifications are violated.
If the primary clock source is the internal oscillator
block (either INTRC or INTOSC), there are no distin-
guishable differences between PRI_RUN and
RC_RUN modes during execution. However, a clock
switch delay will occur during entry to and exit from
RC_RUN mode. Therefore, if the primary clock source
is the internal oscillator block, the use of RC_RUN
mode is not recommended.
If the IRCF bits and the INTSRC bit are all clear, the
INTOSC output is not enabled and the IOFS bit will
remain clear; there will be no indication of the current
clock source. The INTRC source is providing the
device clocks.
If the IRCF bits are changed from all clear (thus,
enabling the INTOSC output) or if INTSRC is set, the
IOFS bit becomes set after the INTOSC output
becomes stable. Clocks to the device continue while
the INTOSC source stabilizes after an interval of
TIOBST.
This mode is entered by setting SCS1 to ‘1’. Although
it is ignored, it is recommended that SCS0 also be
cleared; this is to maintain software compatibility with
future devices. When the clock source is switched to
© 2007 Microchip Technology Inc.
Preliminary
DS39761B-page 35
PIC18F2682/2685/4682/4685
If the IRCF bits were previously at a non-zero value or
if INTSRC was set before setting SCS1 and the
INTOSC source was already stable, the IOFS bit will
remain set.
primary clock becomes ready, a clock switch to the
primary clock occurs (see Figure 3-4). When the clock
switch is complete, the IOFS bit is cleared, the OSTS
bit is set and the primary clock is providing the device
clock. The IDLEN and SCS bits are not affected by the
switch. The INTRC source will continue to run if either
the WDT or the Fail-Safe Clock Monitor is enabled.
On transitions from RC_RUN mode to PRI_RUN mode,
the device continues to be clocked from the INTOSC
multiplexer while the primary clock is started. When the
FIGURE 3-3:
TRANSITION TIMING TO RC_RUN MODE
Q1 Q2 Q3 Q4 Q1
Q2
Q3
Q4
Q1
Q2
Q3
1
2
3
n-1
n
INTRC
OSC1
Clock Transition
CPU
Clock
Peripheral
Clock
Program
Counter
PC
PC + 2
PC + 4
FIGURE 3-4:
TRANSITION TIMING FROM RC_RUN MODE TO PRI_RUN MODE
Q3
Q4
Q1
Q2 Q3 Q4 Q1 Q2 Q3
Q1
Q2
INTOSC
Multiplexer
OSC1
(1)
TOST
(1)
TPLL
1
2
n-1
n
PLL Clock
Output
Clock
Transition
CPU Clock
Peripheral
Clock
Program
Counter
PC
PC + 2
PC + 4
SCS1:SCS0 bits Changed
OSTS bit Set
Note 1: TOST = 1024 TOSC; TPLL = 2 ms (approx). These intervals are not shown to scale.
DS39761B-page 36
Preliminary
© 2007 Microchip Technology Inc.
PIC18F2682/2685/4682/4685
3.3
Sleep Mode
3.4
Idle Modes
The power-managed Sleep mode in the PIC18F2682/
2685/4682/4685 devices is identical to the legacy
Sleep mode offered in all other PIC devices. It is
entered by clearing the IDLEN bit (the default state on
device Reset) and executing the SLEEP instruction.
This shuts down the selected oscillator (Figure 3-5). All
clock source status bits are cleared.
The Idle modes allow the controller’s CPU to be
selectively shut down while the peripherals continue to
operate. Selecting a particular Idle mode allows users
to further manage power consumption.
If the IDLEN bit is set to a ‘1’ when a SLEEPinstruction is
executed, the peripherals will be clocked from the clock
source selected using the SCS1:SCS0 bits; however, the
CPU will not be clocked. The clock source status bits are
not affected. Setting IDLEN and executing a SLEEP
instruction provides a quick method of switching from a
given Run mode to its corresponding Idle mode.
Entering the Sleep mode from any other mode does not
require a clock switch. This is because no clocks are
needed once the controller has entered Sleep. If the
WDT is selected, the INTRC source will continue to
operate. If the Timer1 oscillator is enabled, it will also
continue to run.
If the WDT is selected, the INTRC source will continue
to operate. If the Timer1 oscillator is enabled, it will also
continue to run.
When a wake event occurs in Sleep mode (by
interrupt, Reset or WDT time-out), the device will not
be clocked until the clock source selected by the
SCS1:SCS0 bits becomes ready (see Figure 3-6), or
it will be clocked from the internal oscillator block if
either the Two-Speed Start-up or the Fail-Safe Clock
Monitor are enabled (see Section 24.0 “Special
Features of the CPU”). In either case, the OSTS bit
is set when the primary clock is providing the device
clocks. The IDLEN and SCS bits are not affected by
the wake-up.
Since the CPU is not executing instructions, the only
exits from any of the Idle modes are by interrupt, WDT
time-out or a Reset. When a wake event occurs, CPU
execution is delayed by an interval of TCSD
(parameter 38, Table 27-10) while it becomes ready to
execute code. When the CPU begins executing code,
it resumes with the same clock source for the current
Idle mode. For example, when waking from RC_IDLE
mode, the internal oscillator block will clock the CPU
and peripherals (in other words, RC_RUN mode). The
IDLEN and SCS bits are not affected by the wake-up.
While in any Idle mode or the Sleep mode, a WDT time-
out will result in a WDT wake-up to the Run mode
currently specified by the SCS1:SCS0 bits.
FIGURE 3-5:
TRANSITION TIMING FOR ENTRY TO SLEEP MODE
Q1 Q2 Q3 Q4 Q1
OSC1
CPU
Clock
Peripheral
Clock
Sleep
Program
Counter
PC
PC + 2
FIGURE 3-6:
TRANSITION TIMING FOR WAKE FROM SLEEP (HSPLL)
Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
Q2 Q3 Q4 Q1 Q2
Q1
OSC1
(1)
(1)
TPLL
TOST
PLL Clock
Output
CPU Clock
Peripheral
Clock
Program
Counter
PC
PC + 2
PC + 4
PC + 6
Wake Event
OSTS bit Set
Note1: TOST = 1024 TOSC; TPLL = 2 ms (approx). These intervals are not shown to scale.
© 2007 Microchip Technology Inc.
Preliminary
DS39761B-page 37
PIC18F2682/2685/4682/4685
3.4.1
PRI_IDLE MODE
3.4.2
SEC_IDLE MODE
This mode is unique among the three low-power Idle
modes in that it does not disable the primary device
clock. For timing sensitive applications, this allows for
the fastest resumption of device operation with its more
accurate primary clock source, since the clock source
does not have to “warm up” or transition from another
oscillator.
In SEC_IDLE mode, the CPU is disabled but the
peripherals continue to be clocked from the Timer1
oscillator. This mode is entered from SEC_RUN by set-
ting the IDLEN bit and executing a SLEEPinstruction. If
the device is in another Run mode, set the IDLEN bit
first, then set the SCS1:SCS0 bits to ‘01’ and execute
SLEEP. When the clock source is switched to the
Timer1 oscillator, the primary oscillator is shut down,
the OSTS bit is cleared and the T1RUN bit is set.
PRI_IDLE mode is entered from PRI_RUN mode by
setting the IDLEN bit and executing
a SLEEP
instruction. If the device is in another Run mode, set
IDLEN first, then clear the SCS bits and execute
SLEEP. Although the CPU is disabled, the peripherals
continue to be clocked from the primary clock source
specified by the FOSC3:FOSC0 Configuration bits.
The OSTS bit remains set (see Figure 3-7).
When a wake event occurs, the peripherals continue
to be clocked from the Timer1 oscillator. After an inter-
val of TCSD following the wake event, the CPU begins
executing code being clocked by the Timer1 oscillator.
The IDLEN and SCS bits are not affected by the
wake-up; the Timer1 oscillator continues to run (see
Figure 3-8).
When a wake event occurs, the CPU is clocked from the
primary clock source. A delay of interval TCSD is
required between the wake event and when code
execution starts. This is required to allow the CPU to
become ready to execute instructions. After the wake-
up, the OSTS bit remains set. The IDLEN and SCS bits
are not affected by the wake-up (see Figure 3-8).
Note:
The Timer1 oscillator should already be
running prior to entering SEC_IDLE mode.
If the T1OSCEN bit is not set when the
SLEEP instruction is executed, the SLEEP
instruction will be ignored and entry to
SEC_IDLE mode will not occur. If the
Timer1 oscillator is enabled but not yet run-
ning, peripheral clocks will be delayed until
the oscillator has started. In such situations,
initial oscillator operation is far from stable
and unpredictable operation may result.
FIGURE 3-7:
TRANSITION TIMING FOR ENTRY TO IDLE MODE
Q3
Q4
Q1
Q1
Q2
OSC1
CPU Clock
Peripheral
Clock
Program
Counter
PC
PC + 2
FIGURE 3-8:
TRANSITION TIMING FOR WAKE FROM IDLE TO RUN MODE
Q1
Q3
Q4
Q2
OSC1
TCSD
CPU Clock
Peripheral
Clock
Program
Counter
PC
Wake Event
DS39761B-page 38
Preliminary
© 2007 Microchip Technology Inc.
PIC18F2682/2685/4682/4685
On all exits from Idle or Sleep modes by interrupt, code
execution branches to the interrupt vector if the GIE/
GIEH bit (INTCON<7>) is set. Otherwise, code
execution continues or resumes without branching
(see Section 9.0 “Interrupts”).
3.4.3
RC_IDLE MODE
In RC_IDLE mode, the CPU is disabled but the periph-
erals continue to be clocked from the internal oscillator
block using the INTOSC multiplexer. This mode allows
for controllable power conservation during Idle periods.
A fixed delay of interval TCSD following the wake event
is required when leaving the Sleep and Idle modes.
This delay is required for the CPU to prepare for
execution. Instruction execution resumes on the first
clock cycle following this delay.
From RC_RUN, this mode is entered by setting the
IDLEN bit and executing a SLEEP instruction. If the
device is in another Run mode, first set IDLEN, then set
the SCS1 bit and execute SLEEP. Although its value is
ignored, it is recommended that SCS0 also be cleared;
this is to maintain software compatibility with future
devices. The INTOSC multiplexer may be used to
select a higher clock frequency, by modifying the IRCF
bits, before executing the SLEEPinstruction. When the
clock source is switched to the INTOSC multiplexer, the
primary oscillator is shut down and the OSTS bit is
cleared.
3.5.2
EXIT BY WDT TIME-OUT
A WDT time-out will cause different actions depending
on which power-managed mode the device is in when
the time-out occurs.
If the device is not executing code (all Idle modes and
Sleep mode), the time-out will result in an exit from the
power-managed mode (see Section 3.2 “Run
Modes” and Section 3.3 “Sleep Mode”). If the device
is executing code (all Run modes), the time-out will
result in a WDT Reset (see Section 24.2 “Watchdog
Timer (WDT)”).
If the IRCF bits are set to any non-zero value or the
INTSRC bit is set, the INTOSC output is enabled. The
IOFS bit becomes set, after the INTOSC output
becomes stable, after an interval of TIOBST
(parameter 39, Table 27-10). Clocks to the peripherals
continue while the INTOSC source stabilizes. If the
IRCF bits were previously at a non-zero value, or
INTSRC was set before the SLEEP instruction was
executed and the INTOSC source was already stable,
the IOFS bit will remain set. If the IRCF bits and
INTSRC are all clear, the INTOSC output will not be
enabled, the IOFS bit will remain clear and there will be
no indication of the current clock source.
The WDT timer and postscaler are cleared by executing
a SLEEPor CLRWDT instruction, the loss of a currently
selected clock source (if the Fail-Safe Clock Monitor is
enabled) and modifying the IRCF bits in the OSCCON
register if the internal oscillator block is the device clock
source.
3.5.3
EXIT BY RESET
When a wake event occurs, the peripherals continue to
be clocked from the INTOSC multiplexer. After a delay
of TCSD following the wake event, the CPU begins
executing code being clocked by the INTOSC multi-
plexer. The IDLEN and SCS bits are not affected by the
wake-up. The INTRC source will continue to run if
either the WDT or the Fail-Safe Clock Monitor is
enabled.
Normally, the device is held in Reset by the Oscillator
Start-up Timer (OST) until the primary clock becomes
ready. At that time, the OSTS bit is set and the device
begins executing code. If the internal oscillator block is
the new clock source, the IOFS bit is set instead.
The exit delay time from Reset to the start of code
execution depends on both the clock sources before
and after the wake-up and the type of oscillator if the
new clock source is the primary clock. Exit delays are
summarized in Table 3-2.
3.5
Exiting Idle and Sleep Modes
An exit from Sleep mode or any of the Idle modes is
triggered by an interrupt, a Reset or a WDT time-out.
This section discusses the triggers that cause exits
from power-managed modes. The clocking subsystem
actions are discussed in each of the power-managed
modes (see Section 3.2 “Run Modes”, Section 3.3
“Sleep Mode” and Section 3.4 “Idle Modes”).
Code execution can begin before the primary clock
becomes ready. If either the Two-Speed Start-up (see
Section 24.3 “Two-Speed Start-up”) or Fail-Safe
Clock Monitor (see Section 24.4 “Fail-Safe Clock
Monitor”) is enabled, the device may begin execution
as soon as the Reset source has cleared. Execution is
clocked by the INTOSC multiplexer driven by the
internal oscillator block. Execution is clocked by the
internal oscillator block until either the primary clock
becomes ready or a power-managed mode is entered
before the primary clock becomes ready; the primary
clock is then shut down.
3.5.1
EXIT BY INTERRUPT
Any of the available interrupt sources can cause the
device to exit from an Idle mode or the Sleep mode to
a Run mode. To enable this functionality, an interrupt
source must be enabled by setting its enable bit in one
of the INTCON or PIE registers. The exit sequence is
initiated when the corresponding interrupt flag bit is set.
© 2007 Microchip Technology Inc.
Preliminary
DS39761B-page 39
PIC18F2682/2685/4682/4685
In these instances, the primary clock source either
does not require an oscillator start-up delay, since it is
already running (PRI_IDLE), or normally does not
require an oscillator start-up delay (RC, EC and INTIO
Oscillator modes). However, a fixed delay of interval
TCSD following the wake event is still required when
leaving the Sleep and Idle modes to allow the CPU to
prepare for execution. Instruction execution resumes
on the first clock cycle following this delay.
3.5.4
EXIT WITHOUT AN OSCILLATOR
START-UP DELAY
Certain exits from power-managed modes do not
invoke the OST at all. There are two cases:
• PRI_IDLE mode where the primary clock source
is not stopped
• The primary clock source is not any of the LP, XT,
HS or HSPLL modes
TABLE 3-2:
EXIT DELAY ON WAKE-UP BY RESET FROM SLEEP MODE OR ANY IDLE MODE
(BY CLOCK SOURCES)
Clock Source
Before Wake-up
Clock Source
After Wake-up
Clock Ready Status
Bit (OSCCON)
Exit Delay
LP, XT, HS
HSPLL
OSTS
Primary Device Clock
(PRI_IDLE mode)
(2)
EC, RC
TCSD
INTRC(1)
INTOSC(3)
LP, XT, HS
HSPLL
—
IOFS
(4)
TOST
(4)
TOST + trc
OSTS
T1OSC or INTRC(1)
EC, RC
(2)
TCSD
INTRC(1)
INTOSC(3)
LP, XT, HS
HSPLL
—
(5)
TIOBST
IOFS
(4)
TOST
(4)
TOST + trc
OSTS
INTOSC(3)
EC, RC
(2)
TCSD
INTRC(1)
INTOSC(3)
LP, XT, HS
HSPLL
—
None
IOFS
(4)
TOST
(4)
TOST + trc
OSTS
None
(Sleep mode)
EC, RC
(2)
TCSD
INTRC(1)
INTOSC(3)
—
(5)
TIOBST
IOFS
Note 1: In this instance, refers specifically to the 31 kHz INTRC clock source.
2: TCSD (parameter 38) is a required delay when waking from Sleep and all Idle modes and runs concurrently
with any other required delays (see Section 3.4 “Idle Modes”).
3: Includes both the INTOSC 8 MHz source and postscaler derived frequencies.
4: TOST is the Oscillator Start-up Timer (parameter 32). trc is the PLL Lock-out Timer (parameter F12); it is
also designated as TPLL.
5: Execution continues during TIOBST (parameter 39), the INTOSC stabilization period.
DS39761B-page 40
Preliminary
© 2007 Microchip Technology Inc.
PIC18F2682/2685/4682/4685
A simplified block diagram of the on-chip Reset circuit
is shown in Figure 4-1.
4.0
RESET
The PIC18F2682/2685/4682/4685 devices differentiate
between various kinds of Reset:
4.1
RCON Register
a) Power-on Reset (POR)
Device Reset events are tracked through the RCON
register (Register 4-1). The lower five bits of the
register indicate that a specific Reset event has
occurred. In most cases, these bits can only be cleared
by the event and must be set by the application after
the event. The state of these flag bits, taken together,
can be read to indicate the type of Reset that just
occurred. This is described in more detail in
Section 4.6 “Reset State of Registers”.
b) MCLR Reset during normal operation
c) MCLR Reset during power-managed modes
d) Watchdog Timer (WDT) Reset during execution
e) Programmable Brown-out Reset (BOR)
f) RESETInstruction
g) Stack Full Reset
h) Stack Underflow Reset
This section discusses Resets generated by MCLR,
POR and BOR and covers the operation of the various
start-up timers. Stack Reset events are covered in
Section 5.1.2.4 “Stack Full and Underflow Resets”.
WDT Resets are covered in Section 24.2 “Watchdog
Timer (WDT)”.
The RCON register also has control bits for setting
interrupt priority (IPEN) and software control of the
BOR (SBOREN). Interrupt priority is discussed in
Section 9.0 “Interrupts”. BOR is covered in
Section 4.4 “Brown-out Reset (BOR)”.
FIGURE 4-1:
SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT
RESET
Instruction
Stack Full/Underflow Reset
Stack
Pointer
External Reset
MCLRE
MCLR
( )_IDLE
Sleep
WDT
Time-out
POR Pulse
BOREN
VDD Rise
Detect
VDD
Brown-out
Reset
S
OST/PWRT
OST
1024 Cycles
Chip_Reset
10-Bit Ripple Counter
Q
R
OSC1
32 μs
PWRT
65.5 ms
INTRC(1)
11-Bit Ripple Counter
Enable PWRT
(2)
Enable OST
Note 1: This is the INTRC source from the internal oscillator block and is separate from the RC oscillator of the CLKI pin.
2: See Table 4-2 for time-out situations.
© 2007 Microchip Technology Inc.
Preliminary
DS39761B-page 41
PIC18F2682/2685/4682/4685
REGISTER 4-1:
RCON: RESET CONTROL REGISTER
R/W-0
IPEN
R/W-1(1)
U-0
—
R/W-1
RI
R-1
TO
R-1
PD
R/W-0(2)
POR
R/W-0
BOR
SBOREN
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
-n = Value at POR
bit 7
bit 6
IPEN: Interrupt Priority Enable bit
1= Enable priority levels on interrupts
0= Disable priority levels on interrupts (PIC16CXXX Compatibility mode)
SBOREN: BOR Software Enable bit(1)
If BOREN1:BOREN0 = 01:
1= BOR is enabled
0= BOR is disabled
If BOREN1:BOREN0 = 00, 10or 11:
Bit is disabled and read as ‘0’.
bit 5
bit 4
Unimplemented: Read as ‘0’
RI: RESETInstruction Flag bit
1= The RESETinstruction was not executed (set by firmware only)
0= The RESET instruction was executed causing a device Reset (must be set in software after a
Brown-out Reset occurs)
bit 3
bit 2
bit 1
bit 0
TO: Watchdog Time-out Flag bit
1= Set by power-up, CLRWDTinstruction or SLEEPinstruction
0= A WDT time-out occurred
PD: Power-Down Detection Flag bit
1= Set by power-up or by the CLRWDTinstruction
0= Set by execution of the SLEEPinstruction
POR: Power-on Reset Status bit
1= A Power-on Reset has not occurred (set by firmware only)
0= A Power-on Reset occurred (must be set in software after a Power-on Reset occurs)
BOR: Brown-out Reset Status bit
1= A Brown-out Reset has not occurred (set by firmware only)
0= A Brown-out Reset occurred (must be set in software after a Brown-out Reset occurs)
Note 1: If SBOREN is enabled, its Reset state is ‘1’; otherwise, it is ‘0’.
2: The actual Reset value of POR is determined by the type of device Reset. See the notes following this
register and Section 4.6 “Reset State of Registers” for additional information.
Note 1: It is recommended that the POR bit be set after a Power-on Reset has been detected so that subsequent
Power-on Resets may be detected.
2: Brown-out Reset is said to have occurred when BOR is ‘0’ and POR is ‘1’ (assuming that POR was set to
‘1’ by software immediately after a Power-on Reset).
DS39761B-page 42
Preliminary
© 2007 Microchip Technology Inc.
PIC18F2682/2685/4682/4685
POR events are captured by the POR bit (RCON<1>).
The state of the bit is set to ‘0’ whenever a Power-on
4.2
Master Clear Reset (MCLR)
The MCLR pin provides a method for triggering an
external Reset of the device. A Reset is generated by
holding the pin low. These devices have a noise filter in
the MCLR Reset path which detects and ignores small
pulses.
Reset occurs; it does not change for any other Reset
event. POR is not reset to ‘1’ by any hardware event.
To capture multiple events, the user manually resets
the bit to ‘1’ in software following any Power-on Reset.
The MCLR pin is not driven low by any internal Resets,
including the WDT.
FIGURE 4-2:
EXTERNAL POWER-ON
RESET CIRCUIT (FOR
SLOW VDD POWER-UP)
In PIC18F2682/2685/4682/4685 devices, the MCLR
input can be disabled with the MCLRE Configuration
bit. When MCLR is disabled, the pin becomes a digital
input. See Section 10.5 “PORTE, TRISE and LATE
Registers” for more information.
VDD
VDD
D
R
R1
4.3
Power-on Reset (POR)
MCLR
PIC18FXXXX
A
Power-on Reset pulse is generated on-chip
C
whenever VDD rises above a certain threshold. This
allows the device to start in the initialized state when
VDD is adequate for operation.
Note 1: External Power-on Reset circuit is required
only if the VDD power-up slope is too slow.
The diode D helps discharge the capacitor
quickly when VDD powers down.
To take advantage of the POR circuitry, tie the MCLR
pin through a resistor (1 kΩ to 10 kΩ) to VDD. This will
eliminate external RC components usually needed to
create a Power-on Reset delay. A minimum rise rate for
VDD is specified (parameter D004). For a slow rise
time, see Figure 4-2.
2: R < 40 kΩ is recommended to make sure that
the voltage drop across R does not violate
the device’s electrical specification.
When the device starts normal operation (i.e., exits the
Reset condition), device operating parameters
(voltage, frequency, temperature, etc.) must be met to
ensure operation. If these conditions are not met, the
device must be held in Reset until the operating
conditions are met.
3: R1 ≥ 1 kΩ will limit any current flowing into
MCLR from external capacitor C, in the event
of MCLR/VPP pin breakdown, due to Electro-
static Discharge (ESD) or Electrical
Overstress (EOS).
© 2007 Microchip Technology Inc.
Preliminary
DS39761B-page 43
PIC18F2682/2685/4682/4685
Placing the BOR under software control gives the user
the additional flexibility of tailoring the application to its
environment without having to reprogram the device to
change BOR configuration. It also allows the user to
tailor device power consumption in software by elimi-
nating the incremental current that the BOR consumes.
While the BOR current is typically very small, it may
have some impact in low-power applications.
4.4
Brown-out Reset (BOR)
PIC18F2682/2685/4682/4685 devices implement a
BOR circuit that provides the user with a number of
configuration and power-saving options. The BOR
is controlled
by
the
BORV1:BORV0
and
BOREN1:BOREN0 Configuration bits. There are a total
of four BOR configurations which are summarized in
Table 4-1.
Note:
Even when BOR is under software control,
the Brown-out Reset voltage level is still
set by the BORV1:BORV0 Configuration
bits. It cannot be changed in software.
The BOR threshold is set by the BORV1:BORV0 bits. If
BOR is enabled (any value of BOREN1:BOREN0,
except ‘00’), any drop of VDD below VBOR (parameter
D005) for greater than TBOR (parameter 35) will reset
the device. A Reset may or may not occur if VDD falls
below VBOR for less than TBOR. The chip will remain in
Brown-out Reset until VDD rises above VBOR.
4.4.2
DETECTING BOR
When BOR is enabled, the BOR bit always resets to ‘0’
on any Brown-out Reset or Power-on Reset event. This
makes it difficult to determine if a Brown-out Reset
event has occurred just by reading the state of BOR
alone. A more reliable method is to simultaneously
check the state of both POR and BOR. This assumes
that the POR bit is reset to ‘1’ in software immediately
after any Power-on Reset event. IF BOR is ‘0’ while
POR is ‘1’, it can be reliably assumed that a Brown-out
Reset event has occurred.
If the Power-up Timer is enabled, it will be invoked after
VDD rises above VBOR; it then will keep the chip in
Reset for an additional time delay, TPWRT
(parameter 33). If VDD drops below VBOR while the
Power-up Timer is running, the chip will go back into a
Brown-out Reset and the Power-up Timer will be
initialized. Once VDD rises above VBOR, the Power-up
Timer will execute the additional time delay.
BOR and the Power-on Timer (PWRT) are
independently configured. Enabling Brown-out Reset
does not automatically enable the PWRT.
4.4.3
DISABLING BOR IN SLEEP MODE
When BOREN1:BOREN0 = 10, the BOR remains
under hardware control and operates as previously
described. Whenever the device enters Sleep mode,
however, the BOR is automatically disabled. When the
device returns to any other operating mode, BOR is
automatically re-enabled.
4.4.1
SOFTWARE ENABLED BOR
When BOREN1:BOREN0 = 01, the BOR can be
enabled or disabled by the user in software. This is
done with the control bit, SBOREN (RCON<6>).
Setting SBOREN enables the BOR to function as
previously described. Clearing SBOREN disables the
BOR entirely. The SBOREN bit operates only in this
mode; otherwise it is read as ‘0’.
This mode allows for applications to recover from
brown-out situations, while actively executing code,
when the device requires BOR protection the most. At
the same time, it saves additional power in Sleep mode
by eliminating the small incremental BOR current.
TABLE 4-1:
BOREN1
BOR CONFIGURATIONS
BOR Configuration
Status of
SBOREN
BOR Operation
BOREN0
(RCON<6>)
0
0
1
0
1
0
Unavailable BOR disabled; must be enabled by reprogramming the Configuration bits.
Available BOR enabled in software; operation controlled by SBOREN.
Unavailable BOR enabled in hardware in Run and Idle modes, disabled during Sleep
mode.
1
1
Unavailable BOR enabled in hardware; must be disabled by reprogramming the
Configuration bits.
DS39761B-page 44
Preliminary
© 2007 Microchip Technology Inc.
PIC18F2682/2685/4682/4685
4.5.3
PLL LOCK TIME-OUT
4.5
Device Reset Timers
With the PLL enabled in its PLL mode, the time-out
sequence following a Power-on Reset is slightly
different from other oscillator modes. A separate timer
is used to provide a fixed time-out that is sufficient for
the PLL to lock to the main oscillator frequency. This
PLL lock time-out (TPLL) is typically 2 ms and follows
the oscillator start-up time-out.
PIC18F2682/2685/4682/4685 devices incorporate
three separate on-chip timers that help regulate the
Power-on Reset process. Their main function is to
ensure that the device clock is stable before code is
executed. These timers are:
• Power-up Timer (PWRT)
• Oscillator Start-up Timer (OST)
• PLL Lock Time-out
4.5.4
TIME-OUT SEQUENCE
On power-up, the time-out sequence is as follows:
4.5.1
POWER-UP TIMER (PWRT)
1. After the POR pulse has cleared, PWRT time-out
is invoked (if enabled).
The Power-up Timer (PWRT) of PIC18F2682/2685/
4682/4685 devices is an 11-bit counter which uses the
INTRC source as the clock input. This yields an
approximate time interval of 2048 x 32 μs = 65.6 ms.
While the PWRT is counting, the device is held in
Reset.
2. Then, the OST is activated.
The total time-out will vary based on oscillator configu-
ration and the status of the PWRT. Figure 4-3,
Figure 4-4, Figure 4-5, Figure 4-6 and Figure 4-7 all
depict time-out sequences on power-up, with the
Power-up Timer enabled and the device operating in
HS Oscillator mode. Figures 4-3 through 4-6 also apply
to devices operating in XT or LP modes. For devices in
RC mode and with the PWRT disabled, on the other
hand, there will be no time-out at all.
The power-up time delay depends on the INTRC clock
and will vary from chip-to-chip due to temperature and
process variation. See DC parameter 33 for details.
The PWRT is enabled by clearing the PWRTEN
Configuration bit.
Since the time-outs occur from the POR pulse, if MCLR
is kept low long enough, all time-outs will expire.
Bringing MCLR high will begin execution immediately
(Figure 4-5). This is useful for testing purposes or to
synchronize more than one PIC18FXXXX device
operating in parallel.
4.5.2
OSCILLATOR START-UP TIMER
(OST)
The Oscillator Start-up Timer (OST) provides a
1024 oscillator cycle (from OSC1 input) delay after the
PWRT delay is over (parameter 33). This ensures that
the crystal oscillator or resonator has started and
stabilized.
The OST time-out is invoked only for XT, LP, HS and
HSPLL modes and only on Power-on Reset or on exit
from most power-managed modes.
TABLE 4-2:
Oscillator
TIME-OUT IN VARIOUS SITUATIONS
Power-up(2) and Brown-out
Exit From
Configuration
Power-Managed Mode
PWRTEN = 0
PWRTEN = 1
HSPLL
66 ms(1) + 1024 TOSC + 2 ms(2)
66 ms(1) + 1024 TOSC
66 ms(1)
1024 TOSC + 2 ms(2)
1024 TOSC + 2 ms(2)
HS, XT, LP
EC, ECIO
1024 TOSC
1024 TOSC
—
—
—
—
—
—
RC, RCIO
66 ms(1)
66 ms(1)
INTIO1, INTIO2
Note 1: 66 ms (65.5 ms) is the nominal Power-up Timer (PWRT) delay.
2: 2 ms is the nominal time required for the PLL to lock.
© 2007 Microchip Technology Inc.
Preliminary
DS39761B-page 45
PIC18F2682/2685/4682/4685
FIGURE 4-3:
TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD, VDD RISE < TPWRT)
VDD
MCLR
INTERNAL POR
TPWRT
PWRT TIME-OUT
OST TIME-OUT
TOST
INTERNAL RESET
FIGURE 4-4:
TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 1
VDD
MCLR
INTERNAL POR
TPWRT
PWRT TIME-OUT
OST TIME-OUT
TOST
INTERNAL RESET
FIGURE 4-5:
TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 2
VDD
MCLR
INTERNAL POR
TPWRT
PWRT TIME-OUT
OST TIME-OUT
TOST
INTERNAL RESET
DS39761B-page 46
Preliminary
© 2007 Microchip Technology Inc.
PIC18F2682/2685/4682/4685
FIGURE 4-6:
SLOW RISE TIME (MCLR TIED TO VDD, VDD RISE > TPWRT)
5V
VDD
1V
0V
MCLR
INTERNAL POR
TPWRT
PWRT TIME-OUT
TOST
OST TIME-OUT
INTERNAL RESET
FIGURE 4-7:
TIME-OUT SEQUENCE ON POR w/PLL ENABLED (MCLR TIED TO VDD)
VDD
MCLR
INTERNAL POR
TPWRT
PWRT TIME-OUT
OST TIME-OUT
TOST
TPLL
PLL TIME-OUT
INTERNAL RESET
Note:
TOST = 1024 clock cycles.
TPLL ≈ 2 ms max. First three stages of the Power-up Timer.
© 2007 Microchip Technology Inc.
Preliminary
DS39761B-page 47
PIC18F2682/2685/4682/4685
PD, POR and BOR, are set or cleared differently in
different Reset situations, as indicated in Table 4-3.
These bits are used in software to determine the nature
of the Reset.
4.6
Reset State of Registers
Most registers are unaffected by a Reset. Their status
is unknown on POR and unchanged by all other
Resets. The other registers are forced to a “Reset
state” depending on the type of Reset that occurred.
Table 4-4 describes the Reset states for all of the
Special Function Registers. These are categorized by
Power-on and Brown-out Resets, Master Clear and
WDT Resets and WDT wake-ups.
Most registers are not affected by a WDT wake-up,
since this is viewed as the resumption of normal
operation. Status bits from the RCON register, RI, TO,
TABLE 4-3:
STATUS BITS, THEIR SIGNIFICANCE AND THE INITIALIZATION CONDITION FOR
RCON REGISTER
RCON Register
STKPTR Register
Program
Counter
Condition
SBOREN
RI
TO
PD POR BOR STKFUL STKUNF
Power-on Reset
RESETinstruction
Brown-out Reset
0000h
0000h
0000h
0000h
1
1
0
1
u
1
u
1
1
1
u
1
u
0
u
u
u
0
u
0
u
0
u
u
u
0
u
u
u
u(2)
u(2)
u(2)
MCLR during power-managed Run
modes
MCLR during power-managed Idle
modes and Sleep mode
0000h
0000h
u(2)
u(2)
u
u
1
0
0
u
u
u
u
u
u
u
u
u
WDT time-out during full power or
power-managed Run modes
MCLR during full power execution
0000h
0000h
0000h
u(2)
u(2)
u(2)
u
u
u
u
u
u
u
u
u
u
u
u
u
u
u
u
1
u
u
u
1
Stack Full Reset (STVREN = 1)
Stack Underflow Reset
(STVREN = 1)
Stack Underflow Error (not an actual
Reset, STVREN = 0)
0000h
PC + 2
u(2)
u(2)
u(2)
u
u
u
u
0
u
u
0
0
u
u
u
u
u
u
u
u
u
1
u
u
WDT time-out during
power-managed Idle or Sleep modes
Interrupt exit from
PC + 2(1)
power-managed modes
Legend: u= unchanged
Note 1: When the wake-up is due to an interrupt and the GIEH or GIEL bit is set, the PC is loaded with the
interrupt vector (008h or 0018h).
2: Reset state is ‘1’ for POR and unchanged for all other Resets when software BOR is enabled
(BOREN1:BOREN0 Configuration bits = 01and SBOREN = 1); otherwise, the Reset state is ‘0’.
DS39761B-page 48
Preliminary
© 2007 Microchip Technology Inc.
PIC18F2682/2685/4682/4685
TABLE 4-4:
Register
INITIALIZATION CONDITIONS FOR ALL REGISTERS
MCLR Resets,
WDT Reset,
Power-on Reset,
Brown-out Reset
Wake-up via WDT
or Interrupt
Applicable Devices
RESETInstruction,
Stack Resets
TOSU
2682 2685 4682 4685
2682 2685 4682 4685
2682 2685 4682 4685
2682 2685 4682 4685
2682 2685 4682 4685
2682 2685 4682 4685
2682 2685 4682 4685
2682 2685 4682 4685
2682 2685 4682 4685
2682 2685 4682 4685
2682 2685 4682 4685
2682 2685 4682 4685
2682 2685 4682 4685
2682 2685 4682 4685
2682 2685 4682 4685
2682 2685 4682 4685
2682 2685 4682 4685
2682 2685 4682 4685
2682 2685 4682 4685
2682 2685 4682 4685
2682 2685 4682 4685
2682 2685 4682 4685
2682 2685 4682 4685
2682 2685 4682 4685
2682 2685 4682 4685
2682 2685 4682 4685
2682 2685 4682 4685
2682 2685 4682 4685
2682 2685 4682 4685
2682 2685 4682 4685
2682 2685 4682 4685
---0 0000
0000 0000
0000 0000
00-0 0000
---0 0000
0000 0000
0000 0000
--00 0000
0000 0000
0000 0000
0000 0000
xxxx xxxx
xxxx xxxx
0000 000x
1111 -1-1
11-0 0-00
N/A
---0 0000
0000 0000
0000 0000
uu-0 0000
---0 0000
0000 0000
0000 0000
--00 0000
0000 0000
0000 0000
0000 0000
uuuu uuuu
uuuu uuuu
0000 000u
1111 -1-1
11-0 0-00
N/A
---0 uuuu(3)
uuuu uuuu(3)
uuuu uuuu(3)
uu-u uuuu(3)
---u uuuu
uuuu uuuu
PC + 2(2)
--uu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu(1)
uuuu -u-u(1)
uu-u u-uu(1)
N/A
TOSH
TOSL
STKPTR
PCLATU
PCLATH
PCL
TBLPTRU
TBLPTRH
TBLPTRL
TABLAT
PRODH
PRODL
INTCON
INTCON2
INTCON3
INDF0
POSTINC0
POSTDEC0
PREINC0
PLUSW0
FSR0H
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
---- 0000
xxxx xxxx
xxxx xxxx
N/A
---- 0000
uuuu uuuu
uuuu uuuu
N/A
---- uuuu
uuuu uuuu
uuuu uuuu
N/A
FSR0L
WREG
INDF1
POSTINC1
POSTDEC1
PREINC1
PLUSW1
FSR1H
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
---- 0000
xxxx xxxx
---- 0000
uuuu uuuu
---- uuuu
uuuu uuuu
FSR1L
Legend: u= unchanged, x= unknown, -= unimplemented bit, read as ‘0’, q= value depends on condition.
Shaded cells indicate conditions do not apply for the designated device.
Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).
2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt
vector (0008h or 0018h).
3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are
updated with the current value of the PC. The STKPTR is modified to point to the next location in the
hardware stack.
4: See Table 4-3 for Reset value for specific condition.
5: Bits 6 and 7 of PORTA, LATA and TRISA are enabled depending on the oscillator mode selected. When
not enabled as PORTA pins, they are disabled and read ‘0’.
6: This register reads all ‘0’s until the ECAN™ technology is set up in Mode 1 or Mode 2.
© 2007 Microchip Technology Inc.
Preliminary
DS39761B-page 49
PIC18F2682/2685/4682/4685
TABLE 4-4:
INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)
MCLR Resets,
Power-on Reset,
Brown-out Reset
WDT Reset,
RESETInstruction,
Stack Resets
Wake-up via WDT
or Interrupt
Register
Applicable Devices
BSR
2682 2685 4682 4685
2682 2685 4682 4685
2682 2685 4682 4685
2682 2685 4682 4685
2682 2685 4682 4685
2682 2685 4682 4685
2682 2685 4682 4685
2682 2685 4682 4685
2682 2685 4682 4685
2682 2685 4682 4685
2682 2685 4682 4685
2682 2685 4682 4685
2682 2685 4682 4685
2682 2685 4682 4685
2682 2685 4682 4685
2682 2685 4682 4685
2682 2685 4682 4685
2682 2685 4682 4685
2682 2685 4682 4685
2682 2685 4682 4685
2682 2685 4682 4685
2682 2685 4682 4685
2682 2685 4682 4685
2682 2685 4682 4685
2682 2685 4682 4685
2682 2685 4682 4685
2682 2685 4682 4685
2682 2685 4682 4685
2682 2685 4682 4685
2682 2685 4682 4685
2682 2685 4682 4685
---- 0000
N/A
---- 0000
N/A
---- uuuu
N/A
INDF2
POSTINC2
POSTDEC2
PREINC2
PLUSW2
FSR2H
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
---- 0000
xxxx xxxx
---x xxxx
0000 0000
xxxx xxxx
1111 1111
0100 q000
0-00 0101
---- ---0
0q-1 11q0
xxxx xxxx
xxxx xxxx
0000 0000
0000 0000
1111 1111
-000 0000
xxxx xxxx
0000 0000
0000 0000
0000 0000
0000 0000
xxxx xxxx
xxxx xxxx
--00 0000
--00 0qqq
---- 0000
uuuu uuuu
---u uuuu
0000 0000
uuuu uuuu
1111 1111
0100 00q0
0-00 0101
---- ---0
0q-q qquu
uuuu uuuu
uuuu uuuu
u0uu uuuu
0000 0000
1111 1111
-000 0000
uuuu uuuu
0000 0000
0000 0000
0000 0000
0000 0000
uuuu uuuu
uuuu uuuu
--00 0000
--00 0qqq
---- uuuu
uuuu uuuu
---u uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuqu
0-uu uuuu
---- ---u
uq-u qquu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
1111 1111
-uuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
--uu uuuu
--uu uuuu
FSR2L
STATUS
TMR0H
TMR0L
T0CON
OSCCON
HLVDCON
WDTCON
RCON(4)
TMR1H
TMR1L
T1CON
TMR2
PR2
T2CON
SSPBUF
SSPADD
SSPSTAT
SSPCON1
SSPCON2
ADRESH
ADRESL
ADCON0
ADCON1
Legend: u= unchanged, x= unknown, -= unimplemented bit, read as ‘0’, q= value depends on condition.
Shaded cells indicate conditions do not apply for the designated device.
Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).
2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt
vector (0008h or 0018h).
3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are
updated with the current value of the PC. The STKPTR is modified to point to the next location in the
hardware stack.
4: See Table 4-3 for Reset value for specific condition.
5: Bits 6 and 7 of PORTA, LATA and TRISA are enabled depending on the oscillator mode selected. When
not enabled as PORTA pins, they are disabled and read ‘0’.
6: This register reads all ‘0’s until the ECAN™ technology is set up in Mode 1 or Mode 2.
DS39761B-page 50
Preliminary
© 2007 Microchip Technology Inc.
PIC18F2682/2685/4682/4685
TABLE 4-4:
Register
INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)
MCLR Resets,
WDT Reset,
Power-on Reset,
Brown-out Reset
Wake-up via WDT
or Interrupt
Applicable Devices
RESETInstruction,
Stack Resets
ADCON2
CCPR1H
CCPR1L
CCP1CON
ECCPR1H
ECCPR1L
ECCP1CON
BAUDCON
ECCP1DEL
ECCP1AS
CVRCON
CMCON
TMR3H
2682 2685 4682 4685
2682 2685 4682 4685
2682 2685 4682 4685
2682 2685 4682 4685
2682 2685 4682 4685
2682 2685 4682 4685
2682 2685 4682 4685
2682 2685 4682 4685
2682 2685 4682 4685
2682 2685 4682 4685
2682 2685 4682 4685
2682 2685 4682 4685
2682 2685 4682 4685
2682 2685 4682 4685
2682 2685 4682 4685
2682 2685 4682 4685
2682 2685 4682 4685
2682 2685 4682 4685
2682 2685 4682 4685
2682 2685 4682 4685
2682 2685 4682 4685
2682 2685 4682 4685
2682 2685 4682 4685
2682 2685 4682 4685
2682 2685 4682 4685
2682 2685 4682 4685
2682 2685 4682 4685
2682 2685 4682 4685
2682 2685 4682 4685
2682 2685 4682 4685
2682 2685 4682 4685
0-00 0000
xxxx xxxx
xxxx xxxx
--00 0000
xxxx xxxx
xxxx xxxx
0000 0000
01-0 0-00
0000 0000
0000 0000
0000 0000
0000 0000
xxxx xxxx
xxxx xxxx
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0010
0000 000x
---- --00
0000 0000
0000 0000
0000 0000
xx-0 x000
1111 1111
0000 0000
0000 0000
11-1 1111
1--1 111-
0-00 0000
uuuu uuuu
uuuu uuuu
--00 0000
uuuu uuuu
uuuu uuuu
0000 0000
01-0 0-00
0000 0000
0000 0000
0000 0000
0000 0000
uuuu uuuu
uuuu uuuu
uuuu uuuu
0000 0000
0000 0000
0000 0000
0000 0000
0000 0010
0000 000x
---- --00
0000 0000
0000 0000
0000 0000
uu-0 u000
1111 1111
0000 0000
0000 0000
11-1 1111
1--1 111-
u-uu uuuu
uuuu uuuu
uuuu uuuu
--uu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
--uu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
---- --uu
uuuu uuuu
uuuu uuuu
0000 0000
uu-0 u000
uuuu uuuu
uuuu uuuu
uuuu uuuu
uu-u uuuu
u--u uuu-
TMR3L
T3CON
SPBRGH
SPBRG
RCREG
TXREG
TXSTA
RCSTA
EEADRH
EEADR
EEDATA
EECON2
EECON1
IPR3
PIR3
PIE3
IPR2
Legend: u= unchanged, x= unknown, -= unimplemented bit, read as ‘0’, q= value depends on condition.
Shaded cells indicate conditions do not apply for the designated device.
Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).
2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt
vector (0008h or 0018h).
3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are
updated with the current value of the PC. The STKPTR is modified to point to the next location in the
hardware stack.
4: See Table 4-3 for Reset value for specific condition.
5: Bits 6 and 7 of PORTA, LATA and TRISA are enabled depending on the oscillator mode selected. When
not enabled as PORTA pins, they are disabled and read ‘0’.
6: This register reads all ‘0’s until the ECAN™ technology is set up in Mode 1 or Mode 2.
© 2007 Microchip Technology Inc.
Preliminary
DS39761B-page 51
PIC18F2682/2685/4682/4685
TABLE 4-4:
INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)
MCLR Resets,
Power-on Reset,
Brown-out Reset
WDT Reset,
RESETInstruction,
Stack Resets
Wake-up via WDT
or Interrupt
Register
Applicable Devices
PIR2
PIE2
IPR1
PIR1
PIE1
2682 2685 4682 4685
2682 2685 4682 4685
2682 2685 4682 4685
2682 2685 4682 4685
2682 2685 4682 4685
2682 2685 4682 4685
2682 2685 4682 4685
2682 2685 4682 4685
2682 2685 4682 4685
2682 2685 4682 4685
2682 2685 4682 4685
2682 2685 4682 4685
2682 2685 4682 4685
2682 2685 4682 4685
2682 2685 4682 4685
2682 2685 4682 4685
2682 2685 4682 4685
2682 2685 4682 4685
2682 2685 4682 4685
2682 2685 4682 4685
2682 2685 4682 4685
2682 2685 4682 4685
2682 2685 4682 4685
2682 2685 4682 4685
2682 2685 4682 4685
2682 2685 4682 4685
2682 2685 4682 4685
2682 2685 4682 4685
2682 2685 4682 4685
2682 2685 4682 4685
2682 2685 4682 4685
00-0 0000
0--0 000-
00-0 0000
0--0 000-
1111 1111
-111 1111
0000 0000
-000 0000
0000 0000
-000 0000
0q-0 0000
0000 -111
1111 1111
1111 1111
1111 1111
1111 1111(5)
---- -xxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx(5)
---- x000
xxxx xxxx
xxxx xxxx
xxxx xxxx
xx0x 0000(5)
0001 0000
0000 0000
0000 0000
0000 0000
--00 ----
00-0 0000
0--0 000-
00-0 0000
0--0 000-
1111 1111
-111 1111
0000 0000
-000 0000
0000 0000
-000 0000
0q-0 0000
0000 -111
1111 1111
1111 1111
1111 1111
1111 1111(5)
---- -uuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu(5)
---- x000
uuuu uuuu
uuuu uuuu
uuuu uuuu
uu0u 0000(5)
0001 0000
0000 0000
0000 0000
0000 0000
--00 ----
uu-u uuuu(1)
u--u uuu-(1)
uu-u uuuu
u--u uuu-
uuuu uuuu
-uuu uuuu
uuuu uuuu(1)
-uuu uuuu
uuuu uuuu
-uuu uuuu
uu-u uuuu
uuuu -uuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu(5)
---- -uuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu(5)
---- uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu(5)
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
--uu ----
OSCTUNE
TRISE
TRISD
TRISC
TRISB
TRISA(5)
LATE
LATD
LATC
LATB
LATA(5)
PORTE
PORTD
PORTC
PORTB
PORTA(5)
ECANCON
TXERRCNT
RXERRCNT
COMSTAT
CIOCON
Legend: u= unchanged, x= unknown, -= unimplemented bit, read as ‘0’, q= value depends on condition.
Shaded cells indicate conditions do not apply for the designated device.
Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).
2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt
vector (0008h or 0018h).
3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are
updated with the current value of the PC. The STKPTR is modified to point to the next location in the
hardware stack.
4: See Table 4-3 for Reset value for specific condition.
5: Bits 6 and 7 of PORTA, LATA and TRISA are enabled depending on the oscillator mode selected. When
not enabled as PORTA pins, they are disabled and read ‘0’.
6: This register reads all ‘0’s until the ECAN™ technology is set up in Mode 1 or Mode 2.
DS39761B-page 52
Preliminary
© 2007 Microchip Technology Inc.
PIC18F2682/2685/4682/4685
TABLE 4-4:
Register
INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)
MCLR Resets,
WDT Reset,
Power-on Reset,
Brown-out Reset
Wake-up via WDT
or Interrupt
Applicable Devices
RESETInstruction,
Stack Resets
BRGCON3
BRGCON2
BRGCON1
CANCON
CANSTAT
RXB0D7
2682 2685 4682 4685
2682 2685 4682 4685
2682 2685 4682 4685
2682 2685 4682 4685
2682 2685 4682 4685
2682 2685 4682 4685
2682 2685 4682 4685
2682 2685 4682 4685
2682 2685 4682 4685
2682 2685 4682 4685
2682 2685 4682 4685
2682 2685 4682 4685
2682 2685 4682 4685
2682 2685 4682 4685
2682 2685 4682 4685
2682 2685 4682 4685
2682 2685 4682 4685
2682 2685 4682 4685
2682 2685 4682 4685
2682 2685 4682 4685
2682 2685 4682 4685
2682 2685 4682 4685
2682 2685 4682 4685
2682 2685 4682 4685
2682 2685 4682 4685
2682 2685 4682 4685
2682 2685 4682 4685
2682 2685 4682 4685
2682 2685 4682 4685
2682 2685 4682 4685
2682 2685 4682 4685
00-- -000
0000 0000
0000 0000
1000 000-
100- 000-
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
-xxx xxxx
xxxx xxxx
xxxx xxxx
xxxx x-xx
xxxx xxxx
000- 0000
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
-xxx xxxx
xxxx xxxx
xxxx xxxx
xxxx x-xx
00-- -000
0000 0000
0000 0000
1000 000-
100- 000-
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
-uuu uuuu
uuuu uuuu
uuuu uuuu
uuuu u-uu
uuuu uuuu
000- 0000
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
-uuu uuuu
uuuu uuuu
uuuu uuuu
uuuu u-uu
uu-- -uuu
uuuu uuuu
uuuu uuuu
uuuu uuu-
uuu- uuu-
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
-uuu uuuu
uuuu uuuu
uuuu uuuu
uuuu u-uu
uuuu uuuu
uuu- uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
-uuu uuuu
uuuu uuuu
uuuu uuuu
uuuu u-uu
RXB0D6
RXB0D5
RXB0D4
RXB0D3
RXB0D2
RXB0D1
RXB0D0
RXB0DLC
RXB0EIDL
RXB0EIDH
RXB0SIDL
RXB0SIDH
RXB0CON
RXB1D7
RXB1D6
RXB1D5
RXB1D4
RXB1D3
RXB1D2
RXB1D1
RXB1D0
RXB1DLC
RXB1EIDL
RXB1EIDH
RXB1SIDL
Legend: u= unchanged, x= unknown, -= unimplemented bit, read as ‘0’, q= value depends on condition.
Shaded cells indicate conditions do not apply for the designated device.
Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).
2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt
vector (0008h or 0018h).
3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are
updated with the current value of the PC. The STKPTR is modified to point to the next location in the
hardware stack.
4: See Table 4-3 for Reset value for specific condition.
5: Bits 6 and 7 of PORTA, LATA and TRISA are enabled depending on the oscillator mode selected. When
not enabled as PORTA pins, they are disabled and read ‘0’.
6: This register reads all ‘0’s until the ECAN™ technology is set up in Mode 1 or Mode 2.
© 2007 Microchip Technology Inc.
Preliminary
DS39761B-page 53
PIC18F2682/2685/4682/4685
TABLE 4-4:
INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)
MCLR Resets,
Power-on Reset,
Brown-out Reset
WDT Reset,
RESETInstruction,
Stack Resets
Wake-up via WDT
or Interrupt
Register
Applicable Devices
RXB1SIDH
RXB1CON
TXB0D7
2682 2685 4682 4685
2682 2685 4682 4685
2682 2685 4682 4685
2682 2685 4682 4685
2682 2685 4682 4685
2682 2685 4682 4685
2682 2685 4682 4685
2682 2685 4682 4685
2682 2685 4682 4685
2682 2685 4682 4685
2682 2685 4682 4685
2682 2685 4682 4685
2682 2685 4682 4685
2682 2685 4682 4685
2682 2685 4682 4685
2682 2685 4682 4685
2682 2685 4682 4685
2682 2685 4682 4685
2682 2685 4682 4685
2682 2685 4682 4685
2682 2685 4682 4685
2682 2685 4682 4685
2682 2685 4682 4685
2682 2685 4682 4685
2682 2685 4682 4685
2682 2685 4682 4685
2682 2685 4682 4685
2682 2685 4682 4685
2682 2685 4682 4685
2682 2685 4682 4685
2682 2685 4682 4685
xxxx xxxx
000- 0000
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
-x-- xxxx
xxxx xxxx
xxxx xxxx
xxx- x-xx
xxxx xxxx
0000 0-00
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
-x-- xxxx
xxxx xxxx
xxxx xxxx
xxx- x-xx
xxxx xxxx
0000 0-00
xxxx xxxx
uuuu uuuu
000- 0000
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
-u-- uuuu
uuuu uuuu
uuuu uuuu
uuu- u-uu
uuuu uuuu
0000 0-00
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
-u-- uuuu
uuuu uuuu
uuuu uuuu
uuu- u-uu
uuuu uuuu
0000 0-00
uuuu uuuu
uuuu uuuu
uuu- uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
-u-- uuuu
uuuu uuuu
uuuu uuuu
uuu- u-uu
uuuu uuuu
uuuu u-uu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
-u-- uuuu
uuuu uuuu
uuuu uuuu
uuu- uu-u
uuuu uuuu
uuuu u-uu
0uuu uuuu
TXB0D6
TXB0D5
TXB0D4
TXB0D3
TXB0D2
TXB0D1
TXB0D0
TXB0DLC
TXB0EIDL
TXB0EIDH
TXB0SIDL
TXB0SIDH
TXB0CON
TXB1D7
TXB1D6
TXB1D5
TXB1D4
TXB1D3
TXB1D2
TXB1D1
TXB1D0
TXB1DLC
TXB1EIDL
TXB1EIDH
TXB1SIDL
TXB1SIDH
TXB1CON
TXB2D7
Legend: u= unchanged, x= unknown, -= unimplemented bit, read as ‘0’, q= value depends on condition.
Shaded cells indicate conditions do not apply for the designated device.
Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).
2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt
vector (0008h or 0018h).
3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are
updated with the current value of the PC. The STKPTR is modified to point to the next location in the
hardware stack.
4: See Table 4-3 for Reset value for specific condition.
5: Bits 6 and 7 of PORTA, LATA and TRISA are enabled depending on the oscillator mode selected. When
not enabled as PORTA pins, they are disabled and read ‘0’.
6: This register reads all ‘0’s until the ECAN™ technology is set up in Mode 1 or Mode 2.
DS39761B-page 54
Preliminary
© 2007 Microchip Technology Inc.
PIC18F2682/2685/4682/4685
TABLE 4-4:
Register
INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)
MCLR Resets,
WDT Reset,
Power-on Reset,
Brown-out Reset
Wake-up via WDT
or Interrupt
Applicable Devices
RESETInstruction,
Stack Resets
TXB2D6
2682 2685 4682 4685
2682 2685 4682 4685
2682 2685 4682 4685
2682 2685 4682 4685
2682 2685 4682 4685
2682 2685 4682 4685
2682 2685 4682 4685
2682 2685 4682 4685
2682 2685 4682 4685
2682 2685 4682 4685
2682 2685 4682 4685
2682 2685 4682 4685
2682 2685 4682 4685
2682 2685 4682 4685
2682 2685 4682 4685
2682 2685 4682 4685
2682 2685 4682 4685
2682 2685 4682 4685
2682 2685 4682 4685
2682 2685 4682 4685
2682 2685 4682 4685
2682 2685 4682 4685
2682 2685 4682 4685
2682 2685 4682 4685
2682 2685 4682 4685
2682 2685 4682 4685
2682 2685 4682 4685
2682 2685 4682 4685
2682 2685 4682 4685
2682 2685 4682 4685
2682 2685 4682 4685
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
-x-- xxxx
xxxx xxxx
xxxx xxxx
xxxx x-xx
xxx- x-xx
0000 0-00
xxxx xxxx
xxxx xxxx
xxx- x-xx
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxx- x-xx
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxx- x-xx
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxx- x-xx
xxxx xxxx
xxxx xxxx
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
-u-- uuuu
uuuu uuuu
uuuu uuuu
uuuu u-uu
uuu- u-uu
0000 0-00
uuuu uuuu
uuuu uuuu
uuu- u-uu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuu- u-uu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuu- u-uu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuu- u-uu
uuuu uuuu
uuuu uuuu
uuuu uuuu
0uuu uuuu
0uuu uuuu
0uuu uuuu
0uuu uuuu
0uuu uuuu
0uuu uuuu
0uuu uuuu
-u-- uuuu
uuuu uuuu
uuuu uuuu
uuuu u-uu
uuu- u-uu
uuuu u-uu
uuuu uuuu
uuuu uuuu
uuu- u-uu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuu- u-uu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuu- u-uu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuu- u-uu
uuuu uuuu
uuuu uuuu
uuuu uuuu
TXB2D5
TXB2D4
TXB2D3
TXB2D2
TXB2D1
TXB2D0
TXB2DLC
TXB2EIDL
TXB2EIDH
TXB2SIDL
TXB2SIDH
TXB2CON
RXM1EIDL
RXM1EIDH
RXM1SIDL
RXM1SIDH
RXM0EIDL
RXM0EIDH
RXM0SIDL
RXM0SIDH
RXF5EIDL
RXF5EIDH
RXF5SIDL
RXF5SIDH
RXF4EIDL
RXF4EIDH
RXF4SIDL
RXF4SIDH
RXF3EIDL
RXF3EIDH
Legend: u= unchanged, x= unknown, -= unimplemented bit, read as ‘0’, q= value depends on condition.
Shaded cells indicate conditions do not apply for the designated device.
Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).
2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt
vector (0008h or 0018h).
3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are
updated with the current value of the PC. The STKPTR is modified to point to the next location in the
hardware stack.
4: See Table 4-3 for Reset value for specific condition.
5: Bits 6 and 7 of PORTA, LATA and TRISA are enabled depending on the oscillator mode selected. When
not enabled as PORTA pins, they are disabled and read ‘0’.
6: This register reads all ‘0’s until the ECAN™ technology is set up in Mode 1 or Mode 2.
© 2007 Microchip Technology Inc.
Preliminary
DS39761B-page 55
PIC18F2682/2685/4682/4685
TABLE 4-4:
INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)
MCLR Resets,
Power-on Reset,
Brown-out Reset
WDT Reset,
RESETInstruction,
Stack Resets
Wake-up via WDT
or Interrupt
Register
Applicable Devices
RXF3SIDL
RXF3SIDH
RXF2EIDL
RXF2EIDH
RXF2SIDL
RXF2SIDH
RXF1EIDL
RXF1EIDH
RXF1SIDL
RXF1SIDH
RXF0EIDL
RXF0EIDH
RXF0SIDL
RXF0SIDH
B5D7(6)
B5D6(6)
B5D5(6)
B5D4(6)
B5D3(6)
B5D2(6)
B5D1(6)
B5D0(6)
2682 2685 4682 4685
2682 2685 4682 4685
2682 2685 4682 4685
2682 2685 4682 4685
2682 2685 4682 4685
2682 2685 4682 4685
2682 2685 4682 4685
2682 2685 4682 4685
2682 2685 4682 4685
2682 2685 4682 4685
2682 2685 4682 4685
2682 2685 4682 4685
2682 2685 4682 4685
2682 2685 4682 4685
2682 2685 4682 4685
2682 2685 4682 4685
2682 2685 4682 4685
2682 2685 4682 4685
2682 2685 4682 4685
2682 2685 4682 4685
2682 2685 4682 4685
2682 2685 4682 4685
2682 2685 4682 4685
2682 2685 4682 4685
2682 2685 4682 4685
2682 2685 4682 4685
2682 2685 4682 4685
2682 2685 4682 4685
2682 2685 4682 4685
2682 2685 4682 4685
2682 2685 4682 4685
xxx- x-xx
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxx- x-xx
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxx- x-xx
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxx- x-xx
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
-xxx xxxx
xxxx xxxx
xxxx xxxx
xxxx x-xx
xxxx x-xx
0000 0000
xxxx xxxx
xxxx xxxx
xxxx xxxx
uuu- u-uu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuu- u-uu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuu- u-uu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuu- u-uu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
-uuu uuuu
uuuu uuuu
uuuu uuuu
uuuu u-uu
uuuu u-uu
0000 0000
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuu- u-uu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuu- u-uu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuu- u-uu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuu- u-uu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
-uuu uuuu
uuuu uuuu
uuuu uuuu
uuuu u-uu
uuuu u-uu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
B5DLC(6)
B5EIDL(6)
B5EIDH(6)
B5SIDL(6)
B5SIDH(6)
B5CON(6)
B4D7(6)
B4D6(6)
B4D5(6)
Legend: u= unchanged, x= unknown, -= unimplemented bit, read as ‘0’, q= value depends on condition.
Shaded cells indicate conditions do not apply for the designated device.
Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).
2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt
vector (0008h or 0018h).
3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are
updated with the current value of the PC. The STKPTR is modified to point to the next location in the
hardware stack.
4: See Table 4-3 for Reset value for specific condition.
5: Bits 6 and 7 of PORTA, LATA and TRISA are enabled depending on the oscillator mode selected. When
not enabled as PORTA pins, they are disabled and read ‘0’.
6: This register reads all ‘0’s until the ECAN™ technology is set up in Mode 1 or Mode 2.
DS39761B-page 56
Preliminary
© 2007 Microchip Technology Inc.
PIC18F2682/2685/4682/4685
TABLE 4-4:
Register
INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)
MCLR Resets,
WDT Reset,
Power-on Reset,
Brown-out Reset
Wake-up via WDT
or Interrupt
Applicable Devices
RESETInstruction,
Stack Resets
B4D4(6)
B4D3(6)
B4D2(6)
B4D1(6)
2682 2685 4682 4685
2682 2685 4682 4685
2682 2685 4682 4685
2682 2685 4682 4685
2682 2685 4682 4685
2682 2685 4682 4685
2682 2685 4682 4685
2682 2685 4682 4685
2682 2685 4682 4685
2682 2685 4682 4685
2682 2685 4682 4685
2682 2685 4682 4685
2682 2685 4682 4685
2682 2685 4682 4685
2682 2685 4682 4685
2682 2685 4682 4685
2682 2685 4682 4685
2682 2685 4682 4685
2682 2685 4682 4685
2682 2685 4682 4685
2682 2685 4682 4685
2682 2685 4682 4685
2682 2685 4682 4685
2682 2685 4682 4685
2682 2685 4682 4685
2682 2685 4682 4685
2682 2685 4682 4685
2682 2685 4682 4685
2682 2685 4682 4685
2682 2685 4682 4685
2682 2685 4682 4685
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
-xxx xxxx
xxxx xxxx
xxxx xxxx
xxxx x-xx
xxxx xxxx
0000 0000
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
-xxx xxxx
xxxx xxxx
xxxx xxxx
xxxx x-xx
xxxx xxxx
0000 0000
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
-uuu uuuu
uuuu uuuu
uuuu uuuu
uuuu u-uu
uuuu uuuu
0000 0000
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
-uuu uuuu
uuuu uuuu
uuuu uuuu
uuuu u-uu
uuuu uuuu
0000 0000
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
-uuu uuuu
uuuu uuuu
uuuu uuuu
uuuu u-uu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
-uuu uuuu
uuuu uuuu
uuuu uuuu
uuuu u-uu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
B4D0(6)
B4DLC(6)
B4EIDL(6)
B4EIDH(6)
B4SIDL(6)
B4SIDH(6)
B4CON(6)
B3D7(6)
B3D6(6)
B3D5(6)
B3D4(6)
B3D3(6)
B3D2(6)
B3D1(6)
B3D0(6)
B3DLC(6)
B3EIDL(6)
B3EIDH(6)
B3SIDL(6)
B3SIDH(6)
B3CON(6)
B2D7(6)
B2D6(6)
B2D5(6)
B2D4(6)
B2D3(6)
B2D2(6)
Legend: u= unchanged, x= unknown, -= unimplemented bit, read as ‘0’, q= value depends on condition.
Shaded cells indicate conditions do not apply for the designated device.
Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).
2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt
vector (0008h or 0018h).
3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are
updated with the current value of the PC. The STKPTR is modified to point to the next location in the
hardware stack.
4: See Table 4-3 for Reset value for specific condition.
5: Bits 6 and 7 of PORTA, LATA and TRISA are enabled depending on the oscillator mode selected. When
not enabled as PORTA pins, they are disabled and read ‘0’.
6: This register reads all ‘0’s until the ECAN™ technology is set up in Mode 1 or Mode 2.
© 2007 Microchip Technology Inc.
Preliminary
DS39761B-page 57
PIC18F2682/2685/4682/4685
TABLE 4-4:
INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)
MCLR Resets,
Power-on Reset,
Brown-out Reset
WDT Reset,
RESETInstruction,
Stack Resets
Wake-up via WDT
or Interrupt
Register
Applicable Devices
B2D1(6)
B2D0(6)
2682 2685 4682 4685
2682 2685 4682 4685
2682 2685 4682 4685
2682 2685 4682 4685
2682 2685 4682 4685
2682 2685 4682 4685
2682 2685 4682 4685
2682 2685 4682 4685
2682 2685 4682 4685
2682 2685 4682 4685
2682 2685 4682 4685
2682 2685 4682 4685
2682 2685 4682 4685
2682 2685 4682 4685
2682 2685 4682 4685
2682 2685 4682 4685
2682 2685 4682 4685
2682 2685 4682 4685
2682 2685 4682 4685
2682 2685 4682 4685
2682 2685 4682 4685
2682 2685 4682 4685
2682 2685 4682 4685
2682 2685 4682 4685
2682 2685 4682 4685
2682 2685 4682 4685
2682 2685 4682 4685
2682 2685 4682 4685
2682 2685 4682 4685
2682 2685 4682 4685
2682 2685 4682 4685
xxxx xxxx
xxxx xxxx
-xxx xxxx
xxxx xxxx
xxxx xxxx
xxxx x-xx
xxxx xxxx
0000 0000
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
-xxx xxxx
xxxx xxxx
xxxx xxxx
xxxx x-xx
xxxx xxxx
0000 0000
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
-xxx xxxx
uuuu uuuu
uuuu uuuu
-uuu uuuu
uuuu uuuu
uuuu uuuu
uuuu u-uu
uuuu uuuu
0000 0000
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
-uuu uuuu
uuuu uuuu
uuuu uuuu
uuuu u-uu
uuuu uuuu
0000 0000
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
-uuu uuuu
uuuu uuuu
uuuu uuuu
-uuu uuuu
uuuu uuuu
uuuu uuuu
uuuu u-uu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
-uuu uuuu
uuuu uuuu
uuuu uuuu
uuuu u-uu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
-uuu uuuu
B2DLC(6)
B2EIDL(6)
B2EIDH(6)
B2SIDL(6)
B2SIDH(6)
B2CON(6)
B1D7(6)
B1D6(6)
B1D5(6)
B1D4(6)
B1D3(6)
B1D2(6)
B1D1(6)
B1D0(6)
B1DLC(6)
B1EIDL(6)
B1EIDH(6)
B1SIDL(6)
B1SIDH(6)
B1CON(6)
B0D7(6)
B0D6(6)
B0D5(6)
B0D4(6)
B0D3(6)
B0D2(6)
B0D1(6)
B0D0(6)
B0DLC(6)
Legend: u= unchanged, x= unknown, -= unimplemented bit, read as ‘0’, q= value depends on condition.
Shaded cells indicate conditions do not apply for the designated device.
Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).
2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt
vector (0008h or 0018h).
3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are
updated with the current value of the PC. The STKPTR is modified to point to the next location in the
hardware stack.
4: See Table 4-3 for Reset value for specific condition.
5: Bits 6 and 7 of PORTA, LATA and TRISA are enabled depending on the oscillator mode selected. When
not enabled as PORTA pins, they are disabled and read ‘0’.
6: This register reads all ‘0’s until the ECAN™ technology is set up in Mode 1 or Mode 2.
DS39761B-page 58
Preliminary
© 2007 Microchip Technology Inc.
PIC18F2682/2685/4682/4685
TABLE 4-4:
Register
INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)
MCLR Resets,
WDT Reset,
Power-on Reset,
Brown-out Reset
Wake-up via WDT
or Interrupt
Applicable Devices
RESETInstruction,
Stack Resets
B0EIDL(6)
B0EIDH(6)
B0SIDL(6)
B0SIDH(6)
B0CON(6)
TXBIE(6)
2682 2685 4682 4685
2682 2685 4682 4685
2682 2685 4682 4685
2682 2685 4682 4685
2682 2685 4682 4685
2682 2685 4682 4685
2682 2685 4682 4685
2682 2685 4682 4685
2682 2685 4682 4685
2682 2685 4682 4685
2682 2685 4682 4685
2682 2685 4682 4685
2682 2685 4682 4685
2682 2685 4682 4685
2682 2685 4682 4685
xxxx xxxx
xxxx xxxx
xxxx x-xx
xxxx xxxx
0000 0000
---0 00--
0000 0000
0000 00--
0000 0000
0000 0000
0000 0101
0101 0000
---0 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0001 0001
0001 0001
0000 0000
xxxx xxxx
xxxx xxxx
xxx- x-xx
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxx- x-xx
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu u-uu
uuuu uuuu
0000 0000
---u uu--
0000 0000
0000 00--
0000 0000
0000 0000
0000 0101
0101 0000
---0 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0001 0001
0001 0001
0000 0000
uuuu uuuu
uuuu uuuu
uuu- u-uu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuu- u-uu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu u-uu
uuuu uuuu
uuuu uuuu
---u uu--
uuuu uuuu
uuuu uu--
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
---u uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuu- u-uu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuu- u-uu
uuuu uuuu
BIE0(6)
BSEL0(6)
MSEL3(6)
MSEL2(6)
MSEL1(6)
MSEL0(6)
SDFLC(6)
RXFCON1(6)
RXFCON0(6)
RXFBCON7(6) 2682 2685 4682 4685
RXFBCON6(6) 2682 2685 4682 4685
RXFBCON5(6) 2682 2685 4682 4685
RXFBCON4(6) 2682 2685 4682 4685
RXFBCON3(6) 2682 2685 4682 4685
RXFBCON2(6) 2682 2685 4682 4685
RXFBCON1(6) 2682 2685 4682 4685
RXFBCON0(6) 2682 2685 4682 4685
RXF15EIDL(6) 2682 2685 4682 4685
RXF15EIDH(6) 2682 2685 4682 4685
RXF15SIDL(6) 2682 2685 4682 4685
RXF15SIDH(6) 2682 2685 4682 4685
RXF14EIDL(6) 2682 2685 4682 4685
RXF14EIDH(6) 2682 2685 4682 4685
RXF14SIDL(6) 2682 2685 4682 4685
RXF14SIDH(6) 2682 2685 4682 4685
Legend: u= unchanged, x= unknown, -= unimplemented bit, read as ‘0’, q= value depends on condition.
Shaded cells indicate conditions do not apply for the designated device.
Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).
2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt
vector (0008h or 0018h).
3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are
updated with the current value of the PC. The STKPTR is modified to point to the next location in the
hardware stack.
4: See Table 4-3 for Reset value for specific condition.
5: Bits 6 and 7 of PORTA, LATA and TRISA are enabled depending on the oscillator mode selected. When
not enabled as PORTA pins, they are disabled and read ‘0’.
6: This register reads all ‘0’s until the ECAN™ technology is set up in Mode 1 or Mode 2.
© 2007 Microchip Technology Inc.
Preliminary
DS39761B-page 59
PIC18F2682/2685/4682/4685
TABLE 4-4:
INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)
MCLR Resets,
Power-on Reset,
Brown-out Reset
WDT Reset,
RESETInstruction,
Stack Resets
Wake-up via WDT
or Interrupt
Register
Applicable Devices
RXF13EIDL(6) 2682 2685 4682 4685
RXF13EIDH(6) 2682 2685 4682 4685
RXF13SIDL(6) 2682 2685 4682 4685
RXF13SIDH(6) 2682 2685 4682 4685
RXF12EIDL(6) 2682 2685 4682 4685
RXF12EIDH(6) 2682 2685 4682 4685
RXF12SIDL(6) 2682 2685 4682 4685
RXF12SIDH(6) 2682 2685 4682 4685
RXF11EIDL(6) 2682 2685 4682 4685
RXF11EIDH(6) 2682 2685 4682 4685
RXF11SIDL(6) 2682 2685 4682 4685
RXF11SIDH(6) 2682 2685 4682 4685
RXF10EIDL(6) 2682 2685 4682 4685
RXF10EIDH(6) 2682 2685 4682 4685
RXF10SIDL(6) 2682 2685 4682 4685
RXF10SIDH(6) 2682 2685 4682 4685
xxxx xxxx
xxxx xxxx
xxx- x-xx
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxx- x-xx
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxx- x-xx
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxx- x-xx
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxx- x-xx
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxx- x-xx
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxx- x-xx
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxx- x-xx
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuu- u-uu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuu- u-uu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuu- u-uu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuu- u-uu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuu- u-uu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuu- u-uu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuu- u-uu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuu- u-uu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuu- u-uu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuu- u-uu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuu- u-uu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuu- u-uu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuu- u-uu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuu- u-uu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuu- u-uu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuu- u-uu
uuuu uuuu
RXF9EIDL(6)
RXF9EIDH(6) 2682 2685 4682 4685
RXF9SIDL(6)
2682 2685 4682 4685
RXF9SIDH(6) 2682 2685 4682 4685
RXF8EIDL(6)
2682 2685 4682 4685
RXF8EIDH(6) 2682 2685 4682 4685
RXF8SIDL(6)
2682 2685 4682 4685
RXF8SIDH(6) 2682 2685 4682 4685
RXF7EIDL(6)
2682 2685 4682 4685
RXF7EIDH(6) 2682 2685 4682 4685
RXF7SIDL(6)
2682 2685 4682 4685
RXF7SIDH(6) 2682 2685 4682 4685
RXF6EIDL(6)
2682 2685 4682 4685
RXF6EIDH(6) 2682 2685 4682 4685
RXF6SIDL(6)
2682 2685 4682 4685
RXF6SIDH(6) 2682 2685 4682 4685
2682 2685 4682 4685
Legend: u= unchanged, x= unknown, -= unimplemented bit, read as ‘0’, q= value depends on condition.
Shaded cells indicate conditions do not apply for the designated device.
Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).
2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt
vector (0008h or 0018h).
3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are
updated with the current value of the PC. The STKPTR is modified to point to the next location in the
hardware stack.
4: See Table 4-3 for Reset value for specific condition.
5: Bits 6 and 7 of PORTA, LATA and TRISA are enabled depending on the oscillator mode selected. When
not enabled as PORTA pins, they are disabled and read ‘0’.
6: This register reads all ‘0’s until the ECAN™ technology is set up in Mode 1 or Mode 2.
DS39761B-page 60
Preliminary
© 2007 Microchip Technology Inc.
PIC18F2682/2685/4682/4685
5.1
Program Memory Organization
5.0
MEMORY ORGANIZATION
PIC18 microcontrollers implement a 21-bit program
counter, which is capable of addressing a 2-Mbyte
program memory space. Accessing a location between
the upper boundary of the physically implemented
memory and the 2-Mbyte address will return all ‘0’s (a
NOPinstruction).
There are three types of memory in PIC18 Enhanced
microcontroller devices:
• Program Memory
• Data RAM
• Data EEPROM
As Harvard architecture devices, the data and program
memories use separate busses; this allows for
concurrent access of the two memory spaces. The data
EEPROM, for practical purposes, can be regarded as
a peripheral device, since it is addressed and accessed
through a set of control registers.
The PIC18F2682 and PIC18F4682 each have 80 Kbytes
of Flash memory and can store up to 40,960 single-word
instructions. The PIC18F2685 and PIC18F4685 each
have 96 Kbytes of Flash memory and can store up to
49,152 single-word instructions.
PIC18 devices have two interrupt vectors. The Reset
vector address is at 0000h and the interrupt vector
addresses are at 0008h and 0018h.
Additional detailed information on the operation of the
Flash program memory is provided in Section 6.0
“Flash Program Memory”. Data EEPROM is
discussed separately in Section 7.0 “Data EEPROM
Memory”.
The program memory maps for PIC18F2682/4682 and
PIC18F2685/4685 devices are shown in Figure 5-1.
FIGURE 5-1:
PROGRAM MEMORY MAP AND STACK FOR PIC18F2682/2685/4682/4685 DEVICES
PIC18F2682/4682
PIC18F2685/4685
PC<20:0>
PC<20:0>
21
CALL,RCALL,RETURN
RETFIE,RETLW
21
CALL,RCALL,RETURN
RETFIE,RETLW
Stack Level 1
Stack Level 1
•
•
•
•
•
•
Stack Level 31
Reset Vector
Stack Level 31
Reset Vector
0000h
0000h
High Priority Interrupt Vector
High Priority Interrupt Vector 0008h
00008h
0018h
Low Priority Interrupt Vector 0018h
Low Priority Interrupt Vector
On-Chip
Program Memory
On-Chip
Program Memory
13FFFh
14000h
17FFFh
18000h
Read ‘0’
Read ‘0’
1FFFFFh
200000h
1FFFFFh
200000h
© 2007 Microchip Technology Inc.
Preliminary
DS39761B-page 61
PIC18F2682/2685/4682/4685
The stack operates as a 31-word by 21-bit RAM and a
5-bit Stack Pointer, STKPTR. The stack space is not
part of either program or data space. The Stack Pointer
is readable and writable and the address on the top of
the stack is readable and writable through the Top-of-
Stack Special Function Registers. Data can also be
pushed to, or popped from the stack, using these
registers.
5.1.1
PROGRAM COUNTER
The Program Counter (PC) specifies the address of the
instruction to fetch for execution. The PC is 21 bits wide
and is contained in three separate 8-bit registers. The
low byte, known as the PCL register, is both readable
and writable. The high byte, or PCH register, contains
the PC<15:8> bits; it is not directly readable or writable.
Updates to the PCH register are performed through the
PCLATH register. The upper byte is called PCU. This
register contains the PC<20:16> bits; it is also not
directly readable or writable. Updates to the PCU
register are performed through the PCLATU register.
A CALLtype instruction causes a push onto the stack.
The Stack Pointer is first incremented and the location
pointed to by the Stack Pointer is written with the
contents of the PC (already pointing to the instruction
following the CALL). A RETURNtype instruction causes
a pop from the stack. The contents of the location
pointed to by the STKPTR are transferred to the PC
and then the Stack Pointer is decremented.
The contents of PCLATH and PCLATU are transferred
to the program counter by any operation that writes to
the PCL. Similarly, the upper two bytes of the program
counter are transferred to PCLATH and PCLATU by an
operation that reads PCL. This is useful for computed
offsets to the PC (see Section 5.1.4.1 “Computed
GOTO”).
The Stack Pointer is initialized to ‘00000’ after all
Resets. There is no RAM associated with the location
corresponding to a Stack Pointer value of ‘00000’; this
is only a Reset value. Status bits indicate if the stack is
full, has overflowed or has underflowed.
The PC addresses bytes in the program memory. To
prevent the PC from becoming misaligned with word
instructions, the Least Significant bit of PCL is fixed to
a value of ‘0’. The PC increments by 2 to address
sequential instructions in the program memory.
5.1.2.1
Top-of-Stack Access
Only the top of the return address stack (TOS) is
readable and writable. A set of three registers,
TOSU:TOSH:TOSL, holds the contents of the stack
location pointed to by the STKPTR register (Figure 5-2).
This allows users to implement a software stack if
necessary. After a CALL, RCALL or interrupt, the
software can read the pushed value by reading the
TOSU:TOSH:TOSL registers. These values can be
placed on a user defined software stack. At return time,
the software can return these values to
TOSU:TOSH:TOSL and do a return.
The CALL, RCALL and GOTO program branch
instructions write to the program counter directly. For
these instructions, the contents of PCLATH and
PCLATU are not transferred to the program counter.
5.1.2
RETURN ADDRESS STACK
The return address stack allows any combination of up
to 31 program calls and interrupts to occur. The PC is
pushed onto the stack when a CALL, or RCALLinstruc-
tion is executed, or an interrupt is Acknowledged. The
PC value is pulled off the stack on a RETURN, RETLW
or a RETFIEinstruction. PCLATU and PCLATH are not
affected by any of the RETURNor CALLinstructions.
The user must disable the global interrupt enable bits
while accessing the stack to prevent inadvertent stack
corruption.
FIGURE 5-2:
RETURN ADDRESS STACK AND ASSOCIATED REGISTERS
Return Address Stack <20:0>
11111
11110
11101
Top-of-Stack Registers
Stack Pointer
STKPTR<4:0>
TOSU
00h
TOSH
1Ah
TOSL
34h
00010
00011
00010
00001
00000
001A34h
000D58h
Top-of-Stack
DS39761B-page 62
Preliminary
© 2007 Microchip Technology Inc.
PIC18F2682/2685/4682/4685
When the stack has been popped enough times to
unload the stack, the next pop returns a value of zero
to the PC and sets the STKUNF bit, while the Stack
Pointer remains at zero. The STKUNF bit will remain
set until cleared by software or until a POR occurs.
5.1.2.2
Return Stack Pointer (STKPTR)
The STKPTR register (Register 5-1) contains the Stack
Pointer value, the STKFUL (Stack Full) status bit and
the STKUNF (Stack Underflow) status bit. The value of
the Stack Pointer can be 0 through 31. The Stack
Pointer increments before values are pushed onto the
stack and decrements after values are popped off the
stack. On Reset, the Stack Pointer value will be zero.
The user may read and write the Stack Pointer value.
This feature can be used by a Real-Time Operating
System (RTOS) for return stack maintenance.
Note:
Returning a value of zero to the PC on an
underflow has the effect of vectoring the
program to the Reset vector, where the
stack conditions can be verified and
appropriate actions can be taken. This is
not the same as a Reset, as the contents
of the SFRs are not affected.
After the PC is pushed onto the stack 31 times (without
popping any values off the stack), the STKFUL bit is
set. The STKFUL bit is cleared by software or by a
POR.
5.1.2.3
PUSHand POPInstructions
Since the Top-of-Stack is readable and writable, the
ability to push values onto the stack and pull values off
the stack without disturbing normal program execution
is a desirable feature. The PIC18 instruction set
includes two instructions, PUSH and POP, that permit
the TOS to be manipulated under software control.
TOSU, TOSH and TOSL can be modified to place data
or a return address on the stack.
The action that takes place when the stack becomes
full depends on the state of the STVREN (Stack
Overflow Reset Enable) Configuration bit. (Refer to
Section 24.1 “Configuration Bits” for a description of
the device Configuration bits.) If STVREN is set
(default), the 31st push will push the (PC + 2) value
onto the stack, set the STKFUL bit and reset the
device. The STKFUL bit will remain set and the Stack
Pointer will be set to zero.
The PUSHinstruction places the current PC value onto
the stack. This increments the Stack Pointer and loads
the current PC value onto the stack.
If STVREN is cleared, the STKFUL bit will be set on the
31st push and the Stack Pointer will increment to 31.
Any additional pushes will not overwrite the 31st push
and STKPTR will remain at 31.
The POP instruction discards the current TOS by
decrementing the Stack Pointer. The previous value
pushed onto the stack then becomes the TOS value.
REGISTER 5-1:
STKPTR: STACK POINTER REGISTER
R/C-0
STKFUL(1)
bit 7
R/C-0
STKUNF(1)
U-0
—
R/W-0
SP4
R/W-0
SP3
R/W-0
SP2
R/W-0
SP1
R/W-0
SP0
bit 0
Legend:
C = Clearable bit
W = Writable bit
‘1’ = Bit is set
R = Readable bit
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
-n = Value at POR
bit 7
bit 6
STKFUL: Stack Full Flag bit(1)
1= Stack became full or overflowed
0= Stack has not become full or overflowed
STKUNF: Stack Underflow Flag bit(1)
1= Stack underflow occurred
0= Stack underflow did not occur
bit 5
Unimplemented: Read as ‘0’
bit 4-0
SP4:SP0: Stack Pointer Location bits
Note 1: Bit 7 and bit 6 are cleared by user software or by a POR.
© 2007 Microchip Technology Inc.
Preliminary
DS39761B-page 63
PIC18F2682/2685/4682/4685
5.1.2.4
Stack Full and Underflow Resets
5.1.4
LOOK-UP TABLES IN PROGRAM
MEMORY
Device Resets on stack overflow and stack underflow
conditions are enabled by setting the STVREN bit in
Configuration Register 4L. When STVREN is set, a full
or underflow condition will set the appropriate STKFUL
or STKUNF bit and then cause a device Reset. When
STVREN is cleared, a full or underflow condition will set
the appropriate STKFUL or STKUNF bit, but not cause
a device Reset. The STKFUL or STKUNF bit is cleared
by user software or a Power-on Reset.
There may be programming situations that require the
creation of data structures, or look-up tables, in
program memory. For PIC18 devices, look-up tables
can be implemented in two ways:
• Computed GOTO
• Table Reads
5.1.4.1
Computed GOTO
5.1.3
FAST REGISTER STACK
A computed GOTOis accomplished by adding an offset
to the program counter. An example is shown in
Example 5-2.
A Fast Register Stack is provided for the STATUS,
WREG and BSR registers to provide a “fast return”
option for interrupts. Each stack is only one level deep
and is neither readable nor writable. It is loaded with the
current value of the corresponding register when the
processor vectors for an interrupt. All interrupt sources
will push values into the stack registers. The values in
the registers are then loaded back into their associated
registers, if the RETFIE, FAST instruction is used to
return from the interrupt.
A look-up table can be formed with an ADDWF PCL
instruction and a group of RETLW nninstructions. The
W register is loaded with an offset into the table before
executing a CALLto that table. The first instruction of the
called routine is the ADDWF PCL instruction. The next
instruction executed will be one of the RETLW nn
instructions, that returns the value ‘nn’ to the calling
function.
If both low and high priority interrupts are enabled, the
stack registers cannot be used reliably to return from
low priority interrupts. If a high priority interrupt occurs
while servicing a low priority interrupt, the stack register
values stored by the low priority interrupt will be
overwritten. In these cases, users must save the key
registers in software during a low priority interrupt.
The offset value (in WREG) specifies the number of
bytes that the program counter should advance and
should be multiples of 2 (LSb = 0).
In this method, only one data byte may be stored in
each instruction location and room on the return
address stack is required.
If interrupt priority is not used, all interrupts may use the
Fast Register Stack for returns from interrupt. If no
interrupts are used, the Fast Register Stack can be
used to restore the STATUS, WREG and BSR registers
at the end of a subroutine call. To use the Fast Register
Stack for a subroutine call, a CALL label, FAST
instruction must be executed to save the STATUS,
WREG and BSR registers to the Fast Register Stack. A
RETURN, FASTinstruction is then executed to restore
these registers from the Fast Register Stack.
EXAMPLE 5-2:
COMPUTED GOTOUSING
AN OFFSET VALUE
OFFSET, W
TABLE
MOVF
CALL
ORG
TABLE
nn00h
ADDWF
RETLW
RETLW
RETLW
.
PCL
nnh
nnh
nnh
.
Example 5-1 shows a source code example that uses
the Fast Register Stack during a subroutine call and
return.
.
5.1.4.2
Table Reads and Table Writes
A better method of storing data in program memory
allows two bytes of data to be stored in each instruction
location.
EXAMPLE 5-1:
FAST REGISTER STACK
CODE EXAMPLE
;STATUS, WREG, BSR
;SAVED IN FAST REGISTER
;STACK
CALL SUB1, FAST
Look-up table data may be stored two bytes per
program word by using table reads and writes. The
Table Pointer (TBLPTR) register specifies the byte
address and the Table Latch (TABLAT) register
contains the data that is read from or written to program
memory. Data is transferred to or from program
memory one byte at a time.
•
•
SUB1
•
•
RETURN, FAST ;RESTORE VALUES SAVED
Table read and table write operations are discussed
;IN FAST REGISTER STACK
further in Section 6.1 “Table Reads and Table Writes”.
DS39761B-page 64
Preliminary
© 2007 Microchip Technology Inc.
PIC18F2682/2685/4682/4685
5.2.2
INSTRUCTION FLOW/PIPELINING
5.2
PIC18 Instruction Cycle
An “Instruction Cycle” consists of four Q cycles: Q1
through Q4. The instruction fetch and execute are pipe-
lined in such a manner that a fetch takes one instruction
cycle, while the decode and execute take another
instruction cycle. However, due to the pipelining, each
instruction effectively executes in one cycle. If an
instruction causes the program counter to change (e.g.,
GOTO), then two cycles are required to complete the
instruction (Example 5-3).
5.2.1
CLOCKING SCHEME
The microcontroller clock input, whether from an
internal or external source, is internally divided by four
to generate four non-overlapping quadrature clocks
(Q1, Q2, Q3 and Q4). Internally, the Program Counter
(PC) is incremented on every Q1; the instruction is
fetched from the program memory and latched into the
Instruction Register (IR) during Q4. The instruction is
decoded and executed during the following Q1 through
Q4. The clocks and instruction execution flow are
shown in Figure 5-3.
A fetch cycle begins with the program counter
incrementing in Q1.
In the execution cycle, the fetched instruction is latched
into the Instruction Register (IR) in cycle Q1. This
instruction is then decoded and executed during the
Q2, Q3 and Q4 cycles. Data memory is read during Q2
(operand read) and written during Q4 (destination
write).
FIGURE 5-3:
CLOCK/INSTRUCTION CYCLE
Q2
Q3
Q4
Q2
Q3
Q4
Q2
Q3
Q4
Q1
Q1
Q1
OSC1
Q1
Q2
Q3
Q4
Internal
Phase
Clock
PC
PC + 2
PC + 4
PC
OSC2/CLKO
(RC mode)
Execute INST (PC – 2)
Fetch INST (PC)
Execute INST (PC)
Fetch INST (PC + 2)
Execute INST (PC + 2)
Fetch INST (PC + 4)
EXAMPLE 5-3:
INSTRUCTION PIPELINE FLOW
TCY0
TCY1
TCY2
TCY3
TCY4
TCY5
1. MOVLW 55h
Fetch 1
Execute 1
Fetch 2
2. MOVWF PORTB
Execute 2
Fetch 3
3. BRA
4. BSF
SUB_1
PORTA, BIT3 (Forced NOP)
Execute 3
Fetch 4
Flush (NOP)
Fetch SUB_1 Execute SUB_1
5. Instruction @ address SUB_1
Note:
All instructions are single cycle, except for any program branches. These take two cycles since the
fetch instruction is “flushed” from the pipeline while the new instruction is being fetched and then
executed.
© 2007 Microchip Technology Inc.
Preliminary
DS39761B-page 65
PIC18F2682/2685/4682/4685
The CALL and GOTO instructions have the absolute
program memory address embedded into the instruc-
tion. Since instructions are always stored on word
boundaries, the data contained in the instruction is a
word address. The word address is written to PC<20:1>,
which accesses the desired byte address in program
memory. Instruction #2 in Figure 5-4 shows how the
instruction GOTO 0006h is encoded in the program
memory. Program branch instructions, which encode a
relative address offset, operate in the same manner. The
offset value stored in a branch instruction represents the
number of single-word instructions that the PC will be
offset by. Section 25.0 “Instruction Set Summary”
provides further details of the instruction set.
5.2.3
INSTRUCTIONS IN PROGRAM
MEMORY
The program memory is addressed in bytes. Instruc-
tions are stored as two bytes or four bytes in program
memory. The Least Significant Byte of an instruction
word is always stored in a program memory location
with an even address (LSB = 0). To maintain alignment
with instruction boundaries, the PC increments in steps
of 2 and the LSB will always read ‘0’ (see Section 5.1.1
“Program Counter”).
Figure 5-4 shows an example of how instruction words
are stored in the program memory.
FIGURE 5-4:
INSTRUCTIONS IN PROGRAM MEMORY
Word Address
LSB = 1
LSB = 0
↓
Program Memory
000000h
000002h
000004h
000006h
000008h
00000Ah
00000Ch
00000Eh
000010h
000012h
000014h
Byte Locations →
Instruction 1:
Instruction 2:
MOVLW
GOTO
055h
0006h
0Fh
EFh
F0h
C1h
F4h
55h
03h
00h
23h
56h
Instruction 3:
MOVFF
123h, 456h
and used by the instruction sequence. If the first word
is skipped for some reason and the second word is
executed by itself, a NOP is executed instead. This is
necessary for cases when the two-word instruction is
preceded by a conditional instruction that changes the
PC. Example 5-4 shows how this works.
5.2.4
TWO-WORD INSTRUCTIONS
The standard PIC18 instruction set has four two-word
instructions: CALL, MOVFF, GOTO and LSFR. In all
cases, the second word of the instructions always has
‘1111’ as its four Most Significant bits; the other 12 bits
are literal data, usually a data memory address.
Note:
See Section 5.5 “Program Memory and
the Extended Instruction Set” for
information on two-word instructions in the
extended instruction set.
The use of ‘1111’ in the 4 MSbs of an instruction
specifies a special form of NOP. If the instruction is
executed in proper sequence – immediately after the
first word – the data in the second word is accessed
EXAMPLE 5-4:
CASE 1:
TWO-WORD INSTRUCTIONS
Source Code
Object Code
0110 0110 0000 0000 TSTFSZ
REG1
REG1, REG2 ; No, skip this word
; Execute this word as a NOP
; continue code
; is RAM location 0?
1100 0001 0010 0011
1111 0100 0101 0110
0010 0100 0000 0000
CASE 2:
MOVFF
ADDWF
REG3
Object Code
Source Code
0110 0110 0000 0000
1100 0001 0010 0011
1111 0100 0101 0110
0010 0100 0000 0000
TSTFSZ
MOVFF
REG1
; is RAM location 0?
REG1, REG2 ; Yes, execute this word
; 2nd word of instruction
ADDWF
REG3
; continue code
DS39761B-page 66
Preliminary
© 2007 Microchip Technology Inc.
PIC18F2682/2685/4682/4685
5.3.1
BANK SELECT REGISTER (BSR)
5.3
Data Memory Organization
Large areas of data memory require an efficient
addressing scheme to make rapid access to any
address possible. Ideally, this means that an entire
address does not need to be provided for each read or
write operation. For PIC18 devices, this is accom-
plished with a RAM banking scheme. This divides the
memory space into 16 contiguous banks of 256 bytes.
Depending on the instruction, each location can be
addressed directly by its full 12-bit address, or an 8-bit
low-order address and a 4-bit Bank Pointer.
Note:
The operation of some aspects of data
memory are changed when the PIC18
extended instruction set is enabled. See
Section 5.6 “Data Memory and the
Extended Instruction Set” for more
information.
The data memory in PIC18 devices is implemented as
static RAM. Each register in the data memory has a
12-bit address, allowing up to 4096 bytes of data
memory. The memory space is divided into as many as
16 banks that contain 256 bytes each; PIC18F2682/
2685/4682/4685 devices implement all 16 banks.
Figure 5-5 shows the data memory organization for the
PIC18F2682/2685/4682/4685 devices.
Most instructions in the PIC18 instruction set make use
of the Bank Pointer, known as the Bank Select Register
(BSR). This SFR holds the 4 Most Significant bits of a
location’s address; the instruction itself includes the
8 Least Significant bits. Only the four lower bits of the
BSR are implemented (BSR3:BSR0). The upper four
bits are unused; they will always read ‘0’ and cannot be
written to. The BSR can be loaded directly by using the
MOVLBinstruction.
The data memory contains Special Function Registers
(SFRs) and General Purpose Registers (GPRs). The
SFRs are used for control and status of the controller
and peripheral functions, while GPRs are used for data
storage and scratchpad operations in the user’s
application. Any read of an unimplemented location will
read as ‘0’s.
The value of the BSR indicates the bank in data
memory. The 8 bits in the instruction show the location
in the bank and can be thought of as an offset from the
bank’s lower boundary. The relationship between the
BSR’s value and the bank division in data memory is
shown in Figure 5-6.
The instruction set and architecture allow operations
across all banks. The entire data memory may be
accessed by Direct, Indirect or Indexed Addressing
modes. Addressing modes are discussed later in this
subsection.
Since up to 16 registers may share the same low-order
address, the user must always be careful to ensure that
the proper bank is selected before performing a data
read or write. For example, writing what should be
program data to an 8-bit address of F9h while the BSR
is 0Fh, will end up resetting the program counter.
To ensure that commonly used registers (SFRs and
select GPRs) can be accessed in a single cycle, PIC18
devices implement an Access Bank. This is a 256-byte
memory space that provides fast access to SFRs and
the lower portion of GPR Bank 0 without using the
BSR. Section 5.3.2 “Access Bank” provides a
detailed description of the Access RAM.
While any bank can be selected, only those banks that
are actually implemented can be read or written to.
Writes to unimplemented banks are ignored, while
reads from unimplemented banks will return ‘0’s. Even
so, the STATUS register will still be affected as if the
operation was successful. The data memory map in
Figure 5-5 indicates which banks are implemented.
In the core PIC18 instruction set, only the MOVFF
instruction fully specifies the 12-bit address of the
source and target registers. This instruction ignores the
BSR completely when it executes. All other instructions
include only the low-order address as an operand and
must use either the BSR or the Access Bank to locate
their target registers.
© 2007 Microchip Technology Inc.
Preliminary
DS39761B-page 67
PIC18F2682/2685/4682/4685
FIGURE 5-5:
BSR<3:0>
= 0000
DATA MEMORY MAP FOR PIC18F2682/2685/4682/4685 DEVICES
When a = 0:
The BSR is ignored and the
Data Memory Map
Access Bank is used.
000h
05Fh
060h
0FFh
100h
00h
Access RAM
GPR
The first 128 bytes are
general purpose RAM
(from Bank 0).
Bank 0
FFh
00h
= 0001
= 0010
GPR
GPR
The second 128 bytes are
Special Function Registers
(from Bank 15).
Bank 1
Bank 2
1FFh
200h
FFh
00h
When a = 1:
FFh
00h
2FFh
300h
The BSR specifies the Bank
used by the instruction.
= 0011
Bank 3
Bank 4
Bank 5
Bank 6
Bank 7
Bank 8
Bank 9
Bank 10
Bank 11
Bank 12
Bank 13
GPR
3FFh
400h
FFh
00h
= 0100
= 0101
GPR
4FFh
500h
FFh
00h
GPR
5FFh
600h
FFh
00h
= 0110
= 0111
GPR
Access Bank
FFh
00h
6FFh
700h
00h
Access RAM Low
5Fh
Access RAM High
GPR
60h
FFh
00h
7FFh
800h
(SFRs)
FFh
= 1000
= 1001
GPR
8FFh
900h
FFh
00h
GPR
9FFh
A00h
FFh
00h
= 1010
= 1011
= 1100
= 1101
GPR
AFFh
B00h
FFh
00h
GPR
BFFh
C00h
FFh
00h
GPR
CFFh
D00h
FFh
00h
CAN SFRs
CAN SFRs
DFFh
E00h
FFh
00h
= 1110
= 1111
Bank 14
Bank 15
EFFh
F00h
F5Fh
F60h
FFFh
FFh
00h
CAN SFRs
SFR
FFh
DS39761B-page 68
Preliminary
© 2007 Microchip Technology Inc.
PIC18F2682/2685/4682/4685
FIGURE 5-6:
USE OF THE BANK SELECT REGISTER (DIRECT ADDRESSING)
Data Memory
(2)
(1)
From Opcode
BSR
000h
100h
7
0
7
0
00h
Bank 0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
FFh
00h
Bank 1
Bank 2
(2)
Bank Select
FFh
00h
200h
300h
FFh
00h
Bank 3
through
Bank 13
FFh
00h
E00h
Bank 14
Bank 15
FFh
00h
F00h
FFFh
FFh
Note 1: The Access RAM bit of the instruction can be used to force an override of the selected bank (BSR<3:0>) to
the registers of the Access Bank.
2: The MOVFF instruction embeds the entire 12-bit address in the instruction.
however, the instruction is forced to use the Access
Bank address map; the current value of the BSR is
ignored entirely.
5.3.2
ACCESS BANK
While the use of the BSR with an embedded 8-bit
address allows users to address the entire range of
data memory, it also means that the user must always
ensure that the correct bank is selected. Otherwise,
data may be read from or written to the wrong location.
This can be disastrous if a GPR is the intended target
of an operation, but an SFR is written to instead.
Verifying and/or changing the BSR for each read or
write to data memory can become very inefficient.
Using this “forced” addressing allows the instruction to
operate on a data address in a single cycle, without
updating the BSR first. For 8-bit addresses of 80h and
above, this means that users can evaluate and operate
on SFRs more efficiently. The Access RAM below 80h
is a good place for data values that the user might need
to access rapidly, such as immediate computational
results or common program variables. Access RAM
also allows for faster and more code efficient context
saving and switching of variables.
To streamline access for the most commonly used data
memory locations, the data memory is configured with
an Access Bank, which allows users to access a
mapped block of memory without specifying a BSR.
The Access Bank consists of the first 128 bytes of
memory (00h-7Fh) in Bank 0 and the last 128 bytes of
memory (80h-FFh) in Block 15. The lower half is known
as the “Access RAM” and is composed of GPRs. The
upper half is where the device’s SFRs are mapped.
These two areas are mapped contiguously in the
Access Bank and can be addressed in a linear fashion
by an 8-bit address (Figure 5-5).
The mapping of the Access Bank is slightly different
when the extended instruction set is enabled (XINST
Configuration bit = 1). This is discussed in more detail
in Section 5.6.3 “Mapping the Access Bank in
Indexed Literal Offset Mode”.
5.3.3
GENERAL PURPOSE
REGISTER FILE
PIC18 devices may have banked memory in the GPR
area. This is data RAM, which is available for use by all
instructions. GPRs start at the bottom of Bank 0
(address 000h) and grow upwards towards the bottom of
the SFR area. GPRs are not initialized by a Power-on
Reset and are unchanged on all other Resets.
The Access Bank is used by core PIC18 instructions
that include the Access RAM bit (the ‘a’ parameter in
the instruction). When ‘a’ is equal to ‘1’, the instruction
uses the BSR and the 8-bit address included in the
opcode for the data memory address. When ‘a’ is ‘0’
© 2007 Microchip Technology Inc.
Preliminary
DS39761B-page 69
PIC18F2682/2685/4682/4685
peripheral functions. The reset and interrupt registers
are described in their respective chapters, while the
ALU’s STATUS register is described later in this
section. Registers related to the operation of a
peripheral feature are described in the chapter for that
peripheral.
5.3.4
SPECIAL FUNCTION REGISTERS
The Special Function Registers (SFRs) are registers
used by the CPU and peripheral modules for controlling
the desired operation of the device. These registers are
implemented as static RAM. SFRs start at the top of
data memory (FFFh) and extend downward to occupy
the top half of Bank 15 (F80h to FFFh). A list of these
registers is given in Table 5-1 and Table 5-2.
The SFRs are typically distributed among the
peripherals whose functions they control. Unused SFR
locations are unimplemented and read as ‘0’s.
The SFRs can be classified into two sets: those
associated with the “core” device functionality (ALU,
Resets and interrupts) and those related to the
TABLE 5-1:
SPECIAL FUNCTION REGISTER MAP FOR
PIC18F2682/2685/4682/4685 DEVICES
Address
Name
Address
Name
Address
Name
Address
F9Fh
Name
(3)
FFFh
FFEh
FFDh
FFCh
FFBh
FFAh
FF9h
FF8h
FF7h
FF6h
FF5h
FF4h
FF3h
FF2h
FF1h
FF0h
FEFh
FEEh
FEDh
FECh
FEBh
FEAh
FE9h
FE8h
FE7h
FE6h
FE5h
FE4h
FE3h
FE2h
FE1h
FE0h
TOSU
TOSH
FDFh
FDEh
INDF2
FBFh
FBEh
FBDh
FBCh
FBBh
CCPR1H
CCPR1L
IPR1
(3)
(3)
POSTINC2
F9Eh
F9Dh
F9Ch
F9Bh
F9Ah
F99h
F98h
F97h
F96h
F95h
F94h
F93h
F92h
F91h
F90h
F8Fh
F8Eh
F8Dh
F8Ch
F8Bh
F8Ah
F89h
F88h
F87h
F86h
F85h
F84h
F83h
F82h
F81h
F80h
PIR1
TOSL
FDDh POSTDEC2
CCP1CON
PIE1
(3)
(1)
STKPTR
PCLATU
PCLATH
PCL
FDCh
FDBh
FDAh
FD9h
FD8h
FD7h
FD6h
FD5h
FD4h
FD3h
FD2h
FD1h
FD0h
FCFh
FCEh
FCDh
FCCh
FCBh
FCAh
FC9h
FC8h
FC7h
FC6h
FC5h
FC4h
FC3h
FC2h
FC1h
FC0h
PREINC2
ECCPR1H
—
(3)
(1)
PLUSW2
ECCPR1L
OSCTUNE
(1)
FSR2H
FSR2L
FBAh ECCP1CON
—
—
—
—
FB9h
FB8h
FB7h
FB6h
FB5h
FB4h
FB3h
FB2h
FB1h
FB0h
FAFh
FAEh
FADh
FACh
FABh
FAAh
FA9h
FA8h
FA7h
FA6h
FA5h
FA4h
FA3h
FA2h
FA1h
FA0h
—
TBLPTRU
TBLPTRH
TBLPTRL
TABLAT
PRODH
PRODL
INTCON
INTCON2
INTCON3
STATUS
TMR0H
TMR0L
BAUDCON
ECCP1DEL
(1)
(1)
ECCP1AS
TRISE
(1)
(1)
T0CON
—
CVRCON
TRISD
CMCON
TMR3H
TMR3L
TRISC
TRISB
TRISA
—
OSCCON
HLVDCON
WDTCON
RCON
T3CON
SPBRGH
SPBRG
RCREG
TXREG
TXSTA
—
(3)
INDF0
TMR1H
TMR1L
—
(3)
POSTINC0
—
(3)
(1)
POSTDEC0
T1CON
TMR2
LATE
(3)
(1)
PREINC0
LATD
(3)
PLUSW0
FSR0H
FSR0L
WREG
PR2
RCSTA
EEADRH
EEADR
EEDATA
LATC
LATB
LATA
—
T2CON
SSPBUF
SSPADD
SSPSTAT
SSPCON1
SSPCON2
ADRESH
ADRESL
ADCON0
ADCON1
ADCON2
(3)
(3)
INDF1
EECON2
—
(3)
(3)
POSTINC1
EECON1
IPR3
—
POSTDEC1
—
(3)
(1)
PREINC1
PIR3
PORTE
(3)
(1)
PLUSW1
FSR1H
FSR1L
BSR
PIE3
PORTD
IPR2
PORTC
PORTB
PORTA
PIR2
PIE2
Note 1: Registers available only on PIC18F4X8X devices; otherwise, the registers read as ‘0’.
2: When any TX_ENn bit in RX_TX_SELn is set, then the corresponding bit in this register has transmit properties.
3: This is not a physical register.
DS39761B-page 70
Preliminary
© 2007 Microchip Technology Inc.
PIC18F2682/2685/4682/4685
TABLE 5-1:
SPECIAL FUNCTION REGISTER MAP FOR
PIC18F2682/2685/4682/4685 DEVICES (CONTINUED)
Address
Name
Address
Name
Address
Name
Address
Name
F7Fh
F7Eh
F7Dh
F7Ch
F7Bh
F7Ah
F79h
F78h
F77h
F76h
F75h
F74h
F73h
F72h
F71h
F70h
F6Fh
F6Eh
F6Dh
F6Ch
F6Bh
F6Ah
F69h
F68h
F67h
F66h
F65h
F64h
F63h
F62h
F61h
F60h
—
F5Fh CANCON_RO0
F5Eh CANSTAT_RO0
F3Fh CANCON_RO2
F3Eh CANSTAT_RO2
F1Fh
F1Eh
F1Dh
F1Ch
F1Bh
F1Ah
F19h
F18h
F17h
F16h
F15h
F14h
F13h
F12h
F11h
F10h
F0Fh
F0Eh
F0Dh
F0Ch
F0Bh
F0Ah
F09h
F08h
F07h
F06h
F05h
F04h
F03h
F02h
F01h
F00h
RXM1EIDL
RXM1EIDH
RXM1SIDL
RXM1SIDH
RXM0EIDL
RXM0EIDH
RXM0SIDL
RXM0SIDH
RXF5EIDL
RXF5EIDH
RXF5SIDL
RXF5SIDH
RXF4EIDL
RXF4EIDH
RXF4SIDL
RXF4SIDH
RXF3EIDL
RXF3EIDH
RXF3SIDL
RXF3SIDH
RXF2EIDL
RXF2EIDH
RXF2SIDL
RXF2SIDH
RXF1EIDL
RXF1EIDH
RXF1SIDL
RXF1SIDH
RXF0EIDL
RXF0EIDH
RXF0SIDL
RXF0SIDH
—
—
F5Dh
F5Ch
F5Bh
F5Ah
F59h
F58h
F57h
F56h
F55h
F54h
F53h
F52h
F51h
F50h
RXB1D7
RXB1D6
F3Dh
F3Ch
F3Bh
F3Ah
F39h
F38h
F37h
F36h
F35h
F34h
F33h
F32h
F31h
F30h
TXB1D7
TXB1D6
—
—
RXB1D5
TXB1D5
—
RXB1D4
TXB1D4
—
RXB1D3
TXB1D3
—
RXB1D2
TXB1D2
ECANCON
TXERRCNT
RXERRCNT
COMSTAT
CIOCON
BRGCON3
BRGCON2
BRGCON1
CANCON
CANSTAT
RXB0D7
RXB0D6
RXB0D5
RXB0D4
RXB0D3
RXB0D2
RXB0D1
RXB0D0
RXB0DLC
RXB0EIDL
RXB0EIDH
RXB0SIDL
RXB0SIDH
RXB0CON
RXB1D1
TXB1D1
RXB1D0
TXB1D0
RXB1DLC
RXB1EIDL
RXB1EIDH
RXB1SIDL
RXB1SIDH
RXB1CON
TXB1DLC
TXB1EIDL
TXB1EIDH
TXB1SIDL
TXB1SIDH
TXB1CON
F4Fh CANCON_RO1
F4Eh CANSTAT_RO1
F2Fh CANCON_RO3
F2Eh CANSTAT_RO3
F4DH
F4Ch
F4Bh
F4Ah
F49h
F48h
F47h
F46h
F45h
F44h
F43h
F42h
F41h
F40h
TXB0D7
TXB0D6
F2Dh
F2Ch
F2Bh
F2Ah
F29h
F28h
F27h
F26h
F25h
F24h
F23h
F22h
F21h
F20h
TXB2D7
TXB2D6
TXB0D5
TXB2D5
TXB0D4
TXB2D4
TXB0D3
TXB2D3
TXB0D2
TXB2D2
TXB0D1
TXB2D1
TXB0D0
TXB2D0
TXB0DLC
TXB0EIDL
TXB0EIDH
TXB0SIDL
TXB0SIDH
TXB0CON
TXB2DLC
TXB2EIDL
TXB2EIDH
TXB2SIDL
TXB2SIDH
TXB2CON
Note 1: Registers available only on PIC18F4X8X devices; otherwise, the registers read as ‘0’.
2: When any TX_ENn bit in RX_TX_SELn is set, then the corresponding bit in this register has transmit properties.
3: This is not a physical register.
© 2007 Microchip Technology Inc.
Preliminary
DS39761B-page 71
PIC18F2682/2685/4682/4685
TABLE 5-1:
SPECIAL FUNCTION REGISTER MAP FOR
PIC18F2682/2685/4682/4685 DEVICES (CONTINUED)
Address
Name
Address
Name
Address
Name
Address
Name
EFFh
EFEh
EFDh
EFCh
EFBh
EFAh
EF9h
EF8h
EF7h
EF6h
EF5h
EF4h
EF3h
EF2h
EF1h
EF0h
EEFh
EEEh
EEDh
EECh
EEBh
EEAh
EE9h
EE8h
EE7h
EE6h
EE5h
EE4h
EE3h
EE2h
EE1h
EE0h
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
EDFh
EDEh
EDDh
EDCh
EDBh
EDAh
ED9h
ED8h
ED7h
ED6h
ED5h
ED4h
ED3h
ED2h
ED1h
ED0h
ECFh
ECEh
ECDh
ECCh
ECBh
ECAh
EC9h
EC8h
EC7h
EC6h
EC5h
EC4h
EC3h
EC2h
EC1h
EC0h
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
EBFh
EBEh
EBDh
EBCh
EBBh
EBAh
EB9h
EB8h
EB7h
EB6h
EB5h
EB4h
EB3h
EB2h
EB1h
EB0h
EAFh
EAEh
EADh
EACh
EABh
EAAh
EA9h
EA8h
EA7h
EA6h
EA5h
EA4h
EA3h
EA2h
EA1h
EA0h
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
E9Fh
E9Eh
E9Dh
E9Ch
E9Bh
E9Ah
E99h
E98h
E97h
E96h
E95h
E94h
E93h
E92h
E91h
E90h
E8Fh
E8Eh
E8Dh
E8Ch
E8Bh
E8Ah
E89h
E88h
E87h
E86h
E85h
E84h
E83h
E82h
E81h
E80h
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Note 1: Registers available only on PIC18F4X8X devices; otherwise, the registers read as ‘0’.
2: When any TX_ENn bit in RX_TX_SELn is set, then the corresponding bit in this register has transmit properties.
3: This is not a physical register.
DS39761B-page 72
Preliminary
© 2007 Microchip Technology Inc.
PIC18F2682/2685/4682/4685
TABLE 5-1:
SPECIAL FUNCTION REGISTER MAP FOR
PIC18F2682/2685/4682/4685 DEVICES (CONTINUED)
Address
Name
Address
Name
Address
Name
Address
Name
E7Fh
E7Eh
E7Dh
E7Ch
E7Bh
E7Ah
E79h
E78h
E77h
E76h
E75h
E74h
E73h
E72h
E71h
E70h
E3Fh
E3Eh
E3Dh
E3Ch
E3Bh
E3Ah
E39h
E38h
E37h
E36h
E35h
E34h
E33h
E32h
E31h
E30h
CANCON_RO4
CANSTAT_RO4
E6Fh CANCON_RO5
E5Fh CANCON_RO6
E4Fh CANCON_RO7
E6Eh CANSTAT_RO5
E5Eh CANSTAT_RO6
E4Eh CANSTAT_RO7
(2)
(2)
(2)
(2)
B5D7
E6Dh
E6Ch
E6Bh
E6Ah
E69h
E68h
E67h
E66h
E65h
E64h
E63h
E62h
E61h
E60h
B4D7
B4D6
B4D5
B4D4
B4D3
B4D2
B4D1
B4D0
E5Dh
E5Ch
E5Bh
E5Ah
E59h
E58h
E57h
E56h
E55h
E54h
E53h
E52h
E51h
E50h
E1Fh
E1Eh
E1Dh
E1Ch
E1Bh
E1Ah
E19h
E18h
E17h
E16h
E15h
E14h
E13h
E12h
E11h
E10h
B3D7
B3D6
B3D5
B3D4
B3D3
B3D2
B3D1
B3D0
E4Dh
E4Ch
E4Bh
E4Ah
E49h
E48h
E47h
E46h
E45h
E44h
E43h
E42h
E41h
E40h
E0Fh
E0Eh
E0Dh
E0Ch
E0Bh
E0Ah
E09h
E08h
E07h
E06h
E05h
E04h
E03h
E02h
E01h
E00h
B2D7
B2D6
B2D5
B2D4
B2D3
B2D2
B2D1
B2D0
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
B5D6
(2)
B5D5
(2)
B5D4
(2)
B5D3
(2)
B5D2
(2)
B5D1
(2)
B5D0
(2)
(2)
(2)
(2)
(2)
(2)
(2)
B5DLC
B4DLC
B3DLC
B2DLC
(2)
B5EIDL
B4EIDL
B4EIDH
B3EIDL
B3EIDH
B2EIDL
B2EIDH
(2)
(2)
(2)
(2)
B5EIDH
(2)
(2)
(2)
(2)
(2)
(2)
(2)
B5SIDL
B4SIDL
B3SIDL
B2SIDL
(2)
B5SIDH
B4SIDH
B3SIDH
B2SIDH
(2)
(2)
(2)
(2)
B5CON
B4CON
B3CON
—
B2CON
—
CANCON_RO8
E2Fh CANCON_RO9
CANSTAT_RO8
E2Eh CANSTAT_RO9
—
—
(2)
(2)
B1D7
E2Dh
E2Ch
E2Bh
E2Ah
E29h
E28h
E27h
E26h
E25h
E24h
E23h
E22h
E21h
E20h
B0D7
B0D6
B0D5
B0D4
B0D3
B0D2
B0D1
—
—
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2
B1D6
—
—
(2)
B1D5
—
—
(2)
B1D4
—
—
(2)
B1D3
—
—
(2)
B1D2
—
—
(2)
B1D1
—
—
(2)
B1D0
B0D0
—
—
(2)
(2)
(2)
B1DLC
B0DLC
—
—
(2)
B1EIDL
B0EIDL
B0EIDH
—
—
(2)
(2)
B1EIDH
—
—
(2)
(2)
B1SIDL
B0SIDL
—
—
(2)
(2)
B1SIDH
B0SIDH
—
—
(2)
(2)
B1CON
B0CON
—
—
Note 1: Registers available only on PIC18F4X8X devices; otherwise, the registers read as ‘0’.
2: When any TX_ENn bit in RX_TX_SELn is set, then the corresponding bit in this register has transmit properties.
3: This is not a physical register.
© 2007 Microchip Technology Inc.
Preliminary
DS39761B-page 73
PIC18F2682/2685/4682/4685
TABLE 5-1:
SPECIAL FUNCTION REGISTER MAP FOR
PIC18F2682/2685/4682/4685 DEVICES (CONTINUED)
Address
Name
Address
Name
Address
Name
Address
Name
DFFh
DFEh
DFDh
DFCh
DFBh
DFAh
DF9h
DF8h
DF7h
DF6h
DF5h
DF4h
DF3h
DF2h
DF1h
DF0h
DEFh
DEEh
DEDh
DECh
DEBh
DEAh
DE9h
DE8h
DE7h
DE6h
DE5h
DE4h
DE3h
DE2h
DE1h
DE0h
—
DDFh
DDEh
DDDh
DDCh
DDBh
DDAh
DD9h
DD8h
DD7h
DD6h
DD5h
DD4h
DD3h
DD2h
DD1h
DD0h
DCFh
DCEh
DCDh
DCCh
DCBh
DCAh
DC9h
DC8h
DC7h
DC6h
DC5h
DC4h
DC3h
DC2h
DC1h
DC0h
—
DBFh
DBEh
DBDh
DBCh
DBBh
DBAh
DB9h
DB8h
DB7h
DB6h
DB5h
DB4h
DB3h
DB2h
DB1h
DB0h
DAFh
DAEh
DADh
DACh
DABh
DAAh
DA9h
DA8h
DA7h
DA6h
DA5h
DA4h
DA3h
DA2h
DA1h
DA0h
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
D9Fh
D9Eh
D9Dh
D9Ch
D9Bh
D9Ah
D99h
D98h
D97h
D96h
D95h
D94h
D93h
D92h
D91h
D90h
D8Fh
D8Eh
D8Dh
D8Ch
D8Bh
D8Ah
D89h
D88h
D87h
D86h
D85h
D84h
D83h
D82h
D81h
D80h
—
—
—
—
—
—
—
TXBIE
—
—
—
—
—
BIE0
—
—
—
—
—
BSEL0
SDFLC
—
—
—
—
—
—
—
—
RXFCON1
—
—
RXFCON0
—
MSEL3
MSEL2
MSEL1
MSEL0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
RXF15EIDL
RXF15EIDH
RXF15SIDL
RXF15SIDH
—
—
—
—
—
—
—
—
RXF14EIDL
RXF14EIDH
RXF14SIDL
RXF14SIDH
RXF13EIDL
RXF13EIDH
RXF13SIDL
RXF13SIDH
RXF12EIDL
RXF12EIDH
RXF12SIDL
RXF12SIDH
—
—
—
RXFBCON7
RXFBCON6
RXFBCON5
RXFBCON4
RXFBCON3
RXFBCON2
RXFBCON1
RXFBCON0
Note 1: Registers available only on PIC18F4X8X devices; otherwise, the registers read as ‘0’.
2: When any TX_ENn bit in RX_TX_SELn is set, then the corresponding bit in this register has transmit properties.
3: This is not a physical register.
DS39761B-page 74
Preliminary
© 2007 Microchip Technology Inc.
PIC18F2682/2685/4682/4685
TABLE 5-1:
SPECIAL FUNCTION REGISTER MAP FOR
PIC18F2682/2685/4682/4685 DEVICES (CONTINUED)
Address
Name
D7Fh
D7Eh
D7Dh
D7Ch
D7Bh
D7Ah
D79h
D78h
D77h
D76h
D75h
D74h
D73h
D72h
D71h
D70h
D6Fh
D6Eh
D6Dh
D6Ch
D6Bh
D6Ah
D69h
D68h
D67h
D66h
D65h
D64h
D63h
D62h
D61h
D60h
—
—
—
—
RXF11EIDL
RXF11EIDH
RXF11SIDL
RXF11SIDH
RXF10EIDL
RXF10EIDH
RXF10SIDL
RXF10SIDH
RXF9EIDL
RXF9EIDH
RXF9SIDL
RXF9SIDH
—
—
—
—
RXF8EIDL
RXF8EIDH
RXF8SIDL
RXF8SIDH
RXF7EIDL
RXF7EIDH
RXF7SIDL
RXF7SIDH
RXF6EIDL
RXF6EIDH
RXF6SIDL
RXF6SIDH
Note 1: Registers available only on PIC18F4X8X devices; otherwise, the registers read as ‘0’.
2: When any TX_ENn bit in RX_TX_SELn is set, then the corresponding bit in this register has transmit properties.
3: This is not a physical register.
© 2007 Microchip Technology Inc.
Preliminary
DS39761B-page 75
PIC18F2682/2685/4682/4685
TABLE 5-2:
REGISTER FILE SUMMARY (PIC18F2682/2685/4682/4685)
Value on
POR, BOR on page:
Details
File Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
TOSU
—
—
—
Top-of-Stack Register Upper Byte (TOS<20:16>)
---0 0000 49, 62
0000 0000 49, 62
0000 0000 49, 62
00-0 0000 49, 63
---0 0000 49, 62
0000 0000 49, 62
0000 0000 49, 62
--00 0000 49, 103
0000 0000 49, 103
0000 0000 49, 103
0000 0000 49, 103
xxxx xxxx 49, 111
xxxx xxxx 49, 111
0000 000x 49, 115
1111 -1-1 49, 116
11-0 0-00 49, 117
TOSH
Top-of-Stack Register High Byte (TOS<15:8>)
Top-of-Stack Register Low Byte (TOS<7:0>)
TOSL
STKPTR
PCLATU
PCLATH
PCL
STKFUL
—
STKUNF
—
—
SP4
SP3
SP2
SP1
SP0
bit 21(1) Holding Register for PC<20:16>
Holding Register for PC<15:8>
PC Low Byte (PC<7:0>)
TBLPTRU
TBLPTRH
TBLPTRL
TABLAT
PRODH
PRODL
—
—
bit 21
Program Memory Table Pointer Upper Byte (TBLPTR<20:16>)
Program Memory Table Pointer High Byte (TBLPTR<15:8>)
Program Memory Table Pointer Low Byte (TBLPTR<7:0>)
Program Memory Table Latch
Product Register High Byte
Product Register Low Byte
INTCON
INTCON2
INTCON3
INDF0
GIE/GIEH PEIE/GIEL
TMR0IE
INTEDG1 INTEDG2
INT2IE
INT0IE
RBIE
—
TMR0IF
TMR0IP
—
INT0IF
—
RBIF
RBIP
RBPU
INTEDG0
INT1IP
INT2IP
—
INT1IE
INT2IF
INT1IF
Uses contents of FSR0 to address data memory – value of FSR0 not changed (not a physical register)
Uses contents of FSR0 to address data memory – value of FSR0 post-incremented (not a physical register)
N/A
N/A
N/A
N/A
N/A
49, 89
49, 90
49, 90
49, 90
49, 90
POSTINC0
POSTDEC0
PREINC0
PLUSW0
Uses contents of FSR0 to address data memory – value of FSR0 post-decremented (not a physical register)
Uses contents of FSR0 to address data memory – value of FSR0 pre-incremented (not a physical register)
Uses contents of FSR0 to address data memory – value of FSR0 pre-incremented (not a physical register),
value of FSR0 offset by W
FSR0H
—
—
—
—
Indirect Data Memory Address Pointer 0 High
---- xxxx 49, 89
xxxx xxxx 49, 89
FSR0L
Indirect Data Memory Address Pointer 0 Low Byte
Working Register
WREG
xxxx xxxx
N/A
49
INDF1
Uses contents of FSR1 to address data memory – value of FSR1 not changed (not a physical register)
Uses contents of FSR1 to address data memory – value of FSR1 post-incremented (not a physical register)
Uses contents of FSR1 to address data memory – value of FSR1 post-decremented (not a physical register)
Uses contents of FSR1 to address data memory – value of FSR1 pre-incremented (not a physical register)
49, 89
49, 90
49, 90
49, 90
49, 90
POSTINC1
POSTDEC1
PREINC1
PLUSW1
N/A
N/A
N/A
Uses contents of FSR1 to address data memory – value of FSR1 pre-incremented (not a physical register),
value of FSR1 offset by W
N/A
FSR1H
—
—
—
—
Indirect Data Memory Address Pointer 1 High
---- xxxx 49, 89
xxxx xxxx 49, 89
---- 0000 50, 67
FSR1L
Indirect Data Memory Address Pointer 1 Low Byte
BSR
—
—
—
—
Bank Select Register
INDF2
Uses contents of FSR2 to address data memory – value of FSR2 not changed (not a physical register)
Uses contents of FSR2 to address data memory – value of FSR2 post-incremented (not a physical register)
Uses contents of FSR2 to address data memory – value of FSR2 post-decremented (not a physical register)
Uses contents of FSR2 to address data memory – value of FSR2 pre-incremented (not a physical register)
N/A
N/A
N/A
N/A
N/A
50, 89
50, 90
50, 90
50, 90
50, 90
POSTINC2
POSTDEC2
PREINC2
PLUSW2
Uses contents of FSR2 to address data memory – value of FSR2 pre-incremented (not a physical register),
value of FSR2 offset by W
FSR2H
FSR2L
—
—
—
—
Indirect Data Memory Address Pointer 2 High
---- xxxx 50, 89
xxxx xxxx 50, 89
Indirect Data Memory Address Pointer 2 Low Byte
Legend: x= unknown, u= unchanged, -= unimplemented, q= value depends on condition. Shaded cells are unimplemented, read as ‘0’.
Note 1: Bit 21 of the PC is only available in Test mode and Serial Programming modes.
2: The SBOREN bit is only available when CONFIG2L<1:0> = 01; otherwise, it is disabled and reads as ‘0’. See Section 4.4 “Brown-out Reset
(BOR)”.
3: These registers and/or bits are not implemented on PIC18F2682/2685 devices and are read as ‘0’. Reset values are shown for PIC18F4682/4685
devices; individual unimplemented bits should be interpreted as ‘—’.
4: The PLLEN bit is only available in specific oscillator configurations; otherwise, it is disabled and reads as ‘0’. See Section 2.6.4 “PLL in INTOSC
Modes”.
5: The RE3 bit is only available when Master Clear Reset is disabled (CONFIG3H<7> = 0); otherwise, RE3 reads as ‘0’. This bit is read-only.
6: RA6/RA7 and their associated latch and direction bits are individually configured as port pins based on various primary oscillator modes. When
disabled, these bits read as ‘0’.
7: CAN bits have multiple functions depending on the selected mode of the CAN module.
8: This register reads all ‘0’s until the ECAN™ technology is set up in Mode 1 or Mode 2.
9: These registers and/or bits are available on PIC18F4682/4685 devices only.
DS39761B-page 76
Preliminary
© 2007 Microchip Technology Inc.
PIC18F2682/2685/4682/4685
TABLE 5-2:
REGISTER FILE SUMMARY (PIC18F2682/2685/4682/4685) (CONTINUED)
Value on
POR, BOR on page:
Details
File Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
STATUS
TMR0H
TMR0L
—
—
—
N
OV
Z
DC
C
---x xxxx 50, 87
0000 0000 50, 149
xxxx xxxx 50, 149
1111 1111 50, 149
0100 q000 30, 50
0-00 0101 50, 267
--- ---0 50, 354
0q-1 11q0 50, 127
xxxx xxxx 50, 155
0000 0000 50, 155
0000 0000 50, 151
1111 1111 50, 158
-000 0000 50, 155
-000 0000 50, 157
xxxx xxxx 50, 195
0000 0000 50, 195
0000 0000 50, 197
0000 0000 50, 198
0000 0000 50, 199
xxxx xxxx 50, 256
xxxx xxxx 50, 256
--00 0000 50, 247
--00 0qqq 50, 248
0-00 0000 51, 249
xxxx xxxx 51, 168
xxxx xxxx 51, 168
--00 0000 51, 163
xxxx xxxx 51, 167
xxxx xxxx 51, 167
0000 0000 51, 168
01-0 0-00 51, 230
0000 0000 51, 182
0000 0000 51, 183
0000 0000 51, 263
0000 0000 51, 257
xxxx xxxx 51, 161
xxxx xxxx 51, 161
Timer0 Register High Byte
Timer0 Register Low Byte
T0CON
OSCCON
HLVDCON
WDTCON
RCON
TMR0ON
IDLEN
VDIRMAG
—
T08BIT
IRCF2
—
T0CS
IRCF1
IRVST
—
T0SE
IRCF0
HLVDEN
—
PSA
OSTS
HLVDL3
—
T0PS2
IOFS
HLVDL2
—
T0PS1
SCS1
HLVDL1
—
T0PS0
SCS0
HLVDL0
SWDTEN
BOR
—
IPEN
SBOREN(2)
—
RI
TO
PD
POR
TMR1H
TMR1L
Timer1 Register High Byte
Timer1 Register Low Byte
T1CON
RD16
Timer2 Register
Timer2 Period Register
T2OUTPS3 T2OUTPS2 T2OUTPS1 T2OUTPS0
MSSP Receive Buffer/Transmit Register
MSSP Address Register in I2C™ Slave mode, MSSP Baud Rate Reload Register in I2C Master mode
T1RUN
T1CKPS1 T1CKPS0
T1OSCEN
T1SYNC
TMR1CS
TMR1ON
T2CKPS0
TMR2
PR2
T2CON
—
TMR2ON
T2CKPS1
SSPBUF
SSPADD
SSPSTAT
SSPCON1
SSPCON2
ADRESH
ADRESL
ADCON0
ADCON1
ADCON2
CCPR1H
CCPR1L
CCP1CON
SMP
WCOL
GCEN
CKE
D/A
P
S
R/W
SSPM2
PEN
UA
BF
SSPOV
ACKSTAT
SSPEN
ACKDT
CKP
SSPM3
RCEN
SSPM1
RSEN
SSPM0
SEN
ACKEN
A/D Result Register High Byte
A/D Result Register Low Byte
—
—
—
—
—
CHS3
VCFG1
ACQT2
CHS2
VCFG0
ACQT1
CHS1
PCFG3
ACQT0
CHS0
PCFG2
ADCS2
GO/DONE
PCFG1
ADON
PCFG0
ADCS0
ADFM
ADCS1
Capture/Compare/PWM Register 1 High Byte
Capture/Compare/PWM Register 1 Low Byte
—
—
DC1B1
DC1B0
CCP1M3
CCP1M2
CCP1M1
CCP1M0
ECCPR1H(9) Enhanced Capture/Compare/PWM Register 1 High Byte
ECCPR1L(9)
Enhanced Capture/Compare/PWM Register 1 Low Byte
ECCP1CON(9) EPWM1M1 EPWM1M0 EDC1B1
EDC1B0
SCKP
PDC4(3)
ECCP1M3
BRG16
PDC3(3)
PSSAC1
CVR3
ECCP1M2
—
PDC2(3)
PSSAC0
CVR2
ECCP1M1
WUE
PDC1(3)
PSSBD1(3)
CVR1
ECCP1M0
ABDEN
PDC0(3)
PSSBD0(3)
CVR0
BAUDCON
ECCP1DEL(9)
ECCP1AS(9)
CVRCON(9)
CMCON(9)
TMR3H
ABDOVF
PRSEN
RCIDL
PDC6(3)
—
PDC5(3)
ECCPASE ECCPAS2 ECCPAS1 ECCPAS0
CVREN
C2OUT
CVROE
C1OUT
CVRR
C2INV
CVRSS
C1INV
CIS
CM2
CM1
CM0
Timer3 Register High Byte
Timer3 Register Low Byte
TMR3L
T3CON
RD16
T3ECCP1(9) T3CKPS1 T3CKPS0
T3CCP1(9)
T3SYNC
TMR3CS
TMR3ON
0000 0000 51, 161
Legend: x= unknown, u= unchanged, -= unimplemented, q= value depends on condition. Shaded cells are unimplemented, read as ‘0’.
Note 1: Bit 21 of the PC is only available in Test mode and Serial Programming modes.
2: The SBOREN bit is only available when CONFIG2L<1:0> = 01; otherwise, it is disabled and reads as ‘0’. See Section 4.4 “Brown-out Reset
(BOR)”.
3: These registers and/or bits are not implemented on PIC18F2682/2685 devices and are read as ‘0’. Reset values are shown for PIC18F4682/4685
devices; individual unimplemented bits should be interpreted as ‘—’.
4: The PLLEN bit is only available in specific oscillator configurations; otherwise, it is disabled and reads as ‘0’. See Section 2.6.4 “PLL in INTOSC
Modes”.
5: The RE3 bit is only available when Master Clear Reset is disabled (CONFIG3H<7> = 0); otherwise, RE3 reads as ‘0’. This bit is read-only.
6: RA6/RA7 and their associated latch and direction bits are individually configured as port pins based on various primary oscillator modes. When
disabled, these bits read as ‘0’.
7: CAN bits have multiple functions depending on the selected mode of the CAN module.
8: This register reads all ‘0’s until the ECAN™ technology is set up in Mode 1 or Mode 2.
9: These registers and/or bits are available on PIC18F4682/4685 devices only.
© 2007 Microchip Technology Inc.
Preliminary
DS39761B-page 77
PIC18F2682/2685/4682/4685
TABLE 5-2:
REGISTER FILE SUMMARY (PIC18F2682/2685/4682/4685) (CONTINUED)
Value on
POR, BOR on page:
Details
File Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
SPBRGH
SPBRG
RCREG
TXREG
TXSTA
EUSART Baud Rate Generator Register High Byte
EUSART Baud Rate Generator Register Low Byte
EUSART Receive Register
0000 0000 51, 231
0000 0000 51, 231
0000 0000 51, 238
0000 0000 51, 236
0000 0010 51, 237
0000 000x 51, 237
EUSART Transmit Register
CSRC
SPEN
—
TX9
RX9
—
TXEN
SREN
—
SYNC
CREN
—
SENDB
ADDEN
—
BRGH
FERR
—
TRMT
OERR
TX9D
RX9D
RCSTA
EEADRH
EEADR
EEDATA
EECON2
EECON1
EEPROM Addr Register High Byte ---- --00 51, 108
0000 0000 51, 105
EEPROM Address Register Low Byte
EEPROM Data Register
0000 0000 51, 105
EEPROM Control Register 2 (not a physical register)
0000 0000 51, 105
EEPGD
IRXIP
CFGS
—
FREE
WRERR
TXB1IP
WREN
WR
RD
xx-0 x000 51, 105
1111 1111 51, 126
IPR3
WAKIP
ERRIP
TXB2IP
TXB0IP
RXB1IP
RXB0IP
Mode 0
IPR3
Mode 1, 2
IRXIP
IRXIF
IRXIF
IRXIE
IRXIE
WAKIP
WAKIF
WAKIF
WAKIE
WAKIE
ERRIP
ERRIF
ERRIF
ERRIE
ERRIE
TXBnIP
TXB2IF
TXBnIF
TXB2IE
TXBnIE
TXB1IP(8)
TXB1IF
TXB0IP(8)
TXB0IF
RXBnIP
RXB1IF
RXBnIF
RXB1IE
RXBnIE
FIFOWMIP
RXB0IF
1111 1111 51, 126
0000 0000 51, 120
0000 0000 51, 120
0000 0000 51, 123
0000 0000 51, 123
PIR3
Mode 0
PIR3
Mode 1, 2
TXB1IF(8)
TXB1IE
TXB0IF(8)
TXB0IE
FIFOWMIF
RXB0IE
PIE3
Mode 0
PIE3
TXB1IE(8)
TXB0IE(8)
FIFOMWIE
Mode 1, 2
IPR2
OSCFIP
OSCFIF
OSCFIE
PSPIP(3)
PSPIF(3)
PSPIE(3)
INTSRC
IBF
CMIP(9)
CMIF(9)
CMIE(9)
ADIP
—
—
EEIP
EEIF
BCLIP
BCLIF
BCLIE
SSPIP
SSPIF
SSPIE
TUN3
—
HLVDIP
HLVDIF
HLVDIE
CCP1IP
CCP1IF
CCP1IE
TUN2
TMR3IP
TMR3IF
TMR3IE
TMR2IP
TMR2IF
TMR2IE
TUN1
ECCP1IP(9) 11-1 1111 51, 125
ECCP1IF(9) 00-0 0000 52, 119
ECCP1IE(9) 00-0 0000 52, 122
PIR2
PIE2
—
EEIE
IPR1
RCIP
RCIF
RCIE
—
TXIP
TMR1IP
TMR1IF
TMR1IE
TUN0
1111 1111 52, 124
0000 0000 52, 118
0000 0000 52, 121
0q-0 0000 27, 52
0000 -111 52, 141
1111 1111 52, 138
1111 1111 52, 135
1111 1111 52, 132
1111 1111 52, 129
---- -xxx 52, 141
xxxx xxxx 52, 138
xxxx xxxx 52, 135
xxxx xxxx 52, 132
xxxx xxxx 52, 129
---- xxxx 52, 145
xxxx xxxx 52, 138
xxxx xxxx 52, 135
PIR1
ADIF
TXIF
PIE1
ADIE
PLLEN(4)
TXIE
OSCTUNE
TRISE(3)
TRISD(3)
TRISC
TRISB
TRISA
LATE(3)
LATD(3)
LATC
TUN4
PSPMODE
OBF
IBOV
TRISE2
TRISE1
TRISE0
PORTD Data Direction Register
PORTC Data Direction Register
PORTB Data Direction Register
TRISA7(6)
TRISA6(6) PORTA Data Direction Register
—
—
—
—
—
LATE Data Output Register
LATD Data Output Register
LATC Data Output Register
LATB Data Output Register
LATB
LATA
LATA7(6)
LATA6(6) LATA Data Output Register
PORTE(3)
PORTD(3)
PORTC
—
—
—
—
RE3(5)
RD3
RE2(3)
RD2
RE1(3)
RD1
RE0(3)
RD0
RD7
RD6
RC6
RD5
RC5
RD4
RC4
RC7
RC3
RC2
RC1
RC0
Legend: x= unknown, u= unchanged, -= unimplemented, q= value depends on condition. Shaded cells are unimplemented, read as ‘0’.
Note 1: Bit 21 of the PC is only available in Test mode and Serial Programming modes.
2: The SBOREN bit is only available when CONFIG2L<1:0> = 01; otherwise, it is disabled and reads as ‘0’. See Section 4.4 “Brown-out Reset
(BOR)”.
3: These registers and/or bits are not implemented on PIC18F2682/2685 devices and are read as ‘0’. Reset values are shown for PIC18F4682/4685
devices; individual unimplemented bits should be interpreted as ‘—’.
4: The PLLEN bit is only available in specific oscillator configurations; otherwise, it is disabled and reads as ‘0’. See Section 2.6.4 “PLL in INTOSC
Modes”.
5: The RE3 bit is only available when Master Clear Reset is disabled (CONFIG3H<7> = 0); otherwise, RE3 reads as ‘0’. This bit is read-only.
6: RA6/RA7 and their associated latch and direction bits are individually configured as port pins based on various primary oscillator modes. When
disabled, these bits read as ‘0’.
7: CAN bits have multiple functions depending on the selected mode of the CAN module.
8: This register reads all ‘0’s until the ECAN™ technology is set up in Mode 1 or Mode 2.
9: These registers and/or bits are available on PIC18F4682/4685 devices only.
DS39761B-page 78
Preliminary
© 2007 Microchip Technology Inc.
PIC18F2682/2685/4682/4685
TABLE 5-2:
REGISTER FILE SUMMARY (PIC18F2682/2685/4682/4685) (CONTINUED)
Value on
POR, BOR on page:
Details
File Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PORTB
RB7
RA7(6)
MDSEL1
TEC7
RB6
RA6(6)
MDSEL0
TEC6
RB5
RA5
RB4
RA4
RB3
RA3
RB2
RA2
RB1
RA1
RB0
RA0
xxxx xxxx 52, 132
xx00 0000 52, 129
0001 000 52, 280
0000 0000 52, 285
0000 0000 52, 294
0000 0000 52, 281
PORTA
ECANCON
TXERRCNT
RXERRCNT
FIFOWM
TEC5
EWIN4
TEC4
REC4
TXBP
EWIN3
TEC3
REC3
RXBP
EWIN2
TEC2
EWIN1
TEC1
EWIN0
TEC0
REC7
REC6
REC5
TXBO
REC2
REC1
REC0
EWARN
COMSTAT
Mode 0
RXB0OVFL RXB1OVFL
TXWARN
RXWARN
COMSTAT
Mode 1
—
RXBnOVFL
TXBO
TXBO
TXBP
TXBP
RXBP
RXBP
TXWARN
TXWARN
RXWARN
RXWARN
EWARN
EWARN
-000 0000 52, 281
0000 0000 52, 281
COMSTAT
Mode 2
FIFOEMPT RXBnOVFL
Y
CIOCON
—
—
ENDRHI
—
CANCAP
—
—
—
—
—
—
--00 ---- 52, 315
00-- -000 53, 314
0000 0000 53, 313
0000 0000 53, 312
1000 000- 53, 276
BRGCON3
BRGCON2
BRGCON1
WAKDIS
SEG2PHTS
SJW1
WAKFIL
SAM
SEG2PH2
PRSEG2
BRP2
SEG2PH1
PRSEG1
BRP1
SEG2PH0
PRSEG0
BRP0
SEG1PH2 SEG1PH1
SEG1PH0
SJW0
BRP5
BRP4
ABAT
BRP3
WIN2(7)
(7)
CANCON
Mode 0
REQOP2
REQOP1
REQOP0
WIN1(7)
WIN0(7)
—
(7)
(7)
(7)
(7)
CANCON
Mode 1
REQOP2
REQOP2
REQOP1
REQOP1
REQOP0
REQOP0
ABAT
ABAT
—
—
—
—
1000 ---- 53, 276
1000 0000 53, 276
100- 000- 53, 277
CANCON
Mode 2
FP3(7)
FP2(7)
FP1(7)
FP0(7)
(7)
(7)
CANSTAT
Mode 0
OPMODE2 OPMODE1 OPMODE0
—
ICODE3(7)
ICODE2(7)
ICODE1(7)
EICODE1(7)
—
CANSTAT
Modes 1, 2
OPMODE2 OPMODE1 OPMODE0 EICODE4(7) EICODE3(7) EICODE2(7)
EICODE0(7) 1000 0000 53, 277
RXB0D7
RXB0D6
RXB0D5
RXB0D4
RXB0D3
RXB0D2
RXB0D1
RXB0D0
RXB0DLC
RXB0EIDL
RXB0EIDH
RXB0SIDL
RXB0SIDH
RXB0D77
RXB0D67
RXB0D57
RXB0D47
RXB0D37
RXB0D27
RXB0D17
RXB0D07
—
RXB0D76 RXB0D75 RXB0D74
RXB0D66 RXB0D65 RXB0D64
RXB0D56 RXB0D55 RXB0D54
RXB0D46 RXB0D45 RXB0D44
RXB0D36 RXB0D35 RXB0D34
RXB0D26 RXB0D25 RXB0D24
RXB0D16 RXB0D15 RXB0D14
RXB0D06 RXB0D05 RXB0D04
RXB0D73
RXB0D63
RXB0D53
RXB0D43
RXB0D33
RXB0D23
RXB0D13
RXB0D03
DLC3
RXB0D72
RXB0D62
RXB0D52
RXB0D42
RXB0D32
RXB0D22
RXB0D12
RXB0D02
DLC2
RXB0D71
RXB0D61
RXB0D51
RXB0D41
RXB0D31
RXB0D21
RXB0D11
RXB0D01
DLC1
RXB0D70
RXB0D60
RXB0D50
RXB0D40
RXB0D30
RXB0D20
RXB0D10
RXB0D00
DLC0
xxxx xxxx 53, 293
xxxx xxxx 53, 293
xxxx xxxx 53, 293
xxxx xxxx 53, 293
xxxx xxxx 53, 293
xxxx xxxx 53, 293
xxxx xxxx 53, 293
xxxx xxxx 53, 293
-xxx xxxx 53, 293
xxxx xxxx 53, 292
xxxx xxxx 53, 292
xxxx x-xx 53, 292
xxxx xxxx 53, 291
000- 0000 53, 288
RXRTR
EID6
RB1
EID5
RB0
EID4
EID12
SRR
SID7
EID7
EID3
EID2
EID1
EID0
EID15
EID14
SID1
EID13
SID0
EID11
EID10
EID9
EID8
SID2
EXID
—
EID17
EID16
SID10
SID9
SID8
SID6
SID5
SID4
JTOFF(7)
SID3
FILHIT0(7)
(7)
RXB0CON
Mode 0
RXFUL
RXM1
RXM0(7)
—
RXRTRRO(7) RXBODBEN(7)
RXB0CON
Mode 1, 2
RXFUL
RXM1
RTRRO
FILHIT4
FILHIT3
FILHIT2
FILHIT1
FILHIT0
0000 0000 53, 288
RXB1D7
RXB1D6
RXB1D77
RXB1D67
RXB1D76 RXB1D75 RXB1D74
RXB1D66 RXB1D65 RXB1D64
RXB1D73
RXB1D63
RXB1D72
RXB1D62
RXB1D71
RXB1D61
RXB1D70
RXB1D60
xxxx xxxx 53, 293
xxxx xxxx 53, 293
Legend: x= unknown, u= unchanged, -= unimplemented, q= value depends on condition. Shaded cells are unimplemented, read as ‘0’.
Note 1: Bit 21 of the PC is only available in Test mode and Serial Programming modes.
2: The SBOREN bit is only available when CONFIG2L<1:0> = 01; otherwise, it is disabled and reads as ‘0’. See Section 4.4 “Brown-out Reset
(BOR)”.
3: These registers and/or bits are not implemented on PIC18F2682/2685 devices and are read as ‘0’. Reset values are shown for PIC18F4682/4685
devices; individual unimplemented bits should be interpreted as ‘—’.
4: The PLLEN bit is only available in specific oscillator configurations; otherwise, it is disabled and reads as ‘0’. See Section 2.6.4 “PLL in INTOSC
Modes”.
5: The RE3 bit is only available when Master Clear Reset is disabled (CONFIG3H<7> = 0); otherwise, RE3 reads as ‘0’. This bit is read-only.
6: RA6/RA7 and their associated latch and direction bits are individually configured as port pins based on various primary oscillator modes. When
disabled, these bits read as ‘0’.
7: CAN bits have multiple functions depending on the selected mode of the CAN module.
8: This register reads all ‘0’s until the ECAN™ technology is set up in Mode 1 or Mode 2.
9: These registers and/or bits are available on PIC18F4682/4685 devices only.
© 2007 Microchip Technology Inc.
Preliminary
DS39761B-page 79
PIC18F2682/2685/4682/4685
TABLE 5-2:
REGISTER FILE SUMMARY (PIC18F2682/2685/4682/4685) (CONTINUED)
Value on
POR, BOR on page:
Details
File Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
RXB1D5
RXB1D57
RXB1D47
RXB1D37
RXB1D27
RXB1D17
RXB1D07
—
RXB1D56 RXB1D55 RXB1D54
RXB1D46 RXB1D45 RXB1D44
RXB1D36 RXB1D35 RXB1D34
RXB1D26 RXB1D25 RXB1D24
RXB1D16 RXB1D15 RXB1D14
RXB1D06 RXB1D05 RXB1D04
RXB1D53
RXB1D43
RXB1D33
RXB1D23
RXB1D13
RXB1D03
DLC3
RXB1D52
RXB1D42
RXB1D32
RXB1D22
RXB1D12
RXB1D02
DLC2
RXB1D51
RXB1D41
RXB1D31
RXB1D21
RXB1D11
RXB1D01
DLC1
RXB1D50
RXB1D40
RXB1D30
RXB1D20
RXB1D10
RXB1D00
DLC0
xxxx xxxx 53, 293
xxxx xxxx 53, 293
xxxx xxxx 53, 293
xxxx xxxx 53, 293
xxxx xxxx 53, 293
xxxx xxxx 53, 293
-xxx xxxx 53, 293
xxxx xxxx 53, 292
xxxx xxxx 53, 292
xxxx xxxx 53, 292
xxxx xxxx 54, 291
000- 0000 54, 290
RXB1D4
RXB1D3
RXB1D2
RXB1D1
RXB1D0
RXB1DLC
RXB1EIDL
RXB1EIDH
RXB1SIDL
RXB1SIDH
RXRTR
EID6
RB1
EID5
RB0
EID4
EID12
SRR
SID7
EID7
EID3
EID2
EID1
EID0
EID15
EID14
SID1
EID13
SID0
EID11
EID10
EID9
EID8
SID2
EXID
—
EID17
EID16
SID10
SID9
SID8
SID6
RXRTRRO(7)
SID5
FILHIT2(7)
SID4
FILHIT1(7)
SID3
FILHIT0(7)
(7)
RXB1CON
Mode 0
RXFUL
RXM1
RXM0(7)
—
RXB1CON
Mode 1, 2
RXFUL
RXM1
RTRRO
FILHIT4
FILHIT3
FILHIT2
FILHIT1
FILHIT0
0000 0000 54, 290
TXB0D7
TXB0D77
TXB0D67
TXB0D57
TXB0D47
TXB0D37
TXB0D27
TXB0D17
TXB0D07
—
TXB0D76
TXB0D66
TXB0D56
TXB0D46
TXB0D36
TXB0D26
TXB0D16
TXB0D06
TXRTR
EID6
TXB0D75 TXB0D74
TXB0D65 TXB0D64
TXB0D55 TXB0D54
TXB0D45 TXB0D44
TXB0D35 TXB0D34
TXB0D25 TXB0D24
TXB0D15 TXB0D14
TXB0D05 TXB0D04
TXB0D73
TXB0D63
TXB0D53
TXB0D43
TXB0D33
TXB0D23
TXB0D13
TXB0D03
DLC3
TXB0D72
TXB0D62
TXB0D52
TXB0D42
TXB0D32
TXB0D22
TXB0D12
TXB0D02
DLC2
TXB0D71
TXB0D61
TXB0D51
TXB0D41
TXB0D31
TXB0D21
TXB0D11
TXB0D01
DLC1
TXB0D70
TXB0D60
TXB0D50
TXB0D40
TXB0D30
TXB0D20
TXB0D10
TXB0D00
DLC0
xxxx xxxx 54, 284
xxxx xxxx 54, 284
xxxx xxxx 54, 284
xxxx xxxx 54, 284
xxxx xxxx 54, 284
xxxx xxxx 54, 284
xxxx xxxx 54, 284
xxxx xxxx 54, 284
-x-- xxxx 54, 285
xxxx xxxx 54, 284
xxxx xxxx 54, 283
xxx- x-xx 54, 283
xxxx xxxx 54, 283
0000 0-00 54, 282
xxxx xxxx 54, 284
xxxx xxxx 54, 284
xxxx xxxx 54, 284
xxxx xxxx 54, 284
xxxx xxxx 54, 284
xxxx xxxx 54, 284
xxxx xxxx 54, 284
xxxx xxxx 54, 284
-x-- xxxx 54, 285
xxxx xxxx 54, 284
xxxx xxxx 54, 283
xxx- x-xx 54, 283
xxxx xxxx 54, 283
TXB0D6
TXB0D5
TXB0D4
TXB0D3
TXB0D2
TXB0D1
TXB0D0
TXB0DLC
TXB0EIDL
TXB0EIDH
TXB0SIDL
TXB0SIDH
TXB0CON
TXB1D7
—
EID5
—
EID4
EID12
—
EID7
EID3
EID2
EID1
EID0
EID15
EID14
EID13
SID0
EID11
EID10
EID9
EID8
SID2
SID1
EXIDE
—
EID17
EID16
SID10
SID9
SID8
SID7
TXERR
SID6
SID5
SID4
SID3
TXBIF
TXABT
TXLARB
TXREQ
TXB1D73
TXB1D63
TXB1D53
TXB1D43
TXB1D33
TXB1D23
TXB1D13
TXB1D03
DLC3
—
TXPRI1
TXB1D71
TXB1D61
TXB1D51
TXB1D41
TXB1D31
TXB1D21
TXB1D11
TXB1D01
DLC1
TXPRI0
TXB1D70
TXB1D60
TXB1D50
TXB1D40
TXB1D30
TXB1D20
TXB1D10
TXB1D00
DLC0
TXB1D77
TXB1D67
TXB1D57
TXB1D47
TXB1D37
TXB1D27
TXB1D17
TXB1D07
—
TXB1D76
TXB1D66
TXB1D56
TXB1D46
TXB1D36
TXB1D26
TXB1D16
TXB1D06
TXRTR
EID6
TXB1D75 TXB1D74
TXB1D65 TXB1D64
TXB1D55 TXB1D54
TXB1D45 TXB1D44
TXB1D35 TXB1D34
TXB1D25 TXB1D24
TXB1D15 TXB1D14
TXB1D05 TXB1D04
TXB1D72
TXB1D62
TXB1D52
TXB1D42
TXB1D32
TXB1D22
TXB1D12
TXB1D02
DLC2
TXB1D6
TXB1D5
TXB1D4
TXB1D3
TXB1D2
TXB1D1
TXB1D0
TXB1DLC
TXB1EIDL
TXB1EIDH
TXB1SIDL
TXB1SIDH
—
—
EID4
EID12
—
EID7
EID5
EID13
SID0
SID8
EID3
EID2
EID1
EID0
EID15
EID14
EID11
EID10
EID9
EID8
SID2
SID1
EXIDE
—
EID17
EID16
SID10
SID9
SID7
SID6
SID5
SID4
SID3
Legend: x= unknown, u= unchanged, -= unimplemented, q= value depends on condition. Shaded cells are unimplemented, read as ‘0’.
Note 1: Bit 21 of the PC is only available in Test mode and Serial Programming modes.
2: The SBOREN bit is only available when CONFIG2L<1:0> = 01; otherwise, it is disabled and reads as ‘0’. See Section 4.4 “Brown-out Reset
(BOR)”.
3: These registers and/or bits are not implemented on PIC18F2682/2685 devices and are read as ‘0’. Reset values are shown for PIC18F4682/4685
devices; individual unimplemented bits should be interpreted as ‘—’.
4: The PLLEN bit is only available in specific oscillator configurations; otherwise, it is disabled and reads as ‘0’. See Section 2.6.4 “PLL in INTOSC
Modes”.
5: The RE3 bit is only available when Master Clear Reset is disabled (CONFIG3H<7> = 0); otherwise, RE3 reads as ‘0’. This bit is read-only.
6: RA6/RA7 and their associated latch and direction bits are individually configured as port pins based on various primary oscillator modes. When
disabled, these bits read as ‘0’.
7: CAN bits have multiple functions depending on the selected mode of the CAN module.
8: This register reads all ‘0’s until the ECAN™ technology is set up in Mode 1 or Mode 2.
9: These registers and/or bits are available on PIC18F4682/4685 devices only.
DS39761B-page 80
Preliminary
© 2007 Microchip Technology Inc.
PIC18F2682/2685/4682/4685
TABLE 5-2:
REGISTER FILE SUMMARY (PIC18F2682/2685/4682/4685) (CONTINUED)
Value on
POR, BOR on page:
Details
File Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
TXB1CON
TXB2D7
TXBIF
TXB2D77
TXB2D67
TXB2D57
TXB2D47
TXB2D37
TXB2D27
TXB2D17
TXB2D07
—
TXABT
TXB2D76
TXB2D66
TXB2D56
TXB2D46
TXB2D36
TXB2D26
TXB2D16
TXB2D06
TXRTR
EID6
TXLARB
TXERR
TXREQ
TXB2D73
TXB2D63
TXB2D53
TXB2D43
TXB2D33
TXB2D23
TXB2D13
TXB2D03
DLC3
—
TXB2D72
TXB2D62
TXB2D52
TXB2D42
TXB2D32
TXB2D22
TXB2D12
TXB2D02
DLC2
EID2
TXPRI1
TXB2D71
TXB2D61
TXB2D51
TXB2D41
TXB2D31
TXB2D21
TXB2D11
TXB2D01
DLC1
EID1
TXPRI0
TXB2D70
TXB2D60
TXB2D50
TXB2D40
TXB2D30
TXB2D20
TXB2D10
TXB2D00
DLC0
0000 0-00 54, 282
xxxx xxxx 54, 284
xxxx xxxx 55, 284
xxxx xxxx 55, 284
xxxx xxxx 55, 284
xxxx xxxx 55, 284
xxxx xxxx 55, 284
xxxx xxxx 55, 284
xxxx xxxx 55, 284
-x-- xxxx 55, 285
xxxx xxxx 55, 284
xxxx xxxx 55, 283
xxxx x-xx 55, 283
xxx- x-xx 55, 283
0000 0-00 55, 282
xxxx xxxx 55, 305
xxxx xxxx 55, 305
xxx- x-xx 55, 305
xxxx xxxx 55, 304
xxxx xxxx 55, 305
xxxx xxxx 55, 305
xxx- x-xx 55, 305
xxxx xxxx 55, 304
xxxx xxxx 55, 304
xxxx xxxx 55, 304
xxx- x-xx 55, 303
xxxx xxxx 55, 304
xxxx xxxx 55, 304
xxxx xxxx 55, 304
xxx- x-xx 55, 303
xxxx xxxx 55, 304
xxxx xxxx 55, 304
xxxx xxxx 55, 304
xxx- x-xx 56, 303
xxxx xxxx 56, 304
xxxx xxxx 56, 304
xxxx xxxx 56, 304
xxx- x-xx 56, 303
xxxx xxxx 56, 304
xxxx xxxx 56, 304
xxxx xxxx 56, 304
TXB2D75 TXB2D74
TXB2D65 TXB2D64
TXB2D55 TXB2D54
TXB2D45 TXB2D44
TXB2D35 TXB2D34
TXB2D25 TXB2D24
TXB2D15 TXB2D14
TXB2D05 TXB2D04
TXB2D6
TXB2D5
TXB2D4
TXB2D3
TXB2D2
TXB2D1
TXB2D0
TXB2DLC
TXB2EIDL
TXB2EIDH
TXB2SIDL
TXB2SIDH
TXB2CON
RXM1EIDL
RXM1EIDH
RXM1SIDL
RXM1SIDH
RXM0EIDL
RXM0EIDH
RXM0SIDL
RXM0SIDH
RXF5EIDL
RXF5EIDH
RXF5SIDL
RXF5SIDH
RXF4EIDL
RXF4EIDH
RXF4SIDL
RXF4SIDH
RXF3EIDL
RXF3EIDH
RXF3SIDL
RXF3SIDH
RXF2EIDL
RXF2EIDH
RXF2SIDL
RXF2SIDH
RXF1EIDL
RXF1EIDH
—
EID5
EID13
SID0
SID8
TXLARB
EID5
EID13
SID0
SID8
EID5
EID13
SID0
SID8
EID5
EID13
SID0
SID8
EID5
EID13
SID0
SID8
EID5
EID13
SID0
SID8
EID5
EID13
SID0
SID8
EID5
EID13
—
EID4
EID12
—
EID7
EID3
EID0
EID15
SID2
EID14
SID1
EID11
EID10
—
EID9
EID8
EXIDE
SID6
EID17
SID4
EID16
SID3
SID10
TXBIF
EID7
SID9
SID7
TXERR
EID4
EID12
—
SID5
TXABT
EID6
TXREQ
EID3
—
TXPRI1
EID1
TXPRI0
EID0
EID2
EID15
SID2
EID14
SID1
EID11
EID10
—
EID9
EID8
EXIDEN
SID6
EID17
SID4
EID16
SID3
SID10
EID7
SID9
SID7
EID4
EID12
—
SID5
EID6
EID3
EID2
EID1
EID0
EID15
SID2
EID14
SID1
EID11
EID10
—
EID9
EID8
EXIDEN
SID6
EID17
SID4
EID16
SID3
SID10
EID7
SID9
SID7
EID4
EID12
—
SID5
EID6
EID3
EID2
EID1
EID0
EID15
SID2
EID14
SID1
EID11
EID10
—
EID9
EID8
EXIDEN
SID6
EID17
SID4
EID16
SID3
SID10
EID7
SID9
SID7
EID4
EID12
—
SID5
EID6
EID3
EID2
EID1
EID0
EID15
SID2
EID14
SID1
EID11
EID10
—
EID9
EID8
EXIDEN
SID6
EID17
SID4
EID16
SID3
SID10
EID7
SID9
SID7
EID4
EID12
—
SID5
EID6
EID3
EID2
EID1
EID0
EID15
SID2
EID14
SID1
EID11
EID10
—
EID9
EID8
EXIDEN
SID6
EID17
SID4
EID16
SID3
SID10
EID7
SID9
SID7
EID4
EID12
—
SID5
EID6
EID3
EID2
EID1
EID0
EID15
SID2
EID14
SID1
EID11
EID10
—
EID9
EID8
EXIDEN
SID6
EID17
SID4
EID16
SID3
SID10
EID7
SID9
SID7
EID4
EID12
SID5
EID6
EID3
EID2
EID1
EID0
EID15
EID14
EID11
EID10
EID9
EID8
Legend: x= unknown, u= unchanged, -= unimplemented, q= value depends on condition. Shaded cells are unimplemented, read as ‘0’.
Note 1: Bit 21 of the PC is only available in Test mode and Serial Programming modes.
2: The SBOREN bit is only available when CONFIG2L<1:0> = 01; otherwise, it is disabled and reads as ‘0’. See Section 4.4 “Brown-out Reset
(BOR)”.
3: These registers and/or bits are not implemented on PIC18F2682/2685 devices and are read as ‘0’. Reset values are shown for PIC18F4682/4685
devices; individual unimplemented bits should be interpreted as ‘—’.
4: The PLLEN bit is only available in specific oscillator configurations; otherwise, it is disabled and reads as ‘0’. See Section 2.6.4 “PLL in INTOSC
Modes”.
5: The RE3 bit is only available when Master Clear Reset is disabled (CONFIG3H<7> = 0); otherwise, RE3 reads as ‘0’. This bit is read-only.
6: RA6/RA7 and their associated latch and direction bits are individually configured as port pins based on various primary oscillator modes. When
disabled, these bits read as ‘0’.
7: CAN bits have multiple functions depending on the selected mode of the CAN module.
8: This register reads all ‘0’s until the ECAN™ technology is set up in Mode 1 or Mode 2.
9: These registers and/or bits are available on PIC18F4682/4685 devices only.
© 2007 Microchip Technology Inc.
Preliminary
DS39761B-page 81
PIC18F2682/2685/4682/4685
TABLE 5-2:
REGISTER FILE SUMMARY (PIC18F2682/2685/4682/4685) (CONTINUED)
Value on
POR, BOR on page:
Details
File Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
RXF1SIDL
RXF1SIDH
RXF0EIDL
RXF0EIDH
RXF0SIDL
RXF0SIDH
B5D7(8)
B5D6(8)
B5D5(8)
B5D4(8)
B5D3(8)
SID2
SID10
EID7
SID1
SID9
SID0
SID8
—
EXIDEN
SID6
—
EID17
SID4
EID16
SID3
xxx- x-xx 56, 303
xxxx xxxx 56, 304
xxxx xxxx 56, 304
xxxx xxxx 56, 304
xxx- x-xx 56, 303
xxxx xxxx 56, 304
xxxx xxxx 56, 300
xxxx xxxx 56, 300
xxxx xxxx 56, 300
xxxx xxxx 56, 300
xxxx xxxx 56, 300
xxxx xxxx 56, 300
xxxx xxxx 56, 300
xxxx xxxx 56, 300
-xxx xxxx 56, 301
SID7
SID5
EID6
EID5
EID4
EID3
EID2
EID1
EID0
EID15
SID2
EID14
SID1
EID13
SID0
EID12
—
EID11
EXIDEN
SID6
EID10
—
EID9
EID8
EID17
SID4
EID16
SID3
SID10
B5D77
B5D67
B5D57
B5D47
B5D37
B5D27
B5D17
B5D07
—
SID9
SID8
SID7
SID5
B5D76
B5D66
B5D56
B5D46
B5D36
B5D26
B5D16
B5D06
RXRTR
B5D75
B5D65
B5D55
B5D45
B5D35
B5D25
B5D15
B5D05
RB1
B5D74
B5D64
B5D54
B5D44
B5D34
B5D24
B5D14
B5D04
RB0
B5D73
B5D63
B5D53
B5D43
B5D33
B5D23
B5D13
B5D03
DLC3
B5D72
B5D62
B5D52
B5D42
B5D32
B5D22
B5D12
B5D02
DLC2
B5D71
B5D61
B5D51
B5D41
B5D31
B5D21
B5D11
B5D01
DLC1
B5D70
B5D60
B5D50
B5D40
B5D30
B5D20
B5D10
B5D00
DLC0
B5D2(8)
B5D1(8)
B5D0(8)
B5DLC(8)
Receive mode
B5DLC(8)
—
TXRTR
—
—
DLC3
DLC2
DLC1
DLC0
-x-- xxxx 56, 302
Transmit mode
B5EIDL(8)
B5EIDH(8)
B5SIDL(8)
EID7
EID15
SID2
EID6
EID14
SID1
EID5
EID13
SID0
EID4
EID12
SRR
EID3
EID11
EXID
EID2
EID10
—
EID1
EID9
EID0
EID8
xxxx xxxx 56, 299
xxxx xxxx 56, 299
xxxx x-xx 56, 298
EID17
EID16
Receive mode
B5SIDL(8)
SID2
SID1
SID0
—
EXIDE
—
EID17
EID16
xxx- x-xx 56, 298
Transmit mode
B5SIDH(8)
B5CON(8)
SID10
SID9
SID8
SID7
SID6
SID5
SID4
SID3
xxxx x-xx 56, 297
0000 0000 56, 296
RXFUL
RXM1
RXRTRRO
FILHIT4
FILHIT3
FILHIT2
FILHIT1
FILHIT0
Receive mode
B5CON(8)
TXBIF
TXABT
TXLARB
TXERR
TXREQ
RTREN
TXPRI1
TXPRI0
0000 0000 56, 296
Transmit mode
B4D7(8)
B4D6(8)
B4D5(8)
B4D4(8)
B4D3(8)
B4D2(8)
B4D1(8)
B4D0(8)
B4D77
B4D67
B4D57
B4D47
B4D37
B4D27
B4D17
B4D07
—
B4D76
B4D66
B4D56
B4D46
B4D36
B4D26
B4D16
B4D06
RXRTR
B4D75
B4D65
B4D55
B4D45
B4D35
B4D25
B4D15
B4D05
RB1
B4D74
B4D64
B4D54
B4D44
B4D34
B4D24
B4D14
B4D04
RB0
B4D73
B4D63
B4D53
B4D43
B4D33
B4D23
B4D13
B4D03
DLC3
B4D72
B4D62
B4D52
B4D42
B4D32
B4D22
B4D12
B4D02
DLC2
B4D71
B4D61
B4D51
B4D41
B4D31
B4D21
B4D11
B4D01
DLC1
B4D70
B4D60
B4D50
B4D40
B4D30
B4D20
B4D10
B4D00
DLC0
xxxx xxxx 56, 300
xxxx xxxx 56, 300
xxxx xxxx 56, 300
xxxx xxxx 57, 300
xxxx xxxx 57, 300
xxxx xxxx 57, 300
xxxx xxxx 57, 300
xxxx xxxx 56, 300
-xxx xxxx 56, 301
B4DLC(8)
Receive mode
B4DLC(8)
—
TXRTR
—
—
DLC3
DLC2
DLC1
DLC0
-x-- xxxx 56, 302
Transmit mode
B4EIDL(8)
B4EIDH(8)
EID7
EID6
EID5
EID4
EID3
EID2
EID1
EID9
EID0
EID8
xxxx xxxx 57, 299
xxxx xxxx 57, 299
EID15
EID14
EID13
EID12
EID11
EID10
Legend: x= unknown, u= unchanged, -= unimplemented, q= value depends on condition. Shaded cells are unimplemented, read as ‘0’.
Note 1: Bit 21 of the PC is only available in Test mode and Serial Programming modes.
2: The SBOREN bit is only available when CONFIG2L<1:0> = 01; otherwise, it is disabled and reads as ‘0’. See Section 4.4 “Brown-out Reset
(BOR)”.
3: These registers and/or bits are not implemented on PIC18F2682/2685 devices and are read as ‘0’. Reset values are shown for PIC18F4682/4685
devices; individual unimplemented bits should be interpreted as ‘—’.
4: The PLLEN bit is only available in specific oscillator configurations; otherwise, it is disabled and reads as ‘0’. See Section 2.6.4 “PLL in INTOSC
Modes”.
5: The RE3 bit is only available when Master Clear Reset is disabled (CONFIG3H<7> = 0); otherwise, RE3 reads as ‘0’. This bit is read-only.
6: RA6/RA7 and their associated latch and direction bits are individually configured as port pins based on various primary oscillator modes. When
disabled, these bits read as ‘0’.
7: CAN bits have multiple functions depending on the selected mode of the CAN module.
8: This register reads all ‘0’s until the ECAN™ technology is set up in Mode 1 or Mode 2.
9: These registers and/or bits are available on PIC18F4682/4685 devices only.
DS39761B-page 82
Preliminary
© 2007 Microchip Technology Inc.
PIC18F2682/2685/4682/4685
TABLE 5-2:
REGISTER FILE SUMMARY (PIC18F2682/2685/4682/4685) (CONTINUED)
Value on
POR, BOR on page:
Details
File Name
Bit 7
SID2
SID2
Bit 6
SID1
SID1
Bit 5
SID0
SID0
Bit 4
SRR
—
Bit 3
Bit 2
Bit 1
EID17
EID17
Bit 0
EID16
EID16
B4SIDL(8)
Receive mode
B4SIDL(8)
EXID
—
xxxx x-xx
56, 298
EXIDE
—
xxx- x-xx 56, 298
Transmit mode
B4SIDH(8)
B4CON(8)
SID10
SID9
SID8
SID7
SID6
SID5
SID4
SID3
xxxx xxxx 57, 297
0000 0000 57, 296
RXFUL
RXM1
RXRTRRO
FILHIT4
FILHIT3
FILHIT2
FILHIT1
FILHIT0
Receive mode
B4CON(8)
TXBIF
TXABT
TXLARB
TXERR
TXREQ
RTREN
TXPRI1
TXPRI0
0000 0000 57, 296
Transmit mode
B3D7(8)
B3D6(8)
B3D5(8)
B3D4(8)
B3D3(8)
B3D2(8)
B3D1(8)
B3D0(8)
B3D77
B3D67
B3D57
B3D47
B3D37
B3D27
B3D17
B3D07
—
B3D76
B3D66
B3D56
B3D46
B3D36
B3D26
B3D16
B3D06
RXRTR
B3D75
B3D65
B3D55
B3D45
B3D35
B3D25
B3D15
B3D05
RB1
B3D74
B3D64
B3D54
B3D44
B3D34
B3D24
B3D14
B3D04
RB0
B3D73
B3D63
B3D53
B3D43
B3D33
B3D23
B3D13
B3D03
DLC3
B3D72
B3D62
B3D52
B3D42
B3D32
B3D22
B3D12
B3D02
DLC2
B3D71
B3D61
B3D51
B3D41
B3D31
B3D21
B3D11
B3D01
DLC1
B3D70
B3D60
B3D50
B3D40
B3D30
B3D20
B3D10
B3D00
DLC0
xxxx xxxx 57, 300
xxxx xxxx 57, 300
xxxx xxxx 57, 300
xxxx xxxx 57, 300
xxxx xxxx 57, 300
xxxx xxxx 57, 300
xxxx xxxx 57, 300
xxxx xxxx 57, 300
-xxx xxxx 56, 301
B3DLC(8)
Receive mode
B3DLC(8)
—
TXRTR
—
—
DLC3
DLC2
DLC1
DLC0
-x-- xxxx 56, 302
Transmit mode
B3EIDL(8)
B3EIDH(8)
B3SIDL(8)
EID7
EID15
SID2
EID6
EID14
SID1
EID5
EID13
SID0
EID4
EID12
SRR
EID3
EID11
EXID
EID2
EID10
—
EID1
EID9
EID0
EID8
xxxx xxxx 57, 299
xxxx xxxx 57, 299
xxxx x-xx 56, 298
EID17
EID16
Receive mode
B3SIDL(8)
SID2
SID1
SID0
—
EXIDE
—
EID17
EID16
xxx- x-xx 56, 298
Transmit mode
B3SIDH(8)
B3CON(8)
SID10
SID9
SID8
SID7
SID6
SID5
SID4
SID3
xxxx xxxx 57, 297
0000 0000 57, 296
RXFUL
RXM1
RXRTRRO
FILHIT4
FILHIT3
FILHIT2
FILHIT1
FILHIT0
Receive mode
B3CON(8)
TXBIF
TXABT
TXLARB
TXERR
TXREQ
RTREN
TXPRI1
TXPRI0
0000 0000 57, 296
Transmit mode
B2D7(8)
B2D6(8)
B2D5(8)
B2D4(8)
B2D3(8)
B2D2(8)
B2D1(8)
B2D0(8)
B2D77
B2D67
B2D57
B2D47
B2D37
B2D27
B2D17
B2D07
—
B2D76
B2D66
B2D56
B2D46
B2D36
B2D26
B2D16
B2D06
RXRTR
B2D75
B2D65
B2D55
B2D45
B2D35
B2D25
B2D15
B2D05
RB1
B2D74
B2D64
B2D54
B2D44
B2D34
B2D24
B2D14
B2D04
RB0
B2D73
B2D63
B2D53
B2D43
B2D33
B2D23
B2D13
B2D03
DLC3
B2D72
B2D62
B2D52
B2D42
B2D32
B2D22
B2D12
B2D02
DLC2
B2D71
B2D61
B2D51
B2D41
B2D31
B2D21
B2D11
B2D01
DLC1
B2D70
B2D60
B2D50
B2D40
B2D30
B2D20
B2D10
B2D00
DLC0
xxxx xxxx 57, 300
xxxx xxxx 57, 300
xxxx xxxx 57, 300
xxxx xxxx 57, 300
xxxx xxxx 57, 300
xxxx xxxx 57, 300
xxxx xxxx 58, 300
xxxx xxxx 58, 300
-xxx xxxx 56, 301
B2DLC(8)
Receive mode
B2DLC(8)
—
TXRTR
—
—
DLC3
DLC2
DLC1
DLC0
-x-- xxxx 56, 302
Transmit mode
Legend: x= unknown, u= unchanged, -= unimplemented, q= value depends on condition. Shaded cells are unimplemented, read as ‘0’.
Note 1: Bit 21 of the PC is only available in Test mode and Serial Programming modes.
2: The SBOREN bit is only available when CONFIG2L<1:0> = 01; otherwise, it is disabled and reads as ‘0’. See Section 4.4 “Brown-out Reset
(BOR)”.
3: These registers and/or bits are not implemented on PIC18F2682/2685 devices and are read as ‘0’. Reset values are shown for PIC18F4682/4685
devices; individual unimplemented bits should be interpreted as ‘—’.
4: The PLLEN bit is only available in specific oscillator configurations; otherwise, it is disabled and reads as ‘0’. See Section 2.6.4 “PLL in INTOSC
Modes”.
5: The RE3 bit is only available when Master Clear Reset is disabled (CONFIG3H<7> = 0); otherwise, RE3 reads as ‘0’. This bit is read-only.
6: RA6/RA7 and their associated latch and direction bits are individually configured as port pins based on various primary oscillator modes. When
disabled, these bits read as ‘0’.
7: CAN bits have multiple functions depending on the selected mode of the CAN module.
8: This register reads all ‘0’s until the ECAN™ technology is set up in Mode 1 or Mode 2.
9: These registers and/or bits are available on PIC18F4682/4685 devices only.
© 2007 Microchip Technology Inc.
Preliminary
DS39761B-page 83
PIC18F2682/2685/4682/4685
TABLE 5-2:
REGISTER FILE SUMMARY (PIC18F2682/2685/4682/4685) (CONTINUED)
Value on
POR, BOR on page:
Details
File Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
B2EIDL(8)
B2EIDH(8)
B2SIDL(8)
EID7
EID15
SID2
EID6
EID14
SID1
EID5
EID13
SID0
EID4
EID12
SRR
EID3
EID11
EXID
EID2
EID10
—
EID1
EID9
EID0
EID8
xxxx xxxx 58, 299
xxxx xxxx 58, 299
xxxx x-xx 56, 298
EID17
EID16
Receive mode
B2SIDL(8)
SID2
SID1
SID0
—
EXIDE
—
EID17
EID16
xxx- x-xx 56, 298
Transmit mode
B2SIDH(8)
B2CON(8)
SID10
SID9
SID8
SID7
SID6
SID5
SID4
SID3
xxxx xxxx 58, 297
0000 0000 58, 296
RXFUL
RXM1
RXRTRRO
FILHIT4
FILHIT3
FILHIT2
FILHIT1
FILHIT0
Receive mode
B2CON(8)
TXBIF
RXM1
TXLARB
TXERR
TXREQ
RTREN
TXPRI1
TXPRI0
0000 0000 58, 296
Transmit mode
B1D7(8)
B1D6(8)
B1D5(8)
B1D4(8)
B1D3(8)
B1D2(8)
B1D1(8)
B1D0(8)
B1D77
B1D67
B1D57
B1D47
B1D37
B1D27
B1D17
B1D07
—
B1D76
B1D66
B1D56
B1D46
B1D36
B1D26
B1D16
B1D06
RXRTR
B1D75
B1D65
B1D55
B1D45
B1D35
B1D25
B1D15
B1D05
RB1
B1D74
B1D64
B1D54
B1D44
B1D34
B1D24
B1D14
B1D04
RB0
B1D73
B1D63
B1D53
B1D43
B1D33
B1D23
B1D13
B1D03
DLC3
B1D72
B1D62
B1D52
B1D42
B1D32
B1D22
B1D12
B1D02
DLC2
B1D71
B1D61
B1D51
B1D41
B1D31
B1D21
B1D11
B1D01
DLC1
B1D70
B1D60
B1D50
B1D40
B1D30
B1D20
B1D10
B1D00
DLC0
xxxx xxxx 58, 300
xxxx xxxx 58, 300
xxxx xxxx 58, 300
xxxx xxxx 58, 300
xxxx xxxx 58, 300
xxxx xxxx 58, 300
xxxx xxxx 58, 300
xxxx xxxx 58, 300
-xxx xxxx 56, 301
B1DLC(8)
Receive mode
B1DLC(8)
—
TXRTR
—
—
DLC3
DLC2
DLC1
DLC0
-x-- xxxx 56, 302
Transmit mode
B1EIDL(8)
B1EIDH(8)
B1SIDL(8)
EID7
EID15
SID2
EID6
EID14
SID1
EID5
EID13
SID0
EID4
EID12
SRR
EID3
EID11
EXID
EID2
EID10
—
EID1
EID9
EID0
EID8
xxxx xxxx 58, 299
xxxx xxxx 58, 299
xxxx x-xx 56, 298
EID17
EID16
Receive mode
B1SIDL(8)
SID2
SID1
SID0
—
EXIDE
—
EID17
EID16
xxx- x-xx 56, 298
Transmit mode
B1SIDH(8)
B1CON(8)
SID10
SID9
SID8
SID7
SID6
SID5
SID4
SID3
xxxx xxxx 58, 297
0000 0000 58, 296
RXFUL
RXM1
RXRTRRO
FILHIT4
FILHIT3
FILHIT2
FILHIT1
FILHIT0
Receive mode
B1CON(8)
TXBIF
TXABT
TXLARB
TXERR
TXREQ
RTREN
TXPRI1
TXPRI0
0000 0000 58, 296
Transmit mode
B0D7(8)
B0D6(8)
B0D5(8)
B0D4(8)
B0D3(8)
B0D2(8)
B0D1(8)
B0D0(8)
B0D77
B0D67
B0D57
B0D47
B0D37
B0D27
B0D17
B0D07
—
B0D76
B0D66
B0D56
B0D46
B0D36
B0D26
B0D16
B0D06
RXRTR
B0D75
B0D65
B0D55
B0D45
B0D35
B0D25
B0D15
B0D05
RB1
B0D74
B0D64
B0D54
B0D44
B0D34
B0D24
B0D14
B0D04
RB0
B0D73
B0D63
B0D53
B0D43
B0D33
B0D23
B0D13
B0D03
DLC3
B0D72
B0D62
B0D52
B0D42
B0D32
B0D22
B0D12
B0D02
DLC2
B0D71
B0D61
B0D51
B0D41
B0D31
B0D21
B0D11
B0D01
DLC1
B0D70
B0D60
B0D50
B0D40
B0D30
B0D20
B0D10
B0D00
DLC0
xxxx xxxx 58, 300
xxxx xxxx 58, 300
xxxx xxxx 58, 300
xxxx xxxx 58, 300
xxxx xxxx 58, 300
xxxx xxxx 58, 300
xxxx xxxx 58, 300
xxxx xxxx 58, 300
-xxx xxxx 56, 301
B0DLC(8)
Receive mode
Legend: x= unknown, u= unchanged, -= unimplemented, q= value depends on condition. Shaded cells are unimplemented, read as ‘0’.
Note 1: Bit 21 of the PC is only available in Test mode and Serial Programming modes.
2: The SBOREN bit is only available when CONFIG2L<1:0> = 01; otherwise, it is disabled and reads as ‘0’. See Section 4.4 “Brown-out Reset
(BOR)”.
3: These registers and/or bits are not implemented on PIC18F2682/2685 devices and are read as ‘0’. Reset values are shown for PIC18F4682/4685
devices; individual unimplemented bits should be interpreted as ‘—’.
4: The PLLEN bit is only available in specific oscillator configurations; otherwise, it is disabled and reads as ‘0’. See Section 2.6.4 “PLL in INTOSC
Modes”.
5: The RE3 bit is only available when Master Clear Reset is disabled (CONFIG3H<7> = 0); otherwise, RE3 reads as ‘0’. This bit is read-only.
6: RA6/RA7 and their associated latch and direction bits are individually configured as port pins based on various primary oscillator modes. When
disabled, these bits read as ‘0’.
7: CAN bits have multiple functions depending on the selected mode of the CAN module.
8: This register reads all ‘0’s until the ECAN™ technology is set up in Mode 1 or Mode 2.
9: These registers and/or bits are available on PIC18F4682/4685 devices only.
DS39761B-page 84
Preliminary
© 2007 Microchip Technology Inc.
PIC18F2682/2685/4682/4685
TABLE 5-2:
REGISTER FILE SUMMARY (PIC18F2682/2685/4682/4685) (CONTINUED)
Value on
POR, BOR on page:
Details
File Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
B0DLC(8)
—
TXRTR
—
—
DLC3
DLC2
DLC1
DLC0
-x-- xxxx 56, 302
Transmit mode
B0EIDL(8)
B0EIDH(8)
B0SIDL(8)
EID7
EID15
SID2
EID6
EID14
SID1
EID5
EID13
SID0
EID4
EID12
SRR
EID3
EID11
EXID
EID2
EID10
—
EID1
EID9
EID0
EID8
xxxx xxxx 59, 299
xxxx xxxx 59, 299
xxxx x-xx 56, 298
EID17
EID16
Receive mode
B0SIDL(8)
SID2
SID1
SID0
—
EXIDE
—
EID17
EID16
xxx- x-xx 56, 298
Transmit mode
B0SIDH(8)
B0CON(8)
SID10
SID9
SID8
SID7
SID6
SID5
SID4
SID3
xxxx xxxx 59, 297
0000 0000 58, 296
RXFUL
RXM1
RXRTRRO
FILHIT4
FILHIT3
FILHIT2
FILHIT1
FILHIT0
Receive mode
B0CON(8)
TXBIF
TXABT
TXLARB
TXERR
TXREQ
RTREN
TXPRI1
TXPRI0
0000 0000 58, 296
Transmit mode
TXBIE
—
—
—
TXB2IE
B2IE
TXB1IE
B1IE
TXB0IE
B0IE
—
—
---0 00-- 59, 319
0000 0000 59, 319
0000 00-- 59, 302
0000 0000 59, 311
0000 0000 59, 310
0000 0101 59, 309
0101 0000 59, 308
0000 0000 59, 307
0000 0000 59, 307
0000 0000 59, 307
0000 0000 59, 307
0000 0000 59, 307
0001 0001 59, 307
0001 0001 59, 307
0000 0000 59, 307
---0 0000 59, 306
0000 0000 59, 306
0000 0000 59, 306
xxxx xxxx 59, 304
xxxx xxxx 59, 304
xxx- x-xx 59, 303
xxxx xxxx 59, 303
xxxx xxxx 59, 304
xxxx xxxx 59, 304
xxx- x-xx 59, 303
xxxx xxxx 59, 303
xxxx xxxx 60, 304
xxxx xxxx 60, 304
xxx- x-xx 60, 303
xxxx xxxx 60, 303
BIE0
B5IE
B4IE
B3IE
RXB1IE
—
RXB0IE
—
BSEL0
B5TXEN
FIL15_1
FIL11_1
FIL7_1
FIL3_1
F15BP_3
F13BP_3
F11BP_3
F9BP_3
F7BP_3
F5BP_3
F3BP_3
F1BP_3
—
B4TXEN
FIL15_0
FIL11_0
FIL7_0
FIL3_0
F15BP_2
F13BP_2
F11BP_2
F9BP_2
F7BP_2
F5BP_2
F3BP_2
F1BP_2
—
B3TXEN
FIL14_1
FIL10_1
FIL6_1
FIL2_1
F15BP_1
F13BP_1
F11BP_1
F9BP_1
F7BP_1
F5BP_1
F3BP_1
F1BP_1
—
B2TXEN
FIL14_0
FIL10_0
FIL6_0
B1TXEN
FIL13_1
FIL9_1
FIL5_1
FIL1_1
F14BP_3
F12BP_3
F10BP_3
F8BP_3
F6BP_3
F4BP_3
F2BP_3
F0BP_3
FLC3
B0TXEN
FIL13_0
FIL9_0
FIL5_0
FIL1_0
F14BP_2
F12BP_2
F10BP_2
F8BP_2
F6BP_2
F4BP_2
F2BP_2
F0BP_2
FLC2
MSEL3
FIL12_1
FIL8_1
FIL4_1
FIL0_1
F14BP_1
F12BP_1
F10BP_1
F8BP_1
F6BP_1
F4BP_1
F2BP_1
F0BP_1
FLC1
FIL12_0
FIL8_0
FIL4_0
FIL0_0
F14BP_0
F12BP_0
F10BP_0
F8BP_0
F6BP_0
F4BP_0
F2BP_0
F0BP_0
FLC0
MSEL2
MSEL1
MSEL0
FIL2_0
RXFBCON7
RXFBCON6
RXFBCON5
RXFBCON4
RXFBCON3
RXFBCON2
RXFBCON1
RXFBCON0
SDFLC
F15BP_0
F13BP_0
F11BP_0
F9BP_0
F7BP_0
F5BP_0
F3BP_0
F1BP_0
FLC4
RXFCON1
RXFCON0
RXF15EIDL
RXF15EIDH
RXF15SIDL
RXF15SIDH
RXF14EIDL
RXF14EIDH
RXF14SIDL
RXF14SIDH
RXF13EIDL
RXF13EIDH
RXF13SIDL
RXF13SIDH
RXF15EN
RXF7EN
EID7
RXF14EN RXF13EN RXF12EN
RXF11EN
RXF3EN
EID3
RXF10EN
RXF2EN
EID2
RXF9EN
RXF1EN
EID1
RXF8EN
RXF0EN
EID0
RXF6EN
EID6
RXF5EN
EID5
RXF4EN
EID4
EID12
—
EID15
EID14
SID1
EID13
SID0
EID11
EID10
—
EID9
EID8
SID2
EXIDEN
SID6
EID17
SID4
EID16
SID3
SID10
SID9
SID8
SID7
EID4
EID12
—
SID5
EID7
EID6
EID5
EID3
EID2
EID1
EID0
EID15
EID14
SID1
EID13
SID0
EID11
EID10
—
EID9
EID8
SID2
EXIDEN
SID6
EID17
SID4
EID16
SID3
SID10
SID9
SID8
SID7
EID4
EID12
—
SID5
EID7
EID6
EID5
EID3
EID2
EID1
EID0
EID15
EID14
SID1
EID13
SID0
EID11
EID10
—
EID9
EID8
SID2
EXIDEN
SID6
EID17
SID4
EID16
SID3
SID10
SID9
SID8
SID7
SID5
Legend: x= unknown, u= unchanged, -= unimplemented, q= value depends on condition. Shaded cells are unimplemented, read as ‘0’.
Note 1: Bit 21 of the PC is only available in Test mode and Serial Programming modes.
2: The SBOREN bit is only available when CONFIG2L<1:0> = 01; otherwise, it is disabled and reads as ‘0’. See Section 4.4 “Brown-out Reset
(BOR)”.
3: These registers and/or bits are not implemented on PIC18F2682/2685 devices and are read as ‘0’. Reset values are shown for PIC18F4682/4685
devices; individual unimplemented bits should be interpreted as ‘—’.
4: The PLLEN bit is only available in specific oscillator configurations; otherwise, it is disabled and reads as ‘0’. See Section 2.6.4 “PLL in INTOSC
Modes”.
5: The RE3 bit is only available when Master Clear Reset is disabled (CONFIG3H<7> = 0); otherwise, RE3 reads as ‘0’. This bit is read-only.
6: RA6/RA7 and their associated latch and direction bits are individually configured as port pins based on various primary oscillator modes. When
disabled, these bits read as ‘0’.
7: CAN bits have multiple functions depending on the selected mode of the CAN module.
8: This register reads all ‘0’s until the ECAN™ technology is set up in Mode 1 or Mode 2.
9: These registers and/or bits are available on PIC18F4682/4685 devices only.
© 2007 Microchip Technology Inc.
Preliminary
DS39761B-page 85
PIC18F2682/2685/4682/4685
TABLE 5-2:
REGISTER FILE SUMMARY (PIC18F2682/2685/4682/4685) (CONTINUED)
Value on
POR, BOR on page:
Details
File Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
RXF12EIDL
RXF12EIDH
RXF12SIDL
RXF12SIDH
RXF11EIDL
RXF11EIDH
RXF11SIDL
RXF11SIDH
RXF10EIDL
RXF10EIDH
RXF10SIDL
RXF10SIDH
RXF9EIDL
RXF9EIDH
RXF9SIDL
RXF9SIDH
RXF8EIDL
RXF8EIDH
RXF8SIDL
RXF8SIDH
RXF7EIDL
RXF7EIDH
RXF7SIDL
RXF7SIDH
RXF6EIDL
RXF6EIDH
RXF6SIDL
RXF6SIDH
EID7
EID15
SID2
EID6
EID14
SID1
SID9
EID6
EID14
SID1
SID9
EID6
EID14
SID1
SID9
EID6
EID14
SID1
SID9
EID6
EID14
SID1
SID9
EID6
EID14
SID1
SID9
EID6
EID14
SID1
SID9
EID5
EID13
SID0
SID8
EID5
EID13
SID0
SID8
EID5
EID13
SID0
SID8
EID5
EID13
SID0
SID8
EID5
EID13
SID0
SID8
EID5
EID13
SID0
SID8
EID5
EID13
SID0
SID8
EID4
EID12
—
EID3
EID11
EXIDEN
SID6
EID2
EID10
—
EID1
EID9
EID17
SID4
EID1
EID9
EID17
SID4
EID1
EID9
EID17
SID4
EID1
EID9
EID17
SID4
EID1
EID9
EID17
SID4
EID1
EID9
EID17
SID4
EID1
EID9
EID17
SID4
EID0
EID8
EID16
SID3
EID0
EID8
EID16
SID3
EID0
EID8
EID16
SID3
EID0
EID8
EID16
SID3
EID0
EID8
EID16
SID3
EID0
EID8
EID16
SID3
EID0
EID8
EID16
SID3
xxxx xxxx 60, 304
xxxx xxxx 60, 304
xxx- x-xx 60, 303
xxxx xxxx 60, 303
xxxx xxxx 60, 304
xxxx xxxx 60, 304
xxx- x-xx 60, 303
xxxx xxxx 60, 303
xxxx xxxx 60, 304
xxxx xxxx 60, 304
xxx- x-xx 60, 303
xxxx xxxx 60, 303
xxxx xxxx 60, 304
xxxx xxxx 60, 304
xxx- x-xx 60, 303
xxxx xxxx 60, 303
xxxx xxxx 60, 304
xxxx xxxx 60, 304
xxx- x-xx 60, 303
xxxx xxxx 60, 303
xxxx xxxx 60, 304
xxxx xxxx 60, 304
xxx- x-xx 60, 303
xxxx xxxx 60, 303
xxxx xxxx 60, 304
xxxx xxxx 60, 304
xxx- x-xx 60, 303
xxxx xxxx 60, 303
SID10
EID7
SID7
EID4
EID12
—
SID5
EID2
EID10
—
EID3
EID15
SID2
EID11
EXIDEN
SID6
SID10
EID7
SID7
EID4
EID12
—
SID5
EID2
EID10
—
EID3
EID15
SID2
EID11
EXIDEN
SID6
SID10
EID7
SID7
EID4
EID12
—
SID5
EID2
EID10
—
EID3
EID15
SID2
EID11
EXIDEN
SID6
SID10
EID7
SID7
EID4
EID12
—
SID5
EID2
EID10
—
EID3
EID15
SID2
EID11
EXIDEN
SID6
SID10
EID7
SID7
EID4
EID12
—
SID5
EID2
EID10
—
EID3
EID15
SID2
EID11
EXIDEN
SID6
SID10
EID7
SID7
EID4
EID12
—
SID5
EID2
EID10
—
EID3
EID15
SID2
EID11
EXIDEN
SID6
SID10
SID7
SID5
Legend: x= unknown, u= unchanged, -= unimplemented, q= value depends on condition. Shaded cells are unimplemented, read as ‘0’.
Note 1: Bit 21 of the PC is only available in Test mode and Serial Programming modes.
2: The SBOREN bit is only available when CONFIG2L<1:0> = 01; otherwise, it is disabled and reads as ‘0’. See Section 4.4 “Brown-out Reset
(BOR)”.
3: These registers and/or bits are not implemented on PIC18F2682/2685 devices and are read as ‘0’. Reset values are shown for PIC18F4682/4685
devices; individual unimplemented bits should be interpreted as ‘—’.
4: The PLLEN bit is only available in specific oscillator configurations; otherwise, it is disabled and reads as ‘0’. See Section 2.6.4 “PLL in INTOSC
Modes”.
5: The RE3 bit is only available when Master Clear Reset is disabled (CONFIG3H<7> = 0); otherwise, RE3 reads as ‘0’. This bit is read-only.
6: RA6/RA7 and their associated latch and direction bits are individually configured as port pins based on various primary oscillator modes. When
disabled, these bits read as ‘0’.
7: CAN bits have multiple functions depending on the selected mode of the CAN module.
8: This register reads all ‘0’s until the ECAN™ technology is set up in Mode 1 or Mode 2.
9: These registers and/or bits are available on PIC18F4682/4685 devices only.
DS39761B-page 86
Preliminary
© 2007 Microchip Technology Inc.
PIC18F2682/2685/4682/4685
It is recommended that only BCF, BSF, SWAPF, MOVFF
and MOVWFinstructions are used to alter the STATUS
register, because these instructions do not affect the Z,
C, DC, OV or N bits in the STATUS register.
5.3.5
STATUS REGISTER
The STATUS register, shown in Register 5-2, contains
the arithmetic status of the ALU. As with any other SFR,
it can be the operand for any instruction.
For other instructions that do not affect Status bits, see
the instruction set summaries in Table 25-2 and
Table 25-3.
If the STATUS register is the destination for an instruc-
tion that affects the Z, DC, C, OV or N bits, the results
of the instruction are not written; instead, the status is
updated according to the instruction performed. There-
fore, the result of an instruction with the STATUS
register as its destination may be different than
intended. As an example, CLRFSTATUSwill set the Z
bit and leave the remaining Status bits unchanged
(‘000u u1uu’).
Note:
The C and DC bits operate as the borrow
and digit borrow bits respectively in
subtraction.
REGISTER 5-2:
STATUS REGISTER
U-0
—
U-0
U-0
—
R/W-x
N
R/W-x
OV
R/W-x
Z
R/W-x
DC(1)
R/W-x
C(2)
—
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7-5
bit 4
Unimplemented: Read as ‘0’
N: Negative bit
This bit is used for signed arithmetic (2’s complement). It indicates whether the result was negative
(ALU MSB = 1).
1= Result was negative
0= Result was positive
bit 3
OV: Overflow bit
This bit is used for signed arithmetic (2’s complement). It indicates an overflow of the 7-bit magnitude
which causes the sign bit (bit 7 of the result) to change state.
1= Overflow occurred for signed arithmetic (in this arithmetic operation)
0= No overflow occurred
bit 2
bit 1
Z: Zero bit
1= The result of an arithmetic or logic operation is zero
0= The result of an arithmetic or logic operation is not zero
DC: Digit Carry/Borrow bit(1)
For ADDWF, ADDLW, SUBLWand SUBWFinstructions:
1= A carry-out from the 4th low-order bit of the result occurred
0= No carry-out from the 4th low-order bit of the result
bit 0
C: Carry/Borrow bit(2)
For ADDWF, ADDLW, SUBLWand SUBWFinstructions:
1= A carry-out from the Most Significant bit of the result occurred
0= No carry-out from the Most Significant bit of the result occurred
Note 1: For Borrow, the polarity is reversed. A subtraction is executed by adding the 2’s complement of the second
operand. For rotate (RRF, RLF) instructions, this bit is loaded with either bit 4 or bit 3 of the source register.
2: For Borrow, the polarity is reversed. A subtraction is executed by adding the 2’s complement of the second
operand. For rotate (RRF, RLF) instructions, this bit is loaded with either the high or low-order bit of the
source register.
© 2007 Microchip Technology Inc.
Preliminary
DS39761B-page 87
PIC18F2682/2685/4682/4685
Purpose Register File”) or a location in the Access
Bank (Section 5.3.2 “Access Bank”) as the data
source for the instruction.
5.4
Data Addressing Modes
Note:
The execution of some instructions in the
core PIC18 instruction set are changed
when the PIC18 extended instruction
set is enabled. See Section 5.6 “Data
Memory and the Extended Instruction
Set” for more information.
The Access RAM bit ‘a’ determines how the address is
interpreted. When ‘a’ is ‘1’, the contents of the BSR
(Section 5.3.1 “Bank Select Register (BSR)”) are
used with the address to determine the complete 12-bit
address of the register. When ‘a’ is ‘0’, the address is
interpreted as being a register in the Access Bank.
Addressing that uses the Access RAM is sometimes
also known as Direct Forced Addressing mode.
While the program memory can be addressed in only
one way – through the program counter – information
in the data memory space can be addressed in several
ways. For most instructions, the addressing mode is
fixed. Other instructions may use up to three modes,
depending on which operands are used and whether or
not the extended instruction set is enabled.
A few instructions, such as MOVFF, include the entire
12-bit address (either source or destination) in their
opcodes. In those cases, the BSR is ignored entirely.
The destination of the operation’s results is determined
by the destination bit ‘d’. When ‘d’ is ‘1’, the results are
stored back in the source register, overwriting its origi-
nal contents. When ‘d’ is ‘0’, the results are stored in
the W register. Instructions without the ‘d’ argument
have a destination that is implicit in the instruction.
Their destination is either the target register being
operated on or the W register.
The addressing modes are:
• Inherent
• Literal
• Direct
• Indirect
An additional addressing mode, Indexed Literal Offset,
is available when the extended instruction set is
enabled (XINST Configuration bit = 1). Its operation is
discussed in greater detail in Section 5.6.1 “Indexed
Addressing with Literal Offset”.
5.4.3
INDIRECT ADDRESSING
Indirect Addressing allows the user to access a location
in data memory without giving a fixed address in the
instruction. This is done by using File Select Registers
(FSRs) as pointers to the locations to be read or written
to. Since the FSRs are themselves located in RAM as
Special Function Registers, they can also be directly
manipulated under program control. This makes FSRs
very useful in implementing data structures, such as
tables and arrays in data memory.
5.4.1
INHERENT AND LITERAL
ADDRESSING
Many PIC18 control instructions do not need any
argument at all. They either perform an operation that
globally affects the device or they operate implicitly on
one register. This addressing mode is known as
Inherent Addressing. Examples include SLEEP, RESET
and DAW.
The registers for Indirect Addressing are also
implemented with Indirect File Operands (INDFs) that
permit automatic manipulation of the pointer value with
auto-incrementing, auto-decrementing or offsetting
with another value. This allows for efficient code, using
loops, such as the example of clearing an entire RAM
bank in Example 5-5.
Other instructions work in a similar way but require an
additional explicit argument in the opcode. This is
known as Literal Addressing mode because they
require some literal value as an argument. Examples
include ADDLWand MOVLWwhich, respectively, add or
move a literal value to the W register. Other examples
include CALL and GOTO, which include a 20-bit
program memory address.
EXAMPLE 5-5:
HOW TO CLEAR RAM
(BANK 1) USING
INDIRECT ADDRESSING
5.4.2
DIRECT ADDRESSING
LFSR FSR0, 100h
CLRF POSTINC0
;
Direct Addressing mode specifies all or part of the
source and/or destination address of the operation
within the opcode itself. The options are specified by
the arguments accompanying the instruction.
NEXT
; Clear INDF
; register then
; inc pointer
; All done with
; Bank1?
BTFSS FSR0H, 1
In the core PIC18 instruction set, bit-oriented and byte-
oriented instructions use some version of Direct
Addressing by default. All of these instructions include
some 8-bit literal address as their Least Significant
Byte. This address specifies either a register address in
one of the banks of data RAM (Section 5.3.3 “General
BRA
CONTINUE
NEXT
; NO, clear next
; YES, continue
DS39761B-page 88
Preliminary
© 2007 Microchip Technology Inc.
PIC18F2682/2685/4682/4685
mapped in the SFR space, but are not physically
implemented. Reading or writing to a particular INDF
register actually accesses its corresponding FSR
register pair. A read from INDF1, for example, reads
the data at the address indicated by FSR1H:FSR1L.
Instructions that use the INDF registers as operands
actually use the contents of their corresponding FSR as
a pointer to the instruction’s target. The INDF operand
is just a convenient way of using the pointer.
5.4.3.1
FSR Registers and the
INDF Operand
At the core of Indirect Addressing are three sets of
registers: FSR0, FSR1 and FSR2. Each represents a
pair of 8-bit registers: FSRnH and FSRnL. The four
upper bits of the FSRnH register are not used, so each
FSR pair holds a 12-bit value. This represents a value
that can address the entire range of the data memory
in a linear fashion. The FSR register pairs, then, serve
as pointers to data memory locations.
Because Indirect Addressing uses a full 12-bit address,
data RAM banking is not necessary. Thus, the current
contents of the BSR and Access RAM bit have no effect
on determining the target address.
Indirect Addressing is accomplished with a set of
Indirect File Operands: INDF0 through INDF2. These
can be thought of as “virtual” registers: they are
FIGURE 5-7:
INDIRECT ADDRESSING
000h
Using an instruction with one of the
Indirect Addressing registers as the
operand....
Bank 0
Bank 1
Bank 2
ADDWF, INDF1, 1
100h
200h
300h
FSR1H:FSR1L
...uses the 12-bit address stored in
the FSR pair associated with that
register....
7
0
7
0
x x x x 1 1 1 0
1 1 0 0 1 1 0 0
Bank 3
through
Bank 13
...to determine the data memory
location to be used in that operation.
E00h
In this case, the FSR1 pair contains
ECCh. This means the contents of
location ECCh will be added to that
of the W register and stored back in
ECCh.
Bank 14
F00h
FFFh
Bank 15
Data Memory
© 2007 Microchip Technology Inc.
Preliminary
DS39761B-page 89
PIC18F2682/2685/4682/4685
5.4.3.2
FSR Registers and POSTINC,
5.4.3.3
Operations by FSRs on FSRs
POSTDEC, PREINC and PLUSW
Indirect Addressing operations that target other FSRs
or virtual registers represent special cases. For exam-
ple, using an FSR to point to one of the virtual registers
will not result in successful operations. As a specific
case, assume that the FSR0H:FSR0L pair contains
FE7h, the address of INDF1. Attempts to read the
value of the INDF1 using INDF0 as an operand will
return 00h. Attempts to write to INDF1 using INDF0 as
the operand will result in a NOP.
In addition to the INDF operand, each FSR register pair
also has four additional indirect operands. Like INDF,
these are “virtual” registers that cannot be indirectly
read or written to. Accessing these registers actually
accesses the associated FSR register pair, but also
performs a specific action on its stored value. They are:
• POSTDEC: accesses the FSR value, then
automatically decrements it by 1 afterwards
On the other hand, using the virtual registers to write to
an FSR pair may not occur as planned. In these cases,
the value will be written to the FSR pair but without any
incrementing or decrementing. Thus, writing to INDF2
or POSTDEC2 will write the same value to the
FSR2H:FSR2L pair.
• POSTINC: accesses the FSR value, then
automatically increments it by 1 afterwards
• PREINC: increments the FSR value by 1, then
uses it in the operation
• PLUSW: adds the signed value of the W register
(range of -127 to 128) to that of the FSR and uses
the new value in the operation.
Since the FSRs are physical registers mapped in the
SFR space, they can be manipulated through all direct
operations. Users should proceed cautiously when
working on these registers, particularly if their code
uses Indirect Addressing.
In this context, accessing an INDF register uses the
value in the FSR registers without changing them.
Similarly, accessing a PLUSW register gives the FSR
value offset by that in the W register; neither value is
actually changed in the operation. Accessing the other
virtual registers changes the value of the FSR
registers.
Similarly, operations by Indirect Addressing are gener-
ally permitted on all other SFRs. Users should exercise
the appropriate caution that they do not inadvertently
change settings that might affect the operation of the
device.
Operations on the FSRs with POSTDEC, POSTINC
and PREINC affect the entire register pair; that is,
rollovers of the FSRnL register from FFh to 00h carry
over to the FSRnH register. On the other hand, results
of these operations do not change the value of any
flags in the STATUS register (e.g., Z, N, OV, etc.).
The PLUSW register can be used to implement a form
of Indexed Addressing in the data memory space. By
manipulating the value in the W register, users can
reach addresses that are fixed offsets from pointer
addresses. In some applications, this can be used to
implement some powerful program control structure,
such as software stacks, inside of data memory.
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When using the extended instruction set, this
addressing mode requires the following:
5.5
Program Memory and the
Extended Instruction Set
• The use of the Access Bank is forced (‘a’ = 0);
and
The operation of program memory is unaffected by the
use of the extended instruction set.
• The file address argument is less than or equal to
5Fh.
Enabling the extended instruction set adds eight
additional two-word commands to the existing
PIC18 instruction set: ADDFSR, ADDULNK, CALLW,
MOVSF, MOVSS, PUSHL, SUBFSRand SUBULNK.These
instructions are executed as described in
Section 5.2.4 “Two-Word Instructions”.
Under these conditions, the file address of the instruc-
tion is not interpreted as the lower byte of an address
(used with the BSR in Direct Addressing), or as an 8-bit
address in the Access Bank. Instead, the value is
interpreted as an offset value to an Address Pointer,
specified by FSR2. The offset and the contents of
FSR2 are added to obtain the target address of the
operation.
5.6
Data Memory and the Extended
Instruction Set
Enabling the PIC18 extended instruction set (XINST
Configuration bit = 1) significantly changes certain
aspects of data memory and its addressing. Specifically,
the use of the Access Bank for many of the core PIC18
instructions is different. This is due to the introduction of
a new addressing mode for the data memory space.
This mode also alters the behavior of Indirect
Addressing using FSR2 and its associated operands.
5.6.2
INSTRUCTIONS AFFECTED BY
INDEXED LITERAL OFFSET MODE
Any of the core PIC18 instructions that can use Direct
Addressing are potentially affected by the Indexed
Literal Offset Addressing mode. This includes all byte-
oriented and bit-oriented instructions, or almost one-half
of the standard PIC18 instruction set. Instructions that
only use Inherent or Literal Addressing modes are
unaffected.
What does not change is just as important. The size of
the data memory space is unchanged, as well as its
linear addressing. The SFR map remains the same.
Core PIC18 instructions can still operate in both Direct
and Indirect Addressing mode; inherent and literal
instructions do not change at all. Indirect Addressing
with FSR0 and FSR1 also remains unchanged.
Additionally, byte-oriented and bit-oriented instructions
are not affected if they use the Access Bank (Access
RAM bit is ‘1’), or include a file address of 60h or above.
Instructions meeting these criteria will continue to
execute as before. A comparison of the different possi-
ble addressing modes when the extended instruction
set is enabled in shown in Figure 5-8.
5.6.1
INDEXED ADDRESSING WITH
LITERAL OFFSET
Those who desire to use byte-oriented or bit-oriented
instructions in the Indexed Literal Offset mode should
note the changes to assembler syntax for this mode.
This is described in more detail in Section 25.2.1
“Extended Instruction Syntax”.
Enabling the PIC18 extended instruction set changes
the behavior of Indirect Addressing using the FSR2
register pair and its associated file operands. Under the
proper conditions, instructions that use the Access
Bank – that is, most bit-oriented and byte-oriented –
instructions – can invoke a form of Indexed Addressing
using an offset specified in the instruction. This special
addressing mode is known as Indexed Addressing with
Literal Offset or Indexed Literal Offset mode.
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FIGURE 5-8:
COMPARING ADDRESSING OPTIONS FOR BIT-ORIENTED AND
BYTE-ORIENTED INSTRUCTIONS (EXTENDED INSTRUCTION SET ENABLED)
EXAMPLE INSTRUCTION: ADDWF, f, d, a (Opcode: 0010 01da ffff ffff)
000h
When a = 0and f ≥ 60h:
The instruction executes in
Direct Forced mode. ‘f’ is
interpreted as a location in the
Access RAM between 060h
and 0FFh. This is the same as
the SFRs, or locations F60h to
0FFh (Bank 15) of data
memory.
060h
080h
Bank 0
100h
00h
60h
Bank 1
through
Bank 14
Valid Range
for ‘f’
FFh
F00h
F60h
Access RAM
Locations below 60h are not
available in this addressing
mode.
Bank 15
SFRs
FFFh
Data Memory
When a = 0and f ≤ 5Fh:
000h
080h
100h
Bank 0
The instruction executes in
Indexed Literal Offset mode. ‘f’
is interpreted as an offset to the
address value in FSR2. The
two are added together to
obtain the address of the target
register for the instruction. The
address can be anywhere in
the data memory space.
001001da ffffffff
Bank 1
through
Bank 14
FSR2H
FSR2L
F00h
F60h
Bank 15
Note that in this mode, the
correct syntax is now:
ADDWF [k], d
SFRs
where ‘k’ is the same as ‘f’.
FFFh
Data Memory
BSR
00000000
000h
080h
100h
When a = 1(all values of f):
Bank 0
The instruction executes in
Direct mode (also known as
Direct Long mode). ‘f’ is
interpreted as a location in
one of the 16 banks of the data
memory space. The bank is
designated by the Bank Select
Register (BSR). The address
can be in any implemented
bank in the data memory
space.
001001da ffffffff
Bank 1
through
Bank 14
F00h
F60h
Bank 15
SFRs
FFFh
Data Memory
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Remapping of the Access Bank applies only to opera-
tions using the Indexed Literal Offset mode. Operations
that use the BSR (Access RAM bit is ‘1’) will continue
to use Direct Addressing as before. Any indirect or
indexed operation that explicitly uses any of the indirect
file operands (including FSR2) will continue to operate
as standard Indirect Addressing. Any instruction that
uses the Access Bank, but includes a register address
of greater than 05Fh, will use Direct Addressing and
the normal Access Bank map.
5.6.3
MAPPING THE ACCESS BANK IN
INDEXED LITERAL OFFSET MODE
The use of Indexed Literal Offset Addressing mode
effectively changes how the lower half of Access RAM
(00h to 7Fh) is mapped. Rather than containing just the
contents of the bottom half of Bank 0, this mode maps
the contents from Bank 0 and a user defined “window”
that can be located anywhere in the data memory
space. The value of FSR2 establishes the lower bound-
ary of the addresses mapped into the window, while the
upper boundary is defined by FSR2 plus 95 (5Fh).
Addresses in the Access RAM above 5Fh are mapped
as previously described (see Section 5.3.2 “Access
Bank”). An example of Access Bank remapping in this
addressing mode is shown in Figure 5-9.
5.6.4
BSR IN INDEXED LITERAL
OFFSET MODE
Although the Access Bank is remapped when the
extended instruction set is enabled, the operation of the
BSR remains unchanged. Direct Addressing using the
BSR to select the data memory bank operates in the
same manner as previously described.
FIGURE 5-9:
REMAPPING THE ACCESS BANK WITH INDEXED LITERAL
OFFSET ADDRESSING
Example Situation:
ADDWF f, d, a
FSR2H:FSR2L = 120h
000h
Bank 0
Locations in the region
from the FSR2 Pointer
(120h) to the pointer plus
05Fh (17Fh) are mapped
to the bottom of the
Access RAM (000h-05Fh).
100h
120h
17Fh
Window
Bank 1
00h
Bank 1 “Window”
200h
5Fh
60h
Special Function Registers
at F60h through FFFh are
mapped to 60h through
FFh, as usual.
Bank 2
through
Bank 14
SFRs
Bank 0 addresses below
5Fh are not available in
this mode. They can still
be addressed by using the
BSR.
FFh
Access Bank
F00h
F60h
Bank 15
SFRs
FFFh
Data Memory
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NOTES:
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6.1
Table Reads and Table Writes
6.0
FLASH PROGRAM MEMORY
In order to read and write program memory, there are
two operations that allow the processor to move bytes
between the program memory space and the data RAM:
The Flash program memory is readable, writable and
erasable during normal operation over the entire VDD
range.
• Table Read (TBLRD)
• Table Write (TBLWT)
A read from program memory is executed on one byte
at a time. A write to program memory is executed on
blocks of 64 bytes at a time. Program memory is
erased in blocks of 64 bytes at a time. A Bulk Erase
operation may not be issued from user code.
The program memory space is 16 bits wide, while the
data RAM space is 8 bits wide. Table reads and table
writes move data between these two memory spaces
through an 8-bit register (TABLAT).
Writing or erasing program memory will cease
instruction fetches until the operation is complete. The
program memory cannot be accessed during the write
or erase, therefore, code cannot execute. An internal
programming timer terminates program memory writes
and erases.
Table read operations retrieve data from program
memory and place it into the data RAM space.
Figure 6-1 shows the operation of a table read with
program memory and data RAM.
Table write operations store data from the data memory
space into holding registers in program memory. The
procedure to write the contents of the holding registers
into program memory is detailed in Section 6.5 “Writing
to Flash Program Memory”. Figure 6-2 shows the
operation of a table write with program memory and data
RAM.
A value written to program memory does not need to be
a valid instruction. Executing a program memory
location that forms an invalid instruction results in a
NOP.
Table operations work with byte entities. A table block
containing data, rather than program instructions, is not
required to be word-aligned. Therefore, a table block can
start and end at any byte address. If a table write is being
used to write executable code into program memory,
program instructions will need to be word-aligned.
FIGURE 6-1:
TABLE READ OPERATION
Instruction: TBLRD*
Program Memory
(1)
Table Pointer
Table Latch (8-bit)
TABLAT
TBLPTRU TBLPTRH TBLPTRL
Program Memory
(TBLPTR)
Note 1: Table Pointer register points to a byte in program memory.
© 2007 Microchip Technology Inc.
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FIGURE 6-2:
TABLE WRITE OPERATION
Instruction: TBLWT*
Program Memory
Holding Registers
(1)
Table Pointer
TBLPTRU TBLPTRH TBLPTRL
Table Latch (8-bit)
TABLAT
Program Memory
(TBLPTR)
Note 1: Table Pointer actually points to one of 64 holding registers, the address of which is determined by
TBLPTRL<5:0>. The process for physically writing data to the program memory array is discussed in
Section 6.5 “Writing to Flash Program Memory”.
The FREE bit, when set, will allow a program memory
erase operation. When FREE is set, the erase
operation is initiated on the next WR command. When
FREE is clear, only writes are enabled.
6.2
Control Registers
Several control registers are used in conjunction with
the TBLRDand TBLWTinstructions. These include the:
• EECON1 register
• EECON2 register
• TABLAT register
• TBLPTR registers
The WREN bit, when set, will allow a write operation.
On power-up, the WREN bit is clear. The WRERR bit is
set in hardware when the WREN bit is set, and cleared
when the internal programming timer expires and the
write operation is complete.
6.2.1
EECON1 AND EECON2 REGISTERS
Note:
During normal operation, the WRERR is
read as ‘1’. This can indicate that a write
operation was prematurely terminated by
The EECON1 register (Register 6-1) is the control
register for memory accesses. The EECON2 register is
not a physical register; it is used exclusively in the
memory write and erase sequences. Reading
EECON2 will read all ‘0’s.
a
Reset or
a write operation was
attempted improperly.
The WR control bit initiates write operations. The bit
cannot be cleared, only set, in software; it is cleared in
hardware at the completion of the write operation.
The EEPGD control bit determines if the access will be
a program or data EEPROM memory access. When
clear, any subsequent operations will operate on the
data EEPROM memory. When set, any subsequent
operations will operate on the program memory.
Note:
The EEIF Interrupt flag bit (PIR2<4>) is set
when the write is complete. It must be
cleared in software.
The CFGS control bit determines if the access will be
to the Configuration/Calibration registers or to program
memory/data EEPROM memory. When set,
subsequent operations will operate on Configuration
registers regardless of EEPGD (see Section 24.0
“Special Features of the CPU”). When clear, memory
selection access is determined by EEPGD.
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REGISTER 6-1:
EECON1: DATA EEPROM CONTROL REGISTER 1
R/W-x
EEPGD
bit 7
R/W-x
CFGS
U-0
—
R/W-0
FREE
R/W-x
WRERR(1)
R/W-0
WREN
R/S-0
WR
R/S-0
RD
bit 0
Legend:
S = Settable bit
W = Writable bit
‘1’ = Bit is set
R = Readable bit
-n = Value at POR
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7
bit 6
EEPGD: Flash Program or Data EEPROM Memory Select bit
1= Access Flash program memory
0= Access data EEPROM memory
CFGS: Flash Program/Data EEPROM or Configuration Select bit
1= Access Configuration registers
0= Access Flash program or data EEPROM memory
bit 5
bit 4
Unimplemented: Read as ‘0’
FREE: Flash Row Erase Enable bit
1= Erase the program memory row addressed by TBLPTR on the next WR command (cleared by
completion of erase operation)
0= Perform write-only
bit 3
WRERR: Flash Program/Data EEPROM Error Flag bit(1)
1= A write operation is prematurely terminated (any Reset during self-timed programming in normal
operation or an improper write attempt)
0= The write operation completed
bit 2
bit 1
WREN: Flash Program/Data EEPROM Write Enable bit
1= Allows write cycles to Flash program/data EEPROM
0= Inhibits write cycles to Flash program/data EEPROM
WR: Write Control bit
1= Initiates a data EEPROM erase/write cycle or a program memory erase cycle or write cycle
(The operation is self-timed and the bit is cleared by hardware once write is complete.
The WR bit can only be set (not cleared) in software.)
0= Write cycle to the EEPROM is complete
bit 0
RD: Read Control bit
1= Initiates an EEPROM read (Read takes one cycle. RD is cleared in hardware. The RD bit can only
be set (not cleared) in software. RD bit cannot be set when EEPGD = 1or CFGS = 1.)
0= Does not initiate an EEPROM read
Note 1: When a WRERR occurs, the EEPGD and CFGS bits are not cleared. This allows tracing of the error
condition.
© 2007 Microchip Technology Inc.
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6.2.2
TABLAT – TABLE LATCH REGISTER
6.2.4
TABLE POINTER BOUNDARIES
The Table Latch (TABLAT) is an 8-bit register mapped
into the SFR space. The Table Latch register is used to
hold 8-bit data during data transfers between program
memory and data RAM.
TBLPTR is used in reads, writes and erases of the
Flash program memory.
When a TBLRDis executed, all 22 bits of the TBLPTR
determine which byte is read from program memory
into TABLAT.
6.2.3
TBLPTR – TABLE POINTER
REGISTER
When a TBLWTis executed, the six LSbs of the Table
Pointer register (TBLPTR<5:0>) determine which of the
64 program memory holding registers is written to.
When the timed write to program memory begins (via
the WR bit), the 16 MSbs of the TBLPTR
(TBLPTR<21:6>) determine which program memory
block of 64 bytes is written to. For more detail, see
Section 6.5 “Writing to Flash Program Memory”.
The Table Pointer (TBLPTR) register addresses a byte
within the program memory. The TBLPTR is comprised
of three SFR registers: Table Pointer Upper Byte, Table
Pointer High Byte and Table Pointer Low Byte
(TBLPTRU:TBLPTRH:TBLPTRL). These three regis-
ters join to form a 22-bit wide pointer. The low-order
21 bits allow the device to address up to 2 Mbytes of
program memory space. The 22nd bit allows access to
the Device ID, the user ID and the Configuration bits.
When an erase of program memory is executed, the
16 MSbs of the Table Pointer register (TBLPTR<21:6>)
point to the 64-byte block that will be erased. The Least
Significant bits (TBLPTR<5:0>) are ignored.
The Table Pointer, TBLPTR, is used by the TBLRDand
TBLWTinstructions. These instructions can update the
TBLPTR in one of four ways based on the table opera-
tion. These operations are shown in Table 6-1. These
operations on the TBLPTR only affect the low-order
21 bits.
Figure 6-3 describes the relevant boundaries of
TBLPTR based on Flash program memory operations.
TABLE 6-1:
Example
TABLE POINTER OPERATIONS WITH TBLRDAND TBLWTINSTRUCTIONS
Operation on Table Pointer
TBLRD*
TBLWT*
TBLPTR is not modified
TBLRD*+
TBLWT*+
TBLPTR is incremented after the read/write
TBLPTR is decremented after the read/write
TBLPTR is incremented before the read/write
TBLRD*-
TBLWT*-
TBLRD+*
TBLWT+*
FIGURE 6-3:
TABLE POINTER BOUNDARIES BASED ON OPERATION
21
16 15
8
7
0
TBLPTRU
TBLPTRH
TBLPTRL
Table Erase/Write
TBLPTR<21:6>
Table Write
TBLPTR<5:0>
Table Read – TBLPTR<21:0>
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The internal program memory is typically organized by
words. The Least Significant bit of the address selects
between the high and low bytes of the word. Figure 6-4
shows the interface between the internal program
memory and the TABLAT.
6.3
Reading the Flash Program
Memory
The TBLRD instruction is used to retrieve data from
program memory and places it into data RAM. Table
reads from program memory are performed one byte at
a time.
TBLPTR points to a byte address in program space.
Executing TBLRD places the byte pointed to into
TABLAT. In addition, TBLPTR can be modified
automatically for the next table read operation.
FIGURE 6-4:
READS FROM FLASH PROGRAM MEMORY
Program Memory
(Even Byte Address)
(Odd Byte Address)
TBLPTR = xxxxx1
TBLPTR = xxxxx0
Instruction Register
TABLAT
Read Register
TBLRD
FETCH
(IR)
EXAMPLE 6-1:
READING A FLASH PROGRAM MEMORY WORD
MOVLW
CODE_ADDR_UPPER
TBLPTRU
CODE_ADDR_HIGH
TBLPTRH
CODE_ADDR_LOW
TBLPTRL
; Load TBLPTR with the base
; address of the word
MOVWF
MOVLW
MOVWF
MOVLW
MOVWF
READ_WORD
TBLRD*+
MOVF
MOVWF
TBLRD*+
MOVF
; read into TABLAT and increment
; get data
TABLAT, W
WORD_EVEN
; read into TABLAT and increment
; get data
TABLAT, W
WORD_ODD
MOVF
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6.4.1
FLASH PROGRAM MEMORY
ERASE SEQUENCE
6.4
Erasing Flash Program Memory
The minimum erase block is 32 words or 64 bytes. Only
through the use of an external programmer, or through
ICSP control, can larger blocks of program memory be
Bulk Erased. Word Erase in the Flash array is not
supported.
The sequence of events for erasing a block of internal
program memory location is:
1. Load Table Pointer register with address of row
being erased.
When initiating an erase sequence from the micro-
controller itself, a block of 64 bytes of program memory
is erased. The Most Significant 16 bits of the
TBLPTR<21:6> point to the block being erased.
TBLPTR<5:0> are ignored.
2. Set the EECON1 register for the erase operation:
• set EEPGD bit to point to program memory;
• clear the CFGS bit to access program memory;
• set WREN bit to enable writes;
• set FREE bit to enable the erase.
3. Disable interrupts.
The EECON1 register commands the erase operation.
The EEPGD bit must be set to point to the Flash
program memory. The WREN bit must be set to enable
write operations. The FREE bit is set to select an erase
operation.
4. Write 55h to EECON2.
5. Write 0AAh to EECON2.
6. Set the WR bit. This will begin the Row Erase
cycle.
For protection, the write initiate sequence for EECON2
must be used.
7. The CPU will stall for duration of the erase
(about 2 ms using internal timer).
A long write is necessary for erasing the internal Flash.
Instruction execution is halted while in a long write
cycle. The long write will be terminated by the internal
programming timer.
8. Re-enable interrupts.
EXAMPLE 6-2:
ERASING A FLASH PROGRAM MEMORY ROW
MOVLW
MOVWF
MOVLW
MOVWF
MOVLW
MOVWF
CODE_ADDR_UPPER
TBLPTRU
CODE_ADDR_HIGH
TBLPTRH
CODE_ADDR_LOW
TBLPTRL
; load TBLPTR with the base
; address of the memory block
ERASE_ROW
BSF
BCF
BSF
BSF
EECON1, EEPGD
EECON1, CFGS
EECON1, WREN
EECON1, FREE
INTCON, GIE
55h
EECON2
0AAh
EECON2
EECON1, WR
INTCON, GIE
; point to Flash program memory
; access Flash program memory
; enable write to memory
; enable Row Erase operation
; disable interrupts
BCF
Required
Sequence
MOVLW
MOVWF
MOVLW
MOVWF
BSF
; write 55h
; write 0AAh
; start erase (CPU stall)
; re-enable interrupts
BSF
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The long write is necessary for programming the
6.5
Writing to Flash Program Memory
internal Flash. Instruction execution is halted while in a
long write cycle. The long write will be terminated by
the internal programming timer.
The minimum programming block is 32 words or
64 bytes. Word or byte programming is not supported.
Table writes are used internally to load the holding
registers needed to program the Flash memory. There
are 64 holding registers used by the table writes for
programming.
The EEPROM on-chip timer controls the write time.
The write/erase voltages are generated by an on-chip
charge pump, rated to operate over the voltage range
of the device.
Since the Table Latch (TABLAT) is only a single byte,
the TBLWT instruction may need to be executed
64 times for each programming operation. All of the
table write operations will essentially be short writes
because only the holding registers are written. At the
end of updating the 64 holding registers, the EECON1
register must be written to in order to start the
programming operation with a long write.
Note:
The default value of the holding registers on
device Resets and after write operations is
FFh. A write of FFh to a holding register
does not modify that byte. This means that
individual bytes of program memory may be
modified, provided that the change does not
attempt to change any bit from a ‘0’ to a ‘1’.
When modifying individual bytes, it is not
necessary to load all 64 holding registers
before executing a write operation.
FIGURE 6-5:
TABLE WRITES TO FLASH PROGRAM MEMORY
TABLAT
Write Register
8
8
8
8
TBLPTR = xxxxx0
TBLPTR = xxxxx1
TBLPTR = xxxxx2
TBLPTR = xxxx3F
Holding Register
Holding Register
Holding Register
Holding Register
Program Memory
8. Disable interrupts.
6.5.1
FLASH PROGRAM MEMORY WRITE
SEQUENCE
9. Write 55h to EECON2.
10. Write 0AAh to EECON2.
The sequence of events for programming an internal
program memory location should be:
11. Set the WR bit. This will begin the write cycle.
12. The CPU will stall for duration of the write (about
2 ms using internal timer).
1. Read 64 bytes into RAM.
2. Update data values in RAM as necessary.
13. Re-enable interrupts.
3. Load Table Pointer register with address being
erased.
14. Verify the memory (table read).
This procedure will require about 18 ms to update one
row of 64 bytes of memory. An example of the required
code is given in Example 6-3.
4. Execute the Row Erase procedure.
5. Load Table Pointer register with address of first
byte being written.
6. Write the 64 bytes into the holding registers with
auto-increment.
Note:
Before setting the WR bit, the Table
Pointer address needs to be within the
intended address range of the 64 bytes in
the holding register.
7. Set the EECON1 register for the write operation:
• set EEPGD bit to point to program memory;
• clear the CFGS bit to access program memory;
• set WREN to enable byte writes.
© 2007 Microchip Technology Inc.
Preliminary
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EXAMPLE 6-3:
WRITING TO FLASH PROGRAM MEMORY
MOVLW
D'64
; number of bytes in erase block
MOVWF
MOVLW
MOVWF
MOVLW
MOVWF
MOVLW
MOVWF
MOVLW
MOVWF
MOVLW
MOVWF
COUNTER
BUFFER_ADDR_HIGH
FSR0H
BUFFER_ADDR_LOW
FSR0L
CODE_ADDR_UPPER
TBLPTRU
CODE_ADDR_HIGH
TBLPTRH
CODE_ADDR_LOW
TBLPTRL
; point to buffer
; Load TBLPTR with the base
; address of the memory block
READ_BLOCK
TBLRD*+
MOVF
MOVWF
; read into TABLAT, and inc
; get data
; store data
; done?
TABLAT, W
POSTINC0
DECFSZ COUNTER
BRA
READ_BLOCK
; repeat
MODIFY_WORD
MOVLW
MOVWF
MOVLW
MOVWF
MOVLW
MOVWF
MOVLW
MOVWF
DATA_ADDR_HIGH
FSR0H
DATA_ADDR_LOW
FSR0L
NEW_DATA_LOW
POSTINC0
NEW_DATA_HIGH
INDF0
; point to buffer
; update buffer word
ERASE_BLOCK
MOVLW
MOVWF
MOVLW
MOVWF
MOVLW
MOVWF
BSF
BCF
BSF
BSF
BCF
MOVLW
MOVWF
MOVLW
MOVWF
BSF
CODE_ADDR_UPPER
TBLPTRU
CODE_ADDR_HIGH
TBLPTRH
CODE_ADDR_LOW
TBLPTRL
EECON1, EEPGD
EECON1, CFGS
EECON1, WREN
EECON1, FREE
INTCON, GIE
55h
EECON2
0AAh
EECON2
EECON1, WR
INTCON, GIE
; load TBLPTR with the base
; address of the memory block
; point to Flash program memory
; access Flash program memory
; enable write to memory
; enable Row Erase operation
; disable interrupts
Required
Sequence
; write 55h
; write 0AAh
; start erase (CPU stall)
; re-enable interrupts
; dummy read decrement
; point to buffer
BSF
TBLRD*-
MOVLW
MOVWF
MOVLW
MOVWF
BUFFER_ADDR_HIGH
FSR0H
BUFFER_ADDR_LOW
FSR0L
WRITE_BUFFER_BACK
MOVLW
D’64
; number of bytes in holding register
MOVWF
WRITE_BYTE_TO_HREGS
MOVF
COUNTER
POSTINC0, W
TABLAT
; get low byte of buffer data
; present data to table latch
; write data, perform a short write
; to internal TBLWT holding register.
; loop until buffers are full
MOVWF
TBLWT+*
DECFSZ COUNTER
BRA WRITE_BYTE_TO_HREGS
DS39761B-page 102
Preliminary
© 2007 Microchip Technology Inc.
PIC18F2682/2685/4682/4685
EXAMPLE 6-3:
WRITING TO FLASH PROGRAM MEMORY (CONTINUED)
PROGRAM_MEMORY
BSF
BCF
BSF
BCF
MOVLW
MOVWF
MOVLW
MOVWF
BSF
EECON1, EEPGD
EECON1, CFGS
EECON1, WREN
INTCON, GIE
55h
EECON2
0AAh
EECON2
; point to Flash program memory
; access Flash program memory
; enable write to memory
; disable interrupts
Required
Sequence
; write 55h
; write 0AAh
EECON1, WR
INTCON, GIE
EECON1, WREN
; start program (CPU stall)
; re-enable interrupts
; disable write to memory
BSF
BCF
6.5.2
WRITE VERIFY
6.5.4
PROTECTION AGAINST
SPURIOUS WRITES
Depending on the application, good programming
practice may dictate that the value written to the
memory should be verified against the original value.
This should be used in applications where excessive
writes can stress bits near the specification limit.
To protect against spurious writes to Flash program
memory, the write initiate sequence must also be
followed. See Section 24.0 “Special Features of the
CPU” for more detail.
6.5.3
UNEXPECTED TERMINATION OF
WRITE OPERATION
6.6
Flash Program Operation During
Code Protection
If a write is terminated by an unplanned event, such as
loss of power or an unexpected Reset, the memory
location just programmed should be verified and
reprogrammed if needed. If the write operation is inter-
rupted by a MCLR Reset, or a WDT Time-out Reset
during normal operation, the user can check the
WRERR bit and rewrite the location(s) as needed.
See Section 24.5 “Program Verification and Code
Protection” for details on code protection of Flash
program memory.
TABLE 6-2:
Name
REGISTERS ASSOCIATED WITH PROGRAM FLASH MEMORY
Reset
Values on
page
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
TBLPTRU
—
—
bit 21 Program Memory Table Pointer Upper Byte (TBLPTR<20:16>)
49
49
49
49
49
51
51
51
52
52
TBPLTRH Program Memory Table Pointer High Byte (TBLPTR<15:8>)
TBLPTRL Program Memory Table Pointer High Byte (TBLPTR<7:0>)
TABLAT
INTCON
Program Memory Table Latch
GIE/GIEH PEIE/GIEL TMR0IE INT0IE
RBIE
TMR0IF
INT0IF
WR
TMR3IP ECCP1IP(1)
TMR3IF ECCP1IF(1)
TMR3IE ECCP1IE(1)
RBIF
RD
EECON2 EEPROM Control Register 2 (not a physical register)
EECON1
IPR2
EEPGD
CFGS
—
—
—
—
FREE
EEIP
EEIF
EEIE
WRERR
BCLIP
BCLIF
BCLIE
WREN
HLVDIP
HLVDIF
HLVDIE
OSCFIP CMIP(1)
OSCFIF CMIF(1)
OSCFIE CMIE(1)
PIR2
PIE2
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used during Flash/EEPROM access.
Note 1: These bits are available in PIC18F4682/4685 devices and reserved in PIC18F2682/2685 devices.
© 2007 Microchip Technology Inc.
Preliminary
DS39761B-page 103
PIC18F2682/2685/4682/4685
NOTES:
DS39761B-page 104
Preliminary
© 2007 Microchip Technology Inc.
PIC18F2682/2685/4682/4685
The EECON1 register (Register 7-1) is the control
register for data and program memory access. Control
bit EEPGD determines if the access will be to program
or data EEPROM memory. When clear, operations will
access the data EEPROM memory. When set, program
memory is accessed.
7.0
DATA EEPROM MEMORY
The data EEPROM is a nonvolatile memory array,
separate from the data RAM and program memory, that
is used for long-term storage of program data. It is not
directly mapped in either the register file or program
memory space but is indirectly addressed through the
Special Function Registers (SFRs). The EEPROM is
readable and writable during normal operation over the
entire VDD range.
Control bit CFGS determines if the access will be to the
Configuration registers or to program memory/data
EEPROM memory. When set, subsequent operations
access Configuration registers. When CFGS is clear,
the EEPGD bit selects either program Flash or data
EEPROM memory.
Five SFRs are used to read and write to the data
EEPROM as well as the program memory. They are:
• EECON1
• EECON2
• EEDATA
• EEADR
The WREN bit, when set, will allow a write operation.
On power-up, the WREN bit is clear. The WRERR bit is
set in hardware when the WREN bit is set and cleared
when the internal programming timer expires and the
write operation is complete.
• EEADRH
Note:
During normal operation, the WRERR is
read as ‘1’. This can indicate that a write
operation was prematurely terminated by
The data EEPROM allows byte read and write. When
interfacing to the data memory block, EEDATA holds
the 8-bit data for read/write and the EEADRH:EEADR
register pair holds the address of the EEPROM location
being accessed.
a
Reset, or
a write operation was
attempted improperly.
The WR control bit initiates write operations. The bit
cannot be cleared, only set, in software; it is cleared in
hardware at the completion of the write operation.
The EEPROM data memory is rated for high erase/write
cycle endurance. A byte write automatically erases the
location and writes the new data (erase-before-write).
The write time is controlled by an on-chip timer; it will
vary with voltage and temperature, as well as from chip
to chip. Please refer to parameter D122 (Table 27-1 in
Section 27.0 “Electrical Characteristics”) for exact
limits.
Note:
The EEIF interrupt flag bit (PIR2<4>) is set
when the write is complete. It must be
cleared in software.
Control bits, RD and WR, start read and erase/write
operations, respectively. These bits are set by firmware
and cleared by hardware at the completion of the
operation.
7.1
EEADR and EEADRH Registers
The EEADRH:EEADR register pair is used to address
the data EEPROM for read and write operations.
EEADRH holds the two Most Significant bits of the
address; the upper 6 bits are ignored. The 10-bit range
of the pair can address a memory range of 1024 bytes
(00h to 3FFh).
The RD bit cannot be set when accessing program
memory (EEPGD = 1). Program memory is read using
table read instructions. See Section 6.1 “Table Reads
and Table Writes” regarding table reads.
The EECON2 register is not a physical register. It is
used exclusively in the memory write and erase
sequences. Reading EECON2 will read all ‘0’s.
7.2
EECON1 and EECON2 Registers
Access to the data EEPROM is controlled by two
registers: EECON1 and EECON2. These are the same
registers which control access to the program memory
and are used in a similar manner for the data
EEPROM.
© 2007 Microchip Technology Inc.
Preliminary
DS39761B-page 105
PIC18F2682/2685/4682/4685
REGISTER 7-1:
EECON1: DATA EEPROM CONTROL REGISTER 1
R/W-x
EEPGD
bit 7
R/W-x
CFGS
U-0
—
R/W-0
FREE
R/W-x
WRERR(1)
R/W-0
WREN
R/S-0
WR
R/S-0
RD
bit 0
Legend:
S = Settable bit
W = Writable bit
‘1’ = Bit is set
R = Readable bit
-n = Value at POR
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7
bit 6
EEPGD: Flash Program or Data EEPROM Memory Select bit
1= Access Flash program memory
0= Access data EEPROM memory
CFGS: Flash Program/Data EEPROM or Configuration Select bit
1= Access Configuration registers
0= Access Flash program or data EEPROM memory
bit 5
bit 4
Unimplemented: Read as ‘0’
FREE: Flash Row Erase Enable bit
1= Erase the program memory row addressed by TBLPTR on the next WR command
(cleared by completion of erase operation)
0= Perform write-only
bit 3
WRERR: Flash Program/Data EEPROM Error Flag bit(1)
1= A write operation is prematurely terminated (any Reset during self-timed programming in normal
operation, or an improper write attempt)
0= The write operation completed
bit 2
bit 1
WREN: Flash Program/Data EEPROM Write Enable bit
1= Allows write cycles to Flash program/data EEPROM
0= Inhibits write cycles to Flash program/data EEPROM
WR: Write Control bit
1= Initiates a data EEPROM erase/write cycle or a program memory erase cycle or write cycle.
(The operation is self-timed and the bit is cleared by hardware once write is complete.
The WR bit can only be set (not cleared) in software.)
0= Write cycle to the EEPROM is complete
bit 0
RD: Read Control bit
1= Initiates an EEPROM read (Read takes one cycle. RD is cleared in hardware. The RD bit can only
be set (not cleared) in software. RD bit cannot be set when EEPGD = 1or CFGS = 1.)
0= Does not initiate an EEPROM read
Note 1: When a WRERR occurs, the EEPGD and CFGS bits are not cleared. This allows tracing of the error
condition.
DS39761B-page 106
Preliminary
© 2007 Microchip Technology Inc.
PIC18F2682/2685/4682/4685
Additionally, the WREN bit in EECON1 must be set to
enable writes. This mechanism prevents accidental
writes to data EEPROM due to unexpected code
execution (i.e., runaway programs). The WREN bit
should be kept clear at all times, except when updating
the EEPROM. The WREN bit is not cleared
by hardware.
7.3
Reading the Data EEPROM
Memory
To read a data memory location, the user must write the
address to the EEADRH:EEADR register pair, clear the
EEPGD control bit (EECON1<7>) and then set control
bit, RD (EECON1<0>). The data is available on the
very next instruction cycle; therefore, the EEDATA
register can be read by the next instruction. EEDATA
will hold this value until another read operation, or until
it is written to by the user (during a write operation).
After a write sequence has been initiated, EECON1,
EEADRH:EEADR and EEDATA cannot be modified.
The WR bit will be inhibited from being set unless the
WREN bit is set. The WREN bit must be set on a
previous instruction. Both WR and WREN cannot be
set with the same instruction.
The basic process is shown in Example 7-1.
7.4
Writing to the Data EEPROM
Memory
At the completion of the write cycle, the WR bit is
cleared in hardware and the EEPROM Interrupt Flag bit
(EEIF) is set. The user may either enable this interrupt,
or poll this bit. EEIF must be cleared by software.
To write an EEPROM data location, the address must
first be written to the EEADRH:EEADR register pair
and the data written to the EEDATA register. The
sequence in Example 7-2 must be followed to initiate
the write cycle.
7.5
Write Verify
Depending on the application, good programming
practice may dictate that the value written to the
memory should be verified against the original value.
This should be used in applications where excessive
writes can stress bits near the specification limit.
The write will not begin if this sequence is not exactly
followed (write 55h to EECON2, write 0AAh to
EECON2, then set WR bit) for each byte. It is strongly
recommended that interrupts be disabled during this
code segment.
EXAMPLE 7-1:
DATA EEPROM READ
MOVLW
MOVWF
MOVLW
MOVWF
BCF
BCF
BSF
MOVF
DATA_EE_ADDRH
EEADRH
;
; Upper bits of Data Memory Address to read
;
; Lower bits of Data Memory Address to read
; Point to DATA memory
; Access EEPROM
DATA_EE_ADDR
EEADR
EECON1, EEPGD
EECON1, CFGS
EECON1, RD
EEDATA, W
; EEPROM Read
; W = EEDATA
EXAMPLE 7-2:
DATA EEPROM WRITE
MOVLW
MOVWF
MOVLW
MOVWF
MOVLW
MOVWF
BCF
DATA_EE_ADDRH
EEADRH
DATA_EE_ADDR
EEADR
DATA_EE_DATA
EEDATA
EECON1, EPGD
EECON1, CFGS
EECON1, WREN
;
; Upper bits of Data Memory Address to write
;
; Lower bits of Data Memory Address to write
;
; Data Memory Value to write
; Point to DATA memory
; Access EEPROM
BCF
BSF
; Enable writes
BCF
INTCON, GIE
55h
EECON2
0AAh
EECON2
; Disable Interrupts
;
; Write 55h
;
; Write 0AAh
; Set WR bit to begin write
; Enable Interrupts
MOVLW
MOVWF
MOVLW
MOVWF
BSF
Required
Sequence
EECON1, WR
INTCON, GIE
BSF
; User code execution
BCF
EECON1, WREN
; Disable writes on write complete (EEIF set)
© 2007 Microchip Technology Inc.
Preliminary
DS39761B-page 107
PIC18F2682/2685/4682/4685
7.6
Operation During Code-Protect
7.8
Using the Data EEPROM
Data EEPROM memory has its own code-protect bits in
Configuration Words. External read and write
operations are disabled if code protection is enabled.
The data EEPROM is a high-endurance, byte address-
able array that has been optimized for the storage of
frequently changing information (e.g., program
variables or other data that are updated often).
Frequently changing values will typically be updated
more often than specification D124. If this is not the
case, an array refresh must be performed. For this
reason, variables that change infrequently (such as
constants, IDs, calibration, etc.) should be stored in
Flash program memory.
The microcontroller itself can both read and write to the
internal Data EEPROM, regardless of the state of the
code-protect Configuration bit. Refer to Section 24.0
“Special Features of the CPU” for additional
information.
7.7
Protection Against Spurious Write
A simple data EEPROM refresh routine is shown in
Example 7-3.
There are conditions when the device may not want to
write to the data EEPROM memory. To protect against
spurious EEPROM writes, various mechanisms have
been implemented. On power-up, the WREN bit is
cleared. In addition, writes to the EEPROM are blocked
during the Power-up Timer period (TPWRT,
parameter 33).
Note:
If data EEPROM is only used to store
constants and/or data that changes rarely,
an array refresh is likely not required. See
specification D124.
The write initiate sequence and the WREN bit together
help prevent an accidental write during brown-out,
power glitch or software malfunction.
EXAMPLE 7-3:
DATA EEPROM REFRESH ROUTINE
CLRF
CLRF
BCF
BCF
BCF
EEADR
EEADRH
EECON1, CFGS
EECON1, EEPGD
INTCON, GIE
EECON1, WREN
; Start at address 0
;
; Set for memory
; Set for Data EEPROM
; Disable interrupts
; Enable writes
; Loop to refresh array
; Read current address
;
; Write 55h
;
; Write 0AAh
; Set WR bit to begin write
; Wait for write to complete
BSF
Loop
BSF
EECON1, RD
55h
EECON2
0AAh
EECON2
EECON1, WR
EECON1, WR
$-2
MOVLW
MOVWF
MOVLW
MOVWF
BSF
BTFSC
BRA
INCFSZ EEADR, F
; Increment address
BRA
LOOP
; Not zero, do it again
; Increment the high address
; Not zero, do it again
INCFSZ EEADRH, F
BRA
LOOP
BCF
BSF
EECON1, WREN
INTCON, GIE
; Disable writes
; Enable interrupts
DS39761B-page 108
Preliminary
© 2007 Microchip Technology Inc.
PIC18F2682/2685/4682/4685
TABLE 7-1:
Name
REGISTERS ASSOCIATED WITH DATA EEPROM MEMORY
Reset
Values
on page
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
INTCON
EEADRH
GIE/GIEH PEIE/GIEL TMR0IE
INT0IE
—
RBIE
—
TMR0IF
—
INT0IF
RBIF
49
51
—
—
—
EEPROM Address
Register High Byte
EEADR
EEPROM Address Register Low Byte
51
51
51
51
51
52
52
EEDATA EEPROM Data Register
EECON2 EEPROM Control Register 2 (not a physical register)
EECON1
IPR2
EEPGD
OSCFIP
OSCFIF
OSCFIE
CFGS
CMIP(1)
CMIF(1)
CMIE(1)
—
—
—
—
FREE
EEIP
EEIF
EEIE
WRERR
BCLIP
BCLIF
BCLIE
WREN
HLVDIP
HLVDIF
HLVDIE
WR
RD
TMR3IP ECCP1IP(1)
TMR3IF ECCP1IF(1)
TMR3IE ECCP1IE(1)
PIR2
PIE2
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used during Flash/EEPROM access.
Note 1: These bits are available in PIC18F4682/4685 devices and reserved in PIC18F2682/2685 devices.
© 2007 Microchip Technology Inc.
Preliminary
DS39761B-page 109
PIC18F2682/2685/4682/4685
NOTES:
DS39761B-page 110
Preliminary
© 2007 Microchip Technology Inc.
PIC18F2682/2685/4682/4685
EXAMPLE 8-1:
8 x 8 UNSIGNED
MULTIPLY ROUTINE
8.0
8.1
8 x 8 HARDWARE MULTIPLIER
Introduction
MOVF
MULWF
ARG1, W
ARG2
;
; ARG1 * ARG2 ->
; PRODH:PRODL
All PIC18 devices include an 8 x 8 hardware multiplier
as part of the ALU. The multiplier performs an unsigned
operation and yields a 16-bit result that is stored in the
product register pair, PRODH:PRODL. The multiplier’s
operation does not affect any flags in the STATUS
register.
EXAMPLE 8-2:
8 x 8 SIGNED MULTIPLY
ROUTINE
Making multiplication a hardware operation allows it to
be completed in a single instruction cycle. This has the
advantages of higher computational throughput and
reduced code size for multiplication algorithms and
allows the PIC18 devices to be used in many applica-
tions previously reserved for digital signal processors.
A comparison of various hardware and software
multiply operations, along with the savings in memory
and execution time, is shown in Table 8-1.
MOVF
MULWF
ARG1, W
ARG2
; ARG1 * ARG2 ->
; PRODH:PRODL
; Test Sign Bit
; PRODH = PRODH
BTFSC
SUBWF
ARG2, SB
PRODH, F
;
- ARG1
MOVF
BTFSC
SUBWF
ARG2, W
ARG1, SB
PRODH, F
; Test Sign Bit
; PRODH = PRODH
;
- ARG2
8.2
Operation
Example 8-1 shows the instruction sequence for an
8 x 8 unsigned multiplication. Only one instruction is
required when one of the arguments is already loaded
in the WREG register.
Example 8-2 shows the sequence to do an 8 x 8 signed
multiplication. To account for the signed bits of the
arguments, each argument’s Most Significant bit (MSb)
is tested and the appropriate subtractions are done.
TABLE 8-1:
Routine
PERFORMANCE COMPARISON FOR VARIOUS MULTIPLY OPERATIONS
Program
Memory
(Words)
Time
Cycles
(Max)
Multiply Method
@ 40 MHz @ 10 MHz @ 4 MHz
Without hardware multiply
Hardware multiply
13
1
69
1
6.9 μs
100 ns
9.1 μs
600 ns
24.2 μs
2.8 μs
25.4 μs
4.0 μs
27.6 μs
400 ns
36.4 μs
2.4 μs
69 μs
1 μs
8 x 8 unsigned
8 x 8 signed
Without hardware multiply
Hardware multiply
33
6
91
6
91 μs
6 μs
Without hardware multiply
Hardware multiply
21
28
52
35
242
28
254
40
96.8 μs
11.2 μs
102.6 μs
16.0 μs
242 μs
28 μs
254 μs
40 μs
16 x 16 unsigned
16 x 16 signed
Without hardware multiply
Hardware multiply
© 2007 Microchip Technology Inc.
Preliminary
DS39761B-page 111
PIC18F2682/2685/4682/4685
Example 8-3 shows the sequence to do a 16 x 16
unsigned multiplication. Equation 8-1 shows the
algorithm that is used. The 32-bit result is stored in four
registers (RES3:RES0).
EQUATION 8-2:
16 x 16 SIGNED
MULTIPLICATION
ALGORITHM
RES3:RES0=ARG1H:ARG1L • ARG2H:ARG2L
16
= (ARG1H • ARG2H • 2 ) +
(ARG1H • ARG2L • 2 ) +
(ARG1L • ARG2H • 2 ) +
(ARG1L • ARG2L) +
(-1 • ARG2H<7> • ARG1H:ARG1L • 2 ) +
(-1 • ARG1H<7> • ARG2H:ARG2L • 2
8
EQUATION 8-1:
16 x 16 UNSIGNED
MULTIPLICATION
ALGORITHM
8
16
RES3:RES0
=
=
ARG1H:ARG1L • ARG2H:ARG2L
16
)
16
(ARG1H • ARG2H • 2 ) +
8
(ARG1H • ARG2L • 2 ) +
8
(ARG1L • ARG2H • 2 ) +
EXAMPLE 8-4:
16 x 16 SIGNED
MULTIPLY ROUTINE
(ARG1L • ARG2L)
MOVF
ARG1L, W
MULWF
ARG2L
; ARG1L * ARG2L ->
; PRODH:PRODL
;
;
EXAMPLE 8-3:
16 x 16 UNSIGNED
MULTIPLY ROUTINE
MOVFF
MOVFF
PRODH, RES1
PRODL, RES0
MOVF
ARG1L, W
MULWF
ARG2L
; ARG1L * ARG2L->
; PRODH:PRODL
;
;
;
;
MOVF
MULWF
ARG1H, W
ARG2H
MOVFF
MOVFF
PRODH, RES1
PRODL, RES0
; ARG1H * ARG2H ->
; PRODH:PRODL
;
;
;
;
MOVFF
MOVFF
PRODH, RES3
PRODL, RES2
MOVF
MULWF
ARG1H, W
ARG2H
; ARG1H * ARG2H->
; PRODH:PRODL
;
;
MOVF
MULWF
ARG1L,W
ARG2H
MOVFF
MOVFF
PRODH, RES3
PRODL, RES2
; ARG1L * ARG2H ->
; PRODH:PRODL
;
; Add cross
; products
;
;
;
MOVF
ADDWF
MOVF
ADDWFC RES2, F
CLRF WREG
ADDWFC RES3, F
PRODL, W
RES1, F
PRODH, W
MOVF
MULWF
ARG1L, W
ARG2H
; ARG1L * ARG2H->
; PRODH:PRODL
;
; Add cross
; products
;
;
;
MOVF
ADDWF
MOVF
PRODL, W
RES1, F
PRODH, W
;
ADDWFC RES2, F
CLRF WREG
ADDWFC RES3, F
MOVF
MULWF
ARG1H, W
ARG2L
;
; ARG1H * ARG2L ->
; PRODH:PRODL
;
; Add cross
; products
;
;
;
;
MOVF
ADDWF
MOVF
ADDWFC RES2, F
CLRF WREG
ADDWFC RES3, F
PRODL, W
RES1, F
PRODH, W
MOVF
MULWF
ARG1H, W
ARG2L
;
; ARG1H * ARG2L->
; PRODH:PRODL
;
; Add cross
; products
MOVF
ADDWF
MOVF
PRODL, W
RES1, F
PRODH, W
;
;
ADDWFC RES2, F
CLRF WREG
ADDWFC RES3, F
;
;
;
BTFSS
BRA
MOVF
SUBWF
MOVF
ARG2H, 7
SIGN_ARG1
ARG1L, W
RES2
; ARG2H:ARG2L neg?
; no, check ARG1
;
;
;
Example 8-4 shows the sequence to do a 16 x 16
signed multiply. Equation 8-2 shows the algorithm
used. The 32-bit result is stored in four registers
(RES3:RES0). To account for the signed bits of the
arguments, the MSb for each argument pair is tested
and the appropriate subtractions are done.
ARG1H, W
SUBWFB RES3
SIGN_ARG1
BTFSS
BRA
ARG1H, 7
CONT_CODE
ARG2L, W
RES2
; ARG1H:ARG1L neg?
; no, done
;
;
;
MOVF
SUBWF
MOVF
ARG2H, W
SUBWFB RES3
;
CONT_CODE
:
DS39761B-page 112
Preliminary
© 2007 Microchip Technology Inc.
PIC18F2682/2685/4682/4685
When the IPEN bit is cleared (default state), the
interrupt priority feature is disabled and interrupts are
9.0
INTERRUPTS
compatible with PIC® mid-range devices. In
Compatibility mode, the interrupt priority bits for each
source have no effect. INTCON<6> is the PEIE bit,
which enables/disables all peripheral interrupt sources.
INTCON<7> is the GIE bit, which enables/disables all
interrupt sources. All interrupts branch to address
000008h in Compatibility mode.
The PIC18F2682/2685/4682/4685 devices have multiple
interrupt sources and an interrupt priority feature that
allows each interrupt source to be assigned a high priority
level or a low priority level. The high priority interrupt
vector is at 000008h and the low priority interrupt vector
is at 000018h. High priority interrupt events will interrupt
any low priority interrupts that may be in progress.
There are ten registers which are used to control
interrupt operation. These registers are:
When an interrupt is responded to, the global interrupt
enable bit is cleared to disable further interrupts. If the
IPEN bit is cleared, this is the GIE bit. If interrupt priority
levels are used, this will be either the GIEH or GIEL bit.
High priority interrupt sources can interrupt a low
priority interrupt. Low priority interrupts are not
processed while high priority interrupts are in progress.
• RCON
• INTCON
• INTCON2
• INTCON3
• PIR1, PIR2, PIR3
• PIE1, PIE2, PIE3
• IPR1, IPR2, IPR3
The return address is pushed onto the stack and the
PC is loaded with the interrupt vector address
(000008h or 000018h). Once in the Interrupt Service
Routine, the source(s) of the interrupt can be deter-
mined by polling the interrupt flag bits. The interrupt
flag bits must be cleared in software before re-enabling
interrupts to avoid recursive interrupts.
It is recommended that the Microchip header files
supplied with MPLAB® IDE be used for the symbolic bit
names in these registers. This allows the assembler/
compiler to automatically take care of the placement of
these bits within the specified register.
The “return from interrupt” instruction, RETFIE, exits
the interrupt routine and sets the GIE bit (GIEH or GIEL
if priority levels are used), which re-enables interrupts.
Each interrupt source has three bits to control its
operation. The functions of these bits are:
For external interrupt events, such as the INT pins or
the PORTB input change interrupt, the interrupt latency
will be three to four instruction cycles. The exact
latency is the same for one or two-cycle instructions.
Individual interrupt flag bits are set, regardless of the
status of their corresponding enable bit or the GIE bit.
• Flag bit to indicate that an interrupt event
occurred
• Enable bit that allows program execution to
branch to the interrupt vector address when the
flag bit is set
• Priority bit to select high priority or low priority
Note:
Do not use the MOVFFinstruction to modify
any of the interrupt control registers while
any interrupt is enabled. Doing so may
cause erratic microcontroller behavior.
The interrupt priority feature is enabled by setting the
IPEN bit (RCON<7>). When interrupt priority is
enabled, there are two bits which enable interrupts
globally. Setting the GIEH bit (INTCON<7>) enables all
interrupts that have the priority bit set (high priority).
Setting the GIEL bit (INTCON<6>) enables all
interrupts that have the priority bit cleared (low priority).
When the interrupt flag, enable bit and appropriate
global interrupt enable bit are set, the interrupt will
vector immediately to address 000008h or 000018h,
depending on the priority bit setting. Individual
interrupts can be disabled through their corresponding
enable bits.
© 2007 Microchip Technology Inc.
Preliminary
DS39761B-page 113
PIC18F2682/2685/4682/4685
FIGURE 9-1:
INTERRUPT LOGIC
Wake-up if in Sleep Mode
TMR0IF
TMR0IE
TMR0IP
RBIF
RBIE
RBIP
INT0IF
INT0IE
INT1IF
INT1IE
INT1IP
Interrupt to CPU
Vector to Location
0008h
Peripheral Interrupt Flag bit
Peripheral Interrupt Enable bit
Peripheral Interrupt Priority bit
INT2IF
INT2IE
INT2IP
GIE/GIEH
TMR1IF
TMR1IE
TMR1IP
IPEN
XXXXIF
XXXXIE
XXXXIP
IPEN
PEIE/GIEL
IPEN
Additional Peripheral Interrupts
High Priority Interrupt Generation
Low Priority Interrupt Generation
Peripheral Interrupt Flag bit
Peripheral Interrupt Enable bit
Peripheral Interrupt Priority bit
Interrupt to CPU
Vector to Location
0018h
TMR0IF
TMR0IE
TMR0IP
TMR1IF
TMR1IE
TMR1IP
RBIF
RBIE
XXXXIF
XXXXIE
XXXXIP
RBIP
PEIE/GIEL
GIE/GEIH
INT1IF
INT1IE
INT1IP
Additional Peripheral Interrupts
INT2IF
INT2IE
INT2IP
DS39761B-page 114
Preliminary
© 2007 Microchip Technology Inc.
PIC18F2682/2685/4682/4685
9.1
INTCON Registers
Note:
Interrupt flag bits are set when an interrupt
condition occurs regardless of the state of
its corresponding enable bit or the global
interrupt enable bit. User software should
ensure the appropriate interrupt flag bits
are clear prior to enabling an interrupt.
This feature allows for software polling.
The INTCON registers are readable and writable
registers, which contain various enable, priority and
flag bits.
REGISTER 9-1:
INTCON: INTERRUPT CONTROL REGISTER
R/W-0
GIE/GIEH
bit 7
R/W-0
R/W-0
R/W-0
R/W-0
RBIE
R/W-0
R/W-0
INT0IF
R/W-x
RBIF(1)
PEIE/GIEL
TMR0IE
INT0IE
TMR0IF
bit 0
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
-n = Value at POR
bit 7
GIE/GIEH: Global Interrupt Enable bit
When IPEN = 0:
1= Enables all unmasked interrupts
0= Disables all interrupts
When IPEN = 1:
1= Enables all high priority interrupts
0= Disables all high priority interrupts
bit 6
PEIE/GIEL: Peripheral Interrupt Enable bit
When IPEN = 0:
1= Enables all unmasked peripheral interrupts
0= Disables all peripheral interrupts
When IPEN = 1:
1= Enables all low priority peripheral interrupts
0= Disables all low priority peripheral interrupts
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
TMR0IE: TMR0 Overflow Interrupt Enable bit
1= Enables the TMR0 overflow interrupt
0= Disables the TMR0 overflow interrupt
INT0IE: INT0 External Interrupt Enable bit
1= Enables the INT0 external interrupt
0= Disables the INT0 external interrupt
RBIE: RB Port Change Interrupt Enable bit
1= Enables the RB port change interrupt
0= Disables the RB port change interrupt
TMR0IF: TMR0 Overflow Interrupt Flag bit
1= TMR0 register has overflowed (must be cleared in software)
0= TMR0 register did not overflow
INT0IF: INT0 External Interrupt Flag bit
1= The INT0 external interrupt occurred (must be cleared in software)
0= The INT0 external interrupt did not occur
RBIF: RB Port Change Interrupt Flag bit(1)
1= At least one of the RB7:RB4 pins changed state (must be cleared in software)
0= None of the RB7:RB4 pins have changed state
Note 1: A mismatch condition will continue to set this bit. Reading PORTB will end the mismatch condition and
allow the bit to be cleared.
© 2007 Microchip Technology Inc.
Preliminary
DS39761B-page 115
PIC18F2682/2685/4682/4685
REGISTER 9-2:
INTCON2: INTERRUPT CONTROL REGISTER 2
R/W-1
RBPU
R/W-1
R/W-1
R/W-1
U-0
—
R/W-1
U-0
—
R/W-1
RBIP
INTEDG0
INTEDG1
INTEDG2
TMR0IP
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
-n = Value at POR
bit 7
bit 6
bit 5
bit 4
RBPU: PORTB Pull-up Enable bit
1= All PORTB pull-ups are disabled
0= PORTB pull-ups are enabled by individual port latch values
INTEDG0: External Interrupt 0 Edge Select bit
1= Interrupt on rising edge
0= Interrupt on falling edge
INTEDG1: External Interrupt 1 Edge Select bit
1= Interrupt on rising edge
0= Interrupt on falling edge
INTEDG2: External Interrupt 2 Edge Select bit
1= Interrupt on rising edge
0= Interrupt on falling edge
bit 3
bit 2
Unimplemented: Read as ‘0’
TMR0IP: TMR0 Overflow Interrupt Priority bit
1= High priority
0= Low priority
bit 1
bit 0
Unimplemented: Read as ‘0’
RBIP: RB Port Change Interrupt Priority bit
1= High priority
0= Low priority
Note:
Interrupt flag bits are set when an interrupt condition occurs regardless of the state of its corresponding
enable bit or the global interrupt enable bit. User software should ensure the appropriate interrupt flag bits
are clear prior to enabling an interrupt. This feature allows for software polling.
DS39761B-page 116
Preliminary
© 2007 Microchip Technology Inc.
PIC18F2682/2685/4682/4685
REGISTER 9-3:
INTCON3: INTERRUPT CONTROL REGISTER 3
R/W-1
INT2IP
bit 7
R/W-1
U-0
—
R/W-0
R/W-0
U-0
—
R/W-0
INT2IF
R/W-0
INT1IF
INT1IP
INT2IE
INT1IE
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7
bit 6
INT2IP: INT2 External Interrupt Priority bit
1= High priority
0= Low priority
INT1IP: INT1 External Interrupt Priority bit
1= High priority
0= Low priority
bit 5
bit 4
Unimplemented: Read as ‘0’
INT2IE: INT2 External Interrupt Enable bit
1= Enables the INT2 external interrupt
0= Disables the INT2 external interrupt
bit 3
INT1IE: INT1 External Interrupt Enable bit
1= Enables the INT1 external interrupt
0= Disables the INT1 external interrupt
bit 2
bit 1
Unimplemented: Read as ‘0’
INT2IF: INT2 External Interrupt Flag bit
1= The INT2 external interrupt occurred (must be cleared in software)
0= The INT2 external interrupt did not occur
bit 0
INT1IF: INT1 External Interrupt Flag bit
1= The INT1 external interrupt occurred (must be cleared in software)
0= The INT1 external interrupt did not occur
Note:
Interrupt flag bits are set when an interrupt condition occurs regardless of the state of its corresponding
enable bit or the global interrupt enable bit. User software should ensure the appropriate interrupt flag bits
are clear prior to enabling an interrupt. This feature allows for software polling.
© 2007 Microchip Technology Inc.
Preliminary
DS39761B-page 117
PIC18F2682/2685/4682/4685
9.2
PIR Registers
Note 1: Interrupt flag bits are set when an interrupt
condition occurs regardless of the state of
its corresponding enable bit or the global
interrupt enable bit, GIE (INTCON<7>).
The PIR registers contain the individual flag bits for the
peripheral interrupts. Due to the number of peripheral
interrupt sources, there are two Peripheral Interrupt
Request (Flag) registers (PIR1, PIR2).
2: User software should ensure the appropri-
ate interrupt flag bits are cleared prior to
enabling an interrupt and after servicing
that interrupt.
REGISTER 9-4:
PIR1: PERIPHERAL INTERRUPT REQUEST (FLAG) REGISTER 1
R/W-0
PSPIF(1)
bit 7
R/W-0
ADIF
R-0
R-0
R/W-0
SSPIF
R/W-0
R/W-0
R/W-0
RCIF
TXIF
CCP1IF
TMR2IF
TMR1IF
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
PSPIF: Parallel Slave Port Read/Write Interrupt Flag bit(1)
1= A read or a write operation has taken place (must be cleared in software)
0= No read or write has occurred
ADIF: A/D Converter Interrupt Flag bit
1= An A/D conversion completed (must be cleared in software)
0= The A/D conversion is not complete
RCIF: EUSART Receive Interrupt Flag bit
1= The EUSART receive buffer, RCREG, is full (cleared when RCREG is read)
0= The EUSART receive buffer is empty
TXIF: EUSART Transmit Interrupt Flag bit
1= The EUSART transmit buffer, TXREG, is empty (cleared when TXREG is written)
0= The EUSART transmit buffer is full
SSPIF: Master Synchronous Serial Port Interrupt Flag bit
1= The transmission/reception is complete (must be cleared in software)
0= Waiting to transmit/receive
CCP1IF: CCP1 Interrupt Flag bit
Capture mode:
1= A TMR1 register capture occurred (must be cleared in software)
0= No TMR1 register capture occurred
Compare mode:
1= A TMR1 register compare match occurred (must be cleared in software)
0= No TMR1 register compare match occurred
PWM mode:
Unused in this mode.
bit 1
bit 0
TMR2IF: TMR2 to PR2 Match Interrupt Flag bit
1= TMR2 to PR2 match occurred (must be cleared in software)
0= No TMR2 to PR2 match occurred
TMR1IF: TMR1 Overflow Interrupt Flag bit
1= TMR1 register overflowed (must be cleared in software)
0= TMR1 register did not overflow
Note 1: This bit is reserved on PIC18F2682/2685 devices; always maintain this bit clear.
DS39761B-page 118
Preliminary
© 2007 Microchip Technology Inc.
PIC18F2682/2685/4682/4685
REGISTER 9-5:
PIR2: PERIPHERAL INTERRUPT REQUEST (FLAG) REGISTER 2
R/W-0
OSCFIF
bit 7
R/W-0
CMIF(1)
U-0
—
R/W-0
EEIF
R/W-0
BCLIF
R/W-0
R/W-0
R/W-0
ECCP1IF(1)
bit 0
HLVDIF
TMR3IF
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7
bit 6
OSCFIF: Oscillator Fail Interrupt Flag bit
1= Device oscillator failed, clock input has changed to INTOSC (must be cleared in software)
0= Device clock operating
CMIF: Comparator Interrupt Flag bit(1)
1= Comparator input has changed (must be cleared in software)
0= Comparator input has not changed
bit 5
bit 4
Unimplemented: Read as ‘0’
EEIF: Data EEPROM/Flash Write Operation Interrupt Flag bit
1= The write operation is complete (must be cleared in software)
0= The write operation is not complete or has not been started
bit 3
bit 2
bit 1
bit 0
BCLIF: Bus Collision Interrupt Flag bit
1= A bus collision occurred (must be cleared in software)
0= No bus collision occurred
HLVDIF: High/Low-Voltage Detect Interrupt Flag bit
1= A high/low-voltage condition occurred (must be cleared in software)
0= The device voltage is above the High/Low-Voltage Detect trip point
TMR3IF: TMR3 Overflow Interrupt Flag bit
1= TMR3 register overflowed (must be cleared in software)
0= TMR3 register did not overflow
ECCP1IF: ECCP1 Interrupt Flag bit(1)
Capture mode:
1= A TMR1 register capture occurred (must be cleared in software)
0= No TMR1 register capture occurred
Compare mode:
1= A TMR1 register compare match occurred (must be cleared in software)
0= No TMR1 register compare match occurred
PWM mode:
Unused in this mode.
Note 1: These bits are available in PIC18F4682/4685 and reserved in PIC18F2682/2685 devices.
© 2007 Microchip Technology Inc.
Preliminary
DS39761B-page 119
PIC18F2682/2685/4682/4685
REGISTER 9-6:
PIR3: PERIPHERAL INTERRUPT REQUEST (FLAG) REGISTER 3
R/W-0
R/W-0
R/W-0
ERRIF
R/W-0
R/W-0
TXB1IF(1) TXB0IF(1)
R/W-0
R/W-0
R/W-0
Mode 0
IRXIF
WAKIF
TXB2IF
RXB1IF
RXB0IF
R/W-0
IRXIF
R/W-0
R/W-0
ERRIF
R/W-0
R/W-0
TXB1IF(1) TXB0IF(1)
R/W-0
R/W-0
R/W-0
Mode 1,2
WAKIF
TXBnIF
RXBnIF
FIFOWMIF
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7
bit 6
bit 5
bit 4
IRXIF: CAN Invalid Received Message Interrupt Flag bit
1= An invalid message has occurred on the CAN bus
0= No invalid message on CAN bus
WAKIF: CAN bus Activity Wake-up Interrupt Flag bit
1= Activity on CAN bus has occurred
0= No activity on CAN bus
ERRIF: CAN bus Error Interrupt Flag bit
1= An error has occurred in the CAN module (multiple sources)
0= No CAN module errors
When CAN is in Mode 0:
TXB2IF: CAN Transmit Buffer 2 Interrupt Flag bit
1= Transmit Buffer 2 has completed transmission of a message and may be reloaded
0= Transmit Buffer 2 has not completed transmission of a message
When CAN is in Mode 1 or 2:
TXBnIF: Any Transmit Buffer Interrupt Flag bit
1= One or more transmit buffers have completed transmission of a message and may be reloaded
0= No transmit buffer is ready for reload
bit 3
bit 2
bit 1
TXB1IF: CAN Transmit Buffer 1 Interrupt Flag bit(1)
1= Transmit Buffer 1 has completed transmission of a message and may be reloaded
0= Transmit Buffer 1 has not completed transmission of a message
TXB0IF: CAN Transmit Buffer 0 Interrupt Flag bit(1)
1= Transmit Buffer 0 has completed transmission of a message and may be reloaded
0= Transmit Buffer 0 has not completed transmission of a message
When CAN is in Mode 0:
RXB1IF: CAN Receive Buffer 1 Interrupt Flag bit
1= Receive Buffer 1 has received a new message
0= Receive Buffer 1 has not received a new message
When CAN is in Mode 1 or 2:
RXBnIF: Any Receive Buffer Interrupt Flag bit
1= One or more receive buffers has received a new message
0= No receive buffer has received a new message
bit 0
When CAN is in Mode 0:
RXB0IF: CAN Receive Buffer 0 Interrupt Flag bit
1= Receive Buffer 0 has received a new message
0= Receive Buffer 0 has not received a new message
When CAN is in Mode 1:
Unimplemented: Read as ‘0’
When CAN is in Mode 2:
FIFOWMIF: FIFO Watermark Interrupt Flag bit
1= FIFO high watermark is reached
0= FIFO high watermark is not reached
Note 1: In CAN Mode 1 and 2, these bits are forced to ‘0’.
DS39761B-page 120
Preliminary
© 2007 Microchip Technology Inc.
PIC18F2682/2685/4682/4685
9.3
PIE Registers
The PIE registers contain the individual enable bits for
the peripheral interrupts. Due to the number of
peripheral interrupt sources, there are two Peripheral
Interrupt Enable registers (PIE1, PIE2). When IPEN = 0,
the PEIE bit must be set to enable any of these
peripheral interrupts.
REGISTER 9-7:
PIE1: PERIPHERAL INTERRUPT ENABLE REGISTER 1
R/W-0
PSPIE(1)
bit 7
R/W-0
ADIE
R/W-0
RCIE
R/W-0
TXIE
R/W-0
SSPIE
R/W-0
R/W-0
R/W-0
CCP1IE
TMR2IE
TMR1IE
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
PSPIE: Parallel Slave Port Read/Write Interrupt Enable bit(1)
1= Enables the PSP read/write interrupt
0= Disables the PSP read/write interrupt
ADIE: A/D Converter Interrupt Enable bit
1= Enables the A/D interrupt
0= Disables the A/D interrupt
RCIE: EUSART Receive Interrupt Enable bit
1= Enables the EUSART receive interrupt
0= Disables the EUSART receive interrupt
TXIE: EUSART Transmit Interrupt Enable bit
1= Enables the EUSART transmit interrupt
0= Disables the EUSART transmit interrupt
SSPIE: Master Synchronous Serial Port Interrupt Enable bit
1= Enables the MSSP interrupt
0= Disables the MSSP interrupt
CCP1IE: CCP1 Interrupt Enable bit
1= Enables the CCP1 interrupt
0= Disables the CCP1 interrupt
TMR2IE: TMR2 to PR2 Match Interrupt Enable bit
1= Enables the TMR2 to PR2 match interrupt
0= Disables the TMR2 to PR2 match interrupt
TMR1IE: TMR1 Overflow Interrupt Enable bit
1= Enables the TMR1 overflow interrupt
0= Disables the TMR1 overflow interrupt
Note 1: This bit is reserved on PIC18F2682/2685 devices; always maintain this bit clear.
© 2007 Microchip Technology Inc.
Preliminary
DS39761B-page 121
PIC18F2682/2685/4682/4685
REGISTER 9-8:
PIE2: PERIPHERAL INTERRUPT ENABLE REGISTER 2
R/W-0
OSCFIE
bit 7
R/W-0
CMIE(1)
U-0
—
R/W-0
EEIE
R/W-0
BCLIE
R/W-0
R/W-0
R/W-0
ECCP1IE(1)
bit 0
HLVDIE
TMR3IE
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7
bit 6
OSCFIE: Oscillator Fail Interrupt Enable bit
1= Enabled
0= Disabled
CMIE: Comparator Interrupt Enable bit(1)
1= Enabled
0= Disabled
bit 5
bit 4
Unimplemented: Read as ‘0’
EEIE: Data EEPROM/Flash Write Operation Interrupt Enable bit
1= Enabled
0= Disabled
bit 3
bit 2
bit 1
bit 0
BCLIE: Bus Collision Interrupt Enable bit
1= Enabled
0= Disabled
HLVDIE: High/Low-Voltage Detect Interrupt Enable bit
1= Enabled
0= Disabled
TMR3IE: TMR3 Overflow Interrupt Enable bit
1= Enabled
0= Disabled
ECCP1IE: ECCP1 Interrupt Enable bit(1)
1= Enabled
0= Disabled
Note 1: These bits are available on PIC18F4682/4685 devices only.
DS39761B-page 122
Preliminary
© 2007 Microchip Technology Inc.
PIC18F2682/2685/4682/4685
REGISTER 9-9:
PIE3: PERIPHERAL INTERRUPT ENABLE REGISTER 3
R/W-0
R/W-0
R/W-0
ERRIE
R/W-0
R/W-0
TXB1IE(1) TXB0IE(1)
R/W-0
R/W-0
R/W-0
Mode 0
IRXIE
WAKIE
TXB2IE
RXB1IE
RXB0IE
R/W-0
IRXIE
R/W-0
R/W-0
ERRIE
R/W-0
R/W-0
TXB1IE(1) TXB0IE(1)
R/W-0
R/W-0
R/W-0
FIFOWMIE
bit 0
Mode 1
WAKIE
TXBnIE
RXBnIE
bit 7
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7
bit 6
bit 5
bit 4
IRXIE: CAN Invalid Received Message Interrupt Enable bit
1= Enable invalid message received interrupt
0= Disable invalid message received interrupt
WAKIE: CAN bus Activity Wake-up Interrupt Enable bit
1= Enable bus activity wake-up interrupt
0= Disable bus activity wake-up interrupt
ERRIE: CAN bus Error Interrupt Enable bit
1= Enable CAN bus error interrupt
0= Disable CAN bus error interrupt
When CAN is in Mode 0:
TXB2IE: CAN Transmit Buffer 2 Interrupt Enable bit
1= Enable Transmit Buffer 2 interrupt
0= Disable Transmit Buffer 2 interrupt
When CAN is in Mode 1 or 2:
TXBnIE: CAN Transmit Buffer Interrupts Enable bit
1= Enable transmit buffer interrupt; individual interrupt is enabled by TXBIE and BIE0
0= Disable all transmit buffer interrupts
bit 3
bit 2
bit 1
TXB1IE: CAN Transmit Buffer 1 Interrupt Enable bit(1)
1= Enable Transmit Buffer 1 interrupt
0= Disable Transmit Buffer 1 interrupt
TXB0IE: CAN Transmit Buffer 0 Interrupt Enable bit(1)
1= Enable Transmit Buffer 0 interrupt
0= Disable Transmit Buffer 0 interrupt
When CAN is in Mode 0:
RXB1IE: CAN Receive Buffer 1 Interrupt Enable bit
1= Enable Receive Buffer 1 interrupt
0= Disable Receive Buffer 1 interrupt
When CAN is in Mode 1 or 2:
RXBnIE: CAN Receive Buffer Interrupts Enable bit
1= Enable receive buffer interrupt; individual interrupt is enabled by BIE0
0= Disable all receive buffer interrupts
bit 0
When CAN is in Mode 0:
RXB0IE: CAN Receive Buffer 0 Interrupt Enable bit
1= Enable Receive Buffer 0 interrupt
0= Disable Receive Buffer 0 interrupt
When CAN is in Mode 1:
Unimplemented: Read as ‘0’
When CAN is in Mode 2:
FIFOWMIE: FIFO Watermark Interrupt Enable bit
1= Enable FIFO watermark interrupt
0= Disable FIFO watermark interrupt
Note 1: In CAN Mode 1 and 2, these bits are forced to ‘0’.
© 2007 Microchip Technology Inc.
Preliminary
DS39761B-page 123
PIC18F2682/2685/4682/4685
9.4
IPR Registers
The IPR registers contain the individual priority bits for
the peripheral interrupts. Due to the number of
peripheral interrupt sources, there are two Peripheral
Interrupt Priority registers (IPR1, IPR2). Using the
priority bits requires that the Interrupt Priority Enable
(IPEN) bit be set.
REGISTER 9-10: IPR1: PERIPHERAL INTERRUPT PRIORITY REGISTER 1
R/W-1
PSPIP(1)
R/W-1
ADIP
R/W-1
RCIP
R/W-1
TXIP
R/W-1
SSPIP
R/W-1
R/W-1
R/W-1
CCP1IP
TMR2IP
TMR1IP
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7
bit 6
bit 5
bit 4
PSPIP: Parallel Slave Port Read/Write Interrupt Priority bit(1)
1= High priority
0= Low priority
ADIP: A/D Converter Interrupt Priority bit
1= High priority
0= Low priority
RCIP: EUSART Receive Interrupt Priority bit
1= High priority
0= Low priority
TXIP: EUSART Transmit Interrupt Priority bit
1= High priority
0= Low priority
bit 3
bit 2
bit 1
bit 0
SSPIP: Master Synchronous Serial Port Interrupt Priority bit
1= High priority
0= Low priority
CCP1IP: CCP1 Interrupt Priority bit
1= High priority
0= Low priority
TMR2IP: TMR2 to PR2 Match Interrupt Priority bit
1= High priority
0= Low priority
TMR1IP: TMR1 Overflow Interrupt Priority bit
1= High priority
0= Low priority
Note 1: This bit is reserved on PIC18F2682/2685 devices; always maintain this bit clear.
DS39761B-page 124
Preliminary
© 2007 Microchip Technology Inc.
PIC18F2682/2685/4682/4685
REGISTER 9-11: IPR2: PERIPHERAL INTERRUPT PRIORITY REGISTER 2
R/W-1
R/W-1
CMIP(1)
U-0
—
R/W-1
EEIP
R/W-1
BCLIP
R/W-1
R/W-1
R/W-1
ECCP1IP(1)
bit 0
OSCFIP
HLVDIP
TMR3IP
bit 7
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7
bit 6
OSCFIP: Oscillator Fail Interrupt Priority bit
1= High priority
0= Low priority
CMIP: Comparator Interrupt Priority bit(1)
1= High priority
0= Low priority
bit 5
bit 4
Unimplemented: Read as ‘0’
EEIP: Data EEPROM/Flash Write Operation Interrupt Priority bit
1= High priority
0= Low priority
bit 3
bit 2
bit 1
bit 0
BCLIP: Bus Collision Interrupt Priority bit
1= High priority
0= Low priority
HLVDIP: High/Low-Voltage Detect Interrupt Priority bit
1= High priority
0= Low priority
TMR3IP: TMR3 Overflow Interrupt Priority bit
1= High priority
0= Low priority
ECCP1IP: ECCP1 Interrupt Priority bit(1)
1= High priority
0= Low priority
Note 1: These bits are available on PIC18F4682/4685 devices only.
© 2007 Microchip Technology Inc.
Preliminary
DS39761B-page 125
PIC18F2682/2685/4682/4685
REGISTER 9-12: IPR3: PERIPHERAL INTERRUPT PRIORITY REGISTER 3
R/W-1
IRXIP
R/W-1
R/W-1
ERRIP
R/W-1
R/W-1
TXB1IP(1) TXB0IP(1)
R/W-1
R/W-1
R/W-1
Mode 0
WAKIP
TXB2IP
RXB1IP
RXB0IP
R/W-1
IRXIP
R/W-1
R/W-1
ERRIP
R/W-1
R/W-1
TXB1IP(1) TXB0IP(1)
R/W-1
R/W-1
R/W-1
FIFOWMIP
bit 0
Mode 1,2
WAKIP
TXBnIP
RXBnIP
bit 7
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7
bit 6
bit 5
bit 4
IRXIP: CAN Invalid Received Message Interrupt Priority bit
1= High priority
0= Low priority
WAKIP: CAN bus Activity Wake-up Interrupt Priority bit
1= High priority
0= Low priority
ERRIP: CAN bus Error Interrupt Priority bit
1= High priority
0= Low priority
When CAN is in Mode 0:
TXB2IP: CAN Transmit Buffer 2 Interrupt Priority bit
1= High priority
0= Low priority
When CAN is in Mode 1 or 2:
TXBnIP: CAN Transmit Buffer Interrupt Priority bit
1= High priority
0= Low priority
bit 3
bit 2
bit 1
TXB1IP: CAN Transmit Buffer 1 Interrupt Priority bit(1)
1= High priority
0= Low priority
TXB0IP: CAN Transmit Buffer 0 Interrupt Priority bit(1)
1= High priority
0= Low priority
When CAN is in Mode 0:
RXB1IP: CAN Receive Buffer 1 Interrupt Priority bit
1= High priority
0= Low priority
When CAN is in Mode 1 or 2:
RXBnIP: CAN Receive Buffer Interrupts Priority bit
1= High priority
0= Low priority
bit 0
When CAN is in Mode 0:
RXB0IP: CAN Receive Buffer 0 Interrupt Priority bit
1= High priority
0= Low priority
When CAN is in Mode 1:
Unimplemented: Read as ‘0’
When CAN is in Mode 2:
FIFOWMIP: FIFO Watermark Interrupt Priority bit
1= High priority
0= Low priority
Note 1: In CAN Mode 1 and 2, these bits are forced to ‘0’.
DS39761B-page 126
Preliminary
© 2007 Microchip Technology Inc.
PIC18F2682/2685/4682/4685
9.5
RCON Register
The RCON register contains flag bits which are used to
determine the cause of the last Reset or wake-up from
Idle or Sleep modes. RCON also contains the IPEN bit
which enables interrupt priorities.
REGISTER 9-13: RCON: RESET CONTROL REGISTER
R/W-0
IPEN
R/W-1(1)
U-0
—
R/W-1
RI
R-1
TO
R-1
PD
R/W-0(2)
POR
R/W-0
BOR
SBOREN
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
-n = Value at POR
bit 7
bit 6
IPEN: Interrupt Priority Enable bit
1= Enable priority levels on interrupts
0= Disable priority levels on interrupts (PIC16CXXX Compatibility mode)
SBOREN: BOR Software Enable bit(1)
For details of bit operation, see Register 4-1.
Unimplemented: Read as ‘0’
bit 5
bit 4
RI: RESETInstruction Flag bit
For details of bit operation, see Register 4-1.
TO: Watchdog Time-out Flag bit
bit 3
bit 2
bit 1
bit 0
For details of bit operation, see Register 4-1.
PD: Power-Down Detection Flag bit
For details of bit operation, see Register 4-1.
POR: Power-on Reset Status bit(2)
For details of bit operation, see Register 4-1.
BOR: Brown-out Reset Status bit
For details of bit operation, see Register 4-1.
Note 1: If SBOREN is enabled, its Reset state is ‘1’; otherwise, it is ‘0’.
2: The actual Reset value of POR is determined by the type of device Reset. See Register 4-1 for additional
information.
© 2007 Microchip Technology Inc.
Preliminary
DS39761B-page 127
PIC18F2682/2685/4682/4685
9.6
INTx Pin Interrupts
9.7
TMR0 Interrupt
External interrupts on the RB0/INT0, RB1/INT1 and
RB2/INT2 pins are edge-triggered. If the corresponding
INTEDGx bit in the INTCON2 register is set (= 1), the
interrupt is triggered by a rising edge; if the bit is clear,
the trigger is on the falling edge. When a valid edge
appears on the RBx/INTx pin, the corresponding flag
bit, INTxIF, is set. This interrupt can be disabled by
clearing the corresponding enable bit INTxIE. Flag bit,
INTxIF, must be cleared in software in the Interrupt
Service Routine before re-enabling the interrupt.
In 8-bit mode (which is the default), an overflow in the
TMR0 register (FFh → 00h) will set flag bit TMR0IF. In
16-bit mode, an overflow in the TMR0H:TMR0L regis-
ter pair (FFFFh → 0000h) will set TMR0IF. The interrupt
can be enabled/disabled by setting/clearing enable bit
TMR0IE (INTCON<5>). Interrupt priority for Timer0 is
determined by the value contained in the interrupt
priority bit, TMR0IP (INTCON2<2>). See Section 11.0
“Timer0 Module” for further details on the Timer0
module.
All external interrupts (INT0, INT1 and INT2) can
wake-up the processor from the power-managed
modes if bit INTxIE was set prior to going into the
power-managed modes. If the Global Interrupt
Enable bit, GIE, is set, the processor will branch to
the interrupt vector following wake-up.
9.8
PORTB Interrupt-on-Change
An input change on PORTB<7:4> sets flag bit, RBIF
(INTCON<0>). The interrupt can be enabled/disabled
by setting/clearing enable bit, RBIE (INTCON<3>).
Interrupt priority for PORTB interrupt-on-change is
determined by the value contained in the interrupt
priority bit, RBIP (INTCON2<0>).
Interrupt priority for INT1 and INT2 is determined by the
value contained in the interrupt priority bits, INT1IP
(INTCON3<6>) and INT2IP (INTCON3<7>). There is
no priority bit associated with INT0. It is always a high
priority interrupt source.
9.9
Context Saving During Interrupts
During interrupts, the return PC address is saved on
the stack. Additionally, the WREG, STATUS and BSR
registers are saved on the fast return stack. If a fast
return from interrupt is not used (See Section 5.3
“Data Memory Organization”), the user may need to
save the WREG, STATUS and BSR registers on entry
to the Interrupt Service Routine. Depending on the
user’s application, other registers may also need to be
saved. Example 9-1 saves and restores the WREG,
STATUS and BSR registers during an Interrupt Service
Routine.
EXAMPLE 9-1:
SAVING STATUS, WREG AND BSR REGISTERS IN RAM
MOVWF
MOVFF
MOVFF
;
W_TEMP
STATUS, STATUS_TEMP
BSR, BSR_TEMP
; W_TEMP is in virtual bank
; STATUS_TEMP located anywhere
; BSR_TMEP located anywhere
; USER ISR CODE
;
MOVFF
MOVF
MOVFF
BSR_TEMP, BSR
W_TEMP, W
STATUS_TEMP, STATUS
; Restore BSR
; Restore WREG
; Restore STATUS
DS39761B-page 128
Preliminary
© 2007 Microchip Technology Inc.
PIC18F2682/2685/4682/4685
10.1 PORTA, TRISA and LATA Registers
10.0 I/O PORTS
PORTA is an 8-bit wide, bidirectional port. The
corresponding data direction register is TRISA. Setting
a TRISA bit (= 1) will make the corresponding PORTA
pin an input (i.e., put the corresponding output driver in
a high-impedance mode). Clearing a TRISA bit (= 0)
will make the corresponding PORTA pin an output (i.e.,
put the contents of the output latch on the selected pin).
Depending on the device selected and features
enabled, there are up to five ports available. Some pins
of the I/O ports are multiplexed with an alternate
function from the peripheral features on the device. In
general, when a peripheral is enabled, that pin may not
be used as a general purpose I/O pin.
Each port has three registers for its operation. These
registers are:
Reading the PORTA register reads the status of the
pins, whereas writing to it, will write to the port latch.
• TRIS register (data direction register)
The Data Latch register (LATA) is also memory
mapped. Read-modify-write operations on the LATA
register read and write the latched output value for
PORTA.
• PORT register (reads the levels on the pins of the
device)
• LAT register (output latch)
The Data Latch register (LAT) is useful for read-modify-
write operations on the value that the I/O pins are
driving.
The RA4 pin is multiplexed with the Timer0 module
clock input to become the RA4/T0CKI pin. Pins RA6
and RA7 are multiplexed with the main oscillator pins.
They are enabled as oscillator or I/O pins by the selec-
tion of the main oscillator in Configuration Register 1H
(see Section 24.1 “Configuration Bits” for details).
When they are not used as port pins, RA6 and RA7 and
their associated TRIS and LAT bits are read as ‘0’.
A simplified model of a generic I/O port, without the
interfaces to other peripherals, is shown in Figure 10-1.
FIGURE 10-1:
GENERIC I/O PORT
OPERATION
The other PORTA pins are multiplexed with analog
inputs, the analog VREF+ and VREF- inputs and the
comparator voltage reference output. The operation of
RA5 and RA3:RA0 pins as A/D converter inputs is
selected by clearing/setting the control bits in the
ADCON1 register (A/D Control Register 1).
RD LAT
Data
Bus
D
Q
I/O pin(1)
WR LAT
or PORT
CK
Data Latch
Note:
On a Power-on Reset, RA5 and RA3:RA0
are configured as analog inputs and read
as ‘0’. RA4 is configured as a digital input.
D
Q
All other PORTA pins have TTL input levels and full
CMOS output drivers.
WR TRIS
RD TRIS
CK
TRIS Latch
The TRISA register controls the direction of the RA
pins, even when they are being used as analog inputs.
The user must ensure the bits in the TRISA register are
maintained set when using them as analog inputs.
Input
Buffer
Q
D
EXAMPLE 10-1:
INITIALIZING PORTA
CLRF
PORTA
LATA
0Fh
; Initialize PORTA by
; clearing output
; data latches
; Alternate method
; to clear output
; data latches
EN
RD PORT
CLRF
Note 1: I/O pins have diode protection to VDD and VSS.
MOVLW
MOVWF
MOVWF
MOVWF
MOVLW
; Configure A/D
ADCON1 ; for digital inputs
07h
CMCON
0CFh
; Configure comparators
; for digital input
; Value used to
; initialize data
; direction
MOVWF
TRISA
; Set RA<3:0> as inputs
; RA<5:4> as outputs
© 2007 Microchip Technology Inc.
Preliminary
DS39761B-page 129
PIC18F2682/2685/4682/4685
TABLE 10-1: PORTA I/O SUMMARY
Pin Name
Function
I/O
TRIS Buffer
Description
RA0/AN0/CVREF
RA0
OUT
IN
0
1
1
DIG LATA<0> data output.
TTL PORTA<0> data input.
AN0
IN
ANA A/D input channel 0. Enabled on POR, this analog input overrides the
digital input (read as clear – low level).
(1)
CVREF
OUT
x
ANA Comparator voltage reference analog output. Enabling this analog
output overrides the digital I/O (read as clear – low level).
RA1/AN1
RA1
OUT
IN
0
1
1
DIG LATA<1> data output.
TTL PORTA<1> data input.
AN1
RA2
IN
ANA A/D input channel 1. Enabled on POR, this analog input overrides the
digital input (read as clear – low level).
RA2/AN2/VREF-
OUT
IN
0
1
1
DIG LATA<2> data output.
TTL PORTA<2> data input.
AN2
IN
ANA A/D input channel 2. Enabled on POR, this analog input overrides the
digital input (read as clear – low level).
VREF-
RA3
IN
OUT
IN
1
0
1
1
ANA A/D and comparator negative voltage analog input.
DIG LATA<3> data output.
RA3/AN3/VREF+
RA4/T0CKI
TTL PORTA<3> data input.
AN3
IN
ANA A/D input channel 3. Enabled on POR, this analog input overrides the
digital input (read as clear – low level).
VREF+
RA4
IN
OUT
IN
1
0
1
1
0
1
1
ANA A/D and comparator positive voltage analog input.
DIG LATA<4> data output.
TTL PORTA<4> data input.
T0CKI
IN
ST
Timer0 clock input.
RA5/AN4/SS/HLVDIN RA5
OUT
IN
DIG LATA<5> data output.
TTL PORTA<5> data input.
AN4
SS
IN
ANA A/D input channel 4. Enabled on POR, this analog input overrides the
digital input (read as clear – low level).
IN
IN
1
1
x
TTL Slave select input for MSSP.
HLVDIN
ANA High/Low-Voltage Detect external trip point input.
OSC2/CLKO/RA6
OSC1/CLKI/RA7
OSC2
CLKO
RA6
OUT
ANA Output connection, selected by FOSC3:FOSC0 Configuration bits.
Enabling OSC2 overrides digital I/O.
OUT
x
DIG Output connection, selected by FOSC3:FOSC0 Configuration bits.
Enabling CLKO overrides digital I/O (FOSC/4).
OUT
IN
0
1
x
DIG LATA<6> data output.
TTL PORTA<6> data input.
OSC1
CLKI
RA7
IN
ANA Main oscillator input connection, determined by FOSC3:FOSC0
Configuration bits. Enabling OSC1 overrides digital I/O.
IN
x
ANA Main clock input connection, determined by FOSC3:FOSC0
Configuration bits. Enabling CLKI overrides digital I/O.
OUT
IN
0
1
DIG LATA<7> data output.
TTL PORTA<7> data input.
Legend:
OUT = Output; IN = Input; ANA = Analog Signal; DIG = Digital Output; ST = Schmitt Buffer Input; TTL = TTL Buffer Input
Note 1: This bit is unimplemented on PIC18F2682/2685 devices.
DS39761B-page 130
Preliminary
© 2007 Microchip Technology Inc.
PIC18F2682/2685/4682/4685
TABLE 10-2: SUMMARY OF REGISTERS ASSOCIATED WITH PORTA
Reset
Values
on page
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PORTA
RA7(1)
RA6(1)
RA5
RA4
RA3
RA2
RA1
RA0
52
52
52
50
51
51
LATA
LATA7(1) LATA6(1) LATA Data Output Register
TRISA7(1) TRISA6(1) PORTA Data Direction Register
TRISA
ADCON1
CMCON(2)
CVRCON(2)
—
—
VCFG1
C2INV
CVRR
VCFG0
C1INV
PCFG3
CIS
PCFG2
CM2
PCFG1
CM1
PCFG0
CM0
C2OUT
CVREN
C1OUT
CVROE
CVRSS
CVR3
CVR2
CVR1
CVR0
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PORTA.
Note 1: RA7:RA6 and their associated latch and data direction bits are enabled as I/O pins based on oscillator
configuration; otherwise, they are read as ‘0’.
2: These registers are unimplemented on PIC18F2682/2685 devices.
© 2007 Microchip Technology Inc.
Preliminary
DS39761B-page 131
PIC18F2682/2685/4682/4685
10.2 PORTB, TRISB and LATB
Registers
Note:
On a Power-on Reset, RB4:RB0 are
configured as analog inputs by default and
read as ‘0’; RB7:RB5 are configured as
digital inputs.
PORTB is an 8-bit wide, bidirectional port. The
corresponding data direction register is TRISB. Setting
a TRISB bit (= 1) will make the corresponding PORTB
pin an input (i.e., put the corresponding output driver in
a high-impedance mode). Clearing a TRISB bit (= 0)
will make the corresponding PORTB pin an output (i.e.,
put the contents of the output latch on the selected pin).
By programming the Configuration bit,
PBADEN (CONFIG3H<1>), RB4:RB0 will
alternatively be configured as digital inputs
on POR.
Four of the PORTB pins (RB7:RB4) have an
interrupt-on-change feature. Only pins configured as
inputs can cause this interrupt to occur (i.e., any
RB7:RB4 pin configured as an output is excluded
from the interrupt-on-change comparison). The input
pins (of RB7:RB4) are compared with the old value
latched on the last read of PORTB. The “mismatch”
outputs of RB7:RB4 are ORed together to generate
the RB Port Change Interrupt with Flag bit, RBIF
(INTCON<0>).
The Data Latch register (LATB) is also memory
mapped. Read-modify-write operations on the LATB
register read and write the latched output value for
PORTB.
Pins RB2 through RB3 are multiplexed with the ECAN
peripheral. Refer to Section 23.0 “ECAN™ Technol-
ogy” for proper settings of TRISB when CAN is
enabled.
EXAMPLE 10-2:
INITIALIZING PORTB
; Initialize PORTB by
; clearing output
; data latches
; Alternate method
; to clear output
; data latches
This interrupt can wake the device from Sleep. The
user, in the Interrupt Service Routine, can clear the
interrupt in the following manner:
CLRF
PORTB
LATB
0Eh
a) Any read or write of PORTB (except with the
MOVFF (ANY), PORTB instruction). This will
end the mismatch condition.
CLRF
b) Clear flag bit, RBIF.
MOVLW
MOVWF
; Set RB<4:0> as
ADCON1 ; digital I/O pins
; (required if config bit
A mismatch condition will continue to set flag bit, RBIF.
Reading PORTB will end the mismatch condition and
allow flag bit RBIF to be cleared.
; PBADEN is set)
; Value used to
; initialize data
; direction
; Set RB<3:0> as inputs
; RB<5:4> as outputs
; RB<7:6> as inputs
MOVLW
MOVWF
0CFh
The interrupt-on-change feature is recommended for
wake-up on key depression operation and operations
where PORTB is only used for the interrupt-on-change
feature. Polling of PORTB is not recommended while
using the interrupt-on-change feature.
TRISB
Each of the PORTB pins has a weak internal pull-up. A
single control bit can turn on all the pull-ups. This is
performed by clearing bit RBPU (INTCON2<7>). The
weak pull-up is automatically turned off when the port
pin is configured as an output. The pull-ups are
disabled on all device Resets.
DS39761B-page 132
Preliminary
© 2007 Microchip Technology Inc.
PIC18F2682/2685/4682/4685
TABLE 10-3: PORTB I/O SUMMARY
Pin Name
Function
I/O
TRIS Buffer
Description
RB0/INT0/FLT0/AN10 RB0
OUT
IN
0
1
1
1
1
DIG
TTL
ST
LATB<0> data output.
PORTB<0> data input. Weak pull-up available only in this mode.
External interrupt 0 input.
INT0
FLT0
IN
(1)
IN
ST
Enhanced PWM Fault input.
AN10
IN
ANA A/D input channel 10. Enabled on POR, this analog input overrides
the digital input (read as clear – low level).
RB1/INT1/AN8
RB1
OUT
IN
0
1
1
1
DIG
TTL
ST
LATB<1> data output.
PORTB<1> data input. Weak pull-up available only in this mode.
External interrupt 1 input.
INT1
AN8
IN
IN
ANA A/D input channel 8. Enabled on POR, this analog input overrides
the digital input (read as clear – low level).
RB2/INT2/CANTX
RB2
OUT
IN
x
1
1
1
DIG
TTL
ST
LATB<2> data output.
PORTB<2> data input. Weak pull-up available only in this mode.
External interrupt 2 input.
INT2
IN
CANTX
OUT
DIG
CAN transmit signal output. The CAN interface overrides the
TRIS<2> control when enabled.
RB3/CANRX
RB3
OUT
IN
0
1
1
DIG
TTL
ST
LATB<3> data output.
PORTB<3> data input. Weak pull-up available only in this mode.
CANRX
RB4
IN
CAN receive signal input. Pin must be configured as a digital input by
setting TRISB<3>.
RB4/KBI0/AN9
OUT
IN
0
1
1
1
DIG
TTL
TTL
LATB<4> data output.
PORTB<4> data input. Weak pull-up available only in this mode.
Interrupt-on-pin change.
KBI0
AN9
IN
IN
ANA A/D input channel 9. Enabled on POR, this analog input overrides
the digital input (read as clear – low level).
RB5/KBI1/PGM
RB5
OUT
IN
0
1
1
x
DIG
TTL
TTL
ST
LATB<5> data output.
PORTB<5> data input. Weak pull-up available only in this mode.
Interrupt-on-pin change.
KBI1
PGM
IN
IN
Low-Voltage Programming mode entry (ICSP™). Enabling this
function overrides digital output.
RB6/KBI2/PGC
RB7/KBI3/PGD
RB6
OUT
IN
0
1
1
x
0
1
1
x
x
DIG
TTL
TTL
ST
LATB<6> data output.
PORTB<6> data input. Weak pull-up available only in this mode.
Interrupt-on-pin change.
KBI2
PGC
RB7
IN
IN
Low-Voltage Programming mode entry (ICSP) clock input.
LATB<7> data output.
OUT
IN
DIG
TTL
TTL
DIG
ST
PORTB<7> data input. Weak pull-up available only in this mode.
Interrupt-on-pin change.
KBI3
PGD
IN
OUT
IN
Low-Voltage Programming mode entry (ICSP) clock output.
Low-Voltage Programming mode entry (ICSP) clock input.
Legend:
OUT = Output; IN = Input; ANA = Analog Signal; DIG = Digital Output; ST = Schmitt Buffer Input; TTL – TTL Buffer Input
Note 1: This bit is unimplemented on PIC18F2682/2685 devices.
© 2007 Microchip Technology Inc.
Preliminary
DS39761B-page 133
PIC18F2682/2685/4682/4685
TABLE 10-4: SUMMARY OF REGISTERS ASSOCIATED WITH PORTB
Reset
Values
on page
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PORTB
RB7
RB6
RB5
RB4
RB3
RB2
RB1
RB0
52
52
52
49
49
49
50
LATB
LATB Data Output Register
TRISB
PORTB Data Direction Register
GIE/GIEH PEIE/GIEL TMR0IE
INTCON
INTCON2
INTCON3
ADCON1
INT0IE
RBIE
—
TMR0IF
TMR0IP
—
INT0IF
—
RBIF
RBIP
RBPU
INT2IP
—
INTEDG0 INTEDG1 INTEDG2
INT1IP
—
—
INT2IE
VCFG0
INT1IE
PCFG3
INT2IF
PCFG1
INT1IF
PCFG0
VCFG1
PCFG2
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PORTB.
DS39761B-page 134
Preliminary
© 2007 Microchip Technology Inc.
PIC18F2682/2685/4682/4685
10.3 PORTC, TRISC and LATC
Registers
Note:
On a Power-on Reset, these pins are
configured as digital inputs.
PORTC is an 8-bit wide, bidirectional port. The
corresponding data direction register is TRISC. Setting
a TRISC bit (= 1) will make the corresponding PORTC
pin an input (i.e., put the corresponding output driver in
a high-impedance mode). Clearing a TRISC bit (= 0)
will make the corresponding PORTC pin an output (i.e.,
put the contents of the output latch on the selected pin).
The contents of the TRISC register are affected by
peripheral overrides. Reading TRISC always returns
the current contents, even though a peripheral device
may be overriding one or more of the pins.
EXAMPLE 10-3:
INITIALIZING PORTC
CLRF
PORTC
; Initialize PORTC by
; clearing output
; data latches
The Data Latch register (LATC) is also memory
mapped. Read-modify-write operations on the LATC
register read and write the latched output value for
PORTC.
CLRF
LATC
; Alternate method
; to clear output
; data latches
PORTC is multiplexed with several peripheral functions
(Table 10-5). The pins have Schmitt Trigger input
buffers.
MOVLW
MOVWF
0CFh
; Value used to
; initialize data
; direction
; Set RC<3:0> as inputs
; RC<5:4> as outputs
; RC<7:6> as inputs
TRISC
When enabling peripheral functions, care should be
taken in defining TRIS bits for each PORTC pin. Some
peripherals override the TRIS bit to make a pin an output,
while other peripherals override the TRIS bit to make a
pin an input. The user should refer to the corresponding
peripheral section for the correct TRIS bit settings.
© 2007 Microchip Technology Inc.
Preliminary
DS39761B-page 135
PIC18F2682/2685/4682/4685
TABLE 10-5: PORTC I/O SUMMARY
Pin Name
Function
I/O
TRIS
Buffer
Description
RC0/T1OSO/ RC0
T13CKI
OUT
IN
0
1
x
1
0
1
x
0
1
0
1
0
1
0
DIG
ST
LATC<0> data output.
PORTC<0> data input.
T1OSO
OUT
IN
ANA
ST
Timer1 oscillator output – overrides the TRIS<0> control when enabled.
Timer1/Timer3 clock input.
T13CKI
RC1
RC1/T1OSI
RC2/CCP1
OUT
IN
DIG
ST
LATC<1> data output.
PORTC<1> data input.
T1OSI
RC2
IN
ANA
DIG
ST
Timer1 oscillator input – overrides the TRIS<1> control when enabled.
LATC<2> data output.
OUT
IN
PORTC<2> data input.
CCP1
OUT
IN
DIG
ST
CCP1 compare output.
CCP1 capture input.
RC3/SCK/SCL RC3
SCK
OUT
IN
DIG
ST
LATC<3> data output.
PORTC<3> data input.
OUT
DIG
SPI clock output (MSSP module) – must have TRIS set to ‘1’ to allow the
MSSP module to control the bidirectional communication.
IN
1
0
ST
SPI clock input (MSSP module).
2
SCL
OUT
DIG
I C™/SMBus clock output (MSSP module) – must have TRIS set to ‘1’ to
allow the MSSP module to control the bidirectional communication.
2
2
IN
OUT
IN
1
0
1
1
1
I C/SMB I C/SMBus clock input.
RC4/SDI/SDA RC4
DIG
ST
LATC<4> data output.
PORTC<4> data input.
SDI
IN
ST
SPI data input (MSSP module).
2
SDA
OUT
DIG
I C/SMBus data output (MSSP module) – must have TRIS set to ‘1’ to
allow the MSSP module to control the bidirectional communication.
2
2
IN
1
I C/SMB I C/SMBus data input (MSSP module) – must have TRIS set to ‘1’ to allow
the MSSP module to control the bidirectional communication.
RC5/SDO
RC5
OUT
IN
0
1
0
0
1
0
1
DIG
ST
LATC<5> data output.
PORTC<5> data input.
SPI data output (MSSP module).
LATC<6> data output.
PORTC<6> data input.
EUSART data output.
SDO
RC6
OUT
OUT
IN
DIG
DIG
ST
RC6/TX/CK
TX
CK
OUT
OUT
DIG
DIG
EUSART synchronous clock output – must have TRIS set to ‘1’ to enable
EUSART to control the bidirectional communication.
IN
OUT
IN
1
0
1
1
1
ST
DIG
ST
EUSART synchronous clock input.
LATC<7> data output.
RC7/RX/DT
RC7
PORTC<7> data input.
RX
DT
IN
ST
EUSART asynchronous data input.
OUT
DIG
EUSART synchronous data output – must have TRIS set to ‘1’ to enable
EUSART to control the bidirectional communication.
IN
1
ST
EUSART synchronous data input.
Legend:
OUT = Output; IN = Input; ANA = Analog Signal; DIG = Digital Output; ST = Schmitt Buffer Input;
TTL = TTL Buffer Input; I C = Inter-Integrated Circuit; SMBus = System Management Bus
2
DS39761B-page 136
Preliminary
© 2007 Microchip Technology Inc.
PIC18F2682/2685/4682/4685
TABLE 10-6: SUMMARY OF REGISTERS ASSOCIATED WITH PORTC
Reset
Values
on page
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PORTC
RC7
RC6
RC5
RC4
RC3
RC2
RC1
RC0
52
52
52
LATC
LATC Data Output Register
TRISC
PORTC Data Direction Register
© 2007 Microchip Technology Inc.
Preliminary
DS39761B-page 137
PIC18F2682/2685/4682/4685
PORTD can also be configured as an 8-bit wide micro-
10.4 PORTD, TRISD and LATD
Registers
processor port (Parallel Slave Port) by setting control
bit, PSPMODE (TRISE<4>). In this mode, the input
buffers are TTL. See Section 10.6 “Parallel Slave
Port” for additional information on the Parallel Slave
Port (PSP).
Note:
PORTD is only available on PIC18F4682/
4685 devices.
PORTD is an 8-bit wide, bidirectional port. The corre-
sponding data direction register is TRISD. Setting a
TRISD bit (= 1) will make the corresponding PORTD
pin an input (i.e., put the corresponding output driver in
a high-impedance mode). Clearing a TRISD bit (= 0)
will make the corresponding PORTD pin an output (i.e.,
put the contents of the output latch on the selected pin).
Note:
When the Enhanced PWM mode is used
with either dual or quad outputs, the PSP
functions of PORTD are automatically
disabled.
EXAMPLE 10-4:
INITIALIZING PORTD
CLRF
PORTD
; Initialize PORTD by
; clearing output
; data latches
; Alternate method
; to clear output
; data latches
; Value used to
; initialize data
; direction
The Data Latch register (LATD) is also memory
mapped. Read-modify-write operations on the LATD
register read and write the latched output value for
PORTD.
CLRF
LATD
All pins on PORTD are implemented with Schmitt Trigger
input buffers. Each pin is individually configurable as an
input or output.
MOVLW
MOVWF
0CFh
Three of the PORTD pins are multiplexed with outputs
P1A, P1B, P1C and P1D of the Enhanced CCP1
(ECCP1) module. The operation of these additional
PWM output pins is covered in greater detail in
Section 16.0 “Enhanced Capture/Compare/PWM
(ECCP1) Module”.
TRISD
; Set RD<3:0> as inputs
; RD<5:4> as outputs
; RD<7:6> as inputs
Note:
On a Power-on Reset, these pins are
configured as digital inputs.
DS39761B-page 138
Preliminary
© 2007 Microchip Technology Inc.
PIC18F2682/2685/4682/4685
TABLE 10-7: PORTD I/O SUMMARY
Pin Name Function I/O
TRIS Buffer
Description
RD0/PSP0/ RD0
C1IN+
OUT
IN
0
1
x
x
1
DIG LATD<0> data output.
ST PORTD<0> data input.
PSP0
OUT
IN
DIG Parallel Slave Port (PSP) data output (overrides the TRIS<0> control when enabled).
TTL Parallel Slave Port (PSP) data input (overrides the TRIS<0> control when enabled).
C1IN+
IN
ANA Comparator 1 positive input B. Default on POR. This analog input overrides the
digital input (read as clear – low level).
RD1/PSP1/ RD1
C1IN-
OUT
IN
0
1
x
x
1
DIG LATD<1> data output.
ST PORTD<1> data input.
PSP1
OUT
IN
DIG Parallel Slave Port (PSP) data output (overrides the TRIS<1> control when enabled).
TTL Parallel Slave Port (PSP) data input (overrides the TRIS<1> control when enabled).
C1IN-
IN
ANA Comparator 1 negative input. Default on POR. This analog input overrides the
digital input (read as clear – low level).
RD2/PSP2/ RD2
C2IN+
OUT
IN
0
1
x
x
1
DIG LATD<2> data output.
ST PORTD<2> data input.
PSP2
OUT
IN
DIG Parallel Slave Port (PSP) data output (overrides the TRIS<2> control when enabled).
TTL Parallel Slave Port (PSP) data input (overrides the TRIS<2> control when enabled).
C2IN+
IN
ANA Comparator 2 positive input. Default on POR. This analog input overrides the digital
input (read as clear – low level).
RD3/PSP3/ RD3
C2IN-
OUT
IN
0
1
x
x
1
DIG LATD<3> data output.
ST PORTD<3> data input.
PSP3
OUT
IN
DIG Parallel Slave Port (PSP) data output (overrides the TRIS<3> control when enabled).
TTL Parallel Slave Port (PSP) data input (overrides the TRIS<3> control when enabled).
C2IN-
IN
ANA Comparator 2 negative input. Default input on POR. This analog input overrides the
digital input (read as clear – low level).
RD4/PSP4/ RD4
ECCP1/P1A
OUT
IN
0
1
x
x
0
1
0
0
1
X
x
0
0
1
x
x
0
0
1
x
x
0
DIG LATD<4> data output.
ST PORTD<4> data input.
PSP4
ECCP1
P1A
OUT
IN
DIG Parallel Slave Port (PSP) data output (overrides the TRIS<4> control when enabled).
TTL Parallel Slave Port (PSP) data input (overrides the TRIS<4> control when enabled).
DIG ECCP1 compare output.
OUT
IN
ST ECCP1 capture input.
OUT
OUT
IN
DIG ECCP1 Enhanced PWM output, channel A.
DIG LATD<5> data output.
RD5/PSP5/ RD5
P1B
ST PORTD<5> data input.
PSP5
OUT
IN
DIG Parallel Slave Port (PSP) data output (overrides the TRIS<5> control when enabled).
TTL Parallel Slave Port (PSP) data input (overrides the TRIS<5> control when enabled).
DIG ECCP1 Enhanced PWM output, channel B.
DIG LATD<6> data output.
P1B
OUT
OUT
IN
RD6/PSP6/ RD6
P1C
ST PORTD<6> data input.
PSP6
OUT
IN
DIG Parallel Slave Port (PSP) data output (overrides the TRIS<6> control when enabled).
TTL Parallel Slave Port (PSP) data input (overrides the TRIS<6> control when enabled).
DIG ECCP1 Enhanced PWM output, channel C.
DIG LATD<7> data output.
P1C
OUT
OUT
IN
RD7/PSP7/ RD7
P1D
ST PORTD<7> data input.
PSP7
OUT
IN
DIG Parallel Slave Port (PSP) data output (overrides the TRIS<7> control when enabled).
TTL Parallel Slave Port (PSP) data input (overrides the TRIS<7> control when enabled).
DIG ECCP1 Enhanced PWM output, channel D.
P1D
OUT
Legend:
OUT = Output; IN = Input; ANA = Analog Signal; DIG = Digital Output; ST = Schmitt Buffer Input; TTL = TTL Buffer Input
© 2007 Microchip Technology Inc.
Preliminary
DS39761B-page 139
PIC18F2682/2685/4682/4685
TABLE 10-8: SUMMARY OF REGISTERS ASSOCIATED WITH PORTD
Reset
Values
on page
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
(1)
PORTD
RD7
RD6
RD5
RD4
RD3
RD2
RD1
RD0
52
52
52
52
51
(1)
LATD
LATD Data Output Register
PORTD Data Direction Register
IBF OBF IBOV
EPWM1M1 EPWM1M0 EDC1B1
(1)
TRISD
(1)
TRISE
ECCP1CON
PSPMODE
—
TRISE2
TRISE1
TRISE0
(1)
EDC1B0 ECCP1M3 ECCP1M2 ECCP1M1 ECCP1M0
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PORTD.
Note 1: These registers are available on PIC18F4682/4685 devices only.
DS39761B-page 140
Preliminary
© 2007 Microchip Technology Inc.
PIC18F2682/2685/4682/4685
The fourth pin of PORTE (MCLR/VPP/RE3) is an input
only pin. Its operation is controlled by the MCLRE
Configuration bit. When selected as a port pin
10.5 PORTE, TRISE and LATE
Registers
(MCLRE = 0), it functions as a digital input only pin. As
such, it does not have TRIS or LAT bits associated with
its operation. Otherwise, it functions as the device’s
Master Clear input. In either configuration, RE3 also
functions as the programming voltage input during
programming.
Depending on the particular PIC18F2682/2685/4682/
4685 device selected, PORTE is implemented in two
different ways.
For PIC18F4682/4685 devices, PORTE is a 4-bit wide
port. Three pins (RE0/RD/AN5, RE1/WR/AN6/C1OUT
and RE2/CS/AN7/C2OUT) are individually config-
urable as inputs or outputs. These pins have Schmitt
Trigger input buffers. When selected as an analog
input, these pins will read as ‘0’s.
Note:
On a Power-on Reset, RE3 is enabled as
digital input only if Master Clear
functionality is disabled.
a
The corresponding data direction register is TRISE.
Setting a TRISE bit (= 1) will make the corresponding
PORTE pin an input (i.e., put the corresponding output
driver in a high-impedance mode). Clearing a TRISE bit
(= 0) will make the corresponding PORTE pin an output
(i.e., put the contents of the output latch on the selected
pin).
EXAMPLE 10-5:
INITIALIZING PORTE
; Initialize PORTE by
; clearing output
; data latches
; Alternate method
; to clear output
; data latches
; Configure A/D
; for digital inputs
; Value used to
; initialize data
; direction
; Turn off
; comparators
; Set RE<0> as inputs
; RE<1> as outputs
; RE<2> as inputs
CLRF
PORTE
CLRF
LATE
TRISE controls the direction of the RE pins, even when
they are being used as analog inputs. The user must
make sure to keep the pins configured as inputs when
using them as analog inputs.
MOVLW 0Ah
MOVWF ADCON1
MOVLW 03h
Note:
On a Power-on Reset, RE2:RE0 are
configured as analog inputs.
MOVLW 07h
MOVWF CMCON
MOVWF TRISC
The upper four bits of the TRISE register also control
the operation of the Parallel Slave Port. Their operation
is explained in Register 10-1.
The Data Latch register (LATE) is also memory
mapped. Read-modify-write operations on the LATE
register, read and write the latched output value for
PORTE.
10.5.1
PORTE IN 28-PIN DEVICES
For PIC18F2682/2685 devices, PORTE is only
available when Master Clear functionality is disabled
(MCLRE = 0). In these cases, PORTE is a single bit,
input only port comprised of RE3 only. The pin operates
as previously described.
© 2007 Microchip Technology Inc.
Preliminary
DS39761B-page 141
PIC18F2682/2685/4682/4685
REGISTER 10-1: TRISE REGISTER (PIC18F4682/4685 DEVICES ONLY)
R-0
IBF
R-0
R/W-0
IBOV
R/W-0
U-0
—
R/W-1
R/W-1
R/W-1
OBF
PSPMODE
TRISE2
TRISE1
TRISE0
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7
bit 6
bit 5
bit 4
IBF: Input Buffer Full Status bit
1= A word has been received and waiting to be read by the CPU
0= No word has been received
OBF: Output Buffer Full Status bit
1= The output buffer still holds a previously written word
0= The output buffer has been read
IBOV: Input Buffer Overflow Detect bit (in Microprocessor mode)
1= A write occurred when a previously input word has not been read (must be cleared in software)
0= No overflow occurred
PSPMODE: Parallel Slave Port Mode Select bit
1= Parallel Slave Port mode
0= General purpose I/O mode
bit 3
bit 2
Unimplemented: Read as ‘0’
TRISE2: RE2 Direction Control bit
1= Input
0= Output
bit 1
bit 0
TRISE1: RE1 Direction Control bit
1= Input
0= Output
TRISE0: RE0 Direction Control bit
1= Input
0= Output
DS39761B-page 142
Preliminary
© 2007 Microchip Technology Inc.
PIC18F2682/2685/4682/4685
TABLE 10-9: PORTE I/O SUMMARY
Pin Name
Function I/O TRIS Buffer
Description
RE0/RD/AN5
RE0
OUT
IN
0
1
1
1
DIG LATE<0> data output.
ST PORTE<0> data input.
TTL PSP read enable input.
RD
IN
AN5
IN
ANA A/D input channel 5. Enabled on POR, this analog input overrides the
digital input (read as clear – low level).
RE1/WR/AN6/C1OUT RE1
OUT
IN
0
1
1
1
DIG LATE<1> data output.
ST
PORTE<1> data input.
WR
IN
TTL PSP write enable input.
AN6
IN
ANA A/D input channel 6. Enabled on POR, this analog input overrides the
digital input (read as clear – low level).
C1OUT
OUT
OUT
IN
0
0
1
1
1
DIG Comparator 1 output.
DIG LATE<2> data output.
RE2/CS/AN7/C2OUT RE2
ST
PORTE<2> data input.
CS
IN
TTL PSP chip select input.
AN7
IN
ANA A/D input channel 7. Enabled on POR, this analog input overrides the
digital input (read as clear – low level).
C2OUT
OUT
IN
0
x
x
1
DIG Comparator 2 output.
MCLR/VPP/RE3
MCLR
VPP
ST
ANA High-voltage detection; used by ICSP™ operation.
ST PORTE<3> data input. Disabled when MCLRE Configuration bit is ‘0’.
External Reset input. Disabled when MCLRE Configuration bit is ‘1’.
IN
RE3
IN
Legend:
OUT = Output; IN = Input; ANA = Analog Signal; DIG = Digital Output; ST = Schmitt Buffer Input; TTL = TTL Buffer Input
TABLE 10-10: SUMMARY OF REGISTERS ASSOCIATED WITH PORTE
Reset
Values
on page
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PORTE(3)
LATE(3)
TRISE(3)
ADCON1
CMCON(3)
—
—
—
—
—
—
—
—
RE3(1,2)
—
RE2
RE1
RE0
52
52
52
50
51
LATE Data Output Register
IBF
OBF
—
IBOV
VCFG1
C2INV
PSPMODE
VCFG0
C1INV
—
TRISE2
PCFG2
CM2
TRISE1
PCFG1
CM1
TRISE0
PCFG0
CM0
—
PCFG3
CIS
C2OUT
C1OUT
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PORTE.
Note 1: Implemented only when Master Clear functionality is disabled (MCLRE Configuration bit = 0).
2: RE3 is the only PORTE bit implemented on both PIC18F2682/2685 and PIC18F4682/4685 devices. All
other bits are implemented only when PORTE is implemented (i.e., PIC18F4682/4685 devices).
3: These registers are unimplemented on PIC18F2682/2685 devices.
© 2007 Microchip Technology Inc.
Preliminary
DS39761B-page 143
PIC18F2682/2685/4682/4685
The timing for the control signals in Write and Read
modes is shown in Figure 10-3 and Figure 10-4,
respectively.
10.6 Parallel Slave Port
Note:
The Parallel Slave Port is only available on
PIC18F4682/4685 devices.
FIGURE 10-2:
PORTD AND PORTE
BLOCK DIAGRAM
(PARALLEL SLAVE PORT)
In addition to its function as a general I/O port, PORTD
can also operate as an 8-bit wide Parallel Slave Port
(PSP) or microprocessor port. PSP operation is
controlled by the 4 upper bits of the TRISE register
(Register 10-1). Setting control bit, PSPMODE
(TRISE<4>), enables PSP operation, as long as the
Enhanced CCP1 (ECCP1) module is not operating in
dual output or quad output PWM mode. In Slave mode,
the port is asynchronously readable and writable by the
external world.
One bit of PORTD
Data Bus
D
Q
WR LATD or
WR PORTD
RDx pin
CK
Data Latch
TTL
The PSP can directly interface to an 8-bit micro-
processor data bus. The external microprocessor can
read or write the PORTD latch as an 8-bit latch. Setting
the control bit, PSPMODE, enables the PORTE I/O
pins to become control inputs for the microprocessor
port. When set, port pin RE0 is the RD input, RE1 is the
WR input and RE2 is the CS (Chip Select) input. For
this functionality, the corresponding data direction bits
of the TRISE register (TRISE<2:0>) must be config-
ured as inputs (set). The A/D port configuration bits,
PFCG3:PFCG0 (ADCON1<3:0>), must also be set to
‘1010’.
Q
D
RD PORTD
RD LATD
EN
Set Interrupt Flag
PSPIF (PIR1<7>)
A write to the PSP occurs when both the CS and WR
lines are first detected low and ends when either are
detected high. The PSPIF and IBF flag bits are both set
when the write ends.
PORTE Pins
Read
RD
CS
WR
TTL
TTL
TTL
Chip
Select
A read from the PSP occurs when both the CS and RD
lines are first detected low. The data in PORTD is read
out and the OBF bit is set. If the user writes new data
to PORTD to set OBF, the data is immediately read out;
however, the OBF bit is not set.
Write
Note:
I/O pins have diode protection to VDD and VSS.
When either the CS or RD line is detected high, the
PORTD pins return to the input state and the PSPIF bit
is set. User applications should wait for PSPIF to be set
before servicing the PSP. When this happens, the IBF
and OBF bits can be polled and the appropriate action
taken.
DS39761B-page 144
Preliminary
© 2007 Microchip Technology Inc.
PIC18F2682/2685/4682/4685
FIGURE 10-3:
PARALLEL SLAVE PORT WRITE WAVEFORMS
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
CS
WR
RD
PORTD<7:0>
IBF
OBF
PSPIF
FIGURE 10-4:
PARALLEL SLAVE PORT READ WAVEFORMS
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
CS
WR
RD
PORTD<7:0>
IBF
OBF
PSPIF
TABLE 10-11: REGISTERS ASSOCIATED WITH PARALLEL SLAVE PORT
Reset
Values
on page
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
(1)
PORTD
RD7
RD6
RD5
RD4
RD3
RD2
RD1
RD0
RE0
52
52
52
52
52
52
49
52
52
52
50
51
(1)
LATD
LATD Data Output Register
PORTD Data Direction Register
(1)
TRISD
(1)
PORTE
—
—
—
—
—
—
—
—
RE3
—
RE2
RE1
(1)
LATE
LATE Data Output Register
(1)
TRISE
IBF
OBF
IBOV
PSPMODE
INT0IE
TXIF
—
TRISE2
TMR0IF
CCP1IF
CCP1IE
CCP1IP
PCFG2
CM2
TRISE1
INT0IF
TMR2IF
TMR2IE
TMR2IP
PCFG1
CM1
TRISE0
RBIF
INTCON
PIR1
GIE/GIEH PEIE/GIEL TMR0IE
RBIE
SSPIF
SSPIE
SSPIP
PCFG3
CIS
(2)
PSPIF
PSPIE
PSPIP
—
ADIF
ADIE
ADIP
—
RCIF
RCIE
TMR1IF
TMR1IE
TMR1IP
PCFG0
CM0
(2)
(2)
PIE1
TXIE
IPR1
RCIP
TXIP
ADCON1
VCFG1
C2INV
VCFG0
C1INV
(1)
CMCON
C2OUT
C1OUT
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the Parallel Slave Port.
Note 1: These registers are available on PIC18F4682/4685 devices only.
2: These bits are unimplemented on PIC18F2682/2685 devices and read as ‘0’.
© 2007 Microchip Technology Inc.
Preliminary
DS39761B-page 145
PIC18F2682/2685/4682/4685
NOTES:
DS39761B-page 146
Preliminary
© 2007 Microchip Technology Inc.
PIC18F2682/2685/4682/4685
The T0CON register (Register 11-1) controls all
aspects of the module’s operation, including the
prescale selection. It is both readable and writable.
11.0 TIMER0 MODULE
The Timer0 module incorporates the following features:
• Software selectable operation as a timer or
counter in both 8-bit or 16-bit modes
A simplified block diagram of the Timer0 module in 8-bit
mode is shown in Figure 11-1. Figure 11-2 shows a
simplified block diagram of the Timer0 module in 16-bit
mode.
• Readable and writable registers
• Dedicated 8-bit, software programmable
prescaler
• Selectable clock source (internal or external)
• Edge select for external clock
• Interrupt-on-overflow
REGISTER 11-1: T0CON: TIMER0 CONTROL REGISTER
R/W-1
R/W-1
R/W-1
T0CS
R/W-1
T0SE
R/W-1
PSA
R/W-1
T0PS2
R/W-1
T0PS1
R/W-1
T0PS0
TMR0ON
T08BIT
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2-0
TMR0ON: Timer0 On/Off Control bit
1= Enables Timer0
0= Stops Timer0
T08BIT: Timer0 8-Bit/16-Bit Control bit
1= Timer0 is configured as an 8-bit timer/counter
0= Timer0 is configured as a 16-bit timer/counter
T0CS: Timer0 Clock Source Select bit
1= Transition on T0CKI pin
0= Internal instruction cycle clock (CLKO)
T0SE: Timer0 Source Edge Select bit
1= Increment on high-to-low transition on T0CKI pin
0= Increment on low-to-high transition on T0CKI pin
PSA: Timer0 Prescaler Assignment bit
1= TImer0 prescaler is NOT assigned. Timer0 clock input bypasses prescaler.
0= Timer0 prescaler is assigned. Timer0 clock input comes from prescaler output.
T0PS2:T0PS0: Timer0 Prescaler Select bits
111= 1:256 Prescale value
110= 1:128 Prescale value
101= 1:64 Prescale value
100= 1:32 Prescale value
011= 1:16 Prescale value
010= 1:8 Prescale value
001= 1:4 Prescale value
000= 1:2 Prescale value
© 2007 Microchip Technology Inc.
Preliminary
DS39761B-page 147
PIC18F2682/2685/4682/4685
internal phase clock (TOSC). There is a delay between
synchronization and the onset of incrementing the
timer/counter.
11.1 Timer0 Operation
Timer0 can operate as either a timer or a counter; the
mode is selected by clearing the T0CS bit
(T0CON<5>). In Timer mode, the module increments
on every clock by default unless a different prescaler
value is selected (see Section 11.3 “Prescaler”). If
the TMR0 register is written to, the increment is
inhibited for the following two instruction cycles. The
user can work around this by writing an adjusted value
to the TMR0 register.
11.2 Timer0 Reads and Writes in
16-Bit Mode
TMR0H is not the actual high byte of Timer0 in 16-bit
mode; it is actually a buffered version of the real high
byte of Timer0, which is not directly readable nor
writable (refer to Figure 11-2). TMR0H is updated with
the contents of the high byte of Timer0 during a read of
TMR0L. This provides the ability to read all 16 bits of
Timer0 without having to verify that the read of the high
and low byte were valid, due to a rollover between
successive reads of the high and low byte.
The Counter mode is selected by setting the T0CS bit
(= 1). In Counter mode, Timer0 increments either on
every rising or falling edge of pin RA4/T0CKI. The
incrementing edge is determined by the Timer0 Source
Edge Select bit, T0SE (T0CON<4>). Clearing this bit
selects the rising edge. Restrictions on the external
clock input are discussed below.
Similarly, a write to the high byte of Timer0 must also
take place through the TMR0H Buffer register. The high
byte is updated with the contents of TMR0H when a
write occurs to TMR0L. This allows all 16 bits of Timer0
to be updated at once.
An external clock source can be used to drive Timer0;
however, it must meet certain requirements to ensure
that the external clock can be synchronized with the
FIGURE 11-1:
TIMER0 BLOCK DIAGRAM (8-BIT MODE)
FOSC/4
0
1
1
0
Set
Sync with
Internal
Clocks
TMR0IF
TMR0L
8
on Overflow
Programmable
Prescaler
T0CKI pin
(2 TCY Delay)
T0SE
T0CS
3
T0PS2:T0PS0
PSA
8
Internal Data Bus
Note: Upon Reset, Timer0 is enabled in 8-bit mode with clock input from T0CKI max. prescale.
FIGURE 11-2:
TIMER0 BLOCK DIAGRAM (16-BIT MODE)
FOSC/4
0
1
Set
Sync with
Internal
Clocks
TMR0
High Byte
1
TMR0L
TMR0IF
on Overflow
8
Programmable
Prescaler
T0CKI pin
0
(2 TCY Delay)
T0SE
T0CS
3
Read TMR0L
Write TMR0L
T0PS2:T0PS0
PSA
8
8
TMR0H
8
8
Internal Data Bus
Note: Upon Reset, Timer0 is enabled in 8-bit mode with clock input from T0CKI max. prescale.
DS39761B-page 148
Preliminary
© 2007 Microchip Technology Inc.
PIC18F2682/2685/4682/4685
11.3.1
SWITCHING PRESCALER
ASSIGNMENT
11.3 Prescaler
An 8-bit counter is available as a prescaler for the Timer0
module. The prescaler is not directly readable or writable;
its value is set by the PSA and T0PS2:T0PS0 bits
(T0CON<3:0>) which determine the prescaler
assignment and prescale ratio.
The prescaler assignment is fully under software
control and can be changed “on-the-fly” during program
execution.
11.4 Timer0 Interrupt
Clearing the PSA bit assigns the prescaler to the
Timer0 module. When it is assigned, prescale values
from 1:2 through 1:256 in power-of-2 increments are
selectable.
The TMR0 interrupt is generated when the TMR0
register overflows from FFh to 00h in 8-bit mode, or
from FFFFh to 0000h in 16-bit mode. This overflow sets
the TMR0IF flag bit. The interrupt can be masked by
clearing the TMR0IE bit (INTCON<5>). Before re-
enabling the interrupt, the TMR0IF bit must be cleared
in software by the Interrupt Service Routine.
When assigned to the Timer0 module, all instructions
writing to the TMR0 register (e.g., CLRF TMR0, MOVWF
TMR0, BSF TMR0, etc.) clear the prescaler count.
Note:
Writing to TMR0 when the prescaler is
assigned to Timer0 will clear the prescaler
count but will not change the prescaler
assignment.
Since Timer0 is shut down in Sleep mode, the TMR0
interrupt cannot awaken the processor from Sleep.
TABLE 11-1: REGISTERS ASSOCIATED WITH TIMER0
Reset
Values
on page
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
TMR0L
Timer0 Register Low Byte
Timer0 Register High Byte
50
50
49
50
52
TMR0H
INTCON
T0CON
TRISA
GIE/GIEH PEIE/GIEL TMR0IE
TMR0ON T08BIT T0CS
TRISA7(1) TRISA6(1)
INT0IE
T0SE
RBIE
PSA
TMR0IF
T0PS2
INT0IF
T0PS1
RBIF
T0PS0
PORTA Data Direction Register
Legend: x= unknown, u= unchanged, — = unimplemented locations, read as ‘0’. Shaded cells are not used by Timer0.
Note 1: RA7:RA6 and their associated latch and data direction bits are enabled as I/O pins based on oscillator
configuration; otherwise, they are read as ‘0’.
© 2007 Microchip Technology Inc.
Preliminary
DS39761B-page 149
PIC18F2682/2685/4682/4685
NOTES:
DS39761B-page 150
Preliminary
© 2007 Microchip Technology Inc.
PIC18F2682/2685/4682/4685
A simplified block diagram of the Timer1 module is
shown in Figure 12-1. A block diagram of the module’s
operation in Read/Write mode is shown in Figure 12-2.
12.0 TIMER1 MODULE
The Timer1 timer/counter module incorporates these
features:
The module incorporates its own low-power oscillator
to provide an additional clocking option. The Timer1
oscillator can also be used as a low-power clock source
for the microcontroller in power-managed operation.
• Software selectable operation as a 16-bit timer or
counter
• Readable and writable 8-bit registers (TMR3H
and TMR3L)
Timer1 can also be used to provide Real-Time Clock
(RTC) functionality to applications with only a minimal
addition of external components and code overhead.
• Selectable clock source (internal or external) with
device clock or Timer1 oscillator internal options
• Interrupt on overflow
Timer1 is controlled through the T1CON Control
register (Register 12-1). It also contains the Timer1
Oscillator Enable bit (T1OSCEN). Timer1 can be
enabled or disabled by setting or clearing control bit,
TMR1ON (T1CON<0>).
• Module Reset on CCP1 Special Event Trigger
• Device clock status flag (T1RUN)
REGISTER 12-1: T1CON: TIMER1 CONTROL REGISTER
R/W-0
RD16
R-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
T1RUN
T1CKPS1
T1CKPS0
T1OSCEN
T1SYNC
TMR1CS
TMR1ON
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7
RD16: 16-Bit Read/Write Mode Enable bit
1= Enables register read/write of Timer1 in one 16-bit operation
0= Enables register read/write of Timer1 in two 8-bit operations
bit 6
T1RUN: Timer1 System Clock Status bit
1= Device clock is derived from Timer1 oscillator
0= Device clock is derived from another source
bit 5-4
T1CKPS1:T1CKPS0: Timer1 Input Clock Prescale Select bits
11= 1:8 Prescale value
10= 1:4 Prescale value
01= 1:2 Prescale value
00= 1:1 Prescale value
bit 3
bit 2
T1OSCEN: Timer1 Oscillator Enable bit
1= Timer1 oscillator is enabled
0= Timer1 oscillator is shut off
The oscillator inverter and feedback resistor are turned off to eliminate power drain.
T1SYNC: Timer1 External Clock Input Synchronization Select bit
When TMR1CS = 1:
1= Do not synchronize external clock input
0= Synchronize external clock input
When TMR1CS = 0:
This bit is ignored. Timer1 uses the internal clock when TMR1CS = 0.
bit 1
bit 0
TMR1CS: Timer1 Clock Source Select bit
1= External clock from pin RC0/T1OSO/T13CKI (on the rising edge)
0= Internal clock (FOSC/4)
TMR1ON: Timer1 On bit
1= Enables Timer1
0= Stops Timer1
© 2007 Microchip Technology Inc.
Preliminary
DS39761B-page 151
PIC18F2682/2685/4682/4685
cycle (Fosc/4). When the bit is set, Timer3 increments
on every rising edge of the Timer1 external clock input
or the Timer1 oscillator, if enabled.
12.1 Timer1 Operation
Timer1 can operate in one of these modes:
• Timer
When Timer1 is enabled, the RC1/T1OSI and RC0/
T1OSO/T13CKI pins become inputs. This means the
values of TRISC<1:0> are ignored and the pins are
read as ‘0’.
• Synchronous Counter
• Asynchronous Counter
The operating mode is determined by the clock select
bit, TMR3CS (T3CON<1>). When TMR3CS is cleared
(= 0), Timer3 increments on every internal instruction
FIGURE 12-1:
TIMER1 BLOCK DIAGRAM
Timer1 Oscillator
On/Off
1
1
T1OSO/T13CKI
T1OSI
Synchronize
Detect
Prescaler
1, 2, 4, 8
0
FOSC/4
Internal
Clock
0
2
Sleep Input
T1OSCEN(1)
T1CKPS1:T1CKPS0
T1SYNC
Timer1
On/Off
TMR1CS
TMR1ON
Set
TMR1
Clear TMR1
(CCP1 Special Event Trigger)
TMR1IF
TMR1L
High Byte
on Overflow
Note 1: When enable bit, T1OSCEN, is cleared, the inverter and feedback resistor are turned off to eliminate power drain.
FIGURE 12-2:
TIMER1 BLOCK DIAGRAM (16-BIT READ/WRITE MODE)
Timer1 Oscillator
1
0
1
T1OSO/T13CKI
T1OSI
Prescaler
1, 2, 4, 8
Synchronize
Detect
FOSC/4
Internal
Clock
0
2
Sleep Input
T1OSCEN(1)
T1CKPS1:T1CKPS0
T1SYNC
TMR1CS
Timer1
On/Off
TMR1ON
Set
TMR1IF
on Overflow
TMR1
Clear TMR1
(CCP1 Special Event Trigger)
TMR1L
High Byte
8
Read TMR1L
Write TMR1L
8
8
TMR1H
8
8
Internal Data Bus
Note 1: When enable bit, T1OSCEN, is cleared, the inverter and feedback resistor are turned off to eliminate power drain.
DS39761B-page 152
Preliminary
© 2007 Microchip Technology Inc.
PIC18F2682/2685/4682/4685
TABLE 12-1: CAPACITOR SELECTION
FOR THE TIMER1
12.2 Timer1 16-Bit Read/Write Mode
Timer1 can be configured for 16-bit reads and writes
(see Figure 12-2). When the RD16 control bit
(T1CON<7>) is set, the address for TMR1H is mapped
to a buffer register for the high byte of Timer1. A read
from TMR1L will load the contents of the high byte of
Timer1 into the Timer1 High Byte Buffer register. This
provides the user with the ability to accurately read all
16 bits of Timer1 without having to determine whether
a read of the high byte, followed by a read of the low
byte, has become invalid due to a rollover between
reads.
OSCILLATOR(1,2,3,4)
Osc Type
Freq
C1
C2
LP
32.768 kHz
27 pF
27 pF
Note 1: Microchip suggests these values as a
starting point in validating the oscillator
circuit.
2: Higher capacitance increases the stability
of the oscillator but also increases the
start-up time.
A write to the high byte of Timer1 must also take place
through the TMR1H Buffer register. The Timer1 high
byte is updated with the contents of TMR1H when a
write occurs to TMR1L. This allows a user to write all
16 bits to both the high and low bytes of Timer1 at once.
3: Since each resonator/crystal has its own
characteristics, the user should consult
the resonator/crystal manufacturer for
appropriate
values
of
external
components.
The high byte of Timer1 is not directly readable or
writable in this mode. All reads and writes must take
place through the Timer1 High Byte Buffer register.
Writes to TMR1H do not clear the Timer1 prescaler.
The prescaler is only cleared on writes to TMR1L.
4: Capacitor values are for design guidance
only.
12.3.1
USING TIMER1 AS A CLOCK
SOURCE
The Timer1 oscillator is also available as a clock source
in power-managed modes. By setting the Clock Select
bits, SCS1:SCS0 (OSCCON<1:0>), to ‘01’, the device
switches to SEC_RUN mode; both the CPU and
peripherals are clocked from the Timer1 oscillator. If the
IDLEN bit (OSCCON<7>) is cleared and a SLEEP
instruction is executed, the device enters SEC_IDLE
mode. Additional details are available in Section 3.0
“Power-Managed Modes”.
12.3 Timer1 Oscillator
An on-chip crystal oscillator circuit is incorporated
between pins T1OSI (input) and T1OSO (amplifier
output). It is enabled by setting the Timer1 Oscillator
Enable bit, T1OSCEN (T1CON<3>). The oscillator is a
low-power circuit rated for 32 kHz crystals. It will
continue to run during all power-managed modes. The
circuit for a typical LP oscillator is shown in Figure 12-3.
Table 12-1 shows the capacitor selection for the Timer1
oscillator.
Whenever the Timer1 oscillator is providing the clock
source, the Timer1 system clock status flag, T1RUN
(T1CON<6>), is set. This can be used to determine the
controller’s current clocking mode. It can also indicate
the clock source being currently used by the Fail-Safe
Clock Monitor. If the Clock Monitor is enabled and the
Timer1 oscillator fails while providing the clock, polling
the T1RUN bit will indicate whether the clock is being
provided by the Timer1 oscillator or another source.
The user must provide a software time delay to ensure
proper start-up of the Timer1 oscillator.
FIGURE 12-3:
EXTERNAL
COMPONENTS FOR THE
TIMER1 LP OSCILLATOR
C1
27 pF
PIC18FXXXX
12.3.2
LOW-POWER TIMER1 OPTION
T1OSI
The Timer1 oscillator can operate at two distinct levels
of power consumption based on device configuration.
When the LPT1OSC Configuration bit is set, the Timer1
oscillator operates in a low-power mode. When
LPT1OSC is not set, Timer1 operates at a higher power
level. Power consumption for a particular mode is rela-
tively constant, regardless of the device’s operating
mode. The default Timer1 configuration is the higher
power mode.
XTAL
32.768 kHz
T1OSO
C2
27 pF
Note:
See the Notes with Table 12-1 for additional
information about capacitor selection.
As the low-power Timer1 mode tends to be more
sensitive to interference, high noise environments may
cause some oscillator instability. The low-power option is,
therefore, best suited for low noise applications where
power conservation is an important design consideration.
© 2007 Microchip Technology Inc.
Preliminary
DS39761B-page 153
PIC18F2682/2685/4682/4685
12.3.3
TIMER1 OSCILLATOR LAYOUT
CONSIDERATIONS
12.5 Resetting Timer1 Using the CCP1
Special Event Trigger
The Timer1 oscillator circuit draws very little power
during operation. Due to the low-power nature of the
oscillator, it may also be sensitive to rapidly changing
signals in close proximity.
If either of the CCP1 modules is configured in Compare
mode to generate
a
Special Event Trigger
(CCP1M3:CCP1M0 or CCP2M3:CCP2M0 = 1011), this
signal will reset Timer1. The trigger from ECCP1 will also
start an A/D conversion if the A/D module is enabled
(see Section 15.3.4 “Special Event Trigger” for more
information.).
The oscillator circuit, shown in Figure 12-3, should be
located as close as possible to the microcontroller.
There should be no circuits passing within the oscillator
circuit boundaries other than VSS or VDD.
The module must be configured as either a timer or a
synchronous counter to take advantage of this feature.
When used this way, the CCPR1H:CCPR1L register
pair effectively becomes a period register for Timer1.
If a high-speed circuit must be located near the oscilla-
tor (such as the CCP1 pin in Output Compare or PWM
mode, or the primary oscillator using the OSC2 pin), a
grounded guard ring around the oscillator circuit, as
shown in Figure 12-4, may be helpful when used on a
single-sided PCB or in addition to a ground plane.
If Timer1 is running in Asynchronous Counter mode,
this Reset operation may not work.
In the event that a write to Timer1 coincides with a
Special Event Trigger, the write operation will take
precedence.
FIGURE 12-4:
OSCILLATOR CIRCUIT
WITH GROUNDED
GUARD RING
Note:
The Special Event Triggers from the
ECCP1 module will not set the TMR1IF
interrupt flag bit (PIR1<0>).
VDD
VSS
12.6 Using Timer1 as a Real-Time
Clock
OSC1
OSC2
Adding an external LP oscillator to Timer1 (such as the
one described in Section 12.3 “Timer1 Oscillator”)
gives users the option to include RTC functionality to
their applications. This is accomplished with an
inexpensive watch crystal to provide an accurate time
base and several lines of application code to calculate
the time. When operating in Sleep mode and using a
battery or supercapacitor as a power source, it can
completely eliminate the need for a separate RTC
device and battery backup.
RC0
RC1
RC2
Note: Not drawn to scale.
The application code routine, RTCisr, shown in
Example 12-1, demonstrates a simple method to
increment a counter at one-second intervals using an
Interrupt Service Routine. Incrementing the TMR1
register pair to overflow triggers the interrupt and calls
the routine, which increments the seconds counter by
one; additional counters for minutes and hours are
incremented as the previous counter overflow.
12.4 Timer1 Interrupt
The TMR1 register pair (TMR1H:TMR1L) increments
from 0000h to FFFFh and rolls over to 0000h. The
Timer1 interrupt, if enabled, is generated on overflow,
which is latched in interrupt flag bit, TMR1IF
(PIR1<0>). This interrupt can be enabled or disabled
by setting or clearing the Timer1 Interrupt Enable bit,
TMR1IE (PIE1<0>).
Since the register pair is 16 bits wide, counting up to
overflow the register directly from a 32.768 kHz clock
would take 2 seconds. To force the overflow at the
required one-second intervals, it is necessary to pre-
load it. The simplest method is to set the MSb of
TMR1H with a BSF instruction. Note that the TMR1L
register is never preloaded or altered; doing so may
introduce cumulative error over many cycles.
For this method to be accurate, Timer1 must operate in
Asynchronous mode and the Timer1 overflow interrupt
must be enabled (PIE1<0> = 1) as shown in the routine,
RTCinit. The Timer1 oscillator must also be enabled
and running at all times.
DS39761B-page 154
Preliminary
© 2007 Microchip Technology Inc.
PIC18F2682/2685/4682/4685
EXAMPLE 12-1:
IMPLEMENTING A REAL-TIME CLOCK USING A TIMER1 INTERRUPT SERVICE
RTCinit
MOVLW
MOVWF
CLRF
80h
TMR1H
TMR1L
; Preload TMR1 register pair
; for 1 second overflow
MOVLW
MOVWF
CLRF
b’00001111’
T1OSC
secs
; Configure for external clock,
; Asynchronous operation, external oscillator
; Initialize timekeeping registers
;
CLRF
mins
MOVLW
MOVWF
BSF
.12
hours
PIE1, TMR1IE
; Enable Timer1 interrupt
RETURN
RTCisr
BSF
BCF
INCF
MOVLW
CPFSGT
RETURN
CLRF
TMR1H, 7
PIR1, TMR1IF
secs, F
.59
; Preload for 1 sec overflow
; Clear interrupt flag
; Increment seconds
; 60 seconds elapsed?
secs
; No, done
secs
mins, F
.59
; Clear seconds
; Increment minutes
; 60 minutes elapsed?
INCF
MOVLW
CPFSGT
RETURN
CLRF
mins
; No, done
mins
hours, F
.23
; clear minutes
; Increment hours
; 24 hours elapsed?
INCF
MOVLW
CPFSGT
RETURN
MOVLW
MOVWF
RETURN
hours
; No, done
; Reset hours to 1
.01
hours
; Done
TABLE 12-2: REGISTERS ASSOCIATED WITH TIMER1 AS A TIMER/COUNTER
Reset
Values
on page
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
INTCON
PIR1
GIE/GIEH PEIE/GIEL TMR0IE
INT0IE
TXIF
RBIE
SSPIF
SSPIE
SSPIP
TMR0IF
CCP1IF
CCP1IE
CCP1IP
INT0IF
TMR2IF
TMR2IE
TMR2IP
RBIF
49
52
52
52
50
50
50
PSPIF(1)
PSPIE(1)
PSPIP(1)
ADIF
ADIE
ADIP
RCIF
RCIE
RCIP
TMR1IF
TMR1IE
TMR1IP
PIE1
TXIE
TXIP
IPR1
TMR1L
TMR1H
T1CON
Timer1 Register Low Byte
TImer1 Register High Byte
RD16
T1RUN T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON
Legend: x = unknown, u= unchanged, — = unimplemented, read as ‘0’.
Shaded cells are not used by the Timer1 module.
Note 1: These bits are unimplemented on PIC18F2682/2685 devices; always maintain these bits clear.
© 2007 Microchip Technology Inc.
Preliminary
DS39761B-page 155
PIC18F2682/2685/4682/4685
NOTES:
DS39761B-page 156
Preliminary
© 2007 Microchip Technology Inc.
PIC18F2682/2685/4682/4685
13.1 Timer2 Operation
13.0 TIMER2 MODULE
In normal operation, TMR2 is incremented from 00h on
each clock (FOSC/4). A 2-bit counter/prescaler on the
clock input gives direct input, divide-by-4 and divide-
by-16 prescale options. These options are selected by
the prescaler control bits, T2CKPS1:T2CKPS0
(T2CON<1:0>). The value of TMR2 is compared to that
of the period register, PR2, on each clock cycle. When
the two values match, the comparator generates a
match signal as the timer output. This signal also resets
the value of TMR2 to 00h on the next cycle and drives
the output counter/postscaler (see Section 13.2
“Timer2 Interrupt”).
The Timer2 module incorporates the following features:
• 8-bit timer and period registers (TMR2 and PR2,
respectively)
• Readable and writable (both registers)
• Software programmable prescaler (1:1, 1:4 and
1:16)
• Software programmable postscaler (1:1 through
1:16)
• Interrupt on TMR2 to PR2 match
• Optional use as the shift clock for the MSSP
module
The TMR2 and PR2 registers are both directly readable
and writable. The TMR2 register is cleared on any
device Reset, while the PR2 register initializes at FFh.
Both the prescaler and postscaler counters are cleared
on the following events:
The module is controlled through the T2CON register
(Register 13-1), which enables or disables the timer
and configures the prescaler and postscaler. Timer2
can be shut off by clearing control bit, TMR2ON
(T2CON<2>), to minimize power consumption.
• a write to the TMR2 register
• a write to the T2CON register
A simplified block diagram of the module is shown in
Figure 13-1.
• any device Reset (Power-on Reset, MCLR Reset,
Watchdog Timer Reset or Brown-out Reset)
TMR2 is not cleared when T2CON is written.
REGISTER 13-1: T2CON: TIMER2 CONTROL REGISTER
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
T2OUTPS3 T2OUTPS2 T2OUTPS1 T2OUTPS0
TMR2ON
T2CKPS1
T2CKPS0
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7
Unimplemented: Read as ‘0’
bit 6-3
T2OUTPS3:T2OUTPS0: Timer2 Output Postscale Select bits
0000= 1:1 Postscale
0001= 1:2 Postscale
•
•
•
1111= 1:16 Postscale
bit 2
TMR2ON: Timer2 On bit
1= Timer2 is on
0= Timer2 is off
bit 1-0
T2CKPS1:T2CKPS0: Timer2 Clock Prescale Select bits
00= Prescaler is 1
01= Prescaler is 4
1x= Prescaler is 16
© 2007 Microchip Technology Inc.
Preliminary
DS39761B-page 157
PIC18F2682/2685/4682/4685
13.2 Timer2 Interrupt
13.3 TMR2 Output
Timer2 also can generate an optional device interrupt.
The Timer2 output signal (TMR2 to PR2 match)
provides the input for the 4-bit output counter/
postscaler. This counter generates the TMR2 match
interrupt flag which is latched in TMR2IF (PIR1<1>).
The interrupt is enabled by setting the TMR2 Match
Interrupt Enable bit, TMR2IE (PIE1<1>).
The unscaled output of TMR2 is available primarily to
the CCP1 modules, where it is used as a time base for
operations in PWM mode.
Timer2 can be optionally used as the shift clock source
for the MSSP module operating in SPI mode.
Additional information is provided in Section 17.0
“Master Synchronous Serial Port (MSSP) Module”.
A range of 16 postscale options (from 1:1 through 1:16
inclusive) can be selected with the postscaler control
bits, T2OUTPS3:T2OUTPS0 (T2CON<6:3>).
FIGURE 13-1:
TIMER2 BLOCK DIAGRAM
4
1:1 to 1:16
Set TMR2IF
Postscaler
T2OUTPS3:T2OUTPS0
2
T2CKPS1:T2CKPS0
TMR2 Output
(to PWM or MSSP)
TMR2/PR2
Match
Reset
TMR2
1:1, 1:4, 1:16
Prescaler
FOSC/4
Comparator
PR2
8
8
8
Internal Data Bus
TABLE 13-1: REGISTERS ASSOCIATED WITH TIMER2 AS A TIMER/COUNTER
Reset
Values
on page
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
INTCON GIE/GIEH PEIE/GIEL TMR0IE
INT0IE
TXIF
RBIE
SSPIF
SSPIE
SSPIP
TMR0IF
CCP1IF
CCP1IE
CCP1IP
INT0IF
TMR2IF
TMR2IE
TMR2IP
RBIF
49
52
52
52
50
50
50
PIR1
PIE1
IPR1
PSPIF(1)
PSPIE(1)
PSPIP(1)
ADIF
ADIE
ADIP
RCIF
RCIE
RCIP
TMR1IF
TMR1IE
TMR1IP
TXIE
TXIP
TMR2 Timer2 Register
T2CON
PR2
—
T2OUTPS3 T2OUTPS2 T2OUTPS1 T2OUTPS0 TMR2ON T2CKPS1 T2CKPS0
Timer2 Period Register
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the Timer2 module.
Note 1: These bits are unimplemented on PIC18F2682/2685 devices; always maintain these bits clear.
DS39761B-page 158
Preliminary
© 2007 Microchip Technology Inc.
PIC18F2682/2685/4682/4685
A simplified block diagram of the Timer3 module is
shown in Figure 14-1. A block diagram of the module’s
operation in Read/Write mode is shown in Figure 14-2.
14.0 TIMER3 MODULE
The Timer3 timer/counter module incorporates these
features:
The Timer3 module is controlled through the T3CON
register (Register 14-1). It also selects the clock source
options for the ECCP1/CCP1 modules (see
Section 15.1.1 “CCP1 Modules and Timer
Resources” for more information).
• Software selectable operation as a 16-bit timer or
counter
• Readable and writable 8-bit registers (TMR3H
and TMR3L)
• Selectable clock source (internal or external) with
device clock or Timer1 oscillator internal options
• Interrupt on overflow
• Module Reset on CCP1 Special Event Trigger
REGISTER 14-1: T3CON: TIMER3 CONTROL REGISTER
R/W-0
RD16
R/W-0
T3ECCP1(1)
R/W-0
R/W-0
R/W-0
T3CCP1(1)
R/W-0
R/W-0
R/W-0
T3CKPS1
T3CKPS0
T3SYNC
TMR3CS
TMR3ON
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7
RD16: 16-Bit Read/Write Mode Enable bit
1= Enables register read/write of Timer3 in one 16-bit operation
0= Enables register read/write of Timer3 in two 8-bit operations
bit 6,3
T3ECCP1:T3CCP1: Timer3 and Timer1 to ECCP1/CCP1 Enable bits(1)
1x= Timer3 is the capture/compare clock source for both CCP1 and ECCP1 modules
01= Timer3 is the capture/compare clock source for ECCP1;
Timer1 is the capture/compare clock source for CCP1
00= Timer1 is the capture/compare clock source for both CCP1 and ECCP1 modules
bit 5-4
bit 2
T3CKPS1:T3CKPS0: Timer3 Input Clock Prescale Select bits
11= 1:8 Prescale value
10= 1:4 Prescale value
01= 1:2 Prescale value
00= 1:1 Prescale value
T3SYNC: Timer3 External Clock Input Synchronization Control bit
(Not usable if the device clock comes from Timer1/Timer3.)
When TMR3CS = 1:
1= Do not synchronize external clock input
0= Synchronize external clock input
When TMR3CS = 0:
This bit is ignored. Timer3 uses the internal clock when TMR3CS = 0.
bit 1
bit 0
TMR3CS: Timer3 Clock Source Select bit
1= External clock input from Timer1 oscillator or T13CKI (on the rising edge after the first falling edge)
0= Internal clock (FOSC/4)
TMR3ON: Timer3 On bit
1= Enables Timer3
0= Stops Timer3
Note 1: Thess bits and the ECCP1 module are available on PIC18F4682/4685 devices only.
© 2007 Microchip Technology Inc.
Preliminary
DS39761B-page 159
PIC18F2682/2685/4682/4685
cycle (FOSC/4). When the bit is set, Timer3 increments
on every rising edge of the Timer1 external clock input
or the Timer1 oscillator if enabled.
14.1 Timer3 Operation
Timer3 can operate in one of three modes:
• Timer
As with Timer1, the RC1/T1OSI and RC0/T1OSO/
T13CKI pins become inputs when the Timer1 oscillator
is enabled. This means the values of TRISC<1:0> are
ignored and the pins are read as ‘0’.
• Synchronous Counter
• Asynchronous Counter
The operating mode is determined by the clock select
bit, TMR3CS (T3CON<1>). When TMR3CS is cleared
(= 0), Timer3 increments on every internal instruction
FIGURE 14-1:
TIMER3 BLOCK DIAGRAM
Timer1 Oscillator
1
1
0
T1OSO/T13CKI
T1OSI
Synchronize
Detect
Prescaler
1, 2, 4, 8
0
FOSC/4
Internal
Clock
2
Sleep Input
T1OSCEN(1)
TMR3CS
Timer3
On/Off
T3CKPS1:T3CKPS0
T3SYNC
TMR3ON
Set
TMR3IF
on Overflow
CCP1/ECCP1 Special Event Trigger
TCCPx
Clear TMR3
TMR3
TMR3L
High Byte
Note 1: When enable bit, T1OSCEN, is cleared, the inverter and feedback resistor are turned off to eliminate power drain.
FIGURE 14-2:
TIMER3 BLOCK DIAGRAM (16-BIT READ/WRITE MODE)
Timer1 Oscillator
Timer1 clock input
1
0
T1OSO/T13CKI
T1OSI
1
0
Prescaler
1, 2, 4, 8
Synchronize
Detect
FOSC/4
Internal
Clock
2
Sleep Input
T1OSCEN(1)
T3CKPS1:T3CKPS0
T3SYNC
TMR3CS
Timer3
On/Off
TMR3ON
Set
TMR3IF
on Overflow
CCP1/ECCP1 Special Event Trigger
TCCPx
Clear TMR3
TMR3
TMR3L
High Byte
8
Read TMR1L
Write TMR1L
8
8
TMR3H
8
8
Internal Data Bus
Note 1: When enable bit, T1OSCEN, is cleared, the inverter and feedback resistor are turned off to eliminate power drain.
DS39761B-page 160
Preliminary
© 2007 Microchip Technology Inc.
PIC18F2682/2685/4682/4685
14.2 Timer3 16-Bit Read/Write Mode
14.4 Timer3 Interrupt
Timer3 can be configured for 16-bit reads and writes
(see Figure 14-2). When the RD16 control bit
(T3CON<7>) is set, the address for TMR3H is mapped
to a buffer register for the high byte of Timer3. A read
from TMR3L will load the contents of the high byte of
Timer3 into the Timer3 High Byte Buffer register. This
provides the user with the ability to accurately read all
16 bits of Timer1 without having to determine whether
a read of the high byte, followed by a read of the low
byte, has become invalid due to a rollover between
reads.
The TMR3 register pair (TMR3H:TMR3L) increments
from 0000h to FFFFh and overflows to 0000h. The
Timer3 interrupt, if enabled, is generated on overflow
and is latched in the interrupt flag bit, TMR3IF
(PIR2<1>). This interrupt can be enabled or disabled
by setting or clearing the Timer3 Interrupt Enable bit,
TMR3IE (PIE2<1>).
14.5 Resetting Timer3 Using the
ECCP1 Special Event Trigger
If the ECCP1 module is configured to generate a
A write to the high byte of Timer3 must also take place
through the TMR3H Buffer register. The Timer3 high
byte is updated with the contents of TMR3H when a
write occurs to TMR3L. This allows a user to write all
16 bits to both the high and low bytes of Timer3 at once.
Special Event
Trigger
in
Compare
mode
(ECCP1M3:ECCP1M0 = 1011), this signal will reset
Timer3. It will also start an A/D conversion if the A/D
module is enabled (see Section 15.3.4 “Special
Event Trigger” for more information.).
The high byte of Timer3 is not directly readable or
writable in this mode. All reads and writes must take
place through the Timer3 High Byte Buffer register.
The module must be configured as either a timer or
synchronous counter to take advantage of this feature.
When used this way, the ECCPR1H:ECCPR1L register
pair effectively becomes a period register for Timer3.
Writes to TMR3H do not clear the Timer3 prescaler.
The prescaler is only cleared on writes to TMR3L.
If Timer3 is running in Asynchronous Counter mode,
the Reset operation may not work.
14.3 Using the Timer1 Oscillator as the
Timer3 Clock Source
In the event that a write to Timer3 coincides with a
Special Event Trigger from a CCP1 module, the write
will take precedence.
The Timer1 internal oscillator may be used as the clock
source for Timer3. The Timer1 oscillator is enabled by
setting the T1OSCEN (T1CON<3>) bit. To use it as the
Timer3 clock source, the TMR3CS bit must also be set.
As previously noted, this also configures Timer3 to
increment on every rising edge of the oscillator source.
Note:
The Special Event Triggers from the
ECCP1 module will not set the TMR3IF
interrupt flag bit (PIR2<1>).
The Timer1 oscillator is described in Section 12.0
“Timer1 Module”.
TABLE 14-1: REGISTERS ASSOCIATED WITH TIMER3 AS A TIMER/COUNTER
Reset
Values
on page
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
INTCON GIE/GIEH PEIE/GIEL TMR0IE
INT0IE
EEIF
RBIE
BCLIF
BCLIE
BCLIP
TMR0IF
HLVDIF
HLVDIE
HLVDIP
INT0IF
RBIF
49
52
52
51
51
51
50
51
PIR2
OSCFIF
OSCFIE
OSCFIP
CMIF(1)
CMIE(1)
CMIP(1)
—
—
—
TMR3IF ECCP1IF(1)
TMR3IE ECCP1IE(1)
TMR3IP ECCP1IP(1)
PIE2
EEIE
EEIP
IPR2
TMR3L
Timer3 Register, Low Byte
TMR3H Timer3 Register, High Byte
T1CON
T3CON
RD16
RD16
T1RUN
T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON
T3ECCP1(1) T3CKPS1 T3CKPS0 T3CCP1(1) T3SYNC TMR3CS TMR3ON
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the Timer3 module.
Note 1: These bits are unimplemented on PIC18F2682/2685 devices; always maintain these bits clear.
© 2007 Microchip Technology Inc.
Preliminary
DS39761B-page 161
PIC18F2682/2685/4682/4685
NOTES:
DS39761B-page 162
Preliminary
© 2007 Microchip Technology Inc.
PIC18F2682/2685/4682/4685
The CCP1 module contains a 16-bit register which can
15.0 CAPTURE/COMPARE/PWM
operate as a 16-bit Capture register, a 16-bit Compare
register or a PWM Master/Slave Duty Cycle register.
For the sake of clarity, all CCP1 module operation in the
following sections is described with respect to CCP1,
but is equally applicable to ECCP1.
(CCP1) MODULES
PIC18F2682/2685 devices have one CCP1 module.
PIC18F4682/4685 devices have two CCP1 (Capture/
Compare/PWM) modules. CCP1, discussed in this
chapter, implements standard Capture, Compare and
Pulse-Width Modulation (PWM) modes.
Capture/ and Compare operations described in this
chapter apply to all standard and Enhanced CCP1
modules. The operations of PWM mode, described in
Section 15.4 “PWM Mode”, apply to CCP1 only.
ECCP1 implements an Enhanced PWM mode. The
ECCP1 implementation is discussed in Section 16.0
“Enhanced
Capture/Compare/PWM
(ECCP1)
Module”.
REGISTER 15-1: CCP1CON: CAPTURE/COMPARE/PWM CONTROL REGISTER
U-0
—
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
DC1B1
DC1B0
CCP1M3
CCP1M2
CCP1M1
CCP1M0
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7-6
bit 5-4
Unimplemented: Read as ‘0’
DC1B1:DC1B0: CCP1 Module PWM Duty Cycle bit 1 and bit 0
Capture mode:
Unused.
Compare mode:
Unused.
PWM mode:
These bits are the two LSbs (bit 1 and bit 0) of the 10-bit PWM duty cycle. The eight MSbs
(DC1B9:DC1B2) of the duty cycle are found in CCPR1L.
bit 3-0
CCP1M3:CCP1M0: CCP1 Module Mode Select bits
0000= Capture/Compare/PWM disabled (resets CCP1 module)
0001= Reserved
0010= Compare mode; toggle output on match (CCP1IF bit is set)
0011= Reserved
0100= Capture mode; every falling edge or CAN message received (time-stamp)(1)
0101= Capture mode; every rising edge or CAN message received (time-stamp)(1)
0110= Capture mode; every 4th rising edge or every 4th CAN message received (time-stamp)(1)
0111= Capture mode; every 16th rising edge or every 16th CAN message received (time-stamp)(1)
1000= Compare mode; initialize CCP1 pin low; on compare match, force CCP1 pin high
(CCPIF bit is set)
1001= Compare mode; initialize CCP pin high; on compare match, force CCP1 pin low
(CCPIF bit is set)
1010= Compare mode; generate software interrupt on compare match (CCP1IF bit is set,
CCP1 pin reflects I/O state)
1011= Compare mode; trigger special event; reset timer (TMR1 or TMR3, CCP1IF bit is set)
11xx= PWM mode
Note 1: Selected by CANCAP (CIOCON<4>) bit; overrides the CCP1 input pin source.
© 2007 Microchip Technology Inc.
Preliminary
DS39761B-page 163
PIC18F2682/2685/4682/4685
TABLE 15-1: CCP1 MODE – TIMER
RESOURCE
CCP1/ECCP1 Mode
15.1 CCP1 Module Configuration
Each Capture/Compare/PWM module is associated
with a control register (CCP1CON or ECCP1CON) and
a data register (CCPR1 or ECCPR1). The data register,
in turn, is comprised of two 8-bit registers: CCPR1L or
ECCPR1L (low byte) and CCPR1H or ECCPR1H (high
byte). All registers are both readable and writable.
Timer Resource
Capture
Compare
PWM
Timer1 or Timer3
Timer1 or Timer3
Timer2
The assignment of a particular timer to a module is
determined by the Timer to CCP1/ECCP1 enable bits
in the T3CON register (Register 14-1). Both modules
may be active at any given time and may share the
same timer resource if they are configured to operate
in the same mode (Capture/Compare or PWM) at the
same time. The interactions between the two modules
are summarized in Figure 15-1 and Figure 15-2.
15.1.1
CCP1 MODULES AND TIMER
RESOURCES
The CCP1 modules utilize Timers 1, 2 or 3, depending
on the mode selected. Timer1 and Timer3 are available
to modules in Capture or Compare modes, while
Timer2 is available for modules in PWM mode.
TABLE 15-2: INTERACTIONS BETWEEN CCP1 AND ECCP1 FOR TIMER RESOURCES
CCP1 Mode ECCP1 Mode
Interaction
Capture
Capture
Each module can use TMR1 or TMR3 as the time base. Time base can be different for
each CCP1.
Capture
Compare
CCP1 can be configured for the Special Event Trigger to reset TMR1 or TMR3
(depending upon which time base is used). Automatic A/D conversions on trigger event
can also be done. Operation of CCP1 could be affected if it is using the same timer as a
time base.
Compare
Compare
Capture
CCP1 can be configured for the Special Event Trigger to reset TMR1 or TMR3
(depending upon which time base is used). Operation of CCP1 could be affected if it is
using the same timer as a time base.
Compare
Either module can be configured for the Special Event Trigger to reset the time base.
Automatic A/D conversions on ECCP1 trigger event can be done. Conflicts may occur if
both modules are using the same time base.
Capture
Compare
PWM*
PWM*
PWM*
*
PWM*
PWM*
None
None
Capture
Compare
PWM
None
None
Both PWMs will have the same frequency and update rate (TMR2 interrupt).
Includes standard and Enhanced PWM operation.
DS39761B-page 164
Preliminary
© 2007 Microchip Technology Inc.
PIC18F2682/2685/4682/4685
15.2.4
CCP1 PRESCALER
15.2 Capture Mode
There are four prescaler settings in Capture mode; they
are specified as part of the operating mode selected by
the mode select bits (CCP1M3:CCP1M0). Whenever
the CCP1 module is turned off or the CCP1 module is
not in Capture mode, the prescaler counter is cleared.
This means that any Reset will clear the prescaler
counter.
In Capture mode, the CCPR1H:CCPR1L (or
ECCPR1H:ECCPR1L) register pair captures the 16-bit
value of the TMR1 or TMR3 registers when an event
occurs on the CCP1/ECCP1 pin (RC2 for 28/40/44-pin
devices and RD4 for 40/44-pin devices). An event is
defined as one of the following:
• every falling edge
• every rising edge
Switching from one capture prescaler to another may
generate an interrupt. Also, the prescaler counter will
not be cleared; therefore, the first capture may be from
• every 4th rising edge
• every 16th rising edge
a
non-zero prescaler. Example 15-1 shows the
recommended method for switching between capture
prescalers. This example also clears the prescaler
counter and will not generate the “false” interrupt.
The event is selected by the mode select bits,
CCP1M3:CCP1M0 (CCP1CON<3:0>). When a capture
is made, the interrupt request flag bit, CCP1IF
(PIR1<2>), is set; it must be cleared in software. If
another capture occurs before the value in the CCPR1
register pair is read, the old captured value is overwritten
by the new captured value.
15.2.5
CAN MESSAGE TIME-STAMP
The CAN capture event occurs when a message is
received in any of the receive buffers. When config-
ured, the CAN module provides the trigger to the CCP1
module to cause a capture event. This feature is
provided to “time-stamp” the received CAN messages.
15.2.1
CCP1 PIN CONFIGURATION
In Capture mode, the appropriate CCP1/ECCP1 pin
should be configured as an input by setting the
corresponding TRIS direction bit.
This feature is enabled by setting the CANCAP bit of
the CAN I/O Control register (CIOCON<4>). The
message receive signal from the CAN module then
takes the place of the events on the RC2/CCP1 pin.
Note:
If RC2/CCP1 or RD4/PSP4/ECCP1/P1A
is configured as an output, a write to the
port can cause a capture condition.
If this feature is selected, then four different capture
options for CCP1M<3:0> are available:
15.2.2
TIMER1/TIMER3 MODE SELECTION
• 0100– every time a CAN message is received
• 0101– every time a CAN message is received
The timers that are to be used with the capture feature
(Timer1 and/or Timer3) must be running in Timer mode
or Synchronized Counter mode. In Asynchronous
Counter mode, the capture operation may not work.
The timer to be used with each CCP1 module is
selected in the T3CON register (see Section 15.1.1
“CCP1 Modules and Timer Resources”).
• 0110– every 4th time a CAN message is
received
• 0111– Capture mode, every 16th time a CAN
message is received
EXAMPLE 15-1:
CHANGING BETWEEN
CAPTURE PRESCALERS
15.2.3
SOFTWARE INTERRUPT
CLRF
CCP1CON
; Turn CCP1 module off
When the Capture mode is changed, a false capture
interrupt may be generated. The user should keep the
CCP1IE or ECCP1IE interrupt enable bit clear to avoid
false interrupts. The interrupt flag bit, CCP1IF or
ECCP1IF, should also be cleared following any such
change in operating mode.
MOVLW NEW_CAPT_PS ; Load WREG with the
; new prescaler mode
; value and CCP1 ON
; Load CCP1CON with
; this value
MOVWF CCP1CON
© 2007 Microchip Technology Inc.
Preliminary
DS39761B-page 165
PIC18F2682/2685/4682/4685
FIGURE 15-1:
CAPTURE MODE OPERATION BLOCK DIAGRAM
TMR3H
TMR3L
Set CCP1IF
T3ECCP1
TMR3
Enable
CCP1 pin
Prescaler
÷ 1, 4, 16
and
Edge Detect
CCPR1H
CCPR1L
TMR1
Enable
T3ECCP1
TMR1H
TMR1L
TMR3L
4
CCP1CON<3:0>
Q1:Q4
Set ECCP1IF
4
4
ECCP1CON<3:0>
TMR3H
T3CCP1
T3ECCP1
TMR3
Enable
ECCP1 pin
Prescaler
÷ 1, 4, 16
and
Edge Detect
ECCPR1H ECCPR1L
TMR1
Enable
T3ECCP1
T3CCP1
TMR1H
TMR1L
DS39761B-page 166
Preliminary
© 2007 Microchip Technology Inc.
PIC18F2682/2685/4682/4685
15.3.2
TIMER1/TIMER3 MODE SELECTION
15.3 Compare Mode
Timer1 and/or Timer3 must be running in Timer mode
or Synchronized Counter mode if the CCP1 module is
using the compare feature. In Asynchronous Counter
mode, the compare operation may not work.
In Compare mode, the 16-bit CCPR1 register value is
constantly compared against either the TMR1 or TMR3
register pair value. When a match occurs, the CCP1
pin can be:
• driven high
15.3.3
SOFTWARE INTERRUPT MODE
• driven low
When the Generate Software Interrupt mode is chosen
(CCP1M3:CCP1M0 = 1010), the CCP1 pin is not
affected. Only a CCP1 interrupt is generated, if enabled
and the CCP1IE bit is set.
• toggled (high-to-low or low-to-high)
• remain unchanged (that is, reflects the state of the
I/O latch)
The action on the pin is based on the value of the mode
select bits (CCP1M3:CCP1M0). At the same time, the
interrupt flag bit, CCP1IF, is set.
15.3.4
SPECIAL EVENT TRIGGER
Both CCP1 modules are equipped with a Special
Event Trigger. This is an internal hardware signal
generated in Compare mode to trigger actions by
other modules. The Special Event Trigger is enabled
by selecting the Compare Special Event Trigger mode
(CCP1M3:CCP1M0 = 1011).
15.3.1
CCP1 PIN CONFIGURATION
The user must configure the CCP1 (ECCP1) pin as an
output by clearing the appropriate TRIS bit.
Note:
Clearing the CCP1CON register will force
the RC2 compare output latch to the default
low level. This is not the PORTC I/O data
latch.
For either the CCP1/ECCP1 module, the Special Event
Trigger resets the timer register pair for whichever timer
resource is currently assigned as the module’s time
base. This allows the CCPR1 (ECCPR1) registers to
serve as a programmable period register for either
timer.
FIGURE 15-2:
COMPARE MODE OPERATION BLOCK DIAGRAM
Special Event Trigger
(Timer1 Reset)
Set CCP1IF
CCPR1H
CCPR1L
CCP1 pin
S
R
Q
Compare
Match
Output
Logic
Comparator
TRIS
Output Enable
4
CCP1CON<3:0>
0
1
TMR1H
TMR3H
TMR1L
TMR3L
0
1
Special Event Trigger
(Timer1/Timer3 Reset, A/D Trigger)
T3CCP1
T3ECCP1
Set CCP1IF
ECCP1 pin
S
R
Q
Compare
Match
Output
Logic
Comparator
TRIS
Output Enable
4
ECCPR1H ECCPR1L
ECCP1CON<3:0>
© 2007 Microchip Technology Inc.
Preliminary
DS39761B-page 167
PIC18F2682/2685/4682/4685
TABLE 15-3: REGISTERS ASSOCIATED WITH CAPTURE, COMPARE, TIMER1 AND TIMER3
Reset
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Values
on page
INTCON
GIE/GIEH PEIE/GIEL TMR0IE
INT0IE
RI
RBIE
TO
TMR0IF
PD
INT0IF
POR
RBIF
BOR
49
50
52
52
52
52
52
51
52
52
50
50
50
51
51
51
51
51
51
51
51
51
(2)
RCON
IPR1
IPEN
SBOREN
ADIP
—
RCIP
RCIF
RCIE
—
(1)
PSPIP
PSPIF
PSPIE
TXIP
TXIF
TXIE
EEIP
EEIF
EEIE
SSPIP
SSPIF
SSPIE
BCLIP
BCLIF
BCLIE
CCP1IP
CCP1IF
CCP1IE
HLVDIP
HLVDIF
HLVDIE
TMR2IP
TMR2IF
TMR2IE
TMR1IP
TMR1IF
TMR1IE
(1)
(1)
PIR1
ADIF
PIE1
ADIE
(1)
(1)
(1)
(1)
IPR2
CMIP
TMR3IP ECCP1IP
TMR3IF ECCP1IF
TMR3IE ECCP1IE
OSCFIP
OSCFIF
OSCFIE
(1)
PIR2
CMIF
—
(1)
PIE2
CMIE
—
TRISB
TRISC
TMR1L
TMR1H
T1CON
TMR3H
TMR3L
T3CON
CCPR1L
CCPR1H
CCP1CON
PORTB Data Direction Register
PORTC Data Direction Register
Timer1 Register Low Byte
Timer1 Register High Byte
RD16
T1RUN
T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON
Timer3 Register High Byte
Timer3 Register Low Byte
(1)
(1)
RD16
T3ECCP1
T3CKPS1 T3CKPS0 T3CCP1
T3SYNC TMR3CS TMR3ON
Capture/Compare/PWM Register 1 Low Byte
Capture/Compare/PWM Register 1 High Byte
—
—
DC1B1
DC1B0
CCP1M3 CCP1M2 CCP1M1
CCP1M0
(1)
ECCPR1L
ECCPR1H
Enhanced Capture/Compare/PWM Register 1 Low Byte
Enhanced Capture/Compare/PWM Register 1 High Byte
(1)
(1)
ECCP1CON EPWM1M1 EPWM1M0 EDC1B1 EDC1B0 ECCP1M3 ECCP1M2 ECCP1M1 ECCP1M0
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by Capture and Compare, Timer1 or Timer3.
Note 1: These bits or registers are available on PIC18F4682/4685 devices only.
2: The SBOREN bit is only available when CONFIG2L<1:0> = 01; otherwise, it is disabled and reads as ‘0’.
DS39761B-page 168
Preliminary
© 2007 Microchip Technology Inc.
PIC18F2682/2685/4682/4685
FIGURE 15-4:
PWM OUTPUT
15.4 PWM Mode
Period
In Pulse-Width Modulation (PWM) mode, the CCP1 pin
produces up to a 10-bit resolution PWM output. Since
the CCP1 pin is multiplexed with a PORTB or PORTC
data latch, the appropriate TRIS bit must be cleared to
make the CCP1 pin an output.
Duty Cycle
TMR2 = PR2
Note:
Clearing the CCP1CON register will force
the RC2 output latch to the default low
level. This is not the PORTC I/O data
latch.
TMR2 = Duty Cycle
TMR2 = PR2
15.4.1
PWM PERIOD
Figure 15-3 shows a simplified block diagram of the
CCP1 module in PWM mode.
The PWM period is specified by writing to the PR2
(PR4) register. The PWM period can be calculated
using the following formula.
For a step-by-step procedure on how to set up the
CCP1 module for PWM operation, see Section 15.4.4
“Setup for PWM Operation”.
EQUATION 15-1:
PWM Period = [(PR2) + 1] • 4 • TOSC •
(TMR2 Prescale Value)
FIGURE 15-3:
SIMPLIFIED PWM BLOCK
DIAGRAM
PWM frequency is defined as 1/[PWM period].
CCP1CON<5:4>
Duty Cycle Registers
When TMR1 (TMR3) is equal to PR2 (PR4), the
following three events occur on the next increment
cycle:
CCPR1L
• TMR2 is cleared
CCPR1H (Slave)
Comparator
• The CCP1 pin is set (exception: if PWM duty
cycle = 0%, the CCP1 pin will not be set)
• The PWM duty cycle is latched from CCPR1L into
CCPR1H
R
S
Q
RC2/CCP1
PORTC<2>
Note:
The Timer2 postscaler (see Section 13.0
“Timer2 Module”) is not used in the
determination of the PWM frequency. The
postscaler could be used to have a servo
update rate at a different frequency than
the PWM output.
TMR2
(Note 1)
TRISC<2>
Comparator
PR2
Clear Timer,
CCP1 pin and
latch D.C.
15.4.2
PWM DUTY CYCLE
Note 1: The 8-bit TMR2 value is concatenated with the 2-bit
internal Q clock, or 2 bits of the prescaler, to create
the 10-bit time base.
The PWM duty cycle is specified by writing to the
CCPR1L register and to the CCP1CON<5:4> bits. Up
to 10-bit resolution is available. The CCPR1L contains
the eight MSbs and the CCP1CON<5:4> contains the
two LSbs. This 10-bit value is represented by
CCPR1L:CCP1CON<5:4>. The following equation is
used to calculate the PWM duty cycle in time.
A PWM output (Figure 15-4) has a time base (period)
and a time that the output stays high (duty cycle). The
frequency of the PWM is the inverse of the period (1/
period).
EQUATION 15-2:
PWM Duty Cycle = (CCPR1L:CCP1CON<5:4>) •
TOSC • (TMR2 Prescale Value)
CCPR1L and CCP1CON<5:4> can be written to at any
time, but the duty cycle value is not latched into
CCPR1H until after a match between PR2 and TMR2
occurs (i.e., the period is complete). In PWM mode,
CCPR1H is a read-only register.
© 2007 Microchip Technology Inc.
Preliminary
DS39761B-page 169
PIC18F2682/2685/4682/4685
The CCPR1H register and a 2-bit internal latch are
used to double-buffer the PWM duty cycle. This
double-buffering is essential for glitchless PWM
operation.
EQUATION 15-3:
FOSC
FPWM
⎛
⎝
⎞
⎠
log
bits
PWM Resolution (max) =
log(2)
When the CCPR1H and 2-bit latch match TMR2,
concatenated with an internal 2-bit Q clock or 2 bits of
the TMR2 prescaler, the CCP1 pin is cleared.
Note:
If the PWM duty cycle value is longer than
the PWM period, the CCP1 pin will not be
cleared.
The maximum PWM resolution (bits) for a given PWM
frequency is given by the equation.
TABLE 15-4: EXAMPLE PWM FREQUENCIES AND RESOLUTIONS AT 40 MHz
PWM Frequency
2.44 kHz
9.77 kHz
39.06 kHz 156.25 kHz 312.50 kHz 416.67 kHz
Timer Prescaler (1, 4, 16)
PR2 Value
16
FFh
14
4
1
1
3Fh
8
1
1Fh
7
1
FFh
12
FFh
10
17h
6.58
Maximum Resolution (bits)
15.4.3
PWM AUTO-SHUTDOWN
(ECCP1 ONLY)
15.4.4
SETUP FOR PWM OPERATION
The following steps should be taken when configuring
the CCP1 module for PWM operation:
The PWM auto-shutdown features of the Enhanced
CCP1 module are available to ECCP1 in PIC18F4682/
4685 (40/44-pin) devices. The operation of this feature
is discussed in detail in Section 16.4.7 “Enhanced
PWM Auto-Shutdown”.
1. Set the PWM period by writing to the PR2
register.
2. Set the PWM duty cycle by writing to the
CCPR1L register and CCP1CON<5:4> bits.
Auto-shutdown features are not available for CCP1.
3. Make the CCP1 pin an output by clearing the
appropriate TRIS bit.
4. Set the TMR2 prescale value, then enable
Timer2 by writing to T2CON.
5. Configure the CCP1 module for PWM operation.
DS39761B-page 170
Preliminary
© 2007 Microchip Technology Inc.
PIC18F2682/2685/4682/4685
TABLE 15-5: REGISTERS ASSOCIATED WITH PWM AND TIMER2
Reset
Values
on page
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
INTCON
GIE/GIEH PEIE/GIEL
TMR0IE
—
INT0IE
RI
RBIE
TO
TMR0IF
PD
INT0IF
POR
RBIF
BOR
49
50
52
52
52
52
52
50
50
50
51
51
51
51
51
51
(2)
RCON
PIR1
IPEN
SBOREN
ADIF
(1)
PSPIF
PSPIE
PSPIP
RCIF
RCIE
RCIP
TXIF
TXIE
TXIP
SSPIF
SSPIE
SSPIP
CCP1IF
CCP1IE
CCP1IP
TMR2IF
TMR2IE
TMR2IP
TMR1IF
TMR1IE
TMR1IP
(1)
(1)
PIE1
ADIE
IPR1
ADIP
TRISB
TRISC
TMR2
PORTB Data Direction Register
PORTC Data Direction Register
Timer2 Register
PR2
Timer2 Period Register
T2CON
CCPR1L
CCPR1H
CCP1CON
—
T2OUTPS3 T2OUTPS2 T2OUTPS1 T2OUTPS0 TMR2ON T2CKPS1 T2CKPS0
Capture/Compare/PWM Register 1 Low Byte
Capture/Compare/PWM Register 1 High Byte
—
—
DC1B1
DC1B0
CCP1M3 CCP1M2 CCP1M1 CCP1M0
(1)
ECCPR1L
ECCPR1H
Enhanced Capture/Compare/PWM Register 1 Low Byte
Enhanced Capture/Compare/PWM Register 1 High Byte
(1)
(1)
ECCP1CON EPWM1M1 EPWM1M0 EDC1B1
EDC1B0 ECCP1M3 ECCP1M2 ECCP1M1 ECCP1M0
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PWM or Timer2.
Note 1: These bits or registers are available on PIC18F4682/4685 devices only.
2: The SBOREN bit is only available when CONFIG2L<1:0> = 01; otherwise, it is disabled and reads as ‘0’.
© 2007 Microchip Technology Inc.
Preliminary
DS39761B-page 171
PIC18F2682/2685/4682/4685
NOTES:
DS39761B-page 172
Preliminary
© 2007 Microchip Technology Inc.
PIC18F2682/2685/4682/4685
enhanced features are discussed in detail in
Section 16.4 “Enhanced PWM Mode”. Capture,
Compare and single output PWM functions of the
ECCP1 module are the same as described for the
standard CCP1 module.
16.0 ENHANCED CAPTURE/
COMPARE/PWM (ECCP1)
MODULE
Note:
The ECCP1 module is implemented only
in PIC18F4682/4685 (40/44-pin) devices.
The control register for the Enhanced CCP1 module is
shown in Register 16-1. It differs from the CCP1CON
register in the PIC18F2682/2685 devices in that the
two Most Significant bits are implemented to control
PWM functionality.
In PIC18F4682/4685 devices, ECCP1 is implemented
as a standard CCP1 module with Enhanced PWM
capabilities. These include the provision for 2 or 4
output channels, user-selectable polarity, dead-band
control and automatic shutdown and restart. The
REGISTER 16-1: ECCP1CON: ENHANCED CAPTURE/COMPARE/PWM CONTROL REGISTER
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
EPWM1M1
EPWM1M0
EDC1B1
EDC1B0
ECCP1M3
ECCP1M2
ECCP1M1
ECCP1M0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
-n = Value at POR
bit 7-6
EPWM1M1:EPWM1M0: Enhanced PWM Output Configuration bits
If ECCP1M3:ECCP1M2 = 00, 01, 10:
xx= P1A assigned as Capture/Compare input/output; P1B, P1C, P1D assigned as port pins
If ECCP1M3:ECCP1M2 = 11:
00= Single output: P1A modulated; P1B, P1C, P1D assigned as port pins
01= Full-bridge output forward: P1D modulated; P1A active; P1B, P1C inactive
10= Half-bridge output: P1A, P1B modulated with dead-band control; P1C, P1D assigned as port pins
11= Full-bridge output reverse: P1B modulated; P1C active; P1A, P1D inactive
bit 5-4
EDC1B1:EDC1B0: ECCP1 Module PWM Duty Cycle bit 1 and bit 0
Capture mode:
Unused.
Compare mode:
Unused.
PWM mode:
These bits are the two LSbs of the 10-bit PWM duty cycle. The eight MSbs of the duty cycle are found
in ECCPR1L.
bit 3-0
ECCP1M3:ECCP1M0: Enhanced CCP1 Mode Select bits
0000= Capture/Compare/PWM off (resets ECCP1 module)
0001= Reserved
0010= Compare mode; toggle output on match
0011= Reserved
0100= Capture mode; every falling edge
0101= Capture mode; every rising edge
0110= Capture mode; every 4th rising edge
0111= Capture mode; every 16th rising edge
1000= Compare mode; initialize ECCP1 pin low; set output on compare match (set ECCP1IF)
1001= Compare mode; initialize ECCP1 pin high; clear output on compare match (set ECCP1IF)
1010= Compare mode; generate software interrupt only; ECCP1 pin reverts to I/O state
1011= Compare mode; trigger special event (ECCP1 resets TMR1 or TMR3, sets ECCP1IF bit and
starts the A/D conversion on ECCP1 match)
1100= PWM mode; P1A, P1C active-high; P1B, P1D active-high
1101= PWM mode; P1A, P1C active-high; P1B, P1D active-low
1110= PWM mode; P1A, P1C active-low; P1B, P1D active-high
1111= PWM mode; P1A, P1C active-low; P1B, P1D active-low
© 2007 Microchip Technology Inc.
Preliminary
DS39761B-page 173
PIC18F2682/2685/4682/4685
In addition to the expanded range of modes available
16.2 Capture and Compare Modes
through the ECCP1CON register, the ECCP1 module
has two additional registers associated with Enhanced
PWM operation and auto-shutdown features. They are:
Except for the operation of the Special Event Trigger
discussed below, the Capture and Compare modes of
the ECCP1 module are identical in operation to that of
CCP1. These are discussed in detail in Section 15.2
“Capture Mode” and Section 15.3 “Compare Mode”.
• ECCP1DEL (Dead-Band Delay)
• ECCP1AS (Auto-Shutdown Configuration)
16.1 ECCP1 Outputs and Configuration
16.2.1
SPECIAL EVENT TRIGGER
The Special Event Trigger output of ECCP1 resets the
TMR1 or TMR3 register pair, depending on which timer
resource is currently selected. This allows the ECCP1
register to effectively be a 16-bit programmable period
register for Timer1 or Timer3. The Special Event
Trigger for ECCP1 can also start an A/D conversion. In
order to start the conversion, the A/D converter must be
previously enabled.
The Enhanced CCP1 module may have up to four
PWM outputs, depending on the selected operating
mode. These outputs, designated P1A through P1D,
are multiplexed with I/O pins on PORTD. The outputs
that are active depend on the ECCP1 operating mode
selected. The pin assignments are summarized in
Table 16-1.
To configure the I/O pins as PWM outputs, the proper
PWM mode must be selected by setting the
EPWM1M1:EPWM1M0 and ECCP1M3:ECCP1M0
bits. The appropriate TRISD direction bits for the port
pins must also be set as outputs.
16.3 Standard PWM Mode
When configured in Single Output mode, the ECCP1
module functions identically to the standard CCP1
module in PWM mode, as described in Section 15.4
“PWM Mode”. This is also sometimes referred to as
“Compatible CCP1” mode, as in Table 16-1.
16.1.1
ECCP1 MODULES AND TIMER
RESOURCES
Like the standard CCP1 modules, the ECCP1 module
can utilize Timers 1, 2 or 3, depending on the mode
selected. Timer1 and Timer3 are available for modules
in Capture or Compare modes, while Timer2 is
available for modules in PWM mode. Interactions
between the standard and Enhanced CCP1 modules
are identical to those described for standard CCP1
modules. Additional details on timer resources are
provided in Section 15.1.1 “CCP1 Modules and
Timer Resources”.
Note: When setting up single output PWM
operations, users are free to use either of the
processes described in Section 15.4.4
“Setup
for
PWM
Operation”
or
Section 16.4.9 “Setup for PWM Operation”.
The latter is more generic but will work for
either single or multi-output PWM.
TABLE 16-1: PIN ASSIGNMENTS FOR VARIOUS ECCP1 MODES
CCP1CON
ECCP1 Mode
RD4
RD5
RD6
RD7
Configuration
All PIC18F4682/4685 Devices:
Compatible CCP1
Dual PWM
00xx 11xx
10xx 11xx
x1xx 11xx
ECCP1
P1A
RD5/PSP5
RD6/PSP6
RD6/PSP6
P1C
RD7/PSP7
RD7/PSP7
P1D
P1B
P1B
Quad PWM
P1A
Legend: x= Don’t care. Shaded cells indicate pin assignments not used by ECCP1 in a given mode.
DS39761B-page 174
Preliminary
© 2007 Microchip Technology Inc.
PIC18F2682/2685/4682/4685
16.4.1
PWM PERIOD
16.4 Enhanced PWM Mode
The PWM period is specified by writing to the PR2
register. The PWM period can be calculated using the
following equation.
The Enhanced PWM mode provides additional PWM
output options for a broader range of control applica-
tions. The module is a backward compatible version of
the standard CCP1 module and offers up to four outputs,
designated P1A through P1D. Users are also able to
select the polarity of the signal (either active-high or
active-low). The module’s output mode and polarity are
configured by setting the EPWM1M1:EPWM1M0 and
ECCP1M3:ECCP1M0 bits of the ECCP1CON register.
EQUATION 16-1:
PWM Period = [(PR2) + 1] • 4 • TOSC •
(TMR2 Prescale Value)
PWM frequency is defined as 1/[PWM period]. When
TMR2 is equal to PR2, the following three events occur
on the next increment cycle:
Figure 16-1 shows a simplified block diagram of PWM
operation. All control registers are double-buffered and
are loaded at the beginning of a new PWM cycle (the
period boundary when Timer2 resets) in order to
prevent glitches on any of the outputs. The exception is
the PWM Dead-Band Delay register, ECCP1DEL,
which is loaded at either the duty cycle boundary or the
boundary period (whichever comes first). Because of
the buffering, the module waits until the assigned timer
resets instead of starting immediately. This means that
Enhanced PWM waveforms do not exactly match the
standard PWM waveforms, but are instead offset by
one full instruction cycle (4 TOSC).
• TMR2 is cleared
• The ECCP1 pin is set (if PWM duty cycle = 0%,
the ECCP1 pin will not be set)
• The PWM duty cycle is copied from ECCPR1L
into ECCPR1H
Note:
The Timer2 postscaler (see Section 13.0
“Timer2 Module”) is not used in the
determination of the PWM frequency. The
postscaler could be used to have a servo
update rate at a different frequency than
the PWM output.
As before, the user must manually configure the
appropriate TRIS bits for output.
FIGURE 16-1:
SIMPLIFIED BLOCK DIAGRAM OF THE ENHANCED PWM MODULE
ECCP1CON<5:4>
EPWM1M<1:0>
ECCP1M<3:0>
4
Duty Cycle Registers
2
ECCPR1L
ECCP1/P1A
ECCP1/P1A
P1B
TRISD<4>
TRISD<5>
TRISD<6>
TRISD<7>
ECCPR1H (Slave)
Comparator
TMR2
P1B
Output
Controller
R
S
Q
P1C
P1C
(Note 1)
P1D
P1D
Comparator
PR2
Clear Timer,
set ECCP1 pin and
latch D.C.
ECCP1DEL
Note: The 8-bit TMR2 register is concatenated with the 2-bit internal Q clock, or 2 bits of the prescaler, to create the 10-bit time base.
© 2007 Microchip Technology Inc.
Preliminary
DS39761B-page 175
PIC18F2682/2685/4682/4685
16.4.2
PWM DUTY CYCLE
EQUATION 16-3:
The PWM duty cycle is specified by writing to the
ECCPR1L register and to the ECCP1CON<5:4> bits.
Up to 10-bit resolution is available. The ECCPR1L
contains the eight MSbs and the ECCP1CON<5:4>
contains the two LSbs. This 10-bit value is represented
by ECCPR1L:ECCP1CON<5:4>. The PWM duty cycle
is calculated by the following equation.
FOSC
FPWM
log
(
)
bits
PWM Resolution (max) =
log(2)
Note:
If the PWM duty cycle value is longer than
the PWM period, the ECCP1 pin will not
be cleared.
EQUATION 16-2:
PWM Duty Cycle = (ECCPR1L:ECCP1CON<5:4> •
TOSC • (TMR2 Prescale Value)
16.4.3
PWM OUTPUT CONFIGURATIONS
The EPWM1M1:EPWM1M0 bits in the ECCP1CON
register allow one of four configurations:
ECCPR1L and ECCP1CON<5:4> can be written to at
any time, but the duty cycle value is not copied into
ECCPR1H until a match between PR2 and TMR2
occurs (i.e., the period is complete). In PWM mode,
ECCPR1H is a read-only register.
• Single Output
• Half-Bridge Output
• Full-Bridge Output, Forward mode
• Full-Bridge Output, Reverse mode
The ECCPR1H register and a 2-bit internal latch are
used to double-buffer the PWM duty cycle. This
double-buffering is essential for glitchless PWM opera-
tion. When the ECCPR1H and 2-bit latch match TMR2,
concatenated with an internal 2-bit Q clock or two bits
of the TMR2 prescaler, the ECCP1 pin is cleared. The
maximum PWM resolution (bits) for a given PWM
frequency is given by the following equation.
The Single Output mode is the standard PWM mode
discussed in Section 16.4 “Enhanced PWM Mode”.
The Half-Bridge and Full-Bridge Output modes are
covered in detail in the sections that follow.
The general relationship of the outputs in all
configurations is summarized in Figure 16-2.
TABLE 16-2: EXAMPLE PWM FREQUENCIES AND RESOLUTIONS AT 40 MHz
PWM Frequency
2.44 kHz
9.77 kHz
39.06 kHz 156.25 kHz 312.50 kHz 416.67 kHz
Timer Prescaler (1, 4, 16)
PR2 Value
16
FFh
10
4
1
1
3Fh
8
1
1Fh
7
1
FFh
10
FFh
10
17h
6.58
Maximum Resolution (bits)
DS39761B-page 176
Preliminary
© 2007 Microchip Technology Inc.
PIC18F2682/2685/4682/4685
FIGURE 16-2:
PWM OUTPUT RELATIONSHIPS (ACTIVE-HIGH STATE)
0
PR2 + 1
Duty
Cycle
ECCP1CON
SIGNAL
<7:6>
Period
P1A Modulated
P1A Modulated
P1B Modulated
P1A Active
(Single Output)
00
10
(1)
(1)
Delay
Delay
(Half-Bridge)
P1B Inactive
P1C Inactive
P1D Modulated
P1A Inactive
P1B Modulated
P1C Active
(Full-Bridge,
Forward)
01
(Full-Bridge,
Reverse)
11
P1D Inactive
FIGURE 16-3:
PWM OUTPUT RELATIONSHIPS (ACTIVE-LOW STATE)
0
PR2 + 1
Duty
Cycle
ECCP1CON
<7:6>
SIGNAL
Period
P1A Modulated
P1A Modulated
P1B Modulated
P1A Active
(Single Output)
(Half-Bridge)
00
10
(1)
(1)
Delay
Delay
P1B Inactive
P1C Inactive
P1D Modulated
P1A Inactive
P1B Modulated
P1C Active
(Full-Bridge,
Forward)
01
(Full-Bridge,
Reverse)
11
P1D Inactive
Relationships:
•
•
•
Period = 4 * TOSC * (PR2 + 1) * (TMR2 Prescale Value)
Duty Cycle = TOSC * (ECCPR1L<7:0>:ECCP1CON<5:4>) * (TMR2 Prescale Value)
Delay = 4 * TOSC * (ECCP1DEL<6:0>)
Note 1: Dead-band delay is programmed using the ECCP1DEL register (Section 16.4.6 “Programmable Dead-Band Delay”).
© 2007 Microchip Technology Inc.
Preliminary
DS39761B-page 177
PIC18F2682/2685/4682/4685
16.4.4
HALF-BRIDGE MODE
FIGURE 16-4:
HALF-BRIDGE PWM
OUTPUT
In the Half-Bridge Output mode, two pins are used as
outputs to drive push-pull loads. The PWM output
signal is output on the P1A pin, while the complemen-
tary PWM output signal is output on the P1B pin
(Figure 16-4). This mode can be used for half-bridge
applications, as shown in Figure 16-5, or for full-bridge
applications where four power switches are being
modulated with two PWM signals.
Period
Period
Duty Cycle
(2)
(2)
P1A
P1B
td
td
In Half-Bridge Output mode, the programmable dead-
band delay can be used to prevent shoot-through
current in half-bridge power devices. The value of bits,
PDC6:PDC0, sets the number of instruction cycles
before the output is driven active. If the value is greater
than the duty cycle, the corresponding output remains
inactive during the entire cycle. See Section 16.4.6
“Programmable Dead-Band Delay” for more details
of the dead-band delay operations.
(1)
(1)
(1)
td = Dead-Band Delay
Note 1: At this time, the TMR2 register is equal to the
PR2 register.
2: Output signals are shown as active-high.
Since the P1A and P1B outputs are multiplexed with
the PORTD<4> and PORTD<5> data latches, the
TRISD<4> and TRISD<5> bits must be cleared to
configure P1A and P1B as outputs.
FIGURE 16-5:
EXAMPLES OF HALF-BRIDGE OUTPUT MODE APPLICATIONS
V+
Standard Half-Bridge Circuit (“Push-Pull”)
PIC18F268X/468X
FET
Driver
+
V
-
P1A
Load
FET
Driver
+
V
-
P1B
V-
Half-Bridge Output Driving a Full-Bridge Circuit
V+
PIC18F268X/468X
FET
Driver
FET
Driver
P1A
Load
FET
FET
Driver
Driver
P1B
V-
DS39761B-page 178
Preliminary
© 2007 Microchip Technology Inc.
PIC18F2682/2685/4682/4685
P1A, P1B, P1C and P1D outputs are multiplexed with
the PORTD<4>, PORTD<5>, PORTD<6> and
PORTD<7> data latches. The TRISD<4>, TRISD<5>,
TRISD<6> and TRISD<7> bits must be cleared to
make the P1A, P1B, P1C and P1D pins outputs.
16.4.5
FULL-BRIDGE MODE
In Full-Bridge Output mode, four pins are used as
outputs; however, only two outputs are active at a time.
In the Forward mode, pin P1A is continuously active
and pin P1D is modulated. In the Reverse mode, pin
P1C is continuously active and pin P1B is modulated.
These are illustrated in Figure 16-6.
FIGURE 16-6:
FULL-BRIDGE PWM OUTPUT
Forward Mode
Period
(2)
P1A
Duty Cycle
(2)
(2)
P1B
P1C
(2)
P1D
(1)
(1)
Reverse Mode
Period
Duty Cycle
(2)
P1A
(2)
P1B
(2)
P1C
(2)
P1D
(1)
(1)
Note 1: At this time, the TMR2 register is equal to the PR2 register.
Note 2: Output signal is shown as active-high.
© 2007 Microchip Technology Inc.
Preliminary
DS39761B-page 179
PIC18F2682/2685/4682/4685
FIGURE 16-7:
EXAMPLE OF FULL-BRIDGE APPLICATION
V+
PIC18F268X/468X
QA
QC
FET
Driver
FET
Driver
P1A
Load
P1B
FET
Driver
FET
Driver
P1C
P1D
QB
QD
V-
Figure 16-9 shows an example where the PWM
direction changes from forward to reverse at a near
100% duty cycle. At time t1, the outputs P1A and P1D
become inactive, while output P1C becomes active. In
this example, since the turn-off time of the power
devices is longer than the turn-on time, a shoot-through
current may flow through power devices, QC and QD
(see Figure 16-7), for the duration of ‘t’. The same
phenomenon will occur to power devices, QA and QB,
for PWM direction change from reverse to forward.
16.4.5.1
Direction Change in Full-Bridge Mode
In the Full-Bridge Output mode, the EPWM1M1 bit in
the ECCP1CON register allows the user to control the
forward/reverse direction. When the application
firmware changes this direction control bit, the module
will assume the new direction on the next PWM cycle.
Just before the end of the current PWM period, the
modulated outputs (P1B and P1D) are placed in their
inactive state, while the unmodulated outputs (P1A and
P1C) are switched to drive in the opposite direction.
This occurs in a time interval of (4 TOSC * (Timer2
Prescale Value)) before the next PWM period begins.
The Timer2 prescaler will either be 1, 4 or 16, depend-
ing on the value of the T2CKPS bits (T2CON<1:0>).
During the interval from the switch of the unmodulated
outputs to the beginning of the next period, the
modulated outputs (P1B and P1D) remain inactive.
This relationship is shown in Figure 16-8.
If changing PWM direction at high duty cycle is required
for an application, one of the following requirements
must be met:
1. Reduce PWM for
changing directions.
a PWM period before
2. Use switch drivers that can drive the switches off
faster than they can drive them on.
Other options to prevent shoot-through current may
exist.
Note that in the Full-Bridge Output mode, the ECCP1
module does not provide any dead-band delay. In
general, since only one output is modulated at all times,
dead-band delay is not required. However, there is a
situation where a dead-band delay might be required.
This situation occurs when both of the following
conditions are true:
1. The direction of the PWM output changes when
the duty cycle of the output is at or near 100%.
2. The turn-off time of the power switch, including
the power device and driver circuit, is greater
than the turn-on time.
DS39761B-page 180
Preliminary
© 2007 Microchip Technology Inc.
PIC18F2682/2685/4682/4685
FIGURE 16-8:
PWM DIRECTION CHANGE
(1)
Period
Period
SIGNAL
P1A (Active-High)
P1B (Active-High)
DC
P1C (Active-High)
P1D (Active-High)
(Note 2)
DC
Note 1: The direction bit in the ECCP1 Control register (ECCP1CON<7>) is written any time during the PWM cycle.
2: When changing directions, the P1A and P1C signals switch before the end of the current PWM cycle at
intervals of 4 TOSC, 16 TOSC or 64 TOSC, depending on the Timer2 prescaler value. The modulated P1B and
P1D signals are inactive at this time.
FIGURE 16-9:
PWM DIRECTION CHANGE AT NEAR 100% DUTY CYCLE
Forward Period
Reverse Period
t1
(1)
(1)
P1A
P1B
DC
(1)
(1)
(1)
P1C
P1D
DC
(2)
t
ON
External Switch C
(3)
t
OFF
(1)
External Switch D
Potential
(2,3)
– t
ON
t = t
OFF
Shoot-Through
(1)
Current
Note 1: All signals are shown as active-high.
2:
3:
t
is the turn-on delay of power switch QC and its driver.
ON
t
is the turn-off delay of power switch QD and its driver.
OFF
© 2007 Microchip Technology Inc.
Preliminary
DS39761B-page 181
PIC18F2682/2685/4682/4685
A shutdown event can be caused by either of the
comparator modules, a low level on the RB0/INT0/
FLT0/AN10 pin, or any combination of these three
sources. The comparators may be used to monitor a
voltage input proportional to a current being monitored in
the bridge circuit. If the voltage exceeds a threshold, the
comparator switches state and triggers a shutdown.
Alternatively, a digital signal on the INT0 pin can also
trigger a shutdown. The auto-shutdown feature can be
disabled by not selecting any auto-shutdown sources.
The auto-shutdown sources to be used are selected
using the ECCPAS2:ECCPAS0 bits (bits<6:4> of the
ECCP1AS register).
16.4.6
PROGRAMMABLE DEAD-BAND
DELAY
Note:
Programmable dead-band delay is not
implemented in PIC18F2682/2685 devices
with standard CCP1 modules.
In half-bridge applications where all power switches are
modulated at the PWM frequency at all times, the power
switches normally require more time to turn off than to
turn on. If both the upper and lower power switches are
switched at the same time (one turned on and the other
turned off), both switches may be on for a short period of
time until one switch completely turns off. During this
brief interval, a very high current (shoot-through current)
may flow through both power switches, shorting the
bridge supply. To avoid this potentially destructive shoot-
through current from flowing during switching, turning on
either of the power switches is normally delayed to allow
the other switch to completely turn off.
When a shutdown occurs, the output pins are
asynchronously placed in their shutdown states, spec-
ified by the PSSAC1:PSSAC0 and PSSBD1:PSSBD0
bits (ECCP1AS3:ECCP1AS0). Each pin pair (P1A/P1C
and P1B/P1D) may be set to drive high, drive low or be
tri-stated (not driving). The ECCPASE bit
(ECCP1AS<7>) is also set to hold the Enhanced PWM
outputs in their shutdown states.
In the Half-Bridge Output mode, a digitally programmable
dead-band delay is available to avoid shoot-through cur-
rent from destroying the bridge power switches. The delay
occurs at the signal transition from the non-active state to
the active state. See Figure 16-4 for illustration. Bits
PDC6:PDC0 of the ECCP1DEL register (Register 16-2)
set the delay period in terms of microcontroller instruction
cycles (TCY or 4 TOSC). These bits are not available on
PIC18F2682/2685 devices, as the standard CCP1
module does not support half-bridge operation.
The ECCPASE bit is set by hardware when a shutdown
event occurs. If automatic restarts are not enabled, the
ECCPASE bit is cleared by firmware when the cause of
the shutdown clears. If automatic restarts are enabled,
the ECCPASE bit is automatically cleared when the
cause of the auto-shutdown has cleared.
If the ECCPASE bit is set when a PWM period begins,
the PWM outputs remain in their shutdown state for that
entire PWM period. When the ECCPASE bit is cleared,
the PWM outputs will return to normal operation at the
beginning of the next PWM period.
16.4.7
ENHANCED PWM AUTO-SHUTDOWN
When the ECCP1 is programmed for any of the
Enhanced PWM modes, the active output pins may be
configured
immediately places the Enhanced PWM output pins into
a defined shutdown state when a shutdown event occurs.
Note:
Writing to the ECCPASE bit is disabled
while a shutdown condition is active.
for
auto-shutdown.
Auto-shutdown
REGISTER 16-2: ECCP1DEL: PWM DEAD-BAND DELAY REGISTER(1)
R/W-0
R/W-0
PDC6
R/W-0
PDC5
R/W-0
PDC4
R/W-0
PDC3
R/W-0
PDC2
R/W-0
PDC1
R/W-0
PDC0
PRSEN
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7
PRSEN: PWM Restart Enable bit
1= Upon auto-shutdown, the ECCPASE bit clears automatically once the shutdown event goes away;
the PWM restarts automatically
0= Upon auto-shutdown, ECCPASE must be cleared in software to restart the PWM
bit 6-0
PDC6:PDC0: PWM Delay Count bits
Delay time, in number of FOSC/4 (4 * TOSC) cycles, between the scheduled and actual time for a PWM
signal to transition to active.
Note 1: This register is available on PIC18F4682/4685 devices only.
DS39761B-page 182
Preliminary
© 2007 Microchip Technology Inc.
PIC18F2682/2685/4682/4685
REGISTER 16-3: ECCP1AS: ENHANCED CAPTURE/COMPARE/PWM AUTO-SHUTDOWN
CONFIGURATION REGISTER(1)
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
ECCPASE
ECCPAS2
ECCPAS1
ECCPAS0
PSSAC1
PSSAC0
PSSBD1
PSSBD0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
-n = Value at POR
bit 7
ECCPASE: ECCP1 Auto-Shutdown Event Status bit
1= A shutdown event has occurred; ECCP1 outputs are in shutdown state
0= ECCP1 outputs are operating
bit 6-4
ECCPAS2:ECCPAS0: ECCP1 Auto-Shutdown Source Select bits
111= RB00 or Comparator 1 or Comparator 2
110= RB0 or Comparator 2
101= RB0 or Comparator 1
100= RB0
011= Either Comparator 1 or 2
010= Comparator 2 output
001= Comparator 1 output
000= Auto-shutdown is disabled
bit 3-2
bit 1-0
PSSAC1:PSSAC0: Pins A and C Shutdown State Control bits
1x= Pins A and C tri-state (PIC18F4682/4685 devices)
01= Drive Pins A and C to ‘1’
00= Drive Pins A and C to ‘0’
PSSBD1:PSSBD0: Pins B and D Shutdown State Control bits
1x= Pins B and D tri-state
01= Drive Pins B and D to ‘1’
00= Drive Pins B and D to ‘0’
Note 1: This register is available on PIC18F4682/4685 devices only.
© 2007 Microchip Technology Inc.
Preliminary
DS39761B-page 183
PIC18F2682/2685/4682/4685
16.4.7.1
Auto-Shutdown and Auto-Restart
16.4.8
START-UP CONSIDERATIONS
The auto-shutdown feature can be configured to allow
automatic restarts of the module following a shutdown
event. This is enabled by setting the PRSEN bit of the
ECCP1DEL register (ECCP1DEL<7>).
When the ECCP1 module is used in the PWM mode, the
application hardware must use the proper external pull-up
and/or pull-down resistors on the PWM output pins. When
the microcontroller is released from Reset, all of the I/O
pins are in the high-impedance state. The external circuits
must keep the power switch devices in the OFF state until
the microcontroller drives the I/O pins with the proper
signal levels, or activates the PWM output(s).
In Shutdown mode with PRSEN = 1(Figure 16-10), the
ECCPASE bit will remain set for as long as the cause
of the shutdown continues. When the shutdown condi-
tion clears, the ECCPASE bit is cleared. If PRSEN = 0
(Figure 16-11), once a shutdown condition occurs, the
ECCPASE bit will remain set until it is cleared by
firmware. Once ECCPASE is cleared, the Enhanced
PWM will resume at the beginning of the next PWM
period.
The ECCP1M1:ECCP1M0 bits (ECCP1CON<1:0>)
allow the user to choose whether the PWM output
signals are active-high or active-low for each pair of
PWM output pins (P1A/P1C and P1B/P1D). The PWM
output polarities must be selected before the PWM pins
are configured as outputs. Changing the polarity
configuration while the PWM pins are configured as
outputs is not recommended, since it may result in
damage to the application circuits.
Note:
Writing to the ECCPASE bit is disabled
while a shutdown condition is active.
Independent of the PRSEN bit setting, if the auto-
shutdown source is one of the comparators, the
shutdown condition is a level. The ECCPASE bit
cannot be cleared as long as the cause of the shutdown
persists.
The P1A, P1B, P1C and P1D output latches may not be
in the proper states when the PWM module is initialized.
Enabling the PWM pins for output at the same time as
the ECCP1 module may cause damage to the applica-
tion circuit. The ECCP1 module must be enabled in the
proper output mode and complete a full PWM cycle
before configuring the PWM pins as outputs. The
completion of a full PWM cycle is indicated by the
TMR2IF bit being set as the second PWM period begins.
The Auto-Shutdown mode can be forced by writing a ‘1’
to the ECCPASE bit.
FIGURE 16-10:
PWM AUTO-SHUTDOWN (PRSEN = 1, AUTO-RESTART ENABLED)
PWM Period
Shutdown Event
ECCPASE bit
PWM Activity
Normal PWM
Start of
PWM Period
Shutdown
Event Occurs Event Clears
Shutdown
PWM
Resumes
FIGURE 16-11:
PWM AUTO-SHUTDOWN (PRSEN = 0, AUTO-RESTART DISABLED)
PWM Period
Shutdown Event
ECCPASE bit
PWM Activity
Normal PWM
ECCPASE
Cleared by
Firmware
Shutdown
Event Occurs
Start of
PWM Period
Shutdown
PWM
Resumes
Event Clears
DS39761B-page 184
Preliminary
© 2007 Microchip Technology Inc.
PIC18F2682/2685/4682/4685
16.4.9
SETUP FOR PWM OPERATION
16.4.10 EFFECTS OF A RESET
The following steps should be taken when configuring
the ECCP1 module for PWM operation:
Both Power-on Reset and subsequent Resets will force
all ports to Input mode and the ECCP1 registers to their
Reset states.
1. Configure the PWM pins, P1A and P1B (and
P1C and P1D, if used), as inputs by setting the
corresponding TRIS bits.
This forces the Enhanced CCP1 module to reset to a
state compatible with the standard CCP1 module.
2. Set the PWM period by loading the PR2 register.
3. Configure the ECCP1 module for the desired
PWM mode and configuration by loading the
ECCP1CON register with the appropriate values:
• Select one of the available output
configurations and direction with the
EPWM1M1:EPWM1M0 bits.
• Select the polarities of the PWM output
signals with the ECCP1M3:ECCP1M0 bits.
4. Set the PWM duty cycle by loading the
ECCPR1L register and ECCP1CON<5:4> bits.
5. For Half-Bridge Output mode, set the dead-
band delay by loading ECCP1DEL<6:0> with
the appropriate value.
6. If auto-shutdown operation is required, load the
ECCP1AS register:
• Select the auto-shutdown sources using the
ECCPAS2:ECCPAS0 bits.
• Select the shutdown states of the PWM
output pins using PSSAC1:PSSAC0 and
PSSBD1:PSSBD0 bits.
• Set the ECCPASE bit (ECCP1AS<7>).
• Configure the comparators using the CMCON
register.
• Configure the comparator inputs as analog
inputs.
7. If auto-restart operation is required, set the
PRSEN bit (ECCP1DEL<7>).
8. Configure and start TMR2:
• Clear the TMR2 interrupt flag bit by clearing
the TMR2IF bit (PIR1<1>).
• Set the TMR2 prescale value by loading the
T2CKPS bits (T2CON<1:0>).
• Enable Timer2 by setting the TMR2ON bit
(T2CON<2>).
9. Enable PWM outputs after a new PWM cycle
has started:
• Wait until TMRx overflows (TMRxIF bit is set).
• Enable the ECCP1/P1A, P1B, P1C and/or
P1D pin outputs by clearing the respective
TRIS bits.
• Clear the ECCPASE bit (ECCP1AS<7>).
© 2007 Microchip Technology Inc.
Preliminary
DS39761B-page 185
PIC18F2682/2685/4682/4685
TABLE 16-3: REGISTERS ASSOCIATED WITH ECCP1 MODULE AND TIMER1 TO TIMER3
Reset
Values
on page
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
INTCON
GIE/GIEH PEIE/GIEL TMR0IE
INT0IE
RI
RBIE
TO
TMR0IF
PD
INT0IF
POR
RBIF
BOR
49
50
52
52
52
51
52
52
52
52
52
50
50
50
50
50
50
51
51
51
51
51
51
51
51
(3)
RCON
IPR1
IPEN
SBOREN
ADIP
—
RCIP
RCIF
RCIE
—
(2)
PSPIP
PSPIF
PSPIE
TXIP
TXIF
TXIE
EEIP
EEIF
EEIE
SSPIP
SSPIF
SSPIE
BCLIP
BCLIF
BCLIE
CCP1IP
CCP1IF
CCP1IE
HLVDIP
HLVDIF
HLVDIE
TMR2IP
TMR2IF
TMR2IE
TMR1IP
TMR1IF
TMR1IE
(2)
(2)
PIR1
ADIF
PIE1
ADIE
(2)
(2)
(2)
(2)
IPR2
OSCFIP
OSCFIF
OSCFIE
CMIP
TMR3IP ECCP1IP
TMR3IF ECCP1IF
TMR3IE ECCP1IE
(2)
PIR2
CMIF
—
(2)
PIE2
CMIE
—
TRISB
TRISC
TRISD
PORTB Data Direction Register
PORTC Data Direction Register
PORTD Data Direction Register
Timer1 Register Low Byte
(1)
TMR1L
TMR1H
T1CON
TMR2
Timer1 Register High Byte
RD16
Timer2 Register
T2OUTPS3 T2OUTPS2 T2OUTPS1 T2OUTPS0 TMR2ON T2CKPS1 T2CKPS0
T1RUN
T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON
T2CON
PR2
—
Timer2 Period Register
TMR3L
TMR3H
T3CON
ECCPR1L
Timer3 Register Low Byte
Timer3 Register High Byte
(2)
(2)
RD16
T3ECCP1
T3CKPS1 T3CKPS0 T3CCP1
T3SYNC TMR3CS TMR3ON
(1)
(1)
Enhanced Capture/Compare/PWM Register 1 Low Byte
Enhanced Capture/Compare/PWM Register 1 High Byte
ECCPR1H
(1)
ECCP1CON EPWM1M1 EPWM1M0 EDC1B1
EDC1B0 ECCP1M3 ECCP1M2 ECCP1M1 ECCP1M0
(1)
ECCP1AS
ECCPASE ECCPAS2 ECCPAS1 ECCPAS0 PSSAC1
PRSEN PDC6 PDC5 PDC4 PDC3
PSSAC0 PSSBD1
PDC2 PDC1
PSSBD0
PDC0
(1)
ECCP1DEL
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used during ECCP1 operation.
Note 1: These registers are available on PIC18F4682/4685 devices only.
2: These bits are available on PIC18F4682/4685 and reserved on PIC18F2682/2685 devices.
3: The SBOREN bit is only available when CONFIG2L<1:0> = 01; otherwise, it is disabled and reads as ‘0’.
DS39761B-page 186
Preliminary
© 2007 Microchip Technology Inc.
PIC18F2682/2685/4682/4685
17.3 SPI Mode
17.0 MASTER SYNCHRONOUS
SERIAL PORT (MSSP)
MODULE
The SPI mode allows 8 bits of data to be synchronously
transmitted and received simultaneously. All four
modes of SPI are supported. To accomplish
communication, typically three pins are used:
17.1 Master SSP (MSSP) Module
Overview
• Serial Data Out (SDO) – RC5/SDO
• Serial Data In (SDI) – RC4/SDI/SDA
The Master Synchronous Serial Port (MSSP) module is
a serial interface, useful for communicating with other
peripheral or microcontroller devices. These peripheral
devices may be serial EEPROMs, shift registers,
display drivers, A/D converters, etc. The MSSP module
can operate in one of two modes:
• Serial Clock (SCK) – RC3/SCK/SCL
Additionally, a fourth pin may be used when in a Slave
mode of operation:
• Slave Select (SS) – RA5/AN4/SS/HLVDIN
Figure 17-1 shows the block diagram of the MSSP
module when operating in SPI mode.
• Serial Peripheral Interface (SPI)
• Inter-Integrated Circuit (I2C)
- Full Master mode
FIGURE 17-1:
MSSP BLOCK DIAGRAM
(SPI MODE)
- Slave mode (with general address call)
The I2C interface supports the following modes in
hardware:
Internal
Data Bus
• Master mode
• Multi-Master mode
• Slave mode
Read
Write
SSPBUF reg
SSPSR reg
17.2 Control Registers
The MSSP module has three associated registers.
These include a status register (SSPSTAT) and two
control registers (SSPCON1 and SSPCON2). The use
of these registers and their individual Configuration bits
differ significantly depending on whether the MSSP
module is operating in SPI or I2C mode.
RC4/SDI/SDA
RC5/SDO
bit 0
Shift
Clock
SS Control
Enable
Additional details are provided under the individual
sections.
RA5/AN4/SS/HLVDIN
Edge
Select
2
Clock Select
SSPM3:SSPM0
SMP:CKE
4
TMR2 Output
(
)
2
2
Edge
Select
TOSC
Prescaler
4, 16, 64
RC3/SCK/SCL
Data to TX/RX in SSPSR
TRIS bit
© 2007 Microchip Technology Inc.
Preliminary
DS39761B-page 187
PIC18F2682/2685/4682/4685
SSPSR is the shift register used for shifting data in or
out. SSPBUF is the buffer register to which data bytes
are written to or read from.
17.3.1
REGISTERS
The MSSP module has four registers for SPI mode
operation. These are:
In receive operations, SSPSR and SSPBUF together
create a double-buffered receiver. When SSPSR
receives a complete byte, it is transferred to SSPBUF
and the SSPIF interrupt is set.
• MSSP Control Register 1 (SSPCON1)
• MSSP Status Register (SSPSTAT)
• Serial Receive/Transmit Buffer Register
(SSPBUF)
During transmission, the SSPBUF is not double-
buffered. A write to SSPBUF will write to both SSPBUF
and SSPSR.
• MSSP Shift Register (SSPSR) – Not directly
accessible
SSPCON1 and SSPSTAT are the control and status
registers in SPI mode operation. The SSPCON1
register is readable and writable. The lower 6 bits of
the SSPSTAT are read-only. The upper two bits of the
SSPSTAT are read/write.
REGISTER 17-1: SSPSTAT: MSSP STATUS REGISTER (SPI MODE)
R/W-0
SMP
R/W-0
CKE
R-0
D/A
R-0
P
R-0
S
R-0
R-0
UA
R-0
BF
R/W
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7
bit 6
SMP: Sample bit
SPI Master mode:
1= Input data sampled at end of data output time
0= Input data sampled at middle of data output time
SPI Slave mode:
SMP must be cleared when SPI is used in Slave mode.
CKE: SPI Clock Select bit
1= Transmit occurs on transition from active to Idle clock state
0= Transmit occurs on transition from Idle to active clock state
Polarity of clock state is set by the CKP bit (SSPCON1<4>).
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
D/A: Data/Address bit
Used in I2C mode only.
P: Stop bit
Used in I2C mode only. This bit is cleared when the MSSP module is disabled, SSPEN is cleared.
S: Start bit
Used in I2C mode only.
R/W: Read/Write Information bit
Used in I2C mode only.
UA: Update Address bit
Used in I2C mode only.
BF: Buffer Full Status bit (Receive mode only)
1= Receive complete, SSPBUF is full
0= Receive not complete, SSPBUF is empty
DS39761B-page 188
Preliminary
© 2007 Microchip Technology Inc.
PIC18F2682/2685/4682/4685
REGISTER 17-2: SSPCON1: MSSP CONTROL REGISTER 1 (SPI MODE)
R/W-0
WCOL
R/W-0
SSPOV(1)
R/W-0
SSPEN(2)
R/W-0
CKP
R/W-0
SSPM3(3)
R/W-0
SSPM2(3)
R/W-0
SSPM1(3)
R/W-0
SSPM0(3)
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
-n = Value at POR
bit 7
bit 6
WCOL: Write Collision Detect bit (Transmit mode only)
1= The SSPBUF register is written while it is still transmitting the previous word
(must be cleared in software)
0= No collision
SSPOV: Receive Overflow Indicator bit(1)
SPI Slave mode:
1= A new byte is received while the SSPBUF register is still holding the previous data. In case of over-
flow, the data in SSPSR is lost. Overflow can only occur in Slave mode. The user must read the
SSPBUF, even if only transmitting data, to avoid setting overflow (must be cleared in software).
0= No overflow
bit 5
SSPEN: Master Synchronous Serial Port Enable bit(2)
1= Enables serial port and configures SCK, SDO, SDI and SS as serial port pins(2)
0= Disables serial port and configures these pins as I/O port pins(2)
bit 4
CKP: Clock Polarity Select bit
1= Idle state for clock is a high level
0= Idle state for clock is a low level
bit 3-0
SSPM3:SSPM0: Master Synchronous Serial Port Mode Select bits(3)
0101= SPI Slave mode, clock = SCK pin, SS pin control disabled, SS can be used as I/O pin
0100= SPI Slave mode, clock = SCK pin, SS pin control enabled
0011= SPI Master mode, clock = TMR2 output/2
0010= SPI Master mode, clock = FOSC/64
0001= SPI Master mode, clock = FOSC/16
0000= SPI Master mode, clock = FOSC/4
Note 1: In Master mode, the overflow bit is not set since each new reception (and transmission) is initiated by
writing to the SSPBUF register.
2: When enabled, these pins must be properly configured as input or output.
3: Bit combinations not specifically listed here are either reserved or implemented in I2C™ mode only.
© 2007 Microchip Technology Inc.
Preliminary
DS39761B-page 189
PIC18F2682/2685/4682/4685
reading the data that was just received. Any write to the
SSPBUF register during transmission/reception of data
will be ignored and the write collision detect bit, WCOL
(SSPCON1<7>), will be set. User software must clear
the WCOL bit so that it can be determined if the follow-
ing write(s) to the SSPBUF register completed
successfully.
17.3.2
OPERATION
When initializing the SPI, several options need to be
specified. This is done by programming the appropriate
control bits (SSPCON1<5:0> and SSPSTAT<7:6>).
These control bits allow the following to be specified:
• Master mode (SCK is the clock output)
• Slave mode (SCK is the clock input)
• Clock Polarity (Idle state of SCK)
When the application software is expecting to receive
valid data, the SSPBUF should be read before the next
byte of data to transfer is written to the SSPBUF. The
Buffer Full bit, BF (SSPSTAT<0>), indicates when
SSPBUF has been loaded with the received data
(transmission is complete). When the SSPBUF is read,
the BF bit is cleared. This data may be irrelevant if the
SPI is only a transmitter. Generally, the MSSP interrupt
is used to determine when the transmission/reception
has completed. The SSPBUF must be read and/or
written. If the interrupt method is not going to be used,
then software polling can be done to ensure that a write
collision does not occur. Example 17-1 shows the
loading of the SSPBUF (SSPSR) for data transmission.
• Data Input Sample Phase (middle or end of data
output time)
• Clock Edge (output data on rising/falling edge of
SCK)
• Clock Rate (Master mode only)
• Slave Select mode (Slave mode only)
The MSSP module consists of a transmit/receive shift
register (SSPSR) and a buffer register (SSPBUF). The
SSPSR shifts the data in and out of the device, MSb
first. The SSPBUF holds the data that was written to the
SSPSR until the received data is ready. Once the 8 bits
of data have been received, that byte is moved to the
SSPBUF register. Then, the Buffer Full detect bit, BF
(SSPSTAT<0>) and the interrupt flag bit, SSPIF, are
set. This double-buffering of the received data
(SSPBUF) allows the next byte to start reception before
The SSPSR is not directly readable or writable and can
only be accessed by addressing the SSPBUF register.
Additionally, the MSSP Status register (SSPSTAT)
indicates the various status conditions.
EXAMPLE 17-1:
LOADING THE SSPBUF (SSPSR) REGISTER
LOOP
BTFSS
BRA
SSPSTAT, BF
LOOP
;Has data been received (transmit complete)?
;No
MOVF
SSPBUF, W
;WREG reg = contents of SSPBUF
MOVWF
RXDATA
;Save in user RAM, if data is meaningful
MOVF
MOVWF
TXDATA, W
SSPBUF
;W reg = contents of TXDATA
;New data to xmit
DS39761B-page 190
Preliminary
© 2007 Microchip Technology Inc.
PIC18F2682/2685/4682/4685
17.3.3
ENABLING SPI I/O
17.3.4
TYPICAL CONNECTION
To enable the serial port, MSSP Enable bit, SSPEN
(SSPCON1<5>), must be set. To reset or reconfigure
SPI mode, clear the SSPEN bit, reinitialize the SSPCON
registers and then set the SSPEN bit. This configures
the SDI, SDO, SCK and SS pins as serial port pins. For
the pins to behave as the serial port function, some must
have their data direction bits (in the TRIS register)
appropriately programmed as follows:
Figure 17-2 shows a typical connection between two
microcontrollers. The master controller (Processor 1)
initiates the data transfer by sending the SCK signal.
Data is shifted out of both shift registers on their
programmed clock edge and latched on the opposite
edge of the clock. Both processors should be
programmed to the same Clock Polarity (CKP), then
both controllers would send and receive data at the
same time. Whether the data is meaningful (or dummy
data) depends on the application software. This leads
to three scenarios for data transmission:
• SDI is automatically controlled by the SPI module
• SDO must have TRISC<5> bit cleared
• SCK (Master mode) must have TRISC<3> bit
cleared
• Master sends data – Slave sends dummy data
• Master sends data – Slave sends data
• SCK (Slave mode) must have TRISC<3> bit set
• SS must have TRISF<7> bit set
• Master sends dummy data – Slave sends data
Any serial port function that is not desired may be
overridden by programming the corresponding data
direction (TRIS) register to the opposite value.
FIGURE 17-2:
SPI MASTER/SLAVE CONNECTION
SPI Master SSPM3:SSPM0 = 00xxb
SPI Slave SSPM3:SSPM0 = 010xb
SDI
SDO
Serial Input Buffer
(SSPBUF)
Serial Input Buffer
(SSPBUF)
SDI
SDO
Shift Register
(SSPSR)
Shift Register
(SSPSR)
LSb
MSb
MSb
LSb
Serial Clock
SCK
SCK
PROCESSOR 1
PROCESSOR 2
© 2007 Microchip Technology Inc.
Preliminary
DS39761B-page 191
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The clock polarity is selected by appropriately
programming the CKP bit (SSPCON1<4>). This then,
would give waveforms for SPI communication as
shown in Figure 17-3, Figure 17-5 and Figure 17-6,
where the MSB is transmitted first. In Master mode, the
SPI clock rate (bit rate) is user-programmable to be one
of the following:
17.3.5
MASTER MODE
The master can initiate the data transfer at any time
because it controls the SCK. The master determines
when the slave (Processor 2, Figure 17-2) is to
broadcast data by the software protocol.
In Master mode, the data is transmitted/received as
soon as the SSPBUF register is written to. If the SPI is
only going to receive, the SDO output could be
disabled (programmed as an input). The SSPSR regis-
ter will continue to shift in the signal present on the SDI
pin at the programmed clock rate. As each byte is
received, it will be loaded into the SSPBUF register as
if a normal received byte (interrupts and status bits
appropriately set). This could be useful in receiver
applications as a “Line Activity Monitor” mode.
• FOSC/4 (or TCY)
• FOSC/16 (or 4 • TCY)
• FOSC/64 (or 16 • TCY)
• Timer2 output/2
This allows a maximum data rate (at 40 MHz) of
10.00 Mbps.
Figure 17-3 shows the waveforms for Master mode.
When the CKE bit is set, the SDO data is valid before
there is a clock edge on SCK. The change of the input
sample is shown based on the state of the SMP bit. The
time when the SSPBUF is loaded with the received
data is shown.
FIGURE 17-3:
SPI MODE WAVEFORM (MASTER MODE)
Write to
SSPBUF
SCK
(CKP = 0
CKE = 0)
SCK
(CKP = 1
CKE = 0)
4 Clock
Modes
SCK
(CKP = 0
CKE = 1)
SCK
(CKP = 1
CKE = 1)
SDO
bit 6
bit 6
bit 2
bit 2
bit 5
bit 5
bit 4
bit 4
bit 1
bit 1
bit 0
bit 0
bit 7
bit 7
bit 3
bit 3
(CKE = 0)
SDO
(CKE = 1)
SDI
(SMP = 0)
bit 0
bit 7
Input
Sample
(SMP = 0)
SDI
(SMP = 1)
bit 7
bit 0
Input
Sample
(SMP = 1)
SSPIF
Next Q4 Cycle
after Q2↓
SSPSR to
SSPBUF
DS39761B-page 192
Preliminary
© 2007 Microchip Technology Inc.
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must be high. When the SS pin is low, transmission and
reception are enabled and the SDO pin is driven. When
the SS pin goes high, the SDO pin is no longer driven,
even if in the middle of a transmitted byte, and becomes
a floating output. External pull-up/pull-down resistors
may be desirable depending on the application.
17.3.6
SLAVE MODE
In Slave mode, the data is transmitted and received as
the external clock pulses appear on SCK. When the
last bit is latched, the SSPIF interrupt flag bit is set.
Before enabling the module in SPI Slave mode, the
clock line must match the proper Idle state. The clock
line can be observed by reading the SCK pin. The Idle
state is determined by the CKP bit (SSPCON1<4>).
Note 1: When the SPI is in Slave mode with SS pin
control enabled (SSPCON<3:0> = 0100),
the SPI module will reset if the SS pin is set
to VDD.
While in Slave mode, the external clock is supplied by
the external clock source on the SCK pin. This external
clock must meet the minimum high and low times as
specified in the electrical specifications.
2: If the SPI is used in Slave mode with CKE
set, then the SS pin control must be
enabled.
While in Sleep mode, the slave can transmit/receive
data. When a byte is received, the device will wake-up
from Sleep.
When the SPI module resets, the bit counter is forced
to ‘0’. This can be done by either forcing the SS pin to
a high level or clearing the SSPEN bit.
17.3.7
SLAVE SELECT
SYNCHRONIZATION
To emulate two-wire communication, the SDO pin can
be connected to the SDI pin. When the SPI needs to
operate as a receiver, the SDO pin can be configured
as an input. This disables transmissions from the SDO.
The SDI can always be left as an input (SDI function)
since it cannot create a bus conflict.
The SS pin allows a Synchronous Slave mode. The SPI
must be in Slave mode with SS pin control enabled
(SSPCON1<3:0> = 04h). The pin must not be driven low
for the SS pin to function as an input. The data latch
FIGURE 17-4:
SLAVE SYNCHRONIZATION WAVEFORM
SS
SCK
(CKP = 0
CKE = 0)
SCK
(CKP = 1
CKE = 0)
Write to
SSPBUF
bit 6
bit 7
bit 7
bit 0
SDO
bit 7
SDI
(SMP = 0)
bit 0
bit 7
Input
Sample
(SMP = 0)
SSPIF
Interrupt
Flag
Next Q4 Cycle
after Q2↓
SSPSR to
SSPBUF
© 2007 Microchip Technology Inc.
Preliminary
DS39761B-page 193
PIC18F2682/2685/4682/4685
FIGURE 17-5:
SPI MODE WAVEFORM (SLAVE MODE WITH CKE = 0)
SS
Optional
SCK
(CKP = 0
CKE = 0)
SCK
(CKP = 1
CKE = 0)
Write to
SSPBUF
bit 6
bit 2
bit 5
bit 4
bit 3
bit 1
bit 0
SDO
bit 7
SDI
(SMP = 0)
bit 0
bit 7
Input
Sample
(SMP = 0)
SSPIF
Interrupt
Flag
Next Q4 Cycle
after Q2↓
SSPSR to
SSPBUF
FIGURE 17-6:
SPI MODE WAVEFORM (SLAVE MODE WITH CKE = 1)
SS
Not Optional
SCK
(CKP = 0
CKE = 1)
SCK
(CKP = 1
CKE = 1)
Write to
SSPBUF
bit 6
bit 2
bit 5
bit 4
bit 1
bit 0
SDO
bit 7
bit 3
SDI
(SMP = 0)
bit 0
bit 7
Input
Sample
(SMP = 0)
SSPIF
Interrupt
Flag
Next Q4 Cycle
after Q2↓
SSPSR to
SSPBUF
DS39761B-page 194
Preliminary
© 2007 Microchip Technology Inc.
PIC18F2682/2685/4682/4685
17.3.8
OPERATION IN POWER-MANAGED
MODES
17.3.9
EFFECTS OF A RESET
A Reset disables the MSSP module and terminates the
current transfer.
In SPI Master mode, module clocks may be operating
at a different speed than when in full power mode. In
the case of Sleep mode, all clocks are halted.
17.3.10 BUS MODE COMPATIBILITY
Table 17-1 shows the compatibility between the
standard SPI modes and the states of the CKP and
CKE control bits.
In most power-managed modes, a clock is provided to
the peripherals. That clock should be from the primary
clock source, the secondary clock (Timer1 oscillator at
32.768 kHz) or the INTOSC source. See Section 2.7
“Clock Sources and Oscillator Switching” for
additional information.
TABLE 17-1: SPI BUS MODES
Control Bits State
Standard SPI Mode
In most cases, the speed that the master clocks SPI
data is not important; however, this should be
evaluated for each system.
Terminology
CKP
CKE
0, 0
0, 1
1, 0
1, 1
0
0
1
1
1
0
1
0
If MSSP interrupts are enabled, they can wake the
controller from Sleep mode, or one of the Idle modes,
when the master completes sending data. If an exit
from Sleep or Idle mode is not desired, MSSP
interrupts should be disabled.
There is also an SMP bit which controls when the data
is sampled.
If the Sleep mode is selected, all module clocks are
halted and the transmission/reception will remain in
that state until the devices wakes. After the device
returns to Run mode, the module will resume
transmitting and receiving data.
In SPI Slave mode, the SPI Transmit/Receive Shift
register operates asynchronously to the device. This
allows the device to be placed in any power-managed
mode and data to be shifted into the SPI Transmit/
Receive Shift register. When all 8 bits have been
received, the MSSP interrupt flag bit will be set and if
enabled, will wake the device.
TABLE 17-2: REGISTERS ASSOCIATED WITH SPI OPERATION
Reset
Values
on page
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
INTCON
PIR1
GIE/GIEH PEIE/GIEL TMR0IE
INT0IE
TXIF
RBIE
SSPIF
SSPIE
SSPIP
TMR0IF
CCP1IF
CCP1IE
CCP1IP
INT0IF
RBIF
49
52
52
52
52
52
50
50
50
PSPIF(1)
PSPIE(1)
PSPIP(1)
ADIF
ADIE
ADIP
RCIF
RCIE
RCIP
TMR2IF
TMR1IF
PIE1
TXIE
TXIP
TMR2IE TMR1IE
TMR2IP TMR1IP
IPR1
TRISA
PORTA Data Direction Register
PORTC Data Direction Register
TRISC
SSPBUF
SSPCON1
SSPSTAT
MSSP Receive Buffer/Transmit Register
WCOL
SMP
SSPOV
CKE
SSPEN
D/A
CKP
P
SSPM3
S
SSPM2
R/W
SSPM1
UA
SSPM0
BF
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the MSSP in SPI mode.
Note 1: These bits are unimplemented in PIC18F2682/2685 devices; always maintain these bits clear.
© 2007 Microchip Technology Inc.
Preliminary
DS39761B-page 195
PIC18F2682/2685/4682/4685
2
17.4.1
REGISTERS
17.4 I C Mode
The MSSP module has six registers for I2C operation.
These are:
The MSSP module in I2C mode fully implements all
master and slave functions (including general call
support) and provides interrupts on Start and Stop bits
in hardware to determine a free bus (multi-master
function). The MSSP module implements the standard
mode specifications, as well as 7-bit and 10-bit
addressing.
• MSSP Control Register 1 (SSPCON1)
• MSSP Control Register 2 (SSPCON2)
• MSSP Status Register (SSPSTAT)
• Serial Receive/Transmit Buffer Register
(SSPBUF)
Two pins are used for data transfer:
• MSSP Shift Register (SSPSR) – Not directly
accessible
• Serial clock (SCL) – RC3/SCK/SCL
• Serial data (SDA) – RC4/SDI/SDA
• MSSP Address Register (SSPADD)
The user must configure these pins as inputs or outputs
through the TRISC<4:3> bits.
SSPCON1, SSPCON2 and SSPSTAT are the control
and status registers in I2C mode operation. The
SSPCON1 and SSPCON2 registers are readable and
writable. The lower 6 bits of the SSPSTAT are read-only.
The upper two bits of the SSPSTAT are read/write.
FIGURE 17-7:
MSSP BLOCK DIAGRAM
(I2C™ MODE)
SSPSR is the shift register used for shifting data in or
out. SSPBUF is the buffer register to which data bytes
are written to or read from.
Internal
Data Bus
Write
Read
SSPADD register holds the slave device address
when the MSSP is configured in I2C Slave mode.
When the MSSP is configured in Master mode, the
lower seven bits of SSPADD act as the Baud Rate
Generator reload value.
SSPBUF reg
Shift
Clock
RC3/SCK/SCL
RC4/SDI/SDA
In receive operations, SSPSR and SSPBUF together
create a double-buffered receiver. When SSPSR
receives a complete byte, it is transferred to SSPBUF
and the SSPIF interrupt is set.
SSPSR reg
MSb LSb
Addr Match
Match Detect
SSPADD reg
During transmission, the SSPBUF is not double-
buffered. A write to SSPBUF will write to both SSPBUF
and SSPSR.
Set, Reset
S, P bits
(SSPSTAT reg)
Start and
Stop bit Detect
DS39761B-page 196
Preliminary
© 2007 Microchip Technology Inc.
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REGISTER 17-3: SSPSTAT: MSSP STATUS REGISTER (I2C™ MODE)
R/W-0
SMP
R/W-0
CKE
R-0
D/A
R-0
P(1)
R-0
S(1)
R-0
R/W(2,3)
R-0
UA
R-0
BF
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7
bit 6
bit 5
SMP: Slew Rate Control bit
In Master or Slave mode:
1 = Slew rate control disabled for Standard Speed mode (100 kHz and 1 MHz)
0 = Slew rate control enabled for High-Speed mode (400 kHz)
CKE: SMBus Select bit
In Master or Slave mode:
1= Enable SMBus specific inputs
0= Disable SMBus specific inputs
D/A: Data/Address bit
In Master mode:
Reserved.
In Slave mode:
1= Indicates that the last byte received or transmitted was data
0= Indicates that the last byte received or transmitted was address
bit 4
bit 3
bit 2
P: Stop bit(1)
1= Indicates that a Stop bit has been detected last
0= Stop bit was not detected last
S: Start bit(1)
1= Indicates that a Start bit has been detected last
0= Start bit was not detected last
R/W: Read/Write Information bit (I2C mode only)(2,3)
In Slave mode:
1= Read
0= Write
In Master mode:
1= Transmit is in progress
0= Transmit is not in progress
bit 1
bit 0
UA: Update Address bit (10-Bit Slave mode only)
1= Indicates that the user needs to update the address in the SSPADD register
0= Address does not need to be updated
BF: Buffer Full Status bit
In Receive mode:
1= Receive complete, SSPBUF is full
0= Receive is not complete, SSPBUF is empty
In Transmit mode:
1= Data transmit in progress (does not include the ACK and Stop bits), SSPBUF is full
0= Data transmit complete (does not include the ACK and Stop bits), SSPBUF is empty
Note 1: This bit is cleared on Reset and when SSPEN is cleared.
2: This bit holds the R/W bit information following the last address match. This bit is only valid from the
address match to the next Start bit, Stop bit or not ACK bit.
3: ORing this bit with SEN, RSEN, PEN, RCEN or ACKEN will indicate if the MSSP is in Idle mode.
© 2007 Microchip Technology Inc.
Preliminary
DS39761B-page 197
PIC18F2682/2685/4682/4685
REGISTER 17-4: SSPCON1: MSSP CONTROL REGISTER 1 (I2C™ MODE)
R/W-0
WCOL
R/W-0
R/W-0
SSPEN(1)
R/W-0
CKP
R/W-0
SSPM3(2)
R/W-0
SSPM2(2)
R/W-0
SSPM1(2)
R/W-0
SSPM0(2)
SSPOV
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7
WCOL: Write Collision Detect bit
In Master Transmit mode:
1= A write to the SSPBUF register was attempted while the I2C conditions were not valid for a
transmission to be started (must be cleared in software)
0= No collision
In Slave Transmit mode:
1= The SSPBUF register is written while it is still transmitting the previous word (must be cleared in
software)
0= No collision
In Receive mode (Master or Slave modes):
This is a “don’t care” bit.
bit 6
SSPOV: Receive Overflow Indicator bit
In Receive mode:
1= A byte is received while the SSPBUF register is still holding the previous byte (must be cleared in
software)
0= No overflow
In Transmit mode:
This is a “don’t care” bit in Transmit mode.
bit 5
bit 4
SSPEN: Master Synchronous Serial Port Enable bit(1)
1= Enables the serial port and configures the SDA and SCL pins as the serial port pins
0= Disables serial port and configures these pins as I/O port pins
CKP: SCK Release Control bit
In Slave mode:
1= Release clock
0= Holds clock low (clock stretch), used to ensure data setup time
In Master mode:
Unused in this mode.
bit 3-0
SSPM3:SSPM0: Master Synchronous Serial Port Mode Select bits(2)
1111= I2C Slave mode, 10-bit address with Start and Stop bit interrupts enabled
1110= I2C Slave mode, 7-bit address with Start and Stop bit interrupts enabled
1011= I2C Firmware Controlled Master mode (slave Idle)
1000= I2C Master mode, clock = FOSC/(4 * (SSPADD + 1))
0111= I2C Slave mode, 10-bit address
0110= I2C Slave mode, 7-bit address
Note 1: When enabled, the SDA and SCL pins must be properly configured as input or output.
2: Bit combinations not specifically listed here are either reserved or implemented in SPI mode only.
DS39761B-page 198
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© 2007 Microchip Technology Inc.
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REGISTER 17-5: SSPCON2: MSSP CONTROL REGISTER 2 (I2C™ MODE)
R/W-0
GCEN
R/W-0
R/W-0
ACKDT(1)
R/W-0
ACKEN(2)
R/W-0
RCEN(2)
R/W-0
PEN(2)
R/W-0
RSEN(2)
R/W-0
SEN(2)
ACKSTAT
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
-n = Value at POR
bit 7
bit 6
bit 5
bit 4
GCEN: General Call Enable bit (Slave mode only)
1= Enable interrupt when a general call address (0000h) is received in the SSPSR
0= General call address disabled
ACKSTAT: Acknowledge Status bit (Master Transmit mode only)
1= Acknowledge was not received from slave
0= Acknowledge was received from slave
ACKDT: Acknowledge Data bit (Master Receive mode only)(1)
1= Not Acknowledge
0= Acknowledge
ACKEN: Acknowledge Sequence Enable bit (Master Receive mode only)(2)
1= Initiate Acknowledge sequence on SDA and SCL pins and transmit ACKDT data bit. Automatically
cleared by hardware.
0= Acknowledge sequence Idle
bit 3
bit 2
bit 1
bit 0
RCEN: Receive Enable bit (Master mode only)(2)
1= Enables Receive mode for I2C
0= Receive Idle
PEN: Stop Condition Enable bit (Master mode only)(2)
1= Initiate Stop condition on SDA and SCL pins. Automatically cleared by hardware.
0= Stop condition Idle
RSEN: Repeated Start Condition Enable bit (Master mode only(2)
1= Initiate Repeated Start condition on SDA and SCL pins. Automatically cleared by hardware.
0= Repeated Start condition Idle
SEN: Start Condition Enable/Stretch Enable bit(2)
In Master mode:
1= Initiate Start condition on SDA and SCL pins. Automatically cleared by hardware.
0= Start condition Idle
In Slave mode:
1= Clock stretching is enabled for both slave transmit and slave receive (stretch enabled)
0= Clock stretching is disabled
Note 1: Value that will be transmitted when the user initiates an Acknowledge sequence at the end of a receive.
2: For bits ACKEN, RCEN, PEN, RSEN, SEN: If the I2C module is not in the Idle mode, these bits may not be
set (no spooling) and the SSPBUF may not be written (or writes to the SSPBUF are disabled).
© 2007 Microchip Technology Inc.
Preliminary
DS39761B-page 199
PIC18F2682/2685/4682/4685
17.4.2
OPERATION
17.4.3.1
Addressing
The MSSP module functions are enabled by setting
MSSP Enable bit, SSPEN (SSPCON<5>).
The SSPCON1 register allows control of the I2C
operation. Four mode selection bits (SSPCON<3:0>)
allow one of the following I2C modes to be selected:
• I2C Master mode, clock = (FOSC/4) x (SSPADD + 1)
• I2C Slave mode (7-bit address)
• I2C Slave mode (10-bit address)
Once the MSSP module has been enabled, it waits for
a Start condition to occur. Following the Start condition,
the 8-bits are shifted into the SSPSR register. All
incoming bits are sampled with the rising edge of the
clock (SCL) line. The value of register SSPSR<7:1> is
compared to the value of the SSPADD register. The
address is compared on the falling edge of the eighth
clock (SCL) pulse. If the addresses match and the BF
and SSPOV bits are clear, the following events occur:
• I2C Slave mode (7-bit address) with Start and
Stop bit interrupts enabled
• I2C Slave mode (10-bit address) with Start and
Stop bit interrupts enabled
• I2C Firmware Controlled Master mode, slave is
Idle
Selection of any I2C mode with the SSPEN bit set,
forces the SCL and SDA pins to be open-drain,
provided these pins are programmed to inputs by
setting the appropriate TRISC bits. To ensure proper
operation of the module, pull-up resistors must be
provided externally to the SCL and SDA pins.
1. The SSPSR register value is loaded into the
SSPBUF register.
2. The Buffer Full bit, BF, is set.
3. An ACK pulse is generated.
4. MSSP Interrupt Flag bit, SSPIF (PIR1<3>), is
set (interrupt is generated, if enabled) on the
falling edge of the ninth SCL pulse.
In 10-Bit Address mode, two address bytes need to be
received by the slave. The five Most Significant bits
(MSbs) of the first address byte specify if this is a 10-bit
address. Bit R/W (SSPSTAT<2>) must specify a write so
the slave device will receive the second address byte.
For a 10-bit address, the first byte would equal ‘11110
A9 A8 0’, where ‘A9’ and ‘A8’ are the two MSbs of the
address. The sequence of events for 10-bit address is as
follows, with steps 7 through 9 for the slave-transmitter:
17.4.3
SLAVE MODE
In Slave mode, the SCL and SDA pins must be
configured as inputs (TRISC<4:3> set). The MSSP
module will override the input state with the output data
when required (slave-transmitter).
The I2C Slave mode hardware will always generate an
interrupt on an address match. Through the mode
select bits, the user can also choose to interrupt on
Start and Stop bits
1. Receive first (high) byte of address (bits SSPIF,
BF and UA (SSPSTAT<1>) are set).
2. Update the SSPADD register with second (low)
byte of address (clears bit UA and releases the
SCL line).
3. Read the SSPBUF register (clears bit BF) and
clear flag bit, SSPIF.
When an address is matched, or the data transfer after
an address match is received, the hardware automati-
cally will generate the Acknowledge (ACK) pulse and
load the SSPBUF register with the received value
currently in the SSPSR register.
4. Receive second (low) byte of address (bits
SSPIF, BF and UA are set).
5. Update the SSPADD register with the first (high)
byte of address. If match releases SCL line, this
will clear bit UA.
Any combination of the following conditions will cause
the MSSP module not to give this ACK pulse:
6. Read the SSPBUF register (clears bit BF) and
clear flag bit, SSPIF.
• The Buffer Full bit, BF (SSPSTAT<0>), was set
before the transfer was received.
7. Receive Repeated Start condition.
• The overflow bit, SSPOV (SSPCON<6>), was set
before the transfer was received.
8. Receive first (high) byte of address (bits SSPIF
and BF are set).
9. Read the SSPBUF register (clears bit BF) and
clear flag bit, SSPIF.
In this case, the SSPSR register value is not loaded
into the SSPBUF, but bit SSPIF (PIR1<3>) is set. The
BF bit is cleared by reading the SSPBUF register, while
bit SSPOV is cleared through software.
The SCL clock input must have a minimum high and
low for proper operation. The high and low times of the
I2C specification, as well as the requirement of the
MSSP module, are shown in timing parameter 100 and
parameter 101.
DS39761B-page 200
Preliminary
© 2007 Microchip Technology Inc.
PIC18F2682/2685/4682/4685
17.4.3.2
Reception
17.4.3.3
Transmission
When the R/W bit of the address byte is clear and an
address match occurs, the R/W bit of the SSPSTAT
register is cleared. The received address is loaded into
the SSPBUF register and the SDA line is held low
(ACK).
When the R/W bit of the incoming address byte is set
and an address match occurs, the R/W bit of the
SSPSTAT register is set. The received address is
loaded into the SSPBUF register. The ACK pulse will
be sent on the ninth bit and pin RC3/SCK/SCL is held
low regardless of SEN (see Section 17.4.4 “Clock
Stretching” for more detail). By stretching the clock,
the master will be unable to assert another clock pulse
until the slave is done preparing the transmit data. The
transmit data must be loaded into the SSPBUF register
which also loads the SSPSR register. Then pin RC3/
SCK/SCL should be enabled by setting bit, CKP
(SSPCON1<4>). The eight data bits are shifted out on
the falling edge of the SCL input. This ensures that the
SDA signal is valid during the SCL high time
(Figure 17-9).
When the address byte overflow condition exists, then
the no Acknowledge (ACK) pulse is given. An overflow
condition is defined as either bit BF (SSPSTAT<0>) is
set, or bit SSPOV (SSPCON1<6>) is set.
An MSSP interrupt is generated for each data transfer
byte. Flag bit, SSPIF (PIR1<3>), must be cleared in
software. The SSPSTAT register is used to determine
the status of the byte.
If SEN is enabled (SSPCON2<0> = 1), RC3/SCK/SCL
will be held low (clock stretch) following each data
transfer. The clock must be released by setting bit
CKP (SSPCON<4>). See Section 17.4.4 “Clock
Stretching” for more detail.
The ACK pulse from the master-receiver is latched on
the rising edge of the ninth SCL input pulse. If the SDA
line is high (not ACK), then the data transfer is
complete. In this case, when the ACK is latched by the
slave, the slave logic is reset (resets SSPSTAT regis-
ter) and the slave monitors for another occurrence of
the Start bit. If the SDA line was low (ACK), the next
transmit data must be loaded into the SSPBUF register.
Again, pin RC3/SCK/SCL must be enabled by setting
bit CKP.
An MSSP interrupt is generated for each data transfer
byte. The SSPIF bit must be cleared in software and
the SSPSTAT register is used to determine the status
of the byte. The SSPIF bit is set on the falling edge of
the ninth clock pulse.
© 2007 Microchip Technology Inc.
Preliminary
DS39761B-page 201
PIC18F2682/2685/4682/4685
2
FIGURE 17-8:
I C™ SLAVE MODE TIMING WITH SEN = 0(RECEPTION, 7-BIT ADDRESS)
DS39761B-page 202
Preliminary
© 2007 Microchip Technology Inc.
PIC18F2682/2685/4682/4685
2
FIGURE 17-9:
I C™ SLAVE MODE TIMING (TRANSMISSION, 7-BIT ADDRESS)
© 2007 Microchip Technology Inc.
Preliminary
DS39761B-page 203
PIC18F2682/2685/4682/4685
FIGURE 17-10:
I2C™ SLAVE MODE TIMING WITH SEN = 0(RECEPTION, 10-BIT ADDRESS)
DS39761B-page 204
Preliminary
© 2007 Microchip Technology Inc.
PIC18F2682/2685/4682/4685
2
FIGURE 17-11:
I C™ SLAVE MODE TIMING (TRANSMISSION, 10-BIT ADDRESS)
© 2007 Microchip Technology Inc.
Preliminary
DS39761B-page 205
PIC18F2682/2685/4682/4685
17.4.4
CLOCK STRETCHING
17.4.4.3
Clock Stretching for 7-Bit Slave
Transmit Mode
Both 7 and 10-Bit Slave modes implement automatic
clock stretching during a transmit sequence.
7-Bit Slave Transmit mode implements clock stretch-
ing by clearing the CKP bit after the falling edge of the
ninth clock if the BF bit is clear. This occurs regardless
of the state of the SEN bit.
The SEN bit (SSPCON2<0>) allows clock stretching to
be enabled during receives. Setting SEN will cause
the SCL pin to be held low at the end of each data
receive sequence.
The user’s ISR must set the CKP bit before transmis-
sion is allowed to continue. By holding the SCL line
low, the user has time to service the ISR and load the
contents of the SSPBUF before the master device can
initiate another transmit sequence (see Figure 17-9).
17.4.4.1
Clock Stretching for 7-Bit Slave
Receive Mode (SEN = 1)
In 7-Bit Slave Receive mode, on the falling edge of the
ninth clock at the end of the ACK sequence if the BF
bit is set, the CKP bit in the SSPCON1 register is
automatically cleared, forcing the SCL output to be
held low. The CKP being cleared to ‘0’ will assert the
SCL line low. The CKP bit must be set in the user’s
ISR before reception is allowed to continue. By holding
the SCL line low, the user has time to service the ISR
and read the contents of the SSPBUF before the
master device can initiate another receive sequence.
This will prevent buffer overruns from occurring (see
Figure 17-13).
Note 1: If the user loads the contents of SSPBUF,
setting the BF bit before the falling edge of
the ninth clock, the CKP bit will not be
cleared and clock stretching will not occur.
2: The CKP bit can be set in software
regardless of the state of the BF bit.
17.4.4.4
Clock Stretching for 10-Bit Slave
Transmit Mode
In 10-Bit Slave Transmit mode, clock stretching is
controlled during the first two address sequences by
the state of the UA bit, just as it is in 10-Bit Slave
Receive mode. The first two addresses are followed
by a third address sequence which contains the high-
order bits of the 10-bit address and the R/W bit set to
‘1’. After the third address sequence is performed, the
UA bit is not set, the module is now configured in
Transmit mode and clock stretching is controlled by
the BF flag as in 7-Bit Slave Transmit mode (see
Figure 17-11).
Note 1: If the user reads the contents of the
SSPBUF before the falling edge of the
ninth clock, thus clearing the BF bit, the
CKP bit will not be cleared and clock
stretching will not occur.
2: The CKP bit can be set in software
regardless of the state of the BF bit. The
user should be careful to clear the BF bit
in the ISR before the next receive
sequence in order to prevent an overflow
condition.
17.4.4.2
Clock Stretching for 10-Bit Slave
Receive Mode (SEN = 1)
In 10-Bit Slave Receive mode during the address
sequence, clock stretching automatically takes place
but CKP is not cleared. During this time, if the UA bit is
set after the ninth clock, clock stretching is initiated.
The UA bit is set after receiving the upper byte of the
10-bit address and following the receive of the second
byte of the 10-bit address with the R/W bit cleared to
‘0’. The release of the clock line occurs upon updating
SSPADD. Clock stretching will occur on each data
receive sequence as described in 7-bit mode.
Note:
If the user polls the UA bit and clears it by
updating the SSPADD register before the
falling edge of the ninth clock occurs and if
the user hasn’t cleared the BF bit by read-
ing the SSPBUF register before that time,
then the CKP bit will still NOT be asserted
low. Clock stretching on the basis of the
state of the BF bit only occurs during a
data sequence, not an address sequence.
DS39761B-page 206
Preliminary
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already asserted the SCL line. The SCL output will
remain low until the CKP bit is set and all other
devices on the I2C bus have deasserted SCL. This
ensures that a write to the CKP bit will not violate the
minimum high time requirement for SCL (see
Figure 17-12).
17.4.4.5
Clock Synchronization and
the CKP bit
When the CKP bit is cleared, the SCL output is forced
to ‘0’. However, setting the CKP bit will not assert the
SCL output low until the SCL output is already
sampled low. Therefore, the CKP bit will not assert the
SCL line until an external I2C master device has
FIGURE 17-12:
CLOCK SYNCHRONIZATION TIMING
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
SDA
DX
DX – 1
SCL
CKP
Master device
asserts clock
Master device
deasserts clock
WR
SSPCON
© 2007 Microchip Technology Inc.
Preliminary
DS39761B-page 207
PIC18F2682/2685/4682/4685
2
FIGURE 17-13:
I C™ SLAVE MODE TIMING WITH SEN = 1(RECEPTION, 7-BIT ADDRESS)
DS39761B-page 208
Preliminary
© 2007 Microchip Technology Inc.
PIC18F2682/2685/4682/4685
FIGURE 17-14:
I2C™ SLAVE MODE TIMING SEN = 1(RECEPTION, 10-BIT ADDRESS)
© 2007 Microchip Technology Inc.
Preliminary
DS39761B-page 209
PIC18F2682/2685/4682/4685
If the general call address matches, the SSPSR is
transferred to the SSPBUF, the BF flag bit is set (eighth
bit) and on the falling edge of the ninth bit (ACK bit), the
SSPIF interrupt flag bit is set.
17.4.5
GENERAL CALL ADDRESS
SUPPORT
The addressing procedure for the I2C bus is such that
the first byte after the Start condition usually
determines which device will be the slave addressed by
the master. The exception is the general call address
which can address all devices. When this address is
used, all devices should, in theory, respond with an
Acknowledge.
When the interrupt is serviced, the source for the
interrupt can be checked by reading the contents of the
SSPBUF. The value can be used to determine if the
address was device specific or a general call address.
In 10-Bit Address mode, the SSPADD is required to be
updated for the second half of the address to match
and the UA bit is set (SSPSTAT<1>). If the general call
address is sampled when the GCEN bit is set, while the
slave is configured in 10-Bit Address mode, then the
second half of the address is not necessary, the UA bit
will not be set and the slave will begin receiving data
after the Acknowledge (Figure 17-15).
The general call address is one of eight addresses
reserved for specific purposes by the I2C protocol. It
consists of all ‘0’s with R/W = 0.
The general call address is recognized when the
General Call Enable bit, GCEN, is enabled
(SSPCON2<7> set). Following a Start bit detect, 8 bits
are shifted into the SSPSR and the address is
compared against the SSPADD. It is also compared to
the general call address and fixed in hardware.
FIGURE 17-15:
SLAVE MODE GENERAL CALL ADDRESS SEQUENCE
(7 OR 10-BIT ADDRESS MODE)
Address is compared to General Call Address
after ACK, set interrupt
Receiving Data
ACK
9
R/W = 0
General Call Address
SDA
ACK D7 D6 D5 D4 D3 D2 D1
D0
8
SCL
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
S
SSPIF
BF (SSPSTAT<0>)
Cleared in software
SSPBUF is read
SSPOV (SSPCON1<6>)
GCEN (SSPCON2<7>)
‘0’
‘1’
DS39761B-page 210
Preliminary
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17.4.6
MASTER MODE
Note:
The MSSP module, when configured in
I2C Master mode, does not allow queueing
of events. For instance, the user is not
allowed to initiate a Start condition and
immediately write the SSPBUF register to
initiate transmission before the Start
condition is complete. In this case, the
SSPBUF will not be written to and the
WCOL bit will be set, indicating that a write
to the SSPBUF did not occur.
Master mode is enabled by setting and clearing the
appropriate SSPM bits in SSPCON1 and by setting the
SSPEN bit. In Master mode, the SCL and SDA lines
are manipulated by the MSSP hardware.
Master mode of operation is supported by interrupt
generation on the detection of the Start and Stop
conditions. The Stop (P) and Start (S) bits are cleared
from a Reset or when the MSSP module is disabled.
Control of the I2C bus may be taken when the P bit is
set or the bus is Idle, with both the S and P bits clear.
The following events will cause the MSSP Interrupt
Flag bit, SSPIF, to be set (MSSP interrupt, if enabled):
In Firmware Controlled Master mode, user code
conducts all I2C bus operations based on Start and
Stop bit conditions.
• Start Condition
• Stop Condition
Once Master mode is enabled, the user has six
options.
• Data Transfer Byte Transmitted/Received
• Acknowledge Transmit
• Repeated Start
1. Assert a Start condition on SDA and SCL.
2. Assert a Repeated Start condition on SDA and
SCL.
3. Write to the SSPBUF register initiating
transmission of data/address.
4. Configure the I2C port to receive data.
5. Generate an Acknowledge condition at the end
of a received byte of data.
6. Generate a Stop condition on SDA and SCL.
2
FIGURE 17-16:
MSSP BLOCK DIAGRAM (I C™ MASTER MODE)
Internal
Data Bus
SSPM3:SSPM0
SSPADD<6:0>
Read
Write
SSPBUF
SSPSR
Baud
Rate
Generator
SDA
Shift
Clock
SDA In
MSb
LSb
Start bit, Stop bit,
Acknowledge
Generate
SCL
Start bit Detect
Stop bit Detect
Write Collision Detect
Clock Arbitration
State Counter for
end of XMIT/RCV
SCL In
Bus Collision
Set/Reset, S, P, WCOL (SSPSTAT)
Set SSPIF, BCLIF
Reset ACKSTAT, PEN (SSPCON2)
© 2007 Microchip Technology Inc.
Preliminary
DS39761B-page 211
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I2C Master Mode Operation
A typical transmit sequence would go as follows:
17.4.6.1
1. The user generates a Start condition by setting
the Start Enable bit, SEN (SSPCON2<0>).
The master device generates all of the serial clock
pulses and the Start and Stop conditions. A transfer is
ended with a Stop condition or with a Repeated Start
condition. Since the Repeated Start condition is also
the beginning of the next serial transfer, the I2C bus will
not be released.
2. SSPIF is set. The MSSP module will wait the
required start time before any other operation
takes place.
3. The user loads the SSPBUF with the slave
address to transmit.
In Master Transmitter mode, serial data is output
through SDA, while SCL outputs the serial clock. The
first byte transmitted contains the slave address of the
receiving device (7 bits) and the Read/Write (R/W) bit.
In this case, the R/W bit will be logic ‘0’. Serial data is
transmitted 8 bits at a time. After each byte is transmit-
ted, an Acknowledge bit is received. Start and Stop
conditions are output to indicate the beginning and the
end of a serial transfer.
4. Address is shifted out on the SDA pin until all 8
bits are transmitted.
5. The MSSP Module shifts in the ACK bit from the
slave device and writes its value into the
SSPCON2 register (SSPCON2<6>).
6. The MSSP module generates an interrupt at the
end of the ninth clock cycle by setting the SSPIF
bit.
In Master Receive mode, the first byte transmitted
contains the slave address of the transmitting device
(7 bits) and the R/W bit. In this case, the R/W bit will be
logic ‘1’ Thus, the first byte transmitted is a 7-bit slave
address followed by a ‘1’ to indicate the receive bit.
Serial data is received via SDA, while SCL outputs the
serial clock. Serial data is received 8 bits at a time. After
each byte is received, an Acknowledge bit is transmit-
ted. Start and Stop conditions indicate the beginning
and end of transmission.
7. The user loads the SSPBUF with eight bits of
data.
8. Data is shifted out on the SDA pin until all 8 bits
are transmitted.
9. The MSSP module shifts in the ACK bit from the
slave device and writes its value into the
SSPCON2 register (SSPCON2<6>).
10. The MSSP module generates an interrupt at the
end of the ninth clock cycle by setting the SSPIF
bit.
The Baud Rate Generator used for the SPI mode
operation is used to set the SCL clock frequency for
either 100 kHz, 400 kHz or 1 MHz I2C operation. See
Section 17.4.7 “Baud Rate” for more detail.
11. The user generates a Stop condition by setting
the Stop Enable bit, PEN (SSPCON2<2>).
12. Interrupt is generated once the Stop condition is
complete.
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Once the given operation is complete (i.e., transmis-
sion of the last data bit is followed by ACK), the internal
clock will automatically stop counting and the SCL pin
will remain in its last state.
17.4.7
BAUD RATE
In I2C Master mode, the Baud Rate Generator (BRG)
reload value is placed in the lower 7 bits of the
SSPADD register (Figure 17-17). When a write occurs
to SSPBUF, the Baud Rate Generator will automatically
begin counting. The BRG counts down to 0 and stops
until another reload has taken place. The BRG count is
decremented twice per instruction cycle (TCY) on the
Q2 and Q4 clocks. In I2C Master mode, the BRG is
reloaded automatically.
Table 17-3 demonstrates clock rates based on
instruction cycles and the BRG value loaded into
SSPADD.
FIGURE 17-17:
BAUD RATE GENERATOR BLOCK DIAGRAM
SSPM3:SSPM0
SSPADD<6:0>
SSPM3:SSPM0
SCL
Reload
Reload
Control
CLKO
FOSC/4
BRG Down Counter
TABLE 17-3: I2C™ CLOCK RATE w/BRG
FSCL
FCY
FCY*2
BRG Value
(2 Rollovers of BRG)
10 MHz
10 MHz
10 MHz
4 MHz
4 MHz
4 MHz
1 MHz
1 MHz
1 MHz
20 MHz
20 MHz
20 MHz
8 MHz
8 MHz
8 MHz
2 MHz
2 MHz
2 MHz
19h
20h
64h
0Ah
0Dh
28h
03h
0Ah
00h
400 kHz(1)
312.5 kHz
100 kHz
400 kHz(1)
308 kHz
100 kHz
333 kHz(1)
100 kHz
1 MHz(1)
Note 1: The I2C™ interface does not conform to the 400 kHz I2C specification (which applies to rates greater than
100 kHz) in all details, but may be used with care where higher rates are required by the application.
© 2007 Microchip Technology Inc.
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SCL pin is sampled high, the Baud Rate Generator is
reloaded with the contents of SSPADD<6:0> and
begins counting. This ensures that the SCL high time
will always be at least one BRG rollover count in the
event that the clock is held low by an external device
(Figure 17-18).
17.4.7.1
Clock Arbitration
Clock arbitration occurs when the master, during any
receive, transmit or Repeated Start/Stop condition,
deasserts the SCL pin (SCL allowed to float high).
When the SCL pin is allowed to float high, the Baud
Rate Generator (BRG) is suspended from counting
until the SCL pin is actually sampled high. When the
FIGURE 17-18:
BAUD RATE GENERATOR TIMING WITH CLOCK ARBITRATION
SDA
DX
DX – 1
SCL deasserted but slave holds
SCL low (clock arbitration)
SCL allowed to transition high
SCL
BRG decrements on
Q2 and Q4 cycles
BRG
Value
03h
02h
01h
00h (hold off)
03h
02h
SCL is sampled high, reload takes
place and BRG starts its count
BRG
Reload
DS39761B-page 214
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17.4.8
I2C MASTER MODE START
CONDITION TIMING
Note:
If at the beginning of the Start condition,
the SDA and SCL pins are already sam-
pled low, or if during the Start condition, the
SCL line is sampled low before the SDA
line is driven low, a bus collision occurs,
the Bus Collision Interrupt Flag, BCLIF, is
set, the Start condition is aborted and the
I2C module is reset into its Idle state.
To initiate a Start condition, the user sets the Start
Enable bit, SEN (SSPCON2<0>). If the SDA and SCL
pins are sampled high, the Baud Rate Generator is
reloaded with the contents of SSPADD<6:0> and starts
its count. If SCL and SDA are both sampled high when
the Baud Rate Generator times out (TBRG), the SDA
pin is driven low. The action of the SDA being driven
low while SCL is high is the Start condition and causes
the S bit (SSPSTAT<3>) to be set. Following this, the
Baud Rate Generator is reloaded with the contents of
SSPADD<6:0> and resumes its count. When the Baud
Rate Generator times out (TBRG), the SEN bit
(SSPCON2<0>) will be automatically cleared by
hardware, the Baud Rate Generator is suspended,
leaving the SDA line held low and the Start condition is
complete.
17.4.8.1
WCOL Status Flag
If the user writes the SSPBUF when a Start sequence
is in progress, the WCOL is set and the contents of the
buffer are unchanged (the write doesn’t occur).
Note:
Because queueing of events is not
allowed, writing to the lower 5 bits of
SSPCON2 is disabled until the Start
condition is complete.
FIGURE 17-19:
FIRST START BIT TIMING
Set S bit (SSPSTAT<3>)
At completion of Start bit,
Write to SEN bit occurs here
SDA = 1,
SCL = 1
hardware clears SEN bit
and sets SSPIF bit
TBRG
TBRG
Write to SSPBUF occurs here
1st bit 2nd bit
SDA
TBRG
SCL
TBRG
S
© 2007 Microchip Technology Inc.
Preliminary
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17.4.9
I2C MASTER MODE REPEATED
START CONDITION TIMING
Note 1: If RSEN is programmed while any other
event is in progress, it will not take effect.
A Repeated Start condition occurs when the RSEN bit
(SSPCON2<1>) is programmed high and the I2C logic
module is in the Idle state. When the RSEN bit is set,
the SCL pin is asserted low. When the SCL pin is
sampled low, the Baud Rate Generator is loaded with
the contents of SSPADD<5:0> and begins counting.
The SDA pin is released (brought high) for one Baud
Rate Generator count (TBRG). When the Baud Rate
Generator times out, if SDA is sampled high, the SCL
pin will be deasserted (brought high). When SCL is
sampled high, the Baud Rate Generator is reloaded
with the contents of SSPADD<6:0> and begins count-
ing. SDA and SCL must be sampled high for one TBRG.
This action is then followed by assertion of the SDA pin
(SDA = 0) for one TBRG while SCL is high. Following
this, the RSEN bit (SSPCON2<1>) will be automatically
cleared and the Baud Rate Generator will not be
reloaded, leaving the SDA pin held low. As soon as a
Start condition is detected on the SDA and SCL pins,
the S bit (SSPSTAT<3>) will be set. The SSPIF bit will
not be set until the Baud Rate Generator has timed out.
2: A bus collision during the Repeated Start
condition occurs if:
• SDA is sampled low when SCL goes
from low-to-high.
• SCL goes low before SDA is
asserted low. This may indicate that
another master is attempting to
transmit a data ‘1’.
Immediately following the SSPIF bit getting set, the user
may write the SSPBUF with the 7-bit address in 7-bit
mode, or the default first address in 10-bit mode. After
the first eight bits are transmitted and an ACK is
received, the user may then transmit an additional eight
bits of address (10-bit mode) or eight bits of data (7-bit
mode).
17.4.9.1
WCOL Status Flag
If the user writes the SSPBUF when a Repeated Start
sequence is in progress, the WCOL is set and the
contents of the buffer are unchanged (the write doesn’t
occur).
Note:
Because queueing of events is not
allowed, writing of the lower 5 bits of
SSPCON2 is disabled until the Repeated
Start condition is complete.
FIGURE 17-20:
REPEATED START CONDITION WAVEFORM
Set S (SSPSTAT<3>)
Write to SSPCON2
occurs here.
SDA = 1,
SDA = 1,
SCL = 1
At completion of Start bit,
hardware clears RSEN bit
and sets SSPIF
SCL (no change).
TBRG
TBRG
TBRG
1st bit
SDA
Write to SSPBUF occurs here
TBRG
Falling edge of ninth clock,
end of Xmit
SCL
TBRG
Sr = Repeated Start
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Preliminary
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17.4.10 I2C MASTER MODE
TRANSMISSION
17.4.10.3 ACKSTAT Status Flag
In Transmit mode, the ACKSTAT bit (SSPCON2<6>) is
cleared when the slave has sent an Acknowledge
(ACK = 0) and is set when the slave does not Acknowl-
edge (ACK = 1). A slave sends an Acknowledge when
it has recognized its address (including a general call),
or when the slave has properly received its data.
Transmission of a data byte, a 7-bit address or the
other half of a 10-bit address is accomplished by simply
writing a value to the SSPBUF register. This action will
set the Buffer Full flag bit, BF and allow the Baud Rate
Generator to begin counting and start the next
transmission. Each bit of address/data will be shifted
out onto the SDA pin after the falling edge of SCL is
asserted (see data hold time specification parameter
106). SCL is held low for one Baud Rate Generator
rollover count (TBRG). Data should be valid before SCL
is released high (see data setup time specification
parameter 107). When the SCL pin is released high, it
is held that way for TBRG. The data on the SDA pin
must remain stable for that duration and some hold
time after the next falling edge of SCL. After the eighth
bit is shifted out (the falling edge of the eighth clock),
the BF flag is cleared and the master releases SDA.
This allows the slave device being addressed to
respond with an ACK bit during the ninth bit time if an
address match occurred, or if data was received
properly. The status of ACK is written into the ACKDT
bit on the falling edge of the ninth clock. If the master
receives an Acknowledge, the Acknowledge status bit,
ACKSTAT, is cleared. If not, the bit is set. After the ninth
clock, the SSPIF bit is set and the master clock (Baud
Rate Generator) is suspended until the next data byte
is loaded into the SSPBUF, leaving SCL low and SDA
unchanged (Figure 17-21).
17.4.11 I2C MASTER MODE RECEPTION
Master mode reception is enabled by programming the
Receive Enable bit, RCEN (SSPCON2<3>).
Note:
The MSSP module must be in an Idle state
before the RCEN bit is set or the RCEN bit
will be disregarded.
The Baud Rate Generator begins counting and on each
rollover, the state of the SCL pin changes (high-to-low/
low-to-high) and data is shifted into the SSPSR. After
the falling edge of the eighth clock, the receive enable
flag is automatically cleared, the contents of the
SSPSR are loaded into the SSPBUF, the BF flag bit is
set, the SSPIF flag bit is set and the Baud Rate
Generator is suspended from counting, holding SCL
low. The MSSP is now in Idle state awaiting the next
command. When the buffer is read by the CPU, the BF
flag bit is automatically cleared. The user can then
send an Acknowledge bit at the end of reception by
setting the Acknowledge sequence enable bit, ACKEN
(SSPCON2<4>).
17.4.11.1 BF Status Flag
After the write to the SSPBUF, each bit of address will
be shifted out on the falling edge of SCL until all seven
address bits and the R/W bit are completed. On the fall-
ing edge of the eighth clock, the master will deassert
the SDA pin, allowing the slave to respond with an
Acknowledge. On the falling edge of the ninth clock, the
master will sample the SDA pin to see if the address
was recognized by a slave. The status of the ACK bit is
loaded into the ACKSTAT status bit (SSPCON2<6>).
Following the falling edge of the ninth clock transmis-
sion of the address, the SSPIF is set, the BF flag is
cleared and the Baud Rate Generator is turned off until
another write to the SSPBUF takes place, holding SCL
low and allowing SDA to float.
In receive operation, the BF bit is set when an address
or data byte is loaded into SSPBUF from SSPSR. It is
cleared when the SSPBUF register is read.
17.4.11.2 SSPOV Status Flag
In receive operation, the SSPOV bit is set when 8 bits
are received into the SSPSR and the BF flag bit is
already set from a previous reception.
17.4.11.3 WCOL Status Flag
If the user writes the SSPBUF when a receive is
already in progress (i.e., SSPSR is still shifting in a data
byte), the WCOL bit is set and the contents of the buffer
are unchanged (the write doesn’t occur).
17.4.10.1 BF Status Flag
In Transmit mode, the BF bit (SSPSTAT<0>) is set
when the CPU writes to SSPBUF and is cleared when
all 8 bits are shifted out.
17.4.10.2 WCOL Status Flag
If the user writes the SSPBUF when a transmit is
already in progress (i.e., SSPSR is still shifting out a
data byte), the WCOL is set and the contents of the
buffer are unchanged (the write doesn’t occur).
WCOL must be cleared in software.
© 2007 Microchip Technology Inc.
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2
FIGURE 17-21:
I C™ MASTER MODE WAVEFORM (TRANSMISSION, 7 OR 10-BIT ADDRESS)
DS39761B-page 218
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2
FIGURE 17-22:
I C™ MASTER MODE WAVEFORM (RECEPTION, 7-BIT ADDRESS)
© 2007 Microchip Technology Inc.
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17.4.12 ACKNOWLEDGE SEQUENCE
TIMING
17.4.13 STOP CONDITION TIMING
A Stop bit is asserted on the SDA pin at the end of a
receive/transmit by setting the Stop Sequence Enable
bit, PEN (SSPCON2<2>). At the end of a receive/
transmit, the SCL line is held low after the falling edge
of the ninth clock. When the PEN bit is set, the master
will assert the SDA line low. When the SDA line is
sampled low, the Baud Rate Generator is reloaded and
counts down to 0. When the Baud Rate Generator
times out, the SCL pin will be brought high and one
TBRG (Baud Rate Generator rollover count) later, the
SDA pin will be deasserted. When the SDA pin is
An Acknowledge sequence is enabled by setting the
Acknowledge
sequence
enable
bit,
ACKEN
(SSPCON2<4>). When this bit is set, the SCL pin is
pulled low and the contents of the Acknowledge data bit
are presented on the SDA pin. If the user wishes to gen-
erate an Acknowledge, then the ACKDT bit should be
cleared. If not, the user should set the ACKDT bit before
starting an Acknowledge sequence. The Baud Rate
Generator then counts for one rollover period (TBRG)
and the SCL pin is deasserted (pulled high). When the
SCL pin is sampled high (clock arbitration), the Baud
Rate Generator counts for TBRG. The SCL pin is then
pulled low. Following this, the ACKEN bit is automatically
cleared, the Baud Rate Generator is turned off and the
MSSP module then goes into Idle mode (Figure 17-23).
sampled high while SCL is high, the
(SSPSTAT<4>) is set. A TBRG later, the PEN bit is
cleared and the SSPIF bit is set (Figure 17-24).
P
bit
17.4.13.1 WCOL Status Flag
If the user writes the SSPBUF when a Stop sequence
is in progress, then the WCOL bit is set and the
contents of the buffer are unchanged (the write doesn’t
occur).
17.4.12.1 WCOL Status Flag
If the user writes the SSPBUF when an Acknowledge
sequence is in progress, then WCOL is set and the
contents of the buffer are unchanged (the write doesn’t
occur).
FIGURE 17-23:
ACKNOWLEDGE SEQUENCE WAVEFORM
Acknowledge sequence starts here,
write to SSPCON2
ACKEN automatically cleared
TBRG
ACKEN = 1, ACKDT = 0
TBRG
SDA
SCL
D0
ACK
8
9
SSPIF
Cleared in
software
Set SSPIF at the
end of receive
Cleared in
software
Set SSPIF at the end
of Acknowledge sequence
Note: TBRG = one Baud Rate Generator period.
FIGURE 17-24:
STOP CONDITION RECEIVE OR TRANSMIT MODE
Write to SSPCON2,
set PEN
SCL = 1for TBRG, followed by SDA = 1for TBRG
after SDA sampled high. P bit (SSPSTAT<4>) is set.
Falling edge of
9th clock
PEN bit (SSPCON2<2>) is cleared by
hardware and the SSPIF bit is set
TBRG
SCL
ACK
SDA
P
TBRG
TBRG
TBRG
SCL brought high after TBRG
SDA asserted low before rising edge of clock
to setup Stop condition
Note: TBRG = one Baud Rate Generator period.
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17.4.14 SLEEP OPERATION
17.4.17 MULTI-MASTER COMMUNICATION,
While in Sleep mode, the I2C module can receive
addresses or data and when an address match or
complete byte transfer occurs, wake the processor
from Sleep (if the MSSP interrupt is enabled).
BUS COLLISION AND BUS
ARBITRATION
Multi-Master mode support is achieved by bus arbitra-
tion. When the master outputs address/data bits onto
the SDA pin, arbitration takes place when the master
outputs a ‘1’ on SDA, by letting SDA float high and
another master asserts a ‘0’. When the SCL pin floats
high, data should be stable. If the expected data on
SDA is a ‘1’ and the data sampled on the SDA pin = 0,
then a bus collision has taken place. The master will set
the Bus Collision Interrupt Flag, BCLIF and reset the
I2C port to its Idle state (Figure 17-25).
17.4.15 EFFECT OF A RESET
A Reset disables the MSSP module and terminates the
current transfer.
17.4.16 MULTI-MASTER MODE
In Multi-Master mode, the interrupt generation on the
detection of the Start and Stop conditions allows the
determination of when the bus is free. The Stop (P) and
Start (S) bits are cleared from a Reset or when the
MSSP module is disabled. Control of the I2C bus may
be taken when the P bit (SSPSTAT<4>) is set, or the
bus is Idle, with both the S and P bits clear. When the
bus is busy, enabling the MSSP interrupt will generate
the interrupt when the Stop condition occurs.
If a transmit was in progress when the bus collision
occurred, the transmission is halted, the BF flag is
cleared, the SDA and SCL lines are deasserted and the
SSPBUF can be written to. When the user services the
bus collision Interrupt Service Routine and if the I2C
bus is free, the user can resume communication by
asserting a Start condition.
In multi-master operation, the SDA line must be
monitored for arbitration to see if the signal level is the
expected output level. This check is performed in
hardware with the result placed in the BCLIF bit.
If a Start, Repeated Start, Stop or Acknowledge
condition was in progress when the bus collision
occurred, the condition is aborted, the SDA and SCL
lines are deasserted and the respective control bits in
the SSPCON2 register are cleared. When the user ser-
vices the bus collision Interrupt Service Routine and if
the I2C bus is free, the user can resume communication
by asserting a Start condition.
The states where arbitration can be lost are:
• Address Transfer
• Data Transfer
• A Start Condition
The master will continue to monitor the SDA and SCL
pins. If a Stop condition occurs, the SSPIF bit will be set.
• A Repeated Start Condition
• An Acknowledge Condition
A write to the SSPBUF will start the transmission of
data at the first data bit regardless of where the
transmitter left off when the bus collision occurred.
In Multi-Master mode, the interrupt generation on the
detection of Start and Stop conditions allows the determi-
nation of when the bus is free. Control of the I2C bus can
be taken when the P bit is set in the SSPSTAT register,
or the bus is Idle and the S and P bits are cleared.
FIGURE 17-25:
BUS COLLISION TIMING FOR TRANSMIT AND ACKNOWLEDGE
Sample SDA. While SCL is high,
data doesn’t match what is driven
by the master.
Data changes
while SCL = 0
SDA line pulled low
by another source
Bus collision has occurred.
SDA released
by master
SDA
SCL
Set bus collision
interrupt (BCLIF)
BCLIF
© 2007 Microchip Technology Inc.
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If the SDA pin is sampled low during this count, the
17.4.17.1 Bus Collision During a
Start Condition
BRG is reset and the SDA line is asserted early
(Figure 17-28). If, however, a ‘1’ is sampled on the SDA
pin, the SDA pin is asserted low at the end of the BRG
count. The Baud Rate Generator is then reloaded and
counts down to 0 and during this time, if the SCL pins
are sampled as ‘0’, a bus collision does not occur. At
the end of the BRG count, the SCLpin is asserted low.
During a Start condition, a bus collision occurs if:
a) SDA or SCL are sampled low at the beginning of
the Start condition (Figure 17-26).
b) SCL is sampled low before SDA is asserted low
(Figure 17-27).
During a Start condition, both the SDA and the SCL
pins are monitored.
Note:
The reason that bus collision is not a factor
during a Start condition is that no two bus
masters can assert a Start condition at the
exact same time. Therefore, one master
will always assert SDA before the other.
This condition does not cause a bus
collision because the two masters must be
allowed to arbitrate the first address
following the Start condition. If the address
is the same, arbitration must be allowed to
continue into the data portion, Repeated
Start or Stop conditions.
If the SDA pin is already low, or the SCL pin is already
low, then all of the following occur:
• the Start condition is aborted,
• the BCLIF flag is set; and
• the MSSP module is reset to its Idle state
(Figure 17-26).
The Start condition begins with the SDA and SCL pins
deasserted. When the SDA pin is sampled high, the
Baud Rate Generator is loaded from SSPADD<6:0>
and counts down to 0. If the SCL pin is sampled low
while SDA is high, a bus collision occurs because it is
assumed that another master is attempting to drive a
data ‘1’ during the Start condition.
FIGURE 17-26:
BUS COLLISION DURING START CONDITION (SDA ONLY)
SDA goes low before the SEN bit is set.
Set BCLIF,
S bit and SSPIF set because
SDA = 0, SCL = 1.
SDA
SCL
SEN
Set SEN, enable Start
condition if SDA = 1, SCL = 1
SEN cleared automatically because of bus collision.
MSSP module reset into Idle state.
SDA sampled low before
Start condition. Set BCLIF.
S bit and SSPIF set because
SDA = 0, SCL = 1.
BCLIF
SSPIF and BCLIF are
cleared in software
S
SSPIF
SSPIF and BCLIF are
cleared in software
DS39761B-page 222
Preliminary
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FIGURE 17-27:
BUS COLLISION DURING START CONDITION (SCL = 0)
SDA = 0, SCL = 1
TBRG
TBRG
SDA
Set SEN, enable Start
sequence if SDA = 1, SCL = 1
SCL
SEN
SCL = 0before SDA = 0,
bus collision occurs. Set BCLIF.
SCL = 0before BRG time-out,
bus collision occurs. Set BCLIF.
BCLIF
Interrupt cleared
in software
S
‘0’
‘0’
‘0’
‘0’
SSPIF
FIGURE 17-28:
BRG RESET DUE TO SDA ARBITRATION DURING START CONDITION
SDA = 0, SCL = 1
Set S
Set SSPIF
Less than TBRG
TBRG
SDA pulled low by other master.
Reset BRG and assert SDA.
SDA
SCL
SEN
S
SCL pulled low after BRG
time-out
Set SEN, enable START
sequence if SDA = 1, SCL = 1
‘0’
BCLIF
S
SSPIF
SDA = 0, SCL = 1,
Interrupts cleared
in software
set SSPIF
© 2007 Microchip Technology Inc.
Preliminary
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If SDA is low, a bus collision has occurred (i.e., another
17.4.17.2 Bus Collision During a Repeated
Start Condition
master is attempting to transmit a data ‘0’, Figure 17-29).
If SDA is sampled high, the BRG is reloaded and begins
counting. If SDA goes from high to low before the BRG
times out, no bus collision occurs because no two
masters can assert SDA at exactly the same time.
During a Repeated Start condition, a bus collision
occurs if:
a) A low level is sampled on SDA when SCL goes
from low level to high level.
If SCL goes from high to low before the BRG times out
and SDA has not already been asserted, a bus collision
occurs. In this case, another master is attempting to
transmit a data ‘1’ during the Repeated Start condition,
see Figure 17-30.
b) SCL goes low before SDA is asserted low,
indicating that another master is attempting to
transmit a data ‘1’.
When the user deasserts SDA and the pin is allowed to
float high, the BRG is loaded with SSPADD<6:0> and
counts down to 0. The SCL pin is then deasserted and
when sampled high, the SDA pin is sampled.
If, at the end of the BRG time-out, both SCL and SDA
are still high, the SDA pin is driven low and the BRG is
reloaded and begins counting. At the end of the count,
regardless of the status of the SCL pin, the SCL pin is
driven low and the Repeated Start condition is complete.
FIGURE 17-29:
BUS COLLISION DURING A REPEATED START CONDITION (CASE 1)
SDA
SCL
Sample SDA when SCL goes high.
If SDA = 0, set BCLIF and release SDA and SCL.
RSEN
BCLIF
Cleared in software
‘0’
S
‘0’
SSPIF
FIGURE 17-30:
BUS COLLISION DURING A REPEATED START CONDITION (CASE 2)
TBRG
TBRG
SDA
SCL
SCL goes low before SDA,
set BCLIF. Release SDA and SCL.
BCLIF
RSEN
Interrupt cleared
in software
‘0’
S
SSPIF
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The Stop condition begins with SDA asserted low.
When SDA is sampled low, the SCL pin is allowed to
float. When the pin is sampled high (clock arbitration),
the Baud Rate Generator is loaded with SSPADD<6:0>
and counts down to 0. After the BRG times out, SDA is
sampled. If SDA is sampled low, a bus collision has
occurred. This is due to another master attempting to
drive a data ‘0’ (Figure 17-31). If the SCL pin is
sampled low before SDA is allowed to float high, a bus
collision occurs. This is another case of another master
attempting to drive a data ‘0’ (Figure 17-32).
17.4.17.3 Bus Collision During a Stop
Condition
Bus collision occurs during a Stop condition if:
a) After the SDA pin has been deasserted and
allowed to float high, SDA is sampled low after
the BRG has timed out.
b) After the SCL pin is deasserted, SCL is sampled
low before SDA goes high.
FIGURE 17-31:
BUS COLLISION DURING A STOP CONDITION (CASE 1)
SDA sampled
low after TBRG,
set BCLIF
TBRG
TBRG
TBRG
SDA
SDA asserted low
SCL
PEN
BCLIF
P
‘0’
‘0’
SSPIF
FIGURE 17-32:
BUS COLLISION DURING A STOP CONDITION (CASE 2)
TBRG
TBRG
TBRG
SDA
SCL goes low before SDA goes high,
set BCLIF
Assert SDA
SCL
PEN
BCLIF
P
‘0’
‘0’
SSPIF
© 2007 Microchip Technology Inc.
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NOTES:
DS39761B-page 226
Preliminary
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The pins of the Enhanced USART are multiplexed
with PORTC. In order to configure RC6/TX/CK and
RC7/RX/DT as an EUSART:
18.0 ENHANCED UNIVERSAL
SYNCHRONOUS RECEIVER
TRANSMITTER (EUSART)
• bit SPEN (RCSTA<7>) must be set (= 1)
• bit TRISC<7> must be set (= 1)
The Enhanced Universal Synchronous Asynchronous
Receiver Transmitter (EUSART) module is one of the
two serial I/O modules. (USART is also known as a
Serial Communications Interface or SCI.) The
EUSART can be configured as a full-duplex asynchro-
nous system that can communicate with peripheral
devices, such as CRT terminals and personal comput-
ers. It can also be configured as a half-duplex synchro-
nous system that can communicate with peripheral
devices, such as A/D or D/A integrated circuits, serial
EEPROMs and so on.
• bit TRISC<6> must be cleared (= 0) for
Asynchronous and Synchronous Master modes,
or set (= 1) for Synchronous Slave mode
Note:
The EUSART control will automatically
reconfigure the pin from input to output as
needed.
The operation of the Enhanced USART module is
controlled through three registers:
• Transmit Status and Control (TXSTA)
• Receive Status and Control (RCSTA)
• Baud Rate Control (BAUDCON)
The EUSART module implements additional features,
including Auto-Baud Rate Detection and calibration,
automatic wake-up on Sync Break reception and 12-bit
Break character transmit. These features make it
ideally suited for use in Local Interconnect Network bus
(LIN bus) systems.
These are detailed on the following pages in
Register 18-1, Register 18-2 and Register 18-3,
respectively.
The EUSART can be configured in the following
modes:
• Asynchronous (full duplex) with:
- Auto-Wake-up on Character Reception
- Auto-Baud Calibration
- 12-Bit Break Character Transmission
• Synchronous – Master (half duplex) with
Selectable Clock Polarity
• Synchronous – Slave (half duplex) with
Selectable Clock Polarity
© 2007 Microchip Technology Inc.
Preliminary
DS39761B-page 227
PIC18F2682/2685/4682/4685
REGISTER 18-1: TXSTA: TRANSMIT STATUS AND CONTROL REGISTER
R/W-0
CSRC
R/W-0
TX9
R/W-0
TXEN(1)
R/W-0
SYNC
R/W-0
R/W-0
BRGH
R-1
R/W-0
TX9D
SENDB
TRMT
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7
CSRC: Clock Source Select bit
Asynchronous mode:
Don’t care.
Synchronous mode:
1= Master mode (clock generated internally from BRG)
0= Slave mode (clock from external source)
bit 6
bit 5
bit 4
bit 3
TX9: 9-Bit Transmit Enable bit
1= Selects 9-bit transmission
0= Selects 8-bit transmission
TXEN: Transmit Enable bit(1)
1= Transmit enabled
0= Transmit disabled
SYNC: EUSART Mode Select bit
1= Synchronous mode
0= Asynchronous mode
SENDB: Send Break Character bit
Asynchronous mode:
1= Send Sync Break on next transmission (cleared by hardware upon completion)
0= Sync Break transmission completed
Synchronous mode:
Don’t care.
bit 2
BRGH: High Baud Rate Select bit
Asynchronous mode:
1= High speed
0= Low speed
Synchronous mode:
Unused in this mode.
bit 1
bit 0
TRMT: Transmit Shift Register Status bit
1= TSR empty
0= TSR full
TX9D: 9th bit of Transmit Data
Can be address/data bit or a parity bit.
Note 1: SREN/CREN overrides TXEN in Sync mode.
DS39761B-page 228
Preliminary
© 2007 Microchip Technology Inc.
PIC18F2682/2685/4682/4685
REGISTER 18-2: RCSTA: RECEIVE STATUS AND CONTROL REGISTER
R/W-0
SPEN
R/W-0
RX9
R/W-0
SREN
R/W-0
CREN
R/W-0
R-0
R-0
R-x
ADDEN
FERR
OERR
RX9D
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7
bit 6
bit 5
SPEN: Serial Port Enable bit
1= Serial port enabled (configures RX/DT and TX/CK pins as serial port pins)
0= Serial port disabled (held in Reset)
RX9: 9-Bit Receive Enable bit
1= Selects 9-bit reception
0= Selects 8-bit reception
SREN: Single Receive Enable bit
Asynchronous mode:
Don’t care.
Synchronous mode – Master:
1= Enables single receive
0= Disables single receive
This bit is cleared after reception is complete.
Synchronous mode – Slave:
Don’t care.
bit 4
CREN: Continuous Receive Enable bit
Asynchronous mode:
1= Enables receiver
0= Disables receiver
Synchronous mode:
1= Enables continuous receive until enable bit CREN is cleared (CREN overrides SREN)
0= Disables continuous receive
bit 3
ADDEN: Address Detect Enable bit
Asynchronous mode 9-bit (RX9 = 1):
1= Enables address detection, enables interrupt and loads the receive buffer when RSR<8> is set
0= Disables address detection, all bytes are received and ninth bit can be used as parity bit
Asynchronous mode 9-bit (RX9 = 0):
Don’t care.
bit 2
bit 1
bit 0
FERR: Framing Error bit
1= Framing error (can be updated by reading RCREG register and receiving next valid byte)
0= No framing error
OERR: Overrun Error bit
1= Overrun error (can be cleared by clearing bit CREN)
0= No overrun error
RX9D: 9th bit of Received Data
This can be an address/data bit or a parity bit and must be calculated by user firmware.
© 2007 Microchip Technology Inc.
Preliminary
DS39761B-page 229
PIC18F2682/2685/4682/4685
REGISTER 18-3: BAUDCON: BAUD RATE CONTROL REGISTER
R/W-0
R-1
U-0
—
R/W-0
SCKP
R/W-0
U-0
—
R/W-0
WUE
R/W-0
ABDOVF
RCIDL
BRG16
ABDEN
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7
bit 6
ABDOVF: Auto-Baud Acquisition Rollover Status bit
1= A BRG rollover has occurred during Auto-Baud Rate Detect mode (must be cleared in software)
0= No BRG rollover has occurred
RCIDL: Receive Operation Idle Status bit
1= Receive operation is Idle
0= Receive operation is active
bit 5
bit 4
Unimplemented: Read as ‘0’
SCKP: Synchronous Clock Polarity Select bit
Asynchronous mode:
Unused in this mode.
Synchronous mode:
1= Idle state for clock (CK) is a high level
0= Idle state for clock (CK) is a low level
bit 3
BRG16: 16-Bit Baud Rate Register Enable bit
1= 16-bit Baud Rate Generator – SPBRGH and SPBRG
0= 8-bit Baud Rate Generator – SPBRG only (Compatible mode), SPBRGH value ignored
bit 2
bit 1
Unimplemented: Read as ‘0’
WUE: Wake-up Enable bit
Asynchronous mode:
1= EUSART will continue to sample the RX pin – interrupt generated on falling edge; bit cleared in
hardware on following rising edge
0= RX pin not monitored or rising edge detected
Synchronous mode:
Unused in this mode.
bit 0
ABDEN: Auto-Baud Detect Enable bit
Asynchronous mode:
1= Enable baud rate measurement on the next character. Requires reception of a Sync field (55h);
cleared in hardware upon completion.
0= Baud rate measurement disabled or completed
Synchronous mode:
Unused in this mode.
DS39761B-page 230
Preliminary
© 2007 Microchip Technology Inc.
PIC18F2682/2685/4682/4685
the high baud rate (BRGH = 1) or the 16-bit BRG to
reduce the baud rate error, or achieve a slow baud rate
18.1 Baud Rate Generator (BRG)
The BRG is a dedicated 8-bit or 16-bit generator that
supports both the Asynchronous and Synchronous
modes of the EUSART. By default, the BRG operates
in 8-bit mode; setting the BRG16 bit (BAUDCON<3>)
selects 16-bit mode.
for a fast oscillator frequency.
Writing a new value to the SPBRGH:SPBRG registers
causes the BRG timer to be reset (or cleared). This
ensures that the BRG does not wait for a timer overflow
before outputting the new baud rate.
The SPBRGH:SPBRG register pair controls the period
of a free-running timer. In Asynchronous mode, bits
BRGH (TXSTA<2>) and BRG16 (BAUDCON<3>) also
control the baud rate. In Synchronous mode, BRGH is
ignored. Table 18-1 shows the formula for computation
of the baud rate for different EUSART modes which
only apply in Master mode (internally generated clock).
18.1.1
OPERATION IN POWER-MANAGED
MODES
The device clock is used to generate the desired baud
rate. When one of the power-managed modes is
entered, the new clock source may be operating at a
different frequency. This may require an adjustment to
the value in the SPBRG register pair.
Given the desired baud rate and FOSC, the nearest
integer value for the SPBRGH:SPBRG registers can be
calculated using the formulas in Table 18-1. From this,
the error in baud rate can be determined. An example
calculation is shown in Example 18-1. Typical baud rates
and error values for the various Asynchronous modes
are shown in Table 18-2. It may be advantageous to use
18.1.2
SAMPLING
The data on the RX pin is sampled three times by a
majority detect circuit to determine if a high or a low
level is present at the RX pin.
TABLE 18-1: BAUD RATE FORMULAS
Configuration Bits
BRG/EUSART Mode
Baud Rate Formula
SYNC
BRG16
BRGH
0
0
0
0
1
1
0
0
1
1
0
1
0
1
0
1
x
x
8-bit/Asynchronous
8-bit/Asynchronous
16-bit/Asynchronous
16-bit/Asynchronous
8-bit/Synchronous
16-bit/Synchronous
FOSC/[64 (n + 1)]
FOSC/[16 (n + 1)]
FOSC/[4 (n + 1)]
Legend: x= Don’t care, n = value of SPBRGH:SPBRG register pair
EXAMPLE 18-1: CALCULATING BAUD RATE ERROR
For a device with FOSC of 16 MHz, desired baud rate of 9600, Asynchronous mode, 8-bit BRG:
Desired Baud Rate FOSC/(64 ([SPBRGH:SPBRG] + 1)
Solving for SPBRGH:SPBRG:
=
X
=
=
=
=
=
=
=
((FOSC/Desired Baud Rate)/64) – 1
((16000000/9600)/64) – 1
[25.042] = 25
16000000/(64 (25 + 1))
9615
Calculated Baud Rate
Error
(Calculated Baud Rate – Desired Baud Rate)/Desired Baud Rate
(9615 – 9600)/9600 = 0.16%
TABLE 18-2: REGISTERS ASSOCIATED WITH BAUD RATE GENERATOR
Reset Values
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
on page
TXSTA
RCSTA
CSRC
SPEN
TX9
RX9
TXEN
SREN
—
SYNC
CREN
SCKP
SENDB
ADDEN
BRG16
BRGH
FERR
—
TRMT
OERR
WUE
TX9D
RX9D
51
51
51
51
51
BAUDCON ABDOVF RCIDL
ABDEN
SPBRGH
SPBRG
EUSART Baud Rate Generator Register High Byte
EUSART Baud Rate Generator Register Low Byte
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the BRG.
© 2007 Microchip Technology Inc.
Preliminary
DS39761B-page 231
PIC18F2682/2685/4682/4685
TABLE 18-3: BAUD RATES FOR ASYNCHRONOUS MODES
SYNC = 0, BRGH = 0, BRG16 = 0
BAUD
RATE
(K)
FOSC = 40.000 MHz
FOSC = 20.000 MHz
FOSC = 10.000 MHz
FOSC = 8.000 MHz
Actual
Rate
(K)
SPBRG Actual
value
SPBRG Actual
value
(decimal)
SPBRG Actual
value
(decimal)
SPBRG
value
(decimal)
%
%
Error
%
Error
%
Error
Rate
(K)
Rate
(K)
Rate
(K)
Error
(decimal)
0.3
1.2
—
—
—
—
—
—
—
255
129
31
15
4
—
—
—
129
64
15
7
—
1.201
2.403
9.615
—
—
-0.16
-0.16
-0.16
—
—
103
51
12
—
—
—
1.221
1.73
0.16
1.73
1.73
8.51
-9.58
1.202
2.404
9.766
19.531
52.083
78.125
0.16
0.16
1.73
1.73
-9.58
-32.18
2.4
2.441
9.615
19.531
56.818
125.000
1.73
0.16
1.73
-1.36
8.51
255
64
31
10
4
2.404
9.6
9.766
19.2
57.6
115.2
19.531
62.500
104.167
2
—
—
—
2
1
—
—
—
SYNC = 0, BRGH = 0, BRG16 = 0
BAUD
RATE
(K)
FOSC = 4.000 MHz
FOSC = 2.000 MHz
FOSC = 1.000 MHz
Actual
Rate
(K)
SPBRG Actual
value
SPBRG Actual
value
(decimal)
SPBRG
value
(decimal)
%
%
Error
%
Error
Rate
(K)
Rate
(K)
Error
(decimal)
0.3
1.2
0.300
1.202
0.16
0.16
207
51
25
6
0.300
1.201
2.403
—
-0.16
-0.16
-0.16
—
103
25
12
—
0.300
1.201
—
-0.16
-0.16
—
51
12
—
—
—
—
—
2.4
2.404
0.16
9.6
8.929
-6.99
8.51
—
—
19.2
57.6
115.2
20.833
62.500
62.500
2
—
—
—
—
—
8.51
0
—
—
—
—
—
-45.75
0
—
—
—
—
—
SYNC = 0, BRGH = 1, BRG16 = 0
BAUD
RATE
(K)
FOSC = 40.000 MHz
FOSC = 20.000 MHz
FOSC = 10.000 MHz
FOSC = 8.000 MHz
Actual
Rate
(K)
SPBRG Actual
value
(decimal)
SPBRG Actual
value
(decimal)
SPBRG Actual
value
(decimal)
SPBRG
value
%
Error
%
Error
%
Error
%
Error
Rate
(K)
Rate
(K)
Rate
(K)
(decimal)
0.3
1.2
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
2.4
—
—
—
—
—
—
2.441
9.615
19.531
56.818
125.000
1.73
0.16
1.73
-1.36
8.51
255
64
31
10
4
2.403
9.615
19.230
55.555
—
-0.16
-0.16
-0.16
3.55
—
207
51
25
8
9.6
9.766
19.231
58.140
113.636
1.73
0.16
0.94
-1.36
255
129
42
9.615
19.231
56.818
113.636
0.16
0.16
-1.36
-1.36
129
64
21
10
19.2
57.6
115.2
21
—
SYNC = 0, BRGH = 1, BRG16 = 0
BAUD
RATE
(K)
FOSC = 4.000 MHz
FOSC = 2.000 MHz
FOSC = 1.000 MHz
Actual
Rate
(K)
SPBRG Actual
value
SPBRG Actual
value
(decimal)
SPBRG
value
(decimal)
%
%
Error
%
Error
Rate
(K)
Rate
(K)
Error
(decimal)
0.3
1.2
—
—
—
207
103
25
12
3
—
1.201
2.403
9.615
—
—
-0.16
-0.16
-0.16
—
—
103
51
12
—
0.300
1.201
2.403
—
-0.16
-0.16
-0.16
—
207
51
25
—
1.202
0.16
0.16
0.16
0.16
8.51
8.51
2.4
2.404
9.6
9.615
19.2
57.6
115.2
19.231
62.500
125.000
—
—
—
—
—
—
—
—
—
1
—
—
—
—
—
—
DS39761B-page 232
Preliminary
© 2007 Microchip Technology Inc.
PIC18F2682/2685/4682/4685
TABLE 18-3: BAUD RATES FOR ASYNCHRONOUS MODES (CONTINUED)
SYNC = 0, BRGH = 0, BRG16 = 1
BAUD
RATE
(K)
FOSC = 40.000 MHz
FOSC = 20.000 MHz FOSC = 10.000 MHz
FOSC = 8.000 MHz
Actual
Rate
(K)
SPBRG Actual
value
SPBRG Actual
SPBRG Actual
value
(decimal)
SPBRG
value
(decimal)
%
%
Error
%
Error
%
Error
Rate
(K)
value
Rate
(K)
Rate
(K)
Error
(decimal)
(decimal)
0.3
1.2
0.300
1.200
0.00
0.02
0.06
0.16
0.16
0.94
-1.36
8332
2082
1040
259
129
42
0.300
1.200
0.02
-0.03
-0.03
0.16
4165
1041
520
129
64
0.300
1.200
0.02
-0.03
0.16
0.16
1.73
-1.36
8.51
2082
520
259
64
0.300
1.201
2.403
9.615
19.230
55.555
—
-0.04
-0.16
-0.16
-0.16
-0.16
3.55
—
1665
415
207
51
2.4
2.402
2.399
2.404
9.6
9.615
9.615
9.615
19.2
57.6
115.2
19.231
58.140
113.636
19.231
56.818
113.636
0.16
19.531
56.818
125.000
31
25
-1.36
-1.36
21
10
8
21
10
4
—
SYNC = 0, BRGH = 0, BRG16 = 1
BAUD
RATE
(K)
FOSC = 4.000 MHz
FOSC = 2.000 MHz
FOSC = 1.000 MHz
Actual
Rate
(K)
SPBRG Actual
value
SPBRG Actual
value
(decimal)
SPBRG
value
(decimal)
%
%
Error
%
Error
Rate
(K)
Rate
(K)
Error
(decimal)
0.3
1.2
0.300
1.202
0.04
0.16
0.16
0.16
0.16
8.51
8.51
832
207
103
25
12
3
0.300
1.201
2.403
9.615
—
-0.16
-0.16
-0.16
-0.16
—
415
103
51
12
—
0.300
1.201
2.403
—
-0.16
-0.16
-0.16
—
207
51
25
—
2.4
2.404
9.6
9.615
19.2
57.6
115.2
19.231
62.500
125.000
—
—
—
—
—
—
—
—
—
1
—
—
—
—
—
—
SYNC = 0, BRGH = 1, BRG16 = 1or SYNC = 1, BRG16 = 1
FOSC = 20.000 MHz FOSC = 10.000 MHz
BAUD
RATE
(K)
FOSC = 40.000 MHz
FOSC = 8.000 MHz
Actual
Rate
(K)
SPBRG Actual
SPBRG Actual
SPBRG Actual
value
SPBRG
value
(decimal)
%
Error
%
%
%
Error
value
(decimal)
Rate
(K)
value
Rate
(K)
Rate
(K)
Error
Error
(decimal)
(decimal)
0.3
1.2
0.300
1.200
0.00
0.00
0.02
0.06
-0.03
0.35
-0.22
33332
8332
4165
1040
520
0.300
1.200
0.00
0.02
0.02
-0.03
0.16
-0.22
0.94
16665
4165
2082
520
259
86
0.300
1.200
0.00
0.02
0.06
0.16
0.16
0.94
-1.36
8332
2082
1040
259
129
42
0.300
1.200
-0.01
-0.04
-0.04
-0.16
-0.16
0.79
6665
1665
832
207
103
34
2.4
2.400
2.400
2.402
2.400
9.6
9.606
9.596
9.615
9.615
19.2
57.6
115.2
19.193
57.803
114.943
19.231
57.471
116.279
19.231
58.140
113.636
19.230
57.142
117.647
172
86
42
21
-2.12
16
SYNC = 0, BRGH = 1, BRG16 = 1or SYNC = 1, BRG16 = 1
FOSC = 4.000 MHz FOSC = 2.000 MHz FOSC = 1.000 MHz
BAUD
RATE
(K)
Actual
Rate
(K)
SPBRG Actual
SPBRG Actual
SPBRG
value
(decimal)
%
Error
%
Error
%
Error
value
Rate
(K)
value
Rate
(K)
(decimal)
(decimal)
0.3
1.2
0.300
1.200
0.01
0.04
0.16
0.16
0.16
2.12
-3.55
3332
832
415
103
51
0.300
1.201
2.403
9.615
19.230
55.555
—
-0.04
-0.16
-0.16
-0.16
-0.16
3.55
—
1665
415
207
51
0.300
1.201
2.403
9.615
19.230
—
-0.04
-0.16
-0.16
-0.16
-0.16
—
832
207
103
25
2.4
2.404
9.6
9.615
19.2
57.6
115.2
19.231
58.824
111.111
25
12
16
8
—
8
—
—
—
—
© 2007 Microchip Technology Inc.
Preliminary
DS39761B-page 233
PIC18F2682/2685/4682/4685
While the ABD sequence takes place, the EUSART
state machine is held in Idle. The RCIF interrupt is set
once the fifth rising edge on RX is detected. The value
in the RCREG needs to be read to clear the RCIF
interrupt. ThecontentsofRCREGshouldbediscarded.
18.1.3
AUTO-BAUD RATE DETECT
The Enhanced USART module supports the automatic
detection and calibration of baud rate. This feature is
active only in Asynchronous mode and while the WUE
bit is clear.
Note 1: If the WUE bit is set with the ABDEN bit,
Auto-Baud Rate Detection will occur on
the byte following the Break character.
The automatic baud rate measurement sequence
(Figure 18-1) begins whenever a Start bit is received
and the ABDEN bit is set. The calculation is
self-averaging.
2: It is up to the user to determine that the
incoming character baud rate is within the
range of the selected BRG clock source.
In the Auto-Baud Rate Detect (ABD) mode, the clock to
the BRG is reversed. Rather than the BRG clocking the
incoming RX signal, the RX signal is timing the BRG. In
ABD mode, the internal Baud Rate Generator is used
as a counter to time the bit period of the incoming serial
byte stream.
Some
combinations
of
oscillator
frequency and EUSART baud rates are
not possible due to bit error rates. Overall
system timing and communication baud
rates must be taken into consideration
when using the Auto-Baud Rate
Detection feature.
Once the ABDEN bit is set, the state machine will clear
the BRG and look for a Start bit. The Auto-Baud Rate
Detection must receive a byte with the value 55h
(ASCII “U”, which is also the LIN bus Sync character)
in order to calculate the proper bit rate. The measure-
ment is taken over both a low and high bit time in order
to minimize any effects caused by asymmetry of the
incoming signal. After a Start bit, the SPBRG begins
counting up, using the preselected clock source on the
first rising edge of RX. After eight bits on the RX pin or
the fifth rising edge, an accumulated value totalling the
proper BRG period is left in the SPBRGH:SPBRG
register pair. Once the 5th edge is seen (this should
correspond to the Stop bit), the ABDEN bit is
automatically cleared.
TABLE 18-4: BRG COUNTER
CLOCK RATES
BRG16 BRGH
BRG Counter Clock
0
0
1
1
0
1
0
1
FOSC/512
FOSC/128
FOSC/128
FOSC/32
Note: During the ABD sequence, SPBRG and
SPBRGH are both used as a 16-bit counter,
independent of the BRG16 setting.
If a rollover of the BRG occurs (an overflow from FFFFh
to 0000h), the event is trapped by the ABDOVF status
bit (BAUDCON<7>). It is set in hardware by BRG
rollovers and can be set or cleared by the user in
software. ABD mode remains active after rollover
events and the ABDEN bit remains set (Figure 18-2).
18.1.3.1
ABD and EUSART Transmission
Since the BRG clock is reversed during ABD acquisi-
tion, the EUSART transmitter cannot be used during
ABD. This means that whenever the ABDEN bit is set,
TXREG cannot be written to. Users should also ensure
that ABDEN does not become set during a transmit
sequence. Failing to do this may result in unpredictable
EUSART operation.
While calibrating the baud rate period, the BRG
registers are clocked at 1/8th the preconfigured clock
rate. Note that the BRG clock will be configured by the
BRG16 and BRGH bits. Independent of the BRG16 bit
setting, both the SPBRG and SPBRGH will be used as
a 16-bit counter. This allows the user to verify that no
carry occurred for 8-bit modes by checking for 00h in
the SPBRGH register. Refer to Table 18-4 for counter
clock rates to the BRG.
DS39761B-page 234
Preliminary
© 2007 Microchip Technology Inc.
PIC18F2682/2685/4682/4685
FIGURE 18-1:
BRG Value
AUTOMATIC BAUD RATE CALCULATION
XXXXh
0000h
001Ch
Edge #5
Edge #2
bit 3
Edge #3
bit 5
bit 4
Edge #4
bit 7
Edge #1
bit 1
RX pin
Start
bit 2
bit 6
Stop bit
bit 0
BRG Clock
Auto-Cleared
Set by User
ABDEN bit
RCIF bit
(Interrupt)
Read
RCREG
XXXXh
XXXXh
1Ch
00h
SPBRG
SPBRGH
Note: The ABD sequence requires the EUSART module to be configured in Asynchronous mode and WUE = 0.
FIGURE 18-2:
BRG OVERFLOW SEQUENCE
BRG Clock
ABDEN bit
RX pin
Start
bit 0
ABDOVF bit
BRG Value
FFFFh
XXXXh
0000h
0000h
© 2007 Microchip Technology Inc.
Preliminary
DS39761B-page 235
PIC18F2682/2685/4682/4685
Once the TXREG register transfers the data to the TSR
18.2 EUSART Asynchronous Mode
register (occurs in one TCY), the TXREG register is empty
and the TXIF flag bit (PIR1<4>) is set. This interrupt can
be enabled or disabled by setting or clearing the interrupt
enable bit, TXIE (PIE1<4>). TXIF will be set regardless of
the state of TXIE; it cannot be cleared in software. TXIF
is also not cleared immediately upon loading TXREG, but
becomes valid in the second instruction cycle following
the load instruction. Polling TXIF immediately following a
load of TXREG will return invalid results.
The Asynchronous mode of operation is selected by
clearing the SYNC bit (TXSTA<4>). In this mode, the
EUSART uses standard Non-Return-to-Zero (NRZ)
format (one Start bit, eight or nine data bits and one
Stop bit). The most common data format is 8 bits. An
on-chip, dedicated 8-bit/16-bit Baud Rate Generator
can be used to derive standard baud rate frequencies
from the oscillator.
The EUSART transmits and receives the LSb first. The
EUSART’s transmitter and receiver are functionally
independent but use the same data format and baud
rate. The Baud Rate Generator produces a clock, either
x16 or x64 of the bit shift rate depending on the BRGH
and BRG16 bits (TXSTA<2> and BAUDCON<3>). Parity
is not supported by the hardware, but can be
implemented in software and stored as the 9th data bit.
While TXIF indicates the status of the TXREG register,
another bit, TRMT (TXSTA<1>), shows the status of
the TSR register. TRMT is a read-only bit which is set
when the TSR register is empty. No interrupt logic is
tied to this bit so the user has to poll this bit in order to
determine if the TSR register is empty.
Note 1: The TSR register is not mapped in data
memory so it is not available to the user.
When operating in Asynchronous mode, the EUSART
module consists of the following important elements:
2: Flag bit, TXIF, is set when enable bit,
TXEN, is set.
• Baud Rate Generator
To set up an Asynchronous Transmission:
• Sampling Circuit
• Asynchronous Transmitter
• Asynchronous Receiver
• Auto-Wake-up on Sync Break Character
• 12-Bit Break Character Transmit
• Auto-Baud Rate Detection
1. Initialize the SPBRGH:SPBRG registers for the
appropriate baud rate. Set or clear the BRGH
and BRG16 bits, as required, to achieve the
desired baud rate.
2. Enable the asynchronous serial port by clearing
bit SYNC and setting bit SPEN.
18.2.1
EUSART ASYNCHRONOUS
TRANSMITTER
3. If interrupts are desired, set enable bit TXIE.
4. If 9-bit transmission is desired, set transmit bit
TX9. Can be used as address/data bit.
The EUSART transmitter block diagram is shown in
Figure 18-3. The heart of the transmitter is the Transmit
(Serial) Shift Register (TSR). The Shift register obtains
its data from the Read/Write Transmit Buffer register,
TXREG. The TXREG register is loaded with data in
software. The TSR register is not loaded until the Stop
bit has been transmitted from the previous load. As
soon as the Stop bit is transmitted, the TSR is loaded
with new data from the TXREG register (if available).
5. Enable the transmission by setting bit TXEN
which will also set bit TXIF.
6. If 9-bit transmission is selected, the ninth bit
should be loaded in bit TX9D.
7. Load data to the TXREG register (starts
transmission).
8. If using interrupts, ensure that the GIE and PEIE
bits in the INTCON register (INTCON<7:6>) are
set.
FIGURE 18-3:
EUSART TRANSMIT BLOCK DIAGRAM
Data Bus
TXREG Register
TXIF
TXIE
8
MSb
(8)
LSb
0
Pin Buffer
and Control
•
•
•
TSR Register
TX pin
Interrupt
Baud Rate CLK
SPBRG
TXEN
TRMT
SPEN
BRG16
SPBRGH
TX9
TX9D
Baud Rate Generator
DS39761B-page 236
Preliminary
© 2007 Microchip Technology Inc.
PIC18F2682/2685/4682/4685
FIGURE 18-4:
ASYNCHRONOUS TRANSMISSION
Write to TXREG
Word 1
BRG Output
(Shift Clock)
TX
(pin)
Start bit
bit 0
bit 1
Word 1
bit 7/8
Stop bit
TXIF bit
(Transmit Buffer
Reg. Empty Flag)
1 TCY
Word 1
Transmit Shift Reg
TRMT bit
(Transmit Shift
Reg. Empty Flag)
FIGURE 18-5:
ASYNCHRONOUS TRANSMISSION (BACK-TO-BACK)
Write to TXREG
Word 2
Word 1
BRG Output
(Shift Clock)
TX
(pin)
Start bit
Start bit
Word 2
bit 0
bit 1
bit 7/8
bit 0
Stop bit
1 TCY
Word 1
TXIF bit
(Interrupt Reg. Flag)
1 TCY
Word 1
Transmit Shift Reg.
Word 2
Transmit Shift Reg.
TRMT bit
(Transmit Shift
Reg. Empty Flag)
Note:
This timing diagram shows two consecutive transmissions.
TABLE 18-5: REGISTERS ASSOCIATED WITH ASYNCHRONOUS TRANSMISSION
Reset
Values
on page
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
INTCON
PIR1
GIE/GIEH PEIE/GIEL TMR0IE
INT0IE
TXIF
RBIE
SSPIF
SSPIE
SSPIP
ADDEN
TMR0IF
CCP1IF
INT0IF
RBIF
49
52
52
52
51
51
51
51
51
51
PSPIF(1)
PSPIE(1)
PSPIP(1)
SPEN
ADIF
ADIE
ADIP
RX9
RCIF
RCIE
RCIP
SREN
TMR2IF
TMR1IF
PIE1
TXIE
CCP1IE TMR2IE TMR1IE
CCP1IP TMR2IP TMR1IP
IPR1
TXIP
RCSTA
TXREG
TXSTA
BAUDCON
SPBRGH
SPBRG
CREN
FERR
OERR
RX9D
EUSART Transmit Register
CSRC
TX9
TXEN
—
SYNC
SCKP
SENDB
BRG16
BRGH
—
TRMT
WUE
TX9D
ABDOVF
RCIDL
ABDEN
EUSART Baud Rate Generator Register High Byte
EUSART Baud Rate Generator Register Low Byte
Legend: — = unimplemented locations read as ‘0’. Shaded cells are not used for asynchronous transmission.
Note 1: Reserved in PIC18F2682/2685 devices; always maintain these bits clear.
© 2007 Microchip Technology Inc.
Preliminary
DS39761B-page 237
PIC18F2682/2685/4682/4685
18.2.2
EUSART ASYNCHRONOUS
RECEIVER
18.2.3
SETTING UP 9-BIT MODE WITH
ADDRESS DETECT
The receiver block diagram is shown in Figure 18-6.
The data is received on the RX pin and drives the data
recovery block. The data recovery block is actually a
high-speed shifter operating at x16 times the baud rate,
whereas the main receive serial shifter operates at the
bit rate or at FOSC. This mode would typically be used
in RS-232 systems.
This mode would typically be used in RS-485 systems.
To set up an Asynchronous Reception with Address
Detect Enable:
1. Initialize the SPBRGH:SPBRG registers for the
appropriate baud rate. Set or clear the BRGH
and BRG16 bits, as required, to achieve the
desired baud rate.
To set up an Asynchronous Reception:
2. Enable the asynchronous serial port by clearing
the SYNC bit and setting the SPEN bit.
1. Initialize the SPBRGH:SPBRG registers for the
appropriate baud rate. Set or clear the BRGH
and BRG16 bits, as required, to achieve the
desired baud rate.
3. If interrupts are required, set the RCEN bit and
select the desired priority level with the RCIP bit.
4. Set the RX9 bit to enable 9-bit reception.
5. Set the ADDEN bit to enable address detect.
6. Enable reception by setting the CREN bit.
2. Enable the asynchronous serial port by clearing
bit SYNC and setting bit SPEN.
3. If interrupts are desired, set enable bit, RCIE.
4. If 9-bit reception is desired, set bit RX9.
5. Enable the reception by setting bit CREN.
7. The RCIF bit will be set when reception is
complete. The interrupt will be Acknowledged if
the RCIE and GIE bits are set.
6. Flag bit RCIF will be set when reception is
complete and an interrupt will be generated if
enable bit RCIE was set.
8. Read the RCSTA register to determine if any
error occurred during reception, as well as read
bit 9 of data (if applicable).
7. Read the RCSTA register to get the 9th bit (if
enabled) and determine if any error occurred
during reception.
9. Read RCREG to determine if the device is being
addressed.
10. If any error occurred, clear the CREN bit.
8. Read the 8-bit received data by reading the
RCREG register.
11. If the device has been addressed, clear the
ADDEN bit to allow all received data into the
receive buffer and interrupt the CPU.
9. If any error occurred, clear the error by clearing
enable bit CREN.
10. If using interrupts, ensure that the GIE and PEIE
bits in the INTCON register (INTCON<7:6>) are
set.
FIGURE 18-6:
EUSART RECEIVE BLOCK DIAGRAM
CREN
OERR
FERR
x64 Baud Rate CLK
SPBRG
÷ 64
or
RSR Register
• • •
LSb
MSb
BRG16
SPBRGH
÷ 16
Stop (8)
7
1
0
Start
or
÷ 4
Baud Rate Generator
RX9
Pin Buffer
and Control
Data
Recovery
RX
RX9D
RCREG Register
FIFO
SPEN
8
RCIF
RCIE
Interrupt
Data Bus
DS39761B-page 238
Preliminary
© 2007 Microchip Technology Inc.
PIC18F2682/2685/4682/4685
FIGURE 18-7:
ASYNCHRONOUS RECEPTION
Start
bit
Start
bit
Start
bit
RX (pin)
Stop
bit
Stop
bit
Stop
bit
bit 0
bit 7/8
bit 0 bit 1
bit 7/8
bit 7/8
Rcv Shift Reg
Rcv Buffer Reg
Word 2
RCREG
Word 1
RCREG
Read Rcv
Buffer Reg
RCREG
RCIF
(Interrupt Flag)
OERR bit
CREN
Note:
This timing diagram shows three words appearing on the RX input. The RCREG (Receive Buffer) is read after the third word
causing the OERR (Overrun) bit to be set.
TABLE 18-6: REGISTERS ASSOCIATED WITH ASYNCHRONOUS RECEPTION
Reset
Values
on page
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
INTCON
PIR1
GIE/GIEH PEIE/GIEL TMR0IE
INT0IE
TXIF
RBIE
SSPIF
SSPIE
SSPIP
ADDEN
TMR0IF
CCP1IF
INT0IF
RBIF
49
52
52
52
51
51
51
51
51
51
PSPIF(1)
PSPIE(1)
PSPIP(1)
SPEN
ADIF
ADIE
ADIP
RX9
RCIF
RCIE
RCIP
SREN
TMR2IF TMR1IF
PIE1
TXIE
CCP1IE TMR2IE TMR1IE
CCP1IP TMR2IP TMR1IP
IPR1
TXIP
RCSTA
RCREG
TXSTA
BAUDCON
SPBRGH
SPBRG
CREN
FERR
OERR
RX9D
EUSART Receive Register
CSRC
TX9
TXEN
—
SYNC
SCKP
SENDB
BRG16
BRGH
—
TRMT
WUE
TX9D
ABDOVF
RCIDL
ABDEN
EUSART Baud Rate Generator Register High Byte
EUSART Baud Rate Generator Register Low Byte
Legend: — = unimplemented locations read as ‘0’. Shaded cells are not used for asynchronous reception.
Note 1: Reserved in PIC18F2682/2685 devices; always maintain these bits clear.
© 2007 Microchip Technology Inc.
Preliminary
DS39761B-page 239
PIC18F2682/2685/4682/4685
Character and cause data or framing errors. To work
properly, therefore, the initial character in the trans-
mission must be all ‘0’s. This can be 00h (8 bytes) for
standard RS-232 devices or 000h (12 bits) for LIN bus.
18.2.4
AUTO-WAKE-UP ON SYNC BREAK
CHARACTER
During Sleep mode, all clocks to the EUSART are
suspended. Because of this, the Baud Rate Generator
is inactive and a proper byte reception cannot be
performed. The auto-wake-up feature allows the
controller to wake-up due to activity on the RX/DT line
while the EUSART is operating in Asynchronous mode.
Oscillator start-up time must also be considered,
especially in applications using oscillators with longer
start-up intervals (i.e., XT or HS mode). The Sync
Break (or Wake-up Signal) character must be of
sufficient length and be followed by a sufficient interval
to allow enough time for the selected oscillator to start
and provide proper initialization of the EUSART.
The auto-wake-up feature is enabled by setting the
WUE bit (BAUDCON<1>). Once set, the typical receive
sequence on RX/DT is disabled and the EUSART
remains in an Idle state, monitoring for a wake-up event
independent of the CPU mode. A wake-up event
consists of a high-to-low transition on the RX/DT line.
(This coincides with the start of a Sync Break or a
Wake-up Signal character for the LIN protocol.)
18.2.4.2
Special Considerations Using
the WUE Bit
The timing of WUE and RCIF events may cause some
confusion when it comes to determining the validity of
received data. As noted, setting the WUE bit places the
EUSART in an Idle mode. The wake-up event causes
a receive interrupt by setting the RCIF bit. The WUE bit
is cleared after this when a rising edge is seen on RX/
DT. The interrupt condition is then cleared by reading
the RCREG register. Ordinarily, the data in RCREG will
be dummy data and should be discarded.
Following a wake-up event, the module generates an
RCIF interrupt. The interrupt is generated synchro-
nously to the Q clocks in normal operating modes
(Figure 18-8) and asynchronously, if the device is in
Sleep mode (Figure 18-9). The interrupt condition is
cleared by reading the RCREG register.
The WUE bit is automatically cleared once a low-to-high
transition is observed on the RX line following the wake-
up event. At this point, the EUSART module is in Idle
mode and returns to normal operation. This signals to
the user that the Sync Break event is over.
The fact that the WUE bit has been cleared (or is still
set), and the RCIF flag is set, should not be used as an
indicator of the integrity of the data in RCREG. Users
should consider implementing a parallel method in
firmware to verify received data integrity.
To assure that no actual data is lost, check the RCIDL
bit to verify that a receive operation is not in process. If
a receive operation is not occurring, the WUE bit may
then be set just prior to entering the Sleep mode.
18.2.4.1
Special Considerations Using
Auto-Wake-up
Since auto-wake-up functions by sensing rising edge
transitions on RX/DT, information with any state
changes before the Stop bit may signal a false End-of-
FIGURE 18-8:
AUTO-WAKE-UP BIT (WUE) TIMINGS DURING NORMAL OPERATION
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
OSC1
WUE bit(1)
RX/DT Line
RCIF
Bit set by user
Auto-Cleared
Cleared due to user read of RCREG
Note 1:The EUSART remains in Idle while the WUE bit is set.
FIGURE 18-9:
AUTO-WAKE-UP BIT (WUE) TIMINGS DURING SLEEP
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
Q1
Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
OSC1
WUE bit(2)
RX/DT Line
RCIF
Bit set by user
Auto-Cleared
Note 1
Cleared due to user read of RCREG
Sleep Ends
SLEEPCommand Executed
Note 1: If the wake-up event requires long oscillator warm-up time, the auto-clear of the WUE bit can occur while the stposc signal is still active.
This sequence should not depend on the presence of Q clocks.
2: The EUSART remains in Idle while the WUE bit is set.
DS39761B-page 240
Preliminary
© 2007 Microchip Technology Inc.
PIC18F2682/2685/4682/4685
1. Configure the EUSART for the desired mode.
18.2.5
BREAK CHARACTER SEQUENCE
2. Set the TXEN and SENDB bits to set up the
Break character.
The Enhanced EUSART module has the capability of
sending the special Break character sequences that
are required by the LIN bus standard. The Break char-
acter transmit consists of a Start bit, followed by twelve
‘0’ bits and a Stop bit. The frame Break character is
sent whenever the SENDB and TXEN bits (TXSTA<3>
and TXSTA<5>) are set while the Transmit Shift
register is loaded with data. Note that the value of data
written to TXREG will be ignored and all ‘0’s will be
transmitted.
3. Load the TXREG with a dummy character to
initiate transmission (the value is ignored).
4. Write ‘55h’ to TXREG to load the Sync character
into the transmit FIFO buffer.
5. After the Break has been sent, the SENDB bit is
reset by hardware. The Sync character now
transmits in the preconfigured mode.
When the TXREG becomes empty, as indicated by the
TXIF, the next data byte can be written to TXREG.
The SENDB bit is automatically reset by hardware after
the corresponding Stop bit is sent. This allows the user
to preload the transmit FIFO with the next transmit byte
following the Break character (typically, the Sync
character in the LIN specification).
18.2.6
RECEIVING A BREAK CHARACTER
The Enhanced USART module can receive a Break
character in two ways.
Note that the data value written to the TXREG for the
Break character is ignored. The write simply serves the
purpose of initiating the proper sequence.
The first method forces configuration of the baud rate
at a frequency of 9/13 the typical speed. This allows for
the Stop bit transition to be at the correct sampling
location (13 bits for Break versus Start bit and 8 data
bits for typical data).
The TRMT bit indicates when the transmit operation is
active or Idle, just as it does during normal transmis-
sion. See Figure 18-10 for the timing of the Break
character sequence.
The second method uses the auto-wake-up feature
described in Section 18.2.4 “Auto-Wake-up on Sync
Break Character”. By enabling this feature, the
EUSART will sample the next two transitions on RX/DT,
cause an RCIF interrupt and receive the next data byte
followed by another interrupt.
18.2.5.1
Break and Sync Transmit Sequence
The following sequence will send a message frame
header made up of a Break, followed by an Auto-Baud
Sync byte. This sequence is typical of a LIN bus
master.
Note that following a Break character, the user will
typically want to enable the Auto-Baud Rate Detect
feature. For both methods, the user can set the ABD bit
once the TXIF interrupt is observed.
FIGURE 18-10:
SEND BREAK CHARACTER SEQUENCE
Write to TXREG
Dummy Write
BRG Output
(Shift Clock)
TX (pin)
Start Bit
Bit 0
Bit 1
Break
Bit 11
Stop Bit
TXIF bit
(Transmit Buffer
Reg. Empty Flag)
TRMT bit
(Transmit Shift
Reg. Empty Flag)
SENDB sampled here
Auto-Cleared
SENDB
(Transmit Shift
Reg. Empty Flag)
© 2007 Microchip Technology Inc.
Preliminary
DS39761B-page 241
PIC18F2682/2685/4682/4685
Once the TXREG register transfers the data to the TSR
18.3 EUSART Synchronous
Master Mode
register (occurs in one TCYCLE), the TXREG is empty
and the TXIF flag bit (PIR1<4>) is set. The interrupt can
be enabled or disabled by setting or clearing the inter-
rupt enable bit, TXIE (PIE1<4>). TXIF is set regardless
of the state of enable bit TXIE; it cannot be cleared in
software. It will reset only when new data is loaded into
the TXREG register.
The Synchronous Master mode is entered by setting
the CSRC bit (TXSTA<7>). In this mode, the data is
transmitted in a half-duplex manner (i.e., transmission
and reception do not occur at the same time). When
transmitting data, the reception is inhibited and vice
versa. Synchronous mode is entered by setting bit
SYNC (TXSTA<4>). In addition, enable bit, SPEN
(RCSTA<7>), is set in order to configure the TX and RX
pins to CK (clock) and DT (data) lines, respectively.
While flag bit TXIF indicates the status of the TXREG
register, another bit, TRMT (TXSTA<1>), shows the
status of the TSR register. TRMT is a read-only bit which
is set when the TSR is empty. No interrupt logic is tied to
this bit so the user has to poll this bit in order to
determine if the TSR register is empty. The TSR is not
mapped in data memory so it is not available to the user.
The Master mode indicates that the processor trans-
mits the master clock on the CK line. Clock polarity is
selected with the SCKP bit (BAUDCON<4>); setting
SCKP sets the Idle state on CK as high, while clearing
the bit sets the Idle state as low. This option is provided
to support Microwire devices with this module.
To set up a Synchronous Master Transmission:
1. Initialize the SPBRGH:SPBRG registers for the
appropriate baud rate. Set or clear the BRG16
bit, as required, to achieve the desired baud
rate.
18.3.1
EUSART SYNCHRONOUS MASTER
TRANSMISSION
2. Enable the synchronous master serial port by
setting bits SYNC SPEN and CSRC.
The EUSART transmitter block diagram is shown in
Figure 18-3. The heart of the transmitter is the Transmit
(Serial) Shift Register (TSR). The Shift register obtains
its data from the Read/Write Transmit Buffer register,
TXREG. The TXREG register is loaded with data in
software. The TSR register is not loaded until the last
bit has been transmitted from the previous load. As
soon as the last bit is transmitted, the TSR is loaded
with new data from the TXREG (if available).
3. If interrupts are desired, set enable bit TXIE.
4. If 9-bit transmission is desired, set bit TX9.
5. Enable the transmission by setting bit TXEN.
6. If 9-bit transmission is selected, the ninth bit
should be loaded in bit TX9D.
7. Start transmission by loading data to the TXREG
register.
8. If using interrupts, ensure that the GIE and PEIE
bits in the INTCON register (INTCON<7:6>) are
set.
FIGURE 18-11:
SYNCHRONOUS TRANSMISSION
Q1 Q2 Q3Q4 Q1 Q2 Q3 Q4 Q1Q2 Q3Q4 Q1Q2 Q3 Q4 Q1Q2 Q3 Q4
Q3 Q4 Q1 Q2 Q3Q4 Q1Q2 Q3Q4 Q1 Q2Q3 Q4 Q1 Q2Q3 Q4 Q1Q2 Q3 Q4 Q1 Q2 Q3 Q4
RC7/RX/DT
pin
bit 0
bit 1
bit 2
bit 7
bit 0
bit 1
bit 7
Word 2
Word 1
RC6/TX/CK pin
(SCKP = 0)
RC6/TX/CK pin
(SCKP = 1)
Write to
TXREG Reg
Write Word 1
Write Word 2
TXIF bit
(Interrupt Flag)
TRMT bit
‘1’
‘1’
TXEN bit
Note: Sync Master mode, SPBRG = 0, continuous transmission of two 8-bit words.
DS39761B-page 242
Preliminary
© 2007 Microchip Technology Inc.
PIC18F2682/2685/4682/4685
FIGURE 18-12:
SYNCHRONOUS TRANSMISSION (THROUGH TXEN)
RC7/RX/DT pin
bit 0
bit 1
bit 2
bit 6
bit 7
RC6/TX/CK pin
Write to
TXREG reg
TXIF bit
TRMT bit
TXEN bit
TABLE 18-7: REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER TRANSMISSION
Reset
Values
on page
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
INTCON
PIR1
GIE/GIEH PEIE/GIEL TMR0IE
INT0IE
TXIF
RBIE
SSPIF
SSPIE
SSPIP
ADDEN
TMR0IF
INT0IF
RBIF
49
52
52
52
51
51
51
51
51
51
PSPIF(1)
PSPIE(1)
PSPIP(1)
SPEN
ADIF
ADIE
ADIP
RX9
RCIF
RCIE
RCIP
SREN
CCP1IF TMR2IF TMR1IF
CCP1IE TMR2IE TMR1IE
CCP1IP TMR2IP TMR1IP
PIE1
TXIE
IPR1
TXIP
RCSTA
TXREG
TXSTA
CREN
FERR
OERR
RX9D
EUSART Transmit Register
CSRC
TX9
TXEN
—
SYNC
SCKP
SENDB
BRG16
BRGH
—
TRMT
WUE
TX9D
BAUDCON ABDOVF
RCIDL
ABDEN
SPBRGH
SPBRG
EUSART Baud Rate Generator Register High Byte
EUSART Baud Rate Generator Register Low Byte
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used for synchronous master transmission.
Note 1: Reserved in PIC18F2682/2685 devices; always maintain these bits clear.
© 2007 Microchip Technology Inc.
Preliminary
DS39761B-page 243
PIC18F2682/2685/4682/4685
3. Ensure bits CREN and SREN are clear.
4. If interrupts are desired, set enable bit RCIE.
5. If 9-bit reception is desired, set bit RX9.
6. If a single reception is required, set bit SREN.
For continuous reception, set bit CREN.
7. Interrupt flag bit RCIF will be set when reception
is complete and an interrupt will be generated if
the enable bit RCIE was set.
8. Read the RCSTA register to get the 9th bit (if
enabled) and determine if any error occurred
during reception.
18.3.2
EUSART SYNCHRONOUS
MASTER RECEPTION
Once Synchronous mode is selected, reception is
enabled by setting either the Single Receive Enable bit,
SREN (RCSTA<5>), or the Continuous Receive
Enable bit, CREN (RCSTA<4>). Data is sampled on the
RX pin on the falling edge of the clock.
If enable bit SREN is set, only a single word is received.
If enable bit CREN is set, the reception is continuous
until CREN is cleared. If both bits are set, then CREN
takes precedence.
9. Read the 8-bit received data by reading the
RCREG register.
10. If any error occurred, clear the error by clearing
bit CREN.
11. If using interrupts, ensure that the GIE and PEIE
bits in the INTCON register (INTCON<7:6>) are
set.
To set up a Synchronous Master Reception:
1. Initialize the SPBRGH:SPBRG registers for the
appropriate baud rate. Set or clear the BRG16
bit, as required, to achieve the desired baud rate.
2. Enable the synchronous master serial port by
setting bits SYNC, SPEN and CSRC.
FIGURE 18-13:
SYNCHRONOUS RECEPTION (MASTER MODE, SREN)
Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4Q1 Q2 Q3 Q4 Q1Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
RC7/RX/DT
pin
bit 0
bit 1
bit 2
bit 3
bit 4
bit 5
bit 6
bit 7
RC7/TX/CK pin
(SCKP = 0)
RC7/TX/CK pin
(SCKP = 1)
Write to
bit SREN
SREN bit
CREN bit
‘0’
‘0’
RCIF bit
(Interrupt)
Read
RXREG
Note: Timing diagram demonstrates Sync Master mode with bit SREN = 1and bit BRGH = 0.
TABLE 18-8: REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER RECEPTION
ResetValues
on page
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
INTCON
PIR1
GIE/GIEH PEIE/GIEL
TMR0IE
RCIF
INT0IE
TXIF
RBIE
SSPIF
SSPIE
SSPIP
ADDEN
TMR0IF
CCP1IF
CCP1IE
CCP1IP
FERR
INT0IF
TMR2IF
TMR2IE
TMR2IP
OERR
RBIF
49
52
52
52
51
51
51
51
51
51
(1)
PSPIF
PSPIE
PSPIP
ADIF
ADIE
ADIP
RX9
TMR1IF
TMR1IE
TMR1IP
RX9D
(1)
(1)
PIE1
RCIE
TXIE
IPR1
RCIP
TXIP
RCSTA
RCREG
TXSTA
BAUDCON
SPBRGH
SPBRG
Legend:
SPEN
SREN
CREN
EUSART Receive Register
CSRC
TX9
TXEN
—
SYNC
SCKP
SENDB
BRG16
BRGH
—
TRMT
WUE
TX9D
ABDOVF
RCIDL
ABDEN
EUSART Baud Rate Generator Register High Byte
EUSART Baud Rate Generator Register Low Byte
— = unimplemented, read as ‘0’. Shaded cells are not used for synchronous master reception.
Note 1: Reserved in PIC18F2682/2685 devices; always maintain these bits clear.
DS39761B-page 244
Preliminary
© 2007 Microchip Technology Inc.
PIC18F2682/2685/4682/4685
To set up a Synchronous Slave Transmission:
18.4 EUSART Synchronous
Slave Mode
1. Enable the synchronous slave serial port by
setting bits SYNC and SPEN and clearing bit
Synchronous Slave mode is entered by clearing bit,
CSRC (TXSTA<7>). This mode differs from the
Synchronous Master mode in that the shift clock is sup-
plied externally at the CK pin (instead of being supplied
internally in Master mode). This allows the device to
transfer or receive data while in any low-power mode.
CSRC.
2. Clear bits CREN and SREN.
3. If interrupts are desired, set enable bit TXIE.
4. If 9-bit transmission is desired, set bit TX9.
5. Enable the transmission by setting enable bit
TXEN.
18.4.1
EUSART SYNCHRONOUS
SLAVE TRANSMIT
6. If 9-bit transmission is selected, the ninth bit
should be loaded in bit TX9D.
The operation of the Synchronous Master and Slave
modes are identical, except in the case of the Sleep
mode.
7. Start transmission by loading data to the
TXREGx register.
8. If using interrupts, ensure that the GIE and PEIE
bits in the INTCON register (INTCON<7:6>) are
set.
If two words are written to the TXREG and then the
SLEEPinstruction is executed, the following will occur:
a) The first word will immediately transfer to the
TSR register and transmit.
b) The second word will remain in the TXREG
register.
c) Flag bit TXIF will not be set.
d) When the first word has been shifted out of TSR,
the TXREG register will transfer the second
word to the TSR and flag bit TXIF will now be
set.
e) If enable bit TXIE is set, the interrupt will wake the
chip from Sleep. If the global interrupt is enabled,
the program will branch to the interrupt vector.
TABLE 18-9: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE TRANSMISSION
Reset
Values
on page
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
INTCON
PIR1
GIE/GIEH PEIE/GIEL TMR0IE
INT0IE
TXIF
RBIE
SSPIF
SSPIE
SSPIP
ADDEN
TMR0IF
CCP1IF
CCP1IE
CCP1IP
FERR
INT0IF
RBIF
49
52
52
52
51
51
51
51
51
51
PSPIF(1)
PSPIE(1)
PSPIP(1)
SPEN
ADIF
ADIE
ADIP
RX9
RCIF
RCIE
RCIP
SREN
TMR2IF
TMR1IF
PIE1
TXIE
TMR2IE TMR1IE
TMR2IP TMR1IP
IPR1
TXIP
RCSTA
TXREG
TXSTA
CREN
OERR
RX9D
EUSART Transmit Register
CSRC
TX9
TXEN
—
SYNC
SCKP
SENDB
BRG16
BRGH
—
TRMT
WUE
TX9D
BAUDCON ABDOVF
RCIDL
ABDEN
SPBRGH
SPBRG
EUSART Baud Rate Generator Register High Byte
EUSART Baud Rate Generator Register Low Byte
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used for synchronous slave transmission.
Note 1: Reserved in PIC18F2682/2685 devices; always maintain these bits clear.
© 2007 Microchip Technology Inc.
Preliminary
DS39761B-page 245
PIC18F2682/2685/4682/4685
To set up a Synchronous Slave Reception:
18.4.2
EUSART SYNCHRONOUS SLAVE
RECEPTION
1. Enable the synchronous master serial port by
setting bits SYNC and SPEN and clearing bit
CSRC.
The operation of the Synchronous Master and Slave
modes is identical, except in the case of Sleep or any
Idle mode, and bit SREN, which is a “don’t care” in
Slave mode.
2. If interrupts are desired, set enable bit RCIE.
3. If 9-bit reception is desired, set bit RX9.
4. To enable reception, set enable bit CREN.
If receive is enabled by setting the CREN bit prior to
entering Sleep or any Idle mode, then a word may be
received while in this low-power mode. Once the word
is received, the RSR register will transfer the data to the
RCREG register; if the RCIE enable bit is set, the inter-
rupt generated will wake the chip from the low-power
mode. If the global interrupt is enabled, the program will
branch to the interrupt vector.
5. Flag bit RCIF will be set when reception is
complete. An interrupt will be generated if
enable bit RCIE was set.
6. Read the RCSTA register to get the 9th bit (if
enabled) and determine if any error occurred
during reception.
7. Read the 8-bit received data by reading the
RCREG register.
8. If any error occurred, clear the error by clearing
bit CREN.
9. If using interrupts, ensure that the GIE and PEIE
bits in the INTCON register (INTCON<7:6>) are
set.
TABLE 18-10: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE RECEPTION
Reset
Values
on page
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
INTCON
PIR1
GIE/GIEH PEIE/GIEL TMR0IE
INT0IE
TXIF
RBIE
SSPIF
SSPIE
SSPIP
ADDEN
TMR0IF
CCP1IF
INT0IF
RBIF
49
52
52
52
51
51
51
51
51
51
PSPIF(1)
PSPIE(1)
PSPIP(1)
SPEN
ADIF
ADIE
ADIP
RX9
RCIF
RCIE
RCIP
SREN
TMR2IF TMR1IF
PIE1
TXIE
CCP1IE TMR2IE TMR1IE
CCP1IP TMR2IP TMR1IP
IPR1
TXIP
RCSTA
RCREG
TXSTA
CREN
FERR
OERR
RX9D
EUSART Receive Register
CSRC
TX9
TXEN
—
SYNC
SCKP
SENDB
BRG16
BRGH
—
TRMT
WUE
TX9D
BAUDCON ABDOVF
RCIDL
ABDEN
SPBRGH
SPBRG
EUSART Baud Rate Generator Register High Byte
EUSART Baud Rate Generator Register Low Byte
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used for synchronous slave reception.
Note 1: Reserved in PIC18F2682/2685 devices; always maintain these bits clear.
DS39761B-page 246
Preliminary
© 2007 Microchip Technology Inc.
PIC18F2682/2685/4682/4685
The module has five registers:
19.0 10-BIT ANALOG-TO-DIGITAL
• A/D Result High Register (ADRESH)
• A/D Result Low Register (ADRESL)
• A/D Control Register 0 (ADCON0)
• A/D Control Register 1 (ADCON1)
• A/D Control Register 2 (ADCON2)
CONVERTER (A/D) MODULE
The Analog-to-Digital (A/D) converter module has
8 inputs for the PIC18F2682/2685 devices and 11 for
the PIC18F4682/4685 devices. This module allows
conversion of an analog input signal to a corresponding
10-bit digital number.
The ADCON0 register, shown in Register 19-1, controls
the operation of the A/D module. The ADCON1 register,
shown in Register 19-2, configures the functions of the
port pins. The ADCON2 register, shown in Register 19-3,
configures the A/D clock source, programmed
acquisition time and justification.
REGISTER 19-1: ADCON0: A/D CONTROL REGISTER 0
U-0
—
U-0
—
R/W-0
CHS3
R/W-0
CHS2
R/W-0
CHS1
R/W-0
CHS0
R/W-0
R/W-0
ADON
GO/DONE
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7-6
bit 5-2
Unimplemented: Read as ‘0’
CHS3:CHS0: Analog Channel Select bits
0000= Channel 0 (AN0)
0001= Channel 1 (AN1)
0010= Channel 2 (AN2)
0011= Channel 3 (AN3)
0100= Channel 4 (AN4)
0101= Channel 5 (AN5)(1,2)
0110= Channel 6 (AN6)(1,2)
0111= Channel 7 (AN7)(1,2)
1000= Channel 8 (AN8)
1001= Channel 9 (AN9)
1010= Channel 10 (AN10)
1011= Unused
1100= Unused
1101= Unused
1110= Unused
1111= Unused
bit 1
bit 0
GO/DONE: A/D Conversion Status bit
When ADON = 1:
1= A/D conversion in progress
0= A/D Idle
ADON: A/D On bit
1= A/D converter module is enabled
0= A/D converter module is disabled
Note 1: These channels are not implemented on PIC18F2682/2685 devices.
2: Performing a conversion on unimplemented channels will return full-scale measurements.
© 2007 Microchip Technology Inc.
Preliminary
DS39761B-page 247
PIC18F2682/2685/4682/4685
REGISTER 19-2: ADCON1: A/D CONTROL REGISTER 1
U-0
—
U-0
—
R/W-0
R/W-0
R/W-0(1)
PCFG3
R/W-q(1)
PCFG2
R/W-q(1)
PCFG1
R/W-q(1)
PCFG0
VCFG1
VCFG0
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7-6
bit 5
Unimplemented: Read as ‘0’
VCFG1: Voltage Reference Configuration bit (VREF- source)
1= VREF- (AN2)
0= AVSS
bit 4
VCFG0: Voltage Reference Configuration bit (VREF+ source)
1= VREF+ (AN3)
0= AVDD
bit 3-0
PCFG3:PCFG0: A/D Port Configuration Control bits:
PCFG3:
PCFG0
0000(1)
0001
0010
0011
0100
0101
0110
0111(1)
1000
1001
1010
1011
1100
1101
1110
1111
A
A
A
A
A
D
D
D
D
D
D
D
D
D
D
D
A
A
A
A
A
A
D
D
D
D
D
D
D
D
D
D
A
A
A
A
A
A
A
D
D
D
D
D
D
D
D
D
A
A
A
A
A
A
A
A
D
D
D
D
D
D
D
D
A
A
A
A
A
A
A
A
A
D
D
D
D
D
D
D
A
A
A
A
A
A
A
A
A
A
D
D
D
D
D
D
A
A
A
A
A
A
A
A
A
A
A
D
D
D
D
D
A
A
A
A
A
A
A
A
A
A
A
A
D
D
D
D
A
A
A
A
A
A
A
A
A
A
A
A
A
D
D
D
A
A
A
A
A
A
A
A
A
A
A
A
A
A
D
D
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
D
A = Analog input
D = Digital I/O
Note 1: The POR value of the PCFG bits depends on the value of the PBADEN bit in Configuration Register 3H.
When PBADEN = 1, PCFG<3:0> = 0000; when PBADEN = 0, PCFG<3:0> = 0111.
2: AN5 through AN7 are available only on PIC18F4682/4685 devices.
DS39761B-page 248
Preliminary
© 2007 Microchip Technology Inc.
PIC18F2682/2685/4682/4685
REGISTER 19-3: ADCON2: A/D CONTROL REGISTER 2
R/W-0
ADFM
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
ACQT2
ACQT1
ACQT0
ADCS2
ADCS1
ADCS0
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7
ADFM: A/D Result Format Select bit
1= Right justified
0= Left justified
bit 6
Unimplemented: Read as ‘0’
bit 5-3
ACQT2:ACQT0: A/D Acquisition Time Select bits
111= 20 TAD
110= 16 TAD
101= 12 TAD
100= 8 TAD
011= 6 TAD
010= 4 TAD
001= 2 TAD
(1)
000= 0 TAD
bit 2-0
ADCS2:ADCS0: A/D Conversion Clock Select bits
111= FRC (clock derived from A/D RC oscillator)(1)
110= FOSC/64
101= FOSC/16
100= FOSC/4
011= FRC (clock derived from A/D RC oscillator)(1)
010= FOSC/32
001= FOSC/8
000= FOSC/2
Note 1: If the A/D FRC clock source is selected, a delay of one TCY (instruction cycle) is added before the A/D
clock starts. This allows the SLEEPinstruction to be executed before starting a conversion.
© 2007 Microchip Technology Inc.
Preliminary
DS39761B-page 249
PIC18F2682/2685/4682/4685
The analog reference voltage is software selectable to
either the device’s positive and negative supply voltage
(AVDD and AVSS), or the voltage level on the RA3/AN3/
VREF+ and RA2/AN2/VREF-/CVREF pins.
A device Reset forces all registers to their Reset state.
This forces the A/D module to be turned off and any
conversion in progress is aborted.
Each port pin associated with the A/D converter can be
configured as an analog input, or as a digital I/O. The
ADRESH and ADRESL registers contain the result of
the A/D conversion. When the A/D conversion is
complete, the result is loaded into the ADRESH/
ADRESL registers, the GO/DONE bit (ADCON0
register) is cleared and A/D Interrupt Flag bit, ADIF, is
set. The block diagram of the A/D module is shown in
Figure 19-1.
The A/D converter has a unique feature of being able
to operate while the device is in Sleep mode. To
operate in Sleep, the A/D conversion clock must be
derived from the A/D converter’s internal RC oscillator.
The output of the sample and hold is the input into the
converter, which generates the result via successive
approximation.
FIGURE 19-1:
A/D BLOCK DIAGRAM
CHS3:CHS0
1010
AN10
1001
AN9
1000
AN8
0111
AN7(1)
0110
AN6(1)
0101
AN5(1)
0100
AN4
VAIN
0011
(Input Voltage)
10-Bit
A/D
Converter
AN3
0010
AN2
0001
VCFG1:VCFG0
AN1
(2)
AVDD
0000
AN0
X0
X1
1X
VREF+
VREF-
Reference
Voltage
0X
(2)
AVSS
Note 1: Channels AN5 through AN7 are not available on PIC18F2682/2685 devices.
2: I/O pins have diode protection to VDD and VSS.
DS39761B-page 250
Preliminary
© 2007 Microchip Technology Inc.
PIC18F2682/2685/4682/4685
The value in the ADRESH/ADRESL registers is not
The following steps should be followed to perform an
A/D conversion:
modified for a Power-on Reset. The ADRESH/ADRESL
registers will contain unknown data after a Power-on
Reset.
1. Configure the A/D module:
• Configure analog pins, voltage reference and
digital I/O (ADCON1)
After the A/D module has been configured as desired,
the selected channel must be acquired before the con-
version is started. The analog input channels must
have their corresponding TRIS bits selected as inputs.
To determine acquisition time, see Section 19.1 “A/D
Acquisition Requirements”. After this acquisition
time has elapsed, the A/D conversion can be started.
An acquisition time can be programmed to occur
between setting the GO/DONE bit and the actual start
of the conversion.
• Select A/D input channel (ADCON0)
• Select A/D acquisition time (ADCON2)
• Select A/D conversion clock (ADCON2)
• Turn on A/D module (ADCON0)
2. Configure A/D interrupt (if desired):
• Clear ADIF bit
• Set ADIE bit
• Set GIE bit
3. Wait the required acquisition time (if required).
4. Start conversion:
• Set GO/DONE bit (ADCON0 register)
5. Wait for A/D conversion to complete, by either:
• Polling for the GO/DONE bit to be cleared
OR
• Waiting for the A/D interrupt
6. Read A/D Result registers (ADRESH:ADRESL);
clear bit, ADIF, if required.
7. For next conversion, go to step 1 or step 2, as
required. The A/D conversion time per bit is
defined as TAD. A minimum wait of 2 TAD is
required before next acquisition starts.
FIGURE 19-2:
ANALOG INPUT MODEL
VDD
Sampling
Switch
VT = 0.6V
ANx
SS
RIC ≤ 1k
RSS
Rs
CPIN
VAIN
ILEAKAGE
500 nA
CHOLD = 120 pF
VT = 0.6V
5 pF
VSS
Legend: CPIN
= Input Capacitance
= Threshold Voltage
6V
5V
VDD 4V
VT
ILEAKAGE = Leakage Current at the pin due to
various junctions
3V
RIC
SS
= Interconnect Resistance
= Sampling Switch
2V
CHOLD
RSS
= Sample/Hold Capacitance (from DAC)
= Sampling Switch Resistance
5
6
7
8 9 10 11
Sampling Switch (kΩ)
© 2007 Microchip Technology Inc.
Preliminary
DS39761B-page 251
PIC18F2682/2685/4682/4685
To calculate the minimum acquisition time,
19.1 A/D Acquisition Requirements
Equation 19-1 may be used. This equation assumes
that 1/2 LSb error is used (1024 steps for the A/D). The
1/2 LSb error is the maximum error allowed for the A/D
to meet its specified resolution.
For the A/D converter to meet its specified accuracy,
the charge holding capacitor (CHOLD) must be allowed
to fully charge to the input channel voltage level. The
analog input model is shown in Figure 19-2. The
source impedance (RS) and the internal sampling
switch (RSS) impedance directly affect the time
required to charge the capacitor CHOLD. The sampling
switch (RSS) impedance varies over the device voltage
(VDD). The source impedance affects the offset voltage
at the analog input (due to pin leakage current). The
maximum recommended impedance for analog
sources is 2.5 kΩ. After the analog input channel is
selected (changed), the channel must be sampled for
at least the minimum acquisition time before starting a
conversion.
Example 19-3 shows the calculation of the minimum
required acquisition time TACQ. This calculation is
based on the following application system
assumptions:
CHOLD
Rs
Conversion Error
VDD
Temperature
VHOLD
=
=
≤
=
=
=
120 pF
2.5 kΩ
1/2 LSb
5V → Rss = 7 kΩ
50°C (system max.)
0V @ time = 0
Note:
When the conversion is started, the
holding capacitor is disconnected from the
input pin.
EQUATION 19-1: A/D ACQUISITION TIME
TACQ
=
Amplifier Settling Time + Holding Capacitor Charging Time + Temperature Coefficient
=
TAMP + TC + TCOFF
EQUATION 19-2: A/D MINIMUM CHARGING TIME
VHOLD =
or
(VREF – (VREF/2048)) • (1 – e(-Tc/CHOLD(RIC + RSS + RS))
)
TC
=
-(CHOLD)(RIC + RSS + RS) ln(1/2048)
EQUATION 19-3: CALCULATING THE MINIMUM REQUIRED A/D ACQUISITION TIME
TACQ
TAMP
TCOFF
=
=
=
TAMP + TC + TCOFF
5 μs
(Temp – 25°C)(0.05 μs/°C)
(50°C – 25°C)(0.05 μs/°C)
1.25 μs
Temperature coefficient is only required for temperatures > 25°C. Below 25°C, TCOFF = 0 ms.
TC
=
-(CHOLD)(RIC + RSS + RS) ln(1/2047) μs
-(120 pF) (1 kΩ + 7 kΩ + 2.5 kΩ) ln(0.0004883) μs
9.61 μs
TACQ
=
5 μs + 1.25 μs + 9.61 μs
12.86 μs
DS39761B-page 252
Preliminary
© 2007 Microchip Technology Inc.
PIC18F2682/2685/4682/4685
19.2 Selecting and Configuring
Automatic Acquisition Time
19.3 Selecting the A/D Conversion
Clock
The ADCON2 register allows the user to select an
acquisition time that occurs each time the GO/DONE
bit is set.
The A/D conversion time per bit is defined as TAD. The
A/D conversion requires 11 TAD per 10-bit conversion.
The source of the A/D conversion clock is software
selectable. There are seven possible options for TAD:
When the GO/DONE bit is set, sampling is stopped and
a conversion begins. The user is responsible for ensur-
ing the required acquisition time has passed between
selecting the desired input channel and setting the
GO/DONE bit. This occurs when the ACQT2:ACQT0
bits (ADCON2<5:3>) remain in their Reset state (‘000’)
and is compatible with devices that do not offer
programmable acquisition times.
• 2 TOSC
• 4 TOSC
• 8 TOSC
• 16 TOSC
• 32 TOSC
• 64 TOSC
• Internal RC Oscillator
If desired, the ACQT bits can be set to select a
programmable acquisition time for the A/D module.
When the GO/DONE bit is set, the A/D module
continues to sample the input for the selected
For correct A/D conversions, the A/D conversion clock
(TAD) must be as short as possible, but greater than the
minimum TAD (approximately 2 μs, see parameter 130
for more information).
acquisition time, then automatically begins
a
conversion. Since the acquisition time is programmed,
there may be no need to wait for an acquisition time
between selecting a channel and setting the GO/DONE
bit.
Table 19-1 shows the resultant TAD times derived from
the device operating frequencies and the A/D clock
source selected.
In either case, when the conversion is completed, the
GO/DONE bit is cleared, the ADIF flag is set and the
A/D begins sampling the currently selected channel
again. If an acquisition time is programmed, there is
nothing to indicate if the acquisition time has ended or
if the conversion has begun.
TABLE 19-1: TAD vs. DEVICE OPERATING FREQUENCIES
Maximum Device Frequency
PIC18F2682/2685/4682/4685 PIC18LF2682/2685/4682/4685(4)
AD Clock Source (TAD)
Operation
ADCS2:ADCS0
2 TOSC
4 TOSC
8 TOSC
16 TOSC
32 TOSC
64 TOSC
RC(3)
000
100
001
101
010
110
x11
2.86 MHz
5.71 MHz
11.43 MHz
22.86 MHz
40.0 MHz
40.0 MHz
1.00 MHz(1)
1.43 kHz
2.86 MHz
5.72 MHz
11.43 MHz
22.86 MHz
22.86 MHz
1.00 MHz(2)
Note 1: The RC source has a typical TAD time of 1.2 μs.
2: The RC source has a typical TAD time of 2.5 μs.
3: For device frequencies above 1 MHz, the device must be in Sleep for the entire conversion or the A/D
accuracy may be out of specification.
4: Low-power (PIC18LFXXXX) devices only.
© 2007 Microchip Technology Inc.
Preliminary
DS39761B-page 253
PIC18F2682/2685/4682/4685
19.4 Operation in Power-Managed
Modes
19.5 Configuring Analog Port Pins
The ADCON1, TRISA, TRISB and TRISE registers all
configure the A/D port pins. The port pins needed as
analog inputs must have their corresponding TRIS bits
set (input). If the TRIS bit is cleared (output), the digital
output level (VOH or VOL) will be converted.
The selection of the automatic acquisition time and A/D
conversion clock is determined in part, by the clock
source and frequency while in a power-managed mode.
If the A/D is expected to operate while the device is in
a power-managed mode, the ACQT2:ACQT0 and
ADCS2:ADCS0 bits in ADCON2 should be updated in
accordance with the clock source to be used in that
mode. After entering the mode, an A/D acquisition or
conversion may be started. Once started, the device
should continue to be clocked by the same clock
source until the conversion has been completed.
The A/D operation is independent of the state of the
CHS3:CHS0 bits and the TRIS bits.
Note 1: When reading the PORT register, all pins
configured as analog input channels will
read as cleared (a low level). Pins config-
ured as digital inputs will convert an
analog input. Analog levels on a digitally
configured input will be accurately
converted.
If desired, the device may be placed into the
corresponding Idle mode during the conversion. If the
device clock frequency is less than 1 MHz, the A/D RC
clock source should be selected.
2: Analog levels on any pin defined as a
digital input may cause the digital input
buffer to consume current out of the
device’s specification limits.
Operation in the Sleep mode requires the A/D FRC
clock to be selected. If the ACQT2:ACQT0 bits are set
to ‘000’ and a conversion is started, the conversion will
be delayed one instruction cycle to allow execution of
the SLEEP instruction and entry to Sleep mode. The
IDLEN bit (OSCCON<7>) must have already been
cleared prior to starting the conversion.
3: The PBADEN bit in Configuration
Register 3H configures PORTB pins to
reset as analog or digital pins by control-
ling how the PCFG0 bits in ADCON1 are
reset.
DS39761B-page 254
Preliminary
© 2007 Microchip Technology Inc.
PIC18F2682/2685/4682/4685
Clearing the GO/DONE bit during a conversion will
abort the current conversion. The A/D Result register
pair will NOT be updated with the partially completed
A/D conversion sample. This means the
ADRESH:ADRESL registers will continue to contain
the value of the last completed conversion (or the
last value written to the ADRESH:ADRESL
registers).
19.6 A/D Conversions
Figure 19-3 shows the operation of the A/D converter
after the GO/DONE bit has been set and the
ACQT2:ACQT0 bits are cleared. A conversion is
started after the following instruction to allow entry into
Sleep mode before the conversion begins.
Figure 19-4 shows the operation of the A/D converter
after the GO/DONE bit has been set, the
ACQT2:ACQT0 bits are set to ‘010’ and a 4 TAD
acquisition time is selected before the conversion
starts.
After the A/D conversion is completed or aborted, a
2 TAD wait is required before the next acquisition can
be started. After this wait, acquisition on the selected
channel is automatically started.
Note:
The GO/DONE bit should NOT be set in
the same instruction that turns on the A/D.
FIGURE 19-3:
A/D CONVERSION TAD CYCLES (ACQT<2:0> = 000, TACQ = 0)
TCY - TAD
TAD6 TAD7 TAD8 TAD9 TAD10 TAD11
TAD1 TAD2 TAD3 TAD4 TAD5
b7
b6
b4
b1
b0
b9
b8
b5
b3
b2
Conversion starts
Holding capacitor is disconnected from analog input (typically 100 ns)
Set GO/DONE bit
On the following cycle:
ADRESH:ADRESL is loaded, GO/DONE bit is cleared,
ADIF bit is set, holding capacitor is connected to analog input.
FIGURE 19-4:
A/D CONVERSION TAD CYCLES (ACQT<2:0> = 010, TACQ = 4 TAD)
TAD Cycles
TACQT Cycles
6
7
8
9
10
b1
11
b0
1
2
3
4
1
2
3
4
5
b7
b6
b3
b2
b8
b5
b4
b9
Automatic
Acquisition
Time
Conversion starts
(Holding capacitor is disconnected)
Set GO/DONE bit
(Holding capacitor continues
acquiring input)
On the following cycle:
ADRESH:ADRESL is loaded, GO/DONE bit is cleared,
ADIF bit is set, holding capacitor is connected to analog input.
© 2007 Microchip Technology Inc.
Preliminary
DS39761B-page 255
PIC18F2682/2685/4682/4685
software overhead (moving ADRESH/ADRESL to the
19.7 Use of the ECCP1 Trigger
desired location). The appropriate analog input
channel must be selected and the minimum acquisition
period is either timed by the user, or an appropriate
TACQ time selected before the “Special Event Trigger”
sets the GO/DONE bit (starts a conversion).
An A/D conversion can be started by the “Special Event
Trigger” of the ECCP1 module. This requires that the
ECCP1M3:ECCP1M0 bits (ECCP1CON<3:0>) be
programmed as ‘1011’ and that the A/D module is
enabled (ADON bit is set). When the trigger occurs, the
GO/DONE bit will be set, starting the A/D acquisition
and conversion and the Timer1 (or Timer3) counter will
be reset to zero. Timer1 (or Timer3) is reset to automat-
ically repeat the A/D acquisition period with minimal
If the A/D module is not enabled (ADON is cleared), the
“Special Event Trigger” will be ignored by the A/D
module, but will still reset the Timer1 (or Timer3)
counter.
TABLE 19-2: REGISTERS ASSOCIATED WITH A/D OPERATION
Reset
Values
on page
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
INTCON GIE/GIEH PEIE/GIEL TMR0IE
INT0IE
TXIP
TXIF
TXIE
EEIP
EEIF
EEIE
RBIE
SSPIP
SSPIF
SSPIE
BCLIP
BCLIF
BCLIE
TMR0IF
CCP1IP
CCP1IF
CCP1IE
HLVDIP
HLVDIF
HLVDIE
INT0IF
TMR2IP
TMR2IF
TMR2IE
TMR3IP ECCP1IP(1)
TMR3IF ECCP1IF(1)
TMR3IE ECCP1IE(1)
RBIF
49
52
52
52
51
52
52
50
50
50
50
51
52
52
52
52
52
52
52
52
IPR1
PIR1
PIE1
IPR2
PIR2
PIE2
PSPIP(1)
PSPIF(1)
PSPIE(1)
OSCFIP
OSCFIF
OSCFIE
ADIP
ADIF
RCIP
RCIF
RCIE
—
TMR1IP
TMR1IF
TMR1IE
ADIE
CMIP(1)
CMIF(1)
CMIE(1)
—
—
ADRESH A/D Result Register High Byte
ADRESL A/D Result Register Low Byte
ADCON0
ADCON1
ADCON2
PORTA
TRISA
—
—
—
CHS3
VCFG1
ACQT2
RA5
CHS2
VCFG0
ACQT1
RA4
CHS1
PCFG3
ACQT0
RA3
CHS0 GO/DONE
ADON
PCFG0
ADCS0
RA0
—
PCFG2
ADCS2
RA2
PCFG1
ADCS1
RA1
ADFM
RA7(2)
—
RA6(2)
TRISA7(2) TRISA6(2) PORTA Data Direction Register
PORTB
TRISB
RB7
RB6
RB5
RB4
RB3
RB2
RB1
RB0
PORTB Data Direction Register
LATB Data Output Register
LATB
PORTE(4)
TRISE(4)
LATE(4)
—
IBF
—
—
OBF
—
—
IBOV
—
—
PSPMODE
—
RE3(3)
—
RE2(1)
RE1(1)
RE0(1)
TRISE2
TRISE1
TRISE0
—
LATE Data Output Register
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used for A/D conversion.
Note 1: These bits are unimplemented on PIC18F2682/2685 devices; always maintain these bits clear.
2: These pins may be configured as port pins depending on the oscillator mode selected.
3: RE3 port bit is available only as an input pin when the MCLRE Configuration bit is ‘0’.
4: These registers are not implemented on PIC18F2682/2685 devices.
DS39761B-page 256
Preliminary
© 2007 Microchip Technology Inc.
PIC18F2682/2685/4682/4685
The CMCON register (Register 20-1) selects the
comparator input and output configuration. Block
20.0 COMPARATOR MODULE
Note:
Comparators are only available in 40/44-pin
devices (PIC18F4682/4685).
diagrams of the various comparator configurations are
shown in Figure 20-1.
The analog comparator module contains two compara-
tors that can be configured in a variety of ways. The
inputs can be selected from the analog inputs multiplexed
with pins RA0 through RA5, as well as the on-chip volt-
age reference (see Section 21.0 “Comparator Voltage
Reference Module”). The digital outputs (normal or
inverted) are available at the pin level and can also be
read through the control register.
REGISTER 20-1: CMCON: COMPARATOR CONTROL REGISTER
R-0
R-0
R/W-0
C2INV
R/W-0
C1INV
R/W-0
CIS
R/W-0
CM2
R/W-0
CM1
R/W-0
CM0
C2OUT
C1OUT
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7
C2OUT: Comparator 2 Output bit
When C2INV = 0:
1= C2 VIN+ > C2 VIN-
0= C2 VIN+ < C2 VIN-
When C2INV = 1:
1= C2 VIN+ < C2 VIN-
0= C2 VIN+ > C2 VIN-
bit 6
C1OUT: Comparator 1 Output bit
When C1INV = 0:
1= C1 VIN+ > C1 VIN-
0= C1 VIN+ < C1 VIN-
When C1INV = 1:
1= C1 VIN+ < C1 VIN-
0= C1 VIN+ > C1 VIN-
bit 5
bit 4
bit 3
C2INV: Comparator 2 Output Inversion bit
1= C2 output inverted
0= C2 output not inverted
C1INV: Comparator 1 Output Inversion bit
1= C1 output inverted
0= C1 output not inverted
CIS: Comparator Input Switch bit
When CM2:CM0 = 110:
1= C1 VIN- connects to RD0/PSP0/C1IN+
C2 VIN- connects to RD2/PSP2/C2IN+
0= C1 VIN- connects to RD1/PSP1/C1IN-
C2 VIN- connects to RD3/PSP3/C2IN-
bit 2-0
CM2:CM0: Comparator Mode bits
Figure 20-1 shows the Comparator modes and the CM2:CM0 bit settings.
© 2007 Microchip Technology Inc.
Preliminary
DS39761B-page 257
PIC18F2682/2685/4682/4685
changed, the comparator output level may not be valid
for the specified mode change delay shown in
20.1 Comparator Configuration
There are eight modes of operation for the compara-
tors, shown in Figure 20-1. Bits CM2:CM0 of the
CMCON register are used to select these modes. The
TRISA register controls the data direction of the com-
parator pins for each mode. If the Comparator mode is
Section 27.0 “Electrical Characteristics”.
Note: Comparator interrupts should be disabled
during
a
Comparator mode change;
otherwise, a false interrupt may occur.
FIGURE 20-1:
COMPARATOR I/O OPERATING MODES
Comparators Reset (POR Default Value)
CM2:CM0 = 000
Comparators Off
CM2:CM0 = 111
A
A
D
D
VIN-
RD1/PSP1/C1IN-
VIN-
RD1/PSP1/C1IN-
RD0/PSP0/C1IN+
Off
Off
C1
C2
C1
C2
VIN+
VIN+
RD0/PSP0/C1IN+
(Read as ‘0’)
(Read as ‘0’)
A
A
D
D
VIN-
VIN-
RD3/PSP3/C2IN-
RD2/PSP2/C2IN+
RD3/PSP3/C2IN-
RD2/PSP2/C2IN+
Off
Off
VIN+
VIN+
(Read as ‘0’)
(Read as ‘0’)
Two Independent Comparators
CM2:CM0 = 010
Two Independent Comparators with Outputs
CM2:CM0 = 011
A
A
VIN-
A
A
VIN-
RD1/PSP1/C1IN-
RD1/PSP1/C1IN-
RD0/PSP0/C1IN+
C1OUT
C2OUT
C1OUT
C2OUT
C1
C2
C1
C2
VIN+
VIN+
RD0/PSP0/C1IN+
RE1/WR/AN6/C1OUT*
A
A
VIN-
RD3/PSP3/C2IN-
RD2/PSP2/C2IN+
A
VIN-
RD3/PSP3/C2IN-
VIN+
VIN+
A
RD2/PSP2/C2IN+
RE2/CS/AN7/C2OUT*
Two Common Reference Comparators
CM2:CM0 = 100
Two Common Reference Comparators with Outputs
CM2:CM0 = 101
A
A
A
A
VIN-
VIN-
RD1/PSP1/C1IN-
RD0/PSP0/C1IN+
RD1/PSP1/C1IN-
RD0/PSP0/C1IN+
C1OUT
C2OUT
C1OUT
C1
C2
C1
VIN+
VIN+
RE1/WR/AN6/C1OUT*
A
D
VIN-
RD3/PSP3/C2IN-
RD2/PSP2/C2IN+
A
VIN-
RD3/PSP3/C2IN-
VIN+
C2OUT
C2
VIN+
D
RD2/PSP2/C2IN+
RE2/CS/AN7/C2OUT*
Four Inputs Multiplexed to Two Comparators
CM2:CM0 = 110
One Independent Comparator with Output
CM2:CM0 = 001
RD1/PSP1/
A
A
A
VIN-
RD1/PSP1/C1IN-
RD0/PSP0/C1IN+
C1IN-
CIS = 0
CIS = 1
VIN-
C1OUT
C1
C2
RD0/PSP0/
C1IN+
A
VIN+
C1OUT
C1
C2
VIN+
RD3/PSP3/
C2IN-
RD2/PSP2/
C2IN+
RE1/WR/AN6/C1OUT*
A
A
VIN-
CIS = 0
CIS = 1
C2OUT
D
VIN-
VIN+
RD3/PSP3/C2IN-
Off
VIN+
D
RD2/PSP2/C2IN+
(Read as ‘0’)
CVREF
From VREF Module
A = Analog Input, port reads zeros always
D = Digital Input
CIS (CMCON<3>) is the Comparator Input Switch
* Setting the TRISA<5:4> bits will disable the comparator outputs by configuring the pins as inputs.
DS39761B-page 258
Preliminary
© 2007 Microchip Technology Inc.
PIC18F2682/2685/4682/4685
20.3.2
INTERNAL REFERENCE SIGNAL
20.2 Comparator Operation
The comparator module also allows the selection of an
internally generated voltage reference from the
comparator voltage reference module. This module is
described in more detail in Section 21.0 “Comparator
Voltage Reference Module”.
A single comparator is shown in Figure 20-2, along with
the relationship between the analog input levels and
the digital output. When the analog input at VIN+ is less
than the analog input VIN-, the output of the comparator
is a digital low level. When the analog input at VIN+ is
greater than the analog input VIN-, the output of the
comparator is a digital high level. The shaded areas of
the output of the comparator in Figure 20-2 represent
the uncertainty, due to input offsets and response time.
The internal reference is only available in the mode
where four inputs are multiplexed to two comparators
(CM2:CM0 = 110). In this mode, the internal voltage
reference is applied to the VIN+ pin of both
comparators.
20.3 Comparator Reference
20.4 Comparator Response Time
Depending on the comparator operating mode, either
an external or internal voltage reference may be used.
The analog signal present at VIN- is compared to the
signal at VIN+ and the digital output of the comparator
is adjusted accordingly (Figure 20-2).
Response time is the minimum time, after selecting a
new reference voltage or input source, before the
comparator output has a valid level. If the internal
reference is changed, the maximum delay of the
internal voltage reference must be considered when
using the comparator outputs. Otherwise, the
maximum delay of the comparators should be used
(see Section 27.0 “Electrical Characteristics”).
FIGURE 20-2:
SINGLE COMPARATOR
VIN+
VIN-
+
20.5 Comparator Outputs
Output
–
The comparator outputs are read through the CMCON
register. These bits are read-only. The comparator
outputs may also be directly output to the RE1 and RE2
I/O pins. When enabled, multiplexors in the output path
of the RE1 and RE2 pins will switch and the output of
each pin will be the unsynchronized output of the
comparator. The uncertainty of each of the
comparators is related to the input offset voltage and
the response time given in the specifications.
Figure 20-3 shows the comparator output block
diagram.
VIN-
VIN+
Output
The TRISE bits will still function as an output enable/
disable for the RE1 and RE2 pins while in this mode.
The polarity of the comparator outputs can be changed
using the C2INV and C1INV bits (CMCON<5:4>).
20.3.1
EXTERNAL REFERENCE SIGNAL
When external voltage references are used, the
comparator module can be configured to have the com-
parators operate from the same or different reference
sources. However, threshold detector applications may
require the same reference. The reference signal must
be between VSS and VDD and can be applied to either
pin of the comparator(s).
Note 1: When reading the PORT register, all pins
configured as analog inputs will read as a
‘0’. Pins configured as digital inputs will
convert an analog input according to the
Schmitt Trigger input specification.
2: Analog levels on any pin defined as a
digital input may cause the input buffer to
consume more current than is specified.
© 2007 Microchip Technology Inc.
Preliminary
DS39761B-page 259
PIC18F2682/2685/4682/4685
FIGURE 20-3:
COMPARATOR OUTPUT BLOCK DIAGRAM
Port pins
To RE1 or
RE2 pin
D
Q
Bus
Data
CxINV
EN
Read CMCON
D
Q
Set
CMIF
bit
EN
CL
From
other
Comparator
Reset
20.6 Comparator Interrupts
20.7 Comparator Operation
During Sleep
The comparator interrupt flag is set whenever there is
a change in the output value of either comparator.
Software will need to maintain information about the
status of the output bits, as read from CMCON<7:6>, to
determine the actual change that occurred. The CMIF
bit (PIR2<6>) is the Comparator Interrupt Flag. The
CMIF bit must be reset by clearing it. Since it is also
possible to write a ‘1’ to this register, a simulated
interrupt may be initiated.
When a comparator is active and the device is placed
in Sleep mode, the comparator remains active and the
interrupt is functional if enabled. This interrupt will
wake-up the device from Sleep mode, when enabled.
While the comparator is powered up, higher Sleep
currents than shown in the power-down current
specification will occur. Each operational comparator
will consume additional current, as shown in the
comparator specifications. To minimize power
consumption while in Sleep mode, turn off the
comparators (CM2:CM0 = 111) before entering Sleep.
If the device wakes up from Sleep, the contents of the
CMCON register are not affected.
Both the CMIE bit (PIE2<6>) and the PEIE bit
(INTCON<6>) must be set to enable the interrupt. In
addition, the GIE bit (INTCON<7>) must also be set. If
any of these bits are clear, the interrupt is not enabled,
though the CMIF bit will still be set if an interrupt
condition occurs.
20.8 Effects of a Reset
Note:
If a change in the CMCON register
(C1OUT or C2OUT) should occur when a
read operation is being executed (start of
the Q2 cycle), then the CMIF (PIR
registers) interrupt flag may not get set.
A device Reset forces the CMCON register to its Reset
state, causing the comparator module to be in the Com-
parator Reset mode (CM2:CM0 = 000). This ensures
that all potential inputs are analog inputs. Device
current is minimized when analog inputs are present at
Reset time. The comparators are powered down during
the Reset interval.
The user, in the Interrupt Service Routine, can clear the
interrupt in the following manner:
a) Any read or write of CMCON will end the
mismatch condition.
b) Clear flag bit CMIF.
A mismatch condition will continue to set flag bit CMIF.
Reading CMCON will end the mismatch condition and
allow flag bit CMIF to be cleared.
DS39761B-page 260
Preliminary
© 2007 Microchip Technology Inc.
PIC18F2682/2685/4682/4685
range by more than 0.6V in either direction, one of the
diodes is forward biased and a latch-up condition may
occur. A maximum source impedance of 10 kΩ is
recommended for the analog sources. Any external
component connected to an analog input pin, such as
a capacitor or a Zener diode, should have very little
leakage current.
20.9 Analog Input Connection
Considerations
A simplified circuit for an analog input is shown in
Figure 20-4. Since the analog pins are connected to a
digital output, they have reverse biased diodes to VDD
and VSS. The analog input, therefore, must be between
VSS and VDD. If the input voltage deviates from this
FIGURE 20-4:
COMPARATOR ANALOG INPUT MODEL
VDD
VT = 0.6V
RIC
RS < 10k
AIN
Comparator
Input
ILEAKAGE
500 nA
CPIN
5 pF
VA
VT = 0.6V
VSS
Legend: CPIN
=
=
Input Capacitance
Threshold Voltage
VT
ILEAKAGE = Leakage Current at the pin due to various junctions
RIC
RS
VA
=
=
=
Interconnect Resistance
Source Impedance
Analog Voltage
TABLE 20-1: REGISTERS ASSOCIATED WITH COMPARATOR MODULE
Reset
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Values
on page
CMCON(3)
CVRCON(3) CVREN
C2OUT
C1OUT
CVROE
C2INV
CVRR
C1INV
CIS
CM2
CVR2
CM1
CVR1
INT0IF
CM0
CVR0
RBIF
51
51
52
51
52
52
52
52
52
CVRSS
CVR3
RBIE
BCLIP
BCLIF
BCLIE
RA3
INTCON
IPR2
GIE/GIEH PEIE/GIEL TMR0IE INT0IE
TMR0IF
OSCFIP
OSCFIF
OSCFIE
RA7(1)
CMIP(2)
CMIF(2)
CMIE(2)
RA6(1)
—
—
EEIP
EEIF
EEIE
RA4
HLVDIP TMR3IP ECCP1IP(2)
HLVDIF TMR3IF ECCP1IF(2)
HLVDIE TMR3IE ECCP1IE(2)
PIR2
PIE2
—
PORTA
LATA
RA5
RA2
RA1
RA0
LATA7(1)
LATA6(1) LATA Data Output Register
TRISA
TRISA7(1) TRISA6(1) PORTA Data Direction Register
Legend: — = unimplemented, read as ‘0’. Shaded cells are unused by the comparator module.
Note 1: PORTA pins are enabled based on oscillator configuration.
2: These bits are available in PIC18F4682/4685 devices and reserved in PIC18F2682/2685 devices.
3: These registers are unimplemented on PIC18F2682/2685 devices.
© 2007 Microchip Technology Inc.
Preliminary
DS39761B-page 261
PIC18F2682/2685/4682/4685
NOTES:
DS39761B-page 262
Preliminary
© 2007 Microchip Technology Inc.
PIC18F2682/2685/4682/4685
voltage, each with 16 distinct levels. The range to be
used is selected by the CVRR bit (CVRCON<5>). The
primary difference between the ranges is the size of the
steps selected by the CVREF selection bits
(CVR3:CVR0), with one range offering finer resolution.
The equations used to calculate the output of the
comparator voltage reference are as follows:
21.0 COMPARATOR VOLTAGE
REFERENCE MODULE
Note:
Comparators are only available in 40/44-pin
devices (PIC18F4682/4685).
The comparator voltage reference is a 16-tap resistor
ladder network that provides a selectable reference
voltage. Although its primary purpose is to provide a
reference for the analog comparators, it may also be
used independently of them.
If CVRR = 1:
CVREF = ((CVR3:CVR0)/24) x CVRSRC
If CVRR = 0:
CVREF = (CVDD x 1/4) + (((CVR3:CVR0)/32) x
CVRSRC)
A block diagram is of the module shown in Figure 21-1.
The resistor ladder is segmented to provide two ranges
of CVREF values and has a power-down function to
conserve power when the reference is not being used.
The module’s supply reference can be provided from
either device VDD/VSS or an external voltage reference.
The comparator reference supply voltage can come
from either VDD and VSS, or the external VREF+ and
VREF- that are multiplexed with RA2 and RA3. The
voltage source is selected by the CVRSS bit
(CVRCON<4>).
The settling time of the comparator voltage reference
must be considered when changing the CVREF output
(see Table 27-3 in Section 27.0 “Electrical
Characteristics”).
21.1 Configuring the Comparator
Voltage Reference
The voltage reference module is controlled through the
CVRCON register (Register 21-1). The comparator
voltage reference provides two ranges of output
REGISTER 21-1: CVRCON: COMPARATOR VOLTAGE REFERENCE CONTROL REGISTER
R/W-0
R/W-0
CVROE(1)
R/W-0
CVRR
R/W-0
R/W-0
CVR3
R/W-0
CVR2
R/W-0
CVR1
R/W-0
CVR0
CVREN
CVRSS
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
-n = Value at POR
bit 7
bit 6
bit 5
bit 4
bit 3-0
CVREN: Comparator Voltage Reference Enable bit
1= CVREF circuit powered on
0= CVREF circuit powered down
CVROE: Comparator VREF Output Enable bit(1)
1= CVREF voltage level is also output on the RA0/AN0/CVREF pin
0= CVREF voltage is disconnected from the RA0/AN0/CVREF pin
CVRR: Comparator VREF Range Selection bit
1= 0.00 CVRSRC to 0.75 CVRSRC, with CVRSRC/24 step size
0= 0.25 CVRSRC to 0.75 CVRSRC, with CVRSRC/32 step size
CVRSS: Comparator VREF Source Selection bit
1= Comparator reference source, CVRSRC = (VREF+) – (VREF-)
0= Comparator reference source, CVRSRC = VDD – VSS
CVR3:CVR0: Comparator VREF Value Selection bits (0 ≤ (CVR3:CVR0) ≤ 15)
When CVRR = 1:
CVREF = ((CVR3:CVR0)/24) • (CVRSRC)
When CVRR = 0:
CVREF = (CVRSRC/4) + ((CVR3:CVR0)/32) • (CVRSRC)
Note 1: CVROE overrides the TRISA<0> bit setting. If enabled for output, RA2 must also be configured as an
input by setting TRISA<2> to ‘1’.
© 2007 Microchip Technology Inc.
Preliminary
DS39761B-page 263
PIC18F2682/2685/4682/4685
FIGURE 21-1:
COMPARATOR VOLTAGE REFERENCE BLOCK DIAGRAM
CVRSS = 1
CVRSS = 0
VREF+
VDD
8R
CVR3:CVR0
R
CVREN
R
R
R
16 Steps
CVREF
R
R
R
CVRR
VREF-
8R
CVRSS = 1
CVRSS = 0
21.2 Voltage Reference Accuracy/Error
21.4 Effects of a Reset
The full range of voltage reference cannot be realized
due to the construction of the module. The transistors
on the top and bottom of the resistor ladder network
(Figure 21-1) keep CVREF from approaching the
reference source rails. The voltage reference is derived
from the reference source; therefore, the CVREF output
changes with fluctuations in that source. The tested
absolute accuracy of the voltage reference can be
found in Section 27.0 “Electrical Characteristics”.
A device Reset disables the voltage reference by
clearing bit CVREN (CVRCON<7>). This Reset also
disconnects the reference from the RA0 pin by clearing
bit, CVROE (CVRCON<6>), and selects the high-
voltage range by clearing bit, CVRR (CVRCON<5>).
The CVR value select bits are also cleared.
21.5 Connection Considerations
The voltage reference module operates independently
of the comparator module. The output of the reference
generator may be connected to the RA0 pin if the
TRISA<0> bit and the CVROE bit are both set. Enabling
the voltage reference output onto the RA0 pin, with an
input signal present, will increase current consumption.
Connecting RA0 as a digital output with CVRSS enabled
will also increase current consumption.
21.3 Operation During Sleep
When the device wakes up from Sleep through an
interrupt or a Watchdog Timer time-out, the contents of
the CVRCON register are not affected. To minimize
current consumption in Sleep mode, the voltage
reference should be disabled.
The RA0 pin can be used as a simple D/A output with
limited drive capability. Due to the limited current drive
capability, a buffer must be used on the voltage
reference output for external connections to VREF.
Figure 21-2 shows an example buffering technique.
DS39761B-page 264
Preliminary
© 2007 Microchip Technology Inc.
PIC18F2682/2685/4682/4685
FIGURE 21-2:
COMPARATOR VOLTAGE REFERENCE OUTPUT BUFFER EXAMPLE
PIC18F4682/4685
(1)
R
CVREF
+
Module
CVREF Output
RA0
Voltage
Reference
Output
–
Impedance
Note 1: R is dependent upon the voltage reference configuration bits, CVRCON<3:0> and CVRCON<5>.
TABLE 21-1: REGISTERS ASSOCIATED WITH COMPARATOR VOLTAGE REFERENCE
Reset
Values
on page
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
CVRCON(2)
CMCON(2)
TRISA
CVREN
C2OUT
CVROE
C1OUT
CVRR
C2INV
CVRSS
C1INV
CVR3
CIS
CVR2
CM2
CVR1
CM1
CVR0
CM0
51
51
52
TRISA7(1) TRISA6(1) PORTA Data Direction Register
Legend: Shaded cells are not used with the comparator voltage reference.
Note 1: PORTA pins are enabled based on oscillator configuration.
2: These registers are unimplemented on PIC18F2682/2685 devices.
© 2007 Microchip Technology Inc.
Preliminary
DS39761B-page 265
PIC18F2682/2685/4682/4685
NOTES:
DS39761B-page 266
Preliminary
© 2007 Microchip Technology Inc.
PIC18F2682/2685/4682/4685
The High/Low-Voltage Detect Control register
(Register 22-1) completely controls the operation of the
HLVD module. This allows the circuitry to be “turned
22.0 HIGH/LOW-VOLTAGE
DETECT (HLVD)
off” by the user under software control, which
minimizes the current consumption for the device.
PIC18F2682/2685/4682/4685 devices have a High/
Low-Voltage Detect module (HLVD). This is
a
programmable circuit that allows the user to specify
both a device voltage trip point and the direction of
change from that point. If the device experiences an
excursion past the trip point in that direction, an
interrupt flag is set. If the interrupt is enabled, the
program execution will branch to the interrupt vector
address and the software can then respond to the
interrupt.
The block diagram for the HLVD module is shown in
Figure 22-1.
REGISTER 22-1: HLVDCON: HIGH/LOW-VOLTAGE DETECT CONTROL REGISTER
R/W-0
U-0
—
R-0
R/W-0
R/W-0
HLVDL3(1)
R/W-1
HLVDL2(1)
R/W-0
HLVDL1(1)
R/W-1
HLVDL0(1)
VDIRMAG
IRVST
HLVDEN
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7
VDIRMAG: Voltage Direction Magnitude Select bit
1= Event occurs when voltage equals or exceeds trip point (HLVDL3:HLDVL0)
0= Event occurs when voltage equals or falls below trip point (HLVDL3:HLVDL0)
bit 6
bit 5
Unimplemented: Read as ‘0’
IRVST: Internal Reference Voltage Stable Flag bit
1= Indicates that the voltage detect logic will generate the interrupt flag at the specified voltage range
0= Indicates that the voltage detect logic will not generate the interrupt flag at the specified voltage
range and the HLVD interrupt should not be enabled
bit 4
HLVDEN: High/Low-Voltage Detect Power Enable bit
1= HLVD enabled
0= HLVD disabled
bit 3-0
HLVDL3:HLVDL0: High/Low-Voltage Detection Limit bits(1)
1111= External analog input is used (input comes from the HLVDIN pin)
1110= 4.48V-4.69V
1101= 4.23V-4.43V
1100= 4.01V-4.20V
1011= 3.81V-3.99V
1010= 3.63V-3.80V
1001= 3.46V-3.63V
1000= 3.31V-3.47V
0111= 3.05V-3.19V
0110= 2.82V-2.95V
0101= 2.72V-2.85V
0100= 2.54V-2.66V
0011= 2.38V-2.49V
0010= 2.31V-2.42V
0001= 2.18V-2.28V
0000= 2.12V-2.22V
Note 1: HLVDL3:HLVDL0 modes that result in a trip point below the valid operating voltage of the device are not tested.
© 2007 Microchip Technology Inc.
Preliminary
DS39761B-page 267
PIC18F2682/2685/4682/4685
The module is enabled by setting the HLVDEN bit.
Each time that the HLVD module is enabled, the
circuitry requires some time to stabilize. The IRVST bit
is a read-only bit and is used to indicate when the circuit
is stable. The module can only generate an interrupt
after the circuit is stable and IRVST is set.
event, depending on the configuration of the module.
When the supply voltage is equal to the trip point, the
voltage tapped off of the resistor array is equal to the
internal reference voltage generated by the voltage
reference module. The comparator then generates an
interrupt signal by setting the HLVDIF bit.
The VDIRMAG bit determines the overall operation of
the module. When VDIRMAG is cleared, the module
monitors for drops in VDD below a predetermined set
point. When the bit is set, the module monitors for rises
in VDD above the set point.
The trip point voltage is software programmable to any
one of sixteen values. The trip point is selected
by programming
(HLVDCON<3:0>).
the
HLVDL3:HLVDL0
bits
The HLVD module has an additional feature that allows
the user to supply the trip voltage to the module from an
external source. This mode is enabled when bits
HLVDL3:HLVDL0 are set to ‘1111’. In this state, the
comparator input is multiplexed from the external input
pin, HLVDIN. This gives users flexibility because it
allows them to configure the High/Low-Voltage Detect
interrupt to occur at any voltage in the valid operating
range.
22.1 Operation
When the HLVD module is enabled, a comparator uses
an internally generated reference voltage as the set
point. The set point is compared with the trip point,
where each node in the resistor divider represents a
trip point voltage. The “trip point” voltage is the voltage
level at which the device detects a high or low-voltage
FIGURE 22-1:
HLVD MODULE BLOCK DIAGRAM (WITH EXTERNAL INPUT)
Externally Generated
Trip Point
VDD
VDD
HLVDL3:HLVDL0
HLVDCON
Register
HLVDIN
VDIRMAG
HLVDEN
HLVDIN
Set HLVDIF
HLVDEN
BOREN
Internal Voltage
Reference
DS39761B-page 268
Preliminary
© 2007 Microchip Technology Inc.
PIC18F2682/2685/4682/4685
Depending on the application, the HLVD module does
not need to be operating constantly. To decrease the
current requirements, the HLVD circuitry may only
need to be enabled for short periods where the voltage
is checked. After doing the check, the HLVD module
may be disabled.
22.2 HLVD Setup
The following steps are needed to set up the HLVD
module:
1. Disable the module by clearing the HLVDEN bit
(HLVDCON<4>).
2. Write the value to the HLVDL3:HLVDL0 bits that
select the desired HLVD trip point.
22.4 HLVD Start-up Time
3. Set the VDIRMAG bit to detect high voltage
The internal reference voltage of the HLVD module,
specified in electrical specification parameter D420,
may be used by other internal circuitry, such as the
Programmable Brown-out Reset. If the HLVD or other
circuits using the voltage reference are disabled to
lower the device’s current consumption, the reference
voltage circuit will require time to become stable before
a low or high-voltage condition can be reliably
detected. This start-up time, TIRVST, is an interval that
is independent of device clock speed. It is specified in
electrical specification parameter 36.
(VDIRMAG = 1) or low voltage (VDIRMAG = 0).
4. Enable the HLVD module by setting the
HLVDEN bit.
5. Clear the HLVD interrupt flag (PIR2<2>), which
may have been set from a previous interrupt.
6. Enable the HLVD interrupt if interrupts are
desired by setting the HLVDIE and GIE bits
(PIE<2> and INTCON<7>). An interrupt will not
be generated until the IRVST bit is set.
The HLVD interrupt flag is not enabled until TIRVST has
expired and a stable reference voltage is reached. For
this reason, brief excursions beyond the set point may
not be detected during this interval. Refer to Figure 22-2
or Figure 22-3.
22.3 Current Consumption
When the module is enabled, the HLVD comparator
and voltage divider are enabled and will consume static
current. The total current consumption, when enabled,
is specified in electrical specification parameter D022B.
FIGURE 22-2:
LOW-VOLTAGE DETECT OPERATION (VDIRMAG = 0)
CASE 1:
HLVDIF may not be set
VDD
VLVD
HLVDIF
Enable HLVD
IRVST
TIRVST
HLVDIF cleared in software
Internal Reference is stable
CASE 2:
VDD
VLVD
HLVDIF
Enable HLVD
TIRVST
IRVST
Internal Reference is stable
HLVDIF cleared in software
HLVDIF cleared in software,
HLVDIF remains set since HLVD condition still exists
© 2007 Microchip Technology Inc.
Preliminary
DS39761B-page 269
PIC18F2682/2685/4682/4685
FIGURE 22-3:
HIGH-VOLTAGE DETECT OPERATION (VDIRMAG = 1)
CASE 1:
HLVDIF may not be set
VLVD
VDD
HLVDIF
Enable HLVD
IRVST
TIRVST
HLVDIF cleared in software
Internal Reference is stable
CASE 2:
VLVD
VDD
HLVDIF
Enable HLVD
TIRVST
IRVST
Internal Reference is stable
HLVDIF cleared in software
HLVDIF cleared in software,
HLVDIF remains set since HLVD condition still exists
FIGURE 22-4:
TYPICAL LOW-VOLTAGE
DETECT APPLICATION
22.5 Applications
In many applications, the ability to detect a drop below,
or rise above a particular threshold is desirable. For
example, the HLVD module could be periodically
enabled to detect Universal Serial Bus (USB) attach or
detach. This assumes the device is powered by a lower
voltage source than the USB when detached. An attach
would indicate a high-voltage detect from, for example,
3.3V to 5V (the voltage on USB) and vice versa for a
detach. This feature could save a design a few extra
components and an attach signal (input pin).
VA
VB
For general battery applications, Figure 22-4 shows a
possible voltage curve. Over time, the device voltage
decreases. When the device voltage reaches voltage
VA, the HLVD logic generates an interrupt at time TA.
The interrupt could cause the execution of an ISR,
which would allow the application to perform “house-
keeping tasks” and perform a controlled shutdown
before the device voltage exits the valid operating
range at TB. The HLVD, thus, would give the
TB
TA
Time
Legend:
VA = HLVD trip point
VB = Minimum valid device
operating voltage
application
a time window, represented by the
difference between TA and TB, to safely exit.
DS39761B-page 270
Preliminary
© 2007 Microchip Technology Inc.
PIC18F2682/2685/4682/4685
22.6 Operation During Sleep
22.7 Effects of a Reset
When enabled, the HLVD circuitry continues to operate
during Sleep. If the device voltage crosses the trip
point, the HLVDIF bit will be set and the device will
wake-up from Sleep. Device execution will continue
from the interrupt vector address if interrupts have
been globally enabled.
A device Reset forces all registers to their Reset state.
This forces the HLVD module to be turned off.
TABLE 22-1: REGISTERS ASSOCIATED WITH HIGH/LOW-VOLTAGE DETECT MODULE
Reset
Values
on Page
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
HLVDCON VDIRMAG
—
IRVST
HLVDEN HLVDL3 HLVDL2 HLVDL1
HLVDL0
RBIF
50
49
52
52
51
INTCON
PIR2
GIE/GIEH PEIE/GIEL TMR0IE
INT0IE
EEIF
RBIE
BCLIF
BCLIE
BCLIP
TMR0IF
INT0IF
OSCFIF
OSCFIE
OSCFIP
CMIF(1)
CMIE(1)
CMIP(1)
—
—
—
HLVDIF TMR3IF ECCP1IF(1)
HLVDIE TMR3IE ECCP1IE(1)
HLVDIP TMR3IP ECCP1IP(1)
PIE2
EEIE
EEIP
IPR2
Legend: — = unimplemented, read as ‘0’. Shaded cells are unused by the HLVD module.
Note 1: These bits are available in PIC18F4682/4685 devices and reserved in PIC18F2682/2685 devices.
© 2007 Microchip Technology Inc.
Preliminary
DS39761B-page 271
PIC18F2682/2685/4682/4685
NOTES:
DS39761B-page 272
Preliminary
© 2007 Microchip Technology Inc.
PIC18F2682/2685/4682/4685
23.1 Module Overview
23.0 ECAN™ TECHNOLOGY
The CAN bus module consists of a protocol engine and
message buffering and control. The CAN protocol
engine automatically handles all functions for receiving
and transmitting messages on the CAN bus. Messages
are transmitted by first loading the appropriate data
registers. Status and errors can be checked by reading
the appropriate registers. Any message detected on
the CAN bus is checked for errors and then matched
against filters to see if it should be received and stored
in one of the two receive registers.
PIC18F2682/2685/4682/4685 devices contain an
Enhanced Controller Area Network (ECAN) module.
The ECAN module is fully backward compatible with
the CAN module available in PIC18CXX8 and
PIC18FXX8 devices.
The Controller Area Network (CAN) module is a serial
interface which is useful for communicating with other
peripherals or microcontroller devices. This interface,
or protocol, was designed to allow communications
within noisy environments.
The CAN module supports the following frame types:
The ECAN module is a communication controller, imple-
menting the CAN 2.0A or B protocol as defined in the
BOSCH specification. The module will support CAN 1.2,
CAN 2.0A, CAN 2.0B Passive and CAN 2.0B Active
versions of the protocol. The module implementation is
a full CAN system; however, the CAN specification is not
covered within this data sheet. Refer to the BOSCH CAN
specification for further details.
• Standard Data Frame
• Extended Data Frame
• Remote Frame
• Error Frame
• Overload Frame Reception
• Interframe Space Generation/Detection
The CAN module uses the RB2/CANTX and RB3/
CANRX pins to interface with the CAN bus. In normal
mode, the CAN module automatically overrides
TRISB<2>. The user must ensure that TRISB<3> is
set.
The module features are as follows:
• Implementation of the CAN protocol CAN 1.2,
CAN 2.0A and CAN 2.0B
• DeviceNetTM data bytes filter support
• Standard and extended data frames
• 0-8 bytes data length
23.1.1
MODULE FUNCTIONALITY
• Programmable bit rate up to 1 Mbit/sec
• Fully backward compatible with PIC18XXX8 CAN
module
• Three modes of operation:
- Mode 0 – Legacy mode
The CAN bus module consists of a protocol engine,
message buffering and control (see Figure 23-1). The
protocol engine can best be understood by defining the
types of data frames to be transmitted and received by
the module.
- Mode 1 – Enhanced Legacy mode with
DeviceNet support
The following sequence illustrates the necessary initial-
ization steps before the ECAN module can be used to
transmit or receive a message. Steps can be added or
removed depending on the requirements of the
application.
- Mode 2 – FIFO mode with DeviceNet support
• Support for remote frames with automated handling
• Double-buffered receiver with two prioritized
received message storage buffers
• Six buffers programmable as RX and TX
message buffers
• 16 full (standard/extended identifier) acceptance
filters that can be linked to one of four masks
• Two full acceptance filter masks that can be
assigned to any filter
• One full acceptance filter that can be used as either
an acceptance filter or acceptance filter mask
• Three dedicated transmit buffers with application
specified prioritization and abort capability
• Programmable wake-up functionality with
integrated low-pass filter
1. Ensure that the ECAN module is in Configuration
mode.
2. Select ECAN operational mode.
3. Set up the baud rate registers.
4. Set up the filter and mask registers.
5. Set the ECAN module to normal mode or any
other mode required by the application logic.
• Programmable Loopback mode supports self-test
operation
• Signaling via interrupt capabilities for all CAN
receiver and transmitter error states
• Programmable clock source
• Programmable link to timer module for
time-stamping and network synchronization
• Low-power Sleep mode
© 2007 Microchip Technology Inc.
Preliminary
DS39761B-page 273
PIC18F2682/2685/4682/4685
FIGURE 23-1:
CAN BUFFERS AND PROTOCOL ENGINE BLOCK DIAGRAM
16 – 4 to 1 MUXs
BUFFERS
Acceptance Filters
(RXF0-RXF05)
TXB0
TXB1
TXB2
VCC
A
c
c
e
p
t
MODE 0
RXF15
Acceptance Filters
(RXF06-RXF15)
MODE 1, 2
MODE 0
2 RX
Buffers
Message
Queue
Control
Identifier
M
A
B
Transmit Byte Sequencer
Data Field
Rcv Byte
MODE 1, 2
6 TX/RX
Buffers
Transmit Option
MESSAGE
BUFFERS
PROTOCOL
ENGINE
Receive
REC
TEC
Error
Counter
Transmit
Error
Counter
Err-Pas
Bus-Off
Transmit<7:0>
Shift<14:0>
Receive<8:0>
{Transmit<5:0>, Receive<8:0>}
Comparator
Protocol
Finite
State
Machine
CRC<14:0>
Bit
Timing
Logic
Transmit
Logic
Clock
Generator
Configuration
Registers
TX
RX
DS39761B-page 274
Preliminary
© 2007 Microchip Technology Inc.
PIC18F2682/2685/4682/4685
23.2.1
CAN CONTROL AND STATUS
REGISTERS
23.2 CAN Module Registers
Note:
Not all CAN registers are available in the
Access Bank.
The registers described in this section control the
overall operation of the CAN module and show its
operational status.
There are many control and data registers associated
with the CAN module. For convenience, their
descriptions have been grouped into the following
sections:
• Control and Status Registers
• Dedicated Transmit Buffer Registers
• Dedicated Receive Buffer Registers
• Programmable TX/RX and Auto RTR Buffers
• Baud Rate Control Registers
• I/O Control Register
• Interrupt Status and Control Registers
Detailed descriptions of each register and their usage
are described in the following sections.
© 2007 Microchip Technology Inc.
Preliminary
DS39761B-page 275
PIC18F2682/2685/4682/4685
REGISTER 23-1: CANCON: CAN CONTROL REGISTER
R/W-1
R/W-0
R/W-0
R/S-0
ABAT
R/W-0
WIN2
R/W-0
WIN1
R/W-0
WIN0
U-0
—
Mode 0
Mode 1
Mode 2
REQOP2
REQOP1
REQOP0
R/W-1
R/W-0
R/W-0
R/S-0
ABAT
U0
—
U-0
—
U-0
—
U-0
—
REQOP2
REQOP1
REQOP0
R/W-1
R/W-0
R/W-0
R/S-0
ABAT
R-0
R-0
R-0
R-0
REQOP2
REQOP1
REQOP0
FP3
FP2
FP1
FP0
bit 7
bit 0
Legend:
S = Settable bit
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7-5
REQOP2:REQOP0: Request CAN Operation Mode bits
1xx= Request Configuration mode
011= Request Listen Only mode
010= Request Loopback mode
001= Request Disable mode
000= Request Normal mode
bit 4
ABAT: Abort All Pending Transmissions bit
1= Abort all pending transmissions (in all transmit buffers)
0= Transmissions proceeding as normal
bit 3-1
Mode 0:
WIN2:WIN0: Window Address bits
These bits select which of the CAN buffers to switch into the access bank area. This allows access to the
buffer registers from any data memory bank. After a frame has caused an interrupt, the ICODE3:ICODE0
bits can be copied to the WIN3:WIN0 bits to select the correct buffer. See Example 23-2 for a code
example.
111= Receive Buffer 0
110= Receive Buffer 0
101= Receive Buffer 1
100= Transmit Buffer 0
011= Transmit Buffer 1
010= Transmit Buffer 2
001= Receive Buffer 0
000= Receive Buffer 0
bit 0
Unimplemented: Read as ‘0’
bit 4-0
Mode 1:
Unimplemented: Read as ‘0’
Mode 2:
FP3:FP0: FIFO Read Pointer bits
These bits point to the message buffer to be read.
0111:0000= Message buffer to be read
1111:1000= Reserved
DS39761B-page 276
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REGISTER 23-2: CANSTAT: CAN STATUS REGISTER
R-1
R-0
R-0
R-0
—
R-0
R-0
R-0
U-0
—
Mode 0
(1)
(1)
(1)
OPMODE2
OPMODE1
OPMODE0
ICODE3
ICODE2
ICODE1
R-1
R-0
R-0
R-0
R-0
R-0
R-0
R-0
Mode 1,2
(1)
(1)
(1)
OPMODE2
bit 7
OPMODE1
OPMODE0
EICODE4 EICODE3 EICODE2 EICODE1
EICODE0
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7-5
OPMODE2:OPMODE0: Operation Mode Status bits(1)
111= Reserved
110= Reserved
101= Reserved
100= Configuration mode
011= Listen Only mode
010= Loopback mode
001= Disable/Sleep mode
000= Normal mode
bit 4
Mode 0:
Unimplemented: Read as ‘0’
bit 3-1
ICODE3:ICODE1: Interrupt Code bits
When an interrupt occurs, a prioritized coded interrupt value will be present in these bits. This code
indicates the source of the interrupt. By copying ICODE3:ICODE1 to WIN2:WIN0 (Mode 0) or
EICODE4:EICODE0 to EWIN4:EWIN0 (Mode 1 and 2), it is possible to select the correct buffer to map into
the Access Bank area. See Example 23-2 for a code example. To simplify the description, the following
table lists all five bits.
Mode 0
00000
00010
00100
00110
01000
01010
01100
00010
-----
-----
-----
-----
-----
-----
-----
-----
Mode 1
00000
00010
00100
00110
01000
10001
10000
01110
10000
10001
10010
10011
10100
10101
10110
10111
Mode 2
00000
No interrupt
Error interrupt
TXB2 interrupt
TXB1 interrupt
00010
00100
00110
TXB0 interrupt
01000
RXB1 interrupt
RXB0 interrupt
Wake-up interrupt
RXB0 interrupt
RXB1 interrupt
RX/TX B0 interrupt
RX/TX B1 interrupt
RX/TX B2 interrupt
RX/TX B3 interrupt
RX/TX B4 interrupt
RX/TX B5 interrupt
-----
10000
01110
10000
10000
10010
10011(2)
10100(2)
10101(2)
10110(2)
10111(2)
bit 0
Unimplemented: Read as ‘0’
bit 4-0
Mode 1, 2:
EICODE4:EICODE0: Interrupt Code bits
See ICODE3:ICODE1 above.
Note 1: To achieve maximum power saving and/or able to wake-up on CAN bus activity, switch CAN module in
Disable mode before putting device to Sleep.
2: If buffer is configured as receiver, EICODE bits will contain ‘10000’ upon interrupt.
© 2007 Microchip Technology Inc.
Preliminary
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EXAMPLE 23-1:
CHANGING TO CONFIGURATION MODE
; Request Configuration mode.
MOVLW
MOVWF
B’10000000’
CANCON
; Set to Configuration Mode.
; A request to switch to Configuration mode may not be immediately honored.
; Module will wait for CAN bus to be idle before switching to Configuration Mode.
; Request for other modes such as Loopback, Disable etc. may be honored immediately.
; It is always good practice to wait and verify before continuing.
ConfigWait:
MOVF
ANDLW
CANSTAT, W
B’10000000’
; Read current mode state.
; Interested in OPMODE bits only.
; Is it Configuration mode yet?
; No. Continue to wait...
TSTFSZ WREG
BRA
ConfigWait
; Module is in Configuration mode now.
; Modify configuration registers as required.
; Switch back to Normal mode to be able to communicate.
EXAMPLE 23-2:
WIN AND ICODE BITS USAGE IN INTERRUPT SERVICE ROUTINE TO ACCESS
TX/RX BUFFERS
; Save application required context.
; Poll interrupt flags and determine source of interrupt
; This was found to be CAN interrupt
; TempCANCON and TempCANSTAT are variables defined in Access Bank low
MOVFF
CANCON, TempCANCON
; Save CANCON.WIN bits
; This is required to prevent CANCON
; from corrupting CAN buffer access
; in-progress while this interrupt
; occurred
MOVFF
CANSTAT, TempCANSTAT
; Save CANSTAT register
; This is required to make sure that
; we use same CANSTAT value rather
; than one changed by another CAN
; interrupt.
MOVF
ANDLW
ADDWF
TempCANSTAT, W
B’00001110’
PCL, F
; Retrieve ICODE bits
; Perform computed GOTO
; to corresponding interrupt cause
; 000 = No interrupt
; 001 = Error interrupt
; 010 = TXB2 interrupt
; 011 = TXB1 interrupt
; 100 = TXB0 interrupt
; 101 = RXB1 interrupt
; 110 = RXB0 interrupt
; 111 = Wake-up on interrupt
BRA
BRA
BRA
BRA
BRA
BRA
BRA
NoInterrupt
ErrorInterrupt
TXB2Interrupt
TXB1Interrupt
TXB0Interrupt
RXB1Interrupt
RXB0Interrupt
WakeupInterrupt
BCF
PIR3, WAKIF
; Clear the interrupt flag
;
; User code to handle wake-up procedure
;
;
; Continue checking for other interrupt source or return from here
…
NoInterrupt
…
; PC should never vector here. User may
; place a trap such as infinite loop or pin/port
; indication to catch this error.
DS39761B-page 278
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© 2007 Microchip Technology Inc.
PIC18F2682/2685/4682/4685
EXAMPLE 23-2:
WIN AND ICODE BITS USAGE IN INTERRUPT SERVICE ROUTINE TO ACCESS
TX/RX BUFFERS (CONTINUED)
ErrorInterrupt
BCF
…
PIR3, ERRIF
; Clear the interrupt flag
; Handle error.
RETFIE
TXB2Interrupt
BCF
GOTO
TXB1Interrupt
BCF
GOTO
TXB0Interrupt
BCF
GOTO
RXB1Interrupt
PIR3, TXB2IF
AccessBuffer
; Clear the interrupt flag
; Clear the interrupt flag
; Clear the interrupt flag
; Clear the interrupt flag
PIR3, TXB1IF
AccessBuffer
PIR3, TXB0IF
AccessBuffer
BCF
GOTO
PIR3, RXB1IF
Accessbuffer
RXB0Interrupt
BCF
GOTO
PIR3, RXB0IF
AccessBuffer
; Clear the interrupt flag
AccessBuffer
; This is either TX or RX interrupt
; Copy CANSTAT.ICODE bits to CANCON.WIN bits
MOVF
TempCANCON, W
; Clear CANCON.WIN bits before copying
; new ones.
ANDLW
B’11110001’
; Use previously saved CANCON value to
; make sure same value.
MOVWF
MOVF
ANDLW
TempCANCON
TempCANSTAT, W
B’00001110’
; Copy masked value back to TempCANCON
; Retrieve ICODE bits
; Use previously saved CANSTAT value
; to make sure same value.
IORWF
MOVFF
TempCANCON
TempCANCON, CANCON
; Copy ICODE bits to WIN bits.
; Copy the result to actual CANCON
; Access current buffer…
; User code
; Restore CANCON.WIN bits
MOVF
ANDLW
IORWF
CANCON, W
B’11110001’
TempCANCON
; Preserve current non WIN bits
; Restore original WIN bits
; Do not need to restore CANSTAT - it is read-only register.
; Return from interrupt or check for another module interrupt source
© 2007 Microchip Technology Inc.
Preliminary
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REGISTER 23-3: ECANCON: ENHANCED CAN CONTROL REGISTER
R/W-0
MDSEL1(1)
R/W-0
MDSEL0(1)
R/W-0
FIFOWM(2)
R/W-1
R/W-0
R/W-0
R/W-0
R/W-0
EWIN4
EWIN3
EWIN2
EWIN1
EWIN0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
-n = Value at POR
bit 7-6
MDSEL1:MDSEL0: Mode Select bits(1)
00= Legacy mode (Mode 0, default)
01= Enhanced Legacy mode (Mode 1)
10= Enhanced FIFO mode (Mode 2)
11= Reserved
bit 5
FIFOWM: FIFO High Water Mark bit(2)
1= Will cause FIFO interrupt when one receive buffer remains(3)
0= Will cause FIFO interrupt when four receive buffers remain
bit 4-0
EWIN4:EWIN0: Enhanced Window Address bits
These bits map the group of 16 banked CAN SFRs into access bank addresses 0F60-0F6Dh. Exact
group of registers to map is determined by binary value of these bits.
Mode 0:
Unimplemented: Read as ‘0’
Mode 1, 2:
00000= Acceptance Filters 0, 1, 2 and BRGCON2, 3
00001= Acceptance Filters 3, 4, 5 and BRGCON1, CIOCON
00010= Acceptance Filter Masks, Error and Interrupt Control
00011= Transmit Buffer 0
00100= Transmit Buffer 1
00101= Transmit Buffer 2
00110= Acceptance Filters 6, 7, 8
00111= Acceptance Filters 9, 10, 11
01000= Acceptance Filters 12, 13, 14
01001= Acceptance Filters 15
01010-01110= Reserved
01111= RXINT0, RXINT1
10000= Receive Buffer 0
10001= Receive Buffer 1
10010= TX/RX Buffer 0
10011= TX/RX Buffer 1
10100= TX/RX Buffer 2
10101= TX/RX Buffer 3
10110= TX/RX Buffer 4
10111= TX/RX Buffer 5
11000-11111= Reserved
Note 1: These bits can only be changed in Configuration mode. See Register 23-1 to change to Configuration mode.
2: This bit is used in Mode 2 only.
3: FIFO length of 4 or less will cause this bit to be set.
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REGISTER 23-4: COMSTAT: COMMUNICATION STATUS REGISTER
R/C-0
R/C-0
R-0
R-0
R-0
R-0
R-0
R-0
Mode 0
Mode 1
Mode 2
RXB0OVFL RXB1OVFL
TXBO
TXBP
RXBP
TXWARN
RXWARN
EWARN
R/C-0
—
R/C-0
R-0
R-0
R-0
R-0
R-0
R-0
RXBnOVFL
TXB0
TXBP
RXBP
TXWARN
RXWARN
EWARN
R/C-0
R/C-0
R-0
R-0
R-0
R-0
R-0
R-0
FIFOEMPTY RXBnOVFL
bit 7
TXBO
TXBP
RXBP
TXWARN
RXWARN
EWARN
bit 0
Legend:
R = Readable bit
-n = Value at POR
C = Clearable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7
Mode 0:
RXB0OVFL: Receive Buffer 0 Overflow bit
1= Receive Buffer 0 overflowed
0= Receive Buffer 0 has not overflowed
Mode 1:
Unimplemented: Read as ‘0’
Mode 2:
FIFOEMPTY: FIFO Not Empty bit
1= Receive FIFO is not empty
0= Receive FIFO is empty
bit 6
Mode 0:
RXB1OVFL: Receive Buffer 1 Overflow bit
1= Receive Buffer 1 overflowed
0= Receive Buffer 1 has not overflowed
Mode 1, 2:
RXBnOVFL: Receive Buffer n Overflow bit
1= Receive Buffer n has overflowed
0= Receive Buffer n has not overflowed
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
TXBO: Transmitter Bus-Off bit
1= Transmit error counter > 255
0= Transmit error counter ≤ 255
TXBP: Transmitter Bus Passive bit
1= Transmit error counter > 127
0= Transmit error counter ≤ 127
RXBP: Receiver Bus Passive bit
1= Receive error counter > 127
0= Receive error counter ≤ 127
TXWARN: Transmitter Warning bit
1= Transmit error counter > 95
0= Transmit error counter ≤ 95
RXWARN: Receiver Warning bit
1= 127 ≥ Receive error counter > 95
0= Receive error counter ≤ 95
EWARN: Error Warning bit
This bit is a flag of the RXWARN and TXWARN bits.
1= The RXWARN or the TXWARN bits are set
0= Neither the RXWARN or the TXWARN bits are set
© 2007 Microchip Technology Inc.
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23.2.2
DEDICATED CAN TRANSMIT
BUFFER REGISTERS
This section describes the dedicated CAN Transmit
Buffer registers and their associated control registers.
REGISTER 23-5: TXBnCON: TRANSMIT BUFFER n CONTROL REGISTERS [0 ≤ n ≤ 2]
R/C-0
TXBIF
R-0
TXABT(1)
R-0
R-0
R/W-0
U-0
—
R/W-0
R/W-0
Mode 0
TXLARB(1) TXERR(1) TXREQ(2)
TXPRI1(3) TXPRI0(3)
R/C-0
TXBIF
R-0
TXABT(1)
R-0
R-0
R/W-0
U-0
—
R/W-0
TXPRI1(3) TXPRI0(3)
bit 0
R/W-0
Mode 1,2
TXLARB(1) TXERR(1) TXREQ(2)
bit 7
Legend:
C = Clearable bit
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7
bit 6
bit 5
bit 4
bit 3
TXBIF: Transmit Buffer Interrupt Flag bit
1= Transmit buffer has completed transmission of message and may be reloaded
0= Transmit buffer has not completed transmission of a message
TXABT: Transmission Aborted Status bit(1)
1= Message was aborted
0= Message was not aborted
TXLARB: Transmission Lost Arbitration Status bit(1)
1= Message lost arbitration while being sent
0= Message did not lose arbitration while being sent
TXERR: Transmission Error Detected Status bit(1)
1= A bus error occurred while the message was being sent
0= A bus error did not occur while the message was being sent
TXREQ: Transmit Request Status bit(2)
1= Requests sending a message. Clears the TXABT, TXLARB and TXERR bits.
0= Automatically cleared when the message is successfully sent
bit 2
Unimplemented: Read as ‘0’
TXPRI1:TXPRI0: Transmit Priority bits(3)
bit 1-0
11= Priority Level 3 (highest priority)
10= Priority Level 2
01= Priority Level 1
00= Priority Level 0 (lowest priority)
Note 1: This bit is automatically cleared when TXREQ is set.
2: While TXREQ is set, Transmit Buffer registers remain read-only. Clearing this bit in software while the bit is
set will request a message abort.
3: These bits define the order in which transmit buffers will be transferred. They do not alter the CAN
message identifier.
DS39761B-page 282
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REGISTER 23-6: TXBnSIDH: TRANSMIT BUFFER n STANDARD IDENTIFIER REGISTERS,
HIGH BYTE [0 ≤ n ≤ 2]
R/W-x
SID10
R/W-x
SID9
R/W-x
SID8
R/W-x
SID7
R/W-x
SID6
R/W-x
SID5
R/W-x
SID4
R/W-x
SID3
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7-0
SID10:SID3: Standard Identifier bits (if EXIDE (TXBnSIDL<3>) = 0)
Extended Identifier bits EID28:EID21 (if EXIDE = 1).
REGISTER 23-7: TXBnSIDL: TRANSMIT BUFFER n STANDARD IDENTIFIER REGISTERS,
LOW BYTE [0 ≤ n ≤ 2]
R/W-x
SID2
R/W-x
SID1
R/W-x
SID0
U-0
—
R/W-x
EXIDE
U-0
—
R/W-x
EID17
R/W-x
EID16
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7-5
SID2:SID0: Standard Identifier bits (if EXIDE (TXBnSIDL<3>) = 0)
Extended Identifier bits EID20:EID18 (if EXIDE = 1).
Unimplemented: Read as ‘0’
bit 4
bit 3
EXIDE: Extended Identifier Enable bit
1= Message will transmit extended ID, SID10:SID0 become EID28:EID18
0= Message will transmit standard ID, EID17:EID0 are ignored
bit 2
Unimplemented: Read as ‘0’
bit 1-0
EID17:EID16: Extended Identifier bits
REGISTER 23-8: TXBnEIDH: TRANSMIT BUFFER n EXTENDED IDENTIFIER REGISTERS,
HIGH BYTE [0 ≤ n ≤ 2]
R/W-x
EID15
R/W-x
EID14
R/W-x
EID13
R/W-x
EID12
R/W-x
EID11
R/W-x
EID10
R/W-x
EID9
R/W-x
EID8
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7-0
EID15:EID8: Extended Identifier bits (not used when transmitting standard identifier message)
© 2007 Microchip Technology Inc.
Preliminary
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REGISTER 23-9: TXBnEIDL: TRANSMIT BUFFER n EXTENDED IDENTIFIER REGISTERS,
LOW BYTE [0 ≤ n ≤ 2]
R/W-x
EID7
R/W-x
EID6
R/W-x
EID5
R/W-x
EID4
R/W-x
EID3
R/W-x
EID2
R/W-x
EID1
R/W-x
EID0
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7-0
EID7:EID0: Extended Identifier bits (not used when transmitting standard identifier message)
REGISTER 23-10: TXBnDm: TRANSMIT BUFFER n DATA FIELD BYTE m REGISTERS
[0 ≤ n ≤ 2, 0 ≤ m ≤ 7]
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
TXBnDm0
bit 0
TXBnDm7
TXBnDm6
TXBnDm5
TXBnDm4
TXBnDm3
TXBnDm2
TXBnDm1
bit 7
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
-n = Value at POR
bit 7-0
TXBnDm7:TXBnDm0: Transmit Buffer n Data Field Byte m bits (where 0 ≤ n < 3 and 0 ≤ m < 8)
Each transmit buffer has an array of registers. For example, Transmit Buffer 0 has 7 registers: TXB0D0
to TXB0D7.
DS39761B-page 284
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REGISTER 23-11: TXBnDLC: TRANSMIT BUFFER n DATA LENGTH CODE REGISTERS [0 ≤ n ≤ 2]
U-0
—
R/W-x
U-0
—
U-0
—
R/W-x
DLC3
R/W-x
DLC2
R/W-x
DLC1
R/W-x
DLC0
TXRTR
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7
bit 6
Unimplemented: Read as ‘0’
TXRTR: Transmit Remote Frame Transmission Request bit
1= Transmitted message will have TXRTR bit set
0= Transmitted message will have TXRTR bit cleared
bit 5-4
bit 3-0
Unimplemented: Read as ‘0’
DLC3:DLC0: Data Length Code bits
1111= Reserved
1110= Reserved
1101= Reserved
1100= Reserved
1011= Reserved
1010= Reserved
1001= Reserved
1000= Data length = 8 bytes
0111= Data length = 7 bytes
0110= Data length = 6 bytes
0101= Data length = 5 bytes
0100= Data length = 4 bytes
0011= Data length = 3 bytes
0010= Data length = 2 bytes
0001= Data length = 1 bytes
0000= Data length = 0 bytes
REGISTER 23-12: TXERRCNT: TRANSMIT ERROR COUNT REGISTER
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
TEC7
TEC6
TEC5
TEC4
TEC3
TEC2
TEC1
TEC0
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7-0
TEC7:TEC0: Transmit Error Counter bits
This register contains a value which is derived from the rate at which errors occur. When the error
count overflows, the bus-off state occurs. When the bus has 128 occurrences of 11 consecutive
recessive bits, the counter value is cleared.
© 2007 Microchip Technology Inc.
Preliminary
DS39761B-page 285
PIC18F2682/2685/4682/4685
EXAMPLE 23-3:
TRANSMITTING A CAN MESSAGE USING BANKED METHOD
; Need to transmit Standard Identifier message 123h using TXB0 buffer.
; To successfully transmit, CAN module must be either in Normal or Loopback mode.
; TXB0 buffer is not in access bank. And since we want banked method, we need to make sure
; that correct bank is selected.
BANKSEL TXB0CON
; One BANKSEL in beginning will make sure that we are
; in correct bank for rest of the buffer access.
; Now load transmit data into TXB0 buffer.
MOVLW
MOVWF
MY_DATA_BYTE1
TXB0D0
; Load first data byte into buffer
; Compiler will automatically set “BANKED” bit
; Load rest of data bytes - up to 8 bytes into TXB0 buffer.
...
; Load message identifier
MOVLW
MOVWF
MOVLW
MOVWF
60H
TXB0SIDL
24H
; Load SID2:SID0, EXIDE = 0
; Load SID10:SID3
TXB0SIDH
; No need to load TXB0EIDL:TXB0EIDH, as we are transmitting Standard Identifier Message only.
; Now that all data bytes are loaded, mark it for transmission.
MOVLW
MOVWF
B’00001000’
TXB0CON
; Normal priority; Request transmission
; If required, wait for message to get transmitted
BTFSC
BRA
TXB0CON, TXREQ
$-2
; Is it transmitted?
; No. Continue to wait...
; Message is transmitted.
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EXAMPLE 23-4:
TRANSMITTING A CAN MESSAGE USING WIN BITS
; Need to transmit Standard Identifier message 123h using TXB0 buffer.
; To successfully transmit, CAN module must be either in Normal or Loopback mode.
; TXB0 buffer is not in access bank. Use WIN bits to map it to RXB0 area.
MOVF
CANCON, W
; WIN bits are in lower 4 bits only. Read CANCON
; register to preserve all other bits. If operation
; mode is already known, there is no need to preserve
; other bits.
ANDLW
IORLW
MOVWF
B’11110000’
B’00001000’
CANCON
; Clear WIN bits.
; Select Transmit Buffer 0
; Apply the changes.
; Now TXB0 is mapped in place of RXB0. All future access to RXB0 registers will actually
; yield TXB0 register values.
; Load transmit data into TXB0 buffer.
MOVLW
MOVWF
MY_DATA_BYTE1
RXB0D0
; Load first data byte into buffer
; Access TXB0D0 via RXB0D0 address.
; Load rest of the data bytes - up to 8 bytes into “TXB0” buffer using RXB0 registers.
...
; Load message identifier
MOVLW
MOVWF
MOVLW
MOVWF
60H
RXB0SIDL
24H
; Load SID2:SID0, EXIDE = 0
; Load SID10:SID3
RXB0SIDH
; No need to load RXB0EIDL:RXB0EIDH, as we are transmitting Standard Identifier Message only.
; Now that all data bytes are loaded, mark it for transmission.
MOVLW
MOVWF
B’00001000’
RXB0CON
; Normal priority; Request transmission
; If required, wait for message to get transmitted
BTFSC
BRA
RXB0CON, TXREQ
$-2
; Is it transmitted?
; No. Continue to wait...
; Message is transmitted.
; If required, reset the WIN bits to default state.
© 2007 Microchip Technology Inc.
Preliminary
DS39761B-page 287
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23.2.3
DEDICATED CAN RECEIVE
BUFFER REGISTERS
This section shows the dedicated CAN Receive Buffer
registers with their associated control registers.
REGISTER 23-13: RXB0CON: RECEIVE BUFFER 0 CONTROL REGISTER
R/C-0
RXFUL(1)
R/W-0
RXM1
R/W-0
RXM0
U-0
—
R-0
R/W-0
R-0
R-0
Mode 0
RXRTRRO RXB0DBEN JTOFF(2)
FILHIT0
R/C-0
RXFUL(1)
R/W-0
RXM1
R-0
R-0
R-0
R-0
R-0
R-0
Mode 1,2
RTRRO
FILHIT4
FILHIT3
FILHIT2
FILHIT1
FILHIT0
bit 7
bit 0
Legend:
C = Clearable bit
W = Writable bit
‘1’ = Bit is set
R = Readable bit
-n = Value at POR
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7
bit 6
RXFUL: Receive Full Status bit(1)
1= Receive buffer contains a received message
0= Receive buffer is open to receive a new message
Mode 0:
RXM1: Receive Buffer Mode bit 1 (combines with RXM0 to form RXM<1:0> bits, see bit 5)
11= Receive all messages (including those with errors); filter criteria is ignored
10= Receive only valid messages with extended identifier; EXIDEN in RXFnSIDL must be ‘1’
01= Receive only valid messages with standard identifier; EXIDEN in RXFnSIDL must be ‘0’
00= Receive all valid messages as per EXIDEN bit in RXFnSIDL register
Mode 1, 2:
RXM1: Receive Buffer Mode bit 1
1= Receive all messages (including those with errors); acceptance filters are ignored
0= Receive all valid messages as per acceptance filters
bit 5
Mode 0:
RXM0: Receive Buffer Mode bit 0 (combines with RXM1 to form RXM<1:0> bits, see bit 6)
Mode 1, 2:
RTRRO: Remote Transmission Request bit for Received Message (read-only)
1= A remote transmission request is received
0= A remote transmission request is not received
bit 4
bit 3
Mode 0:
Unimplemented: Read as ‘0’
Mode 1, 2:
FILHIT4: Filter Hit bit 4
This bit combines with other bits to form filter acceptance bits <4:0>.
Mode 0:
RXRTRRO: Remote Transmission Request bit for Received Message (read-only)
1= A remote transmission request is received
0= A remote transmission request is not received
Mode 1, 2:
FILHIT3: Filter Hit bit 3
This bit combines with other bits to form filter acceptance bits <4:0>.
Note 1: This bit is set by the CAN module upon receiving a message and must be cleared by software after the
buffer is read. As long as RXFUL is set, no new message will be loaded and buffer will be considered full.
After clearing the RXFUL flag, the PIR3 bit, RXB0IF, can be cleared. If RXB0IF is cleared, but RXFUL is
not cleared, then RXB0IF is set again.
2: This bit allows same filter jump table for both RXB0CON and RXB1CON.
DS39761B-page 288
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© 2007 Microchip Technology Inc.
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REGISTER 23-13: RXB0CON: RECEIVE BUFFER 0 CONTROL REGISTER (CONTINUED)
bit 2
bit 1
bit 0
Mode 0:
RXB0DBEN: Receive Buffer 0 Double-Buffer Enable bit
1= Receive Buffer 0 overflow will write to Receive Buffer 1
0= No Receive Buffer 0 overflow to Receive Buffer 1
Mode 1, 2:
FILHIT2: Filter Hit bit 2
This bit combines with other bits to form filter acceptance bits <4:0>.
Mode 0:
JTOFF: Jump Table Offset bit (read-only copy of RXB0DBEN)(2)
1= Allows jump table offset between 6 and 7
0= Allows jump table offset between 1 and 0
Mode 1, 2:
FILHIT1: Filter Hit bit 1
This bit combines with other bits to form filter acceptance bits <4:0>.
Mode 0:
FILHIT0: Filter Hit bit 0
This bit indicates which acceptance filter enabled the message reception into Receive Buffer 0.
1= Acceptance Filter 1 (RXF1)
0= Acceptance Filter 0 (RXF0)
Mode 1, 2:
FILHIT0: Filter Hit bit 0
This bit, in combination with FILHIT<4:1>, indicates which acceptance filter enabled the message reception
into this receive buffer.
01111= Acceptance Filter 15 (RXF15)
01110= Acceptance Filter 14 (RXF14)
...
00000= Acceptance Filter 0 (RXF0)
Note 1: This bit is set by the CAN module upon receiving a message and must be cleared by software after the
buffer is read. As long as RXFUL is set, no new message will be loaded and buffer will be considered full.
After clearing the RXFUL flag, the PIR3 bit, RXB0IF, can be cleared. If RXB0IF is cleared, but RXFUL is
not cleared, then RXB0IF is set again.
2: This bit allows same filter jump table for both RXB0CON and RXB1CON.
© 2007 Microchip Technology Inc.
Preliminary
DS39761B-page 289
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REGISTER 23-14: RXB1CON: RECEIVE BUFFER 1 CONTROL REGISTER
R/C-0
RXFUL(1)
R/W-0
RXM1
R/W-0
RXM0
U-0
—
R-0
R/W-0
R-0
R-0
Mode 0
RXRTRRO
FILHIT2
FILHIT1
FILHIT0
R/C-0
RXFUL(1)
R/W-0
RXM1
R-0
R-0
R-0
R-0
R-0
R-0
Mode 1,2
RTRRO
FILHIT4
FILHIT3
FILHIT2
FILHIT1
FILHIT0
bit 7
bit 0
Legend:
C = Clearable bit
W = Writable bit
‘1’ = Bit is set
R = Readable bit
-n = Value at POR
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7
bit 6
RXFUL: Receive Full Status bit(1)
1= Receive buffer contains a received message
0= Receive buffer is open to receive a new message
Mode 0:
RXM1: Receive Buffer Mode bit 1 (combines with RXM0 to form RXM<1:0> bits, see bit 5)
11= Receive all messages (including those with errors); filter criteria is ignored
10= Receive only valid messages with extended identifier; EXIDEN in RXFnSIDL must be ‘1’
01= Receive only valid messages with standard identifier, EXIDEN in RXFnSIDL must be ‘0’
00= Receive all valid messages as per EXIDEN bit in RXFnSIDL register
Mode 1, 2:
RXM1: Receive Buffer Mode bit
1= Receive all messages (including those with errors); acceptance filters are ignored
0= Receive all valid messages as per acceptance filters
bit 5
Mode 0:
RXM0: Receive Buffer Mode bit 0 (combines with RXM1 to form RXM<1:0> bits, see bit 6)
Mode 1, 2:
RTRRO: Remote Transmission Request bit for Received Message (read-only)
1= A remote transmission request is received
0= A remote transmission request is not received
bit 4
bit 3
Mode 0:
Unimplemented: Read as ‘0’
Mode 1, 2:
FILHIT4: Filter Hit bit 4
This bit combines with other bits to form filter acceptance bits <4:0>.
Mode 0:
RXRTRRO: Remote Transmission Request bit for Received Message (read-only)
1= A remote transmission request is received
0= A remote transmission request is not received
Mode 1, 2:
FILHIT3: Filter Hit bit 3
This bit combines with other bits to form filter acceptance bits <4:0>.
Note 1: This bit is set by the CAN module upon receiving a message and must be cleared by software after the
buffer is read. As long as RXFUL is set, no new message will be loaded and buffer will be considered full.
DS39761B-page 290
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REGISTER 23-14: RXB1CON: RECEIVE BUFFER 1 CONTROL REGISTER (CONTINUED)
bit 2-0
Mode 0:
FILHIT2:FILHIT0: Filter Hit bits
These bits indicate which acceptance filter enabled the last message reception into Receive Buffer 1.
111= Reserved
110= Reserved
101= Acceptance Filter 5 (RXF5)
100= Acceptance Filter 4 (RXF4)
011= Acceptance Filter 3 (RXF3)
010= Acceptance Filter 2 (RXF2)
001= Acceptance Filter 1 (RXF1), only possible when RXB0DBEN bit is set
000= Acceptance Filter 0 (RXF0), only possible when RXB0DBEN bit is set
Mode 1, 2:
FILHIT2:FILHIT0 Filter Hit bits <2:0>
These bits, in combination with FILHIT<4:3>, indicate which acceptance filter enabled the message
reception into this receive buffer.
01111= Acceptance Filter 15 (RXF15)
01110= Acceptance Filter 14 (RXF14)
...
00000= Acceptance Filter 0 (RXF0)
Note 1: This bit is set by the CAN module upon receiving a message and must be cleared by software after the
buffer is read. As long as RXFUL is set, no new message will be loaded and buffer will be considered full.
REGISTER 23-15: RXBnSIDH: RECEIVE BUFFER n STANDARD IDENTIFIER REGISTERS,
HIGH BYTE [0 ≤ n ≤ 1]
R-x
R-x
R-x
R-x
R-x
R-x
R-x
R-x
SID10
SID9
SID8
SID7
SID6
SID5
SID4
SID3
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7-0
SID10:SID3: Standard Identifier bits (if EXID (RXBnSIDL<3>) = 0)
Extended Identifier bits EID28:EID21 (if EXID = 1).
© 2007 Microchip Technology Inc.
Preliminary
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REGISTER 23-16: RXBnSIDL: RECEIVE BUFFER n STANDARD IDENTIFIER REGISTERS,
LOW BYTE [0 ≤ n ≤ 1]
R-x
R-x
R-x
R-x
R-x
U-0
—
R-x
R-x
SID2
SID1
SID0
SRR
EXID
EID17
EID16
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7-5
bit 4
SID2:SID0: Standard Identifier bits (if EXID = 0)
Extended Identifier bits EID20:EID18 (if EXID = 1).
SRR: Substitute Remote Request bit
This bit is always ‘0’ when EXID = 1or equal to the value of RXRTRRO (RBXnCON<3>) when EXID = 0.
EXID: Extended Identifier bit
bit 3
1= Received message is an extended data frame, SID10:SID0 are EID28:EID18
0= Received message is a standard data frame
bit 2
Unimplemented: Read as ‘0’
bit 1-0
EID17:EID16: Extended Identifier bits
REGISTER 23-17: RXBnEIDH: RECEIVE BUFFER n EXTENDED IDENTIFIER REGISTERS,
HIGH BYTE [0 ≤ n ≤ 1]
R-x
R-x
R-x
R-x
R-x
R-x
R-x
R-x
EID15
EID14
EID13
EID12
EID11
EID10
EID9
EID8
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7-0
EID15:EID8: Extended Identifier bits
REGISTER 23-18: RXBnEIDL: RECEIVE BUFFER n EXTENDED IDENTIFIER REGISTERS,
LOW BYTE [0 ≤ n ≤ 1]
R-x
R-x
R-x
R-x
R-x
R-x
R-x
R-x
EID7
EID6
EID5
EID4
EID3
EID2
EID1
EID0
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7-0
EID7:EID0: Extended Identifier bits
DS39761B-page 292
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REGISTER 23-19: RXBnDLC: RECEIVE BUFFER n DATA LENGTH CODE REGISTERS [0 ≤ n ≤ 1]
U-0
—
R-x
R-x
R-x
R-x
R-x
R-x
R-x
RXRTR
RB1
RB0
DLC3
DLC2
DLC1
DLC0
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7
bit 6
Unimplemented: Read as ‘0’
RXRTR: Receiver Remote Transmission Request bit
1= Remote transfer request
0= No remote transfer request
bit 5
RB1: Reserved bit 1
Reserved by CAN Spec and read as ‘0’.
RB0: Reserved bit 0
bit 4
Reserved by CAN Spec and read as ‘0’.
DLC3:DLC0: Data Length Code bits
bit 3-0
1111= Invalid
1110= Invalid
1101= Invalid
1100= Invalid
1011= Invalid
1010= Invalid
1001= Invalid
1000= Data length = 8 bytes
0111= Data length = 7 bytes
0110= Data length = 6 bytes
0101= Data length = 5 bytes
0100= Data length = 4 bytes
0011= Data length = 3 bytes
0010= Data length = 2 bytes
0001= Data length = 1 bytes
0000= Data length = 0 bytes
REGISTER 23-20: RXBnDm: RECEIVE BUFFER n DATA FIELD BYTE m REGISTERS
[0 ≤ n ≤ 1, 0 ≤ m ≤ 7]
R-x
R-x
R-x
R-x
R-x
R-x
R-x
R-x
RXBnDm7
RXBnDm6
RXBnDm5
RXBnDm4 RXBnDm3
RXBnDm2
RXBnDm1
RXBnDm0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
-n = Value at POR
bit 7-0
RXBnDm7:RXBnDm0: Receive Buffer n Data Field Byte m bits (where 0 ≤ n < 1 and 0 < m < 7)
Each receive buffer has an array of registers. For example, Receive Buffer 0 has 8 registers: RXB0D0
to RXB0D7.
© 2007 Microchip Technology Inc.
Preliminary
DS39761B-page 293
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REGISTER 23-21: RXERRCNT: RECEIVE ERROR COUNT REGISTER
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
REC7
REC6
REC5
REC4
REC3
REC2
REC1
REC0
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7-0
REC7:REC0: Receive Error Counter bits
This register contains the receive error value as defined by the CAN specifications. When
RXERRCNT > 127, the module will go into an error-passive state. RXERRCNT does not have the
ability to put the module in “bus-off” state.
EXAMPLE 23-5:
READING A CAN MESSAGE
; Need to read a pending message from RXB0 buffer.
; To receive any message, filter, mask and RXM1:RXM0 bits in RXB0CON registers must be
; programmed correctly.
;
; Make sure that there is a message pending in RXB0.
BTFSS
BRA
RXB0CON, RXFUL
NoMessage
; Does RXB0 contain a message?
; No. Handle this situation...
; We have verified that a message is pending in RXB0 buffer.
; If this buffer can receive both Standard or Extended Identifier messages,
; identify type of message received.
BTFSS
BRA
RXB0SIDL, EXID
StandardMessage
; Is this Extended Identifier?
; No. This is Standard Identifier message.
; Yes. This is Extended Identifier message.
; Read all 29-bits of Extended Identifier message.
...
; Now read all data bytes
MOVFF
...
RXB0DO, MY_DATA_BYTE1
; Once entire message is read, mark the RXB0 that it is read and no longer FULL.
BCF
...
RXB0CON, RXFUL
; This will allow CAN Module to load new messages
; into this buffer.
DS39761B-page 294
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23.2.3.1
Programmable TX/RX and
Auto-RTR Buffers
The ECAN module contains 6 message buffers that can
be programmed as transmit or receive buffers. Any of
these buffers can also be programmed to automatically
handle RTR messages.
Note:
These registers are not used in Mode 0.
REGISTER 23-22: BnCON: TX/RX BUFFER n CONTROL REGISTERS IN RECEIVE MODE
[0 ≤ n ≤ 5, TXnEN (BSEL0<n>) = 0](1)
R/W-0
RXFUL(2)
R/W-0
RXM1
R-0
R-0
R-0
R-0
R-0
R-0
RXRTRRO
FILHIT4
FILHIT3
FILHIT2
FILHIT1
FILHIT0
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7
RXFUL: Receive Full Status bit(2)
1= Receive buffer contains a received message
0= Receive buffer is open to receive a new message
bit 6
RXM1: Receive Buffer Mode bit
1= Receive all messages including partial and invalid (acceptance filters are ignored)
0= Receive all valid messages as per acceptance filters
bit 5
RXRTRRO: Read-Only Remote Transmission Request for Received Message bit
1= Received message is a remote transmission request
0= Received message is not a remote transmission request
bit 4-0
FILHIT4:FILHIT0: Filter Hit bits
These bits indicate which acceptance filter enabled the last message reception into this buffer.
01111= Acceptance Filter 15 (RXF15)
01110= Acceptance Filter 14 (RXF14)
...
00001= Acceptance Filter 1 (RXF1)
00000= Acceptance Filter 0 (RXF0)
Note 1: These registers are available in Mode 1 and 2 only.
2: This bit is set by the CAN module upon receiving a message and must be cleared by software after the
buffer is read. As long as RXFUL is set, no new message will be loaded and the buffer will be considered
full.
© 2007 Microchip Technology Inc.
Preliminary
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REGISTER 23-23: BnCON: TX/RX BUFFER n CONTROL REGISTERS IN TRANSMIT MODE
[0 ≤ n ≤ 5, TXnEN (BSEL0<n>) = 1](1)
R/W-0
TXBIF(3)
R-0
TXABT(3)
R-0
TXLARB(3)
R-0
R/W-0
R/W-0
R/W-0
TXPRI1(5)
R/W-0
TXPRI0(5)
TXERR(3) TXREQ(2,4)
RTREN
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
-n = Value at POR
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1-0
TXBIF: Transmit Buffer Interrupt Flag bit(3)
1= A message is successfully transmitted
0= No message was transmitted
TXABT: Transmission Aborted Status bit(3)
1= Message was aborted
0= Message was not aborted
TXLARB: Transmission Lost Arbitration Status bit(3)
1= Message lost arbitration while being sent
0= Message did not lose arbitration while being sent
TXERR: Transmission Error Detected Status bit(3)
1= A bus error occurred while the message was being sent
0= A bus error did not occur while the message was being sent
TXREQ: Transmit Request Status bit(2,4)
1= Requests sending a message; clears the TXABT, TXLARB and TXERR bits
0= Automatically cleared when the message is successfully sent
RTREN: Automatic Remote Transmission Request Enable bit
1= When a remote transmission request is received, TXREQ will be automatically set
0= When a remote transmission request is received, TXREQ will be unaffected
TXPRI1:TXPRI0: Transmit Priority bits(5)
11= Priority Level 3 (highest priority)
10= Priority Level 2
01= Priority Level 1
00= Priority Level 0 (lowest priority)
Note 1: These registers are available in Mode 1 and 2 only.
2: Clearing this bit in software while the bit is set will request a message abort.
3: This bit is automatically cleared when TXREQ is set.
4: While TXREQ is set or transmission is in progress, transmit buffer registers remain read-only.
5: These bits set the order in which the transmit buffer will be transferred. They do not alter the CAN
message identifier.
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REGISTER 23-24: BnSIDH: TX/RX BUFFER n STANDARD IDENTIFIER REGISTERS,
HIGH BYTE IN RECEIVE MODE [0 ≤ n ≤ 5, TXnEN (BSEL0<n>) = 0](1)
R-x
R-x
R-x
R-x
R-x
R-x
R-x
R-x
SID10
SID9
SID8
SID7
SID6
SID5
SID4
SID3
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7-0
SID10:SID3: Standard Identifier bits (if EXIDE (BnSIDL<3>) = 0)
Extended Identifier bits EID28:EID21 (if EXIDE = 1).
Note 1: These registers are available in Mode 1 and 2 only.
REGISTER 23-25: BnSIDH: TX/RX BUFFER n STANDARD IDENTIFIER REGISTERS,
HIGH BYTE IN TRANSMIT MODE [0 ≤ n ≤ 5, TXnEN (BSEL0<n>) = 1](1)
R/W-x
SID10
R/W-x
SID9
R/W-x
SID8
R/W-x
SID7
R/W-x
SID6
R/W-x
SID5
R/W-x
SID4
R/W-x
SID3
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7-0
SID10:SID3: Standard Identifier bits (if EXIDE (BnSIDL<3>) = 0)
Extended Identifier bits EID28:EID21 (if EXIDE = 1).
Note 1: These registers are available in Mode 1 and 2 only.
© 2007 Microchip Technology Inc.
Preliminary
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REGISTER 23-26: BnSIDL: TX/RX BUFFER n STANDARD IDENTIFIER REGISTERS,
LOW BYTE IN RECEIVE MODE [0 ≤ n ≤ 5, TXnEN (BSEL0<n>) = 0](1)
R-x
R-x
R-x
R-x
R-x
U-0
—
R-x
R-x
SID2
SID1
SID0
SRR
EXID
EID17
EID16
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7-5
bit 4
SID2:SID0: Standard Identifier bits (if EXID = 0)
Extended Identifier bits EID20:EID18 (if EXID = 1).
SRR: Substitute Remote Transmission Request bit (only when EXID = 1)
1= Remote transmission request occurred
0= No remote transmission request occurred
bit 3
EXID: Extended Identifier Enable bit
1= Received message is an extended identifier frame (SID10:SID0 are EID28:EID18)
0= Received message is a standard identifier frame
bit 2
Unimplemented: Read as ‘0’
bit 1-0
EID17:EID16: Extended Identifier bits
Note 1: These registers are available in Mode 1 and 2 only.
REGISTER 23-27: BnSIDL: TX/RX BUFFER n STANDARD IDENTIFIER REGISTERS,
LOW BYTE IN RECEIVE MODE [0 ≤ n ≤ 5, TXnEN (BSEL0<n>) = 1](1)
R/W-x
SID2
R/W-x
SID1
R/W-x
SID0
U-0
—
R/W-x
EXIDE
U-0
—
R/W-x
EID17
R/W-x
EID16
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7-5
SID2:SID0: Standard Identifier bits (if EXIDE = 0)
Extended Identifier bits EID20:EID18 (if EXIDE = 1).
Unimplemented: Read as ‘0’
bit 4
bit 3
EXIDE: Extended Identifier Enable bit
1= Received message is an extended identifier frame (SID10:SID0 are EID28:EID18)
0= Received message is a standard identifier frame
bit 2
Unimplemented: Read as ‘0’
bit 1-0
EID17:EID16: Extended Identifier bits
Note 1: These registers are available in Mode 1 and 2 only.
DS39761B-page 298
Preliminary
© 2007 Microchip Technology Inc.
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REGISTER 23-28: BnEIDH: TX/RX BUFFER n EXTENDED IDENTIFIER REGISTERS,
HIGH BYTE IN RECEIVE MODE [0 ≤ n ≤ 5, TXnEN (BSEL0<n>) = 0](1)
R-x
R-x
R-x
R-x
R-x
R-x
R-x
R-x
EID15
EID14
EID13
EID12
EID11
EID10
EID9
EID8
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7-0
EID15:EID8: Extended Identifier bits
Note 1: These registers are available in Mode 1 and 2 only.
REGISTER 23-29: BnEIDH: TX/RX BUFFER n EXTENDED IDENTIFIER REGISTERS,
HIGH BYTE IN TRANSMIT MODE [0 ≤ n ≤ 5, TXnEN (BSEL0<n>) = 1](1)
R/W-x
EID15
R/W-x
EID14
R/W-x
EID13
R/W-x
EID12
R/W-x
EID11
R/W-x
EID10
R/W-x
EID9
R/W-x
EID8
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7-0
EID15:EID8: Extended Identifier bits
Note 1: These registers are available in Mode 1 and 2 only.
REGISTER 23-30: BnEIDL: TX/RX BUFFER n EXTENDED IDENTIFIER REGISTERS,
LOW BYTE IN RECEIVE MODE [0 ≤ n ≤ 5, TXnEN (BSEL<n>) = 0](1)
R-x
R-x
R-x
R-x
R-x
R-x
R-x
R-x
EID7
EID6
EID5
EID4
EID3
EID2
EID1
EID0
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7-0
EID7:EID0: Extended Identifier bits
Note 1: These registers are available in Mode 1 and 2 only.
© 2007 Microchip Technology Inc.
Preliminary
DS39761B-page 299
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REGISTER 23-31: BnEIDL: TX/RX BUFFER n EXTENDED IDENTIFIER REGISTERS,
LOW BYTE IN RECEIVE MODE [0 ≤ n ≤ 5, TXnEN (BSEL<n>) = 1](1)
R/W-x
EID7
R/W-x
EID6
R/W-x
EID5
R/W-x
EID4
R/W-x
EID3
R/W-x
EID2
R/W-x
EID1
R/W-x
EID0
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7-0
EID7:EID0: Extended Identifier bits
Note 1: These registers are available in Mode 1 and 2 only.
REGISTER 23-32: BnDm: TX/RX BUFFER n DATA FIELD BYTE m REGISTERS IN RECEIVE MODE
[0 ≤ n ≤ 5, 0 ≤ m ≤ 7, TXnEN (BSEL<n>) = 0](1)
R-x
R-x
R-x
R-x
R-x
R-x
R-x
R-x
BnDm7
BnDm6
BnDm5
BnDm4
BnDm3
BnDm2
BnDm1
BnDm0
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7-0
BnDm7:BnDm0: Receive Buffer n Data Field Byte m bits (where 0 ≤ n < 3 and 0 < m < 8)
Each receive buffer has an array of registers. For example, Receive Buffer 0 has 7 registers: B0D0 to
B0D7.
Note 1: These registers are available in Mode 1 and 2 only.
REGISTER 23-33: BnDm: TX/RX BUFFER n DATA FIELD BYTE m REGISTERS IN TRANSMIT MODE
[0 ≤ n ≤ 5, 0 ≤ m ≤ 7, TXnEN (BSEL<n>) = 1](1)
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
BnDm7
BnDm6
BnDm5
BnDm4
BnDm3
BnDm2
BnDm1
BnDm0
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7-0
BnDm7:BnDm0: Transmit Buffer n Data Field Byte m bits (where 0 ≤ n < 3 and 0 < m < 8)
Each transmit buffer has an array of registers. For example, Transmit Buffer 0 has 7 registers: TXB0D0
to TXB0D7.
Note 1: These registers are available in Mode 1 and 2 only.
DS39761B-page 300
Preliminary
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REGISTER 23-34: BnDLC: TX/RX BUFFER n DATA LENGTH CODE REGISTERS IN RECEIVE MODE
[0 ≤ n ≤ 5, TXnEN (BSEL<n>) = 0](1)
U-0
—
R-x
R-x
R-x
R-x
R-x
R-x
R-x
RXRTR
RB1
RB0
DLC3
DLC2
DLC1
DLC0
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7
bit 6
Unimplemented: Read as ‘0’
RXRTR: Receiver Remote Transmission Request bit
1= This is a remote transmission request
0= This is not a remote transmission request
bit 5
RB1: Reserved bit 1
Reserved by CAN Spec and read as ‘0’.
RB0: Reserved bit 0
bit 4
Reserved by CAN Spec and read as ‘0’.
DLC3:DLC0: Data Length Code bits
bit 3-0
1111= Reserved
1110= Reserved
1101= Reserved
1100= Reserved
1011= Reserved
1010= Reserved
1001= Reserved
1000= Data length = 8 bytes
0111= Data length = 7 bytes
0110= Data length = 6 bytes
0101= Data length = 5 bytes
0100= Data length = 4 bytes
0011= Data length = 3 bytes
0010= Data length = 2 bytes
0001= Data length = 1 bytes
0000= Data length = 0 bytes
Note 1: These registers are available in Mode 1 and 2 only.
© 2007 Microchip Technology Inc.
Preliminary
DS39761B-page 301
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REGISTER 23-35: BnDLC: TX/RX BUFFER n DATA LENGTH CODE REGISTERS IN TRANSMIT MODE
[0 ≤ n ≤ 5, TXnEN (BSEL<n>) = 1](1)
U-0
—
R/W-x
U-0
—
U-0
—
R/W-x
DLC3
R/W-x
DLC2
R/W-x
DLC1
R/W-x
DLC0
TXRTR
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7
bit 6
Unimplemented: Read as ‘0’
TXRTR: Transmitter Remote Transmission Request bit
1= Transmitted message will have RTR bit set
0= Transmitted message will have RTR bit cleared
bit 5-4
bit 3-0
Unimplemented: Read as ‘0’
DLC3:DLC0: Data Length Code bits
1111-1001= Reserved
1000= Data length = 8 bytes
0111= Data length = 7 bytes
0110= Data length = 6 bytes
0101= Data length = 5 bytes
0100= Data length = 4 bytes
0011= Data length = 3 bytes
0010= Data length = 2 bytes
0001= Data length = 1 bytes
0000= Data length = 0 bytes
Note 1: These registers are available in Mode 1 and 2 only.
REGISTER 23-36: BSEL0: BUFFER SELECT REGISTER 0(1)
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
U-0
—
U-0
—
B5TXEN
B4TXEN
B3TXEN
B2TXEN
B1TXEN
B0TXEN
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7-2
B5TXEN:B0TXEN: Buffer 5 to Buffer 0 Transmit Enable bit
1= Buffer is configured in Transmit mode
0= Buffer is configured in Receive mode
bit 1-0
Unimplemented: Read as ‘0’
Note 1: These registers are available in Mode 1 and 2 only.
DS39761B-page 302
Preliminary
© 2007 Microchip Technology Inc.
PIC18F2682/2685/4682/4685
23.2.3.2
Message Acceptance Filters
and Masks
This section describes the message acceptance filters
and masks for the CAN receive buffers.
REGISTER 23-37: RXFnSIDH: RECEIVE ACCEPTANCE FILTER n STANDARD IDENTIFIER FILTER
REGISTERS, HIGH BYTE [0 ≤ n ≤ 15](1)
R/W-x
SID10
R/W-x
SID9
R/W-x
SID8
R/W-x
SID7
R/W-x
SID6
R/W-x
SID5
R/W-x
SID4
R/W-x
SID3
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7-0
SID10:SID3: Standard Identifier Filter bits (if EXIDEN = 0)
Extended Identifier Filter bits EID28:EID21 (if EXIDEN = 1).
Note 1: Registers RXF6SIDH:RXF15SIDH are available in Mode 1 and 2 only.
REGISTER 23-38: RXFnSIDL: RECEIVE ACCEPTANCE FILTER n STANDARD IDENTIFIER FILTER
REGISTERS, LOW BYTE [0 ≤ n ≤ 15](1)
R/W-x
SID2
R/W-x
SID1
R/W-x
SID0
U-0
—
R/W-x
EXIDEN(2)
U-0
—
R/W-x
EID17
R/W-x
EID16
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7-5
SID2:SID0: Standard Identifier Filter bits (if EXIDEN = 0)
Extended Identifier Filter bits EID20:EID18 (if EXIDEN = 1).
Unimplemented: Read as ‘0’
bit 4
bit 3
EXIDEN: Extended Identifier Filter Enable bit(2)
1= Filter will only accept extended ID messages
0= Filter will only accept standard ID messages
bit 2
Unimplemented: Read as ‘0’
bit 1-0
EID17:EID16: Extended Identifier Filter bits
Note 1: Registers RXF6SIDL:RXF15SIDL are available in Mode 1 and 2 only.
2: In Mode 0, this bit must be set/cleared as required, irrespective of corresponding mask register value.
© 2007 Microchip Technology Inc.
Preliminary
DS39761B-page 303
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REGISTER 23-39: RXFnEIDH: RECEIVE ACCEPTANCE FILTER n EXTENDED IDENTIFIER
REGISTERS, HIGH BYTE [0 ≤ n ≤ 15](1)
R/W-x
EID15
R/W-x
EID14
R/W-x
EID13
R/W-x
EID12
R/W-x
EID11
R/W-x
EID10
R/W-x
EID9
R/W-x
EID8
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7-0
EID15:EID8: Extended Identifier Filter bits
Note 1: Registers RXF6EIDH:RXF15EIDH are available in Mode 1 and 2 only.
REGISTER 23-40: RXFnEIDL: RECEIVE ACCEPTANCE FILTER n EXTENDED IDENTIFIER
REGISTERS, LOW BYTE [0 ≤ n ≤ 15](1)
R/W-x
EID7
R/W-x
EID6
R/W-x
EID5
R/W-x
EID4
R/W-x
EID3
R/W-x
EID2
R/W-x
EID1
R/W-x
EID0
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7-0
EID7:EID0: Extended Identifier Filter bits
Note 1: Registers RXF6EIDL:RXF15EIDL are available in Mode 1 and 2 only.
REGISTER 23-41: RXMnSIDH: RECEIVE ACCEPTANCE MASK n STANDARD IDENTIFIER MASK
REGISTERS, HIGH BYTE [0 ≤ n ≤ 1]
R/W-x
SID10
R/W-x
SID9
R/W-x
SID8
R/W-x
SID7
R/W-x
SID6
R/W-x
SID5
R/W-x
SID4
R/W-x
SID3
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7-0
SID10:SID3: Standard Identifier Mask bits or Extended Identifier Mask bits EID28:EID21
DS39761B-page 304
Preliminary
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REGISTER 23-42: RXMnSIDL: RECEIVE ACCEPTANCE MASK n STANDARD IDENTIFIER MASK
REGISTERS, LOW BYTE [0 ≤ n ≤ 1]
R/W-x
SID2
R/W-x
SID1
R/W-x
SID0
U-0
—
R/W-0
EXIDEN(1)
U-0
—
R/W-x
EID17
R/W-x
EID16
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7-5
bit 4
SID2:SID0: Standard Identifier Mask bits or Extended Identifier Mask bits EID20:EID18
Unimplemented: Read as ‘0’
bit 3
Mode 0:
Unimplemented: Read as ‘0’
Mode 1, 2:
EXIDEN: Extended Identifier Filter Enable Mask bit(1)
1= Messages selected by the EXIDEN bit in RXFnSIDL will be accepted
0= Both standard and extended identifier messages will be accepted
bit 2
Unimplemented: Read as ‘0’
bit 1-0
EID17:EID16: Extended Identifier Mask bits
Note 1: This bit is available in Mode 1 and 2 only.
REGISTER 23-43: RXMnEIDH: RECEIVE ACCEPTANCE MASK n EXTENDED IDENTIFIER MASK
REGISTERS, HIGH BYTE [0 ≤ n ≤ 1]
R/W-x
EID15
R/W-x
EID14
R/W-x
EID13
R/W-x
EID12
R/W-x
EID11
R/W-x
EID10
R/W-x
EID9
R/W-x
EID8
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7-0
EID15:EID8: Extended Identifier Mask bits
REGISTER 23-44: RXMnEIDL: RECEIVE ACCEPTANCE MASK n EXTENDED IDENTIFIER MASK
REGISTERS, LOW BYTE [0 ≤ n ≤ 1]
R/W-x
EID7
R/W-x
EID6
R/W-x
EID5
R/W-x
EID4
R/W-x
EID3
R/W-x
EID2
R/W-x
EID1
R/W-x
EID0
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7-0
EID7:EID0: Extended Identifier Mask bits
© 2007 Microchip Technology Inc.
Preliminary
DS39761B-page 305
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REGISTER 23-45: RXFCONn: RECEIVE FILTER CONTROL REGISTER n [0 ≤ n ≤ 1](1)
R/W-0
R/W-0
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
RXFCON0
RXFCON1
RXF7EN
RXF6EN
RXF5EN
RXF4EN RXF3EN
RXF2EN
RXF1EN
RXF0EN
R/W-0
R/W-0
R/W-0
R/W-1
R/W-0
R/W-0
R/W-0
R/W-0
RXF15EN
RXF14EN
RXF13EN RXF12EN RXF11EN RXF10EN
RXF9EN
RXF8EN
bit 7
bit 0
Legend:
C = Clearable bit
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7-0
RXFnEN: Receive Filter n Enable bits
0= Filter is disabled
1= Filter is enabled
Note 1: This register is available in Mode 1 and 2 only.
Note:
Register 23-46 through Register 23-51 are writable in Configuration mode only.
REGISTER 23-46: SDFLC: STANDARD DATA BYTES FILTER LENGTH COUNT REGISTER(1)
U-0
—
U-0
—
U-0
—
R/W-0
FLC4
R/W-0
FLC3
R/W-0
FLC2
R/W-0
FLC1
R/W-0
FLC0
bit 0
bit 7
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7-5
bit 4-0
Unimplemented: Read as ‘0’
FLC4:FLC0: Filter Length Count bits
Mode 0:
Not used; forced to ‘00000’.
00000-10010 = 0
18 bits are available for standard data byte filter. Actual number of bits used
depends on DLC3:DLC0 bits (RXBnDLC<3:0> or BnDLC<3:0> if configured
as RX buffer) of message being received.
If DLC3:DLC0 = 0000 No bits will be compared with incoming data bits.
If DLC3:DLC0 = 0001 Up to 8 data bits of RXFnEID<7:0>, as determined by FLC2:FLC0, will be
compared with the corresponding number of data bits of the incoming
message.
If DLC3:DLC0 = 0010 Up to 16 data bits of RXFnEID<15:0>, as determined by FLC3:FLC0, will be
compared with the corresponding number of data bits of the incoming
message.
If DLC3:DLC0 = 0011 Up to 18 data bits of RXFnEID<17:0>, as determined by FLC4:FLC0, will be
compared with the corresponding number of data bits of the incoming
message.
Note 1: This register is available in Mode 1 and 2 only.
DS39761B-page 306
Preliminary
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REGISTER 23-47: RXFBCONn: RECEIVE FILTER BUFFER CONTROL REGISTER n(1)
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
RXFBCON0
RXFBCON1
RXFBCON2
RXFBCON3
RXFBCON4
RXFBCON5
RXFBCON6
RXFBCON7
F1BP_3
F1BP_2
F1BP_1
F1BP_0
F0BP_3
F0BP_2
F0BP_1
F0BP_0
R/W-0
R/W-0
R/W-0
R/W-1
R/W-0
R/W-0
R/W-0
R/W-1
F3BP_3
F3BP_2
F3BP_1
F3BP_0
F2BP_3
F2BP_2
F2BP_1
F2BP_0
R/W-0
R/W-0
R/W-0
R/W-1
R/W-0
R/W-0
R/W-0
R/W-1
F5BP_3
F5BP_2
F5BP_1
F5BP_0
F4BP_3
F4BP_2
F4BP_1
F4BP_0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
F7BP_3
F7BP_2
F7BP_1
F7BP_0
F6BP_3
F6BP_2
F6BP_1
F6BP_0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
F9BP_3
F9BP_2
F9BP_1
F9BP_0
F8BP_3
F8BP_2
F8BP_1
F8BP_0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
F11BP_3
F11BP_2
F11BP_1 F11BP_0 F10BP_3
F10BP_2
F10BP_1
F10BP_0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
F13BP_3
F13BP_2
F13BP_1 F13BP_0 F12BP_3
F12BP_2
F12BP_1
F12BP_0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
F15BP_3
F15BP_2
F15BP_1 F15BP_0 F14BP_3
F14BP_2
F14BP_1
F14BP_0
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7-0
FnBP_3:FnBP_0: Filter n Buffer Pointer Nibble bits
0000= Filter n is associated with RXB0
0001= Filter n is associated with RXB1
0010= Filter n is associated with B0
0011= Filter n is associated with B1
...
0111= Filter n is associated with B5
1111-1000= Reserved
Note 1: This register is available in Mode 1 and 2 only.
© 2007 Microchip Technology Inc.
Preliminary
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REGISTER 23-48: MSEL0: MASK SELECT REGISTER 0(1)
R/W-0
R/W-1
R/W-0
R/W-1
R/W-0
R/W-0
R/W-0
R/W-0
FIL3_1
FIL3_0
FIL2_1
FIL2_0
FIL1_1
FIL1_0
FIL0_1
FIL0_0
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7-6
bit 5-4
bit 3-2
bit 1-0
FIL3_1:FIL3_0: Filter 3 Select bits 1 and 0
11= No mask
10= Filter 15
01= Acceptance Mask 1
00= Acceptance Mask 0
FIL2_1:FIL2_0: Filter 2 Select bits 1 and 0
11= No mask
10= Filter 15
01= Acceptance Mask 1
00= Acceptance Mask 0
FIL1_1:FIL1_0: Filter 1 Select bits 1 and 0
11= No mask
10= Filter 15
01= Acceptance Mask 1
00= Acceptance Mask 0
FIL0_1:FIL0_0: Filter 0 Select bits 1 and 0
11= No mask
10= Filter 15
01= Acceptance Mask 1
00= Acceptance Mask 0
Note 1: This register is available in Mode 1 and 2 only.
DS39761B-page 308
Preliminary
© 2007 Microchip Technology Inc.
PIC18F2682/2685/4682/4685
REGISTER 23-49: MSEL1: MASK SELECT REGISTER 1(1)
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-1
R/W-0
R/W-1
FIL7_1
FIL7_0
FIL6_1
FIL6_0
FIL5_1
FIL5_0
FIL4_1
FIL4_0
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7-6
bit 5-4
bit 3-2
bit 1-0
FIL7_1:FIL7_0: Filter 7 Select bits 1 and 0
11= No mask
10= Filter 15
01= Acceptance Mask 1
00= Acceptance Mask 0
FIL6_1:FIL6_0: Filter 6 Select bits 1 and 0
11= No mask
10= Filter 15
01= Acceptance Mask 1
00= Acceptance Mask 0
FIL5_1:FIL5_0: Filter 5 Select bits 1 and 0
11= No mask
10= Filter 15
01= Acceptance Mask 1
00= Acceptance Mask 0
FIL4_1:FIL4_0: Filter 4 Select bits 1 and 0
11= No mask
10= Filter 15
01= Acceptance Mask 1
00= Acceptance Mask 0
Note 1: This register is available in Mode 1 and 2 only.
© 2007 Microchip Technology Inc.
Preliminary
DS39761B-page 309
PIC18F2682/2685/4682/4685
REGISTER 23-50: MSEL2: MASK SELECT REGISTER 2(1)
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
FIL11_1
FIL11_0
FIL10_1
FIL10_0
FIL9_1
FIL9_0
FIL8_1
FIL8_0
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7-6
bit 5-4
bit 3-2
bit 1-0
FIL11_1:FIL11_0: Filter 11 Select bits 1 and 0
11= No mask
10= Filter 15
01= Acceptance Mask 1
00= Acceptance Mask 0
FIL10_1:FIL10_0: Filter 10 Select bits 1 and 0
11= No mask
10= Filter 15
01= Acceptance Mask 1
00= Acceptance Mask 0
FIL9_1:FIL9_0: Filter 9 Select bits 1 and 0
11= No mask
10= Filter 15
01= Acceptance Mask 1
00= Acceptance Mask 0
FIL8_1:FIL8_0: Filter 8 Select bits 1 and 0
11= No mask
10= Filter 15
01= Acceptance Mask 1
00= Acceptance Mask 0
Note 1: This register is available in Mode 1 and 2 only.
DS39761B-page 310
Preliminary
© 2007 Microchip Technology Inc.
PIC18F2682/2685/4682/4685
REGISTER 23-51: MSEL3: MASK SELECT REGISTER 3(1)
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
FIL15_1
FIL15_0
FIL14_1
FIL14_0
FIL13_1
FIL13_0
FIL12_1
FIL12_0
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7-6
bit 5-4
bit 3-2
bit 1-0
FIL15_1:FIL15_0: Filter 15 Select bits 1 and 0
11= No mask
10= Filter 15
01= Acceptance Mask 1
00= Acceptance Mask 0
FIL14_1:FIL14_0: Filter 14 Select bits 1 and 0
11= No mask
10= Filter 15
01= Acceptance Mask 1
00= Acceptance Mask 0
FIL13_1:FIL13_0: Filter 13 Select bits 1 and 0
11= No mask
10= Filter 15
01= Acceptance Mask 1
00= Acceptance Mask 0
FIL12_1:FIL12_0: Filter 12 Select bits 1 and 0
11= No mask
10= Filter 15
01= Acceptance Mask 1
00= Acceptance Mask 0
Note 1: This register is available in Mode 1 and 2 only.
© 2007 Microchip Technology Inc.
Preliminary
DS39761B-page 311
PIC18F2682/2685/4682/4685
23.2.4
This section describes the CAN Baud Rate registers.
Note: These registers are writable in
Configuration mode only.
CAN BAUD RATE REGISTERS
REGISTER 23-52: BRGCON1: BAUD RATE CONTROL REGISTER 1
R/W-0
SJW1
R/W-0
SJW0
R/W-0
BRP5
R/W-0
BRP4
R/W-0
BRP3
R/W-0
BRP2
R/W-0
BRP1
R/W-0
BRP0
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7-6
bit 5-0
SJW1:SJW0: Synchronized Jump Width bits
11= Synchronization jump width time = 4 x TQ
10= Synchronization jump width time = 3 x TQ
01= Synchronization jump width time = 2 x TQ
00= Synchronization jump width time = 1 x TQ
BRP5:BRP0: Baud Rate Prescaler bits
111111= TQ = (2 x 64)/FOSC
111110= TQ = (2 x 63)/FOSC
:
:
000001= TQ = (2 x 2)/FOSC
000000= TQ = (2 x 1)/FOSC
DS39761B-page 312
Preliminary
© 2007 Microchip Technology Inc.
PIC18F2682/2685/4682/4685
REGISTER 23-53: BRGCON2: BAUD RATE CONTROL REGISTER 2
R/W-0
R/W-0
SAM
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
SEG2PHTS
SEG1PH2
SEG1PH1
SEG1PH0
PRSEG2
PRSEG1
PRSEG0
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7
SEG2PHTS: Phase Segment 2 Time Select bit
1= Freely programmable
0= Maximum of PHEG1 or Information Processing Time (IPT), whichever is greater
bit 6
SAM: Sample of the CAN bus Line bit
1= Bus line is sampled three times prior to the sample point
0= Bus line is sampled once at the sample point
bit 5-3
SEG1PH2:SEG1PH0: Phase Segment 1 bits
111= Phase Segment 1 time = 8 x TQ
110= Phase Segment 1 time = 7 x TQ
101= Phase Segment 1 time = 6 x TQ
100= Phase Segment 1 time = 5 x TQ
011= Phase Segment 1 time = 4 x TQ
010= Phase Segment 1 time = 3 x TQ
001= Phase Segment 1 time = 2 x TQ
000= Phase Segment 1 time = 1 x TQ
bit 2-0
PRSEG2:PRSEG0: Propagation Time Select bits
111= Propagation time = 8 x TQ
110= Propagation time = 7 x TQ
101= Propagation time = 6 x TQ
100= Propagation time = 5 x TQ
011= Propagation time = 4 x TQ
010= Propagation time = 3 x TQ
001= Propagation time = 2 x TQ
000= Propagation time = 1 x TQ
© 2007 Microchip Technology Inc.
Preliminary
DS39761B-page 313
PIC18F2682/2685/4682/4685
REGISTER 23-54: BRGCON3: BAUD RATE CONTROL REGISTER 3
R/W-0
R/W-0
U-0
—
U-0
—
U-0
—
R/W-0
R/W-0
R/W-0
WAKDIS
WAKFIL
SEG2PH2(1) SEG2PH1(1) SEG2PH0(1)
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7
bit 6
WAKDIS: Wake-up Disable bit
1= Disable CAN bus activity wake-up feature
0= Enable CAN bus activity wake-up feature
WAKFIL: Selects CAN bus Line Filter for Wake-up bit
1= Use CAN bus line filter for wake-up
0= CAN bus line filter is not used for wake-up
bit 5-3
bit 2-0
Unimplemented: Read as ‘0’
SEG2PH2:SEG2PH0: Phase Segment 2 Time Select bits(1)
111= Phase Segment 2 time = 8 x TQ
110= Phase Segment 2 time = 7 x TQ
101= Phase Segment 2 time = 6 x TQ
100= Phase Segment 2 time = 5 x TQ
011= Phase Segment 2 time = 4 x TQ
010= Phase Segment 2 time = 3 x TQ
001= Phase Segment 2 time = 2 x TQ
000= Phase Segment 2 time = 1 x TQ
Note 1: Ignored if SEG2PHTS bit (BRGCON2<7>) is ‘0’.
DS39761B-page 314
Preliminary
© 2007 Microchip Technology Inc.
PIC18F2682/2685/4682/4685
23.2.5
CAN MODULE I/O CONTROL
REGISTER
This register controls the operation of the CAN module’s
I/O pins in relation to the rest of the microcontroller.
REGISTER 23-55: CIOCON: CAN I/O CONTROL REGISTER
U-0
—
U-0
—
R/W-0
ENDRHI(1)
R/W-0
U-0
—
U-0
—
U-0
—
U-0
—
CANCAP
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7-6
bit 5
Unimplemented: Read as ‘0’
ENDRHI: Enable Drive High bit(1)
1= CANTX pin will drive VDD when recessive
0= CANTX pin will be tri-state when recessive
bit 4
CANCAP: CAN Message Receive Capture Enable bit
1= Enable CAN capture, CAN message receive signal replaces input on RC2/CCP1
0= Disable CAN capture, RC2/CCP1 input to CCP1 module
bit 3-0
Unimplemented: Read as ‘0’
Note 1: Always set this bit when using differential bus to avoid signal crosstalk in CANTX from other nearby pins.
© 2007 Microchip Technology Inc.
Preliminary
DS39761B-page 315
PIC18F2682/2685/4682/4685
23.2.6
CAN INTERRUPT REGISTERS
Register 23-56 through Register 23-58 in this section
are the same as described in Section 9.0 “Interrupts”.
They are duplicated here for convenience.
REGISTER 23-56: PIR3: PERIPHERAL INTERRUPT REQUEST (FLAG) REGISTER 3
R/W-0
IRXIF
R/W-0
R/W-0
ERRIF
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
Mode 0
WAKIF
TXB2IF
TXB1IF(1) TXB0IF(1)
RXB1IF
RXB0IF
R/W-0
IRXIF
R/W-0
R/W-0
ERRIF
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
Mode 1,2
WAKIF
TXBnIF
TXB1IF(1) TXB0IF(1)
RXBnIF
FIFOWMIF
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7
bit 6
bit 5
bit 4
IRXIF: CAN Invalid Received Message Interrupt Flag bit
1= An invalid message has occurred on the CAN bus
0= No invalid message on CAN bus
WAKIF: CAN bus Activity Wake-up Interrupt Flag bit
1= Activity on CAN bus has occurred
0= No activity on CAN bus
ERRIF: CAN bus Error Interrupt Flag bit
1= An error has occurred in the CAN module (multiple sources)
0= No CAN module errors
When CAN is in Mode 0:
TXB2IF: CAN Transmit Buffer 2 Interrupt Flag bit
1= Transmit Buffer 2 has completed transmission of a message and may be reloaded
0= Transmit Buffer 2 has not completed transmission of a message
When CAN is in Mode 1 or 2:
TXBnIF: Any Transmit Buffer Interrupt Flag bit
1= One or more transmit buffers have completed transmission of a message and may be reloaded
0= No transmit buffer is ready for reload
bit 3
bit 2
bit 1
TXB1IF: CAN Transmit Buffer 1 Interrupt Flag bit(1)
1= Transmit Buffer 1 has completed transmission of a message and may be reloaded
0= Transmit Buffer 1 has not completed transmission of a message
TXB0IF: CAN Transmit Buffer 0 Interrupt Flag bit(1)
1= Transmit Buffer 0 has completed transmission of a message and may be reloaded
0= Transmit Buffer 0 has not completed transmission of a message
When CAN is in Mode 0:
RXB1IF: CAN Receive Buffer 1 Interrupt Flag bit
1= Receive Buffer 1 has received a new message
0= Receive Buffer 1 has not received a new message
When CAN is in Mode 1 or 2:
RXBnIF: Any Receive Buffer Interrupt Flag bit
1= One or more receive buffers has received a new message
0= No receive buffer has received a new message
bit 0
When CAN is in Mode 0:
RXB0IF: CAN Receive Buffer 0 Interrupt Flag bit
1= Receive Buffer 0 has received a new message
0= Receive Buffer 0 has not received a new message
When CAN is in Mode 1:
Unimplemented: Read as ‘0’
When CAN is in Mode 2:
FIFOWMIF: FIFO Watermark Interrupt Flag bit
1= FIFO high watermark is reached
0= FIFO high watermark is not reached
Note 1: In CAN Mode 1 and 2, these bits are forced to ‘0’.
DS39761B-page 316
Preliminary
© 2007 Microchip Technology Inc.
PIC18F2682/2685/4682/4685
REGISTER 23-57: PIE3: PERIPHERAL INTERRUPT ENABLE REGISTER 3
R/W-0
IRXIE
R/W-0
R/W-0
ERRIE
R/W-0
R/W-0
TXB1IE(1) TXB0IE(1)
R/W-0
R/W-0
R/W-0
Mode 0
WAKIE
TXB2IE
RXB1IE
RXB0IE
R/W-0
IRXIE
R/W-0
R/W-0
ERRIE
R/W-0
R/W-0
TXB1IE(1) TXB0IE(1)
R/W-0
R/W-0
R/W-0
FIFOWMIE
bit 0
Mode 1
WAKIE
TXBnIE
RXBnIE
bit 7
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7
bit 6
bit 5
bit 4
IRXIE: CAN Invalid Received Message Interrupt Enable bit
1= Enable invalid message received interrupt
0= Disable invalid message received interrupt
WAKIE: CAN bus Activity Wake-up Interrupt Enable bit
1= Enable bus activity wake-up interrupt
0= Disable bus activity wake-up interrupt
ERRIE: CAN bus Error Interrupt Enable bit
1= Enable CAN bus error interrupt
0= Disable CAN bus error interrupt
When CAN is in Mode 0:
TXB2IE: CAN Transmit Buffer 2 Interrupt Enable bit
1= Enable Transmit Buffer 2 interrupt
0= Disable Transmit Buffer 2 interrupt
When CAN is in Mode 1 or 2:
TXBnIE: CAN Transmit Buffer Interrupts Enable bit
1= Enable transmit buffer interrupt; individual interrupt is enabled by TXBIE and BIE0
0= Disable all transmit buffer interrupts
bit 3
bit 2
bit 1
TXB1IE: CAN Transmit Buffer 1 Interrupt Enable bit(1)
1= Enable Transmit Buffer 1 interrupt
0= Disable Transmit Buffer 1 interrupt
TXB0IE: CAN Transmit Buffer 0 Interrupt Enable bit(1)
1= Enable Transmit Buffer 0 interrupt
0= Disable Transmit Buffer 0 interrupt
When CAN is in Mode 0:
RXB1IE: CAN Receive Buffer 1 Interrupt Enable bit
1= Enable Receive Buffer 1 interrupt
0= Disable Receive Buffer 1 interrupt
When CAN is in Mode 1 or 2:
RXBnIE: CAN Receive Buffer Interrupts Enable bit
1= Enable receive buffer interrupt; individual interrupt is enabled by BIE0
0= Disable all receive buffer interrupts
bit 0
When CAN is in Mode 0:
RXB0IE: CAN Receive Buffer 0 Interrupt Enable bit
1= Enable Receive Buffer 0 interrupt
0= Disable Receive Buffer 0 interrupt
When CAN is in Mode 1:
Unimplemented: Read as ‘0’
When CAN is in Mode 2:
FIFOWMIE: FIFO Watermark Interrupt Enable bit
1= Enable FIFO watermark interrupt
0= Disable FIFO watermark interrupt
Note 1: In CAN Mode 1 and 2, these bits are forced to ‘0’.
© 2007 Microchip Technology Inc.
Preliminary
DS39761B-page 317
PIC18F2682/2685/4682/4685
REGISTER 23-58: IPR3: PERIPHERAL INTERRUPT PRIORITY REGISTER 3
R/W-1
IRXIP
R/W-1
R/W-1
ERRIP
R/W-1
R/W-1
TXB1IP(1) TXB0IP(1)
R/W-1
R/W-1
R/W-1
Mode 0
WAKIP
TXB2IP
RXB1IP
RXB0IP
R/W-1
IRXIP
R/W-1
R/W-1
ERRIP
R/W-1
R/W-1
TXB1IP(1) TXB0IP(1)
R/W-1
R/W-1
R/W-1
FIFOWMIP
bit 0
Mode 1,2
WAKIP
TXBnIP
RXBnIP
bit 7
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7
bit 6
bit 5
bit 4
IRXIP: CAN Invalid Received Message Interrupt Priority bit
1= High priority
0= Low priority
WAKIP: CAN bus Activity Wake-up Interrupt Priority bit
1= High priority
0= Low priority
ERRIP: CAN bus Error Interrupt Priority bit
1= High priority
0= Low priority
When CAN is in Mode 0:
TXB2IP: CAN Transmit Buffer 2 Interrupt Priority bit
1= High priority
0= Low priority
When CAN is in Mode 1 or 2:
TXBnIP: CAN Transmit Buffer Interrupt Priority bit
1= High priority
0= Low priority
bit 3
bit 2
bit 1
TXB1IP: CAN Transmit Buffer 1 Interrupt Priority bit(1)
1= High priority
0= Low priority
TXB0IP: CAN Transmit Buffer 0 Interrupt Priority bit(1)
1= High priority
0= Low priority
When CAN is in Mode 0:
RXB1IP: CAN Receive Buffer 1 Interrupt Priority bit
1= High priority
0= Low priority
When CAN is in Mode 1 or 2:
RXBnIP: CAN Receive Buffer Interrupts Priority bit
1= High priority
0= Low priority
bit 0
When CAN is in Mode 0:
RXB0IP: CAN Receive Buffer 0 Interrupt Priority bit
1= High priority
0= Low priority
When CAN is in Mode 1:
Unimplemented: Read as ‘0’
When CAN is in Mode 2:
FIFOWMIP: FIFO Watermark Interrupt Priority bit
1= High priority
0= Low priority
Note 1: In CAN Mode 1 and 2, these bits are forced to ‘0’.
DS39761B-page 318
Preliminary
© 2007 Microchip Technology Inc.
PIC18F2682/2685/4682/4685
REGISTER 23-59: TXBIE: TRANSMIT BUFFERS INTERRUPT ENABLE REGISTER(1)
U-0
—
U-0
—
U-0
—
R/W-0
TXB2IE(2)
R/W-0
TXB1IE(2)
R/W-0
TXB0IE(2)
U-0
—
U-0
—
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7-5
bit 4-2
Unimplemented: Read as ‘0’
TXB2IE:TXB0IE: Transmit Buffer 2-0 Interrupt Enable bit(2)
1= Transmit buffer interrupt is enabled
0= Transmit buffer interrupt is disabled
bit 1-0
Unimplemented: Read as ‘0’
Note 1: This register is available in Mode 1 and 2 only.
2: TXBnIE in PIE3 register must be set to get an interrupt.
REGISTER 23-60: BIE0: BUFFER INTERRUPT ENABLE REGISTER 0(1)
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
B5IE(2)
B4IE(2)
B3IE(2)
B2IE(2)
B1IE(2)
B0IE(2)
RXB1IE(2)
RXB0IE(2)
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7-2
bit 1-0
B5IE:B0IE: Programmable Transmit/Receive Buffer 5-0 Interrupt Enable bit(2)
1= Interrupt is enabled
0= Interrupt is disabled
RXB1IE:RXB0IE: Dedicated Receive Buffer 1-0 Interrupt Enable bit(2)
1= Interrupt is enabled
0= Interrupt is disabled
Note 1: This register is available in Mode 1 and 2 only.
2: Either TXBnIE or RXBnIE in PIE3 register must be set to get an interrupt.
© 2007 Microchip Technology Inc.
Preliminary
DS39761B-page 319
PIC18F2682/2685/4682/4685
TABLE 23-1: CAN CONTROLLER REGISTER MAP
Address(1)
Name
SPBRGH(3)
Address
Name
Address
Name
Address
Name
F7Fh
F5Fh CANCON_RO0
F5Eh CANSTAT_RO0
F3Fh CANCON_RO2
F3Eh CANSTAT_RO2
F1Fh RXM1EIDL
F1Eh RXM1EIDH
F1Dh RXM1SIDL
F1Ch RXM1SIDH
F1Bh RXM0EIDL
F1Ah RXM0EIDH
F19h RXM0SIDL
F18h RXM0SIDH
F17h RXF5EIDL
F16h RXF5EIDH
F15h RXF5SIDL
F14h RXF5SIDH
F13h RXF4EIDL
F12h RXF4EIDH
F11h RXF4SIDL
F10h RXF4SIDH
F0Fh RXF3EIDL
F0Eh RXF3EIDH
F0Dh RXF3SIDL
F0Ch RXF3SIDH
F0Bh RXF2EIDL
F0Ah RXF2EIDH
F09h RXF2SIDL
F08h RXF2SIDH
F07h RXF1EIDL
F06h RXF1EIDH
F05h RXF1SIDL
F04h RXF1SIDH
F03h RXF0EIDL
F02h RXF0EIDH
F01h RXF0SIDL
F00h RXF0SIDH
F7Eh BAUDCON(3)
(4)
F7Dh
F7Ch
F7Bh
F7Ah
—
—
—
—
F5Dh
F5Ch
F5Bh
F5Ah
F59h
F58h
F57h
F56h
F55h
F54h
F53h
F52h
F51h
F50h
RXB1D7
RXB1D6
F3Dh
F3Ch
F3Bh
F3Ah
F39h
F38h
F37h
F36h
F35h
F34h
F33h
F32h
F31h
F30h
TXB1D7
TXB1D6
(4)
(4)
(4)
RXB1D5
TXB1D5
RXB1D4
TXB1D4
F79h ECCP1DEL(3)
RXB1D3
TXB1D3
(4)
F78h
F77h
F76h
F75h
F74h
F73h
F72h
F71h
F70h
F6Fh
F6Eh
F6Dh
F6Ch
F6Bh
F6Ah
F69h
F68h
F67h
F66h
F65h
F64h
F63h
F62h
F61h
F60h
—
RXB1D2
TXB1D2
ECANCON
TXERRCNT
RXERRCNT
COMSTAT
CIOCON
RXB1D1
TXB1D1
RXB1D0
TXB1D0
RXB1DLC
RXB1EIDL
RXB1EIDH
RXB1SIDL
RXB1SIDH
RXB1CON
TXB1DLC
TXB1EIDL
TXB1EIDH
TXB1SIDL
TXB1SIDH
TXB1CON
BRGCON3
BRGCON2
BRGCON1
CANCON
CANSTAT
RXB0D7
F4Fh CANCON_RO1(2)
F4Eh CANSTAT_RO1(2)
F2Fh CANCON_RO3(2)
F2Eh CANSTAT_RO3(2)
F4Dh
F4Ch
F4Bh
F4Ah
F49h
F48h
F47h
F46h
F45h
F44h
F43h
F42h
F41h
F40h
TXB0D7
TXB0D6
F2Dh
F2Ch
F2Bh
F2Ah
F29h
F28h
F27h
F26h
F25h
F24h
F23h
F22h
F21h
F20h
TXB2D7
TXB2D6
RXB0D6
RXB0D5
TXB0D5
TXB2D5
RXB0D4
TXB0D4
TXB2D4
RXB0D3
TXB0D3
TXB2D3
RXB0D2
TXB0D2
TXB2D2
RXB0D1
TXB0D1
TXB2D1
RXB0D0
TXB0D0
TXB2D0
RXB0DLC
RXB0EIDL
RXB0EIDH
RXB0SIDL
RXB0SIDH
RXB0CON
TXB0DLC
TXB0EIDL
TXB0EIDH
TXB0SIDL
TXB0SIDH
TXB0CON
TXB2DLC
TXB2EIDL
TXB2EIDH
TXB2SIDL
TXB2SIDH
TXB2CON
Note 1: Shaded registers are available in Access Bank low area, while the rest are available in Bank 15.
2: CANSTAT register is repeated in these locations to simplify application firmware. Unique names are given
for each instance of the controller register due to the Microchip header file requirement.
3: These registers are not CAN registers.
4: Unimplemented registers are read as ‘0’.
DS39761B-page 320
Preliminary
© 2007 Microchip Technology Inc.
PIC18F2682/2685/4682/4685
TABLE 23-1: CAN CONTROLLER REGISTER MAP (CONTINUED)
Address(1)
EFFh
EFEh
EFDh
EFCh
EFBh
EFAh
EF9h
EF8h
EF7h
EF6h
EF5h
EF4h
EF3h
EF2h
EF1h
EF0h
EEFh
EEEh
EEDh
EECh
EEBh
EEAh
EE9h
EE8h
EE7h
EE6h
EE5h
EE4h
EE3h
EE2h
EE1h
EE0h
Name
Address
EDFh
EDEh
EDDh
EDCh
EDBh
EDAh
ED9h
ED8h
ED7h
ED6h
ED5h
ED4h
ED3h
ED2h
ED1h
ED0h
ECFh
ECEh
ECDh
ECCh
ECBh
ECAh
EC9h
EC8h
EC7h
EC6h
EC5h
EC4h
EC3h
EC2h
EC1h
EC0h
Name
Address
EBFh
EBEh
EBDh
EBCh
EBBh
EBAh
EB9h
EB8h
EB7h
EB6h
EB5h
EB4h
EB3h
EB2h
EB1h
EB0h
EAFh
EAEh
EADh
EACh
EABh
EAAh
EA9h
EA8h
EA7h
EA6h
EA5h
EA4h
EA3h
EA2h
EA1h
EA0h
Name
Address
E9Fh
E9Eh
E9Dh
E9Ch
E9Bh
E9Ah
E99h
E98h
E97h
E96h
E95h
E94h
E93h
E92h
E91h
E90h
E8Fh
E8Eh
E8Dh
E8Ch
E8Bh
E8Ah
E89h
E88h
E87h
E86h
E85h
E84h
E83h
E82h
E81h
E80h
Name
(4)
(4)
(4)
(4)
—
—
—
—
(4)
(4)
(4)
(4)
—
—
—
—
(4)
(4)
(4)
(4)
—
—
—
—
(4)
(4)
(4)
(4)
—
—
—
—
(4)
(4)
(4)
(4)
—
—
—
—
(4)
(4)
(4)
(4)
—
—
—
—
(4)
(4)
(4)
(4)
—
—
—
—
(4)
(4)
(4)
(4)
—
—
—
—
(4)
(4)
(4)
(4)
—
—
—
—
(4)
(4)
(4)
(4)
—
—
—
—
(4)
(4)
(4)
(4)
—
—
—
—
(4)
(4)
(4)
(4)
—
—
—
—
(4)
(4)
(4)
(4)
—
—
—
—
(4)
(4)
(4)
(4)
—
—
—
—
(4)
(4)
(4)
(4)
—
—
—
—
(4)
(4)
(4)
(4)
—
—
—
—
(4)
(4)
(4)
(4)
—
—
—
—
(4)
(4)
(4)
(4)
—
—
—
—
(4)
(4)
(4)
(4)
—
—
—
—
(4)
(4)
(4)
(4)
—
—
—
—
(4)
(4)
(4)
(4)
—
—
—
—
(4)
(4)
(4)
(4)
—
—
—
—
(4)
(4)
(4)
(4)
—
—
—
—
(4)
(4)
(4)
(4)
—
—
—
—
(4)
(4)
(4)
(4)
—
—
—
—
(4)
(4)
(4)
(4)
—
—
—
—
(4)
(4)
(4)
(4)
—
—
—
—
(4)
(4)
(4)
(4)
—
—
—
—
(4)
(4)
(4)
(4)
—
—
—
—
(4)
(4)
(4)
(4)
—
—
—
—
(4)
(4)
(4)
(4)
—
—
—
—
(4)
(4)
(4)
(4)
—
—
—
—
Note 1: Shaded registers are available in Access Bank low area, while the rest are available in Bank 15.
2: CANSTAT register is repeated in these locations to simplify application firmware. Unique names are given
for each instance of the controller register due to the Microchip header file requirement.
3: These registers are not CAN registers.
4: Unimplemented registers are read as ‘0’.
© 2007 Microchip Technology Inc.
Preliminary
DS39761B-page 321
PIC18F2682/2685/4682/4685
TABLE 23-1: CAN CONTROLLER REGISTER MAP (CONTINUED)
Address(1)
Name
Address
Name
Address
Name
Address
E1Fh
E1Eh
E1Dh
E1Ch
E1Bh
E1Ah
E19h
E18h
E17h
E16h
E15h
E14h
E13h
E12h
E11h
E10h
E0Fh
E0Eh
E0Dh
E0Ch
E0Bh
E0Ah
E09h
E08h
E07h
E06h
E05h
E04h
E03h
E02h
E01h
E00h
Name
E7Fh CANCON_RO4(2)
E7Eh CANSTAT_RO4(2)
E5Fh CANCON_RO6(2)
E5Eh CANSTAT_RO6(2)
E3Fh CANCON_RO8(2)
E3Eh CANSTAT_RO8(2)
—
(4)
(4)
—
(4)
E7Dh
E7Ch
E7Bh
E7Ah
E79h
E78h
E77h
E76h
E75h
E74h
E73h
E72h
E71h
E70h
B5D7
B5D6
E5Dh
E5Ch
E5Bh
E5Ah
E59h
E58h
E57h
E56h
E55h
E54h
E53h
E52h
E51h
E50h
B3D7
B3D6
E3Dh
E3Ch
E3Bh
E3Ah
E39h
E38h
E37h
E36h
E35h
E34h
E33h
E32h
E31h
E30h
B1D7
B1D6
—
(4)
—
(4)
B5D5
B3D5
B1D5
—
(4)
B5D4
B3D4
B1D4
—
(4)
B5D3
B3D3
B1D3
—
(4)
B5D2
B3D2
B1D2
—
(4)
B5D1
B3D1
B1D1
—
(4)
B5D0
B3D0
B1D0
—
(4)
B5DLC
B5EIDL
B5EIDH
B5SIDL
B5SIDH
B5CON
B3DLC
B3EIDL
B3EIDH
B3SIDL
B3SIDH
B3CON
B1DLC
B1EIDL
B1EIDH
B1SIDL
B1SIDH
B1CON
—
(4)
—
(4)
—
(4)
—
(4)
—
(4)
—
(4)
E6Fh CANCON_RO5
E6Eh CANSTAT_RO5
E4Fh CANCON_RO7
E4Eh CANSTAT_RO7
E2Fh CANCON_RO9
E2Eh CANSTAT_RO9
—
(4)
—
(4)
E6Dh
E6Ch
E6Bh
E6Ah
E69h
E68h
E67h
E66h
E65h
E64h
E63h
E62h
E61h
E60h
B4D7
B4D6
E4Dh
E4Ch
E4Bh
E4Ah
E49h
E48h
E47h
E46h
E45h
E44h
E43h
E42h
E41h
E40h
B2D7
B2D6
E2Dh
E2Ch
E2Bh
E2Ah
E29h
E28h
E27h
E26h
E25h
E24h
E23h
E22h
E21h
E20h
B0D7
B0D6
—
(4)
—
(4)
B4D5
B2D5
B0D5
—
(4)
B4D4
B2D4
B0D4
—
(4)
B4D3
B2D3
B0D3
—
(4)
B4D2
B2D2
B0D2
—
(4)
B4D1
B2D1
B0D1
—
(4)
B4D0
B2D0
B0D0
—
(4)
B4DLC
B4EIDL
B4EIDH
B4SIDL
B4SIDH
B4CON
B2DLC
B2EIDL
B2EIDH
B2SIDL
B2SIDH
B2CON
B0DLC
B0EIDL
B0EIDH
B0SIDL
B0SIDH
B0CON
—
(4)
—
(4)
—
(4)
—
(4)
—
(4)
—
Note 1: Shaded registers are available in Access Bank low area, while the rest are available in Bank 15.
2: CANSTAT register is repeated in these locations to simplify application firmware. Unique names are given
for each instance of the controller register due to the Microchip header file requirement.
3: These registers are not CAN registers.
4: Unimplemented registers are read as ‘0’.
DS39761B-page 322
Preliminary
© 2007 Microchip Technology Inc.
PIC18F2682/2685/4682/4685
TABLE 23-1: CAN CONTROLLER REGISTER MAP (CONTINUED)
Address(1)
DFFh
DFEh
DFDh
DFCh
DFBh
DFAh
DF9h
DF8h
DF7h
DF6h
DF5h
DF4h
DF3h
DF2h
DF1h
DF0h
DEFh
DEEh
DEDh
DECh
DEBh
DEAh
DE9h
DE8h
DE7h
DE6h
DE5h
DE4h
DE3h
DE2h
DE1h
DE0h
Name
Address
DDFh
DDEh
DDDh
DDCh
DDBh
DDAh
DD9h
DD8h
DD7h
DD6h
DD5h
DD4h
DD3h
DD2h
DD1h
DD0h
DCFh
DCEh
DCDh
DCCh
DCBh
DCAh
DC9h
DC8h
DC7h
DC6h
DC5h
DC4h
DC3h
DC2h
DC1h
DC0h
Name
Address
DBFh
DBEh
DBDh
DBCh
DBBh
DBAh
DB9h
DB8h
DB7h
DB6h
DB5h
DB4h
DB3h
DB2h
DB1h
DB0h
DAFh
DAEh
DADh
DACh
DABh
DAAh
DA9h
DA8h
DA7h
DA6h
DA5h
DA4h
DA3h
DA2h
DA1h
DA0h
Name
Address
D9Fh
D9Eh
D9Dh
D9Ch
D9Bh
D9Ah
D99h
D98h
D97h
D96h
D95h
D94h
Name
(4)
(4)
(4)
(4)
—
—
—
—
(4)
(4)
(4)
(4)
—
—
—
—
(4)
(4)
(4)
(4)
—
—
—
—
(4)
(4)
(4)
TXBIE
—
—
—
(4)
(4)
(4)
(4)
—
—
—
—
(4)
(4)
(4)
BIE0
—
—
—
(4)
(4)
(4)
(4)
—
—
—
—
(4)
(4)
BSEL0
SDFLC
—
—
(4)
(4)
(4)
(4)
—
—
—
—
(4)
(4)
(4)
(4)
—
—
—
—
(4)
(4)
(4)
—
RXFCON1
—
—
(4)
(4)
(4)
—
RXFCON0
—
—
(4)
(4)
MSEL3
MSEL2
MSEL1
MSEL0
—
—
D93h RXF15EIDL
D92h RXF15EIDH
D91h RXF15SIDL
(4)
(4)
—
—
(4)
(4)
—
—
(4)
(4)
—
—
D90h RXF15SIDH
(4)
(4)
(4)
(4)
—
—
—
D8Fh
D8Eh
D8Dh
D8Ch
—
—
—
—
(4)
(4)
(4)
(4)
(4)
(4)
—
—
—
(4)
(4)
(4)
—
—
—
(4)
(4)
(4)
—
—
—
(4)
(4)
(4)
—
—
—
D8Bh RXF14EIDL
D8Ah RXF14EIDH
D89h RXF14SIDL
D88h RXF14SIDH
D87h RXF13EIDL
D86h RXF13EIDH
D85h RXF13SIDL
D84h RXF13SIDH
D83h RXF12EIDL
D82h RXF12EIDH
D81h RXF12SIDL
D80h RXF12SIDH
(4)
(4)
(4)
—
—
—
(4)
(4)
(4)
—
—
—
(4)
(4)
(4)
—
—
—
(4)
(4)
RXFBCON7
RXFBCON6
RXFBCON5
RXFBCON4
RXFBCON3
RXFBCON2
RXFBCON1
RXFBCON0
—
—
(4)
(4)
—
—
(4)
(4)
—
—
(4)
(4)
—
—
(4)
(4)
—
—
(4)
(4)
—
—
(4)
(4)
—
—
(4)
(4)
—
—
Note 1: Shaded registers are available in Access Bank low area, while the rest are available in Bank 15.
2: CANSTAT register is repeated in these locations to simplify application firmware. Unique names are given
for each instance of the controller register due to the Microchip header file requirement.
3: These registers are not CAN registers.
4: Unimplemented registers are read as ‘0’.
© 2007 Microchip Technology Inc.
Preliminary
DS39761B-page 323
PIC18F2682/2685/4682/4685
TABLE 23-1: CAN CONTROLLER REGISTER MAP (CONTINUED)
Address(1)
Name
(4)
D7Fh
D7Eh
D7Dh
D7Ch
D7Bh
D7Ah
D79h
D78h
D77h
D76h
D75h
D74h
D73h
D72h
D71h
D70h
D6Fh
D6Eh
D6Dh
D6Ch
D6Bh
D6Ah
D69h
D68h
D67h
D66h
D65h
D64h
D63h
D62h
D61h
D60h
—
(4)
—
(4)
—
(4)
—
RXF11EIDL
RXF11EIDH
RXF11SIDL
RXF11SIDH
RXF10EIDL
RXF10EIDH
RXF10SIDL
RXF10SIDH
RXF9EIDL
RXF9EIDH
RXF9SIDL
RXF9SIDH
(4)
—
(4)
—
(4)
—
(4)
—
RXF8EIDL
RXF8EIDH
RXF8SIDL
RXF8SIDH
RXF7EIDL
RXF7EIDH
RXF7SIDL
RXF7SIDH
RXF6EIDL
RXF6EIDH
RXF6SIDL
RXF6SIDH
Note 1: Shaded registers are available in Access Bank low area while the rest are available in Bank 15.
2: CANSTAT register is repeated in these locations to simplify application firmware. Unique names are given
for each instance of the controller register due to the Microchip header file requirement.
3: These registers are not CAN registers.
4: Unimplemented registers are read as ‘0’.
DS39761B-page 324
Preliminary
© 2007 Microchip Technology Inc.
PIC18F2682/2685/4682/4685
23.3.2
DISABLE MODE
23.3 CAN Modes of Operation
In Disable mode, the module will not transmit or
receive. The module has the ability to set the WAKIF bit
due to bus activity; however, any pending interrupts will
remain and the error counters will retain their value.
The PIC18F2682/2685/4682/4685 has six main modes
of operation:
• Configuration mode
• Disable mode
If the REQOP<2:0> bits are set to ‘001’, the module will
enter the module Disable mode. This mode is similar to
disabling other peripheral modules by turning off the
module enables. This causes the module internal clock
to stop unless the module is active (i.e., receiving or
transmitting a message). If the module is active, the
module will wait for 11 recessive bits on the CAN bus,
detect that condition as an Idle bus, then accept the
module disable command. OPMODE<2:0> = 001
indicates whether the module successfully went into the
module Disable mode.
• Normal Operation mode
• Listen Only mode
• Loopback mode
• Error Recognition mode
All modes, except Error Recognition, are requested by
setting the REQOP bits (CANCON<7:5>). Error Recog-
nition mode is requested through the RXM bits of the
Receive Buffer register(s). Entry into a mode is
Acknowledged by monitoring the OPMODE bits.
When changing modes, the mode will not actually
change until all pending message transmissions are
complete. Because of this, the user must verify that the
device has actually changed into the requested mode
before further operations are executed.
The WAKIF interrupt is the only module interrupt that is
still active in the Disable mode. If the WAKDIS is
cleared and WAKIE is set, the processor will receive an
interrupt whenever the module detects recessive to
dominant transition. On wake-up, the module will auto-
matically be set to the previous mode of operation. For
example, if the module was switched from Normal to
Disable mode on bus activity wake-up, the module will
automatically enter into Normal mode and the first mes-
sage that caused the module to wake-up is lost. The
module will not generate any error frame. Firmware
logic must detect this condition and make sure that
retransmission is requested. If the processor receives
a wake-up interrupt while it is sleeping, more than one
message may get lost. The actual number of messages
lost would depend on the processor oscillator start-up
time and incoming message bit rate.
23.3.1
CONFIGURATION MODE
The CAN module has to be initialized before the
activation. This is only possible if the module is in the
Configuration mode. The Configuration mode is
requested by setting the REQOP2 bit. Only when the
status bit, OPMODE2, has a high level can the initial-
ization be performed. Afterwards, the Configuration
registers, the Acceptance Mask registers and the
Acceptance Filter registers can be written. The module
is activated by setting the REQOP control bits to zero.
The module will protect the user from accidentally
violating the CAN protocol through programming
errors. All registers which control the configuration of
the module can not be modified while the module is on-
line. The CAN module will not be allowed to enter the
Configuration mode while a transmission or reception
is taking place. The Configuration mode serves as a
lock to protect the following registers:
The I/O pins will revert to normal I/O function when the
module is in the Disable mode.
23.3.3
NORMAL MODE
This is the standard operating mode of the
PIC18F2682/2685/4682/4685 devices. In this mode,
the device actively monitors all bus messages and gen-
erates Acknowledge bits, error frames, etc. This is also
the only mode in which the PIC18F2682/2685/4682/
4685 devices will transmit messages over the CAN
bus.
• Configuration Registers
• Functional Mode Selection Registers
• Bit Timing Registers
• Identifier Acceptance Filter Registers
• Identifier Acceptance Mask Registers
• Filter and Mask Control Registers
• Mask Selection Registers
In the Configuration mode, the module will not transmit
or receive. The error counters are cleared and the
interrupt flags remain unchanged. The programmer will
have access to Configuration registers that are access
restricted in other modes.
© 2007 Microchip Technology Inc.
Preliminary
DS39761B-page 325
PIC18F2682/2685/4682/4685
23.3.4
LISTEN ONLY MODE
23.4 ECAN Module Functional Modes
Listen Only mode provides
a
means for the
In addition to CAN modes of operation, the ECAN mod-
ule offers a total of 3 functional modes. Each of these
modes are identified as Mode 0, Mode 1 and Mode 2.
PIC18F2682/2685/4682/4685 devices to receive all
messages, including messages with errors. This mode
can be used for bus monitor applications or for
detecting the baud rate in ‘hot plugging’ situations. For
Auto-Baud Detection, it is necessary that there are at
least two other nodes which are communicating with
each other. The baud rate can be detected empirically
by testing different values until valid messages are
received. The Listen Only mode is a silent mode,
meaning no messages will be transmitted while in this
state, including error flags or Acknowledge signals. The
filters and masks can be used to allow only particular
messages to be loaded into the receive registers or the
filter masks can be set to all zeros to allow a message
with any identifier to pass. The error counters are reset
and deactivated in this state. The Listen Only mode is
activated by setting the mode request bits in the
CANCON register.
23.4.1
MODE 0 – LEGACY MODE
Mode 0 is designed to be fully compatible with CAN
modules used in PIC18CXX8 and PIC18FXX8 devices.
This is the default mode of operation on all Reset
conditions. As a result, module code written for the
PIC18XX8 CAN module may be used on the ECAN
module without any code changes.
The following is the list of resources available in Mode 0:
• Three transmit buffers: TXB0, TXB1 and TXB2
• Two receive buffers: RXB0 and RXB1
• Two acceptance masks, one for each receive
buffer: RXM0, RXM1
• Six acceptance filters, 2 for RXB0 and 4 for RXB1:
RXF0, RXF1, RXF2, RXF3, RXF4, RXF5
23.3.5
LOOPBACK MODE
23.4.2
MODE 1 – ENHANCED
LEGACY MODE
This mode will allow internal transmission of messages
from the transmit buffers to the receive buffers without
actually transmitting messages on the CAN bus. This
mode can be used in system development and testing.
In this mode, the ACK bit is ignored and the device will
allow incoming messages from itself, just as if they
were coming from another node. The Loopback mode
is a silent mode, meaning no messages will be
transmitted while in this state, including error flags or
Acknowledge signals. The TXCAN pin will revert to port
I/O while the device is in this mode. The filters and
masks can be used to allow only particular messages
to be loaded into the receive registers. The masks can
be set to all zeros to provide a mode that accepts all
messages. The Loopback mode is activated by setting
the mode request bits in the CANCON register.
Mode 1 is similar to Mode 0, with the exception that more
resources are available in Mode 1. There are
16 acceptance filter registers and two acceptance mask
registers. Acceptance Filter 15 can be used as either an
acceptance filter or an acceptance mask register. In
addition to three transmit and two receive buffers, there
are six more message buffers. One or more of these
additional buffers can be programmed as transmit or
receive buffers. These additional buffers can also be
programmed to automatically handle RTR messages.
Fourteen of sixteen acceptance filter registers can be
dynamically associated to any receive buffer and
acceptance mask register. One can use this capability
to associate more than one filter to any one buffer.
When a receive buffer is programmed to use standard
identifier messages, part of the full acceptance filter
register can be used as a data byte filter. The length of
the data byte filter is programmable from 0 to 18 bits.
This functionality simplifies implementation of high-level
protocols, such as the DeviceNet™ protocol.
23.3.6
ERROR RECOGNITION MODE
The module can be set to ignore all errors and receive
any message. In functional Mode 0, the Error Recogni-
tion mode is activated by setting the RXM<1:0> bits in
the RXBnCON registers to ‘11’. In this mode, the data
which is in the message assembly buffer until the error
time, is copied in the receive buffer and can be read via
the CPU interface.
The following is the list of resources available in Mode 1:
• Three transmit buffers: TXB0, TXB1 and TXB2
• Two receive buffers: RXB0 and RXB1
• Six buffers programmable as TX or RX: B0-B5
• Automatic RTR handling on B0-B5
• Sixteen dynamically assigned acceptance filters:
RXF0-RXF15
• Two dedicated acceptance mask registers;
RXF15 programmable as third mask:
RXM0-RXM1, RXF15
• Programmable data filter on standard identifier
messages: SDFLC
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Each receive buffer contains one control register
(RXBnCON), four identifier registers (RXBnSIDL,
RXBnSIDH, RXBnEIDL, RXBnEIDH), one data length
count register (RXBnDLC) and eight data byte registers
(RXBnDm).
23.4.3
MODE 2 – ENHANCED FIFO MODE
In Mode 2, two or more receive buffers are used to form
the receive FIFO (first in, first out) buffer. There is no
one-to-one relationship between the receive buffer and
acceptance filter registers. Any filter that is enabled and
linked to any FIFO receive buffer can generate
acceptance and cause FIFO to be updated.
There is also a separate Message Assembly Buffer
(MAB) which acts as an additional receive buffer. MAB
is always committed to receiving the next message
from the bus and is not directly accessible to user firm-
ware. The MAB assembles all incoming messages one
by one. A message is transferred to appropriate
receive buffers only if the corresponding acceptance
filter criteria is met.
FIFO length is user programmable, from 2-8 buffers
deep. FIFO length is determined by the very first
programmable buffer that is configured as a transmit
buffer. For example, if Buffer 2 (B2) is programmed as
a transmit buffer, FIFO consists of RXB0, RXB1, B0
and B1 – creating a FIFO length of 4. If all program-
mable buffers are configured as receive buffers, FIFO
will have the maximum length of 8.
23.5.3
PROGRAMMABLE TRANSMIT/
RECEIVE BUFFERS
The following is the list of resources available in Mode 2:
The ECAN module implements six new buffers: B0-B5.
These buffers are individually programmable as either
transmit or receive buffers. These buffers are available
only in Mode 1 and 2. As with dedicated transmit and
receive buffers, each of these programmable buffers
occupies 14 bytes of SRAM and are mapped into SFR
memory map.
• Three transmit buffers: TXB0, TXB1 and TXB2
• Two receive buffers: RXB0 and RXB1
• Six buffers programmable as TX or RX; receive
buffers form FIFO: B0-B5
• Automatic RTR handling on B0-B5
• Sixteen acceptance filters: RXF0-RXF15
Each buffer contains one control register (BnCON),
four identifier registers (BnSIDL, BnSIDH, BnEIDL,
BnEIDH), one data length count register (BnDLC) and
eight data byte registers (BnDm). Each of these regis-
ters contains two sets of control bits. Depending on
whether the buffer is configured as transmit or receive,
one would use the corresponding control bit set. By
default, all buffers are configured as receive buffers.
Each buffer can be individually configured as a transmit
or receive buffer by setting the corresponding TXENn
bit in the BSEL0 register.
• Two dedicated acceptance mask registers;
RXF15 programmable as third mask:
RXM0-RXM1, RXF15
• Programmable data filter on standard identifier
messages: SDFLC, useful for DeviceNet protocol
23.5 CAN Message Buffers
23.5.1
DEDICATED TRANSMIT BUFFERS
The PIC18F2682/2685/4682/4685 devices implement
three dedicated transmit buffers – TXB0, TXB1 and
TXB2. Each of these buffers occupies 14 bytes of
SRAM and are mapped into the SFR memory map.
These are the only transmit buffers available in
Mode 0. Mode 1 and 2 may access these and other
additional buffers.
When configured as transmit buffers, user firmware
may access transmit buffers in any order similar to
accessing dedicated transmit buffers. In receive config-
uration with Mode 1 enabled, user firmware may also
access receive buffers in any order required. But in
Mode 2, all receive buffers are combined to form a
single FIFO. Actual FIFO length is programmable by
user firmware. Access to FIFO must be done through
the FIFO Pointer bits (FP<4:0>) in the CANCON
register. It must be noted that there is no hardware
protection against out of order FIFO reads.
Each transmit buffer contains one control register
(TXBnCON), four identifier registers (TXBnSIDL,
TXBnSIDH, TXBnEIDL, TXBnEIDH), one data length
count register (TXBnDLC) and eight data byte registers
(TXBnDm).
23.5.2
DEDICATED RECEIVE BUFFERS
The PIC18F2682/2685/4682/4685 devices implement
two dedicated receive buffers – RXB0 and RXB1. Each
of these buffers occupies 14 bytes of SRAM and are
mapped into SFR memory map. These are the only
receive buffers available in Mode 0. Mode 1 and 2 may
access these and other additional buffers.
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Preliminary
DS39761B-page 327
PIC18F2682/2685/4682/4685
Setting the TXREQ bit does not initiate a message
transmission; it merely flags a message buffer as ready
for transmission. Transmission will start when the
device detects that the bus is available. The device will
then begin transmission of the highest priority message
that is ready.
23.5.4
PROGRAMMABLE AUTO-RTR
BUFFERS
In Mode 1 and 2, any of six programmable transmit/
receive buffers may be programmed to automatically
respond to predefined RTR messages without user
firmware intervention. Automatic RTR handling is
enabled by setting the TXnEN bit in the BSEL0 register
and the RTREN bit in the BnCON register. After this
setup, when an RTR request is received, the TXREQ
bit is automatically set and the current buffer content is
automatically queued for transmission as a RTR
response. As with all transmit buffers, once the TXREQ
bit is set, buffer registers become read-only and any
writes to them will be ignored.
When the transmission has completed successfully, the
TXREQ bit will be cleared, the TXBnIF bit will be set and
an interrupt will be generated if the TXBnIE bit is set.
If the message transmission fails, the TXREQ will remain
set, indicating that the message is still pending for trans-
mission and one of the following condition flags will be
set. If the message started to transmit but encountered
an error condition, the TXERR and the IRXIF bits will be
set and an interrupt will be generated. If the message lost
arbitration, the TXLARB bit will be set.
The following outlines the steps required to
automatically handle RTR messages:
1. Set buffer to Transmit mode by setting TXnEN
23.6.2
ABORTING TRANSMISSION
bit to ‘1’ in BSEL0 register.
The MCU can request to abort a message by clearing
the TXREQ bit associated with the corresponding
message buffer (TXBnCON<3> or BnCON<3>). Set-
ting the ABAT bit (CANCON<4>) will request an abort
of all pending messages. If the message has not yet
started transmission, or if the message started but is
interrupted by loss of arbitration or an error, the abort
will be processed. The abort is indicated when the
module sets the TXABT bit for the corresponding buffer
(TXBnCON<6> or BnCON<6>). If the message has
started to transmit, it will attempt to transmit the current
message fully. If the current message is transmitted
fully and is not lost to arbitration or an error, the TXABT
bit will not be set because the message was trans-
mitted successfully. Likewise, if a message is being
transmitted during an abort request and the message is
lost to arbitration or an error, the message will not be
retransmitted and the TXABT bit will be set, indicating
that the message was successfully aborted.
2. At least one acceptance filter must be
associated with this buffer and preloaded with
expected RTR identifier.
3. Bit RTREN in BnCON register must be set to ‘1’.
4. Buffer must be preloaded with the data to be
sent as a RTR response.
Normally, user firmware will keep buffer data registers
up to date. If firmware attempts to update the buffer
while an automatic RTR response is in the process of
transmission, all writes to buffers are ignored.
23.6 CAN Message Transmission
23.6.1
INITIATING TRANSMISSION
For the MCU to have write access to the message
buffer, the TXREQ bit must be clear, indicating that the
message buffer is clear of any pending message to be
transmitted. At a minimum, the SIDH, SIDL and DLC
registers must be loaded. If data bytes are present in
the message, the data registers must also be loaded. If
the message is to use extended identifiers, the
EIDH:EIDL registers must also be loaded and the
EXIDE bit set.
Once an abort is requested by setting the ABAT or
TXABT bits, it cannot be cleared to cancel the abort
request. Only CAN module hardware or a POR
condition can clear it.
To initiate message transmission, the TXREQ bit must
be set for each buffer to be transmitted. When TXREQ
is set, the TXABT, TXLARB and TXERR bits will be
cleared. To successfully complete the transmission,
there must be at least one node with matching baud
rate on the network.
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buffer with the highest priority will be sent first. If two
buffers have the same priority setting, the buffer with
23.6.3
TRANSMIT PRIORITY
prioritization within the
Transmit priority is
a
the highest buffer number will be sent first. There are
four levels of transmit priority. If TXP bits for a particular
message buffer are set to ‘11’, that buffer has the high-
est possible priority. If TXP bits for a particular message
buffer are set to ‘00’, that buffer has the lowest possible
priority.
PIC18F2682/2685/4682/4685 devices of the pending
transmittable messages. This is independent from and
not related to any prioritization implicit in the message
arbitration scheme built into the CAN protocol. Prior to
sending the SOF, the priority of all buffers that are
queued for transmission is compared. The transmit
FIGURE 23-2:
TRANSMIT BUFFERS
TXB0
TXB1
TXB2
TXB3 - TXB8
Message
Queue
Control
Transmit Byte Sequencer
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Preliminary
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PIC18F2682/2685/4682/4685
modes. Normally, these bits are set to ‘00’ to enable
23.7 Message Reception
reception of all valid messages as determined by the
appropriate acceptance filters. In this case, the deter-
mination of whether or not to receive standard or
extended messages is determined by the EXIDE bit in
the acceptance filter register. In Mode 0, if the RXM bits
are set to ‘01’ or ‘10’, the receiver will accept only
messages with standard or extended identifiers,
respectively. If an acceptance filter has the EXIDE bit
set such that it does not correspond with the RXM
mode, that acceptance filter is rendered useless. In
Mode 1 and 2, setting EXID in the SIDL Mask register
will ensure that only standard or extended identifiers
are received. These two modes of RXM bits can be
used in systems where it is known that only standard or
extended messages will be on the bus. If the RXM bits
are set to ‘11’ (RXM1 = 1in Mode 1 and 2), the buffer
will receive all messages regardless of the values of
the acceptance filters. Also, if a message has an error
before the end of frame, that portion of the message
assembled in the MAB before the error frame will be
loaded into the buffer. This mode may serve as a
valuable debugging tool for a given CAN network. It
should not be used in an actual system environment as
the actual system will always have some bus errors
and all nodes on the bus are expected to ignore them.
23.7.1 RECEIVING A MESSAGE
Of all receive buffers, the MAB is always committed to
receiving the next message from the bus. The MCU
can access one buffer while the other buffer is available
for message reception or holding a previously received
message.
Note:
The entire contents of the MAB are moved
into the receive buffer once a message is
accepted. This means that regardless of
the type of identifier (standard or
extended) and the number of data bytes
received, the entire receive buffer is over-
written with the MAB contents. Therefore,
the contents of all registers in the buffer
must be assumed to have been modified
when any message is received.
When a message is moved into either of the receive
buffers, the associated RXFUL bit is set. This bit must
be cleared by the MCU when it has completed process-
ing the message in the buffer in order to allow a new
message to be received into the buffer. This bit
provides a positive lockout to ensure that the firmware
has finished with the message before the module
attempts to load a new message into the receive buffer.
If the receive interrupt is enabled, an interrupt will be
generated to indicate that a valid message has been
received.
In Mode 1 and 2, when a programmable buffer is
configured as a transmit buffer and one or more
acceptance filters are associated with it, all incoming
messages matching this acceptance filter criteria will
be discarded. To avoid this scenario, user firmware
must make sure that there are no acceptance filters
associated with a buffer configured as a transmit buffer.
Once a message is loaded into any matching buffer,
user firmware may determine exactly what filter caused
this reception by checking the filter hit bits in the
RXBnCON or BnCON registers. In Mode 0,
FILHIT<3:0> of RXBnCON serve as filter hit bits. In
Mode 1 and 2, FILHIT<4:0> of BnCON serves as filter
hit bits. The same registers also indicate whether the
current message is an RTR frame or not. A received
message is considered a standard identifier message if
the EXID bit in the RXBnSIDL or the BnSIDL register is
cleared. Conversely, a set EXID bit indicates an
extended identifier message. If the received message
is a standard identifier message, user firmware needs
to read the SIDL and SIDH registers. In the case of an
extended identifier message, firmware should read the
SIDL, SIDH, EIDL and EIDH registers. If the RXBnDLC
or BnDLC register contain non-zero data count, user
firmware should also read the corresponding number of
data bytes by accessing the RXBnDm or the BnDm
registers. When a received message is an RTR and if
the current buffer is not configured for automatic RTR
handling, user firmware must take appropriate action
and respond manually.
23.7.2
RECEIVE PRIORITY
When in Mode 0, RXB0 is the higher priority buffer and
has two message acceptance filters associated with it.
RXB1 is the lower priority buffer and has four acceptance
filters associated with it. The lower number of acceptance
filters makes the match on RXB0 more restrictive and
implies a higher priority for that buffer. Additionally, the
RXB0CON register can be configured such that if RXB0
contains a valid message and another valid message is
received, an overflow error will not occur and the new
message will be moved into RXB1 regardless of the
acceptance criteria of RXB1. There are also two
programmable acceptance filter masks available, one for
each receive buffer (see Section 23.5 “CAN Message
Buffers”).
In Mode 1 and 2, there are a total of 16 acceptance
filters available and each can be dynamically assigned
to any of the receive buffers. A buffer with a lower
number has higher priority. Given this, if an incoming
message matches with two or more receive buffer
acceptance criteria, the buffer with the lower number
will be loaded with that message.
Each receive buffer contains RXM bits to set special
Receive modes. In Mode 0, RXM<1:0> bits in
RXBnCON define a total of four Receive modes. In
Mode 1 and 2, RXM1 bit, in combination with the EXID
mask and filter bit, define the same four Receive
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23.7.3
ENHANCED FIFO MODE
23.7.4
TIME-STAMPING
When configured for Mode 2, two of the dedicated
receive buffers in combination with one or more
programmable transmit/receive buffers, are used to
create a maximum of an 8-buffer deep FIFO buffer. In
this mode, there is no direct correlation between filters
and receive buffer registers. Any filter that has been
enabled can generate an acceptance. When a
message has been accepted, it is stored in the next
available Receive Buffer register and an Internal Write
Pointer is incremented. The FIFO can be a maximum
of 8 buffers deep. The entire FIFO must consist of con-
tiguous receive buffers. The FIFO head begins at
RXB0 buffer and its tail spans toward B5. The maxi-
mum length of the FIFO is limited by the presence or
absence of the first transmit buffer starting from B0. If a
buffer is configured as a transmit buffer, the FIFO
length is reduced accordingly. For instance, if B3 is
configured as a transmit buffer, the actual FIFO will
consist of RXB0, RXB1, B0, B1 and B2, a total of 5
buffers. If B0 is configured as a transmit buffer, the
FIFO length will be 2. If none of the programmable
buffers are configured as a transmit buffer, the FIFO will
be 8 buffers deep. A system that requires more transmit
buffers should try to locate transmit buffers at the very
end of B0-B5 buffers to maximize available FIFO
length.
The CAN module can be programmed to generate a
time-stamp for every message that is received. When
enabled, the module generates a capture signal for
CCP1, which in turn, captures the value of either
Timer1 or Timer3. This value can be used as the
message time-stamp.
To use the time-stamp capability, the CANCAP bit
(CIOCAN<4>) must be set. This replaces the capture
input for CCP1 with the signal generated from the CAN
module. In addition, CCP1CON<3:0> must be set to
‘0011’ to enable the CCP Special Event Trigger for
CAN events.
23.8 Message Acceptance Filters
and Masks
The message acceptance filters and masks are used to
determine if a message in the Message Assembly
Buffer should be loaded into any of the receive buffers.
Once a valid message has been received into the MAB,
the identifier fields of the message are compared to the
filter values. If there is a match, that message will be
loaded into the appropriate receive buffer. The filter
masks are used to determine which bits in the identifier
are examined with the filters. A truth table is shown
below in Table 23-2 that indicates how each bit in the
identifier is compared to the masks and filters to deter-
mine if a message should be loaded into a receive
buffer. The mask essentially determines which bits to
apply the acceptance filters to. If any mask bit is set to
a zero, then that bit will automatically be accepted
regardless of the filter bit.
When a message is received in FIFO mode, the inter-
rupt flag code bits (EICODE<4:0>) in the CANSTAT
register will have a value of ‘10000’, indicating the
FIFO has received a message. FIFO Pointer bits,
FP<3:0> in the CANCON register, point to the buffer
that contains data not yet read. The FIFO Pointer bits,
in this sense, serve as the FIFO Read Pointer. The user
should use FP bits and read corresponding buffer data.
When receive data is no longer needed, the RXFUL bit
in the current buffer must be cleared, causing FP<3:0>
to be updated by the module.
TABLE 23-2: FILTER/MASK TRUTH TABLE
Message
Identifier
bit n001
Accept or
Reject
bit n
Mask
bit n
Filter
bit n
To determine whether FIFO is empty or not, the user
may use FP<3:0> bits to access the RXFUL bit in the
current buffer. If RXFUL is cleared, the FIFO is consid-
ered to be empty. If it is set, the FIFO may contain one
or more messages. In Mode 2, the module also pro-
vides a bit called FIFO High Water Mark (FIFOWM) in
the ECANCON register. This bit can be used to cause
an interrupt whenever the FIFO contains only one or
four empty buffers. The FIFO high water mark interrupt
can serve as an early warning to a full FIFO condition.
0
1
1
1
1
x
0
0
1
1
x
0
1
0
1
Accept
Accept
Reject
Reject
Accept
Legend: x= don’t care
In Mode 0, acceptance filters RXF0 and RXF1 and filter
mask RXM0 are associated with RXB0. Filters RXF2,
RXF3, RXF4 and RXF5 and mask RXM1 are
associated with RXB1.
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Preliminary
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PIC18F2682/2685/4682/4685
In Mode 1 and 2, there are an additional 10 acceptance
filters, RXF6-RXF15, creating a total of 16 available
filters. RXF15 can be used either as an acceptance
filter or acceptance mask register. Each of these
acceptance filters can be individually enabled or
disabled by setting or clearing the RXFENn bit in the
RXFCONn register. Any of these 16 acceptance filters
can be dynamically associated with any of the receive
buffers. Actual association is made by setting appropri-
ate bits in the RXFBCONn register. Each RXFBCONn
register contains a nibble for each filter. This nibble can
be used to associate a specific filter to any of available
receive buffers. User firmware may associate more
than one filter to any one specific receive buffer.
The coding of the RXB0DBEN bit enables these three
bits to be used similarly to the FILHIT bits and to
distinguish a hit on filter RXF0 and RXF1, in either
RXB0 or after a rollover into RXB1.
• 111= Acceptance Filter 1 (RXF1)
• 110= Acceptance Filter 0 (RXF0)
• 001= Acceptance Filter 1 (RXF1)
• 000= Acceptance Filter 0 (RXF0)
If the RXB0DBEN bit is clear, there are six codes
corresponding to the six filters. If the RXB0DBEN bit is
set, there are six codes corresponding to the six filters,
plus two additional codes corresponding to RXF0 and
RXF1 filters, that rollover into RXB1.
In addition to dynamic filter to buffer association, in
Mode 1 and 2, each filter can also be dynamically
associated to available acceptance mask registers.
The FILn_m bits in the MSELn register can be used to
link a specific acceptance filter to an acceptance mask
register. As with filter to buffer association, one can
also associate more than one mask to a specific
acceptance filter.
In Mode 1 and 2, each buffer control register contains
5 bits of filter hit bits (FILHIT<4:0>). A binary value of ‘0’
indicates a hit from RXF0 and 15 indicates RXF15.
If more than one acceptance filter matches, the FILHIT
bits will encode the binary value of the lowest num-
bered filter that matched. In other words, if filter RXF2
and filter RXF4 match, FILHIT will be loaded with the
value for RXF2. This essentially prioritizes the
acceptance filters with a lower number filter having
higher priority. Messages are compared to filters in
ascending order of filter number.
When a filter matches and a message is loaded into the
receive buffer, the filter number that enabled the mes-
sage reception is loaded into the FILHIT bit(s). In
Mode 0 for RXB1, the RXB1CON register contains the
FILHIT<2:0> bits. They are coded as follows:
The mask and filter registers can only be modified
when the PIC18F2682/2685/4682/4685 devices are in
Configuration mode.
• 101= Acceptance Filter 5 (RXF5)
• 100= Acceptance Filter 4 (RXF4)
• 011= Acceptance Filter 3 (RXF3)
• 010= Acceptance Filter 2 (RXF2)
• 001= Acceptance Filter 1 (RXF1)
• 000= Acceptance Filter 0 (RXF0)
Note:
‘000’ and ‘001’ can only occur if the
RXB0DBEN bit is set in the RXB0CON
register, allowing RXB0 messages to
rollover into RXB1.
FIGURE 23-3:
MESSAGE ACCEPTANCE MASK AND FILTER OPERATION
Acceptance Filter Register
Acceptance Mask Register
RXFn
RXMn
0
0
RXMn
RxRqst
1
RXFn
1
RXFn
RXMn
n
n
Message Assembly Buffer
Identifier
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Preliminary
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The Nominal Bit Time can be thought of as being
divided into separate, non-overlapping time segments.
These segments (Figure 23-4) include:
23.9 Baud Rate Setting
All nodes on a given CAN bus must have the same
nominal bit rate. The CAN protocol uses Non-Return-
to-Zero (NRZ) coding which does not encode a clock
within the data stream. Therefore, the receive clock
must be recovered by the receiving nodes and
synchronized to the transmitter’s clock.
• Synchronization Segment (Sync_Seg)
• Propagation Time Segment (Prop_Seg)
• Phase Buffer Segment 1 (Phase_Seg1)
• Phase Buffer Segment 2 (Phase_Seg2)
As oscillators and transmission time may vary from
node to node, the receiver must have some type of
Phase Lock Loop (PLL) synchronized to data transmis-
sion edges to synchronize and maintain the receiver
clock. Since the data is NRZ coded, it is necessary to
include bit stuffing to ensure that an edge occurs at
least every six bit times to maintain the Digital Phase
Lock Loop (DPLL) synchronization.
The time segments (and thus the Nominal Bit Time) are
in turn made up of integer units of time called Time
Quanta or TQ (see Figure 23-4). By definition, the
Nominal Bit Time is programmable from a minimum of
8 TQ to a maximum of 25 TQ. Also by definition, the
minimum Nominal Bit Time is 1 μs, corresponding to a
maximum 1 Mb/s rate. The actual duration is given by
the following relationship.
The bit timing of the PIC18F2682/2685/4682/4685 is
implemented using a DPLL that is configured to syn-
chronize to the incoming data and provides the nominal
timing for the transmitted data. The DPLL breaks each
bit time into multiple segments made up of minimal
periods of time called the Time Quanta (TQ).
EQUATION 23-2:
Nominal Bit Time= TQ * (Sync_Seg + Prop_Seg +
Phase_Seg1 + Phase_Seg2)
The Time Quantum is a fixed unit derived from the
oscillator period. It is also defined by the programmable
baud rate prescaler, with integer values from 1 to 64, in
addition to a fixed divide-by-two for clock generation.
Mathematically, this is:
Bus timing functions executed within the bit time frame,
such as synchronization to the local oscillator, network
transmission delay compensation and sample point
positioning, are defined by the programmable bit timing
logic of the DPLL.
EQUATION 23-3:
All devices on the CAN bus must use the same bit rate.
However, all devices are not required to have the same
master oscillator clock frequency. For the different clock
frequencies of the individual devices, the bit rate has to
be adjusted by appropriately setting the baud rate
prescaler and number of Time Quanta in each segment.
TQ (μs) = (2 * (BRP + 1))/FOSC (MHz)
or
TQ (μs) = (2 * (BRP + 1)) * TOSC (μs)
where FOSC is the clock frequency, TOSC is the
corresponding oscillator period and BRP is an integer
(0 through 63) represented by the binary values of
BRGCON1<5:0>. The equation above refers to the
effective clock frequency used by the microcontroller. If,
for example, a 10 MHz crystal in HS mode is used, then
the FOSC = 10 MHz and TOSC = 100 ns. If the same
10 MHzcrystalisusedinHSPLLmode,thentheeffective
frequency is FOSC = 40 MHz and TOSC = 25 ns.
The Nominal Bit Rate is the number of bits transmitted
per second, assuming an ideal transmitter with an ideal
oscillator, in the absence of resynchronization. The
nominal bit rate is defined to be a maximum of 1 Mb/s.
The Nominal Bit Time is defined as:
EQUATION 23-1:
TBIT = 1/Nominal Bit Rate
FIGURE 23-4:
BIT TIME PARTITIONING
Input
Signal
Sync
Segment
Propagation
Segment
Phase
Segment 1
Phase
Segment 2
Bit
Time
Intervals
TQ
Sample Point
Nominal Bit Time
© 2007 Microchip Technology Inc.
Preliminary
DS39761B-page 333
PIC18F2682/2685/4682/4685
The CAN protocol uses a bit-stuffing technique that
inserts a bit of a given polarity following five bits with the
opposite polarity. This gives a total of 10 bits transmit-
ted without re-synchronization (compensation for jitter
or phase error).
23.9.1
EXTERNAL CLOCK, INTERNAL
CLOCK AND MEASURABLE JITTER
IN HSPLL-BASED OSCILLATORS
The microcontroller clock frequency generated from a
PLL circuit is subject to a jitter, also defined as Phase
Jitter or Phase Skew. For its PIC18 Enhanced micro-
controllers, Microchip specifies phase jitter (Pjitter) as
being 2% (Gaussian distribution, within 3 standard
deviations, see parameter F13 in Table 27-7) and Total
Given the random nature of the jitter error added, it can
be shown that the total error caused by the jitter tends
to cancel itself over time. For a period of 10 bits, it is
necessary to add only two jitter intervals to correct for
jitter-induced error: one interval in the beginning of the
10-bit period and another at the end. The overall effect
is shown in Figure 23-5.
Jitter (Tjitter) as being 2 * Pjitter
.
FIGURE 23-5:
EFFECTS OF PHASE JITTER ON THE MICROCONTROLLER CLOCK
AND CAN BIT TIME
Nominal Clock
Clock with Jitter
Phase Skew (Jitter)
CAN bit Jitter
CAN bit Time
with Jitter
Once these considerations are taken into account, it is
possible to show that the relation between the jitter and
the total frequency error can be defined as:
For example, assume a CAN bit rate of 125 Kb/s, which
gives an NBT of 8 μs. For a 16 MHz clock generated
from a 4x PLL, the jitter at this clock frequency is:
EQUATION 23-4:
EQUATION 23-5:
1
0.02
16×106
Tjitter
2 × Pjitter
-------------------
-----------------
2% ×
=
= 1.25ns
----------------------- -----------------------
=
Δf =
16 MHz
10 × NBT 10 × NBT
The resultant frequency error is:
where jitter is expressed in terms of time and NBT is the
Nominal Bit Time.
EQUATION 23-6:
2 × (1.25×10–9
)
= 3.125×10–5= 0.0031%
--------------------------------------
10 × (8×10–6
)
DS39761B-page 334
Preliminary
© 2007 Microchip Technology Inc.
PIC18F2682/2685/4682/4685
Table 23-3 shows the relation between the clock
This is clearly smaller than the expected drift of a crystal
oscillator, typically specified at 100 ppm or 0.01%. If we
add jitter to oscillator drift, we have a total frequency drift
of 0.0132%. The total oscillator frequency errors for
common clock frequencies and bit rates, including both
drift and jitter, are shown in Table 23-4.
generated by the PLL and the frequency error from jitter
(measured jitter-induced error of 2%, Gaussian distribu-
tion, within 3 standard deviations), as a percentage of
the nominal clock frequency.
TABLE 23-3: FREQUENCY ERROR FROM JITTER AT VARIOUS PLL GENERATED CLOCK SPEEDS
Frequency Error at Various Nominal Bit Times (Bit Rates)
PLL
Pjitter
Tjitter
8 μs
(125 Kb/s)
4 μs
(250 Kb/s)
2 μs
(500 Kb/s)
1 μs
(1 Mb/s)
Output
40 MHz
24 MHz
16 MHz
0.5 ns
0.83 ns
1.25 ns
1 ns
0.00125%
0.00209%
0.00313%
0.00250%
0.00418%
0.00625%
0.005%
0.008%
0.013%
0.01%
0.017%
0.025%
1.67 ns
2.5 ns
TABLE 23-4: TOTAL FREQUENCY ERROR AT VARIOUS PLL GENERATED CLOCK SPEEDS
(100 PPM OSCILLATOR DRIFT, INCLUDING ERROR FROM JITTER)
Frequency Error at Various Nominal Bit Times (Bit Rates)
Nominal PLL Output
8 μs
4 μs
2 μs
1 μs
(125 Kb/s)
(250 Kb/s)
(500 Kb/s)
(1 Mb/s)
40 MHz
24 MHz
16 MHz
0.01125%
0.01209%
0.01313%
0.01250%
0.01418%
0.01625%
0.015%
0.018%
0.023%
0.02%
0.027%
0.035%
© 2007 Microchip Technology Inc.
Preliminary
DS39761B-page 335
PIC18F2682/2685/4682/4685
23.9.2
TIME QUANTA
23.9.3
SYNCHRONIZATION SEGMENT
As already mentioned, the Time Quanta is a fixed unit
derived from the oscillator period and baud rate
prescaler. Its relationship to TBIT and the Nominal Bit
Rate is shown in Example 23-6.
This part of the bit time is used to synchronize the
various CAN nodes on the bus. The edge of the input
signal is expected to occur during the sync segment.
The duration is 1 TQ.
23.9.4
PROPAGATION SEGMENT
EXAMPLE 23-6:
CALCULATING TQ,
NOMINAL BIT RATE AND
NOMINAL BIT TIME
This part of the bit time is used to compensate for phys-
ical delay times within the network. These delay times
consist of the signal propagation time on the bus line
and the internal delay time of the nodes. The length of
the Propagation Segment can be programmed from
1 TQ to 8 TQ by setting the PRSEG2:PRSEG0 bits.
TQ (μs) = (2 * (BRP + 1))/FOSC (MHz)
TBIT (μs) = TQ (μs) * number of TQ per bit interval
Nominal Bit Rate (bits/s) = 1/TBIT
This frequency (FOSC) refers to the effective
frequency used. If, for example, a 10 MHz external
signal is used along with a PLL, then the effective
frequency will be 4 x 10 MHz which equals 40 MHz.
23.9.5
PHASE BUFFER SEGMENTS
The phase buffer segments are used to optimally
locate the sampling point of the received bit within the
nominal bit time. The sampling point occurs between
Phase Segment 1 and Phase Segment 2. These
segments can be lengthened or shortened by the
resynchronization process. The end of Phase Segment
1 determines the sampling point within a bit time.
Phase Segment 1 is programmable from 1 TQ to 8 TQ
in duration. Phase Segment 2 provides delay before
the next transmitted data transition and is also
programmable from 1 TQ to 8 TQ in duration. However,
due to IPT requirements, the actual minimum length of
Phase Segment 2 is 2 TQ, or it may be defined to be
equal to the greater of Phase Segment 1 or the
Information Processing Time (IPT). The sampling point
should be as late as possible or approximately 80% of
the bit time.
CASE 1:
For FOSC = 16 MHz, BRP<5:0> = 00h and
Nominal Bit Time = 8 TQ:
TQ = (2 * 1)/16 = 0.125 μs (125 ns)
TBIT = 8 * 0.125 = 1 μs (10-6s)
Nominal Bit Rate = 1/10-6 = 106 bits/s (1 Mb/s)
CASE 2:
For FOSC = 20 MHz, BRP<5:0> = 01h and
Nominal Bit Time = 8 TQ:
TQ = (2 * 2)/20 = 0.2 μs (200 ns)
TBIT = 8 * 0.2 = 1.6 μs (1.6 * 10-6s)
23.9.6
SAMPLE POINT
Nominal Bit Rate = 1/1.6 * 10-6s = 625,000 bits/s
The sample point is the point of time at which the bus
level is read and the value of the received bit is
determined. The sampling point occurs at the end of
Phase Segment 1. If the bit timing is slow and contains
many TQ, it is possible to specify multiple sampling of
the bus line at the sample point. The value of the
received bit is determined to be the value of the major-
ity decision of three values. The three samples are
taken at the sample point and twice before, with a time
of TQ/2 between each sample.
(625 Kb/s)
CASE 3:
For FOSC = 25 MHz, BRP<5:0> = 3Fh and
Nominal Bit Time = 25 TQ:
TQ = (2 * 64)/25 = 5.12 μs
TBIT = 25 * 5.12 = 128 μs (1.28 * 10-4s)
Nominal Bit Rate = 1/1.28 * 10-4
=
7813 bits/s
(7.8 Kb/s)
23.9.7
INFORMATION PROCESSING TIME
The Information Processing Time (IPT) is the time
segment starting at the sample point that is reserved
for calculation of the subsequent bit level. The CAN
specification defines this time to be less than or equal
to 2 TQ. The PIC18F2682/2685/4682/4685 devices
define this time to be 2 TQ. Thus, Phase Segment 2
must be at least 2 TQ long.
The frequencies of the oscillators in the different nodes
must be coordinated in order to provide a system wide
specified nominal bit time. This means that all oscilla-
tors must have a TOSC that is an integral divisor of TQ.
It should also be noted that although the number of TQ
is programmable from 4 to 25, the usable minimum is
8 TQ. There is no assurance that a bit time of less than
8 TQ in length will operate correctly.
DS39761B-page 336
Preliminary
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The phase error of an edge is given by the position of
the edge relative to Sync_Seg, measured in TQ. The
phase error is defined in magnitude of TQ as follows:
23.10 Synchronization
To compensate for phase shifts between the oscillator
frequencies of each of the nodes on the bus, each CAN
controller must be able to synchronize to the relevant
signal edge of the incoming signal. When an edge in
the transmitted data is detected, the logic will compare
the location of the edge to the expected time
(Sync_Seg). The circuit will then adjust the values of
Phase Segment 1 and Phase Segment 2 as necessary.
There are two mechanisms used for synchronization.
• e = 0 if the edge lies within Sync_Seg.
• e > 0 if the edge lies before the sample point.
• e < 0 if the edge lies after the sample point of the
previous bit.
If the magnitude of the phase error is less than, or equal
to, the programmed value of the Synchronization Jump
Width, the effect of a resynchronization is the same as
that of a hard synchronization.
23.10.1 HARD SYNCHRONIZATION
If the magnitude of the phase error is larger than the
Synchronization Jump Width and if the phase error is
positive, then Phase Segment 1 is lengthened by an
amount equal to the Synchronization Jump Width.
Hard synchronization is only done when there is a
recessive to dominant edge during a bus Idle condition,
indicating the start of a message. After hard synchroni-
zation, the bit time counters are restarted with
Sync_Seg. Hard synchronization forces the edge
which has occurred to lie within the synchronization
segment of the restarted bit time. Due to the rules of
synchronization, if a hard synchronization occurs, there
will not be a resynchronization within that bit time.
If the magnitude of the phase error is larger than the
resynchronization jump width and if the phase error is
negative, then Phase Segment 2 is shortened by an
amount equal to the Synchronization Jump Width.
23.10.3 SYNCHRONIZATION RULES
23.10.2 RESYNCHRONIZATION
• Only one synchronization within one bit time is
allowed.
As a result of resynchronization, Phase Segment 1
may be lengthened or Phase Segment 2 may be short-
ened. The amount of lengthening or shortening of the
phase buffer segments has an upper bound given by
the Synchronization Jump Width (SJW). The value of
the SJW will be added to Phase Segment 1 (see
Figure 23-6) or subtracted from Phase Segment 2 (see
Figure 23-7). The SJW is programmable between 1 TQ
and 4 TQ.
• An edge will be used for synchronization only if
the value detected at the previous sample point
(previously read bus value) differs from the bus
value immediately after the edge.
• All other recessive to dominant edges fulfilling
rules 1 and 2 will be used for resynchronization,
with the exception that a node transmitting a
dominant bit will not perform a resynchronization
as a result of a recessive to dominant edge with a
positive phase error.
Clocking information will only be derived from
recessive to dominant transitions. The property, that
only a fixed maximum number of successive bits have
the same value, ensures resynchronization to the bit
stream during a frame.
FIGURE 23-6:
LENGTHENING A BIT PERIOD (ADDING SJW TO PHASE SEGMENT 1)
Input
Signal
Bit
Prop
Segment
Phase
Segment 1
Phase
Segment 2
Time
Sync
≤ SJW
Segments
TQ
Sample Point
Nominal Bit Length
Actual Bit Length
© 2007 Microchip Technology Inc.
Preliminary
DS39761B-page 337
PIC18F2682/2685/4682/4685
FIGURE 23-7:
SHORTENING A BIT PERIOD (SUBTRACTING SJW FROM PHASE SEGMENT 2)
Prop
Segment
Phase
Segment 1
Phase
Segment 2
Sync
≤ SJW
TQ
Sample Point
Actual Bit Length
Nominal Bit Length
23.11 Programming Time Segments
23.13 Bit Timing Configuration
Registers
Some requirements for programming of the time
segments:
The Baud Rate Control registers (BRGCON1,
BRGCON2, BRGCON3) control the bit timing for the
CAN bus interface. These registers can only be
modified when the PIC18F2682/2685/4682/4685
devices are in Configuration mode.
• Prop_Seg + Phase_Seg 1 ≥ Phase_Seg 2
• Phase_Seg 2 ≥ Sync Jump Width.
For example, assume that a 125 kHz CAN baud rate is
desired, using 20 MHz for FOSC. With a TOSC of 50 ns,
a baud rate prescaler value of 04h gives a TQ of 500 ns.
To obtain a Nominal Bit Rate of 125 kHz, the Nominal
Bit Time must be 8 μs or 16 TQ.
23.13.1 BRGCON1
The BRP bits control the baud rate prescaler. The
SJW<1:0> bits select the synchronization jump width in
terms of multiples of TQ.
Using 1 TQ for the Sync_Seg, 2 TQ for the Prop_Seg
and 7 TQ for Phase Segment 1 would place the sample
point at 10 TQ after the transition. This leaves 6 TQ for
Phase Segment 2.
23.13.2 BRGCON2
The PRSEG bits set the length of the propagation seg-
ment in terms of TQ. The SEG1PH bits set the length of
Phase Segment 1 in TQ. The SAM bit controls how
many times the RXCAN pin is sampled. Setting this bit
to a ‘1’ causes the bus to be sampled three times: twice
at TQ/2 before the sample point and once at the normal
sample point (which is at the end of Phase Segment 1).
The value of the bus is determined to be the value read
during at least two of the samples. If the SAM bit is set
to a ‘0’, then the RXCAN pin is sampled only once at
the sample point. The SEG2PHTS bit controls how the
length of Phase Segment 2 is determined. If this bit is
set to a ‘1’, then the length of Phase Segment 2 is
determined by the SEG2PH bits of BRGCON3. If the
SEG2PHTS bit is set to a ‘0’, then the length of Phase
Segment 2 is the greater of Phase Segment 1 and the
Information Processing Time (which is fixed at 2 TQ for
the PIC18F2682/2685/4682/4685).
By the rules above, the Sync Jump Width could be the
maximum of 4 TQ. However, normally a large SJW is
only necessary when the clock generation of the differ-
ent nodes is inaccurate or unstable, such as using
ceramic resonators. Typically, an SJW of 1 is enough.
23.12 Oscillator Tolerance
As a rule of thumb, the bit timing requirements allow
ceramic resonators to be used in applications with
transmission rates of up to 125 Kbit/sec. For the full bus
speed range of the CAN protocol, a quartz oscillator is
required. A maximum node-to-node oscillator variation
of 1.7% is allowed.
23.13.3 BRGCON3
The PHSEG2<2:0> bits set the length (in TQ) of Phase
Segment 2 if the SEG2PHTS bit is set to a ‘1’. If the
SEG2PHTS bit is set to a ‘0’, then the PHSEG2<2:0>
bits have no effect.
DS39761B-page 338
Preliminary
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23.14.6 ERROR STATES
23.14 Error Detection
Detected errors are made public to all other nodes via
The CAN protocol provides sophisticated error
detection mechanisms. The following errors can be
detected.
error frames. The transmission of the erroneous
message is aborted and the frame is repeated as soon
as possible. Furthermore, each CAN node is in one of
the three error states: “error-active”, “error-passive” or
“bus-off”, according to the value of the internal error
counters. The error-active state is the usual state
where the bus node can transmit messages and
activate error frames (made of dominant bits) without
any restrictions. In the error-passive state, messages
and passive error frames (made of recessive bits) may
be transmitted. The bus-off state makes it temporarily
impossible for the station to participate in the bus
communication. During this state, messages can
neither be received nor transmitted.
23.14.1 CRC ERROR
With the Cyclic Redundancy Check (CRC), the trans-
mitter calculates special check bits for the bit
sequence, from the start of a frame until the end of the
data field. This CRC sequence is transmitted in the
CRC field. The receiving node also calculates the CRC
sequence using the same formula and performs a
comparison to the received sequence. If a mismatch is
detected, a CRC error has occurred and an error frame
is generated. The message is repeated.
23.14.2 ACKNOWLEDGE ERROR
23.14.7 ERROR MODES AND ERROR
COUNTERS
In the Acknowledge field of a message, the transmitter
checks if the Acknowledge slot (which was sent out as
a recessive bit) contains a dominant bit. If not, no other
node has received the frame correctly. An Acknowl-
edge error has occurred, an error frame is generated
and the message will have to be repeated.
The PIC18F2682/2685/4682/4685 devices contain two
error counters: the Receive Error Counter (RXERRCNT)
and the Transmit Error Counter (TXERRCNT). The
values of both counters can be read by the MCU. These
counters are incremented or decremented in
accordance with the CAN bus specification.
23.14.3 FORM ERROR
The PIC18F2682/2685/4682/4685 devices are error-
active if both error counters are below the error-passive
limit of 128. They are error-passive if at least one of the
error counters equals or exceeds 128. They go to bus-
off if the transmit error counter equals or exceeds the
bus-off limit of 256. The devices remain in this state
until the bus-off recovery sequence is received. The
bus-off recovery sequence consists of 128 occurrences
of 11 consecutive recessive bits (see Figure 23-8).
Note that the CAN module, after going bus-off, will
recover back to error-active without any intervention by
the MCU if the bus remains Idle for 128 x 11 bit times.
If this is not desired, the error Interrupt Service Routine
should address this. The current Error mode of the
CAN module can be read by the MCU via the
COMSTAT register.
If a node detects a dominant bit in one of the four
segments, including End-of-Frame, interframe space,
Acknowledge delimiter or CRC delimiter, then a form
error has occurred and an error frame is generated.
The message is repeated.
23.14.4 BIT ERROR
A bit error occurs if a transmitter sends a dominant bit
and detects a recessive bit, or if it sends a recessive bit
and detects a dominant bit, when monitoring the actual
bus level and comparing it to the just transmitted bit. In
the case where the transmitter sends a recessive bit
and a dominant bit is detected during the arbitration
field and the Acknowledge slot, no bit error is
generated because normal arbitration is occurring.
Additionally, there is an Error State Warning flag bit,
EWARN, which is set if at least one of the error
counters equals or exceeds the error warning limit of
96. EWARN is reset if both error counters are less than
the error warning limit.
23.14.5 STUFF BIT ERROR
lf, between the Start-of-Frame and the CRC delimiter,
six consecutive bits with the same polarity are
detected, the bit stuffing rule has been violated. A stuff
bit error occurs and an error frame is generated. The
message is repeated.
© 2007 Microchip Technology Inc.
Preliminary
DS39761B-page 339
PIC18F2682/2685/4682/4685
FIGURE 23-8:
ERROR MODES STATE DIAGRAM
Reset
Error
Active
-
RXERRCNT < 127 or
TXERRCNT < 127
128 occurrences of
11 consecutive
“recessive” bits
RXERRCNT > 127 or
TXERRCNT > 127
Error
-
Passive
TXERRCNT > 255
Bus-
Off
The interrupts can be broken up into two categories:
receive and transmit interrupts.
23.15 CAN Interrupts
The module has several sources of interrupts. Each of
these interrupts can be individually enabled or
disabled. The PIR3 register contains interrupt flags.
The PIE3 register contains the enables for the 8 main
interrupts. A special set of read-only bits in the
CANSTAT register, the ICODE bits, can be used in
combination with a jump table for efficient handling of
interrupts.
The receive related interrupts are:
• Receive Interrupts
• Wake-up Interrupt
• Receiver Overrun Interrupt
• Receiver Warning Interrupt
• Receiver Error-Passive Interrupt
The transmit related interrupts are:
All interrupts have one source, with the exception of the
error interrupt and buffer interrupts in Mode 1 and 2. Any
of the error interrupt sources can set the error interrupt
flag. The source of the error interrupt can be determined
by reading the Communication Status register,
COMSTAT. In Mode 1 and 2, there are two interrupt
enable/disable and flag bits – one for all transmit buffers
and the other for all receive buffers.
• Transmit Interrupts
• Transmitter Warning Interrupt
• Transmitter Error-Passive Interrupt
• Bus-Off Interrupt
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Preliminary
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In Mode 0, the RXBnIF bit is set to indicate the source
of the interrupt. The interrupt is cleared by the MCU,
resetting the RXBnIF bit to a ‘0’.
23.15.1 INTERRUPT CODE BITS
To simplify the interrupt handling process in user firm-
ware, the ECAN module encodes a special set of bits. In
Mode 0, these bits are ICODE<3:1> in the CANSTAT
register. In Mode 1 and 2, these bits are EICODE<4:0> in
the CANSTAT register. Interrupts are internally prioritized
such that the higher priority interrupts are assigned lower
values. Once the highest priority interrupt condition has
been cleared, the code for the next highest priority inter-
rupt that is pending (if any) will be reflected by the ICODE
bits (see Table 23-5). Note that only those interrupt
sources that have their associated interrupt enable bit set
will be reflected in the ICODE bits.
In Mode 1 and 2, all receive buffers share RXBIE,
RXBIF and RXBIP in PIE3, PIR3 and IPR3, respec-
tively. Bits RXBnIE, RXBnIF and RXBnIP are not used.
Individual receive buffer interrupts can be controlled by
the TXBIE and BIE0 registers. In Mode 1, when a
shared receive interrupt occurs, user firmware must
poll the RXFUL bit of each receive buffer to detect the
source of interrupt. In Mode 2, a receive interrupt
indicates that the new message is loaded into FIFO.
FIFO can be read by using FIFO Pointer bits, FP.
In Mode 2, when a receive message interrupt occurs,
the EICODE bits will always consist of ‘10000’. User
firmware may use FIFO Pointer bits to actually access
the next available buffer.
TABLE 23-5: VALUES FOR ICODE<3:1>
ICODE
Interrupt
Boolean Expression
<2:0>
000
None ERR•WAK•TX0•TX1•TX2•RX0•RX1
Error ERR
23.15.2 TRANSMIT INTERRUPT
When the transmit interrupt is enabled, an interrupt will
be generated when the associated transmit buffer
becomes empty and is ready to be loaded with a new
message. In Mode 0, there are separate interrupt
enable/disable and flag bits for each of the three dedi-
cated transmit buffers. The TXBnIF bit will be set to indi-
cate the source of the interrupt. The interrupt is cleared
by the MCU, resetting the TXBnIF bit to a ‘0’. In Mode 1
and 2, all transmit buffers share one interrupt enable/
disable bit and one flag bit. In Mode 1 and 2, TXBnIE in
PIE3 and TXBnIF in PIR3 indicate when a transmit
buffer has completed transmission of its message. TXB-
nIF, TXBnIE and TXBnIP in PIR3, PIE3 and IPR3,
respectively, are not used in Mode 1 and 2. Individual
transmit buffer interrupts can be enabled or disabled by
setting or clearing TXBIE and BIE0 register bits. When a
shared interrupt occurs, user firmware must poll the
TXREQ bit of all transmit buffers to detect the source of
interrupt.
001
010
011
100
101
110
TXB2 ERR•TX0•TX1•TX2
TXB1 ERR•TX0•TX1
TXB0 ERR•TX0
RXB1 ERR•TX0•TX1•TX2•RX0•RX1
RXB0 ERR•TX0•TX1•TX2•RX0
111 Wake on ERR•TX0•TX1•TX2•RX0•RX1•WAK
Interrupt
Legend:
ERR = ERRIF * ERRIE RX0 = RXB0IF * RXB0IE
TX0 = TXB0IF * TXB0IE RX1 = RXB1IF * RXB1IE
TX1 = TXB1IF * TXB1IE WAK = WAKIF * WAKIE
TX2 = TXB2IF * TXB2IE
23.15.3 RECEIVE INTERRUPT
23.15.4 MESSAGE ERROR INTERRUPT
When the receive interrupt is enabled, an interrupt will
be generated when a message has been successfully
received and loaded into the associated receive buffer.
This interrupt is activated immediately after receiving
the End-Of-Frame (EOF) field.
When an error occurs during transmission or reception
of a message, the message error flag, IRXIF, will be set
and if the IRXIE bit is set, an interrupt will be generated.
This is intended to be used to facilitate baud rate
determination when used in conjunction with Listen
Only mode.
© 2007 Microchip Technology Inc.
Preliminary
DS39761B-page 341
PIC18F2682/2685/4682/4685
23.15.5 BUS ACTIVITY WAKE-UP
INTERRUPT
23.15.6.3 Transmitter Warning
The transmit error counter has reached the MCU
warning limit of 96.
When the PIC18F2682/2685/4682/4685 devices are in
Sleep mode and the bus activity wake-up interrupt is
enabled, an interrupt will be generated and the WAKIF
bit will be set when activity is detected on the CAN bus.
This interrupt causes the PIC18F2682/2685/4682/
4685 devices to exit Sleep mode. The interrupt is reset
by the MCU, clearing the WAKIF bit.
23.15.6.4 Receiver Bus Passive
The receive error counter has exceeded the error-
passive limit of 127 and the device has gone to
error-passive state.
23.15.6.5 Transmitter Bus Passive
23.15.6 ERROR INTERRUPT
The transmit error counter has exceeded the error-
passive limit of 127 and the device has gone to
error-passive state.
When the error interrupt is enabled, an interrupt is
generated if an overflow condition occurs or if the error
state of the transmitter or receiver has changed. The
error flags in COMSTAT will indicate one of the
following conditions.
23.15.6.6 Bus-Off
The transmit error counter has exceeded 255 and the
device has gone to bus-off state.
23.15.6.1 Receiver Overflow
An overflow condition occurs when the MAB has
assembled a valid received message (the message
meets the criteria of the acceptance filters) and the
receive buffer associated with the filter is not available
for loading of a new message. The associated
RXBnOVFL bit in the COMSTAT register will be set to
indicate the overflow condition. This bit must be cleared
by the MCU.
23.15.6.7 Interrupt Acknowledge
Interrupts are directly associated with one or more
status flags in the PIR register. Interrupts are pending
as long as one of the flags is set. Once an interrupt flag
is set by the device, the flag can not be reset by the
microcontroller until the interrupt condition is removed.
23.15.6.2 Receiver Warning
The receive error counter has reached the MCU
warning limit of 96.
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Preliminary
© 2007 Microchip Technology Inc.
PIC18F2682/2685/4682/4685
The inclusion of an internal RC oscillator also provides
24.0 SPECIAL FEATURES OF THE
the additional benefits of a Fail-Safe Clock Monitor
(FSCM) and Two-Speed Start-up. FSCM provides for
background monitoring of the peripheral clock and
automatic switchover in the event of its failure. Two-
Speed Start-up enables code to be executed almost
immediately on start-up, while the primary clock source
completes its start-up delays.
CPU
PIC18F2682/2685/4682/4685 devices include several
features intended to maximize reliability and minimize
cost through elimination of external components.
These are:
• Oscillator Selection
• Resets:
All of these features are enabled and configured by
setting the appropriate Configuration register bits.
- Power-on Reset (POR)
- Power-up Timer (PWRT)
- Oscillator Start-up Timer (OST)
- Brown-out Reset (BOR)
• Interrupts
24.1 Configuration Bits
The Configuration bits can be programmed (read as
‘0’) or left unprogrammed (read as ‘1’) to select various
device configurations. These bits are mapped starting
at program memory location 300000h.
• Watchdog Timer (WDT)
• Fail-Safe Clock Monitor
• Two-Speed Start-up
• Code Protection
The user will note that address 300000h is beyond the
user program memory space. In fact, it belongs to the
configuration memory space (300000h-3FFFFFh), which
can only be accessed using table reads and table writes.
• ID Locations
• In-Circuit Serial Programming
Programming the Configuration registers is done in a
manner similar to programming the Flash memory. The
WR bit in the EECON1 register starts a self-timed write
to the Configuration register. In normal operation mode,
a TBLWT instruction with the TBLPTR pointing to the
Configuration register sets up the address and the data
for the Configuration register write. Setting the WR bit
starts a long write to the Configuration register. The
Configuration registers are written a byte at a time. To
write or erase a configuration cell, a TBLWTinstruction
can write a ‘1’ or a ‘0’ into the cell. For additional details
on Flash programming, refer to Section 6.5 “Writing
to Flash Program Memory”.
The oscillator can be configured for the application
depending on frequency, power, accuracy and cost. All
of the options are discussed in detail in Section 2.0
“Oscillator Configurations”.
A complete discussion of device Resets and interrupts
is available in previous sections of this data sheet.
In addition to their Power-up and Oscillator Start-up
Timers provided for Resets, PIC18F2682/2685/4682/
4685 devices have a Watchdog Timer, which is either
permanently enabled via the Configuration bits or
software controlled (if configured as disabled).
TABLE 24-1: CONFIGURATION BITS AND DEVICE IDs
Default/
Unprogrammed
Value
File Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
300001h CONFIG1H
300002h CONFIG2L
300003h CONFIG2H
IESO
—
FCMEN
—
—
—
—
—
FOSC3
FOSC2
FOSC1
FOSC0
00-- 0111
---1 1111
---1 1111
1--- -01-
1000 -1-1
--11 1111
11-- ----
--11 1111
111- ----
--11 1111
-1-- ----
—
—
—
BORV1
BORV0 BOREN1 BOREN0 PWRTEN
—
WDTPS3 WDTPS2 WDTPS1 WDTPS0 WDTEN
300005h CONFIG3H MCLRE
—
—
—
LPT1OSC PBADEN
—
STVREN
CP0
300006h CONFIG4L DEBUG XINST BBSIZ1 BBSIZ2
LVP
CP2
—
—
CP1
—
(1)
300008h CONFIG5L
300009h CONFIG5H
30000Ah CONFIG6L
—
CPD
—
—
CPB
—
CP5
—
CP4
—
CP3
—
—
(1)
WRT5
WRT4
—
WRT3
—
WRT2
—
WRT1
—
WRT0
—
30000Bh CONFIG6H WRTD
WRTB
—
WRTC
(1)
30000Ch CONFIG7L
30000Dh CONFIG7H
3FFFFEh DEVID1
3FFFFFh DEVID2
—
—
EBTR5
—
EBTR4
—
EBTR3
—
EBTR2
—
EBTR1
—
EBTR0
—
EBTRB
DEV1
DEV9
(2)
DEV2
DEV10
DEV0
DEV8
REV4
DEV7
REV3
DEV6
REV2
DEV5
REV1
DEV4
REV0
DEV3
xxxx xxxx
(2)
xxxx xxxx
Legend: x= unknown, u= unchanged, - = unimplemented, q= value depends on condition. Shaded cells are unimplemented, read as ‘0’.
Note 1: Unimplemented in PIC18F2682/4682 devices; maintain this bIt set.
2: See Register 24-12 and Register 24-13 for DEVID1 and DEVID2 values. DEVID registers are read-only and cannot be
programmed by the user.
© 2007 Microchip Technology Inc.
Preliminary
DS39761B-page 343
PIC18F2682/2685/4682/4685
REGISTER 24-1: CONFIG1H: CONFIGURATION REGISTER 1 HIGH (BYTE ADDRESS 300001h)
R/P-0
IESO
R/P-0
U-0
—
U-0
—
R/P-0
R/P-1
R/P-1
R/P-1
FCMEN
FOSC3
FOSC2
FOSC1
FOSC0
bit 7
bit 0
Legend:
R = Readable bit
P = Programmable bit
U = Unimplemented bit, read as ‘0’
-n = Value when device is unprogrammed
u = Unchanged from programmed state
bit 7
bit 6
IESO: Internal/External Oscillator Switchover bit
1= Oscillator Switchover mode enabled
0= Oscillator Switchover mode disabled
FCMEN: Fail-Safe Clock Monitor Enable bit
1= Fail-Safe Clock Monitor enabled
0= Fail-Safe Clock Monitor disabled
bit 5-4
bit 3-0
Unimplemented: Read as ‘0’
FOSC3:FOSC0: Oscillator Selection bits
11xx= External RC oscillator, CLKO function on RA6
101x= External RC oscillator, CLKO function on RA6
1001= Internal oscillator block, CLKO function on RA6, port function on RA7
1000= Internal oscillator block, port function on RA6 and RA7
0111= External RC oscillator, port function on RA6
0110= HS oscillator, PLL enabled (Clock Frequency = 4 x FOSC1)
0101= EC oscillator, port function on RA6
0100= EC oscillator, CLKO function on RA6
0011= External RC oscillator, CLKO function on RA6
0010= HS oscillator
0001= XT oscillator
0000= LP oscillator
DS39761B-page 344
Preliminary
© 2007 Microchip Technology Inc.
PIC18F2682/2685/4682/4685
REGISTER 24-2: CONFIG2L: CONFIGURATION REGISTER 2 LOW (BYTE ADDRESS 300002h)
U-0
—
U-0
—
U-0
—
R/P-1
R/P-1
R/P-1
BOREN1(1)
R/P-1
R/P-1
BORV1
BORV0
BOREN0(1) PWRTEN(1)
bit 7
bit 0
Legend:
R = Readable bit
P = Programmable bit
U = Unimplemented bit, read as ‘0’
-n = Value when device is unprogrammed
u = Unchanged from programmed state
bit 7-5
bit 4-3
Unimplemented: Read as ‘0’
BORV1:BORV0: Brown-out Reset Voltage bits
11= Minimum setting
.
.
.
00= Maximum setting
bit 2-1
bit 0
BOREN1:BOREN0: Brown-out Reset Enable bits(1)
11= Brown-out Reset enabled in hardware only (SBOREN is disabled)
10= Brown-out Reset enabled in hardware only and disabled in Sleep mode (SBOREN is disabled)
01= Brown-out Reset enabled and controlled by software (SBOREN is enabled)
00= Brown-out Reset disabled in hardware and software
PWRTEN: Power-up Timer Enable bit(1)
1= PWRT disabled
0= PWRT enabled
Note 1: The Power-up Timer is decoupled from Brown-out Reset, allowing these features to be independently
controlled.
© 2007 Microchip Technology Inc.
Preliminary
DS39761B-page 345
PIC18F2682/2685/4682/4685
REGISTER 24-3: CONFIG2H: CONFIGURATION REGISTER 2 HIGH (BYTE ADDRESS 300003h)
U-0
—
U-0
—
U-0
—
R/P-1
R/P-1
R/P-1
R/P-1
R/P-1
WDTPS3
WDTPS2
WDTPS1
WDTPS0
WDTEN
bit 7
bit 0
Legend:
R = Readable bit
P = Programmable bit
U = Unimplemented bit, read as ‘0’
-n = Value when device is unprogrammed
u = Unchanged from programmed state
bit 7-5
bit 4-1
Unimplemented: Read as ‘0’
WDTPS3:WDTPS0: Watchdog Timer Postscale Select bits
1111= 1:32,768
1110= 1:16,384
1101= 1:8,192
1100= 1:4,096
1011= 1:2,048
1010= 1:1,024
1001= 1:512
1000= 1:256
0111= 1:128
0110= 1:64
0101= 1:32
0100= 1:16
0011= 1:8
0010= 1:4
0001= 1:2
0000= 1:1
bit 0
WDTEN: Watchdog Timer Enable bit
1= WDT enabled
0= WDT disabled (control is placed on the SWDTEN bit)
DS39761B-page 346
Preliminary
© 2007 Microchip Technology Inc.
PIC18F2682/2685/4682/4685
REGISTER 24-4: CONFIG3H: CONFIGURATION REGISTER 3 HIGH (BYTE ADDRESS 300005h)
R/P-1
U-0
—
U-0
—
U-0
—
U-0
—
R/P-0
R/P-1
U-0
—
MCLRE
LPT1OSC
PBADEN
bit 7
bit 0
Legend:
R = Readable bit
P = Programmable bit
U = Unimplemented bit, read as ‘0’
-n = Value when device is unprogrammed
u = Unchanged from programmed state
bit 7
MCLRE: MCLR Pin Enable bit
1= MCLR pin enabled; RE3 input pin disabled
0= RE3 input pin enabled; MCLR disabled
bit 6-3
bit 2
Unimplemented: Read as ‘0’
LPT1OSC: Low-Power Timer1 Oscillator Enable bit
1= Timer1 configured for low-power operation
0= Timer1 configured for higher power operation
bit 1
PBADEN: PORTB A/D Enable bit
(Affects ADCON1 Reset state. ADCON1 controls PORTB<4:0> pin configuration.)
1= PORTB<4:0> pins are configured as analog input channels on Reset
0= PORTB<4:0> pins are configured as digital I/O on Reset
bit 0
Unimplemented: Read as ‘0’
REGISTER 24-5: CONFIG4L: CONFIGURATION REGISTER 4 LOW (BYTE ADDRESS 300006h)
R/P-1
R/P-0
R/P-0
R/P-0
U-0
—
R/P-1
LVP
U-0
—
R/P-1
DEBUG
XINST
BBSIZ1
BBSIZ2
STVREN
bit 7
bit 0
Legend:
R = Readable bit
P = Programmable bit
U = Unimplemented bit, read as ‘0’
-n = Value when device is unprogrammed
u = Unchanged from programmed state
bit 7
bit 6
bit 5
bit 4
DEBUG: Background Debugger Enable bit
1= Background debugger disabled, RB6 and RB7 configured as general purpose I/O pins
0= Background debugger enabled, RB6 and RB7 are dedicated to In-Circuit Debug
XINST: Extended Instruction Set Enable bit
1= Instruction set extension and Indexed Addressing mode enabled
0= Instruction set extension and Indexed Addressing mode disabled (Legacy mode)
BBSIZ1: Boot Block Size Select Bit 1
11= 4K words (8 Kbytes) boot block
10= 4K words (8 Kbytes) boot block
BBSIZ2: Boot Block Size Select Bit 0
01= 2K words (4 Kbytes) boot block
00= 1K words (2 Kbytes) boot block
bit 3
bit 2
Unimplemented: Read as ‘0’
LVP: Single-Supply ICSP™ Enable bit
1= Single-Supply ICSP enabled
0= Single-Supply ICSP disabled
bit 1
bit 0
Unimplemented: Read as ‘0’
STVREN: Stack Full/Underflow Reset Enable bit
1= Stack full/underflow will cause Reset
0= Stack full/underflow will not cause Reset
© 2007 Microchip Technology Inc.
Preliminary
DS39761B-page 347
PIC18F2682/2685/4682/4685
REGISTER 24-6: CONFIG5L: CONFIGURATION REGISTER 5 LOW (BYTE ADDRESS 300008h)
U-0
—
U-0
—
R/C-1
CP5(1)
R/C-1
CP4
R/C-1
CP3
R/C-1
CP2
R/C-1
CP1
R/C-1
CP0
bit 7
bit 0
Legend:
R = Readable bit
C = Clearable bit
U = Unimplemented bit, read as ‘0’
-n = Value when device is unprogrammed
u = Unchanged from programmed state
bit 7-6
bit 5
Unimplemented: Read as ‘0’
CP5: Code Protection bit(1)
1= Block 5 (014000-017FFFh) not code-protected
0= Block 5 (014000-017FFFh) code-protected
bit 4
bit 3
bit 2
bit 1
bit 0
CP4: Code Protection bit
1= Block 4 (010000-013FFFh) not code-protected
0= Block 4 (010000-013FFFh) code-protected
CP3: Code Protection bit
1= Block 3 (00C000-00FFFFh) not code-protected
0= Block 3 (00C000-00FFFFh) code-protected
CP2: Code Protection bit
1= Block 2 (008000-00BFFFh) not code-protected
0= Block 2 (008000-00BFFFh) code-protected
CP1: Code Protection bit
1= Block 1 (004000-007FFFh) not code-protected
0= Block 1 (004000-007FFFh) code-protected
CP0: Code Protection bit
1= Block 0 (000800-003FFFh) not code-protected
0= Block 0 (000800-003FFFh) code-protected
Note 1: Unimplemented in PIC18F2682/4682 devices; maintain this bit set.
REGISTER 24-7: CONFIG5H: CONFIGURATION REGISTER 5 HIGH (BYTE ADDRESS 300009h)
R/C-1
CPD
R/C-1
CPB
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
bit 7
bit 0
Legend:
R = Readable bit
C = Clearable bit
U = Unimplemented bit, read as ‘0’
-n = Value when device is unprogrammed
u = Unchanged from programmed state
bit 7
CPD: Data EEPROM Code Protection bit
1= Data EEPROM not code-protected
0= Data EEPROM code-protected
bit 6
CPB: Boot Block Code Protection bit
1= Boot Block (000000-0007FFh) not code-protected
0= Boot Block (000000-0007FFh) code-protected
bit 5-0
Unimplemented: Read as ‘0’
DS39761B-page 348
Preliminary
© 2007 Microchip Technology Inc.
PIC18F2682/2685/4682/4685
REGISTER 24-8: CONFIG6L: CONFIGURATION REGISTER 6 LOW (BYTE ADDRESS 30000Ah)
U-0
—
U-0
—
R/C-1
WRT5(1)
R/C-1
WRT4
R/C-1
WRT3
R/C-1
WRT2
R/C-1
WRT1
R/C-1
WRT0
bit 7
bit 0
Legend:
R = Readable bit
C = Clearable bit
U = Unimplemented bit, read as ‘0’
-n = Value when device is unprogrammed
u = Unchanged from programmed state
bit 7-6
bit 5
Unimplemented: Read as ‘0’
WRT5: Write Protection bit(1)
1= Block 5 (014000-017FFFh) not write-protected
0= Block 5 (014000-017FFFh) write-protected
bit 4
bit 3
bit 2
bit 1
bit 0
WRT4: Write Protection bit
1= Block 4 (010000-013FFFh) not write-protected
0= Block 4 (010000-013FFFh) write-protected
WRT3: Write Protection bit
1= Block 3 (00C000-00FFFFh) not write-protected
0= Block 3 (00C000-00FFFFh) write-protected
WRT2: Write Protection bit
1= Block 2 (008000-00BFFFh) not write-protected
0= Block 2 (008000-00BFFFh) write-protected
WRT1: Write Protection bit
1= Block 1 (004000-007FFFh) not write-protected
0= Block 1 (004000-007FFFh) write-protected
WRT0: Write Protection bit
1= Block 0 (000800-003FFFh) not write-protected
0= Block 0 (000800-003FFFh) write-protected
Note 1: Unimplemented in PIC18F2682/4682 devices; maintain this bit set.
© 2007 Microchip Technology Inc.
Preliminary
DS39761B-page 349
PIC18F2682/2685/4682/4685
REGISTER 24-9: CONFIG6H: CONFIGURATION REGISTER 6 HIGH (BYTE ADDRESS 30000Bh)
R/C-1
R/C-1
R-1
WRTC(1)
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
WRTD
WRTB
bit 7
bit 0
Legend:
R = Readable bit
C = Clearable bit
U = Unimplemented bit, read as ‘0’
-n = Value when device is unprogrammed
u = Unchanged from programmed state
bit 7
WRTD: Data EEPROM Write Protection bit
1= Data EEPROM not write-protected
0= Data EEPROM write-protected
bit 6
WRTB: Boot Block Write Protection bit
1= Boot Block (000000-0007FFh) not write-protected
0= Boot Block (000000-0007FFh) write-protected
bit 5
WRTC: Configuration Register Write Protection bit(1)
1= Configuration registers (300000-3000FFh) not write-protected
0= Configuration registers (300000-3000FFh) write-protected
bit 4-0
Unimplemented: Read as ‘0’
Note 1: This bit is read-only in normal execution mode; it can be written only in Program mode.
DS39761B-page 350
Preliminary
© 2007 Microchip Technology Inc.
PIC18F2682/2685/4682/4685
REGISTER 24-10: CONFIG7L: CONFIGURATION REGISTER 7 LOW (BYTE ADDRESS 30000Ch)
U-0
—
U-0
—
R/C-1
EBTR5(1)
R/C-1
R/C-1
R/C-1
R/C-1
R/C-1
EBTR4
EBTR3
EBTR2
EBTR1
EBTR0
bit 7
bit 0
Legend:
R = Readable bit
C = Clearable bit
U = Unimplemented bit, read as ‘0’
-n = Value when device is unprogrammed
u = Unchanged from programmed state
bit 7-6
bit 5
Unimplemented: Read as ‘0’
EBTR5: Table Read Protection bit(1)
1= Block 5 (014000-017FFFh) not protected from table reads executed in other blocks
0= Block 5 (014000-017FFFh) protected from table reads executed in other blocks
bit 4
bit 3
bit 2
bit 1
bit 0
EBTR4: Table Read Protection bit
1= Block 4 (010000-013FFFh) not protected from table reads executed in other blocks
0= Block 4 (010000-013FFFh) protected from table reads executed in other blocks
EBTR3: Table Read Protection bit
1= Block 3 (00C000-00FFFFh) not protected from table reads executed in other blocks
0= Block 3 (00C000-00FFFFh) protected from table reads executed in other blocks
EBTR2: Table Read Protection bit(1)
1= Block 2 (008000-00BFFFh) not protected from table reads executed in other blocks
0= Block 2 (008000-00BFFFh) protected from table reads executed in other blocks
EBTR1: Table Read Protection bit
1= Block 1 (004000-007FFFh) not protected from table reads executed in other blocks
0= Block 1 (004000-007FFFh) protected from table reads executed in other blocks
EBTR0: Table Read Protection bit
1= Block 0 (000800-003FFFh) not protected from table reads executed in other blocks
0= Block 0 (000800-003FFFh) protected from table reads executed in other blocks
Note 1: Unimplemented in PIC18F2682/4682 devices; maintain this bit set.
REGISTER 24-11: CONFIG7H: CONFIGURATION REGISTER 7 HIGH (BYTE ADDRESS 30000Dh)
U-0
—
R/C-1
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
EBTRB
bit 7
bit 0
Legend:
R = Readable bit
C = Clearable bit
U = Unimplemented bit, read as ‘0’
-n = Value when device is unprogrammed
u = Unchanged from programmed state
bit 7
bit 6
Unimplemented: Read as ‘0’
EBTRB: Boot Block Table Read Protection bit
1= Boot Block (000000-0007FFh) not protected from table reads executed in other blocks
0= Boot Block (000000-0007FFh) protected from table reads executed in other blocks
bit 5-0
Unimplemented: Read as ‘0’
© 2007 Microchip Technology Inc.
Preliminary
DS39761B-page 351
PIC18F2682/2685/4682/4685
REGISTER 24-12: DEVID1: DEVICE ID REGISTER 1 FOR PIC18F2682/2685/4682/4685
R
R
R
R
R
R
R
R
DEV2
DEV1
DEV0
REV4
REV3
REV2
REV1
REV0
bit 7
bit 0
Legend:
R = Read-only bit
P = Programmable bit
U = Unimplemented bit, read as ‘0’
-n = Value when device is unprogrammed
u = Unchanged from programmed state
bit 7-5
bit 4-0
DEV2:DEV0: Device ID bits
000= PIC18F2682
001= PIC18F2685
010= PIC18F4682
011= PIC18F4685
REV3:REV0: Revision ID bits
These bits are used to indicate the device revision.
REGISTER 24-13: DEVID2: DEVICE ID REGISTER 2 FOR PIC18F2682/2685/4682/4685
R
R
R
R
R
R
R
R
DEV10
DEV9
DEV8
DEV7
DEV6
DEV5
DEV4
DEV3
bit 7
bit 0
Legend:
R = Read-only bit
P = Programmable bit
U = Unimplemented bit, read as ‘0’
-n = Value when device is unprogrammed
u = Unchanged from programmed state
bit 7-0 DEV10:DEV3: Device ID bits
These bits are used with the DEV2:DEV0 bits in Device ID Register 1 to identify the part number.
0010 0111= PIC18F2682/2685/4682/4685 devices
Note 1: These values for DEV10:DEV3 may be shared with other devices. The specific device is always identified
by using the entire DEV10:DEV0 bit sequence.
DS39761B-page 352
Preliminary
© 2007 Microchip Technology Inc.
PIC18F2682/2685/4682/4685
24.2 Watchdog Timer (WDT)
Note 1: The CLRWDT and SLEEP instructions
clear the WDT and postscaler counts
when executed.
For PIC18F2682/2685/4682/4685 devices, the WDT is
driven by the INTRC source. When the WDT is
enabled, the clock source is also enabled. The nominal
WDT period is 4 ms and has the same stability as the
INTRC oscillator.
2: Changing the setting of the IRCF bits
(OSCCON<6:4>) clears the WDT and
postscaler counts.
The 4 ms period of the WDT is multiplied by a 16-bit
postscaler. Any output of the WDT postscaler is
selected by a multiplexer, controlled by bits in Configu-
ration Register 2H. Available periods range from 4 ms
to 131.072 seconds (2.18 minutes). The WDT and
postscaler are cleared when any of the following events
occur: a SLEEPor CLRWDTinstruction is executed, the
IRCF bits (OSCCON<6:4>) are changed or a clock
failure has occurred.
3: When a CLRWDTinstruction is executed,
the postscaler count will be cleared.
24.2.1
CONTROL REGISTER
Register 24-14 shows the WDTCON register. This is a
readable and writable register which contains a control
bit that allows software to override the WDT enable
Configuration bit, but only if the Configuration bit has
disabled the WDT.
.
FIGURE 24-1:
WDT BLOCK DIAGRAM
Enable WDT
SWDTEN
WDTEN
INTRC Control
WDT Counter
Wake-up from
Power-Managed
÷128
INTRC Source
Modes
Change on IRCF bits
CLRWDT
WDT
Reset
Reset
Programmable Postscaler
1:1 to 1:32,768
All Device Resets
WDT
4
WDTPS<3:0>
Sleep
© 2007 Microchip Technology Inc.
Preliminary
DS39761B-page 353
PIC18F2682/2685/4682/4685
REGISTER 24-14: WDTCON: WATCHDOG TIMER CONTROL REGISTER
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
R/W-0
SWDTEN(1)
bit 0
bit 7
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7-1
bit 0
Unimplemented: Read as ‘0’
SWDTEN: Software Controlled Watchdog Timer Enable bit(1)
1= Watchdog Timer is on
0= Watchdog Timer is off
Note 1: This bit has no effect if the Configuration bit, WDTEN, is enabled.
TABLE 24-2: SUMMARY OF WATCHDOG TIMER REGISTERS
Reset
Values
on page
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
RCON
WDTCON
IPEN
—
SBOREN
—
—
—
RI
—
TO
—
PD
—
POR
—
BOR
48
SWDTEN
50
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the Watchdog Timer.
DS39761B-page 354
Preliminary
© 2007 Microchip Technology Inc.
PIC18F2682/2685/4682/4685
Reset. For wake-ups from Sleep, the INTOSC or
postscaler clock sources can be selected by setting the
IRCF2:IRCF0 bits prior to entering Sleep mode.
24.3 Two-Speed Start-up
The Two-Speed Start-up feature helps to minimize the
latency period from oscillator start-up to code execution
by allowing the microcontroller to use the INTRC
oscillator as a clock source until the primary clock
source is available. It is enabled by setting the IESO
Configuration bit.
In all other power-managed modes, Two-Speed Start-up
is not used. The device will be clocked by the currently
selected clock source until the primary clock source
becomes available. The setting of the IESO bit is
ignored.
Two-Speed Start-up should be enabled only if the
primary oscillator mode is LP, XT, HS or HSPLL
(Crystal-based modes). Other sources do not require
an OST start-up delay; for these, Two-Speed Start-up
should be disabled.
24.3.1
SPECIAL CONSIDERATIONS FOR
USING TWO-SPEED START-UP
While using the INTRC oscillator in Two-Speed Start-up,
the device still obeys the normal command sequences
for entering power-managed modes, including serial
SLEEP instructions (refer to Section 3.1.4 “Multiple
Sleep Commands”). In practice, this means that user
code can change the SCS1:SCS0 bit settings or issue
SLEEPinstructions before the OST times out. This would
allow an application to briefly wake-up, perform routine
“housekeeping” tasks and return to Sleep before the
device starts to operate from the primary oscillator.
When enabled, Resets and wake-ups from Sleep mode
cause the device to configure itself to run from the
internal oscillator block as the clock source, following
the time-out of the Power-up Timer after a Power-on
Reset is enabled. This allows almost immediate code
execution while the primary oscillator starts and the
OST is running. Once the OST times out, the device
automatically switches to PRI_RUN mode.
Because the OSCCON register is cleared on Reset
events, the INTOSC (or postscaler) clock source is not
initially available after a Reset event; the INTRC clock
is used directly at its base frequency. To use a higher
clock speed on wake-up, the INTOSC or postscaler
clock sources can be selected to provide a higher clock
speed by setting bits, IRCF2:IRCF0, immediately after
User code can also check if the primary clock source is
currently providing the device clocking by checking the
status of the OSTS bit (OSCCON<3>). If the bit is set,
the primary oscillator is providing the clock. Otherwise,
the internal oscillator block is providing the clock during
wake-up from Reset or Sleep mode.
FIGURE 24-2:
TIMING TRANSITION FOR TWO-SPEED START-UP (INTOSC TO HSPLL)
Q3
Q4
Q1
Q2 Q3 Q4 Q1 Q2 Q3
Q1
Q2
INTOSC
Multiplexer
OSC1
(1)
(1)
TOST
TPLL
1
2
n-1
n
PLL Clock
Output
Clock
Transition
CPU Clock
Peripheral
Clock
Program
Counter
PC
PC + 2
PC + 4
PC + 6
Wake from Interrupt Event
Note 1: TOST = 1024 TOSC; TPLL = 2 ms (approx). These intervals are not shown to scale.
OSTS bit Set
© 2007 Microchip Technology Inc.
Preliminary
DS39761B-page 355
PIC18F2682/2685/4682/4685
To use a higher clock speed on wake-up, the INTOSC
24.4 Fail-Safe Clock Monitor
or postscaler clock sources can be selected to provide
a higher clock speed by setting bits, IRCF2:IRCF0,
immediately after Reset. For wake-ups from Sleep, the
INTOSC or postscaler clock sources can be selected
by setting the IRCF2:IRCF0 bits prior to entering Sleep
mode.
The Fail-Safe Clock Monitor (FSCM) allows the
microcontroller to continue operation in the event of an
external oscillator failure by automatically switching the
device clock to the internal oscillator block. The FSCM
function is enabled by setting the FCMEN
Configuration bit.
The FSCM will detect failures of the primary or second-
ary clock sources only. If the internal oscillator block
fails, no failure would be detected, nor would any action
be possible.
When FSCM is enabled, the INTRC oscillator runs at
all times to monitor clocks to peripherals and provide a
backup clock in the event of a clock failure. Clock
monitoring (shown in Figure 24-3) is accomplished by
creating a sample clock signal, which is the INTRC out-
put divided by 64. This allows ample time between
FSCM sample clocks for a peripheral clock edge to
occur. The peripheral device clock and the sample
clock are presented as inputs to the Clock Monitor latch
(CM). The CM is set on the falling edge of the device
clock source, but cleared on the rising edge of the
sample clock.
24.4.1
FSCM AND THE WATCHDOG TIMER
Both the FSCM and the WDT are clocked by the
INTRC oscillator. Since the WDT operates with a
separate divider and counter, disabling the WDT has
no effect on the operation of the INTRC oscillator when
the FSCM is enabled.
As already noted, the clock source is switched to the
INTOSC clock when a clock failure is detected.
Depending on the frequency selected by the
IRCF2:IRCF0 bits, this may mean a substantial change
in the speed of code execution. If the WDT is enabled
with a small prescale value, a decrease in clock speed
allows a WDT time-out to occur and a subsequent
device Reset. For this reason, fail-safe clock events
also reset the WDT and postscaler, allowing it to start
timing from when execution speed was changed and
decreasing the likelihood of an erroneous time-out.
FIGURE 24-3:
FSCM BLOCK DIAGRAM
Clock Monitor
Latch (CM)
(edge-triggered)
Peripheral
Clock
S
C
Q
Q
INTRC
Source
÷ 64
24.4.2
EXITING FAIL-SAFE OPERATION
488 Hz
(2.048 ms)
(32 μs)
The fail-safe condition is terminated by either a device
Reset or by entering a power-managed mode. On
Reset, the controller starts the primary clock source
specified in Configuration Register 1H (with any
required start-up delays that are required for the
oscillator mode, such as OST or PLL timer). The
INTOSC multiplexer provides the device clock until the
primary clock source becomes ready (similar to a Two-
Speed Start-up). The clock source is then switched to
the primary clock (indicated by the OSTS bit in the
OSCCON register becoming set). The Fail-Safe Clock
Monitor then resumes monitoring the peripheral clock.
Clock
Failure
Detected
Clock failure is tested for on the falling edge of the
sample clock. If a sample clock falling edge occurs
while CM is still set, a clock failure has been detected
(Figure 24-4). This causes the following:
• the FSCM generates an oscillator fail interrupt by
setting bit, OSCFIF (PIR2<7>);
• the device clock source is switched to the internal
oscillator block (OSCCON is not updated to show
the current clock source – this is the fail-safe
condition); and
The primary clock source may never become ready
during start-up. In this case, operation is clocked by the
INTOSC multiplexer. The OSCCON register will remain
in its Reset state until a power-managed mode is
entered.
• the WDT is reset.
During switchover, the postscaler frequency from the
internal oscillator block may not be sufficiently stable for
timing sensitive applications. In these cases, it may be
desirable to select another clock configuration and enter
an alternate power-managed mode. This can be done to
attempt a partial recovery or execute a controlled shut-
down. See Section 3.1.4 “Multiple Sleep Commands”
and Section 24.3.1 “Special Considerations for
Using Two-Speed Start-up” for more details.
DS39761B-page 356
Preliminary
© 2007 Microchip Technology Inc.
PIC18F2682/2685/4682/4685
FIGURE 24-4:
FSCM TIMING DIAGRAM
Sample Clock
Oscillator
Failure
Device
Clock
Output
CM Output
(Q)
Failure
Detected
OSCFIF
CM Test
CM Test
CM Test
Note:
The device clock is normally at a much higher frequency than the sample clock. The relative frequencies in this
example have been chosen for clarity.
time considerably longer than the FCSM sample clock
time, a false clock failure may be detected. To prevent
this, the internal oscillator block is automatically config-
ured as the device clock and functions until the primary
clock is stable (the OST and PLL timers have timed
out). This is identical to Two-Speed Start-up mode.
Once the primary clock is stable, the INTRC returns to
its role as the FSCM source.
24.4.3
FSCM INTERRUPTS IN
POWER-MANAGED MODES
By entering a power-managed mode, the clock
multiplexer selects the clock source selected by the
OSCCON register. Fail-Safe Monitoring of the power-
managed clock source resumes in the power-managed
mode.
If an oscillator failure occurs during power-managed
operation, the subsequent events depend on whether
or not the oscillator failure interrupt is enabled. If
enabled (OSCFIF = 1), code execution will be clocked
by the INTOSC multiplexer. An automatic transition
back to the failed clock source will not occur.
Note:
The same logic that prevents false oscilla-
tor failure interrupts on POR, or wake from
Sleep, will also prevent the detection of
the oscillator’s failure to start at all follow-
ing these events. This can be avoided by
monitoring the OSTS bit and using a
timing routine to determine if the oscillator
is taking too long to start. Even so, no
oscillator failure interrupt will be flagged.
If the interrupt is disabled, subsequent interrupts while
in Idle mode will cause the CPU to begin executing
instructions while being clocked by the INTOSC
source.
As noted in Section 24.3.1 “Special Considerations
for Using Two-Speed Start-up”, it is also possible to
select another clock configuration and enter an alternate
power-managed mode while waiting for the primary
clock to become stable. When the new power-managed
mode is selected, the primary clock is disabled.
24.4.4
POR OR WAKE-UP FROM SLEEP
The FSCM is designed to detect oscillator failure at any
point after the device has exited Power-on Reset
(POR) or low-power Sleep mode. When the primary
device clock is EC, RC or INTRC, monitoring can begin
immediately following these events.
For oscillator modes involving a crystal or resonator
(HS, HSPLL, LP or XT), the situation is somewhat
different. Since the oscillator may require a start-up
© 2007 Microchip Technology Inc.
Preliminary
DS39761B-page 357
PIC18F2682/2685/4682/4685
Each of the five blocks has three code protection bits
associated with them. They are:
24.5 Program Verification and
Code Protection
• Code-Protect bit (CPn)
The overall structure of the code protection on the
PIC18 Flash devices differs significantly from other PIC
devices.
• Write-Protect bit (WRTn)
• External Block Table Read bit (EBTRn)
Figure 24-5 shows the program memory organization
for 80- and 96-Kbyte devices and the specific code
protection bit associated with each block. The actual
locations of the bits are summarized in Table 24-3.
The user program memory is divided into five blocks.
One of these is a boot block of 2 Kbytes. The remainder
of the memory is divided into four blocks on binary
boundaries.
FIGURE 24-5:
CODE-PROTECTED PROGRAM MEMORY FOR PIC18F2682/2685/4682/4685
MEMORY SIZE/DEVICE
Block Code Protection
80 Kbytes
(PIC18F2682/4682)
96 Kbytes
(PIC18F2685/4685)
Address
Range
Controlled By:
CPB, WRTB, EBTRB
CP0, WRT0, EBTR0
000000h
0007FFh
Boot Block
Boot Block
Block 0
000800h
Block 0
Block 1
Block 2
Block 3
Block 4
003FFFh
004000h
Block 1
Block 2
Block 3
Block 4
Block 5
CP1, WRT1, EBTR1
CP2, WRT2, EBTR2
CP3, WRT3, EBTR3
CP4, WRT4, EBTR4
CP5, WRT5, EBTR5
007FFFh
008000h
00BFFFh
00C000h
00FFFFh
010000h
013FFFh
014000h
Unimplemented
Read ‘0’s
017FFFh
018000h
Unimplemented
Unimplemented
Read ‘0’s
Read ‘0’s
(Unimplemented Memory Space)
1FFFFFh
DS39761B-page 358
Preliminary
© 2007 Microchip Technology Inc.
PIC18F2682/2685/4682/4685
TABLE 24-3: SUMMARY OF CODE PROTECTION REGISTERS
File Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
300008h
CONFIG5L
CONFIG5H
CONFIG6L
—
CPD
—
—
CPB
—
CP5(1)
CP4
—
CP3
—
CP2
—
CP1
—
CP0
—
300009h
30000Ah
30000Bh
30000Ch
30000Dh
—
WRT5(1)
WRTC
EBTR5(1) EBTR4
WRT4
—
WRT3
—
WRT2
—
WRT1
—
WRT0
—
CONFIG6H WRTD
WRTB
—
CONFIG7L
CONFIG7H
—
—
EBTR3
—
EBTR2
—
EBTR1
—
EBTR0
—
EBTRB
—
—
Legend: Shaded cells are unimplemented.
Note 1: Unimplemented in PIC18F2682/4682 devices; maintain this bit set.
A table read instruction that executes from a location
outside of that block is not allowed to read and will
result in reading ‘0’s. Figures 24-6 through 24-8
illustrate table write and table read protection.
24.5.1
PROGRAM MEMORY
CODE PROTECTION
The program memory may be read to or written from
any location using the table read and table write
instructions. The Device ID may be read with table
reads. The Configuration registers may be read and
written with the table read and table write instructions.
Note:
Code protection bits may only be written to
a ‘0’ from a ‘1’ state. It is not possible to
write a ‘1’ to a bit in the ‘0’ state. Code
protection bits are only set to ‘1’ by a full
Chip Erase or Block Erase function. The
full Chip Erase and Block Erase functions
can only be initiated via ICSP or an
external programmer.
In normal execution mode, the CPn bits have no direct
effect. CPn bits inhibit external reads and writes. A
block of user memory may be protected from table
writes if the WRTn Configuration bit is ‘0’. The EBTRn
bits control table reads. For a block of user memory
with the EBTRn bit set to ‘0’, a table read instruction
that executes from within that block is allowed to read.
© 2007 Microchip Technology Inc.
Preliminary
DS39761B-page 359
PIC18F2682/2685/4682/4685
FIGURE 24-6:
TABLE WRITE (WRTn) DISALLOWED
Register Values
Program Memory
Configuration Bit Settings
000000h
WRTB, EBTRB = 11
0007FFh
000800h
TBLPTR = 0008FFh
WRT0, EBTR0 = 01
PC = 003FFEh
TBLWT*
TBLWT*
003FFFh
004000h
WRT1, EBTR1 = 11
WRT2, EBTR2 = 11
007FFFh
008000h
PC = 00BFFEh
00BFFFh
00C000h
WRT3, EBTR3 = 11
WRT4, EBTR3 = 11
00FFFFh
010000h
013FFFh
014000h
WRT5, EBTR3 = 11
017FFFh
Results: All table writes disabled to Blockn whenever WRTn = 0.
FIGURE 24-7:
EXTERNAL BLOCK TABLE READ (EBTRn) DISALLOWED
Register Values
Program Memory
Configuration Bit Settings
000000h
WRTB, EBTRB = 11
0007FFh
000800h
TBLPTR = 0008FFh
PC = 007FFEh
WRT0, EBTR0 = 01
003FFFh
004000h
TBLRD*
WRT1, EBTR1 = 11
WRT2, EBTR2 = 11
007FFFh
008000h
00BFFFh
00C000h
WRT3, EBTR3 = 11
WRT4, EBTR3 = 11
00FFFFh
010000h
013FFFh
014000h
WRT5, EBTR3 = 11
017FFFh
Results: All table reads from external blocks to Blockn are disabled whenever EBTRn = 0.
TABLAT register returns a value of ‘0’.
DS39761B-page 360
Preliminary
© 2007 Microchip Technology Inc.
PIC18F2682/2685/4682/4685
FIGURE 24-8:
EXTERNAL BLOCK TABLE READ (EBTRn) ALLOWED
Program Memory Configuration Bit Settings
Register Values
000000h
WRTB, EBTRB = 11
0007FFh
000800h
TBLPTR = 0008FFh
PC = 003FFEh
WRT0, EBTR0 = 01
TBLRD*
003FFFh
004000h
WRT1, EBTR1 = 11
WRT2, EBTR2 = 11
007FFFh
008000h
00BFFFh
00C000h
WRT3, EBTR3 = 11
WRT4, EBTR3 = 11
00FFFFh
010000h
013FFFh
014000h
WRT5, EBTR3 = 11
017FFFh
Results: Table reads permitted within Blockn, even when EBTRBn = 0.
TABLAT register returns the value of the data at the location TBLPTR.
© 2007 Microchip Technology Inc.
Preliminary
DS39761B-page 361
PIC18F2682/2685/4682/4685
To use the In-Circuit Debugger function of the micro-
controller, the design must implement In-Circuit Serial
Programming connections to MCLR/VPP/RE3, VDD,
VSS, RB7 and RB6. This will interface to the In-Circuit
Debugger module available from Microchip or one of
the third party development tool companies.
24.5.2
DATA EEPROM
CODE PROTECTION
The entire data EEPROM is protected from external
reads and writes by two bits: CPD and WRTD. CPD
inhibits external reads and writes of data EEPROM.
WRTD inhibits internal and external writes to data
EEPROM. The CPU can continue to read and write
data EEPROM regardless of the protection bit settings.
24.9 Single-Supply ICSP Programming
The LVP Configuration bit enables Single-Supply ICSP
programming (formerly known as Low-Voltage ICSP
Programming or LVP). When Single-Supply Program-
ming is enabled, the microcontroller can be programmed
without requiring high voltage being applied to the
MCLR/VPP/RE3 pin, but the RB5/KBI1/PGM pin is then
dedicated to controlling Program mode entry and is not
available as a general purpose I/O pin.
24.5.3
CONFIGURATION REGISTER
PROTECTION
The Configuration registers can be write-protected.
The WRTC bit controls protection of the Configuration
registers. In normal execution mode, the WRTC bit is
readable only. WRTC can only be written via ICSP or
an external programmer.
While programming using Single-Supply Programming,
VDD is applied to the MCLR/VPP/RE3 pin as in normal
execution mode. To enter Programming mode, VDD is
applied to the PGM pin.
24.6 ID Locations
Eight memory locations (200000h-200007h) are
designated as ID locations, where the user can store
checksum or other code identification numbers. These
locations are both readable and writable during normal
execution through the TBLRD and TBLWT instructions
or during program/verify. The ID locations can be read
when the device is code-protected.
Note 1: High-voltage programming is always avail-
able, regardless of the state of the LVP bit,
by applying VIHH to the MCLR pin.
2: While in Low-Voltage ICSP Programming
mode, the RB5 pin can no longer be used
as a general purpose I/O pin and should
be held low during normal operation.
24.7
In-Circuit Serial Programming
3: When using Low-Voltage ICSP Program-
ming (LVP) and the pull-ups on PORTB
are enabled, bit 5 in the TRISB register
must be cleared to disable the pull-up on
RB5 and ensure the proper operation of
the device.
PIC18F2682/2685/4682/4685 microcontrollers can be
serially programmed while in the end application circuit.
This is simply done with two lines for clock and data
and three other lines for power, ground and the
programming voltage. This allows customers to
manufacture boards with unprogrammed devices and
then program the microcontroller just before shipping
the product. This also allows the most recent firmware
or a custom firmware to be programmed.
4: If the device Master Clear is disabled,
verify that either of the following is done to
ensure proper entry into ICSP mode:
a) disable Low-Voltage Programming
24.8 In-Circuit Debugger
(CONFIG4L<2> = 0); or
When the DEBUG Configuration bit is programmed to
a ‘0’, the In-Circuit Debugger functionality is enabled.
This function allows simple debugging functions when
used with MPLAB® IDE. When the microcontroller has
this feature enabled, some resources are not available
for general use. Table 24-4 shows which resources are
required by the background debugger.
b) make certain that RB5/KBI1/PGM
is held low during entry into ICSP.
If Single-Supply ICSP Programming mode will not be
used, the LVP bit can be cleared. RB5/KBI1/PGM then
becomes available as the digital I/O pin, RB5. The LVP
bit may be set or cleared only when using standard
high-voltage programming (VIHH applied to the MCLR/
VPP/RE3 pin). Once LVP has been disabled, only the
standard high-voltage programming is available and
must be used to program the device.
TABLE 24-4: DEBUGGER RESOURCES
I/O pins:
Stack:
RB6, RB7
2 levels
Memory that is not code-protected can be erased using
either a block erase, or erased row by row, then written
at any specified VDD. If code-protected memory is to be
erased, a block erase is required. If a block erase is to
be performed when using Low-Voltage Programming,
the device must be supplied with VDD of 4.5V to 5.5V.
Note:
Memory sources listed in MPLAB® IDE.
DS39761B-page 362
Preliminary
© 2007 Microchip Technology Inc.
PIC18F2682/2685/4682/4685
The literal instructions may use some of the following
operands:
25.0 INSTRUCTION SET SUMMARY
PIC18F2682/2685/4682/4685 devices incorporate the
standard set of 75 PIC18 core instructions, as well as
an extended set of 8 new instructions, for the optimiza-
tion of code that is recursive or that utilizes a software
stack. The extended set is discussed later in this
section.
• A literal value to be loaded into a file register
(specified by ‘k’)
• The desired FSR register to load the literal value
into (specified by ‘f’)
• No operand required
(specified by ‘—’)
25.1 Standard Instruction Set
The control instructions may use some of the following
operands:
The standard PIC18 instruction set adds many
enhancements to the previous PIC® MCU instruction
sets, while maintaining an easy migration from these
PIC MCU instruction sets. Most instructions are a
single program memory word (16 bits), but there are
four instructions that require two program memory
locations.
• A program memory address (specified by ‘n’)
• The mode of the CALLor RETURNinstructions
(specified by ‘s’)
• The mode of the table read and table write
instructions (specified by ‘m’)
• No operand required (specified by ‘—’)
Each single-word instruction is a 16-bit word divided
into an opcode, which specifies the instruction type and
one or more operands, which further specify the
operation of the instruction.
All instructions are a single word, except for four
double-word instructions. These instructions were
made double-word to contain the required information
in 32 bits. In the second word, the 4 MSbs are ‘1’s. If
this second word is executed as an instruction (by
itself), it will execute as a NOP.
The instruction set is highly orthogonal and is grouped
into four basic categories:
• Byte-oriented operations
• Bit-oriented operations
• Literal operations
All single-word instructions are executed in a single
instruction cycle, unless a conditional test is true or the
program counter is changed as a result of the instruc-
tion. In these cases, the execution takes two instruction
cycles with the additional instruction cycle(s) executed
as a NOP.
• Control operations
The PIC18 instruction set summary in Table 25-2 lists
byte-oriented, bit-oriented, literal and control
operations. Table 25-1 shows the opcode field
descriptions.
The double-word instructions execute in two instruction
cycles.
One instruction cycle consists of four oscillator periods.
Thus, for an oscillator frequency of 4 MHz, the normal
instruction execution time is 1 μs. If a conditional test is
true, or the program counter is changed as a result of
an instruction, the instruction execution time is 2 μs.
Two-word branch instructions (if true) would take 3 μs.
Most byte-oriented instructions have three operands:
1. The file register (specified by ‘f’)
2. The destination of the result (specified by ‘d’)
3. The accessed memory (specified by ‘a’)
The file register designator ‘f’ specifies which file
register is to be used by the instruction. The destination
designator ‘d’ specifies where the result of the opera-
tion is to be placed. If ‘d’ is zero, the result is placed in
the WREG register. If ‘d’ is one, the result is placed in
the file register specified in the instruction.
Figure 25-1 shows the general formats that the instruc-
tions can have. All examples use the convention ‘nnh’
to represent a hexadecimal number.
The Instruction Set Summary, shown in Table 25-2,
lists the standard instructions recognized by the
Microchip MPASM™ Assembler.
All bit-oriented instructions have three operands:
Section 25.1.1 “Standard Instruction Set” provides
a description of each instruction.
1. The file register (specified by ‘f’)
2. The bit in the file register (specified by ‘b’)
3. The accessed memory (specified by ‘a’)
The bit field designator ‘b’ selects the number of the bit
affected by the operation, while the file register
designator ‘f’ represents the number of the file in which
the bit is located.
© 2007 Microchip Technology Inc.
Preliminary
DS39761B-page 363
PIC18F2682/2685/4682/4685
TABLE 25-1: OPCODE FIELD DESCRIPTIONS
Field
Description
a
RAM access bit
a = 0: RAM location in Access RAM (BSR register is ignored)
a = 1: RAM bank is specified by BSR register
bbb
BSR
Bit address within an 8-bit file register (0 to 7).
Bank Select Register. Used to select the current RAM bank.
ALU Status bits: Carry, Digit Carry, Zero, Overflow, Negative.
C, DC, Z, OV, N
d
Destination select bit
d = 0: store result in WREG
d = 1: store result in file register f
dest
f
Destination: either the WREG register or the specified register file location.
8-bit Register file address (00h to FFh), or 2-bit FSR designator (0h to 3h).
12-bit Register file address (000h to FFFh). This is the source address.
12-bit Register file address (000h to FFFh). This is the destination address.
Global Interrupt Enable bit.
f
s
f
d
GIE
k
Literal field, constant data or label (may be either an 8-bit, 12-bit or a 20-bit value)
Label name
label
mm
The mode of the TBLPTR register for the table read and table write instructions.
Only used with table read and table write instructions:
*
No change to register (such as TBLPTR with table reads and writes)
Post-Increment register (such as TBLPTR with table reads and writes)
Post-Decrement register (such as TBLPTR with table reads and writes)
Pre-Increment register (such as TBLPTR with table reads and writes)
*+
*-
+*
n
The relative address (2’s complement number) for relative branch instructions or the direct address for
Call/Branch and Return instructions
PC
Program Counter.
PCL
Program Counter Low Byte.
Program Counter High Byte.
Program Counter High Byte Latch.
Program Counter Upper Byte Latch.
Power-down bit.
PCH
PCLATH
PCLATU
PD
PRODH
PRODL
s
Product of Multiply High Byte.
Product of Multiply Low Byte.
Fast Call/Return mode select bit
s = 0: do not update into/from shadow registers
s = 1: certain registers loaded into/from shadow registers (Fast mode)
TBLPTR
TABLAT
TO
21-bit Table Pointer (points to a Program Memory location).
8-bit Table Latch.
Time-out bit.
TOS
u
Top-of-Stack.
Unused or unchanged.
Watchdog Timer.
WDT
WREG
x
Working register (accumulator).
Don’t care (‘0’ or ‘1’). The assembler will generate code with x = 0. It is the recommended form of use for
compatibility with all Microchip software tools.
z
7-bit offset value for indirect addressing of register files (source).
7-bit offset value for indirect addressing of register files (destination).
Optional argument.
s
z
d
{
}
[text]
(text)
[expr]<n>
→
Indicates an indexed address.
The contents of text.
Specifies bit nof the register indicated by the pointer expr.
Assigned to.
< >
Register bit field.
∈
In the set of.
italics
User defined term (font is Courier).
DS39761B-page 364
Preliminary
© 2007 Microchip Technology Inc.
PIC18F2682/2685/4682/4685
FIGURE 25-1:
GENERAL FORMAT FOR INSTRUCTIONS
Byte-oriented file register operations
15 10
OPCODE f (FILE #)
Example Instruction
9
8
7
0
ADDWF MYREG, W, B
d
a
d = 0for result destination to be WREG register
d = 1for result destination to be file register (f)
a = 0to force Access Bank
a = 1for BSR to select bank
f = 8-bit file register address
Byte to Byte move operations (2-word)
15
12 11
0
0
MOVFF MYREG1, MYREG2
OPCODE
f (Source FILE #)
15
12 11
1111
f (Destination FILE #)
f = 12-bit file register address
Bit-oriented file register operations
15 12 11 9 8
OPCODE b (BIT #)
7
0
BSF MYREG, bit, B
a
f (FILE #)
b = 3-bit position of bit in file register (f)
a = 0to force Access Bank
a = 1for BSR to select bank
f = 8-bit file register address
Literal operations
15
8
7
0
MOVLW 7Fh
OPCODE
k (literal)
k = 8-bit immediate value
Control operations
CALL, GOTOand Branch operations
15
8 7
0
GOTO Label
OPCODE
12 11
n<7:0> (literal)
15
0
1111
n<19:8> (literal)
n = 20-bit immediate value
15
15
8
7
0
CALL MYFUNC
OPCODE
12 11
S
n<7:0> (literal)
0
1111
n<19:8> (literal)
S = Fast bit
15
15
11 10
0
0
BRA MYFUNC
BC MYFUNC
OPCODE
OPCODE
n<10:0> (literal)
n<7:0> (literal)
8 7
© 2007 Microchip Technology Inc.
Preliminary
DS39761B-page 365
PIC18F2682/2685/4682/4685
TABLE 25-2: PIC18FXXXX INSTRUCTION SET
16-Bit Instruction Word
MSb LSb
Mnemonic,
Operands
Status Bits
Affected
Description
Cycles
Notes
BYTE-ORIENTED OPERATIONS
ADDWF f, d, a Add WREG and f
ADDWFC f, d, a Add WREG and Carry bit to f
1
0010 01da ffff ffff C, DC, Z, OV, N 1, 2
0010 00da ffff ffff C, DC, Z, OV, N 1, 2
1
1
1
1
ANDWF
CLRF
COMF
f, d, a AND WREG with f
f, a Clear f
f, d, a Complement f
0001 01da ffff ffff Z, N
0110 101a ffff ffff Z
0001 11da ffff ffff Z, N
1,2
2
1, 2
4
CPFSEQ
CPFSGT
CPFSLT
DECF
f, a
f, a
f, a
Compare f with WREG, skip =
Compare f with WREG, skip >
Compare f with WREG, skip <
1 (2 or 3) 0110 001a ffff ffff None
1 (2 or 3) 0110 010a ffff ffff None
1 (2 or 3) 0110 000a ffff ffff None
4
1, 2
f, d, a Decrement f
1
0000 01da ffff ffff C, DC, Z, OV, N 1, 2, 3, 4
DECFSZ
DCFSNZ
INCF
f, d, a Decrement f, Skip if 0
f, d, a Decrement f, Skip if Not 0
f, d, a Increment f
1 (2 or 3) 0010 11da ffff ffff None
1 (2 or 3) 0100 11da ffff ffff None
1, 2, 3, 4
1, 2
1
0010 10da ffff ffff C, DC, Z, OV, N 1, 2, 3, 4
INCFSZ
INFSNZ
IORWF
MOVF
f, d, a Increment f, Skip if 0
f, d, a Increment f, Skip if Not 0
f, d, a Inclusive OR WREG with f
f, d, a Move f
fs, fd Move fs (source) to 1st word
fd (destination)2nd word
1 (2 or 3) 0011 11da ffff ffff None
1 (2 or 3) 0100 10da ffff ffff None
4
1, 2
1, 2
1
1
1
2
0001 00da ffff ffff Z, N
0101 00da ffff ffff Z, N
1100 ffff ffff ffff None
1111 ffff ffff ffff
MOVFF
MOVWF
MULWF
NEGF
RLCF
RLNCF
RRCF
f, a
f, a
f, a
Move WREG to f
Multiply WREG with f
Negate f
1
1
1
1
1
1
1
1
1
0110 111a ffff ffff None
0000 001a ffff ffff None
0110 110a ffff ffff C, DC, Z, OV, N
0011 01da ffff ffff C, Z, N
0100 01da ffff ffff Z, N
0011 00da ffff ffff C, Z, N
0100 00da ffff ffff Z, N
0110 100a ffff ffff None
0101 01da ffff ffff C, DC, Z, OV, N
1, 2
1, 2
f, d, a Rotate Left f through Carry
f, d, a Rotate Left f (No Carry)
f, d, a Rotate Right f through Carry
f, d, a Rotate Right f (No Carry)
RRNCF
SETF
f, a
Set f
1, 2
SUBFWB f, d, a Subtract f from WREG with
borrow
SUBWF
f, d, a Subtract WREG from f
1
1
0101 11da ffff ffff C, DC, Z, OV, N 1, 2
0101 10da ffff ffff C, DC, Z, OV, N
SUBWFB f, d, a Subtract WREG from f with
borrow
SWAPF
TSTFSZ
XORWF
f, d, a Swap nibbles in f
f, a Test f, skip if 0
f, d, a Exclusive OR WREG with f
1
0011 10da ffff ffff None
4
1, 2
1 (2 or 3) 0110 011a ffff ffff None
0001 10da ffff ffff Z, N
1
Note 1: When a PORT register is modified as a function of itself (e.g., MOVF PORTB, 1, 0), the value used will be that
value present on the pins themselves. For example, if the data latch is ‘1’ for a pin configured as input and is
driven low by an external device, the data will be written back with a ‘0’.
2: If this instruction is executed on the TMR0 register (and where applicable, ‘d’ = 1), the prescaler will be cleared
if assigned.
3: If Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The second
cycle is executed as a NOP.
4: Some instructions are two-word instructions. The second word of these instructions will be executed as a NOP
unless the first word of the instruction retrieves the information embedded in these 16 bits. This ensures that all
program memory locations have a valid instruction.
5: If the table write starts the write cycle to internal memory, the write will continue until terminated.
DS39761B-page 366
Preliminary
© 2007 Microchip Technology Inc.
PIC18F2682/2685/4682/4685
TABLE 25-2: PIC18FXXXX INSTRUCTION SET (CONTINUED)
16-Bit Instruction Word
Mnemonic,
Operands
Status Bits
Affected
Description
Cycles
Notes
MSb LSb
BIT-ORIENTED OPERATIONS
BCF
BSF
BTFSC
BTFSS
BTG
f, b, a Bit Clear f
f, b, a Bit Set f
f, b, a Bit Test f, Skip if Clear
f, b, a Bit Test f, Skip if Set
f, b, a Bit Toggle f
1
1
1001 bbba ffff ffff None
1000 bbba ffff ffff None
1, 2
1, 2
3, 4
3, 4
1, 2
1 (2 or 3) 1011 bbba ffff ffff None
1 (2 or 3) 1010 bbba ffff ffff None
1
0111 bbba ffff ffff None
CONTROL OPERATIONS
BC
BN
n
n
n
n
n
n
n
n
Branch if Carry
1 (2)
1 (2)
1 (2)
1 (2)
1 (2)
1 (2)
1 (2)
2
1110 0010 nnnn nnnn None
1110 0110 nnnn nnnn None
1110 0011 nnnn nnnn None
1110 0111 nnnn nnnn None
1110 0101 nnnn nnnn None
1110 0001 nnnn nnnn None
1110 0100 nnnn nnnn None
1101 0nnn nnnn nnnn None
1110 0000 nnnn nnnn None
1110 110s kkkk kkkk None
1111 kkkk kkkk kkkk
Branch if Negative
Branch if Not Carry
Branch if Not Negative
Branch if Not Overflow
Branch if Not Zero
Branch if Overflow
Branch Unconditionally
Branch if Zero
BNC
BNN
BNOV
BNZ
BOV
BRA
BZ
n
n, s
1 (2)
2
CALL
Call subroutine1st word
2nd word
CLRWDT
DAW
GOTO
—
—
n
Clear Watchdog Timer
Decimal Adjust WREG
Go to address 1st word
2nd word
1
1
2
0000 0000 0000 0100 TO, PD
0000 0000 0000 0111 C
1110 1111 kkkk kkkk None
1111 kkkk kkkk kkkk
NOP
NOP
POP
PUSH
RCALL
RESET
RETFIE
—
—
—
—
n
No Operation
No Operation
1
1
1
1
2
1
2
0000 0000 0000 0000 None
1111 xxxx xxxx xxxx None
0000 0000 0000 0110 None
0000 0000 0000 0101 None
1101 1nnn nnnn nnnn None
0000 0000 1111 1111 All
0000 0000 0001 000s GIE/GIEH,
PEIE/GIEL
4
Pop top of return stack (TOS)
Push top of return stack (TOS)
Relative Call
Software device Reset
Return from interrupt enable
s
RETLW
RETURN
SLEEP
k
s
—
Return with literal in WREG
Return from Subroutine
Go into Standby mode
2
2
1
0000 1100 kkkk kkkk None
0000 0000 0001 001s None
0000 0000 0000 0011 TO, PD
Note 1: When a PORT register is modified as a function of itself (e.g., MOVF PORTB, 1, 0), the value used will be that
value present on the pins themselves. For example, if the data latch is ‘1’ for a pin configured as input and is
driven low by an external device, the data will be written back with a ‘0’.
2: If this instruction is executed on the TMR0 register (and where applicable, ‘d’ = 1), the prescaler will be cleared
if assigned.
3: If Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The second
cycle is executed as a NOP.
4: Some instructions are two-word instructions. The second word of these instructions will be executed as a NOP
unless the first word of the instruction retrieves the information embedded in these 16 bits. This ensures that all
program memory locations have a valid instruction.
5: If the table write starts the write cycle to internal memory, the write will continue until terminated.
© 2007 Microchip Technology Inc.
Preliminary
DS39761B-page 367
PIC18F2682/2685/4682/4685
TABLE 25-2: PIC18FXXXX INSTRUCTION SET (CONTINUED)
16-Bit Instruction Word
Mnemonic,
Operands
Status Bits
Affected
Description
Cycles
Notes
MSb
LSb
LITERAL OPERATIONS
ADDLW
ANDLW
IORLW
LFSR
k
k
k
f, k
Add literal and WREG
AND literal with WREG
Inclusive OR literal with WREG
Move literal (12-bit) 2nd word
1
0000 1111 kkkk
0000 1011 kkkk
0000 1001 kkkk
1110 1110 00ff
1111 0000 kkkk
0000 0001 0000
0000 1110 kkkk
0000 1101 kkkk
0000 1100 kkkk
0000 1000 kkkk
0000 1010 kkkk
kkkk C, DC, Z, OV, N
kkkk Z, N
kkkk Z, N
kkkk None
kkkk
kkkk None
kkkk None
kkkk None
kkkk None
kkkk C, DC, Z, OV, N
kkkk Z, N
1
1
2
to FSR(f)
1st word
MOVLB
MOVLW
MULLW
RETLW
SUBLW
XORLW
k
k
k
k
k
k
Move literal to BSR<3:0>
Move literal to WREG
Multiply literal with WREG
Return with literal in WREG
Subtract WREG from literal
1
1
1
2
1
Exclusive OR literal with WREG 1
DATA MEMORY ↔ PROGRAM MEMORY OPERATIONS
TBLRD*
Table Read
2
0000 0000 0000
0000 0000 0000
0000 0000 0000
0000 0000 0000
0000 0000 0000
0000 0000 0000
0000 0000 0000
0000 0000 0000
1000 None
1001 None
1010 None
1011 None
1100 None
1101 None
1110 None
1111 None
TBLRD*+
TBLRD*-
TBLRD+*
TBLWT*
TBLWT*+
TBLWT*-
TBLWT+*
Table Read with post-increment
Table Read with post-decrement
Table Read with pre-increment
Table Write
Table Write with post-increment
Table Write with post-decrement
Table Write with pre-increment
2
5
5
5
5
Note 1: When a PORT register is modified as a function of itself (e.g., MOVF PORTB, 1, 0), the value used will be that
value present on the pins themselves. For example, if the data latch is ‘1’ for a pin configured as input and is
driven low by an external device, the data will be written back with a ‘0’.
2: If this instruction is executed on the TMR0 register (and where applicable, ‘d’ = 1), the prescaler will be cleared
if assigned.
3: If Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The second
cycle is executed as a NOP.
4: Some instructions are two-word instructions. The second word of these instructions will be executed as a NOP
unless the first word of the instruction retrieves the information embedded in these 16 bits. This ensures that all
program memory locations have a valid instruction.
5: If the table write starts the write cycle to internal memory, the write will continue until terminated.
DS39761B-page 368
Preliminary
© 2007 Microchip Technology Inc.
PIC18F2682/2685/4682/4685
25.1.1
STANDARD INSTRUCTION SET
ADD Literal to W
ADDLW
ADDWF
ADD W to f
Syntax:
ADDLW
k
Syntax:
ADDWF
f {,d {,a}}
Operands:
Operation:
Status Affected:
Encoding:
Description:
0 ≤ k ≤ 255
Operands:
0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
(W) + k → W
N, OV, C, DC, Z
Operation:
(W) + (f) → dest
0000
1111
kkkk
kkkk
Status Affected:
Encoding:
N, OV, C, DC, Z
The contents of W are added to the
8-bit literal ‘k’ and the result is placed
in W.
0010
01da
ffff
ffff
Description:
Add W to register ‘f’. If ‘d’ is ‘0’, the
result is stored in W. If ‘d’ is ‘1’, the
result is stored back in register ‘f’
(default).
Words:
Cycles:
1
1
Q Cycle Activity:
Q1
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank (default).
Q2
Q3
Q4
Decode
Read
literal ‘k’
Process
Data
Write to W
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f ≤ 95 (5Fh). See
Section 25.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
Example:
ADDLW
15h
Before Instruction
10h
After Instruction
25h
W
=
Words:
Cycles:
1
1
W
=
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
register ‘f’
Process
Data
Write to
destination
Example:
ADDWF
REG, 0, 0
Before Instruction
W
REG
=
=
17h
0C2h
After Instruction
W
REG
=
=
0D9h
0C2h
Note:
All PIC18 instructions may take an optional label argument preceding the instruction mnemonic for use in
symbolic addressing. If a label is used, the instruction format then becomes: {label} instruction argument(s).
© 2007 Microchip Technology Inc.
Preliminary
DS39761B-page 369
PIC18F2682/2685/4682/4685
ADDWFC
ADD W and Carry bit to f
ANDLW
AND Literal with W
Syntax:
ADDWFC
f {,d {,a}}
Syntax:
ANDLW
k
Operands:
0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
Operands:
Operation:
Status Affected:
Encoding:
Description:
0 ≤ k ≤ 255
(W) .AND. k → W
N, Z
Operation:
(W) + (f) + (C) → dest
0000
1011
kkkk
kkkk
Status Affected:
Encoding:
N,OV, C, DC, Z
The contents of W are ANDed with the
8-bit literal ‘k’. The result is placed in W.
0010
00da
ffff
ffff
Description:
Add W, the Carry flag and data memory
location ‘f’. If ‘d’ is ‘0’, the result is
placed in W. If ‘d’ is ‘1’, the result is
placed in data memory
Words:
1
1
Cycles:
Q Cycle Activity:
Q1
location ‘f’.
Q2
Q3
Q4
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank (default).
Decode
Read literal
‘k’
Process
Data
Write to W
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f ≤ 95 (5Fh). See
Section 25.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
Example:
ANDLW
05Fh
Before Instruction
W
=
A3h
03h
After Instruction
W
=
Words:
Cycles:
1
1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
register ‘f’
Process
Data
Write to
destination
Example:
ADDWFC
REG, 0, 1
Before Instruction
Carry bit =
1
02h
4Dh
REG
W
=
=
After Instruction
Carry bit =
0
02h
50h
REG
W
=
=
DS39761B-page 370
Preliminary
© 2007 Microchip Technology Inc.
PIC18F2682/2685/4682/4685
ANDWF
AND W with f
BC
Branch if Carry
Syntax:
ANDWF
f {,d {,a}}
Syntax:
BC
n
Operands:
0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
Operands:
Operation:
-128 ≤ n ≤ 127
if Carry bit is ‘1’
(PC) + 2 + 2n → PC
Operation:
(W) .AND. (f) → dest
Status Affected:
Encoding:
None
Status Affected:
Encoding:
N, Z
1110
0010
nnnn
nnnn
0001
01da
ffff
ffff
Description:
If the Carry bit is ‘1’, then the program
Description:
The contents of W are ANDed with
register ‘f’. If ‘d’ is ‘0’, the result is stored
in W. If ‘d’ is ‘1’, the result is stored back
in register ‘f’ (default).
will branch.
The 2’s complement number ‘2n’ is
added to the PC. Since the PC will have
incremented to fetch the next
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank (default).
instruction, the new address will be
PC + 2 + 2n. This instruction is then a
two-cycle instruction.
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f ≤ 95 (5Fh). See
Section 25.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
Words:
Cycles:
1
1(2)
Q Cycle Activity:
If Jump:
Q1
Q2
Q3
Q4
Decode
Read literal
‘n’
Process
Data
Write to PC
Words:
1
1
Cycles:
No
No
No
No
operation
operation
operation
operation
Q Cycle Activity:
Q1
If No Jump:
Q1
Q2
Q3
Q4
Q2
Q3
Q4
Decode
Read
register ‘f’
Process
Data
Write to
destination
Decode
Read literal
‘n’
Process
Data
No
operation
Example:
ANDWF
REG, 0, 0
Example:
HERE
BC
5
Before Instruction
Before Instruction
W
=
17h
C2h
PC
=
address (HERE)
REG
=
After Instruction
After Instruction
If Carry
PC
If Carry
PC
=
=
=
=
1;
W
REG
=
=
02h
C2h
address (HERE + 12)
0;
address (HERE + 2)
© 2007 Microchip Technology Inc.
Preliminary
DS39761B-page 371
PIC18F2682/2685/4682/4685
BCF
Bit Clear f
BN
Branch if Negative
Syntax:
BCF f, b {,a}
Syntax:
BN
n
Operands:
0 ≤ f ≤ 255
0 ≤ b ≤ 7
a ∈ [0,1]
Operands:
Operation:
-128 ≤ n ≤ 127
if Negative bit is ‘1’
(PC) + 2 + 2n → PC
Operation:
0 → f<b>
Status Affected:
Encoding:
None
Status Affected:
Encoding:
None
1110
0110
nnnn
nnnn
1001
bbba
ffff
ffff
Description:
If the Negative bit is ‘1’, then the
Description:
Bit ‘b’ in register ‘f’ is cleared.
program will branch.
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank (default).
The 2’s complement number ‘2n’ is
added to the PC. Since the PC will have
incremented to fetch the next
instruction, the new address will be
PC + 2 + 2n. This instruction is then a
two-cycle instruction.
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f ≤ 95 (5Fh). See
Section 25.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
Words:
Cycles:
1
1(2)
Q Cycle Activity:
If Jump:
Q1
Words:
Cycles:
1
1
Q2
Q3
Q4
Decode
Read literal
‘n’
Process
Data
Write to PC
Q Cycle Activity:
Q1
Q2
Q3
Q4
No
No
No
No
Decode
Read
register ‘f’
Process
Data
Write
register ‘f’
operation
operation
operation
operation
If No Jump:
Q1
Q2
Q3
Q4
Example:
BCF
FLAG_REG, 7, 0
Decode
Read literal
‘n’
Process
Data
No
operation
Before Instruction
FLAG_REG = C7h
After Instruction
FLAG_REG = 47h
Example:
HERE
BN Jump
Before Instruction
PC
=
address (HERE)
After Instruction
If Negative
PC
If Negative
PC
=
=
=
=
1;
address (Jump)
0;
address (HERE + 2)
DS39761B-page 372
Preliminary
© 2007 Microchip Technology Inc.
PIC18F2682/2685/4682/4685
BNC
Branch if Not Carry
BNN
Branch if Not Negative
Syntax:
BNC
n
Syntax:
BNN
n
Operands:
Operation:
-128 ≤ n ≤ 127
Operands:
Operation:
-128 ≤ n ≤ 127
if Carry bit is ‘0’
(PC) + 2 + 2n → PC
if Negative bit is ‘0’
(PC) + 2 + 2n → PC
Status Affected:
Encoding:
None
Status Affected:
Encoding:
None
1110
0011
nnnn
nnnn
1110
0111
nnnn
nnnn
Description:
If the Carry bit is ‘0’, then the program
Description:
If the Negative bit is ‘0’, then the
will branch.
program will branch.
The 2’s complement number ‘2n’ is
added to the PC. Since the PC will
have incremented to fetch the next
instruction, the new address will be
PC + 2 + 2n. This instruction is then a
two-cycle instruction.
The 2’s complement number ‘2n’ is
added to the PC. Since the PC will have
incremented to fetch the next
instruction, the new address will be
PC + 2 + 2n. This instruction is then a
two-cycle instruction.
Words:
Cycles:
1
Words:
Cycles:
1
1(2)
1(2)
Q Cycle Activity:
If Jump:
Q1
Q Cycle Activity:
If Jump:
Q1
Q2
Q3
Q4
Q2
Q3
Q4
Decode
Read literal
‘n’
Process
Data
Write to PC
Decode
Read literal
‘n’
Process
Data
Write to PC
No
No
No
No
No
No
No
No
operation
operation
operation
operation
operation
operation
operation
operation
If No Jump:
Q1
If No Jump:
Q1
Q2
Q3
Q4
Q2
Q3
Q4
Decode
Read literal
‘n’
Process
Data
No
operation
Decode
Read literal
‘n’
Process
Data
No
operation
Example:
HERE
BNC Jump
Example:
HERE
BNN Jump
Before Instruction
Before Instruction
PC
=
address (HERE)
PC
=
address (HERE)
After Instruction
After Instruction
If Carry
PC
If Carry
PC
=
=
=
=
0;
If Negative
PC
If Negative
PC
=
=
=
=
0;
address (Jump)
address (Jump)
1;
1;
address (HERE + 2)
address (HERE + 2)
© 2007 Microchip Technology Inc.
Preliminary
DS39761B-page 373
PIC18F2682/2685/4682/4685
BNOV
Branch if Not Overflow
BNZ
Branch if Not Zero
Syntax:
BNOV
n
Syntax:
BNZ
n
Operands:
Operation:
-128 ≤ n ≤ 127
Operands:
Operation:
-128 ≤ n ≤ 127
if Overflow bit is ‘0’
(PC) + 2 + 2n → PC
if Zero bit is ‘0’
(PC) + 2 + 2n → PC
Status Affected:
Encoding:
None
Status Affected:
Encoding:
None
1110
0101
nnnn
nnnn
1110
0001
nnnn
nnnn
Description:
If the Overflow bit is ‘0’, then the
Description:
If the Zero bit is ‘0’, then the program
program will branch.
will branch.
The 2’s complement number ‘2n’ is
added to the PC. Since the PC will have
incremented to fetch the next
The 2’s complement number ‘2n’ is
added to the PC. Since the PC will have
incremented to fetch the next
instruction, the new address will be
PC + 2 + 2n. This instruction is then a
two-cycle instruction.
instruction, the new address will be
PC + 2 + 2n. This instruction is then a
two-cycle instruction.
Words:
Cycles:
1
Words:
Cycles:
1
1(2)
1(2)
Q Cycle Activity:
If Jump:
Q1
Q Cycle Activity:
If Jump:
Q1
Q2
Q3
Q4
Q2
Q3
Q4
Decode
Read literal
‘n’
Process
Data
Write to PC
Decode
Read literal
‘n’
Process
Data
Write to PC
No
No
No
No
No
No
No
No
operation
operation
operation
operation
operation
operation
operation
operation
If No Jump:
Q1
If No Jump:
Q1
Q2
Q3
Q4
Q2
Q3
Q4
Decode
Read literal
‘n’
Process
Data
No
operation
Decode
Read literal
‘n’
Process
Data
No
operation
Example:
HERE
BNOV Jump
Example:
HERE
BNZ Jump
Before Instruction
Before Instruction
PC
=
address (HERE)
PC
=
address (HERE)
After Instruction
After Instruction
If Overflow
PC
If Overflow
PC
=
=
=
=
0;
If Zero
PC
If Zero
PC
=
=
=
=
0;
address (Jump)
address (Jump)
1;
1;
address (HERE + 2)
address (HERE + 2)
DS39761B-page 374
Preliminary
© 2007 Microchip Technology Inc.
PIC18F2682/2685/4682/4685
BRA
Unconditional Branch
BSF
Bit Set f
Syntax:
BRA
n
Syntax:
BSF f, b {,a}
Operands:
Operation:
Status Affected:
Encoding:
Description:
-1024 ≤ n ≤ 1023
(PC) + 2 + 2n → PC
None
Operands:
0 ≤ f ≤ 255
0 ≤ b ≤ 7
a ∈ [0,1]
Operation:
1 → f<b>
1101
0nnn
nnnn
nnnn
Status Affected:
Encoding:
None
Add the 2’s complement number ‘2n’ to
the PC. Since the PC will have
incremented to fetch the next
instruction, the new address will be
PC + 2 + 2n. This instruction is a
two-cycle instruction.
1000
bbba
ffff
ffff
Description:
Bit ‘b’ in register ‘f’ is set.
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank (default).
Words:
Cycles:
1
2
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f ≤ 95 (5Fh). See
Section 25.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read literal
‘n’
Process
Data
Write to PC
Words:
Cycles:
1
1
No
operation
No
operation
No
operation
No
operation
Q Cycle Activity:
Q1
Example:
HERE
BRA Jump
Q2
Q3
Q4
Decode
Read
register ‘f’
Process
Data
Write
register ‘f’
Before Instruction
PC
=
=
address (HERE)
address (Jump)
After Instruction
PC
Example:
BSF
FLAG_REG, 7, 1
0Ah
8Ah
Before Instruction
FLAG_REG
After Instruction
FLAG_REG
=
=
© 2007 Microchip Technology Inc.
Preliminary
DS39761B-page 375
PIC18F2682/2685/4682/4685
BTFSC
Bit Test File, Skip if Clear
BTFSS
Bit Test File, Skip if Set
Syntax:
BTFSC f, b {,a}
Syntax:
BTFSS f, b {,a}
Operands:
0 ≤ f ≤ 255
0 ≤ b ≤ 7
a ∈ [0,1]
Operands:
0 ≤ f ≤ 255
0 ≤ b < 7
a ∈ [0,1]
Operation:
skip if (f<b>) = 0
Operation:
skip if (f<b>) = 1
Status Affected:
Encoding:
None
Status Affected:
Encoding:
None
1011
bbba
ffff
ffff
1010
bbba
ffff
ffff
Description:
If bit ‘b’ in register ‘f’ is ‘0’, then the next
instruction is skipped. If bit ‘b’ is ‘0’, then
the next instruction fetched during the
current instruction execution is discarded
and a NOPis executed instead, making
this a two-cycle instruction.
Description:
If bit ‘b’ in register ‘f’ is ‘1’, then the next
instruction is skipped. If bit ‘b’ is ‘1’, then
the next instruction fetched during the
current instruction execution is discarded
and a NOPis executed instead, making
this a two-cycle instruction.
If ‘a’ is ‘0’, the Access Bank is selected. If
‘a’ is ‘1’, the BSR is used to select the
GPR bank (default).
If ‘a’ is ‘0’, the Access Bank is selected. If
‘a’ is ‘1’, the BSR is used to select the
GPR bank (default).
If ‘a’ is ‘0’ and the extended instruction set
is enabled, this instruction operates in
Indexed Literal Offset Addressing
mode whenever f ≤ 95 (5Fh).
See Section 25.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f ≤ 95 (5Fh).
See Section 25.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
Words:
Cycles:
1
Words:
Cycles:
1
1(2)
1(2)
Note: 3 cycles if skip and followed
Note: 3 cycles if skip and followed
by a 2-word instruction.
by a 2-word instruction.
Q Cycle Activity:
Q1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Q2
Q3
Q4
Decode
Read
register ‘f’
Process
Data
No
operation
Decode
Read
register ‘f’
Process
Data
No
operation
If skip:
Q1
If skip:
Q1
Q2
Q3
Q4
Q2
Q3
Q4
No
No
No
No
No
No
No
No
operation
operation
operation
operation
operation
operation
operation
operation
If skip and followed by 2-word instruction:
If skip and followed by 2-word instruction:
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
No
No
No
No
No
No
No
No
operation
operation
operation
operation
operation
operation
operation
operation
No
No
No
No
No
No
No
No
operation
operation
operation
operation
operation
operation
operation
operation
Example:
HERE
FALSE
TRUE
BTFSC
:
:
FLAG, 1, 0
Example:
HERE
FALSE
TRUE
BTFSS
:
:
FLAG, 1, 0
Before Instruction
PC
Before Instruction
PC
=
address (HERE)
=
address (HERE)
After Instruction
After Instruction
If FLAG<1>
PC
If FLAG<1>
PC
=
=
=
=
0;
If FLAG<1>
PC
If FLAG<1>
PC
=
=
=
=
0;
address (TRUE)
1;
address (FALSE)
1;
address (FALSE)
address (TRUE)
DS39761B-page 376
Preliminary
© 2007 Microchip Technology Inc.
PIC18F2682/2685/4682/4685
BTG
Bit Toggle f
BOV
Branch if Overflow
Syntax:
BTG f, b {,a}
Syntax:
BOV
n
Operands:
0 ≤ f ≤ 255
0 ≤ b < 7
a ∈ [0,1]
Operands:
Operation:
-128 ≤ n ≤ 127
if Overflow bit is ‘1’
(PC) + 2 + 2n → PC
Operation:
(f<b>) → f<b>
Status Affected:
Encoding:
None
Status Affected:
Encoding:
None
1110
0100
nnnn
nnnn
0111
bbba
ffff
ffff
Description:
If the Overflow bit is ‘1’, then the
Description:
Bit ‘b’ in data memory location ‘f’ is
inverted.
program will branch.
The 2’s complement number ‘2n’ is
added to the PC. Since the PC will
have incremented to fetch the next
instruction, the new address will be
PC + 2 + 2n. This instruction is then a
two-cycle instruction.
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank (default).
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset addressing
mode whenever f ≤ 95 (5Fh). See
Section 25.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
Words:
Cycles:
1
1(2)
Q Cycle Activity:
If Jump:
Q1
Words:
Cycles:
1
1
Q2
Q3
Q4
Decode
Read literal
‘n’
Process
Data
Write to PC
Q Cycle Activity:
Q1
No
No
No
No
operation
Q2
Q3
Q4
operation
operation
operation
Decode
Read
register ‘f’
Process
Data
Write
register ‘f’
If No Jump:
Q1
Q2
Q3
Q4
Decode
Read literal
‘n’
Process
Data
No
operation
Example:
BTG
PORTC, 4, 0
Before Instruction:
PORTC
After Instruction:
PORTC
=
0111 0101 [75h]
0110 0101 [65h]
Example:
HERE
BOV Jump
Before Instruction
=
PC
=
address (HERE)
After Instruction
If Overflow
PC
If Overflow
PC
=
=
=
=
1;
address (Jump)
0;
address (HERE + 2)
© 2007 Microchip Technology Inc.
Preliminary
DS39761B-page 377
PIC18F2682/2685/4682/4685
BZ
Branch if Zero
CALL
Subroutine Call
Syntax:
BZ
n
Syntax:
CALL k {,s}
Operands:
Operation:
-128 ≤ n ≤ 127
Operands:
0 ≤ k ≤ 1048575
s ∈ [0,1]
if Zero bit is ‘1’
(PC) + 2 + 2n → PC
Operation:
(PC) + 4 → TOS,
k → PC<20:1>;
if s = 1,
Status Affected:
Encoding:
None
1110
0000
nnnn
nnnn
(W) → WS,
(STATUS) → STATUSS,
(BSR) → BSRS
Description:
If the Zero bit is ‘1’, then the program
will branch.
The 2’s complement number ‘2n’ is
added to the PC. Since the PC will have
incremented to fetch the next
instruction, the new address will be
PC + 2 + 2n. This instruction is then a
two-cycle instruction.
Status Affected:
None
Encoding:
1st word (k<7:0>)
2nd word(k<19:8>)
1110
1111
110s
k kkk
kkkk
kkkk
7
0
8
k
kkk kkkk
19
Description:
Subroutine call of entire 2-Mbyte
memory range. First, return address
(PC + 4) is pushed onto the return
stack. If ‘s’ = 1, the W, STATUS and
Words:
Cycles:
1
1(2)
Q Cycle Activity:
If Jump:
Q1
BSR registers are also pushed into their
respective shadow registers, WS,
STATUSS and BSRS. If ‘s’ = 0, no
update occurs (default). Then, the
20-bit value ‘k’ is loaded into PC<20:1>.
CALLis a two-cycle instruction.
Q2
Q3
Q4
Decode
Read literal
‘n’
Process
Data
Write to PC
No
operation
No
operation
No
operation
No
operation
Words:
Cycles:
2
2
If No Jump:
Q1
Q2
Q3
Q4
Q Cycle Activity:
Q1
Decode
Read literal
‘n’
Process
Data
No
operation
Q2
Q3
Q4
Decode
Read literal Push PC to Read literal
‘k’<7:0>,
stack
‘k’<19:8>,
Write to PC
Example:
HERE
BZ Jump
No
operation
No
operation
No
operation
No
operation
Before Instruction
PC
=
address (HERE)
After Instruction
If Zero
PC
If Zero
PC
=
=
=
=
1;
Example:
HERE
CALL THERE, 1
address (Jump)
Before Instruction
PC
After Instruction
0;
address (HERE + 2)
=
address (HERE)
PC
=
address (THERE)
TOS
WS
=
=
=
address (HERE + 4)
W
BSRS
STATUSS=
BSR
STATUS
DS39761B-page 378
Preliminary
© 2007 Microchip Technology Inc.
PIC18F2682/2685/4682/4685
CLRF
Clear f
CLRWDT
Clear Watchdog Timer
Syntax:
CLRF f {,a}
Syntax:
CLRWDT
None
Operands:
0 ≤ f ≤ 255
a ∈ [0,1]
Operands:
Operation:
000h → WDT,
000h → WDT postscaler,
1 → TO,
Operation:
000h → f
1 → Z
1 → PD
Status Affected:
Encoding:
Z
Status Affected:
Encoding:
TO, PD
0110
101a
ffff
ffff
0000
0000
0000
0100
Description:
Clears the contents of the specified
register.
Description:
CLRWDTinstruction resets the
Watchdog Timer. It also resets the
postscaler of the WDT. Status bits TO
and PD are set.
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank (default).
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f ≤ 95 (5Fh). See
Section 25.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
Words:
Cycles:
1
1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
No
Process
Data
No
operation
operation
Words:
Cycles:
1
1
Example:
CLRWDT
Q Cycle Activity:
Q1
Before Instruction
WDT Counter
After Instruction
WDT Counter
WDT Postscaler
TO
=
?
Q2
Q3
Q4
Decode
Read
register ‘f’
Process
Data
Write
register ‘f’
=
=
=
=
00h
0
1
PD
1
Example:
CLRF
FLAG_REG,1
Before Instruction
FLAG_REG
After Instruction
FLAG_REG
=
=
5Ah
00h
© 2007 Microchip Technology Inc.
Preliminary
DS39761B-page 379
PIC18F2682/2685/4682/4685
CPFSEQ
Compare f with W, Skip if f = W
COMF
Complement f
Syntax:
CPFSEQ f {,a}
Syntax:
COMF f {,d {,a}}
Operands:
0 ≤ f ≤ 255
a ∈ [0,1]
Operands:
0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
Operation:
(f) – (W),
skip if (f) = (W)
(unsigned comparison)
Operation:
(f) → dest
Status Affected:
Encoding:
N, Z
Status Affected:
Encoding:
None
0001
11da
ffff
ffff
0110
001a
ffff
ffff
Description:
The contents of register ‘f’ are
Description:
Compares the contents of data memory
location ‘f’ to the contents of W by
performing an unsigned subtraction.
complemented. If ‘d’ is ‘1’, the result is
stored in W. If ‘d’ is ‘0’, the result is
stored back in register ‘f’ (default).
If ‘f’ = W, then the fetched instruction is
discarded and a NOPis executed
instead, making this a two-cycle
instruction.
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank (default).
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f ≤ 95 (5Fh). See
Section 25.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘0’, the BSR is used to select the
GPR bank (default).
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f ≤ 95 (5Fh). See
Section 25.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
Words:
Cycles:
1
1
Q Cycle Activity:
Q1
Words:
Cycles:
1
Q2
Q3
Q4
1(2)
Decode
Read
register ‘f’
Process
Data
Write to
destination
Note: 3 cycles if skip and followed
by a 2-word instruction.
Q Cycle Activity:
Q1
Example:
COMF
REG, 0, 0
Q2
Read
register ‘f’
Q3
Process
Data
Q4
No
operation
Before Instruction
Decode
REG
=
13h
After Instruction
If skip:
REG
W
=
=
13h
ECh
Q1
No
Q2
No
Q3
No
Q4
No
operation
operation
operation
operation
If skip and followed by 2-word instruction:
Q1
No
Q2
No
Q3
No
Q4
No
operation
No
operation
No
operation
No
operation
No
operation
operation
operation
operation
Example:
HERE
CPFSEQ REG, 0
NEQUAL
EQUAL
:
:
Before Instruction
PC Address
=
=
=
HERE
?
?
W
REG
After Instruction
If REG
PC
If REG
PC
=
=
≠
=
W;
Address (EQUAL)
W;
Address (NEQUAL)
DS39761B-page 380
Preliminary
© 2007 Microchip Technology Inc.
PIC18F2682/2685/4682/4685
CPFSGT
Compare f with W, Skip if f > W
CPFSLT
Compare f with W, Skip if f < W
Syntax:
CPFSGT f {,a}
Syntax:
CPFSLT f {,a}
Operands:
0 ≤ f ≤ 255
a ∈ [0,1]
Operands:
0 ≤ f ≤ 255
a ∈ [0,1]
Operation:
(f) − (W),
skip if (f) > (W)
(unsigned comparison)
Operation:
(f) – (W),
skip if (f) < (W)
(unsigned comparison)
Status Affected:
Encoding:
None
Status Affected:
Encoding:
None
0110
010a
ffff
ffff
0110
000a
ffff
ffff
Description:
Compares the contents of data memory
location ‘f’ to the contents of the W by
performing an unsigned subtraction.
Description:
Compares the contents of data memory
location ‘f’ to the contents of W by
performing an unsigned subtraction.
If the contents of ‘f’ are greater than the
contents of WREG, then the fetched
instruction is discarded and a NOPis
executed instead, making this a
two-cycle instruction.
If the contents of ‘f’ are less than the
contents of W, then the fetched
instruction is discarded and a NOPis
executed instead, making this a
two-cycle instruction.
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank (default).
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank (default).
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f ≤ 95 (5Fh). See
Section 25.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
Words:
Cycles:
1
1(2)
Note: 3 cycles if skip and followed
by a 2-word instruction.
Q Cycle Activity:
Q1
Q2
Q3
Q4
Words:
Cycles:
1
Decode
Read
register ‘f’
Process
Data
No
operation
1(2)
Note: 3 cycles if skip and followed
If skip:
Q1
by a 2-word instruction.
Q2
Q3
Q4
Q Cycle Activity:
Q1
No
operation
No
operation
No
operation
No
operation
Q2
Read
register ‘f’
Q3
Process
Data
Q4
No
operation
Decode
If skip and followed by 2-word instruction:
If skip:
Q1
Q2
Q3
Q4
Q1
No
Q2
No
Q3
No
Q4
No
No
operation
No
operation
No
operation
No
operation
operation
operation
operation
operation
No
No
No
No
If skip and followed by 2-word instruction:
operation
operation
operation
operation
Q1
No
operation
No
Q2
No
operation
No
Q3
No
operation
No
Q4
No
operation
No
Example:
HERE
NLESS
LESS
CPFSLT REG, 1
:
:
operation
operation
operation
operation
Before Instruction
PC
W
=
=
Address (HERE)
Example:
HERE
NGREATER
GREATER
CPFSGT REG, 0
:
:
?
After Instruction
If REG
PC
If REG
PC
<
=
≥
=
W;
Address (LESS)
W;
Before Instruction
PC
W
=
=
Address (HERE)
Address (NLESS)
?
After Instruction
If REG
PC
If REG
PC
>
=
≤
=
W;
Address (GREATER)
W;
Address (NGREATER)
© 2007 Microchip Technology Inc.
Preliminary
DS39761B-page 381
PIC18F2682/2685/4682/4685
DAW
Decimal Adjust W Register
DECF
Decrement f
Syntax:
DAW
None
Syntax:
DECF f {,d {,a}}
Operands:
Operation:
Operands:
0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
If [W<3:0> >9] or [DC = 1] then
(W<3:0>) + 6 → W<3:0>;
else
Operation:
(f) – 1 → dest
(W<3:0>) → W<3:0>
Status Affected:
Encoding:
C, DC, N, OV, Z
0000
01da
ffff
ffff
If [W<7:4> >9] or [C = 1] then
(W<7:4>) + 6 → W<7:4>;
C = 1;
Description:
Decrement register ‘f’. If ‘d’ is ‘0’, the
result is stored in W. If ‘d’ is ‘1’, the
result is stored back in register ‘f’
(default).
else
(W<7:4>) → W<7:4>
Status Affected:
Encoding:
C
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank (default).
0000
0000
0000
0111
Description:
DAWadjusts the eight-bit value in W,
resulting from the earlier addition of two
variables (each in packed BCD format)
and produces a correct packed BCD
result.
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f ≤ 95 (5Fh). See
Section 25.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
Words:
Cycles:
1
1
Words:
Cycles:
1
1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Q Cycle Activity:
Q1
Decode
Read
register W
Process
Data
Write
W
Q2
Q3
Q4
Example 1:
Decode
Read
register ‘f’
Process
Data
Write to
destination
DAW
Before Instruction
W
=
=
=
A5h
0
0
Example:
DECF
CNT,
1, 0
C
Before Instruction
DC
CNT
Z
After Instruction
=
01h
0
After Instruction
=
W
=
=
=
05h
1
0
C
DC
CNT
Z
=
=
00h
1
Example 2:
Before Instruction
W
=
=
=
CEh
0
0
C
DC
After Instruction
W
=
=
=
34h
1
0
C
DC
DS39761B-page 382
Preliminary
© 2007 Microchip Technology Inc.
PIC18F2682/2685/4682/4685
DECFSZ
Decrement f, Skip if 0
DCFSNZ
Decrement f, Skip if Not 0
Syntax:
DECFSZ f {,d {,a}}
Syntax:
DCFSNZ f {,d {,a}}
Operands:
0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
Operands:
0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
Operation:
(f) – 1 → dest,
Operation:
(f) – 1 → dest,
skip if result = 0
skip if result ≠ 0
Status Affected:
Encoding:
None
Status Affected:
Encoding:
None
0010
11da
ffff
ffff
0100
11da
ffff
ffff
Description:
The contents of register ‘f’ are
Description:
The contents of register ‘f’ are
decremented. If ‘d’ is ‘0’, the result is
placed in W. If ‘d’ is ‘1’, the result is
placed back in register ‘f’ (default).
decremented. If ‘d’ is ‘0’, the result is
placed in W. If ‘d’ is ‘1’, the result is
placed back in register ‘f’ (default).
If the result is ‘0’, the next instruction
which is already fetched is discarded
and a NOPis executed instead, making
it a two-cycle instruction.
If the result is not ‘0’, the next
instruction which is already fetched is
discarded and a NOPis executed
instead, making it a two-cycle
instruction.
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank (default).
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank (default).
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f ≤ 95 (5Fh). See
Section 25.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f ≤ 95 (5Fh). See
Section 25.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
Words:
Cycles:
1
Words:
Cycles:
1
1(2)
1(2)
Note: 3 cycles if skip and followed
by a 2-word instruction.
Note: 3 cycles if skip and followed
by a 2-word instruction.
Q Cycle Activity:
Q1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Q2
Q3
Q4
Decode
Read
register ‘f’
Process
Data
Write to
destination
Decode
Read
Process
Data
Write to
destination
register ‘f’
If skip:
Q1
If skip:
Q1
Q2
Q3
Q4
Q2
Q3
Q4
No
No
No
No
operation
operation
operation
operation
No
No
No
No
operation
operation
operation
operation
If skip and followed by 2-word instruction:
If skip and followed by 2-word instruction:
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
No
No
No
No
operation
operation
operation
operation
No
No
No
No
operation
operation
operation
operation
No
No
No
No
operation
operation
operation
operation
No
No
No
No
operation
operation
operation
operation
Example:
HERE
DECFSZ
GOTO
CNT, 1, 1
LOOP
Example:
HERE
ZERO
NZERO
DCFSNZ TEMP, 1, 0
:
:
CONTINUE
Before Instruction
PC
After Instruction
Before Instruction
TEMP
After Instruction
=
Address (HERE)
=
?
CNT
=
CNT – 1
0;
If CNT
=
=
≠
=
TEMP
If TEMP
PC
If TEMP
PC
=
=
=
≠
=
TEMP – 1,
0;
PC
Address (CONTINUE)
0;
If CNT
PC
Address (ZERO)
0;
Address (HERE + 2)
Address (NZERO)
© 2007 Microchip Technology Inc.
Preliminary
DS39761B-page 383
PIC18F2682/2685/4682/4685
GOTO
Unconditional Branch
INCF
Increment f
Syntax:
GOTO
k
Syntax:
INCF f {,d {,a}}
Operands:
Operation:
Status Affected:
0 ≤ k ≤ 1048575
k → PC<20:1>
None
Operands:
0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
Operation:
(f) + 1 → dest
Encoding:
Status Affected:
Encoding:
C, DC, N, OV, Z
1st word (k<7:0>)
2nd word(k<19:8>)
1110
1111
1111
kkk
k kkk
kkkk
kkkk
kkkk
7
0
8
0010
10da
ffff
ffff
k
19
Description:
The contents of register ‘f’ are
Description:
GOTOallows an unconditional branch
incremented. If ‘d’ is ‘0’, the result is
placed in W. If ‘d’ is ‘1’, the result is
placed back in register ‘f’ (default).
anywhere within entire 2-Mbyte memory
range. The 20-bit value ‘k’ is loaded into
PC<20:1>. GOTOis always a two-cycle
instruction.
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank (default).
Words:
Cycles:
2
2
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f ≤ 95 (5Fh). See
Section 25.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read literal
‘k’<7:0>,
No
operation
Read literal
‘k’<19:8>,
Write to PC
No
operation
No
operation
No
operation
No
operation
Words:
Cycles:
1
1
Q Cycle Activity:
Q1
Example:
GOTO THERE
Q2
Q3
Q4
After Instruction
Decode
Read
register ‘f’
Process
Data
Write to
destination
PC
=
Address (THERE)
Example:
INCF
CNT, 1, 0
Before Instruction
CNT
Z
=
FFh
0
=
=
=
C
?
DC
?
After Instruction
CNT
Z
=
00h
1
=
=
=
C
1
DC
1
DS39761B-page 384
Preliminary
© 2007 Microchip Technology Inc.
PIC18F2682/2685/4682/4685
INFSNZ
Increment f, Skip if Not 0
INCFSZ
Increment f, Skip if 0
Syntax:
INFSNZ f {,d {,a}}
Syntax:
INCFSZ f {,d {,a}}
Operands:
0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
Operands:
0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
Operation:
(f) + 1 → dest,
skip if result ≠ 0
Operation:
(f) + 1 → dest,
skip if result = 0
Status Affected:
Encoding:
None
Status Affected:
Encoding:
None
0100
10da
ffff
ffff
0011
11da
ffff
ffff
Description:
The contents of register ‘f’ are
Description:
The contents of register ‘f’ are
incremented. If ‘d’ is ‘0’, the result is
placed in W. If ‘d’ is ‘1’, the result is
placed back in register ‘f’ (default).
incremented. If ‘d’ is ‘0’, the result is
placed in W. If ‘d’ is ‘1’, the result is
placed back in register ‘f’ (default).
If the result is not ‘0’, the next
instruction which is already fetched is
discarded and a NOPis executed
instead, making it a two-cycle
instruction.
If the result is ‘0’, the next instruction
which is already fetched is discarded
and a NOPis executed instead, making
it a two-cycle instruction.
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank (default).
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank (default).
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f ≤ 95 (5Fh). See
Section 25.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f ≤ 95 (5Fh). See
Section 25.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
Words:
Cycles:
1
Words:
Cycles:
1
1(2)
1(2)
Note: 3 cycles if skip and followed
Note: 3 cycles if skip and followed
by a 2-word instruction.
by a 2-word instruction.
Q Cycle Activity:
Q1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Q2
Q3
Q4
Decode
Read
register ‘f’
Process
Data
Write to
destination
Decode
Read
register ‘f’
Process
Data
Write to
destination
If skip:
Q1
If skip:
Q1
Q2
Q3
Q4
Q2
Q3
Q4
No
No
No
No
No
No
No
No
operation
operation
operation
operation
operation
operation
operation
operation
If skip and followed by 2-word instruction:
If skip and followed by 2-word instruction:
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
No
No
No
No
No
No
No
No
operation
operation
operation
operation
operation
operation
operation
operation
No
No
No
No
No
No
No
No
operation
operation
operation
operation
operation
operation
operation
operation
Example:
HERE
NZERO
ZERO
INCFSZ
:
:
CNT, 1, 0
Example:
HERE
ZERO
NZERO
INFSNZ REG, 1, 0
Before Instruction
PC
After Instruction
Before Instruction
PC
After Instruction
=
Address (HERE)
=
Address (HERE)
REG
If REG
PC
If REG
PC
=
REG + 1
CNT
If CNT
PC
If CNT
PC
=
CNT + 1
≠
=
=
=
0;
=
=
≠
=
0;
Address (NZERO)
0;
Address (ZERO)
Address (ZERO)
0;
Address (NZERO)
© 2007 Microchip Technology Inc.
Preliminary
DS39761B-page 385
PIC18F2682/2685/4682/4685
IORLW
Inclusive OR Literal with W
IORWF
Inclusive OR W with f
Syntax:
IORLW
k
Syntax:
IORWF f {,d {,a}}
Operands:
Operation:
Status Affected:
Encoding:
Description:
0 ≤ k ≤ 255
(W) .OR. k → W
N, Z
Operands:
0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
Operation:
(W) .OR. (f) → dest
0000
1001
kkkk
kkkk
Status Affected:
Encoding:
N, Z
The contents of W are ORed with the
eight-bit literal ‘k’. The result is placed
in W.
0001
00da
ffff
ffff
Description:
Inclusive OR W with register ‘f’. If ‘d’ is
‘0’, the result is placed in W. If ‘d’ is ‘1’,
the result is placed back in register ‘f’
(default).
Words:
Cycles:
1
1
Q Cycle Activity:
Q1
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank (default).
Q2
Q3
Q4
Decode
Read
literal ‘k’
Process
Data
Write to W
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f ≤ 95 (5Fh). See
Section 25.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
Example:
IORLW
35h
Before Instruction
W
=
9Ah
BFh
After Instruction
W
=
Words:
Cycles:
1
1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
register ‘f’
Process
Data
Write to
destination
Example:
IORWF RESULT, 0, 1
Before Instruction
RESULT =
13h
91h
W
=
After Instruction
RESULT =
13h
93h
W
=
DS39761B-page 386
Preliminary
© 2007 Microchip Technology Inc.
PIC18F2682/2685/4682/4685
LFSR
Load FSR
MOVF
Move f
Syntax:
LFSR f, k
Syntax:
MOVF f {,d {,a}}
Operands:
0 ≤ f ≤ 2
0 ≤ k ≤ 4095
Operands:
0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
Operation:
k → FSRf
Operation:
f → dest
Status Affected:
Encoding:
None
Status Affected:
Encoding:
N, Z
1110
1111
1110
0000
00ff
k kkk
11
kkkk
k kkk
0101
00da
ffff
ffff
7
Description:
The 12-bit literal ‘k’ is loaded into the
file select register pointed to by ‘f’.
Description:
The contents of register ‘f’ are moved to
a destination dependent upon the
status of ‘d’. If ‘d’ is ‘0’, the result is
placed in W. If ‘d’ is ‘1’, the result is
placed back in register ‘f’ (default).
Location ‘f’ can be anywhere in the
256-byte bank.
Words:
Cycles:
2
2
Q Cycle Activity:
Q1
Q2
Q3
Q4
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank (default).
Decode
Read literal
‘k’ MSB
Process
Data
Write
literal ‘k’
MSB to
FSRfH
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f ≤ 95 (5Fh). See
Section 25.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
Decode
Read literal
‘k’ LSB
Process
Data
Write literal
‘k’ to FSRfL
Example:
LFSR 2, 3ABh
After Instruction
FSR2H
FSR2L
=
=
03h
ABh
Words:
Cycles:
1
1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
register ‘f’
Process
Data
Write W
Example:
MOVF
REG, 0, 0
Before Instruction
REG
W
=
=
22h
FFh
After Instruction
REG
W
=
=
22h
22h
© 2007 Microchip Technology Inc.
Preliminary
DS39761B-page 387
PIC18F2682/2685/4682/4685
MOVFF
Move f to f
MOVLB
Move Literal to Low Nibble in BSR
Syntax:
MOVFF f ,f
Syntax:
MOVLW k
s
d
Operands:
0 ≤ f ≤ 4095
Operands:
Operation:
Status Affected:
Encoding:
Description:
0 ≤ k ≤ 255
k → BSR
None
s
0 ≤ f ≤ 4095
d
Operation:
(f ) → f
s
d
Status Affected:
None
0000
0001
kkkk
kkkk
Encoding:
The eight-bit literal ‘k’ is loaded into the
Bank Select Register (BSR). The value
of BSR<7:4> always remains ‘0’,
1st word (source)
2nd word (destin.)
1100
1111
ffff
ffff
ffff
ffff
ffffs
ffffd
regardless of the value of k :k .
7
4
Description:
The contents of source register ‘f ’ are
s
moved to destination register ‘f ’.
Words:
Cycles:
1
1
d
Location of source ‘f ’ can be anywhere
s
in the 4096-byte data space (000h to
FFFh) and location of destination ‘f ’
can also be anywhere from 000h to
FFFh.
Q Cycle Activity:
Q1
d
Q2
Q3
Q4
Decode
Read
literal ‘k’
Process
Data
Write literal
‘k’ to BSR
Either source or destination can be W
(a useful special situation).
MOVFFis particularly useful for
transferring a data memory location to a
peripheral register (such as the transmit
buffer or an I/O port).
Example:
MOVLB
5
Before Instruction
BSR Register =
After Instruction
BSR Register =
02h
05h
The MOVFFinstruction cannot use the
PCL, TOSU, TOSH or TOSL as the
destination register.
Words:
Cycles:
2
2 (3)
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
register ‘f’
(src)
Process
Data
No
operation
Decode
No
operation
No
operation
Write
register ‘f’
(dest)
No dummy
read
Example:
MOVFF
REG1, REG2
Before Instruction
REG1
REG2
=
=
33h
11h
After Instruction
REG1
REG2
=
=
33h
33h
DS39761B-page 388
Preliminary
© 2007 Microchip Technology Inc.
PIC18F2682/2685/4682/4685
MOVLW
Move Literal to W
MOVWF
Move W to f
Syntax:
MOVLW
k
Syntax:
MOVWF f {,a}
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
0 ≤ k ≤ 255
k → W
None
Operands:
0 ≤ f ≤ 255
a ∈ [0,1]
Operation:
(W) → f
Status Affected:
Encoding:
None
0000
1110
kkkk
kkkk
0110
111a
ffff
ffff
The eight-bit literal ‘k’ is loaded into W.
Description:
Move data from W to register ‘f’.
Location ‘f’ can be anywhere in the
256-byte bank.
1
1
Cycles:
Q Cycle Activity:
Q1
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank (default).
Q2
Q3
Q4
Decode
Read
literal ‘k’
Process
Data
Write to W
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f ≤ 95 (5Fh). See
Section 25.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
Example:
MOVLW
5Ah
After Instruction
W
=
5Ah
Words:
Cycles:
1
1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
register ‘f’
Process
Data
Write
register ‘f’
Example:
MOVWF
REG, 0
Before Instruction
W
REG
=
=
4Fh
FFh
After Instruction
W
REG
=
=
4Fh
4Fh
© 2007 Microchip Technology Inc.
Preliminary
DS39761B-page 389
PIC18F2682/2685/4682/4685
MULLW
Multiply Literal with W
MULWF
Multiply W with f
Syntax:
MULLW
k
Syntax:
MULWF f {,a}
Operands:
Operation:
Status Affected:
Encoding:
Description:
0 ≤ k ≤ 255
Operands:
0 ≤ f ≤ 255
a ∈ [0,1]
(W) x k → PRODH:PRODL
Operation:
(W) x (f) → PRODH:PRODL
None
Status Affected:
Encoding:
None
0000
1101
kkkk
kkkk
0000
001a
ffff
ffff
An unsigned multiplication is carried
out between the contents of W and the
8-bit literal ‘k’. The 16-bit result is
placed in the PRODH:PRODL register
pair. PRODH contains the high byte.
Description:
An unsigned multiplication is carried
out between the contents of W and the
register file location ‘f’. The 16-bit
result is stored in the PRODH:PRODL
register pair. PRODH contains the
high byte. Both W and ‘f’ are
W is unchanged.
None of the Status flags are affected.
unchanged.
Note that neither Overflow nor Carry is
possible in this operation. A Zero result
is possible but not detected.
None of the Status flags are affected.
Note that neither Overflow nor Carry is
possible in this operation. A Zero
result is possible but not detected.
Words:
Cycles:
1
1
If ‘a’ is ‘0’, the Access Bank is
selected. If ‘a’ is ‘1’, the BSR is used
to select the GPR bank (default).
Q Cycle Activity:
Q1
Q2
Q3
Q4
If ‘a’ is ‘0’ and the extended
Decode
Read
literal ‘k’
Process
Data
Write
instruction set is enabled, this
instruction operates in Indexed Literal
Offset Addressing mode whenever
f ≤ 95 (5Fh). See Section 25.2.3
“Byte-Oriented and Bit-Oriented
Instructions in Indexed Literal Offset
Mode” for details.
registers
PRODH:
PRODL
Example:
MULLW
0C4h
Before Instruction
W
PRODH
PRODL
=
=
=
E2h
?
?
Words:
Cycles:
1
1
After Instruction
Q Cycle Activity:
Q1
W
PRODH
PRODL
=
=
=
E2h
ADh
08h
Q2
Q3
Q4
Decode
Read
register ‘f’
Process
Data
Write
registers
PRODH:
PRODL
Example:
MULWF
REG, 1
Before Instruction
W
=
=
=
=
C4h
REG
B5h
?
PRODH
PRODL
?
After Instruction
W
=
=
=
=
C4h
B5h
8Ah
94h
REG
PRODH
PRODL
DS39761B-page 390
Preliminary
© 2007 Microchip Technology Inc.
PIC18F2682/2685/4682/4685
NEGF
Negate f
NOP
No Operation
Syntax:
NEGF f {,a}
Syntax:
NOP
Operands:
0 ≤ f ≤ 255
a ∈ [0,1]
Operands:
Operation:
Status Affected:
Encoding:
None
No operation
None
Operation:
( f ) + 1 → f
Status Affected:
Encoding:
N, OV, C, DC, Z
0000
1111
0000
xxxx
0000
xxxx
0000
xxxx
0110
110a
ffff
ffff
Description:
Location ‘f’ is negated using two’s
complement. The result is placed in the
data memory location ‘f’.
Description:
Words:
No operation.
1
1
Cycles:
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank (default).
Q Cycle Activity:
Q1
Q2
Q3
No
operation
Q4
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f ≤ 95 (5Fh). See
Section 25.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
Decode
No
operation
No
operation
Example:
None.
Words:
Cycles:
1
1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
register ‘f’
Process
Data
Write
register ‘f’
Example:
NEGF
REG, 1
Before Instruction
REG
After Instruction
REG
=
0011 1010 [3Ah]
1100 0110 [C6h]
=
© 2007 Microchip Technology Inc.
Preliminary
DS39761B-page 391
PIC18F2682/2685/4682/4685
POP
Pop Top of Return Stack
PUSH
Push Top of Return Stack
Syntax:
POP
Syntax:
PUSH
Operands:
Operation:
Status Affected:
Encoding:
Description:
None
Operands:
Operation:
Status Affected:
Encoding:
Description:
None
(TOS) → bit bucket
(PC + 2) → TOS
None
None
0000
0000
0000
0110
0000
0000
0000
0101
The TOS value is pulled off the return
stack and is discarded. The TOS value
then becomes the previous value that
was pushed onto the return stack.
The PC + 2 is pushed onto the top of
the return stack. The previous TOS
value is pushed down on the stack.
This instruction allows implementing a
software stack by modifying TOS and
then pushing it onto the return stack.
This instruction is provided to enable
the user to properly manage the return
stack to incorporate a software stack.
Words:
Cycles:
1
1
Words:
Cycles:
1
1
Q Cycle Activity:
Q1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Q2
Q3
Q4
Decode
PUSH
No
No
Decode
No
operation
POP TOS
value
No
operation
PC + 2 onto
return stack
operation
operation
Example:
POP
Example:
PUSH
GOTO
NEW
Before Instruction
Before Instruction
TOS
Stack (1 level down)
TOS
PC
=
=
345Ah
0124h
=
=
0031A2h
014332h
After Instruction
After Instruction
PC
=
=
=
0126h
0126h
345Ah
TOS
TOS
PC
=
=
014332h
NEW
Stack (1 level down)
DS39761B-page 392
Preliminary
© 2007 Microchip Technology Inc.
PIC18F2682/2685/4682/4685
RCALL
Relative Call
RESET
Reset
Syntax:
RCALL
n
Syntax:
RESET
None
Operands:
Operation:
-1024 ≤ n ≤ 1023
Operands:
Operation:
(PC) + 2 → TOS,
(PC) + 2 + 2n → PC
Reset all registers and flags that are
affected by a MCLR Reset.
Status Affected:
Encoding:
None
Status Affected:
Encoding:
All
1101
1nnn
nnnn
nnnn
0000
0000
1111
1111
Description:
Subroutine call with a jump up to 1K
from the current location. First, return
address (PC + 2) is pushed onto the
stack. Then, add the 2’s complement
number ‘2n’ to the PC. Since the PC will
have incremented to fetch the next
instruction, the new address will be
PC + 2 + 2n. This instruction is a
two-cycle instruction.
Description:
This instruction provides a way to
execute a MCLR Reset in software.
Words:
Cycles:
1
1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Start
No
No
Reset
operation
operation
Words:
1
2
Cycles:
Example:
RESET
Q Cycle Activity:
Q1
After Instruction
Registers =
Q2
Q3
Q4
Reset Value
Reset Value
Flags*
=
Decode Read literal ‘n’ Process
Write to PC
Data
Push PC to
stack
No
No
No
No
operation
operation
operation
operation
Example:
HERE
RCALL Jump
Before Instruction
PC Address (HERE)
After Instruction
PC
TOS =
=
=
Address (Jump)
Address (HERE + 2)
© 2007 Microchip Technology Inc.
Preliminary
DS39761B-page 393
PIC18F2682/2685/4682/4685
RETFIE
Return from Interrupt
RETLW
Return Literal to W
Syntax:
RETFIE {s}
Syntax:
RETLW k
Operands:
Operation:
s ∈ [0,1]
Operands:
Operation:
0 ≤ k ≤ 255
(TOS) → PC,
k → W,
1 → GIE/GIEH or PEIE/GIEL;
if s = 1,
(TOS) → PC,
PCLATU, PCLATH are unchanged
(WS) → W,
(STATUSS) → STATUS,
(BSRS) → BSR,
Status Affected:
Encoding:
None
0000
1100
kkkk
kkkk
PCLATU, PCLATH are unchanged
Description:
W is loaded with the eight-bit literal ‘k’.
The program counter is loaded from the
top of the stack (the return address).
The high address latch (PCLATH)
remains unchanged.
Status Affected:
Encoding:
GIE/GIEH, PEIE/GIEL.
0000
0000
0001
000s
Description:
Return from interrupt. Stack is popped
and Top-of-Stack (TOS) is loaded into
the PC. Interrupts are enabled by
setting either the high or low priority
global interrupt enable bit. If ‘s’ = 1, the
contents of the shadow registers, WS,
STATUSS and BSRS, are loaded into
their corresponding registers, W,
Words:
Cycles:
1
2
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
literal ‘k’
Process
Data
POP PC
from stack,
Write to W
STATUS and BSR. If ‘s’ = 0, no update
of these registers occurs (default).
No
operation
No
operation
No
operation
No
operation
Words:
Cycles:
1
2
Q Cycle Activity:
Q1
Example:
Q2
Q3
Q4
CALL TABLE; W contains table
; offset value
Decode
No
No
POP PC
; W now has
operation
operation
from stack
; table value
Set GIEH or
GIEL
:
TABLE
ADDWF PCL; W = offset
No
No
No
No
operation
operation
operation
operation
RETLW k0; Begin table
RETLW k1;
Example:
RETFIE
1
:
:
After Interrupt
RETLW kn; End of table
PC
=
=
=
=
=
TOS
WS
W
Before Instruction
BSR
STATUS
GIE/GIEH, PEIE/GIEL
BSRS
W
=
07h
STATUSS
1
After Instruction
W
=
value of kn
DS39761B-page 394
Preliminary
© 2007 Microchip Technology Inc.
PIC18F2682/2685/4682/4685
RETURN
Return from Subroutine
RLCF
Rotate Left f through Carry
Syntax:
RETURN {s}
Syntax:
RLCF f {,d {,a}}
Operands:
Operation:
s ∈ [0,1]
Operands:
0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
(TOS) → PC;
if s = 1,
(WS) → W,
Operation:
(f<n>) → dest<n + 1>,
(f<7>) → C,
(C) → dest<0>
(STATUSS) → STATUS,
(BSRS) → BSR,
PCLATU, PCLATH are unchanged
Status Affected:
Encoding:
C, N, Z
Status Affected:
Encoding:
None
0011
01da
ffff
ffff
0000
0000
0001
001s
Description:
The contents of register ‘f’ are rotated
one bit to the left through the Carry
flag. If ‘d’ is ‘0’, the result is placed in
W. If ‘d’ is ‘1’, the result is stored back
in register ‘f’ (default).
Description:
Return from subroutine. The stack is
popped and the top of the stack (TOS)
is loaded into the program counter. If
‘s’= 1, the contents of the shadow
registers, WS, STATUSS and BSRS,
are loaded into their corresponding
registers, W, STATUS and BSR. If
‘s’ = 0, no update of these registers
occurs (default).
If ‘a’ is ‘0’, the Access Bank is
selected. If ‘a’ is ‘1’, the BSR is used to
select the GPR bank (default).
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction
operates in Indexed Literal Offset
Addressing mode whenever
f ≤ 95 (5Fh). See Section 25.2.3
“Byte-Oriented and Bit-Oriented
Instructions in Indexed Literal Offset
Mode” for details.
Words:
Cycles:
1
2
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
No
operation
Process
Data
POP PC
from stack
register f
C
No
No
No
No
operation
operation
operation
operation
Words:
Cycles:
1
1
Q Cycle Activity:
Q1
Example:
RETURN
Q2
Read
register ‘f’
Q3
Q4
After Interrupt
Decode
Process
Data
Write to
destination
PC = TOS
Example:
RLCF
REG, 0, 0
Before Instruction
REG
C
=
=
1110 0110
0
After Instruction
REG
=
=
=
1110 0110
1100 1100
1
W
C
© 2007 Microchip Technology Inc.
Preliminary
DS39761B-page 395
PIC18F2682/2685/4682/4685
RLNCF
Rotate Left f (No Carry)
RRCF
Rotate Right f through Carry
Syntax:
RLNCF f {,d {,a}}
Syntax:
RRCF f {,d {,a}}
Operands:
0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
Operands:
0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
Operation:
(f<n>) → dest<n + 1>,
(f<7>) → dest<0>
Operation:
(f<n>) → dest<n – 1>,
(f<0>) → C,
(C) → dest<7>
Status Affected:
Encoding:
N, Z
Status Affected:
Encoding:
C, N, Z
0100
01da
ffff
ffff
0011
00da
ffff
ffff
Description:
The contents of register ‘f’ are rotated
one bit to the left. If ‘d’ is ‘0’, the result
is placed in W. If ‘d’ is ‘1’, the result is
stored back in register ‘f’ (default).
Description:
The contents of register ‘f’ are rotated
one bit to the right through the Carry
flag. If ‘d’ is ‘0’, the result is placed in W.
If ‘d’ is ‘1’, the result is placed back in
register ‘f’ (default).
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank (default).
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank (default).
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f ≤ 95 (5Fh). See
Section 25.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f ≤ 95 (5Fh). See
Section 25.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
register f
register f
C
Words:
Cycles:
1
1
Words:
Cycles:
1
1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Q Cycle Activity:
Q1
Decode
Read
register ‘f’
Process
Data
Write to
destination
Q2
Q3
Q4
Decode
Read
register ‘f’
Process
Data
Write to
destination
Example:
RLNCF
REG, 1, 0
Before Instruction
REG
After Instruction
Example:
RRCF
REG, 0, 0
=
1010 1011
0101 0111
Before Instruction
REG
=
REG
C
=
=
1110 0110
0
After Instruction
REG
=
=
=
1110 0110
0111 0011
0
W
C
DS39761B-page 396
Preliminary
© 2007 Microchip Technology Inc.
PIC18F2682/2685/4682/4685
RRNCF
Rotate Right f (No Carry)
SETF
Set f
Syntax:
RRNCF f {,d {,a}}
Syntax:
SETF f {,a}
Operands:
0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
Operands:
0 ≤ f ≤ 255
a ∈ [0,1]
Operation:
FFh → f
Operation:
(f<n>) → dest<n – 1>,
(f<0>) → dest<7>
Status Affected:
Encoding:
None
0110
100a
ffff
ffff
Status Affected:
Encoding:
N, Z
Description:
The contents of the specified register
are set to FFh.
0100
00da
ffff
ffff
Description:
The contents of register ‘f’ are rotated
one bit to the right. If ‘d’ is ‘0’, the result
is placed in W. If ‘d’ is ‘1’, the result is
placed back in register ‘f’ (default).
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank (default).
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f ≤ 95 (5Fh). See
Section 25.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
If ‘a’ is ‘0’, the Access Bank will be
selected, overriding the BSR value. If ‘a’
is ‘1’, then the bank will be selected as
per the BSR value (default).
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f ≤ 95 (5Fh). See
Section 25.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
Words:
Cycles:
1
1
Q Cycle Activity:
Q1
Q2
Q3
Q4
register f
Decode
Read
register ‘f’
Process
Data
Write
register ‘f’
Words:
Cycles:
1
1
Example:
SETF
REG,1
Q Cycle Activity:
Q1
Before Instruction
REG
After Instruction
REG
=
=
5Ah
FFh
Q2
Q3
Q4
Decode
Read
register ‘f’
Process
Data
Write to
destination
Example 1:
RRNCF
REG, 1, 0
Before Instruction
REG
After Instruction
REG
=
1101 0111
1110 1011
RRNCF REG, 0, 0
=
Example 2:
Before Instruction
W
REG
=
=
?
1101 0111
After Instruction
W
REG
=
=
1110 1011
1101 0111
© 2007 Microchip Technology Inc.
Preliminary
DS39761B-page 397
PIC18F2682/2685/4682/4685
SLEEP
Enter Sleep mode
SUBFWB
Subtract f from W with Borrow
Syntax:
SLEEP
None
Syntax:
SUBFWB f {,d {,a}}
Operands:
Operation:
Operands:
0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
00h → WDT,
0 → WDT postscaler,
1 → TO,
Operation:
(W) – (f) – (C) → dest
0 → PD
Status Affected:
Encoding:
N, OV, C, DC, Z
Status Affected:
Encoding:
TO, PD
0101
01da
ffff
ffff
0000
0000
0000
0011
Description:
Subtract register ‘f’ and Carry flag
(borrow) from W (2’s complement
method). If ‘d’ is ‘0’, the result is stored
in W. If ‘d’ is ‘1’, the result is stored in
register ‘f’ (default).
Description:
The Power-Down status bit (PD) is
cleared. The Time-out status bit (TO)
is set. Watchdog Timer and its
postscaler are cleared.
The processor is put into Sleep mode
with the oscillator stopped.
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank (default).
Words:
Cycles:
1
1
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f ≤ 95 (5Fh). See
Section 25.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
No
operation
Process
Data
Go to
Sleep
Words:
Cycles:
1
1
Example:
SLEEP
Before Instruction
Q Cycle Activity:
Q1
TO
PD
=
=
?
?
Q2
Q3
Q4
After Instruction
Decode
Read
register ‘f’
Process
Data
Write to
destination
TO
PD
=
=
1 †
0
Example 1:
SUBFWB
REG, 1, 0
Before Instruction
†
If WDT causes wake-up, this bit is cleared.
REG
W
=
=
=
3
2
1
C
After Instruction
REG
W
C
=
FF
2
=
=
=
=
0
Z
0
1
N
; result is negative
Example 2:
Before Instruction
SUBFWB
REG, 0, 0
REG
W
C
=
=
=
2
5
1
After Instruction
REG
W
C
=
2
3
1
0
=
=
=
=
Z
N
0
; result is positive
Example 3:
Before Instruction
SUBFWB
REG, 1, 0
REG
W
C
=
=
=
1
2
0
After Instruction
REG
W
C
=
0
2
1
1
0
=
=
=
=
Z
; result is zero
N
DS39761B-page 398
Preliminary
© 2007 Microchip Technology Inc.
PIC18F2682/2685/4682/4685
SUBLW
Subtract W from Literal
SUBWF
Subtract W from f
Syntax:
SUBLW
k
Syntax:
SUBWF f {,d {,a}}
Operands:
Operation:
Status Affected:
Encoding:
Description:
0 ≤ k ≤ 255
Operands:
0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
k – (W) → W
N, OV, C, DC, Z
Operation:
(f) – (W) → dest
0000
1000
kkkk
kkkk
Status Affected:
Encoding:
N, OV, C, DC, Z
W is subtracted from the eight-bit
literal ‘k’. The result is placed in W.
0101
11da
ffff
ffff
Description:
Subtract W from register ‘f’ (2’s
complement method). If ‘d’ is ‘0’, the
result is stored in W. If ‘d’ is ‘1’, the
result is stored back in register ‘f’
(default).
Words:
Cycles:
1
1
Q Cycle Activity:
Q1
Q2
Q3
Q4
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank (default).
Decode
Read
literal ‘k’
Process
Data
Write to W
Example 1:
SUBLW 02h
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f ≤ 95 (5Fh). See
Section 25.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
Before Instruction
W
C
=
=
01h
?
After Instruction
W
C
Z
=
01h
=
=
=
1
0
0
; result is positive
Words:
Cycles:
1
1
N
Example 2:
SUBLW 02h
Q Cycle Activity:
Q1
Before Instruction
W
C
=
=
02h
?
Q2
Q3
Q4
Decode
Read
register ‘f’
Process
Data
Write to
destination
After Instruction
W
C
Z
=
00h
=
=
=
1
1
0
; result is zero
Example 1:
SUBWF
REG, 1, 0
Before Instruction
N
REG
W
=
3
2
?
Example 3:
Before Instruction
SUBLW 02h
=
=
C
After Instruction
W
C
=
=
03h
?
REG
W
C
Z
N
=
1
2
1
0
0
=
=
=
=
After Instruction
; result is positive
W
C
Z
=
FFh ; (2’s complement)
=
=
=
0
0
1
; result is negative
Example 2:
Before Instruction
SUBWF
REG, 0, 0
N
REG
W
C
=
=
=
2
2
?
After Instruction
REG
W
C
=
2
0
1
1
0
=
=
=
=
; result is zero
Z
N
Example 3:
Before Instruction
SUBWF
REG, 1, 0
REG
W
C
=
=
=
1
2
?
After Instruction
REG
W
C
=
FFh ; (2’s complement)
2
0
0
1
=
=
=
=
; result is negative
Z
N
© 2007 Microchip Technology Inc.
Preliminary
DS39761B-page 399
PIC18F2682/2685/4682/4685
SUBWFB
Subtract W from f with Borrow
SWAPF
Swap f
Syntax:
SUBWFB f {,d {,a}}
Syntax:
SWAPF f {,d {,a}}
Operands:
0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
Operands:
0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
Operation:
(f) – (W) – (C) → dest
Operation:
(f<3:0>) → dest<7:4>,
(f<7:4>) → dest<3:0>
Status Affected:
Encoding:
N, OV, C, DC, Z
0101
10da
ffff
ffff
Status Affected:
Encoding:
None
Description:
Subtract W and the Carry flag (borrow)
from register ‘f’ (2’s complement
method). If ‘d’ is ‘0’, the result is stored
in W. If ‘d’ is ‘1’, the result is stored back
in register ‘f’ (default).
0011
10da
ffff
ffff
Description:
The upper and lower nibbles of register
‘f’ are exchanged. If ‘d’ is ‘0’, the result
is placed in W. If ‘d’ is ‘1’, the result is
placed in register ‘f’ (default).
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank (default).
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank (default).
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f ≤ 95 (5Fh). See
Section 25.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f ≤ 95 (5Fh). See
Section 25.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
Words:
Cycles:
1
1
Words:
1
1
Cycles:
Q Cycle Activity:
Q1
Q Cycle Activity:
Q1
Q2
Read
register ‘f’
Q3
Process
Data
Q4
Write to
Decode
Q2
Q3
Q4
destination
Decode
Read
register ‘f’
Process
Data
Write to
Example 1:
SUBWFB REG, 1, 0
destination
Before Instruction
REG
=
=
=
19h
0Dh
1
(0001 1001)
(0000 1101)
Example:
SWAPF
REG, 1, 0
W
C
Before Instruction
After Instruction
REG
After Instruction
=
53h
35h
REG
=
0Ch
0Dh
1
(0000 1011)
(0000 1101)
W
=
=
=
=
REG
=
C
Z
0
N
0
; result is positive
Example 2:
SUBWFB REG, 0, 0
Before Instruction
REG
W
C
=
=
=
1Bh
1Ah
0
(0001 1011)
(0001 1010)
After Instruction
REG
W
C
=
1Bh
00h
1
(0001 1011)
=
=
=
=
Z
1
; result is zero
N
0
Example 3:
Before Instruction
SUBWFB REG, 1, 0
REG
=
=
=
03h
0Eh
1
(0000 0011)
(0000 1101)
W
C
After Instruction
REG
=
F5h
(1111 0100)
; [2’s comp]
W
=
=
=
=
0Eh
0
0
1
(0000 1101)
C
Z
N
; result is negative
DS39761B-page 400
Preliminary
© 2007 Microchip Technology Inc.
PIC18F2682/2685/4682/4685
TBLRD
Table Read
TBLRD
Table Read (Continued)
Syntax:
TBLRD ( *; *+; *-; +*)
None
Example 1:
TBLRD *+ ;
Operands:
Operation:
Before Instruction
TABLAT
=
=
=
55h
00A356h
34h
if TBLRD *,
TBLPTR
(Prog Mem (TBLPTR)) → TABLAT,
TBLPTR – No Change;
if TBLRD *+,
(Prog Mem (TBLPTR)) → TABLAT,
(TBLPTR) + 1 → TBLPTR;
if TBLRD *-,
(Prog Mem (TBLPTR)) → TABLAT,
(TBLPTR) – 1 → TBLPTR;
if TBLRD +*,
(TBLPTR) + 1 → TBLPTR,
(Prog Mem (TBLPTR)) → TABLAT
MEMORY(00A356h)
After Instruction
TABLAT
TBLPTR
=
=
34h
00A357h
Example 2:
TBLRD +* ;
Before Instruction
TABLAT
TBLPTR
MEMORY(01A357h)
=
=
=
=
0AAh
01A357h
12h
MEMORY(01A358h)
After Instruction
34h
TABLAT
TBLPTR
=
=
34h
01A358h
Status Affected: None
Encoding:
0000
0000
0000
10nn
nn=0 *
=1 *+
=2 *-
=3 +*
Description:
This instruction is used to read the contents
of Program Memory (P.M.). To address the
program memory, a pointer, called Table
Pointer (TBLPTR), is used.
The TBLPTR (a 21-bit pointer) points to
each byte in the program memory. TBLPTR
has a 2-Mbyte address range.
TBLPTR[0] = 0: Least Significant Byte of
Program Memory Word
TBLPTR[0] = 1: Most Significant Byte of
Program Memory Word
The TBLRDinstruction can modify the value
of TBLPTR as follows:
•
•
•
•
no change
post-increment
post-decrement
pre-increment
Words:
Cycles:
1
2
Q Cycle Activity:
Q1
Q2
No
Q3
No
Q4
Decode
No
operation
operation
operation
No
No operation
No
No operation
(Write
TABLAT)
operation (Read Program operation
Memory)
© 2007 Microchip Technology Inc.
Preliminary
DS39761B-page 401
PIC18F2682/2685/4682/4685
TBLWT
Table Write
TBLWT
Table Write (Continued)
Syntax:
TBLWT ( *; *+; *-; +*)
None
Example 1:
TBLWT *+;
Operands:
Operation:
Before Instruction
if TBLWT*,
TABLAT
TBLPTR
HOLDING REGISTER
(00A356h)
=
=
55h
00A356h
(TABLAT) → Holding Register,
TBLPTR – No Change;
if TBLWT*+,
(TABLAT) → Holding Register,
(TBLPTR) + 1 → TBLPTR;
if TBLWT*-,
(TABLAT) → Holding Register,
(TBLPTR) – 1 → TBLPTR;
if TBLWT+*,
(TBLPTR) + 1 → TBLPTR,
(TABLAT) → Holding Register
=
FFh
After Instructions (table write completion)
TABLAT
TBLPTR
HOLDING REGISTER
(00A356h)
=
=
55h
00A357h
=
55h
Example 2:
TBLWT +*;
Before Instruction
TABLAT
TBLPTR
=
=
34h
01389Ah
Status Affected: None
HOLDING REGISTER
(01389Ah)
=
=
FFh
FFh
Encoding:
0000
0000
0000
11nn
nn=0 *
=1 *+
=2 *-
=3 +*
HOLDING REGISTER
(01389Bh)
After Instruction (table write completion)
TABLAT
TBLPTR
=
=
34h
01389Bh
HOLDING REGISTER
(01389Ah)
Description:
This instruction uses the 3 LSBs of the
TBLPTR to determine which of the
8 holding registers the TABLAT is written to.
The holding registers are used to program
the contents of Program Memory (P.M.).
(Refer to Section 6.0 “Flash Program
Memory” for additional details on
=
=
FFh
34h
HOLDING REGISTER
(01389Bh)
programming Flash memory.)
The TBLPTR (a 21-bit pointer) points to
each byte in the program memory. TBLPTR
has a 2-MBtye address range. The LSb of
the TBLPTR selects which byte of the
program memory location to access.
TBLPTR[0] = 0: Least Significant Byte
of Program Memory
Word
TBLPTR[0] = 1: Most Significant Byte of
Program Memory Word
The TBLWT instruction can modify the
value of TBLPTR as follows:
•
•
•
•
no change
post-increment
post-decrement
pre-increment
Words:
1
2
Cycles:
Q Cycle Activity:
Q1
Q2
No
Q3
No
Q4
No
Decode
operation operation operation
No
No No No
operation operation operation operation
(Read
TABLAT)
(Write to
Holding
Register )
DS39761B-page 402
Preliminary
© 2007 Microchip Technology Inc.
PIC18F2682/2685/4682/4685
TSTFSZ
Test f, Skip if 0
XORLW
Exclusive OR Literal with W
Syntax:
TSTFSZ f {,a}
Syntax:
XORLW k
Operands:
0 ≤ f ≤ 255
a ∈ [0,1]
Operands:
Operation:
Status Affected:
Encoding:
Description:
0 ≤ k ≤ 255
(W) .XOR. k → W
N, Z
Operation:
skip if f = 0
Status Affected:
Encoding:
None
0000
1010
kkkk
kkkk
0110
011a
ffff
ffff
The contents of W are XORed with
the 8-bit literal ‘k’. The result is placed
in W.
Description:
If ‘f’ = 0, the next instruction fetched
during the current instruction execution
is discarded and a NOPis executed,
making this a two-cycle instruction.
Words:
Cycles:
1
1
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank (default).
Q Cycle Activity:
Q1
Q2
Q3
Q4
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f ≤ 95 (5Fh). See
Section 25.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
Decode
Read
literal ‘k’
Process
Data
Write to W
Example:
XORLW 0AFh
Before Instruction
W
=
B5h
1Ah
After Instruction
Words:
Cycles:
1
W
=
1(2)
Note: 3 cycles if skip and followed
by a 2-word instruction.
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
register ‘f’
Process
Data
No
operation
If skip:
Q1
Q2
Q3
Q4
No
No
No
No
operation
operation
operation
operation
If skip and followed by 2-word instruction:
Q1
Q2
Q3
Q4
No
No
No
No
operation
operation
operation
operation
No
No
No
No
operation
operation
operation
operation
Example:
HERE
NZERO
ZERO
TSTFSZ CNT, 1
:
:
Before Instruction
PC
=
Address (HERE)
After Instruction
If CNT
PC
If CNT
PC
=
=
≠
=
00h,
Address (ZERO)
00h,
Address (NZERO)
© 2007 Microchip Technology Inc.
Preliminary
DS39761B-page 403
PIC18F2682/2685/4682/4685
XORWF
Exclusive OR W with f
Syntax:
XORWF f {,d {,a}}
Operands:
0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
Operation:
(W) .XOR. (f) → dest
Status Affected:
Encoding:
N, Z
0001
10da
ffff
ffff
Description:
Exclusive OR the contents of W with
register ‘f’. If ‘d’ is ‘0’, the result is stored
in W. If ‘d’ is ‘1’, the result is stored back
in the register ‘f’ (default).
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank (default).
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f ≤ 95 (5Fh). See
Section 25.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
Words:
Cycles:
1
1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
register ‘f’
Process
Data
Write to
destination
Example:
XORWF
REG, 1, 0
Before Instruction
REG
W
=
=
AFh
B5h
After Instruction
REG
W
=
=
1Ah
B5h
DS39761B-page 404
Preliminary
© 2007 Microchip Technology Inc.
PIC18F2682/2685/4682/4685
A summary of the instructions in the extended instruc-
tion set is provided in Table 25-3. Detailed descriptions
are provided in Section 25.2.2 “Extended Instruction
Set”. The opcode field descriptions in Table 25-1 apply
to both the standard and extended PIC18 instruction
sets.
25.2 Extended Instruction Set
In addition to the standard 75 instructions of the PIC18
instruction set, PIC18F2682/2685/4682/4685 devices
also provide an optional extension to the core CPU
functionality. The added features include eight
additional instructions that augment indirect and
indexed addressing operations and the implementation
of Indexed Literal Offset Addressing mode for many of
the standard PIC18 instructions.
Note:
The instruction set extension and the
Indexed Literal Offset Addressing mode
were designed for optimizing applications
written in C; the user may likely never use
these instructions directly in assembler.
The syntax for these commands is pro-
vided as a reference for users who may be
reviewing code that has been generated
by a compiler.
The additional features are disabled by default. To
enable them, users must set the XINST Configuration
bit.
The instructions in the extended set can all be
classified as literal operations, which either manipulate
the File Select Registers or use them for indexed
addressing. Two of the instructions, ADDFSR and
SUBFSR, each have an additional special instantiation
for using FSR2. These versions (ADDULNK and
SUBULNK) allow for automatic return after execution.
25.2.1
EXTENDED INSTRUCTION SYNTAX
Most of the extended instructions use indexed
arguments, using one of the File Select Registers and
some offset to specify a source or destination register.
When an argument for an instruction serves as part of
indexed addressing, it is enclosed in square brackets
(“[ ]”). This is done to indicate that the argument is used
as an index or offset. MPASM™ Assembler will flag an
error if it determines that an index or offset value is not
bracketed.
The extended instructions are specifically implemented
to optimize re-entrant program code (that is, code that
is recursive or that uses a software stack) written in
high-level languages, particularly C. Among other
things, they allow users working in high-level
languages to perform certain operations on data
structures more efficiently. These include:
When the extended instruction set is enabled, brackets
are also used to indicate index arguments in bit-
oriented and byte-oriented instructions. This is in
addition to other changes in their syntax. For more
details, see Section 25.2.3.1 “Extended Instruction
Syntax with Standard PIC18 Commands”.
• Dynamic allocation and deallocation of software
stack space when entering and leaving
subroutines
• Function Pointer invocation
• Software Stack Pointer manipulation
• Manipulation of variables located in a software
stack
Note:
In the past, square brackets have been
used to denote optional arguments in the
PIC18 and earlier instruction sets. In this
text and going forward, optional arguments
are denoted by braces (“{ }”).
TABLE 25-3: EXTENSIONS TO THE PIC18 INSTRUCTION SET
16-Bit Instruction Word
MSb LSb
Mnemonic,
Operands
Status
Affected
Description
Cycles
ADDFSR
ADDULNK
CALLW
f, k
k
Add literal to FSR
Add literal to FSR2 and return
Call subroutine using WREG
1
2
2
2
1110 1000 ffkk kkkk
1110 1000 11kk kkkk
0000 0000 0001 0100
1110 1011 0zzz zzzz
1111 ffff ffff ffff
1110 1011 1zzz zzzz
1111 xxxx xzzz zzzz
1110 1010 kkkk kkkk
None
None
None
None
MOVSF
zs, fd Move zs (source) to 1st word
fd (destination) 2nd word
zs, zd Move zs (source) to 1st word
zd (destination) 2nd word
MOVSS
PUSHL
2
1
None
None
k
Store literal at FSR2,
decrement FSR2
SUBFSR
SUBULNK
f, k
k
Subtract literal from FSR
Subtract literal from FSR2 and
return
1
2
1110 1001 ffkk kkkk
1110 1001 11kk kkkk
None
None
© 2007 Microchip Technology Inc.
Preliminary
DS39761B-page 405
PIC18F2682/2685/4682/4685
25.2.2
EXTENDED INSTRUCTION SET
ADDFSR
Add Literal to FSR
ADDULNK
Add Literal to FSR2 and Return
Syntax:
ADDFSR f, k
Syntax:
ADDULNK k
Operands:
0 ≤ k ≤ 63
f ∈ [ 0, 1, 2 ]
FSR(f) + k → FSR(f)
Operands:
Operation:
0 ≤ k ≤ 63
FSR2 + k → FSR2,
PC = (TOS)
Operation:
Status Affected:
Encoding:
None
Status Affected: None
1110
1000
ffkk
kkkk
Encoding:
1110
1000
11kk
kkkk
Description:
The 6-bit literal ‘k’ is added to the
contents of the FSR specified by ‘f’.
Description:
The 6-bit literal ‘k’ is added to the
contents of FSR2. A RETURNis then
executed by loading the PC with the
TOS.
Words:
1
1
Cycles:
The instruction takes two cycles to
execute; a NOPis performed during the
second cycle.
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
literal ‘k’
Process
Data
Write to
FSR
This may be thought of as a special case
of the ADDFSRinstruction, where f = 3
(binary ‘11’); it operates only on FSR2.
Words:
Cycles:
1
2
Example:
ADDFSR 2, 23h
Before Instruction
FSR2
After Instruction
FSR2
=
03FFh
0422h
Q Cycle Activity:
Q1
Q2
Q3
Q4
=
Decode
Read
literal ‘k’
Process
Data
Write to
FSR
No
No
No
No
Operation
Operation
Operation
Operation
Example:
ADDULNK 23h
Before Instruction
FSR2
PC
TOS
=
=
=
03FFh
0100h
02AFh
After Instruction
FSR2
PC
TOS
=
=
=
0422h
02AFh
TOS – 1
Note:
All PIC18 instructions may take an optional label argument preceding the instruction mnemonic for use in
symbolic addressing. If a label is used, the instruction syntax then becomes: {label} instruction argument(s).
DS39761B-page 406
Preliminary
© 2007 Microchip Technology Inc.
PIC18F2682/2685/4682/4685
CALLW
Subroutine Call Using WREG
MOVSF
Move Indexed to f
Syntax:
CALLW
None
Syntax:
MOVSF [z ], f
s
d
Operands:
Operation:
Operands:
0 ≤ z ≤ 127
s
0 ≤ f ≤ 4095
d
(PC + 2) → TOS,
(W) → PCL,
Operation:
((FSR2) + z ) → f
s
d
(PCLATH) → PCH,
(PCLATU) → PCU
Status Affected:
None
Encoding:
Status Affected:
Encoding:
None
1st word (source)
2nd word (destin.)
1110
1111
1011
ffff
0zzz
ffff
zzzz
ffff
s
0000
0000
0001
0100
d
Description
First, the return address (PC + 2) is
pushed onto the return stack. Next, the
contents of W are written to PCL; the
existing value is discarded. Then, the
contents of PCLATH and PCLATU are
latched into PCH and PCU,
respectively. The second cycle is
executed as a NOPinstruction while the
new next instruction is fetched.
Description:
The contents of the source register are
moved to destination register ‘f ’. The
d
actual address of the source register is
determined by adding the 7-bit literal
offset ‘z ’ in the first word to the value of
s
FSR2. The address of the destination
register is specified by the 12-bit literal
‘f ’ in the second word. Both addresses
d
can be anywhere in the 4096-byte data
space (000h to FFFh).
Unlike CALL, there is no option to
update W, STATUS or BSR.
The MOVSFinstruction cannot use the
PCL, TOSU, TOSH or TOSL as the
destination register.
Words:
Cycles:
1
2
If the resultant source address points to
an indirect addressing register, the
value returned will be 00h.
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
WREG
Push PC to
stack
No
operation
Words:
Cycles:
2
2
No
No
No
No
Q Cycle Activity:
Q1
operation
operation
operation
operation
Q2
Q3
Q4
Decode
Determine
source addr source addr source reg
Determine
Read
Example:
HERE
CALLW
Before Instruction
Decode
No
operation
No
operation
Write
register ‘f’
(dest)
PC
=
address (HERE)
PCLATH =
PCLATU =
10h
00h
06h
No dummy
read
W
=
After Instruction
PC
=
001006h
TOS
=
address (HERE + 2)
Example:
MOVSF
[05h], REG2
PCLATH =
PCLATU =
W
10h
00h
06h
Before Instruction
=
FSR2
=
80h
33h
Contents
of 85h
REG2
=
=
11h
After Instruction
FSR2
=
80h
Contents
of 85h
REG2
=
=
33h
33h
© 2007 Microchip Technology Inc.
Preliminary
DS39761B-page 407
PIC18F2682/2685/4682/4685
MOVSS
Move Indexed to Indexed
PUSHL
Store Literal at FSR2, Decrement FSR2
Syntax:
MOVSS [z ], [z ]
Syntax:
PUSHL k
s
d
Operands:
0 ≤ z ≤ 127
s
Operands:
Operation:
0 ≤ k ≤ 255
0 ≤ z ≤ 127
d
k → (FSR2),
FSR2 – 1 → FSR2
Operation:
((FSR2) + z ) → ((FSR2) + z )
s d
Status Affected:
Encoding:
None
Status Affected: None
Encoding:
1111
1010
kkkk
kkkk
1st word (source)
2nd word (dest.)
Description
1110
1111
1011
xxxx
1zzz
xzzz
zzzz
zzzz
s
d
Description:
The 8-bit literal ‘k’ is written to the data
memory address specified by FSR2. FSR2 is
decremented by 1 after the operation.
The contents of the source register are
moved to the destination register. The
addresses of the source and destination
registers are determined by adding the
This instruction allows users to push values
onto a software stack.
Words:
Cycles:
1
1
7-bit literal offsets ‘z ’ or ‘z ’,
s
d
respectively, to the value of FSR2. Both
registers can be located anywhere in
the 4096-byte data memory space
(000h to FFFh).
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read ‘k’
Process
data
Write to
destination
The MOVSSinstruction cannot use the
PCL, TOSU, TOSH or TOSL as the
destination register.
If the resultant source address points to
an indirect addressing register, the
value returned will be 00h. If the
resultant destination address points to
an indirect addressing register, the
instruction will execute as a NOP.
Example:
PUSHL 08h
Before Instruction
FSR2H:FSR2L
Memory (01ECh)
=
=
01ECh
00h
After Instruction
Words:
2
2
FSR2H:FSR2L
Memory (01ECh)
=
=
01EBh
08h
Cycles:
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Determine
Determine
Read
source addr source addr source reg
Decode
Determine
dest addr
Determine
dest addr
Write
to dest reg
Example:
MOVSS [05h], [06h]
Before Instruction
FSR2
=
=
=
80h
33h
11h
Contents
of 85h
Contents
of 86h
After Instruction
FSR2
=
=
=
80h
33h
33h
Contents
of 85h
Contents
of 86h
DS39761B-page 408
Preliminary
© 2007 Microchip Technology Inc.
PIC18F2682/2685/4682/4685
SUBFSR
Subtract Literal from FSR
SUBULNK
Subtract Literal from FSR2 and Return
Syntax:
SUBFSR f, k
Syntax:
SUBULNK k
Operands:
0 ≤ k ≤ 63
f ∈ [ 0, 1, 2 ]
FSRf – k → FSRf
Operands:
Operation:
0 ≤ k ≤ 63
FSR2 – k → FSR2,
(TOS) → PC
Operation:
Status Affected:
Encoding:
None
Status Affected: None
1110
1001
ffkk
kkkk
Encoding:
1110
1001
11kk
kkkk
Description:
The 6-bit literal ‘k’ is subtracted from
the contents of the FSR specified
by ‘f’.
Description:
The 6-bit literal ‘k’ is subtracted from the
contents of the FSR2. A RETURNis then
executed by loading the PC with the TOS.
Words:
1
1
The instruction takes two cycles to execute;
a NOPis performed during the second cycle.
Cycles:
This may be thought of as a special case of
the SUBFSRinstruction, where f = 3 (binary
‘11’); it operates only on FSR2.
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
register ‘f’
Process
Data
Write to
destination
Words:
1
2
Cycles:
Q Cycle Activity:
Q1
Example:
SUBFSR 2, 23h
03FFh
Q2
Q3
Q4
Before Instruction
FSR2
After Instruction
FSR2
Decode
Read
register ‘f’
Process
Data
Write to
destination
=
No
Operation
No
Operation
No
Operation
No
Operation
=
03DCh
Example:
SUBULNK 23h
Before Instruction
FSR2
PC
=
=
03FFh
0100h
After Instruction
FSR2
PC
=
=
03DCh
(TOS)
© 2007 Microchip Technology Inc.
Preliminary
DS39761B-page 409
PIC18F2682/2685/4682/4685
25.2.3
BYTE-ORIENTED AND
BIT-ORIENTED INSTRUCTIONS IN
INDEXED LITERAL OFFSET MODE
25.2.3.1
Extended Instruction Syntax with
Standard PIC18 Commands
When the extended instruction set is enabled, the file
register argument, ‘f’, in the standard byte-oriented and
bit-oriented commands, is replaced with the literal off-
set value, ‘k’. As already noted, this occurs only when
‘f’ is less than or equal to 5Fh. When an offset value is
used, it must be indicated by square brackets (“[ ]”). As
with the extended instructions, the use of brackets indi-
cates to the compiler that the value is to be interpreted
as an index or an offset. Omitting the brackets, or using
a value greater than 5Fh within brackets, will generate
an error in the MPASM™ Assembler.
Note:
Enabling the PIC18 instruction set
extension may cause legacy applications
to behave erratically or fail entirely.
In addition to eight new commands in the extended set,
enabling the extended instruction set also enables
Indexed Literal Offset Addressing mode (Section 5.6.1
“Indexed Addressing with Literal Offset”). This has
a significant impact on the way that many commands of
the standard PIC18 instruction set are interpreted.
When the extended set is disabled, addresses embed-
ded in opcodes are treated as literal memory locations:
either as a location in the Access Bank (a = 0), or in a
GPR bank designated by the BSR (a = 1). When the
extended instruction set is enabled and a = 0, however,
a file register argument of 5Fh or less is interpreted as
an offset from the pointer value in FSR2 and not as a
literal address. For practical purposes, this means that
all instructions that use the Access RAM bit as an
argument – that is, all bit-oriented and byte-oriented
instructions, or almost half of the core PIC18 instructions
– may behave differently when the extended instruction
set is enabled.
If the index argument is properly bracketed for Indexed
Literal Offset Addressing, the Access RAM argument is
never specified; it will automatically be assumed to be
‘0’. This is in contrast to standard operation (extended
instruction set disabled) when ‘a’ is set on the basis of
the target address. Declaring the Access RAM bit in
this mode will also generate an error in the MPASM
Assembler.
The destination argument, ‘d’, functions as before.
In the latest versions of the MPASM Assembler,
language support for the extended instruction set must
be explicitly invoked. This is done with either the
command line option, /y, or the PE directive in the
source listing.
When the content of FSR2 is 00h, the boundaries of the
Access RAM are essentially remapped to their original
values. This may be useful in creating backward
compatible code. If this technique is used, it may be
necessary to save the value of FSR2 and restore it
when moving back and forth between ‘C’ and assembly
routines in order to preserve the Stack Pointer. Users
must also keep in mind the syntax requirements of the
extended instruction set (see Section 25.2.3.1
“Extended Instruction Syntax with Standard PIC18
Commands”).
25.2.4
CONSIDERATIONS WHEN
ENABLING THE EXTENDED
INSTRUCTION SET
It is important to note that the extensions to the instruc-
tion set may not be beneficial to all users. In particular,
users who are not writing code that uses a software
stack may not benefit from using the extensions to the
instruction set.
Additionally, the Indexed Literal Offset Addressing
mode may create issues with legacy applications
written to the PIC18 assembler. This is because
instructions in the legacy code may attempt to address
registers in the Access Bank below 5Fh. Since these
addresses are interpreted as literal offsets to FSR2
when the instruction set extension is enabled, the
application may read or write to the wrong data
addresses.
Although the Indexed Literal Offset Addressing mode
can be very useful for dynamic stack and pointer
manipulation, it can also be very annoying if a simple
arithmetic operation is carried out on the wrong
register. Users who are accustomed to the PIC18
programming must keep in mind that, when the
extended instruction set is enabled, register addresses
of 5Fh or less are used for Indexed Literal Offset
Addressing.
When porting an application to the PIC18F2682/2685/
4682/4685, it is very important to consider the type of
code. A large, re-entrant application that is written in ‘C’
and would benefit from efficient compilation will do well
when using the instruction set extensions. Legacy
applications that heavily use the Access Bank will most
likely not benefit from using the extended instruction
set.
Representative examples of typical byte-oriented and
bit-oriented instructions in the Indexed Literal Offset
Addressing mode are provided on the following page to
show how execution is affected. The operand
conditions shown in the examples are applicable to all
instructions of these types.
DS39761B-page 410
Preliminary
© 2007 Microchip Technology Inc.
PIC18F2682/2685/4682/4685
ADD W to Indexed
(Indexed Literal Offset mode)
Bit Set Indexed
BSF
ADDWF
(Indexed Literal Offset mode)
Syntax:
ADDWF
[k] {,d}
Syntax:
BSF [k], b
Operands:
0 ≤ k ≤ 95
d ∈ [0,1]
a = 0
Operands:
0 ≤ f ≤ 95
0 ≤ b ≤ 7
a = 0
Operation:
(W) + ((FSR2) + k) → dest
Operation:
1 → ((FSR2 + k))<b>
Status Affected: N, OV, C, DC, Z
Status Affected:
Encoding:
None
Encoding:
0010
01d0
kkkk
kkkk
1000
bbb0
kkkk
kkkk
Description:
The contents of W are added to the contents
of the register indicated by FSR2, offset by the
value ‘k’.
Description:
Bit ‘b’ of the register indicated by FSR2,
offset by the value ‘k’, is set.
Words:
Cycles:
1
1
If ‘d’ is ‘0’, the result is stored in W. If ‘d’ is ‘1’,
the result is stored back in register ‘f’ (default).
Q Cycle Activity:
Q1
Words:
Cycles:
1
1
Q2
Q3
Q4
Decode
Read
register ‘f’
Process
Data
Write to
destination
Q Cycle Activity:
Q1
Q2
Q3
Q4
Example:
BSF
[FLAG_OFST], 7
Decode
Read ‘k’
Process
Data
Write to
destination
Before Instruction
FLAG_OFST
FSR2
=
=
0Ah
0A00h
Example:
ADDWF
[OFST],0
Contents
of 0A0Ah
Before Instruction
=
55h
D5h
W
OFST
FSR2
=
=
=
17h
After Instruction
Contents
2Ch
0A00h
of 0A0Ah
=
Contents
of 0A2Ch
=
20h
After Instruction
W
=
=
37h
20h
Contents
of 0A2Ch
Set Indexed
(Indexed Literal Offset mode)
SETF
Syntax:
SETF [k]
Operands:
Operation:
Status Affected:
Encoding:
Description:
0 ≤ k ≤ 95
FFh → ((FSR2) + k)
None
0110
1000
kkkk
kkkk
The contents of the register indicated by
FSR2, offset by ‘k’, are set to FFh.
Words:
Cycles:
1
1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read ‘k’
Process
Data
Write
register
Example:
SETF
[OFST]
2Ch
Before Instruction
OFST
=
=
FSR2
0A00h
Contents
of 0A2Ch
=
00h
After Instruction
Contents
of 0A2Ch
=
FFh
© 2007 Microchip Technology Inc.
Preliminary
DS39761B-page 411
PIC18F2682/2685/4682/4685
To develop software for the extended instruction set,
the user must enable support for the instructions and
the Indexed Addressing mode in their language tool(s).
Depending on the environment being used, this may be
done in several ways:
25.2.5
SPECIAL CONSIDERATIONS WITH
MICROCHIP MPLAB® IDE TOOLS
The latest versions of Microchip’s software tools have
been designed to fully support the extended instruction
set of the PIC18F2682/2685/4682/4685 family of
devices. This includes the MPLAB C18 C compiler,
MPASM assembly language and MPLAB Integrated
Development Environment (IDE).
• A menu option, or dialog box within the
environment, that allows the user to configure the
language tool and its settings for the project
• A command line option
When selecting
a
target device for software
• A directive in the source code
development, MPLAB IDE will automatically set default
Configuration bits for that device. The default setting for
the XINST Configuration bit is ‘0’, disabling the extended
instruction set and Indexed Literal Offset Addressing
mode. For proper execution of applications developed to
take advantage of the extended instruction set, XINST
must be set during programming.
These options vary between different compilers,
assemblers and development environments. Users are
encouraged to review the documentation accompany-
ing their development systems for the appropriate
information.
DS39761B-page 412
Preliminary
© 2007 Microchip Technology Inc.
PIC18F2682/2685/4682/4685
26.1 MPLAB Integrated Development
26.0 DEVELOPMENT SUPPORT
The PIC® microcontrollers are supported with a full
range of hardware and software development tools:
Environment Software
The MPLAB IDE software brings an ease of software
development previously unseen in the 8/16-bit micro-
controller market. The MPLAB IDE is a Windows®
operating system-based application that contains:
• Integrated Development Environment
- MPLAB® IDE Software
• Assemblers/Compilers/Linkers
- MPASMTM Assembler
• A single graphical interface to all debugging tools
- Simulator
- MPLAB C18 and MPLAB C30 C Compilers
- MPLINKTM Object Linker/
MPLIBTM Object Librarian
- Programmer (sold separately)
- Emulator (sold separately)
- In-Circuit Debugger (sold separately)
• A full-featured editor with color-coded context
• A multiple project manager
- MPLAB ASM30 Assembler/Linker/Library
• Simulators
- MPLAB SIM Software Simulator
• Emulators
• Customizable data windows with direct edit of
contents
- MPLAB ICE 2000 In-Circuit Emulator
- MPLAB REAL ICE™ In-Circuit Emulator
• In-Circuit Debugger
• High-level source code debugging
• Visual device initializer for easy register
initialization
- MPLAB ICD 2
• Mouse over variable inspection
• Device Programmers
• Drag and drop variables from source to watch
windows
- PICSTART® Plus Development Programmer
- MPLAB PM3 Device Programmer
- PICkit™ 2 Development Programmer
• Extensive on-line help
• Integration of select third party tools, such as
HI-TECH Software C Compilers and IAR
C Compilers
• Low-Cost Demonstration and Development
Boards and Evaluation Kits
The MPLAB IDE allows you to:
• Edit your source files (either assembly or C)
• One touch assemble (or compile) and download
to PIC MCU emulator and simulator tools
(automatically updates all project information)
• Debug using:
- Source files (assembly or C)
- Mixed assembly and C
- Machine code
MPLAB IDE supports multiple debugging tools in a
single development paradigm, from the cost-effective
simulators, through low-cost in-circuit debuggers, to
full-featured emulators. This eliminates the learning
curve when upgrading to tools with increased flexibility
and power.
© 2007 Microchip Technology Inc.
Preliminary
DS39761B-page 413
PIC18F2682/2685/4682/4685
26.2 MPASM Assembler
26.5 MPLAB ASM30 Assembler, Linker
and Librarian
The MPASM Assembler is a full-featured, universal
macro assembler for all PIC MCUs.
MPLAB ASM30 Assembler produces relocatable
machine code from symbolic assembly language for
dsPIC30F devices. MPLAB C30 C Compiler uses the
assembler to produce its object file. The assembler
generates relocatable object files that can then be
archived or linked with other relocatable object files and
archives to create an executable file. Notable features
of the assembler include:
The MPASM Assembler generates relocatable object
files for the MPLINK Object Linker, Intel® standard HEX
files, MAP files to detail memory usage and symbol
reference, absolute LST files that contain source lines
and generated machine code and COFF files for
debugging.
The MPASM Assembler features include:
• Integration into MPLAB IDE projects
• Support for the entire dsPIC30F instruction set
• Support for fixed-point and floating-point data
• Command line interface
• User-defined macros to streamline
assembly code
• Rich directive set
• Conditional assembly for multi-purpose
source files
• Flexible macro language
• MPLAB IDE compatibility
• Directives that allow complete control over the
assembly process
26.6 MPLAB SIM Software Simulator
26.3 MPLAB C18 and MPLAB C30
C Compilers
The MPLAB SIM Software Simulator allows code
development in a PC-hosted environment by simulat-
ing the PIC MCUs and dsPIC® DSCs on an instruction
level. On any given instruction, the data areas can be
examined or modified and stimuli can be applied from
a comprehensive stimulus controller. Registers can be
logged to files for further run-time analysis. The trace
buffer and logic analyzer display extend the power of
the simulator to record and track program execution,
actions on I/O, most peripherals and internal registers.
The MPLAB C18 and MPLAB C30 Code Development
Systems are complete ANSI
C
compilers for
Microchip’s PIC18 and PIC24 families of microcontrol-
lers and the dsPIC30 and dsPIC33 family of digital sig-
nal controllers. These compilers provide powerful
integration capabilities, superior code optimization and
ease of use not found with other compilers.
For easy source level debugging, the compilers provide
symbol information that is optimized to the MPLAB IDE
debugger.
The MPLAB SIM Software Simulator fully supports
symbolic debugging using the MPLAB C18 and
MPLAB C30 C Compilers, and the MPASM and
MPLAB ASM30 Assemblers. The software simulator
offers the flexibility to develop and debug code outside
of the hardware laboratory environment, making it an
excellent, economical software development tool.
26.4 MPLINK Object Linker/
MPLIB Object Librarian
The MPLINK Object Linker combines relocatable
objects created by the MPASM Assembler and the
MPLAB C18 C Compiler. It can link relocatable objects
from precompiled libraries, using directives from a
linker script.
The MPLIB Object Librarian manages the creation and
modification of library files of precompiled code. When
a routine from a library is called from a source file, only
the modules that contain that routine will be linked in
with the application. This allows large libraries to be
used efficiently in many different applications.
The object linker/library features include:
• Efficient linking of single libraries instead of many
smaller files
• Enhanced code maintainability by grouping
related modules together
• Flexible creation of libraries with easy module
listing, replacement, deletion and extraction
DS39761B-page 414
Preliminary
© 2007 Microchip Technology Inc.
PIC18F2682/2685/4682/4685
26.7 MPLAB ICE 2000
High-Performance
26.9 MPLAB ICD 2 In-Circuit Debugger
Microchip’s In-Circuit Debugger, MPLAB ICD 2, is a
powerful, low-cost, run-time development tool,
connecting to the host PC via an RS-232 or high-speed
In-Circuit Emulator
The MPLAB ICE 2000 In-Circuit Emulator is intended
to provide the product development engineer with a
complete microcontroller design tool set for PIC
microcontrollers. Software control of the MPLAB ICE
2000 In-Circuit Emulator is advanced by the MPLAB
Integrated Development Environment, which allows
editing, building, downloading and source debugging
from a single environment.
USB interface. This tool is based on the Flash PIC
MCUs and can be used to develop for these and other
PIC MCUs and dsPIC DSCs. The MPLAB ICD 2 utilizes
the in-circuit debugging capability built into the Flash
devices. This feature, along with Microchip’s In-Circuit
Serial ProgrammingTM (ICSPTM) protocol, offers cost-
effective, in-circuit Flash debugging from the graphical
user interface of the MPLAB Integrated Development
Environment. This enables a designer to develop and
debug source code by setting breakpoints, single step-
ping and watching variables, and CPU status and
peripheral registers. Running at full speed enables
testing hardware and applications in real time. MPLAB
ICD 2 also serves as a development programmer for
selected PIC devices.
The MPLAB ICE 2000 is a full-featured emulator
system with enhanced trace, trigger and data monitor-
ing features. Interchangeable processor modules allow
the system to be easily reconfigured for emulation of
different processors. The architecture of the MPLAB
ICE 2000 In-Circuit Emulator allows expansion to
support new PIC microcontrollers.
The MPLAB ICE 2000 In-Circuit Emulator system has
been designed as a real-time emulation system with
advanced features that are typically found on more
expensive development tools. The PC platform and
Microsoft® Windows® 32-bit operating system were
chosen to best make these features available in a
simple, unified application.
26.10 MPLAB PM3 Device Programmer
The MPLAB PM3 Device Programmer is a universal,
CE compliant device programmer with programmable
voltage verification at VDDMIN and VDDMAX for
maximum reliability. It features a large LCD display
(128 x 64) for menus and error messages and a modu-
lar, detachable socket assembly to support various
package types. The ICSP™ cable assembly is included
as a standard item. In Stand-Alone mode, the MPLAB
PM3 Device Programmer can read, verify and program
PIC devices without a PC connection. It can also set
code protection in this mode. The MPLAB PM3
connects to the host PC via an RS-232 or USB cable.
The MPLAB PM3 has high-speed communications and
optimized algorithms for quick programming of large
memory devices and incorporates an SD/MMC card for
file storage and secure data applications.
26.8 MPLAB REAL ICE In-Circuit
Emulator System
MPLAB REAL ICE In-Circuit Emulator System is
Microchip’s next generation high-speed emulator for
Microchip Flash DSC® and MCU devices. It debugs and
programs PIC® and dsPIC® Flash microcontrollers with
the easy-to-use, powerful graphical user interface of the
MPLAB Integrated Development Environment (IDE),
included with each kit.
The MPLAB REAL ICE probe is connected to the design
engineer’s PC using a high-speed USB 2.0 interface and
is connected to the target with either a connector
compatible with the popular MPLAB ICD 2 system
(RJ11) or with the new high speed, noise tolerant, low-
voltage differential signal (LVDS) interconnection
(CAT5).
MPLAB REAL ICE is field upgradeable through future
firmware downloads in MPLAB IDE. In upcoming
releases of MPLAB IDE, new devices will be supported,
and new features will be added, such as software break-
points and assembly code trace. MPLAB REAL ICE
offers significant advantages over competitive emulators
including low-cost, full-speed emulation, real-time
variable watches, trace analysis, complex breakpoints, a
ruggedized probe interface and long (up to three meters)
interconnection cables.
© 2007 Microchip Technology Inc.
Preliminary
DS39761B-page 415
PIC18F2682/2685/4682/4685
26.11 PICSTART Plus Development
Programmer
26.13 Demonstration, Development and
Evaluation Boards
The PICSTART Plus Development Programmer is an
easy-to-use, low-cost, prototype programmer. It
connects to the PC via a COM (RS-232) port. MPLAB
Integrated Development Environment software makes
using the programmer simple and efficient. The
PICSTART Plus Development Programmer supports
most PIC devices in DIP packages up to 40 pins.
Larger pin count devices, such as the PIC16C92X and
PIC17C76X, may be supported with an adapter socket.
The PICSTART Plus Development Programmer is CE
compliant.
A wide variety of demonstration, development and
evaluation boards for various PIC MCUs and dsPIC
DSCs allows quick application development on fully func-
tional systems. Most boards include prototyping areas for
adding custom circuitry and provide application firmware
and source code for examination and modification.
The boards support a variety of features, including LEDs,
temperature sensors, switches, speakers, RS-232
interfaces, LCD displays, potentiometers and additional
EEPROM memory.
The demonstration and development boards can be
used in teaching environments, for prototyping custom
circuits and for learning about various microcontroller
applications.
26.12 PICkit 2 Development Programmer
The PICkit™ 2 Development Programmer is a low-cost
programmer and selected Flash device debugger with
an easy-to-use interface for programming many of
Microchip’s baseline, mid-range and PIC18F families of
Flash memory microcontrollers. The PICkit 2 Starter Kit
includes a prototyping development board, twelve
sequential lessons, software and HI-TECH’s PICC™
Lite C compiler, and is designed to help get up to speed
quickly using PIC® microcontrollers. The kit provides
everything needed to program, evaluate and develop
applications using Microchip’s powerful, mid-range
Flash memory family of microcontrollers.
In addition to the PICDEM™ and dsPICDEM™ demon-
stration/development board series of circuits, Microchip
has a line of evaluation kits and demonstration software
®
for analog filter design, KEELOQ security ICs, CAN,
IrDA®, PowerSmart® battery management, SEEVAL®
evaluation system, Sigma-Delta ADC, flow rate
sensing, plus many more.
Check the Microchip web page (www.microchip.com)
and the latest “Product Selector Guide” (DS00148) for
the complete list of demonstration, development and
evaluation kits.
DS39761B-page 416
Preliminary
© 2007 Microchip Technology Inc.
PIC18F2682/2685/4682/4685
27.0 ELECTRICAL CHARACTERISTICS
(†)
Absolute Maximum Ratings
Ambient temperature under bias.............................................................................................................-40°C to +125°C
Storage temperature .............................................................................................................................. -65°C to +150°C
Voltage on any pin with respect to VSS (except VDD and MCLR) ................................................... -0.3V to (VDD + 0.3V)
Voltage on VDD with respect to VSS ......................................................................................................... -0.3V to +7.5V
Voltage on MCLR with respect to VSS (Note 2) ......................................................................................... 0V to +13.25V
Total power dissipation (Note 1) ...............................................................................................................................1.0W
Maximum current out of VSS pin ...........................................................................................................................300 mA
Maximum current into VDD pin ..............................................................................................................................250 mA
Input clamp current, IIK (VI < 0 or VI > VDD)...................................................................................................................... 20 mA
Output clamp current, IOK (VO < 0 or VO > VDD) .............................................................................................................. 20 mA
Maximum output current sunk by any I/O pin..........................................................................................................25 mA
Maximum output current sourced by any I/O pin ....................................................................................................25 mA
Maximum current sunk by all ports .......................................................................................................................200 mA
Maximum current sourced by all ports ..................................................................................................................200 mA
Note 1: Power dissipation is calculated as follows:
Pdis = VDD x {IDD – ∑ IOH} + ∑ {(VDD – VOH) x IOH} + ∑(VOL x IOL)
2: Voltage spikes below VSS at the MCLR/VPP pin, inducing currents greater than 80 mA, may cause latch-up.
Thus, a series resistor of 50-100Ω should be used when applying a “low” level to the MCLR/VPP/RE3 pin,
rather than pulling this pin directly to VSS.
† NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at those or any other conditions above those
indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for
extended periods may affect device reliability.
© 2007 Microchip Technology Inc.
Preliminary
DS39761B-page 417
PIC18F2682/2685/4682/4685
FIGURE 27-1:
PIC18F2682/2685/4682/4685 VOLTAGE-FREQUENCY GRAPH (INDUSTRIAL)
6.0V
5.5V
5.0V
4.5V
4.0V
PIC18F268X/468X
4.2V
3.5V
3.0V
2.5V
2.0V
40 MHz
Frequency
FIGURE 27-2:
PIC18LF2682/2685/4682/4685 VOLTAGE-FREQUENCY GRAPH (INDUSTRIAL)
6.0V
5.5V
5.0V
PIC18LF268X/468X
4.5V
4.2V
4.0V
3.5V
3.0V
2.5V
2.0V
40 MHz
4 MHz
Frequency
FMAX = (16.36 MHz/V) (VDDAPPMIN – 2.0V) + 4 MHz
Note: VDDAPPMIN is the minimum voltage of the PIC® device in the application.
DS39761B-page 418
Preliminary
© 2007 Microchip Technology Inc.
PIC18F2682/2685/4682/4685
27.1 DC Characteristics: Supply Voltage
PIC18F2682/2685/4682/4685 (Industrial)
PIC18LF2682/2685/4682/4685 (Industrial)
PIC18LF2682/2685/4682/4685
Standard Operating Conditions (unless otherwise stated)
(Industrial)
Operating temperature
-40°C ≤ TA ≤ +85°C for industrial
Standard Operating Conditions (unless otherwise stated)
PIC18F2682/2685/4682/4685
Operating temperature
-40°C ≤ TA ≤ +85°C for industrial
-40°C ≤ TA ≤ +125°C for extended
(Industrial, Extended)
Param
No.
Symbol
Characteristic
Min
Typ Max Units
Conditions
VDD
Supply Voltage
PIC18LF268X/468X 2.0
D001
—
—
5.5
—
V
V
D002
VDR
RAM Data Retention
Voltage
1.5
(1)
D003
VPOR
VDD Start Voltage
to ensure internal
Power-on Reset signal
—
—
—
0.7
—
V
See section on Power-on Reset for details
D004
SVDD
VBOR
VDD Rise Rate
to ensure internal
Power-on Reset signal
0.05
V/ms See section on Power-on Reset for details
Brown-out Reset Voltage
PIC18LF268X/468X
BORV1:BORV0 = 11
BORV1:BORV0 = 10
All Devices
D005
2.00
2.65
2.05 2.16
2.79 2.93
V
V
D005
BORV1:BORV0 = 01
BORV1:BORV0 = 00
4.11
4.36
4.33 4.55
4.59 4.82
V
V
Legend:
Shading of rows is to assist in readability of the table.
Note 1: This is the limit to which VDD can be lowered in Sleep mode, or during a device Reset, without losing RAM data.
© 2007 Microchip Technology Inc.
Preliminary
DS39761B-page 419
PIC18F2682/2685/4682/4685
27.2 DC Characteristics: Power-Down and Supply Current
PIC18F2682/2685/4682/4685 (Industrial)
PIC18LF2682/2685/4682/4685 (Industrial)
PIC18LF2682/2685/4682/4685
Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C ≤ TA ≤ +85°C for industrial
(Industrial)
Standard Operating Conditions (unless otherwise stated)
PIC18F2682/2685/4682/4685
Operating temperature
-40°C ≤ TA ≤ +85°C for industrial
-40°C ≤ TA ≤ +125°C for extended
(Industrial, Extended)
Param
Device
No.
Typ
Max Units
Conditions
(1)
Power-Down Current (IPD)
PIC18LF268X/468X 0.1
0.95
1
μA
μA
μA
μA
μA
μA
μA
μA
μA
μA
-40°C
+25°C
+85°C
-40°C
VDD = 2.0V
(Sleep mode)
0.1
0.2
6
PIC18LF268X/468X 0.1
1.4
2
VDD = 3.0V
(Sleep mode)
0.1
+25°C
+85°C
-40°C
0.3
8
All devices 0.1
1.9
2
0.1
0.4
+25°C
+85°C
+125°C
VDD = 5.0V
(Sleep mode)
15
120
Extended devices only
10
Legend:
Shading of rows is to assist in readability of the table.
Note 1: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with
the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS and all features that add delta
current disabled (such as WDT, Timer1 Oscillator, BOR, etc.).
2: The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading
and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on
the current consumption.
The test conditions for all IDD measurements in active operation mode are:
OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD;
MCLR = VDD; WDT enabled/disabled as specified.
3: For RC oscillator configurations, current through REXT is not included. The current through the resistor can be estimated
by the formula Ir = VDD/2REXT (mA) with REXT in kΩ.
4: Standard low-cost 32 kHz crystals have an operating temperature range of -10°C to +70°C. Extended temperature
crystals are available at a much higher cost.
DS39761B-page 420
Preliminary
© 2007 Microchip Technology Inc.
PIC18F2682/2685/4682/4685
27.2 DC Characteristics: Power-Down and Supply Current
PIC18F2682/2685/4682/4685 (Industrial)
PIC18LF2682/2685/4682/4685 (Industrial) (Continued)
PIC18LF2682/2685/4682/4685
Standard Operating Conditions (unless otherwise stated)
(Industrial)
Operating temperature
-40°C ≤ TA ≤ +85°C for industrial
Standard Operating Conditions (unless otherwise stated)
PIC18F2682/2685/4682/4685
Operating temperature
-40°C ≤ TA ≤ +85°C for industrial
-40°C ≤ TA ≤ +125°C for extended
(Industrial, Extended)
Param
Device
No.
Typ
Max Units
Conditions
(2,3)
Supply Current (IDD)
PIC18LF268X/468X
15
15
15
40
35
30
36
36
36
100
100
100
200
200
200
200
1
μA
μA
-40°C
+25°C
+85°C
-40°C
+25°C
+85°C
-40°C
+25°C
+85°C
+125°C
-40°C
+25°C
+85°C
-40°C
+25°C
+85°C
-40°C
+25°C
+85°C
+125°C
-40°C
+25°C
+85°C
-40°C
+25°C
+85°C
-40°C
+25°C
+85°C
+125°C
VDD = 2.0V
VDD = 3.0V
μA
PIC18LF268X/468X
μA
FOSC = 31 kHz
(RC_RUN mode,
μA
μA
Internal oscillator source)
All devices 105
μA
90
80
μA
VDD = 5.0V
μA
Extended devices only
80
μA
PIC18LF268X/468X 0.32
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
0.33
1
VDD = 2.0V
VDD = 3.0V
0.33
1
PIC18LF268X/468X 0.6
1.6
1.6
1.6
3
FOSC = 1 MHz
(RC_RUN mode,
0.55
0.6
Internal oscillator source)
All devices 1.1
1.1
1
3
VDD = 5.0V
3
Extended devices only
1
3
PIC18LF268X/468X 0.8
2.2
2.2
2.2
3
0.8
VDD = 2.0V
VDD = 3.0V
0.8
PIC18LF268X/468X 1.3
FOSC = 4 MHz
(RC_RUN mode,
1.3
3
1.3
3
Internal oscillator source)
All devices 2.5
5.3
5.3
5.3
8
2.5
2.5
VDD = 5.0V
Extended devices only 2.5
Legend:
Shading of rows is to assist in readability of the table.
Note 1: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with
the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS and all features that add delta
current disabled (such as WDT, Timer1 Oscillator, BOR, etc.).
2: The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading
and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on
the current consumption.
The test conditions for all IDD measurements in active operation mode are:
OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD;
MCLR = VDD; WDT enabled/disabled as specified.
3: For RC oscillator configurations, current through REXT is not included. The current through the resistor can be estimated
by the formula Ir = VDD/2REXT (mA) with REXT in kΩ.
4: Standard low-cost 32 kHz crystals have an operating temperature range of -10°C to +70°C. Extended temperature
crystals are available at a much higher cost.
© 2007 Microchip Technology Inc.
Preliminary
DS39761B-page 421
PIC18F2682/2685/4682/4685
27.2 DC Characteristics: Power-Down and Supply Current
PIC18F2682/2685/4682/4685 (Industrial)
PIC18LF2682/2685/4682/4685 (Industrial) (Continued)
PIC18LF2682/2685/4682/4685
Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C ≤ TA ≤ +85°C for industrial
(Industrial)
Standard Operating Conditions (unless otherwise stated)
PIC18F2682/2685/4682/4685
Operating temperature
-40°C ≤ TA ≤ +85°C for industrial
-40°C ≤ TA ≤ +125°C for extended
(Industrial, Extended)
Param
Device
No.
Typ
Max Units
Conditions
(2,3)
Supply Current (IDD)
PIC18LF268X/468X 2.9
8
μA
μA
-40°C
3.1
8
+25°C
+85°C
-40°C
+25°C
+85°C
-40°C
+25°C
+85°C
+125°C
-40°C
+25°C
+85°C
-40°C
+25°C
+85°C
-40°C
+25°C
+85°C
+125°C
-40°C
+25°C
+85°C
-40°C
+25°C
+85°C
-40°C
+25°C
+85°C
+125°C
VDD = 2.0V
VDD = 3.0V
3.6
12
μA
PIC18LF268X/468X 4.5
12
μA
FOSC = 31 kHz
(RC_IDLE mode,
Internal oscillator source)
4.8
12
μA
5.8
All devices 9.2
9.8
17
μA
25
μA
25
μA
VDD = 5.0V
11.4
36
μA
Extended devices only
21
180
400
400
400
600
600
600
1
μA
PIC18LF268X/468X 165
μA
175
μA
VDD = 2.0V
VDD = 3.0V
190
μA
PIC18LF268X/468X 250
μA
FOSC = 1 MHz
(RC_IDLE mode,
Internal oscillator source)
270
μA
290
μA
All devices 0.5
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
0.5
1
VDD = 5.0V
0.5
1
Extended devices only 0.6
1.4
1.1
1.1
1.1
1.5
1.5
1.5
2.7
2.7
2.7
3.6
PIC18LF268X/468X 0.34
0.35
VDD = 2.0V
VDD = 3.0V
0.36
PIC18LF268X/468X 0.52
FOSC = 4 MHz
(RC_IDLE mode,
Internal oscillator source)
0.54
0.58
All devices
1
1.1
1.1
VDD = 5.0V
Extended devices only 1.1
Legend:
Shading of rows is to assist in readability of the table.
Note 1: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with
the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS and all features that add delta
current disabled (such as WDT, Timer1 Oscillator, BOR, etc.).
2: The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading
and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on
the current consumption.
The test conditions for all IDD measurements in active operation mode are:
OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD;
MCLR = VDD; WDT enabled/disabled as specified.
3: For RC oscillator configurations, current through REXT is not included. The current through the resistor can be estimated
by the formula Ir = VDD/2REXT (mA) with REXT in kΩ.
4: Standard low-cost 32 kHz crystals have an operating temperature range of -10°C to +70°C. Extended temperature
crystals are available at a much higher cost.
DS39761B-page 422
Preliminary
© 2007 Microchip Technology Inc.
PIC18F2682/2685/4682/4685
27.2 DC Characteristics: Power-Down and Supply Current
PIC18F2682/2685/4682/4685 (Industrial)
PIC18LF2682/2685/4682/4685 (Industrial) (Continued)
PIC18LF2682/2685/4682/4685
Standard Operating Conditions (unless otherwise stated)
(Industrial)
Operating temperature
-40°C ≤ TA ≤ +85°C for industrial
Standard Operating Conditions (unless otherwise stated)
PIC18F2682/2685/4682/4685
Operating temperature
-40°C ≤ TA ≤ +85°C for industrial
-40°C ≤ TA ≤ +125°C for extended
(Industrial, Extended)
Param
Device
No.
Typ
Max Units
Conditions
(2,3)
Supply Current (IDD)
PIC18LF268X/468X 250
600
600
600
1.2
1.2
1.2
3
μA
μA
-40°C
250
+25°C
+85°C
-40°C
VDD = 2.0V
VDD = 3.0V
250
μA
PIC18LF268X/468X 550
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
FOSC = 1 MHZ
(PRI_RUN,
480
+25°C
+85°C
-40°C
460
EC oscillator)
All devices 1.2
1.1
1
3
+25°C
+85°C
+125°C
-40°C
VDD = 5.0V
3
Extended devices only
1
3
PIC18LF268X/468X 0.72
2.2
2.2
2.2
3.3
3.3
3.3
6.6
6.6
6.6
6.6
21
0.74
+25°C
+85°C
-40°C
VDD = 2.0V
VDD = 3.0V
0.74
PIC18LF268X/468X 1.3
FOSC = 4 MHz
(PRI_RUN,
1.3
+25°C
+85°C
-40°C
1.3
All devices 2.7
2.6
EC oscillator)
+25°C
+85°C
+125°C
+125°C
VDD = 5.0V
2.5
Extended devices only 2.6
Extended devices only 8.4
VDD = 4.2V
VDD = 5.0V
FOSC = 25 MHz
(PRI_RUN, EC oscillator)
11
28
mA
+125°C
All devices
All devices
15
16
16
21
21
21
38
38
38
44
44
44
mA
mA
mA
mA
mA
mA
-40°C
+25°C
+85°C
-40°C
+25°C
+85°C
VDD = 4.2V
VDD = 5.0V
FOSC = 40 MHZ
(PRI_RUN,
EC oscillator)
Legend:
Shading of rows is to assist in readability of the table.
Note 1: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with
the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS and all features that add delta
current disabled (such as WDT, Timer1 Oscillator, BOR, etc.).
2: The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading
and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on
the current consumption.
The test conditions for all IDD measurements in active operation mode are:
OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD;
MCLR = VDD; WDT enabled/disabled as specified.
3: For RC oscillator configurations, current through REXT is not included. The current through the resistor can be estimated
by the formula Ir = VDD/2REXT (mA) with REXT in kΩ.
4: Standard low-cost 32 kHz crystals have an operating temperature range of -10°C to +70°C. Extended temperature
crystals are available at a much higher cost.
© 2007 Microchip Technology Inc.
Preliminary
DS39761B-page 423
PIC18F2682/2685/4682/4685
27.2 DC Characteristics: Power-Down and Supply Current
PIC18F2682/2685/4682/4685 (Industrial)
PIC18LF2682/2685/4682/4685 (Industrial) (Continued)
PIC18LF2682/2685/4682/4685
Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C ≤ TA ≤ +85°C for industrial
(Industrial)
Standard Operating Conditions (unless otherwise stated)
PIC18F2682/2685/4682/4685
Operating temperature
-40°C ≤ TA ≤ +85°C for industrial
-40°C ≤ TA ≤ +125°C for extended
(Industrial, Extended)
Param
Device
No.
Typ
Max Units
Conditions
(2,3)
Supply Current (IDD)
All devices 9.00 18.00
8.90 17.00
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
-40°C
FOSC = 4 MHZ
(PRI_RUN HSPLL)
+25°C
+85°C
-40°C
+25°C
+85°C
-40°C
+25°C
+85°C
-40°C
+25°C
+85°C
VDD = 4.2V
VDD = 5.0V
VDD = 4.2V
VDD = 5.0V
8.80 16.00
All devices 12.00 24.00
12.00 22.00
FOSC = 4 MHZ
(PRI_RUN HSPLL)
12.00 21.00
All devices 21.00 39.00
21.00 39.00
FOSC = 10 MHZ
(PRI_RUN HSPLL)
21.00 39.00
All devices 28.00 44.00
28.00 44.00
FOSC = 10 MHZ
(PRI_RUN HSPLL)
28.00 44.00
Legend:
Shading of rows is to assist in readability of the table.
Note 1: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with
the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS and all features that add delta
current disabled (such as WDT, Timer1 Oscillator, BOR, etc.).
2: The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading
and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on
the current consumption.
The test conditions for all IDD measurements in active operation mode are:
OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD;
MCLR = VDD; WDT enabled/disabled as specified.
3: For RC oscillator configurations, current through REXT is not included. The current through the resistor can be estimated
by the formula Ir = VDD/2REXT (mA) with REXT in kΩ.
4: Standard low-cost 32 kHz crystals have an operating temperature range of -10°C to +70°C. Extended temperature
crystals are available at a much higher cost.
DS39761B-page 424
Preliminary
© 2007 Microchip Technology Inc.
PIC18F2682/2685/4682/4685
27.2 DC Characteristics: Power-Down and Supply Current
PIC18F2682/2685/4682/4685 (Industrial)
PIC18LF2682/2685/4682/4685 (Industrial) (Continued)
PIC18LF2682/2685/4682/4685
Standard Operating Conditions (unless otherwise stated)
(Industrial)
Operating temperature
-40°C ≤ TA ≤ +85°C for industrial
Standard Operating Conditions (unless otherwise stated)
PIC18F2682/2685/4682/4685
Operating temperature
-40°C ≤ TA ≤ +85°C for industrial
-40°C ≤ TA ≤ +125°C for extended
(Industrial, Extended)
Param
Device
No.
Typ
Max Units
Conditions
(2,3)
Supply Current (IDD)
PIC18LF268X/468X
65
65
70
220
220
220
330
330
330
600
600
600
600
760
760
760
1.4
1.4
1.4
2.2
2.2
2.2
3
μA
μA
μA
μA
μA
μA
μA
μA
μA
μA
μA
μA
μA
μA
μA
μA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
-40°C
+25°C
+85°C
-40°C
VDD = 2.0V
VDD = 3.0V
PIC18LF268X/468X 120
FOSC = 1 MHz
(PRI_IDLE mode,
EC oscillator)
120
+25°C
+85°C
-40°C
130
All devices 300
240
+25°C
+85°C
+125°C
-40°C
VDD = 5.0V
300
Extended devices only 320
PIC18LF268X/468X 260
255
+25°C
+85°C
-40°C
VDD = 2.0V
VDD = 3.0V
270
PIC18LF268X/468X 420
FOSC = 4 MHz
(PRI_IDLE mode,
EC oscillator)
430
+25°C
+85°C
-40°C
450
All devices 0.9
0.9
0.9
+25°C
+85°C
+125°C
+125°C
+125°C
-40°C
VDD = 5.0V
Extended devices only
1
Extended devices only 2.8
4.3
7
VDD = 4.2V
VDD = 5.0V
FOSC = 25 MHz
(PRI_IDLE mode, EC oscillator)
11
All devices
6
18
6.2
6.6
18
+25°C
+85°C
-40°C
VDD = 4.2 V
VDD = 5.0V
FOSC = 40 MHz
(PRI_IDLE mode,
EC oscillator)
18
All devices 8.1
22
9.1
8.3
22
+25°C
+85°C
22
Legend:
Shading of rows is to assist in readability of the table.
Note 1: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with
the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS and all features that add delta
current disabled (such as WDT, Timer1 Oscillator, BOR, etc.).
2: The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading
and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on
the current consumption.
The test conditions for all IDD measurements in active operation mode are:
OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD;
MCLR = VDD; WDT enabled/disabled as specified.
3: For RC oscillator configurations, current through REXT is not included. The current through the resistor can be estimated
by the formula Ir = VDD/2REXT (mA) with REXT in kΩ.
4: Standard low-cost 32 kHz crystals have an operating temperature range of -10°C to +70°C. Extended temperature
crystals are available at a much higher cost.
© 2007 Microchip Technology Inc.
Preliminary
DS39761B-page 425
PIC18F2682/2685/4682/4685
27.2 DC Characteristics: Power-Down and Supply Current
PIC18F2682/2685/4682/4685 (Industrial)
PIC18LF2682/2685/4682/4685 (Industrial) (Continued)
PIC18LF2682/2685/4682/4685
Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C ≤ TA ≤ +85°C for industrial
(Industrial)
Standard Operating Conditions (unless otherwise stated)
PIC18F2682/2685/4682/4685
Operating temperature
-40°C ≤ TA ≤ +85°C for industrial
-40°C ≤ TA ≤ +125°C for extended
(Industrial, Extended)
Param
Device
No.
Typ
Max Units
Conditions
(2,3)
Supply Current (IDD)
PIC18LF268X/468X
PIC18LF268X/468X
All devices
14
15
16
40
35
31
99
81
75
40
40
40
86
86
86
180
180
180
20
20
20
25
μA
μA
μA
μA
μA
μA
μA
μA
μA
μA
μA
μA
μA
μA
μA
μA
μA
μA
-40°C
+25°C
+85°C
-40°C
+25°C
+85°C
-40°C
+25°C
+85°C
-40°C
+25°C
+85°C
-40°C
+25°C
+85°C
-40°C
+25°C
+85°C
VDD = 2.0V
VDD = 3.0V
VDD = 5.0V
VDD = 2.0V
VDD = 3.0V
VDD = 5.0V
(4)
FOSC = 32 kHz
(SEC_RUN mode,
Timer1 as clock)
PIC18LF268X/468X 2.5
3.7
4.5
(4)
PIC18LF268X/468X
5
FOSC = 32 kHz
5.4
6.3
25
25
30
30
30
(SEC_IDLE mode,
Timer1 as clock)
All devices 8.5
9
10.5
Legend:
Shading of rows is to assist in readability of the table.
Note 1: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with
the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS and all features that add delta
current disabled (such as WDT, Timer1 Oscillator, BOR, etc.).
2: The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading
and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on
the current consumption.
The test conditions for all IDD measurements in active operation mode are:
OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD;
MCLR = VDD; WDT enabled/disabled as specified.
3: For RC oscillator configurations, current through REXT is not included. The current through the resistor can be estimated
by the formula Ir = VDD/2REXT (mA) with REXT in kΩ.
4: Standard low-cost 32 kHz crystals have an operating temperature range of -10°C to +70°C. Extended temperature
crystals are available at a much higher cost.
DS39761B-page 426
Preliminary
© 2007 Microchip Technology Inc.
PIC18F2682/2685/4682/4685
27.2 DC Characteristics: Power-Down and Supply Current
PIC18F2682/2685/4682/4685 (Industrial)
PIC18LF2682/2685/4682/4685 (Industrial) (Continued)
PIC18LF2682/2685/4682/4685
Standard Operating Conditions (unless otherwise stated)
(Industrial)
Operating temperature
-40°C ≤ TA ≤ +85°C for industrial
Standard Operating Conditions (unless otherwise stated)
PIC18F2682/2685/4682/4685
Operating temperature
-40°C ≤ TA ≤ +85°C for industrial
-40°C ≤ TA ≤ +125°C for extended
(Industrial, Extended)
Param
Device
No.
Typ
Max Units
Conditions
Module Differential Currents (ΔIWDT, ΔIBOR, ΔILVD, ΔIOSCB, ΔIAD)
D022
(ΔIWDT)
Watchdog Timer 1.3
4.5
4.5
4.5
5.5
5.5
5.5
10
10
10
14
65
75
75
45
45
55
55
4.5
4.5
4.5
6
μA
μA
μA
μA
μA
μA
μA
μA
μA
-40°C
+25°C
+85°C
-40°C
+25°C
+85°C
-40°C
+25°C
+85°C
1.4
2
VDD = 2.0V
VDD = 3.0V
1.9
2
2.8
4
5.5
5.6
13
VDD = 5.0V
μA -40°C to +125°C
D022A
Brown-out Reset
35
40
55
μA
μA
-40°C to +85°C
-40°C to +85°C
VDD = 3.0V
VDD = 5.0V
(ΔIBOR)
μA -40°C to +125°C
D022B
High/Low-Voltage Detect 22
μA
μA
μA
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
VDD = 2.0V
VDD = 3.0V
(ΔILVD)
25
29
VDD = 5.0V
30
μA -40°C to +125°C
D025
Timer1 Oscillator 2.1
μA
μA
-40°C to +85°C
-40°C to +85°C
(4)
(4)
(4)
(ΔIOSCB)
1.8
2.1
2.2
2.6
2.9
3
VDD = 2.0V
32 kHz on Timer1
32 kHz on Timer1
32 kHz on Timer1
μA -40°C to +125°C
μA
μA
μA
μA
μA
μA
μA
μA
μA
-40°C
+25°C
6
VDD = 3.0V
VDD = 5.0V
6
+85°C
8
-40°C
3.2
3.4
8
+25°C
8
+85°C
D026
(ΔIAD)
A/D Converter
1
1
1
2
2
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
VDD = 2.0V
VDD = 3.0V
2
A/D on, not converting
1.6 μS ≤ TAD ≤ 6.4 μS
2
VDD = 5.0V
8
μA -40°C to +125°C
Legend:
Shading of rows is to assist in readability of the table.
Note 1: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with
the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS and all features that add delta
current disabled (such as WDT, Timer1 Oscillator, BOR, etc.).
2: The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading
and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on
the current consumption.
The test conditions for all IDD measurements in active operation mode are:
OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD;
MCLR = VDD; WDT enabled/disabled as specified.
3: For RC oscillator configurations, current through REXT is not included. The current through the resistor can be estimated
by the formula Ir = VDD/2REXT (mA) with REXT in kΩ.
4: Standard low-cost 32 kHz crystals have an operating temperature range of -10°C to +70°C. Extended temperature
crystals are available at a much higher cost.
© 2007 Microchip Technology Inc.
Preliminary
DS39761B-page 427
PIC18F2682/2685/4682/4685
27.3 DC Characteristics: PIC18F2682/2685/4682/4685 (Industrial)
PIC18LF2682/2685/4682/4685 (Industrial)
Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C ≤ TA ≤ +85°C for industrial
DC CHARACTERISTICS
Param
Symbol
No.
Characteristic
Min
Max
Units
Conditions
VIL
Input Low Voltage
I/O ports:
with TTL buffer
D030
VSS
—
0.15 VDD
0.8
V
V
V
V
V
V
V
V
V
V
VDD < 4.5V
D030A
D031
4.5V ≤ VDD ≤ 5.5V
with Schmitt Trigger buffer
RC3 and RC4
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
0.2 VDD
0.3 VDD
0.8
D031A
D031B
D032
I2C™ enabled
SMBus enabled
MCLR
0.2 VDD
0.3 VDD
0.2 VDD
0.3
D033
OSC1
HS, HSPLL modes
RC, EC modes(1)
XT, LP modes
D033A
D033B
D034
OSC1
OSC1
T13CKI
0.3
VIH
Input High Voltage
I/O ports:
with TTL buffer
D040
0.25 VDD + 0.8V
2.0
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
V
V
V
V
V
V
V
V
V
V
V
VDD < 4.5V
D040A
D041
4.5V ≤ VDD ≤ 5.5V
with Schmitt Trigger buffer
RC3 and RC4
0.8 VDD
0.7 VDD
2.1
D041A
D041B
D042
I2C™ enabled
SMBus enabled
MCLR
0.8 VDD
0.7 VDD
0.8 VDD
0.9 VDD
1.6
D043
OSC1
HS, HSPLL modes
EC mode
RC mode(1)
D043A
D043B
D043C
D044
OSC1
OSC1
OSC1
XT, LP modes
T13CKI
1.6
IIL
Input Leakage Current(2,3)
D060
I/O ports
—
1
μA VSS ≤ VPIN ≤ VDD,
Pin at high-impedance
D061
D063
MCLR
—
—
5
5
μA Vss ≤ VPIN ≤ VDD
μA Vss ≤ VPIN ≤ VDD
OSC1
IPU
Weak Pull-up Current
PORTB weak pull-up current
D070
IPURB
50
400
μA VDD = 5V, VPIN = VSS
Note 1: In RC oscillator configuration, the OSC1/CLKI pin is a Schmitt Trigger input. It is not recommended that the
PIC® device be driven with an external clock while in RC mode.
2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified
levels represent normal operating conditions. Higher leakage current may be measured at different input
voltages.
3: Negative current is defined as current sourced by the pin.
4: Parameter is characterized but not tested.
DS39761B-page 428
Preliminary
© 2007 Microchip Technology Inc.
PIC18F2682/2685/4682/4685
27.3 DC Characteristics: PIC18F2682/2685/4682/4685 (Industrial)
PIC18LF2682/2685/4682/4685 (Industrial) (Continued)
Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C ≤ TA ≤ +85°C for industrial
DC CHARACTERISTICS
Param
Symbol
No.
Characteristic
Min
Max
Units
Conditions
VOL
Output Low Voltage
I/O ports
D080
D083
—
—
0.6
0.6
V
V
IOL = 8.5 mA, VDD = 4.5V,
-40°C to +85°C
OSC2/CLKO
IOL = 1.6 mA, VDD = 4.5V,
(RC, RCIO, EC, ECIO modes)
Output High Voltage(3)
-40°C to +85°C
VOH
D090
D092
I/O ports
VDD – 0.7
VDD – 0.7
—
—
V
V
IOH = -3.0 mA, VDD = 4.5V,
-40°C to +85°C
OSC2/CLKO
IOH = -1.3 mA, VDD = 4.5V,
(RC, RCIO, EC, ECIO modes)
-40°C to +85°C
Capacitive Loading Specs
on Output Pins
D100(4)
—
COSC2 OSC2 pin
15
pF In XT, HS and LP modes
when external clock is
used to drive OSC1
D101
D102
CIO
CB
All I/O pins and OSC2
(in RC mode)
—
—
50
pF To meet the AC timing
specifications
pF I2C™ specification
SCL, SDA
400
Note 1: In RC oscillator configuration, the OSC1/CLKI pin is a Schmitt Trigger input. It is not recommended that the
PIC® device be driven with an external clock while in RC mode.
2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified
levels represent normal operating conditions. Higher leakage current may be measured at different input
voltages.
3: Negative current is defined as current sourced by the pin.
4: Parameter is characterized but not tested.
© 2007 Microchip Technology Inc.
Preliminary
DS39761B-page 429
PIC18F2682/2685/4682/4685
TABLE 27-1: MEMORY PROGRAMMING REQUIREMENTS
Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C ≤ TA ≤ +85°C for industrial
DC Characteristics
Param
Sym
No.
Characteristic
Min
Typ†
Max
Units
Conditions
Internal Program Memory
Programming Specifications(1)
D110
D113
VPP
Voltage on MCLR/VPP/RE3 pin
9.00
—
—
—
13.25
10
V
(Note 3)
IDDP
Supply Current during
Programming
mA
Data EEPROM Memory
D120
ED
Byte Endurance
100K
VMIN
1M
—
—
E/W -40°C to +85°C
D121 VDRW VDD for Read/Write
5.5
V
Using EECON to read/write
VMIN = Minimum operating
voltage
D122 TDEW Erase/Write Cycle Time
D123 TRETD Characteristic Retention
—
4
—
—
ms
40
—
Year Provided no other
specifications are violated
D124
TREF
Number of Total Erase/Write
Cycles before Refresh(2)
1M
10M
—
E/W -40°C to +85°C
Program Flash Memory
Cell Endurance
D130
D131
EP
10K
100K
—
—
E/W -40°C to +85°C
VPR
VDD for Read
VMIN
5.5
V
VMIN = Minimum operating
voltage
D132
VIE
VDD for Block Erase
4.5
4.5
—
—
5.5
5.5
V
V
Using ICSP™ port
Using ICSP port
D132A VIW
VDD for Externally Timed Erase
or Write
D132B VPEW VDD for Self-timed Write
VMIN
—
5.5
V
VMIN = Minimum operating
voltage
D133
TIE
ICSP™ Block Erase Cycle Time
—
1
4
—
—
ms VDD > 4.5V
ms VDD > 4.5V
D133A TIW
ICSP Erase or Write Cycle Time
(externally timed)
—
D133A TIW
Self-timed Write Cycle Time
—
2
—
—
ms
D134 TRETD Characteristic Retention
40
100
Year Provided no other
specifications are violated
†
Data in “Typ” column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance
only and are not tested.
Note 1: These specifications are for programming the on-chip program memory through the use of table write
instructions.
2: Refer to Section 7.8 “Using the Data EEPROM” for a more detailed discussion on data EEPROM
endurance.
3: Required only if Single-Supply Programming is disabled.
DS39761B-page 430
Preliminary
© 2007 Microchip Technology Inc.
PIC18F2682/2685/4682/4685
TABLE 27-2: COMPARATOR SPECIFICATIONS
Operating Conditions: 3.0V < VDD < 5.5V, -40°C < TA < +85°C (unless otherwise stated).
Param
No.
Sym
Characteristics
Input Offset Voltage
Min
Typ
Max
Units
Comments
D300
VIOFF
—
0
5.0
—
10
VDD – 1.5
—
mV
V
D301
D302
300
VICM
Input Common Mode Voltage*
Common Mode Rejection Ratio*
Response Time(1)*
CMRR
TRESP
55
—
—
—
dB
ns
ns
150
150
400
PIC18FXXXX
300A
600
PIC18LFXXXX,
VDD = 2.0V
301
TMC2OV Comparator Mode Change to
Output Valid*
—
—
10
μs
*
These parameters are characterized but not tested.
Note 1: Response time measured with one comparator input at (VDD – 1.5)/2 while the other input transitions
from VSS to VDD.
TABLE 27-3: VOLTAGE REFERENCE SPECIFICATIONS
Operating Conditions: 3.0V < VDD < 5.5V, -40°C < TA < +85°C (unless otherwise stated).
Param
No.
Sym
Characteristics
Resolution
Min
Typ
Max
Units
Comments
D310
VRES
VDD/24
—
VDD/32
LSb
D311
VRAA
Absolute Accuracy
—
—
—
—
1/4
1/2
LSb Low Range (CVRR = 1)
LSb High Range (CVRR = 0)
D312
310
VRUR
TSET
Unit Resistor Value (R)*
Settling Time(1)*
—
—
2k
—
—
Ω
10
μs
*
These parameters are characterized but not tested.
Note 1: Settling time measured while CVRR = 1and CVR3:CVR0 transitions from ‘0000’ to ‘1111’.
© 2007 Microchip Technology Inc.
Preliminary
DS39761B-page 431
PIC18F2682/2685/4682/4685
FIGURE 27-3:
HIGH/LOW-VOLTAGE DETECT CHARACTERISTICS
VDD
(HLVDIF can be
cleared in software)
VLVD
(HLVDIF set by hardware)
HLVDIF
TABLE 27-4: HIGH/LOW-VOLTAGE DETECT CHARACTERISTICS
Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C ≤ TA ≤ +85°C for industrial
Param
No.
Sym
Characteristic
Min
Typ† Max
Units
Conditions
D420
HLVD Voltage on
VDD Transition
High-to-Low
HLVDL<3:0> = 0000 2.12
HLVDL<3:0> = 0001 2.18
HLVDL<3:0> = 0010 2.31
HLVDL<3:0> = 0011 2.38
HLVDL<3:0> = 0100 2.54
HLVDL<3:0> = 0101 2.72
HLVDL<3:0> = 0110 2.82
HLVDL<3:0> = 0111 3.05
HLVDL<3:0> = 1000 3.31
HLVDL<3:0> = 1001 3.46
HLVDL<3:0> = 1010 3.63
HLVDL<3:0> = 1011 3.81
HLVDL<3:0> = 1100 4.01
HLVDL<3:0> = 1101 4.23
HLVDL<3:0> = 1110 4.48
HLVDL<3:0> = 1111 1.14
2.17
2.23
2.36
2.44
2.60
2.79
2.89
3.12
3.39
3.55
3.71
3.90
4.11
4.33
4.59
1.20
2.22
2.28
2.42
2.49
2.66
2.85
2.95
3.19
3.47
3.63
3.80
3.99
4.20
4.43
4.69
1.26
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
†
Production tested at TAMB = 25°C. Specifications over temperature limits ensured by characterization.
DS39761B-page 432
Preliminary
© 2007 Microchip Technology Inc.
PIC18F2682/2685/4682/4685
27.4 AC (Timing) Characteristics
27.4.1 TIMING PARAMETER SYMBOLOGY
The timing parameter symbols have been created
using one of the following formats:
1. TppS2ppS
2. TppS
T
3. TCC:ST
4. Ts
(I2C specifications only)
(I2C specifications only)
F
Frequency
T
Time
Lowercase letters (pp) and their meanings:
pp
cc
ck
cs
di
CCP1
CLKO
CS
osc
rd
OSC1
RD
rw
sc
ss
t0
RD or WR
SCK
SDI
do
dt
SDO
SS
Data in
I/O port
MCLR
T0CKI
T13CKI
WR
io
t1
mc
wr
Uppercase letters and their meanings:
S
F
Fall
P
R
V
Z
Period
H
High
Rise
I
L
Invalid (High-Impedance)
Low
Valid
High-Impedance
I2C only
AA
output access
Bus free
High
Low
High
Low
BUF
TCC:ST (I2C specifications only)
CC
HD
Hold
SU
Setup
ST
DAT
STA
DATA input hold
Start condition
STO
Stop condition
© 2007 Microchip Technology Inc.
Preliminary
DS39761B-page 433
PIC18F2682/2685/4682/4685
27.4.2
TIMING CONDITIONS
Note:
Because of space limitations, the generic
terms “PIC18FXXXX” and “PIC18LFXXXX”
are used throughout this section to refer to
the PIC18F2682/2685/4682/4685 and
PIC18LF2682/2685/4682/4685 families of
devices specifically and only those devices.
The temperature and voltages specified in Table 27-5
apply to all timing specifications unless otherwise
noted. Figure 27-4 specifies the load conditions for the
timing specifications.
TABLE 27-5: TEMPERATURE AND VOLTAGE SPECIFICATIONS – AC
Standard Operating Conditions (unless otherwise stated)
Operating temperature
Operating voltage VDD range as described in DC spec Section 27.1 and
Section 27.3. LF parts operate for industrial temperatures only.
-40°C ≤ TA ≤ +85°C for industrial
AC CHARACTERISTICS
FIGURE 27-4:
LOAD CONDITIONS FOR DEVICE TIMING SPECIFICATIONS
Load Condition 1 Load Condition 2
VDD/2
CL
RL
Pin
VSS
CL
Pin
RL = 464Ω
CL = 50 pF for all pins except OSC2/CLKO
and including D and E outputs as ports
VSS
DS39761B-page 434
Preliminary
© 2007 Microchip Technology Inc.
PIC18F2682/2685/4682/4685
27.4.3
TIMING DIAGRAMS AND SPECIFICATIONS
FIGURE 27-5:
EXTERNAL CLOCK TIMING (ALL MODES EXCEPT PLL)
Q4
Q1
1
Q2
Q3
Q4
Q1
OSC1
CLKO
3
4
3
4
2
TABLE 27-6: EXTERNAL CLOCK TIMING REQUIREMENTS
Param.
Symbol
Characteristic
Min
Max
Units
Conditions
No.
1A
FOSC
External CLKI Frequency(1)
DC
DC
DC
DC
DC
0.1
4
1
25
31.25
40
4
MHz XT, RC Oscillator modes
MHz HS Oscillator mode
kHz LP Oscillator mode
MHz EC Oscillator mode
MHz RC Oscillator mode
MHz XT Oscillator mode
MHz HS Oscillator mode
MHz HSPLL Oscillator mode
kHz LP Oscillator mode
Oscillator Frequency(1)
4
25
10
200
—
4
5
1
TOSC
External CLKI Period(1)
Oscillator Period(1)
1000
40
ns
ns
μs
ns
ns
μs
ns
ns
μs
ns
ns
μs
ns
ns
ns
ns
XT, RC Oscillator modes
HS Oscillator mode
LP Oscillator mode
EC Oscillator mode
RC Oscillator mode
XT Oscillator mode
HS Oscillator mode
HSPLL Oscillator mode
LP Oscillator mode
TCY = 4/FOSC
—
32
—
25
—
250
250
40
—
1
250
250
200
—
100
5
2
3
TCY
Instruction Cycle Time(1)
100
30
TOSL,
TOSH
External Clock in (OSC1)
High or Low Time
—
XT Oscillator mode
LP Oscillator mode
HS Oscillator mode
XT Oscillator mode
LP Oscillator mode
HS Oscillator mode
2.5
10
—
—
4
TOSR,
TOSF
External Clock in (OSC1)
Rise or Fall Time
—
20
50
7.5
—
—
Note 1: Instruction cycle period (TCY) equals four times the input oscillator time base period for all configurations
except PLL. All specified values are based on characterization data for that particular oscillator type under
standard operating conditions with the device executing code. Exceeding these specified limits may result
in an unstable oscillator operation and/or higher than expected current consumption. All devices are tested
to operate at “min.” values with an external clock applied to the OSC1/CLKI pin. When an external clock
input is used, the “max.” cycle time limit is “DC” (no clock) for all devices.
© 2007 Microchip Technology Inc.
Preliminary
DS39761B-page 435
PIC18F2682/2685/4682/4685
TABLE 27-7: PLL CLOCK TIMING SPECIFICATIONS (VDD = 4.2V TO 5.5V)
Param
Sym
Characteristic
Min
Typ†
Max
Units Conditions
No.
F10
FOSC Oscillator Frequency Range
4
—
—
—
—
10
40
2
MHz HS mode only
F11
F12
F13
FSYS On-Chip VCO System Frequency
16
—
-2
MHz HS mode only
trc
PLL Start-up Time (Lock Time)
ms
%
ΔCLK CLKO Stability (Jitter)
+2
†
Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance
only and are not tested.
TABLE 27-8: AC CHARACTERISTICS: INTERNAL RC ACCURACY
PIC18F2682/2685/4682/4685 (INDUSTRIAL)
PIC18LF2682/2685/4682/4685 (INDUSTRIAL)
PIC18LF2682/2685/4682/4685 Standard Operating Conditions (unless otherwise stated)
(Industrial)
Operating temperature
-40°C ≤ TA ≤ +85°C for industrial
PIC18F2682/2685/4682/4685 Standard Operating Conditions (unless otherwise stated)
(Industrial) Operating temperature -40°C ≤ TA ≤ +85°C for industrial
Param
No.
Device
Min
Typ
Max Units
Conditions
INTOSC Accuracy @ Freq = 8 MHz, 4 MHz, 2 MHz, 1 MHz, 500 kHz, 250 kHz, 125 kHz(1)
PIC18LF268X/468X
-2
-5
+/-1
—
2
5
%
%
%
+25°C
VDD = 2.7-3.3V
VDD = 2.7-3.3V
VDD = 2.7-3.3V
-10°C to +85°C
-40°C to +85°C
-10
+/-1
10
INTRC Accuracy @ Freq = 31 kHz(2)
PIC18LF268X/468X 26.562
Legend: Shading of rows is to assist in readability of the table.
—
35.938 kHz
-40°C to +85°C
VDD = 2.7-3.3V
Note 1: Frequency calibrated at 25°C. OSCTUNE register can be used to compensate for temperature drift.
2: INTRC frequency after calibration.
DS39761B-page 436
Preliminary
© 2007 Microchip Technology Inc.
PIC18F2682/2685/4682/4685
FIGURE 27-6:
CLKO AND I/O TIMING
Q1
Q2
Q3
Q4
OSC1
11
10
CLKO
13
12
19
18
14
16
I/O pin
(Input)
15
17
I/O pin
(Output)
New Value
Old Value
20, 21
Refer to Figure 27-4 for load conditions.
Note:
TABLE 27-9: CLKO AND I/O TIMING REQUIREMENTS
Param
Symbol
Characteristic
Min
Typ
Max
Units Conditions
No.
10
TOSH2CKL OSC1 ↑ to CLKO ↓
TOSH2CKH OSC1 ↑ to CLKO ↑
—
—
—
—
—
75
75
35
35
—
—
—
50
—
—
200
200
100
100
ns (Note 1)
ns (Note 1)
ns (Note 1)
ns (Note 1)
11
12
13
14
15
16
17
18
18A
TCKR
TCKF
CLKO Rise Time
CLKO Fall Time
TCKL2IOV CLKO ↓ to Port Out Valid
0.5 TCY + 20 ns (Note 1)
TIOV2CKH Port In Valid before CLKO ↑
TCKH2IOI Port In Hold after CLKO ↑
0.25 TCY + 25
—
—
ns (Note 1)
ns (Note 1)
ns
0
TOSH2IOV OSC1 ↑ (Q1 cycle) to Port Out Valid
TOSH2IOI OSC1 ↑ (Q2 cycle) to Port PIC18FXXXX
—
150
—
100
200
ns
Input Invalid (I/O in hold
time)
PIC18LFXXXX
—
ns VDD = 2.0V
19
TIOV2OSH Port Input Valid to OSC1 ↑ (I/O in
0
—
—
ns
setup time)
20
TIOR
TIOF
Port Output Rise Time
Port Output Fall Time
INTx pin High or Low Time
PIC18FXXXX
PIC18LFXXXX
PIC18FXXXX
PIC18LFXXXX
—
—
10
—
10
—
—
—
—
25
60
25
60
—
—
—
ns
20A
21
ns VDD = 2.0V
—
ns
21A
22†
23†
24†
—
ns VDD = 2.0V
TINP
TCY
TCY
20
ns
ns
ns
TRBP
TRCP
RB7:RB4 Change INTx High or Low Time
RC7:RC4 Change INTx High or Low Time
†
These parameters are asynchronous events not related to any internal clock edges.
Note 1: Measurements are taken in RC mode, where CLKO output is 4 x TOSC.
© 2007 Microchip Technology Inc.
Preliminary
DS39761B-page 437
PIC18F2682/2685/4682/4685
FIGURE 27-7:
RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND
POWER-UP TIMER TIMING
VDD
MCLR
30
Internal
POR
33
PWRT
Time-out
32
OSC
Time-out
Internal
Reset
Watchdog
Timer
Reset
31
34
34
I/O pins
Note:
Refer to Figure 27-4 for load conditions.
FIGURE 27-8:
BROWN-OUT RESET TIMING
BVDD
VDD
35
VBGAP = 1.2V
VIRVST
Enable Internal
Reference Voltage
Internal Reference
Voltage Stable
36
TABLE 27-10: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER
AND BROWN-OUT RESET REQUIREMENTS
Param.
No.
Sym
Characteristic
Min
Typ
Max
Units
Conditions
30
TMCL
TWDT
MCLR Pulse Width (low)
2
—
—
μs
31
Watchdog Timer Time-out Period (no
postscaler)
3.4
4.00
4.6
ms
32
33
34
TOST
Oscillation Start-up Timer Period
1024 TOSC
55.6
—
65.5
2
1024 TOSC
—
ms
μs
TOSC = OSC1 period
TPWRT Power-up Timer Period
75
—
TIOZ
I/O High-Impedance from MCLR Low
or Watchdog Timer Reset
—
35
36
TBOR
Brown-out Reset Pulse Width
200
—
—
—
μs
μs
VDD ≤ BVDD (see D005)
VDD ≤ VLVD
TIRVST Time for Internal Reference Voltage to
become stable
20
50
37
38
39
TLVD
TCSD
High/Low-Voltage Detect Pulse Width
CPU Start-up Time
200
—
—
10
1
—
—
—
μs
μs
μs
TIOBST Time for INTOSC to stabilize
—
DS39761B-page 438
Preliminary
© 2007 Microchip Technology Inc.
PIC18F2682/2685/4682/4685
FIGURE 27-9:
TIMER0 AND TIMER1 EXTERNAL CLOCK TIMINGS
T0CKI
41
40
42
T1OSO/T13CKI
46
45
47
48
TMR0 or
TMR1
Note:
Refer to Figure 27-4 for load conditions.
TABLE 27-11: TIMER0 AND TIMER1 EXTERNAL CLOCK REQUIREMENTS
Param
Sym
Characteristic
Min
Max Units
Conditions
No.
40
TT0H
T0CKI High Pulse Width
No prescaler
With prescaler
No prescaler
With prescaler
No prescaler
With prescaler
0.5 TCY + 20
10
—
—
—
—
—
—
ns
ns
ns
ns
ns
41
42
TT0L
TT0P
T0CKI Low Pulse Width
T0CKI Period
0.5 TCY + 20
10
TCY + 10
Greater of:
20 ns or
ns N = prescale value
(1, 2, 4,..., 256)
(TCY + 40)/N
45
46
TT1H
TT1L
T13CKI High Synchronous, no prescaler
0.5 TCY + 20
—
—
—
—
—
—
—
—
—
—
—
ns
Time
Synchronous, PIC18FXXXX
10
ns
with prescaler
PIC18LFXXXX
25
ns VDD = 2.0V
Asynchronous PIC18FXXXX
PIC18LFXXXX
30
ns
50
ns VDD = 2.0V
T13CKI Low Synchronous, no prescaler
0.5 TCY + 5
ns
Time
Synchronous, PIC18FXXXX
10
25
30
50
ns
with prescaler
PIC18LFXXXX
ns VDD = 2.0V
ns
Asynchronous PIC18FXXXX
PIC18LFXXXX
ns VDD = 2.0V
47
48
TT1P
FT1
T13CKI Input Synchronous
Period
Greater of:
20 ns or
(TCY + 40)/N
ns N = prescale value
(1, 2, 4, 8)
Asynchronous
60
DC
—
50
ns
kHz
—
T13CKI Oscillator Input Frequency Range
TCKE2TMRI Delay from External T13CKI Clock Edge to
Timer Increment
2 TOSC
7 TOSC
© 2007 Microchip Technology Inc.
Preliminary
DS39761B-page 439
PIC18F2682/2685/4682/4685
FIGURE 27-10:
CAPTURE/COMPARE/PWM TIMINGS (ALL CCP MODULES)
CCPx
(Capture Mode)
50
51
52
54
CCPx
(Compare or PWM Mode)
53
Note:
Refer to Figure 27-4 for load conditions.
TABLE 27-12: CAPTURE/COMPARE/PWM REQUIREMENTS (ALL CCP MODULES)
Param
Sym
Characteristic
Min
Max
Units
Conditions
No.
50
TCCL CCPx Input Low No prescaler
Time
0.5 TCY + 20
—
—
—
—
—
—
—
ns
ns
ns
ns
ns
ns
ns
With prescaler PIC18FXXXX
10
PIC18LFXXXX
20
VDD = 2.0V
VDD = 2.0V
51
TCCH CCPx Input High No prescaler
Time
0.5 TCY + 20
With prescaler PIC18FXXXX
PIC18LFXXXX
10
20
52
53
TCCP CCPx Input Period
3 TCY + 40
N
N = prescale
value (1, 4 or 16)
TCCR CCPx Output Fall Time
TCCF CCPx Output Fall Time
PIC18FXXXX
PIC18LFXXXX
PIC18FXXXX
PIC18LFXXXX
—
—
—
—
25
45
25
45
ns
ns
ns
ns
VDD = 2.0V
VDD = 2.0V
54
DS39761B-page 440
Preliminary
© 2007 Microchip Technology Inc.
PIC18F2682/2685/4682/4685
FIGURE 27-11:
PARALLEL SLAVE PORT TIMING (PIC18F4682/4685)
RE2/CS
RE0/RD
RE1/WR
65
RD7:RD0
62
64
63
Note:
Refer to Figure 27-4 for load conditions.
TABLE 27-13: PARALLEL SLAVE PORT REQUIREMENTS (PIC18F4682/4685)
Param.
Symbol
Characteristic
Min
Max Units Conditions
No.
62
TDTV2WRH Data In Valid before WR ↑ or CS ↑ (setup time)
20
—
—
ns
63
TWRH2DTI WR ↑ or CS ↑ to Data–In Invalid
PIC18FXXXX
20
ns
(hold time)
PIC18LFXXXX 35
—
ns VDD = 2.0V
64
65
66
TRDL2DTV RD ↓ and CS ↓ to Data–Out Valid
TRDH2DTI RD ↑ or CS ↓ to Data–Out Invalid
TIBFINH
—
80
ns
ns
10
30
Inhibit of the IBF Flag bit being Cleared from WR ↑ or CS ↑
—
3 TCY
© 2007 Microchip Technology Inc.
Preliminary
DS39761B-page 441
PIC18F2682/2685/4682/4685
FIGURE 27-12:
EXAMPLE SPI MASTER MODE TIMING (CKE = 0)
70
SCK
(CKP = 0)
71
72
78
79
78
SCK
(CKP = 1)
79
80
MSb
bit 6 - - - - - -1
LSb
SDO
SDI
75, 76
MSb In
74
bit 6 - - - -1
LSb In
73
Note: Refer to Figure 27-4 for load conditions.
TABLE 27-14: EXAMPLE SPI MODE REQUIREMENTS (MASTER MODE, CKE = 0)
Param
No.
Symbol
Characteristic
Min
Max Units Conditions
73
TDIV2SCH, Setup Time of SDI Data Input to SCK Edge
TDIV2SCL
100
—
—
ns
ns
74
75
TSCH2DIL, Hold Time of SDI Data Input to SCK Edge
TSCL2DIL
100
TDOR
SDO Data Output Rise Time
PIC18FXXXX
—
—
—
—
—
—
—
—
25
45
25
25
45
25
50
100
ns
PIC18LFXXXX
ns VDD = 2.0V
76
78
TDOF
TSCR
SDO Data Output Fall Time
SCK Output Rise Time
ns
PIC18FXXXX
ns
PIC18LFXXXX
ns VDD = 2.0V
79
80
TSCF
SCK Output Fall Time
ns
TSCH2DOV, SDO Data Output Valid after
TSCL2DOV SCK Edge
PIC18FXXXX
ns
PIC18LFXXXX
ns VDD = 2.0V
DS39761B-page 442
Preliminary
© 2007 Microchip Technology Inc.
PIC18F2682/2685/4682/4685
FIGURE 27-13:
EXAMPLE SPI MASTER MODE TIMING (CKE = 1)
81
SCK
(CKP = 0)
71
72
79
78
73
SCK
(CKP = 1)
80
LSb
MSb
bit 6 - - - - - -1
SDO
SDI
75, 76
MSb In
74
bit 6 - - - -1
LSb In
Note: Refer to Figure 27-4 for load conditions.
TABLE 27-15: EXAMPLE SPI MODE REQUIREMENTS (MASTER MODE, CKE = 1)
Param.
No.
Symbol
Characteristic
Min
Max Units Conditions
73
TDIV2SCH, Setup Time of SDI Data Input to SCK Edge
TDIV2SCL
100
—
—
ns
ns
74
75
TSCH2DIL, Hold Time of SDI Data Input to SCK Edge
TSCL2DIL
100
TDOR
SDO Data Output Rise Time PIC18FXXXX
PIC18LFXXXX
—
—
25
45
25
25
45
25
50
100
—
ns
ns VDD = 2.0V
76
78
TDOF
TSCR
SDO Data Output Fall Time
—
ns
SCK Output Rise Time
SCK Output Fall Time
PIC18FXXXX
—
ns
PIC18LFXXXX
—
ns VDD = 2.0V
79
80
TSCF
—
ns
TSCH2DOV, SDO Data Output Valid after PIC18FXXXX
—
ns
TSCL2DOV SCK Edge
PIC18LFXXXX
—
ns VDD = 2.0V
ns
81
TDOV2SCH, SDO Data Output Setup to SCK Edge
TDOV2SCL
TCY
© 2007 Microchip Technology Inc.
Preliminary
DS39761B-page 443
PIC18F2682/2685/4682/4685
FIGURE 27-14:
EXAMPLE SPI SLAVE MODE TIMING (CKE = 0)
SS
70
SCK
(CKP = 0)
83
71
72
78
79
79
78
SCK
(CKP = 1)
80
MSb
LSb
SDO
SDI
bit 6 - - - - - -1
77
75, 76
MSb In
74
bit 6 - - - -1
LSb In
73
Note:
Refer to Figure 27-4 for load conditions.
TABLE 27-16: EXAMPLE SPI MODE REQUIREMENTS (SLAVE MODE TIMING, CKE = 0)
Param
No.
Symbol
Characteristic
Min
Max Units Conditions
70
TSSL2SCH, SS ↓ to SCK ↓ or SCK ↑ Input
TSSL2SCL
TCY
—
ns
71
TSCH
SCK Input High Time
SCK Input Low Time
Continuous
Single Byte
Continuous
Single Byte
1.25 TCY + 30
—
—
—
—
—
ns
71A
72
40
1.25 TCY + 30
40
ns (Note 1)
TSCL
ns
72A
73
ns (Note 1)
TDIV2SCH, Setup Time of SDI Data Input to SCK Edge
TDIV2SCL
100
ns
73A
74
TB2B
Last Clock Edge of Byte1 to the First Clock Edge of Byte 2 1.5 TCY + 40
—
—
ns (Note 2)
TSCH2DIL, Hold Time of SDI Data Input to SCK Edge
TSCL2DIL
100
ns
75
TDOR
SDO Data Output Rise Time
PIC18FXXXX
PIC18LFXXXX
—
25
45
25
50
50
100
—
ns
—
ns VDD = 2.0V
76
77
80
TDOF
SDO Data Output Fall Time
—
ns
TSSH2DOZ SS ↑ to SDO Output High-Impedance
10
ns
TSCH2DOV, SDO Data Output Valid after SCK Edge PIC18FXXXX
TSCL2DOV
—
—
ns
PIC18LFXXXX
ns VDD = 2.0V
ns
83
TscH2ssH, SS ↑ after SCK Edge
TscL2ssH
1.5 TCY + 40
Note 1: Requires the use of parameter 73A.
2: Only if parameter 71A and 72A are used.
DS39761B-page 444
Preliminary
© 2007 Microchip Technology Inc.
PIC18F2682/2685/4682/4685
FIGURE 27-15:
EXAMPLE SPI SLAVE MODE TIMING (CKE = 1)
82
SS
70
SCK
83
(CKP = 0)
71
72
SCK
(CKP = 1)
80
MSb
LSb
bit 6 - - - - - -1
SDO
SDI
75, 76
77
MSb In
74
LSb In
bit 6 - - - -1
Note: Refer to Figure 27-4 for load conditions.
TABLE 27-17: EXAMPLE SPI SLAVE MODE REQUIREMENTS (CKE = 1)
Param
No.
Symbol
Characteristic
Min
Max Units Conditions
70
TSSL2SCH, SS ↓ to SCK ↓ or SCK ↑ Input
TSSL2SCL
TCY
—
ns
71
TSCH
TSCL
TB2B
SCK Input High Time
SCK Input Low Time
Continuous
Single Byte
Continuous
Single Byte
1.25 TCY + 30
—
—
—
—
—
—
ns
71A
72
40
1.25 TCY + 30
40
ns (Note 1)
ns
72A
73A
74
ns (Note 1)
ns (Note 2)
ns
Last Clock Edge of Byte 1 to the fIrst Clock Edge of Byte 2 1.5 TCY + 40
TSCH2DIL, Hold Time of SDI Data Input to SCK Edge
TSCL2DIL
100
75
TDOR
SDO Data Output Rise Time
PIC18FXXXX
—
25
45
25
50
50
ns
PIC18LFXXXX
—
ns VDD = 2.0V
76
77
80
TDOF
SDO Data Output Fall Time
—
ns
TSSH2DOZ SS↑ to SDO Output High-Impedance
TSCH2DOV, SDO Data Output Valid after SCK PIC18FXXXX
10
ns
—
ns
TSCL2DOV Edge
PIC18LFXXXX
—
100
50
ns VDD = 2.0V
82
83
TSSL2DOV SDO Data Output Valid after SS ↓ PIC18FXXXX
—
—
ns
Edge
PIC18LFXXXX
100
—
ns VDD = 2.0V
ns
TSCH2SSH, SS ↑ after SCK Edge
TSCL2SSH
1.5 TCY + 40
Note 1: Requires the use of parameter 73A.
2: Only if parameter 71A and 72A are used.
© 2007 Microchip Technology Inc.
Preliminary
DS39761B-page 445
PIC18F2682/2685/4682/4685
FIGURE 27-16:
I2C™ BUS START/STOP BITS TIMING
SCL
91
93
90
92
SDA
Stop
Condition
Start
Condition
Note: Refer to Figure 27-4 for load conditions.
TABLE 27-18: I2C™ BUS START/STOP BITS REQUIREMENTS (SLAVE MODE)
Param.
Symbol
Characteristic
Min
Max
Units
Conditions
No.
90
TSU:STA Start Condition
Setup Time
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
4700
600
—
—
—
—
—
—
—
—
ns
Only relevant for Repeated
Start condition
91
92
93
THD:STA Start Condition
Hold Time
4000
600
ns
ns
ns
After this period, the first
clock pulse is generated
TSU:STO Stop Condition
Setup Time
4700
600
THD:STO Stop Condition
Hold Time
4000
600
FIGURE 27-17:
I2C™ BUS DATA TIMING
103
102
100
101
SCL
90
106
107
91
92
SDA
In
110
109
109
SDA
Out
Note: Refer to Figure 27-4 for load conditions.
DS39761B-page 446
Preliminary
© 2007 Microchip Technology Inc.
PIC18F2682/2685/4682/4685
TABLE 27-19: I2C™ BUS DATA REQUIREMENTS (SLAVE MODE)
Param.
No.
Symbol
Characteristic
Min
Max Units
Conditions
100
THIGH
Clock High Time
100 kHz mode
4.0
—
—
μs
μs
PIC18FXXXX must operate
at a minimum of 1.5 MHz
400 kHz mode
0.6
PIC18FXXXX must operate
at a minimum of 10 MHz
MSSP module
100 kHz mode
1.5 TCY
4.7
—
—
101
TLOW
Clock Low Time
μs
μs
PIC18FXXXX must operate
at a minimum of 1.5 MHz
400 kHz mode
MSSP module
1.3
—
PIC18FXXXX must operate
at a minimum of 10 MHz
1.5 TCY
—
—
102
103
TR
TF
SDA and SCL Rise 100 kHz mode
Time
1000
ns
ns
400 kHz mode 20 + 0.1 CB 300
CB is specified to be from
10 to 400 pF
SDA and SCL Fall 100 kHz mode
Time
—
300
ns
ns
400 kHz mode 20 + 0.1 CB 300
CB is specified to be from
10 to 400 pF
90
TSU:STA
THD:STA
Start Condition
Setup Time
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
4.7
0.6
4.0
0.6
0
—
—
μs
μs
μs
μs
ns
μs
ns
ns
μs
μs
ns
ns
μs
μs
Only relevant for Repeated
Start condition
91
Start Condition
Hold Time
—
After this period, the first
clock pulse is generated
—
106
107
92
THD:DAT Data Input Hold
Time
—
0
0.9
—
TSU:DAT
TSU:STO
TAA
Data Input Setup
Time
250
100
4.7
0.6
—
(Note 2)
—
Stop Condition
Setup Time
—
—
109
110
Output Valid from
Clock
3500
—
(Note 1)
—
TBUF
Bus Free Time
4.7
1.3
—
Time the bus must be free
before a new transmission
can start
—
D102
CB
Bus Capacitive Loading
—
400
pF
Note 1: As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region
(min. 300 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions.
2: A Fast mode I2C™ bus device can be used in a Standard mode I2C bus system but the requirement,
TSU:DAT ≥ 250 ns, must then be met. This will automatically be the case if the device does not stretch the
LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must
output the next data bit to the SDA line, TR max. + TSU:DAT = 1000 + 250 = 1250 ns (according to the
Standard mode I2C bus specification), before the SCL line is released.
© 2007 Microchip Technology Inc.
Preliminary
DS39761B-page 447
PIC18F2682/2685/4682/4685
FIGURE 27-18:
MASTER SSP I2C™ BUS START/STOP BITS TIMING WAVEFORMS
SCL
93
91
90
92
SDA
Stop
Condition
Start
Condition
Note: Refer to Figure 27-4 for load conditions.
TABLE 27-20: MASTER SSP I2C™ BUS START/STOP BITS REQUIREMENTS
Param.
Symbol
Characteristic
Min
Max Units
Conditions
No.
90
TSU:STA Start condition
Setup Time
100 kHz mode
400 kHz mode
1 MHz mode(1) 2(TOSC)(BRG + 1)
2(TOSC)(BRG + 1)
2(TOSC)(BRG + 1)
—
—
—
—
—
—
—
—
—
—
—
—
ns Only relevant for
Repeated Start condition
91
92
93
THD:STA Start Condition
Hold Time
100 kHz mode
2(TOSC)(BRG + 1)
ns After this period, the first
clock pulse is generated
400 kHz mode
1 MHz mode(1) 2(TOSC)(BRG + 1)
2(TOSC)(BRG + 1)
TSU:STO Stop Condition
Setup Time
100 kHz mode
2(TOSC)(BRG + 1)
ns
ns
400 kHz mode
1 MHz mode(1) 2(TOSC)(BRG + 1)
2(TOSC)(BRG + 1)
THD:STO Stop Condition
Hold Time
100 kHz mode
2(TOSC)(BRG + 1)
400 kHz mode
1 MHz mode(1) 2(TOSC)(BRG + 1)
2(TOSC)(BRG + 1)
Note 1: Maximum pin capacitance = 10 pF for all I2C pins.
FIGURE 27-19:
MASTER SSP I2C™ BUS DATA TIMING
103
102
100
101
SCL
90
106
91
92
107
SDA
In
110
109
109
SDA
Out
Note: Refer to Figure 27-4 for load conditions.
DS39761B-page 448
Preliminary
© 2007 Microchip Technology Inc.
PIC18F2682/2685/4682/4685
TABLE 27-21: MASTER SSP I2C™ BUS DATA REQUIREMENTS
Param.
No.
Symbol
Characteristic
Min
Max Units
Conditions
100
101
102
103
90
THIGH
Clock High
Time
100 kHz mode
400 kHz mode
1 MHz mode(1) 2(TOSC)(BRG + 1)
2(TOSC)(BRG + 1)
2(TOSC)(BRG + 1)
—
—
ms
ms
ms
ms
ms
ms
ns
—
TLOW
TR
Clock Low Time 100 kHz mode
400 kHz mode
2(TOSC)(BRG + 1)
—
2(TOSC)(BRG + 1)
—
1 MHz mode(1) 2(TOSC)(BRG + 1)
—
SDA and SCL 100 kHz mode
Rise Time
—
1000
300
300
300
300
100
—
CB is specified to be from
10 to 400 pF
400 kHz mode
1 MHz mode(1)
20 + 0.1 CB
ns
—
—
ns
TF
SDA and SCL 100 kHz mode
Fall Time
ns
CB is specified to be from
10 to 400 pF
400 kHz mode
1 MHz mode(1)
20 + 0.1 CB
—
ns
ns
TSU:STA Start Condition 100 kHz mode
2(TOSC)(BRG + 1)
ms Only relevant for
Setup Time
Repeated Start
condition
ms
400 kHz mode
1 MHz mode(1) 2(TOSC)(BRG + 1)
2(TOSC)(BRG + 1)
—
ms
—
91
THD:STA Start Condition 100 kHz mode
2(TOSC)(BRG + 1)
—
ms After this period, the first
Hold Time
clock pulse is generated
400 kHz mode
2(TOSC)(BRG + 1)
—
ms
1 MHz mode(1) 2(TOSC)(BRG + 1)
—
ms
ns
106
107
92
THD:DAT Data Input
Hold Time
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
0
—
0
0.9
—
ms
TSU:DAT Data Input
Setup Time
250
ns
ns
(Note 2)
100
—
TSU:STO Stop Condition 100 kHz mode
2(TOSC)(BRG + 1)
2(TOSC)(BRG + 1)
1 MHz mode(1) 2(TOSC)(BRG + 1)
—
ms
ms
ms
ns
Setup Time
400 kHz mode
—
—
109
TAA
Output Valid
from Clock
100 kHz mode
400 kHz mode
1 MHz mode(1)
—
—
3500
1000
—
ns
—
ns
110
TBUF
CB
Bus Free Time 100 kHz mode
400 kHz mode
4.7
1.3
—
ms Time the bus must be free
before a new transmission
—
ms
can start
pF
D102
Bus Capacitive Loading
—
400
Note 1: Maximum pin capacitance = 10 pF for all I2C pins.
2: A Fast mode I2C™ bus device can be used in a Standard mode I2C bus system, but
parameter 107 ≥ 250 ns must then be met. This will automatically be the case if the device does not stretch
the LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must
output the next data bit to the SDA line, parameter 102 + parameter 107 = 1000 + 250 = 1250 ns (for
100 kHz mode), before the SCL line is released.
© 2007 Microchip Technology Inc.
Preliminary
DS39761B-page 449
PIC18F2682/2685/4682/4685
FIGURE 27-20:
EUSART SYNCHRONOUS TRANSMISSION (MASTER/SLAVE) TIMING
RC6/TX/CK
pin
121
121
RC7/RX/DT
pin
120
Note: Refer to Figure 27-4 for load conditions.
122
TABLE 27-22: EUSART SYNCHRONOUS TRANSMISSION REQUIREMENTS
Param
Symbol
Characteristic
Min
Max
Units Conditions
No.
120
TCKH2DTV SYNC XMIT (MASTER & SLAVE)
Clock High to Data Out Valid
PIC18FXXXX
—
—
—
—
—
—
40
100
20
ns
PIC18LFXXXX
ns VDD = 2.0V
ns
121
122
TCKRF
TDTRF
Clock Out Rise Time and Fall Time PIC18FXXXX
(Master mode)
PIC18LFXXXX
50
ns VDD = 2.0V
ns
Data Out Rise Time and Fall Time
PIC18FXXXX
20
PIC18LFXXXX
50
ns VDD = 2.0V
FIGURE 27-21:
EUSART SYNCHRONOUS RECEIVE (MASTER/SLAVE) TIMING
RC6/TX/CK
pin
125
RC7/RX/DT
pin
126
Note: Refer to Figure 27-4 for load conditions.
TABLE 27-23: EUSART SYNCHRONOUS RECEIVE REQUIREMENTS
Param.
Symbol
Characteristic
Min
Max
Units
Conditions
No.
125
TDTV2CKL SYNC RCV (MASTER & SLAVE)
Data Hold before CK ↓ (DT hold time)
10
15
—
—
ns
ns
126
TCKL2DTL Data Hold after CK ↓ (DT hold time)
DS39761B-page 450
Preliminary
© 2007 Microchip Technology Inc.
PIC18F2682/2685/4682/4685
TABLE 27-24: A/D CONVERTER CHARACTERISTICS: PIC18F2682/2685/4682/4685 (INDUSTRIAL)
PIC18LF2682/2685/4682/4685 (INDUSTRIAL)
Param
No.
Sym
Characteristic
Min
Typ
Max
Units
Conditions
A01
NR
Resolution
—
—
—
—
—
—
10
bit ΔVREF ≥ 3.0V
A03
A04
A06
A07
A10
A20
EIL
Integral Linearity Error
Differential Linearity Error
Offset Error
—
< 1
< 1
< 1
< 1
LSb ΔVREF ≥ 3.0V
LSb ΔVREF ≥ 3.0V
LSb ΔVREF ≥ 3.0V
LSb ΔVREF ≥ 3.0V
—
EDL
EOFF
EGN
—
—
—
Gain Error
—
Monotonicity
Guaranteed(1)
ΔVREF Reference Voltage Range
3
—
AVDD – AVSS
V
For 10-bit resolution
(VREFH – VREFL)
A21
A22
A25
A28
A29
A30
VREFH Reference Voltage High
VREFL Reference Voltage Low
AVSS + 3.0V
AVSS – 0.3V
VREFL
—
—
—
—
—
—
AVDD + 0.3V
AVDD – 3.0V
VREFH
V
V
For 10-bit resolution
For 10-bit resolution
VAIN
Analog Input Voltage
V
AVDD Analog Supply Voltage
VDD – 0.3
VSS – 0.3
—
VDD + 0.3
VSS + 0.3
2.5
V
AVSS
ZAIN
Analog Supply Voltage
V
Recommended Impedance of
Analog Voltage Source
kΩ
A40
IAD
A/D Conversion PIC18FXXXX
Current (VDD)
—
—
180
90
—
—
μA Average current
consumption when
A/D is on (Note 2)
PIC18LFXXXX
μA VDD = 2.0V;
average current
consumption when
A/D is on (Note 2)
A50
IREF
VREF Input Current (Note 3)
—
—
—
—
5
150
μA During VAIN acquisition.
μA During A/D conversion
cycle.
Note 1: The A/D conversion result never decreases with an increase in the input voltage and has no missing codes.
2: When A/D is off, it will not consume any current other than minor leakage current. The power-down current
spec includes any such leakage from the A/D module.
3: VREFH current is from RA3/AN3/VREF+ pin or AVDD, whichever is selected as the VREFH source.
VREFL current is from RA2/AN2/VREF- pin or AVSS, whichever is selected as the VREFL source.
© 2007 Microchip Technology Inc.
Preliminary
DS39761B-page 451
PIC18F2682/2685/4682/4685
FIGURE 27-22:
A/D CONVERSION TIMING
BSF ADCON0, GO
(Note 2)
131
130
Q4
A/D CLK(1)
132
. . .
. . .
9
8
7
2
1
0
A/D DATA
ADRES
NEW_DATA
TCY
OLD_DATA
ADIF
GO
DONE
SAMPLING STOPPED
SAMPLE
Note 1: If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts.
This allows the SLEEPinstruction to be executed.
2: This is a minimal RC delay (typically 100 ns), which also disconnects the holding capacitor from the analog input.
TABLE 27-25: A/D CONVERSION REQUIREMENTS
Param
Symbol
Characteristic
Min
Max
Units
Conditions
No.
130
TAD
A/D Clock Period
PIC18FXXXX
0.7
1.4
25.0(1)
25.0(1)
μs TOSC based, VREF ≥ 3.0V
PIC18LFXXXX
μs VDD = 2.0V;
TOSC based, VREF full range
PIC18FXXXX
—
—
11
1
3
μs A/D RC mode
μs VDD = 2.0V; A/D RC mode
TAD
PIC18LFXXXX
131
TCNV
Conversion Time
12
(not including acquisition time) (Note 2)
Acquisition Time (Note 3)
132
135
136
TACQ
TSWC
TAMP
1.4
—
1
—
(Note 4)
—
μs -40°C to +85°C
Switching Time from Convert → Sample
Amplifier Settling Time (Note 5)
μs This may be used if the “new” input
voltage has not changed by more
than 1 LSb (i.e., 5 mV @ 5.12V)
from the last sampled voltage (as
stated on CHOLD).
Note 1: The time of the A/D clock period is dependent on the device frequency and the TAD clock divider.
2: ADRES register may be read on the following TCY cycle.
3: The time for the holding capacitor to acquire the “New” input voltage when the voltage changes full scale
after the conversion (AVDD to AVSS or AVSS to AVDD). The source impedance (RS) on the input channels is
50Ω.
4: On the following cycle of the device clock.
5: See Section 19.0 “10-Bit Analog-to-Digital Converter (A/D) Module” for minimum conditions when input
voltage has changed more than 1 LSb.
DS39761B-page 452
Preliminary
© 2007 Microchip Technology Inc.
PIC18F2682/2685/4682/4685
28.0 DC AND AC
CHARACTERISTICS GRAPHS
AND TABLES
Graphs and tables are not available at this time.
© 2007 Microchip Technology Inc.
Preliminary
DS39761B-page 453
PIC18F2682/2685/4682/4685
NOTES:
DS39761B-page 454
Preliminary
© 2007 Microchip Technology Inc.
PIC18F2682/2685/4682/4685
29.0 PACKAGING INFORMATION
29.1 Package Marking Information
28-Lead PDIP (Skinny DIP)
Example
e
3
PIC18F2685-I/SP
0710017
XXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXX
YYWWNNN
28-Lead SOIC
Example
e
3
XXXXXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXXXXX
PIC18F2685-E/SO
0710017
YYWWNNN
40-Lead PDIP
Example
e
3
XXXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXXX
YYWWNNN
PIC18F4685-I/P
0710017
Legend: XX...X Customer-specific information
Y
YY
Year code (last digit of calendar year)
Year code (last 2 digits of calendar year)
WW
NNN
Week code (week of January 1 is week ‘01’)
Alphanumeric traceability code
Pb-free JEDEC designator for Matte Tin (Sn)
This package is Pb-free. The Pb-free JEDEC designator (
can be found on the outer packaging for this package.
e
3
*
)
e
3
Note: In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
© 2007 Microchip Technology Inc.
Preliminary
DS39761B-page 455
PIC18F2682/2685/4682/4685
29.1 Package Marking Information (Continued)
44-Lead TQFP
Example
-I/PT
XXXXXXXXXX
XXXXXXXXXX
XXXXXXXXXX
YYWWNNN
PIC18F4685
e
3
0710017
44-Lead QFN
Example
XXXXXXXXXX
XXXXXXXXXX
XXXXXXXXXX
YYWWNNN
PIC18F4685
3
e
-I/ML
0710017
DS39761B-page 456
Preliminary
© 2007 Microchip Technology Inc.
PIC18F2682/2685/4682/4685
29.2 Package Details
The following sections give the technical details of the packages.
28-Lead Skinny Plastic Dual In-Line (SP) – 300 mil Body [SPDIP]
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
N
NOTE 1
E1
1
2 3
D
E
A2
A
L
c
b1
A1
b
e
eB
Units
INCHES
NOM
28
Dimension Limits
MIN
MAX
Number of Pins
Pitch
N
e
.100 BSC
–
Top to Seating Plane
A
–
.200
.150
–
Molded Package Thickness
Base to Seating Plane
Shoulder to Shoulder Width
Molded Package Width
Overall Length
A2
A1
E
.120
.015
.290
.240
1.345
.110
.008
.040
.014
–
.135
–
.310
.285
1.365
.130
.010
.050
.018
–
.335
.295
1.400
.150
.015
.070
.022
.430
E1
D
Tip to Seating Plane
Lead Thickness
L
c
Upper Lead Width
b1
b
Lower Lead Width
Overall Row Spacing §
eB
Notes:
1. Pin 1 visual index feature may vary, but must be located within the hatched area.
2. § Significant Characteristic.
3. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" per side.
4. Dimensioning and tolerancing per ASME Y14.5M.
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
Microchip Technology Drawing C04-070B
© 2007 Microchip Technology Inc.
Preliminary
DS39761B-page 457
PIC18F2682/2685/4682/4685
28-Lead Plastic Small Outline (SO) – Wide, 7.50 mm Body [SOIC]
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
D
N
E
E1
NOTE 1
1
2
3
e
b
h
α
h
c
φ
A2
A
L
A1
L1
β
Units
MILLMETERS
Dimension Limits
MIN
NOM
MAX
Number of Pins
Pitch
N
e
28
1.27 BSC
Overall Height
A
–
–
2.65
–
Molded Package Thickness
Standoff §
A2
A1
E
2.05
0.10
–
–
0.30
Overall Width
10.30 BSC
Molded Package Width
Overall Length
Chamfer (optional)
Foot Length
E1
D
h
7.50 BSC
17.90 BSC
0.25
0.40
–
0.75
1.27
L
–
Footprint
L1
φ
c
1.40 REF
Foot Angle Top
Lead Thickness
Lead Width
0°
0.18
0.31
5°
–
–
–
–
–
8°
0.33
0.51
15°
b
Mold Draft Angle Top
Mold Draft Angle Bottom
α
β
5°
15°
Notes:
1. Pin 1 visual index feature may vary, but must be located within the hatched area.
2. § Significant Characteristic.
3. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.15 mm per side.
4. Dimensioning and tolerancing per ASME Y14.5M.
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
REF: Reference Dimension, usually without tolerance, for information purposes only.
Microchip Technology Drawing C04-052B
DS39761B-page 458
Preliminary
© 2007 Microchip Technology Inc.
PIC18F2682/2685/4682/4685
40-Lead Plastic Dual In-Line (P) – 600 mil Body [PDIP]
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
N
NOTE 1
E1
1 2 3
D
E
A2
A
L
c
b1
b
A1
e
eB
Units
INCHES
Dimension Limits
MIN
NOM
MAX
Number of Pins
Pitch
N
e
40
.100 BSC
Top to Seating Plane
Molded Package Thickness
Base to Seating Plane
Shoulder to Shoulder Width
Molded Package Width
Overall Length
A
–
–
–
–
–
–
–
–
–
–
–
–
.250
.195
–
A2
A1
E
.125
.015
.590
.485
1.980
.115
.008
.030
.014
–
.625
.580
2.095
.200
.015
.070
.023
.700
E1
D
Tip to Seating Plane
Lead Thickness
L
c
Upper Lead Width
b1
b
Lower Lead Width
Overall Row Spacing §
eB
Notes:
1. Pin 1 visual index feature may vary, but must be located within the hatched area.
2. § Significant Characteristic.
3. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" per side.
4. Dimensioning and tolerancing per ASME Y14.5M.
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
Microchip Technology Drawing C04-016B
© 2007 Microchip Technology Inc.
Preliminary
DS39761B-page 459
PIC18F2682/2685/4682/4685
44-Lead Plastic Thin Quad Flatpack (PT) – 10x10x1 mm Body, 2.00 mm Footprint [TQFP]
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
D
D1
E
e
E1
N
b
NOTE 1
1 2 3
NOTE 2
α
A
c
φ
A2
β
A1
L
L1
Units
MILLIMETERS
Dimension Limits
MIN
NOM
44
MAX
Number of Leads
Lead Pitch
N
e
0.80 BSC
–
Overall Height
A
–
1.20
1.05
0.15
0.75
Molded Package Thickness
Standoff
A2
A1
L
0.95
0.05
0.45
1.00
–
Foot Length
0.60
Footprint
L1
φ
1.00 REF
3.5°
Foot Angle
0°
7°
Overall Width
E
12.00 BSC
12.00 BSC
10.00 BSC
10.00 BSC
–
Overall Length
D
Molded Package Width
Molded Package Length
Lead Thickness
Lead Width
E1
D1
c
0.09
0.30
11°
0.20
0.45
13°
b
0.37
Mold Draft Angle Top
Mold Draft Angle Bottom
α
β
12°
11°
12°
13°
Notes:
1. Pin 1 visual index feature may vary, but must be located within the hatched area.
2. Chamfers at corners are optional; size may vary.
3. Dimensions D1 and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.25 mm per side.
4. Dimensioning and tolerancing per ASME Y14.5M.
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
REF: Reference Dimension, usually without tolerance, for information purposes only.
Microchip Technology Drawing C04-076B
DS39761B-page 460
Preliminary
© 2007 Microchip Technology Inc.
PIC18F2682/2685/4682/4685
44-Lead Plastic Quad Flat, No Lead Package (ML) – 8x8 mm Body [QFN]
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
D2
D
EXPOSED
PAD
e
b
K
E
E2
2
1
2
1
N
N
NOTE 1
L
TOP VIEW
BOTTOM VIEW
A
A3
A1
Units
MILLIMETERS
Dimension Limits
MIN
NOM
44
MAX
Number of Pins
N
e
Pitch
0.65 BSC
0.90
Overall Height
Standoff
A
0.80
0.00
1.00
0.05
A1
A3
E
0.02
Contact Thickness
Overall Width
0.20 REF
8.00 BSC
6.45
Exposed Pad Width
Overall Length
Exposed Pad Length
Contact Width
Contact Length
Contact-to-Exposed Pad
E2
D
6.30
6.80
8.00 BSC
6.45
D2
b
6.30
0.25
0.30
0.20
6.80
0.38
0.50
–
0.30
L
0.40
K
–
Notes:
1. Pin 1 visual index feature may vary, but must be located within the hatched area.
2. Package is saw singulated.
3. Dimensioning and tolerancing per ASME Y14.5M.
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
REF: Reference Dimension, usually without tolerance, for information purposes only.
Microchip Technology Drawing C04-103B
© 2007 Microchip Technology Inc.
Preliminary
DS39761B-page 461
PIC18F2682/2685/4682/4685
NOTES:
DS39761B-page 462
Preliminary
© 2007 Microchip Technology Inc.
PIC18F2682/2685/4682/4685
APPENDIX A: REVISION HISTORY
APPENDIX B: DEVICE
DIFFERENCES
Revision A (February 2006)
The differences between the devices listed in this data
sheet are shown in Table B-1.
Original data sheet for PIC18F2682/2685/4682/4685
devices.
Revision B (January 2007)
Major edits to Section 27.0 “Electrical Characteristics”.
Packaging diagrams have been updated and minor edits
to text have been made throughout document.
TABLE B-1:
DEVICE DIFFERENCES
Features
PIC18F2682
PIC18F2685
PIC18F4682
PIC18F4685
Program Memory (Bytes)
Program Memory (Instructions)
Interrupt Sources
80K
40960
27
96K
49152
27
80K
40960
28
96K
49152
28
I/O Ports
Ports A, B, C, (E) Ports A, B, C, (E) Ports A, B, C, D, E Ports A, B, C, D, E
Capture/Compare/PWM Modules
1
0
1
0
1
1
1
1
Enhanced Capture/Compare/
PWM Modules
Parallel Slave Port
No
No
Yes
Yes
Communications (PSP)
10-Bit Analog-to-Digital Module
Packages
8 input channels
8 input channels
11 input channels 11 input channels
28-pin PDIP
28-pin SOIC
28-pin PDIP
28-pin SOIC
40-pin PDIP
44-pin TQFP
44-pin QFN
40-pin PDIP
44-pin TQFP
44-pin QFN
© 2007 Microchip Technology Inc.
Preliminary
DS39761B-page 463
PIC18F2682/2685/4682/4685
APPENDIX C: CONVERSION
CONSIDERATIONS
APPENDIX D: MIGRATION FROM
BASELINE TO
ENHANCED DEVICES
This appendix discusses the considerations for
converting from previous versions of a device to the
ones listed in this data sheet. Typically, these changes
are due to the differences in the process technology
used. An example of this type of conversion is from a
PIC16C74A to a PIC16C74B.
This section discusses how to migrate from a Baseline
device (i.e., PIC16C5X) to an Enhanced MCU device
(i.e., PIC18FXXX).
The following are the list of modifications over the
PIC16C5X microcontroller family:
Not Applicable
Not Currently Available
DS39761B-page 464
Preliminary
© 2007 Microchip Technology Inc.
PIC18F2682/2685/4682/4685
APPENDIX E: MIGRATION FROM
APPENDIX F: MIGRATION FROM
HIGH-END TO
MID-RANGE TO
ENHANCED DEVICES
ENHANCED DEVICES
A detailed discussion of the differences between the
mid-range MCU devices (i.e., PIC16CXXX) and the
enhanced devices (i.e., PIC18FXXX) is provided in
AN716, “Migrating Designs from PIC16C74A/74B to
PIC18C442.” The changes discussed, while device
specific, are generally applicable to all mid-range to
enhanced device migrations.
A detailed discussion of the migration pathway and
differences between the high-end MCU devices (i.e.,
PIC17CXXX) and the enhanced devices (i.e.,
PIC18FXXX) is provided in AN726, “PIC17CXXX to
PIC18CXXX Migration.” This Application Note is
available as Literature Number DS00726.
This Application Note is available as Literature Number
DS00716.
© 2007 Microchip Technology Inc.
Preliminary
DS39761B-page 465
PIC18F2682/2685/4682/4685
NOTES:
DS39761B-page 466
Preliminary
© 2007 Microchip Technology Inc.
PIC18F2682/2685/4682/4685
INDEX
Comparator Analog Input Model .............................. 261
Comparator I/O Operating Modes ........................... 258
Comparator Output .................................................. 260
Comparator Voltage Reference ............................... 264
Comparator Voltage Reference Output
Buffer Example ................................................ 265
Compare Mode Operation ....................................... 167
Device Clock .............................................................. 28
Enhanced PWM ....................................................... 175
EUSART Receive .................................................... 238
EUSART Transmit ................................................... 236
External Power-on Reset Circuit
A
A/D ................................................................................... 247
Acquisition Requirements ........................................ 252
ADCON0 Register .................................................... 247
ADCON1 Register .................................................... 247
ADCON2 Register .................................................... 247
ADRESH Register ............................................ 247, 250
ADRESL Register .................................................... 247
Analog Port Pins, Configuring .................................. 254
Associated Registers ............................................... 256
Automatic Acquisition Time ...................................... 253
Configuring the Module ............................................ 251
Conversion Clock (TAD) ........................................... 253
Conversion Requirements ....................................... 452
Conversion Status (GO/DONE Bit) .......................... 250
Conversions ............................................................. 255
Converter Characteristics ........................................ 451
Converter Interrupt, Configuring .............................. 251
Operation in Power-Managed Modes ...................... 254
Special Event Trigger (ECCP1) ....................... 174, 256
Use of the ECCP1 Trigger ....................................... 256
Absolute Maximum Ratings ............................................. 417
AC (Timing) Characteristics ............................................. 433
Load Conditions for Device
Timing Specifications ....................................... 434
Parameter Symbology ............................................. 433
Temperature and Voltage Specifications ................. 434
Timing Conditions .................................................... 434
ACKSTAT ........................................................................ 217
ACKSTAT Status Flag ..................................................... 217
ADCON0 Register ............................................................ 247
GO/DONE Bit ........................................................... 250
ADCON1 Register ............................................................ 247
ADCON2 Register ............................................................ 247
ADDFSR .......................................................................... 406
ADDLW ............................................................................ 369
ADDULNK ........................................................................ 406
ADDWF ............................................................................ 369
ADDWFC ......................................................................... 370
ADRESH Register ............................................................ 247
ADRESL Register .................................................... 247, 250
Analog-to-Digital Converter. See A/D.
(Slow VDD Power-up) ........................................ 43
Fail-Safe Clock Monitor ........................................... 356
Generic I/O Port Operation ...................................... 129
High/Low-Voltage Detect with External Input .......... 268
Interrupt Logic .......................................................... 114
2
MSSP (I C Master Mode) ........................................ 211
2
MSSP (I C Mode) .................................................... 196
MSSP (SPI Mode) ................................................... 187
On-Chip Reset Circuit ................................................ 41
PIC18F2682/2685 ..................................................... 10
PIC18F4682/4685 ..................................................... 11
PLL (HS Mode) .......................................................... 25
PORTD and PORTE (Parallel Slave Port) ............... 144
PWM Operation (Simplified) .................................... 169
Reads from Flash Program Memory ......................... 99
Single Comparator ................................................... 259
Table Read Operation ............................................... 95
Table Write Operation ............................................... 96
Table Writes to Flash Program Memory .................. 101
Timer0 in 16-Bit Mode ............................................. 148
Timer0 in 8-Bit Mode ............................................... 148
Timer1 ..................................................................... 152
Timer1 (16-Bit Read/Write Mode) ............................ 152
Timer2 ..................................................................... 158
Timer3 ..................................................................... 160
Timer3 (16-Bit Read/Write Mode) ............................ 160
Watchdog Timer ...................................................... 353
BN .................................................................................... 372
BNC ................................................................................. 373
BNN ................................................................................. 373
BNOV .............................................................................. 374
BNZ ................................................................................. 374
BOR. See Brown-out Reset.
ANDLW ............................................................................ 370
ANDWF ............................................................................ 371
Assembler
BOV ................................................................................. 377
BRA ................................................................................. 375
BRG. See Baud Rate Generator.
MPASM Assembler .................................................. 414
B
Brown-out Reset (BOR) ..................................................... 44
Detecting ................................................................... 44
Disabling in Sleep Mode ............................................ 44
Software Enabled ...................................................... 44
BSF .................................................................................. 375
BTFSC ............................................................................. 376
BTFSS ............................................................................. 376
BTG ................................................................................. 377
BZ .................................................................................... 378
Baud Rate Generator ....................................................... 213
BC .................................................................................... 371
BCF .................................................................................. 372
BF .................................................................................... 217
BF Status Flag ................................................................. 217
Bit Timing Configuration Registers
BRGCON1 ............................................................... 338
BRGCON2 ............................................................... 338
BRGCON3 ............................................................... 338
Block Diagrams
C
A/D ........................................................................... 250
Analog Input Model .................................................. 251
Baud Rate Generator ............................................... 213
CAN Buffers and Protocol Engine ............................ 274
Capture Mode Operation ......................................... 166
C Compilers
MPLAB C18 ............................................................. 414
MPLAB C30 ............................................................. 414
CALL ................................................................................ 378
CALLW ............................................................................ 407
© 2007 Microchip Technology Inc.
Preliminary
DS39761B-page 467
PIC18F2682/2685/4682/4685
Capture (CCP1 Module) ...................................................165
Associated Registers ...............................................168
CAN Message Time-Stamp .....................................165
CCP1 Pin Configuration ...........................................165
CCPR1H:CCPR1L Registers ...................................165
Prescaler ..................................................................165
Software Interrupt ....................................................165
Timer1/Timer3 Mode Selection ................................165
Capture (ECCP1 Module) ................................................174
Capture/Compare/PWM (CCP1) ......................................163
Capture Mode. See Capture.
Comparator ...................................................................... 257
Analog Input Connection Considerations ................ 261
Associated Registers ............................................... 261
Configuration ........................................................... 258
Effects of a Reset .................................................... 260
Interrupts ................................................................. 260
Operation ................................................................. 259
Operation During Sleep ........................................... 260
Outputs .................................................................... 259
Reference ................................................................ 259
External Signal ................................................ 259
CCP1 Mode and Timer Resources ..........................164
CCPR1H or ECCPR1H Register .............................164
CCPR1L or ECCPR1L Register ...............................164
Compare Mode. See Compare.
Internal Signal .................................................. 259
Response Time ........................................................ 259
Comparator Specifications ............................................... 431
Comparator Voltage Reference ....................................... 263
Accuracy and Error .................................................. 264
Associated Registers ............................................... 265
Configuring .............................................................. 263
Connection Considerations ...................................... 264
Effects of a Reset .................................................... 264
Operation During Sleep ........................................... 264
Compare (CCP1 Module) ................................................ 167
Associated Registers ............................................... 168
CCP1 Pin Configuration ........................................... 167
CCPR1 Register ...................................................... 167
Software Interrupt .................................................... 167
Special Event Trigger .............................................. 167
Timer1/Timer3 Mode Selection ................................ 167
Compare (ECCP1 Module) .............................................. 174
Special Event Trigger .............................. 161, 174, 256
Configuration Bits ............................................................ 343
Configuration Mode ......................................................... 325
Configuration Register
Protection ................................................................ 362
Context Saving During Interrupts ..................................... 128
Conversion Considerations .............................................. 464
CPFSEQ .......................................................................... 380
CPFSGT .......................................................................... 381
CPFSLT ........................................................................... 381
Crystal Oscillator/Ceramic Resonators .............................. 23
Customer Change Notification Service ............................ 478
Customer Notification Service ......................................... 478
Customer Support ............................................................ 478
Interaction Between CCP1 and ECCP1
for Timer Resources ........................................164
Module Configuration ...............................................164
Clock Sources ....................................................................28
Effects of Power-Managed Modes .............................31
Selecting the 31 kHz Source ......................................29
Selection Using OSCCON Register ...........................29
CLRF ................................................................................379
CLRWDT ..........................................................................379
Code Examples
16 x 16 Signed Multiply Routine ..............................112
16 x 16 Unsigned Multiply Routine ..........................112
8 x 8 Signed Multiply Routine ..................................111
8 x 8 Unsigned Multiply Routine ..............................111
Changing Between Capture Prescalers ...................165
Changing to Configuration Mode .............................278
Computed GOTO Using an Offset Value ...................64
Data EEPROM Read ...............................................107
Data EEPROM Refresh Routine ..............................108
Data EEPROM Write ...............................................107
Erasing a Flash Program Memory Row ...................100
Fast Register Stack ....................................................64
How to Clear RAM (Bank 1) Using
Indirect Addressing ............................................88
Implementing a Real-Time Clock Using
a Timer1 Interrupt Service ...............................155
Initializing PORTA ....................................................129
Initializing PORTB ....................................................132
Initializing PORTC ....................................................135
Initializing PORTD ....................................................138
Initializing PORTE ....................................................141
Loading the SSPBUF (SSPSR) Register .................190
Reading a CAN Message ........................................294
Reading a Flash Program Memory Word ..................99
Saving STATUS, WREG and BSR
D
Data Addressing Modes .................................................... 88
Comparing Addressing Options with the
Extended Instruction Set Enabled ..................... 92
Direct ......................................................................... 88
Indexed Literal Offset ................................................ 91
Affected Instructions .......................................... 91
BSR ................................................................... 93
Mapping the Access Bank ................................. 93
Indirect ....................................................................... 88
Inherent and Literal .................................................... 88
Data EEPROM
Registers in RAM .............................................128
Transmitting a CAN Message Using
Banked Method ................................................286
Transmitting a CAN Message
Using WIN Bits .................................................287
WIN and ICODE Bits Usage in Interrupt Service
Routine to Access TX/RX Buffers ....................278
Writing to Flash Program Memory ................... 102–103
Code Protection ...............................................................343
COMF ...............................................................................380
Code Protection ....................................................... 362
DS39761B-page 468
Preliminary
© 2007 Microchip Technology Inc.
PIC18F2682/2685/4682/4685
Data EEPROM Memory ................................................... 105
CAN Message Transmission ................................... 328
Aborting ........................................................... 328
Initiating ........................................................... 328
Priority ............................................................. 329
CAN Modes of Operation ........................................ 325
CAN Registers ......................................................... 275
Baud Rate ....................................................... 312
Control and Status ........................................... 275
Controller Map ................................................. 320
Dedicated Receive Buffers .............................. 288
Dedicated Transmit Buffers ............................. 282
I/O Control ....................................................... 315
Interrupt ........................................................... 316
Configuration Mode ................................................. 325
Disable Mode ........................................................... 325
Error Detection ........................................................ 339
Acknowledge ................................................... 339
Bit .................................................................... 339
CRC ................................................................. 339
Error States ..................................................... 339
Form ................................................................ 339
Modes and Counters ....................................... 339
Stuff Bit ............................................................ 339
Error Modes State (diagram) ................................... 340
Error Recognition Mode ........................................... 326
Filter-Mask Truth (table) .......................................... 331
Functional Modes .................................................... 326
Mode 0 (Legacy Mode) .................................... 326
Mode 1 (Enhanced Legacy Mode) .................. 326
Mode 2 (Enhanced FIFO Mode) ...................... 327
Information Processing Time (IPT) .......................... 336
Lengthening a Bit Period ......................................... 337
Listen Only Mode ..................................................... 326
Loopback Mode ....................................................... 326
Message Acceptance Filters and Masks ......... 303, 331
Message Acceptance Mask and
Associated Registers ............................................... 109
EEADR and EEADRH Registers ............................. 105
EECON1 and EECON2 Registers ........................... 105
Operation During Code-Protect ............................... 108
Protection Against Spurious Write ........................... 108
Reading .................................................................... 107
Use ........................................................................... 108
Write Verify .............................................................. 107
Writing ...................................................................... 107
Data Memory ..................................................................... 67
Access Bank .............................................................. 69
Bank Select Register (BSR) ....................................... 67
Extended Instruction Set ............................................ 91
General Purpose Register File ................................... 69
Map for PIC18F268X/468X ........................................ 68
Special Function Registers ........................................ 70
DAW ................................................................................. 382
DC and AC Characteristics .............................................. 453
DC Characteristics ........................................................... 428
Power-Down and Supply Current ............................ 420
Supply Voltage ......................................................... 419
DCFSNZ .......................................................................... 383
DECF ............................................................................... 382
DECFSZ ........................................................................... 383
Development Support ...................................................... 413
Device Differences ........................................................... 463
Device Overview .................................................................. 7
Features (table) ............................................................ 9
New Core Features ...................................................... 7
Device Reset Timers .......................................................... 45
Oscillator Start-up Timer (OST) ................................. 45
PLL Lock Time-out ..................................................... 45
Power-up Timer (PWRT) ........................................... 45
Direct Addressing ............................................................... 89
Disable Mode ................................................................... 325
Filter Operation ................................................ 332
Message Reception ................................................. 330
Enhanced FIFO Mode ..................................... 331
Priority ............................................................. 330
Time-Stamping ................................................ 331
Normal Mode ........................................................... 325
Oscillator Tolerance ................................................. 338
Overview .................................................................. 273
Phase Buffer Segments ........................................... 336
Programmable TX/RX and
E
ECAN Technology ........................................................... 273
Baud Rate Setting .................................................... 333
Bit Time Partitioning ................................................. 333
Bit Timing Configuration Registers .......................... 338
Calculating TQ, Nominal Bit Rate and
Nominal Bit Time ............................................. 336
CAN Interrupts ......................................................... 340
Acknowledge ................................................... 342
Bus Activity Wake-up ....................................... 342
Bus-Off ............................................................. 342
Code Bits ......................................................... 341
Error ................................................................. 342
Message Error ................................................. 341
Receive ............................................................ 341
Receiver Bus Passive ...................................... 342
Receiver Overflow ........................................... 342
Receiver Warning ............................................ 342
Transmit ........................................................... 341
Transmitter Bus Passive .................................. 342
Transmitter Warning ........................................ 342
CAN Message Buffers ............................................. 327
Dedicated Receive ........................................... 327
Dedicated Transmit .......................................... 327
Programmable Auto-RTR ................................ 328
Programmable Transmit/Receive .................... 327
Auto-RTR Buffers ............................................ 295
Programming Time Segments ................................. 338
Propagation Segment .............................................. 336
Sample Point ........................................................... 336
Shortening a Bit Period ............................................ 338
Synchronization ....................................................... 337
Hard ................................................................. 337
Resynchronization ........................................... 337
Rules ............................................................... 337
Synchronization Segment ........................................ 336
Time Quanta ............................................................ 336
Values for ICODE (table) ......................................... 341
Effect on Standard PIC Instructions ................................. 410
Electrical Characteristics ................................................. 417
© 2007 Microchip Technology Inc.
Preliminary
DS39761B-page 469
PIC18F2682/2685/4682/4685
Enhanced Capture/Compare/PWM (ECCP1) ..................173
Associated Registers ...............................................186
Capture and Compare Modes ..................................174
Capture Mode. See Capture (ECCP1 Module).
Outputs and Configuration .......................................174
Pin Configurations for ECCP1 .................................174
PWM Mode. See PWM (ECCP1 Module).
Standard PWM Mode ...............................................174
Timer Resources ......................................................174
Enhanced Universal Synchronous Receiver
Fast Register Stack ........................................................... 64
Firmware Instructions ...................................................... 363
Flash Program Memory ..................................................... 95
Associated Registers ............................................... 103
Control Registers ....................................................... 96
EECON1 ............................................................ 96
EECON2 ............................................................ 96
TABLAT ............................................................. 96
TABLAT (Table Latch) Register ........................ 98
TBLPTR ............................................................. 96
TBLPTR (Table Pointer) Register ...................... 98
Erase Sequence ...................................................... 100
Erasing .................................................................... 100
Operation During Code-Protect ............................... 103
Reading ..................................................................... 99
Table Pointer
Boundaries Based on Operation ....................... 98
Table Pointer Boundaries .......................................... 98
Table Pointer Operations (table) ................................ 98
Table Reads and Table Writes .................................. 95
Write Sequence ....................................................... 101
Write Verify .............................................................. 103
Writing ..................................................................... 101
Protection Against Spurious Writes ................. 103
Unexpected Termination ................................. 103
FSCM. See Fail-Safe Clock Monitor.
Transmitter (EUSART). See EUSART.
Equations
A/D Acquisition Time ................................................252
A/D Minimum Charging Time ...................................252
Calculating the Minimum Required
A/D Acquisition Time ........................................252
Errata ...................................................................................5
Error Recognition Mode ...................................................325
EUSART
Asynchronous Mode ................................................236
Associated Registers, Receive ........................239
Associated Registers, Transmit .......................237
Auto-Wake-up on Sync Break
Character .................................................240
Break Character Sequence ..............................241
Receiver ...........................................................238
Receiving a Break Character ...........................241
Setting Up 9-Bit Mode with
G
GOTO .............................................................................. 384
Address Detect ........................................238
Transmitter .......................................................236
Baud Rate Generator (BRG) ....................................231
Associated Registers .......................................231
Auto-Baud Rate Detect ....................................234
Baud Rate Error, Calculating ...........................231
Baud Rates, Asynchronous Modes ..................232
High Baud Rate Select (BRGH Bit) ..................231
Operation in Power-Managed Modes ..............231
Sampling ..........................................................231
Synchronous Master Mode ......................................242
Associated Registers, Receive ........................244
Associated Registers, Transmit .......................243
Reception .........................................................244
Transmission ....................................................242
Synchronous Slave Mode ........................................245
Associated Registers, Receive ........................246
Associated Registers, Transmit .......................245
Reception .........................................................246
Transmission ....................................................245
Extended Instruction Set
ADDFSR ..................................................................406
ADDULNK ................................................................406
CALLW .....................................................................407
MOVSF ....................................................................407
MOVSS ....................................................................408
PUSHL .....................................................................408
SUBFSR ..................................................................409
SUBULNK ................................................................409
External Clock Input ...........................................................24
H
Hardware Multiplier .......................................................... 111
Introduction .............................................................. 111
Operation ................................................................. 111
Performance Comparison ........................................ 111
High/Low-Voltage Detect ................................................. 267
Associated Registers ............................................... 271
Characteristics ......................................................... 432
Current Consumption ............................................... 269
Effects of a Reset .................................................... 271
Operation ................................................................. 268
Operation During Sleep ........................................... 271
Setup ....................................................................... 269
Start-up Time ........................................................... 269
Typical Application ................................................... 270
HLVD. See High/Low-Voltage Detect.
I
I/O Ports ........................................................................... 129
2
I C Mode (MSSP)
Acknowledge Sequence Timing .............................. 220
Baud Rate Generator .............................................. 213
Bus Collision
During a Repeated Start Condition .................. 224
During a Start Condition .................................. 222
During a Stop Condition .................................. 225
Clock Arbitration ...................................................... 214
Clock Stretching ....................................................... 206
10-Bit Slave Receive Mode (SEN = 1) ............ 206
10-Bit Slave Transmit Mode ............................ 206
7-Bit Slave Receive Mode (SEN = 1) .............. 206
7-Bit Slave Transmit Mode .............................. 206
Clock Synchronization and the CKP Bit ................... 207
Effect of a Reset ...................................................... 221
General Call Address Support ................................. 210
F
Fail-Safe Clock Monitor ............................................ 343, 356
Exiting Operation .....................................................356
Interrupts in Power-Managed Modes .......................357
POR or Wake-up from Sleep ...................................357
Watchdog Timer (WDT) ...........................................356
2
I C Clock Rate w/BRG ............................................. 213
DS39761B-page 470
Preliminary
© 2007 Microchip Technology Inc.
PIC18F2682/2685/4682/4685
Master Mode ............................................................ 211
DECF ....................................................................... 382
DECFSZ .................................................................. 383
Extended Instructions .............................................. 405
and Using MPLAB Tools ................................. 412
Considerations when Enabling ........................ 410
Syntax ............................................................. 405
General Format ....................................................... 365
GOTO ...................................................................... 384
INCF ........................................................................ 384
INCFSZ .................................................................... 385
INFSNZ .................................................................... 385
IORLW ..................................................................... 386
IORWF ..................................................................... 386
LFSR ....................................................................... 387
MOVF ...................................................................... 387
MOVFF .................................................................... 388
MOVLB .................................................................... 388
MOVLW ................................................................... 389
MOVWF ................................................................... 389
MULLW .................................................................... 390
MULWF ................................................................... 390
NEGF ....................................................................... 391
NOP ......................................................................... 391
Opcode Field Descriptions ...................................... 364
POP ......................................................................... 392
PUSH ....................................................................... 392
RCALL ..................................................................... 393
RESET ..................................................................... 393
RETFIE .................................................................... 394
RETLW .................................................................... 394
RETURN .................................................................. 395
RLCF ....................................................................... 395
RLNCF ..................................................................... 396
RRCF ....................................................................... 396
RRNCF .................................................................... 397
SETF ....................................................................... 397
SETF (Indexed Literal Offset Mode) ........................ 411
SLEEP ..................................................................... 398
Standard Instructions ............................................... 363
SUBFWB ................................................................. 398
SUBLW .................................................................... 399
SUBWF .................................................................... 399
SUBWFB ................................................................. 400
SWAPF .................................................................... 400
TBLRD ..................................................................... 401
TBLWT .................................................................... 402
TSTFSZ ................................................................... 403
XORLW ................................................................... 403
XORWF ................................................................... 404
Summary Table ....................................................... 366
Operation ......................................................... 212
Reception ......................................................... 217
Repeated Start Condition Timing ..................... 216
Start Condition ................................................. 215
Transmission ................................................... 217
Transmit Sequence .......................................... 212
Multi-Master Communication, Bus Collision
and Arbitration ................................................. 221
Multi-Master Mode ................................................... 221
Operation ................................................................. 200
Read/Write Bit Information (R/W Bit) ............... 200, 201
Registers .................................................................. 196
Serial Clock (RC3/SCK/SCL) ................................... 201
Slave Mode .............................................................. 200
Addressing ....................................................... 200
Reception ......................................................... 201
Transmission ................................................... 201
Sleep Operation ....................................................... 221
Stop Condition Timing .............................................. 220
ID Locations ............................................................. 343, 362
INCF ................................................................................. 384
INCFSZ ............................................................................ 385
In-Circuit Debugger .......................................................... 362
In-Circuit Serial Programming (ICSP) ...................... 343, 362
Indexed Literal Offset Addressing Mode .......................... 410
and Standard PIC18 Instructions ............................. 410
Indirect Addressing ............................................................ 89
INFSNZ ............................................................................ 385
Initialization Conditions for All Registers ...................... 49–60
Instruction Cycle ................................................................ 65
Clocking Scheme ....................................................... 65
Flow/Pipelining ........................................................... 65
Instruction Set .................................................................. 363
ADDLW .................................................................... 369
ADDWF .................................................................... 369
ADDWF (Indexed Literal Offset Mode) .................... 411
ADDWFC ................................................................. 370
ANDLW .................................................................... 370
ANDWF .................................................................... 371
BC ............................................................................ 371
BCF .......................................................................... 372
BN ............................................................................ 372
BNC ......................................................................... 373
BNN ......................................................................... 373
BNOV ....................................................................... 374
BNZ .......................................................................... 374
BOV ......................................................................... 377
BRA .......................................................................... 375
BSF .......................................................................... 375
BSF (Indexed Literal Offset Mode) .......................... 411
BTFSC ..................................................................... 376
BTFSS ..................................................................... 376
BTG .......................................................................... 377
BZ ............................................................................ 378
CALL ........................................................................ 378
CLRF ........................................................................ 379
CLRWDT .................................................................. 379
COMF ...................................................................... 380
CPFSEQ .................................................................. 380
CPFSGT .................................................................. 381
CPFSLT ................................................................... 381
DAW ......................................................................... 382
DCFSNZ .................................................................. 383
INTCON Register
RBIF Bit ................................................................... 132
INTCON Registers ........................................................... 115
2
Inter-Integrated Circuit. See I C.
Internal Oscillator Block ..................................................... 26
Adjustment ................................................................. 26
Frequency Drift .......................................................... 26
INTIO Modes ............................................................. 26
INTOSC Output Frequency ....................................... 26
OSCTUNE Register ................................................... 26
Internal RC Oscillator
Use with WDT .......................................................... 353
Internet Address .............................................................. 478
© 2007 Microchip Technology Inc.
Preliminary
DS39761B-page 471
PIC18F2682/2685/4682/4685
Interrupt Sources ..............................................................343
N
A/D Conversion Complete .......................................251
NEGF ............................................................................... 391
NOP ................................................................................. 391
Normal Operation Mode .................................................. 325
Capture Complete (CCP1) .......................................165
Compare Complete (CCP1) .....................................167
ECAN Module ..........................................................340
Interrupt-on-Change (RB7:RB4) ..............................132
INTx Pin ...................................................................128
PORTB, Interrupt-on-Change ..................................128
TMR0 .......................................................................128
TMR0 Overflow ........................................................149
TMR2 to PR2 Match (PWM) ....................................169
TMR3 Overflow ........................................................161
Interrupts ..........................................................................113
Interrupts, Flag Bits
Interrupt-on-Change (RB7:RB4) Flag
(RBIF Bit) .........................................................132
INTOSC, INTRC. See Internal Oscillator Block.
IORLW .............................................................................386
IORWF .............................................................................386
IPR Registers ...................................................................124
O
Oscillator Configuration ..................................................... 23
EC .............................................................................. 23
ECIO .......................................................................... 23
HS .............................................................................. 23
HSPLL ....................................................................... 23
Internal Oscillator Block ............................................. 26
INTIO1 ....................................................................... 23
INTIO2 ....................................................................... 23
LP .............................................................................. 23
RC ............................................................................. 23
RCIO .......................................................................... 23
XT .............................................................................. 23
Oscillator Selection .......................................................... 343
Oscillator Start-up Timer (OST) ................................... 31, 45
Oscillator Switching ........................................................... 28
Oscillator Transitions ......................................................... 29
Oscillator, Timer1 ............................................................. 161
Oscillator, Timer3 ..................................................... 151, 159
L
LFSR ................................................................................387
Listen Only Mode .............................................................325
Loopback Mode ................................................................325
Low-Voltage ICSP Programming. See
P
Single-Supply ICSP Programming.
Packaging Information ..................................................... 455
Details ...................................................................... 457
Marking .................................................................... 455
Parallel Slave Port (PSP) ................................................. 144
Associated Registers ............................................... 145
CS (Chip Select) ...................................................... 144
PORTD .................................................................... 144
RD (Read Input) ....................................................... 144
Select (PSPMODE Bit) .................................... 138, 144
WR (Write Input) ...................................................... 144
PICSTART Plus Development Programmer .................... 416
PIE Registers ................................................................... 121
Pin Functions
M
Master Clear Reset (MCLR) ...............................................43
Master Synchronous Serial Port (MSSP). See MSSP.
Memory Organization .........................................................61
Data Memory .............................................................67
Program Memory .......................................................61
Memory Programming Requirements ..............................430
Microchip Internet Web Site .............................................478
Migration from Baseline to Enhanced Devices ................464
Migration from High-End to Enhanced Devices ...............465
Migration from Mid-Range to Enhanced Devices .............465
MOVF ...............................................................................387
MOVFF .............................................................................388
MOVLB .............................................................................388
MOVLW ............................................................................389
MOVSF ............................................................................407
MOVSS ............................................................................408
MOVWF ...........................................................................389
MPLAB ASM30 Assembler, Linker, Librarian ..................414
MPLAB ICD 2 In-Circuit Debugger ...................................415
MPLAB ICE 2000 High-Performance
MCLR/VPP/RE3 ................................................... 12, 16
OSC1/CLKI/RA7 .................................................. 12, 16
OSC2/CLKO/RA6 ................................................ 12, 16
RA0/AN0 .................................................................... 13
RA0/AN0/CVREF ........................................................ 17
RA1/AN1 .............................................................. 13, 17
RA2/AN2/VREF- ................................................... 13, 17
RA3/AN3/VREF+ .................................................. 13, 17
RA4/T0CKI .......................................................... 13, 17
RA5/AN4/SS/HLVDIN .......................................... 13, 17
RB0/INT0/AN10 ......................................................... 14
RB0/INT0/FLT0/AN10 ................................................ 18
RB1/INT1/AN8 ..................................................... 14, 18
RB2/INT2/CANTX ................................................ 14, 18
RB3/CANRX ........................................................ 14, 18
RB4/KBI0/AN9 ..................................................... 14, 18
RB5/KBI1/PGM .................................................... 14, 18
RB6/KBI2/PGC .................................................... 14, 18
RB7/KBI3/PGD .................................................... 14, 18
RC0/T1OSO/T13CKI ........................................... 15, 19
RC1/T1OSI .......................................................... 15, 19
RC2/CCP1 ........................................................... 15, 19
RC3/SCK/SCL ..................................................... 15, 19
RC4/SDI/SDA ...................................................... 15, 19
RC5/SDO ............................................................. 15, 19
Universal In-Circuit Emulator ...................................415
MPLAB Integrated Development
Environment Software ..............................................413
MPLAB PM3 Device Programmer ....................................415
MPLAB REAL ICE In-Circuit Emulator System ................415
MPLINK Object Linker/MPLIB Object Librarian ...............414
MSSP
ACK Pulse ........................................................ 200, 201
Control Registers (general) ......................................187
I C Mode. See I C Mode.
2
2
Module Overview .....................................................187
SPI Master/Slave Connection ..................................191
SSPBUF ...................................................................192
SSPSR .....................................................................192
MULLW ............................................................................390
MULWF ............................................................................390
DS39761B-page 472
Preliminary
© 2007 Microchip Technology Inc.
PIC18F2682/2685/4682/4685
RC6/TX/CK .......................................................... 15, 19
Power-Managed Modes ..................................................... 33
Clock Sources ........................................................... 33
Clock Transitions and Status Indicators .................... 34
Entering ..................................................................... 33
Exiting Idle and Sleep Modes .................................... 39
By Interrupt ........................................................ 39
By Reset ............................................................ 39
By WDT Time-out .............................................. 39
Without an Oscillator Start-up Delay ................. 40
Idle Modes ................................................................. 37
PRI_IDLE .......................................................... 38
RC_IDLE ........................................................... 39
SEC_IDLE ......................................................... 38
Multiple Sleep Commands ......................................... 34
Run Modes ................................................................ 34
PRI_RUN ........................................................... 34
RC_RUN ............................................................ 35
SEC_RUN ......................................................... 34
Selecting .................................................................... 33
Sleep Mode ............................................................... 37
Summary (table) ........................................................ 33
Power-on Reset (POR) ...................................................... 43
Power-up Timer (PWRT) ........................................... 45
Time-out Sequence ................................................... 45
Power-up Delays ............................................................... 31
Power-up Timer (PWRT) ............................................. 31, 45
Prescaler
RC7/RX/DT .......................................................... 15, 19
RD0/PSP0/C1IN+ ...................................................... 20
RD1/PSP1/C1IN- ....................................................... 20
RD2/PSP2/C2IN+ ...................................................... 20
RD3/PSP3/C2IN- ....................................................... 20
RD4/PSP4/ECCP1/P1A ............................................. 20
RD5/PSP5/P1B .......................................................... 20
RD6/PSP6/P1C .......................................................... 20
RD7/PSP7/P1D .......................................................... 20
RE0/RD/AN5 .............................................................. 21
RE1/WR/AN6/C1OUT ................................................ 21
RE2/CS/AN7/C2OUT ................................................. 21
VDD ...................................................................... 15, 21
VSS ....................................................................... 15, 21
Pinout I/O Descriptions
PIC18F2682/2685 ...................................................... 12
PIC18F4682/4685 ...................................................... 16
PIR Registers ................................................................... 118
PLL Frequency Multiplier ................................................... 25
HSPLL Oscillator Mode .............................................. 25
INTOSC Modes .......................................................... 26
Use with INTOSC ....................................................... 25
PLL Lock Time-out ............................................................. 45
POP ................................................................................. 392
POR. See Power-on Reset.
PORTA
Associated Registers ............................................... 131
I/O Summary ............................................................ 130
LATA Register .......................................................... 129
PORTA Register ...................................................... 129
TRISA Register ........................................................ 129
PORTB
Timer2 ..................................................................... 176
Prescaler, Timer0 ............................................................ 149
Assignment (PSA Bit) .............................................. 149
Rate Select (T0PS2:T0PS0 Bits) ............................. 149
Switching Between Timer0 and WDT ...................... 149
Prescaler, Timer2 ............................................................ 170
PRI_IDLE Mode ................................................................. 38
PRI_RUN Mode ................................................................. 34
Program Counter ............................................................... 62
PCL, PCH and PCU Registers .................................. 62
PCLATH and PCLATU Registers .............................. 62
Program Memory
Code Protection ....................................................... 359
Extended Instruction Set ........................................... 91
Instructions ................................................................ 66
Two-Word .......................................................... 66
Interrupt Vector .......................................................... 61
Look-up Tables .......................................................... 64
Map and Stack (diagram) .......................................... 61
Reset Vector .............................................................. 61
Program Verification and Code Protection ...................... 358
Associated Registers ............................................... 359
Programming, Device Instructions ................................... 363
PSP. See Parallel Slave Port.
Associated Registers ............................................... 134
I/O Summary ............................................................ 133
LATB Register .......................................................... 132
PORTB Register ...................................................... 132
RB7:RB4 Interrupt-on-Change Flag
(RBIF Bit) ......................................................... 132
TRISB Register ........................................................ 132
PORTC
Associated Registers ............................................... 137
I/O Summary ............................................................ 136
LATC Register ......................................................... 135
PORTC Register ...................................................... 135
RC3/SCK/SCL Pin ................................................... 201
TRISC Register ........................................................ 135
PORTD
Associated Registers ............................................... 140
I/O Summary ............................................................ 139
LATD Register ......................................................... 138
Parallel Slave Port (PSP) Function .......................... 138
PORTD Register ...................................................... 138
TRISD Register ........................................................ 138
PORTE
Associated Registers ............................................... 143
I/O Summary ............................................................ 143
LATE Register .......................................................... 141
PORTE Register ...................................................... 141
PSP Mode Select (PSPMODE Bit) .......................... 138
TRISE Register ........................................................ 141
Postscaler, WDT
Pulse-Width Modulation. See PWM (CCP1/ECCP1 Modules).
PUSH ............................................................................... 392
PUSH and POP Instructions .............................................. 63
PUSHL ............................................................................. 408
PWM (CCP1 Module)
Associated Registers ............................................... 171
CCPR1H:CCPR1L Registers .................................. 169
Duty Cycle ............................................................... 169
Example Frequencies/Resolutions .......................... 170
Period ...................................................................... 169
Setup for PWM Operation ....................................... 170
TMR2 to PR2 Match ................................................ 169
Assignment (PSA Bit) .............................................. 149
Rate Select (T0PS2:T0PS0 Bits) ............................. 149
Switching Between Timer0 and WDT ...................... 149
© 2007 Microchip Technology Inc.
Preliminary
DS39761B-page 473
PIC18F2682/2685/4682/4685
PWM (ECCP1 Module) ....................................................175
Auto-Shutdown ........................................................170
Direction Change in Full-Bridge
BnSIDL (TX/RX Buffer n Standard Identifier,
Low Byte in Receive Mode) ............................. 298
BRGCON1 (Baud Rate Control 1) ........................... 312
BRGCON2 (Baud Rate Control 2) ........................... 313
BRGCON3 (Baud Rate Control 3) ........................... 314
BSEL0 (Buffer Select 0) ........................................... 302
CCP1CON (Capture/Compare/PWM Control) ......... 163
CIOCON (CAN I/O Control) ..................................... 315
CMCON (Comparator Control) ................................ 257
COMSTAT (CAN Communication Status) ............... 281
CONFIG1H (Configuration 1 High) .......................... 344
CONFIG2H (Configuration 2 High) .......................... 346
CONFIG2L (Configuration 2 Low) ........................... 345
CONFIG3H (Configuration 3 High) .......................... 347
CONFIG4L (Configuration 4 Low) ........................... 347
CONFIG5H (Configuration 5 High) .......................... 348
CONFIG5L (Configuration 5 Low) ........................... 348
CONFIG6H (Configuration 6 High) .......................... 350
CONFIG6L (Configuration 6 Low) ........................... 349
CONFIG7H (Configuration 7 High) .......................... 351
CONFIG7L (Configuration 7 Low) ........................... 351
CVRCON (Comparator Voltage
Output Mode ....................................................180
Duty Cycle ................................................................176
ECCPR1H:ECCPR1L Registers ..............................175
Effects of a Reset .....................................................185
Enhanced Mode .......................................................175
Enhanced PWM Auto-Shutdown .............................182
Example Frequencies/Resolutions ..........................176
Full-Bridge Application Example ..............................180
Full-Bridge Mode ......................................................179
Half-Bridge Mode .....................................................178
Half-Bridge Output Mode Applications
Example ...........................................................178
Output Configurations ..............................................176
Output Relationships (Active-High) ..........................177
Output Relationships (Active-Low) ...........................177
Period .......................................................................175
Programmable Dead-Band Delay ............................182
Setup ........................................................................185
Start-up Considerations ...........................................184
TMR2 to PR2 Match ................................................175
Reference Control) .......................................... 263
DEVID1 (Device ID 1) .............................................. 352
DEVID2 (Device ID 2) .............................................. 352
ECANCON (Enhanced CAN Control) ...................... 280
ECCP1AS (Enhanced Capture/Compare/PWM
Auto-Shutdown Configuration) ........................ 183
ECCP1CON (Enhanced
Q
Q Clock .................................................................... 170, 176
R
RAM. See Data Memory.
RC Oscillator ......................................................................25
RCIO Oscillator Mode ................................................25
RC_IDLE Mode ..................................................................39
RC_RUN Mode ..................................................................35
RCALL ..............................................................................393
RCON Register
Bit Status During Initialization ....................................48
Reader Response ............................................................479
Register File Summary ................................................. 76–86
Registers
Capture/Compare/PWM Control) .................... 173
ECCP1DEL (PWM Dead-Band Delay) .................... 182
EECON1 (Data EEPROM Control 1) ................. 97, 106
HLVDCON (High/Low-Voltage
Detect Control) ................................................ 267
INTCON (Interrupt Control) ...................................... 115
INTCON2 (Interrupt Control 2) ................................. 116
INTCON3 (Interrupt Control 3) ................................. 117
IPR1 (Peripheral Interrupt Priority 1) ....................... 124
IPR2 (Peripheral Interrupt Priority 2) ....................... 125
IPR3 (Peripheral Interrupt Priority 3) ............... 126, 318
MSEL0 (Mask Select 0) ........................................... 308
MSEL1 (Mask Select 1) ........................................... 309
MSEL2 (Mask Select 2) ........................................... 310
MSEL3 (Mask Select 3) ........................................... 311
OSCCON (Oscillator Control) .................................... 30
OSCTUNE (Oscillator Tuning) ................................... 27
PIE1 (Peripheral Interrupt Enable 1) ........................ 121
PIE2 (Peripheral Interrupt Enable 2) ........................ 122
PIE3 (Peripheral Interrupt Enable 3) ................ 123, 317
PIR1 (Peripheral Interrupt
Request (Flag) 1) ............................................. 118
PIR2 (Peripheral Interrupt
Request (Flag) 2) ............................................. 119
PIR3 (Peripheral Interrupt
Request (Flag) 3) ..................................... 120, 316
RCON (Reset Control) ....................................... 42, 127
RCSTA (Receive Status and Control) ..................... 229
RXB0CON (Receive Buffer 0 Control) ..................... 288
RXB1CON (Receive Buffer 1 Control) ..................... 290
RXBnDLC (Receive Buffer n
ADCON0 (A/D Control 0) .........................................247
ADCON1 (A/D Control 1) .........................................248
ADCON2 (A/D Control 2) .........................................249
BAUDCON (Baud Rate Control) ..............................230
BIE0 (Buffer Interrupt Enable 0) ...............................319
BnCON (TX/RX Buffer n Control,
Receive Mode) .................................................295
BnCON (TX/RX Buffer n Control,
Transmit Mode) ................................................296
BnDLC (TX/RX Buffer n Data Length Code
in Receive Mode) .............................................301
BnDLC (TX/RX Buffer n Data Length Code
in Transmit Mode) ............................................302
BnDm (TX/RX Buffer n Data Field Byte m
in Receive Mode) .............................................300
BnDm (TX/RX Buffer n Data Field Byte m
in Transmit Mode) ............................................300
BnEIDH (TX/RX Buffer n Extended Identifier,
High Byte in Receive Mode) ............................299
BnEIDH (TX/RX Buffer n Extended Identifier,
High Byte in Transmit Mode) ...........................299
BnEIDL (TX/RX Buffer n Extended Identifier,
Low Byte in Receive Mode) ..................... 299, 300
BnSIDH (TX/RX Buffer n Standard Identifier,
High Byte in Receive Mode) ............................297
BnSIDH (TX/RX Buffer n Standard Identifier,
High Byte in Transmit Mode) ...........................297
Data Length Code) .......................................... 293
RXBnDm (Receive Buffer n
Data Field Byte m) ........................................... 293
RXBnEIDH (Receive Buffer n
Extended Identifier, High Byte) ........................ 292
DS39761B-page 474
Preliminary
© 2007 Microchip Technology Inc.
PIC18F2682/2685/4682/4685
RXBnEIDL (Receive Buffer n
Return Address Stack ........................................................ 62
Extended Identifier, Low Byte) ......................... 292
RXBnSIDH (Receive Buffer n
Standard Identifier, High Byte) ......................... 291
RXBnSIDL (Receive Buffer n
Standard Identifier, Low Byte) ......................... 292
RXERRCNT (Receive Error Count) ......................... 294
RXFBCONn (Receive Filter Buffer Control n) .......... 307
RXFCONn (Receive Filter Control n) ....................... 306
RXFnEIDH (Receive Acceptance Filter n
Associated Registers ................................................. 62
Return Stack Pointer (STKPTR) ........................................ 63
Revision History ............................................................... 463
RLCF ............................................................................... 395
RLNCF ............................................................................. 396
RRCF ............................................................................... 396
RRNCF ............................................................................ 397
S
SCK ................................................................................. 187
SDI ................................................................................... 187
SDO ................................................................................. 187
SEC_IDLE Mode ............................................................... 38
SEC_RUN Mode ................................................................ 34
Serial Clock, SCK ............................................................ 187
Serial Data In (SDI) .......................................................... 187
Serial Data Out (SDO) ..................................................... 187
Serial Peripheral Interface. See SPI Mode.
SETF ............................................................................... 397
Slave Select (SS) ............................................................. 187
SLEEP ............................................................................. 398
Sleep
Extended Identifier, High Byte) ........................ 304
RXFnEIDL (Receive Acceptance Filter n
Extended Identifier, Low Byte) ......................... 304
RXFnSIDH (Receive Acceptance Filter n
Standard Identifier Filter, High Byte) ................ 303
RXFnSIDL (Receive Acceptance Filter n
Standard Identifier Filter, Low Byte) ................ 303
RXMnEIDH (Receive Acceptance Mask n
Extended Identifier Mask, High Byte) .............. 305
RXMnEIDL (Receive Acceptance Mask n
Extended Identifier Mask, Low Byte) ............... 305
RXMnSIDH (Receive Acceptance Mask n
Standard Identifier Mask, High Byte) ............... 304
RXMnSIDL (Receive Acceptance Mask n
Standard Identifier Mask, Low Byte) ................ 305
SDFLC (Standard Data Bytes Filter
OSC1 and OSC2 Pin States ...................................... 31
Software Simulator (MPLAB SIM) ................................... 414
Special Event Trigger. See Compare
(CCP1/ECCP1 Modules).
Special Event Trigger. See Compare (ECCP1 Module).
Special Function Registers
Length Count) .................................................. 306
SSPCON1 (MSSP Control 1, I C Mode) ................. 198
2
SSPCON1 (MSSP Control 1, SPI Mode) ................. 189
2
Map ...................................................................... 70–75
SPI Mode (MSSP) ........................................................... 187
Associated Registers ............................................... 195
Bus Mode Compatibility ........................................... 195
Effects of a Reset .................................................... 195
Enabling SPI I/O ...................................................... 191
Master Mode ............................................................ 192
Master/Slave Connection ........................................ 191
Operation ................................................................. 190
Operation in Power-Managed Modes ...................... 195
Serial Clock ............................................................. 187
Serial Data In ........................................................... 187
Serial Data Out ........................................................ 187
Slave Mode .............................................................. 193
Slave Select ............................................................. 187
Slave Select Synchronization .................................. 193
SPI Clock ................................................................. 192
Typical Connection .................................................. 191
SS .................................................................................... 187
SSPOV ............................................................................ 217
SSPOV Status Flag ......................................................... 217
SSPSTAT Register
R/W Bit ............................................................ 200, 201
Stack Full/Underflow Resets .............................................. 64
Status Register .................................................................. 87
SUBFSR .......................................................................... 409
SUBFWB ......................................................................... 398
SUBLW ............................................................................ 399
SUBULNK ........................................................................ 409
SUBWF ............................................................................ 399
SUBWFB ......................................................................... 400
SWAPF ............................................................................ 400
SSPCON2 (MSSP Control 2, I C Mode) ................. 199
2
SSPSTAT (MSSP Status, I C Mode) ....................... 197
SSPSTAT (MSSP Status, SPI Mode) ...................... 188
STATUS ..................................................................... 87
STKPTR (Stack Pointer) ............................................ 63
T0CON (Timer0 Control) .......................................... 147
T1CON (Timer1 Control) .......................................... 151
T2CON (Timer2 Control) .......................................... 157
T3CON (Timer3 Control) .......................................... 159
TRISE (PORTE/PSP Control) .................................. 142
TXBIE (Transmit Buffers Interrupt Enable) .............. 319
TXBnCON (Transmit Buffer n Control) .................... 282
TXBnDLC (Transmit Buffer n
Data Length Code) .......................................... 285
TXBnDm (Transmit Buffer n
Data Field Byte m) ........................................... 284
TXBnEIDH (Transmit Buffer n
Extended Identifier, High Byte) ........................ 283
TXBnEIDL (Transmit Buffer n
Extended Identifier, Low Byte) ......................... 284
TXBnSIDH (Transmit Buffer n
Standard Identifier, High Byte) ......................... 283
TXBnSIDL (Transmit Buffer n
Standard Identifier, Low Byte) ......................... 283
TXERRCNT (Transmit Error Count) ........................ 285
TXSTA (Transmit Status and Control) ..................... 228
WDTCON (Watchdog Timer Control) ...................... 354
RESET ............................................................................. 393
Resets ........................................................................ 41, 343
Brown-out Reset (BOR) ........................................... 343
Oscillator Start-up Timer (OST) ............................... 343
Power-on Reset (POR) ............................................ 343
Power-up Timer (PWRT) ......................................... 343
RETFIE ............................................................................ 394
RETLW ............................................................................ 394
RETURN .......................................................................... 395
© 2007 Microchip Technology Inc.
Preliminary
DS39761B-page 475
PIC18F2682/2685/4682/4685
Bus Collision During a Start Condition
(SCL = 0) ......................................................... 223
Bus Collision During a Start Condition
(SDA Only) ...................................................... 222
Bus Collision During a Stop Condition
(Case 1) ........................................................... 225
Bus Collision During a Stop Condition
T
T0CON Register
PSA Bit .....................................................................149
T0CS Bit ...................................................................148
T0PS2:T0PS0 Bits ...................................................149
T0SE Bit ...................................................................148
Table Reads/Table Writes ..................................................64
TBLRD .............................................................................401
TBLWT .............................................................................402
Time-out in Various Situations (table) ................................45
Timer0 ..............................................................................147
Associated Registers ...............................................149
Clock Source Edge Select (T0SE Bit) ......................148
Clock Source Select (T0CS Bit) ...............................148
Operation .................................................................148
Overflow Interrupt ....................................................149
Prescaler. See Prescaler, Timer0.
(Case 2) ........................................................... 225
Bus Collision for Transmit and
Acknowledge ................................................... 221
Capture/Compare/PWM (All CCP Modules) ............ 440
CLKO and I/O .......................................................... 437
Clock Synchronization ............................................. 207
Clock/Instruction Cycle .............................................. 65
EUSART Synchronous Receive
(Master/Slave) ................................................. 450
EUSART Synchronous Transmission
(Master/Slave) ................................................. 450
Example SPI Master Mode (CKE = 0) ..................... 442
Example SPI Master Mode (CKE = 1) ..................... 443
Example SPI Slave Mode (CKE = 0) ....................... 444
Example SPI Slave Mode (CKE = 1) ....................... 445
External Clock (All Modes Except PLL) ................... 435
Fail-Safe Clock Monitor ........................................... 357
First Start Bit Timing ................................................ 215
Full-Bridge PWM Output .......................................... 179
Half-Bridge PWM Output ......................................... 178
High/Low-Voltage Detect Characteristics ................ 432
High-Voltage Detect (VDIRMAG = 1) ...................... 270
Reads and Writes in 16-Bit Mode ............................148
Timer1 ..............................................................................151
16-Bit Read/Write Mode ...........................................153
Associated Registers ...............................................155
Interrupt ....................................................................154
Operation .................................................................152
Oscillator ..................................................................153
Layout Considerations .....................................154
Resetting, Using a Special Event
Trigger Output (CCP1) .....................................154
Special Event Trigger (ECCP1) ...............................174
Use as a Real-Time Clock .......................................154
Timer2 ..............................................................................157
Associated Registers ...............................................158
Interrupt ....................................................................158
Operation .................................................................157
Output ......................................................................158
PR2 Register .................................................... 169, 175
TMR2 to PR2 Match Interrupt ..................................169
Timer3 ..............................................................................159
16-Bit Read/Write Mode ...........................................161
Associated Registers ...............................................161
Operation .................................................................160
Oscillator ..................................................151, 159, 161
Overflow Interrupt ....................................................161
Special Event Trigger (ECCP1) ...............................161
TMR3H Register .............................................. 151, 159
TMR3L Register ............................................... 151, 159
Timing Diagrams
2
I C Bus Data ............................................................ 446
2
I C Bus Start/Stop Bits ............................................ 446
2
I C Master Mode (7 or 10-Bit Transmission) ........... 218
2
I C Master Mode (7-Bit Reception) .......................... 219
2
I C Slave Mode (10-Bit Reception, SEN = 0) .......... 204
2
I C Slave Mode (10-Bit Reception, SEN = 1) .......... 209
2
I C Slave Mode (10-Bit Transmission) .................... 205
2
I C Slave Mode (7-Bit Reception, SEN = 0) ............ 202
2
I C Slave Mode (7-Bit Reception, SEN = 1) ............ 208
2
I C Slave Mode (7-Bit Transmission) ...................... 203
2
I C Slave Mode General Call Address
Sequence (7 or 10-Bit Address Mode) ............ 210
Low-Voltage Detect (VDIRMAG = 0) ....................... 269
2
Master SSP I C Bus Data ........................................ 448
2
Master SSP I C Bus Start/Stop Bits ........................ 448
Parallel Slave Port (PIC18F4682/4685) ................... 441
Parallel Slave Port (PSP) Read ............................... 145
Parallel Slave Port (PSP) Write ............................... 145
PWM Auto-Shutdown (PRSEN = 0,
Auto-Restart Disabled) .................................... 184
PWM Auto-Shutdown (PRSEN = 1,
Auto-Restart Enabled) ..................................... 184
PWM Direction Change ........................................... 181
PWM Direction Change at Near
100% Duty Cycle ............................................. 181
PWM Output ............................................................ 169
Repeated Start Condition ........................................ 216
Reset, Watchdog Timer (WDT), Oscillator
A/D Conversion ........................................................452
Acknowledge Sequence ..........................................220
Asynchronous Reception .........................................239
Asynchronous Transmission ....................................237
Asynchronous Transmission
(Back-to-Back) .................................................237
Automatic Baud Rate Calculation ............................235
Auto-Wake-up Bit (WUE) During
Normal Operation .............................................240
Auto-Wake-up Bit (WUE) During Sleep ...................240
Baud Rate Generator with Clock Arbitration ............214
BRG Overflow Sequence .........................................235
BRG Reset Due to SDA Arbitration
During Start Condition ......................................223
Brown-out Reset (BOR) ...........................................438
Bus Collision During a Repeated
Start-up Timer (OST) and Power-up
Timer (PWRT) ................................................. 438
Send Break Character Sequence ............................ 241
Slave Synchronization ............................................. 193
Slow Rise Time (MCLR Tied to VDD,
VDD Rise > TPWRT) ............................................ 47
SPI Mode (Master Mode) ......................................... 192
SPI Mode (Slave Mode with CKE = 0) ..................... 194
Start Condition (Case 1) ..................................224
Bus Collision During a Repeated
Start Condition (Case 2) ..................................224
DS39761B-page 476
Preliminary
© 2007 Microchip Technology Inc.
PIC18F2682/2685/4682/4685
SPI Mode (Slave Mode with CKE = 1) ..................... 194
Example SPI Mode Requirements
Stop Condition Receive or Transmit Mode .............. 220
Synchronous Reception
(Master Mode, SREN) ..................................... 244
Synchronous Transmission ...................................... 242
Synchronous Transmission
(Slave Mode, CKE = 1) .................................... 445
External Clock Requirements .................................. 435
2
I C Bus Data Requirements (Slave Mode) .............. 447
2
I C Bus Start/Stop Bits Requirements
(Slave Mode) ................................................... 446
2
(Through TXEN) .............................................. 243
Time-out Sequence on POR w/PLL
Master SSP I C Bus Data Requirements ................ 449
2
Master SSP I C Bus Start/Stop Bits
Enabled (MCLR Tied to VDD) ............................. 47
Time-out Sequence on Power-up
Requirements .................................................. 448
Parallel Slave Port Requirements
(MCLR Not Tied to VDD), Case 1 ....................... 46
Time-out Sequence on Power-up
(MCLR Not Tied to VDD), Case 2 ....................... 46
Time-out Sequence on Power-up
(PIC18F4682/4685) ......................................... 441
PLL Clock ................................................................ 436
Reset, Watchdog Timer, Oscillator Start-up
Timer, Power-up Timer and Brown-out
(MCLR Tied to VDD, VDD Rise Tpwrt) ................ 46
Timer0 and Timer1 External Clock .......................... 439
Transition for Entry to Idle Mode ................................ 38
Transition for Entry to SEC_RUN Mode .................... 35
Transition for Entry to Sleep Mode ............................ 37
Transition for Two-Speed Start-up
(INTOSC to HSPLL) ........................................ 355
Transition for Wake From Idle
to Run Mode ..................................................... 38
Transition for Wake From Sleep (HSPLL) ................. 37
Transition From RC_RUN Mode
Reset Requirements ........................................ 438
Timer0 and Timer1 External
Clock Requirements ........................................ 439
Top-of-Stack Access .......................................................... 62
TRISE Register
PSPMODE Bit ......................................................... 138
TSTFSZ ........................................................................... 403
Two-Speed Start-up ................................................. 343, 355
Two-Word Instructions
Example Cases ......................................................... 66
TXSTA Register
to PRI_RUN Mode ............................................. 36
Transition From SEC_RUN Mode
to PRI_RUN Mode (HSPLL) .............................. 35
Transition to RC_RUN Mode ..................................... 36
Timing Diagrams and Specifications ................................ 435
AC Characteristics
BRGH Bit ................................................................. 231
V
Voltage Reference Specifications .................................... 431
W
Watchdog Timer (WDT) ........................................... 343, 353
Associated Registers ............................................... 354
Control Register ....................................................... 353
Programming Considerations .................................. 353
WCOL ...................................................... 215, 216, 217, 220
WCOL Status Flag ................................... 215, 216, 217, 220
WWW Address ................................................................ 478
WWW, On-Line Support ...................................................... 5
Internal RC Accuracy ....................................... 436
Capture/Compare/PWM Requirements
(All CCP Modules) ........................................... 440
CLKO and I/O Requirements ................................... 437
EUSART Synchronous Receive
Requirements .................................................. 450
EUSART Synchronous Transmission
Requirements .................................................. 450
Example SPI Mode Requirements
(Master Mode, CKE = 0) .................................. 442
Example SPI Mode Requirements
(Master Mode, CKE = 1) .................................. 443
Example SPI Mode Requirements
X
XORLW ........................................................................... 403
XORWF ........................................................................... 404
(Slave Mode, CKE = 0) .................................... 444
© 2007 Microchip Technology Inc.
Preliminary
DS39761B-page 477
PIC18F2682/2685/4682/4685
NOTES:
DS39761B-page 478
Preliminary
© 2007 Microchip Technology Inc.
PIC18F2682/2685/4682/4685
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© 2007 Microchip Technology Inc.
Preliminary
DS39761B-page 479
PIC18F2682/2685/4682/4685
READER RESPONSE
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DS39761B
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PIC18F2682/2685/4682/4685
Device:
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DS39761B-page 480
Preliminary
© 2007 Microchip Technology Inc.
PIC18F2682/2685/4682/4685
PIC18F2682/2685/4682/4685 PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
PART NO.
Device
X
/XX
XXX
Examples:
Temperature
Range
Package
Pattern
a)
PIC18LF4685-I/P 301 = Industrial temp., PDIP
package, Extended VDD limits, QTP pattern
#301.
b)
c)
PIC18LF2685-I/SO = Industrial temp., SOIC
package, Extended VDD limits.
Device
PIC18F2682/2685(1), PIC18F4682/4685(1)
,
PIC18F4685-I/P = Industrial temp., PDIP
package, normal VDD limits.
PIC18F2682/2685T(2), PIC18F4682/4685T(2)
VDD range 4.2V to 5.5V
;
PIC18LF2682/2685(1), PIC18LF4682/4685(1)
PIC18LF2682/2685T(2), PIC18LF4682/4685T(2)
VDD range 2.0V to 5.5V
,
;
Temperature Range
Package
I
=
-40°C to +85°C (Industrial)
PT
SO
SP
P
=
=
=
=
=
TQFP (Thin Quad Flatpack)
SOIC
Skinny Plastic DIP
Note 1:
2:
F
LF
=
=
Standard Voltage Range
Wide Voltage Range
PDIP
QFN
ML
T = in tape and reel PLCC and TQFP
packages only.
Pattern
QTP, SQTP, Code or Special Requirements
(blank otherwise)
© 2007 Microchip Technology Inc.
Preliminary
DS39761B-page 481
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China - Qingdao
Tel: 86-532-8502-7355
Fax: 86-532-8502-7205
Philippines - Manila
Tel: 63-2-634-9065
Fax: 63-2-634-9069
Detroit
Farmington Hills, MI
Tel: 248-538-2250
Fax: 248-538-2260
China - Shanghai
Tel: 86-21-5407-5533
Fax: 86-21-5407-5066
Singapore
Tel: 65-6334-8870
Fax: 65-6334-8850
Kokomo
Kokomo, IN
Tel: 765-864-8360
Fax: 765-864-8387
China - Shenyang
Tel: 86-24-2334-2829
Fax: 86-24-2334-2393
Taiwan - Hsin Chu
Tel: 886-3-572-9526
Fax: 886-3-572-6459
China - Shenzhen
Tel: 86-755-8203-2660
Fax: 86-755-8203-1760
Taiwan - Kaohsiung
Tel: 886-7-536-4818
Fax: 886-7-536-4803
Los Angeles
Mission Viejo, CA
Tel: 949-462-9523
Fax: 949-462-9608
China - Shunde
Tel: 86-757-2839-5507
Fax: 86-757-2839-5571
Taiwan - Taipei
Tel: 886-2-2500-6610
Fax: 886-2-2508-0102
Santa Clara
Santa Clara, CA
Tel: 408-961-6444
Fax: 408-961-6445
China - Wuhan
Tel: 86-27-5980-5300
Fax: 86-27-5980-5118
Thailand - Bangkok
Tel: 66-2-694-1351
Fax: 66-2-694-1350
Toronto
Mississauga, Ontario,
Canada
Tel: 905-673-0699
Fax: 905-673-6509
China - Xian
Tel: 86-29-8833-7250
Fax: 86-29-8833-7256
12/08/06
DS39761B-page 482
Preliminary
© 2007 Microchip Technology Inc.
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