PIC18F46K20-E/SOQTP [MICROCHIP]
28/40/44-Pin Flash Microcontrollers with 10-Bit A/D and nanoWatt Technology; 28 /40/ 44引脚闪存微控制器与10位A / D和纳瓦技术型号: | PIC18F46K20-E/SOQTP |
厂家: | MICROCHIP |
描述: | 28/40/44-Pin Flash Microcontrollers with 10-Bit A/D and nanoWatt Technology |
文件: | 总420页 (文件大小:7028K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
PIC18F23K20/24K20/25K20/
26K20/43K20/44K20/45K20/
46K20
Data Sheet
28/40/44-Pin
Flash Microcontrollers
with 10-Bit A/D and nanoWatt Technology
© 2007 Microchip Technology Inc.
Advance Information
DS41303B
Note the following details of the code protection feature on Microchip devices:
•
Microchip products meet the specification contained in their particular Microchip Data Sheet.
•
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
•
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
•
•
Microchip is willing to work with the customer who is concerned about the integrity of their code.
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION,
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
QUALITY, PERFORMANCE, MERCHANTABILITY OR
FITNESS FOR PURPOSE. Microchip disclaims all liability
arising from this information and its use. Use of Microchip
devices in life support and/or safety applications is entirely at
the buyer’s risk, and the buyer agrees to defend, indemnify and
hold harmless Microchip from any and all damages, claims,
suits, or expenses resulting from such use. No licenses are
conveyed, implicitly or otherwise, under any Microchip
intellectual property rights.
Trademarks
The Microchip name and logo, the Microchip logo, Accuron,
dsPIC, KEELOQ, KEELOQ logo, microID, MPLAB, PIC,
PICmicro, PICSTART, PRO MATE, PowerSmart, rfPIC, and
SmartShunt are registered trademarks of Microchip
Technology Incorporated in the U.S.A. and other countries.
AmpLab, FilterLab, Linear Active Thermistor, Migratable
Memory, MXDEV, MXLAB, PS logo, SEEVAL, SmartSensor
and The Embedded Control Solutions Company are
registered trademarks of Microchip Technology Incorporated
in the U.S.A.
Analog-for-the-Digital Age, Application Maestro, CodeGuard,
dsPICDEM, dsPICDEM.net, dsPICworks, ECAN,
ECONOMONITOR, FanSense, FlexROM, fuzzyLAB,
In-Circuit Serial Programming, ICSP, ICEPIC, Mindi, MiWi,
MPASM, MPLAB Certified logo, MPLIB, MPLINK, PICkit,
PICDEM, PICDEM.net, PICLAB, PICtail, PowerCal,
PowerInfo, PowerMate, PowerTool, REAL ICE, rfLAB,
rfPICDEM, Select Mode, Smart Serial, SmartTel, Total
Endurance, UNI/O, WiperLock and ZENA are trademarks of
Microchip Technology Incorporated in the U.S.A. and other
countries.
SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.
All other trademarks mentioned herein are property of their
respective companies.
© 2007, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.
Printed on recycled paper.
Microchip received ISO/TS-16949:2002 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona, Gresham, Oregon and Mountain View, California. The
Company’s quality system processes and procedures are for its PIC®
MCUs and dsPIC® DSCs, KEELOQ® code hopping devices, Serial
EEPROMs, microperipherals, nonvolatile memory and analog
products. In addition, Microchip’s quality system for the design and
manufacture of development systems is ISO 9001:2000 certified.
DS41303B-page ii
Advance Information
© 2007 Microchip Technology Inc.
PIC18F2XK20/4XK20
28/40/44-Pin Flash Microcontrollers with
10-Bit A/D and nanoWatt Technology
Power-Managed Modes:
Flexible Oscillator Structure:
• Run: CPU on, peripherals on
• Idle: CPU off, peripherals on
• Sleep: CPU off, peripherals off
• Four Crystal modes, up to 64 MHz
• 4X Phase Lock Loop (available for crystal and
internal oscillators)
• Two External RC modes, up to 4 MHz
• Two External Clock modes, up to 64 MHz
• Internal oscillator block:
- 8 user selectable frequencies, from 31 kHz to
16 MHz
• Idle mode currents down to 1.0 μA, typical
• Sleep mode current down to 0.1 μA, typical
• Timer1 Oscillator: 1.0 μA, 32 kHz, 1.8V, typical
• Watchdog Timer: 2.0 μA, 1.8V, typical
• Two-Speed Oscillator Start-up
- Provides a complete range of clock speeds
from 31 kHz to 64 MHz when used with PLL
- User tunable to compensate for frequency drift
• Secondary oscillator using Timer1 @ 32 kHz
• Fail-Safe Clock Monitor:
Peripheral Highlights:
• High-current sink/source 25 mA/25 mA
• Three programmable external interrupts
• Four independent input-change interrupts
• 8 independent weak pull-ups
• Programmable slew rate
- Allows for safe shutdown if primary or secondary
oscillator stops
• Capture/Compare/PWM (CCP) module
• Enhanced Capture/Compare/PWM (ECCP)
module:
- One, two or four PWM outputs
- Selectable polarity
Special Microcontroller Features:
• C compiler optimized architecture:
- Optional extended instruction set designed to
optimize re-entrant code
• Self-programmable under software control
• Priority levels for interrupts
• 8 x 8 Single-Cycle Hardware Multiplier
• Extended Watchdog Timer (WDT):
- Programmable period from 4 ms to 131s
• Single-supply 3V In-Circuit Serial
Programming™ (ICSP™) via two pins
• In-Circuit Debug (ICD) via two pins
• Operating voltage range: 1.8V to 3.6V
• Programmable 16-level High/Low-Voltage
Detection (HLVD) module:
- Programmable dead time
- Auto-Shutdown and Auto-Restart
• Master Synchronous Serial Port (MSSP) module
supporting 3-wire SPI (all 4 modes) and I2C™
Master and Slave modes with address mask
• Enhanced Addressable USART module:
- Supports RS-485, RS-232 and LIN 2.0
- RS-232 operation using internal oscillator
block (no external crystal required)
- Auto-Wake-up on Break
- Auto-Baud Detect
• 10-bit, up to 14-channel Analog-to-Digital
Converter module (ADC):
- Supports interrupt on High/Low-Voltage
Detection
• Programmable Brown-out Reset (BOR)
- With software enable option
- Auto-acquisition capability
- Conversion available during Sleep
- Internal 1.2V Fixed Voltage Reference (FVR)
channel
- Independent input multiplexing
• Dual analog comparators
- Rail-to-rail operation
- Independent input multiplexing
• Programmable On-Chip Voltage Reference
(CVREF) module (% of VDD)
© 2007 Microchip Technology Inc.
Advance Information
DS41303B-page 1
PIC18F2XK20/4XK20
-
Program Memory
Data Memory
MSSP
10-bit
A/D
(ch)
CCP/
ECCP
(PWM)
Timers
8/16-bit
(1)
Device
I/O
Comp.
Flash # Single-Word SRAM EEPROM
(bytes) Instructions (bytes) (bytes)
Master
(2)
SPI
2
I C™
PIC18F23K20
PIC18F24K20
PIC18F25K20
PIC18F26K20
PIC18F43K20
PIC18F44K20
PIC18F45K20
PIC18F46K20
8K
16K
32K
64k
8K
4096
8192
512
768
256
256
25
11
11
11
11
14
14
14
14
1/1
1/1
1/1
1/1
1/1
1/1
1/1
1/1
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
1
1
1
1
1
1
1
1
2
2
2
2
2
2
2
2
1/3
1/3
1/3
1/3
1/3
1/3
1/3
1/3
25
25
25
36
36
36
36
16384
32768
4096
1536
3936
512
256
1024
256
16K
32K
64k
8192
768
256
16384
1536
256
32768
3936
1024
Note 1:
2:
One pin is input only.
Channel count includes internal fixed voltage reference channel.
DS41303B-page 2
Advance Information
© 2007 Microchip Technology Inc.
PIC18F2XK20/4XK20
Pin Diagrams
28-pin PDIP, SOIC, SSOP
1
2
3
4
5
6
7
8
9
28
27
26
25
24
23
22
21
20
19
18
17
16
15
RB7/KBI3/PGD
RB6//KBI2/PGC
RB5/KBI1/PGM
RB4/KBI0/AN11/P1D
RB3/AN9/C12IN3-/CCP2(1)
RB2/INT2/AN8/P1B
RB1/INT1/AN10/C12IN2-/P1C
MCLR/VPP/RE3
RA0/AN0/C12IN0-
RA1/AN1/C12IN1-
RA2/AN2/VREF-/CVREF/C2IN+
RA3/AN3/VREF+/C1IN+
RA4/T0CKI/C1OUT
RA5/AN4/SS/HLVDIN/C2OUT
VSS
RB0/INT0/FLT0/AN12
VDD
OSC1/CLKIN/RA7
VSS
OSC2/CLKOUT/RA6
RC0/T1OSO/T13CKI
RC1/T1OSI/CCP2(1)
RC2/CCP1/P1A
10
11
RC7/RX/DT
RC6/TX/CK
RC5/SDO
RC4/SDI/SDA
12
13
14
RC3/SCK/SCL
40-pin PDIP
MCLR/VPP/RE3
RA0/AN0/C12IN0-
1
2
3
4
5
6
7
8
9
RB7/KBI3/PGD
RB6/KBI2/PGC
RB5/KBI1/PGM
RB4/KBI0/AN11
RB3/AN9/C12IN3-/CCP2(1)
RB2/INT2/AN8
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
RA1/AN1/C12IN1-
RA2/AN2/VREF-/CVREF/C2IN+
RA3/AN3/VREF+/C1IN+
RA4/T0CKI/C1OUT
RA5/AN4/SS/HLVDIN/C2OUT
RE0/RD/AN5
RB1/INT1/AN10/C12IN2-
RB0/INT0/FLT0/AN12
VDD
VSS
RE1/WR/AN6
RE2/CS/AN7
10
VDD
VSS
11
12
13
14
15
16
17
18
19
20
RD7/PSP7/P1D
RD6/PSP6/P1C
RD5/PSP5/P1B
RD4/PSP4
RC7/RX/DT
RC6/TX/CK
RC5/SDO
OSC1/CLKIN/RA7
OSC2/CLKOUT/RA6
RC0/T1OSO/T13CKI
RC1/T1OSI/CCP2(1)
RC2/CCP1/P1A
RC3/SCK/SCL
RD0/PSP0
RC4/SDI/SDA
RD3/PSP3
RD1/PSP1
RD2/PSP2
28-pin QFN
28272625242322
RB3/AN9/C12IN3-/CCP2(1)
RB2/INT2/AN8/P1B
RB1/INT1/AN10/C12IN2-/P1C
RB0/INT0/FLT0/AN12
VDD
RA2/AN2/VREF-/CVREF/C2IN+
RA3/AN3/VREF+/C1IN+
RA4/T0CKI/C1OUT
RA5/AN4/SS/HLVDIN/C2OUT
VSS
1
21
2 PIC18F23K20
3
4
5
6
7
20
19
18
17
16
15
PIC18F24K20
PIC18F25K20
PIC18F26K20
OSC1/CLKIN/RA7
OSC2/CLKOUT/RA6
VSS
RC7/RX/DT
8
9 1011 121314
Note 1: RB3 is the alternate pin for CCP2 multiplexing.
© 2007 Microchip Technology Inc.
Advance Information
DS41303B-page 3
PIC18F2XK20/4XK20
Pin Diagrams (Cont.’d)
44-pin TQFP
NC
33
32
31
30
29
28
27
26
25
24
23
RC7/RX/DT
RD4/PSP4
RD5/PSP5/P1B
RD6/PSP6/P1C
RD7/PSP7/P1D
VSS
1
2
3
4
5
6
7
8
9
RC0/T1OSO/T13CKI
OSC2/CLKOUT/RA6
OSC1/CLKIN/RA7
VSS
VDD
RE2/CS/AN7
RE1/WR/AN6
RE0/RD/AN5
RA5/AN4/SS/HLVDIN/C2OUT
RA4/T0CKI/C1OUT
PIC18F43K20
PIC18F44K20
PIC18F45K20
PIC18F46K20
VDD
RB0/INT0/FLT0/AN12
RB1/INT1/AN10/C12IN2-
RB2/INT2/AN8
10
11
RB3/AN9/C12IN3-/CCP2(1)
44-pin QFN
RC7/RX/DT
OSC2/CLKOUT/RA6
OSC1/CLKIN/RA7
VSS
VSS
VDD
33
32
31
30
29
28
27
26
1
2
3
4
5
6
7
8
9
RD4/PSP4
RD5/PSP5/P1B
RD6/PSP6/P1C
RD7/PSP7/P1D
VSS
PIC18F43K20
PIC18F44K20
PIC18F45K20
PIC18F46K20
VDD
VDD
VDD
RE2/CS/AN7
RE1/WR/AN6
RE0/RD/AN5
RA5/AN4/SS/HLVDIN/C2OUT
RA4/T0CKI/C1OUT
RB0/INT0/FLT0/AN12
RB1/INT1/AN10/C12IN2-
RB2/INT2/AN8
25
24
23
10
11
Note 1: RB3 is the alternate pin for CCP2 multiplexing.
DS41303B-page 4
Advance Information
© 2007 Microchip Technology Inc.
PIC18F2XK20/4XK20
TABLE 1:
PIC18F4XK20 PIN SUMMARY
2
3
4
19
20
21
19
20
21
RA0
RA1
RA2
AN0
AN1
AN2
C12IN0-
C12IN1-
C2IN+
—
—
VREF-/
CVREF
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
5
6
22
23
24
31
22
23
24
33
RA3
RA4
RA5
RA6
AN3
C1IN+
VREF+
—
—
—
—
—
—
—
—
—
T0CKI
—
—
—
—
—
—
—
—
—
—
—
—
—
C1OUT
—
7
AN4
C2OUT HLVDIN
SS
14
—
—
—
—
—
—
—
—
—
—
OSC2/
CLKOUT
13
33
34
35
36
37
38
39
40
15
30
8
32
9
RA7
RB0
RB1
RB2
RB3
RB4
RB5
RB6
RB7
RC0
—
AN12
AN10
AN8
AN9
AN11
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
FLT0
—
—
CCP2(1)
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
—
OSC1/CLKIN
INT0
INT1
INT2
—
KBI0
KBI1
KBI2
KBI3
—
—
—
—
—
—
PGM
PGC
PGD
—
9
10
11
12
14
15
16
17
34
C12IN2-
10
11
14
15
16
17
32
—
C12IN3-
—
—
—
—
—
—
—
—
—
—
T1OSO/
T13CKI
16
17
35
36
35
36
RC1
RC2
—
—
—
—
—
—
CCP2(2)
—
—
—
—
T1OSI
—
—
—
—
—
—
—
—
CCP1/
P1A
—
18
23
37
42
37
42
RC3
RC4
—
—
—
—
—
—
—
—
—
SCK/
SCL
—
—
—
—
—
—
—
—
—
—
—
SDI/
SDA
24
25
26
19
20
21
22
27
28
29
30
43
44
1
43
44
1
RC5
RC6
RC7
RD0
RD1
RD2
RD3
RD4
RD5
RD6
RD7
—
—
—
—
—
—
—
—
—
—
—
AN5
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
P1B
P1C
P1D
—
—
TX/CK
RX/DT
—
—
—
—
—
—
—
SDO
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
38
39
40
41
2
38
39
40
41
2
PSP0
PSP1
PSP2
PSP3
PSP4
PSP5
PSP6
PSP7
3
3
4
4
5
5
—
—
8
9
25
26
27
18
25
26
27
18
RE0
RE1
RE2
RD
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
AN6
AN7
—
WR
10
1
CS
RE3(3)
—
MCLR/VPP
VDD
11
32
12
31
–
7
7
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
28
6
28
6
VDD
VSS
29
NC
NC
NC
30
8
VSS
VDD
–
29
31
VDD
–-
VSS
Note 1: CCP2 multiplexed with RB3 when CONFIG3H<0> = 0
2: CCP2 multiplexed with RC1 when CONFIG3H<0> = 1
3: Input only.
© 2007 Microchip Technology Inc.
Advance Information
DS41303B-page 5
PIC18F2XK20/4XK20
TABLE 2:
PIC18F2XK20 PIN SUMMARY
2
3
4
27
28
1
RA0
RA1
RA2
AN0
AN1
AN2
C12IN0-
C12IN1-
C2IN+
VREF-/
CVREF
5
6
2
3
4
7
RA3
RA4
RA5
RA6
AN3
AN4
C1IN+
C1OUT
C2OUT
VREF+
T0CKI
7
HLVDIN
SS
10
OSC2/
CLKOUT
9
6
RA7
OSC1/
CLKIN
21
22
23
24
25
26
27
28
11
18
19
20
21
22
23
24
25
8
RB0
RB1
RB2
RB3
RB4
RB5
RB6
RB7
RC0
AN12
AN10
AN8
FLT0
P1C
INT0
INT1
INT2
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
C12IN2-
C12IN3-
P1B
CCP2(1)
AN9
AN11
P1D
KBI0
KBI1
KBI2
KBI3
PGM
PGC
PGD
T1OSO/
T13CKI
12
13
9
RC1
RC2
CCP2(2)
T1OSI
10
CCP1/
P1A
14
15
11
12
RC3
RC4
SCK/
SCL
SDI/
SDA
16
17
18
1
13
14
15
26
RC5
RC6
SDO
TX/CK
RX/DT
RC7
RE3(3)
MCLR/
VPP
8
5
VSS
VSS
VDD
19
20
16
17
Note 1: CCP2 multiplexed with RB3 when CONFIG3H<0> = 0
2: CCP2 multiplexed with RC1 when CONFIG3H<0> = 1
3: Input only
DS41303B-page 6
Advance Information
© 2007 Microchip Technology Inc.
PIC18F2XK20/4XK20
Table of Contents
1.0 Device Overview .......................................................................................................................................................................... 9
2.0 Oscillator Module (With Fail-Safe Clock Monitor)....................................................................................................................... 25
3.0 Power-Managed Modes ............................................................................................................................................................. 41
4.0 Reset.......................................................................................................................................................................................... 49
5.0 Memory Organization................................................................................................................................................................. 63
6.0 Flash Program Memory.............................................................................................................................................................. 87
7.0 Data EEPROM Memory ............................................................................................................................................................. 97
8.0 8 x 8 Hardware Multiplier.......................................................................................................................................................... 101
9.0 Interrupts .................................................................................................................................................................................. 103
10.0 I/O Ports ................................................................................................................................................................................... 117
11.0 Timer0 Module ......................................................................................................................................................................... 137
12.0 Timer1 Module ......................................................................................................................................................................... 141
13.0 Timer2 Module ......................................................................................................................................................................... 147
14.0 Timer3 Module ......................................................................................................................................................................... 149
15.0 Capture/Compare/PWM (CCP) Modules ................................................................................................................................. 153
16.0 Enhanced Capture/Compare/PWM (ECCP) Module................................................................................................................ 165
17.0 Master Synchronous Serial Port (MSSP) Module .................................................................................................................... 185
18.0 Enhanced Universal Synchronous Asynchronous Receiver Transmitter (EUSART)............................................................... 227
19.0 Analog-to-Digital Converter (ADC) Module .............................................................................................................................. 255
20.0 Comparator Module.................................................................................................................................................................. 269
21.0 Voltage References.................................................................................................................................................................. 279
22.0 High/Low-Voltage Detect (HLVD)............................................................................................................................................. 283
23.0 Special Features of the CPU.................................................................................................................................................... 289
24.0 Instruction Set Summary.......................................................................................................................................................... 305
25.0 Development Support............................................................................................................................................................... 355
26.0 Electrical Characteristics.......................................................................................................................................................... 359
27.0 DC and AC Characteristics Graphs and Tables....................................................................................................................... 393
28.0 Packaging Information.............................................................................................................................................................. 395
Appendix A: Revision History............................................................................................................................................................. 403
Appendix B: Device Differences ........................................................................................................................................................ 403
The Microchip Web Site..................................................................................................................................................................... 415
Customer Change Notification Service .............................................................................................................................................. 415
Customer Support.............................................................................................................................................................................. 415
Reader Response.............................................................................................................................................................................. 416
Product Identification System ............................................................................................................................................................ 417
© 2007 Microchip Technology Inc.
Advance Information
DS41303B-page 7
PIC18F2XK20/4XK20
TO OUR VALUED CUSTOMERS
It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip
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If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via
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We welcome your feedback.
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The last character of the literature number is the version number, (e.g., DS30000A is version A of document DS30000).
Errata
An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current
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To determine if an errata sheet exists for a particular device, please check with one of the following:
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DS41303B-page 8
Advance Information
© 2007 Microchip Technology Inc.
PIC18F2XK20/4XK20
1.1.2
MULTIPLE OSCILLATOR OPTIONS
AND FEATURES
1.0
DEVICE OVERVIEW
This document contains device specific information for
the following devices:
All of the devices in the PIC18F2XK20/4XK20 family
offer ten different oscillator options, allowing users a
wide range of choices in developing application
hardware. These include:
• PIC18F23K20
• PIC18F24K20
• PIC18F25K20
• PIC18F26K20
• PIC18F43K20
• PIC18F44K20
• PIC18F45K20
• PIC18F46K20
• Four Crystal modes, using crystals or ceramic
resonators
• Two External Clock modes, offering the option of
using two pins (oscillator input and a divide-by-4
clock output) or one pin (oscillator input, with the
second pin reassigned as general I/O)
This family offers the advantages of all PIC18
microcontrollers namely, high computational
–
performance at an economical price – with the addition
of high-endurance, Flash program memory. On top of
these features, the PIC18F2XK20/4XK20 family
introduces design enhancements that make these
microcontrollers a logical choice for many high-
performance, power sensitive applications.
• Two External RC Oscillator modes with the same
pin options as the External Clock modes
• An internal oscillator block which contains a
16 MHz HFINTOSC oscillator and a 31 kHz
LFINTOSC oscillator which together provide 8
user selectable clock frequencies, from 31 kHz to
16 MHz. This option frees the two oscillator pins
for use as additional general purpose I/O.
1.1
New Core Features
1.1.1
nanoWatt TECHNOLOGY
• A Phase Lock Loop (PLL) frequency multiplier,
available to both the high-speed crystal and inter-
nal oscillator modes, which allows clock speeds of
up to 64 MHz. Used with the internal oscillator, the
PLL gives users a complete selection of clock
speeds, from 31 kHz to 64 MHz – all without using
an external crystal or clock circuit.
All of the devices in the PIC18F2XK20/4XK20 family
incorporate a range of features that can significantly
reduce power consumption during operation. Key
items include:
• Alternate Run Modes: By clocking the controller
from the Timer1 source or the internal oscillator
block, power consumption during code execution
can be reduced by as much as 90%.
Besides its availability as a clock source, the internal
oscillator block provides a stable reference source that
gives the family additional features for robust
operation:
• Multiple Idle Modes: The controller can also run
with its CPU core disabled but the peripherals still
active. In these states, power consumption can be
reduced even further, to as little as 4% of normal
operation requirements.
• Fail-Safe Clock Monitor: This option constantly
monitors the main clock source against a refer-
ence signal provided by the LFINTOSC. If a clock
failure occurs, the controller is switched to the
internal oscillator block, allowing for continued
operation or a safe application shutdown.
• On-the-fly Mode Switching: The power-
managed modes are invoked by user code during
operation, allowing the user to incorporate power-
saving ideas into their application’s software
design.
• Two-Speed Start-up: This option allows the
internal oscillator to serve as the clock source
from Power-on Reset, or wake-up from Sleep
mode, until the primary clock source is available.
• Low Consumption in Key Modules: The
power requirements for both Timer1 and the
Watchdog Timer are minimized. See
Section 26.0 “Electrical Characteristics”
for values.
© 2007 Microchip Technology Inc.
Advance Information
DS41303B-page 9
PIC18F2XK20/4XK20
1.2
Other Special Features
1.3
Details on Individual Family
Members
• Memory Endurance: The Flash cells for both
program memory and data EEPROM are rated to
last for many thousands of erase/write cycles – up to
10K for program memory and 100K for EEPROM.
Data retention without refresh is conservatively
estimated to be greater than 40 years.
Devices in the PIC18F2XK20/4XK20 family are avail-
able in 28-pin and 40/44-pin packages. Block diagrams
for the two groups are shown in Figure 1-1 and
Figure 1-2.
The devices are differentiated from each other in five
ways:
• Self-programmability: These devices can write
to their own program memory spaces under inter-
nal software control. By using a bootloader rou-
tine located in the protected Boot Block at the top
of program memory, it becomes possible to create
an application that can update itself in the field.
1. Flash program memory (8 Kbytes for
PIC18F23K20/43K20 devices, 16 Kbytes for
PIC18F24K20/44K20 devices, 32 Kbytes for
PIC18F25K20/45K20 AND 64 Kbytes for
PIC18F26K20/46K20).
• Extended Instruction Set: The PIC18F2XK20/
4XK20 family introduces an optional extension to
the PIC18 instruction set, which adds 8 new
instructions and an Indexed Addressing mode.
This extension, enabled as a device configuration
option, has been specifically designed to optimize
re-entrant application code originally developed in
high-level languages, such as C.
2. A/D channels (11 for 28-pin devices, 14 for
40/44-pin devices).
3. I/O ports (3 bidirectional ports on 28-pin devices,
5 bidirectional ports on 40/44-pin devices).
4. Parallel Slave Port (present only on 40/44-pin
devices).
All other features for devices in this family are identical.
These are summarized in Table 1-1.
• Enhanced CCP module: In PWM mode, this
module provides 1, 2 or 4 modulated outputs for
controlling half-bridge and full-bridge drivers.
Other features include:
The pinouts for all devices are listed in the pin summary
tables: Table 1 and Table 2, and I/O description tables:
Table 1-2 and Table 1-3.
-
Auto-Shutdown, for disabling PWM outputs
on interrupt or other select conditions
- Auto-Restart, to reactivate outputs once the
condition has cleared
- Output steering to selectively enable one or
more of 4 outputs to provide the PWM signal.
• Enhanced Addressable USART: This serial
communication module is capable of standard
RS-232 operation and provides support for the LIN
bus protocol. Other enhancements include
automatic baud rate detection and a 16-bit Baud
Rate Generator for improved resolution. When the
microcontroller is using the internal oscillator
block, the USART provides stable operation for
applications that talk to the outside world without
using an external crystal (or its accompanying
power requirement).
• 10-bit A/D Converter: This module incorporates
programmable acquisition time, allowing for a
channel to be selected and a conversion to be
initiated without waiting for a sampling period and
thus, reduce code overhead.
• Extended Watchdog Timer (WDT): This
enhanced version incorporates a 16-bit
postscaler, allowing an extended time-out range
that is stable across operating voltage and
temperature. See Section 26.0 “Electrical
Characteristics” for time-out periods.
DS41303B-page 10
Advance Information
© 2007 Microchip Technology Inc.
PIC18F2XK20/4XK20
TABLE 1-1:
DEVICE FEATURES
© 2007 Microchip Technology Inc.
Advance Information
DS41303B-page 11
PIC18F2XK20/4XK20
FIGURE 1-1:
PIC18F2XK20 (28-PIN) BLOCK DIAGRAM
Data Bus<8>
Table Pointer<21>
Data Latch
8
8
PORTA
inc/dec logic
21
RA0/AN0
RA1/AN1
Data Memory
RA2/AN2/VREF-/CVREF
RA3/AN3/VREF+
RA4/T0CKI/C1OUT
RA5/AN4/SS/HLVDIN/C2OUT
OSC2/CLKOUT(3)/RA6
OSC1/CLKIN(3)/RA7
PCLATH
PCLATU
Address Latch
20
PCU PCH PCL
Program Counter
12
Data Address<12>
31-Level Stack
STKPTR
4
BSR
12
FSR0
FSR1
FSR2
4
Address Latch
Access
Bank
Program Memory
(8/16/32/64 Kbytes)
12
Data Latch
PORTB
RB0/INT0/FLT0/AN12
RB1/INT1/AN10
RB2/INT2/AN8
inc/dec
logic
8
Table Latch
RB3/AN9/CCP2(1)
RB4/KBI0/AN11
RB5/KBI1/PGM
RB6/KBI2/PGC
RB7/KBI3/PGD
Address
Decode
ROM Latch
IR
Instruction Bus <16>
8
State machine
control signals
Instruction
Decode and
Control
PRODH PRODL
8 x 8 Multiply
PORTC
RC0/T1OSO/T13CKI
RC1/T1OSI/CCP2(1)
RC2/CCP1
3
8
W
BITOP
8
RC3/SCK/SCL
RC4/SDI/SDA
RC5/SDO
8
8
Internal
Oscillator
Block
OSC1(3)
OSC2(3)
T1OSI
Power-up
Timer
RC6/TX/CK
RC7/RX/DT
8
8
Oscillator
Start-up Timer
ALU<8>
8
LFINTOSC
Oscillator
Power-on
Reset
16 MHz
Oscillator
Watchdog
Timer
T1OSO
Precision
Band Gap
Reference
FVR
Brown-out
Reset
Fail-Safe
MCLR(2)
VDD, VSS
Single-Supply
Programming
In-Circuit
PORTE
Clock Monitor
MCLR/VPP/RE3(2)
Debugger
Data
EEPROM
BOR
Timer0
CCP2
Timer1
Timer2
Timer3
HLVD
FVR
ADC
10-bit
FVR
MSSP
Comparator
ECCP1
EUSART
CVREF
Note 1: CCP2 is multiplexed with RC1 when Configuration bit CCP2MX is set, or RB3 when CCP2MX is not set.
2: RE3 is only available when MCLR functionality is disabled.
3: OSC1/CLKIN and OSC2/CLKOUT are only available in select oscillator modes and when these pins are not being used as digital I/O.
Refer to Section 2.0 “Oscillator Module (With Fail-Safe Clock Monitor)” for additional information.
DS41303B-page 12
Advance Information
© 2007 Microchip Technology Inc.
PIC18F2XK20/4XK20
FIGURE 1-2:
PIC18F4XK20 (40/44-PIN) BLOCK DIAGRAM
Data Bus<8>
PORTA
Table Pointer<21>
RA0/AN0
RA1/AN1
Data Latch
8
8
inc/dec logic
21
RA2/AN2/VREF-/CVREF
RA3/AN3/VREF+
Data Memory
RA4/T0CKI/C1OUT
RA5/AN4/SS/HLVDIN/C2OUT
OSC2/CLKOUT(3)/RA6
OSC1/CLKIN(3)/RA7
PCLATU PCLATH
Address Latch
20
PCU PCH PCL
Program Counter
12
Data Address<12>
PORTB
31-Level Stack
STKPTR
RB0/INT0/FLT0/AN12
RB1/INT1/AN10
RB2/INT2/AN8
4
BSR
12
FSR0
FSR1
FSR2
4
Address Latch
Access
Bank
Program Memory
(8/16/32/64 Kbytes)
RB3/AN9/CCP2(1)
RB4/KBI0/AN11
RB5/KBI1/PGM
RB6/KBI2/PGC
RB7/KBI3/PGD
12
Data Latch
inc/dec
logic
8
Table Latch
Address
Decode
PORTC
ROM Latch
IR
RC0/T1OSO/T13CKI
RC1/T1OSI/CCP2(1)
RC2/CCP1/P1A
RC3/SCK/SCL
RC4/SDI/SDA
Instruction Bus <16>
RC5/SDO
RC6/TX/CK
RC7/RX/DT
8
State machine
control signals
Instruction
Decode and
Control
PRODH PRODL
8 x 8 Multiply
PORTD
RD0/PSP0
RD1/PSP1
3
8
RD2/PSP2
RD3/PSP3
RD4/PSP4
W
BITOP
8
8
8
Internal
Oscillator
Block
OSC1(3)
OSC2(3)
T1OSI
RD5/PSP5/P1B
RD6/PSP6/P1C
RD7/PSP7/P1D
Power-up
Timer
8
8
Oscillator
Start-up Timer
ALU<8>
8
LFINTOSC
Oscillator
Power-on
Reset
16 MHz
Oscillator
Watchdog
Timer
T1OSO
PORTE
RE0/RD/AN5
Precision
Band Gap
Reference
FVR
Brown-out
Reset
Fail-Safe
RE1/WR/AN6
RE2/CS/AN7
MCLR(2)
VDD, VSS
Single-Supply
Programming
In-Circuit
MCLR/VPP/RE3(2)
Clock Monitor
Debugger
Data
EEPROM
BOR
Timer0
Timer1
MSSP
Timer2
Timer3
HLVD
FVR
FVR
ADC
10-bit
PSP
Comparator
ECCP1
CCP2
EUSART
CVREF
Note 1: CCP2 is multiplexed with RC1 when Configuration bit CCP2MX is set, or RB3 when CCP2MX is not set.
2: RE3 is only available when MCLR functionality is disabled.
3: OSC1/CLKIN and OSC2/CLKOUT are only available in select oscillator modes and when these pins are not being used as digital I/O.
Refer to Section 2.0 “Oscillator Module (With Fail-Safe Clock Monitor)” for additional information.
© 2007 Microchip Technology Inc.
Advance Information
DS41303B-page 13
PIC18F2XK20/4XK20
TABLE 1-2:
PIC18F2XK20 PINOUT I/O DESCRIPTIONS
Pin Number
Pin Buffer
Type Type
Pin Name
Description
PDIP,
QFN
SOIC
MCLR/VPP/RE3
MCLR
1
26
6
Master Clear (input) or programming voltage (input)
Active-low Master Clear (device Reset) input
Programming voltage input
I
P
I
ST
ST
VPP
RE3
Digital input
OSC1/CLKIN/RA7
OSC1
9
Oscillator crystal or external clock input
Oscillator crystal input or external clock source input
ST buffer when configured in RC mode; CMOS otherwise
External clock source input. Always associated with pin
function OSC1. (See related OSC1/CLKIN, OSC2/CLKOUT
pins)
I
I
ST
CLKIN
CMOS
RA7
I/O
TTL
General purpose I/O pin
OSC2/CLKOUT/RA6
OSC2
10
7
Oscillator crystal or clock output
O
O
—
—
Oscillator crystal output. Connects to crystal or
resonator in Crystal Oscillator mode
In RC mode, OSC2 pin outputs CLKOUT which has 1/4 the
frequency of OSC1 and denotes the instruction cycle rate
General purpose I/O pin
CLKOUT
RA6
I/O
TTL
Legend: TTL= TTL compatible input
ST = Schmitt Trigger input with CMOS levels
= Output
CMOS = CMOS compatible input or output
I
= Input
O
P
= Power
Note 1: Default assignment for CCP2 when Configuration bit CCP2MX is set.
2: Alternate assignment for CCP2 when Configuration bit CCP2MX is cleared.
DS41303B-page 14
Advance Information
© 2007 Microchip Technology Inc.
PIC18F2XK20/4XK20
TABLE 1-2:
PIC18F2XK20 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number
Pin Buffer
Type Type
Pin Name
Description
PORTA is a bidirectional I/O port.
PDIP,
QFN
SOIC
RA0/AN0/C12IN0-
RA0
2
3
4
27
28
1
I/O
I
I
TTL
Analog
Analog
Digital I/O
Analog input 0, ADC channel 0
Comparators C1 and C2 inverting input
AN0
C12IN0-
RA1/AN1/C12IN1-
RA1
I/O
I
I
TTL
Analog
Analog
Digital I/O
ADC input 1, ADC channel 1
Comparators C1 and C2 inverting input
AN1
C12IN1-
RA2/AN2/VREF-/CVREF/
C2IN+
RA2
I/O
TTL
Digital I/O
AN2
I
I
O
I
Analog
Analog
Analog
Analog
Analog input 2, ADC channel 2
A/D reference voltage (low) input
Comparator reference voltage output
Comparator C2 non-inverting input
VREF-
CVREF
C2IN+
RA3/AN3/VREF+/C1IN+
5
2
RA3
I/O
TTL
Digital I/O
AN3
VREF+
C1IN+
I
I
I
Analog
Analog
Analog
Analog input 3, ADC channel 3
A/D reference voltage (high) input
Comparator C1 non-inverting input
RA4/T0CKI/C1OUT
RA4
6
7
3
4
I/O
I
O
ST
ST
CMOS
Digital I/O
Timer0 external clock input
Comparator C1 output
T0CKI
C1OUT
RA5/AN4/SS/HLVDIN/
C2OUT
RA5
I/O
I
I
I
O
TTL
Analog
TTL
Analog
CMOS
Digital I/O
AN4
SS
HLVDIN
C2OUT
Analog input 4, ADC channel 4
SPI slave select input
High/Low-Voltage Detect input
Comparator C2 output
RA6
RA7
See the OSC2/CLKOUT/RA6 pin
See the OSC1/CLKIN/RA7 pin
Legend: TTL= TTL compatible input
ST = Schmitt Trigger input with CMOS levels
= Output
CMOS = CMOS compatible input or output
I
= Input
O
P
= Power
Note 1: Default assignment for CCP2 when Configuration bit CCP2MX is set.
2: Alternate assignment for CCP2 when Configuration bit CCP2MX is cleared.
© 2007 Microchip Technology Inc.
Advance Information
DS41303B-page 15
PIC18F2XK20/4XK20
TABLE 1-2:
PIC18F2XK20 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number
Pin Buffer
Type Type
Pin Name
Description
PDIP,
QFN
SOIC
PORTB is a bidirectional I/O port. PORTB can be software
programmed for internal weak pull-up on each input.
RB0/INT0/FLT0/AN12
21
18
19
RB0
I/O
TTL
ST
ST
Digital I/O
External interrupt 0
PWM Fault input for CCP1
Analog input 12, ADC channel 12
INT0
FLT0
AN12
I
I
I
Analog
RB1/INT1/AN10/C12IN2- 22
/P1C
RB1
I/O
I
I
I
O
TTL
ST
Analog
Analog
CMOS
Digital I/O
External interrupt 1
Analog input 10, ADC channel 10
Comparators C1 and C2 inverting input
Enhanced CCP1 PWM output
INT1
AN10
C12IN2-
P1C
RB2/INT2/AN8/P1B
23
24
25
20
21
22
RB2
INT2
AN8
P1B
I/O
I
I
TTL
ST
Analog
CMOS
Digital I/O
External interrupt 2
Analog input 8, ADC channel 8
Enhanced CCP1 PWM output
O
RB3/AN9/C12IN3-/CCP2
RB3
AN9
I/O
I
I
TTL
Analog
Analog
ST
Digital I/O
Analog input 9, ADC channel 9
Comparators C1 and C2 inverting input
Capture 2 input/Compare 2 output/PWM 2 output
C12IN3-
CCP2(2)
I/O
RB4/KBI0/AN11/P1D
RB4
KBI0
AN11
P1D
I/O
I
I
TTL
TTL
Analog
CMOS
Digital I/O
Interrupt-on-change pin
Analog input 11, ADC channel 11
Enhanced CCP1 PWM output
O
RB5/KBI1/PGM
RB5
26
27
28
23
24
25
I/O
I
I/O
TTL
TTL
ST
Digital I/O
Interrupt-on-change pin
Low-Voltage ICSP™ Programming enable pin
KBI1
PGM
RB6/KBI2/PGC
RB6
I/O
I
I/O
TTL
TTL
ST
Digital I/O
Interrupt-on-change pin
In-Circuit Debugger and ICSP™ programming clock pin
KBI2
PGC
RB7/KBI3/PGD
RB7
I/O
I
I/O
TTL
TTL
ST
Digital I/O
Interrupt-on-change pin
In-Circuit Debugger and ICSP™ programming data pin
KBI3
PGD
Legend: TTL= TTL compatible input
ST = Schmitt Trigger input with CMOS levels
= Output
CMOS = CMOS compatible input or output
I
= Input
O
P
= Power
Note 1: Default assignment for CCP2 when Configuration bit CCP2MX is set.
2: Alternate assignment for CCP2 when Configuration bit CCP2MX is cleared.
DS41303B-page 16
Advance Information
© 2007 Microchip Technology Inc.
PIC18F2XK20/4XK20
TABLE 1-2:
PIC18F2XK20 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number
Pin Buffer
Type Type
Pin Name
Description
PORTC is a bidirectional I/O port.
PDIP,
QFN
SOIC
RC0/T1OSO/T13CKI
RC0
11
12
13
14
15
8
I/O
O
I
ST
—
ST
Digital I/O
Timer1 oscillator output
Timer1/Timer3 external clock input
T1OSO
T13CKI
RC1/T1OSI/CCP2
RC1
9
I/O
I
I/O
ST
Analog
ST
Digital I/O
Timer1 oscillator input
Capture 2 input/Compare 2 output/PWM 2 output
T1OSI
CCP2(1)
RC2/CCP1/P1A
RC2
10
11
12
I/O
I/O
O
ST
ST
CMOS
Digital I/O
Capture 1 input/Compare 1 output
Enhanced CCP1 PWM output
CCP1
P1A
RC3/SCK/SCL
RC3
I/O
I/O
I/O
ST
ST
ST
Digital I/O
SCK
SCL
Synchronous serial clock input/output for SPI mode
Synchronous serial clock input/output for I2C™ mode
RC4/SDI/SDA
RC4
I/O
I
I/O
ST
ST
ST
Digital I/O
SDI
SDA
SPI data in
I2C™ data I/O
RC5/SDO
RC5
16
17
13
14
I/O
O
ST
—
Digital I/O
SPI data out
SDO
RC6/TX/CK
RC6
I/O
O
I/O
ST
—
ST
Digital I/O
TX
CK
EUSART asynchronous transmit
EUSART synchronous clock (see related RX/DT)
RC7/RX/DT
RC7
18
—
15
—
I/O
I
I/O
ST
ST
ST
Digital I/O
RX
DT
EUSART asynchronous receive
EUSART synchronous data (see related TX/CK)
RE3
VSS
VDD
—
P
—
—
—
See MCLR/VPP/RE3 pin
8, 19 5, 16
20 17
Ground reference for logic and I/O pins
Positive supply for logic and I/O pins
CMOS = CMOS compatible input or output
P
Legend: TTL= TTL compatible input
ST = Schmitt Trigger input with CMOS levels
= Output
I
= Input
O
P
= Power
Note 1: Default assignment for CCP2 when Configuration bit CCP2MX is set.
2: Alternate assignment for CCP2 when Configuration bit CCP2MX is cleared.
© 2007 Microchip Technology Inc.
Advance Information
DS41303B-page 17
PIC18F2XK20/4XK20
TABLE 1-3:
Pin Name
PIC18F4XK20 PINOUT I/O DESCRIPTIONS
Pin Number
Pin Buffer
Type Type
Description
PDIP QFN TQFP
MCLR/VPP/RE3
MCLR
1
18
32
18
30
Master Clear (input) or programming voltage (input)
Active-low Master Clear (device Reset) input
Programming voltage input
I
P
I
ST
ST
VPP
RE3
Digital input
OSC1/CLKIN/RA7
OSC1
13
Oscillator crystal or external clock input
Oscillator crystal input or external clock source input
ST buffer when configured in RC mode;
analog otherwise
I
I
ST
CMOS
TTL
CLKIN
External clock source input. Always associated with
pin function OSC1 (See related OSC1/CLKIN,
OSC2/CLKOUT pins)
RA7
I/O
General purpose I/O pin
OSC2/CLKOUT/RA6
OSC2
14
33
31
Oscillator crystal or clock output
O
O
—
—
Oscillator crystal output. Connects to crystal
or resonator in Crystal Oscillator mode
In RC mode, OSC2 pin outputs CLKOUT which
has 1/4 the frequency of OSC1 and denotes
the instruction cycle rate
CLKOUT
RA6
I/O
TTL
General purpose I/O pin
Legend: TTL= TTL compatible input
ST = Schmitt Trigger input with CMOS levels
= Output
CMOS = CMOS compatible input or output
I
= Input
O
P
= Power
Note 1: Default assignment for CCP2 when Configuration bit CCP2MX is set.
2: Alternate assignment for CCP2 when Configuration bit CCP2MX is cleared.
DS41303B-page 18
Advance Information
© 2007 Microchip Technology Inc.
PIC18F2XK20/4XK20
TABLE 1-3:
Pin Name
PIC18F4XK20 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number
Pin Buffer
Type Type
Description
PDIP QFN TQFP
PORTA is a bidirectional I/O port.
RA0/AN0/C12IN0-
RA0
2
3
4
19
20
21
19
20
21
I/O
I
I
TTL
Analog
Analog
Digital I/O
Analog input 0, ADC channel 0
Comparator C1 and C2 inverting input
AN0
C12IN0-
RA1/AN1/C12IN0-
RA1
I/O
I
I
TTL
Analog
Analog
Digital I/O
Analog input 1, ADC channel 1
Comparator C1 and C2 inverting input
AN1
C12IN0-
RA2/AN2/VREF-/CVREF/
C2IN+
RA2
I/O
TTL
Digital I/O
AN2
I
I
O
I
Analog
Analog
Analog
Analog
Analog input 2, ADC channel 2
A/D reference voltage (low) input
Comparator reference voltage output
Comparator C2 non-inverting input
VREF-
CVREF
C2IN+
RA3/AN3/VREF+/
C1IN+
5
22
22
RA3
I/O
TTL
Digital I/O
AN3
VREF+
C1IN+
I
I
I
Analog
Analog
Analog
Analog input 3, ADC channel 3
A/D reference voltage (high) input
Comparator C1 non-inverting input
RA4/T0CKI/C1OUT
RA4
6
7
23
24
23
24
I/O
I
O
ST
ST
CMOS
Digital I/O
Timer0 external clock input
Comparator C1 output
T0CKI
C1OUT
RA5/AN4/SS/HLVDIN/
C2OUT
RA5
I/O
I
I
I
O
TTL
Analog
TTL
Analog
CMOS
Digital I/O
AN4
SS
HLVDIN
C2OUT
Analog input 4, ADC channel 4
SPI slave select input
High/Low-Voltage Detect input
Comparator C2 output
RA6
RA7
See the OSC2/CLKOUT/RA6 pin
See the OSC1/CLKIN/RA7 pin
Legend: TTL= TTL compatible input
ST = Schmitt Trigger input with CMOS levels
= Output
CMOS = CMOS compatible input or output
I
= Input
O
P
= Power
Note 1: Default assignment for CCP2 when Configuration bit CCP2MX is set.
2: Alternate assignment for CCP2 when Configuration bit CCP2MX is cleared.
© 2007 Microchip Technology Inc.
Advance Information
DS41303B-page 19
PIC18F2XK20/4XK20
TABLE 1-3:
Pin Name
PIC18F4XK20 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number
Pin Buffer
Type Type
Description
PDIP QFN TQFP
PORTB is a bidirectional I/O port. PORTB can be
software programmed for internal weak pull-up on
each input.
RB0/INT0/FLT0/AN12
33
34
9
8
9
RB0
I/O
TTL
ST
ST
Digital I/O
External interrupt 0
PWM Fault input for Enhanced CCP1
Analog input 12, ADC channel 12
INT0
FLT0
AN12
I
I
I
Analog
RB1/INT1/AN10/
C12IN2-
RB1
10
I/O
TTL
ST
Analog
Analog
Digital I/O
External interrupt 1
Analog input 10, ADC channel 10
Comparator C1 and C2 inverting input
INT1
AN10
C12IN2-
I
I
I
RB2/INT2/AN8
RB2
35
36
11
12
10
11
I/O
I
I
TTL
ST
Analog
Digital I/O
External interrupt 2
Analog input 8, ADC channel 8
INT2
AN8
RB3/AN9/C12IN3-/
CCP2
RB3
AN9
I/O
I
I
TTL
Analog
Analog
ST
Digital I/O
Analog input 9, ADC channel 9
Comparator C1 and C2 inverting input
Capture 2 input/Compare 2 output/PWM 2 output
C12IN3-
CCP2(2)
I/O
RB4/KBI0/AN11
RB4
37
38
39
14
15
16
14
15
16
I/O
I
I
TTL
TTL
Analog
Digital I/O
Interrupt-on-change pin
Analog input 11, ADC channel 11
KBI0
AN11
RB5/KBI1/PGM
RB5
I/O
I
I/O
TTL
TTL
ST
Digital I/O
Interrupt-on-change pin
Low-Voltage ICSP™ Programming enable pin
KBI1
PGM
RB6/KBI2/PGC
RB6
I/O
I
I/O
TTL
TTL
ST
Digital I/O
Interrupt-on-change pin
In-Circuit Debugger and ICSP™ programming
clock pin
KBI2
PGC
RB7/KBI3/PGD
RB7
40
17
17
I/O
I
I/O
TTL
TTL
ST
Digital I/O
Interrupt-on-change pin
In-Circuit Debugger and ICSP™ programming
data pin
KBI3
PGD
Legend: TTL= TTL compatible input
ST = Schmitt Trigger input with CMOS levels
= Output
CMOS = CMOS compatible input or output
I
= Input
O
P
= Power
Note 1: Default assignment for CCP2 when Configuration bit CCP2MX is set.
2: Alternate assignment for CCP2 when Configuration bit CCP2MX is cleared.
DS41303B-page 20
Advance Information
© 2007 Microchip Technology Inc.
PIC18F2XK20/4XK20
TABLE 1-3:
Pin Name
PIC18F4XK20 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number
Pin Buffer
Type Type
Description
PDIP QFN TQFP
PORTC is a bidirectional I/O port.
RC0/T1OSO/T13CKI
RC0
15
16
17
18
34
35
36
37
32
35
36
37
I/O
O
I
ST
—
ST
Digital I/O
Timer1 oscillator output
Timer1/Timer3 external clock input
T1OSO
T13CKI
RC1/T1OSI/CCP2
RC1
I/O
I
I/O
ST
CMOS
ST
Digital I/O
Timer1 oscillator input
Capture 2 input/Compare 2 output/PWM 2 output
T1OSI
CCP2(1)
RC2/CCP1/P1A
RC2
I/O
I/O
O
ST
ST
—
Digital I/O
CCP1
P1A
Capture 1 input/Compare 1 output/PWM 1 output
Enhanced CCP1 output
RC3/SCK/SCL
RC3
I/O
I/O
ST
ST
Digital I/O
SCK
Synchronous serial clock input/output for
SPI mode
SCL
I/O
ST
Synchronous serial clock input/output for I2C™ mode
RC4/SDI/SDA
RC4
23
42
42
I/O
I
I/O
ST
ST
ST
Digital I/O
SDI
SDA
SPI data in
I2C™ data I/O
RC5/SDO
RC5
24
25
43
44
43
44
I/O
O
ST
—
Digital I/O
SPI data out
SDO
RC6/TX/CK
RC6
I/O
O
I/O
ST
—
ST
Digital I/O
TX
CK
EUSART asynchronous transmit
EUSART synchronous clock (see related RX/DT)
RC7/RX/DT
RC7
26
1
1
I/O
I
I/O
ST
ST
ST
Digital I/O
RX
DT
EUSART asynchronous receive
EUSART synchronous data (see related TX/CK)
Legend: TTL= TTL compatible input
ST = Schmitt Trigger input with CMOS levels
= Output
CMOS = CMOS compatible input or output
I
= Input
O
P
= Power
Note 1: Default assignment for CCP2 when Configuration bit CCP2MX is set.
2: Alternate assignment for CCP2 when Configuration bit CCP2MX is cleared.
© 2007 Microchip Technology Inc.
Advance Information
DS41303B-page 21
PIC18F2XK20/4XK20
TABLE 1-3:
Pin Name
PIC18F4XK20 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number
Pin Buffer
Type Type
Description
PDIP QFN TQFP
PORTD is a bidirectional I/O port or a Parallel Slave
Port (PSP) for interfacing to a microprocessor port.
These pins have TTL input buffers when PSP module
is enabled.
RD0/PSP0
RD0
19
20
21
22
27
28
38
39
40
41
2
38
39
40
41
2
I/O
I/O
ST
TTL
Digital I/O
Parallel Slave Port data
PSP0
RD1/PSP1
RD1
I/O
I/O
ST
TTL
Digital I/O
Parallel Slave Port data
PSP1
RD2/PSP2
RD2
I/O
I/O
ST
TTL
Digital I/O
Parallel Slave Port data
PSP2
RD3/PSP3
RD3
I/O
I/O
ST
TTL
Digital I/O
Parallel Slave Port data
PSP3
RD4/PSP4
RD4
I/O
I/O
ST
TTL
Digital I/O
Parallel Slave Port data
PSP4
RD5/PSP5/P1B
RD5
3
3
I/O
I/O
O
ST
TTL
—
Digital I/O
Parallel Slave Port data
Enhanced CCP1 output
PSP5
P1B
RD6/PSP6/P1C
RD6
29
30
4
5
4
5
I/O
I/O
O
ST
TTL
—
Digital I/O
Parallel Slave Port data
Enhanced CCP1 output
PSP6
P1C
RD7/PSP7/P1D
RD7
I/O
I/O
O
ST
TTL
—
Digital I/O
Parallel Slave Port data
Enhanced CCP1 output
PSP7
P1D
Legend: TTL= TTL compatible input
ST = Schmitt Trigger input with CMOS levels
= Output
CMOS = CMOS compatible input or output
I
= Input
O
P
= Power
Note 1: Default assignment for CCP2 when Configuration bit CCP2MX is set.
2: Alternate assignment for CCP2 when Configuration bit CCP2MX is cleared.
DS41303B-page 22
Advance Information
© 2007 Microchip Technology Inc.
PIC18F2XK20/4XK20
TABLE 1-3:
Pin Name
PIC18F4XK20 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number
Pin Buffer
Type Type
Description
PDIP QFN TQFP
PORTE is a bidirectional I/O port
RE0/RD/AN5
RE0
8
9
25
26
27
—
25
26
27
—
I/O
I
ST
TTL
Digital I/O
RD
Read control for Parallel Slave Port
(see related WR and CS pins)
Analog input 5, ADC channel 5
AN5
I
Analog
RE1/WR/AN6
RE1
I/O
I
ST
TTL
Digital I/O
WR
Write control for Parallel Slave Port
(see related CS and RD pins)
Analog input 6, ADC channel 6
AN6
I
Analog
RE2/CS/AN7
RE2
10
—
I/O
I
ST
TTL
Digital I/O
CS
Chip Select control for Parallel Slave Port
(see related RD and WR)
Analog input 7, ADC channel 7
AN7
RE3
I
Analog
—
—
P
See MCLR/VPP/RE3 pin
VSS
12, 31 6, 30, 6, 29
31
—
Ground reference for logic and I/O pins
VDD
NC
11, 32 7, 8, 7, 28
28, 29
P
—
—
Positive supply for logic and I/O pins
No connect
—
13 12,13,
33, 34
—
Legend: TTL= TTL compatible input
ST = Schmitt Trigger input with CMOS levels
= Output
CMOS = CMOS compatible input or output
I
= Input
O
P
= Power
Note 1: Default assignment for CCP2 when Configuration bit CCP2MX is set.
2: Alternate assignment for CCP2 when Configuration bit CCP2MX is cleared.
© 2007 Microchip Technology Inc.
Advance Information
DS41303B-page 23
PIC18F2XK20/4XK20
NOTES:
DS41303B-page 24
Advance Information
© 2007 Microchip Technology Inc.
PIC18F2XK20/4XK20
The Oscillator module can be configured in one of ten
primary clock modes.
2.0
2.1
OSCILLATOR MODULE (WITH
FAIL-SAFE CLOCK MONITOR)
1. LP
Low-Power Crystal
2. XT
Crystal/Resonator
Overview
3. HS
High-Speed Crystal/Resonator
The Oscillator module has a wide variety of clock
sources and selection features that allow it to be used
in a wide range of applications while maximizing perfor-
mance and minimizing power consumption. Figure 2-1
illustrates a block diagram of the Oscillator module.
4. HSPLL
High-Speed Crystal/Resonator
with PLL enabled
5. RC
External Resistor/Capacitor with
FOSC/4 output on RA6
6. RCIO
7. INTOSC
External Resistor/Capacitor with I/O
on RA6
Clock sources can be configured from external
oscillators, quartz crystal resonators, ceramic resonators
and Resistor-Capacitor (RC) circuits. In addition, the
system clock source can be configured from one of two
internal oscillators, with a choice of speeds selectable via
software. Additional clock features include:
Internal Oscillator with FOSC/4
output on RA6 and I/O on RA7
8. INTOSCIO Internal Oscillator with I/O on RA6
and RA7
9. EC
External Clock with FOSC/4 output
External Clock with I/O on RA6
• Selectable system clock source between external
or internal via software.
10. ECIO
• Two-Speed Start-up mode, which minimizes
latency between external oscillator start-up and
code execution.
Primary Clock modes are selected by the FOSC<3:0>
bits of the CONFIG1H Configuration Register. The
HFINTOSC and LFINTOSC are factory calibrated high-
frequency and low-frequency oscillators, respectively,
which are used as the internal clock sources.
• Fail-Safe Clock Monitor (FSCM) designed to
detect a failure of the external clock source (LP,
XT, HS, EC or RC modes) and switch
automatically to the internal oscillator.
FIGURE 2-1:
PIC® MCU CLOCK SOURCE BLOCK DIAGRAM
PIC18F2XK20/4XK20
Primary Oscillator
LP, XT, HS, RC, EC
HSPLL, HFINTOSC/PLL
T1OSC
OSC2
IDLEN
Sleep
Sleep
4 x PLL
OSC1
OSCTUNE<6>(1)
Peripherals
Secondary Oscillator
Main
T1OSO
T1OSCEN
Enable
Oscillator
T1OSI
OSCCON<6:4>
Internal Oscillator
16 MHz
FOSC<3:0> OSCCON<1:0>
CPU
111
110
101
8 MHz
4 MHz
Sleep
Internal
Oscillator
Block
Clock
Control
2 MHz
100
011
010
001
000
16 MHz
1 MHz
Source
16 MHz
(HFINTOSC)
500 kHz
250 kHz
31 kHz
31 kHz
Source
FOSC<3:0> OSCCON<1:0>
Clock Source Option
for other Modules
1
0
31 kHz (LFINTOSC)
OSCTUNE<7>
WDT, PWRT, FSCM
and Two-Speed Start-up
Note 1: Operates only when HFINTOSC is the primary oscillator.
© 2007 Microchip Technology Inc.
Advance Information
DS41303B-page 25
PIC18F2XK20/4XK20
2.2.4
CLOCK STATUS
2.2
Oscillator Control
The OSTS and IOFS bits of the OSCCON register, and
the T1RUN bit of the T1CON register, indicate which
clock source is currently providing the main clock. The
OSTS bit indicates that the Oscillator Start-up Timer
has timed out and the primary clock is providing the
device clock. The IOFS bit indicates when the internal
oscillator block has stabilized and is providing the
device clock in HFINTOSC Clock modes. The IOFS
and OSTS Status bits will both be set when
SCS<1:0> = 00 and HFINTOSC is the primary clock.
The T1RUN bit indicates when the Timer1 oscillator is
providing the device clock in secondary clock modes.
When SCS<1:0> ≠ 00, only one of these three bits will
be set at any time. If none of these bits are set, the
LFINTOSC is providing the clock or the HFINTOSC has
just started and is not yet stable.
The OSCCON register (Register 2-1) controls several
aspects of the device clock’s operation, both in full
power operation and in power-managed modes.
• Main System Clock Selection (SCS)
• Internal Frequency selection bits (IRCF)
• Clock Status bits (OSTS, IOFS)
• Power management selection (IDLEN)
2.2.1
MAIN SYSTEM CLOCK SELECTION
The System Clock Select bits, SCS<1:0>, select the
main clock source. The available clock sources are
• Primary clock defined by the FOSC<3:0> bits of
CONFIG1H. The primary clock can be the primary
oscillator, an external clock, or the internal oscilla-
tor block.
2.2.5
POWER MANAGEMENT
• Secondary clock (Timer1 oscillator)
• Internal oscillator block (HFINTOSC and
LFINTOSC).
The IDLEN bit of the OSCCON register determines if
the device goes into Sleep mode or one of the Idle
modes when the SLEEPinstruction is executed.
The clock source changes immediately after one or
more of the bits is written to, following a brief clock tran-
sition interval. The SCS bits are cleared to select the
primary clock on all forms of Reset.
The use of the flag and control bits in the OSCCON
register is discussed in more detail in Section 3.0
“Power-Managed Modes”.
Note 1: The Timer1 oscillator must be enabled to
select the secondary clock source. The
Timer1 oscillator is enabled by setting the
T1OSCEN bit of the T1CON register. If
the Timer1 oscillator is not enabled, then
the main oscillator will continue to run
from the previously selected source. The
source will then switch to the secondary
oscillator after the T1OSCEN bit is set.
2.2.2
INTERNAL FREQUENCY
SELECTION
The Internal Oscillator Frequency Select bits
(IRCF<2:0>) select the frequency output of the internal
oscillator block. The choices are the LFINTOSC source
(31 kHz), the HFINTOSC source (16 MHz) or one of
the frequencies derived from the HFINTOSC
postscaler (31.25 kHz to 8 MHz). If the internal oscilla-
tor block is supplying the main clock, changing the
states of these bits will have an immediate change on
the internal oscillator’s output. On device Resets, the
output frequency of the internal oscillator is set to the
default frequency of 1 MHz.
2: It is recommended that the Timer1
oscillator be operating and stable before
selecting the secondary clock source or a
very long delay may occur while the
Timer1 oscillator starts.
2.2.3
LOW FREQUENCY SELECTION
2.2.6
OSCILLATOR TRANSITIONS
When a nominal output frequency of 31 kHz is selected
(IRCF<2:0> = 000), users may choose which internal
oscillator acts as the source. This is done with the
INTSRC bit of the OSCTUNE register. Setting this bit
selects the HFINTOSC as a 31.25 kHz clock source by
enabling the divide-by-512 output of the HFINTOSC
postscaler. Clearing INTSRC selects LFINTOSC (nom-
inally 31 kHz) as the clock source.
PIC18F2XK20/4XK20 devices contain circuitry to pre-
vent clock “glitches” when switching between clock
sources. A short pause in the device clock occurs dur-
ing the clock switch. The length of this pause is the sum
of two cycles of the old clock source and three to four
cycles of the new clock source. This formula assumes
that the new clock source is stable.
This option allows users to select the tunable and more
precise HFINTOSC as a clock source, while maintain-
ing power savings with a very low clock speed. Regard-
less of the setting of INTSRC, LFINTOSC always
remains the clock source for features such as the
Watchdog Timer and the Fail-Safe Clock Monitor.
Clock transitions are discussed in greater detail in
Section 3.1.2 “Entering Power-Managed Modes”.
DS41303B-page 26
Advance Information
© 2007 Microchip Technology Inc.
PIC18F2XK20/4XK20
REGISTER 2-1:
OSCCON: OSCILLATOR CONTROL REGISTER
R/W-0
IDLEN
bit 7
R/W-0
IRCF2
R/W-1
IRCF1
R/W-1
IRCF0
R-q
OSTS(1)
R-0
R/W-0
SCS1
R/W-0
SCS0
IOFS
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
q = depends on condition
x = Bit is unknown
bit 7
IDLEN: Idle Enable bit
1= Device enters Idle mode on SLEEPinstruction
0= Device enters Sleep mode on SLEEPinstruction
bit 6-4
IRCF<2:0>: Internal Oscillator Frequency Select bits
111= 16 MHz (HFINTOSC drives clock directly)
110= 8 MHz
101= 4 MHz
100= 2 MHz
011= 1 MHz(3)
010= 500 kHz
001= 250 kHz
000= 31 kHz (from either HFINTOSC/512 or LFINTOSC directly)(2)
bit 3
OSTS: Oscillator Start-up Time-out Status bit(1)
1= Device is running from the clock defined by FOSC<2:0> of the CONFIG1 register
0= Device is running from the internal oscillator (HFINTOSC or LFINTOSC)
bit 2
IOFS: HFINTOSC Frequency Stable bit
1= HFINTOSC frequency is stable
0= HFINTOSC frequency is not stable
bit 1-0
SCS<1:0>: System Clock Select bits
1x= Internal oscillator block
01= Secondary (Timer1) oscillator
00= Primary clock (determined by CONFIG1H[FOSC<3:0>]).
Note 1: Reset state depends on state of the IESO Configuration bit.
2: Source selected by the INTSRC bit of the OSCTUNE register, see text.
3: Default output frequency of HFINTOSC on Reset.
© 2007 Microchip Technology Inc.
Advance Information
DS41303B-page 27
PIC18F2XK20/4XK20
2.3
Clock Source Modes
2.4
External Clock Modes
Clock Source modes can be classified as external or
internal.
2.4.1 OSCILLATOR START-UP TIMER (OST)
When the Oscillator module is configured for LP, XT or
HS modes, the Oscillator Start-up Timer (OST) counts
1024 oscillations from OSC1. This occurs following a
Power-on Reset (POR) and when the Power-up Timer
(PWRT) has expired (if configured), or a wake-up from
Sleep. During this time, the program counter does not
increment and program execution is suspended. The
OST ensures that the oscillator circuit, using a quartz
crystal resonator or ceramic resonator, has started and
is providing a stable system clock to the Oscillator
module. When switching between clock sources, a
delay is required to allow the new clock to stabilize.
These oscillator delays are shown in Table 2-1.
• External Clock modes rely on external circuitry for
the clock source. Examples are: Clock modules
(EC mode), quartz crystal resonators or ceramic
resonators (LP, XT and HS modes) and Resistor-
Capacitor (RC mode) circuits.
• Internal clock sources are contained internally
within the Oscillator block. The Oscillator block
has two internal oscillators: the 16 MHz High-
Frequency Internal Oscillator (HFINTOSC) and
the 31 kHz Low-Frequency Internal Oscillator
(LFINTOSC).
The system clock can be selected between external or
internal clock sources via the System Clock Select
(SCS<1:0>) bits of the OSCCON register. See
Section 2.9 “Clock Switching” for additional informa-
tion.
In order to minimize latency between external oscillator
start-up and code execution, the Two-Speed Clock
Start-up mode can be selected (see Section 2.10
“Two-Speed Clock Start-up Mode”).
TABLE 2-1:
OSCILLATOR DELAY EXAMPLES
Switch From
Switch To
Frequency
Oscillator Delay
LFINTOSC
HFINTOSC
31 kHz
250 kHz to 16 MHz
Sleep/POR
Oscillator Warm-Up Delay (TWARM)
Sleep/POR
LFINTOSC (31 kHz)
Sleep/POR
EC, RC
EC, RC
DC – 64 MHz
DC – 64 MHz
2 instruction cycles
1 cycle of each
LP, XT, HS
HSPLL
32 kHz to 40 MHz
32 MHz to 64 MHz
250 kHz to 16 MHz
1024 Clock Cycles (OST)
1024 Clock Cycles (OST) + 2 ms
1 μs (approx.)
Sleep/POR
LFINTOSC (31 kHz)
HFINTOSC
2.4.2
EC MODE
FIGURE 2-2:
EXTERNAL CLOCK (EC)
MODE OPERATION
The External Clock (EC) mode allows an externally
generated logic level as the system clock source. When
operating in this mode, an external clock source is
connected to the OSC1 input and the OSC2 is available
for general purpose I/O. Figure 2-2 shows the pin
connections for EC mode.
OSC1/CLKIN
Clock from
Ext. System
PIC® MCU
(1)
I/O
OSC2/CLKOUT
The Oscillator Start-up Timer (OST) is disabled when
EC mode is selected. Therefore, there is no delay in
operation after a Power-on Reset (POR) or wake-up
from Sleep. Because the PIC® MCU design is fully
static, stopping the external clock input will have the
effect of halting the device while leaving all data intact.
Upon restarting the external clock, the device will
resume operation as if no time had elapsed.
Note 1: Alternate pin functions are listed in
Section 1.0 “Device Overview”.
DS41303B-page 28
Advance Information
© 2007 Microchip Technology Inc.
PIC18F2XK20/4XK20
2.4.3
LP, XT, HS MODES
Note 1: Quartz crystal characteristics vary according
to type, package and manufacturer. The
user should consult the manufacturer data
sheets for specifications and recommended
application.
The LP, XT and HS modes support the use of quartz
crystal resonators or ceramic resonators connected to
OSC1 and OSC2 (Figure 2-3). The mode selects a low,
medium or high gain setting of the internal inverter-
amplifier to support various resonator types and speed.
2: Always verify oscillator performance over
the VDD and temperature range that is
expected for the application.
LP Oscillator mode selects the lowest gain setting of the
internal inverter-amplifier. LP mode current consumption
is the least of the three modes. This mode is best suited
to drive resonators with a low drive level specification, for
example, tuning fork type crystals.
3: For oscillator design assistance, reference
the following Microchip Applications Notes:
• AN826, “Crystal Oscillator Basics and
Crystal Selection for rfPIC® and PIC®
Devices” (DS00826)
• AN849, “Basic PIC® Oscillator Design”
(DS00849)
• AN943, “Practical PIC® Oscillator
XT Oscillator mode selects the intermediate gain
setting of the internal inverter-amplifier. XT mode
current consumption is the medium of the three modes.
This mode is best suited to drive resonators with a
medium drive level specification.
HS Oscillator mode selects the highest gain setting of the
internal inverter-amplifier. HS mode current consumption
is the highest of the three modes. This mode is best
suited for resonators that require a high drive setting.
Analysis and Design” (DS00943)
• AN949, “Making Your Oscillator Work”
(DS00949)
Figure 2-3 and Figure 2-4 show typical circuits for
quartz crystal and ceramic resonators, respectively.
FIGURE 2-4:
CERAMIC RESONATOR
OPERATION
(XT OR HS MODE)
FIGURE 2-3:
QUARTZ CRYSTAL
OPERATION (LP, XT OR
HS MODE)
PIC® MCU
OSC1/CLKIN
PIC® MCU
C1
To Internal
Logic
OSC1/CLKIN
(3)
(2)
RP
RF
C1
Sleep
To Internal
Logic
Quartz
Crystal
(2)
RF
Sleep
OSC2/CLKOUT
(1)
C2
RS
Ceramic
Resonator
OSC2/CLKOUT
(1)
C2
RS
Note 1: A series resistor (RS) may be required for
ceramic resonators with low drive level.
Note 1: A series resistor (RS) may be required for
2: The value of RF varies with the Oscillator mode
selected (typically between 2 MΩ to 10 MΩ).
quartz crystals with low drive level.
2: The value of RF varies with the Oscillator mode
selected (typically between 2 MΩ to 10 MΩ).
3: An additional parallel feedback resistor (RP)
may be required for proper ceramic resonator
operation.
© 2007 Microchip Technology Inc.
Advance Information
DS41303B-page 29
PIC18F2XK20/4XK20
2.4.4
EXTERNAL RC MODES
2.5
Internal Clock Modes
The external Resistor-Capacitor (RC) modes support
the use of an external RC circuit. This allows the
designer maximum flexibility in frequency choice while
keeping costs to a minimum when clock accuracy is not
required. There are two modes: RC and RCIO.
The Oscillator module has two independent, internal
oscillators that can be configured or selected as the
system clock source.
1. The HFINTOSC (High-Frequency Internal
Oscillator) is factory calibrated and operates at
16 MHz. The frequency of the HFINTOSC can
be user-adjusted via software using the
OSCTUNE register (Register 2-2).
2.4.4.1
RC Mode
In RC mode, the RC circuit connects to OSC1. OSC2/
CLKOUT outputs the RC oscillator frequency divided
by 4. This signal may be used to provide a clock for
external circuitry, synchronization, calibration, test or
other application requirements. Figure 2-5 shows the
external RC mode connections.
2. The LFINTOSC (Low-Frequency Internal
Oscillator) operates at 31 kHz.
The system clock speed can be selected via software
using the Internal Oscillator Frequency Select bits
IRCF<2:0> of the OSCCON register.
FIGURE 2-5:
EXTERNAL RC MODES
The system clock can be selected between external or
internal clock sources via the System Clock Selection
(SCS<1:0>) bits of the OSCCON register. See
Section 2.9 “Clock Switching” for more information.
VDD
PIC® MCU
REXT
2.5.1 INTOSC AND INTOSCIO MODES
OSC1/CLKIN
Internal
Clock
The INTOSC and INTOSCIO modes configure the
internal oscillators as the primary clock source.The
FOSC<3:0> bits in the CONFIG1H Configuration
register determine which mode is selected. See
Section 23.0 “Special Features of the CPU” for more
information.
CEXT
VSS
(1)
FOSC/4 or
OSC2/CLKOUT
(2)
I/O
In INTOSC mode, OSC1/CLKIN is available for general
purpose I/O. OSC2/CLKOUT outputs the selected
internal oscillator frequency divided by 4. The CLKOUT
signal may be used to provide a clock for external
circuitry, synchronization, calibration, test or other
application requirements.
Recommended values: 10 kΩ ≤ REXT ≤ 100 kΩ
CEXT > 20 pF
Note 1: Alternate pin functions are listed in
Section 1.0 “Device Overview”.
2: Output depends upon RC or RCIO clock mode.
In INTOSCIO mode, OSC1/CLKIN and OSC2/CLKOUT
are available for general purpose I/O.
2.4.4.2
RCIO Mode
2.5.2
HFINTOSC
In RCIO mode, the RC circuit is connected to OSC1.
OSC2 becomes an additional general purpose I/O pin.
The output of the HFINTOSC connects to a postscaler
and multiplexer (see Figure 2-1). One of eight
frequencies can be selected via software using the
IRCF<2:0> bits of the OSCCON register. See
Section 2.5.4 “Frequency Select Bits (IRCF)” for
more information.
The RC oscillator frequency is a function of the supply
voltage, the resistor (REXT) and capacitor (CEXT) values
and the operating temperature. Other factors affecting
the oscillator frequency are:
• input threshold voltage variation
• component tolerances
• packaging variations in capacitance
The HFINTOSC is enabled when:
• SCS1 = 1and IRCF<2:0> ≠ 000
• SCS1 = 1and IRCF<2:0> = 000and INTSRC = 1
The user also needs to take into account variation due
to tolerance of external RC components used.
• IESO bit of CONFIG1H = 1enabling Two-Speed
Start-up.
• FCMEM bit of CONFIG1H = 1enabling Two-
Speed Start-up and Fail-Safe mode.
• FOSC<3:0> of CONFIG1H selects the internal
oscillator as the primary clock
The HF Internal Oscillator (IOFS) bit of the OSCCON
register indicates whether the HFINTOSC is stable or not.
DS41303B-page 30
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© 2007 Microchip Technology Inc.
PIC18F2XK20/4XK20
(PWRT), Watchdog Timer (WDT), Fail-Safe Clock Mon-
itor (FSCM) and peripherals, are not affected by the
change in frequency.
2.5.2.1
OSCTUNE Register
The HFINTOSC is factory calibrated but can be
adjusted in software by writing to the TUN<5:0> bits of
the OSCTUNE register (Register 2-2).
The OSCTUNE register also implements the INTSRC
and PLLEN bits, which control certain features of the
internal oscillator block.
The default value of the TUN<5:0> is ‘000000’. The
value is a 6-bit two’s complement number.
The INTSRC bit allows users to select which internal
oscillator provides the clock source when the 31 kHz
frequency option is selected. This is covered in greater
detail in Section 2.2.3 “Low Frequency Selection”.
When the OSCTUNE register is modified, the
HFINTOSC frequency will begin shifting to the new
frequency. Code execution continues during this shift.
There is no indication that the shift has occurred.
The PLLEN bit controls the operation of the frequency
multiplier, PLL, in internal oscillator modes. For more
details about the function of the PLLEN bit see
Section 2.6.2 “PLL in HFINTOSC Modes”
OSCTUNE does not affect the LFINTOSC frequency.
Operation of features that depend on the LFINTOSC
clock source frequency, such as the Power-up Timer
REGISTER 2-2:
OSCTUNE: OSCILLATOR TUNING REGISTER
R/W-0
INTSRC
bit 7
R/W-0
PLLEN(1)
R/W-0
TUN5
R/W-0
TUN4
R/W-0
TUN3
R/W-0
TUN2
R/W-0
TUN1
R/W-0
TUN0
bit 0
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
-n = Value at POR
bit 7
bit 6
INTSRC: Internal Oscillator Low-Frequency Source Select bit
1= 31.25 kHz device clock derived from 16 MHz HFINTOSC source (divide-by-512 enabled)
0= 31 kHz device clock derived directly from LFINTOSC internal oscillator
PLLEN: Frequency Multiplier PLL for HFINTOSC Enable bit(1)
1= PLL enabled for HFINTOSC (8 MHz and 16 MHz only)
0= PLL disabled
bit 5-0
TUN<5:0>: Frequency Tuning bits
011111= Maximum frequency
011110=
• • •
000001=
000000= Oscillator module is running at the factory calibrated frequency.
111111=
• • •
100000= Minimum frequency
Note 1: The PLLEN bit is active only when the HFINTOSC is the primary clock source (FOSC<2:0> = 100X) and
the selected frequency is 8 MHz or 16 MHz. Otherwise, the PLLEN bit is unavailable and always reads ‘0’.
© 2007 Microchip Technology Inc.
Advance Information
DS41303B-page 31
PIC18F2XK20/4XK20
2.5.3
LFINTOSC
2.5.5
HFINTOSC FREQUENCY DRIFT
The Low-Frequency Internal Oscillator (LFINTOSC) is
a 31 kHz internal clock source.
The factory calibrates the internal oscillator block output
(HFINTOSC) for 16 MHz. However, this frequency may
drift as VDD or temperature changes, which can affect the
controller operation in a variety of ways. It is possible to
adjust the HFINTOSC frequency by modifying the value
of the TUN<5:0> bits in the OSCTUNE register. This has
no effect on the LFINTOSC clock source frequency.
The output of the LFINTOSC connects to internal
oscillator block frequency selection multiplexer (see
Figure 2-1). Select 31 kHz, via software, using the
IRCF<2:0> bits of the OSCCON register and the
INTSRC bit of the OSCTUNE register. See
Section 2.5.4 “Frequency Select Bits (IRCF)” for
more information. The LFINTOSC is also the frequency
for the Power-up Timer (PWRT), Watchdog Timer
(WDT) and Fail-Safe Clock Monitor (FSCM).
Tuning the HFINTOSC source requires knowing when to
make the adjustment, in which direction it should be
made and in some cases, how large a change is
needed. Three possible compensation techniques are
discussed in the following sections, however other tech-
niques may be used.
The LFINTOSC is enabled when any of the following
are enabled:
• IRCF<2:0> bits of the OSCCON register = 000and
INTSRC bit of the OSCTUNE register = 1
2.5.5.1
Compensating with the USART
An adjustment may be required when the USART
begins to generate framing errors or receives data with
errors while in Asynchronous mode. Framing errors
indicate that the device clock frequency is too high; to
adjust for this, decrement the value in OSCTUNE to
reduce the clock frequency. On the other hand, errors
in data may suggest that the clock speed is too low; to
compensate, increment OSCTUNE to increase the
clock frequency.
• Power-up Timer (PWRT)
• Watchdog Timer (WDT)
• Fail-Safe Clock Monitor (FSCM)
2.5.4
FREQUENCY SELECT BITS (IRCF)
The output of the 16 MHz HFINTOSC and 31 kHz
LFINTOSC connects to a postscaler and multiplexer
(see Figure 2-1). The Internal Oscillator Frequency
Select bits IRCF<2:0> of the OSCCON register select
the output frequency of the internal oscillators. One of
eight frequencies can be selected via software:
2.5.5.2
Compensating with the Timers
This technique compares device clock speed to some
reference clock. Two timers may be used; one timer is
clocked by the peripheral clock, while the other is
clocked by a fixed reference source, such as the
Timer1 oscillator.
• 16 MHz
• 8 MHz
• 4 MHz
• 2 MHz
Both timers are cleared, but the timer clocked by the
reference generates interrupts. When an interrupt
occurs, the internally clocked timer is read and both
timers are cleared. If the internally clocked timer value
is greater than expected, then the internal oscillator
block is running too fast. To adjust for this, decrement
the OSCTUNE register.
• 1 MHz (Default after Reset)
• 500 kHz
• 250 kHz
• 31 kHz (LFINTOSC or HFINTOSC/512)
Note:
Following any Reset, the IRCF<2:0> bits of
the OSCCON register are set to ‘011’ and
the frequency selection is set to 1 MHz.
The user can modify the IRCF bits to
select a different frequency.
2.5.5.3
Compensating with the CCP Module
in Capture Mode
A CCP module can use free running Timer1 (or Timer3),
clocked by the internal oscillator block and an external
event with a known period (i.e., AC power frequency).
The time of the first event is captured in the
CCPRxH:CCPRxL registers and is recorded for use later.
When the second event causes a capture, the time of the
first event is subtracted from the time of the second
event. Since the period of the external event is known,
the time difference between events can be calculated.
If the measured time is much greater than the calcu-
lated time, the internal oscillator block is running too
fast; to compensate, decrement the OSCTUNE register.
If the measured time is much less than the calculated
time, the internal oscillator block is running too slow; to
compensate, increment the OSCTUNE register.
DS41303B-page 32
Advance Information
© 2007 Microchip Technology Inc.
PIC18F2XK20/4XK20
2.6.2
PLL IN HFINTOSC MODES
2.6
PLL Frequency Multiplier
The 4x frequency multiplier can be used with the inter-
nal oscillator block to produce faster device clock
speeds than are normally possible with an internal
oscillator. When enabled, the PLL produces a clock
speed of up to 64 MHz.
A Phase Locked Loop (PLL) circuit is provided as an
option for users who wish to use a lower frequency
oscillator circuit or to clock the device up to its highest
rated frequency from the crystal oscillator. This may be
useful for customers who are concerned with EMI due
to high-frequency crystals or users who require higher
clock speeds from an internal oscillator. There are
three conditions when the PLL can be used:
Unlike HSPLL mode, the PLL is controlled through
software. The PLLEN control bit of the OSCTUNE
register is used to enable or disable the PLL operation
when the HFINTOSC is used.
• When the primary clock is HSPLL
The PLL is available when the device is configured to
use the internal oscillator block as its primary clock
source (FOSC<3:0> = 1001or 1000). Additionally, the
PLL will only function when the selected output fre-
quency is either 8 MHz or 16 MHz (OSCCON<6:4> =
111or 110). If both of these conditions are not met, the
PLL is disabled.
• When the primary clock is HFINTOSC and the
selected frequency is 16 MHz
• When the primary clock is HFINTOSC and the
selected frequency is 8 MHz
2.6.1
HSPLL OSCILLATOR MODE
The HSPLL mode makes use of the HS mode oscillator
for frequencies up to 16 MHz. A PLL then multiplies the
oscillator output frequency by 4 to produce an internal
clock frequency up to 64 MHz. The PLLEN bit of the
OSCTUNE register is active only when the HFINTOSC
is the primary clock and is not available in HSPLL oscil-
lator mode.
The PLLEN control bit is only functional in those inter-
nal oscillator modes where the PLL is available. In all
other modes, it is forced to ‘0’ and is effectively
unavailable.
The PLL is only available to the primary oscillator when
the FOSC<3:0> Configuration bits are programmed for
HSPLL mode (= 0110).
FIGURE 2-6:
PLL BLOCK DIAGRAM
(HS MODE)
HS Oscillator Enable
PLL Enable
(from Configuration Register 1H)
OSC2
OSC1
Phase
Comparator
HS Mode
Crystal
Osc
FIN
FOUT
Loop
Filter
÷4
VCO
SYSCLK
© 2007 Microchip Technology Inc.
Advance Information
DS41303B-page 33
PIC18F2XK20/4XK20
2.7
Effects of Power-Managed Modes
on the Various Clock Sources
2.8
Power-up Delays
Power-up delays are controlled by two timers, so that
no external Reset circuitry is required for most applica-
tions. The delays ensure that the device is kept in
Reset until the device power supply is stable under nor-
mal circumstances and the primary clock is operating
and stable. For additional information on power-up
delays, see Section 4.5 “Device Reset Timers”.
For more information about the modes discussed in this
section see Section 3.0 “Power-Managed Modes”. A
quick reference list is also available in Table 3-1.
When PRI_IDLE mode is selected, the designated pri-
mary oscillator continues to run without interruption.
For all other power-managed modes, the oscillator
using the OSC1 pin is disabled. The OSC1 pin (and
OSC2 pin, if used by the oscillator) will stop oscillating.
The first timer is the Power-up Timer (PWRT), which
provides a fixed delay on power-up (parameter 33,
Table 26-9). It is enabled by clearing (= 0) the
PWRTEN Configuration bit.
In secondary clock modes (SEC_RUN and
SEC_IDLE), the Timer1 oscillator is operating and
providing the device clock. The Timer1 oscillator may
also run in all power-managed modes if required to
clock Timer1 or Timer3.
The second timer is the Oscillator Start-up Timer
(OST), intended to keep the chip in Reset until the
crystal oscillator is stable (LP, XT and HS modes). The
OST does this by counting 1024 oscillator cycles
before allowing the oscillator to clock the device.
In internal oscillator modes (INTOSC_RUN and
INTOSC_IDLE), the internal oscillator block provides
the device clock source. The 31 kHz LFINTOSC output
can be used directly to provide the clock and may be
enabled to support various special features, regardless
of the power-managed mode (see Section 23.2
“Watchdog Timer (WDT)”, Section 2.10 “Two-
Speed Clock Start-up Mode” and Section 2.11 “Fail-
Safe Clock Monitor” for more information on WDT,
Fail-Safe Clock Monitor and Two-Speed Start-up). The
HFINTOSC output at 16 MHz may be used directly to
clock the device or may be divided down by the
postscaler. The HFINTOSC output is disabled if the
clock is provided directly from the LFINTOSC output.
When the HSPLL Oscillator mode is selected, the
device is kept in Reset for an additional 2 ms, following
the HS mode OST delay, so the PLL can lock to the
incoming clock frequency.
There is a delay of interval TCSD (parameter 38,
Table 26-9), following POR, while the controller
becomes ready to execute instructions. This delay runs
concurrently with any other delays. This may be the
only delay that occurs when any of the EC, RC or INTIO
modes are used as the primary clock source.
When the HFINTOSC is selected as the primary clock,
the main system clock can be delayed until the
HFINTOSC is stable. This is user selectable by the
HFOFST bit of the CONFIG3H Configuration register.
When the HFOFST bit is cleared the main system clock
is delayed until the HFINTOSC is stable. When the
HFOFST bit is set the main system clock starts imme-
diately. In either case the IOFS bit of the OSCCON reg-
ister can be read to determine whether the HFINTOSC
is operating and stable.
If the Sleep mode is selected, all clock sources are
stopped. Since all the transistor switching currents
have been stopped, Sleep mode achieves the lowest
current consumption of the device (only leakage
currents).
Enabling any on-chip feature that will operate during
Sleep will increase the current consumed during Sleep.
The LFINTOSC is required to support WDT operation.
The Timer1 oscillator may be operating to support a
real-time clock. Other features may be operating that
do not require a device clock source (i.e., SSP slave,
PSP, INTn pins and others). Peripherals that may add
significant current consumption are listed in
Section 26.8 “DC Characteristics”.
TABLE 2-2:
OSC1 AND OSC2 PIN STATES IN SLEEP MODE
OSC1 Pin
OSC Mode
OSC2 Pin
RC, INTOSC
RCIO
Floating, external resistor should pull high
Floating, external resistor should pull high
Configured as PORTA, bit 7
At logic low (clock/4 output)
Configured as PORTA, bit 6
Configured as PORTA, bit 6
Configured as PORTA, bit 6
At logic low (clock/4 output)
INTOSCIO
ECIO
Floating, pulled by external clock
Floating, pulled by external clock
EC
LP, XT, HS and HSPLL
Feedback inverter disabled at quiescent
voltage level
Feedback inverter disabled at quiescent
voltage level
Note:
See Table 4-2 in Section 4.0 “Reset” for time-outs due to Sleep and MCLR Reset.
DS41303B-page 34
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© 2007 Microchip Technology Inc.
PIC18F2XK20/4XK20
2.9
Clock Switching
2.10 Two-Speed Clock Start-up Mode
The system clock source can be switched between
external and internal clock sources via software using
the System Clock Select (SCS<1:0>) bits of the
OSCCON register.
Two-Speed Start-up mode provides additional power
savings by minimizing the latency between external
oscillator start-up and code execution. In applications
that make heavy use of the Sleep mode, Two-Speed
Start-up will remove the external oscillator start-up
time from the time spent awake and can reduce the
overall power consumption of the device.
2.9.1
SYSTEM CLOCK SELECT
(SCS<1:0>) BITS
The System Clock Select (SCS<1:0>) bits of the OSC-
CON register select the system clock source that is
used for the CPU and peripherals.
This mode allows the application to wake-up from
Sleep, perform a few instructions using the HFINTOSC
as the clock source and go back to Sleep without
waiting for the primary oscillator to become stable.
• When SCS<1:0> = 00, the system clock source is
determined by configuration of the FOSC<2:0>
bits in the CONFIG1H Configuration register.
Note:
Executing a SLEEP instruction will abort
the oscillator start-up time and will cause
the OSTS bit of the OSCCON register to
remain clear.
• When SCS<1:0> = 10, the system clock source is
chosen by the internal oscillator frequency
selected by the INTSRC bit of the OSCTUNE
register and the IRCF<2:0> bits of the OSCCON
register.
When the Oscillator module is configured for LP, XT or
HS modes, the Oscillator Start-up Timer (OST) is
enabled (see Section 2.4.1 “Oscillator Start-up Timer
(OST)”). The OST will suspend program execution until
1024 oscillations are counted. Two-Speed Start-up
mode minimizes the delay in code execution by
operating from the internal oscillator as the OST is
counting. When the OST count reaches 1024 and the
OSTS bit of the OSCCON register is set, program
execution switches to the external oscillator.
• When SCS<1:0> = 01, the system clock source is
the 32.768 kHz secondary oscillator shared with
Timer1.
After a Reset, the SCS<1:0> bits of the OSCCON
register are always cleared.
Note:
Any automatic clock switch, which may
occur from Two-Speed Start-up or Fail-Safe
Clock Monitor, does not update the
SCS<1:0> bits of the OSCCON register.
The user can monitor the T1RUN bit of the
T1CON register and the IOFS and OSTS
bits of the OSCCON register to determine
the current system clock source.
2.10.1
TWO-SPEED START-UP MODE
CONFIGURATION
Two-Speed Start-up mode is enabled when all of the
following settings are configured as noted:
• Two-Speed Start-up mode is enabled by setting
the IESO of the CONFIG1H Configuration register
is set. Fail-Safe mode (FCMEM=1) also enables
two-speed by default.
2.9.2
OSCILLATOR START-UP TIME-OUT
STATUS (OSTS) BIT
• SCS<1:0> (of the OSCCON register) = 00.
The Oscillator Start-up Time-out Status (OSTS) bit of
the OSCCON register indicates whether the system
clock is running from the external clock source, as
defined by the FOSC<3:0> bits in the CONFIG1H
Configuration register, or from the internal clock
source. In particular, when the primary oscillator is the
source of the primary clock, OSTS indicates that the
Oscillator Start-up Timer (OST) has timed out for LP,
XT or HS modes.
• FOSC<2:0> bits of the CONFIG1H Configuration
register are configured for LP, XT or HS mode.
Two-Speed Start-up mode becomes active after:
• Power-on Reset (POR) and, if enabled, after
Power-up Timer (PWRT) has expired, or
• Wake-up from Sleep.
If the external clock oscillator is configured to be
anything other than LP, XT or HS mode, then Two-
Speed Start-up is disabled. This is because the external
clock oscillator does not require any stabilization time
after POR or an exit from Sleep.
© 2007 Microchip Technology Inc.
Advance Information
DS41303B-page 35
PIC18F2XK20/4XK20
2.10.2
TWO-SPEED START-UP
SEQUENCE
2.10.4
CLOCK SWITCH TIMING
When switching between one oscillator and another,
the new oscillator may not be operating which saves
power (see Figure 2-7). If this is the case, there is a
delay after the IRCF<2:0> bits of the OSCCON register
are modified before the frequency change takes place.
The OSTS and IOFS bits of the OSCCON register will
reflect the current active status of the external and
HFINTOSC oscillators. The timing of a frequency
selection is as follows:
1. Wake-up from Power-on Reset or Sleep.
2. Instructions begin executing by the internal
oscillator at the frequency set in the IRCF<2:0>
bits of the OSCCON register.
3. OST enabled to count 1024 external clock
cycles.
4. OST timed out. External clock is ready.
5. OSTS is set.
1. IRCF<2:0> bits of the OSCCON register are
modified.
6. Clock switch finishes according to FIGURE 2-7:
“Clock Switch Timing”
2. The old clock continues to operate until the new
clock is ready.
2.10.3
CHECKING TWO-SPEED CLOCK
STATUS
3. Clock switch circuitry waits for two consecutive
rising edges of the old clock after the new clock
ready signal goes true.
Checking the state of the OSTS bit of the OSCCON
register will confirm if the microcontroller is running
from the external clock source, as defined by the
FOSC<2:0> bits in CONFIG1H Configuration register,
or the internal oscillator. OSTS = 0when the external
oscillator is not ready, which indicates that the system
is running from the internal oscillator.
4. The system clock is held low starting at the next
falling edge of the old clock.
5. Clock switch circuitry waits for an additional two
rising edges of the new clock.
6. On the next falling edge of the new clock the low
hold on the system clock is released and new
clock is switched in as the system clock.
7. Clock switch is complete.
See Figure 2-1 for more details.
If the HFINTOSC is the source of both the old and new
frequency, there is no start-up delay before the new
frequency is active. This is because the old and new
frequencies are derived from the HFINTOSC via the
postscaler and multiplexer.
Start-up delay specifications are located in
Section 26.0 “Electrical Characteristics”, under AC
Specifications (Oscillator Module).
DS41303B-page 36
Advance Information
© 2007 Microchip Technology Inc.
PIC18F2XK20/4XK20
FIGURE 2-7:
High Speed
CLOCK SWITCH TIMING
Low Speed
Old Clock
(1)
Start-up Time
Clock Sync
Running
New Clock
New Clk Ready
IRCF <2:0>
Select Old
Select New
System Clock
Low Speed
High Speed
Old Clock
(1)
Start-up Time
Clock Sync
Running
New Clock
New Clk Ready
IRCF <2:0>
Select Old
Select New
System Clock
Note 1: Start-up time includes TOST (1024 TOSC) for external clocks, plus TPLL (approx. 2 ms) for HSPLL mode.
© 2007 Microchip Technology Inc.
Advance Information
DS41303B-page 37
PIC18F2XK20/4XK20
2.11.3
FAIL-SAFE CONDITION CLEARING
2.11 Fail-Safe Clock Monitor
The Fail-Safe condition is cleared by either one of the
following:
The Fail-Safe Clock Monitor (FSCM) allows the device
to continue operating should the external oscillator fail.
The FSCM can detect oscillator failure any time after
the Oscillator Start-up Timer (OST) has expired. The
FSCM is enabled by setting the FCMEN bit in the
CONFIG1H Configuration register. The FSCM is
applicable to all external oscillator modes (LP, XT, HS,
EC, RC and RCIO).
• Any Reset
• By toggling the SCS1 bit of the OSCCON register
Both of these conditions restart the OST. While the
OST is running, the device continues to operate from
the INTOSC selected in OSCCON. When the OST
times out, the Fail-Safe condition is cleared and the
device automatically switches over to the external clock
source. The Fail-Safe condition need not be cleared
before the OSCFIF flag is cleared.
FIGURE 2-8:
FSCM BLOCK DIAGRAM
Clock Monitor
Latch
External
Clock
2.11.4
RESET OR WAKE-UP FROM SLEEP
S
Q
The FSCM is designed to detect an oscillator failure
after the Oscillator Start-up Timer (OST) has expired.
The OST is used after waking up from Sleep and after
any type of Reset. The OST is not used with the EC or
RC Clock modes so that the FSCM will be active as
soon as the Reset or wake-up has completed. When
the FSCM is enabled, the Two-Speed Start-up is also
enabled. Therefore, the device will always be executing
code while the OST is operating.
LFINTOSC
Oscillator
÷ 64
R
Q
31 kHz
(~32 μs)
488 Hz
(~2 ms)
Sample Clock
Clock
Failure
Note:
Due to the wide range of oscillator start-up
times, the Fail-Safe circuit is not active
during oscillator start-up (i.e., after exiting
Reset or Sleep). After an appropriate
amount of time, the user should check the
OSTS bit of the OSCCON register to verify
the oscillator start-up and that the system
Detected
2.11.1
FAIL-SAFE DETECTION
The FSCM module detects a failed oscillator by
comparing the external oscillator to the FSCM sample
clock. The sample clock is generated by dividing the
LFINTOSC by 64. See Figure 2-8. Inside the fail
detector block is a latch. The external clock sets the
latch on each falling edge of the external clock. The
sample clock clears the latch on each rising edge of the
sample clock. A failure is detected when an entire half-
cycle of the sample clock elapses before the primary
clock goes low.
clock
switchover
has
successfully
completed.
2.11.2
FAIL-SAFE OPERATION
When the external clock fails, the FSCM switches the
device clock to an internal clock source and sets the bit
flag OSCFIF of the PIR2 register. The OSCFIF flag will
generate an interrupt if the OSCFIE bit of the PIE2
register is also set. The device firmware can then take
steps to mitigate the problems that may arise from a
failed clock. The system clock will continue to be
sourced from the internal clock source until the device
firmware successfully restarts the external oscillator
and switches back to external operation. An automatic
transition back to the failed clock source will not occur.
The internal clock source chosen by the FSCM is
determined by the IRCF<2:0> bits of the OSCCON
register. This allows the internal oscillator to be
configured before a failure occurs.
DS41303B-page 38
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PIC18F2XK20/4XK20
FIGURE 2-9:
FSCM TIMING DIAGRAM
Sample Clock
Oscillator
Failure
System
Clock
Output
Clock Monitor Output
(Q)
Failure
Detected
OSCFIF
Test
Test
Test
Note:
The system clock is normally at a much higher frequency than the sample clock. The relative frequencies in
this example have been chosen for clarity.
TABLE 2-3:
Name
SUMMARY OF REGISTERS ASSOCIATED WITH CLOCK SOURCES
Value on
Value on
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
all other
Resets
POR, BOR
(1)
CONFIG1H
IESO
FCMEN
—
—
FOSC3 FOSC2 FOSC1
FOSC0
RBIF
—
—
INTCON
GIE/GIEH PEIE/GIEL TMR0IE INT0IE
RBIE
OSTS
TUN3
BCLIE
BCLIF
TMR0IF
IOFS
INT0IF
SCS1
TUN1
0000 000x 0000 000x
0011 q000 0011 q000
0000 0000 000u uuuu
OSCCON
IDLEN
IRCF2
PLLEN
C1IE
IRCF1
TUN5
C2IE
IRCF0
TUN4
EEIE
SCS0
TUN0
OSCTUNE INTSRC
TUN2
PIE2
OSCFIE
OSCFIF
HLVDIE TMR3IE CCP2IE 0000 0000 0000 0000
HLVDIF TMR3IF CCP2IF 0000 0000 0000 0000
PIR2
C1IF
C2IF
EEIF
Legend:
x= unknown, u= unchanged, –= unimplemented locations read as ‘0’. Shaded cells are not used by oscillators.
Note 1: Other (non Power-up) Resets include MCLR Reset and Watchdog Timer Reset during normal operation.
© 2007 Microchip Technology Inc.
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DS41303B-page 39
PIC18F2XK20/4XK20
NOTES:
DS41303B-page 40
Advance Information
© 2007 Microchip Technology Inc.
PIC18F2XK20/4XK20
3.1.1
CLOCK SOURCES
3.0
POWER-MANAGED MODES
The SCS<1:0> bits allow the selection of one of three
clock sources for power-managed modes. They are:
PIC18F2XK20/4XK20 devices offer a total of seven
operating modes for more efficient power manage-
ment. These modes provide a variety of options for
selective power conservation in applications where
resources may be limited (i.e., battery-powered
devices).
• the primary clock, as defined by the FOSC<3:0>
Configuration bits
• the secondary clock (the Timer1 oscillator)
• the internal oscillator block
There are three categories of power-managed modes:
3.1.2
ENTERING POWER-MANAGED
MODES
• Run modes
• Idle modes
• Sleep mode
Switching from one power-managed mode to another
begins by loading the OSCCON register. The
SCS<1:0> bits select the clock source and determine
which Run or Idle mode is to be used. Changing these
bits causes an immediate switch to the new clock
source, assuming that it is running. The switch may
also be subject to clock transition delays. These are
discussed in Section 3.1.3 “Clock Transitions and
Status Indicators” and subsequent sections.
These categories define which portions of the device
are clocked and sometimes, what speed. The Run and
Idle modes may use any of the three available clock
sources (primary, secondary or internal oscillator
block); the Sleep mode does not use a clock source.
The power-managed modes include several power-
saving features offered on previous PIC® microcontroller
devices. One is the clock switching feature which allows
the controller to use the Timer1 oscillator in place of the
primary oscillator. Also included is the Sleep mode,
offered by all PIC® microcontroller devices, where all
device clocks are stopped.
Entry to the power-managed Idle or Sleep modes is
triggered by the execution of a SLEEPinstruction. The
actual mode that results depends on the status of the
IDLEN bit of the OSCCON register.
Depending on the current mode and the mode being
switched to, a change to a power-managed mode does
not always require setting all of these bits. Many
transitions may be done by changing the oscillator select
bits, or changing the IDLEN bit, prior to issuing a SLEEP
instruction. If the IDLEN bit is already configured
correctly, it may only be necessary to perform a SLEEP
instruction to switch to the desired mode.
3.1
Selecting Power-Managed Modes
Selecting
decisions:
a power-managed mode requires two
• Whether or not the CPU is to be clocked
• The selection of a clock source
The IDLEN bit of the OSCCON register controls CPU
clocking, while the SCS<1:0> bits of the OSCCON
register select the clock source. The individual modes,
bit settings, clock sources and affected modules are
summarized in Table 3-1.
TABLE 3-1:
Mode
POWER-MANAGED MODES
OSCCON Bits
Module Clocking
Available Clock and Oscillator Source
IDLEN(1) SCS<1:0>
CPU
Peripherals
Sleep
0
N/A
Off
Off
None – All clocks are disabled
PRI_RUN
N/A
00
Clocked
Clocked
Primary – LP, XT, HS, HSPLL, RC, EC and
Internal Oscillator Block(2)
.
This is the normal full power execution mode.
Secondary – Timer1 Oscillator
Internal Oscillator Block(2)
SEC_RUN
RC_RUN
PRI_IDLE
SEC_IDLE
RC_IDLE
N/A
N/A
1
01
1x
00
01
1x
Clocked
Clocked
Off
Clocked
Clocked
Clocked
Clocked
Clocked
Primary – LP, XT, HS, HSPLL, RC, EC
Secondary – Timer1 Oscillator
Internal Oscillator Block(2)
1
Off
1
Off
Note 1: IDLEN reflects its value when the SLEEPinstruction is executed.
2: Includes HFINTOSC and HFINTOSC postscaler, as well as the LFINTOSC source.
© 2007 Microchip Technology Inc.
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PIC18F2XK20/4XK20
3.1.3
CLOCK TRANSITIONS AND STATUS
INDICATORS
3.2
Run Modes
In the Run modes, clocks to both the core and
peripherals are active. The difference between these
modes is the clock source.
The length of the transition between clock sources is
the sum of:
• Start-up time of the new clock
3.2.1
PRI_RUN MODE
• Two and one half cycles of the old clock source
• Two and one half cycles of the new clock
The PRI_RUN mode is the normal, full power execution
mode of the microcontroller. This is also the default
mode upon a device Reset, unless Two-Speed Start-up
is enabled (see Section 2.10 “Two-Speed Clock
Start-up Mode” for details). In this mode, the OSTS bit
is set. The IOFS bit will be set if the HFINTOSC is the
primary clock source and the oscillator is stable (see
Section 2.2 “Oscillator Control”).
Three flag bits indicate the current clock source and its
status. They are:
• OSTS (of the OSCCON register)
• IOFS (of the OSCCON register)
• T1RUN (of the T1CON register)
In general, only one of these bits will be set while in a
given power-managed mode. Table 3-2 shows the rela-
tionship of the flags to the active main system clock
source.
3.2.2
SEC_RUN MODE
The SEC_RUN mode is the mode compatible to the
“clock switching” feature offered in other PIC18
devices. In this mode, the CPU and peripherals are
clocked from the Timer1 oscillator. This gives users the
option of lower power consumption while still using a
high accuracy clock source.
TABLE 3-2:
SYSTEM CLOCK INDICATORS
OSTS IOFS T1RUN Main System Clock Source
1
0
0
1
0
1
0
1
0
0
1
0
Primary Oscillator
HFINTOSC
SEC_RUN mode is entered by setting the SCS<1:0>
bits to ‘01’. When SEC_RUN mode is active all of the
following are true:
Secondary Oscillator
HFINTOSC as primary clock
• The main clock source is switched to the Timer1
oscillator
LFINTOSC or
HFINTOSC is not yet stable
0
0
0
• Primary oscillator is shut down
• T1RUN bit of the T1CON register is set
• OSTS bit is cleared.
.
Note 1: Caution should be used when modifying a
single IRCF bit. If VDD is less than 2.7V, it
is possible to select a higher clock speed
than is supported by the low VDD.
Improper device operation may result if
the VDD/FOSC specifications are violated.
Note:
The Timer1 oscillator should already be
running prior to entering SEC_RUN mode.
If the T1OSCEN bit is not set when the
SCS<1:0> bits are set to ‘01’, entry to
SEC_RUN mode will not occur until
T1OSCEN bit is set and Timer1 oscillator
is ready.
2: Executing a SLEEP instruction does not
necessarily place the device into Sleep
mode. It acts as the trigger to place the
controller into either the Sleep mode or
one of the Idle modes, depending on the
setting of the IDLEN bit.
On transitions from SEC_RUN mode to PRI_RUN, the
peripherals and CPU continue to be clocked from the
Timer1 oscillator while the primary clock is started.
When the primary clock becomes ready, a clock switch
back to the primary clock occurs (see Figure 2-7).
When the clock switch is complete, the T1RUN bit is
cleared, the OSTS bit is set and the primary clock is
providing the main system clock. The Timer1 oscillator
continues to run as long as the T1OSCEN bit is set.
3.1.4
MULTIPLE FUNCTIONS OF THE
SLEEP COMMAND
The power-managed mode that is invoked with the
SLEEP instruction is determined by the setting of the
IDLEN bit of the OSCCON register at the time the
instruction is executed. All clocks stop and minimum
power is consumed when SLEEPis executed with the
IDLEN bit cleared. The system clock continues to sup-
ply a clock to the peripherals but is disconnected from
the CPU when SLEEP is executed with the IDLEN bit
set.
DS41303B-page 42
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PIC18F2XK20/4XK20
3.2.3
RC_RUN MODE
3.3
Sleep Mode
In RC_RUN mode, the CPU and peripherals are
clocked from the internal oscillator block using one of
the selections from the HFINTOSC multiplexer. In this
mode, the primary oscillator is shut down. RC_RUN
mode provides the best power conservation of all the
Run modes when the LFINTOSC is the main clock
source. It works well for user applications which are not
highly timing sensitive or do not require high-speed
clocks at all times.
The Power-Managed Sleep mode in the PIC18F2XK20/
4XK20 devices is identical to the legacy Sleep mode
offered in all other PIC® microcontroller devices. It is
entered by clearing the IDLEN bit (the default state on
device Reset) and executing the SLEEP instruction.
This shuts down the selected oscillator (Figure 3-1). All
clock source Status bits are cleared.
Entering the Sleep mode from any other mode does not
require a clock switch. This is because no clocks are
needed once the controller has entered Sleep. If the
WDT is selected, the LFINTOSC source will continue to
operate. If the Timer1 oscillator is enabled, it will also
continue to run.
If the primary clock source is the internal oscillator
block (either LFINTOSC or HFINTOSC), there are no
distinguishable differences between PRI_RUN and
RC_RUN modes during execution. However, a clock
switch delay will occur during entry to and exit from
RC_RUN mode. Therefore, if the primary clock source
is the internal oscillator block, the use of RC_RUN
mode is not recommended. See 2.10.4 “Clock Switch
Timing” for details about clock switching.
When a wake event occurs in Sleep mode (by interrupt,
Reset or WDT time-out), the device will not be clocked
until the clock source selected by the SCS<1:0> bits
becomes ready (see Figure 3-2), or it will be clocked
from the internal oscillator block if either the Two-
Speed Start-up or the Fail-Safe Clock Monitor are
enabled (see Section 23.0 “Special Features of the
CPU”). In either case, the OSTS bit is set when the
primary clock is providing the device clocks. The
IDLEN and SCS bits are not affected by the wake-up.
RC_RUN mode is entered by setting the SCS1 bit to
‘1’. The SCS0 bit can be either ‘0’ or ‘1’ but should be
‘0’ to maintain software compatibility with future
devices. When the clock source is switched from the
primary oscillator to the HFINTOSC multiplexer, the pri-
mary oscillator is shut down and the OSTS bit is
cleared. The IRCF bits may be modified at any time to
immediately change the clock speed.
3.4
Idle Modes
The Idle modes allow the controller’s CPU to be
selectively shut down while the peripherals continue to
operate. Selecting a particular Idle mode allows users
to further manage power consumption.
Note:
Caution should be used when modifying a
single IRCF bit. If VDD is less than 2.7V, it
is possible to select a higher clock speed
than is supported by the low VDD.
Improper device operation may result if
the VDD/FOSC specifications are violated.
If the IDLEN bit is set to a ‘1’ when a SLEEPinstruction is
executed, the peripherals will be clocked from the clock
source selected by the SCS<1:0> bits; however, the CPU
will not be clocked. The clock source Status bits are not
affected. Setting IDLEN and executing a SLEEPinstruc-
tion provides a quick method of switching from a given
Run mode to its corresponding Idle mode.
On transitions from RC_RUN mode to PRI_RUN mode,
the device continues to be clocked from the internal
oscillator block while the primary oscillator is started.
When the primary oscillator becomes ready, a clock
switch to the primary clock occurs. When the clock
switch is complete, the IOFS bit is cleared, the OSTS
bit is set and the primary oscillator is providing the main
system clock. The HFINTOSC will continue to run if any
of the conditions noted in Section 2.5.2 “HFINTOSC”
are met. The LFINTOSC source will continue to run if
any of the conditions noted in Section 2.5.3 “LFIN-
TOSC” are met.
If the WDT is selected, the LFINTOSC source will con-
tinue to operate. If the Timer1 oscillator is enabled, it
will also continue to run.
Since the CPU is not executing instructions, the only
exits from any of the Idle modes are by interrupt, WDT
time-out, or a Reset. When a wake event occurs, CPU
execution is delayed by an interval of TCSD
(parameter 38, Table 26-9) while it becomes ready to
execute code. When the CPU begins executing code,
it resumes with the same clock source for the current
Idle mode. For example, when waking from RC_IDLE
mode, the internal oscillator block will clock the CPU
and peripherals (in other words, RC_RUN mode). The
IDLEN and SCS bits are not affected by the wake-up.
While in any Idle mode or the Sleep mode, a WDT
time-out will result in a WDT wake-up to the Run mode
currently specified by the SCS<1:0> bits.
© 2007 Microchip Technology Inc.
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DS41303B-page 43
PIC18F2XK20/4XK20
FIGURE 3-1:
TRANSITION TIMING FOR ENTRY TO SLEEP MODE
Q1 Q2 Q3 Q4 Q1
OSC1
CPU
Clock
Peripheral
Clock
Sleep
Program
Counter
PC
PC + 2
FIGURE 3-2:
TRANSITION TIMING FOR WAKE FROM SLEEP (HSPLL)
Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
Q2 Q3 Q4 Q1 Q2
Q1
OSC1
(1)
(1)
TOST
TPLL
PLL Clock
Output
CPU Clock
Peripheral
Clock
Program
Counter
PC
PC + 2
PC + 4
PC + 6
Wake Event
Note1: TOST = 1024 TOSC; TPLL = 2 ms (approx). These intervals are not shown to scale.
OSTS bit set
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PIC18F2XK20/4XK20
3.4.1
PRI_IDLE MODE
3.4.2
SEC_IDLE MODE
This mode is unique among the three low-power Idle
modes, in that it does not disable the primary device
clock. For timing sensitive applications, this allows for
the fastest resumption of device operation with its more
accurate primary clock source, since the clock source
does not have to “warm-up” or transition from another
oscillator.
In SEC_IDLE mode, the CPU is disabled but the
peripherals continue to be clocked from the Timer1
oscillator. This mode is entered from SEC_RUN by set-
ting the IDLEN bit and executing a SLEEPinstruction. If
the device is in another Run mode, set the IDLEN bit
first, then set the SCS<1:0> bits to ‘01’ and execute
SLEEP. When the clock source is switched to the
Timer1 oscillator, the primary oscillator is shut down,
the OSTS bit is cleared and the T1RUN bit is set.
PRI_IDLE mode is entered from PRI_RUN mode by
setting the IDLEN bit and executing a SLEEP instruc-
tion. If the device is in another Run mode, set IDLEN
first, then clear the SCS bits and execute SLEEP.
Although the CPU is disabled, the peripherals continue
to be clocked from the primary clock source specified
by the FOSC<3:0> Configuration bits. The OSTS bit
remains set (see Figure 3-3).
When a wake event occurs, the peripherals continue to
be clocked from the Timer1 oscillator. After an interval
of TCSD following the wake event, the CPU begins exe-
cuting code being clocked by the Timer1 oscillator. The
IDLEN and SCS bits are not affected by the wake-up;
the Timer1 oscillator continues to run (see Figure 3-4).
When a wake event occurs, the CPU is clocked from the
primary clock source. A delay of interval TCSD is
required between the wake event and when code
execution starts. This is required to allow the CPU to
become ready to execute instructions. After the wake-
up, the OSTS bit remains set. The IDLEN and SCS bits
are not affected by the wake-up (see Figure 3-4).
Note:
The Timer1 oscillator should already be
running prior to entering SEC_IDLE mode.
If the T1OSCEN bit is not set when the
SLEEP instruction is executed, the main
system clock will continue to operate in the
previously selected mode and the corre-
sponding IDLE mode will be entered (i.e.,
PRI_IDLE or RC_IDLE).
FIGURE 3-3:
TRANSITION TIMING FOR ENTRY TO IDLE MODE
Q3
Q4
Q1
Q1
Q2
OSC1
CPU Clock
Peripheral
Clock
Program
Counter
PC
PC + 2
FIGURE 3-4:
TRANSITION TIMING FOR WAKE FROM IDLE TO RUN MODE
Q1
Q3
Q4
Q2
OSC1
TCSD
CPU Clock
Peripheral
Clock
Program
Counter
PC
Wake Event
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PIC18F2XK20/4XK20
3.4.3
RC_IDLE MODE
3.5.1
EXIT BY INTERRUPT
In RC_IDLE mode, the CPU is disabled but the periph-
erals continue to be clocked from the internal oscillator
block from the HFINTOSC multiplexer output. This
mode allows for controllable power conservation during
Idle periods.
Any of the available interrupt sources can cause the
device to exit from an Idle mode or the Sleep mode to
a Run mode. To enable this functionality, an interrupt
source must be enabled by setting its enable bit in one
of the INTCON or PIE registers. The PEIE bIt must also
be set If the desired interrupt enable bit is in a PIE reg-
ister. The exit sequence is initiated when the corre-
sponding interrupt flag bit is set.
From RC_RUN, this mode is entered by setting the
IDLEN bit and executing a SLEEP instruction. If the
device is in another Run mode, first set IDLEN, then set
the SCS1 bit and execute SLEEP. It is recommended
that SCS0 also be cleared, although its value is
ignored, to maintain software compatibility with future
devices. The HFINTOSC multiplexer may be used to
select a higher clock frequency by modifying the IRCF
bits before executing the SLEEPinstruction. When the
clock source is switched to the HFINTOSC multiplexer,
the primary oscillator is shut down and the OSTS bit is
cleared.
The instruction immediately following the SLEEP
instruction is executed on all exits by interrupt from Idle
or Sleep modes. Code execution then branches to the
interrupt vector if the GIE/GIEH bit of the INTCON reg-
ister is set, otherwise code execution continues without
branching (see Section 9.0 “Interrupts”).
A fixed delay of interval TCSD following the wake event
is required when leaving Sleep and Idle modes. This
delay is required for the CPU to prepare for execution.
Instruction execution resumes on the first clock cycle
following this delay.
If the IRCF bits are set to any non-zero value, or the
INTSRC bit is set, the HFINTOSC output is enabled.
The IOFS bit becomes set, after the HFINTOSC output
becomes stable, after an interval of TIOBST
(parameter 39, Table 26-9). Clocks to the peripherals
continue while the HFINTOSC source stabilizes. If the
IRCF bits were previously at a non-zero value, or
INTSRC was set before the SLEEPinstruction was exe-
cuted and the HFINTOSC source was already stable,
the IOFS bit will remain set. If the IRCF bits and
INTSRC are all clear, the HFINTOSC output will not be
enabled, the IOFS bit will remain clear and there will be
no indication of the current clock source.
3.5.2
EXIT BY WDT TIME-OUT
A WDT time-out will cause different actions depending
on which power-managed mode the device is in when
the time-out occurs.
If the device is not executing code (all Idle modes and
Sleep mode), the time-out will result in an exit from the
power-managed mode (see Section 3.2 “Run
Modes” and Section 3.3 “Sleep Mode”). If the device
is executing code (all Run modes), the time-out will
result in a WDT Reset (see Section 23.2 “Watchdog
Timer (WDT)”).
When a wake event occurs, the peripherals continue to
be clocked from the HFINTOSC multiplexer output.
After a delay of TCSD following the wake event, the CPU
begins executing code being clocked by the
HFINTOSC multiplexer. The IDLEN and SCS bits are
not affected by the wake-up. The LFINTOSC source
will continue to run if either the WDT or the Fail-Safe
Clock Monitor is enabled.
The WDT timer and postscaler are cleared by any one
of the following:
• executing a SLEEPinstruction
• executing a CLRWDTinstruction
• the loss of the currently selected clock source
when the Fail-Safe Clock Monitor is enabled
• modifying the IRCF bits in the OSCCON register
when the internal oscillator block is the device
clock source
3.5
Exiting Idle and Sleep Modes
An exit from Sleep mode or any of the Idle modes is
triggered by any one of the following:
3.5.3
EXIT BY RESET
• an interrupt
Exiting Sleep and Idle modes by Reset causes code
execution to restart at address 0. See Section 4.0
“Reset” for more details.
• a Reset
• a watchdog time-out
This section discusses the triggers that cause exits
from power-managed modes. The clocking subsystem
actions are discussed in each of the power-managed
modes (see Section 3.2 “Run Modes”, Section 3.3
“Sleep Mode” and Section 3.4 “Idle Modes”).
The exit delay time from Reset to the start of code
execution depends on both the clock sources before
and after the wake-up and the type of oscillator. Exit
delays are summarized in Table 3-3.
DS41303B-page 46
Advance Information
© 2007 Microchip Technology Inc.
PIC18F2XK20/4XK20
In these instances, the primary clock source either
does not require an oscillator start-up delay since it is
already running (PRI_IDLE), or normally does not
require an oscillator start-up delay (RC, EC, INTOSC,
and INTOSCIO modes). However, a fixed delay of
interval TCSD following the wake event is still required
when leaving Sleep and Idle modes to allow the CPU
to prepare for execution. Instruction execution resumes
on the first clock cycle following this delay.
3.5.4
EXIT WITHOUT AN OSCILLATOR
START-UP DELAY
Certain exits from power-managed modes do not
invoke the OST at all. There are two cases:
• PRI_IDLE mode, where the primary clock source
is not stopped and
• the primary clock source is not any of the LP, XT,
HS or HSPLL modes.
TABLE 3-3:
EXIT DELAY ON WAKE-UP BY RESET FROM SLEEP MODE OR ANY IDLE MODE
(BY CLOCK SOURCES)
Clock Source
before Wake-up
Clock Source
after Wake-up
Clock Ready Status
Bit (OSCCON)
Exit Delay
LP, XT, HS
HSPLL
OSTS
IOFS
OSTS
IOFS
OSTS
IOFS
OSTS
IOFS
Primary Device Clock
(PRI_IDLE mode)
(1)
TCSD
EC, RC
HFINTOSC(2)
LP, XT, HS
HSPLL
(3)
TOST
(3)
TOST + tPLL
T1OSC or LFINTOSC(1)
(1)
EC, RC
TCSD
HFINTOSC(1)
LP, XT, HS
HSPLL
TIOBST
(4)
(4)
TOST
(3)
(3)
TOST + tPLL
HFINTOSC(2)
(1)
EC, RC
TCSD
HFINTOSC(1)
LP, XT, HS
HSPLL
None
(3)
TOST
TOST + tPLL
None
(Sleep mode)
(1)
EC, RC
HFINTOSC(1)
TCSD
(4)
TIOBST
Note 1: TCSD (parameter 38) is a required delay when waking from Sleep and all Idle modes and runs concurrently
with any other required delays (see Section 3.4 “Idle Modes”). On Reset, HFINTOSC defaults to 1 MHz.
2: Includes both the HFINTOSC 16 MHz source and postscaler derived frequencies.
3: TOST is the Oscillator Start-up Timer (parameter 32). tPLL is the PLL Lock-out Timer (parameter F12).
4: Execution continues during the HFINTOSC stabilization period, TIOBST (parameter 39).
© 2007 Microchip Technology Inc.
Advance Information
DS41303B-page 47
PIC18F2XK20/4XK20
NOTES:
DS41303B-page 48
Advance Information
© 2007 Microchip Technology Inc.
PIC18F2XK20/4XK20
A simplified block diagram of the On-Chip Reset Circuit
is shown in Figure 4-1.
4.0
RESET
The PIC18F2XK20/4XK20 devices differentiate
between various kinds of Reset:
4.1
RCON Register
a) Power-on Reset (POR)
Device Reset events are tracked through the RCON
register (Register 4-1). The lower five bits of the regis-
ter indicate that a specific Reset event has occurred. In
most cases, these bits can only be cleared by the event
and must be set by the application after the event. The
state of these flag bits, taken together, can be read to
indicate the type of Reset that just occurred. This is
described in more detail in Section 4.6 “Reset State
of Registers”.
b) MCLR Reset during normal operation
c) MCLR Reset during power-managed modes
d) Watchdog Timer (WDT) Reset (during
execution)
e) Programmable Brown-out Reset (BOR)
f) RESETInstruction
g) Stack Full Reset
h) Stack Underflow Reset
The RCON register also has control bits for setting
interrupt priority (IPEN) and software control of the
BOR (SBOREN). Interrupt priority is discussed in
Section 9.0 “Interrupts”. BOR is covered in
Section 4.4 “Brown-out Reset (BOR)”.
This section discusses Resets generated by MCLR,
POR and BOR and covers the operation of the various
start-up timers. Stack Reset events are covered in
Section 5.1.2.4 “Stack Full and Underflow Resets”.
WDT Resets are covered in Section 23.2 “Watchdog
Timer (WDT)”.
FIGURE 4-1:
SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT
RESET
Instruction
Stack Full/Underflow Reset
Stack
Pointer
External Reset
MCLRE
MCLR
( )_IDLE
Sleep
WDT
Time-out
VDD Rise
Detect
POR Pulse
VDD
Brown-out
Reset
S
BOREN
OST/PWRT
OST
(2)
1024 Cycles
Chip_Reset
10-bit Ripple Counter
R
Q
OSC1
32 μs
(2)
65.5 ms
PWRT
LFINTOSC
11-bit Ripple Counter
Enable PWRT
(1)
Enable OST
Note 1: See Table 4-2 for time-out situations.
2: PWRT and OST counters are reset by POR and BOR. See Sections 4.3 and 4.4.
© 2007 Microchip Technology Inc.
Advance Information
DS41303B-page 49
PIC18F2XK20/4XK20
REGISTER 4-1:
RCON: RESET CONTROL REGISTER
R/W-0
R/W-1
SBOREN(1)
U-0
—
R/W-1
RI
R-1
TO
R-1
PD
R/W-0
POR(2)
R/W-0
BOR
IPEN
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
-n = Value at POR
bit 7
bit 6
IPEN: Interrupt Priority Enable bit
1= Enable priority levels on interrupts
0= Disable priority levels on interrupts (PIC16CXXX Compatibility mode)
SBOREN: BOR Software Enable bit(1)
If BOREN<1:0> = 01:
1= BOR is enabled
0= BOR is disabled
If BOREN<1:0> = 00, 10or 11:
Bit is disabled and read as ‘0’.
bit 5
bit 4
Unimplemented: Read as ‘0’
RI: RESETInstruction Flag bit
1= The RESETinstruction was not executed (set by firmware or Power-on Reset)
0= The RESET instruction was executed causing a device Reset (must be set in firmware after a
code-executed Reset occurs)
bit 3
bit 2
bit 1
bit 0
TO: Watchdog Time-out Flag bit
1= Set by power-up, CLRWDTinstruction or SLEEPinstruction
0= A WDT time-out occurred
PD: Power-down Detection Flag bit
1= Set by power-up or by the CLRWDTinstruction
0= Set by execution of the SLEEPinstruction
POR: Power-on Reset Status bit(2)
1= No Power-on Reset occurred
0= A Power-on Reset occurred (must be set in software after a Power-on Reset occurs)
BOR: Brown-out Reset Status bit(3)
1= A Brown-out Reset has not occurred (set by firmware only)
0= A Brown-out Reset occurred (must be set by firmware after a POR or Brown-out Reset occurs)
Note 1: If SBOREN is enabled, its Reset state is ‘1’; otherwise, it is ‘0’.
2: The actual Reset value of POR is determined by the type of device Reset. See the notes following this
register and Section 4.6 “Reset State of Registers” for additional information.
3: See Table 4-3.
Note 1: Brown-out Reset is indicated when BOR is ‘0’ and POR is ‘1’ (assuming that both POR and BOR were set
to ‘1’ by firmware immediately after POR).
2: It is recommended that the POR bit be set after a Power-on Reset has been detected so that subsequent
Power-on Resets may be detected.
DS41303B-page 50
Advance Information
© 2007 Microchip Technology Inc.
PIC18F2XK20/4XK20
FIGURE 4-2:
EXTERNAL POWER-ON
RESET CIRCUIT (FOR
SLOW VDD POWER-UP)
4.2
Master Clear (MCLR)
The MCLR pin provides a method for triggering an
external Reset of the device. A Reset is generated by
holding the pin low. These devices have a noise filter in
the MCLR Reset path which detects and ignores small
pulses.
VDD
VDD
D
PIC® MCU
The MCLR pin is not driven low by any internal Resets,
including the WDT.
R
R1
MCLR
In PIC18F2XK20/4XK20 devices, the MCLR input can
be disabled with the MCLRE Configuration bit. When
MCLR is disabled, the pin becomes a digital input. See
Section 10.6 “PORTE, TRISE and LATE Registers”
for more information.
C
Note 1: External Power-on Reset circuit is required
only if the VDD power-up slope is too slow.
The diode D helps discharge the capacitor
quickly when VDD powers down.
4.3
Power-on Reset (POR)
A
Power-on Reset pulse is generated on-chip
2: R < 40 kΩ is recommended to make sure that
the voltage drop across R does not violate
the device’s electrical specification.
whenever VDD rises above a certain threshold. This
allows the device to start in the initialized state when
VDD is adequate for operation.
3: R1 ≥ 1 kΩ will limit any current flowing into
MCLR from external capacitor C, in the event
of MCLR/VPP pin breakdown, due to
Electrostatic Discharge (ESD) or Electrical
Overstress (EOS).
To take advantage of the POR circuitry, tie the MCLR
pin through a resistor (1 kΩ to 10 kΩ) to VDD. This will
eliminate external RC components usually needed to
create a Power-on Reset delay. A minimum rise rate for
VDD is specified (parameter D004). For a slow rise
time, see Figure 4-2.
When the device starts normal operation (i.e., exits the
Reset condition), device operating parameters (volt-
age, frequency, temperature, etc.) must be met to
ensure operation. If these conditions are not met, the
device must be held in Reset until the operating
conditions are met.
POR events are captured by the POR bit of the RCON
register. The state of the bit is set to ‘0’ whenever a
POR occurs; it does not change for any other Reset
event. POR is not reset to ‘1’ by any hardware event.
To capture multiple events, the user must manually set
the bit to ‘1’ by software following any POR.
© 2007 Microchip Technology Inc.
Advance Information
DS41303B-page 51
PIC18F2XK20/4XK20
Placing the BOR under software control gives the user
the additional flexibility of tailoring the application to its
environment without having to reprogram the device to
change BOR configuration. It also allows the user to
tailor device power consumption in software by
eliminating the incremental current that the BOR
consumes. While the BOR current is typically very small,
it may have some impact in low-power applications.
4.4
Brown-out Reset (BOR)
PIC18F2XK20/4XK20 devices implement a BOR circuit
that provides the user with a number of configuration
and power-saving options. The BOR is controlled by
the BORV<1:0> and BOREN<1:0> bits of the
CONFIG2L Configuration register. There are a total of
four BOR configurations which are summarized in
Table 4-1.
Note:
Even when BOR is under software control,
the BOR Reset voltage level is still set by
the BORV<1:0> Configuration bits. It can-
not be changed by software.
The BOR threshold is set by the BORV<1:0> bits. If
BOR is enabled (any values of BOREN<1:0>, except
‘00’), any drop of VDD below VBOR (parameter D005)
for greater than TBOR (parameter 35) will reset the
device. A Reset may or may not occur if VDD falls below
VBOR for less than TBOR. The chip will remain in
Brown-out Reset until VDD rises above VBOR.
4.4.2
DETECTING BOR
When BOR is enabled, the BOR bit always resets to ‘0’
on any BOR or POR event. This makes it difficult to
determine if a BOR event has occurred just by reading
the state of BOR alone. A more reliable method is to
simultaneously check the state of both POR and BOR.
This assumes that the POR and BOR bits are reset to
‘1’ by software immediately after any POR event. If
BOR is ‘0’ while POR is ‘1’, it can be reliably assumed
that a BOR event has occurred.
If the Power-up Timer is enabled, it will be invoked after
VDD rises above VBOR; it then will keep the chip in
Reset for an additional time delay, TPWRT
(parameter 33). If VDD drops below VBOR while the
Power-up Timer is running, the chip will go back into a
Brown-out Reset and the Power-up Timer will be
initialized. Once VDD rises above VBOR, the Power-up
Timer will execute the additional time delay.
4.4.3
DISABLING BOR IN SLEEP MODE
BOR and the Power-on Timer (PWRT) are
independently configured. Enabling BOR Reset does
not automatically enable the PWRT.
When BOREN<1:0> = 10, the BOR remains under
hardware control and operates as previously
described. Whenever the device enters Sleep mode,
however, the BOR is automatically disabled. When the
device returns to any other operating mode, BOR is
automatically re-enabled.
4.4.1
SOFTWARE ENABLED BOR
When BOREN<1:0> = 01, the BOR can be enabled or
disabled by the user in software. This is done with the
SBOREN control bit of the RCON register. Setting
SBOREN enables the BOR to function as previously
described. Clearing SBOREN disables the BOR
entirely. The SBOREN bit operates only in this mode;
otherwise it is read as ‘0’.
This mode allows for applications to recover from
brown-out situations, while actively executing code,
when the device requires BOR protection the most. At
the same time, it saves additional power in Sleep mode
by eliminating the small incremental BOR current.
TABLE 4-1:
BOREN1
BOR CONFIGURATIONS
BOR Configuration
Status of
SBOREN
BOR Operation
BOREN0
(RCON<6>)
0
0
1
0
1
0
Unavailable BOR disabled; must be enabled by reprogramming the Configuration bits.
Available BOR enabled by software; operation controlled by SBOREN.
Unavailable BOR enabled by hardware in Run and Idle modes, disabled during
Sleep mode.
1
1
Unavailable BOR enabled by hardware; must be disabled by reprogramming the
Configuration bits.
DS41303B-page 52
Advance Information
© 2007 Microchip Technology Inc.
PIC18F2XK20/4XK20
The OST time-out is invoked only for XT, LP, HS and
HSPLL modes and only on Power-on Reset, or on exit
from all power-managed modes that stop the external
oscillator.
4.5
Device Reset Timers
PIC18F2XK20/4XK20 devices incorporate three
separate on-chip timers that help regulate the
Power-on Reset process. Their main function is to
ensure that the device clock is stable before code is
executed. These timers are:
4.5.3
PLL LOCK TIME-OUT
With the PLL enabled in its PLL mode, the time-out
sequence following a Power-on Reset is slightly
different from other oscillator modes. A separate timer
is used to provide a fixed time-out that is sufficient for
the PLL to lock to the main oscillator frequency. This
PLL lock time-out (TPLL) is typically 2 ms and follows
the oscillator start-up time-out.
• Power-up Timer (PWRT)
• Oscillator Start-up Timer (OST)
• PLL Lock Time-out
4.5.1
The
POWER-UP TIMER (PWRT)
Power-up Timer (PWRT)
of
PIC18F2XK20/4XK20 devices is an 11-bit counter
which uses the LFINTOSC source as the clock input.
This yields an approximate time interval of
2048 x 32 μs = 65.6 ms. While the PWRT is counting,
the device is held in Reset.
4.5.4
TIME-OUT SEQUENCE
On power-up, the time-out sequence is as follows:
1. After the POR pulse has cleared, PWRT time-out
is invoked (if enabled).
The power-up time delay depends on the LFINTOSC
clock and will vary from chip-to-chip due to temperature
and process variation. See DC parameter 33 for
details.
2. Then, the OST is activated.
The total time-out will vary based on oscillator
configuration and the status of the PWRT. Figure 4-3,
Figure 4-4, Figure 4-5, Figure 4-6 and Figure 4-7 all
depict time-out sequences on power-up, with the
Power-up Timer enabled and the device operating in
HS Oscillator mode. Figures 4-3 through 4-6 also
apply to devices operating in XT or LP modes. For
devices in RC mode and with the PWRT disabled, on
the other hand, there will be no time-out at all.
The PWRT is enabled by clearing the PWRTEN
Configuration bit.
4.5.2
OSCILLATOR START-UP TIMER
(OST)
The Oscillator Start-up Timer (OST) provides a 1024
oscillator cycle (from OSC1 input) delay after the
PWRT delay is over (parameter 33). This ensures that
the crystal oscillator or resonator has started and
stabilized.
Since the time-outs occur from the POR pulse, if MCLR
is kept low long enough, all time-outs will expire, after
which, bringing MCLR high will allow program
execution to begin immediately (Figure 4-5). This is
useful for testing purposes or to synchronize more than
one PIC18FXXK20 device operating in parallel.
TABLE 4-2:
Oscillator
TIME-OUT IN VARIOUS SITUATIONS
Power-up(2) and Brown-out
Exit from
Configuration
Power-Managed Mode
PWRTEN = 0
PWRTEN = 1
HSPLL
66 ms(1) + 1024 TOSC + 2 ms(2)
66 ms(1) + 1024 TOSC
66 ms(1)
1024 TOSC + 2 ms(2)
1024 TOSC + 2 ms(2)
HS, XT, LP
EC, ECIO
1024 TOSC
1024 TOSC
—
—
—
—
—
—
RC, RCIO
66 ms(1)
66 ms(1)
INTIO1, INTIO2
Note 1: 66 ms (65.5 ms) is the nominal Power-up Timer (PWRT) delay.
2: 2 ms is the nominal time required for the PLL to lock.
© 2007 Microchip Technology Inc.
Advance Information
DS41303B-page 53
PIC18F2XK20/4XK20
FIGURE 4-3:
TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD, VDD RISE < TPWRT)
VDD
MCLR
INTERNAL POR
TPWRT
PWRT TIME-OUT
OST TIME-OUT
TOST
INTERNAL RESET
FIGURE 4-4:
TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 1
VDD
MCLR
INTERNAL POR
TPWRT
PWRT TIME-OUT
OST TIME-OUT
TOST
INTERNAL RESET
FIGURE 4-5:
TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 2
VDD
MCLR
INTERNAL POR
TPWRT
PWRT TIME-OUT
OST TIME-OUT
TOST
INTERNAL RESET
DS41303B-page 54
Advance Information
© 2007 Microchip Technology Inc.
PIC18F2XK20/4XK20
FIGURE 4-6:
SLOW RISE TIME (MCLR TIED TO VDD, VDD RISE > TPWRT)
5V
0V
VDD
MCLR
INTERNAL POR
TPWRT
PWRT TIME-OUT
TOST
OST TIME-OUT
INTERNAL RESET
FIGURE 4-7:
TIME-OUT SEQUENCE ON POR W/PLL ENABLED (MCLR TIED TO VDD)
VDD
MCLR
INTERNAL POR
TPWRT
PWRT TIME-OUT
OST TIME-OUT
TOST
TPLL
PLL TIME-OUT
INTERNAL RESET
Note:
TOST = 1024 clock cycles.
TPLL ≈ 2 ms max. First three stages of the PWRT timer.
© 2007 Microchip Technology Inc.
Advance Information
DS41303B-page 55
PIC18F2XK20/4XK20
Table 4-4 describes the Reset states for all of the
Special Function Registers. These are categorized by
Power-on and Brown-out Resets, Master Clear and
WDT Resets and WDT wake-ups.
4.6
Reset State of Registers
Some registers are unaffected by a Reset. Their status
is unknown on POR and unchanged by all other
Resets. All other registers are forced to a “Reset state”
depending on the type of Reset that occurred.
Most registers are not affected by a WDT wake-up,
since this is viewed as the resumption of normal
operation. Status bits from the RCON register, RI, TO,
PD, POR and BOR, are set or cleared differently in
different Reset situations, as indicated in Table 4-3.
These bits are used by software to determine the
nature of the Reset.
TABLE 4-3:
STATUS BITS, THEIR SIGNIFICANCE AND THE INITIALIZATION CONDITION
FOR RCON REGISTER
RCON Register
STKPTR Register
Program
Counter
Condition
SBOREN
RI
TO
PD POR BOR STKFUL STKUNF
Power-on Reset
RESETInstruction
Brown-out Reset
0000h
0000h
0000h
0000h
1
1
0
1
u
1
u
1
1
1
u
1
u
0
u
u
u
0
u
0
u
0
u
u
u
0
u
u
u
u(2)
u(2)
u(2)
MCLR during Power-Managed
Run Modes
MCLR during Power-Managed
Idle Modes and Sleep Mode
0000h
0000h
0000h
u(2)
u(2)
u(2)
u
u
u
1
0
u
0
u
u
u
u
u
u
u
u
u
u
u
u
u
u
WDT Time-out during Full Power
or Power-Managed Run Mode
MCLR during Full Power
Execution
Stack Full Reset (STVREN = 1)
0000h
0000h
u(2)
u(2)
u
u
u
u
u
u
u
u
u
u
1
u
u
1
Stack Underflow Reset
(STVREN = 1)
Stack Underflow Error (not an
actual Reset, STVREN = 0)
0000h
u(2)
u(2)
u
u
u
0
u
0
u
u
u
u
u
u
1
u
WDT Time-out during
Power-Managed Idle or Sleep
Modes
PC + 2
Interrupt Exit from
PC + 2(1)
u(2)
u
u
0
u
u
u
u
Power-Managed Modes
Legend: u= unchanged
Note 1: When the wake-up is due to an interrupt and the GIEH or GIEL bits are set, the PC is loaded with the
interrupt vector (008h or 0018h).
2: Reset state is ‘1’ for POR and unchanged for all other Resets when software BOR is enabled
(BOREN<1:0> Configuration bits = 01and SBOREN = 1). Otherwise, the Reset state is ‘0’.
DS41303B-page 56
Advance Information
© 2007 Microchip Technology Inc.
PIC18F2XK20/4XK20
TABLE 4-4:
INITIALIZATION CONDITIONS FOR ALL REGISTERS
MCLR Resets,
WDT Reset,
RESET Instruction,
Stack Resets
Power-on Reset,
Brown-out Reset
Wake-up via WDT
or Interrupt
Register
Applicable Devices
(3)
TOSU
TOSH
PIC18F2XK20 PIC18F4XK20
PIC18F2XK20 PIC18F4XK20
PIC18F2XK20 PIC18F4XK20
PIC18F2XK20 PIC18F4XK20
PIC18F2XK20 PIC18F4XK20
PIC18F2XK20 PIC18F4XK20
PIC18F2XK20 PIC18F4XK20
PIC18F2XK20 PIC18F4XK20
PIC18F2XK20 PIC18F4XK20
PIC18F2XK20 PIC18F4XK20
PIC18F2XK20 PIC18F4XK20
PIC18F2XK20 PIC18F4XK20
PIC18F2XK20 PIC18F4XK20
PIC18F2XK20 PIC18F4XK20
PIC18F2XK20 PIC18F4XK20
PIC18F2XK20 PIC18F4XK20
PIC18F2XK20 PIC18F4XK20
PIC18F2XK20 PIC18F4XK20
PIC18F2XK20 PIC18F4XK20
PIC18F2XK20 PIC18F4XK20
PIC18F2XK20 PIC18F4XK20
PIC18F2XK20 PIC18F4XK20
PIC18F2XK20 PIC18F4XK20
PIC18F2XK20 PIC18F4XK20
PIC18F2XK20 PIC18F4XK20
PIC18F2XK20 PIC18F4XK20
PIC18F2XK20 PIC18F4XK20
PIC18F2XK20 PIC18F4XK20
PIC18F2XK20 PIC18F4XK20
---0 0000
0000 0000
---0 0000
0000 0000
---0 uuuu
(3)
uuuu uuuu
(3)
TOSL
0000 0000
00-0 0000
---0 0000
0000 0000
0000 0000
--00 0000
0000 0000
0000 0000
0000 0000
xxxx xxxx
xxxx xxxx
0000 000x
1111 -1-1
11-0 0-00
N/A
0000 0000
uu-0 0000
---0 0000
0000 0000
0000 0000
--00 0000
0000 0000
0000 0000
0000 0000
uuuu uuuu
uuuu uuuu
0000 000u
1111 -1-1
11-0 0-00
N/A
uuuu uuuu
(3)
STKPTR
PCLATU
PCLATH
PCL
uu-u uuuu
---u uuuu
uuuu uuuu
(2)
PC + 2
TBLPTRU
TBLPTRH
TBLPTRL
TABLAT
PRODH
PRODL
--uu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
(1)
INTCON
INTCON2
INTCON3
INDF0
uuuu uuuu
(1)
uuuu -u-u
(1)
uu-u u-uu
N/A
N/A
POSTINC0
POSTDEC0
PREINC0
PLUSW0
FSR0H
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
---- 0000
xxxx xxxx
xxxx xxxx
N/A
---- 0000
uuuu uuuu
uuuu uuuu
N/A
---- uuuu
uuuu uuuu
uuuu uuuu
N/A
FSR0L
WREG
INDF1
POSTINC1
POSTDEC1
PREINC1
PLUSW1
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
Legend:
u= unchanged, x= unknown, -= unimplemented bit, read as ‘0’, q= value depends on condition.
Shaded cells indicate conditions do not apply for the designated device.
Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).
2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt vector
(0008h or 0018h).
3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are updated with
the current value of the PC. The STKPTR is modified to point to the next location in the hardware stack.
4: See Table 4-3 for Reset value for specific condition.
5: Bits 6 and 7 of PORTA, LATA and TRISA are enabled, depending on the oscillator mode selected. When not enabled as
PORTA pins, they are disabled and read ‘0’.
6: All bits of the ANSELH register initialize to ‘0’ if the PBADEN bit of CONFIG3H is ‘0’.
© 2007 Microchip Technology Inc.
Advance Information
DS41303B-page 57
PIC18F2XK20/4XK20
TABLE 4-4:
INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)
MCLR Resets,
WDT Reset,
RESET Instruction,
Stack Resets
Power-on Reset,
Brown-out Reset
Wake-up via WDT
or Interrupt
Register
Applicable Devices
FSR1H
---- 0000
xxxx xxxx
---- 0000
N/A
---- 0000
uuuu uuuu
---- 0000
N/A
---- uuuu
uuuu uuuu
---- uuuu
N/A
PIC18F2XK20 PIC18F4XK20
PIC18F2XK20 PIC18F4XK20
PIC18F2XK20 PIC18F4XK20
PIC18F2XK20 PIC18F4XK20
PIC18F2XK20 PIC18F4XK20
PIC18F2XK20 PIC18F4XK20
PIC18F2XK20 PIC18F4XK20
PIC18F2XK20 PIC18F4XK20
PIC18F2XK20 PIC18F4XK20
PIC18F2XK20 PIC18F4XK20
PIC18F2XK20 PIC18F4XK20
PIC18F2XK20 PIC18F4XK20
PIC18F2XK20 PIC18F4XK20
PIC18F2XK20 PIC18F4XK20
PIC18F2XK20 PIC18F4XK20
PIC18F2XK20 PIC18F4XK20
PIC18F2XK20 PIC18F4XK20
PIC18F2XK20 PIC18F4XK20
PIC18F2XK20 PIC18F4XK20
PIC18F2XK20 PIC18F4XK20
PIC18F2XK20 PIC18F4XK20
PIC18F2XK20 PIC18F4XK20
PIC18F2XK20 PIC18F4XK20
PIC18F2XK20 PIC18F4XK20
PIC18F2XK20 PIC18F4XK20
PIC18F2XK20 PIC18F4XK20
PIC18F2XK20 PIC18F4XK20
PIC18F2XK20 PIC18F4XK20
PIC18F2XK20 PIC18F4XK20
FSR1L
BSR
INDF2
POSTINC2
POSTDEC2
PREINC2
PLUSW2
FSR2H
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
---- 0000
xxxx xxxx
---x xxxx
0000 0000
xxxx xxxx
1111 1111
0011 qq00
0-00 0101
---- ---0
0q-1 11q0
xxxx xxxx
xxxx xxxx
0000 0000
0000 0000
1111 1111
-000 0000
xxxx xxxx
0000 0000
0000 0000
0000 0000
0000 0000
---- 0000
uuuu uuuu
---u uuuu
0000 0000
uuuu uuuu
1111 1111
0011 qq00
0-00 0101
---- ---0
0q-q qquu
uuuu uuuu
uuuu uuuu
u0uu uuuu
0000 0000
1111 1111
-000 0000
uuuu uuuu
0000 0000
0000 0000
0000 0000
0000 0000
---- uuuu
uuuu uuuu
---u uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
u-uu uuuu
---- ---u
uq-u qquu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
1111 1111
-uuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
FSR2L
STATUS
TMR0H
TMR0L
T0CON
OSCCON
HLVDCON
WDTCON
(4)
RCON
TMR1H
TMR1L
T1CON
TMR2
PR2
T2CON
SSPBUF
SSPADD
SSPSTAT
SSPCON1
SSPCON2
Legend:
u= unchanged, x= unknown, -= unimplemented bit, read as ‘0’, q= value depends on condition.
Shaded cells indicate conditions do not apply for the designated device.
Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).
2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt vector
(0008h or 0018h).
3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are updated with
the current value of the PC. The STKPTR is modified to point to the next location in the hardware stack.
4: See Table 4-3 for Reset value for specific condition.
5: Bits 6 and 7 of PORTA, LATA and TRISA are enabled, depending on the oscillator mode selected. When not enabled as
PORTA pins, they are disabled and read ‘0’.
6: All bits of the ANSELH register initialize to ‘0’ if the PBADEN bit of CONFIG3H is ‘0’.
DS41303B-page 58
Advance Information
© 2007 Microchip Technology Inc.
PIC18F2XK20/4XK20
TABLE 4-4:
INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)
MCLR Resets,
WDT Reset,
RESET Instruction,
Stack Resets
Power-on Reset,
Brown-out Reset
Wake-up via WDT
or Interrupt
Register
Applicable Devices
ADRESH
ADRESL
ADCON0
ADCON1
ADCON2
CCPR1H
CCPR1L
xxxx xxxx
xxxx xxxx
--00 0000
--00 0qqq
0-00 0000
xxxx xxxx
xxxx xxxx
0000 0000
xxxx xxxx
xxxx xxxx
--00 0000
---0 0001
0100 0-00
0000 0000
0000 0000
0000 0000
00-- ----
xxxx xxxx
xxxx xxxx
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0010
0000 000x
0000 0000
---- --00
0000 0000
0000 0000
xx-0 x000
uuuu uuuu
uuuu uuuu
--00 0000
--00 0qqq
0-00 0000
uuuu uuuu
uuuu uuuu
0000 0000
uuuu uuuu
uuuu uuuu
--00 0000
---0 0001
0100 0-00
0000 0000
0000 0000
0000 0000
00-- ----
uuuu uuuu
uuuu uuuu
uuuu uuuu
0000 0000
0000 0000
0000 0000
0000 0000
0000 0010
0000 000x
0000 0000
---- --00
0000 0000
0000 0000
uu-0 u000
uuuu uuuu
uuuu uuuu
--uu uuuu
--uu uuuu
u-uu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
--uu uuuu
---u uuuu
uuuu u-uu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uu-- ----
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
---- --uu
uuuu uuuu
0000 0000
uu-0 u000
PIC18F2XK20 PIC18F4XK20
PIC18F2XK20 PIC18F4XK20
PIC18F2XK20 PIC18F4XK20
PIC18F2XK20 PIC18F4XK20
PIC18F2XK20 PIC18F4XK20
PIC18F2XK20 PIC18F4XK20
PIC18F2XK20 PIC18F4XK20
PIC18F2XK20 PIC18F4XK20
PIC18F2XK20 PIC18F4XK20
PIC18F2XK20 PIC18F4XK20
PIC18F2XK20 PIC18F4XK20
PIC18F2XK20 PIC18F4XK20
PIC18F2XK20 PIC18F4XK20
PIC18F2XK20 PIC18F4XK20
PIC18F2XK20 PIC18F4XK20
PIC18F2XK20 PIC18F4XK20
PIC18F2XK20 PIC18F4XK20
PIC18F2XK20 PIC18F4XK20
PIC18F2XK20 PIC18F4XK20
PIC18F2XK20 PIC18F4XK20
PIC18F2XK20 PIC18F4XK20
PIC18F2XK20 PIC18F4XK20
PIC18F2XK20 PIC18F4XK20
PIC18F2XK20 PIC18F4XK20
PIC18F2XK20 PIC18F4XK20
PIC18F2XK20 PIC18F4XK20
PIC18F2XK20 PIC18F4XK20
PIC18F26K20 PIC18F46K20
PIC18F2XK20 PIC18F4XK20
PIC18F2XK20 PIC18F4XK20
PIC18F2XK20 PIC18F4XK20
CCP1CON
CCPR2H
CCPR2L
CCP2CON
PSTRCON
BAUDCTL
PWM1CON
ECCP1AS
CVRCON
CVRCON2
TMR3H
TMR3L
T3CON
SPBRGH
SPBRG
RCREG
TXREG
TXSTA
RCSTA
EEADR
EEADRH
EEDATA
EECON2
EECON1
Legend:
u= unchanged, x= unknown, -= unimplemented bit, read as ‘0’, q= value depends on condition.
Shaded cells indicate conditions do not apply for the designated device.
Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).
2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt vector
(0008h or 0018h).
3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are updated with
the current value of the PC. The STKPTR is modified to point to the next location in the hardware stack.
4: See Table 4-3 for Reset value for specific condition.
5: Bits 6 and 7 of PORTA, LATA and TRISA are enabled, depending on the oscillator mode selected. When not enabled as
PORTA pins, they are disabled and read ‘0’.
6: All bits of the ANSELH register initialize to ‘0’ if the PBADEN bit of CONFIG3H is ‘0’.
© 2007 Microchip Technology Inc.
Advance Information
DS41303B-page 59
PIC18F2XK20/4XK20
TABLE 4-4:
INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)
MCLR Resets,
WDT Reset,
RESET Instruction,
Stack Resets
Power-on Reset,
Brown-out Reset
Wake-up via WDT
or Interrupt
Register
Applicable Devices
IPR2
PIR2
PIE2
1111 1111
0000 0000
0000 0000
1111 1111
-111 1111
0000 0000
-000 0000
0000 0000
-000 0000
0000 0000
---- -111
1111 1111
1111 1111
1111 1111
1111 1111
0000 0000
0000 0000
1111 1111
-111 1111
0000 0000
-000 0000
0000 0000
-000 0000
0000 0000
---- -111
1111 1111
1111 1111
1111 1111
uuuu uuuu
PIC18F2XK20 PIC18F4XK20
PIC18F2XK20 PIC18F4XK20
PIC18F2XK20 PIC18F4XK20
PIC18F2XK20 PIC18F4XK20
PIC18F2XK20 PIC18F4XK20
PIC18F2XK20 PIC18F4XK20
PIC18F2XK20 PIC18F4XK20
PIC18F2XK20 PIC18F4XK20
PIC18F2XK20 PIC18F4XK20
PIC18F2XK20 PIC18F4XK20
PIC18F2XK20 PIC18F4XK20
PIC18F2XK20 PIC18F4XK20
PIC18F2XK20 PIC18F4XK20
PIC18F2XK20 PIC18F4XK20
PIC18F2XK20 PIC18F4XK20
PIC18F2XK20 PIC18F4XK20
PIC18F2XK20 PIC18F4XK20
PIC18F2XK20 PIC18F4XK20
PIC18F2XK20 PIC18F4XK20
PIC18F2XK20 PIC18F4XK20
PIC18F2XK20 PIC18F4XK20
PIC18F2XK20 PIC18F4XK20
PIC18F2XK20 PIC18F4XK20
PIC18F2XK20 PIC18F4XK20
PIC18F2XK20 PIC18F4XK20
PIC18F2XK20 PIC18F4XK20
PIC18F2XK20 PIC18F4XK20
PIC18F2XK20 PIC18F4XK20
PIC18F2XK20 PIC18F4XK20
PIC18F2XK20 PIC18F4XK20
PIC18F2XK20 PIC18F4XK20
PIC18F2XK20 PIC18F4XK20
(1)
uuuu uuuu
uuuu uuuu
uuuu uuuu
-uuu uuuu
IPR1
PIR1
PIE1
(1)
uuuu uuuu
(1)
-uuu uuuu
uuuu uuuu
-uuu uuuu
uuuu uuuu
---- -uuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
OSCTUNE
TRISE
TRISD
TRISC
TRISB
(5)
(5)
(5)
(5)
TRISA
1111 1111
1111 1111
uuuu uuuu
LATE
LATD
LATC
LATB
---- -xxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
---- -uuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
---- -uuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
(5)
(5)
(5)
(5)
LATA
xxxx xxxx
uuuu uuuu
uuuu uuuu
---- x000
---- x---
xxxx xxxx
xxxx xxxx
xxx0 0000
---- u000
---- u---
uuuu uuuu
uuuu uuuu
uuu0 0000
---- uuuu
---- u---
uuuu uuuu
uuuu uuuu
uuuu uuuu
PORTE
PORTD
PORTC
PORTB
(5)
(5)
(5)
(5)
PORTA
xx0x 0000
uu0u 0000
uuuu uuuu
(6)
ANSELH
---1 1111
1111 1111
0000 ----
1111 1111
0000 0000
0000 0000
---1 1111
1111 1111
0000 ----
1111 1111
0000 0000
0000 0000
---u uuuu
uuuu uuuu
uuuu ----
uuuu uuuu
uuuu uuuu
uuuu uuuu
ANSEL
IOCB
WPUB
CM1CON0
CM2CON0
Legend:
u= unchanged, x= unknown, -= unimplemented bit, read as ‘0’, q= value depends on condition.
Shaded cells indicate conditions do not apply for the designated device.
Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).
2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt vector
(0008h or 0018h).
3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are updated with
the current value of the PC. The STKPTR is modified to point to the next location in the hardware stack.
4: See Table 4-3 for Reset value for specific condition.
5: Bits 6 and 7 of PORTA, LATA and TRISA are enabled, depending on the oscillator mode selected. When not enabled as
PORTA pins, they are disabled and read ‘0’.
6: All bits of the ANSELH register initialize to ‘0’ if the PBADEN bit of CONFIG3H is ‘0’.
DS41303B-page 60
Advance Information
© 2007 Microchip Technology Inc.
PIC18F2XK20/4XK20
TABLE 4-4:
INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)
MCLR Resets,
WDT Reset,
RESET Instruction,
Stack Resets
Power-on Reset,
Brown-out Reset
Wake-up via WDT
or Interrupt
Register
Applicable Devices
CM2CON1
SLRCON
SSPMSK
0000 ----
---1 1111
1111 1111
0000 ----
---1 1111
1111 1111
uuuu ----
---u uuuu
uuuu uuuu
PIC18F2XK20 PIC18F4XK20
PIC18F2XK20 PIC18F4XK20
PIC18F2XK20 PIC18F4XK20
Legend:
u= unchanged, x= unknown, -= unimplemented bit, read as ‘0’, q= value depends on condition.
Shaded cells indicate conditions do not apply for the designated device.
Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).
2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt vector
(0008h or 0018h).
3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are updated with
the current value of the PC. The STKPTR is modified to point to the next location in the hardware stack.
4: See Table 4-3 for Reset value for specific condition.
5: Bits 6 and 7 of PORTA, LATA and TRISA are enabled, depending on the oscillator mode selected. When not enabled as
PORTA pins, they are disabled and read ‘0’.
6: All bits of the ANSELH register initialize to ‘0’ if the PBADEN bit of CONFIG3H is ‘0’.
© 2007 Microchip Technology Inc.
Advance Information
DS41303B-page 61
PIC18F2XK20/4XK20
NOTES:
DS41303B-page 62
Advance Information
© 2007 Microchip Technology Inc.
PIC18F2XK20/4XK20
5.1
Program Memory Organization
5.0
MEMORY ORGANIZATION
PIC18 microcontrollers implement a 21-bit program
counter, which is capable of addressing a 2-Mbyte
program memory space. Accessing a location between
the upper boundary of the physically implemented
memory and the 2-Mbyte address will return all ‘0’s (a
NOPinstruction).
There are three types of memory in PIC18 Enhanced
microcontroller devices:
• Program Memory
• Data RAM
• Data EEPROM
As Harvard architecture devices, the data and program
memories use separate busses; this allows for concur-
rent access of the two memory spaces. The data
EEPROM, for practical purposes, can be regarded as
a peripheral device, since it is addressed and accessed
through a set of control registers.
This family of devices contain the following:
• PIC18F23K20, PIC18F43K20: 8 Kbytes of Flash
Memory, up to 4,096 single-word instructions
• PIC18F24K20, PIC18F44K20: 16 Kbytes of Flash
Memory, up to 8,192 single-word instructions
• PIC18F25K20, PIC18F45K20: 32 Kbytes of Flash
Memory, up to 16,384 single-word instructions
Additional detailed information on the operation of the
Flash program memory is provided in Section 6.0
“Flash Program Memory”. Data EEPROM is
discussed separately in Section 7.0 “Data EEPROM
Memory”.
• PIC18F26K20, PIC18F46K20: 64 Kbytes of Flash
Memory, up to 37,768 single-word instructions
PIC18 devices have two interrupt vectors. The Reset
vector address is at 0000h and the interrupt vector
addresses are at 0008h and 0018h.
The program memory map for PIC18F2XK20/4XK20
devices is shown in Figure 5-1. Memory block details
are shown in Figure 23-2.
FIGURE 5-1:
PROGRAM MEMORY MAP AND STACK FOR PIC18F2XK20/4XK20 DEVICES
PC<20:0>
21
CALL,RCALL,RETURN
RETFIE,RETLW
Stack Level 1
•
•
•
Stack Level 31
0000h
Reset Vector
High Priority Interrupt Vector
Low Priority Interrupt Vector
0008h
0018h
On-Chip
Program Memory
1FFFh
On-Chip
Program Memory
2000h
On-Chip
Program Memory
3FFFh
4000h
PIC18F23K20/
43K20
On-Chip
Program Memory
PIC18F24K20/
44K20
7FFFh
8000h
PIC18F25K20/
45K20
FFFFh
10000h
Read ‘0’
Read ‘0’
Read ‘0’
PIC18F26K20/
46K20
Read ‘0’
1FFFFFh
200000h
© 2007 Microchip Technology Inc.
Advance Information
DS41303B-page 63
PIC18F2XK20/4XK20
The stack operates as a 31-word by 21-bit RAM and a
5-bit Stack Pointer, STKPTR. The stack space is not
part of either program or data space. The Stack Pointer
is readable and writable and the address on the top of
the stack is readable and writable through the Top-of-
Stack (TOS) Special File Registers. Data can also be
pushed to, or popped from the stack, using these
registers.
5.1.1
PROGRAM COUNTER
The Program Counter (PC) specifies the address of the
instruction to fetch for execution. The PC is 21 bits wide
and is contained in three separate 8-bit registers. The
low byte, known as the PCL register, is both readable
and writable. The high byte, or PCH register, contains
the PC<15:8> bits; it is not directly readable or writable.
Updates to the PCH register are performed through the
PCLATH register. The upper byte is called PCU. This
register contains the PC<20:16> bits; it is also not
directly readable or writable. Updates to the PCU
register are performed through the PCLATU register.
A CALLtype instruction causes a push onto the stack;
the Stack Pointer is first incremented and the location
pointed to by the Stack Pointer is written with the
contents of the PC (already pointing to the instruction
following the CALL). A RETURNtype instruction causes
a pop from the stack; the contents of the location
pointed to by the STKPTR are transferred to the PC
and then the Stack Pointer is decremented.
The contents of PCLATH and PCLATU are transferred
to the program counter by any operation that writes
PCL. Similarly, the upper two bytes of the program
counter are transferred to PCLATH and PCLATU by an
operation that reads PCL. This is useful for computed
offsets to the PC (see Section 5.1.4.1 “Computed
GOTO”).
The Stack Pointer is initialized to ‘00000’ after all
Resets. There is no RAM associated with the location
corresponding to a Stack Pointer value of ‘00000’; this
is only a Reset value. Status bits indicate if the stack is
full or has overflowed or has underflowed.
The PC addresses bytes in the program memory. To
prevent the PC from becoming misaligned with word
instructions, the Least Significant bit of PCL is fixed to
a value of ‘0’. The PC increments by 2 to address
sequential instructions in the program memory.
5.1.2.1
Top-of-Stack Access
Only the top of the return address stack (TOS) is readable
and writable. A set of three registers, TOSU:TOSH:TOSL,
hold the contents of the stack location pointed to by the
STKPTR register (Figure 5-2). This allows users to
implement a software stack if necessary. After a CALL,
RCALL or interrupt, the software can read the pushed
value by reading the TOSU:TOSH:TOSL registers. These
values can be placed on a user defined software stack. At
return time, the software can return these values to
TOSU:TOSH:TOSL and do a return.
The CALL, RCALL, GOTO and program branch
instructions write to the program counter directly. For
these instructions, the contents of PCLATH and
PCLATU are not transferred to the program counter.
5.1.2
RETURN ADDRESS STACK
The return address stack allows any combination of up
to 31 program calls and interrupts to occur. The PC is
pushed onto the stack when a CALL or RCALL
instruction is executed or an interrupt is Acknowledged.
The PC value is pulled off the stack on a RETURN,
RETLWor a RETFIEinstruction. PCLATU and PCLATH
are not affected by any of the RETURN or CALL
instructions.
The user must disable the global interrupt enable bits
while accessing the stack to prevent inadvertent stack
corruption.
FIGURE 5-2:
RETURN ADDRESS STACK AND ASSOCIATED REGISTERS
Return Address Stack <20:0>
11111
11110
11101
Top-of-Stack Registers
Stack Pointer
STKPTR<4:0>
TOSU
00h
TOSH
1Ah
TOSL
34h
00010
00011
00010
00001
00000
001A34h
000D58h
Top-of-Stack
DS41303B-page 64
Advance Information
© 2007 Microchip Technology Inc.
PIC18F2XK20/4XK20
When the stack has been popped enough times to
unload the stack, the next pop will return a value of zero
to the PC and sets the STKUNF bit, while the Stack
Pointer remains at zero. The STKUNF bit will remain
set until cleared by software or until a POR occurs.
5.1.2.2
Return Stack Pointer (STKPTR)
The STKPTR register (Register 5-1) contains the Stack
Pointer value, the STKFUL (stack full) Status bit and
the STKUNF (stack underflow) Status bits. The value of
the Stack Pointer can be 0 through 31. The Stack
Pointer increments before values are pushed onto the
stack and decrements after values are popped off the
stack. On Reset, the Stack Pointer value will be zero.
The user may read and write the Stack Pointer value.
This feature can be used by a Real-Time Operating
System (RTOS) for return stack maintenance.
Note:
Returning a value of zero to the PC on an
underflow has the effect of vectoring the
program to the Reset vector, where the
stack conditions can be verified and
appropriate actions can be taken. This is
not the same as a Reset, as the contents
of the SFRs are not affected.
After the PC is pushed onto the stack 31 times (without
popping any values off the stack), the STKFUL bit is
set. The STKFUL bit is cleared by software or by a
POR.
5.1.2.3
PUSHand POPInstructions
Since the Top-of-Stack is readable and writable, the
ability to push values onto the stack and pull values off
the stack without disturbing normal program execution
is a desirable feature. The PIC18 instruction set
includes two instructions, PUSH and POP, that permit
the TOS to be manipulated under software control.
TOSU, TOSH and TOSL can be modified to place data
or a return address on the stack.
The action that takes place when the stack becomes
full depends on the state of the STVREN (Stack Over-
flow Reset Enable) Configuration bit. (Refer to
Section 23.1 “Configuration Bits” for a description of
the device Configuration bits.) If STVREN is set
(default), the 31st push will push the (PC + 2) value
onto the stack, set the STKFUL bit and reset the
device. The STKFUL bit will remain set and the Stack
Pointer will be set to zero.
The PUSHinstruction places the current PC value onto
the stack. This increments the Stack Pointer and loads
the current PC value onto the stack.
If STVREN is cleared, the STKFUL bit will be set on the
31st push and the Stack Pointer will increment to 31.
Any additional pushes will not overwrite the 31st push
and STKPTR will remain at 31.
The POPinstruction discards the current TOS by decre-
menting the Stack Pointer. The previous value pushed
onto the stack then becomes the TOS value.
REGISTER 5-1:
STKPTR: STACK POINTER REGISTER
R/C-0
STKFUL(1)
R/C-0
STKUNF(1)
U-0
—
R/W-0
SP4
R/W-0
SP3
R/W-0
SP2
R/W-0
SP1
R/W-0
SP0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented
‘0’ = Bit is cleared
C = Clearable only bit
x = Bit is unknown
-n = Value at POR
bit 7
bit 6
STKFUL: Stack Full Flag bit(1)
1= Stack became full or overflowed
0= Stack has not become full or overflowed
STKUNF: Stack Underflow Flag bit(1)
1= Stack underflow occurred
0= Stack underflow did not occur
bit 5
Unimplemented: Read as ‘0’
bit 4-0
SP<4:0>: Stack Pointer Location bits
Note 1: Bit 7 and bit 6 are cleared by user software or by a POR.
© 2007 Microchip Technology Inc.
Advance Information
DS41303B-page 65
PIC18F2XK20/4XK20
5.1.2.4
Stack Full and Underflow Resets
5.1.4
LOOK-UP TABLES IN PROGRAM
MEMORY
Device Resets on stack overflow and stack underflow
conditions are enabled by setting the STVREN bit in
Configuration Register 4L. When STVREN is set, a full
or underflow will set the appropriate STKFUL or
STKUNF bit and then cause a device Reset. When
STVREN is cleared, a full or underflow condition will set
the appropriate STKFUL or STKUNF bit but not cause
a device Reset. The STKFUL or STKUNF bits are
cleared by the user software or a Power-on Reset.
There may be programming situations that require the
creation of data structures, or look-up tables, in
program memory. For PIC18 devices, look-up tables
can be implemented in two ways:
• Computed GOTO
• Table Reads
5.1.4.1
Computed GOTO
5.1.3
FAST REGISTER STACK
A computed GOTOis accomplished by adding an offset
to the program counter. An example is shown in
Example 5-2.
A fast register stack is provided for the Status, WREG
and BSR registers, to provide a “fast return” option for
interrupts. The stack for each register is only one level
deep and is neither readable nor writable. It is loaded
with the current value of the corresponding register
when the processor vectors for an interrupt. All inter-
rupt sources will push values into the stack registers.
The values in the registers are then loaded back into
their associated registers if the RETFIE, FAST
instruction is used to return from the interrupt.
A look-up table can be formed with an ADDWF PCL
instruction and a group of RETLW nninstructions. The
W register is loaded with an offset into the table before
executing a call to that table. The first instruction of the
called routine is the ADDWF PCLinstruction. The next
instruction executed will be one of the RETLW nn
instructions that returns the value ‘nn’ to the calling
function.
If both low and high priority interrupts are enabled, the
stack registers cannot be used reliably to return from
low priority interrupts. If a high priority interrupt occurs
while servicing a low priority interrupt, the stack register
values stored by the low priority interrupt will be
overwritten. In these cases, users must save the key
registers by software during a low priority interrupt.
The offset value (in WREG) specifies the number of
bytes that the program counter should advance and
should be multiples of 2 (LSb = 0).
In this method, only one data byte may be stored in
each instruction location and room on the return
address stack is required.
If interrupt priority is not used, all interrupts may use the
fast register stack for returns from interrupt. If no
interrupts are used, the fast register stack can be used
to restore the Status, WREG and BSR registers at the
end of a subroutine call. To use the fast register stack
for a subroutine call, a CALLlabel, FASTinstruction
must be executed to save the Status, WREG and BSR
registers to the fast register stack. A RETURN, FAST
instruction is then executed to restore these registers
from the fast register stack.
EXAMPLE 5-2:
COMPUTED GOTO USING
AN OFFSET VALUE
OFFSET, W
TABLE
MOVF
CALL
ORG
TABLE
nn00h
ADDWF
RETLW
RETLW
RETLW
.
PCL
nnh
nnh
nnh
.
Example 5-1 shows a source code example that uses
the fast register stack during a subroutine call and
return.
.
5.1.4.2
Table Reads and Table Writes
A better method of storing data in program memory
allows two bytes of data to be stored in each instruction
location.
EXAMPLE 5-1:
FAST REGISTER STACK
CODE EXAMPLE
;STATUS, WREG, BSR
;SAVED IN FAST REGISTER
;STACK
CALL SUB1, FAST
Look-up table data may be stored two bytes per pro-
gram word by using table reads and writes. The Table
Pointer (TBLPTR) register specifies the byte address
and the Table Latch (TABLAT) register contains the
data that is read from or written to program memory.
Data is transferred to or from program memory one
byte at a time.
•
•
SUB1
•
•
RETURN, FAST
;RESTORE VALUES SAVED
;IN FAST REGISTER STACK
Table read and table write operations are discussed
further in Section 6.1 “Table Reads and Table
Writes”.
DS41303B-page 66
Advance Information
© 2007 Microchip Technology Inc.
PIC18F2XK20/4XK20
5.2.2
INSTRUCTION FLOW/PIPELINING
5.2
PIC18 Instruction Cycle
An “Instruction Cycle” consists of four Q cycles: Q1
through Q4. The instruction fetch and execute are
pipelined in such a manner that a fetch takes one
instruction cycle, while the decode and execute take
another instruction cycle. However, due to the
pipelining, each instruction effectively executes in one
cycle. If an instruction causes the program counter to
change (e.g., GOTO), then two cycles are required to
complete the instruction (Example 5-3).
5.2.1
CLOCKING SCHEME
The microcontroller clock input, whether from an
internal or external source, is internally divided by four
to generate four non-overlapping quadrature clocks
(Q1, Q2, Q3 and Q4). Internally, the program counter is
incremented on every Q1; the instruction is fetched
from the program memory and latched into the
instruction register during Q4. The instruction is
decoded and executed during the following Q1 through
Q4. The clocks and instruction execution flow are
shown in Figure 5-3.
A fetch cycle begins with the Program Counter (PC)
incrementing in Q1.
In the execution cycle, the fetched instruction is latched
into the Instruction Register (IR) in cycle Q1. This
instruction is then decoded and executed during the
Q2, Q3 and Q4 cycles. Data memory is read during Q2
(operand read) and written during Q4 (destination
write).
FIGURE 5-3:
CLOCK/INSTRUCTION CYCLE
Q2
Q3
Q4
Q2
Q3
Q4
Q2
Q3
Q4
Q1
Q1
Q1
OSC1
Q1
Q2
Q3
Q4
Internal
Phase
Clock
PC
PC
PC + 2
PC + 4
OSC2/CLKOUT
(RC mode)
Execute INST (PC – 2)
Fetch INST (PC)
Execute INST (PC)
Fetch INST (PC + 2)
Execute INST (PC + 2)
Fetch INST (PC + 4)
EXAMPLE 5-3:
INSTRUCTION PIPELINE FLOW
TCY0
TCY1
TCY2
TCY3
TCY4
TCY5
1. MOVLW 55h
2. MOVWF PORTB
3. BRA SUB_1
Fetch 1
Execute 1
Fetch 2
Execute 2
Fetch 3
Execute 3
Fetch 4
4. BSF
PORTA, BIT3 (Forced NOP)
Flush (NOP)
5. Instruction @ address SUB_1
Fetch SUB_1 Execute SUB_1
All instructions are single cycle, except for any program branches. These take two cycles since the fetch instruction
is “flushed” from the pipeline while the new instruction is being fetched and then executed.
© 2007 Microchip Technology Inc.
Advance Information
DS41303B-page 67
PIC18F2XK20/4XK20
The CALL and GOTO instructions have the absolute
program memory address embedded into the
instruction. Since instructions are always stored on word
boundaries, the data contained in the instruction is a
word address. The word address is written to PC<20:1>,
which accesses the desired byte address in program
memory. Instruction #2 in Figure 5-4 shows how the
instruction GOTO 0006h is encoded in the program
memory. Program branch instructions, which encode a
relative address offset, operate in the same manner. The
offset value stored in a branch instruction represents the
number of single-word instructions that the PC will be
offset by. Section 24.0 “Instruction Set Summary”
provides further details of the instruction set.
5.2.3
INSTRUCTIONS IN PROGRAM
MEMORY
The program memory is addressed in bytes.
Instructions are stored as either two bytes or four bytes
in program memory. The Least Significant Byte of an
instruction word is always stored in a program memory
location with an even address (LSb = 0). To maintain
alignment with instruction boundaries, the PC
increments in steps of 2 and the LSb will always read
‘0’ (see Section 5.1.1 “Program Counter”).
Figure 5-4 shows an example of how instruction words
are stored in the program memory.
FIGURE 5-4:
INSTRUCTIONS IN PROGRAM MEMORY
Word Address
LSB = 1
LSB = 0
↓
Program Memory
Byte Locations →
000000h
000002h
000004h
000006h
000008h
00000Ah
00000Ch
00000Eh
000010h
000012h
000014h
Instruction 1:
Instruction 2:
MOVLW
GOTO
055h
0006h
0Fh
EFh
F0h
C1h
F4h
55h
03h
00h
23h
56h
Instruction 3:
MOVFF
123h, 456h
and used by the instruction sequence. If the first word
is skipped for some reason and the second word is
executed by itself, a NOP is executed instead. This is
necessary for cases when the two-word instruction is
preceded by a conditional instruction that changes the
PC. Example 5-4 shows how this works.
5.2.4
TWO-WORD INSTRUCTIONS
The standard PIC18 instruction set has four two-word
instructions: CALL, MOVFF, GOTO and LSFR. In all
cases, the second word of the instruction always has
‘1111’ as its four Most Significant bits; the other 12 bits
are literal data, usually a data memory address.
Note:
See Section 5.6 “PIC18 Instruction
Execution and the Extended Instruc-
tion Set” for information on two-word
instructions in the extended instruction set.
The use of ‘1111’ in the 4 MSbs of an instruction
specifies a special form of NOP. If the instruction is
executed in proper sequence – immediately after the
first word – the data in the second word is accessed
EXAMPLE 5-4:
CASE 1:
TWO-WORD INSTRUCTIONS
Source Code
Object Code
0110 0110 0000 0000 TSTFSZ
REG1
REG1, REG2 ; No, skip this word
; Execute this word as a NOP
; continue code
; is RAM location 0?
1100 0001 0010 0011
1111 0100 0101 0110
0010 0100 0000 0000
CASE 2:
MOVFF
ADDWF
REG3
Object Code
Source Code
TSTFSZ
0110 0110 0000 0000
1100 0001 0010 0011
1111 0100 0101 0110
0010 0100 0000 0000
REG1
; is RAM location 0?
MOVFF
REG1, REG2 ; Yes, execute this word
; 2nd word of instruction
ADDWF
REG3
; continue code
DS41303B-page 68
Advance Information
© 2007 Microchip Technology Inc.
PIC18F2XK20/4XK20
5.3.1
BANK SELECT REGISTER (BSR)
5.3
Data Memory Organization
Large areas of data memory require an efficient
addressing scheme to make rapid access to any
address possible. Ideally, this means that an entire
address does not need to be provided for each read or
write operation. For PIC18 devices, this is accom-
plished with a RAM banking scheme. This divides the
memory space into 16 contiguous banks of 256 bytes.
Depending on the instruction, each location can be
addressed directly by its full 12-bit address, or an 8-bit
low-order address and a 4-bit Bank Pointer.
Note:
The operation of some aspects of data
memory are changed when the PIC18
extended instruction set is enabled. See
Section 5.5 “Data Memory and the
Extended Instruction Set” for more
information.
The data memory in PIC18 devices is implemented as
static RAM. Each register in the data memory has a
12-bit address, allowing up to 4096 bytes of data
memory. The memory space is divided into as many as
16 banks that contain 256 bytes each. Figures 5-5
through 5-7 show the data memory organization for the
PIC18F2XK20/4XK20 devices.
Most instructions in the PIC18 instruction set make use
of the Bank Pointer, known as the Bank Select Register
(BSR). This SFR holds the 4 Most Significant bits of a
location’s address; the instruction itself includes the
8 Least Significant bits. Only the four lower bits of the
BSR are implemented (BSR<3:0>). The upper four bits
are unused; they will always read ‘0’ and cannot be
written to. The BSR can be loaded directly by using the
MOVLBinstruction.
The data memory contains Special Function Registers
(SFRs) and General Purpose Registers (GPRs). The
SFRs are used for control and status of the controller
and peripheral functions, while GPRs are used for data
storage and scratchpad operations in the user’s
application. Any read of an unimplemented location will
read as ‘0’s.
The value of the BSR indicates the bank in data
memory; the 8 bits in the instruction show the location
in the bank and can be thought of as an offset from the
bank’s lower boundary. The relationship between the
BSR’s value and the bank division in data memory is
shown in Figures 5-5 through 5-7.
The instruction set and architecture allow operations
across all banks. The entire data memory may be
accessed by Direct, Indirect or Indexed Addressing
modes. Addressing modes are discussed later in this
subsection.
Since up to 16 registers may share the same low-order
address, the user must always be careful to ensure that
the proper bank is selected before performing a data
read or write. For example, writing what should be
program data to an 8-bit address of F9h while the BSR
is 0Fh will end up resetting the program counter.
To ensure that commonly used registers (SFRs and
select GPRs) can be accessed in a single cycle, PIC18
devices implement an Access Bank. This is a 256-byte
memory space that provides fast access to SFRs and
the lower portion of GPR Bank 0 without using the Bank
Select Register (BSR). Section 5.3.2 “Access Bank”
provides a detailed description of the Access RAM.
While any bank can be selected, only those banks that
are actually implemented can be read or written to.
Writes to unimplemented banks are ignored, while
reads from unimplemented banks will return ‘0’s. Even
so, the STATUS register will still be affected as if the
operation was successful. The data memory maps in
Figures 5-5 through 5-7 indicate which banks are
implemented.
In the core PIC18 instruction set, only the MOVFF
instruction fully specifies the 12-bit address of the
source and target registers. This instruction ignores the
BSR completely when it executes. All other instructions
include only the low-order address as an operand and
must use either the BSR or the Access Bank to locate
their target registers.
© 2007 Microchip Technology Inc.
Advance Information
DS41303B-page 69
PIC18F2XK20/4XK20
FIGURE 5-5:
DATA MEMORY MAP FOR PIC18F23K20/43K20 DEVICES
When ‘a’ = 0:
The BSR is ignored and the
BSR<3:0>
Data Memory Map
Access Bank is used.
000h
05Fh
060h
0FFh
100h
00h
Access RAM
GPR
= 0000
= 0001
= 0010
The first 96 bytes are
general purpose RAM
(from Bank 0).
Bank 0
FFh
00h
The second 160 bytes are
Special Function Registers
(from Bank 15).
GPR
Bank 1
Bank 2
1FFh
200h
FFh
00h
FFh
00h
2FFh
300h
When ‘a’ = 1:
= 0011
The BSR specifies the Bank
used by the instruction.
Bank 3
Bank 4
Bank 5
Bank 6
Bank 7
Bank 8
Bank 9
Bank 10
Bank 11
Bank 12
Bank 13
3FFh
400h
FFh
00h
= 0100
= 0101
4FFh
500h
FFh
00h
5FFh
600h
FFh
00h
= 0110
= 0111
Access Bank
FFh
00h
6FFh
700h
00h
Access RAM Low
5Fh
Access RAM High
60h
FFh
00h
7FFh
800h
(SFRs)
= 1000
= 1001
FFh
8FFh
900h
FFh
00h
Unused
Read 00h
9FFh
A00h
FFh
00h
= 1010
= 1011
= 1100
= 1101
AFFh
B00h
FFh
00h
BFFh
C00h
FFh
00h
CFFh
D00h
FFh
00h
DFFh
E00h
FFh
00h
= 1110
= 1111
Bank 14
Bank 15
EFFh
F00h
F5Fh
F60h
FFFh
FFh
00h
Unused
SFR
FFh
DS41303B-page 70
Advance Information
© 2007 Microchip Technology Inc.
PIC18F2XK20/4XK20
FIGURE 5-6:
DATA MEMORY MAP FOR PIC18F24K20/44K20 DEVICES
When ‘a’ = 0:
The BSR is ignored and the
BSR<3:0>
Data Memory Map
Access Bank is used.
000h
05Fh
060h
0FFh
100h
00h
Access RAM
GPR
= 0000
= 0001
= 0010
The first 96 bytes are
general purpose RAM
(from Bank 0).
Bank 0
FFh
00h
The second 160 bytes are
Special Function Registers
(from Bank 15).
GPR
GPR
Bank 1
Bank 2
1FFh
200h
FFh
00h
FFh
00h
2FFh
300h
When ‘a’ = 1:
= 0011
The BSR specifies the Bank
used by the instruction.
Bank 3
Bank 4
Bank 5
Bank 6
Bank 7
Bank 8
Bank 9
Bank 10
Bank 11
Bank 12
Bank 13
3FFh
400h
FFh
00h
= 0100
= 0101
4FFh
500h
FFh
00h
5FFh
600h
FFh
00h
= 0110
= 0111
Access Bank
FFh
00h
6FFh
700h
00h
Access RAM Low
5Fh
Access RAM High
60h
FFh
00h
7FFh
800h
(SFRs)
= 1000
= 1001
FFh
8FFh
900h
FFh
00h
Unused
Read 00h
9FFh
A00h
FFh
00h
= 1010
= 1011
= 1100
= 1101
AFFh
B00h
FFh
00h
BFFh
C00h
FFh
00h
CFFh
D00h
FFh
00h
DFFh
E00h
FFh
00h
= 1110
= 1111
Bank 14
Bank 15
EFFh
F00h
F5Fh
F60h
FFFh
FFh
00h
Unused
SFR
FFh
© 2007 Microchip Technology Inc.
Advance Information
DS41303B-page 71
PIC18F2XK20/4XK20
FIGURE 5-7:
DATA MEMORY MAP FOR PIC18F25K20/45K20 DEVICES
When ‘a’ = 0:
The BSR is ignored and the
BSR<3:0>
Data Memory Map
Access Bank is used.
000h
05Fh
060h
0FFh
100h
00h
Access RAM
GPR
= 0000
= 0001
= 0010
The first 96 bytes are
general purpose RAM
(from Bank 0).
Bank 0
FFh
00h
The second 160 bytes are
Special Function Registers
(from Bank 15).
GPR
GPR
GPR
GPR
GPR
Bank 1
Bank 2
1FFh
200h
FFh
00h
FFh
00h
2FFh
300h
When ‘a’ = 1:
= 0011
The BSR specifies the Bank
used by the instruction.
Bank 3
Bank 4
Bank 5
Bank 6
Bank 7
Bank 8
Bank 9
Bank 10
Bank 11
Bank 12
Bank 13
3FFh
400h
FFh
00h
= 0100
= 0101
4FFh
500h
FFh
00h
5FFh
600h
FFh
00h
= 0110
= 0111
Access Bank
FFh
00h
6FFh
700h
00h
Access RAM Low
5Fh
Access RAM High
60h
FFh
00h
7FFh
800h
(SFRs)
= 1000
= 1001
FFh
8FFh
900h
FFh
00h
9FFh
A00h
FFh
00h
Unused
Read 00h
= 1010
= 1011
= 1100
= 1101
AFFh
B00h
FFh
00h
BFFh
C00h
FFh
00h
CFFh
D00h
FFh
00h
DFFh
E00h
FFh
00h
= 1110
= 1111
Bank 14
Bank 15
EFFh
F00h
F5Fh
F60h
FFFh
FFh
00h
Unused
SFR
FFh
DS41303B-page 72
Advance Information
© 2007 Microchip Technology Inc.
PIC18F2XK20/4XK20
FIGURE 5-8:
DATA MEMORY MAP FOR PIC18F26K20/46K20 DEVICES
When ‘a’ = 0:
The BSR is ignored and the
BSR<3:0>
Data Memory Map
Access Bank is used.
000h
05Fh
060h
0FFh
100h
00h
Access RAM
GPR
= 0000
= 0001
= 0010
The first 96 bytes are
general purpose RAM
(from Bank 0).
Bank 0
FFh
00h
The second 160 bytes are
Special Function Registers
(from Bank 15).
GPR
GPR
GPR
GPR
Bank 1
Bank 2
1FFh
200h
FFh
00h
FFh
00h
2FFh
300h
When ‘a’ = 1:
= 0011
The BSR specifies the Bank
used by the instruction.
Bank 3
Bank 4
Bank 5
Bank 6
Bank 7
Bank 8
Bank 9
Bank 10
Bank 11
Bank 12
Bank 13
3FFh
400h
FFh
00h
= 0100
= 0101
4FFh
500h
FFh
00h
GPR
GPR
GPR
GPR
GPR
5FFh
600h
FFh
00h
= 0110
= 0111
Access Bank
FFh
00h
6FFh
700h
00h
Access RAM Low
5Fh
Access RAM High
60h
FFh
00h
7FFh
800h
(SFRs)
= 1000
= 1001
FFh
8FFh
900h
FFh
00h
9FFh
A00h
FFh
00h
= 1010
= 1011
= 1100
= 1101
GPR
GPR
GPR
GPR
GPR
AFFh
B00h
FFh
00h
BFFh
C00h
FFh
00h
CFFh
D00h
FFh
00h
DFFh
E00h
FFh
00h
= 1110
= 1111
Bank 14
Bank 15
EFFh
F00h
F5Fh
F60h
FFFh
FFh
00h
GPR
SFR
FFh
© 2007 Microchip Technology Inc.
Advance Information
DS41303B-page 73
PIC18F2XK20/4XK20
FIGURE 5-9:
USE OF THE BANK SELECT REGISTER (DIRECT ADDRESSING)
Memory
Data
(2)
(1)
From Opcode
BSR
000h
100h
7
0
7
0
00h
Bank 0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
1
1
FFh
00h
Bank 1
Bank 2
(2)
Bank Select
FFh
00h
200h
300h
FFh
00h
Bank 3
through
Bank 13
FFh
00h
E00h
Bank 14
Bank 15
FFh
00h
F00h
FFFh
FFh
Note 1: The Access RAM bit of the instruction can be used to force an override of the selected bank (BSR<3:0>) to
the registers of the Access Bank.
2: The MOVFF instruction embeds the entire 12-bit address in the instruction.
DS41303B-page 74
Advance Information
© 2007 Microchip Technology Inc.
PIC18F2XK20/4XK20
5.3.2
ACCESS BANK
5.3.3
GENERAL PURPOSE REGISTER
FILE
While the use of the BSR with an embedded 8-bit
address allows users to address the entire range of
data memory, it also means that the user must always
ensure that the correct bank is selected. Otherwise,
data may be read from or written to the wrong location.
This can be disastrous if a GPR is the intended target
of an operation, but an SFR is written to instead.
Verifying and/or changing the BSR for each read or
write to data memory can become very inefficient.
PIC18 devices may have banked memory in the GPR
area. This is data RAM, which is available for use by all
instructions. GPRs start at the bottom of Bank 0
(address 000h) and grow upwards towards the bottom of
the SFR area. GPRs are not initialized by a Power-on
Reset and are unchanged on all other Resets.
5.3.4
SPECIAL FUNCTION REGISTERS
The Special Function Registers (SFRs) are registers
used by the CPU and peripheral modules for controlling
the desired operation of the device. These registers are
implemented as static RAM. SFRs start at the top of
data memory (FFFh) and extend downward to occupy
the top portion of Bank 15 (F60h to FFFh). A list of
these registers is given in Table 5-1 and Table 5-2.
To streamline access for the most commonly used data
memory locations, the data memory is configured with
an Access Bank, which allows users to access a
mapped block of memory without specifying a BSR.
The Access Bank consists of the first 96 bytes of mem-
ory (00h-5Fh) in Bank 0 and the last 160 bytes of mem-
ory (60h-FFh) in Block 15. The lower half is known as
the “Access RAM” and is composed of GPRs. This
upper half is also where the device’s SFRs are
mapped. These two areas are mapped contiguously in
the Access Bank and can be addressed in a linear
fashion by an 8-bit address (Figures 5-5 through 5-7).
The SFRs can be classified into two sets: those
associated with the “core” device functionality (ALU,
Resets and interrupts) and those related to the
peripheral functions. The Reset and interrupt registers
are described in their respective chapters, while the
ALU’s STATUS register is described later in this
section. Registers related to the operation of a
peripheral feature are described in the chapter for that
peripheral.
The Access Bank is used by core PIC18 instructions
that include the Access RAM bit (the ‘a’ parameter in
the instruction). When ‘a’ is equal to ‘1’, the instruction
uses the BSR and the 8-bit address included in the
opcode for the data memory address. When ‘a’ is ‘0’,
however, the instruction is forced to use the Access
Bank address map; the current value of the BSR is
ignored entirely.
The SFRs are typically distributed among the
peripherals whose functions they control. Unused SFR
locations are unimplemented and read as ‘0’s.
Using this “forced” addressing allows the instruction to
operate on a data address in a single cycle, without
updating the BSR first. For 8-bit addresses of 60h and
above, this means that users can evaluate and operate
on SFRs more efficiently. The Access RAM below 60h
is a good place for data values that the user might need
to access rapidly, such as immediate computational
results or common program variables. Access RAM
also allows for faster and more code efficient context
saving and switching of variables.
The mapping of the Access Bank is slightly different
when the extended instruction set is enabled (XINST
Configuration bit = 1). This is discussed in more detail
in Section 5.5.3 “Mapping the Access Bank in
Indexed Literal Offset Mode”.
© 2007 Microchip Technology Inc.
Advance Information
DS41303B-page 75
PIC18F2XK20/4XK20
TABLE 5-1:
Address
SPECIAL FUNCTION REGISTER MAP FOR PIC18F2XK20/4XK20 DEVICES
Name
Address
FD7h
Name
Address
FAFh
Name
Address
F87h
Name
(2)
FFFh
FFEh
FFDh
FFCh
FFBh
FFAh
FF9h
FF8h
FF7h
FF6h
FF5h
FF4h
FF3h
FF2h
FF1h
FF0h
FEFh
TOSU
TOSH
TMR0H
TMR0L
T0CON
SPBRG
RCREG
TXREG
TXSTA
—
(2)
FD6h
FD5h
FD4h
FD3h
FAEh
FADh
FACh
FABh
FAAh
FA9h
FA8h
F86h
F85h
F84h
F83h
F82h
F81h
F80h
F7Fh
F7Eh
F7Dh
F7Ch
—
(2)
TOSL
—
(2)
STKPTR
PCLATU
PCLATH
PCL
—
PORTE
PORTD(3)
PORTC
PORTB
PORTA
ANSELH
ANSEL
IOCB
OSCCON
RCSTA
EEADRH
EEADR
EEDATA
FD2h HLVDCON
FD1h
FD0h
FCFh
FCEh
FCDh
FCCh
FCBh
FCAh
FC9h
FC8h
FC7h
FC6h
FC5h
FC4h
FC3h
FC2h
FC1h
FC0h
FBFh
FBEh
WDTCON
RCON
TBLPTRU
TBLPTRH
TBLPTRL
TABLAT
PRODH
PRODL
INTCON
INTCON2
INTCON3
INDF0(1)
TMR1H
FA7h EECON2(1)
TMR1L
FA6h
FA5h
FA4h
FA3h
FA2h
FA1h
FA0h
F9Fh
F9Eh
F9Dh
F9Ch
EECON1
(2)
T1CON
—
(2)
TMR2
—
WPUB
(2)
PR2
—
F7Bh CM1CON0
F7Ah CM2CON0
F79h CM2CON1
T2CON
IPR2
PIR2
PIE2
IPR1
PIR1
PIE1
SSPBUF
SSPADD
SSPSTAT
SSPCON1
SSPCON2
ADRESH
ADRESL
ADCON0
ADCON1
ADCON2
CCPR1H
CCPR1L
F78h
F77h
F76h
F75h
F74h
F73h
F72h
F71h
F70h
F6Fh
F6Eh
F6Dh
F6Ch
F6Bh
F6Ah
F69h
F68h
F67h
F66h
F65h
F64h
F63h
F62h
F61h
F60h
SLRCON
SSPMSK
FEEh POSTINC0(1)
FEDh POSTDEC0(1)
FECh PREINC0(1)
FEBh PLUSW0(1)
—
(2)
(2)
—
(2)
(2)
—
—
(2)
F9Bh OSCTUNE
—
(2)
(2)
FEAh
FE9h
FE8h
FE7h
FE6h POSTINC1(1)
FE5h POSTDEC1(1)
FE4h PREINC1(1)
FE3h PLUSW1(1)
FSR0H
FSR0L
WREG
INDF1(1)
F9Ah
F99h
F98h
F97h
F96h
F95h
F94h
F93h
F92h
F91h
F90h
F8Fh
F8Eh
F8Dh
F8Ch
F8Bh
F8Ah
F89h
F88h
—
—
—
—
—
(2)
(2)
(2)
(2)
—
(2)
—
(2)
—
TRISE(3)
TRISD(3)
TRISC
—
(2)
(2)
FBDh CCP1CON
—
(2)
FBCh
FBBh
CCPR2H
CCPR2L
—
(2)
TRISB
—
(2)
FE2h
FE1h
FE0h
FDFh
FDEh POSTINC2(1)
FDDh POSTDEC2(1)
FDCh PREINC2(1)
FDBh PLUSW2(1)
FSR1H
FSR1L
BSR
FBAh CCP2CON
FB9h PSTRCON
TRISA
—
(2)
(2)
—
—
(2)
(2)
FB8h
BAUDCTL
—
—
(2)
(2)
INDF2(1)
FB7h PWM1CON
—
—
(2)
(2)
FB6h
FB5h
ECCP1AS
CVRCON
—
—
LATE(3)
LATD(3)
LATC
—
(2)
(2)
FB4h CVRCON2
—
(2)
FB3h
FB2h
FB1h
FB0h
TMR3H
TMR3L
—
(2)
FDAh
FD9h
FD8h
FSR2H
FSR2L
LATB
—
(2)
T3CON
SPBRGH
LATA
—
(2)
(2)
STATUS
—
—
Note 1: This is not a physical register.
2: Unimplemented registers are read as ‘0’.
3: This register is not available on PIC18F2XK20 devices.
DS41303B-page 76
Advance Information
© 2007 Microchip Technology Inc.
PIC18F2XK20/4XK20
TABLE 5-2:
File Name
TOSU
REGISTER FILE SUMMARY (PIC18F2XK20/4XK20)
Value on
POR, BOR on page:
Details
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
—
—
—
Top-of-Stack Upper Byte (TOS<20:16>)
---0 0000 57, 64
0000 0000 57, 64
0000 0000 57, 64
00-0 0000 57, 65
---0 0000 57, 64
0000 0000 57, 64
0000 0000 57, 64
--00 0000 57, 90
0000 0000 57, 90
0000 0000 57, 90
0000 0000 57, 90
xxxx xxxx 57, 101
xxxx xxxx 57, 101
0000 000x 57, 105
1111 -1-1 57, 106
11-0 0-00 57, 107
TOSH
Top-of-Stack, High Byte (TOS<15:8>)
Top-of-Stack, Low Byte (TOS<7:0>)
TOSL
STKPTR
PCLATU
PCLATH
PCL
STKFUL
—
STKUNF
—
—
—
SP4
SP3
SP2
SP1
SP0
Holding Register for PC<20:16>
Holding Register for PC<15:8>
PC, Low Byte (PC<7:0>)
TBLPTRU
TBLPTRH
TBLPTRL
TABLAT
PRODH
PRODL
INTCON
INTCON2
INTCON3
INDF0
—
—
bit 21
Program Memory Table Pointer Upper Byte (TBLPTR<20:16>)
Program Memory Table Pointer, High Byte (TBLPTR<15:8>)
Program Memory Table Pointer, Low Byte (TBLPTR<7:0>)
Program Memory Table Latch
Product Register, High Byte
Product Register, Low Byte
GIE/GIEH
RBPU
PEIE/GIEL
INTEDG0
INT1IP
TMR0IE
INTEDG1
—
INT0IE
INTEDG2
INT2IE
RBIE
—
TMR0IF
TMR0IP
—
INT0IF
—
RBIF
RBIP
INT2IP
INT1IE
INT2IF
INT1IF
Uses contents of FSR0 to address data memory – value of FSR0 not changed (not a physical register)
N/A
N/A
N/A
N/A
N/A
57, 82
57, 82
57, 82
57, 82
57, 82
POSTINC0 Uses contents of FSR0 to address data memory – value of FSR0 post-incremented (not a physical register)
POSTDEC0 Uses contents of FSR0 to address data memory – value of FSR0 post-decremented (not a physical register)
PREINC0
PLUSW0
Uses contents of FSR0 to address data memory – value of FSR0 pre-incremented (not a physical register)
Uses contents of FSR0 to address data memory – value of FSR0 pre-incremented (not a physical register) –
value of FSR0 offset by W
FSR0H
FSR0L
WREG
INDF1
—
—
—
—
Indirect Data Memory Address Pointer 0, High Byte
---- 0000 57, 82
xxxx xxxx 57, 82
Indirect Data Memory Address Pointer 0, Low Byte
Working Register
xxxx xxxx
N/A
57
Uses contents of FSR1 to address data memory – value of FSR1 not changed (not a physical register)
57, 82
57, 82
57, 82
57, 82
57, 82
POSTINC1 Uses contents of FSR1 to address data memory – value of FSR1 post-incremented (not a physical register)
POSTDEC1 Uses contents of FSR1 to address data memory – value of FSR1 post-decremented (not a physical register)
N/A
N/A
PREINC1
PLUSW1
Uses contents of FSR1 to address data memory – value of FSR1 pre-incremented (not a physical register)
N/A
Uses contents of FSR1 to address data memory – value of FSR1 pre-incremented (not a physical register) –
value of FSR1 offset by W
N/A
FSR1H
FSR1L
BSR
—
—
—
—
Indirect Data Memory Address Pointer 1, High Byte
---- 0000 58, 82
xxxx xxxx 58, 82
---- 0000 58, 69
Indirect Data Memory Address Pointer 1, Low Byte
—
—
—
—
Bank Select Register
INDF2
Uses contents of FSR2 to address data memory – value of FSR2 not changed (not a physical register)
N/A
N/A
N/A
N/A
N/A
58, 82
58, 82
58, 82
58, 82
58, 82
POSTINC2 Uses contents of FSR2 to address data memory – value of FSR2 post-incremented (not a physical register)
POSTDEC2 Uses contents of FSR2 to address data memory – value of FSR2 post-decremented (not a physical register)
PREINC2
PLUSW2
Uses contents of FSR2 to address data memory – value of FSR2 pre-incremented (not a physical register)
Uses contents of FSR2 to address data memory – value of FSR2 pre-incremented (not a physical register) –
value of FSR2 offset by W
FSR2H
FSR2L
STATUS
—
—
—
—
Indirect Data Memory Address Pointer 2, High Byte
---- 0000 58, 82
xxxx xxxx 58, 82
---x xxxx 58, 80
Indirect Data Memory Address Pointer 2, Low Byte
—
—
—
N
OV
Z
DC
C
Legend:
x= unknown, u= unchanged, —= unimplemented, q= value depends on condition
Note 1:
The SBOREN bit is only available when the BOREN<1:0> Configuration bits = 01; otherwise it is disabled and reads as ‘0’. See
Section 4.4 “Brown-out Reset (BOR)”.
2:
3:
4:
5:
6:
These registers and/or bits are not implemented on 28-pin devices and are read as ‘0’. Reset values are shown for 40/44-pin devices;
individual unimplemented bits should be interpreted as ‘-’.
The PLLEN bit is only available in specific oscillator configuration; otherwise it is disabled and reads as ‘0’. See Section 2.6.2 “PLL in
HFINTOSC Modes”.
The RE3 bit is only available when Master Clear Reset is disabled (MCLRE Configuration bit = 0). Otherwise, RE3 reads as ‘0’. This bit is
read-only.
RA6/RA7 and their associated latch and direction bits are individually configured as port pins based on various primary oscillator modes.
When disabled, these bits read as ‘0’.
All bits of the ANSELH register initialize to ‘0’ if the PBADEN bit of CONFIG3H is ‘0’.
© 2007 Microchip Technology Inc.
Advance Information
DS41303B-page 77
PIC18F2XK20/4XK20
TABLE 5-2:
REGISTER FILE SUMMARY (PIC18F2XK20/4XK20) (CONTINUED)
Value on
POR, BOR on page:
Details
File Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
TMR0H
Timer0 Register, High Byte
Timer0 Register, Low Byte
0000 0000 58, 139
xxxx xxxx 58, 139
1111 1111 58, 137
0011 qq00 27, 58
0-00 0101 58, 283
--- ---0 58, 299
TMR0L
T0CON
TMR0ON
IDLEN
T08BIT
IRCF2
—
T0CS
IRCF1
IRVST
—
T0SE
IRCF0
HLVDEN
—
PSA
OSTS
HLVDL3
—
T0PS2
IOFS
T0PS1
SCS1
HLVDL1
—
T0PS0
SCS0
OSCCON
HLVDCON
WDTCON
VDIRMAG
—
HLVDL2
—
HLVDL0
SWDTEN
—
RCON
IPEN
SBOREN(1)
—
RI
TO
PD
POR
BOR
0q-1 11q0 49, 56,
114
TMR1H
TMR1L
Timer1 Register, High Byte
Timer1 Register, Low Bytes
xxxx xxxx 58, 146
xxxx xxxx 58, 146
T1CON
TMR2
RD16
T1RUN
T1CKPS1
T1CKPS0
T1OSCEN
T1SYNC
TMR2ON
TMR1CS
T2CKPS1
TMR1ON 0000 0000 58, 141
0000 0000 58, 148
Timer2 Register
PR2
Timer2 Period Register
T2OUTPS3 T2OUTPS2 T2OUTPS1 T2OUTPS0
SSP Receive Buffer/Transmit Register
1111 1111 58, 148
T2CON
SSPBUF
—
T2CKPS0 -000 0000 58, 147
xxxx xxxx 58, 193,
194
SSPADD
SSPSTAT
SSP Address Register in I2C™ Slave Mode. SSP Baud Rate Reload Register in I2C Master Mode.
0000 0000 58, 194
SMP
WCOL
GCEN
CKE
D/A
P
S
R/W
SSPM2
PEN
UA
BF
0000 0000 58, 187,
196
SSPCON1
SSPOV
ACKSTAT
SSPEN
ACKDT
CKP
SSPM3
RCEN
SSPM1
RSEN
SSPM0
SEN
0000 0000 58, 187,
196
SSPCON2
ADRESH
ADRESL
ACKEN
0000 0000 58, 197
xxxx xxxx 59, 267
xxxx xxxx 59, 267
A/D Result Register, High Byte
A/D Result Register, Low Byte
ADCON0
ADCON1
ADCON2
CCPR1H
CCPR1L
CCP1CON
CCPR2H
CCPR2L
CCP2CON
PSTRCON
BAUDCTL
PWM1CON
ECCP1AS
CVRCON
CVRCON2
TMR3H
—
—
—
—
—
CHS3
VCFG1
ACQT2
CHS2
VCFG0
ACQT1
CHS1
—
CHS0
—
GO/DONE
—
ADON
—
--00 0000 59, 261
--00 ---- 59, 262
0-00 0000 59, 263
xxxx xxxx 59, 154
xxxx xxxx 59, 154
ADFM
ACQT0
ADCS2
ADCS1
ADCS0
Capture/Compare/PWM Register 1, High Byte
Capture/Compare/PWM Register 1, Low Byte
P1M1
P1M0
DC1B1
DC1B0
CCP1M3
CCP1M2
CCP1M1
CCP1M0 0000 0000 59, 165
xxxx xxxx 59, 154
Capture/Compare/PWM Register 2, High Byte
Capture/Compare/PWM Register 2, Low Byte
xxxx xxxx 59, 154
—
—
—
DC2B1
—
DC2B0
STRSYNC
CKTXP
PDC4
CCP2M3
STRD
BRG16
PDC3
PSSAC1
CVR3
—
CCP2M2
STRC
—
CCP2M1
STRB
WUE
CCP2M0 --00 0000 59, 153
—
STRA
ABDEN
PDC0
---0 0001 59, 179
0100 0-00 59, 238
0000 0000 59, 178
ABDOVF
PRSEN
ECCPASE
CVREN
FVREN
RCIDL
PDC6
DTRXP
PDC5
ECCPAS1
CVRR
—
PDC2
PSSAC0
CVR2
—
PDC1
PSSBD1
CVR1
—
ECCPAS2
CVROE
FVRST
ECCPAS0
CVRSS
—
PSSBD0 0000 0000 59, 175
CVR0
—
0000 0000 59, 281
00-- ---- 59, 282
xxxx xxxx 59, 151
xxxx xxxx 59, 151
Timer3 Register, High Byte
Timer3 Register, Low Byte
TMR3L
T3CON
RD16
T3CCP2
T3CKPS1
T3CKPS0
T3CCP1
T3SYNC
TMR3CS
TMR3ON 0000 0000 59, 149
Legend:
x= unknown, u= unchanged, —= unimplemented, q= value depends on condition
Note 1:
The SBOREN bit is only available when the BOREN<1:0> Configuration bits = 01; otherwise it is disabled and reads as ‘0’. See
Section 4.4 “Brown-out Reset (BOR)”.
2:
3:
4:
5:
6:
These registers and/or bits are not implemented on 28-pin devices and are read as ‘0’. Reset values are shown for 40/44-pin devices;
individual unimplemented bits should be interpreted as ‘-’.
The PLLEN bit is only available in specific oscillator configuration; otherwise it is disabled and reads as ‘0’. See Section 2.6.2 “PLL in
HFINTOSC Modes”.
The RE3 bit is only available when Master Clear Reset is disabled (MCLRE Configuration bit = 0). Otherwise, RE3 reads as ‘0’. This bit is
read-only.
RA6/RA7 and their associated latch and direction bits are individually configured as port pins based on various primary oscillator modes.
When disabled, these bits read as ‘0’.
All bits of the ANSELH register initialize to ‘0’ if the PBADEN bit of CONFIG3H is ‘0’.
DS41303B-page 78
Advance Information
© 2007 Microchip Technology Inc.
PIC18F2XK20/4XK20
TABLE 5-2:
REGISTER FILE SUMMARY (PIC18F2XK20/4XK20) (CONTINUED)
Value on
POR, BOR on page:
Details
File Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
SPBRGH
SPBRG
RCREG
TXREG
TXSTA
RCSTA
EEADR
EEADRH
EEDATA
EECON2
EECON1
IPR2
EUSART Baud Rate Generator Register, High Byte
EUSART Baud Rate Generator Register, Low Byte
EUSART Receive Register
0000 0000 59, 227
0000 0000 59, 227
0000 0000 59, 228
0000 0000 59, 227
0000 0010 59, 236
0000 000x 59, 237
EUSART Transmit Register
CSRC
SPEN
EEADR7
—
TX9
RX9
TXEN
SREN
EEADR5
—
SYNC
CREN
EEADR4
—
SENDB
ADDEN
EEADR3
—
BRGH
FERR
EEADR2
—
TRMT
OERR
TX9D
RX9D
EEADR6
—
EEADR1
EEADR9
EEADR0 0000 0000 59, 88, 97
EEADR8 ---- --00 59, 88, 97
0000 0000 59, 88, 97
EEPROM Data Register
EEPROM Control Register 2 (not a physical register)
0000 0000 59, 88, 97
EEPGD
OSCFIP
OSCFIF
OSCFIE
PSPIP(2)
PSPIF(2)
PSPIE(2)
INTSRC
IBF
CFGS
C1IP
—
FREE
EEIP
WRERR
BCLIP
BCLIF
BCLIE
SSPIP
SSPIF
SSPIE
TUN3
—
WREN
HLVDIP
HLVDIF
HLVDIE
CCP1IP
CCP1IF
CCP1IE
TUN2
WR
RD
xx-0 x000 59, 89, 97
1111 1111 60, 113
0000 0000 60, 109
0000 0000 60, 111
1111 1111 60, 112
0000 0000 60, 108
0000 0000 60, 110
0q00 0000 31, 60
0000 -111 60, 130
1111 1111 60, 126
1111 1111 60, 123
1111 1111 60, 120
1111 1111 60, 117
---- -xxx 60, 129
C2IP
C2IF
C2IE
RCIP
RCIF
RCIE
TUN5
IBOV
TMR3IP
TMR3IF
TMR3IE
TMR2IP
TMR2IF
TMR2IE
TUN1
CCP2IP
CCP2IF
CCP2IE
TMR1IP
TMR1IF
TMR1IE
TUN0
PIR2
C1IF
EEIF
PIE2
C1IE
EEIE
IPR1
ADIP
TXIP
PIR1
ADIF
TXIF
PIE1
ADIE
PLLEN(3)
TXIE
OSCTUNE
TRISE(2)
TRISD(2)
TRISC
TRISB
TUN4
PSPMODE
OBF
TRISE2
TRISE1
TRISE0
PORTD Data Direction Control Register
PORTC Data Direction Control Register
PORTB Data Direction Control Register
TRISA
LATE(2)
TRISA7(5)
TRISA6(5) Data Direction Control Register for PORTA
—
—
—
—
—
PORTE Data Latch Register
(Read and Write to Data Latch)
LATD(2)
LATC
PORTD Data Latch Register (Read and Write to Data Latch)
PORTC Data Latch Register (Read and Write to Data Latch)
PORTB Data Latch Register (Read and Write to Data Latch)
xxxx xxxx 60, 126
xxxx xxxx 60, 123
xxxx xxxx 60, 120
xxxx xxxx 60, 117
---- x000 60, 129
xxxx xxxx 60, 126
xxxx xxxx 60, 123
xxx0 0000 60, 120
xx0x 0000 60, 117
---1 1111 60, 133
1111 1111 60, 132
0000 ---- 60, 120
1111 1111 60, 120
0000 0000 60, 274
0000 0000 60, 275
0000 ---- 61, 277
---1 1111 61, 134
1111 1111 61, 204
LATB
LATA
LATA7(5)
LATA6(5) PORTA Data Latch Register (Read and Write to Data Latch)
PORTE
PORTD(2)
PORTC
PORTB
PORTA
ANSELH(6)
ANSEL
—
—
RD6
—
RD5
—
RE3(4)
RE2(2)
RE1(2)
RE0(2)
RD0
RD7
RD4
RD3
RD2
RD1
RC7
RC6
RC5
RC4
RC3
RC2
RC1
RC0
RB7
RB6
RB5
RB4
RB3
RB2
RB1
RB0
RA7(5)
RA6(5)
RA5
RA4
RA3
RA2
RA1
RA0
—
—
—
ANS12
ANS4
IOCB4
WPUB4
C1POL
C2POL
C2RSEL
SLRE
MSK4
ANS11
ANS3
—
ANS10
ANS2
—
ANS9
ANS1
—
ANS8
ANS0
—
ANS7(2)
IOCB7
WPUB7
C1ON
C2ON
MC1OUT
—
ANS6(2)
IOCB6
WPUB6
C1OUT
C2OUT
MC2OUT
—
ANS5(2)
IOCB5
WPUB5
C1OE
C2OE
C1RSEL
—
IOCB
WPUB
WPUB3
C1SP
C2SP
—
WPUB2
C1R
WPUB1
C1CH1
C2CH1
—
WPUB0
C1CH0
C2CH0
—
CM1CON0
CM2CON0
CM2CON1
SLRCON
SSPMSK
C2R
—
SLRD
MSK3
SLRC
MSK2
SLRB
MSK1
SLRA
MSK0
MSK7
MSK6
MSK5
Legend:
x= unknown, u= unchanged, —= unimplemented, q= value depends on condition
Note 1:
The SBOREN bit is only available when the BOREN<1:0> Configuration bits = 01; otherwise it is disabled and reads as ‘0’. See
Section 4.4 “Brown-out Reset (BOR)”.
2:
3:
4:
5:
6:
These registers and/or bits are not implemented on 28-pin devices and are read as ‘0’. Reset values are shown for 40/44-pin devices;
individual unimplemented bits should be interpreted as ‘-’.
The PLLEN bit is only available in specific oscillator configuration; otherwise it is disabled and reads as ‘0’. See Section 2.6.2 “PLL in
HFINTOSC Modes”.
The RE3 bit is only available when Master Clear Reset is disabled (MCLRE Configuration bit = 0). Otherwise, RE3 reads as ‘0’. This bit is
read-only.
RA6/RA7 and their associated latch and direction bits are individually configured as port pins based on various primary oscillator modes.
When disabled, these bits read as ‘0’.
All bits of the ANSELH register initialize to ‘0’ if the PBADEN bit of CONFIG3H is ‘0’.
© 2007 Microchip Technology Inc.
Advance Information
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PIC18F2XK20/4XK20
It is recommended that only BCF, BSF, SWAPF, MOVFF
and MOVWFinstructions are used to alter the STATUS
register, because these instructions do not affect the Z,
C, DC, OV or N bits in the STATUS register.
5.3.5
STATUS REGISTER
The STATUS register, shown in Register 5-2, contains
the arithmetic status of the ALU. As with any other SFR,
it can be the operand for any instruction.
For other instructions that do not affect Status bits, see
the instruction set summaries in Table 24-2 and
Table 24-3.
If the STATUS register is the destination for an instruc-
tion that affects the Z, DC, C, OV or N bits, the results
of the instruction are not written; instead, the STATUS
register is updated according to the instruction per-
formed. Therefore, the result of an instruction with the
STATUS register as its destination may be different
than intended. As an example, CLRF STATUSwill set
the Z bit and leave the remaining Status bits
unchanged (‘000u u1uu’).
Note:
The C and DC bits operate as the borrow
and digit borrow bits, respectively, in
subtraction.
REGISTER 5-2:
STATUS: STATUS REGISTER
U-0
—
U-0
—
U-0
—
R/W-x
N
R/W-x
OV
R/W-x
Z
R/W-x
DC(1)
R/W-x
C(1)
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7-5
bit 4
Unimplemented: Read as ‘0’
N: Negative bit
This bit is used for signed arithmetic (two’s complement). It indicates whether the result was negative
(ALU MSB = 1).
1= Result was negative
0= Result was positive
bit 3
bit 2
OV: Overflow bit
This bit is used for signed arithmetic (two’s complement). It indicates an overflow of the 7-bit magni-
tude which causes the sign bit (bit 7 of the result) to change state.
1= Overflow occurred for signed arithmetic (in this arithmetic operation)
0= No overflow occurred
Z: Zero bit
1= The result of an arithmetic or logic operation is zero
0= The result of an arithmetic or logic operation is not zero
bit 1
bit 0
DC: Digit Carry/Borrow bit (ADDWF, ADDLW,SUBLW,SUBWFinstructions)(1)
1= A carry-out from the 4th low-order bit of the result occurred
0= No carry-out from the 4th low-order bit of the result
C: Carry/Borrow bit (ADDWF, ADDLW, SUBLW, SUBWF instructions)(1)
1= A carry-out from the Most Significant bit of the result occurred
0= No carry-out from the Most Significant bit of the result occurred
Note 1: For Borrow, the polarity is reversed. A subtraction is executed by adding the two’s complement of the
second operand. For rotate (RRF, RLF) instructions, this bit is loaded with either the high-order or low-order
bit of the source register.
DS41303B-page 80
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PIC18F2XK20/4XK20
The Access RAM bit ‘a’ determines how the address is
interpreted. When ‘a’ is ‘1’, the contents of the BSR
(Section 5.3.1 “Bank Select Register (BSR)”) are
used with the address to determine the complete 12-bit
address of the register. When ‘a’ is ‘0’, the address is
interpreted as being a register in the Access Bank.
Addressing that uses the Access RAM is sometimes
also known as Direct Forced Addressing mode.
5.4
Data Addressing Modes
Note:
The execution of some instructions in the
core PIC18 instruction set are changed
when the PIC18 extended instruction set is
enabled. See Section 5.5 “Data Memory
and the Extended Instruction Set” for
more information.
A few instructions, such as MOVFF, include the entire
12-bit address (either source or destination) in their
opcodes. In these cases, the BSR is ignored entirely.
While the program memory can be addressed in only
one way – through the program counter – information
in the data memory space can be addressed in several
ways. For most instructions, the addressing mode is
fixed. Other instructions may use up to three modes,
depending on which operands are used and whether or
not the extended instruction set is enabled.
The destination of the operation’s results is determined
by the destination bit ‘d’. When ‘d’ is ‘1’, the results are
stored back in the source register, overwriting its origi-
nal contents. When ‘d’ is ‘0’, the results are stored in
the W register. Instructions without the ‘d’ argument
have a destination that is implicit in the instruction; their
destination is either the target register being operated
on or the W register.
The addressing modes are:
• Inherent
• Literal
• Direct
5.4.3
INDIRECT ADDRESSING
• Indirect
Indirect addressing allows the user to access a location
in data memory without giving a fixed address in the
instruction. This is done by using File Select Registers
(FSRs) as pointers to the locations which are to be read
or written. Since the FSRs are themselves located in
RAM as Special File Registers, they can also be
directly manipulated under program control. This
makes FSRs very useful in implementing data struc-
tures, such as tables and arrays in data memory.
An additional addressing mode, Indexed Literal Offset,
is available when the extended instruction set is
enabled (XINST Configuration bit = 1). Its operation is
discussed in greater detail in Section 5.5.1 “Indexed
Addressing with Literal Offset”.
5.4.1
INHERENT AND LITERAL
ADDRESSING
Many PIC18 control instructions do not need any argu-
ment at all; they either perform an operation that glo-
bally affects the device or they operate implicitly on one
register. This addressing mode is known as Inherent
Addressing. Examples include SLEEP, RESETand DAW.
The registers for indirect addressing are also
implemented with Indirect File Operands (INDFs) that
permit automatic manipulation of the pointer value with
auto-incrementing, auto-decrementing or offsetting
with another value. This allows for efficient code, using
loops, such as the example of clearing an entire RAM
bank in Example 5-5.
Other instructions work in a similar way but require an
additional explicit argument in the opcode. This is
known as Literal Addressing mode because they
require some literal value as an argument. Examples
include ADDLWand MOVLW, which respectively, add or
move a literal value to the W register. Other examples
include CALL and GOTO, which include a 20-bit
program memory address.
EXAMPLE 5-5:
HOW TO CLEAR RAM
(BANK 1) USING
INDIRECT ADDRESSING
LFSR
FSR0, 100h ;
NEXT
CLRF
POSTINC0
; Clear INDF
; register then
; inc pointer
; All done with
; Bank1?
; NO, clear next
; YES, continue
5.4.2
DIRECT ADDRESSING
Direct addressing specifies all or part of the source
and/or destination address of the operation within the
opcode itself. The options are specified by the
arguments accompanying the instruction.
BTFSS
BRA
FSR0H, 1
NEXT
CONTINUE
In the core PIC18 instruction set, bit-oriented and byte-
oriented instructions use some version of direct
addressing by default. All of these instructions include
some 8-bit literal address as their Least Significant
Byte. This address specifies either a register address in
one of the banks of data RAM (Section 5.3.3 “General
Purpose Register File”) or a location in the Access
Bank (Section 5.3.2 “Access Bank”) as the data
source for the instruction.
© 2007 Microchip Technology Inc.
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PIC18F2XK20/4XK20
5.4.3.1
FSR Registers and the INDF
Operand
5.4.3.2
FSR Registers and POSTINC,
POSTDEC, PREINC and PLUSW
At the core of indirect addressing are three sets of reg-
isters: FSR0, FSR1 and FSR2. Each represents a pair
of 8-bit registers, FSRnH and FSRnL. Each FSR pair
holds a 12-bit value, therefore the four upper bits of the
FSRnH register are not used. The 12-bit FSR value can
address the entire range of the data memory in a linear
fashion. The FSR register pairs, then, serve as pointers
to data memory locations.
In addition to the INDF operand, each FSR register pair
also has four additional indirect operands. Like INDF,
these are “virtual” registers which cannot be directly
read or written. Accessing these registers actually
accesses the location to which the associated FSR
register pair points, and also performs a specific action
on the FSR value. They are:
• POSTDEC: accesses the location to which the
FSR points, then automatically decrements the
FSR by 1 afterwards
Indirect addressing is accomplished with a set of
Indirect File Operands, INDF0 through INDF2. These
can be thought of as “virtual” registers: they are
mapped in the SFR space but are not physically
implemented. Reading or writing to a particular INDF
register actually accesses its corresponding FSR
register pair. A read from INDF1, for example, reads
the data at the address indicated by FSR1H:FSR1L.
Instructions that use the INDF registers as operands
actually use the contents of their corresponding FSR as
a pointer to the instruction’s target. The INDF operand
is just a convenient way of using the pointer.
• POSTINC: accesses the location to which the
FSR points, then automatically increments the
FSR by 1 afterwards
• PREINC: automatically increments the FSR by 1,
then uses the location to which the FSR points in
the operation
• PLUSW: adds the signed value of the W register
(range of -127 to 128) to that of the FSR and uses
the location to which the result points in the
operation.
Because indirect addressing uses a full 12-bit address,
data RAM banking is not necessary. Thus, the current
contents of the BSR and the Access RAM bit have no
effect on determining the target address.
In this context, accessing an INDF register uses the
value in the associated FSR register without changing
it. Similarly, accessing a PLUSW register gives the
FSR value an offset by that in the W register; however,
neither W nor the FSR is actually changed in the
operation. Accessing the other virtual registers
changes the value of the FSR register.
FIGURE 5-10:
INDIRECT ADDRESSING
000h
Using an instruction with one of the
indirect addressing registers as the
operand....
Bank 0
Bank 1
ADDWF, INDF1, 1
100h
200h
300h
Bank 2
FSR1H:FSR1L
...uses the 12-bit address stored in
the FSR pair associated with that
register....
7
0
7
0
Bank 3
through
Bank 13
x x x x 1 1 1 0
1 1 0 0 1 1 0 0
...to determine the data memory
location to be used in that operation.
E00h
In this case, the FSR1 pair contains
ECCh. This means the contents of
location ECCh will be added to that
of the W register and stored back in
ECCh.
Bank 14
Bank 15
F00h
FFFh
Data Memory
DS41303B-page 82
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PIC18F2XK20/4XK20
Operations on the FSRs with POSTDEC, POSTINC
and PREINC affect the entire register pair; that is, roll-
overs of the FSRnL register from FFh to 00h carry over
to the FSRnH register. On the other hand, results of
these operations do not change the value of any flags
in the STATUS register (e.g., Z, N, OV, etc.).
5.5.1
INDEXED ADDRESSING WITH
LITERAL OFFSET
Enabling the PIC18 extended instruction set changes
the behavior of indirect addressing using the FSR2
register pair within Access RAM. Under the proper
conditions, instructions that use the Access Bank – that
is, most bit-oriented and byte-oriented instructions –
can invoke a form of indexed addressing using an
offset specified in the instruction. This special
addressing mode is known as Indexed Addressing with
Literal Offset, or Indexed Literal Offset mode.
The PLUSW register can be used to implement a form
of indexed addressing in the data memory space. By
manipulating the value in the W register, users can
reach addresses that are fixed offsets from pointer
addresses. In some applications, this can be used to
implement some powerful program control structure,
such as software stacks, inside of data memory.
When using the extended instruction set, this
addressing mode requires the following:
5.4.3.3
Operations by FSRs on FSRs
• The use of the Access Bank is forced (‘a’ = 0) and
• The file address argument is less than or equal to
5Fh.
Indirect addressing operations that target other FSRs
or virtual registers represent special cases. For
example, using an FSR to point to one of the virtual
registers will not result in successful operations. As a
specific case, assume that FSR0H:FSR0L contains
FE7h, the address of INDF1. Attempts to read the
value of the INDF1 using INDF0 as an operand will
return 00h. Attempts to write to INDF1 using INDF0 as
the operand will result in a NOP.
Under these conditions, the file address of the
instruction is not interpreted as the lower byte of an
address (used with the BSR in direct addressing), or as
an 8-bit address in the Access Bank. Instead, the value
is interpreted as an offset value to an Address Pointer,
specified by FSR2. The offset and the contents of
FSR2 are added to obtain the target address of the
operation.
On the other hand, using the virtual registers to write to
an FSR pair may not occur as planned. In these cases,
the value will be written to the FSR pair but without any
incrementing or decrementing. Thus, writing to either
the INDF2 or POSTDEC2 register will write the same
value to the FSR2H:FSR2L.
5.5.2
INSTRUCTIONS AFFECTED BY
INDEXED LITERAL OFFSET MODE
Any of the core PIC18 instructions that can use direct
addressing are potentially affected by the Indexed
Literal Offset Addressing mode. This includes all
byte-oriented and bit-oriented instructions, or almost
one-half of the standard PIC18 instruction set.
Instructions that only use Inherent or Literal Addressing
modes are unaffected.
Since the FSRs are physical registers mapped in the
SFR space, they can be manipulated through all direct
operations. Users should proceed cautiously when
working on these registers, particularly if their code
uses indirect addressing.
Additionally, byte-oriented and bit-oriented instructions
are not affected if they do not use the Access Bank
(Access RAM bit is ‘1’), or include a file address of 60h
or above. Instructions meeting these criteria will
continue to execute as before. A comparison of the
different possible addressing modes when the
extended instruction set is enabled is shown in
Figure 5-11.
Similarly, operations by indirect addressing are generally
permitted on all other SFRs. Users should exercise the
appropriate caution that they do not inadvertently change
settings that might affect the operation of the device.
5.5
Data Memory and the Extended
Instruction Set
Enabling the PIC18 extended instruction set (XINST
Configuration bit = 1) significantly changes certain
aspects of data memory and its addressing. Specifi-
cally, the use of the Access Bank for many of the core
PIC18 instructions is different; this is due to the intro-
duction of a new addressing mode for the data memory
space.
Those who desire to use byte-oriented or bit-oriented
instructions in the Indexed Literal Offset mode should
note the changes to assembler syntax for this mode.
This is described in more detail in Section 24.2.1
“Extended Instruction Syntax”.
What does not change is just as important. The size of
the data memory space is unchanged, as well as its
linear addressing. The SFR map remains the same.
Core PIC18 instructions can still operate in both Direct
and Indirect Addressing mode; inherent and literal
instructions do not change at all. Indirect addressing
with FSR0 and FSR1 also remain unchanged.
© 2007 Microchip Technology Inc.
Advance Information
DS41303B-page 83
PIC18F2XK20/4XK20
FIGURE 5-11:
COMPARING ADDRESSING OPTIONS FOR BIT-ORIENTED AND
BYTE-ORIENTED INSTRUCTIONS (EXTENDED INSTRUCTION SET ENABLED)
EXAMPLE INSTRUCTION: ADDWF, f, d, a (Opcode: 0010 01da ffff ffff)
000h
When ‘a’ = 0 and f ≥ 60h:
The instruction executes in
060h
Bank 0
Direct Forced mode. ‘f’ is inter-
preted as a location in the
Access RAM between 060h
and 0FFh. This is the same as
locations F60h to FFFh
(Bank 15) of data memory.
100h
00h
60h
Bank 1
through
Bank 14
Valid range
for ‘f’
Locations below 60h are not
available in this addressing
mode.
FFh
Access RAM
F00h
Bank 15
SFRs
F60h
FFFh
Data Memory
When ‘a’ = 0 and f ≤ 5Fh:
000h
060h
100h
The instruction executes in
Indexed Literal Offset mode. ‘f’
is interpreted as an offset to the
address value in FSR2. The
two are added together to
obtain the address of the target
register for the instruction. The
address can be anywhere in
the data memory space.
Bank 0
001001da ffffffff
Bank 1
through
Bank 14
FSR2H
FSR2L
F00h
F60h
Note that in this mode, the
correct syntax is now:
Bank 15
SFRs
ADDWF [k], d
where ‘k’ is the same as ‘f’.
FFFh
Data Memory
BSR
000h
060h
100h
00000000
When ‘a’ = 1 (all values of f):
The instruction executes in
Direct mode (also known as
Direct Long mode). ‘f’ is inter-
preted as a location in one of
the 16 banks of the data
memory space. The bank is
designated by the Bank Select
Register (BSR). The address
can be in any implemented
bank in the data memory
space.
Bank 0
001001da ffffffff
Bank 1
through
Bank 14
F00h
F60h
Bank 15
SFRs
FFFh
Data Memory
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PIC18F2XK20/4XK20
Remapping of the Access Bank applies only to opera-
tions using the Indexed Literal Offset mode. Operations
that use the BSR (Access RAM bit is ‘1’) will continue
to use direct addressing as before.
5.5.3
MAPPING THE ACCESS BANK IN
INDEXED LITERAL OFFSET MODE
The use of Indexed Literal Offset Addressing mode
effectively changes how the first 96 locations of Access
RAM (00h to 5Fh) are mapped. Rather than containing
just the contents of the bottom section of Bank 0, this
mode maps the contents from a user defined “window”
that can be located anywhere in the data memory
space. The value of FSR2 establishes the lower bound-
ary of the addresses mapped into the window, while the
upper boundary is defined by FSR2 plus 95 (5Fh).
Addresses in the Access RAM above 5Fh are mapped
as previously described (see Section 5.3.2 “Access
Bank”). An example of Access Bank remapping in this
addressing mode is shown in Figure 5-12.
5.6
PIC18 Instruction Execution and
the Extended Instruction Set
Enabling the extended instruction set adds eight
additional commands to the existing PIC18 instruction
set. These instructions are executed as described in
Section 24.2 “Extended Instruction Set”.
FIGURE 5-12:
REMAPPING THE ACCESS BANK WITH INDEXED LITERAL OFFSET
ADDRESSING
Example Situation:
000h
ADDWF f, d, a
FSR2H:FSR2L = 120h
Bank 0
Locations in the region
from the FSR2 pointer
(120h) to the pointer plus
05Fh (17Fh) are mapped
to the bottom of the
Access RAM (000h-05Fh).
100h
120h
17Fh
Bank 1
Window
00h
Bank 1
Bank 1 “Window”
200h
5Fh
60h
Special File Registers at
F60h through FFFh are
mapped to 60h through
FFh, as usual.
Bank 2
through
Bank 14
SFRs
Bank 0 addresses below
5Fh can still be addressed
by using the BSR.
FFh
Access Bank
F00h
Bank 15
SFRs
F60h
FFFh
Data Memory
© 2007 Microchip Technology Inc.
Advance Information
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PIC18F2XK20/4XK20
NOTES:
DS41303B-page 86
Advance Information
© 2007 Microchip Technology Inc.
PIC18F2XK20/4XK20
A value written to program memory does not need to be
a valid instruction. Executing a program memory
location that forms an invalid instruction results in a
NOP.
6.0
FLASH PROGRAM MEMORY
The Flash program memory is readable, writable and
erasable during normal operation over the entire VDD
range.
A read from program memory is executed one byte at
a time. A write to program memory is executed on
blocks of 64, 32 or 8 bytes at a time depending on the
specific device (See Table 6-1). Program memory is
erased in blocks of 64 bytes at a time. The difference
between the write and erase block sizes requires from
1 to 8 block writes to restore the contents of a single
block erase. A bulk erase operation can not be issued
from user code.
6.1
Table Reads and Table Writes
In order to read and write program memory, there are
two operations that allow the processor to move bytes
between the program memory space and the data RAM:
• Table Read (TBLRD)
• Table Write (TBLWT)
The program memory space is 16 bits wide, while the
data RAM space is 8 bits wide. Table reads and table
writes move data between these two memory spaces
through an 8-bit register (TABLAT).
TABLE 6-1:
Device
WRITE/ERASE BLOCK SIZES
Write Block Erase Block
The table read operation retrieves one byte of data
directly from program memory and places it into the
TABLAT register. Figure 6-1 shows the operation of a
table read.
Size (bytes)
Size (bytes)
PIC18F43K20,
PIC18F23K20
8
64
The table write operation stores one byte of data from the
TABLAT register into a write block holding register. The
procedure to write the contents of the holding registers
into program memory is detailed in Section 6.5 “Writing
to Flash Program Memory”. Figure 6-2 shows the
operation of a table write with program memory and data
RAM.
PIC18F24K20,
PIC18F25K20,
PIC18F44K20,
PIC18F45K20
32
64
PIC18F26K20,
PIC18F46K20
64
64
Writing or erasing program memory will cease
instruction fetches until the operation is complete. The
program memory cannot be accessed during the write
or erase, therefore, code cannot execute. An internal
programming timer terminates program memory writes
and erases.
Table operations work with byte entities. Tables contain-
ing data, rather than program instructions, are not
required to be word aligned. Therefore, a table can start
and end at any byte address. If a table write is being
used to write executable code into program memory,
FIGURE 6-1:
TABLE READ OPERATION
Instruction: TBLRD*
Program Memory
(1)
Table Pointer
Table Latch (8-bit)
TABLAT
TBLPTRU TBLPTRH TBLPTRL
Program Memory
(TBLPTR)
Note 1: Table Pointer register points to a byte in program memory.
© 2007 Microchip Technology Inc.
Advance Information
DS41303B-page 87
PIC18F2XK20/4XK20
FIGURE 6-2:
TABLE WRITE OPERATION
Instruction: TBLWT*
Program Memory
Holding Registers
(1)
Table Pointer
Table Latch (8-bit)
TABLAT
TBLPTRU TBLPTRH TBLPTRL
Program Memory
(TBLPTR<MSBs>)
Note 1: During table writes the Table Pointer does not point directly to Program Memory. The LSBs of TBLPRTL
actually point to an address within the write block holding registers. The MSBs of the Table Pointer deter-
mine where the write block will eventually be written. The process for writing the holding registers to the
program memory array is discussed in Section 6.5 “Writing to Flash Program Memory”.
The FREE bit allows the program memory erase oper-
ation. When FREE is set, an erase operation is initiated
on the next WR command. When FREE is clear, only
writes are enabled.
6.2
Control Registers
Several control registers are used in conjunction with
the TBLRDand TBLWTinstructions. These include the:
• EECON1 register
• EECON2 register
• TABLAT register
• TBLPTR registers
The WREN bit, when set, will allow a write operation.
The WREN bit is clear on power-up.
The WRERR bit is set by hardware when the WR bit is
set and cleared when the internal programming timer
expires and the write operation is complete.
6.2.1
EECON1 AND EECON2 REGISTERS
Note:
During normal operation, the WRERR is
read as ‘1’. This can indicate that a write
operation was prematurely terminated by
The EECON1 register (Register 6-1) is the control
register for memory accesses. The EECON2 register is
not a physical register; it is used exclusively in the
memory write and erase sequences. Reading
EECON2 will read all ‘0’s.
a
Reset, or
a write operation was
attempted improperly.
The WR control bit initiates write operations. The WR
bit cannot be cleared, only set, by firmware. Then WR
bit is cleared by hardware at the completion of the write
operation.
The EEPGD control bit determines if the access will be
a program or data EEPROM memory access. When
EEPGD is clear, any subsequent operations will
operate on the data EEPROM memory. When EEPGD
is set, any subsequent operations will operate on the
program memory.
Note:
The EEIF interrupt flag bit of the PIR2
register is set when the write is complete.
The EEIF flag stays set until cleared by
firmware.
The CFGS control bit determines if the access will be
to the Configuration/Calibration registers or to program
memory/data EEPROM memory. When CFGS is set,
subsequent operations will operate on Configuration
registers regardless of EEPGD (see Section 23.0
“Special Features of the CPU”). When CFGS is clear,
memory selection access is determined by EEPGD.
DS41303B-page 88
Advance Information
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PIC18F2XK20/4XK20
REGISTER 6-1:
EECON1: DATA EEPROM CONTROL 1 REGISTER
R/W-x
EEPGD
bit 7
R/W-x
CFGS
U-0
—
R/W-0
FREE
R/W-x
R/W-0
WREN
R/S-0
WR
R/S-0
RD
WRERR
bit 0
Legend:
R = Readable bit
W = Writable bit
S = Bit can be set by software, but not cleared
-n = Value at POR ‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7
bit 6
EEPGD: Flash Program or Data EEPROM Memory Select bit
1= Access Flash program memory
0= Access data EEPROM memory
CFGS: Flash Program/Data EEPROM or Configuration Select bit
1= Access Configuration registers
0= Access Flash program or data EEPROM memory
bit 5
bit 4
Unimplemented: Read as ‘0’
FREE: Flash Row (Block) Erase Enable bit
1= Erase the program memory block addressed by TBLPTR on the next WR command
(cleared by completion of erase operation)
0= Perform write-only
bit 3
WRERR: Flash Program/Data EEPROM Error Flag bit(1)
1= A write operation is prematurely terminated (any Reset during self-timed programming in normal
operation, or an improper write attempt)
0= The write operation completed
bit 2
bit 1
WREN: Flash Program/Data EEPROM Write Enable bit
1= Allows write cycles to Flash program/data EEPROM
0= Inhibits write cycles to Flash program/data EEPROM
WR: Write Control bit
1= Initiates a data EEPROM erase/write cycle or a program memory erase cycle or write cycle.
(The operation is self-timed and the bit is cleared by hardware once write is complete.
The WR bit can only be set (not cleared) by software.)
0= Write cycle to the EEPROM is complete
bit 0
RD: Read Control bit
1= Initiates an EEPROM read (Read takes one cycle. RD is cleared by hardware. The RD bit can only
be set (not cleared) by software. RD bit cannot be set when EEPGD = 1or CFGS = 1.)
0= Does not initiate an EEPROM read
Note 1: When a WRERR occurs, the EEPGD and CFGS bits are not cleared. This allows tracing of the
error condition.
© 2007 Microchip Technology Inc.
Advance Information
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PIC18F2XK20/4XK20
When a TBLRDis executed, all 22 bits of the TBLPTR
determine which byte is read from program memory
directly into the TABLAT register.
6.2.2
TABLAT – TABLE LATCH REGISTER
The Table Latch (TABLAT) is an 8-bit register mapped
into the SFR space. The Table Latch register is used to
hold 8-bit data during data transfers between program
memory and data RAM.
When a TBLWTis executed the byte in the TABLAT reg-
ister is written, not to Flash memory but, to a holding
register in preparation for a program memory write. The
holding registers constitute a write block which varies
depending on the device (See Table 6-1).The 3, 4, or 5
LSbs of the TBLPTRL register determine which specific
address within the holding register block is written to.
The MSBs of the Table Pointer have no effect during
TBLWToperations.
6.2.3
TBLPTR – TABLE POINTER
REGISTER
The Table Pointer (TBLPTR) register addresses a byte
within the program memory. The TBLPTR is comprised
of three SFR registers: Table Pointer Upper Byte, Table
Pointer High Byte and Table Pointer Low Byte
(TBLPTRU:TBLPTRH:TBLPTRL). These three regis-
ters join to form a 22-bit wide pointer. The low-order
21 bits allow the device to address up to 2 Mbytes of
program memory space. The 22nd bit allows access to
the device ID, the user ID and the Configuration bits.
When a program memory write is executed the entire
holding register block is written to the Flash memory at
the address determined by the MSbs of the TBLPTR.
The 3, 4, or 5 LSBs are ignored during Flash memory
writes. For more detail, see Section 6.5 “Writing to
Flash Program Memory”.
The Table Pointer register, TBLPTR, is used by the
TBLRDand TBLWTinstructions. These instructions can
update the TBLPTR in one of four ways based on the
table operation. These operations are shown in
Table 6-2. These operations on the TBLPTR affect only
the low-order 21 bits.
When an erase of program memory is executed, the
16 MSbs of the Table Pointer register (TBLPTR<21:6>)
point to the 64-byte block that will be erased. The Least
Significant bits (TBLPTR<5:0>) are ignored.
Figure 6-3 describes the relevant boundaries of
TBLPTR based on Flash program memory operations.
6.2.4
TABLE POINTER BOUNDARIES
TBLPTR is used in reads, writes and erases of the
Flash program memory.
TABLE 6-2:
Example
TABLE POINTER OPERATIONS WITH TBLRD AND TBLWT INSTRUCTIONS
Operation on Table Pointer
TBLRD*
TBLWT*
TBLPTR is not modified
TBLRD*+
TBLWT*+
TBLPTR is incremented after the read/write
TBLPTR is decremented after the read/write
TBLPTR is incremented before the read/write
TBLRD*-
TBLWT*-
TBLRD+*
TBLWT+*
FIGURE 6-3:
TABLE POINTER BOUNDARIES BASED ON OPERATION
21
16 15
TBLPTRH
8
7
TBLPTRL
0
TBLPTRU
TABLE ERASE/WRITE
TBLPTR<21:n+1>
TABLE WRITE
TBLPTR<n:0>
(1)
(1)
TABLE READ – TBLPTR<21:0>
Note 1: n = 3, 4, 5, or 6 for block sizes of 8, 16, 32 or 64 bytes, respectively.
DS41303B-page 90
Advance Information
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PIC18F2XK20/4XK20
The internal program memory is typically organized by
words. The Least Significant bit of the address selects
between the high and low bytes of the word. Figure 6-4
shows the interface between the internal program
memory and the TABLAT.
6.3
Reading the Flash Program
Memory
The TBLRD instruction retrieves data from program
memory and places it into data RAM. Table reads from
program memory are performed one byte at a time.
TBLPTR points to a byte address in program space.
Executing TBLRD places the byte pointed to into
TABLAT. In addition, TBLPTR can be modified
automatically for the next table read operation.
FIGURE 6-4:
READS FROM FLASH PROGRAM MEMORY
Program Memory
(Even Byte Address)
(Odd Byte Address)
TBLPTR = xxxxx1
TBLPTR = xxxxx0
Instruction Register
(IR)
TABLAT
Read Register
FETCH
TBLRD
EXAMPLE 6-1:
READING A FLASH PROGRAM MEMORY WORD
MOVLW
MOVWF
MOVLW
MOVWF
MOVLW
MOVWF
CODE_ADDR_UPPER
TBLPTRU
CODE_ADDR_HIGH
TBLPTRH
CODE_ADDR_LOW
TBLPTRL
; Load TBLPTR with the base
; address of the word
READ_WORD
TBLRD*+
MOVF
MOVWF
TBLRD*+
MOVFW
MOVF
; read into TABLAT and increment
; get data
TABLAT, W
WORD_EVEN
; read into TABLAT and increment
; get data
TABLAT, W
WORD_ODD
© 2007 Microchip Technology Inc.
Advance Information
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PIC18F2XK20/4XK20
6.4.1
FLASH PROGRAM MEMORY
ERASE SEQUENCE
6.4
Erasing Flash Program Memory
The minimum erase block is 32 words or 64 bytes. Only
through the use of an external programmer, or through
ICSP™ control, can larger blocks of program memory
be bulk erased. Word erase in the Flash array is not
supported.
The sequence of events for erasing a block of internal
program memory is:
1. Load Table Pointer register with address of
block being erased.
When initiating an erase sequence from the Microcon-
troller itself, a block of 64 bytes of program memory is
erased. The Most Significant 16 bits of the
TBLPTR<21:6> point to the block being erased. The
TBLPTR<5:0> bits are ignored.
2. Set the EECON1 register for the erase operation:
• set EEPGD bit to point to program memory;
• clear the CFGS bit to access program memory;
• set WREN bit to enable writes;
• set FREE bit to enable the erase.
3. Disable interrupts.
The EECON1 register commands the erase operation.
The EEPGD bit must be set to point to the Flash pro-
gram memory. The WREN bit must be set to enable
write operations. The FREE bit is set to select an erase
operation.
4. Write 55h to EECON2.
5. Write 0AAh to EECON2.
6. Set the WR bit. This will begin the block erase
cycle.
The write initiate sequence for EECON2, shown as
steps 4 through 6 in Section 6.4.1 “Flash Program
Memory Erase Sequence”, is used to guard against
accidental writes. This is sometimes referred to as a
long write.
7. The CPU will stall for duration of the erase
(about 2 ms using internal timer).
8. Re-enable interrupts.
A long write is necessary for erasing the internal Flash.
Instruction execution is halted during the long write
cycle. The long write is terminated by the internal pro-
gramming timer.
EXAMPLE 6-2:
ERASING A FLASH PROGRAM MEMORY BLOCK
MOVLW
MOVWF
MOVLW
MOVWF
MOVLW
MOVWF
CODE_ADDR_UPPER
TBLPTRU
CODE_ADDR_HIGH
TBLPTRH
CODE_ADDR_LOW
TBLPTRL
; load TBLPTR with the base
; address of the memory block
ERASE_BLOCK
BSF
BCF
BSF
BSF
EECON1, EEPGD
EECON1, CFGS
EECON1, WREN
EECON1, FREE
INTCON, GIE
55h
EECON2
0AAh
EECON2
EECON1, WR
INTCON, GIE
; point to Flash program memory
; access Flash program memory
; enable write to memory
; enable block Erase operation
; disable interrupts
BCF
Required
Sequence
MOVLW
MOVWF
MOVLW
MOVWF
BSF
; write 55h
; write 0AAh
; start erase (CPU stall)
; re-enable interrupts
BSF
DS41303B-page 92
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PIC18F2XK20/4XK20
The long write is necessary for programming the inter-
nal Flash. Instruction execution is halted during a long
write cycle. The long write will be terminated by the
internal programming timer.
6.5
Writing to Flash Program Memory
The programming block size is 8, 32 or 64 bytes,
depending on the device (See Table 6-1). Word or byte
programming is not supported.
The EEPROM on-chip timer controls the write time.
The write/erase voltages are generated by an on-chip
charge pump, rated to operate over the voltage range
of the device.
Table writes are used internally to load the holding
registers needed to program the Flash memory. There
are only as many holding registers as there are bytes
in a write block (See Table 6-1).
Note:
The default value of the holding registers on
device Resets and after write operations is
FFh. A write of FFh to a holding register
does not modify that byte. This means that
individual bytes of program memory may be
modified, provided that the change does not
attempt to change any bit from a ‘0’ to a ‘1’.
When modifying individual bytes, it is not
necessary to load all holding registers
before executing a long write operation.
Since the Table Latch (TABLAT) is only a single byte,
the TBLWTinstruction may need to be executed 8, 32,
or 64 times, depending on the device, for each pro-
gramming operation. All of the table write operations
will essentially be short writes because only the holding
registers are written. After all the holding registers have
been written, the programming operation of that block
of memory is started by configuring the EECON1 regis-
ter for a program memory write and performing the long
write sequence.
FIGURE 6-5:
TABLE WRITES TO FLASH PROGRAM MEMORY
TABLAT
Write Register
8
8
8
8
(1)
TBLPTR = xxxx00
TBLPTR = xxxx01
TBLPTR = xxxx02
TBLPTR = xxxxYY
Holding Register
Holding Register
Holding Register
Holding Register
Program Memory
Note 1: YY = x7, xF, or 1F for 8, 16 or 32 byte write blocks, respectively.
8. Disable interrupts.
6.5.1
FLASH PROGRAM MEMORY WRITE
SEQUENCE
9. Write 55h to EECON2.
10. Write 0AAh to EECON2.
The sequence of events for programming an internal
program memory location should be:
11. Set the WR bit. This will begin the write cycle.
12. The CPU will stall for duration of the write (about
2 ms using internal timer).
1. Read 64 bytes into RAM.
2. Update data values in RAM as necessary.
13. Re-enable interrupts.
3. Load Table Pointer register with address being
erased.
14. Repeat steps 6 to 13 for each block until all 64
bytes are written.
4. Execute the block erase procedure.
15. Verify the memory (table read).
5. Load Table Pointer register with address of first
byte being written.
This procedure will require about 6 ms to update each
write block of memory. An example of the required code
is given in Example 6-3.
6. Write the 8, 32 or 64 byte block into the holding
registers with auto-increment.
7. Set the EECON1 register for the write operation:
• set EEPGD bit to point to program memory;
• clear the CFGS bit to access program memory;
• set WREN to enable byte writes.
Note:
Before setting the WR bit, the Table
Pointer address needs to be within the
intended address range of the bytes in the
holding registers.
© 2007 Microchip Technology Inc.
Advance Information
DS41303B-page 93
PIC18F2XK20/4XK20
EXAMPLE 6-3:
WRITING TO FLASH PROGRAM MEMORY
MOVLW
MOVWF
MOVLW
MOVWF
MOVLW
MOVWF
MOVLW
MOVWF
MOVLW
MOVWF
MOVLW
MOVWF
D'64’
COUNTER
BUFFER_ADDR_HIGH
FSR0H
BUFFER_ADDR_LOW
FSR0L
CODE_ADDR_UPPER
TBLPTRU
CODE_ADDR_HIGH
TBLPTRH
CODE_ADDR_LOW
TBLPTRL
; number of bytes in erase block
; point to buffer
; Load TBLPTR with the base
; address of the memory block
READ_BLOCK
TBLRD*+
MOVF
MOVWF
DECFSZ
BRA
; read into TABLAT, and inc
; get data
; store data
; done?
TABLAT, W
POSTINC0
COUNTER
READ_BLOCK
; repeat
MODIFY_WORD
MOVLW
MOVWF
MOVLW
MOVWF
MOVLW
MOVWF
MOVLW
MOVWF
BUFFER_ADDR_HIGH
FSR0H
BUFFER_ADDR_LOW
FSR0L
NEW_DATA_LOW
POSTINC0
NEW_DATA_HIGH
INDF0
; point to buffer
; update buffer word
ERASE_BLOCK
MOVLW
MOVWF
MOVLW
MOVWF
MOVLW
MOVWF
BSF
BCF
BSF
BSF
BCF
MOVLW
MOVWF
MOVLW
MOVWF
BSF
CODE_ADDR_UPPER
TBLPTRU
CODE_ADDR_HIGH
TBLPTRH
CODE_ADDR_LOW
TBLPTRL
EECON1, EEPGD
EECON1, CFGS
EECON1, WREN
EECON1, FREE
INTCON, GIE
55h
EECON2
0AAh
EECON2
EECON1, WR
INTCON, GIE
; load TBLPTR with the base
; address of the memory block
; point to Flash program memory
; access Flash program memory
; enable write to memory
; enable Erase operation
; disable interrupts
Required
Sequence
; write 55h
; write 0AAh
; start erase (CPU stall)
; re-enable interrupts
; dummy read decrement
; point to buffer
BSF
TBLRD*-
MOVLW
MOVWF
MOVLW
MOVWF
BUFFER_ADDR_HIGH
FSR0H
BUFFER_ADDR_LOW
FSR0L
WRITE_BUFFER_BACK
MOVLW
MOVWF
MOVLW
MOVWF
BlockSize
COUNTER
D’64’/BlockSize
COUNTER2
; number of bytes in holding register
; number of write blocks in 64 bytes
WRITE_BYTE_TO_HREGS
MOVF
MOVWF
TBLWT+*
POSTINC0, W
TABLAT
; get low byte of buffer data
; present data to table latch
; write data, perform a short write
; to internal TBLWT holding register.
DS41303B-page 94
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PIC18F2XK20/4XK20
EXAMPLE 6-3:
WRITING TO FLASH PROGRAM MEMORY (CONTINUED)
DECFSZ COUNTER
; loop until holding registers are full
BRA
WRITE_WORD_TO_HREGS
PROGRAM_MEMORY
BSF
BCF
BSF
BCF
MOVLW
MOVWF
MOVLW
MOVWF
BSF
DCFSZ
BRA
BSF
EECON1, EEPGD
EECON1, CFGS
EECON1, WREN
INTCON, GIE
55h
EECON2
0AAh
EECON2
EECON1, WR
COUNTER2
; point to Flash program memory
; access Flash program memory
; enable write to memory
; disable interrupts
Required
Sequence
; write 55h
; write 0AAh
; start program (CPU stall)
; repeat for remaining write blocks
;
; re-enable interrupts
; disable write to memory
WRITE_BYTE_TO_HREGS
INTCON, GIE
EECON1, WREN
BCF
6.5.2
WRITE VERIFY
6.5.4
PROTECTION AGAINST
SPURIOUS WRITES
Depending on the application, good programming
practice may dictate that the value written to the
memory should be verified against the original value.
This should be used in applications where excessive
writes can stress bits near the specification limit.
To protect against spurious writes to Flash program
memory, the write initiate sequence must also be
followed. See Section 23.0 “Special Features of the
CPU” for more detail.
6.5.3
UNEXPECTED TERMINATION OF
WRITE OPERATION
6.6
Flash Program Operation During
Code Protection
If a write is terminated by an unplanned event, such as
loss of power or an unexpected Reset, the memory
location just programmed should be verified and
reprogrammed if needed. If the write operation is
interrupted by a MCLR Reset or a WDT Time-out Reset
during normal operation, the WRERR bit will be set
which the user can check to decide whether a rewrite
of the location(s) is needed.
See Section 23.3 “Program Verification and Code
Protection” for details on code protection of Flash
program memory.
TABLE 6-3:
Name
REGISTERS ASSOCIATED WITH PROGRAM FLASH MEMORY
Reset
Valueson
page
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
TBLPTRU
—
—
bit 21 Program Memory Table Pointer Upper Byte (TBLPTR<20:16>)
57
57
57
57
57
59
59
60
60
60
TBPLTRH Program Memory Table Pointer High Byte (TBLPTR<15:8>)
TBLPTRL Program Memory Table Pointer Low Byte (TBLPTR<7:0>)
TABLAT
INTCON
Program Memory Table Latch
GIE/GIEH PEIE/GIEL TMR0IE INT0IE
RBIE
TMR0IF
INT0IF
RBIF
EECON2 EEPROM Control Register 2 (not a physical register)
EECON1
IPR2
EEPGD
OSCFIP
OSCFIF
OSCFIE
CFGS
C1IP
C1IF
C1IE
—
FREE
EEIP
EEIF
EEIE
WRERR
BCLIP
BCLIF
BCLIE
WREN
HLVDIP
HLVDIF
HLVDIE
WR
RD
C2IP
C2IF
C2IE
TMR3IP
TMR3IF
TMR3IE
CCP2IP
CCP2IF
CCP2IE
PIR2
PIE2
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used during Flash/EEPROM access.
© 2007 Microchip Technology Inc.
Advance Information
DS41303B-page 95
PIC18F2XK20/4XK20
NOTES:
DS41303B-page 96
Advance Information
© 2007 Microchip Technology Inc.
PIC18F2XK20/4XK20
The EECON1 register (Register 7-1) is the control reg-
ister for data and program memory access. Control bit
EEPGD determines if the access will be to program or
data EEPROM memory. When the EEPGD bit is clear,
operations will access the data EEPROM memory.
When the EEPGD bit is set, program memory is
accessed.
7.0
DATA EEPROM MEMORY
The data EEPROM is a nonvolatile memory array, sep-
arate from the data RAM and program memory, which
is used for long-term storage of program data. It is not
directly mapped in either the register file or program
memory space but is indirectly addressed through the
Special Function Registers (SFRs). The EEPROM is
readable and writable during normal operation over the
entire VDD range.
Control bit, CFGS, determines if the access will be to
the Configuration registers or to program memory/data
EEPROM memory. When the CFGS bit is set,
subsequent operations access Configuration registers.
When the CFGS bit is clear, the EEPGD bit selects
either program Flash or data EEPROM memory.
Four SFRs are used to read and write to the data
EEPROM as well as the program memory. They are:
• EECON1
• EECON2
• EEDATA
• EEADR
The WREN bit, when set, will allow a write operation.
On power-up, the WREN bit is clear.
The WRERR bit is set by hardware when the WR bit is
set and cleared when the internal programming timer
expires and the write operation is complete.
• EEADRH
The data EEPROM allows byte read and write. When
interfacing to the data memory block, EEDATA holds
the 8-bit data for read/write and the EEADR:EEADRH
register pair hold the address of the EEPROM location
being accessed.
Note:
During normal operation, the WRERR
may read as ‘1’. This can indicate that a
write operation was prematurely termi-
nated by a Reset, or a write operation was
attempted improperly.
The EEPROM data memory is rated for high erase/write
cycle endurance. A byte write automatically erases the
location and writes the new data (erase-before-write).
The write time is controlled by an on-chip timer; it will
vary with voltage and temperature as well as from chip-
to-chip. Please refer to parameter D122 (Table 26.10 in
Section 26.0 “Electrical Characteristics”) for exact
limits.
The WR control bit initiates write operations. The bit
can be set but not cleared by software. It is cleared only
by hardware at the completion of the write operation.
Note:
The EEIF interrupt flag bit of the PIR2
register is set when the write is complete.
It must be cleared by software.
Control bits, RD and WR, start read and erase/write
operations, respectively. These bits are set by firmware
and cleared by hardware at the completion of the
operation.
7.1
EEADR and EEADRH Registers
The EEADR register is used to address the data
EEPROM for read and write operations. The 8-bit
range of the register can address a memory range of
256 bytes (00h to FFh). The EEADRH register expands
the range to 1024 bytes by adding an additional two
address bits.
The RD bit cannot be set when accessing program
memory (EEPGD = 1). Program memory is read using
table read instructions. See Section 6.1 “Table Reads
and Table Writes” regarding table reads.
The EECON2 register is not a physical register. It is
used exclusively in the memory write and erase
sequences. Reading EECON2 will read all ‘0’s.
7.2
EECON1 and EECON2 Registers
Access to the data EEPROM is controlled by two
registers: EECON1 and EECON2. These are the same
registers which control access to the program memory
and are used in a similar manner for the data
EEPROM.
© 2007 Microchip Technology Inc.
Advance Information
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PIC18F2XK20/4XK20
REGISTER 7-1:
EECON1: DATA EEPROM CONTROL 1 REGISTER
R/W-x
EEPGD
bit 7
R/W-x
CFGS
U-0
—
R/W-0
FREE
R/W-x
R/W-0
WREN
R/S-0
WR
R/S-0
RD
WRERR
bit 0
Legend:
R = Readable bit
W = Writable bit
S = Bit can be set by software, but not cleared
-n = Value at POR ‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7
bit 6
EEPGD: Flash Program or Data EEPROM Memory Select bit
1= Access Flash program memory
0= Access data EEPROM memory
CFGS: Flash Program/Data EEPROM or Configuration Select bit
1= Access Configuration registers
0= Access Flash program or data EEPROM memory
bit 5
bit 4
Unimplemented: Read as ‘0’
FREE: Flash Row (Block) Erase Enable bit
1= Erase the program memory block addressed by TBLPTR on the next WR command
(cleared by completion of erase operation)
0= Perform write-only
bit 3
WRERR: Flash Program/Data EEPROM Error Flag bit(1)
1= A write operation is prematurely terminated (any Reset during self-timed programming in normal
operation, or an improper write attempt)
0= The write operation completed
bit 2
bit 1
WREN: Flash Program/Data EEPROM Write Enable bit
1= Allows write cycles to Flash program/data EEPROM
0= Inhibits write cycles to Flash program/data EEPROM
WR: Write Control bit
1= Initiates a data EEPROM erase/write cycle or a program memory erase cycle or write cycle.
(The operation is self-timed and the bit is cleared by hardware once write is complete.
The WR bit can only be set (not cleared) by software.)
0= Write cycle to the EEPROM is complete
bit 0
RD: Read Control bit
1= Initiates an EEPROM read (Read takes one cycle. RD is cleared by hardware. The RD bit can only
be set (not cleared) by software. RD bit cannot be set when EEPGD = 1or CFGS = 1.)
0= Does not initiate an EEPROM read
Note 1: When a WRERR occurs, the EEPGD and CFGS bits are not cleared. This allows tracing of the
error condition.
DS41303B-page 98
Advance Information
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PIC18F2XK20/4XK20
Additionally, the WREN bit in EECON1 must be set to
enable writes. This mechanism prevents accidental
writes to data EEPROM due to unexpected code
execution (i.e., runaway programs). The WREN bit
should be kept clear at all times, except when updating
the EEPROM. The WREN bit is not cleared by
hardware.
7.3
Reading the Data EEPROM
Memory
To read a data memory location, the user must write the
address to the EEADR register, clear the EEPGD con-
trol bit of the EECON1 register and then set control bit,
RD. The data is available on the very next instruction
cycle; therefore, the EEDATA register can be read by
the next instruction. EEDATA will hold this value until
another read operation, or until it is written to by the
user (during a write operation).
After a write sequence has been initiated, EECON1,
EEADR and EEDATA cannot be modified. The WR bit
will be inhibited from being set unless the WREN bit is
set. Both WR and WREN cannot be set with the same
instruction.
The basic process is shown in Example 7-1.
At the completion of the write cycle, the WR bit is
cleared by hardware and the EEPROM Interrupt Flag
bit, EEIF, is set. The user may either enable this
interrupt or poll this bit. EEIF must be cleared by
software.
7.4
Writing to the Data EEPROM
Memory
To write an EEPROM data location, the address must
first be written to the EEADR register and the data writ-
ten to the EEDATA register. The sequence in
Example 7-2 must be followed to initiate the write cycle.
7.5
Write Verify
Depending on the application, good programming
practice may dictate that the value written to the
memory should be verified against the original value.
This should be used in applications where excessive
writes can stress bits near the specification limit.
The write will not begin if this sequence is not exactly
followed (write 55h to EECON2, write 0AAh to
EECON2, then set WR bit) for each byte. It is strongly
recommended that interrupts be disabled during this
code segment.
EXAMPLE 7-1:
DATA EEPROM READ
MOVLW
MOVWF
BCF
DATA_EE_ADDR
EEADR
EECON1, EEPGD ; Point to DATA memory
;
; Data Memory Address to read
BCF
BSF
MOVF
EECON1, CFGS
EECON1, RD
EEDATA, W
; Access EEPROM
; EEPROM Read
; W = EEDATA
EXAMPLE 7-2:
DATA EEPROM WRITE
MOVLW
MOVWF
MOVLW
MOVWF
MOVLW
MOVWF
BCF
BCF
BSF
BCF
MOVLW
MOVWF
MOVLW
MOVWF
BSF
DATA_EE_ADDR_LOW
EEADR
DATA_EE_ADDR_HI
EEADRH
DATA_EE_DATA
EEDATA
EECON1, EEPGD
EECON1, CFGS
EECON1, WREN
INTCON, GIE
55h
EECON2
0AAh
EECON2
EECON1, WR
INTCON, GIE
;
; Data Memory Address to write
;
;
;
; Data Memory Value to write
; Point to DATA memory
; Access EEPROM
; Enable writes
; Disable Interrupts
;
; Write 55h
;
; Write 0AAh
; Set WR bit to begin write
; Enable Interrupts
Required
Sequence
BSF
; User code execution
BCF
EECON1, WREN
; Disable writes on write complete (EEIF set)
© 2007 Microchip Technology Inc.
Advance Information
DS41303B-page 99
PIC18F2XK20/4XK20
The write initiate sequence and the WREN bit together
help prevent an accidental write during brown-out,
power glitch or software malfunction.
7.6
Operation During Code-Protect
Data EEPROM memory has its own code-protect bits in
Configuration Words. External read and write
operations are disabled if code protection is enabled.
7.8
Using the Data EEPROM
The microcontroller itself can both read and write to the
internal data EEPROM, regardless of the state of the
code-protect Configuration bit. Refer to Section 23.0
“Special Features of the CPU” for additional
information.
The data EEPROM is
a high-endurance, byte
addressable array that has been optimized for the
storage of frequently changing information (e.g.,
program variables or other data that are updated often).
When variables in one section change frequently, while
variables in another section do not change, it is possible
to exceed the total number of write cycles to the
EEPROM (specification D124) without exceeding the
total number of write cycles to a single byte (specification
D120). If this is the case, then an array refresh must be
performed. For this reason, variables that change
infrequently (such as constants, IDs, calibration, etc.)
should be stored in Flash program memory.
7.7
Protection Against Spurious Write
There are conditions when the user may not want to
write to the data EEPROM memory. To protect against
spurious EEPROM writes, various mechanisms have
been implemented. On power-up, the WREN bit is
cleared. In addition, writes to the EEPROM are blocked
during the Power-up Timer period (TPWRT,
parameter 33).
EXAMPLE 7-3:
DATA EEPROM REFRESH ROUTINE
CLRF
BCF
BCF
BCF
BSF
EEADR
; Start at address 0
EECON1, CFGS
EECON1, EEPGD
INTCON, GIE
EECON1, WREN
; Set for memory
; Set for Data EEPROM
; Disable interrupts
; Enable writes
; Loop to refresh array
; Read current address
;
; Write 55h
;
; Write 0AAh
; Set WR bit to begin write
; Wait for write to complete
Loop
BSF
EECON1, RD
55h
EECON2
0AAh
EECON2
EECON1, WR
EECON1, WR
$-2
MOVLW
MOVWF
MOVLW
MOVWF
BSF
BTFSC
BRA
INCFSZ
BRA
EEADR, F
LOOP
; Increment address
; Not zero, do it again
BCF
BSF
EECON1, WREN
INTCON, GIE
; Disable writes
; Enable interrupts
TABLE 7-1:
Name
REGISTERS ASSOCIATED WITH DATA EEPROM MEMORY
Reset
Values
on page
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
INTCON
EEADR
EEADRH
EEDATA
EECON2
EECON1
IPR2
GIE/GIEH PEIE/GIEL TMR0IE
INT0IE
RBIE
TMR0IF
INT0IF
RBIF
57
59
59
59
59
59
60
60
60
EEADR7
—
EEADR6 EEADR5 EEADR4 EEADR3 EEADR2 EEADR1 EEADR0
—
—
—
—
—
EEADR9 EEADR8
EEPROM Data Register
EEPROM Control Register 2 (not a physical register)
EEPGD
OSCFIP
OSCFIF
OSCFIE
CFGS
C1IP
C1IF
C1IE
—
FREE
EEIP
EEIF
EEIE
WRERR
BCLIP
BCLIF
BCLIE
WREN
WR
RD
C2IP
C2IF
C2IE
HLVDIP TMR3IP CCP2IP
HLVDIF TMR3IF CCP2IF
HLVDIE TMR3IE CCP2IE
PIR2
PIE2
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used during Flash/EEPROM access.
DS41303B-page 100
Advance Information
© 2007 Microchip Technology Inc.
PIC18F2XK20/4XK20
EXAMPLE 8-1:
8 x 8 UNSIGNED
MULTIPLY ROUTINE
8.0
8.1
8 x 8 HARDWARE MULTIPLIER
Introduction
MOVF
MULWF
ARG1, W
ARG2
;
; ARG1 * ARG2 ->
; PRODH:PRODL
All PIC18 devices include an 8 x 8 hardware multiplier
as part of the ALU. The multiplier performs an unsigned
operation and yields a 16-bit result that is stored in the
product register pair, PRODH:PRODL. The multiplier’s
operation does not affect any flags in the STATUS
register.
EXAMPLE 8-2:
8 x 8 SIGNED MULTIPLY
ROUTINE
MOVF
MULWF
ARG1, W
ARG2
Making multiplication a hardware operation allows it to
be completed in a single instruction cycle. This has the
advantages of higher computational throughput and
reduced code size for multiplication algorithms and
allows the PIC18 devices to be used in many applica-
tions previously reserved for digital signal processors.
A comparison of various hardware and software
multiply operations, along with the savings in memory
and execution time, is shown in Table 8-1.
; ARG1 * ARG2 ->
; PRODH:PRODL
; Test Sign Bit
; PRODH = PRODH
BTFSC
SUBWF
ARG2, SB
PRODH, F
;
- ARG1
MOVF
BTFSC
SUBWF
ARG2, W
ARG1, SB
PRODH, F
; Test Sign Bit
; PRODH = PRODH
;
- ARG2
8.2
Operation
Example 8-1 shows the instruction sequence for an 8 x 8
unsigned multiplication. Only one instruction is required
when one of the arguments is already loaded in the
WREG register.
Example 8-2 shows the sequence to do an 8 x 8 signed
multiplication. To account for the sign bits of the argu-
ments, each argument’s Most Significant bit (MSb) is
tested and the appropriate subtractions are done.
TABLE 8-1:
Routine
PERFORMANCE COMPARISON FOR VARIOUS MULTIPLY OPERATIONS
Program
Memory
(Words)
Time
Cycles
(Max)
Multiply Method
@ 40 MHz @ 10 MHz @ 4 MHz
Without hardware multiply
Hardware multiply
13
1
69
1
6.9 μs
100 ns
9.1 μs
600 ns
24.2 μs
2.8 μs
25.4 μs
4.0 μs
27.6 μs
400 ns
36.4 μs
2.4 μs
69 μs
1 μs
8 x 8 unsigned
8 x 8 signed
Without hardware multiply
Hardware multiply
33
6
91
6
91 μs
6 μs
Without hardware multiply
Hardware multiply
21
28
52
35
242
28
254
40
96.8 μs
11.2 μs
102.6 μs
16.0 μs
242 μs
28 μs
254 μs
40 μs
16 x 16 unsigned
16 x 16 signed
Without hardware multiply
Hardware multiply
© 2007 Microchip Technology Inc.
Advance Information
DS41303B-page 101
PIC18F2XK20/4XK20
Example 8-3 shows the sequence to do a 16 x 16
unsigned multiplication. Equation 8-1 shows the
algorithm that is used. The 32-bit result is stored in four
registers (RES<3:0>).
EQUATION 8-2:
16 x 16 SIGNED
MULTIPLICATION
ALGORITHM
RES3:RES0 = ARG1H:ARG1L • ARG2H:ARG2L
16
= (ARG1H • ARG2H • 2 ) +
(ARG1H • ARG2L • 2 ) +
(ARG1L • ARG2H • 2 ) +
(ARG1L • ARG2L) +
(-1 • ARG2H<7> • ARG1H:ARG1L • 2 ) +
(-1 • ARG1H<7> • ARG2H:ARG2L • 2
8
EQUATION 8-1:
16 x 16 UNSIGNED
MULTIPLICATION
ALGORITHM
8
16
RES3:RES0
=
=
ARG1H:ARG1L • ARG2H:ARG2L
16
)
16
(ARG1H • ARG2H • 2 ) +
8
(ARG1H • ARG2L • 2 ) +
8
(ARG1L • ARG2H • 2 ) +
EXAMPLE 8-4:
16 x 16 SIGNED
MULTIPLY ROUTINE
(ARG1L • ARG2L)
MOVF
MULWF
ARG1L, W
ARG2L
; ARG1L * ARG2L ->
; PRODH:PRODL
;
;
EXAMPLE 8-3:
16 x 16 UNSIGNED
MULTIPLY ROUTINE
MOVFF
MOVFF
PRODH, RES1
PRODL, RES0
MOVF
MULWF
ARG1L, W
ARG2L
; ARG1L * ARG2L->
; PRODH:PRODL
;
;
;
;
MOVF
MULWF
ARG1H, W
ARG2H
MOVFF
MOVFF
PRODH, RES1
PRODL, RES0
; ARG1H * ARG2H ->
; PRODH:PRODL
;
;
;
;
MOVFF
MOVFF
PRODH, RES3
PRODL, RES2
MOVF
MULWF
ARG1H, W
ARG2H
; ARG1H * ARG2H->
; PRODH:PRODL
;
;
MOVF
MULWF
ARG1L, W
ARG2H
MOVFF
MOVFF
PRODH, RES3
PRODL, RES2
; ARG1L * ARG2H ->
; PRODH:PRODL
;
; Add cross
; products
;
;
;
MOVF
ADDWF
MOVF
ADDWFC RES2, F
CLRF WREG
ADDWFC RES3, F
PRODL, W
RES1, F
PRODH, W
MOVF
MULWF
ARG1L, W
ARG2H
; ARG1L * ARG2H->
; PRODH:PRODL
;
; Add cross
; products
;
;
;
MOVF
ADDWF
MOVF
PRODL, W
RES1, F
PRODH, W
;
ADDWFC RES2, F
CLRF WREG
ADDWFC RES3, F
MOVF
MULWF
ARG1H, W
ARG2L
;
; ARG1H * ARG2L ->
; PRODH:PRODL
;
; Add cross
; products
;
;
;
;
MOVF
ADDWF
MOVF
ADDWFC RES2, F
CLRF WREG
ADDWFC RES3, F
PRODL, W
RES1, F
PRODH, W
MOVF
MULWF
ARG1H, W
ARG2L
;
; ARG1H * ARG2L->
; PRODH:PRODL
;
; Add cross
; products
MOVF
ADDWF
MOVF
PRODL, W
RES1, F
PRODH, W
;
;
ADDWFC RES2, F
CLRF WREG
ADDWFC RES3, F
;
;
;
BTFSS
BRA
MOVF
SUBWF
MOVF
ARG2H, 7
SIGN_ARG1
ARG1L, W
RES2
; ARG2H:ARG2L neg?
; no, check ARG1
;
;
;
Example 8-4 shows the sequence to do a 16 x 16
signed multiply. Equation 8-2 shows the algorithm
used. The 32-bit result is stored in four registers
(RES<3:0>). To account for the sign bits of the argu-
ments, the MSb for each argument pair is tested and
the appropriate subtractions are done.
ARG1H, W
SUBWFB RES3
SIGN_ARG1
BTFSS
BRA
ARG1H, 7
CONT_CODE
ARG2L, W
RES2
; ARG1H:ARG1L neg?
; no, done
;
;
;
MOVF
SUBWF
MOVF
ARG2H, W
SUBWFB RES3
;
CONT_CODE
:
DS41303B-page 102
Advance Information
© 2007 Microchip Technology Inc.
PIC18F2XK20/4XK20
9.2
Interrupt Priority
9.0
INTERRUPTS
The interrupt priority feature is enabled by setting the
IPEN bit of the RCON register. When interrupt priority
is enabled the GIE and PEIE global interrupt enable
bits of Compatibility mode are replaced by the GIEH
high priority, and GIEL low priority, global interrupt
enables. When set, the GIEH bit of the INTCON regis-
ter enables all interrupts that have their associated
IPRx register or INTCONx register priority bit set (high
priority). When clear, the GIEL bit disables all interrupt
sources including those selected as low priority. When
clear, the GIEL bit of the INTCON register disables only
the interrupts that have their associated priority bit
cleared (low priority). When set, the GIEL bit enables
the low priority sources when the GIEH bit is also set.
The PIC18F2XK20/4XK20 devices have multiple
interrupt sources and an interrupt priority feature that
allows most interrupt sources to be assigned a high
priority level or a low priority level. The high priority
interrupt vector is at 0008h and the low priority interrupt
vector is at 0018h. A high priority interrupt event will
interrupt a low priority interrupt that may be in progress.
There are ten registers which are used to control
interrupt operation. These registers are:
• RCON
• INTCON
• INTCON2
• INTCON3
• PIR1, PIR2
• PIE1, PIE2
• IPR1, IPR2
When the interrupt flag, enable bit and appropriate
global interrupt enable bit are all set, the interrupt will
vector immediately to address 0008h for high priority,
or 0018h for low priority, depending on level of the
interrupting source’s priority bit. Individual interrupts
can be disabled through their corresponding interrupt
enable bits.
It is recommended that the Microchip header files sup-
plied with MPLAB® IDE be used for the symbolic bit
names in these registers. This allows the assembler/
compiler to automatically take care of the placement of
these bits within the specified register.
9.3
Interrupt Response
In general, interrupt sources have three bits to control
their operation. They are:
When an interrupt is responded to, the global interrupt
enable bit is cleared to disable further interrupts. The
GIE bit is the global interrupt enable when the IPEN bit
is cleared. When the IPEN bit is set, enabling interrupt
priority levels, the GIEH bit is the high priority global
interrupt enable and the GIEL bit is the low priority
global interrupt enable. High priority interrupt sources
can interrupt a low priority interrupt. Low priority
interrupts are not processed while high priority
interrupts are in progress.
• Flag bit to indicate that an interrupt event
occurred
• Enable bit that allows program execution to
branch to the interrupt vector address when the
flag bit is set
• Priority bit to select high priority or low priority
9.1
Mid-Range Compatibility
The return address is pushed onto the stack and the
PC is loaded with the interrupt vector address (0008h
or 0018h). Once in the Interrupt Service Routine, the
source(s) of the interrupt can be determined by polling
the interrupt flag bits in the INTCONx and PIRx
registers. The interrupt flag bits must be cleared by
software before re-enabling interrupts to avoid
repeating the same interrupt.
When the IPEN bit is cleared (default state), the interrupt
priority feature is disabled and interrupts are compatible
with PIC® microcontroller mid-range devices. In
Compatibility mode, the interrupt priority bits of the IPRx
registers have no effect. The PEIE bit of the INTCON
register is the global interrupt enable for the peripherals.
The PEIE bit disables only the peripheral interrupt
sources and enables the peripheral interrupt sources
when the GIE bit is also set. The GIE bit of the INTCON
register is the global interrupt enable which enables all
non-peripheral interrupt sources and disables all
interrupt sources, including the peripherals. All interrupts
branch to address 0008h in Compatibility mode.
The “return from interrupt” instruction, RETFIE, exits
the interrupt routine and sets the GIE bit (GIEH or GIEL
if priority levels are used), which re-enables interrupts.
For external interrupt events, such as the INT pins or
the PORTB interrupt-on-change, the interrupt latency
will be three to four instruction cycles. The exact
latency is the same for one-cycle or two-cycle
instructions. Individual interrupt flag bits are set,
regardless of the status of their corresponding enable
bits or the global interrupt enable bit.
Note:
Do not use the MOVFFinstruction to modify
any of the interrupt control registers while
any interrupt is enabled. Doing so may
cause erratic microcontroller behavior.
© 2007 Microchip Technology Inc.
Advance Information
DS41303B-page 103
PIC18F2XK20/4XK20
FIGURE 9-1:
PIC18 INTERRUPT LOGIC
Wake-up if in
Idle or Sleep modes
TMR0IF
TMR0IE
TMR0IP
RBIF
(1)
RBIE
RBIP
INT0IF
INT0IE
Interrupt to CPU
Vector to Location
0008h
INT1IF
INT1IE
INT1IP
INT2IF
INT2IE
INT2IP
SSPIF
SSPIE
SSPIP
GIEH/GIE
ADIF
ADIE
ADIP
IPEN
IPEN
GIEL/PEIE
RCIF
RCIE
RCIP
IPEN
Additional Peripheral Interrupts
High Priority Interrupt Generation
Low Priority Interrupt Generation
SSPIF
SSPIE
SSPIP
Interrupt to CPU
Vector to Location
0018h
TMR0IF
TMR0IE
TMR0IP
ADIF
ADIE
ADIP
(1)
RBIF
RBIE
RBIP
RCIF
RCIE
RCIP
GIEH/GIE
GIEL/PEIE
INT1IF
INT1IE
INT1IP
Additional Peripheral Interrupts
INT2IF
INT2IE
INT2IP
Note 1: The RBIF interrupt also requires the individual pin IOCB enables.
DS41303B-page 104
Advance Information
© 2007 Microchip Technology Inc.
PIC18F2XK20/4XK20
9.4
INTCON Registers
Note:
Interrupt flag bits are set when an interrupt
condition occurs, regardless of the state of
its corresponding enable bit or the global
enable bit. User software should ensure
the appropriate interrupt flag bits are clear
prior to enabling an interrupt. This feature
allows for software polling.
The INTCON registers are readable and writable
registers, which contain various enable, priority and
flag bits.
REGISTER 9-1:
INTCON: INTERRUPT CONTROL REGISTER
R/W-0
GIE/GIEH
bit 7
R/W-0
R/W-0
R/W-0
R/W-0
RBIE
R/W-0
R/W-0
INT0IF
R/W-x
RBIF
PEIE/GIEL
TMR0IE
INT0IE
TMR0IF
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7
GIE/GIEH: Global Interrupt Enable bit
When IPEN = 0:
1= Enables all unmasked interrupts
0= Disables all interrupts including peripherals
When IPEN = 1:
1= Enables all high priority interrupts
0= Disables all interrupts including low priority.
bit 6
PEIE/GIEL: Peripheral Interrupt Enable bit
When IPEN = 0:
1= Enables all unmasked peripheral interrupts
0= Disables all peripheral interrupts
When IPEN = 1:
1= Enables all low priority interrupts
0= Disables all low priority interrupts
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
TMR0IE: TMR0 Overflow Interrupt Enable bit
1= Enables the TMR0 overflow interrupt
0= Disables the TMR0 overflow interrupt
INT0IE: INT0 External Interrupt Enable bit
1= Enables the INT0 external interrupt
0= Disables the INT0 external interrupt
(2)
RBIE: RB Port Change Interrupt Enable bit
1= Enables the RB port change interrupt
0= Disables the RB port change interrupt
TMR0IF: TMR0 Overflow Interrupt Flag bit
1= TMR0 register has overflowed (must be cleared by software)
0= TMR0 register did not overflow
INT0IF: INT0 External Interrupt Flag bit
1= The INT0 external interrupt occurred (must be cleared by software)
0= The INT0 external interrupt did not occur
(1)
RBIF: RB Port Change Interrupt Flag bit
1= At least one of the RB<7:4> pins changed state (must be cleared by software)
0= None of the RB<7:4> pins have changed state
Note 1: A mismatch condition will continue to set the RBIF bit. Reading PORTB will end the
mismatch condition and allow the bit to be cleared.
2: RB port change interrupts also require the individual pin IOCB enables.
© 2007 Microchip Technology Inc.
Advance Information
DS41303B-page 105
PIC18F2XK20/4XK20
REGISTER 9-2:
INTCON2: INTERRUPT CONTROL 2 REGISTER
R/W-1
RBPU
R/W-1
R/W-1
R/W-1
U-0
—
R/W-1
U-0
—
R/W-1
RBIP
INTEDG0
INTEDG1
INTEDG2
TMR0IP
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
-n = Value at POR
bit 7
RBPU: PORTB Pull-up Enable bit
1= All PORTB pull-ups are disabled
0= PORTB pull-ups are enabled provided that the pin is an input and the corresponding WPUB bit is
set.
bit 6
bit 5
bit 4
INTEDG0: External Interrupt 0 Edge Select bit
1= Interrupt on rising edge
0= Interrupt on falling edge
INTEDG1: External Interrupt 1 Edge Select bit
1= Interrupt on rising edge
0= Interrupt on falling edge
INTEDG2: External Interrupt 2 Edge Select bit
1= Interrupt on rising edge
0= Interrupt on falling edge
bit 3
bit 2
Unimplemented: Read as ‘0’
TMR0IP: TMR0 Overflow Interrupt Priority bit
1= High priority
0= Low priority
bit 1
bit 0
Unimplemented: Read as ‘0’
RBIP: RB Port Change Interrupt Priority bit
1= High priority
0= Low priority
Note:
Interrupt flag bits are set when an interrupt
condition occurs, regardless of the state of
its corresponding enable bit or the global
enable bit. User software should ensure
the appropriate interrupt flag bits are clear
prior to enabling an interrupt. This feature
allows for software polling.
DS41303B-page 106
Advance Information
© 2007 Microchip Technology Inc.
PIC18F2XK20/4XK20
REGISTER 9-3:
INTCON3: INTERRUPT CONTROL 3 REGISTER
R/W-1
INT2IP
bit 7
R/W-1
U-0
—
R/W-0
R/W-0
U-0
—
R/W-0
INT2IF
R/W-0
INT1IF
INT1IP
INT2IE
INT1IE
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7
bit 6
INT2IP: INT2 External Interrupt Priority bit
1= High priority
0= Low priority
INT1IP: INT1 External Interrupt Priority bit
1= High priority
0= Low priority
bit 5
bit 4
Unimplemented: Read as ‘0’
INT2IE: INT2 External Interrupt Enable bit
1= Enables the INT2 external interrupt
0= Disables the INT2 external interrupt
bit 3
INT1IE: INT1 External Interrupt Enable bit
1= Enables the INT1 external interrupt
0= Disables the INT1 external interrupt
bit 2
bit 1
Unimplemented: Read as ‘0’
INT2IF: INT2 External Interrupt Flag bit
1= The INT2 external interrupt occurred (must be cleared by software)
0= The INT2 external interrupt did not occur
bit 0
INT1IF: INT1 External Interrupt Flag bit
1= The INT1 external interrupt occurred (must be cleared by software)
0= The INT1 external interrupt did not occur
Note:
Interrupt flag bits are set when an interrupt
condition occurs, regardless of the state of
its corresponding enable bit or the global
enable bit. User software should ensure
the appropriate interrupt flag bits are clear
prior to enabling an interrupt. This feature
allows for software polling.
© 2007 Microchip Technology Inc.
Advance Information
DS41303B-page 107
PIC18F2XK20/4XK20
9.5
PIR Registers
Note 1: Interrupt flag bits are set when an interrupt
condition occurs, regardless of the state of
its corresponding enable bit or the Global
Interrupt Enable bit, GIE of the INTCON
register.
The PIR registers contain the individual flag bits for the
peripheral interrupts. Due to the number of peripheral
interrupt sources, there are two Peripheral Interrupt
Request Flag registers (PIR1 and PIR2).
2: User software should ensure the appropri-
ate interrupt flag bits are cleared prior to
enabling an interrupt and after servicing
that interrupt.
REGISTER 9-4:
PIR1: PERIPHERAL INTERRUPT REQUEST (FLAG) REGISTER 1
R/W-0
PSPIF(1)
bit 7
R/W-0
ADIF
R-0
R-0
R/W-0
SSPIF
R/W-0
R/W-0
R/W-0
RCIF
TXIF
CCP1IF
TMR2IF
TMR1IF
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7
PSPIF: Parallel Slave Port Read/Write Interrupt Flag bit(1)
1= A read or a write operation has taken place (must be cleared by software)
0= No read or write has occurred
bit 6
bit 5
bit 4
bit 3
bit 2
ADIF: A/D Converter Interrupt Flag bit
1= An A/D conversion completed (must be cleared by software)
0= The A/D conversion is not complete or has not been started
RCIF: EUSART Receive Interrupt Flag bit
1= The EUSART receive buffer, RCREG, is full (cleared when RCREG is read)
0= The EUSART receive buffer is empty
TXIF: EUSART Transmit Interrupt Flag bit
1= The EUSART transmit buffer, TXREG, is empty (cleared when TXREG is written)
0= The EUSART transmit buffer is full
SSPIF: Master Synchronous Serial Port Interrupt Flag bit
1= The transmission/reception is complete (must be cleared by software)
0= Waiting to transmit/receive
CCP1IF: CCP1 Interrupt Flag bit
Capture mode:
1= A TMR1 register capture occurred (must be cleared by software)
0= No TMR1 register capture occurred
Compare mode:
1= A TMR1 register compare match occurred (must be cleared by software)
0= No TMR1 register compare match occurred
PWM mode:
Unused in this mode
bit 1
bit 0
TMR2IF: TMR2 to PR2 Match Interrupt Flag bit
1= TMR2 to PR2 match occurred (must be cleared by software)
0= No TMR2 to PR2 match occurred
TMR1IF: TMR1 Overflow Interrupt Flag bit
1= TMR1 register overflowed (must be cleared by software)
0= TMR1 register did not overflow
Note 1: The PSPIF bit is unimplemented on 28-pin devices and will read as ‘0’.
DS41303B-page 108
Advance Information
© 2007 Microchip Technology Inc.
PIC18F2XK20/4XK20
REGISTER 9-5:
PIR2: PERIPHERAL INTERRUPT REQUEST (FLAG) REGISTER 2
R/W-0
OSCFIF
bit 7
R/W-0
C1IF
R/W-0
C2IF
R/W-0
EEIF
R/W-0
BCLIF
R/W-0
R/W-0
R/W-0
HLVDIF
TMR3IF
CCP2IF
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
OSCFIF: Oscillator Fail Interrupt Flag bit
1= Device oscillator failed, clock input has changed to HFINTOSC (must be cleared by software)
0= Device clock operating
C1IF: Comparator C1 Interrupt Flag bit
1= Comparator C1 output has changed (must be cleared by software)
0= Comparator C1 output has not changed
C2IF: Comparator C2 Interrupt Flag bit
1= Comparator C2 output has changed (must be cleared by software)
0= Comparator C2 output has not changed
EEIF: Data EEPROM/Flash Write Operation Interrupt Flag bit
1= The write operation is complete (must be cleared by software)
0= The write operation is not complete or has not been started
BCLIF: Bus Collision Interrupt Flag bit
1= A bus collision occurred (must be cleared by software)
0= No bus collision occurred
HLVDIF: Low-Voltage Detect Interrupt Flag bit
1= A low-voltage condition occurred (direction determined by the VDIRMAG bit of the
HLVDCON register)
0= A low-voltage condition has not occurred
bit 1
bit 0
TMR3IF: TMR3 Overflow Interrupt Flag bit
1= TMR3 register overflowed (must be cleared by software)
0= TMR3 register did not overflow
CCP2IF: CCP2 Interrupt Flag bit
Capture mode:
1= A TMR1 register capture occurred (must be cleared by software)
0= No TMR1 register capture occurred
Compare mode:
1= A TMR1 register compare match occurred (must be cleared by software)
0= No TMR1 register compare match occurred
PWM mode:
Unused in this mode.
© 2007 Microchip Technology Inc.
Advance Information
DS41303B-page 109
PIC18F2XK20/4XK20
9.6
PIE Registers
The PIE registers contain the individual enable bits for
the peripheral interrupts. Due to the number of periph-
eral interrupt sources, there are two Peripheral Interrupt
Enable registers (PIE1 and PIE2). When IPEN = 0, the
PEIE bit must be set to enable any of these peripheral
interrupts.
REGISTER 9-6:
PIE1: PERIPHERAL INTERRUPT ENABLE (FLAG) REGISTER 1
R/W-0
PSPIE(1)
bit 7
R/W-0
ADIE
R/W-0
RCIE
R/W-0
TXIE
R/W-0
SSPIE
R/W-0
R/W-0
R/W-0
CCP1IE
TMR2IE
TMR1IE
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7
PSPIE: Parallel Slave Port Read/Write Interrupt Enable bit(1)
1= Enables the PSP read/write interrupt
0= Disables the PSP read/write interrupt
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
ADIE: A/D Converter Interrupt Enable bit
1= Enables the A/D interrupt
0= Disables the A/D interrupt
RCIE: EUSART Receive Interrupt Enable bit
1= Enables the EUSART receive interrupt
0= Disables the EUSART receive interrupt
TXIE: EUSART Transmit Interrupt Enable bit
1= Enables the EUSART transmit interrupt
0= Disables the EUSART transmit interrupt
SSPIE: Master Synchronous Serial Port Interrupt Enable bit
1= Enables the MSSP interrupt
0= Disables the MSSP interrupt
CCP1IE: CCP1 Interrupt Enable bit
1= Enables the CCP1 interrupt
0= Disables the CCP1 interrupt
TMR2IE: TMR2 to PR2 Match Interrupt Enable bit
1= Enables the TMR2 to PR2 match interrupt
0= Disables the TMR2 to PR2 match interrupt
TMR1IE: TMR1 Overflow Interrupt Enable bit
1= Enables the TMR1 overflow interrupt
0= Disables the TMR1 overflow interrupt
Note 1: The PSPIE bit is unimplemented on 28-pin devices and will read as ‘0’.
DS41303B-page 110
Advance Information
© 2007 Microchip Technology Inc.
PIC18F2XK20/4XK20
REGISTER 9-7:
PIE2: PERIPHERAL INTERRUPT ENABLE (FLAG) REGISTER 2
R/W-0
OSCFIE
bit 7
R/W-0
C1IE
R/W-0
C2IE
R/W-0
EEIE
R/W-0
BCLIE
R/W-0
R/W-0
R/W-0
HLVDIE
TMR3IE
CCP2IE
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
OSCFIE: Oscillator Fail Interrupt Enable bit
1= Enabled
0= Disabled
C1IE: Comparator C1 Interrupt Enable bit
1= Enabled
0= Disabled
C2IE: Comparator C2 Interrupt Enable bit
1= Enabled
0= Disabled
EEIE: Data EEPROM/Flash Write Operation Interrupt Enable bit
1= Enabled
0= Disabled
BCLIE: Bus Collision Interrupt Enable bit
1= Enabled
0= Disabled
HLVDIE: Low-Voltage Detect Interrupt Enable bit
1= Enabled
0= Disabled
TMR3IE: TMR3 Overflow Interrupt Enable bit
1= Enabled
0= Disabled
CCP2IE: CCP2 Interrupt Enable bit
1= Enabled
0= Disabled
© 2007 Microchip Technology Inc.
Advance Information
DS41303B-page 111
PIC18F2XK20/4XK20
9.7
IPR Registers
The IPR registers contain the individual priority bits for the
peripheral interrupts. Due to the number of peripheral
interrupt sources, there are two Peripheral Interrupt
Priority registers (IPR1 and IPR2). Using the priority bits
requires that the Interrupt Priority Enable (IPEN) bit be
set.
REGISTER 9-8:
IPR1: PERIPHERAL INTERRUPT PRIORITY REGISTER 1
R/W-1
PSPIP(1)
bit 7
R/W-1
ADIP
R/W-1
RCIP
R/W-1
TXIP
R/W-1
SSPIP
R/W-1
R/W-1
R/W-1
CCP1IP
TMR2IP
TMR1IP
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7
PSPIP: Parallel Slave Port Read/Write Interrupt Priority bit(1)
1= High priority
0= Low priority
bit 6
bit 5
bit 4
ADIP: A/D Converter Interrupt Priority bit
1= High priority
0= Low priority
RCIP: EUSART Receive Interrupt Priority bit
1= High priority
0= Low priority
TXIP: EUSART Transmit Interrupt Priority bit
1= High priority
0= Low priority
bit 3
bit 2
bit 1
bit 0
SSPIP: Master Synchronous Serial Port Interrupt Priority bit
1= High priority
0= Low priority
CCP1IP: CCP1 Interrupt Priority bit
1= High priority
0= Low priority
TMR2IP: TMR2 to PR2 Match Interrupt Priority bit
1= High priority
0= Low priority
TMR1IP: TMR1 Overflow Interrupt Priority bit
1= High priority
0= Low priority
Note 1: The PSPIF bit is unimplemented on 28-pin devices and will read as ‘0’.
DS41303B-page 112
Advance Information
© 2007 Microchip Technology Inc.
PIC18F2XK20/4XK20
REGISTER 9-9:
IPR2: PERIPHERAL INTERRUPT PRIORITY REGISTER 2
R/W-1
OSCFIP
bit 7
R/W-1
C1IP
R/W-1
C2IP
R/W-1
EEIP
R/W-1
BCLIP
R/W-1
R/W-1
R/W-1
HLVDIP
TMR3IP
CCP2IP
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
OSCFIP: Oscillator Fail Interrupt Priority bit
1= High priority
0= Low priority
C1IP: Comparator C1 Interrupt Priority bit
1= High priority
0= Low priority
C2IP: Comparator C2 Interrupt Priority bit
1= High priority
0= Low priority
EEIP: Data EEPROM/Flash Write Operation Interrupt Priority bit
1= High priority
0= Low priority
BCLIP: Bus Collision Interrupt Priority bit
1= High priority
0= Low priority
HLVDIP: Low-Voltage Detect Interrupt Priority bit
1= High priority
0= Low priority
TMR3IP: TMR3 Overflow Interrupt Priority bit
1= High priority
0= Low priority
CCP2IP: CCP2 Interrupt Priority bit
1= High priority
0= Low priority
© 2007 Microchip Technology Inc.
Advance Information
DS41303B-page 113
PIC18F2XK20/4XK20
9.8
RCON Register
The RCON register contains flag bits which are used to
determine the cause of the last Reset or wake-up from
Idle or Sleep modes. RCON also contains the IPEN bit
which enables interrupt priorities.
The operation of the SBOREN bit and the Reset flag
bits is discussed in more detail in Section 4.1 “RCON
Register”.
REGISTER 9-10: RCON: RESET CONTROL REGISTER
R/W-0
IPEN
R/W-1
SBOREN(1)
U-0
—
R/W-1
RI
R-1
TO
R-1
PD
R/W-0
POR(1)
R/W-0
BOR
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
-n = Value at POR
bit 7
bit 6
IPEN: Interrupt Priority Enable bit
1= Enable priority levels on interrupts
0= Disable priority levels on interrupts (Mid-Range Compatibility mode)
SBOREN: Software BOR Enable bit(1)
For details of bit operation, see Register 4-1.
Unimplemented: Read as ‘0’
bit 5
bit 4
RI: RESETInstruction Flag bit
For details of bit operation, see Register 4-1.
TO: Watchdog Time-out Flag bit
bit 3
bit 2
bit 1
bit 0
For details of bit operation, see Register 4-1.
PD: Power-down Detection Flag bit
For details of bit operation, see Register 4-1
POR: Power-on Reset Status bit
For details of bit operation, see Register 4-1.
BOR: Brown-out Reset Status bit
For details of bit operation, see Register 4-1.
Note 1: Actual Reset values are determined by device configuration and the nature of the device Reset.
See Register 4-1 for additional information.
DS41303B-page 114
Advance Information
© 2007 Microchip Technology Inc.
PIC18F2XK20/4XK20
9.9
INTn Pin Interrupts
9.10 TMR0 Interrupt
External interrupts on the RB0/INT0, RB1/INT1 and
RB2/INT2 pins are edge-triggered. If the corresponding
INTEDGx bit in the INTCON2 register is set (= 1), the
interrupt is triggered by a rising edge; if the bit is clear,
the trigger is on the falling edge. When a valid edge
appears on the RBx/INTx pin, the corresponding flag
bit, INTxF, is set. This interrupt can be disabled by
clearing the corresponding enable bit, INTxE. Flag bit,
INTxF, must be cleared by software in the Interrupt
Service Routine before re-enabling the interrupt.
In 8-bit mode (which is the default), an overflow in the
TMR0 register (FFh → 00h) will set flag bit, TMR0IF. In
16-bit mode, an overflow in the TMR0H:TMR0L regis-
ter pair (FFFFh → 0000h) will set TMR0IF. The interrupt
can be enabled/disabled by setting/clearing enable bit,
TMR0IE of the INTCON register. Interrupt priority for
Timer0 is determined by the value contained in the
interrupt priority bit, TMR0IP of the INTCON2 register.
See Section 11.0 “Timer0 Module” for further details
on the Timer0 module.
All external interrupts (INT0, INT1 and INT2) can wake-
up the processor from Idle or Sleep modes if bit INTxE
was set prior to going into those modes. If the Global
Interrupt Enable bit, GIE, is set, the processor will
branch to the interrupt vector following wake-up.
9.11 PORTB Interrupt-on-Change
An input change on PORTB<7:4> sets flag bit, RBIF of
the INTCON register. The interrupt can be enabled/
disabled by setting/clearing enable bit, RBIE of the
INTCON register. Pins must also be individually
enabled with the IOCB register. Interrupt priority for
PORTB interrupt-on-change is determined by the value
contained in the interrupt priority bit, RBIP of the
INTCON2 register.
Interrupt priority for INT1 and INT2 is determined by the
value contained in the interrupt priority bits, INT1IP and
INT2IP of the INTCON3 register. There is no priority bit
associated with INT0. It is always a high priority inter-
rupt source.
9.12 Context Saving During Interrupts
During interrupts, the return PC address is saved on
the stack. Additionally, the WREG, STATUS and BSR
registers are saved on the fast return stack. If a fast
return from interrupt is not used (see Section 5.3
“Data Memory Organization”), the user may need to
save the WREG, STATUS and BSR registers on entry
to the Interrupt Service Routine. Depending on the
user’s application, other registers may also need to be
saved. Example 9-1 saves and restores the WREG,
STATUS and BSR registers during an Interrupt Service
Routine.
EXAMPLE 9-1:
SAVING STATUS, WREG AND BSR REGISTERS IN RAM
MOVWF
MOVFF
MOVFF
;
W_TEMP
STATUS, STATUS_TEMP
BSR, BSR_TEMP
; W_TEMP is in virtual bank
; STATUS_TEMP located anywhere
; BSR_TMEP located anywhere
; USER ISR CODE
;
MOVFF
MOVF
MOVFF
BSR_TEMP, BSR
W_TEMP, W
STATUS_TEMP, STATUS
; Restore BSR
; Restore WREG
; Restore STATUS
© 2007 Microchip Technology Inc.
Advance Information
DS41303B-page 115
PIC18F2XK20/4XK20
NOTES:
DS41303B-page 116
Advance Information
© 2007 Microchip Technology Inc.
PIC18F2XK20/4XK20
Reading the PORTA register reads the status of the
pins, whereas writing to it, will write to the PORT latch.
10.0 I/O PORTS
Depending on the device selected and features
enabled, there are up to five ports available. Some pins
of the I/O ports are multiplexed with an alternate
function from the peripheral features on the device. In
general, when a peripheral is enabled, that pin may not
be used as a general purpose I/O pin.
The Data Latch (LATA) register is also memory mapped.
Read-modify-write operations on the LATA register read
and write the latched output value for PORTA.
The RA4 pin is multiplexed with the Timer0 module
clock input and one of the comparator outputs to
become the RA4/T0CKI/C1OUT pin. Pins RA6 and
RA7 are multiplexed with the main oscillator pins; they
are enabled as oscillator or I/O pins by the selection of
the main oscillator in the Configuration register (see
Section 23.1 “Configuration Bits” for details). When
they are not used as port pins, RA6 and RA7 and their
associated TRIS and LAT bits are read as ‘0’.
Each port has three registers for its operation. These
registers are:
• TRIS register (data direction register)
• PORT register (reads the levels on the pins of the
device)
• LAT register (output latch)
The other PORTA pins are multiplexed with analog
inputs, the analog VREF+ and VREF- inputs, and the
comparator voltage reference output. The operation of
pins RA<3:0> and RA5 as analog is selected by setting
the ANS<4:0> bits in the ANSEL register which is the
default setting after a Power-on Reset.
The Data Latch (LAT register) is useful for read-modify-
write operations on the value that the I/O pins are
driving.
A simplified model of a generic I/O port, without the
interfaces to other peripherals, is shown in Figure 10-1.
Pins RA0 through RA5 may also be used as comparator
inputs or outputs by setting the appropriate bits in the
CM1CON0 and CM2CON0 registers.
FIGURE 10-1:
GENERIC I/O PORT
OPERATION
Note:
On a Power-on Reset, RA5 and RA<3:0>
are configured as analog inputs and read
as ‘0’. RA4 is configured as a digital input.
RD LAT
Data
Bus
D
Q
The RA4/T0CKI/C1OUT pin is a Schmitt Trigger input.
All other PORTA pins have TTL input levels and full
CMOS output drivers.
I/O pin(1)
WR LAT
or
Port
CK
Data Latch
The TRISA register controls the drivers of the PORTA
pins, even when they are being used as analog inputs.
The user should ensure the bits in the TRISA register
are maintained set when using them as analog inputs.
D
Q
WR TRIS
RD TRIS
CK
TRIS Latch
Input
Buffer
EXAMPLE 10-1:
INITIALIZING PORTA
CLRF
PORTA
LATA
07h
; Initialize PORTA by
; clearing output
; data latches
; Alternate method
; to clear output
; data latches
Q
D
CLRF
EN
MOVLW
MOVWF
MOVWF
MOVWF
MOVLW
; Configure A/D
RD Port
ADCON1 ; for digital inputs
07h
CMCON
0CFh
; Configure comparators
; for digital input
; Value used to
Note 1: I/O pins have diode protection to VDD and VSS.
; initialize data
; direction
; Set RA<3:0> as inputs
; RA<5:4> as outputs
10.1 PORTA, TRISA and LATA Registers
MOVWF
TRISA
PORTA is an 8-bit wide, bidirectional port. The
corresponding data direction register is TRISA. Setting
a TRISA bit (= 1) will make the corresponding PORTA
pin an input (i.e., disable the output driver). Clearing a
TRISA bit (= 0) will make the corresponding PORTA pin
an output (i.e., enable the output driver and put the
contents of the output latch on the selected pin).
© 2007 Microchip Technology Inc.
Advance Information
DS41303B-page 117
PIC18F2XK20/4XK20
TABLE 10-1: PORTA I/O SUMMARY
TRIS
Setting
I/O
Type
Pin
Function
I/O
Description
RA0/AN0/C12IN0-
RA0
0
1
1
O
I
DIG LATA<0> data output; not affected by analog input.
TTL PORTA<0> data input; disabled when analog input enabled.
AN0
C12IN0-
RA1
I
ANA ADC input channel 0. Default input configuration on POR; does not
affect digital output.
1
I
ANA Comparators C1 and C2 inverting input, channel 0. Analog select is
shared with ADC.
RA1/AN1/C12IN1-
0
1
1
O
I
DIG LATA<1> data output; not affected by analog input.
TTL PORTA<1> data input; disabled when analog input enabled.
AN1
C12IN1-
RA2
I
ANA ADC input channel 1. Default input configuration on POR; does not
affect digital output.
1
0
1
1
1
I
O
I
ANA Comparators C1 and C2 inverting input, channel 1. Analog select is
shared with ADC.
RA2/AN2/C2IN+
VREF-/CVREF
DIG LATA<2> data output; not affected by analog input. Disabled when
CVREF output enabled.
TTL PORTA<2> data input. Disabled when analog functions enabled;
disabled when CVREF output enabled.
AN2
I
ANA ADC input channel 2. Default input configuration on POR; not affected
by analog output.
C2IN+
I
ANA Comparator C2 non-inverting input. Analog selection is shared with
ADC.
VREF-
1
x
I
ANA ADC and comparator voltage reference low input.
CVREF
O
ANA Comparator voltage reference output. Enabling this feature disables
digital I/O.
RA3/AN3/C1IN+/
VREF+
RA3
0
1
1
1
O
I
DIG LATA<3> data output; not affected by analog input.
TTL PORTA<3> data input; disabled when analog input enabled.
ANA A/D input channel 3. Default input configuration on POR.
AN3
I
C1IN+
I
ANA Comparator C1 non-inverting input. Analog selection is shared with
ADC.
VREF+
RA4
1
0
1
1
0
0
1
1
1
1
0
0
1
I
O
I
ANA ADC and comparator voltage reference high input.
DIG LATA<4> data output.
RA4/T0CKI/C1OUT
ST
ST
PORTA<4> data input; default configuration on POR.
Timer0 clock input.
T0CKI
C1OUT
RA5
I
O
O
I
DIG Comparator 1 output; takes priority over port data.
DIG LATA<5> data output; not affected by analog input.
TTL PORTA<5> data input; disabled when analog input enabled.
ANA A/D input channel 4. Default configuration on POR.
TTL Slave select input for SSP (MSSP module).
RA5/AN4/SS/
HLVDIN/C2OUT
AN4
SS
I
I
HLVDIN
C2OUT
RA6
I
ANA Low-Voltage Detect external trip point input.
O
O
I
DIG Comparator 2 output; takes priority over port data.
DIG LATA<6> data output. Enabled in RCIO, INTIO2 and ECIO modes only.
OSC2/CLKOUT/
RA6
TTL PORTA<6> data input. Enabled in RCIO, INTIO2 and ECIO modes
only.
OSC2
x
x
O
O
ANA Main oscillator feedback output connection (XT, HS and LP modes).
CLKOUT
DIG System cycle clock output (FOSC/4) in RC, INTIO1 and EC Oscillator
modes.
Legend:
DIG = Digital level output; TTL = TTL input buffer; ST = Schmitt Trigger input buffer; ANA = Analog level input/output;
x= Don’t care (TRIS bit does not affect port direction or is overridden for this option).
DS41303B-page 118
Advance Information
© 2007 Microchip Technology Inc.
PIC18F2XK20/4XK20
TABLE 10-1: PORTA I/O SUMMARY (CONTINUED)
TRIS
Setting
I/O
Type
Pin
Function
I/O
Description
OSC1/CLKIN/RA7
RA7
0
1
x
x
O
I
DIG LATA<7> data output. Disabled in external oscillator modes.
TTL PORTA<7> data input. Disabled in external oscillator modes.
ANA Main oscillator input connection.
OSC1
CLKIN
I
I
ANA Main clock input connection.
Legend:
DIG = Digital level output; TTL = TTL input buffer; ST = Schmitt Trigger input buffer; ANA = Analog level input/output;
x= Don’t care (TRIS bit does not affect port direction or is overridden for this option).
TABLE 10-2: SUMMARY OF REGISTERS ASSOCIATED WITH PORTA
Reset
Values
on page
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PORTA
RA7(1)
RA6(1)
RA5
RA4
RA3
RA2
RA1
RA0
60
60
60
60
61
60
60
59
LATA
LATA7(1) LATA6(1) PORTA Data Latch Register (Read and Write to Data Latch)
TRISA7(1) TRISA6(1) PORTA Data Direction Control Register
ANS7(2)
TRISA
ANSEL
ANS6(2) ANS5(2)
ANS4
SLRE
ANS3
SLRD
C1SP
C2SP
CVR3
ANS2
SLRC
C1R
ANS1
SLRB
ANS0
SLRA
SLRCON
CM1CON
CM2CON
CVRCON
—
—
—
C1ON
C2ON
CVREN
C1OUT
C2OUT
CVROE
C1OE
C2OE
CVRR
C1POL
C2POL
CVRSS
C1CH1
C2CH1
CVR1
C1CH0
C2CH0
CVR0
C2R
CVR2
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PORTA.
Note 1: RA<7:6> and their associated latch and data direction bits are enabled as I/O pins based on oscillator
configuration; otherwise, they are read as ‘0’.
2: Not implemented on PIC18F2XK20 devices.
© 2007 Microchip Technology Inc.
Advance Information
DS41303B-page 119
PIC18F2XK20/4XK20
10.3.2
INTERRUPT-ON-CHANGE
10.2 PORTB, TRISB and LATB
Registers
Four of the PORTB pins (RB<7:4>) are individually
configurable as interrupt-on-change pins. Control bits
in the IOCB register enable (when set) or disable (when
clear) the interrupt function for each pin.
PORTB is an 8-bit wide, bidirectional port. The corre-
sponding data direction register is TRISB. Setting a
TRISB bit (= 1) will make the corresponding PORTB
pin an input (i.e., disable the output driver). Clearing a
TRISB bit (= 0) will make the corresponding PORTB
pin an output (i.e., enable the output driver and put the
contents of the output latch on the selected pin).
When set, the RBIE bit of the INTCON register enables
interrupts on all pins which also have their correspond-
ing IOCB bit set. When clear, the RBIE bit disables all
interrupt-on-changes.
Only pins configured as inputs can cause this interrupt
to occur (i.e., any RB<7:4> pin configured as an output
is excluded from the interrupt-on-change comparison).
The Data Latch register (LATB) is also memory
mapped. Read-modify-write operations on the LATB
register read and write the latched output value for
PORTB.
For enabled interrupt-on-change pins, the values are
compared with the old value latched on the last read of
PORTB. The ‘mismatch’ outputs of the last read are
OR’d together to set the PORTB Change Interrupt flag
bit (RBIF) in the INTCON register.
EXAMPLE 10-2:
INITIALIZING PORTB
CLRF
PORTB
LATB
0Fh
; Initialize PORTB by
; clearing output
; data latches
; Alternate method
; to clear output
; data latches
This interrupt can wake the device from the Sleep
mode, or any of the Idle modes. The user, in the
Interrupt Service Routine, can clear the interrupt in the
following manner:
CLRF
MOVLW
MOVWF
; Set RB<4:0> as
ADCON1 ; digital I/O pins
;(required if config bit
a) Any read or write of PORTB to clear the mis-
match condition (except when PORTB is the
source or destination of a MOVFF instruction).
; PBADEN is set)
; Value used to
; initialize data
; direction
; Set RB<3:0> as inputs
; RB<5:4> as outputs
; RB<7:6> as inputs
MOVLW
MOVWF
0CFh
b) Clear the flag bit, RBIF.
A mismatch condition will continue to set the RBIF flag bit.
Reading or writing PORTB will end the mismatch
condition and allow the RBIF bit to be cleared. The latch
holding the last read value is not affected by a MCLR nor
Brown-out Reset. After either one of these Resets, the
RBIF flag will continue to be set if a mismatch is present.
TRISB
10.3 Additional PORTB Pin Functions
Note:
If a change on the I/O pin should occur
when the read operation is being executed
(start of the Q2 cycle), then the RBIF
interrupt flag may not get set. Furthermore,
since a read or write on a port affects all bits
of that port, care must be taken when using
multiple pins in Interrupt-on-change mode.
Changes on one pin may not be seen while
servicing changes on another pin.
PORTB pins RB<7:4> have an interrupt-on-change
option. All PORTB pins have a weak pull-up option. An
alternate CCP2 peripheral option is available on RB3.
10.3.1
WEAK PULL-UPS
Each of the PORTB pins has an individually controlled
weak internal pull-up. When set, each bit of the WPUB
register enables the corresponding pin pull-up. When
cleared, the RBPU bit of the INTCON2 register enables
pull-ups on all pins which also have their corresponding
WPUB bit set. When set, the RBPU bit disables all
weak pull-ups. The weak pull-up is automatically turned
off when the port pin is configured as an output. The
pull-ups are disabled on a Power-on Reset.
The interrupt-on-change feature is recommended for
wake-up on key depression operation and operations
where PORTB is only used for the interrupt-on-change
feature. Polling of PORTB is not recommended while
using the interrupt-on-change feature.
Note:
On a Power-on Reset, RB<4:0> are
configured as analog inputs by default and
read as ‘0’; RB<7:5> are configured as
digital inputs.
10.3.3
ALTERNATE CCP2 OPTION
RB3 can be configured as the alternate peripheral pin
for the CCP2 module by clearing the CCP2MX Config-
uration bit of CONFIG3H. The default state of the
CCP2MX Configuration bit is ‘1’ which selects RC1 as
the CCP2 peripheral pin.
When the PBADEN Configuration bit is set
to ‘1’, RB<4:0> will alternatively be
configured as digital inputs on POR.
DS41303B-page 120
Advance Information
© 2007 Microchip Technology Inc.
PIC18F2XK20/4XK20
TABLE 10-3: PORTB I/O SUMMARY
TRIS
Setting
I/O
Type
Pin
Function
I/O
Description
RB0/INT0/FLT0/
AN12
RB0
0
1
O
I
DIG LATB<0> data output; not affected by analog input.
TTL PORTB<0> data input; Programmable weak pull-up. Disabled when
(1)
analog input enabled.
INT0
FLT0
AN12
RB1
1
1
1
0
1
I
I
ST
ST
External interrupt 0 input.
Enhanced PWM Fault input (ECCP1 module); enabled by software.
(1)
I
ANA A/D input channel 12.
RB1/INT1/AN10/
C12IN2-/P1C
O
I
DIG LATB<1> data output; not affected by analog input.
TTL PORTB<1> data input; Programmable weak pull-up. Disabled when
(1)
analog input enabled.
INT1
AN10
1
1
1
I
I
I
ST
External Interrupt 1 input.
(1)
ANA ADC input channel 10.
C12IN2-
ANA Comparators C1 and C2 inverting input, channel 2. Analog select is
shared with ADC.
P1C
RB2
0
0
1
O
O
I
DIG ECCP PWM output (28-pin devices only).
RB2/INT2/AN8/
P1B
DIG LATB<2> data output; not affected by analog input.
TTL PORTB<2> data input; Programmable weak pull-up. Disabled when
(1)
analog input enabled.
INT2
AN8
P1B
RB3
1
1
0
0
1
I
I
ST
External interrupt 2 input.
(1)
ANA ADC input channel 8.
O
O
I
DIG ECCP PWM output (28-pin devices only).
DIG LATB<3> data output; not affected by analog input.
TTL PORTB<3> data input; Programmable weak pull-up. Disabled when
RB3/AN9/C12IN3-/
CCP2
(1)
analog input enabled.
(1)
AN9
1
1
I
I
ANA ADC input channel 9.
C12IN3-
ANA Comparators C1 and C2 inverting input, channel 3. Analog select is
shared with ADC.
(2)
CCP2
0
1
0
1
O
I
DIG CCP2 compare and PWM output.
ST
CCP2 capture input
RB4/KBI0/AN11/
P1D
RB4
O
I
DIG LATB<4> data output; not affected by analog input.
TTL PORTB<4> data input; Programmable weak pull-up. Disabled when
(1)
analog input enabled.
KBI0
AN11
P1D
1
1
0
0
1
1
x
I
I
TTL Interrupt-on-pin change.
(1)
ANA ADC input channel 11.
O
O
I
DIG ECCP PWM output (28-pin devices only).
DIG LATB<5> data output.
RB5/KBI1/PGM
RB5
TTL PORTB<5> data input; Programmable weak pull-up.
TTL Interrupt-on-pin change.
KBI1
PGM
I
I
ST
Single-Supply Programming mode entry (ICSP™). Enabled by LVP
Configuration bit; all other pin functions disabled.
Legend:
DIG = Digital level output; TTL = TTL input buffer; ST = Schmitt Trigger input buffer; ANA = Analog level input/output;
x= Don’t care (TRIS bit does not affect port direction or is overridden for this option).
Note 1: Configuration on POR is determined by the PBADEN Configuration bit. Pins are configured as analog inputs by default
when PBADEN is set and digital inputs when PBADEN is cleared.
2: Alternate assignment for CCP2 when the CCP2MX Configuration bit is ‘0’. Default assignment is RC1.
3: All other pin functions are disabled when ICSP or ICD are enabled.
© 2007 Microchip Technology Inc.
Advance Information
DS41303B-page 121
PIC18F2XK20/4XK20
TABLE 10-3: PORTB I/O SUMMARY (CONTINUED)
TRIS
Setting
I/O
Type
Pin
Function
I/O
Description
RB6/KBI2/PGC
RB6
0
1
1
x
0
1
1
x
x
O
I
DIG LATB<6> data output.
TTL PORTB<6> data input; Programmable weak pull-up.
TTL Interrupt-on-pin change.
KBI2
PGC
RB7
I
(3)
I
ST
Serial execution (ICSP) clock input for ICSP and ICD operation.
RB7/KBI3/PGD
O
I
DIG LATB<7> data output.
TTL PORTB<7> data input; Programmable weak pull-up.
TTL Interrupt-on-pin change.
KBI3
PGD
I
(3)
O
I
DIG Serial execution data output for ICSP and ICD operation.
(3)
ST
Serial execution data input for ICSP and ICD operation.
Legend:
DIG = Digital level output; TTL = TTL input buffer; ST = Schmitt Trigger input buffer; ANA = Analog level input/output;
x= Don’t care (TRIS bit does not affect port direction or is overridden for this option).
Note 1: Configuration on POR is determined by the PBADEN Configuration bit. Pins are configured as analog inputs by default
when PBADEN is set and digital inputs when PBADEN is cleared.
2: Alternate assignment for CCP2 when the CCP2MX Configuration bit is ‘0’. Default assignment is RC1.
3: All other pin functions are disabled when ICSP or ICD are enabled.
TABLE 10-4: SUMMARY OF REGISTERS ASSOCIATED WITH PORTB
Reset
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Values
on page
PORTB
RB7
RB6
RB5
RB4
RB3
RB2
RB1
RB0
60
60
60
60
60
61
57
57
57
60
LATB
PORTB Data Latch Register (Read and Write to Data Latch)
PORTB Data Direction Control Register
TRISB
WPUB
WPUB7
IOCB7
—
WPUB6
IOCB6
—
WPUB5 WPUB4 WPUB3 WPUB2 WPUB1 WPUB0
IOCB
IOCB5
—
IOCB4
SLRE
SLRCON
INTCON
INTCON2
INTCON3
ANSELH
SLRD
RBIE
—
SLRC
TMR0IF
TMR0IP
—
SLRB
INT0IF
—
SLRA
RBIF
GIE/GIEH PEIE/GIEL TMR0IE
INT0IE
RBPU
INT2IP
—
INTEDG0 INTEDG1 INTEDG2
RBIP
INT1IP
—
—
—
INT2IE
ANS12
INT1IE
ANS11
INT2IF
ANS9
INT1IF
ANS8
ANS10
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PORTB.
DS41303B-page 122
Advance Information
© 2007 Microchip Technology Inc.
PIC18F2XK20/4XK20
EXAMPLE 10-3:
INITIALIZING PORTC
10.4 PORTC, TRISC and LATC
Registers
CLRF
PORTC
; Initialize PORTC by
; clearing output
; data latches
; Alternate method
; to clear output
; data latches
; Value used to
; initialize data
; direction
PORTC is an 8-bit wide, bidirectional port. The corre-
sponding data direction register is TRISC. Setting a
TRISC bit (= 1) will make the corresponding PORTC
pin an input (i.e., disable the output driver). Clearing a
TRISC bit (= 0) will make the corresponding PORTC
pin an output (i.e., enable the output driver and put the
contents of the output latch on the selected pin).
CLRF
LATC
MOVLW
MOVWF
0CFh
TRISC
; Set RC<3:0> as inputs
; RC<5:4> as outputs
; RC<7:6> as inputs
The Data Latch register (LATC) is also memory
mapped. Read-modify-write operations on the LATC
register read and write the latched output value for
PORTC.
PORTC is multiplexed with several peripheral functions
(Table 10-5). The pins have Schmitt Trigger input buff-
ers. RC1 is the default configuration for the CCP2
peripheral pin. The CCP2 function can be relocated to
the RB3 pin by clearing the CCP2MX bit of Configura-
tion Word CONFIG3H. The default state of the
CCP2MX Configuration bit is ‘1’.
When enabling peripheral functions, care should be
taken in defining TRIS bits for each PORTC pin. The
EUSART and MSSP peripherals override the TRIS bit
to make a pin an output or an input, depending on the
peripheral configuration. Refer to the corresponding
peripheral section for additional information.
Note:
On a Power-on Reset, these pins are con-
figured as digital inputs.
The contents of the TRISC register are affected by
peripheral overrides. Reading TRISC always returns
the current contents, even though a peripheral device
may be overriding one or more of the pins.
© 2007 Microchip Technology Inc.
Advance Information
DS41303B-page 123
PIC18F2XK20/4XK20
TABLE 10-5: PORTC I/O SUMMARY
TRIS
Setting
I/O
Type
Pin
Function
I/O
Description
RC0/T1OSO/
T13CKI
RC0
0
1
x
O
I
DIG
ST
LATC<0> data output.
PORTC<0> data input.
T1OSO
O
ANA
Timer1 oscillator output; enabled when Timer1 oscillator enabled.
Disables digital I/O.
T13CKI
RC1
1
0
1
x
I
O
I
ST
DIG
ST
Timer1/Timer3 counter input.
LATC<1> data output.
RC1/T1OSI/CCP2
PORTC<1> data input.
T1OSI
I
ANA
Timer1 oscillator input; enabled when Timer1 oscillator enabled.
Disables digital I/O.
(1)
CCP2
0
1
0
1
0
1
0
O
I
DIG
ST
CCP2 compare and PWM output; takes priority over port data.
CCP2 capture input.
RC2/CCP1/P1A
RC2
CCP1
P1A
O
I
DIG
ST
LATC<2> data output.
PORTC<2> data input.
O
I
DIG
ST
ECCP1 compare or PWM output; takes priority over port data.
ECCP1 capture input.
O
DIG
ECCP1 Enhanced PWM output, channel A. May be configured for
tri-state during Enhanced PWM shutdown events. Takes priority over
port data.
RC3/SCK/SCL
RC3
SCK
SCL
RC4
0
1
0
1
0
1
0
1
1
1
1
0
1
0
0
1
1
O
I
DIG
ST
LATC<3> data output.
PORTC<3> data input.
O
I
DIG
ST
SPI clock output (MSSP module); takes priority over port data.
SPI clock input (MSSP module).
2
O
I
DIG
I C™ clock output (MSSP module); takes priority over port data.
2
2
I C/SMB I C clock input (MSSP module); input type depends on module setting.
RC4/SDI/SDA
O
I
DIG
ST
LATC<4> data output.
PORTC<4> data input.
SDI
I
ST
SPI data input (MSSP module).
2
SDA
O
I
DIG
I C data output (MSSP module); takes priority over port data.
2
2
I C/SMB I C data input (MSSP module); input type depends on module setting.
RC5/SDO
RC5
O
I
DIG
ST
LATC<5> data output.
PORTC<5> data input.
SDO
RC6
O
O
I
DIG
DIG
ST
SPI data output (MSSP module); takes priority over port data.
LATC<6> data output.
RC6/TX/CK
PORTC<6> data input.
TX
CK
O
DIG
Asynchronous serial transmit data output (USART module); takes
priority over port data. User must configure as output.
1
O
DIG
Synchronous serial clock output (USART module); takes priority over
port data.
1
0
1
1
1
I
O
I
ST
DIG
ST
Synchronous serial clock input (USART module).
LATC<7> data output.
RC7/RX/DT
RC7
PORTC<7> data input.
RX
DT
I
ST
Asynchronous serial receive data input (USART module).
O
DIG
Synchronous serial data output (USART module); takes priority over
port data.
1
I
ST
Synchronous serial data input (USART module). User must configure
as an input.
Legend:
DIG = Digital level output; TTL = TTL input buffer; ST = Schmitt Trigger input buffer; ANA = Analog level input/output;
2
2
I C/SMB = I C/SMBus input buffer; x= Don’t care (TRIS bit does not affect port direction or is overridden for this option).
Note 1: Default assignment for CCP2 when the CCP2MX Configuration bit is set. Alternate assignment is RB3.
DS41303B-page 124
Advance Information
© 2007 Microchip Technology Inc.
PIC18F2XK20/4XK20
TABLE 10-6: SUMMARY OF REGISTERS ASSOCIATED WITH PORTC
Reset
Values
on page
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PORTC
RC7
RC6
RC5
RC4
RC3
RC2
RC1
RC0
60
60
60
58
59
59
59
58
59
59
59
61
LATC
PORTC Data Latch Register (Read and Write to Data Latch)
PORTC Data Direction Control Register
TRISC
T1CON
RD16
RD16
CSRC
SPEN
WCOL
P1M1
—
T1RUN T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON
T3CCP2 T3CKPS1 T3CKPS0 T3CCP1 T3SYNC TMR3CS TMR3ON
T3CON
TXSTA
TX9
RX9
TXEN
SREN
SYNC
CREN
CKP
SENDB
ADDEN
SSPM3
BRGH
FERR
TRMT
OERR
SSPM1
TX9D
RX9D
RCSTA
SSPCON1
CCP1CON
CCP2CON
ECCP1AS
SLRCON
SSPOV
P1M0
—
SSPEN
DC1B1
DC2B1
SSPM2
SSPM0
DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0
DC2B0 CCP2M3 CCP2M2 CCP2M1 CCP2M0
ECCPASE ECCPAS2 ECCPAS1 ECCPAS0 PSSAC1 PSSAC0 PSSBD1 PSSBD0
SLRE SLRD SLRC SLRB SLRA
—
—
—
© 2007 Microchip Technology Inc.
Advance Information
DS41303B-page 125
PIC18F2XK20/4XK20
PORTD can also be configured as an 8-bit wide micro-
processor port (Parallel Slave Port) by setting control
bit, PSPMODE (TRISE<4>). In this mode, the input
buffers are TTL. See Section 10.9 “Parallel Slave
Port” for additional information on the Parallel Slave
Port (PSP).
10.5 PORTD, TRISD and LATD
Registers
Note:
PORTD is only available on 40/44-pin
devices.
PORTD is an 8-bit wide, bidirectional port. The corre-
sponding data direction register is TRISD. Setting a
TRISD bit (= 1) will make the corresponding PORTD
pin an input (i.e., disable the output driver). Clearing a
TRISD bit (= 0) will make the corresponding PORTD
pin an output (i.e., enable the output driver and put the
contents of the output latch on the selected pin).
Note:
When the enhanced PWM mode is used
with either dual or quad outputs, the PSP
functions of PORTD are automatically
disabled.
EXAMPLE 10-4:
INITIALIZING PORTD
CLRF
PORTD
; Initialize PORTD by
; clearing output
; data latches
; Alternate method
; to clear output
; data latches
; Value used to
; initialize data
; direction
The Data Latch register (LATD) is also memory
mapped. Read-modify-write operations on the LATD
register read and write the latched output value for
PORTD.
CLRF
LATD
All pins on PORTD are implemented with Schmitt Trig-
ger input buffers. Each pin is individually configurable
as an input or output.
MOVLW
MOVWF
0CFh
Three of the PORTD pins are multiplexed with outputs
P1B, P1C and P1D of the enhanced CCP module. The
operation of these additional PWM output pins is
covered in greater detail in Section 16.0 “Enhanced
Capture/Compare/PWM (ECCP) Module”.
TRISD
; Set RD<3:0> as inputs
; RD<5:4> as outputs
; RD<7:6> as inputs
Note:
On a Power-on Reset, these pins are
configured as digital inputs.
DS41303B-page 126
Advance Information
© 2007 Microchip Technology Inc.
PIC18F2XK20/4XK20
TABLE 10-7: PORTD I/O SUMMARY
TRIS
Setting
I/O
Type
Pin
Function
I/O
Description
RD0/PSP0
RD0
0
1
x
x
0
1
x
x
0
1
x
x
0
1
x
x
0
1
x
x
0
1
x
x
0
O
I
DIG
ST
LATD<0> data output.
PORTD<0> data input.
PSP0
RD1
O
I
DIG
TTL
DIG
ST
PSP read data output (LATD<0>); takes priority over port data.
PSP write data input.
RD1/PSP1
RD2/PSP2
RD3/PSP3
RD4/PSP4
RD5/PSP5/P1B
O
I
LATD<1> data output.
PORTD<1> data input.
PSP1
RD2
O
I
DIG
TTL
DIG
ST
PSP read data output (LATD<1>); takes priority over port data.
PSP write data input.
O
I
LATD<2> data output.
PORTD<2> data input.
PSP2
RD3
O
I
DIG
TTL
DIG
ST
PSP read data output (LATD<2>); takes priority over port data.
PSP write data input.
O
I
LATD<3> data output.
PORTD<3> data input.
PSP3
RD4
O
I
DIG
TTL
DIG
ST
PSP read data output (LATD<3>); takes priority over port data.
PSP write data input.
O
I
LATD<4> data output.
PORTD<4> data input.
PSP4
RD5
O
I
DIG
TTL
DIG
ST
PSP read data output (LATD<4>); takes priority over port data.
PSP write data input.
O
I
LATD<5> data output.
PORTD<5> data input.
PSP5
P1B
O
I
DIG
TTL
DIG
PSP read data output (LATD<5>); takes priority over port data.
PSP write data input.
O
ECCP1 Enhanced PWM output, channel B; takes priority over port and
PSP data. May be configured for tri-state during Enhanced PWM
shutdown events.
RD6/PSP6/P1C
RD6
PSP6
P1C
0
1
x
x
0
O
I
DIG
ST
LATD<6> data output.
PORTD<6> data input.
O
I
DIG
TTL
DIG
PSP read data output (LATD<6>); takes priority over port data.
PSP write data input.
O
ECCP1 Enhanced PWM output, channel C; takes priority over port and
PSP data. May be configured for tri-state during Enhanced PWM
shutdown events.
RD7/PSP7/P1D
RD7
PSP7
P1D
0
1
x
x
0
O
I
DIG
ST
LATD<7> data output.
PORTD<7> data input.
O
I
DIG
TTL
DIG
PSP read data output (LATD<7>); takes priority over port data.
PSP write data input.
O
ECCP1 Enhanced PWM output, channel D; takes priority over port and
PSP data. May be configured for tri-state during Enhanced PWM
shutdown events.
Legend:
DIG = Digital level output; TTL = TTL input buffer; ST = Schmitt Trigger input buffer; x= Don’t care
(TRIS bit does not affect port direction or is overridden for this option).
© 2007 Microchip Technology Inc.
Advance Information
DS41303B-page 127
PIC18F2XK20/4XK20
TABLE 10-8: SUMMARY OF REGISTERS ASSOCIATED WITH PORTD
Reset
Values
on page
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PORTD
LATD
RD7
RD6
RD5
RD4
RD3
RD2
RD1
RD0
60
60
60
60
59
61
PORTD Data Latch Register (Read and Write to Data Latch)
PORTD Data Direction Control Register
TRISD
TRISE
IBF
P1M1
—
OBF
P1M0
—
IBOV
DC1B1
—
PSPMODE
DC1B0
—
TRISE2
TRISE1
TRISE0
CCP1CON
SLRCON
CCP1M3 CCP1M2 CCP1M1 CCP1M0
SLRD SLRC SLRB SLRA
SLRE
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PORTD.
DS41303B-page 128
Advance Information
© 2007 Microchip Technology Inc.
PIC18F2XK20/4XK20
The fourth pin of PORTE (MCLR/VPP/RE3) is an input
only pin. Its operation is controlled by the MCLRE
10.6 PORTE, TRISE and LATE
Registers
Configuration bit. When selected as
a port pin
Depending on the particular PIC18F2XK20/4XK20
device selected, PORTE is implemented in two
different ways.
(MCLRE = 0), it functions as a digital input only pin; as
such, it does not have TRIS or LAT bits associated with its
operation. Otherwise, it functions as the device’s Master
Clear input. In either configuration, RE3 also functions as
the programming voltage input during programming.
10.6.1
PORTE IN PIC18F4XK20 DEVICES
For PIC18F4XK20 devices, PORTE is a 4-bit wide port.
Three pins (RE0/RD/AN5, RE1/WR/AN6 and RE2/CS/
AN7) are individually configurable as inputs or outputs.
These pins have Schmitt Trigger input buffers. When
selected as an analog input, these pins will read as ‘0’s.
Note:
On a Power-on Reset, RE3 is enabled as
digital input only if Master Clear
functionality is disabled.
a
EXAMPLE 10-5:
INITIALIZING PORTE
The corresponding data direction register is TRISE.
Setting a TRISE bit (= 1) will make the corresponding
PORTE pin an input (i.e., disable the output driver).
Clearing a TRISE bit (= 0) will make the corresponding
PORTE pin an output (i.e., enable the output driver and
put the contents of the output latch on the selected pin).
CLRF
PORTE
LATE
1Fh
; Initialize PORTE by
; clearing output
; data latches
; Alternate method
; to clear output
; data latches
CLRF
MOVLW
ANDWF
MOVLW
; Configure analog pins
TRISE controls the direction of the RE pins, even when
they are being used as analog inputs. The user must
make sure to keep the pins configured as inputs when
using them as analog inputs.
ANSEL,w; for digital only
05h
; Value used to
; initialize data
; direction
MOVWF
TRISE
; Set RE<0> as input
; RE<1> as output
; RE<2> as input
Note:
On a Power-on Reset, RE<2:0> are
configured as analog inputs.
The upper four bits of the TRISE register also control
the operation of the Parallel Slave Port. Their operation
is explained in Register 10-1.
10.6.2
PORTE IN PIC18F2XK20 DEVICES
For PIC18F2XK20 devices, PORTE is only available
when Master Clear functionality is disabled
(MCLR = 0). In these cases, PORTE is a single bit,
input only port comprised of RE3 only. The pin operates
as previously described.
The Data Latch register (LATE) is also memory
mapped. Read-modify-write operations on the LATE
register, read and write the latched output value for
PORTE.
© 2007 Microchip Technology Inc.
Advance Information
DS41303B-page 129
PIC18F2XK20/4XK20
REGISTER 10-1: TRISE: PORTE/PSP CONTROL REGISTER (PIC18F4XK20 DEVICES ONLY)
R-0
IBF
R-0
R/W-0
IBOV
R/W-0
U-0
—
R/W-1
R/W-1
R/W-1
OBF
PSPMODE
TRISE2
TRISE1
TRISE0
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7
bit 6
bit 5
bit 4
IBF: Input Buffer Full Status bit
1= A word has been received and waiting to be read by the CPU
0= No word has been received
OBF: Output Buffer Full Status bit
1= The output buffer still holds a previously written word
0= The output buffer has been read
IBOV: Input Buffer Overflow Detect bit (in Microprocessor mode)
1= A write occurred when a previously input word has not been read (must be cleared by software)
0= No overflow occurred
PSPMODE: Parallel Slave Port Mode Select bit
1= Parallel Slave Port mode
0= General purpose I/O mode
bit 3
bit 2
Unimplemented: Read as ‘0’
TRISE2: RE2 Direction Control bit
1= Input
0= Output
bit 1
bit 0
TRISE1: RE1 Direction Control bit
1= Input
0= Output
TRISE0: RE0 Direction Control bit
1= Input
0= Output
DS41303B-page 130
Advance Information
© 2007 Microchip Technology Inc.
PIC18F2XK20/4XK20
TABLE 10-9: PORTE I/O SUMMARY
TRIS
Setting
I/O
Type
Pin
Function
I/O
Description
RE0/RD/AN5
RE0
0
1
1
1
0
1
1
1
0
1
1
1
—
O
I
DIG
ST
LATE<0> data output; not affected by analog input.
PORTE<0> data input; disabled when analog input enabled.
PSP read enable input (PSP enabled).
RD
I
TTL
ANA
DIG
ST
AN5
RE1
I
A/D input channel 5; default input configuration on POR.
LATE<1> data output; not affected by analog input.
PORTE<1> data input; disabled when analog input enabled.
PSP write enable input (PSP enabled).
RE1/WR/AN6
RE2/CS/AN7
MCLR/VPP/
O
I
WR
AN6
RE2
I
TTL
ANA
DIG
ST
I
A/D input channel 6; default input configuration on POR.
LATE<2> data output; not affected by analog input.
PORTE<2> data input; disabled when analog input enabled.
PSP write enable input (PSP enabled).
O
I
CS
AN7
I
TTL
ANA
ST
I
A/D input channel 7; default input configuration on POR.
MCLR
I
External Master Clear input; enabled when MCLRE Configuration bit is
set.
(1,2)
RE3
VPP
—
I
I
ANA
ST
High-voltage detection; used for ICSP™ mode entry detection. Always
available, regardless of pin mode.
(2)
RE3
—
PORTE<3> data input; enabled when MCLRE Configuration bit is
clear.
Legend:
DIG = Digital level output; TTL = TTL input buffer; ST = Schmitt Trigger input buffer; ANA = Analog level input/output;
x= Don’t care (TRIS bit does not affect port direction or is overridden for this option).
Note 1: RE3 is available on both PIC18F2XK20 and PIC18F4XK20 devices. All other PORTE pins are only implemented on
PIC18F4XK20 devices.
2: RE3 does not have a corresponding TRIS bit to control data direction.
TABLE 10-10: SUMMARY OF REGISTERS ASSOCIATED WITH PORTE
Reset
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Values
on page
PORTE
LATE(2)
TRISE
—
—
—
—
—
—
—
—
RE3(1,2)
—
RE2
RE1
RE0
60
60
60
61
60
LATE Data Output Register
IBF
—
OBF
—
IBOV
—
PSPMODE
SLRE
ANS4
—
TRISE2
SLRC
ANS2
TRISE1
SLRB
TRISE0
SLRA
SLRCON
ANSEL
SLRD
ANS3
ANS7
ANS6
ANS5
ANS1
ANS0
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PORTE.
Note 1: Implemented only when Master Clear functionality is disabled (MCLRE Configuration bit = 0).
2: RE3 is the only PORTE bit implemented on both PIC18F2XK20 and PIC18F2XK20 devices. All other bits
are implemented only when PORTE is implemented (i.e., PIC18F4XK20 devices).
© 2007 Microchip Technology Inc.
Advance Information
DS41303B-page 131
PIC18F2XK20/4XK20
buffer and cause all reads of that pin to return ‘0’ while
allowing analog functions of that pin to operate
correctly.
10.7 Port Analog Control
Some port pins are multiplexed with analog functions
such as the Analog-to-Digital Converter and compara-
tors. When these I/O pins are to be used as analog
inputs it is necessary to disable the digital input buffer
to avoid excessive current caused by improper biasing
of the digital input. Individual control of the digital input
buffers on pins which share analog functions is pro-
vided by the ANSEL and ANSELH registers. Setting an
ANSx bit high will disable the associated digital input
The state of the ANSx bits has no affect on digital
output functions. A pin with the associated TRISx bit
clear and ANSx bit set will still operate as a digital
output but the input mode will be analog. This can
cause unexpected behavior when performing read-
modify-write operations on the affected port.
REGISTER 10-2: ANSEL: ANALOG SELECT REGISTER 1
R/W-1
ANS7(1)
R/W-1
ANS6(1)
R/W-1
ANS5(1)
R/W-1
ANS4
R/W-1
ANS3
R/W-1
ANS2
R/W-1
ANS1
R/W-1
ANS0
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
ANS7: RE2 Analog Select Control bit(1)
1= Digital input buffer of RE2 is disabled
0= Digital input buffer of RE2 is enabled
ANS6: RE1 Analog Select Control bit(1)
1= Digital input buffer of RE1 is disabled
0= Digital input buffer of RE1 is enabled
ANS5: RE0 Analog Select Control bit(1)
1= Digital input buffer of RE0 is disabled
0= Digital input buffer of RE0 is enabled
ANS4: RA5 Analog Select Control bit
1= Digital input buffer of RA5 is disabled
0= Digital input buffer of RA5 is enabled
ANS3: RA3 Analog Select Control bit
1= Digital input buffer of RA3 is disabled
0= Digital input buffer of RA3 is enabled
ANS2: RA2 Analog Select Control bit
1= Digital input buffer of RA2 is disabled
0= Digital input buffer of RA2 is enabled
ANS1: RA1 Analog Select Control bit
1= Digital input buffer of RA1 is disabled
0= Digital input buffer of RA1 is enabled
ANS0: RA0 Analog Select Control bit
1= Digital input buffer of RA0 is disabled
0= Digital input buffer of RA0 is enabled
Note 1: These bits are not implemented on PIC18F2XK20 devices.
DS41303B-page 132
Advance Information
© 2007 Microchip Technology Inc.
PIC18F2XK20/4XK20
REGISTER 10-3: ANSELH: ANALOG SELECT REGISTER 2
U-0
—
U-0
—
U-0
—
R/W-1(1)
ANS12
R/W-1(1)
ANS11
R/W-1(1)
ANS10
R/W-1(1)
ANS9
R/W-1(1)
ANS8
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7-5
bit 4
Unimplemented: Read as ‘0’
ANS12: RB0 Analog Select Control bit
1= Digital input buffer of RB0 is disabled
0= Digital input buffer of RB0 is enabled
bit 3
bit 2
bit 1
bit 0
ANS11: RB4 Analog Select Control bit
1= Digital input buffer of RB4 is disabled
0= Digital input buffer of RB4 is enabled
ANS10: RB1 Analog Select Control bit
1= Digital input buffer of RB1 is disabled
0= Digital input buffer of RB1 is enabled
ANS9: RB3 Analog Select Control bit
1= Digital input buffer of RB3 is disabled
0= Digital input buffer of RB3 is enabled
ANS8: RB2 Analog Select Control bit
1= Digital input buffer of RB2 is disabled
0= Digital input buffer of RB2 is enabled
Note 1: Default state is determined by the PBADEN bit of CONFIG3H. The default state is ‘0’ When
PBADEN = ‘0’.
© 2007 Microchip Technology Inc.
Advance Information
DS41303B-page 133
PIC18F2XK20/4XK20
10.8 Port Slew Rate Control
The output slew rate of each port is programmable to
select either the standard transition rate or a reduced
transition rate of 0.1 times the standard to minimize
EMI. The reduced transition time is the default slew
rate for all ports.
REGISTER 10-4: SLRCON: SLEW RATE CONTROL REGISTER
U-0
—
U-0
—
U-0
—
R/W-1
SLRE(1)
R/W-1
SLRD(1)
R/W-1
SLRC
R/W-1
SLRB
R/W-1
SLRA
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7-5
bit 4
Unimplemented: Read as ‘0’
SLRE: PORTE Slew Rate Control bit(1)
1= All outputs on PORTE slew at 0.1 times the standard rate
0= All outputs on PORTE slew at the standard rate
bit 3
bit 2
bit 1
bit 0
SLRD: PORTD Slew Rate Control bit(1)
1= All outputs on PORTD slew at 0.1 times the standard rate
0= All outputs on PORTD slew at the standard rate
SLRC: PORTC Slew Rate Control bit
1= All outputs on PORTC slew at 0.1 times the standard rate
0= All outputs on PORTC slew at the standard rate
SLRB: PORTB Slew Rate Control bit
1= All outputs on PORTB slew at 0.1 times the standard rate
0= All outputs on PORTB slew at the standard rate
SLRA: PORTA Slew Rate Control bit
1= All outputs on PORTA slew at 0.1 times the standard rate(2)
0= All outputs on PORTA slew at the standard rate
Note 1: These bits are not implemented on PIC18F2XK20 devices.
2: The slew rate of RA6 defaults to standard rate when the pin is used as CLKOUT.
DS41303B-page 134
Advance Information
© 2007 Microchip Technology Inc.
PIC18F2XK20/4XK20
The timing for the control signals in Write and Read
modes is shown in Figure 10-3 and Figure 10-4,
respectively.
10.9 Parallel Slave Port
Note:
The Parallel Slave Port is only available on
PIC18F4XK20 devices.
FIGURE 10-2:
PORTD AND PORTE
BLOCK DIAGRAM
(PARALLEL SLAVE PORT)
In addition to its function as a general I/O port, PORTD
can also operate as an 8-bit wide Parallel Slave Port
(PSP) or microprocessor port. PSP operation is
controlled by the 4 upper bits of the TRISE register
(Register 10-1). Setting control bit, PSPMODE
(TRISE<4>), enables PSP operation as long as the
enhanced CCP module is not operating in dual output
or quad output PWM mode. In Slave mode, the port is
asynchronously readable and writable by the external
world.
One bit of PORTD
Data Bus
D
Q
RDx pin
WR LATD
or
WR PORTD
CK
Data Latch
TTL
The PSP can directly interface to an 8-bit
microprocessor data bus. The external microprocessor
can read or write the PORTD latch as an 8-bit latch.
Setting the control bit, PSPMODE, enables the PORTE
I/O pins to become control inputs for the microprocessor
port. When set, port pin RE0 is the RD input, RE1 is the
WR input and RE2 is the CS (Chip Select) input. For this
functionality, the corresponding data direction bits of the
TRISE register (TRISE<2:0>) must be configured as
inputs (set) and the ANSEL<7:5> bits must be cleared.
Q
D
RD PORTD
RD LATD
EN
Set Interrupt Flag
PSPIF (PIR1<7>)
A write to the PSP occurs when both the CS and WR
lines are first detected low and ends when either are
detected high. The PSPIF and IBF flag bits are both set
when the write ends.
PORTE Pins
Read
RD
A read from the PSP occurs when both the CS and RD
lines are first detected low. The data in PORTD is read
out and the OBF bit is clear. If the user writes new data
to PORTD to set OBF, the data is immediately read out;
however, the OBF bit is not set.
TTL
Chip Select
TTL
CS
Write
WR
TTL
When either the CS or RD lines are detected high, the
PORTD pins return to the input state and the PSPIF bit
is set. User applications should wait for PSPIF to be set
before servicing the PSP; when this happens, the IBF
and OBF bits can be polled and the appropriate action
taken.
Note:
I/O pins have diode protection to VDD and VSS.
© 2007 Microchip Technology Inc.
Advance Information
DS41303B-page 135
PIC18F2XK20/4XK20
FIGURE 10-3:
PARALLEL SLAVE PORT WRITE WAVEFORMS
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
CS
WR
RD
PORTD<7:0>
IBF
OBF
PSPIF
FIGURE 10-4:
PARALLEL SLAVE PORT READ WAVEFORMS
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
CS
WR
RD
PORTD<7:0>
IBF
OBF
PSPIF
TABLE 10-11: REGISTERS ASSOCIATED WITH PARALLEL SLAVE PORT
Reset
Values
on page
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PORTD
LATD
RD7
RD6
RD5
RD4
RD3
RD2
RD1
RD0
RE0
60
60
60
60
60
60
61
57
60
60
60
60
PORTD Data Latch Register (Read and Write to Data Latch)
PORTD Data Direction Control Register
TRISD
PORTE
LATE
—
—
—
—
—
—
—
—
RE3
—
RE2
RE1
LATE Data Output bits
TRISE
SLRCON
INTCON
PIR1
IBF
—
OBF
—
IBOV
—
PSPMODE
SLRE
INT0IE
TXIF
—
TRISE2
SLRC
TRISE1
SLRB
TRISE0
SLRA
SLRD
RBIE
SSPIF
SSPIE
SSPIP
ANS3
GIE/GIEH PEIE/GIEL TMR0IF
TMR0IF
CCP1IF
INT0IF
TMR2IF
RBIF
PSPIF
PSPIE
PSPIP
ANS7
ADIF
ADIE
ADIP
ANS6
RCIF
RCIE
RCIP
ANS5
TMR1IF
PIE1
TXIE
CCP1IE TMR2IE TMR1IE
CCP1IP TMR2IP TMR1IP
IPR1
TXIP
ANSEL
ANS4
ANS2
ANS1
ANS0
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the Parallel Slave Port.
DS41303B-page 136
Advance Information
© 2007 Microchip Technology Inc.
PIC18F2XK20/4XK20
The T0CON register (Register 11-1) controls all
aspects of the module’s operation, including the
prescale selection. It is both readable and writable.
11.0 TIMER0 MODULE
The Timer0 module incorporates the following features:
• Software selectable operation as a timer or
counter in both 8-bit or 16-bit modes
A simplified block diagram of the Timer0 module in 8-bit
mode is shown in Figure 11-1. Figure 11-2 shows a
simplified block diagram of the Timer0 module in 16-bit
mode.
• Readable and writable registers
• Dedicated 8-bit, software programmable
prescaler
• Selectable clock source (internal or external)
• Edge select for external clock
• Interrupt-on-overflow
REGISTER 11-1: T0CON: TIMER0 CONTROL REGISTER
R/W-1
R/W-1
R/W-1
T0CS
R/W-1
T0SE
R/W-1
PSA
R/W-1
T0PS2
R/W-1
T0PS1
R/W-1
T0PS0
TMR0ON
T08BIT
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2-0
TMR0ON: Timer0 On/Off Control bit
1= Enables Timer0
0= Stops Timer0
T08BIT: Timer0 8-bit/16-bit Control bit
1= Timer0 is configured as an 8-bit timer/counter
0= Timer0 is configured as a 16-bit timer/counter
T0CS: Timer0 Clock Source Select bit
1= Transition on T0CKI pin
0= Internal instruction cycle clock (CLKOUT)
T0SE: Timer0 Source Edge Select bit
1= Increment on high-to-low transition on T0CKI pin
0= Increment on low-to-high transition on T0CKI pin
PSA: Timer0 Prescaler Assignment bit
1= TImer0 prescaler is NOT assigned. Timer0 clock input bypasses prescaler.
0= Timer0 prescaler is assigned. Timer0 clock input comes from prescaler output.
T0PS<2:0>: Timer0 Prescaler Select bits
111= 1:256 prescale value
110= 1:128 prescale value
101= 1:64 prescale value
100= 1:32 prescale value
011= 1:16 prescale value
010= 1:8 prescale value
001= 1:4 prescale value
000= 1:2 prescale value
© 2007 Microchip Technology Inc.
Advance Information
DS41303B-page 137
PIC18F2XK20/4XK20
11.1 Timer0 Operation
11.2 Timer0 Reads and Writes in
16-Bit Mode
Timer0 can operate as either a timer or a counter; the
mode is selected with the T0CS bit of the T0CON
register. In Timer mode (T0CS = 0), the module
increments on every clock by default unless a different
prescaler value is selected (see Section 11.3
“Prescaler”). Timer0 incrementing is inhibited for two
instruction cycles following a TMR0 register write. The
user can work around this by adjusting the value written
to the TMR0 register to compensate for the anticipated
missing increments.
TMR0H is not the actual high byte of Timer0 in 16-bit
mode; it is actually a buffered version of the real high
byte of Timer0 which is neither directly readable nor
writable (refer to Figure 11-2). TMR0H is updated with
the contents of the high byte of Timer0 during a read of
TMR0L. This provides the ability to read all 16 bits of
Timer0 without the need to verify that the read of the
high and low byte were valid. Invalid reads could
otherwise occur due to a rollover between successive
reads of the high and low byte.
The Counter mode is selected by setting the T0CS bit
(= 1). In this mode, Timer0 increments either on every
rising or falling edge of pin RA4/T0CKI. The increment-
ing edge is determined by the Timer0 Source Edge
Select bit, T0SE of the T0CON register; clearing this bit
selects the rising edge. Restrictions on the external
clock input are discussed below.
Similarly, a write to the high byte of Timer0 must also
take place through the TMR0H Buffer register. Writing
to TMR0H does not directly affect Timer0. Instead, the
high byte of Timer0 is updated with the contents of
TMR0H when a write occurs to TMR0L. This allows all
16 bits of Timer0 to be updated at once.
An external clock source can be used to drive Timer0;
however, it must meet certain requirements (see
Table 26-10) to ensure that the external clock can be
synchronized with the internal phase clock (TOSC).
There is a delay between synchronization and the
onset of incrementing the timer/counter.
FIGURE 11-1:
TIMER0 BLOCK DIAGRAM (8-BIT MODE)
FOSC/4
0
1
0
1
Set
TMR0IF
on Overflow
Sync with
Internal
Clocks
TMR0L
8
Programmable
Prescaler
T0CKI pin
(2 TCY Delay)
T0SE
T0CS
3
T0PS<2:0>
PSA
8
Internal Data Bus
Note: Upon Reset, Timer0 is enabled in 8-bit mode with clock input from T0CKI max. prescale.
DS41303B-page 138
Advance Information
© 2007 Microchip Technology Inc.
PIC18F2XK20/4XK20
FIGURE 11-2:
TIMER0 BLOCK DIAGRAM (16-BIT MODE)
FOSC/4
0
1
0
1
Sync with
Internal
Clocks
Set
TMR0IF
on Overflow
TMR0
High Byte
TMR0L
Programmable
Prescaler
T0CKI pin
8
(2 TCY Delay)
T0SE
T0CS
3
Read TMR0L
Write TMR0L
T0PS<2:0>
PSA
8
8
TMR0H
8
8
Internal Data Bus
Note: Upon Reset, Timer0 is enabled in 8-bit mode with clock input from T0CKI max. prescale.
11.3.1
SWITCHING PRESCALER
ASSIGNMENT
11.3 Prescaler
An 8-bit counter is available as a prescaler for the Timer0
module. The prescaler is not directly readable or writable;
its value is set by the PSA and T0PS<2:0> bits of the
T0CON register which determine the prescaler
assignment and prescale ratio.
The prescaler assignment is fully under software
control and can be changed “on-the-fly” during program
execution.
11.4 Timer0 Interrupt
Clearing the PSA bit assigns the prescaler to the
Timer0 module. When the prescaler is assigned,
prescale values from 1:2 through 1:256 in integer
power-of-2 increments are selectable.
The TMR0 interrupt is generated when the TMR0 reg-
ister overflows from FFh to 00h in 8-bit mode, or from
FFFFh to 0000h in 16-bit mode. This overflow sets the
TMR0IF flag bit. The interrupt can be masked by clear-
ing the TMR0IE bit of the INTCON register. Before
re-enabling the interrupt, the TMR0IF bit must be
cleared by software in the Interrupt Service Routine.
When assigned to the Timer0 module, all instructions
writing to the TMR0 register (e.g., CLRF TMR0, MOVWF
TMR0, BSF TMR0, etc.) clear the prescaler count.
Note:
Writing to TMR0 when the prescaler is
assigned to Timer0 will clear the prescaler
count but will not change the prescaler
assignment.
Since Timer0 is shut down in Sleep mode, the TMR0
interrupt cannot awaken the processor from Sleep.
TABLE 11-1: REGISTERS ASSOCIATED WITH TIMER0
Reset
Values
on page
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
TMR0L
Timer0 Register, Low Byte
Timer0 Register, High Byte
58
58
57
58
60
TMR0H
INTCON
T0CON
TRISA
GIE/GIEH PEIE/GIEL TMR0IE
INT0IE
T0SE
RA4
RBIE
PSA
RA3
TMR0IF
T0PS2
RA2
INT0IF
T0PS1
RA1
RBIF
T0PS0
RA0
TMR0ON
RA7(1)
T08BIT
RA6(1)
T0CS
RA5
Legend: Shaded cells are not used by Timer0.
Note 1: PORTA<7:6> and their direction bits are individually configured as port pins based on various primary
oscillator modes. When disabled, these bits read as ‘0’.
© 2007 Microchip Technology Inc.
Advance Information
DS41303B-page 139
PIC18F2XK20/4XK20
NOTES:
DS41303B-page 140
Advance Information
© 2007 Microchip Technology Inc.
PIC18F2XK20/4XK20
A simplified block diagram of the Timer1 module is
shown in Figure 12-1. A block diagram of the module’s
operation in Read/Write mode is shown in Figure 12-2.
12.0 TIMER1 MODULE
The Timer1 timer/counter module incorporates the
following features:
The module incorporates its own low-power oscillator
to provide an additional clocking option. The Timer1
oscillator can also be used as a low-power clock source
for the microcontroller in power-managed operation.
• Software selectable operation as a 16-bit timer or
counter
• Readable and writable 8-bit registers (TMR1H
and TMR1L)
Timer1 can also be used to provide Real-Time Clock
(RTC) functionality to applications with only a minimal
addition of external components and code overhead.
• Selectable internal or external clock source and
Timer1 oscillator options
• Interrupt-on-overflow
Timer1 is controlled through the T1CON Control
register (Register 12-1). It also contains the Timer1
Oscillator Enable bit (T1OSCEN). Timer1 can be
enabled or disabled by setting or clearing control bit,
TMR1ON of the T1CON register.
• Reset on CCP Special Event Trigger
• Device clock status flag (T1RUN)
REGISTER 12-1: T1CON: TIMER1 CONTROL REGISTER
R/W-0
RD16
R-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
T1RUN
T1CKPS1
T1CKPS0
T1OSCEN
T1SYNC
TMR1CS
TMR1ON
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7
RD16: 16-bit Read/Write Mode Enable bit
1= Enables register read/write of TImer1 in one 16-bit operation
0= Enables register read/write of Timer1 in two 8-bit operations
bit 6
T1RUN: Timer1 System Clock Status bit
1= Main system clock is derived from Timer1 oscillator
0= Main system clock is derived from another source
bit 5-4
T1CKPS<1:0>: Timer1 Input Clock Prescale Select bits
11= 1:8 Prescale value
10= 1:4 Prescale value
01= 1:2 Prescale value
00= 1:1 Prescale value
bit 3
bit 2
T1OSCEN: Timer1 Oscillator Enable bit
1= Timer1 oscillator is enabled
0= Timer1 oscillator is shut off
The oscillator inverter and feedback resistor are turned off to eliminate power drain.
T1SYNC: Timer1 External Clock Input Synchronization Select bit
When TMR1CS = 1:
1= Do not synchronize external clock input
0= Synchronize external clock input
When TMR1CS = 0:
This bit is ignored. Timer1 uses the internal clock when TMR1CS = 0.
bit 1
bit 0
TMR1CS: Timer1 Clock Source Select bit
1= External clock from pin RC0/T1OSO/T13CKI (on the rising edge)
0= Internal clock (FOSC/4)
TMR1ON: Timer1 On bit
1= Enables Timer1
0= Stops Timer1
© 2007 Microchip Technology Inc.
Advance Information
DS41303B-page 141
PIC18F2XK20/4XK20
instruction cycle (FOSC/4). When the bit is set, Timer1
increments on every rising edge of either the Timer1
external clock input or the Timer1 oscillator, if enabled.
12.1 Timer1 Operation
Timer1 can operate in one of the following modes:
• Timer
When the Timer1 oscillator is enabled, the digital
circuitry associated with the RC1/T1OSI and
RC0/T1OSO/T13CKI pins is disabled. This means the
values of TRISC<1:0> are ignored and the pins are
read as ‘0’.
• Synchronous Counter
• Asynchronous Counter
The operating mode is determined by the clock select
bit, TMR1CS of the T1CON register. When TMR1CS is
cleared (= 0), Timer1 increments on every internal
FIGURE 12-1:
TIMER1 BLOCK DIAGRAM
Timer1 Oscillator
Timer1 Clock Input
1
0
On/Off
T1OSO/T13CKI
T1OSI
1
Synchronize
Detect
Prescaler
1, 2, 4, 8
FOSC/4
Internal
Clock
0
2
Sleep Input
T1OSCEN(1)
T1CKPS<1:0>
T1SYNC
Timer1
On/Off
TMR1CS
TMR1ON
Set
TMR1
High Byte
Clear TMR1
(CCP Special Event Trigger)
TMR1L
TMR1IF
on Overflow
Note 1: When enable bit, T1OSCEN, is cleared, the inverter and feedback resistor are turned off to eliminate power drain.
FIGURE 12-2:
TIMER1 BLOCK DIAGRAM (16-BIT READ/WRITE MODE)
Timer1 Oscillator
Timer1 Clock Input
1
0
T1OSO/T13CKI
T1OSI
1
0
Synchronize
Detect
Prescaler
1, 2, 4, 8
FOSC/4
Internal
Clock
2
Sleep Input
T1OSCEN(1)
T1CKPS<1:0>
T1SYNC
Timer1
On/Off
TMR1CS
TMR1ON
Set
TMR1
High Byte
Clear TMR1
(CCP Special Event Trigger)
TMR1L
TMR1IF
on Overflow
8
Read TMR1L
Write TMR1L
8
8
TMR1H
8
8
Internal Data Bus
Note 1: When enable bit, T1OSCEN, is cleared, the inverter and feedback resistor are turned off to eliminate power drain.
DS41303B-page 142
Advance Information
© 2007 Microchip Technology Inc.
PIC18F2XK20/4XK20
TABLE 12-1: CAPACITOR SELECTION FOR
THE TIMER OSCILLATOR
12.2 Timer1 16-Bit Read/Write Mode
Timer1 can be configured for 16-bit reads and writes
(see Figure 12-2). When the RD16 control bit of the
T1CON register is set, the address for TMR1H is
mapped to a buffer register for the high byte of Timer1.
A read from TMR1L will load the contents of the high
byte of Timer1 into the Timer1 high byte buffer. This
provides the user with the ability to accurately read all
16 bits of Timer1 without the need to determine
whether a read of the high byte, followed by a read of
the low byte, has become invalid due to a rollover or
carry between reads.
Osc Type
Freq
C1
C2
LP
32 kHz
27 pF(1)
27 pF(1)
Note 1: Microchip suggests these values only as a
starting point in validating the oscillator
circuit.
2: Higher capacitance increases the stability
of the oscillator but also increases the
start-up time.
3: Since each resonator/crystal has its own
characteristics, the user should consult
the resonator/crystal manufacturer for
appropriate values of external
Writing to TMR1H does not directly affect Timer1.
Instead, the high byte of Timer1 is updated with the
contents of TMR1H when a write occurs to TMR1L.
This allows all 16 bits of Timer1 to be updated at once.
components.
The high byte of Timer1 is not directly readable or
writable in this mode. All reads and writes must take
place through the Timer1 High Byte Buffer register.
Writes to TMR1H do not clear the Timer1 prescaler.
The prescaler is only cleared on writes to TMR1L.
4: Capacitor values are for design guidance
only.
12.3.1
USING TIMER1 AS A
CLOCK SOURCE
The Timer1 oscillator is also available as a clock source
in power-managed modes. By setting the clock select
bits, SCS<1:0> of the OSCCON register, to ‘01’, the
device switches to SEC_RUN mode; both the CPU and
peripherals are clocked from the Timer1 oscillator. If the
IDLEN bit of the OSCCON register is cleared and a
SLEEP instruction is executed, the device enters
SEC_IDLE mode. Additional details are available in
Section 3.0 “Power-Managed Modes”.
12.3 Timer1 Oscillator
An on-chip crystal oscillator circuit is incorporated
between pins T1OSI (input) and T1OSO (amplifier
output). It is enabled by setting the Timer1 Oscillator
Enable bit, T1OSCEN of the T1CON register. The
oscillator is a low-power circuit rated for 32 kHz crystals.
It will continue to run during all power-managed modes.
The circuit for a typical LP oscillator is shown in
Figure 12-3. Table 12-1 shows the capacitor selection
for the Timer1 oscillator.
Whenever the Timer1 oscillator is providing the clock
source, the Timer1 system clock status flag, T1RUN of
the T1CON register, is set. This can be used to deter-
mine the controller’s current clocking mode. It can also
indicate which clock source is currently being used by
the Fail-Safe Clock Monitor. If the Clock Monitor is
enabled and the Timer1 oscillator fails while providing
the clock, polling the T1RUN bit will indicate whether
the clock is being provided by the Timer1 oscillator or
another source.
The user must provide a software time delay to ensure
proper start-up of the Timer1 oscillator.
FIGURE 12-3:
EXTERNAL
COMPONENTS FOR THE
TIMER1 LP OSCILLATOR
C1
27 pF
PIC® MCU
T1OSI
XTAL
32.768 kHz
T1OSO
C2
27 pF
Note:
See the Notes with Table 12-1 for additional
information about capacitor selection.
© 2007 Microchip Technology Inc.
Advance Information
DS41303B-page 143
PIC18F2XK20/4XK20
12.3.2
LOW-POWER TIMER1 OPTION
12.4 Timer1 Interrupt
The Timer1 oscillator can operate at two distinct levels
of power consumption based on device configuration.
When the LPT1OSC Configuration bit of the
CONFIG3H register is set, the Timer1 oscillator oper-
ates in a low-power mode. When LPT1OSC is not set,
Timer1 operates at a higher power level. Power con-
sumption for a particular mode is relatively constant,
regardless of the device’s operating mode. The default
Timer1 configuration is the higher power mode.
The TMR1 register pair (TMR1H:TMR1L) increments
from 0000h to FFFFh and rolls over to 0000h. The
Timer1 interrupt, if enabled, is generated on overflow,
which is latched in the TMR1IF interrupt flag bit of the
PIR1 register. This interrupt can be enabled or disabled
by setting or clearing the TMR1IE Interrupt Enable bit
of the PIE1 register.
12.5 Resetting Timer1 Using the CCP
Special Event Trigger
As the low-power Timer1 mode tends to be more
sensitive to interference, high noise environments may
cause some oscillator instability. The low-power option is,
therefore, best suited for low noise applications where
power conservation is an important design consideration.
If either of the CCP modules is configured to use Timer1
and generate a Special Event Trigger in Compare mode
(CCP1M<3:0> or CCP2M<3:0> = 1011), this signal will
reset Timer1. The trigger from CCP2 will also start an
A/D conversion if the A/D module is enabled (see
Section 15.3.4 “Special Event Trigger” for more
information).
12.3.3
TIMER1 OSCILLATOR LAYOUT
CONSIDERATIONS
The Timer1 oscillator circuit draws very little power
during operation. Due to the low-power nature of the
oscillator, it may also be sensitive to rapidly changing
signals in close proximity.
The module must be configured as either a timer or a
synchronous counter to take advantage of this feature.
When used this way, the CCPRH:CCPRL register pair
effectively becomes a period register for Timer1.
The oscillator circuit, shown in Figure 12-3, should be
located as close as possible to the microcontroller.
There should be no circuits passing within the oscillator
circuit boundaries other than VSS or VDD.
If Timer1 is running in Asynchronous Counter mode,
this Reset operation may not work.
In the event that a write to Timer1 coincides with a
special Event Trigger, the write operation will take
precedence.
If a high-speed circuit must be located near the oscilla-
tor (such as the CCP1 pin in Output Compare or PWM
mode, or the primary oscillator using the OSC2 pin), a
grounded guard ring around the oscillator circuit, as
shown in Figure 12-4, may be helpful when used on a
single-sided PCB or in addition to a ground plane.
Note:
The Special Event Triggers from the CCP2
module will not set the TMR1IF interrupt
flag bit of the PIR1 register.
FIGURE 12-4:
OSCILLATOR CIRCUIT
WITH GROUNDED
GUARD RING
VDD
VSS
OSC1
OSC2
RC0
RC1
RC2
Note: Not drawn to scale.
DS41303B-page 144
Advance Information
© 2007 Microchip Technology Inc.
PIC18F2XK20/4XK20
Since the register pair is 16 bits wide, a 32.768 kHz
clock source will take 2 seconds to count up to over-
flow. To force the overflow at the required one-second
intervals, it is necessary to preload it; the simplest
method is to set the MSb of TMR1H with a BSFinstruc-
tion. Note that the TMR1L register is never preloaded
or altered; doing so may introduce cumulative error
over many cycles.
12.6 Using Timer1 as a Real-Time Clock
Adding an external LP oscillator to Timer1 (such as the
one described in Section 12.3 “Timer1 Oscillator”
above) gives users the option to include RTC function-
ality to their applications. This is accomplished with an
inexpensive watch crystal to provide an accurate time
base and several lines of application code to calculate
the time. When operating in Sleep mode and using a
battery or supercapacitor as a power source, it can
completely eliminate the need for a separate RTC
device and battery backup.
For this method to be accurate, Timer1 must operate in
Asynchronous mode and the Timer1 overflow interrupt
must be enabled (PIE1<0> = 1), as shown in the
routine, RTCinit. The Timer1 oscillator must also be
enabled and running at all times.
The application code routine, RTCisr, shown in
Example 12-1, demonstrates a simple method to
increment a counter at one-second intervals using an
Interrupt Service Routine. Incrementing the TMR1
register pair to overflow triggers the interrupt and calls
the routine, which increments the seconds counter by
one; additional counters for minutes and hours are
incremented on overflows of the less significant
counters.
EXAMPLE 12-1:
IMPLEMENTING A REAL-TIME CLOCK USING A TIMER1 INTERRUPT SERVICE
RTCinit
MOVLW
MOVWF
CLRF
80h
TMR1H
TMR1L
; Preload TMR1 register pair
; for 1 second overflow
MOVLW
MOVWF
CLRF
b’00001111’
T1CON
secs
; Configure for external clock,
; Asynchronous operation, external oscillator
; Initialize timekeeping registers
;
CLRF
mins
MOVLW
MOVWF
BSF
.12
hours
PIE1, TMR1IE
; Enable Timer1 interrupt
RETURN
RTCisr
BSF
BCF
INCF
MOVLW
CPFSGT
RETURN
CLRF
TMR1H, 7
PIR1, TMR1IF
secs, F
.59
; Preload for 1 sec overflow
; Clear interrupt flag
; Increment seconds
; 60 seconds elapsed?
secs
; No, done
secs
mins, F
.59
; Clear seconds
; Increment minutes
; 60 minutes elapsed?
INCF
MOVLW
CPFSGT
RETURN
CLRF
mins
; No, done
mins
hours, F
.23
; clear minutes
; Increment hours
; 24 hours elapsed?
INCF
MOVLW
CPFSGT
RETURN
CLRF
hours
; No, done
; Reset hours
; Done
hours
RETURN
© 2007 Microchip Technology Inc.
Advance Information
DS41303B-page 145
PIC18F2XK20/4XK20
TABLE 12-2: REGISTERS ASSOCIATED WITH TIMER1 AS A TIMER/COUNTER
Reset
Values
on page
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
INTCON
PIR1
GIE/GIEH PEIE/GIEL TMR0IE
INT0IE
TXIF
RBIE
SSPIF
SSPIE
SSPIP
TMR0IF
CCP1IF
CCP1IE
CCP1IP
INT0IF
TMR2IF
TMR2IE
TMR2IP
RBIF
57
60
60
60
58
58
58
PSPIF(1)
PSPIE(1)
PSPIP(1)
ADIF
ADIE
ADIP
RCIF
RCIE
RCIP
TMR1IF
TMR1IE
TMR1IP
PIE1
TXIE
TXIP
IPR1
TMR1L
TMR1H
T1CON
Timer1 Register, Low Byte
Timer1 Register, High Byte
RD16
T1RUN T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON
Legend: Shaded cells are not used by the Timer1 module.
Note 1: These bits are unimplemented on 28-pin devices; always maintain these bits clear.
DS41303B-page 146
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© 2007 Microchip Technology Inc.
PIC18F2XK20/4XK20
13.1 Timer2 Operation
13.0 TIMER2 MODULE
In normal operation, TMR2 is incremented from 00h on
each clock (FOSC/4). A 4-bit counter/prescaler on the
clock input gives direct input, divide-by-4 and
divide-by-16 prescale options; these are selected by
the prescaler control bits, T2CKPS<1:0> of the T2CON
register. The value of TMR2 is compared to that of the
period register, PR2, on each clock cycle. When the
two values match, the comparator generates a match
signal as the timer output. This signal also resets the
value of TMR2 to 00h on the next cycle and drives the
output counter/postscaler (see Section 13.2 “Timer2
Interrupt”).
The Timer2 module timer incorporates the following
features:
• 8-bit timer and period registers (TMR2 and PR2,
respectively)
• Readable and writable (both registers)
• Software programmable prescaler (1:1, 1:4 and
1:16)
• Software programmable postscaler (1:1 through
1:16)
• Interrupt on TMR2-to-PR2 match
• Optional use as the shift clock for the MSSP
module
The TMR2 and PR2 registers are both directly readable
and writable. The TMR2 register is cleared on any
device Reset, whereas the PR2 register initializes to
FFh. Both the prescaler and postscaler counters are
cleared on the following events:
The module is controlled through the T2CON register
(Register 13-1), which enables or disables the timer
and configures the prescaler and postscaler. Timer2
can be shut off by clearing control bit, TMR2ON of the
T2CON register, to minimize power consumption.
• a write to the TMR2 register
• a write to the T2CON register
A simplified block diagram of the module is shown in
Figure 13-1.
• any device Reset (Power-on Reset, MCLR Reset,
Watchdog Timer Reset or Brown-out Reset)
TMR2 is not cleared when T2CON is written.
REGISTER 13-1: T2CON: TIMER2 CONTROL REGISTER
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
T2OUTPS3 T2OUTPS2 T2OUTPS1 T2OUTPS0
TMR2ON
T2CKPS1
T2CKPS0
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7
Unimplemented: Read as ‘0’
bit 6-3
T2OUTPS<3:0>: Timer2 Output Postscale Select bits
0000= 1:1 Postscale
0001= 1:2 Postscale
•
•
•
1111= 1:16 Postscale
bit 2
TMR2ON: Timer2 On bit
1= Timer2 is on
0= Timer2 is off
bit 1-0
T2CKPS<1:0>: Timer2 Clock Prescale Select bits
00= Prescaler is 1
01= Prescaler is 4
1x= Prescaler is 16
© 2007 Microchip Technology Inc.
Advance Information
DS41303B-page 147
PIC18F2XK20/4XK20
13.2 Timer2 Interrupt
13.3 Timer2 Output
Timer2 can also generate an optional device interrupt.
The Timer2 output signal (TMR2-to-PR2 match) pro-
vides the input for the 4-bit output counter/postscaler.
This counter generates the TMR2 match interrupt flag
which is latched in TMR2IF of the PIR1 register. The
interrupt is enabled by setting the TMR2 Match Inter-
rupt Enable bit, TMR2IE of the PIE1 register.
The unscaled output of TMR2 is available primarily to
the CCP modules, where it is used as a time base for
operations in PWM mode.
Timer2 can be optionally used as the shift clock source
for the MSSP module operating in SPI mode. Addi-
tional information is provided in Section 17.0 “Master
Synchronous Serial Port (MSSP) Module”.
A range of 16 postscale options (from 1:1 through 1:16
inclusive) can be selected with the postscaler control
bits, T2OUTPS<3:0> of the T2CON register.
FIGURE 13-1:
TIMER2 BLOCK DIAGRAM
4
1:1 to 1:16
Set TMR2IF
Postscaler
T2OUTPS<3:0>
T2CKPS<1:0>
2
TMR2 Output
(to PWM or MSSP)
TMR2/PR2
Match
Reset
1:1, 1:4, 1:16
Prescaler
PR2
FOSC/4
Comparator
TMR2
8
8
8
Internal Data Bus
TABLE 13-1: REGISTERS ASSOCIATED WITH TIMER2 AS A TIMER/COUNTER
Reset
Values
on page
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
INTCON GIE/GIEH PEIE/GIEL TMR0IE
INT0IE
TXIF
RBIE
SSPIF
SSPIE
SSPIP
TMR0IF
CCP1IF
CCP1IE
CCP1IP
INT0IF
TMR2IF
TMR2IE
TMR2IP
RBIF
57
60
60
60
58
58
58
PIR1
PSPIF(1)
PSPIE(1)
PSPIP(1)
ADIF
ADIE
ADIP
RCIF
RCIE
RCIP
TMR1IF
TMR1IE
TMR1IP
PIE1
TXIE
TXIP
IPR1
TMR2
T2CON
PR2
Timer2 Register
T2OUTPS3 T2OUTPS2 T2OUTPS1 T2OUTPS0 TMR2ON T2CKPS1 T2CKPS0
Timer2 Period Register
—
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the Timer2 module.
Note 1: These bits are unimplemented on 28-pin devices; always maintain these bits clear.
DS41303B-page 148
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© 2007 Microchip Technology Inc.
PIC18F2XK20/4XK20
A simplified block diagram of the Timer3 module is
shown in Figure 14-1. A block diagram of the module’s
operation in Read/Write mode is shown in Figure 14-2.
14.0 TIMER3 MODULE
The Timer3 module timer/counter incorporates these
features:
The Timer3 module is controlled through the T3CON
register (Register 14-1). It also selects the clock source
options for the CCP modules (see Section 15.1.1
“CCP Modules and Timer Resources” for more
information).
• Software selectable operation as a 16-bit timer or
counter
• Readable and writable 8-bit registers (TMR3H
and TMR3L)
• Selectable clock source (internal or external) with
device clock or Timer1 oscillator internal options
• Interrupt-on-overflow
• Module Reset on CCP Special Event Trigger
REGISTER 14-1: T3CON: TIMER3 CONTROL REGISTER
R/W-0
RD16
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
T3CCP2
T3CKPS1
T3CKPS0
T3CCP1
T3SYNC
TMR3CS
TMR3ON
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7
RD16: 16-bit Read/Write Mode Enable bit
1= Enables register read/write of Timer3 in one 16-bit operation
0= Enables register read/write of Timer3 in two 8-bit operations
bit 6,3
T3CCP<2:1>: Timer3 and Timer1 to CCPx Enable bits
1x= Timer3 is the capture/compare clock source for CCP1 and CP2
01= Timer3 is the capture/compare clock source for CCP2 and
Timer1 is the capture/compare clock source for CCP1
00= Timer1 is the capture/compare clock source for CCP1 and CP2
bit 5-4
bit 2
T3CKPS<1:0>: Timer3 Input Clock Prescale Select bits
11= 1:8 Prescale value
10= 1:4 Prescale value
01= 1:2 Prescale value
00= 1:1 Prescale value
T3SYNC: Timer3 External Clock Input Synchronization Control bit
(Not usable if the device clock comes from Timer1/Timer3.)
When TMR3CS = 1:
1= Do not synchronize external clock input
0= Synchronize external clock input
When TMR3CS = 0:
This bit is ignored. Timer3 uses the internal clock when TMR3CS = 0.
bit 1
bit 0
TMR3CS: Timer3 Clock Source Select bit
1= External clock input from Timer1 oscillator or T13CKI (on the rising edge after the first
falling edge)
0= Internal clock (FOSC/4)
TMR3ON: Timer3 On bit
1= Enables Timer3
0= Stops Timer3
© 2007 Microchip Technology Inc.
Advance Information
DS41303B-page 149
PIC18F2XK20/4XK20
The operating mode is determined by the clock select
bit, TMR3CS of the T3CON register. When TMR3CS is
cleared (= 0), Timer3 increments on every internal
instruction cycle (FOSC/4). When the bit is set, Timer3
increments on every rising edge of the Timer1 external
clock input or the Timer1 oscillator, if enabled.
14.1 Timer3 Operation
Timer3 can operate in one of three modes:
• Timer
• Synchronous Counter
• Asynchronous Counter
As with Timer1, the digital circuitry associated with the
RC1/T1OSI and RC0/T1OSO/T13CKI pins is disabled
when the Timer1 oscillator is enabled. This means the
values of TRISC<1:0> are ignored and the pins are
read as ‘0’.
FIGURE 14-1:
TIMER3 BLOCK DIAGRAM
Timer1 Oscillator
Timer1 Clock Input
1
0
T1OSO/T13CKI
T1OSI
1
0
Synchronize
Detect
Prescaler
1, 2, 4, 8
FOSC/4
Internal
Clock
2
Sleep Input
T1OSCEN(1)
TMR3CS
Timer3
On/Off
T3CKPS<1:0>
T3SYNC
TMR3ON
CCP1/CCP2 Special Event Trigger
Clear TMR3
Set
TMR3
High Byte
TMR3L
TMR3IF
CCP1/CCP2 Select from T3CON<6,3>
on Overflow
Note 1: When enable bit, T1OSCEN, is cleared, the inverter and feedback resistor are turned off to eliminate power drain.
DS41303B-page 150
Advance Information
© 2007 Microchip Technology Inc.
PIC18F2XK20/4XK20
FIGURE 14-2:
TIMER3 BLOCK DIAGRAM (16-BIT READ/WRITE MODE)
Timer1 Oscillator
Timer1 Clock Input
1
0
T13CKI/T1OSO
T1OSI
1
0
Synchronize
Detect
Prescaler
1, 2, 4, 8
FOSC/4
Internal
Clock
2
Sleep Input
T1OSCEN(1)
T3CKPS<1:0>
T3SYNC
Timer3
On/Off
TMR3CS
TMR3ON
CCP1/CCP2 Special Event Trigger
CCP1/CCP2 Select from T3CON<6,3>
Clear TMR3
Set
TMR3
High Byte
TMR3L
TMR3IF
on Overflow
8
Read TMR1L
Write TMR1L
8
8
TMR3H
8
8
Internal Data Bus
Note 1: When enable bit, T1OSCEN, is cleared, the inverter and feedback resistor are turned off to eliminate power drain.
14.2 Timer3 16-Bit Read/Write Mode
14.3 Using the Timer1 Oscillator as the
Timer3 Clock Source
Timer3 can be configured for 16-bit reads and writes
(see Figure 14-2). When the RD16 control bit of the
T3CON register is set, the address for TMR3H is
mapped to a buffer register for the high byte of Timer3.
A read from TMR3L will load the contents of the high
byte of Timer3 into the Timer3 High Byte Buffer register.
This provides the user with the ability to accurately read
all 16 bits of Timer1 without having to determine
whether a read of the high byte, followed by a read of
the low byte, has become invalid due to a rollover
between reads.
The Timer1 internal oscillator may be used as the clock
source for Timer3. The Timer1 oscillator is enabled by
setting the T1OSCEN bit of the T1CON register. To use
it as the Timer3 clock source, the TMR3CS bit must
also be set. As previously noted, this also configures
Timer3 to increment on every rising edge of the
oscillator source.
The Timer1 oscillator is described in Section 12.0
“Timer1 Module”.
A write to the high byte of Timer3 must also take place
through the TMR3H Buffer register. The Timer3 high
byte is updated with the contents of TMR3H when a
write occurs to TMR3L. This allows a user to write all
16 bits to both the high and low bytes of Timer3 at once.
14.4 Timer3 Interrupt
The TMR3 register pair (TMR3H:TMR3L) increments
from 0000h to FFFFh and overflows to 0000h. The
Timer3 interrupt, if enabled, is generated on overflow
and is latched in interrupt flag bit, TMR3IF of the PIR2
register. This interrupt can be enabled or disabled by
setting or clearing the Timer3 Interrupt Enable bit,
TMR3IE of the PIE2 register.
The high byte of Timer3 is not directly readable or
writable in this mode. All reads and writes must take
place through the Timer3 High Byte Buffer register.
Writes to TMR3H do not clear the Timer3 prescaler.
The prescaler is only cleared on writes to TMR3L.
© 2007 Microchip Technology Inc.
Advance Information
DS41303B-page 151
PIC18F2XK20/4XK20
14.5 Resetting Timer3 Using the CCP
Special Event Trigger
If either of the CCP modules is configured to use
Timer3 and to generate a Special Event Trigger
in Compare mode (CCP1M<3:0> or CCP2M<3:0> =
1011), this signal will reset Timer3. It will also start an
A/D conversion if the A/D module is enabled (see
Section 15.3.4 “Special Event Trigger” for more
information).
The module must be configured as either a timer or
synchronous counter to take advantage of this feature.
When used this way, the CCPR2H:CCPR2L register
pair effectively becomes a period register for Timer3.
If Timer3 is running in Asynchronous Counter mode,
the Reset operation may not work.
In the event that a write to Timer3 coincides with a
Special Event Trigger from a CCP module, the write will
take precedence.
Note:
The Special Event Triggers from the CCP2
module will not set the TMR3IF interrupt
flag bit of the PIR2 register.
TABLE 14-1: REGISTERS ASSOCIATED WITH TIMER3 AS A TIMER/COUNTER
Reset
Values
on page
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
INTCON
PIR2
GIE/GIEH PEIE/GIEL TMR0IE
INT0IE
EEIF
RBIE
BCLIF
BCLIE
BCLIP
TMR0IF
HLVDIF
HLVDIE
HLVDIP
INT0IF
TMR3IF
TMR3IE
TMR3IP
RBIF
57
60
60
60
59
59
58
59
OSCFIF
OSCFIE
OSCFIP
C1IF
C1IE
C1IP
C2IF
C2IE
C2IP
CCP2IF
CCP2IE
CCP2IP
PIE2
EEIE
EEIP
IPR2
TMR3L
TMR3H
T1CON
T3CON
Timer3 Register, Low Byte
Timer3 Register, High Byte
RD16
RD16
T1RUN T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON
T3CCP2 T3CKPS1 T3CKPS0 T3CCP1 T3SYNC TMR3CS TMR3ON
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the Timer3 module.
DS41303B-page 152
Advance Information
© 2007 Microchip Technology Inc.
PIC18F2XK20/4XK20
The Capture and Compare operations described in this
chapter apply to both standard and enhanced CCP
modules.
15.0 CAPTURE/COMPARE/PWM
(CCP) MODULES
PIC18F2XK20/4XK20 devices have two CCP
Capture/Compare/PWM) modules. Each module
contains a 16-bit register which can operate as a 16-bit
Capture register, a 16-bit Compare register or a PWM
Master/Slave Duty Cycle register.
Note: Throughout this section and Section 16.0
“Enhanced Capture/Compare/PWM (ECCP)
Module”, references to the register and bit
names for CCP modules are referred to
generically by the use of ‘x’ or ‘y’ in place of the
specific module number. Thus, “CCPxCON”
might refer to the control register for CCP1,
CCP2 or ECCP1. “CCPxCON” is used
throughout these sections to refer to the
module control register, regardless of whether
the CCP module is a standard or enhanced
implementation.
CCP1 is implemented as an enhanced CCP module with
standard Capture and Compare modes and enhanced
PWM modes. The ECCP implementation is discussed in
Section 16.0 “Enhanced Capture/Compare/PWM
(ECCP) Module”. CCP2 is implemented as a standard
CCP module without the enhanced features.
REGISTER 15-1: CCP2CON: STANDARD CAPTURE/COMPARE/PWM CONTROL REGISTER
U-0
—
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
DC2B1
DC2B0
CCP2M3
CCP2M2
CCP2M1
CCP2M0
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7-6
bit 5-4
Unimplemented: Read as ‘0’
DC2B<1:0>: PWM Duty Cycle bit 1 and bit 0 for CCP2 Module
Capture mode:
Unused.
Compare mode:
Unused.
PWM mode:
These bits are the two LSbs (bit 1 and bit 0) of the 10-bit PWM duty cycle. The eight MSbs
(DC2B<9:2>) of the duty cycle are found in CCPR2L.
bit 3-0
CCP2M<3:0>: CCP2 Mode Select bits
0000= Capture/Compare/PWM disabled (resets CCP2 module)
0001= Reserved
0010= Compare mode, toggle output on match (CCP2IF bit is set)
0011= Reserved
0100= Capture mode, every falling edge
0101= Capture mode, every rising edge
0110= Capture mode, every 4th rising edge
0111= Capture mode, every 16th rising edge
1000= Compare mode: initialize CCP2 pin low; on compare match, force CCP2 pin high
(CCP2IF bit is set)
1001= Compare mode: initialize CCP2 pin high; on compare match, force CCP2 pin low
(CCP2IF bit is set)
1010= Compare mode: generate software interrupt on compare match (CCP2IF bit is set,
CCP2 pin reflects I/O state)
1011= Compare mode: trigger special event, reset timer, start A/D conversion on
CCP2 match (CCP2IF bit is set)
11xx= PWM mode
© 2007 Microchip Technology Inc.
Advance Information
DS41303B-page 153
PIC18F2XK20/4XK20
The assignment of a particular timer to a module is
determined by the Timer-to-CCP enable bits in the
T3CON register (Register 14-1). Both modules can be
active at the same time and can share the same timer
resource if they are configured to operate in the same
mode (Capture/Compare or PWM). The interactions
between the two modules are summarized in Figure 15-1
and Figure 15-2. In Asynchronous Counter mode, the
capture operation will not work reliably.
15.1 CCP Module Configuration
Each Capture/Compare/PWM module is associated
with a control register (generically, CCPxCON) and a
data register (CCPRx). The data register, in turn, is
comprised of two 8-bit registers: CCPRxL (low byte)
and CCPRxH (high byte). All registers are both
readable and writable.
15.1.1
CCP MODULES AND TIMER
RESOURCES
15.1.2
CCP2 PIN ASSIGNMENT
The CCP modules utilize Timers 1, 2 or 3, depending
on the mode selected. Timer1 and Timer3 are available
to modules in Capture or Compare modes, while
Timer2 is available for modules in PWM mode.
The pin assignment for CCP2 (Capture input, Compare
and PWM output) can change, based on device config-
uration. The CCP2MX Configuration bit determines the
pin with which CCP2 is multiplexed. By default, it is
assigned to RC1 (CCP2MX = 1). If the Configuration bit
is cleared, CCP2 is multiplexed with RB3.
TABLE 15-1: CCP MODE – TIMER
RESOURCE
Changing the pin assignment of CCP2 does not
automatically change any requirements for configuring
the port pin. Users must always verify that the
appropriate TRIS register is configured correctly for
CCP2 operation, regardless of where it is located.
CCP/ECCP Mode
Timer Resource
Capture
Compare
PWM
Timer1 or Timer3
Timer1 or Timer3
Timer2
TABLE 15-2: INTERACTIONS BETWEEN CCP1 AND CCP2 FOR TIMER RESOURCES
CCP1 Mode CCP2 Mode
Interaction
Capture
Capture
Each module can use TMR1 or TMR3 as the time base. The time base can be different
for each CCP.
Capture
Compare CCP2 can be configured for the Special Event Trigger to reset TMR1 or TMR3
(depending upon which time base is used). Automatic A/D conversions on trigger event
can also be done. Operation of CCP1 could be affected if it is using the same timer as a
time base.
Compare
Compare
Capture
CCP1 can be configured for the Special Event Trigger to reset TMR1 or TMR3
(depending upon which time base is used). Operation of CCP2 could be affected if it is
using the same timer as a time base.
Compare Either module can be configured for the Special Event Trigger to reset the time base.
Automatic A/D conversions on CCP2 trigger event can be done. Conflicts may occur if
both modules are using the same time base.
Capture
Compare
PWM(1)
PWM(1)
PWM(1)
PWM
PWM
None
None
None
Capture
Compare None
PWM Both PWMs will have the same frequency and update rate (TMR2 interrupt).
Note 1: Includes standard and enhanced PWM operation.
DS41303B-page 154
Advance Information
© 2007 Microchip Technology Inc.
PIC18F2XK20/4XK20
EXAMPLE 15-1:
CHANGING BETWEEN
CAPTURE PRESCALERS
(CCP2 SHOWN)
15.2 Capture Mode
In Capture mode, the CCPRxH:CCPRxL register pair
captures the 16-bit value of the TMR1 or TMR3
registers when an event occurs on the corresponding
CCPx pin. An event is defined as one of the following:
CLRF
CCP2CON
; Turn CCP module off
MOVLW NEW_CAPT_PS ; Load WREG with the
; new prescaler mode
• every falling edge
• every rising edge
; value and CCP ON
; Load CCP2CON with
; this value
MOVWF CCP2CON
• every 4th rising edge
• every 16th rising edge
The event is selected by the mode select bits,
CCPxM<3:0> of the CCPxCON register. When a cap-
ture is made, the interrupt request flag bit, CCPxIF, is
set; it must be cleared by software. If another capture
occurs before the value in register CCPRx is read, the
old captured value is overwritten by the new captured
value.
15.2.1
CCP PIN CONFIGURATION
In Capture mode, the appropriate CCPx pin should be
configured as an input by setting the corresponding
TRIS direction bit.
Note:
If the CCPx pin is configured as an output,
a write to the port can cause a capture
condition.
15.2.2
TIMER1/TIMER3 MODE SELECTION
The timers that are to be used with the capture feature
(Timer1 and/or Timer3) must be running in Timer mode or
Synchronized Counter mode. In Asynchronous Counter
mode, the capture operation may not work. The timer to
be used with each CCP module is selected in the T3CON
register (see Section 15.1.1 “CCP Modules and Timer
Resources”).
15.2.3
SOFTWARE INTERRUPT
When the Capture mode is changed, a false capture
interrupt may be generated. The user should keep the
CCPxIE interrupt enable bit clear to avoid false inter-
rupts. The interrupt flag bit, CCPxIF, should also be
cleared following any such change in operating mode.
15.2.4
CCP PRESCALER
There are four prescaler settings in Capture mode; they
are specified as part of the operating mode selected by
the mode select bits (CCPxM<3:0>). Whenever the
CCP module is turned off or Capture mode is disabled,
the prescaler counter is cleared. This means that any
Reset will clear the prescaler counter.
Switching from one capture prescaler to another may
generate an interrupt. Also, the prescaler counter will
not be cleared; therefore, the first capture may be from
a
non-zero prescaler. Example 15-1 shows the
recommended method for switching between capture
prescalers. This example also clears the prescaler
counter and will not generate the “false” interrupt.
© 2007 Microchip Technology Inc.
Advance Information
DS41303B-page 155
PIC18F2XK20/4XK20
FIGURE 15-1:
CAPTURE MODE OPERATION BLOCK DIAGRAM
TMR3H
TMR3
TMR3L
Set CCP1IF
T3CCP2
Enable
CCP1 pin
Prescaler
÷ 1, 4, 16
and
Edge Detect
CCPR1H
CCPR1L
TMR1
Enable
T3CCP2
TMR1H
TMR3H
TMR1L
TMR3L
4
4
CCP1CON<3:0>
Q1:Q4
Set CCP2IF
4
CCP2CON<3:0>
T3CCP1
T3CCP2
TMR3
Enable
CCP2 pin
Prescaler
÷ 1, 4, 16
and
Edge Detect
CCPR2H
CCPR2L
TMR1L
TMR1
Enable
T3CCP2
T3CCP1
TMR1H
DS41303B-page 156
Advance Information
© 2007 Microchip Technology Inc.
PIC18F2XK20/4XK20
15.3.2
TIMER1/TIMER3 MODE SELECTION
15.3 Compare Mode
Timer1 and/or Timer3 must be running in Timer mode
or Synchronized Counter mode if the CCP module is
using the compare feature. In Asynchronous Counter
mode, the compare operation will not work reliably.
In Compare mode, the 16-bit CCPRx register value is
constantly compared against either the TMR1 or TMR3
register pair value. When a match occurs, the CCPx pin
can be:
• driven high
15.3.3
SOFTWARE INTERRUPT MODE
• driven low
When the Generate Software Interrupt mode is chosen
(CCPxM<3:0> = 1010), the corresponding CCPx pin is
not affected. Only the CCPxIF interrupt flag is affected.
• toggled (high-to-low or low-to-high)
• remain unchanged (that is, reflects the state of the
I/O latch)
15.3.4
SPECIAL EVENT TRIGGER
The action on the pin is based on the value of the mode
select bits (CCPxM<3:0>). At the same time, the inter-
rupt flag bit, CCPxIF, is set.
Both CCP modules are equipped with a Special Event
Trigger. This is an internal hardware signal generated
in Compare mode to trigger actions by other modules.
The Special Event Trigger is enabled by selecting
the Compare Special Event Trigger mode
(CCPxM<3:0> = 1011).
15.3.1
CCP PIN CONFIGURATION
The user must configure the CCPx pin as an output by
clearing the appropriate TRIS bit.
For either CCP module, the Special Event Trigger resets
the timer register pair for whichever timer resource is
currently assigned as the module’s time base. This
allows the CCPRx registers to serve as a programmable
period register for either timer.
Note:
Clearing the CCPxCON register will force
the CCPx compare output latch (depend-
ing on device configuration) to the default
low level. This is not the PORTB or
PORTC I/O data latch.
The Special Event Trigger for CCP2 can also start an
A/D conversion. In order to do this, the A/D converter
must already be enabled.
FIGURE 15-2:
COMPARE MODE OPERATION BLOCK DIAGRAM
Special Event Trigger
(Timer1/Timer3 Reset)
Set CCP1IF
CCPR1H
CCPR1L
CCP1 pin
S
R
Q
Output
Logic
Compare
Match
Comparator
TRIS
Output Enable
4
CCP1CON<3:0>
TMR1H
TMR3H
TMR1L
TMR3L
0
0
1
1
Special Event Trigger
(Timer1/Timer3 Reset, A/D Trigger)
T3CCP1
T3CCP2
Set CCP2IF
CCP2 pin
S
R
Q
Compare
Match
Output
Logic
Comparator
TRIS
Output Enable
4
CCPR2H
CCPR2L
CCP2CON<3:0>
© 2007 Microchip Technology Inc.
Advance Information
DS41303B-page 157
PIC18F2XK20/4XK20
TABLE 15-3: REGISTERS ASSOCIATED WITH CAPTURE, COMPARE, TIMER1 AND TIMER3
Reset
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Values
on page
INTCON
RCON
GIE/GIEH PEIE/GIEL TMR0IE
INT0IE
RI
RBIE
TO
TMR0IF
PD
INT0IF
POR
RBIF
BOR
57
56
60
60
60
60
60
60
60
60
58
58
58
59
59
59
59
59
59
59
59
59
IPEN
SBOREN
ADIF
—
PIR1
PSPIF(1)
PSPIE(1)
PSPIP(1)
OSCFIF
OSCFIE
OSCFIP
RCIF
RCIE
RCIP
C2IF
C2IE
C2IP
TXIF
TXIE
TXIP
EEIF
EEIE
EEIP
SSPIF
SSPIE
SSPIP
BCLIF
BCLIE
BCLIP
CCP1IF
TMR2IF TMR1IF
PIE1
ADIE
ADIP
C1IF
CCP1IE TMR2IE TMR1IE
CCP1IP TMR2IP TMR1IP
IPR1
PIR2
HLVDIF
TMR3IF
CCP2IF
PIE2
C1IE
HLVDIE TMR3IE CCP2IE
HLVDIP TMR3IP CCP2IP
IPR2
C1IP
TRISB
PORTB Data Direction Control Register
PORTC Data Direction Control Register
Timer1 Register, Low Byte
TRISC
TMR1L
TMR1H
T1CON
TMR3H
TMR3L
T3CON
CCPR1L
CCPR1H
CCP1CON
CCPR2L
CCPR2H
CCP2CON
Timer1 Register, High Byte
RD16
T1RUN T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON
Timer3 Register, High Byte
Timer3 Register, Low Byte
RD16
T3CCP2 T3CKPS1 T3CKPS0 T3CCP1 T3SYNC TMR3CS TMR3ON
Capture/Compare/PWM Register 1, Low Byte
Capture/Compare/PWM Register 1, High Byte
P1M1
P1M0
DC1B1
DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0
Capture/Compare/PWM Register 2, Low Byte
Capture/Compare/PWM Register 2, High Byte
—
—
DC2B1
DC2B0 CCP2M3 CCP2M2 CCP2M1 CCP2M0
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by Capture/Compare, Timer1 or Timer3.
DS41303B-page 158
Advance Information
© 2007 Microchip Technology Inc.
PIC18F2XK20/4XK20
The PWM output (Figure 15-4) has a time base
(period) and a time that the output stays high (duty
cycle).
15.4 PWM Mode
The PWM mode generates a Pulse-Width Modulated
signal on the CCP2 pin for the CCP module and the
P1A through P1D pins for the ECCP module. Hereafter
the modulated output pin will be referred to as the CCPx
pin. The duty cycle, period and resolution are
determined by the following registers:
FIGURE 15-4:
CCP PWM OUTPUT
Period
Pulse Width
• PR2
TMR2 = PR2
• T2CON
• CCPRxL
• CCPxCON
TMR2 = CCPRxL:DCxB<1:0>
TMR2 = 0
In Pulse-Width Modulation (PWM) mode, the CCP
module produces up to a 10-bit resolution PWM output
on the CCPx pin. Since the CCPx pin is multiplexed
with the PORT data latch, the TRIS for that pin must be
cleared to enable the CCPx pin output driver.
Note:
Clearing the CCPxCON register will
relinquish CCPx control of the CCPx pin.
Figure 15-3 shows a simplified block diagram of PWM
operation.
Figure 15-4 shows a typical waveform of the PWM
signal.
For a step-by-step procedure on how to set up the CCP
module for PWM operation, see Section 15.4.7
“Setup for PWM Operation”.
FIGURE 15-3:
SIMPLIFIED PWM BLOCK
DIAGRAM
DCxB<1:0>
Duty Cycle Registers
CCPRxL
CCPRxH(2) (Slave)
Comparator
CCPx
R
S
Q
(1)
TMR2
TRIS
Comparator
PR2
Clear Timer2,
toggle CCPx pin and
latch duty cycle
Note 1: The 8-bit timer TMR2 register is concatenated
with the 2-bit internal system clock (FOSC), or
2 bits of the prescaler, to create the 10-bit time
base.
2: In PWM mode, CCPRxH is a read-only register.
© 2007 Microchip Technology Inc.
Advance Information
DS41303B-page 159
PIC18F2XK20/4XK20
15.4.1
PWM PERIOD
15.4.2
PWM DUTY CYCLE
The PWM period is specified by the PR2 register of
Timer2. The PWM period can be calculated using the
formula of Equation 15-1.
The PWM duty cycle is specified by writing a 10-bit
value to multiple registers: CCPRxL register and
DCxB<1:0> bits of the CCPxCON register. The
CCPRxL contains the eight MSbs and the DCxB<1:0>
bits of the CCPxCON register contain the two LSbs.
CCPRxL and DCxB<1:0> bits of the CCPxCON
register can be written to at any time. The duty cycle
value is not latched into CCPRxH until after the period
completes (i.e., a match between PR2 and TMR2
registers occurs). While using the PWM, the CCPRxH
register is read-only.
EQUATION 15-1: PWM PERIOD
PWM Period = [(PR2) + 1] • 4 • TOSC •
(TMR2 Prescale Value)
Note: TOSC = 1/FOSC.
When TMR2 is equal to PR2, the following three events
occur on the next increment cycle:
Equation 15-2 is used to calculate the PWM pulse
width.
• TMR2 is cleared
Equation 15-3 is used to calculate the PWM duty cycle
ratio.
• The CCPx pin is set. (Exception: If the PWM duty
cycle = 0%, the pin will not be set.)
• The PWM duty cycle is latched from CCPRxL into
CCPRxH.
EQUATION 15-2: PULSE WIDTH
Pulse Width = (CCPRxL:DCxB<1:0>) •
TOSC • (TMR2 Prescale Value)
Note:
The Timer2 postscaler (see Section 13.1
“Timer2 Operation”) is not used in the
determination of the PWM frequency.
EQUATION 15-3: DUTY CYCLE RATIO
(CCPRxL:DCxB<1:0>)
Duty Cycle Ratio = ----------------------------------------------------------
4(PR2 + 1)
The CCPRxH register and a 2-bit internal latch are
used to double buffer the PWM duty cycle. This double
buffering is essential for glitchless PWM operation.
The 8-bit timer TMR2 register is concatenated with
either the 2-bit internal system clock (FOSC), or 2 bits of
the prescaler, to create the 10-bit time base. The system
clock is used if the Timer2 prescaler is set to 1:1.
When the 10-bit time base matches the CCPRxH and
2-bit latch, then the CCPx pin is cleared (see
Figure 15-3).
DS41303B-page 160
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PIC18F2XK20/4XK20
15.4.3
PWM RESOLUTION
EQUATION 15-4: PWM RESOLUTION
The resolution determines the number of available duty
cycles for a given period. For example, a 10-bit resolution
will result in 1024 discrete duty cycles, whereas an 8-bit
resolution will result in 256 discrete duty cycles.
log[4(PR2 + 1)]
Resolution = ----------------------------------------- bits
log(2)
The maximum PWM resolution is 10 bits when PR2 is
255. The resolution is a function of the PR2 register
value as shown by Equation 15-4.
Note:
If the pulse width value is greater than the
period the assigned PWM pin(s) will
remain unchanged.
TABLE 15-4: EXAMPLE PWM FREQUENCIES AND RESOLUTIONS AT 40 MHz
PWM Frequency
2.44 kHz
9.77 kHz
39.06 kHz 156.25 kHz 312.50 kHz 416.67 kHz
Timer Prescaler (1, 4, 16)
PR2 Value
16
FFh
10
4
1
1
3Fh
8
1
1Fh
7
1
FFh
10
FFh
10
17h
6.58
Maximum Resolution (bits)
TABLE 15-5: EXAMPLE PWM FREQUENCIES AND RESOLUTIONS (FOSC = 20 MHz)
PWM Frequency
1.22 kHz
4.88 kHz
19.53 kHz
78.12 kHz
156.3 kHz
208.3 kHz
Timer Prescale (1, 4, 16)
PR2 Value
16
0xFF
10
4
1
1
0x3F
8
1
0x1F
7
1
0xFF
10
0xFF
10
0x17
6.6
Maximum Resolution (bits)
TABLE 15-6: EXAMPLE PWM FREQUENCIES AND RESOLUTIONS (FOSC = 8 MHz)
PWM Frequency
1.22 kHz
4.90 kHz
19.61 kHz
76.92 kHz
153.85 kHz 200.0 kHz
Timer Prescale (1, 4, 16)
PR2 Value
16
0x65
8
4
0x65
8
1
0x65
8
1
0x19
6
1
0x0C
5
1
0x09
5
Maximum Resolution (bits)
© 2007 Microchip Technology Inc.
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PIC18F2XK20/4XK20
15.4.4
OPERATION IN POWER-MANAGED
MODES
15.4.7
SETUP FOR PWM OPERATION
The following steps should be taken when configuring
the CCP module for PWM operation:
In Sleep mode, the TMR2 register will not increment
and the state of the module will not change. If the CCPx
pin is driving a value, it will continue to drive that value.
When the device wakes up, TMR2 will continue from its
previous state.
1. Disable the PWM pin (CCPx) output drivers by
setting the associated TRIS bit.
2. For the ECCP module only: Select the desired
PWM outputs (P1A through P1D) by setting the
appropriate steering bits of the PSTRCON
register.
In PRI_IDLE mode, the primary clock will continue to
clock the CCP module without change. In all other
power-managed modes, the selected power-managed
mode clock will clock Timer2. Other power-managed
mode clocks will most likely be different than the
primary clock frequency.
3. Set the PWM period by loading the PR2 register.
4. Configure the CCP module for the PWM mode
by loading the CCPxCON register with the
appropriate values.
5. Set the PWM duty cycle by loading the CCPRxL
register and CCPx bits of the CCPxCON register.
15.4.5
CHANGES IN SYSTEM CLOCK
FREQUENCY
6. Configure and start Timer2:
The PWM frequency is derived from the system clock
frequency. Any changes in the system clock frequency
will result in changes to the PWM frequency. See
Section 2.0 “Oscillator Module (With Fail-Safe
Clock Monitor)” for additional details.
• Clear the TMR2IF interrupt flag bit of the
PIR1 register.
• Set the Timer2 prescale value by loading the
T2CKPS bits of the T2CON register.
• Enable Timer2 by setting the TMR2ON bit of
the T2CON register.
15.4.6
EFFECTS OF RESET
7. Enable PWM output after a new PWM cycle has
started:
Any Reset will force all ports to Input mode and the
CCP registers to their Reset states.
• Wait until Timer2 overflows (TMR2IF bit of
the PIR1 register is set).
• Enable the CCPx pin output driver by
clearing the associated TRIS bit.
DS41303B-page 162
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PIC18F2XK20/4XK20
TABLE 15-7: REGISTERS ASSOCIATED WITH PWM AND TIMER2
Reset
Values
on page
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
INTCON
RCON
PIR1
GIE/GIEH PEIE/GIEL TMR0IE
INT0IE
RI
RBIE
TO
TMR0IF
PD
INT0IF
POR
RBIF
BOR
57
56
60
60
60
60
60
58
58
58
59
59
59
59
59
59
59
59
IPEN
PSPIF
PSPIE
PSPIP
SBOREN
ADIF
—
RCIF
RCIE
RCIP
TXIF
TXIE
TXIP
SSPIF
SSPIE
SSPIP
CCP1IF
TMR2IF
TMR1IF
TMR1IE
TMR1IP
PIE1
ADIE
CCP1IE TMR2IE
CCP1IP TMR2IP
IPR1
ADIP
TRISB
TRISC
TMR2
PR2
PORTB Data Direction Control Register
PORTC Data Direction Control Register
Timer2 Register
Timer2 Period Register
T2CON
CCPR1L
—
T2OUTPS3 T2OUTPS2 T2OUTPS1 T2OUTPS0 TMR2ON T2CKPS1 T2CKPS0
Capture/Compare/PWM Register 1, Low Byte
CCPR1H Capture/Compare/PWM Register 1, High Byte
CCP1CON
CCPR2L
P1M1
P1M0
DC1B1
DC1B0
CCP1M3 CCP1M2 CCP1M1 CCP1M0
CCP2M3 CCP2M2 CCP2M1 CCP2M0
Capture/Compare/PWM Register 2, Low Byte
CCPR2H Capture/Compare/PWM Register 2, High Byte
CCP2CON DC2B1 DC2B0
—
—
ECCP1AS ECCPASE ECCPAS2 ECCPAS1 ECCPAS0 PSSAC1 PSSAC0 PSSBD1 PSSBD0
PWM1CON PRSEN PDC6 PDC5 PDC4 PDC3 PDC2 PDC PDC0
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PWM or Timer2.
© 2007 Microchip Technology Inc.
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PIC18F2XK20/4XK20
NOTES:
DS41303B-page 164
Advance Information
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PIC18F2XK20/4XK20
The enhanced features are discussed in detail in
Section 16.4 “PWM (Enhanced Mode)”. Capture,
Compare and single-output PWM functions of the
ECCP module are the same as described for the
standard CCP module.
16.0 ENHANCED
CAPTURE/COMPARE/PWM
(ECCP) MODULE
CCP1 is implemented as a standard CCP module with
enhanced PWM capabilities. These include:
The control register for the enhanced CCP module is
shown in Register 16-1. It differs from the CCP2CON
register in that the two Most Significant bits are
implemented to control PWM functionality.
• Provision for 2 or 4 output channels
• Output steering
• Programmable polarity
• Programmable dead-band control
• Automatic shutdown and restart.
REGISTER 16-1: CCP1CON: ENHANCED CAPTURE/COMPARE/PWM CONTROL REGISTER
R/W-0
P1M1
R/W-0
P1M0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
DC1B1
DC1B0
CCP1M3
CCP1M2
CCP1M1
CCP1M0
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7-6
P1M<1:0>: Enhanced PWM Output Configuration bits
If CCP1M<3:2> = 00, 01, 10:
xx= P1A assigned as Capture/Compare input/output; P1B, P1C, P1D assigned as port pins
If CCP1M<3:2> = 11:
00= Single output: P1A, P1B, P1C and P1D controlled by steering (See Section 16.4.7 “Pulse Steering
Mode”).
01= Full-bridge output forward: P1D modulated; P1A active; P1B, P1C inactive
10= Half-bridge output: P1A, P1B modulated with dead-band control; P1C, P1D assigned as port pins
11= Full-bridge output reverse: P1B modulated; P1C active; P1A, P1D inactive
bit 5-4
DC1B<1:0>: PWM Duty Cycle bit 1 and bit 0
Capture mode:
Unused.
Compare mode:
Unused.
PWM mode:
These bits are the two LSbs of the 10-bit PWM duty cycle. The eight MSbs of the duty cycle are found in
CCPR1L.
bit 3-0
CCP1M<3:0>: Enhanced CCP Mode Select bits
0000= Capture/Compare/PWM off (resets ECCP module)
0001= Reserved
0010= Compare mode, toggle output on match
0011= Capture mode
0100= Capture mode, every falling edge
0101= Capture mode, every rising edge
0110= Capture mode, every 4th rising edge
0111= Capture mode, every 16th rising edge
1000= Compare mode, initialize CCP1 pin low, set output on compare match (set CCP1IF)
1001= Compare mode, initialize CCP1 pin high, clear output on compare match (set CCP1IF)
1010= Compare mode, generate software interrupt only, CCP1 pin reverts to I/O state
1011= Compare mode, trigger special event (ECCP resets TMR1 or TMR3, sets CC1IF bit)
1100= PWM mode; P1A, P1C active-high; P1B, P1D active-high
1101= PWM mode; P1A, P1C active-high; P1B, P1D active-low
1110= PWM mode; P1A, P1C active-low; P1B, P1D active-high
1111= PWM mode; P1A, P1C active-low; P1B, P1D active-low
© 2007 Microchip Technology Inc.
Advance Information
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PIC18F2XK20/4XK20
In addition to the expanded range of modes available
through the CCP1CON register and ECCP1AS
register, the ECCP module has two additional registers
associated with Enhanced PWM operation and
auto-shutdown features. They are:
16.3 Standard PWM Mode
When configured in Single Output mode, the ECCP
module functions identically to the standard CCP
module in PWM mode, as described in Section 15.4
“PWM Mode”. This is also sometimes referred to as
“Single CCP” mode, as in Table 16-1.
• PWM1CON (Dead-band delay)
• PSTRCON (output steering)
16.1 ECCP Outputs and Configuration
The enhanced CCP module may have up to four PWM
outputs, depending on the selected operating mode.
These outputs, designated P1A through P1D, are
multiplexed with I/O pins on PORTC and PORTD (for
PIC18F4XK20 devices) or PORTB (for PIC18F2XK20
devices). The outputs that are active depend on the
CCP operating mode selected. The pin assignments
are summarized in Table 16-1.
To configure the I/O pins as PWM outputs, the proper
PWM mode must be selected by setting the P1M<1:0>
and CCP1M<3:0> bits. The appropriate TRISC and
TRISD direction bits for the port pins must also be set
as outputs.
16.1.1
ECCP MODULES AND TIMER
RESOURCES
Like the standard CCP modules, the ECCP module can
utilize Timers 1, 2 or 3, depending on the mode
selected. Timer1 and Timer3 are available for modules
in Capture or Compare modes, while Timer2 is
available for modules in PWM mode. Interactions
between the standard and enhanced CCP modules are
identical to those described for standard CCP modules.
Additional details on timer resources are provided in
Section 15.1.1
“CCP
Modules
and
Timer
Resources”.
16.2 Capture and Compare Modes
Except for the operation of the Special Event Trigger
discussed below, the Capture and Compare modes of
the ECCP module are identical in operation to that of
CCP2. These are discussed in detail in Section 15.2
“Capture Mode” and Section 15.3 “Compare
Mode”. No changes are required when moving
between 28-pin and 40/44-pin devices.
16.2.1
SPECIAL EVENT TRIGGER
The Special Event Trigger output of ECCP1 resets the
TMR1 or TMR3 register pair, depending on which timer
resource is currently selected. This allows the CCPR1
register to effectively be a 16-bit programmable period
register for Timer1 or Timer3.
DS41303B-page 166
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PIC18F2XK20/4XK20
The PWM outputs are multiplexed with I/O pins and are
designated P1A, P1B, P1C and P1D. The polarity of the
PWM pins is configurable and is selected by setting the
CCP1M bits in the CCP1CON register appropriately.
16.4 PWM (Enhanced Mode)
The Enhanced PWM Mode can generate a PWM signal
on up to four different output pins with up to 10-bits of
resolution. It can do this through four different PWM
output modes:
Table 16-1 shows the pin assignments for each
Enhanced PWM mode.
• Single PWM
Figure 16-1 shows an example of a simplified block
diagram of the Enhanced PWM module.
• Half-Bridge PWM
• Full-Bridge PWM, Forward mode
• Full-Bridge PWM, Reverse mode
Note:
To prevent the generation of an
incomplete waveform when the PWM is
first enabled, the ECCP module waits until
the start of a new PWM period before
generating a PWM signal.
To select an Enhanced PWM mode, the P1M bits of the
CCP1CON register must be set appropriately.
Note:
The PWM Enhanced mode is available on
the Enhanced Capture/Compare/PWM
module (CCP1) only.
FIGURE 16-1:
EXAMPLE SIMPLIFIED BLOCK DIAGRAM OF THE ENHANCED PWM MODE
DC1B<1:0>
P1M<1:0>
CCP1M<3:0>
4
Duty Cycle Registers
2
CCPR1L
CCP1/P1A
CCP1/P1A
P1B
TRIS
TRIS
TRIS
TRIS
CCPR1H (Slave)
Comparator
P1B
Output
Controller
R
S
Q
P1C
P1C
(1)
TMR2
P1D
P1D
Comparator
PR2
Clear Timer2,
toggle PWM pin and
latch duty cycle
PWM1CON
Note 1: The 8-bit timer TMR2 register is concatenated with the 2-bit internal Q clock, or 2 bits of the prescaler to create the 10-bit
time base.
Note 1: The TRIS register value for each PWM output must be configured appropriately.
2: Clearing the CCPxCON register will relinquish ECCP control of all PWM output pins.
3: Any pin not used by an Enhanced PWM mode is available for alternate pin functions.
TABLE 16-1: EXAMPLE PIN ASSIGNMENTS FOR VARIOUS PWM ENHANCED MODES
ECCP Mode
P1M<1:0>
CCP1/P1A
P1B
P1C
P1D
Single
00
10
01
11
Yes(1)
Yes
Yes(1)
Yes
Yes(1)
No
Yes(1)
No
Half-Bridge
Full-Bridge, Forward
Full-Bridge, Reverse
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Note 1: Outputs are enabled by pulse steering in Single mode. See Register 16-4.
© 2007 Microchip Technology Inc.
Advance Information
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PIC18F2XK20/4XK20
FIGURE 16-2:
EXAMPLE PWM (ENHANCED MODE) OUTPUT RELATIONSHIPS (ACTIVE-HIGH
STATE)
PR2+1
Pulse
Width
0
Signal
P1M<1:0>
Period
P1A Modulated
(Single Output)
00
10
Delay(1)
Delay(1)
P1A Modulated
P1B Modulated
P1A Active
(Half-Bridge)
P1B Inactive
(Full-Bridge,
Forward)
01
P1C Inactive
P1D Modulated
P1A Inactive
P1B Modulated
P1C Active
(Full-Bridge,
Reverse)
11
P1D Inactive
Relationships:
•
•
•
Period = 4 * TOSC * (PR2 + 1) * (TMR2 Prescale Value)
Pulse Width = TOSC * (CCPR1L<7:0>:CCP1CON<5:4>) * (TMR2 Prescale Value)
Delay = 4 * TOSC * (PWM1CON<6:0>)
Note 1: Dead-band delay is programmed using the PWM1CON register (Section 16.4.6 “Programmable Dead-Band Delay
mode”).
DS41303B-page 168
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PIC18F2XK20/4XK20
FIGURE 16-3:
EXAMPLE ENHANCED PWM OUTPUT RELATIONSHIPS (ACTIVE-LOW STATE)
PR2+1
Pulse
Width
0
Signal
P1M<1:0>
Period
P1A Modulated
P1A Modulated
P1B Modulated
P1A Active
(Single Output)
00
10
Delay(1)
Delay(1)
(Half-Bridge)
(Full-Bridge,
Forward)
P1B Inactive
P1C Inactive
P1D Modulated
P1A Inactive
P1B Modulated
P1C Active
01
(Full-Bridge,
Reverse)
11
P1D Inactive
Relationships:
•
•
•
Period = 4 * TOSC * (PR2 + 1) * (TMR2 Prescale Value)
Pulse Width = TOSC * (CCPR1L<7:0>:CCP1CON<5:4>) * (TMR2 Prescale Value)
Delay = 4 * TOSC * (PWM1CON<6:0>)
Note 1: Dead-band delay is programmed using the PWM1CON register (Section 16.4.6 “Programmable Dead-Band Delay
mode”).
© 2007 Microchip Technology Inc.
Advance Information
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PIC18F2XK20/4XK20
Since the P1A and P1B outputs are multiplexed with
the PORT data latches, the associated TRIS bits must
be cleared to configure P1A and P1B as outputs.
16.4.1
HALF-BRIDGE MODE
In Half-Bridge mode, two pins are used as outputs to
drive push-pull loads. The PWM output signal is output
on the CCPx/P1A pin, while the complementary PWM
output signal is output on the P1B pin (see
Figure 16-5). This mode can be used for Half-Bridge
applications, as shown in Figure 16-5, or for Full-Bridge
applications, where four power switches are being
modulated with two PWM signals.
FIGURE 16-4:
EXAMPLE OF
HALF-BRIDGE PWM
OUTPUT
Period
Period
Pulse Width
In Half-Bridge mode, the programmable dead-band delay
can be used to prevent shoot-through current in
Half-Bridge power devices. The value of the PDC<6:0>
bits of the PWM1CON register sets the number of
instruction cycles before the output is driven active. If the
value is greater than the duty cycle, the corresponding
output remains inactive during the entire cycle. See
Section 16.4.6 “Programmable Dead-Band Delay
mode” for more details of the dead-band delay
operations.
(2)
(2)
P1A
td
td
P1B
(1)
(1)
(1)
td = Dead-Band Delay
Note 1: At this time, the TMR2 register is equal to the
PR2 register.
2: Output signals are shown as active-high.
FIGURE 16-5:
EXAMPLE OF HALF-BRIDGE APPLICATIONS
Standard Half-Bridge Circuit (“Push-Pull”)
FET
Driver
+
-
P1A
Load
FET
Driver
+
-
P1B
Half-Bridge Output Driving a Full-Bridge Circuit
V+
FET
Driver
FET
Driver
P1A
Load
FET
FET
Driver
Driver
P1B
DS41303B-page 170
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PIC18F2XK20/4XK20
16.4.2
FULL-BRIDGE MODE
In Full-Bridge mode, all four pins are used as outputs.
An example of Full-Bridge application is shown in
Figure 16-6.
In the Forward mode, pin CCP1/P1A is driven to its
active state, pin P1D is modulated, while P1B and P1C
will be driven to their inactive state as shown in
Figure 16-7.
In the Reverse mode, P1C is driven to its active state,
pin P1B is modulated, while P1A and P1D will be driven
to their inactive state as shown Figure 16-7.
P1A, P1B, P1C and P1D outputs are multiplexed with
the PORT data latches. The associated TRIS bits must
be cleared to configure the P1A, P1B, P1C and P1D
pins as outputs.
FIGURE 16-6:
EXAMPLE OF FULL-BRIDGE APPLICATION
V+
QC
QA
FET
Driver
FET
Driver
P1A
P1B
Load
FET
Driver
FET
Driver
P1C
P1D
QD
QB
V-
© 2007 Microchip Technology Inc.
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DS41303B-page 171
PIC18F2XK20/4XK20
FIGURE 16-7:
EXAMPLE OF FULL-BRIDGE PWM OUTPUT
Forward Mode
Period
(2)
P1A
Pulse Width
(2)
P1B
(2)
P1C
(2)
P1D
(1)
(1)
Reverse Mode
Period
Pulse Width
(2)
P1A
(2)
P1B
(2)
P1C
(2)
P1D
(1)
(1)
Note 1: At this time, the TMR2 register is equal to the PR2 register.
2: Output signal is shown as active-high.
DS41303B-page 172
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PIC18F2XK20/4XK20
The Full-Bridge mode does not provide dead-band
delay. As one output is modulated at a time, dead-band
delay is generally not required. There is a situation
where dead-band delay is required. This situation
occurs when both of the following conditions are true:
16.4.2.1
Direction Change in Full-Bridge
Mode
In the Full-Bridge mode, the P1M1 bit in the CCP1CON
register allows users to control the forward/reverse
direction. When the application firmware changes this
direction control bit, the module will change to the new
direction on the next PWM cycle.
1. The direction of the PWM output changes when
the duty cycle of the output is at or near 100%.
2. The turn off time of the power switch, including
the power device and driver circuit, is greater
than the turn on time.
A direction change is initiated in software by changing
the P1M1 bit of the CCP1CON register. The following
sequence occurs prior to the end of the current PWM
period:
Figure 16-9 shows an example of the PWM direction
changing from forward to reverse, at a near 100% duty
cycle. In this example, at time t1, the output P1A and
P1D become inactive, while output P1C becomes
active. Since the turn off time of the power devices is
longer than the turn on time, a shoot-through current
will flow through power devices QC and QD (see
Figure 16-6) for the duration of ‘t’. The same
phenomenon will occur to power devices QA and QB
for PWM direction change from reverse to forward.
• The modulated outputs (P1B and P1D) are placed
in their inactive state.
• The associated unmodulated outputs (P1A and
P1C) are switched to drive in the opposite
direction.
• PWM modulation resumes at the beginning of the
next period.
See Figure 16-8 for an illustration of this sequence.
If changing PWM direction at high duty cycle is required
for an application, two possible solutions for eliminating
the shoot-through current are:
1. Reduce PWM duty cycle for one PWM period
before changing directions.
2. Use switch drivers that can drive the switches off
faster than they can drive them on.
Other options to prevent shoot-through current may
exist.
FIGURE 16-8:
EXAMPLE OF PWM DIRECTION CHANGE
(1)
Period
Period
Signal
P1A (Active-High)
P1B (Active-High)
Pulse Width
P1C (Active-High)
P1D (Active-High)
(2)
Pulse Width
Note 1: The direction bit P1M1 of the CCP1CON register is written any time during the PWM cycle.
2: When changing directions, the P1A and P1C signals switch before the end of the current PWM cycle. The
modulated P1B and P1D signals are inactive at this time. The length of this time is (1/FOSC) • TMR2 prescale
value.
© 2007 Microchip Technology Inc.
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PIC18F2XK20/4XK20
FIGURE 16-9:
EXAMPLE OF PWM DIRECTION CHANGE AT NEAR 100% DUTY CYCLE
Forward Period
Reverse Period
t1
P1A
P1B
PW
P1C
P1D
PW
TON
External Switch C
External Switch D
TOFF
Potential
T = TOFF – TON
Shoot-Through Current
Note 1: All signals are shown as active-high.
2: TON is the turn on delay of power switch QC and its driver.
3: TOFF is the turn off delay of power switch QD and its driver.
16.4.3
START-UP CONSIDERATIONS
When any PWM mode is used, the application
hardware must use the proper external pull-up and/or
pull-down resistors on the PWM output pins.
Note:
When the microcontroller is released from
Reset, all of the I/O pins are in the
high-impedance state. The external cir-
cuits must keep the power switch devices
in the Off state until the microcontroller
drives the I/O pins with the proper signal
levels or activates the PWM output(s).
The CCP1M<1:0> bits of the CCP1CON register allow
the user to choose whether the PWM output signals are
active-high or active-low for each pair of PWM output pins
(P1A/P1C and P1B/P1D). The PWM output polarities
must be selected before the PWM pin output drivers are
enabled. Changing the polarity configuration while the
PWM pin output drivers are enable is not recommended
since it may result in damage to the application circuits.
The P1A, P1B, P1C and P1D output latches may not be
in the proper states when the PWM module is
initialized. Enabling the PWM pin output drivers at the
same time as the Enhanced PWM modes may cause
damage to the application circuit. The Enhanced PWM
modes must be enabled in the proper Output mode and
complete a full PWM cycle before enabling the PWM
pin output drivers. The completion of a full PWM cycle
is indicated by the TMR2IF bit of the PIR1 register
being set as the second PWM period begins.
DS41303B-page 174
Advance Information
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PIC18F2XK20/4XK20
A shutdown condition is indicated by the ECCPASE
(Auto-Shutdown Event Status) bit of the ECCPAS
register. If the bit is a ‘0’, the PWM pins are operating
normally. If the bit is a ‘1’, the PWM outputs are in the
shutdown state.
16.4.4
ENHANCED PWM
AUTO-SHUTDOWN MODE
The PWM mode supports an Auto-Shutdown mode that
will disable the PWM outputs when an external
shutdown event occurs. Auto-Shutdown mode places
the PWM output pins into a predetermined state. This
mode is used to help prevent the PWM from damaging
the application.
When a shutdown event occurs, two things happen:
The ECCPASE bit is set to ‘1’. The ECCPASE will
remain set until cleared in firmware or an auto-restart
occurs (see Section 16.4.5 “Auto-Restart Mode”).
The auto-shutdown sources are selected using the
ECCPAS<2:0> bits of the ECCPAS register. A shutdown
event may be generated by:
The enabled PWM pins are asynchronously placed in
their shutdown states. The PWM output pins are
grouped into pairs [P1A/P1C] and [P1B/P1D]. The state
of each pin pair is determined by the PSSAC and
PSSBD bits of the ECCPAS register. Each pin pair may
be placed into one of three states:
• A logic ‘0’ on the INT pin
• Comparator C1
• Comparator C2
• Setting the ECCPASE bit in firmware
• Drive logic ‘1’
• Drive logic ‘0’
• Tri-state (high-impedance)
REGISTER 16-2: ECCP1AS: ENHANCED CAPTURE/COMPARE/PWM AUTO-SHUTDOWN
CONTROL REGISTER
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
ECCPASE
ECCPAS2
ECCPAS1
ECCPAS0
PSSAC1
PSSAC0
PSSBD1
PSSBD0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
-n = Value at POR
bit 7
ECCPASE: ECCP Auto-Shutdown Event Status bit
1= A shutdown event has occurred; ECCP outputs are in shutdown state
0= ECCP outputs are operating
bit 6-4
ECCPAS<2:0>: ECCP Auto-shutdown Source Select bits
000= Auto-Shutdown is disabled
001= Comparator C1OUT output is high
010= Comparator C2OUT output is high
011= Either Comparator C1OUT or C2OUT is high
100= VIL on INT pin
101= VIL on INT pin or Comparator C1OUT output is high
110= VIL on INT pin or Comparator C2OUT output is high
111= VIL on INT pin or Comparator C1OUT or Comparator C2OUT is high
bit 3-2
bit 1-0
PSSACn: Pins P1A and P1C Shutdown State Control bits
00= Drive pins P1A and P1C to ‘0’
01= Drive pins P1A and P1C to ‘1’
1x= Pins P1A and P1C tri-state
PSSBDn: Pins P1B and P1D Shutdown State Control bits
00= Drive pins P1B and P1D to ‘0’
01= Drive pins P1B and P1D to ‘1’
1x= Pins P1B and P1D tri-state
© 2007 Microchip Technology Inc.
Advance Information
DS41303B-page 175
PIC18F2XK20/4XK20
Note 1: The auto-shutdown condition is
a
level-based signal, not an edge-based
signal. As long as the level is present, the
auto-shutdown will persist.
2: Writing to the ECCPASE bit is disabled
while an auto-shutdown condition
persists.
3: Once the auto-shutdown condition has
been removed and the PWM restarted
(either through firmware or auto-restart)
the PWM signal will always restart at the
beginning of the next PWM period.
FIGURE 16-10:
PWM AUTO-SHUTDOWN WITH FIRMWARE RESTART (PRSEN = 0)
PWM Period
Shutdown Event
ECCPASE bit
PWM Activity
Normal PWM
ECCPASE
Cleared by
Firmware
Start of
Shutdown
Shutdown
PWM
PWM Period
Event Occurs Event Clears
Resumes
16.4.5
AUTO-RESTART MODE
The Enhanced PWM can be configured to automati-
cally restart the PWM signal once the auto-shutdown
condition has been removed. Auto-restart is enabled by
setting the PRSEN bit in the PWM1CON register.
If auto-restart is enabled, the ECCPASE bit will remain
set as long as the auto-shutdown condition is active.
When the auto-shutdown condition is removed, the
ECCPASE bit will be cleared via hardware and normal
operation will resume.
FIGURE 16-11:
PWM AUTO-SHUTDOWN WITH AUTO-RESTART ENABLED (PRSEN = 1)
PWM Period
Shutdown Event
ECCPASE bit
PWM Activity
Normal PWM
Start of
PWM Period
Shutdown
Event Occurs Event Clears
Shutdown
PWM
Resumes
DS41303B-page 176
Advance Information
© 2007 Microchip Technology Inc.
PIC18F2XK20/4XK20
16.4.6
PROGRAMMABLE DEAD-BAND
DELAY MODE
FIGURE 16-12:
EXAMPLE OF
HALF-BRIDGE PWM
OUTPUT
In Half-Bridge applications where all power switches
are modulated at the PWM frequency, the power
switches normally require more time to turn off than to
turn on. If both the upper and lower power switches are
switched at the same time (one turned on, and the
other turned off), both switches may be on for a short
period of time until one switch completely turns off.
Period
Period
Pulse Width
(2)
(2)
P1A
td
td
During this brief interval,
a very high current
P1B
(shoot-through current) will flow through both power
switches, shorting the bridge supply. To avoid this
potentially destructive shoot-through current from
flowing during switching, turning on either of the power
switches is normally delayed to allow the other switch
to completely turn off.
(1)
(1)
(1)
td = Dead-Band Delay
Note 1: At this time, the TMR2 register is equal to the
PR2 register.
In Half-Bridge mode,
a
digitally programmable
2: Output signals are shown as active-high.
dead-band delay is available to avoid shoot-through
current from destroying the bridge power switches. The
delay occurs at the signal transition from the non-active
state to the active state. See Figure 16-12 for
illustration. The lower seven bits of the associated
PWM1CON register (Register 16-3) sets the delay
period in terms of microcontroller instruction cycles
(TCY or 4 TOSC).
FIGURE 16-13:
EXAMPLE OF HALF-BRIDGE APPLICATIONS
V+
Standard Half-Bridge Circuit (“Push-Pull”)
FET
Driver
+
V
-
P1A
Load
FET
Driver
+
V
-
P1B
V-
© 2007 Microchip Technology Inc.
Advance Information
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PIC18F2XK20/4XK20
REGISTER 16-3: PWM1CON: ENHANCED PWM CONTROL REGISTER
R/W-0
R/W-0
PDC6
R/W-0
PDC5
R/W-0
PDC4
R/W-0
PDC3
R/W-0
PDC2
R/W-0
PDC1
R/W-0
PDC0
PRSEN
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7
PRSEN: PWM Restart Enable bit
1= Upon auto-shutdown, the ECCPASE bit clears automatically once the shutdown event goes
away; the PWM restarts automatically
0= Upon auto-shutdown, ECCPASE must be cleared by software to restart the PWM
bit 6-0
PDC<6:0>: PWM Delay Count bits
PDCn = Number of FOSC/4 (4 * TOSC) cycles between the scheduled time when a PWM signal
should transition active and the actual time it transitions active
DS41303B-page 178
Advance Information
© 2007 Microchip Technology Inc.
PIC18F2XK20/4XK20
16.4.7
PULSE STEERING MODE
In Single Output mode, pulse steering allows any of the
PWM pins to be the modulated signal. Additionally, the
same PWM signal can be simultaneously available on
multiple pins.
Note:
The associated TRIS bits must be set to
output (‘0’) to enable the pin output driver
in order to see the PWM signal on the pin.
While the PWM Steering mode is active, CCP1M<1:0>
bits of the CCP1CON register select the PWM output
polarity for the P1<D:A> pins.
Once the Single Output mode is selected
(CCP1M<3:2> = 11 and P1M<1:0> = 00 of the
CCP1CON register), the user firmware can bring out
the same PWM signal to one, two, three or four output
pins by setting the appropriate STR<D:A> bits of the
PSTRCON register, as shown in Table 16-1.
The PWM auto-shutdown operation also applies to
PWM Steering mode as described in Section 16.4.4
“Enhanced PWM Auto-shutdown mode”. An
auto-shutdown event will only affect pins that have
PWM outputs enabled.
REGISTER 16-4: PSTRCON: PULSE STEERING CONTROL REGISTER(1)
U-0
—
U-0
—
U-0
—
R/W-0
R/W-0
STRD
R/W-0
STRC
R/W-0
STRB
R/W-1
STRA
STRSYNC
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7-5
bit 4
Unimplemented: Read as ‘0’
STRSYNC: Steering Sync bit
1= Output steering update occurs on next PWM period
0= Output steering update occurs at the beginning of the instruction cycle boundary
bit 3
bit 2
bit 1
bit 0
STRD: Steering Enable bit D
1= P1D pin has the PWM waveform with polarity control from CCPxM<1:0>
0= P1D pin is assigned to port pin
STRC: Steering Enable bit C
1= P1C pin has the PWM waveform with polarity control from CCPxM<1:0>
0= P1C pin is assigned to port pin
STRB: Steering Enable bit B
1= P1B pin has the PWM waveform with polarity control from CCPxM<1:0>
0 = P1B pin is assigned to port pin
STRA: Steering Enable bit A
1= P1A pin has the PWM waveform with polarity control from CCPxM<1:0>
0= P1A pin is assigned to port pin
Note 1: The PWM Steering mode is available only when the CCP1CON register bits CCP1M<3:2> = 11and
P1M<1:0> = 00.
© 2007 Microchip Technology Inc.
Advance Information
DS41303B-page 179
PIC18F2XK20/4XK20
FIGURE 16-14:
SIMPLIFIED STEERING
BLOCK DIAGRAM
STRA
P1A Signal
CCP1M1
P1A pin
1
PORT Data
STRB
0
TRIS
P1B pin
CCP1M0
1
PORT Data
STRC
0
TRIS
P1C pin
1
CCP1M1
PORT Data
0
TRIS
STRD
P1D pin
1
CCP1M0
PORT Data
0
TRIS
Note 1: Port outputs are configured as shown when
the CCP1CON register bits P1M<1:0> = 00
and CCP1M<3:2> = 11.
2: Single PWM output requires setting at least
one of the STRx bits.
DS41303B-page 180
Advance Information
© 2007 Microchip Technology Inc.
PIC18F2XK20/4XK20
Figures 16-15 and 16-16 illustrate the timing diagrams
of the PWM steering depending on the STRSYNC
setting.
16.4.7.1
Steering Synchronization
The STRSYNC bit of the PSTRCON register gives the
user two selections of when the steering event will
happen. When the STRSYNC bit is ‘0’, the steering
event will happen at the end of the instruction that
writes to the PSTRCON register. In this case, the
output signal at the P1<D:A> pins may be an
incomplete PWM waveform. This operation is useful
when the user firmware needs to immediately remove
a PWM signal from the pin.
When the STRSYNC bit is ‘1’, the effective steering
update will happen at the beginning of the next PWM
period. In this case, steering on/off the PWM output will
always produce a complete PWM waveform.
FIGURE 16-15:
EXAMPLE OF STEERING EVENT AT END OF INSTRUCTION (STRSYNC = 0)
PWM Period
PWM
STRn
P1<D:A>
PORT Data
PORT Data
P1n = PWM
FIGURE 16-16:
EXAMPLE OF STEERING EVENT AT BEGINNING OF INSTRUCTION
(STRSYNC = 1)
PWM
STRn
P1<D:A>
PORT Data
PORT Data
P1n = PWM
© 2007 Microchip Technology Inc.
Advance Information
DS41303B-page 181
PIC18F2XK20/4XK20
16.4.8
OPERATION IN POWER-MANAGED
MODES
In Sleep mode, all clock sources are disabled. Timer2
will not increment and the state of the module will not
change. If the ECCP pin is driving a value, it will con-
tinue to drive that value. When the device wakes up, it
will continue from this state. If Two-Speed Start-ups are
enabled, the initial start-up frequency from HFINTOSC
and the postscaler may not be stable immediately.
In PRI_IDLE mode, the primary clock will continue to
clock the ECCP module without change. In all other
power-managed modes, the selected power-managed
mode clock will clock Timer2. Other power-managed
mode clocks will most likely be different than the
primary clock frequency.
16.4.8.1
Operation with Fail-Safe
Clock Monitor
If the Fail-Safe Clock Monitor is enabled, a clock failure
will force the device into the RC_RUN Power-Managed
mode and the OSCFIF bit of the PIR2 register will be
set. The ECCP will then be clocked from the internal
oscillator clock source, which may have a different
clock frequency than the primary clock.
See the previous section for additional details.
16.4.9
EFFECTS OF A RESET
Both Power-on Reset and subsequent Resets will force
all ports to Input mode and the CCP registers to their
Reset states.
This forces the enhanced CCP module to reset to a
state compatible with the standard CCP module.
DS41303B-page 182
Advance Information
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PIC18F2XK20/4XK20
TABLE 16-2: REGISTERS ASSOCIATED WITH ECCP1 MODULE AND TIMER1 TO TIMER3
Reset
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Values
on page
INTCON
RCON
PIR1
GIE/GIEH PEIE/GIEL
TMR0IE
—
INT0IE
RI
RBIE
TO
TMR0IF
PD
INT0IF
POR
RBIF
57
56
60
60
60
60
60
60
60
60
60
58
58
58
58
58
58
59
59
59
59
59
59
59
59
IPEN
PSPIF
SBOREN
ADIF
BOR
RCIF
RCIE
RCIP
C2IF
C2IE
C2IP
TXIF
TXIE
TXIP
EEIF
EEIE
EEIP
SSPIF
SSPIE
SSPIP
BCLIF
BCLIE
BCLIP
CCP1IF
CCP1IE
CCP1IP
HLVDIF
HLVDIE
HLVDIP
TMR2IF
TMR2IE
TMR2IP
TMR3IF
TMR3IE
TMR3IP
TMR1IF
TMR1IE
TMR1IP
CCP2IF
CCP2IE
CCP2IP
PIE1
PSPIE
ADIE
ADIP
C1IF
IPR1
PSPIP
PIR2
OSCFIF
OSCFIE
OSCFIP
PIE2
C1IE
IPR2
C1IP
TRISB
TRISC
TRISD
TMR1L
TMR1H
T1CON
TMR2
PORTB Data Direction Control Register
PORTC Data Direction Control Register
PORTD Data Direction Control Register
Timer1 Register, Low Byte
Timer1 Register, High Byte
RD16
Timer2 Register
T2OUTPS3 T2OUTPS2 T2OUTPS1 T2OUTPS0 TMR2ON T2CKPS1 T2CKPS0
T1RUN
T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON
T2CON
PR2
—
Timer2 Period Register
TMR3L
TMR3H
T3CON
CCPR1L
CCPR1H
CCP1CON
Timer3 Register, Low Byte
Timer3 Register, High Byte
RD16
T3CCP2
T3CKPS1 T3CKPS0
T3CCP1
T3SYNC TMR3CS TMR3ON
CCP1M2 CCP1M1 CCP1M0
Capture/Compare/PWM Register 1, Low Byte
Capture/Compare/PWM Register 1, High Byte
(1)
(1)
P1M1
P1M0
DC1B1
DC1B0
CCP1M3
PSSAC1
(1)
(1)
ECCP1AS ECCPASE ECCPAS2 ECCPAS1 ECCPAS0
PSSAC0 PSSBD1
PSSBD0
(1)
(1)
(1)
(1)
(1)
(1)
(1)
PWM1CON
PRSEN
PDC6
PDC5
PDC4
PDC3
PDC2
PDC1
PDC0
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used during ECCP operation.
Note 1: These bits are unimplemented on 28-pin devices; always maintain these bits clear.
© 2007 Microchip Technology Inc.
Advance Information
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PIC18F2XK20/4XK20
NOTES:
DS41303B-page 184
Advance Information
© 2007 Microchip Technology Inc.
PIC18F2XK20/4XK20
17.3 SPI Mode
17.0 MASTER SYNCHRONOUS
SERIAL PORT (MSSP)
MODULE
The SPI mode allows 8 bits of data to be synchronously
transmitted and received simultaneously. All four
modes of SPI are supported. To accomplish
communication, typically three pins are used:
17.1 Master SSP (MSSP) Module
Overview
• Serial Data Out – SDO
• Serial Data In – SDI/SDA
• Serial Clock – SCK/SCL
The Master Synchronous Serial Port (MSSP) module is
a serial interface, useful for communicating with other
peripheral or microcontroller devices. These peripheral
devices may be serial EEPROMs, shift registers, dis-
play drivers, A/D converters, etc. The MSSP module
can operate in one of two modes:
Additionally, a fourth pin may be used when in a Slave
mode of operation:
• Slave Select – SS
Figure 17-1 shows the block diagram of the MSSP
module when operating in SPI mode.
• Serial Peripheral Interface (SPI)
• Inter-Integrated Circuit (I2C)
- Full Master mode
FIGURE 17-1:
MSSP BLOCK DIAGRAM
(SPI MODE)
- Slave mode (with general address call)
The I2C interface supports the following modes in
hardware:
Internal
Data Bus
Read
Write
• Master mode
• Multi-Master mode
• Slave mode
SSPBUF Reg
SSPSR Reg
17.2 Control Registers
SDI/SDA
SDO
The MSSP module has seven associated registers.
These include:
Shift
Clock
bit 0
• SSPSTA – STATUS register
• SSPCON1 – First Control register
• SSPCON2 – Second Control register
• SSPBUF – Transmit/Receive buffer
• SSPSR – Shift register (not directly accessible)
• SSPADD – Address register
SS
Control
Enable
SS
Edge
Select
• SSPMSK – Address Mask register
The use of these registers and their individual Configu-
ration bits differ significantly depending on whether the
MSSP module is operated in SPI or I2C mode.
2
Clock Select
Additional details are provided under the individual
sections.
SSPM<3:0>
SMP:CKE
2
4
TMR2 Output
(
)
2
SCK/SCL
Edge
Select
TOSC
Prescaler
4, 16, 64
Data to TX/RX in SSPSR
TRIS bit
© 2007 Microchip Technology Inc.
Advance Information
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PIC18F2XK20/4XK20
SSPSR is the shift register used for shifting data in
and out. SSPBUF provides indirect access to the
SSPSR register. SSPBUF is the buffer register to
which data bytes are written, and from which data
bytes are read.
17.3.1
REGISTERS
The MSSP module has four registers for SPI mode
operation. These are:
• SSPCON1 – Control Register
• SSPSTAT – STATUS register
In receive operations, SSPSR and SSPBUF together
create a double-buffered receiver. When SSPSR
receives a complete byte, it is transferred to SSPBUF
and the SSPIF interrupt is set.
• SSPBUF – Serial Receive/Transmit Buffer
• SSPSR – Shift Register (Not directly accessible)
SSPCON1 and SSPSTAT are the control and STATUS
registers in SPI mode operation. The SSPCON1 regis-
ter is readable and writable. The lower 6 bits of the
SSPSTAT are read-only. The upper two bits of the
SSPSTAT are read/write.
During
transmission,
the
SSPBUF
is
not
double-buffered. A write to SSPBUF will write to both
SSPBUF and SSPSR.
REGISTER 17-1: SSPSTAT: MSSP STATUS REGISTER (SPI MODE)
R/W-0
SMP
R/W-0
CKE
R-0
D/A
R-0
P
R-0
S
R-0
R-0
UA
R-0
BF
R/W
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7
SMP: Sample bit
SPI Master mode:
1= Input data sampled at end of data output time
0= Input data sampled at middle of data output time
SPI Slave mode:
SMP must be cleared when SPI is used in Slave mode.
bit 6
CKE: SPI Clock Select bit(1)
1= Transmit occurs on transition from active to Idle clock state
0= Transmit occurs on transition from Idle to active clock state
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
D/A: Data/Address bit
Used in I2C mode only.
P: Stop bit
Used in I2C mode only. This bit is cleared when the MSSP module is disabled, SSPEN is cleared.
S: Start bit
Used in I2C mode only.
R/W: Read/Write Information bit
Used in I2C mode only.
UA: Update Address bit
Used in I2C mode only.
BF: Buffer Full Status bit (Receive mode only)
1= Receive complete, SSPBUF is full
0= Receive not complete, SSPBUF is empty
Note 1: Polarity of clock state is set by the CKP bit of the SSPCON1 register.
DS41303B-page 186
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PIC18F2XK20/4XK20
REGISTER 17-2: SSPCON1: MSSP CONTROL 1 REGISTER (SPI MODE)
R/W-0
WCOL
R/W-0
R/W-0
R/W-0
CKP
R/W-0
R/W-0
R/W-0
R/W-0
SSPOV
SSPEN
SSPM3
SSPM2
SSPM1
SSPM0
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7
WCOL: Write Collision Detect bit (Transmit mode only)
1= The SSPBUF register is written while it is still transmitting the previous word
(must be cleared by software)
0= No collision
bit 6
SSPOV: Receive Overflow Indicator bit(1)
SPI Slave mode:
1= A new byte is received while the SSPBUF register is still holding the previous data. In case of over-
flow, the data in SSPSR is lost. Overflow can only occur in Slave mode. The user must read the
SSPBUF, even if only transmitting data, to avoid setting overflow (must be cleared by software).
0= No overflow
bit 5
SSPEN: Synchronous Serial Port Enable bit(2)
1= Enables serial port and configures SCK, SDO, SDI and SS as serial port pins
0= Disables serial port and configures these pins as I/O port pins
bit 4
CKP: Clock Polarity Select bit
1= Idle state for clock is a high level
0= Idle state for clock is a low level
bit 3-0
SSPM<3:0>: Synchronous Serial Port Mode Select bits(3)
0101= SPI Slave mode, clock = SCK pin, SS pin control disabled, SS can be used as I/O pin
0100= SPI Slave mode, clock = SCK pin, SS pin control enabled
0011= SPI Master mode, clock = TMR2 output/2
0010= SPI Master mode, clock = FOSC/64
0001= SPI Master mode, clock = FOSC/16
0000= SPI Master mode, clock = FOSC/4
Note 1: In Master mode, the overflow bit is not set since each new reception (and transmission) is initiated by
writing to the SSPBUF register.
2: When enabled, these pins must be properly configured as input or output.
3: Bit combinations not specifically listed here are either reserved or implemented in I2C mode only.
© 2007 Microchip Technology Inc.
Advance Information
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PIC18F2XK20/4XK20
When the application software is expecting to receive
valid data, the SSPBUF should be read before the next
byte of data to transfer is written to the SSPBUF. The
Buffer Full bit, BF of the SSPSTAT register, indicates
when SSPBUF has been loaded with the received data
(transmission is complete). When the SSPBUF is read,
the BF bit is cleared. This data may be irrelevant if the
SPI is only a transmitter. Generally, the MSSP interrupt
is used to determine when the transmission/reception
has completed. The SSPBUF must be read and/or
written. If the interrupt method is not going to be used,
then software polling can be done to ensure that a write
collision does not occur. Example 17-1 shows the
loading of the SSPBUF (SSPSR) for data transmission.
17.3.2
OPERATION
When initializing the SPI, several options need to be
specified. This is done by programming the appropriate
control bits (SSPCON1<5:0> and SSPSTAT<7:6>).
These control bits allow the following to be specified:
• Master mode (SCK is the clock output)
• Slave mode (SCK is the clock input)
• Clock Polarity (Idle state of SCK)
• Data Input Sample Phase (middle or end of data
output time)
• Clock Edge (output data on rising/falling edge of
SCK)
• Clock Rate (Master mode only)
The SSPSR is not directly readable or writable and can
only be accessed by addressing the SSPBUF register.
Additionally, the MSSP STATUS register (SSPSTAT)
indicates the various status conditions.
• Slave Select mode (Slave mode only)
The MSSP consists of a transmit/receive shift register
(SSPSR) and a buffer register (SSPBUF). The SSPSR
shifts the data in and out of the device, MSb first. The
SSPBUF holds the data that was written to the SSPSR
until the received data is ready. Once the 8 bits of data
have been received, that byte is moved to the SSPBUF
register. Then, the Buffer Full detect bit, BF of the
SSPSTAT register, and the interrupt flag bit, SSPIF, are
set. This double-buffering of the received data
(SSPBUF) allows the next byte to start reception before
reading the data that was just received. Any write to the
SSPBUF register during transmission/reception of data
will be ignored and the write collision detect bit WCOL
of the SSPCON1 register, will be set. User software
must clear the WCOL bit so that it can be determined if
the following write(s) to the SSPBUF register
completed successfully.
EXAMPLE 17-1:
LOADING THE SSPBUF (SSPSR) REGISTER
LOOP
BTFSS
BRA
SSPSTAT, BF
LOOP
;Has data been received (transmit complete)?
;No
MOVF
SSPBUF, W
;WREG reg = contents of SSPBUF
MOVWF
RXDATA
;Save in user RAM, if data is meaningful
MOVF
MOVWF
TXDATA, W
SSPBUF
;W reg = contents of TXDATA
;New data to xmit
DS41303B-page 188
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PIC18F2XK20/4XK20
17.3.3
ENABLING SPI I/O
17.3.4
TYPICAL CONNECTION
To enable the serial port, SSP Enable bit, SSPEN of the
SSPCON1 register, must be set. To reset or reconfig-
ure SPI mode, clear the SSPEN bit, reinitialize the
SSPCON registers and then set the SSPEN bit. This
configures the SDI, SDO, SCK and SS pins as serial
port pins. For the pins to behave as the serial port func-
tion, some must have their data direction bits (in the
TRIS register) appropriately programmed as follows:
Figure 17-2 shows a typical connection between two
microcontrollers. The master controller (Processor 1)
initiates the data transfer by sending the SCK signal.
Data is shifted out of both shift registers on their pro-
grammed clock edge and latched on the opposite edge
of the clock. Both processors should be programmed to
the same Clock Polarity (CKP), then both controllers
would send and receive data at the same time.
Whether the data is meaningful (or dummy data)
depends on the application software. This leads to
three scenarios for data transmission:
• SDI is automatically controlled by the SPI module
• SDO must have corresponding TRIS bit cleared
• SCK (Master mode) must have corresponding
TRIS bit cleared
• Master sends data – Slave sends dummy data
• Master sends data – Slave sends data
• SCK (Slave mode) must have corresponding
TRIS bit set
• Master sends dummy data – Slave sends data
• SS must have corresponding TRIS bit set
Any serial port function that is not desired may be
overridden by programming the corresponding data
direction (TRIS) register to the opposite value.
FIGURE 17-2:
SPI MASTER/SLAVE CONNECTION
SPI Master SSPM<3:0> = 00xxb
SPI Slave SSPM<3:0> = 010xb
SDO
SDI
Serial Input Buffer
(SSPBUF)
Serial Input Buffer
(SSPBUF)
SDI
SDO
Shift Register
(SSPSR)
Shift Register
(SSPSR)
LSb
MSb
MSb
LSb
Serial Clock
SCK
SCK
Processor 1
Processor 2
© 2007 Microchip Technology Inc.
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PIC18F2XK20/4XK20
The clock polarity is selected by appropriately
programming the CKP bit of the SSPCON1 register.
This then, would give waveforms for SPI
communication as shown in Figure 17-3, Figure 17-5
and Figure 17-6, where the MSB is transmitted first. In
Master mode, the SPI clock rate (bit rate) is user
programmable to be one of the following:
17.3.5
MASTER MODE
The master can initiate the data transfer at any time
because it controls the SCK. The master determines
when the slave (Processor 2, Figure 17-2) is to
broadcast data by the software protocol.
In Master mode, the data is transmitted/received as
soon as the SSPBUF register is written to. If the SPI is
only going to receive, the SDO output could be dis-
abled (programmed as an input). The SSPSR register
will continue to shift in the signal present on the SDI pin
at the programmed clock rate. As each byte is
received, it will be loaded into the SSPBUF register as
if a normal received byte (interrupts and Status bits
appropriately set). This could be useful in receiver
applications as a “Line Activity Monitor” mode.
• FOSC/4 (or TCY)
• FOSC/16 (or 4 • TCY)
• FOSC/64 (or 16 • TCY)
• Timer2 output/2
This allows a maximum data rate (at 64 MHz) of
16.00 Mbps.
Figure 17-3 shows the waveforms for Master mode.
When the CKE bit is set, the SDO data is valid before
there is a clock edge on SCK. The change of the input
sample is shown based on the state of the SMP bit. The
time when the SSPBUF is loaded with the received
data is shown.
FIGURE 17-3:
SPI MODE WAVEFORM (MASTER MODE)
Write to
SSPBUF
SCK
(CKP = 0
CKE = 0)
SCK
(CKP = 1
CKE = 0)
4 Clock
Modes
SCK
(CKP = 0
CKE = 1)
SCK
(CKP = 1
CKE = 1)
bit 6
bit 6
bit 2
bit 2
bit 5
bit 5
bit 4
bit 4
bit 1
bit 1
bit 0
bit 0
SDO
(CKE = 0)
bit 7
bit 7
bit 3
bit 3
SDO
(CKE = 1)
SDI
(SMP = 0)
bit 0
bit 7
Input
Sample
(SMP = 0)
SDI
(SMP = 1)
bit 0
bit 7
Input
Sample
(SMP = 1)
SSPIF
Next Q4 Cycle
after Q2↓
SSPSR to
SSPBUF
DS41303B-page 190
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PIC18F2XK20/4XK20
must be high. When the SS pin is low, transmission and
reception are enabled and the SDO pin is driven. When
the SS pin goes high, the SDO pin is no longer driven,
even if in the middle of a transmitted byte and becomes
a floating output. External pull-up/pull-down resistors
may be desirable depending on the application.
17.3.6
SLAVE MODE
In Slave mode, the data is transmitted and received as
the external clock pulses appear on SCK. When the
last bit is latched, the SSPIF interrupt flag bit is set.
Before enabling the module in SPI Slave mode, the clock
line must match the proper Idle state. The clock line can
be observed by reading the SCK pin. The Idle state is
determined by the CKP bit of the SSPCON1 register.
Note 1: When the SPI is in Slave mode with SS pin
control enabled (SSPCON<3:0> = 0100),
the SPI module will reset if the SS pin is set
to VDD.
While in Slave mode, the external clock is supplied by
the external clock source on the SCK pin. This external
clock must meet the minimum high and low times as
specified in the electrical specifications.
2: When the SPI is used in Slave mode with
CKE set the SS pin control must also be
enabled.
While in Sleep mode, the slave can transmit/receive
data. When a byte is received, the device will wake-up
from Sleep.
When the SPI module resets, the bit counter is forced
to ‘0’. This can be done by either forcing the SS pin to
a high level or clearing the SSPEN bit.
17.3.7
SLAVE SELECT
SYNCHRONIZATION
To emulate two-wire communication, the SDO pin can
be connected to the SDI pin. When the SPI needs to
operate as a receiver, the SDO pin can be configured
as an input. This disables transmissions from the SDO.
The SDI can always be left as an input (SDI function)
since it cannot create a bus conflict.
The SS pin allows a Synchronous Slave mode. The
SPI must be in Slave mode with SS pin control enabled
(SSPCON1<3:0> = 04h). The pin must not be driven
low for the SS pin to function as an input. The data latch
FIGURE 17-4:
SLAVE SYNCHRONIZATION WAVEFORM
SS
SCK
(CKP = 0
CKE = 0)
SCK
(CKP = 1
CKE = 0)
Write to
SSPBUF
bit 6
bit 7
bit 7
bit 0
SDO
bit 7
SDI
(SMP = 0)
bit 0
bit 7
Input
Sample
(SMP = 0)
SSPIF
Interrupt
Flag
Next Q4 Cycle
after Q2↓
SSPSR to
SSPBUF
© 2007 Microchip Technology Inc.
Advance Information
DS41303B-page 191
PIC18F2XK20/4XK20
FIGURE 17-5:
SPI MODE WAVEFORM (SLAVE MODE WITH CKE = 0)
SS
Optional
SCK
(CKP = 0
CKE = 0)
SCK
(CKP = 1
CKE = 0)
Write to
SSPBUF
bit 6
bit 2
bit 5
bit 4
bit 3
bit 1
bit 0
SDO
bit 7
SDI
(SMP = 0)
bit 0
bit 7
Input
Sample
(SMP = 0)
SSPIF
Interrupt
Flag
Next Q4 Cycle
after Q2↓
SSPSR to
SSPBUF
FIGURE 17-6:
SPI MODE WAVEFORM (SLAVE MODE WITH CKE = 1)
SS
Not Optional
SCK
(CKP = 0
CKE = 1)
SCK
(CKP = 1
CKE = 1)
Write to
SSPBUF
bit 6
bit 3
bit 2
bit 5
bit 4
bit 1
bit 0
SDO
bit 7
bit 7
SDI
(SMP = 0)
bit 0
Input
Sample
(SMP = 0)
SSPIF
Interrupt
Flag
Next Q4 Cycle
after Q2↓
SSPSR to
SSPBUF
DS41303B-page 192
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PIC18F2XK20/4XK20
Transmit/Receive Shift register. When all 8 bits have
been received, the MSSP interrupt flag bit will be set
and if enabled, will wake the device.
17.3.8
OPERATION IN POWER-MANAGED
MODES
In SPI Master mode, module clocks may be operating
at a different speed than when in full power mode; in
the case of the Sleep mode, all clocks are halted.
17.3.9
EFFECTS OF A RESET
A Reset disables the MSSP module and terminates the
current transfer.
In all Idle modes, a clock is provided to the peripherals.
That clock could be from the primary clock source, the
secondary clock (Timer1 oscillator at 32.768 kHz) or
the INTOSC source. See Section 3.0 “Power-Man-
aged Modes” for additional information.
17.3.10 BUS MODE COMPATIBILITY
Table 17-1 shows the compatibility between the
standard SPI modes and the states of the CKP and
CKE control bits.
In most cases, the speed that the master clocks SPI
data is not important; however, this should be
evaluated for each system.
TABLE 17-1: SPI BUS MODES
When MSSP interrupts are enabled, after the master
completes sending data, an MSSP interrupt will wake
the controller:
Control Bits State
Standard SPI Mode
Terminology
CKP
CKE
• from Sleep, in slave mode
0, 0
0, 1
1, 0
1, 1
0
0
1
1
1
0
1
0
• from Idle, in slave or master mode
If an exit from Sleep or Idle mode is not desired, MSSP
interrupts should be disabled.
In SPI master mode, when the Sleep mode is selected,
all module clocks are halted and the transmis-
sion/reception will remain in that state until the devices
wakes. After the device returns to Run mode, the mod-
ule will resume transmitting and receiving data.
There is also an SMP bit which controls when the data
is sampled.
In SPI Slave mode, the SPI Transmit/Receive Shift
register operates asynchronously to the device. This
allows the device to be placed in any power-managed
mode and data to be shifted into the SPI
TABLE 17-2: REGISTERS ASSOCIATED WITH SPI OPERATION
Reset
Values
on page
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
INTCON
PIR1
GIE/GIEH PEIE/GIEL TMR0IE
INT0IE
TXIF
RBIE
SSPIF
SSPIE
SSPIP
TRISA3
TRISC3
TMR0IF
CCP1IF
CCP1IE
CCP1IP
TRISA2
TRISC2
INT0IF
RBIF
57
60
60
60
60
60
58
58
58
PSPIF(1)
PSPIE(1)
PSPIP(1)
ADIF
ADIE
ADIP
RCIF
RCIE
RCIP
TMR2IF
TMR1IF
PIE1
TXIE
TMR2IE TMR1IE
TMR2IP TMR1IP
IPR1
TXIP
TRISA
TRISA7(2) TRISA6(2) TRISA5
TRISA4
TRISC4
TRISA1
TRISC1
TRISA0
TRISC0
TRISC
SSPBUF
SSPCON1
SSPSTAT
TRISC7 TRISC6 TRISC5
SSP Receive Buffer/Transmit Register
WCOL
SMP
SSPOV
CKE
SSPEN
D/A
CKP
P
SSPM3
S
SSPM2
R/W
SSPM1
UA
SSPM0
BF
Legend: Shaded cells are not used by the MSSP in SPI mode.
Note 1: These bits are unimplemented in 28-pin devices; always maintain these bits clear.
2: PORTA<7:6> and their direction bits are individually configured as port pins based on various primary
oscillator modes. When disabled, these bits read as ‘0’.
© 2007 Microchip Technology Inc.
Advance Information
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PIC18F2XK20/4XK20
2
17.4.1
REGISTERS
17.4 I C Mode
The MSSP module has seven registers for I2C
operation. These are:
The MSSP module in I2C mode fully implements all
master and slave functions (including general call
support) and provides interrupts on Start and Stop bits
in hardware to determine a free bus (multi-master
function). The MSSP module implements the standard
mode specifications as well as 7-bit and 10-bit
addressing.
• MSSP Control Register 1 (SSPCON1)
• MSSP Control Register 2 (SSPCON2)
• MSSP STATUS register (SSPSTAT)
• Serial Receive/Transmit Buffer Register
(SSPBUF)
Two pins are used for data transfer:
• MSSP Shift Register (SSPSR) – Not directly
accessible
• Serial clock (SCL) – SCK/SCL
• Serial data (SDA) – SDI/SDA
• MSSP Address Register (SSPADD)
• MSSP Address Mask (SSPMSK)
The user must configure these pins as inputs with the
corresponding TRIS bits.
SSPCON1, SSPCON2 and SSPSTAT are the control
and STATUS registers in I2C mode operation. The
SSPCON1 and SSPCON2 registers are readable and
writable. The lower 6 bits of the SSPSTAT are read-only.
The upper two bits of the SSPSTAT are read/write.
FIGURE 17-7:
MSSP BLOCK DIAGRAM
(I2C™ MODE)
Internal
Data Bus
SSPSR is the shift register used for shifting data in or
out. SSPBUF is the buffer register to which data bytes
are written to or read from.
Read
Write
When the SSP is configured in Master mode, the lower
seven bits of SSPADD act as the Baud Rate Generator
reload value. When the SSP is configured for I2C slave
mode the SSPADD register holds the slave device
address. The SSP can be configured to respond to a
range of addresses by qualifying selected bits of the
address register with the SSPMSK register.
SSPBUF Reg
SCK/SCL
SDI/SDA
Shift
Clock
SSPSR Reg
MSb
LSb
In receive operations, SSPSR and SSPBUF together
create a double-buffered receiver. When SSPSR
receives a complete byte, it is transferred to SSPBUF
and the SSPIF interrupt is set.
SSPMSK Reg
Match Detect
SSPADD Reg
Addr Match
During
transmission,
the
SSPBUF
is
not
double-buffered. A write to SSPBUF will write to both
SSPBUF and SSPSR.
Set, Reset
S, P bits
(SSPSTAT Reg)
Start and
Stop bit Detect
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PIC18F2XK20/4XK20
REGISTER 17-3: SSPSTAT: MSSP STATUS REGISTER (I2C MODE)
R/W-0
SMP
R/W-0
CKE
R-0
D/A
R-0
P(1)
R-0
S(1)
R-0
R/W(2, 3)
R-0
UA
R-0
BF
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7
SMP: Slew Rate Control bit
In Master or Slave mode:
1 = Slew rate control disabled for standard speed mode (100 kHz and 1 MHz)
0 = Slew rate control enabled for high-speed mode (400 kHz)
bit 6
bit 5
CKE: SMBus Select bit
In Master or Slave mode:
1= Enable SMBus specific inputs
0= Disable SMBus specific inputs
D/A: Data/Address bit
In Master mode:
Reserved.
In Slave mode:
1= Indicates that the last byte received or transmitted was data
0= Indicates that the last byte received or transmitted was address
bit 4
bit 3
bit 2
P: Stop bit(1)
1= Indicates that a Stop bit has been detected last
0= Stop bit was not detected last
S: Start bit(1)
1= Indicates that a Start bit has been detected last
0= Start bit was not detected last
R/W: Read/Write Information bit (I2C mode only)(2, 3)
In Slave mode:
1= Read
0= Write
In Master mode:
1= Transmit is in progress
0= Transmit is not in progress
bit 1
bit 0
UA: Update Address bit (10-bit Slave mode only)
1= Indicates that the user needs to update the address in the SSPADD register
0= Address does not need to be updated
BF: Buffer Full Status bit
In Transmit mode:
1= SSPBUF is full
0= SSPBUF is empty
In Receive mode:
1= SSPBUF is full (does not include the ACK and Stop bits)
0= SSPBUF is empty (does not include the ACK and Stop bits)
Note 1: This bit is cleared on Reset and when SSPEN is cleared.
2: This bit holds the R/W bit information following the last address match. This bit is only valid from the
address match to the next Start bit, Stop bit or not ACK bit.
3: ORing this bit with SEN, RSEN, PEN, RCEN or ACKEN will indicate if the MSSP is in Active mode.
© 2007 Microchip Technology Inc.
Advance Information
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PIC18F2XK20/4XK20
REGISTER 17-4: SSPCON1: MSSP CONTROL 1 REGISTER (I2C MODE)
R/W-0
WCOL
R/W-0
R/W-0
R/W-0
CKP
R/W-0
R/W-0
R/W-0
R/W-0
SSPOV
SSPEN
SSPM3
SSPM2
SSPM1
SSPM0
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7
WCOL: Write Collision Detect bit
In Master Transmit mode:
1= A write to the SSPBUF register was attempted while the I2C conditions were not valid for a trans-
mission to be started (must be cleared by software)
0= No collision
In Slave Transmit mode:
1= The SSPBUF register is written while it is still transmitting the previous word (must be cleared by
software)
0= No collision
In Receive mode (Master or Slave modes):
This is a “don’t care” bit.
bit 6
SSPOV: Receive Overflow Indicator bit
In Receive mode:
1= A byte is received while the SSPBUF register is still holding the previous byte (must be cleared
by software)
0= No overflow
In Transmit mode:
This is a “don’t care” bit in Transmit mode.
bit 5
bit 4
SSPEN: Synchronous Serial Port Enable bit
1= Enables the serial port and configures the SDA and SCL pins as the serial port pins
0= Disables serial port and configures these pins as I/O port pins
When enabled, the SDA and SCL pins must be properly configured as input or output.
CKP: SCK Release Control bit
In Slave mode:
1= Release clock
0= Holds clock low (clock stretch), used to ensure data setup time
In Master mode:
Unused in this mode.
bit 3-0
SSPM<3:0>: Synchronous Serial Port Mode Select bits
1111= I2C Slave mode, 10-bit address with Start and Stop bit interrupts enabled
1110= I2C Slave mode, 7-bit address with Start and Stop bit interrupts enabled
1011= I2C Firmware Controlled Master mode (Slave Idle)
1000= I2C Master mode, clock = FOSC/(4 * (SSPADD + 1))
0111= I2C Slave mode, 10-bit address
0110= I2C Slave mode, 7-bit address
Bit combinations not specifically listed here are either reserved or implemented in SPI mode only.
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PIC18F2XK20/4XK20
REGISTER 17-5: SSPCON2: MSSP CONTROL REGISTER (I2C MODE)
R/W-0
GCEN
R/W-0
R/W-0
ACKDT(2)
R/W-0
ACKEN(1)
R/W-0
RCEN(1)
R/W-0
PEN(1)
R/W-0
RSEN(1)
R/W-0
SEN(1)
ACKSTAT
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
-n = Value at POR
bit 7
bit 6
bit 5
GCEN: General Call Enable bit (Slave mode only)
1= Generate interrupt when a general call address (0000h) is received in the SSPSR
0= General call address disabled
ACKSTAT: Acknowledge Status bit (Master Transmit mode only)
1= Acknowledge was not received from slave
0= Acknowledge was received from slave
ACKDT: Acknowledge Data bit (Master Receive mode only)(2)
1= Not Acknowledge
0= Acknowledge
bit 4
ACKEN: Acknowledge Sequence Enable bit (Master Receive mode only)(1)
1= Initiate Acknowledge sequence on SDA and SCL pins and transmit ACKDT data bit.
Automatically cleared by hardware.
0= Acknowledge sequence Idle
bit 3
bit 2
RCEN: Receive Enable bit (Master mode only)(1)
1= Enables Receive mode for I2C
0= Receive Idle
PEN: Stop Condition Enable bit (Master mode only)(1)
1= Initiate Stop condition on SDA and SCL pins. Automatically cleared by hardware.
0= Stop condition Idle
bit 1
bit 0
RSEN: Repeated Start Condition Enable bit (Master mode only)(1)
1= Initiate Repeated Start condition on SDA and SCL pins. Automatically cleared by hardware.
0= Repeated Start condition Idle
SEN: Start Condition Enable/Stretch Enable bit(1)
In Master mode:
1= Initiate Start condition on SDA and SCL pins. Automatically cleared by hardware.
0= Start condition Idle
In Slave mode:
1= Clock stretching is enabled for both slave transmit and slave receive (stretch enabled)
0= Clock stretching is disabled
Note 1: For bits ACKEN, RCEN, PEN, RSEN, SEN: If the I2C module is not in the Idle mode, these bits may not
be set (no spooling) and the SSPBUF may not be written (or writes to the SSPBUF are disabled).
2: Value that will be transmitted when the user initiates an Acknowledge sequence at the end of a receive.
© 2007 Microchip Technology Inc.
Advance Information
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PIC18F2XK20/4XK20
17.4.2
OPERATION
17.4.3.1
Addressing
The MSSP module functions are enabled by setting
SSPEN bit of the SSPCON1 register.
The SSPCON1 register allows control of the I2C
operation. Four mode selection bits of the SSPCON1
register allow one of the following I2C modes to be
selected:
• I2C Master mode, clock = (FOSC/4) x (SSPADD + 1)
• I2C Slave mode (7-bit address)
• I2C Slave mode (10-bit address)
• I2C Slave mode (7-bit address) with Start and
Stop bit interrupts enabled
• I2C Slave mode (10-bit address) with Start and
Stop bit interrupts enabled
• I2C Firmware Controlled Master mode, slave is
Idle
Once the MSSP module has been enabled, it waits for
a Start condition to occur. Following the Start condition,
the 8 bits are shifted into the SSPSR register. All
incoming bits are sampled with the rising edge of the
clock (SCL) line. The value of register SSPSR<7:1> is
compared to the value of the SSPADD register. The
address is compared on the falling edge of the eighth
clock (SCL) pulse. If the addresses match and the BF
and SSPOV bits are clear, the following events occur:
1. The SSPSR register value is loaded into the
SSPBUF register.
2. The Buffer Full bit, BF, is set.
3. An ACK pulse is generated.
4. MSSP Interrupt Flag bit, SSPIF of the PIR1 reg-
ister, is set (interrupt is generated, if enabled) on
the falling edge of the ninth SCL pulse.
Selection of any I2C mode with the SSPEN bit set,
forces the SCL and SDA pins to be open-drain,
provided these pins are programmed to inputs by
setting the appropriate TRIS bits. To ensure proper
operation of the module, pull-up resistors must be
provided externally to the SCL and SDA pins.
In 10-bit Address mode, two address bytes need to be
received by the slave. The five Most Significant bits
(MSbs) of the first address byte specify if this is a 10-bit
address. Bit R/W of the SSPSTAT register must specify
a write so the slave device will receive the second
address byte. For a 10-bit address, the first byte would
equal ‘11110 A9 A8 0’, where ‘A9’ and ‘A8’ are the two
MSbs of the address. The sequence of events for 10-bit
address is as follows, with steps 7 through 9 for the
slave-transmitter:
17.4.3
SLAVE MODE
In Slave mode, the SCL and SDA pins must be config-
ured as inputs. The MSSP module will override the
input state with the output data when required
(slave-transmitter).
The I2C Slave mode hardware will always generate an
interrupt on an address match. Through the mode
select bits, the user can also choose to interrupt on
Start and Stop bits
1. Receive first (high) byte of address (bits SSPIF,
BF and UA (of the SSPSTAT register are set).
2. Update the SSPADD register with second (low)
byte of address (clears bit UA and releases the
SCL line).
3. Read the SSPBUF register (clears bit BF) and
clear flag bit, SSPIF.
When an address is matched, or the data transfer after
an address match is received, the hardware
automatically will generate the Acknowledge (ACK)
pulse and load the SSPBUF register with the received
value currently in the SSPSR register.
4. Receive second (low) byte of address (bits
SSPIF, BF and UA are set). If the address
matches then the SCL is held until the next step.
Otherwise the SCL line is not held.
Any combination of the following conditions will cause
the MSSP module not to give this ACK pulse:
5. Update the SSPADD register with the first (high)
byte of address. (This will clear bit UA and
release a held SCL line.)
• The Buffer Full bit, BF bit of the SSPSTAT regis-
ter, is set before the transfer is received.
6. Read the SSPBUF register (clears bit BF) and
clear flag bit, SSPIF.
• The overflow bit, SSPOV bit of the SSPCON1
register, is set before the transfer is received.
7. Receive Repeated Start condition.
8. Receive first (high) byte of address (bits SSPIF
and BF are set).
In this case, the SSPSR register value is not loaded
into the SSPBUF, but bit SSPIF of the PIR1 register is
set. The BF bit is cleared by reading the SSPBUF
register, while bit SSPOV is cleared through software.
9. Read the SSPBUF register (clears bit BF) and
clear flag bit, SSPIF.
The SCL clock input must have a minimum high and
low for proper operation. The high and low times of the
I2C specification, as well as the requirement of the
MSSP module, are shown in timing parameter 100 and
parameter 101 (See Table 26-19).
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17.4.3.2
Reception
17.4.3.3
Transmission
When the R/W bit of the address byte is clear and an
address match occurs, the R/W bit of the SSPSTAT
register is cleared. The received address is loaded into
the SSPBUF register and the SDA line is held low
(ACK).
When the R/W bit of the incoming address byte is set
and an address match occurs, the R/W bit of the
SSPSTAT register is set. The received address is
loaded into the SSPBUF register. The ACK pulse will
be sent on the ninth bit and pin SCK/SCL is held low
regardless of SEN (see Section 17.4.4 “Clock
Stretching” for more detail). By stretching the clock,
the master will be unable to assert another clock pulse
until the slave is done preparing the transmit data. The
transmit data must be loaded into the SSPBUF register
which also loads the SSPSR register. Then pin
SCK/SCL should be enabled by setting the CKP bit of
the SSPCON1 register. The eight data bits are shifted
out on the falling edge of the SCL input. This ensures
that the SDA signal is valid during the SCL high time
(Figure 17-9).
When the address byte overflow condition exists, then
the no Acknowledge (ACK) pulse is given. An overflow
condition is defined as either bit BF bit of the SSPSTAT
register is set, or bit SSPOV bit of the SSPCON1
register is set.
An MSSP interrupt is generated for each data transfer
byte. Flag bit, SSPIF of the PIR1 register, must be
cleared by software. The SSPSTAT register is used to
determine the status of the byte.
When the SEN bit of the SSPCON2 register is set,
SCK/SCL will be held low (clock stretch) following
each data transfer. The clock must be released by
setting the CKP bit of the SSPCON1 register. See
Section 17.4.4 “Clock Stretching” for more detail.
The ACK pulse from the master-receiver is latched on
the rising edge of the ninth SCL input pulse. If the SDA
line is high (not ACK), then the data transfer is
complete. In this case, when the ACK is latched by the
slave, the slave logic is reset (resets SSPSTAT
register) and the slave monitors for another occurrence
of the Start bit. If the SDA line was low (ACK), the next
transmit data must be loaded into the SSPBUF register.
Again, pin SCK/SCL must be enabled by setting bit
CKP.
An MSSP interrupt is generated for each data transfer
byte. The SSPIF bit must be cleared by software and
the SSPSTAT register is used to determine the status
of the byte. The SSPIF bit is set on the falling edge of
the ninth clock pulse.
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2
FIGURE 17-8:
I C™ SLAVE MODE TIMING WITH SEN = 0 (RECEPTION, 7-BIT ADDRESS)
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2
FIGURE 17-9:
I C™ SLAVE MODE TIMING (TRANSMISSION, 7-BIT ADDRESS)
© 2007 Microchip Technology Inc.
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FIGURE 17-10:
I2C™ SLAVE MODE TIMING WITH SEN = 0 (RECEPTION, 10-BIT ADDRESS)
DS41303B-page 202
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2
FIGURE 17-11:
I C™ SLAVE MODE TIMING (TRANSMISSION, 10-BIT ADDRESS)
© 2007 Microchip Technology Inc.
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PIC18F2XK20/4XK20
This register must be initiated prior to setting
SSPM<3:0> bits to select the I2C Slave mode (7-bit or
10-bit address).
17.4.3.4
SSP Mask Register
An SSP Mask (SSPMSK) register is available in I2C
Slave mode as a mask for the value held in the
SSPSR register during an address comparison
operation. A zero (‘0’) bit in the SSPMSK register has
the effect of making the corresponding bit in the
SSPSR register a “don’t care”.
The SSP Mask register is active during:
• 7-bit Address mode: address compare of A<7:1>.
• 10-bit Address mode: address compare of A<7:0>
only. The SSP mask has no effect during the
reception of the first (high) byte of the address.
This register is reset to all ‘1’s upon any Reset
condition and, therefore, has no effect on standard
SSP operation until written with a mask value.
REGISTER 17-6: SSPMSK: SSP MASK REGISTER
R/W-1
MSK7
R/W-1
MSK6
R/W-1
MSK5
R/W-1
MSK4
R/W-1
MSK3
R/W-1
MSK2
R/W-1
MSK1
R/W-1
MSK0(1)
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7-1
bit 0
MSK<7:1>: Mask bits
1= The received address bit n is compared to SSPADD<n> to detect I2C address match
0= The received address bit n is not used to detect I2C address match
MSK<0>: Mask bit for I2C Slave mode, 10-bit Address(1)
I2C Slave mode, 10-bit Address (SSPM<3:0> = 0111):
1= The received address bit 0 is compared to SSPADD<0> to detect I2C address match
0= The received address bit 0 is not used to detect I2C address match
Note 1: The MSK0 bit is used only in 10-bit slave mode. In all other modes, this bit has no effect.
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17.4.4
CLOCK STRETCHING
17.4.4.3
Clock Stretching for 7-bit Slave
Transmit Mode
Both 7-bit and 10-bit Slave modes implement
automatic clock stretching during a transmit sequence.
7-bit Slave Transmit mode implements clock stretching
by clearing the CKP bit after the falling edge of the
ninth clock if the BF bit is clear. This occurs regardless
of the state of the SEN bit.
The SEN bit of the SSPCON2 register allows clock
stretching to be enabled during receives. Setting SEN
will cause the SCL pin to be held low at the end of
each data receive sequence.
The user’s ISR must set the CKP bit before transmis-
sion is allowed to continue. By holding the SCL line
low, the user has time to service the ISR and load the
contents of the SSPBUF before the master device can
initiate another data transfer sequence (see
Figure 17-9).
17.4.4.1
Clock Stretching for 7-bit Slave
Receive Mode (SEN = 1)
In 7-bit Slave Receive mode, on the falling edge of the
ninth clock at the end of the ACK sequence if the BF
bit is set, the CKP bit of the SSPCON1 register is
automatically cleared, forcing the SCL output to be
held low. The CKP being cleared to ‘0’ will assert the
SCL line low. The CKP bit must be set in the user’s
ISR before reception is allowed to continue. By holding
the SCL line low, the user has time to service the ISR
and read the contents of the SSPBUF before the
master device can initiate another data transfer
sequence. This will prevent buffer overruns from
occurring (see Figure 17-13).
Note 1: If the user loads the contents of SSPBUF,
setting the BF bit before the falling edge of
the ninth clock, the CKP bit will not be
cleared and clock stretching will not occur.
2: The CKP bit can be set by software
regardless of the state of the BF bit.
17.4.4.4
Clock Stretching for 10-bit Slave
Transmit Mode
In 10-bit Slave Transmit mode, clock stretching is con-
trolled during the first two address sequences by the
state of the UA bit, just as it is in 10-bit Slave Receive
mode. The first two addresses are followed by a third
address sequence which contains the high-order bits
of the 10-bit address and the R/W bit set to ‘1’. After
the third address sequence is performed, the UA bit is
not set, the module is now configured in Transmit
mode and clock stretching is controlled by the BF flag
as in 7-bit Slave Transmit mode (see Figure 17-11).
Note 1: If the user reads the contents of the
SSPBUF before the falling edge of the
ninth clock, thus clearing the BF bit, the
CKP bit will not be cleared and clock
stretching will not occur.
2: The CKP bit can be set by software
regardless of the state of the BF bit. The
user should be careful to clear the BF bit
in the ISR before the next receive
sequence in order to prevent an overflow
condition.
17.4.4.2
Clock Stretching for 10-bit Slave
Receive Mode (SEN = 1)
In 10-bit Slave Receive mode during the address
sequence, clock stretching automatically takes place
but CKP is not cleared. During this time, if the UA bit is
set after the ninth clock, clock stretching is initiated.
The UA bit is set after receiving the upper byte of the
10-bit address and following the receive of the second
byte of the 10-bit address with the R/W bit cleared to
‘0’. The release of the clock line occurs upon updating
SSPADD. Clock stretching will occur on each data
receive sequence as described in 7-bit mode.
Note:
If the user polls the UA bit and clears it by
updating the SSPADD register before the
falling edge of the ninth clock occurs and if
the user hasn’t cleared the BF bit by read-
ing the SSPBUF register before that time,
then the CKP bit will still NOT be asserted
low. Clock stretching on the basis of the
state of the BF bit only occurs during a
data sequence, not an address sequence.
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17.4.4.5
Clock Synchronization and
the CKP bit
When the CKP bit is cleared, the SCL output is forced
to ‘0’. However, clearing the CKP bit will not assert the
SCL output low until the SCL output is already sam-
pled low. Therefore, the CKP bit will not assert the
SCL line until an external I2C master device has
already asserted the SCL line. The SCL output will
remain low until the CKP bit is set and all other
devices on the I2C bus have deasserted SCL. This
ensures that a write to the CKP bit will not violate the
minimum high time requirement for SCL (see
Figure 17-12).
FIGURE 17-12:
CLOCK SYNCHRONIZATION TIMING
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
SDA
SCL
DX
DX – 1
Master device
asserts clock
CKP
Master device
deasserts clock
WR
SSPCON1
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2
FIGURE 17-13:
I C™ SLAVE MODE TIMING WITH SEN = 1 (RECEPTION, 7-BIT ADDRESS)
© 2007 Microchip Technology Inc.
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FIGURE 17-14:
I2C™ SLAVE MODE TIMING WITH SEN = 1 (RECEPTION, 10-BIT ADDRESS)
DS41303B-page 208
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If the general call address matches, the SSPSR is
transferred to the SSPBUF, the BF flag bit is set (eighth
bit) and on the falling edge of the ninth bit (ACK bit), the
SSPIF interrupt flag bit is set.
17.4.5
GENERAL CALL ADDRESS
SUPPORT
The addressing procedure for the I2C bus is such that
the first byte after the Start condition usually
determines which device will be the slave addressed by
the master. The exception is the general call address
which can address all devices. When this address is
used, all devices should, in theory, respond with an
Acknowledge.
When the interrupt is serviced, the source for the
interrupt can be checked by reading the contents of the
SSPBUF. The value can be used to determine if the
address was device specific or a general call address.
In 10-bit mode, the SSPADD is required to be updated
for the second half of the address to match and the UA
bit of the SSPSTAT register is set. If the general call
address is sampled when the GCEN bit is set, while the
slave is configured in 10-bit Address mode, then the
second half of the address is not necessary, the UA bit
will not be set and the slave will begin receiving data
after the Acknowledge (Figure 17-15).
The general call address is one of eight addresses
reserved for specific purposes by the I2C protocol. It
consists of all ‘0’s with R/W = 0.
The general call address is recognized when the
GCEN bit of the SSPCON2 is set. Following a Start bit
detect, 8 bits are shifted into the SSPSR and the
address is compared against the SSPADD. It is also
compared to the general call address and fixed in hard-
ware.
FIGURE 17-15:
SLAVE MODE GENERAL CALL ADDRESS SEQUENCE
(7 OR 10-BIT ADDRESS MODE)
Address is compared to General Call Address
after ACK, set interrupt
Receiving Data
D5 D4 D3 D2 D1
ACK
R/W = 0
General Call Address
ACK
9
SDA
SCL
D7 D6
D0
8
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
9
S
SSPIF
BF (SSPSTAT<0>)
Cleared by software
SSPBUF is read
SSPOV (SSPCON1<6>)
GCEN (SSPCON2<7>)
‘0’
‘1’
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17.4.6
MASTER MODE
Note:
The MSSP module, when configured in
I2C Master mode, does not allow queueing
of events. For instance, the user is not
allowed to initiate a Start condition and
immediately write the SSPBUF register to
initiate transmission before the Start
condition is complete. In this case, the
SSPBUF will not be written to and the
WCOL bit will be set, indicating that a write
to the SSPBUF did not occur.
Master mode is enabled by setting and clearing the
appropriate SSPM bits in SSPCON1 and by setting the
SSPEN bit. In Master mode, the SCL and SDA lines
are manipulated by the MSSP hardware.
Master mode of operation is supported by interrupt
generation on the detection of the Start and Stop con-
ditions. The Stop (P) and Start (S) bits are cleared from
a Reset or when the MSSP module is disabled. Control
of the I2C bus may be taken when the P bit is set, or the
bus is Idle, with both the S and P bits clear.
The following events will cause the SSP Interrupt Flag
bit, SSPIF, to be set (SSP interrupt, if enabled):
In Firmware Controlled Master mode, user code
conducts all I2C bus operations based on Start and
Stop bit conditions.
• Start condition
• Stop condition
Once Master mode is enabled, the user has six
options.
• Data transfer byte transmitted/received
• Acknowledge transmit
• Repeated Start
1. Assert a Start condition on SDA and SCL.
2. Assert a Repeated Start condition on SDA and
SCL.
3. Write to the SSPBUF register initiating
transmission of data/address.
4. Configure the I2C port to receive data.
5. Generate an Acknowledge condition at the end
of a received byte of data.
6. Generate a Stop condition on SDA and SCL.
2
FIGURE 17-16:
MSSP BLOCK DIAGRAM (I C™ MASTER MODE)
Internal
Data Bus
SSPM<3:0>
SSPADD<6:0>
Read
Write
SSPBUF
SSPSR
Baud
Rate
Generator
SDA
Shift
Clock
SDA In
MSb
LSb
Start bit, Stop bit,
Acknowledge
Generate
SCL
Start bit Detect
Stop bit Detect
Write Collision Detect
Clock Arbitration
State Counter for
end of XMIT/RCV
SCL In
Bus Collision
Set/Reset, S, P, WCOL (SSPSTAT)
Set SSPIF, BCLIF
Reset ACKSTAT, PEN (SSPCON2)
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I2C Master Mode Operation
A typical transmit sequence would go as follows:
17.4.6.1
1. The user generates a Start condition by setting
the SEN bit of the SSPCON2 register.
The master device generates all of the serial clock
pulses and the Start and Stop conditions. A transfer is
ended with a Stop condition or with a Repeated Start
condition. Since the Repeated Start condition is also
the beginning of the next serial transfer, the I2C bus will
not be released.
2. SSPIF is set. The MSSP module will wait the
required start time before any other operation
takes place.
3. The user loads the SSPBUF with the slave
address to transmit.
In Master Transmitter mode, serial data is output
through SDA, while SCL outputs the serial clock. The
first byte transmitted contains the slave address of the
receiving device (7 bits) and the Read/Write (R/W) bit.
In this case, the R/W bit will be logic ‘0’. Serial data is
transmitted 8 bits at a time. After each byte is transmit-
ted, an Acknowledge bit is received. Start and Stop
conditions are output to indicate the beginning and the
end of a serial transfer.
4. Address is shifted out the SDA pin until all 8 bits
are transmitted.
5. The MSSP module shifts in the ACK bit from the
slave device and writes its value into the
ACKSTAT bit of the SSPCON2 register.
6. The MSSP module generates an interrupt at the
end of the ninth clock cycle by setting the SSPIF
bit.
In Master Receive mode, the first byte transmitted con-
tains the slave address of the transmitting device
(7 bits) and the R/W bit. In this case, the R/W bit will be
logic ‘1’. Thus, the first byte transmitted is a 7-bit slave
address followed by a ‘1’ to indicate the receive bit.
Serial data is received via SDA, while SCL outputs the
serial clock. Serial data is received 8 bits at a time. After
each byte is received, an Acknowledge bit is transmit-
ted. Start and Stop conditions indicate the beginning
and end of transmission.
7. The user loads the SSPBUF with eight bits of
data.
8. Data is shifted out the SDA pin until all 8 bits are
transmitted.
9. The MSSP module shifts in the ACK bit from the
slave device and writes its value into the
ACKSTAT bit of the SSPCON2 register.
10. The MSSP module generates an interrupt at the
end of the ninth clock cycle by setting the SSPIF
bit.
The Baud Rate Generator used for the SPI mode
operation is used to set the SCL clock frequency for
either 100 kHz, 400 kHz or 1 MHz I2C operation. See
Section 17.4.7 “Baud Rate” for more detail.
11. The user generates a Stop condition by setting
the PEN bit of the SSPCON2 register.
12. Interrupt is generated once the Stop condition is
complete.
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Once the given operation is complete (i.e.,
transmission of the last data bit is followed by ACK), the
internal clock will automatically stop counting and the
SCL pin will remain in its last state.
17.4.7
BAUD RATE
In I2C Master mode, the Baud Rate Generator (BRG)
reload value is placed in the SSPADD register
(Figure 17-17). When a write occurs to SSPBUF, the
Baud Rate Generator will automatically begin counting.
The BRG counts down to ‘0’ and stops until another
reload has taken place. The BRG count is decre-
mented twice per instruction cycle (TCY) on the Q2 and
Q4 clocks. In I2C Master mode, the BRG is reloaded
automatically. One half of the SCL period is equal to
Table 17-3 demonstrates clock rates based on
instruction cycles and the BRG value loaded into
SSPADD.
[(SSPADD+1) • 2]/FOSC. Therefore SSPADD
(FCY/FSCL) -1.
=
FIGURE 17-17:
BAUD RATE GENERATOR BLOCK DIAGRAM
SSPM<3:0>
SSPADD<7:0>
SSPM<3:0>
SCL
Reload
Control
Reload
BRG Down Counter
CLKOUT
FOSC/2
TABLE 17-3: I2C™ CLOCK RATE W/BRG
FSCL
FOSC
FCY
BRG Value
(2 Rollovers of BRG)
64 MHz
64 MHz
64 MHz
40 MHz
40 MHz
40 MHz
16 MHz
16 MHz
16 MHz
4 MHz
16 MHz
16 MHz
16 MHz
10 MHz
10 MHz
10 MHz
4 MHz
4 MHz
4 MHz
1 MHz
1 MHz
1 MHz
27h
32h
3Fh
18h
1Fh
63h
09h
0Ch
27h
02h
09h
00h
400 kHz(1)
313.7 kHz
250 kHz
400 kHz(1)
312.5 kHz
100 kHz
400 kHz(1)
308 kHz
100 kHz
333 kHz(1)
4 MHz
100 kHz
1 MHz(1)
4 MHz
Note 1: The I2C interface does not conform to the 400 kHz I2C specification (which applies to rates greater than
100 kHz) in all details, but may be used with care where higher rates are required by the application.
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17.4.7.1
Clock Arbitration
Clock arbitration occurs when the master, during any
receive, transmit or Repeated Start/Stop condition,
deasserts the SCL pin (SCL allowed to float high).
When the SCL pin is allowed to float high, the Baud
Rate Generator (BRG) is suspended from counting
until the SCL pin is actually sampled high. When the
SCL pin is sampled high, the Baud Rate Generator is
reloaded with the contents of SSPADD<6:0> and
begins counting. This ensures that the SCL high time
will always be at least one BRG rollover count in the
event that the clock is held low by an external device
(Figure 17-18).
FIGURE 17-18:
BAUD RATE GENERATOR TIMING WITH CLOCK ARBITRATION
SDA
DX
DX – 1
SCL allowed to transition high
SCL deasserted but slave holds
SCL low (clock arbitration)
SCL
BRG decrements on
Q2 and Q4 cycles
BRG
Value
03h
02h
01h
00h (hold off)
03h
02h
SCL is sampled high, reload takes
place and BRG starts its count
BRG
Reload
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17.4.8
I2C MASTER MODE START
CONDITION TIMING
Note:
If at the beginning of the Start condition,
the SDA and SCL pins are already sam-
pled low, or if during the Start condition, the
SCL line is sampled low before the SDA
line is driven low, a bus collision occurs,
the Bus Collision Interrupt Flag, BCLIF, is
set, the Start condition is aborted and the
I2C module is reset into its Idle state.
To initiate a Start condition, the user sets the Start
Enable bit, SEN bit of the SSPCON2 register. If the
SDA and SCL pins are sampled high, the Baud Rate
Generator is reloaded with the contents of
SSPADD<6:0> and starts its count. If SCL and SDA are
both sampled high when the Baud Rate Generator
times out (TBRG), the SDA pin is driven low. The action
of the SDA being driven low while SCL is high is the
Start condition and causes the S bit of the SSPSTAT1
register to be set. Following this, the Baud Rate Gener-
ator is reloaded with the contents of SSPADD<6:0>
and resumes its count. When the Baud Rate Generator
times out (TBRG), the SEN bit of the SSPCON2 register
will be automatically cleared by hardware; the Baud
Rate Generator is suspended, leaving the SDA line
held low and the Start condition is complete.
17.4.8.1
WCOL Status Flag
If the user writes the SSPBUF when a Start sequence
is in progress, the WCOL is set and the contents of the
buffer are unchanged (the write doesn’t occur).
Note:
Because queueing of events is not
allowed, writing to the lower 5 bits of
SSPCON2 is disabled until the Start
condition is complete.
FIGURE 17-19:
FIRST START BIT TIMING
Set S bit (SSPSTAT<3>)
At completion of Start bit,
Write to SEN bit occurs here
SDA = 1,
SCL = 1
hardware clears SEN bit
and sets SSPIF bit
TBRG
TBRG
Write to SSPBUF occurs here
2nd bit
1st bit
SDA
TBRG
SCL
TBRG
S
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17.4.9
I2C MASTER MODE REPEATED
START CONDITION TIMING
Note 1: If RSEN is programmed while any other
event is in progress, it will not take effect.
A Repeated Start condition occurs when the RSEN bit
of the SSPCON2 register is programmed high and the
I2C logic module is in the Idle state. When the RSEN bit
is set, the SCL pin is asserted low. When the SCL pin
is sampled low, the Baud Rate Generator is loaded with
the contents of SSPADD<5:0> and begins counting.
The SDA pin is released (brought high) for one Baud
Rate Generator count (TBRG). When the Baud Rate
Generator times out, if SDA is sampled high, the SCL
pin will be deasserted (brought high). When SCL is
sampled high, the Baud Rate Generator is reloaded
with the contents of SSPADD<6:0> and begins count-
ing. SDA and SCL must be sampled high for one TBRG.
This action is then followed by assertion of the SDA pin
(SDA = 0) for one TBRG while SCL is high. Following
this, the RSEN bit of the SSPCON2 register will be
automatically cleared and the Baud Rate Generator will
not be reloaded, leaving the SDA pin held low. As soon
as a Start condition is detected on the SDA and SCL
pins, the S bit of the SSPSTAT register will be set. The
SSPIF bit will not be set until the Baud Rate Generator
has timed out.
2: A bus collision during the Repeated Start
condition occurs if:
• SDA is sampled low when SCL goes
from low-to-high.
• SCL goes low before SDA is
asserted low. This may indicate that
another master is attempting to
transmit a data ‘1’.
Immediately following the SSPIF bit getting set, the user
may write the SSPBUF with the 7-bit address in 7-bit
mode or the default first address in 10-bit mode. After the
first eight bits are transmitted and an ACK is received,
the user may then transmit an additional eight bits of
address (10-bit mode) or eight bits of data (7-bit mode).
17.4.9.1
WCOL Status Flag
If the user writes the SSPBUF when a Repeated Start
sequence is in progress, the WCOL is set and the
contents of the buffer are unchanged (the write doesn’t
occur).
Note:
Because queueing of events is not
allowed, writing of the lower 5 bits of
SSPCON2 is disabled until the Repeated
Start condition is complete.
FIGURE 17-20:
REPEAT START CONDITION WAVEFORM
S bit set by hardware
Write to SSPCON2
occurs here.
SDA = 1,
SCL (no change).
SDA = 1,
SCL = 1
At completion of Start bit,
hardware clears RSEN bit
and sets SSPIF
TBRG
TBRG
TBRG
1st bit
SDA
RSEN bit set by hardware
on falling edge of ninth clock,
end of Xmit
Write to SSPBUF occurs here
TBRG
SCL
TBRG
Sr = Repeated Start
© 2007 Microchip Technology Inc.
Advance Information
DS41303B-page 215
PIC18F2XK20/4XK20
17.4.10 I2C MASTER MODE
TRANSMISSION
17.4.10.3 ACKSTAT Status Flag
In Transmit mode, the ACKSTAT bit of the SSPCON2
register is cleared when the slave has sent an Acknowl-
edge (ACK = 0) and is set when the slave does not
Acknowledge (ACK = 1). A slave sends an Acknowl-
edge when it has recognized its address (including a
general call), or when the slave has properly received
its data.
Transmission of a data byte, a 7-bit address or the
other half of a 10-bit address is accomplished by simply
writing a value to the SSPBUF register. This action will
set the Buffer Full flag bit, BF and allow the Baud Rate
Generator to begin counting and start the next trans-
mission. Each bit of address/data will be shifted out
onto the SDA pin after the falling edge of SCL is
asserted (see data hold time specification
parameter 106). SCL is held low for one Baud Rate
Generator rollover count (TBRG). Data should be valid
before SCL is released high (see data setup time spec-
ification parameter 107). When the SCL pin is released
high, it is held that way for TBRG. The data on the SDA
pin must remain stable for that duration and some hold
time after the next falling edge of SCL. After the eighth
bit is shifted out (the falling edge of the eighth clock),
the BF flag is cleared and the master releases SDA.
This allows the slave device being addressed to
respond with an ACK bit during the ninth bit time if an
address match occurred, or if data was received prop-
erly. The status of ACK is written into the ACKDT bit on
the falling edge of the ninth clock. If the master receives
an Acknowledge, the Acknowledge Status bit,
ACKSTAT, is cleared. If not, the bit is set. After the ninth
clock, the SSPIF bit is set and the master clock (Baud
Rate Generator) is suspended until the next data byte
is loaded into the SSPBUF, leaving SCL low and SDA
unchanged (Figure 17-21).
17.4.11 I2C MASTER MODE RECEPTION
Master mode reception is enabled by programming the
Receive Enable bit, RCEN bit of the SSPCON2
register.
Note:
The MSSP module must be in an Idle state
before the RCEN bit is set or the RCEN bit
will be disregarded.
The Baud Rate Generator begins counting and on each
rollover, the state of the SCL pin changes
(high-to-low/low-to-high) and data is shifted into the
SSPSR. After the falling edge of the eighth clock, the
receive enable flag is automatically cleared, the con-
tents of the SSPSR are loaded into the SSPBUF, the
BF flag bit is set, the SSPIF flag bit is set and the Baud
Rate Generator is suspended from counting, holding
SCL low. The MSSP is now in Idle state awaiting the
next command. When the buffer is read by the CPU,
the BF flag bit is automatically cleared. The user can
then send an Acknowledge bit at the end of reception
by setting the Acknowledge Sequence Enable, ACKEN
bit of the SSPCON2 register.
After the write to the SSPBUF, each bit of the address
will be shifted out on the falling edge of SCL until all
seven address bits and the R/W bit are completed. On
the falling edge of the eighth clock, the master will
deassert the SDA pin, allowing the slave to respond
with an Acknowledge. On the falling edge of the ninth
clock, the master will sample the SDA pin to see if the
address was recognized by a slave. The status of the
ACK bit is loaded into the ACKSTAT Status bit of the
SSPCON2 register. Following the falling edge of the
ninth clock transmission of the address, the SSPIF is
set, the BF flag is cleared and the Baud Rate Generator
is turned off until another write to the SSPBUF takes
place, holding SCL low and allowing SDA to float.
17.4.11.1 BF Status Flag
In receive operation, the BF bit is set when an address
or data byte is loaded into SSPBUF from SSPSR. It is
cleared when the SSPBUF register is read.
17.4.11.2 SSPOV Status Flag
In receive operation, the SSPOV bit is set when 8 bits
are received into the SSPSR and the BF flag bit is
already set from a previous reception.
17.4.11.3 WCOL Status Flag
If the user writes the SSPBUF when a receive is
already in progress (i.e., SSPSR is still shifting in a data
byte), the WCOL bit is set and the contents of the buffer
are unchanged (the write doesn’t occur).
17.4.10.1 BF Status Flag
In Transmit mode, the BF bit of the SSPSTAT register
is set when the CPU writes to SSPBUF and is cleared
when all 8 bits are shifted out.
17.4.10.2 WCOL Status Flag
If the user writes the SSPBUF when a transmit is
already in progress (i.e., SSPSR is still shifting out a
data byte), the WCOL is set and the contents of the
buffer are unchanged (the write doesn’t occur).
WCOL must be cleared by software.
DS41303B-page 216
Advance Information
© 2007 Microchip Technology Inc.
PIC18F2XK20/4XK20
2
FIGURE 17-21:
I C™ MASTER MODE WAVEFORM (TRANSMISSION, 7 OR 10-BIT ADDRESS)
© 2007 Microchip Technology Inc.
Advance Information
DS41303B-page 217
PIC18F2XK20/4XK20
2
FIGURE 17-22:
I C™ MASTER MODE WAVEFORM (RECEPTION, 7-BIT ADDRESS)
DS41303B-page 218
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PIC18F2XK20/4XK20
17.4.12 ACKNOWLEDGE SEQUENCE
TIMING
17.4.13 STOP CONDITION TIMING
A Stop bit is asserted on the SDA pin at the end of a
receive/transmit by setting the Stop Sequence Enable
bit, PEN bit of the SSPCON2 register. At the end of a
receive/transmit, the SCL line is held low after the
falling edge of the ninth clock. When the PEN bit is set,
the master will assert the SDA line low. When the SDA
line is sampled low, the Baud Rate Generator is
reloaded and counts down to ‘0’. When the Baud Rate
Generator times out, the SCL pin will be brought high
and one TBRG (Baud Rate Generator rollover count)
later, the SDA pin will be deasserted. When the SDA
pin is sampled high while SCL is high, the P bit of the
SSPSTAT register is set. A TBRG later, the PEN bit is
cleared and the SSPIF bit is set (Figure 17-24).
An Acknowledge sequence is enabled by setting the
Acknowledge Sequence Enable bit, ACKEN bit of the
SSPCON2 register. When this bit is set, the SCL pin is
pulled low and the contents of the Acknowledge data bit
are presented on the SDA pin. If the user wishes to gen-
erate an Acknowledge, then the ACKDT bit should be
cleared. If not, the user should set the ACKDT bit before
starting an Acknowledge sequence. The Baud Rate
Generator then counts for one rollover period (TBRG)
and the SCL pin is deasserted (pulled high). When the
SCL pin is sampled high (clock arbitration), the Baud
Rate Generator counts for TBRG. The SCL pin is then
pulled low. Following this, the ACKEN bit is automatically
cleared, the Baud Rate Generator is turned off and the
MSSP module then goes into Idle mode (Figure 17-23).
17.4.13.1 WCOL Status Flag
If the user writes the SSPBUF when a Stop sequence
is in progress, then the WCOL bit is set and the
contents of the buffer are unchanged (the write doesn’t
occur).
17.4.12.1 WCOL Status Flag
If the user writes the SSPBUF when an Acknowledge
sequence is in progress, then WCOL is set and the
contents of the buffer are unchanged (the write doesn’t
occur).
FIGURE 17-23:
ACKNOWLEDGE SEQUENCE WAVEFORM
Acknowledge sequence starts here,
write to SSPCON2
ACKEN automatically cleared
ACKEN = 1, ACKDT = 0
TBRG
ACK
TBRG
SDA
SCL
D0
8
9
SSPIF
Cleared in
SSPIF set at
the end of receive
software
Cleared in
software
SSPIF set at the end
of Acknowledge sequence
Note: TBRG = one Baud Rate Generator period.
FIGURE 17-24:
STOP CONDITION RECEIVE OR TRANSMIT MODE
SCL = 1for TBRG, followed by SDA = 1for TBRG
after SDA sampled high. P bit (SSPSTAT<4>) is set.
Write to SSPCON2,
set PEN
PEN bit (SSPCON2<2>) is cleared by
hardware and the SSPIF bit is set
Falling edge of
9th clock
TBRG
SCL
SDA
ACK
P
TBRG
TBRG
TBRG
SCL brought high after TBRG
SDA asserted low before rising edge of clock
to setup Stop condition
Note: TBRG = one Baud Rate Generator period.
© 2007 Microchip Technology Inc.
Advance Information
DS41303B-page 219
PIC18F2XK20/4XK20
17.4.14 SLEEP OPERATION
17.4.17 MULTI -MASTER COMMUNICATION,
BUS COLLISION AND BUS
While in Sleep mode, the I2C module can receive
addresses or data and when an address match or com-
plete byte transfer occurs, wake the processor from
Sleep (if the MSSP interrupt is enabled).
ARBITRATION
Multi-Master mode support is achieved by bus arbitra-
tion. When the master outputs address/data bits onto
the SDA pin, arbitration takes place when the master
outputs a ‘1’ on SDA, by letting SDA float high and
another master asserts a ‘0’. When the SCL pin floats
high, data should be stable. If the expected data on
SDA is a ‘1’ and the data sampled on the SDA pin = 0,
then a bus collision has taken place. The master will set
the Bus Collision Interrupt Flag, BCLIF and reset the
I2C port to its Idle state (Figure 17-25).
17.4.15 EFFECTS OF A RESET
A Reset disables the MSSP module and terminates the
current transfer.
17.4.16 MULTI-MASTER MODE
In Multi-Master mode, the interrupt generation on the
detection of the Start and Stop conditions allows the
determination of when the bus is free. The Stop (P) and
Start (S) bits are cleared from a Reset or when the
MSSP module is disabled. Control of the I2C bus may
be taken when the P bit of the SSPSTAT register is set,
or the bus is Idle, with both the S and P bits clear. When
the bus is busy, enabling the SSP interrupt will gener-
ate the interrupt when the Stop condition occurs.
If a transmit was in progress when the bus collision
occurred, the transmission is halted, the BF flag is
cleared, the SDA and SCL lines are deasserted and the
SSPBUF can be written to. When the user services the
bus collision Interrupt Service Routine and if the I2C
bus is free, the user can resume communication by
asserting a Start condition.
In multi-master operation, the SDA line must be
monitored for arbitration to see if the signal level is the
expected output level. This check is performed by
hardware with the result placed in the BCLIF bit.
If a Start, Repeated Start, Stop or Acknowledge condi-
tion was in progress when the bus collision occurred, the
condition is aborted, the SDA and SCL lines are deas-
serted and the respective control bits in the SSPCON2
register are cleared. When the user services the bus col-
lision Interrupt Service Routine and if the I2C bus is free,
the user can resume communication by asserting a Start
condition.
The states where arbitration can be lost are:
• Address Transfer
• Data Transfer
• A Start Condition
The master will continue to monitor the SDA and SCL
pins. If a Stop condition occurs, the SSPIF bit will be set.
• A Repeated Start Condition
• An Acknowledge Condition
A write to the SSPBUF will start the transmission of
data at the first data bit, regardless of where the
transmitter left off when the bus collision occurred.
In Multi-Master mode, the interrupt generation on the
detection of Start and Stop conditions allows the deter-
mination of when the bus is free. Control of the I2C bus
can be taken when the P bit is set in the SSPSTAT
register, or the bus is Idle and the S and P bits are
cleared.
FIGURE 17-25:
BUS COLLISION TIMING FOR TRANSMIT AND ACKNOWLEDGE
Sample SDA. While SCL is high,
data doesn’t match what is driven
by the master.
Data changes
while SCL = 0
SDA line pulled low
by another source
Bus collision has occurred.
SDA released
by master
SDA
SCL
Set bus collision
interrupt (BCLIF)
BCLIF
DS41303B-page 220
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PIC18F2XK20/4XK20
If the SDA pin is sampled low during this count, the
BRG is reset and the SDA line is asserted early
(Figure 17-28). If, however, a ‘1’ is sampled on the SDA
pin, the SDA pin is asserted low at the end of the BRG
count. The Baud Rate Generator is then reloaded and
counts down to 0; if the SCL pin is sampled as ‘0’
during this time, a bus collision does not occur. At the
end of the BRG count, the SCL pin is asserted low.
17.4.17.1 Bus Collision During a Start
Condition
During a Start condition, a bus collision occurs if:
a) SDA or SCL are sampled low at the beginning of
the Start condition (Figure 17-26).
b) SCL is sampled low before SDA is asserted low
(Figure 17-27).
During a Start condition, both the SDA and the SCL
pins are monitored.
Note:
The reason that bus collision is not a factor
during a Start condition is that no two bus
masters can assert a Start condition at the
exact same time. Therefore, one master
will always assert SDA before the other.
This condition does not cause a bus colli-
sion because the two masters must be
allowed to arbitrate the first address fol-
lowing the Start condition. If the address is
the same, arbitration must be allowed to
continue into the data portion, Repeated
Start or Stop conditions.
If the SDA pin is already low, or the SCL pin is already
low, then all of the following occur:
• the Start condition is aborted,
• the BCLIF flag is set and
•
the MSSP module is reset to its Idle state
(Figure 17-26).
The Start condition begins with the SDA and SCL pins
deasserted. When the SDA pin is sampled high, the
Baud Rate Generator is loaded from SSPADD<6:0>
and counts down to 0. If the SCL pin is sampled low
while SDA is high, a bus collision occurs because it is
assumed that another master is attempting to drive a
data ‘1’ during the Start condition.
FIGURE 17-26:
BUS COLLISION DURING START CONDITION (SDA ONLY)
SDA goes low before the SEN bit is set.
Set BCLIF,
S bit and SSPIF set because
SDA = 0, SCL = 1.
SDA
SCL
SEN
Set SEN, enable Start
condition if SDA = 1, SCL = 1
SEN cleared automatically because of bus collision.
SSP module reset into Idle state.
SDA sampled low before
Start condition. Set BCLIF.
S bit and SSPIF set because
SDA = 0, SCL = 1.
BCLIF
SSPIF and BCLIF are
cleared by software
S
SSPIF
SSPIF and BCLIF are
cleared by software
© 2007 Microchip Technology Inc.
Advance Information
DS41303B-page 221
PIC18F2XK20/4XK20
FIGURE 17-27:
BUS COLLISION DURING START CONDITION (SCL = 0)
SDA = 0, SCL = 1
TBRG
TBRG
SDA
Set SEN, enable Start
sequence if SDA = 1, SCL = 1
SCL
SEN
SCL = 0before SDA = 0,
bus collision occurs. Set BCLIF.
SCL = 0before BRG time-out,
bus collision occurs. Set BCLIF.
BCLIF
Interrupt cleared
by software
S
‘0’
‘0’
‘0’
‘0’
SSPIF
FIGURE 17-28:
BRG RESET DUE TO SDA ARBITRATION DURING START CONDITION
SDA = 0, SCL = 1
Set S
Set SSPIF
Less than TBRG
TBRG
SDA pulled low by other master.
Reset BRG and assert SDA.
SDA
SCL
S
SCL pulled low after BRG
time-out
SEN
Set SEN, enable START
sequence if SDA = 1, SCL = 1
‘0’
BCLIF
S
SSPIF
Interrupts cleared
by software
SDA = 0, SCL = 1,
set SSPIF
DS41303B-page 222
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PIC18F2XK20/4XK20
If SDA is low, a bus collision has occurred (i.e., another
master is attempting to transmit a data ‘0’, Figure 17-29).
If SDA is sampled high, the BRG is reloaded and begins
counting. If SDA goes from high-to-low before the BRG
times out, no bus collision occurs because no two
masters can assert SDA at exactly the same time.
17.4.17.2 Bus Collision During a Repeated
Start Condition
During a Repeated Start condition, a bus collision
occurs if:
a) A low level is sampled on SDA when SCL goes
from low level to high level.
If SCL goes from high-to-low before the BRG times out
and SDA has not already been asserted, a bus collision
occurs. In this case, another master is attempting to
transmit a data ‘1’ during the Repeated Start condition,
see Figure 17-30.
b) SCL goes low before SDA is asserted low,
indicating that another master is attempting to
transmit a data ‘1’.
When the user deasserts SDA and the pin is allowed to
float high, the BRG is loaded with SSPADD<6:0> and
counts down to 0. The SCL pin is then deasserted and
when sampled high, the SDA pin is sampled.
If, at the end of the BRG time-out, both SCL and SDA
are still high, the SDA pin is driven low and the BRG is
reloaded and begins counting. At the end of the count,
regardless of the status of the SCL pin, the SCL pin is
driven low and the Repeated Start condition is
complete.
FIGURE 17-29:
BUS COLLISION DURING A REPEATED START CONDITION (CASE 1)
SDA
SCL
Sample SDA when SCL goes high.
If SDA = 0, set BCLIF and release SDA and SCL.
RSEN
BCLIF
Cleared by software
‘0’
S
‘0’
SSPIF
FIGURE 17-30:
BUS COLLISION DURING REPEATED START CONDITION (CASE 2)
TBRG
TBRG
SDA
SCL
SCL goes low before SDA,
set BCLIF. Release SDA and SCL.
BCLIF
RSEN
Interrupt cleared
by software
‘0’
S
SSPIF
© 2007 Microchip Technology Inc.
Advance Information
DS41303B-page 223
PIC18F2XK20/4XK20
The Stop condition begins with SDA asserted low.
When SDA is sampled low, the SCL pin is allowed to
float. When the pin is sampled high (clock arbitration),
the Baud Rate Generator is loaded with SSPADD<6:0>
and counts down to 0. After the BRG times out, SDA is
sampled. If SDA is sampled low, a bus collision has
occurred. This is due to another master attempting to
drive a data ‘0’ (Figure 17-31). If the SCL pin is
sampled low before SDA is allowed to float high, a bus
collision occurs. This is another case of another master
attempting to drive a data ‘0’ (Figure 17-32).
17.4.17.3 Bus Collision During a Stop
Condition
Bus collision occurs during a Stop condition if:
a) After the SDA pin has been deasserted and
allowed to float high, SDA is sampled low after
the BRG has timed out.
b) After the SCL pin is deasserted, SCL is sampled
low before SDA goes high.
FIGURE 17-31:
BUS COLLISION DURING A STOP CONDITION (CASE 1)
SDA sampled
low after TBRG,
set BCLIF
TBRG
TBRG
TBRG
SDA
SDA asserted low
SCL
PEN
BCLIF
P
‘0’
‘0’
SSPIF
FIGURE 17-32:
BUS COLLISION DURING A STOP CONDITION (CASE 2)
TBRG
TBRG
TBRG
SDA
SCL goes low before SDA goes high,
set BCLIF
Assert SDA
SCL
PEN
BCLIF
P
‘0’
‘0’
SSPIF
DS41303B-page 224
Advance Information
© 2007 Microchip Technology Inc.
PIC18F2XK20/4XK20
TABLE 17-4: SUMMARY OF REGISTERS ASSOCIATED WITH I2C™
Reset
Values on
page
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
IPR1
PSPIP
PSPIF
PSPIE
—
ADIP
ADIF
ADIE
—
RCIP
RCIF
RCIE
—
TXIP
TXIF
TXIE
—
SSPIP
SSPIF
SSPIE
BCLIP
BCLIF
BCLIE
CCP1IP
CCP1IF
CCP1IE
—
TMR2IP
TMR2IF
TMR2IE
—
TMR1IP
TMR1IF
TMR1IE
—
60
60
60
60
60
60
58
58
58
58
61
58
60
PIR1
PIE1
IPR2
PIR2
—
—
—
—
—
—
—
PIE2
—
—
—
—
—
—
—
2
2
SSPADD
SSPBUF
SSPCON1
SSPCON2
SSPMSK
SSPSTAT
TRISC
SSP Address Register in I C™ Slave Mode. SSP Baud Rate Reload Register in I C Master Mode.
SSP Receive Buffer/Transmit Register
WCOL
GCEN
MSK7
SMP
SSPOV
ACKSTAT
MSK6
SSPEN
ACKDT
MSK5
D/A
CKP
ACKEN
MSK4
P
SSPM3
RCEN
MSK3
S
SSPM2
PEN
SSPM1
RSEN
MSK1
UA
SSPM0
SEN
MSK2
R/W
MSK0
BF
CKE
TRISC7
TRISC6
TRISC5
TRISC4
TRISC3
TRISC2
TRISC1
TRISC0
Legend:
— = unimplemented, read as ‘0’. Shaded cells are not used by PORTA.
© 2007 Microchip Technology Inc.
Advance Information
DS41303B-page 225
PIC18F2XK20/4XK20
NOTES:
DS41303B-page 226
Advance Information
© 2007 Microchip Technology Inc.
PIC18F2XK20/4XK20
The EUSART module includes the following capabilities:
18.0 ENHANCED UNIVERSAL
SYNCHRONOUS
• Full-duplex asynchronous transmit and receive
• Two-character input buffer
ASYNCHRONOUS RECEIVER
TRANSMITTER (EUSART)
• One-character output buffer
• Programmable 8-bit or 9-bit character length
• Address detection in 9-bit mode
The Enhanced Universal Synchronous Asynchronous
Receiver Transmitter (EUSART) module is a serial I/O
communications peripheral. It contains all the clock
generators, shift registers and data buffers necessary
to perform an input or output serial data transfer
independent of device program execution. The
EUSART, also known as a Serial Communications
Interface (SCI), can be configured as a full-duplex
asynchronous system or half-duplex synchronous
• Input buffer overrun error detection
• Received character framing error detection
• Half-duplex synchronous master
• Half-duplex synchronous slave
• Programmable clock and data polarity
The EUSART module implements the following
additional features, making it ideally suited for use in
Local Interconnect Network (LIN) bus systems:
system.
Full-Duplex
mode
is
useful
for
communications with peripheral systems, such as CRT
terminals and personal computers. Half-Duplex
Synchronous mode is intended for communications
with peripheral devices, such as A/D or D/A integrated
circuits, serial EEPROMs or other microcontrollers.
These devices typically do not have internal clocks for
baud rate generation and require the external clock
signal provided by a master synchronous device.
• Automatic detection and calibration of the baud rate
• Wake-up on Break reception
• 13-bit Break character transmit
Block diagrams of the EUSART transmitter and
receiver are shown in Figure 18-1 and Figure 18-2.
FIGURE 18-1:
EUSART TRANSMIT BLOCK DIAGRAM
Data Bus
TXIE
Interrupt
TXIF
TXREG Register
8
TX/CK pin
MSb
(8)
LSb
0
Pin Buffer
and Control
• • •
Transmit Shift Register (TSR)
TXEN
TRMT
SPEN
Baud Rate Generator
BRG16
FOSC
÷ n
TX9
n
+ 1
Multiplier x4
x16 x64
TX9D
SYNC
BRGH
BRG16
1
X
X
X
1
1
0
1
0
0
0
1
0
0
0
SPBRGH
SPBRG
© 2007 Microchip Technology Inc.
Advance Information
DS41303B-page 227
PIC18F2XK20/4XK20
FIGURE 18-2:
EUSART RECEIVE BLOCK DIAGRAM
SPEN
CREN
OERR
RCIDL
RX/DT pin
RSR Register
MSb
Stop (8)
LSb
0
START
Pin Buffer
and Control
Data
Recovery
7
1
• • •
Baud Rate Generator
FOSC
RX9
÷ n
BRG16
n
+ 1
Multiplier
x4
x16 x64
SYNC
BRGH
BRG16
1
X
1
1
0
1
0
0
0
1
0
0
0
FIFO
SPBRGH
SPBRG
X
X
RX9D
FERR
RCREG Register
8
Data Bus
RCIF
RCIE
Interrupt
The operation of the EUSART module is controlled
through three registers:
• Transmit Status and Control (TXSTA)
• Receive Status and Control (RCSTA)
• Baud Rate Control (BAUDCTL)
These registers are detailed in Register 18-1,
Register 18-2 and Register 18-3, respectively.
For all modes of EUSART operation, the TRIS control
bits corresponding to the RX/DT and TX/CK pins should
be set to ‘1’. The EUSART control will automatically
reconfigure the pin from input to output, as needed.
DS41303B-page 228
Advance Information
© 2007 Microchip Technology Inc.
PIC18F2XK20/4XK20
18.1 EUSART Asynchronous Mode
Note 1: When the SPEN bit is set the RX/DT I/O pin
is automatically configured as an input,
regardless of the state of the corresponding
TRIS bit and whether or not the EUSART
receiver is enabled. The RX/DT pin data
can be read via a normal PORT read but
PORT latch data output is precluded.
The EUSART transmits and receives data using the
standard non-return-to-zero (NRZ) format. NRZ is
implemented with two levels: a VOH mark state which
represents a ‘1’ data bit, and a VOL space state which
represents a ‘0’ data bit. NRZ refers to the fact that
consecutively transmitted data bits of the same value
stay at the output level of that bit without returning to a
neutral level between each bit transmission. An NRZ
transmission port idles in the mark state. Each character
transmission consists of one Start bit followed by eight
or nine data bits and is always terminated by one or
more Stop bits. The Start bit is always a space and the
Stop bits are always marks. The most common data
format is 8 bits. Each transmitted bit persists for a period
of 1/(Baud Rate). An on-chip dedicated 8-bit/16-bit Baud
Rate Generator is used to derive standard baud rate
frequencies from the system oscillator. See Table 18-5
for examples of baud rate configurations.
2: The TXIF transmitter interrupt flag is set
when the TXEN enable bit is set.
18.1.1.2
Transmitting Data
A transmission is initiated by writing a character to the
TXREG register. If this is the first character, or the
previous character has been completely flushed from
the TSR, the data in the TXREG is immediately
transferred to the TSR register. If the TSR still contains
all or part of a previous character, the new character
data is held in the TXREG until the Stop bit of the
previous character has been transmitted. The pending
character in the TXREG is then transferred to the TSR
in one TCY immediately following the Stop bit
transmission. The transmission of the Start bit, data bits
and Stop bit sequence commences immediately
following the transfer of the data to the TSR from the
TXREG.
The EUSART transmits and receives the LSb first. The
EUSART’s transmitter and receiver are functionally
independent, but share the same data format and baud
rate. Parity is not supported by the hardware, but can
be implemented in software and stored as the ninth
data bit.
18.1.1
EUSART ASYNCHRONOUS
TRANSMITTER
18.1.1.3
Transmit Data Polarity
The EUSART transmitter block diagram is shown in
Figure 18-1. The heart of the transmitter is the serial
Transmit Shift Register (TSR), which is not directly
accessible by software. The TSR obtains its data from
the transmit buffer, which is the TXREG register.
The polarity of the transmit data can be controlled with
the CKTXP bit of the BAUDCTL register. The default
state of this bit is ‘0’ which selects high true transmit
idle and data bits. Setting the CKTXP bit to ‘1’ will invert
the transmit data resulting in low true idle and data bits.
The CKTXP bit controls transmit data polarity only in
Asynchronous mode. In Synchronous mode the
CKTXP bit has a different function.
18.1.1.1
Enabling the Transmitter
The EUSART transmitter is enabled for asynchronous
operations by configuring the following three control
bits:
18.1.1.4
Transmit Interrupt Flag
The TXIF interrupt flag bit of the PIR1 register is set
whenever the EUSART transmitter is enabled and no
character is being held for transmission in the TXREG.
In other words, the TXIF bit is only clear when the TSR
is busy with a character and a new character has been
queued for transmission in the TXREG. The TXIF flag bit
is not cleared immediately upon writing TXREG. TXIF
becomes valid in the second instruction cycle following
the write execution. Polling TXIF immediately following
the TXREG write will return invalid results. The TXIF bit
is read-only, it cannot be set or cleared by software.
• TXEN = 1
• SYNC = 0
• SPEN = 1
All other EUSART control bits are assumed to be in
their default state.
Setting the TXEN bit of the TXSTA register enables the
transmitter circuitry of the EUSART. Clearing the SYNC
bit of the TXSTA register configures the EUSART for
asynchronous operation. Setting the SPEN bit of the
RCSTA register enables the EUSART and automatically
configures the TX/CK I/O pin as an output. If the TX/CK
pin is shared with an analog peripheral the analog I/O
function must be disabled by clearing the corresponding
ANSEL bit.
The TXIF interrupt can be enabled by setting the TXIE
interrupt enable bit of the PIE1 register. However, the
TXIF flag bit will be set whenever the TXREG is empty,
regardless of the state of TXIE enable bit.
To use interrupts when transmitting data, set the TXIE
bit only when there is more data to send. Clear the
TXIE interrupt enable bit upon writing the last character
of the transmission to the TXREG.
© 2007 Microchip Technology Inc.
Advance Information
DS41303B-page 229
PIC18F2XK20/4XK20
18.1.1.5
TSR Status
18.1.1.7
Asynchronous Transmission Set-up:
The TRMT bit of the TXSTA register indicates the
status of the TSR register. This is a read-only bit. The
TRMT bit is set when the TSR register is empty and is
cleared when a character is transferred to the TSR
register from the TXREG. The TRMT bit remains clear
until all bits have been shifted out of the TSR register.
No interrupt logic is tied to this bit, so the user needs to
poll this bit to determine the TSR status.
1. Initialize the SPBRGH:SPBRG register pair and
the BRGH and BRG16 bits to achieve the desired
baud rate (see Section 18.3 “EUSART Baud
Rate Generator (BRG)”).
2. Enable the asynchronous serial port by clearing
the SYNC bit and setting the SPEN bit.
3. If 9-bit transmission is desired, set the TX9 con-
trol bit. A set ninth data bit will indicate that the 8
Least Significant data bits are an address when
the receiver is set for address detection.
Note:
The TSR register is not mapped in data
memory, so it is not available to the user.
4. Set the CKTXP control bit if inverted transmit
data polarity is desired.
18.1.1.6
Transmitting 9-Bit Characters
The EUSART supports 9-bit character transmissions.
When the TX9 bit of the TXSTA register is set the
EUSART will shift 9 bits out for each character transmit-
ted. The TX9D bit of the TXSTA register is the ninth,
and Most Significant, data bit. When transmitting 9-bit
data, the TX9D data bit must be written before writing
the 8 Least Significant bits into the TXREG. All nine bits
of data will be transferred to the TSR shift register
immediately after the TXREG is written.
5. Enable the transmission by setting the TXEN
control bit. This will cause the TXIF interrupt bit
to be set.
6. If interrupts are desired, set the TXIE interrupt
enable bit. An interrupt will occur immediately
provided that the GIE and PEIE bits of the
INTCON register are also set.
7. If 9-bit transmission is selected, the ninth bit
should be loaded into the TX9D data bit.
A special 9-bit Address mode is available for use with
multiple receivers. See Section 18.1.2.8 “Address
Detection” for more information on the Address mode.
8. Load 8-bit data into the TXREG register. This
will start the transmission.
FIGURE 18-3:
ASYNCHRONOUS TRANSMISSION
Write to TXREG
Word 1
BRG Output
(Shift Clock)
RC4/C2OUT/TX/CK
pin
Start bit
bit 0
bit 1
Word 1
bit 7/8
Stop bit
TXIF bit
(Transmit Buffer
Reg. Empty Flag)
1 TCY
Word 1
Transmit Shift Reg
TRMT bit
(Transmit Shift
Reg. Empty Flag)
DS41303B-page 230
Advance Information
© 2007 Microchip Technology Inc.
PIC18F2XK20/4XK20
FIGURE 18-4:
ASYNCHRONOUS TRANSMISSION (BACK-TO-BACK)
Write to TXREG
Word 2
Start bit
Word 1
BRG Output
(Shift Clock)
RC4/C2OUT/TX/CK
pin
Start bit
Word 2
bit 0
bit 1
bit 7/8
bit 0
Stop bit
Word 2
1 TCY
Word 1
TXIF bit
(Interrupt Reg. Flag)
1 TCY
TRMT bit
(Transmit Shift
Reg. Empty Flag)
Word 1
Transmit Shift Reg
Transmit Shift Reg
Note:
This timing diagram shows two consecutive transmissions.
TABLE 18-1: REGISTERS ASSOCIATED WITH ASYNCHRONOUS TRANSMISSION
Reset
Values
on page
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
INTCON
PIR1
GIE/GIEH PEIE/GIEL TMR0IE
INT0IE
TXIF
RBIE
SSPIF
SSPIE
SSPIP
ADDEN
TMR0IF
CCP1IF
INT0IF
RBIF
57
60
60
60
59
59
59
59
59
59
PSPIF(1)
PSPIE(1)
PSPIP(1)
SPEN
ADIF
ADIE
ADIP
RX9
RCIF
RCIE
RCIP
SREN
TMR2IF
TMR1IF
PIE1
TXIE
CCP1IE TMR2IE TMR1IE
CCP1IP TMR2IP TMR1IP
IPR1
TXIP
RCSTA
TXREG
TXSTA
BAUDCTL
SPBRGH
SPBRG
CREN
FERR
OERR
RX9D
EUSART Transmit Register
CSRC
TX9
TXEN
SYNC
SENDB
BRG16
BRGH
—
TRMT
WUE
TX9D
ABDOVF
RCIDL
DTRXP
CKTXP
ABDEN
EUSART Baud Rate Generator Register, High Byte
EUSART Baud Rate Generator Register, Low Byte
Legend: — = unimplemented locations read as ‘0’. Shaded cells are not used for asynchronous transmission.
Note 1: Reserved in PIC18F2XK20 devices; always maintain these bits clear.
© 2007 Microchip Technology Inc.
Advance Information
DS41303B-page 231
PIC18F2XK20/4XK20
18.1.2
EUSART ASYNCHRONOUS
RECEIVER
18.1.2.2
Receiving Data
The receiver data recovery circuit initiates character
reception on the falling edge of the first bit. The first bit,
also known as the Start bit, is always a zero. The data
recovery circuit counts one-half bit time to the center of
the Start bit and verifies that the bit is still a zero. If it is
not a zero then the data recovery circuit aborts
character reception, without generating an error, and
resumes looking for the falling edge of the Start bit. If
the Start bit zero verification succeeds then the data
recovery circuit counts a full bit time to the center of the
next bit. The bit is then sampled by a majority detect
circuit and the resulting ‘0’ or ‘1’ is shifted into the RSR.
This repeats until all data bits have been sampled and
shifted into the RSR. One final bit time is measured and
the level sampled. This is the Stop bit, which is always
a ‘1’. If the data recovery circuit samples a ‘0’ in the
Stop bit position then a framing error is set for this
character, otherwise the framing error is cleared for this
character. See Section 18.1.2.5 “Receive Framing
Error” for more information on framing errors.
The Asynchronous mode would typically be used in
RS-232 systems. The receiver block diagram is shown
in Figure 18-2. The data is received on the RX/DT pin
and drives the data recovery block. The data recovery
block is actually a high-speed shifter operating at 16
times the baud rate, whereas the serial Receive Shift
Register (RSR) operates at the bit rate. When all 8 or 9
bits of the character have been shifted in, they are
immediately transferred to
a
two character
First-In-First-Out (FIFO) memory. The FIFO buffering
allows reception of two complete characters and the
start of a third character before software must start
servicing the EUSART receiver. The FIFO and RSR
registers are not directly accessible by software.
Access to the received data is via the RCREG register.
18.1.2.1
Enabling the Receiver
The EUSART receiver is enabled for asynchronous
operation by configuring the following three control bits:
Immediately after all data bits and the Stop bit have
been received, the character in the RSR is transferred
to the EUSART receive FIFO and the RCIF interrupt
flag bit of the PIR1 register is set. The top character in
the FIFO is transferred out of the FIFO by reading the
RCREG register.
• CREN = 1
• SYNC = 0
• SPEN = 1
All other EUSART control bits are assumed to be in
their default state.
Setting the CREN bit of the RCSTA register enables the
receiver circuitry of the EUSART. Clearing the SYNC bit
of the TXSTA register configures the EUSART for
asynchronous operation. Setting the SPEN bit of the
RCSTA register enables the EUSART. The RX/DT I/O
pin must be configured as an input by setting the
corresponding TRIS control bit. If the RX/DT pin is
shared with an analog peripheral the analog I/O function
must be disabled by clearing the corresponding ANSEL
bit.
Note:
If the receive FIFO is overrun, no additional
characters will be received until the overrun
condition is cleared. See Section 18.1.2.6
“Receive Overrun Error” for more
information on overrun errors.
18.1.2.3
Receive Data Polarity
The polarity of the receive data can be controlled with
the DTRXP bit of the BAUDCTL register. The default
state of this bit is ‘0’ which selects high true receive idle
and data bits. Setting the DTRXP bit to ‘1’ will invert the
receive data resulting in low true idle and data bits. The
DTRXP bit controls receive data polarity only in Asyn-
chronous mode. In synchronous mode the DTRXP bit
has a different function.
Note:
When the SPEN bit is set the TX/CK I/O
pin is automatically configured as an
output, regardless of the state of the
corresponding TRIS bit and whether or not
the EUSART transmitter is enabled. The
PORT latch is disconnected from the
output driver so it is not possible to use the
TX/CK pin as a general purpose output.
DS41303B-page 232
Advance Information
© 2007 Microchip Technology Inc.
PIC18F2XK20/4XK20
18.1.2.4
Receive Interrupts
18.1.2.7
Receiving 9-bit Characters
The RCIF interrupt flag bit of the PIR1 register is set
whenever the EUSART receiver is enabled and there is
an unread character in the receive FIFO. The RCIF
interrupt flag bit is read-only, it cannot be set or cleared
by software.
The EUSART supports 9-bit character reception. When
the RX9 bit of the RCSTA register is set, the EUSART
will shift 9 bits into the RSR for each character
received. The RX9D bit of the RCSTA register is the
ninth and Most Significant data bit of the top unread
character in the receive FIFO. When reading 9-bit data
from the receive FIFO buffer, the RX9D data bit must
be read before reading the 8 Least Significant bits from
the RCREG.
RCIF interrupts are enabled by setting the following
bits:
• RCIE interrupt enable bit of the PIE1 register
• PEIE peripheral interrupt enable bit of the
INTCON register
18.1.2.8
Address Detection
• GIE global interrupt enable bit of the INTCON
register
A special Address Detection mode is available for use
when multiple receivers share the same transmission
line, such as in RS-485 systems. Address detection is
enabled by setting the ADDEN bit of the RCSTA
register.
The RCIF interrupt flag bit will be set when there is an
unread character in the FIFO, regardless of the state of
interrupt enable bits.
Address detection requires 9-bit character reception.
When address detection is enabled, only characters
with the ninth data bit set will be transferred to the
receive FIFO buffer, thereby setting the RCIF interrupt
bit. All other characters will be ignored.
18.1.2.5
Receive Framing Error
Each character in the receive FIFO buffer has a
corresponding framing error Status bit. A framing error
indicates that a Stop bit was not seen at the expected
time. The framing error status is accessed via the
FERR bit of the RCSTA register. The FERR bit
represents the status of the top unread character in the
receive FIFO. Therefore, the FERR bit must be read
before reading the RCREG.
Upon receiving an address character, user software
determines if the address matches its own. Upon
address match, user software must disable address
detection by clearing the ADDEN bit before the next
Stop bit occurs. When user software detects the end of
the message, determined by the message protocol
used, software places the receiver back into the
Address Detection mode by setting the ADDEN bit.
The FERR bit is read-only and only applies to the top
unread character in the receive FIFO. A framing error
(FERR = 1) does not preclude reception of additional
characters. It is not necessary to clear the FERR bit.
Reading the next character from the FIFO buffer will
advance the FIFO to the next character and the next
corresponding framing error.
The FERR bit can be forced clear by clearing the SPEN
bit of the RCSTA register which resets the EUSART.
Clearing the CREN bit of the RCSTA register does not
affect the FERR bit. A framing error by itself does not
generate an interrupt.
Note:
If all receive characters in the receive
FIFO have framing errors, repeated reads
of the RCREG will not clear the FERR bit.
18.1.2.6
Receive Overrun Error
The receive FIFO buffer can hold two characters. An
overrun error will be generated If a third character, in its
entirety, is received before the FIFO is accessed. When
this happens the OERR bit of the RCSTA register is set.
The characters already in the FIFO buffer can be read
but no additional characters will be received until the
error is cleared. The error must be cleared by either
clearing the CREN bit of the RCSTA register or by
resetting the EUSART by clearing the SPEN bit of the
RCSTA register.
© 2007 Microchip Technology Inc.
Advance Information
DS41303B-page 233
PIC18F2XK20/4XK20
18.1.2.9
Asynchronous Reception Set-up:
18.1.2.10 9-bit Address Detection Mode Set-up
1. Initialize the SPBRGH:SPBRG register pair and
the BRGH and BRG16 bits to achieve the
desired baud rate (see Section 18.3 “EUSART
Baud Rate Generator (BRG)”).
This mode would typically be used in RS-485 systems.
To set up an Asynchronous Reception with Address
Detect Enable:
1. Initialize the SPBRGH, SPBRG register pair and
the BRGH and BRG16 bits to achieve the
desired baud rate (see Section 18.3 “EUSART
Baud Rate Generator (BRG)”).
2. Enable the serial port by setting the SPEN bit
and the RX/DT pin TRIS bit. The SYNC bit must
be clear for asynchronous operation.
3. If interrupts are desired, set the RCIE interrupt
enable bit and set the GIE and PEIE bits of the
INTCON register.
2. Enable the serial port by setting the SPEN bit.
The SYNC bit must be clear for asynchronous
operation.
4. If 9-bit reception is desired, set the RX9 bit.
3. If interrupts are desired, set the RCIE interrupt
enable bit and set the GIE and PEIE bits of the
INTCON register.
5. Set the DTRXP if inverted receive polarity is
desired.
6. Enable reception by setting the CREN bit.
4. Enable 9-bit reception by setting the RX9 bit.
7. The RCIF interrupt flag bit will be set when a
character is transferred from the RSR to the
receive buffer. An interrupt will be generated if
the RCIE interrupt enable bit was also set.
5. Enable address detection by setting the ADDEN
bit.
6. Set the DTRXP if inverted receive polarity is
desired.
8. Read the RCSTA register to get the error flags
and, if 9-bit data reception is enabled, the ninth
data bit.
7. Enable reception by setting the CREN bit.
8. The RCIF interrupt flag bit will be set when a
character with the ninth bit set is transferred
from the RSR to the receive buffer. An interrupt
will be generated if the RCIE interrupt enable bit
was also set.
9. Get the received 8 Least Significant data bits
from the receive buffer by reading the RCREG
register.
10. If an overrun occurred, clear the OERR flag by
clearing the CREN receiver enable bit.
9. Read the RCSTA register to get the error flags.
The ninth data bit will always be set.
10. Get the received 8 Least Significant data bits
from the receive buffer by reading the RCREG
register. Software determines if this is the
device’s address.
11. If an overrun occurred, clear the OERR flag by
clearing the CREN receiver enable bit.
12. If the device has been addressed, clear the
ADDEN bit to allow all received data into the
receive buffer and generate interrupts.
FIGURE 18-5:
ASYNCHRONOUS RECEPTION
Start
bit
Start
bit
Start
bit
RX/DT pin
bit 7/8
bit 7/8
bit 0 bit 1
Stop
bit
Stop
bit
Stop
bit
bit 0
bit 7/8
Rcv Shift
Reg
Rcv Buffer Reg
Word 2
RCREG
Word 1
RCREG
RCIDL
Read Rcv
Buffer Reg
RCREG
RCIF
(Interrupt Flag)
OERR bit
CREN
Note:
This timing diagram shows three words appearing on the RX input. The RCREG (receive buffer) is read after the third word,
causing the OERR (overrun) bit to be set.
DS41303B-page 234
Advance Information
© 2007 Microchip Technology Inc.
PIC18F2XK20/4XK20
TABLE 18-2: REGISTERS ASSOCIATED WITH ASYNCHRONOUS RECEPTION
Reset
Values
on page
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
INTCON
PIR1
GIE/GIEH PEIE/GIEL TMR0IE
INT0IE
TXIF
RBIE
SSPIF
SSPIE
SSPIP
ADDEN
TMR0IF
INT0IF
RBIF
57
60
60
60
59
59
60
59
59
59
59
PSPIF(1)
PSPIE(1)
PSPIP(1)
SPEN
ADIF
ADIE
ADIP
RX9
RCIF
RCIE
RCIP
SREN
CCP1IF TMR2IF TMR1IF
CCP1IE TMR2IE TMR1IE
CCP1IP TMR2IP TMR1IP
PIE1
TXIE
IPR1
TXIP
RCSTA
RCREG
TRISC
TXSTA
BAUDCTL
SPBRGH
SPBRG
CREN
FERR
OERR
RX9D
EUSART Receive Register
TRISC7
CSRC
TRISC6
TX9
TRISC5
TXEN
TRISC4
SYNC
TRISC3
SENDB
BRG16
TRISC2
BRGH
—
TRISC1 TRISC0
TRMT
WUE
TX9D
ABDOVF
RCIDL
DTRXP
CKTXP
ABDEN
EUSART Baud Rate Generator Register, High Byte
EUSART Baud Rate Generator Register, Low Byte
Legend: — = unimplemented locations read as ‘0’. Shaded cells are not used for asynchronous reception.
Note 1: Reserved in PIC18F2XK20 devices; always maintain these bits clear.
© 2007 Microchip Technology Inc.
Advance Information
DS41303B-page 235
PIC18F2XK20/4XK20
The first (preferred) method uses the OSCTUNE
register to adjust the HFINTOSC output. Adjusting the
value in the OSCTUNE register allows for fine resolution
changes to the system clock source. See Section 2.5
“Internal Clock Modes” for more information.
18.2 Clock Accuracy with
Asynchronous Operation
The factory calibrates the internal oscillator block out-
put (HFINTOSC). However, the HFINTOSC frequency
may drift as VDD or temperature changes, and this
directly affects the asynchronous baud rate. Two meth-
ods may be used to adjust the baud rate clock, but both
require a reference clock source of some kind.
The other method adjusts the value in the Baud Rate
Generator. This can be done automatically with the
Auto-Baud Detect feature (see Section 18.3.1
“Auto-Baud Detect”). There may not be fine enough
resolution when adjusting the Baud Rate Generator to
compensate for a gradual change in the peripheral
clock frequency.
REGISTER 18-1: TXSTA: TRANSMIT STATUS AND CONTROL REGISTER
R/W-0
CSRC
R/W-0
TX9
R/W-0
R/W-0
SYNC
R/W-0
R/W-0
BRGH
R-1
R/W-0
TX9D
(1)
TXEN
SENDB
TRMT
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7
CSRC: Clock Source Select bit
Asynchronous mode:
Don’t care
Synchronous mode:
1= Master mode (clock generated internally from BRG)
0= Slave mode (clock from external source)
bit 6
bit 5
bit 4
bit 3
TX9: 9-bit Transmit Enable bit
1= Selects 9-bit transmission
0= Selects 8-bit transmission
(1)
TXEN: Transmit Enable bit
1= Transmit enabled
0= Transmit disabled
SYNC: EUSART Mode Select bit
1= Synchronous mode
0= Asynchronous mode
SENDB: Send Break Character bit
Asynchronous mode:
1= Send Sync Break on next transmission (cleared by hardware upon completion)
0= Sync Break transmission completed
Synchronous mode:
Don’t care
bit 2
BRGH: High Baud Rate Select bit
Asynchronous mode:
1= High speed
0= Low speed
Synchronous mode:
Unused in this mode
bit 1
bit 0
TRMT: Transmit Shift Register Status bit
1= TSR empty
0= TSR full
TX9D: Ninth bit of Transmit Data
Can be address/data bit or a parity bit.
Note 1: SREN/CREN overrides TXEN in Sync mode.
DS41303B-page 236
Advance Information
© 2007 Microchip Technology Inc.
PIC18F2XK20/4XK20
REGISTER 18-2: RCSTA: RECEIVE STATUS AND CONTROL REGISTER(1)
R/W-0
SPEN
R/W-0
RX9
R/W-0
SREN
R/W-0
CREN
R/W-0
R-0
R-0
R-x
ADDEN
FERR
OERR
RX9D
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7
bit 6
bit 5
SPEN: Serial Port Enable bit
1= Serial port enabled (configures RX/DT and TX/CK pins as serial port pins)
0= Serial port disabled (held in Reset)
RX9: 9-bit Receive Enable bit
1= Selects 9-bit reception
0= Selects 8-bit reception
SREN: Single Receive Enable bit
Asynchronous mode:
Don’t care
Synchronous mode – Master:
1= Enables single receive
0= Disables single receive
This bit is cleared after reception is complete.
Synchronous mode – Slave
Don’t care
bit 4
CREN: Continuous Receive Enable bit
Asynchronous mode:
1= Enables receiver
0= Disables receiver
Synchronous mode:
1= Enables continuous receive until enable bit CREN is cleared (CREN overrides SREN)
0= Disables continuous receive
bit 3
ADDEN: Address Detect Enable bit
Asynchronous mode 9-bit (RX9 = 1):
1= Enables address detection, enable interrupt and load the receive buffer when RSR<8> is set
0= Disables address detection, all bytes are received and ninth bit can be used as parity bit
Asynchronous mode 8-bit (RX9 = 0):
Don’t care
bit 2
bit 1
bit 0
FERR: Framing Error bit
1= Framing error (can be updated by reading RCREG register and receive next valid byte)
0= No framing error
OERR: Overrun Error bit
1= Overrun error (can be cleared by clearing bit CREN)
0= No overrun error
RX9D: Ninth bit of Received Data
This can be address/data bit or a parity bit and must be calculated by user firmware.
© 2007 Microchip Technology Inc.
Advance Information
DS41303B-page 237
PIC18F2XK20/4XK20
REGISTER 18-3: BAUDCTL: BAUD RATE CONTROL REGISTER
R-0
R-1
R/W-0
R/W-0
R/W-0
U-0
—
R/W-0
WUE
R/W-0
ABDOVF
RCIDL
DTRXP
CKTXP
BRG16
ABDEN
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7
bit 6
bit 5
ABDOVF: Auto-Baud Detect Overflow bit
Asynchronous mode:
1= Auto-baud timer overflowed
0= Auto-baud timer did not overflow
Synchronous mode:
Don’t care
RCIDL: Receive Idle Flag bit
Asynchronous mode:
1= Receiver is Idle
0= Start bit has been detected and the receiver is active
Synchronous mode:
Don’t care
DTRXP: Data/Receive Polarity Select bit
Asynchronous mode:
1= Receive data (RX) is inverted (active-low)
0= Receive data (RX) is not inverted (active-high)
Synchronous mode:
1= Data (DT) is inverted (active-low)
0= Data (DT) is not inverted (active-high)
bit 4
CKTXP: Clock/Transmit Polarity Select bit
Asynchronous mode:
1= Idle state for transmit (TX) is low
0= Idle state for transmit (TX) is high
Synchronous mode:
1= Data changes on the falling edge of the clock and is sampled on the rising edge of the clock
0= Data changes on the rising edge of the clock and is sampled on the falling edge of the clock
bit 3
BRG16: 16-bit Baud Rate Generator bit
1= 16-bit Baud Rate Generator is used (SPBRGH:SPBRG)
0= 8-bit Baud Rate Generator is used (SPBRG)
bit 2
bit 1
Unimplemented: Read as ‘0’
WUE: Wake-up Enable bit
Asynchronous mode:
1= Receiver is waiting for a falling edge. No character will be received but RCIF will be set on the falling
edge. WUE will automatically clear on the rising edge.
0= Receiver is operating normally
Synchronous mode:
Don’t care
bit 0
ABDEN: Auto-Baud Detect Enable bit
Asynchronous mode:
1= Auto-Baud Detect mode is enabled (clears when auto-baud is complete)
0= Auto-Baud Detect mode is disabled
Synchronous mode:
Don’t care
DS41303B-page 238
Advance Information
© 2007 Microchip Technology Inc.
PIC18F2XK20/4XK20
If the system clock is changed during an active receive
operation, a receive error or data loss may result. To
avoid this problem, check the status of the RCIDL bit to
make sure that the receive operation is Idle before
changing the system clock.
18.3 EUSART Baud Rate Generator
(BRG)
The Baud Rate Generator (BRG) is an 8-bit or 16-bit
timer that is dedicated to the support of both the
asynchronous and synchronous EUSART operation.
By default, the BRG operates in 8-bit mode. Setting the
BRG16 bit of the BAUDCTL register selects 16-bit
mode.
EXAMPLE 18-1:
CALCULATING BAUD
RATE ERROR
For a device with FOSC of 16 MHz, desired baud rate
of 9600, Asynchronous mode, 8-bit BRG:
The SPBRGH:SPBRG register pair determines the
period of the free running baud rate timer. In
Asynchronous mode the multiplier of the baud rate
period is determined by both the BRGH bit of the TXSTA
register and the BRG16 bit of the BAUDCTL register. In
Synchronous mode, the BRGH bit is ignored.
FOSC
--------------------------------------------------------------------
=
Desired Baud Rate
64([SPBRGH:SPBRG] + 1)
Solving for SPBRGH:SPBRG:
FOSC
---------------------------------------------
Table 18-3 contains the formulas for determining the
baud rate. Example 18-1 provides a sample calculation
for determining the baud rate and baud rate error.
Desired Baud Rate
---------------------------------------------
X =
=
– 1
64
16000000
-----------------------
9600
64
Typical baud rates and error values for various
asynchronous modes have been computed for your
convenience and are shown in Table 18-5. It may be
advantageous to use the high baud rate (BRGH = 1),
or the 16-bit BRG (BRG16 = 1) to reduce the baud rate
error. The 16-bit BRG mode is used to achieve slow
baud rates for fast oscillator frequencies.
-----------------------
– 1
= [25.042] = 25
16000000
64(25 + 1)
--------------------------
=
Calculated Baud Rate
= 9615
Writing a new value to the SPBRGH, SPBRG register
pair causes the BRG timer to be reset (or cleared). This
ensures that the BRG does not wait for a timer overflow
before outputting the new baud rate.
Calc. Baud Rate – Desired Baud Rate
--------------------------------------------------------------------------------------------
Error =
Desired Baud Rate
(9615 – 9600)
----------------------------------
=
= 0.16%
9600
TABLE 18-3: BAUD RATE FORMULAS
Configuration Bits
Baud Rate Formula
BRG/EUSART Mode
SYNC
BRG16
BRGH
0
0
0
0
1
1
0
0
1
1
0
1
0
1
0
1
x
x
8-bit/Asynchronous
8-bit/Asynchronous
16-bit/Asynchronous
16-bit/Asynchronous
8-bit/Synchronous
16-bit/Synchronous
FOSC/[64 (n+1)]
FOSC/[16 (n+1)]
FOSC/[4 (n+1)]
Legend:
x= Don’t care, n = value of SPBRGH, SPBRG register pair
TABLE 18-4: REGISTERS ASSOCIATED WITH BAUD RATE GENERATOR
Reset Values
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
on page
TXSTA
RCSTA
CSRC
SPEN
TX9
RX9
TXEN
SREN
SYNC
CREN
CKTXP
SENDB
ADDEN
BRG16
BRGH
FERR
—
TRMT
OERR
WUE
TX9D
RX9D
59
59
59
59
59
BAUDCTL ABDOVF RCIDL
DTRXP
ABDEN
SPBRGH EUSART Baud Rate Generator Register, High Byte
SPBRG EUSART Baud Rate Generator Register, Low Byte
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the BRG.
© 2007 Microchip Technology Inc.
Advance Information
DS41303B-page 239
PIC18F2XK20/4XK20
TABLE 18-5: BAUD RATES FOR ASYNCHRONOUS MODES
SYNC = 0, BRGH = 0, BRG16 = 0
FOSC = 64.000 MHz
FOSC = 18.432 MHz
FOSC = 16.000 MHz
FOSC = 11.0592 MHz
BAUD
RATE
SPBRG
SPBRG
SPBRG
SPBRG
Actual
Rate
%
Actual
Rate
%
Actual
Rate
%
Actual
Rate
%
value
(decimal)
value
(decimal)
value
(decimal)
value
(decimal)
Error
Error
Error
Error
300
1200
2400
9600
10417
19.2k
57.6k
—
—
—
—
—
—
—
—
—
239
119
29
—
1202
2404
9615
10417
19.23k
—
—
—
207
103
25
—
—
—
143
71
17
16
8
1200
2400
9600
10286
19.20k
0.00
0.00
0.00
-1.26
0.00
0.00
—
0.16
0.16
0.16
0.00
0.16
—
1200
2400
9600
10165
19.20k
0.00
0.00
0.00
-2.42
0.00
0.00
—
—
—
—
9615
10417
19.23k
0.16
0.00
0.16
103
95
51
27
23
14
12
—
2
58.82k
2.12
16
8
57.60k
—
7
57.60k
—
115.2k 111.11k -3.55
—
—
—
—
—
SYNC = 0, BRGH = 0, BRG16 = 0
FOSC = 4.000 MHz FOSC = 3.6864 MHz
FOSC = 8.000 MHz
FOSC = 1.000 MHz
BAUD
RATE
SPBRG
value
SPBRG
value
SPBRG
value
SPBRG
Actual
Rate
%
Error
Actual
Rate
%
Error
Actual
Rate
%
Error
Actual
Rate
%
value
(decimal)
Error
(decimal)
(decimal)
(decimal)
0.00
0.00
0.00
0.00
—
300
1200
—
1202
2404
9615
10417
—
—
0.16
0.16
0.16
0.00
—
—
103
51
12
11
300
1202
2404
—
0.16
0.16
0.16
—
207
51
25
—
5
300
1200
2400
9600
—
191
47
23
5
300
1202
—
0.16
0.16
—
51
12
—
—
—
—
—
—
2400
9600
—
—
10417
19.2k
57.6k
115.2k
10417
—
0.00
—
—
2
—
—
—
—
—
—
19.20k
0.00
0.00
—
—
—
—
—
—
—
—
0
—
—
57.60k
—
—
—
—
—
—
—
—
—
SYNC = 0, BRGH = 1, BRG16 = 0
FOSC = 18.432 MHz FOSC = 16.000 MHz
FOSC = 64.000 MHz
FOSC = 11.0592 MHz
BAUD
RATE
SPBRG
SPBRG
value
SPBRG
value
SPBRG
Actual
Rate
%
Actual
Rate
%
Error
Actual
Rate
%
Error
Actual
Rate
%
value
(decimal)
value
(decimal)
Error
Error
(decimal)
(decimal)
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
300
1200
2400
9600
10417
19.2k
57.6k
—
—
—
—
—
—
—
—
—
—
103
95
51
16
8
—
—
—
71
65
35
11
5
—
—
—
9600
10378
19.20k
57.60k
115.2k
0.00
-0.37
0.00
0.00
0.00
119
110
59
19
9
9615
0.16
0.00
0.16
2.12
-3.55
9600
0.00
0.53
0.00
0.00
0.00
—
—
—
10417
19.23k
58.82k
111.1k
10473
19.20k
57.60k
115.2k
19.23k
57.97k
0.16
0.64
207
68
34
115.2k 114.29k -0.79
DS41303B-page 240
Advance Information
© 2007 Microchip Technology Inc.
PIC18F2XK20/4XK20
TABLE 18-5: BAUD RATES FOR ASYNCHRONOUS MODES (CONTINUED)
SYNC = 0, BRGH = 1, BRG16 = 0
FOSC = 4.000 MHz FOSC = 3.6864 MHz
FOSC = 8.000 MHz
FOSC = 1.000 MHz
BAUD
RATE
SPBRG
SPBRG
value
SPBRG
value
SPBRG
Actual
Rate
%
Actual
Rate
%
Error
Actual
Rate
%
Error
Actual
Rate
%
value
(decimal)
value
(decimal)
Error
Error
(decimal)
(decimal)
—
—
—
—
—
—
300
1200
—
1202
2404
9615
10417
19.23k
—
—
—
207
103
25
—
—
—
191
95
23
21
11
3
300
1202
2404
—
0.16
0.16
0.16
—
207
51
25
—
5
0.16
0.16
0.16
0.00
0.16
—
1200
0.00
0.00
0.00
0.53
0.00
0.00
0.00
2400
2404
9615
10417
19231
55556
—
0.16
0.16
0.00
0.16
-3.55
—
207
51
47
25
8
2400
9600
9600
10417
19.2k
57.6k
115.2k
23
10473
19.2k
57.60k
115.2k
10417
—
0.00
—
12
—
—
—
—
—
—
—
—
—
—
1
—
—
SYNC = 0, BRGH = 0, BRG16 = 1
FOSC = 18.432 MHz FOSC = 16.000 MHz
FOSC = 64.000 MHz
FOSC = 11.0592 MHz
BAUD
RATE
SPBRGH
SPBRGH
:SPBRG
(decimal)
SPBRGH
:SPBRG
(decimal)
SPBRGH
Actual
Rate
%
Actual
Rate
%
Error
Actual
Rate
%
Error
Actual
Rate
%
:SPBRG
(decimal)
:SPBRG
(decimal)
Error
Error
300
1200
2400
9600
10417
19.2k
57.6k
300.0
1200.1
2399
0.00
0.01
-0.02
-0.08
0.00
0.16
0.64
13332
3332
1666
416
383
207
68
300.0
1200
0.00
0.00
0.00
0.00
-0.37
0.00
0.00
0.00
3839
959
479
119
110
59
300.03
1200.5
2398
0.01
0.04
-0.08
0.16
0.00
0.16
2.12
3332
832
416
103
95
300.0
1200
0.00
0.00
0.00
0.00
0.53
0.00
0.00
0.00
2303
575
287
71
2400
2400
9592
9600
9615
9600
10417
19.23k
57.97k
10378
19.20k
57.60k
115.2k
10417
19.23k
58.82k
10473
19.20k
57.60k
115.2k
65
51
35
19
16
11
115.2k 114.29k -0.79
34
9
111.11k -3.55
8
5
SYNC = 0, BRGH = 0, BRG16 = 1
FOSC = 4.000 MHz FOSC = 3.6864 MHz
FOSC = 8.000 MHz
FOSC = 1.000 MHz
BAUD
RATE
SPBRGH
:SPBRG
(decimal)
SPBRGH
:SPBRG
(decimal)
SPBRGH
:SPBRG
(decimal)
SPBRGH
Actual
Rate
%
Error
Actual
Rate
%
Error
Actual
Rate
%
Error
Actual
Rate
%
:SPBRG
(decimal)
Error
300
1200
299.9
1199
-0.02
-0.08
0.16
0.16
0.00
0.16
-3.55
—
1666
416
207
51
300.1
1202
2404
9615
10417
19.23k
—
0.04
0.16
0.16
0.16
0.00
0.16
—
832
207
103
25
300.0
1200
0.00
0.00
0.00
0.00
0.53
0.00
0.00
0.00
767
191
95
23
21
11
3
300.5
1202
2404
—
0.16
0.16
0.16
—
207
51
25
—
5
2400
2404
9615
10417
19.23k
55556
—
2400
9600
9600
10417
19.2k
57.6k
115.2k
47
23
10473
19.20k
57.60k
115.2k
10417
—
0.00
—
25
12
—
—
—
8
—
—
—
—
—
—
—
1
—
—
© 2007 Microchip Technology Inc.
Advance Information
DS41303B-page 241
PIC18F2XK20/4XK20
TABLE 18-5: BAUD RATES FOR ASYNCHRONOUS MODES (CONTINUED)
SYNC = 0, BRGH = 1, BRG16 = 1 or SYNC = 1, BRG16 = 1
FOSC = 64.000 MHz
FOSC = 18.432 MHz
FOSC = 16.000 MHz
FOSC = 11.0592 MHz
BAUD
RATE
SPBRGH
SPBRGH
SPBRGH
SPBRGH
Actual
Rate
%
Actual
Rate
%
Actual
Rate
%
Actual
Rate
%
:SPBRG
(decimal)
:SPBRG
(decimal)
:SPBRG
(decimal)
:SPBRG
(decimal)
Error
Error
Error
Error
300
1200
2400
9600
10417
19.2k
57.6k
300
0.00
0.00
0.00
-0.02
0.00
0.04
-0.08
53332
13332
6666
1666
1535
832
300.0
1200
0.00
0.00
0.00
0.00
0.08
0.00
0.00
0.00
15359
3839
1919
479
441
239
79
300.0
1200.1
2399.5
9592
0.00
0.01
-0.02
-0.08
0.00
0.16
0.64
13332
3332
1666
416
383
207
68
300.0
1200
0.00
0.00
0.00
0.00
0.16
0.00
0.00
0.00
9215
2303
1151
287
264
143
47
1200
2400
2400
2400
9598.1
10417
19.21k
57.55k
9600
9600
10425
19.20k
57.60k
115.2k
10417
19.23k
57.97k
10433
19.20k
57.60k
115.2k
277
115.2k 115.11k -0.08
138
39
114.29k -0.79
34
23
SYNC = 0, BRGH = 1, BRG16 = 1 or SYNC = 1, BRG16 = 1
FOSC = 4.000 MHz FOSC = 3.6864 MHz
FOSC = 8.000 MHz
FOSC = 1.000 MHz
BAUD
RATE
SPBRGH
:SPBRG
(decimal)
SPBRGH
SPBRGH
SPBRGH
Actual
Rate
%
Error
Actual
Rate
%
Actual
Rate
%
Actual
Rate
%
:SPBRG
(decimal)
:SPBRG
(decimal)
:SPBRG
(decimal)
Error
Error
Error
300
1200
300.0
1200
0.00
-0.02
0.04
0.16
0.00
0.16
-0.79
2.12
6666
1666
832
207
191
103
34
300.0
1200
0.01
0.04
0.08
0.16
0.00
0.16
2.12
-3.55
3332
832
416
103
95
300.0
1200
0.00
0.00
0.00
0.00
0.53
0.00
0.00
0.00
3071
767
383
95
300.1
1202
2404
9615
10417
19.23k
—
0.04
0.16
0.16
0.16
0.00
0.16
—
832
207
103
25
2400
2401
2398
2400
9600
9615
9615
9600
10417
19.2k
57.6k
115.2k
10417
19.23k
57.14k
117.6k
10417
19.23k
58.82k
111.1k
10473
19.20k
57.60k
115.2k
87
23
51
47
12
16
15
—
16
8
7
—
—
—
DS41303B-page 242
Advance Information
© 2007 Microchip Technology Inc.
PIC18F2XK20/4XK20
and SPBRG registers are clocked at 1/8th the BRG
base clock rate. The resulting byte measurement is the
average bit time when clocked at full speed.
18.3.1
AUTO-BAUD DETECT
The EUSART module supports automatic detection
and calibration of the baud rate.
Note 1: If the WUE bit is set with the ABDEN bit,
auto-baud detection will occur on the byte
following the Break character (see
In the Auto-Baud Detect (ABD) mode, the clock to the
BRG is reversed. Rather than the BRG clocking the
incoming RX signal, the RX signal is timing the BRG.
The Baud Rate Generator is used to time the period of
a received 55h (ASCII “U”) which is the Sync character
for the LIN bus. The unique feature of this character is
that it has five rising edges including the Stop bit edge.
Section 18.3.2
“Auto-Wake-up
on
Break”).
2: It is up to the user to determine that the
incoming character baud rate is within the
range of the selected BRG clock source.
Some combinations of oscillator frequency
and EUSART baud rates are not possible.
Setting the ABDEN bit of the BAUDCTL register starts
the auto-baud calibration sequence (Figure 18-6).
While the ABD sequence takes place, the EUSART
state machine is held in Idle. On the first rising edge of
the receive line, after the Start bit, the SPBRG begins
counting up using the BRG counter clock as shown in
Table 18-6. The fifth rising edge will occur on the RX
pin at the end of the eighth bit period. At that time, an
accumulated value totaling the proper BRG period is
left in the SPBRGH:SPBRG register pair, the ABDEN
bit is automatically cleared, and the RCIF interrupt flag
is set. A read operation on the RCREG needs to be
performed to clear the RCIF interrupt. RCREG content
should be discarded. When calibrating for modes that
do not use the SPBRGH register the user can verify
that the SPBRG register did not overflow by checking
for 00h in the SPBRGH register.
3: During the auto-baud process, the
auto-baud counter starts counting at 1.
Upon completion of the auto-baud
sequence, to achieve maximum accuracy,
subtract 1 from the SPBRGH:SPBRG
register pair.
TABLE 18-6:
BRG16 BRGH
BRG COUNTER CLOCK RATES
BRG Base
Clock
BRG ABD
Clock
0
0
0
1
FOSC/64
FOSC/16
FOSC/512
FOSC/128
1
1
0
1
FOSC/16
FOSC/4
FOSC/128
FOSC/32
The BRG auto-baud clock is determined by the BRG16
and BRGH bits as shown in Table 18-6. During ABD,
both the SPBRGH and SPBRG registers are used as a
16-bit counter, independent of the BRG16 bit setting.
While calibrating the baud rate period, the SPBRGH
Note:
During the ABD sequence, SPBRG and
SPBRGH registers are both used as a 16-bit
counter, independent of BRG16 setting.
FIGURE 18-6:
AUTOMATIC BAUD RATE CALIBRATION
XXXXh
0000h
001Ch
BRG Value
Edge #1
bit 1
Edge #2
bit 3
Edge #3
bit 5
Edge #4
bit 7
bit 6
Edge #5
Stop bit
RX pin
Start
bit 0
bit 2
bit 4
BRG Clock
Auto Cleared
Set by User
ABDEN bit
RCIDL
RCIF bit
(Interrupt)
Read
RCREG
XXh
XXh
1Ch
00h
SPBRG
SPBRGH
Note 1: The ABD sequence requires the EUSART module to be configured in Asynchronous mode.
© 2007 Microchip Technology Inc.
Advance Information
DS41303B-page 243
PIC18F2XK20/4XK20
18.3.2
AUTO-WAKE-UP ON BREAK
18.3.2.1
Special Considerations
During Sleep mode, all clocks to the EUSART are
suspended. Because of this, the Baud Rate Generator
is inactive and a proper character reception cannot be
performed. The Auto-Wake-up feature allows the
controller to wake-up due to activity on the RX/DT line.
This feature is available only in Asynchronous mode.
Break Character
To avoid character errors or character fragments during
a wake-up event, the wake-up character must be all
zeros.
When the wake-up is enabled the function works
independent of the low time on the data stream. If the
WUE bit is set and a valid non-zero character is
received, the low time from the Start bit to the first rising
edge will be interpreted as the wake-up event. The
remaining bits in the character will be received as a
fragmented character and subsequent characters can
result in framing or overrun errors.
The Auto-Wake-up feature is enabled by setting the
WUE bit of the BAUDCTL register. Once set, the normal
receive sequence on RX/DT is disabled, and the
EUSART remains in an Idle state, monitoring for a
wake-up event independent of the CPU mode. A
wake-up event consists of a high-to-low transition on the
RX/DT line. (This coincides with the start of a Sync Break
or a wake-up signal character for the LIN protocol.)
Therefore, the initial character in the transmission must
be all ‘0’s. This must be 10 or more bit times, 13-bit
times recommended for LIN bus, or any number of bit
times for standard RS-232 devices.
The EUSART module generates an RCIF interrupt
coincident with the wake-up event. The interrupt is
generated synchronously to the Q clocks in normal CPU
operating modes (Figure 18-7), and asynchronously if
the device is in Sleep mode (Figure 18-8). The interrupt
condition is cleared by reading the RCREG register.
Oscillator Startup Time
Oscillator start-up time must be considered, especially
in applications using oscillators with longer start-up
intervals (i.e., LP, XT or HS/PLL mode). The Sync
Break (or wake-up signal) character must be of
sufficient length, and be followed by a sufficient
interval, to allow enough time for the selected oscillator
to start and provide proper initialization of the EUSART.
The WUE bit is automatically cleared by the low-to-high
transition on the RX line at the end of the Break. This
signals to the user that the Break event is over. At this
point, the EUSART module is in Idle mode waiting to
receive the next character.
WUE Bit
The wake-up event causes a receive interrupt by
setting the RCIF bit. The WUE bit is cleared by
hardware by a rising edge on RX/DT. The interrupt
condition is then cleared by software by reading the
RCREG register and discarding its contents.
To ensure that no actual data is lost, check the RCIDL
bit to verify that a receive operation is not in process
before setting the WUE bit. If a receive operation is not
occurring, the WUE bit may then be set just prior to
entering the Sleep mode.
FIGURE 18-7:
AUTO-WAKE-UP BIT (WUE) TIMING DURING NORMAL OPERATION
Q1 Q2 Q3 Q4 Q1 Q2 Q3Q4 Q1Q2 Q3 Q4 Q1Q2 Q3 Q4 Q1Q2 Q3 Q4 Q1Q2 Q3 Q4 Q1Q2 Q3 Q4 Q1Q2 Q3Q4 Q1 Q2 Q3 Q4 Q1Q2 Q3Q4
OSC1
Auto Cleared
Bit set by user
WUE bit
RX/DT Line
RCIF
Cleared due to User Read of RCREG
Note 1: The EUSART remains in Idle while the WUE bit is set.
DS41303B-page 244
Advance Information
© 2007 Microchip Technology Inc.
PIC18F2XK20/4XK20
FIGURE 18-8:
AUTO-WAKE-UP BIT (WUE) TIMINGS DURING SLEEP
Q4
Q1Q2Q3 Q4 Q1Q2 Q3Q4 Q1Q2Q3
Q1
Q2 Q3Q4 Q1Q2Q3 Q4 Q1Q2Q3Q4 Q1Q2Q3 Q4 Q1Q2 Q3Q4
Auto Cleared
OSC1
Bit Set by User
WUE bit
RX/DT Line
Note 1
RCIF
Cleared due to User Read of RCREG
Sleep Command Executed
Sleep Ends
Note 1: If the wake-up event requires long oscillator warm-up time, the automatic clearing of the WUE bit can occur while the stposcsignal is
still active. This sequence should not depend on the presence of Q clocks.
2: The EUSART remains in Idle while the WUE bit is set.
18.3.3
BREAK CHARACTER SEQUENCE
18.3.4
RECEIVING A BREAK CHARACTER
The EUSART module has the capability of sending the
special Break character sequences that are required by
the LIN bus standard. A Break character consists of a
Start bit, followed by 12 ‘0’ bits and a Stop bit.
The Enhanced EUSART module can receive a Break
character in two ways.
The first method to detect a Break character uses the
FERR bit of the RCSTA register and the Received data
as indicated by RCREG. The Baud Rate Generator is
assumed to have been initialized to the expected baud
rate.
To send a Break character, set the SENDB and TXEN
bits of the TXSTA register. The Break character trans-
mission is then initiated by a write to the TXREG. The
value of data written to TXREG will be ignored and all
‘0’s will be transmitted.
A Break character has been received when;
• RCIF bit is set
• FERR bit is set
• RCREG = 00h
The SENDB bit is automatically reset by hardware after
the corresponding Stop bit is sent. This allows the user
to preload the transmit FIFO with the next transmit byte
following the Break character (typically, the Sync
character in the LIN specification).
The second method uses the Auto-Wake-up feature
described in Section 18.3.2 “Auto-Wake-up on
Break”. By enabling this feature, the EUSART will
sample the next two transitions on RX/DT, cause an
RCIF interrupt, and receive the next data byte followed
by another interrupt.
The TRMT bit of the TXSTA register indicates when the
transmit operation is active or Idle, just as it does during
normal transmission. See Figure 18-9 for the timing of
the Break character sequence.
Note that following a Break character, the user will
typically want to enable the Auto-Baud Detect feature.
For both methods, the user can set the ABDEN bit of
the BAUDCTL register before placing the EUSART in
Sleep mode.
18.3.3.1
Break and Sync Transmit Sequence
The following sequence will start a message frame
header made up of a Break, followed by an auto-baud
Sync byte. This sequence is typical of a LIN bus
master.
1. Configure the EUSART for the desired mode.
2. Set the TXEN and SENDB bits to enable the
Break sequence.
3. Load the TXREG with a dummy character to
initiate transmission (the value is ignored).
4. Write ‘55h’ to TXREG to load the Sync character
into the transmit FIFO buffer.
5. After the Break has been sent, the SENDB bit is
reset by hardware and the Sync character is
then transmitted.
When the TXREG becomes empty, as indicated by the
TXIF, the next data byte can be written to TXREG.
© 2007 Microchip Technology Inc.
Advance Information
DS41303B-page 245
PIC18F2XK20/4XK20
FIGURE 18-9:
SEND BREAK CHARACTER SEQUENCE
Write to TXREG
Dummy Write
BRG Output
(Shift Clock)
TX (pin)
Start bit
bit 0
bit 1
Break
bit 11
Stop bit
TXIF bit
(Transmit
interrupt Flag)
TRMT bit
(Transmit Shift
Reg. Empty Flag)
SENDB Sampled Here
Auto Cleared
SENDB
(send Break
control bit)
DS41303B-page 246
Advance Information
© 2007 Microchip Technology Inc.
PIC18F2XK20/4XK20
18.4.1.2
Clock Polarity
18.4 EUSART Synchronous Mode
A clock polarity option is provided for Microwire
compatibility. Clock polarity is selected with the CKTXP
bit of the BAUDCTL register. Setting the CKTXP bit
sets the clock Idle state as high. When the CKTXP bit
is set, the data changes on the falling edge of each
clock and is sampled on the rising edge of each clock.
Clearing the CKTXP bit sets the Idle state as low. When
the CKTXP bit is cleared, the data changes on the
rising edge of each clock and is sampled on the falling
edge of each clock.
Synchronous serial communications are typically used
in systems with a single master and one or more
slaves. The master device contains the necessary
circuitry for baud rate generation and supplies the clock
for all devices in the system. Slave devices can take
advantage of the master clock by eliminating the
internal clock generation circuitry.
There are two signal lines in Synchronous mode: a
bidirectional data line and a clock line. Slaves use the
external clock supplied by the master to shift the serial
data into and out of their respective receive and
transmit shift registers. Since the data line is
bidirectional, synchronous operation is half-duplex
only. Half-duplex refers to the fact that master and
slave devices can receive and transmit data but not
both simultaneously. The EUSART can operate as
either a master or slave device.
18.4.1.3
Synchronous Master Transmission
Data is transferred out of the device on the RX/DT pin.
The RX/DT and TX/CK pin output drivers are automat-
ically enabled when the EUSART is configured for
synchronous master transmit operation.
A transmission is initiated by writing a character to the
TXREG register. If the TSR still contains all or part of a
previous character the new character data is held in the
TXREG until the last bit of the previous character has
been transmitted. If this is the first character, or the pre-
vious character has been completely flushed from the
TSR, the data in the TXREG is immediately transferred
to the TSR. The transmission of the character com-
mences immediately following the transfer of the data
to the TSR from the TXREG.
Start and Stop bits are not used in synchronous
transmissions.
18.4.1
SYNCHRONOUS MASTER MODE
The following bits are used to configure the EUSART
for Synchronous Master operation:
• SYNC = 1
• CSRC = 1
Each data bit changes on the leading edge of the mas-
ter clock and remains valid until the subsequent leading
clock edge.
• SREN = 0(for transmit); SREN = 1(for receive)
• CREN = 0(for transmit); CREN = 1(for receive)
• SPEN = 1
Note:
The TSR register is not mapped in data
memory, so it is not available to the user.
Setting the SYNC bit of the TXSTA register configures
the device for synchronous operation. Setting the CSRC
bit of the TXSTA register configures the device as a
master. Clearing the SREN and CREN bits of the RCSTA
register ensures that the device is in the Transmit mode,
otherwise the device will be configured to receive. Setting
the SPEN bit of the RCSTA register enables the
EUSART. If the RX/DT or TX/CK pins are shared with an
analog peripheral the analog I/O functions must be
disabled by clearing the corresponding ANSEL bits.
18.4.1.4
Data Polarity
The polarity of the transmit and receive data can be
controlled with the DTRXP bit of the BAUDCTL regis-
ter. The default state of this bit is ‘0’ which selects high
true transmit and receive data. Setting the DTRXP bit
to ‘1’ will invert the data resulting in low true transmit
and receive data.
The TRIS bits corresponding to the RX/DT and TX/CK
pins should be set.
18.4.1.1
Master Clock
Synchronous data transfers use a separate clock line,
which is synchronous with the data. A device configured
as a master transmits the clock on the TX/CK line. The
TX/CK pin output driver is automatically enabled when
the EUSART is configured for synchronous transmit or
receive operation. Serial data bits change on the leading
edge to ensure they are valid at the trailing edge of each
clock. One clock cycle is generated for each data bit.
Only as many clock cycles are generated as there are
data bits.
© 2007 Microchip Technology Inc.
Advance Information
DS41303B-page 247
PIC18F2XK20/4XK20
3. Disable Receive mode by clearing bits SREN
and CREN.
18.4.1.5
Synchronous Master Transmission
Set-up:
4. Enable Transmit mode by setting the TXEN bit.
5. If 9-bit transmission is desired, set the TX9 bit.
1. Initialize the SPBRGH, SPBRG register pair and
the BRGH and BRG16 bits to achieve the
desired baud rate (see Section 18.3 “EUSART
Baud Rate Generator (BRG)”).
6. If interrupts are desired, set the TXIE, GIE and
PEIE interrupt enable bits.
2. Enable the synchronous master serial port by
setting bits SYNC, SPEN and CSRC. Set the
TRIS bits corresponding to the RX/DT and
TX/CK I/O pins.
7. If 9-bit transmission is selected, the ninth bit
should be loaded in the TX9D bit.
8. Start transmission by loading data to the TXREG
register.
FIGURE 18-10:
SYNCHRONOUS TRANSMISSION
RX/DT
pin
bit 0
bit 1
bit 2
bit 7
bit 0
bit 1
Word 2
bit 7
Word 1
TX/CK pin
(SCKP = 0)
TX/CK pin
(SCKP = 1)
Write to
TXREG Reg
Write Word 1
Write Word 2
TXIF bit
(Interrupt Flag)
TRMT bit
‘1’
‘1’
TXEN bit
Note:
Sync Master mode, SPBRG = 0, continuous transmission of two 8-bit words.
FIGURE 18-11:
SYNCHRONOUS TRANSMISSION (THROUGH TXEN)
RX/DT pin
bit 0
bit 2
bit 1
bit 6
bit 7
TX/CK pin
Write to
TXREG reg
TXIF bit
TRMT bit
TXEN bit
DS41303B-page 248
Advance Information
© 2007 Microchip Technology Inc.
PIC18F2XK20/4XK20
TABLE 18-7: REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER TRANSMISSION
Reset
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Values
on page
INTCON
PIR1
GIE/GIEH PEIE/GIEL TMR0IE
INT0IE
TXIF
RBIE
SSPIF
SSPIE
SSPIP
ADDEN
TRISC3
TMR0IF
INT0IF
RBIF
57
60
60
60
59
60
59
59
59
59
59
PSPIF(1)
PSPIE(1)
PSPIP(1)
SPEN
ADIF
ADIE
RCIF
RCIE
CCP1IF TMR2IF TMR1IF
CCP1IE TMR2IE TMR1IE
CCP1IP TMR2IP TMR1IP
PIE1
TXIE
IPR1
ADIP
RCIP
TXIP
RCSTA
TRISC
TXREG
TXSTA
BAUDCTL
SPBRGH
SPBRG
RX9
SREN
TRISC5
CREN
TRISC4
FERR
OERR
RX9D
TRISC7
TRISC6
TRISC2
TRISC1
TRISC0
EUSART Transmit Register
CSRC
TX9
TXEN
SYNC
SENDB
BRG16
BRGH
—
TRMT
WUE
TX9D
ABDOVF
RCIDL
DTRXP
CKTXP
ABDEN
EUSART Baud Rate Generator Register, High Byte
EUSART Baud Rate Generator Register, Low Byte
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used for synchronous master transmission.
Note 1: Reserved in PIC18F2XK20 devices; always maintain these bits clear.
© 2007 Microchip Technology Inc.
Advance Information
DS41303B-page 249
PIC18F2XK20/4XK20
18.4.1.6
Synchronous Master Reception
18.4.1.8
Receive Overrun Error
Data is received at the RX/DT pin. The RX/DT pin
output driver must be disabled by setting the
corresponding TRIS bits when the EUSART is
configured for synchronous master receive operation.
The receive FIFO buffer can hold two characters. An
overrun error will be generated if a third character, in its
entirety, is received before RCREG is read to access
the FIFO. When this happens the OERR bit of the
RCSTA register is set. Previous data in the FIFO will
not be overwritten. The two characters in the FIFO
buffer can be read, however, no additional characters
will be received until the error is cleared. The OERR bit
can only be cleared by clearing the overrun condition.
If the overrun error occurred when the SREN bit is set
and CREN is clear then the error is cleared by reading
RCREG. If the overrun occurred when the CREN bit is
set then the error condition is cleared by either clearing
the CREN bit of the RCSTA register or by clearing the
SPEN bit which resets the EUSART.
In Synchronous mode, reception is enabled by setting
either the Single Receive Enable bit (SREN of the
RCSTA register) or the Continuous Receive Enable bit
(CREN of the RCSTA register).
When SREN is set and CREN is clear, only as many
clock cycles are generated as there are data bits in a
single character. The SREN bit is automatically cleared
at the completion of one character. When CREN is set,
clocks are continuously generated until CREN is
cleared. If CREN is cleared in the middle of a character
the CK clock stops immediately and the partial charac-
ter is discarded. If SREN and CREN are both set, then
SREN is cleared at the completion of the first character
and CREN takes precedence.
18.4.1.9
Receiving 9-bit Characters
The EUSART supports 9-bit character reception. When
the RX9 bit of the RCSTA register is set the EUSART
will shift 9-bits into the RSR for each character
received. The RX9D bit of the RCSTA register is the
ninth, and Most Significant, data bit of the top unread
character in the receive FIFO. When reading 9-bit data
from the receive FIFO buffer, the RX9D data bit must
be read before reading the 8 Least Significant bits from
the RCREG.
To initiate reception, set either SREN or CREN. Data is
sampled at the RX/DT pin on the trailing edge of the
TX/CK clock pin and is shifted into the Receive Shift
Register (RSR). When a complete character is
received into the RSR, the RCIF bit is set and the
character is automatically transferred to the two
character receive FIFO. The Least Significant eight bits
of the top character in the receive FIFO are available in
RCREG. The RCIF bit remains set as long as there are
un-read characters in the receive FIFO.
18.4.1.10 Synchronous Master Reception
Set-up:
1. Initialize the SPBRGH, SPBRG register pair for
the appropriate baud rate. Set or clear the
BRGH and BRG16 bits, as required, to achieve
the desired baud rate.
18.4.1.7
Slave Clock
Synchronous data transfers use a separate clock line,
which is synchronous with the data. A device configured
as a slave receives the clock on the TX/CK line. The
TX/CK pin output driver must be disabled by setting the
associated TRIS bit when the device is configured for
synchronous slave transmit or receive operation. Serial
data bits change on the leading edge to ensure they are
valid at the trailing edge of each clock. One data bit is
transferred for each clock cycle. Only as many clock
cycles should be received as there are data bits.
2. Enable the synchronous master serial port by
setting bits SYNC, SPEN and CSRC. Disable
RX/DT and TX/CK output drivers by setting the
corresponding TRIS bits.
3. Ensure bits CREN and SREN are clear.
4. If using interrupts, set the GIE and PEIE bits of
the INTCON register and set RCIE.
5. If 9-bit reception is desired, set bit RX9.
6. Start reception by setting the SREN bit or for
continuous reception, set the CREN bit.
7. Interrupt flag bit RCIF will be set when reception
of a character is complete. An interrupt will be
generated if the enable bit RCIE was set.
8. Read the RCSTA register to get the ninth bit (if
enabled) and determine if any error occurred
during reception.
9. Read the 8-bit received data by reading the
RCREG register.
10. If an overrun error occurs, clear the error by
either clearing the CREN bit of the RCSTA
register or by clearing the SPEN bit which resets
the EUSART.
DS41303B-page 250
Advance Information
© 2007 Microchip Technology Inc.
PIC18F2XK20/4XK20
FIGURE 18-12:
SYNCHRONOUS RECEPTION (MASTER MODE, SREN)
RX/DT
pin
bit 0
bit 1
bit 2
bit 3
bit 4
bit 5
bit 6
bit 7
TX/CK pin
(SCKP = 0)
TX/CK pin
(SCKP = 1)
Write to
bit SREN
SREN bit
‘0’
‘0’
CREN bit
RCIF bit
(Interrupt)
Read
RXREG
Note:
Timing diagram demonstrates Sync Master mode with bit SREN = 1and bit BRGH = 0.
TABLE 18-8: REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER RECEPTION
Reset
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Values
on page
INTCON
PIR1
GIE/GIEH PEIE/GIEL TMR0IE
INT0IE
TXIF
RBIE
SSPIF
SSPIE
SSPIP
ADDEN
TMR0IF
CCP1IF
CCP1IE
CCP1IP
FERR
INT0IF
RBIF
57
60
60
60
59
59
59
59
59
59
PSPIF(1)
PSPIE(1)
PSPIP(1)
SPEN
ADIF
ADIE
ADIP
RX9
RCIF
RCIE
RCIP
SREN
TMR2IF TMR1IF
TMR2IE TMR1IE
TMR2IP TMR1IP
PIE1
TXIE
IPR1
TXIP
RCSTA
RCREG
TXSTA
CREN
OERR
RX9D
EUSART Receive Register
CSRC
TX9
TXEN
SYNC
SENDB
BRG16
BRGH
—
TRMT
WUE
TX9D
BAUDCTL ABDOVF
RCIDL
DTRXP
CKTXP
ABDEN
SPBRGH EUSART Baud Rate Generator Register, High Byte
SPBRG EUSART Baud Rate Generator Register, Low Byte
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used for synchronous master reception.
Note 1: Reserved in 28-pin devices; always maintain these bits clear.
© 2007 Microchip Technology Inc.
Advance Information
DS41303B-page 251
PIC18F2XK20/4XK20
If two words are written to the TXREG and then the
SLEEPinstruction is executed, the following will occur:
18.4.2
SYNCHRONOUS SLAVE MODE
The following bits are used to configure the EUSART
for Synchronous slave operation:
1. The first character will immediately transfer to
the TSR register and transmit.
• SYNC = 1
2. The second word will remain in TXREG register.
3. The TXIF bit will not be set.
• CSRC = 0
• SREN = 0(for transmit); SREN = 1(for receive)
• CREN = 0(for transmit); CREN = 1(for receive)
• SPEN = 1
4. After the first character has been shifted out of
TSR, the TXREG register will transfer the second
character to the TSR and the TXIF bit will now be
set.
Setting the SYNC bit of the TXSTA register configures the
device for synchronous operation. Clearing the CSRC bit
of the TXSTA register configures the device as a slave.
Clearing the SREN and CREN bits of the RCSTA register
ensures that the device is in the Transmit mode,
otherwise the device will be configured to receive. Setting
the SPEN bit of the RCSTA register enables the
EUSART. If the RX/DT or TX/CK pins are shared with an
analog peripheral the analog I/O functions must be
disabled by clearing the corresponding ANSEL bits.
5. If the PEIE and TXIE bits are set, the interrupt
will wake the device from Sleep and execute the
next instruction. If the GIE bit is also set, the
program will call the Interrupt Service Routine.
18.4.2.2
Synchronous Slave Transmission
Set-up:
1. Set the SYNC and SPEN bits and clear the
CSRC bit. Set the TRIS bits corresponding to
the RX/DT and TX/CK I/O pins.
RX/DT and TX/CK pin output drivers must be disabled
by setting the corresponding TRIS bits.
2. Clear the CREN and SREN bits.
3. If using interrupts, ensure that the GIE and PEIE
bits of the INTCON register are set and set the
TXIE bit.
18.4.2.1
EUSART Synchronous Slave
Transmit
The operation of the Synchronous Master and Slave
modes are identical (see Section 18.4.1.3
“Synchronous Master Transmission”), except in the
4. If 9-bit transmission is desired, set the TX9 bit.
5. Enable transmission by setting the TXEN bit.
6. If 9-bit transmission is selected, insert the Most
Significant bit into the TX9D bit.
case of the Sleep mode.
7. Start transmission by writing the Least
Significant 8 bits to the TXREG register.
TABLE 18-9: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE TRANSMISSION
Reset
Values
on page
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
INTCON
PIR1
GIE/GIEH PEIE/GIEL TMR0IE
INT0IE
TXIF
RBIE
SSPIF
SSPIE
SSPIP
ADDEN
TRISC3
TMR0IF
INT0IF
RBIF
57
60
60
60
59
60
59
59
59
59
59
PSPIF(1)
PSPIE(1)
PSPIP(1)
SPEN
ADIF
ADIE
RCIF
RCIE
CCP1IF TMR2IF TMR1IF
CCP1IE TMR2IE TMR1IE
CCP1IP TMR2IP TMR1IP
PIE1
TXIE
IPR1
ADIP
RCIP
TXIP
RCSTA
TRISC
TXREG
TXSTA
BAUDCTL
SPBRGH
SPBRG
RX9
SREN
TRISC5
CREN
TRISC4
FERR
OERR
RX9D
TRISC7
TRISC6
TRISC2
TRISC1
TRISC0
EUSART Transmit Register
CSRC
TX9
TXEN
SYNC
SENDB
BRG16
BRGH
—
TRMT
WUE
TX9D
ABDOVF
RCIDL
DTRXP
CKTXP
ABDEN
EUSART Baud Rate Generator Register, High Byte
EUSART Baud Rate Generator Register, Low Byte
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used for synchronous master transmission.
Note 1: Reserved in PIC18F2XK20 devices; always maintain these bits clear.
DS41303B-page 252
Advance Information
© 2007 Microchip Technology Inc.
PIC18F2XK20/4XK20
18.4.2.3
EUSART Synchronous Slave
Reception
18.4.2.4
Synchronous Slave Reception
Set-up:
The operation of the Synchronous Master and Slave
modes is identical (Section 18.4.1.6 “Synchronous
Master Reception”), with the following exceptions:
1. Set the SYNC and SPEN bits and clear the
CSRC bit. Set the TRIS bits corresponding to
the RX/DT and TX/CK I/O pins.
2. If using interrupts, ensure that the GIE and PEIE
bits of the INTCON register are set and set the
RCIE bit.
• Sleep
• CREN bit is always set, therefore the receiver is
never Idle
3. If 9-bit reception is desired, set the RX9 bit.
4. Set the CREN bit to enable reception.
• SREN bit, which is a “don't care” in Slave mode
A character may be received while in Sleep mode by
setting the CREN bit prior to entering Sleep. Once the
word is received, the RSR register will transfer the data
to the RCREG register. If the RCIE enable bit is set, the
interrupt generated will wake the device from Sleep
and execute the next instruction. If the GIE bit is also
set, the program will branch to the interrupt vector.
5. The RCIF bit will be set when reception is
complete. An interrupt will be generated if the
RCIE bit was set.
6. If 9-bit mode is enabled, retrieve the Most
Significant bit from the RX9D bit of the RCSTA
register.
7. Retrieve the 8 Least Significant bits from the
receive FIFO by reading the RCREG register.
8. If an overrun error occurs, clear the error by
either clearing the CREN bit of the RCSTA
register or by clearing the SPEN bit which resets
the EUSART.
TABLE 18-10: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE RECEPTION
Reset
Values
on page
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
INTCON
PIR1
GIE/GIEH PEIE/GIEL TMR0IE
INT0IE
TXIF
RBIE
SSPIF
SSPIE
SSPIP
ADDEN
TMR0IF
CCP1IF
INT0IF
RBIF
57
60
60
60
59
59
59
59
59
59
PSPIF(1)
PSPIE(1)
PSPIP(1)
SPEN
ADIF
ADIE
ADIP
RX9
RCIF
RCIE
RCIP
SREN
TMR2IF TMR1IF
PIE1
TXIE
CCP1IE TMR2IE TMR1IE
CCP1IP TMR2IP TMR1IP
IPR1
TXIP
RCSTA
RCREG
TXSTA
BAUDCTL
SPBRGH
SPBRG
CREN
FERR
OERR
RX9D
EUSART Receive Register
CSRC
TX9
TXEN
SYNC
SENDB
BRG16
BRGH
—
TRMT
WUE
TX9D
ABDOVF
RCIDL
DTRXP
CKTXP
ABDEN
EUSART Baud Rate Generator Register, High Byte
EUSART Baud Rate Generator Register, Low Byte
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used for synchronous slave reception.
Note 1: Reserved in 28-pin devices; always maintain these bits clear.
© 2007 Microchip Technology Inc.
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PIC18F2XK20/4XK20
NOTES:
DS41303B-page 254
Advance Information
© 2007 Microchip Technology Inc.
PIC18F2XK20/4XK20
19.0 ANALOG-TO-DIGITAL
CONVERTER (ADC) MODULE
The Analog-to-Digital Converter (ADC) allows
conversion of an analog input signal to a 10-bit binary
representation of that signal. This device uses analog
inputs, which are multiplexed into a single sample and
hold circuit. The output of the sample and hold is
connected to the input of the converter. The converter
generates a 10-bit binary result via successive
approximation and stores the conversion result into the
ADC result registers (ADRESL and ADRESH).
The ADC voltage reference is software selectable to
either VDD or a voltage applied to the external reference
pins.
The ADC can generate an interrupt upon completion of
a conversion. This interrupt can be used to wake-up the
device from Sleep.
Figure 19-1 shows the block diagram of the ADC.
FIGURE 19-1:
ADC BLOCK DIAGRAM
VCFG1 = 0
VCFG1 = 1
AVSS
VREF-
AVDD
VCFG0 = 0
VCFG0 = 1
VREF+
0000
AN0
AN1
AN2
AN3
AN4
AN5
AN6
AN7
AN8
AN9
AN10
AN11
AN12
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
ADC
10
GO/DONE
0= Left Justify
1= Right Justify
ADFM
ADON
10
Unused
Unused
VSS
ADRESH ADRESL
FVR
CHS<3:0>
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PIC18F2XK20/4XK20
19.1.4
SELECTING AND CONFIGURING
ACQUISITION TIME
19.1 ADC Configuration
When configuring and using the ADC the following
functions must be considered:
The ADCON2 register allows the user to select an
acquisition time that occurs each time the GO/DONE
bit is set.
• Port configuration
• Channel selection
Acquisition time is set with the ACQT<2:0> bits of the
ADCON2 register. Acquisition delays cover a range of
2 to 20 TAD. When the GO/DONE bit is set, the A/D
module continues to sample the input for the selected
acquisition time, then automatically begins a conver-
sion. Since the acquisition time is programmed, there is
no need to wait for an acquisition time between select-
ing a channel and setting the GO/DONE bit.
• ADC voltage reference selection
• ADC conversion clock source
• Interrupt control
• Results formatting
19.1.1
PORT CONFIGURATION
The ANSEL, ANSELH, TRISA, TRISB and TRISE reg-
isters all configure the A/D port pins. Any port pin
needed as an analog input should have its correspond-
ing ANSx bit set to disable the digital input buffer and
TRISx bit set to disable the digital output driver. If the
TRISx bit is cleared, the digital output level (VOH or
VOL) will be converted.
Manual
acquisition
is
selected
when
ACQT<2:0> = 000. When the GO/DONE bit is set,
sampling is stopped and a conversion begins. The user
is responsible for ensuring the required acquisition time
has passed between selecting the desired input
channel and setting the GO/DONE bit. This option is
also the default Reset state of the ACQT<2:0> bits and
is compatible with devices that do not offer
programmable acquisition times.
The A/D operation is independent of the state of the
ANSx bits and the TRIS bits.
Note 1: When reading the PORT register, all pins
with their corresponding ANSx bit set
read as cleared (a low level). However,
analog conversion of pins configured as
digital inputs (ANSx bit cleared and
TRISx bit set) will be accurately
converted.
In either case, when the conversion is completed, the
GO/DONE bit is cleared, the ADIF flag is set and the
A/D begins sampling the currently selected channel
again. When an acquisition time is programmed, there
is no indication of when the acquisition time ends and
the conversion begins.
19.1.5
CONVERSION CLOCK
2: Analog levels on any pin with the corre-
sponding ANSx bit cleared may cause the
digital input buffer to consume current out
of the device’s specification limits.
The source of the conversion clock is software select-
able via the ADCS bits of the ADCON2 register. There
are seven possible clock options:
3: The PBADEN bit in Configuration
Register 3H configures PORTB pins to
reset as analog or digital pins by
controlling how the bits in ANSELH are
reset.
• FOSC/2
• FOSC/4
• FOSC/8
• FOSC/16
• FOSC/32
19.1.2
CHANNEL SELECTION
• FOSC/64
The CHS bits of the ADCON0 register determine which
channel is connected to the sample and hold circuit.
• FRC (dedicated internal oscillator)
The time to complete one bit conversion is defined as
TAD. One full 10-bit conversion requires 11 TAD periods
as shown in Figure 19-3.
When changing channels, a delay is required before
starting the next conversion. Refer to Section 19.2
“ADC Operation” for more information.
For correct conversion, the appropriate TAD specification
must be met. See A/D conversion requirements in
Table 26-25 for more information. Table 19-1 gives
examples of appropriate ADC clock selections.
19.1.3
ADC VOLTAGE REFERENCE
The VCFG bits of the ADCON1 register provide
independent control of the positive and negative
voltage references. The positive voltage reference can
be either VDD or an external voltage source. Likewise,
the negative voltage reference can be either VSS or an
external voltage source.
Note:
Unless using the FRC, any changes in the
system clock frequency will change the
ADC clock frequency, which may
adversely affect the ADC result.
DS41303B-page 256
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PIC18F2XK20/4XK20
This interrupt can be generated while the device is
operating or while in Sleep. If the device is in Sleep, the
interrupt will wake-up the device. Upon waking from
Sleep, the next instruction following the SLEEP
instruction is always executed. If the user is attempting
to wake-up from Sleep and resume in-line code
execution, the global interrupt must be disabled. If the
global interrupt is enabled, execution will switch to the
Interrupt Service Routine. Please see Section 19.1.6
“Interrupts” for more information.
19.1.6
INTERRUPTS
The ADC module allows for the ability to generate an
interrupt upon completion of an Analog-to-Digital
Conversion. The ADC interrupt flag is the ADIF bit in
the PIR1 register. The ADC interrupt enable is the ADIE
bit in the PIE1 register. The ADIF bit must be cleared by
software.
Note:
The ADIF bit is set at the completion of
every conversion, regardless of whether
or not the ADC interrupt is enabled.
TABLE 19-1: ADC CLOCK PERIOD (TAD) VS. DEVICE OPERATING FREQUENCIES
ADC Clock Period (TAD)
ADC Clock Source ADCS<2:0>
Device Frequency (FOSC)
64 MHz
16 MHz
4 MHz
1 MHz
FOSC/2
FOSC/4
FOSC/8
FOSC/16
FOSC/32
FOSC/64
FRC
000
100
001
101
010
110
x11
31.25 ns(2)
62.5 ns(2)
400 ns(2)
250 ns(2)
500 ns(2)
1.0 μs
125 ns(2)
250 ns(2)
500 ns(2)
1.0 μs
500 ns(2)
1.0 μs
2.0 μs
4.0 μs(3)
8.0 μs(3)
16.0 μs(3)
32.0 μs(3)
64.0 μs(3)
1-4 μs(1,4)
2.0 μs
4.0 μs(3)
8.0 μs(3)
16.0 μs(3)
1-4 μs(1,4)
2.0 μs
4.0 μs(3)
1-4 μs(1,4)
1-4 μs(1,4)
Legend: Shaded cells are outside of recommended range.
Note 1: The FRC source has a typical TAD time of 1.7 μs.
2: These values violate the minimum required TAD time.
3: For faster conversion times, the selection of another clock source is recommended.
4: When the device frequency is greater than 1 MHz, the FRC clock source is only recommended if the
conversion will be performed during Sleep.
19.1.7
RESULT FORMATTING
The 10-bit A/D conversion result can be supplied in two
formats, left justified or right justified. The ADFM bit of
the ADCON2 register controls the output format.
Figure 19-2 shows the two output formats.
FIGURE 19-2:
10-BIT A/D CONVERSION RESULT FORMAT
ADRESH
ADRESL
(ADFM = 0)
MSB
bit 7
LSB
bit 0
bit 0
bit 7
bit 7
bit 0
10-bit A/D Result
Unimplemented: Read as ‘0’
(ADFM = 1)
MSB
LSB
bit 7
bit 0
Unimplemented: Read as ‘0’
10-bit A/D Result
© 2007 Microchip Technology Inc.
Advance Information
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PIC18F2XK20/4XK20
Figure 19-3 shows the operation of the A/D converter
after the GO bit has been set and the ACQT<2:0> bits
are cleared. A conversion is started after the following
instruction to allow entry into SLEEP mode before the
conversion begins.
19.2 ADC Operation
19.2.1
STARTING A CONVERSION
To enable the ADC module, the ADON bit of the
ADCON0 register must be set to a ‘1’. Setting the GO/
DONE bit of the ADCON0 register to a ‘1’ will, depend-
ing on the ACQT bits of the ADCON2 register, either
immediately start the Analog-to-Digital conversion or
start an acquisition delay followed by the Analog-to-
Digital conversion.
Figure 19-4 shows the operation of the A/D converter
after the GO bit has been set and the ACQT<2:0> bits
are set to ‘010’ which selects a 4 TAD acquisition time
before the conversion starts.
Note:
The GO/DONE bit should not be set in the
same instruction that turns on the ADC.
Refer to Section 19.2.9 “A/D Conver-
sion Procedure”.
FIGURE 19-3:
A/D CONVERSION TAD CYCLES (ACQT<2:0> = 000, TACQ = 0)
TCY - TAD
TAD8 TAD9 TAD10 TAD11
2 TAD
TAD1 TAD2 TAD3 TAD4 TAD5 TAD6 TAD7
b4
b1
b0
b9
b8
b7
b6
b5
b3
b2
Conversion starts
Discharge
Holding capacitor is disconnected from analog input (typically 100 ns)
Set GO bit
On the following cycle:
ADRESH:ADRESL is loaded, GO bit is cleared,
ADIF bit is set, holding capacitor is connected to analog input.
FIGURE 19-4:
A/D CONVERSION TAD CYCLES (ACQT<2:0> = 010, TACQ = 4 TAD)
TAD Cycles
TACQT Cycles
6
7
8
9
10
b1
11 2 TAD
b0
1
2
3
4
1
2
3
4
5
b7
b6
b3
b2
b8
b5
b4
b9
Automatic
Acquisition
Time
Discharge
Conversion starts
(Holding capacitor is disconnected from analog input)
Set GO bit
(Holding capacitor continues
acquiring input)
On the following cycle:
ADRESH:ADRESL is loaded, GO bit is cleared,
ADIF bit is set, holding capacitor is connected to analog input.
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PIC18F2XK20/4XK20
19.2.2
COMPLETION OF A CONVERSION
19.2.7
ADC OPERATION DURING SLEEP
When the conversion is complete, the ADC module will:
The ADC module can operate during Sleep. This
requires the ADC clock source to be set to the FRC
option. When the FRC clock source is selected, the
ADC waits one additional instruction before starting the
conversion. This allows the SLEEP instruction to be
executed, which can reduce system noise during the
conversion. If the ADC interrupt is enabled, the device
will wake-up from Sleep when the conversion
completes. If the ADC interrupt is disabled, the ADC
module is turned off after the conversion completes,
although the ADON bit remains set.
• Clear the GO/DONE bit
• Set the ADIF flag bit
• Update the ADRESH:ADRESL registers with new
conversion result
19.2.3
DISCHARGE
The discharge phase is used to initialize the value of
the capacitor array. The array is discharged after every
sample. This feature helps to optimize the unity-gain
amplifier, as the circuit always needs to charge the
capacitor array, rather than charge/discharge based on
previous measure values.
When the ADC clock source is something other than
FRC, a SLEEP instruction causes the present conver-
sion to be aborted and the ADC module is turned off,
although the ADON bit remains set.
19.2.4
TERMINATING A CONVERSION
19.2.8
SPECIAL EVENT TRIGGER
If a conversion must be terminated before completion,
the GO/DONE bit can be cleared by software. The
ADRESH:ADRESL registers will not be updated with
the partially complete Analog-to-Digital conversion
sample. Instead, the ADRESH:ADRESL register pair
will retain the value of the previous conversion.
The CCP2 Special Event Trigger allows periodic ADC
measurements without software intervention. When
this trigger occurs, the GO/DONE bit is set by hardware
and the Timer1 or Timer3 counter resets to zero.
Using the Special Event Trigger does not assure proper
ADC timing. It is the user’s responsibility to ensure that
the ADC timing requirements are met.
Note:
A device Reset forces all registers to their
Reset state. Thus, the ADC module is
turned off and any pending conversion is
terminated.
See Section 15.3.4 “Special Event Trigger” for more
information.
19.2.5
DELAY BETWEEN CONVERSIONS
After the A/D conversion is completed or aborted, a
2 TAD wait is required before the next acquisition can
be started. After this wait, the currently selected
channel is reconnected to the charge holding capacitor
commencing the next acquisition.
19.2.6
ADC OPERATION IN POWER-
MANAGED MODES
The selection of the automatic acquisition time and A/D
conversion clock is determined in part by the clock
source and frequency while in a power-managed mode.
If the A/D is expected to operate while the device is in
a
power-managed mode, the ACQT<2:0> and
ADCS<2:0> bits in ADCON2 should be updated in
accordance with the clock source to be used in that
mode. After entering the mode, an A/D acquisition or
conversion may be started. Once started, the device
should continue to be clocked by the same clock
source until the conversion has been completed.
If desired, the device may be placed into the
corresponding Idle mode during the conversion. If the
device clock frequency is less than 1 MHz, the A/D FRC
clock source should be selected.
© 2007 Microchip Technology Inc.
Advance Information
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PIC18F2XK20/4XK20
19.2.9
A/D CONVERSION PROCEDURE
EXAMPLE 19-1:
A/D CONVERSION
;This code block configures the ADC
;for polling, Vdd and Vss as reference, Frc
clock and AN0 input.
;
This is an example procedure for using the ADC to
perform an Analog-to-Digital conversion:
1. Configure Port:
• Disable pin output driver (See TRIS register)
• Configure pin as analog
2. Configure the ADC module:
• Select ADC conversion clock
• Configure voltage reference
• Select ADC input channel
• Select result format
;Conversion start & polling for completion
; are included.
;
MOVLW
MOVWF
MOVLW
MOVWF
BSF
B’10101111’ ;right justify, Frc,
ADCON2 ; & 12 TAD ACQ time
B’00000000’ ;ADC ref = Vdd,Vss
ADCON1
;
TRISA,0
ANSEL,0
;Set RA0 to input
;Set RA0 to analog
BSF
MOVLW
MOVWF
BSF
ADCPoll:
BTFSC
BRA
B’00000001’ ;AN0, ADC on
• Select acquisition delay
ADCON0
;
• Turn on ADC module
ADCON0,GO
;Start conversion
3. Configure ADC interrupt (optional):
• Clear ADC interrupt flag
• Enable ADC interrupt
ADCON0,GO
ADCPoll
;Is conversion done?
;No, test again
; Result is complete - store 2 MSbits in
; RESULTHI and 8 LSbits in RESULTLO
MOVFF
MOVFF
• Enable peripheral interrupt
• Enable global interrupt(1)
4. Wait the required acquisition time(2)
ADRESH,RESULTHI
ADRESL,RESULTLO
.
5. Start conversion by setting the GO/DONE bit.
6. Wait for ADC conversion to complete by one of
the following:
• Polling the GO/DONE bit
• Waiting for the ADC interrupt (interrupts
enabled)
7. Read ADC Result
8. Clear the ADC interrupt flag (required if interrupt
is enabled).
Note 1: The global interrupt can be disabled if the
user is attempting to wake-up from Sleep
and resume in-line code execution.
2: Software delay required if ACQT bits are
set to zero delay. See Section 19.3 “A/D
Acquisition Requirements”.
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PIC18F2XK20/4XK20
19.2.10 ADC REGISTER DEFINITIONS
The following registers are used to control the opera-
tion of the ADC.
Note:
Analog pin control is performed by the
ANSEL and ANSELH registers. For ANSEL
and ANSELH registers, see Register 10-2
and Register 10-3, respectively.
REGISTER 19-1: ADCON0: A/D CONTROL REGISTER 0
U-0
—
U-0
—
R/W-0
CHS3
R/W-0
CHS2
R/W-0
CHS1
R/W-0
CHS0
R/W-0
R/W-0
ADON
GO/DONE
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7-6
bit 5-2
Unimplemented: Read as ‘0’
CHS<3:0>: Analog Channel Select bits
0000= AN0
0001= AN1
0010= AN2
0011= AN3
0100= AN4
0101= AN5(1)
0110= AN6(1)
0111= AN7(1)
1000= AN8
1001= AN9
1010= AN10
1011= AN11
1100= AN12
1101= Reserved
1110= Reserved
1111= FVR (1.2 Volt Fixed Voltage Reference)
bit 1
bit 0
GO/DONE: A/D Conversion Status bit
1= A/D conversion cycle in progress. Setting this bit starts an A/D conversion cycle.
This bit is automatically cleared by hardware when the A/D conversion has completed.
0= A/D conversion completed/not in progress
ADON: ADC Enable bit
1= ADC is enabled
0= ADC is disabled and consumes no operating current
Note 1: These channels are not implemented on PIC18F2XK20 devices.
© 2007 Microchip Technology Inc.
Advance Information
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PIC18F2XK20/4XK20
REGISTER 19-2: ADCON1: A/D CONTROL REGISTER 1
U-0
—
U-0
—
R/W-0
R/W-0
U-0
—
U-0
—
U-0
—
U-0
—
VCFG1
VCFG0
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7-6
bit 5
Unimplemented: Read as ‘0’
VCFG1: Negative Voltage Reference select bit
1= Negative voltage reference supplied externally through VREF- pin.
0= Negative voltage reference supplied internally by VSS.
bit 4
VCFG0: Positive Voltage Reference select bit
1= Positive voltage reference supplied externally through VREF+ pin.
0= Positive voltage reference supplied internally by VDD.
bit 3-0
Unimplemented: Read as ‘0’
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REGISTER 19-3: ADCON2: A/D CONTROL REGISTER 2
R/W-0
ADFM
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
ACQT2
ACQT1
ACQT0
ADCS2
ADCS1
ADCS0
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7
ADFM: A/D Conversion Result Format Select bit
1= Right justified
0= Left justified
bit 6
Unimplemented: Read as ‘0’
bit 5-3
ACQT<2:0>: A/D Acquisition time select bits. Acquisition time is the duration that the A/D charge hold-
ing capacitor remains connected to A/D channel from the instant the GO/DONE bit is set until conver-
sions begins.
000= 0(1)
001= 2 TAD
010= 4 TAD
011= 6 TAD
100= 8 TAD
101= 12 TAD
110= 16 TAD
111= 20 TAD
bit 2-0
ADCS<2:0>: A/D Conversion Clock Select bits
000= FOSC/2
001= FOSC/8
010= FOSC/32
011= FRC(1) (clock derived from a dedicated internal oscillator = 600 kHz nominal)
100= FOSC/4
101= FOSC/16
110= FOSC/64
111= FRC(1) (clock derived from a dedicated internal oscillator = 600 kHz nominal)
Note 1: When the A/D clock source is selected as FRC then the start of conversion is delayed by one instruction
cycle after the GO/DONE bit is set to allow the SLEEPinstruction to be executed.
© 2007 Microchip Technology Inc.
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PIC18F2XK20/4XK20
REGISTER 19-4: ADRESH: ADC RESULT REGISTER HIGH (ADRESH) ADFM = 0
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
ADRES9
ADRES8
ADRES7
ADRES6
ADRES5
ADRES4
ADRES3
ADRES2
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7-0
ADRES<9:2>: ADC Result Register bits
Upper 8 bits of 10-bit conversion result
REGISTER 19-5: ADRESL: ADC RESULT REGISTER LOW (ADRESL) ADFM = 0
R/W-x
R/W-x
R/W-x
—
R/W-x
—
R/W-x
—
R/W-x
—
R/W-x
—
R/W-x
—
ADRES1
ADRES0
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7-6
bit 5-0
ADRES<1:0>: ADC Result Register bits
Lower 2 bits of 10-bit conversion result
Reserved: Do not use.
REGISTER 19-6: ADRESH: ADC RESULT REGISTER HIGH (ADRESH) ADFM = 1
R/W-x
—
R/W-x
—
R/W-x
—
R/W-x
—
R/W-x
—
R/W-x
—
R/W-x
R/W-x
ADRES9
ADRES8
bit 0
bit 7
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7-2
bit 1-0
Reserved: Do not use.
ADRES<9:8>: ADC Result Register bits
Upper 2 bits of 10-bit conversion result
REGISTER 19-7: ADRESL: ADC RESULT REGISTER LOW (ADRESL) ADFM = 1
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
ADRES7
ADRES6
ADRES5
ADRES4
ADRES3
ADRES2
ADRES1
ADRES0
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 7-0
ADRES<7:0>: ADC Result Register bits
Lower 8 bits of 10-bit conversion result
DS41303B-page 264
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PIC18F2XK20/4XK20
an A/D acquisition must be done before the conversion
can be started. To calculate the minimum acquisition
time, Equation 19-1 may be used. This equation
assumes that 1/2 LSb error is used (1024 steps for the
ADC). The 1/2 LSb error is the maximum error allowed
for the ADC to meet its specified resolution.
19.3 A/D Acquisition Requirements
For the ADC to meet its specified accuracy, the charge
holding capacitor (CHOLD) must be allowed to fully
charge to the input channel voltage level. The Analog
Input model is shown in Figure 19-5. The source
impedance (RS) and the internal sampling switch (RSS)
impedance directly affect the time required to charge the
capacitor CHOLD. The sampling switch (RSS) impedance
varies over the device voltage (VDD), see Figure 19-5.
The maximum recommended impedance for analog
sources is 10 kΩ. As the source impedance is
decreased, the acquisition time may be decreased.
After the analog input channel is selected (or changed),
EQUATION 19-1: ACQUISITION TIME EXAMPLE
Temperature = 50°C and external impedance of 10kΩ 3.0V VDD
Assumptions:
TACQ = Amplifier Settling Time + Hold Capacitor Charging Time + Temperature Coefficient
= TAMP + TC + TCOFF
= 5µs + TC + [(Temperature - 25°C)(0.05µs/°C)]
The value for TC can be approximated with the following equations:
1
2047
⎛
⎞
= VCHOLD
-----------
;[1] VCHOLD charged to within 1/2 lsb
VAPPLIED 1 –
⎝
⎠
–TC
---------
⎛
⎞
VAPPLIED 1 – e RC = VCHOLD
;[2] VCHOLD charge response to VAPPLIED
⎜
⎝
⎟
⎠
–Tc
--------
⎛
⎞
1
2047
VAPPLIED 1 – eRC = VAPPLIED 1 –
⎛
⎞
⎠
;combining [1] and [2]
-----------
⎜
⎝
⎟
⎠
⎝
Solving for TC:
TC = –CHOLD(RIC + RSS + RS) ln(1/2047)
= –13.5pF(1kΩ + 700Ω + 10kΩ) ln(0.0004885)
= 1.20µs
Therefore:
TACQ = 5µS + 1.20µS + [(50°C- 25°C)(0.05µS/°C)]
= 7.45µS
Note 1: The reference voltage (VREF) has no effect on the equation, since it cancels itself out.
2: The charge holding capacitor (CHOLD) is discharged after each conversion.
3: The maximum recommended impedance for analog sources is 10 kΩ. This is required to meet the pin
leakage specification.
© 2007 Microchip Technology Inc.
Advance Information
DS41303B-page 265
PIC18F2XK20/4XK20
FIGURE 19-5:
ANALOG INPUT MODEL
VDD
Sampling
Switch
VT = 0.6V
ANx
SS
RIC ≤ 1k
Rss
Rs
CHOLD = 13.5 pF
VSS/VREF-
(1)
CPIN
5 pF
VA
I LEAKAGE
VT = 0.6V
Discharge
Switch
3.5V
3.0V
2.5V
2.0V
1.5V
Legend: CPIN
= Input Capacitance
= Threshold Voltage
VT
I LEAKAGE = Leakage current at the pin due to
various junctions
= Interconnect Resistance
= Sampling Switch
RIC
SS
100
.1
1
10
CHOLD
= Sample/Hold Capacitance
Rss (kΩ)
Note 1: See Section 26.0 “Electrical Characteristics”.
FIGURE 19-6:
ADC TRANSFER FUNCTION
Full-Scale Range
3FFh
3FEh
3FDh
3FCh
3FBh
1/2 LSB ideal
Full-Scale
Transition
004h
003h
002h
001h
000h
Analog Input Voltage
1/2 LSB ideal
Zero-Scale
Transition
VDD/VREF+
VSS/VREF-
DS41303B-page 266
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PIC18F2XK20/4XK20
TABLE 19-2: REGISTERS ASSOCIATED WITH A/D OPERATION
Reset
Values
on page
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
INTCON
PIR1
PIE1
GIE/GIEH PEIE/GIEL TMR0IE
INT0IE
TXIF
TXIE
TXIP
EEIF
EEIE
EEIP
RBIE
SSPIF
SSPIE
SSPIP
BCLIF
BCLIE
BCLIP
TMR0IF
CCP1IF
CCP1IE
CCP1IP
HLVDIF
HLVDIE
HLVDIP
INT0IF
TMR2IF
TMR2IE
TMR2IP
TMR3IF
TMR3IE
TMR3IP
RBIF
57
60
60
60
60
60
60
59
59
59
59
59
60
60
60
60
60
60
60
60
60
60
PSPIF(1)
PSPIE(1)
PSPIP(1)
OSCFIF
OSCFIE
OSCFIP
ADIF
ADIE
ADIP
C1IF
C1IE
C1IP
RCIF
RCIE
RCIP
C2IF
C2IE
C2IP
TMR1IF
TMR1IE
TMR1IP
CCP2IF
CCP2IE
CCP2IP
IPR1
PIR2
PIE2
IPR2
ADRESH A/D Result Register, High Byte
ADRESL A/D Result Register, Low Byte
ADCON0
ADCON1
ADCON2
ANSEL
ANSELH
PORTA
TRISA
—
—
—
—
CHS3
VCFG1
ACQT2
ANS5(1)
—
CHS2
VCFG0
ACQT1
ANS4
CHS1
—
CHS0 GO/DONE ADON
—
—
—
ADFM
ANS7(1)
—
—
ANS6(1)
ACQT0
ANS3
ANS11
RA3
ADCS2
ANS2
ANS10
RA2
ADCS1
ANS1
ANS9
RA1
ADCS0
ANS0
ANS8
RA0
—
ANS12
RA7(2)
RA6(2)
RA5
RA4
TRISA7(2) TRISA6(2) PORTA Data Direction Control Register
PORTB
TRISB
RB7
PORTB Data Direction Control Register
PORTB Data Latch Register (Read and Write to Data Latch)
RB6
RB5
RB4
RB3
RB2
RB1
RB0
LATB
PORTE(4)
TRISE(4)
LATE(4)
—
IBF
—
—
OBF
—
—
IBOV
—
—
PSPMODE
—
RE3(3)
RE2
RE1
RE0
—
TRISE2
TRISE1
TRISE0
—
PORTE Data Latch Register
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used for A/D conversion.
Note 1: These bits are unimplemented on PIC18F2XK20 devices; always maintain these bits clear.
2: PORTA<7:6> and their direction bits are individually configured as port pins based on various primary
oscillator modes. When disabled, these bits read as ‘0’.
3: RE3 port bit is available only as an input pin when the MCLRE Configuration bit is ‘0’.
4: These registers are not implemented on PIC18F2XK20 devices.
© 2007 Microchip Technology Inc.
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PIC18F2XK20/4XK20
NOTES:
DS41303B-page 268
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PIC18F2XK20/4XK20
FIGURE 20-1:
SINGLE COMPARATOR
20.0 COMPARATOR MODULE
Comparators are used to interface analog circuits to a
digital circuit by comparing two analog voltages and
providing a digital indication of their relative magnitudes.
The comparators are very useful mixed signal building
blocks because they provide analog functionality
independent of the program execution. The Analog
Comparator module includes the following features:
VIN+
VIN-
+
Output
–
VIN-
VIN+
• Independent comparator control
• Programmable input selection
• Comparator output is available internally/externally
• Programmable output polarity
• Interrupt-on-change
Output
• Wake-up from Sleep
• Programmable Speed/Power optimization
• PWM shutdown
Note:
The black areas of the output of the
comparator represents the uncertainty
due to input offsets and response time.
• Programmable and fixed voltage reference
20.1
Comparator Overview
A single comparator is shown in Figure 20-1 along with
the relationship between the analog input levels and
the digital output. When the analog voltage at VIN+ is
less than the analog voltage at VIN-, the output of the
comparator is a digital low level. When the analog
voltage at VIN+ is greater than the analog voltage at
VIN-, the output of the comparator is a digital high level.
© 2007 Microchip Technology Inc.
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PIC18F2XK20/4XK20
FIGURE 20-2:
COMPARATOR C1 SIMPLIFIED BLOCK DIAGRAM
C1CH<1:0>
2
To
Data Bus
D
Q
Q1
C12IN0-
C12IN1-
C12IN2-
C12IN3-
EN
0
RD_CM1CON0
Set C1IF
1
MUX
2
D
Q
Q3*RD_CM1CON0
Reset
EN
To PWM Logic
C1OE
3
CL
(1)
C1ON
C1
C1R
C1VIN-
C1VIN+
-
C1IN+
0
MUX
1
C1OUT
+
(2)
CVREF
FVR
C1OUT pin
0
MUX
1
C1SP
C1POL
C1VREF
C1RSEL
Note 1: When C1ON = 0, the C1 comparator will produce a ‘0’ output to the XOR Gate.
2: Output shown for reference only. See I/O port pin block diagram for more detail.
3: Q1 and Q3 are phases of the four-phase system clock (FOSC).
4: Q1 is held high during Sleep mode.
FIGURE 20-3:
COMPARATOR C2 SIMPLIFIED BLOCK DIAGRAM
To
Data Bus
D
Q
Q1
EN
RD_CM2CON0
C2CH<1:0>
Set C2IF
2
D
Q
Q3*RD_CM2CON0
To PWM Logic
EN
(1)
C2ON
C2
C12IN0-
0
CL
C2OE
NRESET
C2OUT
C12IN1-
C12IN2-
C12IN3-
1
MUX
2
C2VIN-
C2VIN+
(2)
C2OUT pin
3
C2SP
C2POL
C2R
C2IN+
0
MUX
1
CVREF
FVR
0
MUX
1
C2VREF
Note 1: When C2ON = 0, the C2 comparator will produce a ‘0’ output to the XOR Gate.
2: Output shown for reference only. See I/O port pin block diagram for more detail.
3: Q1 and Q3 are phases of the four-phase system clock (FOSC).
4: Q1 is held high during Sleep mode.
C2RSEL
DS41303B-page 270
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PIC18F2XK20/4XK20
20.2 Comparator Control
Note 1: The CxOE bit overrides the PORT data
latch. Setting the CxON has no impact on
the port override.
Each comparator has
Configuration register: CM1CON0 for Comparator C1
and CM2CON0 for Comparator C2. In addition,
a
separate control and
Comparator C2 has
CM2CON1, for controlling the interaction with Timer1 and
simultaneous reading of both comparator outputs.
a
second control register,
2: The internal output of the comparator is
latched with each instruction cycle.
Unless otherwise specified, external
outputs are not latched.
The CM1CON0 and CM2CON0 registers (see Registers
20-1 and 20-2, respectively) contain the control and
Status bits for the following:
20.2.5
COMPARATOR OUTPUT POLARITY
Inverting the output of the comparator is functionally
equivalent to swapping the comparator inputs. The
polarity of the comparator output can be inverted by
setting the CxPOL bit of the CMxCON0 register.
Clearing the CxPOL bit results in a non-inverted output.
• Enable
• Input selection
• Reference selection
• Output selection
• Output polarity
• Speed selection
Table 20-1 shows the output state versus input
conditions, including polarity control.
TABLE 20-1: COMPARATOR OUTPUT
STATE VS. INPUT
20.2.1
COMPARATOR ENABLE
Setting the CxON bit of the CMxCON0 register enables
the comparator for operation. Clearing the CxON bit
disables the comparator resulting in minimum current
consumption.
CONDITIONS
Input Condition
CxPOL
CxOUT
CxVIN- > CxVIN+
CxVIN- < CxVIN+
CxVIN- > CxVIN+
CxVIN- < CxVIN+
0
0
1
1
0
1
1
0
20.2.2
COMPARATOR INPUT SELECTION
The CxCH<1:0> bits of the CMxCON0 register direct
one of four analog input pins to the comparator
inverting input.
20.2.6
COMPARATOR SPEED SELECTION
Note:
To use CxIN+ and C12INx- pins as analog
inputs, the appropriate bits must be set in
the ANSEL register and the corresponding
TRIS bits must also be set to disable the
output drivers.
The trade-off between speed or power can be opti-
mized during program execution with the CxSP control
bit. The default state for this bit is ‘1’ which selects the
normal speed mode. Device power consumption can
be optimized at the cost of slower comparator propaga-
tion delay by clearing the CxSP bit to ‘0’.
20.2.3
COMPARATOR REFERENCE
SELECTION
20.3 Comparator Response Time
Setting the CxR bit of the CMxCON0 register directs an
internal voltage reference or an analog input pin to the
non-inverting input of the comparator. See
Section 21.0 “VOLTAGE REFERENCES” for more
information on the Internal Voltage Reference module.
The comparator output is indeterminate for a period of
time after the change of an input source or the selection
of a new reference voltage. This period is referred to as
the response time. The response time of the
comparator differs from the settling time of the voltage
reference. Therefore, both of these times must be
considered when determining the total response time
to a comparator input change. See the Comparator and
Voltage Reference Specifications in Section 26.0
“Electrical Characteristics” for more details.
20.2.4
COMPARATOR OUTPUT
SELECTION
The output of the comparator can be monitored by
reading either the CxOUT bit of the CMxCON0 register
or the MCxOUT bit of the CM2CON1 register. In order
to make the output available for an external connection,
the following conditions must be true:
• CxOE bit of the CMxCON0 register must be set
• Corresponding TRIS bit must be cleared
• CxON bit of the CMxCON0 register must be set
© 2007 Microchip Technology Inc.
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PIC18F2XK20/4XK20
20.4.1
PRESETTING THE MISMATCH
LATCHES
20.4 Comparator Interrupt Operation
The comparator interrupt flag can be set whenever
there is a change in the output value of the comparator.
Changes are recognized by means of a mismatch
circuit which consists of two latches and an exclusive-
or gate (see Figure 20-2 and Figure 20-3). One latch is
updated with the comparator output level when the
CMxCON0 register is read. This latch retains the value
until the next read of the CMxCON0 register or the
occurrence of a Reset. The other latch of the mismatch
circuit is updated on every Q1 system clock. A
mismatch condition will occur when a comparator
output change is clocked through the second latch on
the Q1 clock cycle. At this point the two mismatch
latches have opposite output levels which is detected
by the exclusive-or gate and fed to the interrupt
circuitry. The mismatch condition persists until either
the CMxCON0 register is read or the comparator
output returns to the previous state.
The comparator mismatch latches can be preset to the
desired state before the comparators are enabled.
When the comparator is off the CxPOL bit controls the
CxOUT level. Set the CxPOL bit to the desired CxOUT
non-interrupt level while the CxON bit is cleared. Then,
configure the desired CxPOL level in the same instruc-
tion that the CxON bit is set. Since all register writes are
performed as a Read-Modify-Write, the mismatch
latches will be cleared during the instruction Read
phase and the actual configuration of the CxON and
CxPOL bits will be occur in the final Write phase.
FIGURE 20-4:
COMPARATOR
INTERRUPT TIMING W/O
CMxCON0 READ
Q1
Q3
Note 1: A write operation to the CMxCON0
register will also clear the mismatch
condition because all writes include a read
operation at the beginning of the write
cycle.
CxIN+
TRT
CxOUT
Set CxIF (edge)
CxIF
reset by software
2: Comparator interrupts will operate correctly
regardless of the state of CxOE.
FIGURE 20-5:
COMPARATOR
INTERRUPT TIMING WITH
CMxCON0 READ
The comparator interrupt is set by the mismatch edge
and not the mismatch level. This means that the inter-
rupt flag can be reset without the additional step of
reading or writing the CMxCON0 register to clear the
mismatch registers. When the mismatch registers are
cleared, an interrupt will occur upon the comparator’s
return to the previous state, otherwise no interrupt will
be generated.
Q1
Q3
CxIN+
TRT
CxOUT
Set CxIF (edge)
CxIF
Software will need to maintain information about the
status of the comparator output, as read from the
CMxCON0 register, or CM2CON1 register, to determine
the actual change that has occurred. See Figures 20-4
and 20-5.
cleared by CMxCON0 read
reset by software
The CxIF bit of the PIR2 register is the comparator
interrupt flag. This bit must be reset by software by
clearing it to ‘0’. Since it is also possible to write a ‘1’ to
this register, an interrupt can be generated.
Note 1: If a change in the CMxCON0 register
(CxOUT) should occur when a read oper-
ation is being executed (start of the Q2
cycle), then the CxIF interrupt flag of the
PIR2 register may not get set.
In mid-range Compatibility mode the CxIE bit of the
PIE2 register and the PEIE and GIE bits of the INTCON
register must all be set to enable comparator interrupts.
If any of these bits are cleared, the interrupt is not
enabled, although the CxIF bit of the PIR2 register will
still be set if an interrupt condition occurs.
2: When either comparator is first enabled,
bias circuitry in the Comparator module
may cause an invalid output from the
comparator until the bias circuitry is stable.
Allow about 1 μs for bias settling then clear
the mismatch condition and interrupt flags
before enabling comparator interrupts.
DS41303B-page 272
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PIC18F2XK20/4XK20
20.5 Operation During Sleep
The comparator, if enabled before entering Sleep mode,
remains active during Sleep. The additional current
consumed by the comparator is shown separately in the
Section 26.0 “Electrical Characteristics”. If the
comparator is not used to wake the device, power
consumption can be minimized while in Sleep mode by
turning off the comparator. Each comparator is turned off
by clearing the CxON bit of the CMxCON0 register.
A change to the comparator output can wake-up the
device from Sleep. To enable the comparator to wake
the device from Sleep, the CxIE bit of the PIE2 register
and the PEIE bit of the INTCON register must be set.
The instruction following the SLEEPinstruction always
executes following a wake from Sleep. If the GIE bit of
the INTCON register is also set, the device will then
execute the Interrupt Service Routine.
20.6 Effects of a Reset
A device Reset forces the CMxCON0 and CM2CON1
registers to their Reset states. This forces both
comparators and the voltage references to their Off
states.
© 2007 Microchip Technology Inc.
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PIC18F2XK20/4XK20
REGISTER 20-1: CM1CON0: COMPARATOR 1 CONTROL REGISTER 0
R/W-0
C1ON
R-0
R/W-0
C1OE
R/W-0
R/W-0
C1SP
R/W-0
C1R
R/W-0
R/W-0
C1OUT
C1POL
C1CH1
C1CH0
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7
bit 6
C1ON: Comparator C1 Enable bit
1= Comparator C1 is enabled
0= Comparator C1 is disabled
C1OUT: Comparator C1 Output bit
If C1POL = 1(inverted polarity):
C1OUT = 0when C1VIN+ > C1VIN-
C1OUT = 1when C1VIN+ < C1VIN-
If C1POL = 0(non-inverted polarity):
C1OUT = 1when C1VIN+ > C1VIN-
C1OUT = 0when C1VIN+ < C1VIN-
bit 5
bit 4
bit 3
bit 2
bit 1-0
C1OE: Comparator C1 Output Enable bit
1= C1OUT is present on the C1OUT pin(1)
0= C1OUT is internal only
C1POL: Comparator C1 Output Polarity Select bit
1= C1OUT logic is inverted
0= C1OUT logic is not inverted
C1SP: Comparator C1 Speed/Power Select bit
1= C1 operates in normal power, higher speed mode
0= C1 operates in low-power, low-speed mode
C1R: Comparator C1 Reference Select bit (non-inverting input)
1= C1VIN+ connects to C1VREF output
0= C1VIN+ connects to C1IN+ pin
C1CH<1:0>: Comparator C1 Channel Select bit
00= C12IN0- pin of C1 connects to C1VIN-
01= C12IN1- pin of C1 connects to C1VIN-
10= C12IN2- pin of C1 connects to C1VIN-
11= C12IN3- pin of C1 connects to C1VIN-
Note 1: Comparator output requires the following three conditions: C1OE = 1, C1ON = 1and corresponding port
TRIS bit = 0.
DS41303B-page 274
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PIC18F2XK20/4XK20
REGISTER 20-2: CM2CON0: COMPARATOR 2 CONTROL REGISTER 0
R/W-0
C2ON
R-0
R/W-0
C2OE
R/W-0
R/W-0
C2SP
R/W-0
C2R
R/W-0
R/W-0
C2OUT
C2POL
C2CH1
C2CH0
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7
bit 6
C2ON: Comparator C2 Enable bit
1= Comparator C2 is enabled
0= Comparator C2 is disabled
C2OUT: Comparator C2 Output bit
If C2POL = 1(inverted polarity):
C2OUT = 0when C2VIN+ > C2VIN-
C2OUT = 1when C2VIN+ < C2VIN-
If C2POL = 0(non-inverted polarity):
C2OUT = 1when C2VIN+ > C2VIN-
C2OUT = 0when C2VIN+ < C2VIN-
bit 5
bit 4
bit 3
bit 2
bit 1-0
C2OE: Comparator C2 Output Enable bit
1= C2OUT is present on C2OUT pin(1)
0= C2OUT is internal only
C2POL: Comparator C2 Output Polarity Select bit
1= C2OUT logic is inverted
0= C2OUT logic is not inverted
C2SP: Comparator C2 Speed/Power Select bit
1= C2 operates in normal power, higher speed mode
0= C2 operates in low-power, low-speed mode
C2R: Comparator C2 Reference Select bits (non-inverting input)
1= C2VIN+ connects to C2VREF
0= C2VIN+ connects to C2IN+ pin
C2CH<1:0>: Comparator C2 Channel Select bits
00= C12IN0- pin of C2 connects to C2VIN-
01= C12IN1- pin of C2 connects to C2VIN-
10= C12IN2- pin of C2 connects to C2VIN-
11= C12IN3- pin of C2 connects to C2VIN-
Note 1: Comparator output requires the following three conditions: C2OE = 1, C2ON = 1and corresponding port
TRIS bit = 0.
© 2007 Microchip Technology Inc.
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PIC18F2XK20/4XK20
20.7 Analog Input Connection
Considerations
Note 1: When reading a PORT register, all pins
configured as analog inputs will read as a
‘0’. Pins configured as digital inputs will
convert as an analog input, according to
the input specification.
A simplified circuit for an analog input is shown in
Figure 20-6. Since the analog input pins share their
connection with a digital input, they have reverse
biased ESD protection diodes to VDD and VSS. The
analog input, therefore, must be between VSS and VDD.
If the input voltage deviates from this range by more
than 0.6V in either direction, one of the diodes is
forward biased and a latch-up may occur.
2: Analog levels on any pin defined as a
digital input, may cause the input buffer to
consume more current than is specified.
A maximum source impedance of 10 kΩ is recommended
for the analog sources. Also, any external component
connected to an analog input pin, such as a capacitor or
a Zener diode, should have very little leakage current to
minimize inaccuracies introduced.
FIGURE 20-6:
ANALOG INPUT MODEL
VDD
VT ≈ 0.6V
RIC
Rs < 10K
AIN
(1)
ILEAKAGE
CPIN
5 pF
VA
VT ≈ 0.6V
Vss
Legend: CPIN
= Input Capacitance
ILEAKAGE = Leakage Current at the pin due to various junctions
RIC
RS
VA
= Interconnect Resistance
= Source Impedance
= Analog Voltage
VT
= Threshold Voltage
Note 1: See Section 26.0 “Electrical Characteristics”.
DS41303B-page 276
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PIC18F2XK20/4XK20
20.8.2
INTERNAL REFERENCE
SELECTION
20.8 Additional Comparator Features
There are two additional comparator features:
There are two internal voltage references available to
the non-inverting input of each comparator. One of
these is the 1.2V Fixed Voltage Reference (FVR) and
the other is the variable Comparator Voltage Reference
(CVREF). The CxRSEL bit of the CM2CON register
determines which of these references is routed to the
Comparator Voltage reference output (CXVREF). Fur-
ther routing to the comparator is accomplished by the
CxR bit of the CMxCON0 register. See Section 21.1
“Comparator Voltage Reference” and Figure 20-2
and Figure 20-3 for more detail.
• Simultaneous read of comparator outputs
• Internal reference selection
20.8.1
SIMULTANEOUS COMPARATOR
OUTPUT READ
The MC1OUT and MC2OUT bits of the CM2CON1
register are mirror copies of both comparator outputs.
The ability to read both outputs simultaneously from a
single register eliminates the timing skew of reading
separate registers.
Note 1: Obtaining the status of C1OUT or C2OUT
by reading CM2CON1 does not affect the
comparator interrupt mismatch registers.
REGISTER 20-3: CM2CON1: COMPARATOR 2 CONTROL REGISTER 1
R-0
R-0
R/W-0
R/W-0
U-0
—
U-0
—
U-0
—
U-0
—
MC1OUT
MC2OUT
C1RSEL
C2RSEL
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
-n = Value at POR
bit 7
bit 6
bit 5
MC1OUT: Mirror Copy of C1OUT bit
MC2OUT: Mirror Copy of C2OUT bit
C1RSEL: Comparator C1 Reference Select bit
1= FVR (1.2 Volt fixed voltage reference) routed to C1VREF input
0= CVREF routed to C1VREF input
bit 4
C2RSEL: Comparator C2 Reference Select bit
1= FVR (1.2 Volt fixed voltage reference) routed to C2VREF input
0= CVREF routed to C2VREF input
bit 3-0
Unimplemented: Read as ‘0’
© 2007 Microchip Technology Inc.
Advance Information
DS41303B-page 277
PIC18F2XK20/4XK20
TABLE 20-2: REGISTERS ASSOCIATED WITH COMPARATOR MODULE
Reset
Values
on page
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
CM1CON0
CM2CON0
C1ON
C2ON
C1OUT
C2OUT
C1OE
C2OE
C1POL
C2POL
C1SP
C2SP
—
C1R
C2R
C1CH1
C2CH1
—
C1CH0
C2CH0
—
60
60
61
59
59
57
60
60
60
60
60
60
CM2CON1 MC1OUT MC2OUT C1RSEL C2RSEL
—
CVRCON
CVRCON2
INTCON
PIR2
CVREN
FVREN
CVROE
FVRST
CVRR
—
CVRSS
—
CVR3
—
CVR2
—
CVR1
—
CVR0
—
GIE/GIEH PEIE/GIEL TMR0IE
INT0IE
EEIF
EEIE
EEIP
RA4
RBIE
BCLIF
BCLIE
BCLIP
RA3
TMR0IF
HLVDIF
INT0IF
RBIF
OSCFIF
OSCFIE
OSCFIP
RA7(1)
C1IF
C1IE
C2IF
C2IE
C2IP
RA5
TMR3IF CCP2IF
PIE2
HLVDIE TMR3IE CCP2IE
HLVDIP TMR3IP CCP2IP
IPR2
C1IP
RA6(1)
PORTA
LATA
RA2
RA1
RA0
LATA7(1)
LATA6(1) PORTA Data Latch Register (Read and Write to Data Latch)
TRISA
TRISA7(1) TRISA6(1) PORTA Data Direction Control Register
Legend: — = unimplemented, read as ‘0’. Shaded cells are unused by the comparator module.
Note 1: PORTA<7:6> and their direction and latch bits are individually configured as port pins based on various
primary oscillator modes. When disabled, these bits read as ‘0’.
DS41303B-page 278
Advance Information
© 2007 Microchip Technology Inc.
PIC18F2XK20/4XK20
21.1.3
OUTPUT CLAMPED TO VSS
21.0 VOLTAGE REFERENCES
The CVREF output voltage can be set to Vss with no
power consumption by configuring CVRCON as
follows:
There are two independent voltage references
available:
• Programmable Comparator Voltage Reference
• 1.2V Fixed Voltage Reference
• CVREN = 0
• CVRR = 1
• CVR<3:0> = 0000
21.1 Comparator Voltage Reference
This allows the comparator to detect a zero-crossing
while not consuming additional CVREF module current.
The Comparator Voltage Reference module provides
an internally generated voltage reference for the com-
parators. The following features are available:
21.1.4
OUTPUT RATIOMETRIC TO VDD
• Independent from Comparator operation
• Two 16-level voltage ranges
• Output clamped to VSS
The comparator voltage reference is VDD derived and
therefore, the CVREF output changes with fluctuations in
VDD. The tested absolute accuracy of the Comparator
Voltage Reference can be found in Section 26.0
“Electrical Characteristics”.
• Ratiometric with VDD
• 1.2 Fixed Reference Voltage (FVR)
The CVRCON register (Figure 21-1) controls the
Voltage Reference module shown in Figure 21-1.
21.1.5
VOLTAGE REFERENCE OUTPUT
The CVREF voltage reference can be output to the
device CVREF pin by setting the CVROE bit of the CVR-
CON register to ‘1’. Selecting the reference voltage for
output on the CVREF pin automatically overrides the
digital output buffer and digital input threshold detector
functions of that pin. Reading the CVREF pin when it
has been configured for reference voltage output will
always return a ‘0’.
21.1.1
INDEPENDENT OPERATION
The comparator voltage reference is independent of
the comparator configuration. Setting the CVREN bit of
the CVRCON register will enable the voltage reference
by allowing current to flow in the CVREF voltage divider.
When both the CVREN bit is cleared, current flow in the
CVREF voltage divider is disabled minimizing the power
drain of the voltage reference peripheral.
Due to the limited current drive capability, a buffer must
be used on the voltage reference output for external
connections to CVREF. Figure 21-2 shows an example
buffering technique.
21.1.2
OUTPUT VOLTAGE SELECTION
The CVREF voltage reference has 2 ranges with 16
voltage levels in each range. Range selection is
controlled by the CVRR bit of the CVRCON register.
The 16 levels are set with the CVR<3:0> bits of the
CVRCON register.
21.1.6
OPERATION DURING SLEEP
When the device wakes up from Sleep through an
interrupt or a Watchdog Timer time-out, the contents of
the CVRCON register are not affected. To minimize
current consumption in Sleep mode, the voltage
reference should be disabled.
The CVREF output voltage is determined by the following
equations:
21.1.7
EFFECTS OF A RESET
EQUATION 21-1: CVREF OUTPUT VOLTAGE
A device Reset affects the following:
CVRR = 1 (low range):
CVREF = (VR<3:0>/24) × CVRSRC
• Comparator voltage reference is disabled
• Fixed voltage reference is disabled
CVRR = 0 (high range):
• CVREF is removed from the CVREF pin
• The high-voltage range is selected
CVREF = (CVRSRC/4) + (VR<3:0> × CVRSRC/32)
CVRSRC = VDD or [(VREF+) - (VREF-)]
• The CVR<3:0> range select bits are cleared
The full range of VSS to VDD cannot be realized due to
the construction of the module. See Figure 21-1.
© 2007 Microchip Technology Inc.
Advance Information
DS41303B-page 279
PIC18F2XK20/4XK20
21.2.1
FVR STABILIZATION PERIOD
21.2 FVR Reference Module
When the Fixed Voltage Reference module is enabled, it
will require some time for the reference and its amplifier
circuits to stabilize. The user program must include a
small delay routine to allow the module to settle. The
FVRST stable bit of the CVRCON2 register also indicates
that the FVR reference has been operating long enough
to be stable. See Section 26.0 “Electrical
Characteristics” for the minimum delay requirement.
The FVR reference is a stable fixed voltage reference,
independent of VDD, with a nominal output voltage of
1.2V. This reference can be enabled by setting the
FVREN bit of the CVRCON2 register to ‘1’. The FVR
defaults to on when any one or more of the HFINTOSC,
HLVD, or BOR functions are enabled. The FVR voltage
reference can be routed to the comparators or an ADC
input channel.
FIGURE 21-1:
VOLTAGE REFERENCE BLOCK DIAGRAM
CVRSS = 1
VREF+
VDD
8R
CVRSS = 0
CVR<3:0>
R
CVREN
R
R
R
16 Steps
CVREF
R
R
R
CVRR
8R
CVRSS = 1
VREF-
CVRSS = 0
FVR
1.2 Volt Fixed
FVREN
Reference
FVRST
From HVLD and
BOR circuits
EN
DS41303B-page 280
Advance Information
© 2007 Microchip Technology Inc.
PIC18F2XK20/4XK20
FIGURE 21-2:
VOLTAGE REFERENCE OUTPUT BUFFER EXAMPLE
PIC18F2XK20/4XK20
CVREF
(1)
R
Module
+
–
Buffered CVREF Output
CVREF
Voltage
Reference
Output
Impedance
Note 1: R is dependent upon the voltage reference Configuration bits, CVR<3:0> and CVRR.
REGISTER 21-1: CVRCON: COMPARATOR VOLTAGE REFERENCE CONTROL REGISTER
R/W-0
R/W-0
CVROE(1)
R/W-0
CVRR
R/W-0
R/W-0
CVR3
R/W-0
CVR2
R/W-0
CVR1
R/W-0
CVR0
CVREN
CVRSS
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
-n = Value at POR
bit 7
bit 6
CVREN: Comparator Voltage Reference Enable bit
1= CVREF circuit powered on
0= CVREF circuit powered down
CVROE: Comparator VREF Output Enable bit(1)
1= CVREF voltage level is also output on the CVREF pin
0= CVREF voltage is disconnected from the CVREF pin
bit 5
CVRR: Comparator VREF Range Selection bit
1= 0 to 0.667 CVRSRC, with CVRSRC/24 step size (low range)
0= 0.25 CVRSRC to 0.75 CVRSRC, with CVRSRC/32 step size (high range)
bit 4
CVRSS: Comparator VREF Source Selection bit
1= Comparator reference source, CVRSRC = (VREF+) – (VREF-)
0= Comparator reference source, CVRSRC = VDD – VSS
bit 3-0
CVR<3:0>: Comparator VREF Value Selection bits (0 ≤ (CVR<3:0>) ≤ 15)
When CVRR = 1:
CVREF = ((CVR<3:0>)/24) • (CVRSRC)
When CVRR = 0:
CVREF = (CVRSRC/4) + ((CVR<3:0>)/32) • (CVRSRC)
Note 1: CVROE overrides the TRISA<2> bit setting.
© 2007 Microchip Technology Inc.
Advance Information
DS41303B-page 281
PIC18F2XK20/4XK20
REGISTER 21-2: CVRCON2: COMPARATOR VOLTAGE REFERENCE CONTROL 2 REGISTER
R/W-0
R-0
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
FVREN
FVRST
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7
bit 6
FVREN: Fixed Voltage Reference Enable bit
1= FVR circuit powered on
0= FVR circuit not enabled by FVREN. Other peripherals may enable FVR.
FVRST: Fixed Voltage Stable Status bit
1= FVR is stable and can be used.
0= FVR is not stable and should not be used.
bit 5-0
Unimplemented: Read as ‘0’.
TABLE 21-1: REGISTERS ASSOCIATED WITH COMPARATOR VOLTAGE REFERENCE
Reset
Values
on page
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
CVRCON
CVRCON2
CM1CON0
CM2CON0
CM2CON1
TRISA
CVREN
FVREN
C1ON
CVROE
FVRST
C1OUT
C2OUT
CVRR
—
CVRSS
—
CVR3
—
CVR2
—
CVR1
—
CVR0
—
60
59
60
60
61
60
C1OE
C2OE
C1POL
C2POL
C1SP
C2SP
—
C1R
C2R
—
C1CH1
C2CH1
—
C1CH0
C2CH0
—
C2ON
MC1OUT MC2OUT C1RSEL C2RSEL
TRISA7(1) TRISA6(1) PORTA Data Direction Control Register
Legend: Shaded cells are not used with the comparator voltage reference.
Note 1: PORTA pins are enabled based on oscillator configuration.
DS41303B-page 282
Advance Information
© 2007 Microchip Technology Inc.
PIC18F2XK20/4XK20
The block diagram for the HLVD module is shown in
Figure 22-1.
22.0 HIGH/LOW-VOLTAGE
DETECT (HLVD)
The module is enabled by setting the HLVDEN bit.
Each time that the HLVD module is enabled, the cir-
cuitry requires some time to stabilize. The IRVST bit is
a read-only bit and is used to indicate when the circuit
is stable. The module can only generate an interrupt
after the circuit is stable and IRVST is set.
PIC18F2XK20/4XK20 devices have a High/Low-Voltage
Detect module (HLVD). This is a programmable circuit
that allows the user to specify both a device voltage trip
point and the direction of change from that point. If the
device experiences an excursion past the trip point in
that direction, an interrupt flag is set. If the interrupt is
enabled, the program execution will branch to the inter-
rupt vector address and the software can then respond
to the interrupt.
The VDIRMAG bit determines the overall operation of
the module. When VDIRMAG is cleared, the module
monitors for drops in VDD below a predetermined set
point. When the bit is set, the module monitors for rises
in VDD above the set point.
The High/Low-Voltage Detect Control register
(Register 22-1) completely controls the operation of the
HLVD module. This allows the circuitry to be “turned
off” by the user under software control, which
minimizes the current consumption for the device.
REGISTER 22-1: HLVDCON: HIGH/LOW-VOLTAGE DETECT CONTROL REGISTER
R/W-0
U-0
—
R-0
R/W-0
R/W-0
HLVDL3(1)
R/W-1
HLVDL2(1)
R/W-0
HLVDL1(1)
R/W-1
HLVDL0(1)
VDIRMAG
IRVST
HLVDEN
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented
‘0’ = Bit is cleared
C = Clearable only bit
x = Bit is unknown
bit 7
VDIRMAG: Voltage Direction Magnitude Select bit
1= Event occurs when voltage equals or exceeds trip point (HLVDL<3:0>)
0= Event occurs when voltage equals or falls below trip point (HLVDL<3:0>)
bit 6
bit 5
Unimplemented: Read as ‘0’
IRVST: Internal Reference Voltage Stable Flag bit
1= Indicates that the voltage detect logic will generate the interrupt flag at the specified voltage range
0= Indicates that the voltage detect logic will not generate the interrupt flag at the specified voltage
range and the HLVD interrupt should not be enabled
bit 4
HLVDEN: High/Low-Voltage Detect Power Enable bit
1= HLVD enabled
0= HLVD disabled
bit 3-0
HLVDL<3:0>: Voltage Detection Limit bits(1)
1111= External analog input is used (input comes from the HLVDIN pin)
1110= Maximum setting
.
.
.
0000= Minimum setting
Note 1: See Table 26-3 for specifications.
© 2007 Microchip Technology Inc.
Advance Information
DS41303B-page 283
PIC18F2XK20/4XK20
The trip point voltage is software programmable to any
one of 16 values. The trip point is selected by
programming the HLVDL<3:0> bits of the HLVDCON
register.
22.1 Operation
When the HLVD module is enabled, a comparator uses
an internally generated reference voltage as the set
point. The set point is compared with the trip point,
where each node in the resistor divider represents a
trip point voltage. The “trip point” voltage is the voltage
level at which the device detects a high or low-voltage
event, depending on the configuration of the module.
When the supply voltage is equal to the trip point, the
voltage tapped off of the resistor array is equal to the
internal reference voltage generated by the voltage
reference module. The comparator then generates an
interrupt signal by setting the HLVDIF bit.
The HLVD module has an additional feature that allows
the user to supply the trip voltage to the module from an
external source. This mode is enabled when bits
HLVDL<3:0> are set to ‘1111’. In this state, the
comparator input is multiplexed from the external input
pin, HLVDIN. This gives users flexibility because it
allows them to configure the High/Low-Voltage Detect
interrupt to occur at any voltage in the valid operating
range.
FIGURE 22-1:
HLVD MODULE BLOCK DIAGRAM (WITH EXTERNAL INPUT)
Externally Generated
Trip Point
VDD
VDD
HLVDL<3:0>
HLVDCON
Register
HLVDIN
VDIRMAG
HLVDEN
HLVDIN
Set
HLVDIF
HLVDEN
BOREN
Internal Voltage
Reference
DS41303B-page 284
Advance Information
© 2007 Microchip Technology Inc.
PIC18F2XK20/4XK20
Depending on the application, the HLVD module does
not need to be operating constantly. To decrease the
current requirements, the HLVD circuitry may only
need to be enabled for short periods where the voltage
is checked. After doing the check, the HLVD module
may be disabled.
22.2 HLVD Setup
The following steps are needed to set up the HLVD
module:
1. Write the value to the HLVDL<3:0> bits that
selects the desired HLVD trip point.
2. Set the VDIRMAG bit to detect high voltage
22.4 HLVD Start-up Time
(VDIRMAG = 1) or low voltage (VDIRMAG = 0).
3. Enable the HLVD module by setting the
HLVDEN bit.
The internal reference voltage of the HLVD module,
specified in electrical specification parameter D420,
may be used by other internal circuitry, such as the
Programmable Brown-out Reset. If the HLVD or other
circuits using the voltage reference are disabled to
lower the device’s current consumption, the reference
voltage circuit will require time to become stable before
a low or high-voltage condition can be reliably
detected. This start-up time, TIRVST, is an interval that
is independent of device clock speed. It is specified in
electrical specification parameter 36.
4. Clear the HLVD interrupt flag bit of the PIR2
register, which may have been set from a
previous interrupt.
5. Enable the HLVD interrupt if interrupts are
desired by setting the HLVDIE bit of the PIE2
register, and the GIE and PEIE bits of the
INTCON register. An interrupt will not be gener-
ated until the IRVST bit is set.
22.3 Current Consumption
The HLVD interrupt flag is not enabled until TIRVST has
expired and a stable reference voltage is reached. For
this reason, brief excursions beyond the set point may
not be detected during this interval. Refer to Figure 22-2
or Figure 22-3.
When the module is enabled, the HLVD comparator
and voltage divider are enabled and will consume static
current. The total current consumption, when enabled,
is specified in electrical specification parameter D022B.
FIGURE 22-2:
LOW-VOLTAGE DETECT OPERATION (VDIRMAG = 0)
CASE 1:
HLVDIF may not be set
VDD
VHLVD
HLVDIF
Enable HLVD
IRVST
TIVRST
HLVDIF cleared by software
Internal Reference is stable
CASE 2:
VDD
VHLVD
HLVDIF
Enable HLVD
TIVRST
IRVST
Internal Reference is stable
HLVDIF cleared by software
HLVDIF cleared by software,
HLVDIF remains set since HLVD condition still exists
© 2007 Microchip Technology Inc.
Advance Information
DS41303B-page 285
PIC18F2XK20/4XK20
FIGURE 22-3:
HIGH-VOLTAGE DETECT OPERATION (VDIRMAG = 1)
CASE 1:
HLVDIF may not be set
VHLVD
VDD
HLVDIF
Enable HLVD
IRVST
TIVRST
HLVDIF cleared by software
Internal Reference is stable
CASE 2:
VHLVD
VDD
HLVDIF
Enable HLVD
TIVRST
IRVST
Internal Reference is stable
HLVDIF cleared by software
HLVDIF cleared by software,
HLVDIF remains set since HLVD condition still exists
DS41303B-page 286
Advance Information
© 2007 Microchip Technology Inc.
PIC18F2XK20/4XK20
FIGURE 22-4:
TYPICAL LOW-VOLTAGE
DETECT APPLICATION
22.5 Applications
In many applications, the ability to detect a drop below,
or rise above, a particular threshold is desirable. For
example, the HLVD module could be periodically
enabled to detect Universal Serial Bus (USB) attach or
detach. This assumes the device is powered by a lower
voltage source than the USB when detached. An attach
would indicate a high-voltage detect from, for example,
3.3V to 5V (the voltage on USB) and vice versa for a
detach. This feature could save a design a few extra
components and an attach signal (input pin).
VA
VB
For general battery applications, Figure 22-4 shows a
possible voltage curve. Over time, the device voltage
decreases. When the device voltage reaches voltage
VA, the HLVD logic generates an interrupt at time TA.
The interrupt could cause the execution of an ISR,
which would allow the application to perform
TB
VA = HLVD trip point
TA
Time
“housekeeping tasks” and perform
a
controlled
Legend:
VB = Minimum valid device
shutdown before the device voltage exits the valid
operating range at TB. The HLVD, thus, would give the
operating voltage
application
a time window, represented by the
difference between TA and TB, to safely exit.
TABLE 22-1: REGISTERS ASSOCIATED WITH HIGH/LOW-VOLTAGE DETECT MODULE
Reset
Values
on Page
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
HLVDCON VDIRMAG
—
IRVST
HLVDEN HLVDL3 HLVDL2 HLVDL1 HLVDL0
58
57
60
60
60
INTCON
PIR2
GIE/GIEH PEIE/GIEL TMR0IE
INT0IE
EEIF
RBIE
BCLIF
BCLIE
BCLIP
TMR0IF
HLVDIF
INT0IF
RBIF
OSCFIF
OSCFIE
OSCFIP
C1IF
C1IE
C1IP
C2IF
C2IE
C2IP
TMR3IF CCP2IF
PIE2
EEIE
EEIP
HLVDIE TMR3IE CCP2IE
HLVDIP TMR3IP CCP2IP
IPR2
Legend: — = unimplemented, read as ‘0’. Shaded cells are unused by the HLVD module.
© 2007 Microchip Technology Inc.
Advance Information
DS41303B-page 287
PIC18F2XK20/4XK20
NOTES:
DS41303B-page 288
Advance Information
© 2007 Microchip Technology Inc.
PIC18F2XK20/4XK20
23.0 SPECIAL FEATURES OF
THE CPU
PIC18F2XK20/4XK20 devices include several features
intended to maximize reliability and minimize cost through
elimination of external components. These are:
• Oscillator Selection
• Resets:
- Power-on Reset (POR)
- Power-up Timer (PWRT)
- Oscillator Start-up Timer (OST)
- Brown-out Reset (BOR)
• Interrupts
• Watchdog Timer (WDT)
• Code Protection
• ID Locations
• In-Circuit Serial Programming™
The oscillator can be configured for the application
depending on frequency, power, accuracy and cost. All
of the options are discussed in detail in Section 2.0
“Oscillator Module (With Fail-Safe Clock Monitor)”.
A complete discussion of device Resets and interrupts
is available in previous sections of this data sheet.
In addition to their Power-up and Oscillator Start-up
Timers provided for Resets, PIC18F2XK20/4XK20
devices have a Watchdog Timer, which is either
permanently enabled via the Configuration bits or
software controlled (if configured as disabled).
The inclusion of an internal RC oscillator also provides
the additional benefits of a Fail-Safe Clock Monitor
(FSCM) and Two-Speed Start-up. FSCM provides for
background monitoring of the peripheral clock and
automatic switchover in the event of its failure. Two-
Speed Start-up enables code to be executed almost
immediately on start-up, while the primary clock source
completes its start-up delays.
All of these features are enabled and configured by
setting the appropriate Configuration register bits.
© 2007 Microchip Technology Inc.
Advance Information
DS41303B-page 289
PIC18F2XK20/4XK20
23.1 Configuration Bits
The Configuration bits can be programmed (read as
‘0’) or left unprogrammed (read as ‘1’) to select various
device configurations. These bits are mapped starting
at program memory location 300000h.
The user will note that address 300000h is beyond the
user program memory space. In fact, it belongs to the
configuration memory space (300000h-3FFFFFh), which
can only be accessed using table reads and table writes.
Programming the Configuration registers is done in a
manner similar to programming the Flash memory. The
WR bit in the EECON1 register starts a self-timed write
to the Configuration register. In normal operation mode,
a TBLWT instruction with the TBLPTR pointing to the
Configuration register sets up the address and the data
for the Configuration register write. Setting the WR bit
starts a long write to the Configuration register. The
Configuration registers are written a byte at a time. To
write or erase a configuration cell, a TBLWTinstruction
can write a ‘1’ or a ‘0’ into the cell. For additional details
on Flash programming, refer to Section 6.5 “Writing
to Flash Program Memory”.
TABLE 23-1: CONFIGURATION BITS AND DEVICE IDs
Default/
Unprogrammed
Value
File Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
300001h CONFIG1H IESO
FCMEN
—
—
—
FOSC3
BORV0
FOSC2
FOSC1
FOSC0
00-- 0111
---1 1111
---1 1111
1--- 1011
10-- -1-1
---- 1111
11-- ----
---- 1111
111- ----
---- 1111
-1-- ----
300002h CONFIG2L
300003h CONFIG2H
—
—
—
—
—
BORV1
BOREN1 BOREN0 PWRTEN
—
WDTPS3 WDTPS2 WDTPS1 WDTPS0 WDTEN
300005h CONFIG3H MCLRE
—
—
—
HFOFST LPT1OSC PBADEN CCP2MX
300006h CONFIG4L DEBUG XINST
—
—
CP3
—
LVP
—
CP1
—
STVREN
CP0
(1)
(1)
300008h CONFIG5L
300009h CONFIG5H
30000Ah CONFIG6L
—
CPD
—
—
CPB
—
—
—
CP2
—
—
—
—
(1)
(1)
—
—
WRT3
—
WRT2
—
WRT1
—
WRT0
—
30000Bh CONFIG6H WRTD
WRTB
—
WRTC
—
—
(1)
(1)
30000Ch CONFIG7L
30000Dh CONFIG7H
—
—
—
EBTR3
—
EBTR2
—
EBTR1
—
EBTR0
—
EBTRB
DEV1
DEV9
—
—
(2)
(2)
3FFFFEh DEVID1
DEV2
DEV10
DEV0
DEV8
REV4
DEV7
REV3
DEV6
REV2
DEV5
REV1
DEV4
REV0
DEV3
qqqq qqqq
(2)
3FFFFFh DEVID2
0000 1100
Legend:
x= unknown, u= unchanged, – = unimplemented, q= value depends on condition.
Shaded cells are unimplemented, read as ‘0’.
Note 1: Unimplemented in PIC18FX3K20 and PIC18FX4K20 devices; maintain this bit set.
2: See Register 23-12 for DEVID1 values. DEVID registers are read-only and cannot be programmed by the user.
DS41303B-page 290
Advance Information
© 2007 Microchip Technology Inc.
PIC18F2XK20/4XK20
REGISTER 23-1: CONFIG1H: CONFIGURATION REGISTER 1 HIGH
R/P-0
IESO
R/P-0
U-0
—
U-0
—
R/P-0
R/P-1
R/P-1
R/P-1
FCMEN
FOSC3
FOSC2
FOSC1
FOSC0
bit 7
bit 0
Legend:
R = Readable bit
P = Programmable bit
U = Unimplemented bit, read as ‘0’
x = Bit is unknown
-n = Value when device is unprogrammed
bit 7
bit 6
IESO: Internal/External Oscillator Switchover bit
1= Oscillator Switchover mode enabled
0= Oscillator Switchover mode disabled
FCMEN: Fail-Safe Clock Monitor Enable bit
1= Fail-Safe Clock Monitor enabled
0= Fail-Safe Clock Monitor disabled
bit 5-4
bit 3-0
Unimplemented: Read as ‘0’
FOSC<3:0>: Oscillator Selection bits
11xx= External RC oscillator, CLKOUT function on RA6
101x= External RC oscillator, CLKOUT function on RA6
1001= Internal oscillator block, CLKOUT function on RA6, port function on RA7
1000= Internal oscillator block, port function on RA6 and RA7
0111= External RC oscillator, port function on RA6
0110= HS oscillator, PLL enabled (Clock Frequency = 4 x FOSC1)
0101= EC oscillator, port function on RA6
0100= EC oscillator, CLKOUT function on RA6
0011= External RC oscillator, CLKOUT function on RA6
0010= HS oscillator
0001= XT oscillator
0000= LP oscillator
© 2007 Microchip Technology Inc.
Advance Information
DS41303B-page 291
PIC18F2XK20/4XK20
REGISTER 23-2: CONFIG2L: CONFIGURATION REGISTER 2 LOW
U-0
—
U-0
—
U-0
—
R/P-1
R/P-1
R/P-1
R/P-1
R/P-1
BORV1(1)
BORV0(1)
BOREN1(2)
BOREN0(2)
PWRTEN(2)
bit 7
bit 0
Legend:
R = Readable bit
P = Programmable bit
U = Unimplemented bit, read as ‘0’
x = Bit is unknown
-n = Value when device is unprogrammed
bit 7-5
bit 4-3
Unimplemented: Read as ‘0’
BORV<1:0>: Brown-out Reset Voltage bits(1)
11= VBOR set to 1.8V nominal
10= VBOR set to 2.2V nominal
01= VBOR set to 2.7V nominal
00= VBOR set to 3.0V nominal
bit 2-1
BOREN<1:0>: Brown-out Reset Enable bits(2)
11= Brown-out Reset enabled in hardware only (SBOREN is disabled)
10= Brown-out Reset enabled in hardware only and disabled in Sleep mode
(SBOREN is disabled)
01= Brown-out Reset enabled and controlled by software (SBOREN is enabled)
00= Brown-out Reset disabled in hardware and software
bit 0
PWRTEN: Power-up Timer Enable bit(2)
1= PWRT disabled
0= PWRT enabled
Note 1: See Section 26.1 “DC Characteristics: Supply Voltage” for specifications.
2: The Power-up Timer is decoupled from Brown-out Reset, allowing these features to be independently controlled.
REGISTER 23-3: CONFIG2H: CONFIGURATION REGISTER 2 HIGH
U-0
—
U-0
—
U-0
—
R/P-1
R/P-1
R/P-1
R/P-1
R/P-1
WDTEN
bit 0
WDTPS3
WDTPS2
WDTPS1
WDTPS0
bit 7
Legend:
R = Readable bit
P = Programmable bit
U = Unimplemented bit, read as ‘0’
x = Bit is unknown
-n = Value when device is unprogrammed
bit 7-5
bit 4-1
Unimplemented: Read as ‘0’
WDTPS<3:0>: Watchdog Timer Postscale Select bits
1111= 1:32,768
1110= 1:16,384
1101= 1:8,192
1100= 1:4,096
1011= 1:2,048
1010= 1:1,024
1001= 1:512
1000= 1:256
0111= 1:128
0110= 1:64
0101= 1:32
0100= 1:16
0011= 1:8
0010= 1:4
0001= 1:2
0000= 1:1
bit 0
WDTEN: Watchdog Timer Enable bit
1= WDT is always enabled. SWDTEN bit has no effect
0= WDT is controlled by SWDTEN bit of the WDTCON register
DS41303B-page 292
Advance Information
© 2007 Microchip Technology Inc.
PIC18F2XK20/4XK20
REGISTER 23-4: CONFIG3H: CONFIGURATION REGISTER 3 HIGH
R/P-1
U-0
—
U-0
—
U-0
—
R/P-1
R/P-0
R/P-1
R/P-1
MCLRE
HFOFST
LPT1OSC
PBADEN
CCP2MX
bit 7
bit 0
Legend:
R = Readable bit
P = Programmable bit
U = Unimplemented bit, read as ‘0’
x = Bit is unknown
-n = Value when device is unprogrammed
bit 7
MCLRE: MCLR Pin Enable bit
1= MCLR pin enabled; RE3 input pin disabled
0= RE3 input pin enabled; MCLR disabled
bit 6-4
bit 3
Unimplemented: Read as ‘0’
HFOFST: HFINTOSC Fast Start-up
1= HFINTOSC starts clocking the CPU without waiting for the oscillator to stabilize.
0= The system clock is held off until the HFINTOSC is stable.
bit 2
bit 1
LPT1OSC: Low-Power Timer1 Oscillator Enable bit
1= Timer1 configured for low-power operation
0= Timer1 configured for higher power operation
PBADEN: PORTB A/D Enable bit
(Affects ADCON1 Reset state. ADCON1 controls PORTB<4:0> pin configuration.)
1= PORTB<4:0> pins are configured as analog input channels on Reset
0= PORTB<4:0> pins are configured as digital I/O on Reset
bit 0
CCP2MX: CCP2 MUX bit
1= CCP2 input/output is multiplexed with RC1
0= CCP2 input/output is multiplexed with RB3
REGISTER 23-5: CONFIG4L: CONFIGURATION REGISTER 4 LOW
R/P-1
R/P-0
U-0
—
U-0
—
U-0
—
R/P-1
LVP
U-0
—
R/P-1
DEBUG
XINST
STVREN
bit 7
bit 0
Legend:
R = Readable bit
P = Programmable bit
U = Unimplemented bit, read as ‘0’
x = Bit is unknown
-n = Value when device is unprogrammed
bit 7
bit 6
DEBUG: Background Debugger Enable bit
1= Background debugger disabled, RB6 and RB7 configured as general purpose I/O pins
0= Background debugger enabled, RB6 and RB7 are dedicated to In-Circuit Debug
XINST: Extended Instruction Set Enable bit
1= Instruction set extension and Indexed Addressing mode enabled
0= Instruction set extension and Indexed Addressing mode disabled (Legacy mode)
bit 5-3
bit 2
Unimplemented: Read as ‘0’
LVP: Single-Supply ICSP Enable bit
1= Single-Supply ICSP enabled
0= Single-Supply ICSP disabled
bit 1
bit 0
Unimplemented: Read as ‘0’
STVREN: Stack Full/Underflow Reset Enable bit
1= Stack full/underflow will cause Reset
0= Stack full/underflow will not cause Reset
© 2007 Microchip Technology Inc.
Advance Information
DS41303B-page 293
PIC18F2XK20/4XK20
REGISTER 23-6: CONFIG5L: CONFIGURATION REGISTER 5 LOW
R/C-1
CP0
U-0
—
U-0
—
U-0
—
U-0
—
R/C-1
CP3(1)
R/C-1
CP2(1)
R/C-1
CP1
bit 0
bit 7
Legend:
R = Readable bit
U = Unimplemented bit, read as ‘0’
C = Clearable only bit
-n = Value when device is unprogrammed
bit 7-4
bit 3
Unimplemented: Read as ‘0’
CP3: Code Protection bit(1)
1= Block 3 not code-protected
0= Block 3 code-protected
bit 2
bit 1
bit 0
CP2: Code Protection bit(1)
1= Block 2 not code-protected
0= Block 2 code-protected
CP1: Code Protection bit
1= Block 1 not code-protected
0= Block 1 code-protected
CP0: Code Protection bit
1= Block 0 not code-protected
0= Block 0 code-protected
Note 1: Unimplemented in PIC18FX3K20 and PIC18FX4K20 devices; maintain this bit set.
REGISTER 23-7: CONFIG5H: CONFIGURATION REGISTER 5 HIGH
U-0
—
R/C-1
CPD
R/C-1
CPB
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
bit 0
bit 7
Legend:
R = Readable bit
U = Unimplemented bit, read as ‘0’
C = Clearable only bit
-n = Value when device is unprogrammed
bit 7
CPD: Data EEPROM Code Protection bit
1= Data EEPROM not code-protected
0= Data EEPROM code-protected
bit 6
CPB: Boot Block Code Protection bit
1= Boot block not code-protected
0= Boot block code-protected
bit 5-0
Unimplemented: Read as ‘0’
DS41303B-page 294
Advance Information
© 2007 Microchip Technology Inc.
PIC18F2XK20/4XK20
REGISTER 23-8: CONFIG6L: CONFIGURATION REGISTER 6 LOW
R/C-1
WRT0
U-0
—
U-0
—
U-0
—
U-0
—
R/C-1
WRT3(1)
R/C-1
WRT2(1)
R/C-1
WRT1
bit 0
bit 7
Legend:
R = Readable bit
U = Unimplemented bit, read as ‘0’
C = Clearable only bit
-n = Value when device is unprogrammed
bit 7-4
bit 3
Unimplemented: Read as ‘0’
WRT3: Write Protection bit(1)
1= Block 3 not write-protected
0= Block 3 write-protected
bit 2
bit 1
bit 0
WRT2: Write Protection bit(1)
1= Block 2 not write-protected
0= Block 2 write-protected
WRT1: Write Protection bit
1= Block 1 not write-protected
0= Block 1 write-protected
WRT0: Write Protection bit
1= Block 0 not write-protected
0= Block 0 write-protected
Note 1: Unimplemented in PIC18FX3K20 and PIC18FX4K20 devices; maintain this bit set.
REGISTER 23-9: CONFIG6H: CONFIGURATION REGISTER 6 HIGH
R/C-1
R/C-1
R-1
WRTC(1)
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
WRTD
WRTB
bit 7
bit 0
Legend:
R = Readable bit
U = Unimplemented bit, read as ‘0’
C = Clearable only bit
-n = Value when device is unprogrammed
bit 7
bit 6
bit 5
WRTD: Data EEPROM Write Protection bit
1= Data EEPROM not write-protected
0= Data EEPROM write-protected
WRTB: Boot Block Write Protection bit
1= Boot block not write-protected
0= Boot block write-protected
WRTC: Configuration Register Write Protection bit(1)
1= Configuration registers not write-protected
0= Configuration registers write-protected
bit 4-0
Unimplemented: Read as ‘0’
Note 1: This bit is read-only in normal execution mode; it can be written only in Program mode.
© 2007 Microchip Technology Inc.
Advance Information
DS41303B-page 295
PIC18F2XK20/4XK20
REGISTER 23-10: CONFIG7L: CONFIGURATION REGISTER 7 LOW
U-0
—
U-0
—
U-0
—
U-0
—
R/C-1
EBTR3(1)
R/C-1
EBTR2(1)
R/C-1
R/C-1
EBTR1
EBTR0
bit 7
bit 0
Legend:
R = Readable bit
U = Unimplemented bit, read as ‘0’
C = Clearable only bit
-n = Value when device is unprogrammed
bit 7-4
bit 3
Unimplemented: Read as ‘0’
EBTR3: Table Read Protection bit(1)
1= Block 3 not protected from table reads executed in other blocks
0= Block 3 protected from table reads executed in other blocks
bit 2
bit 1
bit 0
EBTR2: Table Read Protection bit(1)
1= Block 2 not protected from table reads executed in other blocks
0= Block 2 protected from table reads executed in other blocks
EBTR1: Table Read Protection bit
1= Block 1 not protected from table reads executed in other blocks
0= Block 1 protected from table reads executed in other blocks
EBTR0: Table Read Protection bit
1= Block 0 not protected from table reads executed in other blocks
0= Block 0 protected from table reads executed in other blocks
Note 1: Unimplemented in PIC18FX3K20 and PIC18FX4K20 devices; maintain this bit set.
REGISTER 23-11: CONFIG7H: CONFIGURATION REGISTER 7 HIGH
U-0
—
R/C-1
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
EBTRB
bit 7
bit 0
Legend:
R = Readable bit
U = Unimplemented bit, read as ‘0’
C = Clearable only bit
-n = Value when device is unprogrammed
bit 7
bit 6
Unimplemented: Read as ‘0’
EBTRB: Boot Block Table Read Protection bit
1= Boot block not protected from table reads executed in other blocks
0= Boot block protected from table reads executed in other blocks
bit 5-0
Unimplemented: Read as ‘0’
DS41303B-page 296
Advance Information
© 2007 Microchip Technology Inc.
PIC18F2XK20/4XK20
REGISTER 23-12: DEVID1: DEVICE ID REGISTER 1 FOR PIC18F2XK20/4XK20
R
R
R
R
R
R
R
R
DEV2
DEV1
DEV0
REV4
REV3
REV2
REV1
REV0
bit 7
bit 0
Legend:
R = Readable bit
U = Unimplemented bit, read as ‘0’
C = Clearable only bit
-n = Value when device is unprogrammed
bit 7-5
DEV<2:0>: Device ID bits
010= PIC18F45K20
011= PIC18F25K20
100= PIC18F44K20
101= PIC18F24K20
110= PIC18F43K20
111= PIC18F23K20
bit 4-0
REV<4:0>: Revision ID bits
These bits are used to indicate the device revision.
REGISTER 23-13: DEVID2: DEVICE ID REGISTER 2 FOR PIC18F2XK20/4XK20
R
R
R
R
R
R
R
R
DEV10
DEV9
DEV8
DEV7
DEV6
DEV5
DEV4
DEV3
bit 7
bit 0
Legend:
R = Readable bit
U = Unimplemented bit, read as ‘0’
C = Clearable only bit
-n = Value when device is unprogrammed
bit 7-0 DEV<10:3>: Device ID bits
These bits are used with the DEV<2:0> bits in the Device ID Register 1 to identify the
part number.
0010 0000= PIC18F2XK20/4XK20 devices
Note 1: These values for DEV<10:3> may be shared with other devices. The specific device is always identified
by using the entire DEV<10:0> bit sequence.
© 2007 Microchip Technology Inc.
Advance Information
DS41303B-page 297
PIC18F2XK20/4XK20
23.2 Watchdog Timer (WDT)
For PIC18F2XK20/4XK20 devices, the WDT is driven
by the LFINTOSC source. When the WDT is enabled,
the clock source is also enabled. The nominal WDT
period is 4 ms and has the same stability as the LFIN-
TOSC oscillator.
The 4 ms period of the WDT is multiplied by a 16-bit
postscaler. Any output of the WDT postscaler is
selected by a multiplexer, controlled by bits in Configu-
ration Register 2H. Available periods range from 4 ms
to 131.072 seconds (2.18 minutes). The WDT and
postscaler are cleared when any of the following events
occur: a SLEEPor CLRWDTinstruction is executed, the
IRCF bits of the OSCCON register are changed or a
clock failure has occurred.
Note 1: The CLRWDT and SLEEP instructions
clear the WDT and postscaler counts
when executed.
2: Changing the setting of the IRCF bits of
the OSCCON register clears the WDT
and postscaler counts.
3: When a CLRWDTinstruction is executed,
the postscaler count will be cleared.
FIGURE 23-1:
WDT BLOCK DIAGRAM
Enable WDT
SWDTEN
WDTEN
WDT Counter
Wake-up
from Power
Managed Modes
÷128
LFINTOSC Source
Change on IRCF bits
CLRWDT
WDT
Reset
Reset
Programmable Postscaler
1:1 to 1:32,768
All Device Resets
4
WDTPS<3:0>
Sleep
DS41303B-page 298
Advance Information
© 2007 Microchip Technology Inc.
PIC18F2XK20/4XK20
23.2.1
CONTROL REGISTER
Register 23-14 shows the WDTCON register. This is a
readable and writable register which contains a control
bit that allows software to override the WDT enable
Configuration bit, but only if the Configuration bit has
disabled the WDT.
REGISTER 23-14: WDTCON: WATCHDOG TIMER CONTROL REGISTER
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
R/W-0
SWDTEN(1)
bit 0
bit 7
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7-1
bit 0
Unimplemented: Read as ‘0’
SWDTEN: Software Enable or Disable the Watchdog Timer bit(1)
1= WDT is turned on
0= WDT is turned off (Reset value)
Note 1: This bit has no effect if the Configuration bit, WDTEN, is enabled.
TABLE 23-2: SUMMARY OF WATCHDOG TIMER REGISTERS
Reset
Values
on page
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
RCON
IPEN
—
SBOREN
—
—
—
RI
—
TO
—
PD
—
POR
—
BOR
56
WDTCON
SWDTEN
58
CONFIG2H
WDTPS3 WDTPS2 WDTPS1 WDTPS0 WDTEN
292
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the Watchdog Timer.
© 2007 Microchip Technology Inc.
Advance Information
DS41303B-page 299
PIC18F2XK20/4XK20
Each of the five blocks has three code protection bits
associated with them. They are:
23.3 Program Verification and
Code Protection
• Code-Protect bit (CPn)
The overall structure of the code protection on the
PIC18 Flash devices differs significantly from other
PIC® microcontroller devices.
• Write-Protect bit (WRTn)
• External Block Table Read bit (EBTRn)
Figure 23-2 shows the program memory organization
for 8, 16 and 32-Kbyte devices and the specific code
protection bit associated with each block. The actual
locations of the bits are summarized in Table 23-3.
The user program memory is divided into five blocks.
One of these is a boot block of 0.5K or 2K bytes,
depending on the device. The remainder of the mem-
ory is divided into individual blocks on binary bound-
aries.
FIGURE 23-2:
CODE-PROTECTED PROGRAM MEMORY FOR PIC18F2XK20/4XK20
MEMORY SIZE/DEVICE
Block Code Protection
8 Kbytes
16 Kbytes
32 Kbytes
64 Kbytes
Controlled By:
(PIC18FX3K20)
(PIC18FX4K20)
(PIC18FX5K20)
(PIC18FX6K20)
Boot Block
(000h-1FFh)
Boot Block
(000h-7FFh)
Boot Block
(000h-7FFh)
Boot Block
(000h-7FFh)
CPB, WRTB, EBTRB
CP0, WRT0, EBTR0
CP1, WRT1, EBTR1
CP2, WRT2, EBTR2
CP3, WRT3, EBTR3
Block 0
(200h-FFFh)
Block 0
(800h-1FFFh)
Block 0
(800h-1FFFh)
Block 0
(800h-3FFFh)
Block 1
(1000h-1FFFh)
Block 1
(2000h-3FFFh)
Block 1
(2000h-3FFFh)
Block 1
(4000h-7FFFh)
Block 2
(4000h-5FFFh)
Block 2
(8000h-BFFFh)
Block 3
(6000h-7FFFh)
Block 3
(C000h-FFFFh)
Unimplemented
Unimplemented
Read ‘0’s
Read ‘0’s
(2000h-1FFFFFh) (4000h-1FFFFFh)
Unimplemented
Unimplemented
(Unimplemented
Memory Space)
Read ‘0’s
Read ‘0’s
(8000h-1FFFFFh) (10000h-1FFFFFh)
TABLE 23-3: SUMMARY OF CODE PROTECTION REGISTERS
File Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
300008h CONFIG5L
300009h CONFIG5H
30000Ah CONFIG6L
—
CPD
—
—
CPB
—
—
—
—
—
—
—
—
—
CP3(1)
—
WRT3(1)
CP2(1)
—
WRT2(1)
CP1
—
CP0
—
—
WRT1
—
WRT0
—
30000Bh CONFIG6H WRTD
WRTB
—
WRTC
—
—
—
30000Ch CONFIG7L
30000Dh CONFIG7H
—
—
EBTR3(1) EBTR2(1) EBTR1
EBTR0
—
EBTRB
—
—
—
—
Legend: Shaded cells are unimplemented.
Note 1: Unimplemented in PIC18FX3K20 and PIC18FX4K20 devices; maintain this bit set.
DS41303B-page 300
Advance Information
© 2007 Microchip Technology Inc.
PIC18F2XK20/4XK20
instruction that executes from a location outside of that
block is not allowed to read and will result in reading ‘0’s.
Figures 23-3 through 23-5 illustrate table write and table
read protection.
23.3.1
PROGRAM MEMORY
CODE PROTECTION
The program memory may be read to or written from
any location using the table read and table write
instructions. The device ID may be read with table
reads. The Configuration registers may be read and
written with the table read and table write instructions.
Note:
Code protection bits may only be written to
a ‘0’ from a ‘1’ state. It is not possible to
write a ‘1’ to a bit in the ‘0’ state. Code pro-
tection bits are only set to ‘1’ by a full chip
erase or block erase function. The full chip
erase and block erase functions can only
be initiated via ICSP or an external
programmer.
In normal execution mode, the CPn bits have no direct
effect. CPn bits inhibit external reads and writes. A block
of user memory may be protected from table writes if the
WRTn Configuration bit is ‘0’. The EBTRn bits control
table reads. For a block of user memory with the EBTRn
bit cleared to ‘0’, a table READinstruction that executes
from within that block is allowed to read. A table read
FIGURE 23-3:
TABLE WRITE (WRTn) DISALLOWED
Register Values
Program Memory
Configuration Bit Settings
000000h
0007FFh
WRTB, EBTRB = 11
000800h
TBLPTR = 0008FFh
PC = 001FFEh
WRT0, EBTR0 = 01
TBLWT*
TBLWT*
001FFFh
002000h
WRT1, EBTR1 = 11
WRT2, EBTR2 = 11
WRT3, EBTR3 = 11
003FFFh
004000h
PC = 005FFEh
005FFFh
006000h
007FFFh
Results: All table writes disabled to Blockn whenever WRTn = 0.
© 2007 Microchip Technology Inc.
Advance Information
DS41303B-page 301
PIC18F2XK20/4XK20
FIGURE 23-4:
EXTERNAL BLOCK TABLE READ (EBTRn) DISALLOWED
Register Values
Program Memory
Configuration Bit Settings
000000h
WRTB, EBTRB = 11
0007FFh
000800h
TBLPTR = 0008FFh
PC = 003FFEh
WRT0, EBTR0 = 10
001FFFh
002000h
TBLRD*
WRT1, EBTR1 = 11
WRT2, EBTR2 = 11
003FFFh
004000h
005FFFh
006000h
WRT3, EBTR3 = 11
007FFFh
Results: All table reads from external blocks to Blockn are disabled whenever EBTRn = 0.
TABLAT register returns a value of ‘0’.
FIGURE 23-5:
EXTERNAL BLOCK TABLE READ (EBTRn) ALLOWED
Register Values
Program Memory
Configuration Bit Settings
000000h
WRTB, EBTRB = 11
WRT0, EBTR0 = 10
0007FFh
000800h
TBLPTR = 0008FFh
PC = 001FFEh
TBLRD*
001FFFh
002000h
WRT1, EBTR1 = 11
WRT2, EBTR2 = 11
WRT3, EBTR3 = 11
003FFFh
004000h
005FFFh
006000h
007FFFh
Results: Table reads permitted within Blockn, even when EBTRBn = 0.
TABLAT register returns the value of the data at the location TBLPTR.
DS41303B-page 302
Advance Information
© 2007 Microchip Technology Inc.
PIC18F2XK20/4XK20
To use the In-Circuit Debugger function of the micro-
controller, the design must implement In-Circuit Serial
Programming connections to the following pins:
23.3.2
DATA EEPROM
CODE PROTECTION
The entire data EEPROM is protected from external
reads and writes by two bits: CPD and WRTD. CPD
inhibits external reads and writes of data EEPROM.
WRTD inhibits internal and external writes to data
EEPROM. The CPU can always read data EEPROM
under normal operation, regardless of the protection bit
settings.
• MCLR/VPP/RE3
• VDD
• VSS
• RB7
• RB6
This will interface to the In-Circuit Debugger module
available from Microchip or one of the third party devel-
opment tool companies.
23.3.3
CONFIGURATION REGISTER
PROTECTION
The Configuration registers can be write-protected.
The WRTC bit controls protection of the Configuration
registers. In normal execution mode, the WRTC bit is
readable only. WRTC can only be written via ICSP or
an external programmer.
23.7 Single-Supply ICSP Programming
The LVP Configuration bit enables Single-Supply ICSP
Programming (formerly known as Low-Voltage ICSP
Programming or LVP). When Single-Supply Program-
ming is enabled, the microcontroller can be programmed
without requiring high voltage being applied to the
MCLR/VPP/RE3 pin, but the RB5/KBI1/PGM pin is then
dedicated to controlling Program mode entry and is not
available as a general purpose I/O pin.
23.4 ID Locations
Eight memory locations (200000h-200007h) are
designated as ID locations, where the user can store
checksum or other code identification numbers. These
locations are both readable and writable during normal
execution through the TBLRD and TBLWT instructions
or during program/verify. The ID locations can be read
when the device is code-protected.
While programming, using Single-Supply Programming
mode, VDD is applied to the MCLR/VPP/RE3 pin as in
normal execution mode. To enter Programming mode,
VDD is applied to the PGM pin.
Note 1: High-voltage programming is always
available, regardless of the state of the
LVP bit or the PGM pin, by applying VIHH
to the MCLR pin.
23.5
In-Circuit Serial Programming
PIC18F2XK20/4XK20 devices can be serially
programmed while in the end application circuit. This is
simply done with two lines for clock and data and three
other lines for power, ground and the programming
voltage. This allows customers to manufacture boards
with unprogrammed devices and then program the
microcontroller just before shipping the product. This
also allows the most recent firmware or a custom
firmware to be programmed.
2: By default, Single-Supply ICSP is
enabled in unprogrammed devices (as
supplied from Microchip) and erased
devices.
3: When Single-Supply Programming is
enabled, the RB5 pin can no longer be
used as a general purpose I/O pin.
4: When LVP is enabled, externally pull the
PGM pin to VSS to allow normal program
execution.
23.6 In-Circuit Debugger
When the DEBUG Configuration bit is programmed to
a ‘0’, the In-Circuit Debugger functionality is enabled.
This function allows simple debugging functions when
used with MPLAB® IDE. When the microcontroller has
this feature enabled, some resources are not available
for general use. Table 23-4 shows which resources are
required by the background debugger.
If Single-Supply ICSP Programming mode will not be
used, the LVP bit can be cleared. RB5/KBI1/PGM then
becomes available as the digital I/O pin, RB5. The LVP
bit may be set or cleared only when using standard
high-voltage programming (VIHH applied to the MCLR/
VPP/RE3 pin). Once LVP has been disabled, only the
standard high-voltage programming is available and
must be used to program the device.
TABLE 23-4: DEBUGGER RESOURCES
I/O pins:
RB6, RB7
2 levels
Memory that is not code-protected can be erased using
either a block erase, or erased row by row, then written
at any specified VDD. If code-protected memory is to be
erased, a block erase is required.
Stack:
Program Memory:
Data Memory:
512 bytes
10 bytes
© 2007 Microchip Technology Inc.
Advance Information
DS41303B-page 303
PIC18F2XK20/4XK20
NOTES:
DS41303B-page 304
Advance Information
© 2007 Microchip Technology Inc.
PIC18F2XK20/4XK20
The literal instructions may use some of the following
operands:
24.0 INSTRUCTION SET SUMMARY
PIC18F2XK20/4XK20 devices incorporate the standard
set of 75 PIC18 core instructions, as well as an extended
set of 8 new instructions, for the optimization of code that
is recursive or that utilizes a software stack. The
extended set is discussed later in this section.
• A literal value to be loaded into a file register
(specified by ‘k’)
• The desired FSR register to load the literal value
into (specified by ‘f’)
• No operand required
(specified by ‘—’)
24.1 Standard Instruction Set
The control instructions may use some of the following
operands:
The standard PIC18 instruction set adds many
enhancements to the previous PIC® MCU instruction
sets, while maintaining an easy migration from these
PIC® MCU instruction sets. Most instructions are a sin-
gle program memory word (16 bits), but there are four
instructions that require two program memory loca-
tions.
• A program memory address (specified by ‘n’)
• The mode of the CALLor RETURNinstructions
(specified by ‘s’)
• The mode of the table read and table write
instructions (specified by ‘m’)
Each single-word instruction is a 16-bit word divided
into an opcode, which specifies the instruction type and
one or more operands, which further specify the
operation of the instruction.
• No operand required
(specified by ‘—’)
All instructions are a single word, except for four
double-word instructions. These instructions were
made double-word to contain the required information
in 32 bits. In the second word, the 4 MSbs are ‘1’s. If
this second word is executed as an instruction (by
itself), it will execute as a NOP.
The instruction set is highly orthogonal and is grouped
into four basic categories:
• Byte-oriented operations
• Bit-oriented operations
• Literal operations
All single-word instructions are executed in a single
instruction cycle, unless a conditional test is true or the
program counter is changed as a result of the instruc-
tion. In these cases, the execution takes two instruction
cycles, with the additional instruction cycle(s) executed
as a NOP.
• Control operations
The PIC18 instruction set summary in Table 24-2 lists
byte-oriented, bit-oriented, literal and control
operations. Table 24-1 shows the opcode field
descriptions.
The double-word instructions execute in two instruction
cycles.
Most byte-oriented instructions have three operands:
1. The file register (specified by ‘f’)
One instruction cycle consists of four oscillator periods.
Thus, for an oscillator frequency of 4 MHz, the normal
instruction execution time is 1 μs. If a conditional test is
true, or the program counter is changed as a result of
an instruction, the instruction execution time is 2 μs.
Two-word branch instructions (if true) would take 3 μs.
2. The destination of the result (specified by ‘d’)
3. The accessed memory (specified by ‘a’)
The file register designator ‘f’ specifies which file
register is to be used by the instruction. The destination
designator ‘d’ specifies where the result of the opera-
tion is to be placed. If ‘d’ is zero, the result is placed in
the WREG register. If ‘d’ is one, the result is placed in
the file register specified in the instruction.
Figure 24-1 shows the general formats that the instruc-
tions can have. All examples use the convention ‘nnh’
to represent a hexadecimal number.
The Instruction Set Summary, shown in Table 24-2,
lists the standard instructions recognized by the
Microchip Assembler (MPASMTM).
All bit-oriented instructions have three operands:
1. The file register (specified by ‘f’)
2. The bit in the file register (specified by ‘b’)
3. The accessed memory (specified by ‘a’)
Section 24.1.1 “Standard Instruction Set” provides
a description of each instruction.
The bit field designator ‘b’ selects the number of the bit
affected by the operation, while the file register
designator ‘f’ represents the number of the file in which
the bit is located.
© 2007 Microchip Technology Inc.
Advance Information
DS41303B-page 305
PIC18F2XK20/4XK20
TABLE 24-1: OPCODE FIELD DESCRIPTIONS
Field
Description
a
RAM access bit
a = 0: RAM location in Access RAM (BSR register is ignored)
a = 1: RAM bank is specified by BSR register
bbb
Bit address within an 8-bit file register (0 to 7).
BSR
Bank Select Register. Used to select the current RAM bank.
ALU Status bits: Carry, Digit Carry, Zero, Overflow, Negative.
C, DC, Z, OV, N
d
Destination select bit
d = 0: store result in WREG
d = 1: store result in file register f
dest
f
Destination: either the WREG register or the specified register file location.
8-bit Register file address (00h to FFh) or 2-bit FSR designator (0h to 3h).
12-bit Register file address (000h to FFFh). This is the source address.
12-bit Register file address (000h to FFFh). This is the destination address.
Global Interrupt Enable bit.
f
f
s
d
GIE
k
Literal field, constant data or label (may be either an 8-bit, 12-bit or a 20-bit value).
Label name.
label
mm
The mode of the TBLPTR register for the table read and table write instructions.
Only used with table read and table write instructions:
*
No change to register (such as TBLPTR with table reads and writes)
Post-Increment register (such as TBLPTR with table reads and writes)
Post-Decrement register (such as TBLPTR with table reads and writes)
Pre-Increment register (such as TBLPTR with table reads and writes)
*+
*-
+*
n
The relative address (2’s complement number) for relative branch instructions or the direct address for
CALL/BRANCHand RETURNinstructions.
PC
Program Counter.
PCL
Program Counter Low Byte.
Program Counter High Byte.
Program Counter High Byte Latch.
Program Counter Upper Byte Latch.
Power-down bit.
PCH
PCLATH
PCLATU
PD
PRODH
PRODL
s
Product of Multiply High Byte.
Product of Multiply Low Byte.
Fast Call/Return mode select bit
s = 0: do not update into/from shadow registers
s = 1: certain registers loaded into/from shadow registers (Fast mode)
TBLPTR
TABLAT
TO
21-bit Table Pointer (points to a Program Memory location).
8-bit Table Latch.
Time-out bit.
TOS
u
Top-of-Stack.
Unused or unchanged.
Watchdog Timer.
WDT
WREG
x
Working register (accumulator).
Don’t care (‘0’ or ‘1’). The assembler will generate code with x = 0. It is the recommended form of use for
compatibility with all Microchip software tools.
z
z
{
7-bit offset value for indirect addressing of register files (source).
7-bit offset value for indirect addressing of register files (destination).
Optional argument.
s
d
}
[text]
(text)
[expr]<n>
→
Indicates an indexed address.
The contents of text.
Specifies bit nof the register indicated by the pointer expr.
Assigned to.
< >
Register bit field.
∈
In the set of.
italics
User defined term (font is Courier).
DS41303B-page 306
Advance Information
© 2007 Microchip Technology Inc.
PIC18F2XK20/4XK20
FIGURE 24-1:
GENERAL FORMAT FOR INSTRUCTIONS
Byte-oriented file register operations
15 10
OPCODE f (FILE #)
Example Instruction
9
8
7
0
ADDWF MYREG, W, B
d
a
d = 0for result destination to be WREG register
d = 1for result destination to be file register (f)
a = 0to force Access Bank
a = 1for BSR to select bank
f = 8-bit file register address
Byte to Byte move operations (2-word)
15
12 11
0
0
OPCODE
f (Source FILE #)
MOVFF MYREG1, MYREG2
15
12 11
1111
f (Destination FILE #)
f = 12-bit file register address
Bit-oriented file register operations
15 12 11 9 8
OPCODE b (BIT #)
7
0
BSF MYREG, bit, B
a
f (FILE #)
b = 3-bit position of bit in file register (f)
a = 0to force Access Bank
a = 1for BSR to select bank
f = 8-bit file register address
Literal operations
15
8
7
0
MOVLW 7Fh
OPCODE
k (literal)
k = 8-bit immediate value
Control operations
CALL, GOTO and Branch operations
15
8 7
0
GOTO Label
OPCODE
12 11
n<7:0> (literal)
15
0
1111
n<19:8> (literal)
n = 20-bit immediate value
15
15
8
7
0
CALL MYFUNC
OPCODE
12 11
n<7:0> (literal)
S
0
1111
n<19:8> (literal)
S = Fast bit
15
11 10
0
0
BRA MYFUNC
BC MYFUNC
OPCODE
n<10:0> (literal)
15
OPCODE
8 7
n<7:0> (literal)
© 2007 Microchip Technology Inc.
Advance Information
DS41303B-page 307
PIC18F2XK20/4XK20
TABLE 24-2: PIC18FXXXX INSTRUCTION SET
16-Bit Instruction Word
MSb LSb
Mnemonic,
Operands
Status
Affected
Description
Cycles
Notes
BYTE-ORIENTED OPERATIONS
ADDWF f, d, a Add WREG and f
ADDWFC f, d, a Add WREG and CARRY bit to f
1
1
1
1
1
0010 01da0 ffff
ffff C, DC, Z, OV, N
ffff C, DC, Z, OV, N
ffff Z, N
1, 2
1, 2
1,2
2
1, 2
4
4
1, 2
1, 2, 3, 4
1, 2, 3, 4
1, 2
1, 2, 3, 4
4
1, 2
1, 2
1
0010 0da
0001 01da
0110 101a
0001 11da
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ANDWF
CLRF
COMF
f, d, a AND WREG with f
f, a Clear f
f, d, a Complement f
ffff
Z
ffff Z, N
ffff None
ffff None
ffff None
ffff C, DC, Z, OV, N
ffff None
ffff None
ffff C, DC, Z, OV, N
ffff None
ffff None
ffff Z, N
ffff Z, N
ffff None
ffff
ffff None
ffff None
CPFSEQ
CPFSGT
CPFSLT
DECF
f, a
f, a
f, a
Compare f with WREG, skip =
Compare f with WREG, skip >
Compare f with WREG, skip <
1 (2 or 3) 0110 001a
1 (2 or 3) 0110 010a
1 (2 or 3) 0110 000a
f, d, a Decrement f
1
0000 01da
DECFSZ
DCFSNZ
INCF
f, d, a Decrement f, Skip if 0
f, d, a Decrement f, Skip if Not 0
f, d, a Increment f
1 (2 or 3) 0010 11da
1 (2 or 3) 0100 11da
1
1 (2 or 3) 0011 11da
1 (2 or 3) 0100 10da
1
1
2
0010 10da
INCFSZ
INFSNZ
IORWF
MOVF
f, d, a Increment f, Skip if 0
f, d, a Increment f, Skip if Not 0
f, d, a Inclusive OR WREG with f
f, d, a Move f
0001 00da
0101 00da
1100 ffff
1111 ffff
0110 111a
0000 001a
0110 110a
0011 01da
0100 01da
0011 00da
0100 00da
0110 100a
0101 01da
MOVFF
f , f
Move f (source) to 1st word
s
d
s
f (destination) 2nd word
d
MOVWF
MULWF
NEGF
f, a
f, a
f, a
Move WREG to f
Multiply WREG with f
Negate f
1
1
1
1
1
1
1
1
1
1, 2
1, 2
ffff C, DC, Z, OV, N
ffff C, Z, N
ffff Z, N
ffff C, Z, N
ffff Z, N
RLCF
RLNCF
RRCF
RRNCF
SETF
f, d, a Rotate Left f through Carry
f, d, a Rotate Left f (No Carry)
f, d, a Rotate Right f through Carry
f, d, a Rotate Right f (No Carry)
f, a
Set f
ffff None
ffff C, DC, Z, OV, N
1, 2
1, 2
SUBFWB f, d, a Subtract f from WREG with
borrow
SUBWF
f, d, a Subtract WREG from f
1
1
0101 11da
0101 10da
ffff
ffff
ffff C, DC, Z, OV, N
ffff C, DC, Z, OV, N
SUBWFB f, d, a Subtract WREG from f with
borrow
SWAPF
TSTFSZ
XORWF
f, d, a Swap nibbles in f
f, a Test f, skip if 0
f, d, a Exclusive OR WREG with f
1
0011 10da
ffff
ffff
ffff
ffff None
ffff None
ffff Z, N
4
1, 2
1 (2 or 3) 0110 011a
0001 10da
1
Note 1: When a PORT register is modified as a function of itself (e.g., MOVF PORTB, 1, 0), the value used will be that value
present on the pins themselves. For example, if the data latch is ‘1’ for a pin configured as input and is driven low by an
external device, the data will be written back with a ‘0’.
2: If this instruction is executed on the TMR0 register (and where applicable, ‘d’ = 1), the prescaler will be cleared if
assigned.
3: If Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The second cycle is
executed as a NOP.
4: Some instructions are two-word instructions. The second word of these instructions will be executed as a NOPunless the
first word of the instruction retrieves the information embedded in these 16 bits. This ensures that all program memory
locations have a valid instruction.
DS41303B-page 308
Advance Information
© 2007 Microchip Technology Inc.
PIC18F2XK20/4XK20
TABLE 24-2: PIC18FXXXX INSTRUCTION SET (CONTINUED)
16-Bit Instruction Word
Mnemonic,
Operands
Status
Affected
Description
Cycles
Notes
MSb LSb
BIT-ORIENTED OPERATIONS
BCF
BSF
BTFSC
BTFSS
BTG
f, b, a Bit Clear f
f, b, a Bit Set f
f, b, a Bit Test f, Skip if Clear
f, b, a Bit Test f, Skip if Set
f, d, a Bit Toggle f
1
1
1001 bbba
1000 bbba
ffff
ffff
ffff
ffff
ffff
ffff None
ffff None
ffff None
ffff None
ffff None
1, 2
1, 2
3, 4
3, 4
1, 2
1 (2 or 3) 1011 bbba
1 (2 or 3) 1010 bbba
1
0111 bbba
CONTROL OPERATIONS
BC
BN
n
n
n
n
n
n
n
n
Branch if Carry
1 (2)
1 (2)
1 (2)
1 (2)
1 (2)
1 (2)
1 (2)
2
1110 0010
1110 0110
1110 0011
1110 0111
1110 0101
1110 0001
1110 0100
1101 0nnn
1110 0000
1110 110s
1111 kkkk
0000 0000
0000 0000
1110 1111
1111 kkkk
0000 0000
1111 xxxx
0000 0000
0000 0000
1101 1nnn
0000 0000
0000 0000
nnnn
nnnn
nnnn
nnnn
nnnn
nnnn
nnnn
nnnn
nnnn
kkkk
kkkk
0000
0000
kkkk
kkkk
0000
xxxx
0000
0000
nnnn
1111
0001
nnnn None
nnnn None
nnnn None
nnnn None
nnnn None
nnnn None
nnnn None
nnnn None
nnnn None
kkkk None
kkkk
Branch if Negative
Branch if Not Carry
Branch if Not Negative
Branch if Not Overflow
Branch if Not Zero
Branch if Overflow
Branch Unconditionally
Branch if Zero
Call subroutine 1st word
2nd word
Clear Watchdog Timer
Decimal Adjust WREG
Go to address 1st word
2nd word
BNC
BNN
BNOV
BNZ
BOV
BRA
BZ
n
n, s
1 (2)
2
CALL
CLRWDT
DAW
GOTO
—
—
n
1
1
2
0100 TO, PD
0111
C
kkkk None
kkkk
NOP
NOP
POP
PUSH
RCALL
RESET
RETFIE
—
—
—
—
n
No Operation
No Operation
1
1
1
1
2
1
2
0000 None
xxxx None
0110 None
0101 None
nnnn None
1111 All
4
Pop top of return stack (TOS)
Push top of return stack (TOS)
Relative Call
Software device Reset
Return from interrupt enable
s
000s GIE/GIEH,
PEIE/GIEL
RETLW
RETURN
SLEEP
k
s
—
Return with literal in WREG
Return from Subroutine
Go into Standby mode
2
2
1
0000 1100
0000 0000
0000 0000
kkkk
0001
0000
kkkk None
001s None
0011 TO, PD
Note 1: When a PORT register is modified as a function of itself (e.g., MOVF PORTB, 1, 0), the value used will be that value
present on the pins themselves. For example, if the data latch is ‘1’ for a pin configured as input and is driven low by an
external device, the data will be written back with a ‘0’.
2: If this instruction is executed on the TMR0 register (and where applicable, ‘d’ = 1), the prescaler will be cleared if
assigned.
3: If Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The second cycle is
executed as a NOP.
4: Some instructions are two-word instructions. The second word of these instructions will be executed as a NOPunless the
first word of the instruction retrieves the information embedded in these 16 bits. This ensures that all program memory
locations have a valid instruction.
© 2007 Microchip Technology Inc.
Advance Information
DS41303B-page 309
PIC18F2XK20/4XK20
TABLE 24-2: PIC18FXXXX INSTRUCTION SET (CONTINUED)
16-Bit Instruction Word
Mnemonic,
Operands
Status
Affected
Description
Cycles
Notes
MSb
LSb
LITERAL OPERATIONS
ADDLW
ANDLW
IORLW
LFSR
k
k
k
f, k
Add literal and WREG
AND literal with WREG
Inclusive OR literal with WREG
Move literal (12-bit) 2nd word
1
1
1
2
0000 1111 kkkk
0000 1011 kkkk
0000 1001 kkkk
1110 1110 00ff
1111 0000 kkkk
0000 0001 0000
0000 1110 kkkk
0000 1101 kkkk
0000 1100 kkkk
0000 1000 kkkk
0000 1010 kkkk
kkkk C, DC, Z, OV, N
kkkk Z, N
kkkk Z, N
kkkk None
kkkk
kkkk None
kkkk None
kkkk None
kkkk None
kkkk C, DC, Z, OV, N
kkkk Z, N
to FSR(f)
1st word
MOVLB
MOVLW
MULLW
RETLW
SUBLW
XORLW
k
k
k
k
k
k
Move literal to BSR<3:0>
Move literal to WREG
Multiply literal with WREG
Return with literal in WREG
Subtract WREG from literal
Exclusive OR literal with WREG
1
1
1
2
1
1
DATA MEMORY ↔ PROGRAM MEMORY OPERATIONS
TBLRD*
Table Read
2
0000 0000 0000
0000 0000 0000
0000 0000 0000
0000 0000 0000
0000 0000 0000
0000 0000 0000
0000 0000 0000
0000 0000 0000
1000 None
1001 None
1010 None
1011 None
1100 None
1101 None
1110 None
1111 None
TBLRD*+
TBLRD*-
TBLRD+*
TBLWT*
TBLWT*+
TBLWT*-
TBLWT+*
Table Read with post-increment
Table Read with post-decrement
Table Read with pre-increment
Table Write
Table Write with post-increment
Table Write with post-decrement
Table Write with pre-increment
2
Note 1: When a PORT register is modified as a function of itself (e.g., MOVF PORTB, 1, 0), the value used will be that value
present on the pins themselves. For example, if the data latch is ‘1’ for a pin configured as input and is driven low by an
external device, the data will be written back with a ‘0’.
2: If this instruction is executed on the TMR0 register (and where applicable, ‘d’ = 1), the prescaler will be cleared if
assigned.
3: If Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The second cycle is
executed as a NOP.
4: Some instructions are two-word instructions. The second word of these instructions will be executed as a NOPunless the
first word of the instruction retrieves the information embedded in these 16 bits. This ensures that all program memory
locations have a valid instruction.
DS41303B-page 310
Advance Information
© 2007 Microchip Technology Inc.
PIC18F2XK20/4XK20
24.1.1
STANDARD INSTRUCTION SET
ADDLW
ADD literal to W
ADDWF
ADD W to f
Syntax:
ADDLW
k
Syntax:
ADDWF
f {,d {,a}}
Operands:
Operation:
Status Affected:
Encoding:
Description:
0 ≤ k ≤ 255
Operands:
0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
(W) + k → W
N, OV, C, DC, Z
Operation:
(W) + (f) → dest
0000
1111
kkkk
kkkk
Status Affected:
Encoding:
N, OV, C, DC, Z
The contents of W are added to the
8-bit literal ‘k’ and the result is placed in
W.
0010
01da
ffff
ffff
Description:
Add W to register ‘f’. If ‘d’ is ‘0’, the
result is stored in W. If ‘d’ is ‘1’, the
result is stored back in register ‘f’
(default).
Words:
Cycles:
1
1
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank (default).
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f ≤ 95 (5Fh). See
Section 24.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
literal ‘k’
Process
Data
Write to W
Example:
ADDLW
15h
Before Instruction
10h
After Instruction
25h
W
=
Words:
Cycles:
1
1
W
=
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
register ‘f’
Process
Data
Write to
destination
Example:
ADDWF
REG, 0, 0
Before Instruction
W
=
17h
REG
=
0C2h
After Instruction
W
REG
=
=
0D9h
0C2h
Note:
All PIC18 instructions may take an optional label argument preceding the instruction mnemonic for use in
symbolic addressing. If a label is used, the instruction format then becomes: {label} instruction argument(s).
© 2007 Microchip Technology Inc.
Advance Information
DS41303B-page 311
PIC18F2XK20/4XK20
ADDWFC
ADD W and CARRY bit to f
ANDLW
AND literal with W
Syntax:
ADDWFC
f {,d {,a}}
Syntax:
ANDLW
k
Operands:
0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
Operands:
Operation:
Status Affected:
Encoding:
Description:
0 ≤ k ≤ 255
(W) .AND. k → W
N, Z
Operation:
(W) + (f) + (C) → dest
0000
1011
kkkk
kkkk
Status Affected:
Encoding:
N,OV, C, DC, Z
The contents of W are AND’ed with the
8-bit literal ‘k’. The result is placed in W.
0010
00da
ffff
ffff
Description:
Add W, the CARRY flag and data mem-
ory location ‘f’. If ‘d’ is ‘0’, the result is
placed in W. If ‘d’ is ‘1’, the result is
placed in data memory location ‘f’.
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank (default).
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f ≤ 95 (5Fh). See
Section 24.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
Words:
1
1
Cycles:
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read literal
‘k’
Process
Data
Write to W
Example:
ANDLW
05Fh
Before Instruction
W
=
A3h
03h
After Instruction
W
=
Words:
Cycles:
1
1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
register ‘f’
Process
Data
Write to
destination
Example:
ADDWFC
REG, 0, 1
Before Instruction
CARRY bit =
1
02h
4Dh
REG
W
=
=
After Instruction
CARRY bit =
0
02h
50h
REG
W
=
=
DS41303B-page 312
Advance Information
© 2007 Microchip Technology Inc.
PIC18F2XK20/4XK20
ANDWF
AND W with f
BC
Branch if Carry
Syntax:
ANDWF
f {,d {,a}}
Syntax:
BC
n
Operands:
0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
Operands:
Operation:
-128 ≤ n ≤ 127
if CARRY bit is ‘1’
(PC) + 2 + 2n → PC
Operation:
(W) .AND. (f) → dest
Status Affected:
Encoding:
None
Status Affected:
Encoding:
N, Z
1110
0010
nnnn
nnnn
0001
01da
ffff
ffff
Description:
If the CARRY bit is ‘1’, then the program
will branch.
Description:
The contents of W are AND’ed with
register ‘f’. If ‘d’ is ‘0’, the result is stored
in W. If ‘d’ is ‘1’, the result is stored back
in register ‘f’ (default).
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank (default).
The 2’s complement number ‘2n’ is
added to the PC. Since the PC will have
incremented to fetch the next
instruction, the new address will be
PC + 2 + 2n. This instruction is then a
two-cycle instruction.
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f ≤ 95 (5Fh). See
Section 24.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
Words:
Cycles:
1
1(2)
Q Cycle Activity:
If Jump:
Q1
Q2
Q3
Q4
Decode
Read literal
‘n’
Process
Data
Write to PC
Words:
1
1
Cycles:
No
No
No
No
operation
operation
operation
operation
Q Cycle Activity:
Q1
If No Jump:
Q1
Q2
Q3
Q4
Q2
Q3
Q4
Decode
Read
register ‘f’
Process
Data
Write to
destination
Decode
Read literal
‘n’
Process
Data
No
operation
Example:
ANDWF
REG, 0, 0
Example:
HERE
BC
5
Before Instruction
Before Instruction
W
REG
=
=
17h
C2h
PC
=
address (HERE)
After Instruction
After Instruction
If CARRY
PC
If CARRY
PC
=
=
=
=
1;
address (HERE + 12)
0;
address (HERE + 2)
W
REG
=
=
02h
C2h
© 2007 Microchip Technology Inc.
Advance Information
DS41303B-page 313
PIC18F2XK20/4XK20
BCF
Bit Clear f
BN
Branch if Negative
Syntax:
BCF f, b {,a}
Syntax:
BN
n
Operands:
0 ≤ f ≤ 255
0 ≤ b ≤ 7
a ∈ [0,1]
Operands:
Operation:
-128 ≤ n ≤ 127
if NEGATIVE bit is ‘1’
(PC) + 2 + 2n → PC
Operation:
0 → f<b>
Status Affected:
Encoding:
None
Status Affected:
Encoding:
None
1110
0110
nnnn
nnnn
1001
bbba
ffff
ffff
Description:
If the NEGATIVE bit is ‘1’, then the
program will branch.
Description:
Bit ‘b’ in register ‘f’ is cleared.
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank (default).
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f ≤ 95 (5Fh). See
Section 24.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
The 2’s complement number ‘2n’ is
added to the PC. Since the PC will have
incremented to fetch the next
instruction, the new address will be
PC + 2 + 2n. This instruction is then a
two-cycle instruction.
Words:
Cycles:
1
1(2)
Q Cycle Activity:
If Jump:
Words:
Cycles:
1
1
Q1
Q2
Q3
Q4
Decode
Read literal
‘n’
Process
Data
Write to PC
Q Cycle Activity:
Q1
Q2
Q3
Q4
No
No
No
No
Decode
Read
register ‘f’
Process
Data
Write
register ‘f’
operation
operation
operation
operation
If No Jump:
Q1
Q2
Q3
Q4
Example:
BCF
FLAG_REG, 7, 0
C7h
47h
Decode
Read literal
‘n’
Process
Data
No
operation
Before Instruction
FLAG_REG =
After Instruction
FLAG_REG =
Example:
HERE
BN Jump
Before Instruction
PC
=
address (HERE)
After Instruction
If NEGATIVE
PC
If NEGATIVE
PC
=
=
=
=
1;
address (Jump)
0;
address (HERE + 2)
DS41303B-page 314
Advance Information
© 2007 Microchip Technology Inc.
PIC18F2XK20/4XK20
BNC
Branch if Not Carry
BNN
Branch if Not Negative
Syntax:
BNC
n
Syntax:
BNN
n
Operands:
Operation:
-128 ≤ n ≤ 127
Operands:
Operation:
-128 ≤ n ≤ 127
if CARRY bit is ‘0’
(PC) + 2 + 2n → PC
if NEGATIVE bit is ‘0’
(PC) + 2 + 2n → PC
Status Affected:
Encoding:
None
Status Affected:
Encoding:
None
1110
0011
nnnn
nnnn
1110
0111
nnnn
nnnn
Description:
If the CARRY bit is ‘0’, then the program
will branch.
Description:
If the NEGATIVE bit is ‘0’, then the
program will branch.
The 2’s complement number ‘2n’ is
added to the PC. Since the PC will have
incremented to fetch the next
instruction, the new address will be
PC + 2 + 2n. This instruction is then a
two-cycle instruction.
The 2’s complement number ‘2n’ is
added to the PC. Since the PC will have
incremented to fetch the next
instruction, the new address will be
PC + 2 + 2n. This instruction is then a
two-cycle instruction.
Words:
Cycles:
1
Words:
Cycles:
1
1(2)
1(2)
Q Cycle Activity:
If Jump:
Q Cycle Activity:
If Jump:
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Decode
Read literal
‘n’
Process
Data
Write to PC
Decode
Read literal
‘n’
Process
Data
Write to PC
No
No
No
No
No
No
No
No
operation
operation
operation
operation
operation
operation
operation
operation
If No Jump:
Q1
If No Jump:
Q1
Q2
Q3
Q4
Q2
Q3
Q4
Decode
Read literal
‘n’
Process
Data
No
operation
Decode
Read literal
‘n’
Process
Data
No
operation
Example:
HERE
BNC Jump
Example:
HERE
BNN Jump
Before Instruction
Before Instruction
PC
=
address (HERE)
PC
=
address (HERE)
After Instruction
After Instruction
If CARRY
PC
If CARRY
PC
=
=
=
=
0;
If NEGATIVE
PC
If NEGATIVE
PC
=
=
=
=
0;
address (Jump)
address (Jump)
1;
1;
address (HERE + 2)
address (HERE + 2)
© 2007 Microchip Technology Inc.
Advance Information
DS41303B-page 315
PIC18F2XK20/4XK20
BNOV
Branch if Not Overflow
BNZ
Branch if Not Zero
Syntax:
BNOV
n
Syntax:
BNZ
n
Operands:
Operation:
-128 ≤ n ≤ 127
Operands:
Operation:
-128 ≤ n ≤ 127
if OVERFLOW bit is ‘0’
(PC) + 2 + 2n → PC
if ZERO bit is ‘0’
(PC) + 2 + 2n → PC
Status Affected:
Encoding:
None
Status Affected:
Encoding:
None
1110
0101
nnnn
nnnn
1110
0001
nnnn
nnnn
Description:
If the OVERFLOW bit is ‘0’, then the
program will branch.
Description:
If the ZERO bit is ‘0’, then the program
will branch.
The 2’s complement number ‘2n’ is
added to the PC. Since the PC will have
incremented to fetch the next
instruction, the new address will be
PC + 2 + 2n. This instruction is then a
two-cycle instruction.
The 2’s complement number ‘2n’ is
added to the PC. Since the PC will have
incremented to fetch the next
instruction, the new address will be
PC + 2 + 2n. This instruction is then a
two-cycle instruction.
Words:
Cycles:
1
Words:
Cycles:
1
1(2)
1(2)
Q Cycle Activity:
If Jump:
Q Cycle Activity:
If Jump:
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Decode
Read literal
‘n’
Process
Data
Write to PC
Decode
Read literal
‘n’
Process
Data
Write to PC
No
No
No
No
No
No
No
No
operation
operation
operation
operation
operation
operation
operation
operation
If No Jump:
Q1
If No Jump:
Q1
Q2
Q3
Q4
Q2
Q3
Q4
Decode
Read literal
‘n’
Process
Data
No
operation
Decode
Read literal
‘n’
Process
Data
No
operation
Example:
HERE
BNOV Jump
Example:
HERE
BNZ Jump
Before Instruction
Before Instruction
PC
=
address (HERE)
PC
=
address (HERE)
After Instruction
After Instruction
If OVERFLOW =
PC
0;
If ZERO
PC
If ZERO
PC
=
=
=
=
0;
=
address (Jump)
address (Jump)
If OVERFLOW =
1;
1;
PC
=
address (HERE + 2)
address (HERE + 2)
DS41303B-page 316
Advance Information
© 2007 Microchip Technology Inc.
PIC18F2XK20/4XK20
BRA
Unconditional Branch
BSF
Bit Set f
Syntax:
BRA
n
Syntax:
BSF f, b {,a}
Operands:
Operation:
-1024 ≤ n ≤ 1023
Operands:
0 ≤ f ≤ 255
0 ≤ b ≤ 7
a ∈ [0,1]
(PC) + 2 + 2n → PC
Status Affected: None
Operation:
1 → f<b>
Encoding:
1101
0nnn
nnnn
nnnn
Status Affected:
Encoding:
None
Description:
Add the 2’s complement number ‘2n’ to
the PC. Since the PC will have incre-
mented to fetch the next instruction, the
new address will be PC + 2 + 2n. This
instruction is a two-cycle instruction.
1000
bbba
ffff
ffff
Description:
Bit ‘b’ in register ‘f’ is set.
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank (default).
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f ≤ 95 (5Fh). See
Section 24.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
Words:
Cycles:
1
2
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read literal
‘n’
Process
Data
Write to PC
No
operation
No
operation
No
operation
No
operation
Words:
Cycles:
1
1
Q Cycle Activity:
Q1
Example:
HERE
BRA Jump
Q2
Q3
Q4
Before Instruction
Decode
Read
register ‘f’
Process
Data
Write
register ‘f’
PC
=
=
address (HERE)
address (Jump)
After Instruction
PC
Example:
BSF
FLAG_REG, 7, 1
0Ah
8Ah
Before Instruction
FLAG_REG
After Instruction
FLAG_REG
=
=
© 2007 Microchip Technology Inc.
Advance Information
DS41303B-page 317
PIC18F2XK20/4XK20
BTFSC
Bit Test File, Skip if Clear
BTFSS
Bit Test File, Skip if Set
Syntax:
BTFSC f, b {,a}
Syntax:
BTFSS f, b {,a}
Operands:
0 ≤ f ≤ 255
0 ≤ b ≤ 7
a ∈ [0,1]
Operands:
0 ≤ f ≤ 255
0 ≤ b < 7
a ∈ [0,1]
Operation:
skip if (f<b>) = 0
Operation:
skip if (f<b>) = 1
Status Affected:
Encoding:
None
Status Affected:
Encoding:
None
1011
bbba
ffff
ffff
1010
bbba
ffff
ffff
Description:
If bit ‘b’ in register ‘f’ is ‘0’, then the next
instruction is skipped. If bit ‘b’ is ‘0’, then
the next instruction fetched during the
current instruction execution is discarded
and a NOPis executed instead, making
this a two-cycle instruction.
Description:
If bit ‘b’ in register ‘f’ is ‘1’, then the next
instruction is skipped. If bit ‘b’ is ‘1’, then
the next instruction fetched during the
current instruction execution is discarded
and a NOPis executed instead, making
this a two-cycle instruction.
If ‘a’ is ‘0’, the Access Bank is selected. If
‘a’ is ‘1’, the BSR is used to select the
GPR bank (default).
If ‘a’ is ‘0’, the Access Bank is selected. If
‘a’ is ‘1’, the BSR is used to select the
GPR bank (default).
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates in
Indexed Literal Offset Addressing
mode whenever f ≤ 95 (5Fh).
See Section 24.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f ≤ 95 (5Fh).
See Section 24.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
Words:
Cycles:
1
Words:
Cycles:
1
1(2)
1(2)
Note: 3 cycles if skip and followed
by a 2-word instruction.
Note: 3 cycles if skip and followed
by a 2-word instruction.
Q Cycle Activity:
Q1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Q2
Q3
Q4
Decode
Read
register ‘f’
Process
Data
No
operation
Decode
Read
register ‘f’
Process
Data
No
operation
If skip:
Q1
If skip:
Q1
Q2
Q3
Q4
Q2
Q3
Q4
No
No
No
No
No
No
No
No
operation
operation
operation
operation
operation
operation
operation
operation
If skip and followed by 2-word instruction:
If skip and followed by 2-word instruction:
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
No
No
No
No
No
No
No
No
operation
operation
operation
operation
operation
operation
operation
operation
No
No
No
No
No
No
No
No
operation
operation
operation
operation
operation
operation
operation
operation
Example:
HERE
FALSE
TRUE
BTFSC
:
:
FLAG, 1, 0
Example:
HERE
FALSE
TRUE
BTFSS
:
:
FLAG, 1, 0
Before Instruction
PC
Before Instruction
PC
=
address (HERE)
=
address (HERE)
After Instruction
After Instruction
If FLAG<1>
PC
If FLAG<1>
PC
=
=
=
=
0;
If FLAG<1>
PC
If FLAG<1>
PC
=
=
=
=
0;
address (TRUE)
1;
address (FALSE)
1;
address (FALSE)
address (TRUE)
DS41303B-page 318
Advance Information
© 2007 Microchip Technology Inc.
PIC18F2XK20/4XK20
BTG
Bit Toggle f
BOV
Branch if Overflow
Syntax:
BTG f, b {,a}
Syntax:
BOV
n
Operands:
0 ≤ f ≤ 255
0 ≤ b < 7
a ∈ [0,1]
Operands:
Operation:
-128 ≤ n ≤ 127
if OVERFLOW bit is ‘1’
(PC) + 2 + 2n → PC
Operation:
(f<b>) → f<b>
Status Affected:
Encoding:
None
Status Affected:
Encoding:
None
1110
0100
nnnn
nnnn
0111
bbba
ffff
ffff
Description:
If the OVERFLOW bit is ‘1’, then the
program will branch.
Description:
Bit ‘b’ in data memory location ‘f’ is
inverted.
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank (default).
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f ≤ 95 (5Fh). See
Section 24.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
The 2’s complement number ‘2n’ is
added to the PC. Since the PC will have
incremented to fetch the next
instruction, the new address will be
PC + 2 + 2n. This instruction is then a
two-cycle instruction.
Words:
Cycles:
1
1(2)
Q Cycle Activity:
If Jump:
Words:
Cycles:
1
1
Q1
Q2
Q3
Q4
Decode
Read literal
‘n’
Process
Data
Write to PC
Q Cycle Activity:
Q1
No
operation
No
operation
No
operation
No
operation
Q2
Q3
Q4
Decode
Read
register ‘f’
Process
Data
Write
register ‘f’
If No Jump:
Q1
Q2
Q3
Q4
Decode
Read literal
‘n’
Process
Data
No
operation
Example:
BTG
PORTC, 4, 0
Before Instruction:
PORTC
After Instruction:
PORTC
=
0111 0101 [75h]
0110 0101 [65h]
Example:
HERE
BOV Jump
Before Instruction
=
PC
=
address (HERE)
After Instruction
If OVERFLOW =
PC
If OVERFLOW =
PC
1;
=
address (Jump)
0;
=
address (HERE + 2)
© 2007 Microchip Technology Inc.
Advance Information
DS41303B-page 319
PIC18F2XK20/4XK20
BZ
Branch if Zero
CALL
Subroutine Call
Syntax:
BZ
n
Syntax:
CALL k {,s}
Operands:
Operation:
-128 ≤ n ≤ 127
Operands:
0 ≤ k ≤ 1048575
s ∈ [0,1]
if ZERO bit is ‘1’
(PC) + 2 + 2n → PC
Operation:
(PC) + 4 → TOS,
k → PC<20:1>,
if s = 1
Status Affected:
Encoding:
None
1110
0000
nnnn
nnnn
(W) → WS,
(Status) → STATUSS,
(BSR) → BSRS
Description:
If the ZERO bit is ‘1’, then the program
will branch.
The 2’s complement number ‘2n’ is
added to the PC. Since the PC will
have incremented to fetch the next
instruction, the new address will be
PC + 2 + 2n. This instruction is then a
two-cycle instruction.
Status Affected:
None
Encoding:
1st word (k<7:0>)
2nd word(k<19:8>)
1110
1111
110s
k kkk
kkkk
kkkk
7
0
8
k
kkk kkkk
19
Description:
Subroutine call of entire 2-Mbyte
memory range. First, return address
(PC + 4) is pushed onto the return
stack. If ‘s’ = 1, the W, Status and BSR
registers are also pushed into their
respective shadow registers, WS,
STATUSS and BSRS. If ‘s’ = 0, no
update occurs (default). Then, the
20-bit value ‘k’ is loaded into PC<20:1>.
CALLis a two-cycle instruction.
Words:
Cycles:
1
1(2)
Q Cycle Activity:
If Jump:
Q1
Q2
Q3
Q4
Decode
Read literal
‘n’
Process
Data
Write to PC
No
operation
No
No
No
Words:
Cycles:
2
2
operation
operation
operation
If No Jump:
Q1
Q2
Q3
Q4
Q Cycle Activity:
Q1
Decode
Read literal
‘n’
Process
Data
No
operation
Q2
Q3
Q4
Decode
Read literal PUSH PC to Read literal
‘k’<7:0>,
stack
‘k’<19:8>,
Write to PC
Example:
HERE
BZ Jump
No
operation
No
operation
No
operation
No
operation
Before Instruction
PC
=
address (HERE)
After Instruction
If ZERO
PC
If ZERO
PC
=
=
=
=
1;
Example:
HERE
CALL THERE, 1
address (Jump)
Before Instruction
PC
After Instruction
0;
address (HERE + 2)
=
address (HERE)
PC
=
address (THERE)
TOS
WS
=
=
=
address (HERE + 4)
W
BSR
Status
BSRS
STATUSS=
DS41303B-page 320
Advance Information
© 2007 Microchip Technology Inc.
PIC18F2XK20/4XK20
CLRF
Clear f
CLRWDT
Clear Watchdog Timer
Syntax:
CLRF f {,a}
Syntax:
CLRWDT
None
Operands:
0 ≤ f ≤ 255
a ∈ [0,1]
Operands:
Operation:
000h → WDT,
000h → WDT postscaler,
1 → TO,
Operation:
000h → f
1 → Z
1 → PD
Status Affected:
Encoding:
Z
Status Affected:
Encoding:
TO, PD
0110
101a
ffff
ffff
0000
0000
0000
0100
Description:
Clears the contents of the specified
register.
Description:
CLRWDTinstruction resets the
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank (default).
Watchdog Timer. It also resets the
postscaler of the WDT. Status bits, TO
and PD, are set.
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f ≤ 95 (5Fh). See
Section 24.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
Words:
Cycles:
1
1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
No
Process
Data
No
operation
operation
Words:
Cycles:
1
1
Example:
CLRWDT
Q Cycle Activity:
Q1
Before Instruction
Q2
Q3
Q4
WDT Counter
After Instruction
WDT Counter
WDT Postscaler
TO
=
?
Decode
Read
register ‘f’
Process
Data
Write
register ‘f’
=
=
=
=
00h
0
1
Example:
CLRF
FLAG_REG, 1
PD
1
Before Instruction
FLAG_REG
After Instruction
FLAG_REG
=
=
5Ah
00h
© 2007 Microchip Technology Inc.
Advance Information
DS41303B-page 321
PIC18F2XK20/4XK20
CPFSEQ
Compare f with W, skip if f = W
COMF
Complement f
Syntax:
CPFSEQ f {,a}
Syntax:
COMF f {,d {,a}}
Operands:
0 ≤ f ≤ 255
a ∈ [0,1]
Operands:
0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
Operation:
(f) – (W),
skip if (f) = (W)
(unsigned comparison)
Operation:
(f) → dest
Status Affected:
Encoding:
N, Z
Status Affected:
Encoding:
None
0001
11da
ffff
ffff
0110
001a
ffff
ffff
Description:
The contents of register ‘f’ are
Description:
Compares the contents of data memory
location ‘f’ to the contents of W by
performing an unsigned subtraction.
If ‘f’ = W, then the fetched instruction is
discarded and a NOPis executed
instead, making this a two-cycle
instruction.
complemented. If ‘d’ is ‘0’, the result is
stored in W. If ‘d’ is ‘1’, the result is
stored back in register ‘f’ (default).
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank (default).
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f ≤ 95 (5Fh). See
Section 24.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank (default).
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f ≤ 95 (5Fh). See
Section 24.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
Words:
Cycles:
1
1
Q Cycle Activity:
Q1
Words:
Cycles:
1
Q2
Q3
Q4
1(2)
Decode
Read
register ‘f’
Process
Data
Write to
destination
Note: 3 cycles if skip and followed
by a 2-word instruction.
Q Cycle Activity:
Q1
Example:
COMF
REG, 0, 0
Q2
Q3
Q4
Before Instruction
Decode
Read
register ‘f’
Process
Data
No
operation
REG
=
13h
After Instruction
If skip:
REG
W
=
=
13h
ECh
Q1
No
Q2
No
Q3
No
Q4
No
operation
operation
operation
operation
If skip and followed by 2-word instruction:
Q1
No
Q2
No
Q3
No
Q4
No
operation
No
operation
No
operation
No
operation
No
operation
operation
operation
operation
Example:
HERE
CPFSEQ REG, 0
NEQUAL
EQUAL
:
:
Before Instruction
PC Address
=
HERE
W
REG
=
=
?
?
After Instruction
If REG
PC
=
=
W;
Address (EQUAL)
If REG
PC
≠
=
W;
Address (NEQUAL)
DS41303B-page 322
Advance Information
© 2007 Microchip Technology Inc.
PIC18F2XK20/4XK20
CPFSGT
Compare f with W, skip if f > W
CPFSLT
Compare f with W, skip if f < W
Syntax:
CPFSGT f {,a}
Syntax:
CPFSLT f {,a}
Operands:
0 ≤ f ≤ 255
a ∈ [0,1]
Operands:
0 ≤ f ≤ 255
a ∈ [0,1]
Operation:
(f) – (W),
skip if (f) > (W)
(unsigned comparison)
Operation:
(f) – (W),
skip if (f) < (W)
(unsigned comparison)
Status Affected:
Encoding:
None
Status Affected:
Encoding:
None
0110
010a
ffff
ffff
0110
000a
ffff
ffff
Description:
Compares the contents of data memory
location ‘f’ to the contents of the W by
performing an unsigned subtraction.
If the contents of ‘f’ are greater than the
contents of WREG, then the fetched
instruction is discarded and a NOPis
executed instead, making this a
Description:
Compares the contents of data memory
location ‘f’ to the contents of W by
performing an unsigned subtraction.
If the contents of ‘f’ are less than the
contents of W, then the fetched
instruction is discarded and a NOPis
executed instead, making this a
two-cycle instruction.
two-cycle instruction.
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank (default).
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f ≤ 95 (5Fh). See
Section 24.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank (default).
Words:
Cycles:
1
1(2)
Note: 3 cycles if skip and followed
by a 2-word instruction.
Q Cycle Activity:
Q1
Q2
Q3
Q4
Words:
Cycles:
1
Decode
Read
register ‘f’
Process
Data
No
operation
1(2)
Note: 3 cycles if skip and followed
by a 2-word instruction.
If skip:
Q1
Q2
Q3
Q4
Q Cycle Activity:
Q1
No
operation
No
operation
No
operation
No
operation
Q2
Q3
Q4
No
operation
Decode
Read
register ‘f’
Process
Data
If skip and followed by 2-word instruction:
If skip:
Q1
Q2
Q3
Q4
Q1
No
Q2
No
Q3
No
Q4
No
No
operation
No
operation
No
operation
No
operation
operation
operation
operation
operation
No
No
No
No
If skip and followed by 2-word instruction:
operation
operation
operation
operation
Q1
No
operation
No
Q2
No
operation
No
Q3
No
operation
No
Q4
No
operation
No
Example:
HERE
NLESS
LESS
CPFSLT REG, 1
:
:
operation
operation
operation
operation
Before Instruction
PC
W
=
=
Address (HERE)
Example:
HERE
NGREATER
GREATER
CPFSGT REG, 0
:
:
?
After Instruction
If REG
PC
If REG
PC
<
=
≥
=
W;
Before Instruction
Address (LESS)
W;
Address (NLESS)
PC
W
=
=
Address (HERE)
?
After Instruction
If REG
PC
>
=
W;
Address (GREATER)
If REG
PC
≤
=
W;
Address (NGREATER)
© 2007 Microchip Technology Inc.
Advance Information
DS41303B-page 323
PIC18F2XK20/4XK20
DAW
Decimal Adjust W Register
DECF
Decrement f
Syntax:
DAW
None
Syntax:
DECF f {,d {,a}}
Operands:
Operation:
Operands:
0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
If [W<3:0> > 9] or [DC = 1] then
(W<3:0>) + 6 → W<3:0>;
else
Operation:
(f) – 1 → dest
(W<3:0>) → W<3:0>;
Status Affected:
Encoding:
C, DC, N, OV, Z
0000
01da
ffff
ffff
If [W<7:4> + DC > 9] or [C = 1] then
(W<7:4>) + 6 + DC → W<7:4> ;
else
Description:
Decrement register ‘f’. If ‘d’ is ‘0’, the
result is stored in W. If ‘d’ is ‘1’, the
result is stored back in register ‘f’
(default).
(W<7:4>) + DC → W<7:4>
Status Affected:
Encoding:
C
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank (default).
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f ≤ 95 (5Fh). See
Section 24.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
0000
0000
0000
0111
Description:
DAW adjusts the eight-bit value in W,
resulting from the earlier addition of two
variables (each in packed BCD format)
and produces a correct packed BCD
result.
Words:
Cycles:
1
1
Q Cycle Activity:
Q1
Words:
Cycles:
1
1
Q2
Q3
Q4
Decode
Read
register W
Process
Data
Write
W
Q Cycle Activity:
Q1
Q2
Q3
Q4
Example1:
Decode
Read
register ‘f’
Process
Data
Write to
destination
DAW
Before Instruction
W
C
DC
=
=
=
A5h
0
0
Example:
DECF
CNT,
1, 0
Before Instruction
After Instruction
CNT
Z
After Instruction
=
01h
0
=
W
=
05h
1
0
C
DC
=
=
CNT
Z
=
=
00h
1
Example 2:
Before Instruction
W
=
CEh
C
DC
=
=
0
0
After Instruction
W
=
34h
C
DC
=
=
1
0
DS41303B-page 324
Advance Information
© 2007 Microchip Technology Inc.
PIC18F2XK20/4XK20
DECFSZ
Decrement f, skip if 0
DCFSNZ
Decrement f, skip if not 0
Syntax:
DECFSZ f {,d {,a}}
Syntax:
DCFSNZ f {,d {,a}}
Operands:
0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
Operands:
0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
Operation:
(f) – 1 → dest,
Operation:
(f) – 1 → dest,
skip if result = 0
skip if result ≠ 0
Status Affected:
Encoding:
None
Status Affected:
Encoding:
None
0010
11da
ffff
ffff
0100
11da
ffff
ffff
Description:
The contents of register ‘f’ are
Description:
The contents of register ‘f’ are
decremented. If ‘d’ is ‘0’, the result is
placed in W. If ‘d’ is ‘1’, the result is
placed back in register ‘f’ (default).
If the result is ‘0’, the next instruction,
which is already fetched, is discarded
and a NOPis executed instead, making
it a two-cycle instruction.
decremented. If ‘d’ is ‘0’, the result is
placed in W. If ‘d’ is ‘1’, the result is
placed back in register ‘f’ (default).
If the result is not ‘0’, the next
instruction, which is already fetched, is
discarded and a NOPis executed
instead, making it a two-cycle
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank (default).
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f ≤ 95 (5Fh). See
Section 24.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
instruction.
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank (default).
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f ≤ 95 (5Fh). See
Section 24.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
Words:
Cycles:
1
Words:
Cycles:
1
1(2)
Note: 3 cycles if skip and followed
by a 2-word instruction.
1(2)
Note: 3 cycles if skip and followed
by a 2-word instruction.
Q Cycle Activity:
Q1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Q2
Q3
Q4
Decode
Read
register ‘f’
Process
Data
Write to
destination
Decode
Read
Process
Data
Write to
destination
register ‘f’
If skip:
Q1
If skip:
Q1
Q2
Q3
Q4
Q2
Q3
Q4
No
No
No
No
operation
operation
operation
operation
No
No
No
No
operation
operation
operation
operation
If skip and followed by 2-word instruction:
If skip and followed by 2-word instruction:
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
No
No
No
No
operation
operation
operation
operation
No
No
No
No
operation
operation
operation
operation
No
No
No
No
operation
operation
operation
operation
No
No
No
No
operation
operation
operation
operation
Example:
HERE
DECFSZ
GOTO
CNT, 1, 1
LOOP
Example:
HERE
ZERO
NZERO
DCFSNZ TEMP, 1, 0
:
:
CONTINUE
Before Instruction
PC
After Instruction
Before Instruction
TEMP
After Instruction
=
Address (HERE)
=
?
CNT
=
CNT - 1
0;
If CNT
=
=
≠
=
TEMP
If TEMP
PC
If TEMP
PC
=
=
=
≠
=
TEMP – 1,
0;
Address (ZERO)
0;
Address (NZERO)
PC
Address (CONTINUE)
0;
If CNT
PC
Address (HERE + 2)
© 2007 Microchip Technology Inc.
Advance Information
DS41303B-page 325
PIC18F2XK20/4XK20
GOTO
Unconditional Branch
INCF
Increment f
Syntax:
GOTO
k
Syntax:
INCF f {,d {,a}}
Operands:
Operation:
Status Affected:
0 ≤ k ≤ 1048575
k → PC<20:1>
None
Operands:
0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
Operation:
(f) + 1 → dest
Encoding:
1st word (k<7:0>)
2nd word(k<19:8>)
Status Affected:
Encoding:
C, DC, N, OV, Z
1110
1111
1111
kkk
k kkk
kkkk
kkkk
kkkk
7
0
8
k
0010
10da
ffff
ffff
19
Description:
GOTOallows an unconditional branch
anywhere within entire
2-Mbyte memory range. The 20-bit
value ‘k’ is loaded into PC<20:1>.
GOTOis always a two-cycle
instruction.
Description:
The contents of register ‘f’ are
incremented. If ‘d’ is ‘0’, the result is
placed in W. If ‘d’ is ‘1’, the result is
placed back in register ‘f’ (default).
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank (default).
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f ≤ 95 (5Fh). See
Section 24.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
Words:
Cycles:
2
2
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read literal
‘k’<7:0>,
No
operation
Read literal
‘k’<19:8>,
Write to PC
Words:
Cycles:
1
1
No
operation
No
No
No
operation
operation
operation
Q Cycle Activity:
Q1
Example:
GOTO THERE
Q2
Q3
Q4
Decode
Read
register ‘f’
Process
Data
Write to
destination
After Instruction
PC
=
Address (THERE)
Example:
INCF
CNT, 1, 0
Before Instruction
CNT
Z
=
FFh
0
=
=
=
C
?
DC
?
After Instruction
CNT
Z
=
00h
1
=
=
=
C
1
DC
1
DS41303B-page 326
Advance Information
© 2007 Microchip Technology Inc.
PIC18F2XK20/4XK20
INFSNZ
Increment f, skip if not 0
INCFSZ
Increment f, skip if 0
Syntax:
INFSNZ f {,d {,a}}
Syntax:
INCFSZ f {,d {,a}}
Operands:
0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
Operands:
0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
Operation:
(f) + 1 → dest,
skip if result ≠ 0
Operation:
(f) + 1 → dest,
skip if result = 0
Status Affected:
Encoding:
None
Status Affected:
Encoding:
None
0100
10da
ffff
ffff
0011
11da
ffff
ffff
Description:
The contents of register ‘f’ are
Description:
The contents of register ‘f’ are
incremented. If ‘d’ is ‘0’, the result is
placed in W. If ‘d’ is ‘1’, the result is
placed back in register ‘f’ (default).
If the result is not ‘0’, the next
instruction, which is already fetched, is
discarded and a NOPis executed
instead, making it a two-cycle
incremented. If ‘d’ is ‘0’, the result is
placed in W. If ‘d’ is ‘1’, the result is
placed back in register ‘f’ (default).
If the result is ‘0’, the next instruction,
which is already fetched, is discarded
and a NOPis executed instead, making
it a two-cycle instruction.
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank (default).
instruction.
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank (default).
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f ≤ 95 (5Fh). See
Section 24.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f ≤ 95 (5Fh). See
Section 24.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
Words:
Cycles:
1
Words:
Cycles:
1
1(2)
1(2)
Note: 3 cycles if skip and followed
by a 2-word instruction.
Note: 3 cycles if skip and followed
by a 2-word instruction.
Q Cycle Activity:
Q1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Q2
Q3
Q4
Decode
Read
register ‘f’
Process
Data
Write to
destination
Decode
Read
register ‘f’
Process
Data
Write to
destination
If skip:
Q1
If skip:
Q1
Q2
Q3
Q4
Q2
Q3
Q4
No
No
No
No
No
No
No
No
operation
operation
operation
operation
operation
operation
operation
operation
If skip and followed by 2-word instruction:
If skip and followed by 2-word instruction:
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
No
No
No
No
No
No
No
No
operation
operation
operation
operation
operation
operation
operation
operation
No
No
No
No
No
No
No
No
operation
operation
operation
operation
operation
operation
operation
operation
Example:
HERE
NZERO
ZERO
INCFSZ
:
:
CNT, 1, 0
Example:
HERE
ZERO
NZERO
INFSNZ REG, 1, 0
Before Instruction
PC
After Instruction
Before Instruction
PC
After Instruction
=
Address (HERE)
=
Address (HERE)
REG
If REG
PC
If REG
PC
=
REG + 1
0;
Address (NZERO)
0;
Address (ZERO)
CNT
If CNT
PC
If CNT
PC
=
CNT + 1
≠
=
=
=
=
=
≠
=
0;
Address (ZERO)
0;
Address (NZERO)
© 2007 Microchip Technology Inc.
Advance Information
DS41303B-page 327
PIC18F2XK20/4XK20
IORLW
Inclusive OR literal with W
IORWF
Inclusive OR W with f
Syntax:
IORLW
k
Syntax:
IORWF f {,d {,a}}
Operands:
Operation:
Status Affected:
Encoding:
Description:
0 ≤ k ≤ 255
(W) .OR. k → W
N, Z
Operands:
0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
Operation:
(W) .OR. (f) → dest
0000
1001
kkkk
kkkk
Status Affected:
Encoding:
N, Z
The contents of W are ORed with the
eight-bit literal ‘k’. The result is placed in
W.
0001
00da
ffff
ffff
Description:
Inclusive OR W with register ‘f’. If ‘d’ is
‘0’, the result is placed in W. If ‘d’ is ‘1’,
the result is placed back in register ‘f’
(default).
Words:
Cycles:
1
1
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank (default).
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f ≤ 95 (5Fh). See
Section 24.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
literal ‘k’
Process
Data
Write to W
Example:
IORLW
35h
Before Instruction
W
=
9Ah
BFh
After Instruction
Words:
Cycles:
1
1
W
=
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
register ‘f’
Process
Data
Write to
destination
Example:
IORWF RESULT, 0, 1
Before Instruction
RESULT =
13h
91h
W
=
After Instruction
RESULT =
13h
93h
W
=
DS41303B-page 328
Advance Information
© 2007 Microchip Technology Inc.
PIC18F2XK20/4XK20
LFSR
Load FSR
MOVF
Move f
Syntax:
LFSR f, k
Syntax:
MOVF f {,d {,a}}
Operands:
0 ≤ f ≤ 2
0 ≤ k ≤ 4095
Operands:
0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
Operation:
k → FSRf
Operation:
f → dest
Status Affected:
Encoding:
None
Status Affected:
Encoding:
N, Z
1110
1111
1110
0000
00ff
k kkk
k kkk
11
kkkk
0101
00da
ffff
ffff
7
Description:
The 12-bit literal ‘k’ is loaded into the
File Select Register pointed to by ‘f’.
Description:
The contents of register ‘f’ are moved to
a destination dependent upon the
status of ‘d’. If ‘d’ is ‘0’, the result is
placed in W. If ‘d’ is ‘1’, the result is
placed back in register ‘f’ (default).
Location ‘f’ can be anywhere in the
256-byte bank.
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank (default).
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f ≤ 95 (5Fh). See
Section 24.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
Words:
Cycles:
2
2
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read literal
‘k’ MSB
Process
Data
Write
literal ‘k’
MSB to
FSRfH
Decode
Read literal
‘k’ LSB
Process
Data
Write literal
‘k’ to FSRfL
Example:
LFSR 2, 3ABh
After Instruction
Words:
Cycles:
1
1
FSR2H
FSR2L
=
=
03h
ABh
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
register ‘f’
Process
Data
Write W
Example:
MOVF
REG, 0, 0
Before Instruction
REG
W
=
=
22h
FFh
After Instruction
REG
W
=
=
22h
22h
© 2007 Microchip Technology Inc.
Advance Information
DS41303B-page 329
PIC18F2XK20/4XK20
MOVFF
Move f to f
MOVLB
Move literal to low nibble in BSR
Syntax:
MOVFF f ,f
Syntax:
MOVLW k
s
d
Operands:
0 ≤ f ≤ 4095
Operands:
Operation:
Status Affected:
Encoding:
Description:
0 ≤ k ≤ 255
k → BSR
None
s
0 ≤ f ≤ 4095
d
Operation:
(f ) → f
s
d
Status Affected:
None
0000
0001
kkkk
kkkk
Encoding:
1st word (source)
2nd word (destin.)
The eight-bit literal ‘k’ is loaded into the
Bank Select Register (BSR). The value
of BSR<7:4> always remains ‘0’,
1100
1111
ffff
ffff
ffff
ffff
ffffs
ffffd
Description:
The contents of source register ‘f ’ are
regardless of the value of k :k .
s
7 4
moved to destination register ‘f ’.
d
Words:
Cycles:
1
1
Location of source ‘f ’ can be anywhere
s
in the 4096-byte data space (000h to
FFFh) and location of destination ‘f ’
can also be anywhere from 000h to
FFFh.
Either source or destination can be W
(a useful special situation).
d
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
literal ‘k’
Process
Data
Write literal
‘k’ to BSR
MOVFFis particularly useful for
transferring a data memory location to a
peripheral register (such as the transmit
buffer or an I/O port).
The MOVFFinstruction cannot use the
PCL, TOSU, TOSH or TOSL as the
destination register.
Example:
MOVLB
5
Before Instruction
BSR Register =
After Instruction
BSR Register =
02h
05h
Words:
Cycles:
2
2 (3)
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
register ‘f’
(src)
Process
Data
No
operation
Decode
No
operation
No
operation
Write
register ‘f’
(dest)
No dummy
read
Example:
MOVFF
REG1, REG2
Before Instruction
REG1
REG2
=
=
33h
11h
After Instruction
REG1
REG2
=
=
33h
33h
DS41303B-page 330
Advance Information
© 2007 Microchip Technology Inc.
PIC18F2XK20/4XK20
MOVLW
Move literal to W
MOVWF
Move W to f
Syntax:
MOVLW
k
Syntax:
MOVWF f {,a}
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
0 ≤ k ≤ 255
k → W
None
Operands:
0 ≤ f ≤ 255
a ∈ [0,1]
Operation:
(W) → f
Status Affected:
Encoding:
None
0000
1110
kkkk
kkkk
0110
111a
ffff
ffff
The eight-bit literal ‘k’ is loaded into W.
Description:
Move data from W to register ‘f’.
Location ‘f’ can be anywhere in the
256-byte bank.
1
1
Cycles:
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank (default).
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f ≤ 95 (5Fh). See
Section 24.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
literal ‘k’
Process
Data
Write to W
Example:
MOVLW
5Ah
After Instruction
W
=
5Ah
Words:
Cycles:
1
1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
register ‘f’
Process
Data
Write
register ‘f’
Example:
MOVWF
REG, 0
Before Instruction
W
REG
=
=
4Fh
FFh
After Instruction
W
REG
=
=
4Fh
4Fh
© 2007 Microchip Technology Inc.
Advance Information
DS41303B-page 331
PIC18F2XK20/4XK20
MULLW
Multiply literal with W
MULWF
Multiply W with f
Syntax:
MULLW
k
Syntax:
MULWF f {,a}
Operands:
Operation:
Status Affected:
Encoding:
Description:
0 ≤ k ≤ 255
Operands:
0 ≤ f ≤ 255
a ∈ [0,1]
(W) x k → PRODH:PRODL
Operation:
(W) x (f) → PRODH:PRODL
None
Status Affected:
Encoding:
None
0000
1101
kkkk
kkkk
0000
001a
ffff
ffff
An unsigned multiplication is carried
out between the contents of W and the
8-bit literal ‘k’. The 16-bit result is
placed in the PRODH:PRODL register
pair. PRODH contains the high byte.
W is unchanged.
None of the Status flags are affected.
Note that neither overflow nor carry is
possible in this operation. A zero result
is possible but not detected.
Description:
An unsigned multiplication is carried
out between the contents of W and the
register file location ‘f’. The 16-bit
result is stored in the PRODH:PRODL
register pair. PRODH contains the
high byte. Both W and ‘f’ are
unchanged.
None of the Status flags are affected.
Note that neither overflow nor carry is
possible in this operation. A zero
result is possible but not detected.
If ‘a’ is ‘0’, the Access Bank is
selected. If ‘a’ is ‘1’, the BSR is used
to select the GPR bank (default).
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction
operates in Indexed Literal Offset
Addressing mode whenever
Words:
Cycles:
1
1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
literal ‘k’
Process
Data
Write
registers
PRODH:
PRODL
f ≤ 95 (5Fh). See Section 24.2.3
“Byte-Oriented and Bit-Oriented
Instructions in Indexed Literal Offset
Mode” for details.
Example:
MULLW
0C4h
Before Instruction
Words:
Cycles:
1
1
W
PRODH
PRODL
=
=
=
E2h
?
?
Q Cycle Activity:
Q1
After Instruction
W
Q2
Q3
Q4
=
=
=
E2h
ADh
08h
Decode
Read
register ‘f’
Process
Data
Write
PRODH
PRODL
registers
PRODH:
PRODL
Example:
MULWF
REG, 1
Before Instruction
W
=
C4h
REG
PRODH
PRODL
=
=
=
B5h
?
?
After Instruction
W
=
C4h
REG
PRODH
PRODL
=
=
=
B5h
8Ah
94h
DS41303B-page 332
Advance Information
© 2007 Microchip Technology Inc.
PIC18F2XK20/4XK20
NEGF
Negate f
NOP
No Operation
Syntax:
NEGF f {,a}
Syntax:
NOP
Operands:
0 ≤ f ≤ 255
a ∈ [0,1]
Operands:
Operation:
Status Affected:
Encoding:
None
No operation
None
Operation:
( f ) + 1 → f
Status Affected:
Encoding:
N, OV, C, DC, Z
0000
1111
0000
xxxx
0000
xxxx
0000
xxxx
0110
110a
ffff
ffff
Description:
Location ‘f’ is negated using two’s
complement. The result is placed in the
data memory location ‘f’.
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank (default).
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f ≤ 95 (5Fh). See
Section 24.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
Description:
Words:
No operation.
1
1
Cycles:
Q Cycle Activity:
Q1
Q2
Q3
No
Q4
Decode
No
operation
No
operation
operation
Example:
None.
Words:
Cycles:
1
1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
register ‘f’
Process
Data
Write
register ‘f’
Example:
NEGF
REG, 1
Before Instruction
REG
After Instruction
REG
=
0011 1010 [3Ah]
1100 0110 [C6h]
=
© 2007 Microchip Technology Inc.
Advance Information
DS41303B-page 333
PIC18F2XK20/4XK20
POP
Pop Top of Return Stack
PUSH
Push Top of Return Stack
Syntax:
POP
Syntax:
PUSH
Operands:
Operation:
Status Affected:
Encoding:
Description:
None
Operands:
Operation:
Status Affected:
Encoding:
Description:
None
(TOS) → bit bucket
(PC + 2) → TOS
None
None
0000
0000
0000
0110
0000
0000
0000
0101
The TOS value is pulled off the return
stack and is discarded. The TOS value
then becomes the previous value that
was pushed onto the return stack.
This instruction is provided to enable
the user to properly manage the return
stack to incorporate a software stack.
The PC + 2 is pushed onto the top of
the return stack. The previous TOS
value is pushed down on the stack.
This instruction allows implementing a
software stack by modifying TOS and
then pushing it onto the return stack.
Words:
Cycles:
1
1
Words:
Cycles:
1
1
Q Cycle Activity:
Q1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Q2
Q3
Q4
Decode
PUSH
No
No
Decode
No
operation
POP TOS
value
No
operation
PC + 2 onto
return stack
operation
operation
Example:
POP
Example:
PUSH
GOTO
NEW
Before Instruction
Before Instruction
TOS
Stack (1 level down)
TOS
PC
=
=
345Ah
0124h
=
=
0031A2h
014332h
After Instruction
After Instruction
PC
=
=
=
0126h
0126h
345Ah
TOS
TOS
PC
=
=
014332h
NEW
Stack (1 level down)
DS41303B-page 334
Advance Information
© 2007 Microchip Technology Inc.
PIC18F2XK20/4XK20
RCALL
Relative Call
RESET
Reset
Syntax:
RCALL
n
Syntax:
RESET
None
Operands:
Operation:
-1024 ≤ n ≤ 1023
Operands:
Operation:
(PC) + 2 → TOS,
(PC) + 2 + 2n → PC
Reset all registers and flags that are
affected by a MCLR Reset.
Status Affected:
Encoding:
None
Status Affected:
Encoding:
All
1101
1nnn
nnnn
nnnn
0000
0000
1111
1111
Description:
Subroutine call with a jump up to 1K
from the current location. First, return
address (PC + 2) is pushed onto the
stack. Then, add the 2’s complement
number ‘2n’ to the PC. Since the PC will
have incremented to fetch the next
instruction, the new address will be
PC + 2 + 2n. This instruction is a
two-cycle instruction.
Description:
This instruction provides a way to
execute a MCLR Reset by software.
Words:
Cycles:
1
1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Start
No
No
Reset
operation
operation
Words:
Cycles:
1
2
Example:
RESET
Q Cycle Activity:
Q1
After Instruction
Registers =
Q2
Q3
Q4
Reset Value
Reset Value
Flags*
=
Decode
Read literal
‘n’
Process
Data
Write to PC
PUSH PCto
stack
No
No
No
No
operation
operation
operation
operation
Example:
HERE
RCALL Jump
Before Instruction
PC
After Instruction
PC
TOS =
=
Address (HERE)
=
Address (Jump)
Address (HERE + 2)
© 2007 Microchip Technology Inc.
Advance Information
DS41303B-page 335
PIC18F2XK20/4XK20
RETFIE
Return from Interrupt
RETLW
Return literal to W
Syntax:
RETFIE {s}
Syntax:
RETLW k
Operands:
Operation:
s ∈ [0,1]
Operands:
Operation:
0 ≤ k ≤ 255
(TOS) → PC,
k → W,
1 → GIE/GIEH or PEIE/GIEL,
if s = 1
(TOS) → PC,
PCLATU, PCLATH are unchanged
(WS) → W,
(STATUSS) → Status,
(BSRS) → BSR,
Status Affected:
Encoding:
None
0000
1100
kkkk
kkkk
PCLATU, PCLATH are unchanged.
Description:
W is loaded with the eight-bit literal ‘k’.
The program counter is loaded from the
top of the stack (the return address).
The high address latch (PCLATH)
remains unchanged.
Status Affected:
Encoding:
GIE/GIEH, PEIE/GIEL.
0000
0000
0001
000s
Description:
Return from interrupt. Stack is popped
and Top-of-Stack (TOS) is loaded into
the PC. Interrupts are enabled by
setting either the high or low priority
global interrupt enable bit. If ‘s’ = 1, the
contents of the shadow registers, WS,
STATUSS and BSRS, are loaded into
their corresponding registers, W,
Words:
Cycles:
1
2
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
literal ‘k’
Process
Data
POP PC
from stack,
Write to W
Status and BSR. If ‘s’ = 0, no update of
these registers occurs (default).
No
operation
No
operation
No
operation
No
operation
Words:
Cycles:
1
2
Q Cycle Activity:
Q1
Example:
Q2
Q3
Q4
CALL TABLE ; W contains table
; offset value
Decode
No
operation
No
operation
POP PC
from stack
; W now has
; table value
Set GIEH or
GIEL
:
No
operation
No
operation
No
operation
No
operation
TABLE
ADDWF PCL ; W = offset
RETLW k0
RETLW k1
; Begin table
;
Example:
RETFIE
1
:
:
After Interrupt
PC
W
=
=
=
=
=
TOS
WS
RETLW kn
; End of table
BSR
Status
GIE/GIEH, PEIE/GIEL
BSRS
STATUSS
1
Before Instruction
W
=
07h
After Instruction
W
=
value of kn
DS41303B-page 336
Advance Information
© 2007 Microchip Technology Inc.
PIC18F2XK20/4XK20
RETURN
Return from Subroutine
RLCF
Rotate Left f through Carry
Syntax:
RETURN {s}
Syntax:
RLCF f {,d {,a}}
Operands:
Operation:
s ∈ [0,1]
Operands:
0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
(TOS) → PC,
if s = 1
(WS) → W,
Operation:
(f<n>) → dest<n + 1>,
(f<7>) → C,
(C) → dest<0>
(STATUSS) → Status,
(BSRS) → BSR,
PCLATU, PCLATH are unchanged
Status Affected:
Encoding:
C, N, Z
Status Affected:
Encoding:
None
0011
01da
ffff
ffff
0000
0000
0001
001s
Description:
The contents of register ‘f’ are rotated
one bit to the left through the CARRY
flag. If ‘d’ is ‘0’, the result is placed in
W. If ‘d’ is ‘1’, the result is stored back
in register ‘f’ (default).
If ‘a’ is ‘0’, the Access Bank is
selected. If ‘a’ is ‘1’, the BSR is used to
select the GPR bank (default).
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction
operates in Indexed Literal Offset
Addressing mode whenever
Description:
Return from subroutine. The stack is
popped and the top of the stack (TOS)
is loaded into the program counter. If
‘s’= 1, the contents of the shadow
registers, WS, STATUSS and BSRS,
are loaded into their corresponding
registers, W, Status and BSR. If
‘s’ = 0, no update of these registers
occurs (default).
Words:
Cycles:
1
2
f ≤ 95 (5Fh). See Section 24.2.3
“Byte-Oriented and Bit-Oriented
Instructions in Indexed Literal Offset
Mode” for details.
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
No
operation
Process
Data
POP PC
from stack
register f
C
No
No
No
No
Words:
Cycles:
1
1
operation
operation
operation
operation
Q Cycle Activity:
Q1
Example:
RETURN
Q2
Q3
Q4
After Instruction:
PC = TOS
Decode
Read
register ‘f’
Process
Data
Write to
destination
Example:
RLCF
REG, 0, 0
Before Instruction
REG
C
=
=
1110 0110
0
After Instruction
REG
=
1110 0110
W
C
=
=
1100 1100
1
© 2007 Microchip Technology Inc.
Advance Information
DS41303B-page 337
PIC18F2XK20/4XK20
RLNCF
Rotate Left f (No Carry)
RRCF
Rotate Right f through Carry
Syntax:
RLNCF f {,d {,a}}
Syntax:
RRCF f {,d {,a}}
Operands:
0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
Operands:
0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
Operation:
(f<n>) → dest<n + 1>,
(f<7>) → dest<0>
Operation:
(f<n>) → dest<n – 1>,
(f<0>) → C,
(C) → dest<7>
Status Affected:
Encoding:
N, Z
Status Affected:
Encoding:
C, N, Z
0100
01da
ffff
ffff
0011
00da
ffff
ffff
Description:
The contents of register ‘f’ are rotated
one bit to the left. If ‘d’ is ‘0’, the result
is placed in W. If ‘d’ is ‘1’, the result is
stored back in register ‘f’ (default).
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank (default).
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f ≤ 95 (5Fh). See
Section 24.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
Description:
The contents of register ‘f’ are rotated
one bit to the right through the CARRY
flag. If ‘d’ is ‘0’, the result is placed in W.
If ‘d’ is ‘1’, the result is placed back in
register ‘f’ (default).
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank (default).
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f ≤ 95 (5Fh). See
Section 24.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
register f
register f
C
Words:
Cycles:
1
1
Words:
Cycles:
1
1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Q Cycle Activity:
Q1
Decode
Read
register ‘f’
Process
Data
Write to
destination
Q2
Q3
Q4
Decode
Read
register ‘f’
Process
Data
Write to
destination
Example:
RLNCF
REG, 1, 0
Before Instruction
REG
After Instruction
Example:
RRCF
REG, 0, 0
=
1010 1011
0101 0111
Before Instruction
REG
=
REG
C
=
=
1110 0110
0
After Instruction
REG
=
1110 0110
W
C
=
=
0111 0011
0
DS41303B-page 338
Advance Information
© 2007 Microchip Technology Inc.
PIC18F2XK20/4XK20
RRNCF
Rotate Right f (No Carry)
SETF
Set f
Syntax:
RRNCF f {,d {,a}}
Syntax:
SETF f {,a}
Operands:
0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
Operands:
0 ≤ f ≤ 255
a ∈ [0,1]
Operation:
FFh → f
Operation:
(f<n>) → dest<n – 1>,
(f<0>) → dest<7>
Status Affected:
Encoding:
None
0110
100a
ffff
ffff
Status Affected:
Encoding:
N, Z
Description:
The contents of the specified register
are set to FFh.
0100
00da
ffff
ffff
Description:
The contents of register ‘f’ are rotated
one bit to the right. If ‘d’ is ‘0’, the result
is placed in W. If ‘d’ is ‘1’, the result is
placed back in register ‘f’ (default).
If ‘a’ is ‘0’, the Access Bank will be
selected, overriding the BSR value. If ‘a’
is ‘1’, then the bank will be selected as
per the BSR value (default).
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f ≤ 95 (5Fh). See
Section 24.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank (default).
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f ≤ 95 (5Fh). See
Section 24.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
Words:
Cycles:
1
1
Q Cycle Activity:
Q1
Q2
Q3
Q4
register f
Decode
Read
register ‘f’
Process
Data
Write
register ‘f’
Words:
Cycles:
1
1
Example:
SETF
REG, 1
Q Cycle Activity:
Q1
Before Instruction
REG
After Instruction
REG
=
=
5Ah
FFh
Q2
Q3
Q4
Decode
Read
register ‘f’
Process
Data
Write to
destination
Example 1:
RRNCF
REG, 1, 0
Before Instruction
REG
After Instruction
REG
=
1101 0111
1110 1011
RRNCF REG, 0, 0
=
Example 2:
Before Instruction
W
REG
=
=
?
1101 0111
After Instruction
W
REG
=
=
1110 1011
1101 0111
© 2007 Microchip Technology Inc.
Advance Information
DS41303B-page 339
PIC18F2XK20/4XK20
SLEEP
Enter Sleep mode
SUBFWB
Subtract f from W with borrow
Syntax:
SLEEP
None
Syntax:
SUBFWB f {,d {,a}}
Operands:
Operation:
Operands:
0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
00h → WDT,
0 → WDT postscaler,
1 → TO,
Operation:
(W) – (f) – (C) → dest
0 → PD
Status Affected:
Encoding:
N, OV, C, DC, Z
Status Affected:
Encoding:
TO, PD
0101
01da
ffff
ffff
0000
0000
0000
0011
Description:
Subtract register ‘f’ and CARRY flag
(borrow) from W (2’s complement
method). If ‘d’ is ‘0’, the result is stored
in W. If ‘d’ is ‘1’, the result is stored in
register ‘f’ (default).
Description:
The Power-down Status bit (PD) is
cleared. The Time-out Status bit (TO)
is set. Watchdog Timer and its
postscaler are cleared.
The processor is put into Sleep mode
with the oscillator stopped.
If ‘a’ is ‘0’, the Access Bank is
selected. If ‘a’ is ‘1’, the BSR is used
to select the GPR bank (default).
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction
operates in Indexed Literal Offset
Addressing mode whenever
f ≤ 95 (5Fh). See Section 24.2.3
“Byte-Oriented and Bit-Oriented
Instructions in Indexed Literal Offset
Mode” for details.
Words:
Cycles:
1
1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
No
operation
Process
Data
Go to
Sleep
Example:
SLEEP
Words:
Cycles:
1
1
Before Instruction
TO
PD
=
=
?
?
Q Cycle Activity:
Q1
Q2
Q3
Q4
After Instruction
Decode
Read
register ‘f’
Process
Data
Write to
destination
TO
PD
=
=
1 †
0
Example 1:
SUBFWB
REG, 1, 0
†
If WDT causes wake-up, this bit is cleared.
Before Instruction
REG
W
C
=
=
=
3
2
1
After Instruction
REG
W
C
=
FF
2
=
=
=
=
0
Z
0
1
N
; result is negative
Example 2:
Before Instruction
SUBFWB
REG, 0, 0
REG
W
=
=
=
2
5
1
C
After Instruction
REG
W
C
=
2
3
1
0
=
=
=
=
Z
N
0
; result is positive
Example 3:
SUBFWB
REG, 1, 0
Before Instruction
REG
W
=
=
=
1
2
0
C
After Instruction
REG
W
C
=
0
2
1
1
0
=
=
=
=
Z
; result is zero
N
DS41303B-page 340
Advance Information
© 2007 Microchip Technology Inc.
PIC18F2XK20/4XK20
SUBLW
Subtract W from literal
SUBWF
Subtract W from f
Syntax:
SUBLW
k
Syntax:
SUBWF f {,d {,a}}
Operands:
Operation:
Status Affected:
Encoding:
Description
0 ≤ k ≤ 255
Operands:
0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
k – (W) → W
N, OV, C, DC, Z
Operation:
(f) – (W) → dest
0000
1000
kkkk
kkkk
Status Affected:
Encoding:
N, OV, C, DC, Z
W is subtracted from the eight-bit
literal ‘k’. The result is placed in W.
0101
11da
ffff
ffff
Description:
Subtract W from register ‘f’ (2’s
complement method). If ‘d’ is ‘0’, the
result is stored in W. If ‘d’ is ‘1’, the
result is stored back in register ‘f’
(default).
Words:
1
1
Cycles:
Q Cycle Activity:
Q1
Q2
Q3
Q4
If ‘a’ is ‘0’, the Access Bank is
selected. If ‘a’ is ‘1’, the BSR is used
to select the GPR bank (default).
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction
operates in Indexed Literal Offset
Addressing mode whenever
f ≤ 95 (5Fh). See Section 24.2.3
“Byte-Oriented and Bit-Oriented
Instructions in Indexed Literal Offset
Mode” for details.
Decode
Read
literal ‘k’
Process
Data
Write to W
Example 1:
SUBLW 02h
Before Instruction
W
C
=
=
01h
?
After Instruction
W
C
Z
=
01h
=
=
=
1
0
0
; result is positive
N
Words:
Cycles:
1
1
Example 2:
SUBLW 02h
Before Instruction
Q Cycle Activity:
Q1
W
C
=
=
02h
?
Q2
Q3
Q4
After Instruction
Decode
Read
register ‘f’
Process
Data
Write to
destination
W
C
Z
=
00h
=
=
=
1
1
0
; result is zero
N
Example 1:
SUBWF
REG, 1, 0
Before Instruction
Example 3:
SUBLW 02h
REG
W
C
=
3
2
?
Before Instruction
=
=
W
C
=
=
03h
?
After Instruction
After Instruction
REG
W
C
=
1
2
1
0
0
W
C
Z
=
FFh ; (2’s complement)
=
=
=
=
=
=
=
0
0
1
; result is negative
; result is positive
Z
N
N
Example 2:
Before Instruction
SUBWF
REG, 0, 0
REG
W
=
=
=
2
2
?
C
After Instruction
REG
W
C
=
2
0
1
1
0
=
=
=
=
; result is zero
Z
N
Example 3:
Before Instruction
SUBWF
REG, 1, 0
REG
W
=
=
=
1
2
?
C
After Instruction
REG
W
C
=
FFh ;(2’s complement)
2
0
0
1
=
=
=
=
; result is negative
Z
N
© 2007 Microchip Technology Inc.
Advance Information
DS41303B-page 341
PIC18F2XK20/4XK20
SUBWFB
Subtract W from f with Borrow
SWAPF
Swap f
SUBWFB f {,d {,a}}
Syntax:
Syntax:
SWAPF f {,d {,a}}
Operands:
0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
Operands:
0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
Operation:
(f) – (W) – (C) → dest
Operation:
(f<3:0>) → dest<7:4>,
(f<7:4>) → dest<3:0>
Status Affected:
Encoding:
N, OV, C, DC, Z
0101
10da
ffff
ffff
Status Affected:
Encoding:
None
Description:
Subtract W and the CARRY flag
0011
10da
ffff
ffff
(borrow) from register ‘f’ (2’s comple-
ment method). If ‘d’ is ‘0’, the result is
stored in W. If ‘d’ is ‘1’, the result is
stored back in register ‘f’ (default).
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank (default).
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f ≤ 95 (5Fh). See
Section 24.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
Description:
The upper and lower nibbles of register
‘f’ are exchanged. If ‘d’ is ‘0’, the result
is placed in W. If ‘d’ is ‘1’, the result is
placed in register ‘f’ (default).
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank (default).
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f ≤ 95 (5Fh). See
Section 24.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
Words:
Cycles:
1
1
Words:
1
1
Cycles:
Q Cycle Activity:
Q1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Q2
Q3
Q4
Decode
Read
register ‘f’
Process
Data
Write to
destination
Decode
Read
register ‘f’
Process
Data
Write to
destination
Example 1:
SUBWFB REG, 1, 0
Before Instruction
REG
W
=
=
=
19h
0Dh
1
(0001 1001)
(0000 1101)
Example:
SWAPF
REG, 1, 0
C
Before Instruction
After Instruction
REG
=
53h
35h
REG
=
0Ch
0Dh
1
(0000 1011)
(0000 1101)
After Instruction
W
=
=
=
=
REG
=
C
Z
0
N
0
; result is positive
Example 2:
SUBWFB REG, 0, 0
Before Instruction
REG
W
=
=
=
1Bh
1Ah
0
(0001 1011)
(0001 1010)
C
After Instruction
REG
W
C
=
1Bh
00h
1
(0001 1011)
=
=
=
=
Z
1
; result is zero
N
0
Example 3:
Before Instruction
SUBWFB REG, 1, 0
REG
=
=
=
03h
0Eh
1
(0000 0011)
(0000 1101)
W
C
After Instruction
REG
=
F5h
(1111 0100)
; [2’s comp]
W
=
=
=
=
0Eh
0
0
1
(0000 1101)
C
Z
N
; result is negative
DS41303B-page 342
Advance Information
© 2007 Microchip Technology Inc.
PIC18F2XK20/4XK20
TBLRD
Table Read
TBLRD
Table Read (Continued)
Syntax:
TBLRD ( *; *+; *-; +*)
None
Example1:
TBLRD *+ ;
Operands:
Operation:
Before Instruction
TABLAT
TBLPTR
MEMORY (00A356h)
=
=
=
55h
00A356h
34h
if TBLRD *,
(Prog Mem (TBLPTR)) → TABLAT;
TBLPTR – No Change;
if TBLRD *+,
(Prog Mem (TBLPTR)) → TABLAT;
(TBLPTR) + 1 → TBLPTR;
if TBLRD *-,
(Prog Mem (TBLPTR)) → TABLAT;
(TBLPTR) – 1 → TBLPTR;
if TBLRD +*,
(TBLPTR) + 1 → TBLPTR;
(Prog Mem (TBLPTR)) → TABLAT;
After Instruction
TABLAT
TBLPTR
=
=
34h
00A357h
Example2:
TBLRD +* ;
Before Instruction
TABLAT
TBLPTR
MEMORY (01A357h)
MEMORY (01A358h)
After Instruction
=
=
=
=
AAh
01A357h
12h
34h
TABLAT
TBLPTR
=
=
34h
01A358h
Status Affected: None
Encoding:
0000
0000
0000
10nn
nn=0 *
=1 *+
=2 *-
=3 +*
Description:
This instruction is used to read the contents
of Program Memory (P.M.). To address the
program memory, a pointer called Table
Pointer (TBLPTR) is used.
The TBLPTR (a 21-bit pointer) points to
each byte in the program memory. TBLPTR
has a 2-Mbyte address range.
TBLPTR[0] = 0: LeastSignificantByte
of Program Memory
Word
TBLPTR[0] = 1: Most Significant Byte
of Program Memory
Word
The TBLRDinstruction can modify the value
of TBLPTR as follows:
•
•
•
•
no change
post-increment
post-decrement
pre-increment
Words:
Cycles:
1
2
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
No
No
No
operation
operation
operation
No
No operation
No
No operation
operation (Read Program operation (Write TABLAT)
Memory)
© 2007 Microchip Technology Inc.
Advance Information
DS41303B-page 343
PIC18F2XK20/4XK20
TBLWT
Table Write
TBLWT
Table Write (Continued)
Syntax:
TBLWT ( *; *+; *-; +*)
None
Example1:
TBLWT *+;
Operands:
Operation:
Before Instruction
if TBLWT*,
TABLAT
TBLPTR
HOLDING REGISTER
(00A356h)
=
=
55h
00A356h
(TABLAT) → Holding Register;
TBLPTR – No Change;
if TBLWT*+,
(TABLAT) → Holding Register;
(TBLPTR) + 1 → TBLPTR;
if TBLWT*-,
(TABLAT) → Holding Register;
(TBLPTR) – 1 → TBLPTR;
if TBLWT+*,
(TBLPTR) + 1 → TBLPTR;
(TABLAT) → Holding Register;
=
FFh
After Instructions (table write completion)
TABLAT
TBLPTR
HOLDING REGISTER
(00A356h)
=
=
55h
00A357h
=
55h
Example 2:
TBLWT +*;
Before Instruction
TABLAT
TBLPTR
HOLDING REGISTER
(01389Ah)
HOLDING REGISTER
(01389Bh)
=
=
34h
01389Ah
Status Affected: None
=
FFh
Encoding:
0000
0000
0000
11nn
nn=0 *
=1 *+
=2 *-
=3 +*
=
FFh
After Instruction (table write completion)
TABLAT
TBLPTR
=
=
34h
01389Bh
HOLDING REGISTER
(01389Ah)
HOLDING REGISTER
(01389Bh)
Description:
This instruction uses the 3 LSBs of
TBLPTR to determine which of the
8 holding registers the TABLAT is written
to. The holding registers are used to
program the contents of Program
Memory (P.M.). (Refer to Section 6.0
“Flash Program Memory” for additional
details on programming Flash memory.)
The TBLPTR (a 21-bit pointer) points to
each byte in the program memory.
TBLPTR has a 2-MByte address range.
The LSb of the TBLPTR selects which
byte of the program memory location to
access.
=
=
FFh
34h
TBLPTR[0] = 0: Least Significant
Byte of Program
Memory Word
TBLPTR[0] = 1: Most Significant
Byte of Program
Memory Word
The TBLWT instruction can modify the
value of TBLPTR as follows:
•
•
•
•
no change
post-increment
post-decrement
pre-increment
Words:
1
2
Cycles:
Q Cycle Activity:
Q1
Q2
No
Q3
No
Q4
No
Decode
operation operation operation
No
No No No
operation operation operation operation
(Read
TABLAT)
(Write to
Holding
Register )
DS41303B-page 344
Advance Information
© 2007 Microchip Technology Inc.
PIC18F2XK20/4XK20
TSTFSZ
Test f, skip if 0
XORLW
Exclusive OR literal with W
Syntax:
TSTFSZ f {,a}
Syntax:
XORLW k
Operands:
0 ≤ f ≤ 255
a ∈ [0,1]
Operands:
Operation:
Status Affected:
Encoding:
Description:
0 ≤ k ≤ 255
(W) .XOR. k → W
N, Z
Operation:
skip if f = 0
Status Affected:
Encoding:
None
0000
1010
kkkk
kkkk
0110
011a
ffff
ffff
The contents of W are XORed with
the 8-bit literal ‘k’. The result is placed
in W.
Description:
If ‘f’ = 0, the next instruction fetched
during the current instruction execution
is discarded and a NOPis executed,
making this a two-cycle instruction.
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank (default).
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f ≤ 95 (5Fh). See
Section 24.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
Words:
1
1
Cycles:
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
literal ‘k’
Process
Data
Write to W
Example:
XORLW
0AFh
Before Instruction
W
=
B5h
1Ah
Words:
Cycles:
1
After Instruction
1(2)
W
=
Note: 3 cycles if skip and followed
by a 2-word instruction.
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
register ‘f’
Process
Data
No
operation
If skip:
Q1
Q2
Q3
Q4
No
No
No
No
operation
operation
operation
operation
If skip and followed by 2-word instruction:
Q1
Q2
Q3
Q4
No
No
No
No
operation
operation
operation
operation
No
No
No
No
operation
operation
operation
operation
Example:
HERE
NZERO
ZERO
TSTFSZ CNT, 1
:
:
Before Instruction
PC
=
Address (HERE)
After Instruction
If CNT
PC
If CNT
PC
=
=
≠
=
00h,
Address (ZERO)
00h,
Address (NZERO)
© 2007 Microchip Technology Inc.
Advance Information
DS41303B-page 345
PIC18F2XK20/4XK20
XORWF
Exclusive OR W with f
Syntax:
XORWF f {,d {,a}}
Operands:
0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
Operation:
(W) .XOR. (f) → dest
Status Affected:
Encoding:
N, Z
0001
10da
ffff
ffff
Description:
Exclusive OR the contents of W with
register ‘f’. If ‘d’ is ‘0’, the result is stored
in W. If ‘d’ is ‘1’, the result is stored back
in the register ‘f’ (default).
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank (default).
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f ≤ 95 (5Fh). See
Section 24.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
Words:
1
1
Cycles:
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
register ‘f’
Process
Data
Write to
destination
Example:
XORWF
REG, 1, 0
Before Instruction
REG
W
=
=
AFh
B5h
After Instruction
REG
W
=
=
1Ah
B5h
DS41303B-page 346
Advance Information
© 2007 Microchip Technology Inc.
PIC18F2XK20/4XK20
A summary of the instructions in the extended instruc-
tion set is provided in Table 24-3. Detailed descriptions
are provided in Section 24.2.2 “Extended Instruction
Set”. The opcode field descriptions in Table 24-1
(page 306) apply to both the standard and extended
PIC18 instruction sets.
24.2 Extended Instruction Set
In addition to the standard 75 instructions of the PIC18
instruction set, PIC18F2XK20/4XK20 devices also
provide an optional extension to the core CPU
functionality. The added features include eight
additional instructions that augment indirect and
indexed addressing operations and the implementation
of Indexed Literal Offset Addressing mode for many of
the standard PIC18 instructions.
Note:
The instruction set extension and the
Indexed Literal Offset Addressing mode
were designed for optimizing applications
written in C; the user may likely never use
these instructions directly in assembler.
The syntax for these commands is pro-
vided as a reference for users who may be
reviewing code that has been generated
by a compiler.
The additional features of the extended instruction set
are disabled by default. To enable them, users must set
the XINST Configuration bit.
The instructions in the extended set can all be
classified as literal operations, which either manipulate
the File Select Registers, or use them for indexed
addressing. Two of the instructions, ADDFSR and
SUBFSR, each have an additional special instantiation
for using FSR2. These versions (ADDULNK and
SUBULNK) allow for automatic return after execution.
24.2.1
EXTENDED INSTRUCTION SYNTAX
Most of the extended instructions use indexed
arguments, using one of the File Select Registers and
some offset to specify a source or destination register.
When an argument for an instruction serves as part of
indexed addressing, it is enclosed in square brackets
(“[ ]”). This is done to indicate that the argument is used
as an index or offset. MPASM™ Assembler will flag an
error if it determines that an index or offset value is not
bracketed.
The extended instructions are specifically implemented
to optimize re-entrant program code (that is, code that
is recursive or that uses a software stack) written in
high-level languages, particularly C. Among other
things, they allow users working in high-level
languages to perform certain operations on data
structures more efficiently. These include:
When the extended instruction set is enabled, brackets
are also used to indicate index arguments in byte-
oriented and bit-oriented instructions. This is in addition
to other changes in their syntax. For more details, see
Section 24.2.3.1 “Extended Instruction Syntax with
Standard PIC18 Commands”.
• dynamic allocation and deallocation of software
stack space when entering and leaving
subroutines
• function pointer invocation
• software Stack Pointer manipulation
• manipulation of variables located in a software
stack
Note:
In the past, square brackets have been
used to denote optional arguments in the
PIC18 and earlier instruction sets. In this
text and going forward, optional
arguments are denoted by braces (“{ }”).
TABLE 24-3: EXTENSIONS TO THE PIC18 INSTRUCTION SET
16-Bit Instruction Word
MSb LSb
Mnemonic,
Operands
Status
Affected
Description
Cycles
ADDFSR
ADDULNK
CALLW
f, k
k
Add literal to FSR
Add literal to FSR2 and return
Call subroutine using WREG
1
2
2
2
1110 1000 ffkk kkkk
1110 1000 11kk kkkk
0000 0000 0001 0100
1110 1011 0zzz zzzz
1111 ffff ffff ffff
1110 1011 1zzz zzzz
1111 xxxx xzzz zzzz
1110 1010 kkkk kkkk
None
None
None
None
MOVSF
zs, fd Move zs (source) to 1st word
fd (destination) 2nd word
zs, zd Move zs (source) to 1st word
MOVSS
PUSHL
2
1
None
None
zd (destination)
Store literal at FSR2,
decrement FSR2
2nd word
k
SUBFSR
SUBULNK
f, k
k
Subtract literal from FSR
Subtract literal from FSR2 and
return
1
2
1110 1001 ffkk kkkk
1110 1001 11kk kkkk
None
None
© 2007 Microchip Technology Inc.
Advance Information
DS41303B-page 347
PIC18F2XK20/4XK20
24.2.2
EXTENDED INSTRUCTION SET
ADDFSR
Add Literal to FSR
ADDULNK
Add Literal to FSR2 and Return
Syntax:
ADDFSR f, k
Syntax:
ADDULNK k
Operands:
0 ≤ k ≤ 63
f ∈ [ 0, 1, 2 ]
FSR(f) + k → FSR(f)
None
Operands:
Operation:
0 ≤ k ≤ 63
FSR2 + k → FSR2,
(TOS) → PC
None
Operation:
Status Affected:
Encoding:
Status Affected:
Encoding:
1110
1000
ffkk
kkkk
1110
1000
11kk
kkkk
Description:
The 6-bit literal ‘k’ is added to the
contents of the FSR specified by ‘f’.
Description:
The 6-bit literal ‘k’ is added to the
contents of FSR2. A RETURNis then
executed by loading the PC with the
TOS.
Words:
1
1
Cycles:
The instruction takes two cycles to
execute; a NOPis performed during
the second cycle.
This may be thought of as a special
case of the ADDFSRinstruction,
where f = 3 (binary ‘11’); it operates
only on FSR2.
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
literal ‘k’
Process
Data
Write to
FSR
ADDFSR 2, 23h
Example:
Words:
Cycles:
1
2
Before Instruction
FSR2
After Instruction
FSR2
=
03FFh
0422h
Q Cycle Activity:
Q1
=
Q2
Q3
Q4
Decode
Read
literal ‘k’
Process
Data
Write to
FSR
No
No
No
No
Operation
Operation
Operation
Operation
ADDULNK 23h
Example:
Before Instruction
FSR2
PC
=
=
03FFh
0100h
After Instruction
FSR2
PC
=
=
0422h
(TOS)
Note:
All PIC18 instructions may take an optional label argument preceding the instruction mnemonic for use in
symbolic addressing. If a label is used, the instruction syntax then becomes: {label} instruction argument(s).
DS41303B-page 348
Advance Information
© 2007 Microchip Technology Inc.
PIC18F2XK20/4XK20
CALLW
Subroutine Call Using WREG
MOVSF
Move Indexed to f
Syntax:
CALLW
None
Syntax:
MOVSF [z ], f
s
d
Operands:
Operation:
Operands:
0 ≤ z ≤ 127
s
0 ≤ f ≤ 4095
d
(PC + 2) → TOS,
(W) → PCL,
Operation:
((FSR2) + z ) → f
s
d
(PCLATH) → PCH,
(PCLATU) → PCU
Status Affected:
None
Encoding:
1st word (source)
2nd word (destin.)
Status Affected:
Encoding:
None
1110
1111
1011
ffff
0zzz
ffff
zzzz
ffff
s
0000
0000
0001
0100
d
Description
First, the return address (PC + 2) is
pushed onto the return stack. Next, the
contents of W are written to PCL; the
existing value is discarded. Then, the
contents of PCLATH and PCLATU are
latched into PCH and PCU,
respectively. The second cycle is
executed as a NOPinstruction while the
new next instruction is fetched.
Description:
The contents of the source register are
moved to destination register ‘f ’. The
d
actual address of the source register is
determined by adding the 7-bit literal
offset ‘z ’ in the first word to the value of
s
FSR2. The address of the destination
register is specified by the 12-bit literal
‘f ’ in the second word. Both addresses
d
can be anywhere in the 4096-byte data
space (000h to FFFh).
The MOVSFinstruction cannot use the
PCL, TOSU, TOSH or TOSL as the
destination register.
If the resultant source address points to
an indirect addressing register, the
value returned will be 00h.
Unlike CALL, there is no option to
update W, Status or BSR.
Words:
Cycles:
1
2
Q Cycle Activity:
Q1
Q2
Q3
Q4
Words:
Cycles:
2
2
Decode
Read
WREG
PUSH PC to
stack
No
operation
No
operation
No
operation
No
operation
No
operation
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Determine
Determine
Read
source addr source addr source reg
Example:
HERE
CALLW
Decode
No
operation
No
operation
Write
register ‘f’
(dest)
Before Instruction
PC
=
address (HERE)
PCLATH =
PCLATU =
10h
00h
06h
No dummy
read
W
=
After Instruction
PC
TOS
=
=
001006h
address (HERE + 2)
Example:
MOVSF
[05h], REG2
PCLATH =
PCLATU =
10h
00h
06h
Before Instruction
FSR2
=
80h
33h
W
=
Contents
of 85h
REG2
=
=
11h
After Instruction
FSR2
=
80h
Contents
of 85h
REG2
=
=
33h
33h
© 2007 Microchip Technology Inc.
Advance Information
DS41303B-page 349
PIC18F2XK20/4XK20
MOVSS
Move Indexed to Indexed
PUSHL
Store Literal at FSR2, Decrement FSR2
Syntax:
MOVSS [z ], [z ]
Syntax:
PUSHL k
s
d
Operands:
0 ≤ z ≤ 127
s
Operands:
Operation:
0 ≤ k ≤ 255
0 ≤ z ≤ 127
d
k → (FSR2),
FSR2 – 1 → FSR2
Operation:
((FSR2) + z ) → ((FSR2) + z )
s d
Status Affected:
None
Status Affected: None
Encoding:
1st word (source)
2nd word (dest.)
Encoding:
1111
1010
kkkk
kkkk
1110
1111
1011
xxxx
1zzz
xzzz
zzzz
zzzz
s
d
Description:
The 8-bit literal ‘k’ is written to the data
memory address specified by FSR2. FSR2
is decremented by 1 after the operation.
This instruction allows users to push values
onto a software stack.
Description
The contents of the source register are
moved to the destination register. The
addresses of the source and destination
registers are determined by adding the
7-bit literal offsets ‘z ’ or ‘z ’,
Words:
Cycles:
1
1
s
d
respectively, to the value of FSR2. Both
registers can be located anywhere in
the 4096-byte data memory space
(000h to FFFh).
Q Cycle Activity:
Q1
Q2
Q3
Q4
The MOVSSinstruction cannot use the
PCL, TOSU, TOSH or TOSL as the
destination register.
Decode
Read ‘k’
Process
data
Write to
destination
If the resultant source address points to
an indirect addressing register, the
value returned will be 00h. If the
resultant destination address points to
an indirect addressing register, the
instruction will execute as a NOP.
Example:
PUSHL 08h
Before Instruction
FSR2H:FSR2L
Memory (01ECh)
=
=
01ECh
00h
Words:
2
2
After Instruction
FSR2H:FSR2L
Memory (01ECh)
=
=
01EBh
08h
Cycles:
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Determine
Determine
Read
source addr source addr source reg
Decode
Determine
dest addr
Determine
dest addr
Write
to dest reg
Example:
MOVSS [05h], [06h]
Before Instruction
FSR2
=
=
=
80h
33h
11h
Contents
of 85h
Contents
of 86h
After Instruction
FSR2
=
=
=
80h
33h
33h
Contents
of 85h
Contents
of 86h
DS41303B-page 350
Advance Information
© 2007 Microchip Technology Inc.
PIC18F2XK20/4XK20
SUBFSR
Subtract Literal from FSR
SUBULNK
Subtract Literal from FSR2 and Return
Syntax:
SUBFSR f, k
0 ≤ k ≤ 63
f ∈ [ 0, 1, 2 ]
FSR(f) – k → FSRf
None
Syntax:
SUBULNK k
Operands:
Operands:
Operation:
0 ≤ k ≤ 63
FSR2 – k → FSR2
(TOS) → PC
Operation:
Status Affected:
Encoding:
Status Affected: None
1110
1001
ffkk
kkkk
Encoding:
1110
1001
11kk
kkkk
Description:
The 6-bit literal ‘k’ is subtracted from
the contents of the FSR specified by
‘f’.
Description:
The 6-bit literal ‘k’ is subtracted from the
contents of the FSR2. A RETURNis then
executed by loading the PC with the TOS.
The instruction takes two cycles to
execute; a NOPis performed during the
second cycle.
This may be thought of as a special case of
the SUBFSRinstruction, where f = 3 (binary
‘11’); it operates only on FSR2.
Words:
1
1
Cycles:
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
register ‘f’
Process
Data
Write to
destination
Words:
1
2
Cycles:
Q Cycle Activity:
Q1
Example:
SUBFSR 2, 23h
03FFh
Q2
Q3
Q4
Before Instruction
FSR2
After Instruction
FSR2
Decode
Read
register ‘f’
Process
Data
Write to
destination
=
No
Operation
No
Operation
No
Operation
No
Operation
=
03DCh
Example:
SUBULNK 23h
Before Instruction
FSR2
PC
=
=
03FFh
0100h
After Instruction
FSR2
PC
=
=
03DCh
(TOS)
© 2007 Microchip Technology Inc.
Advance Information
DS41303B-page 351
PIC18F2XK20/4XK20
24.2.3
BYTE-ORIENTED AND
BIT-ORIENTED INSTRUCTIONS IN
INDEXED LITERAL OFFSET MODE
24.2.3.1
Extended Instruction Syntax with
Standard PIC18 Commands
When the extended instruction set is enabled, the file
register argument, ‘f’, in the standard byte-oriented and
bit-oriented commands is replaced with the literal offset
value, ‘k’. As already noted, this occurs only when ‘f’ is
less than or equal to 5Fh. When an offset value is used,
it must be indicated by square brackets (“[ ]”). As with
the extended instructions, the use of brackets indicates
to the compiler that the value is to be interpreted as an
index or an offset. Omitting the brackets, or using a
value greater than 5Fh within brackets, will generate an
error in the MPASM Assembler.
Note: Enabling the PIC18 instruction set
extension may cause legacy applications
to behave erratically or fail entirely.
In addition to eight new commands in the extended set,
enabling the extended instruction set also enables
Indexed Literal Offset Addressing mode (Section 5.5.1
“Indexed Addressing with Literal Offset”). This has
a significant impact on the way that many commands of
the standard PIC18 instruction set are interpreted.
When the extended set is disabled, addresses
embedded in opcodes are treated as literal memory
locations: either as a location in the Access Bank (‘a’ =
0), or in a GPR bank designated by the BSR (‘a’ = 1).
When the extended instruction set is enabled and ‘a’ =
0, however, a file register argument of 5Fh or less is
interpreted as an offset from the pointer value in FSR2
and not as a literal address. For practical purposes, this
means that all instructions that use the Access RAM bit
as an argument – that is, all byte-oriented and bit-
oriented instructions, or almost half of the core PIC18
instructions – may behave differently when the
extended instruction set is enabled.
If the index argument is properly bracketed for Indexed
Literal Offset Addressing, the Access RAM argument is
never specified; it will automatically be assumed to be
‘0’. This is in contrast to standard operation (extended
instruction set disabled) when ‘a’ is set on the basis of
the target address. Declaring the Access RAM bit in
this mode will also generate an error in the MPASM
Assembler.
The destination argument, ‘d’, functions as before.
In the latest versions of the MPASM™ assembler,
language support for the extended instruction set must
be explicitly invoked. This is done with either the
command line option, /y, or the PE directive in the
source listing.
When the content of FSR2 is 00h, the boundaries of the
Access RAM are essentially remapped to their original
values. This may be useful in creating backward
compatible code. If this technique is used, it may be
necessary to save the value of FSR2 and restore it
when moving back and forth between C and assembly
routines in order to preserve the Stack Pointer. Users
must also keep in mind the syntax requirements of the
extended instruction set (see Section 24.2.3.1
“Extended Instruction Syntax with Standard PIC18
Commands”).
24.2.4
CONSIDERATIONS WHEN
ENABLING THE EXTENDED
INSTRUCTION SET
It is important to note that the extensions to the instruc-
tion set may not be beneficial to all users. In particular,
users who are not writing code that uses a software
stack may not benefit from using the extensions to the
instruction set.
Although the Indexed Literal Offset Addressing mode
can be very useful for dynamic stack and pointer
manipulation, it can also be very annoying if a simple
arithmetic operation is carried out on the wrong
register. Users who are accustomed to the PIC18
programming must keep in mind that, when the
extended instruction set is enabled, register addresses
of 5Fh or less are used for Indexed Literal Offset
Addressing.
Additionally, the Indexed Literal Offset Addressing
mode may create issues with legacy applications
written to the PIC18 assembler. This is because
instructions in the legacy code may attempt to address
registers in the Access Bank below 5Fh. Since these
addresses are interpreted as literal offsets to FSR2
when the instruction set extension is enabled, the
application may read or write to the wrong data
addresses.
Representative examples of typical byte-oriented and
bit-oriented instructions in the Indexed Literal Offset
Addressing mode are provided on the following page to
show how execution is affected. The operand condi-
tions shown in the examples are applicable to all
instructions of these types.
When porting an application to the PIC18F2XK20/
4XK20, it is very important to consider the type of code.
A large, re-entrant application that is written in ‘C’ and
would benefit from efficient compilation will do well
when using the instruction set extensions. Legacy
applications that heavily use the Access Bank will most
likely not benefit from using the extended instruction
set.
DS41303B-page 352
Advance Information
© 2007 Microchip Technology Inc.
PIC18F2XK20/4XK20
ADD W to Indexed
(Indexed Literal Offset mode)
Bit Set Indexed
BSF
ADDWF
(Indexed Literal Offset mode)
Syntax:
ADDWF
[k] {,d}
Syntax:
BSF [k], b
Operands:
0 ≤ k ≤ 95
d ∈ [0,1]
Operands:
0 ≤ f ≤ 95
0 ≤ b ≤ 7
Operation:
(W) + ((FSR2) + k) → dest
Operation:
1 → ((FSR2) + k)<b>
Status Affected:
Encoding:
N, OV, C, DC, Z
Status Affected:
Encoding:
None
0010
01d0
kkkk
kkkk
1000
bbb0
kkkk
kkkk
Description:
The contents of W are added to the
contents of the register indicated by
FSR2, offset by the value ‘k’.
If ‘d’ is ‘0’, the result is stored in W. If ‘d’
is ‘1’, the result is stored back in
register ‘f’ (default).
Description:
Bit ‘b’ of the register indicated by FSR2,
offset by the value ‘k’, is set.
Words:
1
1
Cycles:
Q Cycle Activity:
Q1
Words:
Cycles:
1
1
Q2
Q3
Q4
Decode
Read
register ‘f’
Process
Data
Write to
destination
Q Cycle Activity:
Q1
Q2
Q3
Q4
Example:
BSF
[FLAG_OFST], 7
Decode
Read ‘k’
Process
Data
Write to
destination
Before Instruction
FLAG_OFST
FSR2
Contents
of 0A0Ah
=
=
0Ah
0A00h
Example:
ADDWF
[OFST], 0
=
55h
D5h
Before Instruction
After Instruction
W
OFST
FSR2
=
=
=
17h
2Ch
0A00h
Contents
of 0A0Ah
=
Contents
of 0A2Ch
=
20h
After Instruction
W
=
=
37h
20h
Set Indexed
(Indexed Literal Offset mode)
Contents
of 0A2Ch
SETF
Syntax:
SETF [k]
Operands:
Operation:
Status Affected:
Encoding:
Description:
0 ≤ k ≤ 95
FFh → ((FSR2) + k)
None
0110
1000
kkkk
kkkk
The contents of the register indicated by
FSR2, offset by ‘k’, are set to FFh.
Words:
Cycles:
1
1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read ‘k’
Process
Data
Write
register
Example:
SETF
[OFST]
2Ch
Before Instruction
OFST
=
=
FSR2
0A00h
Contents
of 0A2Ch
=
00h
After Instruction
Contents
of 0A2Ch
=
FFh
© 2007 Microchip Technology Inc.
Advance Information
DS41303B-page 353
PIC18F2XK20/4XK20
24.2.5
SPECIAL CONSIDERATIONS WITH
MICROCHIP MPLAB® IDE TOOLS
The latest versions of Microchip’s software tools have
been designed to fully support the extended instruction
set of the PIC18F2XK20/4XK20 family of devices. This
includes the MPLAB C18
assembly language and
Development Environment (IDE).
C
compiler, MPASM
MPLAB Integrated
When selecting target device for software
a
development, MPLAB IDE will automatically set default
Configuration bits for that device. The default setting for
the XINST Configuration bit is ‘0’, disabling the
extended instruction set and Indexed Literal Offset
Addressing mode. For proper execution of applications
developed to take advantage of the extended
instruction set, XINST must be set during
programming.
To develop software for the extended instruction set,
the user must enable support for the instructions and
the Indexed Addressing mode in their language tool(s).
Depending on the environment being used, this may be
done in several ways:
• A menu option, or dialog box within the
environment, that allows the user to configure the
language tool and its settings for the project
• A command line option
• A directive in the source code
These options vary between different compilers,
assemblers and development environments. Users are
encouraged to review the documentation accompanying
their development systems for the appropriate
information.
DS41303B-page 354
Advance Information
© 2007 Microchip Technology Inc.
PIC18F2XK20/4XK20
25.1 MPLAB Integrated Development
Environment Software
25.0 DEVELOPMENT SUPPORT
The PIC® microcontrollers are supported with a full
range of hardware and software development tools:
The MPLAB IDE software brings an ease of software
development previously unseen in the 8/16-bit micro-
controller market. The MPLAB IDE is a Windows®
operating system-based application that contains:
• Integrated Development Environment
- MPLAB® IDE Software
• Assemblers/Compilers/Linkers
- MPASMTM Assembler
• A single graphical interface to all debugging tools
- Simulator
- MPLAB C18 and MPLAB C30 C Compilers
- MPLINKTM Object Linker/
MPLIBTM Object Librarian
- Programmer (sold separately)
- Emulator (sold separately)
- In-Circuit Debugger (sold separately)
• A full-featured editor with color-coded context
• A multiple project manager
- MPLAB ASM30 Assembler/Linker/Library
• Simulators
- MPLAB SIM Software Simulator
• Emulators
• Customizable data windows with direct edit of
contents
- MPLAB ICE 2000 In-Circuit Emulator
- MPLAB REAL ICE™ In-Circuit Emulator
• In-Circuit Debugger
• High-level source code debugging
• Visual device initializer for easy register
initialization
- MPLAB ICD 2
• Mouse over variable inspection
• Device Programmers
• Drag and drop variables from source to watch
windows
- PICSTART® Plus Development Programmer
- MPLAB PM3 Device Programmer
- PICkit™ 2 Development Programmer
• Extensive on-line help
• Integration of select third party tools, such as
HI-TECH Software C Compilers and IAR
C Compilers
• Low-Cost Demonstration and Development
Boards and Evaluation Kits
The MPLAB IDE allows you to:
• Edit your source files (either assembly or C)
• One touch assemble (or compile) and download
to PIC MCU emulator and simulator tools
(automatically updates all project information)
• Debug using:
- Source files (assembly or C)
- Mixed assembly and C
- Machine code
MPLAB IDE supports multiple debugging tools in a
single development paradigm, from the cost-effective
simulators, through low-cost in-circuit debuggers, to
full-featured emulators. This eliminates the learning
curve when upgrading to tools with increased flexibility
and power.
© 2007 Microchip Technology Inc.
Advance Information
DS41303B-page 355
PIC18F2XK20/4XK20
25.2 MPASM Assembler
25.5 MPLAB ASM30 Assembler, Linker
and Librarian
The MPASM Assembler is a full-featured, universal
macro assembler for all PIC MCUs.
MPLAB ASM30 Assembler produces relocatable
machine code from symbolic assembly language for
dsPIC30F devices. MPLAB C30 C Compiler uses the
assembler to produce its object file. The assembler
generates relocatable object files that can then be
archived or linked with other relocatable object files and
archives to create an executable file. Notable features
of the assembler include:
The MPASM Assembler generates relocatable object
files for the MPLINK Object Linker, Intel® standard HEX
files, MAP files to detail memory usage and symbol
reference, absolute LST files that contain source lines
and generated machine code and COFF files for
debugging.
The MPASM Assembler features include:
• Integration into MPLAB IDE projects
• Support for the entire dsPIC30F instruction set
• Support for fixed-point and floating-point data
• Command line interface
• User-defined macros to streamline
assembly code
• Rich directive set
• Conditional assembly for multi-purpose
source files
• Flexible macro language
• MPLAB IDE compatibility
• Directives that allow complete control over the
assembly process
25.6 MPLAB SIM Software Simulator
25.3 MPLAB C18 and MPLAB C30
C Compilers
The MPLAB SIM Software Simulator allows code
development in a PC-hosted environment by simulat-
ing the PIC MCUs and dsPIC® DSCs on an instruction
level. On any given instruction, the data areas can be
examined or modified and stimuli can be applied from
a comprehensive stimulus controller. Registers can be
logged to files for further run-time analysis. The trace
buffer and logic analyzer display extend the power of
the simulator to record and track program execution,
actions on I/O, most peripherals and internal registers.
The MPLAB C18 and MPLAB C30 Code Development
Systems are complete ANSI
C
compilers for
Microchip’s PIC18 and PIC24 families of microcontrol-
lers and the dsPIC30 and dsPIC33 family of digital sig-
nal controllers. These compilers provide powerful
integration capabilities, superior code optimization and
ease of use not found with other compilers.
For easy source level debugging, the compilers provide
symbol information that is optimized to the MPLAB IDE
debugger.
The MPLAB SIM Software Simulator fully supports
symbolic debugging using the MPLAB C18 and
MPLAB C30 C Compilers, and the MPASM and
MPLAB ASM30 Assemblers. The software simulator
offers the flexibility to develop and debug code outside
of the hardware laboratory environment, making it an
excellent, economical software development tool.
25.4 MPLINK Object Linker/
MPLIB Object Librarian
The MPLINK Object Linker combines relocatable
objects created by the MPASM Assembler and the
MPLAB C18 C Compiler. It can link relocatable objects
from precompiled libraries, using directives from a
linker script.
The MPLIB Object Librarian manages the creation and
modification of library files of precompiled code. When
a routine from a library is called from a source file, only
the modules that contain that routine will be linked in
with the application. This allows large libraries to be
used efficiently in many different applications.
The object linker/library features include:
• Efficient linking of single libraries instead of many
smaller files
• Enhanced code maintainability by grouping
related modules together
• Flexible creation of libraries with easy module
listing, replacement, deletion and extraction
DS41303B-page 356
Advance Information
© 2007 Microchip Technology Inc.
PIC18F2XK20/4XK20
25.7 MPLAB ICE 2000
High-Performance
25.9 MPLAB ICD 2 In-Circuit Debugger
Microchip’s In-Circuit Debugger, MPLAB ICD 2, is a
powerful, low-cost, run-time development tool,
connecting to the host PC via an RS-232 or high-speed
USB interface. This tool is based on the Flash PIC
MCUs and can be used to develop for these and other
PIC MCUs and dsPIC DSCs. The MPLAB ICD 2 utilizes
the in-circuit debugging capability built into the Flash
devices. This feature, along with Microchip’s In-Circuit
Serial ProgrammingTM (ICSPTM) protocol, offers cost-
effective, in-circuit Flash debugging from the graphical
user interface of the MPLAB Integrated Development
Environment. This enables a designer to develop and
debug source code by setting breakpoints, single step-
ping and watching variables, and CPU status and
peripheral registers. Running at full speed enables
testing hardware and applications in real time. MPLAB
ICD 2 also serves as a development programmer for
selected PIC devices.
In-Circuit Emulator
The MPLAB ICE 2000 In-Circuit Emulator is intended
to provide the product development engineer with a
complete microcontroller design tool set for PIC
microcontrollers. Software control of the MPLAB ICE
2000 In-Circuit Emulator is advanced by the MPLAB
Integrated Development Environment, which allows
editing, building, downloading and source debugging
from a single environment.
The MPLAB ICE 2000 is a full-featured emulator
system with enhanced trace, trigger and data monitor-
ing features. Interchangeable processor modules allow
the system to be easily reconfigured for emulation of
different processors. The architecture of the MPLAB
ICE 2000 In-Circuit Emulator allows expansion to
support new PIC microcontrollers.
The MPLAB ICE 2000 In-Circuit Emulator system has
been designed as a real-time emulation system with
advanced features that are typically found on more
expensive development tools. The PC platform and
Microsoft® Windows® 32-bit operating system were
chosen to best make these features available in a
simple, unified application.
25.10 MPLAB PM3 Device Programmer
The MPLAB PM3 Device Programmer is a universal,
CE compliant device programmer with programmable
voltage verification at VDDMIN and VDDMAX for
maximum reliability. It features a large LCD display
(128 x 64) for menus and error messages and a modu-
lar, detachable socket assembly to support various
package types. The ICSP™ cable assembly is included
as a standard item. In Stand-Alone mode, the MPLAB
PM3 Device Programmer can read, verify and program
PIC devices without a PC connection. It can also set
code protection in this mode. The MPLAB PM3
connects to the host PC via an RS-232 or USB cable.
The MPLAB PM3 has high-speed communications and
optimized algorithms for quick programming of large
memory devices and incorporates an SD/MMC card for
file storage and secure data applications.
25.8 MPLAB REAL ICE In-Circuit
Emulator System
MPLAB REAL ICE In-Circuit Emulator System is
Microchip’s next generation high-speed emulator for
Microchip Flash DSC® and MCU devices. It debugs and
programs PIC® and dsPIC® Flash microcontrollers with
the easy-to-use, powerful graphical user interface of the
MPLAB Integrated Development Environment (IDE),
included with each kit.
The MPLAB REAL ICE probe is connected to the design
engineer’s PC using a high-speed USB 2.0 interface and
is connected to the target with either a connector
compatible with the popular MPLAB ICD 2 system
(RJ11) or with the new high speed, noise tolerant, low-
voltage differential signal (LVDS) interconnection
(CAT5).
MPLAB REAL ICE is field upgradeable through future
firmware downloads in MPLAB IDE. In upcoming
releases of MPLAB IDE, new devices will be supported,
and new features will be added, such as software break-
points and assembly code trace. MPLAB REAL ICE
offers significant advantages over competitive emulators
including low-cost, full-speed emulation, real-time
variable watches, trace analysis, complex breakpoints, a
ruggedized probe interface and long (up to three meters)
interconnection cables.
© 2007 Microchip Technology Inc.
Advance Information
DS41303B-page 357
PIC18F2XK20/4XK20
25.11 PICSTART Plus Development
Programmer
25.13 Demonstration, Development and
Evaluation Boards
The PICSTART Plus Development Programmer is an
easy-to-use, low-cost, prototype programmer. It
connects to the PC via a COM (RS-232) port. MPLAB
Integrated Development Environment software makes
using the programmer simple and efficient. The
PICSTART Plus Development Programmer supports
most PIC devices in DIP packages up to 40 pins.
Larger pin count devices, such as the PIC16C92X and
PIC17C76X, may be supported with an adapter socket.
The PICSTART Plus Development Programmer is CE
compliant.
A wide variety of demonstration, development and
evaluation boards for various PIC MCUs and dsPIC
DSCs allows quick application development on fully func-
tional systems. Most boards include prototyping areas for
adding custom circuitry and provide application firmware
and source code for examination and modification.
The boards support a variety of features, including LEDs,
temperature sensors, switches, speakers, RS-232
interfaces, LCD displays, potentiometers and additional
EEPROM memory.
The demonstration and development boards can be
used in teaching environments, for prototyping custom
circuits and for learning about various microcontroller
applications.
25.12 PICkit 2 Development Programmer
The PICkit™ 2 Development Programmer is a low-cost
programmer and selected Flash device debugger with
an easy-to-use interface for programming many of
Microchip’s baseline, mid-range and PIC18F families of
Flash memory microcontrollers. The PICkit 2 Starter Kit
includes a prototyping development board, twelve
sequential lessons, software and HI-TECH’s PICC™
Lite C compiler, and is designed to help get up to speed
quickly using PIC® microcontrollers. The kit provides
everything needed to program, evaluate and develop
applications using Microchip’s powerful, mid-range
Flash memory family of microcontrollers.
In addition to the PICDEM™ and dsPICDEM™ demon-
stration/development board series of circuits, Microchip
has a line of evaluation kits and demonstration software
®
for analog filter design, KEELOQ security ICs, CAN,
IrDA®, PowerSmart® battery management, SEEVAL®
evaluation system, Sigma-Delta ADC, flow rate
sensing, plus many more.
Check the Microchip web page (www.microchip.com)
and the latest “Product Selector Guide” (DS00148) for
the complete list of demonstration, development and
evaluation kits.
DS41303B-page 358
Advance Information
© 2007 Microchip Technology Inc.
PIC18F2XK20/4XK20
26.0 ELECTRICAL CHARACTERISTICS
(†)
Absolute Maximum Ratings
Ambient temperature under bias.............................................................................................................-40°C to +125°C
Storage temperature .............................................................................................................................. -65°C to +150°C
Voltage on any pin with respect to VSS (except VDD, and MCLR) .................................................. -0.3V to (VDD + 0.3V)
Voltage on VDD with respect to VSS ......................................................................................................... -0.3V to +5.0V
Voltage on MCLR with respect to VSS (Note 2) ......................................................................................... 0V to +13.25V
Total power dissipation (Note 1) ...............................................................................................................................1.0W
Maximum current out of VSS pin ...........................................................................................................................300 mA
Maximum current into VDD pin ..............................................................................................................................250 mA
Input clamp current, IIK (VI < 0 or VI > VDD)...................................................................................................................... 20 mA
Output clamp current, IOK (VO < 0 or VO > VDD) .............................................................................................................. 20 mA
Maximum output current sunk by any I/O pin..........................................................................................................25 mA
Maximum output current sourced by any I/O pin ....................................................................................................25 mA
Maximum current sunk by all ports .......................................................................................................................200 mA
Maximum current sourced by all ports ..................................................................................................................200 mA
Note 1: Power dissipation is calculated as follows:
Pdis = VDD x {IDD – ∑ IOH} + ∑ {(VDD – VOH) x IOH} + ∑(VOL x IOL)
2: Voltage spikes below VSS at the MCLR/VPP/RE3 pin, inducing currents greater than 80 mA, may cause
latch-up. Thus, a series resistor of 50-100Ω should be used when applying a “low” level to the
MCLR/VPP/RE3 pin, rather than pulling this pin directly to VSS.
† NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at those or any other conditions above those
indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for
extended periods may affect device reliability.
© 2007 Microchip Technology Inc.
Advance Information
DS41303B-page 359
PIC18F2XK20/4XK20
FIGURE 26-1:
PIC18F2XK20/4XK20 VOLTAGE-FREQUENCY GRAPH
3.5V
3.0V
2.7V
2.2V
1.8V
10
20
30 32
40
50
60 64
Frequency (MHz)
DS41303B-page 360
Advance Information
© 2007 Microchip Technology Inc.
PIC18F2XK20/4XK20
26.1 DC Characteristics:Supply Voltage, PIC18F2XK20/4XK20
Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C ≤ TA ≤ +125°C
PIC18F2XK20/4XK20
Param
Symbol
No.
Characteristic
Min
Typ
Max Units
Conditions
D001 VDD
D002 VDR
Supply Voltage
1.8
1.5
—
—
3.6
—
V
V
RAM Data Retention
Voltage(1)
D003 VPOR
D004 SVDD
D005 VBOR
VDD Start Voltage
to ensure internal
Power-on Reset signal
—
—
—
0.7
—
V
See section on Power-on Reset for details
VDD Rise Rate
to ensure internal
Power-on Reset signal
0.05
V/ms See section on Power-on Reset for details
Brown-out Reset Voltage
BORV<1:0> = 11
BORV<1:0> = 10
BORV<1:0> = 01
BORV<1:0> = 00
1.8
—
—
—
—
—
V
V
V
V
—
—
—
2.3
2.8
3.1
Note 1: This is the limit to which VDD can be lowered in Sleep mode, or during a device Reset, without losing RAM
data.
26.2 DC Characteristics: Power-Down Current, PIC18F2XK20/4XK20
Standard Operating Conditions (unless otherwise stated)
PIC18F2XK20/4XK20
Operating temperature
-40°C ≤ TA ≤ +125°C
Param
No.
Device Characteristics
Typ Max Units
Conditions
D006
D007
Power-down Current (IPD)(1) 0.1
—
—
—
—
—
—
—
—
nA
μA
μA
μA
μA
μA
μA
μA
-40°C
+25°C
+85°C
+125°C
-40°C
0.5
2
VDD = 1.8V, (Sleep mode)
VDD = 3.0V, (Sleep mode)
10
0.1
0.5
2
+25°C
+85°C
+125°C
10
Note 1: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is
measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS and
all features that add delta current disabled (such as WDT, Timer1 Oscillator, BOR, etc.).
© 2007 Microchip Technology Inc.
Advance Information
DS41303B-page 361
PIC18F2XK20/4XK20
26.3 DC Characteristics: RC Run Supply Current, PIC18F2XK20/4XK20
Standard Operating Conditions (unless otherwise stated)
PIC18F2XK20/4XK20
Operating temperature
-40°C ≤ TA ≤ +125°C
Param
No.
Device Characteristics
Supply Current (IDD)(1, 2)
Typ Max Units
Conditions
D008
7
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
μA
μA
μA
μA
μA
μA
μA
μA
-40°C
+25°C
+85°C
+125°C
-40°C
8
VDD = 1.8V
VDD = 3.0V
12
32
14
15
21
48
0.5
0.5
0.8
0.8
2.7
2.7
5.2
5.2
FOSC = 31 kHz
(RC_RUN mode,
LFINTOSC source)
D008A
+25°C
+85°C
+125°C
D009
D009A
D010
mA -40°C TO +85°C
mA -40°C to +125°C
mA -40°C TO +85°C
mA -40°C to +125°C
VDD = 1.8V
VDD = 3.0V
VDD = 1.8V
FOSC = 1 MHz
(RC_RUN mode,
HF-INTOSC source)
-40°C TO +85°C
-40°C to +125°C
-40°C TO +85°C
-40°C to +125°C
mA
mA
mA
mA
FOSC = 16 MHz
(RC_RUN mode,
HF-INTOSC source)
D010A
VDD = 3.0V
Note 1: The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as
I/O pin loading and switching rate, oscillator type and circuit, internal code execution pattern and tempera-
ture, also have an impact on the current consumption.
The test conditions for all IDD measurements in active operation mode are:
OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD;
MCLR = VDD; WDT enabled/disabled as specified.
2: For RC oscillator configurations, current through REXT is not included. The current through the resistor can
be estimated by the formula Ir = VDD/2REXT (mA) with REXT in kΩ.
DS41303B-page 362
Advance Information
© 2007 Microchip Technology Inc.
PIC18F2XK20/4XK20
26.4 DC Characteristics: RC Idle Supply Current, PIC18F2XK20/4XK20
Standard Operating Conditions (unless otherwise stated)
PIC18F2XK20/4XK20
Operating temperature
-40°C ≤ TA ≤ +125°C
Param
No.
Device Characteristics
Typ Max Units
Conditions
Supply Current (IDD)(1, 2)
D011
3.0
4.5
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
μA
μA
μA
μA
μA
μA
μA
μA
μA
μA
μA
μA
mA
mA
mA
mA
-40°C
+25°C
VDD = 1.8V
VDD = 3.0V
9.0
+85°C
FOSC = 31 kHz
(RC_IDLE mode,
LFINTOSC source)
TBD
3.0
+125°C
D011A
-40°C
4.5
+25°C
9.0
+85°C
TBD
250
250
400
400
1.0
+125°C
D012
-40°C to +85°C
-40°C to +125°C
-40°C to +85°C
-40°C to +125°C
-40°C to +85°C
-40°C to +125°C
-40°C to +85°C
-40°C to +125°C
VDD = 1.8V
VDD = 3.0V
VDD = 1.8V
VDD = 3.0V
FOSC = 1 MHz
(RC_IDLE mode,
HF-INTOSC source)
D012A
D013
FOSC = 16 MHz
(RC_IDLE mode,
HF-INTOSC source)
1.0
D013A
2.0
2.0
Legend: TBD = To Be Determined.
Note 1: The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as
I/O pin loading and switching rate, oscillator type and circuit, internal code execution pattern and tempera-
ture, also have an impact on the current consumption.
The test conditions for all IDD measurements in active operation mode are:
OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD;
MCLR = VDD; WDT enabled/disabled as specified.
2: For RC oscillator configurations, current through REXT is not included. The current through the resistor can
be estimated by the formula Ir = VDD/2REXT (mA) with REXT in kΩ.
© 2007 Microchip Technology Inc.
Advance Information
DS41303B-page 363
PIC18F2XK20/4XK20
26.5 DC Characteristics: Primary Run Supply Current, PIC18F2XK20/4XK20
Standard Operating Conditions (unless otherwise stated)
PIC18F2XK20/4XK20
Operating temperature
Typ Max Units
—
-40°C ≤ TA ≤ +125°C
Param
No.
Device Characteristics
Supply Current (IDD)(1, 2)
Conditions
D012
-40°C to +85°C
-40°C to +125°C
-40°C to +85°C
-40°C to +125°C
-40°C to +85°C
-40°C to +125°C
-40°C to +85°C
-40°C to +125°C
-40°C to +85°C
-40°C to +125°C
-40°C to +85°C
-40°C to +125°C
-40°C to +85°C
-40°C to +125°C
-40°C to +85°C
-40°C to +125°C
-40°C to +85°C
-40°C to +125°C
-40°C to +85°C
-40°C to +125°C
0.5
0.5
0.8
0.8
3.0
3.0
6.5
6.5
14
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
VDD = 1.8V
VDD = 3.0V
VDD = 1.8V
VDD = 3.0V
VDD = 1.8V
VDD = 3.0V
VDD = 1.8V
VDD = 3.0V
VDD = 1.8V
VDD = 3.0V
FOSC = 1 MHz
(PRI_RUN,
EC oscillator)
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
D012A
D013
FOSC = 20 MHz
(PRI_RUN,
EC oscillator)
D013A
D014
FOSC = 64 MHz
(PRI_RUN,
EC oscillator)
14
D014A
D015
18
18
2.7
2.7
5.2
5.2
14
FOSC = 4 MHz
16 MHz Internal
(PRI_RUN HS+PLL)
D015A
D016
FOSC = 16 MHz
64 MHz Internal
(PRI_RUN HS+PLL)
14
D016A
18
18
Note 1: The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as
I/O pin loading and switching rate, oscillator type and circuit, internal code execution pattern and tempera-
ture, also have an impact on the current consumption.
The test conditions for all IDD measurements in active operation mode are:
OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD;
MCLR = VDD; WDT enabled/disabled as specified.
2: For RC oscillator configurations, current through REXT is not included. The current through the resistor can
be estimated by the formula Ir = VDD/2REXT (mA) with REXT in kΩ.
DS41303B-page 364
Advance Information
© 2007 Microchip Technology Inc.
PIC18F2XK20/4XK20
26.6 DC Characteristics: Primary Idle Supply Current, PIC18F2XK20/4XK20
Standard Operating Conditions (unless otherwise stated)
PIC18F2XK20/4XK20
Operating temperature
Typ Max Units
—
-40°C ≤ TA ≤ +125°C
Param
No.
Device Characteristics
Conditions
Supply Current (IDD)(1, 2)
250
250
400
400
1.0
μA
μA
D017
-40°C to +85°C
-40°C to +125°C
-40°C to +85°C
-40°C to +125°C
-40°C to +85°C
-40°C to +125°C
-40°C to +85°C
-40°C to +125°C
-40°C to +85°C
-40°C to +125°C
-40°C to +85°C
-40°C to +125°C
VDD = 1.8V
VDD = 3.0V
VDD = 1.8V
VDD = 3.0V
VDD = 1.8V
VDD = 3.0V
FOSC = 1 MHz
(PRI_IDLE mode,
EC oscillator)
—
—
—
—
—
—
—
—
—
—
—
D017A
D018
μA
μA
mA
mA
mA
mA
mA
mA
mA
mA
FOSC = 20 MHz
(PRI_IDLEmode,
EC oscillator)
1.0
D018A
D019
2.0
2.0
TBD
TBD
TBD
TBD
FOSC = 64 MHz
(PRI_IDLEmode,
EC oscillator)
D019A
Legend: TBD = To Be Determined.
Note 1: The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as
I/O pin loading and switching rate, oscillator type and circuit, internal code execution pattern and tempera-
ture, also have an impact on the current consumption.
The test conditions for all IDD measurements in active operation mode are:
OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD;
MCLR = VDD; WDT enabled/disabled as specified.
2: For RC oscillator configurations, current through REXT is not included. The current through the resistor can
be estimated by the formula Ir = VDD/2REXT (mA) with REXT in kΩ.
© 2007 Microchip Technology Inc.
Advance Information
DS41303B-page 365
PIC18F2XK20/4XK20
26.7 DC Characteristics: Secondary Oscillator Supply Current, PIC18F2XK20/4XK20
Standard Operating Conditions (unless otherwise stated)
PIC18F2XK20/4XK20
Operating temperature
-40°C ≤ TA ≤ +125°C
Param
No.
Device Characteristics
Supply Current (IDD)(1, 2)
Typ Max Units
Conditions
D020
7
—
—
—
—
—
—
—
—
—
—
—
—
μA
μA
μA
μA
μA
μA
μA
μA
μA
μA
μA
μA
-40°C
+25°C
+85°C
-40°C
+25°C
+85°C
-40°C
+25°C
+85°C
-40°C
+25°C
+85°C
8
VDD = 1.8V
VDD = 3.0V
VDD = 1.8V
VDD = 3.0V
FOSC = 32 kHz(3)
(SEC_RUN mode,
Timer1 as clock)
14
14
15
24
1.0
1.5
3.5
1.0
1.5
3.5
D020A
D021
FOSC = 32 kHz(3)
(SEC_IDLE mode,
Timer1 as clock)
D021A
Note 1: The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as
I/O pin loading and switching rate, oscillator type and circuit, internal code execution pattern and tempera-
ture, also have an impact on the current consumption.
The test conditions for all IDD measurements in active operation mode are:
OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD;
MCLR = VDD; WDT enabled/disabled as specified.
2: For RC oscillator configurations, current through REXT is not included. The current through the resistor can
be estimated by the formula Ir = VDD/2REXT (mA) with REXT in kΩ.
3: Low-Power mode on T1 osc.
DS41303B-page 366
Advance Information
© 2007 Microchip Technology Inc.
PIC18F2XK20/4XK20
26.8 DC Characteristics: Peripheral Supply Current, PIC18F2XK20/4XK20
Standard Operating Conditions (unless otherwise stated)
PIC18F2XK20/4XK20
Operating temperature
-40°C ≤ TA ≤ +125°C
Param
No.
Device Characteristics
Typ Max Units
Conditions
Module Differential Currents (ΔIWDT, ΔIBOR, ΔIHLVD, ΔIOSCB, ΔIAD)
D022
(ΔIWDT)
Watchdog Timer 1.5
—
—
—
—
—
—
—
—
—
μA
μA
μA
μA
μA
μA
μA
μA
-40°C
+25°C
1.5
2.0
2.0
3.0
VDD = 1.8V
VDD = 3.0V
+85°C
-40°C
+25°C
3.0
+85°C
(2)
D022A
(ΔIBOR)
Brown-out Reset
40
45
-40°C to +85°C
-40°C to +85°C
VDD = 2.7V
VDD = 3.3V
Sleep mode,
BOREN<1:0> = 10
0
μA
-40°C to +85°C
VDD = 3.3V
(2)
D022B
(ΔIHLVD)
High/Low-Voltage Detect
TBD
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
μA
μA
μA
μA
μA
μA
μA
μA
μA
μA
μA
μA
μA
μA
μA
μA
μA
-40°C to +85°C
-40°C to +85°C
-40°C
VDD = 1.8V
VDD = 3.3V
TBD
1
D025
(ΔIOSCB)
Timer1 Oscillator
(1)
1
+25°C
VDD = 1.8V
VDD = 3.0V
VDD = 1.8V
VDD = 3.0V
32 kHz on Timer1
1
+85°C
1
-40°C
(1)
1
+25°C
32 kHz on Timer1
1
+85°C
D025A
(ΔIOSCB)
Timer1 Oscillator
5
-40°C
(3)
5
+25°C
32 kHz on Timer1
5
+85°C
5
-40°C
(3)
5
+25°C
32 kHz on Timer1
5
+85°C
D026
(ΔIAD)
A/D Converter TBD
TBD
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
VDD = 1.8V
VDD = 3.0V
VDD = 1.8V
VDD = 3.0V
VDD = 1.8V
VDD = 3.0V
A/D on, not converting
Comparators TBD
D027
(ΔICOMP)
D028
CVREF TBD
—
μA
-40°C to +85°C
(ΔICVREF)
Legend: TBD = To Be Determined.
Note 1: Low-Power mode on T1 osc.
2: BOR and HLVD enable internal band gap reference. With both modules enabled, current consumption will be
less than the sum of both specifications.
3: High-Power mode in T1 osc.
© 2007 Microchip Technology Inc.
Advance Information
DS41303B-page 367
PIC18F2XK20/4XK20
26.9 DC Characteristics: Input/Output Characteristics, PIC18F2XK20/4XK20
Standard Operating Conditions (unless otherwise stated)
DC CHARACTERISTICS
Operating temperature -40°C ≤ TA ≤ +125°C
Param
No.
Symbol
Characteristic
Min
Max
Units
Conditions
VIL
Input Low Voltage
I/O ports:
with TTL buffer
D030
D031
VSS
0.15 VDD
V
with Schmitt Trigger buffer
RC3 and RC4
VSS
VSS
0.2 VDD
0.3 VDD
V
V
D032
D033
MCLR
VSS
VSS
0.2 VDD
0.3 VDD
V
V
OSC1
HS, HSPLL modes
D033A
D033B
D034
OSC1
OSC1
T13CKI
VSS
VSS
VSS
0.2 VDD
0.3 VDD
0.3 VDD
V
V
V
RC, EC modes(1)
XT, LP modes
VIH
Input High Voltage
I/O ports:
D040
D041
with TTL buffer
0.25 VDD + 0.8V
VDD
V
with Schmitt Trigger buffer
RC3 and RC4
0.8 VDD
0.7 VDD
VDD
VDD
V
V
D042
D043
MCLR
OSC1
0.8 VDD
0.7 VDD
VDD
VDD
V
V
HS, HSPLL modes
D043A
D043B
D043C
D044
OSC1
OSC1
OSC1
T13CKI
0.8 VDD
0.9 VDD
1.6
VDD
VDD
VDD
VDD
V
V
V
V
EC mode
RC mode(1)
XT, LP modes
1.6
IIL
Input Leakage Current(2,3)
D060
I/O ports
—
1
μA VSS ≤ VPIN ≤ VDD,
Pin at high-impedance
D061
D063
MCLR
—
—
5
5
μA Vss ≤ VPIN ≤ VDD
μA Vss ≤ VPIN ≤ VDD
OSC1
IPU
Weak Pull-up Current
PORTB weak pull-up current
D070
IPURB
50
400
μA VDD = 3.0V, VPIN = VSS
Note 1: In RC oscillator configuration, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended that
the PIC® device be driven with an external clock while in RC mode.
2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified
levels represent normal operating conditions. Higher leakage current may be measured at different input
voltages.
3: Negative current is defined as current sourced by the pin.
4: Parameter is characterized but not tested.
DS41303B-page 368
Advance Information
© 2007 Microchip Technology Inc.
PIC18F2XK20/4XK20
26.9 DC Characteristics: Input/Output Characteristics, PIC18F2XK20/4XK20 (Continued)
Standard Operating Conditions (unless otherwise stated)
DC CHARACTERISTICS
Operating temperature -40°C ≤ TA ≤ +125°C
Param
No.
Symbol
Characteristic
Output Low Voltage
Min
Max
Units
Conditions
VOL
D080
D083
I/O ports
—
—
0.6
0.6
V
V
IOL = 8.5 mA, VDD = 3.0V,
-40°C to +85°C
OSC2/CLKOUT
IOL = 1.6 mA, VDD = 3.0V,
(RC, RCIO, EC, ECIO modes)
-40°C to +85°C
VOH
Output High Voltage(3)
D090
D092
I/O ports
VDD – 0.7
VDD – 0.7
—
—
V
V
IOH = -3.0 mA, VDD = 3.0V,
-40°C to +85°C
OSC2/CLKOUT
IOH = -1.3 mA, VDD = 3.0V,
(RC, RCIO, EC, ECIO modes)
-40°C to +85°C
Capacitive Loading Specs
on Output Pins
D100(4)
—
COSC2 OSC2 pin
15
pF In XT, HS and LP modes
when external clock is
used to drive OSC1
D101
D102
CIO
CB
All I/O pins and OSC2
(in RC mode)
—
—
50
pF To meet the AC Timing
Specifications
pF I2C™ Specification
SCL, SDA
400
Note 1: In RC oscillator configuration, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended that
the PIC® device be driven with an external clock while in RC mode.
2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified
levels represent normal operating conditions. Higher leakage current may be measured at different input
voltages.
3: Negative current is defined as current sourced by the pin.
4: Parameter is characterized but not tested.
© 2007 Microchip Technology Inc.
Advance Information
DS41303B-page 369
PIC18F2XK20/4XK20
26.10 Memory Programming Requirements
Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C ≤ TA ≤ +125°C
DC CHARACTERISTICS
Param
Sym
No.
Characteristic
Min
Typ†
Max
Units
Conditions
Internal Program Memory
Programming Specifications(1)
D110
D113
VPP
Voltage on MCLR/VPP/RE3 pin
9.00
—
—
—
13.25
10
V
(Note 3)
IDDP
Supply Current during
Programming
mA
Data EEPROM Memory
D120
ED
Byte Endurance
—
1.8
—
100K
—
—
3.6
—
E/W -40°C to +125°C
D121 VDRW VDD for Read/Write
D122 TDEW Erase/Write Cycle Time
D123 TRETD Characteristic Retention
V
Using EECON to read/write
4
ms
40
—
—
Year Provided no other
specifications are violated
D124
TREF
Number of Total Erase/Write
Cycles before Refresh(2)
1M
10M
—
E/W -40°C to +125°C
Program Flash Memory
Cell Endurance
—
3.6
3.6
—
D130
D131
D132
D133
EP
—
1.8
1.8
—
10K
—
E/W -40°C to +125°C
VPR
VIW
TIW
VDD for Read
V
—
VDD for Row Erase or Write
Self-timed Write Cycle Time
V
2
ms
D134 TRETD Characteristic Retention
40
—
—
Year Provided no other
specifications are violated
†
Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance
only and are not tested.
Note 1: These specifications are for programming the on-chip program memory through the use of table write
instructions.
2: Refer to Section 7.8 “Using the Data EEPROM” for a more detailed discussion on data EEPROM
endurance.
3: Required only if single-supply programming is disabled.
DS41303B-page 370
Advance Information
© 2007 Microchip Technology Inc.
PIC18F2XK20/4XK20
TABLE 26-1: COMPARATOR SPECIFICATIONS
Operating Conditions: 1.8V < VDD < 3.6V, -40°C < TA < +125°C (unless otherwise stated).
Param
No.
Sym
Characteristics
Input Offset Voltage
Min
Typ
Max
Units
Comments
CM01
VIOFF
—
0
±7.5
—
±15
VDD
—
mV
V
CM02
CM03
CM04
CM05
VICM
Input Common Mode Voltage
Common Mode Rejection Ratio
Response Time
CMRR
TRESP
55
—
—
—
dB
ns
μs
150
—
400
10
Note 1
TMC2OV Comparator Mode Change to
Output Valid*
*
These parameters are characterized but not tested.
Note 1: Response time measured with one comparator input at VDD/2, while the other input transitions
from VSS to VDD.
TABLE 26-2: CVREF VOLTAGE REFERENCE SPECIFICATIONS
Operating Conditions: 1.8V < VDD < 3.6V, -40°C < TA < +125°C (unless otherwise stated).
Param
No.
Sym
Characteristics
Step Size(2)
Min
Typ
Max
Units
Comments
CV01*
CLSB
—
—
VDD/24
VDD/32
—
—
V
V
Low Range (VRR = 1)
High Range (VRR = 0)
CV02*
CACC
Absolute Accuracy
—
—
—
—
1/4
1/2
LSb Low Range (VRR = 1)
LSb High Range (VRR = 0)
CV03*
CV04*
CR
Unit Resistor Value (R)
Settling Time(1)
—
—
2k
—
—
Ω
CST
10
μs
*
These parameters are characterized but not tested.
Note 1: Settling time measured while CVRR = 1and CVR3:CVR0 transitions from ‘0000’ to ‘1111’.
TABLE 26-3: FIXED VOLTAGE REFERENCE (FVR) SPECIFICATIONS
Operating Conditions: 1.8V < VDD < 3.6V, -40°C < TA < +125°C (unless otherwise stated).
Standard Operating Conditions (unless otherwise stated)
VR Voltage Reference Specifications
Operating temperature
-40°C ≤ TA ≤ +125°C
Param
No.
Sym
Characteristics
VR voltage output
Min
Typ
Max
Units
Comments
VR01
VR02
VROUT
TBD
—
1.2
TBD
TBD
V
TCVOUT Voltage drift temperature
coefficient
TBD
ppm/°C
VR03
VR04
ΔVROUT/ Voltage drift with respect to
—
—
TBD
TBD
—
μV/V
μs
ΔVDD
VDD regulation
TSTABLE Settling Time
TBD
Legend: TBD = To Be Determined
*
These parameters are characterized but not tested.
© 2007 Microchip Technology Inc.
Advance Information
DS41303B-page 371
PIC18F2XK20/4XK20
FIGURE 26-2:
HIGH/LOW-VOLTAGE DETECT CHARACTERISTICS
VDD
(HLVDIF can be
cleared by software)
VHLVD
(HLVDIF set by hardware)
HLVDIF
TABLE 26-4: HIGH/LOW-VOLTAGE DETECT CHARACTERISTICS
Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C ≤ TA ≤ +125°C
Param
No.
Symbol
Characteristic
Min
Typ† Max
Units
Conditions
D420
HLVD Voltage on VDD LVV = 0000
1.8
1.9
2.0
2.1
2.2
2.3
2.4
2.5
2.6
2.7
2.8
2.9
3.0
3.3
3.5
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
Transition High-to-Low
LVV = 0001
LVV = 0010
LVV = 0011
LVV = 0100
LVV = 0101
LVV = 0110
LVV = 0111
LVV = 1000
LVV = 1001
LVV = 1010
LVV = 1011
LVV = 1100
LVV = 1101
LVV = 1110
†
Production tested at TAMB = 25°C. Specifications over temperature limits ensured by characterization.
DS41303B-page 372
Advance Information
© 2007 Microchip Technology Inc.
PIC18F2XK20/4XK20
26.11 AC (Timing) Characteristics
26.11.1 TIMING PARAMETER SYMBOLOGY
The timing parameter symbols have been created
using one of the following formats:
1. TppS2ppS
2. TppS
T
3. TCC:ST
4. Ts
(I2C™ specifications only)
(I2C specifications only)
F
Frequency
T
Time
Lowercase letters (pp) and their meanings:
pp
cc
ck
cs
di
CCP1
CLKOUT
CS
osc
rd
OSC1
RD
rw
sc
ss
t0
RD or WR
SCK
SDI
do
dt
SDO
SS
Data in
I/O port
MCLR
T0CKI
T13CKI
WR
io
t1
mc
wr
Uppercase letters and their meanings:
S
F
Fall
P
R
V
Z
Period
H
High
Rise
I
L
Invalid (High-impedance)
Low
Valid
High-impedance
I2C only
AA
output access
Bus free
High
Low
High
Low
BUF
TCC:ST (I2C specifications only)
CC
HD
Hold
SU
Setup
ST
DAT
STA
DATA input hold
Start condition
STO
Stop condition
© 2007 Microchip Technology Inc.
Advance Information
DS41303B-page 373
PIC18F2XK20/4XK20
26.11.2 TIMING CONDITIONS
The temperature and voltages specified in Table 26-4
apply to all timing specifications unless otherwise
noted. Figure 26-3 specifies the load conditions for the
timing specifications.
TABLE 26-5: TEMPERATURE AND VOLTAGE SPECIFICATIONS – AC
Standard Operating Conditions (unless otherwise stated)
Operating temperature
Operating voltage VDD range as described in DC spec Section 26.1 and
Section 26.9.
-40°C ≤ TA ≤ +125°C
AC CHARACTERISTICS
FIGURE 26-3:
LOAD CONDITIONS FOR DEVICE TIMING SPECIFICATIONS
Load Condition 1 Load Condition 2
VDD/2
CL
RL
Pin
VSS
CL
Pin
RL = 464Ω
CL = 50 pF for all pins except OSC2/CLKOUT
and including D and E outputs as ports
VSS
DS41303B-page 374
Advance Information
© 2007 Microchip Technology Inc.
PIC18F2XK20/4XK20
26.11.3 TIMING DIAGRAMS AND SPECIFICATIONS
FIGURE 26-4:
EXTERNAL CLOCK TIMING (ALL MODES EXCEPT PLL)
Q4
Q1
1
Q2
Q3
Q4
Q1
OSC1
3
4
3
4
2
CLKOUT
TABLE 26-6: EXTERNAL CLOCK TIMING REQUIREMENTS
Param.
Symbol
Characteristic
Min
Max
Units
Conditions
No.
1A
FOSC
External CLKIN
DC
64
MHz EC, ECIO Oscillator mode
Frequency(1)
Oscillator Frequency(1)
DC
0.1
4
4
4
MHz RC Oscillator mode
MHz XT Oscillator mode
MHz HS Oscillator mode
MHz HS + PLL Oscillator mode
kHz LP Oscillator mode
25
4
16
5
33
1
TOSC
External CLKIN Period(1)
Oscillator Period(1)
15.6
250
250
—
ns
ns
ns
EC, ECIO Oscillator mode
RC Oscillator mode
—
10,000
XT Oscillator mode
40
62.5
250
250
ns
ns
HS Oscillator mode
HS + PLL Oscillator mode
30
100
30
2.5
10
—
—
—
μs
ns
ns
μs
ns
ns
ns
ns
LP Oscillator mode
TCY = 4/FOSC
2
3
TCY
Instruction Cycle Time(1)
TOSL,
TOSH
External Clock in (OSC1)
High or Low Time
—
XT Oscillator mode
LP Oscillator mode
HS Oscillator mode
XT Oscillator mode
LP Oscillator mode
HS Oscillator mode
—
—
4
TOSR,
TOSF
External Clock in (OSC1)
Rise or Fall Time
20
50
7.5
—
—
Note 1: Instruction cycle period (TCY) equals four times the input oscillator time base period for all configurations
except PLL. All specified values are based on characterization data for that particular oscillator type under
standard operating conditions with the device executing code. Exceeding these specified limits may result
in an unstable oscillator operation and/or higher than expected current consumption. All devices are tested
to operate at “min.” values with an external clock applied to the OSC1/CLKIN pin. When an external clock
input is used, the “max.” cycle time limit is “DC” (no clock) for all devices.
© 2007 Microchip Technology Inc.
Advance Information
DS41303B-page 375
PIC18F2XK20/4XK20
TABLE 26-7: PLL CLOCK TIMING SPECIFICATIONS (VDD = 4.2V TO 5.5V)
Param
Sym
Characteristic
Min
Typ†
Max
Units Conditions
No.
F10
FOSC Oscillator Frequency Range
4
—
—
—
—
64
64
2
MHz HS mode only
F11
F12
F13
FSYS On-Chip VCO System Frequency
32
—
-2
MHz HS mode only
trc
PLL Start-up Time (Lock Time)
ms
%
ΔCLK CLKOUT Stability (Jitter)
+2
†
Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance
only and are not tested.
TABLE 26-8: AC CHARACTERISTICS: INTERNAL OSCILLATORS ACCURACY
PIC18F2XK20/4XK20
Standard Operating Conditions (unless otherwise stated)
PIC18F2XK20/4XK20
Operating temperature
-40°C ≤ TA ≤ +125°C
Param
No.
Min
Typ
Max
Units
Conditions
HFINTOSC Accuracy @ Freq = 16 MHz, 8 MHz, 4 MHz, 2 MHz, 1 MHz, 500 kHz, 250 kHz(1)
1
—
—
—
1
%
%
%
+25°C
VDD = 1.8-3.6V
VDD = 1.8-3.6V
VDD = 1.8-3.6V
-2
+2
+5
0°C to +85°C
-40°C to +125°C
-5
LFINTOSC Accuracy @ Freq = 31 kHz(2)
26.562
—
35.938 kHz -40°C to +125°C
VDD = 1.8-3.6V
Legend: Shading of rows is to assist in readability of the table.
Note 1: Frequency calibrated at 25°C. OSCTUNE register can be used to compensate for temperature drift.
2: INTOSC frequency after calibration.
3: Change of INTOSC frequency as VDD changes.
FIGURE 26-5:
CLKOUT AND I/O TIMING
Q1
Q2
Q3
Q4
OSC1
11
10
CLKOUT
13
12
19
18
14
16
I/O pin
(Input)
15
17
I/O pin
(Output)
New Value
Old Value
20, 21
Note:
Refer to Figure 26-3 for load conditions.
DS41303B-page 376
Advance Information
© 2007 Microchip Technology Inc.
PIC18F2XK20/4XK20
TABLE 26-9: CLKOUT AND I/O TIMING REQUIREMENTS
Param
No.
Symbol
Characteristic
Min
Typ
Max
Units Conditions
10
11
12
13
14
15
16
17
18
TosH2ckL OSC1 ↑ to CLKOUT ↓
TosH2ckH OSC1 ↑ to CLKOUT ↑
—
75
75
35
35
—
—
—
50
—
200
200
100
100
ns
ns
ns
ns
(Note 1)
(Note 1)
(Note 1)
(Note 1)
(Note 1)
(Note 1)
(Note 1)
—
TckR
TckF
CLKOUT Rise Time
CLKOUT Fall Time
—
—
TckL2ioV CLKOUT ↓ to Port Out Valid
TioV2ckH Port In Valid before CLKOUT ↑
TckH2ioI Port In Hold after CLKOUT ↑
TosH2ioV OSC1 ↑ (Q1 cycle) to Port Out Valid
—
0.5 TCY + 20 ns
0.25 TCY + 25
—
—
ns
ns
ns
ns
0
—
150
—
TosH2ioI OSC1 ↑ (Q2 cycle) to Port Input Invalid
100
(I/O in hold time)
19
TioV2osH Port Input Valid to OSC1 ↑ (I/O in setup time)
0
—
10
10
—
—
—
25
25
—
—
ns
ns
ns
ns
ns
ns
20
TioR
TioF
TINP
TRBP
TRCP
Port Output Rise Time
—
21
Port Output Fall Time
—
22†
23†
24†
INT pin High or Low Time
TCY
TCY
20
RB7:RB4 Change INT High or Low Time
RC7:RC4 Change INT High or Low Time
†
These parameters are asynchronous events not related to any internal clock edges.
Note 1: Measurements are taken in RC mode, where CLKOUT output is 4 x TOSC.
FIGURE 26-6:
RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND
POWER-UP TIMER TIMING
VDD
MCLR
30
Internal
POR
33
PWRT
Time-out
32
OSC
Time-out
Internal
Reset
Watchdog
Timer
Reset
31
34
34
I/O pins
Note:
Refer to Figure 26-3 for load conditions.
© 2007 Microchip Technology Inc.
Advance Information
DS41303B-page 377
PIC18F2XK20/4XK20
FIGURE 26-7:
BROWN-OUT RESET TIMING
BVDD
VDD
35
VBGAP = 1.2V
VIRVST
Enable Internal
Reference Voltage
Internal Reference
Voltage Stable
36
TABLE 26-10: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER
AND BROWN-OUT RESET REQUIREMENTS
Param.
No.
Symbol
Characteristic
Min
Typ
Max
Units
Conditions
30
TmcL
TWDT
MCLR Pulse Width (low)
2
—
—
μs
ms
31
Watchdog Timer Time-out Period
(no postscaler)
—
4.00
TBD
32
33
34
TOST
Oscillation Start-up Timer Period
1024 TOSC
—
65.5
2
1024 TOSC
TBD
—
ms
μs
TOSC = OSC1 period
TPWRT Power-up Timer Period
—
—
TIOZ
I/O High-Impedance from MCLR
Low or Watchdog Timer Reset
—
35
36
TBOR
Brown-out Reset Pulse Width
200
—
—
—
μs VDD ≤ BVDD (see D005)
μs
TIVRST Time for Internal Reference
Voltage to become Stable
20
50
37
38
39
THLVD High/Low-Voltage Detect Pulse Width
200
5
—
—
1
—
10
—
μs
μs
ms
VDD ≤ VHLVD
TCSD
CPU Start-up Time
TIOBST Time for INTOSC to Stabilize
—
Legend: TBD = To Be Determined
FIGURE 26-8: TIMER0 AND TIMER1 EXTERNAL CLOCK TIMINGS
T0CKI
41
40
42
T1OSO/T13CKI
46
45
47
48
TMR0 or
TMR1
Note:
Refer to Figure 26-3 for load conditions.
DS41303B-page 378
Advance Information
© 2007 Microchip Technology Inc.
PIC18F2XK20/4XK20
TABLE 26-11: TIMER0 AND TIMER1 EXTERNAL CLOCK REQUIREMENTS
Param
No.
Symbol
Characteristic
T0CKI High Pulse Width
Min
Max Units Conditions
40
41
42
Tt0H
No prescaler
With prescaler
No prescaler
With prescaler
No prescaler
With prescaler
0.5 TCY + 20
10
—
—
—
—
—
—
ns
ns
ns
ns
ns
Tt0L
Tt0P
T0CKI Low Pulse Width
T0CKI Period
0.5 TCY + 20
10
TCY + 10
Greater of:
20 ns or
ns N = prescale
value
(TCY + 40)/N
(1, 2, 4,..., 256)
45
46
47
Tt1H
Tt1L
T13CKI
High Time
Synchronous, no prescaler
0.5 TCY + 20
10
—
—
ns
ns
Synchronous,
with prescaler
Asynchronous
30
0.5 TCY + 5
10
—
—
—
ns
ns
ns
T13CKI Low Synchronous, no prescaler
Time
Synchronous,
with prescaler
Asynchronous
30
—
—
ns
Tt1P
Ft1
T13CKI
Input Period
Synchronous
Asynchronous
Greater of:
20 ns or
(TCY + 40)/N
ns N = prescale
value (1, 2, 4, 8)
60
DC
—
50
ns
kHz
—
T13CKI Oscillator Input Frequency Range
48
Tcke2tmrI Delay from External T13CKI Clock Edge to
Timer Increment
2 TOSC
7 TOSC
FIGURE 26-9:
CAPTURE/COMPARE/PWM TIMINGS (ALL CCP MODULES)
CCPx
(Capture Mode)
50
51
52
54
CCPx
(Compare or PWM Mode)
53
Note:
Refer to Figure 26-3 for load conditions.
© 2007 Microchip Technology Inc.
Advance Information
DS41303B-page 379
PIC18F2XK20/4XK20
TABLE 26-12: CAPTURE/COMPARE/PWM REQUIREMENTS (ALL CCP MODULES)
Param
Symbol
Characteristic
Min
Max
Units
Conditions
No.
50
TccL
CCPx Input Low No prescaler
0.5 TCY + 20
10
—
—
ns
ns
Time
With
prescaler
51
52
TccH
TccP
CCPx Input
High Time
No prescaler
0.5 TCY + 20
10
—
—
ns
ns
With
prescaler
CCPx Input Period
3 TCY + 40
N
—
ns
N = prescale
value (1, 4 or 16)
53
54
TccR
TccF
CCPx Output Fall Time
CCPx Output Fall Time
—
—
25
25
ns
ns
FIGURE 26-10:
PARALLEL SLAVE PORT TIMING (PIC18F4XK20)
RE2/CS
RE0/RD
RE1/WR
65
RD7:RD0
62
64
63
Note:
Refer to Figure 26-3 for load conditions.
TABLE 26-13: PARALLEL SLAVE PORT REQUIREMENTS (PIC18F4XK20)
Param.
Symbol
Characteristic
Min
Max Units
Conditions
No.
62
TdtV2wrH
Data In Valid before WR ↑ or CS ↑
(setup time)
20
—
ns
63
64
65
66
TwrH2dtI
TrdL2dtV
TrdH2dtI
TibfINH
WR ↑ or CS ↑ to Data–In Invalid (hold time)
RD ↓ and CS ↓ to Data–Out Valid
RD ↑ or CS ↓ to Data–Out Invalid
20
—
10
—
—
80
ns
ns
ns
30
Inhibit of the IBF Flag bit being Cleared from
3 TCY
WR ↑ or CS ↑
DS41303B-page 380
Advance Information
© 2007 Microchip Technology Inc.
PIC18F2XK20/4XK20
FIGURE 26-11:
EXAMPLE SPI MASTER MODE TIMING (CKE = 0)
SS
70
SCK
(CKP = 0)
71
72
78
79
79
SCK
(CKP = 1)
78
80
MSb
bit 6 - - - - - -1
LSb
SDO
SDI
75, 76
MSb In
74
bit 6 - - - -1
LSb In
73
Note: Refer to Figure 26-3 for load conditions.
TABLE 26-14: EXAMPLE SPI MODE REQUIREMENTS (MASTER MODE, CKE = 0)
Param
No.
Symbol
Characteristic
Min
Max Units Conditions
70
TssL2scH, SS ↓ to SCK ↓ or SCK ↑ Input
TssL2scL
TCY
—
ns
71
TscH
SCK Input High Time
(Slave mode)
Continuous
Single Byte
Continuous
Single Byte
1.25 TCY + 30
—
—
—
—
—
ns
71A
72
40
1.25 TCY + 30
40
ns (Note 1)
TscL
SCK Input Low Time
(Slave mode)
ns
72A
73
ns (Note 1)
TdiV2scH, Setup Time of SDI Data Input to SCK Edge
TdiV2scL
100
ns
73A
74
Tb2b
Last Clock Edge of Byte 1 to the 1st Clock Edge 1.5 TCY + 40
of Byte 2
—
—
ns (Note 2)
TscH2diL, Hold Time of SDI Data Input to SCK Edge
TscL2diL
100
ns
75
76
78
TdoR
TdoF
TscR
SDO Data Output Rise Time
SDO Data Output Fall Time
—
—
—
25
25
25
ns
ns
ns
SCK Output Rise Time
(Master mode)
79
80
TscF
SCK Output Fall Time (Master mode)
—
—
25
50
ns
ns
TscH2doV, SDO Data Output Valid after SCK Edge
TscL2doV
Note 1: Requires the use of Parameter #73A.
2: Only if Parameter #71A and #72A are used.
© 2007 Microchip Technology Inc.
Advance Information
DS41303B-page 381
PIC18F2XK20/4XK20
FIGURE 26-12:
EXAMPLE SPI MASTER MODE TIMING (CKE = 1)
SS
81
SCK
(CKP = 0)
71
72
79
78
73
SCK
(CKP = 1)
80
LSb
MSb
bit 6 - - - - - -1
SDO
SDI
75, 76
MSb In
74
bit 6 - - - -1
LSb In
Note: Refer to Figure 26-3 for load conditions.
TABLE 26-15: EXAMPLE SPI MODE REQUIREMENTS (MASTER MODE, CKE = 1)
Param.
No.
Symbol
TscH
TscL
Characteristic
Min
Max Units Conditions
71
SCK Input High Time
Continuous
Single Byte
Continuous
Single Byte
1.25 TCY + 30
—
—
—
—
—
ns
(Slave mode)
71A
72
40
1.25 TCY + 30
40
ns (Note 1)
SCK Input Low Time
(Slave mode)
ns
72A
73
ns (Note 1)
TdiV2scH, Setup Time of SDI Data Input to SCK Edge
TdiV2scL
100
ns
73A
74
Tb2b
Last Clock Edge of Byte 1 to the 1st Clock Edge
of Byte 2
1.5 TCY + 40
100
—
—
ns (Note 2)
TscH2diL,
TscL2diL
Hold Time of SDI Data Input to SCK Edge
ns
75
76
78
TdoR
TdoF
TscR
SDO Data Output Rise Time
SDO Data Output Fall Time
—
—
—
25
25
25
ns
ns
ns
SCK Output Rise Time
(Master mode)
79
80
TscF
SCK Output Fall Time (Master mode)
—
—
25
50
ns
ns
TscH2doV, SDO Data Output Valid after SCK Edge
TscL2doV
81
TdoV2scH, SDO Data Output Setup to SCK Edge
TdoV2scL
TCY
—
ns
Note 1: Requires the use of Parameter #73A.
2: Only if Parameter #71A and #72A are used.
DS41303B-page 382
Advance Information
© 2007 Microchip Technology Inc.
PIC18F2XK20/4XK20
FIGURE 26-13:
EXAMPLE SPI SLAVE MODE TIMING (CKE = 0)
SS
70
SCK
(CKP = 0)
83
71
72
78
79
79
78
SCK
(CKP = 1)
80
MSb
LSb
SDO
SDI
bit 6 - - - - - -1
77
75, 76
MSb In
74
bit 6 - - - -1
LSb In
73
Note:
Refer to Figure 26-3 for load conditions.
TABLE 26-16: EXAMPLE SPI MODE REQUIREMENTS (SLAVE MODE TIMING, CKE = 0)
Param
No.
Symbol
Characteristic
Min
Max Units Conditions
70
TssL2scH, SS ↓ to SCK ↓ or SCK ↑ Input
TssL2scL
TCY
—
ns
71
TscH
SCK Input High Time
(Slave mode)
Continuous
Single Byte
Continuous
Single Byte
1.25 TCY + 30
—
—
—
—
—
ns
71A
72
40
1.25 TCY + 30
40
ns (Note 1)
TscL
SCK Input Low Time
(Slave mode)
ns
72A
73
ns (Note 1)
TdiV2scH, Setup Time of SDI Data Input to SCK Edge
TdiV2scL
100
ns
73A
74
Tb2b
Last Clock Edge of Byte 1 to the First Clock Edge of Byte 2 1.5 TCY + 40
—
—
ns (Note 2)
TscH2diL, Hold Time of SDI Data Input to SCK Edge
TscL2diL
100
ns
75
76
77
78
79
80
TdoR
TdoF
SDO Data Output Rise Time
SDO Data Output Fall Time
—
—
10
—
—
—
25
25
50
25
25
50
ns
ns
ns
ns
ns
ns
TssH2doZ SS↑ to SDO Output High-Impedance
TscR
TscF
SCK Output Rise Time (Master mode)
SCK Output Fall Time (Master mode)
TscH2doV, SDO Data Output Valid after SCK Edge
TscL2doV
83
TscH2ssH, SS ↑ after SCK edge
TscL2ssH
1.5 TCY + 40
—
ns
Note 1: Requires the use of Parameter #73A.
2: Only if Parameter #71A and #72A are used.
© 2007 Microchip Technology Inc.
Advance Information
DS41303B-page 383
PIC18F2XK20/4XK20
FIGURE 26-14:
EXAMPLE SPI SLAVE MODE TIMING (CKE = 1)
82
SS
70
SCK
83
(CKP = 0)
71
72
SCK
(CKP = 1)
80
MSb
bit 6 - - - - - -1
LSb
SDO
SDI
75, 76
77
MSb In
74
bit 6 - - - -1
LSb In
Note: Refer to Figure 26-3 for load conditions.
TABLE 26-17: EXAMPLE SPI SLAVE MODE REQUIREMENTS (CKE = 1)
Param
No.
Symbol
Characteristic
Min
Max Units Conditions
70
TssL2scH, SS ↓ to SCK ↓ or SCK ↑ Input
TssL2scL
TCY
—
ns
71
TscH
TscL
Tb2b
SCK Input High Time
(Slave mode)
Continuous
Single Byte
Continuous
Single Byte
1.25 TCY + 30
—
—
—
—
—
—
ns
71A
72
40
1.25 TCY + 30
40
ns (Note 1)
ns
SCK Input Low Time
(Slave mode)
72A
73A
74
ns (Note 1)
ns (Note 2)
ns
Last Clock Edge of Byte 1 to the First Clock Edge of Byte 2 1.5 TCY + 40
TscH2diL, Hold Time of SDI Data Input to SCK Edge
TscL2diL
100
75
76
77
78
TdoR
TdoF
SDO Data Output Rise Time
SDO Data Output Fall Time
—
—
10
—
25
25
50
25
ns
ns
ns
ns
TssH2doZ SS↑ to SDO Output High-Impedance
TscR
SCK Output Rise Time
(Master mode)
79
80
TscF
SCK Output Fall Time (Master mode)
—
—
25
50
ns
ns
TscH2doV, SDO Data Output Valid after SCK Edge
TscL2doV
82
83
TssL2doV SDO Data Output Valid after SS ↓ Edge
—
50
—
ns
ns
TscH2ssH, SS ↑ after SCK Edge
TscL2ssH
1.5 TCY + 40
Note 1: Requires the use of Parameter #73A.
2: Only if Parameter #71A and #72A are used.
DS41303B-page 384
Advance Information
© 2007 Microchip Technology Inc.
PIC18F2XK20/4XK20
FIGURE 26-15:
I2C™ BUS START/STOP BITS TIMING
SCL
SDA
91
93
90
92
Stop
Condition
Start
Condition
Note: Refer to Figure 26-3 for load conditions.
TABLE 26-18: I2C™ BUS START/STOP BITS REQUIREMENTS (SLAVE MODE)
Param.
Symbol
Characteristic
Min
Max
Units
Conditions
No.
90
TSU:STA Start Condition
Setup Time
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
4700
600
—
—
—
—
—
—
—
—
ns
Only relevant for Repeated
Start condition
91
92
93
THD:STA Start Condition
Hold Time
4000
600
ns
ns
ns
After this period, the first
clock pulse is generated
TSU:STO Stop Condition
Setup Time
4700
600
THD:STO Stop Condition
Hold Time
4000
600
FIGURE 26-16:
I2C™ BUS DATA TIMING
103
102
100
101
SCL
90
106
107
91
92
SDA
In
110
109
109
SDA
Out
Note: Refer to Figure 26-3 for load conditions.
© 2007 Microchip Technology Inc.
Advance Information
DS41303B-page 385
PIC18F2XK20/4XK20
TABLE 26-19: I2C™ BUS DATA REQUIREMENTS (SLAVE MODE)
Param.
Symbol
Characteristic
Min
Max Units
Conditions
No.
100
THIGH
Clock High Time
100 kHz mode
4.0
—
—
μs
μs
PIC18FXXXX must operate
at a minimum of 1.5 MHz
400 kHz mode
0.6
PIC18FXXXX must operate
at a minimum of 10 MHz
SSP Module
1.5 TCY
4.7
—
—
101
TLOW
Clock Low Time
100 kHz mode
μs
μs
PIC18FXXXX must operate
at a minimum of 1.5 MHz
400 kHz mode
1.3
—
PIC18FXXXX must operate
at a minimum of 10 MHz
SSP Module
1.5 TCY
—
—
102
103
TR
TF
SDA and SCL Rise 100 kHz mode
1000
ns
ns
Time
400 kHz mode
20 + 0.1 CB 300
CB is specified to be from
10 to 400 pF
SDA and SCL Fall 100 kHz mode
Time
—
300
ns
ns
400 kHz mode
20 + 0.1 CB 300
CB is specified to be from
10 to 400 pF
90
TSU:STA Start Condition
Setup Time
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
4.7
0.6
4.0
0.6
0
—
—
μs
μs
μs
μs
ns
μs
ns
ns
μs
μs
ns
ns
μs
μs
Only relevant for Repeated
Start condition
91
THD:STA Start Condition
Hold Time
—
After this period, the first
clock pulse is generated
—
106
107
92
THD:DAT Data Input Hold
Time
—
0
0.9
—
TSU:DAT Data Input Setup
Time
250
100
4.7
0.6
—
(Note 2)
—
TSU:STO Stop Condition
Setup Time
—
—
109
110
TAA
Output Valid from
Clock
3500
—
(Note 1)
—
TBUF
Bus Free Time
4.7
1.3
—
Time the bus must be free
before a new transmission
can start
—
D102
CB
Bus Capacitive Loading
—
400
pF
Note 1: As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region
(min. 300 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions.
2: A fast mode I2C bus device can be used in a standard mode I2C bus system but the requirement,
TSU:DAT ≥ 250 ns, must then be met. This will automatically be the case if the device does not stretch the
LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must
output the next data bit to the SDA line, TR max. + TSU:DAT = 1000 + 250 = 1250 ns (according to the
standard mode I2C bus specification), before the SCL line is released.
DS41303B-page 386
Advance Information
© 2007 Microchip Technology Inc.
PIC18F2XK20/4XK20
FIGURE 26-17:
MASTER SSP I2C™ BUS START/STOP BITS TIMING WAVEFORMS
SCL
SDA
93
91
90
92
Stop
Condition
Start
Condition
Note: Refer to Figure 26-3 for load conditions.
TABLE 26-20: MASTER SSP I2C™ BUS START/STOP BITS REQUIREMENTS
Param.
Symbol
Characteristic
Min
Max Units
Conditions
No.
90
TSU:STA Start Condition
Setup Time
100 kHz mode
400 kHz mode
1 MHz mode(1) 2(TOSC)(BRG + 1)
2(TOSC)(BRG + 1)
2(TOSC)(BRG + 1)
—
—
—
—
—
—
—
—
—
—
—
—
ns Only relevant for
Repeated Start
condition
91
92
93
THD:STA Start Condition
Hold Time
100 kHz mode
400 kHz mode
1 MHz mode(1) 2(TOSC)(BRG + 1)
2(TOSC)(BRG + 1)
ns After this period, the
first clock pulse is
generated
2(TOSC)(BRG + 1)
TSU:STO Stop Condition
Setup Time
100 kHz mode
400 kHz mode
1 MHz mode(1) 2(TOSC)(BRG + 1)
2(TOSC)(BRG + 1)
ns
2(TOSC)(BRG + 1)
THD:STO Stop Condition
Hold Time
100 kHz mode
400 kHz mode
2(TOSC)(BRG + 1)
ns
2(TOSC)(BRG + 1)
1 MHz mode(1) 2(TOSC)(BRG + 1)
Note 1: Maximum pin capacitance = 10 pF for all I2C pins.
FIGURE 26-18:
MASTER SSP I2C™ BUS DATA TIMING
103
102
100
101
SCL
90
106
91
92
107
SDA
In
110
109
109
SDA
Out
Note: Refer to Figure 26-3 for load conditions.
© 2007 Microchip Technology Inc.
Advance Information
DS41303B-page 387
PIC18F2XK20/4XK20
TABLE 26-21: MASTER SSP I2C™ BUS DATA REQUIREMENTS
Param.
Symbol
Characteristic
Min
Max Units
Conditions
No.
100
THIGH
Clock High Time 100 kHz mode
400 kHz mode
2(TOSC)(BRG + 1)
2(TOSC)(BRG + 1)
—
—
ms
ms
ms
ms
ms
ms
ns
1 MHz mode(1) 2(TOSC)(BRG + 1)
—
101
102
103
90
TLOW
TR
Clock Low Time 100 kHz mode
400 kHz mode
2(TOSC)(BRG + 1)
2(TOSC)(BRG + 1)
—
—
1 MHz mode(1) 2(TOSC)(BRG + 1)
—
SDA and SCL
Rise Time
100 kHz mode
400 kHz mode
1 MHz mode(1)
100 kHz mode
400 kHz mode
1 MHz mode(1)
—
1000
300
300
300
300
100
—
CB is specified to be from
10 to 400 pF
20 + 0.1 CB
ns
—
—
ns
TF
SDA and SCL
Fall Time
ns
CB is specified to be from
10 to 400 pF
20 + 0.1 CB
—
ns
ns
TSU:STA Start Condition 100 kHz mode
2(TOSC)(BRG + 1)
2(TOSC)(BRG + 1)
ms Only relevant for
Setup Time
Repeated Start
400 kHz mode
—
ms
condition
ms
1 MHz mode(1) 2(TOSC)(BRG + 1)
—
91
THD:STA Start Condition 100 kHz mode
2(TOSC)(BRG + 1)
2(TOSC)(BRG + 1)
—
ms After this period, the first
Hold Time
clock pulse is generated
400 kHz mode
—
ms
1 MHz mode(1) 2(TOSC)(BRG + 1)
—
ms
ns
106
107
92
THD:DAT Data Input
Hold Time
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
0
—
0
0.9
—
ms
TSU:DAT Data Input
Setup Time
250
ns
ns
(Note 2)
100
—
TSU:STO Stop Condition
Setup Time
2(TOSC)(BRG + 1)
—
ms
ms
ms
ns
2(TOSC)(BRG + 1)
—
1 MHz mode(1) 2(TOSC)(BRG + 1)
—
109
TAA
Output Valid
from Clock
100 kHz mode
400 kHz mode
1 MHz mode(1)
100 kHz mode
400 kHz mode
—
—
3500
1000
—
ns
—
ns
110
TBUF
CB
Bus Free Time
4.7
1.3
—
ms Time the bus must be free
before a new transmission
—
ms
can start
pF
D102
Bus Capacitive Loading
—
400
Note 1: Maximum pin capacitance = 10 pF for all I2C pins.
2: A fast mode I2C bus device can be used in a standard mode I2C bus system, but parameter 107 ≥ 250 ns
must then be met. This will automatically be the case if the device does not stretch the LOW period of the
SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next data bit
to the SDA line, parameter 102 + parameter 107 = 1000 + 250 = 1250 ns (for 100 kHz mode), before the
SCL line is released.
DS41303B-page 388
Advance Information
© 2007 Microchip Technology Inc.
PIC18F2XK20/4XK20
FIGURE 26-19:
EUSART SYNCHRONOUS TRANSMISSION (MASTER/SLAVE) TIMING
RC6/TX/CK
pin
121
121
RC7/RX/DT
pin
120
Note: Refer to Figure 26-3 for load conditions.
122
TABLE 26-22: EUSART SYNCHRONOUS TRANSMISSION REQUIREMENTS
Param
Symbol
Characteristic
Min
Max
Units Conditions
No.
120
TckH2dtV SYNC XMIT (MASTER & SLAVE)
Clock High to Data Out Valid
—
—
40
20
ns
ns
121
122
Tckrf
Clock Out Rise Time and Fall Time
(Master mode)
Tdtrf
Data Out Rise Time and Fall Time
—
20
ns
FIGURE 26-20:
EUSART SYNCHRONOUS RECEIVE (MASTER/SLAVE) TIMING
RC6/TX/CK
pin
125
RC7/RX/DT
pin
126
Note: Refer to Figure 26-3 for load conditions.
TABLE 26-23: EUSART SYNCHRONOUS RECEIVE REQUIREMENTS
Param.
Symbol
Characteristic
Min
Max
Units
Conditions
No.
125
TdtV2ckl SYNC RCV (MASTER & SLAVE)
Data Hold before CK ↓ (DT hold time)
10
15
—
—
ns
ns
126
TckL2dtl
Data Hold after CK ↓ (DT hold time)
© 2007 Microchip Technology Inc.
Advance Information
DS41303B-page 389
PIC18F2XK20/4XK20
TABLE 26-24: A/D CONVERTER CHARACTERISTICS: PIC18F2XK20/4XK20
Param
Symbol
Characteristic
Min
Typ
Max
Units
Conditions
No.
A01
NR
Resolution
—
—
—
—
—
—
10
bit ΔVREF ≥ 3.0V
A03
A04
A06
A07
A10
A20
EIL
Integral Linearity Error
Differential Linearity Error
Offset Error
—
<±1
<±1
<±3
<±3
LSb ΔVREF ≥ 3.0V
LSb ΔVREF ≥ 3.0V
LSb ΔVREF ≥ 3.0V
LSb ΔVREF ≥ 3.0V
EDL
EOFF
EGN
—
—
—
Gain Error
—
Monotonicity
Guaranteed(1)
—
VSS ≤ VAIN ≤ VREF
VDD < 3.0V
VDD ≥ 3.0V
ΔVREF Reference Voltage Range
1.8
3
—
—
—
—
V
V
(VREFH – VREFL)
A21
A22
A25
A30
VREFH Reference Voltage High
VDD/2
VSS – 0.3V
VREFL
—
—
—
—
VDD + 0.6
VDD – 3.0V
VREFH
V
V
VREFL
VAIN
Reference Voltage Low
Analog Input Voltage
V
ZAIN
Recommended Impedance of
Analog Voltage Source
—
2.5
kΩ
A50
IREF
VREF Input Current(2)
—
—
—
—
5
150
μA During VAIN acquisition.
μA During A/D conversion
cycle.
Note 1: The A/D conversion result never decreases with an increase in the input voltage and has no missing
codes.
2: VREFH current is from RA3/AN3/VREF+ pin or VDD, whichever is selected as the VREFH source.
VREFL current is from RA2/AN2/VREF-/CVREF pin or VSS, whichever is selected as the VREFL source.
DS41303B-page 390
Advance Information
© 2007 Microchip Technology Inc.
PIC18F2XK20/4XK20
FIGURE 26-21:
A/D CONVERSION TIMING
BSF ADCON0, GO
(Note 2)
131
130
Q4
132
A/D CLK
. . .
.. .
9
8
7
2
1
0
A/D DATA
ADRES
NEW_DATA
TCY
OLD_DATA
ADIF
GO
DONE
SAMPLING STOPPED
SAMPLE
Note 1: If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts.
This allows the SLEEPinstruction to be executed.
2: This is a minimal RC delay (typically 100 ns), which also disconnects the holding capacitor from the analog input.
TABLE 26-25: A/D CONVERSION REQUIREMENTS
Param
Symbol
Characteristic
Min
Max
Units
Conditions
No.
130
TAD
A/D Clock Period
0.7
TBD
11
25.0(1)
μs TOSC based, VREF ≥ 3.0V
μs A/D RC mode
TAD
1
131
132
TCNV
TACQ
Conversion Time
(not including acquisition time) (Note 2)
12
Acquisition Time (Note 3)
1.4
TBD
—
—
μs -40°C to +85°C
μs
0°C ≤ to ≤ +85°C
135
TSWC
TDIS
Switching Time from Convert → Sample
—
(Note 4)
TBD
Discharge Time
0.2
—
μs
Legend: TBD = To Be Determined
Note 1: The time of the A/D clock period is dependent on the device frequency and the TAD clock divider.
2: ADRES register may be read on the following TCY cycle.
3: The time for the holding capacitor to acquire the “New” input voltage when the voltage changes full scale
after the conversion (VDD to VSS or VSS to VDD). The source impedance (RS) on the input channels is 50
Ω.
4: On the following cycle of the device clock.
© 2007 Microchip Technology Inc.
Advance Information
DS41303B-page 391
PIC18F2XK20/4XK20
NOTES:
DS41303B-page 392
Advance Information
© 2007 Microchip Technology Inc.
PIC18F2XK20/4XK20
27.0 DC AND AC
CHARACTERISTICS GRAPHS
AND TABLES
Graphs and tables are not available at this time.
© 2007 Microchip Technology Inc.
Advance Information
DS41303B-page 393
PIC18F2XK20/4XK20
NOTES:
DS41303B-page 394
Advance Information
© 2007 Microchip Technology Inc.
PIC18F2XK20/4XK20
28.0 PACKAGING INFORMATION
28.1 Package Marking Information
28-Lead PDIP
Example
PIC18F25K20-E/SP
XXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXX
e
3
YYWWNNN
0610017
28-Lead SOIC (7.50 mm)
Example
XXXXXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXXXXX
PIC18F25K20-E/SO
0610017
e3
YYWWNNN
40-Lead PDIP
Example
XXXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXXX
YYWWNNN
PIC18F45K20-E/P
0610017
e
3
Legend: XX...X Customer-specific information
Y
YY
WW
NNN
Year code (last digit of calendar year)
Year code (last 2 digits of calendar year)
Week code (week of January 1 is week ‘01’)
Alphanumeric traceability code
e
3
Pb-free JEDEC designator for Matte Tin (Sn)
*
This package is Pb-free. The Pb-free JEDEC designator (
can be found on the outer packaging for this package.
)
e3
Note: In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
© 2007 Microchip Technology Inc.
Advance Information
DS41303B-page 395
PIC18F2XK20/4XK20
Package Marking Information (Continued)
28-Lead SSOP
Example
PIC18F25K20-E/SS
XXXXXXXXXXXXXXX
XXXXXXXXXXXXXXX
XXXXXXXXXXXXXXX
e
3
0610017
YYWWNNN
28-Lead QFN
Example
XXXXXXXX
XXXXXXXX
YYWWNNN
18F24K20
-E/ML
0610017
e
3
44-Lead QFN
Example
XXXXXXXXXX
XXXXXXXXXX
XXXXXXXXXX
YYWWNNN
PIC18F45K20
-E/ML
0610017
e
3
44-Lead TQFP
Example
XXXXXXXXXX
XXXXXXXXXX
XXXXXXXXXX
YYWWNNN
PIC18F44K20
-E/PT
e
3
0610017
DS41303B-page 396
Advance Information
© 2007 Microchip Technology Inc.
PIC18F2XK20/4XK20
28.2 Package Details
The following sections give the technical details of the packages.
28-Lead Skinny Plastic Dual In-Line (SP or PJ) – 300 mil Body [SPDIP]
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
N
NOTE 1
E1
1
2 3
D
E
A2
A
L
c
b1
A1
b
e
eB
Units
INCHES
NOM
28
Dimension Limits
MIN
MAX
Number of Pins
Pitch
N
e
.100 BSC
–
Top to Seating Plane
A
–
.200
.150
–
Molded Package Thickness
Base to Seating Plane
Shoulder to Shoulder Width
Molded Package Width
Overall Length
A2
A1
E
.120
.015
.290
.240
1.345
.110
.008
.040
.014
–
.135
–
.310
.285
1.365
.130
.010
.050
.018
–
.335
.295
1.400
.150
.015
.070
.022
.430
E1
D
Tip to Seating Plane
Lead Thickness
L
c
Upper Lead Width
b1
b
Lower Lead Width
Overall Row Spacing §
eB
Notes:
1. Pin 1 visual index feature may vary, but must be located within the hatched area.
2. § Significant Characteristic.
3. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" per side.
4. Dimensioning and tolerancing per ASME Y14.5M.
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
Microchip Technology Drawing C04-070B
© 2007 Microchip Technology Inc.
Advance Information
DS41303B-page 397
PIC18F2XK20/4XK20
28-Lead Plastic Small Outline (SO or OI) – Wide, 7.50 mm Body [SOIC]
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
D
N
E
E1
NOTE 1
1
2
3
e
b
h
α
h
c
φ
A2
A
L
A1
L1
β
Units
MILLIMETERS
Dimension Limits
MIN
NOM
MAX
Number of Pins
Pitch
N
e
28
1.27 BSC
Overall Height
A
–
–
2.65
–
Molded Package Thickness
Standoff §
A2
A1
E
2.05
0.10
–
–
0.30
Overall Width
10.30 BSC
Molded Package Width
Overall Length
Chamfer (optional)
Foot Length
E1
D
h
7.50 BSC
17.90 BSC
0.25
0.40
–
0.75
1.27
L
–
Footprint
L1
φ
1.40 REF
Foot Angle Top
Lead Thickness
Lead Width
0°
0.18
0.31
5°
–
–
–
–
–
8°
c
0.33
0.51
15°
b
Mold Draft Angle Top
Mold Draft Angle Bottom
α
β
5°
15°
Notes:
1. Pin 1 visual index feature may vary, but must be located within the hatched area.
2. § Significant Characteristic.
3. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.15 mm per side.
4. Dimensioning and tolerancing per ASME Y14.5M.
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
REF: Reference Dimension, usually without tolerance, for information purposes only.
Microchip Technology Drawing C04-052B
DS41303B-page 398
Advance Information
© 2007 Microchip Technology Inc.
PIC18F2XK20/4XK20
40-Lead Plastic Dual In-Line (P or PL) – 600 mil Body [PDIP]
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
N
NOTE 1
E1
1 2 3
D
E
A2
A
L
c
b1
b
A1
e
eB
Units
INCHES
Dimension Limits
MIN
NOM
MAX
Number of Pins
Pitch
N
e
40
.100 BSC
Top to Seating Plane
Molded Package Thickness
Base to Seating Plane
Shoulder to Shoulder Width
Molded Package Width
Overall Length
A
–
–
–
–
–
–
–
–
–
–
–
–
.250
.195
–
A2
A1
E
.125
.015
.590
.485
1.980
.115
.008
.030
.014
–
.625
.580
2.095
.200
.015
.070
.023
.700
E1
D
Tip to Seating Plane
Lead Thickness
L
c
Upper Lead Width
b1
b
Lower Lead Width
Overall Row Spacing §
eB
Notes:
1. Pin 1 visual index feature may vary, but must be located within the hatched area.
2. § Significant Characteristic.
3. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" per side.
4. Dimensioning and tolerancing per ASME Y14.5M.
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
Microchip Technology Drawing C04-016B
© 2007 Microchip Technology Inc.
Advance Information
DS41303B-page 399
PIC18F2XK20/4XK20
28-Lead Plastic Quad Flat, No Lead Package (ML) – 6x6 mm Body [QFN]
with 0.55 mm Contact Length
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
D
D2
EXPOSED
PAD
e
E
b
E2
2
1
2
1
K
N
N
NOTE 1
L
BOTTOM VIEW
TOP VIEW
A
A3
A1
Units
MILLIMETERS
NOM
Dimension Limits
MIN
MAX
Number of Pins
N
e
28
Pitch
0.65 BSC
0.90
Overall Height
Standoff
A
0.80
0.00
1.00
0.05
A1
A3
E
0.02
Contact Thickness
Overall Width
0.20 REF
6.00 BSC
3.70
Exposed Pad Width
Overall Length
Exposed Pad Length
Contact Width
Contact Length
Contact-to-Exposed Pad
E2
D
3.65
4.20
6.00 BSC
3.70
D2
b
3.65
0.23
0.50
0.20
4.20
0.35
0.70
–
0.30
L
0.55
K
–
Notes:
1. Pin 1 visual index feature may vary, but must be located within the hatched area.
2. Package is saw singulated.
3. Dimensioning and tolerancing per ASME Y14.5M.
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
REF: Reference Dimension, usually without tolerance, for information purposes only.
Microchip Technology Drawing C04-105B
DS41303B-page 400
Advance Information
© 2007 Microchip Technology Inc.
PIC18F2XK20/4XK20
44-Lead Plastic Quad Flat, No Lead Package (ML) – 8x8 mm Body [QFN]
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
D2
D
EXPOSED
PAD
e
b
K
E
E2
2
1
2
1
N
N
NOTE 1
L
TOP VIEW
BOTTOM VIEW
A
A3
A1
Units
MILLIMETERS
Dimension Limits
MIN
NOM
44
MAX
Number of Pins
N
e
Pitch
0.65 BSC
0.90
Overall Height
Standoff
A
0.80
0.00
1.00
0.05
A1
A3
E
0.02
Contact Thickness
Overall Width
0.20 REF
8.00 BSC
6.45
Exposed Pad Width
Overall Length
Exposed Pad Length
Contact Width
Contact Length
Contact-to-Exposed Pad
E2
D
6.30
6.80
8.00 BSC
6.45
D2
b
6.30
0.25
0.30
0.20
6.80
0.38
0.50
–
0.30
L
0.40
K
–
Notes:
1. Pin 1 visual index feature may vary, but must be located within the hatched area.
2. Package is saw singulated.
3. Dimensioning and tolerancing per ASME Y14.5M.
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
REF: Reference Dimension, usually without tolerance, for information purposes only.
Microchip Technology Drawing C04-103B
© 2007 Microchip Technology Inc.
Advance Information
DS41303B-page 401
PIC18F2XK20/4XK20
44-Lead Plastic Thin Quad Flatpack (PT) – 10x10x1 mm Body, 2.00 mm Footprint [TQFP]
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
D
D1
E
e
E1
N
b
NOTE 1
1 2 3
NOTE 2
α
A
c
φ
A2
β
A1
L
L1
Units
MILLIMETERS
Dimension Limits
MIN
NOM
44
MAX
Number of Leads
Lead Pitch
N
e
0.80 BSC
–
Overall Height
A
–
1.20
1.05
0.15
0.75
Molded Package Thickness
Standoff
A2
A1
L
0.95
0.05
0.45
1.00
–
Foot Length
0.60
Footprint
L1
φ
1.00 REF
3.5°
Foot Angle
0°
7°
Overall Width
E
12.00 BSC
12.00 BSC
10.00 BSC
10.00 BSC
–
Overall Length
D
Molded Package Width
Molded Package Length
Lead Thickness
Lead Width
E1
D1
c
0.09
0.30
11°
0.20
0.45
13°
b
0.37
Mold Draft Angle Top
Mold Draft Angle Bottom
α
β
12°
11°
12°
13°
Notes:
1. Pin 1 visual index feature may vary, but must be located within the hatched area.
2. Chamfers at corners are optional; size may vary.
3. Dimensions D1 and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.25 mm per side.
4. Dimensioning and tolerancing per ASME Y14.5M.
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
REF: Reference Dimension, usually without tolerance, for information purposes only.
Microchip Technology Drawing C04-076B
DS41303B-page 402
Advance Information
© 2007 Microchip Technology Inc.
PIC18F2XK20/4XK20
APPENDIX A: REVISION HISTORY
APPENDIX B: DEVICE
DIFFERENCES
Revision A (JULY 2006)
The differences between the devices listed in this data
sheet are shown in Table B-1.
Original data sheet for PIC18F2XK20/4XK20 devices.
Revision B (03/2007)
Added
part
numbers
PIC18F26K20
and
PIC18F46K20; Replaced Development Support
Section; Replaced Package Drawings.
TABLE B-1:
DEVICE DIFFERENCES
Features
PIC18F23K20 PIC18F24K20 PIC18F25K20 PIC18F26K20 PIC18F43K20 PIC18F44K20 PIC18F45K20 PIC18F46K20
8192
4096
19
16384
8192
19
32768
16384
19
65536
32768
19
8192
4096
20
16384
8192
20
32768
16384
20
65536
32768
20
Program Memory
(Bytes)
Program Memory
(Instructions)
Interrupt Sources
I/O Ports
Ports A, B, C, Ports A, B, C, Ports A, B, C, Ports A, B, C, Ports A, B, C, Ports A, B, C, Ports A, B, C, Ports A, B, C,
(E)
(E)
(E)
(E)
D, E
D, E
D, E
D, E
Capture/Compare/PWM
Modules
1
1
1
1
1
1
1
1
Enhanced
1
1
1
1
1
1
1
1
Capture/Compare/PWM
Modules
Parallel
No
No
No
No
Yes
Yes
Yes
Yes
Communications (PSP)
10-bit Analog-to-Digital
Module
11 input
channels
11 input
channels
11 input
channels
11 input
channels
14 input
channels
14 input
channels
14 input
channels
14 input
channels
Packages
28-pin PDIP
28-pin PDIP
28-pin PDIP
28-pin PDIP
40-pin PDIP
40-pin PDIP
40-pin PDIP
40-pin PDIP
28-pin SOIC 28-pin SOIC 28-pin SOIC 28-pin SOIC 44-pin TQFP 44-pin TQFP 44-pin TQFP 44-pin TQFP
28-pin SSOP 28-pin SSOP 28-pin SSOP 28-pin SSOP 44-pin QFN 44-pin QFN 44-pin QFN 44-pin QFN
28-pin QFN 28-pin QFN 28-pin QFN 28-pin QFN
© 2007 Microchip Technology Inc.
Advance Information
DS41303B-page 403
PIC18F2XK20/4XK20
NOTES:
DS41303B-page 404
Advance Information
© 2007 Microchip Technology Inc.
PIC18F2XK20/4XK20
INDEX
A
B
A/D
Bank Select Register (BSR) .............................................. 69
Baud Rate Generator ...................................................... 210
BAUDCTL Register .......................................................... 234
BC .................................................................................... 307
BCF ................................................................................. 308
BF .................................................................................... 214
BF Status Flag ................................................................. 214
Block Diagrams
Analog Port Pins, Configuring .................................. 261
Associated Registers ............................................... 261
Conversions ............................................................. 252
Converter Characteristics ........................................ 384
Discharge ................................................................. 253
Selecting and Configuring Acquisition Time ............ 250
Special Event Trigger (ECCP) ................................. 164
Absolute Maximum Ratings ............................................. 353
AC (Timing) Characteristics ............................................. 367
Load Conditions for Device Timing Specifications ... 368
Parameter Symbology ............................................. 367
Temperature and Voltage Specifications ................. 368
Timing Conditions .................................................... 368
AC Characteristics
ADC ......................................................................... 249
ADC Transfer Function ............................................ 260
Analog Input Model .......................................... 260, 270
Baud Rate Generator .............................................. 210
Capture Mode Operation ......................................... 154
CCP PWM ............................................................... 157
Clock Source ............................................................. 25
Comparator 1 ........................................................... 264
Comparator 2 ........................................................... 264
Comparator Voltage Reference ............................... 274
Compare Mode Operation ....................................... 155
Crystal Operation ....................................................... 29
EUSART Receive .................................................... 224
EUSART Transmit ................................................... 223
External POR Circuit (Slow VDD Power-up) .............. 51
External RC Mode ..................................................... 30
Fail-Safe Clock Monitor (FSCM) ................................ 38
Generic I/O Port ....................................................... 115
High/Low-Voltage Detect with External Input .......... 278
Interrupt Logic .......................................................... 102
Internal RC Accuracy ............................................... 370
Access Bank
Mapping with Indexed Literal Offset Mode ................. 84
ACKSTAT ........................................................................ 214
ACKSTAT Status Flag ..................................................... 214
ADC ................................................................................. 249
Acquisition Requirements ........................................ 259
Block Diagram .......................................................... 249
Calculating Acquisition Time .................................... 259
Channel Selection .................................................... 250
Configuration ............................................................ 250
Conversion Clock ..................................................... 250
Conversion Procedure ............................................. 254
Internal Sampling Switch (RSS) IMPEDANCE ............. 259
Interrupts .................................................................. 251
Operation ................................................................. 252
Operation During Sleep ........................................... 253
Port Configuration .................................................... 250
Power Management ................................................. 253
Reference Voltage (VREF) ........................................ 250
Result Formatting ..................................................... 251
Source Impedance ................................................... 259
Special Event Trigger ............................................... 253
Starting an A/D Conversion ..................................... 251
ADCON0 Register ............................................................ 255
ADCON1 Register .................................................... 256, 257
ADDFSR .......................................................................... 342
ADDLW ............................................................................ 305
ADDULNK ........................................................................ 342
ADDWF ............................................................................ 305
ADDWFC ......................................................................... 306
ADRESH Register (ADFM = 0) ........................................ 258
ADRESH Register (ADFM = 1) ........................................ 258
ADRESL Register (ADFM = 0) ......................................... 258
ADRESL Register (ADFM = 1) ......................................... 258
Analog Input Connection Considerations ......................... 270
Analog-to-Digital Converter. See ADC
2
MSSP (I C Master Mode) ........................................ 208
2
MSSP (I C Mode) .................................................... 192
MSSP (SPI Mode) ................................................... 183
On-Chip Reset Circuit ................................................ 49
PIC18F2XK20 ............................................................ 12
PIC18F4XK20 ............................................................ 13
PLL (HS Mode) .......................................................... 33
PORTD and PORTE (Parallel Slave Port) ............... 133
PWM (Enhanced) .................................................... 165
Reads from Flash Program Memory ......................... 89
Resonator Operation ................................................. 29
Table Read Operation ............................................... 85
Table Write Operation ............................................... 86
Table Writes to Flash Program Memory .................... 91
Timer0 in 16-Bit Mode ............................................. 137
Timer0 in 8-Bit Mode ............................................... 136
Timer1 ..................................................................... 140
Timer1 (16-Bit Read/Write Mode) ............................ 140
Timer2 ..................................................................... 146
Timer3 ..................................................................... 148
Timer3 (16-Bit Read/Write Mode) ............................ 149
Voltage Reference Output Buffer Example ............. 275
Watchdog Timer ...................................................... 292
BN .................................................................................... 308
BNC ................................................................................. 309
BNN ................................................................................. 309
BNOV .............................................................................. 310
BNZ ................................................................................. 310
BOR. See Brown-out Reset.
ANDLW ............................................................................ 306
ANDWF ............................................................................ 307
ANSEL (PORT Analog Control) ....................................... 130
ANSEL Register ............................................................... 130
ANSELH Register ............................................................ 131
Assembler
BOV ................................................................................. 313
BRA ................................................................................. 311
Break Character (12-bit) Transmit and Receive .............. 241
BRG. See Baud Rate Generator.
MPASM Assembler .................................................. 350
Brown-out Reset (BOR) ..................................................... 52
© 2007 Microchip Technology Inc.
Advance Information
DS41303B-page 405
PIC18F2XK20/4XK20
Detecting ....................................................................52
Disabling in Sleep Mode ............................................52
Software Enabled .......................................................52
BSF ..................................................................................311
BTFSC .............................................................................312
BTFSS ..............................................................................312
BTG ..................................................................................313
BZ .....................................................................................314
CM1CON0 Register ......................................................... 268
CM2CON0 Register ......................................................... 269
CM2CON1 Register ......................................................... 271
Code Examples
16 x 16 Signed Multiply Routine .............................. 100
16 x 16 Unsigned Multiply Routine .......................... 100
8 x 8 Signed Multiply Routine .................................... 99
8 x 8 Unsigned Multiply Routine ................................ 99
A/D Conversion ........................................................ 254
Changing Between Capture Prescalers ................... 153
Clearing RAM Using Indirect Addressing .................. 80
Computed GOTO Using an Offset Value ................... 66
Data EEPROM Read ................................................. 97
Data EEPROM Refresh Routine ................................ 98
Data EEPROM Write ................................................. 97
Erasing a Flash Program Memory Row ..................... 90
Fast Register Stack ................................................... 66
Implementing a Timer1 Real-Time Clock ................ 143
Initializing PORTA .................................................... 115
Initializing PORTB .................................................... 118
Initializing PORTC ................................................... 121
Initializing PORTD ................................................... 124
Initializing PORTE .................................................... 127
Loading the SSPBUF (SSPSR) Register ................. 186
Reading a Flash Program Memory Word .................. 89
Saving Status, WREG and BSR Registers in RAM . 113
Writing to Flash Program Memory ....................... 92–93
Code Protection ............................................................... 283
COMF .............................................................................. 316
Comparator
C
C Compilers
MPLAB C18 .............................................................350
MPLAB C30 .............................................................350
CALL ................................................................................314
CALLW .............................................................................343
Capture (CCP Module) .....................................................153
Associated Registers ...............................................156
CCP Pin Configuration .............................................153
CCPRxH:CCPRxL Registers ...................................153
Prescaler ..................................................................153
Software Interrupt ....................................................153
Timer1/Timer3 Mode Selection ................................153
Capture (ECCP Module) ..................................................164
Capture/Compare/PWM (CCP) ........................................151
Capture Mode. See Capture.
CCP Mode and Timer Resources ............................152
CCPRxH Register ....................................................152
CCPRxL Register .....................................................152
Compare Mode. See Compare.
Interaction of Two CCP Modules .............................152
Module Configuration ...............................................152
PWM Mode ..............................................................157
Duty Cycle ........................................................158
Effects of Reset ................................................160
Example PWM Frequencies & Resolutions
Associated Registers ............................................... 272
Operation ................................................................. 263
Operation During Sleep ........................................... 267
Response Time ........................................................ 265
Comparator Module ......................................................... 263
C1 Output State Versus Input Conditions ................ 265
Comparator Specifications ............................................... 365
Comparator Voltage Reference (CVREF)
Fosc=20 MHZ ..........................................159
Fosc=40 MHZ ..........................................159
Fosc=8 MHZ ............................................159
Operation in Sleep Mode .................................160
Setup for Operation ..........................................160
System Clock Frequency Changes ..................160
PWM Period .............................................................158
Setup for PWM Operation ........................................160
CCP1CON Register .........................................................163
CCP2CON Register .........................................................151
Clock Accuracy with Asynchronous Operation ................232
Clock Sources
Associated registers ...................................................39
External Modes ..........................................................28
EC ......................................................................28
HS ......................................................................29
LP .......................................................................29
OST ....................................................................28
RC ......................................................................30
XT ......................................................................29
Internal Modes ...........................................................30
Frequency Selection ..........................................32
HFINTOSC .........................................................30
INTOSC .............................................................30
INTOSCIO ..........................................................30
LFINTOSC .........................................................32
Selecting the 31 kHz Source ......................................26
Selection Using OSCCON Register ...........................26
Clock Switching ..................................................................35
CLRF ................................................................................315
CLRWDT ..........................................................................315
Response Time ........................................................ 265
Comparator Voltage Reference (CVREF)
Associated Registers ............................................... 276
Effects of a Reset ............................................ 267, 273
Operation During Sleep ........................................... 273
Overview .................................................................. 273
Comparators
Effects of a Reset .................................................... 267
Compare (CCP Module) .................................................. 155
Associated Registers ............................................... 156
CCPRx Register ...................................................... 155
Pin Configuration ..................................................... 155
Software Interrupt .................................................... 155
Special Event Trigger ...................................... 150, 155
Timer1/Timer3 Mode Selection ................................ 155
Compare (ECCP Module) ................................................ 164
Special Event Trigger .............................................. 164
Computed GOTO ............................................................... 66
CONFIG1H Register ........................................................ 285
CONFIG2H Register ........................................................ 286
CONFIG2L Register ........................................................ 286
CONFIG3H Register ........................................................ 287
CONFIG4L Register ........................................................ 287
CONFIG5H Register ........................................................ 288
CONFIG5L Register ........................................................ 288
CONFIG6H Register ........................................................ 289
CONFIG6L Register ........................................................ 289
DS41303B-page 406
Advance Information
© 2007 Microchip Technology Inc.
PIC18F2XK20/4XK20
CONFIG7H Register ........................................................ 290
CONFIG7L Register ......................................................... 290
Configuration Bits ............................................................. 284
Configuration Register Protection .................................... 297
Context Saving During Interrupts ..................................... 113
CPFSEQ .......................................................................... 316
CPFSGT .......................................................................... 317
CPFSLT ........................................................................... 317
Customer Change Notification Service ............................ 409
Customer Notification Service .......................................... 409
Customer Support ............................................................ 409
CVREF Voltage Reference Specifications ........................ 365
Device Reset Timers ......................................................... 53
Oscillator Start-up Timer (OST) ................................. 53
PLL Lock Time-out .................................................... 53
Power-up Timer (PWRT) ........................................... 53
Time-out Sequence ................................................... 53
DEVID1 Register ............................................................. 291
DEVID2 Register ............................................................. 291
Direct Addressing .............................................................. 81
E
ECCPAS Register ............................................................ 173
EECON1 Register ........................................................ 87, 96
Effect on Standard PIC Instructions ................................. 346
Effects of Power Managed Modes on Various
D
Data Addressing Modes ..................................................... 80
Comparing Addressing Modes with the
Clock Sources ........................................................... 34
Effects of Reset
Extended Instruction Set Enabled ..................... 83
Direct .......................................................................... 80
Indexed Literal Offset ................................................. 82
Instructions Affected .......................................... 82
Indirect ....................................................................... 80
Inherent and Literal .................................................... 80
Data EEPROM
PWM mode .............................................................. 160
Electrical Characteristics ................................................. 353
Enhanced Capture/Compare/PWM (ECCP) .................... 163
Associated Registers ............................................... 181
Capture and Compare Modes ................................. 164
Capture Mode. See Capture (ECCP Module).
Enhanced PWM Mode ............................................. 165
Auto-Restart .................................................... 174
Auto-shutdown ................................................ 173
Direction Change in Full-Bridge Output Mode . 171
Full-Bridge Application ..................................... 169
Full-Bridge Mode ............................................. 169
Half-Bridge Application .................................... 168
Half-Bridge Application Examples ................... 175
Half-Bridge Mode ............................................. 168
Output Relationships (Active-High and
Code Protection ....................................................... 297
Data EEPROM Memory ..................................................... 95
Associated Registers ................................................. 98
EEADR Register ........................................................ 95
EECON1 and EECON2 Registers ............................. 95
Operation During Code-Protect ................................. 98
Protection Against Spurious Write ............................. 98
Reading ...................................................................... 97
Using .......................................................................... 98
Write Verify ................................................................ 97
Writing ........................................................................ 97
Data Memory ..................................................................... 69
Access Bank .............................................................. 74
and the Extended Instruction Set ............................... 82
Bank Select Register (BSR) ....................................... 69
General Purpose Registers ........................................ 74
Map for PIC18F23K20/43K20 .................................... 70
Map for PIC18F24K20/44K20 .................................... 71
Map for PIC18F25K20/45K20 .................................... 72
Special Function Registers ........................................ 74
DAW ................................................................................. 318
DC and AC Characteristics
Active-Low) .............................................. 166
Output Relationships Diagram ......................... 167
Programmable Dead Band Delay .................... 175
Shoot-through Current ..................................... 175
Start-up Considerations ................................... 172
Outputs and Configuration ....................................... 164
Standard PWM Mode .............................................. 164
Timer Resources ..................................................... 164
Enhanced Universal Synchronous Asynchronous
Receiver Transmitter (EUSART) ............................. 223
Errata ................................................................................... 8
EUSART .......................................................................... 223
Asynchronous Mode ................................................ 225
12-bit Break Transmit and Receive ................. 241
Associated Registers, Receive ........................ 231
Associated Registers, Transmit ....................... 227
Auto-Wake-up on Break .................................. 240
Baud Rate Generator (BRG) ........................... 235
Clock Accuracy ................................................ 232
Receiver .......................................................... 228
Setting up 9-bit Mode with Address Detect ..... 230
Transmitter ...................................................... 225
Baud Rate Generator (BRG)
Graphs and Tables .................................................. 387
DC Characteristics
Input/Output ............................................................. 362
Peripheral Supply Current ........................................ 361
Power-Down Current ............................................... 355
Primary Idle Supply Current ..................................... 359
Primary Run Supply Current .................................... 358
RC Idle Supply Current ............................................ 357
RC Run Supply Current ........................................... 356
Secondary Oscillator Supply Current ....................... 360
Supply Voltage ......................................................... 355
DCFSNZ .......................................................................... 319
DECF ............................................................................... 318
DECFSZ ........................................................................... 319
Development Support ...................................................... 349
Device Differences ........................................................... 397
Device Overview .................................................................. 9
Details on Individual Family Members ....................... 10
Features (table) .......................................................... 11
New Core Features ...................................................... 9
Other Special Features .............................................. 10
Associated Registers ....................................... 235
Auto Baud Rate Detect .................................... 239
Baud Rate Error, Calculating ........................... 235
Baud Rates, Asynchronous Modes ................. 236
Formulas .......................................................... 235
High Baud Rate Select (BRGH Bit) ................. 235
Clock polarity
Synchronous Mode .......................................... 243
Data polarity
Asychronous Receive ...................................... 228
Asychronous Transmit ..................................... 225
© 2007 Microchip Technology Inc.
Advance Information
DS41303B-page 407
PIC18F2XK20/4XK20
Synchronous Mode ..........................................243
Interrupts
Characteristics ......................................................... 366
Current Consumption ............................................... 279
Effects of a Reset .................................................... 281
Operation ................................................................. 278
During Sleep .................................................... 281
Asychronous Receive ......................................229
Asychronous Transmit .....................................225
Synchronous Master Mode .............................. 243, 247
Associated Registers, Receive ........................246
Associated Registers, Transmit ............... 244, 247
Reception .........................................................245
Transmission ....................................................243
Synchronous Slave Mode
Setup ....................................................................... 279
Start-up Time ........................................................... 279
Typical Application ................................................... 281
HLVD. See High/Low-Voltage Detect. ............................. 277
HLVDCON Register ......................................................... 277
Associated Registers, Receive ........................248
Reception .........................................................248
Transmission ....................................................247
Extended Instruction Set
I
I/O Ports ........................................................................... 115
2
I C Mode (MSSP)
Acknowledge Sequence Timing .............................. 217
Baud Rate Generator .............................................. 210
Bus Collision
ADDFSR ..................................................................342
ADDULNK ................................................................342
and Using MPLAB Tools ..........................................348
CALLW .....................................................................343
Considerations for Use ............................................346
MOVSF ....................................................................343
MOVSS ....................................................................344
PUSHL .....................................................................344
SUBFSR ..................................................................345
SUBULNK ................................................................345
Syntax ......................................................................341
During a Repeated Start Condition .................. 221
During a Stop Condition .................................. 222
Clock Arbitration ...................................................... 211
Clock Stretching ....................................................... 203
10-Bit Slave Receive Mode (SEN = 1) ............ 203
10-Bit Slave Transmit Mode ............................ 203
7-Bit Slave Receive Mode (SEN = 1) .............. 203
7-Bit Slave Transmit Mode .............................. 203
Clock Synchronization and the CKP bit (SEN = 1) .. 204
Effects of a Reset .................................................... 218
General Call Address Support ................................. 207
F
Fail-Safe Clock Monitor .............................................. 38, 283
Fail-Safe Condition Clearing ......................................38
Fail-Safe Detection ....................................................38
Fail-Safe Operation ....................................................38
Reset or Wake-up from Sleep ....................................38
Fast Register Stack ............................................................66
Firmware Instructions .......................................................299
Flash Program Memory ......................................................85
Associated Registers .................................................93
Control Registers .......................................................86
EECON1 and EECON2 .....................................86
TABLAT (Table Latch) Register .........................88
TBLPTR (Table Pointer) Register ......................88
Erase Sequence ........................................................90
Erasing .......................................................................90
Operation During Code-Protect .................................93
Reading ......................................................................89
Table Pointer
2
I C Clock Rate w/BRG ............................................. 210
Master Mode ............................................................ 208
Operation ......................................................... 209
Reception ........................................................ 214
Repeated Start Condition Timing .................... 213
Start Condition Timing ..................................... 212
Transmission ................................................... 214
Multi-Master Communication, Bus Collision
and Arbitration ................................................. 218
Multi-Master Mode ................................................... 218
Operation ................................................................. 196
Read/Write Bit Information (R/W Bit) ............... 196, 197
Registers ................................................................. 192
Serial Clock (RC3/SCK/SCL) ................................... 197
Slave Mode .............................................................. 196
Addressing ....................................................... 196
Reception ........................................................ 197
Transmission ................................................... 197
Sleep Operation ....................................................... 218
Stop Condition Timing ............................................. 217
ID Locations ............................................................. 283, 297
INCF ................................................................................ 320
INCFSZ ............................................................................ 321
In-Circuit Debugger .......................................................... 297
In-Circuit Serial Programming (ICSP) ...................... 283, 297
Indexed Literal Offset Addressing
and Standard PIC18 Instructions ............................. 346
Indexed Literal Offset Mode ............................................. 346
Indirect Addressing ............................................................ 81
INFSNZ ............................................................................ 321
Initialization Conditions for all Registers ...................... 57–60
Instruction Cycle ................................................................ 67
Clocking Scheme ....................................................... 67
Instruction Flow/Pipelining ................................................. 67
Instruction Set .................................................................. 299
ADDLW .................................................................... 305
ADDWF .................................................................... 305
ADDWF (Indexed Literal Offset Mode) .................... 347
Boundaries Based on Operation ........................88
Table Pointer Boundaries ..........................................88
Table Reads and Table Writes ..................................85
Write Sequence .........................................................91
Writing To ...................................................................91
Protection Against Spurious Writes ...................93
Unexpected Termination ....................................93
Write Verify ........................................................93
G
General Call Address Support .........................................207
GOTO ...............................................................................320
H
Hardware Multiplier ............................................................99
Introduction ................................................................99
Operation ...................................................................99
Performance Comparison ..........................................99
High/Low-Voltage Detect .................................................277
Applications ..............................................................281
Associated Registers ...............................................281
DS41303B-page 408
Advance Information
© 2007 Microchip Technology Inc.
PIC18F2XK20/4XK20
ADDWFC ................................................................. 306
ANDLW .................................................................... 306
ANDWF .................................................................... 307
BC ............................................................................ 307
BCF .......................................................................... 308
BN ............................................................................ 308
BNC ......................................................................... 309
BNN ......................................................................... 309
BNOV ....................................................................... 310
BNZ .......................................................................... 310
BOV ......................................................................... 313
BRA .......................................................................... 311
BSF .......................................................................... 311
BSF (Indexed Literal Offset Mode) .......................... 347
BTFSC ..................................................................... 312
BTFSS ..................................................................... 312
BTG .......................................................................... 313
BZ ............................................................................ 314
CALL ........................................................................ 314
CLRF ........................................................................ 315
CLRWDT .................................................................. 315
COMF ...................................................................... 316
CPFSEQ .................................................................. 316
CPFSGT .................................................................. 317
CPFSLT ................................................................... 317
DAW ......................................................................... 318
DCFSNZ .................................................................. 319
DECF ....................................................................... 318
DECFSZ ................................................................... 319
Extended Instruction Set .......................................... 341
General Format ........................................................ 301
GOTO ...................................................................... 320
INCF ......................................................................... 320
INCFSZ .................................................................... 321
INFSNZ .................................................................... 321
IORLW ..................................................................... 322
IORWF ..................................................................... 322
LFSR ........................................................................ 323
MOVF ....................................................................... 323
MOVFF .................................................................... 324
MOVLB .................................................................... 324
MOVLW ................................................................... 325
MOVWF ................................................................... 325
MULLW .................................................................... 326
MULWF .................................................................... 326
NEGF ....................................................................... 327
NOP ......................................................................... 327
Opcode Field Descriptions ....................................... 300
POP ......................................................................... 328
PUSH ....................................................................... 328
RCALL ..................................................................... 329
RESET ..................................................................... 329
RETFIE .................................................................... 330
RETLW .................................................................... 330
RETURN .................................................................. 331
RLCF ........................................................................ 331
RLNCF ..................................................................... 332
RRCF ....................................................................... 332
RRNCF .................................................................... 333
SETF ........................................................................ 333
SETF (Indexed Literal Offset Mode) ........................ 347
SLEEP ..................................................................... 334
SUBFWB .................................................................. 334
SUBLW .................................................................... 335
SUBWF .................................................................... 335
SUBWFB ................................................................. 336
SWAPF .................................................................... 336
TBLRD ..................................................................... 337
TBLWT .................................................................... 338
TSTFSZ ................................................................... 339
XORLW ................................................................... 339
XORWF ................................................................... 340
INTCON Register ............................................................. 103
INTCON Registers ................................................... 103–105
INTCON2 Register ........................................................... 104
INTCON3 Register ........................................................... 105
Inter-Integrated Circuit. See I C.
Internal Oscillator Block
HFINTOSC Frequency Drift ....................................... 32
PLL in HFINTOSC Modes ......................................... 33
Internal RC Oscillator
Use with WDT .......................................................... 292
Internal Sampling Switch (RSS) IMPEDANCE ..................... 259
Internet Address .............................................................. 409
Interrupt Sources ............................................................. 283
ADC ......................................................................... 251
Capture Complete (CCP) ........................................ 153
Compare Complete (CCP) ...................................... 155
Interrupt-on-Change (RB7:RB4) .............................. 118
INTn Pin ................................................................... 113
PORTB, Interrupt-on-Change .................................. 113
TMR0 ....................................................................... 113
TMR0 Overflow ........................................................ 137
TMR1 Overflow ........................................................ 139
TMR3 Overflow ................................................ 147, 149
Interrupts ......................................................................... 101
IORLW ............................................................................. 322
IORWF ............................................................................. 322
IPR Registers ................................................................... 110
IPR1 Register .................................................................. 110
IPR2 Register .................................................................. 111
2
L
LFSR ............................................................................... 323
Low-Voltage ICSP Programming. See Single-Supply
ICSP Programming
M
Master Clear (MCLR) ......................................................... 51
Master Synchronous Serial Port (MSSP). See MSSP.
Memory Organization ........................................................ 63
Data Memory ............................................................. 69
Program Memory ....................................................... 63
Microchip Internet Web Site ............................................. 409
MOVF .............................................................................. 323
MOVFF ............................................................................ 324
MOVLB ............................................................................ 324
MOVLW ........................................................................... 325
MOVSF ............................................................................ 343
MOVSS ............................................................................ 344
MOVWF ........................................................................... 325
MPLAB ASM30 Assembler, Linker, Librarian .................. 350
MPLAB ICD 2 In-Circuit Debugger .................................. 351
MPLAB ICE 2000 High-Performance Universal
In-Circuit Emulator ................................................... 351
MPLAB ICE 4000 High-Performance Universal
In-Circuit Emulator ................................................... 351
MPLAB Integrated Development Environment Software . 349
MPLAB PM3 Device Programmer ................................... 351
MPLINK Object Linker/MPLIB Object Librarian ............... 350
MSSP
© 2007 Microchip Technology Inc.
Advance Information
DS41303B-page 409
PIC18F2XK20/4XK20
ACK Pulse ........................................................ 196, 197
Control Registers (general) ......................................183
I C Mode. See I C Mode.
Module Overview .....................................................183
SPI Master/Slave Connection ..................................187
SPI Mode. See SPI Mode.
RA4/T0CKI/C1OUT ............................................. 15, 19
RA5/AN4/SS/HLVDIN/C2OUT ............................. 15, 19
RB0/INT0/FLT0/AN12 .......................................... 16, 20
RB1/INT1/AN10/C12IN2- ........................................... 20
RB1/INT1/AN10/P1C/C12IN2- ................................... 16
RB2/INT2/AN8 ........................................................... 20
RB2/INT2/AN8/P1B ................................................... 16
RB3/AN9/CCP2/C12IN3- ..................................... 16, 20
RB4/KBI0/AN11 ......................................................... 20
RB4/KBI0/AN11/P1D ................................................. 16
RB5/KBI1/PGM .................................................... 16, 20
RB6/KBI2/PGC .................................................... 16, 20
RB7/KBI3/PGD .................................................... 16, 20
RC0/T1OSO/T13CKI ........................................... 17, 21
RC1/T1OSI/CCP2 ................................................ 17, 21
RC2/CCP1/P1A ................................................... 17, 21
RC3/SCK/SCL ..................................................... 17, 21
RC4/SDI/SDA ...................................................... 17, 21
RC5/SDO ............................................................. 17, 21
RC6/TX/CK .......................................................... 17, 21
RC7/RX/DT .......................................................... 17, 21
RD0/PSP0 ................................................................. 22
RD1/PSP1 ................................................................. 22
RD2/PSP2 ................................................................. 22
RD3/PSP3 ................................................................. 22
RD4/PSP4 ................................................................. 22
RD5/PSP5/P1B ......................................................... 22
RD6/PSP6/P1C ......................................................... 22
RD7/PSP7/P1D ......................................................... 22
RE0/RD/AN5 .............................................................. 23
RE1/WR/AN6 ............................................................. 23
RE2/CS/AN7 .............................................................. 23
VDD ...................................................................... 17, 23
VSS ...................................................................... 17, 23
Pinout I/O Descriptions
2
2
SSPBUF Register ....................................................188
SSPSR Register ......................................................188
MULLW ............................................................................326
MULWF ............................................................................326
N
NEGF ...............................................................................327
NOP .................................................................................327
O
OSCCON Register .............................................................27
Oscillator Configuration
EC ..............................................................................25
ECIO ..........................................................................25
HS ..............................................................................25
HSPLL ........................................................................25
INTOSC .....................................................................25
INTOSCIO ..................................................................25
LP ...............................................................................25
RC ..............................................................................25
RCIO ..........................................................................25
XT ..............................................................................25
Oscillator Module ...............................................................25
HFINTOSC .................................................................25
LFINTOSC .................................................................25
Oscillator Selection ..........................................................283
Oscillator Start-up Timer (OST) ................................... 34, 53
Oscillator Switching
Fail-Safe Clock Monitor ..............................................38
Two-Speed Clock Start-up .........................................35
Oscillator Transitions ..........................................................26
Oscillator, Timer1 ..................................................... 139, 149
Oscillator, Timer3 .............................................................147
OSCTUNE Register ...........................................................31
PIC18F2XK20 ............................................................ 14
PIC18F4XK20 ............................................................ 18
PIR Registers ................................................................... 106
PIR1 Register .................................................................. 106
PIR2 Register .................................................................. 107
PLL Frequency Multiplier ................................................... 33
HSPLL Oscillator Mode ............................................. 33
POP ................................................................................. 328
POR. See Power-on Reset.
P
P1A/P1B/P1C/P1D.See Enhanced
Capture/Compare/PWM (ECCP) .............................165
Packaging Information .....................................................389
Marking ....................................................................389
Parallel Slave Port (PSP) .........................................124, 133
Associated Registers ...............................................134
CS (Chip Select) ......................................................133
PORTD ....................................................................133
RD (Read Input) .......................................................133
Select (PSPMODE Bit) .................................... 124, 133
WR (Write Input) ......................................................133
PICSTART Plus Development Programmer ....................352
PIE Registers ...................................................................108
PIE1 Register ...................................................................108
PIE2 Register ...................................................................109
Pin Functions
PORTA
Associated Registers ............................................... 117
LATA Register ......................................................... 115
PORTA Register ...................................................... 115
TRISA Register ........................................................ 115
PORTB
Associated Registers ............................................... 120
LATB Register ......................................................... 118
PORTB Register ...................................................... 118
TRISB Register ........................................................ 118
PORTC
Associated Registers ............................................... 123
LATC Register ......................................................... 121
PORTC Register ...................................................... 121
RC3/SCK/SCL Pin ................................................... 197
TRISC Register ........................................................ 121
PORTD
MCLR/VPP/RE3 .................................................... 14, 18
OSC1/CLKI/RA7 .................................................. 14, 18
OSC2/CLKO/RA6 ................................................ 14, 18
RA0/AN0/C12IN0- ................................................ 15, 19
RA1/AN1/C12IN0- ......................................................19
RA1/AN1/C12IN1- ......................................................15
RA2/AN2/VREF-/CVREF/C2IN+ ............................. 15, 19
RA3/AN3/VREF+/C1IN+ ........................................ 15, 19
Associated Registers ............................................... 126
LATD Register ......................................................... 124
Parallel Slave Port (PSP) Function .......................... 124
PORTD Register ...................................................... 124
DS41303B-page 410
Advance Information
© 2007 Microchip Technology Inc.
PIC18F2XK20/4XK20
TRISD Register ........................................................ 124
PORTE
Operation with Fail-Safe Clock Monitor ................... 180
Pulse Steering ......................................................... 177
Steering Synchronization ......................................... 179
PWM Mode. See Enhanced Capture/Compare/PWM ..... 165
PWM1CON Register ........................................................ 176
Associated Registers ............................................... 129
LATE Register .......................................................... 127
PORTE Register ...................................................... 127
PSP Mode Select (PSPMODE Bit) .......................... 124
TRISE Register ........................................................ 127
Power Managed Modes ..................................................... 41
and A/D Operation ................................................... 253
and PWM Operation ................................................ 180
and SPI Operation ................................................... 191
Clock Transitions and Status Indicators ..................... 42
Effects on Clock Sources ........................................... 34
Entering ...................................................................... 41
Exiting Idle and Sleep Modes .................................... 46
by Interrupt ......................................................... 46
by Reset ............................................................. 46
by WDT Time-out ............................................... 46
Without a Start-up Delay .................................... 47
Idle Modes ................................................................. 43
PRI_IDLE ........................................................... 45
RC_IDLE ............................................................ 46
SEC_IDLE ......................................................... 45
Multiple Sleep Functions ............................................ 42
Run Modes ................................................................. 42
PRI_RUN ........................................................... 42
RC_RUN ............................................................ 43
SEC_RUN .......................................................... 42
Selecting .................................................................... 41
Sleep Mode ................................................................ 43
Summary (table) ........................................................ 41
Power-on Reset (POR) ...................................................... 51
Power-up Timer (PWRT) ........................................... 53
Time-out Sequence .................................................... 53
Power-up Delays ................................................................ 34
Power-up Timer (PWRT) ................................................... 34
Prescaler, Timer0 ............................................................. 137
PRI_IDLE Mode ................................................................. 45
PRI_RUN Mode ................................................................. 42
Program Counter ............................................................... 64
PCL, PCH and PCU Registers ................................... 64
PCLATH and PCLATU Registers .............................. 64
Program Memory
and Extended Instruction Set ..................................... 84
Code Protection ....................................................... 295
Instructions ................................................................. 68
Two-Word .......................................................... 68
Interrupt Vector .......................................................... 63
Look-up Tables .......................................................... 66
Map and Stack (diagram) ........................................... 63
Reset Vector .............................................................. 63
Program Verification and Code Protection ....................... 294
Associated Registers ............................................... 294
Programming, Device Instructions ................................... 299
PSP. See Parallel Slave Port.
PSTRCON Register ......................................................... 177
Pulse Steering .................................................................. 177
PUSH ............................................................................... 328
PUSH and POP Instructions .............................................. 65
PUSHL ............................................................................. 344
PWM (CCP Module)
R
RAM. See Data Memory.
RC_IDLE Mode .................................................................. 46
RC_RUN Mode .................................................................. 43
RCALL ............................................................................. 329
RCON Register .......................................................... 50, 112
Bit Status During Initialization .................................... 56
RCREG ............................................................................ 230
RCSTA Register .............................................................. 233
Reader Response ............................................................ 410
Register
RCREG Register ..................................................... 239
Register File ....................................................................... 74
Register File Summary ................................................ 76–78
Registers
ADCON0 (ADC Control 0) ....................................... 255
ADCON1 (ADC Control 1) ............................... 256, 257
ADRESH (ADC Result High) with ADFM = 0) ......... 258
ADRESH (ADC Result High) with ADFM = 1) ......... 258
ADRESL (ADC Result Low) with ADFM = 0) ........... 258
ADRESL (ADC Result Low) with ADFM = 1) ........... 258
ANSEL (Analog Select 1) ........................................ 130
ANSEL (PORT Analog Control) ............................... 130
ANSELH (Analog Select 2) ...................................... 131
ANSELH (PORT Analog Control) ............................ 131
BAUDCTL (Baud Rate Control) ............................... 234
BAUDCTL (EUSART Baud Rate Control) ............... 234
CCP1CON (Enhanced Capture/Compare/PWM
Control) ............................................................ 163
CCP2CON (Standard Capture/Compare/
PWM Control) .................................................. 151
CM1CON0 (C1 Control) .......................................... 268
CM2CON0 (C2 Control) .......................................... 269
CM2CON1 (C2 Control) .......................................... 271
CONFIG1H (Configuration 1 High) .......................... 285
CONFIG2H (Configuration 2 High) .......................... 286
CONFIG2L (Configuration 2 Low) ........................... 286
CONFIG3H (Configuration 3 High) .......................... 287
CONFIG4L (Configuration 4 Low) ........................... 287
CONFIG5H (Configuration 5 High) .......................... 288
CONFIG5L (Configuration 5 Low) ........................... 288
CONFIG6H (Configuration 6 High) .......................... 289
CONFIG6L (Configuration 6 Low) ........................... 289
CONFIG7H (Configuration 7 High) .......................... 290
CONFIG7L (Configuration 7 Low) ........................... 290
CVRCON (Comparator Voltage Reference Control)
CVRCON Register ........................................... 275
CVRCON2 (Comparator Voltage Reference Control 2)
CVRCON2 Register ......................................... 276
DEVID1 (Device ID 1) .............................................. 291
DEVID2 (Device ID 2) .............................................. 291
ECCPAS (Enhanced CCP Auto-shutdown Control) 173
EECON1 (Data EEPROM Control 1) ................... 87, 96
HLVDCON (High/Low-Voltage Detect Control) ....... 277
INTCON (Interrupt Control) ..................................... 103
INTCON2 (Interrupt Control 2) ................................ 104
INTCON3 (Interrupt Control 3) ................................ 105
IPR1 (Peripheral Interrupt Priority 1) ....................... 110
IPR2 (Peripheral Interrupt Priority 2) ....................... 111
OSCCON (Oscillator Control) .................................... 27
Associated Registers ............................................... 161
PWM (ECCP Module)
Effects of a Reset ..................................................... 180
Operation in Power Managed Modes ...................... 180
© 2007 Microchip Technology Inc.
Advance Information
DS41303B-page 411
PIC18F2XK20/4XK20
OSCTUNE (Oscillator Tuning) ...................................31
PIE1 (Peripheral Interrupt Enable 1) ........................108
PIE2 (Peripheral Interrupt Enable 2) ........................109
PIR1 (Peripheral Interrupt Request 1) .....................106
PIR2 (Peripheral Interrupt Request 2) .....................107
PSTRCON (Pulse Steering Control) ........................177
PWM1CON (Enhanced PWM Control) ....................176
RCON (Reset Control) ....................................... 50, 112
RCON (Reset control) ..............................................112
RCSTA (Receive Status and Control) ......................233
SLRCON (PORT Slew Rate Control) .......................132
Special Event Trigger ...................................................... 253
Special Event Trigger. See Compare (ECCP Mode).
Special Event Trigger. See Compare (ECCP Module).
Special Features of the CPU ........................................... 283
Special Function Registers ................................................ 74
Map ............................................................................ 75
SPI Mode (MSSP)
Associated Registers ............................................... 191
Bus Mode Compatibility ........................................... 191
Effects of a Reset .................................................... 191
Enabling SPI I/O ...................................................... 187
Master Mode ............................................................ 188
Master/Slave Connection ......................................... 187
Operation ................................................................. 186
Operation in Power Managed Modes ...................... 191
Serial Clock .............................................................. 183
Serial Data In ........................................................... 183
Serial Data Out ........................................................ 183
Slave Mode .............................................................. 189
Slave Select ............................................................. 183
Slave Select Synchronization .................................. 189
SPI Clock ................................................................. 188
Typical Connection .................................................. 187
SS .................................................................................... 183
SSPCON1 Register ................................................. 185, 194
SSPCON2 Register ......................................................... 195
SSPMSK Register ........................................................... 202
SSPOV ............................................................................ 214
SSPOV Status Flag ......................................................... 214
SSPSTAT Register .................................................. 184, 193
R/W Bit ............................................................ 196, 197
Stack Full/Underflow Resets .............................................. 66
Standard Instructions ....................................................... 299
STATUS Register .............................................................. 79
STKPTR Register .............................................................. 65
SUBFSR .......................................................................... 345
SUBFWB ......................................................................... 334
SUBLW ............................................................................ 335
SUBULNK ........................................................................ 345
SUBWF ............................................................................ 335
SUBWFB ......................................................................... 336
SWAPF ............................................................................ 336
2
SSPCON1 (MSSP Control 1, I C Mode) .................194
SSPCON1 (MSSP Control 1, SPI Mode) .................185
2
SSPCON2 (MSSP Control 2, I C Mode) .................195
SSPMSK (SSP Mask) ..............................................202
SSPSTAT (MSSP Status, SPI Mode) .............. 184, 193
STATUS .....................................................................79
STKPTR (Stack Pointer) ............................................65
T0CON (Timer0 Control) ..........................................135
T1CON (Timer1 Control) ..........................................139
T2CON (Timer2 Control) ..........................................145
T3CON (Timer3 Control) ..........................................147
TRISE (PORTE/PSP Control) ..................................128
TXSTA (Transmit Status and Control) .....................232
WDTCON (Watchdog Timer Control) .......................293
RESET .............................................................................329
Reset State of Registers ....................................................56
Resets ........................................................................ 49, 283
Brown-out Reset (BOR) ...........................................283
Oscillator Start-up Timer (OST) ...............................283
Power-on Reset (POR) ............................................283
Power-up Timer (PWRT) .........................................283
RETFIE ............................................................................330
RETLW .............................................................................330
RETURN ..........................................................................331
Return Address Stack ........................................................64
Return Stack Pointer (STKPTR) ........................................65
Revision History ...............................................................397
RLCF ................................................................................331
RLNCF .............................................................................332
RRCF ...............................................................................332
RRNCF .............................................................................333
S
T
SCK ..................................................................................183
SDI ...................................................................................183
SDO .................................................................................183
SEC_IDLE Mode ................................................................45
SEC_RUN Mode ................................................................42
Serial Clock, SCK .............................................................183
Serial Data In (SDI) ..........................................................183
Serial Data Out (SDO) .....................................................183
Serial Peripheral Interface. See SPI Mode.
SETF ................................................................................333
Shoot-through Current .....................................................175
Single-Supply ICSP Programming.
Slave Select (SS) .............................................................183
Slave Select Synchronization ...........................................189
SLEEP ..............................................................................334
Sleep
T0CON Register .............................................................. 135
T1CON Register .............................................................. 139
T2CON Register .............................................................. 145
T3CON Register .............................................................. 147
Table Pointer Operations (table) ........................................ 88
Table Reads/Table Writes ................................................. 66
TBLRD ............................................................................. 337
TBLWT ............................................................................. 338
Time-out in Various Situations (table) ................................ 53
Timer0 .............................................................................. 135
Associated Registers ............................................... 137
Operation ................................................................. 136
Overflow Interrupt .................................................... 137
Prescaler ................................................................. 137
Prescaler Assignment (PSA Bit) .............................. 137
Prescaler Select (T0PS2:T0PS0 Bits) ..................... 137
Prescaler. See Prescaler, Timer0.
OSC1 and OSC2 Pin States ......................................34
Sleep Mode ........................................................................43
SLRCON Register ............................................................132
Software Simulator (MPLAB SIM) ....................................350
SPBRG .............................................................................235
SPBRGH ..........................................................................235
Reads and Writes in 16-Bit Mode ............................ 136
Source Edge Select (T0SE Bit) ............................... 136
Source Select (T0CS Bit) ......................................... 136
Switching Prescaler Assignment ............................. 137
DS41303B-page 412
Advance Information
© 2007 Microchip Technology Inc.
PIC18F2XK20/4XK20
Timer1 .............................................................................. 139
16-Bit Read/Write Mode ........................................... 141
Associated Registers ............................................... 144
Interrupt .................................................................... 142
Operation ................................................................. 140
Oscillator .......................................................... 139, 141
Oscillator Layout Considerations ............................. 142
Overflow Interrupt .................................................... 139
Resetting, Using the CCP Special Event Trigger ..... 142
Special Event Trigger (ECCP) ................................. 164
TMR1H Register ...................................................... 139
TMR1L Register ....................................................... 139
Use as a Real-Time Clock ....................................... 143
Timer2 .............................................................................. 145
Associated Registers ............................................... 146
Interrupt .................................................................... 146
Operation ................................................................. 145
Output ...................................................................... 146
Timer3 .............................................................................. 147
16-Bit Read/Write Mode ........................................... 149
Associated Registers ............................................... 150
Operation ................................................................. 148
Oscillator .......................................................... 147, 149
Overflow Interrupt ............................................ 147, 149
Special Event Trigger (CCP) .................................... 150
TMR3H Register ...................................................... 147
TMR3L Register ....................................................... 147
Timing Diagrams
High/Low-Voltage Detect Operation
(VDIRMAG = 0) ............................................... 279
High/Low-Voltage Detect Operation
(VDIRMAG = 1) ............................................... 280
I C Bus Data ............................................................ 379
I C Bus Start/Stop Bits ............................................ 379
I C Master Mode (7 or 10-Bit Transmission) ........... 215
I C Master Mode (7-Bit Reception) ......................... 216
I C Slave Mode (10-Bit Reception, SEN = 0) .......... 200
I C Slave Mode (10-Bit Reception, SEN = 1) .......... 206
I C Slave Mode (10-Bit Transmission) .................... 201
I C Slave Mode (7-bit Reception, SEN = 0) ............ 198
I C Slave Mode (7-Bit Reception, SEN = 1) ............ 205
I C Slave Mode (7-Bit Transmission) ...................... 199
I C Slave Mode General Call Address
2
2
2
2
2
2
2
2
2
2
2
Sequence (7 or 10-Bit Address Mode) ............ 207
I C Stop Condition Receive or Transmit Mode ........ 217
2
Internal Oscillator Switch Timing ............................... 37
2
Master SSP I C Bus Data ....................................... 381
2
Master SSP I C Bus Start/Stop Bits ........................ 381
Parallel Slave Port (PIC18F4XK20) ......................... 374
Parallel Slave Port (PSP) Read ............................... 134
Parallel Slave Port (PSP) Write ............................... 134
PWM Auto-shutdown
Auto-restart Enabled ........................................ 174
Firmware Restart ............................................. 174
PWM Direction Change ........................................... 171
PWM Direction Change at Near 100% Duty Cycle .. 172
PWM Output (Active-High) ...................................... 166
PWM Output (Active-Low) ....................................... 167
Repeat Start Condition ............................................ 213
Reset, Watchdog Timer (WDT), Oscillator Start-up
Timer (OST), Power-up Timer (PWRT) ........... 371
Send Break Character Sequence ............................ 242
Slave Synchronization ............................................. 189
Slow Rise Time (MCLR Tied to VDD,
VDD Rise > TPWRT) ............................................ 55
SPI Mode (Master Mode) ........................................ 188
SPI Mode (Slave Mode, CKE = 0) ........................... 190
SPI Mode (Slave Mode, CKE = 1) ........................... 190
Synchronous Reception (Master Mode, SREN) ...... 246
Synchronous Transmission ..................................... 244
Synchronous Transmission (Through TXEN) .......... 244
Time-out Sequence on POR w/PLL Enabled
A/D Conversion ........................................................ 385
Acknowledge Sequence .......................................... 217
Asynchronous Reception ......................................... 230
Asynchronous Transmission .................................... 226
Asynchronous Transmission (Back to Back) ........... 227
Auto Wake-up Bit (WUE) During Normal Operation 240
Auto Wake-up Bit (WUE) During Sleep ................... 241
Automatic Baud Rate Calculator .............................. 239
Baud Rate Generator with Clock Arbitration ............ 211
BRG Reset Due to SDA Arbitration During
Start Condition ................................................. 220
Brown-out Reset (BOR) ........................................... 372
Bus Collision During a Repeated Start
Condition (Case 1) ........................................... 221
Bus Collision During a Repeated Start
Condition (Case 2) ........................................... 221
Bus Collision During a Start Condition (SCL = 0) .... 220
Bus Collision During a Stop Condition (Case 1) ...... 222
Bus Collision During a Stop Condition (Case 2) ...... 222
Bus Collision During Start Condition (SDA only) ..... 219
Bus Collision for Transmit and Acknowledge ........... 218
Capture/Compare/PWM (CCP) ................................ 373
CLKO and I/O .......................................................... 370
Clock Synchronization ............................................. 204
Clock/Instruction Cycle .............................................. 67
Comparator Output .................................................. 263
Example SPI Master Mode (CKE = 0) ..................... 375
Example SPI Master Mode (CKE = 1) ..................... 376
Example SPI Slave Mode (CKE = 0) ....................... 377
Example SPI Slave Mode (CKE = 1) ....................... 378
External Clock (All Modes except PLL) .................... 369
Fail-Safe Clock Monitor (FSCM) ................................ 39
First Start Bit Timing ................................................ 212
Full-Bridge PWM Output .......................................... 170
Half-Bridge PWM Output ................................. 168, 175
High/Low-Voltage Detect Characteristics ................ 366
(MCLR Tied to VDD) .......................................... 55
Time-out Sequence on Power-up (MCLR
Not Tied to VDD, Case 1) ................................... 54
Time-out Sequence on Power-up (MCLR
Not Tied to VDD, Case 2) ................................... 54
Time-out Sequence on Power-up (MCLR
Tied to VDD, VDD Rise < TPWRT) ....................... 54
Timer0 and Timer1 External Clock .......................... 372
Transition for Entry to Sleep Mode ............................ 44
Transition for Wake from Sleep (HSPLL) .................. 44
Transition Timing for Entry to Idle Mode .................... 45
Transition Timing for Wake from Idle to Run Mode ... 45
USART Synchronous Receive (Master/Slave) ........ 383
USART Synchronous Transmission (Master/Slave) 383
Timing Diagrams and Specifications ............................... 369
A/D Conversion Requirements ................................ 385
Capture/Compare/PWM Requirements ................... 374
CLKO and I/O Requirements ................................... 371
Example SPI Mode Requirements
(Master Mode, CKE = 0) .................................. 375
(Master Mode, CKE = 1) .................................. 376
© 2007 Microchip Technology Inc.
Advance Information
DS41303B-page 413
PIC18F2XK20/4XK20
(Slave Mode, CKE = 0) ....................................377
(Slave Mode, CKE = 1) ....................................378
External Clock Requirements ..................................369
W
Wake-up on Break ........................................................... 240
Watchdog Timer (WDT) ........................................... 283, 292
Associated Registers ............................................... 293
Control Register ....................................................... 293
Programming Considerations .................................. 292
WCOL ...................................................... 212, 213, 214, 217
WCOL Status Flag ................................... 212, 213, 214, 217
WDTCON Register .......................................................... 293
WWW Address ................................................................ 409
WWW, On-Line Support ...................................................... 8
2
I C Bus Data Requirements (Slave Mode) ..............380
2
I C Bus Start/Stop Bits Requirements (Slave Mode) .....
379
2
Master SSP I C Bus Data Requirements ................382
Master SSP I C Bus Start/Stop Bits Requirements .381
2
Parallel Slave Port Requirements (PIC18F4X20) ....374
PLL Clock .................................................................370
Reset, Watchdog Timer, Oscillator Start-up Timer,
Power-up Timer and Brown-out Reset
Requirements ...................................................372
Timer0 and Timer1 External Clock Requirements ...373
USART Synchronous Receive Requirements .........383
USART Synchronous Transmission Requirements .383
Top-of-Stack Access ..........................................................64
TRISE Register ................................................................128
PSPMODE Bit ..........................................................124
TSTFSZ ............................................................................339
Two-Speed Clock Start-up Mode .......................................35
Two-Speed Start-up .........................................................283
Two-Word Instructions
X
XORLW ............................................................................ 339
XORWF ........................................................................... 340
Example Cases ..........................................................68
TXREG .............................................................................225
TXSTA Register ...............................................................232
BRGH Bit .................................................................235
V
Voltage Reference. See Comparator Voltage
Reference (CVREF)
Voltage References
Fixed Voltage Reference (FVR) ...............................274
VR Stabilization ........................................................274
VREF. SEE ADC Reference Voltage
DS41303B-page 414
Advance Information
© 2007 Microchip Technology Inc.
PIC18F2XK20/4XK20
THE MICROCHIP WEB SITE
CUSTOMER SUPPORT
Microchip provides online support via our WWW site at
www.microchip.com. This web site is used as a means
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Users of Microchip products can receive assistance
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• General Technical Support – Frequently Asked
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Technical support is available through the web site
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To register, access the Microchip web site at
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© 2007 Microchip Technology Inc.
Advance Information
DS41303B-page 415
PIC18F2XK20/4XK20
READER RESPONSE
It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip prod-
uct. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation
can better serve you, please FAX your comments to the Technical Publications Manager at (480) 792-4150.
Please list the following information, and use this outline to provide us with your comments about this document.
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Y
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PIC18F2XK20/4XK20
DS41303B
Literature Number:
Device:
Questions:
1. What are the best features of this document?
2. How does this document meet your hardware and software development needs?
3. Do you find the organization of this document easy to follow? If not, why?
4. What additions to the document do you think would enhance the structure and subject?
5. What deletions from the document could be made without affecting the overall usefulness?
6. Is there any incorrect or misleading information (what and where)?
7. How would you improve this document?
DS41303B-page 416
Advance Information
© 2007 Microchip Technology Inc.
PIC18F2XK20/4XK20
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
PART NO.
Device
X
/XX
XXX
Examples:
Temperature
Range
Package
Pattern
a)
PIC18F45K20-E/P 301 = Extended temp.,
PDIP package, Extended VDD limits, QTP pat-
tern #301.
b)
c)
PIC18F23K20-E/SO = Extended temp., SOIC
package.
Device:
PIC18F23K20(1), PIC18F24K20(1), PIC18F25K20(1)
,
PIC18F44K20-E/P = Extended temp., PDIP
package.
PIC18F26K20(1), PIC18F43K20(1), PIC18F44K20(1)
PIC18F45K20(1), PIC18F46K20(1)
,
Temperature
Range:
E
=
-40°C to +125°C (Extended)
Package:
ML
P
PT
SO
SP
SS
=
=
=
=
=
=
QFN
PDIP
TQFP (Thin Quad Flatpack)
SOIC
Skinny Plastic DIP
SSOP
Note 1:
T
=
in tape and reel PLCC, and TQFP
packages only.
Pattern:
QTP, SQTP, Code or Special Requirements
(blank otherwise)
© 2007 Microchip Technology Inc.
Advance Information
DS41303B-page 417
WORLDWIDE SALES AND SERVICE
AMERICAS
ASIA/PACIFIC
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EUROPE
Corporate Office
Asia Pacific Office
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Technical Support:
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Web Address:
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Santa Clara, CA
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China - Wuhan
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Thailand - Bangkok
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Toronto
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Tel: 905-673-0699
Fax: 905-673-6509
China - Xian
Tel: 86-29-8833-7250
Fax: 86-29-8833-7256
12/08/06
DS41303B-page 418
Advance Information
© 2007 Microchip Technology Inc.
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