PIC18F67J11-IPT [MICROCHIP]
64/80-Pin High-Performance, 1-Mbit Flash Microcontrollers with nanoWatt Technology; 八十〇分之六十四引脚高性能， 1兆位闪存微控制器采用纳瓦技术
| 型号： | PIC18F67J11-IPT |
| 厂家： | 
MICROCHIP |
| 描述： | 64/80-Pin High-Performance, 1-Mbit Flash Microcontrollers with nanoWatt Technology |
| 文件： | 总448页 (文件大小：7679K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PIC18F87J11 Family
Data Sheet
64/80-Pin High-Performance,
1-Mbit Flash Microcontrollers
with nanoWatt Technology
© 2009 Microchip Technology Inc.
DS39778D
Note the following details of the code protection feature on Microchip devices:
•
Microchip products meet the specification contained in their particular Microchip Data Sheet.
•
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
•
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
•
•
Microchip is willing to work with the customer who is concerned about the integrity of their code.
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION,
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
QUALITY, PERFORMANCE, MERCHANTABILITY OR
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suits, or expenses resulting from such use. No licenses are
conveyed, implicitly or otherwise, under any Microchip
intellectual property rights.
Trademarks
The Microchip name and logo, the Microchip logo, dsPIC,
KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART,
rfPIC and UNI/O are registered trademarks of Microchip
Technology Incorporated in the U.S.A. and other countries.
FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor,
MXDEV, MXLAB, SEEVAL and The Embedded Control
Solutions Company are registered trademarks of Microchip
Technology Incorporated in the U.S.A.
Analog-for-the-Digital Age, Application Maestro, CodeGuard,
dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN,
ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial
Programming, ICSP, Mindi, MiWi, MPASM, MPLAB Certified
logo, MPLIB, MPLINK, mTouch, Octopus, Omniscient Code
Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit,
32
PICtail, PIC logo, REAL ICE, rfLAB, Select Mode, Total
Endurance, TSHARC, UniWinDriver, WiperLock and ZENA
are trademarks of Microchip Technology Incorporated in the
U.S.A. and other countries.
SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.
All other trademarks mentioned herein are property of their
respective companies.
© 2009, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.
Printed on recycled paper.
Microchip received ISO/TS-16949:2002 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
DS39778D-page 2
© 2009 Microchip Technology Inc.
PIC18F87J11 FAMILY
64/80-Pin High-Performance, 1-Mbit Flash Microcontrollers
with nanoWatt Technology
Flexible Oscillator Structure:
Peripheral Highlights (continued):
• Four Crystal modes, including High-Precision PLL
• Two External Clock modes, up to 48 MHz
• Internal Oscillator Block:
- Provides 8 user-selectable frequencies from
31 kHz to 8 MHz
• 8-Bit Parallel Master Port/Enhanced Parallel Slave
Port (PMP/EPSP) with 16 Address Lines
• Dual Analog Comparators with Input Multiplexing
• 10-Bit, up to 15-Channel Analog-to-Digital Converter
module (A/D):
- Provides a complete range of clock speeds,
from 31 kHz to 32 MHz when used with PLL
- User-tunable to compensate for frequency drift
• Secondary Oscillator using Timer1 @ 32 kHz
• Fail-Safe Clock Monitor:
- Auto-acquisition capability
- Conversion available during Sleep
External Memory Bus
(80-pin devices only):
- Allows for safe shutdown if any clock stops
• Address Capability of up to 2 Mbytes
• 8-Bit or 16-Bit Interface
• 12-Bit, 16-Bit and 20-Bit Addressing modes
Peripheral Highlights:
• High-Current Sink/Source 25 mA/25mA on PORTB
Special Microcontroller Features:
and PORTC
• Four Programmable External Interrupts
• Four Input Change Interrupts
• One 8/16-Bit Timer/Counter
• Low-Power, High-Speed CMOS Flash Technology
• C Compiler Optimized Architecture for Re-Entrant
Code
• Two 8-Bit Timers/Counters
• Power Management Features:
• Two 16-Bit Timers/Counters
- Run: CPU on, peripherals on
• Two Capture/Compare/PWM (CCP) modules
• Three Enhanced Capture/Compare/PWM (ECCP)
modules:
- Idle: CPU off, peripherals on
- Sleep: CPU off, peripherals off
• Priority Levels for Interrupts
- One, two or four PWM outputs
- Selectable polarity
- Programmable dead time
• Self-Programmable under Software Control
• 8 x 8 Single-Cycle Hardware Multiplier
• Extended Watchdog Timer (WDT):
- Programmable period from 4 ms to 131s
• Single-Supply In-Circuit Serial Programming™
(ICSP™) via Two Pins
• In-Circuit Debug (ICD) with 3 Breakpoints via Two Pins
• Operating Voltage Range of 2.0V to 3.6V
• 5.5V Tolerant Inputs (digital only pins)
• On-Chip 2.5V Regulator
- Auto-shutdown and auto-restart
• Two Master Synchronous Serial Port (MSSP)
modules supporting 3-Wire SPI (all 4 modes) and
2
I C™ Master and Slave modes
• Two Enhanced USART modules:
- Supports RS-485, RS-232 and LIN 1.2
- Auto-wake-up on Start bit
- Auto-Baud Detect
• Flash Program Memory of 10000 Erase/Write
Cycles and 20-Year Data Retention
MSSP
Flash
Program
Memory
(bytes)
SRAM
Data
Memory
(bytes)
10-Bit CCP/ECCP
Device
I/O
Master
I C™
A/D (ch)
(PWM)
SPI
2
PIC18F66J11
PIC18F66J16
PIC18F67J11
PIC18F86J11
PIC18F86J16
PIC18F87J11
64 kB
96 kB
128 kB
64 kB
96 kB
128 kB
3930
3930
3930
3930
3930
3930
52
52
52
68
68
68
11
11
11
15
15
15
2/3
2/3
2/3
2/3
2/3
2/3
2
2
2
2
2
2
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
2
2
2
2
2
2
2
2
2
2
2
2
2/3
2/3
2/3
2/3
2/3
2/3
N
N
N
Y
Y
Y
Y
Y
Y
Y
Y
Y
© 2009 Microchip Technology Inc.
DS39778D-page 3
PIC18F87J11 FAMILY
Pin Diagrams
64-Pin TQFP
64
63 62 61 60 59 58 57 56 55 54 53 52 51
50 49
RB0/INT0/FLT0
RB1/INT1/PMA4
RB2/INT2/PMA3
RB3/INT3/PMA2
RB4/KBI0/PMA1
RB5/KBI1/PMA0
RB6/KBI2/PGC
VSS
48
47
46
45
44
43
42
41
40
39
38
RE1/PMWR/P2C
RE0/PMRD/P2D
RG0/PMA8/ECCP3/P3A
RG1/PMA7/TX2/CK2
RG2/PMA6/RX2/DT2
RG3/PMCS1/CCP4/P3D
MCLR
1
2
3
4
5
6
7
PIC18F6XJ11
PIC18F6XJ16
RG4/PMCS2/CCP5/P1D
VSS
8
OSC2/CLKO/RA6
OSC1/CLKI/RA7
VDD
9
VDDCORE/VCAP
10
11
12
13
14
15
16
RF7/SS1
RB7/KBI3/PGD
RC5/SDO1
RF6/AN11/C1INA
RF5/AN10/C1INB/CVREF
RF4/AN9/C2INA
37
36
35
34
33
RC4/SDI1/SDA1
RC3/SCK1/SCL1
RC2/ECCP1/P1A
RF3/AN8/C2INB
RF2/PMA5/AN7/C1OUT
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
Note 1: The ECCP2/P2A pin placement depends on the CCP2MX Configuration bit setting.
DS39778D-page 4
© 2009 Microchip Technology Inc.
PIC18F87J11 FAMILY
Pin Diagrams (Continued)
80-Pin TQFP
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61
60
RH2/A18/PMD7(3)
1
RJ2/WRL
RH3/A19/PMD6(3)
2
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
RJ3/WRH
RE1/AD9/PMWR(3)/P2C
3
RB0/INT0/FLT0
RB1/INT1/PMA4
RE0/AD8/PMRD(3)/P2D
4
RG0/PMA8/ECCP3/P3A
RG1/PMA7/TX2/CK2
RG2/PMA6/RX2/DT2
RG3/PMCS1/CCP4/P3D
MCLR
5
RB2/INT2/PMA3
RB3/INT3/PMA2/ECCP2(1)/P2A(1)
RB4/KBI0/PMA1
RB5/KBI1/PMA0
RB6/KBI2/PGC
VSS
6
7
8
9
PIC18F8XJ11
PIC18F8XJ16
RG4/PMCS2/CCP5/P1D
VSS
10
11
12
13
14
15
16
17
18
19
OSC2/CLKO/RA6
OSC1/CLKI/RA7
VDD
VDDCORE/VCAP
RF7/PMD0(3)/SS1
RF6/PMD1(3)/AN11/C1INA
RF5/PMD2(3)/AN10/ C1INB/CVREF
RF4/AN9/C2INA
RB7/KBI3/PGD
RC5/SDO1
RC4/SDI1/SDA1
RC3/SCK1/SCL1
RC2/ECCP1/P1A
RJ7/UB
RF3/AN8/C2INB
RF2/PMA5/AN7/C1OUT
RH7/PMWR(3)/AN15/P1B(2)
RH6/PMRD(3)/AN14/P1C(2)/C1INC
RJ6/LB
20
21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
Note 1: The ECCP2/P2A pin placement depends on the CCP2MX Configuration bit and Processor mode settings.
2: P1B, P1C, P3B, and P3C pin placement depends on the ECCPMX Configuration bit setting.
3: PMP pin placement depends on the PMPMX Configuration bit setting.
© 2009 Microchip Technology Inc.
DS39778D-page 5
PIC18F87J11 FAMILY
Table of Contents
1.0 Device Overview .......................................................................................................................................................................... 9
2.0 Oscillator Configurations ............................................................................................................................................................ 33
3.0 Power-Managed Modes ............................................................................................................................................................. 43
4.0 Reset.......................................................................................................................................................................................... 51
5.0 Memory Organization................................................................................................................................................................. 63
6.0 Flash Program Memory.............................................................................................................................................................. 89
7.0 External Memory Bus................................................................................................................................................................. 99
8.0 8 x 8 Hardware Multiplier.......................................................................................................................................................... 111
9.0 Interrupts .................................................................................................................................................................................. 113
10.0 I/O Ports ................................................................................................................................................................................... 129
11.0 Parallel Master Port.................................................................................................................................................................. 153
12.0 Timer0 Module ......................................................................................................................................................................... 179
13.0 Timer1 Module ......................................................................................................................................................................... 183
14.0 Timer2 Module ......................................................................................................................................................................... 189
15.0 Timer3 Module ......................................................................................................................................................................... 191
16.0 Timer4 Module ......................................................................................................................................................................... 195
17.0 Capture/Compare/PWM (CCP) Modules ................................................................................................................................. 197
18.0 Enhanced Capture/Compare/PWM (ECCP) Module................................................................................................................ 205
19.0 Master Synchronous Serial Port (MSSP) Module .................................................................................................................... 223
20.0 Enhanced Universal Synchronous Asynchronous Receiver Transmitter (EUSART)............................................................... 271
21.0 10-bit Analog-to-Digital Converter (A/D) Module...................................................................................................................... 293
22.0 Comparator Module.................................................................................................................................................................. 303
23.0 Comparator Voltage Reference Module................................................................................................................................... 311
24.0 Special Features of the CPU.................................................................................................................................................... 315
25.0 Instruction Set Summary.......................................................................................................................................................... 331
26.0 Development Support............................................................................................................................................................... 381
27.0 Electrical Characteristics .......................................................................................................................................................... 385
28.0 Packaging Information.............................................................................................................................................................. 425
Appendix A: Revision History............................................................................................................................................................. 431
Appendix B: Device Differences......................................................................................................................................................... 431
The Microchip Web Site..................................................................................................................................................................... 433
Customer Change Notification Service .............................................................................................................................................. 433
Customer Support.............................................................................................................................................................................. 433
Reader Response .............................................................................................................................................................................. 434
Product Identification System............................................................................................................................................................. 447
DS39778D-page 6
© 2009 Microchip Technology Inc.
PIC18F87J11 FAMILY
TO OUR VALUED CUSTOMERS
It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip
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enhanced as new volumes and updates are introduced.
If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via
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The last character of the literature number is the version number, (e.g., DS30000A is version A of document DS30000).
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An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current
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To determine if an errata sheet exists for a particular device, please check with one of the following:
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© 2009 Microchip Technology Inc.
DS39778D-page 7
PIC18F87J11 FAMILY
NOTES:
DS39778D-page 8
© 2009 Microchip Technology Inc.
PIC18F87J11 FAMILY
• A Phase Lock Loop (PLL) frequency multiplier,
available to all of the oscillator modes, which
allows a wide range of clock speeds from 16 MHz
to 40 MHz
1.0
DEVICE OVERVIEW
This document contains device-specific information for
the following devices:
The internal oscillator block provides a stable reference
source that gives the family additional features for
robust operation:
• PIC18F66J11
• PIC18F66J16
• PIC18F67J11
• PIC18F86J11
• PIC18F86J16
• PIC18F87J11
• Fail-Safe Clock Monitor: This option constantly
monitors the main clock source against a reference
signal provided by the internal oscillator. If a clock
failure occurs, the controller is switched to the
internal oscillator, allowing for continued low-speed
operation or a safe application shutdown.
This family introduces a line of low-voltage, general
purpose microcontrollers with the main traditional
advantage of all PIC18 microcontrollers – namely, high
computational performance and a rich feature set – at
an extremely competitive price point. These features
make the PIC18F87J11 Family a logical choice for
many high-performance applications, where an
extended peripheral feature set is required, and cost is
a primary consideration.
• Two-Speed Start-up: This option allows the
internal oscillator to serve as the clock source
from Power-on Reset, or wake-up from Sleep
mode, until the primary clock source is available.
1.1
Core Features
1.1.3
EXPANDED MEMORY
The PIC18F87J11 family provides ample room for
application code, from 64 Kbytes to 128 Kbytes of code
space. The Flash cells for program memory are rated
to last up to 10,000 erase/write cycles. Data retention
without refresh is conservatively estimated to be
greater than 20 years.
1.1.1
nanoWatt TECHNOLOGY
All of the devices in the PIC18F87J11 family incorporate
a range of features that can significantly reduce power
consumption during operation. Key items include:
• Alternate Run Modes: By clocking the controller
from the Timer1 source or the internal RC oscilla-
tor, power consumption during code execution
can be reduced by as much as 90%.
The Flash program memory is readable, writable, and
during normal operation, the PIC18F87J11 Family also
provides plenty of room for dynamic application data
with up to 3930 bytes of data RAM.
• Multiple Idle Modes: The controller can also run
with its CPU core disabled but the peripherals still
active. In these states, power consumption can be
reduced even further, to as little as 4% of normal
operation requirements.
1.1.4
EXTERNAL MEMORY BUS
In the event that 128 Kbytes of memory are inadequate
for an application, the 80-pin members of the
PIC18F87J11 Family also implement an External Mem-
ory Bus (EMB). This allows the controller’s internal
program counter to address a memory space of up to
2 Mbytes, permitting a level of data access that few
8-bit devices can claim. This allows additional memory
options, including:
• On-the-Fly Mode Switching: The
power-managed modes are invoked by user code
during operation, allowing the user to incorporate
power-saving ideas into their application’s
software design.
1.1.2
OSCILLATOR OPTIONS AND
FEATURES
• Using combinations of on-chip and external
memory up to the 2-Mbyte limit
• Using external Flash memory for reprogrammable
application code or large data tables
All of the devices in the PIC18F87J11 Family offer four
different oscillator options, allowing users a range of
choices in developing application hardware. These
include:
• Using external RAM devices for storing large
amounts of variable data
• Two Crystal modes, using crystals or ceramic
resonators.
1.1.5
EXTENDED INSTRUCTION SET
The PIC18F87J11 Family implements the optional
extension to the PIC18 instruction set, adding 8 new
instructions and an Indexed Addressing mode.
Enabled as a device configuration option, the extension
has been specifically designed to optimize re-entrant
application code originally developed in high-level
languages, such as ‘C’.
• Two External Clock modes, offering the option of
a divide-by-4 clock output.
• An internal oscillator block which provides an
8 MHz clock and an INTRC source (approxi-
mately 31 kHz, stable over temperature and VDD),
as well as a range of 6 user-selectable clock
frequencies, between 125 kHz to 4 MHz, for a
total of 8 clock frequencies. This option frees an
oscillator pin for use as an additional general
purpose I/O.
© 2009 Microchip Technology Inc.
DS39778D-page 9
PIC18F87J11 FAMILY
1.1.6
EASY MIGRATION
1.3
Details on Individual Family
Members
Regardless of the memory size, all devices share the
same rich set of peripherals, allowing for a smooth
migration path as applications grow and evolve.
Devices in the PIC18F87J11 Family are available in
64-pin and 80-pin packages. Block diagrams for the
two groups are shown in Figure 1-1 and Figure 1-2.
The devices are differentiated from each other in three
ways:
The consistent pinout scheme used throughout the
entire family also aids in migrating to the next larger
device. This is true when moving between the 64-pin
members, between the 80-pin members, or even
jumping from 64-pin to 80-pin devices.
1. Flash program memory (three sizes, ranging
from 64 Kbytes for PIC18FX6J11 devices to
128 Kbytes for PIC18FX7J11 devices).
The PIC18F87J11 Family is also pin compatible with
other PIC18 families, such as the PIC18F87J10,
PIC18F85J11, PIC18F8720 and PIC18F8722. This
allows a new dimension to the evolution of applications,
allowing developers to select different price points
within Microchip’s PIC18 portfolio, while maintaining
the same feature set.
2. I/O ports (7 bidirectional ports on 64-pin devices,
9 bidirectional ports on 80-pin devices).
3. A/D input channels (11 on 64-pin devices, 15 on
80-pin devices).
All other features for devices in this family are identical.
These are summarized in Table 1-1 and Table 1-2.
The pinouts for all devices are listed in Table 1-3 and
Table 1-4.
1.2
Other Special Features
• Communications: The PIC18F87J11 Family
incorporates a range of serial and parallel com-
munication peripherals. These devices all include
2 independent Enhanced USARTs and 2 Master
SSP modules, capable of both SPI and I2C™
(Master and Slave) modes of operation. The
devices also have a parallel port and can be
configured to function as either a Parallel Master
Port or as a Parallel Slave Port.
• CCP Modules: All devices in the family incorporate
two Capture/Compare/PWM (CCP) modules and
three Enhanced CCP (ECCP) modules to maximize
flexibility in control applications. Up to four different
time bases may be used to perform several
different operations at once. Each of the three
ECCP modules offers up to four PWM outputs,
allowing for a total of 12 PWMs. The ECCPs also
offer many beneficial features, including polarity
selection, programmable dead time, auto-shutdown
and restart, and Half-Bridge and Full-Bridge Output
modes.
• 10-Bit A/D Converter: This module incorporates
programmable acquisition time, allowing for a
channel to be selected and a conversion to be
initiated without waiting for a sampling period, and
thus, reducing code overhead.
• Extended Watchdog Timer (WDT): This
enhanced version incorporates a 16-bit prescaler,
allowing an extended time-out range that is stable
across operating voltage and temperature. See
Section 27.0 “Electrical Characteristics” for
time-out periods.
DS39778D-page 10
© 2009 Microchip Technology Inc.
PIC18F87J11 FAMILY
TABLE 1-1:
DEVICE FEATURES FOR THE PIC18F6XJ1X (64-PIN DEVICES)
Features
PIC18F66J11
PIC18F66J16
PIC18F67J11
Operating Frequency
DC – 48 MHz
64K
DC – 48 MHz
DC – 48 MHz
128K
Program Memory (Bytes)
Program Memory (Instructions)
Data Memory (Bytes)
96K
32768
49152
65536
3930
3930
3930
Interrupt Sources
29
I/O Ports
Ports A, B, C, D, E, F, G
Timers
5
Capture/Compare/PWM Modules
Enhanced Capture/Compare/PWM Modules
Serial Communications
Parallel Communications (PMP)
10-Bit Analog-to-Digital Module
Resets (and Delays)
2
3
MSSP (2), Enhanced USART (2)
Yes
11 Input Channels
POR, BOR, RESETInstruction, Stack Full, Stack Underflow, MCLR, WDT
(PWRT, OST)
Instruction Set
Packages
75 Instructions, 83 with Extended Instruction Set Enabled
64-Pin TQFP
TABLE 1-2:
DEVICE FEATURES FOR THE PIC18F8XJ1X (80-PIN DEVICES)
Features
PIC18F86J11
PIC18F86J16
PIC18F87J11
Operating Frequency
DC – 48 MHz
64K
DC – 48 MHz
DC – 48 MHz
128K
Program Memory (Bytes)
Program Memory (Instructions)
Data Memory (Bytes)
96K
32768
49152
65536
3930
3930
3930
Interrupt Sources
29
I/O Ports
Ports A, B, C, D, E, F, G, H, J
Timers
5
Capture/Compare/PWM Modules
Enhanced Capture/Compare/PWM Modules
Serial Communications
Parallel Communications (PMP)
10-Bit Analog-to-Digital Module
Resets (and Delays)
2
3
MSSP (2), Enhanced USART (2)
Yes
15 Input Channels
POR, BOR, RESETInstruction, Stack Full, Stack Underflow, MCLR, WDT
(PWRT, OST)
Instruction Set
Packages
75 Instructions, 83 with Extended Instruction Set Enabled
80-Pin TQFP
© 2009 Microchip Technology Inc.
DS39778D-page 11
PIC18F87J11 FAMILY
FIGURE 1-1:
PIC18F6XJ1X (64-PIN) BLOCK DIAGRAM
Data Bus<8>
Table Pointer<21>
inc/dec logic
21
PORTA
Data Latch
8
8
RA0:RA7(1)
Data Memory
(2.0, 3.9
PCLATU PCLATH
Kbytes)
Address Latch
20
PCU PCH PCL
Program Counter
12
PORTB
Data Address<12>
RB0:RB7(1)
31 Level Stack
STKPTR
4
BSR
12
FSR0
FSR1
FSR2
4
Address Latch
Access
Bank
Program Memory
(96 Kbytes)
12
Data Latch
PORTC
RC0:RC7(1)
inc/dec
logic
8
Table Latch
Address
Decode
ROM Latch
IR
Instruction Bus <16>
PORTD
RD0:RD7(1)
8
State Machine
Control Signals
Instruction
Decode and
Control
PRODH PRODL
8 x 8 Multiply
PORTE
RE0:RE7(1)
3
Timing
8
Power-up
Timer
Generation
OSC2/CLKO
OSC1/CLKI
BITOP
8
W
8 MHz
INTOSC
8
8
Oscillator
INTRC
Oscillator
Start-up Timer
PORTF
8
8
RF2:RF7(1)
Power-on
Reset
ALU<8>
8
Precision
Band Gap
Reference
Watchdog
Timer
ENVREG
PORTG
Brown-out
Reset(2)
Voltage
Regulator
RG0:RG4(1)
VDDCORE/VCAP
VDD,VSS
MCLR
ADC
10-Bit
Timer0
Timer1
Timer2
CCP5
Timer3
Comparators
Timer4
CCP4
MSSP1
MSSP2
PMP
ECCP1
ECCP2
ECCP3
EUSART1
EUSART2
Note 1: See Table 1-3 for I/O port pin descriptions.
2: BOR functionality is provided when the on-board voltage regulator is enabled.
DS39778D-page 12
© 2009 Microchip Technology Inc.
PIC18F87J11 FAMILY
FIGURE 1-2:
PIC18F8XJ1X (80-PIN) BLOCK DIAGRAM
Data Bus<8>
PORTA
Data Latch
Table Pointer<21>
inc/dec logic
8
RA0:RA7(1)
8
Data Memory
(2.0, 3.9
Kbytes)
PCLATH
PCLATU
Address Latch
21
20
PORTB
PCU PCH PCL
Program Counter
RB0:RB7(1)
12
Data Address<12>
31 Level Stack
STKPTR
4
BSR
4
12
FSR0
FSR1
FSR2
Address Latch
PORTC
Access
Bank
Program Memory
(128 Kbytes)
RC0:RC7(1)
12
Data Latch
inc/dec
logic
8
PORTD
Table Latch
ROM Latch
RD0:RD7(1)
Address
Decode
Instruction Bus <16>
PORTE
IR
RE0:RE7(1)
AD15:AD0, A19:A16
(Multiplexed with PORTD,
PORTE and PORTH)
8
PORTF
PRODH PRODL
8 x 8 Multiply
Instruction
Decode &
Control
State Machine
Control Signals
RF2:RF7(1)
3
8
W
BITOP
8
PORTG
Timing
8
8
Power-up
Timer
Generation
OSC2/CLKO
OSC1/CLKI
RG0:RG4(1)
8 MHz
INTOSC
8
8
Oscillator
Start-up Timer
INTRC
Oscillator
ALU<8>
8
PORTH
RH0:RH7(1)
Power-on
Reset
Precision
Band Gap
Reference
Watchdog
Timer
PORTJ
ENVREG
Brown-out
Reset(2)
RJ0:RJ7(1)
Voltage
Regulator
VDDCORE/VCAP
Timer0
VDD,VSS
Timer1
MCLR
ADC
10-Bit
Timer2
Timer3
Comparators
Timer4
PMP
ECCP1
ECCP2
ECCP3
CCP4
CCP5
MSSP1
MSSP2
EUSART1
EUSART2
Note 1: See Table 1-4 for I/O port pin descriptions.
2: BOR functionality is provided when the on-board voltage regulator is enabled.
© 2009 Microchip Technology Inc.
DS39778D-page 13
PIC18F87J11 FAMILY
TABLE 1-3:
PIC18F6XJ1X PINOUT I/O DESCRIPTIONS
Pin Number
Pin
Buffer
Type
Pin Name
Description
Type
64-TQFP
MCLR
7
I
ST
Master Clear (Reset) input. This pin is an active-low Reset
to the device.
OSC1/CLKI/RA7
OSC1
39
Oscillator crystal or external clock input. Available only in
external oscillator modes (EC/ECPLL and HS/HSPLL).
Main oscillator input connection.
I
I
ST
Oscillator crystal input or external clock source input.
ST buffer when configured in RC mode; CMOS
otherwise.
CLKI
CMOS Main clock input connection.
External clock source input. Always associated
with pin function OSC1. (See related OSC1/CLKI,
OSC2/CLKO pins.)
RA7
I/O
TTL General purpose I/O pin. Available only in INTIO2 and
INTPLL2 Oscillator modes.
OSC2/CLKO/RA6
OSC2
40
Oscillator crystal or clock output. Available only in external
oscillator modes (EC/ECPLL and HS/HSPLL).
Main oscillator feedback output connection.
Oscillator crystal output. Connects to crystal or
resonator in Crystal Oscillator mode.
O
O
—
—
CLKO
System cycle clock output (FOSC/4).
In EC, ECPLL, INTIO1 and INTPLL1 Oscillator modes,
OSC2 pin outputs CLKO which has 1/4 the frequency
of OSC1 and denotes the instruction cycle rate.
RA6
I/O
TTL General purpose I/O pin. Available only in INTIO1 and
INTPLL1 Oscillator modes.
Legend: TTL = TTL compatible input
ST = Schmitt Trigger input with CMOS levels
CMOS = CMOS compatible input or output
Analog = Analog input
I
= Input
O
= Output
P
= Power
OD
= Open-Drain (no P diode to VDD)
Note 1: Default assignment for ECCP2/P2A when Configuration bit, CCP2MX, is set.
2: Alternate assignment for ECCP2/P2A when Configuration bit, CCP2MX, is cleared.
DS39778D-page 14
© 2009 Microchip Technology Inc.
PIC18F87J11 FAMILY
TABLE 1-3:
PIC18F6XJ1X PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number
64-TQFP
Pin
Type
Buffer
Type
Pin Name
Description
PORTA is a bidirectional I/O port.
RA0/AN0
RA0
24
23
22
I/O
I
TTL
Analog
Digital I/O.
Analog input 0.
AN0
RA1/AN1
RA1
I/O
I
TTL
Analog
Digital I/O.
Analog input 1.
AN1
RA2/AN2/VREF-
RA2
I/O
TTL
Digital I/O.
AN2
VREF-
I
I
Analog
Analog
Analog input 2.
A/D reference voltage (low) input.
RA3/AN3/VREF+
RA3
21
I/O
TTL
Digital I/O.
AN3
VREF+
I
I
Analog
Analog
Analog input 3.
A/D reference voltage (high) input.
RA4/T0CKI
RA4
28
27
I/O
I
ST
ST
Digital I/O.
Timer0 external clock input.
T0CKI
RA5/AN4
RA5
I/O
I
TTL
Analog
Digital I/O.
Analog input 4.
AN4
RA6
RA7
—
—
—
—
—
—
See the OSC2/CLKO/RA6 pin.
See the OSC1/CLKI/RA7 pin.
Legend: TTL = TTL compatible input
ST = Schmitt Trigger input with CMOS levels
CMOS = CMOS compatible input or output
Analog = Analog input
I
= Input
O
= Output
P
= Power
OD
= Open-Drain (no P diode to VDD)
Note 1: Default assignment for ECCP2/P2A when Configuration bit, CCP2MX, is set.
2: Alternate assignment for ECCP2/P2A when Configuration bit, CCP2MX, is cleared.
© 2009 Microchip Technology Inc.
DS39778D-page 15
PIC18F87J11 FAMILY
TABLE 1-3:
PIC18F6XJ1X PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number
64-TQFP
Pin
Type
Buffer
Type
Pin Name
Description
PORTB is a bidirectional I/O port. PORTB can be software
programmed for internal weak pull-ups on all inputs.
RB0/FLT0/INT0
RB0
48
47
46
45
44
43
42
I/O
I
I
TTL
ST
ST
Digital I/O.
ECCP1/2/3 Fault input.
External interrupt 0.
FLT0
INT0
RB1/INT1/PMA4
RB1
I/O
I
O
TTL
ST
—
Digital I/O.
External interrupt 1.
Parallel Master Port address.
INT1
PMA4
RB2/INT2/PMA3
RB2
I/O
I
O
TTL
ST
—
Digital I/O.
External interrupt 2.
Parallel Master Port address.
INT2
PMA3
RB3/INT3/PMA2
RB3
I/O
I
O
TTL
ST
—
Digital I/O.
External interrupt 3.
Parallel Master Port address.
INT3
PMA2
RB4/KBI0/PMA1
RB4
I/O
I
I/O
TTL
TTL
—
Digital I/O.
Interrupt-on-change pin.
Parallel Master Port address.
KBI0
PMA1
RB5/KBI1/PMA0
RB5
I/O
I
I/O
TTL
TTL
—
Digital I/O.
Interrupt-on-change pin.
Parallel Master Port address.
KBI1
PMA0
RB6/KBI2/PGC
RB6
I/O
I
I/O
TTL
TTL
ST
Digital I/O.
KBI2
PGC
Interrupt-on-change pin.
In-Circuit Debugger and ICSP™ programming
clock pin.
RB7/KBI3/PGD
RB7
37
I/O
I
I/O
TTL
TTL
ST
Digital I/O.
Interrupt-on-change pin.
In-Circuit Debugger and ICSP programming data pin.
KBI3
PGD
Legend: TTL = TTL compatible input
ST = Schmitt Trigger input with CMOS levels
CMOS = CMOS compatible input or output
Analog = Analog input
I
= Input
O
= Output
P
= Power
OD
= Open-Drain (no P diode to VDD)
Note 1: Default assignment for ECCP2/P2A when Configuration bit, CCP2MX, is set.
2: Alternate assignment for ECCP2/P2A when Configuration bit, CCP2MX, is cleared.
DS39778D-page 16
© 2009 Microchip Technology Inc.
PIC18F87J11 FAMILY
TABLE 1-3:
PIC18F6XJ1X PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number
64-TQFP
Pin
Type
Buffer
Type
Pin Name
Description
PORTC is a bidirectional I/O port.
RC0/T1OSO/T13CKI
RC0
30
29
I/O
O
I
ST
—
ST
Digital I/O.
Timer1 oscillator output.
Timer1/Timer3 external clock input.
T1OSO
T13CKI
RC1/T1OSI/ECCP2/P2A
RC1
I/O
I
I/O
O
ST
CMOS
ST
Digital I/O.
Timer1 oscillator input.
Capture 2 input/Compare 2 output/PWM2 output.
ECCP2 PWM output A.
T1OSI
ECCP2(1)
P2A(1)
—
RC2/ECCP1/P1A
RC2
33
34
35
I/O
I/O
O
ST
ST
—
Digital I/O.
ECCP1
P1A
Capture 1 input/Compare 1 output/PWM1 output.
ECCP1 PWM output A.
RC3/SCK1/SCL1
RC3
I/O
I/O
I/O
ST
ST
ST
Digital I/O.
SCK1
SCL1
Synchronous serial clock input/output for SPI mode.
Synchronous serial clock input/output for I2C™ mode.
RC4/SDI1/SDA1
RC4
I/O
I
I/O
ST
ST
ST
Digital I/O.
SDI1
SDA1
SPI data in.
I2C data I/O.
RC5/SDO1
RC5
36
31
I/O
O
ST
—
Digital I/O.
SPI data out.
SDO1
RC6/TX1/CK1
RC6
I/O
O
I/O
ST
—
ST
Digital I/O.
TX1
CK1
EUSART1 asynchronous transmit.
EUSART1 synchronous clock (see related RX1/DT1).
RC7/RX1/DT1
RC7
32
I/O
I
I/O
ST
ST
ST
Digital I/O.
RX1
DT1
EUSART1 asynchronous receive.
EUSART1 synchronous data (see related TX1/CK1).
Legend: TTL = TTL compatible input
ST = Schmitt Trigger input with CMOS levels
CMOS = CMOS compatible input or output
Analog = Analog input
I
= Input
O
= Output
P
= Power
OD
= Open-Drain (no P diode to VDD)
Note 1: Default assignment for ECCP2/P2A when Configuration bit, CCP2MX, is set.
2: Alternate assignment for ECCP2/P2A when Configuration bit, CCP2MX, is cleared.
© 2009 Microchip Technology Inc.
DS39778D-page 17
PIC18F87J11 FAMILY
TABLE 1-3:
PIC18F6XJ1X PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number
64-TQFP
Pin
Type
Buffer
Type
Pin Name
Description
PORTD is a bidirectional I/O port.
RD0/PMD0
RD0
58
55
54
53
52
I/O
I/O
ST
TTL
Digital I/O.
Parallel Master Port data.
PMD0
RD1/PMD1
RD1
I/O
I/O
ST
TTL
Digital I/O.
Parallel Master Port data.
PMD1
RD2/PMD2
RD2
I/O
I/O
ST
TTL
Digital I/O.
Parallel Master Port data.
PMD2
RD3/PMD3
RD3
I/O
I/O
ST
TTL
Digital I/O.
Parallel Master Port data.
PMD3
RD4/PMD4/SDO2
RD4
I/O
I/O
O
ST
TTL
—
Digital I/O.
Parallel Master Port data.
SPI data out.
PMD4
SDO2
RD5/PMD5/SDI2/SDA2
51
50
49
RD5
I/O
I/O
I
ST
TTL
ST
Digital I/O.
PMD5
SDI2
SDA2
Parallel Master Port data.
SPI data in.
I/O
ST
I2C™ data I/O.
RD6/PMD6/SCK2/SCL2
RD6
I/O
I/O
I/O
I/O
ST
TTL
ST
Digital I/O.
Parallel Master Port data.
PMD6
SCK2
SCL2
Synchronous serial clock input/output for SPI mode.
ST
Synchronous serial clock input/output for I2C mode.
RD7/PMD7/SS2
RD7
I/O
I/O
I
ST
TTL
TTL
Digital I/O.
Parallel Master Port data.
SPI slave select input.
PMD7
SS2
Legend: TTL = TTL compatible input
ST = Schmitt Trigger input with CMOS levels
CMOS = CMOS compatible input or output
Analog = Analog input
I
= Input
O
= Output
P
= Power
OD
= Open-Drain (no P diode to VDD)
Note 1: Default assignment for ECCP2/P2A when Configuration bit, CCP2MX, is set.
2: Alternate assignment for ECCP2/P2A when Configuration bit, CCP2MX, is cleared.
DS39778D-page 18
© 2009 Microchip Technology Inc.
PIC18F87J11 FAMILY
TABLE 1-3:
PIC18F6XJ1X PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number
64-TQFP
Pin
Type
Buffer
Type
Pin Name
Description
PORTE is a bidirectional I/O port.
RE0/PMRD/P2D
RE0
2
1
I/O
I/O
O
ST
—
—
Digital I/O.
Parallel Master Port read strobe.
ECCP2 PWM output D.
PMRD
P2D
RE1/PMWR/P2C
RE1
I/O
I/O
O
ST
—
—
Digital I/O.
Parallel Master Port write strobe.
ECCP2 PWM output C.
PMWR
P2C
RE2/PMBE/P2B
RE2
64
63
I/O
O
O
ST
—
—
Digital I/O.
Parallel Master Port byte enable
ECCP2 PWM output B.
PMBE
P2B
RE3/PMA13/P3C/REFO
RE3
PMA13
P3C
I/O
O
O
ST
—
—
—
Digital I/O.
Parallel Master Port address.
ECCP3 PWM output C.
Reference clock out.
REFO
O
RE4/PMA12/P3B
RE4
62
61
60
59
I/O
O
O
ST
—
—
Digital I/O.
Parallel Master Port address.
ECCP3 PWM output B.
PMA12
P3B
RE5/PMA11/P1C
RE5
I/O
O
O
ST
—
—
Digital I/O.
Parallel Master Port address.
ECCP1 PWM output C.
PMA11
P1C
RE6/PMA10/P1B
RE6
I/O
O
O
ST
—
—
Digital I/O.
Parallel Master Port address.
ECCP1 PWM output B.
PMA10
P1B
RE7/PMA9/ECCP2/P2A
RE7
I/O
O
I/O
O
ST
—
ST
—
Digital I/O.
PMA9
ECCP2(2)
P2A(2)
Parallel Master Port address.
Capture 2 input/Compare 2 output/PWM2 output.
ECCP2 PWM output A.
Legend: TTL = TTL compatible input
ST = Schmitt Trigger input with CMOS levels
CMOS = CMOS compatible input or output
Analog = Analog input
I
= Input
O
= Output
P
= Power
OD
= Open-Drain (no P diode to VDD)
Note 1: Default assignment for ECCP2/P2A when Configuration bit, CCP2MX, is set.
2: Alternate assignment for ECCP2/P2A when Configuration bit, CCP2MX, is cleared.
© 2009 Microchip Technology Inc.
DS39778D-page 19
PIC18F87J11 FAMILY
TABLE 1-3:
PIC18F6XJ1X PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number
64-TQFP
Pin
Type
Buffer
Type
Pin Name
Description
PORTF is a bidirectional I/O port.
RF1/AN6/C2OUT
RF1
17
16
I/O
I
O
ST
Analog
—
Digital I/O.
Analog input 6.
Comparator 2 output.
AN6
C2OUT
RF2/PMA5/AN7/C1OUT
RF2
PMA5
AN7
I/O
O
I
ST
—
Analog
—
Digital I/O.
Parallel Master Port address.
Analog input 7.
C1OUT
O
Comparator 1 output.
RF3/AN8/C2INB
RF3
15
14
13
I
I
I
ST
Analog
Analog
Digital input.
Analog input 8.
Comparator 2 input B.
AN8
C2INB
RF4/AN9/C2INA
RF4
I
I
I
ST
Analog
Analog
Digital input.
Analog input 8.
Comparator 2 input A.
AN9
C2INA
RF5/AN10/C1INB/CVREF
RF5
I
I
I
ST
Digital input.
Analog input 10.
Comparator 1 input B.
Comparator reference voltage output.
AN10
C1INB
CVREF
Analog
Analog
Analog
O
RF6/AN11/C1INA
RF6
12
11
I/O
I
I
ST
Analog
Analog
Digital I/O.
Analog input 11.
Comparator 1 input A.
AN11
C1INA
RF7/SS1
RF7
I/O
I
ST
TTL
Digital I/O.
SPI slave select input.
SS1
Legend: TTL = TTL compatible input
ST = Schmitt Trigger input with CMOS levels
CMOS = CMOS compatible input or output
Analog = Analog input
I
= Input
O
= Output
P
= Power
OD
= Open-Drain (no P diode to VDD)
Note 1: Default assignment for ECCP2/P2A when Configuration bit, CCP2MX, is set.
2: Alternate assignment for ECCP2/P2A when Configuration bit, CCP2MX, is cleared.
DS39778D-page 20
© 2009 Microchip Technology Inc.
PIC18F87J11 FAMILY
TABLE 1-3:
PIC18F6XJ1X PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number
64-TQFP
Pin
Type
Buffer
Type
Pin Name
Description
PORTG is a bidirectional I/O port.
RG0/PMA8/ECCP3/P3A
3
4
5
6
8
RG0
I/O
O
I/O
O
ST
—
ST
—
Digital I/O.
PMA8
ECCP3
P3A
Parallel Master Port address.
Capture 3 input/Compare 3 output/PWM3 output.
ECCP3 PWM output A.
RG1/PMA7/TX2/CK2
RG1
PMA7
TX2
I/O
O
O
ST
—
—
Digital I/O.
Parallel Master Port address.
EUSART2 asynchronous transmit.
EUSART2 synchronous clock (see related RX2/DT2).
CK2
I/O
ST
RG2/PMA6/RX2/DT2
RG2
PMA6
RX2
I/O
O
I
ST
—
ST
ST
Digital I/O.
Parallel Master Port address.
EUSART2 asynchronous receive.
EUSART2 synchronous data (see related TX2/CK2).
DT2
I/O
RG3/PMCS1/CCP4/P3D
RG3
I/O
O
I/O
O
ST
—
ST
—
Digital I/O.
PMCS1
CCP4
P3D
Parallel Master Port chip select 1.
Capture 4 input/Compare 4 output/PWM4 output.
ECCP3 PWM output D.
RG4/PMCS2/CCP5/P1D
RG4
I/O
O
I/O
O
ST
—
ST
—
Digital I/O.
PMCS2
CCP5
P1D
Parallel Master Port chip select 2.
Capture 5 input/Compare 5 output/PWM5 output.
ECCP1 PWM output D.
VSS
9, 25, 41, 56
P
P
P
P
I
—
—
—
—
ST
Ground reference for logic and I/O pins.
Positive supply for peripheral digital logic and I/O pins.
Ground reference for analog modules.
Positive supply for analog modules.
VDD
26, 38, 57
AVss
20
19
18
10
AVDD
ENVREG
Enable for on-chip voltage regulator.
VDDCORE/VCAP
VDDCORE
Core logic power or external filter capacitor connection.
Positive supply for microcontroller core logic
(regulator disabled).
P
P
—
—
VCAP
External filter capacitor connection (regulator
enabled).
Legend: TTL = TTL compatible input
ST = Schmitt Trigger input with CMOS levels
CMOS = CMOS compatible input or output
Analog = Analog input
I
= Input
O
= Output
P
= Power
OD
= Open-Drain (no P diode to VDD)
Note 1: Default assignment for ECCP2/P2A when Configuration bit, CCP2MX, is set.
2: Alternate assignment for ECCP2/P2A when Configuration bit, CCP2MX, is cleared.
© 2009 Microchip Technology Inc.
DS39778D-page 21
PIC18F87J11 FAMILY
TABLE 1-4:
PIC18F8XJ1X PINOUT I/O DESCRIPTIONS
Pin Number
Pin
Type
Buffer
Type
Pin Name
Description
80-TQFP
MCLR
9
I
ST
ST
Master Clear (Reset) input. This pin is an active-low Reset to
the device.
OSC1/CLKI/RA7
OSC1
49
Oscillator crystal or external clock input. Available only in
external oscillator modes (EC/ECPLL and HS/HSPLL).
Main oscillator input connection.
I
I
Oscillator crystal input or external clock source input.
ST buffer when configured in RC mode; CMOS
otherwise.
CLKI
RA7
CMOS Main clock input connection.
External clock source input. Always associated
with pin function OSC1. (See related OSC1/CLKI,
OSC2/CLKO pins.)
I/O
TTL General purpose I/O pin. Available only in INTIO2 and
INTPLL2 Oscillator modes.
OSC2/CLKO/RA6
OSC2
50
Oscillator crystal or clock output. Available only in external
oscillator modes (EC/ECPLL and HS/HSPLL).
Main oscillator feedback output connection.
Oscillator crystal output. Connects to crystal or
resonator in Crystal Oscillator mode.
O
O
—
—
CLKO
System cycle clock output (FOSC/4).
In EC, ECPLL, INTIO1 and INTPLL1 Oscillator modes,
OSC2 pin outputs CLKO which has 1/4 the frequency
of OSC1 and denotes the instruction cycle rate.
RA6
I/O
TTL General purpose I/O pin. Available only in INTIO and INTPLL
Oscillator modes.
Legend: TTL = TTL compatible input
ST = Schmitt Trigger input with CMOS levels
CMOS = CMOS compatible input or output
Analog = Analog input
I
= Input
O
= Output
P
= Power
OD
= Open-Drain (no P diode to VDD)
Note 1: Alternate assignment for ECCP2/P2A when Configuration bit, CCP2MX, is cleared (Extended Microcontroller mode).
2: Default assignment for ECCP2/P2A for all devices in all operating modes (CCP2MX is set).
3: Default assignments for P1B/P1C/P3B/P3C (ECCPMX Configuration bit is set).
4: Alternate assignment for ECCP2/P2A when CCP2MX is cleared (Microcontroller mode).
5: Alternate assignments for P1B/P1C/P3B/P3C (ECCPMX Configuration bit is cleared).
6: Default assignment for PMP data and control pins when PMPMX Configuration bit is set.
7: Alternate assignment for PMP data and control pins when PMPMX Configuration bit is cleared (programmed).
DS39778D-page 22
© 2009 Microchip Technology Inc.
PIC18F87J11 FAMILY
TABLE 1-4:
PIC18F8XJ1X PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number
Pin
Type
Buffer
Type
Pin Name
Description
PORTA is a bidirectional I/O port.
80-TQFP
RA0/AN0
RA0
30
29
28
I/O
I
TTL
Analog
Digital I/O.
Analog input 0.
AN0
RA1/AN1
RA1
I/O
I
TTL
Analog
Digital I/O.
Analog input 1.
AN1
RA2/AN2/VREF-
RA2
I/O
TTL
Digital I/O.
AN2
VREF-
I
I
Analog
Analog
Analog input 2.
A/D reference voltage (low) input.
RA3/AN3/VREF+
RA3
27
34
33
I/O
I
I
TTL
Analog
Analog
Digital I/O.
Analog input 3.
A/D reference voltage (high) input.
AN3
VREF+
RA4/PMD5/T0CKI
RA4
I/O
I/O
I
ST
TTL
ST
Digital I/O.
Parallel Master Port data.
Timer0 external clock input.
(7)
PMD5
T0CKI
RA5/PMD4/AN4
RA5
I/O
I/O
I
TTL
TTL
Analog
Digital I/O.
Parallel Master Port data.
Analog input 4.
(7)
PMD4
AN4
RA6
—
—
—
—
—
—
See the OSC2/CLKO/RA6 pin.
See the OSC1/CLKI/RA7 pin.
RA7
Legend: TTL = TTL compatible input
ST = Schmitt Trigger input with CMOS levels
CMOS = CMOS compatible input or output
Analog = Analog input
I
= Input
O
= Output
P
= Power
OD
= Open-Drain (no P diode to VDD)
Note 1: Alternate assignment for ECCP2/P2A when Configuration bit, CCP2MX, is cleared (Extended Microcontroller mode).
2: Default assignment for ECCP2/P2A for all devices in all operating modes (CCP2MX is set).
3: Default assignments for P1B/P1C/P3B/P3C (ECCPMX Configuration bit is set).
4: Alternate assignment for ECCP2/P2A when CCP2MX is cleared (Microcontroller mode).
5: Alternate assignments for P1B/P1C/P3B/P3C (ECCPMX Configuration bit is cleared).
6: Default assignment for PMP data and control pins when PMPMX Configuration bit is set.
7: Alternate assignment for PMP data and control pins when PMPMX Configuration bit is cleared (programmed).
© 2009 Microchip Technology Inc.
DS39778D-page 23
PIC18F87J11 FAMILY
TABLE 1-4:
PIC18F8XJ1X PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number
Pin
Type
Buffer
Type
Pin Name
Description
80-TQFP
PORTB is a bidirectional I/O port. PORTB can be software
programmed for internal weak pull-ups on all inputs.
RB0/FLT0/INT0
RB0
58
57
56
55
I/O
I
I
TTL
ST
ST
Digital I/O.
ECCP1/2/3 Fault input.
External interrupt 0.
FLT0
INT0
RB1/INT1/PMA4
RB1
I/O
I
O
TTL
ST
—
Digital I/O.
External interrupt 1.
Parallel Master Port address.
INT1
PMA4
RB2/INT2/PMA3
RB2
I/O
I
O
TTL
ST
—
Digital I/O.
External interrupt 2.
Parallel Master Port address.
INT2
PMA3
RB3/INT3/PMA2/
ECCP2/P2A
RB3
I/O
I
O
I/O
O
TTL
ST
—
ST
—
Digital I/O.
External interrupt 3.
Parallel Master Port address.
Capture 2 input/Compare 2 output/PWM2 output.
ECCP2 PWM output A.
INT3
PMA2
(1)
ECCP2
(1)
P2A
RB4/KBI0/PMA1
RB4
54
53
52
47
I/O
I
I/O
TTL
TTL
—
Digital I/O.
Interrupt-on-change pin.
Parallel Master Port address.
KBI0
PMA1
RB5/KBI1/PMA0
RB5
I/O
I
I/O
TTL
TTL
—
Digital I/O.
Interrupt-on-change pin.
Parallel Master Port address.
KBI1
PMA0
RB6/KBI2/PGC
RB6
I/O
I
I/O
TTL
TTL
ST
Digital I/O.
Interrupt-on-change pin.
In-Circuit Debugger and ICSP™ programming clock pin.
KBI2
PGC
RB7/KBI3/PGD
RB7
I/O
I
I/O
TTL
TTL
ST
Digital I/O.
Interrupt-on-change pin.
In-Circuit Debugger and ICSP programming data pin.
KBI3
PGD
Legend: TTL = TTL compatible input
ST = Schmitt Trigger input with CMOS levels
CMOS = CMOS compatible input or output
Analog = Analog input
I
= Input
O
= Output
P
= Power
OD
= Open-Drain (no P diode to VDD)
Note 1: Alternate assignment for ECCP2/P2A when Configuration bit, CCP2MX, is cleared (Extended Microcontroller mode).
2: Default assignment for ECCP2/P2A for all devices in all operating modes (CCP2MX is set).
3: Default assignments for P1B/P1C/P3B/P3C (ECCPMX Configuration bit is set).
4: Alternate assignment for ECCP2/P2A when CCP2MX is cleared (Microcontroller mode).
5: Alternate assignments for P1B/P1C/P3B/P3C (ECCPMX Configuration bit is cleared).
6: Default assignment for PMP data and control pins when PMPMX Configuration bit is set.
7: Alternate assignment for PMP data and control pins when PMPMX Configuration bit is cleared (programmed).
DS39778D-page 24
© 2009 Microchip Technology Inc.
PIC18F87J11 FAMILY
TABLE 1-4:
PIC18F8XJ1X PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number
Pin
Type
Buffer
Type
Pin Name
Description
80-TQFP
PORTC is a bidirectional I/O port.
RC0/T1OSO/T13CKI
RC0
36
35
I/O
O
I
ST
—
ST
Digital I/O.
Timer1 oscillator output.
Timer1/Timer3 external clock input.
T1OSO
T13CKI
RC1/T1OSI/ECCP2/P2A
RC1
T1OSI
I/O
I
I/O
O
ST
CMOS
ST
Digital I/O.
Timer1 oscillator input.
Capture 2 input/Compare 2 output/PWM2 output.
ECCP2 PWM output A.
(2)
ECCP2
(2)
P2A
—
RC2/ECCP1/P1A
RC2
43
44
45
I/O
I/O
O
ST
ST
—
Digital I/O.
ECCP1
P1A
Capture 1 input/Compare 1 output/PWM1 output.
ECCP1 PWM output A.
RC3/SCK1/SCL1
RC3
I/O
I/O
I/O
ST
ST
ST
Digital I/O.
SCK1
SCL1
Synchronous serial clock input/output for SPI mode.
Synchronous serial clock input/output for I C™ mode.
2
RC4/SDI1/SDA1
RC4
I/O
I
I/O
ST
ST
ST
Digital I/O.
SDI1
SDA1
SPI data in.
2
I C data I/O.
RC5/SDO1
RC5
46
37
I/O
O
ST
—
Digital I/O.
SPI data out.
SDO1
RC6/TX1/CK1
RC6
I/O
O
I/O
ST
—
ST
Digital I/O.
TX1
CK1
EUSART1 asynchronous transmit.
EUSART1 synchronous clock (see related RX1/DT1).
RC7/RX1/DT1
RC7
38
I/O
I
I/O
ST
ST
ST
Digital I/O.
RX1
DT1
EUSART1 asynchronous receive.
EUSART1 synchronous data (see related TX1/CK1).
Legend: TTL = TTL compatible input
ST = Schmitt Trigger input with CMOS levels
CMOS = CMOS compatible input or output
Analog = Analog input
I
= Input
O
= Output
P
= Power
OD
= Open-Drain (no P diode to VDD)
Note 1: Alternate assignment for ECCP2/P2A when Configuration bit, CCP2MX, is cleared (Extended Microcontroller mode).
2: Default assignment for ECCP2/P2A for all devices in all operating modes (CCP2MX is set).
3: Default assignments for P1B/P1C/P3B/P3C (ECCPMX Configuration bit is set).
4: Alternate assignment for ECCP2/P2A when CCP2MX is cleared (Microcontroller mode).
5: Alternate assignments for P1B/P1C/P3B/P3C (ECCPMX Configuration bit is cleared).
6: Default assignment for PMP data and control pins when PMPMX Configuration bit is set.
7: Alternate assignment for PMP data and control pins when PMPMX Configuration bit is cleared (programmed).
© 2009 Microchip Technology Inc.
DS39778D-page 25
PIC18F87J11 FAMILY
TABLE 1-4:
PIC18F8XJ1X PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number
Pin
Type
Buffer
Type
Pin Name
Description
80-TQFP
PORTD is a bidirectional I/O port.
RD0/AD0/PMD0
72
69
68
67
66
RD0
AD0
PMD0
I/O
I/O
I/O
ST
TTL
TTL
Digital I/O.
External memory address/data 0.
Parallel Master Port data.
(6)
RD1/AD1/PMD1
RD1
AD1
PMD1
I/O
I/O
I/O
ST
TTL
TTL
Digital I/O.
External memory address/data 1.
Parallel Master Port data.
(6)
RD2/AD2/PMD2
RD2
AD2
PMD2
I/O
I/O
I/O
ST
TTL
TTL
Digital I/O.
External memory address/data 2.
Parallel Master Port data.
(6)
RD3/AD3/PMD3
RD3
AD3
PMD3
I/O
I/O
I/O
ST
TTL
TTL
Digital I/O.
External memory address/data 3.
Parallel Master Port data.
(6)
RD4/AD4/PMD4/SDO2
RD4
AD4
PMD4
I/O
I/O
I/O
O
ST
TTL
TTL
—
Digital I/O.
External memory address/data 4.
Parallel Master Port data.
SPI data out.
(6)
SDO2
RD5/AD5/PMD5/
SDI2/SDA2
RD5
65
64
63
I/O
I/O
I/O
I
ST
TTL
TTL
ST
Digital I/O.
AD5
PMD5
External memory address/data 5.
Parallel Master Port data.
SPI data in.
(6)
SDI2
SDA2
2
I/O
ST
I C™ data I/O.
RD6/AD6/PMD6/
SCK2/SCL2
RD6
I/O
I/O
I/O
I/O
I/O
ST
TTL
TTL
ST
Digital I/O.
External memory address/data 6.
Parallel Master Port data.
Synchronous serial clock input/output for SPI mode.
Synchronous serial clock input/output for I C mode.
AD6
PMD6
(6)
SCK2
SCL2
2
ST
RD7/AD7/PMD7/SS2
RD7
AD7
PMD7
I/O
I/O
I/O
I
ST
Digital I/O.
TTL
TTL
TTL
External memory address/data 7.
Parallel Master Port data.
SPI slave select input.
(6)
SS2
Legend: TTL = TTL compatible input
ST = Schmitt Trigger input with CMOS levels
CMOS = CMOS compatible input or output
Analog = Analog input
I
= Input
O
= Output
P
= Power
OD
= Open-Drain (no P diode to VDD)
Note 1: Alternate assignment for ECCP2/P2A when Configuration bit, CCP2MX, is cleared (Extended Microcontroller mode).
2: Default assignment for ECCP2/P2A for all devices in all operating modes (CCP2MX is set).
3: Default assignments for P1B/P1C/P3B/P3C (ECCPMX Configuration bit is set).
4: Alternate assignment for ECCP2/P2A when CCP2MX is cleared (Microcontroller mode).
5: Alternate assignments for P1B/P1C/P3B/P3C (ECCPMX Configuration bit is cleared).
6: Default assignment for PMP data and control pins when PMPMX Configuration bit is set.
7: Alternate assignment for PMP data and control pins when PMPMX Configuration bit is cleared (programmed).
DS39778D-page 26
© 2009 Microchip Technology Inc.
PIC18F87J11 FAMILY
TABLE 1-4:
PIC18F8XJ1X PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number
Pin
Type
Buffer
Type
Pin Name
Description
80-TQFP
PORTE is a bidirectional I/O port.
RE0/AD8/PMRD/P2D
4
3
RE0
AD8
PMRD
I/O
I/O
I/O
O
ST
TTL
—
Digital I/O.
External memory address/data 8.
Parallel Master Port read strobe.
ECCP2 PWM output D.
(6)
P2D
—
RE1/AD9/PMWR/P2C
RE1
AD9
PMWR
I/O
I/O
I/O
O
ST
TTL
—
Digital I/O.
External memory address/data 9.
Parallel Master Port write strobe.
ECCP2 PWM output C.
(6)
P2C
—
RE2/AD10/PMBE/P2B
78
77
RE2
I/O
I/O
O
ST
TTL
—
Digital I/O.
AD10
PMBE
External memory address/data 10.
Parallel Master Port byte enable.
ECCP2 PWM output B.
(6)
P2B
O
—
RE3/AD11/PMA13/P3C/REFO
RE3
I/O
I/O
O
O
O
ST
TTL
—
—
—
Digital I/O.
AD11
PMA13
External memory address/data 11.
Parallel Master Port address.
ECCP3 PWM output C.
Reference clock out.
(3)
P3C
REFO
RE4/AD12/PMA12/P3B
76
75
74
73
RE4
I/O
I/O
O
ST
TTL
—
Digital I/O.
AD12
PMA12
External memory address/data 12.
Parallel Master Port address.
ECCP3 PWM output B.
(3)
P3B
O
—
RE5/AD13/PMA11/P1C
RE5
I/O
I/O
O
ST
TTL
—
Digital I/O.
AD13
PMA11
External memory address/data 13.
Parallel Master Port address.
ECCP1 PWM output C.
(3)
P1C
O
—
RE6/AD14/PMA10/P1B
RE6
I/O
I/O
O
ST
TTL
—
Digital I/O.
AD14
PMA10
External memory address/data 14.
Parallel Master Port address.
ECCP1 PWM output B.
(3)
P1B
O
—
RE7/AD15/PMA9/ECCP2/P2A
RE7
AD15
PMA9
I/O
I/O
O
I/O
O
ST
TTL
—
ST
—
Digital I/O.
External memory address/data 15.
Parallel Master Port address.
Capture 2 input/Compare 2 output/PWM2 output.
ECCP2 PWM output A.
(4)
ECCP2
(4)
P2A
Legend: TTL = TTL compatible input
ST = Schmitt Trigger input with CMOS levels
CMOS = CMOS compatible input or output
Analog = Analog input
I
= Input
O
= Output
P
= Power
OD
= Open-Drain (no P diode to VDD)
Note 1: Alternate assignment for ECCP2/P2A when Configuration bit, CCP2MX, is cleared (Extended Microcontroller mode).
2: Default assignment for ECCP2/P2A for all devices in all operating modes (CCP2MX is set).
3: Default assignments for P1B/P1C/P3B/P3C (ECCPMX Configuration bit is set).
4: Alternate assignment for ECCP2/P2A when CCP2MX is cleared (Microcontroller mode).
5: Alternate assignments for P1B/P1C/P3B/P3C (ECCPMX Configuration bit is cleared).
6: Default assignment for PMP data and control pins when PMPMX Configuration bit is set.
7: Alternate assignment for PMP data and control pins when PMPMX Configuration bit is cleared (programmed).
© 2009 Microchip Technology Inc.
DS39778D-page 27
PIC18F87J11 FAMILY
TABLE 1-4:
PIC18F8XJ1X PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number
Pin
Type
Buffer
Type
Pin Name
Description
PORTF is a bidirectional I/O port.
80-TQFP
RF1/AN6/C2OUT
RF1
23
18
I/O
I
O
ST
Analog
—
Digital I/O.
Analog input 6.
Comparator 2 output.
AN6
C2OUT
RF2/PMA5/AN7/C1OUT
RF2
PMA5
AN7
I/O
O
I
ST
—
Analog
—
Digital I/O.
Parallel Master Port address.
Analog input 7.
C1OUT
O
Comparator 1 output.
RF3/AN8/C2INB
RF3
17
16
15
I
I
I
ST
Analog
Analog
Digital input.
Analog input 8.
Comparator 2 input B.
AN8
C2INB
RF4/AN9/C2INA
RF4
I
I
I
ST
Analog
Analog
Digital input.
Analog input 8.
Comparator 2 input A.
AN9
C2INA
RF5/PMD2/AN10/
C1INB/CVREF
RF5
I/O
I/O
I
I
O
ST
TTL
Analog
Analog
Analog
Digital I/O.
Parallel Master Port address.
Analog input 10.
Comparator 1 input B.
Comparator reference voltage output.
(7)
PMD2
AN10
C1INB
CVREF
RF6/PMD1/AN11/C1INA
RF6
14
13
I/O
I/O
I
I
ST
TTL
Analog
Analog
Digital I/O.
Parallel Master Port address.
Analog input 11.
(7)
PMD1
AN11
C1INA
Comparator 1 input A.
RF7/PMD0/SS1
RF7
I/O
I/O
I
ST
TTL
TTL
Digital I/O.
Parallel Master Port address.
SPI slave select input.
(7)
PMD0
SS1
Legend: TTL = TTL compatible input
ST = Schmitt Trigger input with CMOS levels
CMOS = CMOS compatible input or output
Analog = Analog input
I
= Input
O
= Output
P
= Power
OD
= Open-Drain (no P diode to VDD)
Note 1: Alternate assignment for ECCP2/P2A when Configuration bit, CCP2MX, is cleared (Extended Microcontroller mode).
2: Default assignment for ECCP2/P2A for all devices in all operating modes (CCP2MX is set).
3: Default assignments for P1B/P1C/P3B/P3C (ECCPMX Configuration bit is set).
4: Alternate assignment for ECCP2/P2A when CCP2MX is cleared (Microcontroller mode).
5: Alternate assignments for P1B/P1C/P3B/P3C (ECCPMX Configuration bit is cleared).
6: Default assignment for PMP data and control pins when PMPMX Configuration bit is set.
7: Alternate assignment for PMP data and control pins when PMPMX Configuration bit is cleared (programmed).
DS39778D-page 28
© 2009 Microchip Technology Inc.
PIC18F87J11 FAMILY
TABLE 1-4:
PIC18F8XJ1X PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number
Pin
Type
Buffer
Type
Pin Name
Description
80-TQFP
PORTG is a bidirectional I/O port.
RG0/PMA8/ECCP3/P3A
5
6
RG0
I/O
O
I/O
O
ST
—
ST
—
Digital I/O.
PMA8
ECCP3
P3A
Parallel Master Port address.
Capture 3 input/Compare 3 output/PWM3 output.
ECCP3 PWM output A.
RG1/PMA7/TX2/CK2
RG1
PMA7
TX2
I/O
O
O
ST
—
—
Digital I/O.
Parallel Master Port address.
EUSART2 asynchronous transmit.
EUSART2 synchronous clock (see related RX2/DT2).
CK2
I/O
ST
RG2/PMA6/RX2/DT2
7
RG2
PMA6
RX2
I/O
I/O
I
ST
—
ST
ST
Digital I/O.
Parallel Master Port address.
EUSART2 asynchronous receive.
EUSART2 synchronous data (see related TX2/CK2).
DT2
I/O
RG3/PMCS1/CCP4/P3D
8
RG3
I/O
I/O
I/O
O
ST
—
ST
—
Digital I/O.
PMCS1
CCP4
P3D
Parallel Master Port chip select 1.
Capture 4 input/Compare 4 output/PWM4 output.
ECCP3 PWM output D.
RG4/PMCS2/CCP5/P1D
10
RG4
I/O
O
I/O
O
ST
—
ST
—
Digital I/O.
PMCS2
CCP5
P1D
Parallel Master Port chip select 2.
Capture 5 input/Compare 5 output/PWM5 output.
ECCP1 PWM output D.
Legend: TTL = TTL compatible input
ST = Schmitt Trigger input with CMOS levels
CMOS = CMOS compatible input or output
Analog = Analog input
I
= Input
O
= Output
P
= Power
OD
= Open-Drain (no P diode to VDD)
Note 1: Alternate assignment for ECCP2/P2A when Configuration bit, CCP2MX, is cleared (Extended Microcontroller mode).
2: Default assignment for ECCP2/P2A for all devices in all operating modes (CCP2MX is set).
3: Default assignments for P1B/P1C/P3B/P3C (ECCPMX Configuration bit is set).
4: Alternate assignment for ECCP2/P2A when CCP2MX is cleared (Microcontroller mode).
5: Alternate assignments for P1B/P1C/P3B/P3C (ECCPMX Configuration bit is cleared).
6: Default assignment for PMP data and control pins when PMPMX Configuration bit is set.
7: Alternate assignment for PMP data and control pins when PMPMX Configuration bit is cleared (programmed).
© 2009 Microchip Technology Inc.
DS39778D-page 29
PIC18F87J11 FAMILY
TABLE 1-4:
PIC18F8XJ1X PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number
Pin
Type
Buffer
Type
Pin Name
Description
80-TQFP
PORTH is a bidirectional I/O port.
RH0/A16
RH0
79
80
1
I/O
O
ST
TTL
Digital I/O.
External memory address/data 16.
A16
RH1/A17
RH1
I/O
O
ST
TTL
Digital I/O.
External memory address/data 17.
A17
RH2/A18/PMD7
RH2
A18
PMD7
I/O
O
I/O
ST
TTL
TTL
Digital I/O.
External memory address/data 18.
Parallel Master Port data.
(7)
RH3/A19/PMD6
2
RH3
A19
PMD6
I/O
O
I/O
ST
TTL
TTL
Digital I/O.
External memory address/data 19.
Parallel Master Port data.
(7)
RH4/PMD3/AN12/
P3C/C2INC
RH4
22
I/O
I/O
I
O
I
ST
TTL
Analog
—
Digital I/O.
Parallel Master Port address.
Analog input 12.
ECCP3 PWM output C.
Comparator 2 input C.
(7)
PMD3
AN12
(5)
P3C
C2INC
Analog
RH5/PMBE/AN13/
P3B/C2IND
RH5
21
20
19
I/O
O
I
O
I
ST
—
Analog
—
Digital I/O.
Parallel Master Port byte enable.
Analog input 13.
ECCP3 PWM output B.
Comparator 2 input D.
(7)
PMBE
AN13
(5)
P3B
C2IND
Analog
RH6/PMRD/AN14/
P1C/C1INC
RH6
I/O
I/O
I
O
I
ST
—
Analog
—
Digital I/O.
Parallel Master Port read strobe.
Analog input 14.
ECCP1 PWM output C.
Comparator 1 input C.
(7)
PMRD
AN14
(5)
P1C
C1INC
Analog
RH7/PMWR/AN15/P1B
RH7
I/O
I/O
I
ST
—
Analog
—
Digital I/O.
Parallel Master Port write strobe.
Analog input 15.
(7)
PMWR
AN15
(5)
P1B
O
ECCP1 PWM output B.
Legend: TTL = TTL compatible input
ST = Schmitt Trigger input with CMOS levels
CMOS = CMOS compatible input or output
Analog = Analog input
I
= Input
O
= Output
P
= Power
OD
= Open-Drain (no P diode to VDD)
Note 1: Alternate assignment for ECCP2/P2A when Configuration bit, CCP2MX, is cleared (Extended Microcontroller mode).
2: Default assignment for ECCP2/P2A for all devices in all operating modes (CCP2MX is set).
3: Default assignments for P1B/P1C/P3B/P3C (ECCPMX Configuration bit is set).
4: Alternate assignment for ECCP2/P2A when CCP2MX is cleared (Microcontroller mode).
5: Alternate assignments for P1B/P1C/P3B/P3C (ECCPMX Configuration bit is cleared).
6: Default assignment for PMP data and control pins when PMPMX Configuration bit is set.
7: Alternate assignment for PMP data and control pins when PMPMX Configuration bit is cleared (programmed).
DS39778D-page 30
© 2009 Microchip Technology Inc.
PIC18F87J11 FAMILY
TABLE 1-4:
PIC18F8XJ1X PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number
Pin
Type
Buffer
Type
Pin Name
Description
PORTJ is a bidirectional I/O port.
80-TQFP
RJ0/ALE
RJ0
62
61
60
59
39
40
41
42
I/O
O
ST
—
Digital I/O.
External memory address latch enable.
ALE
RJ1/OE
RJ1
I/O
O
ST
—
Digital I/O.
External memory output enable.
OE
RJ2/WRL
RJ2
I/O
O
ST
—
Digital I/O.
External memory write low control.
WRL
RJ3/WRH
RJ3
I/O
O
ST
—
Digital I/O.
External memory write high control.
WRH
RJ4/BA0
RJ4
I/O
O
ST
—
Digital I/O.
External memory byte address 0 control.
BA0
RJ5/CE
RJ5
I/O
O
ST
—
Digital I/O
External memory chip enable control.
CE
RJ6/LB
RJ6
I/O
O
ST
—
Digital I/O.
External memory low byte control.
LB
RJ7/UB
RJ7
I/O
O
ST
—
Digital I/O.
External memory high byte control.
UB
VSS
11, 31, 51,
70
P
—
Ground reference for logic and I/O pins.
VDD
32, 48, 71
P
P
P
I
—
—
Positive supply for peripheral digital logic and I/O pins.
Ground reference for analog modules.
Positive supply for analog modules.
AVss
26
25
24
12
AVDD
—
ENVREG
ST
Enable for on-chip voltage regulator.
VDDCORE/VCAP
VDDCORE
Core logic power or external filter capacitor connection.
Positive supply for microcontroller core logic
(regulator disabled).
P
P
—
—
VCAP
External filter capacitor connection (regulator enabled).
Legend: TTL = TTL compatible input
ST = Schmitt Trigger input with CMOS levels
CMOS = CMOS compatible input or output
Analog = Analog input
I
= Input
O
= Output
P
= Power
OD
= Open-Drain (no P diode to VDD)
Note 1: Alternate assignment for ECCP2/P2A when Configuration bit, CCP2MX, is cleared (Extended Microcontroller mode).
2: Default assignment for ECCP2/P2A for all devices in all operating modes (CCP2MX is set).
3: Default assignments for P1B/P1C/P3B/P3C (ECCPMX Configuration bit is set).
4: Alternate assignment for ECCP2/P2A when CCP2MX is cleared (Microcontroller mode).
5: Alternate assignments for P1B/P1C/P3B/P3C (ECCPMX Configuration bit is cleared).
6: Default assignment for PMP data and control pins when PMPMX Configuration bit is set.
7: Alternate assignment for PMP data and control pins when PMPMX Configuration bit is cleared (programmed).
© 2009 Microchip Technology Inc.
DS39778D-page 31
PIC18F87J11 FAMILY
NOTES:
DS39778D-page 32
© 2009 Microchip Technology Inc.
PIC18F87J11 FAMILY
All of these modes are selected by the user by
programming the FOSC2:FOSC0 Configuration bits.
2.0
2.1
OSCILLATOR
CONFIGURATIONS
In addition, PIC18F87J11 Family devices can switch
between different clock sources, either under software
control or automatically under certain conditions. This
allows for additional power savings by managing
device clock speed in real time without resetting the
application.
Oscillator Types
The PIC18F87J11 family of devices can be operated in
eight different oscillator modes:
1. HS
High-Speed Crystal/Resonator
2. HSPLL
High-Speed Crystal/Resonator
with Software PLL Control
The clock sources for the PIC18F87J11 family of
devices are shown in Figure 2-1.
3. EC
External Clock with FOSC/4 Output
4. ECPLL
External Clock with Software PLL
Control
5. INTIO1
6. INTIO2
Internal Oscillator Block with FOSC/4
Output on RA6 and I/O on RA7
Internal Oscillator Block with I/O on
RA6 and RA7
7. INTPLL1 Internal Oscillator Block with Software
PLL Control, FOSC/4 Output on RA6
and I/O on RA7
8. INTPLL2 Internal Oscillator Block with Software
PLL Control and I/O on RA6 and RA7
FIGURE 2-1:
PIC18F87J11 FAMILY CLOCK DIAGRAM
PIC18F87J11 Family
Primary Oscillator
HS, EC
HSPLL, ECPLL, INTPLL
T1OSC
OSC2
OSCTUNE<6>
Sleep
4 x PLL
OSC1
Secondary Oscillator
Peripherals
T1OSO
T1OSCEN
Enable
Oscillator
T1OSI
OSCCON<6:4>
Internal Oscillator
CPU
OSCCON<6:4>
8 MHz
111
110
101
100
011
010
001
4 MHz
2 MHz
Internal
Oscillator
Block
IDLEN
Clock
Control
1 MHz
500 kHz
250 kHz
125 kHz
31 kHz
8 MHz
Source
8 MHz
(INTOSC)
FOSC2:FOSC0 OSCCON<1:0>
Clock Source Option
for Other Modules
1
0
000
INTRC
Source
OSCTUNE<7>
31 kHz (INTRC)
WDT, PWRT, FSCM
and Two-Speed Start-up
© 2009 Microchip Technology Inc.
DS39778D-page 33
PIC18F87J11 FAMILY
The OSCTUNE register (Register 2-2) controls the
tuning and operation of the internal oscillator block. It
also implements the PLLEN bits which control the
operation of the Phase Locked Loop (PLL) (see
Section 2.4.3 “PLL Frequency Multiplier”).
2.2
Control Registers
The OSCCON register (Register 2-1) controls the main
aspects of the device clock’s operation. It selects the
oscillator type to be used, which of the power-managed
modes to invoke and the output frequency of the
INTOSC source. It also provides status on the oscillators.
REGISTER 2-1:
OSCCON: OSCILLATOR CONTROL REGISTER(1)
R/W-0
IDLEN
bit 7
R/W-1
IRCF2(3)
R/W-1
IRCF1(3)
R/W-0
IRCF0(3)
R(2)
U-1
—
R/W-0
SCS1(5)
R/W-0
SCS0(5)
OSTS
bit 0
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
-n = Value at POR
bit 7
IDLEN: Idle Enable bit
1= Device enters an Idle mode when a SLEEPinstruction is executed
0= Device enters Sleep mode when a SLEEPinstruction is executed
bit 6-4
IRCF2:IRCF0: INTOSC Source Frequency Select bits(3)
111= 8 MHz (INTOSC drives clock directly)
110= 4 MHz (default)
101= 2 MHz
100= 1 MHz
011= 500 kHz
010= 250 kHz
001= 125 kHz
000= 31 kHz (from either INTOSC/256 or INTRC)(4)
bit 3
OSTS: Oscillator Start-up Timer Time-out Status bit(2)
1= Oscillator Start-up Timer (OST) time-out has expired; primary oscillator is running
0= Oscillator Start-up Timer (OST) time-out is running; primary oscillator is not ready
bit 2
Unimplemented: Read as ‘1’
bit 1-0
SCS1:SCS0: System Clock Select bits(5)
11= Internal oscillator block
10= Primary oscillator
01= Timer1 oscillator
00= Default primary oscillator (as defined by FOSC2:FOSC0 Configuration bits)
Note 1: Default (legacy) SFR at this address, available when WDTCON<4> = 0.
2: Reset state depends on state of the IESO Configuration bit.
3: Modifying these bits will cause an immediate clock frequency switch if the internal oscillator is providing
the device clocks.
4: Source selected by the INTSRC bit (OSCTUNE<7>), see text.
5: Modifying these bits will cause an immediate clock source switch.
DS39778D-page 34
© 2009 Microchip Technology Inc.
PIC18F87J11 FAMILY
REGISTER 2-2:
OSCTUNE: OSCILLATOR TUNING REGISTER
R/W-0
INTSRC
bit 7
R/W-0
R/W-0
TUN5
R/W-0
TUN4
R/W-0
TUN3
R/W-0
TUN2
R/W-0
TUN1
R/W-0
TUN0
PLLEN
bit 0
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
-n = Value at POR
bit 7
bit 6
INTSRC: Internal Oscillator Low-Frequency Source Select bit
1= 31.25 kHz device clock derived from 8 MHz INTOSC source (divide-by-256 enabled)
0= 31 kHz device clock derived from INTRC 31 kHz oscillator
PLLEN: Frequency Multiplier PLL Enable bit
1= PLL enabled
0= PLL disabled
bit 5-0
TUN5:TUN0: Fast RC Oscillator (INTOSC) Frequency Tuning bits
011111= Maximum frequency
•
•
•
•
000001
000000= Center frequency. Fast RC oscillator is running at the calibrated frequency.
111111
•
•
•
•
100000= Minimum frequency
functions such as a Real-Time Clock (RTC). The
Timer1 oscillator is discussed in greater detail in
Section 13.0 “Timer1 Module”
2.3
Clock Sources and
Oscillator Switching
Essentially, PIC18F87J11 Family devices have three
independent clock sources:
In addition to being a primary clock source in some cir-
cumstances, the internal oscillator is available as a
power-managed mode clock source. The INTRC
source is also used as the clock source for several
special features, such as the WDT and Fail-Safe Clock
Monitor. The internal oscillator block is discussed in
more detail in Section 2.5 “Internal Oscillator
Block”.
• Primary oscillators
• Secondary oscillators
• Internal oscillator
The primary oscillators can be thought of as the main
device oscillators. These are any external oscillators
connected to the OSC1 and OSC2 pins, and include
the External Crystal and Resonator modes and the
External Clock modes. If selected by the
FOSC2:FOSC0 Configuration bits, the internal
oscillator block (either the 31 kHz INTRC or the 8 MHz
INTOSC source) may be considered a primary
oscillator. The particular mode is defined by the FOSC
Configuration bits. The details of these modes are
covered in Section 2.4 “External Oscillator Modes”.
The PIC18F87J11 Family includes features that allow
the device clock source to be switched from the main
oscillator, chosen by device configuration, to one of the
alternate clock sources. When an alternate clock
source is enabled, various power-managed operating
modes are available.
The secondary oscillators are external clock sources
that are not connected to the OSC1 or OSC2 pins.
These sources may continue to operate even after the
controller is placed in a power-managed mode.
PIC18F87J11 Family devices offer the Timer1 oscillator
as a secondary oscillator source. This oscillator, in all
power-managed modes, is often the time base for
© 2009 Microchip Technology Inc.
DS39778D-page 35
PIC18F87J11 FAMILY
2.3.1
CLOCK SOURCE SELECTION
2.3.1.1
System Clock Selection and Device
Resets
The System Clock Select bits, SCS1:SCS0
(OSCCON<1:0>), select the clock source. The avail-
able clock sources are the primary clock defined by the
FOSC2:FOSC0 Configuration bits, the secondary
clock (Timer1 oscillator) and the internal oscillator. The
clock source changes after one or more of the bits are
written to, following a brief clock transition interval.
Since the SCS bits are cleared on all forms of Reset,
this means the primary oscillator defined by the
FOSC2:FOSC0 Configuration bits is used as the
primary clock source on device Resets. This could
either be the internal oscillator block by itself, or one of
the other primary clock source (HS, EC, HSPLL,
ECPLL1/2 or INTPLL1/2).
The OSTS (OSCCON<3>) and T1RUN (T1CON<6>)
bits indicate which clock source is currently providing
the device clock. The OSTS bit indicates that the
Oscillator Start-up Timer (OST) has timed out and the
primary clock is providing the device clock in primary
clock modes. The T1RUN bit indicates when the
Timer1 oscillator is providing the device clock in sec-
ondary clock modes. In power-managed modes, only
one of these bits will be set at any time. If neither of
these bits is set, the INTRC is providing the clock, or
the internal oscillator has just started and is not yet
stable.
In those cases when the internal oscillator block, with-
out PLL, is the default clock on Reset, the Fast RC
oscillator (INTOSC) will be used as the device clock
source. It will initially start at 4 MHz; the postscaler
selection that corresponds to the Reset value of the
IRCF2:IRCF0 bits (‘110’).
Regardless of which primary oscillator is selected,
INTRC will always be enabled on device power-up. It
serves as the clock source until the device has loaded
its configuration values from memory. It is at this point
that the FOSC Configuration bits are read and the
oscillator selection of the operational mode is made.
The IDLEN bit determines if the device goes into Sleep
mode or one of the Idle modes when the SLEEP
instruction is executed.
Note that either the primary clock source, or the internal
oscillator, will have two bit setting options for the possible
values of the SCS1:SCS0 bits at any given time.
The use of the flag and control bits in the OSCCON
register is discussed in more detail in Section 3.0
“Power-Managed Modes”.
2.3.2
OSCILLATOR TRANSITIONS
PIC18F87J11 family devices contain circuitry to
prevent clock “glitches” when switching between clock
sources. A short pause in the device clock occurs dur-
ing the clock switch. The length of this pause is the sum
of two cycles of the old clock source and three to four
cycles of the new clock source. This formula assumes
that the new clock source is stable.
Note 1: The Timer1 oscillator must be enabled to
select the secondary clock source. The
Timer1 oscillator is enabled by setting the
T1OSCEN bit in the Timer1 Control regis-
ter (T1CON<3>). If the Timer1 oscillator is
not enabled, then any attempt to select a
secondary clock source when executing a
SLEEPinstruction will be ignored.
Clock transitions are discussed in greater detail in
Section 3.1.2 “Entering Power-Managed Modes”.
2: It is recommended that the Timer1
oscillator be operating and stable before
executing the SLEEPinstruction or a very
long delay may occur while the Timer1
oscillator starts.
DS39778D-page 36
© 2009 Microchip Technology Inc.
PIC18F87J11 FAMILY
TABLE 2-2:
CAPACITOR SELECTION FOR
CRYSTAL OSCILLATOR
2.4
External Oscillator Modes
2.4.1
CRYSTAL OSCILLATOR/CERAMIC
RESONATORS (HS MODES)
Typical Capacitor Values
Crystal
Freq.
Tested:
Osc Type
In HS or HSPLL Oscillator modes, a crystal or ceramic
resonator is connected to the OSC1 and OSC2 pins to
establish oscillation. Figure 2-2 shows the pin
connections.
C1
C2
HS
4 MHz
8 MHz
20 MHz
27 pF
22 pF
15 pF
27 pF
22 pF
15 pF
The oscillator design requires the use of a crystal rated
for parallel resonant operation.
Capacitor values are for design guidance only.
Note:
Use of a crystal rated for series resonant
operation may give a frequency out of the
crystal manufacturer’s specifications.
Different capacitor values may be required to produce
acceptable oscillator operation. The user should test
the performance of the oscillator over the expected
VDD and temperature range for the application.
TABLE 2-1:
CAPACITOR SELECTION FOR
CERAMIC RESONATORS
Refer to the Microchip application notes cited in
Table 2-1 for oscillator specific information. Also see
the notes following this table for additional
information.
Typical Capacitor Values Used:
Mode
Freq.
OSC1
OSC2
HS
8.0 MHz
16.0 MHz
27 pF
22 pF
27 pF
22 pF
Note 1: Higher capacitance increases the stability
of oscillator but also increases the start-up
time.
Capacitor values are for design guidance only.
Different capacitor values may be required to produce
acceptable oscillator operation. The user should test
the performance of the oscillator over the expected
VDD and temperature range for the application. Refer
to the following application notes for oscillator specific
information:
2: Since each resonator/crystal has its own
characteristics, the user should consult
the resonator/crystal manufacturer for
appropriate
values
of
external
components.
3: Rs may be required to avoid overdriving
• AN588, “PIC® Microcontroller Oscillator Design
crystals with low drive level specification.
Guide”
4: Always verify oscillator performance over
the VDD and temperature range that is
expected for the application.
• AN826, “Crystal Oscillator Basics and Crystal
Selection for rfPIC® and PIC® Devices”
• AN849, “Basic PIC® Oscillator Design”
• AN943, “Practical PIC® Oscillator Analysis and
Design”
FIGURE 2-2:
CRYSTAL/CERAMIC
RESONATOROPERATION
(HS OR HSPLL
• AN949, “Making Your Oscillator Work”
CONFIGURATION)
See the notes following Table 2-2 for additional
information.
(1)
C1
OSC1
To
Internal
Logic
XTAL
(3)
RF
Sleep
OSC2
(2)
RS
(1)
PIC18F87J11
C2
Note 1: See Table 2-1 and Table 2-2 for initial values of
C1 and C2.
2: A series resistor (RS) may be required for AT
strip cut crystals.
3: RF varies with the oscillator mode chosen.
© 2009 Microchip Technology Inc.
DS39778D-page 37
PIC18F87J11 FAMILY
2.4.2
EXTERNAL CLOCK INPUT
(EC MODES)
2.4.3.1
HSPLL and ECPLL Modes
The HSPLL and ECPLL modes provide the ability to
selectively run the device at 4 times the external
oscillating source to produce frequencies up to
40 MHz.
The EC and ECPLL Oscillator modes require an
external clock source to be connected to the OSC1 pin.
There is no oscillator start-up time required after a
Power-on Reset or after an exit from Sleep mode.
The PLL is enabled by programming the
FOSC2:FOSC0 Configuration bits to either ‘111’ (for
ECPLL) or ‘101’ (for HSPLL). In addition, the PLLEN bit
(OSCTUNE<6>) must also be set. Clearing PLLEN
disables the PLL, regardless of the chosen oscillator
configuration. It also allows additional flexibility for
controlling the application’s clock speed in software.
In the EC Oscillator mode, the oscillator frequency
divided by 4 is available on the OSC2 pin. This signal
may be used for test purposes or to synchronize other
logic. Figure 2-3 shows the pin connections for the EC
Oscillator mode.
FIGURE 2-3:
EXTERNAL CLOCK
INPUT OPERATION
(EC CONFIGURATION)
FIGURE 2-5:
PLL BLOCK DIAGRAM
HSPLL or ECPLL (CONFIG2L)
PLL Enable (OSCTUNE)
OSC1/CLKI
Clock from
Ext. System
PIC18F87J11
OSC2
OSC1
OSC2/CLKO
FOSC/4
Phase
Comparator
FIN
HS or EC
Mode
FOUT
An external clock source may also be connected to the
OSC1 pin in the HS mode, as shown in Figure 2-4. In
this configuration, the divide-by-4 output on OSC2 is
not available. Current consumption in this configuration
will be somewhat higher than EC mode, as the internal
oscillator’s feedback circuitry will be enabled (in EC
mode, the feedback circuit is disabled).
Loop
Filter
VCO
÷4
SYSCLK
FIGURE 2-4:
EXTERNAL CLOCK INPUT
OPERATION (HS OSC
CONFIGURATION)
2.4.3.2
PLL and INTOSC
The PLL is also available to the internal oscillator block
when the internal oscillator block is configured as the
primary clock source. In this configuration, the PLL is
enabled in software and generates a clock output of up
to 32 MHz. The operation of INTOSC with the PLL is
described in Section 2.5.2 “INTPLL Modes”.
OSC1
Clock from
Ext. System
PIC18F87J11
(HS Mode)
OSC2
Open
2.4.3
PLL FREQUENCY MULTIPLIER
A Phase Locked Loop (PLL) circuit is provided as an
option for users who want to use a lower frequency
oscillator circuit, or to clock the device up to its highest
rated frequency from a crystal oscillator. This may be
useful for customers who are concerned with EMI due
to high-frequency crystals, or users who require higher
clock speeds from an internal oscillator.
DS39778D-page 38
© 2009 Microchip Technology Inc.
PIC18F87J11 FAMILY
FIGURE 2-6: INTIO1 OSCILLATOR MODE
2.5
Internal Oscillator Block
The PIC18F87J11 Family of devices includes an
internal oscillator block which generates two different
clock signals; either can be used as the microcon-
troller’s clock source. This may eliminate the need for
an external oscillator circuit on the OSC1 and/or OSC2
pins.
I/O (OSC1)
RA7
PIC18F87J11
OSC2
FOSC/4
The main output is the Fast RC oscillator, or INTOSC,
an 8 MHz clock source which can be used to directly
drive the device clock. It also drives a postscaler, which
can provide a range of clock frequencies from 31 kHz
to 4 MHz. INTOSC is enabled when a clock frequency
from 125 kHz to 8 MHz is selected. The INTOSC out-
put can also be enabled when 31 kHz is selected,
depending on the INTSRC bit (OSCTUNE<7>).
FIGURE 2-7: INTIO2 OSCILLATOR MODE
RA7
RA6
I/O (OSC1)
PIC18F87J11
I/O (OSC2)
The other clock source is the internal RC oscillator
(INTRC), which provides a nominal 31 kHz output.
INTRC is enabled if it is selected as the device clock
source; it is also enabled automatically when any of the
following are enabled:
2.5.2
INTPLL MODES
The 4x Phase Locked Loop (PLL) can be used with the
internal oscillator block to produce faster device clock
speeds than are normally possible with the internal
oscillator sources. When enabled, the PLL produces a
clock speed of 16 MHz or 32 MHz.
• Power-up Timer
• Fail-Safe Clock Monitor
• Watchdog Timer
PLL operation is controlled through software. The con-
trol bit, PLLEN (OSCTUNE<6>), is used to enable or
disable its operation. The PLL is available only to
INTOSC when the device is configured to use one of
the INTPLL modes as the primary clock source
(FOSC2:FOSC0 = 011 or 010). Additionally, the PLL
will only function when the selected output frequency is
either 4 MHz or 8 MHz (OSCCON<6:4> = 111or 110).
• Two-Speed Start-up
These features are discussed in greater detail in
Section 24.0 “Special Features of the CPU”.
The clock source frequency (INTOSC direct, INTOSC
with postscaler or INTRC direct) is selected by config-
uring the IRCF bits of the OSCCON register. The
default frequency on device Resets is 4 MHz.
Like the INTIO modes, there are two distinct INTPLL
modes available:
2.5.1
INTIO MODES
• In INTPLL1 mode, the OSC2 pin outputs FOSC/4,
while OSC1 functions as RA7 for digital input and
output. Externally, this is identical in appearance
to INTIO1 (Figure 2-6).
Using the internal oscillator as the clock source elimi-
nates the need for up to two external oscillator pins,
which can then be used for digital I/O. Two distinct
oscillator configurations, which are determined by the
FOSC Configuration bits, are available:
• In INTPLL2 mode, OSC1 functions as RA7 and
OSC2 functions as RA6, both for digital input and
output. Externally, this is identical to INTIO2
(Figure 2-7).
• In INTIO1 mode, the OSC2 pin outputs FOSC/4,
while OSC1 functions as RA7 (see Figure 2-6) for
digital input and output.
• In INTIO2 mode, OSC1 functions as RA7 and
OSC2 functions as RA6 (see Figure 2-7), both for
digital input and output.
© 2009 Microchip Technology Inc.
DS39778D-page 39
PIC18F87J11 FAMILY
2.5.3
INTERNAL OSCILLATOR OUTPUT
FREQUENCY AND TUNING
2.5.4.3
Compensating with the CCP Module
in Capture Mode
The internal oscillator block is calibrated at the factory
to produce an INTOSC output frequency of 8 MHz. It
can be adjusted in the user’s application by writing to
TUN5:TUN0 (OSCTUNE<5:0>) in the OSCTUNE
register (Register 2-2).
A CCP module can use free-running Timer1 (or
Timer3), clocked by the internal oscillator block and an
external event with a known period (i.e., AC power
frequency). The time of the first event is captured in the
CCPRxH:CCPRxL registers and is recorded for use
later. When the second event causes a capture, the
time of the first event is subtracted from the time of the
second event. Since the period of the external event is
known, the time difference between events can be
calculated.
When the OSCTUNE register is modified, the INTOSC
frequency will begin shifting to the new frequency. The
oscillator will stabilize within 1 ms. Code execution
continues during this shift and there is no indication that
the shift has occurred.
If the measured time is much greater than the
calculated time, the internal oscillator block is running
too fast. To compensate, decrement the OSCTUNE
register. If the measured time is much less than the
calculated time, the internal oscillator block is running
too slow. To compensate, increment the OSCTUNE
register.
The INTRC oscillator operates independently of the
INTOSC source. Any changes in INTOSC across
voltage and temperature are not necessarily reflected
by changes in INTRC or vice versa. The frequency of
INTRC is not affected by OSCTUNE.
2.5.4
INTOSC FREQUENCY DRIFT
The INTOSC frequency may drift as VDD or tempera-
ture changes, and can affect the controller operation in
a variety of ways. It is possible to adjust the INTOSC
frequency by modifying the value in the OSCTUNE reg-
ister. Depending on the device, this may have no effect
on the INTRC clock source frequency.
2.6
Reference Clock Output
In addition to the FOSC/4 clock output in certain oscilla-
tor modes, the device clock in the PIC18F87J11 family
can also be configured to provide a reference clock out-
put signal to a port pin. This feature is available in all
oscillator configurations and allows the user to select a
greater range of clock sub-multiples to drive external
devices in the application.
Tuning INTOSC requires knowing when to make the
adjustment, in which direction it should be made, and in
some cases, how large a change is needed. Three
compensation techniques are shown here.
This reference clock output is controlled by the
REFOCON register (Register 2-3). Setting the ROON
bit (REFOCON<7>) makes the clock signal available
on the REFO (RE3) pin. The RODIV3:RODIV0 bits
enable the selection of 16 different clock divider
options.
2.5.4.1
Compensating with the EUSART
An adjustment may be required when the EUSART
begins to generate framing errors or receives data with
errors while in Asynchronous mode. Framing errors
indicate that the device clock frequency is too high. To
adjust for this, decrement the value in OSCTUNE to
reduce the clock frequency. On the other hand, errors
in data may suggest that the clock speed is too low. To
compensate, increment OSCTUNE to increase the
clock frequency.
The ROSSLP and ROSEL bits (REFOCON<5:4>) con-
trol the availability of the reference output during Sleep
mode. The ROSEL bit determines if the oscillator on
OSC1 and OSC2, or the current system clock source,
is used for the reference clock output. The ROSSLP bit
determines if the reference source is available on RE3
when the device is in Sleep mode.
2.5.4.2
Compensating with the Timers
To use the reference clock output in Sleep mode, both
the ROSSLP and ROSEL bits must be set. The device
clock must also be configured for an EC or HS mode;
otherwise, the oscillator on OSC1 and OSC2 will be
powered down when the device enters Sleep mode.
Clearing the ROSEL bit allows the reference output
frequency to change as the system clock changes
during any clock switches.
This technique compares device clock speed to some
reference clock. Two timers may be used; one timer is
clocked by the peripheral clock, while the other is
clocked by a fixed reference source, such as the
Timer1 oscillator.
Both timers are cleared, but the timer clocked by the
reference generates interrupts. When an interrupt
occurs, the internally clocked timer is read and both
timers are cleared. If the internally clocked timer value
is much greater than expected, then the internal
oscillator block is running too fast. To adjust for this,
decrement the OSCTUNE register.
The REFOCON register is an alternate SFR, and
shares the same memory address as the OSCCON
register. It is accessed by setting the ADSHR bit in the
WDTCON register (WDTCON<4>).
DS39778D-page 40
© 2009 Microchip Technology Inc.
PIC18F87J11 FAMILY
REGISTER 2-3:
REFOCON: REFERENCE OSCILLATOR CONTROL REGISTER
R/W-0
ROON
bit 7
U-0
—
R/W-0
R/W-0
ROSEL(1)
R/W-0
R/W-0
R/W-0
R/W-0
ROSSLP
RODIV3
RODIV2
RODIV1
RODIV0
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7
ROON: Reference Oscillator Output Enable bit
1= Reference oscillator output available on REFO pin
0= Reference oscillator output disabled
bit 6
bit 5
Unimplemented: Read as ‘0’
ROSSLP: Reference Oscillator Output Stop in Sleep bit
1= Reference oscillator continues to run in Sleep
0= Reference oscillator is disabled in Sleep
bit 4
ROSEL: Reference Oscillator Source Select bit(1)
1= Primary oscillator (EC or HS) used as the base clock
0= System clock used as the base clock; base clock reflects any clock switching of the device
bit 3-0
RODIV3:RODIV0: Reference Oscillator Divisor Select bits
1111= Base clock value divided by 32,768
1110= Base clock value divided by 16,384
1101= Base clock value divided by 8,192
1100= Base clock value divided by 4,096
1011= Base clock value divided by 2,048
1010= Base clock value divided by 1,024
1001= Base clock value divided by 512
1000= Base clock value divided by 256
0111= Base clock value divided by 128
0110= Base clock value divided by 64
0101= Base clock value divided by 32
0100= Base clock value divided by 16
0011= Base clock value divided by 8
0010= Base clock value divided by 4
0001= Base clock value divided by 2
0000= Base clock value
Note 1: If ROSEL = 1, an EC or HS oscillator must be configured as the default oscillator with the FOSC Configuration
bits to maintain clock output during Sleep mode.
© 2009 Microchip Technology Inc.
DS39778D-page 41
PIC18F87J11 FAMILY
Timer1 oscillator may be operating to support a Real-
Time Clock (RTC). Other features may be operating
that do not require a device clock source (i.e., MSSP
slave, PSP, INTx pins and others). Peripherals that
may add significant current consumption are listed in
Section 27.2 “DC Characteristics: Power-Down and
Supply Current”.
2.7
Effects of Power-Managed Modes
on the Various Clock Sources
When PRI_IDLE mode is selected, the designated pri-
mary oscillator continues to run without interruption.
For all other power-managed modes, the oscillator
using the OSC1 pin is disabled. The OSC1 pin (and
OSC2 pin if used by the oscillator) will stop oscillating.
2.8
Power-up Delays
In secondary clock modes (SEC_RUN and
SEC_IDLE), the Timer1 oscillator is operating and
providing the device clock. The Timer1 oscillator may
also run in all power-managed modes if required to
clock Timer1 or Timer3.
Power-up delays are controlled by two timers, so that
no external Reset circuitry is required for most applica-
tions. The delays ensure that the device is kept in
Reset until the device power supply is stable under nor-
mal circumstances and the primary clock is operating
and stable. For additional information on power-up
delays, see Section 4.6 “Power-up Timer (PWRT)”.
In RC_RUN and RC_IDLE modes, the internal
oscillator provides the device clock source. The 31 kHz
INTRC output can be used directly to provide the clock
and may be enabled to support various special
features, regardless of the power-managed mode (see
Section 24.2 “Watchdog Timer (WDT)” through
Section 24.5 “Fail-Safe Clock Monitor” for more
information on WDT, Fail-Safe Clock Monitor and
Two-Speed Start-up).
The first timer is the Power-up Timer (PWRT), which
provides a fixed delay on power-up (parameter 33,
Table 27-12); it is always enabled.
The second timer is the Oscillator Start-up Timer
(OST), intended to keep the chip in Reset until the
crystal oscillator is stable (HS modes). The OST does
this by counting 1024 oscillator cycles before allowing
the oscillator to clock the device.
If the Sleep mode is selected, all clock sources are
stopped. Since all the transistor switching currents
have been stopped, Sleep mode achieves the lowest
current consumption of the device (only leakage
currents).
There is a delay of interval TCSD (parameter 38,
Table 27-12), following POR, while the controller
becomes ready to execute instructions.
Enabling any on-chip feature that will operate during
Sleep will increase the current consumed during Sleep.
The INTRC is required to support WDT operation. The
TABLE 2-3:
OSC1 AND OSC2 PIN STATES IN SLEEP MODE
Oscillator Mode
OSC1 Pin
OSC2 Pin
EC, ECPLL
HS, HSPLL
Floating, pulled by external clock
At logic low (clock/4 output)
Feedback inverter disabled at quiescent
voltage level
Feedback inverter disabled at quiescent
voltage level
INTOSC, INTPLL1/2
I/O pin RA6, direction controlled by
TRISA<6>
I/O pin RA6, direction controlled by
TRISA<7>
Note:
See Section 4.0 “Reset” for time-outs due to Sleep and MCLR Reset.
DS39778D-page 42
© 2009 Microchip Technology Inc.
PIC18F87J11 FAMILY
3.1.1
CLOCK SOURCES
3.0
POWER-MANAGED MODES
The SCS1:SCS0 bits allow the selection of one of three
clock sources for power-managed modes. They are:
The PIC18F87J11 Family of devices provides the ability
to manage power consumption by simply managing
clocking to the CPU and the peripherals. In general, a
lower clock frequency and a reduction in the number of
circuits being clocked constitutes lower consumed
power. For the sake of managing power in an
application, there are three primary modes of operation:
• the primary clock, as defined by the
FOSC2:FOSC0 Configuration bits
• the secondary clock (Timer1 oscillator)
• the internal oscillator
3.1.2
ENTERING POWER-MANAGED
MODES
• Run mode
• Idle mode
• Sleep mode
Switching from one power-managed mode to another
begins by loading the OSCCON register. The
SCS1:SCS0 bits select the clock source and determine
which Run or Idle mode is to be used. Changing these
bits causes an immediate switch to the new clock
source, assuming that it is running. The switch may
also be subject to clock transition delays. These are
discussed in Section 3.1.3 “Clock Transitions and
Status Indicators” and subsequent sections.
These modes define which portions of the device are
clocked and at what speed. The Run and Idle modes
may use any of the three available clock sources (pri-
mary, secondary or internal oscillator block); the Sleep
mode does not use a clock source.
The power-managed modes include several
power-saving features offered on previous devices.
One is the clock switching feature, offered in other
PIC18 devices, allowing the controller to use the
Timer1 oscillator in place of the primary oscillator. Also
included is the Sleep mode, offered by all PIC®
devices, where all device clocks are stopped.
Entry to the power-managed Idle or Sleep modes is
triggered by the execution of a SLEEPinstruction. The
actual mode that results depends on the status of the
IDLEN bit.
Depending on the current mode and the mode being
switched to, a change to a power-managed mode does
not always require setting all of these bits. Many
transitions may be done by changing the oscillator
select bits, or changing the IDLEN bit, prior to issuing a
SLEEP instruction. If the IDLEN bit is already
configured correctly, it may only be necessary to
perform a SLEEP instruction to switch to the desired
mode.
3.1
Selecting Power-Managed Modes
Selecting
a power-managed mode requires two
decisions: if the CPU is to be clocked or not and which
clock source is to be used. The IDLEN bit
(OSCCON<7>) controls CPU clocking, while the
SCS1:SCS0 bits (OSCCON<1:0>) select the clock
source. The individual modes, bit settings, clock
sources and affected modules are summarized in
Table 3-1.
TABLE 3-1:
Mode
POWER-MANAGED MODES
OSCCON<7,1:0> Module Clocking
IDLEN(1)
SCS1:SCS0 CPU Peripherals
Off Off
Available Clock and Oscillator Source
Sleep
0
N/A
None – All clocks are disabled
PRI_RUN
N/A
10
Clocked Clocked Primary – HS, EC, HSPLL, ECPLL, INTOSC
oscillator;
this is the normal, full-power execution mode
SEC_RUN
RC_RUN
PRI_IDLE
SEC_IDLE
RC_IDLE
N/A
N/A
1
01
11
10
01
11
Clocked Clocked Secondary – Timer1 oscillator
Clocked Clocked Internal oscillator block(2)
Off
Off
Off
Clocked Primary – HS, EC, HSPLL, ECPLL, INTOSC
Clocked Secondary – Timer1 oscillator
Clocked Internal oscillator block(2)
1
1
Note 1: IDLEN reflects its value when the SLEEPinstruction is executed.
2: Includes INTRC and INTOSC postcaler (internal oscillator block).
© 2009 Microchip Technology Inc.
DS39778D-page 43
PIC18F87J11 FAMILY
3.1.3
CLOCK TRANSITIONS AND STATUS
INDICATORS
3.2
Run Modes
In the Run modes, clocks to both the core and
peripherals are active. The difference between these
modes is the clock source.
The length of the transition between clock sources is
the sum of two cycles of the old clock source and three
to four cycles of the new clock source. This formula
assumes that the new clock source is stable.
3.2.1
PRI_RUN MODE
Two bits indicate the current clock source and its status:
OSTS (OSCCON<3>) and T1RUN (T1CON<6>). In
general, only one of these bits will be set while in a given
power-managed mode. When the OSTS bit is set, the
primary clock is providing the device clock. When the
T1RUN bit is set, the Timer1 oscillator is providing the
clock. If neither of these bits is set, INTRC is clocking the
device.
The PRI_RUN mode is the normal, full-power execu-
tion mode of the microcontroller. This is also the default
mode upon a device Reset unless Two-Speed Start-up
is enabled (see Section 24.4 “Two-Speed Start-up”
for details). In this mode, the OSTS bit is set. (see
Section 2.2 “Control Registers”).
3.2.2
SEC_RUN MODE
The SEC_RUN mode is the compatible mode to the
“clock switching” feature offered in other PIC18
devices. In this mode, the CPU and peripherals are
clocked from the Timer1 oscillator. This gives users the
option of lower power consumption while still using a
high-accuracy clock source.
Note:
Executing a SLEEP instruction does not
necessarily place the device into Sleep
mode. It acts as the trigger to place the
controller into either the Sleep mode, or
one of the Idle modes, depending on the
setting of the IDLEN bit.
SEC_RUN mode is entered by setting the SCS1:SCS0
bits to ‘01’. The device clock source is switched to the
Timer1 oscillator (see Figure 3-1), the primary oscilla-
tor is shut down, the T1RUN bit (T1CON<6>) is set and
the OSTS bit is cleared.
3.1.4
MULTIPLE SLEEP COMMANDS
The power-managed mode that is invoked with the
SLEEP instruction is determined by the setting of the
IDLEN bit at the time the instruction is executed. If
another SLEEPinstruction is executed, the device will
enter the power-managed mode specified by IDLEN at
that time. If IDLEN has changed, the device will enter
the new power-managed mode specified by the new
setting.
DS39778D-page 44
© 2009 Microchip Technology Inc.
PIC18F87J11 FAMILY
On transitions from SEC_RUN mode to PRI_RUN
mode, the peripherals and CPU continue to be clocked
from the Timer1 oscillator while the primary clock is
started. When the primary clock becomes ready, a
clock switch back to the primary clock occurs (see
Figure 3-2). When the clock switch is complete, the
T1RUN bit is cleared, the OSTS bit is set and the
primary clock is providing the clock. The IDLEN and
SCS bits are not affected by the wake-up; the Timer1
oscillator continues to run.
Note:
The Timer1 oscillator should already be
running prior to entering SEC_RUN mode.
If the T1OSCEN bit is not set when the
SCS1:SCS0 bits are set to ‘01’, entry to
SEC_RUN mode will not occur. If the
Timer1 oscillator is enabled, but not yet
running, device clocks will be delayed until
the oscillator has started. In such situa-
tions, initial oscillator operation is far from
stable and unpredictable operation may
result.
FIGURE 3-1:
TRANSITION TIMING FOR ENTRY TO SEC_RUN MODE
Q1 Q2 Q3 Q4 Q1
Q2
Q3
Q4
Q1
Q2
Q3
1
2
3
n-1
n
T1OSI
OSC1
Clock Transition
CPU
Clock
Peripheral
Clock
Program
Counter
PC
PC + 2
PC + 4
FIGURE 3-2:
TRANSITION TIMING FROM SEC_RUN MODE TO PRI_RUN MODE (HSPLL)
Q1
Q2
Q3
Q4
Q1
Q2 Q3 Q4 Q1 Q2 Q3
T1OSI
OSC1
(1)
TOST
(1)
TPLL
1
2
n-1
n
PLL Clock
Output
Clock
Transition
CPU Clock
Peripheral
Clock
Program
Counter
PC + 2
PC + 4
PC
OSTS Bit Set
SCS1:SCS0 Bits Changed
Note 1: TOST = 1024 TOSC; TPLL = 2 ms (approx). These intervals are not shown to scale.
© 2009 Microchip Technology Inc.
DS39778D-page 45
PIC18F87J11 FAMILY
On transitions from RC_RUN mode to PRI_RUN mode,
the device continues to be clocked from the INTOSC
block while the primary clock is started. When the
primary clock becomes ready, a clock switch to the pri-
mary clock occurs (see Figure 3-4). When the clock
switch is complete, the OSTS bit is set and the primary
clock is providing the device clock. The IDLEN and
SCS bits are not affected by the switch. The INTRC
block source will continue to run if either the WDT or the
Fail-Safe Clock Monitor is enabled.
3.2.3
RC_RUN MODE
In RC_RUN mode, the CPU and peripherals are
clocked from the internal oscillator; the primary clock is
shut down. This mode provides the best power conser-
vation of all the Run modes while still executing code.
It works well for user applications which are not highly
timing sensitive or do not require high-speed clocks at
all times.
This mode is entered by setting SCS<1:0> to ‘11’.
When the clock source is switched to the internal
oscillator block (see Figure 3-3), the primary oscillator
is shut down and the OSTS bit is cleared.
FIGURE 3-3:
TRANSITION TIMING TO RC_RUN MODE
Q1 Q2 Q3 Q4 Q1
Q2
Q3
Q4
Q1
Q2
Q3
1
2
3
n-1
n
INTRC
OSC1
Clock Transition
CPU
Clock
Peripheral
Clock
Program
Counter
PC
PC + 2
PC + 4
FIGURE 3-4:
TRANSITION TIMING FROM RC_RUN MODE TO PRI_RUN MODE
Q4
Q1
Q2 Q3 Q4 Q1 Q2
Q3
Q3
Q1
Q2
INTRC
OSC1
(1)
TOST
(1)
TPLL
1
2
n-1
n
PLL Clock
Output
Clock
Transition
CPU Clock
Peripheral
Clock
Program
Counter
PC + 2
PC
PC + 4
SCS1:SCS0 Bits Changed
OSTS Bit Set
Note 1: TOST = 1024 TOSC; TPLL = 2 ms (approx). These intervals are not shown to scale.
DS39778D-page 46
© 2009 Microchip Technology Inc.
PIC18F87J11 FAMILY
3.3
Sleep Mode
3.4
Idle Modes
The power-managed Sleep mode is identical to the leg-
acy Sleep mode offered in all other PIC devices. It is
entered by clearing the IDLEN bit (the default state on
device Reset) and executing the SLEEP instruction.
This shuts down the selected oscillator (Figure 3-5). All
clock source status bits are cleared.
The Idle modes allow the controller’s CPU to be
selectively shut down while the peripherals continue to
operate. Selecting a particular Idle mode allows users
to further manage power consumption.
If the IDLEN bit is set to ‘1’ when a SLEEPinstruction is
executed, the peripherals will be clocked from the clock
source selected using the SCS1:SCS0 bits; however, the
CPU will not be clocked. The clock source status bits are
not affected. Setting IDLEN and executing a SLEEP
instruction provides a quick method of switching from a
given Run mode to its corresponding Idle mode.
Entering the Sleep mode from any other mode does not
require a clock switch. This is because no clocks are
needed once the controller has entered Sleep. If the
WDT is selected, the INTRC source will continue to
operate. If the Timer1 oscillator is enabled, it will also
continue to run.
If the WDT is selected, the INTRC source will continue
to operate. If the Timer1 oscillator is enabled, it will also
continue to run.
When a wake event occurs in Sleep mode (by interrupt,
Reset or WDT time-out), the device will not be clocked
until the clock source selected by the SCS1:SCS0 bits
becomes ready (see Figure 3-6), or it will be clocked
from the internal oscillator if either the Two-Speed
Start-up or the Fail-Safe Clock Monitor are enabled
(see Section 24.0 “Special Features of the CPU”). In
either case, the OSTS bit is set when the primary clock
is providing the device clocks. The IDLEN and SCS bits
are not affected by the wake-up.
Since the CPU is not executing instructions, the only
exits from any of the Idle modes are by interrupt, WDT
time-out or a Reset. When a wake event occurs, CPU
execution is delayed by an interval of TCSD
(parameter 38, Table 27-12) while it becomes ready to
execute code. When the CPU begins executing code,
it resumes with the same clock source for the current
Idle mode. For example, when waking from RC_IDLE
mode, the internal oscillator block will clock the CPU
and peripherals (in other words, RC_RUN mode). The
IDLEN and SCS bits are not affected by the wake-up.
While in any Idle mode or the Sleep mode, a WDT
time-out will result in a WDT wake-up to the Run mode
currently specified by the SCS1:SCS0 bits.
FIGURE 3-5:
TRANSITION TIMING FOR ENTRY TO SLEEP MODE
Q1 Q2 Q3 Q4 Q1
OSC1
CPU
Clock
Peripheral
Clock
Sleep
Program
Counter
PC + 2
PC
FIGURE 3-6:
TRANSITION TIMING FOR WAKE FROM SLEEP (HSPLL)
Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
Q2 Q3 Q4 Q1 Q2
Q1
OSC1
(1)
(1)
TOST
TPLL
PLL Clock
Output
CPU Clock
Peripheral
Clock
Program
Counter
PC
OSTS Bit Set
Note1: TOST = 1024 TOSC; TPLL = 2 ms (approx). These intervals are not shown to scale.
PC + 2
PC + 4
PC + 6
Wake Event
© 2009 Microchip Technology Inc.
DS39778D-page 47
PIC18F87J11 FAMILY
3.4.1
PRI_IDLE MODE
3.4.2
SEC_IDLE MODE
This mode is unique among the three low-power Idle
modes, in that it does not disable the primary device
clock. For timing sensitive applications, this allows for
the fastest resumption of device operation with its more
accurate primary clock source, since the clock source
does not have to “warm up” or transition from another
oscillator.
In SEC_IDLE mode, the CPU is disabled but the
peripherals continue to be clocked from the Timer1
oscillator. This mode is entered from SEC_RUN by set-
ting the IDLEN bit and executing a SLEEPinstruction. If
the device is in another Run mode, set IDLEN first, then
set SCS1:SCS0 to ‘01’ and execute SLEEP. When the
clock source is switched to the Timer1 oscillator, the
primary oscillator is shut down, the OSTS bit is cleared
and the T1RUN bit is set.
PRI_IDLE mode is entered from PRI_RUN mode by
setting the IDLEN bit and executing a SLEEP instruc-
tion. If the device is in another Run mode, set IDLEN
first, then set the SCS bits to ‘10’ and execute SLEEP.
Although the CPU is disabled, the peripherals continue
to be clocked from the primary clock source specified
by the FOSC1:FOSC0 Configuration bits. The OSTS
bit remains set (see Figure 3-7).
When a wake event occurs, the peripherals continue to
be clocked from the Timer1 oscillator. After an interval
of TCSD following the wake event, the CPU begins exe-
cuting code being clocked by the Timer1 oscillator. The
IDLEN and SCS bits are not affected by the wake-up;
the Timer1 oscillator continues to run (see Figure 3-8).
When a wake event occurs, the CPU is clocked from the
primary clock source. A delay of interval TCSD is
required between the wake event and when code exe-
cution starts. This is required to allow the CPU to
become ready to execute instructions. After the
wake-up, the OSTS bit remains set. The IDLEN and
SCS bits are not affected by the wake-up (see
Figure 3-8).
Note:
The Timer1 oscillator should already be
running prior to entering SEC_IDLE mode.
If the T1OSCEN bit is not set when the
SLEEPinstruction is executed, the SLEEP
instruction will be ignored and entry to
SEC_IDLE mode will not occur. If the
Timer1 oscillator is enabled, but not yet
running, peripheral clocks will be delayed
until the oscillator has started. In such
situations, initial oscillator operation is far
from stable and unpredictable operation
may result.
FIGURE 3-7:
TRANSITION TIMING FOR ENTRY TO IDLE MODE
Q3
Q4
Q1
Q1
Q2
OSC1
CPU Clock
Peripheral
Clock
Program
Counter
PC
PC + 2
FIGURE 3-8:
TRANSITION TIMING FOR WAKE FROM IDLE TO RUN MODE
Q1
Q3
Q4
Q2
OSC1
TCSD
CPU Clock
Peripheral
Clock
Program
Counter
PC
Wake Event
DS39778D-page 48
© 2009 Microchip Technology Inc.
PIC18F87J11 FAMILY
3.4.3
RC_IDLE MODE
3.5.2
EXIT BY WDT TIME-OUT
In RC_IDLE mode, the CPU is disabled but the
peripherals continue to be clocked from the internal
oscillator block. This mode allows for controllable
power conservation during Idle periods.
A WDT time-out will cause different actions depending
on which power-managed mode the device is in when
the time-out occurs.
If the device is not executing code (all Idle modes and
Sleep mode), the time-out will result in an exit from the
power-managed mode (see Section 3.2 “Run
Modes” and Section 3.3 “Sleep Mode”). If the device
is executing code (all Run modes), the time-out will
result in a WDT Reset (see Section 24.2 “Watchdog
Timer (WDT)”).
From RC_RUN, this mode is entered by setting the
IDLEN bit and executing a SLEEP instruction. If the
device is in another Run mode, first set IDLEN, then
clear the SCS bits and execute SLEEP. When the clock
source is switched to the INTOSC block, the primary
oscillator is shut down and the OSTS bit is cleared.
When a wake event occurs, the peripherals continue to
be clocked from the internal oscillator block. After a
delay of TCSD following the wake event, the CPU
begins executing code being clocked by the INTRC.
The IDLEN and SCS bits are not affected by the
wake-up. The INTRC source will continue to run if
either the WDT or the Fail-Safe Clock Monitor is
enabled.
The Watchdog Timer and postscaler are cleared by one
of the following events:
• Executing a SLEEPor CLRWDTinstruction
• The loss of a currently selected clock source (if
the Fail-Safe Clock Monitor is enabled)
3.5.3
EXIT BY RESET
Exiting an Idle or Sleep mode by Reset automatically
forces the device to run from the INTRC.
3.5
Exiting Idle and Sleep Modes
3.5.4
EXIT WITHOUT AN OSCILLATOR
START-UP DELAY
An exit from Sleep mode, or any of the Idle modes, is
triggered by an interrupt, a Reset or a WDT time-out.
This section discusses the triggers that cause exits
from power-managed modes. The clocking subsystem
actions are discussed in each of the power-managed
modes sections (see Section 3.2 “Run Modes”,
Section 3.3 “Sleep Mode” and Section 3.4 “Idle
Modes”).
Certain exits from power-managed modes do not
invoke the OST at all. There are two cases:
• PRI_IDLE mode, where the primary clock source
is not stopped; and
• The primary clock source is either the EC or
ECPLL mode.
3.5.1
EXIT BY INTERRUPT
In these instances, the primary clock source either
does not require an oscillator start-up delay, since it is
already running (PRI_IDLE), or normally does not
require an oscillator start-up delay (EC). However, a
fixed delay of interval, TCSD, following the wake event
is still required when leaving Sleep and Idle modes to
allow the CPU to prepare for execution. Instruction
execution resumes on the first clock cycle following this
delay.
Any of the available interrupt sources can cause the
device to exit from an Idle mode, or the Sleep mode, to
a Run mode. To enable this functionality, an interrupt
source must be enabled by setting its enable bit in one
of the INTCON or PIE registers. The exit sequence is
initiated when the corresponding interrupt flag bit is set.
On all exits from Idle or Sleep modes by interrupt, code
execution branches to the interrupt vector if the
GIE/GIEH bit (INTCON<7>) is set. Otherwise, code
execution continues or resumes without branching
(see Section 9.0 “Interrupts”).
A fixed delay of interval, TCSD, following the wake event
is required when leaving Sleep and Idle modes. This
delay is required for the CPU to prepare for execution.
Instruction execution resumes on the first clock cycle
following this delay.
© 2009 Microchip Technology Inc.
DS39778D-page 49
PIC18F87J11 FAMILY
NOTES:
DS39778D-page 50
© 2009 Microchip Technology Inc.
PIC18F87J11 FAMILY
A simplified block diagram of the on-chip Reset circuit
is shown in Figure 4-1.
4.0
RESET
The PIC18F87J11 Family of devices differentiate
between various kinds of Reset:
4.1
RCON Register
a) Power-on Reset (POR)
Device Reset events are tracked through the RCON
register (Register 4-1). The lower five bits of the
register indicate that a specific Reset event has
occurred. In most cases, these bits can only be set by
the event and must be cleared by the application after
the event. The state of these flag bits, taken together,
can be read to indicate the type of Reset that just
occurred. This is described in more detail in
Section 4.7 “Reset State of Registers”.
b) MCLR Reset during normal operation
c) MCLR Reset during power-managed modes
d) Watchdog Timer (WDT) Reset (during
execution)
e) Configuration Mismatch (CM)
f) Brown-out Reset (BOR)
g) RESETInstruction
h) Stack Full Reset
The RCON register also has a control bit for setting
interrupt priority (IPEN). Interrupt priority is discussed
in Section 9.0 “Interrupts”.
i) Stack Underflow Reset
This section discusses Resets generated by MCLR,
POR and BOR and covers the operation of the various
start-up timers. Stack Reset events are covered in
Section 5.1.6.4 “Stack Full and Underflow Resets”.
WDT Resets are covered in Section 24.2 “Watchdog
Timer (WDT)”.
FIGURE 4-1:
SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT
RESETInstruction
Configuration Word Mismatch
Stack Full/Underflow Reset
Stack
Pointer
External Reset
MCLR
( )_IDLE
Sleep
WDT
Time-out
POR Pulse
VDD Rise
Detect
VDD
Brown-out
Reset
(1)
S
PWRT
Chip_Reset
32 μs
PWRT
66 ms
Q
R
11-Bit Ripple Counter
INTRC
Note 1: The ENVREG pin must be tied high to enable Brown-out Reset. The Brown-out Reset is provided by the on-chip
voltage regulator when there is insufficient source voltage to maintain regulation.
© 2009 Microchip Technology Inc.
DS39778D-page 51
PIC18F87J11 FAMILY
REGISTER 4-1:
RCON: RESET CONTROL REGISTER
R/W-0
IPEN
U-0
—
R/W-1
CM
R/W-1
RI
R-1
TO
R-1
PD
R/W-0
POR
R/W-0
BOR
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7
IPEN: Interrupt Priority Enable bit
1= Enable priority levels on interrupts
0= Disable priority levels on interrupts (PIC16CXXX Compatibility mode)
bit 6
bit 5
Unimplemented: Read as ‘0’
CM: Configuration Mismatch Flag bit
1= A Configuration Mismatch Reset has not occurred
0= A Configuration Mismatch Reset has occurred (must be set in software after a Configuration
Mismatch Reset occurs)
bit 4
RI: RESETInstruction Flag bit
1= The RESETinstruction was not executed (set by firmware only)
0= The RESET instruction was executed causing a device Reset (must be set in software after a
Brown-out Reset occurs)
bit 3
bit 2
bit 1
bit 0
TO: Watchdog Time-out Flag bit
1= Set by power-up, CLRWDTinstruction or SLEEPinstruction
0= A WDT time-out occurred
PD: Power-Down Detection Flag bit
1= Set by power-up or by the CLRWDTinstruction
0= Set by execution of the SLEEPinstruction
POR: Power-on Reset Status bit
1= A Power-on Reset has not occurred (set by firmware only)
0= A Power-on Reset occurred (must be set in software after a Power-on Reset occurs)
BOR: Brown-out Reset Status bit
1= A Brown-out Reset has not occurred (set by firmware only)
0= A Brown-out Reset occurred (must be set in software after a Brown-out Reset occurs)
Note 1: It is recommended that the POR bit be set after a Power-on Reset has been detected, so that subsequent
Power-on Resets may be detected.
2: If the on-chip voltage regulator is disabled, BOR remains ‘0’ at all times. See Section 4.4.1 “Detecting
BOR” for more information.
3: Brown-out Reset is said to have occurred when BOR is ‘0’ and POR is ‘1’ (assuming that POR was set to
‘1’ by software immediately after a Power-on Reset).
DS39778D-page 52
© 2009 Microchip Technology Inc.
PIC18F87J11 FAMILY
FIGURE 4-2:
EXTERNAL POWER-ON
RESET CIRCUIT (FOR
SLOW VDD POWER-UP)
4.2
Master Clear (MCLR)
The MCLR pin provides a method for triggering a hard
external Reset of the device. A Reset is generated by
holding the pin low. PIC18 extended microcontroller
devices have a noise filter in the MCLR Reset path
which detects and ignores small pulses.
VDD
VDD
D
R
The MCLR pin is not driven low by any internal Resets,
including the WDT.
R1
MCLR
PIC18F87J11
C
4.3
Power-on Reset (POR)
A Power-on Reset condition is generated on-chip
whenever VDD rises above a certain threshold. This
allows the device to start in the initialized state when
VDD is adequate for operation.
Note 1: External Power-on Reset circuit is required
only if the VDD power-up slope is too slow.
The diode D helps discharge the capacitor
quickly when VDD powers down.
To take advantage of the POR circuitry, tie the MCLR
pin through a resistor (1 kΩ to 10 kΩ) to VDD. This will
eliminate external RC components usually needed to
create a Power-on Reset delay. A minimum rise rate for
VDD is specified (parameter D004). For a slow rise
time, see Figure 4-2.
2: R < 40 kΩ is recommended to make sure that
the voltage drop across R does not violate
the device’s electrical specification.
3: R1 ≥ 1 kΩ will limit any current flowing into
MCLR from external capacitor C, in the event
of MCLR/VPP pin breakdown, due to
Electrostatic Discharge (ESD) or Electrical
Overstress (EOS).
When the device starts normal operation (i.e., exits the
Reset condition), device operating parameters
(voltage, frequency, temperature, etc.) must be met to
ensure operation. If these conditions are not met, the
device must be held in Reset until the operating
conditions are met.
4.4.1
DETECTING BOR
The BOR bit always resets to ‘0’ on any Brown-out
Reset or Power-on Reset event. This makes it difficult
to determine if a Brown-out Reset event has occurred
just by reading the state of BOR alone. A more reliable
method is to simultaneously check the state of both
POR and BOR. This assumes that the POR bit is reset
to ‘1’ in software immediately after any Power-on Reset
event. If BOR is ‘0’ while POR is ‘1’, it can be reliably
assumed that a Brown-out Reset event has occurred.
Power-on Reset events are captured by the POR bit
(RCON<1>). The state of the bit is set to ‘0’ whenever
a Power-on Reset occurs; it does not change for any
other Reset event. POR is not reset to ‘1’ by any
hardware event. To capture multiple events, the user
manually resets the bit to ‘1’ in software following any
Power-on Reset.
If the voltage regulator is disabled, Brown-out Reset
functionality is disabled. In this case, the BOR bit
cannot be used to determine a Brown-out Reset event.
The BOR bit is still cleared by a Power-on Reset event.
4.4
Brown-out Reset (BOR)
The PIC18F87J11 family of devices incorporates a
simple Brown-out Reset function when the internal reg-
ulator is enabled (ENVREG pin is tied to VDD). Any
drop of VDD below VBOR (parameter D005)) for greater
than time TBOR (parameter 35) will reset the device. A
Reset may or may not occur if VDD falls below VBOR for
less than TBOR. The chip will remain in Brown-out
Reset until VDD rises above VBOR.
4.5
Configuration Mismatch (CM)
The Configuration Mismatch (CM) Reset is designed to
detect and attempt to recover from random, memory
corrupting events. These include Electrostatic Discharge
(ESD) events, which can cause widespread, single-bit
changes throughout the device and result in catastrophic
failure.
Once a Brown-out Reset has occurred, the Power-up
Timer will keep the chip in Reset for TPWRT
(parameter 33). If VDD drops below VBOR while the
Power-up Timer is running, the chip will go back into a
Brown-out Reset and the Power-up Timer will be
initialized. Once VDD rises above VBOR, the Power-up
Timer will execute the additional time delay.
In PIC18FXXJ Flash devices, the device Configuration
registers (located in the configuration memory space)
are continuously monitored during operation by
comparing their values to complimentary shadow reg-
isters. If a mismatch is detected between the two sets
of registers, a CM Reset automatically occurs. These
events are captured by the CM bit (RCON<5>). The
state of the bit is set to ‘0’ whenever a CM event occurs;
it does not change for any other Reset event.
© 2009 Microchip Technology Inc.
DS39778D-page 53
PIC18F87J11 FAMILY
A CM Reset behaves similarly to a Master Clear Reset,
RESET instruction, WDT time-out or Stack Event
Resets. As with all hard and power Reset events, the
device Configuration Words are reloaded from the
Flash Configuration Words in program memory as the
device restarts.
The power-up time delay depends on the INTRC clock
and will vary from chip-to-chip due to temperature and
process variation. See DC parameter 33 for details.
4.6.1
TIME-OUT SEQUENCE
If enabled, the PWRT time-out is invoked after the POR
pulse has cleared. The total time-out will vary based on
the status of the PWRT. Figure 4-3, Figure 4-4,
Figure 4-5 and Figure 4-6 all depict time-out
sequences on power-up with the Power-up Timer
enabled.
4.6
Power-up Timer (PWRT)
PIC18F87J11 Family devices incorporate an on-chip
Power-up Timer (PWRT) to help regulate the Power-on
Reset process. The PWRT is always enabled. The
main function is to ensure that the device voltage is
stable before code is executed.
Since the time-outs occur from the POR pulse, if MCLR
is kept low long enough, the PWRT will expire. Bringing
MCLR high will begin execution immediately
(Figure 4-5). This is useful for testing purposes, or to
synchronize more than one PIC18FXXXX device
operating in parallel.
The Power-up Timer (PWRT) of the PIC18F87J11
Family devices is an 11-bit counter which uses the
INTRC source as the clock input. This yields an
approximate time interval of 2048 x 32 μs = 66 ms.
While the PWRT is counting, the device is held in
Reset.
FIGURE 4-3:
TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD, VDD RISE < TPWRT)
VDD
MCLR
INTERNAL POR
TPWRT
PWRT TIME-OUT
INTERNAL RESET
FIGURE 4-4:
TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 1
VDD
MCLR
INTERNAL POR
TPWRT
PWRT TIME-OUT
INTERNAL RESET
DS39778D-page 54
© 2009 Microchip Technology Inc.
PIC18F87J11 FAMILY
FIGURE 4-5:
TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 2
VDD
MCLR
INTERNAL POR
TPWRT
PWRT TIME-OUT
INTERNAL RESET
FIGURE 4-6:
SLOW RISE TIME (MCLR TIED TO VDD, VDD RISE > TPWRT)
3.3V
VDD
0V
1V
MCLR
INTERNAL POR
TPWRT
PWRT TIME-OUT
INTERNAL RESET
© 2009 Microchip Technology Inc.
DS39778D-page 55
PIC18F87J11 FAMILY
different Reset situations, as indicated in Table 4-1.
These bits are used in software to determine the nature
of the Reset.
4.7
Reset State of Registers
Most registers are unaffected by a Reset. Their status
is unknown on POR and unchanged by all other
Resets. The other registers are forced to a “Reset
state” depending on the type of Reset that occurred.
Table 4-2 describes the Reset states for all of the
Special Function Registers. These are categorized by
Power-on and Brown-out Resets, Master Clear and
WDT Resets and WDT wake-ups.
Most registers are not affected by a WDT wake-up,
since this is viewed as the resumption of normal
operation. Status bits from the RCON register (CM, RI,
TO, PD, POR and BOR) are set or cleared differently in
TABLE 4-1:
STATUS BITS, THEIR SIGNIFICANCE AND THE INITIALIZATION CONDITION FOR
RCON REGISTER
RCON Register
STKPTR Register
Program
Condition
Counter(1)
CM
RI
TO
PD
POR BOR STKFUL STKUNF
Power-on Reset
0000h
0000h
0000h
0000h
0000h
1
u
1
0
u
1
0
1
u
u
1
u
1
u
1
1
u
1
u
u
0
u
u
u
u
0
u
0
u
u
0
u
u
u
u
0
u
u
u
u
RESETinstruction
Brown-out Reset
Configuration Mismatch Reset
MCLR Reset during
power-managed Run modes
MCLR Reset during
power-managed Idle modes
and Sleep mode
0000h
0000h
u
u
u
u
1
u
0
u
u
u
u
u
u
u
u
u
MCLR Reset during full-power
execution
Stack Full Reset (STVREN = 1)
0000h
0000h
u
u
u
u
u
u
u
u
u
u
u
u
1
u
u
1
Stack Underflow Reset
(STVREN = 1)
Stack Underflow Error (not an
actual Reset, STVREN = 0)
0000h
0000h
PC + 2
u
u
u
u
u
u
u
0
0
u
u
0
u
u
u
u
u
u
u
u
u
1
u
u
WDT time-out during full-power
or power-managed Run modes
WDT time-out during
power-managed Idle or Sleep
modes
Interrupt exit from
PC + 2
u
u
u
0
u
u
u
u
power-managed modes
Legend: u= unchanged
Note 1: When the wake-up is due to an interrupt and the GIEH or GIEL bit is set, the PC is loaded with the interrupt
vector (0008h or 0018h).
DS39778D-page 56
© 2009 Microchip Technology Inc.
PIC18F87J11 FAMILY
TABLE 4-2:
Register
INITIALIZATION CONDITIONS FOR ALL REGISTERS
MCLR Resets,
WDT Reset,
RESETInstruction,
Stack Resets,
CM Resets
Power-on Reset,
Brown-out Reset
Wake-up via WDT
or Interrupt
Applicable Devices
TOSU
PIC18F6XJ1X PIC18F8XJ1X
PIC18F6XJ1X PIC18F8XJ1X
PIC18F6XJ1X PIC18F8XJ1X
PIC18F6XJ1X PIC18F8XJ1X
PIC18F6XJ1X PIC18F8XJ1X
PIC18F6XJ1X PIC18F8XJ1X
PIC18F6XJ1X PIC18F8XJ1X
PIC18F6XJ1X PIC18F8XJ1X
PIC18F6XJ1X PIC18F8XJ1X
PIC18F6XJ1X PIC18F8XJ1X
PIC18F6XJ1X PIC18F8XJ1X
PIC18F6XJ1X PIC18F8XJ1X
PIC18F6XJ1X PIC18F8XJ1X
PIC18F6XJ1X PIC18F8XJ1X
PIC18F6XJ1X PIC18F8XJ1X
PIC18F6XJ1X PIC18F8XJ1X
PIC18F6XJ1X PIC18F8XJ1X
PIC18F6XJ1X PIC18F8XJ1X
PIC18F6XJ1X PIC18F8XJ1X
PIC18F6XJ1X PIC18F8XJ1X
PIC18F6XJ1X PIC18F8XJ1X
PIC18F6XJ1X PIC18F8XJ1X
PIC18F6XJ1X PIC18F8XJ1X
PIC18F6XJ1X PIC18F8XJ1X
PIC18F6XJ1X PIC18F8XJ1X
PIC18F6XJ1X PIC18F8XJ1X
PIC18F6XJ1X PIC18F8XJ1X
PIC18F6XJ1X PIC18F8XJ1X
PIC18F6XJ1X PIC18F8XJ1X
PIC18F6XJ1X PIC18F8XJ1X
PIC18F6XJ1X PIC18F8XJ1X
PIC18F6XJ1X PIC18F8XJ1X
---0 0000
0000 0000
0000 0000
00-0 0000
---0 0000
0000 0000
0000 0000
--00 0000
0000 0000
0000 0000
0000 0000
xxxx xxxx
xxxx xxxx
0000 000x
1111 1111
1100 0000
N/A
---0 0000
0000 0000
0000 0000
uu-0 0000
---0 0000
0000 0000
0000 0000
--00 0000
0000 0000
0000 0000
0000 0000
uuuu uuuu
uuuu uuuu
0000 000u
1111 1111
1100 0000
N/A
---0 uuuu(1)
uuuu uuuu(1)
uuuu uuuu(1)
uu-u uuuu(1)
---u uuuu
uuuu uuuu
PC + 2(2)
--uu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu(3)
uuuu uuuu(3)
uuuu uuuu(3)
N/A
TOSH
TOSL
STKPTR
PCLATU
PCLATH
PCL
TBLPTRU
TBLPTRH
TBLPTRL
TABLAT
PRODH
PRODL
INTCON
INTCON2
INTCON3
INDF0
POSTINC0
POSTDEC0
PREINC0
PLUSW0
FSR0H
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
---- xxxx
xxxx xxxx
xxxx xxxx
N/A
---- uuuu
uuuu uuuu
uuuu uuuu
N/A
---- uuuu
uuuu uuuu
uuuu uuuu
N/A
FSR0L
WREG
INDF1
POSTINC1
POSTDEC1
PREINC1
PLUSW1
FSR1H
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
---- xxxx
xxxx xxxx
---- 0000
---- uuuu
uuuu uuuu
---- 0000
---- uuuu
uuuu uuuu
---- uuuu
FSR1L
BSR
Legend: u= unchanged, x= unknown, -= unimplemented bit, read as ‘0’, q= value depends on condition.
Shaded cells indicate conditions do not apply for the designated device.
Note 1: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are
updated with the current value of the PC. The STKPTR is modified to point to the next location in the
hardware stack.
2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt
vector (0008h or 0018h).
3: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).
4: See Table 4-1 for Reset value for specific condition.
© 2009 Microchip Technology Inc.
DS39778D-page 57
PIC18F87J11 FAMILY
TABLE 4-2:
INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)
MCLR Resets,
WDT Reset,
RESETInstruction,
Stack Resets,
CM Resets
Power-on Reset,
Brown-out Reset
Wake-up via WDT
or Interrupt
Register
Applicable Devices
INDF2
PIC18F6XJ1X PIC18F8XJ1X
PIC18F6XJ1X PIC18F8XJ1X
PIC18F6XJ1X PIC18F8XJ1X
PIC18F6XJ1X PIC18F8XJ1X
PIC18F6XJ1X PIC18F8XJ1X
PIC18F6XJ1X PIC18F8XJ1X
PIC18F6XJ1X PIC18F8XJ1X
PIC18F6XJ1X PIC18F8XJ1X
PIC18F6XJ1X PIC18F8XJ1X
PIC18F6XJ1X PIC18F8XJ1X
PIC18F6XJ1X PIC18F8XJ1X
PIC18F6XJ1X PIC18F8XJ1X
PIC18F6XJ1X PIC18F8XJ1X
PIC18F6XJ1X PIC18F8XJ1X
PIC18F6XJ1X PIC18F8XJ1X
PIC18F6XJ1X PIC18F8XJ1X
PIC18F6XJ1X PIC18F8XJ1X
PIC18F6XJ1X PIC18F8XJ1X
PIC18F6XJ1X PIC18F8XJ1X
PIC18F6XJ1X PIC18F8XJ1X
PIC18F6XJ1X PIC18F8XJ1X
PIC18F6XJ1X PIC18F8XJ1X
PIC18F6XJ1X PIC18F8XJ1X
PIC18F6XJ1X PIC18F8XJ1X
PIC18F6XJ1X PIC18F8XJ1X
PIC18F6XJ1X PIC18F8XJ1X
PIC18F6XJ1X PIC18F8XJ1X
PIC18F6XJ1X PIC18F8XJ1X
PIC18F6XJ1X PIC18F8XJ1X
PIC18F6XJ1X PIC18F8XJ1X
PIC18F6XJ1X PIC18F8XJ1X
PIC18F6XJ1X PIC18F8XJ1X
PIC18F6XJ1X PIC18F8XJ1X
N/A
N/A
N/A
POSTINC2
POSTDEC2
PREINC2
PLUSW2
FSR2H
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
---- xxxx
xxxx xxxx
---x xxxx
0000 0000
xxxx xxxx
1111 1111
0110 q100
0-00 0000
0001 1111
0001 1111
0-11 1100
xxxx xxxx
---0 0000
xxxx xxxx
---- --00
0000 0000
---- --00
0000 0000
---- ---0
1111 1111
0-00 --00
-000 0000
xxxx xxxx
0000 0000
1111 1111
0000 0000
0000 0000
0000 0000
---- uuuu
uuuu uuuu
---u uuuu
0000 0000
uuuu uuuu
1111 1111
0110 q100
u-uu uuuu
uuuu uuuu
uuuu uuuu
0-qq qquu
uuuu uuuu
---u uuuu
uuuu uuuu
---- --uu
u0uu uuuu
---- --uu
0000 0000
---- ---u
1111 1111
0-00 --00
-000 0000
uuuu uuuu
0000 0000
uuuu uuuu
0000 0000
0000 0000
0000 0000
---- uuuu
uuuu uuuu
---u uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
0110 q10u
u-uu uuuu
uuuu uuuu
uuuu uuuu
u-qq qquu
uuuu uuuu
---u uuuu
uuuu uuuu
---- --uu
uuuu uuuu
---- --uu
uuuu uuuu
---- ---u
1111 1111
u-uu --uu
-uuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
FSR2L
STATUS
TMR0H
TMR0L
T0CON
OSCCON
REFOCON
CM1CON
CM2CON
RCON(4)
TMR1H
ODCON1
TMR1L
ODCON2
T1CON
ODCON3
TMR2
PADCFG1
PR2
MEMCON
T2CON
SSP1BUF
SSP1ADD
SSP1MSK
SSP1STAT
SSP1CON1
SSP1CON2
Legend: u= unchanged, x= unknown, -= unimplemented bit, read as ‘0’, q= value depends on condition.
Shaded cells indicate conditions do not apply for the designated device.
Note 1: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are
updated with the current value of the PC. The STKPTR is modified to point to the next location in the
hardware stack.
2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt
vector (0008h or 0018h).
3: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).
4: See Table 4-1 for Reset value for specific condition.
DS39778D-page 58
© 2009 Microchip Technology Inc.
PIC18F87J11 FAMILY
TABLE 4-2:
Register
INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)
MCLR Resets,
WDT Reset,
RESETInstruction,
Stack Resets,
CM Resets
Power-on Reset,
Brown-out Reset
Wake-up via WDT
or Interrupt
Applicable Devices
ADRESH
ADRESL
ADCON0
ADCON1
ANCON0
ANCON1
WDTCON
ECCP1AS
ECCP1DEL
CCPR1H
CCPR1L
CCP1CON
ECCP2AS
ECCP2DEL
CCPR2H
CCPR2L
CCP2CON
ECCP3AS
ECCP3DEL
CCPR3H
CCPR3L
CCP3CON
SPBRG1
RCREG1
TXREG1
TXSTA1
PIC18F6XJ1X PIC18F8XJ1X
PIC18F6XJ1X PIC18F8XJ1X
PIC18F6XJ1X PIC18F8XJ1X
PIC18F6XJ1X PIC18F8XJ1X
PIC18F6XJ1X PIC18F8XJ1X
PIC18F6XJ1X PIC18F8XJ1X
PIC18F6XJ1X PIC18F8XJ1X
PIC18F6XJ1X PIC18F8XJ1X
PIC18F6XJ1X PIC18F8XJ1X
PIC18F6XJ1X PIC18F8XJ1X
PIC18F6XJ1X PIC18F8XJ1X
PIC18F6XJ1X PIC18F8XJ1X
PIC18F6XJ1X PIC18F8XJ1X
PIC18F6XJ1X PIC18F8XJ1X
PIC18F6XJ1X PIC18F8XJ1X
PIC18F6XJ1X PIC18F8XJ1X
PIC18F6XJ1X PIC18F8XJ1X
PIC18F6XJ1X PIC18F8XJ1X
PIC18F6XJ1X PIC18F8XJ1X
PIC18F6XJ1X PIC18F8XJ1X
PIC18F6XJ1X PIC18F8XJ1X
PIC18F6XJ1X PIC18F8XJ1X
PIC18F6XJ1X PIC18F8XJ1X
PIC18F6XJ1X PIC18F8XJ1X
PIC18F6XJ1X PIC18F8XJ1X
PIC18F6XJ1X PIC18F8XJ1X
PIC18F6XJ1X PIC18F8XJ1X
PIC18F6XJ1X PIC18F8XJ1X
PIC18F6XJ1X PIC18F8XJ1X
PIC18F6XJ1X PIC18F8XJ1X
PIC18F6XJ1X PIC18F8XJ1X
PIC18F6XJ1X PIC18F8XJ1X
PIC18F6XJ1X PIC18F8XJ1X
xxxx xxxx
xxxx xxxx
0000 0000
0000 0000
00-0 0000
0000 0000
0x-0 ---0
0000 0000
0000 0000
xxxx xxxx
xxxx xxxx
0000 0000
0000 0000
0000 0000
xxxx xxxx
xxxx xxxx
0000 0000
0000 0000
0000 0000
xxxx xxxx
xxxx xxxx
0000 0000
0000 0000
0000 0000
xxxx xxxx
0000 0010
0000 000x
0000 0000
0000 0000
0000 0000
0000 0010
---- ----
--00 x00-
uuuu uuuu
uuuu uuuu
0000 0000
0000 0000
uu-u uuuu
uuuu uuuu
0x-u ---0
0000 0000
0000 0000
uuuu uuuu
uuuu uuuu
0000 0000
0000 0000
0000 0000
uuuu uuuu
uuuu uuuu
0000 0000
0000 0000
0000 0000
uuuu uuuu
uuuu uuuu
0000 0000
0000 0000
0000 0000
uuuu uuuu
0000 0010
0000 000x
0000 0000
0000 0000
0000 0000
0000 0010
---- ----
--00 u00-
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uu-u uuuu
uuuu uuuu
ux-u ---u
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
---- ----
--00 u00-
RCSTA1
SPBRG2
RCREG2
TXREG2
TXSTA2
EECON2
EECON1
Legend: u= unchanged, x= unknown, -= unimplemented bit, read as ‘0’, q= value depends on condition.
Shaded cells indicate conditions do not apply for the designated device.
Note 1: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are
updated with the current value of the PC. The STKPTR is modified to point to the next location in the
hardware stack.
2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt
vector (0008h or 0018h).
3: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).
4: See Table 4-1 for Reset value for specific condition.
© 2009 Microchip Technology Inc.
DS39778D-page 59
PIC18F87J11 FAMILY
TABLE 4-2:
INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)
MCLR Resets,
WDT Reset,
RESETInstruction,
Stack Resets,
CM Resets
Power-on Reset,
Brown-out Reset
Wake-up via WDT
or Interrupt
Register
Applicable Devices
IPR3
PIC18F6XJ1X PIC18F8XJ1X
PIC18F6XJ1X PIC18F8XJ1X
PIC18F6XJ1X PIC18F8XJ1X
PIC18F6XJ1X PIC18F8XJ1X
PIC18F6XJ1X PIC18F8XJ1X
PIC18F6XJ1X PIC18F8XJ1X
PIC18F6XJ1X PIC18F8XJ1X
PIC18F6XJ1X PIC18F8XJ1X
PIC18F6XJ1X PIC18F8XJ1X
PIC18F6XJ1X PIC18F8XJ1X
PIC18F6XJ1X PIC18F8XJ1X
PIC18F6XJ1X PIC18F8XJ1X
PIC18F6XJ1X PIC18F8XJ1X
PIC18F6XJ1X PIC18F8XJ1X
PIC18F6XJ1X PIC18F8XJ1X
PIC18F6XJ1X PIC18F8XJ1X
PIC18F6XJ1X PIC18F8XJ1X
PIC18F6XJ1X PIC18F8XJ1X
PIC18F6XJ1X PIC18F8XJ1X
PIC18F6XJ1X PIC18F8XJ1X
PIC18F6XJ1X PIC18F8XJ1X
PIC18F6XJ1X PIC18F8XJ1X
PIC18F6XJ1X PIC18F8XJ1X
PIC18F6XJ1X PIC18F8XJ1X
PIC18F6XJ1X PIC18F8XJ1X
PIC18F6XJ1X PIC18F8XJ1X
PIC18F6XJ1X PIC18F8XJ1X
PIC18F6XJ1X PIC18F8XJ1X
PIC18F6XJ1X PIC18F8XJ1X
1111 1111
0000 0000
0000 0000
111- 1111
000- 0000
000- 0000
1111 1111
0000 0000
0000 0000
0000 000x
0000 0000
1111 1111
1111 1111
---1 1111
1111 111-
1111 1111
1111 1111
1111 1111
1111 1111
1111 1111
xxxx xxxx
xxxx xxxx
---x xxxx
xxxx xxx-
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
1111 1111
0000 0000
0000 0000
111- 1111
000- 0000
000- 0000
1111 1111
0000 0000
0000 0000
0000 000x
0000 0000
1111 1111
1111 1111
---1 1111
1111 111-
1111 1111
1111 1111
1111 1111
1111 1111
1111 1111
uuuu uuuu
uuuu uuuu
---u uuuu
uuuu uuu-
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu(3)
uuuu uuuu
uuu- uuuu
uuu- uuuu(3)
uuu- uuuu
uuuu uuuu
uuuu uuuu(3)
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
---u uuuu
uuuu uuu-
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
---u uuuu
uuuu uuu-
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
PIR3
PIE3
IPR2
PIR2
PIE2
IPR1
PIR1
PIE1
RCSTA2
OSCTUNE
TRISJ
TRISH
TRISG
TRISF
TRISE
TRISD
TRISC
TRISB
TRISA
LATJ
LATH
LATG
LATF
LATE
LATD
LATC
LATB
LATA
Legend: u= unchanged, x= unknown, -= unimplemented bit, read as ‘0’, q= value depends on condition.
Shaded cells indicate conditions do not apply for the designated device.
Note 1: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are
updated with the current value of the PC. The STKPTR is modified to point to the next location in the
hardware stack.
2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt
vector (0008h or 0018h).
3: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).
4: See Table 4-1 for Reset value for specific condition.
DS39778D-page 60
© 2009 Microchip Technology Inc.
PIC18F87J11 FAMILY
TABLE 4-2:
Register
INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)
MCLR Resets,
WDT Reset,
RESETInstruction,
Stack Resets,
CM Resets
Power-on Reset,
Brown-out Reset
Wake-up via WDT
or Interrupt
Applicable Devices
PORTJ
PIC18F6XJ1X PIC18F8XJ1X
PIC18F6XJ1X PIC18F8XJ1X
PIC18F6XJ1X PIC18F8XJ1X
PIC18F6XJ1X PIC18F8XJ1X
PIC18F6XJ1X PIC18F8XJ1X
PIC18F6XJ1X PIC18F8XJ1X
PIC18F6XJ1X PIC18F8XJ1X
PIC18F6XJ1X PIC18F8XJ1X
PIC18F6XJ1X PIC18F8XJ1X
PIC18F6XJ1X PIC18F8XJ1X
PIC18F6XJ1X PIC18F8XJ1X
PIC18F6XJ1X PIC18F8XJ1X
PIC18F6XJ1X PIC18F8XJ1X
PIC18F6XJ1X PIC18F8XJ1X
PIC18F6XJ1X PIC18F8XJ1X
PIC18F6XJ1X PIC18F8XJ1X
PIC18F6XJ1X PIC18F8XJ1X
PIC18F6XJ1X PIC18F8XJ1X
PIC18F6XJ1X PIC18F8XJ1X
PIC18F6XJ1X PIC18F8XJ1X
PIC18F6XJ1X PIC18F8XJ1X
PIC18F6XJ1X PIC18F8XJ1X
PIC18F6XJ1X PIC18F8XJ1X
PIC18F6XJ1X PIC18F8XJ1X
PIC18F6XJ1X PIC18F8XJ1X
PIC18F6XJ1X PIC18F8XJ1X
PIC18F6XJ1X PIC18F8XJ1X
PIC18F6XJ1X PIC18F8XJ1X
PIC18F6XJ1X PIC18F8XJ1X
PIC18F6XJ1X PIC18F8XJ1X
PIC18F6XJ1X PIC18F8XJ1X
PIC18F6XJ1X PIC18F8XJ1X
PIC18F6XJ1X PIC18F8XJ1X
xxxx xxxx
0000 xxxx
000x xxxx
x001 100-
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
000x 0000
0000 0000
0100 0-00
0000 0000
0100 0-00
xxxx xxxx
xxxx xxxx
0000 0000
0000 0000
1111 1111
0000 0000
-000 0000
xxxx xxxx
xxxx xxxx
--00 0000
xxxx xxxx
xxxx xxxx
--00 0000
xxxx xxxx
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
---- --11
uuuu uuuu
uuuu uuuu
000u uuuu
xuuu uuu-
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
000u 0000
0000 0000
0100 0-00
0000 0000
0100 0-00
uuuu uuuu
uuuu uuuu
uuuu uuuu
0000 0000
1111 1111
0000 0000
-000 0000
uuuu uuuu
uuuu uuuu
--00 0000
uuuu uuuu
uuuu uuuu
--00 0000
uuuu uuuu
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
---- --11
uuuu uuuu
uuuu uuuu
uuuu uuuu
xuuu uuu-
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu u-uu
uuuu uuuu
uuuu u-uu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
1111 1111
uuuu uuuu
-uuu uuuu
uuuu uuuu
uuuu uuuu
--uu uuuu
uuuu uuuu
uuuu uuuu
--uu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
---- --uu
PORTH
PORTG
PORTF
PORTE
PORTD
PORTC
PORTB
PORTA
SPBRGH1
BAUDCON1
SPBRGH2
BAUDCON2
TMR3H
TMR3L
T3CON
TMR4
PR4
CVRCON
T4CON
CCPR4H
CCPR4L
CCP4CON
CCPR5H
CCPR5L
CCP5CON
SSP2BUF
SSP2ADD
SSP2MSK
SSP2STAT
SSP2CON1
SSP2CON2
CMSTAT
Legend: u= unchanged, x= unknown, -= unimplemented bit, read as ‘0’, q= value depends on condition.
Shaded cells indicate conditions do not apply for the designated device.
Note 1: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are
updated with the current value of the PC. The STKPTR is modified to point to the next location in the
hardware stack.
2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt
vector (0008h or 0018h).
3: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).
4: See Table 4-1 for Reset value for specific condition.
© 2009 Microchip Technology Inc.
DS39778D-page 61
PIC18F87J11 FAMILY
TABLE 4-2:
INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)
MCLR Resets,
WDT Reset,
RESETInstruction,
Stack Resets,
CM Resets
Power-on Reset,
Brown-out Reset
Wake-up via WDT
or Interrupt
Register
Applicable Devices
PMADDRH
PMDOUT1H
PMADDRL
PMDOUT1L
PMDIN1H
PMDIN1L
PMCONH
PMCONL
PMMODEH
PMMODEL
PMDOUT2H
PMDOUT2L
PMDIN2H
PMDIN2L
PMEH
PIC18F6XJ1X PIC18F8XJ1X
PIC18F6XJ1X PIC18F8XJ1X
PIC18F6XJ1X PIC18F8XJ1X
PIC18F6XJ1X PIC18F8XJ1X
PIC18F6XJ1X PIC18F8XJ1X
PIC18F6XJ1X PIC18F8XJ1X
PIC18F6XJ1X PIC18F8XJ1X
PIC18F6XJ1X PIC18F8XJ1X
PIC18F6XJ1X PIC18F8XJ1X
PIC18F6XJ1X PIC18F8XJ1X
PIC18F6XJ1X PIC18F8XJ1X
PIC18F6XJ1X PIC18F8XJ1X
PIC18F6XJ1X PIC18F8XJ1X
PIC18F6XJ1X PIC18F8XJ1X
PIC18F6XJ1X PIC18F8XJ1X
PIC18F6XJ1X PIC18F8XJ1X
PIC18F6XJ1X PIC18F8XJ1X
PIC18F6XJ1X PIC18F8XJ1X
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0-00 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
00-- 0000
10-- 1111
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0-00 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
00-- 0000
10-- 1111
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
u-uu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uu-- uuuu
uu-- uuuu
PMEL
PMSTATH
PMSTATL
Legend: u= unchanged, x= unknown, -= unimplemented bit, read as ‘0’, q= value depends on condition.
Shaded cells indicate conditions do not apply for the designated device.
Note 1: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are
updated with the current value of the PC. The STKPTR is modified to point to the next location in the
hardware stack.
2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt
vector (0008h or 0018h).
3: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).
4: See Table 4-1 for Reset value for specific condition.
DS39778D-page 62
© 2009 Microchip Technology Inc.
PIC18F87J11 FAMILY
5.1
Program Memory Organization
5.0
MEMORY ORGANIZATION
PIC18 microcontrollers implement a 21-bit program
counter which is capable of addressing a 2-Mbyte
program memory space. Accessing a location between
the upper boundary of the physically implemented
memory and the 2-Mbyte address will return all ‘0’s (a
NOPinstruction).
There are two types of memory in PIC18 Flash
microcontroller devices:
• Program Memory
• Data RAM
As Harvard architecture devices, the data and program
memories use separate busses; this allows for
concurrent access of the two memory spaces.
The entire PIC18F87J11 Family of devices offers three
different on-chip Flash program memory sizes, from
64 Kbytes (up to 16,384 single-word instructions) to
128 Kbytes (65,536 single-word instructions). The
program memory maps for individual family members
are shown in Figure 5-3.
Additional detailed information on the operation of the
Flash program memory is provided in Section 6.0
“Flash Program Memory”.
FIGURE 5-1:
MEMORY MAPS FOR PIC18F87J11 FAMILY DEVICES
PC<20:0>
21
CALL, CALLW, RCALL,
RETURN, RETFIE, RETLW,
ADDULNK, SUBULNK
Stack Level 1
•
•
•
Stack Level 31
PIC18FX6J11
PIC18FX6J16
PIC18FX7J11
000000h
On-Chip
Memory
On-Chip
Memory
On-Chip
Memory
Config. Words
00FFFFh
017FFFh
Config. Words
Config. Words
01FFFFh
Unimplemented
Unimplemented
Unimplemented
Read as ‘0’
Read as ‘0’
Read as ‘0’
1FFFFFF
Note:
Sizes of memory areas are not to scale. Sizes of program memory areas are enhanced to show detail.
© 2009 Microchip Technology Inc.
DS39778D-page 63
PIC18F87J11 FAMILY
5.1.1
HARD MEMORY VECTORS
5.1.2
FLASH CONFIGURATION WORDS
All PIC18 devices have a total of three hard-coded
return vectors in their program memory space. The
Reset vector address is the default value to which the
program counter returns on all device Resets; it is
located at 0000h.
Because PIC18F87J11 Family devices do not have
persistent configuration memory, the top four words of
on-chip program memory are reserved for configuration
information. On Reset, the configuration information is
copied into the Configuration registers.
PIC18 devices also have two interrupt vector
addresses for the handling of high-priority and
low-priority interrupts. The high-priority interrupt vector
is located at 0008h and the low-priority interrupt vector
is at 0018h. Their locations in relation to the program
memory map are shown in Figure 5-2.
The Configuration Words are stored in their program
memory location in numerical order, starting with the
lower byte of CONFIG1 at the lowest address and
ending with the upper byte of CONFIG4. For these
devices, only Configuration Words, CONFIG1 through
CONFIG3, are used; CONFIG4 is reserved. The actual
addresses of the Flash Configuration Word for devices
in the PIC18F87J11 Family are shown in Table 5-1.
Their location in the memory map is shown with the
other memory vectors in Figure 5-2.
FIGURE 5-2:
HARD VECTOR AND
CONFIGURATION WORD
LOCATIONS FOR
PIC18F87J11 FAMILY
DEVICES
Additional details on the device Configuration Words
are provided in Section 24.1 “Configuration Bits”.
TABLE 5-1:
FLASH CONFIGURATION
WORD FOR PIC18F87J11
FAMILY DEVICES
0000h
Reset Vector
High-Priority Interrupt Vector
Low-Priority Interrupt Vector
0008h
0018h
Program
Memory
(Kbytes)
Configuration
Word
Addresses
Device
PIC18F66J11
PIC18F86J11
PIC18F66J16
PIC18F86J16
PIC18F67J11
PIC18F87J11
FFF8h to
FFFFh
On-Chip
Program Memory
64
96
17FF8h to
17FFFh
1FFF8h to
1FFFFh
128
(Top of Memory-7)
(Top of Memory)
Flash Configuration Words
Read as ‘0’
1FFFFFh
Legend:
(Top of Memory) represents upper boundary
of on-chip program memory space (see
Figure 5-1 for device-specific values).
Shaded area represents unimplemented
memory. Areas are not shown to scale.
DS39778D-page 64
© 2009 Microchip Technology Inc.
PIC18F87J11 FAMILY
• The Extended Microcontroller Mode allows
access to both internal and external program
memories as a single block. The device can
access its entire on-chip program memory; above
this, the device accesses external program
memory up to the 2-Mbyte program space limit.
Execution automatically switches between the
two memories as required.
5.1.3
PIC18F8XJ11/8XJ16 PROGRAM
MEMORY MODES
The 80-pin devices in this family can address up to a
total of 2 Mbytes of program memory. This is achieved
through the external memory bus. There are two
distinct operating modes available to the controllers:
• Microcontroller (MC)
• Extended Microcontroller (EMC)
The setting of the EMB Configuration bits also controls
the address bus width of the external memory bus. This
is covered in more detail in Section 7.0 “External
Memory Bus”.
The program memory mode is determined by setting
the EMB Configuration bits (CONFIG3L<5:4>), as
shown in Register 5-1. (See also Section 24.1
“Configuration Bits” for additional details on the
device Configuration bits.)
In all modes, the microcontroller has complete access
to data RAM.
The program memory modes operate as follows:
Figure 5-3 compares the memory maps of the different
program memory modes. The differences between
on-chip and external memory access limitations are
more fully explained in Table 5-2.
• The Microcontroller Mode accesses only on-chip
Flash memory. Attempts to read above the top of
on-chip memory causes a read of all ‘0’s (a NOP
instruction).
The Microcontroller mode is also the only operating
mode available to 64-pin devices.
REGISTER 5-1:
CONFIG3L: CONFIGURATION REGISTER 3 LOW
R/WO-1
WAIT(1)
bit 7
R/WO-1
BW(1)
R/WO-1
EMB1(1)
R/WO-1
EMB0(1)
R/WO-1
EASHFT(1)
U-0
—
U-0
—
U-0
—
bit 0
Legend:
WO = Write-Once bit
W = Writable bit
‘1’ = Bit is set
R = Readable bit
-n = Value at POR
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7
WAIT: External Bus Wait Enable bit(1)
1= Wait states on the external bus are disabled
0= Wait states on the external bus are enabled and selected by MEMCON<5:4>
bit 6
BW: Data Bus Width Select bit(1)
1= 16-Bit Data Width modes
0= 8-Bit Data Width modes
bit 5-4
EMB1:EMB0: External Memory Bus Configuration bits(1)
11= Microcontroller mode, external bus disabled
10= Extended Microcontroller mode, 12-bit address width for external bus
01= Extended Microcontroller mode, 16-bit address width for external bus
00= Extended Microcontroller mode, 20-bit address width for external bus
bit 3
EASHFT: External Address Bus Shift Enable bit(1)
1= Address shifting enabled – external address bus is shifted to start at 000000h
0= Address shifting disabled – external address bus reflects the PC value
bit 2-0
Unimplemented: Read as ‘0’
Note 1: Implemented only on 80-pin devices.
© 2009 Microchip Technology Inc.
DS39778D-page 65
PIC18F87J11 FAMILY
To avoid this, the Extended Microcontroller mode
implements an address shifting option to enable auto-
matic address translation. In this mode, addresses
presented on the external bus are shifted down by the
size of the on-chip program memory and are remapped
to start at 0000h. This allows the complete use of the
external memory device’s memory space as an
extension of the device’s on-chip program memory.
5.1.4
EXTENDED MICROCONTROLLER
MODE AND ADDRESS SHIFTING
By default, devices in Extended Microcontroller mode
directly present the program counter value on the
external address bus for those addresses in the range
of the external memory space. In practical terms, this
means addresses in the external memory device below
the top of on-chip memory are unavailable.
FIGURE 5-3:
MEMORY MAPS FOR PIC18F87J11 FAMILY PROGRAM MEMORY MODES
(1)
(2)
Microcontroller Mode
Extended Microcontroller Mode
Extended Microcontroller Mode
(2)
with Address Shifting
On-Chip
Memory
Space
External
Memory
Space
On-Chip
Memory
Space
On-Chip
Memory
Space
External
Memory
Space
000000h
000000h
000000h
On-Chip
Program
Memory
On-Chip
Program
Memory
On-Chip
Program
Memory
No
Access
(Top of Memory)
(Top of Memory) + 1
(Top of Memory)
(Top of Memory) + 1
(Top of Memory)
(Top of Memory) + 1
External
Memory
(3)
Mapped
to
External
Memory
Space
Reads
as ‘0’s
Mapped
to
External
Memory
Space
External
Memory
1FFFFFh –
(Top of Memory)
1FFFFFh
1FFFFFh
1FFFFFh
Legend:
(Top of Memory) represents upper boundary of on-chip program memory space (see Figure 5-1 for device-specific
values). Shaded areas represent unimplemented, or inaccessible areas, depending on the mode.
Note 1: This mode is the only available mode on 64-pin devices and the default on 80-pin devices.
2: These modes are only available on 80-pin devices.
3: Addresses starting at the top of the program memory are translated to start at 0000h of the external device
whenever the EASHFT Configuration bit is set.
TABLE 5-2:
MEMORY ACCESS FOR PIC18F8X11/8616 PROGRAM MEMORY MODES
Internal Program Memory External Program Memory
Execution Table Read Table Write Execution Table Read Table Write
Operating Mode
From
From
To
From
From
To
Microcontroller
Yes
Yes
Yes
Yes
Yes
Yes
No Access
Yes
No Access
Yes
No Access
Yes
Extended Microcontroller
DS39778D-page 66
© 2009 Microchip Technology Inc.
PIC18F87J11 FAMILY
The stack operates as a 31-word by 21-bit RAM and a
5-bit Stack Pointer, STKPTR. The stack space is not
part of either program or data space. The Stack Pointer
is readable and writable and the address on the top of
the stack is readable and writable through the
Top-of-Stack Special Function Registers. Data can also
be pushed to, or popped from the stack, using these
registers.
5.1.5
PROGRAM COUNTER
The Program Counter (PC) specifies the address of the
instruction to fetch for execution. The PC is 21 bits wide
and is contained in three separate 8-bit registers. The
low byte, known as the PCL register, is both readable
and writable. The high byte, or PCH register, contains
the PC<15:8> bits; it is not directly readable or writable.
Updates to the PCH register are performed through the
PCLATH register. The upper byte is called PCU. This
register contains the PC<20:16> bits; it is also not
directly readable or writable. Updates to the PCU
register are performed through the PCLATU register.
A CALLtype instruction causes a push onto the stack.
The Stack Pointer is first incremented and the location
pointed to by the Stack Pointer is written with the
contents of the PC (already pointing to the instruction
following the CALL). A RETURNtype instruction causes
a pop from the stack. The contents of the location
pointed to by the STKPTR are transferred to the PC
and then the Stack Pointer is decremented.
The contents of PCLATH and PCLATU are transferred
to the program counter by any operation that writes
PCL. Similarly, the upper two bytes of the program
counter are transferred to PCLATH and PCLATU by an
operation that reads PCL. This is useful for computed
offsets to the PC (see Section 5.1.8.1 “Computed
GOTO”).
The Stack Pointer is initialized to ‘00000’ after all
Resets. There is no RAM associated with the location
corresponding to a Stack Pointer value of ‘00000’; this
is only a Reset value. Status bits indicate if the stack is
full, has overflowed or has underflowed.
The PC addresses bytes in the program memory. To
prevent the PC from becoming misaligned with word
instructions, the Least Significant bit of PCL is fixed to
a value of ‘0’. The PC increments by 2 to address
sequential instructions in the program memory.
5.1.6.1
Top-of-Stack Access
Only the top of the return address stack (TOS) is
readable and writable. A set of three registers,
TOSU:TOSH:TOSL, hold the contents of the stack loca-
tion pointed to by the STKPTR register (Figure 5-4). This
allows users to implement a software stack if necessary.
After a CALL, RCALL or interrupt (and ADDULNK and
SUBULNK instructions if the extended instruction set is
enabled), the software can read the pushed value by
reading the TOSU:TOSH:TOSL registers. These values
can be placed on a user-defined software stack. At
return time, the software can return these values to
TOSU:TOSH:TOSL and do a return.
The CALL, RCALL, GOTO and program branch
instructions write to the program counter directly. For
these instructions, the contents of PCLATH and
PCLATU are not transferred to the program counter.
5.1.6
RETURN ADDRESS STACK
The return address stack allows any combination of up
to 31 program calls and interrupts to occur. The PC is
pushed onto the stack when a CALLor RCALLinstruc-
tion is executed, or an interrupt is Acknowledged. The
PC value is pulled off the stack on a RETURN, RETLW
or a RETFIE instruction (and on ADDULNK and
SUBULNKinstructions if the extended instruction set is
enabled). PCLATU and PCLATH are not affected by
any of the RETURNor CALLinstructions.
The user must disable the global interrupt enable bits
while accessing the stack to prevent inadvertent stack
corruption.
FIGURE 5-4:
RETURN ADDRESS STACK AND ASSOCIATED REGISTERS
Return Address Stack <20:0>
Stack Pointer
Top-of-Stack Registers
11111
11110
11101
STKPTR<4:0>
TOSU TOSH TOSL
00010
00h
1Ah
34h
00011
00010
00001
00000
001A34h
000D58h
Top-of-Stack
© 2009 Microchip Technology Inc.
DS39778D-page 67
PIC18F87J11 FAMILY
When the stack has been popped enough times to
unload the stack, the next pop will return a value of zero
to the PC and set the STKUNF bit, while the Stack
Pointer remains at zero. The STKUNF bit will remain
set until cleared by software or until a POR occurs.
5.1.6.2
Return Stack Pointer (STKPTR)
The STKPTR register (Register 5-2) contains the Stack
Pointer value, the STKFUL (Stack Full) status bit and
the STKUNF (Stack Underflow) status bits. The value
of the Stack Pointer can be 0 through 31. The Stack
Pointer increments before values are pushed onto the
stack and decrements after values are popped off the
stack. On Reset, the Stack Pointer value will be zero.
The user may read and write the Stack Pointer value.
This feature can be used by a Real-Time Operating
System (RTOS) for return stack maintenance.
Note:
Returning a value of zero to the PC on an
underflow has the effect of vectoring the
program to the Reset vector, where the
stack conditions can be verified and
appropriate actions can be taken. This is
not the same as a Reset, as the contents
of the SFRs are not affected.
After the PC is pushed onto the stack 31 times (without
popping any values off the stack), the STKFUL bit is
set. The STKFUL bit is cleared by software or by a
POR.
5.1.6.3
PUSHand POPInstructions
Since the Top-of-Stack is readable and writable, the
ability to push values onto the stack and pull values off
the stack, without disturbing normal program execu-
tion, is a desirable feature. The PIC18 instruction set
includes two instructions, PUSH and POP, that permit
the TOS to be manipulated under software control.
TOSU, TOSH and TOSL can be modified to place data
or a return address on the stack.
The action that takes place when the stack becomes
full depends on the state of the STVREN (Stack Over-
flow Reset Enable) Configuration bit. (Refer to
Section 24.1 “Configuration Bits” for a description of
the device Configuration bits.) If STVREN is set
(default), the 31st push will push the (PC + 2) value
onto the stack, set the STKFUL bit and reset the
device. The STKFUL bit will remain set and the Stack
Pointer will be set to zero.
The PUSHinstruction places the current PC value onto
the stack. This increments the Stack Pointer and loads
the current PC value onto the stack.
If STVREN is cleared, the STKFUL bit will be set on the
31st push and the Stack Pointer will increment to 31.
Any additional pushes will not overwrite the 31st push
and the STKPTR will remain at 31.
The POP instruction discards the current TOS by
decrementing the Stack Pointer. The previous value
pushed onto the stack then becomes the TOS value.
REGISTER 5-2:
STKPTR: STACK POINTER REGISTER
R/C-0
STKFUL(1)
R/C-0
STKUNF(1)
U-0
—
R/W-0
SP4
R/W-0
SP3
R/W-0
SP2
R/W-0
SP1
R/W-0
SP0
bit 7
bit 0
Legend:
C = Clearable-only bit
W = Writable bit
‘1’ = Bit is set
R = Readable bit
-n = Value at POR
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7
bit 6
STKFUL: Stack Full Flag bit(1)
1= Stack became full or overflowed
0= Stack has not become full or overflowed
STKUNF: Stack Underflow Flag bit(1)
1= Stack underflow occurred
0= Stack underflow did not occur
bit 5
Unimplemented: Read as ‘0’
bit 4-0
SP4:SP0: Stack Pointer Location bits
Note 1: Bit 7 and bit 6 are cleared by user software or by a POR.
DS39778D-page 68
© 2009 Microchip Technology Inc.
PIC18F87J11 FAMILY
5.1.6.4
Stack Full and Underflow Resets
5.1.8
LOOK-UP TABLES IN PROGRAM
MEMORY
Device Resets on stack overflow and stack underflow
conditions are enabled by setting the STVREN bit in
Configuration Register 1L. When STVREN is set, a full
or underflow condition will set the appropriate STKFUL
or STKUNF bit and then cause a device Reset. When
STVREN is cleared, a full or underflow condition will set
the appropriate STKFUL or STKUNF bit, but not cause
a device Reset. The STKFUL or STKUNF bits are
cleared by the user software or a Power-on Reset.
There may be programming situations that require the
creation of data structures, or look-up tables, in
program memory. For PIC18 devices, look-up tables
can be implemented in two ways:
• Computed GOTO
• Table Reads
5.1.8.1
Computed GOTO
5.1.7
FAST REGISTER STACK
A computed GOTOis accomplished by adding an offset
to the program counter. An example is shown in
Example 5-2.
A Fast Register Stack is provided for the STATUS,
WREG and BSR registers to provide a “fast return”
option for interrupts. This stack is only one level deep
and is neither readable nor writable. It is loaded with the
current value of the corresponding register when the
processor vectors for an interrupt. All interrupt sources
will push values into the Stack registers. The values in
the registers are then loaded back into the working
registers if the RETFIE, FAST instruction is used to
return from the interrupt.
A look-up table can be formed with an ADDWF PCL
instruction and a group of RETLW nninstructions. The
W register is loaded with an offset into the table before
executing a call to that table. The first instruction of the
called routine is the ADDWF PCLinstruction. The next
instruction executed will be one of the RETLW nn
instructions that returns the value ‘nn’ to the calling
function.
If both low and high-priority interrupts are enabled, the
Stack registers cannot be used reliably to return from
low-priority interrupts. If a high-priority interrupt occurs
while servicing a low-priority interrupt, the Stack
register values stored by the low-priority interrupt will
be overwritten. In these cases, users must save the key
registers in software during a low-priority interrupt.
The offset value (in WREG) specifies the number of
bytes that the program counter should advance and
should be multiples of 2 (LSb = 0).
In this method, only one data byte may be stored in
each instruction location and room on the return
address stack is required.
If interrupt priority is not used, all interrupts may use the
Fast Register Stack for returns from interrupt. If no
interrupts are used, the Fast Register Stack can be
used to restore the STATUS, WREG and BSR registers
at the end of a subroutine call. To use the Fast Register
Stack for a subroutine call, a CALL label, FAST
instruction must be executed to save the STATUS,
WREG and BSR registers to the Fast Register Stack. A
RETURN, FASTinstruction is then executed to restore
these registers from the Fast Register Stack.
EXAMPLE 5-2:
COMPUTED GOTOUSING
AN OFFSET VALUE
OFFSET, W
TABLE
MOVF
CALL
ORG
TABLE
nn00h
ADDWF
RETLW
RETLW
RETLW
.
PCL
nnh
nnh
nnh
.
Example 5-1 shows a source code example that uses
the Fast Register Stack during a subroutine call and
return.
.
5.1.8.2
Table Reads
A better method of storing data in program memory
allows two bytes of data to be stored in each instruction
location.
EXAMPLE 5-1:
FAST REGISTER STACK
CODE EXAMPLE
;STATUS, WREG, BSR
;SAVED IN FAST REGISTER
;STACK
CALL SUB1, FAST
Look-up table data may be stored two bytes per
program word while programming. The Table Pointer
(TBLPTR) specifies the byte address and the Table
Latch (TABLAT) contains the data that is read from the
program memory. Data is transferred from program
memory one byte at a time.
•
•
SUB1
•
•
RETURN FAST
;RESTORE VALUES SAVED
;IN FAST REGISTER STACK
Table read operation is discussed further in
Section 6.1 “Table Reads and Table Writes”.
© 2009 Microchip Technology Inc.
DS39778D-page 69
PIC18F87J11 FAMILY
5.2.2
INSTRUCTION FLOW/PIPELINING
5.2
PIC18 Instruction Cycle
An “Instruction Cycle” consists of four Q cycles, Q1
through Q4. The instruction fetch and execute are pipe-
lined in such a manner that a fetch takes one instruction
cycle, while the decode and execute takes another
instruction cycle. However, due to the pipelining, each
instruction effectively executes in one cycle. If an
instruction causes the program counter to change (e.g.,
GOTO), then two cycles are required to complete the
instruction (Example 5-3).
5.2.1
CLOCKING SCHEME
The microcontroller clock input, whether from an
internal or external source, is internally divided by four
to generate four non-overlapping quadrature clocks
(Q1, Q2, Q3 and Q4). Internally, the program counter is
incremented on every Q1; the instruction is fetched
from the program memory and latched into the Instruc-
tion Register (IR) during Q4. The instruction is decoded
and executed during the following Q1 through Q4. The
clocks and instruction execution flow are shown in
Figure 5-5.
A fetch cycle begins with the Program Counter (PC)
incrementing in Q1.
In the execution cycle, the fetched instruction is latched
into the Instruction Register (IR) in cycle Q1. This
instruction is then decoded and executed during the
Q2, Q3 and Q4 cycles. Data memory is read during Q2
(operand read) and written during Q4 (destination
write).
FIGURE 5-5:
CLOCK/INSTRUCTION CYCLE
Q2
Q3
Q4
Q2
Q3
Q4
Q2
Q3
Q4
Q1
Q1
Q1
OSC1
Q1
Q2
Q3
Q4
Internal
Phase
Clock
PC
PC
PC + 2
PC + 4
OSC2/CLKO
(RC mode)
Execute INST (PC – 2)
Fetch INST (PC)
Execute INST (PC)
Fetch INST (PC + 2)
Execute INST (PC + 2)
Fetch INST (PC + 4)
EXAMPLE 5-3:
INSTRUCTION PIPELINE FLOW
TCY0
TCY1
TCY2
TCY3
TCY4
TCY5
1. MOVLW 55h
2. MOVWF PORTB
3. BRA SUB_1
Fetch 1
Execute 1
Fetch 2
Execute 2
Fetch 3
Execute 3
Fetch 4
4. BSF
PORTA, BIT3 (Forced NOP)
Flush (NOP)
5. Instruction @ address SUB_1
Fetch SUB_1 Execute SUB_1
All instructions are single cycle, except for any program branches. These take two cycles since the fetch instruction
is “flushed” from the pipeline while the new instruction is being fetched and then executed.
DS39778D-page 70
© 2009 Microchip Technology Inc.
PIC18F87J11 FAMILY
The CALL and GOTO instructions have the absolute
program memory address embedded into the instruc-
tion. Since instructions are always stored on word
boundaries, the data contained in the instruction is a
word address. The word address is written to PC<20:1>
which accesses the desired byte address in program
memory. Instruction #2 in Figure 5-6 shows how the
instruction, GOTO 0006h, is encoded in the program
memory. Program branch instructions, which encode a
relative address offset, operate in the same manner. The
offset value stored in a branch instruction represents the
number of single-word instructions that the PC will be
offset by. Section 25.0 “Instruction Set Summary”
provides further details of the instruction set.
5.2.3
INSTRUCTIONS IN PROGRAM
MEMORY
The program memory is addressed in bytes. Instruc-
tions are stored as two bytes or four bytes in program
memory. The Least Significant Byte of an instruction
word is always stored in a program memory location
with an even address (LSB = 0). To maintain alignment
with instruction boundaries, the PC increments in steps
of 2 and the LSB will always read ‘0’ (see Section 5.1.5
“Program Counter”).
Figure 5-6 shows an example of how instruction words
are stored in the program memory.
FIGURE 5-6:
INSTRUCTIONS IN PROGRAM MEMORY
Word Address
LSB = 1
LSB = 0
↓
Program Memory
Byte Locations →
000000h
000002h
000004h
000006h
000008h
00000Ah
00000Ch
00000Eh
000010h
000012h
000014h
Instruction 1:
Instruction 2:
MOVLW
GOTO
055h
0006h
0Fh
EFh
F0h
C1h
F4h
55h
03h
00h
23h
56h
Instruction 3:
MOVFF
123h, 456h
and used by the instruction sequence. If the first word
is skipped for some reason and the second word is
executed by itself, a NOP is executed instead. This is
necessary for cases when the two-word instruction is
preceded by a conditional instruction that changes the
PC. Example 5-4 shows how this works.
5.2.4
TWO-WORD INSTRUCTIONS
The standard PIC18 instruction set has four two-word
instructions: CALL, MOVFF, GOTO and LSFR. In all
cases, the second word of the instructions always has
‘1111’ as its four Most Significant bits; the other 12 bits
are literal data, usually a data memory address.
Note:
See Section 5.5 “Program Memory and
the Extended Instruction Set” for
information on two-word instructions in the
extended instruction set.
The use of ‘1111’ in the 4 MSbs of an instruction
specifies a special form of NOP. If the instruction is
executed in proper sequence – immediately after the
first word – the data in the second word is accessed
EXAMPLE 5-4:
CASE 1:
TWO-WORD INSTRUCTIONS
Object Code
Source Code
0110 0110 0000 0000
1100 0001 0010 0011
1111 0100 0101 0110
0010 0100 0000 0000
CASE 2:
TSTFSZ
MOVFF
REG1
REG1, REG2 ; No, skip this word
; Execute this word as a NOP
; continue code
; is RAM location 0?
ADDWF
REG3
Object Code
Source Code
TSTFSZ
0110 0110 0000 0000
1100 0001 0010 0011
1111 0100 0101 0110
0010 0100 0000 0000
REG1
; is RAM location 0?
MOVFF
REG1, REG2 ; Yes, execute this word
; 2nd word of instruction
ADDWF
REG3
; continue code
© 2009 Microchip Technology Inc.
DS39778D-page 71
PIC18F87J11 FAMILY
Most instructions in the PIC18 instruction set make use
of the Bank Pointer, known as the Bank Select Register
(BSR). This SFR holds the 4 Most Significant bits of a
location’s address; the instruction itself includes the
8 Least Significant bits. Only the four lower bits of the
BSR are implemented (BSR3:BSR0). The upper four
bits are unused; they will always read ‘0’ and cannot be
written to. The BSR can be loaded directly by using the
MOVLBinstruction.
5.3
Data Memory Organization
Note:
The operation of some aspects of data
memory are changed when the PIC18
extended instruction set is enabled. See
Section 5.6 “Data Memory and the
Extended Instruction Set” for more
information.
The data memory in PIC18 devices is implemented as
static RAM. Each register in the data memory has a
12-bit address, allowing up to 4096 bytes of data
memory. The memory space is divided into as many as
16 banks that contain 256 bytes each. The
PIC18F87J11 family implements all available banks
and provide 3936 bytes of data memory available to the
user. Figure 5-7 shows the data memory organization
for the devices.
The value of the BSR indicates the bank in data mem-
ory. The 8 bits in the instruction show the location in the
bank and can be thought of as an offset from the bank’s
lower boundary. The relationship between the BSR’s
value and the bank division in data memory is shown in
Figure 5-8.
Since up to 16 registers may share the same low-order
address, the user must always be careful to ensure that
the proper bank is selected before performing a data
read or write. For example, writing what should be
program data to an 8-bit address of F9h while the BSR
is 0Fh, will end up resetting the program counter.
The data memory contains Special Function Registers
(SFRs) and General Purpose Registers (GPRs). The
SFRs are used for control and status of the controller
and peripheral functions, while GPRs are used for data
storage and scratchpad operations in the user’s
application. Any read of an unimplemented location will
read as ‘0’s.
While any bank can be selected, only those banks that
are actually implemented can be read or written to.
Writes to unimplemented banks are ignored, while
reads from unimplemented banks will return ‘0’s. Even
so, the STATUS register will still be affected as if the
operation was successful. The data memory map in
Figure 5-7 indicates which banks are implemented.
The instruction set and architecture allow operations
across all banks. The entire data memory may be
accessed by Direct, Indirect or Indexed Addressing
modes. Addressing modes are discussed later in this
section.
In the core PIC18 instruction set, only the MOVFF
instruction fully specifies the 12-bit address of the
source and target registers. This instruction ignores the
BSR completely when it executes. All other instructions
include only the low-order address as an operand and
must use either the BSR or the Access Bank to locate
their target registers.
To ensure that commonly used registers (select SFRs
and select GPRs) can be accessed in a single cycle,
PIC18 devices implement an Access Bank. This is a
256-byte memory space that provides fast access to
select SFRs and the lower portion of GPR Bank 0 with-
out using the BSR. Section 5.3.2 “Access Bank”
provides a detailed description of the Access RAM.
5.3.1
BANK SELECT REGISTER
Large areas of data memory require an efficient
addressing scheme to make rapid access to any
address possible. Ideally, this means that an entire
address does not need to be provided for each read or
write operation. For PIC18 devices, this is accom-
plished with a RAM banking scheme. This divides the
memory space into 16 contiguous banks of 256 bytes.
Depending on the instruction, each location can be
addressed directly by its full 12-bit address, or an 8-bit
low-order address and a 4-bit Bank Pointer.
DS39778D-page 72
© 2009 Microchip Technology Inc.
PIC18F87J11 FAMILY
FIGURE 5-7:
DATA MEMORY MAP FOR PIC18F87J11 FAMILY DEVICES
When a = 0:
The BSR is ignored and the
BSR<3:0>
Data Memory Map
Access Bank is used.
00h
000h
05Fh
060h
0FFh
100h
The first 96 bytes are general
purpose RAM (from Bank 0).
Access RAM
GPR
= 0000
Bank 0
Bank 1
Bank 2
Bank 3
Bank 4
Bank 5
Bank 6
Bank 7
Bank 8
Bank 9
Bank 10
Bank 11
Bank 12
Bank 13
Bank 14
Bank 15
The remaining 160 bytes are
Special Function Registers
(from Bank 15).
FFh
00h
= 0001
= 0010
= 0011
= 0100
= 0101
= 0110
= 0111
= 1000
= 1001
= 1010
= 1011
= 1100
= 1101
= 1110
= 1111
GPR
GPR
GPR
GPR
GPR
GPR
GPR
GPR
GPR
GPR
GPR
GPR
GPR
GPR
1FFh
200h
FFh
00h
When a = 1:
The BSR specifies the bank
used by the instruction.
FFh
00h
2FFh
300h
3FFh
400h
FFh
00h
FFh
00h
4FFh
500h
FFh
00h
5FFh
600h
Access Bank
FFh
00h
6FFh
700h
00h
Access RAM Low
5Fh
60h
FFh
00h
7FFh
800h
Access RAM High
(SFRs)
FFh
FFh
00h
8FFh
900h
FFh
00h
9FFh
A00h
FFh
00h
AFFh
B00h
FFh
00h
BFFh
C00h
FFh
00h
CFFh
D00h
FFh
00h
DFFh
E00h
EFFh
F00h
F5Fh
F60h
FFFh
FFh
00h
GPR(1)
SFR
FFh
Note 1: Addresses F5Ah through F5Fh are also used by SFRs, but are not part of the Access RAM. Users must always
use the complete address, or load the proper BSR value, to access these registers.
© 2009 Microchip Technology Inc.
DS39778D-page 73
PIC18F87J11 FAMILY
FIGURE 5-8:
USE OF THE BANK SELECT REGISTER (DIRECT ADDRESSING)
Data Memory
Bank 0
(2)
(1)
From Opcode
BSR
000h
100h
7
0
7
0
00h
0
0
0
0
0
0
1
0
1
1
1
1
1
1
1
1
FFh
00h
Bank 1
(2)
Bank Select
FFh
00h
200h
300h
Bank 2
FFh
00h
Bank 3
through
Bank 13
FFh
00h
E00h
Bank 14
Bank 15
FFh
00h
F00h
FFFh
FFh
Note 1: The Access RAM bit of the instruction can be used to force an override of the selected bank (BSR<3:0>) to
the registers of the Access Bank.
2: The MOVFF instruction embeds the entire 12-bit address in the instruction.
Using this “forced” addressing allows the instruction to
operate on a data address in a single cycle without
updating the BSR first. For 8-bit addresses of 60h and
above, this means that users can evaluate and operate
on SFRs more efficiently. The Access RAM below 60h
is a good place for data values that the user might need
to access rapidly, such as immediate computational
results or common program variables. Access RAM
also allows for faster and more code efficient context
saving and switching of variables.
5.3.2
ACCESS BANK
While the use of the BSR with an embedded 8-bit
address allows users to address the entire range of
data memory, it also means that the user must always
ensure that the correct bank is selected. Otherwise,
data may be read from or written to the wrong location.
This can be disastrous if a GPR is the intended target
of an operation, but an SFR is written to instead.
Verifying and/or changing the BSR for each read or
write to data memory can become very inefficient.
The mapping of the Access Bank is slightly different
when the extended instruction set is enabled (XINST
Configuration bit = 1). This is discussed in more detail
in Section 5.6.3 “Mapping the Access Bank in
Indexed Literal Offset Mode”.
To streamline access for the most commonly used data
memory locations, the data memory is configured with
an Access Bank, which allows users to access a
mapped block of memory without specifying a BSR.
The Access Bank consists of the first 96 bytes of
memory (00h-5Fh) in Bank 0 and the last 160 bytes of
memory (60h-FFh) in Bank 15. The lower half is known
as the “Access RAM” and is composed of GPRs. The
upper half is where the device’s SFRs are mapped.
These two areas are mapped contiguously in the
Access Bank and can be addressed in a linear fashion
by an 8-bit address (Figure 5-7).
5.3.3
GENERAL PURPOSE
REGISTER FILE
PIC18 devices may have banked memory in the GPR
area. This is data RAM which is available for use by all
instructions. GPRs start at the bottom of Bank 0
(address 000h) and grow upwards towards the bottom
of the SFR area. GPRs are not initialized by a
Power-on Reset and are unchanged on all other
Resets.
The Access Bank is used by core PIC18 instructions
that include the Access RAM bit (the ‘a’ parameter in
the instruction). When ‘a’ is equal to ‘1’, the instruction
uses the BSR and the 8-bit address included in the
opcode for the data memory address. When ‘a’ is ‘0’,
however, the instruction is forced to use the Access
Bank address map; the current value of the BSR is
ignored entirely.
DS39778D-page 74
© 2009 Microchip Technology Inc.
PIC18F87J11 FAMILY
ALU’s STATUS register is described later in this
section. Registers related to the operation of the
peripheral features are described in the chapter for that
peripheral.
5.3.4
SPECIAL FUNCTION REGISTERS
The Special Function Registers (SFRs) are registers
used by the CPU and peripheral modules for controlling
the desired operation of the device. These registers are
implemented as static RAM. SFRs start at the top of
data memory (FFFh) and extend downward to occupy
more than the top half of Bank 15 (F5Ah to FFFh). A list
of these registers is given inTable 5-3, Table 5-4 and
Table 5-5.
The SFRs are typically distributed among the
peripherals whose functions they control. Unused SFR
locations are unimplemented and read as ‘0’s
Note:
Addresses, F5Ah through F5Fh, are not
part of the Access Bank. These registers
must always be accessed using the Bank
Select Register.
The SFRs can be classified into two sets: those
associated with the “core” device functionality (ALU,
Resets and interrupts) and those related to the
peripheral functions. The Reset and interrupt registers
are described in their respective chapters, while the
TABLE 5-3:
SPECIAL FUNCTION REGISTER MAP FOR PIC18F87J11 FAMILY DEVICES
Address
Name
Address
Name
Address
Name
Address
Name
Address
Name
Address
Name
(1)
FFFh
FFEh
FFDh
FFCh
FFBh
FFAh
FF9h
FF8h
FF7h
FF6h
FF5h
FF4h
FF3h
FF2h
FF1h
FF0h
FEFh
TOSU
TOSH
FDFh
INDF2
FBFh ECCP1AS
FBEh ECCP1DEL
F9Fh
F9Eh
F9Dh
F9Ch
IPR1
PIR1
F7Fh
SPBRGH1
F5Fh PMDIN2H
(1)
(1)
FDEh POSTINC2
F7Eh BAUDCON1
F7Dh SPBRGH2
F7Ch BAUDCON2
F5Eh
F5Dh
F5Ch
PMDIN2L
PMEH
TOSL
FDDh POSTDEC2
FBDh
FBCh
CCPR1H
CCPR1L
PIE1
(1)
STKPTR
PCLATU
PCLATH
PCL
FDCh PREINC2
RCSTA2
PMEL
(1)
FDBh
FDAh
FD9h
FD8h
FD7h
FD6h
FD5h
FD4h
PLUSW2
FBBh CCP1CON
FBAh ECCP2AS
FB9h ECCP2DEL
F9Bh OSCTUNE
F7Bh
F7Ah
F79h
F78h
F77h
F76h
F75h
F74h
F73h
F72h
F71h
F70h
F6Fh
F6Eh
F6Dh
F6Ch
F6Bh
F6Ah
TMR3H
TMR3L
T3CON
TMR4
F5Bh PMSTATH
F5Ah PMSTATL
(2)
FSR2H
FSR2L
STATUS
TMR0H
TMR0L
T0CON
—
F9Ah
F99h
F98h
F97h
F96h
F95h
F94h
F93h
F92h
F91h
F90h
F8Fh
F8Eh
F8Dh
F8Ch
F8Bh
F8Ah
F89h
F88h
F87h
F86h
F85h
F84h
F83h
F82h
F81h
F80h
TRISJ
TRISH
(2)
F59h
F58h
F57h
F56h
F55h
F54h
F53h
F52h
F51h
F50h
F4Fh
F4Eh
F4Dh
F4Ch
F4Bh
F4Ah
F49h
F48h
F47h
F46h
F45h
F44h
F43h
F42h
F41h
F40h
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
TBLPTRU
TBLPTRH
TBLPTRL
TABLAT
PRODH
PRODL
INTCON
INTCON2
INTCON3
FB8h
FB7h
CCPR2H
CCPR2L
TRISG
TRISF
TRISE
TRISD
TRISC
TRISB
TRISA
(3)
PR4
FB6h CCP2CON
FB5h ECCP3AS
FB4h ECCP3DEL
T4CON
CCPR4H
CCPR4L
(3)
FD3h OSCCON
FB3h
FB2h
CCPR3H
CCPR3L
CCP4CON
CCPR5H
FD2h
FD1h
FD0h
FCFh
FCEh
FCDh
FCCh
FCBh
FCAh
FC9h
FC8h
FC7h
CM1CON
(2)
CM2CON
RCON
FB1h CCP3CON
LATJ
CCPR5L
(2)
FB0h
FAFh
FAEh
FADh
FACh
FABh
FAAh
FA9h
FA8h
FA7h
FA6h
FA5h
FA4h
FA3h
FA2h
FA1h
FA0h
SPBRG1
RCREG1
TXREG1
TXSTA1
RCSTA1
SPBRG2
RCREG2
TXREG2
TXSTA2
EECON2
EECON1
IPR3
LATH
CCP5CON
SSP2BUF
SSP2ADD
SSP2STAT
SSP2CON1
SSP2CON2
CMSTAT
(1)
(3)
INDF0
TMR1H
LATG
LATF
LATE
LATD
LATC
LATB
LATA
(1)
(3)
FEEh POSTINC0
TMR1L
(1)
(3)
FEDh POSTDEC0
T1CON
(1)
(3)
FECh PREINC0
TMR2
(1)
(3)
FEBh
FEAh
FE9h
FE8h
FE7h
PLUSW0
PR2
FSR0H
FSR0L
WREG
T2CON
(4)
SSP1BUF
SSP1ADD
SSP1STAT
F69h PMADDRH
(2)
(4)
PORTJ
F68h PMADDRL
(1)
(2)
INDF1
PORTH
PORTG
PORTF
PORTE
PORTD
PORTC
PORTB
PORTA
F67h
F66h
F65h
F64h
F63h
F62h
PMDIN1H
(1)
(1)
FE6h POSTINC1
FC6h SSP1CON1
FC5h SSP1CON2
PMDIN1L
PMCONH
PMCONL
FE5h POSTDEC1
(1)
FE4h PREINC1
FC4h
FC3h
FC2h
FC1h
FC0h
ADRESH
ADRESL
PIR3
(1)
FE3h
FE2h
FE1h
FE0h
PLUSW1
PIE3
PMMODEH
PMMODEL
(3)
FSR1H
FSR1L
BSR
ADCON0
ADCON1
IPR2
(3)
PIR2
F61h PMDOUT2H
F60h PMDOUT2L
WDTCON
PIE2
Note 1:
This is not a physical register.
This register is not available on 64-pin devices.
This register shares the same address with another register (see Table 5-4 for alternate register).
The PMADDRH/L and PMDOUT1H/L register pairs share the same address. PMADDR is used in Master modes and PMDOUT1 is used
in Slave modes.
2:
3:
4:
© 2009 Microchip Technology Inc.
DS39778D-page 75
PIC18F87J11 FAMILY
5.3.4.1
Shared Address SFRs
5.3.4.2
Context Defined SFRs
In several locations in the SFR bank, a single address
is used to access two different hardware registers. In
these cases, a “legacy” register of the standard PIC18
SFR set (such as OSCCON, T1CON, etc.) shares its
address with an alternate register. These alternate reg-
isters are associated with enhanced configuration
options for peripherals, or with new device features not
included in the standard PIC18 SFR map. A complete
list of shared register addresses and the registers
associated with them is provided in Table 5-4.
In addition to the shared address SFRs, there are
several registers that share the same address in the
SFR space, but are not accessed with the ADSHR bit.
Instead, the register’s definition and use depends on
the operating mode of its associated peripheral. These
registers are:
• SSPxADD and SSPxMSK: These are two
separate hardware registers, accessed through a
single SFR address. The operating mode of the
MSSP module determines which register is being
accessed. See Section 19.4.3.4 “7-Bit Address
Masking Mode” for additional details.
Access to the alternate registers is enabled in software
by setting the ADSHR bit in the WDTCON register
(Register 5-3). ADSHR must be manually set or
cleared to access the alternate or legacy registers, as
required. Since the bit remains in a given state until
changed, users should always verify the state of
ADSHR before writing to any of the shared SFR
addresses.
• PMADDRH/L and PMDOUT2H/L: In this case,
these named buffer pairs are actually the same
physical registers. The PMP module’s operating
mode determines what function the registers take
on. See Section 11.1.2 “Data Registers” for
additional details.
TABLE 5-4:
SHARED SFR ADDRESSES FOR PIC18F87J11 FAMILY DEVICES
Address
Name
Address
Name
Address
Name
FD3h
FCFh
FCEh
(D)
OSCCON
REFOCON
TMR1H
FCDh
(D)
(A)
(D)
(A)
(D)
(A)
T1CON
ODCON3
TMR2
FC2h
(D)
(A)
(D)
(A)
(D)
(A)
ADCON0
ANCON1
ADCON1
ANCON0
PR4
(A)
(D)
(A)
(D)
(A)
FCCh
FCBh
FC1h
F77h
ODCON1
TMR1L
PADCFG1
PR2
(1)
ODCON2
MEMCON
CVRCON
Legend:
(D) = Default SFR, accessible only when ADSHR = 0; (A) = Alternate SFR, accessible only when ADSHR = 1.
Note 1: Implemented in 80-pin devices only.
REGISTER 5-3:
WDTCON: WATCHDOG TIMER CONTROL REGISTER
R/W-0
R-x
LVDSTAT
U-0
—
R/W-0
U-0
—
U-0
—
U-0
—
U-0
REGSLP
bit 7
ADSHR
SWDTEN
bit 0
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
-n = Value at POR
bit 7
bit 6
REGSLP: Voltage Regulator Low-Power Operation Enable bit
For details of bit operation, see Register 24-9.
LVDSTAT: LVD Status bit
1= VDDCORE > 2.45V
0= VDDCORE < 2.45V
bit 5
bit 4
Unimplemented: Read as ‘0’
ADSHR: Shared Address SFR Select bit
1= Alternate SFR is selected
0= Default (Legacy) SFR is selected
bit 3-1
bit 0
Unimplemented: Read as ‘0’
SWDTEN: Software Controlled Watchdog Timer Enable bit
For details of bit operation, see Register 24-9.
DS39778D-page 76
© 2009 Microchip Technology Inc.
PIC18F87J11 FAMILY
TABLE 5-5:
REGISTER FILE SUMMARY (PIC18F87J11 FAMILY)
Details
on
Page:
Value on
POR, BOR
File Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
TOSU
—
—
—
Top-of-Stack Upper Byte (TOS<20:16>)
---0 0000
0000 0000
0000 0000
00-0 0000
---0 0000
0000 0000
0000 0000
--00 0000
0000 0000
0000 0000
0000 0000
57, 67
57, 67
57, 67
57, 68
57, 67
57, 67
57, 67
57, 98
57, 98
57, 98
57, 98
TOSH
Top-of-Stack High Byte (TOS<15:8>)
Top-of-Stack Low Byte (TOS<7:0>)
TOSL
STKPTR
PCLATU
PCLATH
PCL
STKFUL
—
STKUNF
—
—
bit 21(1)
SP4
SP3
SP2
SP1
SP0
Holding Register for PC<20:16>
Holding Register for PC<15:8>
PC Low Byte (PC<7:0>)
TBLPTRU
TBLPTRH
TBLPTRL
TABLAT
PRODH
PRODL
INTCON
—
—
bit 21
Program Memory Table Pointer Upper Byte (TBLPTR<20:16>)
Program Memory Table Pointer High Byte (TBLPTR<15:8>)
Program Memory Table Pointer Low Byte (TBLPTR<7:0>)
Program Memory Table Latch
Product Register High Byte
xxxx xxxx 57, 111
xxxx xxxx 57, 111
0000 000x 57, 115
Product Register Low Byte
GIE/GIEH
PEIE/GIEL
TMR0IE
INT0IE
RBIE
TMR0IF
INT0IF
RBIF
INTCON2
INTCON3
INDF0
RBPU
INTEDG0
INT1IP
INTEDG1
INT3IE
INTEDG2
INT2IE
INTEDG3
INT1IE
TMR0IP
INT3IF
INT3IP
INT2IF
RBIP
1111 1111 57, 115
1100 0000 57, 115
INT2IP
INT1IF
Uses contents of FSR0 to address data memory – value of FSR0 not changed (not a physical register)
Uses contents of FSR0 to address data memory – value of FSR0 post-incremented (not a physical register)
Uses contents of FSR0 to address data memory – value of FSR0 post-decremented (not a physical register)
Uses contents of FSR0 to address data memory – value of FSR0 pre-incremented (not a physical register)
N/A
N/A
N/A
N/A
N/A
57, 84
57, 85
57, 85
57, 85
57, 85
POSTINC0
POSTDEC0
PREINC0
PLUSW0
Uses contents of FSR0 to address data memory – value of FSR0 pre-incremented (not a physical register) –
value of FSR0 offset by W
FSR0H
—
—
—
—
Indirect Data Memory Address Pointer 0 High Byte
---- xxxx
xxxx xxxx
xxxx xxxx
N/A
57, 84
57, 84
57, 69
57, 84
57, 85
57, 85
57, 85
57, 85
FSR0L
Indirect Data Memory Address Pointer 0 Low Byte
Working Register
WREG
INDF1
Uses contents of FSR1 to address data memory – value of FSR1 not changed (not a physical register)
Uses contents of FSR1 to address data memory – value of FSR1 post-incremented (not a physical register)
Uses contents of FSR1 to address data memory – value of FSR1 post-decremented (not a physical register)
Uses contents of FSR1 to address data memory – value of FSR1 pre-incremented (not a physical register)
POSTINC1
POSTDEC1
PREINC1
PLUSW1
N/A
N/A
N/A
Uses contents of FSR1 to address data memory – value of FSR1 pre-incremented (not a physical register) –
value of FSR1 offset by W
N/A
FSR1H
—
—
—
—
Indirect Data Memory Address Pointer 1 High Byte
---- xxxx
xxxx xxxx
---- 0000
N/A
57, 84
57, 84
57, 72
58, 84
58, 85
58, 85
58, 85
58, 85
FSR1L
Indirect Data Memory Address Pointer 1 Low Byte
BSR
—
—
—
—
Bank Select Register
INDF2
Uses contents of FSR2 to address data memory – value of FSR2 not changed (not a physical register)
Uses contents of FSR2 to address data memory – value of FSR2 post-incremented (not a physical register)
Uses contents of FSR2 to address data memory – value of FSR2 post-decremented (not a physical register)
Uses contents of FSR2 to address data memory – value of FSR2 pre-incremented (not a physical register)
POSTINC2
POSTDEC2
PREINC2
PLUSW2
N/A
N/A
N/A
Uses contents of FSR2 to address data memory – value of FSR2 pre-incremented (not a physical register) –
value of FSR2 offset by W
N/A
Legend:
x= unknown, u= unchanged, -= unimplemented, q= value depends on condition. Bold indicates shared access SFRs.
Bit 21 of the PC is only available in Serial Programming modes.
Note 1:
2:
3:
4:
5:
6:
Default (legacy) SFR at this address, available when WDTCON<4> = 0.
Configuration SFR, overlaps with default SFR at this address; available only when WDTCON<4> = 1.
Reset value is ‘0’ when Two-Speed Start-up is enabled and ‘1’ if disabled.
The SSPxMSK registers are only accessible when SSPxCON2<3:0> = 1001.
Alternate names and definitions for these bits when the MSSP modules are operating in I2C™ Slave mode. See Section 19.4.3.2
“Address Masking Modes” for details
7:
These bits and/or registers are only available in 80-pin devices; otherwise, they are unimplemented and read as ‘0’. Reset values are
shown for 80-pin devices.
8:
9:
These bits are only available in select oscillator modes (FOSC2 Configuration bit = 0); otherwise, they are unimplemented.
The PMADDRH/PMDOUT1H and PMADDRL/PMDOUT1L register pairs share the physical registers and addresses, but have different
functions determined by the module’s operating mode. See Section 11.1.2 “Data Registers” for more information.
© 2009 Microchip Technology Inc.
DS39778D-page 77
PIC18F87J11 FAMILY
TABLE 5-5:
REGISTER FILE SUMMARY (PIC18F87J11 FAMILY) (CONTINUED)
Details
on
Page:
Value on
POR, BOR
File Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
FSR2H
FSR2L
STATUS
TMR0H
TMR0L
T0CON
—
—
—
—
Indirect Data Memory Address Pointer 2 High Byte
---- xxxx
xxxx xxxx
---x xxxx
58, 84
58, 84
58, 82
Indirect Data Memory Address Pointer 2 Low Byte
—
—
—
N
OV
Z
DC
C
Timer0 Register High Byte
Timer0 Register Low Byte
0000 0000 58, 181
xxxx xxxx 58, 181
1111 1111 58, 180
TMR0ON
IDLEN
ROON
CON
T08BIT
IRCF2
—
T0CS
IRCF1
ROSSLP
CPOL
T0SE
IRCF0
PSA
T0PS2
—
T0PS1
SCS1
T0PS0
SCS0
OSCCON(2)
REFOCON(3)
/
OSTS(4)
RODIV3
EVPOL0
EVPOL0
0110 q100
58, 34
58, 41
ROSEL
EVPOL1
EVPOL1
RODIV2
CREF
CREF
RODIV1
CCH1
RODIV0 0-00 0000
CM1CON
COE
COE
CCH0
CCH0
0001 1111 58, 304
0001 1111 58, 304
CM2CON
CON
CPOL
CCH1
RCON
IPEN
—
CM
RI
TO
PD
POR
BOR
0-11 1100 56, 58,
127
TMR1H(2)
ODCON1(3)
TMR1L(2)
ODCON2(3)
T1CON (2)
ODCON3(3)
TMR2(2)
PADCFG1(3)
PR2(2)
/
Timer1 Register High Byte
xxxx xxxx 58, 184
—
—
—
CCP5OD
CCP4OD
ECCP3OD ECCP2OD ECCP1OD ---0 0000 58, 131
xxxx xxxx 58, 184
/
Timer1 Register Low Byte
—
—
T1RUN
—
—
T1CKPS1
—
—
T1CKPS0
—
—
T1OSCEN
—
—
T1SYNC
—
U2OD
TMR1CS
SPI2OD
U1OD
---- --00 58, 131
/
RD16
TMR1ON 0000 0000 58, 184
SPI1OD ---- --00 58, 131
0000 0000 58, 189
—
/
Timer2 Register
—
—
—
—
—
—
—
—
—
PMPTTL ---- ---0 58, 132
1111 1111 58, 189
/
Timer2 Period Register
MEMCON(3,7)
EDBIS
—
—
WAIT1
WAIT0
WM1
WM0
0-00 --00 58, 100
T2CON
T2OUTPS3 T2OUTPS2 T2OUTPS1 T2OUTPS0 TMR2ON
T2CKPS1 T2CKPS0 -000 0000 58, 189
SSP1BUF
MSSP1 Receive Buffer/Transmit Register
xxxx xxxx 58, 224,
233
SSP1ADD/
SSP1MSK(5)
SSP1STAT
MSSP1 Address Register (I2C™ Slave mode), MSSP1 Baud Rate Reload Register (I2C Master mode)
0000 0000 58, 233
0000 0000 58, 240
MSK7
SMP
MSK6
CKE
MSK5
D/A
MSK4
P
MSK3
S
MSK2
R/W
MSK1
UA
MSK0
BF
0000 0000 58, 224,
234
SSP1CON1
SSP1CON2
WCOL
SSPOV
SSPEN
CKP
SSPM3
SSPM2
SSPM1
SSPM0
0000 0000 58, 225,
235
GCEN
GCEN
ACKSTAT
ACKDT
ACKEN
RCEN
PEN
RSEN/
SEN
SEN
0000 0000 58, 236,
270
ACKSTAT ADMSK5(6) ADMSK4(6) ADMSK3(6) ADMSK2(6) ADMSK1(6)
ADRESH
ADRESL
A/D Result Register High Byte
A/D Result Register Low Byte
xxxx xxxx 59, 293
xxxx xxxx 59, 293
ADCON0(2)
ANCON1(3)
ADCON1(2)
ANCON0(3)
WDTCON
/
/
VCFG1
PCFG15
ADFM
VCFG0
PCFG14
ADCAL
CHS3
PCFG13
ACQT2
—
CHS2
PCFG12
ACQT1
PCFG4
ADSHR
CHS1
PCFG11
ACQT0
PCFG3
—
CHS0
PCFG10
ADCS2
PCFG2
—
GO/DONE
PCFG9
ADCS1
PCFG1
—
ADON
PCFG8
ADCS0
PCFG0
0000 0000 59, 293
0000 0000 59, 295
0000 0000 59, 294
00-0 0000 59, 295
PCFG7
REGSLP
PCFG6
LVDSTAT
—
SWDTEN 0x-0 ---0 59, 323
Legend:
x= unknown, u= unchanged, -= unimplemented, q= value depends on condition. Bold indicates shared access SFRs.
Bit 21 of the PC is only available in Serial Programming modes.
Note 1:
2:
3:
4:
5:
6:
Default (legacy) SFR at this address, available when WDTCON<4> = 0.
Configuration SFR, overlaps with default SFR at this address; available only when WDTCON<4> = 1.
Reset value is ‘0’ when Two-Speed Start-up is enabled and ‘1’ if disabled.
The SSPxMSK registers are only accessible when SSPxCON2<3:0> = 1001.
Alternate names and definitions for these bits when the MSSP modules are operating in I2C™ Slave mode. See Section 19.4.3.2
“Address Masking Modes” for details
7:
These bits and/or registers are only available in 80-pin devices; otherwise, they are unimplemented and read as ‘0’. Reset values are
shown for 80-pin devices.
8:
9:
These bits are only available in select oscillator modes (FOSC2 Configuration bit = 0); otherwise, they are unimplemented.
The PMADDRH/PMDOUT1H and PMADDRL/PMDOUT1L register pairs share the physical registers and addresses, but have different
functions determined by the module’s operating mode. See Section 11.1.2 “Data Registers” for more information.
DS39778D-page 78
© 2009 Microchip Technology Inc.
PIC18F87J11 FAMILY
TABLE 5-5:
REGISTER FILE SUMMARY (PIC18F87J11 FAMILY) (CONTINUED)
Details
on
Page:
Value on
POR, BOR
File Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
ECCP1AS
ECCP1DEL
CCPR1H
ECCP1ASE ECCP1AS2 ECCP1AS1 ECCP1AS0 PSS1AC1
PSS1AC0
P1DC2
PSS1BD1 PSS1BD0 0000 0000 59, 221
P1RSEN
P1DC6
P1DC5
P1DC4
P1DC3
P1DC1
P1DC0
0000 0000 59, 221
xxxx xxxx 59, 221
xxxx xxxx 59, 221
Capture/Compare/PWM Register 1 HIgh Byte
Capture/Compare/PWM Register 1 Low Byte
CCPR1L
CCP1CON
ECCP2AS
ECCP2DEL
CCPR2H
P1M1
P1M0
DC1B1
DC1B0
CCP1M3
CCP1M2
PSS2AC0
P2DC2
CCP1M1
CCP1M0 0000 0000 59, 221
ECCP2ASE ECCP2AS2 ECCP2AS1 ECCP2AS0 PSS2AC1
PSS2BD1 PSS2BD0 0000 0000 59, 221
P2RSEN
P2DC6
P2DC5
P2DC4
P2DC3
P2DC1
P2DC0
0000 0000 59, 221
xxxx xxxx 59, 221
xxxx xxxx 59, 221
Capture/Compare/PWM Register 2 High Byte
Capture/Compare/PWM Register 2 Low Byte
CCPR2L
CCP2CON
ECCP3AS
ECCP3DEL
CCPR3H
P2M1
P2M0
DC2B1
DC2B0
CCP2M3
CCP2M2
PSS3AC0
P3DC2
CCP2M1
CCP2M0 0000 0000 59, 221
ECCP3ASE ECCP3AS2 ECCP3AS1 ECCP3AS0 PSS3AC1
PSS3BD1 PSS3BD0 0000 0000 59, 221
P3RSEN
P3DC6
P3DC5
P3DC4
P3DC3
P3DC1
P3DC0
0000 0000 59, 221
xxxx xxxx 59, 221
xxxx xxxx 59, 221
Capture/Compare/PWM Register 1 High Byte
Capture/Compare/PWM Register 1 Low Byte
CCPR3L
CCP3CON
SPBRG1
P3M1
P3M0
DC3B1
DC3B0
CCP3M3
CCP3M2
CCP3M1
CCP3M0 0000 0000 59, 221
0000 0000 59, 275
EUSART1 Baud Rate Generator Register Low Byte
EUSART1 Receive Register
RCREG1
0000 0000 59, 283,
284
TXREG1
EUSART1 Transmit Register
xxxx xxxx 59, 281,
282
TXSTA1
RCSTA1
SPBRG2
RCREG2
CSRC
SPEN
TX9
RX9
TXEN
SREN
SYNC
CREN
SENDB
ADDEN
BRGH
FERR
TRMT
OERR
TX9D
RX9D
0000 0010 59, 281
0000 000x 59, 283
0000 0000 59, 275
EUSART2 Baud Rate Generator Register Low Byte
EUSART2 Receive Register
0000 0000 59, 283,
284
TXREG2
EUSART2 Transmit Register
0000 0000 59, 281,
282
TXSTA2
EECON2
EECON1
IPR3
CSRC
TX9
TXEN
SYNC
SENDB
BRGH
TRMT
TX9D
0000 0010 59, 281
Program Memory Control Register 2 (not a physical register)
---- ----
--00 x00-
59, 90
59, 90
—
—
WPROG
RC2IP
RC2IF
RC2IE
CM1IP
CM1IF
CM1IE
RC1IP
RC1IF
RC1IE
SREN
TUN5
FREE
TX2IP
TX2IF
TX2IE
—
WRERR
TMR4IP
TMR4IF
TMR4IE
BCL1IP
BCL1IF
BCL1IE
SSP1IP
SSP1IF
SSP1IE
ADDEN
TUN3
WREN
CCP5IP
CCP5IF
CCP5IE
LVDIP
WR
—
SSP2IP
SSP2IF
SSP2IE
OSCFIP
OSCFIF
OSCFIE
PMPIP
PMPIF
PMPIE
SPEN
BCL2IP
BCL2IF
BCL2IE
CM2IP
CM2IF
CM2IE
ADIP
CCP4IP
CCP4IF
CCP4IE
TMR3IP
TMR3IF
TMR3IE
TMR2IP
TMR2IF
TMR2IE
OERR
CCP3IP
CCP3IF
CCP3IE
CCP2IP
CCP2IF
CCP2IE
1111 1111 60, 124
0000 0000 60, 118
0000 0000 60, 121
111- 1111 60, 124
000- 0000 60, 118
000- 0000 60, 121
PIR3
PIE3
IPR2
PIR2
—
LVDIF
PIE2
—
LVDIE
IPR1
TX1IP
TX1IF
TX1IE
CREN
TUN4
CCP1IP
CCP1IF
CCP1IE
FERR
TMR1IP 1111 1111 60, 124
TMR1IF 0000 0000 60, 118
TMR1IE 0000 0000 60, 121
PIR1
ADIF
PIE1
ADIE
RCSTA2
OSCTUNE
RX9
RX9D
TUN0
0000 000x 60, 283
0000 0000 60, 35
INTSRC
PLLEN
TUN2
TUN1
Legend:
x= unknown, u= unchanged, -= unimplemented, q= value depends on condition. Bold indicates shared access SFRs.
Bit 21 of the PC is only available in Serial Programming modes.
Note 1:
2:
3:
4:
5:
6:
Default (legacy) SFR at this address, available when WDTCON<4> = 0.
Configuration SFR, overlaps with default SFR at this address; available only when WDTCON<4> = 1.
Reset value is ‘0’ when Two-Speed Start-up is enabled and ‘1’ if disabled.
The SSPxMSK registers are only accessible when SSPxCON2<3:0> = 1001.
Alternate names and definitions for these bits when the MSSP modules are operating in I2C™ Slave mode. See Section 19.4.3.2
“Address Masking Modes” for details
7:
These bits and/or registers are only available in 80-pin devices; otherwise, they are unimplemented and read as ‘0’. Reset values are
shown for 80-pin devices.
8:
9:
These bits are only available in select oscillator modes (FOSC2 Configuration bit = 0); otherwise, they are unimplemented.
The PMADDRH/PMDOUT1H and PMADDRL/PMDOUT1L register pairs share the physical registers and addresses, but have different
functions determined by the module’s operating mode. See Section 11.1.2 “Data Registers” for more information.
© 2009 Microchip Technology Inc.
DS39778D-page 79
PIC18F87J11 FAMILY
TABLE 5-5:
REGISTER FILE SUMMARY (PIC18F87J11 FAMILY) (CONTINUED)
Details
on
Page:
Value on
POR, BOR
File Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
TRISJ(7)
TRISH(7)
TRISG
TRISJ7
TRISH7
—
TRISJ6
TRISH6
—
TRISJ5
TRISH5
—
TRISJ4
TRISH4
TRISG4
TRISF4
TRISE4
TRISD4
TRISC4
TRISB4
TRISA4
LATJ4
LATH4
LATG4
LATF4
LATE4
LATD4
LATC4
LATB4
LATA4
RJ4
TRISJ3
TRISH3
TRISG3
TRISF3
TRISE3
TRISD3
TRISC3
TRISB3
TRISA3
LATJ3
LATH3
LATG3
LATF3
LATE3
LATD3
LATC3
LATB3
LATA3
RJ3
TRISJ2
TRISH2
TRISG2
TRISF2
TRISE2
TRISD2
TRISC2
TRISB2
TRISA2
LATJ2
LATH2
LATG2
LATF2
LATE2
LATD2
LATC2
LATB2
LATA2
RJ2
TRISJ1
TRISH1
TRISG1
TRISF1
TRISE1
TRISD1
TRISC1
TRISB1
TRISA1
LATJ1
LATH1
LATG1
LATF1
LATE1
LATD1
LATC1
LATB1
LATA1
RJ1
TRISJ0
TRISH0
1111 1111 60, 152
1111 1111 60, 150
TRISG0 ---1 1111 60, 148
TRISF
TRISF7
TRISE7
TRISD7
TRISC7
TRISB7
TRISA7(8)
LATJ7
LATH7
—
TRISF6
TRISE6
TRISD6
TRISC6
TRISB6
TRISA6(8)
LATJ6
LATH6
—
TRISF5
TRISE5
TRISD5
TRISC5
TRISB5
TRISA5
LATJ5
LATH5
—
—
1111 111- 60, 146
1111 1111 60, 143
1111 1111 60, 140
1111 1111 60, 138
1111 1111 60, 136
1111 1111 60, 134
xxxx xxxx 60, 152
xxxx xxxx 60, 150
---x xxxx 60, 148
xxxx xxx- 60, 146
xxxx xxxx 60, 143
xxxx xxxx 60, 140
xxxx xxxx 60, 138
xxxx xxxx 60, 136
xxxx xxxx 60, 134
xxxx xxxx 61, 152
0000 xxxx 61, 150
000x xxxx 61, 148
x000 000- 61, 146
xxxx xxxx 61, 143
xxxx xxxx 61, 140
xxxx xxxx 61, 138
xxxx xxxx 61, 136
000x 0000 61, 134
0000 0000 61, 275
0100 0-00 61, 275
0000 0000 61, 275
0100 0-00 61, 275
xxxx xxxx 61, 196
xxxx xxxx 61, 196
TRISE
TRISE0
TRISD0
TRISC0
TRISB0
TRISA0
LATJ0
LATH0
LATG0
—
TRISD
TRISC
TRISB
TRISA
LATJ(7)
LATH(7)
LATG
LATF
LATF7
LATE7
LATD7
LATC7
LATB7
LATA7(8)
RJ7
LATF6
LATE6
LATD6
LATC6
LATB6
LATA6(8)
RJ6
LATF5
LATE5
LATD5
LATC5
LATB5
LATA5
RJ5
LATE
LATE0
LATD0
LATC0
LATB0
LATA0
RJ0
LATD
LATC
LATB
LATA
PORTJ(7)
PORTH(7)
PORTG
PORTF
PORTE
PORTD
PORTC
PORTB
PORTA
SPBRGH1
BAUDCON1
SPBRGH2
BAUDCON2
TMR3H
TMR3L
RH7
RH6
RH5
RJPU(7)
RH4
RH3
RH2
RH1
RH0
RDPU
RF7
REPU
RF6
RG4
RG3
RG2
RG1
RG0
RF5
RF4
RF3
RF2
RF1
—
RE7
RE6
RE5
RE4
RE3
RE2
RE1
RE0
RD7
RD6
RD5
RD4
RD3
RD2
RD1
RD0
RC7
RC6
RC5
RC4
RC3
RC2
RC1
RC0
RB7
RA7(8)
RB6
RA6(8)
RB5
RB4
RB3
RB2
RB1
RB0
RA5
RA4
RA3
RA2
RA1
RA0
EUSART1 Baud Rate Generator Register High Byte
ABDOVF RCIDL RXDTP TXCKP
EUSART2 Baud Rate Generator Register High Byte
BRG16
BRG16
—
—
WUE
WUE
ABDEN
ABDEN
ABDOVF
RCIDL
RXDTP
TXCKP
Timer3 Register High Byte
Timer3 Register Low Byte
T3CON
TMR4
RD16
T3CCP2
T3CKPS1
CVRR
T3CKPS0
CVRSS
T3CCP1
CVR3
T3SYNC
CVR2
TMR3CS
CVR1
TMR3ON 0000 0000 61, 196
0000 0000 61, 195
Timer4 Register
PR4(2)
/
Timer4 Period Register
1111 1111 61, 196
CVRCON(3)
CVREN
—
CVROE
CVR0
0000 0000 61, 312
T4CON
T4OUTPS3 T4OUTPS2 T4OUTPS1 T4OUTPS0 TMR4ON
T4CKPS1 T4CKPS0 -000 0000 61, 195
Legend:
x= unknown, u= unchanged, -= unimplemented, q= value depends on condition. Bold indicates shared access SFRs.
Bit 21 of the PC is only available in Serial Programming modes.
Note 1:
2:
3:
4:
5:
6:
Default (legacy) SFR at this address, available when WDTCON<4> = 0.
Configuration SFR, overlaps with default SFR at this address; available only when WDTCON<4> = 1.
Reset value is ‘0’ when Two-Speed Start-up is enabled and ‘1’ if disabled.
The SSPxMSK registers are only accessible when SSPxCON2<3:0> = 1001.
Alternate names and definitions for these bits when the MSSP modules are operating in I2C™ Slave mode. See Section 19.4.3.2
“Address Masking Modes” for details
7:
These bits and/or registers are only available in 80-pin devices; otherwise, they are unimplemented and read as ‘0’. Reset values are
shown for 80-pin devices.
8:
9:
These bits are only available in select oscillator modes (FOSC2 Configuration bit = 0); otherwise, they are unimplemented.
The PMADDRH/PMDOUT1H and PMADDRL/PMDOUT1L register pairs share the physical registers and addresses, but have different
functions determined by the module’s operating mode. See Section 11.1.2 “Data Registers” for more information.
DS39778D-page 80
© 2009 Microchip Technology Inc.
PIC18F87J11 FAMILY
TABLE 5-5:
REGISTER FILE SUMMARY (PIC18F87J11 FAMILY) (CONTINUED)
Details
on
Page:
Value on
POR, BOR
File Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
CCPR4H
CCPR4L
Capture/Compare/PWM Register 4 High Byte
Capture/Compare/PWM Register 4 Low Byte
xxxx xxxx 61, 198
xxxx xxxx 61, 198
CCP4CON
CCPR5H
CCPR5L
—
—
DC4B1
DC4B0
CCP4M3
CCP5M3
CCP4M2
CCP5M2
CCP4M1
CCP5M1
CCP4M0 --00 0000 61, 198
xxxx xxxx 61, 198
Capture/Compare/PWM Register 5 High Byte
Capture/Compare/PWM Register 5 Low Byte
xxxx xxxx 61, 198
CCP5CON
SSP2BUF
—
—
DC5B1
DC5B0
CCP5M0 --00 0000 61, 198
MSSP2 Receive Buffer/Transmit Register
xxxx xxxx 61, 224,
233
SSP2ADD/
SSP2MSK(5)
MSSP2 Address Register (I2C™ Slave mode), MSSP2 Baud Rate Reload Register (I2C Master mode)
0000 0000 61, 233
0000 0000 61, 240
MSK7
SMP
MSK6
CKE
MSK5
D/A
MSK4
P
MSK3
S
MSK2
R/W
MSK1
UA
MSK0
BF
SSP2STAT
SSP2CON1
SSP2CON2
0000 0000 61, 224,
234
WCOL
SSPOV
SSPEN
CKP
SSPM3
SSPM2
SSPM1
SSPM0
0000 0000 61, 225,
235
GCEN
GCEN
—
ACKSTAT
ACKDT
ACKEN
RCEN
PEN
RSEN/
SEN
SEN
0000 0000 61, 236,
270
ACKSTAT ADMSK5(6) ADMSK4(6) ADMSK3(6) ADMSK2(6) ADMSK1(6)
CMSTAT
—
—
—
—
—
COUT2
COUT1
---- --11 61, 305
0000 0000 62, 160
0000 0000 62, 163
0000 0000 62, 160
0000 0000 62, 160
0000 0000 62, 160
0000 0000 62, 160
PMADDRH /
CS2
CS1
Parallel Master Port Address High Byte
PMDOUT1H(9) Parallel Port Out Data High Byte (Buffer 1)
PMADDRL/ Parallel Master Port Address Low Byte
PMDOUT1L(9) Parallel Port Out Data Low Byte (Buffer 0)
PMDIN1H
PMDIN1L
PMCONH
PMCONL
PMMODEH
PMMODEL
PMDOUT2H
PMDOUT2L
PMDIN2H
PMDIN2L
PMEH
Parallel Port In Data High Byte (Buffer 1)
Parallel Port In Data Low Byte (Buffer 0)
PMPEN
CSF1
—
PSIDL
ALP
ADRMUX1 ADRMUX0
PTBEEN
BEP
PTWREN
WRSP
PTRDEN 0-00 0000 62, 154
CSF0
CS2P
INCM1
WAITM2
CS1P
INCM0
WAITM1
RDSP
0000 0000 62, 155
0000 0000 62, 156
BUSY
IRQM1
WAITB0
IRQM0
WAITM3
MODE16
WAITM0
MODE1
WAITE1
MODE0
WAITB1
WAITE0 0000 0000 62, 157
0000 0000 62, 160
Parallel Port Out Data High Byte (Buffer 3)
Parallel Port Out Data Low Byte (Buffer 2)
Parallel Port In Data High Byte (Buffer 3)
Parallel Port In Data Low Byte (Buffer 2)
0000 0000 62, 160
0000 0000 62, 160
0000 0000 62, 160
PTEN15
PTEN7
IBF
PTEN14
PTEN6
IBOV
PTEN13
PTEN5
—
PTEN12
PTEN4
—
PTEN11
PTEN3
IB3F
PTEN10
PTEN2
IB2F
PTEN9
PTEN1
IB1F
PTEN8
PTEN0
IB0F
0000 0000 62, 157
0000 0000 62, 158
00-- 0000 62, 158
10-- 1111 62, 159
PMEL
PMSTATH
PMSTATL
OBE
OBUF
—
—
OB3E
OB2E
OB1E
OB0E
Legend:
x= unknown, u= unchanged, -= unimplemented, q= value depends on condition. Bold indicates shared access SFRs.
Bit 21 of the PC is only available in Serial Programming modes.
Note 1:
2:
3:
4:
5:
6:
Default (legacy) SFR at this address, available when WDTCON<4> = 0.
Configuration SFR, overlaps with default SFR at this address; available only when WDTCON<4> = 1.
Reset value is ‘0’ when Two-Speed Start-up is enabled and ‘1’ if disabled.
The SSPxMSK registers are only accessible when SSPxCON2<3:0> = 1001.
Alternate names and definitions for these bits when the MSSP modules are operating in I2C™ Slave mode. See Section 19.4.3.2
“Address Masking Modes” for details
7:
These bits and/or registers are only available in 80-pin devices; otherwise, they are unimplemented and read as ‘0’. Reset values are
shown for 80-pin devices.
8:
9:
These bits are only available in select oscillator modes (FOSC2 Configuration bit = 0); otherwise, they are unimplemented.
The PMADDRH/PMDOUT1H and PMADDRL/PMDOUT1L register pairs share the physical registers and addresses, but have different
functions determined by the module’s operating mode. See Section 11.1.2 “Data Registers” for more information.
© 2009 Microchip Technology Inc.
DS39778D-page 81
PIC18F87J11 FAMILY
recommended, therefore, that only BCF, BSF, SWAPF,
MOVFF and MOVWF instructions are used to alter the
STATUS register because these instructions do not
affect the Z, C, DC, OV or N bits in the STATUS
register.
5.3.5
STATUS REGISTER
The STATUS register, shown in Register 5-4, contains
the arithmetic status of the ALU. The STATUS register
can be the operand for any instruction, as with any
other register. If the STATUS register is the destination
for an instruction that affects the Z, DC, C, OV or N bits,
then the write to these five bits is disabled.
For other instructions not affecting any Status bits, see
the instruction set summaries in Table 25-2 and
Table 25-3.
These bits are set or cleared according to the device
logic. Therefore, the result of an instruction with the
STATUS register as destination may be different than
intended. For example, CLRF STATUSwill set the Z bit
but leave the other bits unchanged. The STATUS
register then reads back as ‘000u u1uu’. It is
Note: The C and DC bits operate as a borrow and
digit borrow bit respectively, in subtraction.
REGISTER 5-4:
STATUS REGISTER
U-0
—
U-0
U-0
—
R/W-x
N
R/W-x
OV
R/W-x
Z
R/W-x
DC(1)
R/W-x
C(2)
—
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7-5
bit 4
Unimplemented: Read as ‘0’
N: Negative bit
This bit is used for signed arithmetic (2’s complement). It indicates whether the result was
negative (ALU MSB = 1).
1= Result was negative
0= Result was positive
bit 3
OV: Overflow bit
This bit is used for signed arithmetic (2’s complement). It indicates an overflow of the
7-bit magnitude which causes the sign bit (bit 7) to change state.
1= Overflow occurred for signed arithmetic (in this arithmetic operation)
0= No overflow occurred
bit 2
bit 1
Z: Zero bit
1= The result of an arithmetic or logic operation is zero
0= The result of an arithmetic or logic operation is not zero
DC: Digit carry/borrow bit(1)
For ADDWF, ADDLW, SUBLWand SUBWFinstructions:
1= A carry-out from the 4th low-order bit of the result occurred
0= No carry-out from the 4th low-order bit of the result
bit 0
C: Carry/borrow bit(2)
For ADDWF, ADDLW, SUBLWand SUBWFinstructions:
1= A carry-out from the Most Significant bit of the result occurred
0= No carry-out from the Most Significant bit of the result occurred
Note 1: For borrow, the polarity is reversed. A subtraction is executed by adding the 2’s complement of the second
operand. For rotate (RRF, RLF) instructions, this bit is loaded with either bit 4 or bit 3 of the source register.
2: For borrow, the polarity is reversed. A subtraction is executed by adding the 2’s complement of the second
operand. For rotate (RRF, RLF) instructions, this bit is loaded with either the high or low-order bit of the
source register.
DS39778D-page 82
© 2009 Microchip Technology Inc.
PIC18F87J11 FAMILY
Purpose Register File”), or a location in the Access
Bank (Section 5.3.2 “Access Bank”) as the data
source for the instruction.
5.4
Data Addressing Modes
Note:
The execution of some instructions in the
core PIC18 instruction set are changed
when the PIC18 extended instruction set is
enabled. See Section 5.6 “Data Memory
and the Extended Instruction Set” for
more information.
The Access RAM bit ‘a’ determines how the address is
interpreted. When ‘a’ is ‘1’, the contents of the BSR
(Section 5.3.1 “Bank Select Register”) are used with
the address to determine the complete 12-bit address
of the register. When ‘a’ is ‘0’, the address is interpreted
as being a register in the Access Bank. Addressing that
uses the Access RAM is sometimes also known as
Direct Forced Addressing mode.
While the program memory can be addressed in only
one way – through the program counter – information
in the data memory space can be addressed in several
ways. For most instructions, the addressing mode is
fixed. Other instructions may use up to three modes,
depending on which operands are used and whether or
not the extended instruction set is enabled.
A few instructions, such as MOVFF, include the entire
12-bit address (either source or destination) in their
opcodes. In these cases, the BSR is ignored entirely.
The destination of the operation’s results is determined
by the destination bit ‘d’. When ‘d’ is ‘1’, the results are
stored back in the source register, overwriting its origi-
nal contents. When ‘d’ is ‘0’, the results are stored in
the W register. Instructions without the ‘d’ argument
have a destination that is implicit in the instruction; their
destination is either the target register being operated
on or the W register.
The addressing modes are:
• Inherent
• Literal
• Direct
• Indirect
An additional addressing mode, Indexed Literal Offset,
is available when the extended instruction set is
enabled (XINST Configuration bit = 1). Its operation is
discussed in greater detail in Section 5.6.1 “Indexed
Addressing with Literal Offset”.
5.4.3
INDIRECT ADDRESSING
Indirect Addressing allows the user to access a location
in data memory without giving a fixed address in the
instruction. This is done by using File Select Registers
(FSRs) as pointers to the locations to be read or written
to. Since the FSRs are themselves located in RAM as
Special Function Registers, they can also be directly
manipulated under program control. This makes FSRs
very useful in implementing data structures such as
tables and arrays in data memory.
5.4.1
INHERENT AND LITERAL
ADDRESSING
Many PIC18 control instructions do not need any
argument at all; they either perform an operation that
globally affects the device, or they operate implicitly on
one register. This addressing mode is known as
Inherent Addressing. Examples include SLEEP, RESET
and DAW.
The registers for Indirect Addressing are also
implemented with Indirect File Operands (INDFs) that
permit automatic manipulation of the pointer value with
auto-incrementing, auto-decrementing or offsetting
with another value. This allows for efficient code using
loops, such as the example of clearing an entire RAM
bank in Example 5-5. It also enables users to perform
Indexed Addressing and other Stack Pointer
operations for program memory in data memory.
Other instructions work in a similar way, but require an
additional explicit argument in the opcode. This is
known as Literal Addressing mode, because they
require some literal value as an argument. Examples
include ADDLWand MOVLW, which respectively, add or
move a literal value to the W register. Other examples
include CALL and GOTO, which include a 20-bit
program memory address.
EXAMPLE 5-5:
HOW TO CLEAR RAM
(BANK 1) USING
5.4.2
DIRECT ADDRESSING
INDIRECT ADDRESSING
Direct Addressing specifies all or part of the source
and/or destination address of the operation within the
opcode itself. The options are specified by the
arguments accompanying the instruction.
LFSR
CLRF
FSR0, 100h
;
NEXT
POSTINC0
; Clear INDF
; register then
; inc pointer
; All done with
; Bank1?
In the core PIC18 instruction set, bit-oriented and
byte-oriented instructions use some version of Direct
Addressing by default. All of these instructions include
some 8-bit Literal Address as their Least Significant
Byte. This address specifies either a register address in
one of the banks of data RAM (Section 5.3.3 “General
BTFSS
BRA
FSR0H, 1
NEXT
; NO, clear next
; YES, continue
CONTINUE
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the SFR space but are not physically implemented.
Reading or writing to a particular INDF register actually
accesses its corresponding FSR register pair. A read
from INDF1, for example, reads the data at the address
indicated by FSR1H:FSR1L. Instructions that use the
INDF registers as operands actually use the contents
of their corresponding FSR as a pointer to the instruc-
tion’s target. The INDF operand is just a convenient
way of using the pointer.
5.4.3.1
FSR Registers and the
INDF Operand
At the core of Indirect Addressing are three sets of
registers: FSR0, FSR1 and FSR2. Each represents a
pair of 8-bit registers, FSRnH and FSRnL. The four
upper bits of the FSRnH register are not used, so each
FSR pair holds a 12-bit value. This represents a value
that can address the entire range of the data memory
in a linear fashion. The FSR register pairs, then, serve
as pointers to data memory locations.
Because Indirect Addressing uses a full 12-bit address,
data RAM banking is not necessary. Thus, the current
contents of the BSR and the Access RAM bit have no
effect on determining the target address.
Indirect Addressing is accomplished with a set of Indi-
rect File Operands, INDF0 through INDF2. These can
be thought of as “virtual” registers: they are mapped in
FIGURE 5-9:
INDIRECT ADDRESSING
000h
Using an instruction with one of the
Indirect Addressing registers as the
operand....
Bank 0
Bank 1
ADDWF, INDF1, 1
100h
200h
300h
Bank 2
FSR1H:FSR1L
...uses the 12-bit address stored in
the FSR pair associated with that
register....
7
0
7
0
Bank 3
through
Bank 13
x x x x 1 1 1 1
1 1 0 0 1 1 0 0
...to determine the data memory
location to be used in that operation.
E00h
In this case, the FSR1 pair contains
FCCh. This means the contents of
location FCCh will be added to that
of the W register and stored back in
FCCh.
Bank 14
Bank 15
F00h
FFFh
Data Memory
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5.4.3.2
FSR Registers and POSTINC,
5.4.3.3
Operations by FSRs on FSRs
POSTDEC, PREINC and PLUSW
Indirect Addressing operations that target other FSRs
or virtual registers represent special cases. For exam-
ple, using an FSR to point to one of the virtual registers
will not result in successful operations. As a specific
case, assume that FSR0H:FSR0L contains FE7h, the
address of INDF1. Attempts to read the value of the
INDF1, using INDF0 as an operand, will return 00h.
Attempts to write to INDF1, using INDF0 as the
operand, will result in a NOP.
In addition to the INDF operand, each FSR register pair
also has four additional indirect operands. Like INDF,
these are “virtual” registers that cannot be indirectly
read or written to. Accessing these registers actually
accesses the associated FSR register pair, but also
performs a specific action on its stored value. They are:
• POSTDEC: accesses the FSR value, then
automatically decrements it by ‘1’ afterwards
On the other hand, using the virtual registers to write to
an FSR pair may not occur as planned. In these cases,
the value will be written to the FSR pair but without any
incrementing or decrementing. Thus, writing to INDF2
or POSTDEC2 will write the same value to the
FSR2H:FSR2L.
• POSTINC: accesses the FSR value, then
automatically increments it by ‘1’ afterwards
• PREINC: increments the FSR value by ‘1’, then
uses it in the operation
• PLUSW: adds the signed value of the W register
(range of -127 to 128) to that of the FSR and uses
the new value in the operation
Since the FSRs are physical registers mapped in the
SFR space, they can be manipulated through all direct
operations. Users should proceed cautiously when
working on these registers, particularly if their code
uses Indirect Addressing.
In this context, accessing an INDF register uses the
value in the FSR registers without changing them.
Similarly, accessing a PLUSW register gives the FSR
value offset by the value in the W register; neither value
is actually changed in the operation. Accessing the
other virtual registers changes the value of the FSR
registers.
Similarly, operations by Indirect Addressing are gener-
ally permitted on all other SFRs. Users should exercise
the appropriate caution that they do not inadvertently
change settings that might affect the operation of the
device.
Operations on the FSRs with POSTDEC, POSTINC
and PREINC affect the entire register pair; that is, roll-
overs of the FSRnL register from FFh to 00h carry over
to the FSRnH register. On the other hand, results of
these operations do not change the value of any flags
in the STATUS register (e.g., Z, N, OV, etc.).
The PLUSW register can be used to implement a form
of Indexed Addressing in the data memory space. By
manipulating the value in the W register, users can
reach addresses that are fixed offsets from pointer
addresses. In some applications, this can be used to
implement some powerful program control structure,
such as software stacks, inside of data memory.
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When using the extended instruction set, this
addressing mode requires the following:
5.5
Program Memory and the
Extended Instruction Set
• The use of the Access Bank is forced (‘a’ = 0);
and
The operation of program memory is unaffected by the
use of the extended instruction set.
• The file address argument is less than or equal to
5Fh.
Enabling the extended instruction set adds five
additional two-word commands to the existing PIC18
instruction set: ADDFSR, CALLW, MOVSF, MOVSS and
SUBFSR. These instructions are executed as described
in Section 5.2.4 “Two-Word Instructions”.
Under these conditions, the file address of the
instruction is not interpreted as the lower byte of an
address (used with the BSR in Direct Addressing) or as
an 8-bit address in the Access Bank. Instead, the value
is interpreted as an offset value to an Address Pointer
specified by FSR2. The offset and the contents of
FSR2 are added to obtain the target address of the
operation.
5.6
Data Memory and the Extended
Instruction Set
Enabling the PIC18 extended instruction set (XINST
Configuration bit = 1) significantly changes certain
aspects of data memory and its addressing. Specifi-
cally, the use of the Access Bank for many of the core
PIC18 instructions is different. This is due to the intro-
duction of a new addressing mode for the data memory
space. This mode also alters the behavior of Indirect
Addressing using FSR2 and its associated operands.
5.6.2
INSTRUCTIONS AFFECTED BY
INDEXED LITERAL OFFSET MODE
Any of the core PIC18 instructions that can use Direct
Addressing are potentially affected by the Indexed
Literal Offset Addressing mode. This includes all
byte-oriented and bit-oriented instructions, or almost
one-half of the standard PIC18 instruction set. Instruc-
tions that only use Inherent or Literal Addressing
modes are unaffected.
What does not change is just as important. The size of
the data memory space is unchanged, as well as its
linear addressing. The SFR map remains the same.
Core PIC18 instructions can still operate in both Direct
and Indirect Addressing mode; inherent and literal
instructions do not change at all. Indirect Addressing
with FSR0 and FSR1 also remains unchanged.
Additionally, byte-oriented and bit-oriented instructions
are not affected if they use the Access Bank (Access
RAM bit is ‘1’) or include a file address of 60h or above.
Instructions meeting these criteria will continue to
execute as before. A comparison of the different pos-
sible addressing modes when the extended instruction
set is enabled is shown in Figure 5-10.
5.6.1
INDEXED ADDRESSING WITH
LITERAL OFFSET
Enabling the PIC18 extended instruction set changes
the behavior of Indirect Addressing using the FSR2
register pair and its associated file operands. Under the
proper conditions, instructions that use the Access
Bank – that is, most bit-oriented and byte-oriented
instructions – can invoke a form of Indexed Addressing
using an offset specified in the instruction. This special
addressing mode is known as Indexed Addressing with
Literal Offset, or Indexed Literal Offset mode.
Those who desire to use byte-oriented or bit-oriented
instructions in the Indexed Literal Offset mode should
note the changes to assembler syntax for this mode.
This is described in more detail in Section 25.2.1
“Extended Instruction Syntax”.
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FIGURE 5-10:
COMPARING ADDRESSING OPTIONS FOR BIT-ORIENTED AND
BYTE-ORIENTED INSTRUCTIONS (EXTENDED INSTRUCTION SET ENABLED)
EXAMPLE INSTRUCTION: ADDWF, f, d, a (Opcode: 0010 01da ffff ffff)
000h
When a = 0and f ≥ 60h:
The instruction executes in
Direct Forced mode. ‘f’ is
interpreted as a location in the
Access RAM between 060h
and FFFh. This is the same as
locations F60h to FFFh
(Bank 15) of data memory.
060h
100h
Bank 0
00h
60h
Bank 1
through
Bank 14
Valid range
for ‘f’
Locations below 060h are not
available in this addressing
mode.
FFh
F00h
Access RAM
Bank 15
SFRs
F60h
FFFh
Data Memory
When a = 0and f ≤ 5Fh:
000h
060h
100h
Bank 0
The instruction executes in
Indexed Literal Offset mode. ‘f’
is interpreted as an offset to the
address value in FSR2. The
two are added together to
obtain the address of the target
register for the instruction. The
address can be anywhere in
the data memory space.
001001da ffffffff
Bank 1
through
Bank 14
FSR2H
FSR2L
F00h
F60h
Note that in this mode, the
correct syntax is now:
Bank 15
SFRs
ADDWF [k], d
where ‘k’ is the same as ‘f’.
FFFh
Data Memory
BSR
000h
060h
100h
00000000
When a = 1(all values of f):
Bank 0
The instruction executes in
Direct mode (also known as
Direct Long mode). ‘f’ is
interpreted as a location in
one of the 16 banks of the data
memory space. The bank is
designated by the Bank Select
Register (BSR). The address
can be in any implemented
bank in the data memory
space.
001001da ffffffff
Bank 1
through
Bank 14
F00h
F60h
Bank 15
SFRs
FFFh
Data Memory
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Remapping of the Access Bank applies only to opera-
tions using the Indexed Literal Offset mode. Operations
that use the BSR (Access RAM bit is ‘1’) will continue
to use Direct Addressing as before. Any Indirect or
Indexed Addressing operation that explicitly uses any
of the indirect file operands (including FSR2) will con-
tinue to operate as standard Indirect Addressing. Any
instruction that uses the Access Bank, but includes a
register address of greater than 05Fh, will use Direct
Addressing and the normal Access Bank map.
5.6.3
MAPPING THE ACCESS BANK IN
INDEXED LITERAL OFFSET MODE
The use of Indexed Literal Offset Addressing mode
effectively changes how the lower part of Access RAM
(00h to 5Fh) is mapped. Rather than containing just the
contents of the bottom part of Bank 0, this mode maps
the contents from Bank 0 and a user-defined “window”
that can be located anywhere in the data memory
space. The value of FSR2 establishes the lower bound-
ary of the addresses mapped into the window, while the
upper boundary is defined by FSR2 plus 95 (5Fh).
Addresses in the Access RAM above 5Fh are mapped
as previously described (see Section 5.3.2 “Access
Bank”). An example of Access Bank remapping in this
addressing mode is shown in Figure 5-11.
5.6.4
BSR IN INDEXED LITERAL
OFFSET MODE
Although the Access Bank is remapped when the
extended instruction set is enabled, the operation of the
BSR remains unchanged. Direct Addressing, using the
BSR to select the data memory bank, operates in the
same manner as previously described.
FIGURE 5-11:
REMAPPING THE ACCESS BANK WITH INDEXED LITERAL
OFFSET ADDRESSING
Example Situation:
ADDWF f, d, a
000h
Not Accessible
05Fh
FSR2H:FSR2L = 120h
Bank 0
Locations in the region
from the FSR2 Pointer
(120h) to the pointer plus
05Fh (17Fh) are mapped
to the bottom of the
Access RAM (000h-05Fh).
100h
120h
17Fh
Window
Bank 1
00h
Bank 1 “Window”
200h
5Fh
60h
Special Function Registers
at F60h through FFFh are
mapped to 60h through
FFh, as usual.
Bank 2
through
Bank 14
SFRs
Bank 0 addresses below
5Fh are not available in
this mode. They can still
be addressed by using the
BSR.
FFh
Access Bank
F00h
Bank 15
SFRs
F60h
FFFh
Data Memory
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6.1
Table Reads and Table Writes
6.0
FLASH PROGRAM MEMORY
In order to read and write program memory, there are
two operations that allow the processor to move bytes
between the program memory space and the data RAM:
The Flash program memory is readable, writable and
erasable during normal operation over the entire VDD
range.
• Table Read (TBLRD)
• Table Write (TBLWT)
A read from program memory is executed on one byte
at a time. A write to program memory is executed on
blocks of 64 bytes at a time or two bytes at a time. Pro-
gram memory is erased in blocks of 1024 bytes at a
time. A bulk erase operation may not be issued from
user code.
The program memory space is 16 bits wide, while the
data RAM space is 8 bits wide. Table reads and table
writes move data between these two memory spaces
through an 8-bit register (TABLAT).
Writing or erasing program memory will cease
instruction fetches until the operation is complete. The
program memory cannot be accessed during the write
or erase, therefore, code cannot execute. An internal
programming timer terminates program memory writes
and erases.
Table read operations retrieve data from program
memory and place it into the data RAM space.
Figure 6-1 shows the operation of a table read with
program memory and data RAM.
Table write operations store data from the data memory
space into holding registers in program memory. The
procedure to write the contents of the holding registers
into program memory is detailed in Section 6.5 “Writing
to Flash Program Memory”. Figure 6-2 shows the
operation of a table write with program memory and data
RAM.
A value written to program memory does not need to be
a valid instruction. Executing a program memory
location that forms an invalid instruction results in a
NOP.
Table operations work with byte entities. A table block
containing data, rather than program instructions, is not
required to be word-aligned. Therefore, a table block can
start and end at any byte address. If a table write is being
used to write executable code into program memory,
program instructions will need to be word-aligned.
FIGURE 6-1:
TABLE READ OPERATION
Instruction: TBLRD*
Program Memory
(1)
Table Pointer
Table Latch (8-bit)
TABLAT
TBLPTRU TBLPTRH TBLPTRL
Program Memory
(TBLPTR)
Note 1: Table Pointer register points to a byte in program memory.
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FIGURE 6-2:
TABLE WRITE OPERATION
Instruction: TBLWT*
Program Memory
Holding Registers
(1)
Table Pointer
Table Latch (8-bit)
TABLAT
TBLPTRU TBLPTRH TBLPTRL
Program Memory
(TBLPTR)
Note 1: Table Pointer actually points to one of 64 holding registers, the address of which is determined by
TBLPTRL<5:0>. The process for physically writing data to the program memory array is discussed in
Section 6.5 “Writing to Flash Program Memory”.
The FREE bit, when set, will allow a program memory
erase operation. When FREE is set, the erase
operation is initiated on the next WR command. When
FREE is clear, only writes are enabled.
6.2
Control Registers
Several control registers are used in conjunction with
the TBLRDand TBLWTinstructions. These include the:
• EECON1 register
• EECON2 register
• TABLAT register
• TBLPTR registers
The WREN bit, when set, will allow a write operation.
On power-up, the WREN bit is clear. The WRERR bit is
set in hardware when the WR bit is set and cleared
when the internal programming timer expires and the
write operation is complete.
6.2.1
EECON1 AND EECON2 REGISTERS
Note:
During normal operation, the WRERR is
read as ‘1’. This can indicate that a write
operation was prematurely terminated by
The EECON1 register (Register 6-1) is the control
register for memory accesses. The EECON2 register is
not a physical register; it is used exclusively in the
memory write and erase sequences. Reading
EECON2 will read all ‘0’s.
a
Reset, or
a write operation was
attempted improperly.
The WR control bit initiates write operations. The bit
cannot be cleared, only set, in software. It is cleared in
hardware at the completion of the write operation.
The WPROG bit, when set, allows the user to program
a single word (two bytes) upon the execution of the WR
command. If this bit is cleared, the WR command
programs a block of 64 bytes.
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REGISTER 6-1:
EECON1: EEPROM CONTROL REGISTER 1
U-0
—
U-0
—
R/W-0
R/W-0
FREE
R/W-x
WRERR(1)
R/W-0
WREN
R/S-0
WR
U-0
—
WPROG
bit 7
bit 0
Legend:
S = Set-only bit (cannot be cleared in software)
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7-6
bit 5
Unimplemented: Read as ‘0’
WPROG: One Word-Wide Program bit
1= Program 2 bytes on the next WR command
0= Program 64 bytes on the next WR command
bit 4
bit 3
FREE: Flash Row Erase Enable bit
1= Erase the program memory row addressed by TBLPTR on the next WR command
(cleared by completion of erase operation)
0= Perform write only
WRERR: Flash Program Error Flag bit(1)
1= A write operation is prematurely terminated (any Reset during self-timed programming in normal
operation, or an improper write attempt)
0= The write operation completed
bit 2
bit 1
WREN: Flash Program Write Enable bit
1= Allows write cycles to Flash program memory
0= Inhibits write cycles to Flash program memory
WR: Write Control bit
1= Initiates a program memory erase cycle or write cycle
(The operation is self-timed and the bit is cleared by hardware once write is complete. The WR bit
can only be set (not cleared) in software.)
0= Write cycle is complete
bit 0
Unimplemented: Read as ‘0’
Note 1: When a WRERR occurs, the EEPGD and CFGS bits are not cleared. This allows tracing of the error
condition.
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6.2.2
TABLE LATCH REGISTER (TABLAT)
6.2.4
TABLE POINTER BOUNDARIES
The Table Latch (TABLAT) is an 8-bit register mapped
into the SFR space. The Table Latch register is used to
hold 8-bit data during data transfers between program
memory and data RAM.
TBLPTR is used in reads, writes and erases of the
Flash program memory.
When a TBLRDis executed, all 22 bits of the TBLPTR
determine which byte is read from program memory
into TABLAT.
6.2.3
TABLE POINTER REGISTER
(TBLPTR)
When a TBLWT is executed, the seven LSbs of the
Table Pointer register (TBLPTR<6:0>) determine which
of the 64 program memory holding registers is written
to. When the timed write to program memory begins
(via the WR bit), the 12 MSbs of the TBLPTR
(TBLPTR<21:10>) determine which program memory
block of 1024 bytes is written to. For more detail, see
Section 6.5 “Writing to Flash Program Memory”.
The Table Pointer (TBLPTR) register addresses a byte
within the program memory. The TBLPTR is comprised
of three SFR registers: Table Pointer Upper Byte, Table
Pointer High Byte and Table Pointer Low Byte
(TBLPTRU:TBLPTRH:TBLPTRL). These three regis-
ters join to form a 22-bit wide pointer. The low-order
21 bits allow the device to address up to 2 Mbytes of
program memory space. The 22nd bit allows access to
the device ID, the user ID and the Configuration bits.
When an erase of program memory is executed, the
12 MSbs of the Table Pointer register point to the
1024-byte block that will be erased. The Least
Significant bits are ignored.
The Table Pointer register, TBLPTR, is used by the
TBLRDand TBLWTinstructions. These instructions can
update the TBLPTR in one of four ways based on the
table operation. These operations are shown in
Table 6-1. These operations on the TBLPTR only affect
the low-order 21 bits.
Figure 6-3 describes the relevant boundaries of
TBLPTR based on Flash program memory operations.
TABLE 6-1:
Example
TABLE POINTER OPERATIONS WITH TBLRDAND TBLWTINSTRUCTIONS
Operation on Table Pointer
TBLRD*
TBLWT*
TBLPTR is not modified
TBLRD*+
TBLWT*+
TBLPTR is incremented after the read/write
TBLPTR is decremented after the read/write
TBLPTR is incremented before the read/write
TBLRD*-
TBLWT*-
TBLRD+*
TBLWT+*
FIGURE 6-3:
TABLE POINTER BOUNDARIES BASED ON OPERATION
21
16 15
TBLPTRH
8
7
TBLPTRL
0
TBLPTRU
ERASE: TBLPTR<20:10>
TABLE WRITE: TBLPTR<20:6>
TABLE READ: TBLPTR<21:0>
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TBLPTR points to a byte address in program space.
Executing TBLRD places the byte pointed to into
TABLAT. In addition, TBLPTR can be modified
automatically for the next table read operation.
6.3
Reading the Flash Program
Memory
The TBLRD instruction is used to retrieve data from
program memory and places it into data RAM. Table
reads from program memory are performed one byte at
a time.
The internal program memory is typically organized by
words. The Least Significant bit of the address selects
between the high and low bytes of the word. Figure 6-4
shows the interface between the internal program
memory and the TABLAT.
FIGURE 6-4:
READS FROM FLASH PROGRAM MEMORY
Program Memory
(Even Byte Address)
(Odd Byte Address)
TBLPTR = xxxxx1
TBLPTR = xxxxx0
Instruction Register
TABLAT
Read Register
FETCH
TBLRD
(IR)
EXAMPLE 6-1:
READING A FLASH PROGRAM MEMORY WORD
MOVLW
CODE_ADDR_UPPER
TBLPTRU
CODE_ADDR_HIGH
TBLPTRH
CODE_ADDR_LOW
TBLPTRL
; Load TBLPTR with the base
; address of the word
MOVWF
MOVLW
MOVWF
MOVLW
MOVWF
READ_WORD
TBLRD*+
MOVF
MOVWF
TBLRD*+
MOVF
; read into TABLAT and increment
; get data
TABLAT, W
WORD_EVEN
; read into TABLAT and increment
; get data
TABLAT, W
WORD_ODD
MOVWF
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6.4.1
FLASH PROGRAM MEMORY
ERASE SEQUENCE
6.4
Erasing Flash Program Memory
The minimum erase block is 512 words or 1024 bytes.
Only through the use of an external programmer, or
through ICSP control, can larger blocks of program
memory be bulk erased. Word erase in the Flash array
is not supported.
The sequence of events for erasing a block of internal
program memory location is:
1. Load Table Pointer register with address of row
being erased.
When initiating an erase sequence from the micro-
controller itself, a block of 1024 bytes of program
memory is erased. The Most Significant 12 bits of the
TBLPTR<21:10> point to the block being erased.
TBLPTR<9:0> are ignored.
2. Set the WREN and FREE bits (EECON1<2,4>)
to enable the erase operation.
3. Disable interrupts.
4. Write 55h to EECON2.
5. Write 0AAh to EECON2.
The EECON1 register commands the erase operation.
The WREN bit must be set to enable write operations.
The FREE bit is set to select an erase operation. For
protection, the write initiate sequence for EECON2
must be used.
6. Set the WR bit. This will begin the row erase
cycle.
7. The CPU will stall for duration of the erase for
TIW (see parameter D133A).
8. Re-enable interrupts.
A long write is necessary for erasing the internal Flash.
Instruction execution is halted while in a long write
cycle. The long write will be terminated by the internal
programming timer.
EXAMPLE 6-2:
ERASING A FLASH PROGRAM MEMORY ROW
MOVLW
MOVWF
MOVLW
MOVWF
MOVLW
MOVWF
CODE_ADDR_UPPER
TBLPTRU
CODE_ADDR_HIGH
TBLPTRH
CODE_ADDR_LOW
TBLPTRL
; load TBLPTR with the base
; address of the memory block
ERASE_ROW
BSF
BCF
EECON1, FREE
INTCON, GIE
55h
EECON2
0AAh
EECON2
EECON1, WR
INTCON, GIE
; enable Row Erase operation
; disable interrupts
Required
Sequence
MOVLW
MOVWF
MOVLW
MOVWF
BSF
; write 55h
; write 0AAh
; start erase (CPU stall)
; re-enable interrupts
BSF
DS39778D-page 94
© 2009 Microchip Technology Inc.
PIC18F87J11 FAMILY
The on-chip timer controls the write time. The
write/erase voltages are generated by an on-chip
charge pump, rated to operate over the voltage range
of the device.
6.5
Writing to Flash Program Memory
The programming block is 32 words or 64 bytes.
Programming one word or two bytes at a time is also
supported.
Note 1: Unlike previous PIC18 Flash devices,
members of the PIC18F87J11 family do
not reset the holding registers after a
write occurs. The holding registers must
Table writes are used internally to load the holding
registers needed to program the Flash memory. There
are 64 holding registers used by the table writes for
programming.
be cleared or overwritten before
programming sequence.
a
Since the Table Latch (TABLAT) is only a single byte, the
TBLWTinstruction may need to be executed 64 times for
each programming operation (if WPROG = 0). All of the
table write operations will essentially be short writes
because only the holding registers are written. At the
end of updating the 64 holding registers, the EECON1
register must be written to in order to start the
programming operation with a long write.
2: To maintain the endurance of the program
memory cells, each Flash byte should not
be programmed more than one time
between erase operations. Before
attempting to modify the contents of the
target cell a second time, a row erase of
the target row, or a bulk erase of the entire
memory, must be performed.
The long write is necessary for programming the inter-
nal Flash. Instruction execution is halted while in a long
write cycle. The long write will be terminated by the
internal programming timer.
FIGURE 6-5:
TABLE WRITES TO FLASH PROGRAM MEMORY
TABLAT
Write Register
8
8
8
8
TBLPTR = xxxxx0
TBLPTR = xxxxx1
TBLPTR = xxxxx2
TBLPTR = xxxx3F
Holding Register
Holding Register
Holding Register
Holding Register
Program Memory
8. Disable interrupts.
6.5.1
FLASH PROGRAM MEMORY WRITE
SEQUENCE
9. Write 55h to EECON2.
10. Write 0AAh to EECON2.
The sequence of events for programming an internal
program memory location should be:
11. Set the WR bit. This will begin the write cycle.
12. The CPU will stall for duration of the write for TIW
(parameter D133A).
1. Read 1024 bytes into RAM.
2. Update data values in RAM as necessary.
13. Re-enable interrupts.
3. Load Table Pointer register with address being
erased.
14. Repeat steps 6 through 13 until all 1024 bytes
are written to program memory.
4. Execute the row erase procedure.
15. Verify the memory (table read).
5. Load Table Pointer register with address of first
byte being written, minus 1.
An example of the required code is shown in
Example 6-3 on the following page.
6. Write the 64 bytes into the holding registers with
auto-increment.
Note:
Before setting the WR bit, the Table
Pointer address needs to be within the
intended address range of the 64 bytes in
the holding register.
7. Set the WREN bit (EECON1<2>) to enable byte
writes.
© 2009 Microchip Technology Inc.
DS39778D-page 95
PIC18F87J11 FAMILY
EXAMPLE 6-3:
WRITING TO FLASH PROGRAM MEMORY
MOVLW
MOVWF
MOVLW
MOVWF
MOVLW
MOVWF
CODE_ADDR_UPPER
TBLPTRU
CODE_ADDR_HIGH
TBLPTRH
CODE_ADDR_LOW
TBLPTRL
; Load TBLPTR with the base address
; of the memory block, minus 1
ERASE_BLOCK
BSF
BSF
BCF
EECON1, WREN
EECON1, FREE
INTCON, GIE
55h
EECON2
0AAh
; enable write to memory
; enable Row Erase operation
; disable interrupts
MOVLW
MOVWF
MOVLW
MOVWF
BSF
BSF
MOVLW
MOVWF
; write 55h
EECON2
; write 0AAh
; start erase (CPU stall)
; re-enable interrupts
EECON1, WR
INTCON, GIE
D'16'
WRITE_COUNTER
; Need to write 16 blocks of 64 to write
; one erase block of 1024
RESTART_BUFFER
MOVLW
MOVWF
MOVLW
MOVWF
MOVLW
MOVWF
D'64'
COUNTER
BUFFER_ADDR_HIGH
FSR0H
BUFFER_ADDR_LOW
FSR0L
; point to buffer
FILL_BUFFER
...
; read the new data from I2C, SPI,
; PSP, USART, etc.
WRITE_BUFFER
MOVLW
MOVWF
D’64
COUNTER
; number of bytes in holding register
WRITE_BYTE_TO_HREGS
MOVFF
MOVWF
TBLWT+*
POSTINC0, WREG
TABLAT
; get low byte of buffer data
; present data to table latch
; write data, perform a short write
; to internal TBLWT holding register.
; loop until buffers are full
DECFSZ COUNTER
BRA WRITE_BYTE_TO_HREGS
PROGRAM_MEMORY
BSF
BCF
EECON1, WREN
INTCON, GIE
55h
EECON2
0AAh
; enable write to memory
; disable interrupts
MOVLW
MOVWF
MOVLW
MOVWF
BSF
Required
Sequence
; write 55h
EECON2
; write 0AAh
EECON1, WR
INTCON, GIE
EECON1, WREN
; start program (CPU stall)
; re-enable interrupts
; disable write to memory
BSF
BCF
DECFSZ WRITE_COUNTER
BRA RESTART_BUFFER
; done with one write cycle
; if not done replacing the erase block
DS39778D-page 96
© 2009 Microchip Technology Inc.
PIC18F87J11 FAMILY
3. Set the WREN bit (EECON1<2>) to enable byte
writes.
6.5.2
FLASH PROGRAM MEMORY WRITE
SEQUENCE (WORD
4. Disable interrupts.
PROGRAMMING).
5. Write 55h to EECON2.
The PIC18F87J11 Family of devices have a feature
that allows programming a single word (two bytes).
This feature is enable when the WPROG bit is set. If the
memory location is already erased, the following
sequence is required to enable this feature:
6. Write 0AAh to EECON2.
7. Set the WR bit. This will begin the write cycle.
8. The CPU will stall for duration of the write for TIW
(see parameter D133A).
1. Load the Table Pointer register with the address
of the data to be written
9. Re-enable interrupts.
2. Write the 2 bytes into the holding registers and
perform a table write
EXAMPLE 6-4:
SINGLE-WORD WRITE TO FLASH PROGRAM MEMORY
MOVLW
MOVWF
MOVLW
MOVWF
MOVLW
MOVWF
CODE_ADDR_UPPER
TBLPTRU
CODE_ADDR_HIGH
TBLPTRH
CODE_ADDR_LOW
TBLPTRL
; Load TBLPTR with the base address
MOVLW
DATA0
MOVWF
TABLAT
TBLWT*+
MOVLW
DATA1
MOVWF
TABLAT
TBLWT*
PROGRAM_MEMORY
BSF
BSF
BCF
MOVLW
MOVWF
MOVLW
MOVWF
BSF
EECON1, WPROG
EECON1, WREN
INTCON, GIE
55h
EECON2
0AAh
; enable single word write
; enable write to memory
; disable interrupts
Required
Sequence
; write 55h
EECON2
; write 0AAh
EECON1, WR
INTCON, GIE
EECON1, WPROG
EECON1, WREN
; start program (CPU stall)
; re-enable interrupts
; disable single word write
; disable write to memory
BSF
BCF
BCF
© 2009 Microchip Technology Inc.
DS39778D-page 97
PIC18F87J11 FAMILY
6.5.3
WRITE VERIFY
6.6
Flash Program Operation During
Code Protection
Depending on the application, good programming
practice may dictate that the value written to the
memory should be verified against the original value.
This should be used in applications where excessive
writes can stress bits near the specification limit.
See Section 24.6 “Program Verification and Code
Protection” for details on code protection of Flash
program memory.
6.5.4
UNEXPECTED TERMINATION OF
WRITE OPERATION
If a write is terminated by an unplanned event, such as
loss of power or an unexpected Reset, the memory
location just programmed should be verified and repro-
grammed if needed. If the write operation is interrupted
by a MCLR Reset or a WDT time-out Reset during
normal operation, the user can check the WRERR bit
and rewrite the location(s) as needed.
TABLE 6-2:
Name
REGISTERS ASSOCIATED WITH PROGRAM FLASH MEMORY
Reset
Values on
Page:
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
TBLPTRU
—
—
bit 21
Program Memory Table Pointer Upper Byte
(TBLPTR<20:16>)
57
TBPLTRH Program Memory Table Pointer High Byte (TBLPTR<15:8>)
TBLPTRL Program Memory Table Pointer Low Byte (TBLPTR<7:0>)
57
57
57
57
59
59
TABLAT
INTCON
Program Memory Table Latch
GIE/GIEH PEIE/GIEL TMR0IE
INT0IE
RBIE
TMR0IF
WREN
INT0IF
WR
RBIF
—
EECON2 Program Memory Control Register 2 (not a physical register)
EECON1 WPROG FREE WRERR
—
—
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used during Flash program memory access.
DS39778D-page 98
© 2009 Microchip Technology Inc.
PIC18F87J11 FAMILY
The bus is implemented with 28 pins, multiplexed
across four I/O ports. Three ports (PORTD, PORTE
and PORTH) are multiplexed with the address/data bus
for a total of 20 available lines, while PORTJ is
multiplexed with the bus control signals.
7.0
EXTERNAL MEMORY BUS
Note:
The external memory bus is not
implemented on 64-pin devices.
The External Memory Bus (EMB) allows the device to
access external memory devices (such as Flash,
EPROM, SRAM, etc.) as program or data memory. It
supports both 8 and 16-Bit Data Width modes and
three address widths of up to 20 bits.
A list of the pins and their functions is provided in
Table 7-1.
TABLE 7-1:
Name
PIC18F87J11 FAMILY EXTERNAL BUS – I/O PORT FUNCTIONS
Port
Bit
External Memory Bus Function
RD0/AD0
RD1/AD1
RD2/AD2
RD3/AD3
RD4/AD4
RD5/AD5
RD6/AD6
RD7/AD7
RE0/AD8
RE1/AD9
RE2/AD10
RE3/AD11
RE4/AD12
RE5/AD13
RE6/AD14
RE7/AD15
RH0/A16
RH1/A17
RH2/A18
RH3/A19
RJ0/ALE
RJ1/OE
PORTD
PORTD
PORTD
PORTD
PORTD
PORTD
PORTD
PORTD
PORTE
PORTE
PORTE
PORTE
PORTE
PORTE
PORTE
PORTE
PORTH
PORTH
PORTH
PORTH
PORTJ
PORTJ
PORTJ
PORTJ
PORTJ
PORTJ
PORTJ
PORTJ
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
0
1
2
3
4
5
6
7
Address bit 0 or Data bit 0
Address bit 1 or Data bit 1
Address bit 2 or Data bit 2
Address bit 3 or Data bit 3
Address bit 4 or Data bit 4
Address bit 5 or Data bit 5
Address bit 6 or Data bit 6
Address bit 7 or Data bit 7
Address bit 8 or Data bit 8
Address bit 9 or Data bit 9
Address bit 10 or Data bit 10
Address bit 11 or Data bit 11
Address bit 12 or Data bit 12
Address bit 13 or Data bit 13
Address bit 14 or Data bit 14
Address bit 15 or Data bit 15
Address bit 16
Address bit 17
Address bit 18
Address bit 19
Address Latch Enable (ALE) Control pin
Output Enable (OE) Control pin
Write Low (WRL) Control pin
Write High (WRH) Control pin
Byte Address bit 0 (BA0)
Chip Enable (CE) Control pin
Lower Byte Enable (LB) Control pin
Upper Byte Enable (UB) Control pin
RJ2/WRL
RJ3/WRH
RJ4/BA0
RJ5/CE
RJ6/LB
RJ7/UB
Note:
For the sake of clarity, only I/O port and external bus assignments are shown here. One or more additional
multiplexed features may be available on some pins.
© 2009 Microchip Technology Inc.
DS39778D-page 99
PIC18F87J11 FAMILY
The WAIT bits allow for the addition of wait states to
external memory operations. The use of these bits is
discussed in Section 7.3 “Wait States”.
7.1
External Memory Bus Control
The operation of the interface is controlled by the
MEMCON register (Register 7-1). This register is
available in all program memory operating modes
except Microcontroller mode. In this mode, the register
is disabled and cannot be written to.
The WM bits select the particular operating mode used
when the bus is operating in 16-Bit Data Width mode.
These are discussed in more detail in Section 7.6
“16-Bit Data Width Modes”. These bits have no effect
when an 8-bit Data Width mode is selected.
The EBDIS bit (MEMCON<7>) controls the operation
of the bus and related port functions. Clearing EBDIS
enables the interface and disables the I/O functions of
the ports, as well as any other functions multiplexed to
those pins. Setting the bit enables the I/O ports and
other functions, but allows the interface to override
everything else on the pins when an external memory
operation is required. By default, the external bus is
always enabled and disables all other I/O.
The MEMCON register (see Register 7-1) shares the
same memory space as the PR2 register and can be
alternately selected based on the designation of the
ADSHR bit in the WDTCON register (see
Register 24-9).
The operation of the EBDIS bit is also influenced by the
program memory mode being used. This is discussed
in more detail in Section 7.5 “Program Memory
Modes and the External Memory Bus”.
REGISTER 7-1:
MEMCON: EXTERNAL MEMORY BUS CONTROL REGISTER
R/W-0
EBDIS
bit 7
U-0
—
R/W-0
WAIT1
R/W-0
WAIT0
U-0
—
U-0
—
R/W-0
WM1
R/W-0
WM0
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7
EBDIS: External Bus Disable bit
1= External bus enabled when microcontroller accesses external memory; otherwise, all external bus
drivers are mapped as I/O ports
0= External bus always enabled, I/O ports are disabled
bit 6
Unimplemented: Read as ‘0’
bit 5-4
WAIT1:WAIT0: Table Reads and Writes Bus Cycle Wait Count bits
11= Table reads and writes will wait 0 TCY
10= Table reads and writes will wait 1 TCY
01= Table reads and writes will wait 2 TCY
00= Table reads and writes will wait 3 TCY
bit 3-2
bit 1-0
Unimplemented: Read as ‘0’
WM1:WM0: TBLWTOperation with 16-Bit Data Bus Width Select bits
1x= Word Write mode: TABLAT word output, WRH active when TABLAT written
01= Byte Select mode: TABLAT data copied on both MSB and LSB, WRH and (UB or LB) will activate
00= Byte Write mode: TABLAT data copied on both MSB and LSB, WRH or WRL will activate
DS39778D-page 100
© 2009 Microchip Technology Inc.
PIC18F87J11 FAMILY
7.2.1
ADDRESS SHIFTING ON THE
EXTERNAL BUS
7.2
Address and Data Width
The PIC18F87J11 Family of devices can be indepen-
dently configured for different address and data widths
on the same memory bus. Both address and data width
are set by Configuration bits in the CONFIG3L register.
As Configuration bits, this means that these options
can only be configured by programming the device and
are not controllable in software.
By default, the address presented on the external bus
is the value of the PC. In practical terms, this means
that addresses in the external memory device below
the top of on-chip memory are unavailable to the micro-
controller. To access these physical locations, the glue
logic between the microcontroller and the external
memory must somehow translate addresses.
The BW bit selects an 8-bit or 16-bit data bus width.
Setting this bit (default) selects a data width of 16 bits.
To simplify the interface, the external bus offers an
extension of Extended Microcontroller mode that
automatically performs address shifting. This feature is
controlled by the EASHFT Configuration bit. Setting
this bit offsets addresses on the bus by the size of the
microcontroller’s on-chip program memory and sets
the bottom address at 0000h. This allows the device to
use the entire range of physical addresses of the
external memory.
The EMB1:EMB0 bits determine both the program
memory operating mode and the address bus width.
The available options are 20-bit, 16-bit and 12-bit, as
well as Microcontroller mode (external bus disabled).
Selecting a 16-bit or 12-bit width makes a correspond-
ing number of high-order lines available for I/O
functions. These pins are no longer affected by the
setting of the EBDIS bit. For example, selecting a
16-Bit Addressing mode (EMB1:EMB0 = 01) disables
A19:A16 and allows PORTH<3:0> to function without
interruptions from the bus. Using the smaller address
widths allows users to tailor the memory bus to the size
of the external memory space for a particular design
while freeing up pins for dedicated I/O operation.
7.2.2
21-BIT ADDRESSING
As an extension of 20-bit address width operation, the
external memory bus can also fully address a 2-Mbyte
memory space. This is done by using the Bus Address
bit 0 (BA0) control line as the Least Significant bit of the
address. The UB and LB control signals may also be
used with certain memory devices to select the upper
and lower bytes within a 16-bit wide data word.
Because the EMB bits have the effect of disabling pins
for memory bus operations, it is important to always
select an address width at least equal to the data width.
If a 12-bit address width is used with a 16-bit data
width, the upper four bits of data will not be available on
the bus.
This addressing mode is available in both 8-bit and
certain 16-Bit Data Width modes. Additional details are
provided in Section 7.6.3 “16-Bit Byte Select Mode”
and Section 7.7 “8-Bit Data Width Mode”.
All combinations of address and data widths require
multiplexing of address and data information on the
same lines. The address and data multiplexing, as well
as I/O ports made available by the use of smaller
address widths, are summarized in Table 7-2.
TABLE 7-2:
Data Width
ADDRESS AND DATA LINES FOR DIFFERENT ADDRESS AND DATA WIDTHS
Multiplexed Data and
Address Lines (and
Address Only
Lines (and
Ports Available
for I/O
Address Width
Corresponding Ports) Corresponding Ports)
AD11:AD8
(PORTE<3:0>)
PORTE<7:4>,
All of PORTH
12-bit
16-bit
AD15:AD8
AD7:AD0
All of PORTH
8-bit
(PORTE<7:0>)
(PORTD<7:0>)
A19:A16, AD15:AD8
(PORTH<3:0>,
20-bit
—
PORTE<7:0>)
16-bit
20-bit
—
All of PORTH
—
AD15:AD0
(PORTD<7:0>,
PORTE<7:0>)
16-bit
A19:A16
(PORTH<3:0>)
© 2009 Microchip Technology Inc.
DS39778D-page 101
PIC18F87J11 FAMILY
functions. When EBDIS = 0, the pins function as the
external bus. When EBDIS = 1, the pins function as I/O
ports.
7.3
Wait States
While it may be assumed that external memory devices
will operate at the microcontroller clock rate, this is
often not the case. In fact, many devices require longer
times to write or retrieve data than the time allowed by
the execution of table read or table write operations.
If the device fetches or accesses external memory
while EBDIS = 1, the pins will switch to external bus. If
the EBDIS bit is set by a program executing from exter-
nal memory, the action of setting the bit will be delayed
until the program branches into the internal memory. At
that time, the pins will change from external bus to I/O
ports.
To compensate for this, the external memory bus can
be configured to add a fixed delay to each table opera-
tion using the bus. Wait states are enabled by setting
the WAIT Configuration bit. When enabled, the amount
of delay is set by the WAIT1:WAIT0 bits
(MEMCON<5:4>). The delay is based on multiples of
microcontroller instruction cycle time and are added
following the instruction cycle when the table operation
is executed. The range is from no delay to 3 TCY
(default value).
If the device is executing out of internal memory when
EBDIS = 0, the memory bus address/data and control
pins will not be active. They will go to a state where the
active address/data pins are tri-state; the CE, OE,
WRH, WRL, UB and LB signals are ‘1’ and ALE and
BA0 are ‘0’. Note that only those pins associated with
the current address width are forced to tri-state; the
other pins continue to function as I/O. In the case of
16-bit address width, for example, only AD<15:0>
(PORTD and PORTE) are affected; A19:A16
(PORTH<3:0>) continue to function as I/O.
7.4
Port Pin Weak Pull-ups
With the exception of the upper address lines,
A19:A16, the pins associated with the external memory
bus are equipped with weak pull-ups. The pull-ups are
controlled by the upper three bits of the PORTG
register (PORTG<7:5>). They are named RDPU,
REPU and RJPU and control pull-ups on PORTD,
PORTE and PORTJ, respectively. Setting one of these
bits enables the corresponding pull-ups for that port. All
pull-ups are disabled by default on all device Resets.
In all external memory modes, the bus takes priority
over any other peripherals that may share pins with it.
This includes the Parallel Master Port and serial
communication modules which would otherwise take
priority over the I/O port.
7.6
16-Bit Data Width Modes
In Extended Microcontroller mode, the port pull-ups
can be useful in preserving the memory state on the
external bus while the bus is temporarily disabled
(EBDIS = ‘1’).
In 16-Bit Data Width mode, the external memory
interface can be connected to external memories in
three different configurations:
• 16-Bit Byte Write
• 16-Bit Word Write
• 16-Bit Byte Select
7.5
Program Memory Modes and the
External Memory Bus
The configuration to be used is determined by the
WM1:WM0 bits in the MEMCON register
(MEMCON<1:0>). These three different configurations
allow the designer maximum flexibility in using both
8-bit and 16-bit devices with 16-bit data.
The PIC18F87J11 Family of devices is capable of
operating in one of two program memory modes, using
combinations of on-chip and external program memory.
The functions of the multiplexed port pins depend on
the program memory mode selected, as well as the
setting of the EBDIS bit.
For all 16-bit modes, the Address Latch Enable (ALE)
pin indicates that the address bits, AD<15:0>, are avail-
able on the external memory interface bus. Following
the address latch, the Output Enable signal (OE) will
enable both bytes of program memory at once to form
a 16-bit instruction word. The Chip Enable signal (CE)
is active at any time that the microcontroller accesses
external memory, whether reading or writing; it is
inactive (asserted high) whenever the device is in
Sleep mode.
In Microcontroller Mode, the bus is not active and the
pins have their port functions only. Writes to the
MEMCOM register are not permitted. The Reset value
of EBDIS (‘0’) is ignored and EMB pins behave as I/O
ports.
In Extended Microcontroller Mode, the external
program memory bus shares I/O port functions on the
pins. When the device is fetching or doing table
read/table write operations on the external program
memory space, the pins will have the external bus
function.
In Byte Select mode, JEDEC standard Flash memories
will require BA0 for the byte address line and one I/O
line to select between Byte and Word mode. The other
16-bit modes do not need BA0. JEDEC standard static
RAM memories will use the UB or LB signals for byte
selection.
If the device is fetching and accessing internal program
memory locations only, the EBDIS control bit will
change the pins from external memory to I/O port
DS39778D-page 102
© 2009 Microchip Technology Inc.
PIC18F87J11 FAMILY
During a TBLWTinstruction cycle, the TABLAT data is
presented on the upper and lower bytes of the
AD15:AD0 bus. The appropriate WRH or WRL control
line is strobed on the LSb of the TBLPTR.
7.6.1
16-BIT BYTE WRITE MODE
Figure 7-1 shows an example of 16-Bit Byte Write
mode for PIC18F87J11 Family devices. This mode is
used for two separate 8-bit memories connected for
16-bit operation. This generally includes basic EPROM
and Flash devices. It allows table writes to byte-wide
external memories.
FIGURE 7-1:
16-BIT BYTE WRITE MODE EXAMPLE
D<7:0>
(MSB)
A<x:0>
(LSB)
A<x:0>
PIC18F87J11
AD<7:0>
A<19:0>
D<15:8>
373
373
D<7:0>
D<7:0>
CE
D<7:0>
CE
AD<15:8>
ALE
(2)
(2)
OE WR
OE WR
(1)
A<19:16>
CE
OE
WRH
WRL
Address Bus
Data Bus
Control Lines
Note 1: Upper order address lines are used only for 20-bit address widths.
2: This signal only applies to table writes. See Section 6.1 “Table Reads and Table Writes”.
© 2009 Microchip Technology Inc.
DS39778D-page 103
PIC18F87J11 FAMILY
During
a
TBLWT cycle to an odd address
7.6.2
16-BIT WORD WRITE MODE
(TBLPTR<0> = 1), the TABLAT data is presented on
the upper byte of the AD15:AD0 bus. The contents of
the holding latch are presented on the lower byte of the
AD15:AD0 bus.
Figure 7-2 shows an example of 16-Bit Word Write
mode for PIC18F87J11 Family devices. This mode is
used for word-wide memories which include some of
the EPROM and Flash-type memories. This mode
allows opcode fetches and table reads from all forms of
16-bit memory and table writes to any type of
word-wide external memories. This method makes a
distinction between TBLWT cycles to even or odd
addresses.
The WRH signal is strobed for each write cycle; the
WRL pin is unused. The signal on the BA0 pin indicates
the LSb of the TBLPTR, but it is left unconnected.
Instead, the UB and LB signals are active to select both
bytes. The obvious limitation to this method is that the
table write must be done in pairs on a specific word
boundary to correctly write a word location.
During
a
TBLWT cycle to an even address
(TBLPTR<0> = 0), the TABLAT data is transferred to a
holding latch and the external address data bus is
tri-stated for the data portion of the bus cycle. No write
signals are activated.
FIGURE 7-2:
16-BIT WORD WRITE MODE EXAMPLE
PIC18F87J11
AD<7:0>
A<20:1>
D<15:0>
JEDEC Word
EPROM Memory
A<x:0>
373
D<15:0>
CE
(2)
OE
WR
AD<15:8>
ALE
373
(1)
A<19:16>
CE
OE
WRH
Address Bus
Data Bus
Control Lines
Note 1: Upper order address lines are used only for 20-bit address widths.
2: This signal only applies to table writes. See Section 6.1 “Table Reads and Table Writes”.
DS39778D-page 104
© 2009 Microchip Technology Inc.
PIC18F87J11 FAMILY
Flash and SRAM devices use different control signal
combinations to implement Byte Select mode. JEDEC
standard Flash memories require that a controller I/O
port pin be connected to the memory’s BYTE/WORD
pin to provide the select signal. They also use the BA0
signal from the controller as a byte address. JEDEC
standard static RAM memories, on the other hand, use
the UB or LB signals to select the byte.
7.6.3
16-BIT BYTE SELECT MODE
Figure 7-3 shows an example of 16-Bit Byte Select
mode. This mode allows table write operations to
word-wide external memories with byte selection
capability. This generally includes both word-wide
Flash and SRAM devices.
During a TBLWTcycle, the TABLAT data is presented
on the upper and lower byte of the AD15:AD0 bus. The
WRH signal is strobed for each write cycle; the WRL
pin is not used. The BA0 or UB/LB signals are used to
select the byte to be written, based on the Least
Significant bit of the TBLPTR register.
FIGURE 7-3:
16-BIT BYTE SELECT MODE EXAMPLE
PIC18F87J11
AD<7:0>
A<20:1>
JEDEC Word
FLASH Memory
373
373
A<x:1>
D<15:0>
D<15:0>
(3)
138
CE
A0
AD<15:8>
ALE
(1)
BYTE/WORD OE WR
(2)
A<19:16>
OE
WRH
WRL
A<20:1>
JEDEC Word
A<x:1>
SRAM Memory
BA0
I/O
D<15:0>
D<15:0>
CE
LB
LB
(1)
UB
OE WR
UB
Address Bus
Data Bus
Control Lines
Note 1: This signal only applies to table writes. See Section 6.1 “Table Reads and Table Writes”.
2: Upper order address lines are used only for 20-bit address width.
3: Demultiplexing is only required when multiple memory devices are accessed.
© 2009 Microchip Technology Inc.
DS39778D-page 105
PIC18F87J11 FAMILY
7.6.4
16-BIT MODE TIMING
The presentation of control signals on the external
memory bus is different for the various operating
modes. Typical signal timing diagrams are shown in
Figure 7-4 and Figure 7-5.
FIGURE 7-4:
EXTERNAL MEMORY BUS TIMING FOR TBLRD(EXTENDED
MICROCONTROLLER MODE)
Q1 Q2
Q3
Q4
Q1 Q2
Q3 Q4
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
0Ch
A<19:16>
AD<15:0>
CF33h
9256h
CE
ALE
OE
Opcode Fetch
TBLRD *
from 000100h
Opcode Fetch
MOVLW55h
from 000102h
TBLRD92h
from 199E67h
Opcode Fetch
ADDLW55h
from 000104h
Memory
Cycle
Instruction
Execution
INST(PC – 2)
TBLRDCycle 1
TBLRDCycle 2
MOVLW
FIGURE 7-5:
EXTERNAL MEMORY BUS TIMING FOR SLEEP (EXTENDED
MICROCONTROLLER MODE)
Q1 Q2
Q3
Q4
Q1 Q2
Q3 Q4
Q1
00h
00h
A<19:16>
AD<15:0>
0E55h
0003h
3AAAh
3AABh
CE
ALE
OE
Memory
Cycle
Opcode Fetch
MOVLW55h
Opcode Fetch
SLEEP
Sleep Mode, Bus Inactive
from 007554h
from 007556h
Instruction
Execution
INST(PC – 2)
SLEEP
DS39778D-page 106
© 2009 Microchip Technology Inc.
PIC18F87J11 FAMILY
will enable one byte of program memory for a portion of
the instruction cycle, then BA0 will change and the
second byte will be enabled to form the 16-bit instruc-
tion word. The Least Significant bit of the address, BA0,
must be connected to the memory devices in this
mode. The Chip Enable signal (CE) is active at any
time that the microcontroller accesses external
memory, whether reading or writing. It is inactive
(asserted high) whenever the device is in Sleep mode.
7.7
8-Bit Data Width Mode
In 8-Bit Data Width mode, the external memory bus
operates only in Multiplexed mode; that is, data shares
the 8 Least Significant bits of the address bus.
Figure 7-6 shows an example of 8-Bit Multiplexed
mode for 80-pin devices. This mode is used for a single
8-bit memory connected for 16-bit operation. The
instructions will be fetched as two 8-bit bytes on a
shared data/address bus. The two bytes are sequen-
tially fetched within one instruction cycle (TCY).
Therefore, the designer must choose external memory
devices according to timing calculations based on
1/2 TCY (2 times the instruction rate). For proper mem-
ory speed selection, glue logic propagation delay times
must be considered, along with setup and hold times.
This generally includes basic EPROM and Flash
devices. It allows table writes to byte-wide external
memories.
During a TBLWTinstruction cycle, the TABLAT data is
presented on the upper and lower bytes of the
AD15:AD0 bus. The appropriate level of the BA0
control line is strobed on the LSb of the TBLPTR.
The Address Latch Enable (ALE) pin indicates that the
address bits, AD<15:0>, are available on the external
memory interface bus. The Output Enable signal (OE)
FIGURE 7-6:
8-BIT MULTIPLEXED MODE EXAMPLE
D<7:0>
PIC18F87J11
AD<7:0>
A<19:0>
A<x:1>
373
ALE
D<15:8>
A0
D<7:0>
CE
(1)
AD<15:8>
(1)
(2)
A<19:16>
OE WR
BA0
CE
OE
WRL
Address Bus
Data Bus
Control Lines
Note 1: Upper order address bits are only used for 20-bit address width. The upper AD byte is used for all
address widths except 8-bit.
2: This signal only applies to table writes. See Section 6.1 “Table Reads and Table Writes”.
© 2009 Microchip Technology Inc.
DS39778D-page 107
PIC18F87J11 FAMILY
7.7.1
8-BIT MODE TIMING
The presentation of control signals on the external
memory bus is different for the various operating
modes. Typical signal timing diagrams are shown in
Figure 7-7 and Figure 7-8.
FIGURE 7-7:
EXTERNAL MEMORY BUS TIMING FOR TBLRD(EXTENDED
MICROCONTROLLER MODE)
Q1 Q2
Q3
Q4
Q1 Q2
Q3 Q4
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
A<19:16>
AD<15:8>
AD<7:0>
0Ch
CFh
33h
92h
CE
ALE
OE
Opcode Fetch
TBLRD *
from 000100h
Opcode Fetch
MOVLW55h
from 000102h
Opcode Fetch
ADDLW55h
from 000104h
TBLRD92h
from 199E67h
Memory
Cycle
Instruction
Execution
INST(PC – 2)
TBLRDCycle 1
TBLRDCycle 2
MOVLW
FIGURE 7-8:
EXTERNAL MEMORY BUS TIMING FOR SLEEP (EXTENDED
MICROCONTROLLER MODE)
Q1 Q2
Q3
Q4
Q1 Q2
Q3 Q4
Q1
00h
00h
A<19:16>
3Ah
00h 03h
3Ah
0Eh 55h
AD<15:8>
AD<7:0>
AAh
ABh
BA0
CE
ALE
OE
Memory
Cycle
Opcode Fetch
MOVLW55h
Opcode Fetch
Sleep Mode, Bus Inactive
SLEEP
from 007554h
from 007556h
Instruction
Execution
INST(PC – 2)
SLEEP
DS39778D-page 108
© 2009 Microchip Technology Inc.
PIC18F87J11 FAMILY
In Sleep and Idle modes, the microcontroller core does
not need to access data; bus operations are
suspended. The state of the external bus is frozen, with
the address/data pins and most of the control pins hold-
ing at the same state they were in when the mode was
invoked. The only potential changes are the CE, LB
and UB pins, which are held at logic high.
7.8
Operation in Power-Managed
Modes
In alternate, power-managed Run modes, the external
bus continues to operate normally. If a clock source
with a lower speed is selected, bus operations will run
at that speed. In these cases, excessive access times
for the external memory may result if wait states have
been enabled and added to external memory opera-
tions. If operations in a lower power Run mode are
anticipated, users should provide in their applications
for adjusting memory access times at the lower clock
speeds.
© 2009 Microchip Technology Inc.
DS39778D-page 109
PIC18F87J11 FAMILY
NOTES:
DS39778D-page 110
© 2009 Microchip Technology Inc.
PIC18F87J11 FAMILY
EXAMPLE 8-1:
8 x 8 UNSIGNED
MULTIPLY ROUTINE
8.0
8.1
8 x 8 HARDWARE MULTIPLIER
Introduction
MOVF
MULWF
ARG1, W
ARG2
;
; ARG1 * ARG2 ->
; PRODH:PRODL
All PIC18 devices include an 8 x 8 hardware multiplier
as part of the ALU. The multiplier performs an unsigned
operation and yields a 16-bit result that is stored in the
product register pair, PRODH:PRODL. The multiplier’s
operation does not affect any flags in the STATUS
register.
EXAMPLE 8-2:
8 x 8 SIGNED MULTIPLY
ROUTINE
Making multiplication a hardware operation allows it to
be completed in a single instruction cycle. This has the
advantages of higher computational throughput and
reduced code size for multiplication algorithms and
allows the PIC18 devices to be used in many applica-
tions previously reserved for digital signal processors.
A comparison of various hardware and software
multiply operations, along with the savings in memory
and execution time, is shown in Table 8-1.
MOVF
MULWF
ARG1, W
ARG2
; ARG1 * ARG2 ->
; PRODH:PRODL
; Test Sign Bit
; PRODH = PRODH
BTFSC
SUBWF
ARG2, SB
PRODH, F
;
- ARG1
MOVF
BTFSC
SUBWF
ARG2, W
ARG1, SB
PRODH, F
; Test Sign Bit
; PRODH = PRODH
;
- ARG2
8.2
Operation
Example 8-1 shows the instruction sequence for an 8 x 8
unsigned multiplication. Only one instruction is required
when one of the arguments is already loaded in the
WREG register.
Example 8-2 shows the sequence to do an 8 x 8 signed
multiplication. To account for the sign bits of the argu-
ments, each argument’s Most Significant bit (MSb) is
tested and the appropriate subtractions are done.
TABLE 8-1:
Routine
PERFORMANCE COMPARISON FOR VARIOUS MULTIPLY OPERATIONS
Program
Memory
(Words)
Time
Cycles
(Max)
Multiply Method
@ 48 MHz @ 10 MHz @ 4 MHz
Without hardware multiply
Hardware multiply
13
1
69
1
5.7 μs
83.3 ns
7.5 μs
27.6 μs
400 ns
36.4 μs
2.4 μs
69 μs
1 μs
8 x 8 unsigned
8 x 8 signed
Without hardware multiply
Hardware multiply
33
6
91
6
91 μs
6 μs
500 ns
20.1 μs
2.3 μs
Without hardware multiply
Hardware multiply
21
28
52
35
242
28
254
40
96.8 μs
11.2 μs
102.6 μs
16.0 μs
242 μs
28 μs
254 μs
40 μs
16 x 16 unsigned
16 x 16 signed
Without hardware multiply
Hardware multiply
21.6 μs
3.3 μs
© 2009 Microchip Technology Inc.
DS39778D-page 111
PIC18F87J11 FAMILY
Example 8-3 shows the sequence to do a 16 x 16
unsigned multiplication. Equation 8-1 shows the
algorithm that is used. The 32-bit result is stored in four
registers (RES3:RES0).
EQUATION 8-2:
16 x 16 SIGNED
MULTIPLICATION
ALGORITHM
RES3:RES0 = ARG1H:ARG1L • ARG2H:ARG2L
16
= (ARG1H • ARG2H • 2 ) +
(ARG1H • ARG2L • 2 ) +
(ARG1L • ARG2H • 2 ) +
(ARG1L • ARG2L) +
(-1 • ARG2H<7> • ARG1H:ARG1L • 2 ) +
(-1 • ARG1H<7> • ARG2H:ARG2L • 2
8
EQUATION 8-1:
16 x 16 UNSIGNED
MULTIPLICATION
ALGORITHM
8
16
RES3:RES0
=
=
ARG1H:ARG1L • ARG2H:ARG2L
16
)
16
(ARG1H • ARG2H • 2 ) +
8
(ARG1H • ARG2L • 2 ) +
8
(ARG1L • ARG2H • 2 ) +
EXAMPLE 8-4:
16 x 16 SIGNED
MULTIPLY ROUTINE
(ARG1L • ARG2L)
MOVF
MULWF
ARG1L, W
ARG2L
; ARG1L * ARG2L ->
; PRODH:PRODL
;
;
EXAMPLE 8-3:
16 x 16 UNSIGNED
MULTIPLY ROUTINE
MOVFF
MOVFF
PRODH, RES1
PRODL, RES0
MOVF
MULWF
ARG1L, W
ARG2L
; ARG1L * ARG2L->
; PRODH:PRODL
;
;
;
;
MOVF
MULWF
ARG1H, W
ARG2H
MOVFF
MOVFF
PRODH, RES1
PRODL, RES0
; ARG1H * ARG2H ->
; PRODH:PRODL
;
;
;
;
MOVFF
MOVFF
PRODH, RES3
PRODL, RES2
MOVF
MULWF
ARG1H, W
ARG2H
; ARG1H * ARG2H->
; PRODH:PRODL
;
;
MOVF
MULWF
ARG1L, W
ARG2H
MOVFF
MOVFF
PRODH, RES3
PRODL, RES2
; ARG1L * ARG2H ->
; PRODH:PRODL
;
; Add cross
; products
;
;
;
MOVF
ADDWF
MOVF
ADDWFC RES2, F
CLRF WREG
ADDWFC RES3, F
PRODL, W
RES1, F
PRODH, W
MOVF
MULWF
ARG1L, W
ARG2H
; ARG1L * ARG2H->
; PRODH:PRODL
;
; Add cross
; products
;
;
;
MOVF
ADDWF
MOVF
PRODL, W
RES1, F
PRODH, W
;
ADDWFC RES2, F
CLRF WREG
ADDWFC RES3, F
MOVF
MULWF
ARG1H, W
ARG2L
;
; ARG1H * ARG2L ->
; PRODH:PRODL
;
; Add cross
; products
;
;
;
;
MOVF
ADDWF
MOVF
ADDWFC RES2, F
CLRF WREG
ADDWFC RES3, F
PRODL, W
RES1, F
PRODH, W
MOVF
MULWF
ARG1H, W
ARG2L
;
; ARG1H * ARG2L->
; PRODH:PRODL
;
; Add cross
; products
;
;
;
MOVF
ADDWF
MOVF
PRODL, W
RES1, F
PRODH, W
;
;
ADDWFC RES2, F
CLRF WREG
ADDWFC RES3, F
BTFSS
BRA
MOVF
SUBWF
MOVF
ARG2H, 7
SIGN_ARG1
ARG1L, W
RES2
; ARG2H:ARG2L neg?
; no, check ARG1
;
;
;
Example 8-4 shows the sequence to do a 16 x 16
signed multiply. Equation 8-2 shows the algorithm
used. The 32-bit result is stored in four registers
(RES3:RES0). To account for the sign bits of the
arguments, the MSb for each argument pair is tested
and the appropriate subtractions are done.
ARG1H, W
SUBWFB RES3
SIGN_ARG1
BTFSS
BRA
ARG1H, 7
CONT_CODE
ARG2L, W
RES2
; ARG1H:ARG1L neg?
; no, done
;
;
;
MOVF
SUBWF
MOVF
ARG2H, W
SUBWFB RES3
;
CONT_CODE
:
DS39778D-page 112
© 2009 Microchip Technology Inc.
PIC18F87J11 FAMILY
When the IPEN bit is cleared (default state), the
interrupt priority feature is disabled and interrupts are
compatible with PIC16 mid-range devices. In
Compatibility mode, the interrupt priority bits for each
source have no effect. INTCON<6> is the PEIE bit
which enables/disables all peripheral interrupt sources.
INTCON<7> is the GIE bit which enables/disables all
interrupt sources. All interrupts branch to address
0008h in Compatibility mode.
9.0
INTERRUPTS
Members of the PIC18F87J11 Family of devices have
multiple interrupt sources and an interrupt priority fea-
ture that allows most interrupt sources to be assigned
a high-priority level or a low-priority level. The
high-priority interrupt vector is at 0008h and the
low-priority interrupt vector is at 0018h. High-priority
interrupt events will interrupt any low-priority interrupts
that may be in progress.
When an interrupt is responded to, the global interrupt
enable bit is cleared to disable further interrupts. If the
IPEN bit is cleared, this is the GIE bit. If interrupt priority
levels are used, this will be either the GIEH or GIEL bit.
There are thirteen registers which are used to control
interrupt operation. These registers are:
• RCON
High-priority interrupt sources can interrupt
a
• INTCON
low-priority interrupt. Low-priority interrupts are not
processed while high-priority interrupts are in progress.
• INTCON2
• INTCON3
The return address is pushed onto the stack and the
PC is loaded with the interrupt vector address (0008h
or 0018h). Once in the Interrupt Service Routine, the
source(s) of the interrupt can be determined by polling
the interrupt flag bits. The interrupt flag bits must be
cleared in software before re-enabling interrupts to
avoid recursive interrupts.
• PIR1, PIR2, PIR3
• PIE1, PIE2, PIE3
• IPR1, IPR2, IPR3
It is recommended that the Microchip header files
supplied with MPLAB® IDE be used for the symbolic bit
names in these registers. This allows the
assembler/compiler to automatically take care of the
placement of these bits within the specified register.
The “return from interrupt” instruction, RETFIE, exits
the interrupt routine and sets the GIE bit (GIEH or GIEL
if priority levels are used) which re-enables interrupts.
In general, interrupt sources have three bits to control
their operation. They are:
For external interrupt events, such as the INTx pins or
the PORTB input change interrupt, the interrupt latency
will be three to four instruction cycles. The exact
latency is the same for one or two-cycle instructions.
Individual interrupt flag bits are set regardless of the
status of their corresponding enable bit or the GIE bit.
• Flag bit to indicate that an interrupt event
occurred
• Enable bit that allows program execution to
branch to the interrupt vector address when the
flag bit is set
Note:
Do not use the MOVFFinstruction to modify
any of the interrupt control registers while
any interrupt is enabled. Doing so may
cause erratic microcontroller behavior.
• Priority bit to select high-priority or low-priority
The interrupt priority feature is enabled by setting the
IPEN bit (RCON<7>). When interrupt priority is
enabled, there are two bits which enable interrupts
globally. Setting the GIEH bit (INTCON<7>) enables all
interrupts that have the priority bit set (high priority).
Setting the GIEL bit (INTCON<6>) enables all
interrupts that have the priority bit cleared (low priority).
When the interrupt flag, enable bit and appropriate
global interrupt enable bit are set, the interrupt will
vector immediately to address 0008h or 0018h,
depending on the priority bit setting. Individual
interrupts can be disabled through their corresponding
enable bits.
© 2009 Microchip Technology Inc.
DS39778D-page 113
PIC18F87J11 FAMILY
FIGURE 9-1:
PIC18F87J11 FAMILY INTERRUPT LOGIC
Wake-up if in
Idle or Sleep modes
TMR0IF
TMR0IE
TMR0IP
RBIF
RBIE
RBIP
INT0IF
INT0IE
INT1IF
INT1IE
INT1IP
INT2IF
INT2IE
INT2IP
INT3IF
INT3IE
INT3IP
Interrupt to CPU
Vector to Location
0008h
PIR1<7:0>
PIE1<7:0>
IPR1<7:0>
GIE/GIEH
PIR2<7:5, 3:0>
PIE2<7:5, 3:0>
IPR2<7:5, 3:0>
IPEN
PIR3<7, 0>
PIE3<7, 0>
IPR3<7, 0>
IPEN
PEIE/GIEL
IPEN
High-Priority Interrupt Generation
Low-Priority Interrupt Generation
PIR1<7:0>
PIE1<7:0>
IPR1<7:0>
PIR2<7:5, 3:0>
PIE2<7:5, 3:0>
IPR2<7:5, 3:0>
Interrupt to CPU
Vector to Location
0018h
TMR0IF
TMR0IE
TMR0IP
IPEN
PIR3<7, 0>
PIE3<7, 0>
IPR3<7, 0>
RBIF
RBIE
RBIP
GIE/GIEH
PEIE/GIEL
INT1IF
INT1IE
INT1IP
INT2IF
INT2IE
INT2IP
INT3IF
INT3IE
INT3IP
DS39778D-page 114
© 2009 Microchip Technology Inc.
PIC18F87J11 FAMILY
9.1
INTCON Registers
Note:
Interrupt flag bits are set when an interrupt
condition occurs regardless of the state of
its corresponding enable bit or the global
interrupt enable bit. User software should
ensure the appropriate interrupt flag bits
are clear prior to enabling an interrupt.
This feature allows for software polling.
The INTCON registers are readable and writable
registers which contain various enable, priority and flag
bits.
REGISTER 9-1:
INTCON: INTERRUPT CONTROL REGISTER
R/W-0
R/W-0
PEIE/GIEL
R/W-0
R/W-0
R/W-0
RBIE
R/W-0
R/W-0
INT0IF
R/W-x
RBIF(1)
GIE/GIEH
bit 7
TMR0IE
INT0IE
TMR0IF
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7
GIE/GIEH: Global Interrupt Enable bit
When IPEN = 0:
1= Enables all unmasked interrupts
0= Disables all interrupts
When IPEN = 1:
1= Enables all high-priority interrupts
0= Disables all interrupts
bit 6
PEIE/GIEL: Peripheral Interrupt Enable bit
When IPEN = 0:
1= Enables all unmasked peripheral interrupts
0= Disables all peripheral interrupts
When IPEN = 1:
1= Enables all low-priority peripheral interrupts
0= Disables all low-priority peripheral interrupts
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
TMR0IE: TMR0 Overflow Interrupt Enable bit
1= Enables the TMR0 overflow interrupt
0= Disables the TMR0 overflow interrupt
INT0IE: INT0 External Interrupt Enable bit
1= Enables the INT0 external interrupt
0= Disables the INT0 external interrupt
RBIE: RB Port Change Interrupt Enable bit
1= Enables the RB port change interrupt
0= Disables the RB port change interrupt
TMR0IF: TMR0 Overflow Interrupt Flag bit
1= TMR0 register has overflowed (must be cleared in software)
0= TMR0 register did not overflow
INT0IF: INT0 External Interrupt Flag bit
1= The INT0 external interrupt occurred (must be cleared in software)
0= The INT0 external interrupt did not occur
RBIF: RB Port Change Interrupt Flag bit(1)
1= At least one of the RB7:RB4 pins changed state (must be cleared in software)
0= None of the RB7:RB4 pins have changed state
Note 1: A mismatch condition will continue to set this bit. Reading PORTB will end the mismatch condition and
allow the bit to be cleared.
© 2009 Microchip Technology Inc.
DS39778D-page 115
PIC18F87J11 FAMILY
REGISTER 9-2:
INTCON2: INTERRUPT CONTROL REGISTER 2
R/W-1
R/W-1
INTEDG0
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
RBIP
RBPU
bit 7
INTEDG1
INTEDG2
INTEDG3
TMR0IP
INT3IP
bit 0
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
-n = Value at POR
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
RBPU: PORTB Pull-up Enable bit
1= All PORTB pull-ups are disabled
0= PORTB pull-ups are enabled by individual port latch values
INTEDG0: External Interrupt 0 Edge Select bit
1= Interrupt on rising edge
0= Interrupt on falling edge
INTEDG1: External Interrupt 1 Edge Select bit
1= Interrupt on rising edge
0= Interrupt on falling edge
INTEDG2: External Interrupt 2 Edge Select bit
1= Interrupt on rising edge
0= Interrupt on falling edge
INTEDG3: External Interrupt 3 Edge Select bit
1= Interrupt on rising edge
0= Interrupt on falling edge
TMR0IP: TMR0 Overflow Interrupt Priority bit
1= High priority
0= Low priority
INT3IP: INT3 External Interrupt Priority bit
1= High priority
0= Low priority
RBIP: RB Port Change Interrupt Priority bit
1= High priority
0= Low priority
Note:
Interrupt flag bits are set when an interrupt condition occurs regardless of the state of its corresponding
enable bit or the global interrupt enable bit. User software should ensure the appropriate interrupt flag bits
are clear prior to enabling an interrupt. This feature allows for software polling.
DS39778D-page 116
© 2009 Microchip Technology Inc.
PIC18F87J11 FAMILY
REGISTER 9-3:
INTCON3: INTERRUPT CONTROL REGISTER 3
R/W-1
INT2IP
bit 7
R/W-1
R/W-0
R/W-0
R/W-0
R/W-0
INT3IF
R/W-0
INT2IF
R/W-0
INT1IF
INT1IP
INT3IE
INT2IE
INT1IE
bit 0
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
-n = Value at POR
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
INT2IP: INT2 External Interrupt Priority bit
1= High priority
0= Low priority
INT1IP: INT1 External Interrupt Priority bit
1= High priority
0= Low priority
INT3IE: INT3 External Interrupt Enable bit
1= Enables the INT3 external interrupt
0= Disables the INT3 external interrupt
INT2IE: INT2 External Interrupt Enable bit
1= Enables the INT2 external interrupt
0= Disables the INT2 external interrupt
INT1IE: INT1 External Interrupt Enable bit
1= Enables the INT1 external interrupt
0= Disables the INT1 external interrupt
INT3IF: INT3 External Interrupt Flag bit
1= The INT3 external interrupt occurred (must be cleared in software)
0= The INT3 external interrupt did not occur
INT2IF: INT2 External Interrupt Flag bit
1= The INT2 external interrupt occurred (must be cleared in software)
0= The INT2 external interrupt did not occur
INT1IF: INT1 External Interrupt Flag bit
1= The INT1 external interrupt occurred (must be cleared in software)
0= The INT1 external interrupt did not occur
Note:
Interrupt flag bits are set when an interrupt condition occurs regardless of the state of its corresponding
enable bit or the global interrupt enable bit. User software should ensure the appropriate interrupt flag bits
are clear prior to enabling an interrupt. This feature allows for software polling.
© 2009 Microchip Technology Inc.
DS39778D-page 117
PIC18F87J11 FAMILY
9.2
PIR Registers
Note 1: Interrupt flag bits are set when an interrupt
condition occurs regardless of the state of
its corresponding enable bit or the Global
Interrupt Enable bit, GIE (INTCON<7>).
The PIR registers contain the individual flag bits for the
peripheral interrupts. Due to the number of peripheral
interrupt sources, there are three Peripheral Interrupt
Request (Flag) registers (PIR1, PIR2, PIR3).
2: User software should ensure the
appropriate interrupt flag bits are cleared
prior to enabling an interrupt and after
servicing that interrupt.
REGISTER 9-4:
PIR1: PERIPHERAL INTERRUPT REQUEST (FLAG) REGISTER 1
R/W-0
PMPIF
bit 7
R/W-0
ADIF
R-0
R-0
R/W-0
R/W-0
R/W-0
R/W-0
RC1IF
TX1IF
SSP1IF
CCP1IF
TMR2IF
TMR1IF
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
PMPIF: Parallel Master Port Read/Write Interrupt Flag bit
1= A read or a write operation has taken place (must be cleared in software)
0= No read or write has occurred
ADIF: A/D Converter Interrupt Flag bit
1= An A/D conversion completed (must be cleared in software)
0= The A/D conversion is not complete
RC1IF: EUSART1 Receive Interrupt Flag bit
1= The EUSART1 receive buffer, RCREG1, is full (cleared when RCREG1 is read)
0= The EUSART1 receive buffer is empty
TX1IF: EUSART1 Transmit Interrupt Flag bit
1= The EUSART1 transmit buffer, TXREG1, is empty (cleared when TXREG1 is written)
0= The EUSART1 transmit buffer is full
SSP1IF: MSSP1 Interrupt Flag bit
1= The transmission/reception is complete (must be cleared in software)
0= Waiting to transmit/receive
CCP1IF: ECCP1 Interrupt Flag bit
Capture mode:
1= A TMR1/TMR3 register capture occurred (must be cleared in software)
0= No TMR1/TMR3 register capture occurred
Compare mode:
1= A TMR1/TMR3 register compare match occurred (must be cleared in software)
0= No TMR1/TMR3 register compare match occurred
PWM mode:
Unused in this mode.
bit 1
bit 0
TMR2IF: TMR2 to PR2 Match Interrupt Flag bit
1= TMR2 to PR2 match occurred (must be cleared in software)
0= No TMR2 to PR2 match occurred
TMR1IF: TMR1 Overflow Interrupt Flag bit
1= TMR1 register overflowed (must be cleared in software)
0= TMR1 register did not overflow
DS39778D-page 118
© 2009 Microchip Technology Inc.
PIC18F87J11 FAMILY
REGISTER 9-5:
PIR2: PERIPHERAL INTERRUPT REQUEST (FLAG) REGISTER 2
R/W-0
OSCFIF
bit 7
R/W-0
CM2IF
R/W-0
CM1IF
U-0
—
R/W-0
R/W-0
LVDIF
R/W-0
R/W-0
BCL1IF
TMR3IF
CCP2IF
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7
bit 6
bit 5
OSCFIF: Oscillator Fail Interrupt Flag bit
1= Device oscillator failed, clock input has changed to INTOSC (must be cleared in software)
0= Device clock operating
CM2IF: Comparator 2 Interrupt Flag bit
1= Comparator input has changed (must be cleared in software)
0= Comparator input has not changed
CM1IF: Comparator 1 Interrupt Flag bit
1= Comparator input has changed (must be cleared in software)
0= Comparator input has not changed
bit 4
bit 3
Unimplemented: Read as ‘0’
BCL1IF: Bus Collision Interrupt Flag bit (MSSP1 module)
1= A bus collision occurred (must be cleared in software)
0= No bus collision occurred
bit 2
bit 1
bit 0
LVDIF: Low-Voltage Detect Interrupt Flag bit
1= A low-voltage condition occurred (must be cleared in software)
0= VDDCORE has not fallen below the low-voltage trip point (about 2.45V)
TMR3IF: TMR3 Overflow Interrupt Flag bit
1= TMR3 register overflowed (must be cleared in software)
0= TMR3 register did not overflow
CCP2IF: ECCP2 Interrupt Flag bit
Capture mode:
1= A TMR1/TMR3 register capture occurred (must be cleared in software)
0= No TMR1/TMR3 register capture occurred
Compare mode:
1= A TMR1/TMR3 register compare match occurred (must be cleared in software)
0= No TMR1/TMR3 register compare match occurred
PWM mode:
Unused in this mode.
© 2009 Microchip Technology Inc.
DS39778D-page 119
PIC18F87J11 FAMILY
REGISTER 9-6:
PIR3: PERIPHERAL INTERRUPT REQUEST (FLAG) REGISTER 3
R/W-0
SSP2IF
bit 7
R/W-0
R-0
R/W-0
TX2IF
R/W-0
R/W-0
R/W-0
R/W-0
BCL2IF
RC2IF
TMR4IF
CCP5IF
CCP4IF
CCP3IF
bit 0
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
-n = Value at POR
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
SSP2IF: MSSP2 Interrupt Flag bit
1= The transmission/reception is complete (must be cleared in software)
0= Waiting to transmit/receive
BCL2IF: Bus Collision Interrupt Flag bit (MSSP2 module)
1= A bus collision occurred (must be cleared in software)
0= No bus collision occurred
RC2IF: EUSART2 Receive Interrupt Flag bit
1= The EUSART2 receive buffer, RCREG2, is full (cleared when RCREG2 is read)
0= The EUSART2 receive buffer is empty
TX2IF: EUSART2 Transmit Interrupt Flag bit
1= The EUSART2 transmit buffer, TXREG2, is empty (cleared when TXREG2 is written)
0= The EUSART2 transmit buffer is full
TMR4IF: TMR4 to PR4 Match Interrupt Flag bit
1= TMR4 to PR4 match occurred (must be cleared in software)
0= No TMR4 to PR4 match occurred
CCP5IF: CCP5 Interrupt Flag bit
Capture mode:
1= A TMR1/TMR3 register capture occurred (must be cleared in software)
0= No TMR1/TMR3 register capture occurred
Compare mode:
1= A TMR1/TMR3 register compare match occurred (must be cleared in software)
0= No TMR1/TMR3 register compare match occurred
PWM mode:
Unused in this mode.
bit 1
CCP4IF: CCP4 Interrupt Flag bit
Capture mode:
1= A TMR1/TMR3 register capture occurred (must be cleared in software)
0= No TMR1/TMR3 register capture occurred
Compare mode:
1= A TMR1/TMR3 register compare match occurred (must be cleared in software)
0= No TMR1/TMR3 register compare match occurred
PWM mode:
Unused in this mode.
CCP3IF: ECCP3 Interrupt Flag bit
bit 0
Capture mode:
1= A TMR1/TMR3 register capture occurred (must be cleared in software)
0= No TMR1/TMR3 register capture occurred
Compare mode:
1= A TMR1/TMR3 register compare match occurred (must be cleared in software)
0= No TMR1/TMR3 register compare match occurred
PWM mode:
Unused in this mode.
DS39778D-page 120
© 2009 Microchip Technology Inc.
PIC18F87J11 FAMILY
9.3
PIE Registers
The PIE registers contain the individual enable bits for
the peripheral interrupts. Due to the number of
peripheral interrupt sources, there are three Peripheral
Interrupt Enable registers (PIE1, PIE2, PIE3). When
IPEN = 0, the PEIE bit must be set to enable any of
these peripheral interrupts.
REGISTER 9-7:
PIE1: PERIPHERAL INTERRUPT ENABLE REGISTER 1
R/W-0
PMPIE
bit 7
R/W-0
ADIE
R/W-0
RC1IE
R/W-0
TX1IE
R/W-0
R/W-0
R/W-0
R/W-0
SSP1IE
CCP1IE
TMR2IE
TMR1IE
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
PMPIE: Parallel Master Port Read/Write Interrupt Enable bit
1= Enables the PM read/write interrupt
0= Disables the PM read/write interrupt
ADIE: A/D Converter Interrupt Enable bit
1= Enables the A/D interrupt
0= Disables the A/D interrupt
RC1IE: EUSART1 Receive Interrupt Enable bit
1= Enables the EUSART1 receive interrupt
0= Disables the EUSART1 receive interrupt
TX1IE: EUSART1 Transmit Interrupt Enable bit
1= Enables the EUSART1 transmit interrupt
0= Disables the EUSART1 transmit interrupt
SSP1IE: MSSP1 Interrupt Enable bit
1= Enables the MSSP1 interrupt
0= Disables the MSSP1 interrupt
CCP1IE: ECCP1 Interrupt Enable bit
1= Enables the ECCP1 interrupt
0= Disables the ECCP1 interrupt
TMR2IE: TMR2 to PR2 Match Interrupt Enable bit
1= Enables the TMR2 to PR2 match interrupt
0= Disables the TMR2 to PR2 match interrupt
TMR1IE: TMR1 Overflow Interrupt Enable bit
1= Enables the TMR1 overflow interrupt
0= Disables the TMR1 overflow interrupt
© 2009 Microchip Technology Inc.
DS39778D-page 121
PIC18F87J11 FAMILY
REGISTER 9-8:
PIE2: PERIPHERAL INTERRUPT ENABLE REGISTER 2
R/W-0
OSCFIE
bit 7
R/W-0
CM2IE
R/W-0
CM1IE
U-0
—
R/W-0
R/W-0
LVDIE
R/W-0
R/W-0
BCL1IE
TMR3IE
CCP2IE
bit 0
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
-n = Value at POR
bit 7
bit 6
bit 5
OSCFIE: Oscillator Fail Interrupt Enable bit
1= Enabled
0= Disabled
CM2IE: Comparator 2 Interrupt Enable bit
1= Enabled
0= Disabled
CM1IE: Comparator 1 Interrupt Enable bit
1= Enabled
0= Disabled
bit 4
bit 3
Unimplemented: Read as ‘0’
BCL1IE: Bus Collision Interrupt Enable bit (MSSP1 module)
1= Enabled
0= Disabled
bit 2
bit 1
bit 0
LVDIE: Low-Voltage Detect Interrupt Enable bit
1= Enabled
0= Disabled
TMR3IE: TMR3 Overflow Interrupt Enable bit
1= Enabled
0= Disabled
CCP2IE: ECCP2 Interrupt Enable bit
1= Enabled
0= Disabled
DS39778D-page 122
© 2009 Microchip Technology Inc.
PIC18F87J11 FAMILY
REGISTER 9-9:
PIE3: PERIPHERAL INTERRUPT ENABLE REGISTER 3
R/W-0
SSP2IE
bit 7
R/W-0
R/W-0
RC2IE
R/W-0
TX2IE
R/W-0
R/W-0
R/W-0
R/W-0
BCL2IE
TMR4IE
CCP5IE
CCP4IE
CCP3IE
bit 0
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
-n = Value at POR
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
SSP2IE: MSSP2 Interrupt Enable bit
1= Enabled
0= Disabled
BCL2IE: Bus Collision Interrupt Enable bit (MSSP2 module)
1= Enabled
0= Disabled
RC2IE: EUSART2 Receive Interrupt Enable bit
1= Enabled
0= Disabled
TX2IE: EUSART2 Transmit Interrupt Enable bit
1= Enabled
0= Disabled
TMR4IE: TMR4 to PR4 Match Interrupt Enable bit
1= Enabled
0= Disabled
CCP5IE: CCP5 Interrupt Enable bit
1= Enabled
0= Disabled
CCP4IE: CCP4 Interrupt Enable bit
1= Enabled
0= Disabled
CCP3IE: ECCP3 Interrupt Enable bit
1= Enabled
0= Disabled
© 2009 Microchip Technology Inc.
DS39778D-page 123
PIC18F87J11 FAMILY
9.4
IPR Registers
The IPR registers contain the individual priority bits for
the peripheral interrupts. Due to the number of
peripheral interrupt sources, there are three Peripheral
Interrupt Priority registers (IPR1, IPR2, IPR3). Using
the priority bits requires that the Interrupt Priority
Enable (IPEN) bit be set.
REGISTER 9-10: IPR1: PERIPHERAL INTERRUPT PRIORITY REGISTER 1
R/W-1
R/W-1
ADIP
R/W-1
RC1IP
R/W-1
TX1IP
R/W-1
R/W-1
R/W-1
R/W-1
PMPIP
SSP1IP
CCP1IP
TMR2IP
TMR1IP
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7
bit 6
bit 5
bit 4
PMPIP: Parallel Master Port Read/Write Interrupt Priority bit
1= High priority
0= Low priority
ADIP: A/D Converter Interrupt Priority bit
1= High priority
0= Low priority
RC1IP: EUSART1 Receive Interrupt Priority bit
1= High priority
0= Low priority
TX1IP: EUSART1 Transmit Interrupt Priority bit
1= High priority
0= Low priority
bit 3
bit 2
bit 1
bit 0
SSP1IP: MSSP1 Interrupt Priority bit
1= High priority
0= Low priority
CCP1IP: ECCP1 Interrupt Priority bit
1= High priority
0= Low priority
TMR2IP: TMR2 to PR2 Match Interrupt Priority bit
1= High priority
0= Low priority
TMR1IP: TMR1 Overflow Interrupt Priority bit
1= High priority
0= Low priority
DS39778D-page 124
© 2009 Microchip Technology Inc.
PIC18F87J11 FAMILY
REGISTER 9-11: IPR2: PERIPHERAL INTERRUPT PRIORITY REGISTER 2
R/W-1
R/W-1
CM2IP
R/W-1
CM1IP
U-0
—
R/W-1
R/W-1
LVDIP
R/W-1
R/W-1
OSCFIP
BCL1IP
TMR3IP
CCP2IP
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
-n = Value at POR
bit 7
bit 6
bit 5
OSCFIP: Oscillator Fail Interrupt Priority bit
1= High priority
0= Low priority
CM2IP: Comparator 2 Interrupt Priority bit
1= High priority
0= Low priority
C12IP: Comparator 1 Interrupt Priority bit
1= High priority
0= Low priority
bit 4
bit 3
Unimplemented: Read as ‘0’
BCL1IP: Bus Collision Interrupt Priority bit (MSSP1 module)
1= High priority
0= Low priority
bit 2
bit 1
bit 0
LVDIP: Low-Voltage Detect Interrupt Priority bit
1= High priority
0= Low priority
TMR3IP: TMR3 Overflow Interrupt Priority bit
1= High priority
0= Low priority
CCP2IP: ECCP2 Interrupt Priority bit
1= High priority
0= Low priority
© 2009 Microchip Technology Inc.
DS39778D-page 125
PIC18F87J11 FAMILY
REGISTER 9-12: IPR3: PERIPHERAL INTERRUPT PRIORITY REGISTER 3
R/W-1
R/W-1
R/W-1
RC2IP
R/W-1
TX2IP
R/W-1
R/W-1
R/W-1
R/W-1
SSP2IP
BCL2IP
TMR4IP
CCP5IP
CCP4IP
CCP3IP
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
-n = Value at POR
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
SSP2IP: MSSP2 Interrupt Priority bit
1= High priority
0= Low priority
BCL2IP: Bus Collision Interrupt Priority bit (MSSP2 module)
1= High priority
0= Low priority
RC2IP: EUSART2 Receive Interrupt Priority bit
1= High priority
0= Low priority
TX2IP: EUSART2 Transmit Interrupt Priority bit
1= High priority
0= Low priority
TMR4IE: TMR4 to PR4 Interrupt Priority bit
1= High priority
0= Low priority
CCP5IP: CCP5 Interrupt Priority bit
1= High priority
0= Low priority
CCP4IP: CCP4 Interrupt Priority bit
1= High priority
0= Low priority
CCP3IP: ECCP3 Interrupt Priority bit
1= High priority
0= Low priority
DS39778D-page 126
© 2009 Microchip Technology Inc.
PIC18F87J11 FAMILY
9.5
RCON Register
The RCON register contains bits used to determine the
cause of the last Reset or wake-up from Idle or Sleep
modes. RCON also contains the bit that enables
interrupt priorities (IPEN).
REGISTER 9-13: RCON: RESET CONTROL REGISTER
R/W-0
IPEN
U-0
—
R/W-1
CM
R/W-1
RI
R-1
TO
R-1
PD
R/W-0
POR
R/W-0
BOR
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7
IPEN: Interrupt Priority Enable bit
1= Enable priority levels on interrupts
0= Disable priority levels on interrupts (PIC16CXXX Compatibility mode)
bit 6
bit 5
Unimplemented: Read as ‘0’
CM: Configuration Mismatch Flag bit
For details of bit operation, see Register 4-1.
RI: RESETInstruction Flag bit
bit 4
bit 3
bit 2
bit 1
bit 0
For details of bit operation, see Register 4-1.
TO: Watchdog Timer Time-out Flag bit
For details of bit operation, see Register 4-1.
PD: Power-Down Detection Flag bit
For details of bit operation, see Register 4-1.
POR: Power-on Reset Status bit
For details of bit operation, see Register 4-1.
BOR: Brown-out Reset Status bit
For details of bit operation, see Register 4-1.
© 2009 Microchip Technology Inc.
DS39778D-page 127
PIC18F87J11 FAMILY
9.6
INTx Pin Interrupts
9.7
TMR0 Interrupt
External interrupts on the RB0/INT0, RB1/INT1,
RB2/INT2 and RB3/INT3 pins are edge-triggered. If the
corresponding INTEDGx bit in the INTCON2 register is
set (= 1), the interrupt is triggered by a rising edge; if
the bit is clear, the trigger is on the falling edge. When
a valid edge appears on the RBx/INTx pin, the
corresponding flag bit, INTxIF, is set. This interrupt can
be disabled by clearing the corresponding enable bit,
INTxIE. Flag bit, INTxIF, must be cleared in software in
the Interrupt Service Routine before re-enabling the
interrupt.
In 8-bit mode (which is the default), an overflow in the
TMR0 register (FFh → 00h) will set flag bit, TMR0IF. In
16-bit mode, an overflow in the TMR0H:TMR0L register
pair (FFFFh → 0000h) will set TMR0IF. The interrupt
can be enabled/disabled by setting/clearing enable bit,
TMR0IE (INTCON<5>). Interrupt priority for Timer0 is
determined by the value contained in the interrupt prior-
ity bit, TMR0IP (INTCON2<2>). See Section 12.0
“Timer0 Module” for further details on the Timer0
module.
9.8
PORTB Interrupt-on-Change
All external interrupts (INT0, INT1, INT2 and INT3) can
wake-up the processor from the power-managed
modes if bit INTxIE was set prior to going into the
power-managed modes. If the Global Interrupt Enable
bit, GIE, is set, the processor will branch to the interrupt
vector following wake-up.
An input change on PORTB<7:4> sets flag bit, RBIF
(INTCON<0>). The interrupt can be enabled/disabled
by setting/clearing enable bit, RBIE (INTCON<3>).
Interrupt priority for PORTB interrupt-on-change is
determined by the value contained in the interrupt
priority bit, RBIP (INTCON2<0>).
Interrupt priority for INT1, INT2 and INT3 is determined
by the value contained in the interrupt priority bits,
INT1IP (INTCON3<6>), INT2IP (INTCON3<7>) and
INT3IP (INTCON2<1>). There is no priority bit
associated with INT0. It is always a high-priority
interrupt source.
9.9
Context Saving During Interrupts
During interrupts, the return PC address is saved on
the stack. Additionally, the WREG, STATUS and BSR
registers are saved on the Fast Return Stack. If a fast
return from interrupt is not used (see Section 5.3
“Data Memory Organization”), the user may need to
save the WREG, STATUS and BSR registers on entry
to the Interrupt Service Routine. Depending on the
user’s application, other registers may also need to be
saved. Example 9-1 saves and restores the WREG,
STATUS and BSR registers during an Interrupt Service
Routine.
EXAMPLE 9-1:
SAVING STATUS, WREG AND BSR REGISTERS IN RAM
MOVWF
MOVFF
MOVFF
;
W_TEMP
STATUS, STATUS_TEMP
BSR, BSR_TEMP
; W_TEMP is in virtual bank
; STATUS_TEMP located anywhere
; BSR_TMEP located anywhere
; USER ISR CODE
;
MOVFF
MOVF
MOVFF
BSR_TEMP, BSR
W_TEMP, W
STATUS_TEMP, STATUS
; Restore BSR
; Restore WREG
; Restore STATUS
DS39778D-page 128
© 2009 Microchip Technology Inc.
PIC18F87J11 FAMILY
10.1 I/O Port Pin Capabilities
10.0 I/O PORTS
When developing an application, the capabilities of the
port pins must be considered. Outputs on some pins
have higher output drive strength than others. Similarly,
some pins can tolerate higher than VDD input levels.
Depending on the device selected and features
enabled, there are up to nine ports available. Some
pins of the I/O ports are multiplexed with an alternate
function from the peripheral features on the device. In
general, when a peripheral is enabled, that pin may not
be used as a general purpose I/O pin.
10.1.1
INPUT PINS AND VOLTAGE
CONSIDERATIONS
Each port has three memory-mapped registers for its
operation:
The voltage tolerance of pins used as device inputs is
dependent on the pin’s input function. Pins that are
used as digital only inputs are able to handle DC
voltages up to 5.5V, a level typical for digital logic
circuits. In contrast, pins that also have analog input
functions of any kind (such as A/D and comparator
inputs) can only tolerate voltages up to VDD. Voltage
excursions beyond VDD on these pins should be
avoided.
• TRIS register (Data Direction register)
• PORT register (reads the levels on the pins of the
device)
• LAT register (Output Latch register)
Reading the PORT register reads the current status of
the pins, whereas writing to the PORT register writes to
the Output Latch (LAT) register.
Table 10-1 summarizes the input capabilities. Refer to
Section 27.0 “Electrical Characteristics” for more
details.
Setting a TRIS bit (= 1) makes the corresponding
PORT pin an input (i.e., puts the corresponding output
driver in a high-impedance mode). Clearing a TRIS bit
(= 0) makes the corresponding PORT pin an output
(i.e., puts the contents of the corresponding LAT bit on
the selected pin).
TABLE 10-1: INPUT VOLTAGE LEVELS
Tolerated
Port or Pin
Description
The Output Latch (LAT register) is useful for
read-modify-write operations on the value that the I/O
pins are driving. Read-modify-write operations on the
LAT register read and write the latched output value for
the PORT register.
Input
PORTA<7:0>
PORTC<1:0>
PORTF<6:1>
PORTH<7:4>(1)
PORTB<7:0>
PORTC<7:2>
PORTD<7:0>
PORTE<7:0>
PORTF<7>
VDD
Only VDD input levels
tolerated.
A simplified model of a generic I/O port, without the
interfaces to other peripherals, is shown in Figure 10-1.
5.5V
Tolerates input levels
above VDD, useful for
most standard logic.
FIGURE 10-1:
GENERIC I/O PORT
OPERATION
RD LAT
PORTG<4:0>
PORTH<3:0>(1)
PORTJ<7:0>(1)
Data
Bus
D
Q
WR LAT
or PORT
I/O pin(1)
Note 1: These ports are not available on 64-pin
CK
Data Latch
devices.
D
Q
10.1.2
PIN OUTPUT DRIVE
When used as digital I/O, the output pin drive strengths
vary for groups of pins intended to meet the needs for
a variety of applications. In general, there are three
classes of output pins in terms of drive capability.
WR TRIS
RD TRIS
CK
TRIS Latch
Input
Buffer
PORTB and PORTC, as well as PORTA<7:6>, are
designed to drive higher current loads, such as LEDs.
PORTD, PORTE and PORTJ are capable of driving
digital circuits associated with external memory
devices; they can also drive LEDs, but only those with
smaller current requirements. PORTF, PORTG and
PORTH, along with PORTA<5:0>, have the lowest
drive level, but are capable of driving normal digital
circuit loads with a high input impedance.
Q
D
EN
RD PORT
© 2009 Microchip Technology Inc.
DS39778D-page 129
PIC18F87J11 FAMILY
Table 10-2 summarizes the output capabilities of the
ports. Refer to the “Absolute Maximum Ratings” in
Section 27.0 “Electrical Characteristics” for more
details.
When the open-drain option is required, the output pin
must also be tied through an external pull-up resistor
provided by the user to a higher voltage level, up to 5V
on digital only pins (Figure 10-2). When a digital logic
high signal is output, it is pulled up to the higher voltage
level.
TABLE 10-2: OUTPUT DRIVE LEVELS
Port
Drive
Description
FIGURE 10-2:
USING THE OPEN-DRAIN
OUTPUT (EUSARTx
SHOWN AS EXAMPLE)
PORTA
PORTF
PORTG
PORTH(1)
PORTD
PORTE
PORTJ(1)
PORTB
PORTC
Minimum Intended for indication.
+5V
3.3V
PIC18F87J11
Medium Sufficient drive levels for
external memory interfacing
as well as indication.
3.3V
TXX
VDD
5V
High
Suitable for direct LED drive
levels.
(at logic ‘1’)
Note 1: These ports are not available on 64-pin
devices.
10.1.3
PULL-UP CONFIGURATION
Four of the I/O ports (PORTB, PORTD, PORTE and
PORTJ) implement configurable weak pull-ups on all
pins. These are internal pull-ups that allow floating
digital input signals to be pulled to a consistent level,
without the use of external resistors.
10.1.5
TTL INPUT BUFFER OPTION
Many of the digital I/O ports use Schmitt Trigger (ST)
input buffers. While this form of buffering works well
with many types of input, some applications may
require TTL-level signals to interface with external logic
devices. This is particularly true with the EMB and the
Parallel Master Port (PMP), which are particularly likely
to be interfaced to TTL-level logic or memory devices.
The pull-ups are enabled with a single bit for each of the
ports: RBPU (INTCON2<7>) for PORTB, and RDPU,
REPU and RJPU (PORTG<7:5>) for the other ports.
The inputs for the PMP can be optionally configured for
TTL buffers with the PMPTTL bit in the PADCFG1 reg-
ister (Register 10-4). Setting this bit configures all data
and control input pins for the PMP to use TTL buffers.
By default, these PMP inputs use the port’s ST buffers.
10.1.4
OPEN-DRAIN OUTPUTS
The output pins for several peripherals are also
equipped with a configurable, open-drain output option.
This allows the peripherals to communicate with
external digital logic operating at a higher voltage level,
without the use of level translators.
As with the ODCON registers, the PADCFG1 register
resides in the SFR configuration space; it shares the
same memory address as the TMR2 register.
PADCFG1 is accessed by setting the ADSHR bit
(WDTCON<4>).
The open-drain option is implemented on port pins spe-
cifically associated with the data and clock outputs of
the EUSARTs, the MSSP modules (in SPI mode) and
the CCP and ECCP modules. It is selectively enabled
by setting the open-drain control bit for the correspond-
ing module in the ODCON registers (Register 10-1,
Register 10-2 and Register 10-3). Their configuration
is discussed in more detail with the individual port
where these peripherals are multiplexed.
The ODCON registers all reside in the SFR configuration
space and share the same SFR addresses as the Timer1
registers (see Section 5.3.4.1 “Shared Address SFRs”
for more details). The ODCON registers are accessed by
setting the ADSHR bit (WDTCON<4>).
DS39778D-page 130
© 2009 Microchip Technology Inc.
PIC18F87J11 FAMILY
REGISTER 10-1: ODCON1: PERIPHERAL OPEN-DRAIN CONTROL REGISTER 1
U-0
—
U-0
—
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
CCP5OD
CCP4OD
ECCP3OD
ECCP2OD
ECCP1OD
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7-5
bit 4-3
Unimplemented: Read as ‘0’
CCP5OD:CCP4OD: CCPx Open-Drain Output Enable bits
1= Open-drain output on CCPx pin (Capture/PWM modes) enabled
0= Open-drain output disabled
bit 2-0
ECCP3OD:ECCP1OD: ECCPx Open-Drain Output Enable bits
1= Open-drain output on ECCPx pin (Capture mode) enabled
0= Open-drain output disabled
REGISTER 10-2: ODCON2: PERIPHERAL OPEN-DRAIN CONTROL REGISTER 2
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
R/W-0
U2OD
R/W-0
U1OD
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7-2
bit 1-0
Unimplemented: Read as ‘0’
U2OD:U1OD: EUSARTx Open-Drain Output Enable bits
1= Open-drain output on TXx pin enabled
0= Open-drain output disabled
REGISTER 10-3: ODCON3: PERIPHERAL OPEN-DRAIN CONTROL REGISTER 3
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
R/W-0
R/W-0
SPI2OD
SPI1OD
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7-2
bit 1-0
Unimplemented: Read as ‘0’
SPI2OD:SPI1OD: SPI Open-Drain Output Enable bits
1= Open-drain output on SDOx pin enabled
0= Open-drain output disabled
© 2009 Microchip Technology Inc.
DS39778D-page 131
PIC18F87J11 FAMILY
REGISTER 10-4: PADCFG1: I/O PAD CONFIGURATION CONTROL REGISTER
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
R/W-0
PMPTTL
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7-1
bit 0
Unimplemented: Read as ‘0’
PMPTTL: PMP Module TTL Input Buffer Select bit
1= PMP module uses TTL input buffers
0= PMP module uses Schmitt Trigger input buffers
For INTIO and INTPLL Oscillator modes (FOSC2 Con-
figuration bit is ‘0’), either RA7 or both RA6 and RA7
automatically become available as digital I/O, depend-
ing on the oscillator mode selected. When RA6 is not
configured as a digital I/O, in these cases, it provides a
clock output at FOSC/4. A list of the possible configura-
tions for RA6 and RA7, based on oscillator mode, is
provided in Table 10-3. For these pins, the correspond-
ing PORTA, TRISA and LATA bits are only defined
when the pins are configured as I/O.
10.2 PORTA, TRISA and
LATA Registers
PORTA is an 8-bit wide, bidirectional port. It may func-
tion as a 6-bit or 7-bit port, depending on the oscillator
mode selected. The corresponding Data Direction and
Output Latch registers are TRISA and LATA.
The RA4 pin is multiplexed with the Timer0 module
clock input to become the RA4/T0CKI pin; it is also mul-
tiplexed as the Parallel Master Port data pin (in 80-pin
devices). The other PORTA pins are multiplexed with
the analog VREF+ and VREF- inputs. The operation of
pins, RA<5,3:0>, as A/D Converter inputs is selected
by clearing or setting the appropriate PCFG control bits
in the ANCON0 register.
TABLE 10-3: FUNCTION OF RA7:RA6 IN
INTIO AND INTPLL MODES
Oscillator Mode
(FOSC2:FOSC0 Configuration)
RA6
RA7
Note 1: RA5 (RA5/PMD4/AN4) is multiplexed as
an analog input in all devices and Parallel
Master Port data in 80-pin devices.
INTPLL1 (011)
INTPLL2 (010)
INTIO1 (001)
INTIO2 (000)
CLKO
I/O
I/O
I/O
I/O
I/O
CLKO
I/O
2: RA5 and RA3:RA0 are configured as
analog inputs on any Reset and are read
as ‘0’. RA4 is configured as a digital input.
Legend: CLKO = FOSC/4 clock output;
I/O = digital port.
The RA4/T0CKI pin is a Schmitt Trigger input. All other
PORTA pins have TTL input levels and full CMOS
output drivers.
EXAMPLE 10-1:
INITIALIZING PORTA
; Initialize PORTA by
CLRF
PORTA
; clearing output
; data latches
; Alternate method to
; clear data latches
The TRISA register controls the direction of the PORTA
pins, even when they are being used as analog inputs.
The user must ensure the bits in the TRISA register are
maintained set when using them as analog inputs.
CLRF
BSF
LATA
WDTCON,ADSHR ; Enable write/read to
; the shared SFR
; Configure A/D
; for digital inputs
WDTCON,ADSHR ; Disable write/read
; to the shared SFR
OSC2/CLKO/RA6 and OSC1/CLKI/RA7 normally
serve as the external circuit connections for the
external (primary) oscillator circuit (HS and HSPLL
Oscillator modes), or the external clock input (EC and
ECPLL Oscillator modes). In these cases, RA6 and
RA7 are not available as digital I/O, and their
corresponding TRIS and LAT bits are read as ‘0’.
MOVLW 1Fh
MOVWF ANCON0
BCF
MOVLW 0CFh
MOVWF TRISA
; Value used to
; initialize
; data direction
; Set RA<3:0> as inputs,
; RA<5:4> as outputs
DS39778D-page 132
© 2009 Microchip Technology Inc.
PIC18F87J11 FAMILY
TABLE 10-4: PORTA FUNCTIONS
TRIS
Setting
I/O
Type
Pin Name
RA0/AN0
Function
I/O
Description
RA0
0
1
1
O
I
DIG
TTL
ANA
LATA<0> data output; not affected by analog input.
PORTA<0> data input; disabled when analog input enabled.
AN0
RA1
I
A/D input channel 0. Default input configuration on POR; does not
affect digital output.
RA1/AN1
0
1
1
O
I
DIG
TTL
ANA
LATA<1> data output; not affected by analog input.
PORTA<1> data input; disabled when analog input enabled.
AN1
RA2
I
A/D input channel 1. Default input configuration on POR; does not
affect digital output.
RA2/AN2/VREF-
0
1
1
O
I
DIG
TTL
ANA
LATA<2> data output; not affected by analog input. Disabled when
CVREF output enabled.
PORTA<2> data input. Disabled when analog functions enabled;
disabled when CVREF output enabled.
AN2
I
A/D input channel 2. Default input configuration on POR; not affected
by analog output.
VREF-
RA3
1
0
1
1
1
0
1
x
x
x
0
1
x
x
1
x
x
I
O
I
ANA
DIG
TTL
ANA
ANA
DIG
ST
A/D low reference voltage input.
RA3/AN3/VREF+
LATA<3> data output; not affected by analog input.
PORTA<3> data input; disabled when analog input enabled.
A/D input channel 3. Default input configuration on POR.
A/D high reference voltage input.
AN3
VREF+
RA4
I
I
RA4/PMD5/
T0CKI/
O
I
LATA<4> data output.
PORTA<4> data input; default configuration on POR.
Parallel Master Port data output.
(1)
PMD5
O
I
DIG
TTL
ST
Parallel Master Port data output.
T0CKI
RA5
I
Timer0 clock input.
RA5/PMD4/AN4
O
I
DIG
TTL
DIG
TTL
ANA
ANA
DIG
LATA<5> data output; not affected by analog input.
PORTA<5> data input; disabled when analog input enabled.
Parallel Master Port data output.
(1)
PMD4
O
I
Parallel Master Port data output.
AN4
I
A/D input channel 4. Default configuration on POR.
Main oscillator feedback output connection (HS and HSPLL modes).
OSC2
CLKO
O
O
OSC2/CLKO/
RA6
System cycle clock output, FOSC/4 (EC, ECPLL, INTIO1 and INTPLL1
modes).
RA6
0
1
x
x
0
1
O
I
DIG
TTL
ANA
ANA
DIG
TTL
LATA<6> data output; disabled when FOSC2 Configuration bit is set.
PORTA<6> data input; disabled when FOSC2 Configuration bit is set.
Main oscillator input connection (HS and HSPLL modes).
OSC1
CLKI
RA7
I
OSC1/CLKI/
RA7
I
Main external clock source input (EC and ECPLL modes).
O
I
LATA<7> data output; disabled when FOSC2 Configuration bit is set.
PORTA<7> data input; disabled when FOSC2 Configuration bit is set.
Legend:
O = Output, I = Input, ANA = Analog Signal, DIG = Digital Output, ST = Schmitt Buffer Input,
TTL = TTL Buffer Input, x= Don’t care (TRIS bit does not affect port direction or is overridden for this option).
Note 1: Alternate PMP configuration when the PMPMX Configuration bit is ‘0’; available on 80-pin devices only.
© 2009 Microchip Technology Inc.
DS39778D-page 133
PIC18F87J11 FAMILY
TABLE 10-5: SUMMARY OF REGISTERS ASSOCIATED WITH PORTA
Reset
Values
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
on Page:
PORTA
RA7(1)
LATA7(1) LATA6(1)
TRISA7(1) TRISA6(1) TRISA5
RA6(1)
RA5
RA4
RA3
RA2
RA1
RA0
61
60
60
59
LATA
LATA5
LATA4
TRISA4
PCFG4
LATA3
TRISA3
PCFG3
LATA2
TRISA2
PCFG2
LATA1
TRISA1
PCFG1
LATA0
TRISA0
PCFG0
TRISA
ANCON0(2)
PCFG7 PCFG6
—
Legend: —= unimplemented, read as ‘0’. Shaded cells are not used by PORTA.
Note 1: Implemented only in specific oscillator modes (FOSC2 Configuration bit = 0); otherwise read as ‘0’.
2: Configuration SFR, overlaps with default SFR at this address; available only when WDTCON<4> = 1.
The interrupt-on-change feature is recommended for
10.3 PORTB, TRISB and
LATB Registers
wake-up on key depression operation and operations
where PORTB is only used for the interrupt-on-change
feature. Polling of PORTB is not recommended while
using the interrupt-on-change feature.
PORTB is an 8-bit wide, bidirectional port. The corre-
sponding Data Direction register is TRISB. All pins on
PORTB are digital only and tolerate voltages up to
5.5V.
For 80-pin devices, RB3 can be configured as the
alternate peripheral pin for the ECCP2 module and
Enhanced PWM output 2A by clearing the CCP2MX
Configuration bit. This applies only to 80-pin devices
operating in Extended Microcontroller mode. If the
device is in Microcontroller mode, the alternate
assignment for ECCP2 is RE7. As with other ECCP2
configurations, the user must ensure that the TRISB<3>
bit is set appropriately for the intended operation. Ports,
RB1, RB2, RB3, RB4 and RB5, are multiplexed with
the Parallel Master Port address.
Each of the PORTB pins has a weak internal pull-up. A
single control bit can turn on all the pull-ups. This is
performed by clearing bit, RBPU (INTCON2<7>). The
weak pull-up is automatically turned off when the port
pin is configured as an output. The pull-ups are
disabled on a Power-on Reset.
Four of the PORTB pins (RB7:RB4) have an
interrupt-on-change feature. Only pins configured as
inputs can cause this interrupt to occur (i.e., any
RB7:RB4 pin configured as an output is excluded from
the interrupt-on-change comparison). The input pins (of
RB7:RB4) are compared with the old value latched on
the last read of PORTB. The “mismatch” outputs of
RB7:RB4 are ORed together to generate the RB Port
Change Interrupt with Flag bit, RBIF (INTCON<0>).
EXAMPLE 10-2:
INITIALIZING PORTB
CLRF
PORTB
; Initialize PORTB by
; clearing output
; data latches
CLRF
LATB
0CFh
TRISB
; Alternate method to clear
; output data latches
; Value used to initialize
; data direction
; Set RB<3:0> as inputs
; RB<5:4> as outputs
; RB<7:6> as inputs
MOVLW
MOVWF
This interrupt can wake the device from
power-managed modes. The user, in the Interrupt
Service Routine, can clear the interrupt in the following
manner:
a) Any read or write of PORTB (except with the
MOVFF (ANY), PORTB instruction). This will
end the mismatch condition.
b) Clear flag bit, RBIF.
A mismatch condition will continue to set flag bit, RBIF.
Reading PORTB will end the mismatch condition and
allow flag bit, RBIF, to be cleared.
DS39778D-page 134
© 2009 Microchip Technology Inc.
PIC18F87J11 FAMILY
TABLE 10-6: PORTB FUNCTIONS
TRIS
Setting
I/O
Type
Pin Name
Function
I/O
Description
RB0/INT0/FLT0
RB0
0
1
1
1
0
1
1
x
0
1
1
x
0
1
1
x
0
O
I
DIG LATB<0> data output.
TTL PORTB<0> data input; weak pull-up when RBPU bit is cleared.
INT0
FLT0
RB1
I
ST
ST
External interrupt 0 input.
I
Enhanced PWM Fault input (ECCP1 module); enabled in software.
RB1/INT1/
PMA4
O
I
DIG LATB<1> data output.
TTL PORTB<1> data input; weak pull-up when RBPU bit is cleared.
INT1
PMA4
RB2
I
ST
—
External interrupt 1 input.
O
O
I
Parallel Master Port address out.
RB2/INT2/
PMA3
DIG LATB<2> data output.
TTL PORTB<2> data input; weak pull-up when RBPU bit is cleared.
INT2
PMA3
RB3
I
ST
—
External interrupt 2 input.
O
O
I
Parallel Master Port address out.
RB3/INT3/
PMA2/ECCP2/
P2A
DIG LATB<3> data output.
TTL PORTB<3> data input; weak pull-up when RBPU bit is cleared.
INT3
I
ST
—
External interrupt 3 input.
PMA2
O
O
Parallel Master Port address out.
(1)
ECCP2
DIG ECCP2 compare output and CCP2 PWM output; takes priority over port
data.
1
0
I
ST
ECCP2 capture input.
(1)
P2A
O
DIG ECCP2 Enhanced PWM output, channel A. May be configured for tri-state
during Enhanced PWM shutdown events. Takes priority over port data.
RB4/KBI0/
PMA1
RB4
0
1
O
I
DIG LATB<4> data output.
TTL PORTB<4> data input; weak pull-up when RBPU bit is cleared.
TTL Interrupt-on-pin change.
KBI0
PMA1
RB5
I
x
0
1
O
O
I
—
Parallel Master Port address out.
RB5/KBI1/
PMA0
DIG LATB<5> data output.
TTL PORTB<5> data input; weak pull-up when RBPU bit is cleared.
TTL Interrupt-on-pin change.
KBI1
PMA0
RB6
I
x
0
1
1
x
0
1
1
x
x
O
O
I
—
Parallel Master Port address out.
RB6/KBI2/PGC
RB7/KBI3/PGD
DIG LATB<6> data output.
TTL PORTB<6> data input; weak pull-up when RBPU bit is cleared.
TTL Interrupt-on-pin change.
KBI2
PGC
RB7
I
(2)
I
ST
Serial execution (ICSP™) clock input for ICSP and ICD operation.
O
I
DIG LATB<7> data output.
TTL PORTB<7> data input; weak pull-up when RBPU bit is cleared.
TTL Interrupt-on-pin change.
KBI3
PGD
I
(2)
O
I
DIG Serial execution data output for ICSP and ICD operation.
(2)
ST
Serial execution data input for ICSP and ICD operation.
Legend:
O = Output, I = Input, DIG = Digital Output, ST = Schmitt Buffer Input, TTL = TTL Buffer Input,
x= Don’t care (TRIS bit does not affect port direction or is overridden for this option).
Note 1: Alternate assignment for ECCP2/P2A when the CCP2MX Configuration bit is cleared (Extended Microcontroller mode,
80-pin devices only). Default assignment is RC1.
2: All other pin functions are disabled when ICSP™ or ICD is enabled.
© 2009 Microchip Technology Inc.
DS39778D-page 135
PIC18F87J11 FAMILY
TABLE 10-7: SUMMARY OF REGISTERS ASSOCIATED WITH PORTB
Reset
Values
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
on Page:
PORTB
RB7
RB6
RB5
RB4
RB3
LATB3
TRISB3
RBIE
RB2
RB1
RB0
LATB0
TRISB0
RBIF
61
60
60
57
57
57
LATB
LATB7
TRISB7
LATB6
TRISB6
LATB5
TRISB5
LATB4
TRISB4
INT0IE
LATB2
TRISB2
TMR0IF
LATB1
TRISB1
INT0IF
INT3IP
INT2IF
TRISB
INTCON
INTCON2
INTCON3
GIE/GIEH PEIE/GIEL TMR0IE
RBPU
INTEDG0 INTEDG1 INTEDG2 INTEDG3 TMR0IP
INT1IP INT3IE INT2IE INT1IE INT3IF
RBIP
INT2IP
INT1IF
Legend: Shaded cells are not used by PORTB.
The contents of the TRISC register are affected by
peripheral overrides. Reading TRISC always returns
the current contents, even though a peripheral device
may be overriding one or more of the pins.
10.4 PORTC, TRISC and
LATC Registers
PORTC is an 8-bit wide, bidirectional port. Only
PORTC pins, RC2 through RC7, are digital only pins
and can tolerate input voltages up to 5.5V.
EXAMPLE 10-3:
INITIALIZING PORTC
PORTC is multiplexed with ECCP, MSSP and EUSART
peripheral functions (Table 10-8). The pins have
Schmitt Trigger input buffers. The pins for ECCP, SPI
and EUSART are also configurable for open-drain out-
put whenever these functions are active. Open-drain
configuration is selected by setting the SPIxOD,
ECCPxOD, and UxOD control bits in the ODCON reg-
isters (see Section 10.1.3 “Pull-up Configuration”
for more information).
CLRF
PORTC
; Initialize PORTC by
; clearing output
; data latches
; Alternate method to clear
; output data latches
; Value used to initialize
; data direction
; Set RC<3:0> as inputs
; RC<5:4> as outputs
; RC<7:6> as inputs
CLRF
LATC
0CFh
TRISC
MOVLW
MOVWF
RC1 is normally configured as the default peripheral
pin for the ECCP2 module. Assignment of ECCP2 is
controlled by Configuration bit, CCP2MX (default state,
CCP2MX = 1).
When enabling peripheral functions, care should be
taken in defining TRIS bits for each PORTC pin. Some
peripherals override the TRIS bit to make a pin an output,
while other peripherals override the TRIS bit to make a
pin an input. The user should refer to the corresponding
peripheral section for the correct TRIS bit settings.
Note:
These pins are configured as digital inputs
on any device Reset.
DS39778D-page 136
© 2009 Microchip Technology Inc.
PIC18F87J11 FAMILY
TABLE 10-8: PORTC FUNCTIONS
TRIS
Setting
I/O
Type
Pin Name
Function
I/O
Description
RC0/T1OSO/
T13CKI
RC0
0
1
x
O
I
DIG
ST
LATC<0> data output.
PORTC<0> data input.
T1OSO
O
ANA Timer1 oscillator output; enabled when Timer1 oscillator enabled. Disables
digital I/O.
T13CKI
RC1
1
0
1
x
I
O
I
ST
DIG
ST
Timer1/Timer3 counter input.
LATC<1> data output.
RC1/T1OSI/
ECCP2/P2A
PORTC<1> data input.
T1OSI
I
ANA Timer1 oscillator input; enabled when Timer1 oscillator enabled. Disables
digital I/O.
(1)
ECCP2
0
1
0
O
I
DIG
ST
ECCP2 compare output and ECCP2 PWM output; takes priority over port data.
ECCP2 capture input.
(1)
P2A
O
DIG
ECCP2 Enhanced PWM output, channel A. May be configured for tri-state
during Enhanced PWM shutdown events. Takes priority over port data.
RC2/ECCP1/
P1A
RC2
0
1
0
1
0
O
I
DIG
ST
LATC<2> data output.
PORTC<2> data input.
ECCP1
O
I
DIG
ST
ECCP1 compare output and ECCP1 PWM output; takes priority over port data.
ECCP1 capture input.
P1A
RC3
O
DIG
ECCP1 Enhanced PWM output, channel A. May be configured for tri-state
during Enhanced PWM shutdown events. Takes priority over port data.
RC3/SCK1/
SCL1
0
1
0
1
0
1
0
1
1
1
1
0
1
0
0
1
1
1
O
I
DIG
ST
LATC<3> data output.
PORTC<3> data input.
SCK1
SCL1
RC4
O
I
DIG
ST
SPI clock output (MSSP1 module); takes priority over port data.
SPI clock input (MSSP1 module).
2
O
I
DIG
ST
I C™ clock output (MSSP1 module); takes priority over port data.
2
I C clock input (MSSP1 module); input type depends on module setting.
RC4/SDI1/
SDA1
O
I
DIG
ST
LATC<4> data output.
PORTC<4> data input.
SDI1
I
ST
SPI data input (MSSP1 module).
2
SDA1
O
I
DIG
ST
I C data output (MSSP1 module); takes priority over port data.
2
I C data input (MSSP1 module); input type depends on module setting.
RC5/SDO1
RC5
O
I
DIG
ST
LATC<5> data output.
PORTC<5> data input.
SDO1
RC6
O
O
I
DIG
DIG
ST
SPI data output (MSSP1 module); takes priority over port data.
LATC<6> data output.
RC6/TX1/CK1
PORTC<6> data input.
TX1
CK1
O
O
DIG
DIG
Synchronous serial data output (EUSART1 module); takes priority over port data.
Synchronous serial data input (EUSART1 module). User must configure as
an input.
1
0
1
1
1
I
O
I
ST
DIG
ST
Synchronous serial clock input (EUSART1 module).
LATC<7> data output.
RC7/RX1/DT1
RC7
PORTC<7> data input.
RX1
DT1
I
ST
Asynchronous serial receive data input (EUSART1 module).
O
DIG
Synchronous serial data output (EUSART1 module); takes priority over
port data.
1
I
ST
Synchronous serial data input (EUSART1 module). User must configure as
an input.
Legend:
O = Output, I = Input, ANA = Analog Signal, DIG = Digital Output, ST = Schmitt Buffer Input,
TTL = TTL Buffer Input, x= Don’t care (TRIS bit does not affect port direction or is overridden for this option).
Note 1: Default assignment for ECCP2/P2A when CCP2MX Configuration bit is set.
© 2009 Microchip Technology Inc.
DS39778D-page 137
PIC18F87J11 FAMILY
TABLE 10-9: SUMMARY OF REGISTERS ASSOCIATED WITH PORTC
Reset
Values
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
on Page:
PORTC
RC7
RC6
RC5
RC4
RC3
RC2
RC1
RC0
61
60
60
LATC
LATC7
LATBC6
LATC5
LATCB4
LATC3
LATC2
LATC1
LATC0
TRISC
TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0
10.5 PORTD, TRISD and
LATD Registers
Each of the PORTD pins has a weak internal pull-up.
This is performed by clearing bit RDPU (PORTG<7>).
The weak pull-up is automatically turned off when the
port pin is configured as an output. The pull-ups are
disabled on all device Resets.
PORTD is an 8-bit wide, bidirectional port. All pins on
PORTD are digital only and tolerate voltages up to
5.5V.
All pins on PORTD are implemented with Schmitt
Trigger input buffers. Each pin is individually
configurable as an input or output.
EXAMPLE 10-4:
INITIALIZING PORTD
CLRF
PORTD
; Initialize PORTD by
; clearing output
; data latches
; Alternate method to clear
; output data latches
; Value used to initialize
; data direction
; Set RD<3:0> as inputs
; RD<5:4> as outputs
; RD<7:6> as inputs
Note:
These pins are configured as digital inputs
on any device Reset.
CLRF
LATD
0CFh
TRISD
On 80-pin devices, PORTD is multiplexed with the
system bus as part of the external memory interface.
I/O port and other functions are only available when the
interface is disabled by setting the EBDIS bit
(MEMCON<7>). When the interface is enabled,
PORTD is the low-order byte of the multiplexed
address/data bus (AD7:AD0). The TRISD bits are also
overridden.
MOVLW
MOVWF
PORTD is also multiplexed with the data functions of
the Parallel Master Port data. In this mode, Parallel
Master Port takes priority over the other digital I/O (but
not the external memory bus). This multiplexing is
available when PMPMX = 1. When the Parallel Master
Port is active, the input buffers are TTL. For more
information, refer to Section 11.0 “Parallel Master
Port”.
DS39778D-page 138
© 2009 Microchip Technology Inc.
PIC18F87J11 FAMILY
TABLE 10-10: PORTD FUNCTIONS
TRIS
Setting
I/O
Type
Pin Name
Function
I/O
Description
RD0/AD0/
PMD0
RD0
0
1
x
x
x
x
0
1
x
x
x
x
0
1
x
x
x
x
0
1
x
x
x
x
0
1
x
x
x
x
0
0
1
x
x
x
x
1
1
1
O
I
DIG
ST
LATD<0> data output.
PORTD<0> data input.
(2)
(1)
(1)
(1)
(1)
(1)
AD0
O
I
DIG
TTL
DIG
TTL
DIG
ST
External memory interface, address/data bit 0 output.
(1)
External memory interface, data bit 0 input.
(3)
PMD0
O
I
Parallel Master Port data out.
Parallel Master Port data input.
LATD<1> data output.
RD1/AD1/
PMD1
RD1
O
I
PORTD<1> data input.
(2)
AD1
O
I
DIG
TTL
DIG
TTL
DIG
ST
External memory interface, address/data bit 1 output.
(1)
External memory interface, data bit 1 input.
(3)
PMD1
O
I
Parallel Master Port data out.
Parallel Master Port data input.
LATD<2> data output.
RD2/AD2/
PMD2
RD2
O
I
PORTD<2> data input.
(2)
AD2
O
I
DIG
TTL
DIG
TTL
DIG
ST
External memory interface, address/data bit 2 output.
(1)
External memory interface, data bit 2 input.
(3)
PMD2
O
I
Parallel Master Port data out.
Parallel Master Port data input.
LATD<3> data output.
RD3/AD3/
PMD3
RD3
O
I
PORTD<3> data input.
(2)
AD3
O
I
DIG
TTL
DIG
TTL
DIG
ST
External memory interface, address/data bit 3 output.
(1)
External memory interface, data bit 3 input.
(3)
PMD3
O
I
Parallel Master Port data out.
Parallel Master Port data input.
LATD<4> data output.
RD4/AD4/
PMD4/SDO2
RD4
O
I
PORTD<4> data input.
(2)
AD4
O
I
DIG
TTL
DIG
TTL
DIG
DIG
ST
External memory interface, address/data bit 4 output.
(1)
External memory interface, data bit 4 input.
(3)
PMD4
O
I
Parallel Master Port data out.
Parallel Master Port data input.
SDO2
RD5
O
O
I
SPI data output (MSSP2 module); takes priority over port data.
LATD<5> data output.
RD5/AD5/
PMD5/SDI2/
SDA2
PORTD<5> data input.
(2)
(1)
AD5
O
I
DIG
TTL
DIG
TTL
ST
External memory interface, address/data bit 5 output.
(1)
External memory interface, data bit 5 input.
(3)
PMD5
O
I
Parallel Master Port data out.
Parallel Master Port data input.
SPI data input (MSSP2 module).
SDI2
I
2
SDA2
O
I
DIG
ST
I C™ data output (MSSP2 module); takes priority over port data.
2
I C data input (MSSP2 module); input type depends on module
setting.
Legend:
O = Output, I = Input, DIG = Digital Output, ST = Schmitt Buffer Input, TTL = TTL Buffer Input,
x= Don’t care (TRIS bit does not affect port direction or is overridden for this option).
Note 1: External memory interface I/O takes priority over all other digital and PMP I/O.
2: Available on 80-pin devices only.
3: Default configuration for PMP (PMPMX Configuration bit = 1).
© 2009 Microchip Technology Inc.
DS39778D-page 139
PIC18F87J11 FAMILY
TABLE 10-10: PORTD FUNCTIONS (CONTINUED)
TRIS
Setting
I/O
Type
Pin Name
Function
I/O
Description
RD6/AD6/
PMD6/SCK2/
SCL2
RD6
0
1
x
x
x
x
0
1
0
1
O
I
DIG
ST
LATD<6> data output.
PORTD<6> data input.
(2)
(1)
AD6
O
I
DIG-3 External memory interface, address/data bit 6 output.
(1)
TTL
DIG
TTL
DIG
ST
External memory interface, data bit 6 input.
Parallel Master Port data out.
(3)
PMD6
O
I
Parallel Master Port data input.
SCK2
SCL2
O
I
SPI clock output (MSSP2 module); takes priority over port data.
SPI clock input (MSSP2 module).
2
O
I
DIG
ST
I C™ clock output (MSSP2 module); takes priority over port data.
2
I C clock input (MSSP2 module); input type depends on module
setting.
RD7/AD7/
PMD7/SS2
RD7
0
1
x
x
x
x
x
O
I
DIG
ST
LATD<7> data output.
PORTD<7> data input.
(2)
(1)
AD7
O
I
DIG
TTL
DIG
TTL
TTL
External memory interface, address/data bit 7 output.
(1)
External memory interface, data bit 7 input.
(3)
PMD7
O
I
Parallel Master Port data out.
Parallel Master Port data input.
Slave select input for MSSP2 module.
SS2
I
Legend:
O = Output, I = Input, DIG = Digital Output, ST = Schmitt Buffer Input, TTL = TTL Buffer Input,
x= Don’t care (TRIS bit does not affect port direction or is overridden for this option).
Note 1: External memory interface I/O takes priority over all other digital and PMP I/O.
2: Available on 80-pin devices only.
3: Default configuration for PMP (PMPMX Configuration bit = 1).
TABLE 10-11: SUMMARY OF REGISTERS ASSOCIATED WITH PORTD
Reset
Values
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
on Page:
PORTD
LATD
RD7
RD6
LATD6
TRISD6
REPU
RD5
RD4
LATD4
TRISD4
RG4
RD3
LATD3
TRISD3
RG3
RD2
LATD2
TRISD2
RG2
RD1
LATD1
TRISD1
RG1
RD0
LATD0
TRISD0
RG0
61
60
60
61
LATD7
TRISD7
RDPU
LATD5
TRISD5
RJPU(1)
TRISD
PORTG
Legend: Shaded cells are not used by PORTD.
Note 1: Unimplemented on 64-pin devices, read as ‘0’.
DS39778D-page 140
© 2009 Microchip Technology Inc.
PIC18F87J11 FAMILY
PORTE is also multiplexed with Enhanced PWM
outputs B and C for ECCP1 and ECCP3 and outputs B,
C and D for ECCP2. For all devices, their default
assignments are on PORTE<6:0>. On 80-pin devices,
the multiplexing for the outputs of ECCP1 and ECCP3
is controlled by the ECCPMX Configuration bit.
Clearing this bit reassigns the P1B/P1C and P3B/P3C
outputs to PORTH.
10.6 PORTE, TRISE and
LATE Registers
PORTE is an 8-bit wide, bidirectional port. All pins on
PORTE are digital only and tolerate voltages up to
5.5V.
All pins on PORTE are implemented with Schmitt
Trigger input buffers. Each pin is individually
configurable as an input or output.
For devices operating in Microcontroller mode, pin RE7
can be configured as the alternate peripheral pin for the
ECCP2 module and Enhanced PWM output 2A. This is
done by clearing the CCP2MX Configuration bit.
Note:
These pins are configured as digital inputs
on any device Reset.
On 80-pin devices, PORTE is multiplexed with the
system bus as part of the external memory interface.
I/O port and other functions are only available when the
interface is disabled, by setting the EBDIS bit
(MEMCON<7>). When the interface is enabled,
PORTE is the high-order byte of the multiplexed
address/data bus (AD15:AD8). The TRISE bits are also
overridden.
PORTE is also multiplexed with the Parallel Master
Port address lines. When PMPMX = 0, RE1 and RE0
are multiplexed with the control signals PMWR and
PMRD.
RE3 can also be configured as the Reference Clock
Output (REFO) from the system clock. For further
details, refer to Section 2.6 “Reference Clock
Output”.
Each of the PORTE pins has a weak internal pull-up. A
single control bit can turn off all the pull-ups. This is
performed by clearing bit REPU (PORTG<6>). The
weak pull-up is automatically turned off when the port
pin is configured as an output. The pull-ups are
disabled on any device Reset.
EXAMPLE 10-5:
INITIALIZING PORTE
CLRF
PORTE
; Initialize PORTE by
; clearing output
; data latches
; Alternate method to clear
; output data latches
; Value used to initialize
; data direction
; Set RE<1:0> as inputs
; RE<7:2> as outputs
CLRF
LATE
03h
MOVLW
MOVWF
TRISE
© 2009 Microchip Technology Inc.
DS39778D-page 141
PIC18F87J11 FAMILY
TABLE 10-12: PORTE FUNCTIONS
TRIS
Setting
I/O
Type
Pin Name
Function
I/O
Description
RE0/AD8/
PMRD/P2D
RE0
0
1
x
x
x
x
0
O
I
DIG
ST
LATE<0> data output.
PORTE<0> data input.
(3)
(2)
AD8
O
I
DIG
TTL
DIG
TTL
DIG
External memory interface, address/data bit 8 output.
(2)
External memory interface, data bit 8 input.
(5)
PMRD
O
I
Parallel Master Port read strobe pin.
Parallel Master Port read pin.
P2D
RE1
O
ECCP2 Enhanced PWM output, channel D; takes priority over port
and PMP data. May be configured for tri-state during Enhanced PWM
shutdown events.
RE1/AD9/
PMWR/P2C
0
1
x
x
x
x
0
O
I
DIG
ST
LATE<1> data output.
PORTE<1> data input.
(3)
(2)
AD9
O
I
DIG
TTL
DIG
TTL
DIG
External memory interface, address/data bit 9 output.
(2)
External memory interface, data bit 9 input.
(5)
PMWR
O
I
Parallel Master Port write strobe pin.
Parallel Master Port write pin.
P2C
RE2
O
ECCP2 Enhanced PWM output, channel C; takes priority over port
and PMP data. May be configured for tri-state during Enhanced PWM
shutdown events.
RE2/AD10/
PMBE/P2B
0
1
x
x
x
0
O
I
DIG
ST
LATE<2> data output.
PORTE<2> data input.
(3)
(2)
AD10
O
I
DIG
TTL
DIG
DIG
External memory interface, address/data bit 10 output.
(2)
External memory interface, data bit 10 input.
(5)
PMBE
O
O
Parallel Master Port byte enable.
P2B
ECCP2 Enhanced PWM output, channel B; takes priority over port and
PMP data. May be configured for tri-state during Enhanced PWM
shutdown events.
RE3/AD11/
PMA13/P3C/
REFO
RE3
0
1
x
x
x
0
O
I
DIG
ST
LATE<3> data output.
PORTE<3> data input.
(3)
(2)
AD11
O
I
DIG
TTL
DIG
DIG
External memory interface, address/data bit 11 output.
(2)
External memory interface, data bit 11 input.
PMA13
O
O
Parallel Master Port address.
(1)
P3C
ECCP3 Enhanced PWM output, channel C; takes priority over port
and PMP data. May be configured for tri-state during Enhanced PWM
shutdown events.
REFO
RE4
x
0
1
x
x
x
0
O
O
I
DIG
DIG
ST
Reference output clock.
LATE<4> data output.
PORTE<4> data input.
RE4/AD12/
PMA12/P3B
(3)
(2)
AD12
O
I
DIG
TTL
DIG
DIG
External memory interface, address/data bit 12 output.
(2)
External memory interface, data bit 12 input.
PMA12
O
O
Parallel Master Port address.
(1)
P3B
ECCP3 Enhanced PWM output, channel B; takes priority over port and
PMP data. May be configured for tri-state during Enhanced PWM
shutdown events.
Legend:
O = Output, I = Input, DIG = Digital Output, ST = Schmitt Buffer Input, TTL = TTL Buffer Input,
x= Don’t care (TRIS bit does not affect port direction or is overridden for this option).
Note 1: Default assignments for P1B/P1C and P3B/P3C when ECCPMX Configuration bit is set (80-pin devices only).
2: External memory interface I/O takes priority over all other digital and PMP I/O.
3: Available on 80-pin devices only.
4: Alternate assignment for ECCP2/P2A when ECCP2MX Configuration bit is cleared (all devices in Microcontroller mode).
5: Default configuration for PMP (PMPMX Configuration bit = 1).
DS39778D-page 142
© 2009 Microchip Technology Inc.
PIC18F87J11 FAMILY
TABLE 10-12: PORTE FUNCTIONS (CONTINUED)
TRIS
Setting
I/O
Type
Pin Name
Function
I/O
Description
RE5/AD13/
PMA11/P1C
RE5
0
1
x
x
x
0
O
I
DIG
ST
LATE<5> data output.
PORTE<5> data input.
(3)
(2)
AD13
O
I
DIG
TTL
DIG
DIG
External memory interface, address/data bit 13 output.
(2)
External memory interface, data bit 13 input.
PMA11
O
O
Parallel Master Port address.
(1)
P1C
ECCP1 Enhanced PWM output, channel C; takes priority over port
and PMP data. May be configured for tri-state during Enhanced PWM
shutdown events.
RE6/AD14/
PMA10/P1B
RE6
0
1
x
x
x
0
O
I
DIG
ST
LATE<6> data output.
PORTE<6> data input.
(3)
(2)
AD14
O
I
DIG
TTL
DIG
DIG
External memory interface, address/data bit 14 output.
(2)
External memory interface, data bit 14 input.
PMA10
O
O
Parallel Master Port address.
(1)
P1B
ECCP1 Enhanced PWM output, channel B; takes priority over port and
PMP data. May be configured for tri-state during Enhanced PWM
shutdown events.
RE7/AD15/
PMA9/ECCP2/
P2A
RE7
0
1
x
x
x
0
O
I
DIG
ST
LATE<7> data output.
PORTE<7> data input.
(3)
(2)
AD15
O
I
DIG
TTL
DIG
DIG
External memory interface, address/data bit 15 output.
(2)
External memory interface, data bit 15 input.
PMA9
O
O
Parallel Master Port address.
(4)
ECCP2
ECCP2 compare output and ECCP2 PWM output; takes priority over
port data.
1
0
I
ST
ECCP2 capture input.
(4)
P2A
O
DIG
ECCP2 Enhanced PWM output, channel A; takes priority over port and
PMP data. May be configured for tri-state during Enhanced PWM
shutdown events.
Legend:
O = Output, I = Input, DIG = Digital Output, ST = Schmitt Buffer Input, TTL = TTL Buffer Input,
x= Don’t care (TRIS bit does not affect port direction or is overridden for this option).
Note 1: Default assignments for P1B/P1C and P3B/P3C when ECCPMX Configuration bit is set (80-pin devices only).
2: External memory interface I/O takes priority over all other digital and PMP I/O.
3: Available on 80-pin devices only.
4: Alternate assignment for ECCP2/P2A when ECCP2MX Configuration bit is cleared (all devices in Microcontroller mode).
5: Default configuration for PMP (PMPMX Configuration bit = 1).
TABLE 10-13: SUMMARY OF REGISTERS ASSOCIATED WITH PORTE
Reset
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Values
on Page:
PORTE
LATE
RE7
RE6
RE5
RE4
LATE4
TRISE4
RG4
RE3
LATE3
TRISE3
RG3
RE2
LATE2
TRISE2
RG2
RE1
LATE1
TRISE1
RG1
RE0
LATE0
TRISE0
RG0
61
60
60
61
LATE7
TRISE7
RDPU
LATE6
TRISE6
REPU
LATE5
TRISE5
RJPU(1)
TRISE
PORTG
Legend: Shaded cells are not used by PORTE.
Note 1: Unimplemented on 64-pin devices, read as ‘0’.
© 2009 Microchip Technology Inc.
DS39778D-page 143
PIC18F87J11 FAMILY
When Configuration bit, PMPMX = 0, PORTF is
multiplexed with the Parallel Master Port data. This
multiplexing is available only in 80-pin devices.
10.7 PORTF, LATF and TRISF Registers
PORTF is a 7-bit wide, bidirectional port. Only pin 7 of
PORTF has no analog input; it is the only pin that can
tolerate voltages up to 5.5V.
EXAMPLE 10-6:
INITIALIZING PORTF
All pins on PORTF are implemented with Schmitt
Trigger input buffers. Each pin is individually
configurable as an input or output.
CLRF PORTF
; Initialize PORTF by
; clearing output
; data latches
CLRF LATF
; Alternate method to
; clear output latches
PORTF is multiplexed with analog peripheral functions.
RF1 through RF6 may also be used as analog input
channels for the A/D Converter. All pins may be used as
comparator inputs or outputs by setting the appropriate
bits in the CMCON register. To use RF<6:3> as digital
inputs, it is also necessary to turn off the comparators.
BSF
WDTCON,ADSHR ; Enable write/read to
; the shared SFR
MOVLW C0h
MOVWF ANCON0
MOVLW 0Fh
; make RF1:RF2 digital
;
; make RF<6:3> digital
;
MOVWF ANCON1
Note 1: On device Resets, pins RF6:RF1 are
configured as analog inputs and are read
as ‘0’.
BCF
WDTCON,ADSHR ; Disable write/read to
; the shared SFR
MOVLW CEh
MOVWF TRISF
;
; Set RF5:RF4 as outputs,
; RF<7:6>,<3:1> as inputs
2: To configure PORTF as digital I/O, set the
corresponding bits in ANCON0 and
ANCON1.
DS39778D-page 144
© 2009 Microchip Technology Inc.
PIC18F87J11 FAMILY
TABLE 10-14: PORTF FUNCTIONS
TRIS
Setting
I/O
Type
Pin Name
Function
I/O
Description
RF1/AN6/
C2OUT
RF1
0
1
1
x
0
1
x
1
x
0
1
1
x
0
1
1
x
0
O
I
DIG
ST
LATF<1> data output; not affected by analog input.
PORTF<1> data input; disabled when analog input enabled.
A/D input channel 6. Default configuration on POR.
Comparator 2 output.
AN6
C2OUT
RF2
I
ANA
DIG
DIG
ST
O
O
I
RF2/PMA5/
AN7//C1OUT
LATF<2> data output; not affected by analog input.
PORTF<2> data input; disabled when analog input enabled.
Parallel Master Port address.
PMA5
AN7
O
I
DIG
ANA
DIG
DIG
ST
A/D input channel 7. Default configuration on POR.
Comparator 1 output.
C1OUT
RF3
O
O
I
RF3/AN8/
C2INB
LATF<3> data output; not affected by analog input.
PORTF<3> data input; disabled when analog input enabled.
A/D input channel 8. Default configuration on POR.
Comparator 2 input B.
AN8
C2INB
RF4
I
ANA
ANA
DIG
ST
I
RF4/AN9/
C2INA
O
I
LATF<4> data output; not affected by analog input.
PORTF<4> data input; disabled when analog input enabled.
A/D input channel 9. Default configuration on POR.
Comparator 2 input A.
AN9
C2INA
RF5
I
ANA
ANA
DIG
I
RF5/PMD2/
AN10/C1INB/
CVREF
O
LATF<5> data output; not affected by analog input. Disabled when
CVREF output enabled.
1
I
ST
PORTF<5> data input; disabled when analog input enabled. Disabled
when CVREF output enabled.
(1)
PMD2
x
x
1
O
I
DIG
TTL
ANA
Parallel Master Port data out.
Parallel Master Port data input.
AN10
I
A/D input channel 10 and Comparator C1+ input. Default input
configuration on POR.
C1INB
CVREF
x
x
I
ANA
ANA
Comparator 1 input B.
O
Comparator voltage reference output. Enabling this feature disables
digital I/O.
RF6/PMD1/
AN11/C1INA
RF6
0
1
x
x
1
O
I
DIG
ST
LATF<6> data output; not affected by analog input.
PORTF<6> data input; disabled when analog input enabled.
Parallel Master Port data out.
(1)
PMD1
O
I
DIG
TTL
ANA
Parallel Master Port data input.
AN11
I
A/D input channel 11 and comparator C1- input. Default input
configuration on POR; does not affect digital output.
C1INA
RF7
x
0
1
x
x
1
I
O
I
ANA
DIG
ST
Comparator 1 input A.
RF7/PMD0/
SS1
LATF<7> data output.
PORTF<7> data input.
(1)
PMD0
O
I
DIG
TTL
TTL
Parallel Master Port data out.
Parallel Master Port data input.
Slave select input for MSSP1 module.
SS1
I
Legend:
O = Output, I = Input, ANA = Analog Signal, DIG = Digital Output, ST = Schmitt Buffer Input,
TTL = TTL Buffer Input, x= Don’t care (TRIS bit does not affect port direction or is overridden for this option).
Note 1: Alternate PMP configuration when the PMPMX Configuration bit = 0; available on 80-pin devices only.
© 2009 Microchip Technology Inc.
DS39778D-page 145
PIC18F87J11 FAMILY
TABLE 10-15: SUMMARY OF REGISTERS ASSOCIATED WITH PORTF
Reset
Values
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
on Page:
PORTF
LATF
RF7
RF6
RF5
LATF5
TRISF5
—
RF4
RF3
RF2
RF1
—
—
61
60
60
59
59
LATF7
LATF6
TRISF6
PCFG6
LATF4
TRISF4
PCFG4
LATF3
TRISF3
PCFG3
LATF2
TRISF2
PCFG2
LATF1
TRISF1
PCFG1
PCFG9
TRISF
ANCON0(1) PCFG7
ANCON1(1) PCFG15 PCFG14 PCFG13 PCFG12 PCFG11 PCFG10
TRISF7
—
PCFG0
PCFG8
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PORTF.
Note 1: Configuration SFR, overlaps with default SFR at this address; available only when WDTCON<4> = 1.
10.8 PORTG, TRISG and
Although the port itself is only five bits wide,
PORTG<7:5> bits are still implemented. These are
LATG Registers
used to control the weak pull-ups on the I/O ports asso-
PORTG is a 5-bit wide, bidirectional port. All pins on
ciated with the external memory bus (PORTD, PORTE
PORTG are digital only and tolerate voltages up to
and PORTJ). Setting these bits enables the pull-ups.
5.5V.
Since these are control bits and are not associated with
PORTG is multiplexed with EUSART2 functions
port I/O, the corresponding TRISG and LATG bits are
(Table 10-16). PORTG pins have Schmitt Trigger input
not implemented.
buffers. PORTG is also multiplexed with address and
control functions of the Parallel Master Port.
EXAMPLE 10-7:
INITIALIZING PORTG
When enabling peripheral functions, care should be
taken in defining TRIS bits for each PORTG pin. Some
peripherals override the TRIS bit to make a pin an
output, while other peripherals override the TRIS bit to
make a pin an input. The user should refer to the
corresponding peripheral section for the correct TRIS
bit settings. The pin override value is not loaded into
the TRIS register. This allows read-modify-write of the
TRIS register without concern due to peripheral
overrides.
CLRF
PORTG
; Initialize PORTG by
; clearing output
; data latches
; Alternate method to clear
; output data latches
; Value used to initialize
; data direction
; Set RG1:RG0 as outputs
; RG2 as input
CLRF
LATG
04h
MOVLW
MOVWF
TRISG
; RG4:RG3 as outputs
DS39778D-page 146
© 2009 Microchip Technology Inc.
PIC18F87J11 FAMILY
TABLE 10-16: PORTG FUNCTIONS
TRIS
Setting
I/O
Type
Pin Name
Function
I/O
Description
RG0/PMA8/
ECCP3/P3A
RG0
0
1
x
O
I
DIG
ST
LATG<0> data output.
PORTG<0> data input.
PMA8
O
O
I
DIG
DIG
ST
Parallel Master Port address.
ECCP3
ECCP3 compare and PWM output; takes priority over port data.
ECCP3 capture input.
P3A
RG1
0
O
DIG
ECCP3 Enhanced PWM output, channel A; takes priority over port and
PMP data. May be configured for tri-state during Enhanced PWM
shutdown events.
RG1/PMA7/
TX2/CK2
0
1
x
1
O
I
DIG
ST
LATG<1> data output.
PORTG<1> data input.
Parallel Master Port address.
PMA7
TX2
O
O
DIG
DIG
Synchronous serial data output (EUSART2 module); takes priority over
port data.
CK2
RG2
1
O
DIG
Synchronous serial data input (EUSART2 module). User must configure
as an input.
1
0
1
x
1
1
I
O
I
ST
DIG
ST
Synchronous serial clock input (EUSART2 module).
LATG<2> data output.
RG2/PMA6/
RX2/DT2
PORTG<2> data input.
PMA6
RX2
O
I
DIG
ST
Parallel Master Port address.
Asynchronous serial receive data input (EUSART2 module).
DT2
O
DIG
Synchronous serial data output (EUSART2 module); takes priority over
port data.
1
I
ST
Synchronous serial data input (EUSART2 module). User must configure
as an input.
RG3/PMCS1/
CCP4/P3D
RG3
PMCS1
CCP4
P3D
0
1
x
x
0
1
0
O
I
DIG
ST
LATG<3> data output.
PORTG<3> data input.
O
I
DIG
TTL
DIG
ST
Parallel Master Port address chip select 1
Parallel Master Port address chip select 1 in.
CCP4 compare output and CCP4 PWM output; takes priority over port data.
CCP4 capture input.
O
I
O
DIG
ECCP3 Enhanced PWM output, channel D; takes priority over port and
PMP data. May be configured for tri-state during Enhanced PWM
shutdown events.
RG4/PMCS2/
CCP5/P1D
RG4
0
1
x
0
1
0
O
I
DIG
ST
LATG<4> data output.
PORTG<4> data input.
PMCS2
CCP5
O
O
I
DIG
DIG
ST
Parallel Master Port address chip select 2
CCP5 compare output and CCP5 PWM output; takes priority over port data.
CCP5 capture input.
P1D
O
DIG
ECCP1 Enhanced PWM output, channel D; takes priority over port and
PMP data. May be configured for tri-state during Enhanced PWM
shutdown events.
Legend:
O = Output, I = Input, DIG = Digital Output, ST = Schmitt Buffer Input, TTL = TTL Buffer Input,
x= Don’t care (TRIS bit does not affect port direction or is overridden for this option).
© 2009 Microchip Technology Inc.
DS39778D-page 147
PIC18F87J11 FAMILY
TABLE 10-17: SUMMARY OF REGISTERS ASSOCIATED WITH PORTG
Reset
Values on
Page:
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PORTG
RDPU
—
REPU
—
RJPU(1)
RG4
RG3
RG2
RG1
RG0
61
60
60
LATG
—
—
LATG4
LATG3
LATG2
LATG1
LATG0
TRISG
—
—
TRISG4 TRISG3 TRISG2 TRISG1 TRISG0
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PORTG.
Note 1: Unimplemented on 64-pin devices, read as ‘0’.
10.9 PORTH, LATH and
PORTH can also be configured as the alternate
Enhanced PWM output channels B and C for the
ECCP1 and ECCP3 modules. This is done by clearing
the ECCPMX Configuration bit.
TRISH Registers
Note: PORTH is available only on 80-pin
devices.
PORTH is an 8-bit wide, bidirectional I/O port. PORTH
pins <3:0> are digital only and tolerate voltages up to
5.5V.
EXAMPLE 10-8:
CLRF PORTH
INITIALIZING PORTH
; Initialize PORTH by
; clearing output
; data latches
; Alternate method to
; clear output latches
All pins on PORTH are implemented with Schmitt
Trigger input buffers. Each pin is individually
configurable as an input or output.
CLRF LATH
BSF
WDTCON,ADSHR; Enable write/read to
; the shared SFR
; Configure PORTH as
; digital I/O
WDTCON,ADSHR; Disable write/read to
; the shared SFR
When the external memory interface is enabled, four of
the PORTH pins function as the high-order address
lines for the interface. The address output from the
interface takes priority over other digital I/O. The
corresponding TRISH bits are also overridden. PORTH
pins, RH4 through RH7, are multiplexed with analog
converter inputs. The operation of these pins as analog
inputs is selected by clearing or setting the
corresponding bits in the ANCON1 register. RH2 to
RH6 are multiplexed with the Parallel Master Port and
RH4 to RH6 are multiplexed as comparator inputs.
MOVLW F0h
MOVWF ANCON1
BCF
MOVLW 0CFh
MOVWF TRISH
; Value used to initialize
; data direction
; Set RH<3:0> as inputs
; RH<5:4> as outputs
; RH<7:6> as inputs
DS39778D-page 148
© 2009 Microchip Technology Inc.
PIC18F87J11 FAMILY
TABLE 10-18: PORTH FUNCTIONS
TRIS
Setting
I/O
Type
Pin Name
RH0/A16
Function
I/O
Description
RH0
0
1
x
0
1
x
0
1
x
x
x
0
1
x
x
x
0
1
x
x
O
I
DIG LATH<0> data output.
ST PORTH<0> data input.
A16
O
O
I
DIG External memory interface, address line 16. Takes priority over port data.
DIG LATH<1> data output.
RH1/A17
RH1
ST
PORTH<1> data input.
A17
O
O
I
DIG External memory interface, address line 17. Takes priority over port data.
DIG LATH<2> data output.
RH2/A18/
PMD7
RH2
ST
PORTH<2> data input.
A18
O
O
I
DIG External memory interface, address line 18. Takes priority over port data.
DIG Parallel Master Port data out.
(2)
PMD7
TTL Parallel Master Port data input.
RH3/A19/
PMD6
RH3
O
I
DIG LATH<3> data output.
ST
PORTH<3> data input.
A19
O
O
I
DIG External memory interface, address line 19. Takes priority over port data.
DIG Parallel Master Port data out.
(2)
PMD6
TTL Parallel Master Port data input.
RH4/PMD3/
AN12/P3C/
C2INC
RH4
O
I
DIG LATH<4> data output.
ST
PORTH<4> data input.
(2)
PMD3
I
TTL Parallel Master Port data out.
DIG Parallel Master Port data input.
O
I
AN12
ANA A/D input channel 12. Default input configuration on POR; does not affect
digital output.
(1)
P3C
0
O
DIG ECCP3 Enhanced PWM output, channel C; takes priority over port and PMP
data. May be configured for tri-state during Enhanced PWM shutdown events.
C2INC
RH5
x
0
1
x
I
O
I
ANA Comparator 2 input C.
DIG LATH<5> data output.
RH5/PMBE/
AN13/P3B/
C2IND
ST
PORTH<5> data input.
(2)
PMBE
O
I
DIG Parallel Master Port data byte enable.
AN13
ANA A/D input channel 13. Default input configuration on POR; does not affect
digital output.
(1)
P3B
0
O
DIG ECCP3 Enhanced PWM output, channel B; takes priority over port and PMP
data. May be configured for tri-state during Enhanced PWM shutdown events.
C2IND
RH6
x
0
1
x
x
I
O
I
ANA Comparator 2 input D.
DIG LATH<6> data output.
RH6/PMRD/
AN14/P1C/
C1INC
ST
PORTH<6> data input.
(2)
PMRD
O
I
DIG Parallel Master Port read strobe.
TTL Parallel Master Port read in.
AN14
I
ANA A/D input channel 14. Default input configuration on POR; does not affect
digital output.
(1)
P1C
0
x
O
I
DIG ECCP1 Enhanced PWM output, channel C; takes priority over port and PMP
data. May be configured for tri-state during Enhanced PWM shutdown events.
C1INC
ANA Comparator 1 input C.
Legend:
O = Output, I = Input, ANA = Analog Signal, DIG = Digital Output, ST = Schmitt Buffer Input,
TTL = TTL Buffer Input, x= Don’t care (TRIS bit does not affect port direction or is overridden for this option).
Note 1: Alternate assignments for P1B/P1C and P3B/P3C when the ECCPMX Configuration bit is cleared. Default assignments
are PORTE<6:3>.
2: Alternate PMP configuration when the PMPMX Configuration bit = 0; available on 80-pin devices only.
© 2009 Microchip Technology Inc.
DS39778D-page 149
PIC18F87J11 FAMILY
TABLE 10-18: PORTH FUNCTIONS (CONTINUED)
TRIS
Setting
I/O
Type
Pin Name
Function
I/O
Description
RH7/PMWR/
AN15/P1B
RH7
0
1
x
x
O
I
DIG LATH<7> data output.
ST
PORTH<7> data input.
(2)
PMWR
O
I
DIG Parallel Master Port write strobe.
TTL Parallel Master Port write in.
AN15
I
ANA A/D input channel 15. Default input configuration on POR; does not affect
digital output.
(1)
P1B
0
O
DIG ECCP1 Enhanced PWM output, channel B; takes priority over port and PMP
data. May be configured for tri-state during Enhanced PWM shutdown events.
Legend:
O = Output, I = Input, ANA = Analog Signal, DIG = Digital Output, ST = Schmitt Buffer Input,
TTL = TTL Buffer Input, x= Don’t care (TRIS bit does not affect port direction or is overridden for this option).
Note 1: Alternate assignments for P1B/P1C and P3B/P3C when the ECCPMX Configuration bit is cleared. Default assignments
are PORTE<6:3>.
2: Alternate PMP configuration when the PMPMX Configuration bit = 0; available on 80-pin devices only.
TABLE 10-19: SUMMARY OF REGISTERS ASSOCIATED WITH PORTH
Reset
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Values
on Page:
PORTH(1)
LATH(1)
TRISH(1)
RH7
RH6
RH5
RH4
RH3
RH2
RH1
RH0
60
61
60
59
LATH7
LATH6
LATH5
LATH4
LATH3
LATH2
LATH1
LATH0
TRISH7 TRISH6 TRISH5 TRISH4 TRISH3 TRISH2 TRISH1 TRISH0
ANCON1(2) PCFG15 PCFG14 PCFG13 PCFG12 PCFG11 PCFG10 PCFG9
PCFG8
Legend: Shaded cells are not used by PORTH.
Note 1: Unimplemented on 64-pin devices, read as ‘0’.
2: Configuration SFR, overlaps with default SFR at this address; available only when WDTCON<4> = 1.
DS39778D-page 150
© 2009 Microchip Technology Inc.
PIC18F87J11 FAMILY
Each of the PORTJ pins has a weak internal pull-up. A
single control bit can turn off all the pull-ups. This is
performed by clearing bit RJPU (PORTG<5>). The
weak pull-up is automatically turned off when the port
pin is configured as an output. The pull-ups are
disabled on any device Reset.
10.10 PORTJ, TRISJ and
LATJ Registers
Note: PORTJ is available only on 80-pin devices.
PORTJ is an 8-bit wide, bidirectional port. All pins on
PORTJ are digital only and tolerate voltages up to 5.5V.
All pins on PORTJ are implemented with Schmitt
Trigger input buffers. Each pin is individually
configurable as an input or output.
EXAMPLE 10-9:
INITIALIZING PORTJ
CLRF
PORTJ
; Initialize PORTG by
; clearing output
; data latches
Note:
These pins are configured as digital inputs
on any device Reset.
CLRF
LATJ
0CFh
TRISJ
; Alternate method to clear
; output data latches
; Value used to initialize
; data direction
; Set RJ3:RJ0 as inputs
; RJ5:RJ4 as output
; RJ7:RJ6 as inputs
MOVLW
MOVWF
When the external memory interface is enabled, all of
the PORTJ pins function as control outputs for the
interface. This occurs automatically when the interface
is enabled by clearing the EBDIS control bit
(MEMCON<7>). The TRISJ bits are also overridden.
© 2009 Microchip Technology Inc.
DS39778D-page 151
PIC18F87J11 FAMILY
TABLE 10-20: PORTJ FUNCTIONS
TRIS
Setting
I/O
Type
Pin Name
RJ0/ALE
Function
I/O
Description
RJ0
0
1
x
O
I
DIG
ST
LATJ<0> data output.
PORTJ<0> data input.
ALE
RJ1
O
DIG
External memory interface address latch enable control output; takes
priority over digital I/O.
RJ1/OE
RJ2/WRL
RJ3/WRH
RJ4/BA0
RJ5/CE
RJ6/LB
0
1
x
O
I
DIG
ST
LATJ<1> data output.
PORTJ<1> data input.
OE
O
DIG
External memory interface output enable control output; takes priority
over digital I/O.
RJ2
0
1
x
O
I
DIG
ST
LATJ<2> data output.
PORTJ<2> data input.
WRL
RJ3
O
DIG
External memory bus write low byte control; takes priority over
digital I/O.
0
1
x
O
I
DIG
ST
LATJ<3> data output.
PORTJ<3> data input.
WRH
RJ4
O
DIG
External memory interface write high byte control output; takes priority
over digital I/O.
0
1
x
O
I
DIG
ST
LATJ<4> data output.
PORTJ<4> data input.
BA0
RJ5
O
DIG
External memory interface byte address 0 control output; takes priority
over digital I/O.
0
1
x
O
I
DIG
ST
LATJ<5> data output.
PORTJ<5> data input.
CE
O
DIG
External memory interface chip enable control output; takes priority
over digital I/O.
RJ6
0
1
x
O
I
DIG
ST
LATJ<6> data output.
PORTJ<6> data input.
LB
O
DIG
External memory interface lower byte enable control output; takes
priority over digital I/O.
RJ7/UB
Legend:
RJ7
0
1
x
O
I
DIG
ST
LATJ<7> data output.
PORTJ<7> data input.
UB
O
DIG
External memory interface upper byte enable control output; takes
priority over digital I/O.
O = Output, I = Input, DIG = Digital Output, ST = Schmitt Buffer Input,
x= Don’t care (TRIS bit does not affect port direction or is overridden for this option).
TABLE 10-21: SUMMARY OF REGISTERS ASSOCIATED WITH PORTJ
Reset
Values
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
on Page:
PORTJ(1)
LATJ(1)
TRISJ(1)
RJ7
RJ6
RJ5
RJ4
LATJ4
TRISJ4
RG4
RJ3
LATJ3
TRISJ3
RG3
RJ2
LATJ2
TRISJ2
RG2
RJ1
LATJ1
TRISJ1
RG1
RJ0
LATJ0
TRISJ0
RG0
61
60
60
61
LATJ7
TRISJ7
RDPU
LATJ6
TRISJ6
REPU
LATJ5
TRISJ5
RJPU(1)
PORTG
Legend: Shaded cells are not used by PORTJ.
Note 1: Unimplemented on 64-pin devices, read as ‘0’.
DS39778D-page 152
© 2009 Microchip Technology Inc.
PIC18F87J11 FAMILY
Key features of the PMP module include:
11.0 PARALLEL MASTER PORT
• Up to 16 Programmable Address Lines
• Up to Two Chip Select Lines
The Parallel Master Port module (PMP) is a parallel,
8-bit I/O module, specifically designed to communicate
with a wide variety of parallel devices, such as commu-
nication peripherals, LCDs, external memory devices
and microcontrollers. Because the interface to parallel
peripherals varies significantly, the PMP is highly
configurable. The PMP module can be configured to
serve as either a Parallel Master Port or as a Parallel
Slave Port.
• Programmable Strobe Options
- Individual Read and Write Strobes or;
- Read/Write Strobe with Enable Strobe
• Address Auto-Increment/Auto-Decrement
• Programmable Address/Data Multiplexing
• Programmable Polarity on Control Signals
• Legacy Parallel Slave Port Support
• Enhanced Parallel Slave Support
- Address Support
- 4-Byte Deep, Auto-Incrementing Buffer
• Programmable Wait States
• Selectable Input Voltage Levels
FIGURE 11-1:
PMP MODULE OVERVIEW
Address Bus
Data Bus
Control Lines
PMA<0>
PMALL
PIC18
Parallel Master Port
PMA<1>
PMALH
Up to 16-Bit Address
EEPROM
PMA<13:2>
PMA<14>
PMCS1
PMA<15>
PMCS2
PMBE
FIFO
Buffer
Microcontroller
LCD
PMRD
PMRD/PMWR
PMWR
PMENB
PMD<7:0>
PMA<7:0>
PMA<15:8>
8-Bit Data
© 2009 Microchip Technology Inc.
DS39778D-page 153
PIC18F87J11 FAMILY
The
PMCON
registers
(Register 11-1
and
11.1 Module Registers
Register 11-2) control basic module operations, includ-
ing turning the module on or off. They also configure
address multiplexing and control strobe configuration.
The PMP module has a total of 14 Special Function
Registers for its operation, plus one additional register
to set configuration options. Of these, 8 registers are
used for control and 6 are used for PMP data transfer.
The
PMMODE
registers
(Register 11-3
and
Register 11-4) configure the various Master and Slave
Operating modes, the data width and interrupt
generation.
11.1.1
CONTROL REGISTERS
The eight PMP Control registers are:
The PMEH and PMEL registers (Register 11-5 and
Register 11-6) configure the module’s operation at the
hardware (I/O pin) level.
• PMCONH and PMCONL
• PMMODEH and PMMODEL
• PMSTATL and PMSTATH
• PMEH and PMEL
The
PMSTAT
registers
(Register 11-7
and
Register 11-8) provide status flags for the module’s
input and output buffers, depending on the operating
mode.
REGISTER 11-1: PMCONH: PARALLEL PORT CONTROL HIGH BYTE REGISTER
R/W-0
U-0
—
R/W-0
PSIDL
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
PMPEN
ADRMUX1
ADRMUX0
PTBEEN
PTWREN
PTRDEN
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7
PMPEN: Parallel Master Port Enable bit
1= PMP enabled
0= PMP disabled, no off-chip access performed
bit 6
bit 5
Unimplemented: Read as ‘0’
PSIDL: Stop in Idle Mode bit
1= Discontinue module operation when device enters Idle mode
0= Continue module operation in Idle mode
bit 4-3
ADRMUX1:ADRMUX0: Address/Data Multiplexing Selection bits
11= Reserved
10= All 16 bits of address are multiplexed on PMD<7:0> pins
01= Lower 8 bits of address are multiplexed on PMD<7:0> pins, upper 8 bits are on PMA<15:8>
00= Address and data appear on separate pins
bit 2
bit 1
bit 0
PTBEEN: Byte Enable Port Enable bit (16-bit Master mode)
1= PMBE port enabled
0= PMBE port disabled
PTWREN: Write Enable Strobe Port Enable bit
1= PMWR/PMENB port enabled
0= PMWR/PMENB port disabled
PTRDEN: Read/Write Strobe Port Enable bit
1= PMRD/PMWR port enabled
0= PMRD/PMWR port disabled
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REGISTER 11-2: PMCONL: PARALLEL PORT CONTROL LOW BYTE REGISTER
R/W-0
CSF1
R/W-0
CSF0
R/W-0(1)
ALP
R/W-0(1)
CS2P
R/W-0(1)
CS1P
R/W-0
BEP
R/W-0
WRSP
R/W-0
RDSP
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7-6
CSF1:CSF0: Chip Select Function bits
11= Reserved
10= PMCS1 and PMCS2 function as chip select
01= PMCS2 functions as chip select, PMCS1 used as address bit 14 (PMADDRH address bit 6)
00= PMCS2 and PMCS1 used as address bits 15 and 14 (PMADDRH address bits 7 and 6)
bit 5
bit 4
bit 3
bit 2
bit 1
ALP: Address Latch Polarity bit(1)
1= Active-high (PMALL and PMALH)
0= Active-low (PMALL and PMALH)
CS2P: Chip Select 2 Polarity bit(1)
1= Active-high (PMCS2)
0= Active-low (PMCS2)
CS1P: Chip Select 1 Polarity bit(1)
1= Active-high (PMCS1/PMCS)
0= Active-low (PMCS1/PMCS)
BEP: Byte Enable Polarity bit
1= Byte enable active-high (PMBE)
0= Byte enable active-low (PMBE)
WRSP: Write Strobe Polarity bit
For Slave modes and Master mode 2 (PMMODEH<1:0> = 00, 01, 10):
1= Write strobe active-high (PMWR)
0= Write strobe active-low (PMWR)
For Master mode 1 (PMMODEH<1:0> = 11):
1= Enable strobe active-high (PMENB)
0= Enable strobe active-low (PMENB)
bit 0
RDSP: Read Strobe Polarity bit
For Slave modes and Master mode 2 (PMMODEH<1:0> = 00, 01, 10):
1= Read strobe active-high (PMRD)
0= Read strobe active-low (PMRD)
For Master mode 1 (PMMODEH<1:0> = 11):
1= Read/write strobe active-high (PMRD/PMWR)
0= Read/write strobe active-low (PMRD/PMWR)
Note 1: These bits have no effect when their corresponding pins are used as address lines.
© 2009 Microchip Technology Inc.
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REGISTER 11-3: PMMODEH: PARALLEL PORT MODE HIGH BYTE REGISTER
R-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
BUSY
IRQM1
IRQM0
INCM1
INCM0
MODE16
MODE1
MODE0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
-n = Value at POR
bit 7
BUSY: Busy bit (Master mode only)
1= Port is busy
0= Port is not busy
bit 6-5
IRQM1:IRQM0: Interrupt Request Mode bits
11= Interrupt generated when Read Buffer 3 is read or Write Buffer 3 is written (Buffered PSP mode)
or on a read or write operation when PMA<1:0> = 11(Addressable PSP mode only)
10= No interrupt generated, processor stall activated
01= Interrupt generated at the end of the read/write cycle
00= No interrupt generated
bit 4-3
INCM1:INCM0: Increment Mode bits
11= PSP read and write buffers auto-increment (Legacy PSP mode only)
10= Decrement ADDR<15,13:0> by 1 every read/write cycle
01= Increment ADDR<15,13:0> by 1 every read/write cycle
00= No increment or decrement of address
bit 2
MODE16: 8/16-Bit Mode bit
1= 16-Bit mode: data register is 16 bits, a read or write to the data register invokes two 8-bit transfers
0= 8-Bit mode: data register is 8 bits, a read or write to the data register invokes one 8-bit transfer
bit 1-0
MODE1:MODE0: Parallel Port Mode Select bits
11= Master mode 1 (PMCSx, PMRD/PMWR, PMENB, PMBE, PMA<x:0> and PMD<7:0>)
10= Master mode 2 (PMCSx, PMRD, PMWR, PMBE, PMA<x:0> and PMD<7:0>)
01= Enhanced PSP, control signals (PMRD, PMWR, PMCS, PMD<7:0> and PMA<1:0>)
00= Legacy Parallel Slave Port, control signals (PMRD, PMWR, PMCS and PMD<7:0>)
DS39778D-page 156
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REGISTER 11-4: PMMODEL: PARALLEL PORT MODE LOW BYTE REGISTER
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
WAITB1(1)
WAITB0(1)
WAITM3
WAITM2
WAITM1
WAITM0
WAITE1(1)
WAITE0(1)
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7-6
bit 5-2
bit 1-0
WAITB1:WAITB0: Data Setup to Read/Write Wait State Configuration bits(1)
11= Data wait of 4 TCY; multiplexed address phase of 4 TCY
10= Data wait of 3 TCY; multiplexed address phase of 3 TCY
01= Data wait of 2 TCY; multiplexed address phase of 2 TCY
00= Data wait of 1 TCY; multiplexed address phase of 1 TCY
WAITM3:WAITM0: Read to Byte Enable Strobe Wait State Configuration bits
1111= Wait of additional 15 TCY
...
0001= Wait of additional 1 TCY
0000= No additional wait cycles (operation forced into one TCY)
WAITE1:WAITE0: Data Hold After Strobe Wait State Configuration bits(1)
11= Wait of 4 TCY
10= Wait of 3 TCY
01= Wait of 2 TCY
00= Wait of 1 TCY
Note 1: WAITB and WAITE bits are ignored whenever WAITM3:WAITM0 = 0000.
REGISTER 11-5: PMEH: PARALLEL PORT ENABLE HIGH BYTE REGISTER
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
PTEN15
PTEN14
PTEN13
PTEN12
PTEN11
PTEN10
PTEN9
PTEN8
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
-n = Value at POR
bit 7-6
bit 5-0
PTEN15:PTEN14: PMCSx Strobe Enable bits
1= PMA15 and PMA14 function as either PMA<15:14> or PMCS2 and PMCS1
0= PMA15 and PMA14 function as port I/O
PTEN13:PTEN8: PMP Address Port Enable bits
1= PMA<13:8> function as PMP address lines
0= PMA<13:8> function as port I/O
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REGISTER 11-6: PMEL: PARALLEL PORT ENABLE LOW BYTE REGISTER
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
PTEN7
PTEN6
PTEN5
PTEN4
PTEN3
PTEN2
PTEN1
PTEN0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
-n = Value at POR
bit 7-2
bit 1-0
PTEN7:PTEN2: PMP Address Port Enable bits
1= PMA<7:2> function as PMP address lines
0= PMA<7:2> function as port I/O
PTEN1:PTEN0: PMALH/PMALL Strobe Enable bits
1= PMA1 and PMA0 function as either PMA<1:0> or PMALH and PMALL
0= PMA1 and PMA0 pads functions as port I/O
REGISTER 11-7: PMSTATH: PARALLEL PORT STATUS HIGH BYTE REGISTER
R-0
IBF
R/W-0
IBOV
U-0
—
U-0
—
R-0
R-0
R-0
R-0
IB3F
IB2F
IB1F
IB0F
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7
bit 6
IBF: Input Buffer Full Status bit
1= All writable input buffer registers are full
0= Some or all of the writable input buffer registers are empty
IBOV: Input Buffer Overflow Status bit
1= A write attempt to a full input byte register occurred (must be cleared in software)
0= No overflow occurred
bit 5-4
bit 3-0
Unimplemented: Read as ‘0’
IB3F:IB0F: Input Buffer Status Full bits
1= Input buffer contains data that has not been read (reading buffer will clear this bit)
0= Input buffer does not contain any unread data
DS39778D-page 158
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REGISTER 11-8: PMSTATL: PARALLEL PORT STATUS LOW BYTE REGISTER
R-1
R/W-0
OBUF
U-0
—
U-0
—
R-1
R-1
R-1
R-1
OBE
OB3E
OB2E
OB1E
OB0E
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7
bit 6
OBE: Output Buffer Empty Status bit
1= All readable output buffer registers are empty
0= Some or all of the readable output buffer registers are full
OBUF: Output Buffer Underflow Status bit
1= A read occurred from an empty output byte register (must be cleared in software)
0= No underflow occurred
bit 5-4
bit 3-0
Unimplemented: Read as ‘0’
OBnE: Output Buffer n Status Empty bit
1= Output buffer is empty (writing data to the buffer will clear this bit)
0= Output buffer contains data that has not been transmitted
© 2009 Microchip Technology Inc.
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upper two bits of the register can be used to determine
the operation of chip select signals. If chip select
signals are not used, PMADDR simply functions to hold
the upper 8 bits of the address. The function of the
individual bits in PMADDRH is shown in Register 11-9.
11.1.2
DATA REGISTERS
The PMP module uses 6 registers for transferring data
into and out of the microcontroller. They are arranged
as three pairs to allow the option of 16-bit data
operations:
The PMDOUT2H and PMDOUT2L registers are only
used in buffered Slave modes and serve as a buffer for
outgoing data.
• PMDIN1H and PMDIN1L
• PMDIN2H and PMDIN2L
• PMADDRH/PMDOUT1H and PMADDRL/PMDOUT1L
• PMDOUT2H and PMDOUT2L
11.1.3
PAD CONFIGURATION CONTROL
REGISTER
The PMDIN1 register is used for incoming data in Slave
modes, and both input and output data in Master
modes. The PMDIN2 register is used for buffering input
data in select Slave modes.
In addition to the module level configuration options,
the PMP module can also be configured at the I/O pin
for electrical operation. This option allows users to
select either the normal Schmitt Trigger input buffer on
digital I/O pins shared with the PMP, or use TTL level
compatible buffers instead. Buffer configuration is
controlled by the PMPTTL bit in the PADCFG1 register.
The PMADDRx/PMDOUT1x registers are actually a
single register pair; the name and function is dictated
by the module’s operating mode. In Master modes, the
registers functions as the PMADDRH and PMADDRL
registers, and contain the address of any incoming or
outgoing data. In Slave modes, the registers function
as PMDOUT1H and PMDOUT1L and are used for
outgoing data.
The PADCFG1 register is one of the shared address
SFRs, and has the same address as the TMR2 regis-
ter. PADCFG1 is accessed by setting the ADSHR bit
(WDTCON<4>). Refer to Section 5.3.4.1 “Shared
Address SFRs” for more information.
PMADDRH differs from PMADDRL in that it can also
have limited PMP control functions. When the module
is operating in select Master mode configurations, the
REGISTER 11-9: PMADDRH: PARALLEL PORT ADDRESS REGISTER, HIGH BYTE
(MASTER MODES ONLY)(1)
R/W-0
CS2
R/W-0
CS1
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
ADDR<13:8>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
1 = bit is set
U = Unimplemented bit, read as ‘0’
0 = bit is cleared x = bit is unknown
-n = Value at Reset
bit 7
CS2: Chip Select 2 bit
If PMCON<7:6> = 10 or 01:
1= Chip Select 2 is active
0= Chip Select 2 is inactive
If PMCON<7:6> = 11 or 00:
Bit functions as ADDR<15>.
bit 6
CS1: Chip Select 1 bit
If PMCON<7:6> = 10:
1= Chip Select 1 is active
0= Chip Select 1 is inactive
If PMCON<7:6> = 11 or 0x:
Bit functions as ADDR<14>.
bit 5-0
ADDR13:ADDR0: Destination Address bits
Note 1: In Enhanced Slave mode, PMADDRH functions as PMDOUT1H, one of the Output Data Buffer registers.
DS39778D-page 160
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11.1.4
PMP MULTIPLEXING OPTIONS
(80-PIN DEVICES)
11.2
Slave Port Modes
The primary mode of operation for the module is con-
figured using the MODE1:MODE0 bits in the
PMMODEH register. The setting affects whether the
module acts as a slave or a master and it determines
the usage of the control pins.
By default, the PMP and the external memory bus
multiplex some of their signals to the same I/O pins on
PORTD and PORTE. It is possible that some applica-
tions may require the PMP signals to be located
elsewhere. For these instances, the 80-pin devices can
be configured to multiplex the PMP to different I/O
ports. PMP configuration is determined by the PMPMX
Configuration bit setting; by default, the PMP and EMB
modules share PORTD and PORTE. The optional pin
configuration is shown in Table 11-1.
11.2.1
LEGACY MODE (PSP)
In Legacy mode (PMMODEH<1:0> = 00 and
PMPEN = 1), the module is configured as a Parallel
Slave Port with the associated enabled module pins
dedicated to the module. In this mode, an external
device, such as another microcontroller or micropro-
cessor, can asynchronously read and write data using
the 8-bit data bus (PMD<7:0>), the read (PMRD), write
(PMWR) and chip select (PMCS1) inputs. It acts as a
slave on the bus and responds to the read/write control
signals.
TABLE 11-1: PMP PIN MULTIPLEXING FOR
80-PIN DEVICES
Pin Assignment
PMP Function
PMPMX = 1
PMPMX = 0
Figure 11-2 shows the connection of the Parallel Slave
Port. When chip select is active and a write strobe
occurs (PMCS = 1 and PMWR = 1), the data from
PMD<7:0> is captured into the PMDIN1L register.
PMD0
PMD1
PMD2
PMD3
PMD4
PMD5
PMD6
PMD7
PMBE
PMWR
PMRD
PORTD<0>
PORTD<1>
PORTD<2>
PORTD<3>
PORTD<4>
PORTD<5>
PORTD<6>
PORTD<7>
PORTE<2>
PORTE<1>
PORTE<0>
PORTF<7>
PORTF<6>
PORTF<5>
PORTH<4>
PORTA<5>
PORTA<4>
PORTH<3>
PORTH<2>
PORTH<5>
PORTH<7>
PORTH<6>
FIGURE 11-2:
LEGACY PARALLEL SLAVE PORT EXAMPLE
Address Bus
Data Bus
Master
PMD<7:0>
PIC18 Slave
PMD<7:0>
Control Lines
PMCS
PMRD
PMWR
PMCS1
PMRD
PMWR
© 2009 Microchip Technology Inc.
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11.2.1.1
WRITE TO SLAVE PORT
11.2.1.2
READ FROM SLAVE PORT
When chip select is active and a write strobe occurs
(PMCS = 1and PMWR = 1), the data from PMD<7:0>
is captured into the PMDIN1L register. The PMPIF and
IBF flag bits are set when the write ends. The timing for
the control signals in Write mode is shown in
Figure 11-3. The polarity of the control signals are
configurable.
When chip select is active and a read strobe occurs
(PMCS = 1 and PMRD = 1), the data from the
PMDOUTL1 register (PMDOUTL1<7:0>) is presented
onto PMD<7:0>.The timing for the control signals in
Read mode is shown in Figure 11-4.
FIGURE 11-3:
PARALLEL SLAVE PORT WRITE WAVEFORMS
|
|
|
|
|
|
|
Q4
|
Q1
|
Q2
|
Q3
|
Q4
PMCS1
PMWR
PMRD
PMD<7:0>
IBF
OBE
PMPIF
FIGURE 11-4:
PARALLEL SLAVE PORT READ WAVEFORMS
|
|
|
|
|
|
|
Q4
|
Q1
|
Q2
|
Q3
|
Q4
PMCS1
PMWR
PMRD
PMD<7:0>
IBF
OBE
PMPIF
DS39778D-page 162
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is generated, and the Buffer Overflow flag bit OBUF is
set. If all 4 OBxE status bits are set, then the Output
Buffer Empty flag (OBE) will also be set.
11.2.2
BUFFERED PARALLEL SLAVE
PORT MODE
Buffered Parallel Slave Port mode is functionally iden-
tical to the Legacy Parallel Slave Port mode with one
exception: the implementation of 4-level read and write
buffers. Buffered PSP mode is enabled by setting the
INCM bits in the PMMODE register. If the INCM<1:0>
bits are set to ‘11’, the PMP module will act as the
Buffered Parallel Slave Port.
11.2.2.2
WRITE TO SLAVE PORT
For write operations, the data is be stored sequentially,
starting with Buffer 0 (PMDIN1L<7:0>) and ending with
Buffer 3 (PMDIN2H<7:0). As with read operations, the
module maintains an internal pointer to the buffer that
is to be written next.
When the Buffered mode is active, the
PMDIN1L,PMDIN1H, PMDIN2L and PMDIN2H regis-
ters become the write buffers and the PMDOUT1L,
PMDOUT1H, PMDOUT2L and PMDOUT2H registers
become the read buffers. Buffers are numbered 0
through 3, starting with the lower byte of PMDIN1L to
PMDIN2H as the read buffers, and PMDOUT1L to
PMDOUT2H as the write buffers.
The input buffers have their own write status bits, IBxF
in the PMSTATH register. The bit is set when the buffer
contains unread incoming data, and cleared when the
data has been read. The flag bit is set on the write
strobe. If a write occurs on a buffer when its associated
IBxF bit is set, the Buffer Overflow flag, IBOV, is set;
any incoming data in the buffer will be lost. If all 4 IBxF
flags are set, the Input Buffer Full Flag (IBF) is set.
11.2.2.1
READ FROM SLAVE PORT
In Buffered Slave mode, the module can be configured
to generate an interrupt on every read or write strobe
(IRQM1:IRQM0 = 01). It can be configured to generate
an interrupt on a read from Read Buffer 3 or a write to
Write Buffer 3, which is essentially an interrupt every
fourth read or write strobe (RQM1:IRQM0 = 11). When
interrupting every fourth byte for input data, all input
buffer registers should be read to clear the IBxF flags.
If these flags are not cleared, then their is a risk of
hitting an overflow condition.
For read operations, the bytes will be sent out sequen-
tially, starting with Buffer 0 (PMDOUT1L<7:0>) and
ending with Buffer 3 (PMDOUT2H<7:0>) for every read
strobe. The module maintains an internal pointer to
keep track of which buffer is to be read. Each of the buf-
fers has a corresponding read status bit, OBxE, in the
PMSTATL register. This bit is cleared when a buffer
contains data that has not been written to the bus, and
is set when data is written to the bus. If the current buf-
fer location being read from is empty, a buffer underflow
FIGURE 11-5:
PARALLEL MASTER/SLAVE CONNECTION BUFFERED EXAMPLE
PIC18 Slave
Master
Write
Address
Pointer
Read
Address
Pointer
PMD<7:0>
PMD<7:0>
PMDOUT1L (0)
PMDOUT1H (1)
PMDOUT2L (2)
PMDOUT2H (3)
PMDIN1L (0)
PMDIN1H (1)
PMDIN2L (2)
PMDIN2H (3)
PMCS1
PMRD
PMWR
PMCS
PMRD
PMWR
Data Bus
Control Lines
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11.2.3
ADDRESSABLE PARALLEL SLAVE
PORT MODE
TABLE 11-2: SLAVE MODE BUFFER
ADDRESSING
In the Addressable Parallel Slave Port mode
(PMMODEH<1:0> = 01), the module is configured with
two extra inputs, PMA<1:0>, which are the address
lines 1 and 0. This makes the 4-byte buffer space
directly addressable as fixed pairs of read and write
buffers. As with Buffered Legacy mode, data is output
from PMDOUT1L, PMDOUT1H, PMDOUT2L and
PMDOUT2H, and is read in PMDIN1L, PMDIN1H,
PMDIN2L and PMDIN2H. Table 11-2 shows the buffer
addressing for the incoming address to the input and
output registers.
PMADDR Output Register
Input Register
<1:0>
(Buffer)
(Buffer)
00
01
10
11
PMDOUT1L (0)
PMDOUT1H (1)
PMDOUT2L (2)
PMDOUT2H (3)
PMDIN1L (0)
PMDIN1H (1)
PMDIN2L (2)
PMDIN2H (3)
FIGURE 11-6:
PARALLEL MASTER/SLAVE CONNECTION ADDRESSED BUFFER EXAMPLE
PIC18F Slave
Master
PMA<1:0>
PMA<1:0>
Write
Address
Decode
Read
Address
Decode
PMD<7:0>
PMD<7:0>
PMDOUT1L (0)
PMDOUT1H (1)
PMDOUT2L (2)
PMDOUT2H (3)
PMDIN1L (0)
PMDIN1H (1)
PMDIN2L (2)
PMDIN2H (3)
PMCS1
PMRD
PMWR
PMCS
PMRD
PMWR
Address Bus
Data Bus
Control Lines
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When an output buffer is read, the corresponding
OBxE bit is set. The OBE flag bit is set when all the buf-
fers are empty. If any buffer is already empty (OBxE =
1), the next read to that buffer will generate an OBUF
event.
11.2.3.1
READ FROM SLAVE PORT
When chip select is active and a read strobe occurs
(PMCS = 1and PMRD = 1), the data from one of the
four output bytes is presented onto PMD<7:0>. Which
byte is read depends on the 2-bit address placed on
ADDR<1:0>. Table 11-2 shows the corresponding
output registers and their associated address.
FIGURE 11-7:
PARALLEL SLAVE PORT READ WAVEFORMS
Q1
|
Q2
|
Q3
|
Q4
|
Q1
|
Q2
|
Q3
|
Q4
|
Q1
|
Q2
|
Q3
|
Q4
PMCS
PMWR
PMRD
PMD<7:0>
PMA<1:0>
OBE
PMPIF
When an input buffer is written, the corresponding IBxF
bit is set. The IBF flag bit is set when all the buffers are
written. If any buffer is already written (IBxF = 1), the
next write strobe to that buffer will generate an OBUF
event and the byte will be discarded.
11.2.3.2
WRITE TO SLAVE PORT
When chip select is active and a write strobe occurs
(PMCS = 1and PMWR = 1), the data from PMD<7:0>
is captured into one of the four input buffer bytes.
Which byte is written depends on the 2-bit address
placed on ADDRL<1:0>. Table 11-2 shows the corre-
sponding input registers and their associated address.
FIGURE 11-8:
PARALLEL SLAVE PORT WRITE WAVEFORMS
Q1
|
Q2
|
Q3
|
Q4
|
Q1
|
Q2
|
Q3
|
Q4
|
Q1
|
Q2
|
Q3
|
Q4
PMCS
PMWR
PMRD
PMD<7:0>
PMA<1:0>
IBF
PMPIF
© 2009 Microchip Technology Inc.
DS39778D-page 165
PIC18F87J11 FAMILY
All control signals (PMRD, PMWR, PMBE, PMENB,
PMAL and PMCSx) can be individually configured as
either positive or negative polarity. Configuration is
controlled by separate bits in the PMCONL register.
Note that the polarity of control signals that share the
same output pin (for example, PMWR and PMENB) are
controlled by the same bit; the configuration depends
on which Master Port mode is being used.
11.3 Master Port Modes
In its Master modes, the PMP module provides an 8-bit
data bus, up to 16 bits of address, and all the necessary
control signals to operate a variety of external parallel
devices, such as memory devices, peripherals and
slave microcontrollers. To use the PMP as a master,
the module must be enabled (PMPEN = 1) and the
mode must be set to one of the two possible Master
modes (PMMODEH<1:0> = 10or 11).
11.3.3
DATA WIDTH
Because there are a number of parallel devices with a
variety of control methods, the PMP module is
designed to be extremely flexible to accommodate a
range of configurations. Some of these features
include:
The PMP supports data widths of both 8 and 16 bits.
The data width is selected by the MODE16 bit
(PMMODEH<2>). Because the data path into and out
of the module is only 8 bits wide, 16-bit operations are
always handled in a multiplexed fashion, with the Least
Significant Byte of data being presented first. To differ-
entiate data bytes, the Byte Enable (PMBE) control
strobe is used to signal when the Most Significant Byte
of data is being presented on the data lines.
• 8 and 16-Bit Data modes on an 8-bit data bus
• Configurable address/data multiplexing
• Up to two chip select lines
• Up to 16 selectable address lines
11.3.4
ADDRESS MULTIPLEXING
• Address auto-increment and auto-decrement
• Selectable polarity on all control lines
In either of the Master modes (PMMODEH<1:0> = 1x),
the user can configure the address bus to be multiplexed
together with the data bus. This is accomplished using
the ADRMUX1:ADRMUX0 bits (PMCONH<4:3>). There
are three address multiplexing modes available; typical
pinout configurations for these modes are shown in
Figure 11-9, Figure 11-10 and Figure 11-11.
• Configurable wait states at different stages of the
read/write cycle
11.3.1
PMP AND I/O PIN CONTROL
Multiple control bits are used to configure the presence
or absence of control and address signals in the mod-
ule. These bits are PTBEEN, PTWREN, PTRDEN, and
PTEN<15:0>. They give the user the ability to conserve
pins for other functions and allow flexibility to control
the external address. When any one of these bits is set,
the associated function is present on its associated pin;
when clear, the associated pin reverts to its defined I/O
port function.
In Demultiplexed mode (PMCONH<4:3> = 00), data
and address information are completely separated.
Data bits are presented on PMD<7:0>, and address
bits are presented on PMADDRH<7:0> and
PMADDRL<7:0>.
In Partially Multiplexed mode (PMCONH<4:3> = 01),
the lower eight bits of the address are multiplexed with
the data pins on PMD<7:0>. The upper eight bits of
address are unaffected and are presented on
PMADDRH<7:0>. The PMA0 pin is used as an address
latch and presents the Address Latch Low (PMALL)
enable strobe. The read and write sequences are
extended by a complete CPU cycle during which the
address is presented on the PMD<7:0> pins.
Setting a PTEN bit will enable the associated pin as an
address pin and drive the corresponding data con-
tained in the PMADDR register. Clearing the PTENx bit
will force the pin to revert to its original I/O function.
For the pins configured as chip select (PMCS1 or
PMCS2) with the corresponding PTENx bit set, chip
select pins drive inactive data (with polarity defined by
the CS1P and CS2P bits) when a read or write opera-
tion is not being performed. The PTEN0 and PTEN1
bits also control the PMALL and PMALH signals. When
multiplexing is used, the associated address latch
signals should be enabled.
In Fully Multiplexed mode (PMCONH<4:3> = 10), the
entire 16 bits of the address are multiplexed with the
data pins on PMD<7:0>. The PMA0 and PMA1 pins are
used to present Address Latch Low (PMALL) enable
and Address Latch High (PMALH) enable strobes,
respectively. The read and write sequences are
extended by two complete CPU cycles. During the first
cycle, the lower eight bits of the address are presented
on the PMD<7:0> pins with the PMALL strobe active.
During the second cycle, the upper eight bits of the
address are presented on the PMD<7:0> pins with the
PMALH strobe active. In the event the upper address
bits are configured as chip select pins, the
corresponding address bits are automatically forced
to ‘0’.
11.3.2
READ/WRITE CONTROL
The PMP module supports two distinct read/write
_signaling methods. In Master mode 1, read and write
strobes are combined into a single control line,
PMRD/PMWR. A second control line, PMENB, deter-
mines when a read or write action is to be taken. In
Master mode 2, separate read and write strobes
(PMRD and PMWR) are supplied on separate pins.
DS39778D-page 166
© 2009 Microchip Technology Inc.
PIC18F87J11 FAMILY
FIGURE 11-9:
FIGURE 11-10:
FIGURE 11-11:
DEMULTIPLEXED ADDRESSING MODE (SEPARATE READ AND WRITE
STROBES, TWO CHIP SELECTS)
PIC18F
PMA<13:0>
PMD<7:0>
PMCS1
PMCS2
PMRD
Address Bus
Data Bus
Control Lines
PMWR
PARTIALLY MULTIPLEXED ADDRESSING MODE (SEPARATE READ AND
WRITE STROBES, TWO CHIP SELECTS)
PIC18F
PMA<13:8>
PMD<7:0>
PMA<7:0>
PMCS1
PMCS2
PMALL
PMRD
Address Bus
Multiplexed
Data and
Address Bus
Control Lines
PMWR
FULLY MULTIPLEXED ADDRESSING MODE (SEPARATE READ AND WRITE
STROBES, TWO CHIP SELECTS)
PMD<7:0>
PMA<13:8>
PIC18F
PMCS1
PMCS2
PMALL
PMALH
PMRD
PMWR
Multiplexed
Data and
Address Bus
Control Lines
© 2009 Microchip Technology Inc.
DS39778D-page 167
PIC18F87J11 FAMILY
If the 16-bit mode is enabled (MODE16 = 1), the read
of the low byte of the PMDIN1L register will initiate two
bus reads. The first read data byte is placed into the
PMDIN1L register, and the second read data is placed
into the PMDIN1H.
11.3.5
CHIP SELECT FEATURES
Up to two chip select lines, PMCS1 and PMCS2, are
available for the Master modes of the PMP. The two
chip select lines are multiplexed with the Most Signifi-
cant bits of the address bus (PMADDRH<6> and
PMADDRH<7>). When a pin is configured as a chip
select, it is not included in any address
auto-increment/decrement. The function of the chip
select signals is configured using the chip select
function bits (PMCONL <7:6>).
Note that the read data obtained from the PMDIN1L
register is actually the read value from the previous
read operation. Hence, the first user read will be a
dummy read to initiate the first bus read and fill the read
register. Also, the requested read value will not be
ready until after the BUSY bit is observed low. Thus, in
a back-to-back read operation, the data read from the
register will be the same for both reads. The next read
of the register will yield the new value.
11.3.6
AUTO-INCREMENT/DECREMENT
While the module is operating in one of the Master
modes, the INCM bits (PMMODEH<3:4>) control the
behavior of the address value. The address can be
made to automatically increment or decrement after
each read and write operation. The address increments
once each operation is completed and the BUSY bit
goes to ‘0’. If the chip select signals are disabled and
configured as address bits, the bits will participate in
the increment and decrement operations; otherwise,
the CS2 and CS1 bit values will be unaffected.
11.3.9
WRITE OPERATION
To perform a write onto the parallel bus, the user writes
to the PMDIN1L register. This causes the module to
first output the desired values on the chip select lines
and the address bus. The write data from the PMDIN1L
register is placed onto the PMD<7:0> data bus. Then
the write line (PMWR) is strobed. If the 16-bit mode is
enabled (MODE16 = 1), the write to the PMDIN1L reg-
ister will initiate two bus writes. First write will consist of
the data contained in PMDIN1L and the second write
will contain the PMDIN1H.
11.3.7
WAIT STATES
In Master mode, the user has control over the duration
of the read, write and address cycles by configuring the
module wait states. Three portions of the cycle, the
beginning, middle, and end, are configured using the
corresponding WAITBx, WAITMx and WAITEx bits in
the PMMODEL register.
11.3.10 PARALLEL MASTER PORT STATUS
11.3.10.1 The BUSY Bit
In addition to the PMP interrupt, a BUSY bit is provided
to indicate the status of the module. This bit is only
used in Master mode. While any read or write operation
is in progress, the BUSY bit is set for all but the very last
CPU cycle of the operation. In effect, if a single-cycle
read or write operation is requested, the BUSY bit will
never be active. This allows back-to-back transfers.
While the bit is set, any request by the user to initiate a
new operation will be ignored (i.e., writing or reading
the lower byte of the PMDIN1L register will not initiate
either a read nor a write).
The WAITB1:WAITB0 bits (PMMODEL<7:6>) set the
number of wait cycles for the data setup prior to the
PMRD/PMWT strobe in Mode 10, or prior to the
PMENB strobe in Mode 11. The WAITM3:WAITM0 bits
(PMMODEL<5:2>) set the number of wait cycles for the
PMRD/PMWT strobe in Mode 10, or for the PMENB
strobe in Mode 11. When this wait state setting is 0,
then WAITB and WAITE have no effect. The
WAITE1:WAITE0 bits (PMMODEL<1:0>) define the
number of wait cycles for the data hold time after the
PMRD/PMWT strobe in Mode 10, or after the PMENB
strobe in Mode 11.
11.3.10.2 INTERRUPTS
When the PMP module interrupt is enabled for Master
mode, the module will interrupt on every completed
read or write cycle; otherwise, the BUSY bit is available
to query the status of the module.
11.3.8
READ OPERATION
To perform a read on the Parallel Master Port, the user
reads the PMDIN1L register. This causes the PMP to
output the desired values on the chip select lines and
the address bus. Then the read line (PMRD) is strobed.
The read data is placed into the PMDIN1L register.
DS39778D-page 168
© 2009 Microchip Technology Inc.
PIC18F87J11 FAMILY
11.3.11
MASTER MODE TIMING
This section contains a number of timing examples that
represent the common Master mode configuration
options. These options vary from 8-bit to 16-bit data,
fully demultiplexed to fully multiplexed address, as well
as wait states.
FIGURE 11-12:
READ AND WRITE TIMING, 8-BIT DATA, DEMULTIPLEXED ADDRESS
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
PMCS2
PMCS1
PMD<7:0>
PMA<13:0>
PMWR
PMRD
PMPIF
BUSY
FIGURE 11-13:
PMCS2
READ TIMING, 8-BIT DATA, PARTIALLY MULTIPLEXED ADDRESS
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
PMCS1
Data
Address<7:0>
PMD<7:0>
PMA<13:8>
PMWR
PMRD
PMALL
PMPIF
BUSY
© 2009 Microchip Technology Inc.
DS39778D-page 169
PIC18F87J11 FAMILY
FIGURE 11-14:
READ TIMING, 8-BIT DATA, WAIT STATES ENABLED,
PARTIALLY MULTIPLEXED ADDRESS
Q1- - - Q1- - - Q1- - - Q1- - - Q1- - - Q1- - - Q1- - - Q1- - - Q1- - - Q1- - - Q1- - - Q1- - - Q1- - - Q1- - -
PMCS2
PMCS1
PMD<7:0>
PMA<13:8>
PMRD
Address<7:0>
Data
PMWR
PMALL
PMPIF
BUSY
WAITB<1:0> = 01
WAITE<1:0> = 00
WAITM<3:0> = 0010
FIGURE 11-15:
WRITE TIMING, 8-BIT DATA, PARTIALLY MULTIPLEXED ADDRESS
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
PMCS2
PMCS1
Address<7:0>
Data
PMD<7:0>
PMA<13:8>
PMWR
PMRD
PMALL
PMPIF
BUSY
FIGURE 11-16:
WRITE TIMING, 8-BIT DATA, WAIT STATES ENABLED,
PARTIALLY MULTIPLEXED ADDRESS
Q1- - - Q1- - - Q1- - - Q1- - - Q1- - - Q1- - - Q1- - - Q1- - - Q1- - - Q1- - - Q1- - - Q1- - - Q1- - - Q1- - -
PMCS2
PMCS1
Address<7:0>
Data
PMD<7:0>
PMA<13:8>
PMWR
PMRD
PMALL
PMPIF
BUSY
WAITB<1:0> = 01
WAITE<1:0> = 00
WAITM<3:0> = 0010
DS39778D-page 170
© 2009 Microchip Technology Inc.
PIC18F87J11 FAMILY
FIGURE 11-17:
READ TIMING, 8-BIT DATA, PARTIALLY MULTIPLEXED ADDRESS,
ENABLE STROBE
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
PMCS2
PMCS1
PMD<7:0>
Address<7:0>
Data
PMA<13:8>
PMRD/PMWR
PMENB
PMALL
PMPIF
BUSY
FIGURE 11-18:
WRITE TIMING, 8-BIT DATA, PARTIALLY MULTIPLEXED ADDRESS,
ENABLE STROBE
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
PMCS2
PMCS1
Address<7:0>
Data
PMD<7:0>
PMA<13:8>
PMRD/PMWR
PMENB
PMALL
PMPIF
BUSY
FIGURE 11-19:
READ TIMING, 8-BIT DATA, FULLY MULTIPLEXED 16-BIT ADDRESS
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
PMCS2
PMCS1
Address<7:0>
Address<15:8>
Data
PMD<7:0>
PMWR
PMRD
PMALL
PMALH
PMPIF
BUSY
© 2009 Microchip Technology Inc.
DS39778D-page 171
PIC18F87J11 FAMILY
FIGURE 11-20:
WRITE TIMING, 8-BIT DATA, FULLY MULTIPLEXED 16-BIT ADDRESS
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
PMCS2
PMCS1
PMD<7:0>
PMWR
Address<7:0>
Address<15:8>
Data
PMRD
PMALL
PMALH
PMPIF
BUSY
FIGURE 11-21:
READ TIMING, 16-BIT DATA, DEMULTIPLEXED ADDRESS
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
PMCS2
PMCS1
LSB
MSB
PMD<7:0>
PMA<13:0>
PMWR
PMRD
PMBE
PMPIF
BUSY
FIGURE 11-22:
WRITE TIMING, 16-BIT DATA, DEMULTIPLEXED ADDRESS
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
PMCS2
PMCS1
MSB
LSB
PMD<7:0>
PMA<13:0>
PMWR
PMRD
PMBE
PMPIF
BUSY
DS39778D-page 172
© 2009 Microchip Technology Inc.
PIC18F87J11 FAMILY
FIGURE 11-23:
READ TIMING, 16-BIT MULTIPLEXED DATA,
PARTIALLY MULTIPLEXED ADDRESS
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
PMCS2
PMCS1
Address<7:0>
LSB
MSB
PMD<7:0>
PMA<13:8>
PMWR
PMRD
PMBE
PMALL
PMPIF
BUSY
FIGURE 11-24:
WRITE TIMING, 16-BIT MULTIPLEXED DATA,
PARTIALLY MULTIPLEXED ADDRESS
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
PMCS2
PMCS1
Address<7:0>
LSB
MSB
PMD<7:0>
PMA<13:8>
PMWR
PMRD
PMBE
PMALL
PMPIF
BUSY
© 2009 Microchip Technology Inc.
DS39778D-page 173
PIC18F87J11 FAMILY
FIGURE 11-25:
READ TIMING, 16-BIT MULTIPLEXED DATA,
FULLY MULTIPLEXED 16-BIT ADDRESS
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
Q1 Q2 Q3 Q4
PMCS2
PMCS1
PMD<7:0>
PMWR
Address<7:0>
Address<15:8>
LSB
MSB
PMRD
PMBE
PMALH
PMALL
PMPIF
BUSY
FIGURE 11-26:
WRITE TIMING, 16-BIT MULTIPLEXED DATA,
FULLY MULTIPLEXED 16-BIT ADDRESS
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
PMCS2
PMCS1
PMD<7:0>
PMWR
Address<7:0>
Address<15:8>
LSB
MSB
PMRD
PMBE
PMALH
PMALL
PMPIF
BUSY
DS39778D-page 174
© 2009 Microchip Technology Inc.
PIC18F87J11 FAMILY
11.4.1
MULTIPLEXED MEMORY OR
PERIPHERAL
11.4 Application Examples
This section introduces some potential applications for
the PMP module.
Figure 11-27 demonstrates the hookup of a memory or
other addressable peripheral in Full Multiplex mode.
Consequently, this mode achieves the best pin saving
from the microcontroller perspective. However, for this
configuration, there needs to be some external latches
to maintain the address.
FIGURE 11-27:
EXAMPLE OF A MULTIPLEXED ADDRESSING APPLICATION
PIC18F
A<7:0>
D<7:0>
PMD<7:0>
373
A<15:0>
PMALL
D<7:0>
CE
A<15:8>
373
OE
WR
PMALH
PMCS
PMRD
PMWR
Address Bus
Data Bus
Control Lines
ory or peripheral that is partially multiplexed with an
external latch. If the peripheral has internal latches as
shown in Figure 11-29, then no extra circuitry is
required except for the peripheral itself.
11.4.2
PARTIALLY MULTIPLEXED
MEMORY OR PERIPHERAL
Partial multiplexing implies using more pins; however,
for a few extra pins, some extra performance can be
achieved. Figure 11-28 shows an example of a mem-
FIGURE 11-28:
EXAMPLE OF A PARTIALLY MULTIPLEXED ADDRESSING APPLICATION
PIC18F
A<7:0>
373
PMD<7:0>
PMALL
A<14:0>
D<7:0>
D<7:0>
CE
A<14:8>
PMA<14:7>
OE
WR
Address Bus
Data Bus
PMCS
PMRD
PMWR
Control Lines
FIGURE 11-29:
EXAMPLE OF AN 8-BIT MULTIPLEXED ADDRESS AND DATA APPLICATION
PIC18F
PMD<7:0>
Parallel Peripheral
AD<7:0>
ALE
CS
PMALL
PMCS
PMRD
PMWR
Address Bus
Data Bus
RD
WR
Control Lines
© 2009 Microchip Technology Inc.
DS39778D-page 175
PIC18F87J11 FAMILY
11.4.3
PARALLEL EEPROM EXAMPLE
Figure 11-30 shows an example connecting parallel
EEPROM to the PMP. Figure 11-31 shows a slight
variation to this, configuring the connection for 16-bit
data from a single EEPROM.
FIGURE 11-30:
PARALLEL EEPROM EXAMPLE (UP TO 15-BIT ADDRESS, 8-BIT DATA)
PIC18F
Parallel EEPROM
A<n:0>
PMA<n:0>
PMD<7:0>
D<7:0>
PMCS
PMRD
PMWR
CE
OE
WR
Address Bus
Data Bus
Control Lines
FIGURE 11-31:
PARALLEL EEPROM EXAMPLE (UP TO 15-BIT ADDRESS, 16-BIT DATA)
PIC18F
Parallel EEPROM
A<n:1>
D<7:0>
PMA<n:0>
PMD<7:0>
PMBE
PMCS
PMRD
PMWR
A0
CE
OE
WR
Address Bus
Data Bus
Control Lines
11.4.4
LCD CONTROLLER EXAMPLE
The PMP module can be configured to connect to a
typical LCD controller interface, as shown in
Figure 11-32. In this case, the PMP module is config-
ured for active-high control signals since common LCD
displays require active-high control.
FIGURE 11-32:
LCD CONTROL EXAMPLE (BYTE MODE OPERATION)
PIC18F
LCD Controller
PM<7:0>
D<7:0>
RS
PMA0
PMRD/PMWR
PMCS
R/W
E
Address Bus
Data Bus
Control Lines
DS39778D-page 176
© 2009 Microchip Technology Inc.
PIC18F87J11 FAMILY
TABLE 11-3: REGISTERS ASSOCIATED WITH PMP MODULE
Reset
Values
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
on Page:
INTCON
GIE/GIEH PEIE/GIEL TMR0IE
INT0IE
TX1IF
TX1IE
TX1IP
RBIE
TMR0IF
CCP1IF
CCP1IE
CCP1IP
INT0IF
TMR2IF
TMR2IE
TMR2IP
RBIF
57
60
60
60
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
58
PIR1
PMPIF
PMPIE
PMPIP
PMPEN
CSF1
ADIF
ADIE
ADIP
—
RC1IF
RC1IE
RC1IP
PSIDL
ALP
SSP1IF
SSP1IE
SSP1IP
TMR1IF
TMR1IE
TMR1IP
PIE1
IPR1
PMCONH
PMCONL
PMADDRH/
PMDOUT1H
PMADDRL/
ADRMUX1 ADRMUX0 PTBEEN PTWREN PTRDEN
CSF0
CS1
CS2P
CS1P
BEP
WRSP
RDSP
CS2
Parallel Master Port Address High Byte
(1)
Parallel Port Out Data High Byte (Buffer 1)
Parallel Master Port Address Low Byte
Parallel Port Out Data Low Byte (Buffer 0)
Parallel Port Out Data High Byte (Buffer 3)
Parallel Port Out Data Low Byte (Buffer 2)
Parallel Port In Data High Byte (Buffer 1)
Parallel Port In Data Low Byte (Buffer 0)
Parallel Port In Data High Byte (Buffer 3)
Parallel Port In Data Low Byte (Buffer 2)
(1)
PMDOUT1L
PMDOUT2H
PMDOUT2L
PMDIN1H
PMDIN1L
PMDIN2H
PMDIN2L
PMMODEH
PMMODEL
PMEH
BUSY
WAITB1
PTEN15
PTEN7
IBF
IRQM1
WAITB0
PTEN14
PTEN6
IBOV
IRQM0
WAITM3
PTEN13
PTEN5
—
INCM1
WAITM2
PTEN12
PTEN4
—
INCM0
WAITM1
PTEN11
PTEN3
IB3F
MODE16
WAITM0
PTEN10
PTEN2
IB2F
MODE1
WAITE1
PTEN9
PTEN1
IB1F
MODE0
WAITE0
PTEN8
PTEN0
IB0F
PMEL
PMSTATH
PMSTATL
OBE
OBUF
—
—
—
OB3E
—
OB2E
OB1E
—
OB0E
(2)
PADCFG1
—
—
—
—
PMPTTL
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used during PMP operation.
Note 1: The PMADDRH/PMDOUT1H and PMADDRL/PMDOUT1L register pairs share the physical registers and
addresses, but have different functions determined by the module’s operating mode.
2: Configuration SFR, overlaps with default SFR at this address; available only when WDTCON<4> = 1.
© 2009 Microchip Technology Inc.
DS39778D-page 177
PIC18F87J11 FAMILY
NOTES:
DS39778D-page 178
© 2009 Microchip Technology Inc.
PIC18F87J11 FAMILY
The T0CON register (Register 12-1) controls all
aspects of the module’s operation, including the
prescale selection. It is both readable and writable.
12.0 TIMER0 MODULE
The Timer0 module incorporates the following features:
• Software selectable operation as a timer or coun-
ter in both 8-bit or 16-bit modes
A simplified block diagram of the Timer0 module in 8-bit
mode is shown in Figure 12-1. Figure 12-2 shows a
simplified block diagram of the Timer0 module in 16-bit
mode.
• Readable and writable registers
• Dedicated 8-bit, software programmable
prescaler
• Selectable clock source (internal or external)
• Edge select for external clock
• Interrupt-on-overflow
REGISTER 12-1: T0CON: TIMER0 CONTROL REGISTER
R/W-1
R/W-1
R/W-1
T0CS
R/W-1
T0SE
R/W-1
PSA
R/W-1
T0PS2
R/W-1
T0PS1
R/W-1
T0PS0
TMR0ON
T08BIT
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
-n = Value at POR
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2-0
TMR0ON: Timer0 On/Off Control bit
1= Enables Timer0
0= Stops Timer0
T08BIT: Timer0 8-Bit/16-Bit Control bit
1= Timer0 is configured as an 8-bit timer/counter
0= Timer0 is configured as a 16-bit timer/counter
T0CS: Timer0 Clock Source Select bit
1= Transition on T0CKI pin
0= Internal instruction cycle clock (CLKO)
T0SE: Timer0 Source Edge Select bit
1= Increment on high-to-low transition on T0CKI pin
0= Increment on low-to-high transition on T0CKI pin
PSA: Timer0 Prescaler Assignment bit
1= TImer0 prescaler is not assigned. Timer0 clock input bypasses prescaler.
0= Timer0 prescaler is assigned. Timer0 clock input comes from prescaler output.
T0PS2:T0PS0: Timer0 Prescaler Select bits
111= 1:256 Prescale value
110= 1:128 Prescale value
101= 1:64 Prescale value
100= 1:32 Prescale value
011= 1:16 Prescale value
010= 1:8 Prescale value
001= 1:4 Prescale value
000= 1:2 Prescale value
© 2009 Microchip Technology Inc.
DS39778D-page 179
PIC18F87J11 FAMILY
internal phase clock (TOSC). There is a delay between
synchronization and the onset of incrementing the
timer/counter.
12.1 Timer0 Operation
Timer0 can operate as either a timer or a counter. The
mode is selected with the T0CS bit (T0CON<5>). In
Timer mode (T0CS = 0), the module increments on
every clock by default unless a different prescaler value
is selected (see Section 12.3 “Prescaler”). If the
TMR0 register is written to, the increment is inhibited
for the following two instruction cycles. The user can
work around this by writing an adjusted value to the
TMR0 register.
12.2 Timer0 Reads and Writes in
16-Bit Mode
TMR0H is not the actual high byte of Timer0 in 16-bit
mode. It is actually a buffered version of the real high
byte of Timer0 which is not directly readable nor writ-
able (refer to Figure 12-2). TMR0H is updated with the
contents of the high byte of Timer0 during a read of
TMR0L. This provides the ability to read all 16 bits of
Timer0 without having to verify that the read of the high
and low byte were valid, due to a rollover between
successive reads of the high and low byte.
The Counter mode is selected by setting the T0CS bit
(= 1). In this mode, Timer0 increments either on every
rising or falling edge of pin RA4/T0CKI. The increment-
ing edge is determined by the Timer0 Source Edge
Select bit, T0SE (T0CON<4>); clearing this bit selects
the rising edge. Restrictions on the external clock input
are discussed below.
Similarly, a write to the high byte of Timer0 must also
take place through the TMR0H Buffer register. The high
byte is updated with the contents of TMR0H when a
write occurs to TMR0L. This allows all 16 bits of Timer0
to be updated at once.
An external clock source can be used to drive Timer0;
however, it must meet certain requirements to ensure
that the external clock can be synchronized with the
FIGURE 12-1:
TIMER0 BLOCK DIAGRAM (8-BIT MODE)
FOSC/4
0
1
1
0
Set
TMR0IF
on Overflow
Sync with
Internal
Clocks
TMR0L
8
Programmable
Prescaler
T0CKI pin
(2 TCY Delay)
T0SE
T0CS
3
T0PS2:T0PS0
PSA
8
Internal Data Bus
Note: Upon Reset, Timer0 is enabled in 8-bit mode with clock input from T0CKI max. prescale.
FIGURE 12-2:
TIMER0 BLOCK DIAGRAM (16-BIT MODE)
FOSC/4
0
1
Sync with
Internal
Clocks
Set
TMR0
High Byte
1
TMR0L
TMR0IF
Programmable
Prescaler
on Overflow
T0CKI pin
0
8
(2 TCY Delay)
T0SE
3
T0CS
Read TMR0L
Write TMR0L
T0PS2:T0PS0
PSA
8
8
TMR0H
8
8
Internal Data Bus
Note: Upon Reset, Timer0 is enabled in 8-bit mode with clock input from T0CKI max. prescale.
DS39778D-page 180
© 2009 Microchip Technology Inc.
PIC18F87J11 FAMILY
12.3.1
SWITCHING PRESCALER
ASSIGNMENT
12.3 Prescaler
An 8-bit counter is available as a prescaler for the Timer0
module. The prescaler is not directly readable or writable.
Its value is set by the PSA and T0PS2:T0PS0 bits
(T0CON<3:0>) which determine the prescaler
assignment and prescale ratio.
The prescaler assignment is fully under software
control and can be changed “on-the-fly” during program
execution.
12.4 Timer0 Interrupt
Clearing the PSA bit assigns the prescaler to the
Timer0 module. When it is assigned, prescale values
from 1:2 through 1:256 in power-of-2 increments are
selectable.
The TMR0 interrupt is generated when the TMR0
register overflows from FFh to 00h in 8-bit mode, or
from FFFFh to 0000h in 16-bit mode. This overflow sets
the TMR0IF flag bit. The interrupt can be masked by
clearing the TMR0IE bit (INTCON<5>). Before
re-enabling the interrupt, the TMR0IF bit must be
cleared in software by the Interrupt Service Routine.
When assigned to the Timer0 module, all instructions
writing to the TMR0 register (e.g., CLRF TMR0, MOVWF
TMR0, BSF TMR0, etc.) clear the prescaler count.
Note:
Writing to TMR0 when the prescaler is
assigned to Timer0 will clear the prescaler
count but will not change the prescaler
assignment.
Since Timer0 is shut down in Sleep mode, the TMR0
interrupt cannot awaken the processor from Sleep.
TABLE 12-1: REGISTERS ASSOCIATED WITH TIMER0
Reset
Values
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
on Page:
TMR0L
Timer0 Register Low Byte
Timer0 Register High Byte
58
58
57
58
60
TMR0H
INTCON
T0CON
TRISA
GIE/GIEH PEIE/GIEL TMR0IE
TMR0ON T08BIT T0CS
TRISA7(1) TRISA6(1) TRISA5
INT0IE
T0SE
RBIE
PSA
TMR0IF
T0PS2
INT0IF
T0PS1
TRISA1
RBIF
T0PS0
TRISA0
TRISA4
TRISA3
TRISA2
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by Timer0.
Note 1: These bits are only available in select oscillator modes (FOSC2 Configuration bit = 0); otherwise, they are
unimplemented.
© 2009 Microchip Technology Inc.
DS39778D-page 181
PIC18F87J11 FAMILY
NOTES:
DS39778D-page 182
© 2009 Microchip Technology Inc.
PIC18F87J11 FAMILY
A simplified block diagram of the Timer1 module is
shown in Figure 13-1. A block diagram of the module’s
operation in Read/Write mode is shown in Figure 13-2.
13.0 TIMER1 MODULE
The Timer1 timer/counter module incorporates these
features:
The module incorporates its own low-power oscillator
to provide an additional clocking option. The Timer1
oscillator can also be used as a low-power clock source
for the microcontroller in power-managed operation.
• Software selectable operation as a 16-bit timer or
counter
• Readable and writable 8-bit registers (TMR1H
and TMR1L)
Timer1 can also be used to provide Real-Time Clock
(RTC) functionality to applications with only a minimal
addition of external components and code overhead.
• Selectable clock source (internal or external) with
device clock or Timer1 oscillator internal options
• Interrupt on overflow
Timer1 is controlled through the T1CON Control
register (Register 13-1). It also contains the Timer1
Oscillator Enable bit (T1OSCEN). Timer1 can be
enabled or disabled by setting or clearing control bit,
TMR1ON (T1CON<0>).
• Reset on ECCPx Special Event Trigger
• Device clock status flag (T1RUN)
REGISTER 13-1: T1CON: TIMER1 CONTROL REGISTER(1)
R/W-0
RD16
R-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
T1RUN
T1CKPS1
T1CKPS0
T1OSCEN
T1SYNC
TMR1CS
TMR1ON
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
-n = Value at POR
bit 7
RD16: 16-Bit Read/Write Mode Enable bit
1= Enables register read/write of TImer1 in one 16-bit operation
0= Enables register read/write of Timer1 in two 8-bit operations
bit 6
T1RUN: Timer1 System Clock Status bit
1= Device clock is derived from Timer1 oscillator
0= Device clock is derived from another source
bit 5-4
T1CKPS1:T1CKPS0: Timer1 Input Clock Prescale Select bits
11= 1:8 Prescale value
10= 1:4 Prescale value
01= 1:2 Prescale value
00= 1:1 Prescale value
bit 3
bit 2
T1OSCEN: Timer1 Oscillator Enable bit
1= Timer1 oscillator is enabled
0= Timer1 oscillator is shut off
The oscillator inverter and feedback resistor are turned off to eliminate power drain.
T1SYNC: Timer1 External Clock Input Synchronization Select bit
When TMR1CS = 1:
1= Do not synchronize external clock input
0= Synchronize external clock input
When TMR1CS = 0:
This bit is ignored. Timer1 uses the internal clock when TMR1CS = 0.
bit 1
bit 0
TMR1CS: Timer1 Clock Source Select bit
1= External clock from pin RC0/T1OSO/T13CKI (on the rising edge)
0= Internal clock (FOSC/4)
TMR1ON: Timer1 On bit
1= Enables Timer1
0= Stops Timer1
Note 1: Default (legacy) SFR at this address, available when WDTCON<4> = 0.
© 2009 Microchip Technology Inc.
DS39778D-page 183
PIC18F87J11 FAMILY
cycle (FOSC/4). When the bit is set, Timer1 increments
on every rising edge of the Timer1 external clock input
or the Timer1 oscillator, if enabled.
13.1 Timer1 Operation
Timer1 can operate in one of these modes:
• Timer
When Timer1 is enabled, the RC1/T1OSI and
RC0/T1OSO/T13CKI pins become inputs. This means
the values of TRISC<1:0> are ignored and the pins are
read as ‘0’.
• Synchronous Counter
• Asynchronous Counter
The operating mode is determined by the clock select
bit, TMR1CS (T1CON<1>). When TMR1CS is cleared
(= 0), Timer1 increments on every internal instruction
FIGURE 13-1:
TIMER1 BLOCK DIAGRAM
Timer1 Oscillator
Timer1 Clock Input
1
0
On/Off
T1OSO/T13CKI
T1OSI
1
Synchronize
Detect
Prescaler
1, 2, 4, 8
FOSC/4
Internal
Clock
0
2
Sleep Input
T1OSCEN(1)
T1CKPS1:T1CKPS0
T1SYNC
Timer1
On/Off
TMR1CS
TMR1ON
Set
TMR1
High Byte
Clear TMR1
(ECCPx Special Event Trigger)
TMR1L
TMR1IF
on Overflow
Note 1: When enable bit, T1OSCEN, is cleared, the inverter and feedback resistor are turned off to eliminate power drain.
FIGURE 13-2:
TIMER1 BLOCK DIAGRAM (16-BIT READ/WRITE MODE)
Timer1 Oscillator
Timer1 Clock Input
1
0
T1OSO/T13CKI
T1OSI
1
0
Synchronize
Detect
Prescaler
1, 2, 4, 8
FOSC/4
Internal
Clock
2
Sleep Input
T1OSCEN(1)
T1CKPS1:T1CKPS0
T1SYNC
Timer1
On/Off
TMR1CS
TMR1ON
Set
TMR1IF
on Overflow
TMR1
High Byte
Clear TMR1
(ECCPx Special Event Trigger)
TMR1L
8
Read TMR1L
Write TMR1L
8
8
TMR1H
8
8
Internal Data Bus
Note 1: When enable bit, T1OSCEN, is cleared, the inverter and feedback resistor are turned off to eliminate power drain.
DS39778D-page 184
© 2009 Microchip Technology Inc.
PIC18F87J11 FAMILY
TABLE 13-1: CAPACITOR SELECTION FOR
THETIMEROSCILLATOR(2,3,4)
13.2 Timer1 16-Bit Read/Write Mode
Timer1 can be configured for 16-bit reads and writes
(see Figure 13-2). When the RD16 control bit,
T1CON<7>, is set, the address for TMR1H is mapped
to a buffer register for the high byte of Timer1. A read
from TMR1L will load the contents of the high byte of
Timer1 into the Timer1 High Byte Buffer register. This
provides the user with the ability to accurately read all
16 bits of Timer1 without having to determine whether
a read of the high byte, followed by a read of the low
byte, has become invalid due to a rollover between
reads.
Oscillator
Freq.
C1
C2
Type
LP
32 kHz
27 pF(1)
27 pF(1)
Note 1: Microchip suggests these values as a
starting point in validating the oscillator
circuit.
2: Higher capacitance increases the stability
of the oscillator but also increases the
start-up time.
A write to the high byte of Timer1 must also take place
through the TMR1H Buffer register. The Timer1 high
byte is updated with the contents of TMR1H when a
write occurs to TMR1L. This allows a user to write all
16 bits to both the high and low bytes of Timer1 at once.
3: Since each resonator/crystal has its own
characteristics, the user should consult
the resonator/crystal manufacturer for
appropriate
values
of
external
components.
The high byte of Timer1 is not directly readable or
writable in this mode. All reads and writes must take
place through the Timer1 High Byte Buffer register.
Writes to TMR1H do not clear the Timer1 prescaler.
The prescaler is only cleared on writes to TMR1L.
4: Capacitor values are for design guidance
only.
13.3.1
USING TIMER1 AS A
CLOCK SOURCE
The Timer1 oscillator is also available as a clock source
in power-managed modes. By setting the clock select
bits, SCS1:SCS0 (OSCCON<1:0>), to ‘01’, the device
switches to SEC_RUN mode; both the CPU and
peripherals are clocked from the Timer1 oscillator. If the
IDLEN bit (OSCCON<7>) is cleared and a SLEEP
instruction is executed, the device enters SEC_IDLE
mode. Additional details are available in Section 3.0
“Power-Managed Modes”.
13.3 Timer1 Oscillator
An on-chip crystal oscillator circuit is incorporated
between pins T1OSI (input) and T1OSO (amplifier
output). It is enabled by setting the Timer1 Oscillator
Enable bit, T1OSCEN (T1CON<3>). The oscillator is a
low-power circuit rated for 32 kHz crystals. It will
continue to run during all power-managed modes. The
circuit for a typical LP oscillator is shown in Figure 13-3.
Table 13-1 shows the capacitor selection for the Timer1
oscillator.
Whenever the Timer1 oscillator is providing the clock
source, the Timer1 system clock status flag, T1RUN
(T1CON<6>), is set. This can be used to determine the
controller’s current clocking mode. It can also indicate
the clock source being currently used by the Fail-Safe
Clock Monitor. If the Clock Monitor is enabled and the
Timer1 oscillator fails while providing the clock, polling
the T1RUN bit will indicate whether the clock is being
provided by the Timer1 oscillator or another source.
The user must provide a software time delay to ensure
proper start-up of the Timer1 oscillator.
FIGURE 13-3:
EXTERNAL
COMPONENTS FOR THE
TIMER1 LP OSCILLATOR
C1
27 pF
PIC18F87J11
13.3.2
TIMER1 OSCILLATOR LAYOUT
CONSIDERATIONS
T1OSI
The Timer1 oscillator circuit draws very little power
during operation. Due to the low-power nature of the
oscillator, it may also be sensitive to rapidly changing
signals in close proximity.
XTAL
32.768 kHz
T1OSO
C2
27 pF
The oscillator circuit, shown in Figure 13-3, should be
located as close as possible to the microcontroller.
There should be no circuits passing within the oscillator
circuit boundaries other than VSS or VDD.
Note:
See the Notes with Table 13-1 for additional
information about capacitor selection.
© 2009 Microchip Technology Inc.
DS39778D-page 185
PIC18F87J11 FAMILY
If a high-speed circuit must be located near the oscilla-
tor (such as the ECCP1 pin in Output Compare or PWM
mode, or the primary oscillator using the OSC2 pin), a
grounded guard ring around the oscillator circuit, as
shown in Figure 13-4, may be helpful when used on a
single-sided PCB or in addition to a ground plane.
Note:
The Special Event Triggers from the
ECCPx module will not set the TMR1IF
interrupt flag bit (PIR1<0>).
13.6 Using Timer1 as a Real-Time Clock
Adding an external LP oscillator to Timer1 (such as the
one described in Section 13.3 “Timer1 Oscillator”)
gives users the option to include RTC functionality to
their applications. This is accomplished with an
inexpensive watch crystal to provide an accurate time
base and several lines of application code to calculate
the time. When operating in Sleep mode and using a
battery or supercapacitor as a power source, it can
completely eliminate the need for a separate RTC
device and battery backup.
FIGURE 13-4:
OSCILLATOR CIRCUIT
WITH GROUNDED
GUARD RING
VDD
VSS
OSC1
OSC2
The application code routine, RTCisr, shown in
Example 13-1, demonstrates a simple method to
increment a counter at one-second intervals using an
Interrupt Service Routine. Incrementing the TMR1
register pair to overflow triggers the interrupt and calls
the routine which increments the seconds counter by
one. Additional counters for minutes and hours are
incremented as the previous counter overflows.
RC0
RC1
RC2
Since the register pair is 16 bits wide, counting up to
overflow the register directly from a 32.768 kHz clock
would take 2 seconds. To force the overflow at the
required one-second intervals, it is necessary to pre-
load it. The simplest method is to set the MSb of
TMR1H with a BSF instruction. Note that the TMR1L
register is never preloaded or altered; doing so may
introduce cumulative error over many cycles.
Note: Not drawn to scale.
13.4 Timer1 Interrupt
The TMR1 register pair (TMR1H:TMR1L) increments
from 0000h to FFFFh and rolls over to 0000h. The
Timer1 interrupt, if enabled, is generated on overflow
which is latched in interrupt flag bit, TMR1IF
(PIR1<0>). This interrupt can be enabled or disabled
by setting or clearing the Timer1 Interrupt Enable bit,
TMR1IE (PIE1<0>).
For this method to be accurate, Timer1 must operate in
Asynchronous mode and the Timer1 overflow interrupt
must be enabled (PIE1<0> = 1), as shown in the
routine, RTCinit. The Timer1 oscillator must also be
enabled and running at all times.
13.5 Resetting Timer1 Using the
ECCPx Special Event Trigger
If ECCP1 or ECCP2 is configured to use Timer1 and to
generate a Special Event Trigger in Compare mode
(CCPxM3:CCPxM0 = 1011), this signal will reset
Timer3. The trigger from ECCP2 will also start an A/D
conversion if the A/D module is enabled (see
Section 18.2.1 “Special Event Trigger” for more
information).
The module must be configured as either a timer or a
synchronous counter to take advantage of this feature.
When used this way, the CCPRxH:CCPRxL register
pair effectively becomes a period register for Timer1.
If Timer1 is running in Asynchronous Counter mode,
this Reset operation may not work.
In the event that a write to Timer1 coincides with a
Special Event Trigger, the write operation will take
precedence.
DS39778D-page 186
© 2009 Microchip Technology Inc.
PIC18F87J11 FAMILY
lowing a later Timer1 increment. This can be done by
monitoring TMR1L within the interrupt routine until it
increments, and then updating the TMR1H:TMR1L reg-
ister pair while the clock is low, or one-half of the period
of the clock source. Assuming that Timer1 is being
used as a Real-Time Clock, the clock source is a
32.768 kHz crystal oscillator. In this case, one-half
period of the clock is 15.25 μs.
13.7 Considerations in Asynchronous
Counter Mode
Following a Timer1 interrupt and an update to the
TMR1 registers, the Timer1 module uses a falling edge
on its clock source to trigger the next register update on
the rising edge. If the update is completed after the
clock input has fallen, the next rising edge will not be
counted.
The Real-Time Clock application code in Example 13-1
shows a typical ISR for Timer1, as well as the optional
code required if the update cannot be done reliably
within the required interval.
If the application can reliably update TMR1 before the
timer input goes low, no additional action is needed.
Otherwise, an adjusted update can be performed fol-
EXAMPLE 13-1:
IMPLEMENTING A REAL-TIME CLOCK USING A TIMER1 INTERRUPT SERVICE
RTCinit
MOVLW
MOVWF
CLRF
80h
TMR1H
TMR1L
; Preload TMR1 register pair
; for 1 second overflow
MOVLW
MOVWF
CLRF
b’00001111’
T1CON
secs
; Configure for external clock,
; Asynchronous operation, external oscillator
; Initialize timekeeping registers
;
CLRF
mins
MOVLW
MOVWF
BSF
.12
hours
PIE1, TMR1IE
; Enable Timer1 interrupt
RETURN
RTCisr
; Insert the next 4 lines of code when TMR1
; can not be reliably updated before clock pulse goes low
; wait for TMR1L to become clear
; (may already be clear)
BTFSC
BRA
TMR1L,0
$-2
BTFSS
BRA
TMR1L,0
$-2
; wait for TMR1L to become set
; TMR1 has just incremented
; If TMR1 update can be completed before clock pulse goes low
; Start ISR here
BSF
BCF
INCF
MOVLW
CPFSGT
RETURN
CLRF
TMR1H, 7
PIR1, TMR1IF
secs, F
.59
; Preload for 1 sec overflow
; Clear interrupt flag
; Increment seconds
; 60 seconds elapsed?
secs
; No, done
secs
mins, F
.59
; Clear seconds
; Increment minutes
; 60 minutes elapsed?
INCF
MOVLW
CPFSGT
RETURN
CLRF
mins
; No, done
mins
hours, F
.23
; clear minutes
; Increment hours
; 24 hours elapsed?
INCF
MOVLW
CPFSGT
RETURN
CLRF
hours
; No, done
; Reset hours
; Done
hours
RETURN
© 2009 Microchip Technology Inc.
DS39778D-page 187
PIC18F87J11 FAMILY
TABLE 13-2: REGISTERS ASSOCIATED WITH TIMER1 AS A TIMER/COUNTER
Reset
Values
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
on Page:
INTCON
PIR1
GIE/GIEH PEIE/GIEL TMR0IE
INT0IE
TX1IF
TX1IE
TX1IP
RBIE
TMR0IF
CCP1IF
CCP1IE
CCP1IP
INT0IF
TMR2IF
TMR2IE
TMR2IP
RBIF
57
60
60
60
58
58
58
PMPIF
PMPIE
PMPIP
ADIF
ADIE
ADIP
RC1IF
RC1IE
RC1IP
SSP1IF
SSP1IE
SSP1IP
TMR1IF
TMR1IE
TMR1IP
PIE1
IPR1
TMR1L(1) Timer1 Register Low Byte
TMR1H(1) Timer1 Register High Byte
T1CON(1)
RD16
T1RUN T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON
Legend: Shaded cells are not used by the Timer1 module.
Note 1: Default (legacy) SFR at this address, available when WDTCON<4> = 0.
DS39778D-page 188
© 2009 Microchip Technology Inc.
PIC18F87J11 FAMILY
14.1 Timer2 Operation
14.0 TIMER2 MODULE
In normal operation, TMR2 is incremented from 00h on
each clock (FOSC/4). A 4-bit counter/prescaler on the
clock input gives direct input, divide-by-4 and
divide-by-16 prescale options. These are selected by
the prescaler control bits, T2CKPS1:T2CKPS0
(T2CON<1:0>). The value of TMR2 is compared to that
of the Period register, PR2, on each clock cycle. When
the two values match, the comparator generates a
match signal as the timer output. This signal also resets
the value of TMR2 to 00h on the next cycle and drives
the output counter/postscaler (see Section 14.2
“Timer2 Interrupt”).
The Timer2 module incorporates the following features:
• 8-Bit Timer and Period registers (TMR2 and PR2,
respectively)
• Readable and writable (both registers)
• Software programmable prescaler
(1:1, 1:4 and 1:16)
• Software programmable postscaler
(1:1 through 1:16)
• Interrupt on TMR2 to PR2 match
• Optional use as the shift clock for the
MSSP modules
The TMR2 and PR2 registers are both directly readable
and writable. The TMR2 register is cleared on any
device Reset, while the PR2 register initializes at FFh.
Both the prescaler and postscaler counters are cleared
on the following events:
The module is controlled through the T2CON register
(Register 14-1) which enables or disables the timer and
configures the prescaler and postscaler. Timer2 can be
shut off by clearing control bit, TMR2ON (T2CON<2>),
to minimize power consumption.
• a write to the TMR2 register
• a write to the T2CON register
A simplified block diagram of the module is shown in
Figure 14-1.
• any device Reset (Power-on Reset, MCLR Reset,
Watchdog Timer Reset or Brown-out Reset)
TMR2 is not cleared when T2CON is written.
REGISTER 14-1: T2CON: TIMER2 CONTROL REGISTER
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
T2OUTPS3 T2OUTPS2 T2OUTPS1 T2OUTPS0
TMR2ON
T2CKPS1
T2CKPS0
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7
Unimplemented: Read as ‘0’
bit 6-3
T2OUTPS3:T2OUTPS0: Timer2 Output Postscale Select bits
0000= 1:1 Postscale
0001= 1:2 Postscale
•
•
•
1111= 1:16 Postscale
bit 2
TMR2ON: Timer2 On bit
1= Timer2 is on
0= Timer2 is off
bit 1-0
T2CKPS1:T2CKPS0: Timer2 Clock Prescale Select bits
00= Prescaler is 1
01= Prescaler is 4
1x= Prescaler is 16
© 2009 Microchip Technology Inc.
DS39778D-page 189
PIC18F87J11 FAMILY
14.2 Timer2 Interrupt
14.3 Timer2 Output
Timer2 can also generate an optional device interrupt.
The Timer2 output signal (TMR2 to PR2 match) pro-
vides the input for the 4-bit output counter/postscaler.
This counter generates the TMR2 match interrupt flag
which is latched in TMR2IF (PIR1<1>). The interrupt is
enabled by setting the TMR2 Match Interrupt Enable
bit, TMR2IE (PIE1<1>).
The unscaled output of TMR2 is available primarily to
the ECCPx/CCPx modules, where it is used as a time
base for operations in PWM mode.
Timer2 can be optionally used as the shift clock source
for the MSSP modules operating in SPI mode.
Additional information is provided in Section 19.0
“Master Synchronous Serial Port (MSSP) Module”.
A range of 16 postscale options (from 1:1 through 1:16
inclusive) can be selected with the postscaler control
bits, T2OUTPS3:T2OUTPS0 (T2CON<6:3>).
FIGURE 14-1:
TIMER2 BLOCK DIAGRAM
4
1:1 to 1:16
T2OUTPS3:T2OUTPS0
Set TMR2IF
Postscaler
2
TMR2 Output
T2CKPS1:T2CKPS0
(to PWM or MSSP)
TMR2/PR2
Match
Reset
TMR2
1:1, 1:4, 1:16
Prescaler
Comparator
PR2
FOSC/4
8
8
8
Internal Data Bus
TABLE 14-1: REGISTERS ASSOCIATED WITH TIMER2 AS A TIMER/COUNTER
Reset
Values
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
on Page:
INTCON GIE/GIEH PEIE/GIEL TMR0IE
INT0IE
TX1IF
TX1IE
TX1IP
RBIE
TMR0IF
CCP1IF
CCP1IE
CCP1IP
INT0IF
TMR2IF
TMR2IE
TMR2IP
RBIF
57
60
60
60
58
58
58
PIR1
PIE1
IPR1
PMPIF
PMPIE
PMPIP
ADIF
ADIE
ADIP
RC1IF
RC1IE
RC1IP
SSP1IF
SSP1IE
SSP1IP
TMR1IF
TMR1IE
TMR1IP
TMR2(1) Timer2 Register
T2CON
PR2(1)
—
T2OUTPS3 T2OUTPS2 T2OUTPS1 T2OUTPS0 TMR2ON T2CKPS1 T2CKPS0
Timer2 Period Register
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the Timer2 module.
Note 1: Default (legacy) SFR at this address, available when WDTCON<4> = 0.
DS39778D-page 190
© 2009 Microchip Technology Inc.
PIC18F87J11 FAMILY
A simplified block diagram of the Timer3 module is
shown in Figure 15-1. A block diagram of the module’s
operation in Read/Write mode is shown in Figure 15-2.
15.0 TIMER3 MODULE
The Timer3 timer/counter module incorporates these
features:
The Timer3 module is controlled through the T3CON
register (Register 15-1). It also selects the clock source
options for the CCP and ECCP modules; see
• Software selectable operation as a 16-bit timer or
counter
• Readable and writable 8-bit registers (TMR3H
and TMR3L)
Section 17.1.1
Resources” for more information.
“CCP
Modules
and
Timer
• Selectable clock source (internal or external) with
device clock or Timer1 oscillator internal options
• Interrupt-on-overflow
• Module Reset on ECCPx Special Event Trigger
REGISTER 15-1: T3CON: TIMER3 CONTROL REGISTER
R/W-0
RD16
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
TMR3ON
bit 0
T3CCP2
T3CKPS1
T3CKPS0
T3CCP1
T3SYNC
TMR3CS
bit 7
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
-n = Value at POR
bit 7
RD16: 16-Bit Read/Write Mode Enable bit
1= Enables register read/write of Timer3 in one 16-bit operation
0= Enables register read/write of Timer3 in two 8-bit operations
bit 6,3
T3CCP2:T3CCP1: Timer3 and Timer1 to ECCPx/CCPx Enable bits
11= Timer3 and Timer4 are the clock sources for all ECCPx/CCPx modules
10= Timer3 and Timer4 are the clock sources for ECCP3, CCP4 and CCP5;
Timer1 and Timer2 are the clock sources for ECCP1 and ECCP2
01= Timer3 and Timer4 are the clock sources for ECCP2, ECCP3, CCP4 and CCP5;
Timer1 and Timer2 are the clock sources for ECCP1
00= Timer1 and Timer2 are the clock sources for all ECCPx/CCPx modules
bit 5-4
bit 2
T3CKPS1:T3CKPS0: Timer3 Input Clock Prescale Select bits
11= 1:8 Prescale value
10= 1:4 Prescale value
01= 1:2 Prescale value
00= 1:1 Prescale value
T3SYNC: Timer3 External Clock Input Synchronization Control bit
(Not usable if the device clock comes from Timer1/Timer3.)
When TMR3CS = 1:
1= Do not synchronize external clock input
0= Synchronize external clock input
When TMR3CS = 0:
This bit is ignored. Timer3 uses the internal clock when TMR3CS = 0.
bit 1
bit 0
TMR3CS: Timer3 Clock Source Select bit
1= External clock input from Timer1 oscillator or T13CKI (on the rising edge after the first
falling edge)
0= Internal clock (FOSC/4)
TMR3ON: Timer3 On bit
1= Enables Timer3
0= Stops Timer3
© 2009 Microchip Technology Inc.
DS39778D-page 191
PIC18F87J11 FAMILY
The operating mode is determined by the clock select
bit, TMR3CS (T3CON<1>). When TMR3CS is cleared
(= 0), Timer3 increments on every internal instruction
cycle (FOSC/4). When the bit is set, Timer3 increments
on every rising edge of the Timer1 external clock input
or the Timer1 oscillator, if enabled.
15.1 Timer3 Operation
Timer3 can operate in one of three modes:
• Timer
• Synchronous Counter
• Asynchronous Counter
As
with
Timer1,
the
RC1/T1OSI
and
RC0/T1OSO/T13CKI pins become inputs when the
Timer1 oscillator is enabled. This means the values of
TRISC<1:0> are ignored and the pins are read as ‘0’.
FIGURE 15-1:
TIMER3 BLOCK DIAGRAM
Timer1 Oscillator
Timer1 Clock Input
1
0
1
0
T1OSO/T13CKI
T1OSI
Synchronize
Detect
Prescaler
1, 2, 4, 8
FOSC/4
Internal
Clock
2
Sleep Input
T1OSCEN(1)
TMR3CS
Timer3
On/Off
T3CKPS1:T3CKPS0
T3SYNC
TMR3ON
ECCPx Special Event Trigger
Clear TMR3
Set
TMR3
High Byte
TMR3L
TMR3IF
ECCPx/CCPx Select from T3CON<6,3>
on Overflow
Note 1: When enable bit, T1OSCEN, is cleared, the inverter and feedback resistor are turned off to eliminate power drain.
FIGURE 15-2:
TIMER3 BLOCK DIAGRAM (16-BIT READ/WRITE MODE)
Timer1 Oscillator
Timer1 Clock Input
1
0
1
0
T13CKI/T1OSO
T1OSI
Synchronize
Detect
Prescaler
1, 2, 4, 8
FOSC/4
Internal
Clock
2
Sleep Input
T1OSCEN(1)
T3CKPS1:T3CKPS0
T3SYNC
Timer3
On/Off
TMR3CS
TMR3ON
ECCPx Special Event Trigger
ECCPx/CCPx Select from T3CON<6,3>
Clear TMR3
Set
TMR3IF
on Overflow
TMR3
High Byte
TMR3L
8
Read TMR1L
Write TMR1L
8
8
TMR3H
8
8
Internal Data Bus
Note 1: When enable bit, T1OSCEN, is cleared, the inverter and feedback resistor are turned off to eliminate power drain.
DS39778D-page 192
© 2009 Microchip Technology Inc.
PIC18F87J11 FAMILY
15.2 Timer3 16-Bit Read/Write Mode
15.4 Timer3 Interrupt
Timer3 can be configured for 16-bit reads and writes
(see Figure 15-2). When the RD16 control bit
(T3CON<7>) is set, the address for TMR3H is mapped
to a buffer register for the high byte of Timer3. A read
from TMR3L will load the contents of the high byte of
Timer3 into the Timer3 High Byte Buffer register. This
provides the user with the ability to accurately read all
16 bits of Timer1 without having to determine whether
a read of the high byte, followed by a read of the low
byte, has become invalid due to a rollover between
reads.
The TMR3 register pair (TMR3H:TMR3L) increments
from 0000h to FFFFh and overflows to 0000h. The
Timer3 interrupt, if enabled, is generated on overflow
and is latched in interrupt flag bit, TMR3IF (PIR2<1>).
This interrupt can be enabled or disabled by setting or
clearing the Timer3 Interrupt Enable bit, TMR3IE
(PIE2<1>).
15.5 Resetting Timer3 Using the
ECCPx Special Event Trigger
If ECCP1 or ECCP2 is configured to use Timer3 and to
generate a Special Event Trigger in Compare mode
(CCPxM3:CCPxM0 = 1011), this signal will reset
Timer3. The trigger from ECCP2 will also start an A/D
conversion if the A/D module is enabled (see
Section 18.2.1 “Special Event Trigger” for more
information).
A write to the high byte of Timer3 must also take place
through the TMR3H Buffer register. The Timer3 high
byte is updated with the contents of TMR3H when a
write occurs to TMR3L. This allows a user to write all
16 bits to both the high and low bytes of Timer3 at once.
The high byte of Timer3 is not directly readable or
writable in this mode. All reads and writes must take
place through the Timer3 High Byte Buffer register.
The module must be configured as either a timer or
synchronous counter to take advantage of this feature.
When used this way, the CCPRxH:CCPRxL register
pair effectively becomes a period register for Timer3.
Writes to TMR3H do not clear the Timer3 prescaler.
The prescaler is only cleared on writes to TMR3L.
If Timer3 is running in Asynchronous Counter mode,
the Reset operation may not work.
15.3 Using the Timer1 Oscillator as the
Timer3 Clock Source
In the event that a write to Timer3 coincides with a
Special Event Trigger from an ECCPx module, the
write will take precedence.
The Timer1 internal oscillator may be used as the clock
source for Timer3. The Timer1 oscillator is enabled by
setting the T1OSCEN (T1CON<3>) bit. To use it as the
Timer3 clock source, the TMR3CS bit must also be set.
As previously noted, this also configures Timer3 to
increment on every rising edge of the oscillator source.
Note:
The Special Event Triggers from the
ECCPx module will not set the TMR3IF
interrupt flag bit (PIR1<0>).
The Timer1 oscillator is described in Section 13.0
“Timer1 Module”.
TABLE 15-1: REGISTERS ASSOCIATED WITH TIMER3 AS A TIMER/COUNTER
Reset
Values
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
on Page:
INTCON
PIR2
GIE/GIEH PEIE/GIEL TMR0IE
INT0IE
—
RBIE
TMR0IF
LVDIF
LVDIE
LVDIP
INT0IF
TMR3IF
TMR3IE
TMR3IP
RBIF
57
60
60
60
61
61
58
61
OSCFIF
OSCFIE
OSCFIP
CM2IF
CM2IE
CM2IP
CM1IF
CM1IE
CM1IP
BCL1IF
BCL1IE
BCL1IP
CCP2IF
CCP2IE
CCP2IP
PIE2
—
IPR2
—
TMR3L
TMR3H
T1CON(1)
T3CON
Timer3 Register Low Byte
Timer3 Register High Byte
RD16
RD16
T1RUN T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON
T3CCP2 T3CKPS1 T3CKPS0 T3CCP1 T3SYNC TMR3CS TMR3ON
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the Timer3 module.
Note 1: Default (legacy) SFR at this address, available when WDTCON<4> = 0.
© 2009 Microchip Technology Inc.
DS39778D-page 193
PIC18F87J11 FAMILY
NOTES:
DS39778D-page 194
© 2009 Microchip Technology Inc.
PIC18F87J11 FAMILY
16.1 Timer4 Operation
16.0 TIMER4 MODULE
Timer4 can be used as the PWM time base for the
PWM mode of the ECCPx/CCPx modules. The TMR4
register is readable and writable and is cleared on any
device Reset. The input clock (FOSC/4) has a prescale
option of 1:1, 1:4 or 1:16, selected by control bits
T4CKPS1:T4CKPS0 (T4CON<1:0>). The match out-
put of TMR4 goes through a 4-bit postscaler (which
gives a 1:1 to 1:16 scaling inclusive) to generate a
TMR4 interrupt, latched in flag bit, TMR4IF (PIR3<3>).
The Timer4 timer module has the following features:
• 8-bit timer register (TMR4)
• 8-bit period register (PR4)
• Readable and writable (both registers)
• Software programmable prescaler (1:1, 1:4, 1:16)
• Software programmable postscaler (1:1 to 1:16)
• Interrupt on TMR4 match of PR4
Timer4 has a control register shown in Register 16-1.
Timer4 can be shut off by clearing control bit, TMR4ON
(T4CON<2>), to minimize power consumption. The
prescaler and postscaler selection of Timer4 are also
controlled by this register. Figure 16-1 is a simplified
block diagram of the Timer4 module.
The prescaler and postscaler counters are cleared
when any of the following occurs:
• a write to the TMR4 register
• a write to the T4CON register
• any device Reset (Power-on Reset, MCLR Reset,
Watchdog Timer Reset or Brown-out Reset)
TMR4 is not cleared when T4CON is written.
REGISTER 16-1: T4CON: TIMER4 CONTROL REGISTER
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
T4OUTPS3 T4OUTPS2 T4OUTPS1 T4OUTPS0
TMR4ON
T4CKPS1
T4CKPS0
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7
Unimplemented: Read as ‘0’
bit 6-3
T4OUTPS3:T4OUTPS0: Timer4 Output Postscale Select bits
0000= 1:1 Postscale
0001= 1:2 Postscale
•
•
•
1111= 1:16 Postscale
bit 2
TMR4ON: Timer4 On bit
1= Timer4 is on
0= Timer4 is off
bit 1-0
T4CKPS1:T4CKPS0: Timer4 Clock Prescale Select bits
00= Prescaler is 1
01= Prescaler is 4
1x= Prescaler is 16
© 2009 Microchip Technology Inc.
DS39778D-page 195
PIC18F87J11 FAMILY
16.2 Timer4 Interrupt
16.3 Output of TMR4
The Timer4 module has an 8-bit period register, PR4,
which is both readable and writable. Timer4 increments
from 00h until it matches PR4 and then resets to 00h on
the next increment cycle. The PR4 register is initialized
to FFh upon Reset.
The output of TMR4 (before the postscaler) is used
only as a PWM time base for the ECCPx/CCPx mod-
ules. It is not used as a baud rate clock for the MSSP
modules as is the Timer2 output.
FIGURE 16-1:
TIMER4 BLOCK DIAGRAM
4
1:1 to 1:16
Set TMR4IF
Postscaler
T4OUTPS3:T4OUTPS0
2
TMR4 Output
T4CKPS1:T4CKPS0
(to PWM)
TMR4/PR4
Match
Reset
TMR4
1:1, 1:4, 1:16
Prescaler
FOSC/4
Comparator
PR4
8
8
8
Internal Data Bus
TABLE 16-1: REGISTERS ASSOCIATED WITH TIMER4 AS A TIMER/COUNTER
Reset
Values
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
on Page:
INTCON GIE/GIEH PEIE/GIEL TMR0IE
INT0IE
TX2IP
TX2IF
TX2IE
RBIE
TMR0IF
CCP5IP
CCP5IF
CCP5IE
INT0IF
CCP4IP
CCP4IF
CCP4IE
RBIF
57
60
60
60
61
61
61
IPR3
SSP2IP
SSP2IF
SSP2IE
BCL2IP
BCL2IF
BCL2IE
RC2IP
RC2IF
RC2IE
TMR4IP
TMR4IF
TMR4IE
CCP3IP
CCP3IF
CCP3IE
PIR3
PIE3
TMR4
T4CON
PR4
Timer4 Register
T4OUTPS3 T4OUTPS2 T4OUTPS1 T4OUTPS0 TMR4ON T4CKPS1 T4CKPS0
Timer4 Period Register
—
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the Timer4 module.
DS39778D-page 196
© 2009 Microchip Technology Inc.
PIC18F87J11 FAMILY
Capture and Compare operations described in this
chapter apply to all standard and Enhanced CCP
modules. The operations of PWM mode, described in
Section 17.4 “PWM Mode”, apply to CCP4 and CCP5
only.
17.0 CAPTURE/COMPARE/PWM
(CCP) MODULES
Members of the PIC18F87J11 family of devices all have
a total of five CCP (Capture/Compare/PWM) modules.
Two of these (CCP4 and CCP5) implement standard
Capture, Compare and Pulse-Width Modulation (PWM)
modes and are discussed in this section. The other three
modules (ECCP1, ECCP2, ECCP3) implement
standard Capture and Compare modes, as well as
Enhanced PWM modes. These are discussed in
Section 18.0 “Enhanced Capture/Compare/PWM
(ECCP) Module”.
Note: Throughout this section and Section 18.0
“Enhanced Capture/Compare/PWM (ECCP)
Module”, references to register and bit names
that may be associated with a specific CCP
module are referred to generically by the use of
‘x’ or ‘y’ in place of the specific module number.
Thus, “CCPxCON” might refer to the control
register for ECCP1, ECCP2, ECCP3, CCP4 or
CCP5.
Each CCP/ECCP module contains a 16-bit register
which can operate as a 16-bit Capture register, a 16-bit
Compare register or a PWM Master/Slave Duty Cycle
register. For the sake of clarity, all CCP module opera-
tion in the following sections is described with respect
to CCP4, but is equally applicable to CCP5.
REGISTER 17-1: CCPxCON: CCPx CONTROL REGISTER (CCP4 MODULE, CCP5 MODULE)
U-0
—
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
CCPxX
CCPxY
CCPxM3
CCPxM2
CCPxM1
CCPxM0
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7-6
bit 5-4
Unimplemented: Read as ‘0’
CCPx<X:Y>: PWM Duty Cycle bit 1 and bit 0 for CCPx Module
Capture mode:
Unused.
Compare mode:
Unused.
PWM mode:
These bits are the two Least Significant bits (bit 1 and bit 0) of the 10-bit PWM duty cycle. The eight Most
Significant bits (DCx9:DCx2) of the duty cycle are found in CCPRxL.
bit 3-0
CCPxM3:CCPxM0: CCPx Module Mode Select bits
0000= Capture/Compare/PWM disabled (resets CCPx module)
0001= Reserved
0010= Compare mode, toggle output on match (CCPxIF bit is set)
0011= Reserved
0100= Capture mode: every falling edge
0101= Capture mode: every rising edge
0110= Capture mode: every 4th rising edge
0111= Capture mode: every 16th rising edge
1000= Compare mode: initialize CCPx pin low; on compare match, force CCPx pin high (CCPxIF bit is set)
1001= Compare mode: initialize CCPx pin high; on compare match, force CCPx pin low (CCPxIF bit is set)
1010= Compare mode: generate software interrupt on compare match (CCPxIF bit is set,
CCPx pin reflects I/O state)
1011= Compare mode: trigger special event, reset timer, start A/D conversion on CCPx match
(CCPxIF bit is set)(1)
11xx= PWM mode
© 2009 Microchip Technology Inc.
DS39778D-page 197
PIC18F87J11 FAMILY
The assignment of a particular timer to a module is
determined by the timer to CCP enable bits in the
T3CON register (Register 15-1, page 191). Depending
on the configuration selected, up to four timers may be
active at once, with modules in the same configuration
(Capture/Compare or PWM) sharing timer resources.
The possible configurations are shown in Figure 17-1.
17.1 CCP Module Configuration
Each Capture/Compare/PWM module is associated
with a control register (generically, CCPxCON) and a
data register (CCPRx). The data register, in turn, is
comprised of two 8-bit registers: CCPRxL (low byte)
and CCPRxH (high byte). All registers are both
readable and writable.
17.1.2
OPEN-DRAIN OUTPUT OPTION
17.1.1
CCP MODULES AND TIMER
RESOURCES
When operating in Output mode (i.e., in Compare or
PWM modes), the drivers for the CCP pins can be
optionally configured as open-drain outputs. This feature
allows the voltage level on the pin to be pulled to a higher
level through an external pull-up resistor, and allows the
output to communicate with external circuits without the
need for additional level shifters. For more information,
see Section 10.1.4 “Open-Drain Outputs”.
The ECCP/CCP modules utilize Timers 1, 2, 3 or 4,
depending on the mode selected. Timer1 and Timer3
are available to modules in Capture or Compare
modes, while Timer2 and Timer4 are available for
modules in PWM mode.
TABLE 17-1: CCP MODE – TIMER
RESOURCE
The open-drain output option is controlled by the bits in
the ODCON1 register. Setting the appropriate bit con-
figures the pin for the corresponding module for
open-drain operation. The ODCON1 memory shares
the same address space as TMR1H. The ODCON1
register can be accessed by setting the ADSHR bit in
the WDTCON register (WDTCON<4>).
CCP Mode
Timer Resource
Capture
Compare
PWM
Timer1 or Timer3
Timer1 or Timer3
Timer2 or Timer4
FIGURE 17-1:
ECCPx/CCPx AND TIMER INTERCONNECT CONFIGURATIONS
T3CCP<2:1> = 00
T3CCP<2:1> = 01
T3CCP<2:1> = 10
T3CCP<2:1> = 11
TMR1
TMR3
TMR1
TMR3
TMR1
TMR3
TMR1
TMR3
ECCP1
ECCP1
ECCP2
ECCP3
CCP4
ECCP1
ECCP2
ECCP1
ECCP2
ECCP3
CCP4
ECCP2
ECCP3
CCP4
ECCP3
CCP4
CCP5
CCP5
CCP5
CCP5
TMR2
TMR4
TMR2
TMR4
TMR2
TMR4
TMR2
TMR4
Timer1 is used for all Capture Timer1 and Timer2 are used Timer1 and Timer2 are used Timer3 is used for all Capture
and Compare operations for for Capture and Compare or for Capture and Compare or and Compare operations for
all CCP modules. Timer2 is PWM operations for ECCP1 PWM operations for ECCP1 all CCP modules. Timer4 is
used for PWM operations for only (depending on selected and ECCP2 only (depending used for PWM operations for
all CCP modules. Modules mode).
may share either timer
on the mode selected for each all CCP modules. Modules
module). Both modules may may share either timer
use a timer as a common time resource as a common time
base if they are both in base.
All other modules use either
resource as a common time
base.
Timer3 or Timer4. Modules
may share either timer
Capture/Compare or PWM
modes.
Timer3 and Timer4 are not resource as a common time
Timer1 and Timer2 are not
available.
base
if
they
are
in
available.
Capture/Compare or PWM The other modules use either
modes.
Timer3 or Timer4. Modules
may share either timer
resource as a common time
base
if
they
are
in
Capture/Compare or PWM
modes.
DS39778D-page 198
© 2009 Microchip Technology Inc.
PIC18F87J11 FAMILY
17.2.3
SOFTWARE INTERRUPT
17.2 Capture Mode
When the Capture mode is changed, a false capture
interrupt may be generated. The user should keep the
CCPxIE interrupt enable bit clear to avoid false
interrupts. The interrupt flag bit, CCPxIF, should also be
cleared following any such change in operating mode.
In Capture mode, the CCPRxH:CCPRxL register pair
captures the 16-bit value of the TMR1 or TMR3
registers when an event occurs on the corresponding
CCP pin. An event is defined as one of the following:
• every falling edge
• every rising edge
17.2.4
CCP PRESCALER
• every 4th rising edge
• every 16th rising edge
There are four prescaler settings in Capture mode.
They are specified as part of the operating mode
selected by the mode select bits (CCPxM3:CCPxM0).
Whenever the CCP module is turned off or Capture
mode is disabled, the prescaler counter is cleared. This
means that any Reset will clear the prescaler counter.
The event is selected by the mode select bits,
CCPxM3:CCPxM0 (CCPxCON<3:0>). When a capture
is made, the interrupt request flag bit, CCPxIF, is set; it
must be cleared in software. If another capture occurs
before the value in register CCPRx is read, the old
captured value is overwritten by the new captured value.
Switching from one capture prescaler to another may
generate an interrupt. Also, the prescaler counter will
not be cleared; therefore, the first capture may be from
17.2.1
CCP PIN CONFIGURATION
a
non-zero prescaler. Example 17-1 shows the
recommended method for switching between capture
prescalers. This example also clears the prescaler
counter and will not generate the “false” interrupt.
In Capture mode, the appropriate CCP pin should be
configured as an input by setting the corresponding
TRIS direction bit.
Note:
If RG4/CCP5 is configured as an output, a
write to the port can cause a capture
condition.
EXAMPLE 17-1:
CHANGING BETWEEN
CAPTURE PRESCALERS
(CCP5 SHOWN)
CLRF
CCP5CON
; Turn CCP module off
17.2.2
TIMER1/TIMER3 MODE SELECTION
MOVLW NEW_CAPT_PS ; Load WREG with the
; new prescaler mode
The timers that are to be used with the capture feature
(Timer1 and/or Timer3) must be running in Timer mode or
Synchronized Counter mode. In Asynchronous Counter
mode, the capture operation will not work. The timer to be
used with each CCP module is selected in the T3CON
register (see Section 17.1.1 “CCP Modules and Timer
Resources”).
; value and CCP ON
; Load CCP5CON with
; this value
MOVWF CCP5CON
FIGURE 17-2:
CAPTURE MODE OPERATION BLOCK DIAGRAM
TMR3H
TMR3L
Set CCP4IF
T3CCP2
TMR3
Enable
CCP4 pin
Prescaler
÷ 1, 4, 16
and
Edge Detect
CCPR4H
CCPR4L
TMR1
Enable
T3CCP2
TMR1H
TMR3H
TMR1L
TMR3L
4
4
CCP4CON<3:0>
Q1:Q4
Set CCP5IF
4
CCP5CON<3:0>
T3CCP1
T3CCP2
TMR3
Enable
CCP5 pin
Prescaler
÷ 1, 4, 16
and
Edge Detect
CCPR5H
CCPR5L
TMR1L
TMR1
Enable
T3CCP2
T3CCP1
TMR1H
© 2009 Microchip Technology Inc.
DS39778D-page 199
PIC18F87J11 FAMILY
17.3 Compare Mode
Note:
Clearing the CCP5CON register will force
the RG4 compare output latch (depend-
ing on device configuration) to the default
low level. This is not the PORTB or
PORTC I/O data latch.
In Compare mode, the 16-bit CCPRx register value is
constantly compared against either the TMR1 or TMR3
register pair value. When a match occurs, the CCP pin
can be:
• driven high
17.3.2
TIMER1/TIMER3 MODE SELECTION
• driven low
Timer1 and/or Timer3 must be running in Timer mode
or Synchronized Counter mode if the CCP module is
using the compare feature. In Asynchronous Counter
mode, the compare operation may not work.
• toggled (high-to-low or low-to-high)
• remains unchanged (that is, reflects the state of
the I/O latch)
The action on the pin is based on the value of the mode
select bits (CCPxM3:CCPxM0). At the same time, the
interrupt flag bit, CCPxIF, is set.
17.3.3
SOFTWARE INTERRUPT MODE
When the Generate Software Interrupt mode is chosen
(CCPxM3:CCPxM0 = 1010), the corresponding CCP
pin is not affected. Only a CCP interrupt is generated,
if enabled, and the CCPxIE bit is set.
17.3.1
CCP PIN CONFIGURATION
The user must configure the CCP pin as an output by
clearing the appropriate TRIS bit.
FIGURE 17-3:
COMPARE MODE OPERATION BLOCK DIAGRAM
Set CCP4IF
CCPR4H
CCPR4L
CCP4 pin
S
R
Q
Compare
Match
Output
Logic
Comparator
TRIS
Output Enable
4
CCP4CON<3:0>
TMR1H
TMR3H
TMR1L
TMR3L
0
1
0
1
T3CCP1
T3CCP2
Set CCP5IF
CCP5 pin
S
R
Q
Compare
Match
Output
Logic
Comparator
TRIS
Output Enable
4
CCPR5H
CCPR5L
CCP5CON<3:0>
DS39778D-page 200
© 2009 Microchip Technology Inc.
PIC18F87J11 FAMILY
TABLE 17-2: REGISTERS ASSOCIATED WITH CAPTURE, COMPARE, TIMER1 AND TIMER3
Reset
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Values
on Page:
INTCON
RCON
GIE/GIEH PEIE/GIEL TMR0IE
INT0IE
RI
RBIE
TO
TMR0IF
PD
INT0IF
POR
RBIF
57
58
60
60
60
60
60
60
60
60
60
60
58
58
58
58
61
61
61
61
61
61
61
61
61
IPEN
PMPIF
PMPIE
PMPIP
OSCFIF
OSCFIE
OSCFIP
SSP2IF
SSP2IE
SSP2IP
—
—
CM
BOR
PIR1
ADIF
RC1IF
RC1IE
RC1IP
CM1IF
CM1IE
CM1IP
RC2IF
RC2IE
RC2IP
—
TX1IF
TX1IE
TX1IP
—
SSP1IF
SSP1IE
SSP1IP
BCL1IF
BCL1IE
BCL1IP
TMR4IF
TMR4IE
TMR4IP
TRISG3
CCP1IF
CCP1IE
CCP1IP
LVDIF
TMR2IF
TMR2IE
TMR2IP
TMR3IF
TMR3IE
TMR3IP
CCP4IF
CCP4IE
CCP4IP
TRISG1
TMR1IF
TMR1IE
TMR1IP
CCP2IF
CCP2IE
CCP2IP
CCP3IF
CCP3IE
CCP3IP
TRISG0
PIE1
ADIE
IPR1
ADIP
PIR2
CM2IF
CM2IE
CM2IP
BCL2IF
BCL2IE
BCL2IP
—
PIE2
—
LVDIE
IPR2
—
LVDIP
PIR3
TX2IF
TX2IE
TX2IP
TRISG4
CCP5IF
CCP5IE
CCP5IP
TRISG2
PIE3
IPR3
TRISG
TMR1L(1)
TMR1H(1)
ODCON1(2)
T1CON(1)
TMR3H
TMR3L
T3CON
CCPR4L
CCPR4H
CCPR5L
CCPR5H
CCP4CON
CCP5CON
Timer1 Register Low Byte
Timer1 Register High Byte
—
—
—
CCP5OD CCP4OD ECCP3OD ECCP2OD ECCP1OD
RD16
T1RUN T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON
Timer3 Register High Byte
Timer3 Register Low Byte
RD16
T3CCP2 T3CKPS1 T3CKPS0 T3CCP1 T3SYNC TMR3CS TMR3ON
Capture/Compare/PWM Register 4 Low Byte
Capture/Compare/PWM Register 4 High Byte
Capture/Compare/PWM Register 5 Low Byte
Capture/Compare/PWM Register 5 High Byte
—
—
—
—
DC4B1
DC5B1
DC4B0
DC5B0
CCP4M3 CCP4M2 CCP4M1 CCP4M0
CCP5M3 CCP5M2 CCP5M1 CCP5M0
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by Capture/Compare, Timer1 or Timer3.
Note 1: Default (legacy) SFR at this address, available when WDTCON<4> = 0.
2: Configuration SFR, overlaps with default SFR at this address; available only when WDTCON<4> = 1.
© 2009 Microchip Technology Inc.
DS39778D-page 201
PIC18F87J11 FAMILY
17.4.1
PWM PERIOD
17.4 PWM Mode
The PWM period is specified by writing to the PR2
(PR4) register. The PWM period can be calculated
using Equation 17-1:
In Pulse-Width Modulation (PWM) mode, the CCP pin
produces up to a 10-bit resolution PWM output. Since
the CCP4 and CCP5 pins are multiplexed with a
PORTG data latch, the appropriate TRISG bit must be
cleared to make the CCP4 or CCP5 pin an output.
EQUATION 17-1:
PWM Period = [(PR2) + 1] • 4 • TOSC •
(TMR2 Prescale Value)
Note:
Clearing the CCP4CON or CCP5CON
register will force the RG3 or RG4 output
latch (depending on device configuration)
to the default low level. This is not the
PORTG I/O data latch.
PWM frequency is defined as 1/[PWM period].
When TMR2 (TMR4) is equal to PR2 (PR4), the
following three events occur on the next increment
cycle:
Figure 17-4 shows a simplified block diagram of the
CCP module in PWM mode.
For a step-by-step procedure on how to set up a CCP
module for PWM operation, see Section 17.4.3
“Setup for PWM Operation”.
• TMR2 (TMR4) is cleared
• The CCP pin is set (exception: if PWM duty
cycle = 0%, the CCP pin will not be set)
• The PWM duty cycle is latched from CCPRxL into
CCPRxH
FIGURE 17-4:
SIMPLIFIED PWM BLOCK
DIAGRAM
Note:
The Timer2 and Timer 4 postscalers (see
Section 14.0 “Timer2 Module” and
Section 16.0 “Timer4 Module”) are not
used in the determination of the PWM
frequency. The postscaler could be used
to have a servo update rate at a different
frequency than the PWM output.
Duty Cycle Register
9
0
CCPRxL
CCPxCON<5:4>
Latch
Duty Cycle
(1)
CCPRxH
Comparator
TMRx
17.4.2
PWM DUTY CYCLE
S
R
Q
CCPx
pin
The PWM duty cycle is specified by writing to the
CCPRxL register and to the CCPxCON<5:4> bits. Up
to 10-bit resolution is available. The CCPRxL contains
the eight MSbs and the CCPxCON<5:4> contains the
two LSbs. This 10-bit value is represented by
CCPRxL:CCPxCON<5:4>. Equation 17-2 is used to
calculate the PWM duty cycle in time.
Reset
TMRx = PRx
Match
2 LSbs latched
from Q clocks
Comparator
PRx
TRIS
Output Enable
Set CCPx pin
EQUATION 17-2:
Note 1: The two LSbs of the Duty Cycle register are held by a
2-bit latch that is part of the module’s hardware. It is
physically separate from the CCPRx registers.
PWM Duty Cycle = (CCPRXL:CCPXCON<5:4>) •
TOSC • (TMR2 Prescale Value)
A PWM output (Figure 17-5) has a time base (period)
and a time that the output stays high (duty cycle).
The frequency of the PWM is the inverse of the
period (1/period).
CCPRxL and CCPxCON<5:4> can be written to at any
time, but the duty cycle value is not latched into
CCPRxH until after a match between PR2 (PR4) and
TMR2 (TMR4) occurs (i.e., the period is complete). In
PWM mode, CCPRxH is a read-only register.
FIGURE 17-5:
PWM OUTPUT
Period
Duty Cycle
TMR2 (TMR4) = PR2 (PR4)
TMR2 (TMR4) = Duty Cycle
TMR2 (TMR4) = PR2 (TMR4)
DS39778D-page 202
© 2009 Microchip Technology Inc.
PIC18F87J11 FAMILY
The CCPRxH register and a 2-bit internal latch are
used to double-buffer the PWM duty cycle. This
double-buffering is essential for glitchless PWM
operation.
17.4.3
SETUP FOR PWM OPERATION
The following steps should be taken when configuring
the CCP module for PWM operation:
1. Set the PWM period by writing to the PR2 (PR4)
register.
When the CCPRxH and 2-bit latch match TMR2
(TMR4), concatenated with an internal 2-bit Q clock or
2 bits of the TMR2 (TMR4) prescaler, the CCP pin is
cleared.
2. Set the PWM duty cycle by writing to the
CCPRxL register and CCPxCON<5:4> bits.
3. Make the CCP pin an output by clearing the
appropriate TRIS bit.
The maximum PWM resolution (bits) for a given PWM
frequency is given by Equation 17-3:
4. Set the TMR2 (TMR4) prescale value, then
enable Timer2 (Timer4) by writing to T2CON
(T4CON).
EQUATION 17-3:
FOSC
5. Configure the CCP module for PWM operation.
log( )
FPWM
log(2)
PWM Resolution (max) =
bits
Note:
If the PWM duty cycle value is longer than
the PWM period, the CCP pin will not be
cleared.
TABLE 17-3: EXAMPLE PWM FREQUENCIES AND RESOLUTIONS AT 40 MHz
PWM Frequency
2.44 kHz
9.77 kHz
39.06 kHz 156.25 kHz 312.50 kHz 416.67 kHz
Timer Prescaler (1, 4, 16)
PR2 Value
16
FFh
10
4
1
1
3Fh
8
1
1Fh
7
1
FFh
10
FFh
10
17h
6.58
Maximum Resolution (bits)
© 2009 Microchip Technology Inc.
DS39778D-page 203
PIC18F87J11 FAMILY
TABLE 17-4: REGISTERS ASSOCIATED WITH PWM, TIMER2 AND TIMER4
Reset
Values
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
on Page:
INTCON
RCON
PIR1
GIE/GIEH PEIE/GIEL
TMR0IE
CM
INT0IE
RI
RBIE
TO
TMR0IF
PD
INT0IF
POR
RBIF
57
58
60
60
60
60
60
60
60
58
58
58
61
61
61
61
61
61
61
61
61
58
IPEN
PMPIF
PMPIE
PMPIP
SSP2IF
SSP2IE
SSP2IP
—
—
BOR
ADIF
RC1IF
RC1IE
RC1IP
RC2IF
RC2IE
RC2IP
—
TX1IF
TX1IE
TX1IP
TX2IF
TX2IE
TX2IP
TRISG4
SSP1IF
SSP1IE
SSP1IP
TMR4IF
TMR4IE
TMR4IP
TRISG3
CCP1IF
CCP1IE
CCP1IP
CCP5IF
CCP5IE
CCP5IP
TRISG2
TMR2IF
TMR2IE
TMR2IP
CCP4IF
CCP4IE
CCP4IP
TRISG1
TMR1IF
TMR1IE
TMR1IP
CCP3IF
CCP3IE
CCP3IP
TRISG0
PIE1
ADIE
ADIP
BCL2IF
BCL2IE
BCL2IP
—
IPR1
PIR3
PIE3
IPR3
TRISG
(1)
TMR2
Timer2 Register
(1)
PR2
Timer2 Period Register
T2CON
TMR4
—
T2OUTPS3 T2OUTPS2 T2OUTPS1 T2OUTPS0 TMR2ON T2CKPS1 T2CKPS0
Timer4 Register
PR4
Timer4 Period Register
T4CON
CCPR4L
CCPR4H
CCPR5L
CCPR5H
CCP4CON
CCP5CON
—
T4OUTPS3 T4OUTPS2 T4OUTPS1 T4OUTPS0 TMR4ON T4CKPS1 T4CKPS0
Capture/Compare/PWM Register 4 Low Byte
Capture/Compare/PWM Register 4 High Byte
Capture/Compare/PWM Register 5 Low Byte
Capture/Compare/PWM Register 5 High Byte
—
—
—
—
—
—
DC4B1
DC5B1
—
DC4B0
DC5B0
CCP4M3
CCP5M3
CCP4M2 CCP4M1 CCP4M0
CCP5M2 CCP5M1 CCP5M0
(2)
ODCON1
CCP5OD
CCP4OD ECCP3OD ECCP2OD ECCP1OD
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PWM, Timer2 or Timer4.
Note 1: Default (legacy) SFR at this address, available when WDTCON<4> = 0.
2: Configuration SFR, overlaps with default SFR at this address; available only when WDTCON<4> = 1.
DS39778D-page 204
© 2009 Microchip Technology Inc.
PIC18F87J11 FAMILY
The control register for the Enhanced CCP module is
shown in Register 18-1. It differs from the CCP4CON/
CCP5CON registers in that the two Most Significant
bits are implemented to control PWM functionality.
18.0 ENHANCED CAPTURE/
COMPARE/PWM (ECCP)
MODULE
In the PIC18F87J11 family of devices, three of the CCP
modules are implemented as standard CCP modules
with Enhanced PWM capabilities. These include the
provision for 2 or 4 output channels, user-selectable
polarity, dead-band control and automatic shutdown
and restart. The Enhanced features are discussed in
detail in Section 18.4 “Enhanced PWM Mode”.
Capture, Compare and single-output PWM functions of
the ECCP module are the same as described for the
standard CCP module.
In addition to the expanded range of modes available
through the Enhanced CCPxCON register, the ECCP
modules each have two additional registers associated
with Enhanced PWM operation and auto-shutdown
features. They are:
• ECCPxDEL (ECCPx PWM Delay)
• ECCPxAS (ECCPx Auto-Shutdown Control)
REGISTER 18-1: CCPxCON: ECCPx CONTROL REGISTER (ECCP1/ECCP2/ECCP3)
R/W-0
PxM1
R/W-0
PxM0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
DCxB1
DCxB0
CCPxM3
CCPxM2
CCPxM1
CCPxM0
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7-6
PxM1:PxM0: Enhanced PWM Output Configuration bits
If CCPxM3:CCPxM2 = 00, 01, 10:
xx= PxA assigned as Capture/Compare input/output; PxB, PxC, PxD assigned as port pins
If CCPxM3:CCPxM2 = 11:
00= Single output: PxA modulated; PxB, PxC, PxD assigned as port pins
01= Full-bridge output forward: P1D modulated; P1A active; P1B, P1C inactive
10= Half-bridge output: P1A, P1B modulated with dead-band control; P1C, P1D assigned as port pins
11= Full-bridge output reverse: P1B modulated; P1C active; P1A, P1D inactive
bit 5-4
DCxB1:DCxB0: PWM Duty Cycle bit 1 and bit 0
Capture mode:
Unused.
Compare mode:
Unused.
PWM mode:
These bits are the two LSbs of the 10-bit PWM duty cycle. The eight MSbs of the duty cycle are found in CCPRxL.
© 2009 Microchip Technology Inc.
DS39778D-page 205
PIC18F87J11 FAMILY
REGISTER 18-1: CCPxCON: ECCPx CONTROL REGISTER (ECCP1/ECCP2/ECCP3)
bit 3-0
CCPxM3:CCPxM0: Enhanced CCPx Module Mode Select bits
0000= Capture/Compare/PWM off (resets ECCPx module)
0001= Reserved
0010= Compare mode, toggle output on match
0011= Capture mode
0100= Capture mode: every falling edge
0101= Capture mode: every rising edge
0110= Capture mode: every 4th rising edge
0111= Capture mode: every 16th rising edge
1000= Compare mode: initialize ECCPx pin low; set output on compare match (set CCPxIF)
1001= Compare mode: initialize ECCPx pin high; clear output on compare match (set CCPxIF)
1010= Compare mode: generate software interrupt only; ECCPx pin reverts to I/O state
1011= Compare mode: trigger special event (ECCPx resets TMR1 or TMR3, sets CCPxIF bit,
(1)
ECCPx trigger also starts A/D conversion if A/D module is enabled)
1100= PWM mode: PxA, PxC active-high; PxB, PxD active-high
1101= PWM mode: PxA, PxC active-high; PxB, PxD active-low
1110= PWM mode: PxA, PxC active-low; PxB, PxD active-high
1111= PWM mode: PxA, PxC active-low; PxB, PxD active-low
Note 1: Implemented only for ECCP1 and ECCP2; same as ‘1010’ for ECCP3.
An exception to this configuration is when a 12-bit
18.1 ECCP Outputs and Configuration
address width is selected for the external bus
(EMB1:EMB0 Configuration bits = 01). In this case, the
upper pins of PORTE continue to operate as digital I/O,
even when the external bus is active. P1B/P1C and
P3B/P3C remain available for use as Enhanced PWM
outputs.
Each of the Enhanced CCP modules may have up to
four PWM outputs, depending on the selected
operating mode. These outputs, designated PxA
through PxD, are multiplexed with various I/O pins.
Some ECCP pin assignments are constant, while
others change based on device configuration. For
those pins that do change, the controlling bits are:
If an application requires the use of additional PWM
outputs during enhanced microcontroller operation, the
P1B/P1C and P3B/P3C outputs can be reassigned to
the upper bits of PORTH. This is done by clearing the
ECCPMX Configuration bit.
• CCP2MX Configuration bit
• ECCPMX Configuration bit (80-pin devices only)
• Program Memory Operating mode, set by the
EMB Configuration bits (80-pin devices only)
18.1.2
ECCP2 OUTPUTS AND PROGRAM
MEMORY MODES
The pin assignments for the Enhanced CCP modules
are summarized in Table 18-1, Table 18-2 and
Table 18-3. To configure the I/O pins as PWM outputs,
the proper PWM mode must be selected by setting the
PxMx and CCPxMx bits (CCPxCON<7:6> and <3:0>,
respectively). The appropriate TRIS direction bits for
the corresponding port pins must also be set as
outputs.
For 80-pin devices, the program memory mode of the
device (Section 5.1.3 “PIC18F8xJ11/8XJ16 Program
Memory Modes”) also impacts pin multiplexing for the
module.
The ECCP2 input/output (ECCP2/P2A) can be
multiplexed to one of three pins. The default
assignment (CCP2MX Configuration bit is set) for all
devices is RC1. Clearing CCP2MX reassigns ECCP2/
P2A to RE7.
18.1.1
ECCP1/ECCP3 OUTPUTS AND
PROGRAM MEMORY MODE
In 80-pin devices, the use of Extended Microcontroller
mode has an indirect effect on the use of ECCP1 and
ECCP3 in Enhanced PWM modes. By default, PWM
outputs, P1B/P1C and P3B/P3C, are multiplexed to
PORTE pins along with the high-order byte of the
external memory bus. When the bus is active in
Extended Microcontroller mode, it overrides the
Enhanced CCP outputs and makes them unavailable.
Because of this, ECCP1 and ECCP3 can only be used
in compatible (single output) PWM modes when the
device is in Extended Microcontroller mode and default
pin configuration.
An additional option exists for 80-pin devices. When
these devices are operating in Microcontroller mode,
the multiplexing options described above still apply. In
Extended Microcontroller mode, clearing CCP2MX
reassigns ECCP2/P2A to RB3.
Changing the pin assignment of ECCP2 does not
automatically change any requirements for configuring
the port pin. Users must always verify that the
appropriate TRIS register is configured correctly for
ECCP2 operation regardless of where it is located.
DS39778D-page 206
© 2009 Microchip Technology Inc.
PIC18F87J11 FAMILY
18.1.3
USE OF CCP4 AND CCP5 WITH
ECCP1 AND ECCP3
18.1.5
OPEN-DRAIN OUTPUT OPTION
When operating in compare or standard PWM modes,
the drivers for the ECCP pins can be optionally
configured as open-drain outputs. This feature allows
the voltage level on the pin to be pulled to a higher level
through an external pull-up resistor, and allows the
output to communicate with external circuits without the
need for additional level shifters. For more information,
see Section 10.1.4 “Open-Drain Outputs”
Only the ECCP2 module has four dedicated output pins
that are available for use. Assuming that the I/O ports
or other multiplexed functions on those pins are not
needed, they may be used whenever needed without
interfering with any other CCP module.
ECCP1 and ECCP3, on the other hand, only have
three dedicated output pins: ECCPx/PxA, PxB and
PxC. Whenever these modules are configured for
Quad PWM mode, the pin normally used for CCP4 or
CCP5 becomes the PxD output pins for ECCP3 and
ECCP1, respectively. The CCP4 and CCP5 modules
remain functional but their outputs are overridden.
The open-drain output option is controlled by the bits in
the ODCON1 register. Setting the appropriate bit
configures the pin for the corresponding module for
open-drain operation. The ODCON1 memory shares
the same address space as of TMR1H. The ODCON1
register can be accessed by setting the ADSHR bit in
the WDTCON register (WDTCON<4>).
18.1.4
ECCP MODULES AND TIMER
RESOURCES
Like the standard CCP modules, the ECCP modules
can utilize Timers 1, 2, 3 or 4, depending on the mode
selected. Timer1 and Timer3 are available for modules
in Capture or Compare modes, while Timer2 and
Timer4 are available for modules in PWM mode.
Additional details on timer resources are provided in
Section 17.1.1
“CCP
Modules
and
Timer
Resources”.
TABLE 18-1: PIN CONFIGURATIONS FOR ECCP1
CCP1CON
ECCP Mode
RC2
RE6
RE5
RG4
RH7
RH6
Configuration
All PIC18F6XJ1X Devices:
Compatible CCP 00xx 11xx
ECCP1
P1A
RE6
P1B
P1B
RE5
RE5
P1C
RG4/CCP5
RG4/CCP5
P1D
N/A
N/A
N/A
N/A
N/A
N/A
Dual PWM
10xx 11xx
x1xx 11xx
Quad PWM(1)
P1A
PIC18F8XJ1X Devices, ECCPMX = 0, Microcontroller mode:
Compatible CCP 00xx 11xx
ECCP1
P1A
RE6/AD14 RE5/AD13 RG4/CCP5 RH7/AN15 RH6/AN14
Dual PWM
10xx 11xx
x1xx 11xx
RE6/AD14 RE5/AD13 RG4/CCP5
RE6/AD14 RE5/AD13 P1D
P1B
P1B
RH6/AN14
P1C
Quad PWM(1)
P1A
PIC18F8XJ1X Devices, ECCPMX = 1, Extended Microcontroller mode, 16-Bit or 20-Bit Address Width:
Compatible CCP 00xx 11xx ECCP1 RE6/AD14 RE5/AD13 RG4/CCP5 RH7/AN15 RH6/AN14
PIC18F8XJ1X Devices, ECCPMX = 1,
Microcontroller mode or Extended Microcontroller mode, 12-Bit Address Width:
Compatible CCP 00xx 11xx
ECCP1
P1A
RE6/AD14 RE5/AD13 RG4/CCP5 RH7/AN15 RH6/AN14
Dual PWM
10xx 11xx
x1xx 11xx
P1B
P1B
RE5/AD13 RG4/CCP5 RH7/AN15 RH6/AN14
P1C P1D RH7/AN15 RH6/AN14
Quad PWM(1)
P1A
Legend: x= Don’t care, N/A = Not Available. Shaded cells indicate pin assignments not used by ECCP1 in a given mode.
Note 1: With ECCP1 in Quad PWM mode, CCP5’s output is overridden by P1D; otherwise, CCP5 is fully operational.
© 2009 Microchip Technology Inc.
DS39778D-page 207
PIC18F87J11 FAMILY
TABLE 18-2: PIN CONFIGURATIONS FOR ECCP2
CCP2CON
ECCP Mode
RB3
RC1
RE7
RE2
RE1
RE0
Configuration
All Devices, CCP2MX = 1, Either Operating mode:
Compatible CCP 00xx 11xx
RB3/INT3
RB3/INT3
RB3/INT3
ECCP2
P2A
RE7
RE7
RE7
RE2
P2B
P2B
RE1
RE1
P2C
RE0
RE0
P2D
Dual PWM
Quad PWM
10xx 11xx
x1xx 11xx
P2A
All Devices, CCP2MX = 0, Microcontroller mode:
Compatible CCP 00xx 11xx
RB3/INT3 RC1/T1OS1
RB3/INT3 RC1/T1OS1
RB3/INT3 RC1/T1OS1
ECCP2
P2A
RE2
P2B
P2B
RE1
RE1
P2C
RE0
RE0
P2D
Dual PWM
Quad PWM
10xx 11xx
x1xx 11xx
P2A
PIC18F8XJ1X Devices, CCP2MX = 0, Extended Microcontroller mode:
Compatible CCP 00xx 11xx
ECCP2
P2A
RC1/T1OS1 RE7/AD15
RC1/T1OS1 RE7/AD15
RC1/T1OS1 RE7/AD15
RE2/CS
P2B
RE1/WR
RE1/WR
P2C
RE0/RD
RE0/RD
P2D
Dual PWM
Quad PWM
10xx 11xx
x1xx 11xx
P2A
P2B
Legend: x= Don’t care. Shaded cells indicate pin assignments not used by ECCP2 in a given mode.
TABLE 18-3: PIN CONFIGURATIONS FOR ECCP3
CCP3CON
ECCP Mode
RG0
RE4
RE3
RG3
RH5
RH4
Configuration
PIC18F6XJ1X Devices:
Compatible CCP 00xx 11xx
ECCP3
P3A
RE4
P3B
P3B
RE3
RE3
P3C
RG3/CCP4
RG3/CCP4
P3D
N/A
N/A
N/A
N/A
N/A
N/A
Dual PWM
10xx 11xx
x1xx 11xx
Quad PWM(1)
P3A
PIC18F8XJ1X Devices, ECCPMX = 0, Microcontroller mode:
Compatible CCP 00xx 11xx
ECCP3
P3A
RE6/AD14 RE5/AD13 RG3/CCP4 RH7/AN15 RH6/AN14
Dual PWM
10xx 11xx
x1xx 11xx
RE6/AD14 RE5/AD13 RG3/CCP4
RE6/AD14 RE5/AD13 P3D
P3B
P3B
RH6/AN14
P3C
Quad PWM(1)
P3A
PIC18F8XJ1X Devices, ECCPMX = 1, Extended Microcontroller mode, 16-Bit or 20-Bit Address Width:
Compatible CCP 00xx 11xx ECCP3 RE6/AD14 RE5/AD13 RG3/CCP4 RH7/AN15 RH6/AN14
PIC18F8XJ1X Devices, ECCPMX = 1,
Microcontroller mode or Extended Microcontroller mode, 12-Bit Address Width:
Compatible CCP 00xx 11xx
ECCP3
P3A
RE4/AD12 RE3/AD11 RG3/CCP4 RH5/AN13 RH4/AN12
Dual PWM
10xx 11xx
x1xx 11xx
P3B
P3B
RE3/AD11 RG3/CCP4 RH5/AN13 RH4/AN12
P3C P3D RH5/AN13 RH4/AN12
Quad PWM(1)
P3A
Legend: x= Don’t care, N/A = Not Available. Shaded cells indicate pin assignments not used by ECCP3 in a given mode.
Note 1: With ECCP3 in Quad PWM mode, CCP4’s output is overridden by P1D; otherwise, CCP4 is fully operational.
DS39778D-page 208
© 2009 Microchip Technology Inc.
PIC18F87J11 FAMILY
18.2 Capture and Compare Modes
18.3 Standard PWM Mode
Except for the operation of the Special Event Trigger
discussed below, the Capture and Compare modes of
the ECCP module are identical in operation to that of
CCP4. These are discussed in detail in Section 17.2
“Capture Mode” and Section 17.3 “Compare
Mode”.
When configured in Single Output mode, the ECCP
module functions identically to the standard CCP
module in PWM mode, as described in Section 17.4
“PWM Mode”. This is also sometimes referred to as
“Compatible CCP” mode as in Tables 18-1
through 18-3.
Note:
When setting up single output PWM
operations, users are free to use either of
the processes described in Section 17.4.3
“Setup for PWM Operation” or
Section 18.4.9 “Setup for PWM Opera-
tion”. The latter is more generic but will
work for either single or multi-output PWM.
18.2.1
SPECIAL EVENT TRIGGER
ECCP1 and ECCP2 incorporate an internal hardware
trigger that is generated in Compare mode on a match
between the CCPRx register pair and the selected
timer. This can be used in turn to initiate an action. This
mode is selected by setting CCPxCON<3:0> to ‘1011’.
The Special Event Trigger output of either ECCP1 or
ECCP2 resets the TMR1 or TMR3 register pair, depend-
ing on which timer resource is currently selected. This
allows the CCPRx register pair to effectively be a 16-bit
programmable period register for Timer1 or Timer3. In
addition, the ECCP2 Special Event Trigger will also start
an A/D conversion if the A/D module is enabled.
Special Event Triggers are not implemented for
ECCP3, CCP4 or CCP5. Selecting the Special Event
Trigger mode for these modules has the same effect as
selecting the Compare with Software Interrupt mode
(CCPxM3:CCPxM0 = 1010).
Note:
The Special Event Trigger from ECCP2
will not set the Timer1 or Timer3 interrupt
flag bits.
© 2009 Microchip Technology Inc.
DS39778D-page 209
PIC18F87J11 FAMILY
Enhanced PWM waveforms do not exactly match the
standard PWM waveforms, but are instead offset by
one full instruction cycle (4 TOSC).
18.4 Enhanced PWM Mode
The Enhanced PWM mode provides additional PWM
output options for a broader range of control applica-
tions. The module is a backward compatible version of
the standard CCP module and offers up to four outputs,
designated PxA through PxD. Users are also able to
select the polarity of the signal (either active-high or
active-low). The module’s output mode and polarity
are configured by setting the PxM1:PxM0 and
CCPxM3:CCPxM0 bits of the CCPxCON register
(CCPxCON<7:6> and CCPxCON<3:0>, respectively).
As before, the user must manually configure the
appropriate TRIS bits for output.
18.4.1
PWM PERIOD
The PWM period is specified by writing to the PR2
register. The PWM period can be calculated using the
equation:
EQUATION 18-1:
For the sake of clarity, Enhanced PWM mode operation
is described generically throughout this section with
respect to the ECCP1 and TMR2 modules. Control reg-
ister names are presented in terms of ECCP1. All three
Enhanced modules, as well as the two timer resources,
can be used interchangeably and function identically.
TMR2 or TMR4 can be selected for PWM operation by
selecting the proper bits in T3CON.
PWM Period = [(PR2) + 1] • 4 • TOSC •
(TMR2 Prescale Value)
PWM frequency is defined as 1/[PWM period]. When
TMR2 is equal to PR2, the following three events occur
on the next increment cycle:
• TMR2 is cleared
Figure 18-1 shows a simplified block diagram of PWM
operation. All control registers are double-buffered and
are loaded at the beginning of a new PWM cycle (the
period boundary when Timer2 resets) in order to
prevent glitches on any of the outputs. The exception is
the ECCPx PWM Delay register, ECCPxDEL, which is
loaded at either the duty cycle boundary or the bound-
ary period (whichever comes first). Because of the
buffering, the module waits until the assigned timer
resets instead of starting immediately. This means that
• The ECCP1 pin is set (if PWM duty cycle = 0%,
the ECCP1 pin will not be set)
• The PWM duty cycle is copied from CCPR1L into
CCPR1H
Note:
The Timer2 postscaler (see Section 14.0
“Timer2 Module”) is not used in the
determination of the PWM frequency. The
postscaler could be used to have a servo
update rate at a different frequency than
the PWM output.
FIGURE 18-1:
SIMPLIFIED BLOCK DIAGRAM OF THE ENHANCED PWM MODULE
CCP1CON<5:4>
P1M1<1:0>
CCP1M<3:0>
4
Duty Cycle Registers
2
CCPR1L
ECCP1/P1A
P1B
ECCP1/P1A
P1B
TRISx<x>
TRISx<x>
TRISx<x>
TRISx<x>
CCPR1H (Slave)
Output
Controller
R
S
Q
Comparator
P1C
P1C
P1D
(Note 1)
TMR2
P1D
Comparator
Clear Timer,
set ECCP1 pin and
latch D.C.
PR2
ECCP1DEL
Note: The 8-bit TMR2 register is concatenated with the 2-bit internal Q clock, or 2 bits of the prescaler, to create the 10-bit time base.
DS39778D-page 210
© 2009 Microchip Technology Inc.
PIC18F87J11 FAMILY
18.4.2
PWM DUTY CYCLE
Note:
If the PWM duty cycle value is longer than
the PWM period, the ECCP1 pin will not
be cleared.
The PWM duty cycle is specified by writing to the
CCPR1L register and to the CCP1CON<5:4> bits. Up
to 10-bit resolution is available. The CCPR1L contains
the eight MSbs and the CCP1CON<5:4> contains the
two LSbs. This 10-bit value is represented by
CCPR1L:CCP1CON<5:4>. The PWM duty cycle is
calculated by the following equation:
18.4.3
PWM OUTPUT CONFIGURATIONS
The P1M1:P1M0 bits in the CCP1CON register allow
one of four configurations:
• Single Output
EQUATION 18-2:
• Half-Bridge Output
PWM Duty Cycle = (CCPR1L:CCP1CON<5:4>) •
TOSC • (TMR2 Prescale Value)
• Full-Bridge Output, Forward mode
• Full-Bridge Output, Reverse mode
The Single Output mode is the standard PWM mode
discussed in Section 18.4 “Enhanced PWM Mode”.
The Half-Bridge and Full-Bridge Output modes are
covered in detail in the sections that follow.
CCPR1L and CCP1CON<5:4> can be written to at any
time but the duty cycle value is not copied into
CCPR1H until a match between PR2 and TMR2 occurs
(i.e., the period is complete). In PWM mode, CCPR1H
is a read-only register.
The general relationship of the outputs in all
configurations is summarized in Figure 18-2.
The CCPR1H register and a 2-bit internal latch are
used to double-buffer the PWM duty cycle. This
double-buffering is essential for glitchless PWM opera-
tion. When the CCPR1H and 2-bit latch match TMR2,
concatenated with an internal 2-bit Q clock or two bits
of the TMR2 prescaler, the ECCP1 pin is cleared. The
maximum PWM resolution (bits) for a given PWM
frequency is given by the equation:
EQUATION 18-3:
FOSC
log
(
)
FPWM
bits
PWM Resolution (max) =
log(2)
TABLE 18-4: EXAMPLE PWM FREQUENCIES AND RESOLUTIONS AT 40 MHz
PWM Frequency
2.44 kHz
9.77 kHz
39.06 kHz 156.25 kHz 312.50 kHz 416.67 kHz
Timer Prescaler (1, 4, 16)
PR2 Value
16
FFh
10
4
1
1
3Fh
8
1
1Fh
7
1
FFh
10
FFh
10
17h
6.58
Maximum Resolution (bits)
© 2009 Microchip Technology Inc.
DS39778D-page 211
PIC18F87J11 FAMILY
FIGURE 18-2:
PWM OUTPUT RELATIONSHIPS (ACTIVE-HIGH STATE)
0
PR2 + 1
Duty
Cycle
SIGNAL
CCP1CON<7:6>
Period
(Single Output)
(Half-Bridge)
P1A Modulated
P1A Modulated
P1B Modulated
P1A Active
00
10
(1)
(1)
Delay
Delay
(Full-Bridge,
Forward)
P1B Inactive
P1C Inactive
P1D Modulated
P1A Inactive
P1B Modulated
P1C Active
01
(Full-Bridge,
Reverse)
11
P1D Inactive
FIGURE 18-3:
PWM OUTPUT RELATIONSHIPS (ACTIVE-LOW STATE)
0
Duty
Cycle
PR2 + 1
SIGNAL
CCP1CON<7:6>
Period
P1A Modulated
P1A Modulated
P1B Modulated
P1A Active
(Single Output)
(Half-Bridge)
00
10
(1)
(1)
Delay
Delay
P1B Inactive
P1C Inactive
P1D Modulated
P1A Inactive
P1B Modulated
P1C Active
(Full-Bridge,
Forward)
01
11
(Full-Bridge,
Reverse)
P1D Inactive
Relationships:
•
•
•
Period = 4 * TOSC * (PR2 + 1) * (TMR2 Prescale Value)
Duty Cycle = TOSC * (CCPR1L<7:0>:CCP1CON<5:4>) * (TMR2 Prescale Value)
Delay = 4 * TOSC * (ECCP1DEL<6:0>)
Note 1: Dead-band delay is programmed using the ECCP1DEL register (Section 18.4.6 “Programmable
Dead-Band Delay”).
DS39778D-page 212
© 2009 Microchip Technology Inc.
PIC18F87J11 FAMILY
18.4.4
HALF-BRIDGE MODE
FIGURE 18-4:
HALF-BRIDGE PWM
OUTPUT
In the Half-Bridge Output mode, two pins are used as
outputs to drive push-pull loads. The PWM output
signal is output on the P1A pin, while the complemen-
tary PWM output signal is output on the P1B pin
(Figure 18-4). This mode can be used for half-bridge
applications, as shown in Figure 18-5, or for full-bridge
applications, where four power switches are being
modulated with two PWM signals.
Period
Period
Duty Cycle
(2)
(2)
P1A
P1B
td
td
In Half-Bridge Output mode, the programmable
dead-band delay can be used to prevent shoot-through
current in half-bridge power devices. The value of bits
P1DC6:P1DC0 sets the number of instruction cycles
before the output is driven active. If the value is greater
than the duty cycle, the corresponding output remains
inactive during the entire cycle. See Section 18.4.6
“Programmable Dead-Band Delay” for more details
on dead-band delay operations.
(1)
(1)
(1)
td = Dead Band Delay
Note 1: At this time, the TMR2 register is equal to the
PR2 register.
2: Output signals are shown as active-high.
Since the P1A and P1B outputs are multiplexed with
the PORTC<2> and PORTE<6> data latches, the
TRISC<2> and TRISE<6> bits must be cleared to
configure P1A and P1B as outputs.
FIGURE 18-5:
EXAMPLES OF HALF-BRIDGE OUTPUT MODE APPLICATIONS
V+
Standard Half-Bridge Circuit (“Push-Pull”)
PIC18F87J11
FET
Driver
+
V
-
P1A
Load
FET
Driver
+
V
-
P1B
V-
Half-Bridge Output Driving a Full-Bridge Circuit
V+
PIC18F87J11
FET
FET
Driver
Driver
P1A
Load
FET
FET
Driver
Driver
P1B
V-
© 2009 Microchip Technology Inc.
DS39778D-page 213
PIC18F87J11 FAMILY
P1A, P1B, P1C and P1D outputs are multiplexed with
the port pins as described in Table 18-1, Table 18-2
and Table 18-3. The corresponding TRIS bits must be
cleared to make the P1A, P1B, P1C and P1D pins
outputs.
18.4.5
FULL-BRIDGE MODE
In Full-Bridge Output mode, four pins are used as
outputs; however, only two outputs are active at a time.
In the Forward mode, pin P1A is continuously active
and pin P1D is modulated. In the Reverse mode, pin
P1C is continuously active and pin P1B is modulated.
These are illustrated in Figure 18-6.
FIGURE 18-6:
FULL-BRIDGE PWM OUTPUT
Forward Mode
Period
(2)
P1A
Duty Cycle
(2)
(2)
P1B
P1C
(2)
P1D
(1)
(1)
Reverse Mode
Period
Duty Cycle
(2)
P1A
(2)
P1B
(2)
P1C
(2)
P1D
(1)
(1)
Note 1: At this time, the TMR2 register is equal to the PR2 register.
Note 2: Output signal is shown as active-high.
DS39778D-page 214
© 2009 Microchip Technology Inc.
PIC18F87J11 FAMILY
FIGURE 18-7:
EXAMPLE OF FULL-BRIDGE OUTPUT APPLICATION
V+
PIC18F87J11
QC
QA
FET
Driver
FET
Driver
P1A
Load
P1B
FET
Driver
FET
Driver
P1C
P1D
QD
QB
V-
Figure 18-9 shows an example where the PWM direc-
tion changes from forward to reverse at a near 100%
duty cycle. At time t1, the outputs, P1A and P1D,
become inactive, while output, P1C, becomes active. In
this example, since the turn-off time of the power
devices is longer than the turn-on time, a shoot-through
current may flow through power devices, QC and QD
(see Figure 18-7), for the duration of ‘t’. The same
phenomenon will occur to power devices, QA and QB,
for PWM direction change from reverse to forward.
18.4.5.1
Direction Change in Full-Bridge
Output Mode
In the Full-Bridge Output mode, the P1M1 bit in the
CCP1CON register allows users to control the forward/
reverse direction. When the application firmware
changes this direction control bit, the module will
assume the new direction on the next PWM cycle.
Just before the end of the current PWM period, the
modulated outputs (P1B and P1D) are placed in their
inactive state, while the unmodulated outputs (P1A and
P1C) are switched to drive in the opposite direction.
This occurs in a time interval of (4 TOSC * (Timer2
Prescale Value) before the next PWM period begins.
The Timer2 prescaler will be either 1, 4 or 16, depend-
ing on the value of the T2CKPS bits (T2CON<1:0>).
During the interval from the switch of the unmodulated
outputs to the beginning of the next period, the
modulated outputs (P1B and P1D) remain inactive.
This relationship is shown in Figure 18-8.
If changing PWM direction at high duty cycle is required
for an application, one of the following requirements
must be met:
1. Reduce PWM for
changing directions.
a PWM period before
2. Use switch drivers that can drive the switches off
faster than they can drive them on.
Other options to prevent shoot-through current may
exist.
Note that in the Full-Bridge Output mode, the ECCP1
module does not provide any dead-band delay. In gen-
eral, since only one output is modulated at all times,
dead-band delay is not required. However, there is a
situation where a dead-band delay might be required.
This situation occurs when both of the following
conditions are true:
1. The direction of the PWM output changes when
the duty cycle of the output is at or near 100%.
2. The turn-off time of the power switch, including
the power device and driver circuit, is greater
than the turn-on time.
© 2009 Microchip Technology Inc.
DS39778D-page 215
PIC18F87J11 FAMILY
FIGURE 18-8:
PWM DIRECTION CHANGE
(1)
Period
Period
SIGNAL
P1A (Active-High)
P1B (Active-High)
DC
P1C (Active-High)
P1D (Active-High)
(Note 2)
DC
Note 1: The direction bit in the ECCP1 Control register (CCP1CON<7>) is written at any time during the PWM cycle.
2: When changing directions, the P1A and P1C signals switch before the end of the current PWM cycle at intervals
of 4 TOSC, 16 TOSC or 64 TOSC, depending on the Timer2 prescaler value. The modulated P1B and P1D signals
are inactive at this time.
FIGURE 18-9:
PWM DIRECTION CHANGE AT NEAR 100% DUTY CYCLE
Forward Period
Reverse Period
t1
(1)
(1)
P1A
P1B
DC
(1)
P1C
P1D
(1)
DC
(2)
t
ON
(1)
(1)
External Switch C
External Switch D
(3)
t
OFF
(2,3)
Potential
t = t
– t
ON
OFF
Shoot-Through
(1)
Current
Note 1: All signals are shown as active-high.
2:
3:
t
t
is the turn-on delay of power switch QC and its driver.
ON
is the turn-off delay of power switch QD and its driver.
OFF
DS39778D-page 216
© 2009 Microchip Technology Inc.
PIC18F87J11 FAMILY
18.4.6
PROGRAMMABLE DEAD-BAND
DELAY
18.4.7
ENHANCED PWM
AUTO-SHUTDOWN
In half-bridge applications, where all power switches
are modulated at the PWM frequency at all times, the
power switches normally require more time to turn off
than to turn on. If both the upper and lower power
switches are switched at the same time (one turned on
and the other turned off), both switches may be on for
a short period of time until one switch completely turns
off. During this brief interval, a very high current
(shoot-through current) may flow through both power
switches, shorting the bridge supply. To avoid this
potentially destructive shoot-through current from flow-
ing during switching, turning on either of the power
switches is normally delayed to allow the other switch
to completely turn off.
When the ECCP1 is programmed for any of the
Enhanced PWM modes, the active output pins may be
configured for auto-shutdown. Auto-shutdown immedi-
ately places the Enhanced PWM output pins into a
defined shutdown state when a shutdown event
occurs.
A shutdown event can be caused by either of the two
comparator modules or the FLT0 pin (or any combina-
tion of these three sources). The comparators may be
used to monitor a voltage input proportional to a current
being monitored in the bridge circuit. If the voltage
exceeds a threshold, the comparator switches state and
triggers a shutdown. Alternatively, a low-level digital sig-
nal on the FLT0 pin can also trigger a shutdown. The
auto-shutdown feature can be disabled by not selecting
any auto-shutdown sources. The auto-shutdown
sources to be used are selected using the
ECCP1AS2:ECCP1AS0 bits (ECCP1AS<6:4>).
In the Half-Bridge Output mode, a digitally program-
mable, dead-band delay is available to avoid
shoot-through current from destroying the bridge
power switches. The delay occurs at the signal
transition from the non-active state to the active state
(see Figure 18-4 for illustration). The lower seven bits of
the ECCPxDEL register (Register 18-2) set the delay
period in terms of microcontroller instruction cycles
(TCY or 4 TOSC).
When a shutdown occurs, the output pins are
asynchronously placed in their shutdown states,
specified
by
the
PSS1AC1:PSS1AC0
and
PSS1BD1:PSS1BD0 bits (ECCP1AS3:ECCP1AS0).
Each pin pair (P1A/P1C and P1B/P1D) may be set to
drive high, drive low or be tri-stated (not driving). The
ECCP1ASE bit (ECCP1AS<7>) is also set to hold the
Enhanced PWM outputs in their shutdown states.
The ECCP1ASE bit is set by hardware when a
shutdown event occurs. If automatic restarts are not
enabled, the ECCP1ASE bit is cleared by firmware
when the cause of the shutdown clears. If automatic
restarts are enabled, the ECCP1ASE bit is automati-
cally cleared when the cause of the auto-shutdown has
cleared.
If the ECCP1ASE bit is set when a PWM period begins,
the PWM outputs remain in their shutdown state for that
entire PWM period. When the ECCP1ASE bit is
cleared, the PWM outputs will return to normal
operation at the beginning of the next PWM period.
Note:
Writing to the ECCP1ASE bit is disabled
while a shutdown condition is active.
© 2009 Microchip Technology Inc.
DS39778D-page 217
PIC18F87J11 FAMILY
REGISTER 18-2: ECCPxDEL: ECCPx PWM DELAY REGISTER
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
PxRSEN
PxDC6
PxDC5
PxDC4
PxDC3
PxDC2
PxDC1
PxDC0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
-n = Value at POR
bit 7
PxRSEN: PWM Restart Enable bit
1= Upon auto-shutdown, the ECCPxASE bit clears automatically once the shutdown event goes
away; the PWM restarts automatically
0= Upon auto-shutdown, ECCPxASE must be cleared in software to restart the PWM
bit 6-0
PxDC6:PxDC0: PWM Delay Count bits
Delay time, in number of FOSC/4 (4 * TOSC) cycles, between the scheduled and actual time for a PWM
signal to transition to active.
REGISTER 18-3: ECCPxAS: ECCPx AUTO-SHUTDOWN CONTROL REGISTER
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
ECCPxASE ECCPxAS2
bit 7
ECCPxAS1
ECCPxAS0
PSSxAC1
PSSxAC0
PSSxBD1
PSSxBD0
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7
ECCPxASE: ECCPx Auto-Shutdown Event Status bit
0= ECCPx outputs are operating
1= A shutdown event has occurred; ECCPx outputs are in shutdown state
bit 6-4
ECCPxAS2:ECCPxAS0: ECCPx Auto-Shutdown Source Select bits
000= Auto-shutdown is disabled
001= Comparator 1 output
010= Comparator 2 output
011= Either Comparator 1 or 2
100= FLT0
101= FLT0 or Comparator 1
110= FLT0 or Comparator 2
111= FLT0 or Comparator 1 or Comparator 2
bit 3-2
bit 1-0
PSSxAC1:PSSxAC0: Pins A and C Shutdown State Control bits
00= Drive Pins A and C to ‘0’
01= Drive Pins A and C to ‘1’
1x= Pins A and C tri-state
PSSxBD1:PSSxBD0: Pins B and D Shutdown State Control bits
00= Drive Pins B and D to ‘0’
01= Drive Pins B and D to ‘1’
1x= Pins B and D tri-state
DS39778D-page 218
© 2009 Microchip Technology Inc.
PIC18F87J11 FAMILY
18.4.7.1
Auto-Shutdown and Automatic
Restart
18.4.8
START-UP CONSIDERATIONS
When the ECCP1 module is used in the PWM mode,
the application hardware must use the proper external
pull-up and/or pull-down resistors on the PWM output
pins. When the microcontroller is released from Reset,
all of the I/O pins are in the high-impedance state. The
external circuits must keep the power switch devices in
the OFF state until the microcontroller drives the I/O
pins with the proper signal levels, or activates the PWM
output(s).
The auto-shutdown feature can be configured to allow
automatic restarts of the module following a shutdown
event. This is enabled by setting the P1RSEN bit of the
ECCP1DEL register (ECCP1DEL<7>).
In Shutdown mode with P1RSEN = 1 (Figure 18-10),
the ECCP1ASE bit will remain set for as long as the
cause of the shutdown continues. When the shutdown
condition clears, the ECCP1ASE bit is cleared. If
P1RSEN = 0 (Figure 18-11), once a shutdown condi-
tion occurs, the ECCP1ASE bit will remain set until it is
cleared by firmware. Once ECCP1ASE is cleared, the
Enhanced PWM will resume at the beginning of the
next PWM period.
The CCP1M1:CCP1M0 bits (CCP1CON<1:0>) allow
the user to choose whether the PWM output signals are
active-high or active-low for each pair of PWM output
pins (P1A/P1C and P1B/P1D). The PWM output
polarities must be selected before the PWM pins are
configured as outputs. Changing the polarity configura-
tion while the PWM pins are configured as outputs is
not recommended since it may result in damage to the
application circuits.
Note:
Writing to the ECCP1ASE bit is disabled
while a shutdown condition is active.
Independent of the P1RSEN bit setting, if the
auto-shutdown source is one of the comparators, the
shutdown condition is a level. The ECCP1ASE bit
cannot be cleared as long as the cause of the shutdown
persists.
The P1A, P1B, P1C and P1D output latches may not be
in the proper states when the PWM module is initialized.
Enabling the PWM pins for output at the same time as
the ECCP1 module may cause damage to the applica-
tion circuit. The ECCP1 module must be enabled in the
proper output mode and complete a full PWM cycle
before configuring the PWM pins as outputs. The
completion of a full PWM cycle is indicated by the
TMR2IF bit being set as the second PWM period
begins.
The Auto-Shutdown mode can be forced by writing a ‘1’
to the ECCP1ASE bit.
FIGURE 18-10:
PWM AUTO-SHUTDOWN (P1RSEN = 1, AUTO-RESTART ENABLED)
PWM Period
Shutdown Event
ECCP1ASE bit
PWM Activity
Normal PWM
Start of
PWM Period
Shutdown
Event Occurs Event Clears
Shutdown
PWM
Resumes
FIGURE 18-11:
PWM AUTO-SHUTDOWN (P1RSEN = 0, AUTO-RESTART DISABLED)
PWM Period
Shutdown Event
ECCP1ASE bit
PWM Activity
Normal PWM
ECCP1ASE
Cleared by
Start of
PWM Period
Shutdown
Event Occurs Event Clears
Shutdown Firmware PWM
Resumes
© 2009 Microchip Technology Inc.
DS39778D-page 219
PIC18F87J11 FAMILY
8. If auto-restart operation is required, set the
PxRSEN bit (ECCPxDEL<7>).
18.4.9
SETUP FOR PWM OPERATION
The following steps should be taken when configuring
the ECCP module for PWM operation:
9. Configure and start TMRn (TMR2 or TMR4):
• Clear the TMRn interrupt flag bit by clearing
the TMRnIF bit (PIR1<1> for Timer2 or
PIR3<3> for Timer4).
1. Configure the PWM pins PxA and PxB (and PxC
and PxD, if used) as inputs by setting the
corresponding TRIS bits.
• Set the TMRn prescale value by loading the
TnCKPS bits (TnCON<1:0>).
2. Set the PWM period by loading the PR2 (PR4)
register.
• Enable Timer2 (or Timer4) by setting the
TMRnON bit (TnCON<2>).
3. Configure the ECCP module for the desired
PWM mode and configuration by loading the
CCPxCON register with the appropriate values:
10. Enable PWM outputs after a new PWM cycle
has started:
• Select one of the available output
configurations and direction with the
PxM1:PxM0 bits.
• Wait until TMRn overflows (TMRnIF bit is set).
• Enable the ECCPx/PxA, PxB, PxC and/or
PxD pin outputs by clearing the respective
TRIS bits.
• Select the polarities of the PWM output
signals with the CCPxM3:CCPxM0 bits.
• Clear the ECCPxASE bit (ECCPxAS<7>).
4. Set the PWM duty cycle by loading the CCPRxL
register and the CCPxCON<5:4> bits.
18.4.10 EFFECTS OF A RESET
5. For auto-shutdown:
Both Power-on Reset and subsequent Resets will force
all ports to Input mode and the ECCP registers to their
Reset states.
• Disable auto-shutdown; ECCPxASE = 0
• Configure auto-shutdown source
• Wait for Run condition
This forces the Enhanced CCP module to reset to a
state compatible with the standard CCP module.
6. For Half-Bridge Output mode, set the
dead-band delay by loading ECCPxDEL<6:0>
with the appropriate value.
7. If auto-shutdown operation is required, load the
ECCPxAS register:
• Select the auto-shutdown sources using the
ECCPxAS2:ECCPxAS0 bits.
• Select the shutdown states of the PWM
output pins using the PSSxAC1:PSSxAC0
and PSSxBD1:PSSxBD0 bits.
• Set the ECCPxASE bit (ECCPxAS<7>).
DS39778D-page 220
© 2009 Microchip Technology Inc.
PIC18F87J11 FAMILY
TABLE 18-5: REGISTERS ASSOCIATED WITH ECCP MODULES AND TIMER1 TO TIMER4
Reset
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Values
on Page:
INTCON
RCON
PIR1
GIE/GIEH PEIE/GIEL TMR0IE
INT0IE
RI
RBIE
TMR0IF
PD
INT0IF
POR
RBIF
57
58
60
60
60
60
60
60
60
60
60
60
60
60
60
60
58
58
58
58
58
58
58
61
61
61
61
61
61
59
59,
59
59
59
IPEN
PMPIF
PMPIE
PMPIP
OSCFIF
OSCFIE
OSCFIP
SSP2IF
SSP2IE
SSP2IP
TRISB7
TRISC7
TRISE7
—
—
CM
TO
BOR
ADIF
RC1IF
RC1IE
RC1IP
CM1IF
CM1IE
CM1IP
RC2IF
RC2IE
RC2IP
TRISB5
TRISC5
TRISE5
—
TX1IF
TX1IE
TX1IP
—
SSP1IF
SSP1IE
SSP1IP
BCL1IF
BCL1IE
BCL1IP
TMR4IF
TMR4IE
TMR4IP
TRISB3
TRISC3
TRISE3
TRISG3
TRISH3
CCP1IF
CCP1IE
CCP1IP
LVDIF
TMR2IF
TMR2IE
TMR2IP
TMR3IF
TMR3IE
TMR3IP
CCP4IF
CCP4IE
CCP4IP
TRISB1
TRISC1
TRISE1
TRISG1
TRISH1
TMR1IF
TMR1IE
TMR1IP
CCP2IF
CCP2IE
CCP2IP
CCP3IF
CCP3IE
CCP3IP
TRISB0
TRISC0
TRISE0
TRISG0
TRISH0
PIE1
ADIE
IPR1
ADIP
PIR2
CM2IF
CM2IE
CM2IP
BCL2IF
BCL2IE
BCL2IP
TRISB6
TRISC6
TRISE6
—
PIE2
—
LVDIE
IPR2
—
LVDIP
PIR3
TX2IF
TX2IE
TX2IP
TRISB4
TRISC4
TRISE4
TRISG4
TRISH4
CCP5IF
CCP5IE
CCP5IP
TRISB2
TRISC2
TRISE2
TRISG2
TRISH2
PIE3
IPR3
TRISB
TRISC
TRISE
TRISG
(1)
TRISH
TRISH7
TRISH6
TRISH5
(3)
TMR1L
Timer1 Register Low Byte
Timer1 Register High Byte
(3)
TMR1H
(4)
ODCON1
—
—
—
CCP5OD CCP4OD ECCP3OD ECCP2OD ECCP1OD
(3)
T1CON
RD16
T1RUN
T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON
(3)
TMR2
Timer2 Register
T2OUTPS3 T2OUTPS2 T2OUTPS1 T2OUTPS0 TMR2ON T2CKPS1 T2CKPS0
T2CON
—
(3)
PR2
Timer2 Period Register
Timer3 Register Low Byte
Timer3 Register High Byte
TMR3L
TMR3H
T3CON
TMR4
RD16
T3CCP2 T3CKPS1 T3CKPS0 T3CCP1
T3SYNC TMR3CS TMR3ON
Timer4 Register
T4CON
—
T4OUTPS3 T4OUTPS2 T4OUTPS1 T4OUTPS0 TMR4ON T4CKPS1 T4CKPS0
(3)
PR4
Timer4 Period Register
(2)
CCPRxL
CCPRxH
Capture/Compare/PWM Register x Low Byte
Capture/Compare/PWM Register x High Byte
(2)
(2)
CCPxCON
PxM1
PxM0
DCxB1
DCxB0
CCPxM3
CCPxM2
CCPxM1
CCPxM0
(2)
ECCPxAS
ECCPxASE ECCPxAS2 ECCPxAS1 ECCPxAS0 PSSxAC1 PSSxAC0 PSSxBD1 PSSxBD0
(2)
ECCPxDEL
PxRSEN
PxDC6
PxDC5
PxDC4
PxDC3
PxDC2
PxDC1
PxDC0
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used during ECCP operation.
Note 1: Available on 80-pin devices only.
2: Generic term for all of the identical registers of this name for all Enhanced CCP modules, where ‘x’ identifies the
individual module (ECCP1, ECCP2 or ECCP3). Bit assignments and Reset values for all registers of the same
generic name are identical.
3: Default (legacy) SFR at this address, available when WDTCON<4> = 0.
4: Configuration SFR, overlaps with default SFR at this address; available only when WDTCON<4> = 1.
© 2009 Microchip Technology Inc.
DS39778D-page 221
PIC18F87J11 FAMILY
NOTES:
DS39778D-page 222
© 2009 Microchip Technology Inc.
PIC18F87J11 FAMILY
19.3 SPI Mode
19.0 MASTER SYNCHRONOUS
SERIAL PORT (MSSP)
MODULE
The SPI mode allows 8 bits of data to be synchronously
transmitted and received simultaneously. All four
modes of SPI are supported. To accomplish
communication, typically three pins are used:
19.1 Master SSP (MSSP) Module
Overview
• Serial Data Out (SDOx) – RC5/SDO1 or
RD4/SDO2
The Master Synchronous Serial Port (MSSP) module is
a serial interface, useful for communicating with other
peripheral or microcontroller devices. These peripheral
devices may be serial EEPROMs, shift registers,
display drivers, A/D converters, etc. The MSSP module
can operate in one of two modes:
• Serial Data In (SDIx) – RC4/SDI1/SDA1 or
RD5/SDI2/SDA2
• Serial Clock (SCKx) – RC3/SCK1/SCL1 or
RD6/SCK2/SCL2
Additionally, a fourth pin may be used when in a Slave
mode of operation:
• Serial Peripheral Interface (SPI)
• Inter-Integrated Circuit (I2C™)
- Full Master mode
• Slave Select (SSx) – RF7/SS1 or RD7/SS2
Figure 19-1 shows the block diagram of the MSSP
module when operating in SPI mode.
- Slave mode (with general address call)
The I2C interface supports the following modes in
hardware:
FIGURE 19-1:
MSSP BLOCK DIAGRAM
(SPI MODE)
• Master mode
Internal
Data Bus
• Multi-Master mode
• Slave mode with 5-bit and 7-bit address masking
(with address masking for both 10-bit and 7-bit
addressing)
Read
Write
SSPxBUF reg
All members of the PIC18F87J11 Family have two
MSSP modules, designated as MSSP1 and MSSP2.
Each module operates independently of the other.
SDIx
SSPxSR reg
Note:
Throughout this section, generic refer-
ences to an MSSP module in any of its
operating modes may be interpreted as
being equally applicable to MSSP1 or
MSSP2. Register names and module I/O
signals use the generic designator ‘x’ to
indicate the use of a numeral to distinguish
a particular module when required. Control
bit names are not individuated.
Shift
Clock
bit 0
SDOx
SSx
Control
Enable
SSx
Edge
Select
19.2 Control Registers
2
Each MSSP module has three associated control regis-
ters. These include a status register (SSPxSTAT) and
two control registers (SSPxCON1 and SSPxCON2). The
use of these registers and their individual configuration
bits differ significantly depending on whether the MSSP
module is operated in SPI or I2C mode.
Clock Select
SSPM3:SSPM0
SMP:CKE
2
4
TMR2 Output
(
)
2
SCKx
Edge
Select
TOSC
Additional details are provided under the individual
sections.
Prescaler
4, 16, 64
Note:
In devices with more than one MSSP
module, it is very important to pay close
attention to SSPxCON register names.
SSP1CON1 and SSP1CON2 control
different operational aspects of the same
Data to TXx/RXx in SSPxSR
TRIS bit
Note: Only port I/O names are used in this diagram for
the sake of brevity. Refer to the text for a full list of
multiplexed functions.
module,
while
SSP1CON1
and
SSP2CON1 control the same features for
two different modules.
© 2009 Microchip Technology Inc.
DS39778D-page 223
PIC18F87J11 FAMILY
SSPxSR is the shift register used for shifting data in or
out. SSPxBUF is the buffer register to which data
bytes are written to or read from.
19.3.1
REGISTERS
Each MSSP module has four registers for SPI mode
operation. These are:
In receive operations, SSPxSR and SSPxBUF
together create a double-buffered receiver. When
SSPxSR receives a complete byte, it is transferred to
SSPxBUF and the SSPxIF interrupt is set.
• MSSPx Control Register 1 (SSPxCON1)
• MSSPx Status Register (SSPxSTAT)
• Serial Receive/Transmit Buffer Register
(SSPxBUF)
During transmission, the SSPxBUF is not
double-buffered. A write to SSPxBUF will write to both
SSPxBUF and SSPxSR.
• MSSPx Shift Register (SSPxSR) – Not directly
accessible
SSPxCON1 and SSPxSTAT are the control and status
registers in SPI mode operation. The SSPxCON1
register is readable and writable. The lower 6 bits of
the SSPxSTAT are read-only. The upper two bits of the
SSPxSTAT are read/write.
REGISTER 19-1: SSPxSTAT: MSSPx STATUS REGISTER (SPI MODE)
R/W-0
SMP
R/W-0
CKE(1)
R-0
D/A
R-0
P
R-0
S
R-0
R-0
UA
R-0
BF
R/W
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
-n = Value at POR
bit 7
SMP: Sample bit
SPI Master mode:
1= Input data sampled at end of data output time
0= Input data sampled at middle of data output time
SPI Slave mode:
SMP must be cleared when SPI is used in Slave mode.
bit 6
CKE: SPI Clock Select bit(1)
1= Transmit occurs on transition from active to Idle clock state
0= Transmit occurs on transition from Idle to active clock state
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
D/A: Data/Address bit
Used in I2C mode only.
P: Stop bit
Used in I2C mode only. This bit is cleared when the MSSPx module is disabled, SSPEN is cleared.
S: Start bit
Used in I2C mode only.
R/W: Read/Write Information bit
Used in I2C mode only.
UA: Update Address bit
Used in I2C mode only.
BF: Buffer Full Status bit (Receive mode only)
1= Receive complete, SSPxBUF is full
0= Receive not complete, SSPxBUF is empty
Note 1: Polarity of clock state is set by the CKP bit (SSPxCON1<4>).
DS39778D-page 224
© 2009 Microchip Technology Inc.
PIC18F87J11 FAMILY
REGISTER 19-2: SSPxCON1: MSSPx CONTROL REGISTER 1 (SPI MODE)
R/W-0
WCOL
R/W-0
SSPOV(1)
R/W-0
SSPEN(2)
R/W-0
CKP
R/W-0
SSPM3(3)
R/W-0
SSPM2(3)
R/W-0
SSPM1(3)
R/W-0
SSPM0(3)
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7
WCOL: Write Collision Detect bit
1= The SSPxBUF register is written while it is still transmitting the previous word (must be cleared in
software)
0= No collision
bit 6
SSPOV: Receive Overflow Indicator bit(1)
SPI Slave mode:
1= A new byte is received while the SSPxBUF register is still holding the previous data. In case of
overflow, the data in SSPxSR is lost. Overflow can only occur in Slave mode. The user must read
the SSPxBUF, even if only transmitting data, to avoid setting overflow (must be cleared in
software).
0= No overflow
bit 5
SSPEN: Master Synchronous Serial Port Enable bit(2)
1= Enables serial port and configures SCKx, SDOx, SDIx and SSx as serial port pins
0= Disables serial port and configures these pins as I/O port pins
bit 4
CKP: Clock Polarity Select bit
1= Idle state for clock is a high level
0= Idle state for clock is a low level
bit 3-0
SSPM3:SSPM0: Master Synchronous Serial Port Mode Select bits(3)
0101= SPI Slave mode, clock = SCKx pin, SSx pin control disabled, SSx can be used as I/O pin
0100= SPI Slave mode, clock = SCKx pin, SSx pin control enabled
0011= SPI Master mode, clock = TMR2 output/2
0010= SPI Master mode, clock = FOSC/64
0001= SPI Master mode, clock = FOSC/16
0000= SPI Master mode, clock = FOSC/4
Note 1: In Master mode, the overflow bit is not set since each new reception (and transmission) is initiated by
writing to the SSPxBUF register.
2: When enabled, these pins must be properly configured as input or output.
3: Bit combinations not specifically listed here are either reserved or implemented in I2C mode only.
© 2009 Microchip Technology Inc.
DS39778D-page 225
PIC18F87J11 FAMILY
When the application software is expecting to receive
valid data, the SSPxBUF should be read before the next
byte of data to transfer is written to the SSPxBUF. The
Buffer Full bit, BF (SSPxSTAT<0>), indicates when
SSPxBUF has been loaded with the received data
(transmission is complete). When the SSPxBUF is read,
the BF bit is cleared. This data may be irrelevant if the
SPI is only a transmitter. Generally, the MSSP interrupt
is used to determine when the transmission/reception
has completed. If the interrupt method is not going to be
used, then software polling can be done to ensure that a
write collision does not occur. Example 19-1 shows the
loading of the SSPxBUF (SSPxSR) for data
transmission.
19.3.2
OPERATION
When initializing the SPI, several options need to be
specified. This is done by programming the appropriate
control bits (SSPxCON1<5:0> and SSPxSTAT<7:6>).
These control bits allow the following to be specified:
• Master mode (SCKx is the clock output)
• Slave mode (SCKx is the clock input)
• Clock Polarity (Idle state of SCKx)
• Data Input Sample Phase (middle or end of data
output time)
• Clock Edge (output data on rising/falling edge of
SCKx)
• Clock Rate (Master mode only)
The SSPxSR is not directly readable or writable and
can only be accessed by addressing the SSPxBUF
register. Additionally, the SSPxSTAT register indicates
the various status conditions.
• Slave Select mode (Slave mode only)
Each MSSP module consists of a transmit/receive shift
register (SSPxSR) and a buffer register (SSPxBUF).
The SSPxSR shifts the data in and out of the device,
MSb first. The SSPxBUF holds the data that was
written to the SSPxSR until the received data is ready.
Once the 8 bits of data have been received, that byte is
moved to the SSPxBUF register. Then, the Buffer Full
detect bit, BF (SSPxSTAT<0>) and the interrupt flag bit,
SSPxIF, are set. This double-buffering of the received
data (SSPxBUF) allows the next byte to start reception
before reading the data that was just received. Any
write to the SSPxBUF register during transmis-
sion/reception of data will be ignored and the Write
Collision Detect bit, WCOL (SSPxCON1<7>), will be
set. User software must clear the WCOL bit so that it
can be determined if the following write(s) to the
SSPxBUF register completed successfully.
19.3.3
OPEN-DRAIN OUTPUT OPTION
The drivers for the SDOx output and SCKx clock pins
can be optionally configured as open-drain outputs.
This feature allows the voltage level on the pin to be
pulled to a higher level through an external pull-up
resistor, and allows the output to communicate with
external circuits without the need for additional level
shifters. For more information, see Section 10.1.4
“Open-Drain Outputs”.
The open-drain output option is controlled by the
SPI2OD and SPI1OD bits (ODCON3<1:0>). Setting an
SPIxOD bit configures the SDOx and SCKx pins for the
corresponding module for open-drain operation.
The ODCON3 register shares the same address as the
T1CON register. The ODCON3 register is accessed by
setting the ADSHR bit in the WDTCON register
(WDTCON<4>).
EXAMPLE 19-1:
LOADING THE SSP1BUF (SSP1SR) REGISTER
LOOP
BTFSS
BRA
SSP1STAT, BF
LOOP
;Has data been received (transmit complete)?
;No
MOVF
SSP1BUF, W
;WREG reg = contents of SSP1BUF
MOVWF
RXDATA
;Save in user RAM, if data is meaningful
MOVF
MOVWF
TXDATA, W
SSP1BUF
;W reg = contents of TXDATA
;New data to xmit
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Any serial port function that is not desired may be
overridden by programming the corresponding Data
Direction (TRIS) register to the opposite value.
19.3.4
ENABLING SPI I/O
To enable the serial port, MSSP Enable bit, SSPEN
(SSPxCON1<5>), must be set. To reset or reconfigure
SPI mode, clear the SSPEN bit, reinitialize the
SSPxCON registers and then set the SSPEN bit. This
configures the SDIx, SDOx, SCKx and SSx pins as
serial port pins. For the pins to behave as the serial port
function, some must have their data direction bits (in
the TRIS register) appropriately programmed as
follows:
19.3.5
TYPICAL CONNECTION
Figure 19-2 shows a typical connection between two
microcontrollers. The master controller (Processor 1)
initiates the data transfer by sending the SCKx signal.
Data is shifted out of both shift registers on their pro-
grammed clock edge and latched on the opposite edge
of the clock. Both processors should be programmed to
the same Clock Polarity (CKP), then both controllers
would send and receive data at the same time.
Whether the data is meaningful (or dummy data)
depends on the application software. This leads to
three scenarios for data transmission:
• SDIx is automatically controlled by the
SPI module
• SDOx must have the TRISC<5> or TRISD<4> bit
cleared
• SCKx (Master mode) must have the TRISC<3> or
TRISD<6>bit cleared
• Master sends data – Slave sends dummy data
• Master sends data – Slave sends data
• SCKx (Slave mode) must have the TRISC<3> or
TRISD<6> bit set
• Master sends dummy data – Slave sends data
• SSx must have the TRISF<7> or TRISD<7> bit
set
FIGURE 19-2:
SPI MASTER/SLAVE CONNECTION
SPI Master SSPM3:SSPM0 = 00xxb
SPI Slave SSPM3:SSPM0 = 010xb
SDIx
SDOx
Serial Input Buffer
(SSPxBUF)
Serial Input Buffer
(SSPxBUF)
SDIx
SDOx
Shift Register
(SSPxSR)
Shift Register
(SSPxSR)
LSb
MSb
MSb
LSb
Serial Clock
SCKx
SCKx
PROCESSOR 1
PROCESSOR 2
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shown in Figure 19-3, Figure 19-5 and Figure 19-6,
where the MSB is transmitted first. In Master mode, the
SPI clock rate (bit rate) is user programmable to be one
of the following:
19.3.6
MASTER MODE
The master can initiate the data transfer at any time
because it controls the SCKx. The master determines
when the slave (Processor 1, Figure 19-2) is to
broadcast data by the software protocol.
• FOSC/4 (or TCY)
• FOSC/16 (or 4 • TCY)
• FOSC/64 (or 16 • TCY)
• Timer2 output/2
In Master mode, the data is transmitted/received as
soon as the SSPxBUF register is written to. If the SPI
is only going to receive, the SDOx output could be dis-
abled (programmed as an input). The SSPxSR register
will continue to shift in the signal present on the SDIx
pin at the programmed clock rate. As each byte is
received, it will be loaded into the SSPxBUF register as
if a normal received byte (interrupts and status bits
appropriately set). This could be useful in receiver
applications as a “Line Activity Monitor” mode.
This allows a maximum data rate (at 40 MHz) of
10.00 Mbps.
Figure 19-3 shows the waveforms for Master mode.
When the CKE bit is set, the SDOx data is valid before
there is a clock edge on SCKx. The change of the input
sample is shown based on the state of the SMP bit. The
time when the SSPxBUF is loaded with the received
data is shown.
The clock polarity is selected by appropriately
programming the CKP bit (SSPxCON1<4>). This then,
would give waveforms for SPI communication as
FIGURE 19-3:
SPI MODE WAVEFORM (MASTER MODE)
Write to
SSPxBUF
SCKx
(CKP = 0
CKE = 0)
SCKx
(CKP = 1
CKE = 0)
4 Clock
Modes
SCKx
(CKP = 0
CKE = 1)
SCKx
(CKP = 1
CKE = 1)
bit 6
bit 6
bit 2
bit 2
bit 5
bit 5
bit 4
bit 4
bit 1
bit 1
bit 0
bit 0
SDOx
(CKE = 0)
bit 7
bit 7
bit 3
bit 3
SDOx
(CKE = 1)
SDIx
(SMP = 0)
bit 0
bit 7
Input
Sample
(SMP = 0)
SDIx
(SMP = 1)
bit 0
bit 7
Input
Sample
(SMP = 1)
SSPxIF
Next Q4 Cycle
after Q2↓
SSPxSR to
SSPxBUF
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transmitted byte and becomes a floating output. Exter-
nal pull-up/pull-down resistors may be desirable
depending on the application.
19.3.7
SLAVE MODE
In Slave mode, the data is transmitted and received as
the external clock pulses appear on SCKx. When the
last bit is latched, the SSPxIF interrupt flag bit is set.
Note 1: When the SPI is in Slave mode
with
SSx pin
control
enabled
While in Slave mode, the external clock is supplied by
the external clock source on the SCKx pin. This exter-
nal clock must meet the minimum high and low times
as specified in the electrical specifications.
(SSPxCON1<3:0> = 0100), the SPI
module will reset if the SSx pin is set to VDD.
2: If the SPI is used in Slave mode with CKE
set, then the SSx pin control must be
enabled.
While in Sleep mode, the slave can transmit/receive
data. When a byte is received, the device can be
configured to wake-up from Sleep.
When the SPI module resets, the bit counter is forced
to ‘0’. This can be done by either forcing the SSx pin to
a high level or clearing the SSPEN bit.
19.3.8
SLAVE SELECT
SYNCHRONIZATION
To emulate two-wire communication, the SDOx pin can
be connected to the SDIx pin. When the SPI needs to
operate as a receiver, the SDOx pin can be configured
as an input. This disables transmissions from the
SDOx. The SDIx can always be left as an input (SDI
function) since it cannot create a bus conflict.
The SSx pin allows a Synchronous Slave mode. The
SPI must be in Slave mode with the SSx pin control
enabled (SSPxCON1<3:0> = 04h). When the SSx pin
is low, transmission and reception are enabled and the
SDOx pin is driven. When the SSx pin goes high, the
SDOx pin is no longer driven, even if in the middle of a
FIGURE 19-4:
SLAVE SYNCHRONIZATION WAVEFORM
SSx
SCKx
(CKP = 0
CKE = 0)
SCKx
(CKP = 1
CKE = 0)
Write to
SSPxBUF
bit 6
bit 7
bit 7
bit 0
SDOx
bit 7
SDIx
(SMP = 0)
bit 0
bit 7
Input
Sample
(SMP = 0)
SSPxIF
Interrupt
Flag
Next Q4 Cycle
after Q2
↓
SSPxSR to
SSPxBUF
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DS39778D-page 229
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FIGURE 19-5:
SPI MODE WAVEFORM (SLAVE MODE WITH CKE = 0)
SSx
Optional
SCKx
(CKP = 0
CKE = 0)
SCKx
(CKP = 1
CKE = 0)
Write to
SSPxBUF
bit 6
bit 2
bit 5
bit 4
bit 3
bit 1
bit 0
SDOx
bit 7
SDIx
(SMP = 0)
bit 0
bit 7
Input
Sample
(SMP = 0)
SSPxIF
Interrupt
Flag
Next Q4 Cycle
after Q2↓
SSPxSR to
SSPxBUF
FIGURE 19-6:
SPI MODE WAVEFORM (SLAVE MODE WITH CKE = 1)
SSx
Not Optional
SCKx
(CKP = 0
CKE = 1)
SCKx
(CKP = 1
CKE = 1)
Write to
SSPxBUF
bit 6
bit 3
bit 2
bit 5
bit 4
bit 1
bit 0
SDOx
bit 7
bit 7
SDIx
(SMP = 0)
bit 0
Input
Sample
(SMP = 0)
SSPxIF
Interrupt
Flag
Next Q4 Cycle
after Q2↓
SSPxSR to
SSPxBUF
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19.3.9
OPERATION IN POWER-MANAGED
MODES
19.3.11 BUS MODE COMPATIBILITY
Table 19-1 shows the compatibility between the
standard SPI modes and the states of the CKP and
CKE control bits.
In SPI Master mode, module clocks may be operating
at a different speed than when in full-power mode; in
the case of the Sleep mode, all clocks are halted.
TABLE 19-1: SPI BUS MODES
In Idle modes, a clock is provided to the peripherals.
That clock can be from the primary clock source, the
secondary clock (Timer1 oscillator) or the INTOSC
source. See Section 2.3 “Clock Sources and
Oscillator Switching” for additional information.
Control Bits State
Standard SPI Mode
Terminology
CKP
CKE
0, 0
0, 1
1, 0
1, 1
0
0
1
1
1
0
1
0
In most cases, the speed that the master clocks SPI
data is not important; however, this should be
evaluated for each system.
If MSSP interrupts are enabled, they can wake the con-
troller from Sleep mode, or one of the Idle modes, when
the master completes sending data. If an exit from
Sleep or Idle mode is not desired, MSSP interrupts
should be disabled.
There is also an SMP bit which controls when the data
is sampled.
19.3.12 SPI CLOCK SPEED AND MODULE
INTERACTIONS
If the Sleep mode is selected, all module clocks are
halted and the transmission/reception will remain in
that state until the device wakes. After the device
returns to Run mode, the module will resume
transmitting and receiving data.
Because MSSP1 and MSSP2 are independent
modules, they can operate simultaneously at different
data rates. Setting the SSPM3:SSPM0 bits of the
SSPxCON1 register determines the rate for the
corresponding module.
In SPI Slave mode, the SPI Transmit/Receive Shift
register operates asynchronously to the device. This
allows the device to be placed in any power-managed
mode and data to be shifted into the SPI Trans-
mit/Receive Shift register. When all 8 bits have been
received, the MSSP interrupt flag bit will be set and if
enabled, will wake the device.
An exception is when both modules use Timer2 as a
time base in Master mode. In this instance, any
changes to the Timer2 module’s operation will affect
both MSSP modules equally. If different bit rates are
required for each module, the user should select one of
the other three time base options for one of the
modules.
19.3.10 EFFECTS OF A RESET
A Reset disables the MSSP module and terminates the
current transfer.
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TABLE 19-2: REGISTERS ASSOCIATED WITH SPI OPERATION
Reset
Values
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
on Page:
INTCON
PIR1
GIE/GIEH PEIE/GIEL TMR0IE
INT0IE
TX1IF
RBIE
TMR0IF
CCP1IF
CCP1IE
CCP1IP
CCP5IF
CCP5IE
CCP5IP
TRISC2
TRISD2
TRISF2
INT0IF
RBIF
57
60
PMPIF
PMPIE
PMPIP
SSP2IF
SSP2IE
SSP2IP
TRISC7
TRISD7
TRISF7
ADIF
ADIE
RC1IF
RC1IE
RC1IP
RC2IF
RC2IE
RC2IP
TRISC5
TRISD5
TRISF5
SSP1IF
SSP1IE
SSP1IP
TMR4IF
TMR4IE
TMR4IP
TRISC3
TRISD3
TRISF3
TMR2IF
TMR1IF
PIE1
TX1IE
TX1IP
TX2IF
TMR2IE TMR1IE
TMR2IP TMR1IP
60
IPR1
ADIP
60
PIR3
BCL2IF
BCL2IE
BCL2IP
TRISC6
TRISD6
TRISF6
CCP4IF
CCP4IE
CCP4IP
TRISC1
TRISD1
—
CCP3IF
CCP3IE
CCP3IP
TRISC0
TRISD0
—
60
PIE3
TX2IE
TX2IP
TRISC4
TRISD4
TRISF4
60
IPR3
60
TRISC
TRISD
TRISF
60
60
60
SSP1BUF MSSP1 Receive Buffer/Transmit Register
58
SSPxCON1 WCOL
SSPxSTAT SMP
SSPOV
CKE
SSPEN
D/A
CKP
P
SSPM3
S
SSPM2
R/W
SSPM1
UA
SSPM0
BF
58, 61
58, 61
61
SSP2BUF MSSP2 Receive Buffer/Transmit Register
ODCON3(1)
—
—
—
—
—
—
SPI2OD
SPI1OD
58
Legend: Shaded cells are not used by the MSSP module in SPI mode.
Note 1: Configuration SFR, overlaps with default SFR at this address; available only when WDTCON<4> = 1.
DS39778D-page 232
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2
19.4.1
REGISTERS
19.4 I C Mode
The MSSP module has six registers for I2C operation.
These are:
The MSSP module in I2C mode fully implements all
master and slave functions (including general call
support), and provides interrupts on Start and Stop bits
in hardware to determine a free bus (multi-master
function). The MSSP module implements the standard
mode specifications, as well as 7-bit and 10-bit
addressing.
• MSSPx Control Register 1 (SSPxCON1)
• MSSPx Control Register 2 (SSPxCON2)
• MSSPx Status Register (SSPxSTAT)
• Serial Receive/Transmit Buffer Register
(SSPxBUF)
Two pins are used for data transfer:
• MSSPx Shift Register (SSPxSR) – Not directly
accessible
• Serial Clock (SCLx) – RC3/SCK1/SCL1 or
RD6/SCK2/SCL2
• MSSPx Address Register (SSPxADD)
• I2C Slave Address Mask Register (SSPxMSK)
• Serial Data (SDAx) – RC4/SDI1/SDA1 or
RD5/SDI2/SDA2
SSPxCON1, SSPxCON2 and SSPxSTAT are the
control and status registers in I2C mode operation. The
SSPxCON1 and SSPxCON2 registers are readable and
writable. The lower 6 bits of the SSPxSTAT are
read-only. The upper two bits of the SSPxSTAT are
read/write.
The user must configure these pins as inputs by setting
the associated TRIS bits.
FIGURE 19-7:
MSSP BLOCK DIAGRAM
(I2C™ MODE)
SSPxSR is the shift register used for shifting data in or
out. SSPxBUF is the buffer register to which data
bytes are written to or read from.
Internal
Data Bus
Read
Write
SSPxADD contains the slave device address when the
MSSP is configured in I2C Slave mode. When the
MSSP is configured in Master mode, the lower seven
bits of SSPxADD act as the Baud Rate Generator
reload value.
SSPxBUF reg
SCLx
SDAx
Shift
Clock
SSPxMSK holds the slave address mask value when
the module is configured for 7-bit Address Masking
mode. While it is a separate register, it shares the same
SFR address as SSPxADD; it is only accessible when
the SSPM3:SSPM0 bits are specifically set to permit
access. Additional details are provided in
Section 19.4.3.4 “7-Bit Address Masking Mode”.
SSPxSR reg
LSb
MSb
Match Detect
Addr Match
Address Mask
In receive operations, SSPxSR and SSPxBUF
together, create a double-buffered receiver. When
SSPxSR receives a complete byte, it is transferred to
SSPxBUF and the SSPxIF interrupt is set.
SSPxADD reg
Set, Reset
Start and
Stop bit Detect
During transmission, the SSPxBUF is not
double-buffered. A write to SSPxBUF will write to both
SSPxBUF and SSPxSR.
S, P bits
(SSPxSTAT reg)
Note: Only port I/O names are used in this diagram for
the sake of brevity. Refer to the text for a full list of
multiplexed functions.
© 2009 Microchip Technology Inc.
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REGISTER 19-3: SSPxSTAT: MSSPx STATUS REGISTER (I2C™ MODE)
R/W-0
SMP
R/W-0
CKE
R-0
D/A
R-0
P(1)
R-0
S(1)
R-0
R/W(2,3)
R-0
UA
R-0
BF
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7
bit 6
bit 5
SMP: Slew Rate Control bit
In Master or Slave mode:
1 = Slew rate control disabled for Standard Speed mode (100 kHz and 1 MHz)
0 = Slew rate control enabled for High-Speed mode (400 kHz)
CKE: SMBus Select bit
In Master or Slave mode:
1= Enable SMBus specific inputs
0= Disable SMBus specific inputs
D/A: Data/Address bit
In Master mode:
Reserved.
In Slave mode:
1= Indicates that the last byte received or transmitted was data
0= Indicates that the last byte received or transmitted was address
bit 4
bit 3
bit 2
P: Stop bit(1)
1= Indicates that a Stop bit has been detected last
0= Stop bit was not detected last
S: Start bit(1)
1= Indicates that a Start bit has been detected last
0= Start bit was not detected last
R/W: Read/Write Information bit(2,3)
In Slave mode:
1= Read
0= Write
In Master mode:
1= Transmit is in progress
0= Transmit is not in progress
bit 1
bit 0
UA: Update Address bit (10-Bit Slave mode only)
1= Indicates that the user needs to update the address in the SSPxADD register
0= Address does not need to be updated
BF: Buffer Full Status bit
In Transmit mode:
1= SSPxBUF is full
0= SSPxBUF is empty
In Receive mode:
1= SSPxBUF is full (does not include the ACK and Stop bits)
0= SSPxBUF is empty (does not include the ACK and Stop bits)
Note 1: This bit is cleared on Reset and when SSPEN is cleared.
2: This bit holds the R/W bit information following the last address match. This bit is only valid from the
address match to the next Start bit, Stop bit or not ACK bit.
3: ORing this bit with SEN, RSEN, PEN, RCEN or ACKEN will indicate if the MSSPx is in Active mode.
DS39778D-page 234
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REGISTER 19-4: SSPxCON1: MSSPx CONTROL REGISTER 1 (I2C™ MODE)
R/W-0
WCOL
R/W-0
R/W-0
SSPEN(1)
R/W-0
CKP
R/W-0
SSPM3(2)
R/W-0
SSPM2(2)
R/W-0
SSPM1(2)
R/W-0
SSPM0(2)
SSPOV
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
-n = Value at POR
bit 7
WCOL: Write Collision Detect bit
In Master Transmit mode:
1= A write to the SSPxBUF register was attempted while the I2C conditions were not valid for a
transmission to be started (must be cleared in software)
0= No collision
In Slave Transmit mode:
1= The SSPxBUF register is written while it is still transmitting the previous word (must be cleared in
software)
0= No collision
In Receive mode (Master or Slave modes):
This is a “don’t care” bit.
bit 6
SSPOV: Receive Overflow Indicator bit
In Receive mode:
1= A byte is received while the SSPxBUF register is still holding the previous byte (must be cleared in
software)
0= No overflow
In Transmit mode:
This is a “don’t care” bit in Transmit mode.
bit 5
bit 4
SSPEN: Master Synchronous Serial Port Enable bit(1)
1= Enables the serial port and configures the SDAx and SCLx pins as the serial port pins
0= Disables serial port and configures these pins as I/O port pins
CKP: SCKx Release Control bit
In Slave mode:
1= Releases clock
0= Holds clock low (clock stretch), used to ensure data setup time
In Master mode:
Unused in this mode.
bit 3-0
SSPM3:SSPM0: Master Synchronous Serial Port Mode Select bits(2)
1111= I2C Slave mode, 10-bit address with Start and Stop bit interrupts enabled
1110= I2C Slave mode, 7-bit address with Start and Stop bit interrupts enabled
1011= I2C Firmware Controlled Master mode (Slave Idle)
1001= Load SSPMSK register at SSPADD SFR address(3,4)
1000= I2C Master mode, clock = FOSC/(4 * (SSPxADD + 1))
0111= I2C Slave mode, 10-bit address
0110= I2C Slave mode, 7-bit address
Note 1: When enabled, the SDAx and SCLx pins must be configured as inputs.
2: Bit combinations not specifically listed here are either reserved or implemented in SPI mode only.
3: When SSPM3:SSPM0 = 1001, any reads or writes to the SSPxADD SFR address actually accesses the
SSPxMSK register.
4: This mode is only available when 7-Bit Address Masking mode is selected (MSSPMSK Configuration bit
is ‘1’).
© 2009 Microchip Technology Inc.
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REGISTER 19-5: SSPxCON2: MSSPx CONTROL REGISTER 2 (I2C™ MASTER MODE)
R/W-0
GCEN
R/W-0
R/W-0
ACKDT(1)
R/W-0
ACKEN(2)
R/W-0
RCEN(2)
R/W-0
PEN(2)
R/W-0
RSEN(2)
R/W-0
SEN(2)
ACKSTAT
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7
bit 6
GCEN: General Call Enable bit
Unused in Master mode.
ACKSTAT: Acknowledge Status bit (Master Transmit mode only)
1= Acknowledge was not received from slave
0= Acknowledge was received from slave
bit 5
bit 4
ACKDT: Acknowledge Data bit (Master Receive mode only)(1)
1= Not Acknowledge
0= Acknowledge
ACKEN: Acknowledge Sequence Enable bit(2)
1= Initiates Acknowledge sequence on SDAx and SCLx pins and transmit ACKDT data bit.
Automatically cleared by hardware.
0= Acknowledge sequence Idle
bit 3
bit 2
bit 1
bit 0
RCEN: Receive Enable bit (Master Receive mode only)(2)
1= Enables Receive mode for I2C
0= Receive Idle
PEN: Stop Condition Enable bit(2)
1= Initiates Stop condition on SDAx and SCLx pins. Automatically cleared by hardware.
0= Stop condition Idle
RSEN: Repeated Start Condition Enable bit(2)
1= Initiates Repeated Start condition on SDAx and SCLx pins. Automatically cleared by hardware.
0= Repeated Start condition Idle
SEN: Start Condition Enable bit(2)
1= Initiates Start condition on SDAx and SCLx pins. Automatically cleared by hardware.
0= Start condition Idle
Note 1: Value that will be transmitted when the user initiates an Acknowledge sequence at the end of a receive.
2: If the I2C module is active, these bits may not be set (no spooling) and the SSPxBUF may not be written
(or writes to the SSPxBUF are disabled).
DS39778D-page 236
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REGISTER 19-6: SSPxCON2: MSSPx CONTROL REGISTER 2 (I2C™ SLAVE MODE)
R/W-0
GCEN
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
SEN(1)
ACKSTAT
ADMSK5
ADMSK4
ADMSK3
ADMSK2
ADMSK1
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7
GCEN: General Call Enable bit
1= Enables interrupt when a general call address (0000h) is received in the SSPSR
0= General call address disabled
bit 6
ACKSTAT: Acknowledge Status bit
Unused in Slave mode.
bit 5-2
ADMSK5:ADMSK2: Slave Address Mask Select bits (5-Bit Address Masking mode)
1= Masking of corresponding bits of SSPxADD enabled
0= Masking of corresponding bits of SSPxADD disabled
bit 1
ADMSK1: Slave Address Least Significant bit(s) Mask Select bit
In 7-Bit Addressing mode:
1= Masking of SSPxADD<1> only enabled
0= Masking of SSPxADD<1> only disabled
In 10-Bit Addressing mode:
1= Masking of SSPxADD<1:0> enabled
0= Masking of SSPxADD<1:0> disabled
bit 0
SEN: Stretch Enable bit(1)
1= Clock stretching is enabled for both slave transmit and slave receive (stretch enabled)
0= Clock stretching is disabled
Note 1: If the I2C module is active, this bit may not be set (no spooling) and the SSPBUF may not be written (or
writes to the SSPxBUF are disabled).
REGISTER 19-7: SSPxMSK:I2C™SLAVE ADDRESSMASKREGISTER (7-BITMASKINGMODE)(1)
R/W-1
MSK7
R/W-1
MSK6
R/W-1
MSK5
R/W-1
MSK4
R/W-1
MSK3
R/W-1
MSK2
R/W-1
MSK1
R/W-1
MSK0(2)
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7-0
MSK7:MSK0: Slave Address Mask Select bit
1= Masking of corresponding bit of SSPxADD enabled
0= Masking of corresponding bit of SSPxADD disabled
Note 1: This register shares the same SFR address as SSPxADD, and is only addressable in select MSSPx
operating modes. See Section 19.4.3.4 “7-Bit Address Masking Mode” for more details.
2: MSK0 is not used as a mask bit in 7-bit addressing.
© 2009 Microchip Technology Inc.
DS39778D-page 237
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19.4.2
OPERATION
19.4.3.1
Addressing
The MSSP module functions are enabled by setting the
MSSP Enable bit, SSPEN (SSPxCON1<5>).
The SSPxCON1 register allows control of the I2C
operation. Four mode selection bits (SSPxCON1<3:0>)
allow one of the following I2C modes to be selected:
• I2C Master mode, clock
• I2C Slave mode (7-bit address)
• I2C Slave mode (10-bit address)
Once the MSSP module has been enabled, it waits for
a Start condition to occur. Following the Start condition,
the 8 bits are shifted into the SSPxSR register. All
incoming bits are sampled with the rising edge of the
clock (SCLx) line. The value of register, SSPxSR<7:1>,
is compared to the value of the SSPxADD register. The
address is compared on the falling edge of the eighth
clock (SCLx) pulse. If the addresses match and the BF
and SSPOV bits are clear, the following events occur:
• I2C Slave mode (7-bit address) with Start and
Stop bit interrupts enabled
• I2C Slave mode (10-bit address) with Start and
Stop bit interrupts enabled
• I2C Firmware Controlled Master mode, slave is
Idle
Selection of any I2C mode with the SSPEN bit set
forces the SCLx and SDAx pins to be open-drain,
provided these pins are programmed as inputs by
setting the appropriate TRISC or TRISD bits. To ensure
proper operation of the module, pull-up resistors must
be provided externally to the SCLx and SDAx pins.
1. The SSPxSR register value is loaded into the
SSPxBUF register.
2. The Buffer Full bit, BF, is set.
3. An ACK pulse is generated.
4. The MSSP Interrupt Flag bit, SSPxIF, is set (and
interrupt is generated, if enabled) on the falling
edge of the ninth SCLx pulse.
In 10-Bit Addressing mode, two address bytes need to
be received by the slave. The five Most Significant bits
(MSbs) of the first address byte specify if this is a 10-bit
address. Bit R/W (SSPxSTAT<2>) must specify a write
so the slave device will receive the second address
byte. For a 10-bit address, the first byte would equal
‘11110 A9 A8 0’, where ‘A9’ and ‘A8’ are the two
MSbs of the address. The sequence of events for 10-bit
addressing is as follows, with steps 7 through 9 for the
slave-transmitter:
19.4.3
SLAVE MODE
In Slave mode, the SCLx and SDAx pins must be
configured as inputs (TRISC<4:3> set). The MSSP
module will override the input state with the output data
when required (slave-transmitter).
The I2C Slave mode hardware will always generate an
interrupt on an address match. Address masking will
allow the hardware to generate an interrupt for more
than one address (up to 31 in 7-bit addressing and up
to 63 in 10-bit addressing). Through the mode select
bits, the user can also choose to interrupt on Start and
Stop bits.
1. Receive first (high) byte of address (bits SSPxIF,
BF and UA are set on address match).
2. Update the SSPxADD register with second (low)
byte of address (clears bit UA and releases the
SCLx line).
3. Read the SSPxBUF register (clears bit, BF) and
clear flag bit, SSPxIF.
4. Receive second (low) byte of address (bits
SSPxIF, BF and UA are set).
When an address is matched, or the data transfer after
an address match is received, the hardware auto-
matically will generate the Acknowledge (ACK) pulse
and load the SSPxBUF register with the received value
currently in the SSPxSR register.
5. Update the SSPxADD register with the first
(high) byte of address. If match releases SCLx
line, this will clear bit UA.
6. Read the SSPxBUF register (clears bit BF) and
clear flag bit SSPxIF.
Any combination of the following conditions will cause
the MSSP module not to give this ACK pulse:
7. Receive Repeated Start condition.
• The Buffer Full bit, BF (SSPxSTAT<0>), was set
before the transfer was received.
8. Receive first (high) byte of address (bits SSPxIF
and BF are set).
• The overflow bit, SSPOV (SSPxCON1<6>), was
set before the transfer was received.
9. Read the SSPxBUF register (clears bit BF) and
clear flag bit, SSPxIF.
In this case, the SSPxSR register value is not loaded
into the SSPxBUF, but bit SSPxIF is set. The BF bit is
cleared by reading the SSPxBUF register, while bit
SSPOV is cleared through software.
The SCLx clock input must have a minimum high and
low for proper operation. The high and low times of the
I2C specification, as well as the requirement of the
MSSP module, are shown in timing parameter 100 and
parameter 101.
DS39778D-page 238
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Acknowledge up to 31 addresses when using 7-bit
addressing, or 63 addresses with 10-bit addressing
(see Example 19-2). This Masking mode is selected
when the MSSPMSK Configuration bit is programmed
(‘0’).
19.4.3.2
Address Masking Modes
Masking an address bit causes that bit to become a
“don’t care”. When one address bit is masked, two
addresses will be Acknowledged and cause an
interrupt. It is possible to mask more than one address
bit at a time, which greatly expands the number of
addresses Acknowledged.
The I2C Slave behaves the same way whether address
masking is used or not. However, when address
masking is used, the I2C slave can Acknowledge
multiple addresses and cause interrupts. When this
occurs, it is necessary to determine which address
caused the interrupt by checking the SSPxBUF.
The address mask in this mode is stored in the
SSPxCON2 register, which stops functioning as a con-
trol register in I2C Slave mode (Register 19-6). In 7-Bit
Address Masking mode, address mask bits,
ADMSK<5:1> (SSPxCON2<5:1>), mask the corre-
sponding address bits in the SSPxADD register. For
any ADMSK bits that are set (ADMSK<n> = 1), the cor-
responding address bit is ignored (SSPxADD<n> = x).
For the module to issue an address Acknowledge, it is
sufficient to match only on addresses that do not have
an active address mask.
The PIC18F87J11 Family of devices is capable of using
two different Address Masking modes in I2C Slave
operation: 5-Bit Address Masking and 7-Bit Address
Masking. The Masking mode is selected at device
configuration using the MSSPMSK Configuration bit.
The default device configuration is 7-Bit Address
Masking.
In 10-Bit Address Masking mode, bits ADMSK<5:2>
mask the corresponding address bits in the SSPxADD
register. In addition, ADMSK1 simultaneously masks
the two LSbs of the address (SSPxADD<1:0>). For any
ADMSK bits that are active (ADMSK<n> = 1), the cor-
responding address bit is ignored (SPxADD<n> = x).
Also note, that although in 10-Bit Address Masking
mode, the upper address bits reuse part of the
SSPxADD register bits. The address mask bits do not
interact with those bits; they only affect the lower
address bits.
Both Masking modes, in turn, support address masking
of 7-bit and 10-bit addresses. The combination of
Masking modes and addresses provide different
ranges of Acknowledgable addresses for each
combination.
While both Masking modes function in roughly the
same manner, the way they use address masks are
different.
Note 1: ADMSK1 masks the two Least Significant
bits of the address.
2: The two Most Significant bits of the
address are not affected by address
masking.
19.4.3.3
5-Bit Address Masking Mode
As the name implies, 5-Bit Address Masking mode
uses an address mask of up to 5 bits to create a range
of addresses to be Acknowledged, using bits 5 through
1 of the incoming address. This allows the module to
EXAMPLE 19-2:
7-Bit Addressing:
ADDRESS MASKING EXAMPLES IN 5-BIT MASKING MODE
SSPADD<7:1>= A0h (1010000) (SSPADD<0> is assumed to be ‘0’)
ADMSK<5:1> = 00111
Addresses Acknowledged: A0h, A2h, A4h, A6h, A8h, AAh, ACh, AEh
10-Bit Addressing:
SSPADD<7:0> = A0h (10100000) (The two MSb of the address are ignored in this example, since they
are not affected by masking)
ADMSK<5:1> = 00111
Addresses Acknowledged: A0h, A1h, A2h, A3h, A4h, A5h, A6h, A7h, A8h, A9h, AAh, ABh, ACh, ADh,
AEh, AFh
© 2009 Microchip Technology Inc.
DS39778D-page 239
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Setting or clearing mask bits in SSPxMSK behaves in
the opposite manner of the ADMSK bits in 5-Bit
Address Masking mode. That is, clearing a bit in
SSPxMSK causes the corresponding address bit to be
masked; setting the bit requires a match in that
position. SSPxMSK resets to all ‘1’s upon any Reset
condition and, therefore, has no effect on the standard
MSSP operation until written with a mask value.
19.4.3.4
7-Bit Address Masking Mode
Unlike 5-bit masking, 7-Bit Address Masking mode
uses a mask of up to 8 bits (in 10-bit addressing) to
define a range of addresses than can be Acknowl-
edged, using the lowest bits of the incoming address.
This allows the module to Acknowledge up to 127 dif-
ferent addresses with 7-bit addressing, or 255 with
10-bit addressing (see Example 19-3). This mode is
the default configuration of the module, and is selected
when MSSPMSK is unprogrammed (‘1’).
With 7-bit addressing, SSPxMSK<7:1> bits mask the
corresponding address bits in the SSPxADD register.
For any SSPxMSK bits that are active
(SSPxMSK<n> = 0), the corresponding SSPxADD
address bit is ignored (SSPxADD<n> = x). For the
module to issue an address Acknowledge, it is suffi-
cient to match only on addresses that do not have an
active address mask.
The address mask for 7-Bit Address Masking mode is
stored in the SSPxMSK register, instead of the
SSPxCON2 register. SSPxMSK is a separate hard-
ware register within the module, but it is not directly
addressable. Instead, it shares an address in the SFR
space with the SSPxADD register. To access the
SSPxMSK register, it is necessary to select MSSP
mode, ‘1001’ (SSPCON1<3:0> = 1001), and then read
or write to the location of SSPxADD.
With 10-bit addressing, SSPxMSK<7:0> bits mask the
corresponding address bits in the SSPxADD register.
For any SSPxMSK bits that are active (= 0), the corre-
sponding SSPxADD address bit is ignored
(SSPxADD<n> = x).
To use 7-Bit Address Masking mode, it is necessary to
initialize SSPxMSK with a value before selecting the
I2C Slave Addressing mode. Thus, the required
sequence of events is:
Note:
The two Most Significant bits of the
address are not affected by address
masking.
1. Select
SSPxMSK
Access
mode
(SSPxCON2<3:0> = 1001).
2. Write the mask value to the appropriate
SSPADD register address (FC8h for MSSP1,
F6Eh for MSSP2).
3. Set the appropriate I2C Slave mode
(SSPxCON2<3:0>
=
0111
for
10-bit
addressing, 0110for 7-bit addressing).
EXAMPLE 19-3:
7-Bit Addressing:
ADDRESS MASKING EXAMPLES IN 7-BIT MASKING MODE
SSPxADD<7:1> = 1010 000
SSPxMSK<7:1> = 1111 001
Addresses Acknowledged = A8h, A6h, A4h, A0h
10-Bit Addressing:
SSPxADD<7:0> = 1010 0000(The two MSb are ignored in this example since they are not affected)
SSPxMSK<5:1> = 1111 0
Addresses Acknowledged = A8h, A6h, A4h, A0h
DS39778D-page 240
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19.4.3.5
Reception
19.4.3.6
Transmission
When the R/W bit of the address byte is clear and an
address match occurs, the R/W bit of the SSPxSTAT
register is cleared. The received address is loaded into
the SSPxBUF register and the SDAx line is held low
(ACK).
When the R/W bit of the incoming address byte is set
and an address match occurs, the R/W bit of the
SSPxSTAT register is set. The received address is
loaded into the SSPxBUF register. The ACK pulse will
be sent on the ninth bit and pin SCLx is held low regard-
less of SEN (see Section 19.4.4 “Clock Stretching”
for more details). By stretching the clock, the master
will be unable to assert another clock pulse until the
slave is done preparing the transmit data. The transmit
data must be loaded into the SSPxBUF register which
also loads the SSPxSR register. Then, pin SCLx should
be enabled by setting bit, CKP (SSPxCON1<4>). The
eight data bits are shifted out on the falling edge of the
SCLx input. This ensures that the SDAx signal is valid
during the SCLx high time (Figure 19-10).
When the address byte overflow condition exists, then
the no Acknowledge (ACK) pulse is given. An overflow
condition is defined as either bit, BF (SSPxSTAT<0>),
is set or bit, SSPOV (SSPxCON1<6>), is set.
An MSSP interrupt is generated for each data transfer
byte. The interrupt flag bit, SSPxIF, must be cleared in
software. The SSPxSTAT register is used to determine
the status of the byte.
If SEN is enabled (SSPxCON2<0> = 1), SCLx will be
held low (clock stretch) following each data transfer. The
clock must be released by setting bit, CKP
The ACK pulse from the master-receiver is latched on
the rising edge of the ninth SCLx input pulse. If the
SDAx line is high (not ACK), then the data transfer is
complete. In this case, when the ACK is latched by the
slave, the slave logic is reset and the slave monitors for
another occurrence of the Start bit. If the SDAx line was
low (ACK), the next transmit data must be loaded into
the SSPxBUF register. Again, pin SCLx must be
enabled by setting bit, CKP.
(SSPxCON1<4>).
See
Section 19.4.4
“Clock
Stretching” for more details.
An MSSP interrupt is generated for each data transfer
byte. The SSPxIF bit must be cleared in software and
the SSPxSTAT register is used to determine the status
of the byte. The SSPxIF bit is set on the falling edge of
the ninth clock pulse.
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DS39778D-page 241
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2
FIGURE 19-8:
I C™ SLAVE MODE TIMING WITH SEN = 0(RECEPTION, 7-BIT ADDRESS)
DS39778D-page 242
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2
FIGURE 19-9:
I C™ SLAVE MODE TIMING WITH SEN = 0AND ADMSK<5:1> = 01011
(RECEPTION, 7-BIT ADDRESS)
© 2009 Microchip Technology Inc.
DS39778D-page 243
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2
FIGURE 19-10:
I C™ SLAVE MODE TIMING (TRANSMISSION, 7-BIT ADDRESS)
DS39778D-page 244
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FIGURE 19-11:
I2C™ SLAVE MODE TIMING WITH SEN = 0AND ADMSK<5:1> = 01001
(RECEPTION, 10-BIT ADDRESS)
© 2009 Microchip Technology Inc.
DS39778D-page 245
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FIGURE 19-12:
I2C™ SLAVE MODE TIMING WITH SEN = 0(RECEPTION, 10-BIT ADDRESS)
DS39778D-page 246
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2
FIGURE 19-13:
I C™ SLAVE MODE TIMING (TRANSMISSION, 10-BIT ADDRESS)
© 2009 Microchip Technology Inc.
DS39778D-page 247
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19.4.4
CLOCK STRETCHING
19.4.4.3
Clock Stretching for 7-Bit Slave
Transmit Mode
Both 7-Bit and 10-Bit Slave modes implement
automatic clock stretching during a transmit sequence.
The 7-Bit Slave Transmit mode implements clock
stretching by clearing the CKP bit after the falling edge
of the ninth clock if the BF bit is clear. This occurs
regardless of the state of the SEN bit.
The SEN bit (SSPxCON2<0>) allows clock stretching
to be enabled during receives. Setting SEN will cause
the SCLx pin to be held low at the end of each data
receive sequence.
The user’s ISR must set the CKP bit before transmis-
sion is allowed to continue. By holding the SCLx line
low, the user has time to service the ISR and load the
contents of the SSPxBUF before the master device
can initiate another transmit sequence (see
Figure 19-10).
19.4.4.1
Clock Stretching for 7-Bit Slave
Receive Mode (SEN = 1)
In 7-Bit Slave Receive mode, on the falling edge of the
ninth clock at the end of the ACK sequence, if the BF
bit is set, the CKP bit in the SSPxCON1 register is
automatically cleared, forcing the SCLx output to be
held low. The CKP bit being cleared to ‘0’ will assert
the SCLx line low. The CKP bit must be set in the
user’s ISR before reception is allowed to continue. By
holding the SCLx line low, the user has time to service
the ISR and read the contents of the SSPxBUF before
the master device can initiate another receive
sequence. This will prevent buffer overruns from
occurring (see Figure 19-15).
Note 1: If the user loads the contents of
SSPxBUF, setting the BF bit before the
falling edge of the ninth clock, the CKP bit
will not be cleared and clock stretching
will not occur.
2: The CKP bit can be set in software
regardless of the state of the BF bit.
19.4.4.4
Clock Stretching for 10-Bit Slave
Transmit Mode
Note 1: If the user reads the contents of the
SSPxBUF before the falling edge of the
ninth clock, thus clearing the BF bit, the
CKP bit will not be cleared and clock
stretching will not occur.
In 10-Bit Slave Transmit mode, clock stretching is
controlled during the first two address sequences by
the state of the UA bit, just as it is in 10-Bit Slave
Receive mode. The first two addresses are followed
by a third address sequence, which contains the
high-order bits of the 10-bit address and the R/W bit
set to ‘1’. After the third address sequence is
performed, the UA bit is not set, the module is now
configured in Transmit mode and clock stretching is
controlled by the BF flag as in 7-Bit Slave Transmit
mode (see Figure 19-13).
2: The CKP bit can be set in software
regardless of the state of the BF bit. The
user should be careful to clear the BF bit
in the ISR before the next receive
sequence in order to prevent an overflow
condition.
19.4.4.2
Clock Stretching for 10-Bit Slave
Receive Mode (SEN = 1)
In 10-Bit Slave Receive mode, during the address
sequence, clock stretching automatically takes place
but CKP is not cleared. During this time, if the UA bit is
set after the ninth clock, clock stretching is initiated.
The UA bit is set after receiving the upper byte of the
10-bit address and following the receive of the second
byte of the 10-bit address with the R/W bit cleared to
‘0’. The release of the clock line occurs upon updating
SSPxADD. Clock stretching will occur on each data
receive sequence as described in 7-bit mode.
Note:
If the user polls the UA bit and clears it by
updating the SSPxADD register before the
falling edge of the ninth clock occurs, and
if the user hasn’t cleared the BF bit by
reading the SSPxBUF register before that
time, then the CKP bit will still NOT be
asserted low. Clock stretching on the basis
of the state of the BF bit only occurs during
a
data sequence, not an address
sequence.
DS39778D-page 248
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PIC18F87J11 FAMILY
already asserted the SCLx line. The SCLx output will
remain low until the CKP bit is set and all other
devices on the I2C bus have deasserted SCLx. This
ensures that a write to the CKP bit will not violate the
minimum high time requirement for SCLx (see
Figure 19-14).
19.4.4.5
Clock Synchronization and
the CKP bit
When the CKP bit is cleared, the SCLx output is forced
to ‘0’. However, clearing the CKP bit will not assert the
SCLx output low until the SCLx output is already
sampled low. Therefore, the CKP bit will not assert the
SCLx line until an external I2C master device has
FIGURE 19-14:
CLOCK SYNCHRONIZATION TIMING
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
SDAx
SCLx
DX – 1
DX
Master device
asserts clock
CKP
Master device
deasserts clock
WR
SSPxCON1
© 2009 Microchip Technology Inc.
DS39778D-page 249
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FIGURE 19-15:
I C™ SLAVE MODE TIMING WITH SEN = 1(RECEPTION, 7-BIT ADDRESS)
DS39778D-page 250
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FIGURE 19-16:
I2C™ SLAVE MODE TIMING WITH SEN = 1(RECEPTION, 10-BIT ADDRESS)
© 2009 Microchip Technology Inc.
DS39778D-page 251
PIC18F87J11 FAMILY
If the general call address matches, the SSPxSR is
transferred to the SSPxBUF, the BF flag bit is set
(eighth bit), and on the falling edge of the ninth bit (ACK
bit), the SSPxIF interrupt flag bit is set.
19.4.5
GENERAL CALL ADDRESS
SUPPORT
The addressing procedure for the I2C bus is such that
the first byte after the Start condition usually
determines which device will be the slave addressed by
the master. The exception is the general call address
which can address all devices. When this address is
used, all devices should, in theory, respond with an
Acknowledge.
When the interrupt is serviced, the source for the
interrupt can be checked by reading the contents of the
SSPxBUF. The value can be used to determine if the
address was device-specific or a general call address.
In 10-Bit Addressing mode, the SSPxADD is required
to be updated for the second half of the address to
match and the UA bit is set (SSPxSTAT<1>). If the gen-
eral call address is sampled when the GCEN bit is set,
while the slave is configured in 10-Bit Addressing
mode, then the second half of the address is not
necessary, the UA bit will not be set and the slave will
begin receiving data after the Acknowledge
(Figure 19-17).
The general call address is one of eight addresses
reserved for specific purposes by the I2C protocol. It
consists of all ‘0’s with R/W = 0.
The general call address is recognized when the
General Call Enable bit, GCEN, is enabled
(SSPxCON2<7> set). Following a Start bit detect, 8 bits
are shifted into the SSPxSR and the address is
compared against the SSPxADD. It is also compared to
the general call address and fixed in hardware.
FIGURE 19-17:
SLAVE MODE GENERAL CALL ADDRESS SEQUENCE
(7 OR 10-BIT ADDRESSING MODE)
Address is Compared to General Call Address
after ACK, set interrupt
Receiving Data
ACK
R/W = 0
General Call Address
SDAx
SCLx
ACK D7 D6
D5 D4 D3 D2 D1 D0
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
9
S
SSPxIF
BF (SSPxSTAT<0>)
Cleared in software
SSPxBUF is read
SSPOV (SSPxCON1<6>)
GCEN (SSPxCON2<7>)
‘0’
‘1’
DS39778D-page 252
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19.4.6
MASTER MODE
Note:
The MSSP module, when configured in
I2C Master mode, does not allow queueing
of events. For instance, the user is not
allowed to initiate a Start condition and
immediately write the SSPxBUF register to
initiate transmission before the Start
condition is complete. In this case, the
SSPxBUF will not be written to and the
WCOL bit will be set, indicating that a write
to the SSPxBUF did not occur.
Master mode is enabled by setting and clearing the
appropriate SSPM bits in SSPxCON1 and by setting
the SSPEN bit. In Master mode, the SCLx and SDAx
lines are manipulated by the MSSP hardware if the
TRIS bits are set.
Master mode of operation is supported by interrupt
generation on the detection of the Start and Stop
conditions. The Stop (P) and Start (S) bits are cleared
from a Reset or when the MSSP module is disabled.
Control of the I2C bus may be taken when the P bit is
set, or the bus is Idle, with both the S and P bits clear.
The following events will cause the MSSP Interrupt
Flag bit, SSPxIF, to be set (and MSSP interrupt, if
enabled):
In Firmware Controlled Master mode, user code
conducts all I2C bus operations based on Start and
Stop bit conditions.
• Start condition
• Stop condition
Once Master mode is enabled, the user has six
options.
• Data transfer byte transmitted/received
• Acknowledge transmitted
• Repeated Start
1. Assert a Start condition on SDAx and SCLx.
2. Assert a Repeated Start condition on SDAx and
SCLx.
3. Write to the SSPxBUF register initiating
transmission of data/address.
4. Configure the I2C port to receive data.
5. Generate an Acknowledge condition at the end
of a received byte of data.
6. Generate a Stop condition on SDAx and SCLx.
2
FIGURE 19-18:
MSSP BLOCK DIAGRAM (I C™ MASTER MODE)
Internal
Data Bus
SSPM3:SSPM0
SSPxADD<6:0>
Read
Write
SSPxBUF
SSPxSR
Baud
Rate
Generator
SDAx
Shift
Clock
SDAx In
MSb
LSb
Start bit, Stop bit,
Acknowledge
Generate
SCLx
Start bit Detect
Stop bit Detect
Write Collision Detect
Clock Arbitration
State Counter for
End of XMIT/RCV
SCLx In
Bus Collision
Set/Reset S, P (SSPxSTAT), WCOL (SSPxCON1);
Set SSPxIF, BCLxIF;
Reset ACKSTAT, PEN (SSPxCON2)
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I2C Master Mode Operation
A typical transmit sequence would go as follows:
19.4.6.1
1. The user generates a Start condition by setting
the Start Enable bit, SEN (SSPxCON2<0>).
The master device generates all of the serial clock
pulses and the Start and Stop conditions. A transfer is
ended with a Stop condition or with a Repeated Start
condition. Since the Repeated Start condition is also
the beginning of the next serial transfer, the I2C bus will
not be released.
2. SSPxIF is set. The MSSP module will wait the
required start time before any other operation
takes place.
3. The user loads the SSPxBUF with the slave
address to transmit.
In Master Transmitter mode, serial data is output
through SDAx while SCLx outputs the serial clock. The
first byte transmitted contains the slave address of the
receiving device (7 bits) and the Read/Write (R/W) bit.
In this case, the R/W bit will be logic ‘0’. Serial data is
transmitted 8 bits at a time. After each byte is transmit-
ted, an Acknowledge bit is received. Start and Stop
conditions are output to indicate the beginning and the
end of a serial transfer.
4. Address is shifted out the SDAx pin until all 8 bits
are transmitted.
5. The MSSP module shifts in the ACK bit from the
slave device and writes its value into the
SSPxCON2 register (SSPxCON2<6>).
6. The MSSP module generates an interrupt at the
end of the ninth clock cycle by setting the
SSPxIF bit.
In Master Receive mode, the first byte transmitted
contains the slave address of the transmitting device
(7 bits) and the R/W bit. In this case, the R/W bit will be
logic ‘1’. Thus, the first byte transmitted is a 7-bit slave
address, followed by a ‘1’ to indicate the receive bit.
Serial data is received via SDAx, while SCLx outputs
the serial clock. Serial data is received 8 bits at a time.
After each byte is received, an Acknowledge bit is
transmitted. Start and Stop conditions indicate the
beginning and end of transmission.
7. The user loads the SSPxBUF with eight bits of
data.
8. Data is shifted out the SDAx pin until all 8 bits
are transmitted.
9. The MSSP module shifts in the ACK bit from the
slave device and writes its value into the
SSPxCON2 register (SSPxCON2<6>).
10. The MSSP module generates an interrupt at the
end of the ninth clock cycle by setting the
SSPxIF bit.
The Baud Rate Generator, used for the SPI mode
operation, is used to set the SCLx clock frequency for
either 100 kHz, 400 kHz or 1 MHz I2C operation. See
Section 19.4.7 “Baud Rate” for more details.
11. The user generates a Stop condition by setting
the Stop Enable bit, PEN (SSPxCON2<2>).
12. Interrupt is generated once the Stop condition is
complete.
DS39778D-page 254
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19.4.7
BAUD RATE
19.4.7.1
Baud Rate and Module
Interdependence
In I2C Master mode, the Baud Rate Generator (BRG)
reload value is placed in the lower 7 bits of the
SSPxADD register (Figure 19-19). When a write
occurs to SSPxBUF, the Baud Rate Generator will
automatically begin counting. The BRG counts down to
0 and stops until another reload has taken place. The
BRG count is decremented twice per instruction cycle
(TCY) on the Q2 and Q4 clocks. In I2C Master mode, the
BRG is reloaded automatically.
Because MSSP1 and MSSP2 are independent, they
can operate simultaneously in I2C Master mode at
different baud rates. This is done by using different
BRG reload values for each module.
Because this mode derives its basic clock source from
the system clock, any changes to the clock will affect
both modules in the same proportion. It may be
possible to change one or both baud rates back to a
previous value by changing the BRG reload value.
Once the given operation is complete (i.e., transmis-
sion of the last data bit is followed by ACK), the internal
clock will automatically stop counting and the SCLx pin
will remain in its last state.
Table 19-3 demonstrates clock rates based on
instruction cycles and the BRG value loaded into
SSPxADD.
FIGURE 19-19:
BAUD RATE GENERATOR BLOCK DIAGRAM
SSPM3:SSPM0
SSPxADD<6:0>
SSPM3:SSPM0
SCLx
Reload
Control
Reload
BRG Down Counter
CLKO
FOSC/4
TABLE 19-3: I2C™ CLOCK RATE w/BRG
FSCL
FOSC
FCY
FCY * 2
BRG Value
(2 Rollovers of BRG)
40 MHz
40 MHz
40 MHz
16 MHz
16 MHz
16 MHz
4 MHz
10 MHz
10 MHz
10 MHz
4 MHz
4 MHz
4 MHz
1 MHz
1 MHz
1 MHz
20 MHz
20 MHz
20 MHz
8 MHz
8 MHz
8 MHz
2 MHz
2 MHz
2 MHz
18h
1Fh
63h
09h
0Ch
27h
02h
09h
00h
400 kHz(1)
312.5 kHz
100 kHz
400 kHz(1)
308 kHz
100 kHz
333 kHz(1)
4 MHz
100 kHz
1 MHz(1)
4 MHz
Note 1: The I2C interface does not conform to the 400 kHz I2C specification (which applies to rates greater than
100 kHz) in all details, but may be used with care where higher rates are required by the application.
© 2009 Microchip Technology Inc.
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SCLx pin is sampled high, the Baud Rate Generator is
reloaded with the contents of SSPxADD<6:0> and
begins counting. This ensures that the SCLx high time
will always be at least one BRG rollover count in the
event that the clock is held low by an external device
(Figure 19-20).
19.4.7.2
Clock Arbitration
Clock arbitration occurs when the master, during any
receive, transmit or Repeated Start/Stop condition,
deasserts the SCLx pin (SCLx allowed to float high).
When the SCLx pin is allowed to float high, the Baud
Rate Generator (BRG) is suspended from counting
until the SCLx pin is actually sampled high. When the
FIGURE 19-20:
BAUD RATE GENERATOR TIMING WITH CLOCK ARBITRATION
SDAx
DX
DX – 1
SCLx allowed to transition high
SCLx deasserted but slave holds
SCLx low (clock arbitration)
SCLx
BRG decrements on
Q2 and Q4 cycles
BRG
Value
03h
02h
01h
00h (hold off)
03h
02h
SCLx is sampled high, reload takes
place and BRG starts its count
BRG
Reload
DS39778D-page 256
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19.4.8
I2C MASTER MODE START
CONDITION TIMING
Note:
If, at the beginning of the Start condition,
the SDAx and SCLx pins are already sam-
pled low or if during the Start condition, the
SCLx line is sampled low before the SDAx
line is driven low, a bus collision occurs,
the Bus Collision Interrupt Flag, BCLxIF, is
set, the Start condition is aborted and the
I2C module is reset into its Idle state.
To initiate a Start condition, the user sets the Start
Enable bit, SEN (SSPxCON2<0>). If the SDAx and
SCLx pins are sampled high, the Baud Rate Generator
is reloaded with the contents of SSPxADD<6:0> and
starts its count. If SCLx and SDAx are both sampled
high when the Baud Rate Generator times out (TBRG),
the SDAx pin is driven low. The action of the SDAx
being driven low while SCLx is high is the Start condi-
tion and causes the S bit (SSPxSTAT<3>) to be set.
Following this, the Baud Rate Generator is reloaded
with the contents of SSPxADD<6:0> and resumes its
count. When the Baud Rate Generator times out
(TBRG), the SEN bit (SSPxCON2<0>) will be
automatically cleared by hardware. The Baud Rate
Generator is suspended, leaving the SDAx line held low
and the Start condition is complete.
19.4.8.1
WCOL Status Flag
If the user writes the SSPxBUF when a Start sequence
is in progress, the WCOL bit is set and the contents of
the buffer are unchanged (the write doesn’t occur).
Note:
Because queueing of events is not
allowed, writing to the lower 5 bits of
SSPxCON2 is disabled until the Start
condition is complete.
FIGURE 19-21:
FIRST START BIT TIMING
Set S bit (SSPxSTAT<3>)
Write to SEN bit occurs here
SDAx = 1,
At completion of Start bit,
hardware clears SEN bit
and sets SSPxIF bit
SCLx = 1
TBRG
TBRG
Write to SSPxBUF occurs here
2nd bit
1st bit
SDAx
TBRG
SCLx
TBRG
S
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19.4.9
I2C MASTER MODE REPEATED
START CONDITION TIMING
Note 1: If RSEN is programmed while any other
event is in progress, it will not take effect.
A Repeated Start condition occurs when the RSEN bit
(SSPxCON2<1>) is programmed high and the I2C logic
module is in the Idle state. When the RSEN bit is set,
the SCLx pin is asserted low. When the SCLx pin is
sampled low, the Baud Rate Generator is loaded with
the contents of SSPxADD<5:0> and begins counting.
The SDAx pin is released (brought high) for one Baud
Rate Generator count (TBRG). When the Baud Rate
Generator times out and if SDAx is sampled high, the
SCLx pin will be deasserted (brought high). When
SCLx is sampled high, the Baud Rate Generator is
reloaded with the contents of SSPxADD<6:0> and
begins counting. SDAx and SCLx must be sampled
high for one TBRG. This action is then followed by
assertion of the SDAx pin (SDAx = 0) for one TBRG
while SCLx is high. Following this, the RSEN bit
(SSPxCON2<1>) will be automatically cleared and the
Baud Rate Generator will not be reloaded, leaving the
SDAx pin held low. As soon as a Start condition is
detected on the SDAx and SCLx pins, the S bit
(SSPxSTAT<3>) will be set. The SSPxIF bit will not be
set until the Baud Rate Generator has timed out.
2: A bus collision during the Repeated Start
condition occurs if:
• SDAx is sampled low when SCLx
goes from low-to-high.
• SCLx goes low before SDAx is
asserted low. This may indicate that
another master is attempting to
transmit a data ‘1’.
Immediately following the SSPxIF bit getting set, the
user may write the SSPxBUF with the 7-bit address in
7-bit mode, or the default first address in 10-bit mode.
After the first eight bits are transmitted and an ACK is
received, the user may then transmit an additional eight
bits of address (10-bit mode) or eight bits of data (7-bit
mode).
19.4.9.1
WCOL Status Flag
If the user writes the SSPxBUF when a Repeated Start
sequence is in progress, the WCOL is set and the
contents of the buffer are unchanged (the write doesn’t
occur).
Note:
Because queueing of events is not
allowed, writing of the lower 5 bits of
SSPxCON2 is disabled until the Repeated
Start condition is complete.
FIGURE 19-22:
REPEATED START CONDITION WAVEFORM
S bit set by hardware
SDAx = 1,
SCLx = 1
At completion of Start bit,
hardware clears RSEN bit
and sets SSPxIF
Write to SSPxCON2 occurs here:
SDAx = 1,
SCLx (no change).
TBRG TBRG
TBRG
1st bit
SDAx
RSEN bit set by hardware
on falling edge of ninth clock,
end of XMIT
Write to SSPxBUF occurs here
TBRG
SCLx
TBRG
Sr = Repeated Start
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19.4.10 I2C MASTER MODE TRANSMISSION
The user should verify that the WCOL bit is clear after
each write to SSPxBUF to ensure the transfer is correct.
In all cases, WCOL must be cleared in software.
Transmission of a data byte, a 7-bit address or the
other half of a 10-bit address, is accomplished by sim-
ply writing a value to the SSPxBUF register. This action
will set the Buffer Full flag bit, BF, and allow the Baud
Rate Generator to begin counting and start the next
transmission. Each bit of address/data will be shifted
out onto the SDAx pin after the falling edge of SCLx is
asserted (see data hold time specification
parameter 106). SCLx is held low for one Baud Rate
Generator rollover count (TBRG). Data should be valid
before SCLx is released high (see data setup time
specification parameter 107). When the SCLx pin is
released high, it is held that way for TBRG. The data on
the SDAx pin must remain stable for that duration and
some hold time after the next falling edge of SCLx.
After the eighth bit is shifted out (the falling edge of the
eighth clock), the BF flag is cleared and the master
releases SDAx. This allows the slave device being
addressed to respond with an ACK bit during the ninth
bit time if an address match occurred, or if data was
received properly. The status of ACK is written into the
ACKDT bit on the falling edge of the ninth clock. If the
master receives an Acknowledge, the Acknowledge
Status bit, ACKSTAT, is cleared; if not, the bit is set.
After the ninth clock, the SSPxIF bit is set and the
master clock (Baud Rate Generator) is suspended until
the next data byte is loaded into the SSPxBUF, leaving
SCLx low and SDAx unchanged (Figure 19-23).
19.4.10.3 ACKSTAT Status Flag
In Transmit mode, the ACKSTAT bit (SSPxCON2<6>)
is cleared when the slave has sent an Acknowledge
(ACK = 0) and is set when the slave does not Acknowl-
edge (ACK = 1). A slave sends an Acknowledge when
it has recognized its address (including a general call),
or when the slave has properly received its data.
19.4.11 I2C MASTER MODE RECEPTION
Master mode reception is enabled by programming the
Receive Enable bit, RCEN (SSPxCON2<3>).
Note:
The MSSP module must be in an inactive
state before the RCEN bit is set or the
RCEN bit will be disregarded.
The Baud Rate Generator begins counting and on each
rollover, the state of the SCLx pin changes
(high-to-low/low-to-high) and data is shifted into the
SSPxSR. After the falling edge of the eighth clock, the
receive enable flag is automatically cleared, the con-
tents of the SSPxSR are loaded into the SSPxBUF, the
BF flag bit is set, the SSPxIF flag bit is set and the Baud
Rate Generator is suspended from counting, holding
SCLx low. The MSSP is now in Idle state awaiting the
next command. When the buffer is read by the CPU,
the BF flag bit is automatically cleared. The user can
then send an Acknowledge bit at the end of reception
by setting the Acknowledge Sequence Enable bit,
ACKEN (SSPxCON2<4>).
After the write to the SSPxBUF, each bit of the address
will be shifted out on the falling edge of SCLx until all
seven address bits and the R/W bit are completed. On
the falling edge of the eighth clock, the master will
deassert the SDAx pin, allowing the slave to respond
with an Acknowledge. On the falling edge of the ninth
clock, the master will sample the SDAx pin to see if the
address was recognized by a slave. The status of the
ACK bit is loaded into the ACKSTAT status bit
(SSPxCON2<6>). Following the falling edge of the
ninth clock transmission of the address, the SSPxIF
flag is set, the BF flag is cleared and the Baud Rate
Generator is turned off until another write to the
SSPxBUF takes place, holding SCLx low and allowing
SDAx to float.
19.4.11.1 BF Status Flag
In receive operation, the BF bit is set when an address
or data byte is loaded into SSPxBUF from SSPxSR. It
is cleared when the SSPxBUF register is read.
19.4.11.2 SSPOV Status Flag
In receive operation, the SSPOV bit is set when 8 bits
are received into the SSPxSR and the BF flag bit is
already set from a previous reception.
19.4.11.3 WCOL Status Flag
19.4.10.1 BF Status Flag
If the user writes the SSPxBUF when a receive is
already in progress (i.e., SSPxSR is still shifting in a
data byte), the WCOL bit is set and the contents of the
buffer are unchanged (the write doesn’t occur).
In Transmit mode, the BF bit (SSPxSTAT<0>) is set
when the CPU writes to SSPxBUF and is cleared when
all 8 bits are shifted out.
19.4.10.2 WCOL Status Flag
If the user writes the SSPxBUF when a transmit is
already in progress (i.e., SSPxSR is still shifting out a
data byte), the WCOL bit is set and the contents of the
buffer are unchanged (the write doesn’t occur) after
2 TCY after the SSPxBUF write. If SSPxBUF is rewritten
within 2 TCY, the WCOL bit is set and SSPxBUF is
updated. This may result in a corrupted transfer.
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2
FIGURE 19-23:
I C™ MASTER MODE WAVEFORM (TRANSMISSION, 7 OR 10-BIT ADDRESS)
DS39778D-page 260
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2
FIGURE 19-24:
I C™ MASTER MODE WAVEFORM (RECEPTION, 7-BIT ADDRESS)
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19.4.12 ACKNOWLEDGE SEQUENCE
TIMING
19.4.13 STOP CONDITION TIMING
A Stop bit is asserted on the SDAx pin at the end of a
receive/transmit by setting the Stop Sequence Enable
bit, PEN (SSPxCON2<2>). At the end of
An Acknowledge sequence is enabled by setting the
Acknowledge Sequence Enable bit, ACKEN
(SSPxCON2<4>). When this bit is set, the SCLx pin is
pulled low and the contents of the Acknowledge data bit
are presented on the SDAx pin. If the user wishes to
generate an Acknowledge, then the ACKDT bit should
be cleared. If not, the user should set the ACKDT bit
before starting an Acknowledge sequence. The Baud
Rate Generator then counts for one rollover period
(TBRG) and the SCLx pin is deasserted (pulled high).
When the SCLx pin is sampled high (clock arbitration),
the Baud Rate Generator counts for TBRG; the SCLx pin
is then pulled low. Following this, the ACKEN bit is auto-
matically cleared, the Baud Rate Generator is turned off
and the MSSP module then goes into an inactive state
(Figure 19-25).
a
receive/transmit, the SCLx line is held low after the
falling edge of the ninth clock. When the PEN bit is set,
the master will assert the SDAx line low. When the
SDAx line is sampled low, the Baud Rate Generator is
reloaded and counts down to 0. When the Baud Rate
Generator times out, the SCLx pin will be brought high
and one TBRG (Baud Rate Generator rollover count)
later, the SDAx pin will be deasserted. When the SDAx
pin is sampled high while SCLx is high, the P bit
(SSPxSTAT<4>) is set. A TBRG later, the PEN bit is
cleared and the SSPxIF bit is set (Figure 19-26).
19.4.13.1 WCOL Status Flag
If the user writes the SSPxBUF when a Stop sequence
is in progress, then the WCOL bit is set and the
contents of the buffer are unchanged (the write doesn’t
occur).
19.4.12.1 WCOL Status Flag
If the user writes the SSPxBUF when an Acknowledge
sequence is in progress, then WCOL is set and the
contents of the buffer are unchanged (the write doesn’t
occur).
FIGURE 19-25:
ACKNOWLEDGE SEQUENCE WAVEFORM
Acknowledge sequence starts here,
write to SSPxCON2,
ACKEN automatically cleared
ACKEN = 1, ACKDT = 0
TBRG
ACK
TBRG
SDAx
SCLx
D0
8
9
SSPxIF
Cleared in
software
SSPxIF set at the end
of Acknowledge sequence
SSPxIF set at
the end of receive
Cleared in
software
Note: TBRG = one Baud Rate Generator period.
DS39778D-page 262
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FIGURE 19-26:
STOP CONDITION RECEIVE OR TRANSMIT MODE
SCLx = 1for TBRG, followed by SDAx = 1for TBRG
after SDAx sampled high. P bit (SSPxSTAT<4>) is set
Write to SSPxCON2,
set PEN
PEN bit (SSPxCON2<2>) is cleared by
hardware and the SSPxIF bit is set
Falling edge of
9th clock
TBRG
SCLx
SDAx
ACK
P
TBRG
TBRG
TBRG
SCLx brought high after TBRG
SDAx asserted low before rising edge of clock
to set up Stop condition
Note: TBRG = one Baud Rate Generator period.
19.4.14 SLEEP OPERATION
19.4.17 MULTI -MASTER COMMUNICATION,
BUS COLLISION AND BUS
While in Sleep mode, the I2C module can receive
addresses or data and when an address match or
complete byte transfer occurs, wake the processor
from Sleep (if the MSSP interrupt is enabled).
ARBITRATION
Multi-Master mode support is achieved by bus arbitra-
tion. When the master outputs address/data bits onto
the SDAx pin, arbitration takes place when the master
outputs a ‘1’ on SDAx, by letting SDAx float high, and
another master asserts a ‘0’. When the SCLx pin floats
high, data should be stable. If the expected data on
SDAx is a ‘1’ and the data sampled on the SDAx
pin = 0, then a bus collision has taken place. The
master will set the Bus Collision Interrupt Flag, BCLxIF
and reset the I2C port to its Idle state (Figure 19-27).
19.4.15 EFFECTS OF A RESET
A Reset disables the MSSP module and terminates the
current transfer.
19.4.16 MULTI-MASTER MODE
In Multi-Master mode, the interrupt generation on the
detection of the Start and Stop conditions allows the
determination of when the bus is free. The Stop (P) and
Start (S) bits are cleared from a Reset or when the
MSSP module is disabled. Control of the I2C bus may
be taken when the P bit (SSPxSTAT<4>) is set, or the
bus is Idle, with both the S and P bits clear. When the
bus is busy, enabling the MSSP interrupt will generate
the interrupt when the Stop condition occurs.
If a transmit was in progress when the bus collision
occurred, the transmission is halted, the BF flag is
cleared, the SDAx and SCLx lines are deasserted and
the SSPxBUF can be written to. When the user services
the bus collision Interrupt Service Routine and if the I2C
bus is free, the user can resume communication by
asserting a Start condition.
In multi-master operation, the SDAx line must be
monitored for arbitration to see if the signal level is the
expected output level. This check is performed in
hardware with the result placed in the BCLxIF bit.
If a Start, Repeated Start, Stop or Acknowledge condition
was in progress when the bus collision occurred, the con-
dition is aborted, the SDAx and SCLx lines are
deasserted and the respective control bits in the
SSPxCON2 register are cleared. When the user services
the bus collision Interrupt Service Routine, and if the I2C
bus is free, the user can resume communication by
asserting a Start condition.
The states where arbitration can be lost are:
• Address Transfer
• Data Transfer
• A Start Condition
The master will continue to monitor the SDAx and SCLx
pins. If a Stop condition occurs, the SSPxIF bit will be set.
• A Repeated Start Condition
• An Acknowledge Condition
A write to the SSPxBUF will start the transmission of
data at the first data bit regardless of where the
transmitter left off when the bus collision occurred.
In Multi-Master mode, the interrupt generation on the
detection of Start and Stop conditions allows the determi-
nation of when the bus is free. Control of the I2C bus can
be taken when the P bit is set in the SSPxSTAT register,
or the bus is Idle and the S and P bits are cleared.
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FIGURE 19-27:
BUS COLLISION TIMING FOR TRANSMIT AND ACKNOWLEDGE
Sample SDAx. While SCLx is high,
data doesn’t match what is driven
by the master;
Data changes
while SCLx = 0
SDAx line pulled low
by another source
bus collision has occurred.
SDAx released
by master
SDAx
SCLx
Set bus collision
interrupt (BCLxIF)
BCLxIF
DS39778D-page 264
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If the SDAx pin is sampled low during this count, the
BRG is reset and the SDAx line is asserted early
(Figure 19-30). If, however, a ‘1’ is sampled on the
SDAx pin, the SDAx pin is asserted low at the end of
the BRG count. The Baud Rate Generator is then
reloaded and counts down to 0. If the SCLx pin is
sampled as ‘0’ during this time, a bus collision does not
occur. At the end of the BRG count, the SCLx pin is
asserted low.
19.4.17.1 Bus Collision During a Start
Condition
During a Start condition, a bus collision occurs if:
a) SDAx or SCLx is sampled low at the beginning
of the Start condition (Figure 19-28).
b) SCLx is sampled low before SDAx is asserted
low (Figure 19-29).
During a Start condition, both the SDAx and the SCLx
pins are monitored.
Note:
The reason that bus collision is not a factor
during a Start condition is that no two bus
masters can assert a Start condition at the
exact same time. Therefore, one master
will always assert SDAx before the other.
This condition does not cause a bus colli-
sion because the two masters must be
allowed to arbitrate the first address
following the Start condition. If the address
is the same, arbitration must be allowed to
continue into the data portion, Repeated
Start or Stop conditions.
If the SDAx pin is already low, or the SCLx pin is
already low, then all of the following occur:
• the Start condition is aborted,
• the BCLxIF flag is set and
• the MSSP module is reset to its inactive state
(Figure 19-28)
The Start condition begins with the SDAx and SCLx
pins deasserted. When the SDAx pin is sampled high,
the Baud Rate Generator is loaded from
SSPxADD<6:0> and counts down to 0. If the SCLx pin
is sampled low while SDAx is high, a bus collision
occurs because it is assumed that another master is
attempting to drive a data ‘1’ during the Start condition.
FIGURE 19-28:
BUS COLLISION DURING START CONDITION (SDAx ONLY)
SDAx goes low before the SEN bit is set.
Set BCLxIF,
S bit and SSPxIF set because
SDAx = 0, SCLx = 1.
SDAx
SCLx
SEN
Set SEN, enable Start
condition if SDAx = 1, SCLx = 1
SEN cleared automatically because of bus collision.
MSSP module reset into Idle state.
SDAx sampled low before
Start condition. Set BCLxIF.
S bit and SSPxIF set because
SDAx = 0, SCLx = 1.
BCLxIF
SSPxIF and BCLxIF are
cleared in software
S
SSPxIF
SSPxIF and BCLxIF are
cleared in software
© 2009 Microchip Technology Inc.
DS39778D-page 265
PIC18F87J11 FAMILY
FIGURE 19-29:
BUS COLLISION DURING START CONDITION (SCLx = 0)
SDAx = 0, SCLx = 1
TBRG
TBRG
SDAx
Set SEN, enable Start
sequence if SDAx = 1, SCLx = 1
SCLx
SEN
SCLx = 0before SDAx = 0,
bus collision occurs. Set BCLxIF.
SCLx = 0before BRG time-out,
bus collision occurs. Set BCLxIF.
BCLxIF
Interrupt cleared
in software
S
‘0’
‘0’
‘0’
‘0’
SSPxIF
FIGURE 19-30:
BRG RESET DUE TO SDAx ARBITRATION DURING START CONDITION
SDAx = 0, SCLx = 1
Set S
Set SSPxIF
Less than TBRG
TBRG
SDAx pulled low by other master.
Reset BRG and assert SDAx.
SDAx
SCLx
S
SCLx pulled low after BRG
time-out
SEN
Set SEN, enable Start
sequence if SDAx = 1, SCLx = 1
‘0’
BCLxIF
S
SSPxIF
Interrupts cleared
in software
SDAx = 0, SCLx = 1,
set SSPxIF
DS39778D-page 266
© 2009 Microchip Technology Inc.
PIC18F87J11 FAMILY
If SDAx is low, a bus collision has occurred (i.e., another
19.4.17.2 Bus Collision During a Repeated
Start Condition
master is attempting to transmit
a
data ‘0’,
Figure 19-31). If SDAx is sampled high, the BRG is
reloaded and begins counting. If SDAx goes from
high-to-low before the BRG times out, no bus collision
occurs because no two masters can assert SDAx at
exactly the same time.
During a Repeated Start condition, a bus collision
occurs if:
a) A low level is sampled on SDAx when SCLx
goes from a low level to a high level.
b) SCLx goes low before SDAx is asserted low,
indicating that another master is attempting to
transmit a data ‘1’.
If SCLx goes from high-to-low before the BRG times
out and SDAx has not already been asserted, a bus
collision occurs. In this case, another master is
attempting to transmit a data ‘1’ during the Repeated
Start condition (see Figure 19-32).
When the user deasserts SDAx and the pin is allowed
to float high, the BRG is loaded with SSPxADD<6:0>
and counts down to 0. The SCLx pin is then deasserted
and when sampled high, the SDAx pin is sampled.
If, at the end of the BRG time-out, both SCLx and SDAx
are still high, the SDAx pin is driven low and the BRG is
reloaded and begins counting. At the end of the count,
regardless of the status of the SCLx pin, the SCLx pin is
driven low and the Repeated Start condition is complete.
FIGURE 19-31:
BUS COLLISION DURING A REPEATED START CONDITION (CASE 1)
SDAx
SCLx
Sample SDAx when SCLx goes high.
If SDAx = 0, set BCLxIF and release SDAx and SCLx.
RSEN
BCLxIF
Cleared in software
‘0’
S
‘0’
SSPxIF
© 2009 Microchip Technology Inc.
DS39778D-page 267
PIC18F87J11 FAMILY
FIGURE 19-32:
BUS COLLISION DURING REPEATED START CONDITION (CASE 2)
TBRG
TBRG
SDAx
SCLx
SCLx goes low before SDAx,
set BCLxIF. Release SDAx and SCLx.
BCLxIF
RSEN
Interrupt cleared
in software
‘0’
S
SSPxIF
DS39778D-page 268
© 2009 Microchip Technology Inc.
PIC18F87J11 FAMILY
The Stop condition begins with SDAx asserted low.
When SDAx is sampled low, the SCLx pin is allowed to
float. When the pin is sampled high (clock arbitration),
the Baud Rate Generator is loaded with
SSPxADD<6:0> and counts down to 0. After the BRG
times out, SDAx is sampled. If SDAx is sampled low, a
bus collision has occurred. This is due to another
master attempting to drive a data ‘0’ (Figure 19-33). If
the SCLx pin is sampled low before SDAx is allowed to
float high, a bus collision occurs. This is another case
of another master attempting to drive a data ‘0’
(Figure 19-34).
19.4.17.3 Bus Collision During a Stop
Condition
Bus collision occurs during a Stop condition if:
a) After the SDAx pin has been deasserted and
allowed to float high, SDAx is sampled low after
the BRG has timed out.
b) After the SCLx pin is deasserted, SCLx is
sampled low before SDAx goes high.
FIGURE 19-33:
BUS COLLISION DURING A STOP CONDITION (CASE 1)
SDAx sampled
low after TBRG,
set BCLxIF
TBRG
TBRG
TBRG
SDAx
SDAx asserted low
SCLx
PEN
BCLxIF
P
‘0’
‘0’
SSPxIF
FIGURE 19-34:
BUS COLLISION DURING A STOP CONDITION (CASE 2)
TBRG
TBRG
TBRG
SDAx
SCLx goes low before SDAx goes high,
set BCLxIF
Assert SDAx
SCLx
PEN
BCLxIF
P
‘0’
‘0’
SSPxIF
© 2009 Microchip Technology Inc.
DS39778D-page 269
PIC18F87J11 FAMILY
TABLE 19-4: REGISTERS ASSOCIATED WITH I2C™ OPERATION
Reset
Values
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
on Page:
INTCON
PIR1
GIE/GIEH PEIE/GIEL TMR0IE
INT0IE
TX1IF
TX1IE
TX1IP
—
RBIE
TMR0IF
CCP1IF
CCP1IE
CCP1IP
LVDIF
INT0IF
RBIF
57
60
60
60
60
60
60
60
60
60
60
60
58
58
PMPIF
PMPIE
ADIF
ADIE
RC1IF
RC1IE
RC1IP
CM1IF
CM1IE
CM1IP
RC2IF
RC2IE
RC2IP
TRISC5
TRISD5
SSP1IF
SSP1IE
SSP1IP
BCL1IF
BCL1IE
BCL1IP
TMR4IF
TMR4IE
TMR4IP
TRISC3
TRISD3
TMR2IF TMR1IF
TMR2IE TMR1IE
TMR2IP TMR1IP
TMR3IF CCP2IF
TMR3IE CCP2IE
TMR3IP CCP2IP
CCP4IF CCP3IF
CCP4IE CCP3IE
CCP4IP CCP3IP
TRISC1 TRISC0
TRISD1 TRISD0
PIE1
IPR1
PMPIP
ADIP
PIR2
OSCFIF
OSCFIE
OSCFIP
SSP2IF
SSP2IE
SSP2IP
TRISC7
TRISD7
CM2IF
CM2IE
CM2IP
BCL2IF
BCL2IE
BCL2IP
TRISC6
TRISD6
PIE2
—
LVDIE
IPR2
—
LVDIP
PIR3
TX2IF
TX2IE
TX2IP
TRISC4
TRISD4
CCP5IF
CCP5IE
CCP5IP
TRISC2
TRISD2
PIE3
IPR3
TRISC
TRISD
SSP1BUF MSSP1 Receive Buffer/Transmit Register
SSP1ADD MSSP1 Address Register (I2C™ Slave mode),
MSSP1 Baud Rate Reload Register (I2C Master mode)
SSP1MSK(1) MSK7
MSK6
MSK5
MSK4
CKP
MSK3
SSPM3
RCEN
MSK2
SSPM2
PEN
MSK1
SSPM1
RSEN
MSK0
SSPM0
SEN
58
58
58
SSP1CON1
SSP1CON2
WCOL
GCEN
GCEN
SMP
SSPOV
SSPEN
ACKSTAT ACKDT
ACKSTAT ADMSK5(2) ADMSK4(2) ADMSK3(2) ADMSK2(2) ADMSK1(2)
ACKEN
SEN
SSP1STAT
CKE
D/A
P
S
R/W
UA
BF
58
61
61
SSP2BUF MSSP2 Receive Buffer/Transmit Register
SSP2ADD MSSP2 Address Register (I2C Slave mode),
MSSP2 Baud Rate Reload Register (I2C Master mode)
SSP2MSK(1) MSK7
MSK6
MSK5
MSK4
CKP
MSK3
SSPM3
RCEN
MSK2
SSPM2
PEN
MSK1
SSPM1
RSEN
MSK0
SSPM0
SEN
61
61
61
SSP2CON1
SSP2CON2
WCOL
GCEN
GCEN
SMP
SSPOV
SSPEN
ACKSTAT ACKDT
ACKSTAT ADMSK5(2) ADMSK4(2) ADMSK3(2) ADMSK2(2) ADMSK1(2)
ACKEN
SEN
SSP2STAT
CKE D/A R/W UA
P
S
BF
61
Legend: —= unimplemented, read as ‘0’. Shaded cells are not used by the MSSP module in I2C™ mode.
Note 1: SSPxMSK shares the same address in SFR space as SSPxADD, but is only accessible in certain I2C™
Slave operating modes in 7-bit Masking mode. See Section 19.4.3.4 “7-Bit Address Masking Mode” for
more details.
2: Alternate bit definitions for use in I2C Slave mode operations only.
DS39778D-page 270
© 2009 Microchip Technology Inc.
PIC18F87J11 FAMILY
The pins of EUSART1 and EUSART2 are multiplexed
with the functions of PORTC (RC6/TX1/CK1 and
RC7/RX1/DT1) and PORTG (RG1/TX2/CK2 and
RG2/RX2/DT2), respectively. In order to configure
these pins as an EUSART:
20.0 ENHANCED UNIVERSAL
SYNCHRONOUS
ASYNCHRONOUS RECEIVER
TRANSMITTER (EUSART)
• For EUSART1:
The Enhanced Universal Synchronous Asynchronous
Receiver Transmitter (EUSART) module is one of two
serial I/O modules. (Generically, the EUSART is also
known as a Serial Communications Interface or SCI.)
The EUSART can be configured as a full-duplex
asynchronous system that can communicate with
peripheral devices, such as CRT terminals and
personal computers. It can also be configured as a
half-duplex synchronous system that can communicate
with peripheral devices, such as A/D or D/A integrated
circuits, serial EEPROMs, etc.
- bit SPEN (RCSTA1<7>) must be set (= 1)
- bit TRISC<7> must be set (= 1)
- bit TRISC<6> must be cleared (= 0) for
Asynchronous and Synchronous Master
modes
- bit TRISC<6> must be set (= 1) for
Synchronous Slave mode
• For EUSART2:
- bit SPEN (RCSTA2<7>) must be set (= 1)
- bit TRISG<2> must be set (= 1)
The Enhanced USART module implements additional
features, including automatic baud rate detection and
calibration, automatic wake-up on Sync Break recep-
tion and 12-bit Break character transmit. These make it
ideally suited for use in Local Interconnect Network bus
(LIN bus) systems.
- bit TRISG<1> must be cleared (= 0) for
Asynchronous and Synchronous Master
modes
- bit TRISC<6> must be set (= 1) for
Synchronous Slave mode
All members of the PIC18F87J11 family are equipped
with two independent EUSART modules, referred to as
EUSART1 and EUSART2. They can be configured in
the following modes:
Note:
The EUSART control will automatically
reconfigure the pin from input to output as
needed.
The operation of each Enhanced USART module is
controlled through three registers:
• Asynchronous (full duplex) with:
- Auto-wake-up on character reception
- Auto-baud calibration
• Transmit Status and Control (TXSTAx)
• Receive Status and Control (RCSTAx)
• Baud Rate Control (BAUDCONx)
- 12-bit Break character transmission
• Synchronous – Master (half duplex) with
selectable clock polarity
These are detailed on the following pages in
Register 20-1, Register 20-2 and Register 20-3,
respectively.
• Synchronous – Slave (half duplex) with selectable
clock polarity
Note:
Throughout this section, references to
register and bit names that may be associ-
ated with a specific EUSART module are
referred to generically by the use of ‘x’ in
place of the specific module number.
Thus, “RCSTAx” might refer to the
Receive Status register for either
EUSART1 or EUSART2.
© 2009 Microchip Technology Inc.
DS39778D-page 271
PIC18F87J11 FAMILY
REGISTER 20-1: TXSTAx: TRANSMIT STATUS AND CONTROL REGISTER
R/W-0
CSRC
R/W-0
TX9
R/W-0
TXEN(1)
R/W-0
SYNC
R/W-0
R/W-0
BRGH
R-1
R/W-0
TX9D
SENDB
TRMT
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7
CSRC: Clock Source Select bit
Asynchronous mode:
Don’t care.
Synchronous mode:
1= Master mode (clock generated internally from BRG)
0= Slave mode (clock from external source)
bit 6
bit 5
TX9: 9-Bit Transmit Enable bit
1= Selects 9-bit transmission
0= Selects 8-bit transmission
TXEN: Transmit Enable bit(1)
1= Transmit enabled
0= Transmit disabled
bit 4
bit 3
SYNC: EUSART Mode Select bit
1= Synchronous mode
0= Asynchronous mode
SENDB: Send Break Character bit
Asynchronous mode:
1= Send Sync Break on next transmission (cleared by hardware upon completion)
0= Sync Break transmission completed
Synchronous mode:
Don’t care.
bit 2
BRGH: High Baud Rate Select bit
Asynchronous mode:
1= High speed
0= Low speed
Synchronous mode:
Unused in this mode.
bit 1
bit 0
TRMT: Transmit Shift Register Status bit
1= TSR empty
0= TSR full
TX9D: 9th bit of Transmit Data
Can be address/data bit or a parity bit.
Note 1: SREN/CREN overrides TXEN in Sync mode.
DS39778D-page 272
© 2009 Microchip Technology Inc.
PIC18F87J11 FAMILY
REGISTER 20-2: RCSTAx: RECEIVE STATUS AND CONTROL REGISTER
R/W-0
SPEN
R/W-0
RX9
R/W-0
SREN
R/W-0
CREN
R/W-0
R-0
R-0
R-x
ADDEN
FERR
OERR
RX9D
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7
bit 6
bit 5
SPEN: Serial Port Enable bit
1= Serial port enabled (configures RXx/DTx and TXx/CKx pins as serial port pins)
0= Serial port disabled (held in Reset)
RX9: 9-Bit Receive Enable bit
1= Selects 9-bit reception
0= Selects 8-bit reception
SREN: Single Receive Enable bit
Asynchronous mode:
Don’t care.
Synchronous mode – Master:
1= Enables single receive
0= Disables single receive
This bit is cleared after reception is complete.
Synchronous mode – Slave:
Don’t care.
bit 4
CREN: Continuous Receive Enable bit
Asynchronous mode:
1= Enables receiver
0= Disables receiver
Synchronous mode:
1= Enables continuous receive until enable bit CREN is cleared (CREN overrides SREN)
0= Disables continuous receive
bit 3
ADDEN: Address Detect Enable bit
Asynchronous mode 9-Bit (RX9 = 1):
1= Enables address detection, enables interrupt and loads the receive buffer when RSR<8> is set
0= Disables address detection, all bytes are received and ninth bit can be used as parity bit
Asynchronous mode 9-Bit (RX9 = 0):
Don’t care.
bit 2
bit 1
bit 0
FERR: Framing Error bit
1= Framing error (can be updated by reading RCREGx register and receiving next valid byte)
0= No framing error
OERR: Overrun Error bit
1= Overrun error (can be cleared by clearing bit CREN)
0= No overrun error
RX9D: 9th bit of Received Data
This can be address/data bit or a parity bit and must be calculated by user firmware.
© 2009 Microchip Technology Inc.
DS39778D-page 273
PIC18F87J11 FAMILY
REGISTER 20-3: BAUDCONx: BAUD RATE CONTROL REGISTER
R/W-0
R-1
R/W-0
R/W-0
R/W-0
U-0
—
R/W-0
WUE
R/W-0
ABDOVF
RCIDL
RXDTP
TXCKP
BRG16
ABDEN
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7
ABDOVF: Auto-Baud Acquisition Rollover Status bit
1= A BRG rollover has occurred during Auto-Baud Rate Detect mode
(must be cleared in software)
0= No BRG rollover has occurred
bit 6
bit 5
RCIDL: Receive Operation Idle Status bit
1= Receive operation is Idle
0= Receive operation is active
RXDTP: Data/Receive Polarity Select bit
Asynchronous mode:
1= Receive data (RXx) is inverted (active-low)
0= Receive data (RXx) is not inverted (active-high)
Synchronous mode:
1= Data (DTx) is inverted (active-low)
0= Data (DTx) is not inverted (active-high)
bit 4
TXCKP: Synchronous Clock Polarity Select bit
Asynchronous mode:
1= Idle state for transmit (TXx) is a low level
0= Idle state for transmit (TXx) is a high level
Synchronous mode:
1= Idle state for clock (CKx) is a high level
0= Idle state for clock (CKx) is a low level
bit 3
BRG16: 16-Bit Baud Rate Register Enable bit
1= 16-bit Baud Rate Generator – SPBRGHx and SPBRGx
0= 8-bit Baud Rate Generator – SPBRGx only (Compatible mode), SPBRGHx value ignored
bit 2
bit 1
Unimplemented: Read as ‘0’
WUE: Wake-up Enable bit
Asynchronous mode:
1= EUSART will continue to sample the RXx pin – interrupt generated on falling edge; bit cleared in
hardware on following rising edge
0= RXx pin not monitored or rising edge detected
Synchronous mode:
Unused in this mode.
bit 0
ABDEN: Auto-Baud Detect Enable bit
Asynchronous mode:
1= Enable baud rate measurement on the next character. Requires reception of a Sync field (55h);
cleared in hardware upon completion.
0= Baud rate measurement disabled or completed
Synchronous mode:
Unused in this mode.
DS39778D-page 274
© 2009 Microchip Technology Inc.
PIC18F87J11 FAMILY
the high baud rate (BRGH = 1) or the 16-bit BRG to
reduce the baud rate error, or achieve a slow baud rate
for a fast oscillator frequency.
20.1
Baud Rate Generator (BRG)
The BRG is a dedicated, 8-bit or 16-bit generator that
supports both the Asynchronous and Synchronous
modes of the EUSART. By default, the BRG operates
in 8-bit mode; setting the BRG16 bit (BAUDCONx<3>)
selects 16-bit mode.
Writing a new value to the SPBRGHx:SPBRGx regis-
ters causes the BRG timer to be reset (or cleared). This
ensures the BRG does not wait for a timer overflow
before outputting the new baud rate.
The SPBRGHx:SPBRGx register pair controls the period
of a free-running timer. In Asynchronous mode, bits
BRGH (TXSTAx<2>) and BRG16 (BAUDCONx<3>) also
control the baud rate. In Synchronous mode, BRGH is
ignored. Table 20-1 shows the formula for computation of
the baud rate for different EUSART modes which only
apply in Master mode (internally generated clock).
20.1.1
OPERATION IN POWER-MANAGED
MODES
The device clock is used to generate the desired baud
rate. When one of the power-managed modes is
entered, the new clock source may be operating at a
different frequency. This may require an adjustment to
the value in the SPBRGx register pair.
Given the desired baud rate and FOSC, the nearest
integer value for the SPBRGHx:SPBRGx registers can
be calculated using the formulas in Table 20-1. From this,
the error in baud rate can be determined. An example
calculation is shown in Example 20-1. Typical baud rates
and error values for the various Asynchronous modes
are shown in Table 20-2. It may be advantageous to use
20.1.2
SAMPLING
The data on the RXx pin (either RC7/RX1/DT1 or
RG2/RX2/DT2) is sampled three times by a majority
detect circuit to determine if a high or a low level is
present at the RXx pin.
TABLE 20-1: BAUD RATE FORMULAS
Configuration Bits
BRG/EUSART Mode
Baud Rate Formula
SYNC
BRG16
BRGH
0
0
0
0
1
1
0
0
1
1
0
1
0
1
0
1
x
x
8-bit/Asynchronous
8-bit/Asynchronous
16-bit/Asynchronous
16-bit/Asynchronous
8-bit/Synchronous
16-bit/Synchronous
FOSC/[64 (n + 1)]
FOSC/[16 (n + 1)]
FOSC/[4 (n + 1)]
Legend: x= Don’t care, n = value of SPBRGHx:SPBRGx register pair
© 2009 Microchip Technology Inc.
DS39778D-page 275
PIC18F87J11 FAMILY
EXAMPLE 20-1:
CALCULATING BAUD RATE ERROR
For a device with FOSC of 16 MHz, desired baud rate of 9600, Asynchronous mode, and 8-bit BRG:
Desired Baud Rate = FOSC/(64 ([SPBRGHx:SPBRGx] + 1))
Solving for SPBRGHx:SPBRGx:
X
=
=
=
=
=
=
=
((FOSC/Desired Baud Rate)/64) – 1
((16000000/9600)/64) – 1
[25.042] = 25
16000000/(64 (25 + 1))
9615
Calculated Baud Rate
Error
(Calculated Baud Rate – Desired Baud Rate)/Desired Baud Rate
(9615 – 9600)/9600 = 0.16%
TABLE 20-2: REGISTERS ASSOCIATED WITH BAUD RATE GENERATOR
Reset Values
on Page:
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
TXSTAx
RCSTAx
CSRC
SPEN
TX9
RX9
TXEN
SREN
SYNC
CREN
TXCKP
SENDB
ADDEN
BRG16
BRGH
FERR
—
TRMT
OERR
WUE
TX9D
RX9D
59
59
61
61
61
BAUDCONx ABDOVF RCIDL
RXDTP
ABDEN
SPBRGHx EUSARTx Baud Rate Generator Register High Byte
SPBRGx EUSARTx Baud Rate Generator Register Low Byte
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the BRG.
DS39778D-page 276
© 2009 Microchip Technology Inc.
PIC18F87J11 FAMILY
TABLE 20-3: BAUD RATES FOR ASYNCHRONOUS MODES
SYNC = 0, BRGH = 0, BRG16 = 0
BAUD
RATE
(K)
FOSC = 40.000 MHz
FOSC = 20.000 MHz FOSC = 10.000 MHz
FOSC = 8.000 MHz
Actual
Rate
(K)
SPBRG Actual
value
SPBRG Actual
SPBRG Actual
value
(decimal)
SPBRG
value
(decimal)
%
%
Error
%
Error
%
Error
Rate
(K)
value
Rate
(K)
Rate
(K)
Error
(decimal)
(decimal)
0.3
1.2
—
—
—
—
—
—
—
255
129
31
15
4
—
—
—
129
64
15
7
—
1.201
2.403
9.615
—
—
-0.16
-0.16
-0.16
—
—
103
51
12
—
—
—
1.221
1.73
0.16
1.73
1.73
8.51
-9.58
1.202
2.404
9.766
19.531
52.083
78.125
0.16
0.16
1.73
1.73
-9.58
-32.18
2.4
2.441
9.615
19.531
56.818
125.000
1.73
0.16
1.73
-1.36
8.51
255
64
31
10
4
2.404
9.6
9.766
19.2
57.6
115.2
19.531
62.500
104.167
2
—
—
—
2
1
—
—
—
SYNC = 0, BRGH = 0, BRG16 = 0
BAUD
RATE
(K)
FOSC = 4.000 MHz
FOSC = 2.000 MHz
FOSC = 1.000 MHz
Actual
Rate
(K)
SPBRG Actual
value
SPBRG Actual
value
(decimal)
SPBRG
value
(decimal)
%
%
Error
%
Error
Rate
(K)
Rate
(K)
Error
(decimal)
0.3
1.2
0.300
1.202
0.16
0.16
207
51
25
6
0.300
1.201
2.403
—
-0.16
-0.16
-0.16
—
103
25
12
—
0.300
1.201
—
-0.16
-0.16
—
51
12
—
—
—
—
—
2.4
2.404
0.16
9.6
8.929
-6.99
8.51
—
—
19.2
57.6
115.2
20.833
62.500
62.500
2
—
—
—
—
—
8.51
0
—
—
—
—
—
-45.75
0
—
—
—
—
—
SYNC = 0, BRGH = 1, BRG16 = 0
BAUD
RATE
(K)
FOSC = 40.000 MHz
FOSC = 20.000 MHz
FOSC = 10.000 MHz
FOSC = 8.000 MHz
Actual
Rate
(K)
SPBRG Actual
value
(decimal)
SPBRG Actual
value
(decimal)
SPBRG Actual
value
(decimal)
SPBRG
value
%
Error
%
Error
%
Error
%
Error
Rate
(K)
Rate
(K)
Rate
(K)
(decimal)
0.3
1.2
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
2.4
—
—
—
—
—
—
2.441
9.615
19.531
56.818
125.000
1.73
0.16
1.73
-1.36
8.51
255
64
31
10
4
2.403
9.615
19.230
55.555
—
-0.16
-0.16
-0.16
3.55
—
207
51
25
8
9.6
9.766
19.231
58.140
113.636
1.73
0.16
0.94
-1.36
255
129
42
9.615
19.231
56.818
113.636
0.16
0.16
-1.36
-1.36
129
64
21
10
19.2
57.6
115.2
21
—
SYNC = 0, BRGH = 1, BRG16 = 0
BAUD
RATE
(K)
FOSC = 4.000 MHz
FOSC = 2.000 MHz
FOSC = 1.000 MHz
Actual
Rate
(K)
SPBRG Actual
value
SPBRG Actual
value
(decimal)
SPBRG
value
(decimal)
%
%
Error
%
Error
Rate
(K)
Rate
(K)
Error
(decimal)
0.3
1.2
—
—
—
207
103
25
12
3
—
1.201
2.403
9.615
—
—
-0.16
-0.16
-0.16
—
—
103
51
12
—
0.300
1.201
2.403
—
-0.16
-0.16
-0.16
—
207
51
25
—
1.202
0.16
0.16
0.16
0.16
8.51
8.51
2.4
2.404
9.6
9.615
19.2
57.6
115.2
19.231
62.500
125.000
—
—
—
—
—
—
—
—
—
1
—
—
—
—
—
—
© 2009 Microchip Technology Inc.
DS39778D-page 277
PIC18F87J11 FAMILY
TABLE 20-3: BAUD RATES FOR ASYNCHRONOUS MODES (CONTINUED)
SYNC = 0, BRGH = 0, BRG16 = 1
BAUD
RATE
(K)
FOSC = 40.000 MHz
FOSC = 20.000 MHz
FOSC = 10.000 MHz
FOSC = 8.000 MHz
Actual
Rate
(K)
SPBRG Actual
value
SPBRG Actual
value
(decimal)
SPBRG Actual
value
(decimal)
SPBRG
value
(decimal)
%
%
Error
%
Error
%
Error
Rate
(K)
Rate
(K)
Rate
(K)
Error
(decimal)
0.3
1.2
0.300
1.200
0.00
0.02
0.06
0.16
0.16
0.94
-1.36
8332
2082
1040
259
129
42
0.300
1.200
0.02
-0.03
-0.03
0.16
4165
1041
520
129
64
0.300
1.200
0.02
-0.03
0.16
0.16
1.73
-1.36
8.51
2082
520
259
64
0.300
1.201
2.403
9.615
19.230
55.555
—
-0.04
-0.16
-0.16
-0.16
-0.16
3.55
—
1665
415
207
51
2.4
2.402
2.399
2.404
9.6
9.615
9.615
9.615
19.2
57.6
115.2
19.231
58.140
113.636
19.231
56.818
113.636
0.16
19.531
56.818
125.000
31
25
-1.36
-1.36
21
10
8
21
10
4
—
SYNC = 0, BRGH = 0, BRG16 = 1
BAUD
RATE
(K)
FOSC = 4.000 MHz
FOSC = 2.000 MHz
FOSC = 1.000 MHz
Actual
Rate
(K)
SPBRG Actual
value
SPBRG Actual
value
(decimal)
SPBRG
value
(decimal)
%
%
Error
%
Error
Rate
(K)
Rate
(K)
Error
(decimal)
0.3
1.2
0.300
1.202
0.04
0.16
0.16
0.16
0.16
8.51
8.51
832
207
103
25
12
3
0.300
1.201
2.403
9.615
—
-0.16
-0.16
-0.16
-0.16
—
415
103
51
12
—
0.300
1.201
2.403
—
-0.16
-0.16
-0.16
—
207
51
25
—
2.4
2.404
9.6
9.615
19.2
57.6
115.2
19.231
62.500
125.000
—
—
—
—
—
—
—
—
—
1
—
—
—
—
—
—
SYNC = 0, BRGH = 1, BRG16 = 1or SYNC = 1, BRG16 = 1
FOSC = 20.000 MHz FOSC = 10.000 MHz
BAUD
RATE
(K)
FOSC = 40.000 MHz
FOSC = 8.000 MHz
Actual
Rate
(K)
SPBRG Actual
SPBRG Actual
SPBRG Actual
value
SPBRG
value
(decimal)
%
Error
%
%
%
Error
value
(decimal)
Rate
(K)
value
Rate
(K)
Rate
(K)
Error
Error
(decimal)
(decimal)
0.3
1.2
0.300
1.200
0.00
0.00
0.02
0.06
-0.03
0.35
-0.22
33332
8332
4165
1040
520
0.300
1.200
0.00
0.02
0.02
-0.03
0.16
-0.22
0.94
16665
4165
2082
520
259
86
0.300
1.200
0.00
0.02
0.06
0.16
0.16
0.94
-1.36
8332
2082
1040
259
129
42
0.300
1.200
-0.01
-0.04
-0.04
-0.16
-0.16
0.79
6665
1665
832
207
103
34
2.4
2.400
2.400
2.402
2.400
9.6
9.606
9.596
9.615
9.615
19.2
57.6
115.2
19.193
57.803
114.943
19.231
57.471
116.279
19.231
58.140
113.636
19.230
57.142
117.647
172
86
42
21
-2.12
16
SYNC = 0, BRGH = 1, BRG16 = 1or SYNC = 1, BRG16 = 1
FOSC = 4.000 MHz FOSC = 2.000 MHz FOSC = 1.000 MHz
BAUD
RATE
(K)
Actual
Rate
(K)
SPBRG Actual
SPBRG Actual
SPBRG
value
(decimal)
%
Error
%
Error
%
Error
value
Rate
(K)
value
Rate
(K)
(decimal)
(decimal)
0.3
1.2
0.300
1.200
0.01
0.04
0.16
0.16
0.16
2.12
-3.55
3332
832
415
103
51
0.300
1.201
2.403
9.615
19.230
55.555
—
-0.04
-0.16
-0.16
-0.16
-0.16
3.55
—
1665
415
207
51
0.300
1.201
2.403
9.615
19.230
—
-0.04
-0.16
-0.16
-0.16
-0.16
—
832
207
103
25
2.4
2.404
9.6
9.615
19.2
57.6
115.2
19.231
58.824
111.111
25
12
16
8
—
8
—
—
—
—
DS39778D-page 278
© 2009 Microchip Technology Inc.
PIC18F87J11 FAMILY
20.1.3
AUTO-BAUD RATE DETECT
Note 1: If the WUE bit is set with the ABDEN bit,
Auto-Baud Rate Detection will occur on
the byte following the Break character.
The Enhanced USART module supports the automatic
detection and calibration of baud rate. This feature is
active only in Asynchronous mode and while the WUE
bit is clear.
2: It is up to the user to determine that the
incoming character baud rate is within the
range of the selected BRG clock source.
Some combinations of oscillator frequency
and EUSART baud rates are not possible
due to bit error rates. Overall system tim-
ing and communication baud rates must
be taken into consideration when using the
Auto-Baud Rate Detection feature.
The automatic baud rate measurement sequence
(Figure 20-1) begins whenever a Start bit is received
and the ABDEN bit is set. The calculation is
self-averaging.
In the Auto-Baud Rate Detect (ABD) mode, the clock to
the BRG is reversed. Rather than the BRG clocking the
incoming RXx signal, the RXx signal is timing the BRG.
In ABD mode, the internal Baud Rate Generator is
used as a counter to time the bit period of the incoming
serial byte stream.
3: Ensure that BRG16 (BAUDCON<3>) is
set, to enable the auto-baud feature.
TABLE 20-4: BRG COUNTER
CLOCK RATES
Once the ABDEN bit is set, the state machine will clear
the BRG and look for a Start bit. The Auto-Baud Rate
Detect must receive a byte with the value 55h (ASCII
“U”, which is also the LIN bus Sync character) in order to
calculate the proper bit rate. The measurement is taken
over both a low and a high bit time in order to minimize
any effects caused by asymmetry of the incoming signal.
After a Start bit, the SPBRGx begins counting up, using
the preselected clock source on the first rising edge of
RXx. After eight bits on the RXx pin or the fifth rising
edge, an accumulated value totalling the proper BRG
period is left in the SPBRGHx:SPBRGx register pair.
Once the 5th edge is seen (this should correspond to the
Stop bit), the ABDEN bit is automatically cleared.
BRG16 BRGH
BRG Counter Clock
0
0
1
1
0
1
0
1
FOSC/512
FOSC/128
FOSC/128
FOSC/32
Note: During the ABD sequence, SPBRGx and
SPBRGHx are both used as a 16-bit counter,
independent of BRG16 setting.
20.1.3.1
ABD and EUSART Transmission
If a rollover of the BRG occurs (an overflow from FFFFh
to 0000h), the event is trapped by the ABDOVF status
bit (BAUDCONx<7>). It is set in hardware by BRG roll-
overs and can be set or cleared by the user in software.
ABD mode remains active after rollover events and the
ABDEN bit remains set (Figure 20-2).
Since the BRG clock is reversed during ABD acquisi-
tion, the EUSART transmitter cannot be used during
ABD. This means that whenever the ABDEN bit is set,
TXREGx cannot be written to. Users should also
ensure that ABDEN does not become set during a
transmit sequence. Failing to do this may result in
unpredictable EUSART operation.
While calibrating the baud rate period, the BRG regis-
ters are clocked at 1/8th the preconfigured clock rate.
Note that the BRG clock will be configured by the
BRG16 and BRGH bits. This allows the user to verify
that no carry occurred for 8-bit modes by checking for
00h in the SPBRGHx register. Refer to Table 20-4 for
counter clock rates to the BRG.
While the ABD sequence takes place, the EUSART
state machine is held in Idle. The RCxIF interrupt is set
once the fifth rising edge on RXx is detected. The value
in the RCREGx needs to be read to clear the RCxIF
interrupt. The contents of RCREGx should be
discarded.
© 2009 Microchip Technology Inc.
DS39778D-page 279
PIC18F87J11 FAMILY
FIGURE 20-1:
AUTOMATIC BAUD RATE CALCULATION
BRG Value
RXx pin
XXXXh
0000h
001Ch
Edge #5
Stop Bit
Edge #2
Bit 3
Edge #3
Bit 5
Edge #4
Bit 7
Bit 6
Edge #1
Bit 1
Start
Bit 0
Bit 2
Bit 4
BRG Clock
Auto-Cleared
Set by User
ABDEN bit
RCxIF bit
(Interrupt)
Read
RCREGx
XXXXh
XXXXh
1Ch
00h
SPBRGx
SPBRGHx
Note: The ABD sequence requires the EUSART module to be configured in Asynchronous mode and WUE = 0.
FIGURE 20-2:
BRG OVERFLOW SEQUENCE
BRG Clock
ABDEN bit
RXx pin
Start
Bit 0
ABDOVF bit
BRG Value
FFFFh
XXXXh
0000h
0000h
DS39778D-page 280
© 2009 Microchip Technology Inc.
PIC18F87J11 FAMILY
Once the TXREGx register transfers the data to the TSR
register (occurs in one TCY), the TXREGx register is
empty and the TXxIF flag bit is set. This interrupt can be
enabled or disabled by setting or clearing the interrupt
enable bit, TXxIE. TXxIF will be set regardless of the
state of TXxIE; it cannot be cleared in software. TXxIF is
also not cleared immediately upon loading TXREGx, but
becomes valid in the second instruction cycle following
the load instruction. Polling TXxIF immediately following
a load of TXREGx will return invalid results.
20.2 EUSART Asynchronous Mode
The Asynchronous mode of operation is selected by
clearing the SYNC bit (TXSTAx<4>). In this mode, the
EUSART uses standard Non-Return-to-Zero (NRZ)
format (one Start bit, eight or nine data bits and one Stop
bit). The most common data format is 8 bits. An on-chip,
dedicated 8-bit/16-bit Baud Rate Generator can be used
to derive standard baud rate frequencies from the
oscillator.
The EUSART transmits and receives the LSb first. The
EUSART’s transmitter and receiver are functionally
independent but use the same data format and baud
rate. The Baud Rate Generator produces a clock, either
x16 or x64 of the bit shift rate, depending on the BRGH
and BRG16 bits (TXSTAx<2> and BAUDCONx<3>).
Parity is not supported by the hardware but can be
implemented in software and stored as the 9th data bit.
While TXxIF indicates the status of the TXREGx regis-
ter; another bit, TRMT (TXSTAx<1>), shows the status
of the TSR register. TRMT is a read-only bit which is set
when the TSR register is empty. No interrupt logic is
tied to this bit so the user has to poll this bit in order to
determine if the TSR register is empty.
Note 1: The TSR register is not mapped in data
When operating in Asynchronous mode, the EUSART
module consists of the following important elements:
memory, so it is not available to the user.
2: Flag bit, TXxIF, is set when enable bit,
• Baud Rate Generator
TXEN, is set.
• Sampling Circuit
To set up an Asynchronous Transmission:
• Asynchronous Transmitter
• Asynchronous Receiver
1. Initialize the SPBRGHx:SPBRGx registers for
the appropriate baud rate. Set or clear the
BRGH and BRG16 bits, as required, to achieve
the desired baud rate.
• Auto-Wake-up on Sync Break Character
• 12-Bit Break Character Transmit
• Auto-Baud Rate Detection
2. Enable the asynchronous serial port by clearing
bit SYNC and setting bit, SPEN.
20.2.1
EUSART ASYNCHRONOUS
TRANSMITTER
3. If interrupts are desired, set enable bit, TXxIE.
4. If 9-bit transmission is desired, set transmit bit
TX9. Can be used as address/data bit.
The EUSART transmitter block diagram is shown in
Figure 20-3. The heart of the transmitter is the Transmit
(Serial) Shift Register (TSR). The Shift register obtains
its data from the Read/Write Transmit Buffer register,
TXREGx. The TXREGx register is loaded with data in
software. The TSR register is not loaded until the Stop
bit has been transmitted from the previous load. As
soon as the Stop bit is transmitted, the TSR is loaded
with new data from the TXREGx register (if available).
5. Enable the transmission by setting bit, TXEN,
which will also set bit, TXxIF.
6. If 9-bit transmission is selected, the ninth bit
should be loaded in bit, TX9D.
7. Load data to the TXREGx register (starts
transmission).
8. If using interrupts, ensure that the GIE and PEIE
bits in the INTCON register (INTCON<7:6>) are
set.
FIGURE 20-3:
EUSART TRANSMIT BLOCK DIAGRAM
Data Bus
TXxIF
TXREGx Register
TXxIE
8
MSb
(8)
LSb
0
Pin Buffer
and Control
•
•
•
TSR Register
TXx pin
Interrupt
Baud Rate CLK
TXEN
TRMT
SPEN
BRG16
SPBRGHx SPBRGx
Baud Rate Generator
TX9
TX9D
© 2009 Microchip Technology Inc.
DS39778D-page 281
PIC18F87J11 FAMILY
FIGURE 20-4:
ASYNCHRONOUS TRANSMISSION
Write to TXREGx
Word 1
BRG Output
(Shift Clock)
TXx (pin)
Start bit
bit 0
bit 1
Word 1
bit 7/8
Stop bit
TXxIF bit
(Transmit Buffer
Reg. Empty Flag)
1 TCY
Word 1
Transmit Shift Reg
TRMT bit
(Transmit Shift
Reg. Empty Flag)
FIGURE 20-5:
ASYNCHRONOUS TRANSMISSION (BACK-TO-BACK)
Write to TXREGx
Word 2
Start bit
Word 1
BRG Output
(Shift Clock)
TXx (pin)
Start bit
bit 0
bit 1
bit 7/8
bit 0
Stop bit
1 TCY
Word 2
Word 1
TXxIF bit
(Interrupt Reg. Flag)
1 TCY
Word 1
Transmit Shift Reg.
Word 2
Transmit Shift Reg.
TRMT bit
(Transmit Shift
Reg. Empty Flag)
Note: This timing diagram shows two consecutive transmissions.
TABLE 20-5: REGISTERS ASSOCIATED WITH ASYNCHRONOUS TRANSMISSION
Reset
Values
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
on Page:
INTCON
PIR1
GIE/GIEH PEIE/GIEL TMR0IE
INT0IE
TX1IF
TX1IE
TX1IP
TX2IF
TX2IE
TX2IP
CREN
RBIE
TMR0IF
CCP1IF
INT0IF
RBIF
57
60
60
60
60
60
60
59
59
59
61
61
61
PMPIF
PMPIE
PMPIP
SSP2IF
SSP2IE
SSP2IP
SPEN
ADIF
ADIE
RC1IF
RC1IE
RC1IP
RC2IF
RC2IE
RC2IP
SREN
SSP1IF
SSP1IE
SSP1IP
TMR4IF
TMR2IF
TMR1IF
PIE1
CCP1IE TMR2IE TMR1IE
CCP1IP TMR2IP TMR1IP
IPR1
ADIP
PIR3
BCL2IF
BCL2IE
BCL2IP
RX9
CCP5IF
CCP4IF
CCP4IE
CCP4IP
OERR
CCP3IF
CCP3IE
CCP3IP
RX9D
PIE3
TMR4IE CCP5IE
TMR4IP CCP5IP
IPR3
RCSTAx
TXREGx
TXSTAx
ADDEN
FERR
EUSARTx Transmit Register
CSRC
TX9
TXEN
SYNC
SENDB
BRG16
BRGH
—
TRMT
WUE
TX9D
BAUDCONx ABDOVF
RCIDL
RXDTP
TXCKP
ABDEN
SPBRGHx
SPBRGx
EUSARTx Baud Rate Generator Register High Byte
EUSARTx Baud Rate Generator Register Low Byte
Legend: —= unimplemented locations read as ‘0’. Shaded cells are not used for asynchronous transmission.
DS39778D-page 282
© 2009 Microchip Technology Inc.
PIC18F87J11 FAMILY
20.2.2
EUSART ASYNCHRONOUS
RECEIVER
20.2.3
SETTING UP 9-BIT MODE WITH
ADDRESS DETECT
The receiver block diagram is shown in Figure 20-6.
The data is received on the RXx pin and drives the data
recovery block. The data recovery block is actually a
high-speed shifter operating at x16 times the baud rate,
whereas the main receive serial shifter operates at the
bit rate or at FOSC. This mode would typically be used
in RS-232 systems.
This mode would typically be used in RS-485 systems.
To set up an Asynchronous Reception with Address
Detect Enable:
1. Initialize the SPBRGHx:SPBRGx registers for
the appropriate baud rate. Set or clear the
BRGH and BRG16 bits, as required, to achieve
the desired baud rate.
To set up an Asynchronous Reception:
2. Enable the asynchronous serial port by clearing
the SYNC bit and setting the SPEN bit.
1. Initialize the SPBRGHx:SPBRGx registers for
the appropriate baud rate. Set or clear the
BRGH and BRG16 bits, as required, to achieve
the desired baud rate.
3. If interrupts are required, set the RCEN bit and
select the desired priority level with the RCxIP bit.
4. Set the RX9 bit to enable 9-bit reception.
5. Set the ADDEN bit to enable address detect.
6. Enable reception by setting the CREN bit.
2. Enable the asynchronous serial port by clearing
bit, SYNC, and setting bit, SPEN.
3. If interrupts are desired, set enable bit, RCxIE.
4. If 9-bit reception is desired, set bit, RX9.
5. Enable the reception by setting bit, CREN.
7. The RCxIF bit will be set when reception is
complete. The interrupt will be Acknowledged if
the RCxIE and GIE bits are set.
6. Flag bit, RCxIF, will be set when reception is
complete and an interrupt will be generated if
enable bit, RCxIE, was set.
8. Read the RCSTAx register to determine if any
error occurred during reception, as well as read
bit 9 of data (if applicable).
7. Read the RCSTAx register to get the 9th bit (if
enabled) and determine if any error occurred
during reception.
9. Read RCREGx to determine if the device is
being addressed.
10. If any error occurred, clear the CREN bit.
8. Read the 8-bit received data by reading the
RCREGx register.
11. If the device has been addressed, clear the
ADDEN bit to allow all received data into the
receive buffer and interrupt the CPU.
9. If any error occurred, clear the error by clearing
enable bit, CREN.
10. If using interrupts, ensure that the GIE and PEIE
bits in the INTCON register (INTCON<7:6>) are
set.
FIGURE 20-6:
EUSART RECEIVE BLOCK DIAGRAM
CREN
OERR
FERR
x64 Baud Rate CLK
÷ 64
RSR Register
• • •
MSb
Stop
LSb
Start
BRG16
SPBRGHx SPBRGx
or
÷ 16
(8)
7
1
0
or
Baud Rate Generator
÷ 4
RX9
Pin Buffer
and Control
Data
Recovery
RXx
RX9D
RCREGx Register
FIFO
SPEN
8
Interrupt
RCxIF
RCxIE
Data Bus
© 2009 Microchip Technology Inc.
DS39778D-page 283
PIC18F87J11 FAMILY
FIGURE 20-7:
ASYNCHRONOUS RECEPTION
Start
bit
Start
bit
Start
bit
RXx (pin)
Stop
bit
Stop
bit
Stop
bit
bit 0 bit 1
bit 7/8
bit 0
bit 7/8
bit 7/8
Rcv Shift Reg
Rcv Buffer Reg
Word 2
RCREGx
Word 1
RCREGx
Read Rcv
Buffer Reg
RCREGx
RCxIF
(Interrupt Flag)
OERR bit
CREN
Note: This timing diagram shows three words appearing on the RXx input. The RCREGx (Receive Buffer) is read after the third word
causing the OERR (Overrun) bit to be set.
TABLE 20-6: REGISTERS ASSOCIATED WITH ASYNCHRONOUS RECEPTION
Reset
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Values
on Page:
INTCON
PIR1
GIE/GIEH PEIE/GIEL TMR0IE
INT0IE
TX1IF
TX1IE
TX1IP
TX2IF
TX2IE
TX2IP
CREN
RBIE
TMR0IF
INT0IF
RBIF
57
60
60
60
60
60
60
59
59
59
61
61
61
PMPIF
PMPIE
PMPIP
SSP2IF
SSP2IE
SSP2IP
SPEN
ADIF
ADIE
RC1IF
RC1IE
RC1IP
RC2IF
RC2IE
RC2IP
SREN
SSP1IF
SSP1IE
SSP1IP
CCP1IF TMR2IF TMR1IF
CCP1IE TMR2IE TMR1IE
CCP1IP TMR2IP TMR1IP
PIE1
IPR1
ADIP
PIR3
BCL2IF
BCL2IE
BCL2IP
RX9
TMR4IF CCP5IF
CCP4IF CCP3IF
PIE3
TMR4IE CCP5IE CCP4IE CCP3IE
TMR4IP CCP5IP CCP4IP CCP3IP
IPR3
RCSTAx
RCREGx
TXSTAx
ADDEN
FERR
OERR
RX9D
EUSARTx Receive Register
CSRC
TX9
TXEN
SYNC
SENDB
BRG16
BRGH
—
TRMT
WUE
TX9D
BAUDCONx ABDOVF
RCIDL
RXDTP
TXCKP
ABDEN
SPBRGHx
SPBRGx
EUSARTx Baud Rate Generator Register High Byte
EUSARTx Baud Rate Generator Register Low Byte
Legend: — = unimplemented locations read as ‘0’. Shaded cells are not used for asynchronous reception.
the RXx/DTx line. (This coincides with the start of a
Sync Break or a Wake-up Signal character for the LIN
protocol.)
20.2.4
AUTO-WAKE-UP ON SYNC BREAK
CHARACTER
During Sleep mode, all clocks to the EUSART are
suspended. Because of this, the Baud Rate Generator
is inactive and a proper byte reception cannot be per-
formed. The auto-wake-up feature allows the controller
to wake-up due to activity on the RXx/DTx line while the
EUSART is operating in Asynchronous mode.
Following a wake-up event, the module generates an
RCxIF interrupt. The interrupt is generated synchro-
nously to the Q clocks in normal operating modes
(Figure 20-8) and asynchronously if the device is in
Sleep mode (Figure 20-9). The interrupt condition is
cleared by reading the RCREGx register.
The auto-wake-up feature is enabled by setting the
WUE bit (BAUDCONx<1>). Once set, the typical
receive sequence on RXx/DTx is disabled and the
EUSART remains in an Idle state, monitoring for a
wake-up event independent of the CPU mode. A
wake-up event consists of a high-to-low transition on
The WUE bit is automatically cleared once a low-to-high
transition is observed on the RXx line following the
wake-up event. At this point, the EUSART module is in
Idle mode and returns to normal operation. This signals
to the user that the Sync Break event is over.
DS39778D-page 284
© 2009 Microchip Technology Inc.
PIC18F87J11 FAMILY
20.2.4.1
Special Considerations Using
Auto-Wake-up
20.2.4.2
Special Considerations Using
the WUE Bit
Since auto-wake-up functions by sensing rising edge
transitions on RXx/DTx, information with any state
changes before the Stop bit may signal a false
End-of-Character (EOC) and cause data or framing
errors. To work properly, therefore, the initial character
in the transmission must be all ‘0’s. This can be 00h
(8 bytes) for standard RS-232 devices or 000h (12 bits)
for LIN bus.
The timing of WUE and RCxIF events may cause some
confusion when it comes to determining the validity of
received data. As noted, setting the WUE bit places the
EUSART in an Idle mode. The wake-up event causes a
receive interrupt by setting the RCxIF bit. The WUE bit
is cleared after this when a rising edge is seen on
RXx/DTx. The interrupt condition is then cleared by
reading the RCREGx register. Ordinarily, the data in
RCREGx will be dummy data and should be discarded.
Oscillator start-up time must also be considered,
especially in applications using oscillators with longer
start-up intervals (i.e., HS or HSPLL mode). The Sync
Break (or Wake-up Signal) character must be of
sufficient length and be followed by a sufficient interval
to allow enough time for the selected oscillator to start
and provide proper initialization of the EUSART.
The fact that the WUE bit has been cleared (or is still
set) and the RCxIF flag is set should not be used as an
indicator of the integrity of the data in RCREGx. Users
should consider implementing a parallel method in
firmware to verify received data integrity.
To assure that no actual data is lost, check the RCIDL
bit to verify that a receive operation is not in process. If
a receive operation is not occurring, the WUE bit may
then be set just prior to entering the Sleep mode.
FIGURE 20-8:
AUTO-WAKE-UP BIT (WUE) TIMINGS DURING NORMAL OPERATION
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
Bit set by user
Auto-Cleared
OSC1
WUE bit(1)
RXx/DTx Line
RCxIF
Cleared due to user read of RCREGx
Note 1: The EUSART remains in Idle while the WUE bit is set.
FIGURE 20-9:
AUTO-WAKE-UP BIT (WUE) TIMINGS DURING SLEEP
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
Q1
Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
Auto-Cleared
OSC1
WUE bit(2)
RXx/DTx Line
RCxIF
Bit set by user
Note 1
Cleared due to user read of RCREGx
Sleep Ends
SLEEPCommand Executed
Note 1: If the wake-up event requires long oscillator warm-up time, the auto-clear of the WUE bit can occur before the oscillator is ready. This
sequence should not depend on the presence of Q clocks.
2: The EUSART remains in Idle while the WUE bit is set.
© 2009 Microchip Technology Inc.
DS39778D-page 285
PIC18F87J11 FAMILY
1. Configure the EUSART for the desired mode.
20.2.5
BREAK CHARACTER SEQUENCE
2. Set the TXEN and SENDB bits to set up the
Break character.
The EUSART module has the capability of sending the
special Break character sequences that are required by
the LIN bus standard. The Break character transmit
consists of a Start bit, followed by twelve ‘0’ bits and a
Stop bit. The Frame Break character is sent whenever
the SENDB and TXEN bits (TXSTAx<3> and
TXSTAx<5>) are set while the Transmit Shift Register
is loaded with data. Note that the value of data written
to TXREGx will be ignored and all ‘0’s will be
transmitted.
3. Load the TXREGx with a dummy character to
initiate transmission (the value is ignored).
4. Write ‘55h’ to TXREGx to load the Sync
character into the transmit FIFO buffer.
5. After the Break has been sent, the SENDB bit is
reset by hardware. The Sync character now
transmits in the preconfigured mode.
When the TXREGx becomes empty, as indicated by
the TXxIF, the next data byte can be written to
TXREGx.
The SENDB bit is automatically reset by hardware after
the corresponding Stop bit is sent. This allows the user
to preload the transmit FIFO with the next transmit byte
following the Break character (typically, the Sync
character in the LIN specification).
20.2.6
RECEIVING A BREAK CHARACTER
The Enhanced USART module can receive a Break
character in two ways.
Note that the data value written to the TXREGx for the
Break character is ignored. The write simply serves the
purpose of initiating the proper sequence.
The first method forces configuration of the baud rate
at a frequency of 9/13 the typical speed. This allows for
the Stop bit transition to be at the correct sampling
location (13 bits for Break versus Start bit and 8 data
bits for typical data).
The TRMT bit indicates when the transmit operation is
active or Idle, just as it does during normal transmis-
sion. See Figure 20-10 for the timing of the Break
character sequence.
The second method uses the auto-wake-up feature
described in Section 20.2.4 “Auto-Wake-up on Sync
Break Character”. By enabling this feature, the
EUSART will sample the next two transitions on
RXx/DTx, cause an RCxIF interrupt and receive the
next data byte followed by another interrupt.
20.2.5.1
Break and Sync Transmit Sequence
The following sequence will send a message frame
header made up of a Break, followed by an Auto-Baud
Sync byte. This sequence is typical of a LIN bus
master.
Note that following a Break character, the user will
typically want to enable the Auto-Baud Rate Detect
feature. For both methods, the user can set the ABDEN
bit once the TXxIF interrupt is observed.
FIGURE 20-10:
SEND BREAK CHARACTER SEQUENCE
Write to TXREGx
Dummy Write
BRG Output
(Shift Clock)
TXx (pin)
Start Bit
Bit 0
Bit 1
Break
Bit 11
Stop Bit
TXxIF bit
(Transmit Buffer
Reg. Empty Flag)
TRMT bit
(Transmit Shift
Reg. Empty Flag)
SENDB sampled here
Auto-Cleared
SENDB bit
(Transmit Shift
Reg. Empty Flag)
DS39778D-page 286
© 2009 Microchip Technology Inc.
PIC18F87J11 FAMILY
Once the TXREGx register transfers the data to the
TSR register (occurs in one TCY), the TXREGx is empty
and the TXxIF flag bit is set. The interrupt can be
enabled or disabled by setting or clearing the interrupt
enable bit, TXxIE. TXxIF is set regardless of the state
of enable bit, TXxIE; it cannot be cleared in software. It
will reset only when new data is loaded into the
TXREGx register.
20.3 EUSART Synchronous
Master Mode
The Synchronous Master mode is entered by setting
the CSRC bit (TXSTAx<7>). In this mode, the data is
transmitted in a half-duplex manner (i.e., transmission
and reception do not occur at the same time). When
transmitting data, the reception is inhibited and vice
versa. Synchronous mode is entered by setting bit,
SYNC (TXSTAx<4>). In addition, enable bit, SPEN
(RCSTAx<7>), is set in order to configure the TXx and
RXx pins to CKx (clock) and DTx (data) lines,
respectively.
While flag bit, TXxIF, indicates the status of the TXREGx
register, another bit, TRMT (TXSTAx<1>), shows the
status of the TSR register. TRMT is a read-only bit which
is set when the TSR is empty. No interrupt logic is tied to
this bit, so the user must poll this bit in order to determine
if the TSR register is empty. The TSR is not mapped in
data memory so it is not available to the user.
The Master mode indicates that the processor trans-
mits the master clock on the CKx line. Clock polarity is
selected with the TXCKP bit (BAUDCONx<4>). Setting
TXCKP sets the Idle state on CKx as high, while clear-
ing the bit sets the Idle state as low. This option is
provided to support Microwire devices with this module.
To set up a Synchronous Master Transmission:
1. Initialize the SPBRGHx:SPBRGx registers for the
appropriate baud rate. Set or clear the BRG16
bit, as required, to achieve the desired baud rate.
20.3.1
EUSART SYNCHRONOUS MASTER
TRANSMISSION
2. Enable the synchronous master serial port by
setting bits, SYNC, SPEN and CSRC.
3. If interrupts are desired, set enable bit, TXxIE.
4. If 9-bit transmission is desired, set bit, TX9.
5. Enable the transmission by setting bit, TXEN.
The EUSART transmitter block diagram is shown in
Figure 20-3. The heart of the transmitter is the Transmit
(Serial) Shift Register (TSR). The Shift register obtains
its data from the Read/Write Transmit Buffer register,
TXREGx. The TXREGx register is loaded with data in
software. The TSR register is not loaded until the last
bit has been transmitted from the previous load. As
soon as the last bit is transmitted, the TSR is loaded
with new data from the TXREGx (if available).
6. If 9-bit transmission is selected, the ninth bit
should be loaded in bit, TX9D.
7. Start transmission by loading data to the
TXREGx register.
8. If using interrupts, ensure that the GIE and PEIE
bits in the INTCON register (INTCON<7:6>) are
set.
FIGURE 20-11:
SYNCHRONOUS TRANSMISSION
Q1 Q2 Q3Q4 Q1 Q2 Q3 Q4 Q1Q2 Q3 Q4 Q1Q2 Q3 Q4 Q1 Q2 Q3 Q4
Q3 Q4 Q1 Q2 Q3Q4 Q1Q2 Q3Q4 Q1 Q2Q3Q4 Q1 Q2Q3 Q4Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
RC7/RX1/DT1
bit 0
bit 1
bit 2
bit 7
bit 0
bit 1
bit 7
Word 2
Word 1
RC6/TX1/CK1 pin
(TXCKP = 0)
RC6/TX1/CK1 pin
(TXCKP = 1)
Write to
TXREG1 Reg
Write Word 1
Write Word 2
TX1IF bit
(Interrupt Flag)
TRMT bit
‘1’
‘1’
TXEN bit
Note: Sync Master mode, SPBRGx = 0, continuous transmission of two 8-bit words. This example is equally applicable to EUSART2
(RG1/TX2/CK2 and RG2/RX2/DT2).
© 2009 Microchip Technology Inc.
DS39778D-page 287
PIC18F87J11 FAMILY
FIGURE 20-12:
SYNCHRONOUS TRANSMISSION (THROUGH TXEN)
RC7/RX1/DT1 pin
bit 0
bit 2
bit 1
bit 6
bit 7
RC6/TX1/CK1 pin
Write to
TXREG1 reg
TX1IF bit
TRMT bit
TXEN bit
Note: This example is equally applicable to EUSART2 (RG1/TX2/CK2 and RG2/RX2/DT2).
TABLE 20-7: REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER TRANSMISSION
Reset
Values
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
on Page:
INTCON
PIR1
GIE/GIEH PEIE/GIEL TMR0IE
INT0IE
TX1IF
TX1IE
TX1IP
TX2IF
TX2IE
TX2IP
CREN
RBIE
TMR0IF
INT0IF
RBIF
57
60
60
60
60
60
60
59
59
59
61
61
61
PMPIF
PMPIE
PMPIP
SSP2IF
SSP2IE
SSP2IP
SPEN
ADIF
ADIE
RC1IF
RC1IE
RC1IP
RC2IF
RC2IE
RC2IP
SREN
SSP1IF
SSP1IE
SSP1IP
CCP1IF TMR2IF TMR1IF
CCP1IE TMR2IE TMR1IE
CCP1IP TMR2IP TMR1IP
PIE1
IPR1
ADIP
PIR3
BCL2IF
BCL2IE
BCL2IP
RX9
TMR4IF CCP5IF
CCP4IF
CCP3IF
PIE3
TMR4IE CCP5IE CCP4IE CCP3IE
TMR4IP CCP5IP CCP4IP CCP3IP
IPR3
RCSTAx
TXREGx
TXSTAx
ADDEN
FERR
OERR
RX9D
EUSARTx Transmit Register
CSRC
TX9
TXEN
SYNC
SENDB
BRG16
BRGH
—
TRMT
WUE
TX9D
BAUDCONx ABDOVF
RCIDL
RXDTP
TXCKP
ABDEN
SPBRGHx EUSARTx Baud Rate Generator Register High Byte
SPBRGx EUSARTx Baud Rate Generator Register Low Byte
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used for synchronous master transmission.
DS39778D-page 288
© 2009 Microchip Technology Inc.
PIC18F87J11 FAMILY
3. Ensure bits, CREN and SREN, are clear.
4. If interrupts are desired, set enable bit, RCxIE.
5. If 9-bit reception is desired, set bit, RX9.
6. If a single reception is required, set bit, SREN.
For continuous reception, set bit, CREN.
7. Interrupt flag bit, RCxIF, will be set when recep-
tion is complete and an interrupt will be generated
if the enable bit, RCxIE, was set.
8. Read the RCSTAx register to get the 9th bit (if
enabled) and determine if any error occurred
during reception.
9. Read the 8-bit received data by reading the
RCREGx register.
20.3.2
EUSART SYNCHRONOUS
MASTER RECEPTION
Once Synchronous mode is selected, reception is
enabled by setting either the Single Receive Enable bit,
SREN (RCSTAx<5>) or the Continuous Receive
Enable bit, CREN (RCSTAx<4>). Data is sampled on
the RXx pin on the falling edge of the clock.
If enable bit, SREN, is set, only a single word is
received. If enable bit, CREN, is set, the reception is
continuous until CREN is cleared. If both bits are set,
then CREN takes precedence.
To set up a Synchronous Master Reception:
10. If any error occurred, clear the error by clearing
bit CREN.
11. If using interrupts, ensure that the GIE and PEIE bits
in the INTCON register (INTCON<7:6>) are set.
1. Initialize the SPBRGHx:SPBRGx registers for the
appropriate baud rate. Set or clear the BRG16
bit, as required, to achieve the desired baud rate.
2. Enable the synchronous master serial port by
setting bits, SYNC, SPEN and CSRC.
FIGURE 20-13:
SYNCHRONOUS RECEPTION (MASTER MODE, SREN)
Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4Q1 Q2 Q3 Q4 Q1Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
RC7/RX1/DT1
pin
bit 0
bit 1
bit 2
bit 3
bit 4
bit 5
bit 6
bit 7
RC6/TX1/CK1 pin
(TXCKP = 0)
RC6/TX1/CK1 pin
(TXCKP = 1)
Write to
bit SREN
SREN bit
CREN bit
‘0’
‘0’
RC1IF bit
(Interrupt)
Read
RCREG1
Note: Timing diagram demonstrates Sync Master mode with bit SREN = 1and bit BRGH = 0. This example is equally applicable to EUSART2
(RG1/TX2/CK2 and RG2/RX2/DT2).
© 2009 Microchip Technology Inc.
DS39778D-page 289
PIC18F87J11 FAMILY
TABLE 20-8: REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER RECEPTION
Reset Values
on Page:
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
INTCON
PIR1
GIE/GIEH PEIE/GIEL TMR0IE INT0IE
RBIE
TMR0IF
INT0IF
RBIF
57
60
60
60
60
60
60
59
59
59
61
61
61
PMPIF
PMPIE
PMPIP
SSP2IF
SSP2IE
SSP2IP
SPEN
ADIF
ADIE
RC1IF
RC1IE
RC1IP
RC2IF
RC2IE
RC2IP
SREN
TX1IF
TX1IE
TX1IP
TX2IF
TX2IE
TX2IP
CREN
SSP1IF CCP1IF TMR2IF TMR1IF
SSP1IE CCP1IE TMR2IE TMR1IE
SSP1IP CCP1IP TMR2IP TMR1IP
TMR4IF CCP5IF CCP4IF CCP3IF
TMR4IE CCP5IE CCP4IE CCP3IE
TMR4IP CCP5IP CCP4IP CCP3IP
PIE1
IPR1
ADIP
PIR3
BCL2IF
BCL2IE
BCL2IP
RX9
PIE3
IPR3
RCSTAx
RCREGx
TXSTAx
ADDEN
FERR
OERR
RX9D
EUSARTx Receive Register
CSRC
TX9
TXEN
SYNC
SENDB
BRGH
—
TRMT
WUE
TX9D
BAUDCONx ABDOVF
RCIDL
RXDTP TXCKP BRG16
ABDEN
SPBRGHx EUSARTx Baud Rate Generator Register High Byte
SPBRGx EUSARTx Baud Rate Generator Register Low Byte
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used for synchronous master reception.
To set up a Synchronous Slave Transmission:
20.4 EUSART Synchronous
Slave Mode
1. Enable the synchronous slave serial port by
setting bits, SYNC and SPEN, and clearing bit,
CSRC.
Synchronous Slave mode is entered by clearing bit,
CSRC (TXSTAx<7>). This mode differs from the
Synchronous Master mode in that the shift clock is sup-
plied externally at the CKx pin (instead of being supplied
internally in Master mode). This allows the device to
transfer or receive data while in any low-power mode.
2. Clear bits, CREN and SREN.
3. If interrupts are desired, set enable bit, TXxIE.
4. If 9-bit transmission is desired, set bit, TX9.
5. Enable the transmission by setting enable bit,
TXEN.
20.4.1
EUSART SYNCHRONOUS
SLAVE TRANSMISSION
6. If 9-bit transmission is selected, the ninth bit
should be loaded in bit, TX9D.
The operation of the Synchronous Master and Slave
modes is identical, except in the case of Sleep mode.
7. Start transmission by loading data to the
TXREGx register.
If two words are written to the TXREGx and then the
SLEEPinstruction is executed, the following will occur:
8. If using interrupts, ensure that the GIE and PEIE
bits in the INTCON register (INTCON<7:6>) are
set.
a) The first word will immediately transfer to the
TSR register and transmit.
b) The second word will remain in the TXREGx
register.
c) Flag bit, TXxIF, will not be set.
d) When the first word has been shifted out of TSR,
the TXREGx register will transfer the second
word to the TSR and flag bit, TXxIF, will now be
set.
e) If enable bit, TXxIE, is set, the interrupt will wake
the chip from Sleep. If the global interrupt is
enabled, the program will branch to the interrupt
vector.
DS39778D-page 290
© 2009 Microchip Technology Inc.
PIC18F87J11 FAMILY
TABLE 20-9: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE TRANSMISSION
Reset
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Values
on Page:
INTCON
PIR1
GIE/GIEH PEIE/GIEL TMR0IE
INT0IE
TX1IF
TX1IE
TX1IP
TX2IF
TX2IE
TX2IP
CREN
RBIE
TMR0IF
CCP1IF
INT0IF
RBIF
57
60
60
60
60
60
60
59
59
59
61
61
61
PMPIF
PMPIE
PMPIP
SSP2IF
SSP2IE
SSP2IP
SPEN
ADIF
ADIE
RC1IF
RC1IE
RC1IP
RC2IF
RC2IE
RC2IP
SREN
SSP1IF
SSP1IE
SSP1IP
TMR4IF
TMR2IF TMR1IF
PIE1
CCP1IE TMR2IE TMR1IE
CCP1IP TMR2IP TMR1IP
IPR1
ADIP
PIR3
BCL2IF
BCL2IE
BCL2IP
RX9
CCP5IF
CCP4IF
CCP3IF
PIE3
TMR4IE CCP5IE
TMR4IP CCP5IP
CCP4IE CCP3IE
CCP4IP CCP3IP
IPR3
RCSTAx
TXREGx
TXSTAx
ADDEN
FERR
OERR
RX9D
EUSARTx Transmit Register
CSRC
TX9
TXEN
SYNC
SENDB
BRG16
BRGH
—
TRMT
WUE
TX9D
BAUDCONx ABDOVF
RCIDL
RXDTP
TXCKP
ABDEN
SPBRGHx EUSARTx Baud Rate Generator Register High Byte
SPBRGx EUSARTx Baud Rate Generator Register Low Byte
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used for synchronous slave transmission.
To set up a Synchronous Slave Reception:
20.4.2
EUSART SYNCHRONOUS SLAVE
RECEPTION
1. Enable the synchronous master serial port by
setting bits, SYNC and SPEN, and clearing bit,
CSRC.
The operation of the Synchronous Master and Slave
modes is identical, except in the case of Sleep, or any
Idle mode and bit, SREN, which is a “don’t care” in
Slave mode.
2. If interrupts are desired, set enable bit, RCxIE.
3. If 9-bit reception is desired, set bit, RX9.
4. To enable reception, set enable bit, CREN.
If receive is enabled by setting the CREN bit prior to
entering Sleep or any Idle mode, then a word may be
received while in this low-power mode. Once the word
is received, the RSR register will transfer the data to the
RCREGx register. If the RCxIE enable bit is set, the
interrupt generated will wake the chip from the
low-power mode. If the global interrupt is enabled, the
program will branch to the interrupt vector.
5. Flag bit, RCxIF, will be set when reception is
complete. An interrupt will be generated if
enable bit, RCxIE, was set.
6. Read the RCSTAx register to get the 9th bit (if
enabled) and determine if any error occurred
during reception.
7. Read the 8-bit received data by reading the
RCREGx register.
8. If any error occurred, clear the error by clearing
bit, CREN.
9. If using interrupts, ensure that the GIE and PEIE
bits in the INTCON register (INTCON<7:6>) are
set.
© 2009 Microchip Technology Inc.
DS39778D-page 291
PIC18F87J11 FAMILY
TABLE 20-10: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE RECEPTION
Reset
Values
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
on Page:
INTCON
PIR1
GIE/GIEH PEIE/GIEL TMR0IE
INT0IE
TX1IF
TX1IE
TX1IP
TX2IF
TX2IE
TX2IP
CREN
RBIE
TMR0IF
CCP1IF
INT0IF
RBIF
57
60
60
60
60
60
60
59
59
59
61
61
61
PMPIF
PMPIE
PMPIP
SSP2IF
SSP2IE
SSP2IP
SPEN
ADIF
ADIE
RC1IF
RC1IE
RC1IP
RC2IF
RC2IE
RC2IP
SREN
SSP1IF
SSP1IE
SSP1IP
TMR4IF
TMR2IF TMR1IF
PIE1
CCP1IE TMR2IE TMR1IE
CCP1IP TMR2IP TMR1IP
IPR1
ADIP
PIR3
BCL2IF
BCL2IE
BCL2IP
RX9
CCP5IF
CCP4IF
CCP3IF
CCP3IE
CCP3IP
RX9D
PIE3
TMR4IE CCP5IE CCP4IE
TMR4IP CCP5IP CCP4IP
IPR3
RCSTAx
RCREGx
TXSTAx
ADDEN
FERR
OERR
EUSARTx Receive Register
CSRC
TX9
TXEN
SYNC
SENDB
BRG16
BRGH
—
TRMT
WUE
TX9D
BAUDCONx ABDOVF
RCIDL
RXDTP
TXCKP
ABDEN
SPBRGHx EUSARTx Baud Rate Generator Register High Byte
SPBRGx EUSARTx Baud Rate Generator Register Low Byte
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used for synchronous slave reception.
DS39778D-page 292
© 2009 Microchip Technology Inc.
PIC18F87J11 FAMILY
• A/D Port Configuration Register 2 (ANCON0)
• A/D Port Configuration Register 1 (ANCON1)
• A/D Result Registers (ADRESH and ADRESL)
21.0 10-BIT ANALOG-TO-DIGITAL
CONVERTER (A/D) MODULE
The Analog-to-Digital (A/D) Converter module has
11 inputs for the 64-pin devices and 15 for the 80-pin
devices. This module allows conversion of an analog
input signal to a corresponding 10-bit digital number.
The ADCON0 register, shown in Register 21-1,
controls the operation of the A/D module. The
ADCON1 register, shown in Register 21-2, configures
the A/D clock source, programmed acquisition time and
justification.
The module has six registers:
• A/D Control Register 0 (ADCON0)
• A/D Control Register 1 (ADCON1)
REGISTER 21-1: ADCON0: A/D CONTROL REGISTER 0(1)
R/W-0
R/W-0
R/W-0
CHS3
R/W-0
CHS2
R/W-0
CHS1
R/W-0
CHS0
R/W-0
R/W-0
ADON
VCFG1
VCFG0
GO/DONE
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
-n = Value at POR
bit 7-6
bit
VCFG1: Voltage Reference Configuration bit (VREF- source)
1= VREF- (AN2)
0= AVSS
VCFG0: Voltage Reference Configuration bit (VREF+ source)
1= VREF+ (AN3)
0= AVDD
bit 5-2
CHS3:CHS0: Analog Channel Select bits
0000= Channel 00 (AN0)
0001= Channel 01 (AN1)
0010= Channel 02 (AN2)
0011= Channel 03 (AN3)
0100= Channel 04 (AN4)
0101= Unused
0110= Channel 06 (AN6)
0111= Channel 07 (AN7)
1000= Channel 08 (AN8)
1001= Channel 09 (AN9)
1010= Channel 10 (AN10)
1011= Channel 11 (AN11)
1100= Channel 12 (AN12)(2,3)
1101= Channel 13 (AN13)(2,3)
1110= Channel 14 (AN14)(2,3)
1111= Channel 15 (AN15)(2,3)
bit 1
bit 0
GO/DONE: A/D Conversion Status bit
When ADON = 1:
1= A/D conversion in progress
0= A/D Idle
ADON: A/D On bit
1= A/D Converter module is enabled
0= A/D Converter module is disabled
Note 1: Default (legacy) SFR at this address, available when WDTCON<4> = 0.
2: These channels are not implemented on 64-pin devices.
3: Performing a conversion on unimplemented channels will return random values.
© 2009 Microchip Technology Inc.
DS39778D-page 293
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REGISTER 21-2: ADCON1: A/D CONTROL REGISTER 1(1)
R/W-0
ADFM
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
ADCAL
ACQT2
ACQT1
ACQT0
ADCS2
ADCS1
ADCS0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
-n = Value at POR
bit 7
bit 6
ADFM: A/D Result Format Select bit
1= Right justified
0= Left justified
ADCAL: A/D Calibration bit
1 = Calibration is performed on next A/D conversion
0 = Normal A/D Converter operation (no conversion is performed)
bit 5-3
ACQT2:ACQT0: A/D Acquisition Time Select bits
111= 20 TAD
110= 16 TAD
101= 12 TAD
100= 8 TAD
011= 6 TAD
010= 4 TAD
001= 2 TAD
(1)
000= 0 TAD
bit 2-0
ADCS2:ADCS0: A/D Conversion Clock Select bits
111= FRC (clock derived from A/D RC oscillator)(2)
110= FOSC/64
101= FOSC/16
100= FOSC/4
011= FRC (clock derived from A/D RC oscillator)(2)
010= FOSC/32
001= FOSC/8
000= FOSC/2
Note 1: Default (legacy) SFR at this address, available when WDTCON<4> = 0.
2: If the A/D FRC clock source is selected, a delay of one TCY (instruction cycle) is added before the A/D
clock starts. This allows the SLEEPinstruction to be executed before starting a conversion.
DS39778D-page 294
© 2009 Microchip Technology Inc.
PIC18F87J11 FAMILY
The ANCON0 and ANCON1 registers are used to
configure the operation of the I/O pin associated with
each analog channel. Setting any one of the PCFG bits
configures the corresponding pin to operate as a digital
only I/O. Clearing a bit configures the pin to operate as
an analog input for either the A/D Converter or the
comparator module; all digital peripherals are disabled,
and digital inputs read as ‘0’. As a rule, I/O pins that are
multiplexed with analog inputs default to analog
operation on device Resets.
ANCON0 and ANCON1 are shared address SFRs, and
use the same addresses as the ADCON1 and
ADCON0 registers. The ANCON registers are
accessed by setting the ADSHR bit (WDTCON<4>).
See Section 5.3.4.1 “Shared Address SFRs” for
more information.
REGISTER 21-3: ANCON0: A/D PORT CONFIGURATION REGISTER 2
R/W-0
R/W-0
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
PCFG7
PCFG6
PCFG4
PCFG3
PCFG2
PCFG1
PCFG0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
-n = Value at POR
bit 7-6
PCFG7:PCFG6: Analog Port Configuration bits (AN7 and AN6)
1= Pin configured as a digital port
0= Pin configured as an analog channel; digital input disabled and reads ‘0’
bit 5
Unimplemented: Read as ‘0’
bit 4-0
PCFG4:PCFG0: Analog Port Configuration bits (AN4 through AN0)
1= Pin configured as a digital port
0= Pin configured as an analog channel; digital input disabled and reads ‘0’
REGISTER 21-4: ANCON1: A/D PORT CONFIGURATION REGISTER 1
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
PCFG15(1)
PCFG14(1)
PCFG13(1)
PCFG12(1)
PCFG11
PCFG10
PCFG9
PCFG8
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7-0
PCFG15:PCFG8: Analog Port Configuration bits (AN15 through AN8)
1= Pin configured as a digital port
0= Pin configured as an analog channel; digital input disabled and reads ‘0’
Note 1: AN15 through AN12 are implemented only on 80-pin devices. For 64-pin devices, the corresponding
PCFGx bits are still implemented for these channels, but have no effect.
© 2009 Microchip Technology Inc.
DS39778D-page 295
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The analog reference voltage is software selectable to
either the device’s positive and negative supply voltage
(AVDD and AVSS), or the voltage level on the
RA3/AN3/VREF+ and RA2/AN2/VREF- pins.
the A/D conversion. When the A/D conversion is com-
plete, the result is loaded into the ADRESH:ADRESL
register pair, the GO/DONE bit (ADCON0<1>) is
cleared and A/D Interrupt Flag bit, ADIF, is set.
The A/D Converter has a unique feature of being able
to operate while the device is in Sleep mode. To
operate in Sleep, the A/D conversion clock must be
derived from the A/D’s internal RC oscillator.
A device Reset forces all registers to their Reset state.
This forces the A/D module to be turned off and any
conversion in progress is aborted. The value in the
ADRESH:ADRESL register pair is not modified for a
Power-on Reset. These registers will contain unknown
data after a Power-on Reset.
The output of the sample and hold is the input into the
converter, which generates the result via successive
approximation.
The block diagram of the A/D module is shown in
Figure 21-1.
Each port pin associated with the A/D Converter can be
configured as an analog input or as a digital I/O. The
ADRESH and ADRESL registers contain the result of
FIGURE 21-1:
A/D BLOCK DIAGRAM
CHS3:CHS0
1111
AN15(1)
1110
AN14(1)
1101
AN13(1)
1100
AN12(1)
1011
AN11
1010
AN10
1001
AN9
1000
AN8
0111
AN7
0110
AN6
0100
AN4
VAIN
0011
(Input Voltage)
10-Bit
A/D
Converter
AN3
0010
AN2
0001
VCFG1:VCFG0
VDD
AN1
0000
(2)
AN0
VREF+
VREF-
Reference
Voltage
(2)
VSS
Note 1: Channels AN15 through AN12 are not available on 64-pin devices.
2: I/O pins have diode protection to VDD and VSS.
DS39778D-page 296
© 2009 Microchip Technology Inc.
PIC18F87J11 FAMILY
After the A/D module has been configured as desired,
the selected channel must be acquired before the
conversion is started. The analog input channels must
have their corresponding TRIS bits selected as an
input. To determine acquisition time, see Section 21.1
“A/D Acquisition Requirements”. After this acquisi-
tion time has elapsed, the A/D conversion can be
started. An acquisition time can be programmed to
occur between setting the GO/DONE bit and the actual
start of the conversion.
2. Configure A/D interrupt (if desired):
• Clear ADIF bit
• Set ADIE bit
• Set GIE bit
3. Wait the required acquisition time (if required).
4. Start conversion:
• Set GO/DONE bit (ADCON0<1>)
5. Wait for A/D conversion to complete, by either:
• Polling for the GO/DONE bit to be cleared
The following steps should be followed to do an A/D
conversion:
OR
• Waiting for the A/D interrupt
1. Configure the A/D module:
6. Read A/D Result registers (ADRESH:ADRESL);
clear bit, ADIF, if required.
• Configure the required ADC pins as analog
pins using ANCON0, ANCON1
7. For next conversion, go to step 1 or step 2, as
required. The A/D conversion time per bit is
defined as TAD. A minimum wait of 2 TAD is
required before next acquisition starts.
• Set voltage reference using ADCON0
• Select A/D input channel (ADCON0)
• Select A/D acquisition time (ADCON1)
• Select A/D conversion clock (ADCON1)
• Turn on A/D module (ADCON0)
FIGURE 21-2:
ANALOG INPUT MODEL
VDD
Sampling
Switch
VT = 0.6V
ANx
SS
RIC ≤ 1k
RSS
RS
CPIN
VAIN
ILEAKAGE
±100 nA
CHOLD = 25 pF
VT = 0.6V
5 pF
VSS
Legend: CPIN
= input capacitance
= threshold voltage
VT
ILEAKAGE = leakage current at the pin due to
various junctions
VDD
RIC
= interconnect resistance
= sampling switch
SS
CHOLD
RSS
= sample/hold capacitance (from DAC)
= sampling switch resistance
1
2
3
4
Sampling Switch (kΩ)
© 2009 Microchip Technology Inc.
DS39778D-page 297
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To calculate the minimum acquisition time,
Equation 21-1 may be used. This equation assumes
that 1/2 LSb error is used (1024 steps for the A/D). The
1/2 LSb error is the maximum error allowed for the A/D
to meet its specified resolution.
21.1 A/D Acquisition Requirements
For the A/D Converter to meet its specified accuracy,
the charge holding capacitor (CHOLD) must be allowed
to fully charge to the input channel voltage level. The
analog input model is shown in Figure 21-2. The
source impedance (RS) and the internal sampling
switch (RSS) impedance directly affect the time
required to charge the capacitor CHOLD. The sampling
switch (RSS) impedance varies over the device voltage
(VDD). The source impedance affects the offset voltage
at the analog input (due to pin leakage current). The
maximum recommended impedance for analog
sources is 2.5 kΩ. After the analog input channel is
selected (changed), the channel must be sampled for
at least the minimum acquisition time before starting a
conversion.
Equation 21-3 shows the calculation of the minimum
required acquisition time, TACQ. This calculation is
based on the following application system
assumptions:
CHOLD
Rs
Conversion Error
VDD
Temperature
=
=
≤
=
=
25 pF
2.5 kΩ
1/2 LSb
3V → Rss = 2 kΩ
85°C (system max.)
Note: When the conversion is started, the
holding capacitor is disconnected from the
input pin.
EQUATION 21-1: ACQUISITION TIME
TACQ
=
=
Amplifier Settling Time + Holding Capacitor Charging Time + Temperature Coefficient
TAMP + TC + TCOFF
EQUATION 21-2: A/D MINIMUM CHARGING TIME
VHOLD
or
TC
=
=
(VREF – (VREF/2048)) • (1 – e(-TC/CHOLD(RIC + RSS + RS))
-(CHOLD)(RIC + RSS + RS) ln(1/2048)
)
EQUATION 21-3: CALCULATING THE MINIMUM REQUIRED ACQUISITION TIME
TACQ
TAMP
TCOFF
=
=
=
TAMP + TC + TCOFF
0.2 μs
(Temp – 25°C)(0.02 μs/°C)
(85°C – 25°C)(0.02 μs/°C)
1.2 μs
Temperature coefficient is only required for temperatures > 25°C. Below 25°C, TCOFF = 0 ms.
TC
=
-(CHOLD)(RIC + RSS + RS) ln(1/2048) μs
-(25 pF) (1 kΩ + 2 kΩ + 2.5 kΩ) ln(0.0004883) μs
1.05 μs
TACQ
=
0.2 μs + 1.05 μs + 1.2 μs
2.45 μs
DS39778D-page 298
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PIC18F87J11 FAMILY
TABLE 21-1: TAD vs. DEVICE OPERATING
FREQUENCIES
21.2 Selecting and Configuring
Automatic Acquisition Time
AD Clock Source (TAD)
Maximum
Device
Frequency
The ADCON1 register allows the user to select an
acquisition time that occurs each time the GO/DONE
bit is set.
Operation
ADCS2:ADCS0
2 TOSC
4 TOSC
8 TOSC
16 TOSC
32 TOSC
64 TOSC
RC(2)
000
100
001
101
010
110
x11
2.86 MHz
5.71 MHz
When the GO/DONE bit is set, sampling is stopped and
a conversion begins. The user is responsible for ensur-
ing the required acquisition time has passed between
selecting the desired input channel and setting the
GO/DONE bit. This occurs when the ACQT2:ACQT0
bits (ADCON1<5:3>) remain in their Reset state (‘000’)
and is compatible with devices that do not offer
programmable acquisition times.
11.43 MHz
22.86 MHz
40.00 MHz
40.00 MHz
1.00 MHz(1)
If desired, the ACQT bits can be set to select a pro-
grammable acquisition time for the A/D module. When
the GO/DONE bit is set, the A/D module continues to
sample the input for the selected acquisition time, then
automatically begins a conversion. Since the acquisi-
tion time is programmed, there may be no need to wait
for an acquisition time between selecting a channel and
setting the GO/DONE bit.
Note 1: The RC source has a typical TAD time of
4 μs.
2: For device frequencies above 1 MHz, the
device must be in Sleep mode for the
entire conversion or the A/D accuracy may
be out of specification.
21.4 Configuring Analog Port Pins
In either case, when the conversion is completed, the
GO/DONE bit is cleared, the ADIF flag is set and the
A/D begins sampling the currently selected channel
again. If an acquisition time is programmed, there is
nothing to indicate if the acquisition time has ended or
if the conversion has begun.
The ANCON0, ANCON1, TRISA, TRISF and TRISH
registers control the operation of the A/D port pins. The
port pins needed as analog inputs must have their cor-
responding TRIS bits set (input). If the TRIS bit is
cleared (output), the digital output level (VOH or VOL)
will be converted.
21.3 Selecting the A/D Conversion
Clock
The A/D operation is independent of the state of the
CHS3:CHS0 bits and the TRIS bits.
The A/D conversion time per bit is defined as TAD. The
A/D conversion requires 11 TAD per 10-bit conversion.
The source of the A/D conversion clock is software
selectable.
Note 1: When reading the PORT register, all pins
configured as analog input channels will
read as cleared (a low level). Pins config-
ured as digital inputs will convert an
analog input. Analog levels on a digitally
configured input will be accurately
converted.
There are seven possible options for TAD:
• 2 TOSC
• 4 TOSC
2: Analog levels on any pin defined as a
digital input may cause the digital input
buffer to consume current out of the
device’s specification limits.
• 8 TOSC
• 16 TOSC
• 32 TOSC
• 64 TOSC
• Internal RC Oscillator
For correct A/D conversions, the A/D conversion clock
(TAD) must be as short as possible but greater than the
minimum TAD (see parameter 130 in Table 27-30 for
more information).
Table 21-1 shows the resultant TAD times derived from
the device operating frequencies and the A/D clock
source selected.
© 2009 Microchip Technology Inc.
DS39778D-page 299
PIC18F87J11 FAMILY
21.5 A/D Conversions
21.6 Use of the ECCP2 Trigger
Figure 21-3 shows the operation of the A/D Converter
after the GO/DONE bit has been set and the
ACQT2:ACQT0 bits are cleared. A conversion is
started after the following instruction to allow entry into
Sleep mode before the conversion begins.
An A/D conversion can be started by the “Special Event
Trigger” of the ECCP2 module. This requires that the
CCP2M3:CCP2M0
bits
(CCP2CON<3:0>)
be
programmed as ‘1011’ and that the A/D module is
enabled (ADON bit is set). When the trigger occurs, the
GO/DONE bit will be set, starting the A/D acquisition
and conversion, and the Timer1 (or Timer3) counter will
be reset to zero. Timer1 (or Timer3) is reset to auto-
matically repeat the A/D acquisition period with minimal
software overhead (moving ADRESH/ADRESL to the
desired location). The appropriate analog input
channel must be selected and the minimum acquisition
period is either timed by the user, or an appropriate
TACQ time is selected before the Special Event Trigger
sets the GO/DONE bit (starts a conversion).
Figure 21-4 shows the operation of the A/D Converter
after the GO/DONE bit has been set, the
ACQT2:ACQT0 bits are set to ‘010’ and selecting a
4 TAD acquisition time before the conversion starts.
Clearing the GO/DONE bit during a conversion will
abort the current conversion. The A/D Result register
pair will NOT be updated with the partially completed
A/D
conversion
sample.
This
means
the
ADRESH:ADRESL registers will continue to contain
the value of the last completed conversion (or the last
value written to the ADRESH:ADRESL registers).
If the A/D module is not enabled (ADON is cleared), the
Special Event Trigger will be ignored by the A/D module
but will still reset the Timer1 (or Timer3) counter.
After the A/D conversion is completed or aborted, a
2 TAD wait is required before the next acquisition can be
started. After this wait, acquisition on the selected
channel is automatically started.
Note: The GO/DONE bit should NOT be set in
the same instruction that turns on the A/D.
FIGURE 21-3:
A/D CONVERSION TAD CYCLES (ACQT2:ACQT0 = 000, TACQ = 0)
TCY - TAD
TAD8 TAD9 TAD10 TAD11
TAD1 TAD2 TAD3 TAD4 TAD5 TAD6 TAD7
b4
b1
b0
b9
b8
b7
b6
b5
b3
b2
Conversion starts
Holding capacitor is disconnected from analog input (typically 100 ns)
Set GO/DONE bit
Next Q4: ADRESH/ADRESL is loaded, GO/DONE bit is cleared,
ADIF bit is set, holding capacitor is connected to analog input.
FIGURE 21-4:
A/D CONVERSION TAD CYCLES (ACQT2:ACQT0 = 010, TACQ = 4 TAD)
TAD Cycles
TACQT Cycles
7
8
9
10
b1
11
b0
1
2
3
4
1
2
3
4
5
6
b7
b6
b3
b2
b8
b5
b4
b9
Automatic
Acquisition
Time
Conversion starts
(Holding capacitor is disconnected)
Set GO/DONE bit
(Holding capacitor continues
acquiring input)
Next Q4: ADRESH:ADRESL is loaded, GO/DONE bit is cleared,
ADIF bit is set, holding capacitor is reconnected to analog input.
DS39778D-page 300
© 2009 Microchip Technology Inc.
PIC18F87J11 FAMILY
If the A/D is expected to operate while the device is in
a power-managed mode, the ACQT2:ACQT0 and
ADCS2:ADCS0 bits in ADCON1 should be updated in
accordance with the power-managed mode clock that
will be used. After the power-managed mode is entered
(either of the power-managed Run modes), an A/D
acquisition or conversion may be started. Once an
acquisition or conversion is started, the device should
continue to be clocked by the same power-managed
mode clock source until the conversion has been com-
pleted. If desired, the device may be placed into the
corresponding power-managed Idle mode during the
conversion.
21.7 A/D Converter Calibration
The A/D Converter in the PIC18F87J11 family of
devices includes a self-calibration feature which com-
pensates for any offset generated within the module.
The calibration process is automated and is initiated by
setting the ADCAL bit (ADCON1<6>). The next time
the GO/DONE bit is set, the module will perform a
“dummy” conversion (that is, with reading none of the
input channels) and store the resulting value internally
to compensate for the offset. Thus, subsequent offsets
will be compensated. An example of a calibration
routine is shown in Example 21-1.
The calibration process assumes that the device is in a
relatively steady-state operating condition. If A/D
calibration is used, it should be performed after each
device Reset or if there are other major changes in
operating conditions.
If the power-managed mode clock frequency is less
than 1 MHz, the A/D RC clock source should be
selected.
Operation in the Sleep mode requires the A/D RC clock
to be selected. If bits, ACQT2:ACQT0, are set to ‘000’
and a conversion is started, the conversion will be
delayed one instruction cycle to allow execution of the
SLEEPinstruction and entry to Sleep mode. The IDLEN
and SCS bits in the OSCCON register must have
already been cleared prior to starting the conversion.
21.8 Operation in Power-Managed
Modes
The selection of the automatic acquisition time and A/D
conversion clock is determined in part by the clock
source and frequency while in a power-managed
mode.
EXAMPLE 21-1:
SAMPLE A/D CALIBRATION ROUTINE
BSF
BCF
BCF
BSF
BSF
WDTCON,ADSHR
ANCON0,PCFG0
WDTCON,ADSHR
ADCON0,ADON
ADCON1,ADCAL
ADCON0,GO
;Enable write/read to the shared SFR
;Make Channel 0 analog
;Disable write/read to the shared SFR
;Enable A/D module
;Enable Calibration
;Start a dummy A/D conversion
;
;Wait for the dummy conversion to finish
;
;Calibration done, turn off calibration enable
;Proceed with the actual A/D conversion
BSF
CALIBRATION
BTFSC
BRA
ADCON0,GO
CALIBRATION
ADCON1,ADCAL
BCF
© 2009 Microchip Technology Inc.
DS39778D-page 301
PIC18F87J11 FAMILY
TABLE 21-2: SUMMARY OF A/D REGISTERS
Reset
Values
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
on Page:
INTCON
PIR1
GIE/GIEH PEIE/GIEL TMR0IE
INT0IE
TX1IF
TX1IE
TX1IP
—
RBIE
TMR0IF
CCP1IF
CCP1IE
CCP1IP
LVDIF
INT0IF
TMR2IF
TMR2IE
TMR2IP
TMR3IF
TMR3IE
TMR3IP
RBIF
57
60
60
60
60
60
60
59
59
59
59
59
59
59
61
60
61
60
61
60
PMPIF
PMPIE
ADIF
ADIE
RC1IF
RC1IE
RC1IP
CM1IF
CM1IE
CM1IP
SSP1IF
SSP1IE
SSP1IP
BCL1IF
BCL1IE
BCL1IP
TMR1IF
TMR1IE
TMR1IP
CCP2IF
CCP2IE
CCP2IP
PIE1
IPR1
PMPIP
ADIP
PIR2
OSCFIF
OSCFIE
OSCFIP
CM2IF
CM2IE
CM2IP
PIE2
—
LVDIE
IPR2
—
LVDIP
ADRESH
ADRESL
ADCON0(2)
ANCON0(3)
ADCON1(2)
A/D Result Register High Byte
A/D Result Register Low Byte
VCFG1
PCFG7
ADFM
VCFG0
PCFG6
ADCAL
CHS3
—
CHS3
PCFG4
ACQT1
CHS1
PCFG3
ACQT0
CHS0 GO/DONE ADON
PCFG2
ADCS2
PCFG1
ADCS1
PCFG9
PCFG0
ADCS0
PCFG8
ACQT2
ANCON1(3) PCFG15 PCFG14 PCFG13 PCFG12 PCFG11 PCFG10
CCP2CON
PORTA
TRISA
P2M1
RA7(4)
P2M0
RA6(4)
DC2B1
RA5
DC2B0
RA4
CCP2M3 CCP2M2 CCP2M1 CCP2M0
RA3
TRISA3
RF3
RA2
TRISA2
RF2
RA1
TRISA1
RF1
RA0
TRISA0
—
TRISA7(4) TRISA6(4) TRISA5
TRISA4
RF4
PORTF
TRISF
PORTH(1)
TRISH(1)
RF7
TRISF7
RH7
RF6
TRISF6
RH6
RF5
TRISF5
RH5
TRISF4
RH4
TRISF3
RH3
TRISF2
RH2
TRISF1
RH1
—
RH0
TRISH7
TRISH6
TRISH5
TRISH4
TRISH3
TRISH2
TRISH1
TRISH0
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used for A/D conversion.
Note 1: This register is not implemented on 64-pin devices.
2: Default (legacy) SFR at this address, available when WDTCON<4> = 0.
3: Configuration SFR, overlaps with default SFR at this address; available only when WDTCON<4> = 1.
4: These bits are only available in select oscillator modes (FOSC2 Configuration bit = 0); otherwise, they are
unimplemented.
DS39778D-page 302
© 2009 Microchip Technology Inc.
PIC18F87J11 FAMILY
22.1 Registers
22.0 COMPARATOR MODULE
The CMxCON registers (Register 22-1) select the input
and output configuration for each comparator, as well
as the settings for interrupt generation.
The analog comparator module contains two compara-
tors that can be independently configured in a variety of
ways. The inputs can be selected from the analog
inputs and two internal voltage references. The digital
outputs are available at the pin level and can also be
read through the control register. Multiple output and
interrupt event generation are also available. A generic
single comparator from the module is shown in
Figure 22-1.
The CMSTAT register (Register 22-2) provides the out-
put results of the comparators. The bits in this register
are read-only.
Key features of the module includes:
• Independent comparator control
• Programmable input configuration
• Output to both pin and register levels
• Programmable output polarity
• Independent interrupt generation for each
comparator with configurable interrupt-on-change
FIGURE 22-1:
COMPARATOR SIMPLIFIED BLOCK DIAGRAM
COUTx
(CMSTAT<1:0>)
CCH1:CCH0
0
1
2
3
CxINB
CxINC
CxIND
VIRV
(1)
Interrupt
CMxIF
Logic
(1,2)
EVPOL<4:3>
COE
CREF
VIN-
CxOUT
-
Polarity
Logic
0
1
CxINA
CVREF
Cx
VIN+
CON
CPOL
Note 1: Available in 80-pin devices only.
2: Implemented in Comparator 2 only.
© 2009 Microchip Technology Inc.
DS39778D-page 303
PIC18F87J11 FAMILY
REGISTER 22-1: CMxCON: COMPARATORx CONTROL REGISTER
R/W-0
CON
R/W-0
COE
R/W-0
CPOL
R/W-1
R/W-1
R/W-1
CREF
R/W-1
CCH1
R/W-1
CCH0
EVPOL1
EVPOL0
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7
CON: Comparator Enable bit
1= Comparator is enabled
0= Comparator is disabled
bit 6
COE: Comparator Output Enable bit
1= Comparator output is present on the CxOUT pin
0= Comparator output is internal only
bit 5
CPOL: Comparator Output Polarity Select bit
1= Comparator output is inverted
0= Comparator output is not inverted
bit 4-3
EVPOL1:EVPOL0: Interrupt Polarity Select bits
11= Interrupt generation on any change of the output(1)
10= Interrupt generation only on high-to-low transition of the output
01= Interrupt generation only on low-to-high transition of the output
00= Interrupt generation is disabled
bit 2
CREF: Comparator Reference Select bit (non-inverting input)
1= Non-inverting input connects to internal CVREF voltage
0= Non-inverting input connects to CxINA pin
bit 1-0
CCH1:CCH0: Comparator Channel Select bits
11= Inverting input of comparator connects to VIRV
10= Inverting input of comparator connects to CxIND pin(2)
01= Inverting input of comparator connects to CxINC pin(2)
00= Inverting input of comparator connects to CxINB pin
Note 1: The CMxIF is automatically set any time this mode is selected and must be cleared by the application after
the initial configuration.
2: Available in 80-pin devices only.
DS39778D-page 304
© 2009 Microchip Technology Inc.
PIC18F87J11 FAMILY
REGISTER 22-2: CMSTAT: COMPARATOR OUTPUT STATUS REGISTER
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
R-1
R-1
COUT2
COUT1
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7-2
bit 1-0
Unimplemented: Read as ‘0’
COUT2:COUT1: Comparator x Status bits
If CPOL = 0 (non-inverted polarity):
1= Comparator’s VIN+ > VIN-
0= Comparator’s VIN+ < VIN-
If CPOL = 1 (inverted polarity):
1= Comparator VIN+ < VIN-
0= Comparator VIN+ > VIN-
© 2009 Microchip Technology Inc.
DS39778D-page 305
PIC18F87J11 FAMILY
22.2 Comparator Operation
22.3 Comparator Response Time
A single comparator is shown in Figure 22-2, along with
the relationship between the analog input levels and
the digital output. When the analog input at VIN+ is less
than the analog input VIN-, the output of the comparator
is a digital low level. When the analog input at VIN+ is
greater than the analog input VIN-, the output of the
comparator is a digital high level. The shaded areas of
the output of the comparator in Figure 22-2 represent
the uncertainty due to input offsets and response time.
Response time is the minimum time, after selecting a
new reference voltage or input source, before the com-
parator output has a valid level. The response time of
the comparator differs from the settling time of the volt-
age reference. Therefore, both of these times must be
considered when determining the total response to a
comparator input change. Otherwise, the maximum
delay of the comparators should be used (see
Section 27.0 “Electrical Characteristics”).
22.4 Analog Input Connection
Considerations
FIGURE 22-2:
SINGLE COMPARATOR
VIN+
VIN-
A simplified circuit for an analog input is shown in
Figure 22-3. Since the analog pins are connected to a
digital output, they have reverse biased diodes to VDD
and VSS. The analog input, therefore, must be between
VSS and VDD. If the input voltage deviates from this
range by more than 0.6V in either direction, one of the
diodes is forward biased and a latch-up condition may
occur. A maximum source impedance of 10 kΩ is
recommended for the analog sources. Any external
component connected to an analog input pin, such as
a capacitor or a Zener diode, should have very little
leakage current.
+
Output
–
VIN-
VIN+
Output
FIGURE 22-3:
COMPARATOR ANALOG INPUT MODEL
VDD
VT = 0.6V
RIC
RS < 10k
AIN
Comparator
Input
ILEAKAGE
±500 nA
CPIN
5 pF
VA
VT = 0.6V
VSS
Legend: CPIN
=
=
Input Capacitance
Threshold Voltage
VT
ILEAKAGE = Leakage Current at the pin due to various junctions
RIC
RS
VA
=
=
=
Interconnect Resistance
Source Impedance
Analog Voltage
DS39778D-page 306
© 2009 Microchip Technology Inc.
PIC18F87J11 FAMILY
The comparator module also allows the selection of an
internally generated voltage reference (CVREF) from
the comparator voltage reference module. This module
is described in more detail in Section 23.0 “Compara-
tor Voltage Reference Module”. The reference from
the Comparator Voltage Reference module is only
available when CREF = 1. In this mode, the internal
voltage reference is applied to the comparator’s VIN+
pin.
22.5 Comparator Control and
Configuration
Each comparator has up to eight possible combina-
tions of inputs: up to four external analog inputs, and
one of two internal voltage references.
Both comparators allow a selection of the signal from
pin, CxINA, or the voltage from the comparator refer-
ence (CVREF) on the non-inverting channel. This is
compared to either CxINB, CxINC, CxIND or the micro-
controller’s fixed internal reference voltage (VIRV, 1.2V
nominal) on the inverting channel. The comparator
inputs and outputs are tied to fixed I/O pins, defined in
Table 22-1. The available configurations and their
corresponding bit settings are shown in Figure 22-1.
Note:
The comparator input pin selected by
CCH1:CH0 must be configured as an input
by setting both the corresponding TRISF or
TRISH bit, and the corresponding PCFG bit
in the ANCON1 register.
22.5.1.1
Comparator Configurations in 64-Pin
and 80-Pin Devices
TABLE 22-1: COMPARATOR INPUTS AND
OUTPUTS
In PIC18F87J11 family devices, the C and D input chan-
nels for both comparators are linked to pins in PORTH
and cannot be reassigned to alternate analog inputs.
Because of this, 64-pin devices offer a total of 4 different
configurations for each comparator. In contrast, 80-pin
devices offer a choice of 6 configurations for Comparator
1, and 8 configurations for Comparator 2. The configura-
tions shown in Figure 22-1 are footnoted to indicate
where they are not available.
Comparator
Input or Output
I/O Pin
C1INA (VIN+)
C1INB (VIN-)
C1INC (VIN-)(1)
C1OUT
RF6
RF5
RH6(1)
1
RF2
C2INA(VIN+)
C2INB(VIN-)
C2INC(VIN-)(1)
C2IND(VIN-)(1)
C2OUT
RF4
RF3
2
RH4(1)
RH5(1)
RF1
22.5.2
COMPARATOR ENABLE AND
OUTPUT SELECTION
The comparator outputs are read through the CMSTAT
register. The CMSTAT<0> reads the Comparator 1 out-
put and CMSTAT<1> reads the Comparator 2 output.
These bits are read-only.
Note 1: Available in 80-pin devices only.
22.5.1
COMPARATOR ENABLE AND
INPUT SELECTION
The comparator outputs may also be directly output to
the RF1 and RF2 I/O pins by setting the COE bit
(CMxCON<6>). When enabled, multiplexors in the
output path of the pins switch to the output of the com-
parator. The TRISF<1:2> bits still function as the digital
output enable for the RF1 and RF2 pins while in this
mode.
Setting the CON bit of the CMxCON register
(CMxCON<7>) enables the comparator for operation.
Clearing the CON bit disables the comparator resulting
in minimum current consumption.
The CCH1:CCH0 bits in the CMxCON register
(CMxCON<1:0>) direct either one of three analog input
pins, or the Internal Reference Voltage (VIRV), to the
comparator VIN-. Depending on the comparator operat-
ing mode, either an external or internal voltage
reference may be used. The analog signal present at
VIN- is compared to the signal at VIN+ and the digital
output of the comparator is adjusted accordingly.
By default, the comparator’s output is at logic high
whenever the voltage on VIN+ is greater than on VIN-.
The polarity of the comparator outputs can be inverted
using the CPOL bit (CMxCON<5>).
The uncertainty of each of the comparators is related to
the input offset voltage and the response time given in
the specifications, as discussed in Section 22.2
“Comparator Operation”.
The external reference is used when CREF = 0
(CMxCON<2>) and VIN+ is connected to the CxINA
pin. When external voltage references are used, the
comparator module can be configured to have the ref-
erence sources externally. The reference signal must
be between VSS and VDD, and can be applied to either
pin of the comparator.
© 2009 Microchip Technology Inc.
DS39778D-page 307
PIC18F87J11 FAMILY
FIGURE 22-4:
COMPARATOR I/O CONFIGURATIONS
Comparator Off
CON = 0, CREF = x, CCH1:CCH0 = xx
COE
VIN-
-
Cx
VIN+
Off (Read as ‘0’)
CxOUT
pin
(1)
Comparator CxINB > CxINA Compare
Comparator CxINC > CxINA Compare
CON = 1, CREF = 0, CCH1:CCH0 = 00
CON = 1, CREF = 0, CCH1:CCH0 = 01
COE
COE
VIN-
VIN-
CxINB
-
CxINC
CxINA
-
Cx
Cx
VIN+
VIN+
CxINA
CxOUT
pin
CxOUT
pin
(1,2)
Comparator CxIND > CxINA Compare
Comparator VIRV > CxINA Compare
CON = 1, CREF = 0, CCH1:CCH0 = 10
CON = 1, CREF = 0, CCH1:CCH0 = 11
COE
COE
VIN-
VIN-
CxIND
-
VIRV
-
Cx
Cx
VIN+
VIN+
CxINA
CxINA
CxOUT
pin
CxOUT
pin
(1)
Comparator CxINB > CVREF Compare
Comparator CxINC > CVREF Compare
CON = 1, CREF = 1, CCH1:CCH0 = 00
CON = 1, CREF = 1, CCH1:CCH0 = 01
COE
COE
VIN-
VIN-
CxINB
CVREF
CxINC
CVREF
-
-
Cx
Cx
VIN+
VIN+
CxOUT
pin
CxOUT
pin
(1,2)
Comparator CxIND > CVREF Compare
Comparator VIRV > CVREF Compare
CON = 1, CREF = 1, CCH1:CCH0 = 10
CON = 1, CREF = 1, CCH1:CCH0 = 11
COE
COE
VIN-
VIN-
CxIND
CVREF
VIRV
CVREF
-
-
Cx
Cx
VIN+
VIN+
CxOUT
pin
CxOUT
pin
Legend:
VIRV = Fixed Interval Reference Voltage (1.2V nominal), CVREF = Comparator Voltage Reference module output.
Configurations are available on both Comparators 1 and 2 in all package sizes unless otherwise noted.
Note 1: Configuration is available in 80-pin devices only.
2: Configuration is available in Comparator 2 only (80-pin devices).
DS39778D-page 308
© 2009 Microchip Technology Inc.
PIC18F87J11 FAMILY
transition of the comparator output. Once the interrupt
is generated, it is required to clear the interrupt flag by
software.
22.6 Comparator Interrupts
The comparator interrupt flag is set whenever any of
the following occurs:
When EVPOL<1:0> = 11, the comparator interrupt flag
is set whenever there is a change in the output value of
either comparator. Software will need to maintain infor-
mation about the status of the output bits, as read from
CMSTAT<1:0>, to determine the actual change that
occurred. The CMxIF bits (PIR2<6:5>) are the Compar-
ator Interrupt Flags. The CMxIF bits must be reset by
clearing them. Since it is also possible to write a ‘1’ to
this register, a simulated interrupt may be initiated.
Table 22-2 shows the interrupt generation with respect
to comparator input voltages and EVPOL bit settings.
• Low-to-high transition of the comparator output
• High-to-low transition of the comparator output
• Any change in the comparator output
The comparator interrupt selection is done by the
EVPOL1:EVPOL0 bits in the CMxCON register
(CMxCON<4:3>).
In order to provide maximum flexibility, the output of the
comparator may be inverted using the CPOL bit in the
CMxCON register (CMxCON<5>). This is functionally
identical to reversing the inverting and non-inverting
inputs of the comparator for a particular mode.
Both the CMxIE bits (PIE2<6:5>) and the PEIE bit (INT-
CON<6>) must be set to enable the interrupt. In addi-
tion, the GIE bit (INTCON<7>) must also be set. If any
of these bits are clear, the interrupt is not enabled,
though the CMxIF bits will still be set if an interrupt
condition occurs.
An interrupt is generated on the low-to-high or high-to-
low transition of the comparator output. This mode of
interrupt generation is dependent on EVPOL<1:0> in
the CMxCON register. If EVPOL<1:0> = 01or 10, the
interrupt is generated on a low-to-high or high-to-low
TABLE 22-2: COMPARATOR INTERRUPT GENERATION
Comparator
Interrupt
Generated
CPOL
EVPOL<1:0>
COUTx Transition
Input Change
VIN+ > VIN-
VIN+ < VIN-
VIN+ > VIN-
VIN+ < VIN-
VIN+ > VIN-
VIN+ < VIN-
VIN+ > VIN-
VIN+ < VIN-
VIN+ > VIN-
VIN+ < VIN-
VIN+ > VIN-
VIN+ < VIN-
VIN+ > VIN-
VIN+ < VIN-
VIN+ > VIN-
VIN+ < VIN-
Low-to-High
High-to-Low
Low-to-High
High-to-Low
Low-to-High
High-to-Low
Low-to-High
High-to-Low
High-to-Low
Low-to-High
High-to-Low
Low-to-High
High-to-Low
Low-to-High
High-to-Low
Low-to-High
No
No
00
01
10
11
00
01
10
11
Yes
No
0
No
Yes
Yes
Yes
No
No
No
Yes
Yes
No
1
Yes
Yes
© 2009 Microchip Technology Inc.
DS39778D-page 309
PIC18F87J11 FAMILY
22.7 Comparator Operation
During Sleep
22.8 Effects of a Reset
A device Reset forces the CMxCON registers to their
Reset state. This forces both comparators and the
voltage reference to the OFF state.
When a comparator is active and the device is placed
in Sleep mode, the comparator remains active and the
interrupt is functional if enabled. This interrupt will
wake-up the device from Sleep mode when enabled.
Each operational comparator will consume additional
current. To minimize power consumption while in Sleep
mode, turn off the comparators (CON = 0) before
entering Sleep. If the device wakes up from Sleep, the
contents of the CMxCON register are not affected.
TABLE 22-3: REGISTERS ASSOCIATED WITH COMPARATOR MODULE
Reset
Values
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
on Page:
INTCON
PIR2
GIE/GIEH PEIE/GIEL TMR0IE
INT0IE
—
RBIE
TMR0IF
LVDIF
LVDIE
LVDIP
CREF
CREF
—
INT0IF
TMR3IF
TMR3IE
TMR3IP
CCH1
RBIF
CCP2IF
CCP2IE
CCP2IP
CCH0
CCH0
COUT1
CVR0
PCFG8
PCFG0
—
57
60
60
60
58
58
58
61
59
59
61
60
60
61
60
OSCFIF
OSCFIE
OSCFIP
CON
CM2IF
CM2IE
CM2IP
COE
CM1IF
CM1IE
CM1IP
CPOL
CPOL
—
BCL1IF
BCL1IE
BCL1IP
PIE2
—
IPR2
—
CM1CON
CM2CON
CMSTAT
EVPOL1 EVPOL0
EVPOL1 EVPOL0
CON
COE
CCH1
—
—
—
—
COUT2
CVR1
CVRCON(2) CVREN
ANCON1(2) PCFG15 PCFG14 PCFG13 PCFG12 PCFG11 PCFG10
ANCON0(2) PCFG7
CVROE
CVRR
CVRSS
CVR3
CVR2
PCFG9
PCFG1
RF1
PCFG6
RF6
—
PCFG4
RF4
PCFG3
RF3
PCFG2
RF2
PORTF
LATF
RF7
LATF7
TRISF7
RH7
RF5
LATF6
TRISF6
RH6
LATF5
TRISF5
RH5
LATF4
TRISF4
RH4
LATF3
TRISF3
RH3
LATF2
TRISF2
RH2
LATF1
TRISF1
RH1
—
TRISF
—
PORTH(1)
TRISH(1)
RH0
TRISH7
TRISH6
TRISH5
TRISH4
TRISH3
TRISH2
TRISH1
TRISH0
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used for A/D conversion.
Note 1: These registers are not implemented on 64-pin devices.
2: Configuration SFR, overlaps with default SFR at this address; available only when WDTCON<4> = 1.
DS39778D-page 310
© 2009 Microchip Technology Inc.
PIC18F87J11 FAMILY
A block diagram of the module is shown in Figure 23-1.
The resistor ladder is segmented to provide two ranges
of CVREF values and has a power-down function to
conserve power when the reference is not being used.
The module’s supply reference can be provided from
either device VDD/VSS or an external voltage reference.
23.0 COMPARATOR VOLTAGE
REFERENCE MODULE
The comparator voltage reference is a 16-tap resistor
ladder network that provides a selectable reference
voltage. Although its primary purpose is to provide a
reference for the analog comparators, it may also be
used independently of them.
FIGURE 23-1:
COMPARATOR VOLTAGE REFERENCE BLOCK DIAGRAM
CVRSS = 1
CVRSS = 0
VREF+
VDD
8R
R
CVR3:CVR0
CVREN
R
R
R
16 Steps
CVREF
R
R
R
CVRR
VREF-
8R
CVRSS = 1
CVRSS = 0
© 2009 Microchip Technology Inc.
DS39778D-page 311
PIC18F87J11 FAMILY
The comparator reference supply voltage can come
from either VDD and VSS, or the external VREF+ and
VREF- that are multiplexed with RA2 and RA3. The
voltage source is selected by the CVRSS bit
(CVRCON<4>).
23.1 Configuring the Comparator
Voltage Reference
The comparator voltage reference module is controlled
through the CVRCON register (Register 23-1). The
comparator voltage reference provides two ranges of
output voltage, each with 16 distinct levels. The range
to be used is selected by the CVRR bit (CVRCON<5>).
The primary difference between the ranges is the size
of the steps selected by the CVREF Selection bits
(CVR3:CVR0), with one range offering finer resolution.
The equations used to calculate the output of the
comparator voltage reference are as follows:
The settling time of the comparator voltage reference
must be considered when changing the CVREF
output (see Table 27-3 in Section 27.0 “Electrical
Characteristics”).
The CVRCON register is a shared address SFR and
uses the same address as the PR4 register. The
CVRCON register is accessed by setting the ADSHR
bit (WDTCON<4>).
If CVRR = 1:
CVREF = ((CVR3:CVR0)/24) x (CVRSRC)
If CVRR = 0:
CVREF = (CVRSRC/4) + ((CVR3:CVR0)/32) x
(CVRSRC)
REGISTER 23-1: CVRCON: COMPARATOR VOLTAGE REFERENCE CONTROL REGISTER
R/W-0
R/W-0
CVROE(1)
R/W-0
CVRR
R/W-0
R/W-0
CVR3
R/W-0
CVR2
R/W-0
CVR1
R/W-0
CVR0
CVREN
CVRSS
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7
bit 6
CVREN: Comparator Voltage Reference Enable bit
1= CVREF circuit powered on
0= CVREF circuit powered down
CVROE: Comparator VREF Output Enable bit(1)
1= CVREF voltage level is also output on the RF5/AN10/C1INB/CVREF pin
0= CVREF voltage is disconnected from the RF5/AN10/C1INB/CVREF pin
bit 5
CVRR: Comparator VREF Range Selection bit
1= 0 to 0.667 CVRSRC, with CVRSRC/24 step size (low range)
0= 0.25 CVRSRC to 0.75 CVRSRC, with CVRSRC/32 step size (high range)
bit 4
CVRSS: Comparator VREF Source Selection bit
1= Comparator reference source, CVRSRC = (VREF+) – (VREF-)
0= Comparator reference source, CVRSRC = AVDD – AVSS
bit 3-0
CVR3:CVR0: Comparator VREF Value Selection bits (0 ≤ (CVR3:CVR0) ≤ 15)
When CVRR = 1:
CVREF = ((CVR3:CVR0)/24) • (CVRSRC)
When CVRR = 0:
CVREF = (CVRSRC/4) + ((CVR3:CVR0)/32) • (CVRSRC)
Note 1: CVROE overrides the TRISF<5> bit setting.
DS39778D-page 312
© 2009 Microchip Technology Inc.
PIC18F87J11 FAMILY
The RF5 pin can be used as a simple D/A output with
limited drive capability. Due to the limited current drive
capability, a buffer must be used on the voltage
reference output for external connections to VREF.
Figure 23-2 shows an example buffering technique.
23.2 Voltage Reference Accuracy/Error
The full range of voltage reference cannot be realized
due to the construction of the module. The transistors
on the top and bottom of the resistor ladder network
(Figure 23-1) keep CVREF from approaching the refer-
ence source rails. The voltage reference is derived
from the reference source; therefore, the CVREF output
changes with fluctuations in that source. The tested
absolute accuracy of the voltage reference can be
found in Section 27.0 “Electrical Characteristics”.
23.4 Operation During Sleep
When the device wakes up from Sleep through an
interrupt or a Watchdog Timer time-out, the contents of
the CVRCON register are not affected. To minimize
current consumption in Sleep mode, the voltage
reference should be disabled.
23.3 Connection Considerations
The voltage reference module operates independently
of the comparator module. The output of the reference
generator may be connected to the RF5 pin if the
CVROE bit is set. Enabling the voltage reference out-
put onto RA2 when it is configured as a digital input will
increase current consumption. Connecting RF5 as a
digital output with CVRSS enabled will also increase
current consumption.
23.5 Effects of a Reset
A device Reset disables the voltage reference by
clearing CVREN (CVRCON<7>). This Reset also
disconnects the reference from the RA2 pin by clearing
CVROE, and selects the high-voltage range by clearing
CVRR. The CVR value select bits are also cleared.
FIGURE 23-2:
COMPARATOR VOLTAGE REFERENCE OUTPUT BUFFER EXAMPLE
PIC18F87J11
CVREF
Module
(1)
R
+
–
CVREF Output
RF5
Voltage
Reference
Output
Impedance
Note 1: R is dependent upon the comparator voltage reference configuration bits, CVRCON<5> and CVRCON<3:0>.
TABLE 23-1: REGISTERS ASSOCIATED WITH COMPARATOR VOLTAGE REFERENCE
Reset
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Values
on Page:
CVRCON(2)
CM1CON
CM2CON
TRISA
CVREN
CON
CVROE
COE
CVRR
CVRSS
CVR3
CVR2
CREF
CVR1
CCH1
CVR0
CCH0
CCH0
TRISA0
—
61
58
58
60
60
59
59
CPOL EVPOL1 EVPOL0
CON
COE
CPOL EVPOL1 EVPOL0
CREF
CCH1
TRISA7(1) TRISA6(1) TRISA5 TRISA4 TRISA3
TRISA2
TRISF2
PCFG2
TRISA1
TRISF1
PCFG1
PCFG9
TRISF
TRISF7
PCFG7
TRISF6
PCFG6
TRISF5 TRISF4
PCFG4
TRISF3
PCFG3
ANCON0(2)
ANCON1(2)
—
PCFG0
PCFG8
PCFG15 PCFG14 PCFG13 PCFG12 PCFG11 PCFG10
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used with the comparator voltage reference.
Note 1: These bits are only available in select oscillator modes (FOSC2 Configuration bit = 0); otherwise, they are
unimplemented.
2: Configuration SFR, overlaps with default SFR at this address; available only when WDTCON<4> = 1.
© 2009 Microchip Technology Inc.
DS39778D-page 313
PIC18F87J11 FAMILY
NOTES:
DS39778D-page 314
© 2009 Microchip Technology Inc.
PIC18F87J11 FAMILY
24.1.1
CONSIDERATIONS FOR
CONFIGURING THE PIC18F87J11
FAMILY DEVICES
24.0 SPECIAL FEATURES OF THE
CPU
PIC18F87J11 Family devices include several features
intended to maximize reliability and minimize cost
through elimination of external components. These are:
Unlike previous PIC18 microcontrollers, devices of the
PIC18F87J11 Family do not use persistent memory
registers to store configuration information. The config-
uration bytes are implemented as volatile memory
which means that configuration data must be
programmed each time the device is powered up.
• Oscillator Selection
• Resets:
- Power-on Reset (POR)
- Power-up Timer (PWRT)
- Oscillator Start-up Timer (OST)
- Brown-out Reset (BOR)
• Interrupts
Configuration data is stored in the four words at the top
of the on-chip program memory space, known as the
Flash Configuration Words. It is stored in program
memory in the same order shown in Table 24-2, with
CONFIG1L at the lowest address and CONFIG3H at
the highest. The data is automatically loaded in the
proper Configuration registers during device power-up.
• Watchdog Timer (WDT)
• Fail-Safe Clock Monitor
• Two-Speed Start-up
• Code Protection
When creating applications for these devices, users
should always specifically allocate the location of the
Flash Configuration Word for configuration data. This is
to make certain that program code is not stored in this
address when the code is compiled.
• In-Circuit Serial Programming
The oscillator can be configured for the application
depending on frequency, power, accuracy and cost. All
of the options are discussed in detail in Section 2.0
“Oscillator Configurations”.
The volatile memory cells used for the Configuration
bits always reset to ‘1’ on Power-on Resets. For all
other type of Reset events, the previously programmed
values are maintained and used without reloading from
program memory.
A complete discussion of device Resets and interrupts
is available in previous sections of this data sheet. In
addition to their Power-up and Oscillator Start-up
Timers provided for Resets, the PIC18F87J11 Family
of devices have a configurable Watchdog Timer which
is controlled in software.
The four Most Significant bits of CONFIG1H,
CONFIG2H and CONFIG3H in program memory
should also be ‘1111’. This makes these Configuration
Words appear to be NOP instructions in the remote
event that their locations are ever executed by
accident. Since Configuration bits are not implemented
in the corresponding locations, writing ‘1’s to these
locations has no effect on device operation.
The inclusion of an internal RC oscillator also provides
the additional benefits of a Fail-Safe Clock Monitor
(FSCM) and Two-Speed Start-up. FSCM provides for
background monitoring of the peripheral clock and
automatic switchover in the event of its failure.
Two-Speed Start-up enables code to be executed
almost immediately on start-up, while the primary clock
source completes its start-up delays.
To prevent inadvertent configuration changes during
code execution, all programmable Configuration bits
are write-once. After a bit is initially programmed during
a power cycle, it cannot be written to again. Changing
a device configuration requires that power to the device
be cycled.
All of these features are enabled and configured by
setting the appropriate Configuration register bits.
24.1 Configuration Bits
The Configuration bits can be programmed (read as
‘0’) or left unprogrammed (read as ‘1’) to select various
device configurations. These bits are mapped starting
at program memory location 300000h. A complete list
is shown in Table 24-2. A detailed explanation of the
various bit functions is provided in Register 24-1
through Register 24-6.
© 2009 Microchip Technology Inc.
DS39778D-page 315
PIC18F87J11 FAMILY
TABLE 24-1: MAPPING OF THE FLASH CONFIGURATION WORDS TO THE
CONFIGURATION REGISTERS
Configuration Register
Address
Configuration Byte
Code Space Address
CONFIG1L
CONFIG1H
CONFIG2L
CONFIG2H
CONFIG3L
CONFIG3H
XXXF8h
XXXF9h
XXXFAh
XXXFBh
XXXFCh
XXXFDh
XXXFEh
XXXFFh
300000h
300001h
300002h
300003h
300004h
300005h
300006h
300007h
(1)
CONFIG4L
(1)
CONFIG4H
Note 1: Unimplemented in PIC18F87J11 Family devices.
TABLE 24-2: CONFIGURATION BITS AND DEVICE IDs
Default/
File Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Unprogrammed
(1)
Value
300000h CONFIG1L DEBUG XINST STVREN
—
—
—
—
—
—
—
WDTEN 111- ---1
(2)
(2)
(2)
(2)
300001h CONFIG1H
300002h CONFIG2L
300003h CONFIG2H
—
—
—
—
CP0
—
1111 -111
11-- -111
IESO
FCMEN
—
—
FOSC2
FOSC1
FOSC0
(2)
(2)
(2)
(2)
—
—
—
—
WDTPS3 WDTPS2 WDTPS1 WDTPS0 1111 1111
(3)
(3)
(3)
(3)
(3)
300004h CONFIG3L WAIT
BW
EMB1
EMB0
EASHFT
—
—
ECCPMX
REV1
—
1111 1---
(2)
(2)
(2)
(2)
(3)
(3)
300005h CONFIG3H
3FFFFEh DEVID1
3FFFFFh DEVID2
—
—
—
—
MSSPMSK PMPMX
CCP2MX 1111 1111
(4)
(4)
DEV2
DEV1
DEV9
DEV0
DEV8
REV4
DEV7
REV3
DEV6
REV2
DEV5
REV0
DEV3
xxx0 0000
0100 00xx
DEV10
DEV4
Legend:
x= unknown, u= unchanged, -= unimplemented. Shaded cells are unimplemented, read as ‘0’.
Note 1: Values reflect the unprogrammed state as received from the factory and following Power-on Resets. In all other Reset
states, the configuration bytes maintain their previously programmed states.
2: The value of these bits in program memory should always be ‘1’. This ensures that the location is executed as a NOPif it
is accidentally executed.
3: Implemented in 80-pin devices only.
4: See Register 24-7 and Register 24-8 for DEVID values. These registers are read-only and cannot be programmed by
the user.
DS39778D-page 316
© 2009 Microchip Technology Inc.
PIC18F87J11 FAMILY
REGISTER 24-1: CONFIG1L: CONFIGURATION REGISTER 1 LOW (BYTE ADDRESS 300000h)
R/WO-1
DEBUG
R/WO-1
XINST
R/WO-1
U-0
—
U-0
—
U-0
—
U-0
—
R/WO-1
WDTEN
STVREN
bit 7
bit 0
Legend:
R = Readable bit
WO = Write-Once bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
-n = Value at POR
bit 7
bit 6
bit 5
DEBUG: Background Debugger Enable bit
1= Background debugger disabled; RB6 and RB7 configured as general purpose I/O pins
0= Background debugger enabled; RB6 and RB7 are dedicated to In-Circuit Debug
XINST: Extended Instruction Set Enable bit
1= Instruction set extension and Indexed Addressing mode enabled
0= Instruction set extension and Indexed Addressing mode disabled (Legacy mode)
STVREN: Stack Overflow/Underflow Reset Enable bit
1= Reset on stack overflow/underflow enabled
0= Reset on stack overflow/underflow disabled
bit 4-1
bit 0
Unimplemented: Read as ‘0’
WDTEN: Watchdog Timer Enable bit
1= WDT enabled
0= WDT disabled (control is placed on SWDTEN bit)
REGISTER 24-2: CONFIG1H: CONFIGURATION REGISTER 1 HIGH (BYTE ADDRESS 300001h)
U-1
—
U-1
—
U-1
—
U-1
—
U-0
—
R/WO-1
CP0
U-1
—
U-1
—
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
WO = Write-Once bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7-3
bit 2
Unimplemented: Maintain as ‘01’
CP0: Code Protection bit
1= Program memory is not code-protected
0= Program memory is code-protected
bit 1-0
Unimplemented: Read as ‘0’
© 2009 Microchip Technology Inc.
DS39778D-page 317
PIC18F87J11 FAMILY
REGISTER 24-3: CONFIG2L: CONFIGURATION REGISTER 2 LOW (BYTE ADDRESS 300002h)
R/WO-1
IESO
R/WO-1
FCMEN
U-0
—
U-0
—
U-0
—
R/WO-1
FOSC2
R/WO-1
FOSC1
R/WO-1
FOSC0
bit 7
bit 0
Legend:
R = Readable bit
WO = Write-Once bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
-n = Value at POR
bit 7
bit 6
IESO: Two-Speed Start-up (Internal/External Oscillator Switchover) Control bit
1= Two-Speed Start-up enabled
0= Two-Speed Start-up disabled
FCMEN: Fail-Safe Clock Monitor Enable bit
1= Fail-Safe Clock Monitor enabled
0= Fail-Safe Clock Monitor disabled
bit 5-3
bit 2-0
Unimplemented: Read as ‘0’
FOSC2:FOSC0: Oscillator Selection bits
111= EC oscillator with PLL enabled; CLKO on RA6 (ECPLL)
110= EC oscillator; CLKO on RA6 (EC)
101= HS oscillator with PLL enabled (HSPLL)
100= HS oscillator (HS)
011= Internal oscillator with PLL enabled; CLKO on RA6, port function on RA7 (INTPLL1)
010= Internal oscillator with PLL enabled; port function on RA6 and RA7 (INTPLL2)
001= Internal oscillator block; CLKO on RA6, port function on RA7 (INTIO1)
000= Internal oscillator block ; port function on RA6 and RA7 (INTIO2)
DS39778D-page 318
© 2009 Microchip Technology Inc.
PIC18F87J11 FAMILY
REGISTER 24-4:
CONFIG2H: CONFIGURATION REGISTER 2 HIGH (BYTE ADDRESS 300003h)
U-1
—
U-1
—
U-1
—
U-1
—
R/WO-1
R/WO-1
R/WO-1
R/WO-1
WDTPS3
WDTPS2
WDTPS1
WDTPS0
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
WO = Write-Once bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7-4
bit 3-0
Unimplemented: Maintain as ‘1’
WDTPS3:WDTPS0: Watchdog Timer Postscale Select bits
1111= 1:32,768
1110= 1:16,384
1101= 1:8,192
1100= 1:4,096
1011= 1:2,048
1010= 1:1,024
1001= 1:512
1000= 1:256
0111= 1:128
0110= 1:64
0101= 1:32
0100= 1:16
0011= 1:8
0010= 1:4
0001= 1:2
0000= 1:1
© 2009 Microchip Technology Inc.
DS39778D-page 319
PIC18F87J11 FAMILY
REGISTER 24-5: CONFIG3L: CONFIGURATION REGISTER 3 LOW (BYTE ADDRESS 300004h)
R/WO-1
WAIT(1)
R/WO-1
BW(1)
R/WO-1
EMB1(1)
R/WO-1
EMB0(1)
R/WO-1
EASHFT(1)
U-0
—
U-0
—
U-0
—
bit 7
bit 0
Legend:
R = Readable bit
WO = Write-Once bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
-n = Value at POR
bit 7
WAIT: External Bus Wait Enable bit(1)
1= Wait states on the external bus are disabled
0= Wait states on the external bus are enabled and selected by MEMCON<5:4>
bit 6
BW: Data Bus Width Select bit(1)
1= 16-Bit Data Width modes
0= 8-Bit Data Width modes
bit 5-4
EMB1:EMB0: External Memory Bus Configuration bits(1)
11= Microcontroller mode, external bus disabled
10= Extended Microcontroller mode, 12-bit address width for external bus
01= Extended Microcontroller mode, 16-bit address width for external bus
00= Extended Microcontroller mode, 20-bit address width for external bus
bit 3
EASHFT: External Address Bus Shift Enable bit(1)
1= Address shifting enabled – external address bus is shifted to start at 000000h
0= Address shifting disabled – external address bus reflects the PC value
bit 2-0
Unimplemented: Read as ‘0’
Note 1: Implemented on 80-pin devices only.
DS39778D-page 320
© 2009 Microchip Technology Inc.
PIC18F87J11 FAMILY
REGISTER 24-6: CONFIG3H: CONFIGURATION REGISTER 3 HIGH (BYTE ADDRESS 300005h)
U-1
—
U-1
—
U-1
—
U-1
—
R/WO-1
R/WO-1
PMPMX(1)
R/WO-1
ECCPMX(1)
R/WO-1
MSSPMSK
CCP2MX
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
WO = Write-Once bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7-4
bit 3
Unimplemented: Maintain as ‘1’
MSSPMSK: MSSP Address Masking Mode Select bit
1= 7-Bit Address Masking mode enabled
0= 5-Bit Address Masking mode enable
bit 2
bit 1
PMPMX: PMP Pin Multiplex bit(1)
1= PMP data and control multiplexed to same pins as external memory bus (PORTD and PORTE)
0= PMP data and control multiplexed to alternate pin assignments (PORTA, PORTF and PORTH)
ECCPMX: ECCPx MUX bit(1)
1= ECCP1 outputs (P1B/P1C) are multiplexed with RE6 and RE5;
ECCP3 outputs (P3B/P3C) are multiplexed with RE4 and RE3
0= ECCP1 outputs (P1B/P1C) are multiplexed with RH7 and RH6;
ECCP3 outputs (P3B/P3C) are multiplexed with RH5 and RH4
bit 0
CCP2MX: ECCP2 MUX bit
1= ECCP2/P2A is multiplexed with RC1
0= ECCP2/P2A is multiplexed with RE7 in Microcontroller mode (all devices) or with RB3 in Extended
Microcontroller mode (80-pin devices only)
Note 1: Implemented on 80-pin devices only.
© 2009 Microchip Technology Inc.
DS39778D-page 321
PIC18F87J11 FAMILY
REGISTER 24-7: DEVID1: DEVICE ID REGISTER 1 FOR PIC18F87J11 FAMILY DEVICES
R
R
R
R
R
R
R
R
DEV2
DEV1
DEV0
REV4
REV3
REV2
REV1
REV0
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7-5
bit 4-0
DEV2:DEV0: Device ID bits
See Register 24-8 for a complete listing.
REV4:REV0: Revision ID bits
These bits are used to indicate the device revision.
REGISTER 24-8: DEVID2: DEVICE ID REGISTER 2 FOR PIC18F87J11 FAMILY DEVICES
R
R
R
R
R
R
R
R
DEV10
DEV9
DEV8
DEV7
DEV6
DEV5
DEV4
DEV3
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 7-0
DEV10:DEV3: Device ID bits:
DEV10:DEV3
(DEVID2<7:0>)
DEV2:DEV0
(DEVID1<7:5>)
Device
0100 0100
0100 0100
0100 0100
0100 0100
0100 0101
0100 0101
010
011
100
111
000
001
PIC18F66J11
PIC18F66J16
PIC18F67J11
PIC18F86J11
PIC18F86J16
PIC18F87J11
DS39778D-page 322
© 2009 Microchip Technology Inc.
PIC18F87J11 FAMILY
24.2 Watchdog Timer (WDT)
Note 1: The CLRWDT and SLEEP instructions
clear the WDT and postscaler counts
when executed.
For PIC18F87J11 Family devices, the WDT is driven by
the INTRC oscillator. When the WDT is enabled, the
clock source is also enabled. The nominal WDT period
is 4 ms and has the same stability as the INTRC
oscillator.
2: When a CLRWDT instruction is executed,
the postscaler count will be cleared.
24.2.1
CONTROL REGISTER
The 4 ms period of the WDT is multiplied by a 16-bit
postscaler. Any output of the WDT postscaler is
selected by a multiplexor, controlled by the WDTPS bits
in Configuration Register 2H. Available periods range
from about 4 ms to 135 seconds (2.25 minutes
depending on voltage, temperature and WDT post-
scaler). The WDT and postscaler are cleared whenever
a SLEEPor CLRWDTinstruction is executed, or a clock
failure (primary or Timer1 oscillator) has occurred.
The WDTCON register (Register 24-9) is a readable
and writable register. The SWDTEN bit enables or dis-
ables WDT operation. This allows software to override
the WDTEN Configuration bit and enable the WDT only
if it has been disabled by the Configuration bit.
The ADSHR bit selects which SFRs are currently
selected and accessible. See Section 5.3.4.1 “Shared
Address SFRs” for additional details.
The LVDSTAT is a read-only status bit which is continu-
ously updated and provides information about the current
level of VDDCORE. This bit is only valid when the on-chip
voltage regulator is enabled.
FIGURE 24-1:
WDT BLOCK DIAGRAM
Enable WDT
SWDTEN
INTRC Control
WDT Counter
Wake-up from
Power-Managed
Modes
÷128
INTRC Oscillator
WDT
Reset
Reset
CLRWDT
All Device Resets
Programmable Postscaler
1:1 to 1:32,768
WDT
4
WDTPS3:WDTPS0
Sleep
© 2009 Microchip Technology Inc.
DS39778D-page 323
PIC18F87J11 FAMILY
REGISTER 24-9: WDTCON: WATCHDOG TIMER CONTROL REGISTER
R/W-0
R-x
U-0
—
R/W-0
U-0
—
U-0
—
U-0
—
U-0
SWDTEN(1)
bit 0
REGSLP
LVDSTAT
ADSHR
bit 7
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
-n = Value at POR
bit 7
bit 6
REGSLP: Voltage Regulator Low-Power Operation Enable bit
1= On-chip regulator enters low-power operation when device enters Sleep mode
0= On-chip regulator is active, even in Sleep mode
LVDSTAT: LVD Status bit
1= VDDCORE > 2.45V
0= VDDCORE < 2.45V
bit 5
bit 4
Unimplemented: Read as ‘0’
ADSHR: Shared Address SFR Select bit
For details of bit operation, see Register 5-3.
Unimplemented: Read as ‘0’
bit 3-1
bit 0
SWDTEN: Software Controlled Watchdog Timer Enable bit(1)
1= Watchdog Timer is on
0= Watchdog Timer is off
Note 1: This bit has no effect if the Configuration bit, WDTEN, is enabled.
TABLE 24-3: SUMMARY OF WATCHDOG TIMER REGISTERS
ResetValues
on Page:
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
RCON
IPEN
—
CM
—
RI
TO
—
PD
—
POR
—
BOR
58
59
WDTCON REGSLP LVDSTAT
ADSHR
SWDTEN
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the Watchdog Timer.
DS39778D-page 324
© 2009 Microchip Technology Inc.
PIC18F87J11 FAMILY
FIGURE 24-2:
CONNECTIONS FOR THE
ON-CHIP REGULATOR
24.3 On-Chip Voltage Regulator
All of the PIC18F87J11 family devices power their core
digital logic at a nominal 2.5V. For designs that are
required to operate at a higher typical voltage, such as
3.3V, all devices in the PIC18F87J11 family incorporate
an on-chip regulator that allows the device to run its
core logic from VDD.
Regulator Enabled (ENVREG tied to VDD):
3.3V
PIC18F87J11
VDD
ENVREG
The regulator is controlled by the ENVREG pin. Tying
VDD to the pin enables the regulator, which in turn,
provides power to the core from the other VDD pins.
When the regulator is enabled, a low-ESR filter capac-
itor must be connected to the VDDCORE/VCAP pin
(Figure 24-2). This helps to maintain the stability of the
regulator. The recommended value for the filter capac-
itor is provided in Section 27.3 “DC Characteristics:
PIC18F87J11 Family (Industrial)”.
VDDCORE/VCAP
CF
VSS
Regulator Disabled (ENVREG tied to ground):
If ENVREG is tied to VSS, the regulator is disabled. In
this case, separate power for the core logic at a nomi-
nal 2.5V must be supplied to the device on the
VDDCORE/VCAP pin to run the I/O pins at higher voltage
levels, typically 3.3V. Alternatively, the VDDCORE/VCAP
and VDD pins can be tied together to operate at a lower
nominal voltage. Refer to Figure 24-2 for possible
configurations.
(1)
(1)
2.5V
3.3V
PIC18F87J11
VDD
ENVREG
VDDCORE/VCAP
VSS
24.3.1
VOLTAGE REGULATOR TRACKING
MODE AND LOW-VOLTAGE
DETECTION
When it is enabled, the on-chip regulator provides a
constant voltage of 2.5V nominal to the digital core
logic. The regulator can provide this level from a VDD of
about 2.5V, all the way up to the device’s VDDMAX. It
does not have the capability to boost VDD levels below
2.5V. In order to prevent “brown-out” conditions, when
the voltage drops too low for the regulator, the regulator
enters Tracking mode. In Tracking mode, the regulator
output follows VDD, with a typical voltage drop of
100 mV.
Regulator Disabled (VDD tied to VDDCORE):
(1)
2.5V
PIC18F87J11
VDD
ENVREG
VDDCORE/VCAP
VSS
The on-chip regulator includes a simple, Low-Voltage
Detect (LVD) circuit. If VDD drops too low to maintain
approximately 2.45V on VDDCORE, the circuit sets the
Low-Voltage Detect Interrupt Flag, LVDIF (PIR2<2>).
This can be used to generate an interrupt and put the
application into a low-power operational mode, or
trigger an orderly shutdown. Low-Voltage Detection is
only available when the regulator is enabled.
Note 1: These are typical operating voltages. Refer
to Section 27.1 “DC Characteristics:
Supply Voltage” for the full operating
ranges of VDD and VDDCORE.
The Low-Voltage Detect interrupt is edge-sensitive.
The interrupt flag will only be set once per falling edge
of VDDCORE. Firmware can clear the interrupt flag, but
a new interrupt will not be generated until VDDCORE
rises back above, and then falls below, the 2.45 thresh-
old. Upon device Resets, the interrupt flag will reset to
‘0’, even if VDDCORE is less than 2.45V. When the
regulator is enabled, the LVDSTAT bit in the WDTCON
register can be polled to determine the current level of
VDDCORE.
© 2009 Microchip Technology Inc.
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PIC18F87J11 FAMILY
Substantial Sleep mode power savings can be obtained
by setting the REGSLP bit, but device wake-up time will
increase in order to insure the regulator has enough time
to stabilize. The REGSLP bit is automatically cleared by
hardware when a Low-Voltage Detect condition occurs.
24.3.2
ON-CHIP REGULATOR AND BOR
When the on-chip regulator is enabled, PIC18F87J11
family devices also have a simple brown-out capability.
If the voltage supplied to the regulator is inadequate to
maintain a regulated level, the regulator Reset circuitry
will generate a Brown-out Reset. This event is captured
by the BOR flag bit (RCON<0>).
24.4 Two-Speed Start-up
The operation of the Brown-out Reset is described in
more detail in Section 4.4 “Brown-out Reset (BOR)”
and Section 4.4.1 “Detecting BOR”. The brown-out
voltage levels are specific in Section 27.1 “DC Char-
acteristics: Supply Voltage PIC18F87J11 Family
(Industrial)”.
The Two-Speed Start-up feature helps to minimize the
latency period, from oscillator start-up to code execu-
tion, by allowing the microcontroller to use the INTRC
oscillator as a clock source until the primary clock
source is available. It is enabled by setting the IESO
Configuration bit.
Two-Speed Start-up should be enabled only if the
primary oscillator mode is HS or HSPLL
(Crystal-Based) modes. Since the EC and ECPLL
modes do not require an Oscillator Start-up Timer
delay, Two-Speed Start-up should be disabled.
24.3.3
POWER-UP REQUIREMENTS
The on-chip regulator is designed to meet the power-up
requirements for the device. If the application does not
use the regulator, then strict power-up conditions must
be adhered to. While powering up, VDDCORE must
never exceed VDD by 0.3 volts.
When enabled, Resets and wake-ups from Sleep mode
cause the device to configure itself to run from the inter-
nal oscillator block as the clock source, following the
time-out of the Power-up Timer after a Power-on Reset
is enabled. This allows almost immediate code
execution while the primary oscillator starts and the
OST is running. Once the OST times out, the device
automatically switches to PRI_RUN mode.
24.3.4
OPERATION IN SLEEP MODE
When enabled, the on-chip regulator always consumes
a small incremental amount of current over IDD. This
includes when the device is in Sleep mode, even
though the core digital logic does not require power. To
provide additional savings in applications where power
resources are critical, the regulator can be configured
to automatically disable itself whenever the device
goes into Sleep mode. This feature is controlled by the
REGSLP bit (WDTCON<7>, Register 24-9). Setting
this bit disables the regulator in Sleep mode and
reduces its current consumption to a minimum.
In all other power-managed modes, Two-Speed
Start-up is not used. The device will be clocked by the
currently selected clock source until the primary clock
source becomes available. The setting of the IESO bit
is ignored.
FIGURE 24-3:
TIMING TRANSITION FOR TWO-SPEED START-UP (INTRC TO HSPLL)
Q3
Q4
Q1
Q2 Q3 Q4 Q1 Q2 Q3
Q1
Q2
INTRC
OSC1
(1)
(1)
TOST
TPLL
1
2
n-1
n
PLL Clock
Output
Clock
Transition
CPU Clock
Peripheral
Clock
Program
Counter
PC + 4
PC + 6
PC
PC + 2
OSTS bit Set
Note 1: TOST = 1024 TOSC; TPLL = 2 ms (approx). These intervals are not shown to scale.
Wake from Interrupt Event
DS39778D-page 326
© 2009 Microchip Technology Inc.
PIC18F87J11 FAMILY
Clock failure is tested for on the falling edge of the
sample clock. If a sample clock falling edge occurs
while CM is still set, a clock failure has been detected
(Figure 24-5). This causes the following:
24.4.1
SPECIAL CONSIDERATIONS FOR
USING TWO-SPEED START-UP
While using the INTRC oscillator in Two-Speed
Start-up, the device still obeys the normal command
sequences for entering power-managed modes,
including serial SLEEP instructions (refer to
Section 3.1.4 “Multiple Sleep Commands”). In prac-
tice, this means that user code can change the
SCS1:SCS0 bit settings or issue SLEEP instructions
before the OST times out. This would allow an applica-
tion to briefly wake-up, perform routine “housekeeping”
tasks and return to Sleep before the device starts to
operate from the primary oscillator.
• the FSCM generates an oscillator fail interrupt by
setting bit OSCFIF (PIR2<7>);
• the device clock source is switched to the internal
oscillator block (OSCCON is not updated to show
the current clock source – this is the fail-safe
condition); and
• the WDT is reset.
During switchover, the postscaler frequency from the
internal oscillator block may not be sufficiently stable
for timing sensitive applications. In these cases, it may
be desirable to select another clock configuration and
enter an alternate power-managed mode. This can be
done to attempt a partial recovery or execute a
controlled shutdown. See Section 3.1.4 “Multiple
Sleep Commands” and Section 24.4.1 “Special
Considerations for Using Two-Speed Start-up” for
more details.
User code can also check if the primary clock source is
currently providing the device clocking by checking the
status of the OSTS bit (OSCCON<3>). If the bit is set,
the primary oscillator is providing the clock. Otherwise,
the internal oscillator block is providing the clock during
wake-up from Reset or Sleep mode.
24.5 Fail-Safe Clock Monitor
The FSCM will detect failures of the primary or second-
ary clock sources only. If the internal oscillator block
fails, no failure would be detected, nor would any action
be possible.
The Fail-Safe Clock Monitor (FSCM) allows the
microcontroller to continue operation in the event of an
external oscillator failure by automatically switching the
device clock to the internal oscillator block. The FSCM
function is enabled by setting the FCMEN Configuration
bit.
24.5.1
FSCM AND THE WATCHDOG TIMER
Both the FSCM and the WDT are clocked by the
INTRC oscillator. Since the WDT operates with a
separate divider and counter, disabling the WDT has
no effect on the operation of the INTRC oscillator when
the FSCM is enabled.
When FSCM is enabled, the INTRC oscillator runs at
all times to monitor clocks to peripherals and provide a
backup clock in the event of a clock failure. Clock
monitoring (shown in Figure 24-4) is accomplished by
creating a sample clock signal which is the INTRC out-
put divided by 64. This allows ample time between
FSCM sample clocks for a peripheral clock edge to
occur. The peripheral device clock and the sample
clock are presented as inputs to the Clock Monitor
(CM) latch. The CM is set on the falling edge of the
device clock source but cleared on the rising edge of
the sample clock.
As already noted, the clock source is switched to the
INTRC clock when a clock failure is detected; this may
mean a substantial change in the speed of code execu-
tion. If the WDT is enabled with a small prescale value,
a decrease in clock speed allows a WDT time-out to
occur and a subsequent device Reset. For this reason,
fail-safe clock events also reset the WDT and post-
scaler, allowing it to start timing from when execution
speed was changed and decreasing the likelihood of
an erroneous time-out.
FIGURE 24-4:
FSCM BLOCK DIAGRAM
Clock Monitor
Latch (CM)
(edge-triggered)
Peripheral
Clock
S
C
Q
INTRC
Source
Q
÷ 64
488 Hz
(2.048 ms)
(32 μs)
Clock
Failure
Detected
© 2009 Microchip Technology Inc.
DS39778D-page 327
PIC18F87J11 FAMILY
FIGURE 24-5:
FSCM TIMING DIAGRAM
Sample Clock
Oscillator
Failure
Device
Clock
Output
CM Output
(Q)
Failure
Detected
OSCFIF
CM Test
CM Test
CM Test
Note:
The device clock is normally at a much higher frequency than the sample clock. The relative frequencies in
this example have been chosen for clarity.
24.5.2
EXITING FAIL-SAFE OPERATION
24.5.4
POR OR WAKE-UP FROM SLEEP
The fail-safe condition is terminated by either a device
Reset or by entering a power-managed mode. On
Reset, the controller starts the primary clock source
specified in Configuration Register 2H (with any
required start-up delays that are required for the oscil-
lator mode, such as OST or PLL timer). The INTRC
oscillator provides the device clock until the primary
clock source becomes ready (similar to a Two-Speed
Start-up). The clock source is then switched to the
primary clock (indicated by the OSTS bit in the
OSCCON register becoming set). The Fail-Safe Clock
Monitor then resumes monitoring the peripheral clock.
The FSCM is designed to detect oscillator failure at any
point after the device has exited Power-on Reset (POR)
or low-power Sleep mode. When the primary device
clock is either the EC or INTRC modes, monitoring can
begin immediately following these events.
For HS or HSPLL modes, the situation is somewhat
different. Since the oscillator may require a start-up
time considerably longer than the FSCM sample clock
time, a false clock failure may be detected. To prevent
this, the internal oscillator block is automatically config-
ured as the device clock and functions until the primary
clock is stable (the OST and PLL timers have timed
out). This is identical to Two-Speed Start-up mode.
Once the primary clock is stable, the INTRC returns to
its role as the FSCM source.
The primary clock source may never become ready
during start-up. In this case, operation is clocked by the
INTRC oscillator. The OSCCON register will remain in
its Reset state until a power-managed mode is entered.
Note:
The same logic that prevents false
oscillator failure interrupts on POR, or
wake from Sleep, will also prevent the
detection of the oscillator’s failure to start
at all following these events. This can be
avoided by monitoring the OSTS bit and
using a timing routine to determine if the
oscillator is taking too long to start. Even
so, no oscillator failure interrupt will be
flagged.
24.5.3
FSCM INTERRUPTS IN
POWER-MANAGED MODES
By entering a power-managed mode, the clock
multiplexor selects the clock source selected by the
OSCCON register. Fail-Safe Clock Monitoring of the
power-managed clock source resumes in the
power-managed mode.
If an oscillator failure occurs during power-managed
operation, the subsequent events depend on whether
or not the oscillator failure interrupt is enabled. If
enabled (OSCFIF = 1), code execution will be clocked
by the INTRC multiplexor. An automatic transition back
to the failed clock source will not occur.
As noted in Section 24.4.1 “Special Considerations
for Using Two-Speed Start-up”, it is also possible to
select another clock configuration and enter an alternate
power-managed mode while waiting for the primary
clock to become stable. When the new power-managed
mode is selected, the primary clock is disabled.
If the interrupt is disabled, subsequent interrupts while
in Idle mode will cause the CPU to begin executing
instructions while being clocked by the INTRC source.
DS39778D-page 328
© 2009 Microchip Technology Inc.
PIC18F87J11 FAMILY
24.6 Program Verification and
Code Protection
24.7
In-Circuit Serial Programming
PIC18F87J11 Family microcontrollers can be serially
programmed while in the end application circuit. This is
simply done with two lines for clock and data and three
other lines for power, ground and the programming
voltage. This allows customers to manufacture boards
with unprogrammed devices and then program the
microcontroller just before shipping the product. This
also allows the most recent firmware or a custom
firmware to be programmed.
For all devices in the PIC18F87J11 Family of devices,
the on-chip program memory space is treated as a
single block. Code protection for this block is controlled
by one Configuration bit, CP0. This bit inhibits external
reads and writes to the program memory space. It has
no direct effect in normal execution mode.
24.6.1
CONFIGURATION REGISTER
PROTECTION
24.8 In-Circuit Debugger
The Configuration registers are protected against
untoward changes or reads in two ways. The primary
protection is the write-once feature of the Configuration
bits which prevents reconfiguration once the bit has
been programmed during a power cycle. To safeguard
against unpredictable events, Configuration bit
changes resulting from individual cell level disruptions
(such as ESD events) will cause a parity error and
trigger a device Reset. This is seen by the user as a
Configuration Match Reset.
When the DEBUG Configuration bit is programmed to
a ‘0’, the In-Circuit Debugger functionality is enabled.
This function allows simple debugging functions when
used with MPLAB® IDE. When the microcontroller has
this feature enabled, some resources are not available
for general use. Table 24-4 shows which resources are
required by the background debugger.
TABLE 24-4: DEBUGGER RESOURCES
The data for the Configuration registers is derived from
the Flash Configuration Words in program memory.
When the CP0 bit set, the source data for device
configuration is also protected as a consequence.
I/O pins:
RB6, RB7
2 levels
Stack:
Program Memory:
Data Memory:
512 bytes
10 bytes
© 2009 Microchip Technology Inc.
DS39778D-page 329
PIC18F87J11 FAMILY
NOTES:
DS39778D-page 330
© 2009 Microchip Technology Inc.
PIC18F87J11 FAMILY
The literal instructions may use some of the following
operands:
25.0 INSTRUCTION SET SUMMARY
The PIC18F87J11 Family of devices incorporate the
standard set of 75 PIC18 core instructions, as well as
an extended set of 8 new instructions for the optimiza-
tion of code that is recursive or that utilizes a software
stack. The extended set is discussed later in this
section.
• A literal value to be loaded into a file register
(specified by ‘k’)
• The desired FSR register to load the literal value
into (specified by ‘f’)
• No operand required
(specified by ‘—’)
25.1 Standard Instruction Set
The control instructions may use some of the following
operands:
The standard PIC18 instruction set adds many
enhancements to the previous PIC® instruction sets,
while maintaining an easy migration from these instruc-
tion sets. Most instructions are a single program
memory word (16 bits), but there are four instructions
that require two program memory locations.
• A program memory address (specified by ‘n’)
• The mode of the CALLor RETURNinstructions
(specified by ‘s’)
• The mode of the table read and table write
instructions (specified by ‘m’)
Each single-word instruction is a 16-bit word divided
into an opcode, which specifies the instruction type and
one or more operands, which further specify the
operation of the instruction.
• No operand required
(specified by ‘—’)
All instructions are a single word, except for four
double-word instructions. These instructions were
made double-word to contain the required information
in 32 bits. In the second word, the 4 MSbs are ‘1’s. If
this second word is executed as an instruction (by
itself), it will execute as a NOP.
The instruction set is highly orthogonal and is grouped
into four basic categories:
• Byte-oriented operations
• Bit-oriented operations
• Literal operations
All single-word instructions are executed in a single
instruction cycle, unless a conditional test is true or the
program counter is changed as a result of the instruc-
tion. In these cases, the execution takes two instruction
cycles with the additional instruction cycle(s) executed
as a NOP.
• Control operations
The PIC18 instruction set summary in Table 25-2 lists
byte-oriented, bit-oriented, literal and control
operations. Table 25-1 shows the opcode field
descriptions.
The double-word instructions execute in two instruction
cycles.
Most byte-oriented instructions have three operands:
1. The file register (specified by ‘f’)
One instruction cycle consists of four oscillator periods.
Thus, for an oscillator frequency of 4 MHz, the normal
instruction execution time is 1 μs. If a conditional test is
true, or the program counter is changed as a result of
an instruction, the instruction execution time is 2 μs.
Two-word branch instructions (if true) would take 3 μs.
2. The destination of the result (specified by ‘d’)
3. The accessed memory (specified by ‘a’)
The file register designator, ‘f’, specifies which file reg-
ister is to be used by the instruction. The destination
designator, ‘d’, specifies where the result of the
operation is to be placed. If ‘d’ is ‘0’, the result is placed
in the WREG register. If ‘d’ is ‘1’, the result is placed in
the file register specified in the instruction.
Figure 25-1 shows the general formats that the instruc-
tions can have. All examples use the convention ‘nnh’
to represent a hexadecimal number.
The instruction set summary, shown in Table 25-2, lists
the standard instructions recognized by the Microchip
MPASMTM Assembler.
All bit-oriented instructions have three operands:
1. The file register (specified by ‘f’)
2. The bit in the file register (specified by ‘b’)
3. The accessed memory (specified by ‘a’)
Section 25.1.1 “Standard Instruction Set” provides
a description of each instruction.
The bit field designator ‘b’ selects the number of the bit
affected by the operation, while the file register desig-
nator, ‘f’, represents the number of the file in which the
bit is located.
© 2009 Microchip Technology Inc.
DS39778D-page 331
PIC18F87J11 FAMILY
TABLE 25-1: OPCODE FIELD DESCRIPTIONS
Field
Description
a
RAM access bit:
a = 0: RAM location in Access RAM (BSR register is ignored)
a = 1: RAM bank is specified by BSR register
bbb
Bit address within an 8-bit file register (0 to 7).
BSR
Bank Select Register. Used to select the current RAM bank.
ALU Status bits: Carry, Digit Carry, Zero, Overflow, Negative.
C, DC, Z, OV, N
d
Destination select bit:
d = 0: store result in WREG
d = 1: store result in file register f
dest
f
Destination: either the WREG register or the specified register file location.
8-bit register file address (00h to FFh), or 2-bit FSR designator (0h to 3h).
12-bit register file address (000h to FFFh). This is the source address.
12-bit register file address (000h to FFFh). This is the destination address.
Global Interrupt Enable bit.
f
f
s
d
GIE
k
Literal field, constant data or label (may be either an 8-bit, 12-bit or a 20-bit value).
Label name.
label
mm
The mode of the TBLPTR register for the table read and table write instructions.
Only used with table read and table write instructions:
*
No Change to register (such as TBLPTR with table reads and writes)
Post-Increment register (such as TBLPTR with table reads and writes)
Post-Decrement register (such as TBLPTR with table reads and writes)
Pre-Increment register (such as TBLPTR with table reads and writes)
*+
*-
+*
n
The relative address (2’s complement number) for relative branch instructions or the direct address for
Call/Branch and Return instructions.
PC
Program Counter.
PCL
Program Counter Low Byte.
Program Counter High Byte.
Program Counter High Byte Latch.
Program Counter Upper Byte Latch.
Power-Down bit.
PCH
PCLATH
PCLATU
PD
PRODH
PRODL
s
Product of Multiply High Byte.
Product of Multiply Low Byte.
Fast Call/Return mode select bit:
s = 0: do not update into/from shadow registers
s = 1: certain registers loaded into/from shadow registers (Fast mode)
TBLPTR
TABLAT
TO
21-bit Table Pointer (points to a program memory location).
8-bit Table Latch.
Time-out bit.
TOS
u
Top-of-Stack.
Unused or Unchanged.
Watchdog Timer.
WDT
WREG
x
Working register (accumulator).
Don’t care (‘0’ or ‘1’). The assembler will generate code with x = 0. It is the recommended form of use for
compatibility with all Microchip software tools.
z
z
{
7-bit offset value for Indirect Addressing of register files (source).
7-bit offset value for Indirect Addressing of register files (destination).
Optional argument.
s
d
}
[text]
(text)
[expr]<n>
→
Indicates Indexed Addressing.
The contents of text.
Specifies bit nof the register indicated by the pointer, expr.
Assigned to.
< >
Register bit field.
∈
In the set of.
italics
User-defined term (font is Courier New).
DS39778D-page 332
© 2009 Microchip Technology Inc.
PIC18F87J11 FAMILY
FIGURE 25-1:
GENERAL FORMAT FOR INSTRUCTIONS
Byte-oriented file register operations
15 10
OPCODE f (FILE #)
Example Instruction
9
8
7
0
ADDWF MYREG, W, B
d
a
d = 0for result destination to be WREG register
d = 1for result destination to be file register (f)
a = 0to force Access Bank
a = 1for BSR to select bank
f = 8-bit file register address
Byte to Byte move operations (2-word)
15
12 11
0
0
MOVFF MYREG1, MYREG2
OPCODE
f (Source FILE #)
15
12 11
1111
f (Destination FILE #)
f = 12-bit file register address
Bit-oriented file register operations
15 12 11 9 8
OPCODE b (BIT #)
7
0
BSF MYREG, bit, B
a
f (FILE #)
b = 3-bit position of bit in file register (f)
a = 0to force Access Bank
a = 1for BSR to select bank
f = 8-bit file register address
Literal operations
15
8
7
0
MOVLW 7Fh
OPCODE
k = 8-bit immediate value
k (literal)
Control operations
CALL, GOTO and Branch operations
15
8 7
0
GOTO Label
OPCODE
12 11
n<7:0> (literal)
15
0
1111
n<19:8> (literal)
n = 20-bit immediate value
15
15
8
7
0
CALL MYFUNC
OPCODE
12 11
S
n<7:0> (literal)
0
1111
S = Fast bit
n<19:8> (literal)
15
15
11 10
0
0
BRA MYFUNC
BC MYFUNC
OPCODE
OPCODE
n<10:0> (literal)
n<7:0> (literal)
8 7
© 2009 Microchip Technology Inc.
DS39778D-page 333
PIC18F87J11 FAMILY
TABLE 25-2: PIC18F87J11 FAMILY INSTRUCTION SET
16-Bit Instruction Word
MSb LSb
Mnemonic,
Operands
Status
Affected
Description
Cycles
Notes
BYTE-ORIENTED OPERATIONS
ADDWF f, d, a Add WREG and f
ADDWFC f, d, a Add WREG and Carry bit to f
ANDWF f, d, a AND WREG with f
1
0010 01da ffff ffff C, DC, Z, OV, N 1, 2
0010 00da ffff ffff C, DC, Z, OV, N 1, 2
1
1
1
1
0001 01da ffff ffff Z, N
0110 101a ffff ffff Z
0001 11da ffff ffff Z, N
1,2
2
1, 2
4
CLRF
f, a
Clear f
COMF
f, d, a Complement f
CPFSEQ f, a
CPFSGT f, a
CPFSLT f, a
Compare f with WREG, Skip =
Compare f with WREG, Skip >
Compare f with WREG, Skip <
1 (2 or 3) 0110 001a ffff ffff None
1 (2 or 3) 0110 010a ffff ffff None
1 (2 or 3) 0110 000a ffff ffff None
4
1, 2
DECF
f, d, a Decrement f
1
0000 01da ffff ffff C, DC, Z, OV, N 1, 2, 3, 4
DECFSZ f, d, a Decrement f, Skip if 0
DCFSNZ f, d, a Decrement f, Skip if Not 0
1 (2 or 3) 0010 11da ffff ffff None
1 (2 or 3) 0100 11da ffff ffff None
1, 2, 3, 4
1, 2
INCF
f, d, a Increment f
1
0010 10da ffff ffff C, DC, Z, OV, N 1, 2, 3, 4
INCFSZ f, d, a Increment f, Skip if 0
INFSNZ f, d, a Increment f, Skip if Not 0
1 (2 or 3) 0011 11da ffff ffff None
1 (2 or 3) 0100 10da ffff ffff None
4
1, 2
1, 2
1
IORWF
MOVF
f, d, a Inclusive OR WREG with f
f, d, a Move f
1
1
2
0001 00da ffff ffff Z, N
0101 00da ffff ffff Z, N
1100 ffff ffff ffff None
1111 ffff ffff ffff
MOVFF fs, fd Move fs (source) to 1st word
fd (destination) 2nd word
MOVWF f, a
MULWF f, a
Move WREG to f
Multiply WREG with f
Negate f
1
1
1
1
1
1
1
1
1
0110 111a ffff ffff None
0000 001a ffff ffff None
0110 110a ffff ffff C, DC, Z, OV, N
0011 01da ffff ffff C, Z, N
0100 01da ffff ffff Z, N
0011 00da ffff ffff C, Z, N
0100 00da ffff ffff Z, N
0110 100a ffff ffff None
0101 01da ffff ffff C, DC, Z, OV, N
1, 2
1, 2
NEGF
RLCF
f, a
f, d, a Rotate Left f through Carry
RLNCF f, d, a Rotate Left f (No Carry)
RRCF f, d, a Rotate Right f through Carry
RRNCF f, d, a Rotate Right f (No Carry)
SETF f, a Set f
SUBFWB f, d, a Subtract f from WREG with
Borrow
1, 2
SUBWF f, d, a Subtract WREG from f
SUBWFB f, d, a Subtract WREG from f with
Borrow
1
1
0101 11da ffff ffff C, DC, Z, OV, N 1, 2
0101 10da ffff ffff C, DC, Z, OV, N
SWAPF f, d, a Swap Nibbles in f
1
0011 10da ffff ffff None
4
TSTFSZ f, a
XORWF f, d, a Exclusive OR WREG with f
Test f, Skip if 0
1 (2 or 3) 0110 011a ffff ffff None
0001 10da ffff ffff Z, N
1, 2
1
Note 1: When a PORT register is modified as a function of itself (e.g., MOVF PORTB, 1, 0), the value used will be
that value present on the pins themselves. For example, if the data latch is ‘1’ for a pin configured as input
and is driven low by an external device, the data will be written back with a ‘0’.
2: If this instruction is executed on the TMR0 register (and, where applicable, d = 1), the prescaler will be
cleared if assigned.
3: If the Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The
second cycle is executed as a NOP.
4: Some instructions are two-word instructions. The second word of these instructions will be executed as a
NOPunless the first word of the instruction retrieves the information embedded in these 16 bits. This ensures
that all program memory locations have a valid instruction.
DS39778D-page 334
© 2009 Microchip Technology Inc.
PIC18F87J11 FAMILY
TABLE 25-2: PIC18F87J11 FAMILY INSTRUCTION SET (CONTINUED)
16-Bit Instruction Word
MSb LSb
Mnemonic,
Operands
Status
Affected
Description
Cycles
Notes
BIT-ORIENTED OPERATIONS
BCF
BSF
BTFSC
BTFSS
BTG
f, b, a Bit Clear f
f, b, a Bit Set f
f, b, a Bit Test f, Skip if Clear
f, b, a Bit Test f, Skip if Set
f, b, a Bit Toggle f
1
1
1001 bbba ffff ffff None
1000 bbba ffff ffff None
1, 2
1, 2
3, 4
3, 4
1, 2
1 (2 or 3) 1011 bbba ffff ffff None
1 (2 or 3) 1010 bbba ffff ffff None
1
0111 bbba ffff ffff None
CONTROL OPERATIONS
BC
BN
n
n
n
n
n
n
n
n
Branch if Carry
1 (2)
1 (2)
1 (2)
1 (2)
1 (2)
1 (2)
1 (2)
2
1110 0010 nnnn nnnn None
1110 0110 nnnn nnnn None
1110 0011 nnnn nnnn None
1110 0111 nnnn nnnn None
1110 0101 nnnn nnnn None
1110 0001 nnnn nnnn None
1110 0100 nnnn nnnn None
1101 0nnn nnnn nnnn None
1110 0000 nnnn nnnn None
1110 110s kkkk kkkk None
1111 kkkk kkkk kkkk
Branch if Negative
Branch if Not Carry
Branch if Not Negative
Branch if Not Overflow
Branch if Not Zero
Branch if Overflow
Branch Unconditionally
Branch if Zero
BNC
BNN
BNOV
BNZ
BOV
BRA
BZ
n
n, s
1 (2)
2
CALL
Call Subroutine 1st word
2nd word
CLRWDT —
Clear Watchdog Timer
Decimal Adjust WREG
Go to Address 1st word
2nd word
1
1
2
0000 0000 0000 0100 TO, PD
0000 0000 0000 0111 C
1110 1111 kkkk kkkk None
1111 kkkk kkkk kkkk
DAW
—
n
GOTO
NOP
NOP
POP
PUSH
RCALL
RESET
RETFIE
—
—
—
—
n
No Operation
No Operation
Pop Top of Return Stack (TOS)
Push Top of Return Stack (TOS) 1
Relative Call
Software Device Reset
Return from Interrupt Enable
1
1
1
0000 0000 0000 0000 None
1111 xxxx xxxx xxxx None
0000 0000 0000 0110 None
0000 0000 0000 0101 None
1101 1nnn nnnn nnnn None
0000 0000 1111 1111 All
0000 0000 0001 000s GIE/GIEH,
PEIE/GIEL
4
2
1
2
s
k
RETLW
RETURN s
SLEEP
Return with Literal in WREG
Return from Subroutine
Go into Standby mode
2
2
1
0000 1100 kkkk kkkk None
0000 0000 0001 001s None
0000 0000 0000 0011 TO, PD
—
Note 1: When a PORT register is modified as a function of itself (e.g., MOVF PORTB, 1, 0), the value used will be
that value present on the pins themselves. For example, if the data latch is ‘1’ for a pin configured as input
and is driven low by an external device, the data will be written back with a ‘0’.
2: If this instruction is executed on the TMR0 register (and, where applicable, d = 1), the prescaler will be
cleared if assigned.
3: If the Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The
second cycle is executed as a NOP.
4: Some instructions are two-word instructions. The second word of these instructions will be executed as a
NOPunless the first word of the instruction retrieves the information embedded in these 16 bits. This ensures
that all program memory locations have a valid instruction.
© 2009 Microchip Technology Inc.
DS39778D-page 335
PIC18F87J11 FAMILY
TABLE 25-2: PIC18F87J11 FAMILY INSTRUCTION SET (CONTINUED)
16-Bit Instruction Word
Mnemonic,
Status
Affected
Description
Cycles
Notes
Operands
MSb
LSb
LITERAL OPERATIONS
ADDLW
ANDLW
IORLW
LFSR
k
k
k
f, k
Add Literal and WREG
AND Literal with WREG
Inclusive OR Literal with WREG 1
Move Literal (12-bit) 2nd word
to FSR (f) 1st word
1
1
0000 1111 kkkk kkkk C, DC, Z, OV, N
0000 1011 kkkk kkkk Z, N
0000 1001 kkkk kkkk Z, N
1110 1110 00ff kkkk None
1111 0000 kkkk kkkk
2
MOVLB
MOVLW
MULLW
RETLW
SUBLW
XORLW
k
k
k
k
k
k
Move Literal to BSR<3:0>
Move Literal to WREG
Multiply Literal with WREG
Return with Literal in WREG
Subtract WREG from Literal
1
1
1
2
1
0000 0001 0000 kkkk None
0000 1110 kkkk kkkk None
0000 1101 kkkk kkkk None
0000 1100 kkkk kkkk None
0000 1000 kkkk kkkk C, DC, Z, OV, N
0000 1010 kkkk kkkk Z, N
Exclusive OR Literal with WREG 1
DATA MEMORY ↔ PROGRAM MEMORY OPERATIONS
TBLRD*
Table Read
2
0000 0000 0000 1000 None
0000 0000 0000 1001 None
0000 0000 0000 1010 None
0000 0000 0000 1011 None
0000 0000 0000 1100 None
0000 0000 0000 1101 None
0000 0000 0000 1110 None
0000 0000 0000 1111 None
TBLRD*+
TBLRD*-
TBLRD+*
TBLWT*
TBLWT*+
TBLWT*-
TBLWT+*
Table Read with Post-Increment
Table Read with Post-Decrement
Table Read with Pre-Increment
Table Write
Table Write with Post-Increment
Table Write with Post-Decrement
Table Write with Pre-Increment
2
Note 1: When a PORT register is modified as a function of itself (e.g., MOVF PORTB, 1, 0), the value used will be
that value present on the pins themselves. For example, if the data latch is ‘1’ for a pin configured as input
and is driven low by an external device, the data will be written back with a ‘0’.
2: If this instruction is executed on the TMR0 register (and, where applicable, d = 1), the prescaler will be
cleared if assigned.
3: If the Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The
second cycle is executed as a NOP.
4: Some instructions are two-word instructions. The second word of these instructions will be executed as a
NOPunless the first word of the instruction retrieves the information embedded in these 16 bits. This ensures
that all program memory locations have a valid instruction.
DS39778D-page 336
© 2009 Microchip Technology Inc.
PIC18F87J11 FAMILY
25.1.1
STANDARD INSTRUCTION SET
ADDLW
ADD Literal to W
ADDWF
ADD W to f
Syntax:
ADDLW
k
Syntax:
ADDWF
f {,d {,a}}
Operands:
Operation:
Status Affected:
Encoding:
Description:
0 ≤ k ≤ 255
Operands:
0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
(W) + k → W
N, OV, C, DC, Z
Operation:
(W) + (f) → dest
0000
1111
kkkk
kkkk
Status Affected:
Encoding:
N, OV, C, DC, Z
The contents of W are added to the
8-bit literal ‘k’ and the result is placed in
W.
0010
01da
ffff
ffff
Description:
Add W to register ‘f’. If ‘d’ is ‘0’, the
result is stored in W. If ‘d’ is ‘1’, the
result is stored back in register ‘f’
(default).
Words:
Cycles:
1
1
Q Cycle Activity:
Q1
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank.
Q2
Q3
Q4
Decode
Read
literal ‘k’
Process
Data
Write to
W
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f ≤ 95 (5Fh). See
Section 25.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
Example:
ADDLW
15h
Before Instruction
10h
After Instruction
25h
W
=
W
=
Words:
Cycles:
1
1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
register ‘f’
Process
Data
Write to
destination
Example:
ADDWF
REG, 0, 0
Before Instruction
W
REG
=
=
17h
0C2h
After Instruction
W
REG
=
=
0D9h
0C2h
Note:
All PIC18 instructions may take an optional label argument preceding the instruction mnemonic for use in
symbolic addressing. If a label is used, the instruction format then becomes: {label} instruction argument(s).
© 2009 Microchip Technology Inc.
DS39778D-page 337
PIC18F87J11 FAMILY
ADDWFC
ADD W and Carry bit to f
ANDLW
AND Literal with W
Syntax:
ADDWFC
f {,d {,a}}
Syntax:
ANDLW
k
Operands:
0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
Operands:
Operation:
Status Affected:
Encoding:
Description:
0 ≤ k ≤ 255
(W) .AND. k → W
N, Z
Operation:
(W) + (f) + (C) → dest
0000
1011
kkkk
kkkk
Status Affected:
Encoding:
N,OV, C, DC, Z
The contents of W are ANDed with the
8-bit literal ‘k’. The result is placed in W.
0010
00da
ffff
ffff
Description:
Add W, the Carry flag and data memory
location ‘f’. If ‘d’ is ‘0’, the result is
placed in W. If ‘d’ is ‘1’, the result is
placed in data memory location ‘f’.
Words:
Cycles:
1
1
Q Cycle Activity:
Q1
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank.
Q2
Q3
Q4
Decode
Read literal
‘k’
Process
Data
Write to
W
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f ≤ 95 (5Fh). See
Section 25.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
Example:
ANDLW
05Fh
Before Instruction
W
=
A3h
03h
After Instruction
W
=
Words:
Cycles:
1
1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
register ‘f’
Process
Data
Write to
destination
Example:
ADDWFC
REG, 0, 1
Before Instruction
Carry bit =
1
02h
4Dh
REG
W
=
=
After Instruction
Carry bit =
0
02h
50h
REG
W
=
=
DS39778D-page 338
© 2009 Microchip Technology Inc.
PIC18F87J11 FAMILY
ANDWF
AND W with f
BC
Branch if Carry
BC
Syntax:
ANDWF
f {,d {,a}}
Syntax:
n
Operands:
0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
Operands:
Operation:
-128 ≤ n ≤ 127
if Carry bit is ‘1’,
(PC) + 2 + 2n → PC
Operation:
(W) .AND. (f) → dest
Status Affected:
Encoding:
None
Status Affected:
Encoding:
N, Z
1110
0010
nnnn
nnnn
0001
01da
ffff
ffff
Description:
If the Carry bit is ’1’, then the program
Description:
The contents of W are ANDed with
register ‘f’. If ‘d’ is ‘0’, the result is stored
in W. If ‘d’ is ‘1’, the result is stored back
in register ‘f’ (default).
will branch.
The 2’s complement number ‘2n’ is
added to the PC. Since the PC will have
incremented to fetch the next
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank.
instruction, the new address will be
PC + 2 + 2n. This instruction is then a
two-cycle instruction.
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f ≤ 95 (5Fh). See
Section 25.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
Words:
Cycles:
1
1(2)
Q Cycle Activity:
If Jump:
Q1
Q2
Q3
Q4
Decode
Read literal
‘n’
Process
Data
Write to
PC
Words:
Cycles:
1
1
No
No
No
operation
No
operation
operation
operation
Q Cycle Activity:
Q1
If No Jump:
Q1
Q2
Q3
Q4
Q2
Q3
Q4
Decode
Read
register ‘f’
Process
Data
Write to
destination
Decode
Read literal
‘n’
Process
Data
No
operation
Example:
ANDWF
REG, 0, 0
Example:
HERE
BC
5
Before Instruction
Before Instruction
W
REG
=
=
17h
C2h
PC
=
address (HERE)
After Instruction
After Instruction
If Carry
PC
If Carry
PC
=
=
=
=
1;
W
REG
=
=
02h
C2h
address (HERE + 12)
0;
address (HERE + 2)
© 2009 Microchip Technology Inc.
DS39778D-page 339
PIC18F87J11 FAMILY
BCF
Bit Clear f
BN
Branch if Negative
BN
Syntax:
BCF f, b {,a}
Syntax:
n
Operands:
0 ≤ f ≤ 255
0 ≤ b ≤ 7
a ∈ [0,1]
Operands:
Operation:
-128 ≤ n ≤ 127
if Negative bit is ‘1’,
(PC) + 2 + 2n → PC
Operation:
0 → f<b>
Status Affected:
Encoding:
None
Status Affected:
Encoding:
None
1110
0110
nnnn
nnnn
1001
bbba
ffff
ffff
Description:
If the Negative bit is ‘1’, then the
Description:
Bit ‘b’ in register ‘f’ is cleared.
program will branch.
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank.
The 2’s complement number ‘2n’ is
added to the PC. Since the PC will have
incremented to fetch the next
instruction, the new address will be
PC + 2 + 2n. This instruction is then a
two-cycle instruction.
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f ≤ 95 (5Fh). See
Section 25.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
Words:
Cycles:
1
1(2)
Q Cycle Activity:
If Jump:
Words:
Cycles:
1
1
Q1
Q2
Q3
Q4
Decode
Read literal
‘n’
Process
Data
Write to
PC
Q Cycle Activity:
Q1
Q2
Q3
Q4
No
No
No
No
operation
operation
operation
operation
Decode
Read
register ‘f’
Process
Data
Write
register ‘f’
If No Jump:
Q1
Q2
Q3
Q4
Decode
Read literal
‘n’
Process
Data
No
operation
Example:
BCF
FLAG_REG, 7, 0
Before Instruction
FLAG_REG = C7h
After Instruction
FLAG_REG = 47h
Example:
HERE
BN Jump
Before Instruction
PC
=
address (HERE)
After Instruction
If Negative
PC
If Negative
PC
=
=
=
=
1;
address (Jump)
0;
address (HERE + 2)
DS39778D-page 340
© 2009 Microchip Technology Inc.
PIC18F87J11 FAMILY
BNC
Branch if Not Carry
BNC
BNN
Branch if Not Negative
BNN
Syntax:
n
Syntax:
n
Operands:
Operation:
-128 ≤ n ≤ 127
Operands:
Operation:
-128 ≤ n ≤ 127
if Carry bit is ‘0’,
(PC) + 2 + 2n → PC
if Negative bit is ‘0’,
(PC) + 2 + 2n → PC
Status Affected:
Encoding:
None
Status Affected:
Encoding:
None
1110
0011
nnnn
nnnn
1110
0111
nnnn
nnnn
Description:
If the Carry bit is ‘0’, then the program
Description:
If the Negative bit is ‘0’, then the
will branch.
program will branch.
The 2’s complement number ‘2n’ is
added to the PC. Since the PC will have
incremented to fetch the next
The 2’s complement number ‘2n’ is
added to the PC. Since the PC will have
incremented to fetch the next
instruction, the new address will be
PC + 2 + 2n. This instruction is then a
two-cycle instruction.
instruction, the new address will be
PC + 2 + 2n. This instruction is then a
two-cycle instruction.
Words:
Cycles:
1
Words:
Cycles:
1
1(2)
1(2)
Q Cycle Activity:
If Jump:
Q Cycle Activity:
If Jump:
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Decode
Read literal
‘n’
Process
Data
Write to
PC
Decode
Read literal
‘n’
Process
Data
Write to
PC
No
No
No
No
No
No
No
No
operation
operation
operation
operation
operation
operation
operation
operation
If No Jump:
Q1
If No Jump:
Q1
Q2
Q3
Q4
Q2
Q3
Q4
Decode
Read literal
‘n’
Process
Data
No
operation
Decode
Read literal
‘n’
Process
Data
No
operation
Example:
HERE
BNC Jump
Example:
HERE
BNN Jump
Before Instruction
Before Instruction
PC
=
address (HERE)
PC
=
address (HERE)
After Instruction
After Instruction
If Carry
PC
If Carry
PC
=
=
=
=
0;
If Negative
PC
If Negative
PC
=
=
=
=
0;
address (Jump)
address (Jump)
1;
1;
address (HERE + 2)
address (HERE + 2)
© 2009 Microchip Technology Inc.
DS39778D-page 341
PIC18F87J11 FAMILY
BNOV
Branch if Not Overflow
BNOV
BNZ
Branch if Not Zero
BNZ
Syntax:
n
Syntax:
n
Operands:
Operation:
-128 ≤ n ≤ 127
Operands:
Operation:
-128 ≤ n ≤ 127
if Overflow bit is ‘0’,
(PC) + 2 + 2n → PC
if Zero bit is ‘0’,
(PC) + 2 + 2n → PC
Status Affected:
Encoding:
None
Status Affected:
Encoding:
None
1110
0101
nnnn
nnnn
1110
0001
nnnn
nnnn
Description:
If the Overflow bit is ‘0’, then the
Description:
If the Zero bit is ‘0’, then the program
program will branch.
will branch.
The 2’s complement number ‘2n’ is
added to the PC. Since the PC will have
incremented to fetch the next
The 2’s complement number ‘2n’ is
added to the PC. Since the PC will have
incremented to fetch the next
instruction, the new address will be
PC + 2 + 2n. This instruction is then a
two-cycle instruction.
instruction, the new address will be
PC + 2 + 2n. This instruction is then a
two-cycle instruction.
Words:
Cycles:
1
Words:
Cycles:
1
1(2)
1(2)
Q Cycle Activity:
If Jump:
Q Cycle Activity:
If Jump:
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Decode
Read literal
‘n’
Process
Data
Write to
PC
Decode
Read literal
‘n’
Process
Data
Write to
PC
No
No
No
No
No
No
No
No
operation
operation
operation
operation
operation
operation
operation
operation
If No Jump:
Q1
If No Jump:
Q1
Q2
Q3
Q4
Q2
Q3
Q4
Decode
Read literal
‘n’
Process
Data
No
operation
Decode
Read literal
‘n’
Process
Data
No
operation
Example:
HERE
BNOV Jump
Example:
HERE
BNZ Jump
Before Instruction
Before Instruction
PC
=
address (HERE)
PC
=
address (HERE)
After Instruction
After Instruction
If Overflow
PC
If Overflow
PC
=
=
=
=
0;
If Zero
PC
If Zero
PC
=
=
=
=
0;
address (Jump)
address (Jump)
1;
1;
address (HERE + 2)
address (HERE + 2)
DS39778D-page 342
© 2009 Microchip Technology Inc.
PIC18F87J11 FAMILY
BRA
Unconditional Branch
BRA
BSF
Bit Set f
Syntax:
n
Syntax:
BSF f, b {,a}
Operands:
Operation:
Status Affected:
Encoding:
Description:
-1024 ≤ n ≤ 1023
(PC) + 2 + 2n → PC
None
Operands:
0 ≤ f ≤ 255
0 ≤ b ≤ 7
a ∈ [0,1]
Operation:
1→ f<b>
1101
0nnn
nnnn
nnnn
Status Affected:
Encoding:
None
Add the 2’s complement number ‘2n’ to
the PC. Since the PC will have
incremented to fetch the next
instruction, the new address will be
PC + 2 + 2n. This instruction is a
two-cycle instruction.
1000
bbba
ffff
ffff
Description:
Bit ‘b’ in register ‘f’ is set.
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank.
Words:
Cycles:
1
2
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f ≤ 95 (5Fh). See
Section 25.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read literal
‘n’
Process
Data
Write to
PC
No
operation
No
operation
No
operation
No
operation
Words:
Cycles:
1
1
Q Cycle Activity:
Q1
Example:
HERE
BRA Jump
Q2
Q3
Q4
Before Instruction
Decode
Read
register ‘f’
Process
Data
Write
register ‘f’
PC
=
=
address (HERE)
address (Jump)
After Instruction
PC
Example:
BSF
FLAG_REG, 7, 1
0Ah
8Ah
Before Instruction
FLAG_REG
After Instruction
FLAG_REG
=
=
© 2009 Microchip Technology Inc.
DS39778D-page 343
PIC18F87J11 FAMILY
BTFSC
Bit Test File, Skip if Clear
BTFSS
Bit Test File, Skip if Set
Syntax:
BTFSC f, b {,a}
Syntax:
BTFSS f, b {,a}
Operands:
0 ≤ f ≤ 255
0 ≤ b ≤ 7
a ∈ [0,1]
Operands:
0 ≤ f ≤ 255
0 ≤ b < 7
a ∈ [0,1]
Operation:
skip if (f<b>) = 0
Operation:
skip if (f<b>) = 1
Status Affected:
Encoding:
None
Status Affected:
Encoding:
None
1011
bbba
ffff
ffff
1010
bbba
ffff
ffff
Description:
If bit ‘b’ in register ‘f’ is ‘0’, then the next
instruction is skipped. If bit ‘b’ is ‘0’, then
the next instruction fetched during the
current instruction execution is discarded
and a NOPis executed instead, making
this a two-cycle instruction.
Description:
If bit ‘b’ in register ‘f’ is ‘1’, then the next
instruction is skipped. If bit ‘b’ is ‘1’, then
the next instruction fetched during the
current instruction execution is discarded
and a NOPis executed instead, making
this a two-cycle instruction.
If ‘a’ is ‘0’, the Access Bank is selected. If
‘a’ is ‘1’, the BSR is used to select the
GPR bank.
If ‘a’ is ‘0’, the Access Bank is selected. If
‘a’ is ‘1’, the BSR is used to select the
GPR bank.
If ‘a’ is ‘0’ and the extended instruction set
is enabled, this instruction operates in
Indexed Literal Offset Addressing mode
whenever f ≤ 95 (5Fh). See
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates in
Indexed Literal Offset Addressing mode
whenever f ≤ 95 (5Fh). See
Section 25.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
Section 25.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
Words:
Cycles:
1
Words:
Cycles:
1
1(2)
1(2)
Note: 3 cycles if skip and followed
by a 2-word instruction.
Note: 3 cycles if skip and followed
by a 2-word instruction.
Q Cycle Activity:
Q1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Q2
Q3
Q4
Decode
Read
register ‘f’
Process
Data
No
operation
Decode
Read
register ‘f’
Process
Data
No
operation
If skip:
Q1
If skip:
Q1
Q2
Q3
Q4
Q2
Q3
Q4
No
No
No
No
No
No
No
No
operation
operation
operation
operation
operation
operation
operation
operation
If skip and followed by 2-word instruction:
If skip and followed by 2-word instruction:
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
No
No
No
No
No
No
No
No
operation
operation
operation
operation
operation
operation
operation
operation
No
No
No
No
No
No
No
No
operation
operation
operation
operation
operation
operation
operation
operation
Example:
HERE
FALSE
TRUE
BTFSC
:
:
FLAG, 1, 0
Example:
HERE
FALSE
TRUE
BTFSS
:
:
FLAG, 1, 0
Before Instruction
PC
Before Instruction
PC
=
address (HERE)
=
address (HERE)
After Instruction
After Instruction
If FLAG<1>
PC
If FLAG<1>
PC
=
=
=
=
0;
If FLAG<1>
PC
If FLAG<1>
PC
=
=
=
=
0;
address (TRUE)
1;
address (FALSE)
1;
address (FALSE)
address (TRUE)
DS39778D-page 344
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BTG
Bit Toggle f
BOV
Branch if Overflow
BOV
Syntax:
BTG f, b {,a}
Syntax:
n
Operands:
0 ≤ f ≤ 255
0 ≤ b < 7
a ∈ [0,1]
Operands:
Operation:
-128 ≤ n ≤ 127
if Overflow bit is ‘1’,
(PC) + 2 + 2n → PC
Operation:
(f<b>) → f<b>
Status Affected:
Encoding:
None
Status Affected:
Encoding:
None
1110
0100
nnnn
nnnn
0111
bbba
ffff
ffff
Description:
If the Overflow bit is ‘1’, then the
Description:
Bit ‘b’ in data memory location ‘f’ is
inverted.
program will branch.
The 2’s complement number ‘2n’ is
added to the PC. Since the PC will have
incremented to fetch the next
instruction, the new address will be
PC + 2 + 2n. This instruction is then a
two-cycle instruction.
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank.
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f ≤ 95 (5Fh). See
Section 25.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
Words:
Cycles:
1
1(2)
Q Cycle Activity:
If Jump:
Q1
Q2
Q3
Q4
Words:
Cycles:
1
1
Decode
Read literal
‘n’
Process
Data
Write to PC
Q Cycle Activity:
Q1
No
operation
No
operation
No
operation
No
operation
Q2
Q3
Q4
Decode
Read
register ‘f’
Process
Data
Write
register ‘f’
If No Jump:
Q1
Q2
Q3
Q4
Decode
Read literal
‘n’
Process
Data
No
operation
Example:
BTG
PORTC, 4, 0
Before Instruction:
PORTC
After Instruction:
PORTC
=
0111 0101 [75h]
0110 0101 [65h]
Example:
HERE
BOV Jump
Before Instruction
=
PC
=
address (HERE)
After Instruction
If Overflow
PC
If Overflow
PC
=
=
=
=
1;
address (Jump)
0;
address (HERE + 2)
© 2009 Microchip Technology Inc.
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BZ
Branch if Zero
BZ
CALL
Subroutine Call
Syntax:
n
Syntax:
CALL k {,s}
Operands:
Operation:
-128 ≤ n ≤ 127
Operands:
0 ≤ k ≤ 1048575
s ∈ [0,1]
if Zero bit is ‘1’,
(PC) + 2 + 2n → PC
Operation:
(PC) + 4 → TOS,
k → PC<20:1>;
if s = 1,
Status Affected:
Encoding:
None
1110
0000
nnnn
nnnn
(W) → WS,
(STATUS) → STATUSS,
(BSR) → BSRS
Description:
If the Zero bit is ‘1’, then the program
will branch.
Status Affected:
None
The 2’s complement number ‘2n’ is
added to the PC. Since the PC will have
incremented to fetch the next
instruction, the new address will be
PC + 2 + 2n. This instruction is then a
two-cycle instruction.
Encoding:
1st word (k<7:0>)
2nd word(k<19:8>)
1110
1111
110s
k kkk
kkkk
kkkk
7
0
8
k
kkk kkkk
19
Description:
Subroutine call of entire 2-Mbyte
memory range. First, return address
(PC + 4) is pushed onto the return
stack. If ‘s’ = 1, the W, STATUS and
Words:
Cycles:
1
1(2)
BSR registers are also pushed into their
respective shadow registers, WS,
STATUSS and BSRS. If ‘s’ = 0, no
update occurs (default). Then, the
20-bit value ‘k’ is loaded into PC<20:1>.
CALLis a two-cycle instruction.
Q Cycle Activity:
If Jump:
Q1
Q2
Q3
Q4
Decode
Read literal
‘n’
Process
Data
Write to
PC
No
operation
No
operation
No
operation
No
operation
Words:
Cycles:
2
2
If No Jump:
Q1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Q2
Q3
Q4
Decode
Read literal
‘n’
Process
Data
No
operation
Decode
Read literal Push PC to Read literal
‘k’<7:0>,
stack
’k’<19:8>,
Write to PC
Example:
HERE
BZ Jump
No
No
No
No
Before Instruction
operation
operation
operation
operation
PC
=
address (HERE)
After Instruction
Example:
HERE
CALL THERE,1
If Zero
PC
If Zero
PC
=
=
=
=
1;
address (Jump)
Before Instruction
PC
After Instruction
0;
=
address (HERE)
address (HERE + 2)
PC
TOS
WS
BSRS
STATUSS =
=
address (THERE)
=
=
=
address (HERE + 4)
W
BSR
STATUS
DS39778D-page 346
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CLRF
Clear f
CLRWDT
Clear Watchdog Timer
Syntax:
CLRF f {,a}
Syntax:
CLRWDT
None
Operands:
0 ≤ f ≤ 255
a ∈ [0,1]
Operands:
Operation:
000h → WDT,
000h → WDT postscaler,
1→ TO,
Operation:
000h → f,
1→ Z
1→ PD
Status Affected:
Encoding:
Z
Status Affected:
Encoding:
TO, PD
0110
101a
ffff
ffff
0000
0000
0000
0100
Description:
Clears the contents of the specified
register.
Description:
CLRWDTinstruction resets the
Watchdog Timer. It also resets the
postscaler of the WDT. Status bits, TO
and PD, are set.
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank.
Words:
Cycles:
1
1
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f ≤ 95 (5Fh). See
Section 25.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
No
Process
Data
No
operation
operation
Words:
Cycles:
1
1
Example:
CLRWDT
Before Instruction
Q Cycle Activity:
Q1
WDT Counter
After Instruction
WDT Counter
WDT Postscaler
TO
=
?
Q2
Q3
Q4
Decode
Read
register ‘f’
Process
Data
Write
register ‘f’
=
=
=
=
00h
0
1
PD
1
Example:
CLRF
FLAG_REG,1
Before Instruction
FLAG_REG
After Instruction
FLAG_REG
=
=
5Ah
00h
© 2009 Microchip Technology Inc.
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CPFSEQ
Compare f with W, Skip if f = W
COMF
Complement f
Syntax:
CPFSEQ f {,a}
Syntax:
COMF f {,d {,a}}
Operands:
0 ≤ f ≤ 255
a ∈ [0,1]
Operands:
0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
Operation:
(f) – (W),
skip if (f) = (W)
(unsigned comparison)
Operation:
f → dest
Status Affected:
Encoding:
N, Z
Status Affected:
Encoding:
None
0001
11da
ffff
ffff
0110
001a
ffff
ffff
Description:
The contents of register ‘f’ are
Description:
Compares the contents of data memory
location ‘f’ to the contents of W by
performing an unsigned subtraction.
complemented. If ‘d’ is ‘0’, the result is
stored in W. If ‘d’ is ‘1’, the result is
stored back in register ‘f’ (default).
If ‘f’ = W, then the fetched instruction is
discarded and a NOPis executed
instead, making this a two-cycle
instruction.
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank.
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f ≤ 95 (5Fh). See
Section 25.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank.
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f ≤ 95 (5Fh). See
Section 25.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
Words:
Cycles:
1
1
Q Cycle Activity:
Q1
Words:
Cycles:
1
Q2
Q3
Q4
1(2)
Decode
Read
register ‘f’
Process
Data
Write to
destination
Note: 3 cycles if skip and followed
by a 2-word instruction.
Q Cycle Activity:
Q1
Example:
COMF
REG, 0, 0
Q2
Read
register ‘f’
Q3
Process
Data
Q4
No
operation
Before Instruction
Decode
REG
=
13h
After Instruction
If skip:
Q1
REG
W
=
=
13h
ECh
Q2
No
Q3
No
Q4
No
No
operation
operation
operation
operation
If skip and followed by 2-word instruction:
Q1
No
Q2
No
Q3
No
Q4
No
operation
No
operation
No
operation
No
operation
No
operation
operation
operation
operation
Example:
HERE
CPFSEQ REG, 0
NEQUAL
EQUAL
:
:
Before Instruction
PC Address
=
=
=
HERE
?
?
W
REG
After Instruction
If REG
PC
If REG
PC
=
=
≠
=
W;
Address (EQUAL)
W;
Address (NEQUAL)
DS39778D-page 348
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CPFSGT
Compare f with W, Skip if f > W
CPFSLT
Compare f with W, Skip if f < W
Syntax:
CPFSGT f {,a}
Syntax:
CPFSLT f {,a}
Operands:
0 ≤ f ≤ 255
a ∈ [0,1]
Operands:
0 ≤ f ≤ 255
a ∈ [0,1]
Operation:
(f) – (W),
skip if (f) > (W)
(unsigned comparison)
Operation:
(f) – (W),
skip if (f) < (W)
(unsigned comparison)
Status Affected:
Encoding:
None
Status Affected:
Encoding:
None
0110
010a
ffff
ffff
0110
000a
ffff
ffff
Description:
Compares the contents of data memory
location ‘f’ to the contents of the W by
performing an unsigned subtraction.
Description:
Compares the contents of data memory
location ‘f’ to the contents of W by
performing an unsigned subtraction.
If the contents of ‘f’ are greater than the
contents of WREG, then the fetched
instruction is discarded and a NOPis
executed instead, making this a
two-cycle instruction.
If the contents of ‘f’ are less than the
contents of W, then the fetched
instruction is discarded and a NOPis
executed instead, making this a
two-cycle instruction.
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank.
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank.
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f ≤ 95 (5Fh). See
Section 25.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
Words:
Cycles:
1
1(2)
Note: 3 cycles if skip and followed
by a 2-word instruction.
Q Cycle Activity:
Q1
Q2
Q3
Q4
Words:
Cycles:
1
Decode
Read
Process
Data
No
operation
1(2)
register ‘f’
Note: 3 cycles if skip and followed
by a 2-word instruction.
If skip:
Q1
Q2
Q3
Q4
Q Cycle Activity:
Q1
No
operation
No
operation
No
operation
No
operation
Q2
Read
register ‘f’
Q3
Process
Data
Q4
No
operation
Decode
If skip and followed by 2-word instruction:
Q1
Q2
Q3
Q4
If skip:
Q1
No
operation
No
operation
No
operation
No
operation
Q2
No
Q3
No
Q4
No
No
No
No
No
No
operation
operation
operation
operation
operation
operation
operation
operation
If skip and followed by 2-word instruction:
Q1
No
operation
No
Q2
No
operation
No
Q3
No
operation
No
Q4
No
operation
No
Example:
HERE
NLESS
LESS
CPFSLT REG, 1
:
:
operation
operation
operation
operation
Before Instruction
PC
W
=
=
Address (HERE)
?
Example:
HERE
CPFSGT REG, 0
NGREATER
GREATER
:
:
After Instruction
If REG
PC
If REG
PC
<
=
≥
=
W;
Address (LESS)
W;
Before Instruction
PC
W
=
=
Address (HERE)
?
Address (NLESS)
After Instruction
If REG
PC
If REG
PC
>
=
≤
=
W;
Address (GREATER)
W;
Address (NGREATER)
© 2009 Microchip Technology Inc.
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DAW
Decimal Adjust W Register
DECF
Decrement f
Syntax:
DAW
None
Syntax:
DECF f {,d {,a}}
Operands:
Operation:
Operands:
0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
If [W<3:0> > 9] or [DC = 1] then,
(W<3:0>) + 6 → W<3:0>;
else,
Operation:
(f) – 1→ dest
(W<3:0>) → W<3:0>
Status Affected:
Encoding:
C, DC, N, OV, Z
0000
01da
ffff
ffff
If [W<7:4> > 9] or [C = 1] then,
(W<7:4>) + 6 → W<7:4>,
C = 1;
Description:
Decrement register ‘f’. If ‘d’ is ‘0’, the
result is stored in W. If ‘d’ is ‘1’, the
result is stored back in register ‘f’
(default).
else,
(W<7:4>) → W<7:4>
Status Affected:
Encoding:
C
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank.
0000
0000
0000
0111
Description:
DAW adjusts the eight-bit value in W,
resulting from the earlier addition of two
variables (each in packed BCD format)
and produces a correct packed BCD
result.
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f ≤ 95 (5Fh). See
Section 25.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
Words:
Cycles:
1
1
Q Cycle Activity:
Q1
Words:
Cycles:
1
1
Q2
Q3
Q4
Decode
Read
register W
Process
Data
Write
W
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
register ‘f’
Process
Data
Write to
destination
Example 1:
DAW
Before Instruction
W
=
=
=
A5h
0
Example:
DECF
CNT,
1, 0
C
DC
0
Before Instruction
After Instruction
CNT
Z
=
01h
0
W
=
=
=
05h
1
0
=
C
After Instruction
DC
CNT
Z
=
=
00h
1
Example 2:
Before Instruction
W
=
=
=
CEh
0
0
C
DC
After Instruction
W
=
=
=
34h
1
0
C
DC
DS39778D-page 350
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DECFSZ
Decrement f, Skip if 0
DCFSNZ
Decrement f, Skip if not 0
Syntax:
DECFSZ f {,d {,a}}
Syntax:
DCFSNZ f {,d {,a}}
Operands:
0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
Operands:
0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
Operation:
(f) – 1→ dest,
skip if result = 0
Operation:
(f) – 1→ dest,
skip if result ≠ 0
Status Affected:
Encoding:
None
Status Affected:
Encoding:
None
0010
11da
ffff
ffff
0100
11da
ffff
ffff
Description:
The contents of register ‘f’ are
Description:
The contents of register ‘f’ are
decremented. If ‘d’ is ‘0’, the result is
placed in W. If ‘d’ is ‘1’, the result is
placed back in register ‘f’ (default).
decremented. If ‘d’ is ‘0’, the result is
placed in W. If ‘d’ is ‘1’, the result is
placed back in register ‘f’ (default).
If the result is ‘0’, the next instruction
which is already fetched is discarded
and a NOPis executed instead, making
it a two-cycle instruction.
If the result is not ‘0’, the next
instruction which is already fetched is
discarded and a NOPis executed
instead, making it a two-cycle
instruction.
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank.
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank.
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f ≤ 95 (5Fh). See
Section 25.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f ≤ 95 (5Fh). See
Section 25.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
Words:
Cycles:
1
Words:
Cycles:
1
1(2)
Note: 3 cycles if skip and followed
by a 2-word instruction.
1(2)
Note: 3 cycles if skip and followed
by a 2-word instruction.
Q Cycle Activity:
Q1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Q2
Q3
Q4
Decode
Read
register ‘f’
Process
Data
Write to
destination
Decode
Read
Process
Data
Write to
destination
register ‘f’
If skip:
Q1
If skip:
Q1
Q2
Q3
Q4
Q2
Q3
Q4
No
No
No
No
operation
operation
operation
operation
No
No
No
No
operation
operation
operation
operation
If skip and followed by 2-word instruction:
If skip and followed by 2-word instruction:
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
No
No
No
No
operation
operation
operation
operation
No
No
No
No
operation
operation
operation
operation
No
No
No
No
operation
operation
operation
operation
No
No
No
No
operation
operation
operation
operation
Example:
HERE
DECFSZ
GOTO
CNT, 1, 1
LOOP
Example:
HERE
ZERO
NZERO
DCFSNZ TEMP, 1, 0
:
:
CONTINUE
Before Instruction
PC
After Instruction
Before Instruction
TEMP
After Instruction
=
Address (HERE)
=
?
CNT
=
CNT – 1
0;
If CNT
=
=
≠
=
TEMP
If TEMP
PC
If TEMP
PC
=
=
=
≠
=
TEMP – 1,
0;
Address (ZERO)
0;
Address (NZERO)
PC
Address (CONTINUE)
0;
If CNT
PC
Address (HERE + 2)
© 2009 Microchip Technology Inc.
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GOTO
Unconditional Branch
GOTO
INCF
Increment f
Syntax:
k
Syntax:
INCF f {,d {,a}}
Operands:
Operation:
Status Affected:
0 ≤ k ≤ 1048575
k → PC<20:1>
None
Operands:
0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
Operation:
(f) + 1→ dest
Encoding:
1st word (k<7:0>)
2nd word(k<19:8>)
Status Affected:
Encoding:
C, DC, N, OV, Z
1110
1111
1111
kkk
k kkk
kkkk
kkkk
kkkk
7
0
8
k
0010
10da
ffff
ffff
19
Description:
GOTOallows an unconditional branch
Description:
The contents of register ‘f’ are
anywhere within entire 2-Mbyte memory
range. The 20-bit value ‘k’ is loaded into
PC<20:1>. GOTOis always a two-cycle
instruction.
incremented. If ‘d’ is ‘0’, the result is
placed in W. If ‘d’ is ‘1’, the result is
placed back in register ‘f’ (default).
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank.
Words:
Cycles:
2
2
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f ≤ 95 (5Fh). See
Section 25.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read literal
‘k’<7:0>,
No
operation
Read literal
‘k’<19:8>,
Write to PC
No
No
No
No
operation
operation
operation
operation
Words:
Cycles:
1
1
Example:
GOTO THERE
Q Cycle Activity:
Q1
After Instruction
Q2
Q3
Q4
PC
=
Address (THERE)
Decode
Read
register ‘f’
Process
Data
Write to
destination
Example:
INCF
CNT, 1, 0
Before Instruction
CNT
Z
=
FFh
0
=
=
=
C
?
DC
?
After Instruction
CNT
Z
=
00h
1
=
=
=
C
1
DC
1
DS39778D-page 352
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INFSNZ
Increment f, Skip if not 0
INCFSZ
Increment f, Skip if 0
Syntax:
INFSNZ f {,d {,a}}
Syntax:
INCFSZ f {,d {,a}}
Operands:
0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
Operands:
0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
Operation:
(f) + 1→ dest,
skip if result ≠ 0
Operation:
(f) + 1→ dest,
skip if result = 0
Status Affected:
Encoding:
None
Status Affected:
Encoding:
None
0100
10da
ffff
ffff
0011
11da
ffff
ffff
Description:
The contents of register ‘f’ are
Description:
The contents of register ‘f’ are
incremented. If ‘d’ is ‘0’, the result is
placed in W. If ‘d’ is ‘1’, the result is
placed back in register ‘f’ (default).
incremented. If ‘d’ is ‘0’, the result is
placed in W. If ‘d’ is ‘1’, the result is
placed back in register ‘f’. (default)
If the result is not ‘0’, the next
instruction which is already fetched is
discarded and a NOPis executed
instead, making it a two-cycle
instruction.
If the result is ‘0’, the next instruction
which is already fetched is discarded
and a NOPis executed instead, making
it a two-cycle instruction.
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank.
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank.
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f ≤ 95 (5Fh). See
Section 25.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f ≤ 95 (5Fh). See
Section 25.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
Words:
Cycles:
1
Words:
Cycles:
1
1(2)
1(2)
Note: 3 cycles if skip and followed
by a 2-word instruction.
Note: 3 cycles if skip and followed
by a 2-word instruction.
Q Cycle Activity:
Q1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Q2
Q3
Q4
Decode
Read
register ‘f’
Process
Data
Write to
destination
Decode
Read
register ‘f’
Process
Data
Write to
destination
If skip:
Q1
If skip:
Q1
Q2
Q3
Q4
Q2
Q3
Q4
No
No
No
No
No
No
No
No
operation
operation
operation
operation
operation
operation
operation
operation
If skip and followed by 2-word instruction:
If skip and followed by 2-word instruction:
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
No
No
No
No
No
No
No
No
operation
operation
operation
operation
operation
operation
operation
operation
No
No
No
No
No
No
No
No
operation
operation
operation
operation
operation
operation
operation
operation
Example:
HERE
NZERO
ZERO
INCFSZ
:
:
CNT, 1, 0
Example:
HERE
ZERO
NZERO
INFSNZ REG, 1, 0
Before Instruction
PC
After Instruction
Before Instruction
PC
After Instruction
=
Address (HERE)
=
Address (HERE)
REG
If REG
PC
If REG
PC
=
REG + 1
CNT
If CNT
PC
If CNT
PC
=
CNT + 1
≠
=
=
=
0;
=
=
≠
=
0;
Address (NZERO)
0;
Address (ZERO)
Address (ZERO)
0;
Address (NZERO)
© 2009 Microchip Technology Inc.
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IORLW
Inclusive OR Literal with W
IORLW
IORWF
Inclusive OR W with f
Syntax:
k
Syntax:
IORWF f {,d {,a}}
Operands:
Operation:
Status Affected:
Encoding:
Description:
0 ≤ k ≤ 255
(W) .OR. k → W
N, Z
Operands:
0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
Operation:
(W) .OR. (f) → dest
0000
1001
kkkk
kkkk
Status Affected:
Encoding:
N, Z
The contents of W are ORed with the
eight-bit literal ‘k’. The result is placed
in W.
0001
00da
ffff
ffff
Description:
Inclusive OR W with register ‘f’. If ‘d’ is
‘0’, the result is placed in W. If ‘d’ is ‘1’,
the result is placed back in register ‘f’
(default).
Words:
Cycles:
1
1
Q Cycle Activity:
Q1
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank.
Q2
Q3
Q4
Decode
Read
literal ‘k’
Process
Data
Write to
W
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f ≤ 95 (5Fh). See
Section 25.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
Example:
IORLW
35h
Before Instruction
W
=
9Ah
BFh
After Instruction
W
=
Words:
Cycles:
1
1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
register ‘f’
Process
Data
Write to
destination
Example:
IORWF RESULT, 0, 1
Before Instruction
RESULT =
13h
91h
W
=
After Instruction
RESULT =
13h
93h
W
=
DS39778D-page 354
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LFSR
Load FSR
MOVF
Move f
Syntax:
LFSR f, k
Syntax:
MOVF f {,d {,a}}
Operands:
0 ≤ f ≤ 2
0 ≤ k ≤ 4095
Operands:
0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
Operation:
k → FSRf
Operation:
f → dest
Status Affected:
Encoding:
None
Status Affected:
Encoding:
N, Z
1110
1111
1110
0000
00ff
k kkk
k kkk
11
kkkk
0101
00da
ffff
ffff
7
Description:
The 12-bit literal ‘k’ is loaded into the
file select register pointed to by ‘f’.
Description:
The contents of register ‘f’ are moved to
a destination dependent upon the
status of ‘d’. If ‘d’ is ‘0’, the result is
placed in W. If ‘d’ is ‘1’, the result is
placed back in register ‘f’ (default).
Location ‘f’ can be anywhere in the
256-byte bank.
Words:
Cycles:
2
2
Q Cycle Activity:
Q1
Q2
Q3
Q4
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank.
Decode
Read literal
‘k’ MSB
Process
Data
Write
literal ‘k’
MSB to
FSRfH
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f ≤ 95 (5Fh). See
Section 25.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
Decode
Read literal
‘k’ LSB
Process
Data
Write literal
‘k’ to FSRfL
Example:
LFSR 2, 3ABh
After Instruction
FSR2H
FSR2L
=
=
03h
ABh
Words:
Cycles:
1
1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
register ‘f’
Process
Data
Write
W
Example:
MOVF
REG, 0, 0
Before Instruction
REG
W
=
=
22h
FFh
After Instruction
REG
W
=
=
22h
22h
© 2009 Microchip Technology Inc.
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MOVFF
Move f to f
MOVFF f ,f
MOVLB
Move Literal to Low Nibble in BSR
MOVLW
Syntax:
Syntax:
k
s
d
Operands:
0 ≤ f ≤ 4095
Operands:
Operation:
Status Affected:
Encoding:
Description:
0 ≤ k ≤ 255
k → BSR
None
s
0 ≤ f ≤ 4095
d
Operation:
(f ) → f
s
d
Status Affected:
None
0000
0001
kkkk
kkkk
Encoding:
1st word (source)
2nd word (destin.)
The eight-bit literal ‘k’ is loaded into the
Bank Select Register (BSR). The value
of BSR<7:4> always remains ‘0’
1100
1111
ffff
ffff
ffff
ffff
ffff
ffff
s
d
Description:
The contents of source register ‘f ’ are
regardless of the value of k :k .
s
7 4
moved to destination register ‘f ’.
d
Words:
Cycles:
1
1
Location of source ‘f ’ can be anywhere
s
in the 4096-byte data space (000h to
FFFh) and location of destination ‘f ’
can also be anywhere from 000h to
FFFh.
d
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
literal ‘k’
Process
Data
Write literal
‘k’ to BSR
Either source or destination can be W
(a useful special situation).
MOVFFis particularly useful for
transferring a data memory location to a
peripheral register (such as the transmit
buffer or an I/O port).
Example:
MOVLB
5
Before Instruction
BSR Register =
After Instruction
BSR Register =
02h
05h
The MOVFFinstruction cannot use the
PCL, TOSU, TOSH or TOSL as the
destination register
Words:
Cycles:
2
2
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
register ‘f’
(src)
Process
Data
No
operation
Decode
No
operation
No
operation
Write
register ‘f’
(dest)
No dummy
read
Example:
MOVFF
REG1, REG2
Before Instruction
REG1
REG2
=
=
33h
11h
After Instruction
REG1
REG2
=
=
33h
33h
DS39778D-page 356
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MOVLW
Move Literal to W
MOVLW
MOVWF
Move W to f
Syntax:
k
Syntax:
MOVWF f {,a}
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
0 ≤ k ≤ 255
k → W
None
Operands:
0 ≤ f ≤ 255
a ∈ [0,1]
Operation:
(W) → f
Status Affected:
Encoding:
None
0000
1110
kkkk
kkkk
0110
111a
ffff
ffff
The eight-bit literal ‘k’ is loaded into W.
Description:
Move data from W to register ‘f’.
Location ‘f’ can be anywhere in the
256-byte bank.
1
1
Cycles:
Q Cycle Activity:
Q1
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank.
Q2
Q3
Q4
Decode
Read
literal ‘k’
Process
Data
Write to
W
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f ≤ 95 (5Fh). See
Section 25.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
Example:
MOVLW
5Ah
After Instruction
W
=
5Ah
Words:
Cycles:
1
1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
register ‘f’
Process
Data
Write
register ‘f’
Example:
MOVWF
REG, 0
Before Instruction
W
REG
=
=
4Fh
FFh
After Instruction
W
REG
=
=
4Fh
4Fh
© 2009 Microchip Technology Inc.
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MULLW
Multiply Literal with W
MULWF
Multiply W with f
Syntax:
MULLW
k
Syntax:
MULWF f {,a}
Operands:
Operation:
Status Affected:
Encoding:
Description:
0 ≤ k ≤ 255
Operands:
0 ≤ f ≤ 255
a ∈ [0,1]
(W) x k → PRODH:PRODL
Operation:
(W) x (f) → PRODH:PRODL
None
Status Affected:
Encoding:
None
0000
1101
kkkk
kkkk
0000
001a
ffff
ffff
An unsigned multiplication is carried
out between the contents of W and the
8-bit literal ‘k’. The 16-bit result is
placed in PRODH:PRODL register pair.
PRODH contains the high byte.
Description:
An unsigned multiplication is carried out
between the contents of W and the
register file location ‘f’. The 16-bit result is
stored in the PRODH:PRODL register
pair. PRODH contains the high byte. Both
W and ‘f’ are unchanged.
W is unchanged.
None of the Status flags are affected.
None of the Status flags are affected.
Note that neither Overflow nor Carry is
possible in this operation. A Zero result
is possible but not detected.
Note that neither Overflow nor Carry is
possible in this operation. A Zero result is
possible but not detected.
Words:
Cycles:
1
1
If ‘a’ is ‘0’, the Access Bank is selected. If
‘a’ is ‘1’, the BSR is used to select the
GPR bank.
Q Cycle Activity:
Q1
Q2
Q3
Q4
If ‘a’ is ‘0’ and the extended instruction set
is enabled, this instruction operates in
Indexed Literal Offset Addressing mode
whenever f ≤ 95 (5Fh). See
Section 25.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
Decode
Read
literal ‘k’
Process
Data
Write
registers
PRODH:
PRODL
Example:
MULLW
0C4h
Words:
Cycles:
1
1
Before Instruction
W
PRODH
PRODL
=
=
=
E2h
?
?
Q Cycle Activity:
Q1
Q2
Q3
Q4
After Instruction
Decode
Read
register ‘f’
Process
Data
Write
W
PRODH
PRODL
=
=
=
E2h
ADh
08h
registers
PRODH:
PRODL
Example:
MULWF
REG, 1
Before Instruction
W
=
=
=
=
C4h
REG
B5h
?
PRODH
PRODL
?
After Instruction
W
=
=
=
=
C4h
B5h
8Ah
94h
REG
PRODH
PRODL
DS39778D-page 358
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NEGF
Negate f
NOP
No Operation
Syntax:
NEGF f {,a}
Syntax:
NOP
Operands:
0 ≤ f ≤ 255
a ∈ [0,1]
Operands:
Operation:
Status Affected:
Encoding:
None
No operation
None
Operation:
(f) + 1→ f
Status Affected:
Encoding:
N, OV, C, DC, Z
0000
1111
0000
xxxx
0000
xxxx
0000
xxxx
0110
110a
ffff
ffff
Description:
Location ‘f’ is negated using two’s
complement. The result is placed in the
data memory location ‘f’.
Description:
Words:
No operation.
1
1
Cycles:
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank.
Q Cycle Activity:
Q1
Q2
Q3
No
operation
Q4
Decode
No
operation
No
operation
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f ≤ 95 (5Fh). See
Section 25.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
Example:
None.
Words:
Cycles:
1
1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
register ‘f’
Process
Data
Write
register ‘f’
Example:
NEGF
REG, 1
Before Instruction
REG
After Instruction
REG
=
0011 1010 [3Ah]
1100 0110 [C6h]
=
© 2009 Microchip Technology Inc.
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POP
Pop Top of Return Stack
PUSH
Push Top of Return Stack
Syntax:
POP
Syntax:
PUSH
Operands:
Operation:
Status Affected:
Encoding:
Description:
None
Operands:
Operation:
Status Affected:
Encoding:
Description:
None
(TOS) → bit bucket
(PC + 2) → TOS
None
None
0000
0000
0000
0110
0000
0000
0000
0101
The TOS value is pulled off the return
stack and is discarded. The TOS value
then becomes the previous value that
was pushed onto the return stack.
This instruction is provided to enable
the user to properly manage the return
stack to incorporate a software stack.
The PC + 2 is pushed onto the top of
the return stack. The previous TOS
value is pushed down on the stack.
This instruction allows implementing a
software stack by modifying TOS and
then pushing it onto the return stack.
Words:
Cycles:
1
1
Words:
Cycles:
1
1
Q Cycle Activity:
Q1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Q2
Q3
Q4
Decode
PUSH
No
No
Decode
No
operation
POP TOS
value
No
operation
PC + 2 onto
return stack
operation
operation
Example:
POP
Example:
PUSH
GOTO
NEW
Before Instruction
Before Instruction
TOS
Stack (1 level down)
TOS
PC
=
=
345Ah
0124h
=
=
0031A2h
014332h
After Instruction
After Instruction
PC
=
=
=
0126h
0126h
345Ah
TOS
TOS
PC
=
=
014332h
NEW
Stack (1 level down)
DS39778D-page 360
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RCALL
Relative Call
RCALL
RESET
Reset
Syntax:
n
Syntax:
RESET
None
Operands:
Operation:
-1024 ≤ n ≤ 1023
Operands:
Operation:
(PC) + 2 → TOS,
(PC) + 2 + 2n → PC
Reset all registers and flags that are
affected by a MCLR Reset.
Status Affected:
Encoding:
None
Status Affected:
Encoding:
All
1101
1nnn
nnnn
nnnn
0000
0000
1111
1111
Description:
Subroutine call with a jump up to 1K
from the current location. First, return
address (PC + 2) is pushed onto the
stack. Then, add the 2’s complement
number ‘2n’ to the PC. Since the PC will
have incremented to fetch the next
instruction, the new address will be
PC + 2 + 2n. This instruction is a
two-cycle instruction.
Description:
This instruction provides a way to
execute a MCLR Reset in software.
Words:
Cycles:
1
1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Start
reset
No
operation
No
operation
Words:
Cycles:
1
2
Example:
RESET
Q Cycle Activity:
Q1
After Instruction
Registers =
Q2
Q3
Q4
Reset Value
Reset Value
Flags*
=
Decode
Read literal
‘n’
Process
Data
Write to PC
PUSH PC
to stack
No
No
No
No
operation
operation
operation
operation
Example:
HERE
RCALL Jump
Before Instruction
PC
After Instruction
PC
TOS =
=
Address (HERE)
=
Address (Jump)
Address (HERE + 2)
© 2009 Microchip Technology Inc.
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RETFIE
Return from Interrupt
RETLW
Return Literal to W
RETLW
Syntax:
RETFIE {s}
Syntax:
k
Operands:
Operation:
s ∈ [0,1]
Operands:
Operation:
0 ≤ k ≤ 255
(TOS) → PC,
k → W,
1→ GIE/GIEH or PEIE/GIEL;
if s = 1,
(TOS) → PC,
PCLATU, PCLATH are unchanged
(WS) → W,
(STATUSS) → STATUS,
(BSRS) → BSR,
Status Affected:
Encoding:
None
0000
1100
kkkk
kkkk
PCLATU, PCLATH are unchanged
Description:
W is loaded with the eight-bit literal ‘k’.
The program counter is loaded from the
top of the stack (the return address).
The high address latch (PCLATH)
remains unchanged.
Status Affected:
Encoding:
GIE/GIEH, PEIE/GIEL.
0000
0000
0001
000s
Description:
Return from interrupt. Stack is popped
and Top-of-Stack (TOS) is loaded into
the PC. Interrupts are enabled by
setting either the high or low-priority
global interrupt enable bit. If ‘s’ = 1, the
contents of the shadow registers WS,
STATUSS and BSRS are loaded into
their corresponding registers W,
Words:
Cycles:
1
2
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
literal ‘k’
Process
Data
POP PC
from stack,
write to W
STATUS and BSR. If ‘s’ = 0, no update
of these registers occurs (default).
No
operation
No
No
No
Words:
Cycles:
1
2
operation
operation
operation
Q Cycle Activity:
Q1
Example:
Q2
Q3
Q4
CALL TABLE ; W contains table
; offset value
Decode
No
operation
No
operation
POP PC
from stack
; W now has
; table value
Set GIEH or
GIEL
:
No
operation
No
operation
No
operation
No
operation
TABLE
ADDWF PCL ; W = offset
RETLW k0
RETLW k1
:
; Begin table
;
Example:
RETFIE
1
After Interrupt
:
PC
=
=
=
=
=
TOS
WS
RETLW kn
; End of table
W
BSR
STATUS
BSRS
STATUSS
1
Before Instruction
GIE/GIEH, PEIE/GIEL
W
=
07h
After Instruction
W
=
value of kn
DS39778D-page 362
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RETURN
Return from Subroutine
RLCF
Rotate Left f through Carry
Syntax:
RETURN {s}
Syntax:
RLCF f {,d {,a}}
Operands:
Operation:
s ∈ [0,1]
Operands:
0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
(TOS) → PC;
if s = 1,
(WS) → W,
Operation:
(f<n>) → dest<n + 1>,
(f<7>) → C,
(C) → dest<0>
(STATUSS) → STATUS,
(BSRS) → BSR,
PCLATU, PCLATH are unchanged
Status Affected:
Encoding:
C, N, Z
Status Affected:
Encoding:
None
0011
01da
ffff
ffff
0000
0000
0001
001s
Description:
The contents of register ‘f’ are rotated
one bit to the left through the Carry flag.
If ‘d’ is ‘0’, the result is placed in W. If ‘d’
is ‘1’, the result is stored back in register
‘f’ (default).
Description:
Return from subroutine. The stack is
popped and the top of the stack (TOS)
is loaded into the program counter. If
‘s’= 1, the contents of the shadow
registers WS, STATUSS and BSRS are
loaded into their corresponding
registers W, STATUS and BSR. If
‘s’ = 0, no update of these registers
occurs (default).
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank.
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f ≤ 95 (5Fh). See
Section 25.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
Words:
Cycles:
1
2
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
No
operation
Process
Data
POP PC
register f
C
from stack
No
operation
No
operation
No
operation
No
operation
Words:
Cycles:
1
1
Q Cycle Activity:
Q1
Example:
RETURN
Q2
Q3
Q4
Decode
Read
register ‘f’
Process
Data
Write to
destination
After Instruction:
PC = TOS
Example:
RLCF
REG, 0, 0
Before Instruction
REG
C
=
=
1110 0110
0
After Instruction
REG
W
C
=
=
=
1110 0110
1100 1100
1
© 2009 Microchip Technology Inc.
DS39778D-page 363
PIC18F87J11 FAMILY
RLNCF
Rotate Left f (No Carry)
RRCF
Rotate Right f through Carry
Syntax:
RLNCF f {,d {,a}}
Syntax:
RRCF f {,d {,a}}
Operands:
0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
Operands:
0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
Operation:
(f<n>) → dest<n + 1>,
(f<7>) → dest<0>
Operation:
(f<n>) → dest<n – 1>,
(f<0>) → C,
(C) → dest<7>
Status Affected:
Encoding:
N, Z
Status Affected:
Encoding:
C, N, Z
0100
01da
ffff
ffff
0011
00da
ffff
ffff
Description:
The contents of register ‘f’ are rotated
one bit to the left. If ‘d’ is ‘0’, the result
is placed in W. If ‘d’ is ‘1’, the result is
stored back in register ‘f’ (default).
Description:
The contents of register ‘f’ are rotated
one bit to the right through the Carry
flag. If ‘d’ is ‘0’, the result is placed in W.
If ‘d’ is ‘1’, the result is placed back in
register ‘f’ (default).
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank.
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank.
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f ≤ 95 (5Fh). See
Section 25.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f ≤ 95 (5Fh). See
Section 25.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
register f
register f
C
Words:
Cycles:
1
1
Words:
Cycles:
1
1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Q Cycle Activity:
Q1
Decode
Read
register ‘f’
Process
Data
Write to
destination
Q2
Q3
Q4
Decode
Read
register ‘f’
Process
Data
Write to
destination
Example:
RLNCF
REG, 1, 0
Before Instruction
REG
After Instruction
Example:
RRCF
REG, 0, 0
=
1010 1011
0101 0111
Before Instruction
REG
=
REG
C
=
=
1110 0110
0
After Instruction
REG
W
C
=
=
=
1110 0110
0111 0011
0
DS39778D-page 364
© 2009 Microchip Technology Inc.
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RRNCF
Rotate Right f (No Carry)
SETF
Set f
Syntax:
RRNCF f {,d {,a}}
Syntax:
SETF f {,a}
Operands:
0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
Operands:
0 ≤ f ≤ 255
a ∈ [0,1]
Operation:
FFh → f
Operation:
(f<n>) → dest<n – 1>,
(f<0>) → dest<7>
Status Affected:
Encoding:
None
0110
100a
ffff
ffff
Status Affected:
Encoding:
N, Z
Description:
The contents of the specified register
are set to FFh.
0100
00da
ffff
ffff
Description:
The contents of register ‘f’ are rotated
one bit to the right. If ‘d’ is ‘0’, the result
is placed in W. If ‘d’ is ‘1’, the result is
placed back in register ‘f’ (default).
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank.
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f ≤ 95 (5Fh). See
Section 25.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
If ‘a’ is ‘0’, the Access Bank will be
selected, overriding the BSR value. If ‘a’
is ‘1’, then the bank will be selected as
per the BSR value (default).
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f ≤ 95 (5Fh). See
Section 25.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
Words:
Cycles:
1
1
Q Cycle Activity:
Q1
Q2
Q3
Q4
register f
Decode
Read
register ‘f’
Process
Data
Write
register ‘f’
Words:
Cycles:
1
1
Example:
SETF
REG,1
Q Cycle Activity:
Q1
Before Instruction
REG
After Instruction
REG
=
=
5Ah
FFh
Q2
Q3
Q4
Decode
Read
register ‘f’
Process
Data
Write to
destination
Example 1:
RRNCF
REG, 1, 0
Before Instruction
REG
After Instruction
REG
=
1101 0111
1110 1011
RRNCF REG, 0, 0
=
Example 2:
Before Instruction
W
REG
=
=
?
1101 0111
After Instruction
W
REG
=
=
1110 1011
1101 0111
© 2009 Microchip Technology Inc.
DS39778D-page 365
PIC18F87J11 FAMILY
SLEEP
Enter Sleep Mode
SUBFWB
Subtract f from W with Borrow
Syntax:
SLEEP
None
Syntax:
SUBFWB f {,d {,a}}
Operands:
Operation:
Operands:
0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
00h → WDT,
0→ WDT postscaler,
1→ TO,
Operation:
(W) – (f) – (C) → dest
0→ PD
Status Affected:
Encoding:
N, OV, C, DC, Z
Status Affected:
Encoding:
TO, PD
0101
01da
ffff
ffff
0000
0000
0000
0011
Description:
Subtract register ‘f’ and Carry flag
(borrow) from W (2’s complement
method). If ‘d’ is ‘0’, the result is stored in
W. If ‘d’ is ‘1’, the result is stored in
register ‘f’ (default).
Description:
The Power-Down status bit (PD) is
cleared. The Time-out status bit (TO)
is set. The Watchdog Timer and its
postscaler are cleared.
The processor is put into Sleep mode
with the oscillator stopped.
If ‘a’ is ‘0’, the Access Bank is selected. If
‘a’ is ‘1’, the BSR is used to select the
GPR bank.
Words:
Cycles:
1
1
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates in
Indexed Literal Offset Addressing mode
whenever f ≤ 95 (5Fh). See
Q Cycle Activity:
Q1
Q2
Q3
Q4
Section 25.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
Decode
No
operation
Process
Data
Go to
Sleep
Words:
Cycles:
1
1
Example:
SLEEP
Before Instruction
TO
PD
=
=
?
?
Q Cycle Activity:
Q1
Q2
Q3
Q4
After Instruction
Decode
Read
register ‘f’
Process
Data
Write to
destination
TO
PD
=
=
1 †
0
Example 1:
SUBFWB
REG, 1, 0
†
If WDT causes wake-up, this bit is cleared.
Before Instruction
REG
W
C
=
=
=
3
2
1
After Instruction
REG
W
C
=
FF
2
=
=
=
=
0
Z
0
1
N
; result is negative
Example 2:
Before Instruction
SUBFWB
REG, 0, 0
REG
W
C
=
=
=
2
5
1
After Instruction
REG
W
C
=
2
3
1
0
=
=
=
=
Z
N
0
; result is positive
Example 3:
SUBFWB
REG, 1, 0
Before Instruction
REG
W
C
=
=
=
1
2
0
After Instruction
REG
W
C
=
0
2
1
1
0
=
=
=
=
Z
; result is zero
N
DS39778D-page 366
© 2009 Microchip Technology Inc.
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SUBLW
Subtract W from Literal
SUBLW
SUBWF
Subtract W from f
Syntax:
k
Syntax:
SUBWF f {,d {,a}}
Operands:
Operation:
Status Affected:
Encoding:
Description:
0 ≤ k ≤ 255
Operands:
0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
k – (W) → W
N, OV, C, DC, Z
Operation:
(f) – (W) → dest
0000
1000
kkkk
kkkk
Status Affected:
Encoding:
N, OV, C, DC, Z
W is subtracted from the eight-bit
literal ‘k’. The result is placed in W.
0101
11da
ffff
ffff
Description:
Subtract W from register ‘f’ (2’s
Words:
Cycles:
1
1
complement method). If ‘d’ is ‘0’, the
result is stored in W. If ‘d’ is ‘1’, the result
is stored back in register ‘f’ (default).
Q Cycle Activity:
Q1
Q2
Q3
Q4
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank.
Decode
Read
literal ‘k’
Process
Data
Write to
W
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f ≤ 95 (5Fh). See
Section 25.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
Example 1:
SUBLW 02h
Before Instruction
W
C
=
=
01h
?
After Instruction
W
C
Z
=
01h
=
=
=
1
0
0
; result is positive
Words:
Cycles:
1
1
N
Example 2:
Before Instruction
SUBLW 02h
Q Cycle Activity:
Q1
Q2
Q3
Q4
W
C
=
=
02h
?
Decode
Read
register ‘f’
Process
Data
Write to
destination
After Instruction
W
C
Z
=
00h
Example 1:
SUBWF
REG, 1, 0
=
=
=
1
1
0
; result is zero
Before Instruction
N
REG
W
C
=
=
=
3
2
?
Example 3:
Before Instruction
SUBLW 02h
After Instruction
W
C
=
=
03h
?
REG
W
C
=
1
2
1
0
0
=
=
=
=
; result is positive
After Instruction
Z
W
C
Z
=
FFh ; (2’s complement)
N
=
=
=
0
0
1
; result is negative
Example 2:
SUBWF
REG, 0, 0
N
Before Instruction
REG
W
C
=
=
=
2
2
?
After Instruction
REG
W
C
=
2
0
1
1
0
=
=
=
=
; result is zero
Z
N
Example 3:
Before Instruction
SUBWF
REG, 1, 0
REG
W
C
=
=
=
1
2
?
After Instruction
REG
W
C
=
FFh ;(2’s complement)
2
0
0
1
=
=
=
=
; result is negative
Z
N
© 2009 Microchip Technology Inc.
DS39778D-page 367
PIC18F87J11 FAMILY
SUBWFB
Subtract W from f with Borrow
SWAPF
Swap f
Syntax:
SUBWFB f {,d {,a}}
Syntax:
SWAPF f {,d {,a}}
Operands:
0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
Operands:
0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
Operation:
(f) – (W) – (C) → dest
Operation:
(f<3:0>) → dest<7:4>,
(f<7:4>) → dest<3:0>
Status Affected:
Encoding:
N, OV, C, DC, Z
0101
10da
ffff
ffff
Status Affected:
Encoding:
None
Description:
Subtract W and the Carry flag (borrow)
from register ‘f’ (2’s complement
method). If ‘d’ is ‘0’, the result is stored
in W. If ‘d’ is ‘1’, the result is stored back
in register ‘f’ (default).
0011
10da
ffff
ffff
Description:
The upper and lower nibbles of register
‘f’ are exchanged. If ‘d’ is ‘0’, the result
is placed in W. If ‘d’ is ‘1’, the result is
placed in register ‘f’ (default).
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank.
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank.
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f ≤ 95 (5Fh). See
Section 25.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f ≤ 95 (5Fh). See
Section 25.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
Words:
Cycles:
1
1
Words:
Cycles:
1
1
Q Cycle Activity:
Q1
Q Cycle Activity:
Q1
Q2
Read
register ‘f’
Q3
Process
Data
Q4
Decode
Write to
destination
Q2
Q3
Q4
Decode
Read
register ‘f’
Process
Data
Write to
destination
Example 1:
SUBWFB REG, 1, 0
Before Instruction
REG
W
C
=
=
=
19h
0Dh
1
(0001 1001)
(0000 1101)
Example:
SWAPF
REG, 1, 0
Before Instruction
REG
After Instruction
=
53h
35h
After Instruction
REG
W
=
0Ch
0Dh
1
(0000 1011)
(0000 1101)
=
=
=
=
REG
=
C
Z
0
N
0
; result is positive
Example 2:
Before Instruction
SUBWFB REG, 0, 0
REG
W
C
=
=
=
1Bh
1Ah
0
(0001 1011)
(0001 1010)
After Instruction
REG
W
C
=
1Bh
00h
1
(0001 1011)
=
=
=
=
Z
1
; result is zero
N
0
Example 3:
Before Instruction
SUBWFB REG, 1, 0
REG
W
C
=
=
=
03h
0Eh
1
(0000 0011)
(0000 1101)
After Instruction
REG
=
F5h
(1111 0100)
; [2’s comp]
W
=
=
=
=
0Eh
0
0
1
(0000 1101)
C
Z
N
; result is negative
DS39778D-page 368
© 2009 Microchip Technology Inc.
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TBLRD
Table Read
TBLRD
Table Read (Continued)
Syntax:
TBLRD ( *; *+; *-; +*)
None
Example 1:
TBLRD *+ ;
Operands:
Operation:
Before Instruction
TABLAT
TBLPTR
MEMORY(00A356h)
=
=
=
55h
00A356h
34h
if TBLRD *,
(Prog Mem (TBLPTR)) → TABLAT,
TBLPTR – No Change;
if TBLRD *+,
(Prog Mem (TBLPTR)) → TABLAT,
(TBLPTR) + 1→ TBLPTR;
if TBLRD *-,
(Prog Mem (TBLPTR)) → TABLAT,
(TBLPTR) – 1→ TBLPTR;
if TBLRD +*,
(TBLPTR) + 1→ TBLPTR,
(Prog Mem (TBLPTR)) → TABLAT
After Instruction
TABLAT
TBLPTR
=
=
34h
00A357h
Example 2:
TBLRD +* ;
Before Instruction
TABLAT
TBLPTR
MEMORY(01A357h)
MEMORY(01A358h)
After Instruction
=
=
=
=
AAh
01A357h
12h
34h
TABLAT
TBLPTR
=
=
34h
01A358h
Status Affected: None
Encoding:
0000
0000
0000
10nn
nn=0 *
=1 *+
=2 *-
=3 +*
Description:
This instruction is used to read the contents
of Program Memory (P.M.). To address the
program memory, a pointer called Table
Pointer (TBLPTR) is used.
The TBLPTR (a 21-bit pointer) points to
each byte in the program memory. TBLPTR
has a 2-Mbyte address range.
TBLPTR<0> = 0:Least Significant Byte of
Program Memory Word
TBLPTR<0> = 1:Most Significant Byte of
Program Memory Word
The TBLRDinstruction can modify the value
of TBLPTR as follows:
•
•
•
•
no change
post-increment
post-decrement
pre-increment
Words:
Cycles:
1
2
Q Cycle Activity:
Q1
Q2
No
Q3
No
Q4
Decode
No
operation
operation
operation
No
No operation
No
No operation
(Write
TABLAT)
operation (Read Program operation
Memory)
© 2009 Microchip Technology Inc.
DS39778D-page 369
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TBLWT
Table Write
TBLWT
Table Write (Continued)
Syntax:
TBLWT ( *; *+; *-; +*)
None
Example 1:
TBLWT *+;
Operands:
Operation:
Before Instruction
TABLAT
TBLPTR
HOLDING REGISTER
(00A356h)
=
=
55h
if TBLWT*,
00A356h
(TABLAT) → Holding Register,
TBLPTR – No Change;
if TBLWT*+,
(TABLAT) → Holding Register,
(TBLPTR) + 1→ TBLPTR;
if TBLWT*-,
(TABLAT) → Holding Register,
(TBLPTR) – 1→ TBLPTR;
if TBLWT+*,
(TBLPTR) + 1→ TBLPTR,
(TABLAT) → Holding Register
=
FFh
After Instructions (table write completion)
TABLAT
TBLPTR
HOLDING REGISTER
(00A356h)
=
=
55h
00A357h
=
55h
Example 2:
TBLWT +*;
Before Instruction
TABLAT
TBLPTR
=
=
34h
01389Ah
HOLDING REGISTER
(01389Ah)
HOLDING REGISTER
(01389Bh)
Status Affected: None
=
FFh
Encoding:
0000
0000
0000
11nn
nn=0 *
=1 *+
=2 *-
=3 +*
=
FFh
After Instruction (table write completion)
TABLAT
TBLPTR
HOLDING REGISTER
(01389Ah)
HOLDING REGISTER
(01389Bh)
=
=
34h
01389Bh
Description:
This instruction uses the 3 LSBs of
TBLPTR to determine which of the
8 holding registers the TABLAT is written
to. The holding registers are used to
program the contents of Program Memory
(P.M.). (Refer to Section 5.0 “Memory
Organization” for additional details on
programming Flash memory.)
=
=
FFh
34h
The TBLPTR (a 21-bit pointer) points to
each byte in the program memory.
TBLPTR has a 2-Mbyte address range.
The LSb of the TBLPTR selects which
byte of the program memory location to
access.
TBLPTR<0> = 0:Least Significant Byte
of Program Memory
Word
TBLPTR<0> = 1:Most Significant Byte
of Program Memory
Word
The TBLWT instruction can modify the
value of TBLPTR as follows:
•
•
•
•
no change
post-increment
post-decrement
pre-increment
Words:
1
2
Cycles:
Q Cycle Activity:
Q1
Q2
No
Q3
No
Q4
No
Decode
operation operation operation
No
No No No
operation operation operation operation
(Read
TABLAT)
(Write to
Holding
Register)
DS39778D-page 370
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TSTFSZ
Test f, Skip if 0
XORLW
Exclusive OR Literal with W
XORLW
Syntax:
TSTFSZ f {,a}
Syntax:
k
Operands:
0 ≤ f ≤ 255
a ∈ [0,1]
Operands:
Operation:
Status Affected:
Encoding:
Description:
0 ≤ k ≤ 255
(W) .XOR. k → W
N, Z
Operation:
skip if f = 0
Status Affected:
Encoding:
None
0000
1010
kkkk
kkkk
0110
011a
ffff
ffff
The contents of W are XORed with
the 8-bit literal ‘k’. The result is placed
in W.
Description:
If ‘f’ = 0, the next instruction fetched
during the current instruction execution
is discarded and a NOPis executed,
making this a two-cycle instruction.
Words:
Cycles:
1
1
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank.
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
literal ‘k’
Process
Data
Write to
W
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f ≤ 95 (5Fh). See
Section 25.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
Example:
XORLW
0AFh
Before Instruction
W
=
B5h
1Ah
After Instruction
Words:
Cycles:
1
W
=
1(2)
Note: 3 cycles if skip and followed
by a 2-word instruction.
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
register ‘f’
Process
Data
No
operation
If skip:
Q1
Q2
Q3
Q4
No
No
No
No
operation
operation
operation
operation
If skip and followed by 2-word instruction:
Q1
Q2
Q3
Q4
No
No
No
No
operation
operation
operation
operation
No
No
No
No
operation
operation
operation
operation
Example:
HERE
NZERO
ZERO
TSTFSZ CNT, 1
:
:
Before Instruction
PC
=
Address (HERE)
After Instruction
If CNT
PC
If CNT
PC
=
=
≠
=
00h,
Address (ZERO)
00h,
Address (NZERO)
© 2009 Microchip Technology Inc.
DS39778D-page 371
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XORWF
Exclusive OR W with f
Syntax:
XORWF f {,d {,a}}
Operands:
0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
Operation:
(W) .XOR. (f) → dest
Status Affected:
Encoding:
N, Z
0001
10da
ffff
ffff
Description:
Exclusive OR the contents of W with
register ‘f’. If ‘d’ is ‘0’, the result is stored
in W. If ‘d’ is ‘1’, the result is stored back
in the register ‘f’ (default).
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank.
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f ≤ 95 (5Fh). See
Section 25.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
Words:
Cycles:
1
1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
register ‘f’
Process
Data
Write to
destination
Example:
XORWF
REG, 1, 0
Before Instruction
REG
W
=
=
AFh
B5h
After Instruction
REG
W
=
=
1Ah
B5h
DS39778D-page 372
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A summary of the instructions in the extended instruc-
tion set is provided in Table 25-3. Detailed descriptions
are provided in Section 25.2.2 “Extended Instruction
Set”. The opcode field descriptions in Table 25-1 (page
332) apply to both the standard and extended PIC18
instruction sets.
25.2 Extended Instruction Set
In addition to the standard 75 instructions of the PIC18
instruction set, the PIC18F87J11 Family family of
devices also provide an optional extension to the core
CPU functionality. The added features include eight
additional instructions that augment Indirect and
Indexed Addressing operations and the implementa-
tion of Indexed Literal Offset Addressing for many of
the standard PIC18 instructions.
Note:
The instruction set extension and the
Indexed Literal Offset Addressing mode
were designed for optimizing applications
written in C; the user may likely never use
these instructions directly in assembler.
The syntax for these commands is
provided as a reference for users who may
be reviewing code that has been
generated by a compiler.
The additional features of the extended instruction set
are enabled by default on unprogrammed devices.
Users must properly set or clear the XINST Configura-
tion bit during programming to enable or disable these
features.
The instructions in the extended set can all be
classified as literal operations, which either manipulate
the File Select Registers, or use them for Indexed
Addressing. Two of the instructions, ADDFSR and
SUBFSR, each have an additional special instantiation
for using FSR2. These versions (ADDULNK and
SUBULNK) allow for automatic return after execution.
25.2.1
EXTENDED INSTRUCTION SYNTAX
Most of the extended instructions use indexed argu-
ments, using one of the File Select Registers and some
offset to specify a source or destination register. When
an argument for an instruction serves as part of
Indexed Addressing, it is enclosed in square brackets
(“[ ]”). This is done to indicate that the argument is used
as an index or offset. The MPASM™ Assembler will
flag an error if it determines that an index or offset value
is not bracketed.
The extended instructions are specifically implemented
to optimize re-entrant program code (that is, code that
is recursive or that uses a software stack) written in
high-level languages, particularly C. Among other
things, they allow users working in high-level
languages to perform certain operations on data
structures more efficiently. These include:
When the extended instruction set is enabled, brackets
are also used to indicate index arguments in
byte-oriented and bit-oriented instructions. This is in
addition to other changes in their syntax. For more
details, see Section 25.2.3.1 “Extended Instruction
Syntax with Standard PIC18 Commands”.
• dynamic allocation and deallocation of software
stack space when entering and leaving
subroutines
• function pointer invocation
Note:
In the past, square brackets have been
used to denote optional arguments in the
PIC18 and earlier instruction sets. In this
text and going forward, optional
arguments are denoted by braces (“{ }”).
• software Stack Pointer manipulation
• manipulation of variables located in a software
stack
TABLE 25-3: EXTENSIONS TO THE PIC18 INSTRUCTION SET
16-Bit Instruction Word
MSb LSb
Mnemonic,
Operands
Status
Affected
Description
Cycles
ADDFSR
ADDULNK
CALLW
f, k
k
Add Literal to FSR
Add Literal to FSR2 and Return
Call Subroutine using WREG
1
2
2
2
1110 1000 ffkk kkkk
1110 1000 11kk kkkk
0000 0000 0001 0100
1110 1011 0zzz zzzz
1111 ffff ffff ffff
1110 1011 1zzz zzzz
1111 xxxx xzzz zzzz
1110 1010 kkkk kkkk
None
None
None
None
MOVSF
zs, fd Move zs (source) to 1st word
fd (destination) 2nd word
zs, zd Move zs (source) to 1st word
zd (destination) 2nd word
MOVSS
PUSHL
2
1
None
None
k
Store Literal at FSR2,
Decrement FSR2
SUBFSR
SUBULNK
f, k
k
Subtract Literal from FSR
Subtract Literal from FSR2 and
Return
1
2
1110 1001 ffkk kkkk
1110 1001 11kk kkkk
None
None
© 2009 Microchip Technology Inc.
DS39778D-page 373
PIC18F87J11 FAMILY
25.2.2
EXTENDED INSTRUCTION SET
ADDFSR
Add Literal to FSR
ADDULNK
Add Literal to FSR2 and Return
Syntax:
ADDFSR f, k
Syntax:
ADDULNK k
Operands:
0 ≤ k ≤ 63
f ∈ [ 0, 1, 2 ]
Operands:
Operation:
0 ≤ k ≤ 63
FSR2 + k → FSR2,
(TOS) → PC
None
Operation:
FSR(f) + k → FSR(f)
Status Affected:
Encoding:
None
Status Affected:
Encoding:
1110
1000
ffkk
kkkk
1110
1000
11kk
kkkk
Description:
The 6-bit literal ‘k’ is added to the
contents of the FSR specified by ‘f’.
Description:
The 6-bit literal ‘k’ is added to the
contents of FSR2. A RETURNis then
executed by loading the PC with the
TOS.
Words:
1
1
Cycles:
Q Cycle Activity:
Q1
The instruction takes two cycles to
execute; a NOPis performed during
the second cycle.
Q2
Q3
Q4
Decode
Read
literal ‘k’
Process
Data
Write to
FSR
This may be thought of as a special
case of the ADDFSRinstruction,
where f = 3 (binary ‘11’); it operates
only on FSR2.
Example:
ADDFSR 2, 23h
Words:
1
2
Before Instruction
FSR2
After Instruction
FSR2
Cycles:
=
03FFh
0422h
Q Cycle Activity:
Q1
=
Q2
Q3
Q4
Decode
Read
literal ‘k’
Process
Data
Write to
FSR
No
No
No
No
Operation
Operation
Operation
Operation
Example:
ADDULNK 23h
Before Instruction
FSR2
PC
=
=
03FFh
0100h
After Instruction
FSR2
PC
=
=
0422h
(TOS)
Note:
All PIC18 instructions may take an optional label argument preceding the instruction mnemonic for use in
symbolic addressing. If a label is used, the instruction format then becomes: {label} instruction argument(s).
DS39778D-page 374
© 2009 Microchip Technology Inc.
PIC18F87J11 FAMILY
CALLW
Subroutine Call using WREG
MOVSF
Move Indexed to f
Syntax:
CALLW
None
Syntax:
MOVSF [z ], f
s
d
Operands:
Operation:
Operands:
0 ≤ z ≤ 127
s
0 ≤ f ≤ 4095
d
(PC + 2) → TOS,
(W) → PCL,
Operation:
((FSR2) + z ) → f
s
d
(PCLATH) → PCH,
(PCLATU) → PCU
Status Affected:
None
Encoding:
1st word (source)
2nd word (destin.)
Status Affected:
Encoding:
None
1110
1111
1011
ffff
0zzz
ffff
zzzz
ffff
s
d
0000
0000
0001
0100
Description
First, the return address (PC + 2) is
pushed onto the return stack. Next, the
contents of W are written to PCL; the
existing value is discarded. Then, the
contents of PCLATH and PCLATU are
latched into PCH and PCU,
respectively. The second cycle is
executed as a NOPinstruction while the
new next instruction is fetched.
Description:
The contents of the source register are
moved to destination register ‘f ’. The
d
actual address of the source register is
determined by adding the 7-bit literal
offset ‘z ’, in the first word, to the value
s
of FSR2. The address of the destination
register is specified by the 12-bit literal
‘f ’ in the second word. Both addresses
d
can be anywhere in the 4096-byte data
space (000h to FFFh).
Unlike CALL, there is no option to
update W, STATUS or BSR.
The MOVSFinstruction cannot use the
PCL, TOSU, TOSH or TOSL as the
destination register.
Words:
Cycles:
1
2
If the resultant source address points to
an Indirect Addressing register, the
value returned will be 00h.
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
WREG
Push PC to
stack
No
operation
Words:
Cycles:
2
2
No
No
No
No
Q Cycle Activity:
Q1
operation
operation
operation
operation
Q2
Q3
Q4
Decode
Determine
source addr source addr source reg
Determine
Read
Example:
HERE
CALLW
Before Instruction
Decode
No
operation
No
operation
Write
register ‘f’
(dest)
PC
=
address (HERE)
PCLATH =
PCLATU =
10h
00h
06h
No dummy
read
W
=
After Instruction
PC
=
001006h
TOS
=
address (HERE + 2)
Example:
MOVSF
[05h], REG2
PCLATH =
PCLATU =
W
10h
00h
06h
Before Instruction
=
FSR2
=
80h
33h
Contents
of 85h
REG2
=
=
11h
After Instruction
FSR2
=
80h
Contents
of 85h
REG2
=
=
33h
33h
© 2009 Microchip Technology Inc.
DS39778D-page 375
PIC18F87J11 FAMILY
MOVSS
Move Indexed to Indexed
PUSHL
Store Literal at FSR2, Decrement FSR2
Syntax:
MOVSS [z ], [z ]
Syntax:
PUSHL k
s
d
Operands:
0 ≤ z ≤ 127
s
Operands:
Operation:
0 ≤ k ≤ 255
0 ≤ z ≤ 127
d
k → (FSR2),
FSR2 – 1→ FSR2
Operation:
((FSR2) + z ) → ((FSR2) + z )
s d
Status Affected:
None
Status Affected:
Encoding:
None
Encoding:
1st word (source)
2nd word (dest.)
1111
1010
kkkk
kkkk
1110
1111
1011
xxxx
1zzz
xzzz
zzzz
zzzz
s
d
Description:
The 8-bit literal ‘k’ is written to the data
memory address specified by FSR2.
FSR2 is decremented by 1 after the
operation.
Description
The contents of the source register are
moved to the destination register. The
addresses of the source and destination
registers are determined by adding the
This instruction allows users to push
values onto a software stack.
7-bit literal offsets ‘z ’ or ‘z ’,
s
d
respectively, to the value of FSR2. Both
registers can be located anywhere in
the 4096-byte data memory space
(000h to FFFh).
Words:
Cycles:
1
1
Q Cycle Activity:
Q1
The MOVSSinstruction cannot use the
PCL, TOSU, TOSH or TOSL as the
destination register.
Q2
Q3
Q4
Decode
Read ‘k’
Process
data
Write to
destination
If the resultant source address points to
an Indirect Addressing register, the
value returned will be 00h. If the
Example:
PUSHL 08h
resultant destination address points to
an Indirect Addressing register, the
instruction will execute as a NOP.
Before Instruction
FSR2H:FSR2L
Memory (01ECh)
=
=
01ECh
00h
Words:
2
2
After Instruction
Cycles:
FSR2H:FSR2L
Memory (01ECh)
=
=
01EBh
08h
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Determine
Determine
Read
source addr source addr source reg
Decode
Determine
dest addr
Determine
dest addr
Write
to dest reg
Example:
MOVSS [05h], [06h]
Before Instruction
FSR2
=
=
=
80h
33h
11h
Contents
of 85h
Contents
of 86h
After Instruction
FSR2
=
=
=
80h
33h
33h
Contents
of 85h
Contents
of 86h
DS39778D-page 376
© 2009 Microchip Technology Inc.
PIC18F87J11 FAMILY
SUBFSR
Subtract Literal from FSR
SUBULNK
Subtract Literal from FSR2 and Return
Syntax:
SUBFSR f, k
0 ≤ k ≤ 63
Syntax:
SUBULNK k
Operands:
Operands:
Operation:
0 ≤ k ≤ 63
f ∈ [ 0, 1, 2 ]
FSRf – k → FSRf
None
FSR2 – k → FSR2,
(TOS) → PC
Operation:
Status Affected:
Encoding:
Status Affected: None
1110
1001
ffkk
kkkk
Encoding:
1110
1001
11kk
kkkk
Description:
The 6-bit literal ‘k’ is subtracted from
the contents of the FSR specified
by ‘f’.
Description:
The 6-bit literal ‘k’ is subtracted from the
contents of the FSR2. A RETURNis then
executed by loading the PC with the
TOS.
Words:
1
1
Cycles:
The instruction takes two cycles to
execute; a NOPis performed during the
second cycle.
Q Cycle Activity:
Q1
Q2
Q3
Q4
This may be thought of as a special case
of the SUBFSRinstruction, where f = 3
(binary ‘11’); it operates only on FSR2.
Decode
Read
register ‘f’
Process
Data
Write to
destination
Words:
1
2
Example:
SUBFSR 2, 23h
03FFh
Cycles:
Before Instruction
FSR2
After Instruction
FSR2
Q Cycle Activity:
Q1
=
Q2
Q3
Q4
Decode
Read
register ‘f’
Process
Data
Write to
destination
=
03DCh
No
No
No
No
Operation
Operation
Operation
Operation
Example:
SUBULNK 23h
Before Instruction
FSR2
PC
=
=
03FFh
0100h
After Instruction
FSR2
PC
=
=
03DCh
(TOS)
© 2009 Microchip Technology Inc.
DS39778D-page 377
PIC18F87J11 FAMILY
25.2.3
BYTE-ORIENTED AND
BIT-ORIENTED INSTRUCTIONS IN
INDEXED LITERAL OFFSET MODE
25.2.3.1
Extended Instruction Syntax with
Standard PIC18 Commands
When the extended instruction set is enabled, the file
register argument ‘f’ in the standard byte-oriented and
bit-oriented commands is replaced with the literal offset
value ‘k’. As already noted, this occurs only when ‘f’ is
less than or equal to 5Fh. When an offset value is used,
it must be indicated by square brackets (“[ ]”). As with
the extended instructions, the use of brackets indicates
to the compiler that the value is to be interpreted as an
index or an offset. Omitting the brackets, or using a
value greater than 5Fh within the brackets, will
generate an error in the MPASM Assembler.
Note: Enabling the PIC18 instruction set exten-
sion may cause legacy applications to
behave erratically or fail entirely.
In addition to eight new commands in the extended set,
enabling the extended instruction set also enables
Indexed Literal Offset Addressing (Section 5.6.1
“Indexed Addressing with Literal Offset”). This has
a significant impact on the way that many commands of
the standard PIC18 instruction set are interpreted.
When the extended set is disabled, addresses embed-
ded in opcodes are treated as literal memory locations:
either as a location in the Access Bank (a = 0) or in a
GPR bank designated by the BSR (a = 1). When the
extended instruction set is enabled and a = 0, however,
a file register argument of 5Fh or less is interpreted as
an offset from the pointer value in FSR2 and not as a
literal address. For practical purposes, this means that
all instructions that use the Access RAM bit as an
argument – that is, all byte-oriented and bit-oriented
instructions, or almost half of the core PIC18 instruc-
tions – may behave differently when the extended
instruction set is enabled.
If the index argument is properly bracketed for Indexed
Literal Offset Addressing, the Access RAM argument is
never specified; it will automatically be assumed to be
‘0’. This is in contrast to standard operation (extended
instruction set disabled), when ‘a’ is set on the basis of
the target address. Declaring the Access RAM bit in
this mode will also generate an error in the MPASM
Assembler.
The destination argument ‘d’ functions as before.
In the latest versions of the MPASM Assembler,
language support for the extended instruction set must
be explicitly invoked. This is done with either the
command line option, /y, or the PE directive in the
source listing.
When the content of FSR2 is 00h, the boundaries of the
Access RAM are essentially remapped to their original
values. This may be useful in creating
backward-compatible code. If this technique is used, it
may be necessary to save the value of FSR2 and
restore it when moving back and forth between C and
assembly routines in order to preserve the Stack
Pointer. Users must also keep in mind the syntax
requirements of the extended instruction set (see
Section 25.2.3.1 “Extended Instruction Syntax with
Standard PIC18 Commands”).
25.2.4
CONSIDERATIONS WHEN
ENABLING THE EXTENDED
INSTRUCTION SET
It is important to note that the extensions to the instruc-
tion set may not be beneficial to all users. In particular,
users who are not writing code that uses a software
stack may not benefit from using the extensions to the
instruction set.
Although the Indexed Literal Offset mode can be very
useful for dynamic stack and pointer manipulation, it
can also be very annoying if a simple arithmetic opera-
tion is carried out on the wrong register. Users who are
accustomed to the PIC18 programming must keep in
mind that, when the extended instruction set is
enabled, register addresses of 5Fh or less are used for
Indexed Literal Offset Addressing.
Additionally, the Indexed Literal Offset Addressing
mode may create issues with legacy applications
written to the PIC18 assembler. This is because
instructions in the legacy code may attempt to address
registers in the Access Bank below 5Fh. Since these
addresses are interpreted as literal offsets to FSR2
when the instruction set extension is enabled, the
application may read or write to the wrong data
addresses.
Representative examples of typical byte-oriented and
bit-oriented instructions in the Indexed Literal Offset
mode are provided on the following page to show how
execution is affected. The operand conditions shown in
the examples are applicable to all instructions of these
types.
When porting an application to the PIC18F87J11 Fam-
ily family, it is very important to consider the type of
code. A large, re-entrant application that is written in C
and would benefit from efficient compilation will do well
when using the instruction set extensions. Legacy
applications that heavily use the Access Bank will most
likely not benefit from using the extended instruction
set.
DS39778D-page 378
© 2009 Microchip Technology Inc.
PIC18F87J11 FAMILY
ADD W to Indexed
(Indexed Literal Offset mode)
Bit Set Indexed
BSF
ADDWF
(Indexed Literal Offset mode)
Syntax:
ADDWF
[k] {,d}
Syntax:
BSF [k], b
Operands:
0 ≤ k ≤ 95
d ∈ [0,1]
Operands:
0 ≤ f ≤ 95
0 ≤ b ≤ 7
Operation:
(W) + ((FSR2) + k) → dest
Operation:
1→ ((FSR2) + k)<b>
Status Affected:
Encoding:
N, OV, C, DC, Z
Status Affected:
Encoding:
None
0010
01d0
kkkk
kkkk
1000
bbb0
kkkk
kkkk
Description:
The contents of W are added to the
contents of the register indicated by
FSR2, offset by the value ‘k’.
Description:
Bit ‘b’ of the register indicated by FSR2,
offset by the value ‘k’, is set.
Words:
Cycles:
1
1
If ‘d’ is ‘0’, the result is stored in W. If ‘d’
is ‘1’, the result is stored back in
register ‘f’ (default).
Q Cycle Activity:
Q1
Q2
Q3
Q4
Words:
Cycles:
1
1
Decode
Read
register ‘f’
Process
Data
Write to
destination
Q Cycle Activity:
Q1
Example:
BSF
[FLAG_OFST], 7
Q2
Q3
Q4
Decode
Read ‘k’
Process
Data
Write to
destination
Before Instruction
FLAG_OFST
FSR2
=
=
0Ah
0A00h
Contents
of 0A0Ah
After Instruction
Example:
ADDWF
[OFST],0
=
55h
D5h
Before Instruction
W
OFST
FSR2
=
=
=
17h
Contents
of 0A0Ah
2Ch
=
0A00h
Contents
of 0A2Ch
=
20h
After Instruction
Set Indexed
(Indexed Literal Offset mode)
SETF
W
=
=
37h
20h
Contents
of 0A2Ch
Syntax:
SETF [k]
Operands:
Operation:
Status Affected:
Encoding:
Description:
0 ≤ k ≤ 95
FFh → ((FSR2) + k)
None
0110
1000
kkkk
kkkk
The contents of the register indicated by
FSR2, offset by ‘k’, are set to FFh.
Words:
Cycles:
1
1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read ‘k’
Process
Data
Write
register
Example:
SETF
[OFST]
2Ch
Before Instruction
OFST
FSR2
=
=
0A00h
Contents
of 0A2Ch
=
00h
After Instruction
Contents
of 0A2Ch
=
FFh
© 2009 Microchip Technology Inc.
DS39778D-page 379
PIC18F87J11 FAMILY
25.2.5
SPECIAL CONSIDERATIONS WITH
MICROCHIP MPLAB® IDE TOOLS
The latest versions of Microchip’s software tools have
been designed to fully support the extended instruction
set for the PIC18F87J11 Family family. This includes
the MPLAB C18 C Compiler, MPASM assembly lan-
guage and MPLAB Integrated Development
Environment (IDE).
When selecting
a
target device for software
development, MPLAB IDE will automatically set default
Configuration bits for that device. The default setting for
the XINST Configuration bit is ‘0’, disabling the
extended instruction set and Indexed Literal Offset
Addressing. For proper execution of applications
developed to take advantage of the extended
instruction set, XINST must be set during
programming.
To develop software for the extended instruction set,
the user must enable support for the instructions and
the Indexed Addressing mode in their language tool(s).
Depending on the environment being used, this may be
done in several ways:
• A menu option or dialog box within the
environment that allows the user to configure the
language tool and its settings for the project
• A command line option
• A directive in the source code
These options vary between different compilers,
assemblers and development environments. Users are
encouraged to review the documentation accompany-
ing their development systems for the appropriate
information.
DS39778D-page 380
© 2009 Microchip Technology Inc.
PIC18F87J11 FAMILY
26.1 MPLAB Integrated Development
Environment Software
26.0 DEVELOPMENT SUPPORT
The PIC® microcontrollers are supported with a full
range of hardware and software development tools:
The MPLAB IDE software brings an ease of software
development previously unseen in the 8/16-bit micro-
controller market. The MPLAB IDE is a Windows®
operating system-based application that contains:
• Integrated Development Environment
- MPLAB® IDE Software
• Assemblers/Compilers/Linkers
- MPASMTM Assembler
• A single graphical interface to all debugging tools
- Simulator
- MPLAB C18 and MPLAB C30 C Compilers
- MPLINKTM Object Linker/
MPLIBTM Object Librarian
- Programmer (sold separately)
- Emulator (sold separately)
- In-Circuit Debugger (sold separately)
• A full-featured editor with color-coded context
• A multiple project manager
- MPLAB ASM30 Assembler/Linker/Library
• Simulators
- MPLAB SIM Software Simulator
• Emulators
• Customizable data windows with direct edit of
contents
- MPLAB ICE 2000 In-Circuit Emulator
- MPLAB REAL ICE™ In-Circuit Emulator
• In-Circuit Debugger
• High-level source code debugging
• Visual device initializer for easy register
initialization
- MPLAB ICD 2
• Mouse over variable inspection
• Device Programmers
• Drag and drop variables from source to watch
windows
- PICSTART® Plus Development Programmer
- MPLAB PM3 Device Programmer
- PICkit™ 2 Development Programmer
• Extensive on-line help
• Integration of select third party tools, such as
HI-TECH Software C Compilers and IAR
C Compilers
• Low-Cost Demonstration and Development
Boards and Evaluation Kits
The MPLAB IDE allows you to:
• Edit your source files (either assembly or C)
• One touch assemble (or compile) and download
to PIC MCU emulator and simulator tools
(automatically updates all project information)
• Debug using:
- Source files (assembly or C)
- Mixed assembly and C
- Machine code
MPLAB IDE supports multiple debugging tools in a
single development paradigm, from the cost-effective
simulators, through low-cost in-circuit debuggers, to
full-featured emulators. This eliminates the learning
curve when upgrading to tools with increased flexibility
and power.
© 2009 Microchip Technology Inc.
DS39778D-page 381
PIC18F87J11 FAMILY
26.2 MPASM Assembler
26.5 MPLAB ASM30 Assembler, Linker
and Librarian
The MPASM Assembler is a full-featured, universal
macro assembler for all PIC MCUs.
MPLAB ASM30 Assembler produces relocatable
machine code from symbolic assembly language for
dsPIC30F devices. MPLAB C30 C Compiler uses the
assembler to produce its object file. The assembler
generates relocatable object files that can then be
archived or linked with other relocatable object files and
archives to create an executable file. Notable features
of the assembler include:
The MPASM Assembler generates relocatable object
files for the MPLINK Object Linker, Intel® standard HEX
files, MAP files to detail memory usage and symbol
reference, absolute LST files that contain source lines
and generated machine code and COFF files for
debugging.
The MPASM Assembler features include:
• Integration into MPLAB IDE projects
• Support for the entire dsPIC30F instruction set
• Support for fixed-point and floating-point data
• Command line interface
• User-defined macros to streamline
assembly code
• Rich directive set
• Conditional assembly for multi-purpose
source files
• Flexible macro language
• MPLAB IDE compatibility
• Directives that allow complete control over the
assembly process
26.6 MPLAB SIM Software Simulator
26.3 MPLAB C18 and MPLAB C30
C Compilers
The MPLAB SIM Software Simulator allows code
development in a PC-hosted environment by simulat-
ing the PIC MCUs and dsPIC® DSCs on an instruction
level. On any given instruction, the data areas can be
examined or modified and stimuli can be applied from
a comprehensive stimulus controller. Registers can be
logged to files for further run-time analysis. The trace
buffer and logic analyzer display extend the power of
the simulator to record and track program execution,
actions on I/O, most peripherals and internal registers.
The MPLAB C18 and MPLAB C30 Code Development
Systems are complete ANSI
C
compilers for
Microchip’s PIC18 and PIC24 families of microcon-
trollers and the dsPIC30 and dsPIC33 family of digital
signal controllers. These compilers provide powerful
integration capabilities, superior code optimization and
ease of use not found with other compilers.
For easy source level debugging, the compilers provide
symbol information that is optimized to the MPLAB IDE
debugger.
The MPLAB SIM Software Simulator fully supports
symbolic debugging using the MPLAB C18 and
MPLAB C30 C Compilers, and the MPASM and
MPLAB ASM30 Assemblers. The software simulator
offers the flexibility to develop and debug code outside
of the hardware laboratory environment, making it an
excellent, economical software development tool.
26.4 MPLINK Object Linker/
MPLIB Object Librarian
The MPLINK Object Linker combines relocatable
objects created by the MPASM Assembler and the
MPLAB C18 C Compiler. It can link relocatable objects
from precompiled libraries, using directives from a
linker script.
The MPLIB Object Librarian manages the creation and
modification of library files of precompiled code. When
a routine from a library is called from a source file, only
the modules that contain that routine will be linked in
with the application. This allows large libraries to be
used efficiently in many different applications.
The object linker/library features include:
• Efficient linking of single libraries instead of many
smaller files
• Enhanced code maintainability by grouping
related modules together
• Flexible creation of libraries with easy module
listing, replacement, deletion and extraction
DS39778D-page 382
© 2009 Microchip Technology Inc.
PIC18F87J11 FAMILY
26.7 MPLAB ICE 2000
High-Performance
26.9 MPLAB ICD 2 In-Circuit Debugger
Microchip’s In-Circuit Debugger, MPLAB ICD 2, is a
powerful, low-cost, run-time development tool,
connecting to the host PC via an RS-232 or high-speed
USB interface. This tool is based on the Flash PIC
MCUs and can be used to develop for these and other
PIC MCUs and dsPIC DSCs. The MPLAB ICD 2 utilizes
the in-circuit debugging capability built into the Flash
devices. This feature, along with Microchip’s In-Circuit
Serial ProgrammingTM (ICSPTM) protocol, offers cost-
effective, in-circuit Flash debugging from the graphical
user interface of the MPLAB Integrated Development
Environment. This enables a designer to develop and
debug source code by setting breakpoints, single step-
ping and watching variables, and CPU status and
peripheral registers. Running at full speed enables
testing hardware and applications in real time. MPLAB
ICD 2 also serves as a development programmer for
selected PIC devices.
In-Circuit Emulator
The MPLAB ICE 2000 In-Circuit Emulator is intended
to provide the product development engineer with a
complete microcontroller design tool set for PIC
microcontrollers. Software control of the MPLAB ICE
2000 In-Circuit Emulator is advanced by the MPLAB
Integrated Development Environment, which allows
editing, building, downloading and source debugging
from a single environment.
The MPLAB ICE 2000 is a full-featured emulator
system with enhanced trace, trigger and data monitor-
ing features. Interchangeable processor modules allow
the system to be easily reconfigured for emulation of
different processors. The architecture of the MPLAB
ICE 2000 In-Circuit Emulator allows expansion to
support new PIC microcontrollers.
The MPLAB ICE 2000 In-Circuit Emulator system has
been designed as a real-time emulation system with
advanced features that are typically found on more
expensive development tools. The PC platform and
Microsoft® Windows® 32-bit operating system were
chosen to best make these features available in a
simple, unified application.
26.10 MPLAB PM3 Device Programmer
The MPLAB PM3 Device Programmer is a universal,
CE compliant device programmer with programmable
voltage verification at VDDMIN and VDDMAX for
maximum reliability. It features a large LCD display
(128 x 64) for menus and error messages and a modu-
lar, detachable socket assembly to support various
package types. The ICSP™ cable assembly is included
as a standard item. In Stand-Alone mode, the MPLAB
PM3 Device Programmer can read, verify and program
PIC devices without a PC connection. It can also set
code protection in this mode. The MPLAB PM3
connects to the host PC via an RS-232 or USB cable.
The MPLAB PM3 has high-speed communications and
optimized algorithms for quick programming of large
memory devices and incorporates an SD/MMC card for
file storage and secure data applications.
26.8 MPLAB REAL ICE In-Circuit
Emulator System
MPLAB REAL ICE In-Circuit Emulator System is
Microchip’s next generation high-speed emulator for
Microchip Flash DSC and MCU devices. It debugs and
programs PIC® Flash MCUs and dsPIC® Flash DSCs
with the easy-to-use, powerful graphical user interface of
the MPLAB Integrated Development Environment (IDE),
included with each kit.
The MPLAB REAL ICE probe is connected to the design
engineer’s PC using a high-speed USB 2.0 interface and
is connected to the target with either a connector
compatible with the popular MPLAB ICD 2 system
(RJ11) or with the new high-speed, noise tolerant, Low-
Voltage Differential Signal (LVDS) interconnection
(CAT5).
MPLAB REAL ICE is field upgradeable through future
firmware downloads in MPLAB IDE. In upcoming
releases of MPLAB IDE, new devices will be supported,
and new features will be added, such as software break-
points and assembly code trace. MPLAB REAL ICE
offers significant advantages over competitive emulators
including low-cost, full-speed emulation, real-time
variable watches, trace analysis, complex breakpoints, a
ruggedized probe interface and long (up to three meters)
interconnection cables.
© 2009 Microchip Technology Inc.
DS39778D-page 383
PIC18F87J11 FAMILY
26.11 PICSTART Plus Development
Programmer
26.13 Demonstration, Development and
Evaluation Boards
The PICSTART Plus Development Programmer is an
easy-to-use, low-cost, prototype programmer. It
connects to the PC via a COM (RS-232) port. MPLAB
Integrated Development Environment software makes
using the programmer simple and efficient. The
PICSTART Plus Development Programmer supports
most PIC devices in DIP packages up to 40 pins.
Larger pin count devices, such as the PIC16C92X and
PIC17C76X, may be supported with an adapter socket.
The PICSTART Plus Development Programmer is CE
compliant.
A wide variety of demonstration, development and
evaluation boards for various PIC MCUs and dsPIC
DSCs allows quick application development on fully func-
tional systems. Most boards include prototyping areas for
adding custom circuitry and provide application firmware
and source code for examination and modification.
The boards support a variety of features, including LEDs,
temperature sensors, switches, speakers, RS-232
interfaces, LCD displays, potentiometers and additional
EEPROM memory.
The demonstration and development boards can be
used in teaching environments, for prototyping custom
circuits and for learning about various microcontroller
applications.
26.12 PICkit 2 Development Programmer
The PICkit™ 2 Development Programmer is a low-cost
programmer and selected Flash device debugger with
an easy-to-use interface for programming many of
Microchip’s baseline, mid-range and PIC18F families of
Flash memory microcontrollers. The PICkit 2 Starter Kit
includes a prototyping development board, twelve
sequential lessons, software and HI-TECH’s PICC™
Lite C compiler, and is designed to help get up to speed
quickly using PIC® microcontrollers. The kit provides
everything needed to program, evaluate and develop
applications using Microchip’s powerful, mid-range
Flash memory family of microcontrollers.
In addition to the PICDEM™ and dsPICDEM™ demon-
stration/development board series of circuits, Microchip
has a line of evaluation kits and demonstration software
®
for analog filter design, KEELOQ security ICs, CAN,
IrDA®, PowerSmart battery management, SEEVAL®
evaluation system, Sigma-Delta ADC, flow rate
sensing, plus many more.
Check the Microchip web page (www.microchip.com)
for the complete list of demonstration, development
and evaluation kits.
DS39778D-page 384
© 2009 Microchip Technology Inc.
PIC18F87J11 FAMILY
27.0 ELECTRICAL CHARACTERISTICS
(†)
Absolute Maximum Ratings
Ambient temperature under bias.............................................................................................................-40°C to +100°C
Storage temperature .............................................................................................................................. -65°C to +150°C
Voltage on any digital only input pin or MCLR with respect to VSS (except VDD) ........................................ -0.3V to 6.0V
Voltage on any combined digital and analog pin with respect to VSS ............................................. -0.3V to (VDD + 0.3V)
Voltage on VDDCORE with respect to VSS................................................................................................... -0.3V to 2.75V
Voltage on VDD with respect to VSS ........................................................................................................... -0.3V to 4.0V
Total power dissipation (Note 1) ...............................................................................................................................1.0W
Maximum current out of VSS pin ...........................................................................................................................300 mA
Maximum current into VDD pin ..............................................................................................................................250 mA
Input clamp current, IIK (VI < 0 or VI > VDD) (Note 2)........................................................................................................ ±0 mA
Output clamp current, IOK (VO < 0 or VO > VDD) (Note 2)................................................................................................ ±0 mA
Maximum output current sunk by any PORTB and PORTC I/O pins......................................................................25 mA
Maximum output current sunk by any PORTD, PORTE and PORTJ I/O pins ..........................................................8 mA
Maximum output current sunk by any PORTA, PORTF, PORTG and PORTH I/O pins............................................2 mA
Maximum output current sourced by any PORTB and PORTC I/O pins.................................................................25 mA
Maximum output current sourced by any PORTD, PORTE and PORTJ I/O pins.....................................................8 mA
Maximum output current sourced by any PORTA, PORTF, PORTG and PORTH I/O pins ......................................2 mA
Maximum current sunk by all ports combined.......................................................................................................200 mA
Maximum current sourced by all ports combined..................................................................................................200 mA
Note 1: Power dissipation is calculated as follows:
Pdis = VDD x {IDD – ∑ IOH} + ∑ {(VDD – VOH) x IOH} + ∑ (VOL x IOL) + ∑ (VTPOUT x ITPOUT)
2: No clamping diodes are present.
† NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at those or any other conditions above those
indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for
extended periods may affect device reliability.
© 2009 Microchip Technology Inc.
DS39778D-page 385
PIC18F87J11 FAMILY
FIGURE 27-1:
PIC18F87J11 FAMILY VOLTAGE-FREQUENCY GRAPH, REGULATOR ENABLED
(INDUSTRIAL)
4.0V
3.5V
3.0V
2.5V
2.0V
3.6V
PIC18F87J11 Family
2.35V
8 MHz
0
48 MHZ
Frequency
FIGURE 27-2:
PIC18F87J11 FAMILY VOLTAGE-FREQUENCY GRAPH, REGULATOR DISABLED
(INDUSTRIAL)(1)
3.00V
2.75V
2.7V
2.50V
PIC18F87J11 Family
2.35V
2.25V
2.00V
8 MHz
48 MHz
0
Frequency
Note 1: When the on-chip voltage regulator is disabled, VDD and VDDCORE must be maintained so that
VDDCORE ≤ VDD ≤ 3.6V.
DS39778D-page 386
© 2009 Microchip Technology Inc.
PIC18F87J11 FAMILY
27.1 DC Characteristics: Supply Voltage
PIC18F87J11 Family (Industrial)
PIC18F87J11 Family Family
Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C ≤ TA ≤ +85°C for industrial
(Industrial)
Param
No.
Symbol
Characteristic
Supply Voltage
Min
Typ
Max
Units
Conditions
D001
VDD
VDDCORE
—
—
3.6
3.6
V
V
ENVREG tied to VSS
ENVREG tied to VDD
2.0
D001B
VDDCORE External Supply for
2.0
—
2.7
V
ENVREG tied to VSS
Microcontroller Core
D001C AVDD
D001D AVSS
Analog Supply Voltage
VDD – 0.3
—
—
—
VDD + 0.3
VSS + 0.3
—
V
V
V
Analog Ground Potential VSS – 0.3
D002
D003
D004
VDR
RAM Data Retention
Voltage(1)
1.5
VPOR
SVDD
VDD Power-on Reset
Voltage
—
—
—
0.7
—
V
See Section 4.3 “Power-on
Reset (POR)” for details
VDD Rise Rate
0.05
V/ms See Section 4.3 “Power-on
Reset (POR)” for details
to Ensure Internal
Power-on Reset Signal
D005
VBOR
Brown-out Reset Voltage
—
1.8
—
V
Note 1: This is the limit to which VDD can be lowered in Sleep mode, or during a device Reset, without losing RAM
data.
© 2009 Microchip Technology Inc.
DS39778D-page 387
PIC18F87J11 FAMILY
27.2 DC Characteristics: Power-Down and Supply Current
PIC18F87J11 Family (Industrial)
PIC18F87J11 Family
Standard Operating Conditions (unless otherwise stated)
(Industrial)
Operating temperature
-40°C ≤ TA ≤ +85°C for industrial
Param
No.
Device
Power-Down Current (IPD)
Typ Max Units
Conditions
(1)
All devices 0.5
1.4
1.4
10.2
1.5
1.5
12.6
7
μA
μA
μA
μA
μA
μA
μA
μA
μA
-40°C
+25°C
+85°C
-40°C
+25°C
+85°C
-40°C
+25°C
+85°C
(4)
VDD = 2.0V
0.5
(Sleep mode)
5.5
All devices 0.6
(4)
VDD = 2.5V
0.6
(Sleep mode)
6.8
All devices 2.9
(5)
VDD = 3.3V
3.6
9.6
7
(Sleep mode)
19
Note 1: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with
the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS and all features that add delta
current disabled (such as WDT, Timer1 oscillator, BOR, etc.).
2: The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading
and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on
the current consumption.
The test conditions for all IDD measurements in active operation mode are:
OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD;
MCLR = VDD; WDT enabled/disabled as specified.
3: Standard, low-cost 32 kHz crystals have an operating temperature range of -10°C to +70°C. Extended temperature
crystals are available at a much higher cost.
4: Voltage regulator disabled (ENVREG = 0, tied to VSS).
5: Voltage regulator enabled (ENVREG = 1, tied to VDD, REGSLP = 1).
DS39778D-page 388
© 2009 Microchip Technology Inc.
PIC18F87J11 FAMILY
27.2 DC Characteristics: Power-Down and Supply Current
PIC18F87J11 Family (Industrial) (Continued)
PIC18F87J11 Family
Standard Operating Conditions (unless otherwise stated)
(Industrial)
Operating temperature
-40°C ≤ TA ≤ +85°C for industrial
Param
No.
Device
Typ
Max Units
Conditions
(2,3)
Supply Current (IDD)
All devices
5
14.2
14.2
19.0
16.5
16.5
22.4
84
μA
μA
-40°C
VDD = 2.0V,
5.5
10
+25°C
(4)
VDDCORE = 2.0V
+85°C
μA
All devices 6.8
μA
-40°C
FOSC = 31 kHz
(RC_RUN mode,
VDD = 2.5V,
7.6
14
μA
+25°C
(4)
VDDCORE = 2.5V
+85°C
internal oscillator source)
μA
All devices
37
51
72
μA
-40°C
(5)
84
μA
+25°C
+85°C
-40°C
+25°C
+85°C
-40°C
+25°C
+85°C
-40°C
+25°C
+85°C
-40°C
+25°C
+85°C
-40°C
+25°C
+85°C
-40°C
+25°C
+85°C
VDD = 3.3V
108
μA
All devices 0.43
0.82
0.82
0.95
0.98
0.98
1.10
0.96
0.96
1.18
1.45
1.45
1.58
1.72
1.72
1.85
2.87
2.87
2.96
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
VDD = 2.0V,
VDDCORE = 2.0V
0.47
(4)
(4)
0.52
All devices 0.52
FOSC = 1 MHz
(RC_RUN mode,
VDD = 2.5V,
VDDCORE = 2.5V
0.57
internal oscillator source)
0.63
All devices 0.59
(5)
0.65
VDD = 3.3V
0.72
All devices 0.88
VDD = 2.0V,
VDDCORE = 2.0V
1
(4)
(4)
1.1
All devices 1.2
FOSC = 4 MHz
(RC_RUN mode,
VDD = 2.5V,
VDDCORE = 2.5V
1.3
internal oscillator source)
1.4
All devices 1.3
(5)
1.4
1.5
VDD = 3.3V
Note 1: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with
the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS and all features that add delta
current disabled (such as WDT, Timer1 oscillator, BOR, etc.).
2: The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading
and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on
the current consumption.
The test conditions for all IDD measurements in active operation mode are:
OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD;
MCLR = VDD; WDT enabled/disabled as specified.
3: Standard, low-cost 32 kHz crystals have an operating temperature range of -10°C to +70°C. Extended temperature
crystals are available at a much higher cost.
4: Voltage regulator disabled (ENVREG = 0, tied to VSS).
5: Voltage regulator enabled (ENVREG = 1, tied to VDD, REGSLP = 1).
© 2009 Microchip Technology Inc.
DS39778D-page 389
PIC18F87J11 FAMILY
27.2 DC Characteristics: Power-Down and Supply Current
PIC18F87J11 Family (Industrial) (Continued)
PIC18F87J11 Family
Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C ≤ TA ≤ +85°C for industrial
(Industrial)
Param
No.
Device
Supply Current (IDD) Cont.
Typ
Max Units
Conditions
(2,3)
All devices
All devices
All devices
3
9.4
9.4
μA
μA
-40°C
+25°C
+85°C
-40°C
+25°C
+85°C
-40°C
+25°C
+85°C
-40°C
+25°C
+85°C
-40°C
+25°C
+85°C
-40°C
+25°C
+85°C
-40°C
+25°C
+85°C
-40°C
+25°C
+85°C
-40°C
+25°C
+85°C
VDD = 2.0V,
VDDCORE = 2.0V
3.3
8.5
4
(4)
(4)
17.2
10.5
10.5
19.5
82
μA
μA
FOSC = 31 kHz
(RC_IDLE mode,
internal oscillator source)
VDD = 2.5V,
VDDCORE = 2.5V
4.3
10.3
34
μA
μA
μA
(5)
48
82
μA
VDD = 3.3V
69
105
μA
All devices 0.33
0.75
0.75
0.84
0.78
0.78
0.91
0.82
0.82
0.95
0.98
0.98
1.12
1.14
1.14
1.25
1.27
1.27
1.45
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
VDD = 2.0V,
VDDCORE = 2.0V
0.37
(4)
(4)
0.41
All devices 0.39
FOSC = 1 MHz
(RC_IDLE mode,
internal oscillator source)
VDD = 2.5V,
VDDCORE = 2.5V
0.42
0.47
All devices 0.43
(5)
0.48
VDD = 3.3V
0.54
All devices 0.53
VDD = 2.0V,
VDDCORE = 2.0V
0.57
(4)
(4)
0.61
All devices 0.63
0.67
FOSC = 4 MHz
(RC_IDLE mode,
internal oscillator source)
VDD = 2.5V,
VDDCORE = 2.5V
0.72
All devices 0.7
0.76
(5)
VDD = 3.3V
0.82
Note 1: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with
the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS and all features that add delta
current disabled (such as WDT, Timer1 oscillator, BOR, etc.).
2: The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading
and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on
the current consumption.
The test conditions for all IDD measurements in active operation mode are:
OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD;
MCLR = VDD; WDT enabled/disabled as specified.
3: Standard, low-cost 32 kHz crystals have an operating temperature range of -10°C to +70°C. Extended temperature
crystals are available at a much higher cost.
4: Voltage regulator disabled (ENVREG = 0, tied to VSS).
5: Voltage regulator enabled (ENVREG = 1, tied to VDD, REGSLP = 1).
DS39778D-page 390
© 2009 Microchip Technology Inc.
PIC18F87J11 FAMILY
27.2 DC Characteristics: Power-Down and Supply Current
PIC18F87J11 Family (Industrial) (Continued)
PIC18F87J11 Family
Standard Operating Conditions (unless otherwise stated)
(Industrial)
Operating temperature
-40°C ≤ TA ≤ +85°C for industrial
Param
No.
Device
Supply Current (IDD) Cont.
Typ Max Units
Conditions
(2,3)
All devices 0.17
0.35
0.35
0.42
0.52
0.52
0.61
1.1
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
-40°C
VDD = 2.0V,
VDDCORE = 2.0V
0.18
+25°C
+85°C
-40°C
+25°C
+85°C
-40°C
+25°C
+85°C
-40°C
+25°C
+85°C
-40°C
+25°C
+85°C
-40°C
+25°C
+85°C
-40°C
+25°C
+85°C
-40°C
+25°C
+85°C
(4)
(4)
0.20
All devices 0.29
FOSC = 1 MHZ
(PRI_RUN mode,
EC oscillator)
VDD = 2.5V,
VDDCORE = 2.5V
0.31
0.34
All devices 0.59
(5)
0.44
0.85
0.85
1.25
1.25
1.36
1.7
VDD = 3.3V
0.42
All devices 0.70
VDD = 2.0V,
VDDCORE = 2.0V
0.75
(4)
(4)
0.79
All devices 1.10
FOSC = 4 MHz
(PRI_RUN mode,
EC oscillator)
VDD = 2.5V,
VDDCORE = 2.5V
1.10
1.7
1.12
1.82
1.95
1.89
1.92
14.8
14.8
15.2
23.2
22.7
22.7
All devices 1.55
(5)
1.47
VDD = 3.3V
1.54
All devices 9.9
VDD = 2.5V,
VDDCORE = 2.5V
9.5
(4)
FOSC = 48 MHZ
(PRI_RUN mode,
EC oscillator)
10.1
All devices 13.3
12.2
(5)
VDD = 3.3V
12.1
Note 1: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with
the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS and all features that add delta
current disabled (such as WDT, Timer1 oscillator, BOR, etc.).
2: The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading
and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on
the current consumption.
The test conditions for all IDD measurements in active operation mode are:
OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD;
MCLR = VDD; WDT enabled/disabled as specified.
3: Standard, low-cost 32 kHz crystals have an operating temperature range of -10°C to +70°C. Extended temperature
crystals are available at a much higher cost.
4: Voltage regulator disabled (ENVREG = 0, tied to VSS).
5: Voltage regulator enabled (ENVREG = 1, tied to VDD, REGSLP = 1).
© 2009 Microchip Technology Inc.
DS39778D-page 391
PIC18F87J11 FAMILY
27.2 DC Characteristics: Power-Down and Supply Current
PIC18F87J11 Family (Industrial) (Continued)
PIC18F87J11 Family
Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C ≤ TA ≤ +85°C for industrial
(Industrial)
Param
No.
Device
Supply Current (IDD) Cont.
Typ
Max Units
Conditions
(2,3)
All devices 4.5
5.2
5.2
mA
mA
-40°C
+25°C
+85°C
-40°C
+25°C
+85°C
-40°C
+25°C
+85°C
-40°C
+25°C
+85°C
VDD = 2.5V,
VDDCORE = 2.5V
4.4
(4)
FOSC = 4 MHZ,
16 MHz internal
(PRI_RUN HSPLL mode)
4.5
5.2
6.7
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
All devices 5.7
(5)
5.5
6.3
VDD = 3.3V
5.3
6.3
All devices 10.8
13.5
13.5
13.0
24.1
20.2
19.5
VDD = 2.5V,
VDDCORE = 2.5V
10.8
(4)
FOSC = 10 MHZ,
40 MHz internal
(PRI_RUN HSPLL mode)
9.9
All devices 13.4
12.3
(5)
VDD = 3.3V
11.2
Note 1: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with
the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS and all features that add delta
current disabled (such as WDT, Timer1 oscillator, BOR, etc.).
2: The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading
and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on
the current consumption.
The test conditions for all IDD measurements in active operation mode are:
OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD;
MCLR = VDD; WDT enabled/disabled as specified.
3: Standard, low-cost 32 kHz crystals have an operating temperature range of -10°C to +70°C. Extended temperature
crystals are available at a much higher cost.
4: Voltage regulator disabled (ENVREG = 0, tied to VSS).
5: Voltage regulator enabled (ENVREG = 1, tied to VDD, REGSLP = 1).
DS39778D-page 392
© 2009 Microchip Technology Inc.
PIC18F87J11 FAMILY
27.2 DC Characteristics: Power-Down and Supply Current
PIC18F87J11 Family (Industrial) (Continued)
PIC18F87J11 Family
Standard Operating Conditions (unless otherwise stated)
(Industrial)
Operating temperature
-40°C ≤ TA ≤ +85°C for industrial
Param
No.
Device
Supply Current (IDD) Cont.
Typ Max Units
Conditions
(2,3)
All devices 0.10
0.26
0.18
0.22
0.48
0.30
0.26
0.68
0.45
0.54
0.60
0.56
0.56
0.81
0.70
0.70
1.15
0.98
0.98
6.5
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
-40°C
VDD = 2.0V,
VDDCORE = 2.0V
0.07
+25°C
+85°C
-40°C
+25°C
+85°C
-40°C
+25°C
+85°C
-40°C
+25°C
+85°C
-40°C
+25°C
+85°C
-40°C
+25°C
+85°C
-40°C
+25°C
+85°C
-40°C
+25°C
+85°C
(4)
(4)
0.09
All devices 0.25
FOSC = 1 MHz
(PRI_IDLE mode,
EC oscillator)
VDD = 2.5V,
VDDCORE = 2.5V
0.13
0.10
All devices 0.45
(5)
0.26
VDD = 3.3V
0.30
All devices 0.36
VDD = 2.0V,
VDDCORE = 2.0V
0.33
(4)
(4)
0.35
All devices 0.52
FOSC = 4 MHz
(PRI_IDLE mode,
EC oscillator)
VDD = 2.5V,
VDDCORE = 2.5V
0.45
0.46
All devices 0.80
(5)
0.66
VDD = 3.3V
0.65
All devices 5.2
VDD = 2.5V,
VDDCORE = 2.5V
4.9
5.9
(4)
FOSC = 48 MHz
(PRI_IDLE mode,
EC oscillator)
3.4
4.5
All devices 6.2
12.4
11.5
11.5
(5)
5.9
5.8
VDD = 3.3V
Note 1: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with
the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS and all features that add delta
current disabled (such as WDT, Timer1 oscillator, BOR, etc.).
2: The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading
and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on
the current consumption.
The test conditions for all IDD measurements in active operation mode are:
OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD;
MCLR = VDD; WDT enabled/disabled as specified.
3: Standard, low-cost 32 kHz crystals have an operating temperature range of -10°C to +70°C. Extended temperature
crystals are available at a much higher cost.
4: Voltage regulator disabled (ENVREG = 0, tied to VSS).
5: Voltage regulator enabled (ENVREG = 1, tied to VDD, REGSLP = 1).
© 2009 Microchip Technology Inc.
DS39778D-page 393
PIC18F87J11 FAMILY
27.2 DC Characteristics: Power-Down and Supply Current
PIC18F87J11 Family (Industrial) (Continued)
PIC18F87J11 Family
Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C ≤ TA ≤ +85°C for industrial
(Industrial)
Param
No.
Device
Supply Current (IDD) Cont.
Typ
Max Units
Conditions
(2,3)
All devices
18
35
35
µA
µA
-40°C
+25°C
+85°C
-40°C
+25°C
+85°C
-40°C
+25°C
+85°C
-40°C
+25°C
+85°C
-40°C
+25°C
+85°C
-40°C
+25°C
+85°C
VDD = 2.0V,
VDDCORE = 2.0V
19
28
20
21
32
(4)
(4)
49
45
µA
µA
µA
µA
mA
mA
mA
µA
µA
µA
µA
µA
µA
mA
mA
mA
All devices
(3)
FOSC = 32 kHz
VDD = 2.5V,
VDDCORE = 2.5V
45
(SEC_RUN mode,
Timer1 as clock)
61
All devices 0.06
0.11
0.11
0.15
28
(5)
0.07
0.09
VDD = 3.3V
All devices
All devices
14
15
24
15
16
27
VDD = 2.0V,
VDDCORE = 2.0V
28
(4)
(4)
43
31
(3)
FOSC = 32 kHz
VDD = 2.5V,
VDDCORE = 2.5V
31
(SEC_IDLE mode,
Timer1 as clock)
50
All devices 0.05
0.10
0.10
0.14
(5)
0.06
0.08
VDD = 3.3V
Note 1: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with
the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS and all features that add delta
current disabled (such as WDT, Timer1 oscillator, BOR, etc.).
2: The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading
and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on
the current consumption.
The test conditions for all IDD measurements in active operation mode are:
OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD;
MCLR = VDD; WDT enabled/disabled as specified.
3: Standard, low-cost 32 kHz crystals have an operating temperature range of -10°C to +70°C. Extended temperature
crystals are available at a much higher cost.
4: Voltage regulator disabled (ENVREG = 0, tied to VSS).
5: Voltage regulator enabled (ENVREG = 1, tied to VDD, REGSLP = 1).
DS39778D-page 394
© 2009 Microchip Technology Inc.
PIC18F87J11 FAMILY
27.2 DC Characteristics: Power-Down and Supply Current
PIC18F87J11 Family (Industrial) (Continued)
PIC18F87J11 Family
Standard Operating Conditions (unless otherwise stated)
(Industrial)
Operating temperature
Typ Max Units
Module Differential Currents (ΔIWDT, ΔIOSCB, ΔIAD)
-40°C ≤ TA ≤ +85°C for industrial
Param
No.
Device
Conditions
D022
Watchdog Timer 2.1
7.0
7.0
9.5
8.0
8.0
10.4
12.1
12.1
13.6
24
μA
μA
μA
μA
μA
μA
μA
μA
μA
μA
μA
μA
μA
μA
μA
μA
μA
μA
μA
-40°C
VDD = 2.0V,
2.2
4.3
3.0
3.1
5.5
5.9
6.2
6.9
+25°C
(4)
VDDCORE = 2.0V
+85°C
-40°C
VDD = 2.5V,
+25°C
(4)
VDDCORE = 2.5V
+85°C
-40°C
VDD = 3.3V
+25°C
+85°C
D025
(ΔIOSCB)
Timer1 Oscillator
14
15
23
17
18
25
19
21
28
-40°C
VDD = 2.0V,
VDDCORE = 2.0V
(3)
(3)
(3)
32 kHz on Timer1
32 kHz on Timer1
32 kHz on Timer1
24
+25°C
(4)
(4)
36
+85°C
26
-40°C
VDD = 2.5V,
VDDCORE = 2.5V
26
+25°C
38
+85°C
35
-40°C
VDD = 3.3V
35
+25°C
44
+85°C
D026
(ΔIAD)
A/D Converter 3.0
10.0
-40°C to +85°C
VDD = 2.0V,
(4)
(4)
VDDCORE = 2.0V
A/D on, not converting
3.0
3.2
10.0
11.0
μA
μA
-40°C to +85°C
-40°C to +85°C
VDD = 2.5V,
VDDCORE = 2.5V
VDD = 3.3V
Note 1: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with
the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS and all features that add delta
current disabled (such as WDT, Timer1 oscillator, BOR, etc.).
2: The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading
and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on
the current consumption.
The test conditions for all IDD measurements in active operation mode are:
OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD;
MCLR = VDD; WDT enabled/disabled as specified.
3: Standard, low-cost 32 kHz crystals have an operating temperature range of -10°C to +70°C. Extended temperature
crystals are available at a much higher cost.
4: Voltage regulator disabled (ENVREG = 0, tied to VSS).
5: Voltage regulator enabled (ENVREG = 1, tied to VDD, REGSLP = 1).
© 2009 Microchip Technology Inc.
DS39778D-page 395
PIC18F87J11 FAMILY
27.3 DC Characteristics:PIC18F87J11 Family (Industrial)
Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C ≤ TA ≤ +85°C for industrial
DC CHARACTERISTICS
Param
Symbol
No.
Characteristic
Min
Max
Units
Conditions
VIL
Input Low Voltage
All I/O Ports:
with TTL Buffer
with Schmitt Trigger Buffer
MCLR
D030
D031
D032
D033
D033A
VSS
VSS
VSS
VSS
VSS
0.15 VDD
0.2 VDD
0.2 VDD
0.3 VDD
0.2 VDD
V
V
V
V
V
OSC1
OSC1
HS, HSPLL modes
EC, ECPLL modes
D034
T13CKI
VSS
0.3
V
VIH
Input High Voltage
I/O Ports with Analog Functions:
with TTL Buffer
D040
D041
0.25 VDD + 0.8V
0.8 VDD
VDD
VDD
V
V
VDD < 3.3V
with Schmitt Trigger Buffer
Digital-only I/O Ports:
with TTL Buffer
0.25 VDD + 0.8V
2.0
5.5
5.5
V
V
V
V
V
V
VDD < 3.3V
3.3V ≤ VDD ≤ 3.6V
with Schmitt Trigger Buffer
0.8 VDD
0.8 VDD
0.7 VDD
0.8 VDD
5.5
D042
D043
D043A
MCLR
OSC1
OSC1
VDD
VDD
VDD
HS, HSPLL modes
EC, ECPLL modes
D044
T13CKI
1.6
VDD
V
IIL
Input Leakage Current(1,2)
D060
I/O Ports
—
±1
μA VSS ≤ VPIN ≤ VDD,
Pin at high-impedance
D061
D063
MCLR
—
—
±1
±5
μA Vss ≤ VPIN ≤ VDD
μA Vss ≤ VPIN ≤ VDD
OSC1
IPU
Weak Pull-up Current
PORTB Weak Pull-up Current
D070
IPURB
80
400
μA VDD = 3.3V, VPIN = VSS
Note 1: Negative current is defined as current sourced by the pin.
DS39778D-page 396
© 2009 Microchip Technology Inc.
PIC18F87J11 FAMILY
27.3 DC Characteristics:PIC18F87J11 Family (Industrial) (Continued)
Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C ≤ TA ≤ +85°C for industrial
DC CHARACTERISTICS
Param
Symbol
No.
Characteristic
Min
Max
Units
Conditions
VOL
Output Low Voltage
D080
I/O Ports:
PORTA, PORTF, PORTG,
PORTH
—
—
—
—
0.4
0.4
0.4
0.4
V
V
V
V
IOL = 2 mA, VDD = 3.3V,
-40°C to +85°C
PORTD, PORTE, PORTJ
IOL = 3.4 mA, VDD = 3.3V,
-40°C to +85°C
PORTB, PORTC
IOL = 3.4 mA, VDD = 3.3V,
-40°C to +85°C
D083
D090
OSC2/CLKO
IOL = 1.6 mA, VDD = 3.3V,
(EC, ECPLL modes)
Output High Voltage(1)
-40°C to +85°C
VOH
I/O Ports:
V
V
PORTA, PORTF, PORTG,
PORTH
2.4
2.4
2.4
2.4
—
—
—
—
IOH = -2 mA, VDD = 3.3V,
-40°C to +85°C
PORTD, PORTE, PORTJ
V
V
V
IOH = -2 mA, VDD = 3.3V,
-40°C to +85°C
PORTB, PORTC
IOH = -2 mA, VDD = 3.3V,
-40°C to +85°C
D092
OSC2/CLKO
IOH = -1 mA, VDD = 3.3V,
(INTOSC, EC, ECPLL modes)
-40°C to +85°C
Capacitive Loading Specs
on Output Pins
D100(4) COSC2 OSC2 pin
—
15
pF In HS mode when
external clock is used to drive
OSC1
D101
D102
CIO
CB
All I/O pins and OSC2
SCLx, SDAx
—
—
50
pF To meet the AC Timing
Specifications
pF I2C™ Specification
400
Note 1: Negative current is defined as current sourced by the pin.
© 2009 Microchip Technology Inc.
DS39778D-page 397
PIC18F87J11 FAMILY
TABLE 27-1: MEMORY PROGRAMMING REQUIREMENTS
Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C ≤ TA ≤ +85°C for industrial
DC CHARACTERISTICS
Param
Sym
No.
Characteristic
Min
Typ†
Max
Units
Conditions
Program Flash Memory
Cell Endurance
D130
D131
EP
10K
—
—
—
E/W -40°C to +85°C
VPR
VDD for Read
VMIN
3.6
V
VMIN = Minimum operating
voltage
D132B VPEW VDD for Self-Timed Write
VMIN
—
3.6
V
VMIN = Minimum operating
voltage
D133A TIW
Self-Timed Write Cycle Time
—
2.8
—
—
—
ms
D134 TRETD Characteristic Retention
20
Year Provided no other
specifications are violated
D135
IDDP
Supply Current during
Programming
—
3
14
1
mA
D1xxx TWE
Writes per Erase Cycle
—
—
†
Data in “Typ” column is at 3.3V, 25°C unless otherwise stated. These parameters are for design guidance
only and are not tested.
DS39778D-page 398
© 2009 Microchip Technology Inc.
PIC18F87J11 FAMILY
TABLE 27-2: COMPARATOR SPECIFICATIONS
Operating Conditions: 3.0V < VDD < 3.6V, -40°C < TA < +85°C (unless otherwise stated)
Param
No.
Sym
Characteristics
Input Offset Voltage
Min
Typ
Max
Units
Comments
D300
VIOFF
—
0
±5.0
—
±1.2(2)
±10
mV
V
D301
VICM
Input Common Mode Voltage*
Internal Reference Voltage
Common Mode Rejection Ratio*
Response Time(1)*
AVDD – 1.5
VIRV
—
55
—
—
—
—
V
±1.2%
D302
300
CMRR
TRESP
—
dB
ns
μs
150
—
400
10
301
TMC2OV Comparator Mode Change to
Output Valid*
*
These parameters are characterized but not tested.
Note 1: Response time measured with one comparator input at (VDD – 1.5)/2, while the other input transitions
from VSS to VDD.
2: Tolerance is ±1.2%.
TABLE 27-3: VOLTAGE REFERENCE SPECIFICATIONS
Operating Conditions: 3.0V < VDD < 3.6V, -40°C < TA < +85°C (unless otherwise stated)
Param
No.
Sym
Characteristics
Resolution
Min
Typ
Max
Units
Comments
D310
VRES
VDD/24
—
—
—
2k
—
VDD/32
1/2
LSb
LSb
Ω
D311
D312
310
VRAA
VRUR
TSET
Absolute Accuracy
Unit Resistor Value (R)
Settling Time(1)
—
—
—
10
μs
Note 1: Settling time measured while CVRR = 1and the CVR3:CVR0 bits transition from ‘0000’ to ‘1111’.
TABLE 27-4: INTERNAL VOLTAGE REGULATOR SPECIFICATIONS
Operating Conditions: -40°C < TA < +85°C (unless otherwise stated)
Param
No.
Sym
Characteristics
Min
Typ
Max
Units
Comments
VRGOUT Regulator Output Voltage*
CF External Filter Capacitor Value*
—
2.5
10
—
—
V
4.7
μF
Capacitor must be low-ESR
*
These parameters are characterized but not tested. Parameter numbers not yet assigned for these
specifications.
© 2009 Microchip Technology Inc.
DS39778D-page 399
PIC18F87J11 FAMILY
27.4 AC (Timing) Characteristics
27.4.1
TIMING PARAMETER SYMBOLOGY
The timing parameter symbols have been created
following one of the following formats:
1. TppS2ppS
2. TppS
T
3. TCC:ST
4. Ts
(I2C specifications only)
(I2C specifications only)
F
Frequency
T
Time
Lowercase letters (pp) and their meanings:
pp
cc
ck
cs
di
CCP1
CLKO
CS
osc
rd
OSC1
RD
rw
sc
ss
t0
RD or WR
SCK
SDI
do
dt
SDO
SS
Data in
I/O port
MCLR
T0CKI
T13CKI
WR
io
t1
mc
wr
Uppercase letters and their meanings:
S
F
Fall
P
R
V
Z
Period
H
High
Rise
I
L
Invalid (High-impedance)
Low
Valid
High-impedance
I2C only
AA
output access
Bus free
High
Low
High
Low
BUF
TCC:ST (I2C specifications only)
CC
HD
Hold
SU
Setup
ST
DAT
STA
DATA input hold
Start condition
STO
Stop condition
DS39778D-page 400
© 2009 Microchip Technology Inc.
PIC18F87J11 FAMILY
27.4.2
TIMING CONDITIONS
The temperature and voltages specified in Table 27-5
apply to all timing specifications unless otherwise
noted. Figure 27-3 specifies the load conditions for the
timing specifications.
TABLE 27-5: TEMPERATURE AND VOLTAGE SPECIFICATIONS – AC
Standard Operating Conditions (unless otherwise stated)
AC CHARACTERISTICS
Operating temperature
-40°C ≤ TA ≤ +85°C for industrial
Operating voltage VDD range as described in Section 27.1 and Section 27.3.
FIGURE 27-3:
LOAD CONDITIONS FOR DEVICE TIMING SPECIFICATIONS
Load Condition 1
VDD/2
Load Condition 2
RL
CL
CL
Pin
Pin
VSS
VSS
RL = 464Ω
CL = 50 pF for all pins except OSC2/CLKO/RA6
and including D and E outputs as ports
CL = 15 pF for OSC2/CLKO/RA6
© 2009 Microchip Technology Inc.
DS39778D-page 401
PIC18F87J11 FAMILY
27.4.3
TIMING DIAGRAMS AND SPECIFICATIONS
FIGURE 27-4:
EXTERNAL CLOCK TIMING
Q4
Q1
1
Q2
Q3
Q4
4
Q1
OSC1
CLKO
3
3
4
2
TABLE 27-6: EXTERNAL CLOCK TIMING REQUIREMENTS
Param.
Symbol
Characteristic
Min
Max
Units
Conditions
No.
1A
FOSC
External CLKI Frequency(1)
DC
DC
4
48
10
25
10
—
MHz EC Oscillator mode
ECPLL Oscillator mode
MHz HS Oscillator mode
HSPLL Oscillator mode
Oscillator Frequency(1)
External CLKI Period(1)
Oscillator Period(1)
4
1
TOSC
20.8
100
40.0
100
83.3
10
ns
EC Oscillator mode
—
ECPLL Oscillator mode
250
250
—
ns
HS Oscillator mode
HSPLL Oscillator mode
TCY = 4/FOSC, Industrial
HS Oscillator mode
2
3
TCY
Instruction Cycle Time(1)
ns
ns
TOSL,
TOSH
External Clock in (OSC1)
High or Low Time
—
4
TOSR,
TOSF
External Clock in (OSC1)
Rise or Fall Time
—
7.5
ns
HS Oscillator mode
Note 1: Instruction cycle period (TCY) equals four times the input oscillator time base period for all configurations
except PLL. All specified values are based on characterization data for that particular oscillator type under
standard operating conditions with the device executing code. Exceeding these specified limits may result
in an unstable oscillator operation and/or higher than expected current consumption. All devices are tested
to operate at “min.” values with an external clock applied to the OSC1/CLKI pin. When an external clock
input is used, the “max.” cycle time limit is “DC” (no clock) for all devices.
DS39778D-page 402
© 2009 Microchip Technology Inc.
PIC18F87J11 FAMILY
TABLE 27-7: PLL CLOCK TIMING SPECIFICATIONS (VDD = 2.15V TO 3.6V)
Param
No.
Sym
Characteristic
Min
Typ†
Max
Units Conditions
F10
F11
F12
F13
FOSC Oscillator Frequency Range
4
—
—
—
—
10
40
2
MHz
MHz
ms
FSYS On-Chip VCO System Frequency
16
—
-2
trc
PLL Start-up Time (lock time)
ΔCLK CLKO Stability (jitter)
+2
%
†
Data in “Typ” column is at 3.3V, 25°C, unless otherwise stated. These parameters are for design guidance
only and are not tested.
TABLE 27-8: INTERNAL RC ACCURACY (INTOSC AND INTRC SOURCES)
Param
Device
Min
Typ
Max
Units
Conditions
No.
INTOSC Accuracy @ Freq = 8 MHz, 4 MHz, 2 MHz, 1 MHz, 500 kHz, 250 kHz, 125 kHz, 31 kHz(1)
All Devices
-2
-5
+/-1
—
2
5
%
%
%
+25°C
VDD = 2.7-3.3V
VDD = 2.0-3.3V
VDD = 2.0-3.3V
-10°C to +85°C
-40°C to +85°C
-10
+/-1
10
INTRC Accuracy @ Freq = 31 kHz(1)
All Devices 21.7
—
40.3
kHz
Note 1: The accuracy specification of the 31 kHz clock is determined by which source is providing it at a given time.
When INTSRC (OSCTUNE<7>) is ‘1’, use the INTOSC accuracy specification. When INTSRC is ‘0’, use
the INTRC accuracy specification.
© 2009 Microchip Technology Inc.
DS39778D-page 403
PIC18F87J11 FAMILY
FIGURE 27-5:
CLKO AND I/O TIMING
Q1
Q2
Q3
Q4
OSC1
11
10
CLKO
12
13
14
19
18
16
I/O pin
(Input)
15
17
I/O pin
(Output)
New Value
Old Value
20, 21
Refer to Figure 27-3 for load conditions.
Note:
TABLE 27-9: CLKO AND I/O TIMING REQUIREMENTS
Param
Symbol
Characteristic
Min
Typ
Max
Units Conditions
No.
10
TOSH2CKL OSC1 ↑ to CLKO ↓
TOSH2CKH OSC1 ↑ to CLKO ↑
—
75
75
15
15
—
—
—
50
—
200
200
30
ns (Note 1)
ns (Note 1)
ns (Note 1)
ns (Note 1)
11
12
13
14
15
16
17
18
—
TCKR
TCKF
CLKO Rise Time
CLKO Fall Time
—
—
30
TCKL2IOV CLKO ↓ to Port Out Valid
TIOV2CKH Port In Valid before CLKO ↑
TCKH2IOI Port In Hold after CLKO ↑
TOSH2IOV OSC1 ↑ (Q1 cycle) to Port Out Valid
—
0.5 TCY + 20 ns
0.25 TCY + 25
—
—
ns
ns
ns
ns
0
—
150
—
TOSH2IOI OSC1 ↑ (Q2 cycle) to Port Input Invalid
100
(I/O in hold time)
19
TIOV2OSH Port Input Valid to OSC1 ↑
0
—
—
ns
(I/O in setup time)
20
TIOR
TIOF
TINP
TRBP
Port Output Rise Time
—
—
—
—
—
—
6
5
ns
ns
ns
ns
21
Port Output Fall Time
22†
23†
INTx pin High or Low Time
RB7:RB4 Change INTx High or Low Time
TCY
TCY
—
—
†
These parameters are asynchronous events not related to any internal clock edges.
Note 1: Measurements are taken in EC mode, where CLKO output is 4 x TOSC.
DS39778D-page 404
© 2009 Microchip Technology Inc.
PIC18F87J11 FAMILY
FIGURE 27-6:
PROGRAM MEMORY READ TIMING DIAGRAM
Q1
Q2
Q3
Q4
Q1
Q2
OSC1
A<19:16>
BA0
Address
Address
Address
Address
Data from External
AD<15:0>
163
162
150
151
160
155
161
166
167
168
169
ALE
164
171
CE
OE
171A
165
Operating Conditions: 2.0V < VCC < 3.6V, -40°C < TA < +125°C unless otherwise stated.
TABLE 27-10: CLKO AND I/O TIMING REQUIREMENTS
Param.
Symbol
Characteristics
Min
Typ
Max
Units
No
150
TadV2alL Address Out Valid to ALE ↓
0.25 TCY – 10
—
—
—
ns
(address setup time)
151
TalL2adl
ALE ↓ to Address Out Invalid
5
—
ns
(address hold time)
155
160
161
162
TalL2oeL ALE ↓ to OE ↓
10
0.125 TCY
—
—
—
—
ns
ns
ns
ns
TadZ2oeL AD high-Z to OE ↓ (bus release to OE)
ToeH2adD OE ↑ to AD Driven
0
0.125 TCY – 5
20
—
—
—
TadV2oeH Least Significant Data Valid before OE ↑
(data setup time)
163
164
165
166
167
168
169
171
171A
ToeH2adl OE ↑ to Data In Invalid (data hold time)
0
—
—
0.25 TCY
0.5 TCY
TCY
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
TalH2alL
ALE Pulse Width
—
ToeL2oeH OE Pulse Width
0.5 TCY – 5
—
—
TalH2alH ALE ↑ to ALE ↑ (cycle time)
—
Tacc
Toe
Address Valid to Data Valid
0.75 TCY – 25
—
—
0.5 TCY – 25
0.625 TCY + 10
—
OE ↓ to Data Valid
—
TalL2oeH ALE ↓ to OE ↑
0.625 TCY – 10
0.25 TCY – 20
—
—
TalH2csL Chip Enable Active to ALE ↓
TubL2oeH AD Valid to Chip Enable Active
—
—
10
© 2009 Microchip Technology Inc.
DS39778D-page 405
PIC18F87J11 FAMILY
FIGURE 27-7:
PROGRAM MEMORY WRITE TIMING DIAGRAM
Q1
Q2
Q3
Q4
Q1
Q2
OSC1
A<19:16>
BA0
Address
Address
Address
166
Data
156
Address
AD<15:0>
153
150
151
ALE
CE
171
171A
154
WRH or
WRL
157A
157
UB or
LB
Operating Conditions: 2.0V < VCC < 3.6V, -40°C < TA < +125°C unless otherwise stated.
TABLE 27-11: PROGRAM MEMORY WRITE TIMING REQUIREMENTS
Param.
Symbol
Characteristics
Min
Typ
Max
Units
No
150
TadV2alL Address Out Valid to ALE ↓ (address setup time)
TalL2adl ALE ↓ to Address Out Invalid (address hold time)
TwrH2adl WRn ↑ to Data Out Invalid (data hold time)
TwrL WRn Pulse Width
0.25 TCY – 10
5
—
—
—
—
—
—
—
—
ns
ns
ns
ns
ns
ns
151
153
154
156
157
5
—
0.5 TCY – 5
0.5 TCY – 10
0.25 TCY
0.5 TCY
—
TadV2wrH Data Valid before WRn ↑ (data setup time)
TbsV2wrL Byte Select Valid before WRn ↓
—
(byte select setup time)
157A
166
TwrH2bsI WRn ↑ to Byte Select Invalid (byte select hold time)
TalH2alH ALE ↑ to ALE ↑ (cycle time)
0.125 TCY – 5
—
TCY
—
—
—
—
10
ns
ns
ns
ns
—
0.25 TCY – 20
—
171
TalH2csL Chip Enable Active to ALE ↓
171A
TubL2oeH AD Valid to Chip Enable Active
—
DS39778D-page 406
© 2009 Microchip Technology Inc.
PIC18F87J11 FAMILY
FIGURE 27-8:
RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND
POWER-UP TIMER TIMING
VDD
MCLR
30
Internal
POR
33
PWRT
Time-out
32
Oscillator
Time-out
Internal
Reset
Watchdog
Timer
Reset
31
34
34
I/O pins
Note:
Refer to Figure 27-3 for load conditions.
TABLE 27-12: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER
AND BROWN-OUT RESET REQUIREMENTS
Param.
No.
Symbol
Characteristic
Min
Typ
Max
Units
Conditions
30
TMCL
TWDT
MCLR Pulse Width (low)
2
—
—
TCY (Note 1)
31
Watchdog Timer Time-out Period
(no postscaler)
3.4
4.0
4.6
ms
32
33
34
TOST
Oscillator Start-up Timer Period
1024 TOSC
45.8
—
65.5
2
1024 TOSC
85.2
—
ms
μs
TOSC = OSC1 period
TPWRT Power-up Timer Period
TIOZ
I/O High-Impedance from MCLR
—
—
Low or Watchdog Timer Reset
38
TCSD
CPU Start-up Time
—
200
—
μs
Note 1: To ensure device reset, MCLR must be low for at least 2 TCY or 400 µs, whichever is lower.
© 2009 Microchip Technology Inc.
DS39778D-page 407
PIC18F87J11 FAMILY
TABLE 27-13: TIMER0 AND TIMER1 EXTERNAL CLOCK TIMINGS
T0CKI
41
40
42
T1OSO/T13CKI
46
45
47
48
TMR0 or
TMR1
Note:
Refer to Figure 27-3 for load conditions.
TABLE 27-14: TIMER0 AND TIMER1 EXTERNAL CLOCK REQUIREMENTS
Param
Symbol
Characteristic
Min
Max Units
Conditions
No.
40
TT0H
T0CKI High Pulse Width
No prescaler
With prescaler
No prescaler
With prescaler
No prescaler
With prescaler
0.5 TCY + 20
10
—
—
—
—
—
—
ns
ns
ns
ns
ns
41
42
TT0L
TT0P
T0CKI Low Pulse Width
T0CKI Period
0.5 TCY + 20
10
TCY + 10
Greater of:
20 ns or
ns N = prescale
value
(TCY + 40)/N
(1, 2, 4,..., 256)
45
46
47
TT1H
TT1L
TT1P
T13CKI High Synchronous, no prescaler
0.5 TCY + 20
—
—
—
—
—
—
—
ns
ns
ns
ns
ns
ns
Time
Synchronous, with prescaler
10
Asynchronous
30
0.5 TCY + 5
10
T13CKI Low Synchronous, no prescaler
Time
Synchronous, with prescaler
Asynchronous
30
T13CKI Input Synchronous
Period
Greater of:
20 ns or
ns N = prescale
value
(TCY + 40)/N
(1, 2, 4, 8)
Asynchronous
60
DC
—
50
ns
kHz
—
FT1
T13CKI Oscillator Input Frequency Range
48
TCKE2TMRI Delay from External T13CKI Clock Edge to
Timer Increment
2 TOSC
7 TOSC
DS39778D-page 408
© 2009 Microchip Technology Inc.
PIC18F87J11 FAMILY
FIGURE 27-9:
PARALLEL SLAVE PORT TIMING
PMCSx
PMRD
PMWR
PS4
PMD<7:0>
PS1
PS3
PS2
Refer to Figure 27-3 for load conditions.
Note:
TABLE 27-15: PARALLEL SLAVE PORT REQUIREMENTS
Param.
Symbol
Characteristic
Min
Max Units
Conditions
No.
PS1
TdtV2wrH
Data In Valid before PMWR or PMCSx Inactive
(setup time)
20
—
—
ns
ns
PS2
TwrH2dtI
PMWR or PMCSx Inactive to Data–In Invalid
(hold time)
20
PS3
PS4
TrdL2dtV
TrdH2dtI
PMRD and PMCSx Active to Data–Out Valid
—
80
30
ns
ns
PMRD Active or PMCSx Inactive to Data–Out
Invalid
10
© 2009 Microchip Technology Inc.
DS39778D-page 409
PIC18F87J11 FAMILY
FIGURE 27-10:
PARALLEL MASTER PORT READ TIMING DIAGRAM
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Q1
Q2
System
Clock
PMA<18:13>
PMD<7:0>
Address
Address<7:0>
PM2
Data
PM6
PM7
PM3
PMRD
PMWR
PM5
PMALL/
PMALH
PM1
PMCS<2:1>
Operating Conditions: 2.0V < VCC < 3.6V, -40°C < TA < +85°C unless otherwise stated.
TABLE 27-16: PARALLEL MASTER PORT READ TIMING REQUIREMENTS
Param.
Symbol
Characteristics
Min
Typ
Max
Units
No
PM1
PM2
PMALL/PMALH Pulse Width
—
—
0.5 TCY
—
—
ns
ns
Address out valid to PMALL/PMALH Invalid
(address setup time)
0.75 TCY
PM3
PMALL/PMALH Invalid to Address Out
Invalid (address hold time)
—
0.25 TCY
—
ns
PM5
PM6
PMRD Pulse Width
—
—
0.5 TCY
—
—
—
ns
ns
PMRD or PMENB Active to Data In Valid
(data setup time)
PM7
PMRD or PMENB Inactive to Data In Invalid
(data hold time)
—
—
—
ns
DS39778D-page 410
© 2009 Microchip Technology Inc.
PIC18F87J11 FAMILY
FIGURE 27-11:
PARALLEL MASTER PORT WRITE TIMING DIAGRAM
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Q1
Q2
System
Clock
PMA<18:13>
PMD<7:0>
Address
Address<7:0>
Data
PM12
PM13
PMRD
PMWR
PM11
PMALL/
PMALH
PMCS<2:1>
PM16
Operating Conditions: 2.0V < VCC < 3.6V, -40°C < TA < +85°C unless otherwise stated.
TABLE 27-17: PARALLEL MASTER PORT WRITE TIMING REQUIREMENTS
Param.
Symbol
Characteristics
Min
Typ
Max
Units
No
PM11
PM12
PMWR Pulse Width
—
—
0.5 TCY
—
—
—
ns
ns
Data Out Valid before PMWR or PMENB
Goes Inactive (data setup time)
PM13
PM16
PMWR or PMEMB Invalid to Data Out
Invalid (data hold time)
—
—
—
—
—
ns
ns
PMCSx Pulse Width
TCY – 5
© 2009 Microchip Technology Inc.
DS39778D-page 411
PIC18F87J11 FAMILY
FIGURE 27-12:
CAPTURE/COMPARE/PWM TIMINGS (INCLUDING ECCP MODULES)
CCPx
(Capture Mode)
50
51
52
CCPx
(Compare or PWM Mode)
54
53
Note:
Refer to Figure 27-3 for load conditions.
TABLE 27-18: CAPTURE/COMPARE/PWM REQUIREMENTS (INCLUDING ECCP MODULES)
Param
Symbol
Characteristic
Min
Max
Units
Conditions
No.
50
TCCL
CCPx Input Low No prescaler
0.5 TCY + 20
—
—
—
—
—
ns
ns
ns
ns
ns
Time
With prescaler
10
0.5 TCY + 20
10
51
52
TCCH
TCCP
CCPx Input
High Time
No prescaler
With prescaler
CCPx Input Period
3 TCY + 40
N
N = prescale
value (1, 4 or 16)
53
54
TCCR
TCCF
CCPx Output Fall Time
CCPx Output Fall Time
—
—
25
25
ns
ns
DS39778D-page 412
© 2009 Microchip Technology Inc.
PIC18F87J11 FAMILY
FIGURE 27-13:
EXAMPLE SPI MASTER MODE TIMING (CKE = 0)
SCKx
(CKP = 0)
78
79
SCKx
(CKP = 1)
78
79
80
MSb
bit 6 - - - - - - 1
LSb
SDOx
SDIx
75, 76
MSb In
74
bit 6 - - - - 1
LSb In
73
Note: Refer to Figure 27-3 for load conditions.
TABLE 27-19: EXAMPLE SPI MODE REQUIREMENTS (MASTER MODE, CKE = 0)
Param
No.
Symbol
Characteristic
Min
Max Units Conditions
73
TDIV2SCH, Setup Time of SDIx Data Input to SCKx Edge
TDIV2SCL
100
—
—
ns
ns
73A
TB2B
Last Clock Edge of Byte 1 to the 1st Clock Edge 1.5 TCY + 40
of Byte 2
75
76
78
79
80
TDOR
TDOF
TSCR
TSCF
SDOx Data Output Rise Time
SDOx Data Output Fall Time
SCKx Output Rise Time
SCKx Output Fall Time
—
—
—
—
—
25
25
25
25
50
ns
ns
ns
ns
ns
TSCH2DOV, SDOx Data Output Valid after SCKx Edge
TSCL2DOV
© 2009 Microchip Technology Inc.
DS39778D-page 413
PIC18F87J11 FAMILY
FIGURE 27-14:
EXAMPLE SPI MASTER MODE TIMING (CKE = 1)
81
SCKx
(CKP = 0)
79
78
73
SCKx
(CKP = 1)
80
LSb
MSb
bit 6 - - - - - - 1
SDOx
SDIx
75, 76
bit 6 - - - - 1
MSb In
74
LSb In
Note: Refer to Figure 27-3 for load conditions.
TABLE 27-20: EXAMPLE SPI MODE REQUIREMENTS (MASTER MODE, CKE = 1)
Param.
No.
Symbol
Characteristic
Min
Max Units Conditions
73
TDIV2SCH, Setup Time of SDIx Data Input to SCKx Edge
TDIV2SCL
100
—
—
ns
ns
74
TSCH2DIL, Hold Time of SDIx Data Input to SCKx Edge
TSCL2DIL
100
75
76
78
79
80
TDOR
TDOF
TSCR
TSCF
SDOx Data Output Rise Time
SDOx Data Output Fall Time
SCKx Output Rise Time
SCKx Output Fall Time
—
—
—
—
—
25
25
25
25
50
ns
ns
ns
ns
ns
TSCH2DOV, SDOx Data Output Valid after SCKx Edge
TSCL2DOV
81
TDOV2SCH, SDOx Data Output Setup to SCKx Edge
TDOV2SCL
TCY
—
ns
DS39778D-page 414
© 2009 Microchip Technology Inc.
PIC18F87J11 FAMILY
FIGURE 27-15:
EXAMPLE SPI SLAVE MODE TIMING (CKE = 0)
SSx
70
SCKx
(CKP = 0)
83
71
72
SCKx
(CKP = 1)
80
SDOx
SDI
LSb
MSb
bit 6 - - - - - - 1
75, 76
77
MSb In
74
bit 6 - - - - 1
LSb In
73
Note:
Refer to Figure 27-3 for load conditions.
TABLE 27-21: EXAMPLE SPI MODE REQUIREMENTS (SLAVE MODE TIMING, CKE = 0)
Param
No.
Symbol
Characteristic
Min
Max Units Conditions
70
TSSL2SCH, SSx ↓ to SCKx ↓ or SCKx ↑ Input
3 TCY
—
ns
TSSL2SCL
3 TCY
70A
71
TSSL2WB SSx ↓ to write to SSPxBUF
—
—
—
—
—
—
ns
TSCH
SCKx Input High Time
Continuous
Single byte
Continuous
Single byte
1.25 TCY + 30
ns
71A
72
40
1.25 TCY + 30
40
ns (Note 1)
TSCL
SCKx Input Low Time
ns
72A
73
ns (Note 1)
TDIV2SCH, Setup Time of SDIx Data Input to SCKx Edge
TDIV2SCL
100
ns
73A
74
TB2B
Last Clock Edge of Byte 1 to the First Clock Edge of Byte 2 1.5 TCY + 40
—
—
ns (Note 2)
TSCH2DIL, Hold Time of SDIx Data Input to SCKx Edge
TSCL2DIL
100
ns
75
76
77
80
TDOR
TDOF
SDOx Data Output Rise Time
SDOx Data Output Fall Time
—
—
10
—
25
25
50
50
ns
ns
ns
ns
TSSH2DOZ SSx ↑ to SDOx Output High-Impedance
TSCH2DOV, SDOx Data Output Valid after SCKx Edge
TSCL2DOV
83
TSCH2SSH, SSx ↑ after SCKx Edge
1.5 TCY + 40
—
ns
TSCL2SSH
Note 1: Requires the use of Parameter #73A.
2: Only if Parameter #71A and #72A are used.
© 2009 Microchip Technology Inc.
DS39778D-page 415
PIC18F87J11 FAMILY
FIGURE 27-16:
EXAMPLE SPI SLAVE MODE TIMING (CKE = 1)
82
SSx
70
SCKx
83
(CKP = 0)
71
72
SCKx
(CKP = 1)
80
LSb
SDOx
SDIx
MSb
bit 6 - - - - - - 1
75, 76
77
MSb In
74
bit 6 - - - - 1
LSb In
Note: Refer to Figure 27-3 for load conditions.
TABLE 27-22: EXAMPLE SPI SLAVE MODE REQUIREMENTS (CKE = 1)
Param
No.
Symbol
Characteristic
Min
Max Units Conditions
70
TSSL2SCH, SSx ↓ to SCKx ↓ or SCKx ↑ Input
3 TCY
—
ns
TSSL2SCL
70A
71
TSSL2WB SSx ↓ to write to SSPxBUF
3 TCY
—
—
—
—
—
—
—
ns
TSCH
TSCL
TB2B
SCKx Input High Time
Continuous
Single byte
Continuous
Single byte
1.25 TCY + 30
ns
71A
72
40
1.25 TCY + 30
40
ns (Note 1)
ns
SCKx Input Low Time
72A
73A
74
ns (Note 1)
ns (Note 2)
ns
Last Clock Edge of Byte 1 to the First Clock Edge of Byte 2 1.5 TCY + 40
TSCH2DIL, Hold Time of SDIx Data Input to SCKx Edge
TSCL2DIL
100
75
76
77
80
TDOR
TDOF
SDOx Data Output Rise Time
SDOx Data Output Fall Time
—
—
10
—
25
25
50
50
ns
ns
ns
ns
TSSH2DOZ SSx ↑ to SDOx Output High-Impedance
TSCH2DOV, SDOx Data Output Valid after SCKx Edge
TSCL2DOV
82
83
TSSL2DOV SDOx Data Output Valid after SSx ↓ Edge
—
50
—
ns
ns
TSCH2SSH, SSx ↑ after SCKx Edge
1.5 TCY + 40
TSCL2SSH
Note 1: Requires the use of Parameter #73A.
2: Only if Parameter #71A and #72A are used.
DS39778D-page 416
© 2009 Microchip Technology Inc.
PIC18F87J11 FAMILY
FIGURE 27-17:
I2C™ BUS START/STOP BITS TIMING
SCLx
91
93
90
92
SDAx
Stop
Condition
Start
Condition
Note: Refer to Figure 27-3 for load conditions.
TABLE 27-23: I2C™ BUS START/STOP BITS REQUIREMENTS (SLAVE MODE)
Param.
Symbol
Characteristic
Min
Max
Units
Conditions
No.
90
TSU:STA Start Condition
Setup Time
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
4700
600
—
—
—
—
—
—
—
—
ns
Only relevant for Repeated
Start condition
91
92
93
THD:STA Start Condition
Hold Time
4000
600
ns
ns
ns
After this period, the first
clock pulse is generated
TSU:STO Stop Condition
Setup Time
4700
600
THD:STO Stop Condition
Hold Time
4000
600
FIGURE 27-18:
I2C™ BUS DATA TIMING
103
102
100
101
SCLx
90
106
107
91
92
SDAx
In
110
109
109
SDAx
Out
Note: Refer to Figure 27-3 for load conditions.
© 2009 Microchip Technology Inc.
DS39778D-page 417
PIC18F87J11 FAMILY
TABLE 27-24: I2C™ BUS DATA REQUIREMENTS (SLAVE MODE)
Param.
No.
Symbol
Characteristic
100 kHz mode
Min
Max
Units
Conditions
100
THIGH
Clock High Time
Clock Low Time
4.0
0.6
—
—
μs
μs
400 kHz mode
MSSP modules
100 kHz mode
400 kHz mode
MSSP modules
1.5 TCY
4.7
—
101
TLOW
—
μs
μs
1.3
—
1.5 TCY
—
—
102
103
TR
SDAx and SCLx Rise Time 100 kHz mode
400 kHz mode
1000
300
ns
ns
20 + 0.1 CB
CB is specified to be from
10 to 400 pF
TF
SDAx and SCLx Fall Time 100 kHz mode
400 kHz mode
—
300
300
ns
ns
20 + 0.1 CB
CB is specified to be from
10 to 400 pF
90
TSU:STA
Start Condition Setup Time 100 kHz mode
400 kHz mode
4.7
0.6
4.0
0.6
0
—
—
μs
μs
μs
μs
ns
μs
ns
ns
μs
μs
ns
ns
μs
μs
Only relevant for Repeated
Start condition
91
THD:STA Start Condition Hold Time 100 kHz mode
400 kHz mode
—
After this period, the first clock
pulse is generated
—
106
107
92
THD:DAT Data Input Hold Time
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
—
0
0.9
—
TSU:DAT Data Input Setup Time
250
100
4.7
0.6
—
(Note 2)
—
TSU:STO Stop Condition Setup Time 100 kHz mode
400 kHz mode
—
—
109
110
TAA
Output Valid from Clock
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
3500
—
(Note 1)
—
TBUF
Bus Free Time
4.7
1.3
—
Time the bus must be free
before a new transmission can
start
—
D102
CB
Bus Capacitive Loading
—
400
pF
Note 1: As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region (min. 300 ns)
of the falling edge of SCLx to avoid unintended generation of Start or Stop conditions.
2
2
2: A Fast mode I C™ bus device can be used in a Standard mode I C bus system, but the requirement, TSU:DAT ≥ 250 ns,
must then be met. This will automatically be the case if the device does not stretch the LOW period of the SCLx signal.
If such a device does stretch the LOW period of the SCLx signal, it must output the next data bit to the SDAx line,
2
TR max. + TSU:DAT = 1000 + 250 = 1250 ns (according to the Standard mode I C bus specification), before the SCLx
line is released.
DS39778D-page 418
© 2009 Microchip Technology Inc.
PIC18F87J11 FAMILY
FIGURE 27-19:
MSSP I2C™ BUS START/STOP BITS TIMING WAVEFORMS
SCLx
93
91
90
92
SDAx
Stop
Condition
Start
Condition
Note: Refer to Figure 27-3 for load conditions.
TABLE 27-25: MSSP I2C™ BUS START/STOP BITS REQUIREMENTS
Param.
Symbol
Characteristic
Min
Max Units
Conditions
No.
90
TSU:STA Start Condition
Setup Time
100 kHz mode
400 kHz mode
1 MHz mode(1) 2(TOSC)(BRG + 1)
2(TOSC)(BRG + 1)
2(TOSC)(BRG + 1)
—
—
—
—
—
—
—
—
—
—
—
—
ns Only relevant for
Repeated Start
condition
91
92
93
THD:STA Start Condition
Hold Time
100 kHz mode
2(TOSC)(BRG + 1)
ns After this period, the
first clock pulse is
generated
400 kHz mode
1 MHz mode(1) 2(TOSC)(BRG + 1)
2(TOSC)(BRG + 1)
TSU:STO Stop Condition
Setup Time
100 kHz mode
2(TOSC)(BRG + 1)
ns
400 kHz mode
1 MHz mode(1) 2(TOSC)(BRG + 1)
2(TOSC)(BRG + 1)
THD:STO Stop Condition
Hold Time
100 kHz mode
2(TOSC)(BRG + 1)
ns
400 kHz mode
2(TOSC)(BRG + 1)
1 MHz mode(1) 2(TOSC)(BRG + 1)
Note 1: Maximum pin capacitance = 10 pF for all I2C™ pins.
FIGURE 27-20:
MSSP I2C™ BUS DATA TIMING
103
102
100
101
SCLx
90
106
91
92
107
SDAx
In
110
109
109
SDAx
Out
Note: Refer to Figure 27-3 for load conditions.
© 2009 Microchip Technology Inc.
DS39778D-page 419
PIC18F87J11 FAMILY
TABLE 27-26: MSSP I2C™ BUS DATA REQUIREMENTS
Param.
Symbol
Characteristic
Min
Max Units
Conditions
No.
100
THIGH
Clock High Time 100 kHz mode
400 kHz mode
2(TOSC)(BRG + 1)
2(TOSC)(BRG + 1)
—
—
ms
ms
ms
ms
ms
ms
ns
1 MHz mode(1) 2(TOSC)(BRG + 1)
—
101
102
103
90
TLOW
TR
Clock Low Time 100 kHz mode
400 kHz mode
2(TOSC)(BRG + 1)
—
2(TOSC)(BRG + 1)
—
1 MHz mode(1) 2(TOSC)(BRG + 1)
—
SDAx and SCLx 100 kHz mode
—
1000
300
300
300
300
100
—
CB is specified to be from
10 to 400 pF
Rise Time
400 kHz mode
1 MHz mode(1)
20 + 0.1 CB
ns
—
—
ns
TF
SDAx and SCLx 100 kHz mode
ns
CB is specified to be from
10 to 400 pF
Fall Time
400 kHz mode
20 + 0.1 CB
—
ns
1 MHz mode(1)
ns
TSU:STA Start Condition 100 kHz mode
2(TOSC)(BRG + 1)
ms Only relevant for Repeated
Setup Time
Start condition
400 kHz mode
2(TOSC)(BRG + 1)
—
ms
1 MHz mode(1) 2(TOSC)(BRG + 1)
—
ms
91
THD:STA Start Condition 100 kHz mode
2(TOSC)(BRG + 1)
—
ms After this period, the first
Hold Time
clock pulse is generated
400 kHz mode
2(TOSC)(BRG + 1)
—
ms
1 MHz mode(1) 2(TOSC)(BRG + 1)
—
ms
ns
106
107
92
THD:DAT Data Input
Hold Time
100 kHz mode
400 kHz mode
1 MHz mode(1)
100 kHz mode
400 kHz mode
1 MHz mode(1)
100 kHz mode
400 kHz mode
0
—
0
0.9
—
ms
ns
TBD
250
TSU:DAT Data Input
Setup Time
—
ns
ns
(Note 2)
100
—
TBD
—
ns
TSU:STO Stop Condition
Setup Time
2(TOSC)(BRG + 1)
—
ms
ms
ms
ns
2(TOSC)(BRG + 1)
—
1 MHz mode(1) 2(TOSC)(BRG + 1)
—
109
110
D102
TAA
TBUF
CB
Output Valid
from Clock
100 kHz mode
400 kHz mode
1 MHz mode(1)
100 kHz mode
400 kHz mode
1 MHz mode(1)
—
—
3500
1000
—
ns
—
ns
Bus Free Time
4.7
1.3
TBD
—
—
ms Time the bus must be free
before a new transmission
—
ms
can start
ms
—
Bus Capacitive Loading
400
pF
Legend: TBD = To Be Determined
Note 1: Maximum pin capacitance = 10 pF for all I2C™ pins.
2: A Fast mode I2C bus device can be used in a Standard mode I2C bus system, but parameter #107 ≥ 250 ns
must then be met. This will automatically be the case if the device does not stretch the LOW period of the
SCLx signal. If such a device does stretch the LOW period of the SCLx signal, it must output the next data
bit to the SDAx line, parameter #102 + parameter #107 = 1000 + 250 = 1250 ns (for 100 kHz mode), before
the SCLx line is released.
DS39778D-page 420
© 2009 Microchip Technology Inc.
PIC18F87J11 FAMILY
FIGURE 27-21:
EUSART SYNCHRONOUS TRANSMISSION (MASTER/SLAVE) TIMING
TXx/CKx
pin
121
121
RXx/DTx
pin
120
Note: Refer to Figure 27-3 for load conditions.
122
TABLE 27-27: EUSART SYNCHRONOUS TRANSMISSION REQUIREMENTS
Param
Symbol
Characteristic
Min
Max
Units Conditions
No.
120
TCKH2DTV SYNC XMIT (MASTER and SLAVE)
Clock High to Data Out Valid
—
—
—
40
20
20
ns
ns
ns
121
122
TCKRF
TDTRF
Clock Out Rise Time and Fall Time (Master mode)
Data Out Rise Time and Fall Time
FIGURE 27-22:
EUSART SYNCHRONOUS RECEIVE (MASTER/SLAVE) TIMING
TXx/CKx
pin
125
RXx/DTx
pin
126
Note: Refer to Figure 27-3 for load conditions.
TABLE 27-28: EUSART SYNCHRONOUS RECEIVE REQUIREMENTS
Param.
Symbol
Characteristic
Min
Max
Units
Conditions
No.
125
TDTV2CKL SYNC RCV (MASTER and SLAVE)
Data Hold before CKx ↓ (DTx hold time)
10
15
—
—
ns
ns
126
TCKL2DTL Data Hold after CKx ↓ (DTx hold time)
© 2009 Microchip Technology Inc.
DS39778D-page 421
PIC18F87J11 FAMILY
TABLE 27-29: A/D CONVERTER CHARACTERISTICS: PIC18F87J11 FAMILY (INDUSTRIAL)
Param
Symbol
Characteristic
Min
Typ
Max
Units
Conditions
No.
A01
NR
Resolution
—
—
—
—
—
—
10
bit ΔVREF ≥ 3.0V
A03
A04
A06
A07
A10
A20
EIL
Integral Linearity Error
Differential Linearity Error
Offset Error
—
<±1
<±1
<±3
<±3
LSb ΔVREF ≥ 3.0V
LSb ΔVREF ≥ 3.0V
LSb ΔVREF ≥ 3.0V
LSb ΔVREF ≥ 3.0V
EDL
EOFF
EGN
—
—
—
Gain Error
—
Monotonicity
Guaranteed(1)
—
VSS ≤ VAIN ≤ VREF
ΔVREF Reference Voltage Range
2.0
3
—
—
—
—
V
V
VDD < 3.0V
VDD ≥ 3.0V
(VREFH – VREFL)
A21
A22
A25
A30
VREFH Reference Voltage High
VSS
—
VREFH
VDD – 3.0V
VREFH
V
V
VREFL
VAIN
Reference Voltage Low
Analog Input Voltage
VSS – 0.3V
VREFL
—
—
—
—
V
ZAIN
Recommended Impedance of
Analog Voltage Source
2.5
kΩ
A50
IREF
VREF Input Current(2)
—
—
—
—
5
150
μA During VAIN acquisition.
μA During A/D conversion
cycle.
Note 1: The A/D conversion result never decreases with an increase in the input voltage and has no missing codes.
2: VREFH current is from RA3/AN3/VREF+ pin or VDD, whichever is selected as the VREFH source.
VREFL current is from RA2/AN2/VREF- pin or VSS, whichever is selected as the VREFL source.
FIGURE 27-23:
A/D CONVERSION TIMING
BSF ADCON0, GO
(Note 2)
131
130
Q4
A/D CLK
132
. . .
. . .
0
9
8
7
2
1
A/D DATA
ADRES
NEW_DATA
OLD_DATA
TCY (Note 1)
ADIF
GO
DONE
SAMPLING STOPPED
SAMPLE
Note 1: If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the SLEEPinstruction
to be executed.
2: This is a minimal RC delay (typically 100 ns), which also disconnects the holding capacitor from the analog input.
DS39778D-page 422
© 2009 Microchip Technology Inc.
PIC18F87J11 FAMILY
TABLE 27-30: A/D CONVERSION REQUIREMENTS
Param
Symbol
Characteristic
Min
Max
Units
Conditions
No.
130
TAD
A/D Clock Period
0.7
TBD
11
25.0(1)
μs TOSC based, VREF ≥ 3.0V
μs A/D RC mode
TAD
1
131
TCNV
Conversion Time
12
(not including acquisition time) (Note 2)
132
135
TBD
TACQ
TSWC
TDIS
Acquisition Time (Note 3)
Switching Time from Convert → Sample
Discharge Time
1.4
—
—
(Note 4)
—
μs -40°C to +85°C
μs
0.2
Legend: TBD = To Be Determined
Note 1: The time of the A/D clock period is dependent on the device frequency and the TAD clock divider.
2: ADRES registers may be read on the following TCY cycle.
3: The time for the holding capacitor to acquire the “New” input voltage when the voltage changes full scale
after the conversion (VDD to VSS or VSS to VDD). The source impedance (RS) on the input channels is 50Ω.
4: On the following cycle of the device clock.
© 2009 Microchip Technology Inc.
DS39778D-page 423
PIC18F87J11 FAMILY
NOTES:
DS39778D-page 424
© 2009 Microchip Technology Inc.
PIC18F87J11 FAMILY
28.0 PACKAGING INFORMATION
28.1 Package Marking Information
64-Lead TQFP
Example
XXXXXXXXXX
XXXXXXXXXX
XXXXXXXXXX
YYWWNNN
18F67J11
-I/PT
0810017
e
3
80-Lead TQFP
Example
XXXXXXXXXXXX
XXXXXXXXXXXX
YYWWNNN
PIC18F87J11
-I/PT
0810017
e
3
Legend: XX...X Customer-specific information
Y
YY
WW
NNN
Year code (last digit of calendar year)
Year code (last 2 digits of calendar year)
Week code (week of January 1 is week ‘01’)
Alphanumeric traceability code
e
3
Pb-free JEDEC designator for Matte Tin (Sn)
*
This package is Pb-free. The Pb-free JEDEC designator (
can be found on the outer packaging for this package.
)
e3
Note: In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
© 2009 Microchip Technology Inc.
DS39778D-page 425
PIC18F87J11 FAMILY
28.2 Package Details
The following sections give the technical details of the packages.
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DS39778D-page 426
© 2009 Microchip Technology Inc.
PIC18F87J11 FAMILY
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© 2009 Microchip Technology Inc.
DS39778D-page 427
PIC18F87J11 FAMILY
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DS39778D-page 428
© 2009 Microchip Technology Inc.
PIC18F87J11 FAMILY
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© 2009 Microchip Technology Inc.
DS39778D-page 429
PIC18F87J11 FAMILY
NOTES:
DS39778D-page 430
© 2009 Microchip Technology Inc.
PIC18F87J11 FAMILY
APPENDIX A: REVISION HISTORY
Revision A (January 2007)
APPENDIX B: DEVICE
DIFFERENCES
The differences between the devices listed in this data
sheet are shown in Table B-1.
Original data sheet for the PIC18F87J11 Family of
devices.
Revision B (February 2007)
Updated values in Power-Down and Supply Current
table in “DC Characteristics” section.
Revision C (January 2008)
Updated text and values in several chapters and added
land pattern diagrams for both packages.
Revision D (October 2009)
Removed “Preliminary” marking.
TABLE B-1:
Features
DEVICE DIFFERENCES BETWEEN PIC18F87J11 FAMILY MEMBERS
PIC18F66J11 PIC18F66J16 PIC18F67J11 PIC18F86J11 PIC18F86J16 PIC18F87J11
Program memory
64K
96K
128K
64K
96K
128K
Program Memory
(Instructions)
32764
49148
65532
32764
49148
65532
I/O Ports
Ports A, B, C, D, E, F, G
No
Ports A, B, C, D, E, F, G, H, J
Yes
EMB
10-Bit ADC module
Packages
11 Input Channels
64-Pin TQFP
15 Input Channels
80-Pin TQFP
© 2009 Microchip Technology Inc.
DS39778D-page 431
PIC18F87J11 FAMILY
NOTES:
DS39778D-page 432
© 2009 Microchip Technology Inc.
PIC18F87J11 FAMILY
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© 2009 Microchip Technology Inc.
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PIC18F87J11 FAMILY
READER RESPONSE
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DS39778D-page 434
© 2009 Microchip Technology Inc.
PIC18F87J11 FAMILY
INDEX
Comparator Voltage Reference Output Buffer Example
313
A
A/D ................................................................................... 293
A/D Converter Interrupt, Configuring ....................... 297
Acquisition Requirements ........................................ 298
ADCAL Bit ................................................................ 301
ADRESH Register .................................................... 296
Analog Port Pins, Configuring .................................. 299
Associated Registers ............................................... 302
Automatic Acquisition Time ...................................... 299
Calibration ................................................................ 301
Configuring the Module ............................................ 297
Conversion Clock (TAD) ........................................... 299
Conversion Requirements ....................................... 423
Conversion Status (GO/DONE Bit) .......................... 296
Conversions ............................................................. 300
Converter Characteristics ........................................ 422
Operation in Power-Managed Modes ...................... 301
Special Event Trigger (ECCP) ......................... 209, 300
Use of the ECCP2 Trigger ....................................... 300
Absolute Maximum Ratings ............................................. 385
AC (Timing) Characteristics ............................................. 400
Load Conditions for Device Timing Specifications ... 401
Parameter Symbology ............................................. 400
Temperature and Voltage Specifications ................. 401
Timing Conditions .................................................... 401
ACKSTAT ........................................................................ 259
ACKSTAT Status Flag ..................................................... 259
ADCAL Bit ........................................................................ 301
ADCON0 Register
GO/DONE Bit ........................................................... 296
ADDFSR .......................................................................... 374
ADDLW ............................................................................ 337
ADDULNK ........................................................................ 374
ADDWF ............................................................................ 337
ADDWFC ......................................................................... 338
ADRESL Register ............................................................ 296
Analog-to-Digital Converter. See A/D.
ANDLW ............................................................................ 338
ANDWF ............................................................................ 339
Assembler
MPASM Assembler .................................................. 382
Auto-Wake-up on Sync Break Character ......................... 284
Compare Mode Operation ....................................... 200
Connections for On-Chip Voltage Regulator ........... 325
Demultiplexed Addressing Mode ............................. 167
Device Clock .............................................................. 33
Enhanced PWM ....................................................... 210
EUSART Receive .................................................... 283
EUSART Transmit ................................................... 281
External Power-on Reset Circuit (Slow VDD Power-up)
53
Fail-Safe Clock Monitor ........................................... 327
Fully Multiplexed Addressing Mode ......................... 167
Generic I/O Port Operation ...................................... 129
Interrupt Logic .......................................................... 114
LCD Control ............................................................. 176
Legacy Parallel Slave Port ...................................... 161
MSSP (SPI Mode) ................................................... 223
2
MSSPx (I C Master Mode) ...................................... 253
2
MSSPx (I C Mode) .................................................. 233
Multiplexed Addressing Application ......................... 175
On-Chip Reset Circuit ................................................ 51
Parallel EEPROM (Up to 15-Bit Address, 16-Bit Data) .
176
Parallel EEPROM (Up to 15-Bit Address, 8-Bit Data) ...
176
Parallel Master/Slave Connection Addressed Buffer 164
Parallel Master/Slave Connection Buffered ............. 163
Partially Multiplexed Addressing Application ........... 175
Partially Multiplexed Addressing Mode .................... 167
PIC18F6XJ1X (64-Pin) .............................................. 12
PIC18F8XJ1X (80-Pin) .............................................. 13
PLL ............................................................................ 38
PMP Module ............................................................ 153
PWM Operation (Simplified) .................................... 202
Reads From Flash Program Memory ........................ 93
Table Read Operation ............................................... 89
Table Write Operation ............................................... 90
Table Writes to Flash Program Memory .................... 95
Timer0 in 16-Bit Mode ............................................. 180
Timer0 in 8-Bit Mode ............................................... 180
Timer1 ..................................................................... 184
Timer1 (16-Bit Read/Write Mode) ............................ 184
Timer2 ..................................................................... 190
Timer3 ..................................................................... 192
Timer3 (16-Bit Read/Write Mode) ............................ 192
Timer4 ..................................................................... 196
Watchdog Timer ...................................................... 323
BN .................................................................................... 340
BNC ................................................................................. 341
BNN ................................................................................. 341
BNOV .............................................................................. 342
BNZ ................................................................................. 342
BOR. See Brown-out Reset.
B
Baud Rate Generator ....................................................... 255
BC .................................................................................... 339
BCF .................................................................................. 340
BF .................................................................................... 259
BF Status Flag ................................................................. 259
Block Diagrams
16-Bit Byte Select Mode .......................................... 105
16-Bit Byte Write Mode ............................................ 103
16-Bit Word Write Mode ........................................... 104
8-Bit Multiplexed Address and Data Application ...... 175
8-Bit Multiplexed Mode Example ............................. 107
A/D ........................................................................... 296
Analog Input Model .................................................. 297
Baud Rate Generator ............................................... 255
Capture Mode Operation ......................................... 199
Comparator .............................................................. 303
Comparator Analog Input Model .............................. 306
Comparator I/O Configurations ................................ 308
Comparator Voltage Reference ............................... 311
BOV ................................................................................. 345
BRA ................................................................................. 343
Break Character (12-Bit) Transmit and Receive .............. 286
BRG. See Baud Rate Generator.
Brown-out Reset (BOR) ..................................................... 53
and On-Chip Voltage Regulator .............................. 326
Detecting ................................................................... 53
Disabling in Sleep Mode ............................................ 53
BSF .................................................................................. 343
© 2009 Microchip Technology Inc.
DS39778D-page 435
PIC18F87J11 FAMILY
BTFSC .............................................................................344
BTFSS ..............................................................................344
BTG ..................................................................................345
BZ .....................................................................................346
Associated Registers ............................................... 310
Configuration ........................................................... 307
Control ..................................................................... 307
Effects of a Reset .................................................... 310
Enable, Input Selection ............................................ 307
Enable, Output Selection ......................................... 307
Interrupts ................................................................. 309
Operation ................................................................. 306
Operation During Sleep ........................................... 310
Reference
C
C Compilers
MPLAB C18 .............................................................382
MPLAB C30 .............................................................382
Calibration (A/D Converter) ..............................................301
CALL ................................................................................346
CALLW .............................................................................375
Capture (CCP Module) .....................................................199
Associated Registers ...............................................201
CCP Pin Configuration .............................................199
CCPRxH:CCPRxL Registers ...................................199
Prescaler ..................................................................199
Software Interrupt ....................................................199
Timer1/Timer3 Mode Selection ................................199
Capture (ECCP Module) ..................................................209
Capture/Compare/PWM (CCP) ........................................197
Capture Mode. See Capture.
Response Time ............................................... 306
Single Comparator ................................................... 306
Comparator Specifications ............................................... 399
Comparator Voltage Reference ....................................... 311
Accuracy and Error .................................................. 313
Associated Registers ............................................... 313
Configuring .............................................................. 312
Connection Considerations ...................................... 313
Effects of a Reset .................................................... 313
Operation During Sleep ........................................... 313
Compare (CCP Module) .................................................. 200
Associated Registers ............................................... 201
CCPRx Register ...................................................... 200
Pin Configuration ..................................................... 200
Software Interrupt .................................................... 200
Timer1/Timer3 Mode Selection ................................ 200
Compare (ECCP Module) ................................................ 209
Special Event Trigger ...................................... 209, 300
Compare (ECCPx Modules)
Special Event Trigger .............................................. 193
Computed GOTO ............................................................... 69
Configuration Bits ............................................................ 315
Configuration Mismatch Reset (CM) .................................. 53
Configuration Register Protection .................................... 329
Core Features
Easy Migration ........................................................... 10
Expanded Memory ....................................................... 9
Extended Instruction Set ............................................. 9
External Memory Bus .................................................. 9
nanoWatt Technology .................................................. 9
Oscillator Options and Features .................................. 9
CPFSEQ .......................................................................... 348
CPFSGT .......................................................................... 349
CPFSLT ........................................................................... 349
Crystal Oscillator/Ceramic Resonator ................................ 37
Customer Change Notification Service ............................ 433
Customer Notification Service ......................................... 433
Customer Support ............................................................ 433
CCP Mode and Timer Resources ............................198
CCPRxH Register ....................................................198
CCPRxL Register .....................................................198
Compare Mode. See Compare.
Module Configuration ...............................................198
Timer Interconnect Configurations ...........................198
Clock Sources ....................................................................35
Default System Clock on Reset .................................36
Selection Using OSCCON Register ...........................36
CLRF ................................................................................347
CLRWDT ..........................................................................347
Code Examples
16 x 16 Signed Multiply Routine ..............................112
16 x 16 Unsigned Multiply Routine ..........................112
8 x 8 Signed Multiply Routine ..................................111
8 x 8 Unsigned Multiply Routine ..............................111
A/D Calibration Routine ...........................................301
Changing Between Capture Prescalers ...................199
Computed GOTO Using an Offset Value ...................69
Erasing a Flash Program Memory Row .....................94
Fast Register Stack ....................................................69
How to Clear RAM (Bank 1) Using Indirect Addressing .
83
Implementing a Real-Time Clock Using a Timer1 Inter-
rupt Service ......................................................187
Initializing PORTA ....................................................132
Initializing PORTB ....................................................134
Initializing PORTC ....................................................136
Initializing PORTD ....................................................138
Initializing PORTE ....................................................141
Initializing PORTF ....................................................144
Initializing PORTG ...................................................146
Initializing PORTH ....................................................148
Initializing PORTJ ....................................................151
Loading the SSP1BUF (SSP1SR) Register .............226
Reading a Flash Program Memory Word ..................93
Saving STATUS, WREG and BSR Registers in RAM ...
128
D
Data Addressing Modes .................................................... 83
Comparing Addressing Modes with the Extended In-
struction Set Enabled ........................................ 87
Direct ......................................................................... 83
Indexed Literal Offset ................................................ 86
BSR ................................................................... 88
Instructions Affected .......................................... 86
Mapping Access Bank ....................................... 88
Indirect ....................................................................... 83
Inherent and Literal .................................................... 83
Data Memory ..................................................................... 72
Access Bank .............................................................. 74
Bank Select Register (BSR) ...................................... 72
Extended Instruction Set ........................................... 86
General Purpose Registers ....................................... 74
Memory Map .............................................................. 73
Single-Word Write to Flash Program Memory ...........97
Writing to Flash Program Memory .............................96
Code Protection ...............................................................315
COMF ...............................................................................348
Comparator ......................................................................303
Analog Input Connection Considerations .................306
DS39778D-page 436
© 2009 Microchip Technology Inc.
PIC18F87J11 FAMILY
Memory Maps
Special Function Registers ................................ 75
Special Function Registers ........................................ 75
Context Defined SFRs ....................................... 76
Baud Rate Error, Calculating ........................... 276
Baud Rates, Asynchronous Modes ................. 277
High Baud Rate Select (BRGH Bit) ................. 275
Sampling ......................................................... 275
Synchronous Master Mode ...................................... 287
Associated Registers, Receive ........................ 290
Associated Registers, Transmit ....................... 288
Reception ........................................................ 289
Transmission ................................................... 287
Synchronous Slave Mode ........................................ 290
Associated Registers, Receive ........................ 292
Associated Registers, Transmit ....................... 291
Reception ........................................................ 291
Transmission ................................................... 290
Extended Instruction Set
ADDFSR .................................................................. 374
ADDULNK ............................................................... 374
CALLW .................................................................... 375
MOVSF .................................................................... 375
MOVSS .................................................................... 376
PUSHL ..................................................................... 376
SUBFSR .................................................................. 377
SUBULNK ................................................................ 377
External Memory Bus ........................................................ 99
16-Bit Byte Select Mode .......................................... 105
16-Bit Byte Write Mode ............................................ 103
16-Bit Data Width Modes ......................................... 102
16-Bit Mode Timing ................................................. 106
16-Bit Word Write Mode .......................................... 104
8-Bit Data Width Mode ............................................ 107
8-Bit Mode Timing ................................................... 108
Address and Data Line Usage (table) ..................... 101
Address and Data Width .......................................... 101
Address Shifting ...................................................... 101
Control ..................................................................... 100
I/O Port Functions ...................................................... 99
Operation in Power-Managed Modes ...................... 109
Program Memory Modes ......................................... 102
Extended Microcontroller ................................. 102
Microcontroller ................................................. 102
Wait States .............................................................. 102
Weak Pull-ups on Port Pins ..................................... 102
External Oscillator Modes
Shared Address ................................................. 76
DAW ................................................................................. 350
DC Characteristics ........................................................... 396
Power-Down and Supply Current ............................ 388
Supply Voltage ......................................................... 387
DCFSNZ .......................................................................... 351
DECF ............................................................................... 350
DECFSZ ........................................................................... 351
Default System Clock ......................................................... 36
Development Support ...................................................... 381
Device Differences ........................................................... 431
Device Overview .................................................................. 9
Details on Individual Family Members ....................... 10
Features (64-Pin Devices) ......................................... 11
Features (80-Pin Devices) ......................................... 11
Direct Addressing ............................................................... 84
E
ECCP
Associated Registers ............................................... 221
Capture and Compare Modes .................................. 209
Enhanced PWM Mode ............................................. 210
Standard PWM Mode ............................................... 209
Effect on Standard PIC Instructions ................................. 378
Effects of Power-Managed Modes on Various Clock Sources
42
Electrical Characteristics .................................................. 385
Enhanced Capture/Compare/PWM (ECCP) .................... 205
Capture Mode. See Capture (ECCP Module).
ECCP1/ECCP3 Outputs and Program Memory Mode ...
206
ECCP2 Outputs and Program Memory Modes ........ 206
Outputs and Configuration ....................................... 206
Pin Configurations for ECCP1 ................................. 207
Pin Configurations for ECCP2 ................................. 208
Pin Configurations for ECCP3 ................................. 208
PWM Mode. See PWM (ECCP Module).
Timer Resources ...................................................... 207
Use of CCP4/CCP5 with ECCP1/ECCP3 ................ 207
Enhanced Universal Synchronous Asynchronous Receiver
Transmitter (EUSART). See EUSART.
Clock Input (EC Modes) ............................................ 38
HS .............................................................................. 37
ENVREG pin .................................................................... 325
Equations
F
A/D Acquisition Time ................................................ 298
A/D Minimum Charging Time ................................... 298
Calculating the Minimum Required Acquisition Time .....
298
Fail-Safe Clock Monitor ........................................... 315, 327
Exiting ...................................................................... 328
Interrupts in Power-Managed Modes ...................... 328
POR or Wake-up From Sleep .................................. 328
WDT During Oscillator Failure ................................. 327
Fast Register Stack ........................................................... 69
Firmware Instructions ...................................................... 331
Flash Configuration Words .............................................. 315
Flash Program Memory ..................................................... 89
Associated Registers ................................................. 98
Control Registers ....................................................... 90
EECON1 and EECON2 ..................................... 90
TABLAT (Table Latch) Register ........................ 92
TBLPTR (Table Pointer) Register ...................... 92
Erase Sequence ........................................................ 94
Erasing ...................................................................... 94
Operation During Code-Protect ................................. 98
Reading ..................................................................... 93
Table Pointer
Errata ................................................................................... 7
EUSART
Asynchronous Mode ................................................ 281
12-Bit Break Transmit and Receive ................. 286
Associated Registers, Receive ........................ 284
Associated Registers, Transmit ....................... 282
Auto-Wake-up on Sync Break ......................... 284
Receiver ........................................................... 283
Setting Up 9-Bit Mode with Address Detect ..... 283
Transmitter ....................................................... 281
Baud Rate Generator
Operation in Power-Managed Mode ................ 275
Baud Rate Generator (BRG) .................................... 275
Associated Registers ....................................... 276
Auto-Baud Rate Detect .................................... 279
© 2009 Microchip Technology Inc.
DS39778D-page 437
PIC18F87J11 FAMILY
Boundaries Based on Operation ........................92
Table Pointer Boundaries ..........................................92
Table Reads and Table Writes ..................................89
Write Sequence .........................................................95
Write Sequence (Word Programming) .......................97
Writing ........................................................................95
Unexpected Termination ....................................98
Write Verify ........................................................98
FSCM. See Fail-Safe Clock Monitor.
In-Circuit Serial Programming (ICSP) ...................... 315, 329
Indexed Literal Offset Addressing
and Standard PIC18 Instructions ............................. 378
Indexed Literal Offset Mode ............................................. 378
Indirect Addressing ............................................................ 84
INFSNZ ............................................................................ 353
Initialization Conditions for all Registers ...................... 57–62
Instruction Cycle ................................................................ 70
Clocking Scheme ....................................................... 70
Flow/Pipelining ........................................................... 70
Instruction Set .................................................................. 331
ADDLW .................................................................... 337
ADDWF .................................................................... 337
ADDWF (Indexed Literal Offset Mode) .................... 379
ADDWFC ................................................................. 338
ANDLW .................................................................... 338
ANDWF .................................................................... 339
BC ............................................................................ 339
BCF ......................................................................... 340
BN ............................................................................ 340
BNC ......................................................................... 341
BNN ......................................................................... 341
BNOV ...................................................................... 342
BNZ ......................................................................... 342
BOV ......................................................................... 345
BRA ......................................................................... 343
BSF .......................................................................... 343
BSF (Indexed Literal Offset Mode) .......................... 379
BTFSC ..................................................................... 344
BTFSS ..................................................................... 344
BTG ......................................................................... 345
BZ ............................................................................ 346
CALL ........................................................................ 346
CLRF ....................................................................... 347
CLRWDT ................................................................. 347
COMF ...................................................................... 348
CPFSEQ .................................................................. 348
CPFSGT .................................................................. 349
CPFSLT ................................................................... 349
DAW ........................................................................ 350
DCFSNZ .................................................................. 351
DECF ....................................................................... 350
DECFSZ .................................................................. 351
Extended Instructions .............................................. 373
Considerations when Enabling ........................ 378
Syntax .............................................................. 373
Use with MPLAB IDE Tools ............................. 380
General Format ........................................................ 333
GOTO ...................................................................... 352
INCF ........................................................................ 352
INCFSZ .................................................................... 353
INFSNZ .................................................................... 353
IORLW ..................................................................... 354
IORWF ..................................................................... 354
LFSR ....................................................................... 355
MOVF ...................................................................... 355
MOVFF .................................................................... 356
MOVLB .................................................................... 356
MOVLW ................................................................... 357
MOVWF ................................................................... 357
MULLW .................................................................... 358
MULWF .................................................................... 358
NEGF ....................................................................... 359
NOP ......................................................................... 359
Opcode Field Descriptions ....................................... 332
G
GOTO ...............................................................................352
H
Hardware Multiplier ..........................................................111
8 x 8 Multiplication Algorithms .................................111
Operation .................................................................111
Performance Comparison (table) .............................111
I
I/O Ports ...........................................................................129
Input Pull-up Configuration ......................................130
Open-Drain Outputs .................................................130
Pin Capabilities ........................................................129
2
I C Mode (MSSP)
Acknowledge Sequence Timing ...............................262
Associated Registers ...............................................270
Baud Rate Generator ...............................................255
Bus Collision
During a Repeated Start Condition ..................267
During a Stop Condition ...................................269
Clock Arbitration .......................................................256
Clock Stretching .......................................................248
10-Bit Slave Receive Mode (SEN = 1) .............248
10-Bit Slave Transmit Mode .............................248
7-Bit Slave Receive Mode (SEN = 1) ...............248
7-Bit Slave Transmit Mode ...............................248
Clock Synchronization and the CKP bit ...................249
Effects of a Reset .....................................................263
General Call Address Support .................................252
2
I C Clock Rate w/BRG .............................................255
Master Mode ............................................................253
Operation .........................................................254
Reception .........................................................259
Repeated Start Condition Timing .....................258
Start Condition Timing .....................................257
Transmission ....................................................259
Multi-Master Communication, Bus Collision and Arbitra-
tion ...................................................................263
Multi-Master Mode ...................................................263
Operation .................................................................238
Read/Write Bit Information (R/W Bit) ............... 238, 241
Registers ..................................................................233
Serial Clock (RC3/SCKx/SCLx) ...............................241
Slave Mode ..............................................................238
Address Masking Modes
5-Bit .........................................................239
7-Bit .........................................................240
Addressing .......................................................238
Reception .........................................................241
Transmission ....................................................241
Sleep Operation .......................................................263
Stop Condition Timing ..............................................262
INCF .................................................................................352
INCFSZ ............................................................................353
In-Circuit Debugger ..........................................................329
DS39778D-page 438
© 2009 Microchip Technology Inc.
PIC18F87J11 FAMILY
POP ......................................................................... 360
PUSH ....................................................................... 360
RCALL ..................................................................... 361
RESET ..................................................................... 361
RETFIE .................................................................... 362
RETLW .................................................................... 362
RETURN .................................................................. 363
RLCF ........................................................................ 363
RLNCF ..................................................................... 364
RRCF ....................................................................... 364
RRNCF .................................................................... 365
SETF ........................................................................ 365
SETF (Indexed Literal Offset Mode) ........................ 379
SLEEP ..................................................................... 366
Standard Instructions ............................................... 331
SUBFWB .................................................................. 366
SUBLW .................................................................... 367
SUBWF .................................................................... 367
SUBWFB .................................................................. 368
SWAPF .................................................................... 368
TBLRD ..................................................................... 369
TBLWT ..................................................................... 370
TSTFSZ ................................................................... 371
XORLW .................................................................... 371
XORWF .................................................................... 372
Master Synchronous Serial Port (MSSP). See MSSP.
Memory Organization ........................................................ 63
Data Memory ............................................................. 72
Program Memory ....................................................... 63
Memory Programming Requirements .............................. 398
Microchip Internet Web Site ............................................. 433
MOVF .............................................................................. 355
MOVFF ............................................................................ 356
MOVLB ............................................................................ 356
MOVLW ........................................................................... 357
MOVSF ............................................................................ 375
MOVSS ............................................................................ 376
MOVWF ........................................................................... 357
MPLAB ASM30 Assembler, Linker, Librarian .................. 382
MPLAB ICD 2 In-Circuit Debugger .................................. 383
MPLAB ICE 2000 High-Performance Universal In-Circuit Em-
ulator ........................................................................ 383
MPLAB Integrated Development Environment Software . 381
MPLAB PM3 Device Programmer ................................... 383
MPLAB REAL ICE In-Circuit Emulator System ............... 383
MPLINK Object Linker/MPLIB Object Librarian ............... 382
MSSP
ACK Pulse ....................................................... 238, 241
2
2
I C Mode. See I C Mode.
Module Overview ..................................................... 223
SPI Master/Slave Connection .................................. 227
MULLW ............................................................................ 358
MULWF ............................................................................ 358
INTCON Register
RBIF Bit .................................................................... 134
INTCON Registers ........................................................... 115
2
Inter-Integrated Circuit. See I C.
N
Internal Oscillator Block ..................................................... 39
Adjustment ................................................................. 40
INTIO Modes .............................................................. 39
INTOSC Frequency Drift ............................................ 40
INTOSC Output Frequency ........................................ 40
INTPLL Modes ........................................................... 39
Internal RC Block
NEGF ............................................................................... 359
NOP ................................................................................. 359
O
Open-Drain Outputs ......................................................... 130
Oscillator Configuration ..................................................... 33
EC .............................................................................. 33
ECPLL ....................................................................... 33
HS .............................................................................. 33
HSPLL ....................................................................... 33
Internal Oscillator Block ............................................. 39
INTIO1 ....................................................................... 33
INTIO2 ....................................................................... 33
INTPLL1 .................................................................... 33
INTPLL2 .................................................................... 33
Oscillator Selection .......................................................... 315
Oscillator Start-up Timer (OST) ......................................... 42
Oscillator Switching ........................................................... 35
Oscillator Transitions ......................................................... 36
Oscillator, Timer1 ..................................................... 183, 193
Oscillator, Timer3 ............................................................. 191
Use with WDT .......................................................... 323
Internal Voltage Reference Specifications ....................... 399
Internet Address ............................................................... 433
Interrupt Sources ............................................................. 315
A/D Conversion Complete ....................................... 297
Capture Complete (CCP) ......................................... 199
Compare Complete (CCP) ....................................... 200
Interrupt-on-Change (RB7:RB4) .............................. 134
TMR0 Overflow ........................................................ 181
TMR2 to PR2 Match (PWM) .................................... 210
TMR3 Overflow ................................................ 191, 193
TMR4 to PR4 Match ................................................ 196
TMR4 to PR4 Match (PWM) .................................... 195
Interrupts .......................................................................... 113
During, Context Saving ............................................ 128
INTx Pin ................................................................... 128
PORTB, Interrupt-on-Change .................................. 128
TMR0 ....................................................................... 128
Interrupts, Flag Bits
P
Packaging ........................................................................ 425
Details ...................................................................... 426
Marking .................................................................... 425
Parallel Master Port (PMP) .............................................. 153
Application Examples .............................................. 175
Associated Registers ............................................... 177
Control Registers ..................................................... 154
Data Registers ......................................................... 160
Master Port Modes .................................................. 166
Slave Port Modes .................................................... 161
PICSTART Plus Development Programmer .................... 384
PIE Registers ................................................................... 121
Pin Functions
Interrupt-on-Change (RB7:RB4) Flag (RBIF Bit) ..... 134
INTOSC, INTRC. See Internal Oscillator Block.
IORLW ............................................................................. 354
IORWF ............................................................................. 354
IPR Registers ................................................................... 124
L
LFSR ................................................................................ 355
M
Master Clear (MCLR) ......................................................... 53
© 2009 Microchip Technology Inc.
DS39778D-page 439
PIC18F87J11 FAMILY
AVDD ..........................................................................21
AVDD ..........................................................................31
AVSS ..........................................................................21
AVSS ..........................................................................31
ENVREG .............................................................. 21, 31
MCLR ................................................................... 14, 22
OSC1/CLKI/RA7 .................................................. 14, 22
OSC2/CLKO/RA6 ................................................ 14, 22
RA0/AN0 .............................................................. 15, 23
RA1/AN1 .............................................................. 15, 23
RA2/AN2/VREF- .................................................... 15, 23
RA3/AN3/VREF+ ................................................... 15, 23
RA4/PMD5/T0CKI ......................................................23
RA4/T0CKI .................................................................15
RA5/AN4 ....................................................................15
RA5/PMD4/AN4 .........................................................23
RA6 ...................................................................... 15, 23
RA7 ...................................................................... 15, 23
RB0/FLT0/INT0 .................................................... 16, 24
RB1/INT1/PMA4 .................................................. 16, 24
RB2/INT2/PMA3 .................................................. 16, 24
RB3/INT3//PMA2/ECCP2/P2A ...................................24
RB3/INT3/PMA2 ........................................................16
RB4/KBI0/PMA1 .................................................. 16, 24
RB5/KBI1/PMA0 .................................................. 16, 24
RB6/KBI2/PGC .................................................... 16, 24
RB7/KBI3/PGD .................................................... 16, 24
RC0/T1OSO/T13CKI ...........................................17, 25
RC1/T1OSI/ECCP2/P2A ...................................... 17, 25
RC2/ECCP1/P1A ................................................. 17, 25
RC3/SCK1/SCL1 ................................................. 17, 25
RC4/SDI1/SDA1 .................................................. 17, 25
RC5/SDO1 ........................................................... 17, 25
RC6/TX1/CK1 ...................................................... 17, 25
RC7/RX1/DT1 ...................................................... 17, 25
RD0/AD0/PMD0 .........................................................26
RD0/PMD0 .................................................................18
RD1/AD1/PMD1 .........................................................26
RD1/PMD1 .................................................................18
RD2/AD2/PMD2 .........................................................26
RD2/PMD2 .................................................................18
RD3/AD3/PMD3 .........................................................26
RD3/PMD3 .................................................................18
RD4/AD4/PMD4/SDO2 ..............................................26
RD4/PMD4/SDO2 ......................................................18
RD5/AD5/PMD5/SDI2/SDA2 .....................................26
RD5/PMD5/SDI2/SDA2 .............................................18
RD6/AD6/PMD6/SCK2/SCL2 ....................................26
RD6/PMD6/SCK2/SCL2 ............................................18
RD7/AD7/PMD7/SS2 .................................................26
RD7/PMD7/SS2 .........................................................18
RE0/AD8/PMRD/P2D ................................................27
RE0/PMRD/P2D ........................................................19
RE1/AD9/PMWR/P2C ................................................27
RE1/PMWR/P2C ........................................................19
RE2/AD10/PMBE/P2B ...............................................27
RE2/PMBE/P2B .........................................................19
RE3/AD11/PMA13/P3C/REFO ..................................27
RE3/PMA13/P3C/REFO ............................................19
RE4/AD12/PMA12/P3B .............................................27
RE4/PMA12/P3B .......................................................19
RE5/AD13/PMA11/P1C .............................................27
RE5/PMA11/P1C .......................................................19
RE6/AD14/PMA10/P1B .............................................27
RE6/PMA10/P1B .......................................................19
RE7/AD15/PMA9/ECCP2/P2A .................................. 27
RE7/PMA9/ECCP2/P2A ............................................ 19
RF1/AN6/C2OUT ................................................. 20, 28
RF2/PMA5/AN7/C1OUT ...................................... 20, 28
RF3/AN8/C2INB .................................................. 20, 28
RF4/AN9/C2INA .................................................. 20, 28
RF5/AN10/C1INB/CVREF ........................................... 20
RF5/PMD2/AN10/C1INB/CVREF ................................ 28
RF6/AN11/C1INA ...................................................... 20
RF6/PMD1/AN11/C1INA ........................................... 28
RF7/PMD0/SS1 ......................................................... 28
RF7/SS1 .................................................................... 20
RG0/PMA8/ECCP3/P3A ...................................... 21, 29
RG1/PMA7/TX2/CK2 ........................................... 21, 29
RG2/PMA6/RX2/DT2 ........................................... 21, 29
RG3/PMCS1/CCP4/P3D ..................................... 21, 29
RG4/PMCS2/CCP5/P1D ..................................... 21, 29
RH0/A16 .................................................................... 30
RH1/A17 .................................................................... 30
RH2/A18/PMD7 ......................................................... 30
RH3/A19/PMD6 ......................................................... 30
RH4/PMD3/AN12/P3C/C2INC ................................... 30
RH5/PMBE/AN13/P3B/C2IND ................................... 30
RH6/PMRD/AN14/P1C/C1INC .................................. 30
RH7/PMWR/AN15/P1B ............................................. 30
RJ0/ALE .................................................................... 31
RJ1/OE ...................................................................... 31
RJ2/WRL ................................................................... 31
RJ3/WRH ................................................................... 31
RJ4/BA0 .................................................................... 31
RJ5/CE ...................................................................... 31
RJ6/LB ....................................................................... 31
RJ7/UB ...................................................................... 31
VDD ............................................................................ 21
VDD ............................................................................ 31
VDDCORE/VCAP ..................................................... 21, 31
VSS ............................................................................ 21
VSS ............................................................................ 31
Pinout I/O Descriptions
PIC18F6XJ1X (64-TQFP) .......................................... 14
PIC18F8XJ1X (80-TQFP) .......................................... 22
PIR Registers ................................................................... 118
PLL .................................................................................... 38
HSPLL and ECPLL Oscillator Modes ........................ 38
Use with INTOSC ...................................................... 38
POP ................................................................................. 360
POR. See Power-on Reset.
PORTA
Associated Registers ............................................... 134
LATA Register ......................................................... 132
PORTA Register ...................................................... 132
TRISA Register ........................................................ 132
PORTB
Associated Registers ............................................... 136
LATB Register ......................................................... 134
PORTB Register ...................................................... 134
RB7:RB4 Interrupt-on-Change Flag (RBIF Bit) ........ 134
TRISB Register ........................................................ 134
PORTC
Associated Registers ............................................... 138
LATC Register ......................................................... 136
PORTC Register ...................................................... 136
RC3/SCKx/SCLx Pin ............................................... 241
TRISC Register ........................................................ 136
PORTD
DS39778D-page 440
© 2009 Microchip Technology Inc.
PIC18F87J11 FAMILY
Associated Registers ............................................... 140
LATD Register ......................................................... 138
PORTD Register ...................................................... 138
TRISD Register ........................................................ 138
PCLATH and PCLATU Registers .............................. 67
Program Memory
ALU
Status ................................................................ 82
Extended Instruction Set ........................................... 86
Flash Configuration Words ........................................ 64
Hard Memory Vectors ................................................ 64
Instructions ................................................................ 71
Two-Word .......................................................... 71
Interrupt Vector .......................................................... 64
Look-up Tables .......................................................... 69
Memory Maps ............................................................ 63
Hard Vectors and Configuration Words ............. 64
Modes ................................................................ 66
Modes ........................................................................ 65
Extended Microcontroller ................................... 65
Extended Microcontroller (Address Shifting) ..... 66
Memory Access (table) ...................................... 66
Microcontroller ................................................... 65
Reset Vector .............................................................. 64
Program Verification and Code Protection ...................... 329
Programming, Device Instructions ................................... 331
Pull-up Configuration ....................................................... 130
Pulse-Width Modulation. See PWM (CCP Module) and PWM
(ECCP Module).
PORTE
Associated Registers ............................................... 143
LATE Register .......................................................... 141
PORTE Register ...................................................... 141
TRISE Register ........................................................ 141
PORTF
Associated Registers ............................................... 146
LATF Register .......................................................... 144
PORTF Register ...................................................... 144
TRISF Register ........................................................ 144
PORTG
Associated Registers ............................................... 148
LATG Register ......................................................... 146
PORTG Register ...................................................... 146
TRISG Register ........................................................ 146
PORTH
Associated Registers ............................................... 150
LATH Register ......................................................... 148
PORTH Register ...................................................... 148
TRISH Register ........................................................ 148
PORTJ
Associated Registers ............................................... 152
LATJ Register .......................................................... 151
PORTJ Register ....................................................... 151
TRISJ Register ......................................................... 151
Power-Managed Modes ..................................................... 43
and EUSART Operation ........................................... 275
and SPI Operation ................................................... 231
Clock Sources ............................................................ 43
Clock Transitions and Status Indicators ..................... 44
Entering ...................................................................... 43
Exiting Idle and Sleep Modes .................................... 49
By Interrupt ........................................................ 49
By Reset ............................................................ 49
By WDT Time-out .............................................. 49
Without an Oscillator Start-up Delay .................. 49
Idle Modes ................................................................. 47
PRI_IDLE ........................................................... 48
RC_IDLE ............................................................ 49
SEC_IDLE ......................................................... 48
Multiple Sleep Commands ......................................... 44
Run Modes ................................................................. 44
PRI_RUN ........................................................... 44
RC_RUN ............................................................ 46
SEC_RUN .......................................................... 44
Selecting .................................................................... 43
Sleep Mode ................................................................ 47
OSC1 and OSC2 Pin States .............................. 42
Summary (table) ........................................................ 43
Power-on Reset (POR) ...................................................... 53
Power-up Delays ................................................................ 42
Power-up Timer (PWRT) ............................................. 42, 54
Time-out Sequence .................................................... 54
Prescaler
PUSH ............................................................................... 360
PUSH and POP Instructions .............................................. 68
PUSHL ............................................................................. 376
PWM (CCP Module)
Associated Registers ............................................... 204
Duty Cycle ............................................................... 202
Example Frequencies/Resolutions .......................... 203
Operation Setup ...................................................... 203
Period ...................................................................... 202
PR2/PR4 Registers ................................................. 202
TMR2 (TMR4) to PR2 (PR4) Match ........................ 202
TMR2 to PR2 Match ................................................ 210
TMR4 to PR4 Match ................................................ 195
PWM (ECCP Module) ...................................................... 210
CCPR1H:CCPR1L Registers .................................. 210
Direction Change in Full-Bridge Output Mode ......... 215
Duty Cycle ............................................................... 211
Effects of a Reset .................................................... 220
Enhanced PWM Auto-Shutdown ............................. 217
Example Frequencies/Resolutions .......................... 211
Full-Bridge Mode ..................................................... 214
Full-Bridge Output Application Example .................. 215
Half-Bridge Mode ..................................................... 213
Half-Bridge Output Mode Applications Example ..... 213
Output Configurations .............................................. 211
Output Relationships (Active-High) ......................... 212
Output Relationships (Active-Low) .......................... 212
Period ...................................................................... 210
Programmable Dead-Band Delay ............................ 217
Setup for PWM Operation ....................................... 220
Start-up Considerations ........................................... 219
Q
Q Clock .................................................................... 203, 211
Timer2 ...................................................................... 211
Prescaler, Timer0 ............................................................. 181
Prescaler, Timer2 (Timer4) .............................................. 203
PRI_IDLE Mode ................................................................. 48
PRI_RUN Mode ................................................................. 44
Program Counter ............................................................... 67
PCL, PCH and PCU Registers ................................... 67
R
RAM. See Data Memory.
RC_IDLE Mode .................................................................. 49
RC_RUN Mode .................................................................. 46
RCALL ............................................................................. 361
RCON Register
© 2009 Microchip Technology Inc.
DS39778D-page 441
PIC18F87J11 FAMILY
Bit Status During Initialization ....................................56
Reader Response ............................................................434
Reference Clock Output .....................................................40
Register File .......................................................................74
Register File Summary ................................................. 77–81
Registers
STATUS .................................................................... 82
STKPTR (Stack Pointer) ............................................ 68
T0CON (Timer0 Control) ......................................... 179
T1CON (Timer1 Control) ......................................... 183
T2CON (Timer2 Control) ......................................... 189
T3CON (Timer3 Control) ......................................... 191
T4CON (Timer4 Control) ......................................... 195
TXSTAx (Transmit Status and Control) ................... 272
WDTCON (Watchdog Timer Control) ................ 76, 324
RESET ............................................................................. 361
Reset ................................................................................. 51
Brown-out Reset (BOR) ............................................. 51
Configuration Mismatch (CM) .................................... 51
MCLR Reset, During Power-Managed Modes .......... 51
MCLR Reset, Normal Operation ................................ 51
Power-on Reset (POR) .............................................. 51
RESET Instruction ..................................................... 51
Stack Full Reset ......................................................... 51
Stack Underflow Reset .............................................. 51
Watchdog Timer (WDT) Reset .................................. 51
Resets .............................................................................. 315
Brown-out Reset (BOR) ........................................... 315
Oscillator Start-up Timer (OST) ............................... 315
Power-on Reset (POR) ............................................ 315
Power-up Timer (PWRT) ......................................... 315
RETFIE ............................................................................ 362
RETLW ............................................................................ 362
RETURN .......................................................................... 363
Revision History ............................................................... 431
RLCF ............................................................................... 363
RLNCF ............................................................................. 364
RRCF ............................................................................... 364
RRNCF ............................................................................ 365
ADCON0 (A/D Control 0) .........................................293
ADCON0 (A/D Control 1) .........................................294
ANCON0 (A/D Port Configuration 2) ........................295
ANCON1 (A/D Port Configuration 1) ........................295
BAUDCONx (Baud Rate Control) ............................274
CCPxCON (Capture/Compare/PWM Control) .........197
CCPxCON (ECCPx Control) ....................................205
CMSTAT (Comparator Output Status) .....................305
CMxCON (Comparatorx Control) .............................304
CONFIG1H (Configuration 1 High) ..........................317
CONFIG1L (Configuration 1 Low) ............................317
CONFIG2H (Configuration 2 High) ..........................319
CONFIG3H (Configuration 3 High) ..........................321
CONFIG3L (Configuration 3 Low) ......................65, 320
CVRCON (Comparator Voltage Reference Control) 312
DEVID1 (Device ID 1) ..............................................322
DEVID2 (Device ID 2) ..............................................322
ECCPxAS (ECCPx Auto-Shutdown Control) ...........218
ECCPxDEL (ECCPx PWM Delay) ...........................218
EECON1 (EEPROM Control 1) ..................................91
INTCON (Interrupt Control) ......................................115
INTCON2 (Interrupt Control 2) .................................116
INTCON3 (Interrupt Control 3) .................................117
IPR1 (Peripheral Interrupt Priority 1) ........................124
IPR2 (Peripheral Interrupt Priority 2) ........................125
IPR3 (Peripheral Interrupt Priority 3) ........................126
MEMCON (External Memory Bus Control) ..............100
ODCON1 (Peripheral Open-Drain Control 1) ...........131
ODCON2 (Peripheral Open-Drain Control 2) ...........131
ODCON3 (Peripheral Open-Drain Control 3) ...........131
OSCCON (Oscillator Control) ....................................34
OSCTUNE (Oscillator Tuning) ...................................35
PADCFG1 (I/O Pad Configuration Control) .............132
PIE1 (Peripheral Interrupt Enable 1) ........................121
PIE2 (Peripheral Interrupt Enable 2) ........................122
PIE3 (Peripheral Interrupt Enable 3) ........................123
PIR1 (Peripheral Interrupt Request (Flag) 1) ...........118
PIR2 (Peripheral Interrupt Request (Flag) 2) ...........119
PIR3 (Peripheral Interrupt Request (Flag) 3) ...........120
PMADDRH (Parallel Port Address High Byte, Master
Mode Only) ......................................................160
PMCONH (Parallel Port Control High Byte) .............154
PMCONL (Parallel Port Control Low Byte) ..............155
PMEH (Parallel Port Enable High Byte) ...................157
PMEL (Parallel Port Enable Low Byte) ....................158
PMMODEH (Parallel Port Mode High Byte) .............156
PMMODEL (Parallel Port Mode Low Byte) ..............157
PMSTAT (Parallel Port Status High Byte) ................158
PMSTAT (Parallel Port Status Low Byte) ................159
RCON (Reset Control) ....................................... 52, 127
RCSTAx (Receive Status and Control) ....................273
REFOCON (Reference Oscillator Control) .................41
S
SCKx ................................................................................ 223
SDIx ................................................................................. 223
SDOx ............................................................................... 223
SEC_IDLE Mode ............................................................... 48
SEC_RUN Mode ................................................................ 44
Serial Clock, SCKx .......................................................... 223
Serial Data In (SDIx) ........................................................ 223
Serial Data Out (SDOx) ................................................... 223
Serial Peripheral Interface. See SPI Mode.
SETF ................................................................................ 365
Slave Select (SSx) ........................................................... 223
SLEEP ............................................................................. 366
Software Simulator (MPLAB SIM) ................................... 382
Special Event Trigger. See Compare (ECCP Module).
Special Features of the CPU ........................................... 315
Special Function Registers
Shared Registers ....................................................... 76
SPI Mode (MSSP) ........................................................... 223
Associated Registers ............................................... 232
Bus Mode Compatibility ........................................... 231
Clock Speed, Interactions ........................................ 231
Effects of a Reset .................................................... 231
Enabling SPI I/O ...................................................... 227
Master Mode ............................................................ 228
Master/Slave Connection ......................................... 227
Operation ................................................................. 226
Operation in Power-Managed Modes ...................... 231
Serial Clock .............................................................. 223
Serial Data In ........................................................... 223
Serial Data Out ........................................................ 223
Slave Mode .............................................................. 229
2
SSPCON2 (MSSPx Control 2, I C Master Mode) ....236
2
SSPCON2 (MSSPx Control 2, I C Slave Mode) ......237
2
SSPxCON1 (MSSPx Control 1, I C Mode) ..............235
SSPxCON1 (MSSPx Control 1, SPI Mode) .............225
2
SSPxMSK (I C Slave Address Mask) ......................237
2
SSPxSTAT (MSSPx Status, I C Mode) ...................234
SSPxSTAT (MSSPx Status, SPI Mode) ..................224
DS39778D-page 442
© 2009 Microchip Technology Inc.
PIC18F87J11 FAMILY
Slave Select ............................................................. 223
Slave Select Synchronization .................................. 229
SPI Clock ................................................................. 228
SSPxBUF Register .................................................. 228
SSPxSR Register ..................................................... 228
Typical Connection .................................................. 227
SSPOV ............................................................................. 259
SSPOV Status Flag ......................................................... 259
SSPxSTAT Register
TMR3H Register ...................................................... 191
TMR3L Register ...................................................... 191
Timer4 ............................................................................. 195
Associated Registers ............................................... 196
Operation ................................................................. 195
Output ...................................................................... 196
Postscaler. See Postscaler, Timer4.
PR4 Register ........................................................... 195
Prescaler. See Prescaler, Timer4.
R/W Bit ............................................................. 238, 241
SSx .................................................................................. 223
Stack Full/Underflow Resets .............................................. 69
SUBFSR .......................................................................... 377
SUBFWB .......................................................................... 366
SUBLW ............................................................................ 367
SUBULNK ........................................................................ 377
SUBWF ............................................................................ 367
SUBWFB .......................................................................... 368
SWAPF ............................................................................ 368
TMR4 Register ........................................................ 195
TMR4 to PR4 Match Interrupt .......................... 195, 196
Timing Diagrams
A/D Conversion ....................................................... 422
Asynchronous Reception ......................................... 284
Asynchronous Transmission ................................... 282
Asynchronous Transmission (Back to Back) ........... 282
Automatic Baud Rate Calculation ............................ 280
Auto-Wake-up Bit (WUE) During Normal Operation 285
Auto-Wake-up Bit (WUE) During Sleep ................... 285
Baud Rate Generator with Clock Arbitration ............ 256
BRG Overflow Sequence ........................................ 280
BRG Reset Due to SDAx Arbitration During Start Condi-
tion ................................................................... 266
Bus Collision During a Repeated Start Condition (Case
1) ..................................................................... 267
Bus Collision During a Repeated Start Condition (Case
2) ..................................................................... 268
Bus Collision During a Start Condition (SCLx = 0) .. 266
Bus Collision During a Stop Condition (Case 1) ...... 269
Bus Collision During a Stop Condition (Case 2) ...... 269
Bus Collision During Start Condition (SDAx Only) .. 265
Bus Collision for Transmit and Acknowledge .......... 264
Capture/Compare/PWM (Including ECCP Modules) 412
CLKO and I/O .......................................................... 404
Clock Synchronization ............................................. 249
Clock/Instruction Cycle .............................................. 70
EUSART Synchronous Receive (Master/Slave) ...... 421
EUSART Synchronous Transmission (Master/Slave) ...
421
T
Table Pointer Operations (table) ........................................ 92
Table Reads/Table Writes ................................................. 69
TBLRD ............................................................................. 369
TBLWT ............................................................................. 370
Timer0 .............................................................................. 179
Associated Registers ............................................... 181
Operation ................................................................. 180
Overflow Interrupt .................................................... 181
Prescaler .................................................................. 181
Switching Assignment ...................................... 181
Prescaler Assignment (PSA Bit) .............................. 181
Prescaler Select (T0PS2:T0PS0 Bits) ..................... 181
Prescaler. See Prescaler, Timer0.
Reads and Writes in 16-Bit Mode ............................ 180
Source Edge Select (T0SE Bit) ................................ 180
Source Select (T0CS Bit) ......................................... 180
Timer1 .............................................................................. 183
16-Bit Read/Write Mode ........................................... 185
Associated Registers ............................................... 188
Considerations in Asynchronous Counter Mode ...... 187
Interrupt .................................................................... 186
Operation ................................................................. 184
Oscillator .......................................................... 183, 185
Layout Considerations ..................................... 185
Oscillator, as Secondary Clock .................................. 35
Resetting, Using the ECCPx Special Event Trigger 186
Special Event Trigger (ECCP) ................................. 209
TMR1H Register ...................................................... 183
TMR1L Register ....................................................... 183
Use as a Clock Source ............................................ 185
Use as a Real-Time Clock ....................................... 186
Timer2 .............................................................................. 189
Associated Registers ............................................... 190
Interrupt .................................................................... 190
Operation ................................................................. 189
Output ...................................................................... 190
PR2 Register ............................................................ 210
TMR2 to PR2 Match Interrupt .................................. 210
Timer3 .............................................................................. 191
16-Bit Read/Write Mode ........................................... 193
Associated Registers ............................................... 193
Operation ................................................................. 192
Oscillator .......................................................... 191, 193
Overflow Interrupt ............................................ 191, 193
Special Event Trigger (ECCPx) ............................... 193
Example SPI Master Mode (CKE = 0) ..................... 413
Example SPI Master Mode (CKE = 1) ..................... 414
Example SPI Slave Mode (CKE = 0) ....................... 415
Example SPI Slave Mode (CKE = 1) ....................... 416
External Clock (All Modes Except PLL) ................... 402
External Memory Bus for Sleep (Extended Microcon-
troller Mode) ............................................ 106, 108
External Memory Bus for TBLRD (Extended Microcon-
troller Mode) ............................................ 106, 108
Fail-Safe Clock Monitor ........................................... 328
First Start Bit Timing ................................................ 257
Full-Bridge PWM Output .......................................... 214
Half-Bridge PWM Output ......................................... 213
2
I C Acknowledge Sequence .................................... 262
2
I C Bus Data ............................................................ 417
2
I C Bus Start/Stop Bits ............................................ 417
2
I C Master Mode (7 or 10-Bit Transmission) ........... 260
2
I C Master Mode (7-Bit Reception) ......................... 261
2
I C Slave Mode (10-Bit Reception, SEN = 0, ADMSK =
01001) ............................................................. 245
I C Slave Mode (10-Bit Reception, SEN = 0) .......... 246
I C Slave Mode (10-Bit Reception, SEN = 1) .......... 251
I C Slave Mode (10-Bit Transmission) .................... 247
2
2
2
2
I C Slave Mode (7-bit Reception, SEN = 0, ADMSK =
01011) ............................................................. 243
I C Slave Mode (7-Bit Reception, SEN = 0) ............ 242
2
© 2009 Microchip Technology Inc.
DS39778D-page 443
PIC18F87J11 FAMILY
2
I C Slave Mode (7-Bit Reception, SEN = 1) ............250
Address ........................................................... 174
Write, 16-Bit Muliplexed Data, Partially Multiplexed Ad-
dress ................................................................ 173
Write, 8-Bit Data, Demultiplexed Address ............... 172
Write, 8-Bit Data, Fully Multiplexed 16-Bit Address . 172
Write, 8-Bit Data, Partially Multiplexed Address ...... 170
Write, 8-Bit Data, Partially Multiplexed Address, Enable
Strobe .............................................................. 171
Write, 8-Bit Data, Wait States Enabled, Partially Multi-
plexed Address ................................................ 170
Timing Diagrams and Specifications
2
I C Slave Mode (7-Bit Transmission) .......................244
2
I C Slave Mode General Call Address Sequence (7 or
10-Bit Addressing Mode) .................................252
2
I C Stop Condition Receive or Transmit Mode ........263
2
MSSP I C Bus Data .................................................419
MSSP I C Bus Start/Stop Bits .................................419
2
Parallel Master Port Read ........................................410
Parallel Master Port Write ........................................411
Parallel Slave Port ...................................................409
Parallel Slave Port Read .................................. 162, 165
Parallel Slave Port Write .................................. 162, 165
Program Memory Read ............................................405
Program Memory Write ............................................406
PWM Auto-Shutdown (P1RSEN = 0, Auto-Restart Dis-
abled) ...............................................................219
PWM Auto-Shutdown (P1RSEN = 1, Auto-Restart En-
abled) ...............................................................219
PWM Direction Change ...........................................216
PWM Direction Change at Near 100% Duty Cycle ..216
PWM Output ............................................................202
Read and Write, 8-Bit Data, Demultiplexed Address 169
Read, 16-Bit Data, Demultiplexed Address .............172
Read, 16-Bit Muliplexed Data, Fully Multiplexed 16-Bit
Address ............................................................174
Read, 16-Bit Multiplexed Data, Partially Multiplexed Ad-
dress ................................................................173
Read, 8-Bit Data, Fully Multiplexed 16-Bit Address .171
Read, 8-Bit Data, Partially Multiplexed Address ......169
Read, 8-Bit Data, Partially Multiplexed Address, Enable
Strobe ..............................................................171
Read, 8-Bit Data, Wait States Enabled, Partially Multi-
plexed Address ................................................170
Repeated Start Condition .........................................258
Reset, Watchdog Timer (WDT), Oscillator Start-up Timer
(OST) and Power-up Timer (PWRT) ................407
Send Break Character Sequence ............................286
Slave Synchronization .............................................229
Slow Rise Time (MCLR Tied to VDD, VDD Rise > TPWRT)
............................................................................55
SPI Mode (Master Mode) .........................................228
SPI Mode (Slave Mode, CKE = 0) ...........................230
SPI Mode (Slave Mode, CKE = 1) ...........................230
Synchronous Reception (Master Mode, SREN) ......289
Synchronous Transmission ......................................287
Synchronous Transmission (Through TXEN) ..........288
Time-out Sequence on Power-up (MCLR Not Tied to
VDD), Case 1 ......................................................54
Time-out Sequence on Power-up (MCLR Not Tied to
VDD), Case 2 ......................................................55
Time-out Sequence on Power-up (MCLR Tied to VDD,
VDD Rise < TPWRT) ............................................54
Timer0 and Timer1 External Clock ..........................408
Transition for Entry to Idle Mode ................................48
Transition for Entry to SEC_RUN Mode ....................45
Transition for Entry to Sleep Mode ............................47
Transition for Two-Speed Start-up (INTRC to HSPLL) ..
326
Capture/Compare/PWM Requirements (Including ECCP
Modules) .......................................................... 412
CLKO and I/O Requirements ........................... 404, 405
EUSART Synchronous Receive Requirements ....... 421
EUSART Synchronous Transmission Requirements ....
421
Example SPI Mode Requirements (Master Mode, CKE =
0) ..................................................................... 413
Example SPI Mode Requirements (Master Mode, CKE =
1) ..................................................................... 414
Example SPI Mode Requirements (Slave Mode, CKE =
0) ..................................................................... 415
Example SPI Slave Mode Requirements (CKE = 1) 416
External Clock Requirements .................................. 402
2
I C Bus Data Requirements (Slave Mode) .............. 418
2
I C Bus Start/Stop Bits Requirements (Slave Mode) .....
417
Internal RC Accuracy (INTOSC, INTRC Sources) ... 403
2
MSSP I C Bus Data Requirements ......................... 420
2
MSSP I C Bus Start/Stop Bits Requirements .......... 419
Parallel Master Port Read Requirements ................ 410
Parallel Master Port Write ........................................ 411
Parallel Slave Port Requirements ............................ 409
PLL Clock ................................................................ 403
Program Memory Write Requirements .................... 406
Reset, Watchdog Timer (WDT), Oscillator Start-up Timer
(OST), Power-up Timer (PWRT) and Brown-out
Reset ............................................................... 407
Timer0 and Timer1 External Clock Requirements ... 408
TSTFSZ ........................................................................... 371
Two-Speed Start-up ................................................. 315, 326
Two-Word Instructions
Example Cases .......................................................... 71
TXSTAx Register
BRGH Bit ................................................................. 275
V
VDDCORE/VCAP Pin .......................................................... 325
Voltage Reference Specifications .................................... 399
Voltage Regulator (On-Chip) ........................................... 325
Operation in Sleep Mode ......................................... 326
Power-up Requirements .......................................... 326
W
Watchdog Timer (WDT) ........................................... 315, 323
Associated Registers ............................................... 324
Control Register ....................................................... 323
During Oscillator Failure .......................................... 327
Programming Considerations .................................. 323
WCOL ...................................................... 257, 258, 259, 262
WCOL Status Flag ................................... 257, 258, 259, 262
WWW Address ................................................................ 433
WWW, On-Line Support ...................................................... 7
Transition for Wake From Idle to Run Mode ..............48
Transition for Wake From Sleep (HSPLL) .................47
Transition From RC_RUN Mode to PRI_RUN Mode .46
Transition From SEC_RUN Mode to PRI_RUN Mode
(HSPLL) .............................................................45
Transition to RC_RUN Mode .....................................46
Write, 16-Bit Muliplexed Data, Fully Multiplexed 16-Bit
DS39778D-page 444
© 2009 Microchip Technology Inc.
PIC18F87J11 FAMILY
X
XORLW ............................................................................ 371
XORWF ............................................................................ 372
© 2009 Microchip Technology Inc.
DS39778D-page 445
PIC18F87J11 FAMILY
NOTES:
DS39778D-page 446
© 2009 Microchip Technology Inc.
PIC18F87J11 FAMILY
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
PART NO.
Device
X
/XX
XXX
Examples:
Temperature
Range
Package
Pattern
a)
b)
PIC18F87J11-I/PT 301 = Industrial temp.,
TQFP package, QTP pattern #301.
PIC18F66J16T-I/PT = Tape and reel, Industrial
temp., TQFP package.
Device
PIC18F66J11/66J16/67J11(1)
PIC18F86J11/86J16/87J11(1)
,
,
PIC18F66J11/66J16/67J11T(2)
PIC18F86J11/86J16/87J11T(2)
,
Temperature Range
Package
I
= -40°C to +85°C (Industrial)
PT = TQFP (Thin Quad Flatpack)
Pattern
QTP, SQTP, Code or Special Requirements
(blank otherwise)
Note 1:
2:
F
T
=
=
Standard Voltage Range
in tape and reel
© 2009 Microchip Technology Inc.
DS39778D-page 447
WORLDWIDE SALES AND SERVICE
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Tel: 49-89-627-144-0
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Tel: 86-10-8528-2100
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Tel: 39-0331-742611
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Fax: 82-2-558-5932 or
82-2-558-5934
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Tel: 34-91-708-08-90
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Fax: 972-818-2924
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Tel: 86-21-5407-5533
Fax: 86-21-5407-5066
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Fax: 63-2-634-9069
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China - Shenyang
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Fax: 86-24-2334-2393
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Tel: 886-3-6578-300
Fax: 886-3-6578-370
Kokomo
Kokomo, IN
Tel: 765-864-8360
Fax: 765-864-8387
China - Wuhan
Tel: 86-27-5980-5300
Fax: 86-27-5980-5118
Taiwan - Kaohsiung
Tel: 886-7-536-4818
Fax: 886-7-536-4803
Los Angeles
Mission Viejo, CA
Tel: 949-462-9523
Fax: 949-462-9608
China - Xiamen
Tel: 86-592-2388138
Fax: 86-592-2388130
Taiwan - Taipei
Tel: 886-2-2500-6610
Fax: 886-2-2508-0102
Santa Clara
China - Xian
Tel: 86-29-8833-7252
Fax: 86-29-8833-7256
Thailand - Bangkok
Tel: 66-2-694-1351
Fax: 66-2-694-1350
Santa Clara, CA
Tel: 408-961-6444
Fax: 408-961-6445
China - Zhuhai
Tel: 86-756-3210040
Fax: 86-756-3210049
Toronto
Mississauga, Ontario,
Canada
Tel: 905-673-0699
Fax: 905-673-6509
03/26/09
DS39778D-page 448
© 2009 Microchip Technology Inc.
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