PIC18F83J11 [MICROCHIP]
General Purpose PIC18 J-series Microcontroller providing 10 MIPS performance at 3V with 8MHz inter;
| 型号： | PIC18F83J11 |
| 厂家： | 
MICROCHIP |
| 描述： | General Purpose PIC18 J-series Microcontroller providing 10 MIPS performance at 3V with 8MHz inter 控制器 微控制器 微控制器和处理器 |
| 文件： | 总396页 (文件大小：6471K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PIC18F85J11 Family
Data Sheet
64/80-Pin
High-Performance Microcontrollers
with nanoWatt Technology
© 2007 Microchip Technology Inc.
Preliminary
DS39774C
Note the following details of the code protection feature on Microchip devices:
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•
•
Microchip is willing to work with the customer who is concerned about the integrity of their code.
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Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
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Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
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MICROCHIP MAKES NO REPRESENTATIONS OR
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OTHERWISE, RELATED TO THE INFORMATION,
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Trademarks
The Microchip name and logo, the Microchip logo, Accuron,
dsPIC, KEELOQ, KEELOQ logo, microID, MPLAB, PIC,
PICmicro, PICSTART, PRO MATE, PowerSmart, rfPIC, and
SmartShunt are registered trademarks of Microchip
Technology Incorporated in the U.S.A. and other countries.
AmpLab, FilterLab, Linear Active Thermistor, Migratable
Memory, MXDEV, MXLAB, PS logo, SEEVAL, SmartSensor
and The Embedded Control Solutions Company are
registered trademarks of Microchip Technology Incorporated
in the U.S.A.
Analog-for-the-Digital Age, Application Maestro, CodeGuard,
dsPICDEM, dsPICDEM.net, dsPICworks, ECAN,
ECONOMONITOR, FanSense, FlexROM, fuzzyLAB,
In-Circuit Serial Programming, ICSP, ICEPIC, Mindi, MiWi,
MPASM, MPLAB Certified logo, MPLIB, MPLINK, PICkit,
PICDEM, PICDEM.net, PICLAB, PICtail, PowerCal,
PowerInfo, PowerMate, PowerTool, REAL ICE, rfLAB,
rfPICDEM, Select Mode, Smart Serial, SmartTel, Total
Endurance, UNI/O, WiperLock and ZENA are trademarks of
Microchip Technology Incorporated in the U.S.A. and other
countries.
SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.
All other trademarks mentioned herein are property of their
respective companies.
© 2007, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.
Printed on recycled paper.
Microchip received ISO/TS-16949:2002 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona, Gresham, Oregon and Mountain View, California. The
Company’s quality system processes and procedures are for its PIC®
MCUs and dsPIC® DSCs, KEELOQ® code hopping devices, Serial
EEPROMs, microperipherals, nonvolatile memory and analog
products. In addition, Microchip’s quality system for the design and
manufacture of development systems is ISO 9001:2000 certified.
DS39774C-page ii
Preliminary
© 2007 Microchip Technology Inc.
PIC18F85J11 FAMILY
64/80-Pin High-Performance Microcontrollers
with nanoWatt Technology
Peripheral Highlights:
Low-Power Features:
• High-Current Sink/Source 25 mA/25 mA
(PORTB and PORTC)
• Up to Four External Interrupts
• Power-Managed modes: Run, Idle, Sleep
• Run Current Down to 9 µA, Typical
• Idle Current Down to 2.5 µA, Typical
• Sleep Current Down to 100 nA, Typical
• Fast INTOSC Start-up from Sleep
• Two-Speed Oscillator Start-up Reduces Crystal
Stabilization Wait Time
• Four 8-Bit/16-Bit Timer/Counter modules
• Real-Time Clock (RTC) Software module:
- Configurable 24-hour clock, calendar,
automatic 100-year or 12800-year day of
week calculator using Timer1
• Two Capture/Compare/PWM (CCP) modules:
- Capture is 16-bit, max. resolution 6.25 ns (TCY/16)
- Compare is 16-bit, max. resolution 100 ns (TCY)
- PWM output: PWM resolution is up to 10-bit
• Master Synchronous Serial Port (MSSP) module with
Two Modes of Operation:
Flexible Oscillator Structure:
• Two Crystal modes, 4-25 MHz
• Two External Clock modes, up to 40 MHz
• 4x Phase Lock Loop (PLL)
• Internal Oscillator Block:
- 8 user-selectable frequencies from 31.25 kHz
to 8 MHz
• Secondary Oscillator using Timer1 @ 32 kHz
• Fail-Safe Clock Monitor:
- Allows for safe shutdown if peripheral clock fails
- 3-wire/4-wire SPI (supports all 4 SPI modes)
- I2C™ Master and Slave mode
• One Addressable USART module
• One Enhanced Addressable USART module:
- Supports LIN 1.2
- Auto-wake-up on Start bit and Break character
- Auto-Baud Detect (ABD)
• 10-Bit, up to 12-Channel A/D Converter:
- Auto-acquisition
- Conversion available during Sleep
• Two Analog Comparators
Special Microcontroller Features:
• 1,000 Erase/Write Cycle Flash
Program Memory Typical
• Flash Retention 20 Years Minimum
• Self-Programmable under Software Control
• Priority Levels for Interrupts
• 8 x 8 Single-Cycle Hardware Multiplier
• Extended Watchdog Timer (WDT):
- Programmable period from 4 ms to 131s
• In-Circuit Serial Programming™ (ICSP™) via two pins
• In-Circuit Debug via two pins
• Operating Voltage Range: 2.0V to 3.6V
• 5.5V Tolerant Input (digital pins only)
• Selectable Open-Drain Configuration for Serial
Communication and CCP pins for Driving Outputs up
to 5V
• Programmable Reference Voltage for Comparators
External Memory Bus (PIC18F8XJ11 only):
• Address Capability of up to 2 Mbytes
• 8-Bit or 16-Bit Interface
• 12-Bit, 16-Bit and 20-Bit Addressing modes
• On-Chip 2.5V Regulator
Program Memory
SRAMData
MSSP
10-Bit
A/D (ch)
Device
Memory
(bytes)
I/O
CCP
PSP
Flash # Single-Word
(bytes) Instructions
Master
SPI
2
I C™
PIC18F63J11
PIC18F64J11
PIC18F65J11
PIC18F83J11
PIC18F84J11
PIC18F85J11
8K
16K
32K
8K
4096
8192
1K
1K
2K
1K
1K
2K
52
52
52
68
68
68
1/3
1/3
1/3
1/3
1/3
1/3
2
2
2
2
2
2
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
1/1
1/1
1/1
1/1
1/1
1/1
12
12
12
12
12
12
2
2
2
2
2
2
Y
Y
Y
Y
Y
Y
N
N
N
Y
Y
Y
Y
Y
Y
Y
Y
Y
16384
4096
16K
32K
8192
16384
© 2007 Microchip Technology Inc.
Preliminary
DS39774C-page 1
PIC18F85J11 FAMILY
Pin Diagrams
64-Pin TQFP
64 63 62 61 60 59 58 57 56 55 54 53 52 51
50 49
1
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
RB0/INT0
RB1/INT1
RB2/INT2
RB3/INT3
RB4/KBI0
RE1/WR
RE0/RD
2
3
RG0
RG1/TX2/CK2
RG2/RX2/DT2
RG3
4
5
6
RB5/KBI1
7
RB6/KBI2/PGC
VSS
MCLR
PIC18F63J11
PIC18F64J11
PIC18F65J11
8
RG4
9
VSS
RA6/OSC2/CLKO
RA7/OSC1/CLKI
VDD
10
11
12
13
14
15
16
VDDCORE/VCAP
RF7/AN5/SS
RF6/AN11
RF5/AN10/CVREF
RF4/AN9
RB7/KBI3/PGD
RC5/SDO
RC4/SDI/SDA
RC3/SCK/SCL
RF3/AN8
RC2/CCP1
RF2/AN7/C1OUT
17 18 19 20 21 22 23 24 25 26 27 28
29 30 31 32
Note 1: The CCP2 pin placement depends on the CCP2MX Configuration bit setting.
DS39774C-page 2
Preliminary
© 2007 Microchip Technology Inc.
PIC18F85J11 FAMILY
Pin Diagrams (Continued)
80-Pin TQFP
80 79 78
77 76 75 74 73 72 71 70 69 68 67 66 65
64 63 62 61
RH2/A18
RH3/A19
1
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
RJ2/WRL
2
RJ3/WRH
RE1/WR/AD9
RE0/RD/AD8
RG0
3
RB0/INT0
4
RB1/INT1
5
RB2/INT2
RB3/INT3/CCP2(1)
RG1/TX2/CK2
RG2/RX2/DT2
RG3
6
7
RB4/KBI0
8
RB5/KBI1
MCLR
9
RB6/KBI2/PGC
VSS
PIC18F83J11
PIC18F84J11
PIC18F85J11
RG4
10
11
12
13
14
15
16
17
18
19
20
VSS
RA6/OSC2/CLKO
RA7/OSC1/CLKI
VDD
VDDCORE/VCAP
RF7/AN5/SS
RB7/KBI3/PGD
RC5/SDO
RF6/AN11
RF5/AN10/CVREF
RF4/AN9
RC4/SDI/SDA
RF3/AN8
RC3/SCK/SCL
RC2/CCP1
RF2/AN7/C1OUT
RH7
RJ7/UB
RJ6/LB
RH6
40
21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39
Note 1: The CCP2 pin placement depends on the settings of the CCP2MX and EMB1:EMB0 Configuration bits.
© 2007 Microchip Technology Inc.
Preliminary
DS39774C-page 3
PIC18F85J11 FAMILY
Table of Contents
1.0 Device Overview .......................................................................................................................................................................... 7
2.0 Oscillator Configurations ............................................................................................................................................................ 29
3.0 Power-Managed Modes ............................................................................................................................................................. 37
4.0 Reset.......................................................................................................................................................................................... 45
5.0 Memory Organization................................................................................................................................................................. 57
6.0 Flash Program Memory.............................................................................................................................................................. 83
7.0 External Memory Bus................................................................................................................................................................. 93
8.0 8 x 8 Hardware Multiplier.......................................................................................................................................................... 105
9.0 Interrupts .................................................................................................................................................................................. 107
10.0 I/O Ports ................................................................................................................................................................................... 123
11.0 Timer0 Module ......................................................................................................................................................................... 147
12.0 Timer1 Module ......................................................................................................................................................................... 151
13.0 Timer2 Module ......................................................................................................................................................................... 157
14.0 Timer3 Module ......................................................................................................................................................................... 159
15.0 Capture/Compare/PWM (CCP) Modules ................................................................................................................................. 163
16.0 Master Synchronous Serial Port (MSSP) Module .................................................................................................................... 173
17.0 Enhanced Universal Synchronous Asynchronous Receiver Transmitter (EUSART)............................................................... 217
18.0 Addressable Universal Synchronous Asynchronous Receiver Transmitter (AUSART) ........................................................... 237
19.0 10-bit Analog-to-Digital Converter (A/D) Module...................................................................................................................... 251
20.0 Comparator Module.................................................................................................................................................................. 261
21.0 Comparator Voltage Reference Module................................................................................................................................... 267
22.0 Special Features of the CPU.................................................................................................................................................... 271
23.0 Instruction Set Summary.......................................................................................................................................................... 285
24.0 Development Support............................................................................................................................................................... 335
25.0 Electrical Characteristics.......................................................................................................................................................... 339
26.0 DC and AC Characteristics Graphs and Tables....................................................................................................................... 373
27.0 Packaging Information.............................................................................................................................................................. 375
Appendix A: Revision History............................................................................................................................................................. 379
Appendix B: Migration Between High-End Device Families............................................................................................................... 379
Index .................................................................................................................................................................................................. 381
The Microchip Web Site..................................................................................................................................................................... 391
Customer Change Notification Service .............................................................................................................................................. 391
Customer Support.............................................................................................................................................................................. 391
Reader Response .............................................................................................................................................................................. 392
Product Identification System............................................................................................................................................................. 393
DS39774C-page 4
Preliminary
© 2007 Microchip Technology Inc.
PIC18F85J11 FAMILY
TO OUR VALUED CUSTOMERS
It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip
products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and
enhanced as new volumes and updates are introduced.
If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via
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welcome your feedback.
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You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page.
The last character of the literature number is the version number, (e.g., DS30000A is version A of document DS30000).
Errata
An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current
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To determine if an errata sheet exists for a particular device, please check with one of the following:
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When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are
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© 2007 Microchip Technology Inc.
Preliminary
DS39774C-page 5
PIC18F85J11 FAMILY
NOTES:
DS39774C-page 6
Preliminary
© 2007 Microchip Technology Inc.
PIC18F85J11 FAMILY
The internal oscillator block provides a stable reference
source that gives the family additional features for
robust operation:
1.0
DEVICE OVERVIEW
This document contains device-specific information for
the following devices:
• Fail-Safe Clock Monitor: This option constantly
monitors the main clock source against a reference
signal provided by the internal oscillator. If a clock
failure occurs, the controller is switched to the
internal oscillator, allowing for continued low-speed
operation or a safe application shutdown.
• PIC18F63J11
• PIC18F64J11
• PIC18F65J11
• PIC18F83J11
• PIC18F84J11
• PIC18F85J11
This family combines the traditional advantages of all
PIC18 microcontrollers – namely, high computational
performance and a rich feature set – while maintaining
an extremely competitive price point. These features
make the PIC18F85J11 family a logical choice for
many high-performance applications where price is a
primary consideration.
• Two-Speed Start-up: This option allows the
internal oscillator to serve as the clock source
from Power-on Reset, or wake-up from Sleep
mode, until the primary clock source is available.
1.1.3
MEMORY OPTIONS
The PIC18F85J11 family provides a range of program
memory options, from 8 Kbytes to 32 Kbytes of code
space. The Flash cells for program memory are rated
to last up to 1000 erase/write cycles. Data retention
without refresh is conservatively estimated to be
greater than 20 years.
1.1
Core Features
1.1.1
nanoWatt TECHNOLOGY
All of the devices in the PIC18F85J11 family incorporate
a range of features that can significantly reduce power
consumption during operation. Key items include:
The PIC18F85J11 family also provides plenty of room
for dynamic application data, with up to 2048 bytes of
data RAM.
• Alternate Run Modes: By clocking the controller
from the Timer1 source or the internal RC
oscillator, power consumption during code
execution can be reduced by as much as 90%.
1.1.4
EXTENDED INSTRUCTION SET
• Multiple Idle Modes: The controller can also run
with its CPU core disabled but the peripherals still
active. In these states, power consumption can be
reduced even further, to as little as 4% of normal
operation requirements.
The PIC18F85J11 family implements the optional
extension to the PIC18 instruction set, adding 8 new
instructions and an Indexed Addressing mode.
Enabled as a device configuration option, the extension
has been specifically designed to optimize re-entrant
application code originally developed in high-level
languages, such as ‘C’.
• On-the-Fly Mode Switching: The power-managed
modes are invoked by user code during operation,
allowing the user to incorporate power-saving ideas
into their application’s software design.
1.1.5
EXTERNAL MEMORY BUS
In the event that 32 Kbytes of memory are inadequate
for an application, the 80-pin members of the
PIC18F85J11 family also implement an external mem-
ory bus. This allows the controller’s internal program
counter to address a memory space of up to 2 Mbytes,
permitting a level of data access that few 8-bit devices
can claim. This allows additional memory options,
including:
1.1.2
OSCILLATOR OPTIONS AND
FEATURES
All of the devices in the PIC18F85J11 family offer six
different oscillator options, allowing users a range of
choices in developing application hardware. These
include:
• Two Crystal modes, using crystals or ceramic
resonators.
• Using combinations of on-chip and external
memory up to the 2-Mbyte limit
• Two External Clock modes, offering the option of
a divide-by-4 clock output.
• Using external Flash memory for reprogrammable
application code or large data tables
• A Phase Lock Loop (PLL) frequency multiplier,
available to the External Oscillator modes, which
allows clock speeds of up to 40 MHz.
• Using external RAM devices for storing large
amounts of variable data
• An internal oscillator block which provides an
8 MHz clock ( 2% accuracy) and an INTRC source
(approximately 31 kHz, stable over temperature
and VDD), as well as a range of six user-selectable
clock frequencies, between 125 kHz to 4 MHz, for a
total of eight clock frequencies. This option frees the
two oscillator pins for use as additional general
purpose I/O.
© 2007 Microchip Technology Inc.
Preliminary
DS39774C-page 7
PIC18F85J11 FAMILY
1.1.6
EASY MIGRATION
1.3
Details on Individual Family
Members
Regardless of the memory size, all devices share the
same rich set of peripherals, allowing for a smooth
migration path as applications grow and evolve.
Devices in the PIC18F85J11 family are available in
64-pin and 80-pin packages. Block diagrams for the
two groups are shown in Figure 1-1 and Figure 1-2.
The consistent pinout scheme used throughout the
entire family also aids in migrating to the next larger
device. This is true when moving between the 64-pin
members, between the 80-pin members or even
jumping from 64-pin to 80-pin devices.
The devices are differentiated from each other in four
ways:
1. Flash program memory (three sizes, ranging
from 8 Kbytes for PIC18FX3J11 devices to
32 Kbytes for PIC18FX5J11 devices).
The PIC18F85J11 family is also largely pin compatible
with other PIC18 general purpose families, such as the
PIC18F8720 and PIC18F8722. This allows a new
dimension to the evolution of applications, allowing
developers to select different price points within
Microchip’s PIC18 portfolio, while maintaining a similar
feature set.
2. Data RAM (1024 bytes for PIC18FX3J11 and
PIC18FX4J11 devices, 2048 bytes for
PIC18FX5J11 devices).
3. I/O ports (7 bidirectional ports on 64-pin devices,
9 bidirectional ports on 80-pin devices).
4. External Memory Bus (implemented in 80-pin
devices only).
1.2
Other Special Features
All other features for devices in this family are identical.
These are summarized in Table 1-1 and Table 1-2.
• Communications: The PIC18F85J11 family
incorporates a range of serial communication
peripherals, including an Addressable USART, a
separate Enhanced USART that supports LIN
specification 1.2, and one Master SSP (MSSP)
module capable of both SPI and I2C™ (Master and
Slave) modes of operation.
The pinouts for all devices are listed in Table 1-3 and
Table 1-4.
• CCP Modules: All devices in the family incorporate
two Capture/Compare/PWM (CCP) modules. Up to
four different time bases may be used to perform
several different operations at once.
• 10-Bit A/D Converter: This module incorporates
programmable acquisition time, allowing for a
channel to be selected and a conversion to be
initiated without waiting for a sampling period and
thus, reducing code overhead.
• Extended Watchdog Timer (WDT): This
enhanced version incorporates a 16-bit prescaler,
allowing an extended time-out range that is stable
across operating voltage and temperature. See
Section 25.0 “Electrical Characteristics” for
time-out periods.
DS39774C-page 8
Preliminary
© 2007 Microchip Technology Inc.
PIC18F85J11 FAMILY
TABLE 1-1:
DEVICE FEATURES FOR THE PIC18F6XJ11 FAMILY (64-PIN DEVICES)
Features
PIC18F63J11
PIC18F64J11
PIC18F65J11
Operating Frequency
Program Memory (Bytes)
Program Memory (Instructions)
Data Memory (Bytes)
Interrupt Sources
DC – 40 MHz
8K
16K
32K
16384
2048
4096
1024
8192
1024
27
I/O Ports
Ports A, B, C, D, E, F, G
Timers
4
2
Capture/Compare/PWM Modules
Serial Communications
Parallel Communications (PSP)
External Memory Bus
10-Bit Analog-to-Digital Module
Resets (and Delays)
MSSP, Addressable USART, Enhanced USART
Yes
No
12 Input Channels
POR, BOR, RESETInstruction, Stack Full, Stack Underflow, MCLR, WDT
(PWRT, OST)
Instruction Set
Packages
75 Instructions, 83 with Extended Instruction Set Enabled
64-Pin TQFP
TABLE 1-2:
DEVICE FEATURES FOR THE PIC18F8XJ11 FAMILY (80-PIN DEVICES)
Features
PIC18F83J11
PIC18F84J11
PIC18F85J11
Operating Frequency
Program Memory (Bytes)
Program Memory (Instructions)
Data Memory (Bytes)
Interrupt Sources
DC – 40 MHz
8K
16K
32K
16384
2048
4096
1024
8192
1024
27
I/O Ports
Ports A, B, C, D, E, F, G, H, J
Timers
4
2
Capture/Compare/PWM Modules
Serial Communications
Parallel Communications (PSP)
External Memory Bus
10-Bit Analog-to-Digital Module
Resets (and Delays)
MSSP, Addressable USART, Enhanced USART
Yes
Yes
12 Input Channels
POR, BOR, RESETInstruction, Stack Full, Stack Underflow, MCLR, WDT
(PWRT, OST)
Instruction Set
Packages
75 Instructions, 83 with Extended Instruction Set Enabled
80-Pin TQFP
© 2007 Microchip Technology Inc.
Preliminary
DS39774C-page 9
PIC18F85J11 FAMILY
FIGURE 1-1:
PIC18F6XJ11 (64-PIN) BLOCK DIAGRAM
Data Bus<8>
Table Pointer<21>
inc/dec logic
21
PORTA
RA0:RA7(1,2)
Data Latch
8
8
Data Memory
(3.9 Kbytes)
PCLATU PCLATH
Address Latch
20
PCU PCH PCL
Program Counter
12
PORTB
Data Address<12>
RB0:RB7(1)
31 Level Stack
STKPTR
4
BSR
12
FSR0
FSR1
FSR2
4
Address Latch
Access
Bank
Program Memory
(96 Kbytes)
12
Data Latch
PORTC
RC0:RC7(1)
inc/dec
logic
8
Table Latch
ROM Latch
Address
Decode
Instruction Bus <16>
PORTD
RD0:RD7(1)
IR
8
Instruction
Decode and
Control
State Machine
Control Signals
PRODH PRODL
8 x 8 Multiply
PORTE
RE0:RE7(1)
3
Timing
8
Power-up
Timer
OSC2/CLKO
OSC1/CLKI
Generation
BITOP
8
W
INTRC
Oscillator
8
Oscillator
Start-up Timer
8
8 MHz
Oscillator
PORTF
Power-on
Reset
8
8
RF1:RF7(1)
Precision
Band Gap
Reference
ALU<8>
8
Watchdog
Timer
ENVREG
BOR and
LVD(3)
Voltage
Regulator
PORTG
RG0:RG4(1)
VDDCORE/VCAP
VDD,VSS
MCLR
ADC
10-Bit
Timer0
Timer1
CCP2
Timer2
Timer3
Comparators
MSSP
CCP1
AUSART
EUSART
Note 1: See Table 1-3 for I/O port pin descriptions.
2: RA6 and RA7 are only available as digital I/O in select oscillator modes. See Section 2.0 “Oscillator Configurations” for more
information
3: Brown-out Reset and Low-Voltage Detect functions are provided when the on-board voltage regulator is enabled.
DS39774C-page 10
Preliminary
© 2007 Microchip Technology Inc.
PIC18F85J11 FAMILY
FIGURE 1-2:
PIC18F8XJ11 (80-PIN) BLOCK DIAGRAM
Data Bus<8>
PORTA
RA0:RA7(1,2)
Data Latch
Table Pointer<21>
inc/dec logic
8
8
Data Memory
(3.9 Kbytes)
PCLATU PCLATH
Address Latch
21
20
PORTB
PCU PCH PCL
Program Counter
RB0:RB7(1)
12
Data Address<12>
31 Level Stack
STKPTR
4
BSR
4
12
FSR0
FSR1
FSR2
Address Latch
PORTC
Access
Bank
Program Memory
(128 Kbytes)
RC0:RC7(1)
12
Data Latch
inc/dec
logic
8
PORTD
Table Latch
ROM Latch
RD0:RD7(1)
Address
Decode
Instruction Bus <16>
PORTE
IR
RE0:RE7(1)
AD15:AD0, A19:A16
(Multiplexed with PORTD,
PORTE and PORTH)
8
PORTF
PRODH PRODL
8 x 8 Multiply
Instruction
Decode &
Control
State Machine
Control Signals
RF1:RF7(1)
3
8
W
BITOP
8
PORTG
Timing
Generation
8
8
Power-up
Timer
OSC2/CLKO
OSC1/CLKI
RG0:RG4(1)
INTRC
Oscillator
Start-up Timer
8
8
Oscillator
8 MHz
Oscillator
ALU<8>
8
Power-on
Reset
PORTH
RH0:RH7(1)
Precision
Band Gap
Reference
Watchdog
Timer
ENVREG
BOR and
LVD(3)
Voltage
Regulator
PORTJ
RJ0:RJ7(1)
VDDCORE/VCAP
VDD,VSS
MCLR
ADC
10-Bit
Timer0
CCP1
Timer1
CCP2
Timer2
Timer3
Comparators
MSSP
AUSART
EUSART
Note 1: See Table 1-3 for I/O port pin descriptions.
2: RA6 and RA7 are only available as digital I/O in select oscillator modes. See Section 2.0 “Oscillator Configurations” for more
information
3: Brown-out Reset and Low-Voltage Detect functions are provided when the on-board voltage regulator is enabled.
© 2007 Microchip Technology Inc.
Preliminary
DS39774C-page 11
PIC18F85J11 FAMILY
TABLE 1-3:
PIC18F6XJ11 PINOUT I/O DESCRIPTIONS
Pin Number
Pin Buffer
Pin Name
Description
Type Type
TQFP
MCLR
7
I
ST
Master Clear (input) or programming voltage (input). This
pin is an active-low Reset to the device.
RA7/OSC1/CLKI
RA7
39
Oscillator crystal or external clock input.
General purpose I/O pin.
I/O
TTL
OSC1
CLKI
I
I
CMOS
CMOS
Oscillator crystal input.
External clock source input. Always associated
with pin function OSC1. (See related OSC1/CLKI,
OSC2/CLKO pins.)
RA6/OSC2/CLKO
RA6
40
Oscillator crystal or clock output.
I/O
O
TTL
—
General purpose I/O pin.
OSC2
Oscillator crystal output. Connects to crystal or
resonator in Crystal Oscillator mode.
In EC modes, OSC2 pin outputs CLKO, which has
1/4 the frequency of OSC1 and denotes the
instruction cycle rate.
CLKO
O
—
PORTA is a bidirectional I/O port.
RA0/AN0
RA0
24
23
22
I/O
I
TTL
Analog
Digital I/O.
Analog input 0.
AN0
RA1/AN1
RA1
I/O
I
TTL
Analog
Digital I/O.
Analog input 1.
AN1
RA2/AN2/VREF-
RA2
I/O
TTL
Digital I/O.
AN2
VREF-
I
I
Analog
Analog
Analog input 2.
A/D reference voltage (low) input.
RA3/AN3/VREF+
RA3
21
I/O
TTL
Digital I/O.
AN3
VREF+
I
I
Analog
Analog
Analog input 3.
A/D reference voltage (high) input.
RA4/T0CKI
RA4
28
27
I/O ST/OD
Digital I/O. Open-drain when configured as output.
Timer0 external clock input.
T0CKI
I
ST
RA5/AN4
RA5
I/O
I
TTL
Analog
Digital I/O.
Analog input 4.
AN4
RA6
RA7
See the OSC2/CLKO/RA6 pin.
See the OSC1/CLKI/RA7 pin.
Legend: TTL = TTL compatible input
ST = Schmitt Trigger input with CMOS levels
CMOS = CMOS compatible input or output
Analog = Analog input
I
= Input
O
= Output
P
= Power
OD
= Open-Drain (no P diode to VDD)
Note 1: Default assignment for CCP2 when CCP2MX Configuration bit is set.
2: Alternate assignment for CCP2 when CCP2MX Configuration bit is cleared.
DS39774C-page 12
Preliminary
© 2007 Microchip Technology Inc.
PIC18F85J11 FAMILY
TABLE 1-3:
PIC18F6XJ11 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number
Pin Buffer
Type Type
Pin Name
Description
TQFP
PORTB is a bidirectional I/O port. PORTB can be software
programmed for internal weak pull-ups on all inputs.
RB0/INT0
RB0
48
47
46
45
44
43
42
I/O
I
TTL
ST
Digital I/O.
External interrupt 0.
INT0
RB1/INT1
RB1
I/O
I
TTL
ST
Digital I/O.
External interrupt 1.
INT1
RB2/INT2
RB2
I/O
I
TTL
ST
Digital I/O.
External interrupt 2.
INT2
RB3/INT3
RB3
I/O
I
TTL
ST
Digital I/O.
External interrupt 3.
INT3
RB4/KBI0
RB4
I/O
I
TTL
TTL
Digital I/O.
Interrupt-on-change pin.
KBI0
RB5/KBI1
RB5
I/O
I
TTL
TTL
Digital I/O.
Interrupt-on-change pin.
KBI1
RB6/KBI2/PGC
RB6
I/O
I
I/O
TTL
TTL
ST
Digital I/O.
Interrupt-on-change pin.
In-Circuit Debugger and ICSP™ programming clock pin.
KBI2
PGC
RB7/KBI3/PGD
RB7
37
I/O
I
I/O
TTL
TTL
ST
Digital I/O.
Interrupt-on-change pin.
In-Circuit Debugger and ICSP programming data pin.
KBI3
PGD
Legend: TTL = TTL compatible input
ST = Schmitt Trigger input with CMOS levels
CMOS = CMOS compatible input or output
Analog = Analog input
I
= Input
O
= Output
P
= Power
OD
= Open-Drain (no P diode to VDD)
Note 1: Default assignment for CCP2 when CCP2MX Configuration bit is set.
2: Alternate assignment for CCP2 when CCP2MX Configuration bit is cleared.
© 2007 Microchip Technology Inc.
Preliminary
DS39774C-page 13
PIC18F85J11 FAMILY
TABLE 1-3:
PIC18F6XJ11 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number
Pin Buffer
Type Type
Pin Name
Description
TQFP
PORTC is a bidirectional I/O port.
RC0/T1OSO/T13CKI
RC0
30
29
I/O
O
I
ST
—
ST
Digital I/O.
Timer1 oscillator output.
Timer1/Timer3 external clock input.
T1OSO
T13CKI
RC1/T1OSI/CCP2
RC1
I/O
I
I/O
ST
CMOS
ST
Digital I/O.
Timer1 oscillator input.
Capture 2 input/Compare 2 output/PWM2 output.
T1OSI
CCP2(1)
RC2/CCP1
RC2
33
34
I/O
I/O
ST
ST
Digital I/O.
CCP1
Capture 1 input/Compare 1 output/PWM1 output.
RC3/SCK/SCL
RC3
I/O
I/O
I/O
ST
ST
ST
Digital I/O.
SCK
SCL
Synchronous serial clock input/output for SPI mode.
Synchronous serial clock input/output for I2C™ mode.
RC4/SDI/SDA
RC4
35
I/O
I
I/O
ST
ST
ST
Digital I/O.
SDI
SDA
SPI data in.
I2C data I/O.
RC5/SDO
RC5
36
31
I/O
O
ST
—
Digital I/O.
SPI data out.
SDO
RC6/TX1/CK1
RC6
I/O
O
I/O
ST
—
ST
Digital I/O.
TX1
CK1
EUSART asynchronous transmit.
EUSART synchronous clock (see related RX1/DT1).
RC7/RX1/DT1
RC7
32
I/O
I
I/O
ST
ST
ST
Digital I/O.
RX1
DT1
EUSART asynchronous receive.
EUSART synchronous data (see related TX1/CK1).
Legend: TTL = TTL compatible input
ST = Schmitt Trigger input with CMOS levels
CMOS = CMOS compatible input or output
Analog = Analog input
I
= Input
O
= Output
P
= Power
OD
= Open-Drain (no P diode to VDD)
Note 1: Default assignment for CCP2 when CCP2MX Configuration bit is set.
2: Alternate assignment for CCP2 when CCP2MX Configuration bit is cleared.
DS39774C-page 14
Preliminary
© 2007 Microchip Technology Inc.
PIC18F85J11 FAMILY
TABLE 1-3:
PIC18F6XJ11 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number
Pin Buffer
Type Type
Pin Name
Description
TQFP
PORTD is a bidirectional I/O port.
RD0/PSP0
RD0
58
55
I/O
I/O
ST
TTL
Digital I/O.
Parallel Slave Port data.
PSP0
RD1/PSP1
RD1
I/O
I/O
ST
TTL
Digital I/O.
Parallel Slave Port data.
PSP1
RD2/PSP2
RD2
54
53
52
51
50
49
I/O
I/O
ST
TTL
Digital I/O.
Parallel Slave Port data.
PSP2
RD3/PSP3
RD3
I/O
I/O
ST
TTL
Digital I/O.
Parallel Slave Port data.
PSP3
RD4/PSP4
RD4
I/O
I/O
ST
TTL
Digital I/O.
Parallel Slave Port data.
PSP4
RD5/PSP5
RD5
I/O
I/O
ST
TTL
Digital I/O.
Parallel Slave Port data.
PSP5
RD6/PSP6
RD6
I/O
I/O
ST
TTL
Digital I/O.
Parallel Slave Port data.
PSP6
RD7/PSP7
RD7
I/O
I/O
ST
TTL
Digital I/O.
Parallel Slave Port data.
PSP7
Legend: TTL = TTL compatible input
ST = Schmitt Trigger input with CMOS levels
CMOS = CMOS compatible input or output
Analog = Analog input
I
= Input
O
= Output
P
= Power
OD
= Open-Drain (no P diode to VDD)
Note 1: Default assignment for CCP2 when CCP2MX Configuration bit is set.
2: Alternate assignment for CCP2 when CCP2MX Configuration bit is cleared.
© 2007 Microchip Technology Inc.
Preliminary
DS39774C-page 15
PIC18F85J11 FAMILY
TABLE 1-3:
PIC18F6XJ11 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number
Pin Buffer
Type Type
Pin Name
Description
TQFP
PORTE is a bidirectional I/O port.
RE0/RD
RE0
2
1
I/O
I
ST
TTL
Digital I/O.
Read control for Parallel Slave Port.
RD
RE1/WR
RE1
I/O
I
ST
TTL
Digital I/O.
Write control for Parallel Slave Port.
WR
RE2/CS
RE2
64
I/O
I
ST
TTL
Digital I/O.
Chip select control for Parallel Slave Port.
CS
RE3
RE4
RE5
RE6
I/O
I/O
I/O
I/O
ST
ST
ST
ST
Digital I/O.
Digital I/O.
Digital I/O.
Digital I/O.
63
62
61
60
59
RE7/CCP2
RE7
I/O
I/O
ST
ST
Digital I/O.
CCP2(2)
Capture 2 input/Compare 2 output/PWM2 output.
Legend: TTL = TTL compatible input
ST = Schmitt Trigger input with CMOS levels
CMOS = CMOS compatible input or output
Analog = Analog input
I
= Input
O
= Output
P
= Power
OD
= Open-Drain (no P diode to VDD)
Note 1: Default assignment for CCP2 when CCP2MX Configuration bit is set.
2: Alternate assignment for CCP2 when CCP2MX Configuration bit is cleared.
DS39774C-page 16
Preliminary
© 2007 Microchip Technology Inc.
PIC18F85J11 FAMILY
TABLE 1-3:
PIC18F6XJ11 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number
Pin Buffer
Type Type
Pin Name
Description
TQFP
PORTF is a bidirectional I/O port.
RF1/AN6/C2OUT
RF1
17
16
I/O
I
O
ST
Analog
—
Digital I/O.
Analog input 6.
Comparator 2 output.
AN6
C2OUT
RF2/AN7/C1OUT
RF2
I/O
I
O
ST
Analog
—
Digital I/O.
Analog input 7.
Comparator 1 output.
AN7
C1OUT
RF3/AN8
RF3
15
14
13
I/O
I
ST
Analog
Digital I/O.
Analog input 8.
AN8
RF4/AN9
RF4
I/O
I
ST
Analog
Digital I/O.
Analog input 9.
AN9
RF5/AN10/CVREF
RF5
I/O
I
O
ST
Analog
Analog
Digital I/O.
Analog input 10.
Comparator reference voltage output.
AN10
CVREF
RF6/AN11
RF6
12
11
I/O
I
ST
Analog
Digital I/O.
Analog input 11.
AN11
RF7/AN5/SS
RF7
I/O
O
I
ST
Analog
TTL
Digital I/O.
Analog input 5.
SPI slave select input.
AN5
SS
Legend: TTL = TTL compatible input
ST = Schmitt Trigger input with CMOS levels
CMOS = CMOS compatible input or output
Analog = Analog input
I
= Input
O
= Output
P
= Power
OD
= Open-Drain (no P diode to VDD)
Note 1: Default assignment for CCP2 when CCP2MX Configuration bit is set.
2: Alternate assignment for CCP2 when CCP2MX Configuration bit is cleared.
© 2007 Microchip Technology Inc.
Preliminary
DS39774C-page 17
PIC18F85J11 FAMILY
TABLE 1-3:
PIC18F6XJ11 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number
Pin Buffer
Type Type
Pin Name
Description
TQFP
PORTG is a bidirectional I/O port.
Digital I/O.
RG0
3
4
I/O
ST
RG1/TX2/CK2
RG1
I/O
O
I/O
ST
—
ST
Digital I/O.
TX2
CK2
AUSART asynchronous transmit.
AUSART synchronous clock (see related RX2/DT2).
RG2/RX2/DT2
RG2
5
6
I/O
I
I/O
ST
ST
ST
Digital I/O.
RX2
DT2
AUSART asynchronous receive.
AUSART synchronous data (see related TX2/CK2).
RG3
I/O
ST
Digital I/O.
RG4
8
I/O
P
P
P
P
I
ST
—
—
—
—
ST
Digital I/O.
VSS
9, 25, 41, 56
Ground reference for logic and I/O pins.
Positive supply for logic and I/O pins.
Ground reference for analog modules.
Positive supply for analog modules.
Enable for on-chip voltage regulator.
VDD
26, 38, 57
AVSS
AVDD
ENVREG
20
19
18
10
VDDCORE/VCAP
VDDCORE
Core logic power or external filter capacitor connection.
Positive supply for microcontroller core logic
(regulator disabled).
P
P
—
—
VCAP
External filter capacitor connection (regulator enabled).
Legend: TTL = TTL compatible input
ST = Schmitt Trigger input with CMOS levels
CMOS = CMOS compatible input or output
Analog = Analog input
I
= Input
O
= Output
P
= Power
OD
= Open-Drain (no P diode to VDD)
Note 1: Default assignment for CCP2 when CCP2MX Configuration bit is set.
2: Alternate assignment for CCP2 when CCP2MX Configuration bit is cleared.
DS39774C-page 18
Preliminary
© 2007 Microchip Technology Inc.
PIC18F85J11 FAMILY
TABLE 1-4:
PIC18F8XJ11 PINOUT I/O DESCRIPTIONS
Pin Number
Pin Buffer
Type Type
Pin Name
Description
TQFP
MCLR
9
I
ST
Master Clear (input) or programming voltage (input). This
pin is an active-low Reset to the device.
RA7/OSC1/CLKI
RA7
49
50
Oscillator crystal or external clock input.
General purpose I/O pin.
I/O
I
I
TTL
CMOS
CMOS
OSC1
CLKI
Oscillator crystal input.
External clock source input. Always associated
with pin function OSC1. (See related OSC1/CLKI,
OSC2/CLKO pins.)
RA6/OSC2/CLKO
RA6
Oscillator crystal or clock output.
I/O
O
TTL
—
General purpose I/O pin.
OSC2
Oscillator crystal output. Connects to crystal or
resonator in Crystal Oscillator mode.
In EC modes, OSC2 pin outputs CLKO, which has
1/4 the frequency of OSC1 and denotes the
instruction cycle rate.
CLKO
O
—
PORTA is a bidirectional I/O port.
RA0/AN0
RA0
30
29
28
I/O
I
TTL
Analog
Digital I/O.
Analog input 0.
AN0
RA1/AN1
RA1
I/O
I
TTL
Analog
Digital I/O.
Analog input 1.
AN1
RA2/AN2/VREF-
RA2
I/O
TTL
Digital I/O.
AN2
VREF-
I
I
Analog
Analog
Analog input 2.
A/D reference voltage (low) input.
RA3/AN3/VREF+
RA3
27
I/O
TTL
Digital I/O.
AN3
VREF+
I
I
Analog
Analog
Analog input 3.
A/D reference voltage (high) input.
RA4/T0CKI
RA4
34
33
I/O ST/OD
Digital I/O. Open-drain when configured as output.
Timer0 external clock input.
T0CKI
I
ST
RA5/AN4
RA5
I/O
I
TTL
Analog
Digital I/O.
Analog input 4.
AN4
RA6
RA7
See the OSC2/CLKO/RA6 pin.
See the OSC1/CLKI/RA7 pin.
Legend: TTL = TTL compatible input
ST = Schmitt Trigger input with CMOS levels
CMOS = CMOS compatible input or output
Analog = Analog input
I
= Input
O
= Output
P
= Power
OD
= Open-Drain (no P diode to VDD)
Note 1: Alternate assignment for CCP2 when CCP2MX Configuration bit is cleared (80-pin devices, Extended
Microcontroller mode only).
2: Default assignment for CCP2 when CCP2MX Configuration bit is set.
3: Alternate assignment for CCP2 when CCP2MX Configuration bit is cleared.
© 2007 Microchip Technology Inc.
Preliminary
DS39774C-page 19
PIC18F85J11 FAMILY
TABLE 1-4:
PIC18F8XJ11 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number
Pin Buffer
Type Type
Pin Name
Description
TQFP
PORTB is a bidirectional I/O port. PORTB can be software
programmed for internal weak pull-ups on all inputs.
RB0/INT0
RB0
58
57
56
55
I/O
I
TTL
ST
Digital I/O.
External interrupt 0.
INT0
RB1/INT1
RB1
I/O
I
TTL
ST
Digital I/O.
External interrupt 1.
INT1
RB2/INT2
RB2
I/O
I
TTL
ST
Digital I/O.
External interrupt 2.
INT2
RB3/INT3/CCP2
RB3
I/O
I
I/O
TTL
ST
ST
Digital I/O.
External interrupt 3.
Capture 2 input/Compare 2 output/PWM2 output.
INT3
CCP2(1)
RB4/KBI0
RB4
54
53
52
I/O
I
TTL
TTL
Digital I/O.
Interrupt-on-change pin.
KBI0
RB5/KBI1
RB5
I/O
I
TTL
TTL
Digital I/O.
Interrupt-on-change pin.
KBI1
RB6/KBI2/PGC
RB6
I/O
I
I/O
TTL
TTL
ST
Digital I/O.
Interrupt-on-change pin.
In-Circuit Debugger and ICSP™ programming clock pin.
KBI2
PGC
RB7/KBI3/PGD
RB7
47
I/O
I
I/O
TTL
TTL
ST
Digital I/O.
Interrupt-on-change pin.
In-Circuit Debugger and ICSP programming data pin.
KBI3
PGD
Legend: TTL = TTL compatible input
ST = Schmitt Trigger input with CMOS levels
CMOS = CMOS compatible input or output
Analog = Analog input
I
= Input
O
= Output
P
= Power
OD
= Open-Drain (no P diode to VDD)
Note 1: Alternate assignment for CCP2 when CCP2MX Configuration bit is cleared (80-pin devices, Extended
Microcontroller mode only).
2: Default assignment for CCP2 when CCP2MX Configuration bit is set.
3: Alternate assignment for CCP2 when CCP2MX Configuration bit is cleared.
DS39774C-page 20
Preliminary
© 2007 Microchip Technology Inc.
PIC18F85J11 FAMILY
TABLE 1-4:
PIC18F8XJ11 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number
Pin Buffer
Type Type
Pin Name
Description
TQFP
PORTC is a bidirectional I/O port.
RC0/T1OSO/T13CKI
RC0
36
35
I/O
O
I
ST
—
ST
Digital I/O.
Timer1 oscillator output.
Timer1/Timer3 external clock input.
T1OSO
T13CKI
RC1/T1OSI/CCP2
RC1
I/O
I
I/O
ST
CMOS
ST
Digital I/O.
Timer1 oscillator input.
Capture 2 input/Compare 2 output/PWM2 output.
T1OSI
CCP2(2)
RC2/CCP1
RC2
43
44
I/O
I/O
ST
ST
Digital I/O.
CCP1
Capture 1 input/Compare 1 output/PWM1 output.
RC3/SCK/SCL
RC3
I/O
I/O
I/O
ST
ST
ST
Digital I/O.
SCK
SCL
Synchronous serial clock input/output for SPI mode.
Synchronous serial clock input/output for I2C™ mode.
RC4/SDI/SDA
RC4
45
I/O
I
I/O
ST
ST
ST
Digital I/O.
SDI
SDA
SPI data in.
I2C data I/O.
RC5/SDO
RC5
46
37
I/O
O
ST
—
Digital I/O.
SPI data out.
SDO
RC6/TX1/CK1
RC6
I/O
O
I/O
ST
—
ST
Digital I/O.
TX1
CK1
EUSART asynchronous transmit.
EUSART synchronous clock (see related RX1/DT1).
RC7/RX1/DT1
RC7
38
I/O
I
I/O
ST
ST
ST
Digital I/O.
RX1
DT1
EUSART asynchronous receive.
EUSART synchronous data (see related TX1/CK1).
Legend: TTL = TTL compatible input
ST = Schmitt Trigger input with CMOS levels
CMOS = CMOS compatible input or output
Analog = Analog input
I
= Input
O
= Output
P
= Power
OD
= Open-Drain (no P diode to VDD)
Note 1: Alternate assignment for CCP2 when CCP2MX Configuration bit is cleared (80-pin devices, Extended
Microcontroller mode only).
2: Default assignment for CCP2 when CCP2MX Configuration bit is set.
3: Alternate assignment for CCP2 when CCP2MX Configuration bit is cleared.
© 2007 Microchip Technology Inc.
Preliminary
DS39774C-page 21
PIC18F85J11 FAMILY
TABLE 1-4:
PIC18F8XJ11 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number
Pin Buffer
Type Type
Pin Name
Description
TQFP
PORTD is a bidirectional I/O port.
RD0/AD0/PSP0
RD0
72
69
I/O
I/O
I/O
ST
TTL
TTL
Digital I/O.
External memory address/data 0.
Parallel Slave Port data.
AD0
PSP0
RD1/AD1/PSP1
RD1
I/O
I/O
I/O
ST
TTL
TTL
Digital I/O.
External memory address/data 1.
Parallel Slave Port data.
AD1
PSP1
RD2/AD2/PSP2
RD2
68
67
66
65
64
63
I/O
I/O
I/O
ST
TTL
TTL
Digital I/O.
External memory address/data 2.
Parallel Slave Port data.
AD2
PSP2
RD3/AD3/PSP3
RD3
I/O
I/O
I/O
ST
TTL
TTL
Digital I/O.
External memory address/data 3.
Parallel Slave Port data.
AD3
PSP3
RD4/AD4/PSP4
RD4
I/O
I/O
I/O
ST
TTL
TTL
Digital I/O.
External memory address/data 4.
Parallel Slave Port data.
AD4
PSP4
RD5/AD5/PSP5
RD5
I/O
I/O
I/O
ST
TTL
TTL
Digital I/O.
External memory address/data 5.
Parallel Slave Port data.
AD5
PSP5
RD6/AD6/PSP6
RD6
I/O
I/O
I/O
ST
TTL
TTL
Digital I/O.
External memory address/data 6.
Parallel Slave Port data.
AD6
PSP6
RD7/AD7/PSP7
RD7
I/O
I/O
I/O
ST
TTL
TTL
Digital I/O.
External memory address/data 7.
Parallel Slave Port data.
AD7
PSP7
Legend: TTL = TTL compatible input
ST = Schmitt Trigger input with CMOS levels
CMOS = CMOS compatible input or output
Analog = Analog input
I
= Input
O
= Output
P
= Power
OD
= Open-Drain (no P diode to VDD)
Note 1: Alternate assignment for CCP2 when CCP2MX Configuration bit is cleared (80-pin devices, Extended
Microcontroller mode only).
2: Default assignment for CCP2 when CCP2MX Configuration bit is set.
3: Alternate assignment for CCP2 when CCP2MX Configuration bit is cleared.
DS39774C-page 22
Preliminary
© 2007 Microchip Technology Inc.
PIC18F85J11 FAMILY
TABLE 1-4:
PIC18F8XJ11 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number
Pin Buffer
Type Type
Pin Name
Description
TQFP
PORTE is a bidirectional I/O port.
RE0/RD/AD8
RE0
4
3
I/O
I
I/O
ST
TTL
TTL
Digital I/O.
Read control for Parallel Slave Port.
External memory address/data 8.
RD
AD8
RE1/WR/AD9
RE1
I/O
I
I/O
ST
TTL
TTL
Digital I/O.
Write control for Parallel Slave Port.
External memory address/data 9.
WR
AD9
RE2/AD10/CS
RE2
78
I/O
I/O
I
ST
TTL
TTL
Digital I/O.
External memory address/data 10.
Chip select control for Parallel Slave Port.
AD10
CS
RE3/AD11
RE3
77
76
75
74
73
I/O
I/O
ST
TTL
Digital I/O.
External memory address/data 11.
AD11
RE4/AD12
RE4
I/O
I/O
ST
TTL
Digital I/O.
External memory address/data 12.
AD12
RE5/AD13
RE5
I/O
I/O
ST
TTL
Digital I/O.
External memory address/data 13.
AD13
RE6/AD14
RE6
I/O
I/O
ST
TTL
Digital I/O.
External memory address/data 14.
AD14
RE7/AD15/CCP2
RE7
I/O
I/O
I/O
ST
TTL
ST
Digital I/O.
AD15
External memory address/data 15.
Capture 2 input/Compare 2 output/PWM2 output.
CCP2(3)
Legend: TTL = TTL compatible input
ST = Schmitt Trigger input with CMOS levels
CMOS = CMOS compatible input or output
Analog = Analog input
I
= Input
O
= Output
P
= Power
OD
= Open-Drain (no P diode to VDD)
Note 1: Alternate assignment for CCP2 when CCP2MX Configuration bit is cleared (80-pin devices, Extended
Microcontroller mode only).
2: Default assignment for CCP2 when CCP2MX Configuration bit is set.
3: Alternate assignment for CCP2 when CCP2MX Configuration bit is cleared.
© 2007 Microchip Technology Inc.
Preliminary
DS39774C-page 23
PIC18F85J11 FAMILY
TABLE 1-4:
PIC18F8XJ11 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number
Pin Buffer
Type Type
Pin Name
Description
TQFP
PORTF is a bidirectional I/O port.
RF1/AN6/C2OUT
RF1
23
18
I/O
I
O
ST
Analog
—
Digital I/O.
Analog input 6.
Comparator 2 output.
AN6
C2OUT
RF2/AN7/C1OUT
RF2
I/O
I
O
ST
Analog
—
Digital I/O.
Analog input 7.
Comparator 1 output.
AN7
C1OUT
RF3/AN8
RF3
17
16
15
I/O
I
ST
Analog
Digital I/O.
Analog input 8.
AN8
RF4/AN9
RF4
I/O
I
ST
Analog
Digital I/O.
Analog input 9.
AN9
RF5/AN10/CVREF
RF5
I/O
I
O
ST
Analog
Analog
Digital I/O.
Analog input 10.
Comparator reference voltage output.
AN10
CVREF
RF6/AN11
RF6
14
13
I/O
I
ST
Analog
Digital I/O.
Analog input 11.
AN11
RF7/AN5/SS
RF7
I/O
O
I
ST
Analog
TTL
Digital I/O.
Analog input 5.
SPI slave select input.
AN5
SS
Legend: TTL = TTL compatible input
ST = Schmitt Trigger input with CMOS levels
CMOS = CMOS compatible input or output
Analog = Analog input
I
= Input
O
= Output
P
= Power
OD
= Open-Drain (no P diode to VDD)
Note 1: Alternate assignment for CCP2 when CCP2MX Configuration bit is cleared (80-pin devices, Extended
Microcontroller mode only).
2: Default assignment for CCP2 when CCP2MX Configuration bit is set.
3: Alternate assignment for CCP2 when CCP2MX Configuration bit is cleared.
DS39774C-page 24
Preliminary
© 2007 Microchip Technology Inc.
PIC18F85J11 FAMILY
TABLE 1-4:
PIC18F8XJ11 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number
Pin Buffer
Type Type
Pin Name
Description
TQFP
PORTG is a bidirectional I/O port.
Digital I/O.
RG0
5
6
I/O
ST
RG1/TX2/CK2
RG1
I/O
O
I/O
ST
—
ST
Digital I/O.
TX2
CK2
AUSART asynchronous transmit.
AUSART synchronous clock (see related RX2/DT2).
RG2/RX2/DT2
RG2
7
I/O
I
I/O
ST
ST
ST
Digital I/O.
RX2
DT2
AUSART asynchronous receive.
AUSART synchronous data (see related TX2/CK2).
RG3
RG4
8
I/O
I/O
ST
ST
Digital I/O.
Digital I/O.
10
Legend: TTL = TTL compatible input
ST = Schmitt Trigger input with CMOS levels
CMOS = CMOS compatible input or output
Analog = Analog input
I
= Input
O
= Output
P
= Power
OD
= Open-Drain (no P diode to VDD)
Note 1: Alternate assignment for CCP2 when CCP2MX Configuration bit is cleared (80-pin devices, Extended
Microcontroller mode only).
2: Default assignment for CCP2 when CCP2MX Configuration bit is set.
3: Alternate assignment for CCP2 when CCP2MX Configuration bit is cleared.
© 2007 Microchip Technology Inc.
Preliminary
DS39774C-page 25
PIC18F85J11 FAMILY
TABLE 1-4:
PIC18F8XJ11 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number
Pin Buffer
Type Type
Pin Name
Description
TQFP
PORTH is a bidirectional I/O port.
RH0/A16
RH0
79
80
I/O
I/O
ST
TTL
Digital I/O.
External memory address/data 16.
A16
RH1/A17
RH1
I/O
I/O
ST
TTL
Digital I/O.
External memory address/data 17.
A17
RH2/A18
RH2
1
2
I/O
I/O
ST
TTL
Digital I/O.
External memory address/data 18.
A18
RH3/A19
RH3
I/O
I/O
ST
TTL
Digital I/O.
External memory address/data 19.
A19
RH4
RH5
RH6
RH7
22
21
20
19
I/O
I/O
I/O
I/O
ST
ST
ST
ST
Digital I/O.
Digital I/O.
Digital I/O.
Digital I/O.
Legend: TTL = TTL compatible input
ST = Schmitt Trigger input with CMOS levels
CMOS = CMOS compatible input or output
Analog = Analog input
I
= Input
O
= Output
P
= Power
OD
= Open-Drain (no P diode to VDD)
Note 1: Alternate assignment for CCP2 when CCP2MX Configuration bit is cleared (80-pin devices, Extended
Microcontroller mode only).
2: Default assignment for CCP2 when CCP2MX Configuration bit is set.
3: Alternate assignment for CCP2 when CCP2MX Configuration bit is cleared.
DS39774C-page 26
Preliminary
© 2007 Microchip Technology Inc.
PIC18F85J11 FAMILY
TABLE 1-4:
PIC18F8XJ11 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number
Pin Buffer
Type Type
Pin Name
Description
TQFP
PORTJ is a bidirectional I/O port.
RJ0/ALE
RJ0
62
61
I/O
O
ST
—
Digital I/O.
External memory address latch enable.
ALE
RJ1/OE
RJ1
I/O
O
ST
—
Digital I/O.
External memory output enable.
OE
RJ2/WRL
RJ2
60
59
39
40
41
42
I/O
O
ST
—
Digital I/O.
External memory write low control.
WRL
RJ3/WRH
RJ3
I/O
O
ST
—
Digital I/O.
External memory write high control.
WRH
RJ4/BA0
RJ4
I/O
O
ST
—
Digital I/O.
External memory byte address 0 control.
BA0
RJ5/CE
RJ5
I/O
O
ST
—
Digital I/O
External memory chip enable control.
CE
RJ6/LB
RJ6
I/O
O
ST
—
Digital I/O.
External memory low byte control.
LB
RJ7/UB
RJ7
I/O
O
ST
—
Digital I/O.
External memory high byte control.
UB
VSS
11, 31, 51, 70
P
P
P
P
I
—
—
—
—
ST
Ground reference for logic and I/O pins.
Positive supply for logic and I/O pins.
Ground reference for analog modules.
Positive supply for analog modules.
Enable for on-chip voltage regulator.
VDD
32, 48, 71
AVSS
AVDD
ENVREG
26
25
24
12
VDDCORE/VCAP
VDDCORE
Core logic power or external filter capacitor connection.
Positive supply for microcontroller core logic
(regulator disabled).
P
P
—
—
VCAP
External filter capacitor connection (regulator enabled).
Legend: TTL = TTL compatible input
ST = Schmitt Trigger input with CMOS levels
CMOS = CMOS compatible input or output
Analog = Analog input
I
= Input
O
= Output
P
= Power
OD
= Open-Drain (no P diode to VDD)
Note 1: Alternate assignment for CCP2 when CCP2MX Configuration bit is cleared (80-pin devices, Extended
Microcontroller mode only).
2: Default assignment for CCP2 when CCP2MX Configuration bit is set.
3: Alternate assignment for CCP2 when CCP2MX Configuration bit is cleared.
© 2007 Microchip Technology Inc.
Preliminary
DS39774C-page 27
PIC18F85J11 FAMILY
NOTES:
DS39774C-page 28
Preliminary
© 2007 Microchip Technology Inc.
PIC18F85J11 FAMILY
Five of these are selected by the user by programming
the FOSC2:FOSC0 Configuration bits. The sixth mode
(INTRC) may be invoked under software control; it can
also be configured as the default mode on device
Resets.
2.0
2.1
OSCILLATOR
CONFIGURATIONS
Oscillator Types
The PIC18F85J11 family of devices can be operated in
six different oscillator modes:
In addition, PIC18F85J11 family devices can switch
between different clock sources, either under software
control or automatically under certain conditions. This
allows for additional power savings by managing
device clock speed in real time without resetting the
application.
1. HS
High-Speed Crystal/Resonator
2. HSPLL High-Speed Crystal/Resonator
with Software PLL Control
3. EC
External Clock with FOSC/4 Output
The clock sources for the PIC18F85J11 family of
devices are shown in Figure 2-1.
4. ECPLL External Clock with Software PLL
Control
5. INTOSC Internal Fast RC (8 MHz) Oscillator
6. INTRC Internal 31 kHz Oscillator
FIGURE 2-1:
PIC18F85J11 FAMILY CLOCK DIAGRAM
PIC18F85J11 Family
Primary Oscillator
HS, EC
OSC2
Sleep
HSPLL, ECPLL
4 x PLL
OSC1
Peripherals
Secondary Oscillator
T1OSC
T1OSO
T1OSCEN
Enable
Oscillator
T1OSI
Internal Oscillator
OSCCON<6:4>
CPU
OSCCON<6:4>
8 MHz
111
110
101
4 MHz
2 MHz
Internal
Oscillator
Block
IDLEN
Clock
1 MHz
Control
100
011
010
001
000
500 kHz
250 kHz
125 kHz
31 kHz
8 MHz
Source
8 MHz
(INTOSC)
FOSC2:FOSC0 OSCCON<1:0>
Clock Source Option
for Other Modules
1
0
INTRC
Source
OSCTUNE<7>
31 kHz (INTRC)
WDT, PWRT, FSCM
and Two-Speed Start-up
© 2007 Microchip Technology Inc.
Preliminary
DS39774C-page 29
PIC18F85J11 FAMILY
The OSCTUNE register (Register 2-2) controls the
tuning and operation of the internal oscillator block. It
also implements the PLLEN bits which control the
operation of the Phase Locked Loop (PLL) in Internal
Oscillator modes (see Section 2.4.3 “PLL Frequency
Multiplier”).
2.2
Control Registers
The OSCCON register (Register 2-1) controls the main
aspects of the device clock’s operation. It selects the
oscillator type to be used, which of the power-managed
modes to invoke and the output frequency of the
INTOSC source. It also provides status on the
oscillators.
REGISTER 2-1:
OSCCON: OSCILLATOR CONTROL REGISTER
R/W-0
IDLEN
bit 7
R/W-1
IRCF2(2)
R/W-0
IRCF1(2)
R/W-0
IRCF0(2)
R(1)
R-0
R/W-0
SCS1(4)
R/W-0
SCS0(4)
OSTS
IOFS
bit 0
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
-n = Value at POR
bit 7
IDLEN: Idle Enable bit
1= Device enters an Idle mode when a SLEEPinstruction is executed
0= Device enters Sleep mode when a SLEEPinstruction is executed
bit 6-4
IRCF2:IRCF0: INTOSC Source Frequency Select bits(2)
111= 8 MHz (INTOSC drives clock directly)
110= 4 MHz
101= 2 MHz
100= 1 MHz (default)
011= 500 kHz
010= 250 kHz
001= 125 kHz
000= 31 kHz (from either INTOSC/256 or INTRC)(3)
bit 3
OSTS: Oscillator Start-up Time-out Status bit(1)
1= Oscillator Start-up Timer (OST) time-out has expired; primary oscillator is running
0= Oscillator Start-up Timer (OST) time-out is running; primary oscillator is not ready
bit 2
IOFS: INTOSC Frequency Stable bit
1= Fast RC oscillator frequency is stable
0= Fast RC oscillator frequency is not stable
bit 1-0
SCS1:SCS0: System Clock Select bits(4)
11= Internal oscillator block
10= Primary oscillator
01= Timer1 oscillator
When FOSC2 = 1:
00= Primary oscillator
When FOSC2 = 0:
00= Internal oscillator
Note 1: Reset state depends on state of the IESO Configuration bit.
2: Modifying these bits will cause an immediate clock frequency switch if the internal oscillator is providing
the device clocks.
3: Source selected by the INTSRC bit (OSCTUNE<7>), see text.
4: Modifying these bits will cause an immediate clock source switch.
DS39774C-page 30
Preliminary
© 2007 Microchip Technology Inc.
PIC18F85J11 FAMILY
REGISTER 2-2:
OSCTUNE: OSCILLATOR TUNING REGISTER
R/W-0
R/W-0
PLLEN(1)
R/W-0
TUN5
R/W-0
TUN4
R/W-0
TUN3
R/W-0
TUN2
R/W-0
TUN1
R/W-0
TUN0
INTSRC
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
-n = Value at POR
bit 7
INTSRC: Internal Oscillator Low-Frequency Source Select bit
1= 31.25 kHz device clock derived from 8 MHz INTOSC source (divide-by-256 enabled)
0= 31 kHz device clock derived from INTRC 31 kHz oscillator
bit 6
PLLEN: Frequency Multiplier PLL Enable bit(1)
1= PLL enabled
0= PLL disabled
bit 5-0
TUN5:TUN0: Fast RC Oscillator (INTOSC) Frequency Tuning bits
011111= Maximum frequency
•
•
•
•
000001
000000= Center frequency. Fast RC oscillator is running at the calibrated frequency.
111111
•
•
•
•
100000= Minimum frequency
Note 1: Available only for ECPLL and HSPLL oscillator configurations; otherwise, this bit is unavailable and reads
as ‘0’.
PIC18F85J11 family devices offer the Timer1 oscillator
2.3
Clock Sources and
Oscillator Switching
as a secondary oscillator source. This oscillator, in all
power-managed modes, is often the time base for
functions such as a Real-Time Clock. The Timer1 oscil-
lator is discussed in greater detail in Section 12.3
“Timer1 Oscillator”
Essentially, PIC18F85J11 family devices have three
independent clock sources:
• Primary oscillators
• Secondary oscillators
• Internal oscillator
In addition to being a primary clock source in some cir-
cumstances, the internal oscillator is available as a
power-managed mode clock source. The INTRC
source is also used as the clock source for several
special features, such as the WDT and Fail-Safe Clock
Monitor. The internal oscillator block is discussed in
more detail in Section 2.5 “Internal Oscillator
Block”.
The primary oscillators can be thought of as the main
device oscillators. These are any external oscillators
connected to the OSC1 and OSC2 pins, and include
the External Crystal and Resonator modes and the
External Clock modes. In some circumstances, the
internal oscillator block may be considered a primary
oscillator. The particular mode is defined by the FOSC
Configuration bits. The details of these modes are
covered in Section 2.4 “External Oscillator Modes”.
The PIC18F85J11 family includes features that allow
the device clock source to be switched from the main
oscillator, chosen by device configuration, to one of the
alternate clock sources. When an alternate clock
source is enabled, various power-managed operating
modes are available.
The secondary oscillators are external clock sources
that are not connected to the OSC1 or OSC2 pins.
These sources may continue to operate even after the
controller is placed in a power-managed mode.
© 2007 Microchip Technology Inc.
Preliminary
DS39774C-page 31
PIC18F85J11 FAMILY
2.3.1
CLOCK SOURCE SELECTION
2.3.1.1
System Clock Selection and the
FOSC2 Configuration Bit
The System Clock Select bits, SCS1:SCS0
(OSCCON<1:0>), select the clock source. The avail-
able clock sources are the primary clock, defined by the
FOSC1:FOSC0 Configuration bits, the secondary
clock (Timer1 oscillator) and the internal oscillator. The
clock source changes after one or more of the bits are
written to, following a brief clock transition interval.
The SCS bits are cleared on all forms of Reset. In the
device’s default configuration, this means the primary
oscillator defined by FOSC1:FOSC0 (that is, one of the
HS or EC modes) is used as the primary clock source
on device Resets.
The default clock configuration on Reset can be
changed with the FOSC2 Configuration bit. This bit
determines whether the external or internal oscillator
will be the default clock source on subsequent device
Resets. By extension, it also has the effect of determin-
ing the clock source selected when SCS1:SCS0 are in
their Reset state (= 00). When FOSC2 = 1(default), the
oscillator source defined by FOSC1:FOSC0 is selected
whenever SCS1:SCS0 = 00. When FOSC2 = 0, the
internal oscillator block is selected whenever
SCS1:SCS2 = 00.
The OSTS (OSCCON<3>) and T1RUN (T1CON<6>)
bits indicate which clock source is currently providing
the device clock. The OSTS bit indicates that the
Oscillator Start-up Timer (OST) has timed out and the
primary clock is providing the device clock in primary
clock modes. The T1RUN bit indicates when the
Timer1 oscillator is providing the device clock in sec-
ondary clock modes. In power-managed modes, only
one of these bits will be set at any time. If neither of
these bits are set, the INTRC is providing the clock, or
the internal oscillator has just started and is not yet
stable.
In those cases when the internal oscillator block is the
default clock on Reset, the Fast RC oscillator
(INTOSC) will be used as the device clock source. It will
initially start at 1 MHz; the postscaler selection that
corresponds to the Reset value of the IRCF2:IRCF0
bits (‘100’).
The IDLEN bit determines if the device goes into Sleep
mode or one of the Idle modes when the SLEEP
instruction is executed.
The use of the flag and control bits in the OSCCON
register is discussed in more detail in Section 3.0
“Power-Managed Modes”.
Regardless of the setting of FOSC2, INTRC will always
be enabled on device power-up. It serves as the clock
source until the device has loaded its configuration
values from memory. It is at this point that the FOSC
Configuration bits are read and the oscillator selection
of the operational mode is made.
Note 1: The Timer1 oscillator must be enabled to
select the secondary clock source. The
Timer1 oscillator is enabled by setting the
T1OSCEN bit in the Timer1 Control regis-
ter (T1CON<3>). If the Timer1 oscillator is
not enabled, then any attempt to select a
secondary clock source when executing a
SLEEPinstruction will be ignored.
Note that either the primary clock or the internal
oscillator will have two bit setting options for the
possible values of SCS1:SCS0, at any given time,
depending on the setting of FOSC2.
2: It is recommended that the Timer1
oscillator be operating and stable before
executing the SLEEPinstruction or a very
long delay may occur while the Timer1
oscillator starts.
2.3.2
OSCILLATOR TRANSITIONS
PIC18F85J11 family devices contain circuitry to
prevent clock “glitches” when switching between clock
sources. A short pause in the device clock occurs dur-
ing the clock switch. The length of this pause is the sum
of two cycles of the old clock source and three to four
cycles of the new clock source. This formula assumes
that the new clock source is stable.
Clock transitions are discussed in greater detail in
Section 3.1.2 “Entering Power-Managed Modes”.
DS39774C-page 32
Preliminary
© 2007 Microchip Technology Inc.
PIC18F85J11 FAMILY
TABLE 2-2:
CAPACITOR SELECTION FOR
CRYSTAL OSCILLATOR
2.4
External Oscillator Modes
2.4.1
CRYSTAL OSCILLATOR/CERAMIC
RESONATORS (HS MODES)
Typical Capacitor Values
Crystal
Freq.
Tested:
Osc Type
In HS or HSPLL Oscillator modes, a crystal or ceramic
resonator is connected to the OSC1 and OSC2 pins to
establish oscillation. Figure 2-2 shows the pin
connections.
C1
C2
HS
4 MHz
8 MHz
20 MHz
27 pF
22 pF
15 pF
27 pF
22 pF
15 pF
The oscillator design requires the use of a parallel cut
crystal.
Capacitor values are for design guidance only.
Note:
Use of a series cut crystal may give a fre-
quency out of the crystal manufacturer’s
specifications.
Different capacitor values may be required to produce
acceptable oscillator operation. The user should test
the performance of the oscillator over the expected
VDD and temperature range for the application.
TABLE 2-1:
CAPACITOR SELECTION FOR
CERAMIC RESONATORS
Refer to the Microchip application notes cited in
Table 2-1 for oscillator specific information. Also see
the notes following this table for additional
information.
Typical Capacitor Values Used:
Mode
Freq.
OSC1
OSC2
HS
8.0 MHz
16.0 MHz
27 pF
22 pF
27 pF
22 pF
Note 1: Higher capacitance increases the
stability of oscillator but also increases
the start-up time.
Capacitor values are for design guidance only.
Different capacitor values may be required to produce
acceptable oscillator operation. The user should test
the performance of the oscillator over the expected
VDD and temperature range for the application. Refer
to the following application notes for oscillator specific
information:
2: Since each resonator/crystal has its own
characteristics, the user should consult
the resonator/crystal manufacturer for
appropriate
values
of
external
components.
3: Rs may be required to avoid overdriving
• AN588, “PIC® Microcontroller Oscillator Design
Guide”
crystals with low drive level specification.
4: Always verify oscillator performance over
the VDD and temperature range that is
expected for the application.
• AN826, “Crystal Oscillator Basics and Crystal
Selection for rfPIC® and PIC® Devices”
• AN849, “Basic PIC® Oscillator Design”
• AN943, “Practical PIC® Oscillator Analysis and
Design”
FIGURE 2-2:
CRYSTAL/CERAMIC
RESONATOROPERATION
(HS OR HSPLL
• AN949, “Making Your Oscillator Work”
CONFIGURATION)
See the notes following Table 2-2 for additional
information.
(1)
C1
C2
OSC1
To
Internal
Logic
(3)
XTAL
RF
Sleep
OSC2
(2)
RS
(1)
PIC18F85J11
Note 1: See Table 2-1 and Table 2-2 for initial values of
C1 and C2.
2: A series resistor (RS) may be required for AT
strip cut crystals.
3: RF varies with the oscillator mode chosen.
© 2007 Microchip Technology Inc.
Preliminary
DS39774C-page 33
PIC18F85J11 FAMILY
2.4.2
EXTERNAL CLOCK INPUT
(EC MODES)
2.4.3
PLL FREQUENCY MULTIPLIER
A Phase Locked Loop (PLL) circuit is provided as an
option for users who want to use a lower frequency
oscillator circuit, or to clock the device up to its highest
rated frequency from a crystal oscillator. This may be
useful for customers who are concerned with EMI due
to high-frequency crystals, or users who require higher
clock speeds from an internal oscillator. For these
reasons, the HSPLL and ECPLL modes are available.
The EC and ECPLL Oscillator modes require an exter-
nal clock source to be connected to the OSC1 pin.
There is no oscillator start-up time required after a
Power-on Reset or after an exit from Sleep mode.
In the EC Oscillator mode, the oscillator frequency
divided by 4 is available on the OSC2 pin. This signal
may be used for test purposes or to synchronize other
logic. Figure 2-3 shows the pin connections for the EC
Oscillator mode.
The HSPLL and ECPLL modes provide the ability to
selectively run the device at 4 times the external oscil-
lating source to produce frequencies up to 40 MHz.
The PLL is enabled by programming the
FOSC2:FOSC0 Configuration bits (CONFIG2L<2:0>)
to either ‘110’ (for ECPLL) or ‘100’ (for HSPLL). In
addition, the PLLEN bit (OSCTUNE<6>) must also be
set. Clearing PLLEN disables the PLL, regardless of
the chosen oscillator configuration. It also allows
additional flexibility for controlling the application’s
clock speed in software.
FIGURE 2-3:
EXTERNAL CLOCK
INPUT OPERATION
(EC CONFIGURATION)
OSC1/CLKI
Clock from
Ext. System
PIC18F85J11
OSC2/CLKO
FOSC/4
or RA6
FIGURE 2-5:
PLL BLOCK DIAGRAM
HSPLL or ECPLL (CONFIG2L)
PLL Enable (OSCTUNE)
An external clock source may also be connected to the
OSC1 pin in the HS mode, as shown in Figure 2-4. In
this configuration, the divide-by-4 output on OSC2 is
not available.
OSC2
Phase
Comparator
FIN
HS or EC
OSC1 Mode
FIGURE 2-4:
EXTERNAL CLOCK INPUT
OPERATION (HS OSC
CONFIGURATION)
FOUT
Loop
Filter
OSC1
Clock from
Ext. System
PIC18F85J11
÷4
VCO
SYSCLK
(HS Mode)
OSC2
Open
DS39774C-page 34
Preliminary
© 2007 Microchip Technology Inc.
PIC18F85J11 FAMILY
2.5.3
INTOSC FREQUENCY DRIFT
2.5
Internal Oscillator Block
The INTOSC frequency may drift as VDD or tempera-
ture changes, and can affect the controller operation in
a variety of ways. It is possible to adjust the INTOSC
frequency by modifying the value in the OSCTUNE
register. This will have no effect on the INTRC clock
source frequency.
The PIC18F85J11 family of devices includes an internal
oscillator block which generates two different clock
signals; either can be used as the microcontroller’s clock
source. This may eliminate the need for an external
oscillator circuit on the OSC1 and/or OSC2 pins.
The main output is the Fast RC oscillator, or INTOSC,
an 8 MHz clock source which can be used to directly
drive the device clock. It also drives a postscaler which
can provide a range of clock frequencies from 31 kHz
to 4 MHz. INTOSC is enabled when a clock frequency
from 125 kHz to 8 MHz is selected. The INTOSC out-
put can also be enabled when 31 kHz is selected,
depending on the INTSRC bit (OSCTUNE<7>).
Tuning INTOSC requires knowing when to make the
adjustment, in which direction it should be made, and in
some cases, how large a change is needed. Three
compensation techniques are shown here.
2.5.3.1
Compensating with the EUSART
An adjustment may be required when the EUSART
begins to generate framing errors or receives data with
errors while in Asynchronous mode. Framing errors
indicate that the device clock frequency is too high. To
adjust for this, decrement the value in OSCTUNE to
reduce the clock frequency. On the other hand, errors
in data may suggest that the clock speed is too low. To
compensate, increment OSCTUNE to increase the
clock frequency.
The other clock source is the Internal RC oscillator
(INTRC), which provides a nominal 31 kHz output.
INTRC is enabled if it is selected as the device clock
source. It is also enabled automatically when any of the
following are enabled:
• Power-up Timer
• Fail-Safe Clock Monitor
• Watchdog Timer
2.5.3.2
Compensating with the Timers
• Two-Speed Start-up
This technique compares device clock speed to some
reference clock. Two timers may be used; one timer is
clocked by the peripheral clock, while the other is
clocked by a fixed reference source, such as the
Timer1 oscillator.
These features are discussed in greater detail in
Section 22.0 “Special Features of the CPU”.
The clock source frequency (INTOSC direct, INTOSC
with postscaler or INTRC direct) is selected by config-
uring the IRCF bits of the OSCCON register. The
default frequency on device Resets is 1 MHz.
Both timers are cleared, but the timer clocked by the
reference generates interrupts. When an interrupt
occurs, the internally clocked timer is read and both
timers are cleared. If the internally clocked timer value
is much greater than expected, then the internal
oscillator block is running too fast. To adjust for this,
decrement the OSCTUNE register.
2.5.1
OSC1 AND OSC2 PIN
CONFIGURATION
Whenever the internal oscillator is configured as the
default clock source (FOSC2 = 0), the OSC1 and OSC2
pins are reconfigured automatically as port pins, RA6
and RA7. In this mode, they function as general digital
I/O. All oscillator functions on the pins are disabled.
2.5.3.3
Compensating with the CCP Module
in Capture Mode
2.5.2
INTERNAL OSCILLATOR OUTPUT
FREQUENCY AND TUNING
A CCP module can use free-running Timer1 (or
Timer3), clocked by the internal oscillator block and an
external event with a known period (i.e., AC power
frequency). The time of the first event is captured in the
CCPRxH:CCPRxL registers and is recorded for use
later. When the second event causes a capture, the
time of the first event is subtracted from the time of the
second event. Since the period of the external event is
known, the time difference between events can be
calculated.
The internal oscillator block is calibrated at the factory
to produce an INTOSC output frequency of 8 MHz. It
can be adjusted in the user’s application by writing to
TUN5:TUN0 (OSCTUNE<5:0>) in the OSCTUNE
register (Register 2-2).
When the OSCTUNE register is modified, the INTOSC
frequency will begin shifting to the new frequency. The
oscillator will stabilize within 1 ms. Code execution con-
tinues during this shift. There is no indication that the
shift has occurred.
If the measured time is much greater than the
calculated time, the internal oscillator block is running
too fast. To compensate, decrement the OSCTUNE
register. If the measured time is much less than the
calculated time, the internal oscillator block is running
too slow. To compensate, increment the OSCTUNE
register.
The INTRC oscillator operates independently of the
INTOSC source. Any changes in INTOSC across
voltage and temperature are not necessarily reflected
by changes in INTRC or vice versa. The frequency of
INTRC is not affected by OSCTUNE.
© 2007 Microchip Technology Inc.
Preliminary
DS39774C-page 35
PIC18F85J11 FAMILY
Timer1 oscillator may be operating to support a Real-
Time Clock (RTC). Other features may be operating
that do not require a device clock source (i.e., MSSP
slave, PSP, INTn pins and others). Peripherals that
may add significant current consumption are listed in
Section 25.2 “DC Characteristics: Power-Down and
Supply Current”.
2.6
Effects of Power-Managed Modes
on the Various Clock Sources
When PRI_IDLE mode is selected, the designated pri-
mary oscillator continues to run without interruption.
For all other power-managed modes, the oscillator
using the OSC1 pin is disabled. The OSC1 pin (and
OSC2 pin if used by the oscillator) will stop oscillating.
2.7
Power-up Delays
In secondary clock modes (SEC_RUN and
SEC_IDLE), the Timer1 oscillator is operating and
providing the device clock. The Timer1 oscillator may
also run in all power-managed modes if required to
clock Timer1 or Timer3.
Power-up delays are controlled by two timers, so that
no external Reset circuitry is required for most applica-
tions. The delays ensure that the device is kept in
Reset until the device power supply is stable under nor-
mal circumstances and the primary clock is operating
and stable. For additional information on power-up
delays, see Section 4.6 “Power-up Timer (PWRT)”.
In RC_RUN and RC_IDLE modes, the internal oscilla-
tor provides the device clock source. The 31 kHz
INTRC output can be used directly to provide the clock
and may be enabled to support various special
features, regardless of the power-managed mode (see
Section 22.2 “Watchdog Timer (WDT)” through
Section 22.5 “Fail-Safe Clock Monitor” for more
information on WDT, Fail-Safe Clock Monitor and
Two-Speed Start-up).
The first timer is the Power-up Timer (PWRT), which
provides a fixed delay on power-up (parameter 33,
Table 25-10). It is always enabled.
The second timer is the Oscillator Start-up Timer
(OST), intended to keep the chip in Reset until the
crystal oscillator is stable (HS modes). The OST does
this by counting 1024 oscillator cycles before allowing
the oscillator to clock the device.
If the Sleep mode is selected, all clock sources are
stopped. Since all the transistor switching currents
have been stopped, Sleep mode achieves the lowest
current consumption of the device (only leakage
currents).
There is a delay of interval TCSD (parameter 38,
Table 25-10), following POR, while the controller
becomes ready to execute instructions.
Enabling any on-chip feature that will operate during
Sleep will increase the current consumed during Sleep.
The INTRC is required to support WDT operation. The
TABLE 2-3:
OSC1 AND OSC2 PIN STATES IN SLEEP MODE
Oscillator Mode
OSC1 Pin
OSC2 Pin
EC, ECPLL
HS, HSPLL
Floating, pulled by external clock
At logic low (clock/4 output)
Feedback inverter disabled at quiescent
voltage level
Feedback inverter disabled at quiescent
voltage level
INTOSC
I/O pin, RA6, direction controlled by
TRISA<6>
I/O pin, RA7, direction controlled by
TRISA<7>
Note:
See Table 4-2 in Section 4.0 “Reset” for time-outs due to Sleep and MCLR Reset.
DS39774C-page 36
Preliminary
© 2007 Microchip Technology Inc.
PIC18F85J11 FAMILY
3.1.1
CLOCK SOURCES
3.0
POWER-MANAGED MODES
The SCS1:SCS0 bits allow the selection of one of three
clock sources for power-managed modes. They are:
The PIC18F85J11 family devices provide the ability to
manage power consumption by simply managing clock-
ing to the CPU and the peripherals. In general, a lower
clock frequency and a reduction in the number of circuits
being clocked constitutes lower consumed power. For
the sake of managing power in an application, there are
three primary modes of operation:
• the primary clock, as defined by the
FOSC2:FOSC0 Configuration bits
• the secondary clock (Timer1 oscillator)
• the internal oscillator
3.1.2
ENTERING POWER-MANAGED
MODES
• Run mode
• Idle mode
• Sleep mode
Switching from one power-managed mode to another
begins by loading the OSCCON register. The
SCS1:SCS0 bits select the clock source and determine
which Run or Idle mode is to be used. Changing these
bits causes an immediate switch to the new clock
source, assuming that it is running. The switch may
also be subject to clock transition delays. These are
discussed in Section 3.1.3 “Clock Transitions and
Status Indicators” and subsequent sections.
These modes define which portions of the device are
clocked and at what speed. The Run and Idle modes
may use any of the three available clock sources
(primary, secondary or internal oscillator block); the
Sleep mode does not use a clock source.
The power-managed modes include several
power-saving features offered on previous PIC®
MCUs. One is the clock switching feature, offered in
other PIC18 devices, allowing the controller to use the
Timer1 oscillator in place of the primary oscillator. Also
included is the Sleep mode, offered by all PIC MCUs,
where all device clocks are stopped.
Entry to the power-managed Idle or Sleep modes is
triggered by the execution of a SLEEPinstruction. The
actual mode that results depends on the status of the
IDLEN bit.
Depending on the current mode and the mode being
switched to, a change to a power-managed mode does
not always require setting all of these bits. Many
transitions may be done by changing the oscillator
select bits, or changing the IDLEN bit, prior to issuing a
SLEEP instruction. If the IDLEN bit is already
configured correctly, it may only be necessary to
perform a SLEEP instruction to switch to the desired
mode.
3.1
Selecting Power-Managed Modes
Selecting
a power-managed mode requires two
decisions: if the CPU is to be clocked or not and which
clock source is to be used. The IDLEN bit
(OSCCON<7>) controls CPU clocking, while the
SCS1:SCS0 bits (OSCCON<1:0>) select the clock
source. The individual modes, bit settings, clock
sources and affected modules are summarized in
Table 3-1.
TABLE 3-1:
Mode
POWER-MANAGED MODES
OSCCON bits Module Clocking
IDLEN<7>(1) SCS1:SCS0<1:0> CPU Peripherals
Available Clock and Oscillator Source
Sleep
0
N/A
Off
Off
None – All clocks are disabled
PRI_RUN
N/A
10
Clocked Clocked Primary – HS, EC, HSPLL, ECPLL;
this is the normal, full power execution mode
SEC_RUN
RC_RUN
PRI_IDLE
SEC_IDLE
RC_IDLE
N/A
N/A
1
01
11
10
01
11
Clocked Clocked Secondary – Timer1 Oscillator
Clocked Clocked Internal Oscillator
Off
Off
Off
Clocked Primary – HS, EC, HSPLL, ECPLL
Clocked Secondary – Timer1 Oscillator
Clocked Internal Oscillator
1
1
Note 1: IDLEN reflects its value when the SLEEPinstruction is executed.
© 2007 Microchip Technology Inc.
Preliminary
DS39774C-page 37
PIC18F85J11 FAMILY
3.1.3
CLOCK TRANSITIONS AND STATUS
INDICATORS
3.2
Run Modes
In the Run modes, clocks to both the core and
peripherals are active. The difference between these
modes is the clock source.
The length of the transition between clock sources is
the sum of two cycles of the old clock source and three
to four cycles of the new clock source. This formula
assumes that the new clock source is stable.
3.2.1
PRI_RUN MODE
Two bits indicate the current clock source and its
The PRI_RUN mode is the normal, full power execution
mode of the microcontroller. This is also the default
mode upon a device Reset unless Two-Speed Start-up
is enabled (see Section 22.4 “Two-Speed Start-up”
for details). In this mode, the OSTS bit is set (see
Section 2.2 “Control Registers”).
status:
OSTS
(OSCCON<3>)
and
T1RUN
(T1CON<6>). In general, only one of these bits will be
set while in a given power-managed mode. When the
OSTS bit is set, the primary clock is providing the
device clock. When the T1RUN bit is set, the Timer1
oscillator is providing the clock. If neither of these bits
is set, INTRC is clocking the device.
3.2.2
SEC_RUN MODE
The SEC_RUN mode is the compatible mode to the
“clock switching” feature offered in other PIC18
devices. In this mode, the CPU and peripherals are
clocked from the Timer1 oscillator. This gives users the
option of lower power consumption while still using a
high-accuracy clock source.
Note:
Executing a SLEEP instruction does not
necessarily place the device into Sleep
mode. It acts as the trigger to place the
controller into either the Sleep mode, or
one of the Idle modes, depending on the
setting of the IDLEN bit.
SEC_RUN mode is entered by setting the SCS1:SCS0
bits to ‘01’. The device clock source is switched to the
Timer1 oscillator (see Figure 3-1), the primary oscilla-
tor is shut down, the T1RUN bit (T1CON<6>) is set and
the OSTS bit is cleared.
3.1.4
MULTIPLE SLEEP COMMANDS
The power-managed mode that is invoked with the
SLEEP instruction is determined by the setting of the
IDLEN bit at the time the instruction is executed. If
another SLEEPinstruction is executed, the device will
enter the power-managed mode specified by IDLEN at
that time. If IDLEN has changed, the device will enter
the new power-managed mode specified by the new
setting.
DS39774C-page 38
Preliminary
© 2007 Microchip Technology Inc.
PIC18F85J11 FAMILY
On transitions from SEC_RUN mode to PRI_RUN
mode, the peripherals and CPU continue to be clocked
from the Timer1 oscillator while the primary clock is
started. When the primary clock becomes ready, a
clock switch back to the primary clock occurs (see
Figure 3-2). When the clock switch is complete, the
T1RUN bit is cleared, the OSTS bit is set and the
primary clock is providing the clock. The IDLEN and
SCS bits are not affected by the wake-up; the Timer1
oscillator continues to run.
Note:
The Timer1 oscillator should already be
running prior to entering SEC_RUN mode.
If the T1OSCEN bit is not set when the
SCS1:SCS0 bits are set to ‘01’, entry to
SEC_RUN mode will not occur. If the
Timer1 oscillator is enabled, but not yet
running, device clocks will be delayed until
the oscillator has started. In such situa-
tions, initial oscillator operation is far from
stable and unpredictable operation may
result.
FIGURE 3-1:
TRANSITION TIMING FOR ENTRY TO SEC_RUN MODE
Q1 Q2 Q3 Q4 Q1
Q2
Q3
Q4
Q1
Q2
Q3
1
2
3
n-1
n
T1OSI
OSC1
Clock Transition
CPU
Clock
Peripheral
Clock
Program
Counter
PC
PC + 2
PC + 4
FIGURE 3-2:
TRANSITION TIMING FROM SEC_RUN MODE TO PRI_RUN MODE (HSPLL)
Q1
Q2
Q3
Q4
Q1
Q2 Q3 Q4 Q1 Q2 Q3
T1OSI
OSC1
(1)
TOST
(1)
TPLL
1
2
n-1
n
PLL Clock
Output
Clock
Transition
CPU Clock
Peripheral
Clock
Program
Counter
PC + 2
PC + 4
PC
OSTS bit Set
Note 1: TOST = 1024 TOSC; TPLL = 2 ms (approx). These intervals are not shown to scale.
SCS1:SCS0 bits Changed
© 2007 Microchip Technology Inc.
Preliminary
DS39774C-page 39
PIC18F85J11 FAMILY
On transitions from RC_RUN mode to PRI_RUN mode,
the device continues to be clocked from the INTRC
while the primary clock is started. When the primary
clock becomes ready, a clock switch to the primary
clock occurs (see Figure 3-4). When the clock switch is
complete, the OSTS bit is set and the primary clock is
providing the device clock. The IDLEN and SCS bits
are not affected by the switch. The INTRC source will
continue to run if either the WDT or the Fail-Safe Clock
Monitor is enabled.
3.2.3
RC_RUN MODE
In RC_RUN mode, the CPU and peripherals are
clocked from the internal oscillator; the primary clock is
shut down. This mode provides the best power conser-
vation of all the Run modes while still executing code.
It works well for user applications which are not highly
timing sensitive or do not require high-speed clocks at
all times.
This mode is entered by setting SCS bits to ‘11’. When
the clock source is switched to the INTRC (see
Figure 3-3), the primary oscillator is shut down and the
OSTS bit is cleared.
FIGURE 3-3:
TRANSITION TIMING TO RC_RUN MODE
Q1 Q2 Q3 Q4 Q1
Q2
Q3
Q4
Q1
Q2
Q3
1
2
3
n-1
n
INTRC
OSC1
Clock Transition
CPU
Clock
Peripheral
Clock
Program
Counter
PC
PC + 2
PC + 4
FIGURE 3-4:
TRANSITION TIMING FROM RC_RUN MODE TO PRI_RUN MODE
Q3
Q4
Q1
Q2 Q3 Q4 Q1 Q2 Q3
Q1
Q2
INTRC
OSC1
(1)
TOST
(1)
TPLL
1
2
n-1
n
PLL Clock
Output
Clock
Transition
CPU Clock
Peripheral
Clock
Program
Counter
PC + 2
PC + 4
PC
SCS1:SCS0 bits Changed
OSTS bit Set
Note 1: TOST = 1024 TOSC; TPLL = 2 ms (approx). These intervals are not shown to scale.
DS39774C-page 40
Preliminary
© 2007 Microchip Technology Inc.
PIC18F85J11 FAMILY
3.3
Sleep Mode
3.4
Idle Modes
The power-managed Sleep mode is identical to the
legacy Sleep mode offered in all other PIC micro-
controllers. It is entered by clearing the IDLEN bit (the
default state on device Reset) and executing the
SLEEP instruction. This shuts down the selected
oscillator (Figure 3-5). All clock source status bits are
cleared.
The Idle modes allow the controller’s CPU to be
selectively shut down while the peripherals continue to
operate. Selecting a particular Idle mode allows users
to further manage power consumption.
If the IDLEN bit is set to a ‘1’ when a SLEEPinstruction is
executed, the peripherals will be clocked from the clock
source selected using the SCS1:SCS0 bits; however, the
CPU will not be clocked. The clock source status bits are
not affected. Setting IDLEN and executing a SLEEP
instruction provides a quick method of switching from a
given Run mode to its corresponding Idle mode.
Entering the Sleep mode from any other mode does not
require a clock switch. This is because no clocks are
needed once the controller has entered Sleep. If the
WDT is selected, the INTRC source will continue to
operate. If the Timer1 oscillator is enabled, it will also
continue to run.
If the WDT is selected, the INTRC source will continue
to operate. If the Timer1 oscillator is enabled, it will also
continue to run.
When a wake event occurs in Sleep mode (by interrupt,
Reset or WDT time-out), the device will not be clocked
until the clock source selected by the SCS1:SCS0 bits
becomes ready (see Figure 3-6), or it will be clocked
from the internal oscillator if either the Two-Speed
Start-up or the Fail-Safe Clock Monitor is enabled (see
Section 22.0 “Special Features of the CPU”). In
either case, the OSTS bit is set when the primary clock
is providing the device clocks. The IDLEN and SCS bits
are not affected by the wake-up.
Since the CPU is not executing instructions, the only
exits from any of the Idle modes are by interrupt, WDT
time-out or a Reset. When a wake event occurs, CPU
execution is delayed by an interval of TCSD
(parameter 38, Table 25-10) while it becomes ready to
execute code. When the CPU begins executing code,
it resumes with the same clock source for the current
Idle mode. For example, when waking from RC_IDLE
mode, the internal oscillator block will clock the CPU
and peripherals (in other words, RC_RUN mode). The
IDLEN and SCS bits are not affected by the wake-up.
While in any Idle mode or the Sleep mode, a WDT
time-out will result in a WDT wake-up to the Run mode
currently specified by the SCS1:SCS0 bits.
FIGURE 3-5:
TRANSITION TIMING FOR ENTRY TO SLEEP MODE
Q1 Q2 Q3 Q4 Q1
OSC1
CPU
Clock
Peripheral
Clock
Sleep
Program
Counter
PC
PC + 2
FIGURE 3-6:
TRANSITION TIMING FOR WAKE FROM SLEEP (HSPLL)
Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
Q2 Q3 Q4 Q1 Q2
Q1
OSC1
(1)
(1)
TOST
TPLL
PLL Clock
Output
CPU Clock
Peripheral
Clock
Program
Counter
PC
PC + 2
PC + 4
PC + 6
Wake Event
OSTS bit Set
Note 1: TOST = 1024 TOSC; TPLL = 2 ms (approx). These intervals are not shown to scale.
© 2007 Microchip Technology Inc.
Preliminary
DS39774C-page 41
PIC18F85J11 FAMILY
3.4.1
PRI_IDLE MODE
3.4.2
SEC_IDLE MODE
This mode is unique among the three low-power Idle
modes, in that it does not disable the primary device
clock. For timing sensitive applications, this allows for
the fastest resumption of device operation with its more
accurate primary clock source, since the clock source
does not have to “warm up” or transition from another
oscillator.
In SEC_IDLE mode, the CPU is disabled but the
peripherals continue to be clocked from the Timer1
oscillator. This mode is entered from SEC_RUN by set-
ting the IDLEN bit and executing a SLEEPinstruction. If
the device is in another Run mode, set IDLEN first, then
set SCS1:SCS0 to ‘01’ and execute SLEEP. When the
clock source is switched to the Timer1 oscillator, the
primary oscillator is shut down, the OSTS bit is cleared
and the T1RUN bit is set.
PRI_IDLE mode is entered from PRI_RUN mode by
setting the IDLEN bit and executing a SLEEPinstruc-
tion. If the device is in another Run mode, set IDLEN
first, then set the SCS bits to ‘10’ and execute SLEEP.
Although the CPU is disabled, the peripherals continue
to be clocked from the primary clock source specified
by the FOSC1:FOSC0 Configuration bits. The OSTS
bit remains set (see Figure 3-7).
When a wake event occurs, the peripherals continue to
be clocked from the Timer1 oscillator. After an interval
of TCSD following the wake event, the CPU begins exe-
cuting code being clocked by the Timer1 oscillator. The
IDLEN and SCS bits are not affected by the wake-up;
the Timer1 oscillator continues to run (see Figure 3-8).
When a wake event occurs, the CPU is clocked from the
primary clock source. A delay of interval TCSD is
required between the wake event and when code exe-
cution starts. This is required to allow the CPU to
become ready to execute instructions. After the
wake-up, the OSTS bit remains set. The IDLEN and
SCS bits are not affected by the wake-up (see
Figure 3-8).
Note:
The Timer1 oscillator should already be
running prior to entering SEC_IDLE mode.
If the T1OSCEN bit is not set when the
SLEEPinstruction is executed, the SLEEP
instruction will be ignored and entry to
SEC_IDLE mode will not occur. If the
Timer1 oscillator is enabled, but not yet
running, peripheral clocks will be delayed
until the oscillator has started. In such
situations, initial oscillator operation is far
from stable and unpredictable operation
may result.
FIGURE 3-7:
TRANSITION TIMING FOR ENTRY TO IDLE MODE
Q3
Q4
Q1
Q1
Q2
OSC1
CPU Clock
Peripheral
Clock
Program
Counter
PC
PC + 2
FIGURE 3-8:
TRANSITION TIMING FOR WAKE FROM IDLE TO RUN MODE
Q1
Q3
Q4
Q2
OSC1
TCSD
CPU Clock
Peripheral
Clock
Program
Counter
PC
Wake Event
DS39774C-page 42
Preliminary
© 2007 Microchip Technology Inc.
PIC18F85J11 FAMILY
3.4.3
RC_IDLE MODE
3.5.2
EXIT BY WDT TIME-OUT
In RC_IDLE mode, the CPU is disabled but the periph-
erals continue to be clocked from the internal oscillator.
This mode allows for controllable power conservation
during Idle periods.
A WDT time-out will cause different actions depending
on which power-managed mode the device is in when
the time-out occurs.
If the device is not executing code (all Idle modes and
Sleep mode), the time-out will result in an exit from the
power-managed mode (see Section 3.2 “Run
Modes” and Section 3.3 “Sleep Mode”). If the device
is executing code (all Run modes), the time-out will
result in a WDT Reset (see Section 22.2 “Watchdog
Timer (WDT)”).
From RC_RUN, this mode is entered by setting the
IDLEN bit and executing a SLEEP instruction. If the
device is in another Run mode, first set IDLEN, then
clear the SCS bits and execute SLEEP. When the clock
source is switched to the INTRC, the primary oscillator
is shut down and the OSTS bit is cleared.
When a wake event occurs, the peripherals continue to
be clocked from the INTOSC. After a delay of TCSD
following the wake event, the CPU begins executing
code being clocked by the INTOSC. The IDLEN and
SCS bits are not affected by the wake-up. The INTOSC
source will continue to run if either the WDT or the
Fail-Safe Clock Monitor is enabled.
The Watchdog Timer and postscaler are cleared by one
of the following events:
• executing a SLEEPor CLRWDTinstruction
• the loss of a currently selected clock source (if the
Fail-Safe Clock Monitor is enabled)
3.5.3
EXIT BY RESET
Exiting an Idle or Sleep mode by Reset automatically
forces the device to run from the INTRC.
3.5
Exiting Idle and Sleep Modes
An exit from Sleep mode, or any of the Idle modes, is
triggered by an interrupt, a Reset or a WDT time-out.
This section discusses the triggers that cause exits
from power-managed modes. The clocking subsystem
actions are discussed in each of the power-managed
mode sections (see Section 3.2 “Run Modes”,
Section 3.3 “Sleep Mode” and Section 3.4 “Idle
Modes”).
3.5.4
EXIT WITHOUT AN OSCILLATOR
START-UP DELAY
Certain exits from power-managed modes do not
invoke the OST at all. There are two cases:
• PRI_IDLE mode, where the primary clock source
is not stopped; and
• the primary clock source is either the EC or
ECPLL mode.
3.5.1
EXIT BY INTERRUPT
Any of the available interrupt sources can cause the
device to exit from an Idle mode, or the Sleep mode, to
a Run mode. To enable this functionality, an interrupt
source must be enabled by setting its enable bit in one
of the INTCON or PIE registers. The exit sequence is
initiated when the corresponding interrupt flag bit is set.
In these instances, the primary clock source either
does not require an oscillator start-up delay, since it is
already running (PRI_IDLE), or normally does not
require an oscillator start-up delay (EC). However, a
fixed delay of interval TCSD following the wake event is
still required when leaving Sleep and Idle modes to
allow the CPU to prepare for execution. Instruction
execution resumes on the first clock cycle following this
delay.
On all exits from Idle or Sleep modes by interrupt, code
execution branches to the interrupt vector if the
GIE/GIEH bit (INTCON<7>) is set. Otherwise, code
execution continues or resumes without branching
(see Section 9.0 “Interrupts”).
A fixed delay of interval TCSD following the wake event
is required when leaving Sleep and Idle modes. This
delay is required for the CPU to prepare for execution.
Instruction execution resumes on the first clock cycle
following this delay.
© 2007 Microchip Technology Inc.
Preliminary
DS39774C-page 43
PIC18F85J11 FAMILY
NOTES:
DS39774C-page 44
Preliminary
© 2007 Microchip Technology Inc.
PIC18F85J11 FAMILY
4.1
RCON Register
4.0
RESET
Device Reset events are tracked through the RCON
register (Register 4-1). The lower five bits of the
register indicate that a specific Reset event has
occurred. In most cases, these bits can only be set by
the event and must be cleared by the application after
the event. The state of these flag bits, taken together,
can be read to indicate the type of Reset that just
occurred. This is described in more detail in
Section 4.7 “Reset State of Registers”.
The PIC18F85J11 family of devices differentiate
between various kinds of Reset:
a) Power-on Reset (POR)
b) MCLR Reset during normal operation
c) MCLR Reset during power-managed modes
d) Watchdog Timer (WDT) Reset (during
execution)
e) Brown-out Reset (BOR)
f) RESETInstruction
The RCON register also has a control bit for setting
interrupt priority (IPEN). Interrupt priority is discussed
in Section 9.0 “Interrupts”.
g) Stack Full Reset
h) Stack Underflow Reset
This section discusses Resets generated by MCLR,
POR and BOR, and covers the operation of the various
start-up timers. Stack Reset events are covered in
Section 5.1.6.4 “Stack Full and Underflow Resets”.
WDT Resets are covered in Section 22.2 “Watchdog
Timer (WDT)”.
A simplified block diagram of the on-chip Reset circuit
is shown in Figure 4-1.
FIGURE 4-1:
SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT
RESET
Instruction
Stack Full/Underflow Reset
External Reset
Stack
Pointer
MCLR
( )_IDLE
Sleep
WDT
Time-out
VDD Rise
Detect
POR Pulse
VDD
Brown-out
(1)
Reset
S
PWRT
32 μs
Chip_Reset
65.5 ms
PWRT
11-bit Ripple Counter
R
Q
INTRC
Note 1: The ENVREG pin must be tied high to enable Brown-out Reset. The Brown-out Reset is provided by the on-chip
voltage regulator when there is insufficient source voltage to maintain regulation.
© 2007 Microchip Technology Inc.
Preliminary
DS39774C-page 45
PIC18F85J11 FAMILY
REGISTER 4-1:
RCON: RESET CONTROL REGISTER
R/W-0
IPEN
U-0
—
R/W-1
CM
R/W-1
RI
R-1
TO
R-1
PD
R/W-0
POR
R/W-0
BOR
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7
IPEN: Interrupt Priority Enable bit
1= Enable priority levels on interrupts
0= Disable priority levels on interrupts (PIC16XXXX Compatibility mode)
bit 6
bit 5
Unimplemented: Read as ‘0’
CM: Configuration Mismatch Flag bit
1= A configuration mismatch Reset has not occurred
0= A configuration mismatch Reset occurred. Must be set in software once the reset occurs.
bit 4
RI: RESETInstruction Flag bit
1= The RESETinstruction was not executed (set by firmware only)
0= The RESET instruction was executed causing a device Reset (must be set in software after a
Brown-out Reset occurs)
bit 3
bit 2
bit 1
bit 0
TO: Watchdog Time-out Flag bit
1= Set by power-up, CLRWDTinstruction or SLEEPinstruction
0= A WDT time-out occurred
PD: Power-Down Detection Flag bit
1= Set by power-up or by the CLRWDTinstruction
0= Set by execution of the SLEEPinstruction
POR: Power-on Reset Status bit
1= A Power-on Reset has not occurred (set by firmware only)
0= A Power-on Reset occurred (must be set in software after a Power-on Reset occurs)
BOR: Brown-out Reset Status bit
1= A Brown-out Reset has not occurred (set by firmware only)
0= A Brown-out Reset occurred (must be set in software after a Brown-out Reset occurs)
Note 1: It is recommended that the POR bit be set after a Power-on Reset has been detected so that subsequent
Power-on Resets may be detected.
2: If the on-chip voltage regulator is disabled, BOR remains ‘0’ at all times. See Section 4.4.1 “Detecting
BOR” for more information.
3: Brown-out Reset is said to have occurred when BOR is ‘0’ and POR is ‘1’ (assuming that POR was set to
‘1’ by software immediately after a Power-on Reset).
DS39774C-page 46
Preliminary
© 2007 Microchip Technology Inc.
PIC18F85J11 FAMILY
FIGURE 4-2:
EXTERNAL POWER-ON
RESET CIRCUIT (FOR
SLOW VDD POWER-UP)
4.2
Master Clear (MCLR)
The MCLR pin provides a method for triggering a hard
external Reset of the device. A Reset is generated by
holding the pin low. PIC18 extended microcontroller
devices have a noise filter in the MCLR Reset path
which detects and ignores small pulses.
VDD
VDD
D
R
The MCLR pin is not driven low by any internal Resets,
including the WDT.
R1
MCLR
PIC18F85J11
C
4.3
Power-on Reset (POR)
A Power-on Reset condition is generated on-chip
whenever VDD rises above a certain threshold. This
allows the device to start in the initialized state when
VDD is adequate for operation.
Note 1: External Power-on Reset circuit is required
only if the VDD power-up slope is too slow.
The diode D helps discharge the capacitor
quickly when VDD powers down.
To take advantage of the POR circuitry, tie the MCLR
pin through a resistor (1 kΩ to 10 kΩ) to VDD. This will
eliminate external RC components usually needed to
create a Power-on Reset delay. A minimum rise rate for
VDD is specified (parameter D004). For a slow rise
time, see Figure 4-2.
2: R < 40 kΩ is recommended to make sure that
the voltage drop across R does not violate
the device’s electrical specification.
3: R1 ≥ 1 kΩ will limit any current flowing into
MCLR from external capacitor C, in the event
of MCLR/VPP pin breakdown, due to
Electrostatic Discharge (ESD) or Electrical
Overstress (EOS).
When the device starts normal operation (i.e., exits the
Reset condition), device operating parameters
(voltage, frequency, temperature, etc.) must be met to
ensure operation. If these conditions are not met, the
device must be held in Reset until the operating
conditions are met.
4.4.1
DETECTING BOR
The BOR bit always resets to ‘0’ on any Brown-out
Reset or Power-on Reset event. This makes it difficult
to determine if a Brown-out Reset event has occurred
just by reading the state of BOR alone. A more reliable
method is to simultaneously check the state of both
POR and BOR. This assumes that the POR bit is reset
to ‘1’ in software immediately after any Power-on Reset
event. If BOR is ‘0’ while POR is ‘1’, it can be reliably
assumed that a Brown-out Reset event has occurred.
Power-on Reset events are captured by the POR bit
(RCON<1>). The state of the bit is set to ‘0’ whenever
a Power-on Reset occurs; it does not change for any
other Reset event. POR is not reset to ‘1’ by any
hardware event. To capture multiple events, the user
manually resets the bit to ‘1’ in software following any
Power-on Reset.
If the voltage regulator is disabled, Brown-out Reset
functionality is disabled. In this case, the BOR bit
cannot be used to determine a Brown-out Reset event.
The BOR bit is still cleared by a Power-on Reset event.
4.4
Brown-out Reset (BOR)
The PIC18F85J11 family of devices incorporates a
simple BOR function when the internal regulator is
enabled (ENVREG pin is tied to VDD). The voltage reg-
ulator will trigger a Brown-out Reset when output of the
regulator to the device core approaches the voltage at
which the device is unable to run at full speed. The
BOR circuit also keeps the device in Reset as VDD
rises, until the regulator’s output level is sufficient for
full-speed operation.
Once a BOR has occurred, the Power-up Timer will
keep the chip in Reset for TPWRT (parameter 33). If
VDD drops below the threshold for full-speed operation
while the Power-up Timer is running, the chip will go
back into a Brown-out Reset and the Power-up Timer
will be initialized. Once VDD rises to the point where
regulator output is sufficient, the Power-up Timer will
execute the additional time delay.
© 2007 Microchip Technology Inc.
Preliminary
DS39774C-page 47
PIC18F85J11 FAMILY
4.5
Configuration Mismatch (CM)
4.6
Power-up Timer (PWRT)
The Configuration Mismatch (CM) Reset is designed to
detect and attempt to recover from random, memory
corrupting events. These include Electrostatic Dis-
charge (ESD) events, which can cause widespread,
single bit changes throughout the device and result in
catastrophic failure.
PIC18F85J11 family devices incorporate an on-chip
Power-up Timer (PWRT) to help regulate the Power-on
Reset process. The PWRT is always enabled. The
main function is to ensure that the device voltage is
stable before code is executed.
The Power-up Timer (PWRT) of the PIC18F85J11 fam-
ily devices is an 11-bit counter which uses the INTRC
source as the clock input. This yields an approximate
time interval of 2048 x 32 µs = 65.6 ms. While the
PWRT is counting, the device is held in Reset.
In PIC18FXXJXX Flash devices, the device Configura-
tion registers (located in the configuration memory
space) are continuously monitored during operation by
comparing their values to complimentary Shadow
registers.
The power-up time delay depends on the INTRC clock
and will vary from chip-to-chip due to temperature and
process variation. See DC parameter 33 for details.
If a mismatch is detected between the two sets of reg-
isters, a CM Reset automatically occurs. These events
are captured by the CM bit (RCON<5>) being set to ‘0’.
This bit does not change for any other Reset event.
4.6.1
TIME-OUT SEQUENCE
If enabled, the PWRT time-out is invoked after the POR
pulse has cleared. The total time-out will vary based on
the status of the PWRT. Figure 4-3, Figure 4-4,
Figure 4-5 and Figure 4-6 all depict time-out
sequences on power-up with the Power-up Timer
enabled.
A CM Reset behaves similarly to a Master Clear Reset,
RESET instruction, WDT time-out or Stack Event
Resets. As with all hard and power Reset events, the
device Configuration Words are reloaded from the
Flash Configuration Words in program memory as the
device restarts.
Since the time-outs occur from the POR pulse, if MCLR
is kept low long enough, the PWRT will expire. Bringing
MCLR high will begin execution immediately
(Figure 4-5). This is useful for testing purposes, or to
synchronize more than one PIC18FXXXX device
operating in parallel.
FIGURE 4-3:
TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD, VDD RISE < TPWRT)
VDD
MCLR
INTERNAL POR
TPWRT
PWRT TIME-OUT
INTERNAL RESET
DS39774C-page 48
Preliminary
© 2007 Microchip Technology Inc.
PIC18F85J11 FAMILY
FIGURE 4-4:
TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 1
VDD
MCLR
INTERNAL POR
TPWRT
PWRT TIME-OUT
INTERNAL RESET
FIGURE 4-5:
TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 2
VDD
MCLR
INTERNAL POR
TPWRT
PWRT TIME-OUT
INTERNAL RESET
FIGURE 4-6:
SLOW RISE TIME (MCLR TIED TO VDD, VDD RISE > TPWRT)
3.3V
0V
1V
VDD
MCLR
INTERNAL POR
TPWRT
PWRT TIME-OUT
INTERNAL RESET
© 2007 Microchip Technology Inc.
Preliminary
DS39774C-page 49
PIC18F85J11 FAMILY
Table 4-2 describes the Reset states for all of the
Special Function Registers. These are categorized by
Power-on and Brown-out Resets, Master Clear and
WDT Resets and WDT wake-ups.
4.7
Reset State of Registers
Most registers are unaffected by a Reset. Their status
is unknown on POR and unchanged by all other
Resets. The other registers are forced to a “Reset
state” depending on the type of Reset that occurred.
Most registers are not affected by a WDT wake-up,
since this is viewed as the resumption of normal
operation. Status bits from the RCON register, CM, RI,
TO, PD, POR and BOR, are set or cleared differently in
different Reset situations, as indicated in Table 4-1.
These bits are used in software to determine the nature
of the Reset.
TABLE 4-1:
STATUS BITS, THEIR SIGNIFICANCE AND THE INITIALIZATION CONDITION FOR
RCON REGISTER
RCON Register
STKPTR Register
Program
Condition
Counter(1)
CM
RI
TO
PD
POR BOR STKFUL STKUNF
Power-on Reset
RESETInstruction
Brown-out Reset
0000h
0000h
0000h
0000h
1
u
1
u
1
0
1
u
1
u
1
1
1
u
1
u
0
u
u
u
0
u
0
u
0
u
u
u
0
u
u
u
MCLR during power-managed
Run modes
MCLR during power-managed
Idle modes and Sleep mode
0000h
0000h
0000h
u
u
u
u
1
0
u
0
u
u
u
u
u
u
u
u
u
u
u
u
u
u
WDT time-out during full power
or power-managed Run modes
u
u
MCLR during full power
execution
Stack Full Reset (STVREN = 1)
0000h
0000h
u
u
u
u
u
u
u
u
u
u
1
u
u
1
u
u
Stack Underflow Reset
(STVREN = 1)
Stack Underflow Error (not an
actual Reset, STVREN = 0)
0000h
u
u
u
u
u
0
u
0
u
u
u
u
u
u
1
u
WDT time-out during
power-managed Idle or Sleep
modes
PC + 2
Interrupt exit from
PC + 2
u
u
u
0
u
u
u
u
power-managed modes
Legend: u= unchanged
Note 1: When the wake-up is due to an interrupt and the GIEH or GIEL bit is set, the PC is loaded with the
interrupt vector (0008h or 0018h).
DS39774C-page 50
Preliminary
© 2007 Microchip Technology Inc.
PIC18F85J11 FAMILY
TABLE 4-2:
Register
INITIALIZATION CONDITIONS FOR ALL REGISTERS
MCLR Resets
WDT Reset
RESETInstruction
Stack Resets
CM Resets
Power-on Reset,
Brown-out Reset
Wake-up via WDT
or Interrupt
Applicable Devices
TOSU
PIC18F6XJ11 PIC18F8XJ11
PIC18F6XJ11 PIC18F8XJ11
PIC18F6XJ11 PIC18F8XJ11
PIC18F6XJ11 PIC18F8XJ11
PIC18F6XJ11 PIC18F8XJ11
PIC18F6XJ11 PIC18F8XJ11
PIC18F6XJ11 PIC18F8XJ11
PIC18F6XJ11 PIC18F8XJ11
PIC18F6XJ11 PIC18F8XJ11
PIC18F6XJ11 PIC18F8XJ11
PIC18F6XJ11 PIC18F8XJ11
PIC18F6XJ11 PIC18F8XJ11
PIC18F6XJ11 PIC18F8XJ11
PIC18F6XJ11 PIC18F8XJ11
PIC18F6XJ11 PIC18F8XJ11
PIC18F6XJ11 PIC18F8XJ11
PIC18F6XJ11 PIC18F8XJ11
PIC18F6XJ11 PIC18F8XJ11
PIC18F6XJ11 PIC18F8XJ11
PIC18F6XJ11 PIC18F8XJ11
PIC18F6XJ11 PIC18F8XJ11
PIC18F6XJ11 PIC18F8XJ11
PIC18F6XJ11 PIC18F8XJ11
PIC18F6XJ11 PIC18F8XJ11
PIC18F6XJ11 PIC18F8XJ11
PIC18F6XJ11 PIC18F8XJ11
PIC18F6XJ11 PIC18F8XJ11
PIC18F6XJ11 PIC18F8XJ11
PIC18F6XJ11 PIC18F8XJ11
---0 0000
0000 0000
0000 0000
uu-0 0000
---0 0000
0000 0000
0000 0000
--00 0000
0000 0000
0000 0000
0000 0000
xxxx xxxx
xxxx xxxx
0000 000x
1111 1111
1100 0000
N/A
---0 0000
0000 0000
0000 0000
00-0 0000
---0 0000
0000 0000
0000 0000
--00 0000
0000 0000
0000 0000
0000 0000
uuuu uuuu
uuuu uuuu
0000 000u
1111 1111
1100 0000
N/A
---0 uuuu(1)
uuuu uuuu(1)
uuuu uuuu(1)
uu-u uuuu(1)
---u uuuu
uuuu uuuu
PC + 2(2)
--uu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu(3)
uuuu uuuu(3)
uuuu uuuu(3)
N/A
TOSH
TOSL
STKPTR
PCLATU
PCLATH
PCL
TBLPTRU
TBLPTRH
TBLPTRL
TABLAT
PRODH
PRODL
INTCON
INTCON2
INTCON3
INDF0
POSTINC0
POSTDEC0
PREINC0
PLUSW0
FSR0H
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
---- xxxx
xxxx xxxx
xxxx xxxx
N/A
---- uuuu
uuuu uuuu
uuuu uuuu
N/A
---- uuuu
uuuu uuuu
uuuu uuuu
N/A
FSR0L
WREG
INDF1
POSTINC1
POSTDEC1
PREINC1
PLUSW1
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
Legend: u= unchanged, x= unknown, -= unimplemented bit, read as ‘0’, q= value depends on condition.
Shaded cells indicate conditions do not apply for the designated device.
Note 1: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are
updated with the current value of the PC. The STKPTR is modified to point to the next location in the
hardware stack.
2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt
vector (0008h or 0018h).
3: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).
4: See Table 4-1 for Reset value for specific condition.
5: Bits 6 and 7 of PORTA, LATA and TRISA are enabled depending on the oscillator mode selected. When
not enabled as PORTA pins, they are disabled and read as ‘0’.
© 2007 Microchip Technology Inc.
Preliminary
DS39774C-page 51
PIC18F85J11 FAMILY
TABLE 4-2:
INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)
MCLR Resets
WDT Reset
RESETInstruction
Stack Resets
CM Resets
Power-on Reset,
Brown-out Reset
Wake-up via WDT
or Interrupt
Register
Applicable Devices
FSR1H
PIC18F6XJ11 PIC18F8XJ11
PIC18F6XJ11 PIC18F8XJ11
PIC18F6XJ11 PIC18F8XJ11
PIC18F6XJ11 PIC18F8XJ11
PIC18F6XJ11 PIC18F8XJ11
PIC18F6XJ11 PIC18F8XJ11
PIC18F6XJ11 PIC18F8XJ11
PIC18F6XJ11 PIC18F8XJ11
PIC18F6XJ11 PIC18F8XJ11
PIC18F6XJ11 PIC18F8XJ11
PIC18F6XJ11 PIC18F8XJ11
PIC18F6XJ11 PIC18F8XJ11
PIC18F6XJ11 PIC18F8XJ11
PIC18F6XJ11 PIC18F8XJ11
PIC18F6XJ11 PIC18F8XJ11
PIC18F6XJ11 PIC18F8XJ11
PIC18F6XJ11 PIC18F8XJ11
PIC18F6XJ11 PIC18F8XJ11
PIC18F6XJ11 PIC18F8XJ11
PIC18F6XJ11 PIC18F8XJ11
PIC18F6XJ11 PIC18F8XJ11
PIC18F6XJ11 PIC18F8XJ11
PIC18F6XJ11 PIC18F8XJ11
PIC18F6XJ11 PIC18F8XJ11
PIC18F6XJ11 PIC18F8XJ11
PIC18F6XJ11 PIC18F8XJ11
PIC18F6XJ11 PIC18F8XJ11
PIC18F6XJ11 PIC18F8XJ11
---- xxxx
xxxx xxxx
---- 0000
N/A
---- uuuu
uuuu uuuu
---- 0000
N/A
---- uuuu
uuuu uuuu
---- uuuu
N/A
FSR1L
BSR
INDF2
POSTINC2
POSTDEC2
PREINC2
PLUSW2
FSR2H
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
---- xxxx
xxxx xxxx
---x xxxx
0000 0000
xxxx xxxx
1111 1111
0100 q000
0--- ---0
0-11 11q0
xxxx xxxx
xxxx xxxx
0000 0000
0000 0000
1111 1111
-000 0000
xxxx xxxx
0000 0000
0000 0000
0000 0000
0000 0000
---- uuuu
uuuu uuuu
---u uuuu
0000 0000
uuuu uuuu
1111 1111
0100 q000
0--- ---0
0-uq qquu
uuuu uuuu
uuuu uuuu
u0uu uuuu
0000 0000
1111 1111
-000 0000
uuuu uuuu
0000 0000
0000 0000
0000 0000
0000 0000
---- uuuu
uuuu uuuu
---u uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu quuu
u--- ---u
u-uu qquu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
1111 1111
-uuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
FSR2L
STATUS
TMR0H
TMR0L
T0CON
OSCCON
WDTCON
RCON(4)
TMR1H
TMR1L
T1CON
TMR2
PR2
T2CON
SSPBUF
SSPADD
SSPSTAT
SSPCON1
SSPCON2
Legend: u= unchanged, x= unknown, -= unimplemented bit, read as ‘0’, q= value depends on condition.
Shaded cells indicate conditions do not apply for the designated device.
Note 1: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are
updated with the current value of the PC. The STKPTR is modified to point to the next location in the
hardware stack.
2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt
vector (0008h or 0018h).
3: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).
4: See Table 4-1 for Reset value for specific condition.
5: Bits 6 and 7 of PORTA, LATA and TRISA are enabled depending on the oscillator mode selected. When
not enabled as PORTA pins, they are disabled and read as ‘0’.
DS39774C-page 52
Preliminary
© 2007 Microchip Technology Inc.
PIC18F85J11 FAMILY
TABLE 4-2:
Register
INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)
MCLR Resets
WDT Reset
RESETInstruction
Stack Resets
CM Resets
Power-on Reset,
Brown-out Reset
Wake-up via WDT
or Interrupt
Applicable Devices
ADRESH
ADRESL
ADCON0
ADCON1
ADCON2
CVRCON
CMCON
TMR3H
TMR3L
T3CON
PSPCON
SPBRG1
RCREG1
TXREG1
TXSTA1
RCSTA1
EECON2
EECON1
IPR3
PIC18F6XJ11 PIC18F8XJ11
PIC18F6XJ11 PIC18F8XJ11
PIC18F6XJ11 PIC18F8XJ11
PIC18F6XJ11 PIC18F8XJ11
PIC18F6XJ11 PIC18F8XJ11
PIC18F6XJ11 PIC18F8XJ11
PIC18F6XJ11 PIC18F8XJ11
PIC18F6XJ11 PIC18F8XJ11
PIC18F6XJ11 PIC18F8XJ11
PIC18F6XJ11 PIC18F8XJ11
PIC18F6XJ11 PIC18F8XJ11
PIC18F6XJ11 PIC18F8XJ11
PIC18F6XJ11 PIC18F8XJ11
PIC18F6XJ11 PIC18F8XJ11
PIC18F6XJ11 PIC18F8XJ11
PIC18F6XJ11 PIC18F8XJ11
PIC18F6XJ11 PIC18F8XJ11
PIC18F6XJ11 PIC18F8XJ11
PIC18F6XJ11 PIC18F8XJ11
PIC18F6XJ11 PIC18F8XJ11
PIC18F6XJ11 PIC18F8XJ11
PIC18F6XJ11 PIC18F8XJ11
PIC18F6XJ11 PIC18F8XJ11
PIC18F6XJ11 PIC18F8XJ11
PIC18F6XJ11 PIC18F8XJ11
PIC18F6XJ11 PIC18F8XJ11
PIC18F6XJ11 PIC18F8XJ11
PIC18F6XJ11 PIC18F8XJ11
PIC18F6XJ11 PIC18F8XJ11
xxxx xxxx
xxxx xxxx
0-00 0000
--00 0000
0-00 0000
0000 0000
0000 0111
xxxx xxxx
xxxx xxxx
0000 0000
0000 ----
0000 0000
0000 0000
0000 0000
0000 0010
0000 000x
---- ----
---0 x00-
--00 -11-
--00 -00-
--00 -00-
11-- 111-
00-- 000-
00-- 000-
1111 1-11
0000 0-00
0000 0-00
0-00 --00
0000 0000
uuuu uuuu
uuuu uuuu
0-00 0000
--00 0000
0-00 0000
0000 0000
0000 0111
uuuu uuuu
uuuu uuuu
uuuu uuuu
0000 ----
0000 0000
0000 0000
0000 0000
0000 0010
0000 000x
---- ----
---0 u00-
--00 -11-
--00 -00-
--00 -00-
11-- 111-
00-- 000-
00-- 000-
1111 1-11
0000 0-00
0000 0-00
0-00 --00
0000 0000
uuuu uuuu
uuuu uuuu
u-uu uuuu
--uu uuuu
u-uu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu ----
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
---- ----
---0 u00-
--uu -uu-
--uu -00-(3)
--uu -00-
uu-- uuu-
uu-- uuu-(3)
uu-- uuu-
uuuu u-uu
uuuu u-uu(3)
uuuu u-uu
u-uu --uu
uuuu uuuu
PIR3
PIE3
IPR2
PIR2
PIE2
IPR1
PIR1
PIE1
MEMCON
OSCTUNE
Legend: u= unchanged, x= unknown, -= unimplemented bit, read as ‘0’, q= value depends on condition.
Shaded cells indicate conditions do not apply for the designated device.
Note 1: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are
updated with the current value of the PC. The STKPTR is modified to point to the next location in the
hardware stack.
2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt
vector (0008h or 0018h).
3: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).
4: See Table 4-1 for Reset value for specific condition.
5: Bits 6 and 7 of PORTA, LATA and TRISA are enabled depending on the oscillator mode selected. When
not enabled as PORTA pins, they are disabled and read as ‘0’.
© 2007 Microchip Technology Inc.
Preliminary
DS39774C-page 53
PIC18F85J11 FAMILY
TABLE 4-2:
INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)
MCLR Resets
WDT Reset
RESETInstruction
Stack Resets
CM Resets
Power-on Reset,
Brown-out Reset
Wake-up via WDT
or Interrupt
Register
Applicable Devices
TRISJ
PIC18F6XJ11 PIC18F8XJ11
PIC18F6XJ11 PIC18F8XJ11
PIC18F6XJ11 PIC18F8XJ11
PIC18F6XJ11 PIC18F8XJ11
PIC18F6XJ11 PIC18F8XJ11
PIC18F6XJ11 PIC18F8XJ11
PIC18F6XJ11 PIC18F8XJ11
PIC18F6XJ11 PIC18F8XJ11
PIC18F6XJ11 PIC18F8XJ11
PIC18F6XJ11 PIC18F8XJ11
PIC18F6XJ11 PIC18F8XJ11
PIC18F6XJ11 PIC18F8XJ11
PIC18F6XJ11 PIC18F8XJ11
PIC18F6XJ11 PIC18F8XJ11
PIC18F6XJ11 PIC18F8XJ11
PIC18F6XJ11 PIC18F8XJ11
PIC18F6XJ11 PIC18F8XJ11
PIC18F6XJ11 PIC18F8XJ11
PIC18F6XJ11 PIC18F8XJ11
PIC18F6XJ11 PIC18F8XJ11
PIC18F6XJ11 PIC18F8XJ11
PIC18F6XJ11 PIC18F8XJ11
PIC18F6XJ11 PIC18F8XJ11
PIC18F6XJ11 PIC18F8XJ11
PIC18F6XJ11 PIC18F8XJ11
PIC18F6XJ11 PIC18F8XJ11
PIC18F6XJ11 PIC18F8XJ11
PIC18F6XJ11 PIC18F8XJ11
PIC18F6XJ11 PIC18F8XJ11
PIC18F6XJ11 PIC18F8XJ11
PIC18F6XJ11 PIC18F8XJ11
PIC18F6XJ11 PIC18F8XJ11
1111 1111
1111 1111
0001 1111
1111 111-
1111 1-11
1111 1111
1111 1111
1111 1111
1111 1111(5)
xxxx xxxx
xxxx xxxx
00-x xxxx
xxxx xxx-
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx(5)
xxxx xxxx
xxxx xxxx
000x xxxx
xxxx xxx-
xxxx x-xx
xxxx xxxx
xxxx xxxx
xxxx xxxx
xx0x 0000(5)
0000 0000
01-0 0-00
xxxx xxxx
xxxx xxxx
--00 0000
1111 1111
1111 1111
0001 1111
1111 111-
1111 1-11
1111 1111
1111 1111
1111 1111
1111 1111(5)
uuuu uuuu
uuuu uuuu
00-u uuuu
uuuu uuu-
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu(5)
uuuu uuuu
uuuu uuuu
000u uuuu
uuuu uuu-
uuuu u-uu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uu0u 0000(5)
0000 0000
01-0 0-00
uuuu uuuu
uuuu uuuu
--00 0000
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuu-
uuuu u-uu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu(5)
uuuu uuuu
uuuu uuuu
uu-u uuuu
uuuu uuu-
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu(5)
uuuu uuuu
uuuu uuuu
000u uuuu
uuuu uuu-
uuuu u-uu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu(5)
uuuu uuuu
uu-u u-uu
uuuu uuuu
uuuu uuuu
--uu uuuu
TRISH
TRISG
TRISF
TRISE
TRISD
TRISC
TRISB
TRISA(5)
LATJ
LATH
LATG
LATF
LATE
LATD
LATC
LATB
LATA(5)
PORTJ
PORTH
PORTG
PORTF
PORTE
PORTD
PORTC
PORTB
PORTA(5)
SPBRGH1
BAUDCON1
CCPR1H
CCPR1L
CCP1CON
Legend: u= unchanged, x= unknown, -= unimplemented bit, read as ‘0’, q= value depends on condition.
Shaded cells indicate conditions do not apply for the designated device.
Note 1: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are
updated with the current value of the PC. The STKPTR is modified to point to the next location in the
hardware stack.
2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt
vector (0008h or 0018h).
3: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).
4: See Table 4-1 for Reset value for specific condition.
5: Bits 6 and 7 of PORTA, LATA and TRISA are enabled depending on the oscillator mode selected. When
not enabled as PORTA pins, they are disabled and read as ‘0’.
DS39774C-page 54
Preliminary
© 2007 Microchip Technology Inc.
PIC18F85J11 FAMILY
TABLE 4-2:
Register
INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)
MCLR Resets
WDT Reset
RESETInstruction
Stack Resets
CM Resets
Power-on Reset,
Brown-out Reset
Wake-up via WDT
or Interrupt
Applicable Devices
CCPR2H
CCPR2L
CCP2CON
SPBRG2
RCREG2
TXREG2
TXSTA2
PIC18F6XJ11 PIC18F8XJ11
PIC18F6XJ11 PIC18F8XJ11
PIC18F6XJ11 PIC18F8XJ11
PIC18F6XJ11 PIC18F8XJ11
PIC18F6XJ11 PIC18F8XJ11
PIC18F6XJ11 PIC18F8XJ11
PIC18F6XJ11 PIC18F8XJ11
PIC18F6XJ11 PIC18F8XJ11
xxxx xxxx
xxxx xxxx
--00 0000
0000 0000
0000 0000
0000 0000
0000 -010
0000 000x
uuuu uuuu
uuuu uuuu
--00 0000
0000 0000
0000 0000
0000 0000
0000 -010
0000 000x
uuuu uuuu
uuuu uuuu
--uu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu -uuu
uuuu uuuu
RCSTA2
Legend: u= unchanged, x= unknown, -= unimplemented bit, read as ‘0’, q= value depends on condition.
Shaded cells indicate conditions do not apply for the designated device.
Note 1: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are
updated with the current value of the PC. The STKPTR is modified to point to the next location in the
hardware stack.
2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt
vector (0008h or 0018h).
3: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).
4: See Table 4-1 for Reset value for specific condition.
5: Bits 6 and 7 of PORTA, LATA and TRISA are enabled depending on the oscillator mode selected. When
not enabled as PORTA pins, they are disabled and read as ‘0’.
© 2007 Microchip Technology Inc.
Preliminary
DS39774C-page 55
PIC18F85J11 FAMILY
NOTES:
DS39774C-page 56
Preliminary
© 2007 Microchip Technology Inc.
PIC18F85J11 FAMILY
5.1
Program Memory Organization
5.0
MEMORY ORGANIZATION
PIC18 microcontrollers implement a 21-bit program
counter which is capable of addressing a 2-Mbyte
program memory space. Accessing a location between
the upper boundary of the physically implemented
memory and the 2-Mbyte address will return all ‘0’s (a
NOPinstruction).
There are two types of memory in PIC18 Flash
microcontroller devices:
• Program Memory
• Data RAM
As Harvard architecture devices, the data and program
memories use separate busses; this allows for
concurrent access of the two memory spaces.
The entire PIC18F85J11 family offers a range of
on-chip Flash program memory sizes, from 8 Kbytes
(up to 4,096 single-word instructions) to 32 Kbytes
(32,768 single-word instructions). The program
memory maps for individual family members are shown
in Figure 5-1.
Additional detailed information on the operation of the
Flash program memory is provided in Section 6.0
“Flash Program Memory”.
FIGURE 5-1:
MEMORY MAPS FOR PIC18F85J11 FAMILY DEVICES
PC<20:0>
21
CALL, CALLW, RCALL,
RETURN, RETFIE, RETLW,
ADDULNK, SUBULNK
Stack Level 1
•
•
•
Stack Level 31
PIC18FX3J11
PIC18FX4J11
PIC18FX5J11
000000h
On-Chip
Memory
On-Chip
Memory
On-Chip
Memory
Config. Words
001FFFh
Config. Words
003FFFh
Config. Words
007FFFh
Unimplemented
Unimplemented
Unimplemented
Read as ‘0’
Read as ‘0’
Read as ‘0’
1FFFFFh
Note:
Sizes of memory areas are not to scale. Sizes of program memory areas are enhanced to show detail.
© 2007 Microchip Technology Inc.
Preliminary
DS39774C-page 57
PIC18F85J11 FAMILY
5.1.1
HARD MEMORY VECTORS
5.1.2
FLASH CONFIGURATION WORDS
All PIC18 devices have a total of three hard-coded
return vectors in their program memory space. The
Reset vector address is the default value to which the
program counter returns on all device Resets; it is
located at 0000h.
Because PIC18F85J11 family devices do not have per-
sistent configuration memory, the top four words of
on-chip program memory are reserved for configuration
information. On Reset, the configuration information is
copied into the Configuration registers.
PIC18 devices also have two interrupt vector
addresses for the handling of high priority and low
priority interrupts. The high priority interrupt vector is
located at 0008h and the low priority interrupt vector is
at 0018h. Their locations in relation to the program
memory map are shown in Figure 5-2.
The Configuration Words are stored in their program
memory location in numerical order, starting with the
lower byte of CONFIG1 at the lowest address and end-
ing with the upper byte of CONFIG4. For these devices,
only Configuration Words, CONFIG1 through
CONFIG3, are used; CONFIG4 is reserved. The actual
addresses of the Flash Configuration Word for devices
in the PIC18F85J11 family are shown in Table 5-1.
Their location in the memory map is shown with the
other memory vectors in Figure 5-2.
FIGURE 5-2:
HARD VECTOR AND
CONFIGURATION WORD
LOCATIONS FOR
Additional details on the device Configuration Words
are provided in Section 22.1 “Configuration Bits”.
PIC18F85J11 FAMILY
FAMILY DEVICES
TABLE 5-1:
FLASH CONFIGURATION
WORD FOR PIC18F85J11
FAMILY DEVICES
0000h
0008h
Reset Vector
High Priority Interrupt Vector
Low Priority Interrupt Vector 0018h
Program
Memory
(Kbytes)
Configuration
Word
Addresses
Device
PIC18F63J11
PIC18F83J11
PIC18F64J11
PIC18F84J11
PIC18F65J11
PIC18F85J11
8
1FF8h to 1FFFh
3FF8h to 3FFFh
7FF8h to 7FFFh
On-Chip
Program Memory
16
32
(Top of Memory-7)
(Top of Memory)
Flash Configuration Words
Read as ‘0’
1FFFFFh
Legend:
(Top of Memory) represents upper boundary
of on-chip program memory space (see
Figure 5-1 for device-specific values).
Shaded area represents unimplemented
memory. Areas are not shown to scale.
DS39774C-page 58
Preliminary
© 2007 Microchip Technology Inc.
PIC18F85J11 FAMILY
• The Extended Microcontroller Mode allows
access to both internal and external program
memories as a single block. The device can
access its entire on-chip program memory; above
this, the device accesses external program
memory up to the 2-Mbyte program space limit.
Execution automatically switches between the
two memories as required.
5.1.3
PIC18F8XJ11 PROGRAM MEMORY
MODES
The 80-pin devices in this family can address up to a
total of 2 Mbytes of program memory. This is achieved
through the external memory bus. There are two
distinct operating modes available to the controllers:
• Microcontroller (MC)
• Extended Microcontroller (EMC)
The setting of the EMB Configuration bits also controls
the address bus width of the external memory bus. This
is covered in more detail in Section 7.0 “External
Memory Bus”.
The Program Memory mode is determined by setting
the EMB Configuration bits (CONFIG3L<5:4>), as
shown in Register 5-1. (See also Section 22.1
“Configuration Bits” for additional details on the
device Configuration bits.)
In all modes, the microcontroller has complete access
to data RAM.
The Program Memory modes operate as follows:
Figure 5-3 compares the memory maps of the different
Program Memory modes. The differences between
on-chip and external memory access limitations are
more fully explained in Table 5-2.
• The Microcontroller Mode accesses only on-chip
Flash memory. Attempts to read above the top of
on-chip memory causes a read of all ‘0’s (a NOP
instruction).
The Microcontroller mode is also the only operating
mode available to 64-pin devices.
REGISTER 5-1:
CONFIG3L: CONFIGURATION REGISTER 3 LOW (BYTE ADDRESS 300004h)(1)
R/WO-1
WAIT
R/WO-1
BW
R/WO-1
EMB1
R/WO-1
EMB0
R/WO-1
EASHFT
U-0
—
U-0
—
U-0
—
bit 7
bit 0
Legend:
R = Readable bit
WO = Write-Once bit
U = Unimplemented bit, read as ‘0’
‘1’ = Bit is set ‘0’ = Bit is cleared
-n = Value when device is unprogrammed
bit 7
WAIT: External Bus Wait Enable bit
1= Wait selections from MEMCON.WAIT<1:0> unavailable, and the device will not wait
0= Wait programmed by MEMCON.WAIT<1:0>
bit 6
BW: Data Bus Width Select bit
1= 16-Bit External Bus mode
0= 8-Bit External Bus mode
bit 5:4
EMB1:EMB0: External Memory Bus Configuration bits
00= Extended Microcontroller mode – 20-Bit Address mode
01= Extended Microcontroller mode – 16-Bit Address mode
10= Extended Microcontroller mode – 12-Bit Address mode
11= Microcontroller mode – external bus disabled
bit 3
EASHFT: External Address Bus Shift Enable bit
1= Address shifting enabled – external address bus is shifted to start at 000000h
0= Address shifting disabled – external address bus reflects the PC value
bit 2-0
Unimplemented: Read as ‘0’
Note 1: CONFIG3L and its associated bits are implemented only in 80-pin devices.
© 2007 Microchip Technology Inc.
Preliminary
DS39774C-page 59
PIC18F85J11 FAMILY
To avoid this, the Extended Microcontroller mode
implements an address shifting option to enable auto-
matic address translation. In this mode, addresses
presented on the external bus are shifted down by the
size of the on-chip program memory and are remapped
to start at 0000h. This allows the complete use of the
external memory device’s memory space.
5.1.4
EXTENDED MICROCONTROLLER
MODE AND ADDRESS SHIFTING
By default, devices in Extended Microcontroller mode
directly present the program counter value on the
external address bus for those addresses in the range
of the external memory space. In practical terms, this
means addresses in the external memory device below
the top of on-chip memory are unavailable.
FIGURE 5-3:
MEMORY MAPS FOR PIC18F85J11 FAMILY PROGRAM MEMORY MODES
(1)
(2)
Extended Microcontroller Mode
Microcontroller Mode
Extended Microcontroller Mode
(2)
with Address Shifting
On-Chip
Memory
Space
On-Chip
Memory
Space
External
Memory
Space
External
Memory
Space
On-Chip
Memory
Space
000000h
000000h
000000h
On-Chip
Program
Memory
On-Chip
Program
Memory
On-Chip
Program
Memory
No
Access
(Top of Memory)
(Top of Memory) + 1
(Top of Memory)
(Top of Memory) + 1
(Top of Memory)
(Top of Memory) + 1
External
Memory
Mapped
to
External
Memory
Space
Reads
‘0’s
Mapped
to
External
Memory
Space
External
Memory
1FFFFFh –
(Top of Memory)
1FFFFFh
1FFFFFh
1FFFFFh
Legend:
(Top of Memory) represents upper boundary of on-chip program memory space (see Figure 5-1 for device-specific
values). Shaded areas represent unimplemented, or inaccessible areas, depending on the mode.
Note 1: This mode is the only available mode on 64-pin devices and the default on 80-pin devices.
2: These modes are only available on 80-pin devices.
TABLE 5-2:
MEMORY ACCESS FOR PIC18F8XJ11 PROGRAM MEMORY MODES
Internal Program Memory External Program Memory
Execution Table Read Table Write
Operating Mode
Execution
From
Table Read Table Write
From
From
To
From
To
Microcontroller
Yes
Yes
Yes
Yes
Yes
Yes
No Access
Yes
No Access
Yes
No Access
Yes
Extended Microcontroller
DS39774C-page 60
Preliminary
© 2007 Microchip Technology Inc.
PIC18F85J11 FAMILY
The stack operates as a 31-word by 21-bit RAM and a
5-bit Stack Pointer, STKPTR. The stack space is not
part of either program or data space. The Stack Pointer
is readable and writable and the address on the top of
the stack is readable and writable through the
Top-of-Stack Special Function Registers. Data can also
be pushed to, or popped from the stack, using these
registers.
5.1.5
PROGRAM COUNTER
The Program Counter (PC) specifies the address of the
instruction to fetch for execution. The PC is 21 bits wide
and is contained in three separate 8-bit registers. The
low byte, known as the PCL register, is both readable
and writable. The high byte, or PCH register, contains
the PC<15:8> bits; it is not directly readable or writable.
Updates to the PCH register are performed through the
PCLATH register. The upper byte is called PCU. This
register contains the PC<20:16> bits; it is also not
directly readable or writable. Updates to the PCU
register are performed through the PCLATU register.
A CALLtype instruction causes a push onto the stack.
The Stack Pointer is first incremented and the location
pointed to by the Stack Pointer is written with the
contents of the PC (already pointing to the instruction
following the CALL). A RETURNtype instruction causes
a pop from the stack. The contents of the location
pointed to by the STKPTR are transferred to the PC
and then the Stack Pointer is decremented.
The contents of PCLATH and PCLATU are transferred
to the program counter by any operation that writes
PCL. Similarly, the upper two bytes of the program
counter are transferred to PCLATH and PCLATU by an
operation that reads PCL. This is useful for computed
offsets to the PC (see Section 5.1.8.1 “Computed
GOTO”).
The Stack Pointer is initialized to ‘00000’ after all
Resets. There is no RAM associated with the location
corresponding to a Stack Pointer value of ‘00000’; this
is only a Reset value. Status bits indicate if the stack is
full, has overflowed or has underflowed.
The PC addresses bytes in the program memory. To
prevent the PC from becoming misaligned with word
instructions, the Least Significant bit of PCL is fixed to
a value of ‘0’. The PC increments by 2 to address
sequential instructions in the program memory.
5.1.6.1
Top-of-Stack Access
Only the top of the return address stack (TOS) is
readable and writable. A set of three registers,
TOSU:TOSH:TOSL, holds the contents of the stack
location pointed to by the STKPTR register
(Figure 5-4). This allows users to implement a software
stack if necessary. After a CALL, RCALL or interrupt
(and ADDULNK and SUBULNK instructions if the
extended instruction set is enabled), the software can
The CALL, RCALL, GOTO and program branch
instructions write to the program counter directly. For
these instructions, the contents of PCLATH and
PCLATU are not transferred to the program counter.
5.1.6
RETURN ADDRESS STACK
The return address stack allows any combination of up
to 31 program calls and interrupts to occur. The PC is
pushed onto the stack when a CALLor RCALLinstruc-
tion is executed, or an interrupt is Acknowledged. The
PC value is pulled off the stack on a RETURN, RETLWor
a RETFIEinstruction (and on ADDULNKand SUBULNK
instructions if the extended instruction set is enabled).
PCLATU and PCLATH are not affected by any of the
RETURNor CALLinstructions.
read
the
pushed
value
by
reading
the
TOSU:TOSH:TOSL registers. These values can be
placed on a user-defined software stack. At return time,
the software can return these values to
TOSU:TOSH:TOSL and do a return.
The user must disable the global interrupt enable bits
while accessing the stack to prevent inadvertent stack
corruption.
FIGURE 5-4:
RETURN ADDRESS STACK AND ASSOCIATED REGISTERS
Return Address Stack <20:0>
Stack Pointer
Top-of-Stack Registers
11111
11110
11101
STKPTR<4:0>
TOSU TOSH TOSL
00010
00h
1Ah
34h
00011
00010
00001
00000
001A34h
000D58h
Top-of-Stack
© 2007 Microchip Technology Inc.
Preliminary
DS39774C-page 61
PIC18F85J11 FAMILY
When the stack has been popped enough times to
unload the stack, the next pop will return a value of zero
to the PC and set the STKUNF bit, while the Stack
Pointer remains at zero. The STKUNF bit will remain
set until cleared by software or until a POR occurs.
5.1.6.2
Return Stack Pointer (STKPTR)
The STKPTR register (Register 5-2) contains the Stack
Pointer value, the STKFUL (Stack Full) status bit and
the STKUNF (Stack Underflow) status bits. The value
of the Stack Pointer can be 0 through 31. The Stack
Pointer increments before values are pushed onto the
stack and decrements after values are popped off the
stack. On Reset, the Stack Pointer value will be zero.
The user may read and write the Stack Pointer value.
This feature can be used by a Real-Time Operating
System (RTOS) for return stack maintenance.
Note:
Returning a value of zero to the PC on an
underflow has the effect of vectoring the
program to the Reset vector, where the
stack conditions can be verified and
appropriate actions can be taken. This is
not the same as a Reset, as the contents
of the SFRs are not affected.
After the PC is pushed onto the stack 31 times (without
popping any values off the stack), the STKFUL bit is
set. The STKFUL bit is cleared by software or by a
POR.
5.1.6.3
PUSHand POPInstructions
Since the Top-of-Stack is readable and writable, the
ability to push values onto the stack and pull values off
the stack, without disturbing normal program execu-
tion, is a desirable feature. The PIC18 instruction set
includes two instructions, PUSH and POP, that permit
the TOS to be manipulated under software control.
TOSU, TOSH and TOSL can be modified to place data
or a return address on the stack.
The action that takes place when the stack becomes
full depends on the state of the STVREN (Stack Over-
flow Reset Enable) Configuration bit. (Refer to
Section 22.1 “Configuration Bits” for a description of
the device Configuration bits.) If STVREN is set
(default), the 31st push will push the (PC + 2) value
onto the stack, set the STKFUL bit and reset the
device. The STKFUL bit will remain set and the Stack
Pointer will be set to zero.
The PUSHinstruction places the current PC value onto
the stack. This increments the Stack Pointer and loads
the current PC value onto the stack.
If STVREN is cleared, the STKFUL bit will be set on the
31st push and the Stack Pointer will increment to 31.
Any additional pushes will not overwrite the 31st push
and the STKPTR will remain at 31.
The POP instruction discards the current TOS by
decrementing the Stack Pointer. The previous value
pushed onto the stack then becomes the TOS value.
REGISTER 5-2:
STKPTR: STACK POINTER REGISTER
R/C-0
STKFUL(1)
R/C-0
STKUNF(1)
U-0
—
R/W-0
SP4
R/W-0
SP3
R/W-0
SP2
R/W-0
SP1
R/W-0
SP0
bit 7
bit 0
Legend:
C = Clearable-only bit
W = Writable bit
‘1’ = Bit is set
R = Readable bit
-n = Value at POR
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7
bit 6
STKFUL: Stack Full Flag bit(1)
1= Stack became full or overflowed
0= Stack has not become full or overflowed
STKUNF: Stack Underflow Flag bit(1)
1= Stack underflow occurred
0= Stack underflow did not occur
bit 5
Unimplemented: Read as ‘0’
bit 4-0
SP4:SP0: Stack Pointer Location bits
Note 1: Bit 7 and bit 6 are cleared by user software or by a POR.
DS39774C-page 62
Preliminary
© 2007 Microchip Technology Inc.
PIC18F85J11 FAMILY
5.1.6.4
Stack Full and Underflow Resets
5.1.8
LOOK-UP TABLES IN PROGRAM
MEMORY
Device Resets on stack overflow and stack underflow
conditions are enabled by setting the STVREN bit in
Configuration Register 1L. When STVREN is set, a full
or underflow condition will set the appropriate STKFUL
or STKUNF bit and then cause a device Reset. When
STVREN is cleared, a full or underflow condition will set
the appropriate STKFUL or STKUNF bit, but not cause
a device Reset. The STKFUL or STKUNF bits are
cleared by the user software or a Power-on Reset.
There may be programming situations that require the
creation of data structures, or look-up tables, in
program memory. For PIC18 devices, look-up tables
can be implemented in two ways:
• Computed GOTO
• Table Reads
5.1.8.1
Computed GOTO
5.1.7
FAST REGISTER STACK
A computed GOTOis accomplished by adding an offset
to the program counter. An example is shown in
Example 5-2.
A Fast Register Stack is provided for the STATUS,
WREG and BSR registers to provide a “fast return”
option for interrupts. This stack is only one level deep
and is neither readable nor writable. It is loaded with the
current value of the corresponding register when the
processor vectors for an interrupt. All interrupt sources
will push values into the Stack registers. The values in
the registers are then loaded back into the working
registers if the RETFIE, FAST instruction is used to
return from the interrupt.
A look-up table can be formed with an ADDWF PCL
instruction and a group of RETLW nninstructions. The
W register is loaded with an offset into the table before
executing a call to that table. The first instruction of the
called routine is the ADDWF PCLinstruction. The next
instruction executed will be one of the RETLW nn
instructions that returns the value ‘nn’ to the calling
function.
If both low and high priority interrupts are enabled, the
Stack registers cannot be used reliably to return from
low priority interrupts. If a high priority interrupt occurs
while servicing a low priority interrupt, the Stack
register values stored by the low priority interrupt will be
overwritten. In these cases, users must save the key
registers in software during a low priority interrupt.
The offset value (in WREG) specifies the number of
bytes that the program counter should advance and
should be multiples of 2 (LSb = 0).
In this method, only one data byte may be stored in
each instruction location and room on the return
address stack is required.
If interrupt priority is not used, all interrupts may use the
Fast Register Stack for returns from interrupt. If no
interrupts are used, the Fast Register Stack can be
used to restore the STATUS, WREG and BSR registers
at the end of a subroutine call. To use the Fast Register
Stack for a subroutine call, a CALL label, FAST
instruction must be executed to save the STATUS,
WREG and BSR registers to the Fast Register Stack. A
RETURN, FASTinstruction is then executed to restore
these registers from the Fast Register Stack.
EXAMPLE 5-2:
COMPUTED GOTOUSING
AN OFFSET VALUE
OFFSET, W
TABLE
MOVF
CALL
ORG
TABLE
nn00h
ADDWF
RETLW
RETLW
RETLW
.
PCL
nnh
nnh
nnh
.
Example 5-1 shows a source code example that uses
the Fast Register Stack during a subroutine call and
return.
.
5.1.8.2
Table Reads
A better method of storing data in program memory
allows two bytes of data to be stored in each instruction
location.
EXAMPLE 5-1:
FAST REGISTER STACK
CODE EXAMPLE
;STATUS, WREG, BSR
;SAVED IN FAST REGISTER
;STACK
CALL SUB1, FAST
Look-up table data may be stored two bytes per
program word while programming. The Table Pointer
(TBLPTR) specifies the byte address and the Table
Latch (TABLAT) contains the data that is read from the
program memory. Data is transferred from program
memory one byte at a time.
•
•
SUB1
•
•
RETURN FAST
;RESTORE VALUES SAVED
;IN FAST REGISTER STACK
Table read operation is discussed further in
Section 6.1 “Table Reads and Table Writes”.
© 2007 Microchip Technology Inc.
Preliminary
DS39774C-page 63
PIC18F85J11 FAMILY
5.2.2
INSTRUCTION FLOW/PIPELINING
5.2
PIC18 Instruction Cycle
An “Instruction Cycle” consists of four Q cycles, Q1
through Q4. The instruction fetch and execute are pipe-
lined in such a manner that a fetch takes one instruction
cycle, while the decode and execute take another
instruction cycle. However, due to the pipelining, each
instruction effectively executes in one cycle. If an
instruction causes the program counter to change (e.g.,
GOTO), then two cycles are required to complete the
instruction (Example 5-3).
5.2.1
CLOCKING SCHEME
The microcontroller clock input, whether from an
internal or external source, is internally divided by four
to generate four non-overlapping quadrature clocks
(Q1, Q2, Q3 and Q4). Internally, the program counter is
incremented on every Q1; the instruction is fetched
from the program memory and latched into the
Instruction Register (IR) during Q4. The instruction is
decoded and executed during the following Q1 through
Q4. The clocks and instruction execution flow are
shown in Figure 5-5.
A fetch cycle begins with the Program Counter (PC)
incrementing in Q1.
In the execution cycle, the fetched instruction is latched
into the Instruction Register (IR) in cycle Q1. This
instruction is then decoded and executed during the
Q2, Q3 and Q4 cycles. Data memory is read during Q2
(operand read) and written during Q4 (destination
write).
FIGURE 5-5:
CLOCK/INSTRUCTION CYCLE
Q2
Q3
Q4
Q2
Q3
Q4
Q2
Q3
Q4
Q1
Q1
Q1
OSC1
Q1
Q2
Q3
Q4
Internal
Phase
Clock
PC
PC + 2
PC + 4
PC
OSC2/CLKO
(RC mode)
Execute INST (PC – 2)
Fetch INST (PC)
Execute INST (PC)
Fetch INST (PC + 2)
Execute INST (PC + 2)
Fetch INST (PC + 4)
EXAMPLE 5-3:
INSTRUCTION PIPELINE FLOW
TCY0
TCY1
TCY2
TCY3
TCY4
TCY5
1. MOVLW 55h
2. MOVWF PORTB
3. BRA SUB_1
Fetch 1
Execute 1
Fetch 2
Execute 2
Fetch 3
Execute 3
Fetch 4
4. BSF
PORTA, BIT3 (Forced NOP)
Flush (NOP)
5. Instruction @ address SUB_1
Fetch SUB_1 Execute SUB_1
All instructions are single cycle, except for any program branches. These take two cycles since the fetch instruction
is “flushed” from the pipeline while the new instruction is being fetched and then executed.
DS39774C-page 64
Preliminary
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PIC18F85J11 FAMILY
The CALL and GOTO instructions have the absolute
program memory address embedded into the instruc-
tion. Since instructions are always stored on word
boundaries, the data contained in the instruction is a
word address. The word address is written to PC<20:1>
which accesses the desired byte address in program
memory. Instruction #2 in Figure 5-6 shows how the
instruction, GOTO 0006h, is encoded in the program
memory. Program branch instructions, which encode a
relative address offset, operate in the same manner. The
offset value stored in a branch instruction represents the
number of single-word instructions that the PC will be
offset by. Section 23.0 “Instruction Set Summary”
provides further details of the instruction set.
5.2.3
INSTRUCTIONS IN PROGRAM
MEMORY
The program memory is addressed in bytes. Instruc-
tions are stored as two bytes or four bytes in program
memory. The Least Significant Byte of an instruction
word is always stored in a program memory location
with an even address (LSB = 0). To maintain alignment
with instruction boundaries, the PC increments in steps
of 2 and the LSB will always read ‘0’ (see Section 5.1.5
“Program Counter”).
Figure 5-6 shows an example of how instruction words
are stored in the program memory.
FIGURE 5-6:
INSTRUCTIONS IN PROGRAM MEMORY
Word Address
LSB = 1
LSB = 0
↓
Program Memory
Byte Locations →
000000h
000002h
000004h
000006h
000008h
00000Ah
00000Ch
00000Eh
000010h
000012h
000014h
Instruction 1:
Instruction 2:
MOVLW
GOTO
055h
0Fh
EFh
F0h
C1h
F4h
55h
03h
00h
23h
56h
0006h
Instruction 3:
MOVFF
123h, 456h
and used by the instruction sequence. If the first word
is skipped for some reason and the second word is
executed by itself, a NOP is executed instead. This is
necessary for cases when the two-word instruction is
preceded by a conditional instruction that changes the
PC. Example 5-4 shows how this works.
5.2.4
TWO-WORD INSTRUCTIONS
The standard PIC18 instruction set has four two-word
instructions: CALL, MOVFF, GOTO and LSFR. In all
cases, the second word of the instructions always has
‘1111’ as its four Most Significant bits; the other 12 bits
are literal data, usually a data memory address.
Note:
See Section 5.5 “Program Memory and
the Extended Instruction Set” for
information on two-word instructions in the
extended instruction set.
The use of ‘1111’ in the 4 MSbs of an instruction
specifies a special form of NOP. If the instruction is
executed in proper sequence – immediately after the
first word – the data in the second word is accessed
EXAMPLE 5-4:
CASE 1:
TWO-WORD INSTRUCTIONS
Object Code
Source Code
0110 0110 0000 0000
1100 0001 0010 0011
1111 0100 0101 0110
0010 0100 0000 0000
CASE 2:
TSTFSZ
MOVFF
REG1
REG1, REG2 ; No, skip this word
; Execute this word as a NOP
; continue code
; is RAM location 0?
ADDWF
REG3
Object Code
Source Code
TSTFSZ
0110 0110 0000 0000
1100 0001 0010 0011
1111 0100 0101 0110
0010 0100 0000 0000
REG1
; is RAM location 0?
MOVFF
REG1, REG2 ; Yes, execute this word
; 2nd word of instruction
ADDWF
REG3
; continue code
© 2007 Microchip Technology Inc.
Preliminary
DS39774C-page 65
PIC18F85J11 FAMILY
5.3.1
BANK SELECT REGISTER
5.3
Data Memory Organization
Large areas of data memory require an efficient
addressing scheme to make rapid access to any
address possible. Ideally, this means that an entire
address does not need to be provided for each read or
write operation. For PIC18 devices, this is accom-
plished with a RAM banking scheme. This divides the
memory space into 16 contiguous banks of 256 bytes.
Depending on the instruction, each location can be
addressed directly by its full 12-bit address, or an 8-bit
low-order address and a 4-bit Bank Pointer.
Note:
The operation of some aspects of data
memory are changed when the PIC18
extended instruction set is enabled. See
Section 5.6 “Data Memory and the
Extended Instruction Set” for more
information.
The data memory in PIC18 devices is implemented as
static RAM. Each register in the data memory has a
12-bit address, allowing up to 4096 bytes of data
memory. The memory space is divided into as many as
16 banks that contain 256 bytes each. The
PIC18FX3J11/X4J11 devices, with up to 16 Kbytes of
program memory, implement 4 complete banks for a
total of 1024 bytes. PIC18FX5J11 devices, with
32 Kbytes of program memory, implement 8 complete
banks for a total of 2048 bytes. Figure 5-7 and
Figure 5-8 show the data memory organization for the
devices.
Most instructions in the PIC18 instruction set make use
of the Bank Pointer, known as the Bank Select Register
(BSR). This SFR holds the 4 Most Significant bits of a
location’s address; the instruction itself includes the
8 Least Significant bits. Only the four lower bits of the
BSR are implemented (BSR3:BSR0). The upper four
bits are unused; they will always read ‘0’ and cannot be
written to. The BSR can be loaded directly by using the
MOVLBinstruction.
The data memory contains Special Function Registers
(SFRs) and General Purpose Registers (GPRs). The
SFRs are used for control and status of the controller
and peripheral functions, while GPRs are used for data
storage and scratchpad operations in the user’s
application. Any read of an unimplemented location will
read as ‘0’s.
The value of the BSR indicates the bank in data
memory. The 8 bits in the instruction show the location
in the bank and can be thought of as an offset from the
bank’s lower boundary. The relationship between the
BSR’s value and the bank division in data memory is
shown in Figure 5-9.
Since up to 16 registers may share the same low-order
address, the user must always be careful to ensure that
the proper bank is selected before performing a data
read or write. For example, writing what should be
program data to an 8-bit address of F9h while the BSR
is 0Fh, will end up resetting the program counter.
The instruction set and architecture allow operations
across all banks. The entire data memory may be
accessed by Direct, Indirect or Indexed Addressing
modes. Addressing modes are discussed later in this
section.
To ensure that commonly used registers (select SFRs
and select GPRs) can be accessed in a single cycle,
PIC18 devices implement an Access Bank. This is a
256-byte memory space that provides fast access to
select SFRs and the lower portion of GPR Bank 0 with-
out using the BSR. Section 5.3.2 “Access Bank”
provides a detailed description of the Access RAM.
While any bank can be selected, only those banks that
are actually implemented can be read or written to.
Writes to unimplemented banks are ignored, while
reads from unimplemented banks will return ‘0’s. Even
so, the STATUS register will still be affected as if the
operation was successful. The data memory map in
Figure 5-7 indicates which banks are implemented.
In the core PIC18 instruction set, only the MOVFF
instruction fully specifies the 12-bit address of the
source and target registers. This instruction ignores the
BSR completely when it executes. All other instructions
include only the low-order address as an operand and
must use either the BSR or the Access Bank to locate
their target registers.
DS39774C-page 66
Preliminary
© 2007 Microchip Technology Inc.
PIC18F85J11 FAMILY
FIGURE 5-7:
DATA MEMORY MAP FOR PIC18FX3J11/X4J11 DEVICES
When a = 0:
The BSR is ignored and the
BSR<3:0>
Data Memory Map
Access Bank is used.
00h
000h
05Fh
060h
0FFh
100h
Access RAM
GPR
The first 96 bytes are general
purpose RAM (from Bank 0).
= 0000
Bank 0
Bank 1
Bank 2
Bank 3
FFh
00h
The second 160 bytes are
Special Function Registers
(from Bank 15).
= 0001
= 0010
= 0011
GPR
GPR
GPR
1FFh
200h
FFh
00h
When a = 1:
The BSR specifies the bank
used by the instruction.
FFh
00h
2FFh
300h
3FFh
400h
FFh
00h
= 0100
Bank 4
Access Bank
00h
Access RAM Low
5Fh
60h
Unused
Access RAM High
Read as ‘0’
(SFRs)
to
FFh
= 1110
= 1111
Bank 14
Bank 15
EFFh
F00h
F5Fh
F60h
FFFh
FFh
00h
Unused
SFR
FFh
© 2007 Microchip Technology Inc.
Preliminary
DS39774C-page 67
PIC18F85J11 FAMILY
FIGURE 5-8:
DATA MEMORY MAP FOR PIC18FX5J11 DEVICES
When a = 0:
The BSR is ignored and the
BSR<3:0>
Data Memory Map
Access Bank is used.
00h
000h
05Fh
060h
0FFh
100h
Access RAM
GPR
The first 96 bytes are general
purpose RAM (from Bank 0).
= 0000
Bank 0
Bank 1
Bank 2
Bank 3
Bank 4
Bank 5
Bank 6
Bank 7
FFh
00h
The second 160 bytes are
Special Function Registers
(from Bank 15).
= 0001
= 0010
= 0011
= 0100
= 0101
= 0110
= 0111
GPR
GPR
GPR
GPR
GPR
GPR
GPR
1FFh
200h
FFh
00h
When a = 1:
The BSR specifies the bank
used by the instruction.
FFh
00h
2FFh
300h
3FFh
400h
FFh
00h
FFh
00h
4FFh
500h
FFh
00h
5FFh
600h
FFh
00h
6FFh
700h
Access Bank
00h
FFh
00h
7FFh
800h
Access RAM Low
5Fh
60h
Access RAM High
(SFRs)
FFh
= 1000
Bank 8
Unused
to
Read as ‘0’
= 1110
= 1111
Bank 14
Bank 15
EFFh
F00h
F5Fh
F60h
FFFh
FFh
00h
Unused
SFR
FFh
DS39774C-page 68
Preliminary
© 2007 Microchip Technology Inc.
PIC18F85J11 FAMILY
FIGURE 5-9:
USE OF THE BANK SELECT REGISTER (DIRECT ADDRESSING)
Data Memory
(2)
(1)
From Opcode
1 1
BSR
000h
100h
7
0
7
0
00h
Bank 0
0
0
0
0
0
0
1
0
1
1
1
1
1 1
FFh
00h
Bank 1
Bank 2
(2)
Bank Select
FFh
00h
200h
300h
FFh
00h
Bank 3
through
Bank 13
FFh
00h
E00h
Bank 14
Bank 15
FFh
00h
F00h
FFFh
FFh
Note 1: The Access RAM bit of the instruction can be used to force an override of the selected bank (BSR<3:0>)
to the registers of the Access Bank.
2: The MOVFF instruction embeds the entire 12-bit address in the instruction.
however, the instruction is forced to use the Access
Bank address map; the current value of the BSR is
ignored entirely.
5.3.2
ACCESS BANK
While the use of the BSR with an embedded 8-bit
address allows users to address the entire range of data
memory, it also means that the user must always ensure
that the correct bank is selected. Otherwise, data may
be read from, or written to, the wrong location. This can
be disastrous if a GPR is the intended target of an oper-
ation, but an SFR is written to instead. Verifying and/or
changing the BSR for each read or write to data memory
can become very inefficient.
Using this “forced” addressing allows the instruction to
operate on a data address in a single cycle without
updating the BSR first. For 8-bit addresses of 60h and
above, this means that users can evaluate and operate
on SFRs more efficiently. The Access RAM below 60h
is a good place for data values that the user might need
to access rapidly, such as immediate computational
results or common program variables. Access RAM
also allows for faster and more code efficient context
saving and switching of variables.
To streamline access for the most commonly used data
memory locations, the data memory is configured with
an Access Bank, which allows users to access a
mapped block of memory without specifying a BSR.
The Access Bank consists of the first 96 bytes of
memory (00h-5Fh) in Bank 0 and the last 160 bytes of
memory (60h-FFh) in Bank 15. The lower half is known
as the “Access RAM” and is composed of GPRs. The
upper half is where the device’s SFRs are mapped.
These two areas are mapped contiguously in the
Access Bank and can be addressed in a linear fashion
by an 8-bit address (Figure 5-7).
The mapping of the Access Bank is slightly different
when the extended instruction set is enabled (XINST
Configuration bit = 1). This is discussed in more detail
in Section 5.6.3 “Mapping the Access Bank in
Indexed Literal Offset Mode”.
5.3.3
GENERAL PURPOSE
REGISTER FILE
PIC18 devices may have banked memory in the GPR
area. This is data RAM which is available for use by all
instructions. GPRs start at the bottom of Bank 0
(address 000h) and grow upwards towards the bottom of
the SFR area. GPRs are not initialized by a Power-on
Reset and are unchanged on all other Resets.
The Access Bank is used by core PIC18 instructions
that include the Access RAM bit (the ‘a’ parameter in
the instruction). When ‘a’ is equal to ‘1’, the instruction
uses the BSR and the 8-bit address included in the
opcode for the data memory address. When ‘a’ is ‘0’,
© 2007 Microchip Technology Inc.
Preliminary
DS39774C-page 69
PIC18F85J11 FAMILY
The SFRs can be classified into two sets: those
associated with the “core” device functionality (ALU,
Resets and interrupts) and those related to the
peripheral functions. The Reset and Interrupt registers
are described in their respective chapters, while the
ALU’s STATUS register is described later in this section.
Registers related to the operation of the peripheral
features are described in the chapter for that peripheral.
5.3.4
SPECIAL FUNCTION REGISTERS
The Special Function Registers (SFRs) are registers
used by the CPU and peripheral modules for controlling
the desired operation of the device. These registers are
implemented as static RAM. SFRs start at the top of
data memory (FFFh) and extend downward to occupy
more than the top half of Bank 15 (F60h to FFFh). A list
of these registers is given in Table 5-3 and Table 5-4.
The SFRs are typically distributed among the
peripherals whose functions they control. Unused SFR
locations are unimplemented and read as ‘0’s.
TABLE 5-3:
SPECIAL FUNCTION REGISTER MAP FOR PIC18F85J11 FAMILY DEVICES
Address
Name
Address
Name
Address
Name
Address
Name
Address
Name
(1)
(2)
FFFh
FFEh
FFDh
TOSU
TOSH
TOSL
FDFh
INDF2
FBFh
FBEh
FBDh
FBCh
FBBh
FBAh
FB9h
FB8h
FB7h
FB6h
FB5h
FB4h
FB3h
FB2h
FB1h
FB0h
FAFh
FAEh
FADh
FACh
FABh
FAAh
FA9h
FA8h
FA7h
FA6h
FA5h
FA4h
FA3h
FA2h
FA1h
FA0h
—
F9Fh
F9Eh
F9Dh
IPR1
PIR1
PIE1
F7Fh
SPBRGH1
(1)
(1)
(2)
FDEh POSTINC2
—
F7Eh BAUDCON1
(2)
(2)
FDDh POSTDEC2
—
F7Dh
F7Ch
F7Bh
F7Ah
F79h
F78h
F77h
F76h
F75h
F74h
F73h
F72h
F71h
F70h
F6Fh
F6Eh
F6Dh
F6Ch
F6Bh
F6Ah
F69h
F68h
F67h
F66h
F65h
F64h
F63h
F62h
F61h
F60h
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
(1)
(2)
(3)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
FFCh
FFBh
FFAh
FF9h
FF8h
FF7h
FF6h
FF5h
FF4h
FF3h
FF2h
FF1h
FF0h
FEFh
STKPTR
PCLATU
PCLATH
PCL
FDCh PREINC2
—
F9Ch MEMCON
(1)
(2)
FDBh PLUSW2
—
F9Bh OSCTUNE
(2)
(3)
FDAh
FD9h
FD8h
FD7h
FD6h
FD5h
FD4h
FD3h
FD2h
FD1h
FD0h
FCFh
FCEh
FCDh
FCCh
FCBh
FCAh
FC9h
FC8h
FC7h
FC6h
FC5h
FC4h
FC3h
FC2h
FC1h
FC0h
FSR2H
FSR2L
—
F9Ah
F99h
F98h
F97h
F96h
F95h
F94h
F93h
F92h
F91h
F90h
F8Fh
F8Eh
F8Dh
F8Ch
F8Bh
F8Ah
F89h
F88h
F87h
F86h
F85h
F84h
F83h
F82h
F81h
F80h
TRISJ
TRISH
(2)
(3)
—
(2)
TBLPTRU
TBLPTRH
TBLPTRL
TABLAT
PRODH
PRODL
STATUS
TMR0H
TMR0L
T0CON
—
TRISG
TRISF
TRISE
TRISD
TRISC
TRISB
TRISA
(2)
—
(2)
—
CVRCON
CMCON
TMR3H
(2)
—
OSCCON
(2)
INTCON
INTCON2
INTCON3
—
TMR3L
(3)
WDTCON
RCON
T3CON
LATJ
(3)
PSPCON
SPBRG1
RCREG1
TXREG1
TXSTA1
RCSTA1
LATH
(1)
INDF0
TMR1H
LATG
LATF
LATE
LATD
LATC
LATB
LATA
(1)
(1)
FEEh POSTINC0
TMR1L
FEDh POSTDEC0
T1CON
(1)
FECh PREINC0
TMR2
(1)
FEBh PLUSW0
PR2
(2)
FEAh
FE9h
FE8h
FE7h
FSR0H
FSR0L
WREG
T2CON
—
CCPR1H
CCPR1L
CCP1CON
CCPR2H
CCPR2L
CCP2CON
SPBRG2
RCREG2
TXREG2
TXSTA2
(2)
SSPBUF
SSPADD
SSPSTAT
SSPCON1
SSPCON2
ADRESH
ADRESL
ADCON0
ADCON1
ADCON2
—
(2)
(3)
—
PORTJ
PORTH
(1)
(3)
INDF1
EECON2
EECON1
IPR3
(1)
(1)
FE6h POSTINC1
PORTG
PORTF
PORTE
PORTD
PORTC
PORTB
PORTA
FE5h POSTDEC1
(1)
FE4h PREINC1
PIR3
(1)
FE3h PLUSW1
PIE3
FE2h
FE1h
FE0h
FSR1H
FSR1L
BSR
IPR2
PIR2
PIE2
RCSTA2
Note 1: This is not a physical register.
2: Unimplemented registers are read as ‘0’.
3: This register is not available on 64-pin devices.
DS39774C-page 70
Preliminary
© 2007 Microchip Technology Inc.
PIC18F85J11 FAMILY
TABLE 5-4:
PIC18F85J11 FAMILY REGISTER FILE SUMMARY
Value on
POR, BOR on page
Details
File Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
TOSU
—
—
—
Top-of-Stack Upper Byte (TOS<20:16>)
---0 0000 51, 61
0000 0000 51, 61
0000 0000 51, 61
uu-0 0000 51, 62
---0 0000 51, 61
0000 0000 51, 61
0000 0000 51, 61
--00 0000 51, 86
0000 0000 51, 86
0000 0000 51, 86
0000 0000 51, 86
xxxx xxxx 51, 105
xxxx xxxx 51, 105
0000 000x 51, 109
TOSH
Top-of-Stack High Byte (TOS<15:8>)
Top-of-Stack Low Byte (TOS<7:0>)
TOSL
STKPTR
PCLATU
PCLATH
PCL
STKFUL
—
STKUNF
—
—
bit 21(1)
Return Stack Pointer
Holding Register for PC<20:16>
Holding Register for PC<15:8>
PC Low Byte (PC<7:0>)
TBLPTRU
TBLPTRH
TBLPTRL
TABLAT
PRODH
PRODL
INTCON
—
—
bit 21
Program Memory Table Pointer Upper Byte (TBLPTR<20:16>)
Program Memory Table Pointer High Byte (TBLPTR<15:8>)
Program Memory Table Pointer Low Byte (TBLPTR<7:0>)
Program Memory Table Latch
Product Register High Byte
Product Register Low Byte
GIE/GIEH PEIE/GIEL
TMR0IE
INT0IE
RBIE
TMR0IF
INT0IF
RBIF
INTCON2
INTCON3
INDF0
RBPU
INTEDG0
INT1IP
INTEDG1
INT3IE
INTEDG2
INT2IE
INTEDG3
INT1IE
TMR0IP
INT3IF
INT3IP
INT2IF
RBIP
1111 1111 51, 110
1100 0000 51, 111
INT2IP
INT1IF
Uses contents of FSR0 to address data memory – value of FSR0 not changed (not a physical register)
Uses contents of FSR0 to address data memory – value of FSR0 post-incremented (not a physical register)
Uses contents of FSR0 to address data memory – value of FSR0 post-decremented (not a physical register)
Uses contents of FSR0 to address data memory – value of FSR0 pre-incremented (not a physical register)
N/A
N/A
N/A
N/A
N/A
51, 77
51, 78
51, 78
51, 78
51, 78
POSTINC0
POSTDEC0
PREINC0
PLUSW0
Uses contents of FSR0 to address data memory – value of FSR0 pre-incremented (not a physical register) –
value of FSR0 offset by W
FSR0H
—
—
—
—
Indirect Data Memory Address Pointer 0 High Byte
---- xxxx 51, 77
xxxx xxxx 51, 77
FSR0L
Indirect Data Memory Address Pointer 0 Low Byte
Working Register
WREG
xxxx xxxx
N/A
51
INDF1
Uses contents of FSR1 to address data memory – value of FSR1 not changed (not a physical register)
Uses contents of FSR1 to address data memory – value of FSR1 post-incremented (not a physical register)
Uses contents of FSR1 to address data memory – value of FSR1 post-decremented (not a physical register)
Uses contents of FSR1 to address data memory – value of FSR1 pre-incremented (not a physical register)
51, 77
51, 78
51, 78
51, 78
51, 78
POSTINC1
POSTDEC1
PREINC1
PLUSW1
N/A
N/A
N/A
Uses contents of FSR1 to address data memory – value of FSR1 pre-incremented (not a physical register) –
value of FSR1 offset by W
N/A
FSR1H
—
—
—
—
Indirect Data Memory Address Pointer 1 High Byte
---- xxxx 52, 77
xxxx xxxx 52, 77
---- 0000 52, 66
FSR1L
Indirect Data Memory Address Pointer 1 Low Byte
BSR
—
—
—
—
Bank Select Register
INDF2
Uses contents of FSR2 to address data memory – value of FSR2 not changed (not a physical register)
Uses contents of FSR2 to address data memory – value of FSR2 post-incremented (not a physical register)
Uses contents of FSR2 to address data memory – value of FSR2 post-decremented (not a physical register)
Uses contents of FSR2 to address data memory – value of FSR2 pre-incremented (not a physical register)
N/A
N/A
N/A
N/A
N/A
52, 77
52, 78
52, 78
52, 78
52, 78
POSTINC2
POSTDEC2
PREINC2
PLUSW2
Uses contents of FSR2 to address data memory – value of FSR2 pre-incremented (not a physical register) –
value of FSR2 offset by W
FSR2H
FSR2L
STATUS
—
—
—
—
Indirect Data Memory Address Pointer 2 High Byte
---- xxxx 52, 77
xxxx xxxx 52, 77
---x xxxx 52, 75
Indirect Data Memory Address Pointer 2 Low Byte
—
—
—
N
OV
Z
DC
C
Legend: x= unknown, u= unchanged, -= unimplemented, q= value depends on condition, r= reserved, do not modify
Note 1:
2:
Bit 21 of the PC is only available in Test mode and Serial Programming modes.
These registers and/or bits are available only on 80-pin devices; otherwise, they are unimplemented and read as ‘0’. Reset states shown
are for 80-pin devices.
3:
4:
5:
Alternate names and definitions for these bits when the MSSP module is operating in I2C™ Slave mode. See Section 16.4.3.2 “Address
Masking” for details.
The PLLEN bit is only available in specific oscillator configurations; otherwise, it is disabled and reads as ‘0’. See Section 2.4.3 “PLL
Frequency Multiplier” for details.
RA6/RA7 and their associated latch and direction bits are configured as port pins only when the internal oscillator is selected as the default
clock source (FOSC2 Configuration bit = 0); otherwise, they are disabled and these bits read as ‘0’.
© 2007 Microchip Technology Inc.
Preliminary
DS39774C-page 71
PIC18F85J11 FAMILY
TABLE 5-4:
PIC18F85J11 FAMILY REGISTER FILE SUMMARY (CONTINUED)
Value on
POR, BOR on page
Details
File Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
TMR0H
TMR0L
T0CON
OSCCON
WDTCON
RCON
Timer0 Register High Byte
Timer0 Register Low Byte
0000 0000 52, 149
xxxx xxxx 52, 149
1111 1111 52, 147
0100 q000 30, 52
TMR0ON
IDLEN
T08BIT
IRCF2
—
T0CS
IRCF1
—
T0SE
IRCF0
—
PSA
OSTS
—
T0PS2
IOFS
—
T0PS1
SCS1
—
T0PS0
SCS0
REGSLP
IPEN
SWDTEN 0--- ---0 52, 278
—
CM
RI
TO
PD
POR
BOR
0-11 11q0 46, 52
xxxx xxxx 52, 155
xxxx xxxx 52, 155
TMR1H
TMR1L
Timer1 Register High Byte
Timer1 Register Low Byte
T1CON
TMR2
RD16
T1RUN
T1CKPS1
T1CKPS0 T1OSCEN
T1SYNC
TMR1CS
T2CKPS1
TMR1ON 0000 0000 52, 151
0000 0000 52, 158
Timer2 Register
PR2
Timer2 Period Register
T2OUTPS3 T2OUTPS2 T2OUTPS1 T2OUTPS0 TMR2ON
MSSP Receive Buffer/Transmit Register
1111 1111 52, 158
T2CON
SSPBUF
—
T2CKPS0 -000 0000 52, 157
xxxx xxxx 52, 181,
216
SSPADD
SSPSTAT
MSSP Address Register (I2C™ Slave mode). MSSP Baud Rate Reload Register (I2C Master mode).
0000 0000 52, 216
SMP
CKE
D/A
P
S
R/W
SSPM2
PEN
UA
BF
0000 0000 52, 174,
183
SSPCON1
SSPCON2
WCOL
SSPOV
SSPEN
CKP
SSPM3
RCEN
SSPM1
RSEN
SSPM0
0000 0000 52, 175,
184
GCEN
GCEN
ACKSTAT
ACKDT
ACKEN
SEN
SEN
0000 0000 52, 185,
186
ACKSTAT ADMSK5(3) ADMSK4(3) ADMSK3(3) ADMSK2(3) ADMSK1(3)
ADRESH
ADRESL
A/D Result Register High Byte
A/D Result Register Low Byte
xxxx xxxx 53, 259
xxxx xxxx 53, 259
ADCON0
ADCON1
ADCON2
CVRCON
CMCON
TMR3H
ADCAL
—
—
—
CHS3
VCFG1
ACQT2
CVRR
C2INV
CHS2
VCFG0
ACQT1
CVRSS
C1INV
CHS1
PCFG3
ACQT0
CVR3
CIS
CHS0
PCFG2
ADCS2
CVR2
CM2
GO/DONE
PCFG1
ADCS1
CVR1
ADON
PCFG0
ADCS0
CVR0
CM0
0-00 0000 53, 251
--00 0000 53, 252
0-00 0000 53, 253
0000 0000 53, 267
0000 0111 53, 261
xxxx xxxx 53, 161
xxxx xxxx 53, 161
ADFM
CVREN
C2OUT
—
CVROE
C1OUT
CM1
Timer3 Register High Byte
Timer3 Register Low Byte
TMR3L
T3CON
RD16
IBF
T3CCP2
OBF
T3CKPS1
IBOV
T3CKPS0
T3CCP1
—
T3SYNC
—
TMR3CS
—
TMR3ON 0000 0000 53, 159
PSPCON
SPBRG1
RCREG1
TXREG1
TXSTA1
RCSTA1
EECON2
EECON1
PSPMODE
—
0000 ---- 53, 159
0000 0000 53, 221
0000 0000 53, 229
0000 0000 53, 227
0000 0010 53, 218
0000 000x 53, 219
---- ---- 53, 84
---0 x00- 53, 85
EUSART Baud Rate Generator Register
EUSART Receive Register
EUSART Transmit Register
CSRC
SPEN
TX9
RX9
TXEN
SREN
SYNC
CREN
SENDB
ADDEN
BRGH
FERR
TRMT
OERR
TX9D
RX9D
EEPROM Control Register 2 (not a physical register)
FREE
—
—
—
WRERR
WREN
WR
—
Legend: x= unknown, u= unchanged, -= unimplemented, q= value depends on condition, r= reserved, do not modify
Note 1:
2:
Bit 21 of the PC is only available in Test mode and Serial Programming modes.
These registers and/or bits are available only on 80-pin devices; otherwise, they are unimplemented and read as ‘0’. Reset states shown
are for 80-pin devices.
3:
4:
5:
Alternate names and definitions for these bits when the MSSP module is operating in I2C™ Slave mode. See Section 16.4.3.2 “Address
Masking” for details.
The PLLEN bit is only available in specific oscillator configurations; otherwise, it is disabled and reads as ‘0’. See Section 2.4.3 “PLL
Frequency Multiplier” for details.
RA6/RA7 and their associated latch and direction bits are configured as port pins only when the internal oscillator is selected as the default
clock source (FOSC2 Configuration bit = 0); otherwise, they are disabled and these bits read as ‘0’.
DS39774C-page 72
Preliminary
© 2007 Microchip Technology Inc.
PIC18F85J11 FAMILY
TABLE 5-4:
PIC18F85J11 FAMILY REGISTER FILE SUMMARY (CONTINUED)
Value on
POR, BOR on page
Details
File Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
IPR3
—
—
—
—
RC2IP
RC2IF
RC2IE
—
TX2IP
TX2IF
TX2IE
—
—
CCP2IP
CCP2IF
CCP2IE
LVDIP
LVDIF
LVDIE
—
CCP1IP
CCP1IF
CCP1IE
TMR3IP
TMR3IF
TMR3IE
TMR2IP
TMR2IF
TMR2IE
WM1
—
—
--00 -11- 53, 120
--00 -00- 53, 114
--00 -00- 53, 117
11-- 111- 53, 119
00-- 000- 53, 113
00-- 000- 53, 116
1111 1-11 53, 118
0000 0-00 53, 112
0000 0-00 53, 115
0-00 --00 53, 94
0000 0000 31, 53
1111 1111 54, 143
1111 1111 54, 141
0001 1111 54, 140
1111 111- 54, 138
1111 1-11 54, 136
1111 1111 54, 133
1111 1111 54, 130
1111 1111 54, 127
1111 1111 54, 125
xxxx xxxx 54, 143
xxxx xxxx 54, 141
00-x xxxx 54, 140
xxxx xxx- 54, 138
xxxx xxxx 54, 136
xxxx xxxx 54, 133
xxxx xxxx 54, 130
xxxx xxxx 54, 127
xxxx xxxx 54, 125
xxxx xxxx 54, 143
xxxx xxxx 54, 141
000x xxxx 54, 140
xxxx xxx- 54, 138
xxxx x-xx 54, 136
xxxx xxxx 54, 133
xxxx xxxx 54, 130
xxxx xxxx 54, 127
xx0x 0000 54, 125
PIR3
—
PIE3
—
—
—
—
IPR2
OSCFIP
OSCFIF
OSCFIE
PSPIP
PSPIF
PSPIE
EBDIS
INTSRC
TRISJ7
TRISH7
SPIOD
TRISF7
TRISE7
TRISD7
TRISC7
TRISB7
TRISA7(5)
LATJ7
LATH7
U2OD
LATF7
LATE7
LATD7
LATC7
LATB7
LATA7(5)
RJ7
CMIP
CMIF
BCLIP
BCLIF
BCLIE
SSPIP
SSPIF
SSPIE
—
—
PIR2
—
—
—
PIE2
CMIE
ADIP
—
—
—
IPR1
RC1IP
RC1IF
RC1IE
WAIT1
TUN5
TRISJ5
TRISH5
CCP1OD
TRISF5
TRISE5
TRISD5
TRISC5
TRISB5
TRISA5
LATJ5
LATH5
—
TX1IP
TX1IF
TX1IE
WAIT0
TUN4
TRISJ4
TRISH4
TRISG4
TRISF4
TRISE4
TRISD4
TRISC4
TRISB4
TRISA4
LATJ4
LATH4
LATG4
LATF4
LATE4
LATD4
LATC4
LATB4
LATA4
RJ4
TMR1IP
TMR1IF
TMR1IE
WM0
TUN0
TRISJ0
TRISH0
TRISG0
—
PIR1
ADIF
—
PIE1
ADIE
—
MEMCON(2)
OSCTUNE
TRISJ(2)
TRISH(2)
TRISG
TRISF
TRISE
TRISD
TRISC
TRISB
TRISA
LATJ(2)
LATH(2)
LATG
—
—
PLLEN(4)
TRISJ6
TRISH6
CCP2OD
TRISF6
TRISE6
TRISD6
TRISC6
TRISB6
TRISA6(5)
LATJ6
LATH6
U1OD
LATF6
LATE6
LATD6
LATC6
LATB6
LATA6(5)
RJ6
TUN3
TRISJ3
TRISH3
TRISG3
TRISF3
TRISE3
TRISD3
TRISC3
TRISB3
TRISA3
LATJ3
LATH3
LATG3
LATF3
LATE3
LATD3
LATC3
LATB3
LATA3
RJ3
TUN2
TRISJ2
TRISH2
TRISG2
TRISF2
—
TUN1
TRISJ1
TRISH1
TRISG1
TRISF1
TRISE1
TRISD1
TRISC1
TRISB1
TRISA1
LATJ1
LATH1
LATG1
LATF1
LATE1
LATD1
LATC1
LATB1
LATA1
RJ1
TRISE0
TRISD0
TRISC0
TRISB0
TRISA0
LATJ0
LATH0
LATG0
—
TRISD2
TRISC2
TRISB2
TRISA2
LATJ2
LATH2
LATG2
LATF2
LATE2
LATD2
LATC2
LATB2
LATA2
RJ2
LATF
LATF5
LATE5
LATD5
LATC5
LATB5
LATA5
RJ5
LATE
LATE0
LATD0
LATC0
LATB0
LATA0
RJ0
LATD
LATC
LATB
LATA
PORTJ(2)
PORTH(2)
PORTG
PORTF
PORTE
PORTD
PORTC
PORTB
PORTA
RH7
RH6
RH5
RJPU(2)
RH4
RH3
RH2
RH1
RH0
RDPU
RF7
REPU
RF6
RG4
RG3
RG2
RG1
RG0
RF5
RF4
RF3
RF2
RF1
—
RE7
RE6
RE5
RE4
RE3
—
RE1
RE0
RD7
RD6
RD5
RD4
RD3
RD2
RD1
RD0
RC7
RC6
RC5
RC4
RC3
RC2
RC1
RC0
RB7
RA7(5)
RB6
RA6(5)
RB5
RB4
RB3
RB2
RB1
RB0
RA5
RA4
RA3
RA2
RA1
RA0
Legend: x= unknown, u= unchanged, -= unimplemented, q= value depends on condition, r= reserved, do not modify
Note 1:
2:
Bit 21 of the PC is only available in Test mode and Serial Programming modes.
These registers and/or bits are available only on 80-pin devices; otherwise, they are unimplemented and read as ‘0’. Reset states shown
are for 80-pin devices.
3:
4:
5:
Alternate names and definitions for these bits when the MSSP module is operating in I2C™ Slave mode. See Section 16.4.3.2 “Address
Masking” for details.
The PLLEN bit is only available in specific oscillator configurations; otherwise, it is disabled and reads as ‘0’. See Section 2.4.3 “PLL
Frequency Multiplier” for details.
RA6/RA7 and their associated latch and direction bits are configured as port pins only when the internal oscillator is selected as the default
clock source (FOSC2 Configuration bit = 0); otherwise, they are disabled and these bits read as ‘0’.
© 2007 Microchip Technology Inc.
Preliminary
DS39774C-page 73
PIC18F85J11 FAMILY
TABLE 5-4:
PIC18F85J11 FAMILY REGISTER FILE SUMMARY (CONTINUED)
Value on
POR, BOR on page
Details
File Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
SPBRGH1
BAUDCON1
CCPR1H
CCPR1L
CCP1CON
CCPR2H
CCPR2L
CCP2CON
SPBRG2
RCREG2
TXREG2
TXSTA2
EUSART Baud Rate Generator High Byte
ABDOVF RCMT
0000 0000 54, 221
01-0 0-00 54, 220
xxxx xxxx 54, 164
xxxx xxxx 54, 164
—
SCKP
BRG16
—
WUE
ABDEN
Capture/Compare/PWM Register 1 High Byte
Capture/Compare/PWM Register 1 Low Byte
—
—
DC1B1
DC1B0
CCP1M3
CCP2M3
CCP1M2
CCP2M2
CCP1M1
CCP2M1
CCP1M0 --00 0000 54, 163
xxxx xxxx 55, 164
Capture/Compare/PWM Register 2 High Byte
Capture/Compare/PWM Register 2 Low Byte
xxxx xxxx 55, 164
—
—
DC2B1
DC2B0
CCP2M0 --00 0000 55, 163
0000 0000 55, 240
AUSART Baud Rate Generator Register
AUSART Receive Register
0000 0000 55, 245
AUSART Transmit Register
0000 0000 55, 243
CSRC
SPEN
TX9
RX9
TXEN
SREN
SYNC
CREN
—
BRGH
FERR
TRMT
OERR
TX9D
RX9D
0000 -010 55, 238
0000 000x 55, 239
RCSTA2
ADDEN
Legend: x= unknown, u= unchanged, -= unimplemented, q= value depends on condition, r= reserved, do not modify
Note 1:
2:
Bit 21 of the PC is only available in Test mode and Serial Programming modes.
These registers and/or bits are available only on 80-pin devices; otherwise, they are unimplemented and read as ‘0’. Reset states shown
are for 80-pin devices.
3:
4:
5:
Alternate names and definitions for these bits when the MSSP module is operating in I2C™ Slave mode. See Section 16.4.3.2 “Address
Masking” for details.
The PLLEN bit is only available in specific oscillator configurations; otherwise, it is disabled and reads as ‘0’. See Section 2.4.3 “PLL
Frequency Multiplier” for details.
RA6/RA7 and their associated latch and direction bits are configured as port pins only when the internal oscillator is selected as the default
clock source (FOSC2 Configuration bit = 0); otherwise, they are disabled and these bits read as ‘0’.
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register then reads back as ‘000u u1uu’. It is recom-
mended, therefore, that only BCF, BSF, SWAPF, MOVFF
and MOVWFinstructions are used to alter the STATUS
register because these instructions do not affect the Z,
C, DC, OV or N bits in the STATUS register.
5.3.5
STATUS REGISTER
The STATUS register, shown in Register 5-3, contains
the arithmetic status of the ALU. The STATUS register
can be the operand for any instruction, as with any
other register. If the STATUS register is the destination
for an instruction that affects the Z, DC, C, OV or N bits,
then the write to these five bits is disabled.
For other instructions not affecting any Status bits, see
the instruction set summaries in Table 23-2 and
Table 23-3.
These bits are set or cleared according to the device
logic. Therefore, the result of an instruction with the
STATUS register as destination may be different than
intended. For example, CLRF STATUSwill set the Z bit
but leave the other bits unchanged. The STATUS
Note: The C and DC bits operate as a borrow and
digit borrow bit respectively, in subtraction.
REGISTER 5-3:
STATUS REGISTER
U-0
—
U-0
U-0
—
R/W-x
N
R/W-x
OV
R/W-x
Z
R/W-x
DC(1)
R/W-x
C(2)
—
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7-5
bit 4
Unimplemented: Read as ‘0’
N: Negative bit
This bit is used for signed arithmetic (2’s complement). It indicates whether the result was
negative (ALU MSB = 1).
1= Result was negative
0= Result was positive
bit 3
OV: Overflow bit
This bit is used for signed arithmetic (2’s complement). It indicates an overflow of the
7-bit magnitude which causes the sign bit (bit 7) to change state.
1= Overflow occurred for signed arithmetic (in this arithmetic operation)
0= No overflow occurred
bit 2
bit 1
Z: Zero bit
1= The result of an arithmetic or logic operation is zero
0= The result of an arithmetic or logic operation is not zero
DC: Digit Carry/Borrow bit(1)
For ADDWF, ADDLW, SUBLWand SUBWFinstructions:
1= A carry-out from the 4th low-order bit of the result occurred
0= No carry-out from the 4th low-order bit of the result
bit 0
C: Carry/Borrow bit(2)
For ADDWF, ADDLW, SUBLWand SUBWFinstructions:
1= A carry-out from the Most Significant bit of the result occurred
0= No carry-out from the Most Significant bit of the result occurred
Note 1: For borrow, the polarity is reversed. A subtraction is executed by adding the 2’s complement of the second
operand. For rotate (RRF, RLF) instructions, this bit is loaded with either bit 4 or bit 3 of the source register.
2: For borrow, the polarity is reversed. A subtraction is executed by adding the 2’s complement of the second
operand. For rotate (RRF, RLF) instructions, this bit is loaded with either the high or low-order bit of the
source register.
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The Access RAM bit ‘a’ determines how the address is
interpreted. When ‘a’ is ‘1’, the contents of the BSR
(Section 5.3.1 “Bank Select Register”) are used with
the address to determine the complete 12-bit address
of the register. When ‘a’ is ‘0’, the address is interpreted
as being a register in the Access Bank. Addressing that
uses the Access RAM is sometimes also known as
Direct Forced Addressing mode.
5.4
Data Addressing Modes
Note:
The execution of some instructions in the
core PIC18 instruction set are changed
when the PIC18 extended instruction set is
enabled. See Section 5.6 “Data Memory
and the Extended Instruction Set” for
more information.
A few instructions, such as MOVFF, include the entire
12-bit address (either source or destination) in their
opcodes. In these cases, the BSR is ignored entirely.
While the program memory can be addressed in only
one way – through the program counter – information
in the data memory space can be addressed in several
ways. For most instructions, the addressing mode is
fixed. Other instructions may use up to three modes,
depending on which operands are used and whether or
not the extended instruction set is enabled.
The destination of the operation’s results is determined
by the destination bit ‘d’. When ‘d’ is ‘1’, the results are
stored back in the source register, overwriting its origi-
nal contents. When ‘d’ is ‘0’, the results are stored in
the W register. Instructions without the ‘d’ argument
have a destination that is implicit in the instruction; their
destination is either the target register being operated
on or the W register.
The addressing modes are:
• Inherent
• Literal
• Direct
5.4.3
INDIRECT ADDRESSING
• Indirect
Indirect Addressing allows the user to access a location
in data memory without giving a fixed address in the
instruction. This is done by using File Select Registers
(FSRs) as pointers to the locations to be read or written
to. Since the FSRs are themselves located in RAM as
Special Function Registers, they can also be directly
manipulated under program control. This makes FSRs
very useful in implementing data structures such as
tables and arrays in data memory.
An additional addressing mode, Indexed Literal Offset,
is available when the extended instruction set is
enabled (XINST Configuration bit = 1). Its operation is
discussed in greater detail in Section 5.6.1 “Indexed
Addressing with Literal Offset”.
5.4.1
INHERENT AND LITERAL
ADDRESSING
Many PIC18 control instructions do not need any
argument at all; they either perform an operation that
globally affects the device, or they operate implicitly on
one register. This addressing mode is known as Inherent
Addressing. Examples include SLEEP, RESETand DAW.
The registers for Indirect Addressing are also
implemented with Indirect File Operands (INDFs) that
permit automatic manipulation of the pointer value with
auto-incrementing, auto-decrementing or offsetting
with another value. This allows for efficient code using
loops, such as the example of clearing an entire RAM
bank in Example 5-5. It also enables users to perform
Indexed Addressing and other Stack Pointer
operations for program memory in data memory.
Other instructions work in a similar way, but require an
additional explicit argument in the opcode. This is
known as Literal Addressing mode, because they
require some literal value as an argument. Examples
include ADDLWand MOVLW, which respectively, add or
move a literal value to the W register. Other examples
include CALL and GOTO, which include a 20-bit
program memory address.
EXAMPLE 5-5:
HOW TO CLEAR RAM
(BANK 1) USING
INDIRECT ADDRESSING
5.4.2
DIRECT ADDRESSING
LFSR
FSR0, 100h
;
NEXT
CLRF
POSTINC0
; Clear INDF
; register then
; inc pointer
; All done with
; Bank1?
Direct Addressing specifies all or part of the source
and/or destination address of the operation within the
opcode itself. The options are specified by the
arguments accompanying the instruction.
BTFSS
BRA
FSR0H, 1
NEXT
; NO, clear next
; YES, continue
In the core PIC18 instruction set, bit-oriented and
byte-oriented instructions use some version of Direct
Addressing by default. All of these instructions include
some 8-bit literal address as their Least Significant
Byte. This address specifies either a register address in
one of the banks of data RAM (Section 5.3.3 “General
Purpose Register File”), or a location in the Access
Bank (Section 5.3.2 “Access Bank”) as the data
source for the instruction.
CONTINUE
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the SFR space but are not physically implemented.
Reading or writing to a particular INDF register actually
accesses its corresponding FSR register pair. A read
from INDF1, for example, reads the data at the address
indicated by FSR1H:FSR1L. Instructions that use the
INDF registers as operands actually use the contents
of their corresponding FSR as a pointer to the instruc-
tion’s target. The INDF operand is just a convenient
way of using the pointer.
5.4.3.1
FSR Registers and the
INDF Operand
At the core of Indirect Addressing are three sets of
registers: FSR0, FSR1 and FSR2. Each represents a
pair of 8-bit registers, FSRnH and FSRnL. The four
upper bits of the FSRnH register are not used, so each
FSR pair holds a 12-bit value. This represents a value
that can address the entire range of the data memory
in a linear fashion. The FSR register pairs, then, serve
as pointers to data memory locations.
Because Indirect Addressing uses a full 12-bit address,
data RAM banking is not necessary. Thus, the current
contents of the BSR and the Access RAM bit have no
effect on determining the target address.
Indirect Addressing is accomplished with a set of Indi-
rect File Operands, INDF0 through INDF2. These can
be thought of as “virtual” registers: they are mapped in
FIGURE 5-10:
INDIRECT ADDRESSING
000h
Using an instruction with one of the
Indirect Addressing registers as the
operand....
Bank 0
Bank 1
ADDWF, INDF1, 1
100h
200h
300h
Bank 2
FSR1H:FSR1L
...uses the 12-bit address stored in
the FSR pair associated with that
register....
7
0
7
0
x x x x 1 1 1 1
1 1 0 0 1 1 0 0
Bank 3
through
Bank 13
...to determine the data memory
location to be used in that operation.
E00h
In this case, the FSR1 pair contains
FCCh. This means the contents of
location FCCh will be added to that
of the W register and stored back in
FCCh.
Bank 14
Bank 15
F00h
FFFh
Data Memory
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5.4.3.2
FSR Registers and POSTINC,
5.4.3.3
Operations by FSRs on FSRs
POSTDEC, PREINC and PLUSW
Indirect Addressing operations that target other FSRs
or virtual registers represent special cases. For exam-
ple, using an FSR to point to one of the virtual registers
will not result in successful operations. As a specific
case, assume that FSR0H:FSR0L contain FE7h, the
address of INDF1. Attempts to read the value of the
INDF1, using INDF0 as an operand, will return 00h.
Attempts to write to INDF1, using INDF0 as the
operand, will result in a NOP.
In addition to the INDF operand, each FSR register pair
also has four additional indirect operands. Like INDF,
these are “virtual” registers that cannot be indirectly
read or written to. Accessing these registers actually
accesses the associated FSR register pair, but also
performs a specific action on its stored value. They are:
• POSTDEC: accesses the FSR value, then
automatically decrements it by ‘1’ afterwards
On the other hand, using the virtual registers to write to
an FSR pair may not occur as planned. In these cases,
the value will be written to the FSR pair but without any
incrementing or decrementing. Thus, writing to INDF2
or POSTDEC2 will write the same value to the
FSR2H:FSR2L.
• POSTINC: accesses the FSR value, then
automatically increments it by ‘1’ afterwards
• PREINC: increments the FSR value by ‘1’, then
uses it in the operation
• PLUSW: adds the signed value of the W register
(range of -127 to 128) to that of the FSR and uses
the new value in the operation
Since the FSRs are physical registers mapped in the
SFR space, they can be manipulated through all direct
operations. Users should proceed cautiously when
working on these registers, particularly if their code
uses Indirect Addressing.
In this context, accessing an INDF register uses the
value in the FSR registers without changing them.
Similarly, accessing a PLUSW register gives the FSR
value offset by the value in the W register; neither value
is actually changed in the operation. Accessing the
other virtual registers changes the value of the FSR
registers.
Similarly, operations by Indirect Addressing are gener-
ally permitted on all other SFRs. Users should exercise
the appropriate caution that they do not inadvertently
change settings that might affect the operation of the
device.
Operations on the FSRs with POSTDEC, POSTINC
and PREINC affect the entire register pair; that is, roll-
overs of the FSRnL register from FFh to 00h carry over
to the FSRnH register. On the other hand, results of
these operations do not change the value of any flags
in the STATUS register (e.g., Z, N, OV, etc.).
5.5
Program Memory and the
Extended Instruction Set
The operation of program memory is unaffected by the
use of the extended instruction set.
The PLUSW register can be used to implement a form
of Indexed Addressing in the data memory space. By
manipulating the value in the W register, users can
reach addresses that are fixed offsets from pointer
addresses. In some applications, this can be used to
implement some powerful program control structure,
such as software stacks, inside of data memory.
Enabling the extended instruction set adds five
additional two-word commands to the existing PIC18
instruction set: ADDFSR, CALLW, MOVSF, MOVSS and
SUBFSR. These instructions are executed as described
in Section 5.2.4 “Two-Word Instructions”.
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5.6.2
INSTRUCTIONS AFFECTED BY
INDEXED LITERAL OFFSET MODE
5.6
Data Memory and the Extended
Instruction Set
Any of the core PIC18 instructions that can use Direct
Addressing are potentially affected by the Indexed
Literal Offset Addressing mode. This includes all
byte-oriented and bit-oriented instructions, or almost
one-half of the standard PIC18 instruction set. Instruc-
tions that only use Inherent or Literal Addressing
modes are unaffected.
Enabling the PIC18 extended instruction set (XINST
Configuration bit = 1) significantly changes certain
aspects of data memory and its addressing. Specifically,
the use of the Access Bank for many of the core PIC18
instructions is different; this is due to the introduction of
a new addressing mode for the data memory space.
This mode also alters the behavior of Indirect
Addressing using FSR2 and its associated operands.
Additionally, byte-oriented and bit-oriented instructions
are not affected if they use the Access Bank (Access
RAM bit is ‘1’) or include a file address of 60h or above.
Instructions meeting these criteria will continue to
execute as before. A comparison of the different
possible addressing modes when the extended
instruction set is enabled is shown in Figure 5-11.
What does not change is just as important. The size of
the data memory space is unchanged, as well as its
linear addressing. The SFR map remains the same.
Core PIC18 instructions can still operate in both Direct
and Indirect Addressing mode; inherent and literal
instructions do not change at all. Indirect Addressing
with FSR0 and FSR1 also remains unchanged.
Those who desire to use byte-oriented or bit-oriented
instructions in the Indexed Literal Offset mode should
note the changes to assembler syntax for this mode.
This is described in more detail in Section 23.2.1
“Extended Instruction Syntax”.
5.6.1
INDEXED ADDRESSING WITH
LITERAL OFFSET
Enabling the PIC18 extended instruction set changes
the behavior of Indirect Addressing using the FSR2
register pair and its associated file operands. Under the
proper conditions, instructions that use the Access
Bank – that is, most bit-oriented and byte-oriented
instructions – can invoke a form of Indexed Addressing
using an offset specified in the instruction. This special
addressing mode is known as Indexed Addressing with
Literal Offset, or Indexed Literal Offset mode.
When using the extended instruction set, this
addressing mode requires the following:
• The use of the Access Bank is forced (‘a’ = 0);
and
• The file address argument is less than or equal to
5Fh.
Under these conditions, the file address of the
instruction is not interpreted as the lower byte of an
address (used with the BSR in Direct Addressing) or as
an 8-bit address in the Access Bank. Instead, the value
is interpreted as an offset value to an Address Pointer
specified by FSR2. The offset and the contents of FSR2
are added to obtain the target address of the operation.
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FIGURE 5-11:
COMPARING ADDRESSING OPTIONS FOR BIT-ORIENTED AND
BYTE-ORIENTED INSTRUCTIONS (EXTENDED INSTRUCTION SET ENABLED)
EXAMPLE INSTRUCTION: ADDWF, f, d, a (Opcode: 0010 01da ffff ffff)
000h
When a = 0and f ≥ 60h:
The instruction executes in
Direct Forced mode. ‘f’ is
interpreted as a location in the
Access RAM between 060h
and FFFh. This is the same as
locations F60h to FFFh
(Bank 15) of data memory.
060h
100h
Bank 0
00h
60h
Bank 1
through
Bank 14
Valid range
for ‘f’
Locations below 060h are not
available in this addressing
mode.
FFh
F00h
Access RAM
Bank 15
F40h
FFFh
SFRs
Data Memory
When a = 0and f ≤ 5Fh:
000h
060h
100h
Bank 0
The instruction executes in
Indexed Literal Offset mode. ‘f’
is interpreted as an offset to the
address value in FSR2. The
two are added together to
obtain the address of the target
register for the instruction. The
address can be anywhere in
the data memory space.
001001da ffffffff
Bank 1
through
Bank 14
FSR2H
FSR2L
F00h
F40h
Note that in this mode, the
correct syntax is now:
Bank 15
ADDWF [k], d
SFRs
where ‘k’ is the same as ‘f’.
FFFh
Data Memory
BSR
000h
060h
100h
00000000
When a = 1(all values of f):
Bank 0
The instruction executes in
Direct mode (also known as
Direct Long mode). ‘f’ is
interpreted as a location in
one of the 16 banks of the data
memory space. The bank is
designated by the Bank Select
Register (BSR). The address
can be in any implemented
bank in the data memory
space.
001001da ffffffff
Bank 1
through
Bank 14
F00h
F40h
Bank 15
SFRs
FFFh
Data Memory
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Remapping of the Access Bank applies only to opera-
tions using the Indexed Literal Offset mode. Operations
that use the BSR (Access RAM bit is ‘1’) will continue
to use Direct Addressing as before. Any Indirect or
Indexed Addressing operation that explicitly uses any
of the indirect file operands (including FSR2) will con-
tinue to operate as standard Indirect Addressing. Any
instruction that uses the Access Bank, but includes a
register address of greater than 05Fh, will use Direct
Addressing and the normal Access Bank map.
5.6.3
MAPPING THE ACCESS BANK IN
INDEXED LITERAL OFFSET MODE
The use of Indexed Literal Offset Addressing mode
effectively changes how the lower part of Access RAM
(00h to 5Fh) is mapped. Rather than containing just the
contents of the bottom part of Bank 0, this mode maps
the contents from Bank 0 and a user-defined “window”
that can be located anywhere in the data memory
space. The value of FSR2 establishes the lower bound-
ary of the addresses mapped into the window, while the
upper boundary is defined by FSR2 plus 95 (5Fh).
Addresses in the Access RAM above 5Fh are mapped
as previously described (see Section 5.3.2 “Access
Bank”). An example of Access Bank remapping in this
addressing mode is shown in Figure 5-12.
5.6.4
BSR IN INDEXED LITERAL
OFFSET MODE
Although the Access Bank is remapped when the
extended instruction set is enabled, the operation of the
BSR remains unchanged. Direct Addressing, using the
BSR to select the data memory bank, operates in the
same manner as previously described.
FIGURE 5-12:
REMAPPING THE ACCESS BANK WITH INDEXED LITERAL
OFFSET ADDRESSING
Example Situation:
000h
ADDWF f, d, a
Not Accessible
05Fh
FSR2H:FSR2L = 120h
Bank 0
Locations in the region
from the FSR2 Pointer
(120h) to the pointer plus
05Fh (17Fh) are mapped
to the bottom of the
Access RAM (000h-05Fh).
100h
120h
17Fh
Window
Bank 1
00h
Bank 1 “Window”
200h
5Fh
60h
Special Function Registers
at F60h through FFFh are
mapped to 60h through
FFh, as usual.
Bank 2
through
Bank 14
SFRs
Bank 0 addresses below
5Fh are not available in
this mode. They can still
be addressed by using the
BSR.
FFh
Access Bank
F00h
Bank 15
SFRs
F60h
FFFh
Data Memory
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NOTES:
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6.1
Table Reads and Table Writes
6.0
FLASH PROGRAM MEMORY
In order to read and write program memory, there are
two operations that allow the processor to move bytes
between the program memory space and the data RAM:
The Flash program memory is readable, writable and
erasable during normal operation over the entire VDD
range.
• Table Read (TBLRD)
• Table Write (TBLWT)
A read from program memory is executed on one byte
at a time. A write to program memory is executed on
blocks of 64 bytes at a time. Program memory is
erased in blocks of 1024 bytes at a time. A Bulk Erase
operation may not be issued from user code.
The program memory space is 16 bits wide, while the
data RAM space is 8 bits wide. Table reads and table
writes move data between these two memory spaces
through an 8-bit register (TABLAT).
Writing or erasing program memory will cease
instruction fetches until the operation is complete. The
program memory cannot be accessed during the write
or erase, therefore, code cannot execute. An internal
programming timer terminates program memory writes
and erases.
Table read operations retrieve data from program
memory and place it into the data RAM space.
Figure 6-1 shows the operation of a table read with
program memory and data RAM.
Table write operations store data from the data memory
space into holding registers in program memory. The
procedure to write the contents of the holding registers
into program memory is detailed in Section 6.5 “Writing
to Flash Program Memory”. Figure 6-2 shows the
operation of a table write with program memory and data
RAM.
A value written to program memory does not need to be
a valid instruction. Executing a program memory
location that forms an invalid instruction results in a
NOP.
Table operations work with byte entities. A table block
containing data, rather than program instructions, is not
required to be word-aligned. Therefore, a table block can
start and end at any byte address. If a table write is being
used to write executable code into program memory,
program instructions will need to be word-aligned.
FIGURE 6-1:
TABLE READ OPERATION
Instruction: TBLRD*
Program Memory
(1)
Table Pointer
Table Latch (8-bit)
TABLAT
TBLPTRU TBLPTRH TBLPTRL
Program Memory
(TBLPTR)
Note 1: Table Pointer register points to a byte in program memory.
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FIGURE 6-2:
TABLE WRITE OPERATION
Instruction: TBLWT*
Program Memory
Holding Registers
(1)
Table Pointer
TBLPTRU TBLPTRH TBLPTRL
Table Latch (8-bit)
TABLAT
Program Memory
(TBLPTR)
Note 1: Table Pointer actually points to one of 64 holding registers, the address of which is determined by
TBLPTRL<5:0>. The process for physically writing data to the program memory array is discussed in
Section 6.5 “Writing to Flash Program Memory”.
The WREN bit, when set, will allow a write operation.
On power-up, the WREN bit is clear. The WRERR bit is
set in hardware when the WR bit is set and cleared
when the internal programming timer expires and the
write operation is complete.
6.2
Control Registers
Several control registers are used in conjunction with
the TBLRDand TBLWTinstructions. These include the:
• EECON1 register
• EECON2 register
• TABLAT register
• TBLPTR registers
Note:
During normal operation, the WRERR is
read as ‘1’. This can indicate that a write
operation was prematurely terminated by
a
Reset, or
a write operation was
6.2.1
EECON1 AND EECON2 REGISTERS
attempted improperly.
The EECON1 register (Register 6-1) is the control
register for memory accesses. The EECON2 register is
not a physical register; it is used exclusively in the
memory write and erase sequences. Reading
EECON2 will read all ‘0’s.
The WR control bit initiates write operations. The bit
cannot be cleared, only set, in software. It is cleared in
hardware at the completion of the write operation.
The FREE bit, when set, will allow a program memory
erase operation. When FREE is set, the erase
operation is initiated on the next WR command. When
FREE is clear, only writes are enabled.
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REGISTER 6-1:
EECON1: EEPROM CONTROL REGISTER 1
U-0
—
U-0
—
U-0
—
R/W-0
FREE
R/W-x
R/W-0
WREN
R/S-0
WR
U-0
—
WRERR
bit 7
bit 0
Legend:
U = Unimplemented bit, read as ‘0’
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
S = Set only bit (cannot be cleared in software)
‘0’ = Bit is cleared x = Bit is unknown
bit 7-5
bit 4
Unimplemented: Read as ‘0’
FREE: Flash Row Erase Enable bit
1= Erase the program memory row addressed by TBLPTR on the next WR command (cleared by
completion of erase operation)
0= Perform write only
bit 3
WRERR: Flash Program Error Flag bit
1= A write operation is prematurely terminated (any Reset during self-timed programming in normal
operation, or an improper write attempt)
0= The write operation completed
bit 2
bit 1
WREN: Flash Program Write Enable bit
1= Allows write cycles to Flash program memory
0= Inhibits write cycles to Flash program memory
WR: Write Control bit
1= Initiates a program memory erase cycle or write cycle
(The operation is self-timed and the bit is cleared by hardware once write is complete.
The WR bit can only be set (not cleared) in software.)
0= Write cycle is complete
bit 0
Unimplemented: Read as ‘0’
© 2007 Microchip Technology Inc.
Preliminary
DS39774C-page 85
PIC18F85J11 FAMILY
6.2.2
TABLE LATCH REGISTER (TABLAT)
6.2.4
TABLE POINTER BOUNDARIES
The Table Latch (TABLAT) is an 8-bit register mapped
into the SFR space. The Table Latch register is used to
hold 8-bit data during data transfers between program
memory and data RAM.
TBLPTR is used in reads, writes and erases of the
Flash program memory.
When a TBLRDis executed, all 22 bits of the TBLPTR
determine which byte is read from program memory
into TABLAT.
6.2.3
TABLE POINTER REGISTER
(TBLPTR)
When a TBLWT is executed, the seven LSbs of the
Table Pointer register (TBLPTR<6:0>) determine which
of the 64 program memory holding registers is written
to. When the timed write to program memory begins
(via the WR bit), the 12 MSbs of the TBLPTR
(TBLPTR<21:10>) determine which program memory
block of 1024 bytes is written to. For more detail, see
Section 6.5 “Writing to Flash Program Memory”.
The Table Pointer (TBLPTR) register addresses a byte
within the program memory. The TBLPTR is comprised
of three SFR registers: Table Pointer Upper Byte, Table
Pointer High Byte and Table Pointer Low Byte
(TBLPTRU:TBLPTRH:TBLPTRL). These three regis-
ters join to form a 22-bit wide pointer. The low-order
21 bits allow the device to address up to 2 Mbytes of
program memory space. The 22nd bit allows access to
the device ID, the user ID and the Configuration bits.
When an erase of program memory is executed, the
12 MSbs of the Table Pointer register point to the
1024-byte block that will be erased. The Least
Significant bits are ignored.
The Table Pointer register, TBLPTR, is used by the
TBLRDand TBLWTinstructions. These instructions can
update the TBLPTR in one of four ways based on the
table operation. These operations are shown in
Table 6-1. These operations on the TBLPTR only affect
the low-order 21 bits.
Figure 6-3 describes the relevant boundaries of the
TBLPTR based on Flash program memory operations.
TABLE 6-1:
Example
TABLE POINTER OPERATIONS WITH TBLRDAND TBLWTINSTRUCTIONS
Operation on Table Pointer
TBLRD*
TBLWT*
TBLPTR is not modified
TBLRD*+
TBLWT*+
TBLPTR is incremented after the read/write
TBLPTR is decremented after the read/write
TBLPTR is incremented before the read/write
TBLRD*-
TBLWT*-
TBLRD+*
TBLWT+*
FIGURE 6-3:
TABLE POINTER BOUNDARIES BASED ON OPERATION
21
16 15
TBLPTRH
8
7
TBLPTRL
0
TBLPTRU
ERASE: TBLPTR<21:10>
TABLE WRITE: TBLPTR<21:6>
TABLE READ: TBLPTR<21:0>
DS39774C-page 86
Preliminary
© 2007 Microchip Technology Inc.
PIC18F85J11 FAMILY
The internal program memory is typically organized by
words. The Least Significant bit of the address selects
between the high and low bytes of the word. Figure 6-4
shows the interface between the internal program
memory and the TABLAT.
6.3
Reading the Flash Program Memory
The TBLRD instruction is used to retrieve data from
program memory and places it into data RAM. Table
reads from program memory are performed one byte at
a time.
TBLPTR points to a byte address in program space.
Executing TBLRD places the byte pointed to into
TABLAT. In addition, TBLPTR can be modified
automatically for the next table read operation.
FIGURE 6-4:
READS FROM FLASH PROGRAM MEMORY
Program Memory
(Even Byte Address)
(Odd Byte Address)
TBLPTR = xxxxx1
TBLPTR = xxxxx0
Instruction Register
TABLAT
Read Register
FETCH
TBLRD
(IR)
EXAMPLE 6-1:
READING A FLASH PROGRAM MEMORY WORD
MOVLW
CODE_ADDR_UPPER
TBLPTRU
CODE_ADDR_HIGH
TBLPTRH
CODE_ADDR_LOW
TBLPTRL
; Load TBLPTR with the base
; address of the word
MOVWF
MOVLW
MOVWF
MOVLW
MOVWF
READ_WORD
TBLRD*+
MOVF
MOVWF
TBLRD*+
MOVF
; read into TABLAT and increment
; get data
TABLAT, W
WORD_EVEN
; read into TABLAT and increment
; get data
TABLAT, W
WORD_ODD
MOVF
© 2007 Microchip Technology Inc.
Preliminary
DS39774C-page 87
PIC18F85J11 FAMILY
6.4.1
FLASH PROGRAM MEMORY
ERASE SEQUENCE
6.4
Erasing Flash Program Memory
The minimum erase block is 512 words or 1024 bytes.
Only through the use of an external programmer, or
through ICSP control, can larger blocks of program
memory be Bulk Erased. Word Erase in the Flash array
is not supported.
The sequence of events for erasing a block of internal
program memory location is:
1. Load Table Pointer register with address of row
being erased.
When initiating an erase sequence from the micro-
controller itself, a block of 1024 bytes of program
memory is erased. The Most Significant 12 bits of the
TBLPTR<21:10> point to the block being erased;
TBLPTR<9:0> are ignored.
2. Set the WREN and FREE bits (EECON1<2,4>)
to enable the erase operation.
3. Disable interrupts.
4. Write 55h to EECON2.
5. Write 0AAh to EECON2.
The EECON1 register commands the erase operation.
The WREN bit must be set to enable write operations.
The FREE bit is set to select an erase operation. For
protection, the write initiate sequence for EECON2
must be used.
6. Set the WR bit. This will begin the Row Erase
cycle.
7. The CPU will stall for duration of the erase for
TIW (see parameter D133A).
8. Re-enable interrupts.
A long write is necessary for erasing the internal Flash.
Instruction execution is halted while in a long write
cycle. The long write will be terminated by the internal
programming timer.
EXAMPLE 6-2:
ERASING A FLASH PROGRAM MEMORY ROW
MOVLW
MOVWF
MOVLW
MOVWF
MOVLW
MOVWF
CODE_ADDR_UPPER
TBLPTRU
CODE_ADDR_HIGH
TBLPTRH
CODE_ADDR_LOW
TBLPTRL
; load TBLPTR with the base
; address of the memory block
ERASE_ROW
BSF
BSF
BCF
MOVLW
MOVWF
MOVLW
MOVWF
BSF
EECON1, WREN
EECON1, FREE
INTCON, GIE
55h
EECON2
0AAh
EECON2
EECON1, WR
INTCON, GIE
; enable write to memory
; enable Row Erase operation
; disable interrupts
Required
Sequence
; write 55h
; write 0AAh
; start erase (CPU stall)
; re-enable interrupts
BSF
DS39774C-page 88
Preliminary
© 2007 Microchip Technology Inc.
PIC18F85J11 FAMILY
The on-chip timer controls the write time. The
write/erase voltages are generated by an on-chip
charge pump, rated to operate over the voltage range
of the device.
6.5
Writing to Flash Program Memory
The minimum programming block is 32 words or
64 bytes. Word or byte programming is not supported.
Table writes are used internally to load the holding
registers needed to program the Flash memory. There
are 64 holding registers used by the table writes for
programming.
Note 1: Unlike previous PIC® MCUs, members of
the PIC18F85J11 family do not reset the
holding registers after a write occurs. The
holding registers must be cleared or over-
written before a programming sequence.
Since the Table Latch (TABLAT) is only a single byte, the
TBLWTinstruction may need to be executed 64 times for
each programming operation. All of the table write oper-
ations will essentially be short writes because only the
holding registers are written. At the end of updating the
64 holding registers, the EECON1 register must be
written to in order to start the programming operation
with a long write.
2: To maintain the endurance of the program
memory cells, each Flash byte should not
be programmed more than one time
between erase operations. Before
attempting to modify the contents of the
target cell a second time, a Row Erase of
the target row, or a Bulk Erase of the
entire memory, must be performed.
The long write is necessary for programming the inter-
nal Flash. Instruction execution is halted while in a long
write cycle. The long write will be terminated by the
internal programming timer.
FIGURE 6-5:
TABLE WRITES TO FLASH PROGRAM MEMORY
TABLAT
Write Register
8
8
8
8
TBLPTR = xxxxx0
TBLPTR = xxxxx1
TBLPTR = xxxxx2
TBLPTR = xxxx3F
Holding Register
Holding Register
Holding Register
Holding Register
Program Memory
8. Disable interrupts.
6.5.1
FLASH PROGRAM MEMORY WRITE
SEQUENCE
9. Write 55h to EECON2.
10. Write 0AAh to EECON2.
The sequence of events for programming an internal
program memory location should be:
11. Set the WR bit. This will begin the write cycle.
12. The CPU will stall for duration of the write for TIW
(see parameter D133A).
1. Read 1024 bytes into RAM.
2. Update data values in RAM as necessary.
13. Re-enable interrupts.
3. Load Table Pointer register with address being
erased.
14. Repeat steps 6 through 13 until all 1024 bytes
are written to program memory.
4. Execute the Row Erase procedure.
15. Verify the memory (table read).
5. Load Table Pointer register with address of first
byte being written, minus 1.
An example of the required code is shown in
Example 6-3 on the following page.
6. Write the 64 bytes into the holding registers with
auto-increment.
Note:
Before setting the WR bit, the Table
Pointer address needs to be within the
intended address range of the 64 bytes in
the holding register.
7. Set the WREN bit (EECON1<2>) to enable byte
writes.
© 2007 Microchip Technology Inc.
Preliminary
DS39774C-page 89
PIC18F85J11 FAMILY
EXAMPLE 6-3:
WRITING TO FLASH PROGRAM MEMORY
MOVLW
MOVWF
MOVLW
MOVWF
MOVLW
MOVWF
CODE_ADDR_UPPER
TBLPTRU
CODE_ADDR_HIGH
TBLPTRH
CODE_ADDR_LOW
TBLPTRL
; Load TBLPTR with the base address
; of the memory block, minus 1
ERASE_BLOCK
BSF
BSF
BCF
EECON1, WREN
EECON1, FREE
INTCON, GIE
55h
EECON2
0AAh
; enable write to memory
; enable Row Erase operation
; disable interrupts
MOVLW
MOVWF
MOVLW
MOVWF
BSF
BSF
MOVLW
MOVWF
; write 55h
EECON2
; write 0AAh
; start erase (CPU stall)
; re-enable interrupts
EECON1, WR
INTCON, GIE
D'16'
WRITE_COUNTER
; Need to write 16 blocks of 64 to write
; one erase block of 1024
RESTART_BUFFER
MOVLW
MOVWF
MOVLW
MOVWF
MOVLW
MOVWF
D'64'
COUNTER
BUFFER_ADDR_HIGH
FSR0H
BUFFER_ADDR_LOW
FSR0L
; point to buffer
FILL_BUFFER
...
; read the new data from I2C, SPI,
; PSP, USART, etc.
WRITE_BUFFER
MOVLW
MOVWF
D’64
COUNTER
; number of bytes in holding register
WRITE_BYTE_TO_HREGS
MOVFF
MOVWF
TBLWT+*
POSTINC0, WREG
TABLAT
; get low byte of buffer data
; present data to table latch
; write data, perform a short write
; to internal TBLWT holding register.
; loop until buffers are full
DECFSZ COUNTER
BRA WRITE_BYTE_TO_HREGS
PROGRAM_MEMORY
BSF
BCF
EECON1, WREN
INTCON, GIE
55h
EECON2
0AAh
; enable write to memory
; disable interrupts
MOVLW
MOVWF
MOVLW
MOVWF
BSF
Required
Sequence
; write 55h
EECON2
; write 0AAh
EECON1, WR
INTCON, GIE
EECON1, WREN
; start program (CPU stall)
; re-enable interrupts
; disable write to memory
BSF
BCF
DECFSZ WRITE_COUNTER
BRA RESTART_BUFFER
; done with one write cycle
; if not done replacing the erase block
DS39774C-page 90
Preliminary
© 2007 Microchip Technology Inc.
PIC18F85J11 FAMILY
6.5.2
WRITE VERIFY
6.6
Flash Program Operation During
Code Protection
Depending on the application, good programming
practice may dictate that the value written to the
memory should be verified against the original value.
This should be used in applications where excessive
writes can stress bits near the specification limit.
See Section 22.6 “Program Verification and Code
Protection” for details on code protection of Flash
program memory.
6.5.3
UNEXPECTED TERMINATION OF
WRITE OPERATION
If a write is terminated by an unplanned event, such as
loss of power or an unexpected Reset, the memory
location just programmed should be verified and repro-
grammed if needed. If the write operation is interrupted
by a MCLR Reset or a WDT Time-out Reset during
normal operation, the user can check the WRERR bit
and rewrite the location(s) as needed.
TABLE 6-2:
Name
REGISTERS ASSOCIATED WITH PROGRAM FLASH MEMORY
Reset
Values on
page
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
TBLPTRU
—
—
bit 21 Program Memory Table Pointer Upper Byte (TBLPTR<20:16>)
51
51
51
51
51
53
53
TBPLTRH Program Memory Table Pointer High Byte (TBLPTR<15:8>)
TBLPTRL Program Memory Table Pointer Low Byte (TBLPTR<7:0>)
TABLAT
INTCON
Program Memory Table Latch
GIE/GIEH PEIE/GIEL TMR0IE
INT0IE
RBIE
TMR0IF
WREN
INT0IF
WR
RBIF
—
EECON2 EEPROM Control Register 2 (not a physical register)
EECON1 FREE WRERR
—
—
—
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used during program memory access.
© 2007 Microchip Technology Inc.
Preliminary
DS39774C-page 91
PIC18F85J11 FAMILY
NOTES:
DS39774C-page 92
Preliminary
© 2007 Microchip Technology Inc.
PIC18F85J11 FAMILY
The bus is implemented with 28 pins, multiplexed
across four I/O ports. Three ports (PORTD, PORTE
and PORTH) are multiplexed with the address/data bus
for a total of 20 available lines, while PORTJ is
multiplexed with the bus control signals.
7.0
EXTERNAL MEMORY BUS
Note:
The external memory bus is not
implemented on 64-pin devices.
The external memory bus allows the device to access
external memory devices (such as Flash, EPROM,
SRAM, etc.) as program or data memory. It supports
both 8 and 16-Bit Data Width modes and three address
widths of up to 20 bits.
A list of the pins and their functions is provided in
Table 7-1.
TABLE 7-1:
Name
PIC18F85J11 FAMILY EXTERNAL BUS – I/O PORT FUNCTIONS
Port
Bit
External Memory Bus Function
RD0/AD0
RD1/AD1
RD2/AD2
RD3/AD3
RD4/AD4
RD5/AD5
RD6/AD6
RD7/AD7
RE0/AD8
RE1/AD9
RE2/AD10
RE3/AD11
RE4/AD12
RE5/AD13
RE6/AD14
RE7/AD15
RH0/A16
RH1/A17
RH2/A18
RH3/A19
RJ0/ALE
RJ1/OE
PORTD
PORTD
PORTD
PORTD
PORTD
PORTD
PORTD
PORTD
PORTE
PORTE
PORTE
PORTE
PORTE
PORTE
PORTE
PORTE
PORTH
PORTH
PORTH
PORTH
PORTJ
PORTJ
PORTJ
PORTJ
PORTJ
PORTJ
PORTJ
PORTJ
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
0
1
2
3
4
5
6
7
Address bit 0 or Data bit 0
Address bit 1 or Data bit 1
Address bit 2 or Data bit 2
Address bit 3 or Data bit 3
Address bit 4 or Data bit 4
Address bit 5 or Data bit 5
Address bit 6 or Data bit 6
Address bit 7 or Data bit 7
Address bit 8 or Data bit 8
Address bit 9 or Data bit 9
Address bit 10 or Data bit 10
Address bit 11 or Data bit 11
Address bit 12 or Data bit 12
Address bit 13 or Data bit 13
Address bit 14 or Data bit 14
Address bit 15 or Data bit 15
Address bit 16
Address bit 17
Address bit 18
Address bit 19
Address Latch Enable (ALE) Control pin
Output Enable (OE) Control pin
Write Low (WRL) Control pin
Write High (WRH) Control pin
Byte Address bit 0 (BA0)
Chip Enable (CE) Control pin
Lower Byte Enable (LB) Control pin
Upper Byte Enable (UB) Control pin
RJ2/WRL
RJ3/WRH
RJ4/BA0
RJ5/CE
RJ6/LB
RJ7/UB
Note:
For the sake of clarity, only I/O port and external bus assignments are shown here. One or more additional
multiplexed features may be available on some pins.
© 2007 Microchip Technology Inc.
Preliminary
DS39774C-page 93
PIC18F85J11 FAMILY
The operation of the EBDIS bit is also influenced by the
Program Memory mode being used. This is discussed
in more detail in Section 7.5 “Program Memory
Modes and the External Memory Bus”.
7.1
External Memory Bus Control
The operation of the interface is controlled by the
MEMCON register (Register 7-1). This register is
available in all Program Memory modes except Micro-
controller mode. In this mode, the register is disabled
and cannot be written to.
The WAIT bits allow for the addition of wait states to
external memory operations. The use of these bits is
discussed in Section 7.3 “Wait States”.
The EBDIS bit (MEMCON<7>) controls the operation
of the bus and related port functions. Clearing EBDIS
enables the interface and disables the I/O functions of
the ports, as well as any other functions multiplexed to
those pins. Setting the bit enables the I/O ports and
other functions, but allows the interface to override
everything else on the pins when an external memory
operation is required. By default, the external bus is
always enabled and disables all other I/O.
The WM bits select the particular operating mode used
when the bus is operating in 16-Bit Data Width mode.
These are discussed in more detail in Section 7.6
“16-Bit Data Width Modes”. These bits have no effect
when an 8-Bit Data Width mode is selected.
REGISTER 7-1:
MEMCON: EXTERNAL MEMORY BUS CONTROL REGISTER
R/W-0
EBDIS
bit 15
U-0
—
R/W-0
WAIT1
R/W-0
WAIT0
U-0
—
U-0
—
R/W-0
WM1
R/W-0
WM0
bit 8
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7
EBDIS: External Bus Disable bit
1= External bus enabled when microcontroller accesses external memory; otherwise, all external bus
drivers are mapped as I/O ports
0= External bus always enabled, I/O ports are disabled
bit 6
Unimplemented: Read as ‘0’
bit 5-4
WAIT1:WAIT0: Table Reads and Writes Bus Cycle Wait Count bits
11= Table reads and writes will wait 0 TCY
10= Table reads and writes will wait 1 TCY
01= Table reads and writes will wait 2 TCY
00= Table reads and writes will wait 3 TCY
bit 3-2
bit 1-0
Unimplemented: Read as ‘0’
WM1:WM0: TBLWTOperation with 16-Bit Data Bus Width Select bits
1x= Word Write mode: TABLAT0 and TABLAT1 word output, WRH active when TABLAT1 written
01= Byte Select mode: TABLAT data copied on both MSB and LSB, WRH and (UB or LB) will activate
00= Byte Write mode: TABLAT data copied on both MSB and LSB, WRH or WRL will activate
DS39774C-page 94
Preliminary
© 2007 Microchip Technology Inc.
PIC18F85J11 FAMILY
7.2.1
ADDRESS SHIFTING ON THE
EXTERNAL BUS
7.2
Address and Data Width
The PIC18F85J11 family of devices can be indepen-
dently configured for different address and data widths
on the same memory bus. Both address and data width
are set by Configuration bits in the CONFIG3L register.
As Configuration bits, this means that these options
can only be configured by programming the device and
are not controllable in software.
By default, the address presented on the external bus
is the value of the PC. In practical terms, this means
that addresses in the external memory device below
the top of on-chip memory are unavailable to the micro-
controller. To access these physical locations, the glue
logic between the microcontroller and the external
memory must somehow translate addresses.
The BW bit selects an 8-bit or 16-bit data bus width.
Setting this bit (default) selects a data width of 16 bits.
To simplify the interface, the external bus offers an
extension of Extended Microcontroller mode that
automatically performs address shifting. This feature is
controlled by the EASHFT Configuration bit. Setting
this bit offsets addresses on the bus by the size of the
microcontroller’s on-chip program memory and sets
the bottom address at 0000h. This allows the device to
use the entire range of physical addresses of the
external memory.
The EMB1:EMB0 bits determine both the Program
Memory mode and the address bus width. The avail-
able options are 20-bit, 16-bit and 12-bit, as well as the
default Microcontroller mode (external bus disabled).
Selecting a 16-bit or 12-bit width makes a correspond-
ing number of high-order lines available for I/O func-
tions; these pins are no longer affected by the setting of
the EBDIS bit. For example, selecting a 16-Bit Address
mode (EMB1:EMB0 = 01) disables A19:A16 and
allows PORTH<3:0> to function without interruptions
from the bus. Using the smaller address widths allows
users to tailor the memory bus to the size of the exter-
nal memory space for a particular design while freeing
up pins for dedicated I/O operation.
7.2.2
21-BIT ADDRESSING
As an extension of 20-bit address width operation, the
external memory bus can also fully address a 2-Mbyte
memory space. This is done by using the Bus Address
bit 0 (BA0) control line as the Least Significant bit of the
address. The UB and LB control signals may also be
used with certain memory devices to select the upper
and lower bytes within a 16-bit wide data word.
Because the EMB bits have the effect of disabling pins
for memory bus operations, it is important to always
select an address width at least equal to the data width.
If a 12-bit address width is used with a 16-bit data
width, the upper four bits of data will not be available on
the bus.
This addressing mode is available in both 8-bit and
certain 16-Bit Data Width modes. Additional details are
provided in Section 7.6.3 “16-Bit Byte Select Mode”
and Section 7.7 “8-Bit Data Width Mode”.
All combinations of address and data widths require
multiplexing of address and data information on the
same lines. The address and data multiplexing, as well
as I/O ports made available by the use of smaller
address widths, are summarized in Table 7-2.
TABLE 7-2:
Data Width
ADDRESS AND DATA LINES FOR DIFFERENT ADDRESS AND DATA WIDTHS
Multiplexed Data and
Address Lines (and
Address-Only
Lines (and
Ports Available
for I/O
Address Width
Corresponding Ports) Corresponding Ports)
AD11:AD8
(PORTE<3:0>)
PORTE<7:4>,
All of PORTH
12-bit
16-bit
AD15:AD8
AD7:AD0
All of PORTH
8-bit
(PORTE<7:0>)
(PORTD<7:0>)
A19:A16, AD15:AD8
(PORTH<3:0>,
20-bit
—
PORTE<7:0>)
16-bit
20-bit
—
All of PORTH
—
AD15:AD0
(PORTD<7:0>,
PORTE<7:0>)
16-bit
A19:A16
(PORTH<3:0>)
© 2007 Microchip Technology Inc.
Preliminary
DS39774C-page 95
PIC18F85J11 FAMILY
If the device fetches or accesses external memory
while EBDIS = 1, the pins will switch to the external
bus. If the EBDIS bit is set by a program executing from
external memory, the action of setting the bit will be
delayed until the program branches into the internal
memory. At that time, the pins will change from external
bus to I/O ports.
7.3
Wait States
While it may be assumed that external memory devices
will operate at the microcontroller clock rate, this is
often not the case. In fact, many devices require longer
times to write or retrieve data than the time allowed by
the execution of table read or table write operations.
To compensate for this, the external memory bus can
be configured to add a fixed delay to each table opera-
tion using the bus. Wait states are enabled by setting
the WAIT Configuration bit. When enabled, the amount
of delay is set by the WAIT1:WAIT0 bits
(MEMCON<5:4>). The delay is based on multiples of
microcontroller instruction cycle time and are added
following the instruction cycle when the table operation
is executed. The range is from no delay to 3 TCY
(default value).
If the device is executing out of internal memory when
EBDIS = 0, the memory bus address/data and control
pins will not be active. They will go to a state where the
active address/data pins are tri-state; the CE, OE,
WRH, WRL, UB and LB signals are ‘1’ and ALE and
BA0 are ‘0’. Note that only those pins associated with
the current address width are forced to tri-state; the
other pins continue to function as I/O. In the case of
16-bit address width, for example, only AD<15:0>
(PORTD and PORTE) are affected; A19:A16
(PORTH<3:0>) continue to function as I/O.
7.4
Port Pin Weak Pull-ups
In all External Memory modes, the bus takes priority
over any other peripherals that may share pins with it.
This includes the Parallel Slave Port and serial commu-
nication modules which would otherwise take priority
over the I/O port.
With the exception of the upper address lines,
A19:A16, the pins associated with the external memory
bus are equipped with weak pull-ups. The pull-ups are
controlled by the upper three bits of the PORTG
register. They are named RDPU, REPU and RJPU and
control pull-ups on PORTD, PORTE and PORTJ,
respectively. Setting one of these bits enables the
corresponding pull-ups for that port. All pull-ups are
disabled by default on all device Resets.
7.6
16-Bit Data Width Modes
In 16-Bit Data Width mode, the external memory
interface can be connected to external memories in
three different configurations:
• 16-Bit Byte Write
• 16-Bit Word Write
• 16-Bit Byte Select
7.5
Program Memory Modes and the
External Memory Bus
The PIC18F85J11 family of devices are capable of
operating in one of two Program Memory modes, using
combinations of on-chip and external program memory.
The functions of the multiplexed port pins depend on
the Program Memory mode selected, as well as the
setting of the EBDIS bit.
The configuration to be used is determined by the
WM1:WM0 bits in the MEMCON register
(MEMCON<1:0>). These three different configurations
allow the designer maximum flexibility in using both
8-bit and 16-bit devices with 16-bit data.
For all 16-Bit Data Width modes, the Address Latch
Enable (ALE) pin indicates that the address bits,
AD<15:0>, are available on the external memory inter-
face bus. Following the address latch, the Output
Enable signal (OE) will enable both bytes of program
memory at once to form a 16-bit instruction word. The
Chip Enable signal (CE) is active at any time that the
microcontroller accesses external memory, whether
reading or writing. It is inactive (asserted high)
whenever the device is in Sleep mode.
In Microcontroller Mode, the bus is not active and the
pins have their port functions only. Writes to the
MEMCOM register are not permitted. The Reset value
of EBDIS (‘0’) is ignored and EMB pins behave as I/O
ports.
In Extended Microcontroller Mode, the external
program memory bus shares I/O port functions on the
pins. When the device is fetching or doing table
read/table write operations on the external program
memory space, the pins will have the external bus
function.
In Byte Select mode, JEDEC standard Flash memories
will require BA0 for the byte address line and one I/O
line to select between Byte and Word mode. The other
16-Bit Data Width modes do not need BA0. JEDEC
standard static RAM memories will use the UB or LB
signals for byte selection.
If the device is fetching and accessing internal program
memory locations only, the EBDIS control bit will
change the pins from external memory to I/O port
functions. When EBDIS = 0, the pins function as the
external bus. When EBDIS = 1, the pins function as I/O
ports.
DS39774C-page 96
Preliminary
© 2007 Microchip Technology Inc.
PIC18F85J11 FAMILY
During a TBLWTinstruction cycle, the TABLAT data is
presented on the upper and lower bytes of the
AD15:AD0 bus. The appropriate WRH or WRL control
line is strobed on the LSb of the TBLPTR.
7.6.1
16-BIT BYTE WRITE MODE
Figure 7-1 shows an example of 16-Bit Byte Write
mode for PIC18F85J11 family devices. This mode is
used for two separate 8-bit memories connected for
16-bit operation. This generally includes basic EPROM
and Flash devices. It allows table writes to byte-wide
external memories.
FIGURE 7-1:
16-BIT BYTE WRITE MODE EXAMPLE
D<7:0>
(MSB)
A<x:0>
(LSB)
PIC18F85J11
AD<7:0>
A<19:0>
D<15:8>
373
373
A<x:0>
D<7:0>
D<7:0>
CE
D<7:0>
CE
AD<15:8>
ALE
(2)
(2)
OE WR
OE WR
(1)
A<19:16>
CE
OE
WRH
WRL
Address Bus
Data Bus
Control Lines
Note 1: Upper order address lines are used only for 20-bit address widths.
2: This signal only applies to table writes. See Section 6.1 “Table Reads and Table Writes”.
© 2007 Microchip Technology Inc.
Preliminary
DS39774C-page 97
PIC18F85J11 FAMILY
During
a
TBLWT cycle to an odd address
7.6.2
16-BIT WORD WRITE MODE
(TBLPTR<0> = 1), the TABLAT data is presented on
the upper byte of the AD15:AD0 bus. The contents of
the holding latch are presented on the lower byte of the
AD15:AD0 bus.
Figure 7-2 shows an example of 16-Bit Word Write
mode for PIC18F85J11 family devices. This mode is
used for word-wide memories which include some of
the EPROM and Flash-type memories. This mode
allows opcode fetches and table reads from all forms of
16-bit memory and table writes to any type of
word-wide external memories. This method makes a
distinction between TBLWT cycles to even or odd
addresses.
The WRH signal is strobed for each write cycle; the
WRL pin is unused. The signal on the BA0 pin indicates
the LSb of the TBLPTR, but it is left unconnected.
Instead, the UB and LB signals are active to select both
bytes. The obvious limitation to this method is that the
table write must be done in pairs on a specific word
boundary to correctly write a word location.
During
a
TBLWT cycle to an even address
(TBLPTR<0> = 0), the TABLAT data is transferred to a
holding latch and the external address data bus is
tri-stated for the data portion of the bus cycle. No write
signals are activated.
FIGURE 7-2:
16-BIT WORD WRITE MODE EXAMPLE
PIC18F85J11
AD<7:0>
A<20:1>
JEDEC Word
A<x:0>
373
373
EPROM Memory
D<15:0>
D<15:0>
(2)
CE
OE
WR
AD<15:8>
ALE
(1)
A<19:16>
CE
OE
WRH
Address Bus
Data Bus
Control Lines
Note 1: Upper order address lines are used only for 20-bit address widths.
2: This signal only applies to table writes. See Section 6.1 “Table Reads and Table Writes”.
DS39774C-page 98
Preliminary
© 2007 Microchip Technology Inc.
PIC18F85J11 FAMILY
Flash and SRAM devices use different control signal
combinations to implement Byte Select mode. JEDEC
standard Flash memories require that a controller I/O
port pin be connected to the memory’s BYTE/WORD
pin to provide the select signal. They also use the BA0
signal from the controller as a byte address. JEDEC
standard static RAM memories, on the other hand, use
the UB or LB signals to select the byte.
7.6.3
16-BIT BYTE SELECT MODE
Figure 7-3 shows an example of 16-Bit Byte Select
mode. This mode allows table write operations to
word-wide external memories with byte selection
capability. This generally includes both word-wide
Flash and SRAM devices.
During a TBLWTcycle, the TABLAT data is presented
on the upper and lower byte of the AD15:AD0 bus. The
WRH signal is strobed for each write cycle; the WRL
pin is not used. The BA0 or UB/LB signals are used to
select the byte to be written, based on the Least
Significant bit of the TBLPTR register.
FIGURE 7-3:
16-BIT BYTE SELECT MODE EXAMPLE
PIC18F85J11
AD<7:0>
A<20:1>
373
373
JEDEC Word
FLASH Memory
A<x:1>
D<15:0>
D<15:0>
(3)
138
CE
A0
AD<15:8>
ALE
(1)
BYTE/WORD OE WR
(2)
A<19:16>
OE
WRH
WRL
A<20:1>
JEDEC Word
A<x:1>
SRAM Memory
BA0
I/O
D<15:0>
D<15:0>
CE
LB
LB
(1)
UB
OE WR
UB
Address Bus
Data Bus
Control Lines
Note 1: This signal only applies to table writes. See Section 6.1 “Table Reads and Table Writes”.
2: Upper order address lines are used only for 20-bit address width.
3: Demultiplexing is only required when multiple memory devices are accessed.
© 2007 Microchip Technology Inc.
Preliminary
DS39774C-page 99
PIC18F85J11 FAMILY
7.6.4
16-BIT MODE TIMING
The presentation of control signals on the external
memory bus is different for the various operating
modes. Typical signal timing diagrams are shown in
Figure 7-4 and Figure 7-5.
FIGURE 7-4:
EXTERNAL MEMORY BUS TIMING FOR TBLRD(EXTENDED
MICROCONTROLLER MODE)
Q1 Q2
Q3
Q4
Q1 Q2
Q3 Q4
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
0Ch
A<19:16>
CF33h
9256h
AD<15:0>
CE
ALE
OE
Opcode Fetch
TBLRD *
from 000100h
Opcode Fetch
MOVLW55h
from 000102h
TBLRD92h
from 199E67h
Opcode Fetch
ADDLW55h
from 000104h
Memory
Cycle
Instruction
Execution
INST(PC – 2)
TBLRDCycle 1
TBLRDCycle 2
MOVLW
FIGURE 7-5:
EXTERNAL MEMORY BUS TIMING FOR SLEEP (EXTENDED
MICROCONTROLLER MODE)
Q1 Q2
Q3
Q4
Q1 Q2
Q3 Q4
Q1
00h
00h
A<19:16>
AD<15:0>
0E55h
0003h
3AAAh
3AABh
CE
ALE
OE
Memory
Cycle
Opcode Fetch
MOVLW55h
Opcode Fetch
SLEEP
Sleep Mode, Bus Inactive
from 007554h
from 007556h
Instruction
Execution
INST(PC – 2)
SLEEP
DS39774C-page 100
Preliminary
© 2007 Microchip Technology Inc.
PIC18F85J11 FAMILY
will enable one byte of program memory for a portion of
the instruction cycle, then BA0 will change and the
second byte will be enabled to form the 16-bit instruc-
tion word. The Least Significant bit of the address, BA0,
must be connected to the memory devices in this
mode. The Chip Enable signal (CE) is active at any
time that the microcontroller accesses external
memory, whether reading or writing. It is inactive
(asserted high) whenever the device is in Sleep mode.
7.7
8-Bit Data Width Mode
In 8-Bit Data Width mode, the external memory bus
operates only in Multiplexed mode; that is, data shares
the 8 Least Significant bits of the address bus.
Figure 7-6 shows an example of 8-Bit Multiplexed
mode for 80-pin devices. This mode is used for a single
8-bit memory connected for 16-bit operation. The
instructions will be fetched as two 8-bit bytes on a
shared data/address bus. The two bytes are sequen-
tially fetched within one instruction cycle (TCY).
Therefore, the designer must choose external memory
devices according to timing calculations based on
1/2 TCY (2 times the instruction rate). For proper mem-
ory speed selection, glue logic propagation delay times
must be considered, along with setup and hold times.
This generally includes basic EPROM and Flash
devices. It allows table writes to byte-wide external
memories.
During a TBLWTinstruction cycle, the TABLAT data is
presented on the upper and lower bytes of the
AD15:AD0 bus. The appropriate level of the BA0
control line is strobed on the LSb of the TBLPTR.
The Address Latch Enable (ALE) pin indicates that the
address bits, AD<15:0>, are available on the external
memory interface bus. The Output Enable signal (OE)
FIGURE 7-6:
8-BIT MULTIPLEXED MODE EXAMPLE
D<7:0>
PIC18F85J11
AD<7:0>
A<19:0>
A<x:1>
373
ALE
A0
D<15:8>
D<7:0>
CE
(1)
AD<15:8>
(1)
A<19:16>
(2)
OE WR
BA0
CE
OE
WRL
Address Bus
Data Bus
Control Lines
Note 1: Upper order address bits are only used 20-bit address width. The upper AD byte is used for all
address widths except 8-bit.
2: This signal only applies to table writes. See Section 6.1 “Table Reads and Table Writes”.
© 2007 Microchip Technology Inc.
Preliminary
DS39774C-page 101
PIC18F85J11 FAMILY
7.7.1
8-BIT MODE TIMING
The presentation of control signals on the external
memory bus is different for the various operating
modes. Typical signal timing diagrams are shown in
Figure 7-7 and Figure 7-8.
FIGURE 7-7:
EXTERNAL MEMORY BUS TIMING FOR TBLRD(EXTENDED
MICROCONTROLLER MODE)
Q1 Q2
Q3
Q4
Q1 Q2
Q3 Q4
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
0Ch
CFh
A<19:16>
AD<15:8>
AD<7:0>
CE
33h
92h
ALE
OE
Opcode Fetch
TBLRD *
from 000100h
Opcode Fetch
MOVLW55h
from 000102h
TBLRD92h
from 199E67h
Opcode Fetch
ADDLW55h
from 000104h
Memory
Cycle
Instruction
Execution
INST(PC – 2)
TBLRDCycle 1
TBLRDCycle 2
MOVLW
FIGURE 7-8:
EXTERNAL MEMORY BUS TIMING FOR SLEEP (EXTENDED
MICROCONTROLLER MODE)
Q1 Q2
Q3
Q4
Q1 Q2
Q3 Q4
Q1
00h
00h
A<19:16>
AD<15:8>
AD<7:0>
3Ah
0Eh 55h
3Ah
00h 03h
AAh
ABh
BA0
CE
ALE
OE
Memory
Cycle
Opcode Fetch
MOVLW55h
Opcode Fetch
Sleep Mode, Bus Inactive
SLEEP
from 007554h
from 007556h
Instruction
Execution
INST(PC – 2)
SLEEP
DS39774C-page 102
Preliminary
© 2007 Microchip Technology Inc.
PIC18F85J11 FAMILY
In Sleep and Idle modes, the microcontroller core does
not need to access data; bus operations are
suspended. The state of the external bus is frozen, with
the address/data pins and most of the control pins hold-
ing at the same state they were in when the mode was
invoked. The only potential changes are the CE, LB
and UB pins, which are held at logic high.
7.8
Operation in Power-Managed
Modes
In alternate, power-managed Run modes, the external
bus continues to operate normally. If a clock source
with a lower speed is selected, bus operations will run
at that speed. In these cases, excessive access times
for the external memory may result if wait states have
been enabled and added to external memory opera-
tions. If operations in a lower power Run mode are
anticipated, users should provide in their applications
for adjusting memory access times at the lower clock
speeds.
© 2007 Microchip Technology Inc.
Preliminary
DS39774C-page 103
PIC18F85J11 FAMILY
NOTES:
DS39774C-page 104
Preliminary
© 2007 Microchip Technology Inc.
PIC18F85J11 FAMILY
EXAMPLE 8-1:
8 x 8 UNSIGNED
MULTIPLY ROUTINE
8.0
8.1
8 x 8 HARDWARE MULTIPLIER
Introduction
MOVF
MULWF
ARG1, W
ARG2
;
; ARG1 * ARG2 ->
; PRODH:PRODL
All PIC18 devices include an 8 x 8 hardware multiplier
as part of the ALU. The multiplier performs an unsigned
operation and yields a 16-bit result that is stored in the
Product register pair, PRODH:PRODL. The multiplier’s
operation does not affect any flags in the STATUS
register.
EXAMPLE 8-2:
8 x 8 SIGNED MULTIPLY
ROUTINE
Making multiplication a hardware operation allows it to
be completed in a single instruction cycle. This has the
advantages of higher computational throughput and
reduced code size for multiplication algorithms and
allows the PIC18 devices to be used in many applica-
tions previously reserved for digital signal processors.
A comparison of various hardware and software
multiply operations, along with the savings in memory
and execution time, is shown in Table 8-1.
MOVF
MULWF
ARG1, W
ARG2
; ARG1 * ARG2 ->
; PRODH:PRODL
; Test Sign Bit
; PRODH = PRODH
BTFSC
SUBWF
ARG2, SB
PRODH, F
;
- ARG1
MOVF
BTFSC
SUBWF
ARG2, W
ARG1, SB
PRODH, F
; Test Sign Bit
; PRODH = PRODH
;
- ARG2
8.2
Operation
Example 8-1 shows the instruction sequence for an 8 x 8
unsigned multiplication. Only one instruction is required
when one of the arguments is already loaded in the
WREG register.
Example 8-2 shows the sequence to do an 8 x 8 signed
multiplication. To account for the sign bits of the argu-
ments, each argument’s Most Significant bit (MSb) is
tested and the appropriate subtractions are done.
TABLE 8-1:
Routine
PERFORMANCE COMPARISON FOR VARIOUS MULTIPLY OPERATIONS
Program
Memory
(Words)
Time
Cycles
(Max)
Multiply Method
@ 40 MHz @ 10 MHz @ 4 MHz
Without hardware multiply
Hardware multiply
13
1
69
1
6.9 µs
100 ns
9.1 µs
600 ns
24.2 µs
2.8 µs
25.4 µs
4.0 µs
27.6 µs
400 ns
36.4 µs
2.4 µs
69 µs
1 µs
8 x 8 unsigned
8 x 8 signed
Without hardware multiply
Hardware multiply
33
6
91
6
91 µs
6 µs
Without hardware multiply
Hardware multiply
21
28
52
35
242
28
254
40
96.8 µs
11.2 µs
102.6 µs
16.0 µs
242 µs
28 µs
254 µs
40 µs
16 x 16 unsigned
16 x 16 signed
Without hardware multiply
Hardware multiply
© 2007 Microchip Technology Inc.
Preliminary
DS39774C-page 105
PIC18F85J11 FAMILY
Example 8-3 shows the sequence to do a 16 x 16
unsigned multiplication. Equation 8-1 shows the
algorithm that is used. The 32-bit result is stored in four
registers (RES3:RES0).
EQUATION 8-2:
16 x 16 SIGNED
MULTIPLICATION
ALGORITHM
RES3:RES0
=
=
ARG1H:ARG1L • ARG2H:ARG2L
(ARG1H • ARG2H • 2 ) +
16
8
EQUATION 8-1:
16 x 16 UNSIGNED
MULTIPLICATION
ALGORITHM
(ARG1H • ARG2L • 2 ) +
(ARG1L • ARG2H • 2 ) +
(ARG1L • ARG2L) +
(-1 • ARG2H<7> • ARG1H:ARG1L • 2 ) +
8
16
RES3:RES0
=
=
ARG1H:ARG1L • ARG2H:ARG2L
16
(-1 • ARG1H<7> • ARG2H:ARG2L • 2
)
16
(ARG1H • ARG2H • 2 ) +
8
(ARG1H • ARG2L • 2 ) +
8
(ARG1L • ARG2H • 2 ) +
EXAMPLE 8-4:
16 x 16 SIGNED
MULTIPLY ROUTINE
(ARG1L • ARG2L)
MOVF
ARG1L, W
MULWF
ARG2L
; ARG1L * ARG2L ->
; PRODH:PRODL
;
;
EXAMPLE 8-3:
16 x 16 UNSIGNED
MULTIPLY ROUTINE
MOVFF
MOVFF
PRODH, RES1
PRODL, RES0
MOVF
ARG1L, W
MULWF
ARG2L
; ARG1L * ARG2L->
; PRODH:PRODL
;
;
;
;
MOVF
MULWF
ARG1H, W
ARG2H
MOVFF
MOVFF
PRODH, RES1
PRODL, RES0
; ARG1H * ARG2H ->
; PRODH:PRODL
;
;
;
;
MOVFF
MOVFF
PRODH, RES3
PRODL, RES2
MOVF
MULWF
ARG1H, W
ARG2H
; ARG1H * ARG2H->
; PRODH:PRODL
;
;
MOVF
MULWF
ARG1L, W
ARG2H
MOVFF
MOVFF
PRODH, RES3
PRODL, RES2
; ARG1L * ARG2H ->
; PRODH:PRODL
;
; Add cross
; products
;
;
;
MOVF
ADDWF
MOVF
ADDWFC RES2, F
CLRF WREG
ADDWFC RES3, F
PRODL, W
RES1, F
PRODH, W
MOVF
MULWF
ARG1L, W
ARG2H
; ARG1L * ARG2H->
; PRODH:PRODL
;
; Add cross
; products
;
;
;
MOVF
ADDWF
MOVF
PRODL, W
RES1, F
PRODH, W
;
ADDWFC RES2, F
CLRF WREG
ADDWFC RES3, F
MOVF
MULWF
ARG1H, W
ARG2L
;
; ARG1H * ARG2L ->
; PRODH:PRODL
;
; Add cross
; products
;
;
;
;
MOVF
ADDWF
MOVF
ADDWFC RES2, F
CLRF WREG
ADDWFC RES3, F
PRODL, W
RES1, F
PRODH, W
MOVF
MULWF
ARG1H, W
ARG2L
;
; ARG1H * ARG2L->
; PRODH:PRODL
;
; Add cross
; products
MOVF
ADDWF
MOVF
PRODL, W
RES1, F
PRODH, W
;
;
ADDWFC RES2, F
CLRF WREG
ADDWFC RES3, F
;
;
;
BTFSS
BRA
MOVF
SUBWF
MOVF
ARG2H, 7
SIGN_ARG1
ARG1L, W
RES2
; ARG2H:ARG2L neg?
; no, check ARG1
;
;
;
Example 8-4 shows the sequence to do a 16 x 16
signed multiply. Equation 8-2 shows the algorithm
used. The 32-bit result is stored in four registers
(RES3:RES0). To account for the sign bits of the
arguments, the MSb for each argument pair is tested
and the appropriate subtractions are done.
ARG1H, W
SUBWFB RES3
SIGN_ARG1
BTFSS
BRA
ARG1H, 7
CONT_CODE
ARG2L, W
RES2
; ARG1H:ARG1L neg?
; no, done
;
;
;
MOVF
SUBWF
MOVF
ARG2H, W
SUBWFB RES3
;
CONT_CODE
:
DS39774C-page 106
Preliminary
© 2007 Microchip Technology Inc.
PIC18F85J11 FAMILY
When the IPEN bit is cleared (default state), the
interrupt priority feature is disabled and interrupts are
compatible with PIC® MCU mid-range devices. In
Compatibility mode, the interrupt priority bits for each
source have no effect. INTCON<6> is the PEIE bit
which enables/disables all peripheral interrupt sources.
INTCON<7> is the GIE bit which enables/disables all
interrupt sources. All interrupts branch to address
0008h in Compatibility mode.
9.0
INTERRUPTS
Members of the PIC18F85J11 family of devices have
multiple interrupt sources and an interrupt priority
feature that allows most interrupt sources to be
assigned a high priority level or a low priority level. The
high priority interrupt vector is at 0008h and the low
priority interrupt vector is at 0018h. High priority inter-
rupt events will interrupt any low priority interrupts that
may be in progress.
When an interrupt is responded to, the global interrupt
enable bit is cleared to disable further interrupts. If the
IPEN bit is cleared, this is the GIE bit. If interrupt priority
levels are used, this will be either the GIEH or GIEL bit.
High priority interrupt sources can interrupt a low
priority interrupt. Low priority interrupts are not
processed while high priority interrupts are in progress.
There are thirteen registers which are used to control
interrupt operation. These registers are:
• RCON
• INTCON
• INTCON2
• INTCON3
The return address is pushed onto the stack and the
PC is loaded with the interrupt vector address (0008h
or 0018h). Once in the Interrupt Service Routine (ISR),
the source(s) of the interrupt can be determined by
polling the interrupt flag bits. The interrupt flag bits must
be cleared in software before re-enabling interrupts to
avoid recursive interrupts.
• PIR1, PIR2, PIR3
• PIE1, PIE2, PIE3
• IPR1, IPR2, IPR3
It is recommended that the Microchip header files
supplied with MPLAB® IDE be used for the symbolic bit
names in these registers. This allows the
assembler/compiler to automatically take care of the
placement of these bits within the specified register.
The “return from interrupt” instruction, RETFIE, exits
the interrupt routine and sets the GIE bit (GIEH or GIEL
if priority levels are used) which re-enables interrupts.
In general, interrupt sources have three bits to control
their operation. They are:
For external interrupt events, such as the INTx pins or
the PORTB input change interrupt, the interrupt latency
will be three to four instruction cycles. The exact
latency is the same for one or two-cycle instructions.
Individual interrupt flag bits are set regardless of the
status of their corresponding enable bit or the GIE bit.
• Flag bit to indicate that an interrupt event
occurred
• Enable bit that allows program execution to
branch to the interrupt vector address when the
flag bit is set
Note:
Do not use the MOVFFinstruction to modify
any of the Interrupt Control registers while
any interrupt is enabled. Doing so may
cause erratic microcontroller behavior.
• Priority bit to select high priority or low priority
The interrupt priority feature is enabled by setting the
IPEN bit (RCON<7>). When interrupt priority is
enabled, there are two bits which enable interrupts
globally. Setting the GIEH bit (INTCON<7>) enables all
interrupts that have the priority bit set (high priority).
Setting the GIEL bit (INTCON<6>) enables all
interrupts that have the priority bit cleared (low priority).
When the interrupt flag, enable bit and appropriate
global interrupt enable bit are set, the interrupt will
vector immediately to address 0008h or 0018h,
depending on the priority bit setting. Individual
interrupts can be disabled through their corresponding
enable bits.
© 2007 Microchip Technology Inc.
Preliminary
DS39774C-page 107
PIC18F85J11 FAMILY
FIGURE 9-1:
PIC18F85J11 FAMILY INTERRUPT LOGIC
Wake-up if in
Idle or Sleep modes
TMR0IF
TMR0IE
TMR0IP
RBIF
RBIE
RBIP
INT0IF
INT0IE
INT1IF
INT1IE
INT1IP
INT2IF
INT2IE
INT2IP
INT3IF
INT3IE
INT3IP
Interrupt to CPU
Vector to Location
0008h
PIR1<6:3,1:0>
PIE1<6:3,1:0>
IPR1<6:3,1:0>
GIE/GIEH
PIR2<7:6,3:1>
PIE2<7:6 3:1>
IPR2<7:6,3:1>
IPEN
PIR3<6:4,2:1>
PIE3<6:4,2:1>
IPR3<6:4,2:1>
IPEN
PEIE/GIEL
IPEN
High Priority Interrupt Generation
Low Priority Interrupt Generation
PIR1<6:3,1:0>
PIE1<6:3,1:0>
IPR1<6:3,1:0>
PIR2<7:6,3:1>
PIE2<7:6,3:1>
IPR2<7:6,3:1>
Interrupt to CPU
Vector to Location
0018h
TMR0IF
TMR0IE
TMR0IP
IPEN
PIR3<6:4,2:1>
PIE3<6:4,2:1>
IPR3<6:4,2:1>
RBIF
RBIE
RBIP
GIE/GIEH
PEIE/GIEL
INT1IF
INT1IE
INT1IP
INT2IF
INT2IE
INT2IP
INT3IF
INT3IE
INT3IP
DS39774C-page 108
Preliminary
© 2007 Microchip Technology Inc.
PIC18F85J11 FAMILY
9.1
INTCON Registers
Note:
Interrupt flag bits are set when an interrupt
condition occurs regardless of the state of
its corresponding enable bit or the global
interrupt enable bit. User software should
ensure the appropriate interrupt flag bits
are clear prior to enabling an interrupt.
This feature allows for software polling.
The INTCON registers are readable and writable
registers which contain various enable, priority and flag
bits.
REGISTER 9-1:
INTCON: INTERRUPT CONTROL REGISTER
R/W-0
R/W-0
PEIE/GIEL
R/W-0
R/W-0
R/W-0
RBIE
R/W-0
R/W-0
INT0IF
R/W-x
RBIF(1)
GIE/GIEH
bit 7
TMR0IE
INT0IE
TMR0IF
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7
GIE/GIEH: Global Interrupt Enable bit
When IPEN = 0:
1= Enables all unmasked interrupts
0= Disables all interrupts
When IPEN = 1:
1= Enables all high priority interrupts
0= Disables all interrupts
bit 6
PEIE/GIEL: Peripheral Interrupt Enable bit
When IPEN = 0:
1= Enables all unmasked peripheral interrupts
0= Disables all peripheral interrupts
When IPEN = 1:
1= Enables all low priority peripheral interrupts
0= Disables all low priority peripheral interrupts
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
TMR0IE: TMR0 Overflow Interrupt Enable bit
1= Enables the TMR0 overflow interrupt
0= Disables the TMR0 overflow interrupt
INT0IE: INT0 External Interrupt Enable bit
1= Enables the INT0 external interrupt
0= Disables the INT0 external interrupt
RBIE: RB Port Change Interrupt Enable bit
1= Enables the RB port change interrupt
0= Disables the RB port change interrupt
TMR0IF: TMR0 Overflow Interrupt Flag bit
1= TMR0 register has overflowed (must be cleared in software)
0= TMR0 register did not overflow
INT0IF: INT0 External Interrupt Flag bit
1= The INT0 external interrupt occurred (must be cleared in software)
0= The INT0 external interrupt did not occur
RBIF: RB Port Change Interrupt Flag bit(1)
1= At least one of the RB7:RB4 pins changed state (must be cleared in software)
0= None of the RB7:RB4 pins have changed state
Note 1: A mismatch condition will continue to set this bit. Reading PORTB will end the mismatch condition and
allow the bit to be cleared.
© 2007 Microchip Technology Inc.
Preliminary
DS39774C-page 109
PIC18F85J11 FAMILY
REGISTER 9-2:
INTCON2: INTERRUPT CONTROL REGISTER 2
R/W-1
R/W-1
INTEDG0
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
RBIP
RBPU
bit 7
INTEDG1
INTEDG2
INTEDG3
TMR0IP
INT3IP
bit 0
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
-n = Value at POR
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
RBPU: PORTB Pull-up Enable bit
1= All PORTB pull-ups are disabled
0= PORTB pull-ups are enabled by individual port latch values
INTEDG0: External Interrupt 0 Edge Select bit
1= Interrupt on rising edge
0= Interrupt on falling edge
INTEDG1: External Interrupt 1 Edge Select bit
1= Interrupt on rising edge
0= Interrupt on falling edge
INTEDG2: External Interrupt 2 Edge Select bit
1= Interrupt on rising edge
0= Interrupt on falling edge
INTEDG3: External Interrupt 3 Edge Select bit
1= Interrupt on rising edge
0= Interrupt on falling edge
TMR0IP: TMR0 Overflow Interrupt Priority bit
1= High priority
0= Low priority
INT3IP: INT3 External Interrupt Priority bit
1= High priority
0= Low priority
RBIP: RB Port Change Interrupt Priority bit
1= High priority
0= Low priority
Note:
Interrupt flag bits are set when an interrupt condition occurs regardless of the state of its corresponding
enable bit or the global interrupt enable bit. User software should ensure the appropriate interrupt flag bits
are clear prior to enabling an interrupt. This feature allows for software polling.
DS39774C-page 110
Preliminary
© 2007 Microchip Technology Inc.
PIC18F85J11 FAMILY
REGISTER 9-3:
INTCON3: INTERRUPT CONTROL REGISTER 3
R/W-1
INT2IP
bit 7
R/W-1
R/W-0
R/W-0
R/W-0
R/W-0
INT3IF
R/W-0
INT2IF
R/W-0
INT1IF
INT1IP
INT3IE
INT2IE
INT1IE
bit 0
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
-n = Value at POR
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
INT2IP: INT2 External Interrupt Priority bit
1= High priority
0= Low priority
INT1IP: INT1 External Interrupt Priority bit
1= High priority
0= Low priority
INT3IE: INT3 External Interrupt Enable bit
1= Enables the INT3 external interrupt
0= Disables the INT3 external interrupt
INT2IE: INT2 External Interrupt Enable bit
1= Enables the INT2 external interrupt
0= Disables the INT2 external interrupt
INT1IE: INT1 External Interrupt Enable bit
1= Enables the INT1 external interrupt
0= Disables the INT1 external interrupt
INT3IF: INT3 External Interrupt Flag bit
1= The INT3 external interrupt occurred (must be cleared in software)
0= The INT3 external interrupt did not occur
INT2IF: INT2 External Interrupt Flag bit
1= The INT2 external interrupt occurred (must be cleared in software)
0= The INT2 external interrupt did not occur
INT1IF: INT1 External Interrupt Flag bit
1= The INT1 external interrupt occurred (must be cleared in software)
0= The INT1 external interrupt did not occur
Note:
Interrupt flag bits are set when an interrupt condition occurs regardless of the state of its corresponding
enable bit or the global interrupt enable bit. User software should ensure the appropriate interrupt flag bits
are clear prior to enabling an interrupt. This feature allows for software polling.
© 2007 Microchip Technology Inc.
Preliminary
DS39774C-page 111
PIC18F85J11 FAMILY
9.2
PIR Registers
Note 1: Interrupt flag bits are set when an interrupt
condition occurs regardless of the state of
its corresponding enable bit or the Global
Interrupt Enable bit, GIE (INTCON<7>).
The PIR registers contain the individual flag bits for the
peripheral interrupts. Due to the number of peripheral
interrupt sources, there are three Peripheral Interrupt
Request (Flag) registers (PIR1, PIR2, PIR3).
2: User software should ensure the
appropriate interrupt flag bits are cleared
prior to enabling an interrupt and after
servicing that interrupt.
REGISTER 9-4:
PIR1: PERIPHERAL INTERRUPT REQUEST (FLAG) REGISTER 1
R/W-0
PSPIF
bit 7
R/W-0
ADIF
R-0
R-0
R/W-0
SSPIF
U-0
—
R/W-0
R/W-0
RC1IF
TX1IF
TMR2IF
TMR1IF
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7
bit 6
bit 5
bit 4
bit 3
PSPIF: Parallel Slave Port Read/Write Interrupt Flag bit
1= A read or a write operation has taken place (must be cleared in software)
0= No read or write has occurred
ADIF: A/D Converter Interrupt Flag bit
1= An A/D conversion completed (must be cleared in software)
0= The A/D conversion is not complete
RC1IF: EUSART Receive Interrupt Flag bit
1= The EUSART receive buffer, RCREG1, is full (cleared when RCREG1 is read)
0= The EUSART receive buffer is empty
TX1IF: EUSART Transmit Interrupt Flag bit
1= The EUSART transmit buffer, TXREG1, is empty (cleared when TXREG1 is written)
0= The EUSART transmit buffer is full
SSPIF: Master Synchronous Serial Port Interrupt Flag bit
1= The transmission/reception is complete (must be cleared in software)
0= Waiting to transmit/receive
bit 2
bit 1
Unimplemented: Read as ‘0’
TMR2IF: TMR2 to PR2 Match Interrupt Flag bit
1= TMR2 to PR2 match occurred (must be cleared in software)
0= No TMR2 to PR2 match occurred
bit 0
TMR1IF: TMR1 Overflow Interrupt Flag bit
1= TMR1 register overflowed (must be cleared in software)
0= TMR1 register did not overflow
DS39774C-page 112
Preliminary
© 2007 Microchip Technology Inc.
PIC18F85J11 FAMILY
REGISTER 9-5:
PIR2: PERIPHERAL INTERRUPT REQUEST (FLAG) REGISTER 2
R/W-0
OSCFIF
bit 7
R/W-0
CMIF
U-0
—
U-0
—
R/W-0
BCLIF
R/W-0
LVDIF
R/W-0
U-0
—
TMR3IF
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7
bit 6
OSCFIF: Oscillator Fail Interrupt Flag bit
1= Device oscillator failed, clock input has changed to INTOSC (must be cleared in software)
0= Device clock operating
CMIF: Comparator Interrupt Flag bit
1= Comparator input has changed (must be cleared in software)
0= Comparator input has not changed
bit 5-4
bit 3
Unimplemented: Read as ‘0’
BCLIF: Bus Collision Interrupt Flag bit
1= A bus collision occurred (must be cleared in software)
0= No bus collision occurred
bit 2
bit 1
bit 0
LVDIF: Low-Voltage Detect Interrupt Flag bit
1= A low-voltage condition occurred (must be cleared in software)
0= The device voltage is above the regulator’s low-voltage trip point
TMR3IF: TMR3 Overflow Interrupt Flag bit
1= TMR3 register overflowed (must be cleared in software)
0= TMR3 register did not overflow
Unimplemented: Read as ‘0’
© 2007 Microchip Technology Inc.
Preliminary
DS39774C-page 113
PIC18F85J11 FAMILY
REGISTER 9-6:
PIR3: PERIPHERAL INTERRUPT REQUEST (FLAG) REGISTER 3
U-0
—
U-0
—
R-0
R-0
U-0
—
R/W-0
R/W-0
U-0
—
RC2IF
TX2IF
CCP2IF
CCP1IF
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7-6
bit 5
Unimplemented: Read as ‘0’
RC2IF: AUSART Receive Interrupt Flag bit
1= The AUSART receive buffer, RCREG2, is full (cleared when RCREG2 is read)
0= The AUSART receive buffer is empty
bit 4
TX2IF: AUSART Transmit Interrupt Flag bit
1= The AUSART transmit buffer, TXREG2, is empty (cleared when TXREG2 is written)
0= The AUSART transmit buffer is full
bit 3
bit 2
Unimplemented: Read as ‘0’
CCP2IF: CCP2 Interrupt Flag bit
Capture mode:
1= A TMR1/TMR3 register capture occurred (must be cleared in software)
0= No TMR1/TMR3 register capture occurred
Compare mode:
1= A TMR1/TMR3 register compare match occurred (must be cleared in software)
0= No TMR1/TMR3 register compare match occurred
PWM mode:
Unused in this mode.
bit 1
CCP1IF: CCP1 Interrupt Flag bit
Capture mode:
1= A TMR1/TMR3 register capture occurred (must be cleared in software)
0= No TMR1/TMR3 register capture occurred
Compare mode:
1= A TMR1/TMR3 register compare match occurred (must be cleared in software)
0= No TMR1/TMR3 register compare match occurred
PWM mode:
Unused in this mode.
bit 0
Unimplemented: Read as ‘0’
DS39774C-page 114
Preliminary
© 2007 Microchip Technology Inc.
PIC18F85J11 FAMILY
9.3
PIE Registers
The PIE registers contain the individual enable bits for
the peripheral interrupts. Due to the number of
peripheral interrupt sources, there are three Peripheral
Interrupt Enable registers (PIE1, PIE2, PIE3). When
IPEN = 0, the PEIE bit must be set to enable any of
these peripheral interrupts.
REGISTER 9-7:
PIE1: PERIPHERAL INTERRUPT ENABLE REGISTER 1
R/W-0
PSPIE
bit 7
R/W-0
ADIE
R/W-0
RC1IE
R/W-0
TX1IE
R/W-0
SSPIE
U-0
—
R/W-0
R/W-0
TMR2IE
TMR1IE
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7
bit 6
bit 5
bit 4
bit 3
PSPIE: Parallel Slave Port Read/Write Interrupt Enable bit
1= Enables the PSP read/write interrupt
0= Disables the PSP read/write interrupt
ADIE: A/D Converter Interrupt Enable bit
1= Enables the A/D interrupt
0= Disables the A/D interrupt
RC1IE: EUSART Receive Interrupt Enable bit
1= Enables the EUSART receive interrupt
0= Disables the EUSART receive interrupt
TX1IE: EUSART Transmit Interrupt Enable bit
1= Enables the EUSART transmit interrupt
0= Disables the EUSART transmit interrupt
SSPIE: Master Synchronous Serial Port Interrupt Enable bit
1= Enables the MSSP interrupt
0= Disables the MSSP interrupt
bit 2
bit 1
Unimplemented: Read as ‘0’
TMR2IE: TMR2 to PR2 Match Interrupt Enable bit
1= Enables the TMR2 to PR2 match interrupt
0= Disables the TMR2 to PR2 match interrupt
bit 0
TMR1IE: TMR1 Overflow Interrupt Enable bit
1= Enables the TMR1 overflow interrupt
0= Disables the TMR1 overflow interrupt
© 2007 Microchip Technology Inc.
Preliminary
DS39774C-page 115
PIC18F85J11 FAMILY
REGISTER 9-8:
PIE2: PERIPHERAL INTERRUPT ENABLE REGISTER 2
R/W-0
OSCFIE
bit 7
R/W-0
CMIE
U-0
—
U-0
—
R/W-0
BCLIE
R/W-0
LVDIE
R/W-0
U-0
—
TMR3IE
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7
bit 6
OSCFIE: Oscillator Fail Interrupt Enable bit
1= Enabled
0= Disabled
CMIE: Comparator Interrupt Enable bit
1= Enabled
0= Disabled
bit 5-4
bit 3
Unimplemented: Read as ‘0’
BCLIE: Bus Collision Interrupt Enable bit
1= Enabled
0= Disabled
bit 2
bit 1
bit 0
LVDIE: Low-Voltage Detect Interrupt Enable bit
1= Enabled
0= Disabled
TMR3IE: TMR3 Overflow Interrupt Enable bit
1= Enabled
0= Disabled
Unimplemented: Read as ‘0’
DS39774C-page 116
Preliminary
© 2007 Microchip Technology Inc.
PIC18F85J11 FAMILY
REGISTER 9-9:
PIE3: PERIPHERAL INTERRUPT ENABLE REGISTER 3
U-0
—
U-0
—
R-0
R-0
U-0
—
R/W-0
R/W-0
U-0
—
RC2IE
TX2IE
CCP2IE
CCP1IE
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7-6
bit 5
Unimplemented: Read as ‘0’
RC2IE: AUSART Receive Interrupt Enable bit
1= Enabled
0= Disabled
bit 4
TX2IE: AUSART Transmit Interrupt Enable bit
1= Enabled
0= Disabled
bit 3
bit 2
Unimplemented: Read as ‘0’
CCP2IE: CCP2 Interrupt Enable bit
1= Enabled
0= Disabled
bit 1
bit 0
CCP1IE: CCP1 Interrupt Enable bit
1= Enabled
0= Disabled
Unimplemented: Read as ‘0’
© 2007 Microchip Technology Inc.
Preliminary
DS39774C-page 117
PIC18F85J11 FAMILY
9.4
IPR Registers
The IPR registers contain the individual priority bits for
the peripheral interrupts. Due to the number of
peripheral interrupt sources, there are three Peripheral
Interrupt Priority registers (IPR1, IPR2, IPR3). Using
the priority bits requires that the Interrupt Priority
Enable (IPEN) bit be set.
REGISTER 9-10: IPR1: PERIPHERAL INTERRUPT PRIORITY REGISTER 1
R/W-1
PSPIP
R/W-1
ADIP
R/W-1
RC1IP
R/W-1
TX1IP
R/W-1
SSPIP
U-0
—
R/W-1
R/W-1
TMR2IP
TMR1IP
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7
bit 6
bit 5
bit 4
PSPIP: Parallel Slave Port Read/Write Interrupt Priority bit
1= High priority
0= Low priority
ADIP: A/D Converter Interrupt Priority bit
1= High priority
0= Low priority
RC1IP: EUSART Receive Interrupt Priority bit
1= High priority
0= Low priority
TX1IP: EUSART Transmit Interrupt Priority bit
1= High priority
0= Low priority
bit 3
SSPIP: Master Synchronous Serial Port Interrupt Priority bit
1= High priority
0= Low priority
bit 2
bit 1
Unimplemented: Read as ‘0’
TMR2IP: TMR2 to PR2 Match Interrupt Priority bit
1= High priority
0= Low priority
bit 0
TMR1IP: TMR1 Overflow Interrupt Priority bit
1= High priority
0= Low priority
DS39774C-page 118
Preliminary
© 2007 Microchip Technology Inc.
PIC18F85J11 FAMILY
REGISTER 9-11: IPR2: PERIPHERAL INTERRUPT PRIORITY REGISTER 2
R/W-1
R/W-1
CMIP
U-0
—
U-0
—
R/W-1
BCLIP
R/W-1
LVDIP
R/W-1
U-0
—
OSCFIP
TMR3IP
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7
bit 6
OSCFIP: Oscillator Fail Interrupt Priority bit
1= High priority
0= Low priority
CMIP: Comparator Interrupt Priority bit
1= High priority
0= Low priority
bit 5-4
bit 3
Unimplemented: Read as ‘0’
BCLIP: Bus Collision Interrupt Priority bit
1= High priority
0= Low priority
bit 2
bit 1
bit 0
LVDIP: Low-Voltage Detect Interrupt Priority bit
1= High priority
0= Low priority
TMR3IP: TMR3 Overflow Interrupt Priority bit
1= High priority
0= Low priority
Unimplemented: Read as ‘0’
© 2007 Microchip Technology Inc.
Preliminary
DS39774C-page 119
PIC18F85J11 FAMILY
REGISTER 9-12: IPR3: PERIPHERAL INTERRUPT PRIORITY REGISTER 3
U-0
—
U-0
—
R-0
R-0
U-0
—
R/W-1
R/W-1
U-0
—
RC2IP
TX2IP
CCP2IP
CCP1IP
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7-6
bit 5
Unimplemented: Read as ‘0’
RC2IP: AUSART Receive Priority Flag bit
1= High priority
0= Low priority
bit 4
TX2IP: AUSART Transmit Interrupt Priority bit
1= High priority
0= Low priority
bit 3
bit 2
Unimplemented: Read as ‘0’
CCP2IP: CCP2 Interrupt Priority bit
1= High priority
0= Low priority
bit 1
bit 0
CCP1IP: CCP1 Interrupt Priority bit
1= High priority
0= Low priority
Unimplemented: Read as ‘0’
DS39774C-page 120
Preliminary
© 2007 Microchip Technology Inc.
PIC18F85J11 FAMILY
9.5
RCON Register
The RCON register contains bits used to determine the
cause of the last Reset or wake-up from Idle or Sleep
modes. RCON also contains the bit that enables
interrupt priorities (IPEN).
REGISTER 9-13: RCON: RESET CONTROL REGISTER
R/W-0
IPEN
U-0
—
R/W-1
CM
R/W-1
RI
R-1
TO
R-1
PD
R/W-0
POR
R/W-0
BOR
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7
IPEN: Interrupt Priority Enable bit
1= Enable priority levels on interrupts
0= Disable priority levels on interrupts (PIC16CXXX Compatibility mode)
bit 6
bit 5
Unimplemented: Read as ‘0’
CM: Configuration Mismatch Flag bit
For details of bit operation, see Register 4-1.
RI: RESETInstruction Flag bit
bit 4
bit 3
bit 2
bit 1
bit 0
For details of bit operation, see Register 4-1.
TO: Watchdog Timer Time-out Flag bit
For details of bit operation, see Register 4-1.
PD: Power-Down Detection Flag bit
For details of bit operation, see Register 4-1.
POR: Power-on Reset Status bit
For details of bit operation, see Register 4-1.
BOR: Brown-out Reset Status bit
For details of bit operation, see Register 4-1.
© 2007 Microchip Technology Inc.
Preliminary
DS39774C-page 121
PIC18F85J11 FAMILY
9.6
INTx Pin Interrupts
9.7
TMR0 Interrupt
External interrupts on the RB0/INT0, RB1/INT1,
RB2/INT2 and RB3/INT3 pins are edge-triggered. If the
corresponding INTEDGx bit in the INTCON2 register is
set (= 1), the interrupt is triggered by a rising edge; if
the bit is clear, the trigger is on the falling edge. When
a valid edge appears on the RBx/INTx pin, the
corresponding flag bit, INTxIF, is set. This interrupt can
be disabled by clearing the corresponding enable bit,
INTxIE. Flag bit, INTxIF, must be cleared in software in
the Interrupt Service Routine before re-enabling the
interrupt.
In 8-bit mode (which is the default), an overflow in the
TMR0 register (FFh → 00h) will set flag bit, TMR0IF. In
16-bit mode, an overflow in the TMR0H:TMR0L register
pair (FFFFh → 0000h) will set TMR0IF. The interrupt can
be enabled/disabled by setting/clearing enable bit,
TMR0IE (INTCON<5>). Interrupt priority for Timer0 is
determined by the value contained in the interrupt priority
bit, TMR0IP (INTCON2<2>). See Section 11.0 “Timer0
Module” for further details on the Timer0 module.
9.8
PORTB Interrupt-on-Change
All external interrupts (INT0, INT1, INT2 and INT3) can
wake-up the processor from the power-managed
modes if bit INTxIE was set prior to going into the
power-managed modes. If the Global Interrupt Enable
bit, GIE, is set, the processor will branch to the interrupt
vector following wake-up.
An input change on PORTB<7:4> sets flag bit, RBIF
(INTCON<0>). The interrupt can be enabled/disabled
by setting/clearing enable bit, RBIE (INTCON<3>).
Interrupt priority for PORTB interrupt-on-change is
determined by the value contained in the interrupt
priority bit, RBIP (INTCON2<0>).
Interrupt priority for INT1, INT2 and INT3 is determined
by the value contained in the interrupt priority bits,
INT1IP (INTCON3<6>), INT2IP (INTCON3<7>) and
INT3IP (INTCON2<1>). There is no priority bit
associated with INT0. It is always a high priority
interrupt source.
9.9
Context Saving During Interrupts
During interrupts, the return PC address is saved on
the stack. Additionally, the WREG, STATUS and BSR
registers are saved on the Fast Return Stack. If a fast
return from interrupt is not used (see Section 5.3
“Data Memory Organization”), the user may need to
save the WREG, STATUS and BSR registers on entry
to the Interrupt Service Routine. Depending on the
user’s application, other registers may also need to be
saved. Example 9-1 saves and restores the WREG,
STATUS and BSR registers during an Interrupt Service
Routine.
EXAMPLE 9-1:
SAVING STATUS, WREG AND BSR REGISTERS IN RAM
MOVWF
MOVFF
MOVFF
;
W_TEMP
STATUS, STATUS_TEMP
BSR, BSR_TEMP
; W_TEMP is in virtual bank
; STATUS_TEMP located anywhere
; BSR_TMEP located anywhere
; USER ISR CODE
;
MOVFF
MOVF
MOVFF
BSR_TEMP, BSR
W_TEMP, W
STATUS_TEMP, STATUS
; Restore BSR
; Restore WREG
; Restore STATUS
DS39774C-page 122
Preliminary
© 2007 Microchip Technology Inc.
PIC18F85J11 FAMILY
10.1 I/O Port Pin Capabilities
10.0 I/O PORTS
When developing an application, the capabilities of the
port pins must be considered. Outputs on some pins
have higher output drive strength than others. Similarly,
some pins can tolerate higher than VDD input levels.
Depending on the device selected and features
enabled, there are up to nine ports available. Some
pins of the I/O ports are multiplexed with an alternate
function from the peripheral features on the device. In
general, when a peripheral is enabled, that pin may not
be used as a general purpose I/O pin.
10.1.1
INPUT PINS AND VOLTAGE
CONSIDERATIONS
Each port has three memory mapped registers for its
operation:
The voltage tolerance of pins used as device inputs is
dependent on the pin’s input function. Pins that are used
as digital only inputs are able to handle DC voltages up
to 5.5V, a level typical for digital logic circuits. In contrast,
pins that also have analog input functions of any kind
can only tolerate voltages up to VDD. Voltage excursions
beyond VDD on these pins should be avoided.
• TRIS register (Data Direction register)
• PORT register (reads the levels on the pins of the
device)
• LAT register (Output Latch register)
Reading the PORT register reads the current status of
the pins, whereas writing to the PORT register writes to
the Output Latch (LAT) register.
Table 10-1 summarizes the input voltage capabilities.
Refer to Section 25.0 “Electrical Characteristics” for
more details.
Setting a TRIS bit (= 1) makes the corresponding
PORT pin an input (i.e., put the corresponding output
driver in a High-Impedance mode). Clearing a TRIS bit
(= 0) makes the corresponding PORT pin an output
(i.e., put the contents of the corresponding LAT bit on
the selected pin).
TABLE 10-1: INPUT VOLTAGE TOLERANCE
Tolerated
Port or Pin
Description
Input
PORTA<7:0>
PORTC<1:0>
PORTF<7:1>
PORTB<7:0>
PORTC<7:2>
PORTD<7:0>
PORTE<7:0>
PORTG<4:0>
PORTH<7:0>(1)
PORTJ<7:0>(1)
VDD
Only VDD input levels
tolerated.
The Output Latch (LAT register) is useful for
read-modify-write operations on the value that the I/O
pins are driving. Read-modify-write operations on the
LAT register read and write the latched output value for
the PORT register.
5.5V
Tolerates input levels
above VDD, useful for
most standard logic.
A simplified model of a generic I/O port, without the
interfaces to other peripherals, is shown in Figure 10-1.
FIGURE 10-1:
GENERIC I/O PORT
OPERATION
RD LAT
Note 1: Not available on 64-pin devices.
Data
Bus
D
Q
10.1.2 PIN OUTPUT DRIVE
I/O pin(1)
WR LAT
or PORT
When used as digital I/O, the output pin drive strengths
vary for groups of pins intended to meet the needs for
a variety of applications. In general, there are three
classes of output pins in terms of drive capability.
CK
Data Latch
D
Q
PORTB and PORTC, as well as PORTA<7:6>, are
designed to drive higher current loads, such as LEDs.
PORTD, PORTE and PORTJ are capable of driving
digital circuits associated with external memory
devices. They can also drive LEDs, but only those with
smaller current requirements. PORTF, PORTG and
PORTH, along with PORTA<5:0>, have the lowest
drive level, but are capable of driving normal digital
circuit loads with a high input impedance.
WR TRIS
RD TRIS
CK
TRIS Latch
Input
Buffer
D
Q
Table 10-2 summarizes the output capabilities of the
ports. Refer to the “Absolute Maximum Ratings” in
Section 25.0 “Electrical Characteristics” for more
details.
EN
RD PORT
Note 1: I/O pins have diode protection to VDD and VSS.
© 2007 Microchip Technology Inc.
Preliminary
DS39774C-page 123
PIC18F85J11 FAMILY
TABLE 10-2: OUTPUT DRIVE LEVELS FOR
VARIOUS PORTS
10.2 PORTA, TRISA and
LATA Registers
Low
Medium
PORTD
High
PORTA is an 8-bit wide, bidirectional port. The corre-
sponding Data Direction and Output Latch registers are
TRISA and LATA.
PORTA<5:0>
PORTF
PORTA<7:6>
PORTB
PORTE
RA4/T0CKI is a Schmitt Trigger input. All other PORTA
pins have TTL input levels and full CMOS output
drivers.
PORTG
PORTH(1)
PORTJ(1)
PORTC
Note 1: Not available on 64-pin devices.
The RA4 pin is multiplexed with the Timer0 clock input.
RA5 and RA3:RA0 are multiplexed with analog inputs
for the A/D converter.
10.1.3 PULL-UP CONFIGURATION
Four of the I/O ports (PORTB, PORTD, PORTE and
PORTJ) implement configurable weak pull-ups on all
pins. These are internal pull-ups that allow floating
digital input signals to be pulled to a consistent level
without the use of external resistors.
The operation of the analog inputs as A/D converter
inputs is selected by clearing or setting the
PCFG3:PCFG0 control bits in the ADCON1 register.
The corresponding TRISA bits control the direction of
these pins, even when they are being used as analog
inputs. The user must ensure the bits in the TRISA
register are maintained set when using them as analog
inputs.
The pull-ups are enabled with a single bit for each of the
ports: RBPU (INTCON2<7>) for PORTB, and RDPU,
REPU and RJPU (PORTG<7:5>) for the other ports.
Note:
RA5 and RA3:RA0 are configured as
analog inputs on any Reset and are read
as ‘0’. RA4 is configured as a digital input.
10.1.4
OPEN-DRAIN OUTPUTS
The output pins for several peripherals are also
equipped with a configurable open-drain output option.
This allows the peripherals to communicate with
external digital logic, operating at a higher voltage
level, without the use of level translators.
RA6/OSC2/CLKO and RA7/OSC1/CLKI normally
serve as the external circuit connections for the exter-
nal (primary) oscillator circuit (HS Oscillator modes), or
the external clock input and output (EC Oscillator
modes). In these cases, RA6 and RA7 are not available
as digital I/O and their corresponding TRIS and LAT
bits are read as ‘0’. When the device is configured to
use INTOSC or INTRC as the default oscillator mode
(FOSC2 Configuration bit is ‘0’), RA6 and RA7 are
automatically configured as digital I/O; the oscillator
and clock in/clock out functions are disabled.
The open-drain option is implemented on port pins
specifically associated with the data and clock outputs
of the USARTs, the MSSP module (in SPI mode) and
the CCP modules. The option is selectively enabled by
setting the open-drain control bit for the corresponding
module in TRISG and LATG. Their configuration is dis-
cussed in more detail in the sections for PORTC,
PORTE and PORTG.
EXAMPLE 10-1:
INITIALIZING PORTA
When the open-drain option is required, the output pin
must also be tied through an external pull-up resistor
provided by the user to a higher voltage level, up to 5V
(Figure 10-2). When a digital logic high signal is output,
it is pulled up to the higher voltage level.
CLRF
PORTA
LATA
07h
; Initialize PORTA by
; clearing output latches
; Alternate method to
; clear output data latches
; Configure A/D
CLRF
MOVLW
MOVWF
MOVLW
ADCON1 ; for digital inputs
0BFh
FIGURE 10-2:
USING THE OPEN-DRAIN
OUTPUT (USARTs
; Value used to initialize
; data direction
; Set RA<7, 5:0> as inputs,
; RA<6> as output
SHOWN AS EXAMPLES
MOVWF
TRISA
+5V
3.3V
PIC18F85J11
3.3V
TXX
5V
VDD
(at logic ‘1’)
DS39774C-page 124
Preliminary
© 2007 Microchip Technology Inc.
PIC18F85J11 FAMILY
TABLE 10-3:
Pin Name
PORTA FUNCTIONS
TRIS
I/O
Type
Function
I/O
Description
Setting
RA0/AN0
RA0
0
1
1
O
I
DIG
TTL
ANA
LATA<0> data output; not affected by analog input.
PORTA<0> data input; disabled when analog input enabled.
AN0
RA1
I
A/D input channel 0. Default input configuration on POR; does not
affect digital output.
RA1/AN1
0
1
1
O
I
DIG
TTL
ANA
LATA<1> data output; not affected by analog input.
PORTA<1> data input; disabled when analog input enabled.
AN1
RA2
I
A/D input channel 1. Default input configuration on POR; does not
affect digital output.
RA2/AN2/VREF-
0
1
1
1
0
1
1
1
0
1
x
0
1
1
0
1
x
x
0
1
x
x
O
I
DIG
TTL
ANA
ANA
DIG
TTL
ANA
ANA
DIG
ST
LATA<2> data output; not affected by analog input.
PORTA<2> data input. Disabled when analog functions enabled.
A/D input channel 2. Default input configuration on POR.
A/D and comparator low reference voltage input.
AN2
VREF-
RA3
I
I
RA3/AN3/
VREF+
O
I
LATA<3> data output; not affected by analog input.
PORTA<3> data input; disabled when analog input enabled.
A/D input channel 3. Default input configuration on POR.
A/D and comparator high reference voltage input.
AN3
VREF+
RA4
I
I
RA4/T0CKI
RA5/AN4
O
I
LATA<4> data output.
PORTA<4> data input; default configuration on POR.
Timer0 clock input.
T0CKI
RA5
I
ST
O
I
DIG
TTL
ANA
DIG
TTL
ANA
DIG
DIG
TTL
ANA
ANA
LATA<5> data output; not affected by analog input.
PORTA<5> data input; disabled when analog input enabled.
A/D input channel 4. Default configuration on POR.
LATA<6> data output; disabled when FOSC2 Configuration bit is set.
PORTA<6> data input; disabled when FOSC2 Configuration bit is set.
Main oscillator feedback output connection (HS and HSPLL modes).
System cycle clock output, FOSC/4 (EC and ECPLL modes).
LATA<7> data output; disabled when FOSC2 Configuration bit is set.
PORTA<7> data input; disabled when FOSC2 Configuration bit is set.
Main oscillator input connection (HS and HSPLL modes).
Main external clock source input (EC and ECPLL modes).
AN4
RA6
I
RA6/OSC2/
CLKO
O
I
OSC2
CLKO
RA7
O
O
O
I
RA7/OSC1/
CLKI
OSC1
CLKI
I
I
Legend:
O = Output, I = Input, ANA = Analog Signal, DIG = Digital Output, ST = Schmitt Buffer Input,
TTL = TTL Buffer Input, x= Don’t care (TRIS bit does not affect port direction or is overridden for this option).
TABLE 10-4: SUMMARY OF REGISTERS ASSOCIATED WITH PORTA
Reset
Values
on page
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PORTA
LATA
RA7(1)
LATA7(1)
TRISA7(1) TRISA6(1) TRISA5
RA6(1)
LATA6(1)
RA5
RA4
RA3
RA2
RA1
RA0
54
54
54
53
LATA5
LATA4
TRISA4
VCFG0
LATA3
TRISA3
PCFG3
LATA2
TRISA2
PCFG2
LATA1
TRISA1
PCFG1
LATA0
TRISA0
PCFG0
TRISA
ADCON1
—
—
VCFG1
Legend: — = Unimplemented, read as ‘0’. Shaded cells are not used by PORTA.
x= Don’t care.
Note 1: These bits are enabled depending on the oscillator mode selected. When not enabled as PORTA pins,
they are disabled and read as ‘x’.
© 2007 Microchip Technology Inc.
Preliminary
DS39774C-page 125
PIC18F85J11 FAMILY
A mismatch condition will continue to set flag bit, RBIF.
Reading PORTB will end the mismatch condition and
allow flag bit, RBIF, to be cleared.
10.3 PORTB, TRISB and
LATB Registers
PORTB is an 8-bit wide, bidirectional port. The corre-
sponding Data Direction and Output Latch registers are
TRISB and LATB. All pins on PORTB are digital only
and tolerate voltages up to 5.5V.
The interrupt-on-change feature is recommended for
wake-up on key depression operation and operations
where PORTB is only used for the interrupt-on-change
feature. Polling of PORTB is not recommended while
using the interrupt-on-change feature.
Each of the PORTB pins has a weak internal pull-up. A
single control bit can turn on all the pull-ups. This is
performed by clearing bit RBPU (INTCON2<7>). The
weak pull-up is automatically turned off when the port
pin is configured as an output. The pull-ups are
disabled on a Power-on Reset.
EXAMPLE 10-2:
INITIALIZING PORTB
CLRF
PORTB
; Initialize PORTB by
; clearing output
; data latches
Four of the PORTB pins (RB7:RB4) have an
interrupt-on-change feature. Only pins configured as
inputs can cause this interrupt to occur (i.e., any
RB7:RB4 pin configured as an output is excluded from
the interrupt-on-change comparison). The input pins (of
RB7:RB4) are compared with the old value latched on
the last read of PORTB. The “mismatch” outputs of
RB7:RB4 are ORed together to generate the RB Port
Change Interrupt with Flag bit, RBIF (INTCON<0>).
CLRF
LATB
; Alternate method
; to clear output
; data latches
; Value used to
; initialize data
; direction
; Set RB<3:0> as inputs
; RB<5:4> as outputs
; RB<7:6> as inputs
MOVLW
MOVWF
0CFh
TRISB
This interrupt can wake the device from power-managed
modes. The user, in the Interrupt Service Routine, can
clear the interrupt in the following manner:
a) Any read or write of PORTB (except with the
MOVFF (ANY), PORTB instruction). This will
end the mismatch condition.
b) Clear flag bit, RBIF.
DS39774C-page 126
Preliminary
© 2007 Microchip Technology Inc.
PIC18F85J11 FAMILY
TABLE 10-5: PORTB FUNCTIONS
TRIS
Setting
I/O
Type
Pin Name
RB0/INT0
Function
I/O
Description
RB0
0
1
1
0
1
1
0
1
1
0
1
1
0
1
0
1
O
I
DIG LATB<0> data output.
TTL PORTB<0> data input; weak pull-up when RBPU bit is cleared.
INT0
RB1
I
ST
External interrupt 0 input.
RB1/INT1
RB2/INT2
O
I
DIG LATB<1> data output.
TTL PORTB<1> data input; weak pull-up when RBPU bit is cleared.
INT1
RB2
I
ST
External interrupt 1 input.
O
I
DIG LATB<2> data output.
TTL PORTB<2> data input; weak pull-up when RBPU bit is cleared.
INT2
RB3
I
ST
External interrupt 2 input.
RB3/INT3/
CCP2
O
I
DIG LATB<3> data output.
TTL PORTB<3> data input; weak pull-up when RBPU bit is cleared.
INT3
I
ST
DIG CCP2 compare output and CCP2 PWM output; takes priority over port data.
ST CCP2 capture input.
External interrupt 3 input.
(1)
CCP2
O
I
RB4/KBI0
RB4
O
I
DIG LATB<4> data output.
TTL PORTB<4> data input; weak pull-up when RBPU bit is cleared.
TTL Interrupt-on-pin change.
KBI0
RB5
I
RB5/KBI1
0
1
O
I
DIG LATB<5> data output.
TTL PORTB<5> data input; weak pull-up when RBPU bit is cleared.
TTL Interrupt-on-pin change.
KBI1
RB6
I
RB6/KBI2/PGC
0
1
1
x
0
1
1
x
x
O
I
DIG LATB<6> data output.
TTL PORTB<6> data input; weak pull-up when RBPU bit is cleared.
TTL Interrupt-on-pin change.
KBI2
PGC
RB7
I
(2)
I
ST
Serial execution (ICSP™) clock input for ICSP and ICD operation.
RB7/KBI3/PGD
O
I
DIG LATB<7> data output.
TTL PORTB<7> data input; weak pull-up when RBPU bit is cleared.
TTL Interrupt-on-pin change.
KBI3
PGD
I
(2)
O
I
DIG Serial execution data output for ICSP and ICD operation.
(2)
ST
Serial execution data input for ICSP and ICD operation.
Legend:
O = Output, I = Input, DIG = Digital Output, ST = Schmitt Buffer Input, TTL = TTL Buffer Input, x= Don’t care (TRIS bit
does not affect port direction or is overridden for this option).
Note 1: Alternate assignment for CCP2 when the CCP2MX Configuration bit is cleared (Extended Microcontroller mode, 80-pin
devices only). Default assignment is RC1.
2: All other pin functions are disabled when ICSP™ or ICD is enabled.
TABLE 10-6: SUMMARY OF REGISTERS ASSOCIATED WITH PORTB
Reset
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Values
on page
PORTB
LATB
RB7
RB6
RB5
RB4
RB3
LATB3
TRISB3
RBIE
RB2
RB1
RB0
LATB0
TRISB0
RBIF
54
54
54
51
51
51
LATB7
TRISB7
LATB6
TRISB6
LATB5
TRISB5
LATB4
TRISB4
INT0IE
LATB2
TRISB2
TMR0IF
LATB1
TRISB1
INT0IF
INT3IP
INT2IF
TRISB
INTCON
INTCON2
INTCON3
GIE/GIEH PEIE/GIEL TMR0IE
RBPU
INTEDG0 INTEDG1 INTEDG2 INTEDG3 TMR0IP
INT1IP INT3IE INT2IE INT1IE INT3IF
RBIP
INT2IP
INT1IF
Legend: Shaded cells are not used by PORTB.
© 2007 Microchip Technology Inc.
Preliminary
DS39774C-page 127
PIC18F85J11 FAMILY
When enabling peripheral functions, care should be
taken in defining TRIS bits for each PORTC pin. Some
peripherals override the TRIS bit to make a pin an output,
while other peripherals override the TRIS bit to make a
pin an input. The user should refer to the corresponding
peripheral section for the correct TRIS bit settings.
10.4 PORTC, TRISC and
LATC Registers
PORTC is an 8-bit wide, bidirectional port. The corre-
sponding Data Direction and Output Latch registers are
TRISC and LATC. Only PORTC pins, RC2 through
RC7, are digital only pins and can tolerate input
voltages up to 5.5V.
Note:
These pins are configured as digital inputs
on any device Reset.
PORTC is multiplexed with CCP, MSSP and EUSART
peripheral functions (Table 10-7). The pins have
Schmitt Trigger input buffers. The pins for CCP, SPI
and EUSART are also configurable for open-drain out-
put whenever these functions are active. Open-drain
configuration is selected by setting the SPIOD,
CCPxOD and U1OD control bits (TRISG<7:5> and
LATG<6>, respectively).
The contents of the TRISC register are affected by
peripheral overrides. Reading TRISC always returns
the current contents, even though a peripheral device
may be overriding one or more of the pins.
EXAMPLE 10-3:
INITIALIZING PORTC
CLRF
PORTC
; Initialize PORTC by
; clearing output
; data latches
RC1 is normally configured as the default peripheral
pin for the CCP2 module. Assignment of CCP2 is con-
trolled by Configuration bit, CCP2MX (default state,
CCP2MX = 1).
CLRF
LATC
; Alternate method
; to clear output
; data latches
MOVLW
MOVWF
0CFh
; Value used to
; initialize data
; direction
; Set RC<3:0> as inputs
; RC<5:4> as outputs
; RC<7:6> as inputs
TRISC
DS39774C-page 128
Preliminary
© 2007 Microchip Technology Inc.
PIC18F85J11 FAMILY
TABLE 10-7: PORTC FUNCTIONS
TRIS
Setting
I/O
Type
Pin Name
Function
I/O
Description
RC0/T1OSO/
T13CKI
RC0
0
1
x
O
I
DIG
ST
LATC<0> data output.
PORTC<0> data input.
T1OSO
O
ANA Timer1 oscillator output; enabled when Timer1 oscillator enabled. Disables
digital I/O.
T13CKI
RC1
1
0
1
x
I
O
I
ST
DIG
ST
Timer1/Timer3 counter input.
LATC<1> data output.
RC1/T1OSI/
CCP2
PORTC<1> data input.
T1OSI
I
ANA Timer1 oscillator input; enabled when Timer1 oscillator enabled. Disables
digital I/O.
(1)
CCP2
0
1
0
1
0
1
0
1
0
1
0
1
0
1
1
1
1
0
1
0
0
1
1
1
O
I
DIG
ST
CCP2 compare output and CCP2 PWM output; takes priority over port data.
CCP2 capture input.
RC2/CCP1
RC2
CCP1
RC3
SCK
SCL
O
I
DIG
ST
LATC<2> data output.
PORTC<2> data input.
O
I
DIG
ST
CCP1 compare output and CCP1 PWM output; takes priority over port data.
CCP1 capture input.
RC3/SCK/SCL
O
I
DIG
ST
LATC<3> data output.
PORTC<3> data input.
O
I
DIG
ST
SPI clock output (MSSP module); takes priority over port data.
SPI clock input (MSSP module).
2
O
I
DIG
ST
I C™ clock output (MSSP module); takes priority over port data.
2
I C clock input (MSSP module); input type depends on module setting.
RC4/SDI/SDA
RC4
O
I
DIG
ST
LATC<4> data output.
PORTC<4> data input.
SDI
I
ST
SPI data input (MSSP module).
2
SDA
O
I
DIG
ST
I C data output (MSSP module); takes priority over port data.
2
I C data input (MSSP module); input type depends on module setting.
RC5/SDO
RC5
O
I
DIG
ST
LATC<5> data output.
PORTC<5> data input.
SDO
RC6
O
O
I
DIG
DIG
ST
SPI data output (MSSP module); takes priority over port data.
LATC<6> data output.
RC6/TX1/CK1
PORTC<6> data input.
TX1
CK1
O
O
DIG
DIG
Synchronous serial data output (EUSART module); takes priority over port data.
Synchronous serial data input (EUSART module). User must configure as
an input.
1
0
1
1
1
I
O
I
ST
DIG
ST
Synchronous serial clock input (EUSART module).
LATC<7> data output.
RC7/RX1/DT1
RC7
PORTC<7> data input.
RX1
DT1
I
ST
Asynchronous serial receive data input (EUSART module).
O
DIG
Synchronous serial data output (EUSART module); takes priority over
port data.
1
I
ST
Synchronous serial data input (EUSART module). User must configure as
an input.
Legend:
O = Output, I = Input, ANA = Analog Signal, DIG = Digital Output, ST = Schmitt Buffer Input, x= Don’t care (TRIS bit
does not affect port direction or is overridden for this option).
Note 1: Default assignment for CCP2 when CCP2MX Configuration bit is set.
© 2007 Microchip Technology Inc.
Preliminary
DS39774C-page 129
PIC18F85J11 FAMILY
TABLE 10-8: SUMMARY OF REGISTERS ASSOCIATED WITH PORTC
Reset
Values
on page
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PORTC
RC7
RC6
RC5
RC4
RC3
RC2
RC1
RC0
54
54
54
54
54
LATC
LATC7
LATBC6
LATC5
LATCB4
LATC3
LATC2
LATC1
LATC0
TRISC
LATG
TRISG
TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0
U2OD U1OD LATG4 LATG3 LATG2 LATG1 LATG0
SPIOD CCP2OD CCP1OD TRISG4 TRISG3 TRISG2 TRISG1 TRISG0
—
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PORTC.
DS39774C-page 130
Preliminary
© 2007 Microchip Technology Inc.
PIC18F85J11 FAMILY
PORTD can also be configured to function as an 8-bit
wide, parallel microprocessor port by setting the
PSPMODE control bit (PSPCON<4>). In this mode,
parallel port data takes priority over other digital I/O (but
not the external memory interface). When the parallel
port is active, the input buffers are TTL. For more
information, refer to Section 10.11 “Parallel Slave
Port”.
10.5 PORTD, TRISD and
LATD Registers
PORTD is an 8-bit wide, bidirectional port. The corre-
sponding Data Direction and Output Latch registers are
TRISD and LATD. All pins on PORTD are digital only
and tolerate voltages up to 5.5V.
All pins on PORTD are implemented with Schmitt
Trigger input buffers. Each pin is individually
configurable as an input or output.
EXAMPLE 10-4:
INITIALIZING PORTD
CLRF
PORTD
; Initialize PORTD by
; clearing output
; data latches
Note:
These pins are configured as digital inputs
on any device Reset.
CLRF
LATD
; Alternate method
; to clear output
; data latches
; Value used to
; initialize data
; direction
; Set RD<3:0> as inputs
; RD<5:4> as outputs
; RD<7:6> as inputs
Each of the PORTD pins has a weak internal pull-up. A
single control bit can turn off all the pull-ups. This is
performed by setting bit RDPU (PORTG<7>). The
weak pull-up is automatically turned off when the port
pin is configured as an output. The pull-ups are
disabled on all device Resets.
MOVLW
MOVWF
0CFh
TRISD
On 80-pin devices, PORTD is multiplexed with the
system bus as part of the external memory interface.
I/O port and other functions are only available when the
interface is disabled, by setting the EBDIS bit
(MEMCON<7>). When the interface is enabled,
PORTD is the low-order byte of the multiplexed
address/data bus (AD7:AD0). The TRISD bits are also
overridden.
© 2007 Microchip Technology Inc.
Preliminary
DS39774C-page 131
PIC18F85J11 FAMILY
TABLE 10-9: PORTD FUNCTIONS
TRIS
Setting
I/O
Type
Pin Name
Function
I/O
Description
RD0/AD0/PSP0
RD0
0
1
x
x
O
I
DIG
ST
LATD<0> data output.
PORTD<0> data input.
(2)
(1)
AD0
O
I
DIG
TTL
DIG
TTL
DIG
ST
External memory interface, address/data bit 0 output.
(1)
External memory interface, data bit 0 input.
PSP0
RD1
O
I
PSP read output data (LATD<0>); takes priority over port data.
PSP write data input.
RD1/AD1/PSP1
RD2/AD2/PSP2
RD3/AD3/PSP3
RD4/AD4/PSP4
RD5/AD5/PSP5
RD6/AD6/PSP6
0
1
x
x
x
x
0
1
x
x
x
x
0
1
x
x
x
x
0
1
x
x
x
x
0
1
x
x
x
x
0
1
x
x
x
x
O
I
LATD<1> data output.
PORTD<1> data input.
(2)
(1)
AD1
O
I
DIG
TTL
DIG
TTL
DIG
ST
External memory interface, address/data bit 1 output.
(1)
External memory interface, data bit 1 input.
PSP1
RD2
O
I
PSP read output data (LATD<1>); takes priority over port data.
PSP write data input.
O
I
LATD<2> data output.
PORTD<2> data input.
(2)
(1)
AD2
O
I
DIG
TTL
DIG
TTL
DIG
ST
External memory interface, address/data bit 2 output.
(1)
External memory interface, data bit 2 input.
PSP2
RD3
O
I
PSP read output data (LATD<2>); takes priority over port data.
PSP write data input.
O
I
LATD<3> data output.
PORTD<3> data input.
(2)
(1)
AD3
O
I
DIG
TTL
DIG
TTL
DIG
ST
External memory interface, address/data bit 3 output.
(1)
External memory interface, data bit 3 input.
PSP3
RD4
O
I
PSP read output data (LATD<3>); takes priority over port data.
PSP write data input.
O
I
LATD<4> data output.
PORTD<4> data input.
(2)
(1)
AD4
O
I
DIG
TTL
DIG
TTL
DIG
ST
External memory interface, address/data bit 4 output.
(1)
External memory interface, data bit 4 input.
PSP4
RD5
O
I
PSP read output data (LATD<4>); takes priority over port data.
PSP write data input.
O
I
LATD<5> data output.
PORTD<5> data input.
(2)
(1)
AD5
O
I
DIG
TTL
DIG
TTL
DIG
ST
External memory interface, address/data bit 5 output.
(1)
External memory interface, data bit 5 input.
PSP5
RD6
O
I
PSP read output data (LATD<5>); takes priority over port data.
PSP write data input.
O
I
LATD<6> data output.
PORTD<6> data input.
(2)
(1)
AD6
O
I
DIG-3 External memory interface, address/data bit 6 output.
(1)
TTL
DIG
TTL
External memory interface, data bit 6 input.
PSP read output data (LATD<6>); takes priority over port data.
PSP write data input.
PSP6
O
I
Legend:
O = Output, I = Input, DIG = Digital Output, ST = Schmitt Buffer Input, TTL = TTL Buffer Input, x= Don’t care (TRIS bit
does not affect port direction or is overridden for this option).
Note 1: External memory interface I/O takes priority over all other digital and PSP I/O.
2: Available on 80-pin devices only.
DS39774C-page 132
Preliminary
© 2007 Microchip Technology Inc.
PIC18F85J11 FAMILY
TABLE 10-9: PORTD FUNCTIONS (CONTINUED)
TRIS
Setting
I/O
Type
Pin Name
Function
I/O
Description
RD7/AD7/PSP7
RD7
0
1
x
x
x
x
O
I
DIG
ST
LATD<7> data output.
PORTD<7> data input.
(2)
(1)
AD7
O
I
DIG
TTL
DIG
TTL
External memory interface, address/data bit 7 output.
(1)
External memory interface, data bit 7 input.
PSP7
O
I
PSP read output data (LATD<7>); takes priority over port data.
PSP write data input.
Legend:
O = Output, I = Input, DIG = Digital Output, ST = Schmitt Buffer Input, TTL = TTL Buffer Input, x= Don’t care (TRIS bit
does not affect port direction or is overridden for this option).
Note 1: External memory interface I/O takes priority over all other digital and PSP I/O.
2: Available on 80-pin devices only.
TABLE 10-10: SUMMARY OF REGISTERS ASSOCIATED WITH PORTD
Reset
Values
on page
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PORTD
LATD
RD7
LATD7
TRISD7
RDPU
RD6
LATD6
TRISD6
REPU
RD5
RD4
LATD4
TRISD4
RG4
RD3
LATD3
TRISD3
RG3
RD2
LATD2
TRISD2
RG2
RD1
LATD1
TRISD1
RG1
RD0
LATD0
TRISD0
RG0
54
54
54
54
LATD5
TRISD5
RJPU(1)
TRISD
PORTG
Legend: Shaded cells are not used by PORTD.
Note 1: Unimplemented on 64-pin devices, read as ‘0’.
© 2007 Microchip Technology Inc.
Preliminary
DS39774C-page 133
PIC18F85J11 FAMILY
When the Parallel Slave Port is active on PORTD, three
of the PORTE pins (RE0, RE1 and RE2) are configured
as digital control inputs for the port. The control
functions are summarized in Table 10-11. The reconfig-
uration occurs automatically when the PSPMODE
control bit (PSPCON<4>) is set. Users must still make
certain the corresponding TRISE bits are set to
configure these pins as digital inputs.
10.6 PORTE, TRISE and
LATE Registers
PORTE is an 8-bit wide, bidirectional port. The corre-
sponding Data Direction and Output Latch registers are
TRISE and LATE. All pins on PORTE are digital only
and tolerate voltages up to 5.5V.
All pins on PORTE are implemented with Schmitt Trig-
ger input buffers. Each pin is individually configurable
as an input or output. The RE7 pin is also configurable
for open-drain output when CCP2 is active on this pin.
Open-drain configuration is selected by setting the
CCP2OD control bit (TRISG<6>)
RE7 can also be configured as the alternate peripheral
pin for the CCP2 module. This is done by clearing the
CCP2MX Configuration bit.
EXAMPLE 10-5:
INITIALIZING PORTE
Note:
These pins are configured as digital inputs
on any device Reset.
CLRF
PORTE
LATE
03h
; Initialize PORTE by
; clearing output
; data latches
; Alternate method
; to clear output
; data latches
; Value used to
; initialize data
; direction
Each of the PORTE pins has a weak internal pull-up. A
single control bit can turn off all the pull-ups. This is
performed by setting bit REPU (PORTG<6>). The
weak pull-up is automatically turned off when the port
pin is configured as an output. The pull-ups are
disabled on any device Reset.
CLRF
MOVLW
MOVWF
TRISE
; Set RE<1:0> as inputs
; RE<7:2> as outputs
On 80-pin devices, PORTE is multiplexed with the
system bus as part of the external memory interface.
I/O port and other functions are only available when the
interface is disabled by setting the EBDIS bit
(MEMCON<7>). When the interface is enabled,
PORTE is the high-order byte of the multiplexed
address/data bus (AD15:AD8). The TRISE bits are also
overridden.
DS39774C-page 134
Preliminary
© 2007 Microchip Technology Inc.
PIC18F85J11 FAMILY
TABLE 10-11: PORTE FUNCTIONS
TRIS
Setting
I/O
Type
Pin Name
Function
I/O
Description
RE0/RD/AD8
RE0
0
1
1
x
x
0
1
1
x
x
0
1
x
x
1
0
1
x
x
0
1
x
x
0
1
x
x
0
1
x
x
0
1
x
x
0
O
I
DIG
ST
LATE<0> data output.
PORTE<0> data input.
RD
I
TTL
DIG
TTL
DIG
ST
Parallel Slave Port read enable control input.
External memory interface, address/data bit 8 output.
(1)
(2)
(2)
AD8
O
I
(2)
External memory interface, data bit 8 input.
RE1/WR/AD9
RE2/AD10/CS
RE1
O
I
LATE<1> data output.
PORTE<1> data input.
WR
I
TTL
DIG
TTL
DIG
ST
Parallel Slave Port write enable control input.
External memory interface, address/data bit 9 output.
(1)
AD9
O
I
(2)
External memory interface, data bit 9 input.
RE2
O
I
LATE<2> data output.
PORTE<2> data input.
(1)
(2)
AD10
O
I
DIG
TTL
TTL
DIG
ST
External memory interface, address/data bit 10 output.
(2)
External memory interface, data bit 10 input.
CS
I
Parallel Slave Port chip select control input.
LATE<3> data output.
RE3/AD11
RE4/AD12
RE5/AD13
RE6/AD14
RE3
O
I
PORTE<3> data input.
(1)
(2)
(2)
AD11
O
I
DIG
TTL
DIG
ST
External memory interface, address/data bit 11 output.
(2)
External memory interface, data bit 11 input.
RE4
O
I
LATE<4> data output.
PORTE<4> data input.
(1)
AD12
O
I
DIG
TTL
DIG
ST
External memory interface, address/data bit 12 output.
(2)
External memory interface, data bit 12 input.
RE5
O
I
LATE<5> data output.
PORTE<5> data input.
(1)
(2)
AD13
O
I
DIG
TTL
DIG
ST
External memory interface, address/data bit 13 output.
(2)
External memory interface, data bit 13 input.
RE6
O
I
LATE<6> data output.
PORTE<6> data input.
(1)
(2)
(2)
AD14
O
I
DIG
TTL
DIG
ST
External memory interface, address/data bit 14 output.
(2)
External memory interface, data bit 14 input.
RE7/AD15/
CCP2
RE7
O
I
LATE<7> data output.
PORTE<7> data input.
(1)
AD15
O
I
DIG
TTL
DIG
External memory interface, address/data bit 15 output.
(2)
External memory interface, data bit 15 input.
(3)
CCP2
O
CCP2 compare output and CCP2 PWM output; takes priority over
port data.
1
I
ST
CCP2 capture input.
Legend:
O = Output, I = Input, DIG = Digital Output, ST = Schmitt Buffer Input, TTL = TTL Buffer Input, x= Don’t care (TRIS bit
does not affect port direction or is overridden for this option).
Note 1: Available on 80-pin devices only.
2: External memory interface I/O takes priority over all other digital and PSP I/O.
3: Alternate assignment for CCP2 when CCP2MX Configuration bit is cleared (all devices in Microcontroller mode).
© 2007 Microchip Technology Inc.
Preliminary
DS39774C-page 135
PIC18F85J11 FAMILY
TABLE 10-12: SUMMARY OF REGISTERS ASSOCIATED WITH PORTE
Reset
Values
on page
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PORTE
LATE
RE7
RE6
RE5
RE4
LATE4
TRISE4
RG4
RE3
LATE3
TRISE3
RG3
RE2
LATE2
TRISE2
RG2
RE1
LATE1
TRISE1
RG1
RE0
LATE0
TRISE0
RG0
54
54
54
54
54
LATE7
TRISE7
RDPU
SPIOD
LATE6
TRISE6
REPU
LATE5
TRISE5
RJPU(1)
TRISE
PORTG
TRISG
CCP2OD CCP1OD TRISG4
TRISG3
TRISG2
TRISG1
TRISG0
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PORTE.
Note 1: Unimplemented on 64-pin devices, read as ‘0’.
DS39774C-page 136
Preliminary
© 2007 Microchip Technology Inc.
PIC18F85J11 FAMILY
EXAMPLE 10-6:
INITIALIZING PORTF
10.7 PORTF, LATF and TRISF Registers
CLRF
PORTF
; Initialize PORTF by
; clearing output
; data latches
; Alternate method
; to clear output
; data latches
PORTF is a 7-bit wide, bidirectional port. The corre-
sponding Data Direction and Output Latch registers are
TRISF and LATF. All pins on PORTF are implemented
with Schmitt Trigger input buffers. Each pin is individually
configurable as an input or output.
CLRF
LATF
MOVLW
MOVWF
MOVLW
MOVWF
MOVLW
07h
CMCON
0Fh;
;
PORTF is multiplexed with analog peripheral functions.
Pins RF1 through RF6 may be used as comparator
inputs or outputs by setting the appropriate bits in the
CMCON register. To use RF6:RF3 as digital inputs, it is
also necessary to turn off the comparators.
; Turn off comparators
ADCON1 ; Set PORTF as digital I/O
0CEh
; Value used to
; initialize data
; direction
; Set RF3:RF1 as inputs
; RF5:RF4 as outputs
; RF7:RF6 as inputs
Note 1: On device Resets, pins RF6:RF1 are
configured as analog inputs and are read
as ‘0’.
MOVWF
TRISF
2: To configure PORTF as digital I/O, turn off
comparators and set ADCON1 value.
© 2007 Microchip Technology Inc.
Preliminary
DS39774C-page 137
PIC18F85J11 FAMILY
TABLE 10-13: PORTF FUNCTIONS
TRIS
Setting
I/O
Type
Pin Name
Function
I/O
Description
RF1/AN6/
C2OUT
RF1
0
1
1
0
0
1
1
0
0
1
1
O
I
DIG
ST
LATF<1> data output; not affected by analog input.
PORTF<1> data input; disabled when analog input enabled.
A/D input channel 6. Default configuration on POR.
Comparator 2 output; takes priority over port data.
LATF<2> data output; not affected by analog input.
PORTF<2> data input; disabled when analog input enabled.
A/D input channel 7. Default configuration on POR.
Comparator 1 output; takes priority over port data.
LATF<3> data output; not affected by analog input.
PORTF<3> data input; disabled when analog input enabled.
AN6
C2OUT
RF2
I
ANA
DIG
DIG
ST
O
O
I
RF2/AN7/
C1OUT
AN7
C1OUT
RF3
I
ANA
TTL
DIG
ST
O
O
I
RF3/AN8
RF4/AN9
AN8
RF4
I
ANA
A/D input channel 8 and Comparator C2+ input. Default input
configuration on POR; not affected by analog output.
0
1
1
O
I
DIG
ST
LATF<4> data output; not affected by analog input.
PORTF<4> data input; disabled when analog input enabled.
AN9
RF5
I
ANA
A/D input channel 9 and Comparator C2- input. Default input
configuration on POR; does not affect digital output.
RF5/AN10/
CVREF
0
1
1
x
O
I
DIG
ST
LATF<5> data output; not affected by analog input. Disabled when
CVREF output enabled.
PORTF<5> data input; disabled when analog input enabled. Disabled
when CVREF output enabled.
AN10
CVREF
RF6
I
ANA
ANA
A/D input channel 10 and Comparator C1+ input. Default input
configuration on POR.
O
Comparator voltage reference output. Enabling this feature disables
digital I/O.
RF6/AN11
0
1
1
O
I
DIG
ST
LATF<6> data output; not affected by analog input.
PORTF<6> data input; disabled when analog input enabled.
AN11
RF7
I
ANA
A/D input channel 11 and Comparator C1- input. Default input
configuration on POR; does not affect digital output.
RF7/AN5/SS
0
1
1
O
I
DIG
ST
LATF<7> data output.
PORTF<7> data input.
AN5
SS
I
ANA
TTL
A/D input channel 5. Default configuration on POR.
Slave select input for MSSP module.
1
I
Legend:
O = Output, I = Input, ANA = Analog Signal, DIG = Digital Output, ST = Schmitt Buffer Input, TTL = TTL Buffer Input,
x= Don’t care (TRIS bit does not affect port direction or is overridden for this option).
TABLE 10-14: SUMMARY OF REGISTERS ASSOCIATED WITH PORTF
Reset
Values
on page
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PORTF
LATF
RF7
LATF7
TRISF7
—
RF6
LATF6
TRISF6
—
RF5
RF4
RF3
LATF3
TRISF3
PCFG3
CIS
RF2
LATF2
TRISF2
PCFG2
CM2
RF1
LATF1
TRISF1
PCFG1
CM1
—
—
54
54
54
53
53
53
LATF5
TRISF5
VCFG1
C2INV
CVRR
LATF4
TRISF4
VCFG0
C1INV
CVRSS
TRISF
—
ADCON1
CMCON
CVRCON
PCFG0
CM0
CVR0
C2OUT
CVREN
C1OUT
CVROE
CVR3
CVR2
CVR1
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PORTF.
DS39774C-page 138
Preliminary
© 2007 Microchip Technology Inc.
PIC18F85J11 FAMILY
Although the port itself is only five bits wide, the
PORTG<7:5> bits are still implemented to control the
weak pull-ups on the I/O ports associated with PORTD,
PORTE and PORTJ. Setting these bits enables the
respective port pull-ups.
10.8 PORTG, TRISG and
LATG Registers
PORTG is a 5-bit wide, bidirectional port. The corre-
sponding Data Direction and Output Latch registers are
TRISG and LATG. All pins on PORTG are digital only
and tolerate voltages up to 5.5V.
Most of the corresponding TRISG and LATG bits are
implemented as open-drain control bits for CCP1,
CCP2 and SPI (TRISG<7:5>), and the USARTs
(LATG<7:6>). Setting these bits configures the output
pin for the corresponding peripheral for open-drain
operation. LATG<5> is not implemented.
When operating as I/O, all PORTG pins have Schmitt
Trigger input buffers. Pins RG1 and RG2 are multi-
plexed with the AUSART module. The RG1 pin is also
configurable for open-drain output when the AUSART
is active. Open-drain configuration is selected by
setting the U2OD control bit (LATG<7>).
EXAMPLE 10-7:
INITIALIZING PORTG
When enabling peripheral functions, care should be
taken in defining TRIS bits for each PORTG pin. Some
peripherals override the TRIS bit to make a pin an
output, while other peripherals override the TRIS bit to
make a pin an input. The user should refer to the
corresponding peripheral section for the correct TRIS
bit settings. The pin override value is not loaded into
the TRIS register. This allows read-modify-write of the
TRIS register without concern due to peripheral
overrides.
CLRF
PORTG
LATG
04h
; Initialize PORTG by
; clearing output
; data latches
; Alternate method
; to clear output
; data latches
; Value used to
; initialize data
; direction
CLRF
MOVLW
MOVWF
TRISG
; Set RG1:RG0 as outputs
; RG2 as input
; RG4:RG3 as inputs
© 2007 Microchip Technology Inc.
Preliminary
DS39774C-page 139
PIC18F85J11 FAMILY
TABLE 10-15: PORTG FUNCTIONS
TRIS
Setting
I/O
Type
Pin Name
RG0
Function
I/O
Description
RG0
0
1
0
1
1
O
I
DIG
ST
LATG<0> data output.
PORTG<0> data input.
LATG<1> data output.
PORTG<1> data input.
RG1/TX2/CK2
R21
O
I
DIG
ST
TX2
CK2
O
DIG
Synchronous serial data output (AUSART2 module); takes priority over
port data.
1
O
DIG
Synchronous serial data input (AUSART2 module). User must configure
as an input.
1
0
1
1
1
I
O
I
ST
DIG
ST
Synchronous serial clock input (AUSART2 module).
LATG<2> data output.
RG2/RX2/DT2
RG2
PORTG<2> data input.
RX2
DT2
I
ST
Asynchronous serial receive data input (AUSART2 module).
O
DIG
Synchronous serial data output (AUSART2 module); takes priority over
port data.
1
I
ST
Synchronous serial data input (AUSART2 module). User must configure
as an input.
RG3
RG4
RG3
RG4
0
1
0
1
O
I
DIG
ST
LATG<3> data output.
PORTG<3> data input.
LATG<4> data output.
PORTG<4> data input.
O
I
DIG
ST
Legend:
O = Output, I = Input, DIG = Digital Output, ST = Schmitt Buffer Input, x= Don’t care (TRIS bit does not affect port
direction or is overridden for this option).
TABLE 10-16: SUMMARY OF REGISTERS ASSOCIATED WITH PORTG
Reset
Values on
page
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PORTG
RDPU
U2OD
REPU
U1OD
RJPU(1)
—
RG4
RG3
RG2
RG1
RG0
54
54
54
LATG
LATG4
LATG3
LATG2
LATG1
LATG0
TRISG
SPIOD CCP2OD CCP1OD TRISG4 TRISG3 TRISG2 TRISG1 TRISG0
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PORTG.
Note 1: Unimplemented on 64-pin devices, read as ‘0’.
DS39774C-page 140
Preliminary
© 2007 Microchip Technology Inc.
PIC18F85J11 FAMILY
EXAMPLE 10-8:
INITIALIZING PORTH
10.9 PORTH, LATH and TRISH Registers
CLRF
PORTH
; Initialize PORTH by
; clearing output
; data latches
Note: PORTH is available only on 80-pin
devices.
CLRF
LATH
; Alternate method
; to clear output
; data latches
; Configure PORTH as
; digital I/O
; Value used to
; initialize data
; direction
PORTH is an 8-bit wide, bidirectional I/O port. The corre-
sponding Data Direction and Output Latch registers are
TRISH and LATH. All pins are digital only and tolerate
voltages up to 5.5V.
MOVLW
MOVWF
MOVLW
0Fh
ADCON1
0CFh
All pins on PORTH are implemented with Schmitt
Trigger input buffers. Each pin is individually
configurable as an input or output.
MOVWF
TRISH
; Set RH3:RH0 as inputs
; RH5:RH4 as outputs
; RH7:RH6 as inputs
When the external memory interface is enabled, four of
the PORTH pins function as the high-order address
lines for the interface. The address output from the
interface takes priority over other digital I/O. The
corresponding TRISH bits are also overridden.
TABLE 10-17: PORTH FUNCTIONS
TRIS
Setting
I/O
Type
Pin Name
RH0/A16
Function
I/O
Description
RH0
0
1
x
0
1
x
0
1
x
0
1
x
0
1
0
1
0
1
0
1
O
I
DIG LATH<0> data output.
ST PORTH<0> data input.
A16
O
O
I
DIG External memory interface, address line 16. Takes priority over port data.
DIG LATH<1> data output.
RH1/A17
RH2/A18
RH3/A19
RH1
ST
PORTH<1> data input.
A17
O
O
I
DIG External memory interface, address line 17. Takes priority over port data.
DIG LATH<2> data output.
RH2
ST
PORTH<2> data input.
A18
O
O
I
DIG External memory interface, address line 18. Takes priority over port data.
DIG LATH<3> data output.
RH3
ST
PORTH<3> data input.
A19
O
O
I
DIG External memory interface, address line 19. Takes priority over port data.
DIG LATH<4> data output.
RH4
RH4
ST
DIG LATH<5> data output.
ST PORTH<5> data input.
DIG LATH<6> data output.
ST PORTH<6> data input.
DIG LATH<7> data output.
ST PORTH<7> data input.
PORTH<4> data input.
RH5
RH5
RH6
RH7
O
I
RH6
O
I
RH7
O
I
Legend:
O = Output, I = Input, DIG = Digital Output, ST = Schmitt Buffer Input, x= Don’t care (TRIS bit does not affect port
direction or is overridden for this option).
TABLE 10-18: SUMMARY OF REGISTERS ASSOCIATED WITH PORTH
Reset
Values
on page
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PORTH
LATH
RH7
RH6
RH5
RH4
RH3
RH2
RH1
RH0
54
54
54
LATH7
TRISH7
LATH6
TRISH6
LATH5
TRISH5
LATH4
TRISH4
LATH3
TRISH3
LATH2
LATH1
LATH0
TRISH
TRISH2 TRISH1 TRISH0
© 2007 Microchip Technology Inc.
Preliminary
DS39774C-page 141
PIC18F85J11 FAMILY
When the external memory interface is enabled, all of
the PORTJ pins function as control outputs for the
interface. This occurs automatically when the interface
is enabled by clearing the EBDIS control bit
(MEMCON<7>). The TRISJ bits are also overridden.
10.10 PORTJ, TRISJ and LATJ Registers
Note: PORTJ is available only on 80-pin devices.
PORTJ is an 8-bit wide, bidirectional port. The corre-
sponding Data Direction and Output Latch registers are
TRISJ and LATJ. All pins on PORTJ are digital only and
tolerate voltages up to 5.5V.
EXAMPLE 10-9:
INITIALIZING PORTJ
CLRF
CLRF
MOVLW
PORTJ
LATJ
0CFh
; Initialize PORTJ by
; clearing output latches
; Alternate method
; to clear output latches
; Value used to
All pins on PORTJ are implemented with Schmitt
Trigger input buffers. Each pin is individually
configurable as an input or output.
Note:
These pins are configured as digital inputs
on any device Reset.
; initialize data
; direction
MOVWF
TRISJ
; Set RJ3:RJ0 as inputs
; RJ5:RJ4 as output
; RJ7:RJ6 as inputs
Each of the PORTJ pins has a weak internal pull-up.
The pull-ups are provided to keep the inputs at a known
state for the external memory interface while powering
up. A single control bit can turn off all the pull-ups. This
is performed by clearing bit, RJPU (PORTG<5>). The
weak pull-up is automatically turned off when the port
pin is configured as an output. The pull-ups are
disabled on any device Reset.
DS39774C-page 142
Preliminary
© 2007 Microchip Technology Inc.
PIC18F85J11 FAMILY
TABLE 10-19: PORTJ FUNCTIONS
TRIS
Setting
I/O
Type
Pin Name
RJ0/ALE
Function
I/O
Description
RJ0
0
1
x
O
I
DIG
ST
LATJ<0> data output.
PORTJ<0> data input.
ALE
RJ1
O
DIG
External memory interface address latch enable control output; takes
priority over digital I/O.
RJ1/OE
RJ2/WRL
RJ3/WRH
RJ4/BA0
RJ5/CE
RJ6/LB
0
1
x
O
I
DIG
ST
LATJ<1> data output.
PORTJ<1> data input.
OE
O
DIG
External memory interface output enable control output; takes priority
over digital I/O.
RJ2
0
1
x
O
I
DIG
ST
LATJ<2> data output.
PORTJ<2> data input.
WRL
RJ3
O
DIG
External memory bus write low byte control; takes priority over
digital I/O.
0
1
x
O
I
DIG
ST
LATJ<3> data output.
PORTJ<3> data input.
WRH
RJ4
O
DIG
External memory interface write high byte control output; takes priority
over digital I/O.
0
1
x
O
I
DIG
ST
LATJ<4> data output.
PORTJ<4> data input.
BA0
RJ5
O
DIG
External memory interface byte address 0 control output; takes priority
over digital I/O.
0
1
x
O
I
DIG
ST
LATJ<5> data output.
PORTJ<5> data input.
CE
O
DIG
External memory interface chip enable control output; takes priority
over digital I/O.
RJ6
0
1
x
O
I
DIG
ST
LATJ<6> data output.
PORTJ<6> data input.
LB
O
DIG
External memory interface lower byte enable control output; takes
priority over digital I/O.
RJ7/UB
Legend:
RJ7
0
1
x
O
I
DIG
ST
LATJ<7> data output.
PORTJ<7> data input.
UB
O
DIG
External memory interface upper byte enable control output; takes
priority over digital I/O.
O = Output, I = Input, DIG = Digital Output, ST = Schmitt Buffer Input, x= Don’t care (TRIS bit does not affect port
direction or is overridden for this option).
TABLE 10-20: SUMMARY OF REGISTERS ASSOCIATED WITH PORTJ
Reset
Values
on page
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PORTJ
RJ7
RJ6
RJ5
RJ4
LATJ4
TRISJ4
RG4
RJ3
LATJ3
TRISJ3
RG3
RJ2
LATJ2
TRISJ2
RG2
RJ1
LATJ1
TRISJ1
RG1
RJ0
LATJ0
TRISJ0
RG0
54
54
54
54
LATJ
LATJ7
TRISJ7
RDPU
LATJ6
TRISJ6
REPU
LATJ5
TRISJ5
RJPU
TRISJ
PORTG
Legend: Shaded cells are not used by PORTJ.
© 2007 Microchip Technology Inc.
Preliminary
DS39774C-page 143
PIC18F85J11 FAMILY
FIGURE 10-3:
PORTD AND PORTE
BLOCK DIAGRAM
(PARALLELSLAVEPORT)
10.11 Parallel Slave Port
PORTD can also function as an 8-bit wide Parallel
Slave Port, or microprocessor port, when control bit
PSPMODE (PSPCON<4>) is set. It is asynchronously
readable and writable by the external world through RD
control input pin, RE0/RD, and WR control input pin,
RE1/WR.
Data Bus
D
Q
RDx
pin
WR LATD
or
CK
Note:
For 80-pin devices, the Parallel Slave Port
is available only in Microcontroller mode.
PORTD
Data Latch
TTL
D
Q
The PSP can directly interface to an 8-bit micro-
processor data bus. The external microprocessor can
read or write the PORTD latch as an 8-bit latch. Setting
bit PSPMODE enables port pin, RE0/RD, to be the RD
input, RE1/WR to be the WR input and RE2/CS to be
the CS (Chip Select) input. For this functionality, the
corresponding data direction bits of the TRISE register
(TRISE<2:0>) must be configured as inputs (set).
RD PORTD
EN
TRIS Latch
RD LATD
A write to the PSP occurs when both the CS and WR
lines are first detected low and ends when either are
detected high. The PSPIF and IBF flag bits are both set
when the write ends.
One bit of PORTD
Set Interrupt Flag
PSPIF (PIR1<7>)
A read from the PSP occurs when both the CS and RD
lines are first detected low. The data in PORTD is read
out and the OBF bit is set. If the user writes new data
to PORTD to set OBF, the data is immediately read out;
however, the OBF bit is not set.
Read
When either the CS or RD lines are detected high, the
PORTD pins return to the input state and the PSPIF bit
is set. User applications should wait for PSPIF to be set
before servicing the PSP. When this happens, the IBF
and OBF bits can be polled and the appropriate action
taken.
RD
CS
TTL
Chip Select
TTL
Write
TTL
WR
The timing for the control signals in Write and Read
modes is shown in Figure 10-4 and Figure 10-5,
respectively.
Note: I/O pin has protection diodes to VDD and VSS.
DS39774C-page 144
Preliminary
© 2007 Microchip Technology Inc.
PIC18F85J11 FAMILY
REGISTER 10-1: PSPCON: PARALLEL SLAVE PORT CONTROL REGISTER
R-0
IBF
R-0
R/W-0
IBOV
R/W-0
U-0
—
U-0
—
U-0
—
U-0
—
OBF
PSPMODE
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7
bit 6
bit 5
bit 4
bit 3-0
IBF: Input Buffer Full Status bit
1= A word has been received and is waiting to be read by the CPU
0= No word has been received
OBF: Output Buffer Full Status bit
1= The output buffer still holds a previously written word
0= The output buffer has been read
IBOV: Input Buffer Overflow Detect bit
1= A write occurred when a previously input word has not been read (must be cleared in software)
0= No overflow occurred
PSPMODE: Parallel Slave Port Mode Select bit
1= Parallel Slave Port mode
0= General Purpose I/O mode
Unimplemented: Read as ‘0’
FIGURE 10-4:
PARALLEL SLAVE PORT WRITE WAVEFORMS
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
CS
WR
RD
PORTD<7:0>
IBF
OBF
PSPIF
© 2007 Microchip Technology Inc.
Preliminary
DS39774C-page 145
PIC18F85J11 FAMILY
FIGURE 10-5:
PARALLEL SLAVE PORT READ WAVEFORMS
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
CS
WR
RD
PORTD<7:0>
IBF
OBF
PSPIF
TABLE 10-21: REGISTERS ASSOCIATED WITH PARALLEL SLAVE PORT
Reset
Values
on page
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PORTD
LATD
RD7
LATD7
TRISD7
RE7
RD6
LATD6
TRISD6
RE6
RD5
LATD5
TRISD5
RE5
RD4
LATD4
TRISD4
RE4
RD3
LATD3
TRISD3
RE3
RD2
LATD2
TRISD2
RE2
RD1
LATD1
TRISD1
RE1
RD0
LATD0
TRISD0
RE0
54
54
54
54
54
54
53
51
53
53
53
TRISD
PORTE
LATE
LATE7
TRISE7
IBF
LATE6
TRISE6
OBF
LATE5
TRISE5
IBOV
LATE4
TRISE4
PSPMODE
INT0IE
TX1IF
LATE3
TRISE3
—
LATE2
TRISE2
—
LATE1
TRISE1
—
LATE0
TRISE0
—
TRISE
PSPCON
INTCON
PIR1
GIE/GIEH PEIE/GIEL TMR0IE
RBIE
TMR0IF
—
INT0IF
TMR2IF
TMR2IE
TMR2IP
RBIF
PSPIF
PSPIE
PSPIP
ADIF
ADIE
ADIP
RC1IF
RC1IE
RC1IP
SSP1IF
SSP1IE
SSP1IP
TMR1IF
TMR1IE
TMR1IP
PIE1
TX1IE
—
IPR1
TX1IP
—
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the Parallel Slave Port.
DS39774C-page 146
Preliminary
© 2007 Microchip Technology Inc.
PIC18F85J11 FAMILY
The T0CON register (Register 11-1) controls all
aspects of the module’s operation, including the
prescale selection; it is both readable and writable.
11.0 TIMER0 MODULE
The Timer0 module incorporates the following features:
• Software selectable operation as a timer or
counter in both 8-bit or 16-bit modes
A simplified block diagram of the Timer0 module in 8-bit
mode is shown in Figure 11-1. Figure 11-2 shows a
simplified block diagram of the Timer0 module in 16-bit
mode.
• Readable and writable registers
• Dedicated, 8-bit software programmable
prescaler
• Selectable clock source (internal or external)
• Edge select for external clock
• Interrupt on overflow
REGISTER 11-1: T0CON: TIMER0 CONTROL REGISTER
R/W-1
R/W-1
R/W-1
T0CS
R/W-1
T0SE
R/W-1
PSA
R/W-1
T0PS2
R/W-1
T0PS1
R/W-1
T0PS0
TMR0ON
T08BIT
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
-n = Value at POR
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2-0
TMR0ON: Timer0 On/Off Control bit
1= Enables Timer0
0= Stops Timer0
T08BIT: Timer0 8-Bit/16-Bit Control bit
1= Timer0 is configured as an 8-bit timer/counter
0= Timer0 is configured as a 16-bit timer/counter
T0CS: Timer0 Clock Source Select bit
1= Transition on T0CKI pin
0= Internal instruction cycle clock (CLKO)
T0SE: Timer0 Source Edge Select bit
1= Increment on high-to-low transition on T0CKI pin
0= Increment on low-to-high transition on T0CKI pin
PSA: Timer0 Prescaler Assignment bit
1= TImer0 prescaler is not assigned. Timer0 clock input bypasses prescaler.
0= Timer0 prescaler is assigned. Timer0 clock input comes from prescaler output.
T0PS2:T0PS0: Timer0 Prescaler Select bits
111= 1:256 Prescale value
110= 1:128 Prescale value
101= 1:64 Prescale value
100= 1:32 Prescale value
011= 1:16 Prescale value
010= 1:8 Prescale value
001= 1:4 Prescale value
000= 1:2 Prescale value
© 2007 Microchip Technology Inc.
Preliminary
DS39774C-page 147
PIC18F85J11 FAMILY
internal phase clock (TOSC). There is a delay between
synchronization and the onset of incrementing the
timer/counter.
11.1 Timer0 Operation
Timer0 can operate as either a timer or a counter. The
mode is selected with the T0CS bit (T0CON<5>). In
Timer mode (T0CS = 0), the module increments on
every clock by default unless a different prescaler value
is selected (see Section 11.3 “Prescaler”). If the
TMR0 register is written to, the increment is inhibited
for the following two instruction cycles. The user can
work around this by writing an adjusted value to the
TMR0 register.
11.2 Timer0 Reads and Writes in
16-Bit Mode
TMR0H is not the actual high byte of Timer0 in 16-bit
mode. It is actually a buffered version of the real high
byte of Timer0 which is not directly readable nor writ-
able (refer to Figure 11-2). TMR0H is updated with the
contents of the high byte of Timer0 during a read of
TMR0L. This provides the ability to read all 16 bits of
Timer0 without having to verify that the read of the high
and low byte were valid, due to a rollover between
successive reads of the high and low byte.
The Counter mode is selected by setting the T0CS bit
(= 1). In this mode, Timer0 increments either on every
rising or falling edge of pin RA4/T0CKI. The increment-
ing edge is determined by the Timer0 Source Edge
Select bit, T0SE (T0CON<4>). Clearing this bit selects
the rising edge. Restrictions on the external clock input
are discussed below.
Similarly, a write to the high byte of Timer0 must also
take place through the TMR0H Buffer register. The high
byte is updated with the contents of TMR0H when a
write occurs to TMR0L. This allows all 16 bits of Timer0
to be updated at once.
An external clock source can be used to drive Timer0;
however, it must meet certain requirements to ensure
that the external clock can be synchronized with the
FIGURE 11-1:
TIMER0 BLOCK DIAGRAM (8-BIT MODE)
FOSC/4
0
1
1
0
Set
TMR0IF
on Overflow
Sync with
Internal
Clocks
TMR0L
8
Programmable
Prescaler
T0CKI pin
(2 TCY Delay)
T0SE
T0CS
3
T0PS2:T0PS0
PSA
8
Internal Data Bus
Note: Upon Reset, Timer0 is enabled in 8-bit mode with clock input from T0CKI max. prescale.
FIGURE 11-2:
TIMER0 BLOCK DIAGRAM (16-BIT MODE)
0
FOSC/4
1
Sync with
Internal
Clocks
Set
TMR0
High Byte
1
TMR0L
TMR0IF
Programmable
Prescaler
on Overflow
8
0
T0CKI pin
(2 TCY Delay)
T0SE
T0CS
3
Read TMR0L
Write TMR0L
T0PS2:T0PS0
PSA
8
8
TMR0H
8
8
Internal Data Bus
Note: Upon Reset, Timer0 is enabled in 8-bit mode with clock input from T0CKI max. prescale.
DS39774C-page 148
Preliminary
© 2007 Microchip Technology Inc.
PIC18F85J11 FAMILY
11.3.1
SWITCHING PRESCALER
ASSIGNMENT
11.3 Prescaler
An 8-bit counter is available as a prescaler for the Timer0
module. The prescaler is not directly readable or writable.
Its value is set by the PSA and T0PS2:T0PS0 bits
(T0CON<3:0>) which determine the prescaler
assignment and prescale ratio.
The prescaler assignment is fully under software
control and can be changed “on-the-fly” during program
execution.
11.4 Timer0 Interrupt
Clearing the PSA bit assigns the prescaler to the
Timer0 module. When it is assigned, prescale values
from 1:2 through 1:256, in power-of-2 increments, are
selectable.
The TMR0 interrupt is generated when the TMR0
register overflows from FFh to 00h in 8-bit mode, or
from FFFFh to 0000h in 16-bit mode. This overflow sets
the TMR0IF flag bit. The interrupt can be masked by
clearing the TMR0IE bit (INTCON<5>). Before
re-enabling the interrupt, the TMR0IF bit must be
cleared in software by the Interrupt Service Routine.
When assigned to the Timer0 module, all instructions
writing to the TMR0 register (e.g., CLRF TMR0, MOVWF
TMR0, BSF TMR0, etc.) clear the prescaler count.
Note:
Writing to TMR0 when the prescaler is
assigned to Timer0 will clear the prescaler
count but will not change the prescaler
assignment.
Since Timer0 is shut down in Sleep mode, the TMR0
interrupt cannot awaken the processor from Sleep.
TABLE 11-1: REGISTERS ASSOCIATED WITH TIMER0
Reset
Values
on page
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
TMR0L
Timer0 Register Low Byte
Timer0 Register High Byte
52
52
51
52
54
TMR0H
INTCON
T0CON
TRISA
GIE/GIEH PEIE/GIEL TMR0IE
TMR0ON T08BIT T0CS
TRISA7(1) TRISA6(1) TRISA5
INT0IE
T0SE
RBIE
PSA
TMR0IF
T0PS2
INT0IF
T0PS1
TRISA1
RBIF
T0PS0
TRISA0
TRISA4
TRISA3
TRISA2
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by Timer0.
Note 1: RA6/RA7 and their associated latch and direction bits are configured as port pins only when the internal
oscillator is selected as the default clock source (FOSC2 Configuration bit = 0); otherwise, they are
disabled and these bits read as ‘0’.
© 2007 Microchip Technology Inc.
Preliminary
DS39774C-page 149
PIC18F85J11 FAMILY
NOTES:
DS39774C-page 150
Preliminary
© 2007 Microchip Technology Inc.
PIC18F85J11 FAMILY
A simplified block diagram of the Timer1 module is
shown in Figure 12-1. A block diagram of the module’s
operation in Read/Write mode is shown in Figure 12-2.
12.0 TIMER1 MODULE
The Timer1 timer/counter module incorporates these
features:
The module incorporates its own low-power oscillator
to provide an additional clocking option. The Timer1
oscillator can also be used as a low-power clock source
for the microcontroller in power-managed operation.
• Software selectable operation as a 16-bit timer or
counter
• Readable and writable 8-bit registers (TMR1H
and TMR1L)
Timer1 can also be used to provide Real-Time Clock
(RTC) functionality to applications with only a minimal
addition of external components and code overhead.
• Selectable clock source (internal or external) with
device clock or Timer1 oscillator internal options
• Interrupt on overflow
Timer1 is controlled through the T1CON Control
register (Register 12-1). It also contains the Timer1
Oscillator Enable bit (T1OSCEN). Timer1 can be
enabled or disabled by setting or clearing control bit,
TMR1ON (T1CON<0>).
• Reset on CCPx Special Event Trigger
• Device clock status flag (T1RUN)
REGISTER 12-1: T1CON: TIMER1 CONTROL REGISTER
R/W-0
RD16
R-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
T1RUN
T1CKPS1
T1CKPS0
T1OSCEN
T1SYNC
TMR1CS
TMR1ON
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
-n = Value at POR
bit 7
RD16: 16-Bit Read/Write Mode Enable bit
1= Enables register read/write of TImer1 in one 16-bit operation
0= Enables register read/write of Timer1 in two 8-bit operations
bit 6
T1RUN: Timer1 System Clock Status bit
1= Device clock is derived from Timer1 oscillator
0= Device clock is derived from another source
bit 5-4
T1CKPS1:T1CKPS0: Timer1 Input Clock Prescale Select bits
11= 1:8 Prescale value
10= 1:4 Prescale value
01= 1:2 Prescale value
00= 1:1 Prescale value
bit 3
bit 2
T1OSCEN: Timer1 Oscillator Enable bit
1= Timer1 oscillator is enabled
0= Timer1 oscillator is shut off
The oscillator inverter and feedback resistor are turned off to eliminate power drain.
T1SYNC: Timer1 External Clock Input Synchronization Select bit
When TMR1CS = 1:
1= Do not synchronize external clock input
0= Synchronize external clock input
When TMR1CS = 0:
This bit is ignored. Timer1 uses the internal clock when TMR1CS = 0.
bit 1
bit 0
TMR1CS: Timer1 Clock Source Select bit
1= External clock from pin RC0/T1OSO/T13CKI (on the rising edge)
0= Internal clock (FOSC/4)
TMR1ON: Timer1 On bit
1= Enables Timer1
0= Stops Timer1
© 2007 Microchip Technology Inc.
Preliminary
DS39774C-page 151
PIC18F85J11 FAMILY
cycle (FOSC/4). When the bit is set, Timer1 increments
on every rising edge of the Timer1 external clock input
or the Timer1 oscillator, if enabled.
12.1 Timer1 Operation
Timer1 can operate in one of these modes:
• Timer
When Timer1 is enabled, the RC1/T1OSI and
RC0/T1OSO/T13CKI pins become inputs. This means
the values of TRISC<1:0> are ignored and the pins are
read as ‘0’.
• Synchronous Counter
• Asynchronous Counter
The operating mode is determined by the clock select
bit, TMR1CS (T1CON<1>). When TMR1CS is cleared
(= 0), Timer1 increments on every internal instruction
FIGURE 12-1:
TIMER1 BLOCK DIAGRAM (8-BIT MODE)
Timer1 Oscillator
Timer1 Clock Input
1
0
On/Off
1
T1OSO/T13CKI
T1OSI
Synchronize
Detect
Prescaler
1, 2, 4, 8
FOSC/4
Internal
Clock
0
2
Sleep Input
T1OSCEN(1)
Timer1
On/Off
TMR1CS
T1CKPS1:T1CKPS0
T1SYNC
TMR1ON
Set
TMR1
High Byte
Clear TMR1
(CCPx Special Event Trigger)
TMR1L
TMR1IF
on Overflow
Note 1: When enable bit, T1OSCEN, is cleared, the inverter and feedback resistor are turned off to eliminate power drain.
FIGURE 12-2:
TIMER1 BLOCK DIAGRAM (16-BIT READ/WRITE MODE)
Timer1 Oscillator
Timer1 Clock Input
1
0
T1OSO/T13CKI
T1OSI
1
0
Synchronize
Detect
Prescaler
1, 2, 4, 8
FOSC/4
Internal
Clock
2
Sleep Input
T1OSCEN(1)
T1CKPS1:T1CKPS0
T1SYNC
Timer1
On/Off
TMR1CS
TMR1ON
Set
TMR1IF
on Overflow
TMR1
Clear TMR1
(CCPx Special Event Trigger)
TMR1L
High Byte
8
Read TMR1L
Write TMR1L
8
8
TMR1H
8
8
Internal Data Bus
Note 1: When enable bit, T1OSCEN, is cleared, the inverter and feedback resistor are turned off to eliminate power drain.
DS39774C-page 152
Preliminary
© 2007 Microchip Technology Inc.
PIC18F85J11 FAMILY
TABLE 12-1: CAPACITOR SELECTION FOR
THE TIMER1
12.2 Timer1 16-Bit Read/Write Mode
Timer1 can be configured for 16-bit reads and writes
(see Figure 12-2). When the RD16 control bit
(T1CON<7>) is set, the address for TMR1H is mapped
to a buffer register for the high byte of Timer1. A read
from TMR1L will load the contents of the high byte of
Timer1 into the Timer1 High Byte Buffer register. This
provides the user with the ability to accurately read all
16 bits of Timer1 without having to determine whether
a read of the high byte, followed by a read of the low
byte, has become invalid due to a rollover between
reads.
OSCILLATOR(2,3,4)
Oscillator
Freq.
C1
C2
Type
LP
32.768 kHz
27 pF(1)
27 pF(1)
Note 1: Microchip suggests these values as a
starting point in validating the oscillator
circuit.
2: Higher capacitance increases the stability
of the oscillator but also increases the
start-up time.
A write to the high byte of Timer1 must also take place
through the TMR1H Buffer register. The Timer1 high
byte is updated with the contents of TMR1H when a
write occurs to TMR1L. This allows a user to write all
16 bits to both the high and low bytes of Timer1 at once.
3: Since each resonator/crystal has its own
characteristics, the user should consult
the resonator/crystal manufacturer for
appropriate
values
of
external
The high byte of Timer1 is not directly readable or
writable in this mode. All reads and writes must take
place through the Timer1 High Byte Buffer register.
Writes to TMR1H do not clear the Timer1 prescaler.
The prescaler is only cleared on writes to TMR1L.
components.
4: Capacitor values are for design guidance
only.
12.3.1
USING TIMER1 AS A
CLOCK SOURCE
12.3 Timer1 Oscillator
The Timer1 oscillator is also available as a clock source
in power-managed modes. By setting the System
Clock Select bits, SCS1:SCS0 (OSCCON<1:0>), to
‘01’, the device switches to SEC_RUN mode; both the
CPU and peripherals are clocked from the Timer1
oscillator. If the IDLEN bit (OSCCON<7>) is cleared
and a SLEEPinstruction is executed, the device enters
SEC_IDLE mode. Additional details are available in
Section 3.0 “Power-Managed Modes”.
An on-chip crystal oscillator circuit is incorporated
between pins T1OSI (input) and T1OSO (amplifier
output). It is enabled by setting the Timer1 Oscillator
Enable bit, T1OSCEN (T1CON<3>). The oscillator is a
low-power circuit rated for 32 kHz crystals. It will
continue to run during all power-managed modes. The
circuit for a typical LP oscillator is shown in Figure 12-3.
Table 12-1 shows the capacitor selection for the Timer1
oscillator.
Whenever the Timer1 oscillator is providing the clock
source, the Timer1 system clock status flag, T1RUN
(T1CON<6>), is set. This can be used to determine the
controller’s current clocking mode. It can also indicate
the clock source being currently used by the Fail-Safe
Clock Monitor. If the Fail-Safe Clock Monitor is enabled
and the Timer1 oscillator fails while providing the clock,
polling the T1RUN bit will indicate whether the clock is
being provided by the Timer1 oscillator or another
source.
The user must provide a software time delay to ensure
proper start-up of the Timer1 oscillator.
FIGURE 12-3:
EXTERNAL
COMPONENTS FOR THE
TIMER1 LP OSCILLATOR
C1
27 pF
PIC18F85J11
T1OSI
XTAL
32.768 kHz
T1OSO
C2
27 pF
Note:
See the Notes with Table 12-1 for additional
information about capacitor selection.
© 2007 Microchip Technology Inc.
Preliminary
DS39774C-page 153
PIC18F85J11 FAMILY
12.3.2
TIMER1 OSCILLATOR LAYOUT
CONSIDERATIONS
12.5 Resetting Timer1 Using the CCPx
Special Event Trigger
The Timer1 oscillator circuit draws very little power
during operation. Due to the low-power nature of the
oscillator, it may also be sensitive to rapidly changing
signals in close proximity.
If CCP1 or CCP2 is configured to use Timer1 and to
generate a Special Event Trigger in Compare mode
(CCPxM3:CCPxM0 = 1011), this signal will reset
Timer3. The trigger from CCP2 will also start an A/D
conversion if the A/D module is enabled (see
Section 15.3.4 “Special Event Trigger” for more
information).
The oscillator circuit, shown in Figure 12-3, should be
located as close as possible to the microcontroller.
There should be no circuits passing within the oscillator
circuit boundaries other than VSS or VDD.
The module must be configured as either a timer or a
synchronous counter to take advantage of this feature.
When used this way, the CCPRxH:CCPRxL register
pair effectively becomes a Period register for Timer1.
If a high-speed circuit must be located near the oscilla-
tor (such as the CCP1 pin in Output Compare or PWM
mode, or the primary oscillator using the OSC2 pin), a
grounded guard ring around the oscillator circuit, as
shown in Figure 12-4, may be helpful when used on a
single-sided PCB or in addition to a ground plane.
If Timer1 is running in Asynchronous Counter mode,
this Reset operation may not work.
In the event that a write to Timer1 coincides with a
Special Event Trigger, the write operation will take
precedence.
FIGURE 12-4:
OSCILLATOR CIRCUIT
WITH GROUNDED
GUARD RING
Note:
The Special Event Triggers from the CCPx
module will not set the TMR1IF interrupt
flag bit (PIR1<0>).
VDD
VSS
12.6 Using Timer1 as a Real-Time Clock
OSC1
OSC2
Adding an external LP oscillator to Timer1 (such as the
one described in Section 12.3 “Timer1 Oscillator”
above) gives users the option to include RTC function-
ality to their applications. This is accomplished with an
inexpensive watch crystal to provide an accurate time
base and several lines of application code to calculate
the time. When operating in Sleep mode and using a
battery or supercapacitor as a power source, it can
completely eliminate the need for a separate RTC
device and battery backup.
RC0
RC1
RC2
The application code routine, RTCisr, shown in
Example 12-1, demonstrates a simple method to
increment a counter at one-second intervals using an
Interrupt Service Routine. Incrementing the TMR1
register pair to overflow triggers the interrupt and calls
the routine which increments the seconds counter by
one. Additional counters for minutes and hours are
incremented as the previous counter overflows.
Note: Not drawn to scale.
12.4 Timer1 Interrupt
The TMR1 register pair (TMR1H:TMR1L) increments
from 0000h to FFFFh and rolls over to 0000h. The
Timer1 interrupt, if enabled, is generated on overflow
which is latched in interrupt flag bit, TMR1IF
(PIR1<0>). This interrupt can be enabled or disabled
by setting or clearing the Timer1 Interrupt Enable bit,
TMR1IE (PIE1<0>).
Since the register pair is 16 bits wide, counting up to
overflow the register directly from a 32.768 kHz clock
would take 2 seconds. To force the overflow at the
required one-second intervals, it is necessary to pre-
load it. The simplest method is to set the MSb of
TMR1H with a BSF instruction. Note that the TMR1L
register is never preloaded or altered; doing so may
introduce cumulative error over many cycles.
For this method to be accurate, Timer1 must operate in
Asynchronous mode and the Timer1 overflow interrupt
must be enabled (PIE1<0> = 1), as shown in the
routine, RTCinit. The Timer1 oscillator must also be
enabled and running at all times.
DS39774C-page 154
Preliminary
© 2007 Microchip Technology Inc.
PIC18F85J11 FAMILY
EXAMPLE 12-1:
IMPLEMENTING A REAL-TIME CLOCK USING A TIMER1 INTERRUPT SERVICE
RTCinit
MOVLW
MOVWF
CLRF
80h
TMR1H
TMR1L
; Preload TMR1 register pair
; for 1 second overflow
MOVLW
MOVWF
CLRF
b’00001111’
T1CON
secs
; Configure for external clock,
; Asynchronous operation, external oscillator
; Initialize timekeeping registers
;
CLRF
mins
MOVLW
MOVWF
BSF
.12
hours
PIE1, TMR1IE
; Enable Timer1 interrupt
RETURN
RTCisr
BSF
BCF
INCF
MOVLW
TMR1H, 7
PIR1, TMR1IF
secs, F
.59
; Preload for 1 sec overflow
; Clear interrupt flag
; Increment seconds
; 60 seconds elapsed?
CPFSGT secs
RETURN
; No, done
CLRF
INCF
MOVLW
secs
mins, F
.59
; Clear seconds
; Increment minutes
; 60 minutes elapsed?
CPFSGT mins
RETURN
; No, done
CLRF
INCF
MOVLW
mins
hours, F
.23
; clear minutes
; Increment hours
; 24 hours elapsed?
CPFSGT hours
RETURN
; No, done
; Reset hours
; Done
CLRF
hours
RETURN
TABLE 12-2: REGISTERS ASSOCIATED WITH TIMER1 AS A TIMER/COUNTER
Reset
Values
on page
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
INTCON
PIR1
GIE/GIEH PEIE/GIEL TMR0IE
INT0IE
TX1IF
TX1IE
TX1IP
RBIE
SSPIF
SSPIE
SSPIP
TMR0IF
INT0IF
TMR2IF
TMR2IE
TMR2IP
RBIF
51
53
53
53
52
52
52
PSPIF
PSPIE
PSPIP
ADIF
ADIE
ADIP
RC1IF
RC1IE
RC1IP
—
—
—
TMR1IF
TMR1IE
TMR1IP
PIE1
IPR1
TMR1L
TMR1H
T1CON
Timer1 Register Low Byte
Timer1 Register High Byte
RD16
T1RUN T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON
Legend: Shaded cells are not used by the Timer1 module.
© 2007 Microchip Technology Inc.
Preliminary
DS39774C-page 155
PIC18F85J11 FAMILY
NOTES:
DS39774C-page 156
Preliminary
© 2007 Microchip Technology Inc.
PIC18F85J11 FAMILY
13.1 Timer2 Operation
13.0 TIMER2 MODULE
In normal operation, TMR2 is incremented from 00h on
each clock (FOSC/4). A 4-bit counter/prescaler on the
clock input gives direct input, divide-by-4 and
divide-by-16 prescale options. These are selected by
the prescaler control bits, T2CKPS1:T2CKPS0
(T2CON<1:0>). The value of TMR2 is compared to that
of the Period register, PR2, on each clock cycle. When
the two values match, the comparator generates a
match signal as the timer output. This signal also resets
the value of TMR2 to 00h on the next cycle and drives
the output counter/postscaler (see Section 13.2
“Timer2 Interrupt”).
The Timer2 module incorporates the following features:
• 8-bit Timer and Period registers (TMR2 and PR2,
respectively)
• Readable and writable (both registers)
• Software programmable prescaler
(1:1, 1:4 and 1:16)
• Software programmable postscaler
(1:1 through 1:16)
• Interrupt on TMR2 to PR2 match
• Optional use as the shift clock for the
MSSP module
The TMR2 and PR2 registers are both directly readable
and writable. The TMR2 register is cleared on any
device Reset while the PR2 register initializes at FFh.
Both the prescaler and postscaler counters are cleared
on the following events:
The module is controlled through the T2CON register
(Register 13-1) which enables or disables the timer and
configures the prescaler and postscaler. Timer2 can be
shut off by clearing control bit, TMR2ON (T2CON<2>),
to minimize power consumption.
• a write to the TMR2 register
• a write to the T2CON register
A simplified block diagram of the module is shown in
Figure 13-1.
• any device Reset (Power-on Reset, MCLR Reset,
Watchdog Timer Reset or Brown-out Reset)
TMR2 is not cleared when T2CON is written.
REGISTER 13-1: T2CON: TIMER2 CONTROL REGISTER
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
T2OUTPS3 T2OUTPS2 T2OUTPS1 T2OUTPS0
TMR2ON
T2CKPS1
T2CKPS0
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7
Unimplemented: Read as ‘0’
bit 6-3
T2OUTPS3:T2OUTPS0: Timer2 Output Postscale Select bits
0000= 1:1 Postscale
0001= 1:2 Postscale
•
•
•
1111= 1:16 Postscale
bit 2
TMR2ON: Timer2 On bit
1= Timer2 is on
0= Timer2 is off
bit 1-0
T2CKPS1:T2CKPS0: Timer2 Clock Prescale Select bits
00= Prescaler is 1
01= Prescaler is 4
1x= Prescaler is 16
© 2007 Microchip Technology Inc.
Preliminary
DS39774C-page 157
PIC18F85J11 FAMILY
13.2 Timer2 Interrupt
13.3 Timer2 Output
Timer2 can also generate an optional device interrupt.
The Timer2 output signal (TMR2 to PR2 match) pro-
vides the input for the 4-bit output counter/postscaler.
This counter generates the TMR2 match interrupt flag
which is latched in TMR2IF (PIR1<1>). The interrupt is
enabled by setting the TMR2 Match Interrupt Enable
bit, TMR2IE (PIE1<1>).
The unscaled output of TMR2 is available primarily to
the CCP modules where it is used as a time base for
operations in PWM mode.
Timer2 can be optionally used as the shift clock source
for the MSSP module operating in SPI mode.
Additional information is provided in Section 16.0
“Master Synchronous Serial Port (MSSP) Module”.
A range of 16 postscale options (from 1:1 through 1:16
inclusive) can be selected with the postscaler control
bits, T2OUTPS3:T2OUTPS0 (T2CON<6:3>).
FIGURE 13-1:
TIMER2 BLOCK DIAGRAM
4
1:1 to 1:16
Set TMR2IF
Postscaler
T2OUTPS3:T2OUTPS0
2
TMR2 Output
T2CKPS1:T2CKPS0
(to PWM or MSSP)
TMR2/PR2
Match
Reset
TMR2
1:1, 1:4, 1:16
Prescaler
FOSC/4
Comparator
PR2
8
8
8
Internal Data Bus
TABLE 13-1: REGISTERS ASSOCIATED WITH TIMER2 AS A TIMER/COUNTER
Reset
Values
on page
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
INTCON GIE/GIEH PEIE/GIEL TMR0IE
INT0IE
TX1IF
TX1IE
TX1IP
RBIE
SSPIF
SSPIE
SSPIP
TMR0IF
INT0IF
TMR2IF
TMR2IE
TMR2IP
RBIF
51
53
53
53
52
52
52
PIR1
PSPIF
PSPIE
PSPIP
ADIF
ADIE
ADIP
RC1IF
RC1IE
RC1IP
—
—
—
TMR1IF
TMR1IE
TMR1IP
PIE1
IPR1
TMR2
T2CON
PR2
Timer2 Register
T2OUTPS3 T2OUTPS2 T2OUTPS1 T2OUTPS0 TMR2ON T2CKPS1 T2CKPS0
Timer2 Period Register
—
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the Timer2 module.
DS39774C-page 158
Preliminary
© 2007 Microchip Technology Inc.
PIC18F85J11 FAMILY
A simplified block diagram of the Timer3 module is
shown in Figure 14-1. A block diagram of the module’s
operation in Read/Write mode is shown in Figure 14-2.
14.0 TIMER3 MODULE
The Timer3 timer/counter module incorporates these
features:
The Timer3 module is controlled through the T3CON
register (Register 14-1). It also selects the clock source
options for the CCP modules. See Section 15.2.2
“Timer1/Timer3 Mode Selection” for more
information.
• Software selectable operation as a 16-bit timer or
counter
• Readable and writable 8-bit registers (TMR3H
and TMR3L)
• Selectable clock source (internal or external) with
device clock or Timer1 oscillator internal options
• Interrupt on overflow
• Module Reset on CCPx Special Event Trigger
REGISTER 14-1: T3CON: TIMER3 CONTROL REGISTER
R/W-0
RD16
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
T3CCP2
T3CKPS1
T3CKPS0
T3CCP1
T3SYNC
TMR3CS
TMR3ON
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
-n = Value at POR
bit 7
RD16: 16-Bit Read/Write Mode Enable bit
1= Enables register read/write of Timer3 in one 16-bit operation
0= Enables register read/write of Timer3 in two 8-bit operations
bit 6,3
T3CCP2:T3CCP1: Timer3 and Timer1 to CCPx Enable bits
1x= Timer3 is the capture/compare clock source for the CCP modules
01= Timer3 is the capture/compare clock source for CCP2;
Timer1 is the capture/compare clock source for CCP1
00= Timer1 is the capture/compare clock source for the CCP modules
bit 5-4
bit 2
T3CKPS1:T3CKPS0: Timer3 Input Clock Prescale Select bits
11= 1:8 Prescale value
10= 1:4 Prescale value
01= 1:2 Prescale value
00= 1:1 Prescale value
T3SYNC: Timer3 External Clock Input Synchronization Control bit
(Not usable if the device clock comes from Timer1/Timer3.)
When TMR3CS = 1:
1= Do not synchronize external clock input
0= Synchronize external clock input
When TMR3CS = 0:
This bit is ignored. Timer3 uses the internal clock when TMR3CS = 0.
bit 1
bit 0
TMR3CS: Timer3 Clock Source Select bit
1= External clock input from Timer1 oscillator or T13CKI (on the rising edge after the first
falling edge)
0= Internal clock (FOSC/4)
TMR3ON: Timer3 On bit
1= Enables Timer3
0= Stops Timer3
© 2007 Microchip Technology Inc.
Preliminary
DS39774C-page 159
PIC18F85J11 FAMILY
The operating mode is determined by the clock select
bit, TMR3CS (T3CON<1>). When TMR3CS is cleared
(= 0), Timer3 increments on every internal instruction
cycle (FOSC/4). When the bit is set, Timer3 increments
on every rising edge of the Timer1 external clock input
or the Timer1 oscillator, if enabled.
14.1 Timer3 Operation
Timer3 can operate in one of three modes:
• Timer
• Synchronous Counter
• Asynchronous Counter
As
with
Timer1,
the
RC1/T1OSI
and
RC0/T1OSO/T13CKI pins become inputs when the
Timer1 oscillator is enabled. This means the values of
TRISC<1:0> are ignored and the pins are read as ‘0’.
FIGURE 14-1:
TIMER3 BLOCK DIAGRAM (8-BIT MODE)
Timer1 Oscillator
Timer1 Clock Input
1
0
1
0
T1OSO/T13CKI
T1OSI
Synchronize
Detect
Prescaler
1, 2, 4, 8
FOSC/4
Internal
Clock
2
Sleep Input
T1OSCEN(1)
T3CKPS1:T3CKPS0
T3SYNC
Timer3
On/Off
TMR3CS
TMR3ON
CCPx Special Event Trigger
CCPx Select from T3CON<6,3>
Clear TMR3
Set
TMR3
High Byte
TMR3L
TMR3IF
on Overflow
Note 1: When enable bit, T1OSCEN, is cleared, the inverter and feedback resistor are turned off to eliminate power drain.
FIGURE 14-2:
TIMER3 BLOCK DIAGRAM (16-BIT READ/WRITE MODE)
Timer1 Oscillator
Timer1 Clock Input
1
0
1
0
T1OSO/T13CKI
T1OSI
Synchronize
Detect
Prescaler
1, 2, 4, 8
FOSC/4
Internal
Clock
2
Sleep Input
T1OSCEN(1)
T3CKPS1:T3CKPS0
T3SYNC
Timer3
On/Off
TMR3CS
TMR3ON
CCPx Special Event Trigger
Clear TMR3
Set
TMR3
High Byte
TMR3L
TMR3IF
CCPx Select from T3CON<6,3>
on Overflow
8
Read TMR1L
Write TMR1L
8
8
TMR3H
8
8
Internal Data Bus
Note 1: When enable bit, T1OSCEN, is cleared, the inverter and feedback resistor are turned off to eliminate power drain.
DS39774C-page 160
Preliminary
© 2007 Microchip Technology Inc.
PIC18F85J11 FAMILY
14.2 Timer3 16-Bit Read/Write Mode
14.4 Timer3 Interrupt
Timer3 can be configured for 16-bit reads and writes
(see Figure 14-2). When the RD16 control bit
(T3CON<7>) is set, the address for TMR3H is mapped
to a buffer register for the high byte of Timer3. A read
from TMR3L will load the contents of the high byte of
Timer3 into the Timer3 High Byte Buffer register. This
provides the user with the ability to accurately read all
16 bits of Timer1 without having to determine whether
a read of the high byte, followed by a read of the low
byte, has become invalid due to a rollover between
reads.
The TMR3 register pair (TMR3H:TMR3L) increments
from 0000h to FFFFh and overflows to 0000h. The
Timer3 interrupt, if enabled, is generated on overflow
and is latched in interrupt flag bit, TMR3IF (PIR2<1>).
This interrupt can be enabled or disabled by setting or
clearing the Timer3 Interrupt Enable bit, TMR3IE
(PIE2<1>).
14.5 Resetting Timer3 Using the CCPx
Special Event Trigger
If CCP1 or CCP2 is configured to use Timer3 and to
generate a Special Event Trigger in Compare mode
(CCPxM3:CCPxM0 = 1011), this signal will reset
Timer3. The trigger from CCP2 will also start an A/D
conversion if the A/D module is enabled (see
Section 15.3.4 “Special Event Trigger” for more
information).
A write to the high byte of Timer3 must also take place
through the TMR3H Buffer register. The Timer3 high
byte is updated with the contents of TMR3H when a
write occurs to TMR3L. This allows a user to write all
16 bits to both the high and low bytes of Timer3 at once.
The high byte of Timer3 is not directly readable or
writable in this mode. All reads and writes must take
place through the Timer3 High Byte Buffer register.
The module must be configured as either a timer or
synchronous counter to take advantage of this feature.
When used this way, the CCPRxH:CCPRxL register
pair effectively becomes a Period register for Timer3.
Writes to TMR3H do not clear the Timer3 prescaler.
The prescaler is only cleared on writes to TMR3L.
If Timer3 is running in Asynchronous Counter mode,
the Reset operation may not work.
14.3 Using the Timer1 Oscillator as the
Timer3 Clock Source
In the event that a write to Timer3 coincides with a
Special Event Trigger from a CCPx module, the write
will take precedence.
The Timer1 internal oscillator may be used as the clock
source for Timer3. The Timer1 oscillator is enabled by
setting the T1OSCEN (T1CON<3>) bit. To use it as the
Timer3 clock source, the TMR3CS bit must also be set.
As previously noted, this also configures Timer3 to
increment on every rising edge of the oscillator source.
Note:
The Special Event Triggers from the CCPx
module will not set the TMR3IF interrupt
flag bit (PIR2<1>).
The Timer1 oscillator is described in Section 12.0
“Timer1 Module”.
TABLE 14-1: REGISTERS ASSOCIATED WITH TIMER3 AS A TIMER/COUNTER
Reset
Values
on page
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
INTCON
PIR2
GIE/GIEH PEIE/GIEL TMR0IE
INT0IE
—
RBIE
BCLIF
BCLIE
BCLIP
TMR0IF
LVDIF
LVDIE
LVDIP
INT0IF
TMR3IF
TMR3IE
TMR3IP
RBIF
—
51
53
53
53
53
53
52
53
OSCFIF
OSCFIE
OSCFIP
CMIF
CMIE
CMIP
—
—
—
PIE2
—
—
IPR2
—
—
TMR3L
TMR3H
T1CON
T3CON
Timer3 Register Low Byte
Timer3 Register High Byte
RD16
RD16
T1RUN T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON
T3CCP2 T3CKPS1 T3CKPS0 T3CCP1 T3SYNC TMR3CS TMR3ON
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the Timer3 module.
© 2007 Microchip Technology Inc.
Preliminary
DS39774C-page 161
PIC18F85J11 FAMILY
NOTES:
DS39774C-page 162
Preliminary
© 2007 Microchip Technology Inc.
PIC18F85J11 FAMILY
Each CCP module contains a 16-bit register which can
operate as a 16-bit Capture register, a 16-bit Compare
register or a PWM Master/Slave Duty Cycle register.
For the sake of clarity, all CCP module operation in the
following sections is described with respect to CCP2,
but is equally applicable to CCP1.
15.0 CAPTURE/COMPARE/PWM
(CCP) MODULES
PIC18F85J11 family devices have two CCP
(Capture/Compare/PWM) modules, designated CCP1
and CCP2. Both modules implement standard Capture,
Compare and Pulse-Width Modulation (PWM) modes.
REGISTER 15-1: CCPxCON: CCPx CONTROL REGISTER (CCP1, CCP2 MODULES)
U-0
—
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
DCxB1
DCxB0
CCPxM3
CCPxM2
CCPxM1
CCPxM0
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7-6
bit 5-4
Unimplemented: Read as ‘0’
DCxB1:DCxB0: PWM Duty Cycle bit 1 and bit 0 for CCPx Module
Capture mode:
Unused.
Compare mode:
Unused.
PWM mode:
These bits are the two Least Significant bits (bit 1 and bit 0) of the 10-bit PWM duty cycle. The eight
Most Significant bits (DCx9:DCx2) of the duty cycle are found in CCPRxL.
bit 3-0
CCPxM3:CCPxM0: CCPx Module Mode Select bits
0000= Capture/Compare/PWM disabled (resets CCPx module)
0001= Reserved
0010= Compare mode, toggle output on match (CCPxIF bit is set)
0011= Reserved
0100= Capture mode, every falling edge
0101= Capture mode, every rising edge
0110= Capture mode, every 4th rising edge
0111= Capture mode, every 16th rising edge
1000= Compare mode: initialize CCPx pin low; on compare match, force CCPx pin high (CCPxIF bit
is set)
1001= Compare mode: initialize CCPx pin high; on compare match, force CCPx pin low (CCPxIF bit
is set)
1010= Compare mode: generate software interrupt on compare match (CCPxIF bit is set, CCPx pin
reflects I/O state)
1011= Compare mode: Special Event Trigger; reset timer; start A/D conversion on CCPx match
(CCPxIF bit is set)(1)
11xx= PWM mode
Note 1: CCPxM3:CCPxM0 = 1011will only reset timer and not start A/D conversion on CCPx match.
© 2007 Microchip Technology Inc.
Preliminary
DS39774C-page 163
PIC18F85J11 FAMILY
Depending on the configuration selected, up to four
timers may be active at once, with modules in the same
configuration (Capture/Compare or PWM) sharing
timer resources. The possible configurations are
shown in Figure 15-1.
15.1 CCP Module Configuration
Each Capture/Compare/PWM module is associated
with a control register (generically, CCPxCON) and a
data register (CCPRx). The data register, in turn, is
comprised of two 8-bit registers: CCPRxL (low byte)
and CCPRxH (high byte). All registers are both
readable and writable.
15.1.2
OPEN-DRAIN OUTPUT OPTION
When operating in Output mode (i.e., in Compare or
PWM modes), the drivers for the CCPx pins can be
optionally configured as open-drain outputs. This
feature allows the voltage level on the pin to be pulled
to a higher level through an external pull-up resistor
and allows the output to communicate with external
circuits without the need for additional level shifters.
15.1.1
CCP MODULES AND TIMER
RESOURCES
The CCP modules utilize Timers 1, 2 or 3, depending
on the mode selected. Timer1 and Timer3 are available
to modules in Capture or Compare mode, while Timer2
is available for modules in PWM mode.
The open-drain output option is controlled by the
CCP2OD and CCP1OD bits (TRISG<6:5>). Setting the
appropriate bit configures the pin for the corresponding
module for open-drain operation.
TABLE 15-1: CCPx MODE – TIMER
RESOURCE
CCPx Mode
Timer Resource
15.1.3
CCP2 PIN ASSIGNMENT
Capture
Compare
PWM
Timer1 or Timer3
Timer1 or Timer3
Timer2
The pin assignment for CCP2 (Capture input, Compare
and PWM output) can change, based on device config-
uration. The CCP2MX Configuration bit determines
which pin CCP2 is multiplexed to. By default, it is
assigned to RC1 (CCP2MX = 1). If the Configuration bit
is cleared, CCP2 is multiplexed with RE7.
The assignment of a particular timer to a module is
determined by the timer to CCPx enable bits in the
T3CON register (Register 14-1). Both modules may be
active at any given time and may share the same timer
resource if they are configured to operate in the same
mode (Capture/Compare or PWM) at the same time.
The interactions between the two modules are
summarized in Table 15-2.
Changing the pin assignment of CCP2 does not
automatically change any requirements for configuring
the port pin. Users must always verify that the appropri-
ate TRIS register is configured correctly for CCP2
operation, regardless of where it is located.
FIGURE 15-1:
CCPx AND TIMER INTERCONNECT CONFIGURATIONS
T3CCP<2:1> = 00
T3CCP<2:1> = 01
T3CCP<2:1> = 1x
TMR1
TMR3
TMR1
TMR3
TMR1
TMR3
CCP1
CCP2
CCP1
CCP1
CCP2
CCP2
TMR2
TMR2
TMR2
Timer1 is used for all Capture
and Compare operations for
all CCP modules. Timer2 is
used for PWM operations for
all CCP modules. Modules
may share either timer
resource as a common time
base.
Timer1 is used for Capture
and Compare operations for
CCP1 and Timer 3 is used for
CCP2.
Timer3 is used for all Capture
and Compare operations for
all CCP modules. Timer2 is
used for PWM operations for
all CCP modules. Modules
may share either timer
resource as a common time
base.
Both the modules use Timer2
as a common time base if they
are in PWM modes.
DS39774C-page 164
Preliminary
© 2007 Microchip Technology Inc.
PIC18F85J11 FAMILY
TABLE 15-2: INTERACTIONS BETWEEN CCP1 AND CCP2 FOR TIMER RESOURCES
CCP1 Mode CCP2 Mode
Interaction
Capture
Capture
Each module can use TMR1 or TMR3 as the time base. The time base can be different
for each CCP module.
Capture
Compare CCP2 can be configured for the Special Event Trigger to reset TMR1 or TMR3
(depending upon which time base is used). Automatic A/D conversions on trigger event
can also be done. Operation of CCP1 could be affected if it is using the same timer as a
time base.
Compare
Compare
Capture
CCP1 can be configured for the Special Event Trigger to reset TMR1 or TMR3
(depending upon which time base is used). Operation of CCP2 could be affected if it is
using the same timer as a time base.
Compare Either module can be configured for the Special Event Trigger to reset the time base.
Automatic A/D conversions on CCP2 trigger event can be done. Conflicts may occur if
both modules are using the same time base.
Capture
Compare
PWM
PWM
PWM
None
None
None
Capture
PWM
Compare None
PWM Both PWMs will have the same frequency and update rate (TMR2 interrupt).
PWM
© 2007 Microchip Technology Inc.
Preliminary
DS39774C-page 165
PIC18F85J11 FAMILY
15.2.3
SOFTWARE INTERRUPT
15.2 Capture Mode
When the Capture mode is changed, a false capture
interrupt may be generated. The user should keep the
CCP2IE bit (PIE3<2>) clear to avoid false interrupts
and should clear the flag bit, CCP2IF, following any
such change in operating mode.
In Capture mode, the CCPR2H:CCPR2L register pair
captures the 16-bit value of the TMR1 or TMR3 register
when an event occurs on the CCP2 pin (RB3, RC1 or
RE7, depending on device configuration). An event is
defined as one of the following:
• every falling edge
• every rising edge
15.2.4
CCP PRESCALER
There are four prescaler settings in Capture mode.
They are specified as part of the operating mode
selected by the mode select bits (CCP2M3:CCP2M0).
Whenever the CCP2 module is turned off, or the CCP2
module is not in Capture mode, the prescaler counter
is cleared. This means that any Reset will clear the
prescaler counter.
• every 4th rising edge
• every 16th rising edge
The event is selected by the mode select bits,
CCP2M3:CCP2M0 (CCP2CON<3:0>). When
a
capture is made, the interrupt request flag bit, CCP2IF
(PIR3<2>), is set; it must be cleared in software. If
another capture occurs before the value in register
CCPR2 is read, the old captured value is overwritten by
the new captured value.
Switching from one capture prescaler to another may
generate an interrupt. Also, the prescaler counter will
not be cleared; therefore, the first capture may be from
a
non-zero prescaler. Example 15-1 shows the
15.2.1
CCPx PIN CONFIGURATION
recommended method for switching between capture
prescalers. This example also clears the prescaler
counter and will not generate the “false” interrupt.
In Capture mode, the appropriate CCPx pin should be
configured as an input by setting the corresponding
TRIS direction bit.
EXAMPLE 15-1:
CHANGING BETWEEN
CAPTURE PRESCALERS
Note: If RB3/INT3/CCP2, RC1/T1OSI/CCP2 or
RE7/CCP2 is configured as an output, a write
to the port can cause a capture condition.
CLRF CCP2CON
MOVLW NEW_CAPT_PS ; Load WREG with the
; new prescaler mode
; Turn CCP module off
15.2.2
TIMER1/TIMER3 MODE SELECTION
; value and CCP ON
The timers that are to be used with the capture feature
(Timer1 and/or Timer3) must be running in Timer mode or
Synchronized Counter mode. In Asynchronous Counter
mode, the capture operation may not work. The timer to
be used with each CCP module is selected in the T3CON
register (see Section 15.1.1 “CCP Modules and Timer
Resources”).
MOVWF CCP2CON
; Load CCP2CON with
; this value
FIGURE 15-2:
CAPTURE MODE OPERATION BLOCK DIAGRAM
TMR3H
TMR3L
Set CCP1IF
T3CCP2
TMR3
Enable
CCP1 pin
Prescaler
÷ 1, 4, 16
and
Edge Detect
CCPR1H
CCPR1L
TMR1
Enable
T3CCP2
TMR1H
TMR1L
TMR3L
4
4
CCP1CON<3:0>
Q1:Q4
Set CCP2IF
4
CCP2CON<3:0>
TMR3H
T3CCP1
T3CCP2
TMR3
Enable
CCP2 pin
Prescaler
÷ 1, 4, 16
and
Edge Detect
CCPR2H
CCPR2L
TMR1L
TMR1
Enable
T3CCP2
T3CCP1
TMR1H
DS39774C-page 166
Preliminary
© 2007 Microchip Technology Inc.
PIC18F85J11 FAMILY
15.3.3
SOFTWARE INTERRUPT MODE
15.3 Compare Mode
When the Generate Software Interrupt mode is chosen
(CCP2M3:CCP2M0 = 1010), the CCP2 pin is not
affected. Only a CCP2 interrupt is generated, if
enabled, and the CCP2IE bit is set.
In Compare mode, the 16-bit CCPR2 register value is
constantly compared against either the TMR1 or TMR3
register pair value. When a match occurs, the CCP2
pin can be:
• driven high
15.3.4
SPECIAL EVENT TRIGGER
• driven low
Both CCP modules are equipped with a Special Event
Trigger. This is an internal hardware signal generated
in Compare mode to trigger actions by other modules.
The Special Event Trigger is enabled by selecting
the Compare Special Event Trigger mode
(CCP2M3:CCP2M0 = 1011).
• toggled (high-to-low or low-to-high)
• remains unchanged (that is, reflects the state of
the I/O latch)
The action on the pin is based on the value of the mode
select bits (CCP2M3:CCP2M0). At the same time, the
interrupt flag bit, CCP2IF, is set.
For either CCP module, the Special Event Trigger resets
the Timer register pair for whichever timer resource is
currently assigned as the module’s time base. This
allows the CCPRx registers to serve as a Programmable
Period register for either timer.
15.3.1
CCPx PIN CONFIGURATION
The user must configure the CCPx pin as an output by
clearing the appropriate TRIS bit.
The Special Event Trigger for CCP2 can also start an
A/D conversion. In order to do this, the A/D converter
must already be enabled.
Note:
Clearing the CCP2CON register will force
the RB3, RC1 or RE7 compare output
latch (depending on device configuration)
to the default low level. This is not the
PORTB, PORTC or PORTE I/O data latch.
Note:
The Special Event Trigger of CCP1 only
resets Timer1/Timer3 and cannot start an
A/D conversion even when the A/D
converter is enabled.
15.3.2
TIMER1/TIMER3 MODE SELECTION
Timer1 and/or Timer3 must be running in Timer mode,
or Synchronized Counter mode, if the CCPx module is
using the compare feature. In Asynchronous Counter
mode, the compare operation may not work.
FIGURE 15-3:
COMPARE MODE OPERATION BLOCK DIAGRAM
Special Event Trigger
(Timer1 Reset)
Set CCP1IF
CCPR1H
CCPR1L
CCP1 pin
S
R
Q
Output
Logic
Compare
Match
Comparator
TRIS
Output Enable
4
CCP1CON<3:0>
TMR1H
TMR3H
TMR1L
TMR3L
0
0
1
1
Special Event Trigger
(Timer1/Timer3 Reset, A/D Trigger)
T3CCP1
T3CCP2
Set CCP2IF
CCP2 pin
S
R
Q
Compare
Match
Output
Logic
Comparator
TRIS
Output Enable
4
CCPR2H
CCPR2L
CCP2CON<3:0>
© 2007 Microchip Technology Inc.
Preliminary
DS39774C-page 167
PIC18F85J11 FAMILY
TABLE 15-3: REGISTERS ASSOCIATED WITH CAPTURE, COMPARE, TIMER1 AND TIMER3
Reset
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Values
on Page
INTCON
RCON
GIE/GIEH PEIE/GIEL TMR0IE
INT0IE
RI
RBIE
TO
TMR0IF
PD
INT0IF
POR
RBIF
BOR
—
51
52
53
53
53
53
53
53
54
54
54
52
52
52
53
53
53
54
54
54
55
55
55
IPEN
—
—
—
CM
RC2IF
RC2IE
RC2IP
—
PIR3
TX2IF
TX2IE
TX2IP
—
—
CCP2IF
CCP1IF
PIE3
—
—
—
CCP2IE CCP1IE
CCP2IP CCP1IP
—
IPR3
—
—
—
—
PIR2
OSCFIF
OSCFIE
OSCFIP
TRISC7
TRISE7
SPIOD
CMIF
CMIE
CMIP
TRISC6
TRISE6
BCLIF
BCLIE
BCLIP
TRISC3
TRISE3
TRISG3
LVDIF
LVDIE
LVDIP
TRISC2
—
TMR3IF
TMR3IE
TMR3IP
TRISC1
TRISE1
—
PIE2
—
—
—
IPR2
—
—
—
TRISC
TRISE
TRISC5
TRISE5
TRISC4
TRISE4
TRISC0
TRISE0
TRISG
TMR1L
TMR1H
T1CON
TMR3H
TMR3L
T3CON
CCPR1L
CCPR1H
CCP1CON
CCPR2L
CCPR2H
CCP2CON
CCP2OD CCP1OD TRISG4
TRISG2 TRISG1 TRISG0
Timer1 Register Low Byte
Timer1 Register High Byte
RD16
T1RUN T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON
Timer3 Register High Byte
Timer3 Register Low Byte
RD16
T3CCP2 T3CKPS1 T3CKPS0 T3CCP1 T3SYNC TMR3CS TMR3ON
Capture/Compare/PWM Register 1 Low Byte
Capture/Compare/PWM Register 1 High Byte
—
—
DC1B1
DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0
Capture/Compare/PWM Register 2 Low Byte
Capture/Compare/PWM Register 2 High Byte
—
—
DC2B1
DC2B0 CCP2M3 CCP2M2 CCP2M1 CCP2M0
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by Capture/Compare, Timer1 or Timer3.
DS39774C-page 168
Preliminary
© 2007 Microchip Technology Inc.
PIC18F85J11 FAMILY
A PWM output (Figure 15-5) has a time base (period)
and a time that the output stays high (duty cycle). The
frequency of the PWM is the inverse of the period
(1/period).
15.4 PWM Mode
In Pulse-Width Modulation (PWM) mode, the CCP2 pin
produces up to a 10-bit resolution PWM output. Since
the CCP2 pin is multiplexed with a PORTB, PORTC or
PORTE data latch, the appropriate TRIS bit must be
cleared to make the CCP2 pin an output.
FIGURE 15-5:
PWM OUTPUT
Period
Note:
Clearing the CCP2CON register will force
the RB3, RC1 or RE7 output latch
(depending on device configuration) to the
default low level. This is not the PORTB,
PORTC or PORTE I/O data latch.
Duty Cycle
TMR2 = PR2
Figure 15-4 shows a simplified block diagram of the
CCP1 module in PWM mode.
TMR2 = Duty Cycle
TMR2 = PR2
For a step-by-step procedure on how to set up the CCP
module for PWM operation, see Section 15.4.3
“Setup for PWM Operation”.
15.4.1
PWM PERIOD
The PWM period is specified by writing to the PR2
register. The PWM period can be calculated using the
following formula:
FIGURE 15-4:
SIMPLIFIED PWM BLOCK
DIAGRAM
CCP1CON<5:4>
Duty Cycle Registers
EQUATION 15-1:
CCPR1L
PWM Period = (PR2) + 1] • 4 • TOSC •
(TMR2 Prescale Value)
PWM frequency is defined as 1/[PWM period].
CCPR1H (Slave)
Comparator
When TMR2 is equal to PR2, the following three events
occur on the next increment cycle:
Q
R
S
RC2/CCP1
• TMR2 is cleared
(Note 1)
TMR2
• The CCP2 pin is set (exception: if PWM duty
cycle = 0%, the CCP2 pin will not be set)
• The PWM duty cycle is latched from CCPR2L into
CCPR2H
TRISC<2>
Comparator
PR2
Clear Timer,
CCP1 pin and
latch D.C.
Note:
The Timer2 postscalers (see Section 13.0
“Timer2 Module”) are not used in the
determination of the PWM frequency. The
postscaler could be used to have a servo
update rate at a different frequency than
the PWM output.
Note 1: The 8-bit TMR2 value is concatenated with the 2-bit
internal Q clock, or 2 bits of the prescaler, to create
the 10-bit time base.
© 2007 Microchip Technology Inc.
Preliminary
DS39774C-page 169
PIC18F85J11 FAMILY
The CCPR2H register and a 2-bit internal latch are
used to double-buffer the PWM duty cycle. This
double-buffering is essential for glitchless PWM
operation.
15.4.2
PWM DUTY CYCLE
The PWM duty cycle is specified by writing to the
CCPR2L register and to the CCP2CON<5:4> bits. Up
to 10-bit resolution is available. The CCPR2L contains
the eight MSbs and the CCP2CON<5:4> contains the
two LSbs. This 10-bit value is represented by
CCPR2L:CCP2CON<5:4>. The following equation is
used to calculate the PWM duty cycle in time:
When the CCPR2H and 2-bit latch match TMR2,
concatenated with an internal 2-bit Q clock or 2 bits of
the TMR2 prescaler, the CCP2 pin is cleared.
The maximum PWM resolution (bits) for a given PWM
frequency is given by the equation:
EQUATION 15-2:
PWM Duty Cycle = (CCPR2L:CCP2CON<5:4>) •
TOSC • (TMR2 Prescale Value)
EQUATION 15-3:
FOSC
⎛
⎝
⎞
⎠
---------------
log
FPWM
PWM Resolution (max)
= ----------------------------- b i t s
CCPR2L and CCP2CON<5:4> can be written to at any
time, but the duty cycle value is not latched into
CCPR2H until after a match between PR2 and TMR2
occurs (i.e., the period is complete). In PWM mode,
CCPR2H is a read-only register.
log(2)
Note:
If the PWM duty cycle value is longer than
the PWM period, the CCP2 pin will not be
cleared.
TABLE 15-4: EXAMPLE PWM FREQUENCIES AND RESOLUTIONS AT 40 MHz
PWM Frequency
2.44 kHz
9.77 kHz
39.06 kHz 156.25 kHz 312.50 kHz 416.67 kHz
Timer Prescaler (1, 4, 16)
PR2 Value
16
FFh
14
4
1
1
3Fh
8
1
1Fh
7
1
FFh
12
FFh
10
17h
6.58
Maximum Resolution (bits)
DS39774C-page 170
Preliminary
© 2007 Microchip Technology Inc.
PIC18F85J11 FAMILY
3. Make the CCP2 pin an output by clearing the
appropriate TRIS bit.
15.4.3
SETUP FOR PWM OPERATION
The following steps should be taken when configuring
the CCP module for PWM operation:
4. Set the TMR2 prescale value, then enable
Timer2 by writing to T2CON.
1. Set the PWM period by writing to the PR2
register.
5. Configure the CCP2 module for PWM operation.
2. Set the PWM duty cycle by writing to the
CCPR2L register and CCP2CON<5:4> bits.
TABLE 15-5: REGISTERS ASSOCIATED WITH PWM AND TIMER2
Reset
Values
on Page
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
INTCON
RCON
PIR1
GIE/GIEH PEIE/GIEL TMR0IE
INT0IE
RI
RBIE
TO
TMR0IF
PD
INT0IF
POR
RBIF
BOR
51
52
53
53
53
54
54
54
52
52
52
54
54
54
55
55
55
IPEN
PSPIF
PSPIE
PSPIP
TRISC7
TRISE7
SPIOD
—
CM
ADIF
RC1IF
RC1IE
RC1IP
TRISC5
TRISE5
TX1IF
TX1IE
TX1IP
TRISC4
TRISE4
TRISG4
SSPIF
SSPIE
SSPIP
TRISC3
TRISE3
TRISG3
—
TMR2IF TMR1IF
TMR2IE TMR1IE
TMR2IP TMR1IP
PIE1
ADIE
—
IPR1
ADIP
—
TRISC
TRISE
TRISG
TMR2
PR2
TRISC6
TRISE6
TRISC2 TRISC1 TRISC0
TRISE1 TRISE0
TRISG2 TRISG1 TRISG0
—
CCP2OD CCP1OD
Timer2 Register
Timer2 Period Register
T2CON
—
T2OUTPS3 T2OUTPS2 T2OUTPS1 T2OUTPS0 TMR2ON T2CKPS1 T2CKPS0
CCPR1L Capture/Compare/PWM Register 1 Low Byte
CCPR1H Capture/Compare/PWM Register 1 High Byte
CCP1CON
—
—
DC1B1
DC1B0
CCP1M3 CCP1M2 CCP1M1 CCP1M0
CCPR2L Capture/Compare/PWM Register 2 Low Byte
CCPR2H Capture/Compare/PWM Register 2 High Byte
CCP2CON
—
—
DC2B1
DC2B0
CCP2M3 CCP2M2 CCP2M1 CCP2M0
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PWM or Timer2.
© 2007 Microchip Technology Inc.
Preliminary
DS39774C-page 171
PIC18F85J11 FAMILY
NOTES:
DS39774C-page 172
Preliminary
© 2007 Microchip Technology Inc.
PIC18F85J11 FAMILY
16.3 SPI Mode
16.0 MASTER SYNCHRONOUS
SERIAL PORT (MSSP)
MODULE
The SPI mode allows 8 bits of data to be synchronously
transmitted and received simultaneously. All four
modes of SPI are supported. To accomplish
communication, typically three pins are used:
16.1 Master SSP (MSSP) Module
Overview
• Serial Data Out (SDO) – RC5/SDO
• Serial Data In (SDI) – RC4/SDI/SDA
• Serial Clock (SCK) – RC3/SCK/SCL
The Master Synchronous Serial Port (MSSP) module is
a serial interface, useful for communicating with other
peripheral or microcontroller devices. These peripheral
devices may be serial EEPROMs, shift registers,
display drivers, A/D converters, etc. The MSSP module
can operate in one of two modes:
Additionally, a fourth pin may be used when in a Slave
mode of operation:
• Slave Select (SS) – RF7/AN5/SS
Figure 16-1 shows the block diagram of the MSSP
module when operating in SPI mode.
• Serial Peripheral Interface (SPI)
• Inter-Integrated Circuit (I2C™)
- Full Master mode
FIGURE 16-1:
MSSP BLOCK DIAGRAM
(SPI MODE)
- Slave mode (with general address call)
The I2C interface supports the following modes in
hardware:
Internal
Data Bus
• Master mode
• Multi-Master mode
• Slave mode
Read
Write
SSPBUF reg
16.2 Control Registers
SDI
The MSSP module has three associated control
registers. These include a status register (SSPSTAT)
and two control registers (SSPCON1 and SSPCON2).
The use of these registers and their individual bits differ
significantly depending on whether the MSSP module
is operated in SPI or I2C mode.
SSPSR reg
Shift
Clock
bit 0
SDO
Additional details are provided under the individual
sections.
SS
Control
Enable
SS
Edge
Select
2
Clock Select
SSPM3:SSPM0
SMP:CKE
2
4
TMR2 Output
2
(
)
SCK
Edge
Select
TOSC
Prescaler
4, 16, 64
Data to TXx/RXx in SSPSR
TRIS bit
© 2007 Microchip Technology Inc.
Preliminary
DS39774C-page 173
PIC18F85J11 FAMILY
SSPSR is the shift register used for shifting data in or
out. SSPBUF is the buffer register to which data bytes
are written to or read from.
16.3.1
REGISTERS
The MSSP module has four registers for SPI mode
operation. These are:
In receive operations, SSPSR and SSPBUF together
create a double-buffered receiver. When SSPSR
receives a complete byte, it is transferred to SSPBUF
and the SSPIF interrupt is set.
• MSSP Control Register 1 (SSPCON1)
• MSSP Status Register (SSPSTAT)
• Serial Receive/Transmit Buffer Register (SSPBUF)
• MSSP Shift Register (SSPSR) – Not directly
accessible
During
transmission,
the
SSPBUF
is
not
double-buffered. A write to SSPBUF will write to both
SSPBUF and SSPSR.
SSPCON1 and SSPSTAT are the control and status
registers in SPI mode operation. The SSPCON1
register is readable and writable. The lower 6 bits of
the SSPSTAT are read-only. The upper two bits of the
SSPSTAT are read/write.
REGISTER 16-1: SSPSTAT: MSSP STATUS REGISTER (SPI MODE)
R/W-0
SMP
R/W-0
CKE(1)
R-0
D/A
R-0
P
R-0
S
R-0
R0
UA
R-0
BF
R/W
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7
SMP: Sample bit
SPI Master mode:
1= Input data sampled at end of data output time
0= Input data sampled at middle of data output time
SPI Slave mode:
SMP must be cleared when SPI is used in Slave mode.
bit 6
CKE: SPI Clock Select bit(1)
1= Transmit occurs on transition from active to Idle clock state
0= Transmit occurs on transition from Idle to active clock state
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
D/A: Data/Address bit
Used in I2C™ mode only.
P: Stop bit
Used in I2C mode only. This bit is cleared when the MSSP module is disabled, SSPEN is cleared.
S: Start bit
Used in I2C mode only.
R/W: Read/Write Information bit
Used in I2C mode only.
UA: Update Address bit
Used in I2C mode only.
BF: Buffer Full Status bit (Receive mode only)
1= Receive complete, SSPBUF is full
0= Receive not complete, SSPBUF is empty
Note 1: Polarity of clock state is set by the CKP bit (SSPCON1<4>).
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Preliminary
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REGISTER 16-2: SSPCON1: MSSP CONTROL REGISTER 1 (SPI MODE)
R/W-0
WCOL
R/W-0
SSPOV(1)
R/W-0
SSPEN(2)
R/W-0
CKP
R/W-0
SSPM3(3)
R/W-0
SSPM2(3)
R/W-0
SSPM1(3)
R/W-0
SSPM0(3)
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7
WCOL: Write Collision Detect bit (Transmit mode only)
1= The SSPBUF register is written while it is still transmitting the previous word (must be cleared in
software)
0= No collision
bit 6
SSPOV: Receive Overflow Indicator bit(1)
SPI Slave mode:
1= A new byte is received while the SSPBUF register is still holding the previous data. In case of over-
flow, the data in SSPSR is lost. Overflow can only occur in Slave mode. The user must read the
SSPBUF, even if only transmitting data, to avoid setting overflow (must be cleared in software).
0= No overflow
bit 5
SSPEN: Master Synchronous Serial Port Enable bit(2)
1= Enables serial port and configures SCK, SDO, SDI and SS as serial port pins
0= Disables serial port and configures these pins as I/O port pins
bit 4
CKP: Clock Polarity Select bit
1= Idle state for clock is a high level
0= Idle state for clock is a low level
bit 3-0
SSPM3:SSPM0: Master Synchronous Serial Port Mode Select bits(3)
0101= SPI Slave mode, clock = SCK pin, SS pin control disabled, SS can be used as I/O pin
0100= SPI Slave mode, clock = SCK pin, SS pin control enabled
0011= SPI Master mode, clock = TMR2 output/2
0010= SPI Master mode, clock = FOSC/64
0001= SPI Master mode, clock = FOSC/16
0000= SPI Master mode, clock = FOSC/4
Note 1: In Master mode, the overflow bit is not set, since each new reception (and transmission) is initiated by
writing to the SSPBUF register.
2: When enabled, this pin must be properly configured as an input or output.
3: Bit combinations not specifically listed here are either reserved or implemented in I2C™ mode only.
© 2007 Microchip Technology Inc.
Preliminary
DS39774C-page 175
PIC18F85J11 FAMILY
before reading the data that was just received. Any
write to the SSPBUF register during transmis-
sion/reception of data will be ignored and the Write
Collision detect bit, WCOL (SSPCON1<7>), will be set.
User software must clear the WCOL bit so that it can be
determined if the following write(s) to the SSPBUF
register completed successfully.
16.3.2
OPERATION
When initializing the SPI, several options need to be
specified. This is done by programming the appropriate
control bits (SSPCON1<5:0> and SSPSTAT<7:6>).
These control bits allow the following to be specified:
• Master mode (SCK is the clock output)
• Slave mode (SCK is the clock input)
• Clock Polarity (Idle state of SCK)
When the application software is expecting to receive
valid data, the SSPBUF should be read before the next
byte of data to transfer is written to the SSPBUF. The
Buffer Full bit, BF (SSPSTAT<0>), indicates when
SSPBUF has been loaded with the received data (trans-
mission is complete). When the SSPBUF is read, the BF
bit is cleared. This data may be irrelevant if the SPI is
only a transmitter. Generally, the MSSP interrupt is used
to determine when the transmission/reception has com-
pleted. The SSPBUF must be read and/or written. If the
interrupt method is not going to be used, then software
polling can be done to ensure that a write collision does
not occur. Example 16-1 shows the loading of the
SSPBUF (SSPSR) for data transmission.
• Data Input Sample Phase (middle or end of data
output time)
• Clock Edge (output data on rising/falling edge of
SCK)
• Clock Rate (Master mode only)
• Slave Select mode (Slave mode only)
The MSSP consists of a transmit/receive shift register
(SSPSR) and a buffer register (SSPBUF). The SSPSR
shifts the data in and out of the device, MSb first. The
SSPBUF holds the data that was written to the SSPSR
until the received data is ready. Once the 8 bits of data
have been received, that byte is moved to the SSPBUF
register. Then, the Buffer Full detect bit, BF
(SSPSTAT<0>), and the MSSP Interrupt Flag bit,
SSPIF, are set. This double-buffering of the received
data (SSPBUF) allows the next byte to start reception
The SSPSR is not directly readable or writable and can
only be accessed by addressing the SSPBUF register.
Additionally, the SSPSTAT register indicates the
various status conditions.
EXAMPLE 16-1:
LOADING THE SSPBUF (SSPSR) REGISTER
LOOP
BTFSS
BRA
SSPSTAT, BF
LOOP
;Has data been received (transmit complete)?
;No
MOVF
MOVWF
MOVF
MOVWF
SSPBUF, W
RXDATA
TXDATA, W
SSPBUF
;WREG reg = contents of SSPBUF
;Save in user RAM, if data is meaningful
;W reg = contents of TXDATA
;New data to xmit
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Preliminary
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PIC18F85J11 FAMILY
to a higher level through an external pull-up resistor,
and allows the output to communicate with external
circuits without the need for additional level shifters.
16.3.3
ENABLING SPI I/O
To enable the serial port, MSSP Enable bit, SSPEN
(SSPCON1<5>), must be set. To reset or reconfigure
SPI mode, clear the SSPEN bit, reinitialize the
SSPCON registers and then set the SSPEN bit. This
configures the SDI, SDO, SCK and SS pins as serial
port pins. For the pins to behave as the serial port func-
tion, some must have their data direction bits (in the
TRIS register) appropriately programmed as follows:
The open-drain output option is controlled by the
SPIOD bit (TRISG<7>). Setting the bit configures both
pins for open-drain operation.
16.3.5
TYPICAL CONNECTION
Figure 16-2 shows a typical connection between two
microcontrollers. The master controller (Processor 1)
initiates the data transfer by sending the SCK signal.
Data is shifted out of both shift registers on their pro-
grammed clock edge and latched on the opposite edge
of the clock. Both processors should be programmed to
the same Clock Polarity (CKP), then both controllers
would send and receive data at the same time.
Whether the data is meaningful (or dummy data)
depends on the application software. This leads to
three scenarios for data transmission:
• SDI is automatically controlled by the SPI module
• SDO must have TRISC<5> bit cleared
• SCK (Master mode) must have TRISC<3> bit
cleared
• SCK (Slave mode) must have TRISC<3> bit set
• SS must have TRISF<7> bit set
Any serial port function that is not desired may be
overridden by programming the corresponding data
direction (TRIS) register to the opposite value.
• Master sends data – Slave sends dummy data
• Master sends data – Slave sends data
16.3.4
OPEN-DRAIN OUTPUT OPTION
The drivers for the SDO output and SCK clock pins can
be optionally configured as open-drain outputs. This
feature allows the voltage level on the pin to be pulled
• Master sends dummy data – Slave sends data
FIGURE 16-2:
SPI MASTER/SLAVE CONNECTION
SPI Master SSPM3:SSPM0 = 00xx
SPI Slave SSPM3:SSPM0 = 010x
SDO
SDI
Serial Input Buffer
(SSPBUF)
Serial Input Buffer
(SSPBUF)
SDI
SDO
SCK
Shift Register
(SSPSR)
Shift Register
(SSPSR)
LSb
MSb
MSb
LSb
Serial Clock
SCK
PROCESSOR 1
PROCESSOR 2
© 2007 Microchip Technology Inc.
Preliminary
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The clock polarity is selected by appropriately
programming the CKP bit (SSPCON1<4>). This, then,
would give waveforms for SPI communication as
shown in Figure 16-3, Figure 16-5 and Figure 16-6,
where the MSB is transmitted first. In Master mode, the
SPI clock rate (bit rate) is user-programmable to be one
of the following:
16.3.6
MASTER MODE
The master can initiate the data transfer at any time
because it controls the SCK. The master determines
when the slave (Processor 2, Figure 16-2) will
broadcast data by the software protocol.
In Master mode, the data is transmitted/received as
soon as the SSPBUF register is written to. If the SPI is
only going to receive, the SDO output could be dis-
abled (programmed as an input). The SSPSR register
will continue to shift in the signal present on the SDI pin
at the programmed clock rate. As each byte is
received, it will be loaded into the SSPBUF register as
if a normal received byte (interrupts and status bits
appropriately set). This could be useful in receiver
applications as a “Line Activity Monitor” mode.
• FOSC/4 (or TCY)
• FOSC/16 (or 4 • TCY)
• FOSC/64 (or 16 • TCY)
• Timer2 output/2
This allows a maximum data rate (at 40 MHz) of
10.00 Mbps.
Figure 16-3 shows the waveforms for Master mode.
When the CKE bit is set, the SDO data is valid before
there is a clock edge on SCK. The change of the input
sample is shown based on the state of the SMP bit. The
time when the SSPBUF is loaded with the received
data is shown.
FIGURE 16-3:
SPI MODE WAVEFORM (MASTER MODE)
Write to
SSPBUF
SCK
(CKP = 0
CKE = 0)
SCK
(CKP = 1
CKE = 0)
4 Clock
Modes
SCK
(CKP = 0
CKE = 1)
SCK
(CKP = 1
CKE = 1)
SDO
bit 6
bit 6
bit 2
bit 2
bit 5
bit 5
bit 4
bit 4
bit 1
bit 1
bit 0
bit 0
bit 7
bit 7
bit 3
bit 3
(CKE = 0)
SDO
(CKE = 1)
SDI
(SMP = 0)
bit 0
bit 7
Input
Sample
(SMP = 0)
SDI
(SMP = 1)
bit 0
bit 7
Input
Sample
(SMP = 1)
SSPIF
Next Q4 Cycle
after Q2↓
SSPSR to
SSPBUF
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Preliminary
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PIC18F85J11 FAMILY
driven. When the SS pin goes high, the SDO pin is no
longer driven, even if in the middle of a transmitted byte
16.3.7
SLAVE MODE
In Slave mode, the data is transmitted and received as
the external clock pulses appear on SCK. When the
last bit is latched, the SSPIF interrupt flag bit is set.
and
becomes
a
floating
output.
External
pull-up/pull-down resistors may be desirable depending
on the application.
Before enabling the module in SPI Slave mode, the
clock line must match the proper Idle state. The clock
line can be observed by reading the SCK pin. The Idle
state is determined by the CKP bit (SSPCON1<4>).
Note 1: When the SPI is in Slave mode with SS pin
control enabled (SSPCON1<3:0> = 0100),
the SPI module will reset if the SS pin is set
to VDD.
While in Slave mode, the external clock is supplied by
the external clock source on the SCK pin. This external
clock must meet the minimum high and low times as
specified in the electrical specifications.
2: If the SPI is used in Slave mode with CKE
set, then the SS pin control must be
enabled.
When the SPI module resets, the bit counter is forced
to ‘0’. This can be done by either forcing the SS pin to
a high level or clearing the SSPEN bit.
While in Sleep mode, the slave can transmit/receive
data. When a byte is received, the device will wake-up
from Sleep.
To emulate two-wire communication, the SDO pin can
be connected to the SDI pin. When the SPI needs to
operate as a receiver, the SDO pin can be configured
as an input. This disables transmissions from the SDO.
The SDI can always be left as an input (SDI function)
since it cannot create a bus conflict.
16.3.8
SLAVE SELECT
SYNCHRONIZATION
The SS pin allows a Synchronous Slave mode. The SPI
must be in Slave mode with SS pin control enabled
(SSPCON1<3:0> = 04h). When the SS pin is low, trans-
mission and reception are enabled and the SDO pin is
FIGURE 16-4:
SLAVE SYNCHRONIZATION WAVEFORM
SS
SCK
(CKP = 0
CKE = 0)
SCK
(CKP = 1
CKE = 0)
Write to
SSPBUF
bit 6
bit 7
bit 7
bit 0
SDO
bit 7
SDI
(SMP = 0)
bit 0
bit 7
Input
Sample
(SMP = 0)
SSPIF
Interrupt
Flag
Next Q4 Cycle
after Q2
↓
SSPSR to
SSPBUF
© 2007 Microchip Technology Inc.
Preliminary
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PIC18F85J11 FAMILY
FIGURE 16-5:
SPI MODE WAVEFORM (SLAVE MODE WITH CKE = 0)
SS
Optional
SCK
(CKP = 0
CKE = 0)
SCK
(CKP = 1
CKE = 0)
Write to
SSPBUF
bit 6
bit 2
bit 5
bit 4
bit 3
bit 1
bit 0
SDO
bit 7
SDI
(SMP = 0)
bit 0
bit 7
Input
Sample
(SMP = 0)
SSPIF
Interrupt
Flag
Next Q4 Cycle
after Q2↓
SSPSR to
SSPBUF
FIGURE 16-6:
SPI MODE WAVEFORM (SLAVE MODE WITH CKE = 1)
SS
Not Optional
SCK
(CKP = 0
CKE = 1)
SCK
(CKP = 1
CKE = 1)
Write to
SSPBUF
bit 6
bit 3
bit 2
bit 5
bit 4
bit 1
bit 0
SDO
bit 7
bit 7
SDI
(SMP = 0)
bit 0
Input
Sample
(SMP = 0)
SSPIF
Interrupt
Flag
Next Q4 Cycle
after Q2↓
SSPSR to
SSPBUF
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Preliminary
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mode and data to be shifted into the SPI
Transmit/Receive Shift register. When all 8 bits have
been received, the MSSP interrupt flag bit will be set,
and if enabled, will wake the device.
16.3.9
OPERATION IN POWER-MANAGED
MODES
In SPI Master mode, module clocks may be operating
at a different speed than when in full power mode; in
the case of Sleep mode, all clocks are halted.
16.3.10 EFFECTS OF A RESET
In Idle modes, a clock is provided to the peripherals.
That clock should be from the primary clock source, the
secondary clock (Timer1 oscillator at 32.768 kHz) or
the INTRC source. See Section 2.3 “Clock Sources
and Oscillator Switching” for additional information.
A Reset disables the MSSP module and terminates the
current transfer.
16.3.11 BUS MODE COMPATIBILITY
Table 16-1 shows the compatibility between the
standard SPI modes and the states of the CKP and
CKE control bits.
In most cases, the speed that the master clocks SPI
data is not important; however, this should be
evaluated for each system.
TABLE 16-1: SPI BUS MODES
If MSSP interrupts are enabled, they can wake the con-
troller from Sleep mode, or one of the Idle modes, when
the master completes sending data. If an exit from
Sleep or Idle mode is not desired, MSSP interrupts
should be disabled.
Control Bits State
Standard SPI Mode
Terminology
CKP
CKE
0, 0
0, 1
1, 0
1, 1
0
0
1
1
1
0
1
0
If the Sleep mode is selected, all module clocks are
halted and the transmission/reception will remain in
that state until the devices wakes. After the device
returns to Run mode, the module will resume
transmitting and receiving data.
There is also an SMP bit which controls when the data
is sampled.
In SPI Slave mode, the SPI Transmit/Receive Shift
register operates asynchronously to the device. This
allows the device to be placed in any power-managed
TABLE 16-2: REGISTERS ASSOCIATED WITH SPI OPERATION
Reset
Values
on page
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
INTCON
PIR1
GIE/GIEH PEIE/GIEL TMR0IE
INT0IE
TX1IF
RBIE
SSPIF
TMR0IF
—
INT0IF
RBIF
51
53
53
53
54
54
54
52
52
52
PSPIF
PSPIE
PSPIP
TRISC7
TRISF7
SPIOD
ADIF
ADIE
RC1IF
RC1IE
RC1IP
TRISC5
TRISF5
TMR2IF
TMR1IF
PIE1
TX1IE
SSPIE
SSPIP
TRISC3
TRISF3
TRISG3
—
TMR2IE TMR1IE
TMR2IP TMR1IP
IPR1
ADIP
TX1IP
—
TRISC
TRISF
TRISC6
TRISF6
TRISC4
TRISF4
TRISC2
TRISF2
TRISG2
TRISC1
TRISF1
TRISG1
TRISC0
—
TRISG
SSPBUF
SSPCON1
SSPSTAT
CCP2OD CCP1OD TRISG4
TRISG0
MSSP Receive Buffer/Transmit Register
WCOL
SMP
SSPOV
CKE
SSPEN
D/A
CKP
P
SSPM3
S
SSPM2
R/W
SSPM1
UA
SSPM0
BF
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the MSSP module in SPI mode.
© 2007 Microchip Technology Inc.
Preliminary
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PIC18F85J11 FAMILY
2
16.4.1
REGISTERS
16.4 I C Mode
The MSSP module has six registers for I2C operation.
These are:
The MSSP module in I2C mode fully implements all
master and slave functions (including general call
support) and provides interrupts on Start and Stop bits
in hardware to determine a free bus (multi-master
function). The MSSP module implements the standard
mode specifications, as well as 7-bit and 10-bit
addressing.
• MSSP Control Register 1 (SSPCON1)
• MSSP Control Register 2 (SSPCON2)
• MSSP Status Register (SSPSTAT)
• Serial Receive/Transmit Buffer Register
(SSPBUF)
Two pins are used for data transfer:
• MSSP Shift Register (SSPSR) – Not directly
accessible
• Serial Clock (SCL) – RC3/SCK/SCL
• Serial Data (SDA) – RC4/SDI/SDA
• MSSP Address Register (SSPADD)
The user must configure these pins as inputs by setting
the TRISC<4:3> bits.
SSPCON1, SSPCON2 and SSPSTAT are the control
and status registers in I2C mode operation. The
SSPCON1 and SSPCON2 registers are readable and
writable. The lower 6 bits of the SSPSTAT are
read-only. The upper two bits of the SSPSTAT are
read/write.
FIGURE 16-7:
MSSP BLOCK DIAGRAM
(I2C™ MODE)
Internal
Many of the bits in SSPCON2 assume different
functions, depending on whether the module is operat-
ing in Master or Slave mode; bits <5:2> also assume
different names in Slave mode. The different aspects of
SSPCON2 are shown in Register 16-5 (for Master
mode) and Register 16-6 (Slave mode).
Data Bus
Read
Write
SSPBUF reg
SCL
SDA
Shift
Clock
SSPSR is the shift register used for shifting data in or
out. SSPBUF is the buffer register to which data bytes
are written to or read from.
SSPSR reg
LSb
MSb
SSPADD register holds the slave device address when
the MSSP is configured in I2C Slave mode. When the
MSSP is configured in Master mode, the lower seven
bits of SSPADD act as the Baud Rate Generator reload
value.
Match Detect
Addr Match
Address Mask
In receive operations, SSPSR and SSPBUF together
create a double-buffered receiver. When SSPSR
receives a complete byte, it is transferred to SSPBUF
and the SSPIF interrupt is set.
SSPADD reg
Set, Reset
S, P bits
(SSPSTAT reg)
Start and
Stop bit Detect
During
transmission,
the
SSPBUF
is
not
double-buffered. A write to SSPBUF will write to both
SSPBUF and SSPSR.
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Preliminary
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REGISTER 16-3: SSPSTAT: MSSP STATUS REGISTER (I2C™ MODE)
R/W-0
SMP
R/W-0
CKE
R-0
D/A
R-0
P(1)
R-0
S(1)
R-0
R0
UA
R-0
BF
R/W
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7
SMP: Slew Rate Control bit
In Master or Slave mode:
1 = Slew rate control disabled for Standard Speed mode (100 kHz and 1 MHz)
0 = Slew rate control enabled for High-Speed mode (400 kHz)
bit 6
bit 5
CKE: SMBus Select bit
In Master or Slave mode:
1= Enable SMBus specific inputs
0= Disable SMBus specific inputs
D/A: Data/Address bit
In Master mode:
Reserved.
In Slave mode:
1= Indicates that the last byte received or transmitted was data
0= Indicates that the last byte received or transmitted was address
bit 4
bit 3
bit 2
P: Stop bit(1)
1= Indicates that a Stop bit has been detected last
0= Stop bit was not detected last
S: Start bit(1)
1= Indicates that a Start bit has been detected last
0= Start bit was not detected last
R/W: Read/Write Information bit (I2C mode only)
In Slave mode:(2)
1= Read
0= Write
In Master mode:(3)
1= Transmit is in progress
0= Transmit is not in progress
bit 1
bit 0
UA: Update Address bit (10-Bit Slave mode only)
1= Indicates that the user needs to update the address in the SSPADD register
0= Address does not need to be updated
BF: Buffer Full Status bit
In Transmit mode:
1= SSPBUF is full
0= SSPBUF is empty
In Receive mode:
1= SSPBUF is full (does not include the ACK and Stop bits)
0= SSPBUF is empty (does not include the ACK and Stop bits)
Note 1: This bit is cleared on Reset and when SSPEN is cleared.
2: This bit holds the R/W bit information following the last address match. This bit is only valid from the
address match to the next Start bit, Stop bit or not ACK bit.
3: ORing this bit with SEN, RSEN, PEN, RCEN or ACKEN will indicate if the MSSP is in Active mode.
© 2007 Microchip Technology Inc.
Preliminary
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REGISTER 16-4: SSPCON1: MSSP CONTROL REGISTER 1 (I2C™ MODE)
R/W-0
WCOL
R/W-0
R/W-0
SSPEN(1)
R/W-0
CKP
R/W-0
R/W-0
R/W-0
R/W-0
SSPOV
SSPM3
SSPM2
SSPM1
SSPM0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
-n = Value at POR
bit 7
WCOL: Write Collision Detect bit
In Master Transmit mode:
1= A write to the SSPBUF register was attempted while the I2C conditions were not valid for a
transmission to be started (must be cleared in software)
0= No collision
In Slave Transmit mode:
1= The SSPBUF register is written while it is still transmitting the previous word (must be cleared in
software)
0= No collision
In Receive mode (Master or Slave modes):
This is a “don’t care” bit.
bit 6
SSPOV: Receive Overflow Indicator bit
In Receive mode:
1= A byte is received while the SSPBUF register is still holding the previous byte (must be cleared in
software)
0= No overflow
In Transmit mode:
This is a “don’t care” bit in Transmit mode.
bit 5
bit 4
SSPEN: Master Synchronous Serial Port Enable bit(1)
1= Enables the serial port and configures the SDA and SCL pins as the serial port pins
0= Disables serial port and configures these pins as I/O port pins
CKP: SCK Release Control bit
In Slave mode:
1= Release clock
0= Holds clock low (clock stretch), used to ensure data setup time
In Master mode:
Unused in this mode.
bit 3-0
SSPM3:SSPM0: Synchronous Serial Port Mode Select bits
1111= I2C Slave mode, 10-bit address with Start and Stop bit interrupts enabled
1110= I2C Slave mode, 7-bit address with Start and Stop bit interrupts enabled
1011= I2C Firmware Controlled Master mode (slave Idle)
1000= I2C Master mode, clock = FOSC/(4 * (SSPADD + 1))
0111= I2C Slave mode, 10-bit address
0110= I2C Slave mode, 7-bit address
Bit combinations not specifically listed here are either reserved or implemented in SPI mode only.
Note 1: When enabled, the SDA and SCL pins must be configured as inputs.
DS39774C-page 184
Preliminary
© 2007 Microchip Technology Inc.
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REGISTER 16-5: SSPCON2: MSSP CONTROL REGISTER 2 (I2C™ MASTER MODE)
R/W-0
GCEN
R/W-0
R/W-0
ACKDT(1)
R/W-0
ACKEN(2)
R/W-0
RCEN(2)
R/W-0
PEN(2)
R/W-0
RSEN(2)
R/W-0
SEN(2)
ACKSTAT
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7
bit 6
GCEN: General Call Enable bit
Unused in Master mode.
ACKSTAT: Acknowledge Status bit (Master Transmit mode only)
1= Acknowledge was not received from slave
0= Acknowledge was received from slave
bit 5
bit 4
ACKDT: Acknowledge Data bit (Master Receive mode only)(1)
1= Not Acknowledge
0= Acknowledge
ACKEN: Acknowledge Sequence Enable bit(2)
1= Initiate Acknowledge sequence on SDA and SCL pins and transmit ACKDT data bit. Automatically
cleared by hardware.
0= Acknowledge sequence Idle
bit 3
bit 2
bit 1
bit 0
RCEN: Receive Enable bit (Master Receive mode only)(2)
1= Enables Receive mode for I2C
0= Receive Idle
PEN: Stop Condition Enable bit(2)
1= Initiate Stop condition on SDA and SCL pins. Automatically cleared by hardware.
0= Stop condition Idle
RSEN: Repeated Start Condition Enable bit(2)
1= Initiate Repeated Start condition on SDA and SCL pins. Automatically cleared by hardware.
0= Repeated Start condition Idle
SEN: Start Condition Enable bit(2)
1= Initiate Start condition on SDA and SCL pins. Automatically cleared by hardware.
0= Start condition Idle
Note 1: Value that will be transmitted when the user initiates an Acknowledge sequence at the end of a receive.
2: If the I2C module is active, these bits may not be set (no spooling) and the SSPBUF may not be written (or
writes to the SSPBUF are disabled).
© 2007 Microchip Technology Inc.
Preliminary
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REGISTER 16-6: SSPCON2: MSSP CONTROL REGISTER 2 (I2C™ SLAVE MODE)
R/W-0
GCEN
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
SEN(1)
ACKSTAT
ADMSK5
ADMSK4
ADMSK3
ADMSK2
ADMSK1
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7
GCEN: General Call Enable bit
1= Enable interrupt when a general call address (0000h) is received in the SSPSR
0= General call address disabled
bit 6
ACKSTAT: Acknowledge Status bit
Unused in Slave mode.
bit 5-2
ADMSK5:ADMSK2: Slave Address Mask Select bits
1= Masking of corresponding bits of SSPADD enabled
0= Masking of corresponding bits of SSPADD disabled
bit 1
ADMSK1: Slave Address Least Significant bit(s) Mask Select bit
In 7-Bit Address mode:
1= Masking of SSPADD<1> only enabled
0= Masking of SSPADD<1> only disabled
In 10-Bit Address mode:
1= Masking of SSPADD<1:0> enabled
0= Masking of SSPADD<1:0> disabled
bit 0
SEN: Stretch Enable bit(1)
1= Clock stretching is enabled for both slave transmit and slave receive (stretch enabled)
0= Clock stretching is disabled
Note 1: If the I2C module is active, this bit may not be set (no spooling) and the SSPBUF may not be written (or
writes to the SSPBUF are disabled).
DS39774C-page 186
Preliminary
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The SCL clock input must have a minimum high and
low for proper operation. The high and low times of the
I2C specification, as well as the requirement of the
MSSP module, are shown in timing parameter 100 and
parameter 101.
16.4.2
OPERATION
The MSSP module functions are enabled by setting the
MSSP Enable bit, SSPEN (SSPCON1<5>).
The SSPCON1 register allows control of the I2C
operation. Four mode selection bits (SSPCON1<3:0>)
allow one of the following I2C modes to be selected:
16.4.3.1
Addressing
• I2C Master mode,
clock = (FOSC/4) x (SSPADD + 1)
• I2C Slave mode (7-bit address)
• I2C Slave mode (10-bit address)
• I2C Slave mode (7-bit address) with Start and
Stop bit interrupts enabled
• I2C Slave mode (10-bit address) with Start and
Stop bit interrupts enabled
• I2C Firmware Controlled Master mode,
slave is Idle
Selection of any I2C mode, with the SSPEN bit set,
forces the SCL and SDA pins to be open-drain,
provided these pins are programmed to inputs by
setting the appropriate TRISC or TRISD bits. To ensure
proper operation of the module, pull-up resistors must
be provided externally to the SCL and SDA pins.
Once the MSSP module has been enabled, it waits for a
Start condition to occur. Following the Start condition, the
8 bits are shifted into the SSPSR register. All incoming
bits are sampled with the rising edge of the clock (SCL)
line. The value of register SSPSR<7:1> is compared to
the value of the SSPADD register. The address is com-
pared on the falling edge of the eighth clock (SCL) pulse.
If the addresses match and the BF and SSPOV bits are
clear, the following events occur:
1. The SSPSR register value is loaded into the
SSPBUF register.
2. The Buffer Full bit, BF, is set.
3. An ACK pulse is generated.
4. The MSSP Interrupt Flag bit, SSPIF, is set (and
the interrupt is generated, if enabled) on the
falling edge of the ninth SCL pulse.
In 10-Bit Addressing mode, two address bytes need to
be received by the slave. The five Most Significant bits
(MSbs) of the first address byte specify if this is a 10-bit
address. Bit R/W (SSPSTAT<2>) must specify a write
so the slave device will receive the second address
byte. For a 10-bit address, the first byte would equal
‘11110 A9 A8 0’, where ‘A9’ and ‘A8’ are the two
MSbs of the address. The sequence of events for 10-bit
addressing is as follows, with steps 7 through 9 for the
slave-transmitter:
16.4.3
SLAVE MODE
In Slave mode, the SCL and SDA pins must be
configured as inputs (TRISC<4:3> set). The MSSP
module will override the input state with the output data
when required (slave-transmitter).
The I2C Slave mode hardware will always generate an
interrupt on an exact address match. In addition,
address masking will also allow the hardware to gener-
ate an interrupt for more than one address (up to 31 in
7-bit addressing and up to 63 in 10-bit addressing).
Through the mode select bits, the user can also choose
to interrupt on Start and Stop bits.
1. Receive first (high) byte of address (bits SSPIF,
BF and UA (SSPSTAT<1>) are set).
2. Update the SSPADD register with second (low)
byte of address (clears bit UA and releases the
SCL line).
When an address is matched, or the data transfer after
an address match is received, the hardware auto-
matically will generate the Acknowledge (ACK) pulse
and load the SSPBUF register with the received value
currently in the SSPSR register.
3. Read the SSPBUF register (clears bit BF) and
clear flag bit, SSPIF.
4. Receive second (low) byte of address (SSPIF,
BF and UA bits are set).
Any combination of the following conditions will cause
the MSSP module not to give this ACK pulse:
5. Update the SSPADD register with the first (high)
byte of address. If match releases SCL line, this
will clear UA bit.
• The Buffer Full bit, BF (SSPSTAT<0>), was set
before the transfer was received.
6. Read the SSPBUF register (clears bit BF) and
clear flag bit, SSPIF.
• The MSSP Overflow bit, SSPOV (SSPCON1<6>),
was set before the transfer was received.
7. Receive Repeated Start condition.
In this case, the SSPSR register value is not loaded
into the SSPBUF, but the SSPIF bit is set. The BF bit is
cleared by reading the SSPBUF register, while the
SSPOV bit is cleared through software.
8. Receive first (high) byte of address (SSPIF and
BF bits are set).
9. Read the SSPBUF register (clears BF bit) and
clear flag bit, SSPIF.
© 2007 Microchip Technology Inc.
Preliminary
DS39774C-page 187
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to issue an address Acknowledge, it is sufficient to match
only on addresses that do not have an active address
mask.
16.4.3.2
Address Masking
Masking an address bit causes that bit to become a
“don’t care”. When one address bit is masked, two
addresses will be Acknowledged and cause an
interrupt. It is possible to mask more than one address
bit at a time, which makes it possible to Acknowledge
up to 31 addresses in 7-Bit Addressing mode and up to
63 addresses in 10-Bit Addressing mode (see
Example 16-2).
The I2C Slave behaves the same way, whether
address masking is used or not. However, when
address masking is used, the I2C slave can
Acknowledge multiple addresses and cause interrupts.
When this occurs, it is necessary to determine which
address caused the interrupt by checking SSPBUF.
In 10-Bit Addressing mode, ADMSK<5:2> bits mask
the corresponding address bits in the SSPADD regis-
ter. In addition, ADMSK1 simultaneously masks the two
LSbs of the address (SSPADD<1:0>). For any ADMSK
bits that are active (ADMSK<n> = 1), the correspond-
ing address bit is ignored (SSPADD<n> = x). Also note
that although in 10-Bit Addressing mode, the upper
address bits reuse part of the SSPADD register bits, the
address mask bits do not interact with those bits. They
only affect the lower address bits.
Note 1: ADMSK1 masks the two Least Significant
bits of the address.
In 7-Bit Addressing mode, Address Mask bits,
ADMSK<5:1> (SSPCON2<5:1>), mask the correspond-
ing address bits in the SSPADD register. For any ADMSK
bits that are set (ADMSK<n> = 1), the corresponding
address bit is ignored (SSPADD<n> = x). For the module
2: The two Most Significant bits of the
address are not affected by address
masking.
EXAMPLE 16-2:
7-Bit Addressing:
ADDRESS MASKING EXAMPLES
SSPADD<7:1> = A0h (1010000) (SSPADD<0> is assumed to be ‘0’)
ADMSK<5:1> = 00111
Addresses Acknowledged: A0h, A2h, A4h, A6h, A8h, AAh, ACh, AEh
10-Bit Addressing:
SSPADD<7:0> = A0h (10100000) (the two MSbs of the address are ignored in this example, since they are
not affected by masking)
ADMSK<5:1> = 00111
Addresses Acknowledged: A0h, A1h, A2h, A3h, A4h, A5h, A6h, A7h, A8h, A9h, AAh, ABh, ACh, ADh, AEh, AFh
DS39774C-page 188
Preliminary
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16.4.3.3
Reception
16.4.3.4
Transmission
When the R/W bit of the address byte is clear and an
address match occurs, the R/W bit of the SSPSTAT
register is cleared. The received address is loaded into
the SSPBUF register and the SDA line is held low
(ACK).
When the R/W bit of the incoming address byte is set
and an address match occurs, the R/W bit of the
SSPSTAT register is set. The received address is
loaded into the SSPBUF register. The ACK pulse will
be sent on the ninth bit and pin RC3 is held low, regard-
less of SEN (see Section 16.4.4 “Clock Stretching”
for more details). By stretching the clock, the master
will be unable to assert another clock pulse until the
slave is done preparing the transmit data. The transmit
data must be loaded into the SSPBUF register which
also loads the SSPSR register. Then, pin RC3 should
be enabled by setting bit, CKP (SSPCON1<4>). The
eight data bits are shifted out on the falling edge of the
SCL input. This ensures that the SDA signal is valid
during the SCL high time (Figure 16-10).
When the address byte overflow condition exists, then
the no Acknowledge (ACK) pulse is given. An overflow
condition is defined as either bit, BF (SSPSTAT<0>), is
set or bit, SSPOV (SSPCON1<6>), is set.
An MSSP interrupt is generated for each data transfer
byte. The interrupt flag bit, SSPIF, must be cleared in
software. The SSPSTAT register is used to determine
the status of the byte.
If SEN is enabled (SSPCON2<0> = 1), SCK/SCL will
be held low (clock stretch) following each data
transfer. The clock must be released by setting bit,
CKP (SSPCON1<4>). See Section 16.4.4 “Clock
Stretching” for more details.
The ACK pulse from the master-receiver is latched on
the rising edge of the ninth SCL input pulse. If the SDA
line is high (not ACK), then the data transfer is
complete. In this case, when the ACK is latched by the
slave, the slave logic is reset (resets SSPSTAT
register) and the slave monitors for another occurrence
of the Start bit. If the SDA line was low (ACK), the next
transmit data must be loaded into the SSPBUF register.
Again, pin RC3 must be enabled by setting bit, CKP.
An MSSP interrupt is generated for each data transfer
byte. The SSPIF bit must be cleared in software and
the SSPSTAT register is used to determine the status
of the byte. The SSPIF bit is set on the falling edge of
the ninth clock pulse.
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Preliminary
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2
FIGURE 16-8:
I C™ SLAVE MODE TIMING WITH SEN = 0(RECEPTION, 7-BIT ADDRESSING)
DS39774C-page 190
Preliminary
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2
FIGURE 16-9:
I C™ SLAVE MODE TIMING WITH SEN = 0AND ADMSK<5:1> = 01011
(RECEPTION, 7-BIT ADDRESSING)
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Preliminary
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2
FIGURE 16-10:
I C™ SLAVE MODE TIMING (TRANSMISSION, 7-BIT ADDRESSING)
DS39774C-page 192
Preliminary
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FIGURE 16-11:
I2C™ SLAVE MODE TIMING WITH SEN = 0(RECEPTION, 10-BIT ADDRESSING)
© 2007 Microchip Technology Inc.
Preliminary
DS39774C-page 193
PIC18F85J11 FAMILY
FIGURE 16-12:
I2C™ SLAVE MODE TIMING WITH SEN = 0AND ADMSK<5:1> = 01001
(RECEPTION, 10-BIT ADDRESSING)
DS39774C-page 194
Preliminary
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2
FIGURE 16-13:
I C™ SLAVE MODE TIMING (TRANSMISSION, 10-BIT ADDRESSING)
© 2007 Microchip Technology Inc.
Preliminary
DS39774C-page 195
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16.4.4
CLOCK STRETCHING
16.4.4.3
Clock Stretching for 7-Bit Slave
Transmit Mode
Both 7-Bit and 10-Bit Slave modes implement
automatic clock stretching during a transmit sequence.
The 7-Bit Slave Transmit mode implements clock
stretching by clearing the CKP bit after the falling edge
of the ninth clock if the BF bit is clear. This occurs
regardless of the state of the SEN bit.
The SEN bit (SSPCON2<0>) allows clock stretching to
be enabled during receives. Setting SEN will cause
the SCL pin to be held low at the end of each data
receive sequence.
The user’s ISR must set the CKP bit before transmis-
sion is allowed to continue. By holding the SCL line
low, the user has time to service the ISR and load the
contents of the SSPBUF before the master device can
initiate another transmit sequence (see Figure 16-10).
16.4.4.1
Clock Stretching for 7-Bit Slave
Receive Mode (SEN = 1)
In 7-Bit Slave Receive mode when the BF bit is set, on
the falling edge of the ninth clock at the end of the
ACK sequence, the CKP bit in the SSPCON1 register
is automatically cleared, forcing the SCL output to be
held low. The CKP bit being cleared to ‘0’ will assert
the SCL line low. The CKP bit must be set in the user’s
ISR before reception is allowed to continue. By holding
the SCL line low, the user has time to service the ISR
and read the contents of the SSPBUF before the
master device can initiate another receive sequence.
This will prevent buffer overruns from occurring (see
Figure 16-15).
Note 1: If the user loads the contents of SSPBUF,
setting the BF bit before the falling edge of
the ninth clock, the CKP bit will not be
cleared and clock stretching will not occur.
2: The CKP bit can be set in software
regardless of the state of the BF bit.
16.4.4.4
Clock Stretching for 10-Bit Slave
Transmit Mode
In 10-Bit Slave Transmit mode, clock stretching is
controlled during the first two address sequences by
the state of the UA bit, just as it is in 10-Bit Slave
Receive mode. The first two addresses are followed
by a third address sequence which contains the
high-order bits of the 10-bit address and the R/W bit
set to ‘1’. After the third address sequence is
performed, the UA bit is not set, the module is now
configured in Transmit mode and clock stretching is
controlled by the BF flag as in 7-Bit Slave Transmit
mode (see Figure 16-13).
Note 1: If the user reads the contents of the
SSPBUF before the falling edge of the
ninth clock, thus clearing the BF bit, the
CKP bit will not be cleared and clock
stretching will not occur.
2: The CKP bit can be set in software
regardless of the state of the BF bit. The
user should be careful to clear the BF bit
in the ISR before the next receive
sequence in order to prevent an overflow
condition.
16.4.4.2
Clock Stretching for 10-Bit Slave
Receive Mode (SEN = 1)
In 10-Bit Slave Receive mode, during the address
sequence, clock stretching automatically takes place
but the CKP bit is not cleared. During this time, if the
UA bit is set after the ninth clock, clock stretching is
initiated. The UA bit is set after receiving the upper
byte of the 10-bit address and following the receive of
the second byte of the 10-bit address with the R/W bit
cleared to ‘0’. The release of the clock line occurs
upon updating SSPADD. Clock stretching will occur on
each data receive sequence as described in 7-bit
mode.
Note:
If the user polls the UA bit and clears it by
updating the SSPADD register before the
falling edge of the ninth clock occurs and if
the user hasn’t cleared the BF bit by read-
ing the SSPBUF register before that time,
then the CKP bit will still NOT be asserted
low. Clock stretching on the basis of the
state of the BF bit only occurs during a
data sequence, not an address sequence.
DS39774C-page 196
Preliminary
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already asserted the SCL line. The SCL output will
remain low until the CKP bit is set and all other
devices on the I2C bus have deasserted SCL. This
ensures that a write to the CKP bit will not violate the
minimum high time requirement for SCL (see
Figure 16-14).
16.4.4.5
Clock Synchronization and
the CKP bit
When the CKP bit is cleared, the SCL output is forced
to ‘0’. However, clearing the CKP bit will not assert the
SCL output low until the SCL output is already sam-
pled low. Therefore, the CKP bit will not assert the
SCL line until an external I2C master device has
FIGURE 16-14:
CLOCK SYNCHRONIZATION TIMING
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
SDA
SCL
DX
DX – 1
Master Device
Asserts Clock
CKP
Master Device
Deasserts Clock
WR
SSPCONx
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Preliminary
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2
FIGURE 16-15:
I C™ SLAVE MODE TIMING WITH SEN = 1(RECEPTION, 7-BIT ADDRESSING)
DS39774C-page 198
Preliminary
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FIGURE 16-16:
I2C™ SLAVE MODE TIMING WITH SEN = 1(RECEPTION, 10-BIT ADDRESSING)
© 2007 Microchip Technology Inc.
Preliminary
DS39774C-page 199
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If the general call address matches, the SSPSR is
transferred to the SSPBUF, the BF flag bit is set (eighth
bit) and on the falling edge of the ninth bit (ACK bit), the
SSPIF interrupt flag bit is set.
16.4.5
GENERAL CALL ADDRESS
SUPPORT
The addressing procedure for the I2C bus is such that
the first byte after the Start condition usually
determines which device will be the slave addressed by
the master. The exception is the general call address
which can address all devices. When this address is
used, all devices should, in theory, respond with an
Acknowledge.
When the interrupt is serviced, the source for the
interrupt can be checked by reading the contents of the
SSPBUF. The value can be used to determine if the
address was device specific or a general call address.
In 10-Bit Addressing mode, the SSPADD is required to
be updated for the second half of the address to match
and the UA bit is set (SSPSTAT<1>). If the general call
address is sampled when the GCEN bit is set, while the
slave is configured in 10-Bit Addressing mode, then the
second half of the address is not necessary, the UA bit
will not be set and the slave will begin receiving data
after the Acknowledge (Figure 16-17).
The general call address is one of eight addresses
reserved for specific purposes by the I2C protocol. It
consists of all ‘0’s with R/W = 0.
The general call address is recognized when the
General Call Enable bit, GCEN, is enabled
(SSPCON2<7> set). Following a Start bit detect, 8 bits
are shifted into the SSPSR and the address is
compared against the SSPADD. It is also compared to
the general call address and fixed in hardware.
FIGURE 16-17:
SLAVE MODE GENERAL CALL ADDRESS SEQUENCE
(7 OR 10-BIT ADDRESSING MODE)
Address is compared to General Call Address;
after ACK, set interrupt
Receiving Data
ACK
9
R/W = 0
General Call Address
ACK D7 D6
D5 D4 D3 D2 D1 D0
SDA
SCL
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
S
SSPIF
BF (SSPSTAT<0>)
Cleared in software
SSPBUF is read
SSPOV (SSPCON1<6>)
GCEN (SSPCON2<7>)
‘0’
‘1’
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Preliminary
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16.4.6
MASTER MODE
Note:
The MSSP module, when configured in
I2C Master mode, does not allow queueing
of events. For instance, the user is not
allowed to initiate a Start condition and
immediately write the SSPBUF register to
initiate transmission before the Start con-
dition is complete. In this case, the
SSPBUF will not be written to and the
WCOL bit will be set, indicating that a write
to the SSPBUF did not occur.
Master mode is enabled by setting and clearing the
appropriate SSPM bits in SSPCON1 and by setting the
SSPEN bit. In Master mode, the SCL and SDA lines
are manipulated by the MSSP hardware.
Master mode of operation is supported by interrupt
generation on the detection of the Start and Stop con-
ditions. The Stop (P) and Start (S) bits are cleared from
a Reset or when the MSSP module is disabled. Control
of the I2C bus may be taken when the P bit is set, or the
bus is Idle, with both the S and P bits clear.
The following events will cause the MSSP Interrupt
Flag bit, SSPIF, to be set (and MSSP interrupt, if
enabled):
In Firmware Controlled Master mode, user code
conducts all I2C bus operations based on Start and
Stop bit conditions.
• Start Condition
Once Master mode is enabled, the user has six
options.
• Stop Condition
• Data Transfer Byte Transmitted/Received
• Acknowledge Transmit
• Repeated Start
1. Assert a Start condition on SDA and SCL.
2. Assert a Repeated Start condition on SDA and
SCL.
3. Write to the SSPBUF register initiating
transmission of data/address.
4. Configure the I2C port to receive data.
5. Generate an Acknowledge condition at the end
of a received byte of data.
6. Generate a Stop condition on SDA and SCL.
2
FIGURE 16-18:
MSSP BLOCK DIAGRAM (I C™ MASTER MODE)
Internal
Data Bus
SSPM3:SSPM0
SSPADD<6:0>
Read
Write
SSPBUF
SSPSR
Baud
Rate
Generator
SDA
Shift
Clock
SDA In
MSb
LSb
Start bit, Stop bit,
Acknowledge
Generate
SCL
Start bit Detect
Stop bit Detect
Write Collision Detect
Clock Arbitration
State Counter for
End of XMIT/RCV
SCL In
Bus Collision
Set/Reset S, P, WCOL (SSPSTAT, SSPCON1);
Set SSPIF, BCLIF;
Reset ACKSTAT, PEN (SSPCON2)
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Preliminary
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I2C Master Mode Operation
A typical transmit sequence would go as follows:
16.4.6.1
1. The user generates a Start condition by setting
the Start Enable bit, SEN (SSPCON2<0>).
The master device generates all of the serial clock
pulses and the Start and Stop conditions. A transfer is
ended with a Stop condition or with a Repeated Start
condition. Since the Repeated Start condition is also
the beginning of the next serial transfer, the I2C bus will
not be released.
2. SSPIF is set. The MSSP module will wait the
required start time before any other operation
takes place.
3. The user loads the SSPBUF with the slave
address to transmit.
In Master Transmitter mode, serial data is output
through SDA, while SCL outputs the serial clock. The
first byte transmitted contains the slave address of the
receiving device (7 bits) and the Read/Write (R/W) bit.
In this case, the R/W bit will be logic ‘0’. Serial data is
transmitted 8 bits at a time. After each byte is transmit-
ted, an Acknowledge bit is received. Start and Stop
conditions are output to indicate the beginning and the
end of a serial transfer.
4. Address is shifted out the SDA pin until all 8 bits
are transmitted.
5. The MSSP module shifts in the ACK bit from the
slave device and writes its value into the
SSPCON2 register (SSPCON2<6>).
6. The MSSP module generates an interrupt at the
end of the ninth clock cycle by setting the SSPIF
bit.
In Master Receive mode, the first byte transmitted
contains the slave address of the transmitting device
(7 bits) and the R/W bit. In this case, the R/W bit will be
logic ‘1’. Thus, the first byte transmitted is a 7-bit slave
address followed by a ‘1’ to indicate the receive bit.
Serial data is received via SDA, while SCL outputs the
serial clock. Serial data is received 8 bits at a time. After
each byte is received, an Acknowledge bit is transmit-
ted. Start and Stop conditions indicate the beginning
and end of transmission.
7. The user loads the SSPBUF with eight bits of
data.
8. Data is shifted out the SDA pin until all 8 bits are
transmitted.
9. The MSSP module shifts in the ACK bit from the
slave device and writes its value into the
SSPCON2 register (SSPCON2<6>).
10. The MSSP module generates an interrupt at the
end of the ninth clock cycle by setting the SSPIF
bit.
The Baud Rate Generator used for the SPI mode
operation is used to set the SCL clock frequency for
either 100 kHz, 400 kHz or 1 MHz I2C operation. See
Section 16.4.7 “Baud Rate” for more detail.
11. The user generates a Stop condition by setting
the Stop Enable bit, PEN (SSPCON2<2>).
12. Interrupt is generated once the Stop condition is
complete.
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Preliminary
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Table 16-3 demonstrates clock rates based on
instruction cycles and the BRG value loaded into
SSPADD.
16.4.7
BAUD RATE
In I2C Master mode, the Baud Rate Generator (BRG)
reload value is placed in the lower 7 bits of the
SSPADD register (Figure 16-19). When a write occurs
to SSPBUF, the Baud Rate Generator will automatically
begin counting. The BRG counts down to 0 and stops
until another reload has taken place. The BRG count is
decremented twice per instruction cycle (TCY) on the
Q2 and Q4 clocks. In I2C Master mode, the BRG is
reloaded automatically.
16.4.7.1
Baud Rate Generation in
Power-Managed Modes
When the device is operating in one of the
power-managed modes, the clock source to the BRG
may change frequency, or even stop, depending on the
mode and clock source selected. Switching to a Run or
Idle mode from either the secondary clock or internal
oscillator is likely to change the clock rate to the BRG.
In Sleep mode, the BRG will not be clocked at all.
Once the given operation is complete (i.e., transmis-
sion of the last data bit is followed by ACK), the internal
clock will automatically stop counting and the SCL pin
will remain in its last state.
FIGURE 16-19:
BAUD RATE GENERATOR BLOCK DIAGRAM
SSPM3:SSPM0
SSPADD<6:0>
SSPM3:SSPM0
SCL
Reload
Control
Reload
BRG Down Counter
CLKO
FOSC/4
TABLE 16-3: I2C™ CLOCK RATE w/BRG
FSCL
FCY
FCY * 2
BRG Value
(2 Rollovers of BRG)
10 MHz
10 MHz
10 MHz
4 MHz
4 MHz
4 MHz
1 MHz
1 MHz
1 MHz
20 MHz
20 MHz
20 MHz
8 MHz
8 MHz
8 MHz
2 MHz
2 MHz
2 MHz
18h
1Fh
63h
09h
0Ch
27h
02h
09h
00h
400 kHz(1)
312.5 kHz
100 kHz
400 kHz(1)
308 kHz
100 kHz
333 kHz(1)
100 kHz
1 MHz(1)
Note 1: The I2C™ interface does not conform to the 400 kHz I2C specification (which applies to rates greater than
100 kHz) in all details, but may be used with care where higher rates are required by the application.
© 2007 Microchip Technology Inc.
Preliminary
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SCL pin is sampled high, the Baud Rate Generator is
reloaded with the contents of SSPADD<6:0> and
begins counting. This ensures that the SCL high time
will always be at least one BRG rollover count in the
event that the clock is held low by an external device
(Figure 16-20).
16.4.7.2
Clock Arbitration
Clock arbitration occurs when the master, during any
receive, transmit or Repeated Start/Stop condition,
deasserts the SCL pin (SCL allowed to float high).
When the SCL pin is allowed to float high, the Baud
Rate Generator (BRG) is suspended from counting
until the SCL pin is actually sampled high. When the
FIGURE 16-20:
BAUD RATE GENERATOR TIMING WITH CLOCK ARBITRATION
SDA
DX
DX – 1
SCL deasserted but slave holds
SCL low (clock arbitration)
SCL allowed to transition high
SCL
BRG decrements on
Q2 and Q4 cycles
BRG
Value
03h
02h
01h
00h (hold off)
03h
02h
SCL is sampled high, reload takes
place and BRG starts its count
BRG
Reload
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16.4.8
I2C MASTER MODE START
CONDITION TIMING
Note:
If, at the beginning of the Start condition,
the SDA and SCL pins are already sam-
pled low, or if during the Start condition, the
SCL line is sampled low before the SDA
line is driven low, a bus collision occurs.
The Bus Collision Interrupt Flag, BCLIF, is
set, the Start condition is aborted and the
I2C module is reset into its Idle state.
To initiate a Start condition, the user sets the Start
Enable bit, SEN (SSPCON2<0>). If the SDA and SCL
pins are sampled high, the Baud Rate Generator is
reloaded with the contents of SSPADD<6:0> and starts
its count. If SCL and SDA are both sampled high when
the Baud Rate Generator times out (TBRG), the SDA
pin is driven low. The action of the SDA being driven
low while SCL is high is the Start condition and causes
the S bit (SSPSTAT<3>) to be set. Following this, the
Baud Rate Generator is reloaded with the contents of
SSPADD<6:0> and resumes its count. When the Baud
Rate Generator times out (TBRG), the SEN bit
(SSPCON2<0>) will be automatically cleared by
hardware. The Baud Rate Generator is suspended,
leaving the SDA line held low and the Start condition is
complete.
16.4.8.1
WCOL Status Flag
If the user writes the SSPBUF when a Start sequence
is in progress, the WCOL is set and the contents of the
buffer are unchanged (the write doesn’t occur).
Note:
Because queueing of events is not
allowed, writing to the lower 5 bits of
SSPCON2 is disabled until the Start
condition is complete.
FIGURE 16-21:
FIRST START BIT TIMING
Set S bit (SSPSTAT<3>)
At completion of Start bit,
Write to SEN bit occurs here
SDA = 1,
SCL = 1
hardware clears SEN bit
and sets SSPIF bit
TBRG
TBRG
Write to SSPBUF occurs here
1st bit 2nd bit
SDA
TBRG
SCL
TBRG
S
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Preliminary
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16.4.9
I2C MASTER MODE REPEATED
START CONDITION TIMING
Note 1: If RSEN is programmed while any other
event is in progress, it will not take effect.
A Repeated Start condition occurs when the RSEN bit
(SSPCON2<1>) is programmed high and the I2C logic
module is in the Idle state. When the RSEN bit is set,
the SCL pin is asserted low. When the SCL pin is
sampled low, the Baud Rate Generator is loaded with
the contents of SSPADD<6:0> and begins counting.
The SDA pin is released (brought high) for one Baud
Rate Generator count (TBRG). When the Baud Rate
Generator times out, if SDA is sampled high, the SCL
pin will be deasserted (brought high). When SCL is
sampled high, the Baud Rate Generator is reloaded
with the contents of SSPADD<6:0> and begins
counting. SDA and SCL must be sampled high for one
TBRG. This action is then followed by assertion of the
SDA pin (SDA = 0) for one TBRG while SCL is high.
Following this, the RSEN bit (SSPCON2<1>) will be
automatically cleared and the Baud Rate Generator will
not be reloaded, leaving the SDA pin held low. As soon
as a Start condition is detected on the SDA and SCL
pins, the S bit (SSPSTAT<3>) will be set. The SSPIF bit
will not be set until the Baud Rate Generator has timed
out.
2: A bus collision during the Repeated Start
condition occurs if:
• SDA is sampled low when SCL goes
from low-to-high.
• SCL goes low before SDA is
asserted low. This may indicate that
another master is attempting to
transmit a data ‘1’.
Immediately following the SSPIF bit getting set, the user
may write the SSPBUF with the 7-bit address in 7-Bit
Addressing mode or the default first address in 10-Bit
Addressing mode. After the first eight bits are transmit-
ted and an ACK is received, the user may then transmit
an additional eight bits of address (10-Bit Addressing
mode) or eight bits of data (7-Bit Addressing mode).
16.4.9.1
WCOL Status Flag
If the user writes the SSPBUF when a Repeated Start
sequence is in progress, the WCOL is set and the
contents of the buffer are unchanged (the write doesn’t
occur).
Note:
Because queueing of events is not
allowed, writing of the lower 5 bits of
SSPCON2 is disabled until the Repeated
Start condition is complete.
FIGURE 16-22:
REPEATED START CONDITION WAVEFORM
S bit set by hardware
SDA = 1,
SCL = 1
At completion of Start bit,
hardware clears RSEN bit
and sets SSPIF
Write to SSPCON2 occurs here: SDA = 1,
SCL (no change)
TBRG
TBRG
TBRG
1st bit
SDA
RSEN bit set by hardware
on falling edge of ninth clock,
end of Xmit
Write to SSPBUF occurs here
TBRG
SCL
TBRG
Sr = Repeated Start
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Preliminary
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16.4.10 I2C MASTER MODE
TRANSMISSION
The user should verify that the WCOL is clear after
each write to SSPBUF to ensure the transfer is correct.
In all cases, WCOL must be cleared in software.
Transmission of a data byte, a 7-bit address or the
other half of a 10-bit address is accomplished by simply
writing a value to the SSPBUF register. This action will
set the Buffer Full bit, BF, and allow the Baud Rate
Generator to begin counting and start the next trans-
mission. Each bit of address/data will be shifted out
onto the SDA pin after the falling edge of SCL is
asserted (see data hold time specification
parameter 106). SCL is held low for one Baud Rate
Generator rollover count (TBRG). Data should be valid
before SCL is released high (see data setup time
specification parameter 107). When the SCL pin is
released high, it is held that way for TBRG. The data on
the SDA pin must remain stable for that duration and
some hold time after the next falling edge of SCL. After
the eighth bit is shifted out (the falling edge of the eighth
clock), the BF flag is cleared and the master releases
SDA. This allows the slave device being addressed to
respond with an ACK bit during the ninth bit time if an
address match occurred, or if data was received
properly. The status of ACK is written into the ACKDT
bit on the falling edge of the ninth clock. If the master
receives an Acknowledge, the Acknowledge Status bit,
ACKSTAT, is cleared; if not, the bit is set. After the ninth
clock, the SSPIF bit is set and the master clock (Baud
Rate Generator) is suspended until the next data byte
is loaded into the SSPBUF, leaving SCL low and SDA
unchanged (Figure 16-23).
16.4.10.3 ACKSTAT Status Flag
In Transmit mode, the ACKSTAT bit (SSPCON2<6>) is
cleared when the slave has sent an Acknowledge
(ACK = 0) and is set when the slave does not Acknowl-
edge (ACK = 1). A slave sends an Acknowledge when
it has recognized its address (including a general call),
or when the slave has properly received its data.
16.4.11 I2C MASTER MODE RECEPTION
Master mode reception is enabled by programming the
Receive Enable bit, RCEN (SSPCON2<3>).
Note:
The MSSP module must be in an Idle state
before the RCEN bit is set or the RCEN bit
will be disregarded.
The Baud Rate Generator begins counting, and on
each rollover, the state of the SCL pin changes
(high-to-low/low-to-high) and data is shifted into the
SSPSR. After the falling edge of the eighth clock, the
receive enable flag is automatically cleared, the con-
tents of the SSPSR are loaded into the SSPBUF, the
BF flag bit is set, the SSPIF flag bit is set and the Baud
Rate Generator is suspended from counting, holding
SCL low. The MSSP is now in Idle state awaiting the
next command. When the buffer is read by the CPU,
the BF flag bit is automatically cleared. The user can
then send an Acknowledge bit at the end of reception
by setting the Acknowledge Sequence Enable bit,
ACKEN (SSPCON2<4>).
After the write to the SSPBUF, each bit of the address
will be shifted out on the falling edge of SCL until all
seven address bits and the R/W bit are completed. On
the falling edge of the eighth clock, the master will
deassert the SDA pin, allowing the slave to respond
with an Acknowledge. On the falling edge of the ninth
clock, the master will sample the SDA pin to see if the
address was recognized by a slave. The status of the
ACK bit is loaded into the ACKSTAT bit
(SSPCON2<6>). Following the falling edge of the ninth
clock transmission of the address, the SSPIF bit is set,
the BF flag is cleared and the Baud Rate Generator is
turned off until another write to the SSPBUF takes
place, holding SCL low and allowing SDA to float.
16.4.11.1 BF Status Flag
In receive operation, the BF bit is set when an address
or data byte is loaded into SSPBUF from SSPSR. It is
cleared when the SSPBUF register is read.
16.4.11.2 SSPOV Status Flag
In receive operation, the SSPOV bit is set when 8 bits
are received into the SSPSR and the BF flag bit is
already set from a previous reception.
16.4.11.3 WCOL Status Flag
16.4.10.1 BF Status Flag
If the user writes the SSPBUF when a receive is
already in progress (i.e., SSPSR is still shifting in a data
byte), the WCOL bit is set and the contents of the buffer
are unchanged (the write doesn’t occur).
In Transmit mode, the BF bit (SSPSTAT<0>) is set
when the CPU writes to SSPBUF and is cleared when
all 8 bits are shifted out.
16.4.10.2 WCOL Status Flag
If the user writes to the SSPBUF when a transmit is
already in progress (i.e., SSPSR is still shifting out a
data byte), the WCOL is set and the contents of the
buffer are unchanged (the write doesn’t occur) after
2 TCY after the SSPBUF write. If SSPBUF is rewritten
within 2 TCY, the WCOL bit is set and SSPBUF is
updated. This may result in a corrupted transfer.
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Preliminary
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2
FIGURE 16-23:
I C™ MASTER MODE WAVEFORM (TRANSMISSION,
7 OR 10-BIT ADDRESSING)
DS39774C-page 208
Preliminary
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2
FIGURE 16-24:
I C™ MASTER MODE WAVEFORM (RECEPTION, 7-BIT ADDRESSING)
© 2007 Microchip Technology Inc.
Preliminary
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16.4.12 ACKNOWLEDGE SEQUENCE
TIMING
16.4.13 STOP CONDITION TIMING
A Stop bit is asserted on the SDA pin at the end of a
receive/transmit by setting the Stop Sequence Enable
bit, PEN (SSPCON2<2>). At the end of
An Acknowledge sequence is enabled by setting the
Acknowledge Sequence Enable bit, ACKEN
(SSPCON2<4>). When this bit is set, the SCL pin is
pulled low and the contents of the Acknowledge data bit
are presented on the SDA pin. If the user wishes to gen-
erate an Acknowledge, then the ACKDT bit should be
cleared. If not, the user should set the ACKDT bit before
starting an Acknowledge sequence. The Baud Rate
Generator then counts for one rollover period (TBRG)
and the SCL pin is deasserted (pulled high). When the
SCL pin is sampled high (clock arbitration), the Baud
Rate Generator counts for TBRG. The SCL pin is then
pulled low. Following this, the ACKEN bit is automatically
cleared, the Baud Rate Generator is turned off and the
MSSP module then goes into Idle mode (Figure 16-25).
a
receive/transmit, the SCL line is held low after the fall-
ing edge of the ninth clock. When the PEN bit is set, the
master will assert the SDA line low. When the SDA line
is sampled low, the Baud Rate Generator is reloaded
and counts down to ‘0’. When the Baud Rate Generator
times out, the SCL pin will be brought high and one
TBRG (Baud Rate Generator rollover count) later, the
SDA pin will be deasserted. When the SDA pin is
sampled high while SCL is high, the
(SSPSTAT<4>) is set. A TBRG later, the PEN bit is
cleared and the SSPIF bit is set (Figure 16-26).
P
bit
16.4.13.1 WCOL Status Flag
If the user writes the SSPBUF when a Stop sequence
is in progress, then the WCOL bit is set and the
contents of the buffer are unchanged (the write doesn’t
occur).
16.4.12.1 WCOL Status Flag
If the user writes the SSPBUF when an Acknowledge
sequence is in progress, then WCOL is set and the
contents of the buffer are unchanged (the write doesn’t
occur).
FIGURE 16-25:
ACKNOWLEDGE SEQUENCE WAVEFORM
Acknowledge sequence starts here,
write to SSPCON2,
ACKEN automatically cleared
TBRG
ACKEN = 1, ACKDT = 0
TBRG
SDA
D0
8
ACK
SCL
9
SSPIF
Cleared in
software
SSPIF set at
the end of receive
Cleared in
software
SSPIF set at the end
of Acknowledge sequence
Note: TBRG = one Baud Rate Generator period.
FIGURE 16-26:
STOP CONDITION RECEIVE OR TRANSMIT MODE
Write to SSPCON2,
SCL = 1for TBRG, followed by SDA = 1for TBRG
after SDA sampled high. P bit (SSPSTAT<4>) is set.
set PEN
Falling edge of
PEN bit (SSPCON2<2>) is cleared by
hardware and the SSPIF bit is set
9th clock
ACK
TBRG
SCL
SDA
P
TBRG
TBRG
TBRG
SCL brought high after TBRG
SDA asserted low before rising edge of clock
to setup Stop condition
Note: TBRG = one Baud Rate Generator period.
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Preliminary
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16.4.14 SLEEP OPERATION
16.4.17 MULTI -MASTER COMMUNICATION,
BUS COLLISION AND BUS
While in Sleep mode, the I2C module can receive
addresses or data and when an address match or
complete byte transfer occurs, wake the processor
from Sleep (if the MSSP interrupt is enabled).
ARBITRATION
Multi-Master mode support is achieved by bus arbitra-
tion. When the master outputs address/data bits onto
the SDA pin, arbitration takes place when the master
outputs a ‘1’ on SDA by letting SDA float high, and
another master asserts a ‘0’. When the SCL pin floats
high, data should be stable. If the expected data on
SDA is a ‘1’ and the data sampled on the SDA pin = 0,
then a bus collision has taken place. The master will set
the Bus Collision Interrupt Flag, BCLIF and reset the
I2C port to its Idle state (Figure 16-27).
16.4.15 EFFECTS OF A RESET
A Reset disables the MSSP module and terminates the
current transfer.
16.4.16 MULTI-MASTER MODE
In Multi-Master mode, the interrupt generation on the
detection of the Start and Stop conditions allows the
determination of when the bus is free. The Stop (P) and
Start (S) bits are cleared from a Reset or when the
MSSP module is disabled. Control of the I2C bus may
be taken when the P bit (SSPSTAT<4>) is set, or the
bus is Idle, with both the S and P bits clear. When the
bus is busy, enabling the MSSP interrupt will generate
the interrupt when the Stop condition occurs.
If a transmit was in progress when the bus collision
occurred, the transmission is halted, the BF flag is
cleared, the SDA and SCL lines are deasserted and the
SSPBUF can be written to. When the user services the
bus collision Interrupt Service Routine and if the I2C bus
is free, the user can resume communication by asserting
a Start condition.
In multi-master operation, the SDA line must be
monitored for arbitration to see if the signal level is the
expected output level. This check is performed in
hardware with the result placed in the BCLIF bit.
If a Start, Repeated Start, Stop or Acknowledge condition
was in progress when the bus collision occurred, the
condition is aborted, the SDA and SCL lines are
deasserted and the respective control bits in the
SSPCON2 register are cleared. When the user services
the bus collision Interrupt Service Routine and if the I2C
bus is free, the user can resume communication by
asserting a Start condition.
The states where arbitration can be lost are:
• Address Transfer
• Data Transfer
• A Start Condition
The master will continue to monitor the SDA and SCL
pins. If a Stop condition occurs, the SSPIF bit will be set.
• A Repeated Start Condition
• An Acknowledge Condition
A write to the SSPBUF will start the transmission of
data at the first data bit regardless of where the
transmitter left off when the bus collision occurred.
In Multi-Master mode, the interrupt generation on the
detection of Start and Stop conditions allows the deter-
mination of when the bus is free. Control of the I2C bus
can be taken when the P bit is set in the SSPSTAT
register, or the bus is Idle and the S and P bits are
cleared.
FIGURE 16-27:
BUS COLLISION TIMING FOR TRANSMIT AND ACKNOWLEDGE
Sample SDA. While SCL is high,
Data changes
while SCL = 0
SDA line pulled low
by another source
data doesn’t match what is driven
by the master.
Bus collision has occurred.
SDA released
by master
SDA
SCL
Set bus collision
interrupt (BCLIF)
BCLIF
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Preliminary
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If the SDA pin is sampled low during this count, the
BRG is reset and the SDA line is asserted early
(Figure 16-30). If, however, a ‘1’ is sampled on the SDA
pin, the SDA pin is asserted low at the end of the BRG
count. The Baud Rate Generator is then reloaded and
counts down to 0. If the SCL pin is sampled as ‘0’
during this time, a bus collision does not occur. At the
end of the BRG count, the SCL pin is asserted low.
16.4.17.1 Bus Collision During a Start
Condition
During a Start condition, a bus collision occurs if:
a) SDA or SCL are sampled low at the beginning of
the Start condition (Figure 16-28).
b) SCL is sampled low before SDA is asserted low
(Figure 16-29).
During a Start condition, both the SDA and the SCL
pins are monitored.
Note:
The reason that bus collision is not a factor
during a Start condition is that no two bus
masters can assert a Start condition at the
exact same time. Therefore, one master
will always assert SDA before the other.
This condition does not cause a bus colli-
sion because the two masters must be
allowed to arbitrate the first address
following the Start condition. If the address
is the same, arbitration must be allowed to
continue into the data portion, Repeated
Start or Stop conditions.
If the SDA pin is already low, or the SCL pin is already
low, then all of the following occur:
• the Start condition is aborted;
• the BCLIF flag is set; and
• the MSSP module is reset to its Idle state
(Figure 16-28).
The Start condition begins with the SDA and SCL pins
deasserted. When the SDA pin is sampled high, the
Baud Rate Generator is loaded from SSPADD<6:0>
and counts down to 0. If the SCL pin is sampled low
while SDA is high, a bus collision occurs, because it is
assumed that another master is attempting to drive a
data ‘1’ during the Start condition.
FIGURE 16-28:
BUS COLLISION DURING START CONDITION (SDA ONLY)
SDA goes low before the SEN bit is set.
Set BCLIF,
S bit and SSPIF set because
SDA = 0, SCL = 1.
SDA
SCL
SEN
Set SEN, enable Start
condition if SDA = 1, SCL = 1
SEN cleared automatically because of bus collision.
MSSP module reset into Idle state.
SDA sampled low before
Start condition. Set BCLIF.
S bit and SSPIF set because
SDA = 0, SCL = 1.
BCLIF
SSPIF and BCLIF are
cleared in software
S
SSPIF
SSPIF and BCLIF are
cleared in software
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Preliminary
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FIGURE 16-29:
BUS COLLISION DURING START CONDITION (SCL = 0)
SDA = 0, SCL = 1
TBRG
TBRG
SDA
Set SEN, enable Start
sequence if SDA = 1, SCL = 1
SCL
SEN
SCL = 0before SDA = 0,
bus collision occurs. Set BCLIF.
SCL = 0before BRG time-out,
bus collision occurs. Set BCLIF.
BCLIF
Interrupt cleared
in software
S
‘0’
‘0’
‘0’
SSPIF
‘0’
FIGURE 16-30:
BRG RESET DUE TO SDA ARBITRATION DURING START CONDITION
SDA = 0, SCL = 1
Set S
Set SSPIF
Less than TBRG
TBRG
SDA pulled low by other master.
Reset BRG and assert SDA.
SDA
SCL
SEN
S
SCL pulled low after BRG
time-out
Set SEN, enable Start
sequence if SDA = 1, SCL = 1
‘0’
BCLIF
S
SSPIF
Interrupts cleared
in software
SDA = 0, SCL = 1,
set SSPIF
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Preliminary
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If SDA is low, a bus collision has occurred (i.e., another
master is attempting to transmit a data ‘0’, see
Figure 16-31). If SDA is sampled high, the BRG is
reloaded and begins counting. If SDA goes from
high-to-low before the BRG times out, no bus collision
occurs because no two masters can assert SDA at
exactly the same time.
16.4.17.2 Bus Collision During a Repeated
Start Condition
During a Repeated Start condition, a bus collision
occurs if:
a) A low level is sampled on SDA when SCL goes
from low level to high level.
b) SCL goes low before SDA is asserted low,
indicating that another master is attempting to
transmit a data ‘1’.
If SCL goes from high-to-low before the BRG times out
and SDA has not already been asserted, a bus collision
occurs. In this case, another master is attempting to
transmit a data ‘1’ during the Repeated Start condition
(see Figure 16-32).
When the user deasserts SDA and the pin is allowed to
float high, the BRG is loaded with SSPADD<6:0> and
counts down to 0. The SCL pin is then deasserted and
when sampled high, the SDA pin is sampled.
If, at the end of the BRG time-out, both SCL and SDA
are still high, the SDA pin is driven low and the BRG is
reloaded and begins counting. At the end of the count,
regardless of the status of the SCL pin, the SCL pin is
driven low and the Repeated Start condition is complete.
FIGURE 16-31:
BUS COLLISION DURING A REPEATED START CONDITION (CASE 1)
SDA
SCL
Sample SDA when SCL goes high.
If SDA = 0, set BCLIF and release SDA and SCL.
RSEN
BCLIF
Cleared in software
‘0’
S
‘0’
SSPIF
FIGURE 16-32:
BUS COLLISION DURING REPEATED START CONDITION (CASE 2)
TBRG
TBRG
SDA
SCL
SCL goes low before SDA,
set BCLIF. Release SDA and SCL.
BCLIF
RSEN
Interrupt cleared
in software
‘0’
S
SSPIF
DS39774C-page 214
Preliminary
© 2007 Microchip Technology Inc.
PIC18F85J11 FAMILY
The Stop condition begins with SDA asserted low.
When SDA is sampled low, the SCL pin is allowed to
float. When the pin is sampled high (clock arbitration),
the Baud Rate Generator is loaded with SSPADD<6:0>
and counts down to 0. After the BRG times out, SDA is
sampled. If SDA is sampled low, a bus collision has
occurred. This is due to another master attempting to
drive a data ‘0’ (Figure 16-33). If the SCL pin is
sampled low before SDA is allowed to float high, a bus
collision occurs. This is another case of another master
attempting to drive a data ‘0’ (Figure 16-34).
16.4.17.3 Bus Collision During a Stop
Condition
Bus collision occurs during a Stop condition if:
a) After the SDA pin has been deasserted and
allowed to float high, SDA is sampled low after
the BRG has timed out.
b) After the SCL pin is deasserted, SCL is sampled
low before SDA goes high.
FIGURE 16-33:
BUS COLLISION DURING A STOP CONDITION (CASE 1)
SDA sampled
low after TBRG,
set BCLIF
TBRG
TBRG
TBRG
SDA
SCL
SDA asserted low
PEN
BCLIF
‘0’
‘0’
P
SSPIF
FIGURE 16-34:
BUS COLLISION DURING A STOP CONDITION (CASE 2)
TBRG
TBRG
TBRG
SDA
SCL goes low before SDA goes high,
set BCLIF
Assert SDA
SCL
PEN
BCLIF
‘0’
‘0’
P
SSPIF
© 2007 Microchip Technology Inc.
Preliminary
DS39774C-page 215
PIC18F85J11 FAMILY
TABLE 16-4: REGISTERS ASSOCIATED WITH I2C™ OPERATION
Reset
Values
on Page
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
INTCON
PIR1
GIE/GIEH PEIE/GIEL TMR0IE
INT0IE
TX1IF
TX1IE
TX1IP
—
RBIE
SSPIF
SSPIE
SSPIP
BCLIF
BCLIE
BCLIP
TRISC3
TMR0IF
—
INT0IF
TMR2IF
TMR2IE
TMR2IP
TMR3IF
TMR3IE
TMR3IP
TRISC1
RBIF
TMR1IF
TMR1IE
TMR1IP
—
51
53
53
53
53
53
53
54
52
52
52
52
PSPIF
PSPIE
ADIF
ADIE
RC1IF
RC1IE
RC1IP
—
PIE1
—
IPR1
PSPIP
ADIP
—
PIR2
OSCFIF
OSCFIE
OSCFIP
TRISC7
CMIF
CMIE
CMIP
TRISC6
LVDIF
LVDIE
LVDIP
TRISC2
PIE2
—
—
—
IPR2
—
—
—
TRISC
TRISC5
TRISC4
TRISC0
SSPBUF
MSSP Receive Buffer/Transmit Register
SSPADD MSSP Address Register (I2C™ Slave mode), MSSP Baud Rate Reload Register (I2C Master mode)
SSPCON1
SSPCON2
WCOL
GCEN
GCEN
SMP
SSPOV
SSPEN
CKP
SSPM3
SSPM2
SSPM1
SSPM0
SEN
SEN
BF
ACKSTAT ACKDT
ACKEN
RCEN
PEN
RSEN
(1)
(1)
(1)
(1)
(1)
ACKSTAT ADMSK5 ADMSK4 ADMSK3 ADMSK2 ADMSK1
SSPSTAT
CKE D/A R/W UA
P
S
52
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the MSSP module in I2C™ mode.
Note 1: Alternate bit definitions for use in I2C Slave mode operations only.
DS39774C-page 216
Preliminary
© 2007 Microchip Technology Inc.
PIC18F85J11 FAMILY
The pins of the EUSART are multiplexed with the
functions of PORTC (RC6/TX1/CK1 and RC7/RX1/DT1).
In order to configure these pins as a EUSART:
17.0 ENHANCED UNIVERSAL
SYNCHRONOUS
ASYNCHRONOUS RECEIVER
TRANSMITTER (EUSART)
• bit SPEN (RCSTA1<7>) must be set (= 1)
• bit TRISC<7> must be set (= 1)
PIC18F85J11 family devices have three serial I/O
modules: the MSSP module, discussed in the previous
chapter and two Universal Synchronous Asynchronous
Receiver Transmitter (USART) modules. (Generically,
the USART is also known as a Serial Communications
Interface or SCI.) The EUSART can be configured as a
full-duplex, asynchronous system that can communicate
with peripheral devices, such as CRT terminals and per-
sonal computers. It can also be configured as a
half-duplex, synchronous system that can communicate
with peripheral devices, such as A/D or D/A integrated
circuits, serial EEPROMs, etc.
• bit TRISC<6> must be set (= 1)
Note:
The EUSART control will automatically
reconfigure the pin from input to output as
needed.
The driver for the TX1 output pin can also be optionally
configured as an open-drain output. This feature allows
the voltage level on the pin to be pulled to a higher level
through an external pull-up resistor, and allows the
output to communicate with external circuits without the
need for additional level shifters.
The open-drain output option is controlled by the U1OD
bit (LATG<6>). Setting the bit configures the pin for
open-drain operation.
There are two distinct implementations of the USART
module in these devices: the Enhanced USART
(EUSART) discussed here and the Addressable
USART discussed in the next chapter. For this device
family, USART1 always refers to the EUSART, while
USART2 is always the AUSART.
17.1 Control Registers
The operation of the Enhanced USART module is
controlled through three registers:
The EUSART and AUSART modules implement the
same core features for serial communications; their
basic operation is essentially the same. The EUSART
module provides additional features, including Auto-
matic Baud Rate Detection and calibration, automatic
wake-up on Sync Break reception and 12-bit Break
character transmit. These features make it ideally
suited for use in Local Interconnect Network bus (LIN
bus) systems.
• Transmit Status and Control Register 1 (TXSTA1)
• Receive Status and Control Register 1 (RCSTA1)
• Baud Rate Control Register 1 (BAUDCON1)
The registers are described in Register 17-1,
Register 17-2 and Register 17-3.
The EUSART can be configured in the following
modes:
• Asynchronous (full-duplex) with:
- Auto-wake-up on character reception
- Auto-baud calibration
- 12-bit Break character transmission
• Synchronous – Master (half-duplex) with
selectable clock polarity
• Synchronous – Slave (half-duplex) with selectable
clock polarity
© 2007 Microchip Technology Inc.
Preliminary
DS39774C-page 217
PIC18F85J11 FAMILY
REGISTER 17-1: TXSTA1: EUSART TRANSMIT STATUS AND CONTROL REGISTER
R/W-0
CSRC
R/W-0
TX9
R/W-0
TXEN(1)
R/W-0
SYNC
R/W-0
R/W-0
BRGH
R-1
R/W-0
TX9D
SENDB
TRMT
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7
CSRC: Clock Source Select bit
Asynchronous mode:
Don’t care.
Synchronous mode:
1= Master mode (clock generated internally from BRG)
0= Slave mode (clock from external source)
bit 6
bit 5
bit 4
bit 3
TX9: 9-Bit Transmit Enable bit
1= Selects 9-bit transmission
0= Selects 8-bit transmission
TXEN: Transmit Enable bit(1)
1= Transmit enabled
0= Transmit disabled
SYNC: AUSART Mode Select bit
1= Synchronous mode
0= Asynchronous mode
SENDB: Send Break Character bit
Asynchronous mode:
1= Send Sync Break on next transmission (cleared by hardware upon completion)
0= Sync Break transmission completed
Synchronous mode:
Don’t care.
bit 2
BRGH: High Baud Rate Select bit
Asynchronous mode:
1= High speed
0= Low speed
Synchronous mode:
Unused in this mode.
bit 1
bit 0
TRMT: Transmit Shift Register Status bit
1= TSR empty
0= TSR full
TX9D: 9th Bit of Transmit Data
Can be address/data bit or a parity bit.
Note 1: SREN/CREN overrides TXEN in Sync mode.
DS39774C-page 218
Preliminary
© 2007 Microchip Technology Inc.
PIC18F85J11 FAMILY
REGISTER 17-2: RCSTA1: EUSART RECEIVE STATUS AND CONTROL REGISTER
R/W-0
SPEN
R/W-0
RX9
R/W-0
SREN
R/W-0
CREN
R/W-0
R-0
R-0
R-x
ADDEN
FERR
OERR
RX9D
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7
bit 6
bit 5
SPEN: Serial Port Enable bit
1= Serial port enabled (configures RX1/DT1 and TX1/CK1 pins as serial port pins)
0= Serial port disabled (held in Reset)
RX9: 9-Bit Receive Enable bit
1= Selects 9-bit reception
0= Selects 8-bit reception
SREN: Single Receive Enable bit
Asynchronous mode:
Don’t care.
Synchronous mode – Master:
1= Enables single receive
0= Disables single receive
This bit is cleared after reception is complete.
Synchronous mode – Slave:
Don’t care.
bit 4
CREN: Continuous Receive Enable bit
Asynchronous mode:
1= Enables receiver
0= Disables receiver
Synchronous mode:
1= Enables continuous receive until enable bit CREN is cleared (CREN overrides SREN)
0= Disables continuous receive
bit 3
ADDEN: Address Detect Enable bit
Asynchronous mode 9-bit (RX9 = 1):
1= Enables address detection, enables interrupt and loads the receive buffer when RSR<8> is set
0= Disables address detection, all bytes are received and ninth bit can be used as parity bit
Asynchronous mode 9-bit (RX9 = 0):
Don’t care.
bit 2
bit 1
bit 0
FERR: Framing Error bit
1= Framing error (can be updated by reading RCREG1 register and receiving next valid byte)
0= No framing error
OERR: Overrun Error bit
1= Overrun error (can be cleared by clearing bit CREN)
0= No overrun error
RX9D: 9th Bit of Received Data
This can be address/data bit or a parity bit and must be calculated by user firmware.
© 2007 Microchip Technology Inc.
Preliminary
DS39774C-page 219
PIC18F85J11 FAMILY
REGISTER 17-3: BAUDCON1: BAUD RATE CONTROL REGISTER 1
R/W-0
R-1
U-0
—
R/W-0
SCKP
R/W-0
U-0
—
R/W-0
WUE
R/W-0
ABDOVF
RCMT
BRG16
ABDEN
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7
bit 6
ABDOVF: Auto-Baud Acquisition Rollover Status bit
1= A BRG rollover has occurred during Auto-Baud Rate Detect mode (must be cleared in software)
0= No BRG rollover has occurred
RCMT: Receive Operation Idle Status bit
1= Receive operation is Idle
0= Receive operation is active
bit 5
bit 4
Unimplemented: Read as ‘0’
SCKP: Synchronous Clock Polarity Select bit
Asynchronous mode:
Unused in this mode.
Synchronous mode:
1= Idle state for clock (CK1) is a high level
0= Idle state for clock (CK1) is a low level
bit 3
BRG16: 16-Bit Baud Rate Register Enable bit
1= 16-bit Baud Rate Generator – SPBRGH1 and SPBRG1
0= 8-bit Baud Rate Generator – SPBRG1 only (Compatible mode), SPBRGH1 value ignored
bit 2
bit 1
Unimplemented: Read as ‘0’
WUE: Wake-up Enable bit
Asynchronous mode:
1= EUSART will continue to sample the RX1 pin – interrupt generated on falling edge; bit cleared in
hardware on following rising edge
0= RX1 pin not monitored or rising edge detected
Synchronous mode:
Unused in this mode.
bit 0
ABDEN: Auto-Baud Detect Enable bit
Asynchronous mode:
1= Enable baud rate measurement on the next character. Requires reception of a Sync field (55h);
cleared in hardware upon completion.
0= Baud rate measurement disabled or completed
Synchronous mode:
Unused in this mode.
DS39774C-page 220
Preliminary
© 2007 Microchip Technology Inc.
PIC18F85J11 FAMILY
Asynchronous modes are shown in Table 17-2. It may
be advantageous to use the high baud rate (BRGH = 1)
or the 16-bit BRG to reduce the baud rate error, or
achieve a slow baud rate for a fast oscillator frequency.
17.2 EUSART Baud Rate Generator
(BRG)
The BRG is a dedicated, 8-bit or 16-bit generator that
supports both the Asynchronous and Synchronous
modes of the EUSART. By default, the BRG operates
in 8-bit mode; setting the BRG16 bit (BAUDCON1<3>)
selects 16-bit mode.
Writing a new value to the SPBRGH1:SPBRG1 regis-
ters causes the BRG timer to be reset (or cleared). This
ensures the BRG does not wait for a timer overflow
before outputting the new baud rate.
The SPBRGH1:SPBRG1 register pair controls the
period of a free-running timer. In Asynchronous mode,
BRGH (TXSTA1<2>) and BRG16 (BAUDCON1<3>) bits
also control the baud rate. In Synchronous mode, BRGH
is ignored. Table 17-1 shows the formula for computa-
tion of the baud rate for different EUSART modes that
only apply in Master mode (internally generated clock).
17.2.1
OPERATION IN POWER-MANAGED
MODES
The device clock is used to generate the desired baud
rate. When one of the power-managed modes is
entered, the new clock source may be operating at a
different frequency. This may require an adjustment to
the value in the SPBRG1 register pair.
Given the desired baud rate and FOSC, the nearest
integer value for the SPBRGH1:SPBRG1 registers can
be calculated using the formulas in Table 17-1. From
this, the error in baud rate can be determined. An
example calculation is shown in Example 17-1. Typical
baud rates and error values for the various
17.2.2
SAMPLING
The data on the RX1 pin is sampled three times by a
majority detect circuit to determine if a high or low level
is present at the RX1 pin.
TABLE 17-1: BAUD RATE FORMULAS
Configuration Bits
BRG/EUSART Mode
Baud Rate Formula
FOSC/[64 (n + 1)]
FOSC/[16 (n + 1)]
SYNC
BRG16
BRGH
0
0
0
0
1
1
0
0
1
1
0
1
0
1
0
1
x
x
8-Bit/Asynchronous
8-Bit/Asynchronous
16-Bit/Asynchronous
16-Bit/Asynchronous
8-Bit/Synchronous
16-Bit/Synchronous
FOSC/[4 (n + 1)]
Legend: x= Don’t care, n = Value of SPBRGH1:SPBRG1 register pair
EXAMPLE 17-1: CALCULATING BAUD RATE ERROR
For a device with FOSC of 16 MHz, desired baud rate of 9600, Asynchronous mode, 8-bit BRG:
Desired Baud Rate = FOSC/(64 ([SPBRGH1:SPBRG1] + 1))
Solving for SPBRGH1:SPBRG1:
= ((FOSC/Desired Baud Rate)/64) – 1
X
= ((16000000/9600)/64) – 1
= [25.042] = 25
Calculated Baud Rate = 16000000/(64 (25 + 1))
= 9615
Error
= (Calculated Baud Rate – Desired Baud Rate)/Desired Baud Rate
= (9615 – 9600)/9600 = 0.16%
TABLE 17-2: REGISTERS ASSOCIATED WITH THE BAUD RATE GENERATOR
Reset Values
on Page
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
TXSTA1
RCSTA1
CSRC
SPEN
TX9
RX9
TXEN
SREN
—
SYNC
CREN
SCKP
SENDB
ADDEN
BRG16
BRGH
FERR
—
TRMT
OERR
WUE
TX9D
RX9D
53
53
54
54
53
BAUDCON1 ABDOVF RCMT
ABDEN
SPBRGH1
SPBRG1
EUSART Baud Rate Generator Register High Byte
EUSART Baud Rate Generator Register Low Byte
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the BRG.
© 2007 Microchip Technology Inc.
Preliminary
DS39774C-page 221
PIC18F85J11 FAMILY
TABLE 17-3: BAUD RATES FOR ASYNCHRONOUS MODES
SYNC = 0, BRGH = 0, BRG16 = 0
BAUD
RATE
(K)
FOSC = 40.000 MHz
FOSC = 20.000 MHz
FOSC = 10.000 MHz
FOSC = 8.000 MHz
Actual
Rate
(K)
SPBRG Actual
Value
SPBRG Actual
Value
(decimal)
SPBRG Actual
Value
(decimal)
SPBRG
Value
(decimal)
%
%
Error
%
Error
%
Error
Rate
(K)
Rate
(K)
Rate
(K)
Error
(decimal)
0.3
1.2
—
—
—
—
—
—
—
255
129
31
15
4
—
—
—
129
64
15
7
—
1.201
2.403
9.615
—
—
-0.16
-0.16
-0.16
—
—
103
51
12
—
—
—
1.221
1.73
0.16
1.73
1.73
8.51
-9.58
1.202
2.404
9.766
19.531
52.083
78.125
0.16
0.16
1.73
1.73
-9.58
-32.18
2.4
2.441
9.615
19.531
56.818
125.000
1.73
0.16
1.73
-1.36
8.51
255
64
31
10
4
2.404
9.6
9.766
19.2
57.6
115.2
19.531
62.500
104.167
2
—
—
—
2
1
—
—
—
SYNC = 0, BRGH = 0, BRG16 = 0
BAUD
RATE
(K)
FOSC = 4.000 MHz
FOSC = 2.000 MHz
FOSC = 1.000 MHz
Actual
Rate
(K)
SPBRG Actual
Value
SPBRG Actual
Value
(decimal)
SPBRG
Value
(decimal)
%
%
Error
%
Error
Rate
(K)
Rate
(K)
Error
(decimal)
0.3
1.2
0.300
1.202
0.16
0.16
207
51
25
6
0.300
1.201
2.403
—
-0.16
-0.16
-0.16
—
103
25
12
—
0.300
1.201
—
-0.16
-0.16
—
51
12
—
—
—
—
—
2.4
2.404
0.16
9.6
8.929
-6.99
8.51
—
—
19.2
57.6
115.2
20.833
62.500
62.500
2
—
—
—
—
—
8.51
0
—
—
—
—
—
-45.75
0
—
—
—
—
—
SYNC = 0, BRGH = 1, BRG16 = 0
BAUD
RATE
(K)
FOSC = 40.000 MHz
FOSC = 20.000 MHz
FOSC = 10.000 MHz
FOSC = 8.000 MHz
Actual
Rate
(K)
SPBRG Actual
Value
(decimal)
SPBRG Actual
Value
(decimal)
SPBRG Actual
Value
(decimal)
SPBRG
Value
%
Error
%
Error
%
Error
%
Error
Rate
(K)
Rate
(K)
Rate
(K)
(decimal)
0.3
1.2
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
2.4
—
—
—
—
—
—
2.441
9.615
19.531
56.818
125.000
1.73
0.16
1.73
-1.36
8.51
255
64
31
10
4
2.403
9.615
19.230
55.555
—
-0.16
-0.16
-0.16
3.55
—
207
51
25
8
9.6
9.766
19.231
58.140
113.636
1.73
0.16
0.94
-1.36
255
129
42
9.615
19.231
56.818
113.636
0.16
0.16
-1.36
-1.36
129
64
21
10
19.2
57.6
115.2
21
—
SYNC = 0, BRGH = 1, BRG16 = 0
BAUD
RATE
(K)
FOSC = 4.000 MHz
FOSC = 2.000 MHz
FOSC = 1.000 MHz
Actual
Rate
(K)
SPBRG Actual
Value
SPBRG Actual
Value
(decimal)
SPBRG
Value
(decimal)
%
%
Error
%
Error
Rate
(K)
Rate
(K)
Error
(decimal)
0.3
1.2
—
—
—
207
103
25
12
3
—
1.201
2.403
9.615
—
—
-0.16
-0.16
-0.16
—
—
103
51
12
—
0.300
1.201
2.403
—
-0.16
-0.16
-0.16
—
207
51
25
—
1.202
0.16
0.16
0.16
0.16
8.51
8.51
2.4
2.404
9.6
9.615
19.2
57.6
115.2
19.231
62.500
125.000
—
—
—
—
—
—
—
—
—
1
—
—
—
—
—
—
DS39774C-page 222
Preliminary
© 2007 Microchip Technology Inc.
PIC18F85J11 FAMILY
TABLE 17-3: BAUD RATES FOR ASYNCHRONOUS MODES (CONTINUED)
SYNC = 0, BRGH = 0, BRG16 = 1
BAUD
RATE
(K)
FOSC = 40.000 MHz
FOSC = 20.000 MHz FOSC = 10.000 MHz
FOSC = 8.000 MHz
Actual
Rate
(K)
SPBRG Actual
Value
SPBRG Actual
SPBRG Actual
Value
(decimal)
SPBRG
Value
(decimal)
%
%
Error
%
Error
%
Error
Rate
(K)
Value
Rate
(K)
Rate
(K)
Error
(decimal)
(decimal)
0.3
1.2
0.300
1.200
0.00
0.02
0.06
0.16
0.16
0.94
-1.36
8332
2082
1040
259
129
42
0.300
1.200
0.02
-0.03
-0.03
0.16
4165
1041
520
129
64
0.300
1.200
0.02
-0.03
0.16
0.16
1.73
-1.36
8.51
2082
520
259
64
0.300
1.201
2.403
9.615
19.230
55.555
—
-0.04
-0.16
-0.16
-0.16
-0.16
3.55
—
1665
415
207
51
2.4
2.402
2.399
2.404
9.6
9.615
9.615
9.615
19.2
57.6
115.2
19.231
58.140
113.636
19.231
56.818
113.636
0.16
19.531
56.818
125.000
31
25
-1.36
-1.36
21
10
8
21
10
4
—
SYNC = 0, BRGH = 0, BRG16 = 1
BAUD
RATE
(K)
FOSC = 4.000 MHz
FOSC = 2.000 MHz
FOSC = 1.000 MHz
Actual
Rate
(K)
SPBRG Actual
Value
SPBRG Actual
Value
(decimal)
SPBRG
Value
(decimal)
%
%
Error
%
Error
Rate
(K)
Rate
(K)
Error
(decimal)
0.3
1.2
0.300
1.202
0.04
0.16
0.16
0.16
0.16
8.51
8.51
832
207
103
25
12
3
0.300
1.201
2.403
9.615
—
-0.16
-0.16
-0.16
-0.16
—
415
103
51
12
—
0.300
1.201
2.403
—
-0.16
-0.16
-0.16
—
207
51
25
—
2.4
2.404
9.6
9.615
19.2
57.6
115.2
19.231
62.500
125.000
—
—
—
—
—
—
—
—
—
1
—
—
—
—
—
—
SYNC = 0, BRGH = 1, BRG16 = 1or SYNC = 1, BRG16 = 1
FOSC = 20.000 MHz FOSC = 10.000 MHz
BAUD
RATE
(K)
FOSC = 40.000 MHz
FOSC = 8.000 MHz
Actual
Rate
(K)
SPBRG Actual
SPBRG Actual
SPBRG Actual
Value
SPBRG
Value
(decimal)
%
Error
%
%
%
Error
Value
(decimal)
Rate
(K)
Value
Rate
(K)
Rate
(K)
Error
Error
(decimal)
(decimal)
0.3
1.2
0.300
1.200
0.00
0.00
0.02
0.06
-0.03
0.35
-0.22
33332
8332
4165
1040
520
0.300
1.200
0.00
0.02
0.02
-0.03
0.16
-0.22
0.94
16665
4165
2082
520
259
86
0.300
1.200
0.00
0.02
0.06
0.16
0.16
0.94
-1.36
8332
2082
1040
259
129
42
0.300
1.200
-0.01
-0.04
-0.04
-0.16
-0.16
0.79
6665
1665
832
207
103
34
2.4
2.400
2.400
2.402
2.400
9.6
9.606
9.596
9.615
9.615
19.2
57.6
115.2
19.193
57.803
114.943
19.231
57.471
116.279
19.231
58.140
113.636
19.230
57.142
117.647
172
86
42
21
-2.12
16
SYNC = 0, BRGH = 1, BRG16 = 1or SYNC = 1, BRG16 = 1
FOSC = 4.000 MHz FOSC = 2.000 MHz FOSC = 1.000 MHz
BAUD
RATE
(K)
Actual
Rate
(K)
SPBRG Actual
SPBRG Actual
SPBRG
Value
(decimal)
%
Error
%
Error
%
Error
Value
Rate
(K)
Value
Rate
(K)
(decimal)
(decimal)
0.3
1.2
0.300
1.200
0.01
0.04
0.16
0.16
0.16
2.12
-3.55
3332
832
415
103
51
0.300
1.201
2.403
9.615
19.230
55.555
—
-0.04
-0.16
-0.16
-0.16
-0.16
3.55
—
1665
415
207
51
0.300
1.201
2.403
9.615
19.230
—
-0.04
-0.16
-0.16
-0.16
-0.16
—
832
207
103
25
2.4
2.404
9.6
9.615
19.2
57.6
115.2
19.231
58.824
111.111
25
12
16
8
—
8
—
—
—
—
© 2007 Microchip Technology Inc.
Preliminary
DS39774C-page 223
PIC18F85J11 FAMILY
While the ABD sequence takes place, the EUSART
state machine is held in Idle. The RC1IF interrupt is set
once the fifth rising edge on RX1 is detected. The value
in the RCREG1 needs to be read to clear the RC1IF
interrupt. The contents of RCREG1 should be
discarded.
17.2.3
AUTO-BAUD RATE DETECT
The Enhanced USART module supports the automatic
detection and calibration of baud rate. This feature is
active only in Asynchronous mode and while the WUE
bit is clear.
The automatic baud rate measurement sequence
(Figure 17-1) begins whenever a Start bit is received
and the ABDEN bit is set. The calculation is
self-averaging.
Note 1: If the WUE bit is set with the ABDEN bit,
Auto-Baud Rate Detection will occur on
the byte following the Break character.
2: It is up to the user to determine that the
incoming character baud rate is within the
range of the selected BRG clock source.
Some combinations of oscillator frequency
and EUSART baud rates are not possible
due to bit error rates. Overall system
timing and communication baud rates
must be taken into consideration when
using the Auto-Baud Rate Detection
feature.
In the Auto-Baud Rate Detect (ABD) mode, the clock to
the BRG is reversed. Rather than the BRG clocking the
incoming RX1 signal, the RX1 signal is timing the BRG.
In ABD mode, the internal Baud Rate Generator is
used as a counter to time the bit period of the incoming
serial byte stream.
Once the ABDEN bit is set, the state machine will clear
the BRG and look for a Start bit. The Auto-Baud Rate
Detect must receive a byte with the value, 55h (ASCII
“U”, which is also the LIN bus Sync character), in order
to calculate the proper bit rate. The measurement is
taken over both a low and high bit time in order to min-
imize any effects caused by asymmetry of the incoming
signal. After a Start bit, the SPBRG1 begins counting
up, using the preselected clock source on the first rising
edge of RX1. After eight bits on the RX1 pin, or the fifth
rising edge, an accumulated value totalling the proper
BRG period is left in the SPBRGH1:SPBRG1 register
pair. Once the 5th edge is seen (this should correspond
to the Stop bit), the ABDEN bit is automatically cleared.
TABLE 17-4: BRG COUNTER CLOCK
RATES
BRG16 BRGH
BRG Counter Clock
0
0
1
0
1
FOSC/512
FOSC/128
FOSC/128
FOSC/32
0
1
1
Note:
During the ABD sequence, SPBRG1 and
SPBRGH1 are both used as a 16-bit
counter, independent of the BRG16 setting.
If a rollover of the BRG occurs (an overflow from FFFFh
to 0000h), the event is trapped by the ABDOVF status bit
(BAUDCON1<7>). It is set in hardware by BRG rollovers
and can be set or cleared by the user in software. ABD
mode remains active after rollover events and the
ABDEN bit remains set (Figure 17-2).
17.2.3.1
ABD and EUSART Transmission
Since the BRG clock is reversed during ABD acquisi-
tion, the EUSART transmitter cannot be used during
ABD. This means that whenever the ABDEN bit is set,
TXREG1 cannot be written to. Users should also
ensure that ABDEN does not become set during a
transmit sequence. Failing to do this may result in
unpredictable EUSART operation.
While calibrating the baud rate period, the BRG regis-
ters are clocked at 1/8th the preconfigured clock rate.
Note that the BRG clock will be configured by the
BRG16 and BRGH bits. Independent of the BRG16 bit
setting, both the SPBRG1 and SPBRGH1 will be used
as a 16-bit counter. This allows the user to verify that
no carry occurred for 8-bit modes by checking for 00h
in the SPBRGH1 register. Refer to Table 17-4 for
counter clock rates to the BRG.
DS39774C-page 224
Preliminary
© 2007 Microchip Technology Inc.
PIC18F85J11 FAMILY
FIGURE 17-1:
BRG Value
AUTOMATIC BAUD RATE CALCULATION
XXXXh
0000h
001Ch
Edge #5
Stop bit
Edge #2
bit 3
Edge #3
bit 5
bit 4
Edge #4
bit 7
Edge #1
bit 1
RX1 pin
Start
bit 2
bit 6
bit 0
BRG Clock
Auto-Cleared
Set by User
ABDEN bit
RC1IF bit
(Interrupt)
Read
RCREG1
XXXXh
XXXXh
1Ch
00h
SPBRG1
SPBRGH1
Note: The ABD sequence requires the EUSART module to be configured in Asynchronous mode and WUE = 0.
FIGURE 17-2:
BRG OVERFLOW SEQUENCE
BRG Clock
ABDEN bit
RX1 pin
Start
bit 0
ABDOVF bit
BRG Value
FFFFh
XXXXh
0000h
0000h
© 2007 Microchip Technology Inc.
Preliminary
DS39774C-page 225
PIC18F85J11 FAMILY
Once the TXREG1 register transfers the data to the TSR
register (occurs in one TCY), the TXREG1 register is
empty and the TX1IF flag bit (PIR1<4>) is set. This inter-
rupt can be enabled or disabled by setting or clearing the
interrupt enable bit, TX1IE (PIE1<4>). TX1IF will be set
regardless of the state of TX1IE; it cannot be cleared in
software. TX1IF is also not cleared immediately upon
loading TXREG1, but becomes valid in the second
instruction cycle following the load instruction. Polling
TX1IF immediately following a load of TXREG1 will
return invalid results.
17.3 EUSART Asynchronous Mode
The Asynchronous mode of operation is selected by
clearing the SYNC bit (TXSTA1<4>). In this mode, the
EUSART uses standard Non-Return-to-Zero (NRZ) for-
mat (one Start bit, eight or nine data bits and one Stop
bit). The most common data format is 8 bits. An
on-chip, dedicated 8-bit/16-bit Baud Rate Generator
can be used to derive standard baud rate frequencies
from the oscillator.
The EUSART transmits and receives the LSb first. The
EUSART’s transmitter and receiver are functionally
independent, but use the same data format and baud
rate. The Baud Rate Generator produces a clock, either
x16 or x64 of the bit shift rate, depending on the BRGH
and BRG16 bits (TXSTA1<2> and BAUDCON1<3>).
Parity is not supported by the hardware but can be
implemented in software and stored as the 9th data bit.
While TX1IF indicates the status of the TXREG1 regis-
ter, another bit, TRMT (TXSTA1<1>), shows the status
of the TSR register. TRMT is a read-only bit which is set
when the TSR register is empty. No interrupt logic is
tied to this bit so the user has to poll this bit in order to
determine if the TSR register is empty.
Note 1: The TSR register is not mapped in data
When operating in Asynchronous mode, the EUSART
module consists of the following important elements:
memory so it is not available to the user.
2: Flag bit, TX1IF, is set when enable bit,
• Baud Rate Generator
• Sampling Circuit
TXEN, is set.
To set up an Asynchronous Transmission:
• Asynchronous Transmitter
• Asynchronous Receiver
• Auto-Wake-up on Sync Break Character
• 12-Bit Break Character Transmit
• Auto-Baud Rate Detection
1. Initialize the SPBRGH1:SPBRG1 registers for
the appropriate baud rate. Set or clear the
BRGH and BRG16 bits, as required, to achieve
the desired baud rate.
2. Enable the asynchronous serial port by clearing
bit, SYNC, and setting bit, SPEN.
3. If interrupts are desired, set enable bit, TX1IE.
4. If 9-bit transmission is desired, set transmit bit,
TX9; can be used as address/data bit.
5. Enable the transmission by setting bit, TXEN,
which will also set bit, TX1IF.
6. If 9-bit transmission is selected, the ninth bit
should be loaded in bit, TX9D.
7. Load data to the TXREG1 register (starts
transmission).
8. If using interrupts, ensure that the GIE and PEIE bits
in the INTCON register (INTCON<7:6>) are set.
17.3.1
EUSART ASYNCHRONOUS
TRANSMITTER
The EUSART transmitter block diagram is shown in
Figure 17-3. The heart of the transmitter is the Transmit
(Serial) Shift register (TSR). The Shift register obtains
its data from the Read/Write Transmit Buffer register,
TXREG1. The TXREG1 register is loaded with data in
software. The TSR register is not loaded until the Stop
bit has been transmitted from the previous load. As
soon as the Stop bit is transmitted, the TSR is loaded
with new data from the TXREG1 register (if available).
FIGURE 17-3:
EUSART TRANSMIT BLOCK DIAGRAM
Data Bus
TX1IF
TXREG1 Register
8
TX1IE
MSb
(8)
LSb
0
Pin Buffer
and Control
•
• •
TSR Register
TX1 pin
Interrupt
Baud Rate CLK
SPBRG1
TXEN
SPEN
TRMT
BRG16
SPBRGH1
TX9
Baud Rate Generator
TX9D
DS39774C-page 226
Preliminary
© 2007 Microchip Technology Inc.
PIC18F85J11 FAMILY
FIGURE 17-4:
ASYNCHRONOUS TRANSMISSION
Write to TXREG1
Word 1
BRG Output
(Shift Clock)
TX1 (pin)
Start bit
bit 0
bit 1
Word 1
bit 7/8
Stop bit
TX1IF bit
(Transmit Buffer
Reg. Empty Flag)
1 TCY
Word 1
Transmit Shift Reg
TRMT bit
(Transmit Shift
Reg. Empty Flag)
FIGURE 17-5:
ASYNCHRONOUS TRANSMISSION (BACK-TO-BACK)
Write to TXREG1
Word 2
Start bit
Word 1
BRG Output
(Shift Clock)
TX1 (pin)
Start bit
Word 2
bit 0
bit 1
bit 7/8
bit 0
Stop bit
1 TCY
Word 1
TX1IF bit
(Interrupt Reg. Flag)
1 TCY
Word 1
Transmit Shift Reg.
Word 2
Transmit Shift Reg.
TRMT bit
(Transmit Shift
Reg. Empty Flag)
Note: This timing diagram shows two consecutive transmissions.
TABLE 17-5: REGISTERS ASSOCIATED WITH ASYNCHRONOUS TRANSMISSION
Reset
Values
on Page
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
INTCON
PIR1
GIE/GIEH PEIE/GIEL TMR0IE
INT0IE
TX1IF
TX1IE
TX1IP
CREN
RBIE
SSPIF
SSPIE
SSPIP
ADDEN
TMR0IF
—
INT0IF
RBIF
51
53
53
53
53
53
53
54
54
53
54
PSPIF
PSPIE
PSPIP
SPEN
ADIF
ADIE
ADIP
RX9
RC1IF
RC1IE
RC1IP
SREN
TMR2IF
TMR1IF
PIE1
—
TMR2IE TMR1IE
TMR2IP TMR1IP
IPR1
—
RCSTA1
TXREG1
TXSTA1
FERR
OERR
RX9D
EUSART Transmit Register
CSRC
TX9
TXEN
—
SYNC
SCKP
SENDB
BRG16
BRGH
—
TRMT
WUE
TX9D
BAUDCON1 ABDOVF
RCMT
ABDEN
SPBRGH1
SPBRG1
LATG
EUSART Baud Rate Generator Register High Byte
EUSART Baud Rate Generator Register Low Byte
U2OD
U1OD
—
LATG4
LATG3
LATG2
LATG1
LATG0
Legend: — = unimplemented locations read as ‘0’. Shaded cells are not used for asynchronous transmission.
© 2007 Microchip Technology Inc.
Preliminary
DS39774C-page 227
PIC18F85J11 FAMILY
17.3.2
EUSART ASYNCHRONOUS
RECEIVER
17.3.3
SETTING UP 9-BIT MODE WITH
ADDRESS DETECT
The receiver block diagram is shown in Figure 17-6.
The data is received on the RX1 pin and drives the data
recovery block. The data recovery block is actually a
high-speed shifter operating at x16 times the baud rate,
whereas the main receive serial shifter operates at the
bit rate or at FOSC. This mode would typically be used
in RS-232 systems.
This mode would typically be used in RS-485 systems.
To set up an Asynchronous Reception with Address
Detect Enable:
1. Initialize the SPBRGH1:SPBRG1 registers for
the appropriate baud rate. Set or clear the
BRGH and BRG16 bits, as required, to achieve
the desired baud rate.
To set up an Asynchronous Reception:
2. Enable the asynchronous serial port by clearing
the SYNC bit and setting the SPEN bit.
1. Initialize the SPBRGH1:SPBRG1 registers for
the appropriate baud rate. Set or clear the
BRGH and BRG16 bits, as required, to achieve
the desired baud rate.
3. If interrupts are required, set the RCEN bit and
select the desired priority level with the RC1IP
bit.
2. Enable the asynchronous serial port by clearing
bit, SYNC, and setting bit, SPEN.
4. Set the RX9 bit to enable 9-bit reception.
5. Set the ADDEN bit to enable address detect.
6. Enable reception by setting the CREN bit.
3. If interrupts are desired, set enable bit, RC1IE.
4. If 9-bit reception is desired, set bit, RX9.
5. Enable the reception by setting bit, CREN.
7. The RC1IF bit will be set when reception is
complete. The interrupt will be Acknowledged if
the RC1IE and GIE bits are set.
6. Flag bit, RC1IF, will be set when reception is
complete and an interrupt will be generated if
enable bit, RC1IE, was set.
8. Read the RCSTA1 register to determine if any
error occurred during reception, as well as read
bit 9 of data (if applicable).
7. Read the RCSTA1 register to get the 9th bit (if
enabled) and determine if any error occurred
during reception.
9. Read RCREG1 to determine if the device is
being addressed.
8. Read the 8-bit received data by reading the
RCREG1 register.
10. If any error occurred, clear the CREN bit.
11. If the device has been addressed, clear the
ADDEN bit to allow all received data into the
receive buffer and interrupt the CPU.
9. If any error occurred, clear the error by clearing
enable bit, CREN.
10. If using interrupts, ensure that the GIE and PEIE
bits in the INTCON register (INTCON<7:6>) are
set.
FIGURE 17-6:
EUSART RECEIVE BLOCK DIAGRAM
CREN
OERR
FERR
x64 Baud Rate CLK
÷ 64
or
RSR Register
• • •
MSb
LSb
BRG16
SPBRGH1 SPBRG1
÷ 16
Stop (8)
7
1
0
Start
or
÷ 4
Baud Rate Generator
RX9
Pin Buffer
and Control
Data
Recovery
RX1
RX9D
RCREG1 Register
FIFO
SPEN
8
Interrupt
RC1IF
RC1IE
Data Bus
DS39774C-page 228
Preliminary
© 2007 Microchip Technology Inc.
PIC18F85J11 FAMILY
FIGURE 17-7:
ASYNCHRONOUS RECEPTION
Start
bit
Start
Start
RX1 (pin)
bit 0 bit 1
bit 7/8 Stop
bit
bit
bit 0
bit 7/8 Stop
bit
bit
bit 7/8 Stop
bit
Rcv Shift Reg
Rcv Buffer Reg
Word 2
RCREG1
Word 1
RCREG1
RCREG1
Read Rcv
Buffer Reg
RC1IF
(Interrupt Flag)
OERR bit
CREN bit
Note: This timing diagram shows three words appearing on the RX1 input. The RCREG1 (EUSART Receive register) is read after the third
word causing the OERR (Overrun Error) bit to be set.
TABLE 17-6: REGISTERS ASSOCIATED WITH ASYNCHRONOUS RECEPTION
Reset
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Values
on Page
INTCON
PIR1
GIE/GIEH PEIE/GIEL TMR0IE
INT0IE
TX1IF
TX1IE
TX1IP
CREN
RBIE
SSPIF
SSPIE
SSPIP
ADDEN
TMR0IF
—
INT0IF
RBIF
51
53
53
53
53
53
53
54
54
53
PSPIF
PSPIE
PSPIP
SPEN
ADIF
ADIE
ADIP
RX9
RC1IF
RC1IE
RC1IP
SREN
TMR2IF TMR1IF
TMR2IE TMR1IE
TMR2IP TMR1IP
PIE1
—
IPR1
—
RCSTA1
RCREG1
TXSTA1
FERR
OERR
RX9D
EUSART Receive Register
CSRC
TX9
TXEN
—
SYNC
SCKP
SENDB
BRG16
BRGH
—
TRMT
WUE
TX9D
BAUDCON1 ABDOVF
RCMT
ABDEN
SPBRGH1
SPBRG1
EUSART Baud Rate Generator Register High Byte
EUSART Baud Rate Generator Register Low Byte
Legend: — = unimplemented locations read as ‘0’. Shaded cells are not used for asynchronous reception.
© 2007 Microchip Technology Inc.
Preliminary
DS39774C-page 229
PIC18F85J11 FAMILY
End-of-Character (EOC) and cause data or framing
errors. Therefore, to work properly, the initial character
in the transmission must be all ‘0’s. This can be 00h
(8 bytes) for standard RS-232 devices or 000h (12 bits)
for LIN bus.
17.3.4
AUTO-WAKE-UP ON SYNC BREAK
CHARACTER
During Sleep mode, all clocks to the EUSART are
suspended. Because of this, the Baud Rate Generator
is inactive and a proper byte reception cannot be per-
formed. The auto-wake-up feature allows the controller
to wake-up due to activity on the RX1/DT1 line, while
the EUSART is operating in Asynchronous mode.
Oscillator start-up time must also be considered,
especially in applications using oscillators with longer
start-up intervals (i.e., XT or HS mode). The Sync
Break (or Wake-up Signal) character must be of
sufficient length and be followed by a sufficient interval
to allow enough time for the selected oscillator to start
and provide proper initialization of the EUSART.
The auto-wake-up feature is enabled by setting the
WUE bit (BAUDCON<1>). Once set, the typical receive
sequence on RX1/DT1 is disabled and the EUSART
remains in an Idle state, monitoring for a wake-up event
independent of the CPU mode. A wake-up event
consists of a high-to-low transition on the RX1/DT1
line. (This coincides with the start of a Sync Break or a
Wake-up Signal character for the LIN protocol.)
17.3.4.2
Special Considerations Using
the WUE Bit
The timing of WUE and RC1IF events may cause some
confusion when it comes to determining the validity of
received data. As noted, setting the WUE bit places the
EUSART in an Idle mode. The wake-up event causes
a receive interrupt by setting the RC1IF bit. The WUE
bit is cleared after this when a rising edge is seen on
RX1/DT1. The interrupt condition is then cleared by
reading the RCREG1 register. Ordinarily, the data in
RCREG1 will be dummy data and should be discarded.
Following a wake-up event, the module generates an
RC1IF interrupt. The interrupt is generated synchro-
nously to the Q clocks in normal operating modes
(Figure 17-8), and asynchronously, if the device is in
Sleep mode (Figure 17-9). The interrupt condition is
cleared by reading the RCREG1 register.
The WUE bit is automatically cleared once a low-to-high
transition is observed on the RX1 line following the
wake-up event. At this point, the EUSART module is in
Idle mode and returns to normal operation. This signals
to the user that the Sync Break event is over.
The fact that the WUE bit has been cleared (or is still
set) and the RC1IF flag is set should not be used as an
indicator of the integrity of the data in RCREG1. Users
should consider implementing a parallel method in
firmware to verify received data integrity.
17.3.4.1
Special Considerations Using
Auto-Wake-up
To assure that no actual data is lost, check the RCMT
bit to verify that a receive operation is not in process. If
a receive operation is not occurring, the WUE bit may
then be set just prior to entering the Sleep mode.
Since auto-wake-up functions by sensing rising edge
transitions on RX1/DT1, information with any state
changes before the Stop bit may signal a false
FIGURE 17-8:
AUTO-WAKE-UP BIT (WUE) TIMINGS DURING NORMAL OPERATION
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
OSC1
Bit set by user
Auto-Cleared
WUE bit(1)
RX1/DT1 Line
RC1IF
Cleared due to user read of RCREG1
Note 1: The EUSART remains in Idle while the WUE bit is set.
FIGURE 17-9:
AUTO-WAKE-UP BIT (WUE) TIMINGS DURING SLEEP
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
Q1
Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
OSC1
Bit set by user
Auto-Cleared
WUE bit(2)
RX1/DT1 Line
RC1IF
Note 1
Cleared due to user read of RCREG1
Sleep Ends
SLEEPCommand Executed
Note 1: If the wake-up event requires long oscillator warm-up time, the auto-clear of the WUE bit can occur while the stposc signal is still active.
This sequence should not depend on the presence of Q clocks.
2: The EUSART remains in Idle while the WUE bit is set.
DS39774C-page 230
Preliminary
© 2007 Microchip Technology Inc.
PIC18F85J11 FAMILY
1. Configure the EUSART for the desired mode.
17.3.5
BREAK CHARACTER SEQUENCE
2. Set the TXEN and SENDB bits to set up the
Break character.
The Enhanced USART module has the capability of
sending the special Break character sequences that
are required by the LIN bus standard. The Break char-
acter transmit consists of a Start bit, followed by twelve
‘0’ bits and a Stop bit. The Frame Break character is
sent whenever the SENDB and TXEN bits
(TXSTA1<3> and TXSTA1<5>) are set while the Trans-
mit Shift register is loaded with data. Note that the value
of data written to TXREG1 will be ignored and all ‘0’s
will be transmitted.
3. Load the TXREG1 with a dummy character to
initiate transmission (the value is ignored).
4. Write ‘55h’ to TXREG1 to load the Sync
character into the transmit FIFO buffer.
5. After the Break has been sent, the SENDB bit is
reset by hardware. The Sync character now
transmits in the preconfigured mode.
When the TXREG1 becomes empty, as indicated by the
TX1IF, the next data byte can be written to TXREG1.
The SENDB bit is automatically reset by hardware after
the corresponding Stop bit is sent. This allows the user
to preload the transmit FIFO with the next transmit byte
following the Break character (typically, the Sync char-
acter in the LIN specification).
17.3.6
RECEIVING A BREAK CHARACTER
The Enhanced USART module can receive a Break
character in two ways.
Note that the data value written to the TXREG1 for the
Break character is ignored. The write simply serves the
purpose of initiating the proper sequence.
The first method forces configuration of the baud rate
at a frequency of 9/13 the typical speed. This allows for
the Stop bit transition to be at the correct sampling
location (13 bits for Break versus Start bit and 8 data
bits for typical data).
The TRMT bit indicates when the transmit operation is
active or Idle, just as it does during normal transmis-
sion. See Figure 17-10 for the timing of the Break
character sequence.
The second method uses the auto-wake-up feature
described in Section 17.3.4 “Auto-Wake-up on Sync
Break Character”. By enabling this feature, the
EUSART will sample the next two transitions on
RX1/DT1, cause an RC1IF interrupt and receive the
next data byte followed by another interrupt.
17.3.5.1
Break and Sync Transmit Sequence
The following sequence will send a message frame
header made up of a Break, followed by an Auto-Baud
Sync byte. This sequence is typical of a LIN bus
master.
Note that following a Break character, the user will
typically want to enable the Auto-Baud Rate Detect
feature. For both methods, the user can set the ABDEN
bit once the TX1IF interrupt is observed.
FIGURE 17-10:
SEND BREAK CHARACTER SEQUENCE
Write to TXREG1
Dummy Write
BRG Output
(Shift Clock)
TX1 (pin)
Start bit
bit 0
bit 1
Break
bit 11
Stop bit
TX1IF bit
(Transmit Buffer
Reg. Empty Flag)
TRMT bit
(Transmit Shift
Reg. Empty Flag)
SENDB sampled here
Auto-Cleared
SENDB
(Transmit Shift
Reg. Empty Flag)
© 2007 Microchip Technology Inc.
Preliminary
DS39774C-page 231
PIC18F85J11 FAMILY
Once the TXREG1 register transfers the data to the
TSR register (occurs in one TCYCLE), the TXREG1 is
empty and the TX1IF flag bit (PIR1<4>) is set. The
interrupt can be enabled or disabled by setting or clear-
ing the interrupt enable bit, TX1IE (PIE1<4>). TX1IF is
set regardless of the state of enable bit, TX1IE; it can-
not be cleared in software. It will reset only when new
data is loaded into the TXREG1 register.
17.4 EUSART Synchronous
Master Mode
The Synchronous Master mode is entered by setting
the CSRC bit (TXSTA1<7>). In this mode, the data is
transmitted in a half-duplex manner (i.e., transmission
and reception do not occur at the same time). When
transmitting data, the reception is inhibited and vice
versa. Synchronous mode is entered by setting bit,
SYNC (TXSTA1<4>). In addition, enable bit, SPEN
(RCSTA1<7>), is set in order to configure the TX1 and
RX1 pins to CK1 (clock) and DT1 (data) lines,
respectively.
While flag bit TX1IF indicates the status of the TXREG1
register, another bit, TRMT (TXSTA1<1>), shows the
status of the TSR register. TRMT is a read-only bit which
is set when the TSR is empty. No interrupt logic is tied to
this bit so the user has to poll this bit in order to deter-
mine if the TSR register is empty. The TSR is not
mapped in data memory so it is not available to the user.
The Master mode indicates that the processor trans-
mits the master clock on the CK1 line. Clock polarity is
selected with the SCKP bit (BAUDCON1<4>). Setting
SCKP sets the Idle state on CK1 as high, while clearing
the bit sets the Idle state as low. This option is provided
to support Microwire devices with this module.
To set up a Synchronous Master Transmission:
1. Initialize the SPBRGH1:SPBRG1 registers for
the appropriate baud rate. Set or clear the
BRG16 bit, as required, to achieve the desired
baud rate.
17.4.1
EUSART SYNCHRONOUS MASTER
TRANSMISSION
2. Enable the synchronous master serial port by
setting bits SYNC, SPEN and CSRC.
The EUSART transmitter block diagram is shown in
Figure 17-3. The heart of the transmitter is the Transmit
(Serial) Shift register (TSR). The Shift register obtains
its data from the Read/Write Transmit Buffer register,
TXREG1. The TXREG1 register is loaded with data in
software. The TSR register is not loaded until the last
bit has been transmitted from the previous load. As
soon as the last bit is transmitted, the TSR is loaded
with new data from the TXREG1 (if available).
3. If interrupts are desired, set enable bit, TX1IE.
4. If 9-bit transmission is desired, set bit, TX9.
5. Enable the transmission by setting bit, TXEN.
6. If 9-bit transmission is selected, the ninth bit
should be loaded in bit TX9D.
7. Start transmission by loading data to the
TXREG1 register.
8. If using interrupts, ensure that the GIE and PEIE
bits in the INTCON register (INTCON<7:6>) are
set.
FIGURE 17-11:
SYNCHRONOUS TRANSMISSION
Q1 Q2 Q3 Q4 Q1Q2 Q3 Q4 Q1Q2 Q3 Q4 Q1Q2 Q3 Q4 Q1Q2 Q3 Q4
Q3 Q4 Q1 Q2 Q3Q4 Q1Q2 Q3Q4 Q1Q2 Q3 Q4 Q1Q2Q3 Q4 Q1Q2 Q3 Q4 Q1 Q2 Q3 Q4
RC7/RX1/DT1
pin
bit 0
bit 1
bit 2
bit 7
bit 0
bit 1
bit 7
Word 2
Word 1
RC6/TX1/CK1 pin
(SCKP = 0)
RC6/TX1/CK1 pin
(SCKP = 1)
Write to
TXREG1 Reg
Write Word 1
Write Word 2
TX1IF bit
(Interrupt Flag)
TRMT bit
‘1’
‘1’
TXEN bit
Note: Sync Master mode, SPBRG1 = 0; continuous transmission of two 8-bit words.
DS39774C-page 232
Preliminary
© 2007 Microchip Technology Inc.
PIC18F85J11 FAMILY
FIGURE 17-12:
SYNCHRONOUS TRANSMISSION (THROUGH TXEN)
RC7/RX1/DT1 pin
bit 0
bit 2
bit 1
bit 6
bit 7
RC6/TX1/CK1 pin
Write to
TXREG1 Reg
TX1IF bit
TRMT bit
TXEN bit
TABLE 17-7: REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER TRANSMISSION
Reset
Values
on Page
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
INTCON
PIR1
GIE/GIEH PEIE/GIEL TMR0IE
INT0IE
TX1IF
TX1IE
TX1IP
CREN
RBIE
SSPIF
SSPIE
SSPIP
ADDEN
TMR0IF
—
INT0IF
RBIF
51
53
53
53
53
53
53
54
54
53
54
PSPIF
PSPIE
PSPIP
SPEN
ADIF
ADIE
ADIP
RX9
RC1IF
RC1IE
RC1IP
SREN
TMR2IF TMR1IF
TMR2IE TMR1IE
TMR2IP TMR1IP
PIE1
—
IPR1
—
RCSTA1
TXREG1
TXSTA1
FERR
OERR
RX9D
EUSART Transmit Register
CSRC
TX9
TXEN
—
SYNC
SCKP
SENDB
BRG16
BRGH
—
TRMT
WUE
TX9D
BAUDCON1 ABDOVF
RCMT
ABDEN
SPBRGH1 EUSART Baud Rate Generator Register High Byte
SPBRG1
LATG
EUSART Baud Rate Generator Register Low Byte
U2OD U1OD LATG4 LATG3
—
LATG2
LATG1
LATG0
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used for synchronous master transmission.
© 2007 Microchip Technology Inc.
Preliminary
DS39774C-page 233
PIC18F85J11 FAMILY
3. Ensure bits, CREN and SREN, are clear.
4. If interrupts are desired, set enable bit, RC1IE.
5. If 9-bit reception is desired, set bit, RX9.
17.4.2
EUSART SYNCHRONOUS
MASTER RECEPTION
Once Synchronous mode is selected, reception is
enabled by setting either the Single Receive Enable bit,
SREN (RCSTA1<5>), or the Continuous Receive
Enable bit, CREN (RCSTA1<4>). Data is sampled on
the RX1 pin on the falling edge of the clock.
6. If a single reception is required, set bit, SREN.
For continuous reception, set bit, CREN.
7. Interrupt flag bit, RC1IF, will be set when
reception is complete and an interrupt will be
generated if the enable bit, RC1IE, was set.
If enable bit, SREN, is set, only a single word is
received. If enable bit, CREN, is set, the reception is
continuous until CREN is cleared. If both bits are set,
then CREN takes precedence.
8. Read the RCSTA1 register to get the 9th bit (if
enabled) and determine if any error occurred
during reception.
9. Read the 8-bit received data by reading the
RCREG1 register.
To set up a Synchronous Master Reception:
1. Initialize the SPBRGH1:SPBRG1 registers for the
appropriate baud rate. Set or clear the BRG16 bit,
as required, to achieve the desired baud rate.
10. If any error occurred, clear the error by clearing
bit, CREN.
11. If using interrupts, ensure that the GIE and PEIE
bits in the INTCON register (INTCON<7:6>) are
set.
2. Enable the synchronous master serial port by
setting bits, SYNC, SPEN and CSRC.
FIGURE 17-13:
SYNCHRONOUS RECEPTION (MASTER MODE, SREN)
Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4Q1 Q2 Q3 Q4 Q1Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
RC7/RX1/DT1
pin
bit 0
bit 1
bit 2
bit 3
bit 4
bit 5
bit 6
bit 7
RC6/TX1/CK1 pin
(SCKP = 0)
RC6/TX1/CK1 pin
(SCKP = 1)
Write to
SREN bit
SREN bit
CREN bit
‘0’
‘0’
RC1IF bit
(Interrupt)
Read
RCREG1
Note: Timing diagram demonstrates Sync Master mode with bit SREN = 1and bit BRGH = 0.
TABLE 17-8: REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER RECEPTION
Reset
Values
on Page
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
INTCON
PIR1
GIE/GIEH PEIE/GIEL TMR0IE
INT0IE
TX1IF
TX1IE
TX1IP
CREN
RBIE
SSPIF
SSPIE
SSPIP
ADDEN
TMR0IF
—
INT0IF
RBIF
51
53
53
53
53
53
53
54
54
53
PSPIF
PSPIE
PSPIP
SPEN
ADIF
ADIE
ADIP
RX9
RC1IF
RC1IE
RC1IP
SREN
TMR2IF TMR1IF
TMR2IE TMR1IE
TMR2IP TMR1IP
PIE1
—
IPR1
—
RCSTA1
RCREG1
TXSTA1
FERR
OERR
RX9D
EUSART Receive Register
CSRC
TX9
TXEN
—
SYNC
SCKP
SENDB
BRG16
BRGH
—
TRMT
WUE
TX9D
BAUDCON1 ABDOVF
RCMT
ABDEN
SPBRGH1 EUSART Baud Rate Generator Register High Byte
SPBRG1 EUSART Baud Rate Generator Register Low Byte
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used for synchronous master reception.
DS39774C-page 234
Preliminary
© 2007 Microchip Technology Inc.
PIC18F85J11 FAMILY
To set up a Synchronous Slave Transmission:
17.5 EUSART Synchronous Slave Mode
1. Enable the synchronous slave serial port by
setting bits, SYNC and SPEN, and clearing bit,
CSRC.
Synchronous Slave mode is entered by clearing bit,
CSRC (TXSTA<7>). This mode differs from the
Synchronous Master mode in that the shift clock is sup-
plied externally at the CK1 pin (instead of being supplied
internally in Master mode). This allows the device to
transfer or receive data while in any low-power mode.
2. Clear bits, CREN and SREN.
3. If interrupts are desired, set enable bit, TX1IE.
4. If 9-bit transmission is desired, set bit, TX9.
5. Enable the transmission by setting enable bit,
TXEN.
17.5.1
EUSART SYNCHRONOUS SLAVE
TRANSMIT
6. If 9-bit transmission is selected, the ninth bit
should be loaded in bit TX9D.
The operation of the Synchronous Master and Slave
modes are identical except in the case of the Sleep
mode.
7. Start transmission by loading data to the
TXREG1 register.
If two words are written to the TXREG1 and then the
SLEEPinstruction is executed, the following will occur:
8. If using interrupts, ensure that the GIE and PEIE
bits in the INTCON register (INTCON<7:6>) are
set.
a) The first word will immediately transfer to the
TSR register and transmit.
b) The second word will remain in the TXREG1
register.
c) Flag bit, TX1IF, will not be set.
d) When the first word has been shifted out of TSR,
the TXREG1 register will transfer the second
word to the TSR and flag bit, TX1IF, will now be
set.
e) If enable bit, TX1IE, is set, the interrupt will wake
the chip from Sleep. If the global interrupt is
enabled, the program will branch to the interrupt
vector.
TABLE 17-9: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE TRANSMISSION
Reset
Values
on Page
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
INTCON
PIR1
GIE/GIEH PEIE/GIEL TMR0IE
INT0IE
TX1IF
TX1IE
TX1IP
CREN
RBIE
SSPIF
SSPIE
SSPIP
ADDEN
TMR0IF
—
INT0IF
RBIF
51
53
53
53
53
53
53
54
54
53
54
PSPIF
PSPIE
PSPIP
SPEN
ADIF
ADIE
ADIP
RX9
RC1IF
RC1IE
RC1IP
SREN
TMR2IF TMR1IF
TMR2IE TMR1IE
TMR2IP TMR1IP
PIE1
—
IPR1
—
RCSTA1
TXREG1
TXSTA1
FERR
OERR
RX9D
EUSART Transmit Register
CSRC
TX9
TXEN
—
SYNC
SCKP
SENDB
BRG16
BRGH
—
TRMT
WUE
TX9D
BAUDCON1 ABDOVF
RCMT
ABDEN
SPBRGH1 EUSART Baud Rate Generator Register High Byte
SPBRG1
LATG
EUSART Baud Rate Generator Register Low Byte
U2OD U1OD LATG4 LATG3
—
LATG2
LATG1
LATG0
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used for synchronous slave transmission.
© 2007 Microchip Technology Inc.
Preliminary
DS39774C-page 235
PIC18F85J11 FAMILY
To set up a Synchronous Slave Reception:
17.5.2
EUSART SYNCHRONOUS SLAVE
RECEPTION
1. Enable the synchronous master serial port by
setting bits, SYNC and SPEN, and clearing bit,
CSRC.
The operation of the Synchronous Master and Slave
modes is identical except in the case of Sleep or any
Idle mode, and bit SREN, which is a “don’t care” in
Slave mode.
2. If interrupts are desired, set enable bit, RC1IE.
3. If 9-bit reception is desired, set bit, RX9.
4. To enable reception, set enable bit, CREN.
If receive is enabled by setting the CREN bit prior to
entering Sleep or any Idle mode, then a word may be
received while in this low-power mode. Once the word
is received, the RSR register will transfer the data to the
RCREG1 register. If the RC1IE enable bit is set, the
interrupt generated will wake the chip from the
low-power mode. If the global interrupt is enabled, the
program will branch to the interrupt vector.
5. Flag bit, RC1IF, will be set when reception is
complete. An interrupt will be generated if
enable bit, RC1IE, was set.
6. Read the RCSTA1 register to get the 9th bit (if
enabled) and determine if any error occurred
during reception.
7. Read the 8-bit received data by reading the
RCREG1 register.
8. If any error occurred, clear the error by clearing
bit, CREN.
9. If using interrupts, ensure that the GIE and PEIE
bits in the INTCON register (INTCON<7:6>) are
set.
TABLE 17-10: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE RECEPTION
Reset
Values
on Page
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
INTCON
PIR1
GIE/GIEH PEIE/GIEL TMR0IE
INT0IE
TX1IF
TX1IE
TX1IP
CREN
RBIE
SSPIF
SSPIE
SSPIP
ADDEN
TMR0IF
—
INT0IF
RBIF
51
53
53
53
53
53
53
54
54
53
PSPIF
PSPIE
PSPIP
SPEN
ADIF
ADIE
ADIP
RX9
RC1IF
RC1IE
RC1IP
SREN
TMR2IF TMR1IF
TMR2IE TMR1IE
TMR2IP TMR1IP
PIE1
—
IPR1
—
RCSTA1
RCREG1
TXSTA1
FERR
OERR
RX9D
EUSART Receive Register
CSRC
TX9
TXEN
—
SYNC
SCKP
SENDB
BRG16
BRGH
—
TRMT
WUE
TX9D
BAUDCON1 ABDOVF
RCMT
ABDEN
SPBRGH1 EUSART Baud Rate Generator Register High Byte
SPBRG1 EUSART Baud Rate Generator Register Low Byte
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used for synchronous slave reception.
DS39774C-page 236
Preliminary
© 2007 Microchip Technology Inc.
PIC18F85J11 FAMILY
18.0 ADDRESSABLE UNIVERSAL
SYNCHRONOUS
Note:
The AUSART control will automatically
reconfigure the pin from input to output as
needed.
ASYNCHRONOUS RECEIVER
TRANSMITTER (AUSART)
The driver for the TX2 output pin can also be optionally
configured as an open-drain output. This feature allows
the voltage level on the pin to be pulled to a higher level
through an external pull-up resistor, and allows the
output to communicate with external circuits without the
need for additional level shifters.
The Addressable Universal Synchronous Asynchro-
nous Receiver Transmitter (AUSART) module is very
similar in function to the Enhanced USART module
discussed in the previous chapter. It is provided as an
additional channel for serial communication with
external devices for those situations that do not require
Auto-Baud Detection or LIN bus support.
The open-drain output option is controlled by the U2OD
bit (LATG<7>). Setting this bit configures the pin for
open-drain operation.
The AUSART can be configured in the following modes:
• Asynchronous (full-duplex)
18.1 Control Registers
• Synchronous – Master (half-duplex)
• Synchronous – Slave (half-duplex)
The operation of the Addressable USART module is
controlled through two registers, TXSTA2 and
RCSTA2. These are detailed in Register 18-1 and
Register 18-2, respectively.
The pins of the AUSART module are multiplexed with
the functions of PORTG (RG1/TX2/CK2 and
RG2/RX2/DT2, respectively). In order to configure
these pins as an AUSART:
• bit SPEN (RCSTA2<7>) must be set (= 1)
• bit TRISG<2> must be set (= 1)
• bit TRISG<1> must be cleared (= 0) for
Asynchronous and Synchronous Master modes
• bit TRISG<1> must be set (= 1) for Synchronous
Slave mode
© 2007 Microchip Technology Inc.
Preliminary
DS39774C-page 237
PIC18F85J11 FAMILY
REGISTER 18-1: TXSTA2: AUSART TRANSMIT STATUS AND CONTROL REGISTER
R/W-0
CSRC
R/W-0
TX9
R/W-0
TXEN(1)
R/W-0
SYNC
U-0
—
R/W-0
BRGH
R-1
R/W-0
TX9D
TRMT
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7
CSRC: Clock Source Select bit
Asynchronous mode:
Don’t care.
Synchronous mode:
1= Master mode (clock generated internally from BRG)
0= Slave mode (clock from external source)
bit 6
bit 5
TX9: 9-Bit Transmit Enable bit
1= Selects 9-bit transmission
0= Selects 8-bit transmission
TXEN: Transmit Enable bit(1)
1= Transmit enabled
0= Transmit disabled
bit 4
SYNC: AUSART Mode Select bit
1= Synchronous mode
0= Asynchronous mode
bit 3
bit 2
Unimplemented: Read as ‘0’
BRGH: High Baud Rate Select bit
Asynchronous mode:
1= High speed
0= Low speed
Synchronous mode:
Unused in this mode.
bit 1
bit 0
TRMT: Transmit Shift Register Status bit
1= TSR empty
0= TSR full
TX9D: 9th Bit of Transmit Data
Can be address/data bit or parity bit.
Note 1: SREN/CREN overrides TXEN in Sync mode.
DS39774C-page 238
Preliminary
© 2007 Microchip Technology Inc.
PIC18F85J11 FAMILY
REGISTER 18-2: RCSTA2: AUSART RECEIVE STATUS AND CONTROL REGISTER
R/W-0
SPEN
R/W-0
RX9
R/W-0
SREN
R/W-0
CREN
R/W-0
R-0
R-0
R-x
ADDEN
FERR
OERR
RX9D
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7
bit 6
bit 5
SPEN: Serial Port Enable bit
1= Serial port enabled (configures RX2/DT2 and TX2/CK2 pins as serial port pins)
0= Serial port disabled (held in Reset)
RX9: 9-Bit Receive Enable bit
1= Selects 9-bit reception
0= Selects 8-bit reception
SREN: Single Receive Enable bit
Asynchronous mode:
Don’t care.
Synchronous mode – Master:
1= Enables single receive
0= Disables single receive
This bit is cleared after reception is complete.
Synchronous mode – Slave:
Don’t care.
bit 4
CREN: Continuous Receive Enable bit
Asynchronous mode:
1= Enables receiver
0= Disables receiver
Synchronous mode:
1= Enables continuous receive until enable bit, CREN, is cleared (CREN overrides SREN)
0= Disables continuous receive
bit 3
ADDEN: Address Detect Enable bit
Asynchronous mode 9-Bit (RX9 = 1):
1= Enables address detection, enables interrupt and loads the receive buffer when RSR<8> is set
0= Disables address detection, all bytes are received and ninth bit can be used as parity bit
Asynchronous mode 9-Bit (RX9 = 0):
Don’t care.
bit 2
bit 1
bit 0
FERR: Framing Error bit
1= Framing error (can be updated by reading RCREG2 register and receiving next valid byte)
0= No framing error
OERR: Overrun Error bit
1= Overrun error (can be cleared by clearing the CREN bit)
0= No overrun error
RX9D: 9th Bit of Received Data
This can be address/data bit or parity bit and must be calculated by user firmware.
© 2007 Microchip Technology Inc.
Preliminary
DS39774C-page 239
PIC18F85J11 FAMILY
geous to use the high baud rate (BRGH = 1) to reduce
the baud rate error, or achieve a slow baud rate for a
fast oscillator frequency.
18.2 AUSART Baud Rate Generator
(BRG)
The BRG is a dedicated, 8-bit generator that supports
both the Asynchronous and Synchronous modes of the
AUSART.
Writing a new value to the SPBRG2 register causes the
BRG timer to be reset (or cleared). This ensures the
BRG does not wait for a timer overflow before outputting
the new baud rate.
The SPBRG2 register controls the period of a
free-running timer. In Asynchronous mode, bit BRGH
(TXSTA<2>) also controls the baud rate. In Synchro-
nous mode, BRGH is ignored. Table 18-1 shows the
formula for computation of the baud rate for different
AUSART modes, which only apply in Master mode
(internally generated clock).
18.2.1
OPERATION IN POWER-MANAGED
MODES
The device clock is used to generate the desired baud
rate. When one of the power-managed modes is
entered, the new clock source may be operating at a
different frequency. This may require an adjustment to
the value in the SPBRG2 register.
Given the desired baud rate and FOSC, the nearest
integer value for the SPBRG2 register can be calcu-
lated using the formulas in Table 18-1. From this, the
error in baud rate can be determined. An example
calculation is shown in Example 18-1. Typical baud
rates and error values for the various Asynchronous
modes are shown in Table 18-2. It may be advanta-
18.2.2
SAMPLING
The data on the RX2 pin is sampled three times by a
majority detect circuit to determine if a high or low level
is present at the RX2 pin.
TABLE 18-1: BAUD RATE FORMULAS
Configuration Bits
BRG/AUSART Mode
Baud Rate Formula
SYNC
BRGH
0
0
1
0
1
x
Asynchronous
Asynchronous
Synchronous
FOSC/[64 (n + 1)]
FOSC/[16 (n + 1)]
FOSC/[4 (n + 1)]
Legend: x= Don’t care, n = Value of SPBRG2 register
EXAMPLE 18-1: CALCULATING BAUD RATE ERROR
For a device with FOSC of 16 MHz, desired baud rate of 9600, Asynchronous mode, BRGH = 0:
Desired Baud Rate
Solving for SPBRG2:
X
=
FOSC/(64 ([SPBRG2] + 1))
=
=
=
((FOSC/Desired Baud Rate)/64) – 1
((16000000/9600)/64) – 1
[25.042] = 25
Calculated Baud Rate = 16000000/(64 (25 + 1))
=
=
=
9615
Error
(Calculated Baud Rate – Desired Baud Rate)/Desired Baud Rate
(9615 – 9600)/9600 = 0.16%
TABLE 18-2: REGISTERS ASSOCIATED WITH THE BAUD RATE GENERATOR
Reset
Values on
Page
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
TXSTA2
RCSTA2
SPBRG2
CSRC
SPEN
TX9
RX9
TXEN
SREN
SYNC
CREN
—
BRGH
FERR
TRMT
OERR
TX9D
RX9D
55
55
55
ADDEN
AUSART Baud Rate Generator Register
Legend: — = unimplemented locations read as ‘0’. Shaded cells are not used by the BRG.
DS39774C-page 240
Preliminary
© 2007 Microchip Technology Inc.
PIC18F85J11 FAMILY
TABLE 18-3: BAUD RATES FOR ASYNCHRONOUS MODES
BRGH = 0
FOSC = 40.000 MHz
FOSC = 20.000 MHz
FOSC = 10.000 MHz
FOSC = 8.000 MHz
BAUD
RATE
(K)
Actual
Rate
(K)
SPBRG Actual
SPBRG Actual
SPBRG Actual
SPBRG
Value
(decimal)
%
Error
%
Error
%
Error
%
Error
Value
Rate
(K)
Value
Rate
(K)
Value
Rate
(K)
(decimal)
(decimal)
(decimal)
0.3
1.2
—
—
—
—
—
—
—
255
129
31
15
4
—
—
—
129
64
15
7
—
1.201
2.403
9.615
—
—
-0.16
-0.16
-0.16
—
—
103
51
12
—
—
—
1.221
1.73
0.16
1.73
1.73
8.51
-9.58
1.202
2.404
9.766
19.531
52.083
78.125
0.16
0.16
1.73
1.73
-9.58
-32.18
2.4
2.441
9.615
19.531
56.818
125.000
1.73
0.16
1.73
-1.36
8.51
255
64
31
10
4
2.404
9.6
9.766
19.2
57.6
115.2
19.531
62.500
104.167
2
—
—
—
2
1
—
—
—
BRGH = 0
FOSC = 4.000 MHz
FOSC = 2.000 MHz
FOSC = 1.000 MHz
BAUD
RATE
(K)
Actual
Rate
(K)
SPBRG Actual
SPBRG Actual
SPBRG
Value
(decimal)
%
Error
%
Error
%
Error
Value
Rate
(K)
Value
Rate
(K)
(decimal)
(decimal)
0.3
1.2
0.300
1.202
0.16
0.16
207
51
25
6
0.300
1.201
2.403
—
-0.16
-0.16
-0.16
—
103
25
12
—
0.300
1.201
—
-0.16
-0.16
—
51
12
—
—
—
—
—
2.4
2.404
0.16
9.6
8.929
-6.99
8.51
—
—
19.2
57.6
115.2
20.833
62.500
62.500
2
—
—
—
—
—
8.51
0
—
—
—
—
—
-45.75
0
—
—
—
—
—
BRGH = 1
BAUD
RATE
(K)
FOSC = 40.000 MHz
FOSC = 20.000 MHz
FOSC = 10.000 MHz
FOSC = 8.000 MHz
Actual
Rate
(K)
SPBRG Actual
Value
SPBRG Actual
Value
(decimal)
SPBRG Actual
Value
(decimal)
SPBRG
Value
(decimal)
%
%
Error
%
Error
%
Error
Rate
(K)
Rate
(K)
Rate
(K)
Error
(decimal)
0.3
1.2
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
2.4
—
—
—
—
—
—
2.441
9.615
19.531
56.818
125.000
1.73
0.16
1.73
-1.36
8.51
255
64
31
10
4
2.403
9.615
19.230
55.555
—
-0.16
-0.16
-0.16
3.55
—
207
51
25
8
9.6
9.766
19.231
58.140
113.636
1.73
0.16
0.94
-1.36
255
129
42
9.615
19.231
56.818
113.636
0.16
0.16
-1.36
-1.36
129
64
21
10
19.2
57.6
115.2
21
—
BRGH = 1
BAUD
RATE
(K)
FOSC = 4.000 MHz
FOSC = 2.000 MHz
FOSC = 1.000 MHz
Actual
Rate
(K)
SPBRG Actual
Value
SPBRG Actual
Value
(decimal)
SPBRG
Value
(decimal)
%
%
Error
%
Error
Rate
(K)
Rate
(K)
Error
(decimal)
0.3
1.2
—
—
—
207
103
25
12
3
—
1.201
2.403
9.615
—
—
-0.16
-0.16
-0.16
—
—
103
51
12
—
0.300
1.201
2.403
—
-0.16
-0.16
-0.16
—
207
51
25
—
1.202
0.16
0.16
0.16
0.16
8.51
8.51
2.4
2.404
9.6
9.615
19.2
57.6
115.2
19.231
62.500
125.000
—
—
—
—
—
—
—
—
—
1
—
—
—
—
—
—
© 2007 Microchip Technology Inc.
Preliminary
DS39774C-page 241
PIC18F85J11 FAMILY
Once the TXREG2 register transfers the data to the
TSR register (occurs in one TCY), the TXREG2 register
is empty and the TX2IF flag bit (PIR3<4>) is set. This
interrupt can be enabled or disabled by setting or
clearing the interrupt enable bit, TX2IE (PIE3<4>).
TX2IF will be set regardless of the state of TX2IE; it
cannot be cleared in software. TX2IF is also not
cleared immediately upon loading TXREG2, but
becomes valid in the second instruction cycle following
the load instruction. Polling TX2IF immediately
following a load of TXREG2 will return invalid results.
18.3 AUSART Asynchronous Mode
The Asynchronous mode of operation is selected by
clearing the SYNC bit (TXSTA2<4>). In this mode, the
AUSART uses standard Non-Return-to-Zero (NRZ)
format (one Start bit, eight or nine data bits and one
Stop bit). The most common data format is 8 bits. An
on-chip, dedicated, 8-bit Baud Rate Generator can be
used to derive standard baud rate frequencies from the
oscillator.
The AUSART transmits and receives the LSb first. The
AUSART’s transmitter and receiver are functionally
independent but use the same data format and baud
rate. The Baud Rate Generator produces a clock,
either x16 or x64 of the bit shift rate, depending on the
BRGH bit (TXSTA2<2>). Parity is not supported by the
hardware but can be implemented in software and
stored as the 9th data bit.
While TX2IF indicates the status of the TXREG2
register, another bit, TRMT (TXSTA2<1>), shows the
status of the TSR register. TRMT is a read-only bit
which is set when the TSR register is empty. No inter-
rupt logic is tied to this bit so the user has to poll this bit
in order to determine if the TSR register is empty.
Note 1: The TSR register is not mapped in data
When operating in Asynchronous mode, the AUSART
module consists of the following important elements:
memory so it is not available to the user.
2: Flag bit, TX2IF, is set when enable bit,
• Baud Rate Generator
• Sampling Circuit
TXEN, is set.
To set up an Asynchronous Transmission:
• Asynchronous Transmitter
• Asynchronous Receiver
1. Initialize the SPBRG2 register for the appropri-
ate baud rate. Set or clear the BRGH bit, as
required, to achieve the desired baud rate.
18.3.1
AUSART ASYNCHRONOUS
TRANSMITTER
2. Enable the asynchronous serial port by clearing
the SYNC bit and setting the SPEN bit.
The AUSART transmitter block diagram is shown in
Figure 18-1. The heart of the transmitter is the Transmit
(Serial) Shift register (TSR). The Shift register obtains
its data from the Read/Write Transmit Buffer register,
TXREG2. The TXREG2 register is loaded with data in
software. The TSR register is not loaded until the Stop
bit has been transmitted from the previous load. As
soon as the Stop bit is transmitted, the TSR is loaded
with new data from the TXREG2 register (if available).
3. If interrupts are desired, set enable bit, TX2IE.
4. If 9-bit transmission is desired, set transmit bit,
TX9; can be used as address/data bit.
5. Enable the transmission by setting bit, TXEN,
which will also set bit, TX2IF.
6. If 9-bit transmission is selected, the ninth bit
should be loaded in bit, TX9D.
7. Load data to the TXREG2 register (starts
transmission).
8. If using interrupts, ensure that the GIE and PEIE bits
in the INTCON register (INTCON<7:6>) are set.
FIGURE 18-1:
AUSART TRANSMIT BLOCK DIAGRAM
Data Bus
TXREG2 Register
TX2IF
TX2IE
8
MSb
(8)
LSb
Pin Buffer
0
•
•
•
and Control
TX2 pin
TSR Register
Interrupt
Baud Rate CLK
TXEN
TRMT
SPEN
SPBRG2
Baud Rate Generator
TX9
TX9D
DS39774C-page 242
Preliminary
© 2007 Microchip Technology Inc.
PIC18F85J11 FAMILY
FIGURE 18-2:
ASYNCHRONOUS TRANSMISSION
Write to TXREG2
Word 1
BRG Output
(Shift Clock)
TX2 (pin)
Start bit
bit 0
bit 1
Word 1
bit 7/8
Stop bit
TX2IF bit
(Transmit Buffer
Reg. Empty Flag)
1 TCY
Word 1
Transmit Shift Reg
TRMT bit
(Transmit Shift
Reg. Empty Flag)
FIGURE 18-3:
ASYNCHRONOUS TRANSMISSION (BACK-TO-BACK)
Write to TXREG2
Word 2
Start bit
Word 1
BRG Output
(Shift Clock)
TX2 (pin)
bit 0
bit 1
bit 7/8
Stop bit
Start bit
Word 2
bit 0
1 TCY
Word 1
TX2IF bit
(Interrupt Reg. Flag)
1 TCY
Word 1
Transmit Shift Reg.
Word 2
Transmit Shift Reg.
TRMT bit
(Transmit Shift
Reg. Empty Flag)
Note: This timing diagram shows two consecutive transmissions.
TABLE 18-4: REGISTERS ASSOCIATED WITH ASYNCHRONOUS TRANSMISSION
Reset
Values
on Page
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
INTCON
PIR3
GIE/GIEH PEIE/GIEL TMR0IE
INT0IE
TX2IF
TX2IE
TX2IP
CREN
RBIE
—
TMR0IF
CCP2IF
CCP2IE
CCP2IP
FERR
INT0IF
CCP1IF
CCP1IE
CCP1IP
OERR
RBIF
—
51
53
53
53
55
55
55
55
54
—
—
—
—
RC2IF
RC2IE
RC2IP
SREN
PIE3
—
—
IPR3
—
—
—
—
RCSTA2
TXREG2
TXSTA2
SPBRG2
LATG
SPEN
RX9
ADDEN
RX9D
AUSART Transmit Register
CSRC TX9 TXEN
SYNC
—
BRGH
TRMT
TX9D
AUSART Baud Rate Generator Register
U2OD U1OD LATG4
—
LATG3
LATG2
LATG1
LATG0
Legend: — = unimplemented locations read as ‘0’. Shaded cells are not used for asynchronous transmission.
© 2007 Microchip Technology Inc.
Preliminary
DS39774C-page 243
PIC18F85J11 FAMILY
18.3.2
AUSART ASYNCHRONOUS
RECEIVER
18.3.3
SETTING UP 9-BIT MODE WITH
ADDRESS DETECT
The receiver block diagram is shown in Figure 18-4.
The data is received on the RX2 pin and drives the data
recovery block. The data recovery block is actually a
high-speed shifter operating at x16 times the baud rate,
whereas the main receive serial shifter operates at the
bit rate or at FOSC. This mode would typically be used
in RS-232 systems.
This mode would typically be used in RS-485 systems.
To set up an Asynchronous Reception with Address
Detect Enable:
1. Initialize the SPBRG2 register for the appropriate
baud rate. Set or clear the BRGH and BRG16
bits, as required, to achieve the desired baud
rate.
To set up an Asynchronous Reception:
2. Enable the asynchronous serial port by clearing
the SYNC bit and setting the SPEN bit.
1. Initialize the SPBRG2 register for the appropriate
baud rate. Set or clear the BRGH bit, as required,
to achieve the desired baud rate.
3. If interrupts are required, set the RCEN bit and
select the desired priority level with the RC2IP
bit.
2. Enable the asynchronous serial port by clearing
bit, SYNC, and setting bit, SPEN.
4. Set the RX9 bit to enable 9-bit reception.
5. Set the ADDEN bit to enable address detect.
6. Enable reception by setting the CREN bit.
3. If interrupts are desired, set enable bit, RC2IE.
4. If 9-bit reception is desired, set bit, RX9.
5. Enable the reception by setting bit, CREN.
7. The RC2IF bit will be set when reception is
complete. The interrupt will be Acknowledged if
the RC2IE and GIE bits are set.
6. Flag bit, RC2IF, will be set when reception is
complete and an interrupt will be generated if
enable bit, RC2IE, was set.
8. Read the RCSTA2 register to determine if any
error occurred during reception, as well as read
bit 9 of data (if applicable).
7. Read the RCSTA2 register to get the 9th bit (if
enabled) and determine if any error occurred
during reception.
9. Read RCREG2 to determine if the device is
being addressed.
8. Read the 8-bit received data by reading the
RCREG2 register.
10. If any error occurred, clear the CREN bit.
9. If any error occurred, clear the error by clearing
enable bit, CREN.
11. If the device has been addressed, clear the
ADDEN bit to allow all received data into the
receive buffer and interrupt the CPU.
10. If using interrupts, ensure that the GIE and PEIE
bits in the INTCON register (INTCON<7:6>) are
set.
FIGURE 18-4:
AUSART RECEIVE BLOCK DIAGRAM
CREN
FERR
OERR
x64 Baud Rate CLK
SPBRG2
÷ 64
or
MSb
RSR Register
• • •
LSb
÷ 16
Stop (8)
7
1
0
Start
or
÷ 4
Baud Rate Generator
RX9
Pin Buffer
and Control
Data
Recovery
RX2
RCREG2 Register
RX9D
FIFO
SPEN
8
Interrupt
RC2IF
RC2IE
Data Bus
DS39774C-page 244
Preliminary
© 2007 Microchip Technology Inc.
PIC18F85J11 FAMILY
FIGURE 18-5:
ASYNCHRONOUS RECEPTION
Start
bit
Start
bit
Start
bit
RX2 (pin)
bit 0 bit 1
bit 7/8 Stop
bit
bit 0
bit 7/8 Stop
bit
bit 7/8 Stop
bit
Rcv Shift Reg
Rcv Buffer Reg
Word 2
RCREG2
Word 1
RCREG2
Read Rcv
Buffer Reg
RCREG2
RC2IF
(Interrupt Flag)
OERR bit
CREN
Note: This timing diagram shows three words appearing on the RX2 input. The RCREG2 (AUSART Receive register) is read after the third
word, causing the OERR (Overrun Error) bit to be set.
TABLE 18-5: REGISTERS ASSOCIATED WITH ASYNCHRONOUS RECEPTION
Reset
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Values
on Page
INTCON
PIR3
GIE/GIEH PEIE/GIEL TMR0IE
INT0IE
TX2IF
TX2IE
TX2IP
CREN
RBIE
—
TMR0IF
CCP2IF
INT0IF
RBIF
—
51
53
53
53
55
55
55
55
—
—
—
—
RC2IF
RC2IE
RC2IP
SREN
CCP1IF
PIE3
—
CCP2IE CCP1IE
CCP2IP CCP1IP
—
IPR3
—
—
—
—
RCSTA2
RCREG2
TXSTA2
SPBRG2
SPEN
RX9
ADDEN
FERR
OERR
RX9D
AUSART Receive Register
CSRC TX9 TXEN
SYNC
—
BRGH
TRMT
TX9D
AUSART Baud Rate Generator Register
Legend: — = unimplemented locations read as ‘0’. Shaded cells are not used for asynchronous reception.
© 2007 Microchip Technology Inc.
Preliminary
DS39774C-page 245
PIC18F85J11 FAMILY
Once the TXREG2 register transfers the data to the
TSR register (occurs in one TCYCLE), the TXREG2 is
empty and the TX2IF flag bit (PIR3<4>) is set. The
interrupt can be enabled or disabled by setting or clear-
ing the interrupt enable bit, TX2IE (PIE3<4>). TX2IF is
set regardless of the state of enable bit, TX2IE; it
cannot be cleared in software. It will reset only when
new data is loaded into the TXREG2 register.
18.4 AUSART Synchronous
Master Mode
The Synchronous Master mode is entered by setting
the CSRC bit (TXSTA2<7>). In this mode, the data is
transmitted in a half-duplex manner (i.e., transmission
and reception do not occur at the same time). When
transmitting data, the reception is inhibited and vice
versa. Synchronous mode is entered by setting bit,
SYNC (TXSTA2<4>). In addition, enable bit, SPEN
(RCSTA2<7>), is set in order to configure the TX2 and
RX2 pins to CK2 (clock) and DT2 (data) lines,
respectively.
While flag bit, TX2IF, indicates the status of the TXREG2
register, another bit, TRMT (TXSTA2<1>), shows the
status of the TSR register. TRMT is a read-only bit which
is set when the TSR is empty. No interrupt logic is tied to
this bit so the user has to poll this bit in order to deter-
mine if the TSR register is empty. The TSR is not
mapped in data memory so it is not available to the user.
The Master mode indicates that the processor transmits
the master clock on the CK2 line.
To set up a Synchronous Master Transmission:
18.4.1
AUSART SYNCHRONOUS MASTER
TRANSMISSION
1. Initialize the SPBRG2 register for the appropriate
baud rate.
The AUSART transmitter block diagram is shown in
Figure 18-1. The heart of the transmitter is the Transmit
(Serial) Shift register (TSR). The Shift register obtains
its data from the Read/Write Transmit Buffer register,
TXREG2. The TXREG2 register is loaded with data in
software. The TSR register is not loaded until the last
bit has been transmitted from the previous load. As
soon as the last bit is transmitted, the TSR is loaded
with new data from the TXREG2 (if available).
2. Enable the synchronous master serial port by
setting bits, SYNC, SPEN and CSRC.
3. If interrupts are desired, set enable bit, TX2IE.
4. If 9-bit transmission is desired, set bit, TX9.
5. Enable the transmission by setting bit, TXEN.
6. If 9-bit transmission is selected, the ninth bit
should be loaded in bit TX9D.
7. Start transmission by loading data to the
TXREG2 register.
8. If using interrupts, ensure that the GIE and PEIE
bits in the INTCON register (INTCON<7:6>) are
set.
FIGURE 18-6:
SYNCHRONOUS TRANSMISSION
Q1 Q2 Q3Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1Q2 Q3 Q4 Q1 Q2 Q3 Q4
Q3 Q4 Q1 Q2 Q3Q4 Q1Q2 Q3Q4 Q1 Q2Q3Q4 Q1 Q2Q3 Q4Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
RX2/DT2 pin
TX2/CK2 pin
bit 0
bit 1
bit 2
bit 7
bit 0
bit 1
bit 7
Word 2
Word 1
Write to
TXREG2 Reg
Write Word 1
Write Word 2
TX2IF bit
(Interrupt Flag)
TRMT bit
TXEN bit
‘1’
‘1’
Note: Sync Master mode, SPBRG2 = 0; continuous transmission of two 8-bit words.
DS39774C-page 246
Preliminary
© 2007 Microchip Technology Inc.
PIC18F85J11 FAMILY
FIGURE 18-7:
SYNCHRONOUS TRANSMISSION (THROUGH TXEN)
RX2/DT2 pin
bit 0
bit 1
bit 2
bit 6
bit 7
TX2/CK2 pin
Write to
TXREG2 Reg
TX2IF bit
TRMT bit
TXEN bit
TABLE 18-6: REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER TRANSMISSION
Reset
Values
on Page
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
INTCON
PIR3
GIE/GIEH PEIE/GIEL TMR0IE
INT0IE
TX2IF
TX2IE
TX2IP
CREN
RBIE
—
TMR0IF
CCP2IF
INT0IF
RBIF
—
51
53
53
53
55
55
55
55
54
—
—
—
—
RC2IF
RC2IE
RC2IP
SREN
CCP1IF
PIE3
—
CCP2IE CCP1IE
CCP2IP CCP1IP
—
IPR3
—
—
—
—
RCSTA2
TXREG2
TXSTA2
SPBRG2
LATG
SPEN
RX9
ADDEN
FERR
BRGH
LATG2
OERR
TRMT
LATG1
RX9D
AUSART Transmit Register
CSRC TX9 TXEN
SYNC
—
TX9D
AUSART Baud Rate Generator Register
U2OD U1OD LATG4
—
LATG3
LATG0
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used for synchronous master transmission.
© 2007 Microchip Technology Inc.
Preliminary
DS39774C-page 247
PIC18F85J11 FAMILY
4. If interrupts are desired, set enable bit, RC2IE.
5. If 9-bit reception is desired, set bit, RX9.
18.4.2
AUSART SYNCHRONOUS
MASTER RECEPTION
6. If a single reception is required, set bit, SREN.
For continuous reception, set bit, CREN.
Once Synchronous mode is selected, reception is
enabled by setting either the Single Receive Enable bit,
SREN (RCSTA2<5>), or the Continuous Receive
Enable bit, CREN (RCSTA2<4>). Data is sampled on
the RX2 pin on the falling edge of the clock.
7. Interrupt flag bit, RC2IF, will be set when
reception is complete and an interrupt will be
generated if the enable bit, RC2IE, was set.
8. Read the RCSTA2 register to get the 9th bit (if
enabled) and determine if any error occurred
during reception.
If enable bit, SREN, is set, only a single word is
received. If enable bit, CREN, is set, the reception is
continuous until CREN is cleared. If both bits are set,
then CREN takes precedence.
9. Read the 8-bit received data by reading the
RCREG2 register.
To set up a Synchronous Master Reception:
10. If any error occurred, clear the error by clearing
bit, CREN.
1. Initialize the SPBRG2 register for the appropriate
baud rate.
11. If using interrupts, ensure that the GIE and PEIE
bits in the INTCON register (INTCON<7:6>) are
set.
2. Enable the synchronous master serial port by
setting bits SYNC, SPEN and CSRC.
3. Ensure bits CREN and SREN are clear.
FIGURE 18-8:
SYNCHRONOUS RECEPTION (MASTER MODE, SREN)
Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
RX2/DT2 pin
TX2/CK2 pin
bit 0
bit 1
bit 2
bit 3
bit 4
bit 5
bit 6
bit 7
Write to
bit SREN
SREN bit
CREN bit
‘0’
‘0’
RC2IF bit
(Interrupt)
Read
RCREG2
Note: Timing diagram demonstrates Sync Master mode with bit SREN = 1and bit BRGH = 0.
TABLE 18-7: REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER RECEPTION
Reset
Values
on Page
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
INTCON
PIR3
GIE/GIEH PEIE/GIEL TMR0IE
INT0IE
TX2IF
TX2IE
TX2IP
CREN
RBIE
—
TMR0IF
CCP2IF
CCP2IE
CCP2IP
FERR
INT0IF
CCP1IF
CCP1IE
CCP1IP
OERR
RBIF
—
51
53
53
53
55
55
55
55
—
—
—
—
RC2IF
RC2IE
RC2IP
SREN
PIE3
—
—
IPR3
—
—
—
—
RCSTA2
SPEN
RX9
ADDEN
RX9D
RCREG2 AUSART Receive Register
TXSTA2 CSRC TX9 TXEN
SYNC
—
BRGH
TRMT
TX9D
SPBRG2 AUSART Baud Rate Generator Register
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used for synchronous master reception.
DS39774C-page 248
Preliminary
© 2007 Microchip Technology Inc.
PIC18F85J11 FAMILY
To set up a Synchronous Slave Transmission:
18.5 AUSART Synchronous Slave Mode
1. Enable the synchronous slave serial port by
setting bits, SYNC and SPEN, and clearing bit,
CSRC.
Synchronous Slave mode is entered by clearing bit,
CSRC (TXSTA2<7>). This mode differs from the
Synchronous Master mode in that the shift clock is
supplied externally at the CK2 pin (instead of being
supplied internally in Master mode). This allows the
device to transfer or receive data while in any
low-power mode.
2. Clear bits, CREN and SREN.
3. If interrupts are desired, set enable bit, TX2IE.
4. If 9-bit transmission is desired, set bit, TX9.
5. Enable the transmission by setting enable bit,
TXEN.
18.5.1
AUSART SYNCHRONOUS
SLAVE TRANSMIT
6. If 9-bit transmission is selected, the ninth bit
should be loaded in bit TX9D.
The operation of the Synchronous Master and Slave
modes are identical except in the case of the Sleep
mode.
7. Start transmission by loading data to the
TXREG2 register.
8. If using interrupts, ensure that the GIE and PEIE
bits in the INTCON register (INTCON<7:6>) are
set.
If two words are written to the TXREG2 and then the
SLEEPinstruction is executed, the following will occur:
a) The first word will immediately transfer to the
TSR register and transmit.
b) The second word will remain in the TXREG2
register.
c) Flag bit, TX2IF, will not be set.
d) When the first word has been shifted out of TSR,
the TXREG2 register will transfer the second
word to the TSR and flag bit, TX2IF, will now be
set.
e) If enable bit, TX2IE, is set, the interrupt will wake
the chip from Sleep. If the global interrupt is
enabled, the program will branch to the interrupt
vector.
TABLE 18-8: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE TRANSMISSION
Reset
Values
on Page
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
INTCON
PIR3
GIE/GIEH PEIE/GIEL TMR0IE
INT0IE
TX2IF
TX2IE
TX2IP
CREN
RBIE
—
TMR0IF
CCP2IF
CCP2IE
CCP2IP
FERR
INT0IF
CCP1IF
CCP1IE
CCP1IP
OERR
RBIF
—
51
53
53
53
55
55
55
55
54
—
—
—
—
RC2IF
RC2IE
RC2IP
SREN
PIE3
—
—
IPR3
—
—
—
—
RCSTA2
TXREG2
TXSTA2
SPBRG2
LATG
SPEN
RX9
ADDEN
RX9D
AUSART Transmit Register
CSRC TX9 TXEN
SYNC
—
BRGH
TRMT
TX9D
AUSART Baud Rate Generator Register
U2OD U1OD LATG4
—
LATG3
LATG2
LATG1
LATG0
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used for synchronous slave transmission.
© 2007 Microchip Technology Inc.
Preliminary
DS39774C-page 249
PIC18F85J11 FAMILY
To set up a Synchronous Slave Reception:
18.5.2
AUSART SYNCHRONOUS
SLAVE RECEPTION
1. Enable the synchronous master serial port by
setting bits, SYNC and SPEN, and clearing bit,
CSRC.
The operation of the Synchronous Master and Slave
modes is identical except in the case of Sleep or any
Idle mode, and bit, SREN, which is a “don’t care” in
Slave mode.
2. If interrupts are desired, set enable bit, RC2IE.
3. If 9-bit reception is desired, set bit, RX9.
4. To enable reception, set enable bit, CREN.
If receive is enabled by setting the CREN bit prior to
entering Sleep or any Idle mode, then a word may be
received while in this low-power mode. Once the word
is received, the RSR register will transfer the data to the
RCREG2 register. If the RC2IE enable bit is set, the
interrupt generated will wake the chip from the
low-power mode. If the global interrupt is enabled, the
program will branch to the interrupt vector.
5. Flag bit, RC2IF, will be set when reception is
complete. An interrupt will be generated if
enable bit, RC2IE, was set.
6. Read the RCSTA2 register to get the 9th bit (if
enabled) and determine if any error occurred
during reception.
7. Read the 8-bit received data by reading the
RCREG2 register.
8. If any error occurred, clear the error by clearing
bit, CREN.
9. If using interrupts, ensure that the GIE and PEIE
bits in the INTCON register (INTCON<7:6>) are
set.
TABLE 18-9: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE RECEPTION
Reset
Values
on Page
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
INTCON
PIR3
GIE/GIEH PEIE/GIEL TMR0IE
INT0IE
TX2IF
TX2IE
TX2IP
CREN
RBIE
—
TMR0IF
CCP2IF
INT0IF
RBIF
—
51
53
53
53
55
55
55
55
—
—
—
—
RC2IF
RC2IE
RC2IP
SREN
CCP1IF
PIE3
—
CCP2IE CCP1IE
CCP2IP CCP1IP
—
IPR3
—
—
—
—
RCSTA2
RCREG2
TXSTA2
SPBRG2
SPEN
RX9
ADDEN
FERR
OERR
RX9D
AUSART Receive Register
CSRC TX9 TXEN
SYNC
—
BRGH
TRMT
TX9D
AUSART Baud Rate Generator Register
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used for synchronous slave reception.
DS39774C-page 250
Preliminary
© 2007 Microchip Technology Inc.
PIC18F85J11 FAMILY
The ADCON0 register, shown in Register 19-1,
controls the operation of the A/D module. The
ADCON1 register, shown in Register 19-2, configures
the functions of the port pins. The ADCON2 register,
shown in Register 19-3, configures the A/D clock
source, programmed acquisition time and justification.
19.0 10-BIT ANALOG-TO-DIGITAL
CONVERTER (A/D) MODULE
The Analog-to-Digital (A/D) converter module has
12 inputs for all PIC18F85J11 family devices. This
module allows conversion of an analog input signal to
a corresponding 10-bit digital number.
The module has five registers:
• A/D Result Register High Byte (ADRESH)
• A/D Result Register Low Byte (ADRESL)
• A/D Control Register 0 (ADCON0)
• A/D Control Register 1 (ADCON1)
• A/D Control Register 2 (ADCON2)
REGISTER 19-1: ADCON0: A/D CONTROL REGISTER 0
R/W-0
U-0
—
R/W-0
CHS3
R/W-0
CHS2
R/W-0
CHS1
R/W-0
CHS0
R/W-0
R/W-0
ADON
ADCAL
GO/DONE
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7
ADCAL: A/D Calibration bit
1= Calibration is performed on next A/D conversion
0= Normal A/D converter operation (no calibration is performed)
bit 6
Unimplemented: Read as ‘0’
bit 5-2
CHS3:CHS0: Analog Channel Select bits
0000= Channel 00 (AN0)
0001= Channel 01 (AN1)
0010= Channel 02 (AN2)
0011= Channel 03 (AN3)
0100= Channel 04 (AN4)
0101= Channel 05 (AN5)
0110= Channel 06 (AN6)
0111= Channel 07 (AN7)
1000= Channel 08 (AN8)
1001= Channel 09 (AN9)
1010= Channel 10 (AN10)
1011= Channel 11 (AN11)
11xx= Unused
bit 1
bit 0
GO/DONE: A/D Conversion Status bit
When ADON = 1:
1= A/D conversion in progress
0= A/D Idle
ADON: A/D On bit
1= A/D converter module is enabled
0= A/D converter module is disabled
© 2007 Microchip Technology Inc.
Preliminary
DS39774C-page 251
PIC18F85J11 FAMILY
REGISTER 19-2: ADCON1: A/D CONTROL REGISTER 1
U-0
—
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
VCFG1
VCFG0
PCFG3
PCFG2
PCFG1
PCFG0
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7-6
bit 5
Unimplemented: Read as ‘0’
VCFG1: Voltage Reference Configuration bit (VREF- source)
1= VREF- (AN2)
0= AVSS
bit 4
VCFG0: Voltage Reference Configuration bit (VREF+ source)
1= VREF+ (AN3)
0= AVDD
bit 3-0
PCFG3:PCFG0: A/D Port Configuration Control bits:
PCFG<3:0> AN11 AN10 AN9 AN8 AN7 AN6 AN5 AN4 AN3 AN2 AN1 AN0
0000
0001
A
A
A
A
D
D
D
D
D
D
D
D
D
D
D
D
A
A
A
A
A
D
D
D
D
D
D
D
D
D
D
D
A
A
A
A
A
A
D
D
D
D
D
D
D
D
D
D
A
A
A
A
A
A
A
D
D
D
D
D
D
D
D
D
A
A
A
A
A
A
A
A
D
D
D
D
D
D
D
D
A
A
A
A
A
A
A
A
A
D
D
D
D
D
D
D
A
A
A
A
A
A
A
A
A
A
D
D
D
D
D
D
A
A
A
A
A
A
A
A
A
A
A
D
D
D
D
D
A
A
A
A
A
A
A
A
A
A
A
A
D
D
D
D
A
A
A
A
A
A
A
A
A
A
A
A
A
D
D
D
A
A
A
A
A
A
A
A
A
A
A
A
A
A
D
D
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
D
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
A = Analog input
D = Digital I/O
DS39774C-page 252
Preliminary
© 2007 Microchip Technology Inc.
PIC18F85J11 FAMILY
REGISTER 19-3: ADCON2: A/D CONTROL REGISTER 2
R/W-0
ADFM
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
ACQT2
ACQT1
ACQT0
ADCS2
ADCS1
ADCS0
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7
ADFM: A/D Result Format Select bit
1= Right justified
0= Left justified
bit 6
Unimplemented: Read as ‘0’
bit 5-3
ACQT2:ACQT0: A/D Acquisition Time Select bits
111= 20 TAD
110= 16 TAD
101= 12 TAD
100= 8 TAD
011= 6 TAD
010= 4 TAD
001= 2 TAD
(1)
000= 0 TAD
bit 2-0
ADCS2:ADCS0: A/D Conversion Clock Select bits
111= FRC (clock derived from A/D RC oscillator)(1)
110= FOSC/64
101= FOSC/16
100= FOSC/4
011= FRC (clock derived from A/D RC oscillator)(1)
010= FOSC/32
001= FOSC/8
000= FOSC/2
Note 1: If the A/D FRC clock source is selected, a delay of one TCY (instruction cycle) is added before the A/D
clock starts. This allows the SLEEPinstruction to be executed before starting a conversion.
© 2007 Microchip Technology Inc.
Preliminary
DS39774C-page 253
PIC18F85J11 FAMILY
The analog reference voltage is software selectable to
either the device’s positive and negative supply voltage
(AVDD and AVSS), or the voltage level on the
RA3/AN3/VREF+ and RA2/AN2/VREF- pins.
the A/D conversion. When the A/D conversion is com-
plete, the result is loaded into the ADRESH:ADRESL
register pair, the GO/DONE bit (ADCON0<1>) is
cleared and the A/D Interrupt Flag bit, ADIF, is set.
The A/D converter has a unique feature of being able
to operate while the device is in Sleep mode. To
operate in Sleep, the A/D conversion clock must be
derived from the A/D’s internal RC oscillator.
A device Reset forces all registers to their Reset state.
This forces the A/D module to be turned off and any
conversion in progress is aborted. The value in the
ADRESH:ADRESL register pair is not modified for a
Power-on Reset. These registers will contain unknown
data after a Power-on Reset.
The output of the sample and hold is the input into the
converter, which generates the result via successive
approximation.
The block diagram of the A/D module is shown in
Figure 19-1.
Each port pin associated with the A/D converter can be
configured as an analog input or as a digital I/O. The
ADRESH and ADRESL registers contain the result of
FIGURE 19-1:
A/D BLOCK DIAGRAM(1)
CHS3:CHS0
1011
AN11
1010
AN10
1001
AN9
1000
AN8
0111
AN7
0110
AN6
0101
AN5
0100
AN4
VAIN
0011
(Input Voltage)
10-Bit
A/D
AN3
Converter
0010
AN2
0001
VCFG1:VCFG0
AN1
0000
AN0
VDD
VREF+
VREF-
Reference
Voltage
VSS
Note 1: I/O pins have diode protection to VDD and VSS.
DS39774C-page 254
Preliminary
© 2007 Microchip Technology Inc.
PIC18F85J11 FAMILY
After the A/D module has been configured as desired,
the selected channel must be acquired before the
conversion is started. The analog input channels must
have their corresponding TRIS bits selected as inputs.
To determine acquisition time, see Section 19.1 “A/D
Acquisition Requirements”. After this acquisition
time has elapsed, the A/D conversion can be started.
An acquisition time can be programmed to occur
between setting the GO/DONE bit and the actual start
of the conversion.
3. Wait the required acquisition time (if required).
4. Start conversion:
• Set GO/DONE bit (ADCON0<1>)
5. Wait for A/D conversion to complete, by either:
• Polling for the GO/DONE bit to be cleared
OR
• Waiting for the A/D interrupt
6. Read A/D Result registers (ADRESH:ADRESL);
clear ADIF bit, if required.
The following steps should be followed to do an A/D
conversion:
7. For next conversion, go to step 1 or step 2, as
required. The A/D conversion time per bit is
defined as TAD. A minimum wait of 2 TAD is
required before next acquisition starts.
1. Configure the A/D module:
• Configure analog pins, voltage reference and
digital I/O (ADCON1)
• Select A/D input channel (ADCON0)
• Select A/D acquisition time (ADCON2)
• Select A/D conversion clock (ADCON2)
• Turn on A/D module (ADCON0)
2. Configure A/D interrupt (if desired):
• Clear ADIF bit
• Set ADIE bit
• Set GIE bit
FIGURE 19-2:
ANALOG INPUT MODEL
VDD
Sampling
Switch
VT = 0.6V
ANx
SS
RIC ≤ 1k
RSS
RS
CPIN
5 pF
VAIN
ILEAKAGE
100 nA
CHOLD = 25 pF
VT = 0.6V
VSS
Legend: CPIN
= Input Capacitance
= Threshold Voltage
6V
5V
VDD 4V
VT
ILEAKAGE = Leakage Current at the pin due to
various junctions
3V
RIC
SS
= Interconnect Resistance
= Sampling Switch
2V
CHOLD
RSS
= Sample/Hold Capacitance (from DAC)
= Sampling Switch Resistance
1
2
3
4
Sampling Switch (kΩ)
© 2007 Microchip Technology Inc.
Preliminary
DS39774C-page 255
PIC18F85J11 FAMILY
To calculate the minimum acquisition time,
Equation 19-1 may be used. This equation assumes
that 1/2 LSb error is used (1024 steps for the A/D). The
1/2 LSb error is the maximum error allowed for the A/D
to meet its specified resolution.
19.1 A/D Acquisition Requirements
For the A/D converter to meet its specified accuracy,
the charge holding capacitor (CHOLD) must be allowed
to fully charge to the input channel voltage level. The
analog input model is shown in Figure 19-2. The
source impedance (RS) and the internal sampling
switch (RSS) impedance directly affect the time
required to charge the capacitor CHOLD. The sampling
switch (RSS) impedance varies over the device voltage
(VDD). The source impedance affects the offset voltage
at the analog input (due to pin leakage current). The
maximum recommended impedance for analog
sources is 2.5 kΩ. After the analog input channel is
selected (changed), the channel must be sampled for
at least the minimum acquisition time before starting a
conversion.
Equation 19-3 shows the calculation of the minimum
required acquisition time, TACQ. This calculation is
based on the following application system
assumptions:
CHOLD
Rs
Conversion Error
VDD
Temperature
=
=
≤
=
=
25 pF
2.5 kΩ
1/2 LSb
3V → Rss = 2 kΩ
85°C (system max.)
Note: When the conversion is started, the
holding capacitor is disconnected from the
input pin.
EQUATION 19-1: A/D ACQUISITION TIME
TACQ
=
Amplifier Settling Time + Holding Capacitor Charging Time + Temperature Coefficient
=
TAMP + TC + TCOFF
EQUATION 19-2: A/D MINIMUM CHARGING TIME
VHOLD
or
TC
=
=
(VREF – (VREF/2048)) • (1 – e(-TC/CHOLD(RIC + RSS + RS))
)
-(CHOLD)(RIC + RSS + RS) ln(1/2048)
EQUATION 19-3: CALCULATING THE MINIMUM REQUIRED ACQUISITION TIME
TACQ
TAMP
TCOFF
=
=
=
TAMP + TC + TCOFF
0.2 µs
(Temp – 25°C)(0.02 µs/°C)
(85°C – 25°C)(0.02 µs/°C)
1.2 µs
Temperature coefficient is only required for temperatures > 25°C. Below 25°C, TCOFF = 0 ms.
TC
=
-(CHOLD)(RIC + RSS + RS) ln(1/2048) µs
-(25 pF) (1 kΩ + 2 kΩ + 2.5 kΩ) ln(0.0004883) µs
1.05 µs
TACQ
=
0.2 µs + 1 µs + 1.2 µs
2.4 µs
DS39774C-page 256
Preliminary
© 2007 Microchip Technology Inc.
PIC18F85J11 FAMILY
TABLE 19-1: TAD vs. DEVICE OPERATING
FREQUENCIES
19.2 Selecting and Configuring
Automatic Acquisition Time
AD Clock Source (TAD)
Maximum
Device
Frequency
The ADCON2 register allows the user to select an
acquisition time that occurs each time the GO/DONE
bit is set.
Operation
ADCS2:ADCS0
2 TOSC
4 TOSC
8 TOSC
16 TOSC
32 TOSC
64 TOSC
RC(1)
000
100
001
101
010
110
x11
2.86 MHz
5.71 MHz
11.43 MHz
22.86 MHz
40.0 MHz
40.0 MHz
1.00 MHz(2)
When the GO/DONE bit is set, sampling is stopped and
a conversion begins. The user is responsible for ensur-
ing the required acquisition time has passed between
selecting the desired input channel and setting the
GO/DONE bit. This occurs when the ACQT2:ACQT0
bits (ADCON2<5:3>) remain in their Reset state (‘000’)
and is compatible with devices that do not offer
programmable acquisition times.
If desired, the ACQT bits can be set to select a
programmable acquisition time for the A/D module.
When the GO/DONE bit is set, the A/D module contin-
ues to sample the input for the selected acquisition
time, then automatically begins a conversion. Since the
acquisition time is programmed, there may be no need
to wait for an acquisition time between selecting a
channel and setting the GO/DONE bit.
Note 1: The RC source has a typical TAD time of
4 µs.
2: For device frequencies above 1 MHz, the
device must be in Sleep mode for the
entire conversion or the A/D accuracy may
be out of specification.
19.4 Configuring Analog Port Pins
In either case, when the conversion is completed, the
GO/DONE bit is cleared, the ADIF flag is set and the
A/D begins sampling the currently selected channel
again. If an acquisition time is programmed, there is
nothing to indicate if the acquisition time has ended or
if the conversion has begun.
The ADCON1, TRISA, TRISF and TRISH registers
control the operation of the A/D port pins. The port pins
needed as analog inputs must have their correspond-
ing TRIS bits set (input). If the TRIS bit is cleared
(output), the digital output level (VOH or VOL) will be
converted.
19.3 Selecting the A/D Conversion
Clock
The A/D operation is independent of the state of the
CHS3:CHS0 bits and the TRIS bits.
The A/D conversion time per bit is defined as TAD. The
A/D conversion requires 11 TAD per 10-bit conversion.
The source of the A/D conversion clock is software
selectable.
Note 1: When reading the PORT register, all pins
configured as analog input channels will
read as cleared (a low level). Pins config-
ured as digital inputs will convert an
analog input. Analog levels on a digitally
configured input will be accurately
converted.
There are seven possible options for TAD:
• 2 TOSC
• 4 TOSC
2: Analog levels on any pin defined as a
digital input may cause the digital input
buffer to consume current out of the
device’s specification limits.
• 8 TOSC
• 16 TOSC
• 32 TOSC
• 64 TOSC
• Internal RC Oscillator
For correct A/D conversions, the A/D conversion clock
(TAD) must be as short as possible but greater than the
minimum TAD (see parameter 130 in Table 25-24 for
more information).
Table 19-1 shows the resultant TAD times derived from
the device operating frequencies and the A/D clock
source selected.
© 2007 Microchip Technology Inc.
Preliminary
DS39774C-page 257
PIC18F85J11 FAMILY
19.5 A/D Conversions
19.6 Use of the CCP2 Trigger
Figure 19-3 shows the operation of the A/D converter
after the GO/DONE bit has been set and the
ACQT2:ACQT0 bits are cleared. A conversion is
started after the following instruction to allow entry into
Sleep mode before the conversion begins.
An A/D conversion can be started by the “Special Event
Trigger” of the CCP2 module. This requires that the
CCP2M3:CCP2M0 bits (CCP2CON<3:0>) be pro-
grammed as ‘1011’ and that the A/D module is enabled
(ADON bit is set). When the trigger occurs, the
GO/DONE bit will be set, starting the A/D acquisition
and conversion, and the Timer1 (or Timer3) counter will
be reset to zero. Timer1 (or Timer3) is reset to auto-
matically repeat the A/D acquisition period with minimal
software overhead (moving ADRESH/ADRESL to the
desired location). The appropriate analog input
channel must be selected and the minimum acquisition
period is either timed by the user, or an appropriate
TACQ time is selected before the Special Event Trigger
sets the GO/DONE bit (starts a conversion).
Figure 19-4 shows the operation of the A/D converter
after the GO/DONE bit has been set, the
ACQT2:ACQT0 bits have been set to ‘010’ and a
4 TAD acquisition time has been selected before the
conversion starts.
Clearing the GO/DONE bit during a conversion will
abort the current conversion. The A/D Result register
pair will NOT be updated with the partially completed
A/D
conversion
sample.
This
means
the
ADRESH:ADRESL registers will continue to contain
the value of the last completed conversion (or the last
value written to the ADRESH:ADRESL registers).
If the A/D module is not enabled (ADON is cleared), the
Special Event Trigger will be ignored by the A/D module
but will still reset the Timer1 (or Timer3) counter.
After the A/D conversion is completed or aborted, a
2 TAD wait is required before the next acquisition can be
started. After this wait, acquisition on the selected
channel is automatically started.
Note:
The GO/DONE bit should NOT be set in
the same instruction that turns on the A/D.
FIGURE 19-3:
A/D CONVERSION TAD CYCLES (ACQT2:ACQT0 = 000, TACQ = 0)
TCY – TAD
TAD6 TAD7 TAD8 TAD9 TAD10 TAD11
TAD1 TAD2 TAD3 TAD4 TAD5
b7
b6
b4
b1
b0
b9
b8
b5
b3
b2
Conversion starts
Holding capacitor is disconnected from analog input (typically 100 ns)
Set GO/DONE bit
Next Q4: ADRESH/ADRESL are loaded, GO/DONE bit is cleared,
ADIF bit is set, holding capacitor is connected to analog input.
FIGURE 19-4:
A/D CONVERSION TAD CYCLES (ACQT2:ACQT0 = 010, TACQ = 4 TAD)
TAD Cycles
TACQT Cycles
7
8
9
10
b1
11
b0
1
2
3
4
1
2
3
4
5
6
b7
b6
b3
b2
b8
b5
b4
b9
Automatic
Acquisition
Time
Conversion starts
(Holding capacitor is disconnected)
Set GO/DONE bit
(Holding capacitor continues
acquiring input)
Next Q4: ADRESH:ADRESL are loaded, GO/DONE bit is cleared,
ADIF bit is set, holding capacitor is reconnected to analog input.
DS39774C-page 258
Preliminary
© 2007 Microchip Technology Inc.
PIC18F85J11 FAMILY
If the A/D is expected to operate while the device is in
a power-managed mode, the ACQT2:ACQT0 and
ADCS2:ADCS0 bits in ADCON2 should be updated in
accordance with the power-managed mode clock that
will be used. After the power-managed mode is entered
(either of the power-managed Run modes), an A/D
acquisition or conversion may be started. Once an
acquisition or conversion is started, the device should
continue to be clocked by the same power-managed
mode clock source until the conversion has been com-
pleted. If desired, the device may be placed into the
corresponding power-managed Idle mode during the
conversion.
19.7 A/D Converter Calibration
The A/D converter in the PIC18F85J11 family of
devices includes a self-calibration feature which com-
pensates for any offset generated within the module.
The calibration process is automated and is initiated by
setting the ADCAL bit (ADCON0<7>). The next time
the GO/DONE bit is set, the module will perform a
“dummy” conversion (that is, with reading none of the
input channels) and store the resulting value internally
to compensate for offset. Thus, subsequent offsets will
be compensated.
The calibration process assumes that the device is in a
relatively steady-state operating condition. If A/D
calibration is used, it should be performed after each
device Reset or if there are other major changes in
operating conditions.
If the power-managed mode clock frequency is less
than 1 MHz, the A/D RC clock source should be
selected.
Operation in the Sleep mode requires the A/D RC clock
to be selected. If bits, ACQT2:ACQT0, are set to ‘000’
and a conversion is started, the conversion will be
delayed one instruction cycle to allow execution of the
SLEEPinstruction and entry to Sleep mode. The IDLEN
and SCS<1:0> bits in the OSCCON register must have
already been cleared prior to starting the conversion.
19.8 Operation in Power-Managed
Modes
The selection of the automatic acquisition time and A/D
conversion clock is determined in part by the clock
source and frequency while in a power-managed
mode.
TABLE 19-2: SUMMARY OF A/D REGISTERS
Reset
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Values
on Page
INTCON
PIR1
GIE/GIEH PEIE/GIEL TMR0IE
INT0IE
TX1IF
TX1IE
TX1IP
TX2IF
TX2IE
TX2IP
RBIE
SSPIF
SSPIE
SSPIP
—
TMR0IF
—
INT0IF
TMR2IF
TMR2IE
TMR2IP
CCP1IF
CCP1IE
CCP1IP
RBIF
TMR1IF
TMR1IE
TMR1IP
—
51
53
53
53
53
53
53
53
53
53
53
53
54
54
54
54
54
PSPIF
PSPIE
PSPIP
—
ADIF
ADIE
ADIP
—
RC1IF
RC1IE
RC1IP
RC2IF
RC2IE
RC2IP
PIE1
—
IPR1
—
PIR3
CCP2IF
CCP2IE
CCP2IP
PIE3
—
—
—
—
IPR3
—
—
—
—
ADRESH
ADRESL
ADCON0
ADCON1
ADCON2
CCP2CON
PORTA
TRISA
A/D Result Register High Byte
A/D Result Register Low Byte
ADCAL
—
—
—
CHS3
VCFG1
ACQT2
DC2B1
RA5
CHS2
VCFG0
ACQT1
CHS1
PCFG3
ACQT0
CHS0 GO/DONE ADON
PCFG2
ADCS2
PCFG1
ADCS1
PCFG0
ADCS0
ADFM
—
—
RA7(1)
—
RA6(1)
DC2B0 CCP2M3 CCP2M2 CCP2M1 CCP2M0
RA4
TRISA4
RF4
RA3
TRISA3
RF3
RA2
TRISA2
RF2
RA1
TRISA1
RF1
RA0
TRISA0
—
TRISA7(1) TRISA6(1) TRISA5
PORTF
TRISF
RF7
RF6
RF5
TRISF5
TRISF4
TRISF5
TRISF4
TRISF3
TRISF2
TRISF1
—
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used for A/D conversion.
Note 1: RA6/RA7 and their associated latch and direction bits are configured as port pins only when the internal
oscillator is selected as the default clock source (FOSC2 Configuration bit = 0); otherwise, they are
disabled and these bits read as ‘0’.
© 2007 Microchip Technology Inc.
Preliminary
DS39774C-page 259
PIC18F85J11 FAMILY
NOTES:
DS39774C-page 260
Preliminary
© 2007 Microchip Technology Inc.
PIC18F85J11 FAMILY
The CMCON register (Register 20-1) selects the
comparator input and output configuration. Block
diagrams of the various comparator configurations are
shown in Figure 20-1.
20.0 COMPARATOR MODULE
The analog comparator module contains two
comparators that can be configured in a variety of
ways. The inputs can be selected from the analog
inputs multiplexed with pins RF1 through RF6, as well
as the on-chip voltage reference (see Section 21.0
“Comparator Voltage Reference Module”). The digi-
tal outputs (normal or inverted) are available at the pin
level and can also be read through the control register.
REGISTER 20-1: CMCON: COMPARATOR MODULE CONTROL REGISTER
R-0
R-0
R/W-0
C2INV
R/W-0
C1INV
R/W-0
CIS
R/W-1
CM2
R/W-1
CM1
R/W-1
CM0
C2OUT
C1OUT
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
-n = Value at POR
bit 7
C2OUT: Comparator 2 Output bit
When C2INV = 0:
1= C2 VIN+ > C2 VIN-
0= C2 VIN+ < C2 VIN-
When C2INV = 1:
1= C2 VIN+ < C2 VIN-
0= C2 VIN+ > C2 VIN-
bit 6
C1OUT: Comparator 1 Output bit
When C1INV = 0:
1= C1 VIN+ > C1 VIN-
0= C1 VIN+ < C1 VIN-
When C1INV = 1:
1= C1 VIN+ < C1 VIN-
0= C1 VIN+ > C1 VIN-
bit 5
bit 4
bit 3
C2INV: Comparator 2 Output Inversion bit
1= C2 output inverted
0= C2 output not inverted
C1INV: Comparator 1 Output Inversion bit
1= C1 output inverted
0= C1 output not inverted
CIS: Comparator Input Switch bit
When CM2:CM0 = 110:
1= C1 VIN- connects to RF5/AN10/CVREF
C2 VIN- connects to RF3/AN8
0= C1 VIN- connects to RF6/AN11
C2 VIN- connects to RF4/AN9
bit 2-0
CM2:CM0: Comparator Mode bits
Figure 20-1 shows the Comparator modes and the CM2:CM0 bit settings.
© 2007 Microchip Technology Inc.
Preliminary
DS39774C-page 261
PIC18F85J11 FAMILY
mode is changed, the comparator output level may not
be valid for the specified mode change delay shown in
Section 25.0 “Electrical Characteristics”.
20.1 Comparator Configuration
There are eight modes of operation for the compara-
tors, shown in Figure 20-1. Bits CM2:CM0 of the
CMCON register are used to select these modes. The
TRISF register controls the data direction of the
comparator pins for each mode. If the Comparator
Note:
Comparator interrupts should be disabled
during Comparator mode change;
otherwise, a false interrupt may occur.
a
FIGURE 20-1:
COMPARATOR I/O OPERATING MODES
Comparator Outputs Disabled
CM2:CM0 = 000
Comparators Off (POR Default Value)
CM2:CM0 = 111
A
D
VIN-
VIN-
RF6/AN11
RF6/AN11
Off (Read as ‘0’)
Off (Read as ‘0’)
Off (Read as ‘0’)
Off (Read as ‘0’)
C1
C2
C1
C2
VIN+
VIN+
A
D
RF5/AN10/
CVREF
RF5/AN10/
CVREF
RF4/AN9
RF3/AN8
A
A
D
D
VIN-
VIN-
RF4/AN9
RF3/AN8
VIN+
VIN+
Two Independent Comparators
CM2:CM0 = 010
Two Independent Comparators with Outputs
CM2:CM0 = 011
A
A
VIN-
VIN-
RF6/AN11
RF6/AN11
C1OUT
C2OUT
C1OUT
C2OUT
C1
C2
C1
C2
VIN+
VIN+
A
A
RF5/AN10/
CVREF
RF5/AN10/
CVREF
RF2/AN7/C1OUT*
A
A
VIN-
RF4/AN9
RF3/AN8
A
A
RF4/AN9
RF3/AN8
VIN-
VIN+
VIN+
RF1/AN6/C2OUT*
Two Common Reference Comparators
CM2:CM0 = 100
Two Common Reference Comparators with Outputs
CM2:CM0 = 101
A
A
VIN-
VIN-
RF6/AN11
RF6/AN11
C1OUT
C2OUT
C1OUT
C1
C2
C1
VIN+
VIN+
A
A
RF5/AN10/
CVREF
RF5/AN10
CVREF
RF2/AN7/C1OUT*
A
D
VIN-
RF4/AN9
RF3/AN8
RF4/AN9
RF3/AN8
A
D
VIN-
VIN+
C2OUT
C2
VIN+
RF1/AN6/C2OUT*
Four Inputs Multiplexed to Two Comparators
CM2:CM0 = 110
One Independent Comparator with Output
CM2:CM0 = 001
A
RF6/AN11
A
A
VIN-
RF6/AN11
CIS = 0
CIS = 1
VIN-
A
C1OUT
C1
RF5/AN10/
CVREF
VIN+
RF5/AN10/
CVREF
C1OUT
C2OUT
C1
C2
VIN+
A
A
RF2/AN7/C1OUT*
RF4/AN9
RF3/AN8
VIN-
CIS = 0
CIS = 1
VIN+
D
VIN-
RF4/AN9
Off (Read as ‘0’)
C2
VIN+
D
RF3/AN8
CVREF
From VREF module
A = Analog Input, port reads zeros always
D = Digital Input
CIS (CMCON<3>) is the Comparator Input Switch
* Setting the TRISF<2:1> bits will disable the comparator outputs by configuring the pins as inputs.
DS39774C-page 262
Preliminary
© 2007 Microchip Technology Inc.
PIC18F85J11 FAMILY
20.3.2
INTERNAL REFERENCE SIGNAL
20.2 Comparator Operation
The comparator module also allows the selection of an
internally generated voltage reference from the
comparator voltage reference module. This module is
described in more detail in Section 21.0 “Comparator
Voltage Reference Module”.
A single comparator is shown in Figure 20-2, along with
the relationship between the analog input levels and
the digital output. When the analog input at VIN+ is less
than the analog input VIN-, the output of the comparator
is a digital low level. When the analog input at VIN+ is
greater than the analog input VIN-, the output of the
comparator is a digital high level. The shaded areas of
the output of the comparator in Figure 20-2 represent
the uncertainty due to input offsets and response time.
The internal reference is only available in the mode
where four inputs are multiplexed to two comparators
(CM2:CM0 = 110). In this mode, the internal voltage
reference is applied to the VIN+ pin of both
comparators.
20.3 Comparator Reference
20.4 Comparator Response Time
Depending on the comparator operating mode, either
an external or internal voltage reference may be used.
The analog signal present at VIN- is compared to the
signal at VIN+ and the digital output of the comparator
is adjusted accordingly (Figure 20-2).
Response time is the minimum time, after selecting a
new reference voltage or input source, before the
comparator output has a valid level. If the internal ref-
erence is changed, the maximum delay of the internal
voltage reference must be considered when using the
comparator outputs. Otherwise, the maximum delay of
the comparators should be used (see Section 25.0
“Electrical Characteristics”).
FIGURE 20-2:
SINGLE COMPARATOR
VIN+
VIN-
+
20.5 Comparator Outputs
Output
–
The comparator outputs are read through the CMCON
register. These bits are read-only. The comparator
outputs may also be directly output to the RF1 and RF2
I/O pins. When enabled, multiplexors in the output path
of the RF1 and RF2 pins will switch and the output of
each pin will be the unsynchronized output of the
comparator. The uncertainty of each of the
comparators is related to the input offset voltage and
the response time given in the specifications.
Figure 20-3 shows the comparator output block
diagram.
VIN-
VIN+
Output
The TRISF bits will still function as output enables/
disables for the RF1 and RF2 pins while in this mode.
The polarity of the comparator outputs can be changed
using the C2INV and C1INV bits (CMCON<5:4>).
20.3.1
EXTERNAL REFERENCE SIGNAL
Note 1: When reading the PORT register, all pins
configured as analog inputs will read as
‘0’. Pins configured as digital inputs will
convert an analog input according to the
Schmitt Trigger input specification.
When external voltage references are used, the
comparator module can be configured to have the com-
parators operate from the same or different reference
sources. However, threshold detector applications may
require the same reference. The reference signal must
be between VSS and VDD and can be applied to either
pin of the comparator(s).
2: Analog levels on any pin defined as a
digital input may cause the input buffer to
consume more current than is specified.
© 2007 Microchip Technology Inc.
Preliminary
DS39774C-page 263
PIC18F85J11 FAMILY
FIGURE 20-3:
COMPARATOR OUTPUT BLOCK DIAGRAM
Port pins
To RF1 or
RF2 pin
-
Bus
Data
D
Q
CxINV
Read CMCON
EN
Set
CMIF
bit
D
Q
EN
CL
From
Other
Comparator
Reset
20.6 Comparator Interrupts
20.7 Comparator Operation
During Sleep
The comparator interrupt flag is set whenever there is
a change in the output value of either comparator.
Software will need to maintain information about the
status of the output bits, as read from CMCON<7:6>, to
determine the actual change that occurred. The CMIF
bit (PIR2<6>) is the Comparator Interrupt Flag. The
CMIF bit must be reset by clearing it. Since it is also
possible to write a ‘1’ to this register, a simulated
interrupt may be initiated.
When a comparator is active and the device is placed
in Sleep mode, the comparator remains active and the
interrupt is functional if enabled. This interrupt will
wake-up the device from Sleep mode when enabled.
Each operational comparator will consume additional
current, as shown in the comparator specifications. To
minimize power consumption while in Sleep mode, turn
off the comparators (CM2:CM0 = 111) before entering
Sleep. If the device wakes up from Sleep, the contents
of the CMCON register are not affected.
Both the CMIE bit (PIE2<6>) and the PEIE bit
(INTCON<6>) must be set to enable the interrupt. In
addition, the GIE bit (INTCON<7>) must also be set. If
any of these bits are clear, the interrupt is not enabled,
though the CMIF bit will still be set if an interrupt
condition occurs.
20.8 Effects of a Reset
A device Reset forces the CMCON register to its Reset
state, causing the comparator modules to be turned off
(CM2:CM0 = 111). However, the input pins (RF3
through RF6) are configured as analog inputs by
default on device Reset. The I/O configuration for these
pins is determined by the setting of the PCFG3:PCFG0
bits (ADCON1<3:0>). Therefore, device current is
minimized when analog inputs are present at Reset
time.
Note:
If a change in the CMCON register
(C1OUT or C2OUT) should occur when a
read operation is being executed (start of
the Q2 cycle), then the CMIF (PIR2<6>)
interrupt flag may not get set.
The user, in the Interrupt Service Routine, can clear the
interrupt in the following manner:
a) Any read or write of CMCON will end the
mismatch condition.
b) Clear flag bit, CMIF.
A mismatch condition will continue to set flag bit, CMIF.
Reading CMCON will end the mismatch condition and
allow flag bit, CMIF, to be cleared.
DS39774C-page 264
Preliminary
© 2007 Microchip Technology Inc.
PIC18F85J11 FAMILY
range by more than 0.6V in either direction, one of the
diodes is forward biased and a latch-up condition may
occur. A maximum source impedance of 10 kΩ is
recommended for the analog sources. Any external
component connected to an analog input pin, such as
a capacitor or a Zener diode, should have very little
leakage current.
20.9 Analog Input Connection
Considerations
A simplified circuit for an analog input is shown in
Figure 20-4. Since the analog pins are connected to a
digital output, they have reverse biased diodes to VDD
and VSS. The analog input, therefore, must be between
VSS and VDD. If the input voltage deviates from this
FIGURE 20-4:
COMPARATOR ANALOG INPUT MODEL
VDD
VT = 0.6V
RIC
RS < 10k
AIN
Comparator
Input
ILEAKAGE
500 nA
CPIN
5 pF
VA
VT = 0.6V
VSS
Legend: CPIN
=
=
Input Capacitance
Threshold Voltage
VT
ILEAKAGE = Leakage Current at the pin due to various junctions
RIC
RS
VA
=
=
=
Interconnect Resistance
Source Impedance
Analog Voltage
TABLE 20-1: REGISTERS ASSOCIATED WITH COMPARATOR MODULE
Reset
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Values
on Page
INTCON
PIR2
GIE/GIEH PEIE/GIEL TMR0IE
INT0IE
—
RBIE
BCLIF
BCLIE
BCLIP
CIS
TMR0IF
LVDIF
LVDIE
LVDIP
CM2
INT0IF
TMR3IF
TMR3IE
TMR3IP
CM1
RBIF
—
51
53
53
53
53
53
54
54
54
OSCFIF
OSCFIE
OSCFIP
C2OUT
CVREN
RF7
CMIF
CMIE
—
—
PIE2
—
—
IPR2
CMIP
—
—
—
CMCON
CVRCON
PORTF
LATF
C1OUT
CVROE
RF6
C2INV
CVRR
RF5
C1INV
CVRSS
RF4
CM0
CVR0
—
CVR3
RF3
CVR2
RF2
CVR1
RF1
LATF7
LATF6
TRISF6
LATF5
TRISF5
LATF4
TRISF4
LATF3
TRISF3
LATF2
TRISF2
LATF1
TRISF1
—
TRISF
TRISF7
—
Legend: — = unimplemented, read as ‘0’. Shaded cells are unused by the comparator module.
© 2007 Microchip Technology Inc.
Preliminary
DS39774C-page 265
PIC18F85J11 FAMILY
NOTES:
DS39774C-page 266
Preliminary
© 2007 Microchip Technology Inc.
PIC18F85J11 FAMILY
The range to be used is selected by the CVRR bit
(CVRCON<5>). The primary difference between the
ranges is the size of the steps selected by the CVREF
Selection bits (CVR3:CVR0), with one range offering
finer resolution. The equations used to calculate the
output of the comparator voltage reference are as
follows:
21.0 COMPARATOR VOLTAGE
REFERENCE MODULE
The comparator voltage reference is a 16-tap resistor
ladder network that provides a selectable reference
voltage. Although its primary purpose is to provide a
reference for the analog comparators, it may also be
used independently of them.
If CVRR = 1:
CVREF = ((CVR3:CVR0)/24) x (CVRSRC)
A block diagram of the module is shown in Figure 21-1.
The resistor ladder is segmented to provide two ranges
of CVREF values and has a power-down function to
conserve power when the reference is not being used.
The module’s supply reference can be provided from
either device VDD/VSS or an external voltage reference.
If CVRR = 0:
CVREF = (CVRSRC/4) + ((CVR3:CVR0)/32) x
(CVRSRC)
The comparator reference supply voltage can come
from either VDD and VSS, or the external VREF+ and
VREF- that are multiplexed with RA2 and RA3. The
voltage source is selected by the CVRSS bit
(CVRCON<4>).
21.1 Configuring the Comparator
Voltage Reference
The comparator voltage reference module is controlled
through the CVRCON register (Register 21-1). The
comparator voltage reference provides two ranges of
output voltage, each with 16 distinct levels.
The settling time of the comparator voltage reference
must be considered when changing the CVREF
output (see Table 25-3 in Section 25.0 “Electrical
Characteristics”).
REGISTER 21-1: CVRCON: COMPARATOR VOLTAGE REFERENCE CONTROL REGISTER
R/W-0
R/W-0
CVROE(1)
R/W-0
CVRR
R/W-0
R/W-0
CVR3
R/W-0
CVR2
R/W-0
CVR1
R/W-0
CVR0
CVREN
CVRSS
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7
bit 6
bit 5
bit 4
bit 3-0
CVREN: Comparator Voltage Reference Enable bit
1= CVREF circuit powered on
0= CVREF circuit powered down
CVROE: Comparator VREF Output Enable bit(1)
1= CVREF voltage level is also output on the RF5/AN10/CVREF pin
0= CVREF voltage is disconnected from the RF5/AN10/CVREF pin
CVRR: Comparator VREF Range Selection bit
1= 0 to 0.667 CVRSRC, with CVRSRC/24 step size (low range)
0= 0.25 CVRSRC to 0.75 CVRSRC, with CVRSRC/32 step size (high range)
CVRSS: Comparator VREF Source Selection bit
1= Comparator reference source, CVRSRC = (VREF+) – (VREF-)
0= Comparator reference source, CVRSRC = VDD – VSS
CVR3:CVR0: Comparator VREF Value Selection bits (0 ≤ (CVR3:CVR0) ≤ 15)
When CVRR = 1:
CVREF = ((CVR3:CVR0)/24) • (CVRSRC)
When CVRR = 0:
CVREF = (CVRSRC/4) + ((CVR3:CVR0)/32) • (CVRSRC)
Note 1: CVROE overrides the TRISF<5> bit setting.
© 2007 Microchip Technology Inc.
Preliminary
DS39774C-page 267
PIC18F85J11 FAMILY
FIGURE 21-1:
COMPARATOR VOLTAGE REFERENCE BLOCK DIAGRAM
CVRSS = 1
VREF+
VDD
8R
CVRSS = 0
CVR3:CVR0
R
CVREN
R
R
R
16 Steps
CVREF
R
R
R
CVRR
VREF-
8R
CVRSS = 1
CVRSS = 0
21.2 Comparator Voltage Reference
Accuracy/Error
21.4 Effects of a Reset
A device Reset disables the comparator voltage
reference by clearing bit, CVREN (CVRCON<7>). This
Reset also disconnects the reference from the RA2 pin
by clearing bit, CVROE (CVRCON<6>) and selects the
high-voltage range by clearing bit, CVRR
(CVRCON<5>). The CVR<3:0> value select bits are
also cleared.
The full range of comparator voltage reference cannot
be realized due to the construction of the module. The
transistors on the top and bottom of the resistor ladder
network (Figure 21-1) keep CVREF from approaching the
reference source rails. The voltage reference is derived
from the reference source; therefore, the CVREF output
changes with fluctuations in that source. The tested
absolute accuracy of the voltage reference can be found
in Section 25.0 “Electrical Characteristics”.
21.5 Connection Considerations
The comparator voltage reference module operates
independently of the comparator module. The output of
the reference generator may be connected to the RF5
pin if the CVROE bit is set. Enabling the voltage refer-
ence output onto RA2 when it is configured as a digital
input will increase current consumption. Connecting
RF5 as a digital output with CVRSS enabled will also
increase current consumption.
21.3 Operation During Sleep
When the device wakes up from Sleep through an
interrupt or a Watchdog Timer time-out, the contents of
the CVRCON register are not affected. To minimize
current consumption in Sleep mode, the comparator
voltage reference should be disabled.
The RF5 pin can be used as a simple D/A output with
limited drive capability. Due to the limited current drive
capability, a buffer must be used on the comparator volt-
age reference output for external connections to VREF.
Figure 21-2 shows an example buffering technique.
DS39774C-page 268
Preliminary
© 2007 Microchip Technology Inc.
PIC18F85J11 FAMILY
FIGURE 21-2:
COMPARATOR VOLTAGE REFERENCE OUTPUT BUFFER EXAMPLE
PIC18F85J11
(1)
R
CVREF
Module
+
–
CVREF Output
RF5
Voltage
Reference
Output
Impedance
Note 1: R is dependent upon the Comparator Voltage Reference bits, CVRCON<5> and CVRCON<3:0>.
TABLE 21-1: REGISTERS ASSOCIATED WITH COMPARATOR VOLTAGE REFERENCE
Reset
Values
on page
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
CVRCON
CMCON
TRISF
CVREN
C2OUT
TRISF7
CVROE
C1OUT
TRISF6
CVRR
C2INV
CVRSS
C1INV
CVR3
CIS
CVR2
CM2
CVR1
CM1
CVR0
CM0
—
53
53
54
TRISF5 TRISF4
TRISF3
TRISF2
TRISF1
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used with the comparator voltage reference.
© 2007 Microchip Technology Inc.
Preliminary
DS39774C-page 269
PIC18F85J11 FAMILY
NOTES:
DS39774C-page 270
Preliminary
© 2007 Microchip Technology Inc.
PIC18F85J11 FAMILY
22.1.1
CONSIDERATIONS FOR
CONFIGURING THE PIC18F85J11
FAMILY DEVICES
22.0 SPECIAL FEATURES OF THE
CPU
PIC18F85J11 family devices include several features
intended to maximize reliability and minimize cost
through elimination of external components. These are:
Devices of the PIC18F85J11 family do not use persistent
memory registers to store configuration information. The
configuration bytes are implemented as volatile memory
which means that configuration data must be
programmed each time the device is powered up.
• Oscillator Selection
• Resets:
- Power-on Reset (POR)
- Power-up Timer (PWRT)
- Oscillator Start-up Timer (OST)
- Brown-out Reset (BOR)
• Interrupts
Configuration data is stored in the four words at the top
of the on-chip program memory space, known as the
Flash Configuration Words. It is stored in program
memory in the same order shown in Table 22-2, with
CONFIG1L at the lowest address and CONFIG3H at
the highest. The data is automatically loaded in the
proper Configuration registers during device power-up.
• Watchdog Timer (WDT)
• Fail-Safe Clock Monitor
• Two-Speed Start-up
• Code Protection
When creating applications for these devices, users
should always specifically allocate the location of the
Flash Configuration Word for configuration data. This is
to make certain that program code is not stored in this
address when the code is compiled.
• In-Circuit Serial Programming
The oscillator can be configured for the application
depending on frequency, power, accuracy and cost. All
of the options are discussed in detail in Section 2.0
“Oscillator Configurations”.
The volatile memory cells used for the Configuration
bits always reset to ‘1’ on Power-on Resets. For all
other types of Reset events, the previously
programmed values are maintained and used without
reloading from program memory.
A complete discussion of device Resets and interrupts
is available in previous sections of this data sheet.
The four Most Significant bits of CONFIG1H,
CONFIG2H and CONFIG3H in program memory
should also be ‘1111’. This makes these Configuration
Words appear to be NOP instructions in the remote
event that their locations are ever executed by
accident. Since Configuration bits are not implemented
in the corresponding locations, writing ‘1’s to these
locations has no effect on device operation.
In addition to their Power-up and Oscillator Start-up
Timers provided for Resets, the PIC18F85J11 family of
devices have a configurable Watchdog Timer which is
controlled in software.
The inclusion of an internal RC oscillator also provides
the additional benefits of a Fail-Safe Clock Monitor
(FSCM) and Two-Speed Start-up. FSCM provides for
background monitoring of the peripheral clock and
automatic switchover in the event of its failure.
Two-Speed Start-up enables code to be executed
almost immediately on start-up while the primary clock
source completes its start-up delays.
To prevent inadvertent configuration changes during
code execution, all programmable Configuration bits
are write-once. After a bit is initially programmed during
a power cycle, it cannot be written to again. Changing
a device configuration requires that power to the device
be cycled.
All of these features are enabled and configured by
setting the appropriate Configuration register bits.
TABLE 22-1: MAPPING OF THE FLASH
CONFIGURATION WORDS TO
THE CONFIGURATION
22.1 Configuration Bits
The Configuration bits can be programmed (read as
‘0’), or left unprogrammed (read as ‘1’), to select
various device configurations. These bits are mapped
starting at program memory location 300000h. A
complete list is shown in Table 22-2. A detailed
explanation of the various bit functions is provided in
Register 22-1 through Register 22-6.
REGISTERS
Configuration
Configuration
Byte
Code Space
Address
Register
Address
CONFIG1L
CONFIG1H
CONFIG2L
CONFIG2H
CONFIG3L
CONFIG3H
XXXF8h
XXXF9h
XXXFAh
XXXFBh
XXXFCh
XXXFDh
300000h
300001h
300002h
300003h
300004h
300005h
© 2007 Microchip Technology Inc.
Preliminary
DS39774C-page 271
PIC18F85J11 FAMILY
TABLE 22-2: CONFIGURATION BITS AND DEVICE IDs
Default/
Unprogrammed
Value(1)
File Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
300000h CONFIG1L
300001h CONFIG1H
300002h CONFIG2L
300003h CONFIG2H
300004h CONFIG3L(4)
300005h CONFIG3H
3FFFFEh DEVID1
DEBUG
XINST
STVREN
—
—
—
—
—
WDTEN
—
111- ---1
---- 01--
11-- -111
(2)
(2)
(2)
(2)
(3)
—
—
—
—
—
CP0
IESO
FCMEN
—
—
—
FOSC2
FOSC1
FOSC0
(2)
(2)
(2)
(2)
—
—
—
—
WDTPS3 WDTPS2 WDTPS1 WDTPS0 ---- 1111
WAIT
BW
EMB1
EMB0
EASHFT
—
—
—
—
—
1111 1---
(2)
(2)
(2)
(2)
—
—
—
—
—
CCP2MX ---- ---1
(5)
(5)
DEV2
DEV1
DEV9
DEV0
DEV8
REV4
DEV7
REV3
DEV6
REV2
DEV5
REV1
DEV4
REV0
DEV3
xxxx xxxx
0000 10x1
3FFFFFh DEVID2
DEV10
Legend:
x= unknown, – = unimplemented. Shaded cells are unimplemented, read as ‘0’.
Note 1: Values reflect the unprogrammed state as received from the factory and following Power-on Resets. In all other Reset
states, the configuration bytes maintain their previously programmed states.
2: The value of these bits in program memory should always be ‘1’. This ensures that the location is executed as a NOPif it
is accidentally executed.
3: This bit should always be maintained as ‘0’.
4: CONFIG3L is implemented in 80-pin devices only.
5: See Register 22-7 and Register 22-8 for DEVID values. These registers are read-only and cannot be programmed by
the user.
DS39774C-page 272
Preliminary
© 2007 Microchip Technology Inc.
PIC18F85J11 FAMILY
REGISTER 22-1: CONFIG1L: CONFIGURATION REGISTER 1 LOW (BYTE ADDRESS 300000h)
R/WO-1
DEBUG
R/WO-1
XINST
R/WO-1
U-0
—
U-0
—
U-0
—
U-0
—
R/WO-1
WDTEN
STVREN
bit 7
bit 0
Legend:
R = Readable bit
WO = Write-Once bit
U = Unimplemented bit, read as ‘0’
-n = Value when device is unprogrammed
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7
bit 6
bit 5
DEBUG: Background Debugger Enable bit
1= Background debugger disabled; RB6 and RB7 configured as general purpose I/O pins
0= Background debugger enabled; RB6 and RB7 are dedicated to in-circuit debug
XINST: Extended Instruction Set Enable bit
1= Instruction set extension and Indexed Addressing mode enabled
0= Instruction set extension and Indexed Addressing mode disabled (Legacy mode)
STVREN: Stack Overflow/Underflow Reset Enable bit
1= Reset on stack overflow/underflow enabled
0= Reset on stack overflow/underflow disabled
bit 4-1
bit 0
Unimplemented: Read as ‘0’
WDTEN: Watchdog Timer Enable bit
1= WDT enabled
0= WDT disabled (control is placed on SWDTEN bit)
REGISTER 22-2: CONFIG1H: CONFIGURATION REGISTER 1 HIGH (BYTE ADDRESS 300001h)
U-0
U-0
U-0
U-0
U-0
R/WO-1
CP0
U-0
—
U-0
—
(1)
(1)
(1)
(1)
(2)
—
—
—
—
—
bit 7
bit 0
Legend:
R = Readable bit
WO = Write-Once bit
U = Unimplemented bit, read as ‘0’
‘1’ = Bit is set ‘0’ = Bit is cleared
-n = Value when device is unprogrammed
bit 7-4
bit 3
Unimplemented: Read as ‘1’(1)
Unimplemented: Read as ‘0’(2)
CP0: Code Protection bit
bit 2
1= Program memory is not code-protected
0= Program memory is code-protected
bit 1-0
Unimplemented: Read as ‘0’
Note 1: The value of these bits in program memory should always be ‘1’. This ensures that the location is
executed as a NOPif it is accidentally executed.
2: This bit should always be maintained as ‘0’.
© 2007 Microchip Technology Inc.
Preliminary
DS39774C-page 273
PIC18F85J11 FAMILY
REGISTER 22-3: CONFIG2L: CONFIGURATION REGISTER 2 LOW (BYTE ADDRESS 300002h)
R/WO-1
IESO
R/WO-1
FCMEN
U-0
—
U-0
—
U-0
—
R/WO-1
FOSC2
R/WO-1
FOSC1
R/WO-1
FOSC0
bit 7
bit 0
Legend:
R = Readable bit
WO = Write-Once bit
U = Unimplemented bit, read as ‘0’
‘1’ = Bit is set ‘0’ = Bit is cleared
-n = Value when device is unprogrammed
bit 7
bit 6
IESO: Two-Speed Start-up (Internal/External Oscillator Switchover) Control bit
1= Two-Speed Start-up enabled
0= Two-Speed Start-up disabled
FCMEN: Fail-Safe Clock Monitor Enable bit
1= Fail-Safe Clock Monitor enabled
0= Fail-Safe Clock Monitor disabled
bit 5-3
bit 2-0
Unimplemented: Read as ‘0’
FOSC2:FOSC0: Oscillator Selection bits
111= OSC1/OSC2 as primary; EC oscillator with CLKO function and software controlled
PLL (ECPLL)
110= OSC1/OSC2 as primary; EC oscillator with CLKO function (EC)
101= OSC1/OSC2 as primary; HS oscillator with software controlled PLL (HSPLL)
100= OSC1/OSC2 as primary; HS oscillator (HS)
011= INTOSC with CLKO as primary; port function on RA7; EC oscillator with CLKO function and
software controlled PLL (ECPLL)
010= INTOSC with CLKO as primary; port function on RA7; EC oscillator with CLKO function
001= INTOSC as primary with port function on RA6/RA7; HS oscillator with software controlled
PLL (HSPLL)
000= INTOSC as primary with port function on RA6/RA7; HS oscillator (HS)
DS39774C-page 274
Preliminary
© 2007 Microchip Technology Inc.
PIC18F85J11 FAMILY
REGISTER 22-4:
CONFIG2H: CONFIGURATION REGISTER 2 HIGH (BYTE ADDRESS 300003h)
U-0
U-0
U-0
U-0
R/WO-1
R/WO-1
R/WO-1
R/WO-1
(1)
(1)
(1)
(1)
—
—
—
—
WDTPS3
WDTPS2
WDTPS1
WDTPS0
bit 7
bit 0
Legend:
R = Readable bit
WO = Write-Once bit
U = Unimplemented bit, read as ‘0’
‘1’ = Bit is set ‘0’ = Bit is cleared
-n = Value when device is unprogrammed
bit 7-4
bit 3-0
Unimplemented: Read as ‘1’(1)
WDTPS3:WDTPS0: Watchdog Timer Postscale Select bits
1111= 1:32,768
1110= 1:16,384
1101= 1:8,192
1100= 1:4,096
1011= 1:2,048
1010= 1:1,024
1001= 1:512
1000= 1:256
0111= 1:128
0110= 1:64
0101= 1:32
0100= 1:16
0011= 1:8
0010= 1:4
0001= 1:2
0000= 1:1
Note 1: The value of these bits in program memory should always be ‘1’. This ensures that the location is
executed as a NOPif it is accidentally executed.
© 2007 Microchip Technology Inc.
Preliminary
DS39774C-page 275
PIC18F85J11 FAMILY
REGISTER 22-5: CONFIG3L: CONFIGURATION REGISTER 3 LOW (BYTE ADDRESS 300004h)(1)
R/WO-1
WAIT
R/WO-1
BW
R/WO-1
EMB1
R/WO-1
EMB0
R/WO-1
EASHFT
U-0
—
U-0
—
U-0
—
bit 7
bit 0
Legend:
R = Readable bit
WO = Write-Once bit
U = Unimplemented bit, read as ‘0’
‘1’ = Bit is set ‘0’ = Bit is cleared
-n = Value when device is unprogrammed
bit 7
WAIT: External Bus Wait Enable bit
1= Wait selections from MEMCON.WAIT<1:0> are unavailable and the device will not wait
0= Wait programmed by MEMCON.WAIT<1:0>
bit 6
BW: Data Bus Width Select bit
1= 16-Bit External Bus mode
0= 8-Bit External Bus mode
bit 5-4
EMB1:EMB0: External Memory Bus Configuration bits
00= Extended Microcontroller mode – 20-Bit Address mode
01= Extended Microcontroller mode – 16-Bit Address mode
10= Extended Microcontroller mode – 12-Bit Address mode
11= Microcontroller mode – external bus disabled
bit 3
EASHFT: External Address Bus Shift Enable bit
1= Address shifting enabled – external address bus is shifted to start at 000000h
0= Address shifting disabled – external address bus reflects the PC value
bit 2-0
Unimplemented: Read as ‘0’
Note 1: CONFIG3L and its associated bits are implemented only in 80-pin devices.
REGISTER 22-6: CONFIG3H: CONFIGURATION REGISTER 3 HIGH (BYTE ADDRESS 300005h)
U-0
U-0
U-0
U-0
U-0
—
U-0
—
U-0
—
R/WO-1
(1)
(1)
(1)
(1)
—
—
—
—
CCP2MX
bit 7
bit 0
Legend:
R = Readable bit
WO = Write-Once bit
U = Unimplemented bit, read as ‘0’
‘1’ = Bit is set ‘0’ = Bit is cleared
-n = Value when device is unprogrammed
bit 7-1
bit 0
Unimplemented: Read as ‘1’(1)
CCP2MX: CCP2 MUX bit
1= CCP2 is multiplexed with RC1
0= CCP2 is multiplexed with RE7 in Microcontroller mode (all devices) or with RB3 in Extended
Microcontroller mode (80-pin devices only)
Note 1: The value of these bits in program memory should always be ‘1’. This ensures that the location is
executed as a NOPif it is accidentally executed.
DS39774C-page 276
Preliminary
© 2007 Microchip Technology Inc.
PIC18F85J11 FAMILY
REGISTER 22-7: DEVID1: DEVICE ID REGISTER 1 FOR PIC18F85J11 FAMILY DEVICES
R
R
R
R
R
R
R
R
DEV2
DEV1
DEV0
REV4
REV3
REV2
REV1
REV0
bit 7
bit 0
Legend:
R = Read-only bit
bit 7-5
DEV2:DEV0: Device ID bits
111= PIC18F85J11
101= PIC18F84J11
100= PIC18F83J11
011= PIC18F65J11
001= PIC18F64J11
000= PIC18F63J11
bit 4-0
REV4:REV0: Revision ID bits
These bits are used to indicate the device revision.
REGISTER 22-8: DEVID2: DEVICE ID REGISTER 2 FOR PIC18F85J11 FAMILY DEVICES
R
R
R
R
R
R
R
R
DEV10(1)
DEV9(1)
DEV8(1)
DEV7(1)
DEV6(1)
DEV5(1)
DEV4(1)
DEV3(1)
bit 7
bit 0
Legend:
R = Read-only bit
bit 7-0
DEV10:DEV3: Device ID bits(1)
These bits are used with the DEV2:DEV0 bits in the Device ID Register 1 to identify the part number.
0011 1001 = PIC18F6XJ11/8XJ11 devices
Note 1: The values for DEV10:DEV3 may be shared with other device families. The specific device is always
identified by using the entire DEV10:DEV0 bit sequence.
© 2007 Microchip Technology Inc.
Preliminary
DS39774C-page 277
PIC18F85J11 FAMILY
22.2 Watchdog Timer (WDT)
Note 1: The CLRWDT and SLEEP instructions
clear the WDT and postscaler counts
when executed.
For PIC18F85J11 family devices, the WDT is driven by
the INTRC oscillator. When the WDT is enabled, the
clock source is also enabled. The nominal WDT period is
4 ms and has the same stability as the INTRC oscillator.
2: When a CLRWDTinstruction is executed,
the postscaler count will be cleared.
The 4 ms period of the WDT is multiplied by a 16-bit
postscaler. Any output of the WDT postscaler is
selected by a multiplexor, controlled by the WDTPS bits
in Configuration Register 2H. Available periods range
from 4 ms to 131.072 seconds (2.18 minutes). The
WDT and postscaler are cleared whenever a SLEEPor
CLRWDT instruction is executed, or a clock failure
(primary or Timer1 oscillator) has occurred.
22.2.1
CONTROL REGISTER
The WDTCON register (Register 22-9) is a readable
and writable register. The SWDTEN bit enables or dis-
ables WDT operation. This allows software to override
the WDTEN Configuration bit and enable the WDT only
if it has been disabled by the Configuration bit.
FIGURE 22-1:
WDT BLOCK DIAGRAM
Enable WDT
SWDTEN
INTRC Control
WDT Counter
Wake-up from
Power-Managed
Modes
÷128
INTRC Oscillator
WDT
Reset
Reset
CLRWDT
All Device Resets
Programmable Postscaler
1:1 to 1:32,768
WDT
4
WDTPS3:WDTPS0
Sleep
REGISTER 22-9: WDTCON: WATCHDOG TIMER CONTROL REGISTER
R/W-0
REGSLP(1)
bit 7
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
R/W-0
SWDTEN(2)
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7
REGSLP: Voltage Regulator Low-Power Operation Enable bit
1= On-chip regulator enters low-power operation when device enters Sleep mode
0= On-chip regulator continues to operate normally in Sleep mode
bit 6-1
bit 0
Unimplemented: Read as ‘0’
SWDTEN: Software Controlled Watchdog Timer Enable bit(1)
1= Watchdog Timer is on
0= Watchdog Timer is off
Note 1: The REGSLP bit is automatically cleared when a Low-Voltage Detect condition occurs.
2: This bit has no effect if the Configuration bit, WDTEN, is enabled.
TABLE 22-3: SUMMARY OF WATCHDOG TIMER REGISTERS
ResetValues
on Page
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
RCON
WDTCON
IPEN
—
—
CM
—
RI
—
TO
—
PD
—
POR
—
BOR
52
52
REGSLP
SWDTEN
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the Watchdog Timer.
DS39774C-page 278
Preliminary
© 2007 Microchip Technology Inc.
PIC18F85J11 FAMILY
FIGURE 22-2:
CONNECTIONS FOR THE
ON-CHIP REGULATOR
22.3 On-Chip Voltage Regulator
All of the PIC18F85J11 family devices power their core
digital logic at a nominal 2.5V. For designs that are
required to operate at a higher typical voltage, such as
3.3V, all devices in the PIC18F85J11 family incorporate
an on-chip regulator that allows the device to run its
core logic from VDD.
Regulator Enabled (ENVREG tied to VDD):
3.3V
PIC18F85J11
VDD
ENVREG
VDDCORE/VCAP
VSS
The regulator is controlled by the ENVREG pin. Tying
VDD to the pin enables the regulator, which in turn, pro-
vides power to the core from the other VDD pins. When
the regulator is enabled, a low-ESR filter capacitor must
be connected to the VDDCORE/VCAP pin (Figure 22-2).
This helps to maintain the stability of the regulator. The
recommended value for the filter capacitor is provided in
Section 25.3 “DC Characteristics: PIC18F85J11
Family (Industrial)”.
CF
Regulator Disabled (ENVREG tied to ground):
(1)
(1)
2.5V
3.3V
If ENVREG is tied to VSS, the regulator is disabled. In
this case, separate power for the core logic at a nominal
2.5V must be supplied to the device on the
VDDCORE/VCAP pin to run the I/O pins at higher voltage
levels, typically 3.3V. Alternatively, the VDDCORE/VCAP
and VDD pins can be tied together to operate at a lower
nominal voltage. Refer to Figure 22-2 for possible
configurations.
PIC18F85J11
VDD
ENVREG
VDDCORE/VCAP
VSS
22.3.1
VOLTAGE REGULATION AND
LOW-VOLTAGE DETECTION
Regulator Disabled (VDD tied to VDDCORE):
When it is enabled, the on-chip regulator provides a
constant voltage of 2.5V nominal to the digital core
logic. The regulator can provide this level from a VDD of
about 2.5V, all the way up to the device’s VDDMAX. It
does not have the capability to boost VDD levels below
2.5V.
(1)
2.5V
PIC18F85J11
VDD
ENVREG
VDDCORE/VCAP
VSS
In order to prevent “brown-out” conditions, the regulator
enters Tracking mode when the voltage drops too low
for the regulator. In Tracking mode, the regulator output
follows VDD, with a typical voltage drop of 100 mV.
The on-chip regulator includes a simple Low-Voltage
Detect (LVD) circuit. If VDD drops too low to maintain
approximately 2.45V on VDDCORE, the circuit sets the
Low-Voltage Detect Interrupt Flag, LVDIF (PIR2<2>),
and clears the REGSLP (WDTCON<7>) bit if it was set.
Note 1: These are typical operating voltages. Refer
to Section 25.1 “DC Characteristics:
Supply Voltage” for the full operating
ranges of VDD and VDDCORE.
This can be used to generate an interrupt and put the
application into a low-power operational mode or to
trigger an orderly shutdown. Low-Voltage Detection is
only available when the regulator is enabled.
© 2007 Microchip Technology Inc.
Preliminary
DS39774C-page 279
PIC18F85J11 FAMILY
22.3.2
ON-CHIP REGULATOR AND BOR
22.3.4
OPERATION IN SLEEP MODE
When the on-chip regulator is enabled, PIC18F85J11
family devices also have a simple Brown-out Reset
capability. If the voltage supplied to the regulator falls to
a level that is inadequate to maintain a regulated output
for full-speed operation, the regulator Reset circuitry
will generate a Brown-out Reset. This event is captured
by the BOR flag bit (RCON<0>).
When enabled, the on-chip regulator always consumes
a small incremental amount of current over IDD. This
includes when the device is in Sleep mode, even
though the core digital logic does not require power. To
provide additional savings in applications where power
resources are critical, the regulator can be configured
to automatically disable itself whenever the device
goes into Sleep mode. This feature is controlled by the
REGSLP bit (WDTCON<7>). Setting this bit disables
the regulator in Sleep mode and reduces its current
consumption to a minimum.
The operation of the Brown-out Reset is described in
more detail in Section 4.4 “Brown-out Reset (BOR)”
and Section 4.4.1 “Detecting BOR”.
22.3.3
POWER-UP REQUIREMENTS
Substantial Sleep-mode power savings can be
obtained by setting the REGSLP bit, but this will
increase device wake-up time to ensure the regulator
has enough time to stabilize.
The on-chip regulator is designed to meet the power-up
requirements for the device. If the application does not
use the regulator, then strict power-up conditions must
be adhered to. While powering up, VDDCORE must
never exceed VDD by 0.3 volts.
The REGSLP bit is cleared automatically by hardware
when a Low-Voltage Detect condition occurs. The
REGSLP bit can be set again in software, which would
keep the voltage regulator in Low-Power mode. This is
not recommended, however, if any write operations to
the Flash will be performed.
DS39774C-page 280
Preliminary
© 2007 Microchip Technology Inc.
PIC18F85J11 FAMILY
22.4.1
SPECIAL CONSIDERATIONS FOR
USING TWO-SPEED START-UP
22.4 Two-Speed Start-up
The Two-Speed Start-up feature helps to minimize the
latency period, from oscillator start-up to code execu-
tion, by allowing the microcontroller to use the INTRC
oscillator as a clock source until the primary clock
source is available. It is enabled by setting the IESO
Configuration bit.
While using the INTRC oscillator in Two-Speed
Start-up, the device still obeys the normal command
sequences for entering power-managed modes,
including serial SLEEP instructions (refer to
Section 3.1.4 “Multiple Sleep Commands”). In
practice, this means that user code can change the
SCS1:SCS0 bit settings or issue SLEEP instructions
before the OST times out. This would allow an applica-
tion to briefly wake-up, perform routine “housekeeping”
tasks and return to Sleep before the device starts to
operate from the primary oscillator.
Two-Speed Start-up should be enabled only if the
primary oscillator mode is HS or HSPLL
(Crystal-Based) modes. Since the EC and ECPLL
modes do not require an Oscillator Start-up Timer
delay, Two-Speed Start-up should be disabled.
When enabled, Resets and wake-ups from Sleep mode
cause the device to configure itself to run from the inter-
nal oscillator block as the clock source, following the
time-out of the Power-up Timer, after a Power-on Reset
is enabled. This allows almost immediate code
execution while the primary oscillator starts and the
OST is running. Once the OST times out, the device
automatically switches to PRI_RUN mode.
User code can also check if the primary clock source is
currently providing the device clocking by checking the
status of the OSTS bit (OSCCON<3>). If the bit is set,
the primary oscillator is providing the clock. Otherwise,
the internal oscillator block is providing the clock during
wake-up from Reset or Sleep mode.
In all other power-managed modes, Two-Speed
Start-up is not used. The device will be clocked by the
currently selected clock source until the primary clock
source becomes available. The setting of the IESO bit
is ignored.
FIGURE 22-3:
TIMING TRANSITION FOR TWO-SPEED START-UP (INTRC TO HSPLL)
Q4
Q1
Q2 Q3 Q4 Q1 Q2
Q3
Q3
Q1
Q2
INTRC
OSC1
(1)
TOST
(1)
TPLL
1
2
n-1
n
PLL Clock
Output
Clock
Transition
CPU Clock
Peripheral
Clock
Program
Counter
PC + 4
PC + 6
PC
PC + 2
Wake from Interrupt Event
OSTS bit Set
Note 1: TOST = 1024 TOSC; TPLL = 2 ms (approx). These intervals are not shown to scale.
© 2007 Microchip Technology Inc.
Preliminary
DS39774C-page 281
PIC18F85J11 FAMILY
During switchover, the postscaler frequency from the
internal oscillator block may not be sufficiently stable
for timing sensitive applications. In these cases, it may
be desirable to select another clock configuration and
enter an alternate power-managed mode. This can be
done to attempt a partial recovery or execute a
controlled shutdown. See Section 3.1.4 “Multiple
Sleep Commands” and Section 22.4.1 “Special
Considerations for Using Two-Speed Start-up” for
more details.
22.5 Fail-Safe Clock Monitor
The Fail-Safe Clock Monitor (FSCM) allows the
microcontroller to continue operation in the event of an
external oscillator failure by automatically switching the
device clock to the internal oscillator block. The FSCM
function is enabled by setting the FCMEN Configuration
bit.
When FSCM is enabled, the INTRC oscillator runs at
all times to monitor clocks to peripherals and provides
a backup clock in the event of a clock failure. Clock
monitoring (shown in Figure 22-4) is accomplished by
creating a sample clock signal which is the INTRC out-
put divided by 64. This allows ample time between
FSCM sample clocks for a peripheral clock edge to
occur. The peripheral device clock and the sample
clock are presented as inputs to the Clock Monitor latch
(CM). The CM is set on the falling edge of the device
clock source but cleared on the rising edge of the
sample clock.
The FSCM will detect failures of the primary or secondary
clock sources only. If the internal oscillator block fails, no
failure would be detected, nor would any action be
possible.
22.5.1
FSCM AND THE WATCHDOG TIMER
Both the FSCM and the WDT are clocked by the
INTRC oscillator. Since the WDT operates with a
separate divider and counter, disabling the WDT has
no effect on the operation of the INTRC oscillator when
the FSCM is enabled.
FIGURE 22-4:
FSCM BLOCK DIAGRAM
As already noted, the clock source is switched to the
INTRC clock when a clock failure is detected. This may
mean a substantial change in the speed of code execu-
tion. If the WDT is enabled with a small prescale value,
a decrease in clock speed allows a WDT time-out to
occur and a subsequent device Reset. For this reason,
Fail-Safe Clock Monitor events also reset the WDT and
postscaler, allowing it to start timing from when execu-
tion speed was changed and decreasing the likelihood
of an erroneous time-out.
Clock Monitor
Latch (CM)
(edge-triggered)
Peripheral
Clock
S
C
Q
Q
INTRC
Source
÷ 64
488 Hz
(2.048 ms)
(32 μs)
If the interrupt is disabled, subsequent interrupts while
in Idle mode will cause the CPU to begin executing
instructions while being clocked by the INTRC source.
Clock
Failure
Detected
Clock failure is tested for on the falling edge of the
sample clock. If a sample clock falling edge occurs
while CM is still set, a clock failure has been detected
(Figure 22-5). This causes the following:
• the FSCM generates an oscillator fail interrupt by
setting bit, OSCFIF (PIR2<7>);
• the device clock source is switched to the internal
oscillator block (OSCCON is not updated to show
the current clock source – this is the fail-safe
condition); and
• the WDT is reset.
DS39774C-page 282
Preliminary
© 2007 Microchip Technology Inc.
PIC18F85J11 FAMILY
FIGURE 22-5:
FSCM TIMING DIAGRAM
Sample Clock
Oscillator
Failure
Device
Clock
Output
CM Output
(Q)
Failure
Detected
OSCFIF
CM Test
CM Test
CM Test
Note:
The device clock is normally at a much higher frequency than the sample clock. The relative frequencies in
this example have been chosen for clarity.
22.5.2
EXITING FAIL-SAFE OPERATION
22.5.4
POR OR WAKE-UP FROM SLEEP
The fail-safe condition is terminated by either a device
Reset or by entering a power-managed mode. On
Reset, the controller starts the primary clock source
specified in Configuration Register 2H (with any
required start-up delays that are required for the oscil-
lator mode, such as OST or PLL timer). The INTRC
oscillator provides the device clock until the primary
clock source becomes ready (similar to a Two-Speed
Start-up). The clock source is then switched to the
primary clock (indicated by the OSTS bit in the
OSCCON register becoming set). The Fail-Safe Clock
Monitor then resumes monitoring the peripheral clock.
The FSCM is designed to detect oscillator failure at any
point after the device has exited Power-on Reset
(POR) or low-power Sleep mode. When the primary
device clock is either EC or INTRC mode, monitoring
can begin immediately following these events.
For HS or HSPLL modes, the situation is somewhat
different. Since the oscillator may require a start-up
time considerably longer than the FSCM sample clock
time, a false clock failure may be detected. To prevent
this, the internal oscillator block is automatically config-
ured as the device clock and functions until the primary
clock is stable (the OST and PLL timers have timed
out). This is identical to Two-Speed Start-up mode.
Once the primary clock is stable, the INTRC returns to
its role as the FSCM source.
The primary clock source may never become ready
during start-up. In this case, operation is clocked by the
INTOSC multiplexor. The OSCCON register will remain
in its Reset state until a power-managed mode is
entered.
Note:
The same logic that prevents false
oscillator failure interrupts on POR, or
wake from Sleep, will also prevent the
detection of the oscillator’s failure to start
at all following these events. This can be
avoided by monitoring the OSTS bit and
using a timing routine to determine if the
oscillator is taking too long to start. Even
so, no oscillator failure interrupt will be
flagged.
22.5.3
FSCM INTERRUPTS IN
POWER-MANAGED MODES
By entering a power-managed mode, the clock
multiplexor selects the clock source selected by the
OSCCON register. Fail-Safe Clock Monitoring of the
power-managed clock source resumes in the
power-managed mode.
If an oscillator failure occurs during power-managed
operation, the subsequent events depend on whether
or not the oscillator failure interrupt is enabled. If
enabled (OSCFIF = 1), code execution will be clocked
by the INTRC multiplexor. An automatic transition back
to the failed clock source will not occur.
As noted in Section 22.4.1 “Special Considerations
for Using Two-Speed Start-up”, it is also possible to
select another clock configuration and enter an alternate
power-managed mode while waiting for the primary
clock to become stable. When the new power-managed
mode is selected, the primary clock is disabled.
© 2007 Microchip Technology Inc.
Preliminary
DS39774C-page 283
PIC18F85J11 FAMILY
22.6 Program Verification and
Code Protection
22.7
In-Circuit Serial Programming
PIC18F85J11 family microcontrollers can be serially
programmed while in the end application circuit. This is
simply done with two lines for clock and data and three
other lines for power, ground and the programming
voltage. This allows customers to manufacture boards
with unprogrammed devices and then program the
microcontroller just before shipping the product. This
also allows the most recent firmware or a custom
firmware to be programmed.
For all devices in the PIC18F85J11 family of devices,
the on-chip program memory space is treated as a
single block. Code protection for this block is controlled
by one Configuration bit, CP0. This bit inhibits external
reads and writes to the program memory space. It has
no direct effect in normal execution mode.
22.6.1
CONFIGURATION REGISTER
PROTECTION
22.8 In-Circuit Debugger
The Configuration registers are protected against
untoward changes or reads in two ways. The primary
protection is the write-once feature of the Configuration
bits which prevents reconfiguration once the bit has
been programmed during a power cycle. To safeguard
against unpredictable events, Configuration bit
changes resulting from individual cell level disruptions
(such as ESD events) will cause a parity error and
trigger a device Reset.
When the DEBUG Configuration bit is programmed to
‘0’, the in-circuit debugger functionality is enabled. This
function allows simple debugging functions when used
with MPLAB® IDE. When the microcontroller has this
feature enabled, some resources are not available for
general use. Table 22-4 shows which resources are
required by the background debugger.
The data for the Configuration registers is derived from
the Flash Configuration Words in program memory.
When the CP0 bit is set, the source data for device
configuration is also protected as a consequence.
TABLE 22-4: DEBUGGER RESOURCES
I/O pins:
RB6, RB7
2 levels
Stack:
Program Memory:
Data Memory:
512 bytes
10 bytes
DS39774C-page 284
Preliminary
© 2007 Microchip Technology Inc.
PIC18F85J11 FAMILY
The literal instructions may use some of the following
operands:
23.0 INSTRUCTION SET SUMMARY
The PIC18F85J11 family of devices incorporate the
standard set of 75 PIC18 core instructions, as well as
an extended set of 8 new instructions for the optimiza-
tion of code that is recursive or that utilizes a software
stack. The extended set is discussed later in this
section.
• A literal value to be loaded into a File Select
Register (specified by ‘k’).
• The desired FSR register to load the literal value
into (specified by ‘f’).
• No operand required (specified by ‘—’).
The control instructions may use some of the following
operands:
23.1 Standard Instruction Set
• A program memory address (specified by ‘n’).
The standard PIC18 instruction set adds many
enhancements to the previous PIC® MCU instruction
sets, while maintaining an easy migration from these
PIC MCU instruction sets. Most instructions are a
single program memory word (16 bits), but there are
four instructions that require two program memory
locations.
• The mode of the CALLor RETURNinstructions
(specified by ‘s’).
• The mode of the table read and table write
instructions (specified by ‘m’).
• No operand required (specified by ‘—’).
All instructions are a single word, except for four
double-word instructions. These instructions were
made double-word to contain the required information
in 32 bits. In the second word, the 4 MSbs are ‘1’s. If
this second word is executed as an instruction (by
itself), it will execute as a NOP.
Each single-word instruction is a 16-bit word divided
into an opcode, which specifies the instruction type,
and one or more operands, which further specify the
operation of the instruction.
The instruction set is highly orthogonal and is grouped
into four basic categories:
All single-word instructions are executed in a single
instruction cycle unless a conditional test is true or the
program counter is changed as a result of the instruc-
tion. In these cases, the execution takes two instruction
cycles with the additional instruction cycle(s) executed
as a NOP.
• Byte-Oriented operations
• Bit-Oriented operations
• Literal operations
• Control operations
The PIC18 instruction set summary in Table 23-2 lists
byte-oriented, bit-oriented, literal and control
operations. Table 23-1 shows the opcode field
descriptions.
The double-word instructions execute in two instruction
cycles.
One instruction cycle consists of four oscillator periods.
Thus, for an oscillator frequency of 4 MHz, the normal
instruction execution time is 1 µs. If a conditional test is
true, or the program counter is changed as a result of
an instruction, the instruction execution time is 2 µs.
Two-word branch instructions (if true) would take 3 µs.
Most byte-oriented instructions have three operands:
1. The File Select Register (specified by ‘f’).
2. The destination of the result (specified by ‘d’).
3. The accessed memory (specified by ‘a’).
Figure 23-1 shows the general formats that the instruc-
tions can have. All examples use the convention ‘nnh’
to represent a hexadecimal number.
The File Select Register designator, ‘f’, specifies which
File Select Register is to be used by the instruction.
The destination designator, ‘d’, specifies where the
result of the operation is to be placed. If ‘d’ is zero, the
result is placed in the WREG register. If ‘d’ is one, the
result is placed in the File Select Register specified in
the instruction.
The instruction set summary, shown in Table 23-2, lists
the standard instructions recognized by the Microchip
MPASMTM Assembler.
Section 23.1.1 “Standard Instruction Set” provides
a description of each instruction.
All bit-oriented instructions have three operands:
1. The File Select Register (specified by ‘f’).
2. The bit in the File Select Register (specified by
‘b’).
3. The accessed memory (specified by ‘a’).
The bit field designator, ‘b’, selects the number of the bit
affected by the operation, while the File Select Register
designator, ‘f’, represents the number of the file in
which the bit is located.
© 2007 Microchip Technology Inc.
Preliminary
DS39774C-page 285
PIC18F85J11 FAMILY
TABLE 23-1: OPCODE FIELD DESCRIPTIONS
Field
Description
a
RAM access bit:
a = 0: RAM location in Access RAM (BSR register is ignored)
a = 1: RAM bank is specified by BSR register
bbb
Bit address within an 8-bit File Select Register (0 to 7).
Bank Select Register. Used to select the current RAM bank.
ALU STATUS bits: Carry, Digit Carry, Zero, Overflow, Negative.
BSR
C, DC, Z, OV, N
d
Destination select bit:
d = 0: store result in WREG
d = 1: store result in File Select Register f
dest
f
Destination: either the WREG register or the specified register file location.
8-bit register file address (00h to FFh) or 2-bit FSR designator (0h to 3h).
12-bit register file address (000h to FFFh). This is the source address.
12-bit register file address (000h to FFFh). This is the destination address.
Global Interrupt Enable bit.
f
s
f
d
GIE
k
Literal field, constant data or label (may be either an 8-bit, 12-bit or a 20-bit value).
Label name.
label
mm
The mode of the TBLPTR register for the table read and table write instructions.
Only used with table read and table write instructions:
*
No change to register (such as TBLPTR with table reads and writes)
Post-Increment register (such as TBLPTR with table reads and writes)
Post-Decrement register (such as TBLPTR with table reads and writes)
Pre-Increment register (such as TBLPTR with table reads and writes)
*+
*-
+*
n
The relative address (2’s complement number) for relative branch instructions or the direct address for
Call/Branch and Return instructions.
PC
Program Counter.
PCL
Program Counter Low Byte.
Program Counter High Byte.
Program Counter High Byte Latch.
Program Counter Upper Byte Latch.
Power-Down bit.
PCH
PCLATH
PCLATU
PD
PRODH
PRODL
s
Product of Multiply High Byte.
Product of Multiply Low Byte.
Fast Call/Return mode select bit:
s = 0: do not update into/from shadow registers
s = 1: certain registers loaded into/from shadow registers (Fast mode)
TBLPTR
TABLAT
TO
21-bit Table Pointer (points to a program memory location).
8-bit Table Latch.
Time-out bit.
TOS
u
Top-of-Stack.
Unused or unchanged.
Watchdog Timer.
WDT
WREG
x
Working register (accumulator).
Don’t care (‘0’ or ‘1’). The assembler will generate code with x = 0. It is the recommended form of use for
compatibility with all Microchip software tools.
z
7-bit offset value for Indirect Addressing of register files (source).
7-bit offset value for Indirect Addressing of register files (destination).
Optional argument.
s
z
d
{
}
[text]
(text)
[expr]<n>
→
Indicates an Indexed Address.
The contents of text.
Specifies bit nof the register indicated by the pointer, expr.
Assigned to.
< >
Register bit field.
∈
In the set of.
italics
User-defined term (font is Courier New).
DS39774C-page 286
Preliminary
© 2007 Microchip Technology Inc.
PIC18F85J11 FAMILY
FIGURE 23-1:
GENERAL FORMAT FOR INSTRUCTIONS
Byte-Oriented File Select Register operations
15 10
Example Instruction
9
8
7
0
ADDWF MYREG, W, B
OPCODE
d
a
f (FILE #)
d = 0for result destination to be WREG register
d = 1for result destination to be File Select Register (f)
a = 0to force Access Bank
a = 1for BSR to select bank
f = 8-bit File Select Register address
Byte to Byte move operations (2-word)
15
12 11
0
0
OPCODE
f (Source FILE #)
MOVFF MYREG1, MYREG2
15
12 11
1111
f (Destination FILE #)
f = 12-bit File Select Register address
Bit-Oriented File Select Register operations
15 12 11 9 8
OPCODE b (BIT #)
7
0
BSF MYREG, bit, B
a
f (FILE #)
b = 3-bit position of bit in File Select Register (f)
a = 0to force Access Bank
a = 1for BSR to select bank
f = 8-bit File Select Register address
Literal operations
15
8
7
0
MOVLW 7Fh
OPCODE
k (literal)
k = 8-bit immediate value
Control operations
CALL, GOTOand Branch operations
15
8 7
0
GOTO Label
OPCODE
12 11
n<7:0> (literal)
15
0
1111
n<19:8> (literal)
n = 20-bit immediate value
15
15
8
7
0
CALL MYFUNC
OPCODE
12 11
S
n<7:0> (literal)
0
1111
S = Fast bit
n<19:8> (literal)
15
15
11 10
0
0
BRA MYFUNC
BC MYFUNC
OPCODE
n<10:0> (literal)
n<7:0> (literal)
8 7
OPCODE
© 2007 Microchip Technology Inc.
Preliminary
DS39774C-page 287
PIC18F85J11 FAMILY
TABLE 23-2: PIC18F85J11 FAMILY INSTRUCTION SET
16-bit Instruction Word
Mnemonic,
Operands
Status
Affected
Description
Cycles
Notes
MSb LSb
BYTE-ORIENTED OPERATIONS
ADDWF f, d, a Add WREG and f
ADDWFC f, d, a Add WREG and Carry bit to f
ANDWF f, d, a AND WREG with f
1
1
1
1
1
0010 01da ffff ffff C, DC, Z, OV, N 1, 2
0010 00da ffff ffff C, DC, Z, OV, N 1, 2
0001 01da ffff ffff Z, N
0110 101a ffff ffff Z
0001 11da ffff ffff Z, N
1,2
2
1, 2
4
CLRF
f, a
Clear f
COMF
f, d, a Complement f
CPFSEQ f, a
CPFSGT f, a
CPFSLT f, a
Compare f with WREG, Skip =
Compare f with WREG, Skip >
Compare f with WREG, Skip <
1 (2 or 3) 0110 001a ffff ffff None
1 (2 or 3) 0110 010a ffff ffff None
1 (2 or 3) 0110 000a ffff ffff None
4
1, 2
DECF
f, d, a Decrement f
1
0000 01da ffff ffff C, DC, Z, OV, N 1, 2, 3, 4
DECFSZ f, d, a Decrement f, Skip if 0
DCFSNZ f, d, a Decrement f, Skip if Not 0
1 (2 or 3) 0010 11da ffff ffff None
1 (2 or 3) 0100 11da ffff ffff None
1, 2, 3, 4
1, 2
INCF
f, d, a Increment f
1
0010 10da ffff ffff C, DC, Z, OV, N 1, 2, 3, 4
INCFSZ
INFSNZ
IORWF
MOVF
f, d, a Increment f, Skip if 0
f, d, a Increment f, Skip if Not 0
f, d, a Inclusive OR WREG with f
f, d, a Move f
1 (2 or 3) 0011 11da ffff ffff None
1 (2 or 3) 0100 10da ffff ffff None
4
1, 2
1, 2
1
1
1
2
0001 00da ffff ffff Z, N
0101 00da ffff ffff Z, N
1100 ffff ffff ffff None
1111 ffff ffff ffff
MOVFF
f , f
Move f (source) to
1st word
s
d
s
f (destination) 2nd word
d
MOVWF f, a
Move WREG to f
Multiply WREG with f
Negate f
1
1
1
1
1
1
1
1
1
0110 111a ffff ffff None
0000 001a ffff ffff None
0110 110a ffff ffff C, DC, Z, OV, N
0011 01da ffff ffff C, Z, N
0100 01da ffff ffff Z, N
0011 00da ffff ffff C, Z, N
0100 00da ffff ffff Z, N
0110 100a ffff ffff None
0101 01da ffff ffff C, DC, Z, OV, N
MULWF
NEGF
RLCF
RLNCF
RRCF
RRNCF
SETF
f, a
f, a
1, 2
1, 2
f, d, a Rotate Left f through Carry
f, d, a Rotate Left f (No Carry)
f, d, a Rotate Right f through Carry
f, d, a Rotate Right f (No Carry)
f, a
Set f
1, 2
SUBFWB f, d, a Subtract f from WREG with
Borrow
SUBWF
f, d, a Subtract WREG from f
1
1
0101 11da ffff ffff C, DC, Z, OV, N 1, 2
0101 10da ffff ffff C, DC, Z, OV, N
SUBWFB f, d, a Subtract WREG from f with
Borrow
SWAPF
TSTFSZ f, a
XORWF f, d, a Exclusive OR WREG with f
f, d, a Swap Nibbles in f
1
0011 10da ffff ffff None
4
1, 2
Test f, Skip if 0
1 (2 or 3) 0110 011a ffff ffff None
0001 10da ffff ffff Z, N
1
Note 1: When a PORT register is modified as a function of itself (e.g., MOVF PORTB, 1, 0), the value used will be that
value present on the pins themselves. For example, if the data latch is ‘1’ for a pin configured as input and is
driven low by an external device, the data will be written back with a ‘0’.
2: If this instruction is executed on the TMR0 register (and, where applicable, d = 1), the prescaler will be cleared if
assigned.
3: If the Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The
second cycle is executed as a NOP.
4: Some instructions are two-word instructions. The second word of these instructions will be executed as a NOP
unless the first word of the instruction retrieves the information embedded in these 16 bits. This ensures that all
program memory locations have a valid instruction.
DS39774C-page 288
Preliminary
© 2007 Microchip Technology Inc.
PIC18F85J11 FAMILY
TABLE 23-2: PIC18F85J11 FAMILY INSTRUCTION SET (CONTINUED)
16-bit Instruction Word
Mnemonic,
Operands
Status
Affected
Description
Cycles
Notes
MSb LSb
BIT-ORIENTED OPERATIONS
BCF
BSF
BTFSC
BTFSS
BTG
f, b, a Bit Clear f
f, b, a Bit Set f
f, b, a Bit Test f, Skip if Clear
f, b, a Bit Test f, Skip if Set
f, b, a Bit Toggle f
1
1
1001 bbba ffff ffff None
1000 bbba ffff ffff None
1, 2
1, 2
3, 4
3, 4
1, 2
1 (2 or 3) 1011 bbba ffff ffff None
1 (2 or 3) 1010 bbba ffff ffff None
1
0111 bbba ffff ffff None
CONTROL OPERATIONS
BC
BN
n
n
n
n
n
n
n
n
Branch if Carry
1 (2)
1 (2)
1 (2)
1 (2)
1 (2)
1 (2)
1 (2)
2
1110 0010 nnnn nnnn None
1110 0110 nnnn nnnn None
1110 0011 nnnn nnnn None
1110 0111 nnnn nnnn None
1110 0101 nnnn nnnn None
1110 0001 nnnn nnnn None
1110 0100 nnnn nnnn None
1101 0nnn nnnn nnnn None
1110 0000 nnnn nnnn None
1110 110s kkkk kkkk None
1111 kkkk kkkk kkkk
Branch if Negative
Branch if Not Carry
Branch if Not Negative
Branch if Not Overflow
Branch if Not Zero
Branch if Overflow
Branch Unconditionally
Branch if Zero
BNC
BNN
BNOV
BNZ
BOV
BRA
BZ
n
n, s
1 (2)
2
CALL
Call Subroutine 1st word
2nd word
CLRWDT
DAW
GOTO
—
—
n
Clear Watchdog Timer
Decimal Adjust WREG
1
1
2
0000 0000 0000 0100 TO, PD
0000 0000 0000 0111 C
1110 1111 kkkk kkkk None
1111 kkkk kkkk kkkk
Go to Address
1st word
2nd word
NOP
NOP
POP
PUSH
RCALL
RESET
RETFIE
—
—
—
—
n
No Operation
No Operation
Pop Top of Return Stack (TOS)
Push Top of Return Stack (TOS)
Relative Call
1
1
1
1
2
1
2
0000 0000 0000 0000 None
1111 xxxx xxxx xxxx None
0000 0000 0000 0110 None
0000 0000 0000 0101 None
1101 1nnn nnnn nnnn None
0000 0000 1111 1111 All
0000 0000 0001 000s GIE/GIEH,
PEIE/GIEL
4
Software Device Reset
Return from Interrupt Enable
s
RETLW
RETURN
SLEEP
k
s
—
Return with Literal in WREG
Return from Subroutine
Go into Standby mode
2
2
1
0000 1100 kkkk kkkk None
0000 0000 0001 001s None
0000 0000 0000 0011 TO, PD
Note 1: When a PORT register is modified as a function of itself (e.g., MOVF PORTB, 1, 0), the value used will be that
value present on the pins themselves. For example, if the data latch is ‘1’ for a pin configured as input and is
driven low by an external device, the data will be written back with a ‘0’.
2: If this instruction is executed on the TMR0 register (and, where applicable, d = 1), the prescaler will be cleared if
assigned.
3: If the Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The
second cycle is executed as a NOP.
4: Some instructions are two-word instructions. The second word of these instructions will be executed as a NOP
unless the first word of the instruction retrieves the information embedded in these 16 bits. This ensures that all
program memory locations have a valid instruction.
© 2007 Microchip Technology Inc.
Preliminary
DS39774C-page 289
PIC18F85J11 FAMILY
TABLE 23-2: PIC18F85J11 FAMILY INSTRUCTION SET (CONTINUED)
16-bit Instruction Word
Mnemonic,
Operands
Status
Affected
Description
Cycles
Notes
MSb
LSb
LITERAL OPERATIONS
ADDLW
ANDLW
IORLW
LFSR
k
k
k
f, k
Add Literal and WREG
AND Literal with WREG
Inclusive OR Literal with WREG
Move Literal (12-bit) 2nd word
1
1
1
2
0000 1111 kkkk
0000 1011 kkkk
0000 1001 kkkk
1110 1110 00ff
1111 0000 kkkk
0000 0001 0000
0000 1110 kkkk
0000 1101 kkkk
0000 1100 kkkk
0000 1000 kkkk
0000 1010 kkkk
kkkk C, DC, Z, OV, N
kkkk Z, N
kkkk Z, N
kkkk None
kkkk
kkkk None
kkkk None
kkkk None
kkkk None
kkkk C, DC, Z, OV, N
kkkk Z, N
to FSR(f)
1st word
MOVLB
MOVLW
MULLW
RETLW
SUBLW
XORLW
k
k
k
k
k
k
Move Literal to BSR<3:0>
Move Literal to WREG
Multiply Literal with WREG
Return with Literal in WREG
Subtract WREG from Literal
Exclusive OR Literal with WREG
1
1
1
2
1
1
DATA MEMORY ↔ PROGRAM MEMORY OPERATIONS
TBLRD*
Table Read
2
0000 0000 0000
0000 0000 0000
0000 0000 0000
0000 0000 0000
0000 0000 0000
0000 0000 0000
0000 0000 0000
0000 0000 0000
1000 None
1001 None
1010 None
1011 None
1100 None
1101 None
1110 None
1111 None
TBLRD*+
TBLRD*-
TBLRD+*
TBLWT*
TBLWT*+
TBLWT*-
TBLWT+*
Table Read with Post-Increment
Table Read with Post-Decrement
Table Read with Pre-Increment
Table Write
Table Write with Post-Increment
Table Write with Post-Decrement
Table Write with Pre-Increment
2
Note 1: When a PORT register is modified as a function of itself (e.g., MOVF PORTB, 1, 0), the value used will be that
value present on the pins themselves. For example, if the data latch is ‘1’ for a pin configured as input and is
driven low by an external device, the data will be written back with a ‘0’.
2: If this instruction is executed on the TMR0 register (and, where applicable, d = 1), the prescaler will be cleared if
assigned.
3: If the Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The
second cycle is executed as a NOP.
4: Some instructions are two-word instructions. The second word of these instructions will be executed as a NOP
unless the first word of the instruction retrieves the information embedded in these 16 bits. This ensures that all
program memory locations have a valid instruction.
DS39774C-page 290
Preliminary
© 2007 Microchip Technology Inc.
PIC18F85J11 FAMILY
23.1.1
STANDARD INSTRUCTION SET
ADDLW
ADD Literal to W
ADDWF
ADD W to f
Syntax:
ADDLW k
Syntax:
ADDWF f {,d {,a}}
Operands:
Operation:
0 ≤ k ≤ 255
(W) + k → W
Operands:
0 ≤ f ≤ 255
d ∈ [0, 1]
a ∈ [0, 1]
Status Affected:
Encoding:
N, OV, C, DC, Z
0000 1111
Operation:
(W) + (f) → dest
kkkk
kkkk
Status Affected:
Encoding:
N, OV, C, DC, Z
Description:
The contents of W are added to the
8-bit literal ‘k’ and the result is placed
in W.
0010
01da
ffff
ffff
Description:
Add W to register ‘f’. If ‘d’ is ‘0’, the
result is stored in W. If ‘d’ is ‘1’, the
result is stored back in register ‘f’
(default).
Words:
Cycles:
1
1
Q Cycle Activity:
Q1
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank (default).
Q2
Q3
Q4
Decode
Read
literal ‘k’
Process
Data
Write to
W
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f ≤ 95 (5Fh). See
Section 23.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
Example:
ADDLW
15h
Before Instruction
10h
After Instruction
25h
W
=
W
=
Words:
Cycles:
1
1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
register ‘f’
Process
Data
Write to
destination
Example:
ADDWF
REG, 0, 0
Before Instruction
W
REG
=
=
17h
0C2h
After Instruction
W
REG
=
=
0D9h
0C2h
Note:
All PIC18 instructions may take an optional label argument preceding the instruction mnemonic for use in
symbolic addressing. If a label is used, the instruction format then becomes: {label} instruction argument(s).
© 2007 Microchip Technology Inc.
Preliminary
DS39774C-page 291
PIC18F85J11 FAMILY
ADDWFC
ADD W and Carry bit to f
ANDLW
AND Literal with W
Syntax:
ADDWFC f {,d {,a}}
Syntax:
ANDLW k
0 ≤ k ≤ 255
(W) .AND. k → W
N, Z
Operands:
0 ≤ f ≤ 255
d ∈ [0, 1]
a ∈ [0, 1]
Operands:
Operation:
Status Affected:
Encoding:
Description:
Operation:
(W) + (f) + (C) → dest
0000
1011
kkkk
kkkk
Status Affected:
Encoding:
N, OV, C, DC, Z
The contents of W are ANDed with the
8-bit literal ‘k’. The result is placed in W.
0010
00da
ffff
ffff
Description:
Add W, the Carry flag and data memory
location ‘f’. If ‘d’ is ‘0’, the result is
placed in W. If ‘d’ is ‘1’, the result is
placed in data memory location ‘f’.
Words:
Cycles:
1
1
Q Cycle Activity:
Q1
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank (default).
Q2
Q3
Q4
Decode
Read literal
‘k’
Process
Data
Write to
W
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f ≤ 95 (5Fh). See
Section 23.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
Example:
ANDLW
05Fh
Before Instruction
W
=
A3h
03h
After Instruction
W
=
Words:
Cycles:
1
1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
register ‘f’
Process
Data
Write to
destination
Example:
ADDWFC
REG, 0, 1
Before Instruction
Carry bit =
1
02h
4Dh
REG
W
=
=
After Instruction
Carry bit =
0
02h
50h
REG
W
=
=
DS39774C-page 292
Preliminary
© 2007 Microchip Technology Inc.
PIC18F85J11 FAMILY
ANDWF
AND W with f
BC
Branch if Carry
Syntax:
ANDWF f {,d {,a}}
Syntax:
BC n
Operands:
0 ≤ f ≤ 255
d ∈ [0, 1]
a ∈ [0, 1]
Operands:
Operation:
-128 ≤ n ≤ 127
if Carry bit is ‘1’,
(PC) + 2 + 2n → PC
Operation:
(W) .AND. (f) → dest
Status Affected:
Encoding:
None
Status Affected:
Encoding:
N, Z
1110
0010
nnnn
nnnn
0001
01da
ffff
ffff
Description:
If the Carry bit is ’1’, then the program
Description:
The contents of W are ANDed with
register ‘f’. If ‘d’ is ‘0’, the result is stored
in W. If ‘d’ is ‘1’, the result is stored back
in register ‘f’ (default).
will branch.
The 2’s complement number ‘2n’ is
added to the PC. Since the PC will have
incremented to fetch the next
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank (default).
instruction, the new address will be
PC + 2 + 2n. This instruction is then a
two-cycle instruction.
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f ≤ 95 (5Fh). See
Section 23.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
Words:
Cycles:
1
1(2)
Q Cycle Activity:
If Jump:
Q1
Q2
Q3
Q4
Decode
Read literal
‘n’
Process
Data
Write to
PC
Words:
Cycles:
1
1
No
No
No
operation
No
operation
operation
operation
Q Cycle Activity:
Q1
If No Jump:
Q1
Q2
Q3
Q4
Q2
Q3
Q4
Decode
Read
register ‘f’
Process
Data
Write to
destination
Decode
Read literal
‘n’
Process
Data
No
operation
Example:
ANDWF
REG, 0, 0
Example:
HERE
BC
5
Before Instruction
Before Instruction
W
REG
=
=
17h
C2h
PC
=
address (HERE)
1;
After Instruction
After Instruction
If Carry
PC
If Carry
PC
=
=
=
=
W
REG
=
=
02h
C2h
address (HERE + 12)
0;
address (HERE + 2)
© 2007 Microchip Technology Inc.
Preliminary
DS39774C-page 293
PIC18F85J11 FAMILY
BCF
Bit Clear f
BN
Branch if Negative
Syntax:
BCF f, b {,a}
Syntax:
BN n
Operands:
0 ≤ f ≤ 255
0 ≤ b ≤ 7
a ∈ [0, 1]
Operands:
Operation:
-128 ≤ n ≤ 127
if Negative bit is ‘1’,
(PC) + 2 + 2n → PC
Operation:
0 → f<b>
None
Status Affected:
Encoding:
None
Status Affected:
Encoding:
1110
0110
nnnn
nnnn
1001
bbba
ffff
ffff
Description:
If the Negative bit is ‘1’, then the
Description:
Bit ‘b’ in register ‘f’ is cleared.
program will branch.
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank (default).
The 2’s complement number, ‘2n’, is
added to the PC. Since the PC will have
incremented to fetch the next
instruction, the new address will be
PC + 2 + 2n. This instruction is then a
two-cycle instruction.
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f ≤ 95 (5Fh). See
Section 23.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
Words:
Cycles:
1
1(2)
Q Cycle Activity:
If Jump:
Words:
Cycles:
1
1
Q1
Q2
Q3
Q4
Decode
Read literal
‘n’
Process
Data
Write to
PC
Q Cycle Activity:
Q1
Q2
Q3
Q4
No
No
No
No
operation
operation
operation
operation
Decode
Read
register ‘f’
Process
Data
Write
register ‘f’
If No Jump:
Q1
Q2
Q3
Q4
Decode
Read literal
‘n’
Process
Data
No
operation
Example:
BCF
FLAG_REG, 7, 0
Before Instruction
FLAG_REG = C7h
After Instruction
FLAG_REG = 47h
Example:
HERE
BN Jump
Before Instruction
PC
=
address (HERE)
After Instruction
If Negative
PC
If Negative
PC
=
=
=
=
1;
address (Jump)
0;
address (HERE + 2)
DS39774C-page 294
Preliminary
© 2007 Microchip Technology Inc.
PIC18F85J11 FAMILY
BNC
Branch if Not Carry
BNN
Branch if Not Negative
Syntax:
BNC n
Syntax:
BNN n
Operands:
Operation:
-128 ≤ n ≤ 127
Operands:
Operation:
-128 ≤ n ≤ 127
if Carry bit is ‘0’,
(PC) + 2 + 2n → PC
if Negative bit is ‘0’,
(PC) + 2 + 2n → PC
Status Affected:
Encoding:
None
Status Affected:
Encoding:
None
1110
0011
nnnn
nnnn
1110
0111
nnnn
nnnn
Description:
If the Carry bit is ‘0’, then the program
Description:
If the Negative bit is ‘0’, then the
will branch.
program will branch.
The 2’s complement number, ‘2n’, is
added to the PC. Since the PC will have
incremented to fetch the next
The 2’s complement number, ‘2n’, is
added to the PC. Since the PC will have
incremented to fetch the next
instruction, the new address will be
PC + 2 + 2n. This instruction is then a
two-cycle instruction.
instruction, the new address will be
PC + 2 + 2n. This instruction is then a
two-cycle instruction.
Words:
Cycles:
1
Words:
Cycles:
1
1(2)
1(2)
Q Cycle Activity:
If Jump:
Q Cycle Activity:
If Jump:
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Decode
Read literal
‘n’
Process
Data
Write to
PC
Decode
Read literal
‘n’
Process
Data
Write to
PC
No
No
No
No
No
No
No
No
operation
operation
operation
operation
operation
operation
operation
operation
If No Jump:
Q1
If No Jump:
Q1
Q2
Q3
Q4
Q2
Q3
Q4
Decode
Read literal
‘n’
Process
Data
No
operation
Decode
Read literal
‘n’
Process
Data
No
operation
Example:
HERE
BNC Jump
Example:
HERE
BNN Jump
Before Instruction
Before Instruction
PC
=
address (HERE)
PC
=
address (HERE)
After Instruction
After Instruction
If Carry
PC
If Carry
PC
=
=
=
=
0;
If Negative
PC
If Negative
PC
=
=
=
=
0;
address (Jump)
1;
address (Jump)
1;
address (HERE + 2)
address (HERE + 2)
© 2007 Microchip Technology Inc.
Preliminary
DS39774C-page 295
PIC18F85J11 FAMILY
BNOV
Branch if Not Overflow
BNZ
Branch if Not Zero
Syntax:
BNOV n
Syntax:
BNZ n
Operands:
Operation:
-128 ≤ n ≤ 127
Operands:
Operation:
-128 ≤ n ≤ 127
if Overflow bit is ‘0’,
(PC) + 2 + 2n → PC
if Zero bit is ‘0’,
(PC) + 2 + 2n → PC
Status Affected:
Encoding:
None
Status Affected:
Encoding:
None
1110
0101
nnnn
nnnn
1110
0001
nnnn
nnnn
Description:
If the Overflow bit is ‘0’, then the
Description:
If the Zero bit is ‘0’, then the program
program will branch.
will branch.
The 2’s complement number, ‘2n’, is
added to the PC. Since the PC will have
incremented to fetch the next
The 2’s complement number, ‘2n’, is
added to the PC. Since the PC will have
incremented to fetch the next
instruction, the new address will be
PC + 2 + 2n. This instruction is then a
two-cycle instruction.
instruction, the new address will be
PC + 2 + 2n. This instruction is then a
two-cycle instruction.
Words:
Cycles:
1
Words:
Cycles:
1
1(2)
1(2)
Q Cycle Activity:
If Jump:
Q Cycle Activity:
If Jump:
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Decode
Read literal
‘n’
Process
Data
Write to
PC
Decode
Read literal
‘n’
Process
Data
Write to
PC
No
No
No
No
No
No
No
No
operation
operation
operation
operation
operation
operation
operation
operation
If No Jump:
Q1
If No Jump:
Q1
Q2
Q3
Q4
Q2
Q3
Q4
Decode
Read literal
‘n’
Process
Data
No
operation
Decode
Read literal
‘n’
Process
Data
No
operation
Example:
HERE
BNOV Jump
Example:
HERE
BNZ Jump
Before Instruction
Before Instruction
PC
=
address (HERE)
PC
=
address (HERE)
After Instruction
After Instruction
If Overflow
PC
If Overflow
PC
=
=
=
=
0;
If Zero
PC
If Zero
PC
=
=
=
=
0;
address (Jump)
1;
address (Jump)
1;
address (HERE + 2)
address (HERE + 2)
DS39774C-page 296
Preliminary
© 2007 Microchip Technology Inc.
PIC18F85J11 FAMILY
BRA
Unconditional Branch
BSF
Bit Set f
Syntax:
BRA n
Syntax:
BSF f, b {,a}
Operands:
Operation:
Status Affected:
Encoding:
Description:
-1024 ≤ n ≤ 1023
(PC) + 2 + 2n → PC
None
Operands:
0 ≤ f ≤ 255
0 ≤ b ≤ 7
a ∈ [0, 1]
Operation:
1→ f<b>
None
1101
0nnn
nnnn
nnnn
Status Affected:
Encoding:
Add the 2’s complement number, ‘2n’,
to the PC. Since the PC will have
incremented to fetch the next
instruction, the new address will be
PC + 2 + 2n. This instruction is a
two-cycle instruction.
1000
bbba
ffff
ffff
Description:
Bit ‘b’ in register ‘f’ is set.
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank (default).
Words:
Cycles:
1
2
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f ≤ 95 (5Fh). See
Section 23.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read literal
‘n’
Process
Data
Write to
PC
No
operation
No
operation
No
operation
No
operation
Words:
Cycles:
1
1
Q Cycle Activity:
Q1
Example:
HERE
BRA Jump
Q2
Q3
Q4
Before Instruction
Decode
Read
register ‘f’
Process
Data
Write
register ‘f’
PC
=
=
address (HERE)
address (Jump)
After Instruction
PC
Example:
BSF
FLAG_REG, 7, 1
0Ah
8Ah
Before Instruction
FLAG_REG
After Instruction
FLAG_REG
=
=
© 2007 Microchip Technology Inc.
Preliminary
DS39774C-page 297
PIC18F85J11 FAMILY
BTFSC
Bit Test File, Skip if Clear
BTFSS
Bit Test File, Skip if Set
Syntax:
BTFSC f, b {,a}
Syntax:
BTFSS f, b {,a}
Operands:
0 ≤ f ≤ 255
0 ≤ b ≤ 7
a ∈ [0, 1]
Operands:
0 ≤ f ≤ 255
0 ≤ b < 7
a ∈ [0, 1]
Operation:
skip if (f<b>) = 0
Operation:
skip if (f<b>) = 1
Status Affected:
Encoding:
None
Status Affected:
Encoding:
None
1011
bbba
ffff
ffff
1010
bbba
ffff
ffff
Description:
If bit ‘b’ in register ‘f’ is ‘0’, then the next
instruction is skipped. If bit ‘b’ is ‘0’, then
the next instruction fetched during the
current instruction execution is discarded
and a NOPis executed instead, making
this a two-cycle instruction.
Description:
If bit ‘b’ in register ‘f’ is ‘1’, then the next
instruction is skipped. If bit ‘b’ is ‘1’, then
the next instruction fetched during the
current instruction execution is discarded
and a NOPis executed instead, making
this a two-cycle instruction.
If ‘a’ is ‘0’, the Access Bank is selected. If
‘a’ is ‘1’, the BSR is used to select the
GPR bank (default).
If ‘a’ is ‘0’, the Access Bank is selected. If
‘a’ is ‘1’, the BSR is used to select the
GPR bank (default).
If ‘a’ is ‘0’ and the extended instruction set
is enabled, this instruction operates in
Indexed Literal Offset Addressing mode
whenever f ≤ 95 (5Fh). See
Section 23.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates in
Indexed Literal Offset Addressing mode
whenever f ≤ 95 (5Fh). See
Section 23.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
Words:
Cycles:
1
Words:
Cycles:
1
1(2)
1(2)
Note: 3 cycles if skip and followed
by a 2-word instruction.
Note: 3 cycles if skip and followed
by a 2-word instruction.
Q Cycle Activity:
Q1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Q2
Q3
Q4
Decode
Read
register ‘f’
Process
Data
No
operation
Decode
Read
register ‘f’
Process
Data
No
operation
If skip:
Q1
If skip:
Q1
Q2
Q3
Q4
Q2
Q3
Q4
No
No
No
No
No
No
No
No
operation
operation
operation
operation
operation
operation
operation
operation
If skip and followed by 2-word instruction:
If skip and followed by 2-word instruction:
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
No
No
No
No
No
No
No
No
operation
operation
operation
operation
operation
operation
operation
operation
No
No
No
No
No
No
No
No
operation
operation
operation
operation
operation
operation
operation
operation
Example:
HERE
FALSE
TRUE
BTFSC
:
:
FLAG, 1, 0
Example:
HERE
FALSE
TRUE
BTFSS
:
:
FLAG, 1, 0
Before Instruction
PC
Before Instruction
PC
=
address (HERE)
=
address (HERE)
After Instruction
After Instruction
If FLAG<1>
PC
If FLAG<1>
PC
=
=
=
=
0;
If FLAG<1>
PC
If FLAG<1>
PC
=
=
=
=
0;
address (TRUE)
1;
address (FALSE)
1;
address (FALSE)
address (TRUE)
DS39774C-page 298
Preliminary
© 2007 Microchip Technology Inc.
PIC18F85J11 FAMILY
BTG
Bit Toggle f
BOV
Branch if Overflow
Syntax:
BTG f, b {,a}
Syntax:
BOV n
Operands:
0 ≤ f ≤ 255
0 ≤ b < 7
a ∈ [0, 1]
Operands:
Operation:
-128 ≤ n ≤ 127
if Overflow bit is ‘1’,
(PC) + 2 + 2n → PC
Operation:
(f<b>) → f<b>
Status Affected:
Encoding:
None
Status Affected:
Encoding:
None
1110
0100
nnnn
nnnn
0111
bbba
ffff
ffff
Description:
If the Overflow bit is ‘1’, then the
Description:
Bit ‘b’ in data memory location ‘f’ is
inverted.
program will branch.
The 2’s complement number, ‘2n’, is
added to the PC. Since the PC will have
incremented to fetch the next
instruction, the new address will be
PC + 2 + 2n. This instruction is then a
two-cycle instruction.
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank (default).
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f ≤ 95 (5Fh). See
Section 23.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
Words:
Cycles:
1
1(2)
Q Cycle Activity:
If Jump:
Q1
Q2
Q3
Q4
Words:
Cycles:
1
1
Decode
Read literal
‘n’
Process
Data
Write to PC
Q Cycle Activity:
Q1
No
operation
No
operation
No
operation
No
operation
Q2
Q3
Q4
Decode
Read
register ‘f’
Process
Data
Write
register ‘f’
If No Jump:
Q1
Q2
Q3
Q4
Decode
Read literal
‘n’
Process
Data
No
operation
Example:
BTG
PORTC, 4, 0
Before Instruction:
PORTC
After Instruction:
PORTC
=
0111 0101 [75h]
0110 0101 [65h]
Example:
HERE
BOV Jump
Before Instruction
=
PC
=
address (HERE)
After Instruction
If Overflow
PC
If Overflow
PC
=
=
=
=
1;
address (Jump)
0;
address (HERE + 2)
© 2007 Microchip Technology Inc.
Preliminary
DS39774C-page 299
PIC18F85J11 FAMILY
BZ
Branch if Zero
CALL
Subroutine Call
Syntax:
BZ n
Syntax:
CALL k {,s}
Operands:
Operation:
-128 ≤ n ≤ 127
Operands:
0 ≤ k ≤ 1048575
s ∈ [0, 1]
if Zero bit is ‘1’,
(PC) + 2 + 2n → PC
Operation:
(PC) + 4 → TOS,
k → PC<20:1>;
if s = 1,
Status Affected:
Encoding:
None
1110
0000
nnnn
nnnn
(W) → WS,
(STATUS) → STATUSS,
(BSR) → BSRS
Description:
If the Zero bit is ‘1’, then the program
will branch.
Status Affected:
None
The 2’s complement number, ‘2n’, is
added to the PC. Since the PC will have
incremented to fetch the next
instruction, the new address will be
PC + 2 + 2n. This instruction is then a
two-cycle instruction.
Encoding:
1st word (k<7:0>)
2nd word(k<19:8>)
1110
1111
110s
k kkk
kkkk
kkkk
7
0
8
k
kkk kkkk
19
Description:
Subroutine call of entire 2-Mbyte
memory range. First, return address
Words:
Cycles:
1
(PC+ 4) is pushed onto the return stack.
If ‘s’ = 1, the W, STATUS and BSR
registers are also pushed into their
respective shadow registers, WS,
STATUSS and BSRS. If ‘s’ = 0, no
update occurs (default). Then, the
20-bit value, ‘k’, is loaded into
PC<20:1>. CALLis a two-cycle
instruction.
1(2)
Q Cycle Activity:
If Jump:
Q1
Q2
Q3
Q4
Decode
Read literal
‘n’
Process
Data
Write to
PC
No
No
No
No
operation
operation
operation
operation
Words:
Cycles:
2
2
If No Jump:
Q1
Q2
Q3
Q4
Q Cycle Activity:
Q1
Decode
Read literal
‘n’
Process
Data
No
operation
Q2
Q3
Q4
Decode
Read literal Push PC to Read literal
‘k’<7:0>,
stack
’k’<19:8>,
Write to PC
Example:
HERE
BZ Jump
Before Instruction
No
No
No
No
PC
=
address (HERE)
operation
operation
operation
operation
After Instruction
If Zero
PC
If Zero
PC
=
=
=
=
1;
Example:
HERE
CALL THERE,1
address (Jump)
0;
Before Instruction
PC
After Instruction
address (HERE + 2)
=
address (HERE)
PC
=
address (THERE)
TOS
WS
=
=
=
address (HERE + 4)
W
BSRS
STATUSS =
BSR
STATUS
DS39774C-page 300
Preliminary
© 2007 Microchip Technology Inc.
PIC18F85J11 FAMILY
CLRF
Clear f
CLRWDT
Clear Watchdog Timer
Syntax:
CLRF f {,a}
Syntax:
CLRWDT
None
Operands:
0 ≤ f ≤ 255
a ∈ [0, 1]
Operands:
Operation:
000h → WDT,
000h → WDT postscaler,
1→ TO,
Operation:
000h → f,
1→ Z
1→ PD
Status Affected:
Encoding:
Z
Status Affected:
Encoding:
TO, PD
0110
101a
ffff
ffff
0000
0000
0000
0100
Description:
Clears the contents of the specified
register.
Description:
CLRWDTinstruction resets the
Watchdog Timer. It also resets the
postscaler of the WDT. Status bits, TO
and PD, are set.
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank (default).
Words:
Cycles:
1
1
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f ≤ 95 (5Fh). See
Section 23.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
No
Process
Data
No
operation
operation
Words:
Cycles:
1
1
Example:
CLRWDT
Before Instruction
Q Cycle Activity:
Q1
WDT Counter
After Instruction
WDT Counter
WDT Postscaler
TO
=
?
Q2
Q3
Q4
Decode
Read
Process
Data
Write
register ‘f’
=
=
=
=
00h
0
1
register ‘f’
PD
1
Example:
CLRF
FLAG_REG,1
Before Instruction
FLAG_REG
After Instruction
FLAG_REG
=
=
5Ah
00h
© 2007 Microchip Technology Inc.
Preliminary
DS39774C-page 301
PIC18F85J11 FAMILY
CPFSEQ
Compare f with W, Skip if f = W
COMF
Complement f
Syntax:
CPFSEQ f {,a}
Syntax:
COMF f {,d {,a}}
Operands:
0 ≤ f ≤ 255
a ∈ [0, 1]
Operands:
0 ≤ f ≤ 255
d ∈ [0, 1]
a ∈ [0, 1]
Operation:
(f) – (W),
skip if (f) = (W)
(unsigned comparison)
Operation:
f → dest
Status Affected:
Encoding:
N, Z
Status Affected:
Encoding:
None
0001
11da
ffff
ffff
0110
001a
ffff
ffff
Description:
The contents of register ‘f’ are
Description:
Compares the contents of data memory
location ‘f’ to the contents of W by
performing an unsigned subtraction.
complemented. If ‘d’ is ‘0’, the result is
stored in W. If ‘d’ is ‘1’, the result is
stored back in register ‘f’ (default).
If ‘f’ = W, then the fetched instruction is
discarded and a NOPis executed
instead, making this a two-cycle
instruction.
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank (default).
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f ≤ 95 (5Fh). See
Section 23.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank (default).
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f ≤ 95 (5Fh). See
Section 23.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
Words:
Cycles:
1
1
Q Cycle Activity:
Q1
Words:
Cycles:
1
Q2
Q3
Q4
1(2)
Decode
Read
register ‘f’
Process
Data
Write to
destination
Note: 3 cycles if skip and followed
by a 2-word instruction.
Q Cycle Activity:
Q1
Example:
COMF
REG, 0, 0
Q2
Read
register ‘f’
Q3
Process
Data
Q4
No
operation
Before Instruction
Decode
REG
=
13h
After Instruction
If skip:
Q1
REG
W
=
=
13h
ECh
Q2
No
Q3
No
Q4
No
No
operation
operation
operation
operation
If skip and followed by 2-word instruction:
Q1
No
Q2
No
Q3
No
Q4
No
operation
No
operation
No
operation
No
operation
No
operation
operation
operation
operation
Example:
HERE
CPFSEQ REG, 0
NEQUAL
EQUAL
:
:
Before Instruction
PC Address
=
=
=
HERE
?
?
W
REG
After Instruction
If REG
PC
If REG
PC
=
=
≠
=
W;
Address (EQUAL)
W;
Address (NEQUAL)
DS39774C-page 302
Preliminary
© 2007 Microchip Technology Inc.
PIC18F85J11 FAMILY
CPFSGT
Compare f with W, Skip if f > W
CPFSLT
Compare f with W, Skip if f < W
Syntax:
CPFSGT f {,a}
Syntax:
CPFSLT f {,a}
Operands:
0 ≤ f ≤ 255
a ∈ [0, 1]
Operands:
0 ≤ f ≤ 255
a ∈ [0, 1]
Operation:
(f) – (W),
skip if (f) > (W)
(unsigned comparison)
Operation:
(f) – (W),
skip if (f) < (W)
(unsigned comparison)
Status Affected:
Encoding:
None
Status Affected:
Encoding:
None
0110
010a
ffff
ffff
0110
000a
ffff
ffff
Description:
Compares the contents of data memory
location ‘f’ to the contents of the W by
performing an unsigned subtraction.
Description:
Compares the contents of data memory
location ‘f’ to the contents of W by
performing an unsigned subtraction.
If the contents of ‘f’ are greater than the
contents of WREG, then the fetched
instruction is discarded and a NOPis
executed instead, making this a
two-cycle instruction.
If the contents of ‘f’ are less than the
contents of W, then the fetched
instruction is discarded and a NOPis
executed instead, making this a
two-cycle instruction.
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank (default).
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank (default).
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f ≤ 95 (5Fh). See
Section 23.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
Words:
Cycles:
1
1(2)
Note: 3 cycles if skip and followed
by a 2-word instruction.
Q Cycle Activity:
Q1
Q2
Q3
Q4
Words:
Cycles:
1
Decode
Read
Process
Data
No
operation
1(2)
register ‘f’
Note: 3 cycles if skip and followed
by a 2-word instruction.
If skip:
Q1
Q2
Q3
Q4
Q Cycle Activity:
Q1
No
operation
No
operation
No
operation
No
operation
Q2
Read
register ‘f’
Q3
Process
Data
Q4
No
operation
Decode
If skip and followed by 2-word instruction:
Q1
Q2
Q3
Q4
If skip:
Q1
No
operation
No
operation
No
operation
No
operation
Q2
No
Q3
No
Q4
No
No
No
No
No
No
operation
operation
operation
operation
operation
operation
operation
operation
If skip and followed by 2-word instruction:
Q1
No
Q2
No
Q3
No
Q4
No
Example:
HERE
NLESS
LESS
CPFSLT REG, 1
:
:
operation
No
operation
No
operation
No
operation
No
operation
operation
operation
operation
Before Instruction
PC
W
=
=
Address (HERE)
Example:
HERE
NGREATER
GREATER
CPFSGT REG, 0
:
:
?
After Instruction
If REG
PC
If REG
PC
<
=
≥
=
W;
Address (LESS)
W;
Before Instruction
PC
W
=
=
Address (HERE)
Address (NLESS)
?
After Instruction
If REG
PC
If REG
PC
>
=
≤
=
W;
Address (GREATER)
W;
Address (NGREATER)
© 2007 Microchip Technology Inc.
Preliminary
DS39774C-page 303
PIC18F85J11 FAMILY
DAW
Decimal Adjust W Register
DECF
Decrement f
Syntax:
DAW
None
Syntax:
DECF f {,d {,a}}
Operands:
Operation:
Operands:
0 ≤ f ≤ 255
d ∈ [0, 1]
a ∈ [0, 1]
If [W<3:0> > 9] or [DC = 1], then
(W<3:0>) + 6 → W<3:0>;
else
Operation:
(f) – 1→ dest
(W<3:0>) → W<3:0>
Status Affected:
Encoding:
C, DC, N, OV, Z
0000
01da
ffff
ffff
If [W<7:4> > 9] or [C = 1], then
(W<7:4>) + 6 → W<7:4>;
C = 1;
Description:
Decrement register ‘f’. If ‘d’ is ‘0’, the
result is stored in W. If ‘d’ is ‘1’, the
result is stored back in register ‘f’
(default).
else
(W<7:4>) → W<7:4>
Status Affected:
Encoding:
C
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank (default).
0000
0000
0000
0111
Description:
DAW adjusts the eight-bit value in W,
resulting from the earlier addition of two
variables (each in packed BCD format)
and produces a correct packed BCD
result.
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f ≤ 95 (5Fh). See
Section 23.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
Words:
Cycles:
1
1
Q Cycle Activity:
Q1
Words:
Cycles:
1
1
Q2
Q3
Q4
Decode
Read
register W
Process
Data
Write
W
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
register ‘f’
Process
Data
Write to
destination
Example 1:
DAW
Before Instruction
W
=
A5h
0
0
Example:
DECF
CNT,
1, 0
C
=
=
DC
Before Instruction
After Instruction
CNT
Z
=
01h
0
W
=
=
=
05h
1
0
=
C
After Instruction
DC
CNT
Z
=
=
00h
1
Example 2:
Before Instruction
W
=
=
=
CEh
0
0
C
DC
After Instruction
W
=
=
=
34h
1
0
C
DC
DS39774C-page 304
Preliminary
© 2007 Microchip Technology Inc.
PIC18F85J11 FAMILY
DECFSZ
Decrement f, Skip if 0
DCFSNZ
Decrement f, Skip if Not 0
Syntax:
DECFSZ f {,d {,a}}
Syntax:
DCFSNZ f {,d {,a}}
Operands:
0 ≤ f ≤ 255
d ∈ [0, 1]
a ∈ [0, 1]
Operands:
0 ≤ f ≤ 255
d ∈ [0, 1]
a ∈ [0, 1]
Operation:
(f) – 1→ dest,
skip if result = 0
Operation:
(f) – 1→ dest,
skip if result ≠ 0
Status Affected:
Encoding:
None
Status Affected:
Encoding:
None
0010
11da
ffff
ffff
0100
11da
ffff
ffff
Description:
The contents of register ‘f’ are
Description:
The contents of register ‘f’ are
decremented. If ‘d’ is ‘0’, the result is
placed in W. If ‘d’ is ‘1’, the result is
placed back in register ‘f’ (default).
decremented. If ‘d’ is ‘0’, the result is
placed in W. If ‘d’ is ‘1’, the result is
placed back in register ‘f’ (default).
If the result is ‘0’, the next instruction
which is already fetched is discarded
and a NOPis executed instead, making
it a two-cycle instruction.
If the result is not ‘0’, the next
instruction which is already fetched is
discarded and a NOPis executed
instead, making it a two-cycle
instruction.
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank (default).
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank (default).
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f ≤ 95 (5Fh). See
Section 23.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f ≤ 95 (5Fh). See
Section 23.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
Words:
Cycles:
1
Words:
Cycles:
1
1(2)
Note: 3 cycles if skip and followed
by a 2-word instruction.
1(2)
Note: 3 cycles if skip and followed
by a 2-word instruction.
Q Cycle Activity:
Q1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Q2
Q3
Q4
Decode
Read
register ‘f’
Process
Data
Write to
destination
Decode
Read
Process
Data
Write to
destination
register ‘f’
If skip:
Q1
If skip:
Q1
Q2
Q3
Q4
Q2
Q3
Q4
No
No
No
No
operation
operation
operation
operation
No
No
No
No
operation
operation
operation
operation
If skip and followed by 2-word instruction:
If skip and followed by 2-word instruction:
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
No
No
No
No
operation
operation
operation
operation
No
No
No
No
operation
operation
operation
operation
No
No
No
No
operation
operation
operation
operation
No
No
No
No
operation
operation
operation
operation
Example:
HERE
DECFSZ
GOTO
CNT, 1, 1
LOOP
Example:
HERE
ZERO
NZERO
DCFSNZ TEMP, 1, 0
:
:
CONTINUE
Before Instruction
PC
After Instruction
Before Instruction
TEMP
After Instruction
=
Address (HERE)
=
?
CNT
=
CNT – 1
0;
If CNT
=
=
≠
=
TEMP
If TEMP
PC
If TEMP
PC
=
=
=
≠
=
TEMP – 1
0;
PC
Address (CONTINUE)
0;
If CNT
PC
Address (ZERO)
0;
Address (HERE + 2)
Address (NZERO)
© 2007 Microchip Technology Inc.
Preliminary
DS39774C-page 305
PIC18F85J11 FAMILY
GOTO
Unconditional Branch
INCF
Increment f
Syntax:
GOTO k
Syntax:
INCF f {,d {,a}}
Operands:
Operation:
Status Affected:
0 ≤ k ≤ 1048575
k → PC<20:1>
None
Operands:
0 ≤ f ≤ 255
d ∈ [0, 1]
a ∈ [0, 1]
Operation:
(f) + 1→ dest
Encoding:
1st word (k<7:0>)
2nd word(k<19:8>)
Status Affected:
Encoding:
C, DC, N, OV, Z
1110
1111
1111
kkk
k kkk
kkkk
kkkk
kkkk
7
0
8
k
0010
10da
ffff
ffff
19
Description:
GOTOallows an unconditional branch
Description:
The contents of register ‘f’ are
anywhere within entire 2-Mbyte memory
range. The 20-bit value, ‘k’, is loaded
into PC<20:1>. GOTOis always a
two-cycle instruction.
incremented. If ‘d’ is ‘0’, the result is
placed in W. If ‘d’ is ‘1’, the result is
placed back in register ‘f’ (default).
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank (default).
Words:
Cycles:
2
2
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f ≤ 95 (5Fh). See
Section 23.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read literal
‘k’<7:0>,
No
operation
Read literal
‘k’<19:8>,
Write to PC
No
No
No
No
operation
operation
operation
operation
Words:
Cycles:
1
1
Example:
GOTO THERE
Q Cycle Activity:
Q1
After Instruction
Q2
Q3
Q4
PC
=
Address (THERE)
Decode
Read
register ‘f’
Process
Data
Write to
destination
Example:
INCF
CNT, 1, 0
Before Instruction
CNT
Z
=
FFh
0
?
?
=
=
=
C
DC
After Instruction
CNT
Z
=
00h
1
1
=
=
=
C
DC
1
DS39774C-page 306
Preliminary
© 2007 Microchip Technology Inc.
PIC18F85J11 FAMILY
INFSNZ
Increment f, Skip if Not 0
INCFSZ
Increment f, Skip if 0
Syntax:
INFSNZ f {,d {,a}}
Syntax:
INCFSZ f {,d {,a}}
Operands:
0 ≤ f ≤ 255
d ∈ [0, 1]
a ∈ [0, 1]
Operands:
0 ≤ f ≤ 255
d ∈ [0, 1]
a ∈ [0, 1]
Operation:
(f) + 1→ dest,
skip if result ≠ 0
Operation:
(f) + 1→ dest,
skip if result = 0
Status Affected:
Encoding:
None
Status Affected:
Encoding:
None
0100
10da
ffff
ffff
0011
11da
ffff
ffff
Description:
The contents of register ‘f’ are
Description:
The contents of register ‘f’ are
incremented. If ‘d’ is ‘0’, the result is
placed in W. If ‘d’ is ‘1’, the result is
placed back in register ‘f’ (default).
incremented. If ‘d’ is ‘0’, the result is
placed in W. If ‘d’ is ‘1’, the result is
placed back in register ‘f’. (default)
If the result is not ‘0’, the next
instruction which is already fetched is
discarded and a NOPis executed
instead, making it a two-cycle
instruction.
If the result is ‘0’, the next instruction
which is already fetched is discarded
and a NOPis executed instead, making
it a two-cycle instruction.
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank (default).
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank (default).
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f ≤ 95 (5Fh). See
Section 23.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f ≤ 95 (5Fh). See
Section 23.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
Words:
Cycles:
1
Words:
Cycles:
1
1(2)
1(2)
Note: 3 cycles if skip and followed
by a 2-word instruction.
Note: 3 cycles if skip and followed
by a 2-word instruction.
Q Cycle Activity:
Q1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Q2
Q3
Q4
Decode
Read
register ‘f’
Process
Data
Write to
destination
Decode
Read
register ‘f’
Process
Data
Write to
destination
If skip:
Q1
If skip:
Q1
Q2
Q3
Q4
Q2
Q3
Q4
No
No
No
No
No
No
No
No
operation
operation
operation
operation
operation
operation
operation
operation
If skip and followed by 2-word instruction:
If skip and followed by 2-word instruction:
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
No
No
No
No
No
No
No
No
operation
operation
operation
operation
operation
operation
operation
operation
No
No
No
No
No
No
No
No
operation
operation
operation
operation
operation
operation
operation
operation
Example:
HERE
NZERO
ZERO
INCFSZ
:
:
CNT, 1, 0
Example:
HERE
ZERO
NZERO
INFSNZ REG, 1, 0
Before Instruction
PC
After Instruction
Before Instruction
PC
After Instruction
=
Address (HERE)
=
Address (HERE)
REG
If REG
PC
If REG
PC
=
REG + 1
CNT
If CNT
PC
If CNT
PC
=
CNT + 1
≠
=
=
=
0;
=
=
≠
=
0;
Address (NZERO)
0;
Address (ZERO)
Address (ZERO)
0;
Address (NZERO)
© 2007 Microchip Technology Inc.
Preliminary
DS39774C-page 307
PIC18F85J11 FAMILY
IORLW
Inclusive OR Literal with W
IORWF
Inclusive OR W with f
Syntax:
IORLW k
Syntax:
IORWF f {,d {,a}}
Operands:
Operation:
Status Affected:
Encoding:
Description:
0 ≤ k ≤ 255
(W) .OR. k → W
N, Z
Operands:
0 ≤ f ≤ 255
d ∈ [0, 1]
a ∈ [0, 1]
Operation:
(W) .OR. (f) → dest
0000
1001
kkkk
kkkk
Status Affected:
Encoding:
N, Z
The contents of W are ORed with the
eight-bit literal ‘k’. The result is placed
in W.
0001
00da
ffff
ffff
Description:
Inclusive OR W with register ‘f’. If ‘d’ is
‘0’, the result is placed in W. If ‘d’ is ‘1’,
the result is placed back in register ‘f’
(default).
Words:
Cycles:
1
1
Q Cycle Activity:
Q1
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank (default).
Q2
Q3
Q4
Decode
Read
literal ‘k’
Process
Data
Write to
W
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f ≤ 95 (5Fh). See
Section 23.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
Example:
IORLW
35h
Before Instruction
W
=
9Ah
BFh
After Instruction
W
=
Words:
Cycles:
1
1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
register ‘f’
Process
Data
Write to
destination
Example:
IORWF RESULT, 0, 1
Before Instruction
RESULT =
13h
91h
W
=
After Instruction
RESULT =
13h
93h
W
=
DS39774C-page 308
Preliminary
© 2007 Microchip Technology Inc.
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LFSR
Load FSR
MOVF
Move f
Syntax:
LFSR f, k
Syntax:
MOVF f {,d {,a}}
Operands:
0 ≤ f ≤ 2
0 ≤ k ≤ 4095
Operands:
0 ≤ f ≤ 255
d ∈ [0, 1]
a ∈ [0, 1]
Operation:
k → FSRf
Operation:
f → dest
Status Affected:
Encoding:
None
Status Affected:
Encoding:
N, Z
1110
1111
1110
0000
00ff
k kkk
11
kkkk
k kkk
0101
00da
ffff
ffff
7
Description:
The 12-bit literal ‘k’ is loaded into the
File Select Register pointed to by ‘f’.
Description:
The contents of register ‘f’ are moved to
a destination dependent upon the
status of ‘d’. If ‘d’ is ‘0’, the result is
placed in W. If ‘d’ is ‘1’, the result is
placed back in register ‘f’ (default).
Location ‘f’ can be anywhere in the
256-byte bank.
Words:
Cycles:
2
2
Q Cycle Activity:
Q1
Q2
Q3
Q4
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank (default).
Decode
Read literal
‘k’ MSB
Process
Data
Write
literal ‘k’
MSB to
FSRfH
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f ≤ 95 (5Fh). See
Section 23.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
Decode
Read literal
‘k’ LSB
Process
Data
Write literal
‘k’ to FSRfL
Example:
LFSR 2, 3ABh
After Instruction
FSR2H
FSR2L
=
=
03h
ABh
Words:
Cycles:
1
1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
register ‘f’
Process
Data
Write
W
Example:
MOVF
REG, 0, 0
Before Instruction
REG
W
=
=
22h
FFh
After Instruction
REG
W
=
=
22h
22h
© 2007 Microchip Technology Inc.
Preliminary
DS39774C-page 309
PIC18F85J11 FAMILY
MOVFF
Move f to f
MOVFF f ,f
MOVLB
Move Literal to Low Nibble in BSR
Syntax:
Syntax:
MOVLW k
0 ≤ k ≤ 255
k → BSR
None
s
d
Operands:
0 ≤ f ≤ 4095
Operands:
Operation:
Status Affected:
Encoding:
Description:
s
0 ≤ f ≤ 4095
d
Operation:
(f ) → f
s
d
Status Affected:
None
0000
0001
kkkk
kkkk
Encoding:
1st word (source)
2nd word (destin.)
The eight-bit literal ‘k’ is loaded into the
Bank Select Register (BSR). The value
of BSR<7:4> always remains ‘0’
1100
1111
ffff
ffff
ffff
ffff
ffff
ffff
s
d
Description:
The contents of source register, ‘f ’, are
regardless of the value of k :k .
s
7 4
moved to destination register, ‘f ’.
d
Words:
Cycles:
1
1
Location of source, ‘f ’, can be
s
anywhere in the 4096-byte data space
(000h to FFFh) and location of
Q Cycle Activity:
Q1
destination, ‘f ’, can also be anywhere
d
Q2
Q3
Q4
from 000h to FFFh.
Decode
Read
Process
Data
Write literal
‘k’ to BSR
Either source or destination can be W
(a useful special situation).
literal ‘k’
MOVFFis particularly useful for
transferring a data memory location to a
peripheral register (such as the transmit
buffer or an I/O port).
Example:
MOVLB
5
Before Instruction
BSR Register =
After Instruction
BSR Register =
02h
05h
The MOVFFinstruction cannot use the
PCL, TOSU, TOSH or TOSL as the
destination register
Words:
Cycles:
2
2
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
register ‘f’
(src)
Process
Data
No
operation
Decode
No
operation
No
operation
Write
register ‘f’
(dest)
No dummy
read
Example:
MOVFF
REG1, REG2
Before Instruction
REG1
REG2
=
=
33h
11h
After Instruction
REG1
REG2
=
=
33h
33h
DS39774C-page 310
Preliminary
© 2007 Microchip Technology Inc.
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MOVLW
Move Literal to W
MOVWF
Move W to f
Syntax:
MOVLW k
0 ≤ k ≤ 255
k → W
Syntax:
MOVWF f {,a}
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Operands:
0 ≤ f ≤ 255
a ∈ [0, 1]
Operation:
(W) → f
None
Status Affected:
Encoding:
None
0000
1110
kkkk
kkkk
0110
111a
ffff
ffff
The eight-bit literal ‘k’ is loaded into W.
Description:
Move data from W to register ‘f’.
Location ‘f’ can be anywhere in the
256-byte bank.
1
1
Cycles:
Q Cycle Activity:
Q1
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank (default).
Q2
Q3
Q4
Decode
Read
literal ‘k’
Process
Data
Write to
W
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f ≤ 95 (5Fh). See
Section 23.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
Example:
MOVLW
5Ah
After Instruction
W
=
5Ah
Words:
Cycles:
1
1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
register ‘f’
Process
Data
Write
register ‘f’
Example:
MOVWF
REG, 0
Before Instruction
W
REG
=
=
4Fh
FFh
After Instruction
W
REG
=
=
4Fh
4Fh
© 2007 Microchip Technology Inc.
Preliminary
DS39774C-page 311
PIC18F85J11 FAMILY
MULLW
Multiply Literal with W
MULWF
Multiply W with f
Syntax:
MULLW k
Syntax:
MULWF f {,a}
Operands:
Operation:
Status Affected:
Encoding:
Description:
0 ≤ k ≤ 255
Operands:
0 ≤ f ≤ 255
a ∈ [0, 1]
(W) x k → PRODH:PRODL
None
Operation:
(W) x (f) → PRODH:PRODL
Status Affected:
Encoding:
None
0000
1101
kkkk
kkkk
0000
001a
ffff
ffff
An unsigned multiplication is carried
out between the contents of W and the
8-bit literal ‘k’. The 16-bit result is
placed in the PRODH:PRODL register
pair. PRODH contains the high byte.
Description:
An unsigned multiplication is carried out
between the contents of W and the
register file location, ‘f’. The 16-bit result is
stored in the PRODH:PRODL register
pair. PRODH contains the high byte. Both
W and ‘f’ are unchanged.
W is unchanged.
None of the Status flags are affected.
None of the Status flags are affected.
Note that neither Overflow nor Carry is
possible in this operation. A Zero result
is possible but not detected.
Note that neither Overflow nor Carry is
possible in this operation. A Zero result is
possible but not detected.
Words:
Cycles:
1
1
If ‘a’ is ‘0’, the Access Bank is selected. If
‘a’ is ‘1’, the BSR is used to select the
GPR bank (default).
Q Cycle Activity:
Q1
Q2
Q3
Q4
If ‘a’ is ‘0’ and the extended instruction set
is enabled, this instruction operates in
Indexed Literal Offset Addressing mode
whenever f ≤ 95 (5Fh). See
Section 23.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
Decode
Read
literal ‘k’
Process
Data
Write
registers
PRODH:
PRODL
Example:
MULLW
0C4h
Words:
Cycles:
1
1
Before Instruction
W
PRODH
PRODL
=
=
=
E2h
?
?
Q Cycle Activity:
Q1
Q2
Q3
Q4
After Instruction
Decode
Read
register ‘f’
Process
Data
Write
W
PRODH
PRODL
=
=
=
E2h
ADh
08h
registers
PRODH:
PRODL
Example:
MULWF
REG, 1
Before Instruction
W
=
=
=
=
C4h
REG
B5h
?
PRODH
PRODL
?
After Instruction
W
=
=
=
=
C4h
B5h
8Ah
94h
REG
PRODH
PRODL
DS39774C-page 312
Preliminary
© 2007 Microchip Technology Inc.
PIC18F85J11 FAMILY
NEGF
Negate f
NOP
No Operation
Syntax:
NEGF f {,a}
Syntax:
NOP
Operands:
0 ≤ f ≤ 255
a ∈ [0, 1]
Operands:
Operation:
Status Affected:
Encoding:
None
No operation
None
Operation:
(f) + 1→ f
Status Affected:
Encoding:
N, OV, C, DC, Z
0000
1111
0000
xxxx
0000
xxxx
0000
xxxx
0110
110a
ffff
ffff
Description:
Location ‘f’ is negated using two’s
complement. The result is placed in the
data memory location ‘f’.
Description:
Words:
No operation.
1
1
Cycles:
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank (default).
Q Cycle Activity:
Q1
Q2
Q3
No
operation
Q4
Decode
No
operation
No
operation
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f ≤ 95 (5Fh). See
Section 23.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
Example:
None.
Words:
Cycles:
1
1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
register ‘f’
Process
Data
Write
register ‘f’
Example:
NEGF
REG, 1
Before Instruction
REG
After Instruction
REG
=
0011 1010 [3Ah]
1100 0110 [C6h]
=
© 2007 Microchip Technology Inc.
Preliminary
DS39774C-page 313
PIC18F85J11 FAMILY
POP
Pop Top of Return Stack
PUSH
Push Top of Return Stack
Syntax:
POP
Syntax:
PUSH
Operands:
Operation:
Status Affected:
Encoding:
Description:
None
Operands:
Operation:
Status Affected:
Encoding:
Description:
None
(TOS) → bit bucket
(PC + 2) → TOS
None
None
0000
0000
0000
0110
0000
0000
0000
0101
The TOS value is pulled off the return
stack and is discarded. The TOS value
then becomes the previous value that
was pushed onto the return stack.
This instruction is provided to enable
the user to properly manage the return
stack to incorporate a software stack.
The PC + 2 is pushed onto the top of
the return stack. The previous TOS
value is pushed down on the stack.
This instruction allows implementing a
software stack by modifying TOS and
then pushing it onto the return stack.
Words:
Cycles:
1
1
Words:
Cycles:
1
1
Q Cycle Activity:
Q1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Q2
Q3
Q4
Decode
PUSH
No
No
Decode
No
operation
POP TOS
value
No
operation
PC + 2 onto
return stack
operation
operation
Example:
POP
Example:
PUSH
GOTO
NEW
Before Instruction
Before Instruction
TOS
Stack (1 level down)
TOS
PC
=
=
345Ah
0124h
=
=
0031A2h
014332h
After Instruction
After Instruction
PC
=
=
=
0126h
0126h
345Ah
TOS
TOS
PC
=
=
014332h
NEW
Stack (1 level down)
DS39774C-page 314
Preliminary
© 2007 Microchip Technology Inc.
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RCALL
Relative Call
RESET
Reset
Syntax:
RCALL n
Syntax:
RESET
None
Operands:
Operation:
-1024 ≤ n ≤ 1023
Operands:
Operation:
(PC) + 2 → TOS,
(PC) + 2 + 2n → PC
Reset all registers and flags that are
affected by a MCLR Reset.
Status Affected:
Encoding:
None
Status Affected:
Encoding:
All
1101
1nnn
nnnn
nnnn
0000
0000
1111
1111
Description:
Subroutine call with a jump up to 1K
from the current location. First, return
address (PC + 2) is pushed onto the
stack. Then, add the 2’s complement
number, ‘2n’, to the PC. Since the PC
will have incremented to fetch the next
instruction, the new address will be
PC + 2 + 2n. This instruction is a
two-cycle instruction.
Description:
This instruction provides a way to
execute a MCLR Reset in software.
Words:
Cycles:
1
1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Start
No
No
Reset
operation
operation
Words:
Cycles:
1
2
Example:
RESET
Q Cycle Activity:
Q1
After Instruction
Registers =
Q2
Q3
Q4
Reset Value
Reset Value
Flags*
=
Decode
Read literal
‘n’
Process
Data
Write to PC
PUSH PC
to stack
No
No
No
No
operation
operation
operation
operation
Example:
HERE
RCALL Jump
Before Instruction
PC
After Instruction
PC
TOS =
=
Address (HERE)
=
Address (Jump)
Address (HERE + 2)
© 2007 Microchip Technology Inc.
Preliminary
DS39774C-page 315
PIC18F85J11 FAMILY
RETFIE
Return from Interrupt
RETLW
Return Literal to W
Syntax:
RETFIE {s}
Syntax:
RETLW k
Operands:
Operation:
s ∈ [0, 1]
Operands:
Operation:
0 ≤ k ≤ 255
(TOS) → PC,
k → W,
1→ GIE/GIEH or PEIE/GIEL;
if s = 1,
(TOS) → PC,
PCLATU, PCLATH are unchanged
(WS) → W,
(STATUSS) → STATUS,
(BSRS) → BSR,
Status Affected:
Encoding:
None
0000
1100
kkkk
kkkk
PCLATU, PCLATH are unchanged
Description:
W is loaded with the eight-bit literal ‘k’.
The program counter is loaded from the
top of the stack (the return address).
The high address latch (PCLATH)
remains unchanged.
Status Affected:
Encoding:
GIE/GIEH, PEIE/GIEL.
0000
0000
0001
000s
Description:
Return from interrupt. Stack is popped
and Top-of-Stack (TOS) is loaded into
the PC. Interrupts are enabled by
setting either the high or low priority
global interrupt enable bit. If ‘s’ = 1, the
contents of the shadow registers, WS,
STATUSS and BSRS, are loaded into
their corresponding registers, W,
Words:
Cycles:
1
2
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
literal ‘k’
Process
Data
POP PC
from stack,
write to W
STATUS and BSR. If ‘s’ = 0, no update
of these registers occurs (default).
No
operation
No
No
No
Words:
Cycles:
1
2
operation
operation
operation
Q Cycle Activity:
Q1
Example:
Q2
Q3
Q4
CALL TABLE ; W contains table
; offset value
Decode
No
operation
No
operation
POP PC
from stack
; W now has
; table value
Set GIEH or
GIEL
:
No
operation
No
operation
No
operation
No
operation
TABLE
ADDWF PCL ; W = offset
RETLW k0
RETLW k1
:
; Begin table
;
Example:
RETFIE
1
After Interrupt
:
PC
=
=
=
=
=
TOS
WS
RETLW kn
; End of table
W
BSR
STATUS
BSRS
STATUSS
1
Before Instruction
GIE/GIEH, PEIE/GIEL
W
=
07h
After Instruction
W
=
value of kn
DS39774C-page 316
Preliminary
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RETURN
Return from Subroutine
RLCF
Rotate Left f through Carry
Syntax:
RETURN {s}
Syntax:
RLCF f {,d {,a}}
Operands:
Operation:
s ∈ [0, 1]
Operands:
0 ≤ f ≤ 255
d ∈ [0, 1]
a ∈ [0, 1]
(TOS) → PC;
if s = 1,
(WS) → W,
Operation:
(f<n>) → dest<n + 1>,
(f<7>) → C,
(C) → dest<0>
(STATUSS) → STATUS,
(BSRS) → BSR,
PCLATU, PCLATH are unchanged
Status Affected:
Encoding:
C, N, Z
Status Affected:
Encoding:
None
0011
01da
ffff
ffff
0000
0000
0001
001s
Description:
The contents of register ‘f’ are rotated
one bit to the left through the Carry flag.
If ‘d’ is ‘0’, the result is placed in W. If ‘d’
is ‘1’, the result is stored back in register
‘f’ (default).
Description:
Return from subroutine. The stack is
popped and the top of the stack (TOS)
is loaded into the program counter. If
‘s’= 1, the contents of the shadow
registers, WS, STATUSS and BSRS,
are loaded into their corresponding
registers, W, STATUS and BSR. If
‘s’ = 0, no update of these registers
occurs (default).
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank (default).
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f ≤ 95 (5Fh). See
Section 23.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
Words:
Cycles:
1
2
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
No
operation
Process
Data
POP PC
register f
C
from stack
No
operation
No
operation
No
operation
No
operation
Words:
Cycles:
1
1
Q Cycle Activity:
Q1
Example:
RETURN
Q2
Q3
Q4
Decode
Read
register ‘f’
Process
Data
Write to
destination
After Instruction:
PC = TOS
Example:
RLCF
REG, 0, 0
Before Instruction
REG
C
=
=
1110 0110
0
After Instruction
REG
W
C
=
=
=
1110 0110
1100 1100
1
© 2007 Microchip Technology Inc.
Preliminary
DS39774C-page 317
PIC18F85J11 FAMILY
RLNCF
Rotate Left f (No Carry)
RRCF
Rotate Right f through Carry
Syntax:
RLNCF f {,d {,a}}
Syntax:
RRCF f {,d {,a}}
Operands:
0 ≤ f ≤ 255
d ∈ [0, 1]
a ∈ [0, 1]
Operands:
0 ≤ f ≤ 255
d ∈ [0, 1]
a ∈ [0, 1]
Operation:
(f<n>) → dest<n + 1>,
(f<7>) → dest<0>
Operation:
(f<n>) → dest<n – 1>,
(f<0>) → C,
(C) → dest<7>
Status Affected:
Encoding:
N, Z
Status Affected:
Encoding:
C, N, Z
0100
01da
ffff
ffff
0011
00da
ffff
ffff
Description:
The contents of register ‘f’ are rotated
one bit to the left. If ‘d’ is ‘0’, the result
is placed in W. If ‘d’ is ‘1’, the result is
stored back in register ‘f’ (default).
Description:
The contents of register ‘f’ are rotated
one bit to the right through the Carry
flag. If ‘d’ is ‘0’, the result is placed in W.
If ‘d’ is ‘1’, the result is placed back in
register ‘f’ (default).
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank (default).
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank (default).
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f ≤ 95 (5Fh). See
Section 23.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f ≤ 95 (5Fh). See
Section 23.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
register f
register f
C
Words:
Cycles:
1
1
Words:
Cycles:
1
1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Q Cycle Activity:
Q1
Decode
Read
register ‘f’
Process
Data
Write to
destination
Q2
Q3
Q4
Decode
Read
register ‘f’
Process
Data
Write to
destination
Example:
RLNCF
REG, 1, 0
Before Instruction
REG
After Instruction
Example:
RRCF
REG, 0, 0
=
1010 1011
0101 0111
Before Instruction
REG
=
REG
C
=
=
1110 0110
0
After Instruction
REG
W
C
=
=
=
1110 0110
0111 0011
0
DS39774C-page 318
Preliminary
© 2007 Microchip Technology Inc.
PIC18F85J11 FAMILY
RRNCF
Rotate Right f (No Carry)
SETF
Set f
Syntax:
RRNCF f {,d {,a}}
Syntax:
SETF f {,a}
Operands:
0 ≤ f ≤ 255
d ∈ [0, 1]
a ∈ [0, 1]
Operands:
0 ≤ f ≤ 255
a ∈ [0, 1]
Operation:
FFh → f
None
Operation:
(f<n>) → dest<n – 1>,
(f<0>) → dest<7>
Status Affected:
Encoding:
0110
100a
ffff
ffff
Status Affected:
Encoding:
N, Z
Description:
The contents of the specified register
are set to FFh.
0100
00da
ffff
ffff
Description:
The contents of register ‘f’ are rotated
one bit to the right. If ‘d’ is ‘0’, the result
is placed in W. If ‘d’ is ‘1’, the result is
placed back in register ‘f’ (default).
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank (default).
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f ≤ 95 (5Fh). See
Section 23.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
If ‘a’ is ‘0’, the Access Bank will be
selected, overriding the BSR value. If ‘a’
is ‘1’, then the bank will be selected as
per the BSR value (default).
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f ≤ 95 (5Fh). See
Section 23.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
Words:
Cycles:
1
1
Q Cycle Activity:
Q1
Q2
Q3
Q4
register f
Decode
Read
register ‘f’
Process
Data
Write
register ‘f’
Words:
Cycles:
1
1
Example:
SETF
REG,1
Q Cycle Activity:
Q1
Before Instruction
REG
After Instruction
REG
=
=
5Ah
FFh
Q2
Q3
Q4
Decode
Read
register ‘f’
Process
Data
Write to
destination
Example 1:
RRNCF
REG, 1, 0
Before Instruction
REG
After Instruction
REG
=
1101 0111
1110 1011
RRNCF REG, 0, 0
=
Example 2:
Before Instruction
W
REG
=
=
?
1101 0111
After Instruction
W
REG
=
=
1110 1011
1101 0111
© 2007 Microchip Technology Inc.
Preliminary
DS39774C-page 319
PIC18F85J11 FAMILY
SLEEP
Enter Sleep Mode
SUBFWB
Subtract f from W with Borrow
Syntax:
SLEEP
None
Syntax:
SUBFWB f {,d {,a}}
Operands:
Operation:
Operands:
0 ≤ f ≤ 255
d ∈ [0, 1]
a ∈ [0, 1]
00h → WDT,
0→ WDT postscaler,
1→ TO,
Operation:
(W) – (f) – (C) → dest
0→ PD
Status Affected:
Encoding:
N, OV, C, DC, Z
Status Affected:
Encoding:
TO, PD
0101
01da
ffff
ffff
0000
0000
0000
0011
Description:
Subtract register ‘f’ and Carry flag
(borrow) from W (2’s complement
method). If ‘d’ is ‘0’, the result is stored in
W. If ‘d’ is ‘1’, the result is stored in
register ‘f’ (default).
Description:
The Power-Down status bit (PD) is
cleared. The Time-out status bit (TO)
is set. The Watchdog Timer and its
postscaler are cleared.
The processor is put into Sleep mode
with the oscillator stopped.
If ‘a’ is ‘0’, the Access Bank is selected. If
‘a’ is ‘1’, the BSR is used to select the
GPR bank (default).
Words:
Cycles:
1
1
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates in
Indexed Literal Offset Addressing mode
whenever f ≤ 95 (5Fh). See
Q Cycle Activity:
Q1
Q2
Q3
Q4
Section 23.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
Decode
No
operation
Process
Data
Go to
Sleep
Words:
Cycles:
1
1
Example:
SLEEP
Before Instruction
TO
PD
=
=
?
?
Q Cycle Activity:
Q1
Q2
Q3
Q4
After Instruction
Decode
Read
register ‘f’
Process
Data
Write to
destination
TO
PD
=
=
1†
0
Example 1:
SUBFWB
REG, 1, 0
†
If WDT causes wake-up, this bit is cleared.
Before Instruction
REG
W
C
=
=
=
3
2
1
After Instruction
REG
W
C
=
FF
2
=
=
=
=
0
Z
0
1
N
; result is negative
Example 2:
Before Instruction
SUBFWB
REG, 0, 0
REG
W
C
=
=
=
2
5
1
After Instruction
REG
W
C
=
2
3
1
0
0
=
=
=
=
Z
N
; result is positive
Example 3:
Before Instruction
SUBFWB
REG, 1, 0
REG
W
C
=
=
=
1
2
0
After Instruction
REG
W
C
=
0
2
1
1
0
=
=
=
=
Z
; result is zero
N
DS39774C-page 320
Preliminary
© 2007 Microchip Technology Inc.
PIC18F85J11 FAMILY
SUBLW
Subtract W from Literal
SUBWF
Subtract W from f
Syntax:
SUBLW k
Syntax:
SUBWF f {,d {,a}}
Operands:
Operation:
Status Affected:
Encoding:
Description:
0 ≤ k ≤ 255
Operands:
0 ≤ f ≤ 255
d ∈ [0, 1]
a ∈ [0, 1]
k – (W) → W
N, OV, C, DC, Z
Operation:
(f) – (W) → dest
0000
1000
kkkk
kkkk
Status Affected:
Encoding:
N, OV, C, DC, Z
W is subtracted from the eight-bit
literal ‘k’. The result is placed in W.
0101
11da
ffff
ffff
Description:
Subtract W from register ‘f’ (2’s
Words:
Cycles:
1
1
complement method). If ‘d’ is ‘0’, the
result is stored in W. If ‘d’ is ‘1’, the result
is stored back in register ‘f’ (default).
Q Cycle Activity:
Q1
Q2
Q3
Q4
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank (default).
Decode
Read
literal ‘k’
Process
Data
Write to
W
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f ≤ 95 (5Fh). See
Section 23.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
Example 1:
SUBLW 02h
Before Instruction
W
C
=
=
01h
?
After Instruction
W
C
Z
=
01h
=
=
=
1
0
0
; result is positive
Words:
Cycles:
1
1
N
Example 2:
SUBLW 02h
Q Cycle Activity:
Q1
Before Instruction
Q2
Q3
Q4
W
C
=
=
02h
?
Decode
Read
register ‘f’
Process
Data
Write to
destination
After Instruction
W
C
Z
=
00h
Example 1:
SUBWF
REG, 1, 0
=
=
=
1
1
0
; result is zero
Before Instruction
N
REG
W
C
=
=
=
3
2
?
Example 3:
SUBLW 02h
Before Instruction
After Instruction
W
C
=
=
03h
?
REG
W
C
=
1
2
1
0
0
=
=
=
=
; result is positive
After Instruction
Z
W
C
Z
=
FFh ; (2’s complement)
N
=
=
=
0
0
1
; result is negative
Example 2:
Before Instruction
SUBWF
REG, 0, 0
N
REG
W
C
=
=
=
2
2
?
After Instruction
REG
W
C
=
2
0
1
1
0
=
=
=
=
; result is zero
Z
N
Example 3:
Before Instruction
SUBWF
REG, 1, 0
REG
W
C
=
=
=
1
2
?
After Instruction
REG
W
C
=
FFh ; (2’s complement)
2
0
0
1
=
=
=
=
; result is negative
Z
N
© 2007 Microchip Technology Inc.
Preliminary
DS39774C-page 321
PIC18F85J11 FAMILY
SUBWFB
Subtract W from f with Borrow
SWAPF
Swap f
Syntax:
SUBWFB f {,d {,a}}
Syntax:
SWAPF f {,d {,a}}
Operands:
0 ≤ f ≤ 255
d ∈ [0, 1]
a ∈ [0, 1]
Operands:
0 ≤ f ≤ 255
d ∈ [0, 1]
a ∈ [0, 1]
Operation:
(f) – (W) – (C) → dest
Operation:
(f<3:0>) → dest<7:4>,
(f<7:4>) → dest<3:0>
Status Affected:
Encoding:
N, OV, C, DC, Z
0101
10da
ffff
ffff
Status Affected:
Encoding:
None
Description:
Subtract W and the Carry flag (borrow)
from register ‘f’ (2’s complement
method). If ‘d’ is ‘0’, the result is stored
in W. If ‘d’ is ‘1’, the result is stored back
in register ‘f’ (default).
0011
10da
ffff
ffff
Description:
The upper and lower nibbles of register
‘f’ are exchanged. If ‘d’ is ‘0’, the result
is placed in W. If ‘d’ is ‘1’, the result is
placed in register ‘f’ (default).
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank (default).
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank (default).
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f ≤ 95 (5Fh). See
Section 23.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f ≤ 95 (5Fh). See
Section 23.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
Words:
Cycles:
1
1
Words:
Cycles:
1
1
Q Cycle Activity:
Q1
Q Cycle Activity:
Q1
Q2
Read
register ‘f’
Q3
Process
Data
Q4
Write to
destination
Decode
Q2
Q3
Q4
Decode
Read
register ‘f’
Process
Data
Write to
destination
Example 1:
SUBWFB REG, 1, 0
Before Instruction
REG
W
C
=
=
=
19h
0Dh
1
(0001 1001)
(0000 1101)
Example:
SWAPF
REG, 1, 0
Before Instruction
REG
After Instruction
=
53h
35h
After Instruction
REG
W
C
=
0Ch
0Dh
1
0
0
(0000 1011)
(0000 1101)
=
=
=
=
REG
=
Z
N
; result is positive
Example 2:
Before Instruction
SUBWFB REG, 0, 0
REG
W
C
=
=
=
1Bh
1Ah
0
(0001 1011)
(0001 1010)
After Instruction
REG
W
C
=
1Bh
00h
1
1
0
(0001 1011)
=
=
=
=
Z
; result is zero
N
Example 3:
Before Instruction
SUBWFB REG, 1, 0
REG
W
C
=
=
=
03h
0Eh
1
(0000 0011)
(0000 1101)
After Instruction
REG
=
F5h
(1111 0100)
; [2’s comp]
W
C
Z
=
=
=
=
0Eh
0
0
(0000 1101)
N
1
; result is negative
DS39774C-page 322
Preliminary
© 2007 Microchip Technology Inc.
PIC18F85J11 FAMILY
TBLRD
Table Read
TBLRD
Table Read (Continued)
Syntax:
TBLRD ( *; *+; *-; +*)
None
Example 1:
TBLRD *+ ;
Operands:
Operation:
Before Instruction
TABLAT
=
=
=
55h
00A356h
34h
if TBLRD *,
TBLPTR
(Prog Mem (TBLPTR)) → TABLAT;
TBLPTR – No Change
if TBLRD *+,
(Prog Mem (TBLPTR)) → TABLAT;
(TBLPTR) + 1→ TBLPTR
if TBLRD *-,
(Prog Mem (TBLPTR)) → TABLAT;
(TBLPTR) – 1→ TBLPTR
if TBLRD +*,
(TBLPTR) + 1→ TBLPTR;
(Prog Mem (TBLPTR)) → TABLAT
MEMORY(00A356h)
After Instruction
TABLAT
TBLPTR
=
=
34h
00A357h
Example 2:
TBLRD +* ;
Before Instruction
TABLAT
TBLPTR
=
=
=
=
AAh
01A357h
12h
MEMORY(01A357h)
MEMORY(01A358h)
After Instruction
34h
TABLAT
TBLPTR
=
=
34h
01A358h
Status Affected: None
Encoding:
0000
0000
0000
10nn
nn=0 *
=1 *+
=2 *-
=3 +*
Description:
This instruction is used to read the contents
of Program Memory (P.M.). To address the
program memory, a pointer called Table
Pointer (TBLPTR) is used.
The TBLPTR (a 21-bit pointer) points to
each byte in the program memory. TBLPTR
has a 2-Mbyte address range.
TBLPTR<0> = 0:Least Significant Byte of
program memory word
TBLPTR<0> = 1:Most Significant Byte of
program memory word
The TBLRDinstruction can modify the value
of TBLPTR as follows:
•
•
•
•
no change
post-increment
post-decrement
pre-increment
Words:
Cycles:
1
2
Q Cycle Activity:
Q1
Q2
No
Q3
No
Q4
Decode
No
operation
operation
operation
No
No operation
No
No operation
(Write
TABLAT)
operation (Read Program operation
Memory)
© 2007 Microchip Technology Inc.
Preliminary
DS39774C-page 323
PIC18F85J11 FAMILY
TBLWT
Table Write
TBLWT
Table Write (Continued)
Syntax:
TBLWT ( *; *+; *-; +*)
None
Example 1:
TBLWT *+;
Operands:
Operation:
Before Instruction
if TBLWT*,
TABLAT
TBLPTR
HOLDING REGISTER
(00A356h)
=
=
55h
00A356h
(TABLAT) → Holding Register;
TBLPTR – No Change
if TBLWT*+,
(TABLAT) → Holding Register;
(TBLPTR) + 1→ TBLPTR
if TBLWT*-,
(TABLAT) → Holding Register;
(TBLPTR) – 1→ TBLPTR
if TBLWT+*,
(TBLPTR) + 1→ TBLPTR;
(TABLAT) → Holding Register
=
FFh
After Instructions (table write completion)
TABLAT
TBLPTR
HOLDING REGISTER
(00A356h)
=
=
55h
00A357h
=
55h
Example 2:
TBLWT +*;
Before Instruction
TABLAT
TBLPTR
=
=
34h
01389Ah
HOLDING REGISTER
(01389Ah)
Status Affected: None
=
=
FFh
FFh
Encoding:
0000
0000
0000
11nn
nn=0 *
=1 *+
=2 *-
=3 +*
HOLDING REGISTER
(01389Bh)
After Instruction (table write completion)
TABLAT
TBLPTR
=
=
34h
01389Bh
HOLDING REGISTER
(01389Ah)
Description:
This instruction uses the 3 LSBs of
TBLPTR to determine which of the
8 holding registers the TABLAT is written
to. The holding registers are used to
program the contents of Program Memory
(P.M.). (Refer to Section 5.0 “Memory
Organization” for additional details on
programming Flash memory.)
=
=
FFh
34h
HOLDING REGISTER
(01389Bh)
The TBLPTR (a 21-bit pointer) points to
each byte in the program memory.
TBLPTR has a 2-Mbyte address range.
The LSb of the TBLPTR selects which
byte of the program memory location to
access.
TBLPTR<0> = 0:Least Significant Byte
of program memory
word
TBLPTR<0> = 1:Most Significant Byte
of program memory
word
The TBLWT instruction can modify the
value of TBLPTR as follows:
•
•
•
•
no change
post-increment
post-decrement
pre-increment
Words:
1
2
Cycles:
Q Cycle Activity:
Q1
Q2
No
Q3
No
Q4
No
Decode
operation operation operation
No
No No No
operation operation operation operation
(Read
TABLAT)
(Write to
Holding
Register)
DS39774C-page 324
Preliminary
© 2007 Microchip Technology Inc.
PIC18F85J11 FAMILY
TSTFSZ
Test f, Skip if 0
XORLW
Exclusive OR Literal with W
Syntax:
TSTFSZ f {,a}
Syntax:
XORLW k
0 ≤ k ≤ 255
(W) .XOR. k → W
N, Z
Operands:
0 ≤ f ≤ 255
a ∈ [0, 1]
Operands:
Operation:
Status Affected:
Encoding:
Description:
Operation:
skip if f = 0
Status Affected:
Encoding:
None
0000
1010
kkkk
kkkk
0110
011a
ffff
ffff
The contents of W are XORed with
the 8-bit literal ‘k’. The result is placed
in W.
Description:
If ‘f’ = 0, the next instruction fetched
during the current instruction execution
is discarded and a NOPis executed,
making this a two-cycle instruction.
Words:
Cycles:
1
1
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank (default).
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
literal ‘k’
Process
Data
Write to
W
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f ≤ 95 (5Fh). See
Section 23.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
Example:
XORLW
0AFh
Before Instruction
W
=
B5h
1Ah
After Instruction
Words:
Cycles:
1
W
=
1(2)
Note: 3 cycles if skip and followed
by a 2-word instruction.
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
register ‘f’
Process
Data
No
operation
If skip:
Q1
Q2
Q3
Q4
No
No
No
No
operation
operation
operation
operation
If skip and followed by 2-word instruction:
Q1
Q2
Q3
Q4
No
No
No
No
operation
operation
operation
operation
No
No
No
No
operation
operation
operation
operation
Example:
HERE
NZERO
ZERO
TSTFSZ CNT, 1
:
:
Before Instruction
PC
=
Address (HERE)
After Instruction
If CNT
PC
If CNT
PC
=
=
≠
=
00h,
Address (ZERO)
00h,
Address (NZERO)
© 2007 Microchip Technology Inc.
Preliminary
DS39774C-page 325
PIC18F85J11 FAMILY
XORWF
Exclusive OR W with f
Syntax:
XORWF f {,d {,a}}
Operands:
0 ≤ f ≤ 255
d ∈ [0, 1]
a ∈ [0, 1]
Operation:
(W) .XOR. (f) → dest
Status Affected:
Encoding:
N, Z
0001
10da
ffff
ffff
Description:
Exclusive OR the contents of W with
register ‘f’. If ‘d’ is ‘0’, the result is stored
in W. If ‘d’ is ‘1’, the result is stored back
in the register ‘f’ (default).
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank (default).
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f ≤ 95 (5Fh). See
Section 23.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
Words:
Cycles:
1
1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
register ‘f’
Process
Data
Write to
destination
Example:
XORWF
REG, 1, 0
Before Instruction
REG
W
=
=
AFh
B5h
After Instruction
REG
W
=
=
1Ah
B5h
DS39774C-page 326
Preliminary
© 2007 Microchip Technology Inc.
PIC18F85J11 FAMILY
A summary of the instructions in the extended instruc-
tion set is provided in Table 23-3. Detailed descriptions
are provided in Section 23.2.2 “Extended Instruction
Set”. The opcode field descriptions in Table 23-1
(page 286) apply to both the standard and extended
PIC18 instruction sets.
23.2 Extended Instruction Set
In addition to the standard 75 instructions of the PIC18
instruction set, the PIC18F85J11 family of devices also
provides an optional extension to the core CPU func-
tionality. The added features include eight additional
instructions that augment Indirect and Indexed
Addressing operations and the implementation of
Indexed Literal Offset Addressing for many of the
standard PIC18 instructions.
Note:
The instruction set extension and the
Indexed Literal Offset Addressing mode
were designed for optimizing applications
written in C. The user may likely never use
these instructions directly in the assem-
bler. The syntax for these commands is
provided as a reference for users who may
be reviewing code that has been
generated by a compiler.
The additional features of the extended instruction set
are enabled by default on unprogrammed devices.
Users must properly set or clear the XINST Configura-
tion bit during programming to enable or disable these
features.
The instructions in the extended set can all be
classified as literal operations, which either manipulate
the File Select Registers, or use them for Indexed
Addressing. Two of the instructions, ADDFSR and
SUBFSR, each have an additional special instantiation
for using FSR2. These versions (ADDULNK and
SUBULNK) allow for automatic return after execution.
23.2.1
EXTENDED INSTRUCTION SYNTAX
Most of the extended instructions use indexed argu-
ments, using one of the File Select Registers and some
offset to specify a source or destination register. When
an argument for an instruction serves as part of
Indexed Addressing, it is enclosed in square brackets
(“[ ]”). This is done to indicate that the argument is used
as an index or offset. The MPASM™ Assembler will
flag an error if it determines that an index or offset value
is not bracketed.
The extended instructions are specifically implemented
to optimize re-entrant program code (that is, code that
is recursive or that uses a software stack) written in
high-level languages, particularly C. Among other
things, they allow users working in high-level
languages to perform certain operations on data
structures more efficiently. These include:
When the extended instruction set is enabled, brackets
are also used to indicate index arguments in
byte-oriented and bit-oriented instructions. This is in
addition to other changes in their syntax. For more
details, see Section 23.2.3.1 “Extended Instruction
Syntax with Standard PIC18 Commands”.
• Dynamic allocation and deallocation of software
stack space when entering and leaving
subroutines
• Function Pointer invocation
Note:
In the past, square brackets have been
used to denote optional arguments in the
PIC18 and earlier instruction sets. In this
text, and going forward, optional arguments
are denoted by braces (“{ }”).
• Software Stack Pointer manipulation
• Manipulation of variables located in a software
stack
TABLE 23-3: EXTENSIONS TO THE PIC18 INSTRUCTION SET
Mnemonic,
16-Bit Instruction Word
Status
Description
Cycles
Operands
Affected
MSb
LSb
ADDFSR f, k
Add Literal to FSR
Add Literal to FSR2 and Return
Call Subroutine using WREG
1
2
2
2
1110 1000 ffkk kkkk
1110 1000 11kk kkkk
0000 0000 0001 0100
1110 1011 0zzz zzzz
1111 ffff ffff ffff
1110 1011 1zzz zzzz
1111 xxxx xzzz zzzz
1110 1010 kkkk kkkk
1110 1001 ffkk kkkk
1110 1001 11kk kkkk
None
None
None
None
ADDULNK
CALLW
k
MOVSF
zs, fd Move zs (source) to 1st word
fd (destination) 2nd word
MOVSS
zs, zd Move zs (source) to 1st word
zd (destination) 2nd word
2
None
PUSHL
k
Store Literal at FSR2, Decrement FSR2
Subtract Literal from FSR
Subtract Literal from FSR2 and Return
1
1
2
None
None
None
SUBFSR
SUBULNK
f, k
k
© 2007 Microchip Technology Inc.
Preliminary
DS39774C-page 327
PIC18F85J11 FAMILY
23.2.2
EXTENDED INSTRUCTION SET
ADDFSR
Add Literal to FSR
ADDULNK
Add Literal to FSR2 and Return
Syntax:
ADDFSR f, k
Syntax:
ADDULNK k
Operands:
0 ≤ k ≤ 63
f ∈ [ 0, 1, 2 ]
FSR(f) + k → FSR(f)
Operands:
Operation:
0 ≤ k ≤ 63
FSR2 + k → FSR2,
(TOS) → PC
Operation:
Status Affected:
Encoding:
None
Status Affected:
Encoding:
None
1110
1000
ffkk
kkkk
1110
1000
11kk
kkkk
Description:
The 6-bit literal ‘k’ is added to the
contents of the FSR specified by ‘f’.
Description:
The 6-bit literal ‘k’ is added to the
contents of FSR2. A RETURNis then
executed by loading the PC with the
TOS.
Words:
1
1
Cycles:
The instruction takes two cycles to
execute; a NOPis performed during
the second cycle.
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
literal ‘k’
Process
Data
Write to
FSR
This may be thought of as a special
case of the ADDFSRinstruction,
where f = 3 (binary ‘11’); it operates
only on FSR2.
Example:
ADDFSR 2, 23h
Words:
1
2
Before Instruction
FSR2
After Instruction
FSR2
Cycles:
=
03FFh
0422h
Q Cycle Activity:
Q1
Q2
Q3
Q4
=
Decode
Read
literal ‘k’
Process
Data
Write to
FSR
No
No
No
No
Operation
Operation
Operation
Operation
Example:
ADDULNK 23h
Before Instruction
FSR2
PC
=
=
03FFh
0100h
After Instruction
FSR2
PC
=
=
0422h
(TOS)
Note:
All PIC18 instructions may take an optional label argument preceding the instruction mnemonic for use in
symbolic addressing. If a label is used, the instruction format then becomes: {label} instruction argument(s).
DS39774C-page 328
Preliminary
© 2007 Microchip Technology Inc.
PIC18F85J11 FAMILY
CALLW
Subroutine Call Using WREG
MOVSF
Move Indexed to f
Syntax:
CALLW
None
Syntax:
MOVSF [z ], f
s
d
Operands:
Operation:
Operands:
0 ≤ z ≤ 127
s
0 ≤ f ≤ 4095
d
(PC + 2) → TOS,
(W) → PCL,
Operation:
((FSR2) + z ) → f
s
d
(PCLATH) → PCH,
(PCLATU) → PCU
Status Affected:
None
Encoding:
1st word (source)
2nd word (destin.)
Status Affected:
Encoding:
None
1110
1111
1011
ffff
0zzz
ffff
zzzz
ffff
s
d
0000
0000
0001
0100
Description
First, the return address (PC + 2) is
pushed onto the return stack. Next, the
contents of W are written to PCL; the
existing value is discarded. Then, the
contents of PCLATH and PCLATU are
latched into PCH and PCU,
respectively. The second cycle is
executed as a NOPinstruction while the
new next instruction is fetched.
Description:
The contents of the source register are
moved to destination register, ‘f ’. The
d
actual address of the source register is
determined by adding the 7-bit literal
offset, ‘z ’, in the first word to the value
s
of FSR2. The address of the destination
register is specified by the 12-bit literal,
‘f ’, in the second word. Both addresses
d
can be anywhere in the 4096-byte data
space (000h to FFFh).
Unlike CALL, there is no option to
update W, STATUS or BSR.
The MOVSFinstruction cannot use the
PCL, TOSU, TOSH or TOSL as the
destination register.
Words:
Cycles:
1
2
If the resultant source address points to
an Indirect Addressing register, the
value returned will be 00h.
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
WREG
Push PC to
stack
No
operation
Words:
Cycles:
2
2
No
operation
No
operation
No
operation
No
operation
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Determine
source addr source addr source reg
Determine
Read
Example:
HERE
CALLW
Before Instruction
Decode
No
operation
No
operation
Write
register ‘f’
(dest)
PC
=
address (HERE)
PCLATH =
PCLATU =
10h
00h
06h
No dummy
read
W
=
After Instruction
PC
=
001006h
TOS
=
address (HERE + 2)
Example:
MOVSF
[05h], REG2
PCLATH =
PCLATU =
W
10h
00h
06h
Before Instruction
=
FSR2
=
80h
33h
Contents
of 85h
REG2
=
=
11h
After Instruction
FSR2
=
80h
Contents
of 85h
REG2
=
=
33h
33h
© 2007 Microchip Technology Inc.
Preliminary
DS39774C-page 329
PIC18F85J11 FAMILY
MOVSS
Move Indexed to Indexed
PUSHL
Store Literal at FSR2, Decrement FSR2
Syntax:
MOVSS [z ], [z ]
Syntax:
PUSHL k
s
d
Operands:
0 ≤ z ≤ 127
s
Operands:
Operation:
0 ≤ k ≤ 255
0 ≤ z ≤ 127
d
k → (FSR2),
FSR2 – 1→ FSR2
Operation:
((FSR2) + z ) → ((FSR2) + z )
s d
Status Affected:
None
Status Affected:
Encoding:
None
Encoding:
1st word (source)
2nd word (dest.)
1111
1010
kkkk
kkkk
1110
1111
1011
xxxx
1zzz
xzzz
zzzz
zzzz
s
d
Description:
The 8-bit literal ‘k’ is written to the data
memory address specified by FSR2.
FSR2 is decremented by 1 after the
operation.
Description
The contents of the source register are
moved to the destination register. The
addresses of the source and destination
registers are determined by adding the
This instruction allows users to push
values onto a software stack.
7-bit literal offsets, ‘z ’ or ‘z ’,
s
d
respectively, to the value of FSR2. Both
registers can be located anywhere in
the 4096-byte data memory space
(000h to FFFh).
Words:
Cycles:
1
1
Q Cycle Activity:
Q1
The MOVSSinstruction cannot use the
PCL, TOSU, TOSH or TOSL as the
destination register.
Q2
Q3
Q4
Decode
Read ‘k’
Process
data
Write to
destination
If the resultant source address points to
an Indirect Addressing register, the
value returned will be 00h. If the
Example:
PUSHL 08h
resultant destination address points to
an Indirect Addressing register, the
instruction will execute as a NOP.
Before Instruction
FSR2H:FSR2L
Memory (01ECh)
=
=
01ECh
00h
Words:
2
2
After Instruction
Cycles:
FSR2H:FSR2L
Memory (01ECh)
=
=
01EBh
08h
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Determine
Determine
Read
source addr source addr source reg
Decode
Determine
dest addr
Determine
dest addr
Write
to dest reg
Example:
MOVSS [05h], [06h]
Before Instruction
FSR2
=
=
=
80h
33h
11h
Contents
of 85h
Contents
of 86h
After Instruction
FSR2
=
=
=
80h
33h
33h
Contents
of 85h
Contents
of 86h
DS39774C-page 330
Preliminary
© 2007 Microchip Technology Inc.
PIC18F85J11 FAMILY
SUBFSR
Subtract Literal from FSR
SUBULNK
Subtract Literal from FSR2 and Return
Syntax:
SUBFSR f, k
0 ≤ k ≤ 63
f ∈ [ 0, 1, 2 ]
FSRf – k → FSRf
None
Syntax:
SUBULNK k
Operands:
Operands:
Operation:
0 ≤ k ≤ 63
FSR2 – k → FSR2,
(TOS) → PC
Operation:
Status Affected: None
Status Affected:
Encoding:
Encoding:
1110
1001
11kk
kkkk
1110
1001
ffkk
kkkk
Description:
The 6-bit literal, ‘k’, is subtracted from
the contents of the FSR2. A RETURNis
then executed by loading the PC with
the TOS.
Description:
The 6-bit literal, ‘k’, is subtracted
from the contents of the FSR
specified by ‘f’.
Words:
1
1
The instruction takes two cycles to
execute; a NOPis performed during the
second cycle.
Cycles:
Q Cycle Activity:
Q1
Q2
Q3
Q4
This may be thought of as a special case
of the SUBFSRinstruction, where f = 3
(binary ‘11’); it operates only on FSR2.
Decode
Read
register ‘f’
Process
Data
Write to
destination
Words:
1
2
Example:
SUBFSR 2, 23h
03FFh
Cycles:
Before Instruction
FSR2
After Instruction
FSR2
Q Cycle Activity:
Q1
=
Q2
Q3
Q4
Decode
Read
register ‘f’
Process
Data
Write to
destination
=
03DCh
No
No
No
No
Operation
Operation
Operation
Operation
Example:
SUBULNK 23h
Before Instruction
FSR2
PC
=
=
03FFh
0100h
After Instruction
FSR2
PC
=
=
03DCh
(TOS)
© 2007 Microchip Technology Inc.
Preliminary
DS39774C-page 331
PIC18F85J11 FAMILY
23.2.3
BYTE-ORIENTED AND
BIT-ORIENTED INSTRUCTIONS IN
INDEXED LITERAL OFFSET MODE
23.2.3.1
Extended Instruction Syntax with
Standard PIC18 Commands
When the extended instruction set is enabled, the File
Select Register argument, ‘f’, in the standard,
byte-oriented and bit-oriented commands is replaced
with the literal offset value, ‘k’. As already noted, this
occurs only when ‘f’ is less than or equal to 5Fh. When
an offset value is used, it must be indicated by square
brackets (“[ ]”). As with the extended instructions, the
use of brackets indicates to the compiler that the value
is to be interpreted as an index or an offset. Omitting
the brackets, or using a value greater than 5Fh within
the brackets, will generate an error in the MPASM
Assembler.
Note: Enabling the PIC18 instruction set exten-
sion may cause legacy applications to
behave erratically or fail entirely.
In addition to eight new commands in the extended set,
enabling the extended instruction set also enables
Indexed Literal Offset Addressing (Section 5.6.1
“Indexed Addressing with Literal Offset”). This has
a significant impact on the way that many commands of
the standard PIC18 instruction set are interpreted.
When the extended set is disabled, addresses embed-
ded in opcodes are treated as literal memory locations:
either as a location in the Access Bank (a = 0) or in a
GPR bank designated by the BSR (a = 1). When the
extended instruction set is enabled and a = 0, however,
a File Select Register argument of 5Fh or less is inter-
preted as an offset from the pointer value in FSR2 and
not as a literal address. For practical purposes, this
means that all instructions that use the Access RAM bit
as an argument – that is, all byte-oriented and
bit-oriented instructions, or almost half of the core
PIC18 instructions – may behave differently when the
extended instruction set is enabled.
If the index argument is properly bracketed for Indexed
Literal Offset Addressing, the Access RAM argument is
never specified; it will automatically be assumed to be
‘0’. This is in contrast to standard operation (extended
instruction set disabled) when ‘a’ is set on the basis of
the target address. Declaring the Access RAM bit in
this mode will also generate an error in the MPASM
Assembler.
The destination argument, ‘d’, functions as before.
In the latest versions of the MPASM Assembler,
language support for the extended instruction set must
be explicitly invoked. This is done with either the
command line option, /y, or the PE directive in the
source listing.
When the content of FSR2 is 00h, the boundaries of
the Access RAM are essentially remapped to their
original values. This may be useful in creating
backward-compatible code. If this technique is used,
it may be necessary to save the value of FSR2 and
restore it when moving back and forth between C and
assembly routines in order to preserve the Stack
Pointer. Users must also keep in mind the syntax
requirements of the extended instruction set (see
Section 23.2.3.1 “Extended Instruction Syntax
with Standard PIC18 Commands”).
23.2.4
CONSIDERATIONS WHEN
ENABLING THE EXTENDED
INSTRUCTION SET
It is important to note that the extensions to the instruc-
tion set may not be beneficial to all users. In particular,
users who are not writing code that uses a software
stack may not benefit from using the extensions to the
instruction set.
Although the Indexed Literal Offset mode can be very
useful for dynamic stack and pointer manipulation, it
can also be very annoying if a simple arithmetic opera-
tion is carried out on the wrong register. Users who are
accustomed to the PIC18 programming must keep in
mind that, when the extended instruction set is
enabled, register addresses of 5Fh or less are used for
Indexed Literal Offset Addressing.
Additionally, the Indexed Literal Offset Addressing
mode may create issues with legacy applications
written to the PIC18 assembler. This is because
instructions in the legacy code may attempt to address
registers in the Access Bank below 5Fh. Since these
addresses are interpreted as literal offsets to FSR2
when the instruction set extension is enabled, the
application may read or write to the wrong data
addresses.
Representative examples of typical byte-oriented and
bit-oriented instructions in the Indexed Literal Offset
mode are provided on the following page to show how
execution is affected. The operand conditions shown in
the examples are applicable to all instructions of these
types.
When porting an application to the PIC18F85J11 family,
it is very important to consider the type of code. A large,
re-entrant application that is written in C and would ben-
efit from efficient compilation will do well when using the
instruction set extensions. Legacy applications that
heavily use the Access Bank will most likely not benefit
from using the extended instruction set.
DS39774C-page 332
Preliminary
© 2007 Microchip Technology Inc.
PIC18F85J11 FAMILY
ADD W to Indexed
(Indexed Literal Offset mode)
Bit Set Indexed
BSF
ADDWF
(Indexed Literal Offset mode)
Syntax:
ADDWF [k] {,d}
Syntax:
BSF [k], b
Operands:
0 ≤ k ≤ 95
d ∈ [0, 1]
Operands:
0 ≤ f ≤ 95
0 ≤ b ≤ 7
Operation:
(W) + ((FSR2) + k) → dest
Operation:
1→ ((FSR2) + k)<b>
Status Affected:
Encoding:
N, OV, C, DC, Z
Status Affected:
Encoding:
None
0010
01d0
kkkk
kkkk
1000
bbb0
kkkk
kkkk
Description:
The contents of W are added to the
contents of the register indicated by
FSR2, offset by the value, ‘k’.
Description:
Bit ‘b’ of the register indicated by FSR2,
offset by the value, ‘k’, is set.
Words:
Cycles:
1
1
If ‘d’ is ‘0’, the result is stored in W. If ‘d’
is ‘1’, the result is stored back in
register ‘f’ (default).
Q Cycle Activity:
Q1
Q2
Q3
Q4
Words:
Cycles:
1
1
Decode
Read
register ‘f’
Process
Data
Write to
destination
Q Cycle Activity:
Q1
Example:
BSF
[FLAG_OFST], 7
Q2
Q3
Q4
Decode
Read ‘k’
Process
Data
Write to
destination
Before Instruction
FLAG_OFST
FSR2
Contents
of 0A0Ah
=
=
0Ah
0A00h
Example:
ADDWF
[OFST],0
=
55h
D5h
Before Instruction
After Instruction
W
=
=
=
17h
Contents
of 0A0Ah
OFST
FSR2
2Ch
=
0A00h
Contents
of 0A2Ch
=
20h
After Instruction
Set Indexed
(Indexed Literal Offset mode)
SETF
W
=
=
37h
20h
Contents
of 0A2Ch
Syntax:
SETF [k]
Operands:
Operation:
Status Affected:
Encoding:
Description:
0 ≤ k ≤ 95
FFh → ((FSR2) + k)
None
0110
1000
kkkk
kkkk
The contents of the register indicated by
FSR2, offset by ‘k’, are set to FFh.
Words:
Cycles:
1
1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read ‘k’
Process
Data
Write
register
Example:
SETF
[OFST]
2Ch
Before Instruction
OFST
=
=
FSR2
0A00h
Contents
of 0A2Ch
=
00h
After Instruction
Contents
of 0A2Ch
=
FFh
© 2007 Microchip Technology Inc.
Preliminary
DS39774C-page 333
PIC18F85J11 FAMILY
To develop software for the extended instruction set,
the user must enable support for the instructions and
the Indexed Addressing mode in their language tool(s).
Depending on the environment being used, this may be
done in several ways:
23.2.5
SPECIAL CONSIDERATIONS WITH
MICROCHIP MPLAB® IDE TOOLS
The latest versions of Microchip’s software tools have
been designed to fully support the extended instruction
set for the PIC18F85J11 family. This includes the
MPLAB C18 C Compiler, MPASM assembly language
and MPLAB Integrated Development Environment
(IDE).
• A menu option or dialog box within the
environment that allows the user to configure the
language tool and its settings for the project
• A command line option
When selecting
a
target device for software
• A directive in the source code
development, MPLAB IDE will automatically set default
Configuration bits for that device. The default setting for
the XINST Configuration bit is ‘0’, disabling the
extended instruction set and Indexed Literal Offset
Addressing. For proper execution of applications
developed to take advantage of the extended
instruction set, XINST must be set during
programming.
These options vary between different compilers,
assemblers and development environments. Users are
encouraged to review the documentation accompany-
ing their development systems for the appropriate
information.
DS39774C-page 334
Preliminary
© 2007 Microchip Technology Inc.
PIC18F85J11 FAMILY
24.1 MPLAB Integrated Development
Environment Software
24.0 DEVELOPMENT SUPPORT
The PIC® microcontrollers are supported with a full
range of hardware and software development tools:
The MPLAB IDE software brings an ease of software
development previously unseen in the 8/16-bit micro-
controller market. The MPLAB IDE is a Windows®
operating system-based application that contains:
• Integrated Development Environment
- MPLAB® IDE Software
• Assemblers/Compilers/Linkers
- MPASMTM Assembler
• A single graphical interface to all debugging tools
- Simulator
- MPLAB C18 and MPLAB C30 C Compilers
- MPLINKTM Object Linker/
MPLIBTM Object Librarian
- Programmer (sold separately)
- Emulator (sold separately)
- In-Circuit Debugger (sold separately)
• A full-featured editor with color-coded context
• A multiple project manager
- MPLAB ASM30 Assembler/Linker/Library
• Simulators
- MPLAB SIM Software Simulator
• Emulators
• Customizable data windows with direct edit of
contents
- MPLAB ICE 2000 In-Circuit Emulator
- MPLAB REAL ICE™ In-Circuit Emulator
• In-Circuit Debugger
• High-level source code debugging
• Visual device initializer for easy register
initialization
- MPLAB ICD 2
• Mouse over variable inspection
• Device Programmers
• Drag and drop variables from source to watch
windows
- PICSTART® Plus Development Programmer
- MPLAB PM3 Device Programmer
- PICkit™ 2 Development Programmer
• Extensive on-line help
• Integration of select third party tools, such as
HI-TECH Software C Compilers and IAR
C Compilers
• Low-Cost Demonstration and Development
Boards and Evaluation Kits
The MPLAB IDE allows you to:
• Edit your source files (either assembly or C)
• One touch assemble (or compile) and download
to PIC MCU emulator and simulator tools
(automatically updates all project information)
• Debug using:
- Source files (assembly or C)
- Mixed assembly and C
- Machine code
MPLAB IDE supports multiple debugging tools in a
single development paradigm, from the cost-effective
simulators, through low-cost in-circuit debuggers, to
full-featured emulators. This eliminates the learning
curve when upgrading to tools with increased flexibility
and power.
© 2007 Microchip Technology Inc.
Preliminary
DS39774C-page 335
PIC18F85J11 FAMILY
24.2 MPASM Assembler
24.5 MPLAB ASM30 Assembler, Linker
and Librarian
The MPASM Assembler is a full-featured, universal
macro assembler for all PIC MCUs.
MPLAB ASM30 Assembler produces relocatable
machine code from symbolic assembly language for
dsPIC30F devices. MPLAB C30 C Compiler uses the
assembler to produce its object file. The assembler
generates relocatable object files that can then be
archived or linked with other relocatable object files and
archives to create an executable file. Notable features
of the assembler include:
The MPASM Assembler generates relocatable object
files for the MPLINK Object Linker, Intel® standard HEX
files, MAP files to detail memory usage and symbol
reference, absolute LST files that contain source lines
and generated machine code and COFF files for
debugging.
The MPASM Assembler features include:
• Integration into MPLAB IDE projects
• Support for the entire dsPIC30F instruction set
• Support for fixed-point and floating-point data
• Command line interface
• User-defined macros to streamline
assembly code
• Rich directive set
• Conditional assembly for multi-purpose
source files
• Flexible macro language
• MPLAB IDE compatibility
• Directives that allow complete control over the
assembly process
24.6 MPLAB SIM Software Simulator
24.3 MPLAB C18 and MPLAB C30
C Compilers
The MPLAB SIM Software Simulator allows code
development in a PC-hosted environment by simulat-
ing the PIC MCUs and dsPIC® DSCs on an instruction
level. On any given instruction, the data areas can be
examined or modified and stimuli can be applied from
a comprehensive stimulus controller. Registers can be
logged to files for further run-time analysis. The trace
buffer and logic analyzer display extend the power of
the simulator to record and track program execution,
actions on I/O, most peripherals and internal registers.
The MPLAB C18 and MPLAB C30 Code Development
Systems are complete ANSI
C
compilers for
Microchip’s PIC18 and PIC24 families of microcontrol-
lers and the dsPIC30 and dsPIC33 family of digital sig-
nal controllers. These compilers provide powerful
integration capabilities, superior code optimization and
ease of use not found with other compilers.
For easy source level debugging, the compilers provide
symbol information that is optimized to the MPLAB IDE
debugger.
The MPLAB SIM Software Simulator fully supports
symbolic debugging using the MPLAB C18 and
MPLAB C30 C Compilers, and the MPASM and
MPLAB ASM30 Assemblers. The software simulator
offers the flexibility to develop and debug code outside
of the hardware laboratory environment, making it an
excellent, economical software development tool.
24.4 MPLINK Object Linker/
MPLIB Object Librarian
The MPLINK Object Linker combines relocatable
objects created by the MPASM Assembler and the
MPLAB C18 C Compiler. It can link relocatable objects
from precompiled libraries, using directives from a
linker script.
The MPLIB Object Librarian manages the creation and
modification of library files of precompiled code. When
a routine from a library is called from a source file, only
the modules that contain that routine will be linked in
with the application. This allows large libraries to be
used efficiently in many different applications.
The object linker/library features include:
• Efficient linking of single libraries instead of many
smaller files
• Enhanced code maintainability by grouping
related modules together
• Flexible creation of libraries with easy module
listing, replacement, deletion and extraction
DS39774C-page 336
Preliminary
© 2007 Microchip Technology Inc.
PIC18F85J11 FAMILY
24.7 MPLAB ICE 2000
High-Performance
24.9 MPLAB ICD 2 In-Circuit Debugger
Microchip’s In-Circuit Debugger, MPLAB ICD 2, is a
powerful, low-cost, run-time development tool,
connecting to the host PC via an RS-232 or high-speed
USB interface. This tool is based on the Flash PIC
MCUs and can be used to develop for these and other
PIC MCUs and dsPIC DSCs. The MPLAB ICD 2 utilizes
the in-circuit debugging capability built into the Flash
devices. This feature, along with Microchip’s In-Circuit
Serial ProgrammingTM (ICSPTM) protocol, offers cost-
effective, in-circuit Flash debugging from the graphical
user interface of the MPLAB Integrated Development
Environment. This enables a designer to develop and
debug source code by setting breakpoints, single step-
ping and watching variables, and CPU status and
peripheral registers. Running at full speed enables
testing hardware and applications in real time. MPLAB
ICD 2 also serves as a development programmer for
selected PIC devices.
In-Circuit Emulator
The MPLAB ICE 2000 In-Circuit Emulator is intended
to provide the product development engineer with a
complete microcontroller design tool set for PIC
microcontrollers. Software control of the MPLAB ICE
2000 In-Circuit Emulator is advanced by the MPLAB
Integrated Development Environment, which allows
editing, building, downloading and source debugging
from a single environment.
The MPLAB ICE 2000 is a full-featured emulator
system with enhanced trace, trigger and data monitor-
ing features. Interchangeable processor modules allow
the system to be easily reconfigured for emulation of
different processors. The architecture of the MPLAB
ICE 2000 In-Circuit Emulator allows expansion to
support new PIC microcontrollers.
The MPLAB ICE 2000 In-Circuit Emulator system has
been designed as a real-time emulation system with
advanced features that are typically found on more
expensive development tools. The PC platform and
Microsoft® Windows® 32-bit operating system were
chosen to best make these features available in a
simple, unified application.
24.10 MPLAB PM3 Device Programmer
The MPLAB PM3 Device Programmer is a universal,
CE compliant device programmer with programmable
voltage verification at VDDMIN and VDDMAX for
maximum reliability. It features a large LCD display
(128 x 64) for menus and error messages and a modu-
lar, detachable socket assembly to support various
package types. The ICSP™ cable assembly is included
as a standard item. In Stand-Alone mode, the MPLAB
PM3 Device Programmer can read, verify and program
PIC devices without a PC connection. It can also set
code protection in this mode. The MPLAB PM3
connects to the host PC via an RS-232 or USB cable.
The MPLAB PM3 has high-speed communications and
optimized algorithms for quick programming of large
memory devices and incorporates an SD/MMC card for
file storage and secure data applications.
24.8 MPLAB REAL ICE In-Circuit
Emulator System
MPLAB REAL ICE In-Circuit Emulator System is
Microchip’s next generation high-speed emulator for
Microchip Flash DSC® and MCU devices. It debugs and
programs PIC® and dsPIC® Flash microcontrollers with
the easy-to-use, powerful graphical user interface of the
MPLAB Integrated Development Environment (IDE),
included with each kit.
The MPLAB REAL ICE probe is connected to the design
engineer’s PC using a high-speed USB 2.0 interface and
is connected to the target with either a connector
compatible with the popular MPLAB ICD 2 system
(RJ11) or with the new high speed, noise tolerant, low-
voltage differential signal (LVDS) interconnection
(CAT5).
MPLAB REAL ICE is field upgradeable through future
firmware downloads in MPLAB IDE. In upcoming
releases of MPLAB IDE, new devices will be supported,
and new features will be added, such as software break-
points and assembly code trace. MPLAB REAL ICE
offers significant advantages over competitive emulators
including low-cost, full-speed emulation, real-time
variable watches, trace analysis, complex breakpoints, a
ruggedized probe interface and long (up to three meters)
interconnection cables.
© 2007 Microchip Technology Inc.
Preliminary
DS39774C-page 337
PIC18F85J11 FAMILY
24.11 PICSTART Plus Development
Programmer
24.13 Demonstration, Development and
Evaluation Boards
The PICSTART Plus Development Programmer is an
easy-to-use, low-cost, prototype programmer. It
connects to the PC via a COM (RS-232) port. MPLAB
Integrated Development Environment software makes
using the programmer simple and efficient. The
PICSTART Plus Development Programmer supports
most PIC devices in DIP packages up to 40 pins.
Larger pin count devices, such as the PIC16C92X and
PIC17C76X, may be supported with an adapter socket.
The PICSTART Plus Development Programmer is CE
compliant.
A wide variety of demonstration, development and
evaluation boards for various PIC MCUs and dsPIC
DSCs allows quick application development on fully func-
tional systems. Most boards include prototyping areas for
adding custom circuitry and provide application firmware
and source code for examination and modification.
The boards support a variety of features, including LEDs,
temperature sensors, switches, speakers, RS-232
interfaces, LCD displays, potentiometers and additional
EEPROM memory.
The demonstration and development boards can be
used in teaching environments, for prototyping custom
circuits and for learning about various microcontroller
applications.
24.12 PICkit 2 Development Programmer
The PICkit™ 2 Development Programmer is a low-cost
programmer and selected Flash device debugger with
an easy-to-use interface for programming many of
Microchip’s baseline, mid-range and PIC18F families of
Flash memory microcontrollers. The PICkit 2 Starter Kit
includes a prototyping development board, twelve
sequential lessons, software and HI-TECH’s PICC™
Lite C compiler, and is designed to help get up to speed
quickly using PIC® microcontrollers. The kit provides
everything needed to program, evaluate and develop
applications using Microchip’s powerful, mid-range
Flash memory family of microcontrollers.
In addition to the PICDEM™ and dsPICDEM™ demon-
stration/development board series of circuits, Microchip
has a line of evaluation kits and demonstration software
®
for analog filter design, KEELOQ security ICs, CAN,
IrDA®, PowerSmart® battery management, SEEVAL®
evaluation system, Sigma-Delta ADC, flow rate
sensing, plus many more.
Check the Microchip web page (www.microchip.com)
and the latest “Product Selector Guide” (DS00148) for
the complete list of demonstration, development and
evaluation kits.
DS39774C-page 338
Preliminary
© 2007 Microchip Technology Inc.
PIC18F85J11 FAMILY
25.0 ELECTRICAL CHARACTERISTICS
(†)
Absolute Maximum Ratings
Ambient temperature under bias.............................................................................................................-40°C to +100°C
Storage temperature .............................................................................................................................. -65°C to +150°C
Voltage on any digital only I/O pin or MCLR with respect to VSS (except VDD) ........................................... -0.3V to 6.0V
Voltage on any combined digital and analog pin with respect to VSS (except VDD and MCLR)...... -0.3V to (VDD + 0.3V)
Voltage on VDDCORE with respect to VSS................................................................................................... -0.3V to 2.75V
Voltage on VDD with respect to VSS ........................................................................................................... -0.3V to 3.6V
Total power dissipation (Note 1) ...............................................................................................................................1.0W
Maximum current out of VSS pin ...........................................................................................................................300 mA
Maximum current into VDD pin ..............................................................................................................................250 mA
Maximum output current sunk by PORTA<7:6> and any PORTB and PORTC I/O pins.........................................25 mA
Maximum output current sunk by any PORTD, PORTE and PORTJ I/O pins ..........................................................8 mA
Maximum output current sunk by PORTA<5:0> and any PORTF, PORTG and PORTH I/O pins ............................2 mA
Maximum output current sourced by PORTA<7:6> and any PORTB and PORTC I/O pins ...................................25 mA
Maximum output current sourced by any PORTD, PORTE and PORTJ I/O pins.....................................................8 mA
Maximum output current sourced by PORTA<5:0> and any PORTF, PORTG and PORTH I/O pins .......................2 mA
Maximum current sunk by all ports combined.......................................................................................................200 mA
Note 1: Power dissipation is calculated as follows:
Pdis = VDD x {IDD – ∑ IOH} + ∑ {(VDD – VOH) x IOH} + ∑(VOL x IOL)
† NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at those or any other conditions above those
indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for
extended periods may affect device reliability.
© 2007 Microchip Technology Inc.
Preliminary
DS39774C-page 339
PIC18F85J11 FAMILY
FIGURE 25-1:
PIC18F85J11 FAMILY VOLTAGE-FREQUENCY GRAPH,
REGULATOR ENABLED (INDUSTRIAL)(1)
4.0V
3.5V
3.6V
3.0V
2.5V
2.0V
PIC18F6XJ11/8XJ11
2.35V
0
8 MHz
40 MHz
Frequency
Note 1: When the on-chip regulator is enabled, its BOR circuit will automatically trigger a device Reset
before VDD reaches a level at which full-speed operation is not possible.
FIGURE 25-2:
PIC18F85J11 FAMILY VOLTAGE-FREQUENCY GRAPH,
REGULATOR DISABLED (INDUSTRIAL)(1,2)
3.00V
2.75V
2.7V
2.50V
PIC18F6XJ11/8XJ11
2.35V
2.25V
2.00V
8 MHz
40 MHz
Frequency
Note 1: For frequencies between 4 MHz and 40 MHz, FMAX = (51.42 MHz/V) * (VDDCORE – 2V) + 4 MHz.
2: When the on-chip voltage regulator is disabled, VDD and VDDCORE must be maintained so that
VDDCORE ≤ VDD ≤ 3.6V.
DS39774C-page 340
Preliminary
© 2007 Microchip Technology Inc.
PIC18F85J11 FAMILY
25.1 DC Characteristics: Supply Voltage
PIC18F85J11 Family (Industrial)
PIC18F85J11 Family
Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C ≤ TA ≤ +85°C for industrial
(Industrial)
Param
Symbol
No.
Characteristic
Supply Voltage
Min
Typ
Max
Units
Conditions
D001
VDD
VDDCORE
—
—
3.6
3.6
V
V
ENVREG tied to VSS
ENVREG tied to VDD
2.0
D001B VDDCORE External Supply for
2.0
—
2.70
V
ENVREG tied to VSS
Microcontroller Core
D001C AVDD
D001D AVSS
Analog Supply Voltage
VDD – 0.3
—
—
—
VDD + 0.3
VSS + 0.3
—
V
V
V
Analog Ground Potential VSS – 0.3
D002
VDR
RAM Data Retention
Voltage(1)
1.5
D003
VPOR
VDD Start Voltage
to ensure internal
Power-on Reset signal
—
—
—
0.7
—
V
See Section 4.3 “Power-on
Reset (POR)” for details
D004
D005
SVDD
VBOR
VDD Rise Rate
to ensure internal
Power-on Reset signal
0.05
—
V/ms See Section 4.3 “Power-on
Reset (POR)” for details
Brown-out Reset Voltage
1.9
—
V
Note 1: This is the limit to which VDD can be lowered in Sleep mode, or during a device Reset, without losing RAM data.
© 2007 Microchip Technology Inc.
Preliminary
DS39774C-page 341
PIC18F85J11 FAMILY
25.2 DC Characteristics: Power-Down and Supply Current
PIC18F85J11 Family (Industrial)
PIC18F85J11 Family
Standard Operating Conditions (unless otherwise stated)
(Industrial)
Operating temperature
-40°C ≤ TA ≤ +85°C for industrial
Param
No.
Device
Typ Max Units
Conditions
Power-Down Current (IPD)(1)
All devices 0.2
0.9
0.9
5
µA
µA
µA
µA
µA
µA
µA
µA
µA
-40°C
+25°C
+85°C
-40°C
+25°C
+85°C
-40°C
+25°C
+85°C
VDD = 2.0V,
VDDCORE = 2.0V
(Sleep mode)(4)
0.1
2.4
All devices 0.5
0.9
0.9
5
VDD = 2.5V,
VDDCORE = 2.5V
(Sleep mode)(4)
0.1
2.7
All devices 2.7
6
VDD = 3.3V
3.5
6.7
6
(Sleep mode)(5)
12
Legend: TBD = To Be Determined
Note 1: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is
measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS, and
all features that add delta current disabled (such as WDT, Timer1 oscillator, BOR, etc.).
2: The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as
I/O pin loading and switching rate, oscillator type and circuit, internal code execution pattern and
temperature, also have an impact on the current consumption.
The test conditions for all IDD measurements in active operation mode are:
OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD;
MCLR = VDD; WDT enabled/disabled as specified.
3: Standard, low-cost 32 kHz crystals have an operating temperature range of -10°C to +70°C. Extended tem-
perature crystals are available at a much higher cost.
4: Voltage regulator disabled (ENVREG tied to VSS).
5: Voltage regulator enabled (ENVREG tied to VDD).
DS39774C-page 342
Preliminary
© 2007 Microchip Technology Inc.
PIC18F85J11 FAMILY
25.2 DC Characteristics: Power-Down and Supply Current
PIC18F85J11 Family (Industrial) (Continued)
PIC18F85J11 Family
Standard Operating Conditions (unless otherwise stated)
(Industrial)
Operating temperature
-40°C ≤ TA ≤ +85°C for industrial
Param
No.
Device
Supply Current (IDD)(2)
Typ Max Units
Conditions
All devices 6.5
16
16
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
-40°C
VDD = 2.0V,
7
+25°C
VDDCORE = 2.0V(4)
9.5
20
+85°C
-40°C
FOSC = 31 kHz
(RC_RUN mode,
internal oscillator
source)
All devices 10
18
VDD = 2.5V,
10.5
18
+25°C
VDDCORE = 2.5V(4)
12.5
24
+85°C
-40°C
All devices 41
100
100
110
750
750
840
850
850
910
900
900
990
52
+25°C
+85°C
-40°C
+25°C
+85°C
-40°C
+25°C
+85°C
-40°C
+25°C
+85°C
-40°C
+25°C
+85°C
-40°C
+25°C
+85°C
-40°C
+25°C
+85°C
VDD = 3.3V(5)
71
All devices 359
VDD = 2.0V,
387
VDDCORE = 2.0V(4)
407
FOSC = 1 MHz
(INTOSC_RUN mode,
internal oscillator
source)
All devices 438
VDD = 2.5V,
470
VDDCORE = 2.5V(4)
491
All devices 486
526
VDD = 3.3V(5)
564
All devices 0.76 1.45 mA
0.84 1.45 mA
VDD = 2.0V,
VDDCORE = 2.0V(4)
0.9
1.6
mA
FOSC = 4 MHz
(INTOSC_RUN mode,
internal oscillator
source)
All devices 1.1
1.63 mA
VDD = 2.5V,
1.18 1.63 mA
1.24 1.75 mA
VDDCORE = 2.5V(4)
All devices 1.25 1.86 mA
1.29 1.86 mA
VDD = 3.3V(5)
1.37 1.94 mA
Legend: TBD = To Be Determined
Note 1: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is
measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS, and
all features that add delta current disabled (such as WDT, Timer1 oscillator, BOR, etc.).
2: The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as
I/O pin loading and switching rate, oscillator type and circuit, internal code execution pattern and
temperature, also have an impact on the current consumption.
The test conditions for all IDD measurements in active operation mode are:
OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD;
MCLR = VDD; WDT enabled/disabled as specified.
3: Standard, low-cost 32 kHz crystals have an operating temperature range of -10°C to +70°C. Extended tem-
perature crystals are available at a much higher cost.
4: Voltage regulator disabled (ENVREG tied to VSS).
5: Voltage regulator enabled (ENVREG tied to VDD).
© 2007 Microchip Technology Inc.
Preliminary
DS39774C-page 343
PIC18F85J11 FAMILY
25.2 DC Characteristics: Power-Down and Supply Current
PIC18F85J11 Family (Industrial) (Continued)
PIC18F85J11 Family
Standard Operating Conditions (unless otherwise stated)
(Industrial)
Operating temperature
-40°C ≤ TA ≤ +85°C for industrial
Param
No.
Device
Supply Current (IDD)(2)
Typ Max Units
Conditions
All devices 2.4
8
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
-40°C
VDD = 2.0V,
2.5
8
+25°C
VDDCORE = 2.0V(4)
4.8
12
+85°C
-40°C
FOSC = 31 kHz
(RC_IDLE mode,
internal oscillator
source)
All devices 3.2
9
VDD = 2.5V,
3.2
9
+25°C
VDDCORE = 2.5V(4)
6
14
+85°C
-40°C
All devices 62
82
42
82
+25°C
+85°C
-40°C
+25°C
+85°C
-40°C
+25°C
+85°C
-40°C
+25°C
+85°C
-40°C
+25°C
+85°C
-40°C
+25°C
+85°C
-40°C
+25°C
+85°C
VDD = 3.3V(5)
59
97
All devices 251
570
570
590
610
610
650
710
710
790
760
760
800
850
850
900
950
950
VDD = 2.0V,
264
VDDCORE = 2.0V(4)
272
FOSC = 1 MHz
(INTOSC_IDLE mode,
internal oscillator
source)
All devices 284
VDD = 2.5V,
284
VDDCORE = 2.5V(4)
293
All devices 295
323
VDD = 3.3V(5)
392
All devices 368
VDD = 2.0V,
362
VDDCORE = 2.0V(4)
370
All devices 400
410
FOSC = 4 MHz
(INTOSC_IDLE mode,
internal oscillator
source)
VDD = 2.5V,
VDDCORE = 2.5V(4)
418
All devices 460
462
VDD = 3.3V(5)
486 1,000 µA
Legend: TBD = To Be Determined
Note 1: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is
measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS, and
all features that add delta current disabled (such as WDT, Timer1 oscillator, BOR, etc.).
2: The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as
I/O pin loading and switching rate, oscillator type and circuit, internal code execution pattern and
temperature, also have an impact on the current consumption.
The test conditions for all IDD measurements in active operation mode are:
OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD;
MCLR = VDD; WDT enabled/disabled as specified.
3: Standard, low-cost 32 kHz crystals have an operating temperature range of -10°C to +70°C. Extended tem-
perature crystals are available at a much higher cost.
4: Voltage regulator disabled (ENVREG tied to VSS).
5: Voltage regulator enabled (ENVREG tied to VDD).
DS39774C-page 344
Preliminary
© 2007 Microchip Technology Inc.
PIC18F85J11 FAMILY
25.2 DC Characteristics: Power-Down and Supply Current
PIC18F85J11 Family (Industrial) (Continued)
PIC18F85J11 Family
Standard Operating Conditions (unless otherwise stated)
(Industrial)
Operating temperature
-40°C ≤ TA ≤ +85°C for industrial
Param
No.
Device
Supply Current (IDD)(2)
Typ Max Units
Conditions
All devices 165
490
490
490
670
670
670
850
850
850
2.2
2.2
2.2
2.5
2.5
2.5
3.0
3.0
3.0
14
µA
µA
-40°C
VDD = 2.0V,
180
+25°C
VDDCORE = 2.0V(4)
200
µA
+85°C
-40°C
All devices 256
µA
FOSC = 1 MHZ
(PRI_RUN mode,
EC oscillator)
VDD = 2.5V,
260
µA
+25°C
VDDCORE = 2.5V(4)
280
µA
+85°C
-40°C
All devices 460
µA
456
µA
+25°C
+85°C
-40°C
+25°C
+85°C
-40°C
+25°C
+85°C
-40°C
+25°C
+85°C
-40°C
+25°C
+85°C
-40°C
+25°C
+85°C
VDD = 3.3V(5)
482
µA
All devices 0.63
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
VDD = 2.0V,
0.68
VDDCORE = 2.0V(4)
0.74
All devices 0.91
FOSC = 4 MHz
(PRI_RUN mode,
EC oscillator)
VDD = 2.5V,
1.04
VDDCORE = 2.5V(4)
1.04
All devices 1.32
1.32
VDD = 3.3V(5)
1.41
All devices 7.47
5.81
VDD = 2.5V,
14
VDDCORE = 2.5V(4)
FOSC = 40 MHZ
(PRI_RUN mode,
EC oscillator)
6.32
13
All devices 8.84
8.66
18
18
VDD = 3.3V(5)
7.97
16
Legend: TBD = To Be Determined
Note 1: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is
measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS, and
all features that add delta current disabled (such as WDT, Timer1 oscillator, BOR, etc.).
2: The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as
I/O pin loading and switching rate, oscillator type and circuit, internal code execution pattern and
temperature, also have an impact on the current consumption.
The test conditions for all IDD measurements in active operation mode are:
OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD;
MCLR = VDD; WDT enabled/disabled as specified.
3: Standard, low-cost 32 kHz crystals have an operating temperature range of -10°C to +70°C. Extended tem-
perature crystals are available at a much higher cost.
4: Voltage regulator disabled (ENVREG tied to VSS).
5: Voltage regulator enabled (ENVREG tied to VDD).
© 2007 Microchip Technology Inc.
Preliminary
DS39774C-page 345
PIC18F85J11 FAMILY
25.2 DC Characteristics: Power-Down and Supply Current
PIC18F85J11 Family (Industrial) (Continued)
PIC18F85J11 Family
Standard Operating Conditions (unless otherwise stated)
(Industrial)
Operating temperature
-40°C ≤ TA ≤ +85°C for industrial
Param
No.
Device
Supply Current (IDD)(2)
Typ Max Units
Conditions
All devices 2.8
3.8
3.8
4.5
mA
mA
mA
-40°C
FOSC = 4 MHZ,
16 MHz internal
(PRI_RUN mode,
HSPLL oscillator)
VDD = 2.0V,
3.02
3.01
+25°C
VDDCORE = 2.0V(4)
+85°C
All devices 4.5
5.4
5.6
5.6
mA
mA
mA
-40°C
FOSC = 4 MHZ,
16 MHz internal
(PRI_RUN mode,
HSPLL oscillator)
VDD = 2.5V,
4.8
+25°C
VDDCORE = 2.5V(4)
+85°C
4.54
All devices 5.72
6.7
6.5
6.5
mA
mA
mA
-40°C
FOSC = 4 MHZ,
16 MHz internal
(PRI_RUN mode,
HSPLL oscillator)
VDD = 3.3V(5)
+25°C
+85°C
5.55
5.3
All devices 7.4
8.5
8.5
7.5
mA
mA
mA
-40°C
FOSC = 10 MHZ,
40 MHz internal
(PRI_RUN mode,
HSPLL oscillator)
VDD = 2.5V,
+25°C
7.23
6.55
VDDCORE = 2.5V(4)
+85°C
All devices 9.74 11.6
9.43 11.6
mA
mA
-40°C
FOSC = 10 MHZ,
40 MHz internal
(PRI_RUN mode,
HSPLL oscillator)
VDD = 3.3V(5)
+25°C
+85°C
8.89 10.5 mA
Legend: TBD = To Be Determined
Note 1: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is
measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS, and
all features that add delta current disabled (such as WDT, Timer1 oscillator, BOR, etc.).
2: The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as
I/O pin loading and switching rate, oscillator type and circuit, internal code execution pattern and
temperature, also have an impact on the current consumption.
The test conditions for all IDD measurements in active operation mode are:
OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD;
MCLR = VDD; WDT enabled/disabled as specified.
3: Standard, low-cost 32 kHz crystals have an operating temperature range of -10°C to +70°C. Extended tem-
perature crystals are available at a much higher cost.
4: Voltage regulator disabled (ENVREG tied to VSS).
5: Voltage regulator enabled (ENVREG tied to VDD).
DS39774C-page 346
Preliminary
© 2007 Microchip Technology Inc.
PIC18F85J11 FAMILY
25.2 DC Characteristics: Power-Down and Supply Current
PIC18F85J11 Family (Industrial) (Continued)
PIC18F85J11 Family
Standard Operating Conditions (unless otherwise stated)
(Industrial)
Operating temperature
-40°C ≤ TA ≤ +85°C for industrial
Param
No.
Device
Supply Current (IDD)(2)
Typ Max Units
Conditions
All devices 50
120
120
130
480
300
270
550
500
460
850
850
800
950
950
900
1.3
1.2
1.2
8
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
mA
mA
mA
mA
mA
mA
mA
mA
mA
-40°C
VDD = 2.0V,
51
+25°C
VDDCORE = 2.0V(4)
54
+85°C
-40°C
All devices 223
FOSC = 1 MHz
(PRI_IDLE mode,
EC oscillator)
VDD = 2.5V,
134
+25°C
VDDCORE = 2.5V(4)
110
+85°C
-40°C
All devices 307
254
+25°C
+85°C
-40°C
+25°C
+85°C
-40°C
+25°C
+85°C
-40°C
+25°C
+85°C
-40°C
+25°C
+85°C
-40°C
+25°C
+85°C
VDD = 3.3V(5)
194
All devices 307
VDD = 2.0V,
200
VDDCORE = 2.0V(4)
202
All devices 483
FOSC = 4 MHz
(PRI_IDLE mode,
EC oscillator)
VDD = 2.5V,
318
VDDCORE = 2.5V(4)
343
All devices 0.52
0.47
VDD = 3.3V(5)
0.47
All devices 2.38
2.04
VDD = 2.5V,
8
VDDCORE = 2.5V(4)
FOSC = 40 MHz
(PRI_IDLE mode,
EC oscillator)
2.52
9
All devices 3.02
2.99
10
10
VDD = 3.3V(5)
4.23
11
Legend: TBD = To Be Determined
Note 1: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is
measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS, and
all features that add delta current disabled (such as WDT, Timer1 oscillator, BOR, etc.).
2: The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as
I/O pin loading and switching rate, oscillator type and circuit, internal code execution pattern and
temperature, also have an impact on the current consumption.
The test conditions for all IDD measurements in active operation mode are:
OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD;
MCLR = VDD; WDT enabled/disabled as specified.
3: Standard, low-cost 32 kHz crystals have an operating temperature range of -10°C to +70°C. Extended tem-
perature crystals are available at a much higher cost.
4: Voltage regulator disabled (ENVREG tied to VSS).
5: Voltage regulator enabled (ENVREG tied to VDD).
© 2007 Microchip Technology Inc.
Preliminary
DS39774C-page 347
PIC18F85J11 FAMILY
25.2 DC Characteristics: Power-Down and Supply Current
PIC18F85J11 Family (Industrial) (Continued)
PIC18F85J11 Family
Standard Operating Conditions (unless otherwise stated)
(Industrial)
Operating temperature
-40°C ≤ TA ≤ +85°C for industrial
Param
No.
Device
Supply Current (IDD)(2)
Typ Max Units
Conditions
All devices 10.5
22
28
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
-10°C
VDD = 2.0V,
13.4
+25°C
VDDCORE = 2.0V(4)
17.6
40
+70°C
-10°C
FOSC = 32 kHz(3)
(SEC_RUN mode,
Timer1 as clock)
All devices 13.2
30
VDD = 2.5V,
16.2
35
+25°C
VDDCORE = 2.5V(4)
20.7
50
+70°C
-10°C
All devices 39
120
150
190
15
58
+25°C
+70°C
-10°C
+25°C
+70°C
-10°C
+25°C
+70°C
-10°C
+25°C
+70°C
VDD = 3.3V(5)
75
All devices 5.7
8.9
VDD = 2.0V,
20
VDDCORE = 2.0V(4)
12.8
26
FOSC = 32 kHz(3)
(SEC_IDLE mode,
Timer1 as clock)
All devices 6.6
9.7
17
VDD = 2.5V,
24
VDDCORE = 2.5V(4)
13.7
30
All devices 39
115
52.8 145
72.7 185
VDD = 3.3V(5)
Legend: TBD = To Be Determined
Note 1: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is
measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS, and
all features that add delta current disabled (such as WDT, Timer1 oscillator, BOR, etc.).
2: The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as
I/O pin loading and switching rate, oscillator type and circuit, internal code execution pattern and
temperature, also have an impact on the current consumption.
The test conditions for all IDD measurements in active operation mode are:
OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD;
MCLR = VDD; WDT enabled/disabled as specified.
3: Standard, low-cost 32 kHz crystals have an operating temperature range of -10°C to +70°C. Extended tem-
perature crystals are available at a much higher cost.
4: Voltage regulator disabled (ENVREG tied to VSS).
5: Voltage regulator enabled (ENVREG tied to VDD).
DS39774C-page 348
Preliminary
© 2007 Microchip Technology Inc.
PIC18F85J11 FAMILY
25.2 DC Characteristics: Power-Down and Supply Current
PIC18F85J11 Family (Industrial) (Continued)
PIC18F85J11 Family
Standard Operating Conditions (unless otherwise stated)
(Industrial)
Operating temperature
-40°C ≤ TA ≤ +85°C for industrial
Param
No.
Device
Typ Max Units
Conditions
Module Differential Currents (ΔIWDT, ΔIOSCB, ΔIAD)
D022
Watchdog Timer 1.6
4
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
-40°C
VDD = 2.0V,
(ΔIWDT)
1.7
1.6
2.5
2.5
2.3
3.8
2.6
2.4
4
4
5
5
5
6
6
6
12.5
12.5
18
12.5
12.5
+25°C
+85°C
-40°C
+25°C
+85°C
-40°C
+25°C
+85°C
-40°C
+25°C
+85°C
-40°C
+25°C
+85°C
-40°C
+25°C
+85°C
-40°C to
+85°C
VDDCORE = 2.0V(4)
VDD = 2.5V,
VDDCORE = 2.5V(4)
VDD = 3.3V(5)
D025
(ΔIOSCB)
Timer1 Oscillator 6.6
VDD = 2.0V,
32 kHz on Timer1(3)
7.9
11.5
7.2
8.1
11.9 18.5
7
9
11
1
VDDCORE = 2.0V(4)
VDD = 2.5V,
32 kHz on Timer1(3)
32 kHz on Timer1(3)
VDDCORE = 2.5V(4)
12.5
12.5
18.5
1.5
VDD = 3.3V(5)
D026
(ΔIAD)
A/D Converter
VDD = 2.0V,
VDDCORE = 2.0V(4)
1
1
1.5
1.5
µA
µA
-40°C to
+85°C
VDD = 2.5V,
A/D on, not converting
VDDCORE = 2.5V(4)
VDD = 3.3V(5)
-40°C to
Legend: TBD = To Be Determined
Note 1: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is
measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS, and
all features that add delta current disabled (such as WDT, Timer1 oscillator, BOR, etc.).
2: The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as
I/O pin loading and switching rate, oscillator type and circuit, internal code execution pattern and
temperature, also have an impact on the current consumption.
The test conditions for all IDD measurements in active operation mode are:
OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD;
MCLR = VDD; WDT enabled/disabled as specified.
3: Standard, low-cost 32 kHz crystals have an operating temperature range of -10°C to +70°C. Extended tem-
perature crystals are available at a much higher cost.
4: Voltage regulator disabled (ENVREG tied to VSS).
5: Voltage regulator enabled (ENVREG tied to VDD).
© 2007 Microchip Technology Inc.
Preliminary
DS39774C-page 349
PIC18F85J11 FAMILY
25.3 DC Characteristics: PIC18F85J11 Family (Industrial)
Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C ≤ TA ≤ +85°C for industrial
DC CHARACTERISTICS
Param
Symbol
No.
Characteristic
Min
Max
Units
Conditions
VIL
Input Low Voltage
All I/O ports:
with TTL buffer
with Schmitt Trigger buffer
MCLR
D030
D031
D032
D033
D033A
VSS
VSS
VSS
VSS
VSS
0.15 VDD
0.2 VDD
0.2 VDD
0.3 VDD
0.2 VDD
V
V
V
V
V
OSC1
OSC1
HS, HSPLL modes
EC, ECPLL modes(1)
D034
T13CKI
VSS
0.3
V
VIH
Input High Voltage
I/O ports with analog functions:
with TTL buffer
D040
D041
0.25 VDD + 0.8V
0.8 VDD
VDD
VDD
V
V
VDD < 3.3V
with Schmitt Trigger buffer
Digital only I/O ports:
with TTL buffer
Dxxx
0.25 VDD + 0.8V
2.0
5.5
5.5
V
V
V
V
V
V
VDD < 3.3V
DxxxA
Dxxx
3.3V ≤ VDD ≤ 3.6V
with Schmitt Trigger buffer
0.8 VDD
0.8 VDD
0.7 VDD
0.8 VDD
5.5
D042
D043
D043A
MCLR
OSC1
OSC1
VDD
VDD
VDD
HS, HSPLL modes
EC, ECPLL modes
D044
T13CKI
1.6
VDD
V
IIL
Input Leakage Current(1)
D060
I/O ports
—
1
µA VSS ≤ VPIN ≤ VDD,
pin at high-impedance
D061
D063
MCLR
—
—
1
1
µA Vss ≤ VPIN ≤ VDD
µA Vss ≤ VPIN ≤ VDD
OSC1
IPU
Weak Pull-up Current
PORTB weak pull-up current
D070
IPURB
30
240
µA VDD = 3.3V, VPIN = VSS
Note 1: Negative current is defined as current sourced by the pin.
DS39774C-page 350
Preliminary
© 2007 Microchip Technology Inc.
PIC18F85J11 FAMILY
25.3 DC Characteristics: PIC18F85J11 Family (Industrial) (Continued)
Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C ≤ TA ≤ +85°C for industrial
DC CHARACTERISTICS
Param
Symbol
No.
Characteristic
Min
Max
Units
Conditions
VOL
Output Low Voltage
D080
I/O ports:
PORTA, PORTF, PORTG,
PORTH
—
—
—
—
0.4
0.4
0.4
0.4
V
V
V
V
IOL = 2 mA, VDD = 3.3V,
-40°C to +85°C
PORTD, PORTE, PORTJ
IOL = 3.4 mA, VDD = 3.3V,
-40°C to +85°C
PORTB, PORTC
IOL = 3.4 mA, VDD = 3.3V,
-40°C to +85°C
D083
D090
OSC2/CLKO
IOL = 1.6 mA, VDD = 3.3V,
(EC, ECPLL modes)
Output High Voltage(1)
-40°C to +85°C
VOH
I/O ports:
V
V
PORTA, PORTF, PORTG,
PORTH
2.4
2.4
2.4
2.4
—
—
—
—
IOH = -2 mA, VDD = 3.3V,
-40°C to +85°C
IOH = -2 mA, VDD = 3.3V,
-40°C to +85°C
PORTD, PORTE, PORTJ
V
V
V
PORTB, PORTC
IOH = -2 mA, VDD = 3.3V,
-40°C to +85°C
D092
D100
OSC2/CLKO
(INTOSC, EC, ECPLL modes)
IOH = -1 mA, VDD = 3.3V,
-40°C to +85°C
Capacitive Loading Specs
on Output Pins
COSC2 OSC2 pin
—
15
pF In HS mode when
external clock is used to drive
OSC1
D101
D102
CIO
CB
All I/O pins and OSC2
SCLx, SDAx
—
—
50
pF To meet the AC Timing
Specifications
pF I2C™ Specification
400
Note 1: Negative current is defined as current sourced by the pin.
© 2007 Microchip Technology Inc.
Preliminary
DS39774C-page 351
PIC18F85J11 FAMILY
TABLE 25-1: MEMORY PROGRAMMING REQUIREMENTS
Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C ≤ TA ≤ +85°C for industrial
DC CHARACTERISTICS
Param
Sym
No.
Characteristic
Min
Typ†
Max
Units
Conditions
Program Flash Memory
Cell Endurance
D130
D131
EP
100
1k
—
—
E/W -40°C to +85°C
VPR
VDD for Read
VMIN
3.6
V
VMIN = Minimum operating
voltage
D132B VPEW VDD for Self-Timed Write
VMIN
—
3.6
V
VMIN = Minimum operating
voltage
D133A TIW
Self-Timed Write Cycle Time
—
2.8
—
—
—
ms
D134 TRETD Characteristic Retention
20
Year Provided no other
specifications are violated
D135
IDDP
Supply Current during
Programming
—
—
3
7
1
mA
D1xxx TWE
Writes per Erase Cycle
—
Per one physical word
address
†
Data in “Typ” column is at 3.3V, 25°C unless otherwise stated. These parameters are for design guidance
only and are not tested.
DS39774C-page 352
Preliminary
© 2007 Microchip Technology Inc.
PIC18F85J11 FAMILY
TABLE 25-2: COMPARATOR SPECIFICATIONS
Operating Conditions: 3.0V ≤ VDD ≤ 3.6V, -40°C ≤ TA ≤ +85°C (unless otherwise stated)
Param
No.
Sym
Characteristics
Input Offset Voltage
Min
Typ
Max
Units
Comments
D300
VIOFF
—
0
5.0
—
10
AVDD – 1.5
—
mV
V
D301
D302
300
VICM
Input Common Mode Voltage*
Common Mode Rejection Ratio*
Response Time*(1)
CMRR
TRESP
55
—
—
—
dB
ns
µs
150
—
400
301
TMC2OV Comparator Mode Change to
Output Valid*
10
*
These parameters are characterized but not tested.
Note 1: Response time measured with one comparator input at (AVDD – 1.5)/2, while the other input transitions
from VSS to VDD.
TABLE 25-3: VOLTAGE REFERENCE SPECIFICATIONS
Operating Conditions: 3.0V ≤ VDD ≤ 3.6V, -40°C ≤ TA ≤ +85°C (unless otherwise stated)
Param
No.
Sym
Characteristics
Min
Typ
Max
Units
Comments
D310
VRES
Resolution
VDD/24
—
—
—
2k
—
VDD/32
1/2
LSb
LSb
Ω
D311
D312
310
VRAA
VRUR
TSET
Absolute Accuracy
Unit Resistor Value (R)
Settling Time(1)
—
—
—
10
µs
Note 1: Settling time measured while CVRR = 1and CVR3:CVR0 bits transition from ‘0000’ to ‘1111’.
TABLE 25-4: INTERNAL VOLTAGE REGULATOR SPECIFICATIONS
Operating Conditions: -40°C ≤ TA ≤ +85°C (unless otherwise stated)
Param
No.
Sym
Characteristics
Min
Typ
Max
Units
Comments
VRGOUT Regulator Output Voltage*
External Filter Capacitor Value*
—
2.5
10
—
—
V
CEFC
4.7
µF
Capacitor must be low-ESR
*
These parameters are characterized but not tested. Parameter numbers not yet assigned for these
specifications.
© 2007 Microchip Technology Inc.
Preliminary
DS39774C-page 353
PIC18F85J11 FAMILY
25.4 AC (Timing) Characteristics
25.4.1
TIMING PARAMETER SYMBOLOGY
The timing parameter symbols have been created
following one of the following formats:
1. TppS2ppS
2. TppS
T
3. TCC:ST
4. Ts
(I2C specifications only)
(I2C specifications only)
F
Frequency
T
Time
Lowercase letters (pp) and their meanings:
pp
cc
ck
cs
di
CCP1
CLKO
CS
osc
rd
OSC1
RD
rw
sc
ss
t0
RD or WR
SCK
SDI
do
dt
SDO
SS
Data in
I/O port
MCLR
T0CKI
T13CKI
WR
io
t1
mc
wr
Uppercase letters and their meanings:
S
F
Fall
P
R
V
Z
Period
H
High
Rise
I
L
Invalid (High-impedance)
Low
Valid
High-impedance
I2C only
AA
output access
Bus free
High
Low
High
Low
BUF
TCC:ST (I2C specifications only)
CC
HD
Hold
SU
Setup
ST
DAT
STA
DATA input hold
Start condition
STO
Stop condition
DS39774C-page 354
Preliminary
© 2007 Microchip Technology Inc.
PIC18F85J11 FAMILY
25.4.2
TIMING CONDITIONS
The temperature and voltages specified in Table 25-5
apply to all timing specifications unless otherwise
noted. Figure 25-3 specifies the load conditions for the
timing specifications.
TABLE 25-5: TEMPERATURE AND VOLTAGE SPECIFICATIONS – AC
Standard Operating Conditions (unless otherwise stated)
AC CHARACTERISTICS
Operating temperature
Operating voltage VDD range as described in Section 25.1 and Section 25.3.
-40°C ≤ TA ≤ +85°C for industrial
FIGURE 25-3:
LOAD CONDITIONS FOR DEVICE TIMING SPECIFICATIONS
Load Condition 1
VDD/2
Load Condition 2
RL
CL
CL
Pin
Pin
VSS
VSS
RL = 464Ω
CL = 50 pF for all pins except RA6/OSC2/CLKO
and including D and E outputs as ports
CL = 15 pF for RA6/OSC2/CLKO
© 2007 Microchip Technology Inc.
Preliminary
DS39774C-page 355
PIC18F85J11 FAMILY
25.4.3
TIMING DIAGRAMS AND SPECIFICATIONS
FIGURE 25-4:
EXTERNAL CLOCK TIMING (ALL MODES EXCEPT PLL)
Q4
Q1
1
Q2
Q3
Q4
Q1
OSC1
CLKO
3
4
4
3
2
TABLE 25-6: EXTERNAL CLOCK TIMING REQUIREMENTS
Param.
Symbol
Characteristic
Min
Max
Units
Conditions
No.
1A
1
FOSC
External CLKI Frequency(1)
Oscillator Frequency(1)
External CLKI Period(1)
Oscillator Period(1)
DC
DC
25
40
40
—
MHz ECPLL Oscillator mode
MHz HSPLL Oscillator mode
TOSC
TCY
ns
ns
ns
ns
EC Oscillator mode
HS Oscillator mode
TCY = 4/FOSC, Industrial
EC Oscillator mode
25
250
—
2
3
Instruction Cycle Time(1)
100
10
TOSL,
TOSH
External Clock in (OSC1)
High or Low Time
—
4
TOSR,
TOSF
External Clock in (OSC1)
Rise or Fall Time
—
7.5
ns
EC Oscillator mode
Note 1: Instruction cycle period (TCY) equals four times the input oscillator time base period for all configurations
except PLL. All specified values are based on characterization data for that particular oscillator type under
standard operating conditions with the device executing code. Exceeding these specified limits may result
in an unstable oscillator operation and/or higher than expected current consumption. All devices are tested
to operate at “min.” values with an external clock applied to the OSC1/CLKI pin. When an external clock
input is used, the “max.” cycle time limit is “DC” (no clock) for all devices.
DS39774C-page 356
Preliminary
© 2007 Microchip Technology Inc.
PIC18F85J11 FAMILY
TABLE 25-7: PLL CLOCK TIMING SPECIFICATIONS (VDD = 2.15V TO 3.6V)
Param
No.
Sym
Characteristic
Min
Typ†
Max
Units Conditions
F10
F11
F12
F13
FOSC Oscillator Frequency Range
4
—
—
—
—
10
40
2
MHz HS mode only
FSYS On-Chip VCO System Frequency
16
—
-2
MHz HS mode only
trc
PLL Start-up Time (Lock Time)
ms
%
ΔCLK CLKO Stability (Jitter)
+2
†
Data in “Typ” column is at 3.3V, 25°C, unless otherwise stated. These parameters are for design guidance
only and are not tested.
TABLE 25-8: INTERNAL RC ACCURACY (INTOSC AND INTRC SOURCES)
PIC18F85J11 Family
Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C ≤ TA ≤ +85°C for industrial
(Industrial)
Param
No.
Device
Min
Typ
Max
Units
Conditions
INTOSC Accuracy @ Freq = 8 MHz, 4 MHz, 2 MHz, 1 MHz, 500 kHz, 250 kHz, 125 kHz, 31 kHz(1)
All devices
-2
-5
+/-1
—
2
5
%
%
%
+25°C
VDD = 2.7-3.3V
VDD = 2.0-3.3V
VDD = 2.0-3.3V
-10°C to +85°C
-40°C to +85°C
-10
+/-1
10
INTRC Accuracy @ Freq = 31 kHz(1)
All devices 26.562
—
35.938
kHz
-40°C to +85°C
VDD = 2.0-3.3V
Legend: TBD = To Be Determined
Note 1: The accuracy specification of the 31 kHz clock is determined by which source is providing it at a given
time. When INTSRC (OSCTUNE<7>) is ‘1’, use the INTOSC accuracy specification. When INTSRC is ‘0’,
use the INTRC accuracy specification.
© 2007 Microchip Technology Inc.
Preliminary
DS39774C-page 357
PIC18F85J11 FAMILY
FIGURE 25-5:
CLKO AND I/O TIMING
Q4
Q1
Q2
Q3
OSC1
11
10
CLKO
12
13
14
18
19
16
I/O pin
(Input)
15
17
I/O pin
(Output)
Old Value
New Value
20, 21
Refer to Figure 25-3 for load conditions.
Note:
TABLE 25-9: CLKO AND I/O TIMING REQUIREMENTS
Param
Symbol
Characteristic
Min
Typ
Max
Units Conditions
No.
10
TOSH2CKL OSC1 ↑ to CLKO ↓
TOSH2CKH OSC1 ↑ to CLKO ↑
—
75
75
15
15
—
—
—
50
—
200
200
30
ns (Note 1)
ns (Note 1)
ns (Note 1)
ns (Note 1)
11
12
13
14
15
16
17
18
—
TCKR
TCKF
CLKO Rise Time
CLKO Fall Time
—
—
30
TCKL2IOV CLKO ↓ to Port Out Valid
TIOV2CKH Port In Valid before CLKO ↑
TCKH2IOI Port In Hold after CLKO ↑
TOSH2IOV OSC1 ↑ (Q1 cycle) to Port Out Valid
—
0.5 TCY + 20 ns
0.25 TCY + 25
—
—
ns
ns
ns
ns
0
—
150
—
TOSH2IOI OSC1 ↑ (Q2 cycle) to Port Input Invalid
100
(I/O in hold time)
19
TIOV2OSH Port Input Valid to OSC1 ↑
0
—
—
ns
(I/O in setup time)
20
TIOR
TIOF
TINP
TRBP
Port Output Rise Time
—
—
—
—
—
—
6
5
ns
ns
ns
ns
21
Port Output Fall Time
22†
23†
INTx Pin High or Low Time
RB7:RB4 Change INTx High or Low Time
TCY
TCY
—
—
†
These parameters are asynchronous events not related to any internal clock edges.
Note 1: Measurements are taken in EC mode, where CLKO output is 4 x TOSC.
DS39774C-page 358
Preliminary
© 2007 Microchip Technology Inc.
PIC18F85J11 FAMILY
FIGURE 25-6:
RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND
POWER-UP TIMER TIMING
VDD
MCLR
30
Internal
POR
33
PWRT
Time-out
32
Oscillator
Time-out
Internal
Reset
Watchdog
Timer
Reset
31
34
34
I/O pins
Note:
Refer to Figure 25-3 for load conditions.
TABLE 25-10: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER
AND BROWN-OUT RESET REQUIREMENTS
Param
No.
Symbol
Characteristic
Min
Typ
Max
Units
Conditions
(Note 1)
30
TMCL
TWDT
MCLR Pulse Width (low)
2 TCY
3.4
10 TCY
4.0
—
31
Watchdog Timer Time-out Period
(no postscaler)
4.6
ms
32
33
34
TOST
Oscillator Start-up Timer Period
1024 TOSC
45.8
—
65.5
2
1024 TOSC
85.2
TOSC = OSC1 period
TPWRT Power-up Timer Period
ms
µs
TIOZ
I/O High-Impedance from MCLR
—
—
Low or Watchdog Timer Reset
38
TCSD
CPU Start-up Time
—
—
10
—
—
µs
200
µs Voltage regulator
enabled and put to
Sleep
39
TIOBST Time for INTOSC to Stabilize
—
1
—
µs
Note 1: To ensure device Reset, MCLR must be low for at least 2 TCY or 400 µs, which ever is lower.
© 2007 Microchip Technology Inc.
Preliminary
DS39774C-page 359
PIC18F85J11 FAMILY
FIGURE 25-7:
TIMER0 AND TIMER1 EXTERNAL CLOCK TIMINGS
T0CKI
41
40
42
T1OSO/T13CKI
46
45
47
48
TMR0 or
TMR1
Note:
Refer to Figure 25-3 for load conditions.
TABLE 25-11: TIMER0 AND TIMER1 EXTERNAL CLOCK REQUIREMENTS
Param
Symbol
Characteristic
Min
Max Units
Conditions
No.
40
TT0H
T0CKI High Pulse Width
No prescaler
With prescaler
No prescaler
With prescaler
No prescaler
With prescaler
0.5 TCY + 20
10
—
—
—
—
—
—
ns
ns
ns
ns
ns
41
42
TT0L
TT0P
T0CKI Low Pulse Width
T0CKI Period
0.5 TCY + 20
10
TCY + 10
Greater of:
20 ns or
ns N = prescale
value
(TCY + 40)/N
(1, 2, 4,..., 256)
45
46
47
TT1H
TT1L
TT1P
T13CKI High Synchronous, no prescaler
0.5 TCY + 20
—
—
—
—
—
—
—
ns
ns
ns
ns
ns
ns
Time
Synchronous, with prescaler
10
Asynchronous
30
0.5 TCY + 5
10
T13CKI Low Synchronous, no prescaler
Time
Synchronous, with prescaler
Asynchronous
30
T13CKI Input Synchronous
Period
Greater of:
20 ns or
ns N = prescale
value
(TCY + 40)/N
(1, 2, 4, 8)
Asynchronous
60
DC
—
50
ns
kHz
—
FT1
T13CKI Oscillator Input Frequency Range
48
TCKE2TMRI Delay from External T13CKI Clock Edge to
Timer Increment
2 TOSC
7 TOSC
DS39774C-page 360
Preliminary
© 2007 Microchip Technology Inc.
PIC18F85J11 FAMILY
FIGURE 25-8:
CAPTURE/COMPARE/PWM TIMINGS (CCP1, CCP2 MODULES)
CCPx
(Capture Mode)
51
50
52
54
CCPx
(Compare or PWM Mode)
53
Note:
Refer to Figure 25-3 for load conditions.
TABLE 25-12: CAPTURE/COMPARE/PWM REQUIREMENTS (CCP1, CCP2 MODULES)
Param
Symbol
Characteristic
Min
Max
Units
Conditions
No.
50
TCCL
CCPx Input Low No prescaler
0.5 TCY + 20
—
—
—
—
—
ns
ns
ns
ns
ns
Time
With prescaler
10
0.5 TCY + 20
10
51
52
TCCH
TCCP
CCPx Input
High Time
No prescaler
With prescaler
CCPx Input Period
3 TCY + 40
N
N = prescale
value (1, 4 or 16)
53
54
TCCR
TCCF
CCPx Output Fall Time
CCPx Output Fall Time
—
—
25
25
ns
ns
© 2007 Microchip Technology Inc.
Preliminary
DS39774C-page 361
PIC18F85J11 FAMILY
FIGURE 25-9:
EXAMPLE SPI MASTER MODE TIMING (CKE = 0)
SS
70
SCK
(CKP = 0)
71
72
78
79
79
78
SCK
(CKP = 1)
80
MSb
bit 6 - - - - - - 1
LSb
SDO
SDI
75, 76
MSb In
74
bit 6 - - - - 1
LSb In
73
Note: Refer to Figure 25-3 for load conditions.
TABLE 25-13: EXAMPLE SPI MODE REQUIREMENTS (MASTER MODE, CKE = 0)
Param
No.
Symbol
Characteristic
Min
Max Units Conditions
70
TSSL2SCH, SS ↓ to SCK ↓ or SCK ↑ Input
TSSL2SCL
TCY
—
ns
71
TSCH
SCK Input High Time
(Slave mode)
Continuous
Single byte
Continuous
Single byte
1.25 TCY + 30
—
—
—
—
—
ns
71A
72
40
1.25 TCY + 30
40
ns (Note 1)
TSCL
SCK Input Low Time
(Slave mode)
ns
72A
73
ns (Note 1)
TDIV2SCH, Setup Time of SDI Data Input to SCK Edge
TDIV2SCL
100
ns
73A
74
TB2B
Last Clock Edge of Byte 1 to the 1st Clock Edge 1.5 TCY + 40
of Byte 2
—
—
ns (Note 2)
TSCH2DIL, Hold Time of SDI Data Input to SCK Edge
TSCL2DIL
100
ns
75
76
78
79
80
TDOR
TDOF
TSCR
TSCF
SDO Data Output Rise Time
—
—
—
—
—
25
25
25
25
50
ns
ns
ns
ns
ns
SDO Data Output Fall Time
SCK Output Rise Time (Master mode)
SCK Output Fall Time (Master mode)
TSCH2DOV, SDO Data Output Valid after SCK Edge
TSCL2DOV
Note 1: Requires the use of Parameter #73A.
2: Only if Parameter #71A and #72A are used.
DS39774C-page 362
Preliminary
© 2007 Microchip Technology Inc.
PIC18F85J11 FAMILY
FIGURE 25-10:
EXAMPLE SPI MASTER MODE TIMING (CKE = 1)
SS
81
SCK
(CKP = 0)
71
72
79
78
73
SCK
(CKP = 1)
80
LSb
bit 6 - - - - - - 1
MSb
SDO
SDI
75, 76
MSb In
74
bit 6 - - - - 1
LSb In
Note: Refer to Figure 25-3 for load conditions.
TABLE 25-14: EXAMPLE SPI MODE REQUIREMENTS (MASTER MODE, CKE = 1)
Param.
No.
Symbol
TSCH
Characteristic
Min
Max Units Conditions
71
SCK Input High Time
Continuous
Single byte
Continuous
Single byte
1.25 TCY + 30
—
—
—
—
—
ns
(Slave mode)
71A
72
40
1.25 TCY + 30
40
ns (Note 1)
TSCL
SCK Input Low Time
(Slave mode)
ns
72A
73
ns (Note 1)
TDIV2SCH, Setup Time of SDI Data Input to SCK Edge
TDIV2SCL
100
ns
73A
74
TB2B
Last Clock Edge of Byte 1 to the 1st Clock Edge 1.5 TCY + 40
of Byte 2
—
—
ns (Note 2)
TSCH2DIL, Hold Time of SDI Data Input to SCK Edge
TSCL2DIL
100
ns
75
76
78
79
80
TDOR
TDOF
TSCR
TSCF
SDO Data Output Rise Time
—
—
—
—
—
25
25
25
25
50
ns
ns
ns
ns
ns
SDO Data Output Fall Time
SCK Output Rise Time (Master mode)
SCK Output Fall Time (Master mode)
TSCH2DOV, SDO Data Output Valid after SCK Edge
TSCL2DOV
81
TDOV2SCH, SDO Data Output Setup to SCK Edge
TDOV2SCL
TCY
—
ns
Note 1: Requires the use of Parameter #73A.
2: Only if Parameter #71A and #72A are used.
© 2007 Microchip Technology Inc.
Preliminary
DS39774C-page 363
PIC18F85J11 FAMILY
FIGURE 25-11:
EXAMPLE SPI SLAVE MODE TIMING (CKE = 0)
SS
70
SCK
(CKP = 0)
83
71
72
78
79
79
78
SCK
(CKP = 1)
80
SDO
SDI
MSb
LSb
bit 6 - - - - - - 1
75, 76
77
MSb In
74
bit 6 - - - - 1
LSb In
73
Note:
Refer to Figure 25-3 for load conditions.
TABLE 25-15: EXAMPLE SPI MODE REQUIREMENTS (SLAVE MODE TIMING, CKE = 0)
Param
No.
Symbol
Characteristic
Min
Max Units Conditions
70
TSSL2SCH, SS ↓ to SCK ↓ or SCK ↑ Input
TSSL2SCL
3 TCY
—
ns
70A
71
TSSL2WB SS to Write to SSPBUF
3 TCY
1.25 TCY + 30
40
—
—
—
—
—
—
ns
TSCH
SCK Input High Time
(Slave mode)
Continuous
Single Byte
Continuous
Single Byte
ns
71A
72
ns (Note 1)
TSCL
SCK Input Low Time
(Slave mode)
1.25 TCY + 30
40
ns
72A
73
ns (Note 1)
TDIV2SCH, Setup Time of SDI Data Input to SCK Edge
TDIV2SCL
100
ns
73A
74
TB2B
Last Clock Edge of Byte 1 to the First Clock Edge of Byte 2 1.5 TCY + 40
—
—
ns (Note 2)
TSCH2DIL, Hold Time of SDI Data Input to SCK Edge
TSCL2DIL
100
ns
75
76
77
78
79
80
TDOR
TDOF
SDO Data Output Rise Time
SDO Data Output Fall Time
—
—
10
—
—
—
25
25
50
25
25
50
ns
ns
ns
ns
ns
ns
TSSH2DOZ SS ↑ to SDO Output High-Impedance
TSCR
TSCF
SCK Output Rise Time (Master mode)
SCK Output Fall Time (Master mode)
TSCH2DOV, SDO Data Output Valid after SCK Edge
TSCL2DOV
83
TSCH2SSH, SS ↑ after SCK Edge
TSCL2SSH
1.5 TCY + 40
—
ns
Note 1: Requires the use of Parameter #73A.
2: Only if Parameter #71A and #72A are used.
DS39774C-page 364
Preliminary
© 2007 Microchip Technology Inc.
PIC18F85J11 FAMILY
FIGURE 25-12:
EXAMPLE SPI SLAVE MODE TIMING (CKE = 1)
82
SS
70
SCK
83
(CKP = 0)
71
72
SCK
(CKP = 1)
80
SDO
SDI
LSb
MSb
bit 6 - - - - - - 1
bit 6 - - - - 1
77
75, 76
MSb In
74
LSb In
Note: Refer to Figure 25-3 for load conditions.
TABLE 25-16: EXAMPLE SPI SLAVE MODE REQUIREMENTS (CKE = 1)
Param
No.
Symbol
Characteristic
Min
Max Units Conditions
70
TSSL2SCH, SS ↓ to SCK ↓ or SCK ↑ Input
TSSL2SCL
3 TCY
—
ns
70A
71
TSSL2WB SS to Write to SSPBUF
3 TCY
—
—
—
—
—
—
—
ns
TSCH
TSCL
TB2B
SCK Input High Time
(Slave mode)
Continuous
Single Byte
Continuous
Single Byte
1.25 TCY + 30
ns
71A
72
40
1.25 TCY + 30
40
ns (Note 1)
ns
SCK Input Low Time
(Slave mode)
72A
73A
74
ns (Note 1)
ns (Note 2)
ns
Last Clock Edge of Byte 1 to the First Clock Edge of Byte 2 1.5 TCY + 40
TSCH2DIL, Hold Time of SDI Data Input to SCK Edge
TSCL2DIL
100
75
76
77
78
79
80
TDOR
TDOF
SDO Data Output Rise Time
SDO Data Output Fall Time
—
—
10
—
—
—
25
25
50
25
25
50
ns
ns
ns
ns
ns
ns
TSSH2DOZ SS ↑ to SDO Output High-Impedance
TSCR
TSCF
SCK Output Rise Time (Master mode)
SCK Output Fall Time (Master mode)
TSCH2DOV, SDO Data Output Valid after SCK Edge
TSCL2DOV
82
83
TSSL2DOV SDO Data Output Valid after SS ↓ Edge
—
50
—
ns
ns
TSCH2SSH, SS ↑ after SCK Edge
TSCL2SSH
1.5 TCY + 40
Note 1: Requires the use of Parameter #73A.
2: Only if Parameter #71A and #72A are used.
© 2007 Microchip Technology Inc.
Preliminary
DS39774C-page 365
PIC18F85J11 FAMILY
FIGURE 25-13:
I2C™ BUS START/STOP BITS TIMING
SCL
91
93
90
92
SDA
Start
Condition
Stop
Condition
Note: Refer to Figure 25-3 for load conditions.
TABLE 25-17: I2C™ BUS START/STOP BITS REQUIREMENTS (SLAVE MODE)
Param.
Symbol
Characteristic
Min
Max
Units
Conditions
No.
90
TSU:STA Start Condition
Setup Time
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
4700
600
—
—
—
—
—
—
—
—
ns
Only relevant for Repeated
Start condition
91
92
93
THD:STA Start Condition
Hold Time
4000
600
ns
ns
ns
After this period, the first
clock pulse is generated
TSU:STO Stop Condition
Setup Time
4700
600
THD:STO Stop Condition
Hold Time
4000
600
DS39774C-page 366
Preliminary
© 2007 Microchip Technology Inc.
PIC18F85J11 FAMILY
FIGURE 25-14:
I2C™ BUS DATA TIMING
103
102
100
101
SCL
90
106
107
92
91
SDA
In
110
109
109
SDA
Out
Note: Refer to Figure 25-3 for load conditions.
TABLE 25-18: I2C™ BUS DATA REQUIREMENTS (SLAVE MODE)
Param.
No.
Symbol
Characteristic
100 kHz mode
Min
Max
Units
Conditions
100
THIGH
Clock High Time
Clock Low Time
4.0
0.6
—
—
μs
μs
400 kHz mode
MSSP module
100 kHz mode
400 kHz mode
MSSP module
1.5 TCY
4.7
—
101
TLOW
—
μs
μs
1.3
—
1.5 TCY
—
—
102
103
TR
SDA and SCL Rise Time 100 kHz mode
400 kHz mode
1000
300
ns
ns
20 + 0.1 CB
CB is specified to be from
10 to 400 pF
TF
SDA and SCL Fall Time
100 kHz mode
400 kHz mode
—
300
300
ns
ns
20 + 0.1 CB
CB is specified to be from
10 to 400 pF
90
TSU:STA
Start Condition Setup Time 100 kHz mode
400 kHz mode
4.7
0.6
4.0
0.6
0
—
—
μs
μs
μs
μs
ns
μs
ns
ns
μs
μs
ns
ns
μs
μs
pF
Only relevant for Repeated
Start condition
91
THD:STA Start Condition Hold Time 100 kHz mode
400 kHz mode
—
After this period, the first clock
pulse is generated
—
106
107
92
THD:DAT Data Input Hold Time
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
—
0
0.9
—
TSU:DAT Data Input Setup Time
250
100
4.7
0.6
—
(Note 2)
—
TSU:STO Stop Condition Setup Time 100 kHz mode
400 kHz mode
—
—
109
110
D102
TAA
TBUF
CB
Output Valid from Clock
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
3500
—
(Note 1)
—
Bus Free Time
4.7
1.3
—
—
Time the bus must be free before
a new transmission can start
—
Bus Capacitive Loading
400
Note 1: As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region (min. 300 ns) of
the falling edge of SCL to avoid unintended generation of Start or Stop conditions.
2
2
2: A Fast mode I C™ bus device can be used in a Standard mode I C bus system, but the requirement, TSU:DAT ≥ 250 ns,
must then be met. This will automatically be the case if the device does not stretch the LOW period of the SCL signal. If
such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line,
2
TR max. + TSU:DAT = 1000 + 250 = 1250 ns (according to the Standard mode I C bus specification), before the SCL line
is released.
© 2007 Microchip Technology Inc.
Preliminary
DS39774C-page 367
PIC18F85J11 FAMILY
FIGURE 25-15:
MSSP I2C™ BUS START/STOP BITS TIMING WAVEFORMS
SCL
93
91
90
92
SDA
Start
Condition
Stop
Condition
Note: Refer to Figure 25-3 for load conditions.
TABLE 25-19: MSSP I2C™ BUS START/STOP BITS REQUIREMENTS
Param.
Symbol
Characteristic
Min
Max Units
Conditions
No.
90
TSU:STA Start Condition
Setup Time
100 kHz mode
400 kHz mode
1 MHz mode(1) 2(TOSC)(BRG + 1)
2(TOSC)(BRG + 1)
2(TOSC)(BRG + 1)
—
—
—
—
—
—
—
—
—
—
—
—
ns Only relevant for
Repeated Start
condition
91
92
93
THD:STA Start Condition
Hold Time
100 kHz mode
400 kHz mode
1 MHz mode(1) 2(TOSC)(BRG + 1)
2(TOSC)(BRG + 1)
ns After this period, the
first clock pulse is
generated
2(TOSC)(BRG + 1)
TSU:STO Stop Condition
Setup Time
100 kHz mode
400 kHz mode
1 MHz mode(1) 2(TOSC)(BRG + 1)
2(TOSC)(BRG + 1)
ns
2(TOSC)(BRG + 1)
THD:STO Stop Condition
Hold Time
100 kHz mode
400 kHz mode
2(TOSC)(BRG + 1)
ns
2(TOSC)(BRG + 1)
1 MHz mode(1) 2(TOSC)(BRG + 1)
Note 1: Maximum pin capacitance = 10 pF for all I2C™ pins.
FIGURE 25-16:
MSSP I2C™ BUS DATA TIMING
102
103
100
101
SCL
90
106
92
107
91
SDA
In
110
109
109
SDA
Out
Note: Refer to Figure 25-3 for load conditions.
DS39774C-page 368
Preliminary
© 2007 Microchip Technology Inc.
PIC18F85J11 FAMILY
TABLE 25-20: MSSP I2C™ BUS DATA REQUIREMENTS
Param.
No.
Symbol
Characteristic
Min
Max Units
Conditions
100
101
102
103
90
THIGH
Clock High
Time
100 kHz mode 2(TOSC)(BRG + 1)
400 kHz mode 2(TOSC)(BRG + 1)
1 MHz mode(1) 2(TOSC)(BRG + 1)
—
—
ms
ms
ms
ms
ms
ms
ns
—
TLOW
TR
Clock Low Time 100 kHz mode 2(TOSC)(BRG + 1)
400 kHz mode 2(TOSC)(BRG + 1)
—
—
1 MHz mode(1) 2(TOSC)(BRG + 1)
—
SDA and SCL 100 kHz mode
Rise Time
—
1000
300
300
300
300
100
—
CB is specified to be from
10 to 400 pF
400 kHz mode
20 + 0.1 CB
ns
1 MHz mode(1)
—
ns
TF
SDA and SCL 100 kHz mode
Fall Time
—
20 + 0.1 CB
—
ns
CB is specified to be from
10 to 400 pF
400 kHz mode
1 MHz mode(1)
ns
ns
TSU:STA Start Condition 100 kHz mode 2(TOSC)(BRG + 1)
ms Only relevant for Repeated
Setup Time
Start condition
400 kHz mode 2(TOSC)(BRG + 1)
—
ms
1 MHz mode(1) 2(TOSC)(BRG + 1)
—
ms
91
THD:STA Start Condition 100 kHz mode 2(TOSC)(BRG + 1)
—
ms After this period, the first
Hold Time
clock pulse is generated
400 kHz mode 2(TOSC)(BRG + 1)
—
ms
1 MHz mode(1) 2(TOSC)(BRG + 1)
—
ms
ns
106
107
92
THD:DAT Data Input
Hold Time
100 kHz mode
400 kHz mode
1 MHz mode(1)
100 kHz mode
400 kHz mode
1 MHz mode(1)
0
—
0
0.9
—
ms
ns
TBD
250
100
TBD
TSU:DAT Data Input
Setup Time
—
ns
ns
ns
ms
ms
ms
ns
ns
ns
(Note 2)
—
—
TSU:STO Stop Condition 100 kHz mode 2(TOSC)(BRG + 1)
—
Setup Time
400 kHz mode 2(TOSC)(BRG + 1)
1 MHz mode(1) 2(TOSC)(BRG + 1)
—
—
109
110
D102
TAA
TBUF
CB
Output Valid
from Clock
100 kHz mode
400 kHz mode
1 MHz mode(1)
—
—
3500
1000
—
—
Bus Free Time 100 kHz mode
4.7
1.3
TBD
—
—
ms Time the bus must be free
before a new transmission
400 kHz mode
1 MHz mode(1)
—
ms
can start
ms
—
Bus Capacitive Loading
400
pF
Legend: TBD = To Be Determined
Note 1: Maximum pin capacitance = 10 pF for all I2C™ pins.
2: A Fast mode I2C bus device can be used in a Standard mode I2C bus system, but parameter #107 ≥ 250 ns
must then be met. This will automatically be the case if the device does not stretch the LOW period of the
SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next data bit
to the SDA line, parameter #102 + parameter #107 = 1000 + 250 = 1250 ns (for 100 kHz mode), before the
SCL line is released.
© 2007 Microchip Technology Inc.
Preliminary
DS39774C-page 369
PIC18F85J11 FAMILY
FIGURE 25-17:
EUSART/AUSART SYNCHRONOUSTRANSMISSION (MASTER/SLAVE)TIMING
TXx/CKx
pin
121
121
RXx/DTx
pin
120
Note: Refer to Figure 25-3 for load conditions.
122
TABLE 25-21: EUSART/AUSART SYNCHRONOUS TRANSMISSION REQUIREMENTS
Param
Symbol
Characteristic
Min
Max
Units Conditions
No.
120
TCKH2DTV SYNC XMIT (MASTER and SLAVE)
Clock High to Data Out Valid
—
—
—
40
20
20
ns
ns
ns
121
122
TCKRF
TDTRF
Clock Out Rise Time and Fall Time (Master mode)
Data Out Rise Time and Fall Time
FIGURE 25-18:
EUSART/AUSART SYNCHRONOUS RECEIVE (MASTER/SLAVE) TIMING
TXx/CKx
pin
125
RXx/DTx
pin
126
Note: Refer to Figure 25-3 for load conditions.
TABLE 25-22: EUSART/AUSART SYNCHRONOUS RECEIVE REQUIREMENTS
Param.
Symbol
Characteristic
Min
Max
Units
Conditions
No.
125
TDTV2CKL SYNC RCV (MASTER and SLAVE)
Data Hold before CKx ↓ (DTx hold time)
10
15
—
—
ns
ns
126
TCKL2DTL Data Hold after CKx ↓ (DTx hold time)
DS39774C-page 370
Preliminary
© 2007 Microchip Technology Inc.
PIC18F85J11 FAMILY
TABLE 25-23: A/D CONVERTER CHARACTERISTICS: PIC18F85J11 FAMILY (INDUSTRIAL)
Param
Symbol
Characteristic
Min
Typ
Max
Units
Conditions
No.
A01
NR
Resolution
—
—
—
—
—
—
10
bits
A03
A04
A06
A07
A10
A20
EIL
Integral Linearity Error
Differential Linearity Error
Offset Error
—
< 1
< 1
< 3
< 3
LSb ΔVREF ≥ 3.0V
LSb ΔVREF ≥ 3.0V
LSb ΔVREF ≥ 3.0V
LSb ΔVREF ≥ 3.0V
EDL
EOFF
EGN
—
—
—
Gain Error
—
Monotonicity
Guaranteed(1)
—
VSS ≤ VAIN ≤ VREF
ΔVREF Reference Voltage Range
2.0
3
—
—
—
—
V
V
VDD < 3.0V
VDD ≥ 3.0V
(VREFH – VREFL)
A21
A22
A25
A30
VREFH Reference Voltage High
VSS
—
VREFH
VDD – 3.0V
VREFH
V
V
VREFL
VAIN
Reference Voltage Low
Analog Input Voltage
VSS – 0.3V
VREFL
—
—
—
—
V
ZAIN
Recommended Impedance of
Analog Voltage Source
2.5
kΩ
A50
IREF
VREF Input Current(2)
—
—
—
—
5
150
µA During VAIN acquisition
µA During A/D conversion
cycle
Note 1: The A/D conversion result never decreases with an increase in the input voltage and has no missing codes.
2: VREFH current is from RA3/AN3/VREF+ pin or VDD, whichever is selected as the VREFH source.
VREFL current is from RA2/AN2/VREF- pin or VSS, whichever is selected as the VREFL source.
© 2007 Microchip Technology Inc.
Preliminary
DS39774C-page 371
PIC18F85J11 FAMILY
FIGURE 25-19:
A/D CONVERSION TIMING
BSF ADCON0, GO
(Note 2)
131
130
Q4
132
A/D CLK
. . .
. . .
9
8
7
2
1
0
A/D DATA
ADRES
OLD_DATA
NEW_DATA
TCY (Note 1)
ADIF
GO
DONE
SAMPLING STOPPED
SAMPLE
Note 1: If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the SLEEPinstruction
to be executed.
2: This is a minimal RC delay (typically 100 ns), which also disconnects the holding capacitor from the analog input.
TABLE 25-24: A/D CONVERSION REQUIREMENTS
Param
Symbol
Characteristic
Min
Max
Units
Conditions
No.
µs
130
TAD
A/D Clock Period
0.7
TBD
11
25.0(1)
TOSC based, VREF ≥ 3.0V
1
µs A/D RC mode
131
132
TCNV
TACQ
Conversion Time
12
TAD
(not including acquisition time)(2)
Acquisition Time(3)
1.4
—
—
µs -40°C to +85°C
135
TSWC
TDIS
Switching Time from Convert → Sample
—
(Note 4)
TBD
Discharge Time
0.2
—
µs
Legend: TBD = To Be Determined
Note 1: The time of the A/D clock period is dependent on the device frequency and the TAD clock divider.
2: ADRES registers may be read on the following TCY cycle.
3: The time for the holding capacitor to acquire the “New” input voltage when the voltage changes full scale
after the conversion (VDD to VSS or VSS to VDD). The source impedance (RS) on the input channels is 50Ω.
4: On the following cycle of the device clock.
DS39774C-page 372
Preliminary
© 2007 Microchip Technology Inc.
PIC18F85J11 FAMILY
26.0 DC AND AC
CHARACTERISTICS GRAPHS
AND TABLES
Graphs and tables are not available at this time.
© 2007 Microchip Technology Inc.
Preliminary
DS39774C-page 373
PIC18F85J11 FAMILY
NOTES:
DS39774C-page 374
Preliminary
© 2007 Microchip Technology Inc.
PIC18F85J11 FAMILY
27.0 PACKAGING INFORMATION
27.1 Package Marking Information
64-Lead TQFP
Example
XXXXXXXXXX
XXXXXXXXXX
XXXXXXXXXX
YYWWNNN
18F65J11
-I/PT
0710017
e
3
80-Lead TQFP
Example
XXXXXXXXXXXX
XXXXXXXXXXXX
YYWWNNN
PIC18F85J11
-I/PT
0710017
e
3
Legend: XX...X Customer-specific information
Y
YY
Year code (last digit of calendar year)
Year code (last 2 digits of calendar year)
Week code (week of January 1 is week ‘01’)
Alphanumeric traceability code
WW
NNN
e
3
Pb-free JEDEC designator for Matte Tin (Sn)
*
This package is Pb-free. The Pb-free JEDEC designator (
can be found on the outer packaging for this package.
)
e3
Note: In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
© 2007 Microchip Technology Inc.
Preliminary
DS39774C-page 375
PIC18F85J11 FAMILY
27.2 Package Details
The following sections give the technical details of the packages.
64-Lead Plastic Thin Quad Flatpack (PT) – 10x10x1 mm Body, 2.00 mm Footprint [TQFP]
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
D
D1
E
e
E1
N
b
NOTE 1
1 2 3
NOTE 2
α
A
c
φ
A2
A1
β
L
L1
Units
MILLIMETERS
Dimension Limits
MIN
NOM
64
MAX
Number of Leads
N
e
Lead Pitch
0.50 BSC
–
Overall Height
A
–
1.20
1.05
0.15
0.75
Molded Package Thickness
Standoff
A2
A1
L
0.95
0.05
0.45
1.00
–
Foot Length
0.60
Footprint
L1
φ
1.00 REF
3.5°
Foot Angle
0°
7°
Overall Width
E
12.00 BSC
12.00 BSC
10.00 BSC
10.00 BSC
–
Overall Length
Molded Package Width
Molded Package Length
Lead Thickness
Lead Width
D
E1
D1
c
0.09
0.17
11°
0.20
0.27
13°
b
0.22
Mold Draft Angle Top
Mold Draft Angle Bottom
α
β
12°
11°
12°
13°
Notes:
1. Pin 1 visual index feature may vary, but must be located within the hatched area.
2. Chamfers at corners are optional; size may vary.
3. Dimensions D1 and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.25 mm per side.
4. Dimensioning and tolerancing per ASME Y14.5M.
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
REF: Reference Dimension, usually without tolerance, for information purposes only.
Microchip Technology Drawing C04-085B
DS39774C-page 376
Preliminary
© 2007 Microchip Technology Inc.
PIC18F85J11 FAMILY
80-Lead Plastic Thin Quad Flatpack (PT) – 12x12x1 mm Body, 2.00 mm Footprint [TQFP]
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
D
D1
E
e
E1
N
b
NOTE 1
123
α
NOTE 2
A
c
φ
A2
β
A1
L1
L
Units
MILLIMETERS
Dimension Limits
MIN
NOM
80
MAX
Number of Leads
Lead Pitch
N
e
0.50 BSC
–
Overall Height
A
–
1.20
1.05
0.15
0.75
Molded Package Thickness
Standoff
A2
A1
L
0.95
0.05
0.45
1.00
–
Foot Length
0.60
Footprint
L1
φ
1.00 REF
3.5°
Foot Angle
0°
7°
Overall Width
E
14.00 BSC
14.00 BSC
12.00 BSC
12.00 BSC
–
Overall Length
D
Molded Package Width
Molded Package Length
Lead Thickness
Lead Width
E1
D1
c
0.09
0.17
11°
0.20
0.27
13°
b
0.22
Mold Draft Angle Top
Mold Draft Angle Bottom
α
β
12°
11°
12°
13°
Notes:
1. Pin 1 visual index feature may vary, but must be located within the hatched area.
2. Chamfers at corners are optional; size may vary.
3. Dimensions D1 and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.25 mm per side.
4. Dimensioning and tolerancing per ASME Y14.5M.
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
REF: Reference Dimension, usually without tolerance, for information purposes only.
Microchip Technology Drawing C04-092B
© 2007 Microchip Technology Inc.
Preliminary
DS39774C-page 377
PIC18F85J11 FAMILY
NOTES:
DS39774C-page 378
Preliminary
© 2007 Microchip Technology Inc.
PIC18F85J11 FAMILY
APPENDIX A: REVISION HISTORY
APPENDIX B: MIGRATION
BETWEEN HIGH-END
DEVICE FAMILIES
Revision A (October 2006)
Original data sheet for PIC18F85J11 family devices.
Devices in the PIC18F85J11 and PIC18F8722 families
are very similar in their functions and feature sets. How-
ever, there are some potentially important differences
which should be considered when migrating an applica-
tion across device families to achieve a new design goal.
These are summarized in Table B-1. The areas of
difference which could have a major impact on migration
are discussed in greater detail later in this section.
Revision B (March 2007)
Updated power-down and supply current electrical
characteristics and package detail drawings.
Revision C (April 2007)
Updated electrical characteristics.
TABLE B-1:
NOTABLE DIFFERENCES BETWEEN PIC18F85J11 AND PIC18F8722 FAMILIES
Characteristic
PIC18F85J11 Family
PIC18F8722 Family
Operating Frequency
Supply Voltage
40 MHz @ 2.15V
2.0V-3.6V, dual voltage requirement
Low
40 MHz @ 4.2V
2.0V-5.5V
Operating Current
Program Memory Endurance
I/O Sink/Source at 25 mA
Input Voltage Tolerance on I/O pins
I/O
Lower
1,000 write/erase cycles (typical)
PORTB and PORTC only
5.5V on digital only pins
68 (RF0 is not available)
100,000 write/erase cycles (typical)
All ports
VDD on all I/O pins
70
Pull-ups
PORTB, PORTD, PORTE
and PORTJ
PORTB
Oscillator Options
Limited options (EC, HS, PLL,
flexible INTRC)
More options (EC, HS, XT, LP, RC,
PLL, flexible INTRC)
Program Memory Retention
Self-Writes to Program Memory
Programming Time (normalized)
Programming Entry
20 years (minimum)
Available
40 years (minimum)
Available
156 µs/byte (10 ms/64-byte block)
Low voltage, key sequence
Single block, all or nothing
15.6 µs/byte (1 ms/64)
VPP and LVP
Code Protection
Multiple code protection blocks
Configuration Words
Stored in last 4 words of program
memory space
Stored in configuration space,
starting at 300000h
Power-up Timer
Data EEPROM
BOR
Always on
Use self-programming
Simple BOR with voltage regulator
Simple LVD with voltage regulator
12
Configurable
Available
Programmable BOR
Available
LVD
A/D Channels
16
A/D Calibration
Microprocessor mode (EMB)
External Memory Addressing
In-Circuit Emulation
Required
Not required
Available
Self-calibration feature
Address shifting available
Not available
Address shifting not available
Available
© 2007 Microchip Technology Inc.
DS39774C-page 379
PIC18F85J11 FAMILY
B.1
Power Requirement Differences
B.3
Oscillator Differences
The most significant difference between the
PIC18F85J11 and PIC18F8722 device families is the
power requirements. PIC18F85J11 devices are
designed on a smaller process; this results in lower
maximum voltage and higher leakage current.
PIC18F8722 and PIC18F85J11 family devices share a
similar range of oscillator options. The major difference
is that PIC18F85J11 family devices support a smaller
number of primary (external) oscillator options, namely
HS and EC Oscillator modes.
The operating voltage range for PIC18F85J11 devices is
2.0V to 3.6V. In addition, these devices have split power
requirements: one for the core logic and one for the I/O.
One of the VDD pins is separated for the core logic supply,
VDDCORE. This pin has specific voltage and capacitor
requirements as described in Section 25.0 “Electrical
Characteristics”.
While both device families have an internal PLL that
can be used with the primary oscillators, the PLL for the
PIC18F85J11 family is not enabled as a device
configuration option. Instead, it must be enabled in
software.
The clocking differences should be considered when
making a conversion between the PIC18F8722 and
PIC18F85J11 device families.
The current specifications for PIC18F85J11 devices
are yet to be determined.
B.4
Peripherals
B.2
Pin Differences
Peripherals must also be considered when making a
conversion between the PIC18F85J11 and the
PIC18F8722:
There are several differences in the pinout between the
PIC18F85J11 and the PIC18F8722 families:
• Input voltage tolerance
• Output current capabilities
• Available I/O
• External Memory Bus: The External Memory
Bus (EMB) on the PIC18F85J11 does not support
Microcontroller mode; however, it does support
external address offset.
Pins on the PIC18F85J11 that have digital only input
capability will tolerate voltages up to 5.5V and are thus
tolerant to voltages above VDD. Table 10-1 in
Section 10.1 “I/O Port Pin Capabilities” contains the
complete list.
• A/D Converter: There are only 12 channels on
PIC18F85J11 devices. The converters for these
devices also require a calibration step prior to
normal operation.
• Data EEPROM: PIC18F85J11 devices do not
In addition to input differences, there are output differ-
ences as well. PIC18F85J11 devices have three
classes of pin output current capability: high, medium
and low. Not all I/O pins can source or sink equal levels
of current. Only PORTB and PORTC support the
25 mA source/sink capability that is supported by all
output pins on the PIC18F8722. Table 10-2 in
Section 10.1 “I/O Port Pin Capabilities” contains the
complete list of output capabilities.
have this module.
• BOR: PIC18F85J11 devices do not have a
programmable BOR. Simple Brown-out Reset
capability is provided through the use of the
internal voltage regulator.
• LVD: PIC18F85J11 devices do not have a
separate programmable LVD module. Simple,
Low-Voltage Detection capability with a config-
urable interrupt is provided through the use of the
internal voltage regulator.
There are additional differences in how some pin func-
tions are implemented on PIC18F85J11 devices. First,
the MCLR pin is dedicated only to MCLR and cannot be
configured as an input (RG5). Finally, RF0 does not
exist on PIC18F85J11 devices.
All of these pin differences (including power pin
differences) should be accounted for when making a
conversion between PIC18F8722 and PIC18F85J11
devices.
DS39774C-page 380
© 2007 Microchip Technology Inc.
PIC18F85J11 FAMILY
INDEX
Baud Rate Generator (BRG) ................................... 240
Associated Registers ....................................... 240
Baud Rate Error, Calculating ........................... 240
Baud Rates, Asynchronous Modes ................. 241
High Baud Rate Select (BRGH Bit) ................. 240
Operation in Power-Managed Modes .............. 240
Sampling ......................................................... 240
Control Registers ..................................................... 237
Synchronous Master Mode ...................................... 246
Associated Registers, Receive ........................ 248
Associated Registers, Transmit ....................... 247
Reception ........................................................ 248
Transmission ................................................... 246
Synchronous Slave Mode ........................................ 249
Associated Registers, Receive ........................ 250
Associated Registers, Transmit ....................... 249
Reception ........................................................ 250
Transmission ................................................... 249
Auto-Wake-up on Sync Break Character ......................... 230
A
A/D ................................................................................... 251
A/D Converter Interrupt, Configuring ....................... 255
Acquisition Requirements ........................................ 256
ADCAL Bit ................................................................ 259
ADCON0 Register .................................................... 251
ADCON1 Register .................................................... 251
ADCON2 Register .................................................... 251
ADRESH Register ............................................ 251, 254
ADRESL Register .................................................... 251
Analog Port Pins, Configuring .................................. 257
Associated Registers ............................................... 259
Automatic Acquisition Time ...................................... 257
Configuring the Module ............................................ 255
Conversion Clock (TAD) ........................................... 257
Conversion Requirements ....................................... 372
Conversion Status (GO/DONE Bit) .......................... 254
Conversions ............................................................. 258
Converter Calibration ............................................... 259
Converter Characteristics ........................................ 371
Operation in Power-Managed Modes ...................... 259
Special Event Trigger (CCP2) .................................. 258
Use of the CCP2 Trigger .......................................... 258
Absolute Maximum Ratings ............................................. 339
AC (Timing) Characteristics ............................................. 354
Load Conditions for Device Timing
B
Baud Rate Generator ...................................................... 203
BC .................................................................................... 293
BCF ................................................................................. 294
BF .................................................................................... 207
BF Status Flag ................................................................. 207
Block Diagrams
Specifications ................................................... 355
Parameter Symbology ............................................. 354
Temperature and Voltage
16-Bit Byte Select Mode ............................................ 99
16-Bit Byte Write Mode .............................................. 97
16-Bit Word Write Mode ............................................ 98
8-Bit Multiplexed Mode ............................................ 101
A/D ........................................................................... 254
Analog Input Model .................................................. 255
AUSART Receive .................................................... 244
AUSART Transmit ................................................... 242
Baud Rate Generator .............................................. 203
Capture Mode Operation ......................................... 166
Comparator Analog Input Model .............................. 265
Comparator I/O Operating Modes ........................... 262
Comparator Output .................................................. 264
Comparator Voltage Reference ............................... 268
Comparator Voltage Reference
Output Buffer Example .................................... 269
Compare Mode Operation ....................................... 167
Connections for On-Chip Voltage Regulator ........... 279
Device Clock .............................................................. 29
EUSART Receive .................................................... 228
EUSART Transmit ................................................... 226
External Power-on Reset Circuit
Specifications ................................................... 355
Timing Conditions .................................................... 355
ACKSTAT ........................................................................ 207
ACKSTAT Status Flag ..................................................... 207
ADCAL Bit ........................................................................ 259
ADCON0 Register ............................................................ 251
GO/DONE Bit ........................................................... 254
ADCON1 Register ............................................................ 251
ADCON2 Register ............................................................ 251
ADDFSR .......................................................................... 328
ADDLW ............................................................................ 291
Addressable Universal Synchronous Asynchronous
Receiver Transmitter (AUSART). See AUSART.
ADDULNK ........................................................................ 328
ADDWF ............................................................................ 291
ADDWFC ......................................................................... 292
ADRESH Register ............................................................ 251
ADRESL Register .................................................... 251, 254
Analog-to-Digital Converter. See A/D.
ANDLW ............................................................................ 292
ANDWF ............................................................................ 293
Assembler
MPASM Assembler .................................................. 336
AUSART
(Slow VDD Power-up) ........................................ 47
Fail-Safe Clock Monitor ........................................... 282
Generic I/O Port Operation ...................................... 123
Interrupt Logic .......................................................... 108
2
MSSP (I C Master Mode) ........................................ 201
Asynchronous Mode ................................................ 242
Associated Registers, Receive ........................ 245
Associated Registers, Transmit ....................... 243
Receiver ........................................................... 244
Setting up 9-Bit Mode with
2
MSSP (I C Mode) .................................................... 182
MSSP (SPI Mode) ................................................... 173
On-Chip Reset Circuit ................................................ 45
PIC18F6XJ11 ............................................................ 10
PIC18F8XJ11 ............................................................ 11
PLL ............................................................................ 34
Address Detect ........................................ 244
Transmitter ....................................................... 242
© 2007 Microchip Technology Inc.
Preliminary
DS39774C-page 381
PIC18F85J11 FAMILY
PORTD and PORTE (Parallel Slave Port) ...............144
PWM Operation (Simplified) ....................................169
Reads From Flash Program Memory .........................87
Single Comparator ...................................................263
Table Read Operation ................................................83
Table Write Operation ................................................84
Table Writes to Flash Program Memory ....................89
Timer0 in 16-Bit Mode ..............................................148
Timer0 in 8-Bit Mode ................................................148
Timer1 (16-Bit Read/Write Mode) ............................152
Timer1 (8-Bit Mode) .................................................152
Timer2 ......................................................................158
Timer3 (16-Bit Read/Write Mode) ............................160
Timer3 (8-Bit Mode) .................................................160
Watchdog Timer .......................................................278
BN ....................................................................................294
BNC ..................................................................................295
BNN ..................................................................................295
BNOV ...............................................................................296
BNZ ..................................................................................296
BOR. See Brown-out Reset.
Code Examples
16 x 16 Signed Multiply Routine .............................. 106
16 x 16 Unsigned Multiply Routine .......................... 106
8 x 8 Signed Multiply Routine .................................. 105
8 x 8 Unsigned Multiply Routine .............................. 105
Changing Between Capture Prescalers ................... 166
Computed GOTO Using an Offset Value ................... 63
Erasing a Flash Program Memory Row ..................... 88
Fast Register Stack ................................................... 63
How to Clear RAM (Bank 1) Using
Indirect Addressing ............................................ 76
Implementing a Real-Time Clock Using
a Timer1 Interrupt Service ............................... 155
Initializing PORTA .................................................... 124
Initializing PORTB .................................................... 126
Initializing PORTC ................................................... 128
Initializing PORTD ................................................... 131
Initializing PORTE .................................................... 134
Initializing PORTF .................................................... 137
Initializing PORTG ................................................... 139
Initializing PORTH ................................................... 141
Initializing PORTJ .................................................... 142
Loading the SSPBUF (SSPSR) Register ................. 176
Reading a Flash Program Memory Word .................. 87
Saving STATUS, WREG and BSR
BOV ..................................................................................299
BRA ..................................................................................297
BRG. See Baud Rate Generator.
BRGH Bit
TXSTA1 Register .....................................................221
TXSTA2 Register .....................................................240
Brown-out Reset (BOR) .....................................................47
and On-Chip Voltage Regulator ...............................280
Detecting ....................................................................47
BSF ..................................................................................297
BTFSC .............................................................................298
BTFSS ..............................................................................298
BTG ..................................................................................299
BZ .....................................................................................300
Registers in RAM ............................................. 122
Writing to Flash Program Memory ............................. 90
Code Protection ............................................................... 271
COMF .............................................................................. 302
Comparator ...................................................................... 261
Analog Input Connection Considerations ................ 265
Associated Registers ............................................... 265
Configuration ........................................................... 262
Effects of a Reset .................................................... 264
Interrupts ................................................................. 264
Operation ................................................................. 263
Operation During Sleep ........................................... 264
Outputs .................................................................... 263
Reference ................................................................ 263
External Signal ................................................ 263
Internal Signal .................................................. 263
Response Time ........................................................ 263
Comparator Specifications ............................................... 353
Comparator Voltage Reference ....................................... 267
Accuracy and Error .................................................. 268
Associated Registers ............................................... 269
Configuring .............................................................. 267
Connection Considerations ...................................... 268
Effects of a Reset .................................................... 268
Operation During Sleep ........................................... 268
Compare (CCP Module) .................................................. 167
Associated Registers ............................................... 168
CCPR2 Register ...................................................... 167
CCPx Pin Configuration ........................................... 167
Software Interrupt .................................................... 167
Special Event Trigger ...................................... 161, 167
Timer1/Timer3 Mode Selection ................................ 167
Compare (CCP2 Module)
C
C Compilers
MPLAB C18 .............................................................336
MPLAB C30 .............................................................336
CALL ................................................................................300
CALLW .............................................................................329
Capture (CCP Module) .....................................................166
Associated Registers ...............................................168
CCPR2H:CCPR2L Registers ...................................166
CCPx Pin Configuration ...........................................166
Software Interrupt ....................................................166
Timer1/Timer3 Mode Selection ................................166
Capture/Compare/PWM (CCP) ........................................163
Capture Mode. See Capture.
CCPRxH Register ....................................................164
CCPRxL Register .....................................................164
CCPx Mode and Timer Resources ..........................164
Compare Mode. See Compare.
Configuration ............................................................164
Interaction of CCP1 and CCP2 for
Timer Resources ..............................................165
Interconnect Configurations .....................................164
Clock Sources ....................................................................31
Default System Clock on Reset .................................32
Selection Using OSCCON Register ...........................32
CLRF ................................................................................301
CLRWDT ..........................................................................301
Special Event Trigger .............................................. 258
Computed GOTO ............................................................... 63
Configuration Bits ............................................................ 271
Configuration Bits, Device IDs
Associated Registers ............................................... 272
DS39774C-page 382
Preliminary
© 2007 Microchip Technology Inc.
PIC18F85J11 FAMILY
Configuration Register Protection .................................... 284
Core Features
Equations
A/D Acquisition Time ............................................... 256
A/D Minimum Charging Time .................................. 256
Calculating the Minimum Required
Easy Migration ............................................................. 8
Extended Instruction Set .............................................. 7
External Memory Bus ................................................... 7
Memory Options ........................................................... 7
nanoWatt Technology .................................................. 7
Oscillator Options and Features .................................. 7
CPFSEQ .......................................................................... 302
CPFSGT .......................................................................... 303
CPFSLT ........................................................................... 303
Crystal Oscillator/Ceramic Resonator ................................ 33
Customer Change Notification Service ............................ 391
Customer Notification Service .......................................... 391
Customer Support ............................................................ 391
Acquisition Time .............................................. 256
Errata ................................................................................... 5
EUSART
Asynchronous Mode ................................................ 226
Associated Registers, Receive ........................ 229
Associated Registers, Transmit ....................... 227
Auto-Wake-up on Sync Break ......................... 230
Break Character Sequence ............................. 231
Receiver .......................................................... 228
Setting up 9-Bit Mode with
Address Detect ........................................ 228
Transmitter ...................................................... 226
Baud Rate Generator (BRG) ................................... 221
Associated Registers ....................................... 221
Auto-Baud Rate Detect .................................... 224
Baud Rate Error, Calculating ........................... 221
Baud Rates, Asynchronous Modes ................. 222
High Baud Rate Select (BRGH Bit) ................. 221
Operation in Power-Managed Modes .............. 221
Sampling ......................................................... 221
Control Registers ..................................................... 217
Synchronous Master Mode ...................................... 232
Associated Registers, Receive ........................ 234
Associated Registers, Transmit ....................... 233
Reception ........................................................ 234
Transmission ................................................... 232
Synchronous Slave Mode ........................................ 235
Associated Registers, Receive ........................ 236
Associated Registers, Transmit ....................... 235
Reception ........................................................ 236
Transmission ................................................... 235
Extended Instruction Set ................................................. 327
ADDFSR .................................................................. 328
ADDULNK ............................................................... 328
CALLW .................................................................... 329
Considerations when Enabling ................................ 332
MOVSF .................................................................... 329
MOVSS .................................................................... 330
PUSHL ..................................................................... 330
SUBFSR .................................................................. 331
SUBULNK ................................................................ 331
Syntax ...................................................................... 327
Use with MPLAB IDE Tools ..................................... 334
Extended Microcontroller Mode ......................................... 96
External Memory Bus ........................................................ 93
16-Bit Byte Select Mode ............................................ 99
16-Bit Byte Write Mode .............................................. 97
16-Bit Data Width Modes ........................................... 96
16-Bit Mode Timing ................................................. 100
16-Bit Word Write Mode ............................................ 98
21-Bit Addressing ...................................................... 95
8-Bit Data Width Mode ............................................ 101
8-Bit Mode Timing ................................................... 102
Address and Data Line Usage (table) ....................... 95
Address and Data Width ............................................ 95
Address Shifting ........................................................ 95
and Program Memory Modes .................................... 96
Control ....................................................................... 94
I/O Port Functions ...................................................... 93
D
Data Addressing Modes ..................................................... 76
Comparing Addressing Modes with the
Extended Instruction Set Enabled ..................... 80
Direct .......................................................................... 76
Indexed Literal Offset ................................................. 79
BSR ................................................................... 81
Instructions Affected .......................................... 79
Mapping Access Bank ....................................... 81
Indirect ....................................................................... 76
Inherent and Literal .................................................... 76
Data Memory ..................................................................... 66
Access Bank .............................................................. 69
Bank Select Register (BSR) ....................................... 66
Extended Instruction Set ............................................ 79
General Purpose Registers ........................................ 69
Memory Maps
PIC18FX3J11/X4J11 Devices ........................... 67
PIC18FX5J11 Devices ....................................... 68
Special Function Registers ................................ 70
Special Function Registers ........................................ 70
DAW ................................................................................. 304
DC and AC Characteristics
Graphs and Tables .................................................. 373
DC Characteristics
PIC18F85J11 Family ............................................... 350
Power-Down and Supply Current ............................ 342
Supply Voltage ......................................................... 341
DCFSNZ .......................................................................... 305
DECF ............................................................................... 304
DECFSZ ........................................................................... 305
Default System Clock ......................................................... 32
Details on Individual Family Members ................................. 8
Development Support ...................................................... 335
Device Overview .................................................................. 7
Features (64-Pin Devices) ........................................... 9
Features (80-Pin Devices) ........................................... 9
Direct Addressing ............................................................... 77
E
Effect on Standard PIC18 Instructions ............................. 332
Effects of Power-Managed Modes on
Various Clock Sources ............................................... 36
Electrical Characteristics .................................................. 339
Enhanced Universal Synchronous Asynchronous
Receiver Transmitter (EUSART). See EUSART.
ENVREG Pin .................................................................... 279
© 2007 Microchip Technology Inc.
Preliminary
DS39774C-page 383
PIC18F85J11 FAMILY
Operation in Power-Managed Modes ......................103
Wait States .................................................................96
Weak Pull-ups on Port Pins .......................................96
External Oscillator Modes ..................................................33
EC Modes ..................................................................34
HS Modes ..................................................................33
Clock Synchronization and the CKP Bit ................... 197
Effects of a Reset .................................................... 211
General Call Address Support ................................. 200
2
I C Clock Rate w/BRG ............................................. 203
Master Mode ............................................................ 201
Baud Rate Generator ...................................... 203
Operation ......................................................... 202
Reception ........................................................ 207
Repeated Start Condition Timing .................... 206
Start Condition Timing ..................................... 205
Transmission ................................................... 207
Multi-Master Communication, Bus Collision
F
Fail-Safe Clock Monitor ............................................ 271, 282
Exiting Fail-Safe Operation ......................................283
Interrupts in Power-Managed Modes .......................283
POR or Wake-up From Sleep ..................................283
WDT During Oscillator Failure .................................282
Fast Register Stack ............................................................63
Firmware Instructions .......................................................285
Flash Configuration Words ...............................................271
Mapping ...................................................................271
Flash Program Memory ......................................................83
Associated Registers .................................................91
Control Registers .......................................................84
EECON1 and EECON2 .....................................84
TABLAT (Table Latch) Register .........................86
TBLPTR (Table Pointer) Register ......................86
Erase Sequence ........................................................88
Erasing .......................................................................88
Operation During Code-Protect .................................91
Reading ......................................................................87
Table Pointer
and Arbitration ................................................. 211
Multi-Master Mode ................................................... 211
Operation ................................................................. 187
Read/Write Bit Information (R/W Bit) ............... 187, 189
Registers ................................................................. 182
Serial Clock (SCK/SCL) ........................................... 189
Slave Mode .............................................................. 187
Addressing ....................................................... 187
Addressing Masking ........................................ 188
Reception ........................................................ 189
Transmission ................................................... 189
Sleep Operation ....................................................... 211
Stop Condition Timing ............................................. 210
INCF ................................................................................ 306
INCFSZ ............................................................................ 307
In-Circuit Debugger .......................................................... 284
In-Circuit Serial Programming (ICSP) ...................... 271, 284
Indexed Literal Offset Addressing
and Standard PIC18 Instructions ............................. 332
Indexed Literal Offset Mode ............................................. 332
Indirect Addressing ............................................................ 77
INFSNZ ............................................................................ 307
Initialization Conditions for all Registers ...................... 51–55
Instruction Cycle ................................................................ 64
Clocking Scheme ....................................................... 64
Flow/Pipelining ........................................................... 64
Instruction Set .................................................................. 285
ADDLW .................................................................... 291
ADDWF .................................................................... 291
ADDWF (Indexed Literal Offset Mode) .................... 333
ADDWFC ................................................................. 292
ANDLW .................................................................... 292
ANDWF .................................................................... 293
BC ............................................................................ 293
BCF ......................................................................... 294
BN ............................................................................ 294
BNC ......................................................................... 295
BNN ......................................................................... 295
BNOV ...................................................................... 296
BNZ ......................................................................... 296
BOV ......................................................................... 299
BRA ......................................................................... 297
BSF .......................................................................... 297
BSF (Indexed Literal Offset Mode) .......................... 333
BTFSC ..................................................................... 298
BTFSS ..................................................................... 298
BTG ......................................................................... 299
BZ ............................................................................ 300
CALL ........................................................................ 300
CLRF ....................................................................... 301
CLRWDT ................................................................. 301
COMF ...................................................................... 302
CPFSEQ .................................................................. 302
Boundaries Based on Operation ........................86
Table Pointer Boundaries ..........................................86
Table Reads and Table Writes ..................................83
Write Sequence .........................................................89
Writing ........................................................................89
Unexpected Termination ....................................91
Write Verify ........................................................91
FSCM. See Fail-Safe Clock Monitor.
G
GOTO ...............................................................................306
H
Hardware Multiplier ..........................................................105
Introduction ..............................................................105
Operation .................................................................105
Performance Comparison ........................................105
I
I/O Ports ...........................................................................123
Input Voltage Considerations ...................................123
Open-Drain Outputs .................................................124
Output Pin Drive .......................................................123
Pin Capabilities ........................................................123
Pull-up Configuration ...............................................124
2
I C Mode (MSSP) ............................................................182
Acknowledge Sequence Timing ...............................210
Associated Registers ...............................................216
Baud Rate Generator ...............................................203
Bus Collision
During a Repeated Start Condition ..................214
During a Stop Condition ...................................215
Clock Arbitration .......................................................204
Clock Stretching .......................................................196
10-Bit Slave Receive Mode (SEN = 1) .............196
10-Bit Slave Transmit Mode .............................196
7-Bit Slave Receive Mode (SEN = 1) ...............196
7-Bit Slave Transmit Mode ...............................196
DS39774C-page 384
Preliminary
© 2007 Microchip Technology Inc.
PIC18F85J11 FAMILY
CPFSGT .................................................................. 303
CPFSLT ................................................................... 303
DAW ......................................................................... 304
DCFSNZ .................................................................. 305
DECF ....................................................................... 304
DECFSZ ................................................................... 305
General Format ........................................................ 287
GOTO ...................................................................... 306
INCF ......................................................................... 306
INCFSZ .................................................................... 307
INFSNZ .................................................................... 307
IORLW ..................................................................... 308
IORWF ..................................................................... 308
LFSR ........................................................................ 309
MOVF ....................................................................... 309
MOVFF .................................................................... 310
MOVLB .................................................................... 310
MOVLW ................................................................... 311
MOVWF ................................................................... 311
MULLW .................................................................... 312
MULWF .................................................................... 312
NEGF ....................................................................... 313
NOP ......................................................................... 313
Opcode Field Descriptions ....................................... 286
PIC18F85J11 Family (table) .................................... 288
POP ......................................................................... 314
PUSH ....................................................................... 314
RCALL ..................................................................... 315
RESET ..................................................................... 315
RETFIE .................................................................... 316
RETLW .................................................................... 316
RETURN .................................................................. 317
RLCF ........................................................................ 317
RLNCF ..................................................................... 318
RRCF ....................................................................... 318
RRNCF .................................................................... 319
SETF ........................................................................ 319
SETF (Indexed Literal Offset Mode) ........................ 333
SLEEP ..................................................................... 320
Standard Instructions ............................................... 285
SUBFWB .................................................................. 320
SUBLW .................................................................... 321
SUBWF .................................................................... 321
SUBWFB .................................................................. 322
SWAPF .................................................................... 322
TBLRD ..................................................................... 323
TBLWT ..................................................................... 324
TSTFSZ ................................................................... 325
XORLW .................................................................... 325
XORWF .................................................................... 326
Interrupt Sources ............................................................. 271
A/D Conversion Complete ....................................... 255
Capture Complete (CCP) ........................................ 166
Compare Complete (CCP) ...................................... 167
Interrupt-on-Change (RB7:RB4) .............................. 126
TMR1 Overflow ........................................................ 151
TMR2 to PR2 Match (PWM) .................................... 169
TMR3 Overflow ........................................................ 159
Interrupts ......................................................................... 107
During, Context Saving ............................................ 122
INTx Pin ................................................................... 122
PORTB, Interrupt-on-Change .................................. 122
TMR0 ....................................................................... 122
Interrupts, Flag Bits
Interrupt-on-Change (RB7:RB4)
Flag (RBIF Bit) ................................................. 126
INTOSC, INTRC. See Internal Oscillator Block.
IORLW ............................................................................. 308
IORWF ............................................................................. 308
IPR Registers ................................................................... 118
L
LFSR ............................................................................... 309
M
Master Clear (MCLR) ......................................................... 47
Master Synchronous Serial Port (MSSP). See MSSP.
Memory Organization ........................................................ 57
Data Memory ............................................................. 66
Program Memory ....................................................... 57
Memory Programming Requirements .............................. 352
Microchip Internet Web Site ............................................. 391
Microcontroller Mode ......................................................... 96
Migration Between High-End Device Families ................. 379
Oscillator Differences .............................................. 380
Peripherals .............................................................. 380
Pin Differences ........................................................ 380
Power Requirement Differences .............................. 380
MOVF .............................................................................. 309
MOVFF ............................................................................ 310
MOVLB ............................................................................ 310
MOVLW ........................................................................... 311
MOVSF ............................................................................ 329
MOVSS ............................................................................ 330
MOVWF ........................................................................... 311
MPLAB ASM30 Assembler, Linker, Librarian .................. 336
MPLAB ICD 2 In-Circuit Debugger .................................. 337
MPLAB ICE 2000 High-Performance
Universal In-Circuit Emulator ................................... 337
MPLAB Integrated Development
Environment Software ............................................. 335
MPLAB PM3 Device Programmer ................................... 337
MPLAB REAL ICE In-Circuit Emulator System ............... 337
MPLINK Object Linker/MPLIB Object Librarian ............... 336
MSSP
ACK Pulse ....................................................... 187, 189
Control Registers (general) ..................................... 173
Module Overview ..................................................... 173
SPI Master/Slave Connection .................................. 177
SSPBUF Register .................................................... 178
SSPSR Register ...................................................... 178
MULLW ............................................................................ 312
MULWF ............................................................................ 312
INTCON Register
RBIF Bit .................................................................... 126
INTCON Registers ........................................................... 109
2
Inter-Integrated Circuit. See I C Mode.
Internal Oscillator Block ..................................................... 35
Adjustment ................................................................. 35
INTOSC Frequency Drift ............................................ 35
INTOSC Output Frequency ........................................ 35
OSC1, OSC2 Pin Configuration ................................. 35
Internal RC Oscillator
Use with WDT .......................................................... 278
Internal Voltage Regulator Specifications ........................ 353
Internet Address ............................................................... 391
© 2007 Microchip Technology Inc.
Preliminary
DS39774C-page 385
PIC18F85J11 FAMILY
RD2/AD2/PSP2 ......................................................... 22
RD2/PSP2 ................................................................. 15
RD3/AD3/PSP3 ......................................................... 22
RD3/PSP3 ................................................................. 15
RD4/AD4/PSP4 ......................................................... 22
RD4/PSP4 ................................................................. 15
RD5/AD5/PSP5 ......................................................... 22
RD5/PSP5 ................................................................. 15
RD6/AD6/PSP6 ......................................................... 22
RD6/PSP6 ................................................................. 15
RD7/AD7/PSP7 ......................................................... 22
RD7/PSP7 ................................................................. 15
RE0/RD ..................................................................... 16
RE0/RD/AD8 .............................................................. 23
RE1/WR ..................................................................... 16
RE1/WR/AD9 ............................................................. 23
RE2/AD10/CS ............................................................ 23
RE2/CS ...................................................................... 16
RE3 ............................................................................ 16
RE3/AD11 .................................................................. 23
RE4 ............................................................................ 16
RE4/AD12 .................................................................. 23
RE5 ............................................................................ 16
RE5/AD13 .................................................................. 23
RE6 ............................................................................ 16
RE6/AD14 .................................................................. 23
RE7/AD15/CCP2 ....................................................... 23
RE7/CCP2 ................................................................. 16
RF1/AN6/C2OUT ................................................. 17, 24
RF2/AN7/C1OUT ................................................. 17, 24
RF3/AN8 .............................................................. 17, 24
RF4/AN9 .............................................................. 17, 24
RF5/AN10/CVREF ................................................ 17, 24
RF6/AN11 ............................................................ 17, 24
RF7/AN5/SS ........................................................ 17, 24
RG0 ..................................................................... 18, 25
RG1/TX2/CK2 ...................................................... 18, 25
RG2/RX2/DT2 ...................................................... 18, 25
RG3 ..................................................................... 18, 25
RG4 ..................................................................... 18, 25
RH0/A16 .................................................................... 26
RH1/A17 .................................................................... 26
RH2/A18 .................................................................... 26
RH3/A19 .................................................................... 26
RH4 ........................................................................... 26
RH5 ........................................................................... 26
RH6 ........................................................................... 26
RH7 ........................................................................... 26
RJ0/ALE .................................................................... 27
RJ1/OE ...................................................................... 27
RJ2/WRL ................................................................... 27
RJ3/WRH ................................................................... 27
RJ4/BA0 .................................................................... 27
RJ5/CE ...................................................................... 27
RJ6/LB ....................................................................... 27
RJ7/UB ...................................................................... 27
VDD ...................................................................... 18, 27
VDDCORE/VCAP ..................................................... 18, 27
VSS ...................................................................... 18, 27
Pinout I/O Descriptions
N
NEGF ...............................................................................313
NOP .................................................................................313
O
Oscillator Configuration ......................................................29
EC ..............................................................................29
ECPLL ........................................................................29
HS ..............................................................................29
HSPLL ........................................................................29
Internal Oscillator Block .............................................35
INTOSC .....................................................................29
INTRC ........................................................................29
Oscillator Selection ..........................................................271
Oscillator Start-up Timer (OST) .........................................36
Oscillator Switching ............................................................31
Oscillator Transitions ..........................................................32
Oscillator, Timer1 ..................................................... 151, 161
Oscillator, Timer3 .............................................................159
P
Packaging ........................................................................375
Details ......................................................................376
Marking ....................................................................375
Parallel Slave Port (PSP) .................................................144
Associated Registers ...............................................146
RE0/RD Pin ..............................................................144
RE1/WR Pin .............................................................144
RE2/CS Pin ..............................................................144
PICSTART Plus Development Programmer ....................338
PIE Registers ...................................................................115
Pin Functions
AVDD ....................................................................18, 27
AVSS ....................................................................18, 27
ENVREG .............................................................. 18, 27
MCLR ................................................................... 12, 19
RA0/AN0 .............................................................. 12, 19
RA1/AN1 .............................................................. 12, 19
RA2/AN2/VREF- .................................................... 12, 19
RA3/AN3/VREF+ ................................................... 12, 19
RA4/T0CKI ........................................................... 12, 19
RA5/AN4 .............................................................. 12, 19
RA6/OSC2/CLKO ................................................ 12, 19
RA7/OSC1/CLKI .................................................. 12, 19
RB0/INT0 ............................................................. 13, 20
RB1/INT1 ............................................................. 13, 20
RB2/INT2 ............................................................. 13, 20
RB3/INT3 ...................................................................13
RB3/INT3/CCP2 .........................................................20
RB4/KBI0 ............................................................. 13, 20
RB5/KBI1 ............................................................. 13, 20
RB6/KBI2/PGC .................................................... 13, 20
RB7/KBI3/PGD .................................................... 13, 20
RC0/T1OSO/T13CKI ...........................................14, 21
RC1/T1OSI/CCP2 ................................................ 14, 21
RC2/CCP1 ........................................................... 14, 21
RC3/SCK/SCL ..................................................... 14, 21
RC4/SDI/SDA ...................................................... 14, 21
RC5/SDO ............................................................. 14, 21
RC6/TX1/CK1 ...................................................... 14, 21
RC7/RX1/DT1 ...................................................... 14, 21
RD0/AD0/PSP0 ..........................................................22
RD0/PSP0 ..................................................................15
RD1/AD1/PSP1 ..........................................................22
RD1/PSP1 ..................................................................15
PIC18F6XJ11 ............................................................ 12
PIC18F8XJ11 ............................................................ 19
PIR Registers ................................................................... 112
DS39774C-page 386
Preliminary
© 2007 Microchip Technology Inc.
PIC18F85J11 FAMILY
PLL ..................................................................................... 34
ECPLL Oscillator Mode .............................................. 34
HSPLL Oscillator Mode .............................................. 34
POP ................................................................................. 314
POR. See Power-on Reset.
Idle Modes ................................................................. 41
PRI_IDLE .......................................................... 42
RC_IDLE ........................................................... 43
SEC_IDLE ......................................................... 42
Multiple Sleep Commands ......................................... 38
Run Modes ................................................................ 38
PRI_RUN ........................................................... 38
RC_RUN ............................................................ 40
SEC_RUN ......................................................... 38
Selecting .................................................................... 37
Sleep Mode ............................................................... 41
Summary (table) ........................................................ 37
Power-on Reset (POR) ...................................................... 47
Power-up Delays ............................................................... 36
Power-up Timer (PWRT) ............................................. 36, 48
Time-out Sequence ................................................... 48
Prescaler, Capture ........................................................... 166
Prescaler, Timer0 ............................................................ 149
Prescaler, Timer2 ............................................................ 170
PRI_IDLE Mode ................................................................. 42
PRI_RUN Mode ................................................................. 38
Program Counter ............................................................... 61
PCL, PCH and PCU Registers .................................. 61
PCLATH and PCLATU Registers .............................. 61
Program Memory
PORTA
Associated Registers ............................................... 125
LATA Register .......................................................... 124
PORTA Register ...................................................... 124
TRISA Register ........................................................ 124
PORTB
Associated Registers ............................................... 127
LATB Register .......................................................... 126
PORTB Register ...................................................... 126
RB7:RB4 Interrupt-on-Change
Flag (RBIF Bit) ................................................. 126
TRISB Register ........................................................ 126
PORTC
Associated Registers ............................................... 130
LATC Register ......................................................... 128
PORTC Register ...................................................... 128
RC3/SCK/SCL Pin ................................................... 189
TRISC Register ........................................................ 128
PORTD ............................................................................ 144
Associated Registers ............................................... 133
LATD Register ......................................................... 131
PORTD Register ...................................................... 131
TRISD Register ........................................................ 131
PORTE
Associated Registers ............................................... 136
LATE Register .......................................................... 134
PORTE Register ...................................................... 134
RE0/RD Pin .............................................................. 144
RE1/WR Pin ............................................................. 144
RE2/CS Pin .............................................................. 144
TRISE Register ........................................................ 134
PORTF
Associated Registers ............................................... 138
LATF Register .......................................................... 137
PORTF Register ...................................................... 137
TRISF Register ........................................................ 137
PORTG
Associated Registers ............................................... 140
LATG Register ......................................................... 139
PORTG Register ...................................................... 139
TRISG Register ........................................................ 139
PORTH
Extended Instruction Set ........................................... 78
Flash Configuration Words ........................................ 58
Hard Memory Vectors ................................................ 58
Instructions ................................................................ 65
Two-Word .......................................................... 65
Interrupt Vector .......................................................... 58
Look-up Tables .......................................................... 63
Memory Maps ............................................................ 57
Hard Vectors and
Configuration Words .................................. 58
Modes ........................................................................ 59
Extended Microcontroller ................................... 59
Extended Microcontroller
(Address Shifting) ...................................... 60
Memory Access (table) ...................................... 60
Microcontroller ................................................... 59
Reset Vector .............................................................. 58
Program Memory Modes
Operation of the External Memory Bus ..................... 96
Program Verification and Code Protection ...................... 284
Programming, Device Instructions ................................... 285
PSP.See Parallel Slave Port.
Associated Registers ............................................... 141
LATH Register ......................................................... 141
PORTH Register ...................................................... 141
TRISH Register ........................................................ 141
PORTJ
PSPMODE Bit (PSPCON Register) ................................. 144
Pulse-Width Modulation. See PWM (CCP Module).
PUSH ............................................................................... 314
PUSH and POP Instructions .............................................. 62
PUSHL ............................................................................. 330
PWM (CCP Module)
Associated Registers ............................................... 143
LATJ Register .......................................................... 142
PORTJ Register ....................................................... 142
TRISJ Register ......................................................... 142
Power-Managed Modes ..................................................... 37
and SPI Operation ................................................... 181
Clock Sources ............................................................ 37
Clock Transitions and Status Indicators ..................... 38
Entering ...................................................................... 37
Exiting Idle and Sleep Modes .................................... 43
By Interrupt ........................................................ 43
By Reset ............................................................ 43
By WDT Time-out .............................................. 43
Without an Oscillator Start-up Delay .................. 43
Associated Registers ............................................... 171
Duty Cycle ............................................................... 170
Example Frequencies/Resolutions .......................... 170
Period ...................................................................... 169
Setup for PWM Operation ....................................... 171
TMR2 to PR2 Match ................................................ 169
Q
Q Clock ............................................................................ 170
© 2007 Microchip Technology Inc.
Preliminary
DS39774C-page 387
PIC18F85J11 FAMILY
TXSTA1 (EUSART Transmit Status
and Control) ..................................................... 218
TXSTA2 (AUSART Transmit Status
R
RAM. See Data Memory.
RC_IDLE Mode ..................................................................43
RC_RUN Mode ..................................................................40
RCALL ..............................................................................315
RCON Register
Bit Status During Initialization ....................................50
Reader Response ............................................................392
Register File .......................................................................69
Register File Summary ................................................. 71–74
Registers
and Control) ..................................................... 238
WDTCON (Watchdog Timer Control) ...................... 278
RESET ............................................................................. 315
Reset ................................................................................. 45
Brown-out Reset (BOR) ............................................. 45
MCLR Reset, During Power-Managed Modes .......... 45
MCLR Reset, Normal Operation ................................ 45
Power-on Reset (POR) .............................................. 45
RESET Instruction ..................................................... 45
Stack Full Reset ......................................................... 45
Stack Underflow Reset .............................................. 45
Watchdog Timer (WDT) Reset .................................. 45
Resets .............................................................................. 271
Brown-out Reset (BOR) ........................................... 271
Oscillator Start-up Timer (OST) ............................... 271
Power-on Reset (POR) ............................................ 271
Power-up Timer (PWRT) ......................................... 271
RETFIE ............................................................................ 316
RETLW ............................................................................ 316
RETURN .......................................................................... 317
Return Address Stack ........................................................ 61
Return Stack Pointer (STKPTR) ........................................ 62
RLCF ............................................................................... 317
RLNCF ............................................................................. 318
RRCF ............................................................................... 318
RRNCF ............................................................................ 319
ADCON0 (A/D Control 0) .........................................251
ADCON1 (A/D Control 1) .........................................252
ADCON2 (A/D Control 2) .........................................253
BAUDCON1 (Baud Rate Control 1) .........................220
CCPxCON (CCPx Control) ......................................163
CMCON (Comparator Control) ................................261
CONFIG1H (Configuration 1 High) ..........................273
CONFIG1L (Configuration 1 Low) ............................273
CONFIG2H (Configuration 2 High) ..........................275
CONFIG2L (Configuration 2 Low) ............................274
CONFIG3H (Configuration 3 High) ..........................276
CONFIG3L (Configuration 3 Low) ......................59, 276
CVRCON (Comparator Voltage
Reference Control) ...........................................267
DEVID1 (Device ID Register 1) ................................277
DEVID2 (Device ID Register 2) ................................277
EECON1 (EEPROM Control 1) ..................................85
INTCON (Interrupt Control) ......................................109
INTCON2 (Interrupt Control 2) .................................110
INTCON3 (Interrupt Control 3) .................................111
IPR1 (Peripheral Interrupt Priority 1) ........................118
IPR2 (Peripheral Interrupt Priority 2) ........................119
IPR3 (Peripheral Interrupt Priority 3) ........................120
MEMCON (External Memory Bus Control) ................94
OSCCON (Oscillator Control) ....................................30
OSCTUNE (Oscillator Tuning) ...................................31
PIE1 (Peripheral Interrupt Enable 1) ........................115
PIE2 (Peripheral Interrupt Enable 2) ........................116
PIE3 (Peripheral Interrupt Enable 3) ........................117
PIR1 (Peripheral Interrupt
S
SCK ................................................................................. 173
SDI ................................................................................... 173
SDO ................................................................................. 173
SEC_IDLE Mode ............................................................... 42
SEC_RUN Mode ................................................................ 38
Serial Clock, SCK ............................................................ 173
Serial Data In (SDI) .......................................................... 173
Serial Data Out (SDO) ..................................................... 173
Serial Peripheral Interface. See SPI Mode.
SETF ................................................................................ 319
Slave Select (SS) ............................................................. 173
SLEEP ............................................................................. 320
Sleep
Request (Flag) 1) .............................................112
PIR2 (Peripheral Interrupt
Request (Flag) 2) .............................................113
PIR3 (Peripheral Interrupt
Request (Flag) 3) .............................................114
PSPCON (Parallel Slave Port Control) ....................145
RCON (Reset Control) ....................................... 46, 121
RCSTA1 (EUSART Receive
OSC1 and OSC2 Pin States ...................................... 36
Software Simulator (MPLAB SIM) ................................... 336
Special Event Trigger. See Compare (CCP Module).
Special Features of the CPU ........................................... 271
SPI Mode (MSSP)
Associated Registers ............................................... 181
Bus Mode Compatibility ........................................... 181
Effects of a Reset .................................................... 181
Enabling SPI I/O ...................................................... 177
Master Mode ............................................................ 178
Master/Slave Connection ......................................... 177
Operation ................................................................. 176
Operation in Power-Managed Modes ...................... 181
Serial Clock .............................................................. 173
Serial Data In ........................................................... 173
Serial Data Out ........................................................ 173
Slave Mode .............................................................. 179
Slave Select ............................................................. 173
Slave Select Synchronization .................................. 179
SPI Clock ................................................................. 178
Typical Connection .................................................. 177
Status and Control) ..........................................219
RCSTA2 (AUSART Receive
Status and Control) ..........................................239
2
SSPCON1 (MSSP Control 1, I C Mode) .................184
SSPCON1 (MSSP Control 1, SPI Mode) .................175
SSPCON2 (MSSP Control 2,
2
I C Master Mode) .............................................185
2
SSPCON2 (MSSP Control 2, I C Slave Mode) .......186
2
SSPSTAT (MSSP Status, I C Mode) .......................183
SSPSTAT (MSSP Status, SPI Mode) ......................174
STATUS .....................................................................75
STKPTR (Stack Pointer) ............................................62
T0CON (Timer0 Control) ..........................................147
T1CON (Timer1 Control) ..........................................151
T2CON (Timer2 Control) ..........................................157
T3CON (Timer3 Control) ..........................................159
DS39774C-page 388
Preliminary
© 2007 Microchip Technology Inc.
PIC18F85J11 FAMILY
SS .................................................................................... 173
SSPOV ............................................................................. 207
SSPOV Status Flag ......................................................... 207
SSPSTAT Register
Timing Diagrams
A/D Conversion ....................................................... 372
Acknowledge Sequence .......................................... 210
Asynchronous Reception ................................. 229, 245
Asynchronous Transmission ........................... 227, 243
Asynchronous Transmission
(Back-to-Back) ......................................... 227, 243
Automatic Baud Rate Calculation ............................ 225
Auto-Wake-up Bit (WUE) During
Normal Operation ............................................ 230
Auto-Wake-up Bit (WUE) During Sleep ................... 230
Baud Rate Generator with Clock Arbitration ............ 204
BRG Overflow Sequence ........................................ 225
BRG Reset Due to SDA Arbitration During
R/W Bit ............................................................. 187, 189
Stack Full/Underflow Resets .............................................. 63
STATUS Register .............................................................. 75
SUBFSR .......................................................................... 331
SUBFWB .......................................................................... 320
SUBLW ............................................................................ 321
SUBULNK ........................................................................ 331
SUBWF ............................................................................ 321
SUBWFB .......................................................................... 322
SWAPF ............................................................................ 322
Start Condition ................................................. 213
Bus Collision During a Repeated Start
Condition (Case 1) ........................................... 214
Bus Collision During a Repeated Start
Condition (Case 2) ........................................... 214
Bus Collision During a Start
Condition (SCL = 0) ......................................... 213
Bus Collision During a Stop
Condition (Case 1) ........................................... 215
Bus Collision During a Stop
Condition (Case 2) ........................................... 215
Bus Collision During Start
Condition (SDA Only) ...................................... 212
Bus Collision for Transmit and Acknowledge .......... 211
Capture/Compare/PWM (CCP1, CCP2) .................. 361
CLKO and I/O .......................................................... 358
Clock Synchronization ............................................. 197
Clock/Instruction Cycle .............................................. 64
EUSART/AUSART Synchronous Receive
(Master/Slave) ................................................. 370
EUSART/AUSART Synchronous Transmission
(Master/Slave) ................................................. 370
Example SPI Master Mode (CKE = 0) ..................... 362
Example SPI Master Mode (CKE = 1) ..................... 363
Example SPI Slave Mode (CKE = 0) ....................... 364
Example SPI Slave Mode (CKE = 1) ....................... 365
External Clock (All Modes Except PLL) ................... 356
External Memory Bus for Sleep (Extended
T
Table Pointer Operations (table) ........................................ 86
Table Reads/Table Writes ................................................. 63
TBLRD ............................................................................. 323
TBLWT ............................................................................. 324
Timer0 .............................................................................. 147
Associated Registers ............................................... 149
Clock Source Select (T0CS Bit) ............................... 148
Interrupt .................................................................... 149
Operation ................................................................. 148
Prescaler .................................................................. 149
Switching Assignment ...................................... 149
Prescaler Assignment (PSA Bit) .............................. 149
Prescaler Select (T0PS2:T0PS0 Bits) ..................... 149
Prescaler. See Prescaler, Timer0.
Reads and Writes in 16-Bit Mode ............................ 148
Source Edge Select (T0SE Bit) ................................ 148
Timer1 .............................................................................. 151
16-Bit Read/Write Mode ........................................... 153
Associated Registers ............................................... 155
Interrupt .................................................................... 154
Operation ................................................................. 152
Oscillator .......................................................... 151, 153
Layout Considerations ..................................... 154
Oscillator, as Secondary Clock .................................. 31
Overflow Interrupt .................................................... 151
Resetting, Using the CCPx
Special Event Trigger ...................................... 154
TMR1H Register ...................................................... 151
TMR1L Register ....................................................... 151
Use as a Clock Source ............................................ 153
Use as a Real-Time Clock ....................................... 154
Timer2 .............................................................................. 157
Associated Registers ............................................... 158
Interrupt .................................................................... 158
Operation ................................................................. 157
Output ...................................................................... 158
PR2 Register ............................................................ 169
TMR2 to PR2 Match Interrupt .................................. 169
Timer3 .............................................................................. 159
16-Bit Read/Write Mode ........................................... 161
Associated Registers ............................................... 161
Interrupt .................................................................... 161
Operation ................................................................. 160
Oscillator .......................................................... 159, 161
Overflow Interrupt .................................................... 159
Special Event Trigger (CCP) .................................... 161
TMR3H Register ...................................................... 159
TMR3L Register ....................................................... 159
Microcontroller Mode) .............................. 100, 102
External Memory Bus for TBLRD (Extended
Microcontroller Mode) .............................. 100, 102
Fail-Safe Clock Monitor ........................................... 283
First Start Bit Timing ................................................ 205
2
I C Bus Data ............................................................ 367
2
I C Bus Start/Stop Bits ............................................ 366
2
I C Master Mode (7 or 10-Bit Transmission) ........... 208
2
I C Master Mode (7-Bit Reception) ......................... 209
2
I C Slave Mode (10-Bit Reception, SEN = 0) .......... 193
2
I C Slave Mode (10-Bit Reception, SEN = 0,
ADMSK = 01001) ............................................ 194
I C Slave Mode (10-Bit Reception, SEN = 1) .......... 199
I C Slave Mode (10-Bit Transmission) .................... 195
I C Slave Mode (7-Bit Reception, SEN = 0) ............ 190
2
2
2
2
I C Slave Mode (7-Bit Reception, SEN = 0,
ADMSK = 01011) ............................................ 191
I C Slave Mode (7-Bit Reception, SEN = 1) ............ 198
I C Slave Mode (7-Bit Transmission) ...................... 192
I C Slave Mode General Call Address Sequence
2
2
2
(7 or 10-Bit Address Mode) ............................. 200
© 2007 Microchip Technology Inc.
Preliminary
DS39774C-page 389
PIC18F85J11 FAMILY
2
I C Stop Condition Receive or
Example SPI Mode Requirements
Transmit Mode .................................................210
(Master Mode, CKE = 0) .................................. 362
Example SPI Mode Requirements
(Master Mode, CKE = 1) .................................. 363
Example SPI Mode Requirements
(Slave Mode, CKE = 0) .................................... 364
Example SPI Slave Mode
2
MSSP I C Bus Data .................................................368
2
MSSP I C Bus Start/Stop Bits .................................368
Parallel Slave Port (PSP) Read ...............................146
Parallel Slave Port (PSP) Write ...............................145
PWM Output ............................................................169
Repeated Start Condition .........................................206
Reset, Watchdog Timer (WDT), Oscillator Start-up
Timer (OST) and Power-up Timer (PWRT) .....359
Send Break Character Sequence ............................231
Slave Synchronization .............................................179
Slow Rise Time (MCLR Tied to VDD,
VDD Rise > TPWRT) ............................................49
SPI Mode (Master Mode) .........................................178
SPI Mode (Slave Mode, CKE = 0) ...........................180
SPI Mode (Slave Mode, CKE = 1) ...........................180
Synchronous Reception
Requirements (CKE = 1) ................................. 365
External Clock Requirements .................................. 356
2
I C Bus Data Requirements (Slave Mode) .............. 367
2
I C Bus Start/Stop Bits Requirements
(Slave Mode) ................................................... 366
Internal RC Accuracy ............................................... 357
2
MSSP I C Bus Data Requirements ......................... 369
2
MSSP I C Bus Start/Stop Bits Requirements .......... 368
PLL Clock ................................................................ 357
Reset, Watchdog Timer, Oscillator Start-up
Timer, Power-up Timer and Brown-out
(Master Mode, SREN) .............................. 234, 248
Synchronous Transmission .............................. 232, 246
Synchronous Transmission
(Through TXEN) .......................................233, 247
Time-out Sequence on Power-up
Reset Requirements ........................................ 359
Timer0 and Timer1 External
Clock Requirements ........................................ 360
Top-of-Stack Access .......................................................... 61
TSTFSZ ........................................................................... 325
Two-Speed Start-up ................................................. 271, 281
Two-Word Instructions
(MCLR Not Tied to VDD), Case 1 .......................49
Time-out Sequence on Power-up
(MCLR Not Tied to VDD), Case 2 .......................49
Time-out Sequence on Power-up
Example Cases .......................................................... 65
V
(MCLR Tied to VDD, VDD Rise < TPWRT) ...........48
Timer0 and Timer1 External Clock ..........................360
Transition for Entry to Idle Mode ................................42
Transition for Entry to SEC_RUN Mode ....................39
Transition for Entry to Sleep Mode ............................41
Transition for Two-Speed Start-up
(INTRC to HSPLL) ...........................................281
Transition for Wake From Idle to Run Mode ..............42
Transition for Wake From Sleep (HSPLL) .................41
Transition From RC_RUN Mode to
VDDCORE/VCAP Pin .......................................................... 279
Voltage Reference Specifications .................................... 353
Voltage Regulator (On-Chip) ........................................... 279
Brown-out Reset (BOR) ........................................... 280
Low-Voltage Detection (LVD) .................................. 279
Operation in Sleep Mode ......................................... 280
Power-up Requirements .......................................... 280
W
Watchdog Timer (WDT) ........................................... 271, 278
Associated Registers ............................................... 278
Control Register ....................................................... 278
Programming Considerations .................................. 278
WCOL ...................................................... 205, 206, 207, 210
WCOL Status Flag ................................... 205, 206, 207, 210
WWW Address ................................................................ 391
WWW, On-Line Support ...................................................... 5
PRI_RUN Mode .................................................40
Transition From SEC_RUN Mode to
PRI_RUN Mode (HSPLL) ..................................39
Transition to RC_RUN Mode .....................................40
Timing Diagrams and Specifications
Capture/Compare/PWM Requirements
(CCP1, CCP2) .................................................361
CLKO and I/O Requirements ...................................358
EUSART/AUSART Synchronous Receive
Requirements ...................................................370
EUSART/AUSART Synchronous Transmission
Requirements ...................................................370
X
XORLW ............................................................................ 325
XORWF ........................................................................... 326
DS39774C-page 390
Preliminary
© 2007 Microchip Technology Inc.
PIC18F85J11 FAMILY
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DS39774C-page 392
Preliminary
© 2007 Microchip Technology Inc.
PIC18F85J11 FAMILY
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
PART NO.
Device
X
/XX
XXX
Examples:
Temperature
Range
Package
Pattern
a)
PIC18F85J11-I/PT 301 = Industrial temp.,
TQFP package, QTP pattern #301.
PIC18F63J11T-I/PT = Tape and reel, Industrial
temp., TQFP package.
b)
Device
PIC18F63J11/64J11/65J11(1)
PIC18F83J11/84J11/85J11(1)
,
,
PIC18F63J11/64J11/65J11T(2)
PIC18F83J11/84J11/85J11T(2)
,
Temperature Range
Package
I
= -40°C to +85°C (Industrial)
PT = TQFP (Thin Quad Flatpack)
Pattern
QTP, SQTP, Code or Special Requirements
(blank otherwise)
Note 1:
2:
F
T
=
=
Standard Voltage Range
In Tape and Reel
© 2007 Microchip Technology Inc.
Preliminary
DS39774C-page 393
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12/08/06
DS39774C-page 394
Preliminary
© 2007 Microchip Technology Inc.
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