PIC18F8525-EPTQTP [MICROCHIP]
64/80-Pin High Performance, 64-Kbyte Enhanced FLASH Microcontrollers with A/D; 八十〇分之六十四引脚高性能， 64 KB的增强型闪存微控制器与A / D
| 型号： | PIC18F8525-EPTQTP |
| 厂家： | 
MICROCHIP |
| 描述： | 64/80-Pin High Performance, 64-Kbyte Enhanced FLASH Microcontrollers with A/D |
| 文件： | 总386页 (文件大小：6657K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PIC18F6X2X/8X2X
Data Sheet
64/80-Pin High Performance,
64-Kbyte Enhanced FLASH
Microcontrollers with A/D
2003 Microchip Technology Inc.
Advance Information
DS39612A
Note the following details of the code protection feature on Microchip devices:
•
Microchip products meet the specification contained in their particular Microchip Data Sheet.
•
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
•
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip's Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
•
•
Microchip is willing to work with the customer who is concerned about the integrity of their code.
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device
applications and the like is intended through suggestion only
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
No representation or warranty is given and no liability is
assumed by Microchip Technology Incorporated with respect
to the accuracy or use of such information, or infringement of
patents or other intellectual property rights arising from such
use or otherwise. Use of Microchip’s products as critical
components in life support systems is not authorized except
with express written approval by Microchip. No licenses are
conveyed, implicitly or otherwise, under any intellectual
property rights.
Trademarks
The Microchip name and logo, the Microchip logo, dsPIC,
KEELOQ, MPLAB, PIC, PICmicro, PICSTART, PRO MATE and
PowerSmart are registered trademarks of Microchip
Technology Incorporated in the U.S.A. and other countries.
FilterLab, microID, MXDEV, MXLAB, PICMASTER, SEEVAL
and The Embedded Control Solutions Company are
registered trademarks of Microchip Technology Incorporated
in the U.S.A.
Accuron, Application Maestro, dsPICDEM, dsPICDEM.net,
ECONOMONITOR, FanSense, FlexROM, fuzzyLAB, In-
Circuit Serial Programming, ICSP, ICEPIC, microPort,
Migratable Memory, MPASM, MPLIB, MPLINK, MPSIM,
PICC, PICkit, PICDEM, PICDEM.net, PowerCal, PowerInfo,
PowerMate, PowerTool, rfLAB, rfPIC, Select Mode,
SmartSensor, SmartShunt, SmartTel and Total Endurance are
trademarks of Microchip Technology Incorporated in the
U.S.A. and other countries.
Serialized Quick Turn Programming (SQTP) is a service mark
of Microchip Technology Incorporated in the U.S.A.
All other trademarks mentioned herein are property of their
respective companies.
© 2003, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.
Printed on recycled paper.
Microchip received QS-9000 quality system
certification for its worldwide headquarters,
design and wafer fabrication facilities in
Chandler and Tempe, Arizona in July 1999
and Mountain View, California in March 2002.
The Company’s quality system processes and
procedures are QS-9000 compliant for its
PICmicro® 8-bit MCUs, KEELOQ® code hopping
devices, Serial EEPROMs, microperipherals,
non-volatile memory and analog products. In
addition, Microchip’s quality system for the
design and manufacture of development
systems is ISO 9001 certified.
DS39612A-page ii
Advance Information
2003 Microchip Technology Inc.
PIC18F6X2X/8X2X
64/80-Pin High Performance, 64-Kbyte Enhanced FLASH
Microcontrollers with A/D
High Performance RISC CPU:
External Memory Interface
(PIC18F8X2X Devices Only):
• Address capability of up to 2 Mbytes
• 16-bit interface
• Linear program memory addressing to 64 Kbytes
• Linear data memory addressing to 4 Kbytes
• 1 Kbyte of data EEPROM
• Up to 10 MIPs operation:
- DC - 40 MHz osc./clock input
Analog Features:
• 10-bit, up to 16-channel Analog-to-Digital
Converter (A/D):
- Auto acquisition
- Conversion available during SLEEP
• Programmable 16-level Low Voltage Detection
(LVD) module:
- Supports interrupt on Low Voltage Detection
• Programmable Brown-out Reset (BOR)
• Dual analog comparators:
- 4 MHz - 10 MHz osc./clock input with PLL active
• 16-bit wide instructions, 8-bit wide data path
• Priority levels for interrupts
• 31-level, software accessible hardware stack
• 8 x 8 Single Cycle Hardware Multiplier
Peripheral Features:
• High current sink/source 25 mA/25 mA
• Four external interrupt pins
- Programmable input/output configuration
• Timer0 module: 8-bit/16-bit timer/counter
• Timer1 module: 16-bit timer/counter
• Timer2 module: 8-bit timer/counter
• Timer3 module: 16-bit timer/counter
• Timer4 module: 8-bit timer/counter
• Secondary oscillator clock option - Timer1/Timer3
• Two Capture/Compare/PWM (CCP) modules:
- Capture is 16-bit, max. resolution 6.25 ns (TCY/16)
- Compare is 16-bit, max. resolution 100 ns (TCY)
- PWM output: PWM resolution is 1 to 10-bit
• Three Enhanced Capture/Compare/PWM (ECCP)
modules:
- Same Capture/Compare features as CCP
- One, two, or four PWM outputs
- Selectable polarity
- Programmable dead-time
- Auto shutdown on external event
- Auto Restart
Special Microcontroller Features:
• 100,000 erase/write cycle Enhanced FLASH
program memory typical
• 1,000,000 erase/write cycle Data EEPROM
memory typical
• 1 second programming time
• FLASH/Data EEPROM Retention: > 100 years
• Self-reprogrammable under software control
• Power-on Reset (POR), Power-up Timer (PWRT)
and Oscillator Start-up Timer (OST)
• Watchdog Timer (WDT) with its own On-Chip
RC Oscillator for reliable operation
• Programmable code protection
• Power saving SLEEP mode
• Selectable oscillator options including:
- 4X Phase Lock Loop (of primary oscillator)
- Secondary Oscillator (32 kHz) clock input
• In-Circuit Serial Programming™ (ICSP™) via two pins
• MPLAB® In-Circuit Debug (ICD 2) via two pins
• Master Synchronous Serial Port (MSSP) module
with two modes of operation:
- 3-wire SPI™ (supports all 4 SPI modes)
2
CMOS Technology:
- I C™ Master and Slave mode
• Two Enhanced USART modules:
- Supports RS-485, RS-232, and LIN 1.2
- Auto wake-up on START bit
- Auto baud detect
• Low power, high speed FLASH technology
• Fully static design
• Wide operating voltage range (2.0V to 5.5V)
• Industrial and Extended temperature ranges
• Parallel Slave Port (PSP) module
Program Memory
# Single
Data Memory
10-bit
A/D
(ch)
MSSP/
SPI/
CCP/
ECCP
Timers
8-bit/16-bit
Device
I/O
PWM
EUSART
EMI
SRAM EEPROM
(bytes) (bytes)
2
Bytes
Word
Master I C
Instructions
PIC18F6525 48K
PIC18F6621 64K
PIC18F8525 48K
PIC18F8621 64K
24576
32768
24576
32768
3840
3840
3840
3840
1024
1024
1024
1024
53
53
69
69
12
12
16
16
2/3
2/3
2/3
2/3
14
14
14
14
Y
Y
Y
Y
2
2
2
2
2/3
2/3
2/3
2/3
N
N
Y
Y
2003 Microchip Technology Inc.
Advance Information
DS39612A-page 1
PIC18F6X2X/8X2X
Pin Diagrams
64-Pin TQFP
64 63 62 61 60 59 58 57 56 55 54 53 52 51
50 49
RB0/INT0
RE1/WR/P2C
RE0/RD/P2D
RG0/CCP3/P3A
RG1/TX2/CK2
RG2/RX2/DT2
RG3/CCP4/P3D
MCLR/VPP/RG5
RG4/CCP5/P1D
VSS
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
1
RB1/INT1
2
RB2/INT2
3
RB3/INT3
4
RB4/KBI0
5
RB5/KBI1/PGM
RB6/KBI2/PGC
VSS
6
7
PIC18F6525
PIC18F6621
8
OSC2/CLKO/RA6
OSC1/CLKI
VDD
9
VDD
10
11
12
13
14
15
16
RF7/SS
RB7/KBI3/PGD
RC5/SDO
RF6/AN11
RF5/AN10/CVREF
RF4/AN9
RC4/SDI/SDA
RC3/SCK/SCL
RC2/CCP1/P1A
RF3/AN8
RF2/AN7/C1OUT
17 18 19 20 21 22 23 24 25 26 27 28
29 30 31 32
Note 1: CCP2/P2A are multiplexed with RC1 when CCP2MX is set, or RE7 when CCP2MX is not set.
DS39612A-page 2
Advance Information
2003 Microchip Technology Inc.
PIC18F6X2X/8X2X
Pin Diagrams (Cont.’d)
80-Pin TQFP
80 79 78
77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61
RH2/A18
RH3/A19
RJ2/WRL
RJ3/WRH
RB0/INT0
RB1/INT1
1
2
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
RE1/AD9/WR/P2C
RE0/AD8/RD/P2D
RG0/CCP3/P3A
RG1/TX2/CK2
RG2/RX2/DT2
RG3/CCP4/P3D
MCLR/VPP/RG5
RG4/CCP5/P1D
VSS
3
4
RB2/INT2
RB3/INT3/CCP2(1)/P2A(1)
5
6
RB4/KBI0
7
RB5/KBI1/PGM
RB6/KBI2/PGC
VSS
8
9
PIC18F8525
PIC18F8621
10
11
12
13
14
15
16
17
18
19
20
OSC2/CLKO/RA6
OSC1/CLKI
VDD
VDD
RF7/SS
RB7/KBI3/PGD
RC5/SDO
RF6/AN11
RF5/AN10/CVREF
RF4/AN9
RC4/SDI/SDA
RC3/SCK/SCL
RC2/CCP1/P1A
RJ7/UB
RF3/AN8
RF2/AN7/C1OUT
RH7/AN15/P1B(2)
RH6/AN14/P1C(2)
RJ6/LB
40
21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39
Note 1: CCP2/P2A are multiplexed with RC1 when CCP2MX is set; with RE7 when CCP2MX is cleared and the device is
configured in Microcontroller mode; or with RB3 when CCP2MX is cleared in all other Program Memory modes.
2: P1B/P1C/P3B/P3C are multiplexed with RE6:RE3 when ECCPMX is set, and with RH7:RH4 when ECCPMX is
not set.
2003 Microchip Technology Inc.
Advance Information
DS39612A-page 3
PIC18F6X2X/8X2X
Table of Contents
1.0 Device Overview .......................................................................................................................................................................... 7
2.0 Oscillator Configurations ............................................................................................................................................................ 21
3.0 Reset.......................................................................................................................................................................................... 31
4.0 Memory Organization................................................................................................................................................................. 41
5.0 FLASH Program Memory........................................................................................................................................................... 63
6.0 External Memory Interface ......................................................................................................................................................... 73
7.0 Data EEPROM Memory ............................................................................................................................................................. 81
8.0 8 X 8 Hardware Multiplier........................................................................................................................................................... 87
9.0 Interrupts .................................................................................................................................................................................... 89
10.0 I/O Ports ................................................................................................................................................................................... 105
11.0 Timer0 Module ......................................................................................................................................................................... 133
12.0 Timer1 Module ......................................................................................................................................................................... 137
13.0 Timer2 Module ......................................................................................................................................................................... 143
14.0 Timer3 Module ......................................................................................................................................................................... 145
15.0 Timer4 Module ......................................................................................................................................................................... 149
16.0 Capture/Compare/PWM (CCP) Modules ................................................................................................................................. 151
17.0 Enhanced Capture/Compare/PWM (ECCP) Module................................................................................................................ 159
18.0 Master Synchronous Serial Port (MSSP) Module .................................................................................................................... 175
19.0 Enhanced Universal Synchronous Asynchronous Receiver Transmitter (USART).................................................................. 215
20.0 10-bit Analog-to-Digital Converter (A/D) Module...................................................................................................................... 235
21.0 Comparator Module.................................................................................................................................................................. 243
22.0 Comparator Voltage Reference Module................................................................................................................................... 249
23.0 Low Voltage Detect .................................................................................................................................................................. 253
24.0 Special Features of the CPU.................................................................................................................................................... 259
25.0 Instruction Set Summary.......................................................................................................................................................... 277
26.0 Development Support............................................................................................................................................................... 319
27.0 Electrical Characteristics.......................................................................................................................................................... 325
28.0 DC and AC Characteristics Graphs and Tables....................................................................................................................... 359
29.0 Packaging Information.............................................................................................................................................................. 361
Appendix A: Revision History............................................................................................................................................................. 365
Appendix B: Device Differences......................................................................................................................................................... 365
Appendix C: Conversion Considerations ........................................................................................................................................... 366
Appendix D: Migration from Mid-Range to Enhanced Devices.......................................................................................................... 366
Appendix E: Migration from High-End to Enhanced Devices............................................................................................................. 367
Index .................................................................................................................................................................................................. 369
On-Line Support................................................................................................................................................................................. 379
Systems Information and Upgrade Hot Line ...................................................................................................................................... 379
Reader Response .............................................................................................................................................................................. 380
PIC18F6X2X/8X2X Product Identification System............................................................................................................................. 381
DS39612A-page 4
Advance Information
2003 Microchip Technology Inc.
PIC18F6X2X/8X2X
TO OUR VALUED CUSTOMERS
It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip
products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and
enhanced as new volumes and updates are introduced.
If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via
E-mail at docerrors@mail.microchip.com or fax the Reader Response Form in the back of this data sheet to (480) 792-4150.
We welcome your feedback.
Most Current Data Sheet
To obtain the most up-to-date version of this data sheet, please register at our Worldwide Web site at:
http://www.microchip.com
You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page.
The last character of the literature number is the version number, (e.g., DS30000A is version A of document DS30000).
Errata
An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current
devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision
of silicon and revision of document to which it applies.
To determine if an errata sheet exists for a particular device, please check with one of the following:
•
•
•
Microchip’s Worldwide Web site; http://www.microchip.com
Your local Microchip sales office (see last page)
The Microchip Corporate Literature Center; U.S. FAX: (480) 792-7277
When contacting a sales office or the literature center, please specify which device, revision of silicon and data sheet (include liter-
ature number) you are using.
Customer Notification System
Register on our web site at www.microchip.com/cn to receive the most current information on all of our products.
2003 Microchip Technology Inc.
Advance Information
DS39612A-page 5
PIC18F6X2X/8X2X
NOTES:
DS39612A-page 6
Advance Information
2003 Microchip Technology Inc.
PIC18F6X2X/8X2X
With the addition of new operating modes, the external
memory interface offers many new options, including:
1.0
DEVICE OVERVIEW
This document contains device specific information for
the following devices:
• Operating the microcontroller entirely from external
memory
• PIC18F6525
• PIC18F6621
• PIC18F8525
• PIC18F8621
• Using combinations of on-chip and external
memory, up to the 2-Mbyte limit
• Using external FLASH memory for reprogrammable
application code or large data tables
• Using external RAM devices for storing large
amounts of variable data
This family offers the advantages of all
PIC18 microcontrollers - namely, high computational
performance at an economical price - with the
addition of high endurance enhanced FLASH program
memory. The PIC18F6X2X/8X2X family also provides
an enhanced range of program memory options and
versatile analog features that make it ideal for complex,
high performance applications.
1.1.3
EASY MIGRATION
Regardless of the memory size, all devices share the
same rich set of peripherals, allowing for a smooth
migration path as applications grow and evolve.
The consistent pinout scheme used throughout the
entire family also aids in migrating to the next larger
device. This is true when moving between the 64-pin
members, between the 80-pin members, or even
jumping from 64-pin to 80-pin devices.
1.1
Key Features
1.1.1
EXPANDED MEMORY
The PIC18F6X2X/8X2X family provides ample room
for application code, and includes members with
48 Kbytes or 64 Kbytes of code space.
1.1.4
• Communications: The PIC18F6X2X/8X2X family
incorporates range of serial communication
OTHER SPECIAL FEATURES
a
Other memory features are:
peripherals, including 2 independent enhanced
USARTs and a Master SSP module capable of both
SPI and I2C (Master and Slave) modes of operation.
Also, for PIC18F6X2X/8X2X devices, one of the
general purpose I/O ports can be reconfigured as an
8-bit parallel slave port for direct processor to
processor communications.
• Data
RAM
and
Data
EEPROM:
The
PIC18F6X2X/8X2X family also provides plenty of
room for application data. The devices have
3840 bytes of data RAM as well as 1024 bytes of
data EEPROM for long term retention of non-volatile
data.
• Memory Endurance: The enhanced FLASH cells
for both program memory and data EEPROM are
rated to last for many thousands of erase/write
• CCP Modules: All devices in the family incorporate
two Capture/Compare/PWM (CCP) modules and
three enhanced CCP modules to maximize flexibility
in control applications. Up to four different time
bases may be used to perform several different
operations at once. Each of the three ECCPs offer
up to four PWM outputs, allowing for a total of 12
PWMs. The ECCPs also offer many beneficial fea-
tures, including polarity selection, programmable
dead-time, auto shutdown and restart, and
Half-Bridge and Full-Bridge Output modes.
cycles
- up to 100,000 for program memory, and
1,000,000 for EEPROM. Data retention without
refresh is conservatively estimated to be greater
than 40 years.
1.1.2
EXTERNAL MEMORY INTERFACE
In the unlikely event that 64 Kbytes of program memory
is inadequate for an application, the PIC18F8X2X
members of the family also implement an external
memory interface. This allows the controller’s internal
program counter to address a memory space of up to
2 MBytes, permitting a level of data access that few
8-bit devices can claim.
• Analog Features: All devices in the family feature
10-bit A/D converters with up to 16 input channels,
as well as the ability to perform conversions during
SLEEP mode and auto-acquisition conversions.
Also included are dual analog comparators with
programmable input and output configuration, a
programmable Low Voltage Detect module, and a
Programmable Brown-out Reset module.
• Self-programmability: These devices can write to
their own program memory spaces under internal
software control. By using a bootloader routine
located in the protected boot block at the top of
program memory, it becomes possible to create an
application that can update itself in the field.
2003 Microchip Technology Inc.
Advance Information
DS39612A-page 7
PIC18F6X2X/8X2X
3. I/O ports (7 on PIC18F6X2X devices, 9 on
PIC18F8X2X)
1.2
Details on Individual Family
Members
4. External program memory interface (present
only on PIC18F8X2X devices)
The PIC18F6X2X/8X2X devices are available in 64-pin
and 80-pin packages. They are differentiated from
each other in four ways:
All other features for devices in the PIC18F6X2X/8X2X
family are identical. These are summarized in
Table 1-1.
1. FLASH program memory (48 Kbytes for
PIC18FX525 devices and 64 Kbytes for
PIC18FX621 devices)
Block diagrams of the PIC18F6X2X and PIC18F8X2X
devices are provided in Figure 1-1 and Figure 1-2,
respectively. The pinouts for these device families are
listed in Table 1-2.
2. A/D channels (12 for PIC18F6X2X devices,
16 for PIC18F8X2X)
TABLE 1-1:
PIC18F6X2X/8X2X DEVICE FEATURES
Features
PIC18F6525
PIC18F6621
PIC18F8525
PIC18F8621
Operating Frequency
Program Memory (Bytes)
Program Memory (Instructions)
Data Memory (Bytes)
Data EEPROM Memory (Bytes)
External Memory Interface
Interrupt Sources
DC - 40 MHz
48K
DC - 40 MHz
64K
DC - 40 MHz
48K
DC - 40 MHz
64K
24576
3840
32768
3840
24576
3840
32768
3840
1024
1024
1024
1024
No
No
Yes
Yes
17
17
17
17
I/O Ports
Ports A, B, C, D,
E, F, G
Ports A, B, C, D, Ports A, B, C, D, E, Ports A, B, C, D, E,
E, F, G
F, G, H, J
F, G, H, J
Timers
5
2
3
5
2
3
5
2
3
5
2
3
Capture/Compare/PWM Modules
Enhanced Capture/Compare/
PWM Module
Serial Communications
MSSP,
MSSP,
MSSP,
MSSP,
Addressable
EUSART (2)
Addressable
EUSART (2)
Addressable
EUSART (2)
Addressable
EUSART (2)
Parallel Communications
10-bit Analog-to-Digital Module
RESETS (and Delays)
PSP
PSP
PSP
PSP
12 input channels 12 input channels 16 input channels 16 input channels
POR, BOR, POR, BOR, POR, BOR, POR, BOR,
RESETInstruction, RESETInstruction, RESETInstruction, RESETInstruction,
Stack Full,
Stack Underflow
(PWRT, OST)
Stack Full,
Stack Underflow
(PWRT, OST)
Stack Full,
Stack Underflow
(PWRT, OST)
Stack Full,
Stack Underflow
(PWRT, OST)
Programmable Low Voltage
Detect
Yes
Yes
Yes
Yes
Programmable Brown-out Reset
Instruction Set
Yes
Yes
Yes
Yes
77 Instructions
64-pin TQFP
77 Instructions
64-pin TQFP
77 Instructions
80-pin TQFP
77 Instructions
80-pin TQFP
Package
DS39612A-page 8
Advance Information
2003 Microchip Technology Inc.
PIC18F6X2X/8X2X
FIGURE 1-1:
PIC18F6525/6621 BLOCK DIAGRAM
Data Bus<8>
PORTA
RA0/AN0
Table Pointer<21>
inc/dec logic
Data Latch
21
RA1/AN1
RA2/AN2/VREF-
RA3/AN3/VREF+
RA4/T0CKI
8
8
Data RAM
( 3.8 Kbytes )
21
RA5/AN4/LVDIN
OSC2/CLKO/RA6
Address Latch
12
20
PCLATU PCLATH
PORTB
Address<12>
RB0/INT0
PCU PCH PCL
Program Counter
RB1/INT1
RB2/INT2
RB3/INT3
4
BSR
12
FSR0
4
Bank 0, F
Address Latch
FSR1
FSR2
RB4/KBI0
Program Memory
(48/64 Kbytes)
31 Level Stack
RB5/KBI1/PGM
RB6/KBI2/PGC
RB7/KBI3/PGD
12
Data Latch
inc/dec
logic
Decode
PORTC
Table Latch
RC0/T1OSO/T13CKI
RC1/T1OSI/CCP2(1)/P2A(1)
RC2/CCP1/P1A
8
16
ROM Latch
IR
RC3/SCK/SCL
RC4/SDI/SDA
RC5/SDO
RC6/TX1/CK1
RC7/RX1/DT1
PORTD
PORTE
8
RD7/PSP7 :RD0/PSP0
PRODH PRODL
8 x 8 Multiply
Instruction
Decode &
Control
RE0/RD/P2D
RE1/WR/P2C
RE2/CS/P2B
RE3/P3C
8
3
W
8
BITOP
8
8
Power-up
Timer
OSC2/CLKO
OSC1/CLKI
RE4/P3B
Timing
RE5/P1C
Oscillator
Start-up Timer
8
Generation
RE6/P1B
RE7/CCP2(1)/P2A(1)
ALU<8>
Power-on
Reset
PORTF
RF0/AN5
8
Watchdog
Timer
RF1/AN6/C2OUT
RF2/AN7/C1OUT
RF3/AN8
RF4/AN9
RF5/AN10/CVREF
RF6/AN11
Precision
Bandgap
Reference
Brown-out
Reset
Test Mode
Select
RF7/SS
PORTG
MCLR(2)
Timer2
RG0/CCP3/P3A
RG1/TX2/CK2
RG2/RX2/DT2
RG3/CCP4/P3D
RG4/CCP5/P1D
RG5(2)
VDD,VSS
Timer1
Data
EEPROM
BOR
LVD
10-bit
Timer4
Timer0
Timer3
ADC
MSSP
Comparator ECCP1 ECCP2 ECCP3 CCP4 CCP5
EUSART1 EUSART2
Note 1: CCP2/P2A are multiplexed with RC1 when CCP2MX is set, or RE7 when CCP2MX is not set.
2: RG5 is multiplexed with MCLR, and is only available when the MCLR Resets are disabled.
2003 Microchip Technology Inc.
Advance Information
DS39612A-page 9
PIC18F6X2X/8X2X
FIGURE 1-2:
PIC18F8525/8621 BLOCK DIAGRAM
Data Bus<8>
PORTA
PORTB
RA0/AN0
RA1/AN1
RA2/AN2/VREF-
RA3/AN3/VREF+
RA4/T0CKI
RA5/AN4/LVDIN
OSC2/CLKO/RA6
Table Pointer<21>
inc/dec logic
Data Latch
21
8
8
Data RAM
(3.8 Kbytes)
21
Address Latch
12
RB0/INT0
RB1/INT1
20
PCLATU PCLATH
RB2/INT2
Address<12>
RB3/INT3/CCP2(1)/P2A(1)
RB4/KBI0
PCU PCH PCL
Program Counter
4
12
FSR0
4
RB5/KBI1/PGM
RB6/KBI2/PGC
RB7/KBI3/PGD
BSR
Bank0, F
Address Latch
FSR1
FSR2
Program Memory
(48/64 Kbytes)
31 Level Stack
PORTC
12
RC0/T1OSO/T13CKI
RC1/T1OSI/CCP2(1)/P2A(1)
RC2/CCP1/P1A
RC3/SCK/SCL
RC4/SDI/SDA
Data Latch
inc/dec
logic
Decode
Table Latch
8
16
RC5/SDO
ROM Latch
IR
RC6/TX1/CK1
RC7/RX1/DT1
PORTD
PORTE
RD7/PSP7:RD0/PSP0(4)
AD15:AD0, A19:16(4)
8
RE0/RD/P2D(4)
RE1/WR/P2C(4)
RE2/CS/P2B(4)
RE3/P3C(2,4)
PRODH PRODL
8 x 8 Multiply
Instruction
Decode &
Control
RE4/P3B(2,4)
8
3
RE5/P1C(2,4)
RE6/P1B(2,4)
W
8
BITOP
8
8
Power-up
Timer
RE7/CCP2(1)/P2A(1,4)
OSC2/CLKO
OSC1/CLKI
PORTF
RF0/AN5
Timing
Generation
Oscillator
Start-up Timer
8
RF1/AN6/C2OUT
RF2/AN7/C1OUT
RF3/AN8
RF4/AN9
RF5/AN10/CVREF
RF6/AN11
ALU<8>
Power-on
Reset
8
Watchdog
Timer
Precision
Bandgap
Reference
Brown-out
Reset
RF7/SS
PORTG
PORTH
PORTJ
Test Mode
Select
RG0/CCP3/P3A
RG1/TX2/CK2
RG2/RX2/DT2
RG3/CCP4/P3D
RG4/CCP5/P1D
RG5(3)
MCLR(3)
Timer2
VDD,VSS
Timer1
RH0:RH3/AD19(4)
RH4/AN12/P3C(2)
RH5/AN13/P3B(2)
RH6/AN14/P1C(2)
RH7/AN15/P1B(2)
Data
EEPROM
BOR
LVD
10-bit
Timer4
Timer0
Timer3
ADC
RJ0/ALE
RJ1/OE
RJ2/WRL
RJ3/WRH
RJ4/BA0
RJ5/CE
RJ6/LB
MSSP
Comparator ECCP1 ECCP2 ECCP3 CCP4 CCP5
EUSART1 EUSART2
RJ7/UB
Note 1: CCP2/P2A are multiplexed with RC1 when CCP2MX is set; with RE7 when CCP2MX is cleared and the device is configured in
Microcontroller mode; or with RB3 when CCP2MX is cleared in all other Program Memory modes.
2: P1B/P1C/P3B/P3C are multiplexed with RE6:RE3 when ECCPMX is set, and with RH7:RH4 when ECCPMX is not set.
3: RG5 is multiplexed with MCLR, and is only available when the MCLR Resets are disabled.
4: External memory interface pins are multiplexed with PORTD (AD7:AD0), PORTE (AD15:AD8) and PORTH (A19:A16).
DS39612A-page 10
Advance Information
2003 Microchip Technology Inc.
PIC18F6X2X/8X2X
TABLE 1-2:
PIC18F6X2X/8X2X PINOUT I/O DESCRIPTIONS
Pin Number
Pin
Type
Buffer
Type
Pin Name
Description
PIC18F6X2X PIC18F8X2X
MCLR/VPP/RG5
MCLR
7
9
Master Clear (input) or programming
voltage (output).
I
ST
Master Clear (Reset) input. This pin is an
active low RESET to the device.
Programming voltage input.
Digital input.
VPP
RG5
P
I
—
ST
OSC1/CLKI
OSC1
39
49
Oscillator crystal or external clock input.
Oscillator crystal input or external clock
source input. ST buffer when configured
in RC mode; otherwise CMOS.
I
I
CMOS/ST
CMOS
CLKI
External clock source input. Always
associated with pin function OSC1 (see
OSC1/CLKI, OSC2/CLKO pins).
OSC2/CLKO/RA6
OSC2
40
50
Oscillator crystal or clock output.
Oscillator crystal output.
O
O
—
—
Connects to crystal or resonator in
Crystal Oscillator mode.
In RC mode, OSC2 pin outputs CLKO
which has 1/4 the frequency of OSC1
and denotes the instruction cycle rate.
General purpose I/O pin.
CLKO
RA6
I/O
TTL
Legend:
TTL = TTL compatible input
ST = Schmitt Trigger input with CMOS levels
CMOS = CMOS compatible input or output
Analog = Analog input
I
= Input
O
= Output
P
= Power
OD
= Open Drain (no P diode to VDD)
Note 1: Alternate assignment for CCP2/P2A in PIC18F8X2X devices when CCP2MX (CONFIG3H<0>) is not set (all Program
Memory modes except Microcontroller).
2: Default assignment for CCP2/P2A when CCP2MX is set (all devices).
3: External memory interface functions are only available on PIC18F8X2X devices.
4: Default assignment for P1B/P1C/P3B/P3C for PIC18F8X2X devices when ECCPMX (CONFIG3H<1>) is set, and for all
PIC18F6X2X devices.
5: Alternate assignment for CCP2/P2A in PIC18F8X2X devices when CCP2MX is not set (Microcontroller mode).
6: PORTH and PORTJ (and their multiplexed functions) are only available on PIC18F8X2X devices.
7: Alternate assignment for P1B/P1C/P3B/P3C for PIC18F8X2X devices when ECCPMX (CONFIG3H<1>) is not set.
8: AVDD must be connected to a positive supply and AVSS must be connected to a ground reference for proper operation of
the part in User or ICSP modes. See parameter D001A for details.
2003 Microchip Technology Inc.
Advance Information
DS39612A-page 11
PIC18F6X2X/8X2X
TABLE 1-2:
PIC18F6X2X/8X2X PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number
Pin
Type
Buffer
Type
Pin Name
Description
PIC18F6X2X PIC18F8X2X
PORTA is a bi-directional I/O port.
RA0/AN0
RA0
24
23
22
30
29
28
I/O
I
TTL
Analog
Digital I/O.
Analog input 0.
AN0
RA1/AN1
RA1
I/O
I
TTL
Analog
Digital I/O.
Analog input 1.
AN1
RA2/AN2/VREF-
RA2
I/O
TTL
Digital I/O.
AN2
VREF-
I
I
Analog
Analog
Analog input 2.
A/D reference voltage (Low) input.
RA3/AN3/VREF+
RA3
21
28
27
27
34
33
I/O
I
I
TTL
Analog
Analog
Digital I/O.
Analog input 3.
A/D reference voltage (High) input.
AN3
VREF+
RA4/T0CKI
RA4
I/O
I
ST/OD
ST
Digital I/O – Open drain when
configured as output.
Timer0 external clock input.
T0CKI
RA5/AN4/LVDIN
RA5
I/O
TTL
Digital I/O.
AN4
LVDIN
I
I
Analog
Analog
Analog input 4.
Low Voltage Detect input.
RA6
See the OSC2/CLKO/RA6 pin.
Legend:
TTL = TTL compatible input
ST = Schmitt Trigger input with CMOS levels
CMOS = CMOS compatible input or output
Analog = Analog input
I
= Input
O
= Output
P
= Power
OD
= Open Drain (no P diode to VDD)
Note 1: Alternate assignment for CCP2/P2A in PIC18F8X2X devices when CCP2MX (CONFIG3H<0>) is not set (all Program
Memory modes except Microcontroller).
2: Default assignment for CCP2/P2A when CCP2MX is set (all devices).
3: External memory interface functions are only available on PIC18F8X2X devices.
4: Default assignment for P1B/P1C/P3B/P3C for PIC18F8X2X devices when ECCPMX (CONFIG3H<1>) is set, and for all
PIC18F6X2X devices.
5: Alternate assignment for CCP2/P2A in PIC18F8X2X devices when CCP2MX is not set (Microcontroller mode).
6: PORTH and PORTJ (and their multiplexed functions) are only available on PIC18F8X2X devices.
7: Alternate assignment for P1B/P1C/P3B/P3C for PIC18F8X2X devices when ECCPMX (CONFIG3H<1>) is not set.
8: AVDD must be connected to a positive supply and AVSS must be connected to a ground reference for proper operation of
the part in User or ICSP modes. See parameter D001A for details.
DS39612A-page 12
Advance Information
2003 Microchip Technology Inc.
PIC18F6X2X/8X2X
TABLE 1-2:
PIC18F6X2X/8X2X PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number
Pin
Type
Buffer
Type
Pin Name
Description
PIC18F6X2X PIC18F8X2X
PORTB is a bi-directional I/O port. PORTB
can be software programmed for internal
weak pull-ups on all inputs.
RB0/INT0
RB0
48
47
46
45
58
57
56
55
I/O
I
TTL
ST
Digital I/O.
External interrupt 0.
INT0
RB1/INT1
RB1
I/O
I
TTL
ST
Digital I/O.
External interrupt 1.
INT1
RB2/INT2
RB2
I/O
I
TTL
ST
Digital I/O.
External interrupt 2.
INT2
RB3/INT3/CCP2/P2A
RB3
INT3
CCP2
I/O
I/O
I/O
TTL
ST
ST
Digital I/O.
External interrupt 3.
Capture2 input, Compare2 output,
PWM2 output.
(1)
(1)
P2A
O
—
Enhanced CCP2 output P2A.
RB4/KBI0
RB4
44
43
54
53
I/O
I
TTL
ST
Digital I/O.
Interrupt-on-change pin.
KBI0
RB5/KBI1/PGM
RB5
I/O
I
I/O
TTL
ST
ST
Digital I/O.
KBI1
PGM
Interrupt-on-change pin.
Low voltage ICSP programming
enable pin.
RB6/KBI2/PGC
RB6
42
37
52
47
I/O
I
I/O
TTL
ST
ST
Digital I/O.
KBI2
PGC
Interrupt-on-change pin.
In-Circuit Debugger and
ICSP programming clock.
RB7/KBI3/PGD
RB7
I/O
I
I/O
TTL
ST
ST
Digital I/O.
KBI3
PGD
Interrupt-on-change pin.
In-Circuit Debugger and
ICSP programming data.
Legend:
TTL = TTL compatible input
ST = Schmitt Trigger input with CMOS levels
CMOS = CMOS compatible input or output
Analog = Analog input
I
= Input
O
= Output
P
= Power
OD
= Open Drain (no P diode to VDD)
Note 1: Alternate assignment for CCP2/P2A in PIC18F8X2X devices when CCP2MX (CONFIG3H<0>) is not set (all Program
Memory modes except Microcontroller).
2: Default assignment for CCP2/P2A when CCP2MX is set (all devices).
3: External memory interface functions are only available on PIC18F8X2X devices.
4: Default assignment for P1B/P1C/P3B/P3C for PIC18F8X2X devices when ECCPMX (CONFIG3H<1>) is set, and for all
PIC18F6X2X devices.
5: Alternate assignment for CCP2/P2A in PIC18F8X2X devices when CCP2MX is not set (Microcontroller mode).
6: PORTH and PORTJ (and their multiplexed functions) are only available on PIC18F8X2X devices.
7: Alternate assignment for P1B/P1C/P3B/P3C for PIC18F8X2X devices when ECCPMX (CONFIG3H<1>) is not set.
8: AVDD must be connected to a positive supply and AVSS must be connected to a ground reference for proper operation of
the part in User or ICSP modes. See parameter D001A for details.
2003 Microchip Technology Inc.
Advance Information
DS39612A-page 13
PIC18F6X2X/8X2X
TABLE 1-2:
PIC18F6X2X/8X2X PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number
Pin
Type
Buffer
Type
Pin Name
Description
PIC18F6X2X PIC18F8X2X
PORTC is a bi-directional I/O port.
RC0/T1OSO/T13CKI
RC0
30
29
36
35
I/O
O
I
ST
—
ST
Digital I/O.
Timer1 oscillator output.
Timer1/Timer3 external clock input.
T1OSO
T13CKI
RC1/T1OSI/CCP2/P2A
RC1
T1OSI
CCP2
I/O
I
I/O
ST
CMOS
ST
Digital I/O.
Timer1 oscillator input.
Capture2 input, Compare2 output,
PWM2 output.
(2)
(2)
P2A
O
—
Enhanced CCP2 output P2A.
RC2/CCP1/P1A
RC2
33
34
43
44
I/O
I/O
ST
ST
Digital I/O.
Capture1 input, Compare1 output,
PWM1 output.
CCP1
P1A
O
—
Enhanced CCP1 output P1A.
RC3/SCK/SCL
RC3
I/O
I/O
ST
ST
Digital I/O.
Synchronous serial clock input/output for
SPI mode.
SCK
SCL
I/O
ST
Synchronous serial clock input/output for
I C mode.
2
RC4/SDI/SDA
RC4
35
45
I/O
I
I/O
ST
ST
ST
Digital I/O.
SDI
SDA
SPI data in.
2
I C data I/O.
RC5/SDO
RC5
36
31
46
37
I/O
O
ST
—
Digital I/O.
SPI data out.
SDO
RC6/TX1/CK1
RC6
I/O
O
I/O
ST
—
ST
Digital I/O.
TX1
CK1
USART 1 asynchronous transmit.
USART 1 synchronous clock
(see RX1/DT1).
RC7/RX1/DT1
RC7
32
38
I/O
I
I/O
ST
ST
ST
Digital I/O.
RX1
DT1
USART 1 asynchronous receive.
USART 1 synchronous data
(see TX1/CK1).
Legend:
TTL = TTL compatible input
ST = Schmitt Trigger input with CMOS levels
CMOS = CMOS compatible input or output
Analog = Analog input
I
= Input
O
= Output
P
= Power
OD
= Open Drain (no P diode to VDD)
Note 1: Alternate assignment for CCP2/P2A in PIC18F8X2X devices when CCP2MX (CONFIG3H<0>) is not set (all Program
Memory modes except Microcontroller).
2: Default assignment for CCP2/P2A when CCP2MX is set (all devices).
3: External memory interface functions are only available on PIC18F8X2X devices.
4: Default assignment for P1B/P1C/P3B/P3C for PIC18F8X2X devices when ECCPMX (CONFIG3H<1>) is set, and for all
PIC18F6X2X devices.
5: Alternate assignment for CCP2/P2A in PIC18F8X2X devices when CCP2MX is not set (Microcontroller mode).
6: PORTH and PORTJ (and their multiplexed functions) are only available on PIC18F8X2X devices.
7: Alternate assignment for P1B/P1C/P3B/P3C for PIC18F8X2X devices when ECCPMX (CONFIG3H<1>) is not set.
8: AVDD must be connected to a positive supply and AVSS must be connected to a ground reference for proper operation of
the part in User or ICSP modes. See parameter D001A for details.
DS39612A-page 14
Advance Information
2003 Microchip Technology Inc.
PIC18F6X2X/8X2X
TABLE 1-2:
PIC18F6X2X/8X2X PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number
Pin
Type
Buffer
Type
Pin Name
Description
PIC18F6X2X PIC18F8X2X
PORTD is a bi-directional I/O port. These
pins have TTL input buffers when external
memory is enabled.
RD0/AD0/PSP0
RD0
58
55
54
53
52
51
50
49
72
69
68
67
66
65
64
63
I/O
I/O
I/O
ST
TTL
TTL
Digital I/O.
External memory address/data 0.
Parallel slave port data.
(3)
AD0
PSP0
RD1/AD1/PSP1
RD1
I/O
I/O
I/O
ST
TTL
TTL
Digital I/O.
External memory address/data 1.
Parallel slave port data.
(3)
AD1
PSP1
RD2/AD2/PSP2
RD2
I/O
I/O
I/O
ST
TTL
TTL
Digital I/O.
External memory address/data 2.
Parallel slave port data.
(3)
AD2
PSP2
RD3/AD3/PSP3
RD3
I/O
I/O
I/O
ST
TTL
TTL
Digital I/O.
External memory address/data 3.
Parallel slave port data.
(3)
AD3
PSP3
RD4/AD4/PSP4
RD4
I/O
I/O
I/O
ST
TTL
TTL
Digital I/O.
External memory address/data 4.
Parallel slave port data.
(3)
AD4
PSP4
RD5/AD5/PSP5
RD5
I/O
I/O
I/O
ST
TTL
TTL
Digital I/O.
External memory address/data 5.
Parallel Slave Port data.
(3)
AD5
PSP5
RD6/AD6/PSP6
RD6
I/O
I/O
I/O
ST
TTL
TTL
Digital I/O.
External memory address/data 6.
Parallel slave port data.
(3)
AD6
PSP6
RD7/AD7/PSP7
RD7
I/O
I/O
I/O
ST
TTL
TTL
Digital I/O.
External memory address/data 7.
Parallel slave port data.
(3)
AD7
PSP7
Legend:
TTL = TTL compatible input
ST = Schmitt Trigger input with CMOS levels
CMOS = CMOS compatible input or output
Analog = Analog input
I
= Input
O
= Output
P
= Power
OD
= Open Drain (no P diode to VDD)
Note 1: Alternate assignment for CCP2/P2A in PIC18F8X2X devices when CCP2MX (CONFIG3H<0>) is not set (all Program
Memory modes except Microcontroller).
2: Default assignment for CCP2/P2A when CCP2MX is set (all devices).
3: External memory interface functions are only available on PIC18F8X2X devices.
4: Default assignment for P1B/P1C/P3B/P3C for PIC18F8X2X devices when ECCPMX (CONFIG3H<1>) is set, and for all
PIC18F6X2X devices.
5: Alternate assignment for CCP2/P2A in PIC18F8X2X devices when CCP2MX is not set (Microcontroller mode).
6: PORTH and PORTJ (and their multiplexed functions) are only available on PIC18F8X2X devices.
7: Alternate assignment for P1B/P1C/P3B/P3C for PIC18F8X2X devices when ECCPMX (CONFIG3H<1>) is not set.
8: AVDD must be connected to a positive supply and AVSS must be connected to a ground reference for proper operation of
the part in User or ICSP modes. See parameter D001A for details.
2003 Microchip Technology Inc.
Advance Information
DS39612A-page 15
PIC18F6X2X/8X2X
TABLE 1-2:
PIC18F6X2X/8X2X PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number
Pin
Type
Buffer
Type
Pin Name
Description
PIC18F6X2X PIC18F8X2X
PORTE is a bi-directional I/O port.
RE0/AD8/RD/P2D
RE0
2
1
4
I/O
I/O
I
ST
TTL
TTL
—
Digital I/O.
(3)
AD8
RD
P2D
External memory address/data 8.
Read control for parallel slave port.
Enhanced CCP2 output P2D.
O
RE1/AD9/WR/P2C
RE1
3
I/O
I/O
I
ST
TTL
TTL
ST
Digital I/O.
(3)
AD9
External memory address/data 9.
Write control for parallel slave port.
Enhanced CCP2 output P2C.
WR
P2C
O
RE2/AD10/CS/P2B
RE2
64
78
I/O
I/O
I
ST
TTL
TTL
—
Digital I/O.
(3)
AD10
CS
P2B
External memory address/data 10.
Chip select control for parallel slave port.
Enhanced CCP2 output P2B.
O
RE3/AD11/P3C
RE3
63
62
61
60
59
77
76
75
74
73
I/O
I/O
O
ST
TTL
—
Digital I/O.
External memory address/data 11.
Enhanced CCP3 output P3C.
(3)
AD11
(4)
P3C
RE4/AD12/P3B
RE4
I/O
I/O
O
ST
TTL
—
Digital I/O.
External memory address/data 12.
Enhanced CCP3 output P3B.
(3)
AD12
P3B
(4)
RE5/AD13/P1C
RE5
I/O
I/O
O
ST
TTL
—
Digital I/O.
External memory address/data 13.
Enhanced CCP1 output P1C.
(3)
AD13
P1C
(4)
RE6/AD14/P1B
RE6
I/O
I/O
O
ST
TTL
—
Digital I/O.
External memory address/data 14.
Enhanced CCP1 output P1B.
(3)
AD14
P1B
(4)
RE7/AD15/CCP2/P2A
RE7
I/O
I/O
I/O
ST
TTL
ST
Digital I/O.
(3)
AD15
External memory address/data 15.
Capture2 input, Compare2 output,
PWM2 output.
(5)
CCP2
(5)
P2A
O
—
Enhanced CCP2 output P2A.
Legend:
TTL = TTL compatible input
ST = Schmitt Trigger input with CMOS levels
CMOS = CMOS compatible input or output
Analog = Analog input
I
= Input
O
= Output
P
= Power
OD
= Open Drain (no P diode to VDD)
Note 1: Alternate assignment for CCP2/P2A in PIC18F8X2X devices when CCP2MX (CONFIG3H<0>) is not set (all Program
Memory modes except Microcontroller).
2: Default assignment for CCP2/P2A when CCP2MX is set (all devices).
3: External memory interface functions are only available on PIC18F8X2X devices.
4: Default assignment for P1B/P1C/P3B/P3C for PIC18F8X2X devices when ECCPMX (CONFIG3H<1>) is set, and for all
PIC18F6X2X devices.
5: Alternate assignment for CCP2/P2A in PIC18F8X2X devices when CCP2MX is not set (Microcontroller mode).
6: PORTH and PORTJ (and their multiplexed functions) are only available on PIC18F8X2X devices.
7: Alternate assignment for P1B/P1C/P3B/P3C for PIC18F8X2X devices when ECCPMX (CONFIG3H<1>) is not set.
8: AVDD must be connected to a positive supply and AVSS must be connected to a ground reference for proper operation of
the part in User or ICSP modes. See parameter D001A for details.
DS39612A-page 16
Advance Information
2003 Microchip Technology Inc.
PIC18F6X2X/8X2X
TABLE 1-2:
PIC18F6X2X/8X2X PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number
Pin
Type
Buffer
Type
Pin Name
Description
PIC18F6X2X PIC18F8X2X
PORTF is a bi-directional I/O port.
RF0/AN5
RF0
18
17
24
23
I/O
I
ST
Analog
Digital I/O.
Analog input 5.
AN5
RF1/AN6/C2OUT
RF1
I/O
I
O
ST
Analog
ST
Digital I/O.
Analog input 6.
Comparator 2 output.
AN6
C2OUT
RF2/AN7/C1OUT
RF2
16
18
I/O
I
O
ST
Analog
ST
Digital I/O.
Analog input 7.
Comparator 1 output.
AN7
C1OUT
RF3/AN8
RF1
15
14
13
17
16
15
I/O
I
ST
Analog
Digital I/O.
Analog input 8.
AN8
RF4/AN9
RF1
I/O
I
ST
Analog
Digital I/O.
Analog input 9.
AN9
RF5/AN10/CVREF
RF1
I/O
I
O
ST
Analog
Analog
Digital I/O.
Analog input 10.
Comparator VREF output.
AN10
CVREF
RF6/AN11
RF6
12
11
14
13
I/O
I
ST
Analog
Digital I/O.
Analog input 11.
AN11
RF7/SS
RF7
I/O
I
ST
TTL
Digital I/O.
SPI slave select input.
SS
Legend:
TTL = TTL compatible input
ST = Schmitt Trigger input with CMOS levels
CMOS = CMOS compatible input or output
Analog = Analog input
I
= Input
O
= Output
P
= Power
OD
= Open Drain (no P diode to VDD)
Note 1: Alternate assignment for CCP2/P2A in PIC18F8X2X devices when CCP2MX (CONFIG3H<0>) is not set (all Program
Memory modes except Microcontroller).
2: Default assignment for CCP2/P2A when CCP2MX is set (all devices).
3: External memory interface functions are only available on PIC18F8X2X devices.
4: Default assignment for P1B/P1C/P3B/P3C for PIC18F8X2X devices when ECCPMX (CONFIG3H<1>) is set, and for all
PIC18F6X2X devices.
5: Alternate assignment for CCP2/P2A in PIC18F8X2X devices when CCP2MX is not set (Microcontroller mode).
6: PORTH and PORTJ (and their multiplexed functions) are only available on PIC18F8X2X devices.
7: Alternate assignment for P1B/P1C/P3B/P3C for PIC18F8X2X devices when ECCPMX (CONFIG3H<1>) is not set.
8: AVDD must be connected to a positive supply and AVSS must be connected to a ground reference for proper operation of
the part in User or ICSP modes. See parameter D001A for details.
2003 Microchip Technology Inc.
Advance Information
DS39612A-page 17
PIC18F6X2X/8X2X
TABLE 1-2:
PIC18F6X2X/8X2X PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number
Pin
Type
Buffer
Type
Pin Name
Description
PIC18F6X2X PIC18F8X2X
PORTG is a bi-directional I/O port.
RG0/CCP3/P3A
RG0
3
4
5
6
8
7
5
I/O
I/O
ST
ST
Digital I/O.
Capture3 input, Compare3 output,
PWM3 output.
CCP3
P3A
O
—
Enhanced CCP3 output P3A.
RG1/TX2/CK2
RG1
6
I/O
O
I/O
ST
—
ST
Digital I/O.
TX2
CK2
USART 2 asynchronous transmit.
USART 2 synchronous clock
(see RX2/DT2).
RG2/RX2/DT2
RG2
7
I/O
I
I/O
ST
ST
ST
Digital I/O.
RX2
DT2
USART 2 asynchronous receive.
USART 2 synchronous data
(see TX2/CK2).
RG3/CCP4/P3D
RG3
8
I/O
I/O
ST
ST
Digital I/O.
Capture4 input, Compare4 output,
PWM4 output.
CCP4
P3D
O
—
Enhanced CCP3 output P3D.
RG4/CCP5/P1D
RG4
10
9
I/O
I/O
ST
ST
Digital I/O.
Capture5 input, Compare5 output,
PWM5 output.
CCP5
P1D
RG5
O
—
—
Enhanced CCP1 output P1D.
—
See MCLR/VPP/RG5 pin.
Legend:
TTL = TTL compatible input
ST = Schmitt Trigger input with CMOS levels
CMOS = CMOS compatible input or output
Analog = Analog input
I
= Input
O
= Output
P
= Power
OD
= Open Drain (no P diode to VDD)
Note 1: Alternate assignment for CCP2/P2A in PIC18F8X2X devices when CCP2MX (CONFIG3H<0>) is not set (all Program
Memory modes except Microcontroller).
2: Default assignment for CCP2/P2A when CCP2MX is set (all devices).
3: External memory interface functions are only available on PIC18F8X2X devices.
4: Default assignment for P1B/P1C/P3B/P3C for PIC18F8X2X devices when ECCPMX (CONFIG3H<1>) is set, and for all
PIC18F6X2X devices.
5: Alternate assignment for CCP2/P2A in PIC18F8X2X devices when CCP2MX is not set (Microcontroller mode).
6: PORTH and PORTJ (and their multiplexed functions) are only available on PIC18F8X2X devices.
7: Alternate assignment for P1B/P1C/P3B/P3C for PIC18F8X2X devices when ECCPMX (CONFIG3H<1>) is not set.
8: AVDD must be connected to a positive supply and AVSS must be connected to a ground reference for proper operation of
the part in User or ICSP modes. See parameter D001A for details.
DS39612A-page 18
Advance Information
2003 Microchip Technology Inc.
PIC18F6X2X/8X2X
TABLE 1-2:
PIC18F6X2X/8X2X PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number
Pin
Type
Buffer
Type
Pin Name
Description
PIC18F6X2X PIC18F8X2X
(6)
PORTH is a bi-directional I/O port
.
RH0/A16
RH0
—
—
—
—
—
79
80
1
I/O
O
ST
TTL
Digital I/O.
External memory address 16.
A16
RH1/A17
RH1
I/O
O
ST
TTL
Digital I/O.
External memory address 17.
A17
RH2/A18
RH2
I/O
O
ST
TTL
Digital I/O.
External memory address 18.
A18
RH3/A19
RH3
2
I/O
O
ST
TTL
Digital I/O.
External memory address 19.
A19
RH4/AN12/P3C
RH4
22
I/O
I
O
ST
Analog
—
Digital I/O.
Analog input 12.
Enhanced CCP3 output P3C.
AN12
(7)
P3C
RH5/AN13/P3B
RH5
—
—
—
21
20
19
I/O
I
O
ST
Analog
—
Digital I/O.
Analog input 13.
Enhanced CCP3 output P3B.
AN13
(7)
P3B
RH6/AN14/P1C
RH6
I/O
I
O
ST
Analog
—
Digital I/O.
Analog input 14.
Enhanced CCP1 output P1C.
AN14
(7)
P1C
RH7/AN15/P1B
RH7
I/O
I
O
ST
Analog
—
Digital I/O.
Analog input 15.
Enhanced CCP1 output P1B.
AN15
(7)
P1B
Legend:
TTL = TTL compatible input
ST = Schmitt Trigger input with CMOS levels
CMOS = CMOS compatible input or output
Analog = Analog input
I
= Input
O
= Output
P
= Power
OD
= Open Drain (no P diode to VDD)
Note 1: Alternate assignment for CCP2/P2A in PIC18F8X2X devices when CCP2MX (CONFIG3H<0>) is not set (all Program
Memory modes except Microcontroller).
2: Default assignment for CCP2/P2A when CCP2MX is set (all devices).
3: External memory interface functions are only available on PIC18F8X2X devices.
4: Default assignment for P1B/P1C/P3B/P3C for PIC18F8X2X devices when ECCPMX (CONFIG3H<1>) is set, and for all
PIC18F6X2X devices.
5: Alternate assignment for CCP2/P2A in PIC18F8X2X devices when CCP2MX is not set (Microcontroller mode).
6: PORTH and PORTJ (and their multiplexed functions) are only available on PIC18F8X2X devices.
7: Alternate assignment for P1B/P1C/P3B/P3C for PIC18F8X2X devices when ECCPMX (CONFIG3H<1>) is not set.
8: AVDD must be connected to a positive supply and AVSS must be connected to a ground reference for proper operation of
the part in User or ICSP modes. See parameter D001A for details.
2003 Microchip Technology Inc.
Advance Information
DS39612A-page 19
PIC18F6X2X/8X2X
TABLE 1-2:
PIC18F6X2X/8X2X PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number
Pin
Type
Buffer
Type
Pin Name
Description
PIC18F6X2X PIC18F8X2X
(6)
PORTJ is a bi-directional I/O port
Digital I/O.
.
RJ0/ALE
RJ0
—
—
—
—
—
—
—
—
62
61
60
59
39
40
41
42
I/O
O
ST
TTL
ALE
External memory address latch enable.
RJ1/OE
RJ1
I/O
O
ST
TTL
Digital I/O.
External memory output enable.
OE
RJ2/WRL
RJ2
I/O
O
ST
TTL
Digital I/O.
External memory write low control.
WRL
RJ3/WRH
RJ3
I/O
O
ST
TTL
Digital I/O.
External memory write high control.
WRH
RJ4/BA0
RJ4
I/O
O
ST
TTL
Digital I/O.
System bus byte address 0 control.
BA0
RJ5/CE
RJ5
I/O
O
ST
TTL
Digital I/O
External memory access indicator.
CE
RJ6/LB
RJ6
I/O
O
ST
TTL
Digital I/O.
External memory low byte select.
LB
RJ7/UB
RJ7
I/O
O
ST
TTL
Digital I/O.
External memory high byte select.
UB
VSS
VDD
9, 25,
41, 56
11, 31,
51, 70
P
—
Ground reference for logic and I/O pins.
10, 26,
38, 57
12, 32,
48, 71
P
—
Positive supply for logic and I/O pins.
(8)
AVSS
20
19
26
25
P
P
—
—
Ground reference for analog modules.
Positive supply for analog modules.
(8)
AVDD
Legend:
TTL = TTL compatible input
ST = Schmitt Trigger input with CMOS levels
CMOS = CMOS compatible input or output
Analog = Analog input
I
= Input
O
= Output
P
= Power
OD
= Open Drain (no P diode to VDD)
Note 1: Alternate assignment for CCP2/P2A in PIC18F8X2X devices when CCP2MX (CONFIG3H<0>) is not set (all Program
Memory modes except Microcontroller).
2: Default assignment for CCP2/P2A when CCP2MX is set (all devices).
3: External memory interface functions are only available on PIC18F8X2X devices.
4: Default assignment for P1B/P1C/P3B/P3C for PIC18F8X2X devices when ECCPMX (CONFIG3H<1>) is set, and for all
PIC18F6X2X devices.
5: Alternate assignment for CCP2/P2A in PIC18F8X2X devices when CCP2MX is not set (Microcontroller mode).
6: PORTH and PORTJ (and their multiplexed functions) are only available on PIC18F8X2X devices.
7: Alternate assignment for P1B/P1C/P3B/P3C for PIC18F8X2X devices when ECCPMX (CONFIG3H<1>) is not set.
8: AVDD must be connected to a positive supply and AVSS must be connected to a ground reference for proper operation of
the part in User or ICSP modes. See parameter D001A for details.
DS39612A-page 20
Advance Information
2003 Microchip Technology Inc.
PIC18F6X2X/8X2X
FIGURE 2-1:
CRYSTAL/CERAMIC
RESONATOR OPERATION
(HS, XT OR LP
2.0
2.1
OSCILLATOR
CONFIGURATIONS
CONFIGURATION)
Oscillator Types
(1)
C1
C2
OSC1
The PIC18F6X2X/8X2X devices can be operated in
twelve different Oscillator modes. The user can pro-
gram four configuration bits (FOSC3, FOSC2, FOSC1,
and FOSC0) to select one of these eight modes:
To
Internal
Logic
(3)
RF
XTAL
1. LP
2. XT
3. HS
4. RC
5. EC
6. ECIO
Low Power Crystal
SLEEP
(2)
RS
Crystal/Resonator
(1)
PIC18F6X2X/8X2X
OSC2
High Speed Crystal/Resonator
External Resistor/Capacitor
External Clock
Note 1: See Table 2-1 and Table 2-2 for
recommended values of C1 and C2.
2: A series resistor (RS) may be required for
AT strip cut crystals.
External Clock with I/O pin
enabled
7. HS+PLL
8. RCIO
High Speed Crystal/Resonator
with PLL enabled
3: RF varies with the Oscillator mode chosen.
External Resistor/Capacitor with
I/O pin enabled
TABLE 2-1:
CAPACITOR SELECTION FOR
CERAMIC RESONATORS
9. ECIO+SPLL External Clock with software
controlled PLL
Ranges Tested:
10. ECIO+PLL External Clock with PLL and I/O
pin enabled
Mode
Freq
C1
C2
11. HS+SPLL
High Speed Crystal/Resonator
with software control
XT
455 kHz
2.0 MHz
4.0 MHz
68 - 100 pF 68 - 100 pF
15 - 68 pF
15 - 68 pF
15 - 68 pF
15 - 68 pF
12. RCIO
External Resistor/Capacitor with
I/O pin enabled
HS
8.0 MHz
16.0 MHz
10 - 68 pF
10 - 22 pF
10 - 68 pF
10 - 22 pF
2.2
Crystal Oscillator/Ceramic
Resonators
These values are for design guidance only.
See notes following this table.
In XT, LP, HS, HS+PLL or HS+SPLL Oscillator modes, a
crystal or ceramic resonator is connected to the OSC1
and OSC2 pins to establish oscillation. Figure 2-1 shows
the pin connections.
Resonators Used:
2.0 MHz Murata Erie CSA2.00MG
4.0 MHz Murata Erie CSA4.00MG
8.0 MHz Murata Erie CSA8.00MT
16.0 MHz Murata Erie CSA16.00MX
0.5%
0.5%
0.5%
0.5%
The PIC18F6X2X/8X2X oscillator design requires the
use of a parallel cut crystal.
All resonators used did not have built-in capacitors.
Note:
Use of a series cut crystal may give a fre-
quency out of the crystal manufacturers
specifications.
Note 1: Higher capacitance increases the stability
of the oscillator but also increases the
start-up time.
2: When operating below 3V VDD, or when
using certain ceramic resonators at any
voltage, it may be necessary to use high
gain HS mode, try a lower frequency
resonator, or switch to a crystal oscillator.
3: Since each resonator/crystal has its own
characteristics, the user should consult the
resonator/crystal manufacturer for appro-
priate values of external components, or
verify oscillator performance.
2003 Microchip Technology Inc.
Advance Information
DS39612A-page 21
PIC18F6X2X/8X2X
TABLE 2-2:
CAPACITOR SELECTION FOR
CRYSTAL OSCILLATOR
FIGURE 2-2:
EXTERNAL CLOCK INPUT
OPERATION (HS, XT OR LP
OSC CONFIGURATION)
Ranges Tested:
Mode
Freq
C1
C2
OSC1
Clock from
Ext. System
LP
32.0 kHz
200 kHz
200 kHz
1.0 MHz
4.0 MHz
4.0 MHz
8.0 MHz
20.0 MHz
25.0 MHz
33 pF
15 pF
33 pF
15 pF
PIC18F6X2X/8X2X
OSC2
Open
XT
HS
47-68 pF
15 pF
47-68 pF
15 pF
15 pF
15 pF
2.3
RC Oscillator
15 pF
15 pF
For timing insensitive applications, the “RC” and
“RCIO” device options offer additional cost savings.
The RC oscillator frequency is a function of the supply
voltage, the resistor (REXT) and capacitor (CEXT) val-
ues and the operating temperature. In addition to this,
the oscillator frequency will vary from unit to unit due to
normal process parameter variation. Furthermore, the
difference in lead frame capacitance between package
types will also affect the oscillation frequency, espe-
cially for low CEXT values. The user also needs to take
into account variation due to tolerance of external R
and C components used. Figure 2-3 shows how the
R/C combination is connected.
15-33 pF
15-33 pF
TBD
15-33 pF
15-33 pF
TBD
These values are for design guidance only.
See notes following this table.
Crystals Used
32.0 kHz
200 kHz
1.0 MHz
4.0 MHz
8.0 MHz
Epson C-001R32.768K-A ± 20 PPM
STD XTL 200.000KHz
ECS ECS-10-13-1
ECS ECS-40-20-1
± 20 PPM
± 50 PPM
± 50 PPM
In the RC Oscillator mode, the oscillator frequency
divided by 4 is available on the OSC2 pin. This signal
may be used for test purposes or to synchronize other
logic.
Epson CA-301 8.000M-C ± 30 PPM
20.0 MHz Epson CA-301 20.000M-C ± 30 PPM
Note 1: Higher capacitance increases the stability
of the oscillator but also increases the
start-up time.
FIGURE 2-3:
RC OSCILLATOR MODE
VDD
2: Rs (see Figure 2-1) may be required in
HS mode, as well as XT mode, to avoid
overdriving crystals with low drive level
specification.
REXT
Internal
OSC1
Clock
CEXT
VSS
3: Since each resonator/crystal has its own
characteristics, the user should consult the
resonator/crystal manufacturer for appro-
priate values of external components, or
verify oscillator performance.
PIC18F6X2X/8X2X
OSC2/CLKO
FOSC/4
Recommended values: 3 kΩ ≤ REXT ≤ 100 kΩ
CEXT > 20pF
An external clock source may also be connected to the
OSC1 pin in the HS, XT and LP modes as shown in
Figure 2-2.
The RCIO Oscillator mode functions like the RC mode
except that the OSC2 pin becomes an additional gen-
eral purpose I/O pin. The I/O pin becomes bit 6 of
PORTA (RA6).
DS39612A-page 22
Advance Information
2003 Microchip Technology Inc.
PIC18F6X2X/8X2X
2.4
External Clock Input
2.5
Phase Locked Loop (PLL)
The EC, ECIO, EC+PLL and EC+SPLL Oscillator
modes require an external clock source to be con-
nected to the OSC1 pin. The feedback device between
OSC1 and OSC2 is turned off in these modes to save
current. There is a maximum 1.5 µs start-up required
after a Power-on Reset or Wake-up from SLEEP mode.
A phase locked loop circuit is provided as a
programmable option for users that want to multiply the
frequency of the incoming oscillator signal by 4. For an
input clock frequency of 10 MHz, the internal clock
frequency will be multiplied to 40 MHz. This is useful for
customers who are concerned with EMI due to high
frequency crystals.
In the EC Oscillator mode, the oscillator frequency
divided by 4 is available on the OSC2 pin. This signal
may be used for test purposes or to synchronize other
logic. Figure 2-4 shows the pin connections for the EC
Oscillator mode.
The PLL can only be enabled when the oscillator con-
figuration bits are programmed for High Speed Oscilla-
tor or External Clock mode. If they are programmed for
any other mode, the PLL is not enabled and the system
clock will come directly from OSC1. There are two
types of PLL modes - Software Controlled PLL and
Configuration bits Controlled PLL. In Software Con-
trolled PLL mode, PIC18F6X2X/8X2X executes at reg-
ular clock frequency after all RESET conditions. During
execution, the application can enable PLL and switch
to 4x clock frequency operation by setting the PLLEN
bit in the OSCCON register. In Configuration bits Con-
trolled PLL, the PLL operation cannot be changed “on-
the-fly”. To enable or disable it, the controller must
either cycle through a Power-on Reset, or switch the
clock source from the main oscillator to the Timer1
oscillator and back again (see Section 2.6 for details on
oscillator switching).
FIGURE 2-4:
EXTERNAL CLOCK INPUT
OPERATION
(EC CONFIGURATION)
OSC1
Clock from
Ext. System
PIC18F6X2X/8X2X
OSC2
FOSC/4
The ECIO Oscillator mode functions like the EC mode
except that the OSC2 pin becomes an additional gen-
eral purpose I/O pin. The I/O pin becomes bit 6 of
PORTA (RA6). Figure 2-5 shows the pin connections
for the ECIO Oscillator mode.
The type of PLL is selected by programming
FOSC<3:0> configuration bits in CONFIG1H Configura-
tion register. The Oscillator mode is specified during
device programming.
FIGURE 2-5:
EXTERNAL CLOCK INPUT
OPERATION
A PLL lock timer is used to ensure that the PLL has
locked before device execution starts. The PLL lock
timer has a time-out that is called TPLL.
(ECIOCONFIGURATION)
OSC1
Clock from
Ext. System
PIC18F6X2X/8X2X
I/O (OSC2)
RA6
FIGURE 2-6:
PLL BLOCK DIAGRAM
PLL Enable
Phase
Comparator
FIN
Loop
Filter
VCO
SYSCLK
FOUT
Divide by 4
2003 Microchip Technology Inc.
Advance Information
DS39612A-page 23
PIC18F6X2X/8X2X
Low Power Execution mode. Figure 2-7 shows a block
diagram of the system clock sources. The clock
switching feature is enabled by programming the
Oscillator Switching Enable (OSCSEN) bit in the
CONFIG1H Configuration register to a ‘0’. Clock
switching is disabled in an erased device. See
Section 12.0 for further details of the Timer1 oscillator.
See Section 24.0 for Configuration register details.
2.6
Oscillator Switching Feature
The PIC18F6X2X/8X2X devices include a feature that
allows the system clock source to be switched from the
main oscillator to an alternate low frequency clock
source. For the PIC18F6X2X/8X2X devices, this
alternate clock source is the Timer1 oscillator. If a low
frequency crystal (32 kHz, for example) has been
attached to the Timer1 oscillator pins and the Timer1
oscillator has been enabled, the device can switch to a
FIGURE 2-7:
DEVICE CLOCK SOURCES
PIC18F6X2X/8X2X
Main Oscillator
OSC2
TOSC/4
4 x PLL
SLEEP
TOSC
TT1P
TSCLK
OSC1
Timer1 Oscillator
T1OSO
T1OSCEN
Enable
Oscillator
Clock
Source
T1OSI
Clock Source Option
for Other Modules
DS39612A-page 24
Advance Information
2003 Microchip Technology Inc.
PIC18F6X2X/8X2X
2.6.1
SYSTEM CLOCK SWITCH BIT
Note:
The Timer1 oscillator must be enabled
and operating to switch the system clock
source. The Timer1 oscillator is enabled
by setting the T1OSCEN bit in the Timer1
Control register (T1CON). If the Timer1
oscillator is not enabled, then any write to
the SCS0 bit will be ignored (SCS0 bit
forced cleared) and the main oscillator will
continue to be the system clock source.
The system clock source switching is performed under
software control. The system clock switch bits,
SCS1:SCS0 (OSCCON<1:0>), control the clock
switching. When the SCS0 bit is ‘0’, the system clock
source comes from the main oscillator that is selected
by the FOSC configuration bits in CONFIG1H Configu-
ration register. When the SCS0 bit is set, the system
clock source will come from the Timer1 oscillator. The
SCS0 bit is cleared on all forms of RESET.
When FOSC bits are programmed for Software PLL
mode, SCS1 bit can be used to select between primary
oscillator/clock and PLL output. SCS1 bit will only have
an effect on the system clock if the PLL is enabled
(PLLEN = 1) and locked (LOCK = 1), else it will be
forced cleared. When programmed with Configuration
Controlled PLL, SCS1 bit will be forced clear.
REGISTER 2-1:
OSCCON REGISTER
U-0
—
U-0
—
U-0
—
U-0
—
R/W-0
LOCK
R/W-0
R/W-0
SCS1
R/W-0
SCS0
PLLEN
bit 7
bit 0
bit 7-4 Unimplemented: Read as ‘0’
bit 3
bit 2
bit 1
LOCK: Phase Lock Loop Lock Status bit
1= Phase lock loop output is stable as system clock
0= Phase lock loop output is not stable and output cannot be used as system clock
PLLEN(1): Phase Lock Loop Enable bit
1= Enable phase lock loop output as system clock
0= Disable phase lock loop
SCS1: System Clock Switch bit 1
When PLLEN and LOCK bits are set:
1= Use PLL output
0= Use primary oscillator/clock input pin
When PLLEN or LOCK bit is cleared:
Bit is forced clear.
bit 0
SCS0(2): System Clock Switch bit 0
When OSCSEN configuration bit = 0and T1OSCEN bit = 1:
1= Switch to Timer1 oscillator/clock pin
0= Use primary oscillator/clock input pin
When OSCSEN and T1OSCEN are in other states:
Bit is forced clear.
Note 1: PLLEN bit is forced set when configured for ECIO+PLL and HS+PLL. This bit is
writable for ECIO+SPLL and HS+SPLL modes only; forced cleared for all other
Oscillator modes.
2: The setting of SCS0 = 1supersedes SCS1 = 1.
Legend:
R = Readable bit
- n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
2003 Microchip Technology Inc.
Advance Information
DS39612A-page 25
PIC18F6X2X/8X2X
A timing diagram indicating the transition from the main
oscillator to the Timer1 oscillator is shown in Figure 2-8.
The Timer1 oscillator is assumed to be running all the
time. After the SCS0 bit is set, the processor is frozen at
the next occurring Q1 cycle. After eight synchronization
cycles are counted from the Timer1 oscillator, operation
resumes. No additional delays are required after the
synchronization cycles.
2.6.2
OSCILLATOR TRANSITIONS
PIC18F6X2X/8X2X devices contain circuitry to prevent
“glitches” when switching between oscillator sources.
Essentially, the circuitry waits for eight rising edges of
the clock source that the processor is switching to. This
ensures that the new clock source is stable and that its
pulse width will not be less than the shortest pulse
width of the two clock sources.
FIGURE 2-8:
TIMING DIAGRAM FOR TRANSITION FROM OSC1 TO TIMER1 OSCILLATOR
Q1 Q2 Q3 Q4 Q1
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Q1
TT1P
2
1
3
4
5
6
7
8
T1OSI
OSC1
TSCS
TOSC
Internal
System
Clock
TDLY
SCS
(OSCCON<0>)
Program
Counter
PC
PC + 2
PC + 4
Note:
TDLY is delay from SCS high to first count of transition circuit.
The sequence of events that takes place when switch-
ing from the Timer1 oscillator to the main oscillator will
depend on the mode of the main oscillator. In addition
to eight clock cycles of the main oscillator, additional
delays may take place.
If the main oscillator is configured for an external crys-
tal (HS, XT, LP), then the transition will take place after
an oscillator start-up time (TOST) has occurred. A timing
diagram, indicating the transition from the Timer1 oscil-
lator to the main oscillator for HS, XT and LP modes, is
shown in Figure 2-9.
FIGURE 2-9:
TIMING FOR TRANSITION BETWEEN TIMER1 AND OSC1 (HS, XT, LP)
Q1 Q2 Q3 Q4 Q1 Q2 Q3
Q3
Q4
Q1
TT1P
T1OSI
OSC1
1
2
3
4
5
6
7
8
TOST
TSCS
TOSC
Internal
System Clock
SCS
(OSCCON<0>)
Program
Counter
PC + 6
PC
PC + 2
Note 1: TOST = 1024 TOSC (drawing not to scale).
DS39612A-page 26
Advance Information
2003 Microchip Technology Inc.
PIC18F6X2X/8X2X
If the main oscillator is configured for HS mode with
PLL active, an oscillator start-up time (TOST) plus an
additional PLL time-out (TPLL) will occur. The PLL time-
out is typically 2 ms and allows the PLL to lock to the
main oscillator frequency. A timing diagram, indicating
the transition from the Timer1 oscillator to the main
oscillator for HS-PLL mode, is shown in Figure 2-10.
FIGURE 2-10:
TIMING FOR TRANSITION BETWEEN TIMER1 AND OSC1
(HS WITH PLL ACTIVE, SCS1 = 1)
TT1P
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
Q4
Q1
T1OSI
OSC1
TOST
TPLL
TOSC
1
TSCS
PLL Clock
Input
2
3
4
5
6
7
8
Internal System
Clock
SCS
(OSCCON<0>)
Program Counter
PC + 4
PC
PC + 2
Note 1: TOST = 1024 TOSC (drawing not to scale).
If the main oscillator is configured for EC mode with PLL
active, only PLL time-out (TPLL) will occur. The PLL time-
out is typically 2 ms and allows the PLL to lock to the
main oscillator frequency. A timing diagram, indicating
the transition from the Timer1 oscillator to the main
oscillator for EC with PLL active, is shown in Figure 2-11.
FIGURE 2-11:
TIMING FOR TRANSITION BETWEEN TIMER1 AND OSC1
(EC WITH PLL ACTIVE, SCS1 = 1)
TT1P
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
Q4
Q1
T1OSI
OSC1
TPLL
TOSC
TSCS
4
PLL Clock
Input
1
2
3
5
6
7
8
Internal System
Clock
SCS
(OSCCON<0>)
Program Counter
PC + 4
PC
PC + 2
2003 Microchip Technology Inc.
Advance Information
DS39612A-page 27
PIC18F6X2X/8X2X
If the main oscillator is configured in the RC, RCIO, EC
or ECIO modes, there is no oscillator start-up time-out.
Operation will resume after eight cycles of the main
oscillator have been counted. A timing diagram, indi-
cating the transition from the Timer1 oscillator to the
main oscillator for RC, RCIO, EC and ECIO modes, is
shown in Figure 2-12.
FIGURE 2-12:
TIMING FOR TRANSITION BETWEEN TIMER1 AND OSC1 (RC, EC)
Q3
Q4
Q1
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
TT1P
TOSC
T1OSI
OSC1
6
1
4
5
7
8
2
3
Internal System
Clock
SCS
(OSCCON<0>)
TSCS
Program
Counter
PC + 2
PC
PC + 4
Note:
RC Oscillator mode assumed.
switching currents have been removed, SLEEP mode
achieves the lowest current consumption of the device
(only leakage currents). Enabling any on-chip feature
that will operate during SLEEP will increase the current
consumed during SLEEP. The user can wake from
SLEEP through external RESET, Watchdog Timer
Reset, or through an interrupt.
2.7
Effects of SLEEP Mode on the
On-Chip Oscillator
When the device executes a SLEEPinstruction, the on-
chip clocks and oscillator are turned off and the device
is held at the beginning of an instruction cycle (Q1
state). With the oscillator off, the OSC1 and OSC2
signals will stop oscillating. Since all the transistor
TABLE 2-3:
OSC Mode
OSC1 AND OSC2 PIN STATES IN SLEEP MODE
OSC1 Pin
OSC2 Pin
RC
RCIO
Floating, external resistor should pull high
At logic low
Floating, external resistor should pull high
Configured as PORTA, bit 6
Configured as PORTA, bit 6
At logic low
ECIO
Floating
Floating
EC
LP, XT, and HS
Feedback inverter disabled, at
quiescent voltage level
Feedback inverter disabled, at
quiescent voltage level
Note:
See Table 3-1 in Section 3.0, “Reset” for time-outs due to SLEEP and MCLR Reset.
DS39612A-page 28
Advance Information
2003 Microchip Technology Inc.
PIC18F6X2X/8X2X
With the PLL enabled (HS+PLL and EC+PLL Oscillator
mode), the time-out sequence following a Power-on
Reset is different from other Oscillator modes. The
time-out sequence is as follows: First, the PWRT time-
out is invoked after a POR time delay has expired.
Then, the Oscillator Start-up Timer (OST) is invoked.
However, this is still not a sufficient amount of time to
allow the PLL to lock at high frequencies. The PWRT
timer is used to provide an additional fixed 2 ms (nom-
inal) time-out to allow the PLL ample time to lock to the
incoming clock frequency.
2.8
Power-up Delays
Power-up delays are controlled by two timers so that no
external RESET circuitry is required for most applica-
tions. The delays ensure that the device is kept in
RESET until the device power supply and clock are sta-
ble. For additional information on RESET operation,
see Section 3.0, “Reset”.
The first timer is the Power-up Timer (PWRT) which
optionally provides a fixed delay of 72 ms (nominal) on
power-up only (POR and BOR). The second timer is
the Oscillator Start-up Timer (OST), intended to keep
the chip in RESET until the crystal oscillator is stable.
2003 Microchip Technology Inc.
Advance Information
DS39612A-page 29
PIC18F6X2X/8X2X
NOTES:
DS39612A-page 30
Advance Information
2003 Microchip Technology Inc.
PIC18F6X2X/8X2X
Most registers are not affected by a WDT wake-up
since this is viewed as the resumption of normal oper-
ation. Status bits from the RCON register, RI, TO, PD,
POR and BOR, are set or cleared differently in different
RESET situations as indicated in Table 3-2. These bits
are used in software to determine the nature of the
RESET. See Table 3-3 for a full description of the
RESET states of all registers.
3.0
RESET
The PIC18F6X2X/8X2X devices differentiate between
various kinds of RESET:
a) Power-on Reset (POR)
b) MCLR Reset during normal operation
c) MCLR Reset during SLEEP
d) Watchdog Timer (WDT) Reset (during normal
operation)
A simplified block diagram of the On-Chip Reset Circuit
is shown in Figure 3-1.
e) Programmable Brown-out Reset (BOR)
f) RESETInstruction
The enhanced MCU devices have a MCLR noise filter
in the MCLR Reset path. The filter will detect and
ignore small pulses. The MCLR pin is not driven low by
any internal RESETS, including the WDT.
g) Stack Full Reset
h) Stack Underflow Reset
Most registers are unaffected by a RESET. Their status
is unknown on POR and unchanged by all other
RESETS. The other registers are forced to a “RESET
state” on Power-on Reset, MCLR, WDT Reset, Brown-
out Reset, MCLR Reset during SLEEP and by the
RESETinstruction.
FIGURE 3-1:
SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT
RESETInstruction
Stack Full/Underflow Reset
Stack
Pointer
External Reset
WDT
Time-out
Reset
MCLR
WDT
Module
SLEEP
VDD Rise
Detect
Power-on Reset
VDD
Brown-out
Reset
S
BOREN
OST/PWRT
OST
10-bit Ripple Counter
Chip_Reset
Q
R
OSC1
PWRT
10-bit Ripple Counter
On-chip
RC OSC(1)
Enable PWRT
(2)
Enable OST
Note 1: This is a separate oscillator from the RC oscillator of the CLKI pin.
2: See Table 3-1 for time-out situations.
2003 Microchip Technology Inc.
Advance Information
DS39612A-page 31
PIC18F6X2X/8X2X
3.1
Power-on Reset (POR)
3.3
Oscillator Start-up Timer (OST)
A Power-on Reset pulse is generated on-chip when
VDD rise is detected. To take advantage of the POR cir-
cuitry, tie the MCLR pin through a 1 kΩ to 10 kΩ resis-
tor to VDD. This will eliminate external RC components
usually needed to create a Power-on Reset delay. A
minimum rise rate for VDD is specified (parameter
D004). For a slow rise time, see Figure 3-2.
The Oscillator Start-up Timer (OST) provides 1024
oscillator cycle (from OSC1 input) delays after the
PWRT delay is over (parameter #32). This ensures that
the crystal oscillator or resonator has started and
stabilized.
The OST time-out is invoked only for XT, LP and HS
modes and only on Power-on Reset, or wake-up from
SLEEP.
When the device starts normal operation (i.e., exits the
RESET condition), device operating parameters (volt-
age, frequency, temperature, etc.) must be met to
ensure operation. If these conditions are not met, the
device must be held in RESET until the operating
conditions are met.
3.4
PLL Lock Time-out
With the PLL enabled, the time-out sequence following
a Power-on Reset is different from other Oscillator
modes. A portion of the Power-up Timer is used to pro-
vide a fixed time-out that is sufficient for the PLL to lock
to the main oscillator frequency. This PLL lock time-out
(TPLL) is typically 2 ms and follows the oscillator
start-up time-out.
FIGURE 3-2:
EXTERNAL POWER-ON
RESET CIRCUIT (FOR
SLOW VDD POWER-UP)
VDD
3.5
Brown-out Reset (BOR)
A configuration bit, BOREN, can disable (if clear/
programmed) or enable (if set) the Brown-out Reset
circuitry. If VDD falls below parameter D005 for greater
than parameter #35, the brown-out situation will reset
the chip. A RESET may not occur if VDD falls below
parameter D005 for less than parameter #35. The chip
will remain in Brown-out Reset until VDD rises above
BVDD. If the Power-up Timer is enabled, it will be
invoked after VDD rises above BVDD; it then will keep
the chip in RESET for an additional time delay
(parameter #33). If VDD drops below BVDD while the
Power-up Timer is running, the chip will go back into a
Brown-out Reset and the Power-up Timer will be
initialized. Once VDD rises above BVDD, the Power-up
Timer will execute the additional time delay.
D
R
R1
MCLR
PIC18F6X2X/8X2X
C
Note 1: External Power-on Reset circuit is required
only if the VDD power-up slope is too slow.
The diode D helps discharge the capacitor
quickly when VDD powers down.
2: R < 40 kΩ is recommended to make sure
that the voltage drop across R does not
violate the device’s electrical specification.
3: R1 = 1 kΩ to 10 kΩ will limit any current
flowing into MCLR from external capacitor
C in the event of MCLR/VPP pin breakdown,
due to Electrostatic Discharge (ESD) or
Electrical Overstress (EOS).
3.6
Time-out Sequence
On power-up, the time-out sequence is as follows:
First, PWRT time-out is invoked after the POR time
delay has expired. Then, OST is activated. The total
time-out will vary based on oscillator configuration and
the status of the PWRT. For example, in RC mode with
the PWRT disabled, there will be no time-out at all.
Figure 3-3, Figure 3-4, Figure 3-5, Figure 3-6 and
Figure 3-7 depict time-out sequences on power-up.
3.2
Power-up Timer (PWRT)
The Power-up Timer provides a fixed nominal time-out
(parameter #33) only on power-up from the POR. The
Power-up Timer operates on an internal RC oscillator.
The chip is kept in RESET as long as the PWRT is
active. The PWRT’s time delay allows VDD to rise to an
acceptable level. A configuration bit is provided to
enable/disable the PWRT.
Since the time-outs occur from the POR pulse, the
time-outs will expire if MCLR is kept low long enough.
Bringing MCLR high will begin execution immediately
(Figure 3-5). This is useful for testing purposes or to
synchronize more than one PIC18F6X2X/8X2X device
operating in parallel.
The power-up time delay will vary from chip-to-chip due
to VDD, temperature and process variation. See DC
parameter #33 for details.
Table 3-2 shows the RESET conditions for some
Special Function Registers, while Table 3-3 shows the
RESET conditions for all of the registers.
DS39612A-page 32
Advance Information
2003 Microchip Technology Inc.
PIC18F6X2X/8X2X
TABLE 3-1:
Oscillator
TIME-OUT IN VARIOUS SITUATIONS
Power-up(2)
Wake-up from
SLEEP or
Oscillator Switch
Brown-out
Configuration
PWRTE = 0
PWRTE = 1
HS with PLL enabled(1)
72 ms + 1024 TOSC
+ 2ms
1024 TOSC
+ 2 ms
72 ms(2) + 1024 TOSC
+ 2 ms
1024 TOSC + 2 ms
HS, XT, LP
EC
72 ms + 1024 TOSC
72 ms
1024 TOSC
1.5 µs
—
72 ms(2) + 1024 TOSC
72 ms(2)
1024 TOSC
1.5 µs(3)
—
External RC
72 ms
72 ms(2)
Note 1: 2 ms is the nominal time required for the 4x PLL to lock.
2: 72 ms is the nominal power-up timer delay, if implemented.
3: 1.5 µs is the recovery time from SLEEP. There is no recovery time from oscillator switch.
REGISTER 3-1:
RCON REGISTER BITS AND POSITIONS(1)
R/W-0
IPEN
U-0
—
U-0
—
R/W-1
RI
R/W-1
TO
R/W-1
PD
R/W-0
POR
R/W-0
BOR
bit 7
Note 1: Refer to Section 4.14 (page 61) for bit definitions.
bit 0
TABLE 3-2:
STATUS BITS, THEIR SIGNIFICANCE AND THE INITIALIZATION CONDITION FOR
RCON REGISTER
Program
Counter
Condition
RI TO PD POR BOR STKFUL STKUNF
Power-on Reset
0000h
0000h
1
u
1
u
1
u
0
u
0
u
u
u
u
u
MCLR Reset during normal
operation
Software Reset during normal operation
Stack Full Reset during normal operation
0000h
0000h
0000h
0
u
u
u
u
u
u
u
u
u
u
u
u
u
u
u
u
1
u
1
u
Stack Underflow Reset during normal
operation
MCLR Reset during SLEEP
WDT Reset
0000h
0000h
u
1
u
1
u
1
0
0
1
1
0
1
0
1
0
u
u
u
1
u
u
u
u
0
u
u
u
u
u
u
u
u
u
u
u
WDT Wake-up
PC + 2
0000h
PC + 2(1)
Brown-out Reset
Interrupt wake-up from SLEEP
Legend: u= unchanged, x= unknown, - = unimplemented bit, read as ‘0’
Note 1: When the wake-up is due to an interrupt and the GIEH or GIEL bits are set, the PC is loaded with the
interrupt vector (0008h or 0018h).
2003 Microchip Technology Inc.
Advance Information
DS39612A-page 33
PIC18F6X2X/8X2X
TABLE 3-3:
INITIALIZATION CONDITIONS FOR ALL REGISTERS
MCLR Resets
WDT Reset
RESET Instruction
Stack Resets
Power-on Reset,
Brown-out Reset
Wake-up via WDT
or Interrupt
Register
Applicable Devices
TOSU
PIC18F6X2X PIC18F8X2X
PIC18F6X2X PIC18F8X2X
PIC18F6X2X PIC18F8X2X
PIC18F6X2X PIC18F8X2X
PIC18F6X2X PIC18F8X2X
PIC18F6X2X PIC18F8X2X
PIC18F6X2X PIC18F8X2X
PIC18F6X2X PIC18F8X2X
PIC18F6X2X PIC18F8X2X
PIC18F6X2X PIC18F8X2X
PIC18F6X2X PIC18F8X2X
PIC18F6X2X PIC18F8X2X
PIC18F6X2X PIC18F8X2X
PIC18F6X2X PIC18F8X2X
PIC18F6X2X PIC18F8X2X
PIC18F6X2X PIC18F8X2X
PIC18F6X2X PIC18F8X2X
PIC18F6X2X PIC18F8X2X
PIC18F6X2X PIC18F8X2X
PIC18F6X2X PIC18F8X2X
PIC18F6X2X PIC18F8X2X
PIC18F6X2X PIC18F8X2X
PIC18F6X2X PIC18F8X2X
PIC18F6X2X PIC18F8X2X
PIC18F6X2X PIC18F8X2X
PIC18F6X2X PIC18F8X2X
PIC18F6X2X PIC18F8X2X
PIC18F6X2X PIC18F8X2X
PIC18F6X2X PIC18F8X2X
---0 0000
0000 0000
0000 0000
00-0 0000
--00 0000
0000 0000
0000 0000
--00 0000
0000 0000
0000 0000
0000 0000
xxxx xxxx
xxxx xxxx
0000 000x
1111 1111
1100 0000
N/A
---0 0000
0000 0000
0000 0000
uu-0 0000
--00 0000
0000 0000
0000 0000
--00 0000
0000 0000
0000 0000
0000 0000
uuuu uuuu
uuuu uuuu
0000 000x
1111 1111
1100 0000
N/A
---0 uuuu(3)
uuuu uuuu(3)
uuuu uuuu(3)
uu-u uuuu(3)
--uu uuuu
uuuu uuuu
PC + 2(2)
--uu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu(1)
uuuu uuuu(1)
uuuu uuuu(1)
N/A
TOSH
TOSL
STKPTR
PCLATU
PCLATH
PCL
TBLPTRU
TBLPTRH
TBLPTRL
TABLAT
PRODH
PRODL
INTCON
INTCON2
INTCON3
INDF0
POSTINC0
POSTDEC0
PREINC0
PLUSW0
FSR0H
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
---- 0000
xxxx xxxx
xxxx xxxx
N/A
---- 0000
uuuu uuuu
uuuu uuuu
N/A
---- uuuu
uuuu uuuu
uuuu uuuu
N/A
FSR0L
WREG
INDF1
POSTINC1
POSTDEC1
PREINC1
PLUSW1
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
Legend: u= unchanged, x= unknown, -= unimplemented bit, read as ‘0’, q= value depends on condition.
Shaded cells indicate conditions do not apply for the designated device.
Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).
2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt
vector (0008h or 0018h).
3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are
updated with the current value of the PC. The STKPTR is modified to point to the next location in the
hardware stack.
4: See Table 3-2 for RESET value for specific condition.
5: Bit 6 of PORTA, LATA, and TRISA are enabled in ECIO and RCIO Oscillator modes only. In all other
Oscillator modes, they are disabled and read ‘0’.
6: Bit 6 of PORTA, LATA and TRISA are not available on all devices. When unimplemented, they are read ‘0’.
7: If MCLR function is disabled, PORTG<5> is a read only bit.
DS39612A-page 34
Advance Information
2003 Microchip Technology Inc.
PIC18F6X2X/8X2X
TABLE 3-3:
Register
INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)
MCLR Resets
WDT Reset
Power-on Reset,
Brown-out Reset
Wake-up via WDT
or Interrupt
Applicable Devices
RESET Instruction
Stack Resets
FSR1H
PIC18F6X2X PIC18F8X2X
PIC18F6X2X PIC18F8X2X
PIC18F6X2X PIC18F8X2X
PIC18F6X2X PIC18F8X2X
PIC18F6X2X PIC18F8X2X
PIC18F6X2X PIC18F8X2X
PIC18F6X2X PIC18F8X2X
PIC18F6X2X PIC18F8X2X
PIC18F6X2X PIC18F8X2X
PIC18F6X2X PIC18F8X2X
PIC18F6X2X PIC18F8X2X
PIC18F6X2X PIC18F8X2X
PIC18F6X2X PIC18F8X2X
PIC18F6X2X PIC18F8X2X
PIC18F6X2X PIC18F8X2X
PIC18F6X2X PIC18F8X2X
PIC18F6X2X PIC18F8X2X
PIC18F6X2X PIC18F8X2X
PIC18F6X2X PIC18F8X2X
PIC18F6X2X PIC18F8X2X
PIC18F6X2X PIC18F8X2X
PIC18F6X2X PIC18F8X2X
PIC18F6X2X PIC18F8X2X
PIC18F6X2X PIC18F8X2X
PIC18F6X2X PIC18F8X2X
PIC18F6X2X PIC18F8X2X
PIC18F6X2X PIC18F8X2X
PIC18F6X2X PIC18F8X2X
PIC18F6X2X PIC18F8X2X
---- 0000
xxxx xxxx
---- 0000
N/A
---- 0000
uuuu uuuu
---- 0000
N/A
---- uuuu
uuuu uuuu
---- uuuu
N/A
FSR1L
BSR
INDF2
POSTINC2
POSTDEC2
PREINC2
PLUSW2
FSR2H
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
---- 0000
xxxx xxxx
---x xxxx
0000 0000
xxxx xxxx
1111 1111
---- 0000
--00 0101
---- ---0
0--1 11qq
xxxx xxxx
xxxx xxxx
0-00 0000
0000 0000
1111 1111
-000 0000
xxxx xxxx
0000 0000
0000 0000
0000 0000
0000 0000
---- 0000
uuuu uuuu
---u uuuu
uuuu uuuu
uuuu uuuu
1111 1111
---- 0000
--00 0101
---- ---0
0--1 qquu
uuuu uuuu
uuuu uuuu
u-uu uuuu
0000 0000
1111 1111
-000 0000
uuuu uuuu
0000 0000
0000 0000
0000 0000
0000 0000
---- uuuu
uuuu uuuu
---u uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
---- uuuu
--uu uuuu
---- ---u
u--1 qquu
uuuu uuuu
uuuu uuuu
u-uu uuuu
uuuu uuuu
1111 1111
-uuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
FSR2L
STATUS
TMR0H
TMR0L
T0CON
OSCCON
LVDCON
WDTCON
RCON(4)
TMR1H
TMR1L
T1CON
TMR2
PR2
T2CON
SSPBUF
SSPADD
SSPSTAT
SSPCON1
SSPCON2
Legend: u= unchanged, x= unknown, -= unimplemented bit, read as ‘0’, q= value depends on condition.
Shaded cells indicate conditions do not apply for the designated device.
Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).
2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt
vector (0008h or 0018h).
3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are
updated with the current value of the PC. The STKPTR is modified to point to the next location in the
hardware stack.
4: See Table 3-2 for RESET value for specific condition.
5: Bit 6 of PORTA, LATA, and TRISA are enabled in ECIO and RCIO Oscillator modes only. In all other
Oscillator modes, they are disabled and read ‘0’.
6: Bit 6 of PORTA, LATA and TRISA are not available on all devices. When unimplemented, they are read ‘0’.
7: If MCLR function is disabled, PORTG<5> is a read only bit.
2003 Microchip Technology Inc.
Advance Information
DS39612A-page 35
PIC18F6X2X/8X2X
TABLE 3-3:
INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)
MCLR Resets
WDT Reset
RESET Instruction
Stack Resets
Power-on Reset,
Brown-out Reset
Wake-up via WDT
or Interrupt
Register
Applicable Devices
ADRESH
ADRESL
ADCON0
ADCON1
ADCON2
CCPR1H
CCPR1L
CCP1CON
CCPR2H
CCPR2L
CCP2CON
CCPR3H
CCPR3L
CCP3CON
ECCP1AS
CVRCON
CMCON
TMR3H
PIC18F6X2X PIC18F8X2X
PIC18F6X2X PIC18F8X2X
PIC18F6X2X PIC18F8X2X
PIC18F6X2X PIC18F8X2X
PIC18F6X2X PIC18F8X2X
PIC18F6X2X PIC18F8X2X
PIC18F6X2X PIC18F8X2X
PIC18F6X2X PIC18F8X2X
PIC18F6X2X PIC18F8X2X
PIC18F6X2X PIC18F8X2X
PIC18F6X2X PIC18F8X2X
PIC18F6X2X PIC18F8X2X
PIC18F6X2X PIC18F8X2X
PIC18F6X2X PIC18F8X2X
PIC18F6X2X PIC18F8X2X
PIC18F6X2X PIC18F8X2X
PIC18F6X2X PIC18F8X2X
PIC18F6X2X PIC18F8X2X
PIC18F6X2X PIC18F8X2X
PIC18F6X2X PIC18F8X2X
PIC18F6X2X PIC18F8X2X
PIC18F6X2X PIC18F8X2X
PIC18F6X2X PIC18F8X2X
PIC18F6X2X PIC18F8X2X
PIC18F6X2X PIC18F8X2X
PIC18F6X2X PIC18F8X2X
PIC18F6X2X PIC18F8X2X
PIC18F6X2X PIC18F8X2X
PIC18F6X2X PIC18F8X2X
PIC18F6X2X PIC18F8X2X
PIC18F6X2X PIC18F8X2X
xxxx xxxx
xxxx xxxx
--00 0000
--00 0000
0-00 0000
xxxx xxxx
xxxx xxxx
0000 0000
xxxx xxxx
xxxx xxxx
--00 0000
xxxx xxxx
xxxx xxxx
0000 0000
0000 0000
0000 0000
0000 0000
xxxx xxxx
xxxx xxxx
0000 0000
0000 ----
0000 0000
0000 0000
0000 0000
0000 -010
0000 000x
---- --00
0000 0000
0000 0000
xx-0 x000
xx-x x000
uuuu uuuu
uuuu uuuu
--00 0000
--00 0000
0-00 0000
uuuu uuuu
uuuu uuuu
0000 0000
uuuu uuuu
uuuu uuuu
--00 0000
uuuu uuuu
uuuu uuuu
uuuu uuuu
0000 0000
0000 0000
0000 0000
uuuu uuuu
uuuu uuuu
uuuu uuuu
0000 ----
0000 0000
0000 0000
0000 0000
0000 -010
0000 000x
---- --00
0000 0000
0000 0000
uu-0 u000
uu-u u000
uuuu uuuu
uuuu uuuu
--uu uuuu
--uu uuuu
u-uu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
--uu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu ----
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu -uuu
uuuu uuuu
---- --uu
uuuu uuuu
uuuu uuuu
uu-0 u000
uu-u u000
TMR3L
T3CON
PSPCON
SPBRG1
RCREG1
TXREG1
TXSTA1
RCSTA1
EEADRH
EEADR
EEDATA
EECON2
EECON1
Legend: u= unchanged, x= unknown, -= unimplemented bit, read as ‘0’, q= value depends on condition.
Shaded cells indicate conditions do not apply for the designated device.
Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).
2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt
vector (0008h or 0018h).
3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are
updated with the current value of the PC. The STKPTR is modified to point to the next location in the
hardware stack.
4: See Table 3-2 for RESET value for specific condition.
5: Bit 6 of PORTA, LATA, and TRISA are enabled in ECIO and RCIO Oscillator modes only. In all other
Oscillator modes, they are disabled and read ‘0’.
6: Bit 6 of PORTA, LATA and TRISA are not available on all devices. When unimplemented, they are read ‘0’.
7: If MCLR function is disabled, PORTG<5> is a read only bit.
DS39612A-page 36
Advance Information
2003 Microchip Technology Inc.
PIC18F6X2X/8X2X
TABLE 3-3:
Register
INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)
MCLR Resets
WDT Reset
Power-on Reset,
Brown-out Reset
Wake-up via WDT
or Interrupt
Applicable Devices
RESET Instruction
Stack Resets
IPR3
PIC18F6X2X PIC18F8X2X
PIC18F6X2X PIC18F8X2X
PIC18F6X2X PIC18F8X2X
PIC18F6X2X PIC18F8X2X
PIC18F6X2X PIC18F8X2X
PIC18F6X2X PIC18F8X2X
PIC18F6X2X PIC18F8X2X
PIC18F6X2X PIC18F8X2X
PIC18F6X2X PIC18F8X2X
PIC18F6X2X PIC18F8X2X
PIC18F6X2X PIC18F8X2X
PIC18F6X2X PIC18F8X2X
PIC18F6X2X PIC18F8X2X
PIC18F6X2X PIC18F8X2X
PIC18F6X2X PIC18F8X2X
PIC18F6X2X PIC18F8X2X
PIC18F6X2X PIC18F8X2X
PIC18F6X2X PIC18F8X2X
PIC18F6X2X PIC18F8X2X
PIC18F6X2X PIC18F8X2X
PIC18F6X2X PIC18F8X2X
PIC18F6X2X PIC18F8X2X
PIC18F6X2X PIC18F8X2X
PIC18F6X2X PIC18F8X2X
PIC18F6X2X PIC18F8X2X
PIC18F6X2X PIC18F8X2X
PIC18F6X2X PIC18F8X2X
PIC18F6X2X PIC18F8X2X
--11 1111
--00 0000
--00 0000
-1-1 1111
-0-0 0000
-0-0 0000
1111 1111
0000 0000
0000 0000
0-00 --00
1111 1111
1111 1111
---1 1111
1111 1111
1111 1111
1111 1111
1111 1111
1111 1111
-111 1111(5)
xxxx xxxx
xxxx xxxx
---x xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
-xxx xxxx(5)
--11 1111
--00 0000
--00 0000
-1-1 1111
-0-0 0000
-0-0 0000
1111 1111
0000 0000
0000 0000
0-00 --00
1111 1111
1111 1111
---1 1111
1111 1111
1111 1111
1111 1111
1111 1111
1111 1111
-111 1111(5)
uuuu uuuu
uuuu uuuu
---u uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
-uuu uuuu(5)
--uu uuuu
--uu uuuu
--uu uuuu
-u-u uuuu
-u-u uuuu(1)
-u-u uuuu
uuuu uuuu
uuuu uuuu(1)
uuuu uuuu
u-uu --uu
uuuu uuuu
uuuu uuuu
---u uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
-uuu uuuu(5)
uuuu uuuu
uuuu uuuu
---u uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
-uuu uuuu(5)
PIR3
PIE3
IPR2
PIR2
PIE2
IPR1
PIR1
PIE1
MEMCON
TRISJ
TRISH
TRISG
TRISF
TRISE
TRISD
TRISC
TRISB
TRISA(5,6)
LATJ
LATH
LATG
LATF
LATE
LATD
LATC
LATB
LATA(5,6)
Legend: u= unchanged, x= unknown, -= unimplemented bit, read as ‘0’, q= value depends on condition.
Shaded cells indicate conditions do not apply for the designated device.
Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).
2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt
vector (0008h or 0018h).
3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are
updated with the current value of the PC. The STKPTR is modified to point to the next location in the
hardware stack.
4: See Table 3-2 for RESET value for specific condition.
5: Bit 6 of PORTA, LATA, and TRISA are enabled in ECIO and RCIO Oscillator modes only. In all other
Oscillator modes, they are disabled and read ‘0’.
6: Bit 6 of PORTA, LATA and TRISA are not available on all devices. When unimplemented, they are read ‘0’.
7: If MCLR function is disabled, PORTG<5> is a read only bit.
2003 Microchip Technology Inc.
Advance Information
DS39612A-page 37
PIC18F6X2X/8X2X
TABLE 3-3:
INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)
MCLR Resets
WDT Reset
RESET Instruction
Stack Resets
Power-on Reset,
Brown-out Reset
Wake-up via WDT
or Interrupt
Register
Applicable Devices
PORTJ
PIC18F6X2X PIC18F8X2X
PIC18F6X2X PIC18F8X2X
PIC18F6X2X PIC18F8X2X
PIC18F6X2X PIC18F8X2X
PIC18F6X2X PIC18F8X2X
PIC18F6X2X PIC18F8X2X
PIC18F6X2X PIC18F8X2X
PIC18F6X2X PIC18F8X2X
PIC18F6X2X PIC18F8X2X
PIC18F6X2X PIC18F8X2X
PIC18F6X2X PIC18F8X2X
PIC18F6X2X PIC18F8X2X
PIC18F6X2X PIC18F8X2X
PIC18F6X2X PIC18F8X2X
PIC18F6X2X PIC18F8X2X
PIC18F6X2X PIC18F8X2X
PIC18F6X2X PIC18F8X2X
PIC18F6X2X PIC18F8X2X
PIC18F6X2X PIC18F8X2X
PIC18F6X2X PIC18F8X2X
PIC18F6X2X PIC18F8X2X
PIC18F6X2X PIC18F8X2X
PIC18F6X2X PIC18F8X2X
PIC18F6X2X PIC18F8X2X
PIC18F6X2X PIC18F8X2X
PIC18F6X2X PIC18F8X2X
PIC18F6X2X PIC18F8X2X
PIC18F6X2X PIC18F8X2X
PIC18F6X2X PIC18F8X2X
PIC18F6X2X PIC18F8X2X
PIC18F6X2X PIC18F8X2X
PIC18F6X2X PIC18F8X2X
xxxx xxxx
xxxx xxxx
---x xxxx
0000 0000
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
-xxx 0000(5)
0000 0000
-1-0 0-00
0000 0000
-1-0 0-00
0000 0000
0000 0000
1111 1111
-000 0000
xxxx xxxx
xxxx xxxx
--00 0000
xxxx xxxx
xxxx xxxx
--00 0000
0000 0000
0000 0000
0000 0000
0000 -010
0000 000x
0000 0000
0000 0000
0000 0000
0000 0000
uuuu uuuu
xxxx uuuu
---u uuuu
0000 0000
0000 0000
uuuu uuuu
uuuu uuuu
uuuu uuuu
-uuu 0000(5)
0000 0000
-1-0 0-00
0000 0000
-1-0 0-00
0000 0000
0000 0000
1111 1111
-000 0000
xxxx xxxx
xxxx xxxx
--00 0000
xxxx xxxx
xxxx xxxx
--00 0000
0000 0000
0000 0000
0000 0000
0000 -010
0000 000x
0000 0000
0000 0000
0000 0000
0000 0000
uuuu uuuu
uuuu uuuu
---u uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
-uuu uuuu(5)
uuuu uuuu
-1-u u-uu
uuuu uuuu
-1-u u-uu
uuuu uuuu
uuuu uuuu
uuuu uuuu
-uuu uuuu
uuuu uuuu
uuuu uuuu
--uu uuuu
uuuu uuuu
uuuu uuuu
--uu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu -u1u
uuuu uuu-
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
PORTH
PORTG(7)
PORTF
PORTE
PORTD
PORTC
PORTB
PORTA(5,6)
SPBRGH1
BAUDCON1
SPBRGH2
BAUDCON2
ECCP1DEL
TMR4
PR4
T4CON
CCPR4H
CCPR4L
CCP4CON
CCPR5H
CCPR5L
CCP5CON
SPBRG2
RCREG2
TXREG2
TXSTA2
RCSTA2
ECCP3AS
ECCP3DEL
ECCP2AS
ECCP2DEL
Legend: u= unchanged, x= unknown, -= unimplemented bit, read as ‘0’, q= value depends on condition.
Shaded cells indicate conditions do not apply for the designated device.
Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).
2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt
vector (0008h or 0018h).
3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are
updated with the current value of the PC. The STKPTR is modified to point to the next location in the
hardware stack.
4: See Table 3-2 for RESET value for specific condition.
5: Bit 6 of PORTA, LATA, and TRISA are enabled in ECIO and RCIO Oscillator modes only. In all other
Oscillator modes, they are disabled and read ‘0’.
6: Bit 6 of PORTA, LATA and TRISA are not available on all devices. When unimplemented, they are read ‘0’.
7: If MCLR function is disabled, PORTG<5> is a read only bit.
DS39612A-page 38
Advance Information
2003 Microchip Technology Inc.
PIC18F6X2X/8X2X
FIGURE 3-3:
TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD VIA 1 kΩ RESISTOR)
VDD
MCLR
INTERNAL POR
TPWRT
PWRT TIME-OUT
OST TIME-OUT
TOST
INTERNAL RESET
FIGURE 3-4:
TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 1
VDD
MCLR
INTERNAL POR
TPWRT
PWRT TIME-OUT
OST TIME-OUT
TOST
INTERNAL RESET
FIGURE 3-5:
TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 2
VDD
MCLR
INTERNAL POR
TPWRT
PWRT TIME-OUT
OST TIME-OUT
TOST
INTERNAL RESET
2003 Microchip Technology Inc.
Advance Information
DS39612A-page 39
PIC18F6X2X/8X2X
FIGURE 3-6:
SLOW RISE TIME (MCLR TIED TO VDD VIA 1 kΩ RESISTOR)
5V
1V
0V
VDD
MCLR
INTERNAL POR
TPWRT
PWRT TIME-OUT
TOST
OST TIME-OUT
INTERNAL RESET
FIGURE 3-7:
TIME-OUT SEQUENCE ON POR W/ PLL ENABLED
(MCLR TIED TO VDD VIA 1 kΩ RESISTOR)
VDD
MCLR
INTERNAL POR
TPWRT
PWRT TIME-OUT
OST TIME-OUT
TOST
TPLL
PLL TIME-OUT
INTERNAL RESET
Note:
TOST = 1024 clock cycles.
TPLL ≈ 2 ms max. First three stages of the PWRT timer.
DS39612A-page 40
Advance Information
2003 Microchip Technology Inc.
PIC18F6X2X/8X2X
4.1.1
PIC18F6X2X/8X2X PROGRAM
MEMORY MODES
4.0
MEMORY ORGANIZATION
There are three memory blocks in PIC18F6X2X/8X2X
devices. They are:
PIC18F8X2X devices differ significantly from their
PIC18 predecessors in their utilization of program
memory. In addition to available on-chip FLASH pro-
gram memory, these controllers can also address up to
2 Mbytes of external program memory through the
external memory interface. There are four distinct
operating modes available to the controllers:
• Program Memory
• Data RAM
• Data EEPROM
Data and program memory use separate busses which
allows for concurrent access of these blocks. Additional
detailed information for FLASH program memory and
data EEPROM is provided in Section 5.0 and
Section 7.0, respectively.
• Microprocessor (MP)
• Microprocessor with Boot Block (MPBB)
• Extended Microcontroller (EMC)
• Microcontroller (MC)
In addition to on-chip FLASH, the PIC18F8X2X devices
are also capable of accessing external program mem-
ory through an external memory bus. Depending on the
selected operating mode (discussed in Section 4.1.1),
the controllers may access either internal or external
program memory exclusively, or both internal and
external memory in selected blocks. Additional infor-
mation on the external memory interface is provided in
Section 6.0.
The Program Memory mode is determined by setting
the two Least Significant bits of the CONFIG3L
Configuration Byte register as shown in Register 4-1.
(See also Section 24.1 for additional details on the
device configuration bits.)
The Program Memory modes operate as follows:
• The Microprocessor Mode permits access only
to external program memory; the contents of the
on-chip FLASH memory are ignored. The 21-bit
program counter permits access to a 2-MByte
linear program memory space.
4.1
Program Memory Organization
A 21-bit program counter is capable of addressing the
2-Mbyte program memory space. Accessing a location
between the physically implemented memory and the
2-Mbyte address will cause a read of all ‘0’s (a NOP
instruction).
• The Microprocessor with Boot Block Mode
accesses on-chip FLASH memory from addresses
000000h to 0007FFh. Above this, external program
memory is accessed all the way up to the 2-MByte
limit. Program execution automatically switches
between the two memories as required.
The PIC18F6525 and PIC18F8525 each have
48 Kbytes of on-chip FLASH memory, while the
PIC18F6621 and PIC18F8621 have 64 Kbytes of
FLASH. This means that PIC18FX525 devices can
store internally up to 24,576 single word instructions,
and PIC18FX621 devices can store up to 32,768 single
word instructions.
• The Microcontroller Mode accesses only
on-chip FLASH memory. Attempts to read above
the physical limit of the on-chip FLASH (BFFFh for
the PIC18FX525, FFFFh for the PIC18FX621)
causes a read of all ‘0’s (a NOPinstruction).
The Microcontroller mode is also the only operating
mode available to PIC18F6X2X devices.
The RESET vector address is at 0000h, and the
interrupt vector addresses are at 0008h and 0018h.
• The Extended Microcontroller Mode allows
access to both internal and external program
memories as a single block. The device can
access its entire on-chip FLASH memory; above
this, the device accesses external program mem-
ory up to the 2-MByte program space limit. As
with Boot Block mode, execution automatically
switches between the two memories as required.
Figure 4-1 shows the program memory map for
PIC18FX525 devices, while Figure 4-2 shows the
program memory map for PIC18FX621 devices.
In all modes, the microcontroller has complete access
to data RAM and EEPROM.
Figure 4-3 compares the memory maps of the different
Program Memory modes. The differences between
on-chip and external memory access limitations are
more fully explained in Table 4-1.
2003 Microchip Technology Inc.
Advance Information
DS39612A-page 41
PIC18F6X2X/8X2X
FIGURE 4-1:
INTERNAL PROGRAM
MEMORY MAP AND
FIGURE 4-2:
INTERNAL PROGRAM
MEMORY MAP AND
STACK FOR PIC18FX525
STACK FOR PIC18FX621
PC<20:0>
PC<20:0>
21
21
CALL,RCALL,RETURN
RETFIE,RETLW
CALL,RCALL,RETURN
RETFIE,RETLW
Stack Level 1
Stack Level 1
•
•
•
•
•
•
Stack Level 31
RESET Vector
Stack Level 31
RESET Vector
000000h
000000h
High Priority Interrupt Vector
Low Priority Interrupt Vector
High Priority Interrupt Vector
Low Priority Interrupt Vector
000008h
000018h
000008h
000018h
On-Chip FLASH
Program Memory
00BFFFh
00C000h
On-Chip FLASH
Program Memory
00FFFFh
010000h
Read ‘0’
Read ‘0’
1FFFFFh
200000h
1FFFFFh
200000h
TABLE 4-1:
Operating Mode
Microprocessor
MEMORY ACCESS FOR PIC18F8X2X PROGRAM MEMORY MODES
Internal Program Memory
External Program Memory
Execution
From
Table Read
Execution
From
Table Read
From
Table Write To
Table Write To
From
No Access
Yes
No Access
Yes
No Access
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Microprocessor
w/ Boot Block
Microcontroller
Yes
Yes
Yes
Yes
Yes
Yes
No Access
Yes
No Access
Yes
No Access
Yes
Extended
Microcontroller
DS39612A-page 42
Advance Information
2003 Microchip Technology Inc.
PIC18F6X2X/8X2X
REGISTER 4-1:
CONFIG3L CONFIGURATION BYTE
R/P-1
WAIT
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
R/P-1
PM1
R/P-1
PM0
bit 7
bit 0
bit 7
WAIT: External Bus Data Wait Enable bit
1= Wait selections unavailable, device will not wait
0= Wait programmed by WAIT1 and WAIT0 bits of MEMCOM register (MEMCOM<5:4>)
bit 6-2
bit 1-0
Unimplemented: Read as ‘0’
PM1:PM0: Processor Data Memory Mode Select bits
11= Microcontroller mode
10= Microprocessor mode(1)
01= Microcontroller with Boot Block mode(1)
00= Extended Microcontroller mode(1)
Note 1: This mode is available only on PIC18F8X2X devices.
Legend:
R = Readable bit
P = Programmable bit U = Unimplemented bit, read as ‘0’
‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
- n = Value after erase
FIGURE 4-3:
MEMORY MAPS FOR PIC18F6X2X/8X2X PROGRAM MEMORY MODES
Microprocessor
with Boot Block
Mode(3)
Extended
Microcontroller
Mode(3)
Microprocessor
Microcontroller
Mode
Mode(3)
000000h
000000h
000000h
000000h
On-Chip
Program
Memory
(No
On-Chip
Program
Memory
On-Chip
On-Chip
Program
Memory
Program
Memory
00BFFFh(1)
00FFFFh(2)
00C000h(1)
010000h(2)
00BFFFh(1)
00FFFFh(2)
00C000h(1)
010000h(2)
access)
0007FFh
000800h
External
Program
Memory
Reads
‘0’s
External
Program
Memory
External
Program
Memory
1FFFFFh
1FFFFFh
1FFFFFh
1FFFFFh
External
Memory
On-Chip
FLASH
External
Memory
External
Memory
On-Chip
FLASH
On-Chip
FLASH
On-Chip
FLASH
Note 1: PIC18F8525 and PIC18F6525.
2: PIC18F8621 and PIC18F6621.
3: This mode is available only on PIC18F8X2X devices.
2003 Microchip Technology Inc.
Advance Information
DS39612A-page 43
PIC18F6X2X/8X2X
4.2.2
RETURN STACK POINTER
(STKPTR)
4.2
Return Address Stack
The return address stack allows any combination of up
to 31 program calls and interrupts to occur. The PC
(Program Counter) is pushed onto the stack when a
CALLor RCALLinstruction is executed, or an interrupt
is Acknowledged. The PC value is pulled off the stack
on a RETURN, RETLW, or a RETFIE instruction.
PCLATU and PCLATH are not affected by any of the
RETURNor CALLinstructions.
The STKPTR register contains the stack pointer value,
the STKFUL (stack full) status bit, and the STKUNF
(stack underflow) status bits. Register 4-2 shows the
STKPTR register. The value of the stack pointer can be
0 through 31. The stack pointer increments when val-
ues are pushed onto the stack and decrements when
values are popped off the stack. At RESET, the stack
pointer value will be ‘0’. The user may read and write
the stack pointer value. This feature can be used by a
real-time operating system for return stack
maintenance.
The stack operates as a 31-word by 21-bit RAM and a
5-bit stack pointer, with the stack pointer initialized to
00000b after all RESETS. There is no RAM associated
with stack pointer 00000b. This is only a RESET value.
During a CALLtype instruction causing a push onto the
stack, the stack pointer is first incremented and the
RAM location pointed to by the stack pointer is written
with the contents of the PC. During a RETURN type
instruction causing a pop from the stack, the contents
of the RAM location pointed to by the STKPTR are
transferred to the PC and then the stack pointer is
decremented.
After the PC is pushed onto the stack 31 times (without
popping any values off the stack), the STKFUL bit is
set. The STKFUL bit can only be cleared in software or
by a POR.
The action that takes place when the stack becomes
full depends on the state of the STVREN (Stack Over-
flow Reset Enable) configuration bit. Refer to
Section 25.0 for a description of the device configura-
tion bits. If STVREN is set (default), the 31st push will
push the (PC + 2) value onto the stack, set the STKFUL
bit, and reset the device. The STKFUL bit will remain
set and the stack pointer will be set to ‘0’.
The stack space is not part of either program or data
space. The stack pointer is readable and writable, and
the address on the top of the stack is readable and writ-
able through SFR registers. Data can also be pushed
to, or popped from the stack using the top-of-stack
SFRs. Status bits indicate if the stack pointer is at, or
beyond the 31 levels provided.
If STVREN is cleared, the STKFUL bit will be set on the
31st push and the stack pointer will increment to 31.
Any additional pushes will not overwrite the 31st push,
and STKPTR will remain at 31.
4.2.1
TOP-OF-STACK ACCESS
When the stack has been popped enough times to
unload the stack, the next pop will return a value of zero
to the PC and sets the STKUNF bit, while the stack
pointer remains at ‘0’. The STKUNF bit will remain set
until cleared in software or a POR occurs.
The top of the stack is readable and writable. Three
register locations, TOSU, TOSH and TOSL hold the
contents of the stack location pointed to by the
STKPTR register. This allows users to implement a
software stack if necessary. After a CALL, RCALLor
interrupt, the software can read the pushed value by
reading the TOSU, TOSH and TOSL registers. These
values can be placed on a user defined software stack.
At return time, the software can replace the TOSU,
TOSH and TOSL and do a return.
Note:
Returning a value of zero to the PC on an
underflow has the effect of vectoring the
program to the RESET vector, where the
stack conditions can be verified and
appropriate actions can be taken.
The user must disable the global interrupt enable bits
during this time to prevent inadvertent stack
operations.
DS39612A-page 44
Advance Information
2003 Microchip Technology Inc.
PIC18F6X2X/8X2X
REGISTER 4-2:
STKPTR REGISTER
R/C-0 R/C-0
U-0
—
R/W-0
SP4
R/W-0
SP3
R/W-0
SP2
R/W-0
SP1
R/W-0
SP0
STKFUL(1) STKUNF(1)
bit 7
bit 0
bit 7
bit 6
STKFUL: Stack Full Flag bit
1= Stack became full or overflowed
0= Stack has not become full or overflowed
STKUNF: Stack Underflow Flag bit
1= Stack underflow occurred
0= Stack underflow did not occur
bit 5
Unimplemented: Read as ‘0’
bit 4-0
SP4:SP0: Stack Pointer Location bits
Note 1: Bit 7 and bit 6 can only be cleared in user software or by a POR.
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
- n = Value at POR
FIGURE 4-4:
RETURN ADDRESS STACK AND ASSOCIATED REGISTERS
Return Address Stack
11111
11110
11101
STKPTR<4:0>
TOSU
0x00
TOSH
0x1A
TOSL
0x34
00010
00011
0x001A34 00010
0x000D58 00001
00000
Top-of-Stack
4.2.3
PUSHAND POPINSTRUCTIONS
4.2.4
STACK FULL/UNDERFLOW RESETS
Since the Top-of-Stack (TOS) is readable and writable,
the ability to push values onto the stack and pull values
off the stack, without disturbing normal program execu-
tion, is a desirable option. To push the current PC value
onto the stack, a PUSH instruction can be executed.
This will increment the stack pointer and load the cur-
rent PC value onto the stack. TOSU, TOSH and TOSL
can then be modified to place a return address on the
stack.
These RESETS are enabled by programming the
STVREN configuration bit. When the STVREN bit is
disabled, a full or underflow condition will set the appro-
priate STKFUL or STKUNF bit, but not cause a device
RESET. When the STVREN bit is enabled, a full or
underflow condition will set the appropriate STKFUL or
STKUNF bit and then cause a device RESET. The
STKFUL or STKUNF bits are only cleared by the user
software or a POR Reset.
The ability to pull the TOS value off of the stack and
replace it with the value that was previously pushed
onto the stack, without disturbing normal execution, is
achieved by using the POPinstruction. The POPinstruc-
tion discards the current TOS by decrementing the
stack pointer. The previous value pushed onto the
stack then becomes the TOS value.
2003 Microchip Technology Inc.
Advance Information
DS39612A-page 45
PIC18F6X2X/8X2X
4.3
Fast Register Stack
4.4
PCL, PCLATH and PCLATU
A “fast interrupt return” option is available for interrupts.
A fast register stack is provided for the STATUS,
WREG and BSR registers and is only one in depth. The
stack is not readable or writable and is loaded with the
current value of the corresponding register when the
processor vectors for an interrupt. The values in the
registers are then loaded back into the working regis-
ters if the FAST RETURNinstruction is used to return
from the interrupt.
The program counter (PC) specifies the address of the
instruction to fetch for execution. The PC is 21 bits
wide. The low byte is called the PCL register; this reg-
ister is readable and writable. The high byte is called
the PCH register. This register contains the PC<15:8>
bits and is not directly readable or writable; updates to
the PCH register may be performed through the
PCLATH register. The upper byte is called PCU. This
register contains the PC<20:16> bits and is not directly
readable or writable; updates to the PCU register may
be performed through the PCLATU register.
A low or high priority interrupt source will push values
into the stack registers. If both low and high priority
interrupts are enabled, the stack registers cannot be
used reliably for low priority interrupts. If a high priority
interrupt occurs while servicing a low priority interrupt,
the stack register values stored by the low priority
interrupt will be overwritten.
The PC addresses bytes in the program memory. To
prevent the PC from becoming misaligned with word
instructions, the LSB of the PCL is fixed to a value of
‘0’. The PC increments by 2 to address sequential
instructions in the program memory.
If high priority interrupts are not disabled during low pri-
ority interrupts, users must save the key registers in
software during a low priority interrupt.
The CALL, RCALL, GOTO and program branch
instructions write to the program counter directly. For
these instructions, the contents of PCLATH and
PCLATU are not transferred to the program counter.
If no interrupts are used, the fast register stack can be
used to restore the STATUS, WREG and BSR registers
at the end of a subroutine call. To use the fast register
stack for a subroutine call, a FAST CALL instruction
must be executed.
The contents of PCLATH and PCLATU will be trans-
ferred to the program counter by an operation that
writes PCL. Similarly, the upper two bytes of the pro-
gram counter will be transferred to PCLATH and
PCLATU by an operation that reads PCL. This is useful
for computed offsets to the PC (see Section 4.8.1).
Example 4-1 shows a source code example that uses
the fast register stack.
4.5
Clocking Scheme/Instruction
Cycle
EXAMPLE 4-1:
FAST REGISTER STACK
CODE EXAMPLE
CALL SUB1, FAST
;STATUS, WREG, BSR
;SAVED IN FAST REGISTER
;STACK
The clock input (from OSC1) is internally divided by
four to generate four non-overlapping quadrature
clocks, namely Q1, Q2, Q3 and Q4. Internally, the pro-
gram counter (PC) is incremented every Q1, the
instruction is fetched from the program memory and
latched into the instruction register in Q4. The instruc-
tion is decoded and executed during the following Q1
through Q4. The clocks and instruction execution flow
are shown in Figure 4-5.
•
•
SUB1
•
•
•
RETURN FAST
;RESTORE VALUES SAVED
;IN FAST REGISTER STACK
FIGURE 4-5:
CLOCK/INSTRUCTION CYCLE
Q2
Q3
Q4
Q2
Q3
Q4
Q2
Q3
Q4
Q1
Q1
Q1
OSC1
Q1
Q2
Q3
Internal
Phase
Clock
Q4
PC
PC+2
PC+4
PC
OSC2/CLKO
(RC mode)
Execute INST (PC-2)
Fetch INST (PC)
Execute INST (PC)
Fetch INST (PC+2)
Execute INST (PC+2)
Fetch INST (PC+4)
DS39612A-page 46
Advance Information
2003 Microchip Technology Inc.
PIC18F6X2X/8X2X
A fetch cycle begins with the program counter (PC)
incrementing in Q1.
4.6
Instruction Flow/Pipelining
An “Instruction Cycle” consists of four Q cycles (Q1,
Q2, Q3 and Q4). The instruction fetch and execute are
pipelined such that fetch takes one instruction cycle,
while decode and execute take another instruction
cycle. However, due to the pipelining, each instruction
effectively executes in one cycle. If an instruction
causes the program counter to change (e.g., GOTO),
then two cycles are required to complete the instruction
(Example 4-2).
In the execution cycle, the fetched instruction is latched
into the “Instruction Register” (IR) in cycle Q1. This
instruction is then decoded and executed during the
Q2, Q3, and Q4 cycles. Data memory is read during Q2
(operand read) and written during Q4 (destination
write).
EXAMPLE 4-2:
INSTRUCTION PIPELINE FLOW
TCY0
TCY1
TCY2
TCY3
TCY4
TCY5
1. MOVLW 55h
2. MOVWF PORTB
3. BRA SUB_1
Fetch 1
Execute 1
Fetch 2
Execute 2
Fetch 3
Execute 3
Fetch 4
4. BSF
PORTA, BIT3 (Forced NOP)
Flush (NOP)
5. Instruction @ address SUB_1
Fetch SUB_1 Execute SUB_1
All instructions are single cycle except for any program branches. These take two cycles since the fetch instruction
is “flushed” from the pipeline, while the new instruction is being fetched and then executed.
word boundaries, the data contained in the instruction
4.7
Instructions in Program Memory
is a word address. The word address is written to
PC<20:1> which accesses the desired byte address in
program memory. Instruction #2 in Figure 4-6 shows
how the instruction “GOTO 000006h” is encoded in the
program memory. Program branch instructions, which
encode a relative address offset, operate in the same
manner. The offset value stored in a branch instruction
represents the number of single word instructions that
the PC will be offset by. Section 25.0 provides further
details of the instruction set.
The program memory is addressed in bytes. Instruc-
tions are stored as two bytes or four bytes in program
memory. The Least Significant Byte of an instruction
word is always stored in a program memory location
with an even address (LSB = 0). Figure 4-6 shows an
example of how instruction words are stored in the pro-
gram memory. To maintain alignment with instruction
boundaries, the PC increments in steps of 2 and the
LSB will always read ‘0’ (see Section 4.4).
The CALL and GOTO instructions have an absolute
program memory address embedded into the
instruction. Since instructions are always stored on
FIGURE 4-6:
INSTRUCTIONS IN PROGRAM MEMORY
Word Address
LSB = 1
LSB = 0
↓
Program Memory
Byte Locations →
000000h
000002h
000004h
000006h
000008h
00000Ah
00000Ch
00000Eh
000010h
000012h
000014h
Instruction 1:
Instruction 2:
0Fh
EFh
F0h
C1h
F4h
55h
03h
00h
23h
56h
MOVLW
GOTO
055h
000006h
Instruction 3:
MOVFF
123h, 456h
2003 Microchip Technology Inc.
Advance Information
DS39612A-page 47
PIC18F6X2X/8X2X
accessed. If the second word of the instruction is exe-
cuted by itself (first word was skipped), it will execute as
a NOP. This action is necessary when the two-word
instruction is preceded by a conditional instruction that
changes the PC. A program example that demon-
strates this concept is shown in Example 4-3. Refer to
Section 25.0 for further details of the instruction set.
4.7.1
TWO-WORD INSTRUCTIONS
The PIC18F6X2X/8X2X devices have four two-word
instructions: MOVFF, CALL, GOTO and LFSR. The
second word of these instructions has the 4 MSBs set
to ‘1’s and is a special kind of NOP instruction. The
lower 12 bits of the second word contain data to be
used by the instruction. If the first word of the instruc-
tion is executed, the data in the second word is
EXAMPLE 4-3:
CASE 1:
TWO-WORD INSTRUCTIONS
Object Code
Source Code
0110 0110 0000 0000 TSTFSZ
1100 0001 0010 0011 MOVFF
1111 0100 0101 0110
REG1
; is RAM location 0?
REG1, REG2 ; No, execute 2-word instruction
; 2nd operand holds address of REG2
0010 0100 0000 0000 ADDWF
REG3
; continue code
CASE 2:
Object Code
Source Code
0110 0110 0000 0000 TSTFSZ
1100 0001 0010 0011 MOVFF
1111 0100 0101 0110
REG1
; is RAM location 0?
REG1, REG2 ; Yes
; 2nd operand becomes NOP
REG3 ; continue code
0010 0100 0000 0000 ADDWF
4.8.2
TABLE READS/TABLE WRITES
4.8
Lookup Tables
A better method of storing data in program memory
allows 2 bytes of data to be stored in each instruction
location.
Lookup tables are implemented two ways. These are:
• Computed GOTO
• Table Reads
Lookup table data may be stored 2 bytes per program
word by using table reads and writes. The table pointer
(TBLPTR) specifies the byte address and the table
latch (TABLAT) contains the data that is read from, or
written to program memory. Data is transferred to/from
program memory, one byte at a time.
4.8.1
COMPUTED GOTO
A computed GOTOis accomplished by adding an offset
to the program counter (ADDWF PCL).
A lookup table can be formed with an ADDWF PCL
instruction and a group of RETLW 0xnn instructions.
WREG is loaded with an offset into the table before
executing a call to that table. The first instruction of the
called routine is the ADDWF PCLinstruction. The next
instruction executed will be one of the RETLW 0xnn
instructions that returns the value 0xnn to the calling
function.
A description of the table read/table write operation is
shown in Section 5.0.
The offset value (value in WREG) specifies the number
of bytes that the program counter should advance.
In this method, only one data byte may be stored in
each instruction location and room on the return
address stack is required.
DS39612A-page 48
Advance Information
2003 Microchip Technology Inc.
PIC18F6X2X/8X2X
4.9.1
GENERAL PURPOSE REGISTER
FILE
4.9
Data Memory Organization
The data memory is implemented as static RAM. Each
register in the data memory has a 12-bit address,
allowing up to 4096 bytes of data memory. Figure 4-7
shows the data memory organization for the
PIC18F6X2X/8X2X devices.
The register file can be accessed either directly or indi-
rectly. Indirect addressing operates using a File Select
Register and corresponding Indirect File Operand. The
operation of indirect addressing is shown in
Section 4.12.
The data memory map is divided into 16 banks that
contain 256 bytes each. The lower 4 bits of the Bank
Select Register (BSR<3:0>) select which bank will be
accessed. The upper 4 bits for the BSR are not
implemented.
Enhanced MCU devices may have banked memory in
the GPR area. GPRs are not initialized by a Power-on
Reset and are unchanged on all other RESETS.
Data RAM is available for use as general purpose reg-
isters by all instructions. The top section of Bank 15
(F60h to FFFh) contains SFRs. All other banks of data
memory contain GPRs, starting with Bank 0.
The data memory contains Special Function Registers
(SFR) and General Purpose Registers (GPR). The
SFRs are used for control and status of the controller
and peripheral functions, while GPRs are used for data
storage and scratch pad operations in the user’s appli-
cation. The SFRs start at the last location of Bank 15
(0FFFh) and extend downwards. Any remaining space
beyond the SFRs in the bank may be implemented as
GPRs. GPRs start at the first location of Bank 0 and
grow upwards. Any read of an unimplemented location
will read as ‘0’s.
4.9.2
SPECIAL FUNCTION REGISTERS
The Special Function Registers (SFRs) are registers
used by the CPU and peripheral modules for controlling
the desired operation of the device. These registers are
implemented as static RAM. A list of these registers is
given in Table 4-2 and Table 4-3.
The SFRs can be classified into two sets: those asso-
ciated with the “core” function and those related to the
peripheral functions. Those registers related to the
“core” are described in this section, while those related
to the operation of the peripheral features are
described in the section of that peripheral feature. The
SFRs are typically distributed among the peripherals
whose functions they control.
The entire data memory may be accessed directly or
indirectly. Direct addressing may require the use of the
BSR register. Indirect addressing requires the use of a
File Select Register (FSRn) and a corresponding Indi-
rect File Operand (INDFn). Each FSR holds a 12-bit
address value that can be used to access any location
in the data memory map without banking.
The instruction set and architecture allow operations
across all banks. This may be accomplished by indirect
addressing or by the use of the MOVFFinstruction. The
MOVFF instruction is a two-word/two-cycle instruction
that moves a value from one register to another.
The unused SFR locations are unimplemented and
read as ‘0’s. The addresses for the SFRs are listed in
Table 4-2.
To ensure that commonly used registers (SFRs and
select GPRs) can be accessed in a single cycle
regardless of the current BSR values, an Access Bank
is implemented. A segment of Bank 0 and a segment of
Bank 15 comprise the Access RAM. Section 4.10
provides a detailed description of the Access RAM.
2003 Microchip Technology Inc.
Advance Information
DS39612A-page 49
PIC18F6X2X/8X2X
FIGURE 4-7:
DATA MEMORY MAP FOR PIC18F6X2X/8X2X DEVICES
BSR<3:0>
Data Memory Map
000h
00h
Access RAM
GPRs
= 0000
05Fh
Bank 0
060h
FFh
00h
0FFh
100h
= 0001
= 0010
GPRs
GPRs
Bank 1
Bank 2
Bank 3
FFh
00h
1FFh
200h
FFh
00h
2FFh
300h
= 0011
= 0100
GPRs
GPRs
FFh
3FFh
400h
Bank 4
Access Bank
4FFh
500h
00h
Access RAM low
5Fh
50h
Access RAM high
(SFRs)
FFh
Bank 5
to
Bank 13
GPRs
GPRs
When a = 0,
the BSR is ignored and the
Access Bank is used.
The first 128 bytes are General
Purpose RAM (from Bank 0).
The second 128 bytes are
Special Function Registers
(from Bank 15).
DFFh
E00h
00h
= 1110
Bank 14
Bank 15
FFh
00h
EFFh
F00h
Unused
SFRs
= 1111
F5Fh
F60h
FFh
FFFh
When a = 1,
the BSR is used to specify the
RAM location that the instruction
uses.
DS39612A-page 50
Advance Information
2003 Microchip Technology Inc.
PIC18F6X2X/8X2X
TABLE 4-2:
SPECIAL FUNCTION REGISTER MAP
Address
FFFh
FFEh
FFDh
FFCh
FFBh
FFAh
FF9h
FF8h
FF7h
FF6h
FF5h
FF4h
FF3h
FF2h
FF1h
FF0h
FEFh
Name
TOSU
Address
FDFh
Name
INDF2(3)
Address
FBFh
FBEh
Name
Address
F9Fh
Name
IPR1
PIR1
PIE1
CCPR1H
CCPR1L
TOSH
FDEh POSTINC2(3)
FDDh POSTDEC2(3)
FDCh PREINC2(3)
FDBh PLUSW2(3)
F9Eh
TOSL
FBDh CCP1CON
F9Dh
F9Ch MEMCON(2)
STKPTR
PCLATU
PCLATH
PCL
FBCh
FBBh
CCPR2H
CCPR2L
(1)
F9Bh
F9Ah
F99h
F98h
F97h
F96h
F95h
F94h
F93h
F92h
F91h
F90h
F8Fh
F8Eh
F8Dh
F8Ch
F8Bh
F8Ah
F89h
—
FDAh
FD9h
FD8h
FD7h
FD6h
FD5h
FD4h
FD3h
FD2h
FD1h
FD0h
FCFh
FCEh
FCDh
FCCh
FCBh
FCAh
FC9h
FC8h
FC7h
FC6h
FC5h
FC4h
FC3h
FC2h
FC1h
FC0h
FSR2H
FSR2L
FBAh CCP2CON
TRISJ(2)
TRISH(2)
TRISG
TRISF
TRISE
TRISD
TRISC
TRISB
TRISA
LATJ(2)
LATH(2)
LATG
FB9h
FB8h
CCPR3H
CCPR3L
TBLPTRU
TBLPTRH
TBLPTRL
TABLAT
PRODH
PRODL
INTCON
INTCON2
INTCON3
INDF0(3)
STATUS
TMR0H
TMR0L
T0CON
FB7h CCP3CON
FB6h ECCP1AS
FB5h CVRCON
(1)
—
FB4h
FB3h
FB2h
FB1h
CMCON
TMR3H
TMR3L
T3CON
OSCCON
LVDCON
WDTCON
RCON
FB0h PSPCON
FAFh SPBRG1
FAEh RCREG1
TMR1H
FEEh POSTINC0(3)
FEDh POSTDEC0(3)
FECh PREINC0(3)
FEBh PLUSW0(3)
TMR1L
LATF
T1CON
FADh
FACh
FABh
TXREG1
TXSTA1
RCSTA1
LATE
TMR2
LATD
PR2
LATC
FEAh
FE9h
FE8h
FE7h
FE6h POSTINC1(3)
FE5h POSTDEC1(3)
FE4h PREINC1(3)
FE3h PLUSW1(3)
FSR0H
FSR0L
WREG
INDF1(3)
T2CON
FAAh EEADRH
LATB
SSPBUF
SSPADD
SSPSTAT
SSPCON1
SSPCON2
ADRESH
ADRESL
ADCON0
ADCON1
ADCON2
FA9h
FA8h
FA7h
FA6h
FA5h
FA4h
FA3h
FA2h
FA1h
FA0h
EEADR
EEDATA
EECON2
EECON1
IPR3
LATA
F88h PORTJ(2)
F87h PORTH(2)
F86h
F85h
F84h
F83h
F82h
F81h
F80h
PORTG
PORTF
PORTE
PORTD
PORTC
PORTB
PORTA
PIR3
PIE3
FE2h
FE1h
FE0h
FSR1H
FSR1L
BSR
IPR2
PIR2
PIE2
Note 1: Unimplemented registers are read as ‘0’.
2: This register is not available on PIC18F6X2X devices.
3: This is not a physical register.
2003 Microchip Technology Inc.
Advance Information
DS39612A-page 51
PIC18F6X2X/8X2X
TABLE 4-2:
SPECIAL FUNCTION REGISTER MAP (CONTINUED)
Address
Name
Address
F5Fh
Name
Address
F3Fh
Name
Address
F1Fh
Name
(1)
(1)
(1)
F7Fh
SPBRGH1
—
—
—
(1)
(1)
(1)
F7Eh BAUDCON1
F7Dh SPBRGH2
F5Eh
F5Dh
F5Ch
F5Bh
F5Ah
F59h
F58h
F57h
F56h
F55h
F54h
F53h
F52h
F51h
F50h
F4Fh
F4Eh
F4Dh
F4Ch
F4Bh
F4Ah
F49h
F48h
F47h
F46h
F45h
F44h
F43h
F42h
F41h
F40h
F3Eh
F3Dh
F3Ch
F3Bh
F3Ah
F39h
F38h
F37h
F36h
F35h
F34h
F33h
F32h
F31h
F30h
F2Fh
F2Eh
F2Dh
F2Ch
F2Bh
F2Ah
F29h
F28h
F27h
F26h
F25h
F24h
F23h
F22h
F21h
F20h
F1Eh
F1Dh
F1Ch
F1Bh
F1Ah
F19h
F18h
F17h
F16h
F15h
F14h
F13h
F12h
F11h
F10h
F0Fh
F0Eh
F0Dh
F0Ch
F0Bh
F0Ah
F09h
F08h
F07h
F06h
F05h
F04h
F03h
F02h
F01h
F00h
—
—
—
(1)
(1)
(1)
—
—
—
(1)
(1)
(1)
F7Ch BAUDCON2
—
—
—
(1)
(1)
(1)
(1)
—
—
F7Bh
F7Ah
—
—
—
(1)
(1)
(1)
(1)
—
—
—
(1)
(1)
(1)
F79h ECCP1DEL
—
—
—
(1)
(1)
(1)
F78h
F77h
F76h
F75h
F74h
TMR4
PR4
—
—
—
(1)
(1)
(1)
—
—
—
(1)
(1)
(1)
T4CON
CCPR4H
CCPR4L
—
—
—
(1)
(1)
(1)
—
—
—
(1)
(1)
(1)
—
—
—
(1)
(1)
(1)
F73h CCP4CON
—
—
—
(1)
(1)
(1)
F72h
F71h
CCPR5H
CCPR5L
—
—
—
(1)
(1)
(1)
—
—
—
(1)
(1)
(1)
F70h CCP5CON
—
—
—
(1)
(1)
(1)
F6Fh
F6Eh
F6Dh
F6Ch
F6Bh
F6Ah
SPBRG2
RCREG2
TXREG2
TXSTA2
—
—
—
(1)
(1)
(1)
—
—
—
(1)
(1)
(1)
—
—
—
(1)
(1)
(1)
—
—
—
(1)
(1)
(1)
RCSTA2
ECCP3AS
—
—
—
(1)
(1)
(1)
—
—
—
(1)
(1)
(1)
F69h ECCP3DEL
F68h ECCP2AS
—
—
—
(1)
(1)
(1)
—
—
—
(1)
(1)
(1)
F67h ECCP2DEL
—
—
—
(1)
(1)
(1)
(1)
F66h
F65h
F64h
F63h
F62h
F61h
F60h
—
—
—
—
—
—
—
—
—
—
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
—
—
—
(1)
(1)
(1)
—
—
—
(1)
(1)
(1)
—
—
—
(1)
(1)
(1)
—
—
—
(1)
(1)
(1)
—
—
—
(1)
(1)
(1)
—
—
—
Note 1: Unimplemented registers are read as ‘0’.
2: This register is not available on PIC18F6X2X devices.
3: This is not a physical register.
DS39612A-page 52
Advance Information
2003 Microchip Technology Inc.
PIC18F6X2X/8X2X
TABLE 4-3:
File Name
TOSU
REGISTER FILE SUMMARY
Value on
POR, BOR on page:
Details
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
—
—
—
Top-of-Stack Upper Byte (TOS<20:16>)
---0 0000 34, 44
0000 0000 34, 44
0000 0000 34, 44
00-0 0000 34, 45
--10 0000 34, 46
0000 0000 34, 46
0000 0000 34, 46
--00 0000 34, 71
0000 0000 34, 71
0000 0000 34, 71
0000 0000 34, 71
xxxx xxxx 34, 87
xxxx xxxx 34, 87
0000 0000 34, 91
1111 1111 34, 92
1100 0000 34, 93
TOSH
Top-of-Stack High Byte (TOS<15:8>)
Top-of-Stack Low Byte (TOS<7:0>)
TOSL
STKPTR
PCLATU
PCLATH
PCL
STKFUL
—
STKUNF
—
—
Return Stack Pointer
bit 21
Holding Register for PC<20:16>
Holding Register for PC<15:8>
PC Low Byte (PC<7:0>)
(2)
TBLPTRU
—
—
bit 21
Program Memory Table Pointer Upper Byte (TBLPTR<20:16>)
TBLPTRH Program Memory Table Pointer High Byte (TBLPTR<15:8>)
TBLPTRL
TABLAT
PRODH
PRODL
Program Memory Table Pointer Low Byte (TBLPTR<7:0>)
Program Memory Table Latch
Product Register High Byte
Product Register Low Byte
INTCON
INTCON2
INTCON3
INDF0
GIE/GIEH PEIE/GIEL
TMR0IE
INTEDG1
INT3IE
INT0IE
INTEDG2
INT2IE
RBIE
INTEDG3
INT1IE
TMR0IF
TMR0IP
INT3IF
INT0IF
INT3IP
INT2IF
RBIF
RBIP
RBPU
INTEDG0
INT1IP
INT2IP
INT1IF
Uses contents of FSR0 to address data memory - value of FSR0 not changed (not a physical register)
n/a
n/a
58
58
POSTINC0 Uses contents of FSR0 to address data memory - value of FSR0 post-incremented
(not a physical register)
POSTDEC0 Uses contents of FSR0 to address data memory - value of FSR0 post-decremented
(not a physical register)
n/a
58
PREINC0
PLUSW0
Uses contents of FSR0 to address data memory - value of FSR0 pre-incremented (not a physical register)
n/a
n/a
58
58
Uses contents of FSR0 to address data memory - value of FSR0 pre-incremented
(not a physical register) - value of FSR0 offset by value in WREG
FSR0H
FSR0L
WREG
INDF1
—
—
—
—
Indirect Data Memory Address Pointer 0 High Byte ---- 0000 34, 58
xxxx xxxx 34, 58
Indirect Data Memory Address Pointer 0 Low Byte
Working Register
xxxx xxxx
34
58
58
Uses contents of FSR1 to address data memory - value of FSR1 not changed (not a physical register)
n/a
n/a
POSTINC1 Uses contents of FSR1 to address data memory - value of FSR1 post-incremented
(not a physical register)
POSTDEC1 Uses contents of FSR1 to address data memory - value of FSR1 post-decremented
(not a physical register)
n/a
58
PREINC1
PLUSW1
Uses contents of FSR1 to address data memory - value of FSR1 pre-incremented (not a physical register)
n/a
n/a
58
58
Uses contents of FSR1 to address data memory - value of FSR1 pre-incremented
(not a physical register) - value of FSR1 offset by value in WREG
FSR1H
FSR1L
BSR
—
—
—
—
Indirect Data Memory Address Pointer 1 High Byte ---- 0000 35, 58
xxxx xxxx 35, 58
Indirect Data Memory Address Pointer 1 Low Byte
—
—
—
—
Bank Select Register
---- 0000 35, 57
INDF2
Uses contents of FSR2 to address data memory - value of FSR2 not changed (not a physical register)
n/a
n/a
58
58
POSTINC2 Uses contents of FSR2 to address data memory - value of FSR2 post-incremented
(not a physical register)
POSTDEC2 Uses contents of FSR2 to address data memory - value of FSR2 post-decremented
(not a physical register)
n/a
58
Legend:
x= unknown, u= unchanged, - = unimplemented, q= value depends on condition
Note 1:
RA6 and associated bits are configured as port pins in RCIO and ECIO Oscillator mode only and read ‘0’ in all other
Oscillator modes.
2:
3:
4:
Bit 21 of the TBLPTRU allows access to the device configuration bits.
These registers are unused on PIC18F6X2X devices; always maintain these clear.
RG5 is available only if MCLR function is disabled in configuration.
2003 Microchip Technology Inc.
Advance Information
DS39612A-page 53
PIC18F6X2X/8X2X
TABLE 4-3:
REGISTER FILE SUMMARY (CONTINUED)
Value on
POR, BOR on page:
Details
File Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PREINC2
PLUSW2
Uses contents of FSR2 to address data memory - value of FSR2 pre-incremented
(not a physical register)
n/a
n/a
58
58
Uses contents of FSR2 to address data memory - value of FSR2 pre-incremented
(not a physical register) - value of FSR2 offset by value in WREG
FSR2H
—
—
—
—
Indirect Data Memory Address Pointer 2 High Byte ---- 0000 35, 58
xxxx xxxx 35, 58
FSR2L
Indirect Data Memory Address Pointer 2 Low Byte
STATUS
TMR0H
TMR0L
—
—
—
N
OV
Z
DC
C
---x xxxx 35, 60
0000 0000 35, 135
xxxx xxxx 35, 135
1111 1111 35, 133
---- ---0 25, 35
--00 0101 35, 255
Timer0 Register High Byte
Timer0 Register Low Byte
T0CON
OSCCON
LVDCON
WDTCON
RCON
TMR0ON
T08BIT
—
T0CS
—
T0SE
—
PSA
—
T0PS2
—
T0PS1
—
T0PS0
SCS
—
—
—
IRVST
—
LVDEN
—
LVDL3
—
LVDL2
—
LVDL1
—
LVDL0
—
—
SWDTE ---- ---0 35, 269
IPEN
—
—
RI
TO
PD
POR
BOR
0--1 11qq 35, 61,
103
TMR1H
Timer1 Register High Byte
Timer1 Register Low Byte
xxxx xxxx 35, 141
xxxx xxxx 35, 141
TMR1L
T1CON
RD16
—
T1CKPS1
T1CKPS0 T1OSCEN T1SYNC
TMR1CS
TMR1ON 0-00 0000 35, 141
0000 0000 35, 144
TMR2
Timer2 Register
PR2
Timer2 Period Register
1111 1111 35, 144
T2CON
—
T2OUTPS3 T2OUTPS2 T2OUTPS1 T2OUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 35, 144
SSPBUF
SSPADD
SSPSTAT
SSPCON1
SSPCON2
ADRESH
ADRESL
ADCON0
ADCON1
ADCON2
CCPR1H
CCPR1L
CCP1CON
CCPR2H
CCPR2L
CCP2CON
CCPR3H
CCPR3L
CCP3CON
SSP Receive Buffer/Transmit Register
2
xxxx xxxx 35, 183
0000 0000 35, 183
0000 0000 35, 176
0000 0000 35, 177
0000 0000 35, 187
xxxx xxxx 36, 242
xxxx xxxx 36, 242
--00 0000 36, 235
--00 0000 36, 236
0-00 0000 36, 237
xxxx xxxx 36, 174
xxxx xxxx 36, 174
2
SSP Address Register in I C Slave mode. SSP Baud Rate Reload Register in I C Master mode.
SMP
WCOL
GCEN
CKE
D/A
P
S
R/W
SSPM2
PEN
UA
BF
SSPOV
ACKSTAT
SSPEN
ACKDT
CKP
SSPM3
RCEN
SSPM1
RSEN
SSPM0
SEN
ACKEN
A/D Result Register High Byte
A/D Result Register Low Byte
—
—
—
—
—
CHS3
VCFG1
ACQT2
CHS2
VCFG0
ACQT1
CHS1
PCFG3
ACQT0
CHS0
PCFG2
ADCS2
GO/DONE
PCFG1
ADON
PCFG0
ADCS0
ADFM
ADCS1
Enhanced Capture/Compare/PWM Register 1 High Byte
Enhanced Capture/Compare/PWM Register 1 Low Byte
P1M1
P1M0
DC1B1
DC1B0
CCP1M3
CCP2M3
CCP3M3
CCP1M2
CCP2M2
CCP3M2
CCP1M1
CCP2M1
CCP3M1
CCP1M0 0000 0000 36, 159
xxxx xxxx 36, 174
Enhanced Capture/Compare/PWM Register 2 High Byte
Enhanced Capture/Compare/PWM Register 2 Low Byte
xxxx xxxx 36, 174
P2M1
P2M0
DC2B1
DC2B0
CCP2M0 0000 0000 36, 159
xxxx xxxx 36, 174
Enhanced Capture/Compare/PWM Register 3 High Byte
Enhanced Capture/Compare/PWM Register 3 Low Byte
xxxx xxxx 36, 174
P3M1
P3M0
CCP3X
CCP3Y
CCP3M0 0000 0000 36, 159
ECCP1AS ECCP1ASE ECCP1AS2 ECCP1AS1 ECCP1AS0 PSS1AC1 PSS1AC0 PSS1BD1 PSS1BD0 0000 0000 36, 171
CVRCON
CVREN
CVROE
CVRR
CVRSS
CVR3
CVR2
CVR1
CVR0
0000 0000 36, 249
Legend:
x= unknown, u= unchanged, - = unimplemented, q= value depends on condition
Note 1:
RA6 and associated bits are configured as port pins in RCIO and ECIO Oscillator mode only and read ‘0’ in all other
Oscillator modes.
2:
3:
4:
Bit 21 of the TBLPTRU allows access to the device configuration bits.
These registers are unused on PIC18F6X2X devices; always maintain these clear.
RG5 is available only if MCLR function is disabled in configuration.
DS39612A-page 54
Advance Information
2003 Microchip Technology Inc.
PIC18F6X2X/8X2X
TABLE 4-3:
File Name
REGISTER FILE SUMMARY (CONTINUED)
Value on
POR, BOR on page:
Details
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
CMCON
C2OUT
C1OUT
C2INV
C1INV
CIS
CM2
CM1
CM0
0000 0000 36, 243
xxxx xxxx 36, 147
xxxx xxxx 36, 147
TMR3H
TMR3L
T3CON
PSPCON
SPBRG1
RCREG1
TXREG1
TXSTA1
RCSTA1
EEADRH
EEADR
EEDATA
EECON2
EECON1
IPR3
Timer3 Register High Byte
Timer3 Register Low Byte
RD16
IBF
T3CCP2
OBF
T3CKPS1
IBOV
T3CKPS0
T3CCP1
—
T3SYNC
—
TMR3CS
—
TMR3ON 0000 0000 36, 147
PSPMODE
—
0000 ---- 36, 131
0000 0000 36, 219
0000 0000 36, 226
0000 0000 36, 224
0000 -010 36, 216
0000 000x 36, 217
USART1 Baud Rate Generator
USART1 Receive Register
USART1 Transmit Register
CSRC
SPEN
—
TX9
RX9
—
TXEN
SREN
—
SYNC
CREN
—
—
ADDEN
—
BRGH
FERR
—
TRMT
OERR
TX9D
RX9D
EE Adr Register High ---- --00 36, 85
0000 0000 36, 85
Data EEPROM Address Register
Data EEPROM Data Register
0000 0000 36, 85
Data EEPROM Control Register 2 (not a physical register)
---- ---- 36, 85
EEPGD
—
CFGS
—
—
RC2IP
RC2IF
RC2IE
—
FREE
TX2IP
TX2IF
TX2IE
EEIP
EEIF
WRERR
TMR4IP
TMR4IF
TMR4IE
BCLIP
BCLIF
BCLIE
SSPIP
SSPIF
SSPIE
—
WREN
CCP5IP
CCP5IF
CCP5IE
LVDIP
WR
RD
xx-0 x000 36, 82
CCP4IP
CCP4IF
CCP4IE
TMR3IP
TMR3IF
TMR3IE
TMR2IP
TMR2IF
TMR2IE
WM1
CCP3IP --11 1111 37, 102
CCP3IF --00 0000 37, 96
CCP3IE --00 0000 37, 99
CCP2IP -1-1 1111 37, 101
CCP2IF -0-0 0000 37, 95
CCP2IE -0-0 0000 37, 98
TMR1IP 1111 1111 37, 100
TMR1IF 0000 0000 37, 94
TMR1IE 0000 0000 37, 97
PIR3
—
—
PIE3
—
—
IPR2
—
CMIP
CMIF
CMIE
ADIP
ADIF
ADIE
—
PIR2
—
—
LVDIF
PIE2
—
—
EEIE
TXIP
LVDIE
IPR1
PSPIP
PSPIF
PSPIE
EBDIS
RCIP
RCIF
RCIE
WAIT1
CCP1IP
CCP1IF
CCP1IE
—
PIR1
TXIF
PIE1
TXIE
(3)
MEMCON
WAIT0
WM0
0-00 --00 37, 73
1111 1111 37, 129
1111 1111 37, 126
---1 1111 37, 121
1111 1111 37, 118
1111 1111 37, 115
1111 1111 37, 112
1111 1111 37, 110
1111 1111 37, 107
-111 1111 37, 123
xxxx xxxx 37, 129
xxxx xxxx 37, 126
---x xxxx 37, 123
xxxx xxxx 37, 121
xxxx xxxx 37, 118
xxxx xxxx 37, 115
xxxx xxxx 37, 112
xxxx xxxx 37, 110
-xxx xxxx 37, 107
(3)
TRISJ
Data Direction Control Register for PORTJ
Data Direction Control Register for PORTH
(3)
TRISH
TRISG
TRISF
TRISE
TRISD
TRISC
TRISB
TRISA
—
—
—
Data Direction Control Register for PORTG
Data Direction Control Register for PORTF
Data Direction Control Register for PORTE
Data Direction Control Register for PORTD
Data Direction Control Register for PORTC
Data Direction Control Register for PORTB
(1)
—
TRISA6
Data Direction Control Register for PORTA
(3)
LATJ
Read PORTJ Data Latch, Write PORTJ Data Latch
Read PORTH Data Latch, Write PORTH Data Latch
(3)
LATH
LATG
LATF
LATE
LATD
LATC
LATB
LATA
—
—
—
Read PORTG Data Latch, Write PORTG Data Latch
Read PORTF Data Latch, Write PORTF Data Latch
Read PORTE Data Latch, Write PORTE Data Latch
Read PORTD Data Latch, Write PORTD Data Latch
Read PORTC Data Latch, Write PORTC Data Latch
Read PORTB Data Latch, Write PORTB Data Latch
(1)
(1)
—
LATA6
Read PORTA Data Latch, Write PORTA Data Latch
Legend:
x= unknown, u= unchanged, - = unimplemented, q= value depends on condition
Note 1:
RA6 and associated bits are configured as port pins in RCIO and ECIO Oscillator mode only and read ‘0’ in all other
Oscillator modes.
2:
3:
4:
Bit 21 of the TBLPTRU allows access to the device configuration bits.
These registers are unused on PIC18F6X2X devices; always maintain these clear.
RG5 is available only if MCLR function is disabled in configuration.
2003 Microchip Technology Inc.
Advance Information
DS39612A-page 55
PIC18F6X2X/8X2X
TABLE 4-3:
REGISTER FILE SUMMARY (CONTINUED)
Value on
POR, BOR on page:
Details
File Name
(3)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PORTJ
PORTH
Read PORTJ pins, Write PORTJ Data Latch
xxxx xxxx 38, 129
xxxx xxxx 38, 126
--0x xxxx 38, 123
(3)
Read PORTH pins, Write PORTH Data Latch
(4)
PORTG
—
—
Read PORTG pins, Write PORTG Data Latch
RG5
PORTF
PORTE
PORTD
PORTC
PORTB
PORTA
Read PORTF pins, Write PORTF Data Latch
Read PORTE pins, Write PORTE Data Latch
Read PORTD pins, Write PORTD Data Latch
Read PORTC pins, Write PORTC Data Latch
xxxx xxxx 38, 121
xxxx xxxx 38, 118
xxxx xxxx 38, 115
xxxx xxxx 38, 112
xxxx xxxx 38, 110
-x0x 0000 38, 107
0000 0000 38, 219
Read PORTB pins, Write PORTB Data Latch
(1)
(1)
—
RA6
Read PORTA pins, Write PORTA Data Latch
SPBRGH1 Enhanced USART1 Baud Rate Generator High Byte
BAUDCON1 RCIDL SCKP
SPBRGH2 Enhanced USART2 Baud Rate Generator High Byte
—
—
BRG16
—
WUE
ABDEN -1-1 0-00 38, 218
0000 0000 38, 219
BAUDCON2
—
RCIDL
P1DC6
—
SCKP
BRG16
P1DC3
—
WUE
ABDEN -1-0 0-00 38, 218
ECCP1DEL P1RSEN
P1DC5
P1DC4
P1DC2
P1DC1
P1DC0
0000 0000 38, 170
0000 0000 38, 150
1111 1111 38, 150
TMR4
Timer4 Register
PR4
Timer4 Period Register
T4CON
—
TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR4ON T4CKPS1 T4CKPS0 -000 0000 38, 149
CCPR4H
CCPR4L
CCP4CON
CCPR5H
CCPR5L
CCP5CON
SPBRG2
RCREG2
TXREG2
TXSTA2
RCSTA2
Capture/Compare/PWM Register 4 High Byte
Capture/Compare/PWM Register 4 Low Byte
xxxx xxxx 38, 155
xxxx xxxx 38, 155
—
—
CCPxX
CCPxY
CCPxM3
CCPxM3
CCPxM2
CCPxM2
CCPxM1
CCPxM1
CCPxM0 --00 0000 38, 151
xxxx xxxx 38, 155
Capture/Compare/PWM Register 5 High Byte
Capture/Compare/PWM Register 5 Low Byte
xxxx xxxx 38, 155
—
—
CCPxX
CCPxY
CCPxM0 --00 0000 38, 151
0000 0000 38, 219
USART2 Baud Rate Generator
USART2 Receive Register
USART2 Transmit Register
0000 0000 38, 226
0000 0000 38, 224
CSRC
SPEN
TX9
RX9
TXEN
SREN
SYNC
CREN
SENDB
ADEN
BRGH
FERR
TRMT
OERR
TX9D
RX9D
0000 -010 38, 224
0000 000x 38, 224
ECCP3AS ECCP3ASE ECCP3AS2 ECCP3AS1 ECCP3AS0 PSS3AC1 PSS3AC0 PSS3BD1 PSS3BD0 0000 0000 38, 171
ECCP3DEL P3RSEN P3DC6 P3DC5 P3DC4 P3DC3 P3DC2 P3DC1 P3DC0 0000 0000 38, 170
ECCP2AS ECCP2ASE ECCP2AS2 ECCP2AS1 ECCP2AS0 PSS2AC1 PSS2AC0 PSS2BD1 PSS2BD0 0000 0000 38, 171
ECCP2DEL P2RSEN P2DC6 P2DC5 P2DC4 P2DC3 P2DC2 P2DC1 P2DC0 0000 0000 38, 170
x= unknown, u= unchanged, - = unimplemented, q= value depends on condition
Legend:
Note 1:
RA6 and associated bits are configured as port pins in RCIO and ECIO Oscillator mode only and read ‘0’ in all other
Oscillator modes.
2:
3:
4:
Bit 21 of the TBLPTRU allows access to the device configuration bits.
These registers are unused on PIC18F6X2X devices; always maintain these clear.
RG5 is available only if MCLR function is disabled in configuration.
DS39612A-page 56
Advance Information
2003 Microchip Technology Inc.
PIC18F6X2X/8X2X
4.10
Access Bank
4.11 Bank Select Register (BSR)
The Access Bank is an architectural enhancement,
which is very useful for C compiler code optimization.
The techniques used by the C compiler may also be
useful for programs written in assembly.
The need for a large general purpose memory space
dictates a RAM banking scheme. The data memory is
partitioned into sixteen banks. When using direct
addressing, the BSR should be configured for the
desired bank.
This data memory region can be used for:
BSR<3:0> holds the upper 4 bits of the 12-bit RAM
address. The BSR<7:4> bits will always read ‘0’s, and
writes will have no effect.
• Intermediate computational values
• Local variables of subroutines
• Faster context saving/switching of variables
• Common variables
A
MOVLB instruction has been provided in the
instruction set to assist in selecting banks.
• Faster evaluation/control of SFRs (no banking)
If the currently selected bank is not implemented, any
read will return all ‘0’s and all writes are ignored. The
STATUS register bits will be set/cleared as appropriate
for the instruction performed.
The Access Bank is comprised of the upper 160 bytes
in Bank 15 (SFRs) and the lower 96 bytes in Bank 0.
These two sections will be referred to as Access RAM
High and Access RAM Low, respectively. Figure 4-7
indicates the Access RAM areas.
Each Bank extends up to FFh (256 bytes). All data
memory is implemented as static RAM.
A bit in the instruction word specifies if the operation is
to occur in the bank specified by the BSR register or in
the Access Bank. This bit is denoted by the ‘a’ bit (for
access bit).
A MOVFFinstruction ignores the BSR since the 12-bit
addresses are embedded into the instruction word.
Section 4.12 provides a description of indirect address-
ing which allows linear addressing of the entire RAM
space.
When forced in the Access Bank (a = 0), the last
address in Access RAM Low is followed by the first
address in Access RAM High. Access RAM High maps
the Special Function Registers so that these registers
can be accessed without any software overhead. This is
useful for testing status flags and modifying control bits.
FIGURE 4-8:
DIRECT ADDRESSING
Direct Addressing
(3)
From Opcode
BSR<3:0>
7
0
(2)
(3)
Bank Select
Location Select
00h
01h
100h
0Eh
E00h
0Fh
F00h
000h
Data
Memory(1)
0FFh
1FFh
EFFh
FFFh
Bank 0
Bank 1
Bank 14 Bank 15
Note 1: For register file map detail, see Table 4-2.
2: The access bit of the instruction can be used to force an override of the selected bank (BSR<3:0>) to the
registers of the Access Bank.
3: The MOVFFinstruction embeds the entire 12-bit address in the instruction.
2003 Microchip Technology Inc.
Advance Information
DS39612A-page 57
PIC18F6X2X/8X2X
If INDF0, INDF1, or INDF2 are read indirectly via an
FSR, all ‘0’s are read (zero bit is set). Similarly, if
INDF0, INDF1, or INDF2 are written to indirectly, the
operation will be equivalent to a NOPinstruction and the
STATUS bits are not affected.
4.12 Indirect Addressing, INDF and
FSR Registers
Indirect addressing is a mode of addressing data mem-
ory, where the data memory address in the instruction
is not fixed. An FSR register is used as a pointer to the
data memory location that is to be read or written. Since
this pointer is in RAM, the contents can be modified by
the program. This can be useful for data tables in the
data memory and for software stacks. Figure 4-9
shows the operation of indirect addressing. This shows
the moving of the value to the data memory address
specified by the value of the FSR register.
4.12.1
INDIRECT ADDRESSING
OPERATION
Each FSR register has an INDF register associated
with it, plus four additional register addresses. Perform-
ing an operation on one of these five registers deter-
mines how the FSR will be modified during indirect
addressing.
Indirect addressing is possible by using one of the INDF
registers. Any instruction using the INDF register actu-
ally accesses the register pointed to by the File Select
Register, FSR. Reading the INDF register itself indirectly
(FSR = 0), will read 00h. Writing to the INDF register
indirectly, results in a no operation. The FSR register
contains a 12-bit address which is shown in Figure 4-10.
When data access is done to one of the five INDFn
locations, the address selected will configure the FSRn
register to:
• Do nothing to FSRn after an indirect access (no
change) - INDFn.
• Auto-decrement FSRn after an indirect access
(post-decrement) - POSTDECn.
The INDFn register is not a physical register. Address-
ing INDFn actually addresses the register whose
address is contained in the FSRn register (FSRn is a
pointer). This is indirect addressing.
• Auto-increment FSRn after an indirect access
(post-increment) - POSTINCn.
• Auto-increment FSRn before an indirect access
(pre-increment) - PREINCn.
Example 4-4 shows a simple use of indirect addressing
to clear the RAM in Bank 1 (locations 100h-1FFh) in a
minimum number of instructions.
• Use the value in the WREG register as an offset
to FSRn. Do not modify the value of the WREG or
the FSRn register after an indirect access (no
change) - PLUSWn.
EXAMPLE 4-4:
HOW TO CLEAR RAM
(BANK 1) USING
When using the auto-increment or auto-decrement fea-
tures, the effect on the FSR is not reflected in the
STATUS register. For example, if the indirect address
causes the FSR to equal ‘0’, the Z bit will not be set.
INDIRECT ADDRESSING
LFSR FSR0 ,0x100
CLRF POSTINC0
;
NEXT
; Clear INDF
; register and
; inc pointer
; All done with
; Bank1?
Incrementing or decrementing an FSR affects all 12
bits. That is, when FSRnL overflows from an increment,
FSRnH will be incremented automatically.
BTFSS FSR0H, 1
GOTO NEXT
; NO, clear next
; YES, continue
Adding these features allows the FSRn to be used as a
stack pointer in addition to its uses for table operations
in data memory.
CONTINUE
There are three indirect addressing registers. To
address the entire data memory space (4096 bytes),
these registers are 12 bits wide. To store the 12 bits of
addressing information, two 8-bit registers are
required. These indirect addressing registers are:
Each FSR has an address associated with it that per-
forms an indexed indirect access. When a data access
to this INDFn location (PLUSWn) occurs, the FSRn is
configured to add the signed value in the WREG regis-
ter and the value in FSR to form the address before an
indirect access. The FSR value is not changed.
1. FSR0: composed of FSR0H:FSR0L
2. FSR1: composed of FSR1H:FSR1L
3. FSR2: composed of FSR2H:FSR2L
If an FSR register contains a value that points to one of
the INDFn, an indirect read will read 00h (zero bit is
set), while an indirect write will be equivalent to a NOP
(STATUS bits are not affected).
In addition, there are registers INDF0, INDF1 and
INDF2, which are not physically implemented. Reading
or writing to these registers activates indirect address-
ing, with the value in the corresponding FSR register
being the address of the data. If an instruction writes a
value to INDF0, the value will be written to the address
pointed to by FSR0H:FSR0L. A read from INDF1 reads
the data from the address pointed to by
FSR1H:FSR1L. INDFn can be used in code anywhere
an operand can be used.
If an indirect addressing operation is done where the
target address is an FSRnH or FSRnL register,
the write operation will dominate over the pre- or
post-increment/decrement functions.
DS39612A-page 58
Advance Information
2003 Microchip Technology Inc.
PIC18F6X2X/8X2X
FIGURE 4-9:
INDIRECT ADDRESSING OPERATION
0h
RAM
Instruction
Executed
Opcode
Address
12
FFFh
File Address = Access of an Indirect Addressing Register
BSR<3:0>
12
8
12
Instruction
Fetched
4
Opcode
File
FSR
FIGURE 4-10:
INDIRECT ADDRESSING
Indirect Addressing
11
FSR Register
0
Location Select
0000h
Data
Memory(1)
0FFFh
Note 1: For register file map detail, see Table 4-2.
2003 Microchip Technology Inc.
Advance Information
DS39612A-page 59
PIC18F6X2X/8X2X
For example, CLRF STATUSwill clear the upper three
bits and set the Z bit. This leaves the STATUS register
as 000u u1uu(where u= unchanged).
4.13 STATUS Register
The STATUS register, shown in Register 4-3, contains
the arithmetic status of the ALU. The STATUS register
can be the destination for any instruction, as with any
other register. If the STATUS register is the destination
for an instruction that affects the Z, DC, C, OV, or N bits,
then the write to these five bits is disabled. These bits
are set or cleared according to the device logic.
Therefore, the result of an instruction with the STATUS
register as destination may be different than intended.
It is recommended, therefore, that only BCF, BSF,
SWAPF, MOVFF and MOVWF instructions are used to
alter the STATUS register because these instructions
do not affect the Z, C, DC, OV, or N bits from the
STATUS register. For other instructions not affecting
any STATUS bits, see Table 25-2.
Note:
The C and DC bits operate as a borrow
and digit borrow bit respectively, in
subtraction.
REGISTER 4-3:
STATUS REGISTER
U-0
—
U-0
—
U-0
—
R/W-x
R/W-x
OV
R/W-x
Z
R/W-x
DC
R/W-x
C
N
bit 7
bit 0
bit 7-5
bit 4
Unimplemented: Read as ‘0’
N: Negative bit
This bit is used for signed arithmetic (2’s complement). It indicates whether the result was
negative (ALU MSB = 1).
1= Result was negative
0= Result was positive
bit 3
OV: Overflow bit
This bit is used for signed arithmetic (2’s complement). It indicates an overflow of the
7-bit magnitude which causes the sign bit (bit 7) to change state.
1= Overflow occurred for signed arithmetic (in this arithmetic operation)
0= No overflow occurred
bit 2
bit 1
Z: Zero bit
1= The result of an arithmetic or logic operation is zero
0= The result of an arithmetic or logic operation is not zero
DC: Digit Carry/Borrow bit
For ADDWF, ADDLW, SUBLW, and SUBWFinstructions.
1= A carry-out from the 4th low order bit of the result occurred
0= No carry-out from the 4th low order bit of the result
Note:
For borrow, the polarity is reversed. A subtraction is executed by adding the two’s
complement of the second operand. For rotate (RRF, RLF) instructions, this bit is
loaded with either bit 4 or bit 3 of the source register.
bit 0
C: Carry/Borrow bit
For ADDWF, ADDLW, SUBLW, and SUBWFinstructions.
1= A carry-out from the Most Significant bit of the result occurred
0= No carry-out from the Most Significant bit of the result occurred
Note:
For borrow, the polarity is reversed. A subtraction is executed by adding the two’s
complement of the second operand. For rotate (RRF, RLF) instructions, this bit is
loaded with either the high or low order bit of the source register.
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
- n = Value at POR
DS39612A-page 60
Advance Information
2003 Microchip Technology Inc.
PIC18F6X2X/8X2X
4.14 RCON Register
Note:
It is recommended that the POR bit be set
after Power-on Reset has been
detected, so that subsequent Power-on
Resets may be detected.
a
The Reset Control (RCON) register contains flag bits
that allow differentiation between the sources of a
device RESET. These flags include the TO, PD, POR,
BOR and RI bits. This register is readable and writable.
REGISTER 4-4:
RCON REGISTER
R/W-0
IPEN
U-0
—
U-0
—
R/W-1
RI
R/W-1
TO
R/W-1
PD
R/W-0
POR
R/W-0
BOR
bit 7
bit 0
bit 7
IPEN: Interrupt Priority Enable bit
1= Enable priority levels on interrupts
0= Disable priority levels on interrupts (PIC16CXXX Compatibility mode)
bit 6-5 Unimplemented: Read as ‘0’
bit 4
RI: RESETInstruction Flag bit
1= The RESETinstruction was not executed
0= The RESETinstruction was executed causing a device RESET
(must be set in software after a Brown-out Reset occurs)
bit 3
bit 2
bit 1
TO: Watchdog Time-out Flag bit
1= After power-up, CLRWDTinstruction, or SLEEPinstruction
0= A WDT time-out occurred
PD: Power-down Detection Flag bit
1= After power-up or by the CLRWDTinstruction
0= By execution of the SLEEPinstruction
POR: Power-on Reset Status bit
1= A Power-on Reset has not occurred
0= A Power-on Reset occurred
(must be set in software after a Power-on Reset occurs)
bit 0
BOR: Brown-out Reset Status bit
1= A Brown-out Reset has not occurred
0= A Brown-out Reset occurred
(must be set in software after a Brown-out Reset occurs)
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
- n = Value at POR
2003 Microchip Technology Inc.
Advance Information
DS39612A-page 61
PIC18F6X2X/8X2X
NOTES:
DS39612A-page 62
Advance Information
2003 Microchip Technology Inc.
PIC18F6X2X/8X2X
5.1
Table Reads and Table Writes
5.0
FLASH PROGRAM MEMORY
In order to read and write program memory, there are
two operations that allow the processor to move bytes
between the program memory space and the data RAM:
The FLASH program memory is readable, writable, and
erasable, during normal operation over the entire VDD
range.
• Table Read (TBLRD)
• Table Write (TBLWT)
A read from program memory is executed on one byte
at a time. A write to program memory is executed on
blocks of 8 bytes at a time. Program memory is erased
in blocks of 64 bytes at a time. A bulk erase operation
may not be issued from user code.
The program memory space is 16 bits wide, while the
data RAM space is 8 bits wide. Table reads and table
writes move data between these two memory spaces
through an 8-bit register (TABLAT).
Writing or erasing program memory will cease instruc-
tion fetches until the operation is complete. The pro-
gram memory cannot be accessed during the write or
erase, therefore, code cannot execute. An internal
programming timer terminates program memory writes
and erases.
Table read operations retrieve data from program
memory and places it into the data RAM space.
Figure 5-1 shows the operation of a table read with
program memory and data RAM.
Table write operations store data from the data memory
space into holding registers in program memory. The
procedure to write the contents of the holding registers
into program memory is detailed in Section 5.5, “Writing
to FLASH Program Memory”. Figure 5-2 shows the
operation of a table write with program memory and data
RAM.
A value written to program memory does not need to be
a valid instruction. Executing a program memory
location that forms an invalid instruction results in a
NOP.
Table operations work with byte entities. A table block
containing data, rather than program instructions, is not
required to be word aligned. Therefore, a table block can
start and end at any byte address. If a table write is being
used to write executable code into program memory,
program instructions will need to be word aligned.
FIGURE 5-1:
TABLE READ OPERATION
Instruction: TBLRD*
Program Memory
(1)
Table Pointer
Table Latch (8-bit)
TABLAT
TBLPTRU TBLPTRH TBLPTRL
Program Memory
(TBLPTR)
Note 1: Table Pointer register points to a byte in program memory.
2003 Microchip Technology Inc.
Advance Information
DS39612A-page 63
PIC18F6X2X/8X2X
FIGURE 5-2:
TABLE WRITE OPERATION
Instruction: TBLWT*
Program Memory
Holding Registers
(1)
Table Pointer
Table Latch (8-bit)
TABLAT
TBLPTRU TBLPTRH TBLPTRL
Program Memory
(TBLPTR)
Note 1: Table pointer actually points to one of eight holding registers, the address of which is determined by
TBLPTRL<2:0>. The process for physically writing data to the program memory array is discussed in
Section 5.5.
The FREE bit, when set, will allow a program memory
erase operation. When the FREE bit is set, the erase
operation is initiated on the next WR command. When
FREE is clear, only writes are enabled.
5.2
Control Registers
Several control registers are used in conjunction with
the TBLRDand TBLWTinstructions. These include the:
• EECON1 register
• EECON2 register
• TABLAT register
• TBLPTR registers
The WREN bit, when set, will allow a write operation.
On power-up, the WREN bit is clear. The WRERR bit is
set when a write operation is interrupted by a MCLR
Reset or a WDT Time-out Reset during normal opera-
tion. In these situations, the user can check the
WRERR bit and rewrite the location. It is necessary to
reload the data and address registers (EEDATA and
EEADR) due to RESET values of zero.
5.2.1
EECON1 AND EECON2 REGISTERS
EECON1 is the control register for memory accesses.
EECON2 is not a physical register. Reading EECON2
will read all ‘0’s. The EECON2 register is used
exclusively in the memory write and erase sequences.
The WR control bit initiates write operations. The bit
cannot be cleared, only set, in software; it is cleared in
hardware at the completion of the write operation. The
inability to clear the WR bit in software prevents the
Control bit EEPGD determines if the access will be a
program or data EEPROM memory access. When
clear, any subsequent operations will operate on the
data EEPROM memory. When set, any subsequent
operations will operate on the program memory.
accidental or premature termination of
operation.
a write
Note:
Interrupt flag bit, EEIF in the PIR2 register,
is set when the write is complete. It must
be cleared in software.
Control bit CFGS determines if the access will be to the
configuration/calibration registers or to program
memory/data EEPROM memory. When set,
subsequent operations will operate on configuration
registers regardless of EEPGD (see Section 24.0,
“Special Features of the CPU”). When clear, memory
selection access is determined by EEPGD.
DS39612A-page 64
Advance Information
2003 Microchip Technology Inc.
PIC18F6X2X/8X2X
REGISTER 5-1:
EECON1 REGISTER (ADDRESS FA6h)
R/W-x
R/W-x
CFGS
U-0
—
R/W-0
FREE
R/W-x
R/W-0
WREN
R/S-0
WR
R/S-0
RD
EEPGD
WRERR
bit 7
bit 0
bit 7
bit 6
EEPGD: FLASH Program or Data EEPROM Memory Select bit
1= Access FLASH program memory
0= Access data EEPROM memory
CFGS: FLASH Program/Data EEPROM or Configuration Select bit
1= Access Configuration registers
0= Access FLASH program or data EEPROM memory
bit 5
bit 4
Unimplemented: Read as ‘0’
FREE: FLASH Row Erase Enable bit
1= Erase the program memory row addressed by TBLPTR on the next WR command
(cleared by completion of erase operation)
0= Perform write only
bit 3
WRERR: FLASH Program/Data EEPROM Error Flag bit
1= A write operation is prematurely terminated
(any RESET during self-timed programming in normal operation)
0= The write operation completed
Note:
When a WRERR occurs, the EEPGD and CFGS bits are not cleared. This allows
tracing of the error condition.
bit 2
bit 1
WREN: FLASH Program/Data EEPROM Write Enable bit
1= Allows write cycles to FLASH program/data EEPROM
0= Inhibits write cycles to FLASH program/data EEPROM
WR: Write Control bit
1= Initiates a data EEPROM erase/write cycle or a program memory erase cycle or write cycle.
(The operation is self-timed and the bit is cleared by hardware once write is complete. The
WR bit can only be set (not cleared) in software.)
0= Write cycle to the EEPROM is complete
bit 0
RD: Read Control bit
1= Initiates an EEPROM read
(Read takes one cycle. RD is cleared in hardware. The RD bit can only be set (not cleared)
in software. RD bit cannot be set when EEPGD = 1.)
0= Does not initiate an EEPROM read
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
- n = Value at POR
2003 Microchip Technology Inc.
Advance Information
DS39612A-page 65
PIC18F6X2X/8X2X
5.2.2
TABLAT - TABLE LATCH REGISTER
5.2.4
TABLE POINTER BOUNDARIES
The Table Latch (TABLAT) is an 8-bit register mapped
into the SFR space. The Table Latch register is used to
hold 8-bit data during data transfers between program
memory and data RAM.
TBLPTR is used in reads, writes, and erases of the
FLASH program memory.
When a TBLRDis executed, all 22 bits of the TBLPTR
determine which byte is read from program memory
into TABLAT.
5.2.3
TBLPTR - TABLE POINTER
REGISTER
When a TBLWTis executed, the three LSbs of the Table
Pointer register (TBLPTR<2:0>) determine which of the
eight program memory holding registers is written to.
When the timed write to program memory (long write)
begins, the 19 MSbs of the TBLPTR (TBLPTR<21:3>)
will determine which program memory block of 8 bytes
is written to. For more detail, see Section 5.5, “Writing
to FLASH Program Memory”.
The Table Pointer register (TBLPTR) addresses a byte
within the program memory. The TBLPTR is comprised
of three SFR registers: Table Pointer Upper Byte, Table
Pointer High Byte and Table Pointer Low Byte
(TBLPTRU:TBLPTRH:TBLPTRL). These three regis-
ters join to form a 22-bit wide pointer. The low order
21 bits allow the device to address up to 2 Mbytes of
program memory space. The 22nd bit allows access to
the device ID, the user ID and the configuration bits.
When an erase of program memory is executed, the
16 MSbs of the Table Pointer register (TBLPTR<21:6>)
point to the 64-byte block that will be erased. The Least
Significant bits (TBLPTR<5:0>) are ignored.
The table pointer, TBLPTR, is used by the TBLRDand
TBLWTinstructions. These instructions can update the
TBLPTR in one of four ways based on the table opera-
tion. These operations are shown in Table 5-1. These
operations on the TBLPTR only affect the low order
21 bits.
Figure 5-3 describes the relevant boundaries of
TBLPTR based on FLASH program memory
operations.
TABLE 5-1:
Example
TABLE POINTER OPERATIONS WITH TBLRD AND TBLWT INSTRUCTIONS
Operation on Table Pointer
TBLRD*
TBLWT*
TBLPTR is not modified
TBLRD*+
TBLWT*+
TBLPTR is incremented after the read/write
TBLPTR is decremented after the read/write
TBLPTR is incremented before the read/write
TBLRD*-
TBLWT*-
TBLRD+*
TBLWT+*
FIGURE 5-3:
TABLE POINTER BOUNDARIES BASED ON OPERATION
21
16 15
TBLPTRH
8
7
TBLPTRL
0
TBLPTRU
ERASE - TBLPTR<20:6>
WRITE - TBLPTR<21:3>
READ - TBLPTR<21:0>
DS39612A-page 66
Advance Information
2003 Microchip Technology Inc.
PIC18F6X2X/8X2X
TBLPTR points to a byte address in program space.
Executing TBLRD places the byte pointed to into
TABLAT. In addition, TBLPTR can be modified
automatically for the next table read operation.
5.3
Reading the FLASH Program
Memory
The TBLRDinstruction is used to retrieve data from pro-
gram memory and places it into data RAM. Table reads
from program memory are performed one byte at a
time.
The internal program memory is typically organized by
words. The Least Significant bit of the address selects
between the high and low bytes of the word. Figure 5-4
shows the interface between the internal program
memory and the TABLAT.
FIGURE 5-4:
READS FROM FLASH PROGRAM MEMORY
Program Memory
(Even Byte Address)
(Odd Byte Address)
TBLPTR = xxxxx1
TBLPTR = xxxxx0
Instruction Register
(IR)
TABLAT
Read Register
FETCH
TBLRD
EXAMPLE 5-1:
READING A FLASH PROGRAM MEMORY WORD
MOVLW
MOVWF
MOVLW
MOVWF
MOVLW
MOVWF
CODE_ADDR_UPPER
TBLPTRU
CODE_ADDR_HIGH
TBLPTRH
CODE_ADDR_LOW
TBLPTRL
; Load TBLPTR with the base
; address of the word
READ_WORD
TBLRD*+
MOVF
MOVWF
; read into TABLAT and increment
; get data
TABLAT, W
WORD_EVEN
TBLRD*+
MOVFW
MOVWF
; read into TABLAT and increment
; get data
TABLAT, W
WORD_ODD
2003 Microchip Technology Inc.
Advance Information
DS39612A-page 67
PIC18F6X2X/8X2X
5.4.1
FLASH PROGRAM MEMORY
ERASE SEQUENCE
5.4
Erasing FLASH Program Memory
The minimum erase block is 32 words or 64 bytes. Only
through the use of an external programmer, or through
ICSP control, can larger blocks of program memory be
bulk erased. Word erase in the FLASH array is not
supported.
The sequence of events for erasing a block of internal
program memory location is:
1. Load Table Pointer register with address of row
being erased.
When initiating an erase sequence from the micro-
controller itself, a block of 64 bytes of program memory
is erased. The Most Significant 16 bits of the
TBLPTR<21:6> point to the block being erased.
TBLPTR<5:0> are ignored.
2. Set the EECON1 register for the erase operation:
• set EEPGD bit to point to program memory;
• clear the CFGS bit to access program memory;
• set WREN bit to enable writes;
• set FREE bit to enable the erase.
3. Disable interrupts.
The EECON1 register commands the erase operation.
The EEPGD bit must be set to point to the FLASH pro-
gram memory. The WREN bit must be set to enable
write operations. The FREE bit is set to select an erase
operation.
4. Write 55h to EECON2.
5. Write AAh to EECON2.
6. Set the WR bit. This will begin the row erase
cycle.
For protection, the write initiate sequence for EECON2
must be used.
7. The CPU will stall for duration of the erase
(about 2 ms using internal timer).
A long write is necessary for erasing the internal
FLASH. Instruction execution is halted while in a long
write cycle. The long write will be terminated by the
internal programming timer.
8. Re-enable interrupts.
EXAMPLE 5-2:
ERASING A FLASH PROGRAM MEMORY ROW
MOVLW
MOVWF
MOVLW
MOVWF
MOVLW
MOVWF
CODE_ADDR_UPPER
TBLPTRU
CODE_ADDR_HIGH
TBLPTRH
CODE_ADDR_LOW
TBLPTRL
; load TBLPTR with the base
; address of the memory block
ERASE_ROW
BSF
BCF
BSF
BSF
EECON1,EEPGD
EECON1,CFGS
EECON1,WREN
EECON1,FREE
INTCON,GIE
55h
EECON2
AAh
EECON2
EECON1,WR
INTCON,GIE
; point to FLASH program memory
; access FLASH program memory
; enable write to memory
; enable Row Erase operation
; disable interrupts
BCF
Required
Sequence
MOVLW
MOVWF
MOVLW
MOVWF
BSF
; write 55H
; write AAH
; start erase (CPU stall)
; re-enable interrupts
BSF
DS39612A-page 68
Advance Information
2003 Microchip Technology Inc.
PIC18F6X2X/8X2X
the holding registers are written. At the end of updating
8 registers, the EECON1 register must be written to, to
start the programming operation with a long write.
5.5
Writing to FLASH Program
Memory
The minimum programming block is 4 words or 8 bytes.
Word or byte programming is not supported.
The long write is necessary for programming the inter-
nal FLASH. Instruction execution is halted while in a
long write cycle. The long write will be terminated by
the internal programming timer.
Table writes are used internally to load the holding
registers needed to program the FLASH memory.
There are 8 holding registers used by the Table Writes
for programming.
The EEPROM on-chip timer controls the write time.
The write/erase voltages are generated by an on-chip
charge pump, rated to operate over the voltage range
of the device for byte or word operations.
Since the Table Latch (TABLAT) is only a single byte,
the TBLWT instruction has to be executed 8 times for
each programming operation. All of the table write
operations will essentially be short writes because only
FIGURE 5-5:
TABLE WRITES TO FLASH PROGRAM MEMORY
TABLAT
Write Register
8
8
8
8
TBLPTR = xxxxx0
TBLPTR = xxxxx2
TBLPTR = xxxxx7
Holding Register
TBLPTR = xxxxx1
Holding Register
Holding Register
Holding Register
Program Memory
8. Disable interrupts.
5.5.1
FLASH PROGRAM MEMORY WRITE
SEQUENCE
9. Write 55h to EECON2.
10. Write AAh to EECON2.
The sequence of events for programming an internal
program memory location should be:
11. Set the WR bit. This will begin the write cycle.
12. The CPU will stall for duration of the write (about
2 ms using internal timer).
1. Read 64 bytes into RAM.
2. Update data values in RAM as necessary.
13. Re-enable interrupts.
3. Load Table Pointer register with address being
erased.
14. Repeat steps 6-14 seven times to write 64 bytes.
15. Verify the memory (table read).
4. Do the row erase procedure.
5. Load Table Pointer register with address of first
byte being written.
This procedure will require about 18 ms to update one
row of 64 bytes of memory. An example of the required
code is given in Example 5-3.
6. Write the first 8 bytes into the holding registers
with auto-increment.
Note:
Before setting the WR bit, the Table
Pointer address needs to be within the
intended address range of the eight bytes
in the holding register.
7. Set the EECON1 register for the write operation:
• set EEPGD bit to point to program memory;
• clear the CFGS bit to access program memory;
• set WREN to enable byte writes.
2003 Microchip Technology Inc.
Advance Information
DS39612A-page 69
PIC18F6X2X/8X2X
EXAMPLE 5-3:
WRITING TO FLASH PROGRAM MEMORY
MOVLW
MOVWF
MOVLW
MOVWF
MOVLW
MOVWF
MOVLW
MOVWF
MOVLW
MOVWF
MOVLW
MOVWF
D'64
COUNTER
BUFFER_ADDR_HIGH
FSR0H
BUFFER_ADDR_LOW
FSR0L
CODE_ADDR_UPPER
TBLPTRU
CODE_ADDR_HIGH
TBLPTRH
CODE_ADDR_LOW
TBLPTRL
; number of bytes in erase block
; point to buffer
; Load TBLPTR with the base
; address of the memory block
READ_BLOCK
TBLRD*+
MOVF
MOVWF
; read into TABLAT, and inc
; get data
; store data
; done?
TABLAT, W
POSTINC0
DECFSZ COUNTER
BRA
READ_BLOCK
; repeat
MODIFY_WORD
MOVLW
MOVWF
MOVLW
MOVWF
MOVLW
MOVWF
MOVLW
MOVWF
DATA_ADDR_HIGH
FSR0H
DATA_ADDR_LOW
FSR0L
NEW_DATA_LOW
POSTINC0
NEW_DATA_HIGH
INDF0
; point to buffer
; update buffer word
ERASE_BLOCK
MOVLW
MOVWF
MOVLW
MOVWF
MOVLW
MOVWF
BSF
BCF
BSF
BSF
BCF
MOVLW
MOVWF
MOVLW
MOVWF
BSF
CODE_ADDR_UPPER
TBLPTRU
CODE_ADDR_HIGH
TBLPTRH
CODE_ADDR_LOW
TBLPTRL
EECON1,EEPGD
EECON1,CFGS
EECON1,WREN
EECON1,FREE
INTCON,GIE
55h
EECON2
AAh
EECON2
EECON1,WR
INTCON,GIE
; load TBLPTR with the base
; address of the memory block
; point to FLASH program memory
; access FLASH program memory
; enable write to memory
; enable Row Erase operation
; disable interrupts
Required
Sequence
; write 55H
; write AAH
; start erase (CPU stall)
; re-enable interrupts
; dummy read decrement
BSF
TBLRD*-
WRITE_BUFFER_BACK
MOVLW
8
; number of write buffer groups of 8 bytes
; point to buffer
MOVWF
MOVLW
MOVWF
MOVLW
MOVWF
COUNTER_HI
BUFFER_ADDR_HIGH
FSR0H
BUFFER_ADDR_LOW
FSR0L
PROGRAM_LOOP
MOVLW
MOVWF
8
; number of bytes in holding register
COUNTER
WRITE_WORD_TO_HREGS
MOVFW
MOVWF
TBLWT+*
POSTINC0, W
TABLAT
; get low byte of buffer data
; present data to table latch
; write data, perform a short write
; to internal TBLWT holding register.
; loop until buffers are full
DECFSZ COUNTER
BRA WRITE_WORD_TO_HREGS
DS39612A-page 70
Advance Information
2003 Microchip Technology Inc.
PIC18F6X2X/8X2X
EXAMPLE 5-3:
WRITING TO FLASH PROGRAM MEMORY (CONTINUED)
PROGRAM_MEMORY
BSF
BCF
BSF
BCF
MOVLW
MOVWF
MOVLW
MOVWF
BSF
EECON1,EEPGD
EECON1,CFGS
EECON1,WREN
INTCON,GIE
55h
EECON2
AAh
EECON2
EECON1,WR
INTCON,GIE
; point to FLASH program memory
; access FLASH program memory
; enable write to memory
; disable interrupts
Required
Sequence
; write 55H
; write AAH
; start program (CPU stall)
; re-enable interrupts
; loop until done
BSF
DECFSZ COUNTER_HI
BRA PROGRAM_LOOP
BCF
EECON1,WREN
; disable write to memory
WDT Time-out Reset during normal operation. In these
situations, users can check the WRERR bit and rewrite
the location.
5.5.2
WRITE VERIFY
Depending on the application, good programming
practice may dictate that the value written to the mem-
ory should be verified against the original value. This
should be used in applications where excessive writes
can stress bits near the specification limit.
5.5.4
PROTECTION AGAINST SPURIOUS
WRITES
To protect against spurious writes to FLASH program
memory, the write initiate sequence must also be fol-
lowed. See Section 24.0, “Special Features of the
CPU” for more detail.
5.5.3
UNEXPECTED TERMINATION OF
WRITE OPERATION
If a write is terminated by an unplanned event, such as
loss of power or an unexpected RESET, the memory
location just programmed should be verified and repro-
grammed if needed. The WRERR bit is set when a
write operation is interrupted by a MCLR Reset or a
5.6
FLASH Program Operation During
Code Protection
See Section 24.0, “Special Features of the CPU” for
details on code protection of FLASH program memory.
TABLE 5-2:
Name
REGISTERS ASSOCIATED WITH PROGRAM FLASH MEMORY
Value on
Value on:
POR, BOR
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
all other
RESETS
TBLPTRU
—
—
bit21 Program Memory Table Pointer Upper Byte
(TBLPTR<20:16>)
--00 0000 --00 0000
TBPLTRH Program Memory Table Pointer High Byte (TBLPTR<15:8>)
TBLPTRL Program Memory Table Pointer High Byte (TBLPTR<7:0>)
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
TABLAT
INTCON
EECON2
EECON1
IPR2
Program Memory Table Latch
GIE/GIEH PEIE/GIEL TMR0IE
INTE
RBIE
TMR0IF
INTF
RBIF
RD
EEPROM Control Register 2 (not a physical register)
—
—
EEPGD
CFGS
CMIP
CMIF
CMIE
—
—
—
—
FREE
EEIP
EEIF
EEIE
WRERR WREN
WR
xx-0 x000 uu-0 u000
—
—
—
BCLIP
BCLIF
BCLIE
LVDIP
LVDIF
LVDIE
TMR3IP
TMR3IF
TMR3IE
CCP2IP ---1 1111 ---1 1111
CCP2IF ---0 0000 ---0 0000
PIR2
PIE2
CCP2IE ---0 0000 ---0 0000
Legend:
x= unknown, u= unchanged, r= reserved, -= unimplemented, read as ‘0’.
Shaded cells are not used during FLASH/EEPROM access.
2003 Microchip Technology Inc.
Advance Information
DS39612A-page 71
PIC18F6X2X/8X2X
NOTES:
DS39612A-page 72
Advance Information
2003 Microchip Technology Inc.
PIC18F6X2X/8X2X
6.1
Program Memory Modes and the
External Memory Interface
6.0
EXTERNAL MEMORY
INTERFACE
As previously noted, PIC18F8X2X controllers are
capable of operating in any one of four Program Mem-
ory modes using combinations of on-chip and external
program memory. The functions of the multiplexed port
pins depends on the Program Memory mode selected,
as well as the setting of the EBDIS bit.
Note: The external memory interface is not
implemented on PIC18F6X2X (64-pin) devices.
The external memory interface is a feature of the
PIC18F8X2X devices that allows the controller to
access external memory devices (such as FLASH,
EPROM, SRAM, etc.) as program or data memory.
In Microprocessor Mode, the external bus is always
active and the port pins have only the external bus
function.
The physical implementation of the interface uses 27
pins. These pins are reserved for external address/data
bus functions; they are multiplexed with I/O port pins on
four ports. Three I/O ports are multiplexed with the
address/data bus, while the fourth port is multiplexed
with the bus control signals. The I/O port functions are
enabled when the EBDIS bit in the MEMCON register
is set (see Register 6-1). A list of the multiplexed pins
and their functions is provided in Table 6-1.
In Microcontroller Mode, the bus is not active and
the pins have their port functions only. Writes to the
MEMCOM register are not permitted.
In Microprocessor with Boot Block or Extended
Microcontroller Mode, the external program memory
bus shares I/O port functions on the pins. When the
device is fetching or doing table read/table write oper-
ations on the external program memory space, the
pins will have the external bus function. If the device is
fetching and accessing internal program memory loca-
tions only, the EBDIS control bit will change the pins
from external memory to I/O port functions. When
EBDIS = 0, the pins function as the external bus.
When EBDIS = 1, the pins function as I/O ports.
As implemented in the PIC18F8X2X devices, the inter-
face operates in a similar manner to the external
memory interface introduced on PIC18C601/801
microcontrollers. The most notable difference is that
the interface on PIC18F8X2X devices only operates in
16-bit modes. The 8-bit mode is not supported.
For a more complete discussion of the operating
modes that use the external memory interface, refer to
Section 4.1.1, “PIC18F6X2X/8X2X Program Memory
Modes”.
REGISTER 6-1:
MEMCON REGISTER
R/W-0
EBDIS
U-0
—
R/W-0
WAIT1
R/W-0
WAIT0
U-0
—
U-0
—
R/W-0
WM1
R/W-0
WM0
bit7
bit0
bit 7
EBDIS: External Bus Disable bit
1= External system bus disabled, all external bus drivers are mapped as I/O ports
0= External system bus enabled and I/O ports are disabled
bit 6
Unimplemented: Read as ‘0’
bit 5-4
WAIT1:WAIT0: Table Reads and Writes Bus Cycle Wait Count bits
11= Table reads and writes will wait 0 TCY
10= Table reads and writes will wait 1 TCY
01= Table reads and writes will wait 2 TCY
00= Table reads and writes will wait 3 TCY
bit 3-2
bit 1-0
Unimplemented: Read as ‘0’
WM1:WM0: TBLWRTOperation with 16-bit Bus bits
1x= Word Write mode: TABLAT<0> and TABLAT<1> word output, WRH active when
TABLAT<1> written
01= Byte Select mode: TABLAT data copied on both MS and LS Byte, WRH and (UB or LB)
will activate
00= Byte Write mode: TABLAT data copied on both MS and LS Byte, WRH or WRL will activate
Note:
The MEMCON register is unimplemented and reads all ‘0’s when the device is in
Microcontroller mode.
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
- n = Value at POR
2003 Microchip Technology Inc.
Advance Information
DS39612A-page 73
PIC18F6X2X/8X2X
If the device fetches or accesses external memory
while EBDIS = 1, the pins will switch to external bus. If
the EBDIS bit is set by a program executing from
external memory, the action of setting the bit will be
delayed until the program branches into the internal
memory. At that time, the pins will change from
external bus to I/O ports.
When the device is executing out of internal memory
(EBDIS = 0) in Microprocessor with Boot Block mode
or Extended Microcontroller mode, the control signals
will NOT be active. They will go to a state where the
AD<15:0> and A<19:16> are tri-state; the CE, OE,
WRH, WRL, UB and LB signals are ‘1’, and ALE and
BA0 are ‘0’.
TABLE 6-1:
Name
PIC18F8X2X EXTERNAL BUS - I/O PORT FUNCTIONS
Port
Bit
Function
RD0/AD0
RD1/AD1
RD2/AD2
RD3/AD3
RD4/AD4
RD5/AD5
RD6/AD6
RD7/AD7
RE0/AD8
RE1/AD9
RE2/AD10
RE3/AD11
RE4/AD12
RE5/AD13
RE6/AD14
RE7/AD15
RH0/A16
RH1/A17
RH2/A18
RH3/A19
RJ0/ALE
RJ1/OE
PORTD
PORTD
PORTD
PORTD
PORTD
PORTD
PORTD
PORTD
PORTE
PORTE
PORTE
PORTE
PORTE
PORTE
PORTE
PORTE
PORTH
PORTH
PORTH
PORTH
PORTJ
PORTJ
PORTJ
PORTJ
PORTJ
PORTJ
PORTJ
PORTJ
bit 0 Input/Output or System Bus Address bit 0 or Data bit 0
bit 1 Input/Output or System Bus Address bit 1 or Data bit 1
bit 2 Input/Output or System Bus Address bit 2 or Data bit 2
bit 3 Input/Output or System Bus Address bit 3 or Data bit 3
bit 4 Input/Output or System Bus Address bit 4 or Data bit 4
bit 5 Input/Output or System Bus Address bit 5 or Data bit 5
bit 6 Input/Output or System Bus Address bit 6 or Data bit 6
bit 7 Input/Output or System Bus Address bit 7 or Data bit 7
bit 0 Input/Output or System Bus Address bit 8 or Data bit 8
bit 1 Input/Output or System Bus Address bit 9 or Data bit 9
bit 2 Input/Output or System Bus Address bit 10 or Data bit 10
bit 3 Input/Output or System Bus Address bit 11 or Data bit 11
bit 4 Input/Output or System Bus Address bit 12 or Data bit 12
bit 5 Input/Output or System Bus Address bit 13 or Data bit 13
bit 6 Input/Output or System Bus Address bit 14 or Data bit 14
bit 7 Input/Output or System Bus Address bit 15 or Data bit 15
bit 0 Input/Output or System Bus Address bit 16
bit 1 Input/Output or System Bus Address bit 17
bit 2 Input/Output or System Bus Address bit 18
bit 3 Input/Output or System Bus Address bit 19
bit 0 Input/Output or System Bus Address Latch Enable (ALE) Control pin
bit 1 Input/Output or System Bus Output Enable (OE) Control pin
bit 2 Input/Output or System Bus Write Low (WRL) Control pin
bit 3 Input/Output or System Bus Write High (WRH) Control pin
bit 4 Input/Output or System Bus Byte Address bit 0
RJ2/WRL
RJ3/WRH
RJ4/BA0
RJ5/CE
bit 5 Input/Output or System Bus Chip Enable (CE) Control pin
bit 6 Input/Output or System Bus Lower Byte Enable (LB) Control pin
bit 7 Input/Output or System Bus Upper Byte Enable (UB) Control pin
RJ6/LB
RJ7/UB
DS39612A-page 74
Advance Information
2003 Microchip Technology Inc.
PIC18F6X2X/8X2X
In Byte Select mode, JEDEC standard FLASH memo-
ries will require BA0 for the byte address line and one
I/O line, to select between Byte and Word mode. The
other 16-bit modes do not need BA0. JEDEC standard
static RAM memories will use the UB or LB signals for
byte selection.
6.2
16-bit Mode
The external memory interface implemented in
PIC18F8X2X devices operates only in 16-bit mode.
The mode selection is not software configurable but is
programmed via the configuration bits.
The WM1:WM0 bits in the MEMCON register deter-
mine three types of connections in 16-bit mode. They
are referred to as:
6.2.1
16-BIT BYTE WRITE MODE
Figure 6-1 shows an example of 16-bit Byte Write
mode for PIC18F8X2X devices. This mode is used for
two separate 8-bit memories connected for 16-bit oper-
ation. This generally includes basic EPROM and
FLASH devices. It allows table writes to byte-wide
external memories.
• 16-bit Byte Write
• 16-bit Word Write
• 16-bit Byte Select
These three different configurations allow the designer
maximum flexibility in using 8-bit and 16-bit memory
devices.
During a TBLWTinstruction cycle, the TABLAT data is
presented on the upper and lower bytes of the
AD15:AD0 bus. The appropriate WRH or WRL control
line is strobed on the LSb of the TBLPTR.
For all 16-bit modes, the Address Latch Enable (ALE)
pin indicates that the address bits A15:A0 are available
on the external memory interface bus. Following the
address latch, the Output Enable signal (OE) will
enable both bytes of program memory at once to form
a 16-bit instruction word. The Chip Enable signal (CE)
is active at any time that the microcontroller accesses
external memory, whether reading or writing; it is inac-
tive (asserted high) whenever the device is in SLEEP
mode.
FIGURE 6-1:
16-BIT BYTE WRITE MODE EXAMPLE
D<7:0>
PIC18F8X2X
AD<7:0>
(MSB)
A<x:0>
(LSB)
A<x:0>
A<19:0>
D<15:8>
373
373
D<7:0>
D<7:0>
CE
D<7:0>
CE
AD<15:8>
ALE
(1)
(1)
OE WR
OE WR
A<19:16>
CE
OE
WRH
WRL
Address Bus
Data Bus
Control Lines
Note 1: This signal only applies to table writes. See Section 5.1, “Table Reads and Writes”.
2003 Microchip Technology Inc.
Advance Information
DS39612A-page 75
PIC18F6X2X/8X2X
During
a
TBLWT cycle to an odd address
6.2.2
16-BIT WORD WRITE MODE
(TBLPTR<0> = 1), the TABLAT data is presented on
the upper byte of the AD15:AD0 bus. The contents of
the holding latch are presented on the lower byte of the
AD15:AD0 bus.
Figure 6-2 shows an example of 16-bit Word Write
mode for PIC18F8X2X devices. This mode is used for
word-wide memories which includes some of the
EPROM and FLASH type memories. This mode allows
opcode fetches and table reads from all forms of 16-bit
memory, and table writes to any type of word-wide
external memories. This method makes a distinction
between TBLWTcycles to even or odd addresses.
The WRH signal is strobed for each write cycle; the
WRL pin is unused. The signal on the BA0 pin indicates
the LSbit of the TBLPTR but it is left unconnected.
Instead, the UB and LB signals are active to select both
bytes. The obvious limitation to this method is that the
table write must be done in pairs on a specific word
boundary to correctly write a word location.
During
a
TBLWT cycle to an even address
(TBLPTR<0> = 0), the TABLAT data is transferred to a
holding latch and the external address data bus is tri-
stated for the data portion of the bus cycle. No write
signals are activated.
FIGURE 6-2:
16-BIT WORD WRITE MODE EXAMPLE
PIC18F8X2X
AD<7:0>
A<20:1>
D<15:0>
JEDEC Word
EPROM Memory
373
A<x:0>
D<15:0>
CE
(1)
OE
WR
AD<15:8>
373
ALE
A<19:16>
CE
OE
WRH
Address Bus
Data Bus
Control Lines
Note 1: This signal only applies to table writes. See Section 5.1, “Table Reads and Writes”.
DS39612A-page 76
Advance Information
2003 Microchip Technology Inc.
PIC18F6X2X/8X2X
FLASH and SRAM devices use different control signal
combinations to implement Byte Select mode. JEDEC
standard FLASH memories require that a controller I/O
port pin be connected to the memory’s BYTE/WORD
pin to provide the select signal. They also use the BA0
signal from the controller as a byte address. JEDEC
standard static RAM memories, on the other hand, use
the UB or LB signals to select the byte.
6.2.3
16-BIT BYTE SELECT MODE
Figure 6-3 shows an example of 16-bit Byte Select
mode for PIC18F8X2X devices. This mode allows table
write operations to word-wide external memories with
byte selection capability. This generally includes both
word-wide FLASH and SRAM devices.
During a TBLWTcycle, the TABLAT data is presented
on the upper and lower byte of the AD15:AD0 bus. The
WRH signal is strobed for each write cycle; the WRL
pin is not used. The BA0 or UB/LB signals are used to
select the byte to be written based on the Least
Significant bit of the TBLPTR register.
FIGURE 6-3:
16-BIT BYTE SELECT MODE EXAMPLE
PIC18F8X2X
AD<7:0>
A<20:1>
373
373
JEDEC Word
FLASH Memory
A<x:1>
D<15:0>
D<15:0>
(2)
138
CE
A0
AD<15:8>
(1)
ALE
A<19:16>
OE
BYTE/WORD OE WR
WRH
A<20:1>
WRL
JEDEC Word
A<x:1>
SRAM Memory
BA0
I/O
D<15:0>
D<15:0>
CE
LB
LB
(1)
UB
OE WR
UB
Address Bus
Data Bus
Control Lines
Note 1: This signal only applies to table writes. See Section 5.1, “Table Reads and Writes”.
2: Demultiplexing is only required when multiple memory devices are accessed.
2003 Microchip Technology Inc.
Advance Information
DS39612A-page 77
PIC18F6X2X/8X2X
6.2.4
16-BIT MODE TIMING
The presentation of control signals on the external
memory bus is different for the various operating
modes. Typical signal timing diagrams are shown in
Figure 6-4 through Figure 6-6.
FIGURE 6-4:
EXTERNAL MEMORY BUS TIMING FOR TBLRD (MICROPROCESSOR MODE)
Q1
Q1
Q2
Q2
Q3
Q3
Q4
Q4
Q1
Q1
Q2
Q2
Q3
Q3
Q4
Q4
Q4
Q1
Q4
Q2
Q4
Q3
Q4
Q4
Apparent Q
Actual Q
00h
0Ch
A<19:16>
3AABh
0E55h
9256h
AD<15:0>
CF33h
BA0
ALE
OE
WRH
‘1’
‘1’
WRL
CE
‘1’
‘0’
‘1’
‘0’
1 TCY Wait
Memory
Cycle
Opcode Fetch
MOVLW55h
Table Read
of 92h
from 007556h
from 199E67h
Instruction
Execution
TBLRDCycle1
TBLRDCycle2
FIGURE 6-5:
EXTERNAL MEMORY BUS TIMING FOR TBLRD
(EXTENDED MICROCONTROLLER MODE)
Q1 Q2
Q3
Q4
Q1 Q2
Q3 Q4
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
0Ch
A<19:16>
CF33h
9256h
AD<15:0>
CE
ALE
OE
Opcode Fetch
TBLRD*
from 000100h
Opcode Fetch
MOVLW55h
from 000102h
TBLRD92h
from 199E67h
Opcode Fetch
ADDLW55h
from 000104h
Memory
Cycle
Instruction
Execution
INST(PC-2)
TBLRDCycle1
TBLRDCycle2
MOVLW
DS39612A-page 78
Advance Information
2003 Microchip Technology Inc.
PIC18F6X2X/8X2X
FIGURE 6-6:
EXTERNAL MEMORY BUS TIMING FOR SLEEP (MICROPROCESSOR MODE)
Q1 Q2
Q3
Q4
Q1 Q2
Q3 Q4
Q1
00h
00h
A<19:16>
AD<15:0>
0E55h
0003h
3AAAh
3AABh
CE
ALE
OE
Memory
Cycle
Opcode Fetch
MOVLW55h
Opcode Fetch
SLEEP
SLEEP Mode, Bus Inactive
from 007554h
from 007556h
Instruction
Execution
INST(PC-2)
SLEEP
2003 Microchip Technology Inc.
Advance Information
DS39612A-page 79
PIC18F6X2X/8X2X
NOTES:
DS39612A-page 80
Advance Information
2003 Microchip Technology Inc.
PIC18F6X2X/8X2X
7.1
EEADR and EEADRH
7.0
DATA EEPROM MEMORY
The address register pair can address up to a maxi-
mum of 1024 bytes of data EEPROM. The two MSbits
of the address are stored in EEADRH, while the
remaining eight LSbits are stored in EEADR. The six
Most Significant bits of EEADRH are unused and are
read as ‘0’.
The data EEPROM is readable and writable during nor-
mal operation over the entire VDD range. The data
memory is not directly mapped in the register file
space. Instead, it is indirectly addressed through the
Special Function Registers (SFR).
There are five SFRs used to read and write the
program and data EEPROM memory. These registers
are:
7.2
EECON1 and EECON2 Registers
• EECON1
• EECON2
• EEDATA
• EEADRH
• EEADR
EECON1 is the control register for EEPROM memory
accesses.
EECON2 is not a physical register. Reading EECON2
will read all ‘0’s. The EECON2 register is used
exclusively in the EEPROM write sequence.
Control bits RD and WR initiate read and write opera-
tions, respectively. These bits cannot be cleared, only
set in software. They are cleared in hardware at the
completion of the read or write operation. The inability
to clear the WR bit in software prevents the accidental
or premature termination of a write operation.
The EEPROM data memory allows byte read and write.
When interfacing to the data memory block, EEDATA
holds the 8-bit data for read/write. EEADR and
EEADRH hold the address of the EEPROM location
being accessed. These devices have 1024 bytes of
data EEPROM with an address range from 00h to
3FFh.
The WREN bit, when set, will allow a write operation.
On power-up, the WREN bit is clear. The WRERR bit is
set when a write operation is interrupted by a MCLR
Reset or a WDT Time-out Reset during normal
operation. In these situations, the user can check the
WRERR bit and rewrite the location. It is necessary to
reload the data and address registers (EEDATA and
EEADR) due to the RESET condition forcing the
contents of the registers to zero.
The EEPROM data memory is rated for high erase/
write cycles. A byte write automatically erases the loca-
tion and writes the new data (erase-before-write). The
write time is controlled by an on-chip timer. The write
time will vary with voltage and temperature, as well as
from chip to chip. Please refer to parameter D122
(Section 27.0, “Electrical Characteristics”) for exact
limits.
Note:
Interrupt flag bit, EEIF in the PIR2 register,
is set when write is complete. It must be
cleared in software.
2003 Microchip Technology Inc.
Advance Information
DS39612A-page 81
PIC18F6X2X/8X2X
REGISTER 7-1:
EECON1 REGISTER (ADDRESS FA6h)
R/W-x
R/W-x
CFGS
U-0
—
R/W-0
FREE
R/W-x
R/W-0
WREN
R/S-0
WR
R/S-0
RD
EEPGD
WRERR
bit 7
bit 0
bit 7
bit 6
EEPGD: FLASH Program/Data EEPROM Memory Select bit
1= Access FLASH program memory
0= Access data EEPROM memory
CFGS: FLASH Program/Data EEPROM or Configuration Select bit
1= Access Configuration or Calibration registers
0= Access FLASH program or data EEPROM memory
bit 5
bit 4
Unimplemented: Read as ‘0’
FREE: FLASH Row Erase Enable bit
1= Erase the program memory row addressed by TBLPTR on the next WR command
(cleared by completion of erase operation)
0= Perform write only
bit 3
WRERR: FLASH Program/Data EEPROM Error Flag bit
1= A write operation is prematurely terminated
(any MCLR or any WDT Reset during self-timed programming in normal operation)
0= The write operation completed
Note:
When a WRERR occurs, the EEPGD or FREE bits are not cleared. This allows
tracing of the error condition.
bit 2
bit 1
WREN: FLASH Program/Data EEPROM Write Enable bit
1= Allows write cycles to FLASH program/data EEPROM
0= Inhibits write cycles to FLASH program/data EEPROM
WR: Write Control bit
1= Initiates a data EEPROM erase/write cycle or a program memory erase cycle or write cycle.
(The operation is self-timed and the bit is cleared by hardware once write is complete. The
WR bit can only be set (not cleared) in software.)
0= Write cycle to the EEPROM is complete
bit 0
RD: Read Control bit
1= Initiates an EEPROM read
(Read takes one cycle. RD is cleared in hardware. The RD bit can only be set (not cleared)
in software. RD bit cannot be set when EEPGD = 1.)
0= Does not initiate an EEPROM read
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
- n = Value at POR
DS39612A-page 82
Advance Information
2003 Microchip Technology Inc.
PIC18F6X2X/8X2X
control bit (EECON1<6>), and then set the RD control
bit (EECON1<0>). The data is available for the very
next instruction cycle; therefore, the EEDATA register
can be read by the next instruction. EEDATA will hold
this value until another read operation or until it is
written to by the user (during a write operation).
7.3
Reading the Data EEPROM
Memory
To read a data memory location, the user must write the
address to the EEADRH:EEADR register pair, clear the
EEPGD control bit (EECON1<7>), clear the CFGS
EXAMPLE 7-1:
DATA EEPROM READ
MOVLW
MOVWF
MOVLW
MOVWF
BCF
DATA_EE_ADDRH
EEADRH
DATA_EE_ADDR
EEADR
;
; Upper bits of Data Memory Address to read
;
; Lower bits of Data Memory Address to read
EECON1, EEPGD ; Point to DATA memory
BCF
BSF
MOVF
EECON1, CFGS
EECON1, RD
EEDATA, W
; Access EEPROM
; EEPROM Read
; W = EEDATA
should be kept clear at all times except when updating
the EEPROM. The WREN bit is not cleared
by hardware
7.4
Writing to the Data EEPROM
Memory
To write an EEPROM data location, the address must
first be written to the EEADRH:EEADR register pair
and the data written to the EEDATA register. Then the
sequence in Example 7-2 must be followed to initiate
the write cycle.
After a write sequence has been initiated, EECON1,
EEADRH, EEADR and EEDATA cannot be modified.
The WR bit will be inhibited from being set unless the
WREN bit is set. The WREN bit must be set on a pre-
vious instruction. Both WR and WREN cannot be set
with the same instruction.
The write will not initiate if the above sequence is not
exactly followed (write 55h to EECON2, write AAh to
EECON2, then set WR bit) for each byte. It is strongly
recommended that interrupts be disabled during this
code segment.
At the completion of the write cycle, the WR bit is
cleared in hardware and the EEPROM Write Complete
Interrupt Flag bit (EEIF) is set. The user may either
enable this interrupt or poll this bit. EEIF must be
cleared by software.
Additionally, the WREN bit in EECON1 must be set to
enable writes. This mechanism prevents accidental
writes to data EEPROM due to unexpected code
execution (i.e., runaway programs). The WREN bit
EXAMPLE 7-2:
DATA EEPROM WRITE
MOVLW
DATA_EE_ADDRH
EEADRH
DATA_EE_ADDR
EEADR
DATA_EE_DATA
EEDATA
EECON1,EEPGD
EECON1,CFGS
EECON1,WREN
;
MOVWF
MOVLW
MOVWF
MOVLW
MOVWF
BCF
; Upper bits of Data Memory Address to write
;
; Lower bits of Data Memory Address to write
;
; Data Memory Value to write
; Point to DATA memory
; Access EEPROM
BCF
BSF
; Enable writes
BCF
INTCON,GIE
55h
EECON2
AAh
EECON2
; Disable Interrupts
;
; Write 55h
;
; Write AAh
; Set WR bit to begin write
; Enable Interrupts
MOVLW
MOVWF
MOVLW
MOVWF
BSF
Required
Sequence
EECON1,WR
INTCON,GIE
BSF
; User code execution
BCF
EECON1,WREN
; Disable writes on write complete (EEIF set)
2003 Microchip Technology Inc.
Advance Information
DS39612A-page 83
PIC18F6X2X/8X2X
7.5
Write Verify
7.8
Using the Data EEPROM
Depending on the application, good programming
practice may dictate that the value written to the mem-
ory should be verified against the original value. This
should be used in applications where excessive writes
can stress bits near the specification limit.
The data EEPROM is a high endurance, byte address-
able array that has been optimized for the storage of
frequently changing information (e.g., program vari-
ables or other data that are updated often). Frequently
changing values will typically be updated more often
than specification D124. If this is not the case, an array
refresh must be performed. For this reason, variables
that change infrequently (such as constants, IDs, cali-
bration, etc.) should be stored in FLASH program
memory.
7.6
Protection Against Spurious Write
There are conditions when the device may not want to
write to the data EEPROM memory. To protect against
spurious EEPROM writes, various mechanisms have
been built-in. On power-up, the WREN bit is cleared.
Also, the Power-up Timer (72 ms duration) prevents
EEPROM write.
A simple data EEPROM refresh routine is shown in
Example 7-3.
Note:
If data EEPROM is only used to store con-
stants and/or data that changes rarely, an
array refresh is likely not required. See
specification D124.
The write initiate sequence and the WREN bit together
help prevent an accidental write during brown-out,
power glitch, or software malfunction.
7.7
Operation During Code Protect
Data EEPROM memory has its own code protect
mechanism. External read and write operations are
disabled if either of these mechanisms are enabled.
The microcontroller itself can both read and write to the
internal data EEPROM regardless of the state of the
code protect configuration bit. Refer to Section 24.0,
“Special Features of the CPU” for additional
information.
EXAMPLE 7-3:
DATA EEPROM REFRESH ROUTINE
CLRF
CLRF
BCF
BCF
BCF
EEADR
EEADRH
EECON1,CFGS
EECON1,EEPGD
INTCON,GIE
EECON1,WREN
; Start at address 0
;
; Set for memory
; Set for Data EEPROM
; Disable interrupts
; Enable writes
; Loop to refresh array
; Read current address
;
; Write 55h
;
; Write AAh
; Set WR bit to begin write
; Wait for write to complete
BSF
Loop
BSF
EECON1,RD
55h
EECON2
AAh
EECON2
EECON1,WR
EECON1,WR
$-2
MOVLW
MOVWF
MOVLW
MOVWF
BSF
BTFSC
BRA
INCFSZ EEADR,F
; Increment address
BRA
Loop
; Not zero, do it again
; Increment the high address
; Not zero, do it again
INCFSZ EEADRH, F
BRA
Loop
BCF
BSF
EECON1,WREN
INTCON,GIE
; Disable writes
; Enable interrupts
DS39612A-page 84
Advance Information
2003 Microchip Technology Inc.
PIC18F6X2X/8X2X
TABLE 7-1:
REGISTERS ASSOCIATED WITH DATA EEPROM MEMORY
Value on
all other
RESETS
Value on:
POR, BOR
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
INTCON
EEADRH
EEADR
GIE/GIEH PEIE/GIEL TMR0IE INT0IE
RBIE
—
TMR0IF
—
INT0IF
RBIF
0000 0000 0000 0000
—
—
—
—
EE Addr Register High ---- --00 ---- --00
0000 0000 0000 0000
EEPROM Address Register
EEDATA EEPROM Data Register
EECON2 EEPROM Control Register 2 (not a physical register)
0000 0000 0000 0000
—
—
EECON1
IPR2
EEPGD
CFGS
CMIP
CMIF
CMIE
—
—
—
—
FREE WRERR WREN
WR
RD
xx-0 x000 uu-0 u000
—
—
—
EEIP
EEIF
EEIE
BCLIP
BCLIF
BCLIE
LVDIP
LVDIF
LVDIE
TMR3IP
TMR3IF
TMR3IE
CCP2IP ---1 1111 ---1 1111
CCP2IF ---0 0000 ---0 0000
CCP2IE ---0 0000 ---0 0000
PIR2
PIE2
Legend:
x= unknown, u= unchanged, r= reserved, -= unimplemented, read as ‘0’.
Shaded cells are not used during FLASH/EEPROM access.
2003 Microchip Technology Inc.
Advance Information
DS39612A-page 85
PIC18F6X2X/8X2X
NOTES:
DS39612A-page 86
Advance Information
2003 Microchip Technology Inc.
PIC18F6X2X/8X2X
8.2
Operation
8.0
8.1
8 X 8 HARDWARE MULTIPLIER
Introduction
Example 8-1 shows the sequence to do an 8 x 8
unsigned multiply. Only one instruction is required
when one argument of the multiply is already loaded in
the WREG register.
An 8 x 8 hardware multiplier is included in the ALU of
the PIC18F6X2X/8X2X devices. By making the multi-
ply a hardware operation, it completes in a single
instruction cycle. This is an unsigned multiply that gives
a 16-bit result. The result is stored in the 16-bit product
register pair (PRODH:PRODL). The multiplier does not
affect any flags in the ALUSTA register.
Example 8-2 shows the sequence to do an 8 x 8 signed
multiply. To account for the sign bits of the arguments,
each argument’s Most Significant bit (MSb) is tested
and the appropriate subtractions are done.
EXAMPLE 8-1:
8 x 8 UNSIGNED
MULTIPLY ROUTINE
Making the 8 x 8 multiplier execute in a single cycle
gives the following advantages:
MOVF
MULWF
ARG1, W
ARG2
;
• Higher computational throughput
; ARG1 * ARG2 ->
;
• Reduces code size requirements for multiply
algorithms
PRODH:PRODL
The performance increase allows the device to be used
in applications previously reserved for Digital Signal
Processors.
EXAMPLE 8-2:
8 x 8 SIGNED MULTIPLY
ROUTINE
Table 8-1 shows a performance comparison between
enhanced devices using the single cycle hardware mul-
tiply, and performing the same function without the
hardware multiply.
MOVF
MULWF
ARG1,
ARG2
W
; ARG1 * ARG2 ->
; PRODH:PRODL
; Test Sign Bit
; PRODH = PRODH
BTFSC
SUBWF
ARG2, SB
PRODH, F
;
- ARG1
MOVF
ARG2,
W
BTFSC
SUBWF
ARG1, SB
PRODH, F
; Test Sign Bit
; PRODH = PRODH
;
- ARG2
TABLE 8-1:
Routine
PERFORMANCE COMPARISON
Program
Time
@ 40 MHz @ 10 MHz @ 4 MHz
Cycles
(Max)
Multiply Method
Memory
(Words)
Without hardware multiply
Hardware multiply
13
1
69
1
6.9 µs
100 ns
9.1 µs
600 ns
24.2 µs
2.4 µs
25.4 µs
3.6 µs
27.6 µs
400 ns
36.4 µs
2.4 µs
69 µs
1 µs
91 µs
6 µs
8 x 8 unsigned
8 x 8 signed
Without hardware multiply
Hardware multiply
33
6
91
6
Without hardware multiply
Hardware multiply
21
24
52
36
242
24
254
36
96.8 µs
9.6 µs
242 µs
24 µs
254 µs
36 µs
16 x 16 unsigned
16 x 16 signed
Without hardware multiply
Hardware multiply
102.6 µs
14.4 µs
2003 Microchip Technology Inc.
Advance Information
DS39612A-page 87
PIC18F6X2X/8X2X
Example 8-3 shows the sequence to do a 16 x 16
unsigned multiply. Equation 8-1 shows the algorithm
that is used. The 32-bit result is stored in four registers,
RES3:RES0.
EQUATION 8-2:
16 x 16 SIGNED
MULTIPLICATION
ALGORITHM
RES3:RES0
=
=
ARG1H:ARG1L • ARG2H:ARG2L
EQUATION 8-1:
16 x 16 UNSIGNED
MULTIPLICATION
ALGORITHM
(ARG1H • ARG2H • 216) +
(ARG1H • ARG2L • 28) +
(ARG1L • ARG2H • 28) +
(ARG1L • ARG2L) +
RES3:RES0
=
=
ARG1H:ARG1L • ARG2H:ARG2L
(ARG1H • ARG2H • 216) +
(ARG1H • ARG2L • 28) +
(ARG1L • ARG2H • 28) +
(ARG1L • ARG2L)
(-1 • ARG2H<7> • ARG1H:ARG1L • 216) +
(-1 • ARG1H<7> • ARG2H:ARG2L • 216)
EXAMPLE 8-4:
16 x 16 SIGNED
MULTIPLY ROUTINE
MOVF
MULWF
ARG1L,
ARG2L
W
; ARG1L * ARG2L ->
; PRODH:PRODL
;
;
EXAMPLE 8-3:
16 x 16 UNSIGNED
MULTIPLY ROUTINE
MOVFF
MOVFF
PRODH, RES1
PRODL, RES0
MOVF
MULWF
ARG1L, W
ARG2L
;
;
; ARG1L * ARG2L ->
; PRODH:PRODL
;
;
MOVF
MULWF
ARG1H,
ARG2H
W
; ARG1H * ARG2H ->
; PRODH:PRODL
;
;
MOVFF
MOVFF
PRODH, RES1
PRODL, RES0
MOVFF
MOVFF
PRODH, RES3
PRODL, RES2
;
;
MOVF
MULWF
ARG1H,
ARG2H
W
; ARG1H * ARG2H ->
; PRODH:PRODL
;
;
MOVF
MULWF
ARG1L,
ARG2H
W
; ARG1L * ARG2H ->
; PRODH:PRODL
;
; Add cross
; products
;
;
;
MOVFF
MOVFF
PRODH, RES3
PRODL, RES2
MOVF
ADDWF
MOVF
ADDWFC RES2,
CLRF WREG
ADDWFC RES3,
PRODL,
RES1,
PRODH,
W
F
W
F
MOVF
MULWF
ARG1L,
ARG2H
W
; ARG1L * ARG2H ->
; PRODH:PRODL
MOVF
ADDWF
MOVF
PRODL,
RES1,
PRODH,
W
F
W
F
;
F
W
; Add cross
; products
;
;
;
;
MOVF
MULWF
ARG1H,
ARG2L
;
ADDWFC RES2,
CLRF WREG
ADDWFC RES3,
; ARG1H * ARG2L ->
; PRODH:PRODL
;
; Add cross
; products
;
;
;
F
W
MOVF
ADDWF
MOVF
ADDWFC RES2,
CLRF WREG
ADDWFC RES3,
PRODL,
RES1,
PRODH,
W
F
W
F
;
MOVF
MULWF
ARG1H,
ARG2L
;
; ARG1H * ARG2L ->
; PRODH:PRODL
MOVF
ADDWF
MOVF
PRODL,
RES1,
PRODH,
W
F
W
F
;
F
; Add cross
; products
;
;
;
;
;
BTFSS
BRA
MOVF
SUBWF
MOVF
ARG2H,
7
; ARG2H:ARG2L neg?
; no, check ARG1
;
;
;
ADDWFC RES2,
CLRF WREG
ADDWFC RES3,
SIGN_ARG1
ARG1L,
RES2
W
F
ARG1H,
W
SUBWFB RES3
Example 8-4 shows the sequence to do a 16 x 16
signed multiply. Equation 8-2 shows the algorithm
used. The 32-bit result is stored in four registers,
RES3:RES0. To account for the sign bits of the argu-
ments, each argument pairs’ Most Significant bit (MSb)
is tested and the appropriate subtractions are done.
SIGN_ARG1
BTFSS
BRA
ARG1H,
CONT_CODE
ARG2L,
RES2
ARG2H,
7
; ARG1H:ARG1L neg?
; no, done
;
;
;
MOVF
SUBWF
MOVF
W
W
SUBWFB RES3
;
CONT_CODE
:
DS39612A-page 88
Advance Information
2003 Microchip Technology Inc.
PIC18F6X2X/8X2X
When the IPEN bit is cleared (default state), the inter-
rupt priority feature is disabled and interrupts are
compatible with PICmicro® mid-range devices. In Com-
patibility mode, the interrupt priority bits for each source
have no effect. INTCON<6> is the PEIE bit which
enables/disables all peripheral interrupt sources.
INTCON<7> is the GIE bit which enables/disables all
interrupt sources. All interrupts branch to address
000008h in Compatibility mode.
9.0
INTERRUPTS
The PIC18F6X2X/8X2X devices have multiple interrupt
sources and an interrupt priority feature that allows
each interrupt source to be assigned a high or a low pri-
ority level. The high priority interrupt vector is at
000008h, while the low priority interrupt vector is at
000018h. High priority interrupt events will override any
low priority interrupts that may be in progress.
There are thirteen registers which are used to control
interrupt operation. They are:
When an interrupt is responded to, the global interrupt
enable bit is cleared to disable further interrupts. If the
IPEN bit is cleared, this is the GIE bit. If interrupt priority
levels are used, this will be either the GIEH or GIEL bit.
High priority interrupt sources can interrupt a low
priority interrupt.
• RCON
• INTCON
• INTCON2
• INTCON3
The return address is pushed onto the stack and the
PC is loaded with the interrupt vector address
(000008h or 000018h). Once in the Interrupt Service
Routine, the source(s) of the interrupt can be deter-
mined by polling the interrupt flag bits. The interrupt
flag bits must be cleared in software before re-enabling
interrupts to avoid recursive interrupts.
• PIR1, PIR2, PIR3
• PIE1, PIE2, PIE3
• IPR1, IPR2, IPR3
It is recommended that the Microchip header files sup-
plied with MPLAB® IDE be used for the symbolic bit
names in these registers. This allows the assembler/
compiler to automatically take care of the placement of
these bits within the specified register.
The “return from interrupt” instruction, RETFIE, exits
the interrupt routine and sets the GIE bit (GIEH or GIEL
if priority levels are used) which re-enables interrupts.
Each interrupt source has three bits to control its
operation. The functions of these bits are:
For external interrupt events, such as the INT pins or
the PORTB input change interrupt, the interrupt latency
will be three to four instruction cycles. The exact
latency is the same for one or two-cycle instructions.
Individual interrupt flag bits are set regardless of the
status of their corresponding enable bit or the GIE bit.
• Flag bit to indicate that an interrupt event
occurred
• Enable bit that allows program execution to
branch to the interrupt vector address when the
flag bit is set
• Priority bit to select high priority or low priority
The interrupt priority feature is enabled by setting the
IPEN bit (RCON<7>). When interrupt priority is
enabled, there are two bits which enable interrupts glo-
bally. Setting the GIEH bit (INTCON<7>) enables all
interrupts that have the priority bit set. Setting the GIEL
bit (INTCON<6>) enables all interrupts that have the
priority bit cleared. When the interrupt flag, enable bit
and appropriate global interrupt enable bit are set, the
interrupt will vector immediately to address 000008h or
000018h, depending on the priority level. Individual
interrupts can be disabled through their corresponding
enable bits.
2003 Microchip Technology Inc.
Advance Information
DS39612A-page 89
PIC18F6X2X/8X2X
FIGURE 9-1:
INTERRUPT LOGIC
Wake-up if in SLEEP mode
TMR0IF
TMR0IE
TMR0IP
RBIF
RBIE
RBIP
INT0IF
INT0IE
Interrupt to CPU
Vector to Location
0008h
INT1IF
INT1IE
INT1IP
INT2IF
INT2IE
INT2IP
Peripheral Interrupt Flag bit
Peripheral Interrupt Enable bit
Peripheral Interrupt Priority bit
GIEH/GIE
TMR1IF
TMR1IE
TMR1IP
IPE
IPEN
XXXXIF
XXXXIE
XXXXIP
GIEL/PEIE
IPEN
Additional Peripheral Interrupts
High Priority Interrupt Generation
Low Priority Interrupt Generation
Peripheral Interrupt Flag bit
Peripheral Interrupt Enable bit
Peripheral Interrupt Priority bit
Interrupt to CPU
Vector to Location
0018h
TMR0IF
TMR0IE
TMR0IP
TMR1IF
TMR1IE
TMR1IP
RBIF
RBIE
XXXXIF
XXXXIE
XXXXIP
GIEL/PEIE
RBIP
GIE/GEIH
INT1IF
INT1IE
INT1IP
Additional Peripheral Interrupts
INT2IF
INT2IE
INT2IP
DS39612A-page 90
Advance Information
2003 Microchip Technology Inc.
PIC18F6X2X/8X2X
9.1
INTCON Registers
Note:
Interrupt flag bits are set when an interrupt
condition occurs, regardless of the state of
its corresponding enable bit or the global
enable bit. User software should ensure
the appropriate interrupt flag bits are clear
prior to enabling an interrupt. This feature
allows for software polling.
The INTCON registers are readable and writable
registers which contain various enable, priority and flag
bits.
REGISTER 9-1:
INTCON REGISTER
R/W-0 R/W-0
R/W-0
R/W-0
R/W-0
RBIE
R/W-0
R/W-0
INT0IF
R/W-x
RBIF
GIE/GIEH PEIE/GIEL TMR0IE
bit 7
INT0IE
TMR0IF
bit 0
bit 7
GIE/GIEH: Global Interrupt Enable bit
When IPEN (RCON<7>) = 0:
1= Enables all unmasked interrupts
0= Disables all interrupts
When IPEN (RCON<7>) = 1:
1= Enables all high priority interrupts
0= Disables all interrupts
bit 6
PEIE/GIEL: Peripheral Interrupt Enable bit
When IPEN (RCON<7>) = 0:
1= Enables all unmasked peripheral interrupts
0= Disables all peripheral interrupts
When IPEN (RCON<7>) = 1:
1= Enables all low priority peripheral interrupts
0= Disables all low priority peripheral interrupts
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
TMR0IE: TMR0 Overflow Interrupt Enable bit
1= Enables the TMR0 overflow interrupt
0= Disables the TMR0 overflow interrupt
INT0IE: INT0 External Interrupt Enable bit
1= Enables the INT0 external interrupt
0= Disables the INT0 external interrupt
RBIE: RB Port Change Interrupt Enable bit
1= Enables the RB port change interrupt
0= Disables the RB port change interrupt
TMR0IF: TMR0 Overflow Interrupt Flag bit
1= TMR0 register has overflowed (must be cleared in software)
0= TMR0 register did not overflow
INT0IF: INT0 External Interrupt Flag bit
1= The INT0 external interrupt occurred (must be cleared in software)
0= The INT0 external interrupt did not occur
RBIF: RB Port Change Interrupt Flag bit
1= At least one of the RB7:RB4 pins changed state (must be cleared in software)
0= None of the RB7:RB4 pins have changed state
Note:
A mismatch condition will continue to set this bit. Reading PORTB will end the
mismatch condition and allow the bit to be cleared.
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
- n = Value at POR
2003 Microchip Technology Inc.
Advance Information
DS39612A-page 91
PIC18F6X2X/8X2X
REGISTER 9-2:
INTCON2 REGISTER
R/W-1
RBPU
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
RBIP
INTEDG0 INTEDG1 INTEDG2 INTEDG3 TMR0IP
INT3IP
bit 7
bit 0
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
RBPU: PORTB Pull-up Enable bit
1= All PORTB pull-ups are disabled
0= PORTB pull-ups are enabled by individual port latch values
INTEDG0: External Interrupt 0 Edge Select bit
1= Interrupt on rising edge
0= Interrupt on falling edge
INTEDG1: External Interrupt 1 Edge Select bit
1= Interrupt on rising edge
0= Interrupt on falling edge
INTEDG2: External Interrupt 2 Edge Select bit
1= Interrupt on rising edge
0= Interrupt on falling edge
INTEDG3: External Interrupt 3 Edge Select bit
1= Interrupt on rising edge
0= Interrupt on falling edge
TMR0IP: TMR0 Overflow Interrupt Priority bit
1= High priority
0= Low priority
INT3IP: INT3 External Interrupt Priority bit
1= High priority
0= Low priority
RBIP: RB Port Change Interrupt Priority bit
1= High priority
0= Low priority
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
- n = Value at POR
Note:
Interrupt flag bits are set when an interrupt condition occurs, regardless of the state
of its corresponding enable bit or the global enable bit. User software should ensure
the appropriate interrupt flag bits are clear prior to enabling an interrupt. This feature
allows for software polling.
DS39612A-page 92
Advance Information
2003 Microchip Technology Inc.
PIC18F6X2X/8X2X
REGISTER 9-3:
INTCON3 REGISTER
R/W-1
R/W-1
R/W-0
R/W-0
R/W-0
R/W-0
INT3IF
R/W-0
INT2IF
R/W-0
INT1IF
INT2IP
INT1IP
INT3IE
INT2IE
INT1IE
bit 7
bit 0
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
INT2IP: INT2 External Interrupt Priority bit
1= High priority
0= Low priority
INT1IP: INT1 External Interrupt Priority bit
1= High priority
0= Low priority
INT3IE: INT3 External Interrupt Enable bit
1= Enables the INT3 external interrupt
0= Disables the INT3 external interrupt
INT2IE: INT2 External Interrupt Enable bit
1= Enables the INT2 external interrupt
0= Disables the INT2 external interrupt
INT1IE: INT1 External Interrupt Enable bit
1= Enables the INT1 external interrupt
0= Disables the INT1 external interrupt
INT3IF: INT3 External Interrupt Flag bit
1= The INT3 external interrupt occurred (must be cleared in software)
0= The INT3 external interrupt did not occur
INT2IF: INT2 External Interrupt Flag bit
1= The INT2 external interrupt occurred (must be cleared in software)
0= The INT2 external interrupt did not occur
INT1IF: INT1 External Interrupt Flag bit
1= The INT1 external interrupt occurred (must be cleared in software)
0= The INT1 external interrupt did not occur
Legend: Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
- n = Value at POR
Note:
Interrupt flag bits are set when an interrupt condition occurs, regardless of the state
of its corresponding enable bit or the global enable bit. User software should ensure
the appropriate interrupt flag bits are clear prior to enabling an interrupt. This feature
allows for software polling.
2003 Microchip Technology Inc.
Advance Information
DS39612A-page 93
PIC18F6X2X/8X2X
9.2
PIR Registers
Note 1: Interrupt flag bits are set when an interrupt
condition occurs, regardless of the state of
its corresponding enable bit or the global
enable bit, GIE (INTCON<7>).
The PIR registers contain the individual flag bits for the
peripheral interrupts. Due to the number of peripheral
interrupt sources, there are three Peripheral Interrupt
Flag registers (PIR1, PIR2 and PIR3).
2: User software should ensure the appropri-
ate interrupt flag bits are cleared prior to
enabling an interrupt and after servicing
that interrupt.
REGISTER 9-4:
PIR1: PERIPHERAL INTERRUPT REQUEST (FLAG) REGISTER 1
R/W-0
PSPIF(1)
bit 7
R/W-0
ADIF
R-0
R-0
R/W-0
SSPIF
R/W-0
R/W-0
R/W-0
TMR1IF
bit 0
RC1IF
TX1IF
CCP1IF
TMR2IF
bit 7
PSPIF: Parallel Slave Port Read/Write Interrupt Flag bit(1)
1= A read or a write operation has taken place (must be cleared in software)
0= No read or write has occurred
Note 1: Enabled only in Microcontroller mode for PIC18F8X2X devices.
bit 6
bit 5
bit 4
bit 3
bit 2
ADIF: A/D Converter Interrupt Flag bit
1= An A/D conversion completed (must be cleared in software)
0= The A/D conversion is not complete
RC1IF: USART1 Receive Interrupt Flag bit
1= The USART1 receive buffer, RCREGx, is full (cleared when RCREGx is read)
0= The USART1 receive buffer is empty
TX1IF: USART Transmit Interrupt Flag bit
1= The USART1 transmit buffer, TXREGx, is empty (cleared when TXREGx is written)
0= The USART1 transmit buffer is full
SSPIF: Master Synchronous Serial Port Interrupt Flag bit
1= The transmission/reception is complete (must be cleared in software)
0= Waiting to transmit/receive
CCP1IF: CCP1 Interrupt Flag bit
Capture mode:
1= A TMR1 register capture occurred (must be cleared in software)
0= No TMR1 register capture occurred
Compare mode:
1= A TMR1 register compare match occurred (must be cleared in software)
0= No TMR1 register compare match occurred
PWM mode:
Unused in this mode.
bit 1
bit 0
TMR2IF: TMR2 to PR2 Match Interrupt Flag bit
1= TMR2 to PR2 match occurred (must be cleared in software)
0= No TMR2 to PR2 match occurred
TMR1IF: TMR1 Overflow Interrupt Flag bit
1= TMR1 register overflowed (must be cleared in software)
0= TMR1 register did not overflow
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
- n = Value at POR
DS39612A-page 94
Advance Information
2003 Microchip Technology Inc.
PIC18F6X2X/8X2X
REGISTER 9-5:
PIR2: PERIPHERAL INTERRUPT REQUEST (FLAG) REGISTER 2
U-0
—
R/W-0
CMIF
U-0
—
R/W-0
EEIF
R/W-0
BCLIF
R/W-0
LVDIF
R/W-0
R/W-0
CCP2IF
bit 0
TMR3IF
bit 7
bit 7
bit 6
Unimplemented: Read as ‘0’
CMIF: Comparator Interrupt Flag bit
1= The comparator input has changed (must be cleared in software)
0= The comparator input has not changed
bit 5
bit 4
Unimplemented: Read as ‘0’
EEIF: Data EEPROM/FLASH Write Operation Interrupt Flag bit
1= The write operation is complete (must be cleared in software)
0= The write operation is not complete, or has not been started
bit 3
BCLIF: Bus Collision Interrupt Flag bit
1= A bus collision occurred while the SSP module (configured in I2C Master mode)
was transmitting (must be cleared in software)
0= No bus collision occurred
bit 2
bit 1
bit 0
LVDIF: Low Voltage Detect Interrupt Flag bit
1= A low voltage condition occurred (must be cleared in software)
0= The device voltage is above the Low Voltage Detect trip point
TMR3IF: TMR3 Overflow Interrupt Flag bit
1= TMR3 register overflowed (must be cleared in software)
0= TMR3 register did not overflow
CCP2IF: CCP2 Interrupt Flag bit
Capture mode:
1= A TMR1 or TMR3 register capture occurred (must be cleared in software)
0= No TMR1 or TMR3 register capture occurred
Compare mode:
1= A TMR1 or TMR3 register compare match occurred (must be cleared in software)
0= No TMR1 or TMR3 register compare match occurred
PWM mode:
Unused in this mode.
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
- n = Value at POR
2003 Microchip Technology Inc.
Advance Information
DS39612A-page 95
PIC18F6X2X/8X2X
REGISTER 9-6:
PIR3: PERIPHERAL INTERRUPT REQUEST (FLAG) REGISTER 3
U-0
—
U-0
—
R-0
R-0
R/W-0
R/W-0
R/W-0
R/W-0
CCP3IF
bit 0
RC2IF
TX2IF
TMR4IF
CCP5IF
CCP4IF
bit 7
bit 7-6
bit 5
Unimplemented: Read as ‘0’
RC2IF: USART2 Receive Interrupt Flag bit
1= The USART2 receive buffer, RCREGx, is full (cleared when RCREGx is read)
0= The USART2 receive buffer is empty
bit 4
TX2IF: USART2 Transmit Interrupt Flag bit
1= The USART2 transmit buffer, TXREGx, is empty (cleared when TXREGx is written)
0= The USART2 transmit buffer is full
bit 3
TMR4IF: TMR3 Overflow Interrupt Flag bit
1= TMR4 register overflowed (must be cleared in software)
0= TMR4 register did not overflow
bit 2-0
CCPxIF: CCPx Interrupt Flag bit (ECCP3, CCP4 and CCP5)
Capture mode:
1= A TMR1 or TMR3 register capture occurred (must be cleared in software)
0= No TMR1 or TMR3 register capture occurred
Compare mode:
1= A TMR1 or TMR3 register compare match occurred (must be cleared in software)
0= No TMR1 or TMR3 register compare match occurred
PWM mode:
Unused in this mode.
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
- n = Value at POR
DS39612A-page 96
Advance Information
2003 Microchip Technology Inc.
PIC18F6X2X/8X2X
9.3
PIE Registers
The PIE registers contain the individual enable bits for
the peripheral interrupts. Due to the number of periph-
eral interrupt sources, there are three Peripheral Inter-
rupt Enable registers (PIE1, PIE2 and PIE3). When the
IPEN bit (RCON<7>) is ‘0’, the PEIE bit must be set to
enable any of these peripheral interrupts.
REGISTER 9-7:
PIE1: PERIPHERAL INTERRUPT ENABLE REGISTER 1
R/W-0
PSPIE(1)
bit 7
R/W-0
ADIE
R/W-0
RC1IE
R/W-0
TX1IE
R/W-0
SSPIE
R/W-0
R/W-0
R/W-0
TMR1IE
bit 0
CCP1IE
TMR2IE
bit 7
PSPIE: Parallel Slave Port Read/Write Interrupt Enable bit(1)
1= Enables the PSP read/write interrupt
0= Disables the PSP read/write interrupt
Note 1: Enabled only in Microcontroller mode for PIC18F8X2X devices.
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
ADIE: A/D Converter Interrupt Enable bit
1= Enables the A/D interrupt
0= Disables the A/D interrupt
RC1IE: USART1 Receive Interrupt Enable bit
1= Enables the USART1 receive interrupt
0= Disables the USART1 receive interrupt
TX1IE: USART1 Transmit Interrupt Enable bit
1= Enables the USART1 transmit interrupt
0= Disables the USART1 transmit interrupt
SSPIE: Master Synchronous Serial Port Interrupt Enable bit
1= Enables the MSSP interrupt
0= Disables the MSSP interrupt
CCP1IE: CCP1 Interrupt Enable bit
1= Enables the CCP1 interrupt
0= Disables the CCP1 interrupt
TMR2IE: TMR2 to PR2 Match Interrupt Enable bit
1= Enables the TMR2 to PR2 match interrupt
0= Disables the TMR2 to PR2 match interrupt
TMR1IE: TMR1 Overflow Interrupt Enable bit
1= Enables the TMR1 overflow interrupt
0= Disables the TMR1 overflow interrupt
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
- n = Value at POR
2003 Microchip Technology Inc.
Advance Information
DS39612A-page 97
PIC18F6X2X/8X2X
REGISTER 9-8:
PIE2: PERIPHERAL INTERRUPT ENABLE REGISTER 2
U-0
—
R/W-0
CMIE
U-0
—
R/W-0
EEIE
R/W-0
BCLIE
R/W-0
LVDIE
R/W-0
R/W-0
TMR3IE
CCP2IE
bit 7
bit 0
bit 7
bit 6
Unimplemented: Read as ‘0’
CMIE: Comparator Interrupt Enable bit
1= Enables the comparator interrupt
0= Disables the comparator interrupt
bit 5
bit 4
Unimplemented: Read as ‘0’
EEIE: Data EEPROM/FLASH Write Operation Interrupt Enable bit
1= Enables the write operation interrupt
0= Disables the write operation interrupt
bit 3
bit 2
bit 1
bit 0
BCLIE: Bus Collision Interrupt Enable bit
1= Enables the bus collision interrupt
0= Disables the bus collision interrupt
LVDIE: Low Voltage Detect Interrupt Enable bit
1= Enables the Low Voltage Detect interrupt
0= Disables the Low Voltage Detect interrupt
TMR3IE: TMR3 Overflow Interrupt Enable bit
1= Enables the TMR3 overflow interrupt
0= Disables the TMR3 overflow interrupt
CCP2IE: CCP2 Interrupt Enable bit
1= Enables the CCP2 interrupt
0= Disables the CCP2 interrupt
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
- n = Value at POR
DS39612A-page 98
Advance Information
2003 Microchip Technology Inc.
PIC18F6X2X/8X2X
REGISTER 9-9:
PIE3: PERIPHERAL INTERRUPT ENABLE REGISTER 3
U-0
—
U-0
—
R/W-0
RC2IE
R/W-0
TX2IE
R/W-0
R/W-0
R/W-0
R/W-0
TMR4IE
CCP5IE
CCP4IE
CCP3IE
bit 7
bit 0
bit 7-6
bit 5
Unimplemented: Read as ‘0’
RC2IE: USART2 Receive Interrupt Enable bit
1= Enables the USART2 receive interrupt
0= Disables the USART2 receive interrupt
bit 4
TX2IE: USART2 Transmit Interrupt Enable bit
1= Enables the USART2 transmit interrupt
0= Disables the USART2 transmit interrupt
bit 3
TMR4IE: TMR4 to PR4 Match Interrupt Enable bit
1= Enables the TMR4 to PR4 match interrupt
0= Disables the TMR4 to PR4 match interrupt
bit 2-0
CCPxIE: CCPx Interrupt Enable bit (ECCP3, CCP4 and CCP5)
1= Enables the CCPx interrupt
0= Disables the CCPx interrupt
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
- n = Value at POR
2003 Microchip Technology Inc.
Advance Information
DS39612A-page 99
PIC18F6X2X/8X2X
9.4
IPR Registers
The IPR registers contain the individual priority bits for
the peripheral interrupts. Due to the number of periph-
eral interrupt sources, there are three Peripheral Inter-
rupt Priority registers (IPR1, IPR2 and IPR3). The
operation of the priority bits requires that the Interrupt
Priority Enable (IPEN) bit be set.
REGISTER 9-10: IPR1: PERIPHERAL INTERRUPT PRIORITY REGISTER 1
R/W-1
PSPIP(1)
bit 7
R/W-1
ADIP
R/W-1
RC1IP
R/W-1
TX1IP
R/W-1
SSPIP
R/W-1
R/W-1
R/W-1
TMR1IP
bit 0
CCP1IP
TMR2IP
bit 7
PSPIP: Parallel Slave Port Read/Write Interrupt Priority bit(1)
1= High priority
0= Low priority
Note 1: Enabled only in Microcontroller mode for PIC18F8X2X devices.
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
ADIP: A/D Converter Interrupt Priority bit
1= High priority
0= Low priority
RC1IP: USART1 Receive Interrupt Priority bit
1= High priority
0= Low priority
TX1IP: USART1 Transmit Interrupt Priority bit
1= High priority
0= Low priority
SSPIP: Master Synchronous Serial Port Interrupt Priority bit
1= High priority
0= Low priority
CCP1IP: CCP1 Interrupt Priority bit
1= High priority
0= Low priority
TMR2IP: TMR2 to PR2 Match Interrupt Priority bit
1= High priority
0= Low priority
TMR1IP: TMR1 Overflow Interrupt Priority bit
1= High priority
0= Low priority
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
- n = Value at POR
DS39612A-page 100
Advance Information
2003 Microchip Technology Inc.
PIC18F6X2X/8X2X
REGISTER 9-11: IPR2: PERIPHERAL INTERRUPT PRIORITY REGISTER 2
U-0
—
R/W-1
CMIP
U-0
—
R/W-1
EEIP
R/W-1
BCLIP
R/W-1
LVDIP
R/W-1
R/W-1
TMR3IP
CCP2IP
bit 7
bit 0
bit 7
bit 6
Unimplemented: Read as ‘0’
CMIP: Comparator Interrupt Priority bit
1= High priority
0= Low priority
bit 5
bit 4
Unimplemented: Read as ‘0’
EEIP: Data EEPROM/FLASH Write Operation Interrupt Priority bit
1= High priority
0= Low priority
bit 3
bit 2
bit 1
bit 0
BCLIP: Bus Collision Interrupt Priority bit
1= High priority
0= Low priority
LVDIP: Low Voltage Detect Interrupt Priority bit
1= High priority
0= Low priority
TMR3IP: TMR3 Overflow Interrupt Priority bit
1= High priority
0= Low priority
CCP2IP: CCP2 Interrupt Priority bit
1= High priority
0= Low priority
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
- n = Value at POR
2003 Microchip Technology Inc.
Advance Information
DS39612A-page 101
PIC18F6X2X/8X2X
REGISTER 9-12: IPR3: PERIPHERAL INTERRUPT PRIORITY REGISTER 3
U-0
—
U-0
—
R/W-1
RC2IP
R/W-1
TX2IP
R/W-1
R/W-1
R/W-1
R/W-1
TMR4IP
CCP5IP
CCP4IP
CCP3IP
bit 7
bit 0
bit 7-6
bit 5
Unimplemented: Read as ‘0’
RC2IP: USART2 Receive Interrupt Priority bit
1= High priority
0= Low priority
bit 4
TX2IP: USART2 Transmit Interrupt Priority bit
1= High priority
0= Low priority
bit 3
TMR4IP: TMR4 to PR4 Match Interrupt Priority bit
1= High priority
0= Low priority
bit 2-0
CCPxIP: CCPx Interrupt Priority bit (ECCP3, CCP4 and CCP5)
1= High priority
0= Low priority
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
- n = Value at POR
DS39612A-page 102
Advance Information
2003 Microchip Technology Inc.
PIC18F6X2X/8X2X
9.5
RCON Register
The RCON register contains the IPEN bit which is used
to enable prioritized interrupts. The functions of the
other bits in this register are discussed in more detail in
Section 4.14.
REGISTER 9-13: RCON REGISTER
R/W-0
IPEN
U-0
—
U-0
—
R/W-1
RI
R-1
TO
R-1
PD
R/W-0
POR
R/W-0
BOR
bit 7
bit 0
bit 7
IPEN: Interrupt Priority Enable bit
1= Enable priority levels on interrupts
0= Disable priority levels on interrupts (PIC16 Compatibility mode)
bit 6-5
bit 4
Unimplemented: Read as ‘0’
RI: RESETInstruction Flag bit
For details of bit operation, see Register 4-4.
TO: Watchdog Time-out Flag bit
bit 3
bit 2
bit 1
bit 0
For details of bit operation, see Register 4-4.
PD: Power-down Detection Flag bit
For details of bit operation, see Register 4-4.
POR: Power-on Reset Status bit
For details of bit operation, see Register 4-4.
BOR: Brown-out Reset Status bit
For details of bit operation, see Register 4-4.
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
- n = Value at POR
2003 Microchip Technology Inc.
Advance Information
DS39612A-page 103
PIC18F6X2X/8X2X
9.6
INT0 Interrupt
9.8
PORTB Interrupt-on-Change
External interrupts on the RB0/INT0, RB1/INT1,
RB2/INT2 and RB3/INT3 pins are edge-triggered:
either rising, if the corresponding INTEDGx bit is set in
the INTCON2 register or falling, if the INTEDGx bit is
clear. When a valid edge appears on the RBx/INTx pin,
the corresponding flag bit, INTxF, is set. This interrupt
can be disabled by clearing the corresponding enable
bit, INTxE. Flag bit, INTxF, must be cleared in software
in the Interrupt Service Routine before re-enabling the
interrupt. All external interrupts (INT0, INT1, INT2 and
INT3) can wake-up the processor from SLEEP if bit
INTxIE was set prior to going into SLEEP. If the global
interrupt enable bit GIE is set, the processor will branch
to the interrupt vector following wake-up.
An input change on PORTB<7:4> sets flag bit RBIF
(INTCON<0>). The interrupt can be enabled/disabled
by setting/clearing enable bit, RBIE (INTCON<3>).
Interrupt priority for PORTB interrupt-on-change is
determined by the value contained in the interrupt
priority bit, RBIP (INTCON2<0>).
9.9
Context Saving During Interrupts
During an interrupt, the return PC value is saved on the
stack. Additionally, the WREG, STATUS and BSR
registers are saved on the fast return stack. If a fast
return from interrupt is not used (see Section 4.3), the
user may need to save the WREG, STATUS and BSR
registers in software. Depending on the user’s
application, other registers may also need to be saved.
Example 9-1 saves and restores the WREG, STATUS
and BSR registers during an Interrupt Service Routine.
The interrupt priority for INT1, INT2 and INT3 is
determined by the value contained in the interrupt
priority bits: INT1IP (INTCON3<6>), INT2IP
(INTCON3<7>) and INT3IP (INTCON2<1>). There is
no priority bit associated with INT0; it is always a high
priority interrupt source.
9.7
TMR0 Interrupt
In 8-bit mode (which is the default), an overflow in the
TMR0 register (FFh → 00h) will set flag bit TMR0IF. In
16-bit mode, an overflow in the TMR0H:TMR0L
registers (FFFFh → 0000h) will set flag bit TMR0IF. The
interrupt can be enabled/disabled by setting/clearing
enable bit, TMR0IE (INTCON<5>). Interrupt priority for
Timer0 is determined by the value contained in the
interrupt priority bit, TMR0IP (INTCON2<2>). See
Section 11.0 for further details on the Timer0 module.
EXAMPLE 9-1:
SAVING STATUS, WREG AND BSR REGISTERS IN RAM
MOVWF
MOVFF
MOVFF
;
W_TEMP
STATUS,STATUS_TEMP
BSR,
; W_TEMP is in virtual bank
; STATUS_TEMP located anywhere
; BSR located anywhere
BSR_TEMP
; USER ISR CODE
;
MOVFF
MOVF
MOVFF
BSR_TEMP, BSR
W_TEMP,
STATUS_TEMP,STATUS
; Restore BSR
; Restore WREG
; Restore STATUS
W
DS39612A-page 104
Advance Information
2003 Microchip Technology Inc.
PIC18F6X2X/8X2X
10.1 PORTA, TRISA and LATA
Registers
10.0 I/O PORTS
Depending on the device selected, there are either
seven
or
nine
I/O
ports
available
on
PORTA is a 7-bit wide, bi-directional port. The corre-
sponding Data Direction register is TRISA. Setting a
TRISA bit (= 1) will make the corresponding PORTA pin
an input (i.e., put the corresponding output driver in a
high-impedance mode). Clearing a TRISA bit (= 0) will
make the corresponding PORTA pin an output (i.e., put
the contents of the output latch on the selected pin).
PIC18F6X2X/8X2X devices. Some of their pins are
multiplexed with one or more alternate functions from
the other peripheral features on the device. In general,
when a peripheral is enabled, that pin may not be used
as a general purpose I/O pin.
Each port has three registers for its operation. These
registers are:
Reading the PORTA register reads the status of the
pins, whereas writing to it will write to the port latch.
• TRIS register (Data Direction register)
The Data Latch register (LATA) is also memory
mapped. Read-modify-write operations on the LATA
register, read and write the latched output value for
PORTA.
• PORT register (reads the levels on the pins of the
device)
• LAT register (Output Latch register)
The Data Latch (LAT) register is useful for
read-modify-write operations on the value that the I/O
pins are driving.
The RA4 pin is multiplexed with the Timer0 module
clock input to become the RA4/T0CKI pin. The
RA4/T0CKI pin is a Schmitt Trigger input and an open
drain output. All other RA port pins have TTL input
levels and full CMOS output drivers.
A simplified version of a generic I/O port and its
operation is shown in Figure 10-1.
The RA6 pin is only enabled as a general I/O pin in
ECIO and RCIO Oscillator modes.
FIGURE 10-1:
SIMPLIFIED BLOCK
DIAGRAM OF
The other PORTA pins are multiplexed with analog
inputs and the analog VREF+ and VREF- inputs. The
operation of each pin is selected by clearing/setting the
control bits in the ADCON1 register (A/D Control
Register 1).
PORT/LAT/TRIS
OPERATION
RD LAT
Note:
On a Power-on Reset, RA5 and RA3:RA0
are configured as analog inputs and read
as ‘0’. RA6 and RA4 are configured as
digital inputs.
TRIS
D
Q
WR LAT +
WR Port
CK
Data Latch
The TRISA register controls the direction of the RA pins
even when they are being used as analog inputs. The
user must ensure the bits in the TRISA register are
maintained set when using them as analog inputs.
Data Bus
RD Port
I/O pin
EXAMPLE 10-1:
INITIALIZING PORTA
CLRF
PORTA
LATA
0x0F
; Initialize PORTA by
; clearing output
; data latches
; Alternate method
; to clear output
; data latches
CLRF
MOVLW
MOVWF
MOVLW
; Configure A/D
ADCON1 ; for digital inputs
0xCF
; Value used to
; initialize data
; direction
MOVWF
TRISA
; Set RA<3:0> as inputs
; RA<5:4> as outputs
2003 Microchip Technology Inc.
Advance Information
DS39612A-page 105
PIC18F6X2X/8X2X
FIGURE 10-2:
BLOCK DIAGRAM OF
RA3:RA0AND RA5PINS
FIGURE 10-3:
BLOCK DIAGRAM OF
RA4/T0CKI PIN
RD LATA
RD LATA
Data
Bus
Data
Bus
D
Q
D
Q
Q
WR LATA
or
PORTA
WR LATA
or
PORTA
VDD
I/O pin(1)
Q
Data Latch
CK
CK
P
N
Data Latch
I/O pin(1)
D
Q
N
D
Q
VSS
WR TRISA
RD TRISA
Schmitt
Trigger
Input
WR TRISA
RD TRISA
CK
Q
VSS
Analog
Q
CK
TRIS Latch
TRIS Latch
Input
Buffer
Mode
TTL
Input
Buffer
Q
D
Q
D
EN
EN
RD PORTA
RD PORTA
TMR0 Clock Input
To A/D Converter and LVD Modules
Note 1: I/O pins have protection diodes to VDD and VSS.
Note 1: I/O pins have protection diodes to VDD and VSS.
FIGURE 10-4:
BLOCK DIAGRAM OF RA6 PIN (WHEN ENABLED AS I/O)
ECRA6 or RCRA6 Enable
Data Bus
RD LATA
D
Q
Q
VDD
P
WR LATA or PORTA
CK
Data Latch
I/O pin(1)
N
D
Q
WR TRISA
VSS
CK
Q
TRIS Latch
TTL
Input
Buffer
TRISA
RD
ECRA6 or RCRA6 Enable
Q
D
EN
RD PORTA
Note 1: I/O pins have protection diodes to VDD and VSS.
DS39612A-page 106
Advance Information
2003 Microchip Technology Inc.
PIC18F6X2X/8X2X
TABLE 10-1: PORTA FUNCTIONS
Name
RA0/AN0
Bit#
Buffer
Function
bit 0
bit 1
bit 2
bit 3
bit 4
TTL
TTL
TTL
TTL
ST
Input/output or analog input.
RA1/AN1
Input/output or analog input.
RA2/AN2/VREF-
RA3/AN3/VREF+
RA4/T0CKI
Input/output or analog input or VREF-.
Input/output or analog input or VREF+.
Input/output or external clock input for Timer0.
Output is open drain type.
RA5/AN4/LVDIN
OSC2/CLKO/RA6
bit 5
TTL
Input/output or slave select input for synchronous serial port or analog
input, or Low Voltage Detect input.
bit 6
TTL
OSC2 or clock output, or I/O pin.
Legend: TTL = TTL input, ST = Schmitt Trigger input
TABLE 10-2: SUMMARY OF REGISTERS ASSOCIATED WITH PORTA
Value on
all other
RESETS
Value on
POR, BOR
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PORTA
LATA
—
—
—
—
RA6
RA5
RA4
RA3
RA2
RA1
RA0
-x0x 0000 -u0u 0000
-xxx xxxx -uuu uuuu
-111 1111 -111 1111
LATA Data Output Register
TRISA
ADCON1
PORTA Data Direction Register
—
VCFG1 VCFG0 PCFG3 PCFG2 PCFG1 PCFG0 --00 0000 --00 0000
Legend: x= unknown, u= unchanged, - = unimplemented locations read as ‘0’.
Shaded cells are not used by PORTA.
2003 Microchip Technology Inc.
Advance Information
DS39612A-page 107
PIC18F6X2X/8X2X
A mismatch condition will continue to set flag bit, RBIF.
Reading PORTB will end the mismatch condition and
allow flag bit RBIF to be cleared.
10.2 PORTB, TRISB and LATB
Registers
PORTB is an 8-bit wide, bi-directional port. The corre-
sponding Data Direction register is TRISB. Setting a
TRISB bit (= 1) will make the corresponding PORTB
pin an input (i.e., put the corresponding output driver in
a high-impedance mode). Clearing a TRISB bit (= 0)
will make the corresponding PORTB pin an output (i.e.,
put the contents of the output latch on the selected pin).
The interrupt-on-change feature is recommended for
wake-up on key depression operation and operations
where PORTB is only used for the interrupt-on-change
feature. Polling of PORTB is not recommended while
using the interrupt-on-change feature.
For PIC18F8X2X devices, RB3 can be configured by
the configuration bit, CCP2MX, as the alternate
peripheral pin for the CCP2 module. This is only
available when the device is configured in
Microprocessor, Microprocessor with Boot Block, or
Extended Microcontroller operating modes.
The Data Latch register (LATB) is also memory
mapped. Read-modify-write operations on the LATB
register, read and write the latched output value for
PORTB.
The RB5 pin is used as the LVP programming pin.
When the LVP configuration bit is programmed, this pin
loses the I/O function and become a programming test
function.
EXAMPLE 10-2:
INITIALIZING PORTB
CLRF
PORTB
; Initialize PORTB by
; clearing output
; data latches
CLRF
LATB
; Alternate method
; to clear output
; data latches
Note:
When LVP is enabled, the weak pull-up on
RB5 is disabled.
MOVLW
MOVWF
0xCF
; Value used to
; initialize data
; direction
; Set RB<3:0> as inputs
; RB<5:4> as outputs
; RB<7:6> as inputs
FIGURE 10-5:
BLOCK DIAGRAM OF
RB7:RB4 PINS
TRISB
VDD
RBPU(2)
Data Bus
Weak
P
Pull-up
Each of the PORTB pins has a weak internal pull-up. A
single control bit can turn on all the pull-ups. This is
performed by clearing bit RBPU (INTCON2<7>). The
weak pull-up is automatically turned off when the port
pin is configured as an output. The pull-ups are
disabled on a Power-on Reset.
Data Latch
D
Q
WR LATB
or PORTB
I/O pin(1)
CK
TRIS Latch
D
Q
Note:
On a Power-on Reset, these pins are
configured as digital inputs.
WR TRISB
TTL
Input
Buffer
CK
ST
Buffer
Four of the PORTB pins (RB3:RB0) are the external
interrupt pins, INT3 through INT0. In order to use these
pins as external interrupts, the corresponding TRISB
bit must be set to ‘1’.
RD TRISB
RD LATB
The other four PORTB pins (RB7:RB4) have an
interrupt-on-change feature. Only pins configured as
inputs can cause this interrupt to occur (i.e., any
RB7:RB4 pin configured as an output is excluded from
the interrupt-on-change comparison). The input pins (of
RB7:RB4) are compared with the old value latched on
the last read of PORTB. The “mismatch” outputs of
RB7:RB4 are ORed together to generate the RB port
change interrupt with flag bit, RBIF (INTCON<0>).
Latch
Q
D
RD PORTB
Set RBIF
Q1
EN
Q
D
RD PORTB
Q3
From other
RB7:RB4 pins
EN
RB7:RB5 in Serial Programming Mode
This interrupt can wake the device from SLEEP. The
user, in the Interrupt Service Routine, can clear the
interrupt in the following manner:
Note 1: I/O pins have diode protection to VDD and VSS.
2: To enable weak pull-ups, set the appropriate TRIS bit(s)
and clear the RBPU bit (INTCON2<7>).
a) Any read or write of PORTB (except with the
MOVFF instruction). This will end the mismatch
condition.
b) Clear flag bit RBIF.
DS39612A-page 108
Advance Information
2003 Microchip Technology Inc.
PIC18F6X2X/8X2X
FIGURE 10-6:
BLOCK DIAGRAM OF RB2:RB0 PINS
VDD
RBPU(2)
Weak
P
Pull-up
Data Latch
Data Bus
D
Q
I/O pin(1)
WR Port
CK
TRIS Latch
D
Q
TTL
Input
WR TRIS
CK
Buffer
RD TRIS
RD Port
Q
D
EN
INTx
RD Port
Schmitt Trigger
Buffer
Note 1: I/O pins have diode protection to VDD and VSS.
2: To enable weak pull-ups, set the appropriate TRIS bit(s) and clear the RBPU bit (OPTION_REG<7>).
FIGURE 10-7:
BLOCK DIAGRAM OF RB3 PIN
VDD
Weak
RBPU(2)
CCP2MX
P
Pull-up
CCP Output(3)
1
VDD
P
Enable(3)
CCP Output
0
Data Latch
Data Bus
I/O pin(1)
D
Q
WR LATB or
WR PORTB
N
CK
VSS
TRIS Latch
D
TTL
WR TRISB
Input
CK
Q
Buffer
RD TRISB
RD LATB
D
Q
RD PORTB
EN
RD PORTB
CCP2 or INT3
Schmitt Trigger
Buffer
CCP2MX = 0
Note 1: I/O pin has diode protection to VDD and VSS.
2: To enable weak pull-ups, set the appropriate TRIS bit(s) and clear the RBPU bit (INTCON2<7>).
3: For PIC18F8X2X parts, the CCP2 input/output is multiplexed with RB3 if the CCP2MX bit is enabled (= 0) in the Configuration
register and the device is operating in Microprocessor, Microprocessor with Boot Block or Extended Microcontroller mode.
2003 Microchip Technology Inc.
Advance Information
DS39612A-page 109
PIC18F6X2X/8X2X
TABLE 10-3: PORTB FUNCTIONS
Name
RB0/INT0
Bit#
Buffer
Function
bit 0
TTL/ST(1) Input/output pin or external interrupt input 0.
Internal software programmable weak pull-up.
RB1/INT1
RB2/INT2
bit 1
bit 2
bit 3
TTL/ST(1) Input/output pin or external interrupt input 1.
Internal software programmable weak pull-up.
TTL/ST(1) Input/output pin or external interrupt input 2.
Internal software programmable weak pull-up.
RB3/INT3/
TTL/ST(4) Input/output pin, external interrupt input 3, Capture2 input/Compare2
CCP2(3)/P2A(3)
output/PWM2 output, or Enhanced PWM output P2A.
Internal software programmable weak pull-up.
RB4/KBI0
bit 4
bit 5
TTL
Input/output pin (with interrupt-on-change).
Internal software programmable weak pull-up.
RB5/KBI1/PGM
TTL/ST(2) Input/output pin (with interrupt-on-change).
Internal software programmable weak pull-up.
Low voltage ICSP enable pin.
RB6/KBI2/PGC
RB7/KBI3/PGD
bit 6
bit 7
TTL/ST(2) Input/output pin (with interrupt-on-change).
Internal software programmable weak pull-up.
Serial programming clock.
TTL/ST(2) Input/output pin (with interrupt-on-change).
Internal software programmable weak pull-up.
Serial programming data.
Legend: TTL = TTL input, ST = Schmitt Trigger input
Note 1: This buffer is a Schmitt Trigger input when configured as the external interrupt.
2: This buffer is a Schmitt Trigger input when used in Serial Programming mode.
3: Valid for PIC18F8X2X devices in all operating modes except Microcontroller mode when CCP2MX is not
set. RC1 is the default assignment for CCP2/PA2 when CCP2MX is set in all devices; RE7 is the alternate
assignment for PIC18F8X2X devices in Microcontroller mode when CCP2MX is clear.
4: This buffer is a Schmitt Trigger input when configured as the CCP2 input.
TABLE 10-4: SUMMARY OF REGISTERS ASSOCIATED WITH PORTB
Value on
Value on
POR, BOR
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
all other
RESETS
PORTB
LATB
RB7
RB6
RB5
RB4
RB3
RB2
RB1
RB0
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
1111 1111 1111 1111
0000 0000 0000 0000
1111 1111 1111 1111
LATB Data Output Register
TRISB
PORTB Data Direction Register
GIE/GIEH PEIE/GIEL TMR0IE
INTCON
INTCON2
INTCON3
Legend:
INT0IE
RBIE
TMR0IF INT0IF
RBIF
RBIP
RBPU
INTEDG0 INTEDG1 INTEDG2 INTEDG3 TMR0IP INT3IP
INT1IP INT3IE INT2IE INT1IE INT3IF INT2IF
INT2IP
INT1IF 1100 0000 1100 0000
x= unknown, u= unchanged. Shaded cells are not used by PORTB.
DS39612A-page 110
Advance Information
2003 Microchip Technology Inc.
PIC18F6X2X/8X2X
The pin override value is not loaded into the TRIS reg-
ister. This allows read-modify-write of the TRIS register
without concern due to peripheral overrides.
10.3 PORTC, TRISC and LATC
Registers
PORTC is an 8-bit wide, bi-directional port. The corre-
sponding Data Direction register is TRISC. Setting a
TRISC bit (= 1) will make the corresponding PORTC
pin an input (i.e., put the corresponding output driver in
a high-impedance mode). Clearing a TRISC bit (= 0)
will make the corresponding PORTC pin an output (i.e.,
put the contents of the output latch on the selected pin).
RC1 is normally configured by configuration bit,
CCP2MX, as the default peripheral pin of the CCP2
module (default/erased state, CCP2MX = 1).
EXAMPLE 10-3:
INITIALIZING PORTC
CLRF
PORTC
; Initialize PORTC by
; clearing output
; data latches
The Data Latch register (LATC) is also memory
mapped. Read-modify-write operations on the LATC
register, read and write the latched output value for
PORTC.
CLRF
LATC
; Alternate method
; to clear output
; data latches
MOVLW
MOVWF
0xCF
; Value used to
; initialize data
; direction
; Set RC<3:0> as inputs
; RC<5:4> as outputs
; RC<7:6> as inputs
PORTC is multiplexed with several peripheral functions
(Table 10-5). PORTC pins have Schmitt Trigger input
buffers.
TRISC
When enabling peripheral functions, care should be
taken in defining TRIS bits for each PORTC pin. Some
peripherals override the TRIS bit to make a pin an
output, while other peripherals override the TRIS bit to
make a pin an input. The user should refer to the
corresponding peripheral section for the correct TRIS
bit settings.
Note:
On a Power-on Reset, these pins are
configured as digital inputs.
FIGURE 10-8:
PORTC BLOCK DIAGRAM (PERIPHERAL OUTPUT OVERRIDE)
PORTC/Peripheral Out Select
Peripheral Data Out
VDD
P
0
1
RD LATC
Data Bus
D
Q
Q
(1)
I/O pin
or
WR LATC
CK
WR PORTC
Data Latch
TRIS OVERRIDE
N
D
Q
Q
Pin
Override
Peripheral
VSS
TRIS
Override
Logic
WR TRISC
CK
RC0
Yes
Timer1 OSC for
Timer1/Timer3
TRIS Latch
RC1
Yes
Timer1 OSC for
Timer1/Timer3,
CCP2 I/O
RD TRISC
Schmitt
Trigger
Peripheral Output
RC2
RC3
Yes
Yes
CCP1 I/O
(2)
Enable
2
Q
D
SPI/I C
Master Clock
EN
2
RC4
RC5
RC6
Yes
Yes
Yes
I C Data Out
RD PORTC
SPI Data Out
Peripheral Data In
USART1 Async
Xmit, Sync Clock
Note 1: I/O pins have diode protection to VDD and VSS.
2: Peripheral output enable is only active if peripheral select is active.
RC7
Yes
USART1 Sync
Data Out
2003 Microchip Technology Inc.
Advance Information
DS39612A-page 111
PIC18F6X2X/8X2X
TABLE 10-5: PORTC FUNCTIONS
Name
Bit# Buffer Type
Function
RC0/T1OSO/T13CKI bit 0
ST
ST
ST
ST
Input/output port pin, Timer1 oscillator output, or Timer1/Timer3
clock input.
RC1/T1OSI/CCP2(1)
P2A(1)
/
bit 1
bit 2
bit 3
Input/output port pin, Timer1 oscillator input, standard Capture2
input/Compare2 output/PWM output, or Enhanced PWM output P2A.
RC2/CCP1/P1A
Input/output port pin, Capture1 input/Compare1 output/PWM1
output, or Enhanced PWM output P1A.
RC3 can also be the synchronous serial clock for both SPI and I2C
RC3/SCK/SCL
modes.
RC4/SDI/SDA
RC5/SDO
bit 4
bit 5
bit 6
ST
ST
ST
RC4 can also be the SPI Data In (SPI mode) or Data I/O (I2C mode).
Input/output port pin or Synchronous Serial Port data output.
RC6/TX1/CK1
Input/output port pin, Addressable USART1 Asynchronous Transmit,
or Addressable USART1 Synchronous Clock.
RC7/RX1/DT1
bit 7
ST
Input/output port pin, Addressable USART1 Asynchronous Receive,
or Addressable USART1 Synchronous Data.
Legend: ST = Schmitt Trigger input
Note 1: Valid when CCP2MX is set in all devices and in all operating modes (default). RE7 is the alternate assign-
ment for CCP2/P2A for all PIC18F6X2X devices and PIC18F8X2X devices in Microcontroller modes
when CCP2MX is not set; RB3 is the alternate assignment for PIC18F8X2X devices in all other operating
modes.
TABLE 10-6: SUMMARY OF REGISTERS ASSOCIATED WITH PORTC
Value on
Value on
POR, BOR
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
all other
RESETS
PORTC
LATC
RC7
RC6
RC5
RC4
RC3
RC2
RC1
RC0
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
1111 1111 1111 1111
LATC Data Output Register
PORTC Data Direction Register
TRISC
Legend: x= unknown, u= unchanged
DS39612A-page 112
Advance Information
2003 Microchip Technology Inc.
PIC18F6X2X/8X2X
FIGURE 10-9:
PORTD BLOCK DIAGRAM
IN I/O PORT MODE
10.4 PORTD, TRISD and LATD
Registers
PORTD is an 8-bit wide, bi-directional port. The corre-
sponding Data Direction register is TRISD. Setting a
TRISD bit (= 1) will make the corresponding PORTD
pin an input (i.e., put the corresponding output driver in
a high-impedance mode). Clearing a TRISD bit (= 0)
will make the corresponding PORTD pin an output (i.e.,
put the contents of the output latch on the selected pin).
RD LATD
Data
Bus
D
Q
WR LATD
or
PORTD
I/O pin(1)
CK
Data Latch
The Data Latch register (LATD) is also memory
mapped. Read-modify-write operations on the LATD
register, read and write the latched output value for
PORTD.
D
Q
Schmitt
Trigger
Input
WR TRISD
RD TRISD
CK
TRIS Latch
Buffer
PORTD is an 8-bit port with Schmitt Trigger input buff-
ers. Each pin is individually configurable as an input or
output.
Note:
On a Power-on Reset, these pins are
configured as digital inputs.
Q
D
PORTD is multiplexed with the system bus as the
external memory interface; I/O port functions are only
available when the system bus is disabled by setting
the EBDIS bit in the MEMCOM register
(MEMCON<7>). When operating as the external
memory interface, PORTD is the low order byte of the
multiplexed address/data bus (AD7:AD0).
EN
RD PORTD
Note 1: I/O pins have diode protection to VDD and VSS.
PORTD can also be configured as an 8-bit wide
microprocessor port (Parallel Slave Port) by setting
control bit PSPMODE (TRISE<4>). In this mode, the
input buffers are TTL. See Section 10.10 for additional
information on the Parallel Slave Port (PSP).
EXAMPLE 10-4:
INITIALIZING PORTD
CLRF PORTD
; Initialize PORTD by
; clearing output
; data latches
CLRF LATD
MOVLW 0xCF
MOVWF TRISD
; Alternate method
; to clear output
; data latches
; Value used to
; initialize data
; direction
; Set RD<3:0> as inputs
; RD<5:4> as outputs
; RD<7:6> as inputs
2003 Microchip Technology Inc.
Advance Information
DS39612A-page 113
PIC18F6X2X/8X2X
FIGURE 10-10:
PORTD BLOCK DIAGRAM IN SYSTEM BUS MODE
Q
D
EN
RD PORTD
RD LATD
Data Bus
(1)
I/O pin
Port
D
Q
0
1
Data
WR LATD
or PORTD
CK
Data Latch
D
Q
TTL
Input
Buffer
WR TRISD
RD TRISD
CK
TRIS Latch
Bus Enable
System Bus
Data/TRIS Out
Control
Drive Bus
Instruction Register
Instruction Read
Note 1: I/O pins have protection diodes to VDD and VSS.
DS39612A-page 114
Advance Information
2003 Microchip Technology Inc.
PIC18F6X2X/8X2X
TABLE 10-7: PORTD FUNCTIONS
Name
Bit#
Buffer Type
Function
RD0/AD0/PSP0
RD1/AD1/PSP1
RD2/AD2/PSP2
RD3/AD3/PSP3
RD4/AD4/PSP4
RD5/AD5/PSP5
RD6/AD6/PSP6
RD7/AD7/PSP7
bit 0
bit 1
bit 2
bit 3
bit 4
bit 5
bit 6
bit 7
ST/TTL(1)
ST/TTL(1)
ST/TTL(1)
ST/TTL(1)
ST/TTL(1)
ST/TTL(1)
ST/TTL(1)
ST/TTL(1)
Input/output port pin, address/data bus bit 0 or parallel slave port bit 0.
Input/output port pin, address/data bus bit 1 or parallel slave port bit 1.
Input/output port pin, address/data bus bit 2 or parallel slave port bit 2.
Input/output port pin, address/data bus bit 3 or parallel slave port bit 3.
Input/output port pin, address/data bus bit 4 or parallel slave port bit 4.
Input/output port pin, address/data bus bit 5 or parallel slave port bit 5.
Input/output port pin, address/data bus bit 6 or parallel slave port bit 6.
Input/output port pin, address/data bus bit 7 or parallel slave port bit 7.
Legend: ST = Schmitt Trigger input, TTL = TTL input
Note 1: Input buffers are Schmitt Triggers when in I/O mode and TTL buffers when in System Bus or Parallel
Slave Port mode.
TABLE 10-8: SUMMARY OF REGISTERS ASSOCIATED WITH PORTD
Value on
all other
RESETS
Value on
POR, BOR
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PORTD
LATD
RD7
RD6
RD5
RD4
RD3
RD2
RD1
RD0
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
1111 1111 1111 1111
0000 ---- 0000 ----
LATD Data Output Register
PORTD Data Direction Register
TRISD
PSPCON
IBF
OBF
—
IBOV PSPMODE
WAIT1 WAIT0
—
—
—
—
—
—
MEMCON EBDIS
WM1
WM0 0-00 --00 0-00 --00
Legend: x= unknown, u= unchanged, - = unimplemented, read as ‘0’. Shaded cells are not used by PORTD.
2003 Microchip Technology Inc.
Advance Information
DS39612A-page 115
PIC18F6X2X/8X2X
When the parallel slave port is active, three PORTE
pins (RE0/AD8/RD, RE1/AD9/WR, and RE2/AD10/CS)
function as its control inputs. This automatically occurs
when the PSPMODE bit (PSPCON<4>) is set. Users
must also make certain that bits TRISE<2:0> are set to
configure the pins as digital inputs, and the ADCON1
register is configured for digital I/O. The PORTE PSP
control functions are summarized in Table 10-9.
10.5 PORTE, TRISE and LATE
Registers
PORTE is an 8-bit wide, bi-directional port. The corre-
sponding Data Direction register is TRISE. Setting a
TRISE bit (= 1) will make the corresponding PORTE
pin an input (i.e., put the corresponding output driver in
a high-impedance mode). Clearing a TRISE bit (= 0)
will make the corresponding PORTE pin an output (i.e.,
put the contents of the output latch on the selected pin).
Pin RE7 can be configured as the alternate peripheral
pin for the CCP2 module when the device is operating
in Microcontroller mode. This is done by clearing the
configuration bit CCP2MX in the CONFIG3H
Configuration register (CONFIG3H<0>).
Read-modify-write operations on the LATE register,
read and write the latched output value for PORTE.
PORTE is an 8-bit port with Schmitt Trigger input buff-
ers. Each pin is individually configurable as an input or
output. PORTE is multiplexed with the CCP module
(Table 10-9).
Note:
For PIC18F8X2X (80-pin) devices operat-
ing in Extended Microcontroller mode,
PORTE defaults to the system bus on
Power-on Reset.
On PIC18F8X2X devices, PORTE is also multiplexed
with the system bus as the external memory interface;
the I/O bus is available only when the system bus is
disabled by setting the EBDIS bit in the MEMCON
register (MEMCON<7>). If the device is configured in
Microprocessor or Extended Microcontroller mode,
then the PORTE<7:0> becomes the high byte of the
address/data bus for the external program memory
interface. In Microcontroller mode, the PORTE<2:0>
pins become the control inputs for the parallel slave
port when bit PSPMODE (PSPCON<4>) is set. (Refer
to Section 4.1.1 for more information on Program
Memory modes.)
EXAMPLE 10-5:
INITIALIZING PORTE
CLRF
PORTE
; Initialize PORTE by
; clearing output
; data latches
CLRF
LATE
; Alternate method
; to clear output
; data latches
MOVLW
MOVWF
0x03
; Value used to
; initialize data
; direction
; Set RE1:RE0 as inputs
; RE7:RE2 as outputs
TRISE
DS39612A-page 116
Advance Information
2003 Microchip Technology Inc.
PIC18F6X2X/8X2X
FIGURE 10-11:
PORTE BLOCK DIAGRAM IN I/O MODE
Peripheral Out Select
Peripheral Data Out
VDD
P
0
1
(1)
I/O pin
RD LATE
Data Bus
D
Q
Q
WR LATE
or WR PORTE
CK
Data Latch
N
D
Q
Q
VSS
TRIS
WR TRISE
CK
TRIS OVERRIDE
Override
TRIS Latch
Pin Override
Peripheral
RE0
RE1
RE2
RE3
RE4
RE5
RE6
RE7
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
External Bus
External Bus
External Bus
External Bus
External Bus
External Bus
External Bus
External Bus
RD TRISE
Schmitt
Trigger
Peripheral Enable
Q
D
EN
RD PORTE
Peripheral Data In
Note 1: I/O pins have diode protection to VDD and VSS.
FIGURE 10-12:
PORTE BLOCK DIAGRAM IN SYSTEM BUS MODE
Q
D
EN
RD PORTE
RD LATE
Data Bus
(1)
I/O pin
Port
0
1
D
Q
Data
WR LATE
or PORTE
CK
Data Latch
D
Q
TTL
Input
Buffer
WR TRISE
CK
TRIS Latch
RD TRISE
Bus Enable
Data/TRIS Out
Drive Bus
System Bus
Control
Instruction Register
Instruction Read
Note 1: I/O pins have protection diodes to VDD and VSS.
2003 Microchip Technology Inc.
Advance Information
DS39612A-page 117
PIC18F6X2X/8X2X
TABLE 10-9:
Name
PORTE FUNCTIONS
Bit#
Buffer Type
Function
RE0/AD8/RD/P2D
RE1/AD9/WR/P2C
RE2/AD10/CS/P2B
bit 0
ST/TTL(1)
Input/output port pin, address/data bit 8, Read control for parallel slave
port, or Enhanced PWM2 output P2D
For RD (PSP Control mode):
1= Not a read operation
0= Read operation, reads PORTD register (if chip selected)
bit 1
bit 2
ST/TTL(1)
ST/TTL(1)
Input/output port pin, address/data bit 9, Write control for parallel slave
port, or Enhanced PWM2 output P2C
For WR (PSP Control mode):
1= Not a write operation
0= Write operation, writes PORTD register (if chip selected)
Input/output port pin, address/data bit 10, Chip Select control for
parallel slave port, or Enhanced PWM2 output P2B
For CS (PSP Control mode):
1= Device is not selected
0= Device is selected
RE3/AD11/P3C(2)
RE4/AD12/P3B(2)
RE5/AD13/P1C(2)
RE6/AD14/P1B(2)
bit 3
bit 4
bit 5
bit 6
bit 7
ST/TTL(1)
ST/TTL(1)
ST/TTL(1)
ST/TTL(1)
ST/TTL(1)
Input/output port pin, address/data bit 11 or Enhanced PWM3
output P3C.
Input/output port pin, address/data bit 12 or Enhanced PWM3
output P3B.
Input/output port pin, address/data bit 13 or Enhanced PWM1
output P1C.
Input/output port pin, address/data bit 14 or Enhanced PWM1
output P1B.
RE7/AD15/CCP2(3)
P2A(3)
/
Input/output port pin, address/data bit 15, Capture2 input/Compare2
output/PWM output or Enhanced PWM output P2A.
Legend: ST = Schmitt Trigger input, TTL = TTL input
Note 1: Input buffers are Schmitt Triggers when in I/O or CCP/ECCP modes, and TTL buffers when in System Bus
or PSP Control modes.
2: Valid for all PIC18F6X2X devices and PIC18F8X2X devices when ECCPMX is set. Alternate assignments
for P1B/P1C/P3B/P3C are RH7, RH6, RH5 and RH4, respectively.
3: Valid for all PIC18F6X2X devices and PIC18F8X2X devices in Microcontroller mode when CCP2MX is not
set. RC1 is the default assignment for CCP2/P2A for all devices in Microcontroller mode when CCP2MX is
set; RB3 is the alternate assignment for PIC18F8X2X devices in operating modes except Microcontroller
mode when CCP2MX is not set.
TABLE 10-10: SUMMARY OF REGISTERS ASSOCIATED WITH PORTE
Value on
Value on:
POR, BOR
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
all other
RESETS
1111 1111
xxxx xxxx
xxxx xxxx
0-00 --00
0000 ----
1111 1111
uuuu uuuu
uuuu uuuu
0000 --00
0000 ----
TRISE
PORTE Data Direction Control Register
Read PORTE pin/Write PORTE Data Latch
Read PORTE Data Latch/Write PORTE Data Latch
PORTE
LATE
MEMCON
PSPCON
EBDIS
IBF
—
WAIT1
WAIT0
—
—
—
—
WM1
—
WM0
—
OBF
IBOV PSPMODE
Legend: x= unknown, u= unchanged. Shaded cells are not used by PORTE.
DS39612A-page 118
Advance Information
2003 Microchip Technology Inc.
PIC18F6X2X/8X2X
EXAMPLE 10-6:
INITIALIZING PORTF
10.6 PORTF, LATF, and TRISF
Registers
CLRF
PORTF
; Initialize PORTF by
; clearing output
; data latches
; Alternate method
; to clear output
; data latches
;
PORTF is an 8-bit wide, bi-directional port. The corre-
sponding Data Direction register is TRISF. Setting a
TRISF bit (= 1) will make the corresponding PORTF pin
an input (i.e., put the corresponding output driver in a
high-impedance mode). Clearing a TRISF bit (= 0) will
make the corresponding PORTF pin an output (i.e., put
the contents of the output latch on the selected pin).
CLRF
LATF
MOVLW
MOVWF
MOVLW
MOVWF
MOVLW
0x07
CMCON
0x0F
; Turn off comparators
;
ADCON1 ; Set PORTF as digital I/O
0xCF
Read-modify-write operations on the LATF register,
read and write the latched output value for PORTF.
; Value used to
; initialize data
; direction
; Set RF3:RF0 as inputs
; RF5:RF4 as outputs
; RF7:RF6 as inputs
PORTF is multiplexed with several analog peripheral
functions, including the A/D converter inputs and
comparator inputs, outputs, and voltage reference.
MOVWF
TRISF
Note 1: On a Power-on Reset, the RF6:RF0 pins
are configured as inputs and read as ‘0’.
2: To configure PORTF as digital I/O, turn off
comparators and set ADCON1 value.
FIGURE 10-13:
PORTF RF1/AN6/C2OUT, RF2/AN7/C1OUT PINS BLOCK DIAGRAM
PORT/Comparator Select
Comparator Data Out
VDD
P
0
1
RD LATF
Q
Data Bus
D
I/O pin
WR LATF
or
WR PORTF
CK
Q
Data Latch
N
D
Q
Q
VSS
WR TRISF
CK
Analog
Input
Mode
TRIS Latch
Schmitt
Trigger
RD TRISF
Q
D
EN
RD PORTF
To A/D Converter
Note 1: I/O pins have diode protection to VDD and VSS.
2003 Microchip Technology Inc.
Advance Information
DS39612A-page 119
PIC18F6X2X/8X2X
FIGURE 10-14:
RF6:RF3 AND RF0 PINS
BLOCK DIAGRAM
FIGURE 10-15:
RF7 PIN BLOCK
DIAGRAM
RD LATF
RD LATF
Data
Bus
Data
Bus
D
Q
D
Q
WR LATF or
WR PORTF
I/O pin
WR LATF
or
WR PORTF
VDD
CK
Data Latch
CK
Data Latch
Q
P
D
Q
N
I/O pin
Schmitt
Trigger
Input
D
Q
WR TRISF
CK
TRIS Latch
Buffer
WR TRISF
RD TRISF
VSS
Analog
CK
TRIS Latch
Q
TTL
Input
Buffer
Input
Mode
RD TRISF
ST
Input
Q
D
Buffer
Q
D
EN
RD PORTF
SS Input
EN
RD PORTF
To A/D Converter or Comparator Input
Note 1: I/O pins have diode protection to VDD and VSS.
Note:
I/O pins have diode protection to VDD and VSS.
DS39612A-page 120
Advance Information
2003 Microchip Technology Inc.
PIC18F6X2X/8X2X
TABLE 10-11: PORTF FUNCTIONS
Name
RF0/AN5
Bit#
Buffer Type
Function
bit 0
ST
ST
ST
ST
ST
ST
Input/output port pin or analog input.
RF1/AN6/C2OUT bit 1
RF2/AN7/C1OUT bit 2
Input/output port pin, analog input or comparator 2 output.
Input/output port pin, analog input or comparator 1 output.
Input/output port pin or analog input/comparator input.
Input/output port pin or analog input/comparator input.
RF3/AN8
RF4/AN9
bit 3
bit 4
bit 5
RF5/AN10/
CVREF
Input/output port pin, analog input/comparator input, or
comparator reference output.
RF6/AN11
RF7/SS
bit 6
bit 7
ST
Input/output port pin or analog input/comparator input.
ST/TTL
Input/output port pin or Slave Select pin for Synchronous Serial Port.
Legend: ST = Schmitt Trigger input, TTL = TTL input
TABLE 10-12: SUMMARY OF REGISTERS ASSOCIATED WITH PORTF
Value on
all other
RESETS
Value on:
POR, BOR
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
TRISF
PORTF Data Direction Control Register
Read PORTF pin/Write PORTF Data Latch
Read PORTF Data Latch/Write PORTF Data Latch
1111 1111 1111 1111
xxxx xxxx uuuu uuuu
0000 0000 uuuu uuuu
PORTF
LATF
ADCON1
CMCON
—
—
VCFG1 VCFG0 PCFG3 PCFG2 PCFG1 PCFG0 --00 0000 --00 0000
C2OUT C1OUT C2INV C1INV CIS CM2 CM1 CM0 0000 0000 0000 0000
CVRCON CVREN CVROE CVRR CVRSS CVR3 CVR2 CVR1 CVR0 0000 0000 0000 0000
Legend: x= unknown, u= unchanged. Shaded cells are not used by PORTF.
2003 Microchip Technology Inc.
Advance Information
DS39612A-page 121
PIC18F6X2X/8X2X
The sixth pin of PORTG (MCLR/VPP/RG5) is a digital
input pin. Its operation is controlled by the MCLRE
configuration bit in Configuration Register 3H
(CONFIG3H<7>). In its default configuration
(MCLRE = 1), the pin functions as the device Master
Clear input. When selected as a port pin (MCLRE = 0),
it functions as an input only pin; as such, it does not
have TRISG or LATG bits associated with it.
10.7 PORTG, TRISG and LATG
Registers
PORTG is a 6-bit wide port with 5 bi-directional pins
(RG0:RG4) and one optional input only pin (RG5). The
corresponding Data Direction register is TRISG. Setting
a TRISG bit (= 1) will make the corresponding PORTG
pin an input (i.e., put the corresponding output driver in
a high-impedance mode). Clearing a TRISG bit (= 0)
will make the corresponding PORTC pin an output (i.e.,
put the contents of the output latch on the selected pin).
In either configuration, RG5 also functions as the
programming voltage input during device programming.
Note 1: On a Power-on Reset, RG5 is enabled as
a digital input only if Master Clear
functionality is disabled (MCLRE = 0).
The Data Latch register (LATG) is also memory
mapped. Read-modify-write operations on the LATG
register, read and write the latched output value for
PORTG.
2: If the device Master Clear is disabled,
verify that either of the following is done to
ensure proper entry into ICSP mode:
a.) disable low voltage programming
(CONFIG4L<2> = 0); or
PORTG is multiplexed with both CCP and USART
functions (Table 10-13). PORTG pins have Schmitt
Trigger input buffers.
When enabling peripheral functions, care should be
taken in defining TRIS bits for each PORTG pin. Some
peripherals override the TRIS bit to make a pin an out-
put, while other peripherals override the TRIS bit to
make a pin an input. The user should refer to the corre-
sponding peripheral section for the correct TRIS bit
settings.
b.) make certain that RB5/KBI1/PGM is
held low during entry into ICSP.
EXAMPLE 10-7:
INITIALIZING PORTG
CLRF
PORTG
;
Initialize PORTG by
; clearing output
; data latches
CLRF
LATG
; Alternate method
; to clear output
; data latches
Note:
On a Power-on Reset, these pins are
configured as digital inputs.
The pin override value is not loaded into the TRIS reg-
ister. This allows read-modify-write operations of the
TRIS register without concern due to peripheral
overrides.
MOVLW
MOVWF
0x04
;
Value used to
; initialize data
; direction
TRISG
;
Set RG1:RG0 as outputs
; RG2 as input
RG4:RG3 as inputs
;
FIGURE 10-16:
PORTG BLOCK DIAGRAM (PERIPHERAL OUTPUT OVERRIDE)
TRIS OVERRIDE
PORTG/Peripheral Out Select
Pin
Override
Peripheral
Peripheral Data Out
VDD
P
0
1
RG0
RG1
Yes
Yes
CCP3 I/O
USART1 Async Xmit,
Sync Clock
RD LATG
Data Bus
RG2
Yes
USART1 Async Rcv,
Sync Data Out
D
Q
Q
I/O pin(1)
WR LATG or
WR PORTG
CK
RG3
RG4
Yes
Yes
CCP4 I/O
CCP5 I/O
Data Latch
N
D
Q
Q
Note 1: I/O pins have diode protection to VDD
VSS
and VSS.
TRIS
Override
Logic
WR TRISG
CK
2: Peripheral output enable is only active
if peripheral select is active.
TRIS Latch
RD TRISG
Schmitt
Trigger
Peripheral Output
Enable(2)
Q
D
EN
RD PORTG
Peripheral Data In
DS39612A-page 122
Advance Information
2003 Microchip Technology Inc.
PIC18F6X2X/8X2X
FIGURE 10-17:
MCLR/VPP/RG5 PIN BLOCK DIAGRAM
MCLRE
Data Bus
MCLR/VPP/RG5
RD TRISA
Schmitt
Trigger
RD LATA
Latch
Q
D
EN
RD PORTA
High Voltage Detect
HV
Internal MCLR
Filter
Low Level
MCLR Detect
TABLE 10-13: PORTG FUNCTIONS
Name
Bit# Buffer Type
Function
RG0/CCP3/P3A
bit 0
bit 1
bit 2
bit 3
bit 4
bit 5
ST
ST
ST
ST
ST
ST
Input/output port pin, Capture3 input/Compare3 output/PWM3 output,
or Enhanced PWM3 output P3A.
RG1/TX2/CK2
RG2/RX2/DT2
RG3/CCP4/P3D
RG4/CCP5/P1D
MCLR/VPP/RG5
Input/output port pin, Addressable USART2 Asynchronous Transmit, or
Addressable USART2 Synchronous Clock.
Input/output port pin, Addressable USART2 Asynchronous Receive, or
Addressable USART2 Synchronous Data.
Input/output port pin, Capture4 input/Compare4 output/PWM4 output,
or Enhanced PWM3 output P3D.
Input/output port pin, Capture5 input/Compare5 output/PWM5 output,
or Enhanced PWM1 output P1D.
Master Clear input or programming voltage input (if MCLR is enabled).
Input only port pin or programming voltage input (if MCLR is
disabled).
Legend: ST = Schmitt Trigger input
TABLE 10-14: SUMMARY OF REGISTERS ASSOCIATED WITH PORTG
Value on
all other
RESETS
Value on
POR, BOR
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PORTG
LATG
—
—
—
—
—
—
RG5(1) Read PORTG pin/Write PORTG Data Latch
--0x xxxx --0u uuuu
---x xxxx ---u uuuu
---1 1111 ---1 1111
—
—
LATG Data Output Register
TRISG
Data Direction Control Register for PORTG
Legend: x= unknown, u= unchanged
Note 1: RG5 is available as an input only when MCLR is disabled.
2003 Microchip Technology Inc.
Advance Information
DS39612A-page 123
PIC18F6X2X/8X2X
FIGURE 10-18:
RH3:RH0 PINS BLOCK
DIAGRAM IN I/O MODE
10.8 PORTH, LATH, and TRISH
Registers
Note:
PORTH is available only on PIC18F8X2X
devices.
RD LATH
Data
Bus
PORTH is an 8-bit wide, bi-directional I/O port. The cor-
responding data direction register is TRISH. Setting a
TRISH bit (= 1) will make the corresponding PORTH
pin an input (i.e., put the corresponding output driver in
a high-impedance mode). Clearing a TRISH bit (= 0)
will make the corresponding PORTH pin an output (i.e.,
put the contents of the output latch on the selected pin).
D
Q
I/O pin(1)
WR LATH
or
PORTH
CK
Data Latch
D
Q
Read-modify-write operations on the LATH register,
read and write the latched output value for PORTH.
Schmitt
Trigger
Input
WR TRISH
RD TRISH
CK
TRIS Latch
Buffer
Pins RH7:RH4 are multiplexed with analog inputs
AN15:AN12. Pins RH3:RH0 are multiplexed with the
system bus as the external memory interface; they are
the high order address bits A19:A16. By default, pins
RH7:RH4 are enabled as A/D inputs and pins
RH3:RH0 are enabled as the system address bus.
Register ADCON1 configures RH7:RH4 as I/O or A/D
inputs. Register MEMCON configures RH3:RH0 as I/O
or system bus pins.
Q
D
EN
RD PORTH
Note 1: On Power-on Reset, PORTH pins
RH7:RH4 default to A/D inputs and read
as ‘0’.
Note 1: I/O pins have diode protection to VDD and VSS.
2: On Power-on Reset, PORTH pins
FIGURE 10-19:
RH7:RH4 PINS BLOCK
DIAGRAM IN I/O MODE
RH3:RH0 default to system bus signals.
EXAMPLE 10-8:
INITIALIZING PORTH
RD LATH
CLRF
PORTH
; Initialize PORTH by
; clearing output
; data latches
; Alternate method
; to clear output
; data latches
;
Data
Bus
D
Q
I/O pin(1)
CLRF
LATH
WR LATH
or
PORTH
CK
Data Latch
MOVLW
MOVWF
MOVLW
0Fh
ADCON1
0CFh
;
D
Q
Schmitt
Trigger
Input
; Value used to
; initialize data
; direction
WR TRISH
CK
TRIS Latch
Buffer
MOVWF
TRISH
; Set RH3:RH0 as inputs
; RH5:RH4 as outputs
; RH7:RH6 as inputs
RD TRISH
Q
D
EN
RD PORTH
To A/D Converter
Note 1: I/O pins have diode protection to VDD and VSS.
DS39612A-page 124
Advance Information
2003 Microchip Technology Inc.
PIC18F6X2X/8X2X
FIGURE 10-20:
RH3:RH0 PINS BLOCK DIAGRAM IN SYSTEM BUS MODE
Q
D
EN
RD PORTH
RD LATH
Data Bus
I/O pin(1)
Port
D
Q
0
1
Data
WR LATH
or
PORTH
CK
Data Latch
D
Q
WR TRISH
RD TRISH
TTL
Input
Buffer
CK
TRIS Latch
External Enable
Address Out
System Bus
Control
Drive System
To Instruction Register
Instruction Read
Note 1: I/O pins have diode protection to VDD and VSS.
2003 Microchip Technology Inc.
Advance Information
DS39612A-page 125
PIC18F6X2X/8X2X
TABLE 10-15: PORTH FUNCTIONS
Name
RH0/A16
Bit#
Buffer Type
Function
bit 0
bit 1
bit 2
bit 3
bit 4
ST/TTL(1)
ST/TTL(1)
ST/TTL(1)
ST/TTL(1)
ST
Input/output port pin or address bit 16 for external memory interface.
Input/output port pin or address bit 17 for external memory interface.
Input/output port pin or address bit 18 for external memory interface.
Input/output port pin or address bit 19 for external memory interface.
RH1/A17
RH2/A18
RH3/A19
RH4/AN12/P3C(2)
Input/output port pin, analog input channel 12 or Enhanced PWM
output P3C.
RH5/AN13/P3B(2)
RH6/AN14/P1C(2)
RH7/AN15/P1B(2)
bit 5
bit 6
bit 7
ST
ST
ST
Input/output port pin, analog input channel 13 or Enhanced PWM
output P3B.
Input/output port pin, analog input channel 14 or Enhanced PWM
output P1C.
Input/output port pin, analog input channel 15 or Enhanced PWM3
output P1B.
Legend: ST = Schmitt Trigger input, TTL = TTL input
Note 1: Input buffers are Schmitt Triggers when in I/O mode and TTL buffers when in System Bus or Parallel Slave
Port mode.
2: Valid only for PIC18F8X2X devices when ECCPMX is not set. The alternate assignments for
P1B/P1C/P3B/P3C in all PIC18F6X2X devices and in PIC18F8X2X devices when ECCPMX is set are RE6,
RE5, RE4 and RE3, respectively.
TABLE 10-16: SUMMARY OF REGISTERS ASSOCIATED WITH PORTH
Value on
Value on:
POR, BOR
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
all other
RESETS
1111 1111
xxxx xxxx
xxxx xxxx
--00 0000
0-00 --00
1111 1111
uuuu uuuu
uuuu uuuu
--00 0000
0-00 --00
TRISH
PORTH Data Direction Control Register
Read PORTH pin/Write PORTH Data Latch
PORTH
LATH
Read PORTH Data Latch/Write PORTH Data Latch
ADCON1
MEMCON
—
—
—
VCFG1 VCFG0 PCFG3 PCFG2 PCFG1 PCFG0
WAIT1 WAIT0 WM1 WM0
EBDIS
—
—
Legend: x= unknown, u= unchanged, - = unimplemented. Shaded cells are not used by PORTH.
DS39612A-page 126
Advance Information
2003 Microchip Technology Inc.
PIC18F6X2X/8X2X
FIGURE 10-21:
PORTJ BLOCK DIAGRAM
IN I/O MODE
10.9 PORTJ, TRISJ and LATJ Registers
Note:
PORTJ is available only on PIC18F8X2X
devices.
RD LATJ
PORTJ is an 8-bit wide, bi-directional port. The corre-
sponding Data Direction register is TRISJ. Setting a
TRISJ bit (= 1) will make the corresponding PORTJ pin
an input (i.e., put the corresponding output driver in a
high-impedance mode). Clearing a TRISJ bit (= 0) will
make the corresponding PORTJ pin an output (i.e., put
the contents of the output latch on the selected pin).
Data
Bus
D
Q
I/O pin(1)
WR LATJ
or
PORTJ
CK
Data Latch
D
Q
The Data Latch register (LATJ) is also memory
mapped. Read-modify-write operations on the LATJ
register, read and write the latched output value for
PORTJ.
Schmitt
Trigger
Input
WR TRISJ
RD TRISJ
CK
TRIS Latch
Buffer
PORTJ is multiplexed with the system bus as the exter-
nal memory interface; I/O port functions are only avail-
able when the system bus is disabled. When operating
as the external memory interface, PORTJ provides the
control signal to external memory devices. The RJ5 pin
is not multiplexed with any system bus functions.
Q
D
EN
When enabling peripheral functions, care should be
taken in defining TRIS bits for each PORTJ pin. Some
peripherals override the TRIS bit to make a pin an out-
put, while other peripherals override the TRIS bit to
make a pin an input. The user should refer to the corre-
sponding peripheral section for the correct TRIS bit
settings.
RD PORTJ
Note 1: I/O pins have diode protection to VDD and VSS.
Note:
On a Power-on Reset, these pins are
configured as digital inputs.
The pin override value is not loaded into the TRIS reg-
ister. This allows read-modify-write of the TRIS register
without concern due to peripheral overrides.
EXAMPLE 10-9:
INITIALIZING PORTJ
CLRF
PORTJ
; Initialize PORTG by
; clearing output
; data latches
CLRF
LATJ
; Alternate method
; to clear output
; data latches
MOVLW
MOVWF
0xCF
; Value used to
; initialize data
; direction
; Set RJ3:RJ0 as inputs
; RJ5:RJ4 as output
; RJ7:RJ6 as inputs
TRISJ
2003 Microchip Technology Inc.
Advance Information
DS39612A-page 127
PIC18F6X2X/8X2X
FIGURE 10-22:
RJ4:RJ0 PINS BLOCK DIAGRAM IN SYSTEM BUS MODE
Q
D
EN
RD PORTJ
RD LATJ
Data Bus
I/O pin(1)
Port
D
Q
0
1
Data
WR LATJ
or
PORTJ
CK
Data Latch
D
Q
WR TRISJ
RD TRISJ
CK
TRIS Latch
Control Out
System Bus
Control
External Enable
Drive System
Note 1: I/O pins have diode protection to VDD and VSS.
FIGURE 10-23:
RJ7:RJ6 PINS BLOCK DIAGRAM IN SYSTEM BUS MODE
Q
D
EN
RD PORTJ
RD LATJ
Data Bus
I/O pin(1)
Port
D
Q
0
1
Data
WR LATJ
or
PORTJ
CK
Data Latch
D
Q
WR TRISJ
CK
TRIS Latch
RD TRISJ
UB/LB Out
WM = 01
System Bus
Control
Drive System
Note 1: I/O pins have diode protection to VDD and VSS.
DS39612A-page 128
Advance Information
2003 Microchip Technology Inc.
PIC18F6X2X/8X2X
TABLE 10-17: PORTJ FUNCTIONS
Name Bit# Buffer Type
RJ0/ALE
Function
bit 0
bit 1
bit 2
bit 3
bit 4
bit 5
bit 6
bit 7
ST
ST
ST
ST
ST
ST
ST
ST
Input/output port pin or Address Latch Enable control for external
memory interface.
RJ1/OE
RJ2/WRL
RJ3/WRH
RJ4/BA0
RJ5/CE
RJ6/LB
Input/output port pin or Output Enable control for external memory
interface.
Input/output port pin or Write Low Byte control for external memory
interface.
Input/output port pin or Write High Byte control for external memory
interface.
Input/output port pin or Byte Address 0 control for external memory
interface.
Input/output port pin or Chip Enable control for external memory
interface.
Input/output port pin or Lower Byte Select control for external
memory interface.
RJ7/UB
Input/output port pin or Upper Byte Select control for external
memory interface.
Legend: ST = Schmitt Trigger input
TABLE 10-18: SUMMARY OF REGISTERS ASSOCIATED WITH PORTJ
Value on
all other
RESETS
Value on
POR, BOR
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PORTJ
LATJ
Read PORTJ pin/Write PORTJ Data Latch
LATJ Data Output Register
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
1111 1111 1111 1111
TRISJ
Data Direction Control Register for PORTJ
Legend: x= unknown, u= unchanged
2003 Microchip Technology Inc.
Advance Information
DS39612A-page 129
PIC18F6X2X/8X2X
FIGURE 10-24:
PORTD AND PORTE
BLOCK DIAGRAM
(PARALLELSLAVEPORT)
10.10 Parallel Slave Port
PORTD also operates as an 8-bit wide parallel slave
port, or microprocessor port, when control bit
PSPMODE (PSPCON<4>) is set. It is asynchronously
readable and writable by the external world through RD
control input pin, RE0/RD and WR control input pin,
RE1/WR.
Data Bus
D
Q
RDx
Pin
WR LATD
CK
Data Latch
or
PORTD
Note:
For PIC18F8X2X devices, the parallel
slave port is available only in
Microcontroller mode.
TTL
Q
D
The PSP can directly interface to an 8-bit micro-
processor data bus. The external microprocessor can
read or write the PORTD latch as an 8-bit latch. Setting
bit PSPMODE enables port pin RE0/RD to be the RD
input, RE1/WR to be the WR input and RE2/CS to be
the CS (chip select) input. For this functionality, the cor-
responding data direction bits of the TRISE register
(TRISE<2:0>) must be configured as inputs (set). The
RD PORTD
EN
TRIS Latch
RD LATD
A/D
port
configuration
bits
PCFG2:PCFG0
One bit of PORTD
(ADCON1<2:0>) must be set, which will configure pins
RE2:RE0 as digital I/O.
Set Interrupt Flag
PSPIF (PIR1<7>)
A write to the PSP occurs when both the CS and WR
lines are first detected low. A read from the PSP occurs
when both the CS and RD lines are first detected low.
The PORTE I/O pins become control inputs for the
microprocessor
port
when
bit
PSPMODE
(PSPCON<4>) is set. In this mode, the user must make
sure that the TRISE<2:0> bits are set (pins are config-
ured as digital inputs) and the ADCON1 is configured
for digital I/O. In this mode, the input buffers are TTL.
Read
RD
CS
TTL
Chip Select
TTL
Write
WR
TTL
Note: I/O pin has protection diodes to VDD and VSS.
DS39612A-page 130
Advance Information
2003 Microchip Technology Inc.
PIC18F6X2X/8X2X
REGISTER 10-1: PSPCON REGISTER
R-0
IBF
R-0
R/W-0
IBOV
R/W-0
U-0
—
U-0
—
U-0
—
U-0
—
OBF
PSPMODE
bit 7
bit 0
bit 7
bit 6
bit 5
IBF: Input Buffer Full Status bit
1= A word has been received and is waiting to be read by the CPU
0= No word has been received
OBF: Output Buffer Full Status bit
1= The output buffer still holds a previously written word
0= The output buffer has been read
IBOV: Input Buffer Overflow Detect bit
1= A write occurred when a previously input word has not been read
(must be cleared in software)
0= No overflow occurred
bit 4
PSPMODE: Parallel Slave Port Mode Select bit
1= Parallel Slave Port mode
0= General Purpose I/O mode
bit 3-0
Unimplemented: Read as ‘0’
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
- n = Value at POR
FIGURE 10-25:
PARALLEL SLAVE PORT WRITE WAVEFORMS
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
CS
WR
RD
PORTD<7:0>
IBF
OBF
PSPIF
2003 Microchip Technology Inc.
Advance Information
DS39612A-page 131
PIC18F6X2X/8X2X
FIGURE 10-26:
PARALLEL SLAVE PORT READ WAVEFORMS
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
CS
WR
RD
PORTD<7:0>
IBF
OBF
PSPIF
TABLE 10-19: REGISTERS ASSOCIATED WITH PARALLEL SLAVE PORT
Value on
all other
RESETS
Value on
POR, BOR
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PORTD
LATD
Port Data Latch when written; Port pins when read
LATD Data Output bits
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
1111 1111 1111 1111
0000 0000 0000 0000
TRISD
PORTE
PORTD Data Direction bits
—
—
—
—
—
Read PORTE pin/
Write PORTE Data Latch
LATE
—
—
—
—
—
—
—
—
—
LATE Data Output bits
xxxx xxxx uuuu uuuu
1111 1111 1111 1111
0000 ---- 0000 ----
0000 0000 0000 0000
TRISE
PSPCON
—
PORTE Data Direction bits
IBF
OBF
IBOV
PSPMODE
INT0IE
TXIF
—
—
—
—
INTCON GIE/GIEH PEIE/GIEL TMR0IF
RBIE
SSPIF
SSPIE
SSPIP
TMR0IF INT0IF
RBIF
(1)
PIR1
PSPIF
PSPIE
PSPIP
ADIF
ADIE
ADIP
RCIF
RCIE
RCIP
CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
CCP1IP TMR2IP TMR1IP 1111 1111 1111 1111
(1)
(1)
PIE1
TXIE
IPR1
TXIP
Legend:
x= unknown, u= unchanged, - = unimplemented, read as ‘0’. Shaded cells are not used by the parallel slave port.
Note 1: Enabled only in Microcontroller mode for PIC18F8X2X devices.
DS39612A-page 132
Advance Information
2003 Microchip Technology Inc.
PIC18F6X2X/8X2X
Figure 11-1 shows a simplified block diagram of the
Timer0 module in 8-bit mode and Figure 11-2 shows a
simplified block diagram of the Timer0 module in 16-bit
mode.
11.0 TIMER0 MODULE
The Timer0 module has the following features:
• Software selectable as an 8-bit or 16-bit timer/
counter
The T0CON register (Register 11-1) is a readable and
writable register that controls all the aspects of Timer0,
including the prescale selection.
• Readable and writable
• Dedicated 8-bit software programmable prescaler
• Clock source selectable to be external or internal
• Interrupt-on-overflow from FFh to 00h in 8-bit
mode and FFFFh to 0000h in 16-bit mode
• Edge select for external clock
REGISTER 11-1: T0CON: TIMER0 CONTROL REGISTER
R/W-1
TMR0ON
bit 7
R/W-1
R/W-1
T0CS
R/W-1
T0SE
R/W-1
PSA
R/W-1
T0PS2
R/W-1
T0PS1
R/W-1
T0PS0
T08BIT
bit 0
bit 7
bit 6
bit 5
bit 4
bit 3
TMR0ON: Timer0 On/Off Control bit
1= Enables Timer0
0= Stops Timer0
T08BIT: Timer0 8-bit/16-bit Control bit
1= Timer0 is configured as an 8-bit timer/counter
0= Timer0 is configured as a 16-bit timer/counter
T0CS: Timer0 Clock Source Select bit
1= Transition on T0CKI pin
0= Internal instruction cycle clock (CLKO)
T0SE: Timer0 Source Edge Select bit
1= Increment on high-to-low transition on T0CKI pin
0= Increment on low-to-high transition on T0CKI pin
PSA: Timer0 Prescaler Assignment bit
1= TImer0 prescaler is not assigned. Timer0 clock input bypasses prescaler.
0= Timer0 prescaler is assigned. Timer0 clock input comes from prescaler output.
bit 2-0 T0PS2:T0PS0: Timer0 Prescaler Select bits
111= 1:256 prescale value
110= 1:128 prescale value
101= 1:64 prescale value
100= 1:32 prescale value
011= 1:16 prescale value
010= 1:8 prescale value
001= 1:4 prescale value
000= 1:2 prescale value
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
- n = Value at POR
2003 Microchip Technology Inc.
Advance Information
DS39612A-page 133
PIC18F6X2X/8X2X
FIGURE 11-1:
TIMER0 BLOCK DIAGRAM IN 8-BIT MODE
Data Bus
FOSC/4
0
1
8
0
Sync with
Internal
Clocks
TMR0
RA4/T0CKI pin
Programmable
Prescaler
1
(2 TCY delay)
T0SE
3
PSA
Set Interrupt
Flag bit TMR0IF
on Overflow
T0PS2, T0PS1, T0PS0
T0CS
Note:
Upon RESET, Timer0 is enabled in 8-bit mode with clock input from T0CKI max. prescale.
FIGURE 11-2:
TIMER0 BLOCK DIAGRAM IN 16-BIT MODE
FOSC/4
0
0
Sync with
Set Interrupt
Flag bit TMR0IF
on Overflow
TMR0
High Byte
Internal
TMR0L
1
Clocks
Programmable
1
T0CKI pin
8
Prescaler
(2 TCY delay)
T0SE
3
Read TMR0L
Write TMR0L
PSA
T0PS2, T0PS1, T0PS0
T0CS
8
8
TMR0H
8
Data Bus<7:0>
Note:
Upon RESET, Timer0 is enabled in 8-bit mode with clock input from T0CKI max. prescale.
DS39612A-page 134
Advance Information
2003 Microchip Technology Inc.
PIC18F6X2X/8X2X
11.2.1
SWITCHING PRESCALER
ASSIGNMENT
11.1 Timer0 Operation
Timer0 can operate as a timer or as a counter.
The prescaler assignment is fully under software con-
trol, (i.e., it can be changed “on-the-fly” during program
execution).
Timer mode is selected by clearing the T0CS bit. In
Timer mode, the Timer0 module will increment every
instruction cycle (without prescaler). If the TMR0 regis-
ter is written, the increment is inhibited for the following
two instruction cycles. The user can work around this
by writing an adjusted value to the TMR0 register.
11.3 Timer0 Interrupt
The TMR0 interrupt is generated when the TMR0 reg-
ister overflows from FFh to 00h in 8-bit mode, or FFFFh
to 0000h in 16-bit mode. This overflow sets the TMR0IF
bit. The interrupt can be masked by clearing the
TMR0IE bit. The TMR0IE bit must be cleared in soft-
ware by the Timer0 module Interrupt Service Routine
before re-enabling this interrupt. The TMR0 interrupt
cannot awaken the processor from SLEEP since the
timer is shut-off during SLEEP.
Counter mode is selected by setting the T0CS bit. In
Counter mode, Timer0 will increment, either on every
rising or falling edge of pin RA4/T0CKI. The increment-
ing edge is determined by the Timer0 Source Edge
Select bit (T0SE). Clearing the T0SE bit selects the ris-
ing edge. Restrictions on the external clock input are
discussed below.
When an external clock input is used for Timer0, it must
meet certain requirements. The requirements ensure
the external clock can be synchronized with the internal
phase clock (TOSC). Also, there is a delay in the actual
incrementing of Timer0 after synchronization.
11.4 16-Bit Mode Timer Reads and
Writes
TMR0H is not the high byte of the timer/counter in
16-bit mode, but is actually a buffered version of the
high byte of Timer0 (refer to Figure 11-2). The high byte
of the Timer0 counter/timer is not directly readable nor
writable. TMR0H is updated with the contents of the
high byte of Timer0 during a read of TMR0L. This pro-
vides the ability to read all 16 bits of Timer0 without
having to verify that the read of the high and low byte
were valid, due to a rollover between successive reads
of the high and low byte.
11.2 Prescaler
An 8-bit counter is available as a prescaler for the Timer0
module. The prescaler is not readable or writable.
The PSA and T0PS2:T0PS0 bits determine the
prescaler assignment and prescale ratio.
Clearing bit PSA will assign the prescaler to the Timer0
module. When the prescaler is assigned to the Timer0
module, prescale values of 1:2, 1:4,..., 1:256 are
selectable.
A write to the high byte of Timer0 must also take place
through the TMR0H Buffer register. Timer0 high byte is
updated with the contents of TMR0H when a write
occurs to TMR0L. This allows all 16 bits of Timer0 to be
updated at once.
When assigned to the Timer0 module, all instructions
writing to the TMR0 register (e.g., CLRF TMR0, MOVWF
TMR0, BSF TMR0, x, and so on) will clear the
prescaler count.
Note:
Writing to TMR0 when the prescaler is
assigned to Timer0 will clear the prescaler
count, but will not change the prescaler
assignment.
TABLE 11-1: REGISTERS ASSOCIATED WITH TIMER0
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2
Value on
all other
RESETS
Value on
POR, BOR
Bit 1
Bit 0
TMR0L Timer0 Module Low Byte Register
TMR0H Timer0 Module High Byte Register
xxxx xxxx uuuu uuuu
0000 0000 0000 0000
INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 0000 0000 0000 0000
T0CON
TRISA
TMR0ON
—
T08BIT
T0CS
T0SE
PSA
T0PS2 T0PS1 T0PS0 1111 1111 1111 1111
PORTA Data Direction Register
-111 1111 -111 1111
Legend: x= unknown, u= unchanged, - = unimplemented locations, read as ‘0’.
Shaded cells are not used by Timer0.
2003 Microchip Technology Inc.
Advance Information
DS39612A-page 135
PIC18F6X2X/8X2X
NOTES:
DS39612A-page 136
Advance Information
2003 Microchip Technology Inc.
PIC18F6X2X/8X2X
Register 12-1 details the Timer1 Control register. This
register controls the operating mode of the Timer1
module, and contains the Timer1 oscillator enable bit
(T1OSCEN). Timer1 can be enabled or disabled by
setting or clearing control bit, TMR1ON (T1CON<0>).
12.0 TIMER1 MODULE
The Timer1 module timer/counter has the following
features:
• 16-bit timer/counter
(two 8-bit registers; TMR1H and TMR1L)
Timer1 can also be used to provide Real-Time Clock
(RTC) functionality to applications with only a minimal
addition of external components and code overhead.
• Readable and writable (both registers)
• Internal or external clock select
• Interrupt-on-overflow from FFFFh to 0000h
• RESET from CCP module special event trigger
Figure 12-1 is a simplified block diagram of the Timer1
module.
REGISTER 12-1: T1CON: TIMER1 CONTROL REGISTER
R/W-0
RD16
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON
bit 0
bit 7
bit 7
bit 6
RD16: 16-bit Read/Write Mode Enable bit
1= Enables register read/write of Timer1 in one 16-bit operation
0= Enables register read/write of Timer1 in two 8-bit operations
Unimplemented: Read as ‘0’
bit 5-4 T1CKPS1:T1CKPS0: Timer1 Input Clock Prescale Select bits
11= 1:8 prescale value
10= 1:4 prescale value
01= 1:2 prescale value
00= 1:1 prescale value
bit 3
bit 2
T1OSCEN: Timer1 Oscillator Enable bit
1= Timer1 Oscillator is enabled
0= Timer1 Oscillator is shut-off
The oscillator inverter and feedback resistor are turned off to eliminate power drain.
T1SYNC: Timer1 External Clock Input Synchronization Select bit
When TMR1CS = 1:
1= Do not synchronize external clock input
0= Synchronize external clock input
When TMR1CS = 0:
This bit is ignored. Timer1 uses the internal clock when TMR1CS = 0.
bit 1
bit 0
TMR1CS: Timer1 Clock Source Select bit
1= External clock from pin RC0/T1OSO/T13CKI (on the rising edge)
0= Internal clock (FOSC/4)
TMR1ON: Timer1 On bit
1= Enables Timer1
0= Stops Timer1
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
- n = Value at POR
2003 Microchip Technology Inc.
Advance Information
DS39612A-page 137
PIC18F6X2X/8X2X
When TMR1CS = 0, Timer1 increments every instruc-
tion cycle. When TMR1CS = 1, Timer1 increments on
every rising edge of the external clock input or the
Timer1 oscillator, if enabled.
12.1 Timer1 Operation
Timer1 can operate in one of these modes:
• As a timer
• As a synchronous counter
• As an asynchronous counter
When the Timer1 oscillator is enabled (T1OSCEN is
set), the RC1/T1OSI and RC0/T1OSO/T13CKI pins
become inputs. That is, the TRISC<1:0> value is
ignored, and the pins are read as ‘0’.
The operating mode is determined by the clock select
bit, TMR1CS (T1CON<1>).
Timer1 also has an internal “RESET input”. This
RESET can be generated by ECCP1 or ECCP2 special
event trigger. This is discussed in detail in Section 12.4.
FIGURE 12-1:
TIMER1 BLOCK DIAGRAM
CCP Special Event Trigger
TMR1IF
Overflow
Interrupt
Flag Bit
Synchronized
TMR1
CLR
0
Clock Input
TMR1L
TMR1H
1
TMR1ON
On/Off
T1SYNC
T1OSC
1
T1OSO/T13CKI
T1OSI
Synchronize
det
T1OSCEN
Enable
Oscillator
Prescaler
1, 2, 4, 8
FOSC/4
Internal
Clock
(1)
0
2
SLEEP Input
T1CKPS1:T1CKPS0
TMR1CS
Note 1: When enable bit T1OSCEN is cleared, the inverter and feedback resistor are turned off. This eliminates power drain.
FIGURE 12-2:
TIMER1 BLOCK DIAGRAM: 16-BIT READ/WRITE MODE
Data Bus<7:0>
8
TMR1H
8
8
Write TMR1L
Read TMR1L
CCP Special Event Trigger
0
TMR1IF
Overflow
Interrupt
Synchronized
Clock Input
TMR1
8
CLR
Timer 1
High Byte
TMR1L
Flag bit
1
TMR1ON
T1SYNC
On/Off
T1OSC
T1OSO/T13CKI
1
Synchronize
det
Prescaler
1, 2, 4, 8
T1OSCEN
FOSC/4
Internal
Clock
Enable
0
(1)
T1OSI
Oscillator
2
SLEEP Input
TMR1CS
T1CKPS1:T1CKPS0
Note 1: When enable bit T1OSCEN is cleared, the inverter and feedback resistor are turned off. This eliminates power drain.
DS39612A-page 138
Advance Information
2003 Microchip Technology Inc.
PIC18F6X2X/8X2X
12.2 Timer1 Oscillator
12.3 Timer1 Interrupt
A crystal oscillator circuit is built-in between pins T1OSI
(input) and T1OSO (amplifier output). It is enabled by
setting control bit T1OSCEN (T1CON<3>). The oscilla-
tor is a low power oscillator rated up to 200 kHz. It will
continue to run during SLEEP. It is primarily intended
for a 32 kHz crystal. The circuit for a typical LP oscilla-
tor is shown in Figure 12-3. Table 12-1 shows the
capacitor selection for the Timer1 oscillator.
The TMR1 register pair (TMR1H:TMR1L) increments
from 0000h to FFFFh and rolls over to 0000h. The
TMR1 interrupt, if enabled, is generated on overflow
which is latched in interrupt flag bit, TMR1IF
(PIR1<0>). This interrupt can be enabled/disabled by
setting/clearing TMR1 interrupt enable bit, TMR1IE
(PIE1<0>).
12.4 Resetting Timer1 Using an ECCP
Special Trigger Output
The user must provide a software time delay to ensure
proper start-up of the Timer1 oscillator
If either the ECCP1 or ECCP2 module is configured in
Compare mode to generate a “special event trigger”
(CCP1M3:CCP1M0 = 1011), this signal will reset
Timer1. The trigger for ECCP2 will also start an A/D
conversion if the A/D module is enabled.
FIGURE 12-3:
EXTERNAL
COMPONENTS FOR THE
TIMER1 LP OSCILLATOR
C1
33 pF
PIC18F6X2X/8X2X
Note:
The special event triggers from the CCP1
module will not set interrupt flag bit
TMR1IF (PIR1<0>).
T1OSI
XTAL
32.768 kHz
Timer1 must be configured for either Timer or Synchro-
nized Counter mode to take advantage of this feature.
If Timer1 is running in Asynchronous Counter mode,
this RESET operation may not work.
T1OSO
C2
33 pF
In the event that a write to Timer1 coincides with a
special event trigger from ECCP1, the write will take
precedence.
Note:
See the notes with Table 12-1 for additional
information about capacitor selection.
In this mode of operation, the CCPR1H:CCPR1L regis-
ter pair effectively becomes the period register for
Timer1.
TABLE 12-1: CAPACITOR SELECTION
FOR THE ALTERNATE
12.5 Timer1 16-Bit Read/Write Mode
OSCILLATOR
Osc Type
Freq
C1
C2
Timer1 can be configured for 16-bit reads and writes
(see Figure 12-2). When the RD16 control bit
(T1CON<7>) is set, the address for TMR1H is mapped
to a buffer register for the high byte of Timer1. A read
from TMR1L will load the contents of the high byte of
Timer1 into the Timer1 high byte buffer. This provides
the user with the ability to accurately read all 16 bits of
Timer1 without having to determine whether a read of
the high byte, followed by a read of the low byte, is valid
due to a rollover between reads.
LP
32 kHz
TBD(1)
TBD(1)
Crystal to be Tested:
32.768 kHz Epson C-001R32.768K-A
20 PPM
Note 1: Microchip suggests 33 pF as a starting
point in validating the oscillator circuit.
2: Higher capacitance increases the stability
of the oscillator but also increases the
start-up time.
A write to the high byte of Timer1 must also take place
through the TMR1H Buffer register. Timer1 high byte is
updated with the contents of TMR1H when a write
occurs to TMR1L. This allows a user to write all 16 bits
to both the high and low bytes of Timer1 at once.
3: Since each resonator/crystal has its own
characteristics, the user should consult
the resonator/crystal manufacturer for
The high byte of Timer1 is not directly readable or writ-
able in this mode. All reads and writes must take place
through the Timer1 High Byte Buffer register. Writes to
TMR1H do not clear the Timer1 prescaler. The
prescaler is only cleared on writes to TMR1L.
appropriate
components.
values
of
external
4: Capacitor values are for design guidance
only.
2003 Microchip Technology Inc.
Advance Information
DS39612A-page 139
PIC18F6X2X/8X2X
tine which increments the seconds counter by one;
additional counters for minutes and hours are
incremented as the previous counter overflow.
12.6 Using Timer1 as a Real-Time
Clock
Adding an external LP oscillator to Timer1 (such as the
one described in Section 12.2) gives users the option
to include RTC functionality to their applications. This is
accomplished with an inexpensive watch crystal to pro-
vide an accurate time base, and several lines of appli-
cation code to calculate the time. When operating in
SLEEP mode and using a battery or supercapacitor as
a power source, it can completely eliminate the need
for a separate RTC device and battery backup.
Since the register pair is 16 bits wide, counting up to
overflow the register directly from a 32.768 kHz clock
would take 2 seconds. To force the overflow at the
required one-second intervals, it is necessary to pre-
load it; the simplest method is to set the MSbit of
TMR1H with a BSF instruction. Note that the TMR1L
register is never preloaded or altered; doing so may
introduce cumulative error over many cycles.
For this method to be accurate, Timer1 must operate in
Asynchronous mode, and the Timer1 overflow interrupt
must be enabled (PIE1<0> = 1), as shown in the rou-
tine, RTCinit. The Timer1 oscillator must also be
enabled and running at all times.
The application code routine, RTCisr, shown in
Example 12-1, demonstrates a simple method to incre-
ment a counter at one-second intervals using an Inter-
rupt Service Routine. Incrementing the TMR1 register
pair to overflow, triggers the interrupt and calls the rou-
EXAMPLE 12-1:
IMPLEMENTING A REAL-TIME CLOCK USING A TIMER1 INTERRUPT SERVICE
RTCinit
MOVLW
MOVWF
CLRF
0x80
TMR1H
TMR1L
; Preload TMR1 register pair
; for 1 second overflow
MOVLW
MOVWF
CLRF
b’00001111’
T1OSC
secs
; Configure for external clock,
; Asynchronous operation, external oscillator
; Initialize timekeeping registers
;
CLRF
mins
MOVLW
MOVWF
BSF
.12
hours
PIE1, TMR1IE
; Enable Timer1 interrupt
RETURN
RTCisr
BSF
BCF
INCF
MOVLW
TMR1H,7
PIR1,TMR1IF
secs,F
; Preload for 1 sec overflow
; Clear interrupt flag
; Increment seconds
.59
; 60 seconds elapsed?
CPFSGT secs
RETURN
; No, done
CLRF
INCF
MOVLW
secs
mins,F
.59
; Clear seconds
; Increment minutes
; 60 minutes elapsed?
CPFSGT mins
RETURN
; No, done
CLRF
INCF
MOVLW
mins
hours,F
.23
; clear minutes
; Increment hours
; 24 hours elapsed?
CPFSGT hours
RETURN
; No, done
MOVLW
MOVWF
RETURN
.01
hours
; Reset hours to 1
; Done
DS39612A-page 140
Advance Information
2003 Microchip Technology Inc.
PIC18F6X2X/8X2X
TABLE 12-2: REGISTERS ASSOCIATED WITH TIMER1 AS A TIMER/COUNTER
Value on
all other
RESETS
Value on
POR, BOR
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
INTCON GIE/GIEH PEIE/GIEL TMR0IE
INT0IE
TXIF
RBIE
SSPIF
SSPIE
SSPIP
TMR0IF
INT0IF
RBIF
0000 0000 0000 0000
PIR1
PSPIF
PSPIE
PSPIP
ADIF
ADIE
ADIP
RCIF
RCIE
RCIP
CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
CCP1IP TMR2IP TMR1IP 1111 1111 1111 1111
PIE1
TXIE
TXIP
IPR1
TMR1L
Holding Register for the Least Significant Byte of the 16-bit TMR1 Register
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
TMR1H Holding Register for the Most Significant Byte of the 16-bit TMR1 Register
T1CON
Legend:
RD16
—
T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 0-00 0000 u-uu uuuu
x= unknown, u= unchanged, - = unimplemented, read as ‘0’. Shaded cells are not used by the Timer1 module.
2003 Microchip Technology Inc.
Advance Information
DS39612A-page 141
PIC18F6X2X/8X2X
NOTES:
DS39612A-page 142
Advance Information
2003 Microchip Technology Inc.
PIC18F6X2X/8X2X
13.1 Timer2 Operation
13.0 TIMER2 MODULE
Timer2 can be used as the PWM time base for the
PWM mode of the CCP module. The TMR2 register is
readable and writable and is cleared on any device
RESET. The input clock (FOSC/4) has a prescale option
of 1:1, 1:4 or 1:16, selected by control bits
T2CKPS1:T2CKPS0 (T2CON<1:0>). The match out-
put of TMR2 goes through a 4-bit postscaler (which
gives a 1:1 to 1:16 scaling inclusive) to generate a
TMR2 interrupt, latched in flag bit TMR2IF (PIR1<1>).
The Timer2 module timer has the following features:
• 8-bit timer (TMR2 register)
• 8-bit period register (PR2)
• Readable and writable (both registers)
• Software programmable prescaler (1:1, 1:4, 1:16)
• Software programmable postscaler (1:1 to 1:16)
• Interrupt on TMR2 match of PR2
• SSP module optional use of TMR2 output to
generate clock shift
The prescaler and postscaler counters are cleared
when any of the following occurs:
Timer2 has a control register shown in Register 13-1.
Timer2 can be shut-off by clearing control bit TMR2ON
(T2CON<2>) to minimize power consumption.
Figure 13-1 is a simplified block diagram of the Timer2
module. Register 13-1 shows the Timer2 Control regis-
ter. The prescaler and postscaler selection of Timer2
are controlled by this register.
• a write to the TMR2 register
• a write to the T2CON register
• any device RESET (Power-on Reset, MCLR
Reset, Watchdog Timer Reset, or Brown-out
Reset)
TMR2 is not cleared when T2CON is written.
REGISTER 13-1: T2CON: TIMER2 CONTROL REGISTER
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
T2OUTPS3 T2OUTPS2 T2OUTPS1 T2OUTPS0 TMR2ON T2CKPS1 T2CKPS0
bit 0
bit 7
bit 7
Unimplemented: Read as ‘0’
bit 6-3 T2OUTPS3:T2OUTPS0: Timer2 Output Postscale Select bits
0000= 1:1 postscale
0001= 1:2 postscale
•
•
•
1111= 1:16 postscale
bit 2
TMR2ON: Timer2 On bit
1= Timer2 is on
0= Timer2 is off
bit 1-0 T2CKPS1:T2CKPS0: Timer2 Clock Prescale Select bits
00= Prescaler is 1
01= Prescaler is 4
1x= Prescaler is 16
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
- n = Value at POR
2003 Microchip Technology Inc.
Advance Information
DS39612A-page 143
PIC18F6X2X/8X2X
13.2 Timer2 Interrupt
13.3 Output of TMR2
The Timer2 module has an 8-bit period register, PR2.
Timer2 increments from 00h until it matches PR2 and
then resets to 00h on the next increment cycle. PR2 is
a readable and writable register. The PR2 register is
initialized to FFh upon RESET.
The output of TMR2 (before the postscaler) is fed to the
synchronous serial port module which optionally uses it
to generate the shift clock.
FIGURE 13-1:
TIMER2 BLOCK DIAGRAM
Sets Flag
TMR2
bit TMR2IF
(1)
Output
Prescaler
RESET
EQ
TMR2
FOSC/4
1:1, 1:4, 1:16
Postscaler
1:1 to 1:16
2
Comparator
T2CKPS1:T2CKPS0
4
PR2
T2OUTPS3:T2OUTPS0
Note 1: TMR2 register output can be software selected by the SSP module as a baud clock.
TABLE 13-1: REGISTERS ASSOCIATED WITH TIMER2 AS A TIMER/COUNTER
Value on
all other
RESETS
Value on
POR, BOR
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
INTCON GIE/GIEH PEIE/GIEL TMR0IE
INT0IE
TXIF
RBIE
SSPIF
SSPIE
SSPIP
TMR0IF
INT0IF
RBIF
0000 0000 0000 0000
PIR1
PSPIF
PSPIE
PSPIP
ADIF
ADIE
ADIP
RCIF
RCIE
RCIP
CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
CCP1IP TMR2IP TMR1IP 1111 1111 1111 1111
0000 0000 0000 0000
PIE1
TXIE
TXIP
IPR1
TMR2
T2CON
PR2
Timer2 Module Register
—
T2OUTPS3 T2OUTPS2 T2OUTPS1 T2OUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 -000 0000
Timer2 Period Register 1111 1111 1111 1111
x= unknown, u= unchanged, - = unimplemented, read as ‘0’. Shaded cells are not used by the Timer2 module.
Legend:
DS39612A-page 144
Advance Information
2003 Microchip Technology Inc.
PIC18F6X2X/8X2X
Figure 14-1 is a simplified block diagram of the Timer3
module.
14.0 TIMER3 MODULE
The Timer3 module timer/counter has the following
features:
Register 14-1 shows the Timer3 Control register. This
register controls the operating mode of the Timer3
module and sets the CCP clock source.
• 16-bit timer/counter
(two 8-bit registers: TMR3H and TMR3L)
Register 12-1 shows the Timer1 Control register. This
register controls the operating mode of the Timer1
module, as well as contains the Timer1 oscillator
enable bit (T1OSCEN) which can be a clock source for
Timer3.
• Readable and writable (both registers)
• Internal or external clock select
• Interrupt-on-overflow from FFFFh to 0000h
• RESET from CCP module trigger
REGISTER 14-1: T3CON: TIMER3 CONTROL REGISTER
R/W-0
RD16
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
T3CCP2 T3CKPS1 T3CKPS0 T3CCP1 T3SYNC TMR3CS TMR3ON
bit 0
bit 7
bit 7
RD16: 16-bit Read/Write Mode Enable bit
1= Enables register read/write of Timer3 in one 16-bit operation
0= Enables register read/write of Timer3 in two 8-bit operations
bit 6,3 T3CCP2:T3CCP1: Timer3 and Timer1 to CCPx Enable bits
11=Timer3 and Timer4 are the clock sources for CCP1 through CCP5
10=Timer3 and Timer4 are the clock sources for CCP3 through CCP5;
Timer1 and Timer2 are the clock sources for CCP1 and CCP2
01=Timer3 and Timer4 are the clock sources for CCP2 through CCP5;
Timer1 and Timer2 are the clock sources for CCP1
00=Timer1 and Timer2 are the clock sources for CCP1 through CCP5
bit 5-4 T3CKPS1:T3CKPS0: Timer3 Input Clock Prescale Select bits
11= 1:8 prescale value
10= 1:4 prescale value
01= 1:2 prescale value
00= 1:1 prescale value
bit 2
T3SYNC: Timer3 External Clock Input Synchronization Control bit
(Not usable if the system clock comes from Timer1/Timer3.)
When TMR3CS = 1:
1= Do not synchronize external clock input
0= Synchronize external clock input
When TMR3CS = 0:
This bit is ignored. Timer3 uses the internal clock when TMR3CS = 0.
bit 1
bit 0
TMR3CS: Timer3 Clock Source Select bit
1= External clock input from Timer1 oscillator or T13CKI
(on the rising edge after the first falling edge)
0= Internal clock (FOSC/4)
TMR3ON: Timer3 On bit
1= Enables Timer3
0= Stops Timer3
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
- n = Value at POR
2003 Microchip Technology Inc.
Advance Information
DS39612A-page 145
PIC18F6X2X/8X2X
When TMR3CS = 0, Timer3 increments every instruc-
tion cycle. When TMR3CS = 1, Timer3 increments on
every rising edge of the Timer1 external clock input or
the Timer1 oscillator, if enabled.
14.1 Timer3 Operation
Timer3 can operate in one of these modes:
• As a timer
• As a synchronous counter
• As an asynchronous counter
When the Timer1 oscillator is enabled (T1OSCEN is
set), the RC1/T1OSI and RC0/T1OSO/T13CKI pins
become inputs. That is, the TRISC<1:0> value is
ignored and the pins are read as ‘0’.
The operating mode is determined by the clock select
bit, TMR3CS (T3CON<1>).
Timer3 also has an internal “RESET input”. This RESET
can be generated by the CCP module (Section 14.0).
FIGURE 14-1:
TIMER3 BLOCK DIAGRAM
CCP Special Trigger
T3CCPx
TMR3IF
Overflow
Interrupt
Synchronized
Clock Input
0
Flag bit
CLR
TMR3L
TMR3H
T1OSC
1
TMR3ON
On/Off
T3SYNC
(3)
T1OSO/
T13CKI
1
Synchronize
det
Prescaler
1, 2, 4, 8
T1OSCEN
Enable
FOSC/4
Internal
Clock
0
(1)
T1OSI
Oscillator
2
SLEEP Input
TMR3CS
T3CKPS1:T3CKPS0
Note 1: When enable bit T1OSCEN is cleared, the inverter and feedback resistor are turned off. This eliminates power drain.
FIGURE 14-2:
TIMER3 BLOCK DIAGRAM CONFIGURED IN 16-BIT READ/WRITE MODE
Data Bus<7:0>
8
TMR3H
8
8
Write TMR3L
Read TMR3L
CCP Special Trigger
T3CCPx
0
Synchronized
Clock Input
Set TMR3IF Flag bit
on Overflow
8
TMR3
CLR
Timer3
High Byte
TMR3L
1
To Timer1 Clock Input
TMR3ON
On/Off
T3SYNC
T1OSC
T1OSO/
T13CKI
1
Synchronize
det
Prescaler
1, 2, 4, 8
T1OSCEN
Enable
Oscillator
FOSC/4
Internal
Clock
0
(1)
T1OSI
2
SLEEP Input
T3CKPS1:T3CKPS0
TMR3CS
Note 1: When the T1OSCEN bit is cleared, the inverter and feedback resistor are turned off. This eliminates power drain.
DS39612A-page 146
Advance Information
2003 Microchip Technology Inc.
PIC18F6X2X/8X2X
14.2 Timer1 Oscillator
14.4 Resetting Timer3 Using an ECCP
Special Trigger Output
The Timer1 oscillator may be used as the clock source
for Timer3. The Timer1 oscillator is enabled by setting
the T1OSCEN (T1CON<3>) bit. The oscillator is a low
power oscillator rated up to 200 kHz. See Section 12.0
for further details.
If either the ECCP1 or ECCP2 module is configured in
Compare mode to generate a special event trigger
(CCP1M3:CCP1M0 = 1011), this signal will reset
Timer3.
Note:
The special event triggers from the CCP
module will not set interrupt flag bit,
TMR3IF (PIR1<0>).
14.3 Timer3 Interrupt
The TMR3 register pair (TMR3H:TMR3L) increments
from 0000h to FFFFh and rolls over to 0000h. The
TMR3 interrupt, if enabled, is generated on overflow
which is latched in interrupt flag bit, TMR3IF
(PIR2<1>). This interrupt can be enabled/disabled by
setting/clearing TMR3 interrupt enable bit, TMR3IE
(PIE2<1>).
Timer3 must be configured for either Timer or Synchro-
nized Counter mode to take advantage of this feature.
If Timer3 is running in Asynchronous Counter mode,
this RESET operation may not work. In the event that a
write to Timer3 coincides with a special event trigger
from ECCP1, the write will take precedence. In this
mode of operation, the CCPR1H:CCPR1L register pair
effectively becomes the period register for Timer3.
TABLE 14-1: REGISTERS ASSOCIATED WITH TIMER3 AS A TIMER/COUNTER
Value on
all other
RESETS
Value on
POR, BOR
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
INTCON
GIE/
GIEH
PEIE/
GIEL
TMR0IE
INT0IE
RBIE
TMR0IF
INT0IF
RBIF
0000 0000 0000 0000
PIR2
—
—
—
—
—
—
—
—
—
EEIF
EEIE
EEIP
BCLIF
BCLIE
BCLIP
LVDIF
LVDIE
LVDIP
TMR3IF
TMR3IE
TMR3IP
CCP2IF ---0 0000 ---0 0000
CCP2IE ---0 0000 ---0 0000
CCP2IP ---1 1111 ---1 1111
xxxx xxxx uuuu uuuu
PIE2
IPR2
TMR3L
TMR3H
T1CON
T3CON
Legend:
Holding Register for the Least Significant Byte of the 16-bit TMR3 Register
Holding Register for the Most Significant Byte of the 16-bit TMR3 Register
xxxx xxxx uuuu uuuu
RD16
RD16
—
T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 0-00 0000 u-uu uuuu
T3CCP2 T3CKPS1 T3CKPS0 T3CCP1 T3SYNC TMR3CS TMR3ON 0000 0000 uuuu uuuu
x= unknown, u= unchanged, - = unimplemented, read as ‘0’. Shaded cells are not used by the Timer3 module.
2003 Microchip Technology Inc.
Advance Information
DS39612A-page 147
PIC18F6X2X/8X2X
NOTES:
DS39612A-page 148
Advance Information
2003 Microchip Technology Inc.
PIC18F6X2X/8X2X
15.1 Timer4 Operation
15.0 TIMER4 MODULE
Timer4 can be used as the PWM time base for the
PWM mode of the CCP module. The TMR4 register is
readable and writable and is cleared on any device
RESET. The input clock (FOSC/4) has a prescale option
of 1:1, 1:4 or 1:16, selected by control bits
T4CKPS1:T4CKPS0 (T4CON<1:0>). The match out-
put of TMR4 goes through a 4-bit postscaler (which
gives a 1:1 to 1:16 scaling inclusive) to generate a
TMR4 interrupt, latched in flag bit TMR4IF (PIR3<3>).
The Timer4 module timer has the following features:
• 8-bit timer (TMR4 register)
• 8-bit period register (PR4)
• Readable and writable (both registers)
• Software programmable prescaler (1:1, 1:4, 1:16)
• Software programmable postscaler (1:1 to 1:16)
• Interrupt on TMR4 match of PR4
Timer4 has a control register shown in Register 15-1.
Timer4 can be shut-off by clearing control bit, TMR4ON
(T4CON<2>), to minimize power consumption. The
prescaler and postscaler selection of Timer4 are also
controlled by this register. Figure 15-1 is a simplified
block diagram of the Timer4 module.
The prescaler and postscaler counters are cleared
when any of the following occurs:
• a write to the TMR4 register
• a write to the T4CON register
• any device RESET (Power-on Reset, MCLR
Reset, Watchdog Timer Reset, or Brown-out
Reset)
TMR4 is not cleared when T4CON is written.
REGISTER 15-1: T4CON: TIMER4 CONTROL REGISTER
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
T4OUTPS3 T4OUTPS2 T4OUTPS1 T4OUTPS0 TMR4ON T4CKPS1 T4CKPS0
bit 0
bit 7
bit 7
Unimplemented: Read as ‘0’
bit 6-3 T4OUTPS3:T4OUTPS0: Timer4 Output Postscale Select bits
0000= 1:1 postscale
0001= 1:2 postscale
•
•
•
1111= 1:16 postscale
bit 2
TMR4ON: Timer4 On bit
1= Timer4 is on
0= Timer4 is off
bit 1-0 T4CKPS1:T4CKPS0: Timer4 Clock Prescale Select bits
00= Prescaler is 1
01= Prescaler is 4
1x= Prescaler is 16
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
- n = Value at POR
2003 Microchip Technology Inc.
Advance Information
DS39612A-page 149
PIC18F6X2X/8X2X
15.2 Timer4 Interrupt
15.3 Output of TMR4
The Timer4 module has an 8-bit period register, PR4,
which is both readable and writable. Timer4 increments
from 00h until it matches PR4 and then resets to 00h on
the next increment cycle. The PR4 register is initialized
to FFh upon RESET.
The output of TMR4 (before the postscaler) is used
only as a PWM time base for the CCP modules. It is not
used as a baud rate clock for the MSSP, as is the
Timer2 output.
FIGURE 15-1:
TIMER4 BLOCK DIAGRAM
Sets Flag
TMR4
bit TMR4IF
(1)
Output
Prescaler
RESET
EQ
TMR4
FOSC/4
1:1, 1:4, 1:16
Postscaler
1:1 to 1:16
2
Comparator
PR4
T4CKPS1:T4CKPS0
4
T4OUTPS3:T4OUTPS0
TABLE 15-1: REGISTERS ASSOCIATED WITH TIMER4 AS A TIMER/COUNTER
Value on
all other
RESETS
Value on
POR, BOR
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
INTCON GIE/GIEH PEIE/GIEL TMR0IE
INT0IE
TX2IP
TX2IF
TX2IE
RBIE
TMR0IF
INT0IF
RBIF
0000 0000 0000 0000
IPR3
—
—
—
—
—
—
RC2IP
RC2IF
RC2IE
TMR4IP
TMR4IF
TMR4IE
CCP5IP CCP4IP CCP3IP --11 1111 --00 0000
CCP5IF CCP4IF CCP3IF --00 0000 --00 0000
CCP5IE CCP4IE CCP3IE --00 0000 --00 0000
0000 0000 0000 0000
PIR3
PIE3
TMR4
T4CON
PR4
Timer4 Module Register
—
T4OUTPS3 T4OUTPS2 T4OUTPS1 T4OUTPS0 TMR4ON T4CKPS1 T4CKPS0 -000 0000 -000 0000
Timer4 Period Register 1111 1111 1111 1111
x= unknown, u= unchanged, - = unimplemented, read as ‘0’. Shaded cells are not used by the Timer4 module.
Legend:
DS39612A-page 150
Advance Information
2003 Microchip Technology Inc.
PIC18F6X2X/8X2X
Capture and Compare operations described in this
chapter apply to all standard and enhanced CCP mod-
ules. The operations of PWM mode described in
Section 16.4 applies to CCP4 and CCP5 only.
16.0 CAPTURE/COMPARE/PWM
(CCP) MODULES
PIC18F6X2X/8X2X devices all have a total of five CCP
(Capture/Compare/PWM) modules. Two of these
(CCP4 and CCP5) implement standard Capture, Com-
pare and Pulse Width Modulation (PWM) modes, and
are discussed in this section. The other three modules
(ECCP1, ECCP2, ECCP3) implement standard Cap-
ture and Compare modes, as well as enhanced PWM
modes. These are discussed in Section 17.0.
Note:
Throughout this section and Section 17.0,
references to register and bit names that
may be associated with a specific CCP
module are referred to generically by the
use of ‘x’ or ‘y’ in place of the specific mod-
ule number. Thus, “CCPxCON” might refer
to the control register for CCP4 or CCP5, or
ECCP1, ECCP2 or ECCP3. “CCPxCON” is
used throughout these sections to refer to
the module control register, regardless of
whether the CCP module is a standard or
enhanced implementation.
Each CCP/ECCP module contains a 16-bit register
which can operate as a 16-bit Capture register, a 16-bit
Compare register or a PWM Master/Slave Duty Cycle
register. For the sake of clarity, all CCP module opera-
tion in the following sections is described with respect
to CCP4, but is equally applicable to CCP5.
REGISTER 16-1: CCPxCON REGISTER (CCP4 AND CCP5 MODULES)
U-0
—
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
DCxB1
DCxB0
CCPxM3 CCPxM2 CCPxM1 CCPxM0
bit 0
bit 7
bit 7-6
bit 5-4
Unimplemented: Read as ‘0’
DCxB1:DCxB0: PWM Duty Cycle bit 1 and bit 0 for CCP Module x
Capture mode:
Unused
Compare mode:
Unused
PWM mode:
These bits are the two LSbits (bit 1 and bit 0) of the 10-bit PWM duty cycle. The eight MSbits
(DCx9:DCx2) of the duty cycle are found in CCPRxL.
bit 3-0
CCPxM3:CCPxM0: CCP Module x Mode Select bits
0000= Capture/Compare/PWM disabled (resets CCPx module)
0001= Reserved
0010= Compare mode, toggle output on match (CCPxIF bit is set)
0011= Reserved
0100= Capture mode, every falling edge
0101= Capture mode, every rising edge
0110= Capture mode, every 4th rising edge
0111= Capture mode, every 16th rising edge
1000= Compare mode; initialize CCP pin low; on compare match, force CCP pin high
(CCPIF bit is set)
1001= Compare mode; initialize CCP pin high; on compare match, force CCP pin low
(CCPIF bit is set)
1010= Compare mode; generate software interrupt on compare match (CCPIF bit is set,
CCP pin reflects I/O state)
1011= Reserved
11xx= PWM mode
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
- n = Value at POR
2003 Microchip Technology Inc.
Advance Information
DS39612A-page 151
PIC18F6X2X/8X2X
TABLE 16-1: CCP MODE - TIMER
RESOURCE
16.1 CCP Module Configuration
Each Capture/Compare/PWM module is associated
with a control register (generically, CCPxCON) and a
data register (CCPRx). The data register in turn is com-
prised of two 8-bit registers: CCPRxL (low byte) and
CCPRxH (high byte). All registers are both readable
and writable.
CCP Mode
Timer Resource
Capture
Compare
PWM
Timer1 or Timer3
Timer1 or Timer3
Timer2 or Timer4
The assignment of a particular timer to a module is
determined by the Timer-to-CCP enable bits in the
T3CON register (Register 14-1, page 145). Depending
on the configuration selected, up to four timers may be
active at once, with modules in the same configuration
(Capture/Compare or PWM) sharing timer resources.
The possible configurations are shown in Figure 16-1.
16.1.1
CCP MODULES AND TIMER
RESOURCES
The CCP/ECCP modules utilize Timers 1, 2, 3 or 4,
depending on the mode selected. Timer1 and Timer3
are available to modules in Capture or Compare
modes, while Timer2 and Timer4 are available for
modules in PWM mode.
FIGURE 16-1:
CCP AND TIMER INTERCONNECT CONFIGURATIONS
T3CCP<2:1> = 00
T3CCP<2:1> = 01
T3CCP<2:1> = 10
T3CCP<2:1> = 11
TMR1
TMR3
TMR1
TMR3
TMR1
TMR3
TMR1
TMR3
ECCP1
ECCP2
ECCP3
CCP4
ECCP1
ECCP1
ECCP2
ECCP1
ECCP2
ECCP3
CCP4
ECCP2
ECCP3
CCP4
ECCP3
CCP4
CCP5
CCP5
CCP5
CCP5
TMR2
TMR4
TMR2
TMR4
TMR2
TMR4
TMR2
TMR4
Timer1 is used for all Capture Timer1 and Timer2 are used Timer1 and Timer2 are used
for Capture and Compare or
all CCP modules. Timer2 is PWM operations for ECCP1 PWM operations for ECCP1
used for PWM operations for only (depending on selected and ECCP2 only (depending
Timer3 is used for all Capture
and Compare operations for
all CCP modules. Timer4 is
used for PWM operations for
all CCP modules. Modules
may share either timer
resource as a common time
base.
and Compare operations for for Capture and Compare or
on the mode selected for each
module). Both modules may
use a timer as a common time
base if they are both in
Capture/Compare or PWM
modes.
all CCP modules. Modules mode).
may share either timer
All other modules use either
resource as a common time
base.
Timer3 or Timer4. Modules
may share either timer
Timer3 and Timer4 are not resource as a common time
Timer1 and Timer2 are not
available.
available.
base
if
they
are
in
Capture/Compare or PWM The other modules use either
modes.
Timer3 or Timer4. Modules
may share either timer
resource as a common time
base
if
they
are
in
Capture/Compare or PWM
modes.
DS39612A-page 152
Advance Information
2003 Microchip Technology Inc.
PIC18F6X2X/8X2X
16.2.3
SOFTWARE INTERRUPT
16.2 Capture Mode
When the Capture mode is changed, a false capture
interrupt may be generated. The user should keep bit
CCP4IE (PIE3<1>) clear to avoid false interrupts and
should clear the flag bit, CCP4IF, following any such
change in operating mode.
In Capture mode, the CCPR4H:CCPR4L register pair
captures the 16-bit value of the TMR1 or TMR3 regis-
ters when an event occurs on pin RG3/CCP4. An event
is defined as one of the following:
• every falling edge
• every rising edge
16.2.4
CCP PRESCALER
• every 4th rising edge
• every 16th rising edge
There are four prescaler settings in Capture mode; they
are specified as part of the operating mode selected by
the mode select bits (CCP4M3:CCP4M0). Whenever
the CCP module is turned off or the CCP module is not
in Capture mode, the prescaler counter is cleared. This
means that any RESET will clear the prescaler counter.
The event is selected by the mode select bits,
CCP4M3:CCP4M0 (CCP4CON<3:0>). When a cap-
ture is made, the interrupt request flag bit CCP4IF
(PIR3<1>) is set; it must be cleared in software. If
another capture occurs before the value in register
CCPR4 is read, the old captured value is overwritten by
the new captured value.
Switching from one capture prescaler to another may
generate an interrupt. Also, the prescaler counter will
not be cleared, therefore, the first capture may be from
a non-zero prescaler. Example 16-1 shows the recom-
mended method for switching between capture pres-
calers. This example also clears the prescaler counter
and will not generate the “false” interrupt.
16.2.1
CCP PIN CONFIGURATION
In Capture mode, the RG3/CCP4 pin should be
configured as an input by setting the TRISG<3> bit.
Note:
If the RG3/CCP4 is configured as an out-
put, a write to the port can cause a capture
condition.
EXAMPLE 16-1:
CHANGING BETWEEN
CAPTURE PRESCALERS
CLRF
CCP4CON
; Turn CCP module off
MOVLW
NEW_CAPT_PS ; Load WREG with the
; new prescaler mode
16.2.2
TIMER1/TIMER3 MODE SELECTION
The timers that are to be used with the capture feature
(Timer1 and/or Timer3) must be running in Timer mode
or Synchronized Counter mode. In Asynchronous
Counter mode, the capture operation may not work.
The timer to be used with each CCP module is selected
in the T3CON register (see Section 16.1.1).
; value and CCP ON
; Load CCP1CON with
; this value
MOVWF
CCP4CON
FIGURE 16-2:
CAPTURE MODE OPERATION BLOCK DIAGRAM
TMR3H
TMR3L
CCPR4L
TMR1L
Set Flag bit CCP4IF
T3CCP2
TMR3
Enable
Prescaler
÷ 1, 4, 16
RG3/CCP4 pin
CCPR4H
TMR1
and
Edge Detect
Enable
T3CCP2
TMR1H
CCP1CON<3:0>
Q’s
2003 Microchip Technology Inc.
Advance Information
DS39612A-page 153
PIC18F6X2X/8X2X
16.3.2
TIMER1/TIMER3 MODE SELECTION
16.3 Compare Mode
Timer1 and/or Timer3 must be running in Timer mode
or Synchronized Counter mode, if the CCP module is
using the compare feature. In Asynchronous Counter
mode, the compare operation may not work.
In Compare mode, the 16-bit CCPR1 register value is
constantly compared against either the TMR1 or TMR3
register pair value. When a match occurs, the CCP4
pin can be:
• driven high
16.3.3
SOFTWARE INTERRUPT MODE
• driven low
When the Generate Software Interrupt mode is chosen
(CCP4M3:CCP4M0 = 1010), the CCP4 pin is not
affected. Only a CCP interrupt is generated if enabled
and the CCP4IE bit is set.
• toggled (high to low or low to high)
• remain unchanged (that is, reflects the state of the
I/O latch)
The action on the pin is based on the value of the mode
select bits (CCP4M3:CCP4M0). At the same time, the
interrupt flag bit CCP4IF is set.
16.3.4
SPECIAL EVENT TRIGGER
Although shown in Figure 16-3, the compare on match
special event triggers are not implemented on CCP4 or
CCP5; they are only available on ECCP1 and ECCP2.
Their operation is discussed in detail in Section 17.2.1.
16.3.1
CCP PIN CONFIGURATION
The user must configure the CCPx pin as an output by
clearing the appropriate TRIS bit.
Note:
Clearing the CCP4CON register will force
the RG3/CCP4 compare output latch to
the default low level. This is not the
PORTG I/O data latch.
FIGURE 16-3:
COMPARE MODE OPERATION BLOCK DIAGRAM
Special Event Trigger
(ECCP1 and ECCP2 only)
Set Flag bit CCP4IF
CCPR4H CCPR4L
Comparator
Q
S
R
Output
Logic
Match
RG3/CCP4 pin
TRISG<3>
Output Enable
1
CCP4CON<3:0>
Mode Select
0
T3CCP2
TMR1H TMR1L
TMR3H TMR3L
DS39612A-page 154
Advance Information
2003 Microchip Technology Inc.
PIC18F6X2X/8X2X
TABLE 16-2: REGISTERS ASSOCIATED WITH CAPTURE, COMPARE, TIMER1 AND TIMER3
Value on
Value on
POR, BOR
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
all other
RESETS
INTCON
RCON
PIR1
GIE/GIEH PEIE/GIEL TMR0IE
INT0IE
RI
RBIE
TO
TMR0IF
PD
INT0IF
POR
RBIF
BOR
0000 0000 0000 0000
0--1 11qq 0--q qquu
IPEN
PSPIF
PSPIE
PSPIP
—
—
ADIF
ADIE
ADIP
CMIE
CMIF
CMIP
—
—
RCIF
RCIE
RCIP
—
TXIF
TXIE
TXIP
EEIE
EEIF
EEIP
TX2IF
TX2IE
TX2IP
SSPIF
SSPIE
SSPIP
BCLIF
BCLIE
BCLIP
TMR4IF
CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
CCP1IP TMR2IP TMR1IP 1111 1111 1111 1111
PIE1
IPR1
PIR2
LVDIF
LVDIE
LVDIP
TMR3IF CCP2IF -0-0 0000 ---0 0000
TMR3IE CCP2IE -0-0 0000 ---0 0000
TMR3IP CCP2IP -1-1 1111 ---1 1111
PIE2
—
—
IPR2
—
—
PIR3
—
RC2IF
RC2IE
RC2IP
CCP5IF CCP4IF CCP3IF --00 0000 --00 0000
PIE3
—
—
TMR4IE CCP5IE CCP4IE CCP3IE --00 0000 --00 0000
TMR4IP CCP5IP CCP4IP CCP3IP --11 1111 --11 1111
1111 1111 1111 1111
IPR3
—
—
TRISC
TMR1L
TMR1H
T1CON
TMR3H
TMR3L
T3CON
PORTC Data Direction Register
Holding Register for the Least Significant Byte of the 16-bit TMR1 Register
Holding Register for the Most Significant Byte of the 16-bit TMR1 Register
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
RD16
—
T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 0-00 0000 u-uu uuuu
Timer3 Register High Byte
Timer3 Register Low Byte
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
RD16
T3CCP2 T3CKPS1 T3CKPS0 T3CCP1 T3SYNC TMR3CS TMR3ON 0000 0000 uuuu uuuu
(1)
CCPRxL
CCPRxH
Capture/Compare/PWM Register x (LSB)
Capture/Compare/PWM Register x (MSB)
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
(1)
(1)
CCPxCON
Legend:
—
—
DCxB1
DCxB0
CCPxM3 CCPxM2 CCPxM1 CCPxM0 --00 0000 --00 0000
x= unknown, u= unchanged, - = unimplemented, read as ‘0’.
Shaded cells are not used by Capture and Compare, Timer1 or Timer3.
Note 1: Generic term for all of the identical registers of this name for all CCP modules, where ‘x’ identifies the individual module
(CCP4 and CCP5). Bit assignments and RESET values for all registers of the same generic name are identical.
2003 Microchip Technology Inc.
Advance Information
DS39612A-page 155
PIC18F6X2X/8X2X
16.4.1
PWM PERIOD
16.4 PWM Mode
The PWM period is specified by writing to the PR2
(PR4) register. The PWM period can be calculated
using the following formula:
In Pulse Width Modulation (PWM) mode, the CCP4 pin
produces up to a 10-bit resolution PWM output. Since
the CCP4 pin is multiplexed with the PORTG data
latch, the TRISG<3> bit must be cleared to make the
CCP4 pin an output.
PWM period = (PR2) + 1] • 4 • TOSC •
(TMR2 prescale value)
PWM frequency is defined as 1 / [PWM period].
Note:
Clearing the CCP4CON register will force
the CCP4 PWM output latch to the default
low level. This is not the PORTG I/O data
latch.
When TMR2 (TMR4) is equal to PR2 (PR2), the
following three events occur on the next increment
cycle:
Figure 16-4 shows a simplified block diagram of the
CCP module in PWM mode.
• TMR2 (TMR4) is cleared
• The CCP4 pin is set (exception: if PWM duty
cycle = 0%, the CCP4 pin will not be set)
For a step-by-step procedure on how to set up the CCP
module for PWM operation, see Section 16.4.3.
• The PWM duty cycle is latched from CCPR4L into
CCPR4H
FIGURE 16-4:
SIMPLIFIED PWM BLOCK
DIAGRAM
Note:
The Timer2 and Timer4 postscalers (see
Section 13.0) are not used in the determi-
nation of the PWM frequency. The
postscaler could be used to have a servo
update rate at a different frequency than
the PWM output.
CCP1CON<5:4>
Duty Cycle Registers
CCPR4L
16.4.2
PWM DUTY CYCLE
CCPR4H (Slave)
Comparator
The PWM duty cycle is specified by writing to the
CCPR4L register and to the CCP4CON<5:4> bits. Up
to 10-bit resolution is available. The CCPR1L contains
the eight MSbs and the CCP4CON<5:4> contains the
two LSbs. This 10-bit value is represented by
CCPR4L:CCP4CON<5:4>. The following equation is
used to calculate the PWM duty cycle in time:
Q
R
RG3/CCP4
(Note 1)
TMR2
S
TRISG<3>
Comparator
PR2
PWM duty cycle = (CCPR4L:CCP4CON<5:4>) •
TOSC • (TMR2 prescale value)
Clear Timer,
CCP1 pin and
latch D.C.
CCPR4L and CCP4CON<5:4> can be written to at any
time, but the duty cycle value is not latched into
CCPR4H until after a match between PR2 and TMR2
occurs (i.e., the period is complete). In PWM mode,
CCPR4H is a read only register.
Note 1: 8-bit timer TMR2 or TMR4 is concatenated with 2-bit
internal Q clock or 2 bits of the prescaler to create
10-bit time base.
A PWM output (Figure 16-5) has a time base (period)
and a time that the output stays high (duty cycle). The
frequency of the PWM is the inverse of the period
(1/period).
The CCPR1H register and a 2-bit internal latch are
used to double-buffer the PWM duty cycle. This
double-buffering is essential for glitchless PWM
operation.
When the CCPR4H and 2-bit latch match TMR2, con-
catenated with an internal 2-bit Q clock or 2 bits of the
TMR2 prescaler, the CCP4 pin is cleared.
FIGURE 16-5:
PWM OUTPUT
Period
The maximum PWM resolution (bits) for a given PWM
frequency is given by the equation:
FOSC
Duty Cycle
---------------
log
FPWM
PWM Resolution (max)
= ----------------------------- b i t s
TMR2 = PR2
log(2)
TMR2 = Duty Cycle
Note:
If the PWM duty cycle value is longer than
the PWM period, the CCP4 pin will not be
cleared.
TMR2 = PR2
DS39612A-page 156
Advance Information
2003 Microchip Technology Inc.
PIC18F6X2X/8X2X
3. Set the PWM duty cycle by writing to the
CCPR4L register and CCP4CON<5:4> bits.
16.4.3
SETUP FOR PWM OPERATION
The following steps should be taken when configuring
the CCP module for PWM operation:
4. Make the CCP4 pin an output by clearing the
TRISG<3> bit.
1. Select TMR2 or TMR4 by setting or clearing the
T3CCP2:T3CCP1 bits in T3CON register.
5. Set TMR2 or TMR4 prescale value, enable
Timer2 or Timer4 by writing to T2CON or
T4CON.
2. Set the PWM period by writing to the PR2 or
PR4 register
6. Configure the CCP4 module for PWM operation.
TABLE 16-3: EXAMPLE PWM FREQUENCIES AND RESOLUTIONS AT 40 MHz
PWM Frequency
2.44 kHz
9.77 kHz
39.06 kHz 156.25 kHz 312.50 kHz 416.67 kHz
Timer Prescaler (1, 4, 16)
PR2 Value
16
FFh
14
4
1
1
3Fh
8
1
1Fh
7
1
FFh
12
FFh
10
17h
6.58
Maximum Resolution (bits)
TABLE 16-4: REGISTERS ASSOCIATED WITH PWM, TIMER2 AND TIMER4
Value on
all other
RESETS
Value on
POR, BOR
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
INTCON
RCON
PIR1
GIE/GIEH PEIE/GIEL TMR0IE
INT0IE
RI
RBIE
TO
TMR0IF
PD
INT0IF
POR
RBIF
BOR
0000 00000000 0000
0--1 11qq0--q qquu
IPEN
PSPIF
PSPIE
PSPIP
—
—
ADIF
ADIE
ADIP
CMIE
CMIF
CMIP
—
—
RCIF
RCIE
RCIP
—
TXIF
TXIE
TXIP
EEIE
EEIF
EEIP
TX2IF
TX2IE
TX2IP
SSPIF
SSPIE
SSPIP
BCLIF
BCLIE
BCLIP
TMR4IF
TMR4IE
TMR4IP
CCP1IF TMR2IF TMR1IF 0000 00000000 0000
CCP1IE TMR2IE TMR1IE 0000 00000000 0000
CCP1IP TMR2IP TMR1IP 1111 11111111 1111
PIE1
IPR1
PIR2
LVDIF
LVDIE
LVDIP
TMR3IF CCP2IF -0-0 0000---0 0000
TMR3IE CCP2IE -0-0 0000---0 0000
TMR3IP CCP2IP -1-1 1111---1 1111
PIE2
—
—
IPR2
—
—
PIR3
—
RC2IF
RC2IE
RC2IP
CCP5IF CCP4IF CCP3IF --00 0000--00 0000
CCP5IE CCP4IE CCP3IE --00 0000--00 0000
CCP5IP CCP4IP CCP3IP --11 1111--11 1111
0000 00000000 0000
PIE3
—
—
IPR3
—
—
TMR2
PR2
Timer2 Module Register
Timer2 Module Period Register
1111 11111111 1111
T2CON
T3CON
TMR4
PR4
—
T2OUTPS3 T2OUTPS2 T2OUTPS1 T2OUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000-000 0000
T3CCP2 T3CKPS1 T3CKPS0 T3CCP1 T3SYNC TMR3CS TMR3ON 0000 0000uuuu uuuu
RD16
Timer4 Register
0000 0000uuuu uuuu
1111 1111uuuu uuuu
Timer4 Period Register
T4CON
—
T4OUTPS3 T4OUTPS2 T4OUTPS1 T4OUTPS0 TMR4ON T4CKPS1 T4CKPS0 -000 0000uuuu uuuu
(1)
CCPRxL
CCPRxH
Capture/Compare/PWM Register x (LSB)
Capture/Compare/PWM Register x (MSB)
xxxx xxxxuuuu uuuu
xxxx xxxxuuuu uuuu
(1)
(1)
CCPxCON
Legend:
—
—
DCxB1
DCxB0
CCPxM3 CCPxM2 CCPxM1 CCPxM0 --00 0000--00 0000
x= unknown, u= unchanged, - = unimplemented, read as ‘0’. Shaded cells are not used by PWM,Timer2 or Timer4.
Note 1: Generic term for all of the identical registers of this name for all CCP modules, where ‘x’ identifies the individual module
(CCP4 and CCP5). Bit assignments and RESET values for all registers of the same generic name are identical.
2003 Microchip Technology Inc.
Advance Information
DS39612A-page 157
PIC18F6X2X/8X2X
NOTES:
DS39612A-page 158
Advance Information
2003 Microchip Technology Inc.
PIC18F6X2X/8X2X
Compare functions of the ECCP module are the same
as the standard CCP module.
17.0 ENHANCED
CAPTURE/COMPARE/PWM
The prototype control register for the enhanced CCP
module is shown in Register 17-1. In addition to the
expanded range of modes available through the
CCPxCON register, the ECCP modules each have two
additional registers associated with enhanced PWM
operation and auto shutdown features. They are:
(ECCP) MODULE
The enhanced CCP (ECCP) modules differ from the
standard CCP modules by the addition of enhanced
PWM capabilities. These allow for 2 or 4 output
channels, user selectable polarity, dead band control,
and automatic shutdown and restart, and are
discussed in detail in Section 17.4. Except for the
addition of the special event trigger, Capture and
• ECCPxDEL (Dead band delay)
• ECCPxAS (Auto shutdown configuration)
REGISTER 17-1: CCPxCON REGISTER (ECCP1, ECCP2 AND ECCP3 MODULES)
R/W-0
PxM1
R/W-0
PxM0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
DCxB1
DCxB0
CCPxM3 CCPxM2 CCPxM1 CCPxM0
bit 0
bit 7
bit 7-6
PxM1:PxM0: Enhanced PWM Output Configuration bits
If CCPxM3:CCPxM2 = 00, 01, 10:
xx= PxA assigned as Capture/Compare input/output; PxB, PxC, PxD assigned as port pins
If CCPxM3:CCPxM2 = 11:
00= Single output: PxA modulated, PxB, PxC, PxD assigned as port pins
01= Full-bridge output forward: P1D modulated; P1A active; P1B, P1C inactive
10= Half-bridge output: P1A, P1B modulated with dead band control; P1C, P1D assigned
as port pins
11= Full-bridge output reverse: P1B modulated; P1C active; P1A, P1D inactive
bit 5-4
DCxB1:DCxB0: PWM Duty Cycle bit 1 and bit 0
Capture mode:
Unused.
Compare mode:
Unused.
PWM mode:
These bits are the two LSbs of the 10-bit PWM duty cycle. The eight MSbs of the duty cycle are
found in CCPRxL.
bit 3-0
CCPxM3:CCPxM0: Enhanced CCP Mode Select bits
0000=Capture/Compare/PWM off (resets CCPx module)
0001=Reserved
0010=Compare mode, toggle output on match
0011=Capture mode
0100=Capture mode, every falling edge
0101=Capture mode, every rising edge
0110=Capture mode, every 4th rising edge
0111=Capture mode, every 16th rising edge
1000=Compare mode, initialize CCP pin low, set output on compare match (set CCPxIF)
1001=Compare mode, initialize CCP pin high, clear output on compare match (set CCPxIF)
1010=Compare mode, generate software interrupt only, CCP pin reverts to I/O state
1011=Compare mode, trigger special event (ECCP resets TMR1 or TMR3, sets CCxIF bit,
ECCP2 trigger starts A/D conversion if A/D module is enabled)(1)
1100=PWM mode; PxA, PxC active high; PxB, PxD active high
1101=PWM mode; PxA, PxC active high; PxB, PxD active low
1110=PWM mode; PxA, PxC active low; PxB, PxD active high
1111=PWM mode; PxA, PxC active low; PxB, PxD active low
Note 1: Implemented only for ECCP1 and ECCP2; same as ‘1010’ for ECCP3.
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
- n = Value at POR
2003 Microchip Technology Inc.
Advance Information
DS39612A-page 159
PIC18F6X2X/8X2X
ECCP1 and ECCP3, on the other hand, only have
three dedicated output pins: CCPx/P3A, PxB, and PxC.
Whenever these modules are configured for Quad
PWM mode, the pin normally used for CCP4 or CCP5
becomes the D output pins for ECCP3 and ECCP1,
respectively. The CCP4 and CCP5 modules remain
functional but their outputs are overridden.
17.1 ECCP Outputs and Configuration
Each of the enhanced CCP modules may have up to
four PWM outputs, depending on the selected
operating mode. These outputs, designated PxA
through PxD, are multiplexed with various I/O pins.
Some ECCP pin assignments are constant, while
others change based on device configuration. For
those pins that do change, the controlling bits are:
17.1.2
ECCP MODULE OUTPUTS AND
PROGRAM MEMORY MODES
• CCP2MX configuration bit (CONFIG3H<0>)
• ECCPMX configuration bit (CONFIG3H<1>)
For PIC18F8X2X devices, the Program Memory mode
of the device (Section 4.1.1) impacts both pin
multiplexing and the operation of the module.
• Program Memory mode (set by configuration bits
CONFIG3L<1:0>)
The ECCP2 input/output (CCP2/P2A) can be multi-
plexed to one of three pins. By default, this is RC1 for
all devices; in this case, the default is when CCP2MX
is set and the device is operating in Microcontroller
mode. With PIC18F8X2X devices, three other options
exist. When CCP2MX is not set (= 0) and the device is
in Microcontroller mode, CCP2/P2A is multiplexed to
RE7; in all other Program Memory modes, it is
multiplexed to RB3.
The pin assignments for the enhanced CCP modules
are summarized in Table 17-1, Table 17-2 and
Table 17-3. To configure the I/O pins as PWM outputs,
the proper PWM mode must be selected by setting the
PxMx and CCPxMx bits (CCPxCON<7:6> and <3:0>,
respectively). The appropriate TRIS direction bits for
the corresponding port pins must also be set as
outputs.
17.1.1
USE OF CCP4 AND CCP5 WITH
ECCP1 AND ECCP3
The final option is for CCP2MX to be set while the
device is operating in one of the three other Program
Memory modes. In this case, ECCP1 and ECCP3 oper-
ate as compatible (i.e., single output) CCP modules.
The pins used by their other outputs (PxB through PxD)
are available for other multiplexed functions. ECCP2
continues to operate as an enhanced CCP module
regardless of the Program Memory mode.
Only ECCP2 module has four dedicated output pins
available for use. Assuming that the I/O ports or other
multiplexed functions on those pins are not needed,
they may be used whenever needed without interfering
with any other CCP module.
TABLE 17-1: PIN CONFIGURATIONS FOR ECCP1
CCP1CON
ECCP Mode
RC2
RE6
RE5
RG4
RH7
RH6
Configuration
All PIC18F6X2X devices:
Compatible CCP
Dual PWM
00xx11xx
10xx11xx
x1xx11xx
CCP1
P1A
RE6
P1B
P1B
RE5
RE5
P1C
RG4/CCP5
RG4/CCP5
P1D
n/a
n/a
n/a
n/a
n/a
n/a
Quad PWM
P1A
PIC18F8X2X devices, ECCPMX = 1, Microcontroller mode:
Compatible CCP
Dual PWM
00xx11xx
10xx11xx
x1xx11xx
CCP1
P1A
RE6/AD14 RE5/AD13 RG4/CCP5 RH7/AN15 RH6/AN14
P1B
P1B
RE5/AD13 RG4/CCP5 RH7/AN15 RH6/AN14
P1C P1D RH7/AN15 RH6/AN14
Quad PWM
P1A
PIC18F8X2X devices, ECCPMX = 0, Microcontroller mode:
Compatible CCP
Dual PWM
00xx11xx
10xx11xx
x1xx11xx
CCP1
P1A
RE6/AD14 RE5/AD13 RG4/CCP5 RH7/AN15 RH6/AN14
RE6/AD14 RE5/AD13 RG4/CCP5
RE6/AD14 RE5/AD13 P1D
P1B
P1B
RH6/AN14
P1C
Quad PWM
P1A
PIC18F8X2X devices, ECCPMX = 1, all other Program Memory modes:
00xx11xx CCP1 RE6/AD14 RE5/AD13 RG4/CCP5 RH7/AN15 RH6/AN14
Compatible CCP
Legend: x= Don’t care, n/a = Not available. Shaded cells indicate pin assignments not used by ECCP1 in a given mode.
Note 1: With ECCP1 in Quad PWM mode, CCP5’s output is overridden by P1D; otherwise CCP5 is fully operational.
DS39612A-page 160
Advance Information
2003 Microchip Technology Inc.
PIC18F6X2X/8X2X
TABLE 17-2: PIN CONFIGURATIONS FOR ECCP2
CCP2CON
ECCP Mode
RB3
RC1
RE7
RE2
RE1
RE0
Configuration
All devices, CCP2MX = 1, Microcontroller mode:
Compatible CCP
Dual PWM
00xx11xx
10xx11xx
x1xx11xx
RB3/INT3
RB3/INT3
RB3/INT3
CCP2
P2A
RE7
RE7
RE7
RE2
P2B
P2B
RE1
RE1
P2C
RE0
RE0
P2D
Quad PWM
P2A
All devices, CCP2MX = 0, Microcontroller mode:
Compatible CCP
Dual PWM
00xx11xx
10xx11xx
x1xx11xx
RB3/INT3 RC1/T1OS1
RB3/INT3 RC1/T1OS1
RB3/INT3 RC1/T1OS1
CCP2
P2A
RE2
P2B
P2B
RE1
RE1
P2C
RE0
RE0
P2D
Quad PWM
P2A
PIC18F8X2X devices, CCP2MX = 0, all other Program Memory modes:
Compatible CCP
Dual PWM
00xx11xx
10xx11xx
x1xx11xx
CCP2
P2A
RC1/T1OS1 RE7/AD15
RC1/T1OS1 RE7/AD15
RC1/T1OS1 RE7/AD15
RE2/CS
P2B
RE1/WR
RE1/WR
P2C
RE0/RD
RE0/RD
P2D
Quad PWM
P2A
P2B
Legend: x= Don’t care. Shaded cells indicate pin assignments not used by ECCP2 in a given mode.
TABLE 17-3: PIN CONFIGURATIONS FOR ECCP3
CCP3CON
ECCP Mode
RG0
RE4
RE3
RG3
RH5
RH4
Configuration
All PIC18F6X2X devices:
Compatible CCP 00xx11xx
CCP3
P3A
RE4
P3B
P3B
RE3
RE3
P3C
RG3/CCP4
RG3/CCP4
P3D
n/a
n/a
n/a
n/a
n/a
n/a
Dual PWM
Quad PWM
10xx11xx
x1xx11xx
P3A
PIC18F8X2X devices, ECCPMX = 1, Microcontroller mode:
Compatible CCP 00xx11xx
CCP3
P3A
RE4/AD12 RE3/AD11 RG3/CCP4 RH5/AN13 RH4/AN12
Dual PWM
Quad PWM
10xx11xx
x1xx11xx
P3B
P3B
RE3/AD11 RG3/CCP4 RH5/AN13 RH4/AN12
P3A
P3C
P3D
RH5/AN13 RH4/AN12
PIC18F8X2X devices, ECCPMX = 0, Microcontroller mode:
Compatible CCP 00xx11xx
CCP3
P3A
RE6/AD14 RE5/AD13 RG3/CCP4 RH7/AN15 RH6/AN14
Dual PWM
Quad PWM
10xx11xx
x1xx11xx
RE6/AD14 RE5/AD13 RG3/CCP4
RE6/AD14 RE5/AD13 P3D
P3B
P3B
RH6/AN14
P3C
P3A
PIC18F8X2X devices, ECCPMX = 1, all other Program Memory modes:
Compatible CCP 00xx11xx
CCP3
RE6/AD14 RE5/AD13 RG3/CCP4 RH7/AN15 RH6/AN14
Legend: x= Don’t care, n/a = Not available. Shaded cells indicate pin assignments not used by ECCP3 in a given mode.
Note 1: With ECCP3 in Quad PWM mode, CCP4’s output is overridden by P1D; otherwise CCP4 is fully operational.
2003 Microchip Technology Inc.
Advance Information
DS39612A-page 161
PIC18F6X2X/8X2X
17.1.3
ECCP MODULES AND TIMER
RESOURCES
17.4 Enhanced PWM Mode
The Enhanced PWM mode provides additional PWM
output options for a broader range of control applica-
tions. The module is a backward compatible version of
the standard CCP module and offers up to four outputs,
designated PxA through PxD. Users are also able to
select the polarity of the signal (either active high or
active low). The module’s output mode and polarity
are configured by setting the PxM1:PxM0 and
CCPxM3CCPxM0 bits of the CCPxCON register
(CCPxCON<7:6> and CCPxCON<3:0>, respectively).
Like the standard CCP modules, the ECCP modules
can utilize Timers 1, 2, 3 or 4, depending on the mode
selected. Timer1 and Timer3 are available for modules
in Capture or Compare modes, while Timer2 and
Timer4 are available for modules in PWM mode. Addi-
tional details on timer resources are provided in
Section 16.1.1.
17.2 Capture and Compare Modes
For the sake of clarity, Enhanced PWM mode operation
is described generically throughout this section with
respect to ECCP1 and TMR2 modules. Control register
names are presented in terms of ECCP1. All three
enhanced modules, as well as the two timer resources,
can be used interchangeably and function identically.
TMR2 or TMR4 can be selected for PWM operation by
selecting the proper bits in T3CON.
Except for the operation of the special event trigger dis-
cussed below, the Capture and Compare modes of the
ECCP module are identical in operation to that of
CCP4. These are discussed in detail in Section 16.2
and Section 16.3.
17.2.1
SPECIAL EVENT TRIGGER
In this mode, an internal hardware trigger is generated
in Compare mode, on a match between the CCPR reg-
ister pair and the selected timer. This can be used in
turn to initiate an action.
Figure 17-1 shows a simplified block diagram of PWM
operation. All control registers are double-buffered and
are loaded at the beginning of a new PWM cycle (the
period boundary when Timer2 resets) in order to pre-
vent glitches on any of the outputs. The exception is the
PWM delay register, ECCP1DEL, which is loaded at
either the duty cycle boundary or the boundary period
(whichever comes first). Because of the buffering, the
module waits until the assigned timer resets instead of
starting immediately. This means that enhanced PWM
waveforms do not exactly match the standard PWM
waveforms but are instead offset by one full instruction
cycle (4 TOSC).
The special event trigger output of either ECCP1 or
ECCP2 resets the TMR1 or TMR3 register pair,
depending on which timer resource is currently
selected. This allows the CCPRx register to effectively
be a 16-bit programmable period register for Timer1 or
Timer3. In addition, the ECCP2 special event trigger
will also start an A/D conversion if the A/D module is
enabled.
The triggers are not implemented for ECCP3, CCP4 or
CCP5. Selecting the Special Event mode
(CCPxM3:CCPxM0 = 1011) for these modules has the
same effect as selecting the Compare with Software
Interrupt mode (CCPxM3:CCPxM0 = 1010).
As before, the user must manually configure the
appropriate TRIS bits for output.
17.4.1
PWM PERIOD
Note:
The special event trigger from ECCP2 will
not set the Timer1 or Timer3 interrupt flag
bits.
The PWM period is specified by writing to the PR2
register. The PWM period can be calculated using the
equation:
PWM Period = [(PR2) + 1] • 4 • TOSC •
(TMR2 Prescale Value)
17.3 Standard PWM Mode
When configured in Single Output mode, the ECCP
module functions identically to the standard CCP
module in PWM mode as described in Section 16.4.
This is also sometimes referred to as “Compatible
CCP” mode as in Tables 17-1 through 17-3.
PWM frequency is defined as 1 / [PWM period]. When
TMR2 is equal to PR2, the following three events occur
on the next increment cycle:
• TMR2 is cleared
• The CCP1 pin is set (if PWM duty cycle = 0%, the
CCP1 pin will not be set)
Note:
When setting up single output PWM opera-
tions, users are free to use either of the
processes described in Section 16.4.3 or
Section 17.4.9. The latter is more generic
but will work for either single or multi-output
PWM.
• The PWM duty cycle is copied from CCPR1L into
CCPR1H
Note:
The Timer2 postscaler (see Section 13.0)
is not used in the determination of the
PWM frequency. The postscaler could be
used to have a servo update rate at a
different frequency than the PWM output.
DS39612A-page 162
Advance Information
2003 Microchip Technology Inc.
PIC18F6X2X/8X2X
FIGURE 17-1:
SIMPLIFIED BLOCK DIAGRAM OF THE ENHANCED PWM MODULE
CCP1CON<5:4>
P1M1<1:0>
CCP1M<3:0>
4
Duty Cycle Registers
2
CCPR1L
CCP1/P1A
CCP1/P1A
P1B
TRISx<x>
TRISx<x>
TRISx<x>
TRISx<x>
CCPR1H (Slave)
Comparator
P1B
Output
Controller
R
Q
P1C
P1C
P1D
(Note 1)
TMR2
S
P1D
Comparator
PR2
Clear Timer,
set CCP1 pin and
latch D.C.
ECCP1DEL
Note: The 8-bit timer TMR2 register is concatenated with the 2-bit internal Q clock, or 2 bits of the prescaler, to create the 10-bit
time base.
The CCPRxH register and a 2-bit internal latch are
used to double-buffer the PWM duty cycle. This
double-buffering is essential for glitchless PWM opera-
tion. When the CCPR1H and 2-bit latch match TMR2,
concatenated with an internal 2-bit Q clock or two bits
of the TMR2 prescaler, the CCP1 pin is cleared. The
maximum PWM resolution (bits) for a given PWM
frequency is given by the equation:
17.4.2
PWM DUTY CYCLE
The PWM duty cycle is specified by writing to the
CCPR1L register and to the CCP1CON<5:4> bits. Up
to 10-bit resolution is available. The CCPR1L contains
the eight MSbs and the CCP1CON<5:4> contains the
two LSbs. This 10-bit value is represented by
CCPRxL:CCPxCON<5:4>. The PWM duty cycle is
calculated by the equation:
FOSC
log
PWM Duty Cycle = (CCPR1L:CCP1CON<5:4>) •
TOSC • (TMR2 Prescale Value)
(
)
FPWM
bits
PWM Resolution (max) =
log(2)
CCPR1L and CCP1CON<5:4> can be written to at any
time but the duty cycle value is not copied into
CCPR1H until a match between PR2 and TMR2 occurs
(i.e., the period is complete). In PWM mode, CCPR1H
is a read only register.
Note:
If the PWM duty cycle value is longer than
the PWM period, the CCP1 pin will not be
cleared.
TABLE 17-4: EXAMPLE PWM FREQUENCIES AND RESOLUTIONS AT 40 MHz
PWM Frequency
2.44 kHz
9.77 kHz
39.06 kHz 156.25 kHz 312.50 kHz 416.67 kHz
Timer Prescaler (1, 4, 16)
PR2 Value
16
FFh
10
4
1
1
3Fh
8
1
1Fh
7
1
FFh
10
FFh
10
17h
6.58
Maximum Resolution (bits)
2003 Microchip Technology Inc.
Advance Information
DS39612A-page 163
PIC18F6X2X/8X2X
The Single Output mode is the standard PWM mode
discussed in Section 17.4. The Half-Bridge and
Full-Bridge Output modes are covered in detail in the
sections that follow.
17.4.3
PWM OUTPUT CONFIGURATIONS
The P1M1:P1M0 bits in the CCP1CON register allow
one of four configurations:
• Single Output
The general relationship of the outputs in all
configurations is summarized in Figure 17-2.
• Half-Bridge Output
• Full-Bridge Output, Forward mode
• Full-Bridge Output, Reverse mode
FIGURE 17-2:
PWM OUTPUT RELATIONSHIPS (ACTIVE HIGH STATE)
0
PR2+1
Duty
Cycle
SIGNAL
CCP1CON
<7:6>
Period
P1A Modulated
P1A Modulated
P1B Modulated
P1A Active
(Single Output)
00
10
(1)
(1)
Delay
Delay
(Half-Bridge)
P1B Inactive
P1C Inactive
P1D Modulated
P1A Inactive
P1B Modulated
P1C Active
(Full-Bridge,
Forward)
01
(Full-Bridge,
Reverse)
11
P1D Inactive
DS39612A-page 164
Advance Information
2003 Microchip Technology Inc.
PIC18F6X2X/8X2X
FIGURE 17-3:
PWM OUTPUT RELATIONSHIPS (ACTIVE LOW STATE)
0
PR2+1
Duty
Cycle
SIGNAL
CCP1CON
<7:6>
Period
P1A Modulated
P1A Modulated
P1B Modulated
P1A Active
(Single Output)
00
10
(1)
(1)
Delay
Delay
(Half-Bridge)
P1B Inactive
P1C Inactive
P1D Modulated
P1A Inactive
P1B Modulated
P1C Active
(Full-Bridge,
Forward)
01
(Full-Bridge,
Reverse)
11
P1D Inactive
Relationships:
•
•
•
Period = 4 * TOSC * (PR2 + 1) * (TMR2 prescale value)
Duty Cycle = TOSC * (CCPR1L<7:0>:CCP1CON<5:4>) * (TMR2 prescale value)
Delay = 4 * TOSC * (ECCP1DEL<6:0>)
Note 1: Dead band delay is programmed using the ECCP1DEL register (Section 17.4.6).
17.4.4
HALF-BRIDGE MODE
FIGURE 17-4:
HALF-BRIDGE PWM
OUTPUT
In the Half-Bridge Output mode, two pins are used as
outputs to drive push-pull loads. The PWM output sig-
nal is output on the P1A pin, while the complementary
PWM output signal is output on the P1B pin
(Figure 17-4). This mode can be used for half-bridge
applications, as shown in Figure 17-5, or for full-bridge
applications, where four power switches are being
modulated with two PWM signals.
Period
Period
Duty Cycle
(2)
(2)
P1A
td
td
P1B
In Half-Bridge Output mode, the programmable dead
band delay can be used to prevent shoot-through
current in half-bridge power devices. The value of bits
PDC6:PDC0 sets the number of instruction cycles
before the output is driven active. If the value is greater
than the duty cycle, the corresponding output remains
inactive during the entire cycle. See Section 17.4.6 for
more details of the dead band delay operations.
(1)
(1)
(1)
td = Dead Band Delay
Note 1: At this time, the TMR2 register is equal to the
PR2 register.
2: Output signals are shown as active high.
Since the P1A and P1B outputs are multiplexed with
the PORTC<2> and PORTE<6> data latches, the
TRISC<2> and TRISE<6> bits must be cleared to
configure P1A and P1B as outputs.
2003 Microchip Technology Inc.
Advance Information
DS39612A-page 165
PIC18F6X2X/8X2X
FIGURE 17-5:
EXAMPLES OF HALF-BRIDGE OUTPUT MODE APPLICATIONS
V+
Standard Half-Bridge Circuit (“Push-Pull”)
PIC18F6X2X/8X2X
FET
Driver
+
V
-
P1A
Load
FET
Driver
+
V
-
P1B
V-
Half-Bridge Output Driving a Full-Bridge Circuit
V+
PIC18F6X2X/8X2X
FET
Driver
FET
Driver
P1A
Load
FET
Driver
FET
Driver
P1B
V-
DS39612A-page 166
Advance Information
2003 Microchip Technology Inc.
PIC18F6X2X/8X2X
P1A, P1B, P1C and P1D outputs are multiplexed with
the PORTC<2>, PORTE<6:5>, and PORTG<4> data
latches. The TRISC<2>, TRISC<6:5>, and TRISG<4>
bits must be cleared to make the P1A, P1B, P1C, and
P1D pins outputs.
17.4.5
FULL-BRIDGE MODE
In Full-Bridge Output mode, four pins are used as
outputs; however, only two outputs are active at a time.
In the Forward mode, pin P1A is continuously active
and pin P1D is modulated. In the Reverse mode, pin
P1C is continuously active and pin P1B is modulated.
These are illustrated in Figure 17-6.
FIGURE 17-6:
FULL-BRIDGE PWM OUTPUT
Forward Mode
Period
(2)
P1A
Duty Cycle
(2)
(2)
P1B
P1C
(2)
P1D
(1)
(1)
Reverse Mode
Period
Duty Cycle
(2)
P1A
(2)
P1B
(2)
P1C
(2)
P1D
(1)
(1)
Note 1: At this time, the TMR2 register is equal to the PR2 register.
Note 2: Output signal is shown as active high.
2003 Microchip Technology Inc.
Advance Information
DS39612A-page 167
PIC18F6X2X/8X2X
FIGURE 17-7:
EXAMPLE OF FULL-BRIDGE APPLICATION
V+
PIC18F6X2X/8X2X
QC
QA
FET
Driver
FET
Driver
P1A
Load
P1B
FET
Driver
FET
Driver
P1C
P1D
QD
QB
V-
Figure 17-9 shows an example where the PWM direc-
tion changes from forward to reverse at a near 100%
duty cycle. At time t1, the output P1A and P1D become
inactive, while output P1C becomes active. In this
example, since the turn off time of the power devices is
longer than the turn on time, a shoot-through current
may flow through power devices QC and QD (see
Figure 17-7) for the duration of ‘t’. The same phenom-
enon will occur to power devices QA and QB for PWM
direction change from reverse to forward.
17.4.5.1
Direction Change in Full-Bridge Mode
In the Full-Bridge Output mode, the P1M1 bit in the
CCP1CON register allows user to control the
forward/reverse direction. When the application firm-
ware changes this direction control bit, the module will
assume the new direction on the next PWM cycle.
Just before the end of the current PWM period, the
modulated outputs (P1B and P1D) are placed in their
inactive state, while the unmodulated outputs (P1A and
P1C) are switched to drive in the opposite direction.
This occurs in a time interval of (4 TOSC * (Timer2
Prescale value) before the next PWM period begins.
The Timer2 prescaler will be either 1, 4 or 16, depend-
ing on the value of the T2CKPS bit (T2CON<1:0>).
During the interval from the switch of the unmodulated
outputs to the beginning of the next period, the
modulated outputs (P1B and P1D) remain inactive.
This relationship is shown in Figure 17-8.
If changing PWM direction at high duty cycle is required
for an application, one of the following requirements
must be met:
1. Reduce PWM for
changing directions.
a PWM period before
2. Use switch drivers that can drive the switches off
faster than they can drive them on.
Other options to prevent shoot-through current may
exist.
Note that in the Full-Bridge Output mode, the CCP1
module does not provide any dead band delay. In gen-
eral, since only one output is modulated at all times,
dead band delay is not required. However, there is a
situation where a dead band delay might be required.
This situation occurs when both of the following
conditions are true:
1. The direction of the PWM output changes when
the duty cycle of the output is at or near 100%.
2. The turn off time of the power switch, including
the power device and driver circuit, is greater
than the turn on time.
DS39612A-page 168
Advance Information
2003 Microchip Technology Inc.
PIC18F6X2X/8X2X
FIGURE 17-8:
PWM DIRECTION CHANGE
(1)
Period
Period
SIGNAL
P1A (Active High)
P1B (Active High)
DC
P1C (Active High)
P1D (Active High)
(Note 2)
DC
Note 1: The direction bit in the CCP1 Control register (CCP1CON<7>) is written any time during the PWM cycle.
2: When changing directions, the P1A and P1C signals switch before the end of the current PWM cycle at intervals
of 4 TOSC, 16 TOSC or 64 TOSC, depending on the Timer2 prescaler value. The modulated P1B and P1D signals
are inactive at this time.
FIGURE 17-9:
PWM DIRECTION CHANGE AT NEAR 100% DUTY CYCLE
Forward Period
Reverse Period
t1
P1A
P1B
DC
P1C
P1D
DC
t
ON
External Switch C
External Switch D
t
OFF
Potential
Shoot-Through
Current
t = t
– t
ON
OFF
Note 1: All signals are shown as active high.
2: t is the turn on delay of power switch QC and its driver.
ON
3: t
is the turn off delay of power switch QD and its driver.
OFF
2003 Microchip Technology Inc.
Advance Information
DS39612A-page 169
PIC18F6X2X/8X2X
A shutdown event can be caused by either of the two
comparator modules or the INT0 pin (or any combination
of these three sources). The comparators may be used
to monitor a voltage input proportional to a current being
monitored in the bridge circuit. If the voltage exceeds a
threshold, the comparator switches state and triggers a
shutdown. Alternatively, a digital signal on the INT0 pin
can also trigger a shutdown. The auto shutdown feature
can be disabled by not selecting any auto shutdown
sources. The auto shutdown sources to be used are
selected using the ECCP1AS2:ECCP1AS0 bits
(bits<6:4> of the ECCP1AS register).
17.4.6
PROGRAMMABLE DEAD BAND
DELAY
In half-bridge applications where all power switches are
modulated at the PWM frequency at all times, the
power switches normally require more time to turn off
than to turn on. If both the upper and lower power
switches are switched at the same time (one turned on,
and the other turned off), both switches may be on for
a short period of time until one switch completely turns
off. During this brief interval, a very high current
(shoot-through current) may flow through both power
switches, shorting the bridge supply. To avoid this
potentially destructive shoot-through current from flow-
ing during switching, turning on either of the power
switches is normally delayed to allow the other switch
to completely turn off.
When a shutdown occurs, the output pins are
asynchronously placed in their shutdown states,
specified
by
the
PSS1AC1:PSS1AC0
and
PSS1BD1:PSS1BD0 bits (ECCP1AS3:ECCP1AS0).
Each pin pair (P1A/P1C and P1B/P1D) may be set to
drive high, drive low, or be tri-stated (not driving). The
ECCP1ASE bit (ECCP1AS<7>) is also set to hold the
enhanced PWM outputs in their shutdown states.
In the Half-Bridge Output mode, a digitally program-
mable dead band delay is available to avoid
shoot-through current from destroying the bridge
power switches. The delay occurs at the signal transi-
tion from the non-active state to the active state. See
Figure 17-4 for illustration. The lower seven bits of the
ECCPxDEL register (Register 17-2) set the delay
period in terms of microcontroller instruction cycles
(TCY or 4 TOSC).
The ECCP1ASE bit is set by hardware when a shut-
down event occurs. If automatic restarts are not
enabled, the ECCPASE bit is cleared by firmware when
the cause of the shutdown clears. If automatic restarts
are enabled, the ECCPASE bit is automatically cleared
when the cause of the auto shutdown has cleared.
17.4.7
ENHANCED PWM
AUTO SHUTDOWN
If the ECCPASE bit is set when a PWM period begins,
the PWM outputs remain in their shutdown state for that
entire PWM period. When the ECCPASE bit is cleared,
the PWM outputs will return to normal operation at the
beginning of the next PWM period.
When the CCP1 is programmed for any of the
enhanced PWM modes, the active output pins may be
configured for auto shutdown. Auto shutdown immedi-
ately places the enhanced PWM output pins into a
defined shutdown state when a shutdown event
occurs.
Note:
Writing to the ECCPASE bit is disabled
while a shutdown condition is active.
REGISTER 17-2: ECCPxDEL: PWM CONFIGURATION REGISTER
R/W-0
PxRSEN
bit 7
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
PxDC6
PxDC5
PxDC4
PxDC3
PxDC2
PxDC1
PxDC0
bit 0
bit 7
PxRSEN: PWM Restart Enable bit
1= Upon auto shutdown, the ECCPxASE bit clears automatically once the shutdown event
goes away; the PWM restarts automatically
0= Upon auto shutdown, ECCPxASE must be cleared in software to restart the PWM
bit 6-0
PxDC6:PxDC0: PWM Delay Count bits
Delay time, in number of FOSC/4 (4*TOSC) cycles, between the scheduled and actual time for a
PWM signal to transition to active.
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
- n = Value at POR
DS39612A-page 170
Advance Information
2003 Microchip Technology Inc.
PIC18F6X2X/8X2X
REGISTER 17-3: ECCPxAS: ENHANCED CAPTURE/COMPARE/PWM AUTO SHUTDOWN
CONTROL REGISTER
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
ECCPxASE ECCPxAS2 ECCPxAS1 ECCPxAS0 PSSxAC1 PSSxAC0 PSSxBD1 PSSxBD0
bit 7
bit 0
bit 7
ECCPxASE: ECCP Auto Shutdown Event Status bit
0= ECCP outputs are operating
1= A shutdown event has occurred; ECCP outputs are in shutdown state
bit 6-4
ECCPxAS2:ECCPxAS0: ECCP Auto Shutdown Source Select bits
000= Auto shutdown is disabled
001= Comparator 1 output
010= Comparator 2 output
011= Either Comparator 1 or 2
100= INT0
101= INT0 or Comparator 1
110= INT0 or Comparator 2
111= INT0 or Comparator 1 or Comparator 2
bit 3-2
bit 1-0
PSSxAC1:PSSxAC0: Pin A and C Shutdown State Control bits
00= Drive Pins A and C to ‘0’
01= Drive Pins A and C to ‘1’
1x= Pins A and C tri-state
PSSxBD1:PSSxBD0: Pin B and D Shutdown State Control bits
00= Drive Pins B and D to ‘0’
01= Drive Pins B and D to ‘1’
1x= Pins B and D tri-state
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
- n = Value at POR
2003 Microchip Technology Inc.
Advance Information
DS39612A-page 171
PIC18F6X2X/8X2X
17.4.7.1
Auto Shutdown and Automatic
Restart
17.4.8
START-UP CONSIDERATIONS
When the ECCP module is used in the PWM mode, the
application hardware must use the proper external
pull-up and/or pull-down resistors on the PWM output
pins. When the microcontroller is released from
RESET, all of the I/O pins are in the high-impedance
state. The external circuits must keep the power switch
devices in the off state until the microcontroller drives
the I/O pins with the proper signal levels, or activates
the PWM output(s).
The auto shutdown feature can be configured to allow
automatic restarts of the module following a shutdown
event. This is enabled by setting the P1RSEN bit of the
ECCP1DEL register (ECCP1DEL<7>).
In Shutdown mode with PRSEN = 1(Figure 17-10), the
ECCPASE bit will remain set for as long as the cause
of the shutdown continues. When the shutdown condi-
tion clears, the ECCP1ASE bit is cleared. If PRSEN = 0
(Figure 17-11), once a shutdown condition occurs, the
ECCP1ASE bit will remain set until it is cleared by firm-
ware. Once ECCP1ASE is cleared, the enhanced
PWM will resume at the beginning of the next PWM
period.
The CCP1M1:CCP1M0 bits (CCP1CON<1:0>) allow
the user to choose whether the PWM output signals are
active high or active low for each pair of PWM output
pins (P1A/P1C and P1B/P1D). The PWM output polar-
ities must be selected before the PWM pins are config-
ured as outputs. Changing the polarity configuration
while the PWM pins are configured as outputs is not
recommended since it may result in damage to the
application circuits.
Note:
Writing to the ECCPASE bit is disabled
while a shutdown condition is active.
Independent of the P1RSEN bit setting, if the auto shut-
down source is one of the comparators, the shutdown
condition is a level. The ECCP1ASE bit cannot be
cleared as long as the cause of the shutdown persists.
The P1A, P1B, P1C and P1D output latches may not be
in the proper states when the PWM module is initialized.
Enabling the PWM pins for output at the same time as
the ECCP module may cause damage to the applica-
tion circuit. The ECCP module must be enabled in the
proper output mode and complete a full PWM cycle
before configuring the PWM pins as outputs. The com-
pletion of a full PWM cycle is indicated by the TMR2IF
bit being set as the second PWM period begins.
The Auto Shutdown mode can be forced by writing a ‘1’
to the ECCPASE bit.
FIGURE 17-10:
PWM AUTO SHUTDOWN (PRSEN = 1, AUTO RESTART ENABLED)
PWM Period
Shutdown Event
ECCPASE bit
PWM Activity
Normal PWM
Start of
PWM Period
Shutdown
Event Occurs Event Clears
Shutdown
PWM
Resumes
FIGURE 17-11:
PWM AUTO SHUTDOWN (PRSEN = 0, AUTO RESTART DISABLED)
PWM Period
Shutdown Event
ECCPASE bit
PWM Activity
Normal PWM
ECCPASE
Cleared by
Firmware
Start of
PWM Period
Shutdown
Event Occurs Event Clears
Shutdown
PWM
Resumes
DS39612A-page 172
Advance Information
2003 Microchip Technology Inc.
PIC18F6X2X/8X2X
7. If auto restart operation is required, set the
PxRSEN bit (ECCPxDEL<7>).
17.4.9
SETUP FOR PWM OPERATION
The following steps should be taken when configuring
the ECCPx module for PWM operation:
8. Configure and start TMRn (TMR2 or TMR4):
• Clear the TMRn interrupt flag bit by clearing
the TMRnIF bit (PIR1<1> for Timer2 or
PIR3<3> for Timer4).
1. Configure the PWM pins PxA and PxB (and PxC
and PxD, if used) as inputs by setting the
corresponding TRIS bits.
• Set the TMRn prescale value by loading the
TnCKPS bits (TnCON<1:0>).
2. Set the PWM period by loading the PR2 (PR4)
register.
• Enable Timer2 (or Timer4) by setting the
TMRnON bit (TnCON<2>).
3. Configure the ECCPx module for the desired
PWM mode and configuration by loading the
CCPxCON register with the appropriate values:
9. Enable PWM outputs after a new PWM cycle
has started:
• Select one of the available output
configurations and direction with the
PxM1:PxM0 bits.
• Wait until TMRn overflows (TMRnIF bit is set).
• Enable the CCPx/PxA, PxB, PxC and/or PxD
pin outputs by clearing the respective TRIS
bits.
• Select the polarities of the PWM output
signals with the CCPxM3:CCPxM0 bits.
• Clear the ECCPASE bit (ECCPxAS<7>).
4. Set the PWM duty cycle by loading the CCPRxL
register and CCPxCON<5:4> bits.
17.4.10 EFFECTS OF A RESET
5. For Half-Bridge Output mode, set the dead band
delay by loading ECCPxDEL<6:0> with the
appropriate value.
Both Power-on Reset and subsequent RESETS will
force all ports to Input mode and the CCP registers to
their RESET states.
6. If auto shutdown operation is required, load the
ECCPxAS register:
This forces the enhanced CCP module to reset to a
state compatible with the standard CCP module.
• Select the auto shutdown sources using the
ECCPxAS2:ECCPxAS0 bits.
• Select the shutdown states of the PWM
output pins using PSSxAC1:PSSxAC0 and
PSSxBD1:PSSxBD0 bits.
• Set the ECCPxASE bit (ECCPxAS<7>).
• Configure the comparators using the CMCON
register.
• Configure the comparator inputs as analog
inputs.
2003 Microchip Technology Inc.
Advance Information
DS39612A-page 173
PIC18F6X2X/8X2X
TABLE 17-5: REGISTERS ASSOCIATED WITH ECCP MODULES AND TIMER1 TO TIMER4
Value on
all other
RESETS
Value on
POR, BOR
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
INTCON
RCON
PIR1
GIE/GIEH PEIE/GIEL
TMR0IE
—
INT0IE
RI
RBIE
TO
TMR0IF
PD
INT0IF
POR
RBIF
BOR
0000 000x 0000 000u
0--1 11qq 0--q qquu
IPEN
PSPIF
PSPIE
PSPIP
—
—
ADIF
ADIE
ADIP
CMIE
CMIF
CMIP
—
RCIF
RCIE
RCIP
—
TXIF
TXIE
TXIP
EEIE
EEIF
EEIP
TX2IF
TX2IE
TX2IP
SSPIF
SSPIE
SSPIP
BCLIF
BCLIE
BCLIP
TMR4IF
TMR4IE
TMR4IP
CCP1IF
CCP1IE
CCP1IP
LVDIF
TMR2IF
TMR2IE
TMR2IP
TMR3IF
TMR3IE
TMR3IP
CCP4IF
CCP4IE
CCP4IP
TMR1IF 0000 0000 0000 0000
TMR1IF 0000 0000 0000 0000
TMR1IF 1111 1111 1111 1111
CCP2IF -0-0 0000 ---0 0000
CCP2IE -0-0 0000 ---0 0000
CCP2IP -1-1 1111 ---1 1111
CCP3IF --00 0000 --00 0000
CCP3IE --00 0000 --00 0000
CCP3IP --11 1111 --11 1111
1111 1111 1111 1111
PIE1
IPR1
PIR2
PIE2
—
—
LVDIE
IPR2
—
—
LVDIP
PIR3
—
RC2IF
RC2IE
RC2IP
CCP5IF
CCP5IE
CCP5IP
PIE3
—
—
IPR3
—
—
TRISB
TRISC
TRISE
TRISG
TRISH
TMR1L
TMR1H
T1CON
TMR2
T2CON
PR2
PORTB Data Direction Register
PORTC Data Direction Register
PORTE Data Direction Register
1111 1111 1111 1111
1111 1111 1111 1111
—
—
—
PORTG Data Direction Register
---1 1111 ---1 1111
PORTH Data Direction Register
1111 1111 1111 1111
Holding Register for the Least Significant Byte of the 16-bit TMR1 Register
Holding Register for the Most Significant Byte of the 16-bit TMR1 Register
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
RD16
—
T1CKPS1
T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 0-00 0000 u-uu uuuu
Timer2 Module Register
0000 0000 0000 0000
—
T2OUTPS3 T2OUTPS2 T2OUTPS1 T2OUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 -000 0000
Timer2 Period Register
1111 1111 1111 1111
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
TMR3L
TMR3H
T3CON
TMR4
T4CON
PR4
Holding Register for the Least Significant Byte of the 16-bit TMR3 Register
Holding Register for the Most Significant Byte of the 16-bit TMR3 Register
RD16
T3CCP2
T3CKPS1
T3CKPS0
T3CCP1
T3SYNC TMR3CS TMR3ON 0000 0000 uuuu uuuu
Timer4 Module Register
0000 0000 0000 0000
—
T4OUTPS3 T4OUTPS2 T4OUTPS1 T4OUTPS0 TMR4ON T4CKPS1 T4CKPS0 -000 0000 -000 0000
Timer4 Period Register
1111 1111 1111 1111
xxxx xxxx uuuu uuuu
(1)
CCPRxL
CCPRxH
Capture/Compare/PWM Register 1 (LSB)
Capture/Compare/PWM Register 1 (MSB)
(1)
(1)
xxxx xxxx uuuu uuuu
CCPxCON
PxM1
PxM0
DCxB1
DCxB0
CCPxM3
CCPxM2 CCPxM1 CCPxM0 0000 0000 0000 0000
(1)
ECCPxAS
ECCPxASE ECCPxAS2 ECCPxAS1 ECCPxAS0 PSSxAC1 PSSxAC0 PSSxBD1 PSSxBD0 0000 0000 0000 0000
(1)
ECCPxDEL
PxRSEN
PxDC6
PxDC5
PxDC4
PxDC3
PxDC2
PxDC1
PxDC0
0000 0000 uuuu uuuu
Legend:
x= unknown, u= unchanged, - = unimplemented, read as ‘0’. Shaded cells are not used during ECCP operation.
Note 1: Generic term for all of the identical registers of this name for all enhanced CCP modules, where ‘x’ identifies the individual
module (ECCP1, ECCP2 or ECCP3). Bit assignments and RESET values for all registers of the same generic name are
identical.
DS39612A-page 174
Advance Information
2003 Microchip Technology Inc.
PIC18F6X2X/8X2X
18.3 SPI Mode
18.0 MASTER SYNCHRONOUS
SERIAL PORT (MSSP)
MODULE
The SPI mode allows 8 bits of data to be synchronously
transmitted and received simultaneously. All four
modes of SPI are supported. To accomplish
communication, typically three pins are used:
18.1 Master SSP (MSSP) Module
Overview
• Serial Data Out (SDO) - RC5/SDO
• Serial Data In (SDI) - RC4/SDI/SDA
• Serial Clock (SCK) - RC3/SCK/SCL
The Master Synchronous Serial Port (MSSP) module is
a serial interface, useful for communicating with other
peripheral or microcontroller devices. These peripheral
devices may be serial EEPROMs, shift registers, dis-
play drivers, A/D converters, etc. The MSSP module
can operate in one of two modes:
Additionally, a fourth pin may be used when in a Slave
mode of operation:
• Slave Select (SS) - RF7/SS
Figure 18-1 shows the block diagram of the MSSP
module when operating in SPI mode.
• Serial Peripheral Interface (SPI)
• Inter-Integrated Circuit (I2C)
- Full Master mode
FIGURE 18-1:
MSSP BLOCK DIAGRAM
(SPI MODE)
- Slave mode (with general address call)
The I2C interface supports the following modes in
hardware:
Internal
Data Bus
Read
Write
• Master mode
• Multi-Master mode
• Slave mode
SSPBUF reg
SSPSR reg
18.2 Control Registers
RC4/SDI/SDA
RC5/SDO
The MSSP module has three associated registers.
These include a status register (SSPSTAT) and two
control registers (SSPCON1 and SSPCON2). The use
of these registers and their individual configuration bits
differ significantly depending on whether the MSSP
module is operated in SPI or I2C mode.
Shift
Clock
bit0
RF7/SS
Control
Enable
SS
Additional details are provided under the individual
sections.
Edge
Select
2
Clock Select
SSPM3:SSPM0
SMP:CKE
2
4
TMR2 Output
RC3/SCK/
SCL
(
)
2
Edge
Select
TOSC
Prescaler
4, 16, 64
Data to TX/RX in SSPSR
TRIS bit
2003 Microchip Technology Inc.
Advance Information
DS39612A-page 175
PIC18F6X2X/8X2X
SSPSR is the shift register used for shifting data in or
out. SSPBUF is the buffer register to which data bytes
are written to or read from.
18.3.1
REGISTERS
The MSSP module has four registers for SPI mode
operation. These are:
In receive operations, SSPSR and SSPBUF together
create a double-buffered receiver. When SSPSR
receives a complete byte, it is transferred to SSPBUF
and the SSPIF interrupt is set.
• MSSP Control Register 1 (SSPCON1)
• MSSP Status Register (SSPSTAT)
• Serial Receive/Transmit Buffer Register
(SSPBUF)
During transmission, the SSPBUF is not double-
buffered. A write to SSPBUF will write to both SSPBUF
and SSPSR.
• MSSP Shift Register (SSPSR) - Not directly
accessible
SSPCON1 and SSPSTAT are the control and status
registers in SPI mode operation. The SSPCON1 regis-
ter is readable and writable. The lower 6 bits of the
SSPSTAT are read only. The upper two bits of the
SSPSTAT are read/write.
REGISTER 18-1: SSPSTAT: MSSP STATUS REGISTER (SPI MODE)
R/W-0
SMP
R/W-0
CKE
R-0
D/A
R-0
P
R-0
S
R-0
R-0
UA
R-0
BF
R/W
bit 7
bit 0
bit 7
bit 6
SMP: Sample bit
SPI Master mode:
1= Input data sampled at end of data output time
0= Input data sampled at middle of data output time
SPI Slave mode:
SMP must be cleared when SPI is used in Slave mode.
CKE: SPI Clock Edge Select bit
When CKP = 0:
1= Data transmitted on rising edge of SCK
0= Data transmitted on falling edge of SCK
When CKP = 1:
1= Data transmitted on falling edge of SCK
0= Data transmitted on rising edge of SCK
bit 5
bit 4
D/A: Data/Address bit
Used in I2C mode only.
P: STOP bit
Used in I2C mode only. This bit is cleared when the MSSP module is disabled, SSPEN is
cleared.
bit 3
bit 2
bit 1
bit 0
S: START bit
Used in I2C mode only.
R/W: Read/Write bit Information
Used in I2C mode only.
UA: Update Address bit
Used in I2C mode only.
BF: Buffer Full Status bit (Receive mode only)
1= Receive complete, SSPBUF is full
0= Receive not complete, SSPBUF is empty
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
- n = Value at POR
DS39612A-page 176
Advance Information
2003 Microchip Technology Inc.
PIC18F6X2X/8X2X
REGISTER 18-2: SSPCON1: MSSP CONTROL REGISTER 1 (SPI MODE)
R/W-0
WCOL
R/W-0
R/W-0
R/W-0
CKP
R/W-0
R/W-0
R/W-0
R/W-0
SSPOV
SSPEN
SSPM3
SSPM2
SSPM1
SSPM0
bit 7
bit 0
bit 7
bit 6
WCOL: Write Collision Detect bit (Transmit mode only)
1= The SSPBUF register is written while it is still transmitting the previous word
(must be cleared in software)
0= No collision
SSPOV: Receive Overflow Indicator bit
SPI Slave mode:
1= A new byte is received while the SSPBUF register is still holding the previous data. In case
of overflow, the data in SSPSR is lost. Overflow can only occur in Slave mode. The user
must read the SSPBUF, even if only transmitting data, to avoid setting overflow (must be
cleared in software).
0= No overflow
Note:
In Master mode, the overflow bit is not set since each new reception (and
transmission) is initiated by writing to the SSPBUF register.
bit 5
bit 4
SSPEN: Synchronous Serial Port Enable bit
1= Enables serial port and configures SCK, SDO, SDI, and SS as serial port pins
0= Disables serial port and configures these pins as I/O port pins
Note:
When enabled, these pins must be properly configured as input or output.
CKP: Clock Polarity Select bit
1= IDLE state for clock is a high level
0= IDLE state for clock is a low level
bit 3-0 SSPM3:SSPM0: Synchronous Serial Port Mode Select bits
0101= SPI Slave mode, clock = SCK pin, SS pin control disabled, SS can be used as I/O pin
0100= SPI Slave mode, clock = SCK pin, SS pin control enabled
0011= SPI Master mode, clock = TMR2 output/2
0010= SPI Master mode, clock = FOSC/64
0001= SPI Master mode, clock = FOSC/16
0000= SPI Master mode, clock = FOSC/4
Note:
Bit combinations not specifically listed here are either reserved or implemented in
I2C mode only.
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
- n = Value at POR
2003 Microchip Technology Inc.
Advance Information
DS39612A-page 177
PIC18F6X2X/8X2X
reading the data that was just received. Any write to the
SSPBUF register during transmission/reception of data
will be ignored, and the write collision detect bit, WCOL
(SSPCON1<7>), will be set. User software must clear
the WCOL bit so that it can be determined if the follow-
ing write(s) to the SSPBUF register completed
successfully.
18.3.2
OPERATION
When initializing the SPI, several options need to be
specified. This is done by programming the appropriate
control bits (SSPCON1<5:0>) and SSPSTAT<7:6>.
These control bits allow the following to be specified:
• Master mode (SCK is the clock output)
• Slave mode (SCK is the clock input)
• Clock Polarity (IDLE state of SCK)
When the application software is expecting to receive
valid data, the SSPBUF should be read before the next
byte of data to transfer is written to the SSPBUF. Buffer
full bit, BF (SSPSTAT<0>), indicates when SSPBUF
has been loaded with the received data (transmission
is complete). When the SSPBUF is read, the BF bit is
cleared. This data may be irrelevant if the SPI is only a
transmitter. Generally, the MSSP interrupt is used to
determine when the transmission/reception has com-
pleted. The SSPBUF must be read and/or written. If the
interrupt method is not going to be used, then software
polling can be done to ensure that a write collision does
not occur. Example 18-1 shows the loading of the
SSPBUF (SSPSR) for data transmission.
• Data Input Sample Phase (middle or end of data
output time)
• Clock Edge (output data on rising/falling edge of
SCK)
• Clock Rate (Master mode only)
• Slave Select mode (Slave mode only)
The MSSP consists of a Transmit/Receive Shift regis-
ter (SSPSR) and a Buffer register (SSPBUF). The
SSPSR shifts the data in and out of the device, MSb
first. The SSPBUF holds the data that was written to the
SSPSR until the received data is ready. Once the 8 bits
of data have been received, that byte is moved to the
SSPBUF register. Then the buffer full detect bit, BF
(SSPSTAT<0>), and the interrupt flag bit, SSPIF, are
set. This double-buffering of the received data
(SSPBUF) allows the next byte to start reception before
The SSPSR is not directly readable or writable, and
can only be accessed by addressing the SSPBUF reg-
ister. Additionally, the MSSP status register (SSPSTAT)
indicates the various status conditions.
EXAMPLE 18-1:
LOADING THE SSPBUF (SSPSR) REGISTER
LOOP
BTFSS
BRA
SSPSTAT, BF
LOOP
;Has data been received (transmit complete)?
;No
MOVF
SSPBUF, W
;WREG reg = contents of SSPBUF
MOVWF
RXDATA
;Save in user RAM, if data is meaningful
MOVF
MOVWF
TXDATA, W
SSPBUF
;W reg = contents of TXDATA
;New data to xmit
DS39612A-page 178
Advance Information
2003 Microchip Technology Inc.
PIC18F6X2X/8X2X
18.3.3
ENABLING SPI I/O
18.3.4
TYPICAL CONNECTION
To enable the serial port, SSP enable bit, SSPEN
(SSPCON1<5>), must be set. To reset or reconfigure
SPI mode, clear the SSPEN bit, re-initialize the
SSPCON registers, and then set the SSPEN bit. This
configures the SDI, SDO, SCK, and SS pins as serial
port pins. For the pins to behave as the serial port func-
tion, some must have their data direction bits (in the
TRIS register) appropriately programmed as follows:
Figure 18-2 shows a typical connection between two
microcontrollers. The master controller (Processor 1)
initiates the data transfer by sending the SCK signal.
Data is shifted out of both shift registers on their pro-
grammed clock edge, and latched on the opposite
edge of the clock. Both processors should be pro-
grammed to the same Clock Polarity (CKP), then both
controllers would send and receive data at the same
time. Whether the data is meaningful (or dummy data)
depends on the application software. This leads to
three scenarios for data transmission:
• SDI is automatically controlled by the SPI module
• SDO must have TRISC<5> bit cleared
• SCK (Master mode) must have TRISC<3> bit
cleared
• Master sends data — Slave sends dummy data
• Master sends data — Slave sends data
• SCK (Slave mode) must have TRISC<3> bit set
• SS must have TRISF<7> bit set
• Master sends dummy data — Slave sends data
Any serial port function that is not desired may be
overridden by programming the corresponding Data
Direction (TRIS) register to the opposite value.
FIGURE 18-2:
SPI MASTER/SLAVE CONNECTION
SPI Master SSPM3:SSPM0 = 00xxb
SPI Slave SSPM3:SSPM0 = 010xb
SDO
SDI
Serial Input Buffer
(SSPBUF)
Serial Input Buffer
(SSPBUF)
SDI
SDO
Shift Register
(SSPSR)
Shift Register
(SSPSR)
LSb
MSb
MSb
LSb
Serial Clock
SCK
SCK
PROCESSOR 1
PROCESSOR 2
2003 Microchip Technology Inc.
Advance Information
DS39612A-page 179
PIC18F6X2X/8X2X
The clock polarity is selected by appropriately
programming the CKP bit (SSPCON1<4>). This then,
would give waveforms for SPI communication as
shown in Figure 18-3, Figure 18-5, and Figure 18-6,
where the MSB is transmitted first. In Master mode, the
SPI clock rate (bit rate) is user programmable to be one
of the following:
18.3.5
MASTER MODE
The master can initiate the data transfer at any time
because it controls the SCK. The master determines
when the slave (Processor 2, Figure 18-2) is to
broadcast data by the software protocol.
In Master mode, the data is transmitted/received as
soon as the SSPBUF register is written to. If the SPI is
only going to receive, the SDO output could be dis-
abled (programmed as an input). The SSPSR register
will continue to shift in the signal present on the SDI pin
at the programmed clock rate. As each byte is
received, it will be loaded into the SSPBUF register as
if a normal received byte (interrupts and status bits
appropriately set). This could be useful in receiver
applications as a “Line Activity Monitor” mode.
• FOSC/4 (or TCY)
• FOSC/16 (or 4 • TCY)
• FOSC/64 (or 16 • TCY)
• Timer2 output/2
This allows a maximum data rate (at 40 MHz) of
10.00 Mbps.
Figure 18-3 shows the waveforms for Master mode.
FIGURE 18-3:
SPI MODE WAVEFORM (MASTER MODE)
Write to
SSPBUF
SCK
(CKP = 0
CKE = 0)
SCK
(CKP = 1
CKE = 0)
4 Clock
Modes
SCK
(CKP = 0
CKE = 1)
SCK
(CKP = 1
CKE = 1)
bit 6
bit 6
bit 2
bit 2
bit 5
bit 5
bit 4
bit 4
bit 1
bit 1
bit 0
bit 0
SDO
(CKE = 0)
bit 7
bit 7
bit 3
bit 3
SDO
(CKE = 1)
SDI
(SMP = 0)
bit 0
bit 7
Input
Sample
(SMP = 0)
SDI
(SMP = 1)
bit 0
bit 7
Input
Sample
(SMP = 1)
SSPIF
Next Q4 Cycle
after Q2↓
SSPSR to
SSPBUF
DS39612A-page 180
Advance Information
2003 Microchip Technology Inc.
PIC18F6X2X/8X2X
even if in the middle of a transmitted byte, and
becomes a floating output. External pull-up/pull-down
resistors may be desirable, depending on the
application.
18.3.6
SLAVE MODE
In Slave mode, the data is transmitted and received as
the external clock pulses appear on SCK. When the
last bit is latched, the SSPIF interrupt flag bit is set.
Note 1: When the SPI is in Slave mode with SS
pin control enabled (SSPCON<3:0> =
0100), the SPI module will reset if the SS
pin is set to VDD.
While in Slave mode, the external clock is supplied by
the external clock source on the SCK pin. This external
clock must meet the minimum high and low times as
specified in the electrical specifications.
2: If the SPI is used in Slave mode with CKE
set, then the SS pin control must be
enabled.
While in SLEEP mode, the slave can transmit/receive
data. When a byte is received, the device will wake-up
from SLEEP.
When the SPI module resets, the bit counter is forced
to ‘0’. This can be done by either forcing the SS pin to
a high level or clearing the SSPEN bit.
18.3.7
SLAVE SELECT
SYNCHRONIZATION
The SS pin allows a Synchronous Slave mode. The
SPI must be in Slave mode with SS pin control enabled
(SSPCON1<3:0> = 04h). The pin must not be driven
low for the SS pin to function as an input. The data latch
must be high. When the SS pin is low, transmission and
reception are enabled and the SDO pin is driven. When
the SS pin goes high, the SDO pin is no longer driven
To emulate two-wire communication, the SDO pin can
be connected to the SDI pin. When the SPI needs to
operate as a receiver, the SDO pin can be configured
as an input. This disables transmissions from the SDO.
The SDI can always be left as an input (SDI function)
since it cannot create a bus conflict.
FIGURE 18-4:
SLAVE SYNCHRONIZATION WAVEFORM
SS
SCK
(CKP = 0
CKE = 0)
SCK
(CKP = 1
CKE = 0)
Write to
SSPBUF
bit 6
bit 7
bit 7
bit 0
SDO
bit 7
SDI
(SMP = 0)
bit 0
bit 7
Input
Sample
(SMP = 0)
SSPIF
Interrupt
Flag
Next Q4 Cycle
SSPSR to
SSPBUF
after Q2↓
2003 Microchip Technology Inc.
Advance Information
DS39612A-page 181
PIC18F6X2X/8X2X
FIGURE 18-5:
SPI MODE WAVEFORM (SLAVE MODE WITH CKE = 0)
SS
Optional
SCK
(CKP = 0
CKE = 0)
SCK
(CKP = 1
CKE = 0)
Write to
SSPBUF
bit 6
bit 2
bit 5
bit 4
bit 3
bit 1
bit 0
SDO
bit 7
SDI
(SMP = 0)
bit 0
bit 7
Input
Sample
(SMP = 0)
SSPIF
Interrupt
Flag
Next Q4 Cycle
after Q2↓
SSPSR to
SSPBUF
FIGURE 18-6:
SPI MODE WAVEFORM (SLAVE MODE WITH CKE = 1)
SS
Not Optional
SCK
(CKP = 0
CKE = 1)
SCK
(CKP = 1
CKE = 1)
Write to
SSPBUF
bit 6
bit 2
bit 5
bit 4
bit 1
bit 0
SDO
bit 7
bit 7
bit 3
SDI
(SMP = 0)
bit 0
Input
Sample
(SMP = 0)
SSPIF
Interrupt
Flag
Next Q4 Cycle
after Q2↓
SSPSR to
SSPBUF
DS39612A-page 182
Advance Information
2003 Microchip Technology Inc.
PIC18F6X2X/8X2X
18.3.8
SLEEP OPERATION
18.3.10 BUS MODE COMPATIBILITY
In Master mode, all module clocks are halted and the
transmission/reception will remain in that state until the
device wakes from SLEEP. After the device returns to
normal mode, the module will continue to transmit/
receive data.
Table 18-1 shows the compatibility between the
standard SPI modes and the states of the CKP and
CKE control bits.
TABLE 18-1: SPI BUS MODES
In Slave mode, the SPI Transmit/Receive Shift register
operates asynchronously to the device. This allows the
device to be placed in SLEEP mode and data to be
shifted into the SPI Transmit/Receive Shift register.
When all 8 bits have been received, the MSSP interrupt
flag bit will be set and if enabled, will wake the device
from SLEEP.
Control Bits State
Standard SPI Mode
Terminology
CKP
CKE
0, 0
0, 1
1, 0
1, 1
0
0
1
1
1
0
1
0
18.3.9
EFFECTS OF A RESET
There is also a SMP bit which controls when the data is
sampled.
A RESET disables the MSSP module and terminates
the current transfer.
TABLE 18-2: REGISTERS ASSOCIATED WITH SPI OPERATION
Value on
all other
RESETS
Value on
POR, BOR
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
INTCON
PIR1
GIE/GIEH PEIE/GIEL TMR0IE INT0IE
RBIE
SSPIF
SSPIE
SSPIP
TMR0IF
INT0IF
RBIF
0000 0000 0000 0000
PSPIF
PSPIE
PSPIP
ADIF
ADIE
ADIP
RCIF
RCIE
RCIP
TXIF
TXIE
TXIP
CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
CCP1IP TMR2IP TMR1IP 1111 1111 1111 1111
1111 1111 1111 1111
PIE1
IPR1
TRISC
PORTC Data Direction Register
TRISF7 TRISF6 TRISF5 TRISF4 TRISF3
Synchronous Serial Port Receive Buffer/Transmit Register
TRISF
TRISF2
TRISF1 TRISF0 1111 1111 uuuu uuuu
xxxx xxxx uuuu uuuu
SSPBUF
SSPCON1
SSPSTAT
Legend:
WCOL
SMP
SSPOV
CKE
SSPEN
D/A
CKP
P
SSPM3
S
SSPM2
R/W
SSPM1 SSPM0 0000 0000 0000 0000
UA
BF
0000 0000 0000 0000
x= unknown, u= unchanged, - = unimplemented, read as ‘0’. Shaded cells are not used by the MSSP in SPI mode.
2003 Microchip Technology Inc.
Advance Information
DS39612A-page 183
PIC18F6X2X/8X2X
2
18.4.1
REGISTERS
18.4 I C Mode
The MSSP module has six registers for I2C operation.
These are:
The MSSP module in I2C mode fully implements all
master and slave functions (including general call sup-
port) and provides interrupts on START and STOP bits
in hardware to determine a free bus (multi-master func-
tion). The MSSP module implements the standard
mode specifications as well as 7-bit and 10-bit
addressing.
• MSSP Control Register 1 (SSPCON1)
• MSSP Control Register 2 (SSPCON2)
• MSSP Status Register (SSPSTAT)
• Serial Receive/Transmit Buffer Register
(SSPBUF)
Two pins are used for data transfer:
• MSSP Shift Register (SSPSR) - Not directly
accessible
• Serial clock (SCL) - RC3/SCK/SCL
• Serial data (SDA) - RC4/SDI/SDA
• MSSP Address Register (SSPADD)
The user must configure these pins as inputs or outputs
through the TRISC<4:3> bits.
SSPCON1, SSPCON2 and SSPSTAT are the control
and status registers in I2C mode operation. The
SSPCON1 and SSPCON2 registers are readable and
writable. The lower 6 bits of the SSPSTAT are
read only. The upper two bits of the SSPSTAT are
read/write.
FIGURE 18-7:
MSSP BLOCK DIAGRAM
(I2C MODE)
Internal
Data Bus
SSPSR is the shift register used for shifting data in or
out. SSPBUF is the buffer register to which data bytes
are written to or read from.
Read
Write
SSPADD register holds the slave device address
when the SSP is configured in I2C Slave mode. When
the SSP is configured in Master mode, the lower
seven bits of SSPADD act as the baud rate generator
reload value.
SSPBUF reg
RC3/SCK/SCL
Shift
Clock
SSPSR reg
In receive operations, SSPSR and SSPBUF together
create a double-buffered receiver. When SSPSR
receives a complete byte, it is transferred to SSPBUF
and the SSPIF interrupt is set.
RC4/
SDI/
SDA
MSb
LSb
Addr Match
Match Detect
During transmission, the SSPBUF is not double-
buffered. A write to SSPBUF will write to both SSPBUF
and SSPSR.
SSPADD reg
START and
Set, Reset
S, P bits
(SSPSTAT reg)
STOP bit Detect
DS39612A-page 184
Advance Information
2003 Microchip Technology Inc.
PIC18F6X2X/8X2X
REGISTER 18-3: SSPSTAT: MSSP STATUS REGISTER (I2C MODE)
R/W-0
SMP
R/W-0
CKE
R-0
D/A
R-0
P
R-0
S
R-0
R-0
UA
R-0
BF
R/W
bit 7
bit 0
bit 7
SMP: Slew Rate Control bit
In Master or Slave mode:
1 = Slew rate control disabled for Standard Speed mode (100 kHz and 1 MHz)
0 = Slew rate control enabled for High Speed mode (400 kHz)
bit 6
bit 5
CKE: SMBus Select bit
In Master or Slave mode:
1= Enable SMBus specific inputs
0= Disable SMBus specific inputs
D/A: Data/Address bit
In Master mode:
Reserved.
In Slave mode:
1= Indicates that the last byte received or transmitted was data
0= Indicates that the last byte received or transmitted was address
bit 4
bit 3
bit 2
P: STOP bit
1= Indicates that a STOP bit has been detected last
0= STOP bit was not detected last
Note:
This bit is cleared on RESET and when SSPEN is cleared.
S: START bit
1= Indicates that a START bit has been detected last
0= START bit was not detected last
Note:
This bit is cleared on RESET and when SSPEN is cleared.
R/W: Read/Write bit Information (I2C mode only)
In Slave mode:
1= Read
0= Write
Note:
This bit holds the R/W bit information following the last address match. This bit is only
valid from the address match to the next START bit, STOP bit, or not ACK bit.
In Master mode:
1= Transmit is in progress
0= Transmit is not in progress
Note:
ORing this bit with SEN, RSEN, PEN, RCEN, or ACKEN will indicate if the MSSP is
in IDLE mode.
bit 1
bit 0
UA: Update Address bit (10-bit Slave mode only)
1= Indicates that the user needs to update the address in the SSPADD register
0= Address does not need to be updated
BF: Buffer Full Status bit
In Transmit mode:
1= Receive complete, SSPBUF is full
0= Receive not complete, SSPBUF is empty
In Receive mode:
1= Data transmit in progress (does not include the ACK and STOP bits), SSPBUF is full
0= Data transmit complete (does not include the ACK and STOP bits), SSPBUF is empty
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
- n = Value at POR
2003 Microchip Technology Inc.
Advance Information
DS39612A-page 185
PIC18F6X2X/8X2X
REGISTER 18-4: SSPCON1: MSSP CONTROL REGISTER 1 (I2C MODE)
R/W-0
WCOL
R/W-0
R/W-0
R/W-0
CKP
R/W-0
R/W-0
R/W-0
R/W-0
SSPOV
SSPEN
SSPM3
SSPM2
SSPM1
SSPM0
bit 7
bit 0
bit 7
WCOL: Write Collision Detect bit
In Master Transmit mode:
1= A write to the SSPBUF register was attempted while the I2C conditions were not valid for
a transmission to be started (must be cleared in software)
0= No collision
In Slave Transmit mode:
1= The SSPBUF register is written while it is still transmitting the previous word (must be
cleared in software)
0= No collision
In Receive mode (Master or Slave modes):
This is a “don’t care” bit.
bit 6
SSPOV: Receive Overflow Indicator bit
In Receive mode:
1= A byte is received while the SSPBUF register is still holding the previous byte (must be
cleared in software)
0= No overflow
In Transmit mode:
This is a “don’t care” bit in Transmit mode.
bit 5
bit 4
SSPEN: Synchronous Serial Port Enable bit
1= Enables the serial port and configures the SDA and SCL pins as the serial port pins
0= Disables serial port and configures these pins as I/O port pins
Note:
When enabled, the SDA and SCL pins must be properly configured as input or
output.
CKP: SCK Release Control bit
In Slave mode:
1= Release clock
0= Holds clock low (clock stretch), used to ensure data setup time
In Master mode:
Unused in this mode.
bit 3-0 SSPM3:SSPM0: Synchronous Serial Port Mode Select bits
1111= I2C Slave mode, 10-bit address with START and STOP bit interrupts enabled
1110= I2C Slave mode, 7-bit address with START and STOP bit interrupts enabled
1011= I2C Firmware Controlled Master mode (Slave IDLE)
1000= I2C Master mode, clock = FOSC / (4 * (SSPADD+1))
0111= I2C Slave mode, 10-bit address
0110= I2C Slave mode, 7-bit address
Note:
Bit combinations not specifically listed here are either reserved or implemented in
SPI mode only.
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
- n = Value at POR
DS39612A-page 186
Advance Information
2003 Microchip Technology Inc.
PIC18F6X2X/8X2X
REGISTER 18-5: SSPCON2: MSSP CONTROL REGISTER 2 (I2C MODE)
R/W-0
GCEN
R/W-0
R/W-0
R/W-0
R/W-0
RCEN
R/W-0
PEN
R/W-0
RSEN
R/W-0
SEN
ACKSTAT
ACKDT
ACKEN
bit 7
bit 0
bit 7
bit 6
bit 5
GCEN: General Call Enable bit (Slave mode only)
1= Enable interrupt when a general call address (0000h) is received in the SSPSR
0= General call address disabled
ACKSTAT: Acknowledge Status bit (Master Transmit mode only)
1= Acknowledge was not received from slave
0= Acknowledge was received from slave
ACKDT: Acknowledge Data bit (Master Receive mode only)
1= Not Acknowledge
0= Acknowledge
Note:
Value that will be transmitted when the user initiates an Acknowledge sequence at
the end of a receive.
bit 4
ACKEN: Acknowledge Sequence Enable bit (Master Receive mode only)
1= Initiate Acknowledge sequence on SDA and SCL pins, and transmit ACKDT data bit.
Automatically cleared by hardware.
0= Acknowledge sequence IDLE
bit 3
bit 2
RCEN: Receive Enable bit (Master mode only)
1= Enables Receive mode for I2C
0= Receive IDLE
PEN: STOP Condition Enable bit (Master mode only)
1= Initiate STOP condition on SDA and SCL pins. Automatically cleared by hardware.
0= STOP condition IDLE
bit 1
bit 0
RSEN: Repeated START Condition Enabled bit (Master mode only)
1= Initiate Repeated START condition on SDA and SCL pins. Automatically cleared by
hardware.
0= Repeated START condition IDLE
SEN: START Condition Enabled/Stretch Enabled bit
In Master mode:
1= Initiate START condition on SDA and SCL pins. Automatically cleared by hardware.
0= START condition IDLE
In Slave mode:
1= Clock stretching is enabled for both slave transmit and slave receive (stretch enabled)
0= Clock stretching is disabled
Note:
For bits ACKEN, RCEN, PEN, RSEN, SEN: If the I2C module is not in the IDLE
mode, this bit may not be set (no spooling) and the SSPBUF may not be written (or
writes to the SSPBUF are disabled).
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
- n = Value at POR
2003 Microchip Technology Inc.
Advance Information
DS39612A-page 187
PIC18F6X2X/8X2X
18.4.2
OPERATION
18.4.3.1
Addressing
The MSSP module functions are enabled by setting
MSSP enable bit, SSPEN (SSPCON<5>).
The SSPCON1 register allows control of the I2C oper-
ation. Four mode selection bits (SSPCON<3:0>) allow
one of the following I2C modes to be selected:
• I2C Master mode, clock = (FOSC / 4) x
(SSPADD + 1)
• I2C Slave mode (7-bit address)
• I2C Slave mode (10-bit address)
• I2C Slave mode (7-bit address), with START and
STOP bit interrupts enabled
• I2C Slave mode (10-bit address), with START and
STOP bit interrupts enabled
• I2C firmware controlled master operation, slave is
IDLE
Once the MSSP module has been enabled, it waits for
a START condition to occur. Following the START con-
dition, the 8-bits are shifted into the SSPSR register. All
incoming bits are sampled with the rising edge of the
clock (SCL) line. The value of register SSPSR<7:1> is
compared to the value of the SSPADD register. The
address is compared on the falling edge of the eighth
clock (SCL) pulse. If the addresses match and the BF
and SSPOV bits are clear, the following events occur:
1. The SSPSR register value is loaded into the
SSPBUF register.
2. The buffer full bit BF is set.
3. An ACK pulse is generated.
4. MSSP interrupt flag bit, SSPIF (PIR1<3>), is set
(interrupt is generated, if enabled) on the falling
edge of the ninth SCL pulse.
Selection of any I2C mode with the SSPEN bit set,
forces the SCL and SDA pins to be open drain,
provided these pins are programmed to inputs by
setting the appropriate TRISC bits. To ensure proper
operation of the module, pull-up resistors must be
provided externally to the SCL and SDA pins.
In 10-bit Address mode, two address bytes need to be
received by the slave. The five Most Significant bits
(MSbs) of the first address byte specify if this is a 10-bit
address. Bit R/W (SSPSTAT<2>) must specify a write so
the slave device will receive the second address byte.
For a 10-bit address, the first byte would equal ‘11110
A9 A8 0’, where ‘A9’ and ‘A8’ are the two MSbs of the
address. The sequence of events for 10-bit address is as
follows, with steps 7 through 9 for the slave-transmitter:
18.4.3
SLAVE MODE
In Slave mode, the SCL and SDA pins must be config-
ured as inputs (TRISC<4:3> set). The MSSP module
will override the input state with the output data when
required (slave-transmitter).
The I2C Slave mode hardware will always generate an
interrupt on an address match. Through the mode
select bits, the user can also choose to interrupt on
START and STOP bits
1. Receive first (high) byte of address (bits SSPIF,
BF and bit UA (SSPSTAT<1>) are set).
2. Update the SSPADD register with second (low)
byte of address (clears bit UA and releases the
SCL line).
3. Read the SSPBUF register (clears bit BF) and
clear flag bit SSPIF.
When an address is matched or the data transfer after
an address match is received, the hardware automati-
cally will generate the Acknowledge (ACK) pulse and
load the SSPBUF register with the received value
currently in the SSPSR register.
4. Receive second (low) byte of address (bits
SSPIF, BF, and UA are set).
5. Update the SSPADD register with the first (high)
byte of address. If match releases SCL line, this
will clear bit UA.
Any combination of the following conditions will cause
the MSSP module not to give this ACK pulse:
6. Read the SSPBUF register (clears bit BF) and
clear flag bit SSPIF.
• The buffer full bit BF (SSPSTAT<0>) was set
before the transfer was received.
7. Receive Repeated START condition.
8. Receive first (high) byte of address (bits SSPIF
and BF are set).
• The overflow bit SSPOV (SSPCON<6>) was set
before the transfer was received.
9. Read the SSPBUF register (clears bit BF) and
clear flag bit SSPIF.
In this case, the SSPSR register value is not loaded
into the SSPBUF, but bit SSPIF (PIR1<3>) is set. The
BF bit is cleared by reading the SSPBUF register, while
bit SSPOV is cleared through software.
The SCL clock input must have a minimum high and
low for proper operation. The high and low times of the
I2C specification, as well as the requirement of the
MSSP module, are shown in timing parameter #100
and parameter #101.
DS39612A-page 188
Advance Information
2003 Microchip Technology Inc.
PIC18F6X2X/8X2X
18.4.3.2
Reception
18.4.3.3
Transmission
When the R/W bit of the address byte is clear and an
address match occurs, the R/W bit of the SSPSTAT
register is cleared. The received address is loaded into
the SSPBUF register and the SDA line is held low
(ACK).
When the R/W bit of the incoming address byte is set
and an address match occurs, the R/W bit of the
SSPSTAT register is set. The received address is
loaded into the SSPBUF register. The ACK pulse will
be sent on the ninth bit and pin RC3/SCK/SCL is held
low regardless of SEN (see Section 18.4.4, “Clock
Stretching” for more detail). By stretching the clock, the
master will be unable to assert another clock pulse until
the slave is done preparing the transmit data. The
transmit data must be loaded into the SSPBUF register
which also loads the SSPSR register. Then pin RC3/
SCK/SCL should be enabled by setting bit CKP
(SSPCON1<4>). The eight data bits are shifted out on
the falling edge of the SCL input. This ensures that the
SDA signal is valid during the SCL high time
(Figure 18-9).
When the address byte overflow condition exists, then
the no Acknowledge (ACK) pulse is given. An overflow
condition is defined as either bit BF (SSPSTAT<0>) is
set, or bit SSPOV (SSPCON1<6>) is set.
An MSSP interrupt is generated for each data transfer
byte. Flag bit SSPIF (PIR1<3>) must be cleared in soft-
ware. The SSPSTAT register is used to determine the
status of the byte.
If SEN is enabled (SSPCON1<0> = 1), RC3/SCK/SCL
will be held low (clock stretch) following each data
transfer. The clock must be released by setting bit CKP
(SSPCON<4>). See Section 18.4.4, “Clock Stretching”
for more detail.
The ACK pulse from the master-receiver is latched on
the rising edge of the ninth SCL input pulse. If the SDA
line is high (not ACK), then the data transfer is com-
plete. In this case, when the ACK is latched by the
slave, the slave logic is reset (resets SSPSTAT regis-
ter) and the slave monitors for another occurrence of
the START bit. If the SDA line was low (ACK), the next
transmit data must be loaded into the SSPBUF register.
Again, pin RC3/SCK/SCL must be enabled by setting
bit CKP.
An MSSP interrupt is generated for each data transfer
byte. The SSPIF bit must be cleared in software and
the SSPSTAT register is used to determine the status
of the byte. The SSPIF bit is set on the falling edge of
the ninth clock pulse.
2003 Microchip Technology Inc.
Advance Information
DS39612A-page 189
PIC18F6X2X/8X2X
2
FIGURE 18-8:
I C SLAVE MODE TIMING WITH SEN = 0 (RECEPTION, 7-BIT ADDRESS)
DS39612A-page 190
Advance Information
2003 Microchip Technology Inc.
PIC18F6X2X/8X2X
2
FIGURE 18-9:
I C SLAVE MODE TIMING (TRANSMISSION, 7-BIT ADDRESS)
2003 Microchip Technology Inc.
Advance Information
DS39612A-page 191
PIC18F6X2X/8X2X
FIGURE 18-10:
I2C SLAVE MODE TIMING WITH SEN = 0 (RECEPTION, 10-BIT ADDRESS)
DS39612A-page 192
Advance Information
2003 Microchip Technology Inc.
PIC18F6X2X/8X2X
2
FIGURE 18-11:
I C SLAVE MODE TIMING (TRANSMISSION, 10-BIT ADDRESS)
2003 Microchip Technology Inc.
Advance Information
DS39612A-page 193
PIC18F6X2X/8X2X
18.4.4
CLOCK STRETCHING
18.4.4.3
Clock Stretching for 7-bit Slave
Transmit Mode
Both 7 and 10-bit Slave modes implement automatic
clock stretching during a transmit sequence.
7-bit Slave Transmit mode implements clock stretching
by clearing the CKP bit after the falling edge of the
ninth clock if the BF bit is clear. This occurs regardless
of the state of the SEN bit.
The SEN bit (SSPCON2<0>) allows clock stretching to
be enabled during receives. Setting SEN will cause
the SCL pin to be held low at the end of each data
receive sequence.
The user’s ISR must set the CKP bit before transmis-
sion is allowed to continue. By holding the SCL line
low, the user has time to service the ISR and load the
contents of the SSPBUF before the master device can
initiate another transmit sequence (see Figure 18-9).
18.4.4.1
Clock Stretching for 7-bit Slave
Receive Mode (SEN = 1)
In 7-bit Slave Receive mode, on the falling edge of the
ninth clock at the end of the ACK sequence if the BF
bit is set, the CKP bit in the SSPCON1 register is
automatically cleared, forcing the SCL output to be
held low. The CKP being cleared to ‘0’ will assert the
SCL line low. The CKP bit must be set in the user’s
ISR before reception is allowed to continue. By holding
the SCL line low, the user has time to service the ISR
and read the contents of the SSPBUF before the
master device can initiate another receive sequence.
This will prevent buffer overruns from occurring (see
Figure 18-13).
Note 1: If the user loads the contents of SSPBUF,
setting the BF bit before the falling edge of
the ninth clock, the CKP bit will not be
cleared and clock stretching will not occur.
2: The CKP bit can be set in software
regardless of the state of the BF bit.
18.4.4.4
Clock Stretching for 10-bit Slave
Transmit Mode
In 10-bit Slave Transmit mode, clock stretching is con-
trolled during the first two address sequences by the
state of the UA bit, just as it is in 10-bit Slave Receive
mode. The first two addresses are followed by a third
address sequence which contains the high order bits
of the 10-bit address and the R/W bit set to ‘1’. After
the third address sequence is performed, the UA bit is
not set, the module is now configured in Transmit
mode, and clock stretching is controlled by the BF flag
as in 7-bit Slave Transmit mode (see Figure 18-11).
Note 1: If the user reads the contents of the
SSPBUF before the falling edge of the
ninth clock, thus clearing the BF bit, the
CKP bit will not be cleared and clock
stretching will not occur.
2: The CKP bit can be set in software
regardless of the state of the BF bit. The
user should be careful to clear the BF bit
in the ISR before the next receive
sequence in order to prevent an overflow
condition.
18.4.4.2
Clock Stretching for 10-bit Slave
Receive Mode (SEN = 1)
In 10-bit Slave Receive mode during the address
sequence, clock stretching automatically takes place
but CKP is not cleared. During this time, if the UA bit is
set after the ninth clock, clock stretching is initiated.
The UA bit is set after receiving the upper byte of the
10-bit address, and following the receive of the second
byte of the 10-bit address with the R/W bit cleared to
‘0’. The release of the clock line occurs upon updating
SSPADD. Clock stretching will occur on each data
receive sequence as described in 7-bit mode.
Note:
If the user polls the UA bit and clears it by
updating the SSPADD register before the
falling edge of the ninth clock occurs, and
if the user hasn’t cleared the BF bit by
reading the SSPBUF register before that
time, then the CKP bit will still NOT be
asserted low. Clock stretching on the basis
of the state of the BF bit only occurs during
a
data sequence, not an address
sequence.
DS39612A-page 194
Advance Information
2003 Microchip Technology Inc.
PIC18F6X2X/8X2X
already asserted the SCL line. The SCL output will
remain low until the CKP bit is set, and all other
devices on the I2C bus have deasserted SCL. This
ensures that a write to the CKP bit will not violate the
minimum high time requirement for SCL (see
Figure 18-12).
18.4.4.5
Clock Synchronization and
the CKP bit
When the CKP bit is cleared, the SCL output is forced
to ‘0’. However, setting the CKP bit will not assert the
SCL output low until the SCL output is already sam-
pled low. Therefore, the CKP bit will not assert the
SCL line until an external I2C master device has
FIGURE 18-12:
CLOCK SYNCHRONIZATION TIMING
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
SDA
SCL
DX
DX-1
Master device
asserts clock
CKP
Master device
deasserts clock
WR
SSPCON
2003 Microchip Technology Inc.
Advance Information
DS39612A-page 195
PIC18F6X2X/8X2X
2
FIGURE 18-13:
I C SLAVE MODE TIMING WITH SEN = 1 (RECEPTION, 7-BIT ADDRESS)
DS39612A-page 196
Advance Information
2003 Microchip Technology Inc.
PIC18F6X2X/8X2X
FIGURE 18-14:
I2C SLAVE MODE TIMING SEN = 1 (RECEPTION, 10-BIT ADDRESS)
2003 Microchip Technology Inc.
Advance Information
DS39612A-page 197
PIC18F6X2X/8X2X
If the general call address matches, the SSPSR is
transferred to the SSPBUF, the BF flag bit is set (eighth
bit), and on the falling edge of the ninth bit (ACK bit),
the SSPIF interrupt flag bit is set.
18.4.5
GENERAL CALL ADDRESS
SUPPORT
The addressing procedure for the I2C bus is such that
the first byte after the START condition usually deter-
mines which device will be the slave addressed by the
master. The exception is the general call address which
can address all devices. When this address is used, all
devices should, in theory, respond with an
Acknowledge.
When the interrupt is serviced, the source for the inter-
rupt can be checked by reading the contents of the
SSPBUF. The value can be used to determine if the
address was device specific or a general call address.
In 10-bit mode, the SSPADD is required to be updated
for the second half of the address to match, and the UA
bit is set (SSPSTAT<1>). If the general call address is
sampled when the GCEN bit is set, while the slave is
configured in 10-bit Address mode, then the second
half of the address is not necessary, the UA bit will not
be set, and the slave will begin receiving data after the
Acknowledge (Figure 18-15).
The general call address is one of eight addresses
reserved for specific purposes by the I2C protocol. It
consists of all ‘0’s with R/W = 0.
The general call address is recognized when the Gen-
eral Call Enable bit (GCEN) is enabled (SSPCON2<7>
set). Following a START bit detect, 8 bits are shifted
into the SSPSR and the address is compared against
the SSPADD. It is also compared to the general call
address and fixed in hardware.
FIGURE 18-15:
SLAVE MODE GENERAL CALL ADDRESS SEQUENCE
(7 OR 10-BIT ADDRESS MODE)
Address is compared to General Call Address
after ACK, set interrupt
Receiving Data
D5 D4 D3 D2 D1
ACK
R/W = 0
General Call Address
ACK
SDA
SCL
D7 D6
D0
8
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
9
S
SSPIF
BF (SSPSTAT<0>)
Cleared in software
SSPBUF is read
SSPOV (SSPCON1<6>)
GCEN (SSPCON2<7>)
‘0’
‘1’
DS39612A-page 198
Advance Information
2003 Microchip Technology Inc.
PIC18F6X2X/8X2X
18.4.6
MASTER MODE
Note:
The MSSP module, when configured in
I2C Master mode, does not allow queueing
of events. For instance, the user is not
allowed to initiate a START condition and
immediately write the SSPBUF register to
initiate transmission before the START
condition is complete. In this case, the
SSPBUF will not be written to and the
WCOL bit will be set, indicating that a write
to the SSPBUF did not occur.
Master mode is enabled by setting and clearing the
appropriate SSPM bits in SSPCON1 and by setting the
SSPEN bit. In Master mode, the SCL and SDA lines
are manipulated by the MSSP hardware.
Master mode of operation is supported by interrupt
generation on the detection of the START and STOP
conditions. The STOP (P) and START (S) bits are
cleared from a RESET or when the MSSP module is
disabled. Control of the I2C bus may be taken when the
P bit is set or the bus is IDLE, with both the S and P bits
clear.
The following events will cause SSP interrupt flag bit,
SSPIF, to be set (SSP interrupt, if enabled):
• START condition
In Firmware Controlled Master mode, user code con-
ducts all I2C bus operations based on START and
STOP bit conditions.
• STOP condition
• Data transfer byte transmitted/received
• Acknowledge transmit
• Repeated START
Once Master mode is enabled, the user has six
options.
1. Assert a START condition on SDA and SCL.
2. Assert a Repeated START condition on SDA
and SCL.
3. Write to the SSPBUF register initiating
transmission of data/address.
4. Configure the I2C port to receive data.
5. Generate an Acknowledge condition at the end
of a received byte of data.
6. Generate a STOP condition on SDA and SCL.
2
FIGURE 18-16:
MSSP BLOCK DIAGRAM (I C MASTER MODE)
Internal
Data Bus
SSPM3:SSPM0
SSPADD<6:0>
Read
Write
SSPBUF
SSPSR
Baud
Rate
Generator
SDA
Shift
Clock
SDA In
MSb
LSb
START bit, STOP bit,
Acknowledge
Generate
SCL
START bit Detect
STOP bit Detect
Write Collision Detect
Clock Arbitration
State Counter for
end of XMIT/RCV
SCL In
Bus Collision
Set/Reset, S, P, WCOL (SSPSTAT)
Set SSPIF, BCLIF
Reset ACKSTAT, PEN (SSPCON2)
2003 Microchip Technology Inc.
Advance Information
DS39612A-page 199
PIC18F6X2X/8X2X
I2C Master Mode Operation
A typical transmit sequence would go as follows:
1. The user generates a START condition by set-
18.4.6.1
The master device generates all of the serial clock
pulses and the START and STOP conditions. A trans-
fer is ended with a STOP condition or with a Repeated
START condition. Since the Repeated START condi-
tion is also the beginning of the next serial transfer, the
I2C bus will not be released.
ting
the
START
enable
bit,
SEN
(SSPCON2<0>).
2. SSPIF is set. The MSSP module will wait the
required start time before any other operation
takes place.
3. The user loads the SSPBUF with the slave
address to transmit.
In Master Transmitter mode, serial data is output
through SDA, while SCL outputs the serial clock. The
first byte transmitted contains the slave address of the
receiving device (7 bits) and the Read/Write (R/W) bit.
In this case, the R/W bit will be logic ‘0’. Serial data is
transmitted 8 bits at a time. After each byte is transmit-
ted, an Acknowledge bit is received. START and STOP
conditions are output to indicate the beginning and the
end of a serial transfer.
4. Address is shifted out the SDA pin until all 8 bits
are transmitted.
5. The MSSP Module shifts in the ACK bit from the
slave device and writes its value into the
SSPCON2 register (SSPCON2<6>).
6. The MSSP module generates an interrupt at the
end of the ninth clock cycle by setting the SSPIF
bit.
In Master Receive mode, the first byte transmitted con-
tains the slave address of the transmitting device
(7 bits) and the R/W bit. In this case, the R/W bit will be
logic ‘1'’ Thus, the first byte transmitted is a 7-bit slave
address followed by a ‘1’ to indicate receive bit. Serial
data is received via SDA, while SCL outputs the serial
clock. Serial data is received 8 bits at a time. After each
byte is received, an Acknowledge bit is transmitted.
START and STOP conditions indicate the beginning
and end of transmission.
7. The user loads the SSPBUF with eight bits of
data.
8. Data is shifted out the SDA pin until all 8 bits are
transmitted.
9. The MSSP module shifts in the ACK bit from the
slave device and writes its value into the
SSPCON2 register (SSPCON2<6>).
10. The MSSP module generates an interrupt at the
end of the ninth clock cycle by setting the SSPIF
bit.
The baud rate generator used for the SPI mode opera-
tion is used to set the SCL clock frequency for either
100 kHz, 400 kHz or 1 MHz I2C operation. See
Section 18.4.7, “Baud Rate Generator” for more detail.
11. The user generates a STOP condition by setting
the STOP enable bit, PEN (SSPCON2<2>).
12. Interrupt is generated once the STOP condition
is complete.
DS39612A-page 200
Advance Information
2003 Microchip Technology Inc.
PIC18F6X2X/8X2X
Once the given operation is complete (i.e., transmis-
sion of the last data bit is followed by ACK), the internal
clock will automatically stop counting and the SCL pin
will remain in its last state.
18.4.7
BAUD RATE GENERATOR
In I2C Master mode, the baud rate generator (BRG)
reload value is placed in the lower 7 bits of the
SSPADD register (Figure 18-17). When a write occurs
to SSPBUF, the baud rate generator will automatically
begin counting. The BRG counts down to ‘0’ and stops
until another reload has taken place. The BRG count is
decremented twice per instruction cycle (TCY) on the
Q2 and Q4 clocks. In I2C Master mode, the BRG is
reloaded automatically.
Table 18-3 demonstrates clock rates based on
instruction cycles and the BRG value loaded into
SSPADD.
FIGURE 18-17:
BAUD RATE GENERATOR BLOCK DIAGRAM
SSPM3:SSPM0
SSPADD<6:0>
SSPM3:SSPM0
SCL
Reload
Control
Reload
BRG Down Counter
CLKO
FOSC/4
TABLE 18-3: I2C CLOCK RATE W/BRG
FSCL
FCY
FCY*2
BRG Value
(2 Rollovers of BRG)
10 MHz
10 MHz
10 MHz
4 MHz
4 MHz
4 MHz
1 MHz
1 MHz
1 MHz
20 MHz
20 MHz
20 MHz
8 MHz
8 MHz
8 MHz
2 MHz
2 MHz
2 MHz
19h
20h
3Fh
0Ah
0Dh
28h
03h
0Ah
00h
400 kHz(1)
312.5 kHz
100 kHz
400 kHz(1)
308 kHz
100 kHz
333 kHz(1)
100 kHz
1 MHz(1)
Note 1: The I2C interface does not conform to the 400 kHz I2C specification (which applies to rates greater than
100 kHz) in all details, but may be used with care where higher rates are required by the application.
2003 Microchip Technology Inc.
Advance Information
DS39612A-page 201
PIC18F6X2X/8X2X
SCL pin is sampled high, the baud rate generator is
reloaded with the contents of SSPADD<6:0> and
begins counting. This ensures that the SCL high time
will always be at least one BRG rollover count in the
event that the clock is held low by an external device
(Figure 18-18).
18.4.7.1
Clock Arbitration
Clock arbitration occurs when the master, during any
receive, transmit or Repeated START/STOP condition,
deasserts the SCL pin (SCL allowed to float high).
When the SCL pin is allowed to float high, the Baud
Rate Generator (BRG) is suspended from counting
until the SCL pin is actually sampled high. When the
FIGURE 18-18:
BAUD RATE GENERATOR TIMING WITH CLOCK ARBITRATION
SDA
DX
DX-1
SCL allowed to transition high
SCL deasserted but slave holds
SCL low (clock arbitration)
SCL
BRG decrements on
Q2 and Q4 cycles
BRG
Value
03h
02h
01h
00h (hold off)
03h
02h
SCL is sampled high, reload takes
place and BRG starts its count
BRG
Reload
DS39612A-page 202
Advance Information
2003 Microchip Technology Inc.
PIC18F6X2X/8X2X
18.4.8
I2C MASTER MODE START
CONDITION TIMING
Note:
If at the beginning of the START condition,
the SDA and SCL pins are already sam-
pled low, or if during the START condition,
the SCL line is sampled low before the
SDA line is driven low, a bus collision
occurs, the Bus Collision Interrupt Flag,
BCLIF, is set, the START condition is
aborted, and the I2C module is reset into
its IDLE state.
To initiate a START condition, the user sets the START
condition enable bit, SEN (SSPCON2<0>). If the SDA
and SCL pins are sampled high, the baud rate genera-
tor is reloaded with the contents of SSPADD<6:0> and
starts its count. If SCL and SDA are both sampled high
when the baud rate generator times out (TBRG), the
SDA pin is driven low. The action of the SDA being
driven low while SCL is high is the START condition
and causes the S bit (SSPSTAT<3>) to be set. Follow-
ing this, the baud rate generator is reloaded with the
contents of SSPADD<6:0> and resumes its count.
When the baud rate generator times out (TBRG), the
SEN bit (SSPCON2<0>) will be automatically cleared
by hardware, the baud rate generator is suspended,
leaving the SDA line held low and the START condition
is complete.
18.4.8.1
WCOL Status Flag
If the user writes the SSPBUF when a START
sequence is in progress, the WCOL is set and the con-
tents of the buffer are unchanged (the write doesn’t
occur).
Note:
Because queueing of events is not
allowed, writing to the lower 5 bits of
SSPCON2 is disabled until the START
condition is complete.
FIGURE 18-19:
FIRST START BIT TIMING
Set S bit (SSPSTAT<3>)
At completion of START bit,
Write to SEN bit occurs here
SDA = 1,
SCL = 1
hardware clears SEN bit
and sets SSPIF bit
TBRG
TBRG
Write to SSPBUF occurs here
2nd bit
1st bit
SDA
TBRG
SCL
TBRG
S
2003 Microchip Technology Inc.
Advance Information
DS39612A-page 203
PIC18F6X2X/8X2X
18.4.9
I2C MASTER MODE REPEATED
START CONDITION TIMING
Note 1: If RSEN is programmed while any other
event is in progress, it will not take effect.
A Repeated START condition occurs when the RSEN
bit (SSPCON2<1>) is programmed high and the I2C
logic module is in the IDLE state. When the RSEN bit is
set, the SCL pin is asserted low. When the SCL pin is
sampled low, the baud rate generator is loaded with the
contents of SSPADD<5:0> and begins counting. The
SDA pin is released (brought high) for one baud rate
generator count (TBRG). When the baud rate generator
times out, if SDA is sampled high, the SCL pin will be
deasserted (brought high). When SCL is sampled high,
the baud rate generator is reloaded with the contents of
SSPADD<6:0> and begins counting. SDA and SCL
must be sampled high for one TBRG. This action is then
followed by assertion of the SDA pin (SDA = 0) for one
TBRG while SCL is high. Following this, the RSEN bit
(SSPCON2<1>) will be automatically cleared and the
baud rate generator will not be reloaded, leaving the
SDA pin held low. As soon as a START condition is
detected on the SDA and SCL pins, the S bit
(SSPSTAT<3>) will be set. The SSPIF bit will not be set
until the baud rate generator has timed out.
2: A bus collision during the Repeated
START condition occurs if:
• SDA is sampled low when SCL goes
from low to high.
• SCL goes low before SDA is
asserted low. This may indicate that
another master is attempting to
transmit a data ‘1’.
Immediately following the SSPIF bit getting set, the user
may write the SSPBUF with the 7-bit address in 7-bit
mode, or the default first address in 10-bit mode. After
the first eight bits are transmitted and an ACK is
received, the user may then transmit an additional eight
bits of address (10-bit mode) or eight bits of data (7-bit
mode).
18.4.9.1
WCOL Status Flag
If the user writes the SSPBUF when a Repeated
START sequence is in progress, the WCOL is set and
the contents of the buffer are unchanged (the write
doesn’t occur).
Note:
Because queueing of events is not
allowed, writing of the lower 5 bits of
SSPCON2 is disabled until the Repeated
START condition is complete.
FIGURE 18-20:
REPEAT START CONDITION WAVEFORM
Set S (SSPSTAT<3>)
Write to SSPCON2
occurs here.
SDA = 1,
SCL (no change).
SDA = 1,
SCL = 1
At completion of START bit,
hardware clears RSEN bit
and sets SSPIF
TBRG
TBRG
TBRG
1st bit
SDA
Write to SSPBUF occurs here
TBRG
Falling edge of ninth clock,
end of Xmit
SCL
TBRG
Sr = Repeated START
DS39612A-page 204
Advance Information
2003 Microchip Technology Inc.
PIC18F6X2X/8X2X
18.4.10 I2C MASTER MODE
TRANSMISSION
18.4.10.3 ACKSTAT Status Flag
In Transmit mode, the ACKSTAT bit (SSPCON2<6>) is
cleared when the slave has sent an Acknowledge
(ACK = 0), and is set when the slave does not
Acknowledge (ACK = 1). A slave sends an Acknowl-
edge when it has recognized its address (including a
general call), or when the slave has properly received
its data.
Transmission of a data byte, a 7-bit address, or the
other half of a 10-bit address is accomplished by simply
writing a value to the SSPBUF register. This action will
set the buffer full flag bit, BF, and allow the baud rate
generator to begin counting and start the next transmis-
sion. Each bit of address/data will be shifted out onto
the SDA pin after the falling edge of SCL is asserted
(see data hold time specification parameter #106). SCL
is held low for one baud rate generator rollover count
(TBRG). Data should be valid before SCL is released
high (see data setup time specification parameter
#107). When the SCL pin is released high, it is held that
way for TBRG. The data on the SDA pin must remain
stable for that duration and some hold time after the
next falling edge of SCL. After the eighth bit is shifted
out (the falling edge of the eighth clock), the BF flag is
cleared and the master releases SDA. This allows the
slave device being addressed to respond with an ACK
bit during the ninth bit time if an address match
occurred, or if data was received properly. The status
of ACK is written into the ACKDT bit on the falling edge
of the ninth clock. If the master receives an Acknowl-
edge, the Acknowledge status bit, ACKSTAT, is
cleared. If not, the bit is set. After the ninth clock, the
SSPIF bit is set and the master clock (baud rate gener-
ator) is suspended until the next data byte is loaded into
the SSPBUF, leaving SCL low and SDA unchanged
(Figure 18-21).
18.4.11 I2C MASTER MODE RECEPTION
Master mode reception is enabled by programming the
receive enable bit, RCEN (SSPCON2<3>).
Note:
The MSSP module must be in an IDLE
state before the RCEN bit is set or the
RCEN bit will be disregarded.
The baud rate generator begins counting, and on each
rollover, the state of the SCL pin changes (high to low/
low to high) and data is shifted into the SSPSR. After
the falling edge of the eighth clock, the receive enable
flag is automatically cleared, the contents of the
SSPSR are loaded into the SSPBUF, the BF flag bit is
set, the SSPIF flag bit is set and the baud rate genera-
tor is suspended from counting, holding SCL low. The
MSSP is now in IDLE state awaiting the next com-
mand. When the buffer is read by the CPU, the BF flag
bit is automatically cleared. The user can then send an
Acknowledge bit at the end of reception by setting the
Acknowledge sequence enable bit, ACKEN
(SSPCON2<4>).
After the write to the SSPBUF, each bit of address will
be shifted out on the falling edge of SCL until all seven
address bits and the R/W bit are completed. On the fall-
ing edge of the eighth clock, the master will deassert
the SDA pin, allowing the slave to respond with an
Acknowledge. On the falling edge of the ninth clock, the
master will sample the SDA pin to see if the address
was recognized by a slave. The status of the ACK bit is
loaded into the ACKSTAT status bit (SSPCON2<6>).
Following the falling edge of the ninth clock transmis-
sion of the address, the SSPIF is set, the BF flag is
cleared and the baud rate generator is turned off until
another write to the SSPBUF takes place, holding SCL
low and allowing SDA to float.
18.4.11.1 BF Status Flag
In receive operation, the BF bit is set when an address
or data byte is loaded into SSPBUF from SSPSR. It is
cleared when the SSPBUF register is read.
18.4.11.2 SSPOV Status Flag
In receive operation, the SSPOV bit is set when 8 bits
are received into the SSPSR and the BF flag bit is
already set from a previous reception.
18.4.11.3 WCOL Status Flag
If the user writes the SSPBUF when a receive is
already in progress (i.e., SSPSR is still shifting in a data
byte), the WCOL bit is set and the contents of the buffer
are unchanged (the write doesn’t occur).
18.4.10.1 BF Status Flag
In Transmit mode, the BF bit (SSPSTAT<0>) is set
when the CPU writes to SSPBUF and is cleared when
all 8 bits are shifted out.
18.4.10.2 WCOL Status Flag
If the user writes the SSPBUF when a transmit is
already in progress (i.e., SSPSR is still shifting out a
data byte), the WCOL is set and the contents of the
buffer are unchanged (the write doesn’t occur).
WCOL must be cleared in software.
2003 Microchip Technology Inc.
Advance Information
DS39612A-page 205
PIC18F6X2X/8X2X
2
FIGURE 18-21:
I C MASTER MODE WAVEFORM (TRANSMISSION, 7 OR 10-BIT ADDRESS)
DS39612A-page 206
Advance Information
2003 Microchip Technology Inc.
PIC18F6X2X/8X2X
2
FIGURE 18-22:
I C MASTER MODE WAVEFORM (RECEPTION, 7-BIT ADDRESS)
2003 Microchip Technology Inc.
Advance Information
DS39612A-page 207
PIC18F6X2X/8X2X
18.4.12 ACKNOWLEDGE SEQUENCE
TIMING
18.4.13 STOP CONDITION TIMING
A STOP bit is asserted on the SDA pin at the end of a
receive/transmit by setting the STOP sequence enable
bit, PEN (SSPCON2<2>). At the end of a receive/
transmit, the SCL line is held low after the falling edge
of the ninth clock. When the PEN bit is set, the master
will assert the SDA line low. When the SDA line is sam-
pled low, the baud rate generator is reloaded and
counts down to ‘0’. When the baud rate generator times
out, the SCL pin will be brought high, and one TBRG
(baud rate generator rollover count) later, the SDA pin
will be deasserted. When the SDA pin is sampled high
while SCL is high, the P bit (SSPSTAT<4>) is set. A
TBRG later, the PEN bit is cleared and the SSPIF bit is
set (Figure 18-24).
An Acknowledge sequence is enabled by setting the
Acknowledge
sequence
enable
bit,
ACKEN
(SSPCON2<4>). When this bit is set, the SCL pin is
pulled low and the contents of the Acknowledge data bit
are presented on the SDA pin. If the user wishes to gen-
erate an Acknowledge, then the ACKDT bit should be
cleared. If not, the user should set the ACKDT bit before
starting an Acknowledge sequence. The baud rate gen-
erator then counts for one rollover period (TBRG) and the
SCL pin is deasserted (pulled high). When the SCL pin
is sampled high (clock arbitration), the baud rate gener-
ator counts for TBRG. The SCL pin is then pulled low. Fol-
lowing this, the ACKEN bit is automatically cleared, the
baud rate generator is turned off and the MSSP module
then goes into IDLE mode (Figure 18-23).
18.4.13.1 WCOL Status Flag
If the user writes the SSPBUF when a STOP sequence
is in progress, then the WCOL bit is set and the con-
tents of the buffer are unchanged (the write doesn’t
occur).
18.4.12.1 WCOL Status Flag
If the user writes the SSPBUF when an Acknowledge
sequence is in progress, then WCOL is set and the
contents of the buffer are unchanged (the write doesn’t
occur).
FIGURE 18-23:
ACKNOWLEDGE SEQUENCE WAVEFORM
Acknowledge sequence starts here,
write to SSPCON2
ACKEN automatically cleared
ACKEN = 1, ACKDT = 0
TBRG
ACK
TBRG
SDA
SCL
D0
8
9
SSPIF
Cleared in
Set SSPIF at the end
of receive
software
Cleared in
software
Set SSPIF at the end
of Acknowledge sequence
Note: TBRG = one baud rate generator period.
FIGURE 18-24:
STOP CONDITION RECEIVE OR TRANSMIT MODE
SCL = 1for TBRG, followed by SDA = 1for TBRG
after SDA sampled high. P bit (SSPSTAT<4>) is set.
Write to SSPCON2,
set PEN
PEN bit (SSPCON2<2>) is cleared by
hardware and the SSPIF bit is set
Falling edge of
9th clock
TBRG
SCL
SDA
ACK
P
TBRG
TBRG
TBRG
SCL brought high after TBRG
SDA asserted low before rising edge of clock
to setup STOP condition
Note: TBRG = one baud rate generator period.
DS39612A-page 208
Advance Information
2003 Microchip Technology Inc.
PIC18F6X2X/8X2X
18.4.14 SLEEP OPERATION
18.4.17 MULTI -MASTER COMMUNICATION,
BUS COLLISION, AND BUS
ARBITRATION
While in SLEEP mode, the I2C module can receive
addresses or data and when an address match or com-
plete byte transfer occurs, wake the processor from
SLEEP (if the MSSP interrupt is enabled).
Multi-Master mode support is achieved by bus arbitra-
tion. When the master outputs address/data bits onto
the SDA pin, arbitration takes place when the master
outputs a ‘1’ on SDA, by letting SDA float high and
another master asserts a ‘0’. When the SCL pin floats
high, data should be stable. If the expected data on
SDA is a ‘1’ and the data sampled on the SDA pin = 0,
then a bus collision has taken place. The master will set
the Bus Collision Interrupt Flag, BCLIF and reset the
I2C port to its IDLE state (Figure 18-25).
18.4.15 EFFECT OF A RESET
A RESET disables the MSSP module and terminates
the current transfer.
18.4.16 MULTI-MASTER MODE
In Multi-Master mode, the interrupt generation on the
detection of the START and STOP conditions allows
the determination of when the bus is free. The STOP
(P) and START (S) bits are cleared from a RESET or
when the MSSP module is disabled. Control of the I2C
bus may be taken when the P bit (SSPSTAT<4>) is set,
or the bus is IDLE with both the S and P bits clear.
When the bus is busy, enabling the SSP interrupt will
generate the interrupt when the STOP condition
occurs.
If a transmit was in progress when the bus collision
occurred, the transmission is halted, the BF flag is
cleared, the SDA and SCL lines are deasserted, and
the SSPBUF can be written to. When the user services
the bus collision Interrupt Service Routine, and if the
I2C bus is free, the user can resume communication by
asserting a START condition.
If a START, Repeated START, STOP, or Acknowledge
condition was in progress when the bus collision
occurred, the condition is aborted, the SDA and SCL
lines are deasserted, and the respective control bits in
the SSPCON2 register are cleared. When the user ser-
vices the bus collision Interrupt Service Routine, and if
the I2C bus is free, the user can resume communication
by asserting a START condition.
In multi-master operation, the SDA line must be
monitored for arbitration to see if the signal level is the
expected output level. This check is performed in
hardware with the result placed in the BCLIF bit.
The states where arbitration can be lost are:
• Address Transfer
• Data Transfer
The master will continue to monitor the SDA and SCL
pins. If a STOP condition occurs, the SSPIF bit will be set.
• A START Condition
• A Repeated START Condition
• An Acknowledge Condition
A write to the SSPBUF will start the transmission of
data at the first data bit regardless of where the
transmitter left off when the bus collision occurred.
In Multi-Master mode, the interrupt generation on the
detection of START and STOP conditions allows the
determination of when the bus is free. Control of the I2C
bus can be taken when the P bit is set in the SSPSTAT
register, or the bus is IDLE and the S and P bits are
cleared.
FIGURE 18-25:
BUS COLLISION TIMING FOR TRANSMIT AND ACKNOWLEDGE
Sample SDA. While SCL is high,
data doesn’t match what is driven
by the master.
Data changes
while SCL = 0
SDA line pulled low
by another source
Bus collision has occurred.
SDA released
by master
SDA
SCL
Set bus collision
interrupt (BCLIF)
BCLIF
2003 Microchip Technology Inc.
Advance Information
DS39612A-page 209
PIC18F6X2X/8X2X
If the SDA pin is sampled low during this count, the
BRG is reset and the SDA line is asserted early
(Figure 18-28). If, however, a ‘1’ is sampled on the SDA
pin, the SDA pin is asserted low at the end of the BRG
count. The baud rate generator is then reloaded and
counts down to ‘0’, and during this time, if the SCL pins
are sampled as ‘0’, a bus collision does not occur. At
the end of the BRG count, the SCLpin is asserted low.
18.4.17.1 Bus Collision During a START
Condition
During a START condition, a bus collision occurs if:
a) SDA or SCL are sampled low at the beginning of
the START condition (Figure 18-26).
b) SCL is sampled low before SDA is asserted low
(Figure 18-27).
During a START condition, both the SDA and the SCL
pins are monitored.
Note:
The reason that bus collision is not a factor
during a START condition is that no two bus
masters can assert a START condition at
the exact same time. Therefore, one mas-
ter will always assert SDA before the other.
This condition does not cause a bus colli-
sion because the two masters must be
allowed to arbitrate the first address follow-
ing the START condition. If the address is
the same, arbitration must be allowed to
continue into the data portion, Repeated
START or STOP conditions.
If the SDA pin is already low, or the SCL pin is already
low, then all of the following occur:
• the START condition is aborted,
• the BCLIF flag is set, and
•
the MSSP module is reset to its IDLE state
(Figure 18-26).
The START condition begins with the SDA and SCL
pins deasserted. When the SDA pin is sampled high,
the baud rate generator is loaded from SSPADD<6:0>
and counts down to ‘0’. If the SCL pin is sampled low
while SDA is high, a bus collision occurs because it is
assumed that another master is attempting to drive a
data ‘1’ during the START condition.
FIGURE 18-26:
BUS COLLISION DURING START CONDITION (SDA ONLY)
SDA goes low before the SEN bit is set.
Set BCLIF,
S bit and SSPIF set because
SDA = 0, SCL = 1.
SDA
SCL
SEN
Set SEN, enable START
condition if SDA = 1, SCL = 1
SEN cleared automatically because of bus collision.
SSP module reset into IDLE state.
SDA sampled low before
START condition. Set BCLIF.
S bit and SSPIF set because
SDA = 0, SCL = 1.
BCLIF
SSPIF and BCLIF are
cleared in software
S
SSPIF
SSPIF and BCLIF are
cleared in software
DS39612A-page 210
Advance Information
2003 Microchip Technology Inc.
PIC18F6X2X/8X2X
FIGURE 18-27:
BUS COLLISION DURING START CONDITION (SCL = 0)
SDA = 0, SCL = 1
TBRG
TBRG
SDA
Set SEN, enable START
sequence if SDA = 1, SCL = 1
SCL
SEN
SCL = 0before SDA = 0,
bus collision occurs. Set BCLIF.
SCL = 0before BRG time-out,
bus collision occurs. Set BCLIF.
BCLIF
Interrupt cleared
in software
S
‘0’
‘0’
‘0’
‘0’
SSPIF
FIGURE 18-28:
BRG RESET DUE TO SDA ARBITRATION DURING START CONDITION
SDA = 0, SCL = 1
Set S
Set SSPIF
Less than TBRG
TBRG
SDA pulled low by other master.
Reset BRG and assert SDA.
SDA
SCL
S
SCL pulled low after BRG
time-out
SEN
Set SEN, enable START
sequence if SDA = 1, SCL = 1
‘0’
BCLIF
S
SSPIF
Interrupts cleared
in software
SDA = 0, SCL = 1,
set SSPIF
2003 Microchip Technology Inc.
Advance Information
DS39612A-page 211
PIC18F6X2X/8X2X
If SDA is low, a bus collision has occurred (i.e., another
master is attempting to transmit a data ‘0’, Figure 18-29).
If SDA is sampled high, the BRG is reloaded and begins
counting. If SDA goes from high to low before the BRG
times out, no bus collision occurs because no two
masters can assert SDA at exactly the same time.
18.4.17.2 Bus Collision During a Repeated
START Condition
During a Repeated START condition, a bus collision
occurs if:
a) A low level is sampled on SDA when SCL goes
from low level to high level.
If SCL goes from high to low before the BRG times out
and SDA has not already been asserted, a bus collision
occurs. In this case, another master is attempting to
transmit a data ‘1’ during the Repeated START
condition, see Figure 18-30.
b) SCL goes low before SDA is asserted low, indi-
cating that another master is attempting to
transmit a data ‘1’.
When the user deasserts SDA and the pin is allowed to
float high, the BRG is loaded with SSPADD<6:0> and
counts down to ‘0’. The SCL pin is then deasserted and
when sampled high, the SDA pin is sampled.
If, at the end of the BRG time-out, both SCL and SDA
are still high, the SDA pin is driven low and the BRG is
reloaded and begins counting. At the end of the count
regardless of the status of the SCL pin, the SCL pin is
driven low and the Repeated START condition is
complete.
FIGURE 18-29:
BUS COLLISION DURING A REPEATED START CONDITION (CASE 1)
SDA
SCL
Sample SDA when SCL goes high.
If SDA = 0, set BCLIF and release SDA and SCL.
RSEN
BCLIF
Cleared in software
‘0’
S
‘0’
SSPIF
FIGURE 18-30:
BUS COLLISION DURING REPEATED START CONDITION (CASE 2)
TBRG
TBRG
SDA
SCL
SCL goes low before SDA,
set BCLIF. Release SDA and SCL.
BCLIF
RSEN
Interrupt cleared
in software
‘0’
S
SSPIF
DS39612A-page 212
Advance Information
2003 Microchip Technology Inc.
PIC18F6X2X/8X2X
The STOP condition begins with SDA asserted low.
When SDA is sampled low, the SCL pin is allowed to
float. When the pin is sampled high (clock arbitration),
the baud rate generator is loaded with SSPADD<6:0>
and counts down to ‘0’. After the BRG times out, SDA
is sampled. If SDA is sampled low, a bus collision has
occurred. This is due to another master attempting to
drive a data ‘0’ (Figure 18-31). If the SCL pin is
sampled low before SDA is allowed to float high, a bus
collision occurs. This is another case of another master
attempting to drive a data ‘0’ (Figure 18-32).
18.4.17.3 Bus Collision During a STOP
Condition
Bus collision occurs during a STOP condition if:
a) After the SDA pin has been deasserted and
allowed to float high, SDA is sampled low after
the BRG has timed out.
b) After the SCL pin is deasserted, SCL is sampled
low before SDA goes high.
FIGURE 18-31:
BUS COLLISION DURING A STOP CONDITION (CASE 1)
SDA sampled
low after TBRG,
set BCLIF
TBRG
TBRG
TBRG
SDA
SDA asserted low
SCL
PEN
BCLIF
P
‘0’
‘0’
SSPIF
FIGURE 18-32:
BUS COLLISION DURING A STOP CONDITION (CASE 2)
TBRG
TBRG
TBRG
SDA
SCL goes low before SDA goes high,
set BCLIF
Assert SDA
SCL
PEN
BCLIF
P
‘0’
‘0’
SSPIF
2003 Microchip Technology Inc.
Advance Information
DS39612A-page 213
PIC18F6X2X/8X2X
NOTES:
DS39612A-page 214
Advance Information
2003 Microchip Technology Inc.
PIC18F6X2X/8X2X
The pins of USART1 and USART2 are multiplexed with
the functions of PORTC (RC6/TX1/CK1 and RC7RX1/
DT1) and PORTG (RG1/TX2/CK2 and RG2/RX2/DT2),
respectively. In order to configure these pins as a
USART:
19.0 ENHANCED UNIVERSAL
SYNCHRONOUS
ASYNCHRONOUS RECEIVER
TRANSMITTER (USART)
• For USART1:
The Universal Synchronous Asynchronous Receiver
Transmitter (USART) module is one of the two serial
I/O modules. (USART is also known as a Serial Com-
munications Interface or SCI.) The USART can be con-
figured as a full-duplex asynchronous system that can
communicate with peripheral devices, such as CRT ter-
minals and personal computers. It can also be config-
ured as a half-duplex synchronous system that can
communicate with peripheral devices, such as A/D or
D/A integrated circuits, serial EEPROMs, etc.
- bit SPEN (RCSTA1<7>) must be set (= 1)
- bit TRISC<7> must be set (= 1)
- bit TRISC<6> must be cleared (= 0) for
Asynchronous and Synchronous Master
modes
- bit TRISC<6> must be set (= 1) for
Synchronous Slave mode
• For USART2:
- bit SPEN (RCSTA2<7>) must be set (= 1)
- bit TRISG<2> must be set (= 1)
The Enhanced USART module implements additional
features, including automatic baud rate detection and
calibration, automatic wake-up on Sync Break recep-
tion and 12-bit Break character transmit. These make it
ideally suited for use in Local Interconnect Network bus
(LIN bus) systems.
- bit TRISG<1> must be cleared (= 0) for
Asynchronous and Synchronous Master
modes
- bit TRISC<6> must be set (= 1) for
Synchronous Slave mode
The USART can be configured in the following modes:
Note:
The USART control will automatically
reconfigure the pin from input to output as
needed.
• Asynchronous (full-duplex) with:
- Auto wake-up on character reception
- Auto baud calibration
The operation of each enhanced USART module is
controlled through three registers:
- 12-bit Break character transmission
• Synchronous - Master (half-duplex) with
selectable clock polarity
• Transmit Status and Control (TXSTAx)
• Receive Status and Control (RCSTAx)
• Baud Rate Control (BAUDCONx)
• Synchronous - Slave (half-duplex) with selectable
clock polarity
These are detailed on the following pages in
Register 19-1, Register 19-2 and Register 19-3,
respectively.
Note:
Throughout this section, references to
register and bit names that may be associ-
ated with a specific USART module are
referred to generically by the use of ‘x’ in
place of the specific module number.
Thus, “RCSTAx” might refer to the
Receive Status register for either USART1
or USART2
2003 Microchip Technology Inc.
Advance Information
DS39612A-page 215
PIC18F6X2X/8X2X
REGISTER 19-1: TXSTAx: TRANSMIT STATUS AND CONTROL REGISTER
R/W-0
CSRC
R/W-0
TX9
R/W-0
TXEN
R/W-0
SYNC
R/W-0
R/W-0
BRGH
R-1
R/W-0
TX9D
SENDB
TRMT
bit 7
bit 0
bit 7
CSRC: Clock Source Select bit
Asynchronous mode:
Don’t care.
Synchronous mode:
1= Master mode (clock generated internally from BRG)
0= Slave mode (clock from external source)
bit 6
bit 5
TX9: 9-bit Transmit Enable bit
1= Selects 9-bit transmission
0= Selects 8-bit transmission
TXEN: Transmit Enable bit
1= Transmit enabled
0= Transmit disabled
Note:
SREN/CREN overrides TXEN in Sync mode.
bit 4
bit 3
SYNC: USART Mode Select bit
1= Synchronous mode
0= Asynchronous mode
SENDB: Send Break Character bit
Asynchronous mode:
1= Send Sync Break on next transmission (cleared by hardware upon completion)
0= Sync Break transmission completed
Synchronous mode:
Don’t care.
bit 2
BRGH: High Baud Rate Select bit
Asynchronous mode:
1= High speed
0= Low speed
Synchronous mode:
Unused in this mode.
bit 1
bit 0
TRMT: Transmit Shift Register Status bit
1= TSR empty
0= TSR full
TX9D: 9th bit of Transmit Data
Can be address/data bit or a parity bit.
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
- n = Value at POR
DS39612A-page 216
Advance Information
2003 Microchip Technology Inc.
PIC18F6X2X/8X2X
REGISTER 19-2: RCSTAx: RECEIVE STATUS AND CONTROL REGISTER
R/W-0
SPEN
R/W-0
RX9
R/W-0
SREN
R/W-0
CREN
R/W-0
R-0
R-0
R-x
ADDEN
FERR
OERR
RX9D
bit 7
bit 0
bit 7
bit 6
bit 5
SPEN: Serial Port Enable bit
1= Serial port enabled (configures RX/DT and TX/CK pins as serial port pins)
0= Serial port disabled (held in RESET)
RX9: 9-bit Receive Enable bit
1= Selects 9-bit reception
0= Selects 8-bit reception
SREN: Single Receive Enable bit
Asynchronous mode:
Don’t care.
Synchronous mode - Master:
1= Enables single receive
0= Disables single receive
This bit is cleared after reception is complete.
Synchronous mode - Slave:
Don’t care.
bit 4
CREN: Continuous Receive Enable bit
Asynchronous mode:
1= Enables receiver
0= Disables receiver
Synchronous mode:
1= Enables continuous receive until enable bit CREN is cleared (CREN overrides SREN)
0= Disables continuous receive
bit 3
ADDEN: Address Detect Enable bit
Asynchronous mode 9-bit (RX9 = 1):
1= Enables address detection, enables interrupt and loads the receive buffer when RSR<8>
is set
0= Disables address detection, all bytes are received and ninth bit can be used as parity bit
Asynchronous mode 9-bit (RX9 = 0):
Don’t care.
bit 2
bit 1
bit 0
FERR: Framing Error bit
1= Framing error (can be updated by reading RCREGx register and receive next valid byte)
0= No framing error
OERR: Overrun Error bit
1= Overrun error (can be cleared by clearing bit CREN)
0= No overrun error
RX9D: 9th bit of Received Data
This can be address/data bit or a parity bit and must be calculated by user firmware.
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
- n = Value at POR
2003 Microchip Technology Inc.
Advance Information
DS39612A-page 217
PIC18F6X2X/8X2X
REGISTER 19-3: BAUDCONx: BAUD RATE CONTROL REGISTER
U-0
—
R-1
U-0
—
R/W-0
SCKP
R/W-0
U-0
—
R/W-0
WUE
R/W-0
RCIDL
BRG16
ABDEN
bit 7
bit 0
bit 7
bit 6
Unimplemented: Read as ‘0’
RCIDL: Receive Operation IDLE Status bit
1= Receive operation is IDLE
0= Receive operation is active
bit 5
bit 4
Unimplemented: Read as ‘0’
SCKP: Synchronous Clock Polarity Select bit
Asynchronous mode:
Unused in this mode.
Synchronous mode:
1= IDLE state for clock (CK) is a high level
0= IDLE state for clock (CK) is a low level
bit 3
BRG16: 16-bit Baud Rate Register Enable bit
1= 16-bit baud rate generator - SPBRGHx and SPBRGx
0= 8-bit baud rate generator - SPBRGx only (Compatible mode), SPBRGHx value ignored
bit 2
bit 1
Unimplemented: Read as ‘0’
WUE: Wake-up Enable bit
Asynchronous mode:
1= USART will continue to sample the RX pin - interrupt generated on falling edge; bit cleared
in hardware on following rising edge
0= RX pin not monitored or rising edge detected
Synchronous mode:
Unused in this mode.
bit 0
ABDEN: Auto Baud Detect Enable bit
Asynchronous mode:
1= Enable baud rate measurement on the next character - requires reception of a Sync field
(55h); cleared in hardware upon completion
0= Baud rate measurement disabled or completed
Synchronous mode:
Unused in this mode.
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
- n = Value at POR
DS39612A-page 218
Advance Information
2003 Microchip Technology Inc.
PIC18F6X2X/8X2X
this, the error in baud rate can be determined. An
example calculation is shown in Example 19-1. Typical
baud rates and error values for the various Asynchro-
nous modes are shown in Table 19-2. It may be advan-
tageous to use the high baud rate (BRGH = 1) or the
16-bit BRG to reduce the baud rate error, or achieve a
slow baud rate for a fast oscillator frequency.
19.1 USART Baud Rate Generator (BRG)
The BRG is a dedicated 8-bit or 16-bit generator that
supports both the Asynchronous and Synchronous
modes of the USART. By default, the BRG operates in
8-bit mode; setting the BRG16 bit (BAUDCONx<3>)
selects 16-bit mode.
The SPBRGHx:SPBRGx register pair controls the
period of a free running timer. In Asynchronous mode,
bits BRGH (TXSTAx<2>) and BRG16 also control the
baud rate. In Synchronous mode, bit BRGH is ignored.
Table 19-1 shows the formula for computation of the
baud rate for different USART modes which only apply
in Master mode (internally generated clock).
Writing a new value to the SPBRGHx:SPBRGx regis-
ters causes the BRG timer to be reset (or cleared). This
ensures the BRG does not wait for a timer overflow
before outputting the new baud rate.
19.1.1
SAMPLING
The data on the RXx pin (either RC7/RX1/DT1 or RG2/
RX2/DT2) is sampled three times by a majority detect
circuit to determine if a high or a low level is present at
the RX pin.
Given the desired baud rate and FOSC, the nearest
integer value for the SPBRGHx:SPBRGx registers can
be calculated using the formulas in Table 19-1. From
TABLE 19-1: BAUD RATE FORMULAS
Configuration Bits
BRG/USART Mode
Baud Rate Formula
SYNC
BRG16
BRGH
0
0
0
0
1
1
0
0
1
1
0
1
0
1
0
1
x
x
8-bit/Asynchronous
8-bit/Asynchronous
16-bit/Asynchronous
16-bit/Asynchronous
8-bit/Synchronous
16-bit/Synchronous
FOSC / [64 (n+1)]
FOSC / [16 (n+1)]
FOSC / [4 (n+1)]
Legend: x= Don’t care, n = value of SPBRGHx:SPBRGx register pair
EXAMPLE 19-1: CALCULATING BAUD RATE ERROR
For a device with FOSC of 16 MHz, desired baud rate of 9600, Asynchronous mode, 8-bit BRG:
Desired Baud Rate = FOSC / (64 ([SPBRGHx:SPBRGx] + 1))
Solving for SPBRGHx:SPBRGx:
X
= ((FOSC / Desired Baud Rate)/64) – 1
= ((16000000 / 9600) / 64) – 1
= [25.042] = 25
Calculated Baud Rate= 16000000 / (64 (25 + 1))
= 9615
Error
= (Calculated Baud Rate – Desired Baud Rate) / Desired Baud Rate
= (9615 – 9600) / 9600 = 0.16%
TABLE 19-2: REGISTERS ASSOCIATED WITH BAUD RATE GENERATOR
Value on
POR, BOR
Value on all
other RESETS
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
TXSTAx
CSRC
SPEN
—
TX9
RX9
TXEN
SREN
—
SYNC
CREN
SCKP
SENDB
ADDEN
BRG16
BRGH
FERR
—
TRMT
OERR
WUE
TX9D
RX9D
0000 -010
0000 -00x
-1-1 0-00
0000 0000
0000 0000
0000 -010
0000 -00x
-1-1 0-00
0000 0000
0000 0000
RCSTAx
BAUDCONx
RCIDL
ABDEN
SPBRGHx Baud Rate Generator Register, High Byte
SPBRGx
Legend:
Baud Rate Generator Register, Low Byte
x= unknown, - = unimplemented, read as ‘0’. Shaded cells are not used by the BRG.
2003 Microchip Technology Inc.
Advance Information
DS39612A-page 219
PIC18F6X2X/8X2X
TABLE 19-3: BAUD RATES FOR ASYNCHRONOUS MODES
SYNC = 0, BRGH = 0, BRG16 = 0
BAUD
RATE
(K)
FOSC = 40.000 MHz
FOSC = 20.000 MHz
FOSC = 10.000 MHz
FOSC = 8.000 MHz
Actual
Rate
(K)
SPBRG Actual
value
SPBRG Actual
value
(decimal)
SPBRG Actual
value
(decimal)
SPBRG
value
(decimal)
%
%
Error
%
Error
%
Error
Rate
(K)
Rate
(K)
Rate
(K)
Error
(decimal)
0.3
1.2
—
—
—
—
—
—
—
255
129
31
15
4
—
—
—
129
64
15
7
—
1201
2403
9615
—
—
-0.16
-0.16
-0.16
—
—
103
51
12
—
—
—
1.221
1.73
0.16
1.73
1.73
8.51
-9.58
1.202
2.404
9.766
19.531
52.083
78.125
0.16
0.16
1.73
1.73
-9.58
-32.18
2.4
2.441
9.615
19.531
56.818
125.000
1.73
0.16
1.73
-1.36
8.51
255
64
31
10
4
2.404
9.6
9.766
19.2
57.6
115.2
19.531
62.500
104.167
2
—
—
—
2
1
—
—
—
SYNC = 0, BRGH = 0, BRG16 = 0
BAUD
RATE
(K)
FOSC = 4.000 MHz
FOSC = 2.000 MHz
FOSC = 1.000 MHz
Actual
Rate
(K)
SPBRG Actual
value
SPBRG Actual
value
(decimal)
SPBRG
value
(decimal)
%
%
Error
%
Error
Rate
(K)
Rate
(K)
Error
(decimal)
0.3
1.2
0.300
1.202
0.16
0.16
207
51
25
6
300
1201
2403
—
-0.16
-0.16
-0.16
—
103
25
12
—
300
1201
—
-0.16
-0.16
—
51
12
—
—
—
—
—
2.4
2.404
0.16
9.6
8.929
-6.99
8.51
—
—
19.2
57.6
115.2
20.833
62.500
62.500
2
—
—
—
—
—
8.51
0
—
—
—
—
—
-45.75
0
—
—
—
—
—
SYNC = 0, BRGH = 1, BRG16 = 0
BAUD
RATE
(K)
FOSC = 40.000 MHz
FOSC = 20.000 MHz
FOSC = 10.000 MHz
FOSC = 8.000 MHz
Actual
Rate
(K)
SPBRG Actual
value
(decimal)
SPBRG Actual
value
(decimal)
SPBRG Actual
value
(decimal)
SPBRG
value
%
Error
%
Error
%
Error
%
Error
Rate
(K)
Rate
(K)
Rate
(K)
(decimal)
0.3
1.2
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
2.4
—
—
—
—
—
—
2.441
9.615
19.531
56.818
125.000
1.73
0.16
1.73
-1.36
8.51
255
64
31
10
4
2403
9615
19230
55555
—
-0.16
-0.16
-0.16
3.55
—
207
51
25
8
9.6
9.766
19.231
58.140
113.636
1.73
0.16
0.94
-1.36
255
129
42
9.615
19.231
56.818
113.636
0.16
0.16
-1.36
-1.36
129
64
21
10
19.2
57.6
115.2
21
—
SYNC = 0, BRGH = 1, BRG16 = 0
BAUD
RATE
(K)
FOSC = 4.000 MHz
FOSC = 2.000 MHz
FOSC = 1.000 MHz
Actual
Rate
(K)
SPBRG Actual
value
SPBRG Actual
value
(decimal)
SPBRG
value
(decimal)
%
%
Error
%
Error
Rate
(K)
Rate
(K)
Error
(decimal)
0.3
1.2
—
—
—
207
103
25
12
3
—
1201
2403
9615
—
—
-0.16
-0.16
-0.16
—
—
103
51
12
—
300
1201
2403
—
-0.16
-0.16
-0.16
—
207
51
25
—
1.202
0.16
0.16
0.16
0.16
8.51
8.51
2.4
2.404
9.6
9.615
19.2
57.6
115.2
19.231
62.500
125.000
—
—
—
—
—
—
—
—
—
1
—
—
—
—
—
—
DS39612A-page 220
Advance Information
2003 Microchip Technology Inc.
PIC18F6X2X/8X2X
TABLE 19-3: BAUD RATES FOR ASYNCHRONOUS MODES (CONTINUED)
SYNC = 0, BRGH = 0, BRG16 = 1
BAUD
RATE
(K)
FOSC = 40.000 MHz
FOSC = 20.000 MHz FOSC = 10.000 MHz
FOSC = 8.000 MHz
Actual
Rate
(K)
SPBRG Actual
value
SPBRG Actual
SPBRG Actual
value
(decimal)
SPBRG
value
(decimal)
%
%
Error
%
Error
%
Error
Rate
(K)
value
Rate
(K)
Rate
(K)
Error
(decimal)
(decimal)
0.3
1.2
0.300
1.200
0.00
0.02
0.06
0.16
0.16
0.94
-1.36
8332
2082
1040
259
129
42
0.300
1.200
0.02
-0.03
-0.03
0.16
4165
1041
520
129
64
0.300
1.200
0.02
-0.03
0.16
0.16
1.73
-1.36
8.51
2082
520
259
64
300
1201
2403
9615
19230
55555
—
-0.04
-0.16
-0.16
-0.16
-0.16
3.55
—
1665
415
207
51
2.4
2.402
2.399
2.404
9.6
9.615
9.615
9.615
19.2
57.6
115.2
19.231
58.140
113.636
19.231
56.818
113.636
0.16
19.531
56.818
125.000
31
25
-1.36
-1.36
21
10
8
21
10
4
—
SYNC = 0, BRGH = 0, BRG16 = 1
BAUD
RATE
(K)
FOSC = 4.000 MHz
FOSC = 2.000 MHz
FOSC = 1.000 MHz
Actual
Rate
(K)
SPBRG Actual
value
SPBRG Actual
value
(decimal)
SPBRG
value
(decimal)
%
%
Error
%
Error
Rate
(K)
Rate
(K)
Error
(decimal)
0.3
1.2
0.300
1.202
0.04
0.16
0.16
0.16
0.16
8.51
8.51
832
207
103
25
12
3
300
1201
2403
9615
—
-0.16
-0.16
-0.16
-0.16
—
415
103
51
12
—
300
1201
2403
—
-0.16
-0.16
-0.16
—
207
51
25
—
2.4
2.404
9.6
9.615
19.2
57.6
115.2
19.231
62.500
125.000
—
—
—
—
—
—
—
—
—
1
—
—
—
—
—
—
SYNC = 0, BRGH = 1, BRG16 = 1 or SYNC = 1, BRG16 = 1
FOSC = 20.000 MHz FOSC = 10.000 MHz
BAUD
RATE
(K)
FOSC = 40.000 MHz
FOSC = 8.000 MHz
Actual
Rate
(K)
SPBRG Actual
SPBRG Actual
SPBRG Actual
value
SPBRG
value
(decimal)
%
Error
%
%
%
Error
value
(decimal)
Rate
(K)
value
Rate
(K)
Rate
(K)
Error
Error
(decimal)
(decimal)
0.3
1.2
0.300
1.200
0.00
0.00
0.02
0.06
-0.03
0.35
-0.22
33332
8332
4165
1040
520
0.300
1.200
0.00
0.02
0.02
-0.03
0.16
-0.22
0.94
16665
4165
2082
520
259
86
0.300
1.200
0.00
0.02
0.06
0.16
0.16
0.94
-1.36
8332
2082
1040
259
129
42
300
1200
-0.01
-0.04
-0.04
-0.16
-0.16
0.79
6665
1665
832
207
103
34
2.4
2.400
2.400
2.402
2400
9.6
9.606
9.596
9.615
9615
19.2
57.6
115.2
19.193
57.803
114.943
19.231
57.471
116.279
19.231
58.140
113.636
19230
57142
117647
172
86
42
21
-2.12
16
SYNC = 0, BRGH = 1, BRG16 = 1 or SYNC = 1, BRG16 = 1
FOSC = 4.000 MHz FOSC = 2.000 MHz FOSC = 1.000 MHz
BAUD
RATE
(K)
Actual
Rate
(K)
SPBRG Actual
SPBRG Actual
SPBRG
value
(decimal)
%
Error
%
Error
%
Error
value
Rate
(K)
value
Rate
(K)
(decimal)
(decimal)
0.3
1.2
0.300
1.200
0.01
0.04
0.16
0.16
0.16
2.12
-3.55
3332
832
415
103
51
300
1201
2403
9615
19230
55555
—
-0.04
-0.16
-0.16
-0.16
-0.16
3.55
—
1665
415
207
51
300
1201
2403
9615
19230
—
-0.04
-0.16
-0.16
-0.16
-0.16
—
832
207
103
25
2.4
2.404
9.6
9.615
19.2
57.6
115.2
19.231
58.824
111.111
25
12
16
8
—
8
—
—
—
—
2003 Microchip Technology Inc.
Advance Information
DS39612A-page 221
PIC18F6X2X/8X2X
no carry occurred for 8-bit modes by checking for 00h
in the SPBRGHx register. Refer to Table 19-4 for
counter clock rates to the BRG.
19.1.2
AUTO BAUD RATE DETECT
The enhanced USART module supports the automatic
detection and calibration of baud rate. This feature is
active only in Asynchronous mode and while the WUE
bit is clear.
While the ABD sequence takes place, the USART state
machine is held in IDLE. The RCIF interrupt is set once
the fifth rising edge on RX is detected. The value in the
RCREGx needs to be read to clear the RCIF interrupt.
RCREGx content should be discarded.
The automatic baud rate measurement sequence
(Figure 19-1) begins whenever a START bit is received
and the ABDEN bit is set. The calculation is
self-averaging.
Note 1: If the WUE bit is set with the ABDEN bit,
auto baud rate detection will occur on the
byte following the Break character.
In the Auto Baud Rate Detect (ABD) mode, the clock to
the BRG is reversed. Rather than the BRG clocking the
incoming RX signal, the RX signal is timing the BRG. In
ABD mode, the internal baud rate generator is used as
a counter to time the bit period of the incoming serial
byte stream.
2: It is up to the user to determine that the
incoming character baud rate is within the
range of the selected BRG clock source.
Some combinations of oscillator fre-
quency and USART baud rates are not
possible due to bit error rates. Overall
system timing and communication baud
rates must be taken into consideration
when using the auto baud rate detection
feature.
Once the ABDEN bit is set, the state machine will clear
the BRG and look for a START bit. The auto baud
detect must receive a byte with the value 55h (ASCII
“U”, which is also the LIN bus Sync character), in order
to calculate the proper bit rate. The measurement is
taken over both a low and a high bit time in order to
minimize any effects caused by asymmetry of the
incoming signal. After a START bit, the SPBRGx
begins counting up using the preselected clock source
on the first rising edge of RX. After eight bits on the RX
pin or the fifth rising edge, an accumulated value total-
ling the proper BRG period is left in the
SPBRGHx:SPBRGx register pair. Once the 5th edge is
seen (this should correspond to the STOP bit), the
ABDEN bit is automatically cleared.
TABLE 19-4: BRG COUNTER CLOCK
RATES
BRG16 BRGH
BRG Counter Clock
0
0
0
1
FOSC/512
FOSC/128
1
1
0
1
FOSC/128
FOSC/32
While calibrating the baud rate period, the BRG regis-
ters are clocked at 1/8th the preconfigured clock rate.
Note that the BRG clock will be configured by the
BRG16 and BRGH bits. Independent of the BRG16 bit
setting, both the SPBRGx and SPBRGHx will be used
as a 16-bit counter. This allows the user to verify that
Note:
During the ABD sequence, SPBRGx and
SPBRGHx are both used as a 16-bit
counter, independent of BRG16 setting.
FIGURE 19-1:
AUTOMATIC BAUD RATE CALCULATION
BRG Value
XXXXh
0000h
001Ch
Edge #1
Edge #2
Bit 3
Edge #3
Bit 5
Edge #4
Bit 7
Edge #5
RX pin
Bit 1
START
Bit 0
Bit 2
Bit 4
Bit 6
STOP Bit
BRG Clock
Auto Cleared
Set by User
ABDEN bit
RCIF bit
(Interrupt)
Read
RCREGx
XXXXh
XXXXh
1Ch
00h
SPBRGx
SPBRGHx
Note: The ABD sequence requires the USART module to be configured in Asynchronous mode and WUE = 0.
DS39612A-page 222
Advance Information
2003 Microchip Technology Inc.
PIC18F6X2X/8X2X
Once the TXREGx register transfers the data to the TSR
register (occurs in one TCY), the TXREGx register is
empty and flag bit TXIF (PIR1<4>) is set. This interrupt
can be enabled/disabled by setting/clearing enable bit
TXIE (PIE1<4>). Flag bit TXIF will be set regardless of
the state of enable bit TXIE and cannot be cleared in
software. Flag bit TXIF is not cleared immediately upon
loading the Transmit Buffer register, TXREGx. TXIF
becomes valid in the second instruction cycle following
the load instruction. Polling TXIF immediately following a
load of TXREGx will return invalid results.
19.2 USART Asynchronous Mode
The Asynchronous mode of operation is selected by
clearing the SYNC bit (TXSTAx<4>). In this mode, the
USART uses standard non-return-to-zero (NRZ) format
(one START bit, eight or nine data bits and one STOP
bit). The most common data format is 8 bits. An on-chip
dedicated 8-bit/16-bit baud rate generator can be used
to derive standard baud rate frequencies from the
oscillator.
The USART transmits and receives the LSb first. The
USART’s transmitter and receiver are functionally inde-
pendent but use the same data format and baud rate.
The baud rate generator produces a clock, either x16
or x64 of the bit shift rate depending on the BRGH and
BRG16 bits (TXSTAx<2> and BAUDCONx<3>). Parity
is not supported by the hardware but can be
implemented in software and stored as the 9th data bit.
While flag bit TXIF indicates the status of the TXREGx
register, another bit, TRMT (TXSTAx<1>), shows the
status of the TSR register. Status bit TRMT is a read
only bit which is set when the TSR register is empty. No
interrupt logic is tied to this bit so the user has to poll
this bit in order to determine if the TSR register is
empty.
When operating in Asynchronous mode, the USART
module consists of the following important elements:
Note 1: The TSR register is not mapped in data
memory so it is not available to the user.
• Baud Rate Generator
2: Flag bit TXIF is set when enable bit TXEN
• Sampling Circuit
is set.
• Asynchronous Transmitter
• Asynchronous Receiver
To set up an Asynchronous Transmission:
1. Initialize the SPBRGHx:SPBRGx registers for
the appropriate baud rate. Set or clear the
BRGH and BRG16 bits, as required, to achieve
the desired baud rate.
• Auto Wake-up on Sync Break Character
• 12-bit Break Character Transmit
• Auto Baud Rate Detection
2. Enable the asynchronous serial port by clearing
bit SYNC and setting bit SPEN.
19.2.1
USART ASYNCHRONOUS
TRANSMITTER
3. If interrupts are desired, set enable bit TXIE.
The USART transmitter block diagram is shown in
Figure 19-2. The heart of the transmitter is the Transmit
(Serial) Shift Register (TSR). The Shift register obtains
its data from the Read/Write Transmit Buffer register,
TXREGx. The TXREGx register is loaded with data in
software. The TSR register is not loaded until the STOP
bit has been transmitted from the previous load. As
soon as the STOP bit is transmitted, the TSR is loaded
with new data from the TXREGx register (if available).
4. If 9-bit transmission is desired, set transmit bit
TX9. Can be used as address/data bit.
5. Enable the transmission by setting bit TXEN
which will also set bit TXIF.
6. If 9-bit transmission is selected, the ninth bit
should be loaded in bit TX9D.
7. Load data to the TXREGx register (starts
transmission).
If using interrupts, ensure that the GIE and PEIE bits in
the INTCON register (INTCON<7:6>) are set.
FIGURE 19-2:
USART TRANSMIT BLOCK DIAGRAM
Data Bus
TXIF
TXREGx Register
8
TXIE
MSb
(8)
LSb
0
Pin Buffer
and Control
•
• •
TSR Register
TX pin
Interrupt
Baud Rate CLK
TXEN
TRMT
SPEN
BRG16
SPBRGHx SPBRGx
Baud Rate Generator
TX9
TX9D
2003 Microchip Technology Inc.
Advance Information
DS39612A-page 223
PIC18F6X2X/8X2X
FIGURE 19-3:
ASYNCHRONOUS TRANSMISSION
Write to TXREGx
Word 1
BRG Output
(Shift Clock)
TX
(pin)
START bit
bit 0
bit 1
Word 1
bit 7/8
STOP bit
TXIF bit
(Transmit Buffer
Reg. Empty Flag)
1 TCY
Word 1
Transmit Shift Reg
TRMT bit
(Transmit Shift
Reg. Empty Flag)
FIGURE 19-4:
ASYNCHRONOUS TRANSMISSION (BACK TO BACK)
Write to TXREGx
Word 2
Word 1
BRG Output
(Shift Clock)
TX
(pin)
START bit
START bit
Word 2
bit 0
bit 1
bit 7/8
bit 0
STOP bit
1 TCY
Word 1
TXIF bit
(Interrupt Reg. Flag)
1 TCY
Word 1
Transmit Shift Reg.
Word 2
Transmit Shift Reg.
TRMT bit
(Transmit Shift
Reg. Empty Flag)
Note:
This timing diagram shows two consecutive transmissions.
TABLE 19-5: REGISTERS ASSOCIATED WITH ASYNCHRONOUS TRANSMISSION
Value on
all other
RESETS
Value on
POR, BOR
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
INTCON
PIR1
GIE/GIEH PEIE/GIEL TMR0IE INT0IE
RBIE
—
TMR0IF INT0IF
RBIF
0000 000x 0000 000u
—
—
ADIF
ADIE
ADIP
RX9
RCIF
RCIE
RCIP
SREN
TXIF
TXIE
TXIP
CCP1IF TMR2IF TMR1IF -000 -000 -000 -000
CCP1IE TMR2IE TMR1IE -000 -000 -000 -000
CCP1IP TMR2IP TMR1IP -111 -111 -111 -111
PIE1
—
IPR1
—
—
RCSTAx
TXREGx
TXSTAx
BAUDCONx
SPEN
CREN ADDEN
FERR
OERR
RX9D
0000 -00x 0000 -00x
0000 0000 0000 0000
0000 0010 0000 0010
USART Transmit Register
CSRC
—
TX9
TXEN
—
SYNC SENDB BRGH
SCKP BRG16
TRMT
WUE
TX9D
RCIDL
—
ABDEN -1-1 0-00 -1-1 0-00
0000 0000 0000 0000
SPBRGHx Baud Rate Generator Register, High Byte
SPBRGx
Legend:
Baud Rate Generator Register, Low Byte
0000 0000 0000 0000
x= unknown, - = unimplemented locations read as ‘0’. Shaded cells are not used for asynchronous transmission.
DS39612A-page 224
Advance Information
2003 Microchip Technology Inc.
PIC18F6X2X/8X2X
19.2.2
USART ASYNCHRONOUS
RECEIVER
19.2.3
SETTING UP 9-BIT MODE WITH
ADDRESS DETECT
The receiver block diagram is shown in Figure 19-5.
The data is received on the RXx pin and drives the data
recovery block. The data recovery block is actually a
high speed shifter operating at x16 times the baud rate,
whereas the main receive serial shifter operates at the
bit rate or at FOSC. This mode would typically be used
in RS-232 systems.
This mode would typically be used in RS-485 systems.
To set up an Asynchronous Reception with Address
Detect Enable:
1. Initialize the SPBRGHx:SPBRGx registers for
the appropriate baud rate. Set or clear the
BRGH and BRG16 bits, as required, to achieve
the desired baud rate.
To set up an Asynchronous Reception:
2. Enable the asynchronous serial port by clearing
the SYNC bit and setting the SPEN bit.
1. Initialize the SPBRGHx:SPBRGx registers for
the appropriate baud rate. Set or clear the
BRGH and BRG16 bits, as required, to achieve
the desired baud rate.
3. If interrupts are required, set the RCEN bit and
select the desired priority level with the RCIP bit.
4. Set the RX9 bit to enable 9-bit reception.
5. Set the ADDEN bit to enable address detect.
6. Enable reception by setting the CREN bit.
2. Enable the asynchronous serial port by clearing
bit SYNC and setting bit SPEN.
3. If interrupts are desired, set enable bit RCIE.
4. If 9-bit reception is desired, set bit RX9.
5. Enable the reception by setting bit CREN.
7. The RCIF bit will be set when reception is com-
plete. The interrupt will be Acknowledged if the
RCIE and GIE bits are set.
6. Flag bit RCIF will be set when reception is com-
plete and an interrupt will be generated if enable
bit RCIE was set.
8. Read the RCSTAx register to determine if any
error occurred during reception, as well as read
bit 9 of data (if applicable).
7. Read the RCSTAx register to get the 9th bit (if
enabled) and determine if any error occurred
during reception.
9. Read RCREGx to determine if the device is
being addressed.
10. If any error occurred, clear the CREN bit.
8. Read the 8-bit received data by reading the
RCREGx register.
11. If the device has been addressed, clear the
ADDEN bit to allow all received data into the
receive buffer and interrupt the CPU.
9. If any error occurred, clear the error by clearing
enable bit CREN.
10. If using interrupts, ensure that the GIE and PEIE
bits in the INTCON register (INTCON<7:6>) are
set.
FIGURE 19-5:
USART RECEIVE BLOCK DIAGRAM
CREN
OERR
FERR
x64 Baud Rate CLK
÷ 64
RSR Register
• • •
MSb
LSb
BRG16
SPBRGHx SPBRGx
or
÷ 16
STOP (8)
7
1
0
START
or
Baud Rate Generator
÷ 4
RX9
Pin Buffer
and Control
Data
Recovery
RX
RX9D
RCREGx Register
FIFO
SPEN
8
Interrupt
RCIF
RCIE
Data Bus
2003 Microchip Technology Inc.
Advance Information
DS39612A-page 225
PIC18F6X2X/8X2X
FIGURE 19-6:
ASYNCHRONOUS RECEPTION
START
bit
START
bit
START
STOP bit
bit
RX (pin)
bit 0 bit 1
bit 7/8
STOP
bit
STOP
bit
bit 0
bit 7/8
bit 7/8
Rcv Shift Reg
Rcv Buffer Reg
Word 2
RCREGx
Word 1
RCREGx
Read Rcv
Buffer Reg
RCREGx
RCIF
(Interrupt Flag)
OERR bit
CREN
Note:
This timing diagram shows three words appearing on the RX input. The RCREGx (receive buffer) is read after the third word
causing the OERR (overrun) bit to be set.
TABLE 19-6: REGISTERS ASSOCIATED WITH ASYNCHRONOUS RECEPTION
Value on
all other
RESETS
Value on
POR, BOR
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
INTCON
PIR1
GIE/GIEH PEIE/GIEL TMR0IE INT0IE
RBIE
—
TMR0IF INT0IF
RBIF
0000 000x 0000 000u
—
—
ADIF
ADIE
ADIP
RX9
RCIF
RCIE
RCIP
SREN
TXIF
TXIE
TXIP
CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
CCP1IP TMR2IP TMR1IP 1111 1111 1111 1111
PIE1
—
IPR1
—
—
RCSTAx
RCREGx
TXSTAx
BAUDCONx
SPEN
CREN ADDEN FERR
OERR
RX9D
0000 000x 0000 000x
0000 0000 0000 0000
0000 0010 0000 0010
USART Receive Register
CSRC
—
TX9
TXEN
—
SYNC SENDB BRGH
TRMT
WUE
TX9D
RCIDL
SCKP BRG16
—
ABDEN -1-1 0-00 -1-1 0-00
0000 0000 0000 0000
SPBRGHx Baud Rate Generator Register, High Byte
SPBRGx
Legend:
Baud Rate Generator Register, Low Byte
0000 0000 0000 0000
x= unknown, - = unimplemented locations read as ‘0’. Shaded cells are not used for asynchronous reception.
DS39612A-page 226
Advance Information
2003 Microchip Technology Inc.
PIC18F6X2X/8X2X
and cause data or framing errors. To work properly,
therefore, the initial character in the transmission must
be all ‘0’s. This can be 00h (8 bytes) for standard RS-232
devices, or 000h (12 bits) for LIN bus.
19.2.4
AUTO WAKE-UP ON SYNC BREAK
CHARACTER
During SLEEP mode, all clocks to the USART are sus-
pended. Because of this, the baud rate generator is
inactive and a proper byte reception cannot be per-
formed. The auto wake-up feature allows the controller
to wake-up due to activity on the RX/DT line while the
USART is operating in Asynchronous mode.
Oscillator start-up time must also be considered,
especially in applications using oscillators with longer
start-up intervals (i.e., XT or HS mode). The Sync
Break (or Wake-up Signal) character must be of suffi-
cient length and be followed by a sufficient interval to
allow enough time for the selected oscillator to start
and provide proper initialization of the USART.
The auto wake-up feature is enabled by setting the
WUE bit (BAUDCONx<1>). Once set, the typical
receive sequence on RX/DT is disabled, and the
USART remains in an IDLE state, monitoring for a
wake-up event independent of the CPU mode. A wake-
up event consists of a high-to-low transition on the RX/
DT line. (This coincides with the start of a Sync Break
or a Wake-up Signal character for the LIN protocol.)
19.2.4.2
Special Considerations Using the
WUE Bit
The timing of WUE and RCIF events may cause some
confusion when it comes to determining the validity of
received data. As noted, setting the WUE bit places the
USART in an IDLE mode. The wake-up event causes a
receive interrupt by setting the RCIF bit. The WUE bit
is cleared after this when a rising edge is seen on RX/
DT. The interrupt condition is then cleared by reading
the RCREGx register. Ordinarily, the data in RCREGx
will be dummy data and should be discarded.
Following a wake-up event, the module generates an
RCIF interrupt. The interrupt is generated synchro-
nously to the Q clocks in normal operating modes
(Figure 19-7) and asynchronously, if the device is in
SLEEP mode (Figure 19-8). The interrupt condition is
cleared by reading the RCREGx register.
The WUE bit is automatically cleared once a low-to-high
transition is observed on the RX line following the wake-
up event. At this point, the USART module is in IDLE
mode and returns to normal operation. This signals to
the user that the Sync Break event is over.
The fact that the WUE bit has been cleared (or is still
set) and the RCIF flag is set should not be used as an
indicator of the integrity of the data in RCREGx. Users
should consider implementing a parallel method in
firmware to verify received data integrity.
To assure that no actual data is lost, check the RCIDL
bit to verify that a receive operation is not in process. If
a receive operation is not occurring, the WUE bit may
then be set just prior to entering the SLEEP mode.
19.2.4.1
Special Considerations Using Auto
Wake-up
Since auto wake-up functions by sensing rising edge
transitions on RX/DT, information with any state changes
before the STOP bit may signal a false end-of-character
FIGURE 19-7:
AUTO WAKE-UP BIT (WUE) TIMINGS DURING NORMAL OPERATION
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
OSC1
WUE bit
Bit set by user
Auto Cleared
RX/DT Line
RCIF
Cleared due to user read of RCREGx
Note: The USART remains in IDLE while the WUE bit is set.
FIGURE 19-8:
AUTO WAKE-UP BIT (WUE) TIMINGS DURING SLEEP
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
Q1
Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
OSC1
WUE bit
Bit set by user
Auto Cleared
RX/DT Line
RCIF
Note 1
Cleared due to user read of RCREGx
SLEEP Ends
SLEEP Command Executed
Note 1: If the wake-up event requires long oscillator warm-up time, the auto clear of the WUE bit can occur while the stposc signal is still active.
This sequence should not depend on the presence of Q clocks.
2: The USART remains in IDLE while the WUE bit is set.
2003 Microchip Technology Inc.
Advance Information
DS39612A-page 227
PIC18F6X2X/8X2X
1. Configure the USART for the desired mode.
19.2.5
BREAK CHARACTER SEQUENCE
2. Set the TXEN and SENDB bits to set up the
Break character.
The enhanced USART module has the capability of
sending the special Break character sequences that
are required by the LIN bus standard. The Break char-
acter transmit consists of a START bit, followed by
twelve ‘0’ bits and a STOP bit. The frame Break char-
acter is sent whenever the SENDB and TXEN bits
(TXSTAx<3> and TXSTAx<5>) are set while the Trans-
mit Shift register is loaded with data. Note that the value
of data written to TXREGx will be ignored and all ‘0’s
will be transmitted.
3. Load the TXREGx with a dummy character to
initiate transmission (the value is ignored).
4. Write ‘55h’ to TXREGx to load the Sync
character into the transmit FIFO buffer.
5. After the Break has been sent, the SENDB bit is
reset by hardware. The Sync character now
transmits in the preconfigured mode.
When the TXREGx becomes empty, as indicated by
the TXIF, the next data byte can be written to TXREGx.
The SENDB bit is automatically reset by hardware after
the corresponding STOP bit is sent. This allows the
user to preload the transmit FIFO with the next transmit
byte following the Break character (typically, the Sync
character in the LIN specification).
19.2.6
RECEIVING A BREAK CHARACTER
The Enhanced USART module can receive a Break
character in two ways.
Note that the data value written to the TXREGx for the
Break character is ignored. The write simply serves the
purpose of initiating the proper sequence.
The first method forces configuration of the baud rate
at a frequency of 9/13 the typical speed. This allows for
the STOP bit transition to be at the correct sampling
location (13 bits for Break versus START bit and 8 data
bits for typical data).
The TRMT bit indicates when the transmit operation is
active or IDLE, just as it does during normal transmis-
sion. See Figure 19-9 for the timing of the Break
character sequence.
The second method uses the auto wake-up feature
described in Section 19.2.4. By enabling this feature,
the USART will sample the next two transitions on RX/
DT, cause an RCIF interrupt, and receive the next data
byte followed by another interrupt.
19.2.5.1
Break and Sync Transmit Sequence
The following sequence will send a message frame
header made up of a Break, followed by an auto baud
Sync byte. This sequence is typical of a LIN bus
master.
Note that following a Break character, the user will typ-
ically want to enable the auto baud rate detect feature.
For both methods, the user can set the ABD bit once
the TXIF interrupt is observed.
FIGURE 19-9:
SEND BREAK CHARACTER SEQUENCE
Write to TXREGx
Dummy Write
BRG Output
(Shift Clock)
TX (pin)
START Bit
Bit 0
Bit 1
Break
Bit 11
STOP Bit
TXIF bit
(Transmit Buffer
Reg. Empty Flag)
TRMT bit
(Transmit Shift
Reg. Empty Flag)
SENDB sampled here
Auto Cleared
SENDB
(Transmit Shift
Reg. Empty Flag)
DS39612A-page 228
Advance Information
2003 Microchip Technology Inc.
PIC18F6X2X/8X2X
Once the TXREGx register transfers the data to the
TSR register (occurs in one TCYCLE), the TXREGx is
empty and interrupt bit TXIF (PIR1<4>) is set. The
interrupt can be enabled/disabled by setting/clearing
enable bit TXIE (PIE1<4>). Flag bit TXIF will be set
regardless of the state of enable bit TXIE, and cannot
be cleared in software. It will reset only when new data
is loaded into the TXREGx register.
19.3 USART Synchronous Master
Mode
The Synchronous Master mode is entered by setting
the CSRC bit (TXSTAx<7>). In this mode, the data is
transmitted in a half-duplex manner (i.e., transmission
and reception do not occur at the same time). When
transmitting data, the reception is inhibited and vice
versa. Synchronous mode is entered by setting bit
SYNC (TXSTAx<4>). In addition, enable bit SPEN
(RCSTAx<7>) is set in order to configure the TXx and
RXx pins to CK (clock) and DT (data) lines,
respectively.
While flag bit TXIF indicates the status of the TXREGx
register, another bit, TRMT (TXSTAx<1>), shows the
status of the TSR register. TRMT is a read only bit which
is set when the TSR is empty. No interrupt logic is tied to
this bit so the user has to poll this bit in order to deter-
mine if the TSR register is empty. The TSR is not
mapped in data memory so it is not available to the user.
The Master mode indicates that the processor trans-
mits the master clock on the CK line. Clock polarity is
selected with the SCKP bit (BAUDCONx<4>); setting
SCKP sets the IDLE state on CK as high, while clearing
the bit sets the IDLE state as low. This option is
provided to support Microwire® devices with this
module.
To set up a Synchronous Master Transmission:
1. Initialize the SPBRGHx:SPBRGx registers for
the appropriate baud rate. Set or clear the
BRG16 bit, as required, to achieve the desired
baud rate.
19.3.1
USART SYNCHRONOUS MASTER
TRANSMISSION
2. Enable the synchronous master serial port by
setting bits SYNC, SPEN, and CSRC.
3. If interrupts are desired, set enable bit TXIE.
4. If 9-bit transmission is desired, set bit TX9.
5. Enable the transmission by setting bit TXEN.
The USART transmitter block diagram is shown in
Figure 19-2. The heart of the transmitter is the Transmit
(Serial) Shift Register (TSR). The Shift register obtains
its data from the Read/Write Transmit Buffer register,
TXREGx. The TXREGx register is loaded with data in
software. The TSR register is not loaded until the last
bit has been transmitted from the previous load. As
soon as the last bit is transmitted, the TSR is loaded
with new data from the TXREGx (if available).
6. If 9-bit transmission is selected, the ninth bit
should be loaded in bit TX9D.
7. Start transmission by loading data to the
TXREGx register.
8. If using interrupts, ensure that the GIE and PEIE
bits in the INTCON register (INTCON<7:6>) are
set.
FIGURE 19-10:
SYNCHRONOUS TRANSMISSION
Q1 Q2 Q3Q4 Q1 Q2 Q3 Q4 Q1Q2 Q3 Q4 Q1Q2 Q3 Q4Q1 Q2 Q3 Q4
Q3 Q4 Q1 Q2 Q3Q4 Q1Q2 Q3Q4 Q1 Q2Q3Q4 Q1 Q2Q3 Q4Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
RC7/RX1/DT1
pin
bit 0
bit 1
bit 2
bit 7
bit 0
bit 1
bit 7
Word 2
Word 1
RC6/TX1/CK1 pin
(SCKP = 0)
RC6/TX1/CK1 pin
(SCKP = 1)
Write to
TXREGx Reg
Write Word 1
Write Word 2
TXIF bit
(Interrupt Flag)
TRMT bit
‘1’
‘1’
TXEN bit
Note: Sync Master mode, SPBRGx = 0, continuous transmission of two 8-bit words.
2003 Microchip Technology Inc.
Advance Information
DS39612A-page 229
PIC18F6X2X/8X2X
FIGURE 19-11:
SYNCHRONOUS TRANSMISSION (THROUGH TXEN)
RC7/RX1/DT1 pin
bit 0
bit 2
bit 1
bit 6
bit 7
RC6/TX1/CK1 pin
Write to
TXREGx reg
TXIF bit
TRMT bit
TXEN bit
TABLE 19-7: REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER TRANSMISSION
Value on
all other
RESETS
Value on
POR, BOR
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
INTCON
PIR1
GIE/GIEH PEIE/GIEL TMR0IE INT0IE
RBIE
—
TMR0IF
INT0IF
RBIF
0000 0000 0000 0000
—
—
ADIF
ADIE
ADIP
RX9
RCIF
RCIE
RCIP
SREN
TXIF
TXIE
TXIP
CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
CCP1IP TMR2IP TMR1IP 1111 1111 1111 1111
PIE1
—
IPR1
—
—
RCSTAx
TXREGx
TXSTAx
BAUDCONx
SPEN
CREN ADDEN
FERR
OERR
RX9D
0000 000x 0000 000x
0000 0000 0000 0000
0000 0010 0000 0010
-1-0 0-00 -1-0 0-00
0000 0000 0000 0000
0000 0000 0000 0000
USART Transmit Register
CSRC
—
TX9
TXEN
—
SYNC SENDB
SCKP BRG16
BRGH
—
TRMT
WUE
TX9D
RCIDL
ABDEN
SPBRGHx Baud Rate Generator Register, High Byte
SPBRGx
Legend:
Baud Rate Generator Register, Low Byte
x= unknown, - = unimplemented, read as ‘0’. Shaded cells are not used for synchronous master transmission.
DS39612A-page 230
Advance Information
2003 Microchip Technology Inc.
PIC18F6X2X/8X2X
3. Ensure bits CREN and SREN are clear.
4. If interrupts are desired, set enable bit RCIE.
5. If 9-bit reception is desired, set bit RX9.
19.3.2
USART SYNCHRONOUS MASTER
RECEPTION
Once Synchronous mode is selected, reception is
enabled by setting either the Single Receive Enable bit,
SREN (RCSTAx<5>), or the Continuous Receive
Enable bit, CREN (RCSTAx<4>). Data is sampled on
the RXx pin on the falling edge of the clock.
6. If a single reception is required, set bit SREN.
For continuous reception, set bit CREN.
7. Interrupt flag bit RCIF will be set when reception
is complete and an interrupt will be generated if
the enable bit RCIE was set.
If enable bit SREN is set, only a single word is received.
If enable bit CREN is set, the reception is continuous
until CREN is cleared. If both bits are set, then CREN
takes precedence.
8. Read the RCSTAx register to get the 9th bit (if
enabled) and determine if any error occurred
during reception.
9. Read the 8-bit received data by reading the
RCREGx register.
To set up a Synchronous Master Reception:
1. Initialize the SPBRGHx:SPBRGx registers for
the appropriate baud rate. Set or clear the
BRG16 bit, as required, to achieve the desired
baud rate.
10. If any error occurred, clear the error by clearing
bit CREN.
11. If using interrupts, ensure that the GIE and PEIE
bits in the INTCON register (INTCON<7:6>) are
set.
2. Enable the synchronous master serial port by
setting bits SYNC, SPEN and CSRC.
FIGURE 19-12:
SYNCHRONOUS RECEPTION (MASTER MODE, SREN)
Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4Q1 Q2 Q3 Q4 Q1Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
RC7/RX1/DT1
pin
bit 0
bit 1
bit 2
bit 3
bit 4
bit 5
bit 6
bit 7
RC7/TX1/CK1 pin
(SCKP = 0)
RC7/TX1/CK1 pin
(SCKP = 1)
Write to
bit SREN
SREN bit
CREN bit ‘0’
‘0’
RCIF bit
(Interrupt)
Read
RXREG
Note: Timing diagram demonstrates Sync Master mode with bit SREN = 1and bit BRGH = 0.
TABLE 19-8: REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER RECEPTION
Value on
all other
RESETS
Value on
POR, BOR
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
INTCON
PIR1
GIE/GIEH PEIE/GIEL TMR0IE INT0IE
RBIE
—
TMR0IF INT0IF
RBIF
0000 0000 0000 0000
—
—
ADIF
ADIE
ADIP
RX9
RCIF
RCIE
RCIP
SREN
TXIF
TXIE
TXIP
CCP1IF TMR2IF TMR1IF 0000 -000 0000 -000
CCP1IE TMR2IE TMR1IE 0000 -000 0000 -000
CCP1IP TMR2IP TMR1IP 1111 1111 1111 1111
PIE1
—
IPR1
—
—
RCSTAx
RCREGx
TXSTAx
BAUDCONx
SPEN
CREN ADDEN
FERR
OERR
RX9D
0000 000x 0000 000x
0000 0000 0000 0000
0000 0010 0000 0010
USART Receive Register
CSRC
—
TX9
TXEN
—
SYNC SENDB
BRGH
—
TRMT
WUE
TX9D
RCIDL
SCKP
BRG16
ABDEN -1-0 0-00 -1-0 0-00
0000 0000 0000 0000
SPBRGHx Baud Rate Generator Register, High Byte
SPBRGx
Legend:
Baud Rate Generator Register, Low Byte
0000 0000 0000 0000
x= unknown, - = unimplemented, read as ‘0’. Shaded cells are not used for synchronous master reception.
2003 Microchip Technology Inc.
Advance Information
DS39612A-page 231
PIC18F6X2X/8X2X
To set up a Synchronous Slave Transmission:
19.4 USART Synchronous Slave Mode
1. Enable the synchronous slave serial port by set-
ting bits SYNC and SPEN and clearing bit
CSRC.
Synchronous Slave mode is entered by clearing bit
CSRC (TXSTAx<7>). This mode differs from the Syn-
chronous Master mode in that the shift clock is supplied
externally at the CKx pin (instead of being supplied
internally in Master mode). This allows the device to
transfer or receive data while in any Low Power mode.
2. Clear bits CREN and SREN.
3. If interrupts are desired, set enable bit TXIE.
4. If 9-bit transmission is desired, set bit TX9.
5. Enable the transmission by setting enable bit
TXEN.
19.4.1
USART SYNCHRONOUS SLAVE
TRANSMIT
6. If 9-bit transmission is selected, the ninth bit
should be loaded in bit TX9D.
The operation of the Synchronous Master and Slave
modes are identical except in the case of the SLEEP
mode.
7. Start transmission by loading data to the
TXREGx register.
If two words are written to the TXREGx and then the
SLEEPinstruction is executed, the following will occur:
8. If using interrupts, ensure that the GIE and PEIE
bits in the INTCON register (INTCON<7:6>) are
set.
a) The first word will immediately transfer to the
TSR register and transmit.
b) The second word will remain in TXREGx
register.
c) Flag bit TXIF will not be set.
d) When the first word has been shifted out of TSR,
the TXREGx register will transfer the second
word to the TSR and flag bit TXIF will now be
set.
e) If enable bit TXIE is set, the interrupt will wake
the chip from SLEEP. If the global interrupt is
enabled, the program will branch to the interrupt
vector.
TABLE 19-9: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE TRANSMISSION
Value on
all other
RESETS
Value on
POR, BOR
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
INTCON
PIR1
GIE/GIEH PEIE/GIEL TMR0IE INT0IE
RBIE
—
TMR0IF INT0IF
RBIF
0000 000x 0000 000u
—
—
ADIF
ADIE
ADIP
RX9
RCIF
RCIE
RCIP
SREN
TXIF
TXIE
TXIP
CREN
CCP1IF TMR2IF TMR1IF -000 -000 -000 -000
CCP1IE TMR2IE TMR1IE -000 -000 -000 -000
CCP1IP TMR2IP TMR1IP -111 -111 -111 -111
PIE1
—
IPR1
—
—
RCSTAx
TXREGx
TXSTAx
BAUDCONx
SPEN
ADDEN
FERR
OERR
RX9D
0000 -00x 0000 -00x
0000 0000 0000 0000
0000 0010 0000 0010
USART Transmit Register
CSRC
—
TX9
TXEN
—
SYNC
SCKP
SENDB BRGH
BRG16
TRMT
WUE
TX9D
RCIDL
—
ABDEN -1-1 0-00 -1-1 0-00
0000 0000 0000 0000
SPBRGHx Baud Rate Generator Register, High Byte
SPBRGx
Legend:
Baud Rate Generator Register, Low Byte
0000 0000 0000 0000
x= unknown, - = unimplemented, read as ‘0’. Shaded cells are not used for synchronous slave transmission.
DS39612A-page 232
Advance Information
2003 Microchip Technology Inc.
PIC18F6X2X/8X2X
To set up a Synchronous Slave Reception:
19.4.2
USART SYNCHRONOUS SLAVE
RECEPTION
1. Enable the synchronous master serial port by
setting bits SYNC and SPEN and clearing bit
CSRC.
The operation of the Synchronous Master and Slave
modes is identical except in the case of SLEEP or any
IDLE mode and bit SREN, which is a “don't care” in
Slave mode.
2. If interrupts are desired, set enable bit RCIE.
3. If 9-bit reception is desired, set bit RX9.
4. To enable reception, set enable bit CREN.
If receive is enabled by setting the CREN bit prior to
entering SLEEP or any IDLE mode, then a word may
be received while in this Low Power mode. Once the
word is received, the RSR register will transfer the data
to the RCREGx register; if the RCIE enable bit is set,
the interrupt generated will wake the chip from Low
Power mode. If the global interrupt is enabled, the
program will branch to the interrupt vector.
5. Flag bit RCIF will be set when reception is com-
plete. An interrupt will be generated if enable bit
RCIE was set.
6. Read the RCSTAx register to get the 9th bit (if
enabled) and determine if any error occurred
during reception.
7. Read the 8-bit received data by reading the
RCREGx register.
8. If any error occurred, clear the error by clearing
bit CREN.
9. If using interrupts, ensure that the GIE and PEIE
bits in the INTCON register (INTCON<7:6>) are
set.
TABLE 19-10: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE RECEPTION
Value on
all other
RESETS
Value on
POR, BOR
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
INTCON
PIR1
GIE/GIEH PEIE/GIEL TMR0IE INT0IE
RBIE
—
TMR0IF INT0IF
RBIF
0000 0000 0000 0000
ADIF
ADIE
ADIP
RX9
RCIF
RCIE
RCIP
SREN
TXIF
TXIE
TXIP
CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
CCP1IP TMR2IP TMR1IP 1111 1111 1111 1111
—
—
PIE1
—
IPR1
—
—
RCSTAx
RCREGx
TXSTAx
BAUDCONx
SPEN
CREN ADDEN
FERR
OERR
RX9D
0000 000x 0000 000x
0000 0000 0000 0000
0000 0010 0000 0010
USART Receive Register
CSRC
—
TX9
TXEN
—
SYNC
SCKP
SENDB BRGH
BRG16
TRMT
WUE
TX9D
RCIDL
—
ABDEN -1-0 0-00 -1-0 0-00
0000 0000 0000 0000
SPBRGHx Baud Rate Generator Register, High Byte
SPBRGx
Legend:
Baud Rate Generator Register, Low Byte
0000 0000 0000 0000
x= unknown, - = unimplemented, read as ‘0’. Shaded cells are not used for synchronous slave reception.
2003 Microchip Technology Inc.
Advance Information
DS39612A-page 233
PIC18F6X2X/8X2X
NOTES:
DS39612A-page 234
Advance Information
2003 Microchip Technology Inc.
PIC18F6X2X/8X2X
The module has five registers:
20.0 10-BIT ANALOG-TO-DIGITAL
CONVERTER (A/D) MODULE
• A/D Result High Register (ADRESH)
• A/D Result Low Register (ADRESL)
• A/D Control Register 0 (ADCON0)
• A/D Control Register 1 ((ADCON1)
• A/D Control Register 2 ((ADCON2)
The analog-to-digital (A/D) converter module has 12
inputs for the PIC18F6X2X devices and 16 for the
PIC18F8X2X devices. This module allows conversion
of an analog input signal to a corresponding 10-bit
digital number.
The ADCON0 register, shown in Register 20-1, con-
trols the operation of the A/D module. The ADCON1
register, shown in Register 20-2, configures the func-
tions of the port pins. The ADCON2, shown in
Register 20-3, configures the A/D clock source,
justification and auto-acquisition time.
A new feature for the A/D converter is the addition of pro-
grammable acquisition time. This feature allows the user
to select a new channel for conversion and setting the
GO/DONE bit immediately. When the GO/DONE bit is
set, the selected channel is sampled for the pro-
grammed acquisition time before a conversion is actu-
ally started. This removes the firmware overhead that
may have been required to allow for an acquisition
(sampling) period (see Register 20-3 and Section 20.4).
REGISTER 20-1: ADCON0 REGISTER
U-0
—
U-0
—
R/W-0
CHS3
R/W-0
CHS2
R/W-0
CHS1
R/W-0
CHS0
R/W-0
R/W-0
ADON
GO/DONE
bit 7
bit 0
bit 7-6 Unimplemented: Read as ‘0’
bit 5-2 CHS3:CHS0: Analog Channel Select bits
0000= Channel 0 (AN0)
0001= Channel 1 (AN1)
0010= Channel 2 (AN2)
0011= Channel 3 (AN3)
0100= Channel 4 (AN4)
0101= Channel 5 (AN5)
0110= Channel 6 (AN6)
0111= Channel 7 (AN7)
1000= Channel 8 (AN8)
1001= Channel 9 (AN9)
1010= Channel 10 (AN10)
1011= Channel 11 (AN11)
1100= Channel 12 (AN12)(1)
1101= Channel 13 (AN13)(1)
1110= Channel 14 (AN14)(1)
1111= Channel 15 (AN15)(1)
Note 1: These channels are not available on the PIC18F6X2X (64-pin) devices.
bit 1
bit 0
GO/DONE: A/D Conversion Status bit
When ADON = 1:
1= A/D conversion in progress (setting this bit starts the A/D conversion which is automatically
cleared by hardware when the A/D conversion is complete)
0= A/D conversion not in progress
ADON: A/D On bit
1= A/D converter module is enabled
0= A/D converter module is disabled
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
- n = Value at POR
2003 Microchip Technology Inc.
Advance Information
DS39612A-page 235
PIC18F6X2X/8X2X
REGISTER 20-2: ADCON1 REGISTER
U-0
—
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
VCFG1
VCFG0
PCFG3
PCFG2
PCFG1
PCFG0
bit 7
bit 0
bit 7-6
bit 5-4
Unimplemented: Read as ‘0’
VCFG1:VCFG0: Voltage Reference Configuration bits:
VCFG1
A/D VREF+
VCFG0
A/D VREF-
00
01
10
11
AVDD
AVSS
External VREF+
AVDD
AVSS
External VREF-
External VREF-
External VREF+
bit 3-0
PCFG3:PCFG0: A/D Port Configuration Control bits:
PCFG3
PCFG0
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
A
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
A
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
A
A
D
D
D
D
D
D
D
D
D
D
D
D
D
D
A
A
A
D
D
D
D
D
D
D
D
D
D
D
D
D
A
A
A
A
D
D
D
D
D
D
D
D
D
D
D
D
A
A
A
A
A
D
D
D
D
D
D
D
D
D
D
D
A
A
A
A
A
A
D
D
D
D
D
D
D
D
D
D
A
A
A
A
A
A
A
D
D
D
D
D
D
D
D
D
A
A
A
A
A
A
A
A
D
D
D
D
D
D
D
D
A
A
A
A
A
A
A
A
A
D
D
D
D
D
D
D
A
A
A
A
A
A
A
A
A
A
D
D
D
D
D
D
A
A
A
A
A
A
A
A
A
A
A
D
D
D
D
D
A
A
A
A
A
A
A
A
A
A
A
A
D
D
D
D
A
A
A
A
A
A
A
A
A
A
A
A
A
D
D
D
A
A
A
A
A
A
A
A
A
A
A
A
A
A
D
D
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
D
A = Analog input
D = Digital I/O
Note:
Shaded cells indicate A/D channels available only on PIC18F8X2X devices.
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
- n = Value at POR
DS39612A-page 236
Advance Information
2003 Microchip Technology Inc.
PIC18F6X2X/8X2X
REGISTER 20-3: ADCON2 REGISTER
R/W-0
ADFM
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
ACQT2
ACQT1
ACQT0
ADCS2
ADCS1
ADCS0
bit 7
bit 0
bit 7
ADFM: A/D Result Format Select bit
1= Right justified
0= Left justified
bit 6
Unimplemented: Read as ‘0’
bit 5-3
ACQT2:ACQT0: A/D Acquisition Time Select bits
(1)
000= 0 TAD
001= 2 TAD
010= 4 TAD
011= 6 TAD
100= 8 TAD
101= 12 TAD
110= 16 TAD
111= 20 TAD
bit 2-0
ADCS2:ADCS0: A/D Conversion Clock Select bits
000= FOSC/2
001= FOSC/8
010= FOSC/32
011= FRC (clock derived from A/D RC oscillator)(1)
100= FOSC/4
101= FOSC/16
110= FOSC/64
111= FRC (clock derived from A/D RC oscillator)(1)
Note 1: If the A/D FRC clock source is selected, a delay of one TCY (instruction cycle) is
added before the A/D clock starts. This allows the SLEEPinstruction to be executed
before starting a conversion.
Legend:
R = Readable bit
- n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
2003 Microchip Technology Inc.
Advance Information
DS39612A-page 237
PIC18F6X2X/8X2X
The analog reference voltage is software selectable to
either the device’s positive and negative supply voltage
(VDD and VSS), or the voltage level on the
RA3/AN3/VREF+ pin and RA2/AN2/VREF- pin.
A device RESET forces all registers to their RESET
state. This forces the A/D module to be turned off and
any conversion is aborted.
Each port pin associated with the A/D converter can be
configured as an analog input (RA3 can also be a volt-
age reference), or as a digital I/O. The ADRESH and
ADRESL registers contain the result of the A/D conver-
sion. When the A/D conversion is complete, the result
is loaded into the ADRESH/ADRESL registers, the
GO/DONE bit (ADCON0 register) is cleared, and A/D
interrupt flag bit, ADIF, is set. The block diagram of the
A/D module is shown in Figure 20-1.
The A/D converter has a unique feature of being able
to operate while the device is in SLEEP mode. To oper-
ate in SLEEP, the A/D conversion clock must be
derived from the A/D’s internal RC oscillator.
The output of the sample and hold is the input into the
converter which generates the result via successive
approximation.
FIGURE 20-1:
A/D BLOCK DIAGRAM
CHS3:CHS0
1111
AN15(1)
1110
AN14(1)
1101
AN13(1)
1100
AN12(1)
1011
AN11
1010
AN10
1001
AN9
1000
AN8
0111
AN7
0110
AN6
0101
AN5
0100
AN4
VAIN
0011
(Input Voltage)
10-bit
Converter
A/D
AN3
0010
AN2
0001
VCFG1:VCFG0
AN1
0000
AN0
VDD
VREF+
VREF-
Reference
Voltage
VSS
Note 1: Channels AN15 through AN12 are not available on PIC18F6X2X devices.
2: I/O pins have diode protection to VDD and VSS.
DS39612A-page 238
Advance Information
2003 Microchip Technology Inc.
PIC18F6X2X/8X2X
The value in the ADRESH/ADRESL registers is
not modified for Power-on Reset. The
2. Configure A/D interrupt (if desired):
• Clear ADIF bit
a
ADRESH/ADRESL registers will contain unknown data
after a Power-on Reset.
• Set ADIE bit
• Set GIE bit
After the A/D module has been configured as desired,
the selected channel must be acquired before the con-
version is started. The analog input channels must
have their corresponding TRIS bits selected as an
input. To determine acquisition time, see Section 20.1.
After this acquisition time has elapsed, the A/D
conversion can be started.
3. Wait the required acquisition time (not required
in case of auto-acquisition time).
4. Start conversion:
• Set GO/DONE bit (ADCON0 register)
5. Wait for A/D conversion to complete, by either:
• Polling for the GO/DONE bit to be cleared
OR
The following steps should be followed to do an A/D
conversion:
• Waiting for the A/D interrupt
6. Read A/D Result registers (ADRESH:ADRESL);
clear bit ADIF, if required.
1. Configure the A/D module:
• Configure analog pins, voltage reference and
digital I/O (ADCON1)
• Select A/D input channel (ADCON0)
• Select A/D conversion clock (ADCON2)
• Turn on A/D module (ADCON0)
7. For next conversion, go to step 1 or step 2, as
required. The A/D conversion time per bit is
defined as TAD. A minimum wait of 2 TAD is
required before next acquisition starts.
FIGURE 20-2:
ANALOG INPUT MODEL
VDD
Sampling
Switch
VT = 0.6V
ANx
SS
RIC ≤ 1k
RSS
Rs
CPIN
I leakage
± 500 nA
VAIN
CHOLD = 120 pF
VT = 0.6V
5 pF
VSS
Legend: CPIN
VT
= input capacitance
= threshold voltage
6V
5V
VDD 4V
3V
I LEAKAGE = leakage current at the pin due to
various junctions
RIC
= interconnect resistance
= sampling switch
2V
SS
CHOLD
RSS
= sample/hold capacitance (from DAC)
= sampling switch resistance
5
6
7
8 9 10 11
Sampling Switch ( kΩ )
2003 Microchip Technology Inc.
Advance Information
DS39612A-page 239
PIC18F6X2X/8X2X
To calculate the minimum acquisition time,
Equation 20-1 may be used. This equation assumes
that 1/2 LSb error is used (1024 steps for the A/D). The
1/2 LSb error is the maximum error allowed for the A/D
to meet its specified resolution.
20.1 A/D Acquisition Requirements
For the A/D converter to meet its specified accuracy,
the charge holding capacitor (CHOLD) must be allowed
to fully charge to the input channel voltage level. The
analog input model is shown in Figure 20-2. The
source impedance (RS) and the internal sampling
switch (RSS) impedance directly affect the time
required to charge the capacitor CHOLD. The sampling
switch (RSS) impedance varies over the device voltage
(VDD). The source impedance affects the offset voltage
at the analog input (due to pin leakage current). The
maximum recommended impedance for analog
sources is 2.5 kΩ. After the analog input channel is
selected (changed), this acquisition must be done
before the conversion can be started.
Example 20-1 shows the calculation of the minimum
required acquisition time, TACQ. This calculation is
based on the following application system
assumptions:
CHOLD
Rs
Conversion Error
VDD
Temperature
VHOLD
=
=
≤
=
=
=
120 pF
2.5 kΩ
1/2 LSb
5V → Rss = 7 kΩ
50°C (system max.)
0V @ time = 0
Note:
When the conversion is started, the hold-
ing capacitor is disconnected from the
input pin.
EQUATION 20-1: ACQUISITION TIME
TACQ
=
=
Amplifier Settling Time + Holding Capacitor Charging Time + Temperature Coefficient
TAMP + TC + TCOFF
EQUATION 20-2: A/D MINIMUM CHARGING TIME
VHOLD
or
Tc
=
=
(VREF – (VREF/2048)) • (1 – e(-Tc/CHOLD(RIC + RSS + RS))
)
-(120 pF)(1 kΩ + RSS + RS) ln(1/2047)
EXAMPLE 20-1:
CALCULATING THE MINIMUM REQUIRED ACQUISITION TIME
TACQ
=
TAMP + TC + TCOFF
Temperature coefficient is only required for temperatures > 25°C.
TACQ
TC
=
=
2 µs + TC + [(Temp – 25°C)(0.05 µs/°C)]
-CHOLD (RIC + RSS + RS) ln(1/2047)
-120 pF (1 kΩ + 7 kΩ + 2.5 kΩ) ln(0.0004885)
-120 pF (10.5 kΩ) ln(0.0004885)
-1.26 µs (-7.6241)
9.61 µs
TACQ
=
2 µs + 9.61 µs + [(50°C – 25°C)(0.05 µs/°C)]
11.61 µs + 1.25 µs
12.86 µs
DS39612A-page 240
Advance Information
2003 Microchip Technology Inc.
PIC18F6X2X/8X2X
20.2 Selecting the A/D Conversion
Clock
20.4 A/D Conversions
Figure 20-3 shows the operation of the A/D converter
after the GO bit has been set. Clearing the GO/DONE
bit during a conversion will abort the current conver-
sion. The A/D result register pair will NOT be updated
with the partially completed A/D conversion sample.
That is, the ADRESH:ADRESL registers will continue
to contain the value of the last completed conversion
(or the last value written to the ADRESH:ADRESL reg-
isters). After the A/D conversion is aborted, a 2 TAD wait
is required before the next acquisition is started. After
this 2 TAD wait, acquisition on the selected channel is
automatically started.
The A/D conversion time per bit is defined as TAD. The
A/D conversion requires 12 TAD per 10-bit conversion.
The source of the A/D conversion clock is software
selectable. There are seven possible options for TAD:
• 2 TOSC
• 4 TOSC
• 8 TOSC
• 16 TOSC
• 32 TOSC
• 64 TOSC
Note:
The GO/DONE bit should NOT be set in
• Internal RC oscillator
the same instruction that turns on the A/D.
For correct A/D conversions, the A/D conversion clock
(TAD) must be selected to ensure a minimum TAD time
of 1.6 µs.
20.5 Use of the ECCP2 Trigger
Table 20-1 shows the resultant TAD times derived from
the device operating frequencies and the A/D clock
source selected.
An A/D conversion can be started by the special event
trigger of the ECCP2 module. This requires that the
CCP2M3:CCP2M0 bits (CCP2CON<3:0>) be pro-
grammed as ‘1011’ and that the A/D module is enabled
(ADON bit is set). When the trigger occurs, the
GO/DONE bit will be set, starting the A/D conversion,
and the Timer1 (or Timer3) counter will be reset to zero.
Timer1 (or Timer3) is reset to automatically repeat the
A/D acquisition period with minimal software overhead
(moving ADRESH/ADRESL to the desired location).
The appropriate analog input channel must be selected
and the minimum acquisition done before the special
event trigger sets the GO/DONE bit and starts a
conversion.
20.3 Configuring Analog Port Pins
The ADCON1, TRISA, TRISF and TRISH registers con-
trol the operation of the A/D port pins. The port pins
needed as analog inputs must have their corresponding
TRIS bits set (input). If the TRIS bit is cleared (output),
the digital output level (VOH or VOL) will be converted.
The A/D operation is independent of the state of the
CHS3:CHS0 bits and the TRIS bits.
Note 1: When reading the port register, all pins
configured as analog input channels will
read as cleared (a low level). Pins config-
ured as digital inputs will convert an ana-
log input. Analog levels on a digitally
configured input will not affect the
conversion accuracy.
If the A/D module is not enabled (ADON is cleared), the
special event trigger will be ignored by the A/D module
but will still reset the Timer1 (or Timer3) counter.
2: Analog levels on any pin defined as a dig-
ital input may cause the input buffer to
consume current out of the device’s
specification limits.
TABLE 20-1: TAD vs. DEVICE OPERATING FREQUENCIES
AD Clock Source (TAD)
Maximum Device Frequency
PIC18F6X2X/8X2X
Operation
ADCS2:ADCS0
2 TOSC
4 TOSC
8 TOSC
16 TOSC
32 TOSC
64 TOSC
RC
000
100
001
101
010
110
x11
1.25 MHz
2.50 MHz
5.00 MHz
10.0 MHz
20.0 MHz
40.0 MHz
—
2003 Microchip Technology Inc.
Advance Information
DS39612A-page 241
PIC18F6X2X/8X2X
FIGURE 20-3:
A/D CONVERSION TAD CYCLES
TCY - TAD
TAD6 TAD7 TAD8 TAD9 TAD10 TAD11
TAD1 TAD2 TAD3 TAD4 TAD5
b5
b4
b3
b2
b1
b0
b0
b7
b6
b8
b9
Conversion starts
Holding capacitor is disconnected from analog input (typically 100 ns)
Set GO bit
Next Q4: ADRESH/ADRESL is loaded, GO bit is cleared,
ADIF bit is set, holding capacitor is connected to analog input.
TABLE 20-2: SUMMARY OF A/D REGISTERS
Value on
all other
RESETS
Value on
POR, BOR
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
INTCON
GIE/
GIEH
PEIE/
GIEL
TMR0IE INT0IE
RBIE
TMR0IF
INT0IF
RBIF
0000 0000
0000 0000
PIR1
PSPIF
PSPIE
PSPIP
—
ADIF
ADIE
ADIP
CMIF
CMIE
CMIP
RCIF
RCIE
RCIP
—
TXIF
TXIE
TXIP
—
SSPIF CCP1IF
SSPIE CCP1IE
SSPIP CCP1IP
TMR2IF
TMR2IE
TMR2IP
TMR3IF
TMR3IE
TMR3IP
TMR1IF 0000 0000
TMR1IE 0000 0000
TMR1IP 1111 1111
CCP2IF -0-- 0000
CCP2IE -0-- 0000
CCP2IP -0-- 0000
xxxx xxxx
0000 0000
0000 0000
1111 1111
-0-- 0000
-0-- 0000
-0-- 0000
uuuu uuuu
uuuu uuuu
--00 0000
--00 0000
0--- -000
--0u 0000
--11 1111
u000 0000
uuuu uuuu
1111 1111
0000 xxxx
uuuu uuuu
1111 1111
PIE1
IPR1
PIR2
BCLIF
BCLIE
BCLIP
LVDIF
LVDIE
LVDIP
PIE2
—
—
—
IPR2
—
—
—
ADRESH
ADRESL
ADCON0
ADCON1
ADCON2
PORTA
TRISA
PORTF
LATF
A/D Result Register High Byte
A/D Result Register Low Byte
xxxx xxxx
—
—
—
—
CHS3
CHS3
CHS1
CHS0
GO/DONE
PCFG1
ADCS1
RA1
ADON
PCFG0
ADCS0
RA0
--00 0000
--00 0000
0--- -000
--0x 0000
--11 1111
x000 0000
xxxx xxxx
1111 1111
0000 xxxx
xxxx xxxx
1111 1111
VCFG1 VCFG0 PCFG3 PCFG2
ACQT2 ACQT1 ACQT0 ADCS2
ADFM
—
—
RA6
RA5
RA4
RA3
RA2
—
PORTA Data Direction Register
RF7
LATF7
RF6
RF5
RF4
RF3
RF2
RF1
RF0
LATF6
LATF5
LATF4
LATF3
LATF2
LATF1
LATF0
TRISF
PORTF Data Direction Control Register
(1)
PORTH
RH7
RH6
RH5
RH4
RH3
RH2
RH1
RH0
(1)
LATH
LATH7
LATH6
LATH5
LATH4 LATH3
LATH2
LATH1
LATH0
(1)
TRISH
PORTH Data Direction Control Register
Legend:
x= unknown, u= unchanged, - = unimplemented, read as ‘0’. Shaded cells are not used for A/D conversion.
Note 1: Implemented on PIC18F8X2X devices only.
DS39612A-page 242
Advance Information
2003 Microchip Technology Inc.
PIC18F6X2X/8X2X
The CMCON register, shown as Register 21-1, con-
trols the comparator input and output multiplexers. A
block diagram of the various comparator configurations
is shown in Figure 21-1.
21.0 COMPARATOR MODULE
The comparator module contains two analog compara-
tors. The inputs to the comparators are multiplexed
with the RF1 through RF6 pins. The on-chip Voltage
Reference (Section 22.0) can also be an input to the
comparators.
REGISTER 21-1: CMCON REGISTER
R-0
R-0
R/W-0
C2INV
R/W-0
C1INV
R/W-0
CIS
R/W-0
CM2
R/W-0
CM1
R/W-0
CM0
C2OUT
C1OUT
bit 7
bit 0
bit 7
C2OUT: Comparator 2 Output bit
When C2INV = 0:
1= C2 VIN+ > C2 VIN-
0= C2 VIN+ < C2 VIN-
When C2INV = 1:
1= C2 VIN+ < C2 VIN-
0= C2 VIN+ > C2 VIN-
bit 6
C1OUT: Comparator 1 Output bit
When C1INV = 0:
1= C1 VIN+ > C1 VIN-
0= C1 VIN+ < C1 VIN-
When C1INV = 1:
1= C1 VIN+ < C1 VIN-
0= C1 VIN+ > C1 VIN-
bit 5
bit 4
bit 3
C2INV: Comparator 2 Output Inversion bit
1= C2 output inverted
0= C2 output not inverted
C1INV: Comparator 1 Output Inversion bit
1= C1 output inverted
0= C1 output not inverted
CIS: Comparator Input Switch bit
When CM2:CM0 = 110:
1= C1 VIN- connects to RF5/AN10
C2 VIN- connects to RF3/AN8
0= C1 VIN- connects to RF6/AN11
C2 VIN- connects to RF4/AN9
bit 2-0
CM2:CM0: Comparator Mode bits
Figure 21-1 shows the Comparator modes and CM2:CM0 bit settings.
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
- n = Value at POR
2003 Microchip Technology Inc.
Advance Information
DS39612A-page 243
PIC18F6X2X/8X2X
mode is changed, the comparator output level may not
be valid for the specified mode change delay shown in
Section 27.0, Electrical Specifications.
21.1 Comparator Configuration
There are eight modes of operation for the compara-
tors. The CMCON register is used to select these
modes. Figure 21-1 shows the eight possible modes.
The TRISF register controls the data direction of the
comparator pins for each mode. If the Comparator
Note:
Comparator interrupts should be disabled
during Comparator mode change.
Otherwise, a false interrupt may occur.
a
FIGURE 21-1:
COMPARATOR I/O OPERATING MODES
Comparators Reset (POR Default Value)
Comparators Off
CM2:CM0 = 000
CM2:CM0 = 111
A
D
VIN-
VIN-
RF6/AN11
RF5/AN10
RF6/AN11
Off (Read as ‘0’)
Off (Read as ‘0’)
Off (Read as ‘0’)
Off (Read as ‘0’)
C1
C2
C1
C2
VIN+
VIN+
A
D
RF5/AN10
A
A
D
VIN-
VIN-
RF4/AN9
RF3/AN8
RF4/AN9
VIN+
VIN+
D
RF3/AN8
Two Independent Comparators with Outputs
CM2:CM0 = 011
Two Independent Comparators
CM2:CM0 = 010
A
VIN-
A
VIN-
RF6/AN11
RF5/AN10
RF6/AN11
RF5/AN10
C1OUT
C2OUT
C1
C2
VIN+
A
C1OUT
C2OUT
C1
C2
VIN+
A
RF2/AN7/C1OUT
A
A
VIN-
A
VIN-
RF4/AN9
RF3/AN8
RF4/AN9
VIN+
VIN+
A
RF3/AN8
RF1/AN6/C2OUT
Two Common Reference Comparators
Two Common Reference Comparators with Outputs
CM2:CM0 = 100
CM2:CM0 = 101
A
A
VIN-
VIN-
RF6/AN11
RF5/AN10
RF6/AN11
RF5/AN10
C1OUT
C2OUT
C1OUT
C1
C2
C1
C2
VIN+
VIN+
A
A
RF2/AN7/C1OUT
A
D
VIN-
RF4/AN9
RF3/AN8
A
VIN-
VIN+
RF4/AN9
C2OUT
VIN+
D
RF3/AN8
RF1/AN6/C2OUT
Four Inputs Multiplexed to Two Comparators
One Independent Comparator with Output
CM2:CM0 = 110
CM2:CM0 = 001
A
A
A
VIN-
RF6/AN11
RF6/AN11
RF5/AN10
CIS = 0
CIS = 1
VIN-
A
C1OUT
C1
C2
VIN+
RF5/AN10
C1OUT
C2OUT
C1
C2
VIN+
RF2/AN7/C1OUT
A
A
RF4/AN9
RF3/AN8
VIN-
CIS = 0
CIS = 1
VIN+
D
VIN-
RF4/AN9
Off (Read as ‘0’)
VIN+
D
RF3/AN8
CVREF
From VREF Module
A = Analog Input, port reads zeros always
DS39612A-page 244
D = Digital Input
CIS (CMCON<3>) is the Comparator Input Switch
Advance Information
2003 Microchip Technology Inc.
PIC18F6X2X/8X2X
21.3.2
INTERNAL REFERENCE SIGNAL
21.2 Comparator Operation
The comparator module also allows the selection of an
internally generated voltage reference for the
A single comparator is shown in Figure 21-2, along with
the relationship between the analog input levels and
the digital output. When the analog input at VIN+ is less
than the analog input VIN-, the output of the comparator
is a digital low level. When the analog input at VIN+ is
greater than the analog input VIN-, the output of the
comparator is a digital high level. The shaded areas of
the output of the comparator in Figure 21-2 represent
the uncertainty due to input offsets and response time.
comparators. Section 22.0 contains
a
detailed
description of the comparator voltage reference
module that provides this signal. The internal reference
signal is used when comparators are in mode
CM<2:0> = 110 (Figure 21-1). In this mode, the
internal voltage reference is applied to the VIN+ pin of
both comparators.
21.4 Comparator Response Time
21.3 Comparator Reference
Response time is the minimum time, after selecting a
new reference voltage or input source, before the
comparator output has a valid level. If the internal ref-
erence is changed, the maximum delay of the internal
voltage reference must be considered when using the
comparator outputs. Otherwise, the maximum delay of
the comparators should be used (Section 27.0).
An external or internal reference signal may be used
depending on the comparator operating mode. The
analog signal present at VIN- is compared to the signal
at VIN+, and the digital output of the comparator is
adjusted accordingly (Figure 21-2).
FIGURE 21-2:
SINGLE COMPARATOR
21.5 Comparator Outputs
VIN+
VIN-
+
The comparator outputs are read through the CMCON
register. These bits are read only. The comparator
outputs may also be directly output to the RF1 and RF2
I/O pins. When enabled, multiplexors in the output path
of the RF1 and RF2 pins will switch and the output of
each pin will be the unsynchronized output of the com-
parator. The uncertainty of each of the comparators is
related to the input offset voltage and the response time
given in the specifications. Figure 21-3 shows the
comparator output block diagram.
Output
–
VIN-
VIN+
The TRISA bits will still function as an output enable/
disable for the RF1 and RF2 pins while in this mode.
The polarity of the comparator outputs can be changed
using the C2INV and C1INV bits (CMCON<4:5>).
Output
Note 1: When reading the Port register, all pins
configured as analog inputs will read as a
‘0’. Pins configured as digital inputs will
convert an analog input according to the
Schmitt Trigger input specification.
21.3.1
EXTERNAL REFERENCE SIGNAL
When external voltage references are used, the
comparator module can be configured to have the com-
parators operate from the same, or different reference
sources. However, threshold detector applications may
require the same reference. The reference signal must
be between VSS and VDD and can be applied to either
pin of the comparator(s).
2: Analog levels on any pin defined as a dig-
ital input may cause the input buffer to
consume more current than is specified.
2003 Microchip Technology Inc.
Advance Information
DS39612A-page 245
PIC18F6X2X/8X2X
FIGURE 21-3:
COMPARATOR OUTPUT BLOCK DIAGRAM
Port Pins
MULTIPLEX
+
-
CxINV
To RF1 or
RF2 Pin
Bus
Data
Q
D
Read CMCON
EN
Q
Set
CMIF
bit
D
From
Other
Comparator
EN
CL
Read CMCON
RESET
21.6 Comparator Interrupts
Note:
If a change in the CMCON register
(C1OUT or C2OUT) should occur when a
read operation is being executed (start of
the Q2 cycle), then the CMIF (PIR
registers) interrupt flag may not get set.
The comparator interrupt flag is set whenever there is
a change in the output value of either comparator.
Software will need to maintain information about the
status of the output bits, as read from CMCON<7:6>, to
determine the actual change that occurred. The CMIF
bit (PIR registers) is the comparator interrupt flag. The
CMIF bit must be reset by clearing ‘0’. Since it is also
possible to write a ‘1’ to this register, a simulated
interrupt may be initiated.
The user, in the Interrupt Service Routine, can clear the
interrupt in the following manner:
a) Any read or write of CMCON will end the
mismatch condition.
b) Clear flag bit CMIF.
The CMIE bit (PIE registers) and the PEIE bit (INTCON
register) must be set to enable the interrupt. In addition,
the GIE bit must also be set. If any of these bits are
clear, the interrupt is not enabled, though the CMIF bit
will still be set if an interrupt condition occurs.
A mismatch condition will continue to set flag bit CMIF.
Reading CMCON will end the mismatch condition and
allow flag bit CMIF to be cleared.
DS39612A-page 246
Advance Information
2003 Microchip Technology Inc.
PIC18F6X2X/8X2X
21.7 Comparator Operation During
SLEEP
21.9 Analog Input Connection
Considerations
When a comparator is active and the device is placed
in SLEEP mode, the comparator remains active and
the interrupt is functional if enabled. This interrupt will
wake-up the device from SLEEP mode when enabled.
While the comparator is powered up, higher SLEEP
currents than shown in the power-down current
specification will occur. Each operational comparator
will consume additional current, as shown in the com-
parator specifications. To minimize power consumption
while in SLEEP mode, turn off the comparators,
CM<2:0> = 111, before entering SLEEP. If the device
wakes up from SLEEP, the contents of the CMCON
register are not affected.
A simplified circuit for an analog input is shown in
Figure 21-4. Since the analog pins are connected to a
digital output, they have reverse biased diodes to VDD
and VSS. The analog input, therefore, must be between
VSS and VDD. If the input voltage deviates from this
range by more than 0.6V in either direction, one of the
diodes is forward biased and a latchup condition may
occur. A maximum source impedance of 10 kΩ is
recommended for the analog sources. Any external
component connected to an analog input pin, such as
a capacitor or a Zener diode, should have very little
leakage current.
21.8 Effects of a RESET
A device RESET forces the CMCON register to its
RESET state, causing the comparator module to be in
the comparator RESET mode, CM<2:0> = 000. This
ensures that all potential inputs are analog inputs.
Device current is minimized when analog inputs are
present at RESET time. The comparators will be
powered down during the RESET interval.
FIGURE 21-4:
COMPARATOR ANALOG INPUT MODEL
VDD
VT = 0.6V
RIC
RS < 10k
AIN
Comparator
Input
ILEAKAGE
±500 nA
CPIN
5 pF
VA
VT = 0.6V
VSS
Legend:
CPIN
VT
=
=
Input Capacitance
Threshold Voltage
ILEAKAGE = Leakage Current at the pin due to various junctions
RIC
RS
VA
=
=
=
Interconnect Resistance
Source Impedance
Analog Voltage
2003 Microchip Technology Inc.
Advance Information
DS39612A-page 247
PIC18F6X2X/8X2X
TABLE 21-1: REGISTERS ASSOCIATED WITH COMPARATOR MODULE
Value on
all other
RESETS
Value on
POR
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
CMCON C2OUT C1OUT C2INV C1INV
CIS
CM2
CM1
CM0
0000 0000 0000 0000
CVRCON CVREN CVROE CVRR CVRSS CVR3
CVR2
CVR1
CVR0 0000 0000 0000 0000
RBIF 0000 0000 0000 0000
INTCON
GIE/
PEIE/ TMR0IE INT0IE
GIEL
RBIE TMR0IF INT0IF
GIEH
PIR2
—
—
CMIF
CMIE
CMIP
RF6
—
—
—
—
BCLIF
BCLIE
BCLIP
RF3
LVDIF TMR3IF CCP2IF -0-- 0000 -0-- 0000
LVDIE TMR3IE CCP2IE -0-- 0000 -0-- 0000
LVDIP TMR3IP CCP2IP -1-- 1111 -1-- 1111
PIE2
IPR2
—
—
—
PORTF
LATF
TRISF
RF7
RF5
RF4
RF2
RF1
LATF1 LATF0 xxxx xxxx uuuu uuuu
TRISF7 TRISF6 TRISF5 TRISF4 TRISF3 TRISF2 TRISF1 TRISF0 1111 1111 1111 1111
RF0
x000 0000 u000 0000
LATF7 LATF6 LATF5 LATF4 LATF3 LATF2
Legend: x= unknown, u= unchanged, - = unimplemented, read as ‘0’.
Shaded cells are unused by the comparator module.
DS39612A-page 248
Advance Information
2003 Microchip Technology Inc.
PIC18F6X2X/8X2X
22.1 Configuring the Comparator
Voltage Reference
22.0 COMPARATOR VOLTAGE
REFERENCE MODULE
The comparator voltage reference can output 16
distinct voltage levels for each range. The equations
used to calculate the output of the comparator voltage
reference are as follows:
The comparator voltage reference is a 16-tap resistor
ladder network that provides a selectable voltage refer-
ence. The resistor ladder is segmented to provide two
ranges of CVREF values and has a power-down func-
tion to conserve power when the reference is not being
used. The CVRCON register controls the operation of
the reference as shown in Register 22-1. The block
diagram is given in Figure 22-1.
If CVRR = 1:
CVREF = (CVR<3:0>/24) x CVRSRC
If CVRR = 0:
CVREF = (CVDD x 1/4) + (CVR<3:0>/32) x CVRSRC
The comparator reference supply voltage can come
from either VDD and VSS, or the external VREF+ and
VREF- that are multiplexed with RA3 and RA2. The
comparator reference supply voltage is controlled by
the CVRSS bit.
The settling time of the comparator voltage reference
must be considered when changing the CVREF output
(Section 27.0).
REGISTER 22-1:
CVRCON REGISTER
R/W-0 R/W-0
CVREN CVROE(1)
bit 7
R/W-0
CVRR
R/W-0
R/W-0
CVR3
R/W-0
CVR2
R/W-0
CVR1
R/W-0
CVR0
CVRSS
bit 0
bit 7
bit 6
CVREN: Comparator Voltage Reference Enable bit
1= CVREF circuit powered on
0= CVREF circuit powered down
CVROE: Comparator VREF Output Enable bit(1)
1= CVREF voltage level is also output on the RF5/AN10/CVREF pin
0= CVREF voltage is disconnected from the RF5/AN10/CVREF pin
Note 1: If enabled for output, RF5 must also be configured as an input by setting TRISF<5>
to ‘1’.
bit 5
CVRR: Comparator VREF Range Selection bit
1= 0.00 CVRSRC to 0.75 CVRSRC, with CVRSRC/24 step size
0= 0.25 CVRSRC to 0.75 CVRSRC, with CVRSRC/32 step size
bit 4
CVRSS: Comparator VREF Source Selection bit
1= Comparator reference source CVRSRC = VREF+ – VREF-
0= Comparator reference source CVRSRC = VDD – VSS
bit 3-0
CVR3:CVR0: Comparator VREF Value Selection bits (0 ≤ VR3:VR0 ≤ 15)
When CVRR = 1:
CVREF = (CVR<3:0>/ 24) • (CVRSRC)
When CVRR = 0:
CVREF = 1/4 • (CVRSRC) + (CVR3:CVR0/32) • (CVRSRC)
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
- n = Value at POR
2003 Microchip Technology Inc.
Advance Information
DS39612A-page 249
PIC18F6X2X/8X2X
FIGURE 22-1:
VOLTAGE REFERENCE BLOCK DIAGRAM
VDD
VREF+
16 Stages
CVRSS = 1
CVRSS = 0
CVREN
R
R
R
8R
R
CVRR
CVRSS = 0
8R
CVRSS = 1
VREF-
CVR3
CVREF
(From CVRCON<3:0>)
CVR0
16-1 Analog Mux
Note: R is defined in Section 27.0.
22.2 Voltage Reference Accuracy/Error
22.4 Effects of a RESET
The full range of voltage reference cannot be realized
due to the construction of the module. The transistors
on the top and bottom of the resistor ladder network
(Figure 22-1) keep CVREF from approaching the refer-
ence source rails. The voltage reference is derived
from the reference source; therefore, the CVREF output
changes with fluctuations in that source. The tested
absolute accuracy of the voltage reference can be
found in Section 27.0.
A device RESET disables the voltage reference by
clearing bit CVREN (CVRCON<7>). This RESET also
disconnects the reference from the RA2 pin by clearing
bit CVROE (CVRCON<6>) and selects the high volt-
age range by clearing bit CVRR (CVRCON<5>). The
VRSS value select bits, CVRCON<3:0>, are also
cleared.
22.5 Connection Considerations
The voltage reference module operates independently
of the comparator module. The output of the reference
generator may be connected to the RF5 pin if the
TRISF<5> bit is set and the CVROE bit is set. Enabling
the voltage reference output onto the RF5 pin with an
input signal present will increase current consumption.
Connecting RF5 as a digital output with VRSS enabled
will also increase current consumption.
22.3 Operation During SLEEP
When the device wakes up from SLEEP through an
interrupt or a Watchdog Timer time-out, the contents of
the CVRCON register are not affected. To minimize
current consumption in SLEEP mode, the voltage
reference should be disabled.
The RF5 pin can be used as a simple D/A output with
limited drive capability. Due to the limited current drive
capability, a buffer must be used on the voltage refer-
ence output for external connections to VREF.
Figure 22-2 shows an example buffering technique.
DS39612A-page 250
Advance Information
2003 Microchip Technology Inc.
PIC18F6X2X/8X2X
FIGURE 22-2:
VOLTAGE REFERENCE OUTPUT BUFFER EXAMPLE
(1)
RF5
R
CVREF
+
–
Module
CVREF Output
Voltage
Reference
Output
Impedance
Note 1: R is dependent upon the voltage reference configuration bits CVRCON<3:0> and CVRCON<5>.
TABLE 22-1: REGISTERS ASSOCIATED WITH COMPARATOR VOLTAGE REFERENCE
Value on
Value on
all other
RESETS
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
POR
CVRCON CVREN CVROE CVRR CVRSS CVR3
CVR2
CM2
CVR1
CM1
CVR0 0000 0000 0000 0000
CM0 0000 0000 0000 0000
CMCON
TRISF
C2OUT C1OUT C2INV C1INV
CIS
TRISF7 TRISF6 TRISF5 TRISF4 TRISF3 TRISF2 TRISF1 TRISF0 1111 1111 1111 1111
Legend: x= unknown, u= unchanged, - = unimplemented, read as ‘0’.
Shaded cells are not used with the comparator voltage reference.
2003 Microchip Technology Inc.
Advance Information
DS39612A-page 251
PIC18F6X2X/8X2X
NOTES:
DS39612A-page 252
Advance Information
2003 Microchip Technology Inc.
PIC18F6X2X/8X2X
The Low Voltage Detect circuitry is completely under
software control. This allows the circuitry to be “turned
off” by the software which minimizes the current
consumption for the device.
23.0 LOW VOLTAGE DETECT
In many applications, the ability to determine if the
device voltage (VDD) is below a specified voltage level
is a desirable feature. A window of operation for the
application can be created, where the application soft-
ware can do “housekeeping tasks” before the device
voltage exits the valid operating range. This can be
done using the Low Voltage Detect module.
Figure 23-1 shows a possible application voltage curve
(typically for batteries). Over time, the device voltage
decreases. When the device voltage equals voltage VA,
the LVD logic generates an interrupt. This occurs at
time TA. The application software then has the time,
until the device voltage is no longer in valid operating
range, to shutdown the system. Voltage point VB is the
minimum valid operating voltage specification. This
occurs at time TB. The difference TB – TA is the total
time for shut-down.
This module is a software programmable circuitry,
where a device voltage trip point can be specified.
When the voltage of the device becomes lower then the
specified point, an interrupt flag is set. If the interrupt is
enabled, the program execution will branch to the inter-
rupt vector address and the software can then respond
to that interrupt source.
FIGURE 23-1:
TYPICAL LOW VOLTAGE DETECT APPLICATION
VA
VB
Legend:
VA = LVD trip point
VB = Minimum valid device
operating voltage
TB
TA
Time
The block diagram for the LVD module is shown in
Figure 23-2. A comparator uses an internally gener-
ated reference voltage as the set point. When the
selected tap output of the device voltage crosses the
set point (is lower than), the LVDIF bit is set.
supply voltage is equal to the trip point, the voltage
tapped off of the resistor array is equal to the 1.2V
internal reference voltage generated by the voltage
reference module. The comparator then generates an
interrupt signal setting the LVDIF bit. This voltage is
software programmable to any one of 16 values (see
Figure 23-2). The trip point is selected by
programming the LVDL3:LVDL0 bits (LVDCON<3:0>).
Each node in the resistor divider represents a “trip
point” voltage. The “trip point” voltage is the minimum
supply voltage level at which the device can operate
before the LVD module asserts an interrupt. When the
2003 Microchip Technology Inc.
Advance Information
DS39612A-page 253
PIC18F6X2X/8X2X
FIGURE 23-2:
LOW VOLTAGE DETECT (LVD) BLOCK DIAGRAM
VDD
LVDIN
LVD3:LVD0
LVDCON
Register
LVDIF
Internally Generated
LVDEN
Reference Voltage
(Parameter #D423)
The LVD module has an additional feature that allows
the user to supply the trip voltage to the module from
an external source. This mode is enabled when bits
LVDL3:LVDL0 are set to ‘1111’. In this state, the com-
parator input is multiplexed from the external input pin,
LVDIN (Figure 23-3). This gives users flexibility
because it allows them to configure the Low Voltage
Detect interrupt to occur at any voltage in the valid
operating range.
FIGURE 23-3:
LOW VOLTAGE DETECT (LVD) WITH EXTERNAL INPUT BLOCK DIAGRAM
VDD
VDD
LVD3:LVD0
LVDCON
Register
LVDIN
LVDEN
Externally Generated
Trip Point
LVD
VxEN
BODEN
EN
BGAP
DS39612A-page 254
Advance Information
2003 Microchip Technology Inc.
PIC18F6X2X/8X2X
23.1 Control Register
The
Low
Voltage
Detect
Control
register
(Register 23-1) controls the operation of the Low
Voltage Detect circuitry.
REGISTER 23-1: LVDCON REGISTER
U-0
—
U-0
—
R-0
R/W-0
R/W-0
LVDL3
R/W-1
LVDL2
R/W-0
LVDL1
R/W-1
LVDL0
IRVST
LVDEN
bit 7
bit 0
bit 7-6 Unimplemented: Read as ‘0’
bit 5
bit 4
IRVST: Internal Reference Voltage Stable Flag bit
1= Indicates that the Low Voltage Detect logic will generate the interrupt flag at the specified
voltage range
0= Indicates that the Low Voltage Detect logic will not generate the interrupt flag at the
specified voltage range and the LVD interrupt should not be enabled
LVDEN: Low Voltage Detect Power Enable bit
1= Enables LVD, powers up LVD circuit
0= Disables LVD, powers down LVD circuit
bit 3-0 LVDL3:LVDL0: Low Voltage Detection Limit bits
1111= External analog input is used (input comes from the LVDIN pin)
1110= 4.45V - 4.83V
1101= 4.16V - 4.5V
1100= 3.96V - 4.3V
1011= 3.76V - 3.92V
1010= 3.57V - 3.87V
1001= 3.47V - 3.75V
1000= 3.27V - 3.55V
0111= 2.98V - 3.22V
0110= 2.77V - 3.01V
0101= 2.67V - 2.89V
0100= 2.48V - 2.68V
0011= 2.37V - 2.57V
0010= 2.18V - 2.36V
0001= 1.98V - 2.14V
0000= Reserved
Note:
LVDL3:LVDL0 modes, which result in a trip point below the valid operating voltage
of the device, are not tested.
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
- n = Value at POR
2003 Microchip Technology Inc.
Advance Information
DS39612A-page 255
PIC18F6X2X/8X2X
The following steps are needed to set up the LVD
module:
23.2 Operation
Depending on the power source for the device voltage,
the voltage normally decreases relatively slowly. This
means that the LVD module does not need to be con-
stantly operating. To decrease the current require-
ments, the LVD circuitry only needs to be enabled for
short periods where the voltage is checked. After doing
the check, the LVD module may be disabled.
1. Write the value to the LVDL3:LVDL0 bits
(LVDCON register) which selects the desired
LVD trip point.
2. Ensure that LVD interrupts are disabled (the
LVDIE bit is cleared or the GIE bit is cleared).
3. Enable the LVD module (set the LVDEN bit in
the LVDCON register).
Each time that the LVD module is enabled, the circuitry
requires some time to stabilize. After the circuitry has
stabilized, all status flags may be cleared. The module
will then indicate the proper state of the system.
4. Wait for the LVD module to stabilize (the IRVST
bit to become set).
5. Clear the LVD interrupt flag, which may have
falsely become set, until the LVD module has
stabilized (clear the LVDIF bit).
6. Enable the LVD interrupt (set the LVDIE and the
GIE bits).
Figure 23-4 shows typical waveforms that the LVD
module may be used to detect.
FIGURE 23-4:
LOW VOLTAGE DETECT WAVEFORMS
CASE 1:
LVDIF may not be set
VDD
VLVD
LVDIF
Enable LVD
Internally Generated
Reference Stable
TIVRST
LVDIF cleared in software
CASE 2:
VDD
VLVD
LVDIF
Enable LVD
TIVRST
Internally Generated
Reference Stable
LVDIF cleared in software
LVDIF cleared in software,
LVDIF remains set since LVD condition still exists
DS39612A-page 256
Advance Information
2003 Microchip Technology Inc.
PIC18F6X2X/8X2X
23.2.1
REFERENCE VOLTAGE SET POINT
23.3 Operation During SLEEP
The internal reference voltage of the LVD module, spec-
ified in electrical specification parameter #D423, may be
used by other internal circuitry (the Programmable
Brown-out Reset). If these circuits are disabled (lower
current consumption), the reference voltage circuit
requires a time to become stable before a low voltage
condition can be reliably detected. This time is invariant
of system clock speed. This start-up time is specified in
electrical specification parameter #36. The low voltage
interrupt flag will not be enabled until a stable reference
voltage is reached. Refer to the waveform in Figure 23-4.
When enabled, the LVD circuitry continues to operate
during SLEEP. If the device voltage crosses the trip
point, the LVDIF bit will be set and the device will
wake-up from SLEEP. Device execution will continue
from the interrupt vector address if interrupts have
been globally enabled.
23.4 Effects of a RESET
A device RESET forces all registers to their RESET
state. This forces the LVD module to be turned off.
23.2.2
CURRENT CONSUMPTION
When the module is enabled, the LVD comparator and
voltage divider are enabled and will consume static cur-
rent. The voltage divider can be tapped from multiple
places in the resistor array. Total current consumption,
when enabled, is specified in electrical specification
parameter #D022B.
2003 Microchip Technology Inc.
Advance Information
DS39612A-page 257
PIC18F6X2X/8X2X
NOTES:
DS39612A-page 258
Advance Information
2003 Microchip Technology Inc.
PIC18F6X2X/8X2X
24.1 Configuration Bits
24.0 SPECIAL FEATURES OF THE
CPU
The configuration bits can be programmed (read as ‘0’)
or left unprogrammed (read as ‘1’), to select various
device configurations. These bits are mapped, starting
at program memory location 300000h.
There are several features intended to maximize sys-
tem reliability, minimize cost through elimination of
external components, provide power saving operating
modes and offer code protection. These are:
The user will note that address 300000h is beyond the
user program memory space. In fact, it belongs to the
configuration memory space (300000h through
3FFFFFh) which can only be accessed using table
reads and table writes.
• OSC Selection
• RESET
- Power-on Reset (POR)
- Power-up Timer (PWRT)
- Oscillator Start-up Timer (OST)
- Brown-out Reset (BOR)
• Interrupts
Programming the Configuration registers is done in a
manner similar to programming the FLASH memory.
The EECON1 register WR bit starts a self-timed write
to the Configuration register. In normal operation mode,
a TBLWT instruction, with the TBLPTR pointed to the
Configuration register, sets up the address and the
data for the Configuration register write. Setting the WR
bit starts a long write to the Configuration register. The
Configuration registers are written a byte at a time. To
write or erase a configuration cell, a TBLWTinstruction
can write a ‘1’ or a ‘0’ into the cell.
• Watchdog Timer (WDT)
• SLEEP
• Code Protection
• ID Locations
• In-Circuit Serial Programming
All PIC18F6X2X/8X2X devices have a Watchdog Timer
which is permanently enabled via the configuration bits,
or software controlled. It runs off its own RC oscillator
for added reliability. There are two timers that offer nec-
essary delays on power-up. One is the Oscillator Start-
up Timer (OST), intended to keep the chip in RESET
until the crystal oscillator is stable. The other is the
Power-up Timer (PWRT) which provides a fixed delay
on power-up only, designed to keep the part in RESET
while the power supply stabilizes. With these two tim-
ers on-chip, most applications need no external
RESET circuitry.
SLEEP mode is designed to offer a very low current
power-down mode. The user can wake-up from SLEEP
through external RESET, Watchdog Timer wake-up, or
through an interrupt. Several oscillator options are also
made available to allow the part to fit the application.
The RC oscillator option saves system cost, while the
LP crystal option saves power. A set of configuration
bits are used to select various options.
2003 Microchip Technology Inc.
Advance Information
DS39612A-page 259
PIC18F6X2X/8X2X
TABLE 24-1: CONFIGURATION BITS AND DEVICE IDS
Default/
Unprogrammed
Value
File Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
300001h CONFIG1H
300002h CONFIG2L
300003h CONFIG2H
—
—
—
—
OSCSEN
—
—
—
FOSC3
FOSC2
FOSC1
FOSC0
PWRTEN
WDTEN
PM0
--1- 1111
---- 1111
---1 1111
1--- --11
1--- --11
1--- -1-1
---- 1111
11-- ----
---- 1111
111- ----
---- 1111
-1-- ----
(Note 3)
BORV1 BORV0
BODEN
—
—
—
WDTPS3 WDTPS2 WDTPS1 WDTPS0
(1)
300004h CONFIG3L
WAIT
—
—
—
—
—
—
—
—
PM1
ECCPMX
—
(1)
300005h CONFIG3H MCLRE
300006h CONFIG4L DEBUG
—
—
CCP2MX
STVREN
CP0
—
—
—
—
LVP
CP2
—
(2)
300008h CONFIG5L
300009h CONFIG5H
30000Ah CONFIG6L
—
CPD
—
—
—
—
CP3
—
CP1
CPB
—
—
—
—
—
(2)
(2)
—
—
WRT3
—
WRT2
—
WRT1
—
WRT0
—
30000Bh CONFIG6H WRTD
WRTB
—
WRTC
—
—
30000Ch CONFIG7L
30000Dh CONFIG7H
3FFFFEh DEVID1
3FFFFFh DEVID2
—
—
—
EBTR3
—
EBTR2
—
EBTR1
—
EBTR0
—
EBTRB
DEV1
DEV9
—
—
DEV2
DEV10
DEV0
DEV8
REV4
DEV7
REV3
DEV6
REV2
DEV5
REV1
DEV4
REV0
DEV3
0000 1010
Legend:
x= unknown, u= unchanged, - = unimplemented, q= value depends on condition.
Shaded cells are unimplemented, read as ‘0’.
Note 1: Unimplemented in PIC18F6X2X devices; maintain this bit set.
2: Unimplemented in PIC18FX525 devices; maintain this bit set.
3: See Register 24-13 for DEVID1 values.
DS39612A-page 260
Advance Information
2003 Microchip Technology Inc.
PIC18F6X2X/8X2X
REGISTER 24-1: CONFIG1H: CONFIGURATION REGISTER 1 HIGH (BYTE ADDRESS 300001h)
U-0
—
U-0
—
R/P-1
U-0
—
R/P-1
R/P-1
R/P-1
R/P-1
OSCSEN
FOSC3
FOSC2
FOSC1
FOSC0
bit 7
bit 0
bit 7-6 Unimplemented: Read as ‘0’
bit 5
bit 4
OSCSEN: Oscillator System Clock Switch Enable bit
1= Oscillator system clock switch option is disabled (main oscillator is source)
0= Timer1 oscillator system clock switch option is enabled (oscillator switching is enabled)
Unimplemented: Read as ‘0’
bit 3-0 FOSC3:FOSC0: Oscillator Selection bits
1111= RC oscillator with OSC2 configured as RA6
1110= HS oscillator with SW enabled 4x PLL
1101= EC oscillator with OSC2 configured as RA6 and SW enabled 4x PLL
1100= EC oscillator with OSC2 configured as RA6 and HW enabled 4x PLL
1011= Reserved; do not use
1010= Reserved; do not use
1001= Reserved; do not use
1000= Reserved; do not use
0111= RC oscillator with OSC2 configured as RA6
0110= HS oscillator with HW enabled 4x PLL
0101= EC oscillator with OSC2 configured as RA6
0100= EC oscillator with OSC2 configured as divide by 4 clock output
0011= RC oscillator with OSC2 configured as divide by 4 clock output
0010= HS oscillator
0001= XT oscillator
0000= LP oscillator
Legend:
R = Readable bit
P = Programmable bit U = Unimplemented bit, read as ‘0’
u = Unchanged from programmed state
- n = Value when device is unprogrammed
2003 Microchip Technology Inc.
Advance Information
DS39612A-page 261
PIC18F6X2X/8X2X
REGISTER 24-2: CONFIG2L: CONFIGURATION REGISTER 2 LOW (BYTE ADDRESS 300002h)
U-0
—
U-0
—
U-0
—
U-0
—
R/P-1
R/P-1
R/P-1
R/P-1
BORV1
BORV0
BOREN PWRTEN
bit 0
bit 7
bit 7-4 Unimplemented: Read as ‘0’
bit 3-2 BORV1:BORV0: Brown-out Reset Voltage bits
11= VBOR set to 2.0V
10= VBOR set to 2.7V
01= VBOR set to 4.2V
00= VBOR set to 4.5V
bit 1
bit 0
BOREN: Brown-out Reset Enable bit
1= Brown-out Reset enabled
0= Brown-out Reset disabled
PWRTEN: Power-up Timer Enable bit
1= PWRT disabled
0= PWRT enabled
Legend:
R = Readable bit
P = Programmable bit
U = Unimplemented bit, read as ‘0’
- n = Value when device is unprogrammed
u = Unchanged from programmed state
REGISTER 24-3: CONFIG2H: CONFIGURATION REGISTER 2 HIGH (BYTE ADDRESS 300003h)
U-0
—
U-0
—
U-0
—
R/P-1
R/P-1
R/P-1
R/P-1
R/P-1
WDTPS3 WDTPS2 WDTPS1 WDTPS0 WDTEN
bit 0
bit 7
bit 7-5 Unimplemented: Read as ‘0’
bit 4-1 WDTPS2:WDTPS0: Watchdog Timer Postscaler Select bits
1111= 1:32768
1110= 1:16384
1101= 1:8192
1100= 1:4096
1011= 1:2048
1010= 1:1024
1001= 1:512
1000= 1:256
0111= 1:128
0110= 1:64
0101= 1:32
0100= 1:16
0011= 1:8
0010= 1:4
0001= 1:2
0000= 1:1
bit 0
WDTEN: Watchdog Timer Enable bit
1= WDT enabled
0= WDT disabled (control is placed on the SWDTEN bit)
Legend:
R = Readable bit
P = Programmable bit
U = Unimplemented bit, read as ‘0’
- n = Value when device is unprogrammed
u = Unchanged from programmed state
DS39612A-page 262
Advance Information
2003 Microchip Technology Inc.
PIC18F6X2X/8X2X
REGISTER 24-4: CONFIG3L: CONFIGURATION REGISTER 3 LOW (BYTE ADDRESS 300004h)(1)
R/P-1
WAIT
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
R/P-1
PM1
R/P-1
PM0
bit 7
bit 0
bit 7
WAIT: External Bus Data Wait Enable bit
1= Wait selections unavailable for table reads and table writes
0= Wait selections for table reads and table writes are determined by WAIT1:WAIT0 bits
(MEMCOM<5:4>)
bit 6-2 Unimplemented: Read as ‘0’
bit 1-0 PM1:PM0: Processor Mode Select bits
11= Microcontroller mode
10= Microprocessor mode
01= Microprocessor with Boot Block mode
00= Extended Microcontroller mode
Note 1: This register is unimplemented for PIC18F6X2X devices; maintain these bits set.
Legend:
R = Readable bit
P = Programmable bit
U = Unimplemented bit, read as ‘0’
- n = Value when device is unprogrammed
u = Unchanged from programmed state
REGISTER 24-5: CONFIG3H: CONFIGURATION REGISTER 3 HIGH (BYTE ADDRESS 300005h)
R/P-1
MCLRE(1)
bit 7
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
R/P-1
R/P-1
ECCPMX(2) CCP2MX
bit 0
bit 7
MCLRE: MCLR Enable bit(1)
1= MCLR pin enabled, RG5 input pin disabled
0= RG5 input enabled, MCLR disabled
bit 6-2 Unimplemented: Read as ‘0’
bit 1
ECCPMX: ECCP Mux bit(2)
1= Enhanced CCP1 (P1B/P1C) and Enhanced CCP3 (P3B/P3C) PWM outputs are
multiplexed with RE6 through RE3
0= Enhanced CCP1 (P1B/P1C) and Enhanced CCP3 (P3B/P3C) PWM outputs are
multiplexed with RH7 through RH4
bit 0
CCP2MX: CCP2 Mux bit
In Microcontroller mode:
1= CCP2 input/output is multiplexed with RC1
0= CCP2 input/output is multiplexed with RE7
In Microprocessor, Microprocessor with Boot Block and Extended Microcontroller modes
(PIC18F8X8X devices only):
1= CCP2 input/output is multiplexed with RC1
0= CCP2 input/output is multiplexed with RB3
Note 1: If MCLR is disabled, either disable low voltage ICSP or hold RB5/PGM low to
ensure proper entry into ICSP mode.
2: This register is unimplemented for PIC18F6X2X devices; maintain these bits set.
Legend:
R = Readable bit
P = Programmable bit
U = Unimplemented bit, read as ‘0’
- n = Value when device is unprogrammed
u = Unchanged from programmed state
2003 Microchip Technology Inc.
Advance Information
DS39612A-page 263
PIC18F6X2X/8X2X
REGISTER 24-6: CONFIG4L: CONFIGURATION REGISTER 4 LOW (BYTE ADDRESS 300006h)
R/P-1
DEBUG
bit 7
U-0
—
U-0
—
U-0
—
U-0
—
R/P-1
LVP
U-0
—
R/P-1
STVREN
bit 0
bit 7
DEBUG: Background Debugger Enable bit
1= Background debugger disabled. RB6 and RB7 configured as general purpose I/O pins.
0= Background debugger enabled. RB6 and RB7 are dedicated to in-circuit debug.
bit 6-3 Unimplemented: Read as ‘0’
bit 2
LVP: Low Voltage ICSP Enable bit
1= Low voltage ICSP enabled
0= Low voltage ICSP disabled
bit 1
bit 0
Unimplemented: Read as ‘0’
STVREN: Stack Full/Underflow Reset Enable bit
1= Stack full/underflow will cause RESET
0= Stack full/underflow will not cause RESET
Legend:
R = Readable bit
P = Programmable bit U = Unimplemented bit, read as ‘0’
- n = Value when device is unprogrammed
u = Unchanged from programmed state
DS39612A-page 264
Advance Information
2003 Microchip Technology Inc.
PIC18F6X2X/8X2X
REGISTER 24-7: CONFIG5L: CONFIGURATION REGISTER 5 LOW (BYTE ADDRESS 300008h)
U-0
—
U-0
—
U-0
—
U-0
—
R/C-1
CP3(1)
R/C-1
CP2
R/C-1
CP1
R/C-1
CP0
bit 7
bit 0
bit 7-4 Unimplemented: Read as ‘0’
bit 3
CP3: Code Protection bit(1)
1= Block 3 (00C000-00FFFFh) not code protected
0= Block 3 (00C000-00FFFFh) code protected
Note 1: Unimplemented in PIC18FX525 devices; maintain this bit set.
bit 2
bit 1
bit 0
CP2: Code Protection bit
1= Block 2 (008000-00BFFFh) not code protected
0= Block 2 (008000-00BFFFh) code protected
CP1: Code Protection bit
1= Block 1 (004000-007FFFh) not code protected
0= Block 1 (004000-007FFFh) code protected
CP0: Code Protection bit
1= Block 0 (000800-003FFFh) not code protected
0= Block 0 (000800-003FFFh) code protected
Legend:
R = Readable bit
C = Clearable bit
U = Unimplemented bit, read as ‘0’
u = Unchanged from programmed state
- n = Value when device is unprogrammed
REGISTER 24-8: CONFIG5H: CONFIGURATION REGISTER 5 HIGH (BYTE ADDRESS 300009h)
R/C-1
CPD
R/C-1
CPB
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
bit 7
bit 0
bit 7
bit 6
CPD: Data EEPROM Code Protection bit
1= Data EEPROM not code protected
0= Data EEPROM code protected
CPB: Boot Block Code Protection bit
1= Boot block (000000-0007FFh) not code protected
0= Boot block (000000-0007FFh) code protected
bit 5-0 Unimplemented: Read as ‘0’
Legend:
R = Readable bit
C = Clearable bit
U = Unimplemented bit, read as ‘0’
u = Unchanged from programmed state
- n = Value when device is unprogrammed
2003 Microchip Technology Inc.
Advance Information
DS39612A-page 265
PIC18F6X2X/8X2X
REGISTER 24-9: CONFIG6L: CONFIGURATION REGISTER 6 LOW (BYTE ADDRESS 30000Ah)
U-0
—
U-0
—
U-0
—
U-0
—
R/C-1
WRT3(1)
R/C-1
WRT2
R/C-1
WRT1
R/C-1
WRT0
bit 7
bit 0
bit 7-4 Unimplemented: Read as ‘0’
bit 3
WRT3: Write Protection bit(1)
1= Block 3 (00C000-00FFFFh) not write protected
0= Block 3 (00C000-00FFFFh) write protected
Note 1: Unimplemented in PIC18FX525 devices; maintain this bit set.
bit 2
bit 1
bit 0
WRT2: Write Protection bit
1= Block 2 (008000-00BFFFh) not write protected
0= Block 2 (008000-00BFFFh) write protected
WRT1: Write Protection bit
1= Block 1 (004000-007FFFh) not write protected
0= Block 1 (004000-007FFFh) write protected
WR0: Write Protection bit
1= Block 0 (000800-003FFFh) not write protected
0= Block 0 (000800-003FFFh) write protected
Legend:
R = Readable bit
P = Programmable bit
U = Unimplemented bit, read as ‘0’
u = Unchanged from programmed state
- n = Value when device is unprogrammed
REGISTER 24-10: CONFIG6H: CONFIGURATION REGISTER 6 HIGH (BYTE ADDRESS 30000Bh)
R/C-1
R/C-1
R/C-1
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
WRTD
WRTB
WRTC
bit 7
bit 0
bit 7
bit 6
bit 5
WRTD: Data EEPROM Write Protection bit
1= Data EEPROM not write protected
0= Data EEPROM write protected
WRTB: Boot Block Write Protection bit
1= Boot block (000000-0007FFh) not write protected
0= Boot block (000000-0007FFh) write protected
WRTC: Configuration Register Write Protection bit
1= Configuration registers (300000-3000FFh) not write protected
0= Configuration registers (300000-3000FFh) write protected
bit 4-0 Unimplemented: Read as ‘0’
Legend:
R = Readable bit
P = Programmable bit U = Unimplemented bit, read as ‘0’
- n = Value when device is unprogrammed
u = Unchanged from programmed state
DS39612A-page 266
Advance Information
2003 Microchip Technology Inc.
PIC18F6X2X/8X2X
REGISTER 24-11: CONFIG7L: CONFIGURATION REGISTER 7 LOW (BYTE ADDRESS 30000Ch)
U-0
—
U-0
—
U-0
—
U-0
—
R/C-1
EBTR3(1)
R/C-1
R/C-1
R/C-1
EBTR0
bit 0
EBTR2
EBTR1
bit 7
bit 7-4 Unimplemented: Read as ‘0’
bit 3
EBTR3: Table Read Protection bit(1)
1= Block 3 (00C000-00FFFFh) not protected from table reads executed in other blocks
0= Block 3 (00C000-00FFFFh) protected from table reads executed in other blocks
Note 1: Unimplemented in PIC18FX525 devices; maintain this bit set.
bit 2
bit 1
bit 0
EBTR2: Table Read Protection bit
1= Block 2 (008000-00BFFFh) not protected from table reads executed in other blocks
0= Block 2 (008000-00BFFFh) protected from table reads executed in other blocks
EBTR1: Table Read Protection bit
1= Block 1 (004000-007FFFh) not protected from table reads executed in other blocks
0= Block 1 (004000-007FFFh) protected from table reads executed in other blocks
EBTR0: Table Read Protection bit
1= Block 0 (000800-003FFFh) not protected from table reads executed in other blocks
0= Block 0 (000800-003FFFh) protected from table reads executed in other blocks
Legend:
R = Readable bit
P = Programmable bit
U = Unimplemented bit, read as ‘0’
- n = Value when device is unprogrammed
u = Unchanged from programmed state
REGISTER 24-12: CONFIG7H: CONFIGURATION REGISTER 7 HIGH (BYTE ADDRESS 30000Dh)
U-0
—
R/C-1
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
EBTRB
bit 7
bit 0
bit 7
bit 6
Unimplemented: Read as ‘0’
EBTRB: Boot Block Table Read Protection bit
1= Boot block (000000-0007FFh) not protected from table reads executed in other blocks
0= Boot block (000000-0007FFh) protected from table reads executed in other blocks
bit 5-0 Unimplemented: Read as ‘0’
Legend:
R = Readable bit
P = Programmable bit U = Unimplemented bit, read as ‘0’
- n = Value when device is unprogrammed
u = Unchanged from programmed state
2003 Microchip Technology Inc.
Advance Information
DS39612A-page 267
PIC18F6X2X/8X2X
REGISTER 24-13: DEVICE ID REGISTER 1 FOR PIC18F6X2X/8X2X DEVICES (ADDRESS 3FFFFEh)
R
R
R
R
R
R
R
R
DEV2
DEV1
DEV0
REV4
REV3
REV2
REV1
REV0
bit 7
bit 0
bit 7-5 DEV2:DEV0: Device ID bits
100= PIC18F8621
101= PIC18F6621
110= PIC18F8525
111= PIC18F6525
bit 4-0 REV4:REV0: Revision ID bits
These bits are used to indicate the device revision.
Legend:
R = Readable bit
P = Programmable bit U = Unimplemented bit, read as ‘0’
u = Unchanged from programmed state
- n = Value when device is unprogrammed
REGISTER 24-14: DEVICE ID REGISTER 2 FOR PIC18F6X2X/8X2X DEVICES (ADDRESS 3FFFFFh)
R-0
R-0
R-0
R-0
R-1
R-0
R-1
R-0
DEV10
DEV9
DEV8
DEV7
DEV6
DEV5
DEV4
DEV3
bit 7
bit 0
bit 7-0 DEV10:DEV3: Device ID bits
These bits are used with the DEV2:DEV0 bits in the Device ID Register 1 to identify the part
number.
0000 1010= PIC18F6X2X/8X2X
Legend:
R = Readable bit
P = Programmable bit U = Unimplemented bit, read as ‘0’
- n = Value when device is unprogrammed
u = Unchanged from programmed state
DS39612A-page 268
Advance Information
2003 Microchip Technology Inc.
PIC18F6X2X/8X2X
The WDT time-out period values may be found in the
Electrical Specifications section under parameter #31.
Values for the WDT postscaler may be assigned using
the configuration bits.
24.2 Watchdog Timer (WDT)
The Watchdog Timer is a free running on-chip RC
oscillator which does not require any external
components. This RC oscillator is separate from the
RC oscillator of the OSC1/CLKI pin. That means that
the WDT will run even if the clock on the OSC1/CLKI
and OSC2/CLKO/RA6 pins of the device has been
stopped, for example, by execution of a SLEEP
instruction.
Note 1: The CLRWDT and SLEEP instructions
clear the WDT and the postscaler if
assigned to the WDT and prevent it from
timing out and generating a device
RESET condition.
2: When a CLRWDT instruction is executed
and the postscaler is assigned to the
WDT, the postscaler count will be cleared
but the postscaler assignment is not
changed.
During normal operation, a WDT time-out generates a
device RESET (Watchdog Timer Reset). If the device is
in SLEEP mode, a WDT time-out causes the device to
wake-up and continue with normal operation (Watch-
dog Timer wake-up). The TO bit in the RCON register
will be cleared upon a WDT time-out.
24.2.1
CONTROL REGISTER
The Watchdog Timer is enabled or disabled by a device
configuration bit, WDTEN (CONFIG2H<0>). If WDTEN
is set, software execution may not disable this function.
When WDTEN is cleared, the SWDTEN bit enables or
disables the operation of the WDT.
Register 24-15 shows the WDTCON register. This is a
readable and writable register which contains a control
bit that allows software to override the WDT enable
configuration bit only when the configuration bit has
disabled the WDT.
REGISTER 24-15: WDTCON REGISTER
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
R/W-0
SWDTEN
bit 0
bit 7
bit 7-1 Unimplemented: Read as ‘0’
bit 0
SWDTEN: Software Controlled Watchdog Timer Enable bit
1= Watchdog Timer is on
0= Watchdog Timer is turned off (if CONFIG2H<0> = 0)
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
- n = Value at POR
2003 Microchip Technology Inc.
Advance Information
DS39612A-page 269
PIC18F6X2X/8X2X
24.2.2
WDT POSTSCALER
The WDT has a postscaler that can extend the WDT
Reset period. The postscaler is selected at the time of
the device programming by the value written to the
CONFIG2H Configuration register.
FIGURE 24-1:
WATCHDOG TIMER BLOCK DIAGRAM
WDT Timer
Postscaler
16
16 - to - 1 MUX
WDTPS3:WDTPS0
WDTEN
Configuration bit
SWDTEN bit
WDT
Time-out
Note:
WDPS3:WDPS0 are bits in register CONFIG2H.
TABLE 24-2: SUMMARY OF WATCHDOG TIMER REGISTERS
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
CONFIG2H
RCON
—
IPEN
—
—
—
—
—
—
—
WDTPS3 WDTPS2 WDTPS2 WDTPS0
WDTEN
BOR
RI
—
TO
—
PD
—
POR
—
WDTCON
SWDTEN
Legend: Shaded cells are not used by the Watchdog Timer.
DS39612A-page 270
Advance Information
2003 Microchip Technology Inc.
PIC18F6X2X/8X2X
External MCLR Reset will cause a device RESET. All
other events are considered a continuation of program
execution and will cause a “wake-up”. The TO and PD
bits in the RCON register can be used to determine the
cause of the device RESET. The PD bit, which is set on
power-up, is cleared when SLEEP is invoked. The TO
bit is cleared if a WDT time-out occurred (and caused
wake-up).
24.3 Power-down Mode (SLEEP)
Power-down mode is entered by executing a SLEEP
instruction.
If enabled, the Watchdog Timer will be cleared but
keeps running, the PD bit (RCON<3>) is cleared, the
TO (RCON<4>) bit is set, and the oscillator driver is
turned off. The I/O ports maintain the status they had
before the SLEEP instruction was executed (driving
high, low, or hi-impedance).
When the SLEEPinstruction is being executed, the next
instruction (PC + 2) is prefetched. For the device to
wake-up through an interrupt event, the corresponding
interrupt enable bit must be set (enabled). Wake-up is
regardless of the state of the GIE bit. If the GIE bit is
clear (disabled), the device continues execution at the
instruction after the SLEEPinstruction. If the GIE bit is
set (enabled), the device executes the instruction after
the SLEEP instruction and then branches to the inter-
rupt address. In cases where the execution of the
instruction following SLEEP is not desirable, the user
should have a NOPafter the SLEEPinstruction.
For lowest current consumption in this mode, place all
I/O pins at either VDD or VSS, ensure no external cir-
cuitry is drawing current from the I/O pin, power-down
the A/D and disable external clocks. Pull all I/O pins
that are hi-impedance inputs, high or low externally, to
avoid switching currents caused by floating inputs. The
T0CKI input should also be at VDD or VSS for lowest
current consumption. The contribution from on-chip
pull-ups on PORTB should be considered.
The MCLR pin must be at a logic high level (VIHMC).
24.3.2
WAKE-UP USING INTERRUPTS
24.3.1
WAKE-UP FROM SLEEP
When global interrupts are disabled (GIE cleared) and
any interrupt source has both its interrupt enable bit
and interrupt flag bit set, one of the following will occur:
The device can wake-up from SLEEP through one of
the following events:
1. External RESET input on MCLR pin.
• If an interrupt condition (interrupt flag bit and
interrupt enable bits are set) occurs before the
execution of a SLEEPinstruction, the SLEEP
instruction will complete as a NOP. Therefore, the
WDT and WDT postscaler will not be cleared, the
TO bit will not be set and PD bits will not be
cleared.
2. Watchdog Timer wake-up (if WDT was
enabled).
3. Interrupt from INT pin, RB port change or a
peripheral interrupt.
The following peripheral interrupts can wake the device
from SLEEP:
• If the interrupt condition occurs during or after
the execution of a SLEEPinstruction, the device
will immediately wake-up from SLEEP. The
SLEEPinstruction will be completely executed
before the wake-up. Therefore, the WDT and
WDT postscaler will be cleared, the TO bit will be
set and the PD bit will be cleared.
1. PSP read or write.
2. TMR1 interrupt. Timer1 must be operating as an
asynchronous counter.
3. TMR3 interrupt. Timer3 must be operating as an
asynchronous counter.
4. CCP Capture mode interrupt.
5. Special event trigger (Timer1 in Asynchronous
mode using an external clock).
Even if the flag bits were checked before executing a
SLEEP instruction, it may be possible for flag bits to
become set before the SLEEPinstruction completes. To
determine whether a SLEEPinstruction executed, test
the PD bit. If the PD bit is set, the SLEEP instruction
was executed as a NOP.
6. MSSP (START/STOP) bit detect interrupt.
7. MSSP transmit or receive in Slave mode
(SPI/I2C).
8. USART RX or TX (Synchronous Slave mode).
9. A/D conversion (when A/D clock source is RC).
10. EEPROM write operation complete.
11. LVD interrupt.
To ensure that the WDT is cleared, a CLRWDT
instruction should be executed before a SLEEP
instruction.
Other peripherals cannot generate interrupts since
during SLEEP, no on-chip clocks are present.
2003 Microchip Technology Inc.
Advance Information
DS39612A-page 271
PIC18F6X2X/8X2X
FIGURE 24-2:
WAKE-UP FROM SLEEP THROUGH INTERRUPT(1,2)
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
OSC1
CLKO(4)
INT pin
(2)
TOST
INTF Flag
(INTCON<1>)
Interrupt Latency(3)
GIEH bit
(INTCON<7>)
Processor in
SLEEP
INSTRUCTION FLOW
PC
PC
PC + 2
PC + 4
PC + 4
PC + 4
0008h
000Ah
Instruction
Inst(0008h)
Inst(PC + 2)
Inst(PC + 4)
Inst(PC + 2)
Inst(000Ah)
Inst(PC) = SLEEP
Fetched
Instruction
Executed
Dummy Cycle
Dummy Cycle
Inst(0008h)
SLEEP
Inst(PC - 1)
Note 1: XT, HS or LP Oscillator mode assumed.
2: GIE = 1assumed. In this case, after wake-up, the processor jumps to the interrupt routine. If GIE = 0, execution will continue in-line.
3: TOST = 1024 TOSC (drawing not to scale). This delay will not occur for RC and EC Osc modes.
4: CLKO is not available in these Osc modes but shown here for timing reference.
DS39612A-page 272
Advance Information
2003 Microchip Technology Inc.
PIC18F6X2X/8X2X
Each of the blocks has three code protection bits
associated with them. They are:
24.4 Program Verification and
Code Protection
• Code Protect bit (CPn)
The overall structure of the code protection on the
PIC18 FLASH devices differs significantly from other
PICmicro® devices.
• Write Protect bit (WRTn)
• External Block Table Read bit (EBTRn)
Figure 24-3 shows the program memory organization
for 48 and 64-Kbyte devices and the specific code
protection bit associated with each block. The actual
locations of the bits are summarized in Table 24-3.
The user program memory is divided on binary bound-
aries into four blocks of 16 Kbytes each. The first block is
further divided into a boot block of 2048 bytes and a
second block (Block 0) of 14 Kbytes.
FIGURE 24-3:
CODE PROTECTED PROGRAM MEMORY FOR PIC18F6X2X/8X2X DEVICES
MEMORY SIZE/DEVICE
Block Code Protection
48 Kbytes
64 Kbytes
Address
Controlled By:
(PIC18FX525
(PIC18FX621)
Range
000000h
0007FFh
Boot Block
Block 0
Boot Block
Block 0
CPB, WRTB, EBTRB
CP0, WRT0, EBTR0
000800h
003FFFh
004000h
Block 1
Block 2
Block 1
Block 2
Block 3
CP1, WRT1, EBTR1
CP2, WRT2, EBTR2
CP3, WRT3, EBTR3
007FFFh
008000h
00BFFFh
00C000h
Unimplemented Read ‘0’
00FFFFh
TABLE 24-3: SUMMARY OF CODE PROTECTION REGISTERS
File Name
300008h
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
CONFIG5L
CONFIG5H
CONFIG6L
CONFIG6H
CONFIG7L
CONFIG7H
—
CPD
—
—
CPB
—
—
—
—
—
—
—
—
—
CP3*
—
CP2
—
CP1
—
CP0
—
300009h
30000Ah
30000Bh
30000Ch
30000Dh
—
WRT3*
—
WRT2
—
WRT1
—
WRT0
—
WRTD
—
WRTB
—
WRTC
—
EBTR3*
—
EBTR2
—
EBTR1
—
EBTR0
—
—
EBTRB
—
Legend: Shaded cells are unimplemented.
*
Unimplemented in PIC18FX585 devices.
2003 Microchip Technology Inc.
Advance Information
DS39612A-page 273
PIC18F6X2X/8X2X
cutes from within that block is allowed to read. A table
read instruction that executes from a location outside of
that block is not allowed to read and will result in read-
ing ‘0’s. Figures 24-4 through 24-6 illustrate table write
and table read protection.
24.4.1
PROGRAM MEMORY
CODE PROTECTION
The user memory may be read to or written from any
location using the table read and table write instruc-
tions. The device ID may be read with table reads. The
Configuration registers may be read and written with
the table read and table write instructions.
Note: Code protection bits may only be written to
a ‘0’ from a ‘1’ state. It is not possible to
write a ‘1’ to a bit in the ‘0’ state. Code pro-
tection bits are only set to ‘1’ by a full chip
erase or block erase function. The full chip
erase and block erase functions can only
be initiated via ICSP or an external
programmer.
In user mode, the CPn bits have no direct effect. CPn
bits inhibit external reads and writes. A block of user
memory may be protected from table writes if the
WRTn configuration bit is ‘0’. The EBTRn bits control
table reads. For a block of user memory with the
EBTRn bit set to ‘0’, a table read instruction that exe-
FIGURE 24-4:
TABLE WRITE (WRTn) DISALLOWED
Program Memory
Register Values
Configuration Bit Settings
000000h
0007FFh
000800h
WRTB,EBTRB = 11
TBLPTR = 000FFFh
PC = 003FFEh
WRT0,EBTR0 = 01
WRT1,EBTR1 = 11
TBLWT*
003FFFh
004000h
007FFFh
008000h
TBLWT*
WRT2,EBTR2 = 11
WRT3,EBTR3 = 11
PC = 008FFEh
00BFFFh
00C000h
00FFFFh
Results: All table writes disabled to Block n whenever WRTn = 0.
DS39612A-page 274
Advance Information
2003 Microchip Technology Inc.
PIC18F6X2X/8X2X
FIGURE 24-5:
EXTERNAL BLOCK TABLE READ (EBTRn) DISALLOWED
Register Values
Program Memory
Configuration Bit Settings
000000h
0007FFh
000800h
WRTB,EBTRB = 11
TBLPTR = 000FFFh
PC = 004FFEh
WRT0,EBTR0 = 10
WRT1,EBTR1 = 11
003FFFh
004000h
TBLRD*
007FFFh
008000h
WRT2,EBTR2 = 11
WRT3,EBTR3 = 11
00BFFFh
00C000h
00FFFFh
Results: All table reads from external blocks to Block n are disabled whenever EBTRn = 0.
TABLAT register returns a value of ‘0’.
FIGURE 24-6:
EXTERNAL BLOCK TABLE READ (EBTRn) ALLOWED
Register Values
Program Memory
Configuration Bit Settings
000000h
0007FFh
000800h
WRTB,EBTRB = 11
TBLPTR = 000FFFh
PC = 003FFEh
WRT0,EBTR0 = 10
TBLRD*
003FFFh
004000h
WRT1,EBTR1 = 11
007FFFh
008000h
WRT2,EBTR2 = 11
WRT3,EBTR3 = 11
00BFFFh
00C000h
00FFFFh
Results: Table reads permitted within Block n, even when EBTRBn = 0.
TABLAT register returns the value of the data at the location TBLPTR.
2003 Microchip Technology Inc.
Advance Information
DS39612A-page 275
PIC18F6X2X/8X2X
To use the in-circuit debugger function of the microcon-
troller, the design must implement In-Circuit Serial Pro-
gramming connections to MCLR/VPP, VDD, GND, RB7
and RB6. This will interface to the in-circuit debugger
module available from Microchip or one of the third
party development tool companies.
24.4.2
DATA EEPROM CODE
PROTECTION
The entire data EEPROM is protected from external
reads and writes by two bits: CPD and WRTD. CPD
inhibits external reads and writes of data EEPROM.
WRTD inhibits external writes to data EEPROM. The
CPU can continue to read and write data EEPROM
regardless of the protection bit settings.
24.8 Low Voltage ICSP Programming
The LVP bit Configuration register, CONFIG4L,
enables low voltage ICSP programming. This mode
allows the microcontroller to be programmed via ICSP
using a VDD source in the operating voltage range. This
only means that VPP does not have to be brought to
VIHH, but can instead be left at the normal operating
voltage. In this mode, the RB5/PGM pin is dedicated to
the programming function and ceases to be a general
purpose I/O pin. During programming, VDD is applied to
the MCLR/VPP pin. To enter Programming mode, VDD
must be applied to the RB5/PGM pin provided the LVP
bit is set. The LVP bit defaults to a (‘1’) from the factory.
24.4.3
CONFIGURATION REGISTER
PROTECTION
The Configuration registers can be write protected. The
WRTC bit controls protection of the Configuration regis-
ters. In user mode, the WRTC bit is readable only. WRTC
can only be written via ICSP or an external programmer.
24.5 ID Locations
Eight memory locations (200000h - 200007h) are des-
ignated as ID locations where the user can store check-
sum or other code identification numbers. These
locations are accessible during normal execution
through the TBLRDand TBLWTinstructions, or during
program/verify. The ID locations can be read when the
device is code protected.
Note 1: The High Voltage Programming mode is
always available, regardless of the state
of the LVP bit, by applying VIHH to the
MCLR pin.
2: While in Low Voltage ICSP mode, the
RB5 pin can no longer be used as a gen-
eral purpose I/O pin, and should be held
low during normal operation.
24.6
In-Circuit Serial Programming
PIC18F6X2X/8X2X microcontrollers can be serially
programmed while in the end application circuit. This is
simply done with two lines for clock and data, and three
other lines for power, ground and the programming
voltage. This allows customers to manufacture boards
with unprogrammed devices and then program the
microcontroller just before shipping the product. This
also allows the most recent firmware or a custom
firmware to be programmed.
3: When using low voltage ICSP program-
ming (LVP) and the pull-ups on PORTB
are enabled, bit 5 in the TRISB register
must be cleared to disable the pull-up on
RB5 and ensure the proper operation of
the device.
4: If the device Master Clear is disabled,
verify that either of the following is done to
ensure proper entry into ICSP mode:
a.) disable low voltage programming
(CONFIG4L<2> = 0); or
24.7 In-Circuit Debugger
When the DEBUG bit in Configuration register,
CONFIG4L, is programmed to a ‘0’, the in-circuit
debugger functionality is enabled. This function allows
simple debugging functions when used with MPLAB®
IDE. When the microcontroller has this feature
enabled, some of the resources are not available for
general use. Table 24-4 shows which features are
consumed by the background debugger.
b.) make certain that RB5/PGM is held
low during entry into ICSP.
If Low Voltage Programming mode is not used, the LVP
bit can be programmed to a ‘0’ and RB5/PGM becomes
a digital I/O pin. However, the LVP bit may only be pro-
grammed when programming is entered with VIHH on
MCLR/VPP.
It should be noted that once the LVP bit is programmed
to ‘0’, only the High Voltage Programming mode is
available and only High Voltage Programming mode
can be used to program the device.
TABLE 24-4: DEBUGGER RESOURCES
I/O pins
RB6, RB7
Stack
2 levels
512 bytes
10 bytes
When using low voltage ICSP, the part must be sup-
plied 4.5V to 5.5V if a bulk erase will be executed. This
includes reprogramming of the code protect bits from
an on-state to off-state. For all other cases of low volt-
age ICSP, the part may be programmed at the normal
operating voltage. This means unique user IDs or user
code can be reprogrammed or added.
Program Memory
Data Memory
DS39612A-page 276
Advance Information
2003 Microchip Technology Inc.
PIC18F6X2X/8X2X
The literal instructions may use some of the following
operands:
25.0 INSTRUCTION SET SUMMARY
The PIC18 instruction set adds many enhancements to
the previous PICmicro instruction sets, while maintain-
ing an easy migration from these PICmicro instruction
sets.
• A literal value to be loaded into a file register
(specified by ‘k’)
• The desired FSR register to load the literal value
into (specified by ‘f’)
Most instructions are a single program memory word
(16 bits), but there are three instructions that require
two program memory locations.
• No operand required
(specified by ‘—’)
The control instructions may use some of the following
operands:
Each single word instruction is a 16-bit word divided
into an OPCODE, which specifies the instruction type
and one or more operands, which further specify the
operation of the instruction.
• A program memory address (specified by ‘n’)
• The mode of the call or return instructions
(specified by ‘s’)
The instruction set is highly orthogonal and is grouped
into four basic categories:
• The mode of the table read and table write
instructions (specified by ‘m’)
• Byte-oriented operations
• Bit-oriented operations
• Literal operations
• No operand required
(specified by ‘—’)
All instructions are a single word, except for three
double-word instructions. These three instructions
were made double-word instructions so that all the
required information is available in these 32 bits. In the
second word, the 4 MSbs are ‘1’s. If this second word
is executed as an instruction (by itself), it will execute
as a NOP.
• Control operations
The PIC18 instruction set summary in Table 25-2 lists
byte-oriented, bit-oriented, literal and control
operations. Table 25-1 shows the opcode field
descriptions.
Most byte-oriented instructions have three operands:
All single word instructions are executed in a single
instruction cycle unless a conditional test is true, or the
program counter is changed as a result of the instruc-
tion. In these cases, the execution takes two instruction
cycles with the additional instruction cycle(s) executed
as a NOP.
1. The file register (specified by ‘f’)
2. The destination of the result
(specified by ‘d’)
3. The accessed memory
(specified by ‘a’)
The file register designator ‘f’ specifies which file regis-
ter is to be used by the instruction.
The double-word instructions execute in two instruction
cycles.
The destination designator ‘d’ specifies where the
result of the operation is to be placed. If ‘d’ is zero, the
result is placed in the WREG register. If ‘d’ is one, the
result is placed in the file register specified in the
instruction.
One instruction cycle consists of four oscillator periods.
Thus, for an oscillator frequency of 4 MHz, the normal
instruction execution time is 1 µs. If a conditional test is
true or the program counter is changed as a result of an
instruction, the instruction execution time is 2 µs.
Two-word branch instructions (if true) would take 3 µs.
All bit-oriented instructions have three operands:
1. The file register (specified by ‘f’)
Figure 25-1 shows the general formats that the
instructions can have.
2. The bit in the file register
(specified by ‘b’)
All examples use the format ‘nnh’ to represent a hexa-
decimal number, where ‘h’ signifies a hexadecimal
digit.
3. The accessed memory
(specified by ‘a’)
The bit field designator ‘b’ selects the number of the bit
affected by the operation, while the file register desig-
nator ‘f’ represents the number of the file in which the
bit is located.
The Instruction Set Summary, shown in Table 25-2,
lists the instructions recognized by the Microchip
Assembler (MPASMTM).
Section 25.1 provides a description of each instruction.
2003 Microchip Technology Inc.
Advance Information
DS39612A-page 277
PIC18F6X2X/8X2X
TABLE 25-1: OPCODE FIELD DESCRIPTIONS
Field
Description
a
RAM access bit
a = 0: RAM location in Access RAM (BSR register is ignored)
a = 1: RAM bank is specified by BSR register
bbb
BSR
d
Bit address within an 8-bit file register (0 to 7)
Bank Select Register. Used to select the current RAM bank.
Destination select bit
d = 0: store result in WREG
d = 1: store result in file register f.
dest
f
Destination either the WREG register or the specified register file location
8-bit register file address (0x00 to 0xFF)
fs
12-bit register file address (0x000 to 0xFFF). This is the source address.
12-bit register file address (0x000 to 0xFFF). This is the destination address.
Literal field, constant data or label (may be either an 8-bit, 12-bit or a 20-bit value)
Label name
fd
k
label
mm
The mode of the TBLPTR register for the table read and table write instructions.
Only used with table read and table write instructions:
*
No change to register (such as TBLPTR with table reads and writes)
Post-Increment register (such as TBLPTR with table reads and writes)
Post-Decrement register (such as TBLPTR with table reads and writes)
Pre-Increment register (such as TBLPTR with table reads and writes)
*+
*-
+*
n
The relative address (2’s complement number) for relative branch instructions, or the direct address for call/
branch and return instructions
PRODH
PRODL
s
Product of Multiply High Byte
Product of Multiply Low Byte
Fast Call/Return mode select bit
s = 0: do not update into/from shadow registers
s = 1: certain registers loaded into/from shadow registers (Fast mode)
u
Unused or Unchanged
WREG
x
Working register (accumulator)
Don't care (0 or 1)
The assembler will generate code with x = 0. It is the recommended form of use for compatibility with all
Microchip software tools.
TBLPTR
21-bit Table Pointer (points to a Program Memory location)
8-bit Table Latch
TABLAT
TOS
Top-of-Stack
PC
Program Counter
PCL
Program Counter Low Byte
Program Counter High Byte
Program Counter High Byte Latch
Program Counter Upper Byte Latch
Global Interrupt Enable bit
Watchdog Timer
PCH
PCLATH
PCLATU
GIE
WDT
TO
Time-out bit
PD
Power-down bit
C, DC, Z, OV, N
ALU STATUS bits Carry, Digit Carry, Zero, Overflow, Negative
Optional
[
]
)
(
Contents
→
< >
∈
Assigned to
Register bit field
In the set of
italics
User defined term (font is courier)
DS39612A-page 278
Advance Information
2003 Microchip Technology Inc.
PIC18F6X2X/8X2X
FIGURE 25-1:
GENERAL FORMAT FOR INSTRUCTIONS
Byte-oriented file register operations
Example Instruction
15
10
OPCODE
9
8
7
0
ADDWF MYREG, W, B
d
a
f (FILE #)
d = 0 for result destination to be WREG register
d = 1 for result destination to be file register (f)
a = 0 to force Access Bank
a = 1 for BSR to select bank
f = 8-bit file register address
Byte to Byte move operations (2-word)
15
12 11
0
0
OPCODE
f (Source FILE #)
MOVFF MYREG1, MYREG2
15
12 11
1111
f (Destination FILE #)
f = 12-bit file register address
Bit-oriented file register operations
15 12 11 9 8
OPCODE b (BIT #)
7
0
BSF MYREG, bit, B
a
f (FILE #)
b = 3-bit position of bit in file register (f)
a = 0 to force Access Bank
a = 1 for BSR to select bank
f = 8-bit file register address
Literal operations
15
8
7
0
MOVLW 0x7F
OPCODE
k (literal)
k = 8-bit immediate value
Control operations
CALL, GOTO and Branch operations
15
8 7
0
GOTO Label
OPCODE
12 11
n<7:0> (literal)
15
0
1111
n<19:8> (literal)
n = 20-bit immediate value
15
15
8
7
0
CALL MYFUNC
OPCODE
12 11
n<7:0> (literal)
S
0
n<19:8> (literal)
S = Fast bit
11 10
15
0
0
BRA MYFUNC
BC MYFUNC
OPCODE
n<10:0> (literal)
15
OPCODE
8 7
n<7:0> (literal)
2003 Microchip Technology Inc.
Advance Information
DS39612A-page 279
PIC18F6X2X/8X2X
TABLE 25-2: PIC18FXXX INSTRUCTION SET
16-Bit Instruction Word
MSb LSb
Mnemonic,
Description
Operands
Status
Affected
Cycles
Notes
BYTE-ORIENTED FILE REGISTER OPERATIONS
ADDWF
f, d, a Add WREG and f
1
0010 01da ffff ffff C, DC, Z, OV, N 1, 2
0010 00da ffff ffff C, DC, Z, OV, N 1, 2
ADDWFC f, d, a Add WREG and Carry bit to f
ANDWF
CLRF
1
1
1
1
f, d, a AND WREG with f
f, a Clear f
f, d, a Complement f
0001 01da ffff ffff Z, N
0110 101a ffff ffff Z
0001 11da ffff ffff Z, N
1,2
2
1, 2
4
COMF
CPFSEQ
CPFSGT
CPFSLT
DECF
f, a
f, a
f, a
Compare f with WREG, skip =
Compare f with WREG, skip >
Compare f with WREG, skip <
1 (2 or 3) 0110 001a ffff ffff None
1 (2 or 3) 0110 010a ffff ffff None
1 (2 or 3) 0110 000a ffff ffff None
4
1, 2
f, d, a Decrement f
1
0000 01da ffff ffff C, DC, Z, OV, N 1, 2, 3, 4
DECFSZ
DCFSNZ
INCF
f, d, a Decrement f, Skip if 0
f, d, a Decrement f, Skip if Not 0
f, d, a Increment f
1 (2 or 3) 0010 11da ffff ffff None
1 (2 or 3) 0100 11da ffff ffff None
1, 2, 3, 4
1, 2
1
0010 10da ffff ffff C, DC, Z, OV, N 1, 2, 3, 4
INCFSZ
INFSNZ
IORWF
MOVF
f, d, a Increment f, Skip if 0
f, d, a Increment f, Skip if Not 0
f, d, a Inclusive OR WREG with f
f, d, a Move f
fs, fd Move fs (source) to 1st word
fd (destination) 2nd word
1 (2 or 3) 0011 11da ffff ffff None
1 (2 or 3) 0100 10da ffff ffff None
4
1, 2
1, 2
1
1
1
2
0001 00da ffff ffff Z, N
0101 00da ffff ffff Z, N
1100 ffff ffff ffff None
1111 ffff ffff ffff
MOVFF
MOVWF
MULWF
NEGF
RLCF
RLNCF
RRCF
f, a
f, a
f, a
Move WREG to f
Multiply WREG with f
Negate f
1
1
1
1
1
1
1
1
1
0110 111a ffff ffff None
0000 001a ffff ffff None
0110 110a ffff ffff C, DC, Z, OV, N 1, 2
0011 01da ffff ffff C, Z, N
0100 01da ffff ffff Z, N
0011 00da ffff ffff C, Z, N
0100 00da ffff ffff Z, N
0110 100a ffff ffff None
f, d, a Rotate Left f through Carry
f, d, a Rotate Left f (No Carry)
f, d, a Rotate Right f through Carry
f, d, a Rotate Right f (No Carry)
1, 2
RRNCF
SETF
f, a
Set f
SUBFWB f, d, a Subtract f from WREG with
borrow
0101 01da ffff ffff C, DC, Z, OV, N 1, 2
SUBWF
f, d, a Subtract WREG from f
1
1
0101 11da ffff ffff C, DC, Z, OV, N
0101 10da ffff ffff C, DC, Z, OV, N 1, 2
SUBWFB f, d, a Subtract WREG from f with
borrow
SWAPF
TSTFSZ
XORWF
f, d, a Swap nibbles in f
f, a Test f, skip if 0
f, d, a Exclusive OR WREG with f
1
0011 10da ffff ffff None
4
1, 2
1 (2 or 3) 0110 011a ffff ffff None
1
0001 10da ffff ffff Z, N
BIT-ORIENTED FILE REGISTER OPERATIONS
BCF
BSF
BTFSC
BTFSS
BTG
f, b, a Bit Clear f
f, b, a Bit Set f
f, b, a Bit Test f, Skip if Clear
f, b, a Bit Test f, Skip if Set
f, d, a Bit Toggle f
1
1
1001 bbba ffff ffff None
1000 bbba ffff ffff None
1, 2
1, 2
3, 4
3, 4
1, 2
1 (2 or 3) 1011 bbba ffff ffff None
1 (2 or 3) 1010 bbba ffff ffff None
1
0111 bbba ffff ffff None
Note 1: When a Port register is modified as a function of itself (e.g., MOVF PORTB, 1, 0), the value used will be that
value present on the pins themselves. For example, if the data latch is ‘1’ for a pin configured as an input and is
driven low by an external device, the data will be written back with a ‘0’.
2: If this instruction is executed on the TMR0 register (and where applicable, d = 1), the prescaler will be cleared if
assigned.
3: If Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The second
cycle is executed as a NOP.
4: Some instructions are 2-word instructions. The second word of these instructions will be executed as a NOP
unless the first word of the instruction retrieves the information embedded in these 16 bits. This ensures that all
program memory locations have a valid instruction.
5: If the table write starts the write cycle to internal memory, the write will continue until terminated.
DS39612A-page 280
Advance Information
2003 Microchip Technology Inc.
PIC18F6X2X/8X2X
TABLE 25-2: PIC18FXXX INSTRUCTION SET (CONTINUED)
16-Bit Instruction Word
MSb LSb
Mnemonic,
Operands
Status
Affected
Description
Cycles
Notes
CONTROL OPERATIONS
BC
BN
n
n
n
n
n
n
n
n
Branch if Carry
1 (2)
1 (2)
1 (2)
1 (2)
1 (2)
2
1 (2)
1 (2)
1 (2)
2
1110 0010 nnnn nnnn None
1110 0110 nnnn nnnn None
1110 0011 nnnn nnnn None
1110 0111 nnnn nnnn None
1110 0101 nnnn nnnn None
1110 0001 nnnn nnnn None
1110 0100 nnnn nnnn None
1101 0nnn nnnn nnnn None
1110 0000 nnnn nnnn None
1110 110s kkkk kkkk None
1111 kkkk kkkk kkkk
Branch if Negative
Branch if Not Carry
Branch if Not Negative
Branch if Not Overflow
Branch if Not Zero
Branch if Overflow
Branch Unconditionally
Branch if Zero
BNC
BNN
BNOV
BNZ
BOV
BRA
BZ
n
n, s
CALL
Call subroutine 1st word
2nd word
CLRWDT
DAW
GOTO
—
—
n
Clear Watchdog Timer
Decimal Adjust WREG
Go to address 1st word
2nd word
1
1
2
0000 0000 0000 0100 TO, PD
0000 0000 0000 0111 C
1110 1111 kkkk kkkk None
1111 kkkk kkkk kkkk
NOP
NOP
POP
PUSH
RCALL
RESET
RETFIE
—
—
—
—
n
No Operation
No Operation
1
1
1
1
2
1
2
0000 0000 0000 0000 None
1111 xxxx xxxx xxxx None
0000 0000 0000 0110 None
0000 0000 0000 0101 None
1101 1nnn nnnn nnnn None
0000 0000 1111 1111 All
0000 0000 0001 000s GIE/GIEH,
PEIE/GIEL
4
Pop top of return stack (TOS)
Push top of return stack (TOS)
Relative Call
Software device RESET
Return from interrupt enable
s
RETLW
RETURN
SLEEP
k
s
—
Return with literal in WREG
Return from Subroutine
Go into Standby mode
2
2
1
0000 1100 kkkk kkkk None
0000 0000 0001 001s None
0000 0000 0000 0011 TO, PD
Note 1: When a Port register is modified as a function of itself (e.g., MOVF PORTB, 1, 0), the value used will be that
value present on the pins themselves. For example, if the data latch is ‘1’ for a pin configured as an input and is
driven low by an external device, the data will be written back with a ‘0’.
2: If this instruction is executed on the TMR0 register (and where applicable, d = 1), the prescaler will be cleared if
assigned.
3: If Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The second
cycle is executed as a NOP.
4: Some instructions are 2-word instructions. The second word of these instructions will be executed as a NOP
unless the first word of the instruction retrieves the information embedded in these 16 bits. This ensures that all
program memory locations have a valid instruction.
5: If the table write starts the write cycle to internal memory, the write will continue until terminated.
2003 Microchip Technology Inc.
Advance Information
DS39612A-page 281
PIC18F6X2X/8X2X
TABLE 25-2: PIC18FXXX INSTRUCTION SET (CONTINUED)
16-Bit Instruction Word
Mnemonic,
Operands
Status
Affected
Description
Cycles
Notes
MSb
LSb
LITERAL OPERATIONS
ADDLW
ANDLW
IORLW
LFSR
k
k
k
f, k
Add literal and WREG
1
0000 1111 kkkk
0000 1011 kkkk
0000 1001 kkkk
1110 1110 00ff
1111 0000 kkkk
0000 0001 0000
0000 1110 kkkk
0000 1101 kkkk
0000 1100 kkkk
0000 1000 kkkk
0000 1010 kkkk
kkkk C, DC, Z, OV, N
kkkk Z, N
kkkk Z, N
kkkk None
kkkk
kkkk None
kkkk None
kkkk None
kkkk None
kkkk C, DC, Z, OV, N
kkkk Z, N
AND literal with WREG
Inclusive OR literal with WREG
Move literal (12-bit) 2nd word
to FSRx 1st word
Move literal to BSR<3:0>
Move literal to WREG
Multiply literal with WREG
Return with literal in WREG
Subtract WREG from literal
1
1
2
MOVLB
MOVLW
MULLW
RETLW
SUBLW
XORLW
k
k
k
k
k
k
1
1
1
2
1
Exclusive OR literal with WREG 1
DATA MEMORY ↔ PROGRAM MEMORY OPERATIONS
TBLRD*
Table Read
2
0000 0000 0000
0000 0000 0000
0000 0000 0000
0000 0000 0000
0000 0000 0000
0000 0000 0000
0000 0000 0000
0000 0000 0000
1000 None
1001 None
1010 None
1011 None
1100 None
1101 None
1110 None
1111 None
TBLRD*+
TBLRD*-
TBLRD+*
TBLWT*
TBLWT*+
TBLWT*-
TBLWT+*
Table Read with post-increment
Table Read with post-decrement
Table Read with pre-increment
Table Write
Table Write with post-increment
Table Write with post-decrement
Table Write with pre-increment
2 (5)
Note 1: When a Port register is modified as a function of itself (e.g., MOVF PORTB, 1, 0), the value used will be that
value present on the pins themselves. For example, if the data latch is ‘1’ for a pin configured as an input and is
driven low by an external device, the data will be written back with a ‘0’.
2: If this instruction is executed on the TMR0 register (and where applicable, d = 1), the prescaler will be cleared if
assigned.
3: If Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The second
cycle is executed as a NOP.
4: Some instructions are 2-word instructions. The second word of these instructions will be executed as a NOP
unless the first word of the instruction retrieves the information embedded in these 16 bits. This ensures that all
program memory locations have a valid instruction.
5: If the table write starts the write cycle to internal memory, the write will continue until terminated.
DS39612A-page 282
Advance Information
2003 Microchip Technology Inc.
PIC18F6X2X/8X2X
25.1 Instruction Set
ADDLW
ADD literal to W
ADDWF
ADD W to f
Syntax:
[ label ] ADDLW
0 ≤ k ≤ 255
k
Syntax:
[ label ] ADDWF
f [,d [,a] f [,d [,a]
Operands:
Operation:
Status Affected:
Encoding:
Operands:
0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
(W) + k → W
N, OV, C, DC, Z
Operation:
(W) + (f) → dest
0000
1111
kkkk
kkkk
Status Affected:
Encoding:
N, OV, C, DC, Z
Description:
The contents of W are added to the
8-bit literal ‘k’ and the result is
placed in W.
0010
01da
ffff
ffff
Description:
Add W to register ‘f’. If ‘d’ is 0, the
result is stored in W. If ‘d’ is 1, the
result is stored back in register ‘f’
(default). If ‘a’ is 0, the Access
Bank will be selected. If ‘a’ is 1, the
BSR is used.
Words:
Cycles:
1
1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
literal ‘k’
Process
Data
Write to W
Words:
Cycles:
1
1
Q Cycle Activity:
Q1
ADDLW
0x15
Example:
Q2
Q3
Q4
Before Instruction
Decode
Read
register ‘f’
Process
Data
Write to
destination
W
=
0x10
After Instruction
W
=
0x25
ADDWF
REG, 0, 0
Example:
Before Instruction
W
REG
=
=
0x17
0xC2
After Instruction
W
REG
=
=
0xD9
0xC2
2003 Microchip Technology Inc.
Advance Information
DS39612A-page 283
PIC18F6X2X/8X2X
ADDWFC
ADD W and Carry bit to f
ANDLW
AND literal with W
Syntax:
[ label ] ADDWFC
f [,d [,a]
Syntax:
[ label ] ANDLW
0 ≤ k ≤ 255
(W) .AND. k → W
N,Z
k
Operands:
0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
Operands:
Operation:
Status Affected:
Encoding:
Operation:
(W) + (f) + (C) → dest
0000
1011
kkkk
kkkk
Status Affected:
Encoding:
N,OV, C, DC, Z
Description:
The contents of W are ANDed with
the 8-bit literal ‘k’. The result is
placed in W.
0010
00da
ffff
ffff
Description:
Add W, the Carry Flag and data
memory location ‘f’. If ‘d’ is 0, the
result is placed in W. If ‘d’ is 1, the
result is placed in data memory loca-
tion ‘f’. If ‘a’ is 0, the Access Bank
will be selected. If ‘a’ is 1, the BSR
will not be overridden.
Words:
Cycles:
1
1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read literal
‘k’
Process
Data
Write to W
Words:
Cycles:
1
1
ANDLW
0x5F
Example:
Q Cycle Activity:
Q1
Before Instruction
Q2
Q3
Q4
W
=
0xA3
0x03
Decode
Read
register ‘f’
Process
Data
Write to
destination
After Instruction
W
=
ADDWFC
REG, 0, 1
Example:
Before Instruction
Carry bit =
1
REG
W
=
=
0x02
0x4D
After Instruction
Carry bit =
0
REG
W
=
=
0x02
0x50
DS39612A-page 284
Advance Information
2003 Microchip Technology Inc.
PIC18F6X2X/8X2X
ANDWF
AND W with f
BC
Branch if Carry
Syntax:
[ label ] ANDWF
f [,d [,a]
Syntax:
[ label ] BC
n
Operands:
0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
Operands:
Operation:
-128 ≤ n ≤ 127
if carry bit is ’1’
(PC) + 2 + 2n → PC
Operation:
(W) .AND. (f) → dest
Status Affected:
Encoding:
None
Status Affected:
Encoding:
N,Z
1110
0010
nnnn
nnnn
0001
01da
ffff
ffff
Description:
If the Carry bit is ‘1’, then the
program will branch.
Description:
The contents of W are AND’ed with
register ‘f’. If ‘d’ is 0, the result is
stored in W. If ‘d’ is 1, the result is
stored back in register ‘d’ (default).
If ‘a’ is 0, the Access Bank will be
selected. If ‘a’ is 1, the BSR will not
be overridden (default).
The 2’s complement number ‘2n’ is
added to the PC. Since the PC will
have incremented to fetch the next
instruction, the new address will be
PC+2+2n. This instruction is then
a two-cycle instruction.
Words:
Cycles:
1
1
Words:
Cycles:
1
1(2)
Q Cycle Activity:
Q1
Q Cycle Activity:
If Jump:
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Decode
Read
register ‘f’
Process
Data
Write to
destination
Decode
Read literal
‘n’
Process
Data
Write to PC
No
operation
No
operation
No
operation
No
operation
ANDWF
REG, 0, 0
Example:
Before Instruction
If No Jump:
Q1
W
REG
=
=
0x17
0xC2
Q2
Q3
Q4
Decode
Read literal
‘n’
Process
Data
No
operation
After Instruction
W
REG
=
=
0x02
0xC2
HERE
BC
5
Example:
Before Instruction
PC
=
address (HERE)
After Instruction
If Carry
PC
If Carry
PC
=
=
=
=
1;
address (HERE+12)
0;
address (HERE+2)
2003 Microchip Technology Inc.
Advance Information
DS39612A-page 285
PIC18F6X2X/8X2X
BCF
Bit Clear f
BN
Branch if Negative
[ label ] BN
Syntax:
[ label ] BCF f,b[,a]
Syntax:
n
Operands:
0 ≤ f ≤ 255
0 ≤ b ≤ 7
a ∈ [0,1]
Operands:
Operation:
-128 ≤ n ≤ 127
if negative bit is ’1’
(PC) + 2 + 2n → PC
Operation:
0 → f<b>
Status Affected:
Encoding:
None
Status Affected:
Encoding:
None
1110
0110
nnnn
nnnn
1001
bbba
ffff
ffff
Description:
If the Negative bit is ‘1’, then the
program will branch.
Description:
Bit ‘b’ in register ‘f’ is cleared. If ‘a’
is 0, the Access Bank will be
selected, overriding the BSR value.
If ‘a’ = 1, then the bank will be
selected as per the BSR value
(default).
The 2’s complement number ‘2n’ is
added to the PC. Since the PC will
have incremented to fetch the next
instruction, the new address will be
PC+2+2n. This instruction is then
a two-cycle instruction.
Words:
Cycles:
1
1
Words:
Cycles:
1
1(2)
Q Cycle Activity:
Q1
Q Cycle Activity:
If Jump:
Q2
Q3
Q4
Decode
Read
register ‘f’
Process
Data
Write
Q1
Q2
Q3
Q4
register ‘f’
Decode
Read literal
‘n’
Process
Data
Write to PC
BCF
FLAG_REG, 7, 0
Example:
No
operation
No
operation
No
operation
No
operation
Before Instruction
FLAG_REG
=
=
0xC7
0x47
If No Jump:
Q1
After Instruction
FLAG_REG
Q2
Q3
Q4
Decode
Read literal
‘n’
Process
Data
No
operation
HERE
BN Jump
Example:
Before Instruction
PC
=
address (HERE)
After Instruction
If Negative
PC
If Negative
PC
=
=
=
=
1;
address (Jump)
0;
address (HERE+2)
DS39612A-page 286
Advance Information
2003 Microchip Technology Inc.
PIC18F6X2X/8X2X
BNC
Branch if Not Carry
BNN
Branch if Not Negative
Syntax:
[ label ] BNC
-128 ≤ n ≤ 127
if carry bit is ’0’
n
Syntax:
[ label ] BNN
-128 ≤ n ≤ 127
n
Operands:
Operation:
Operands:
Operation:
if negative bit is ’0’
(PC) + 2 + 2n → PC
(PC) + 2 + 2n → PC
Status Affected:
Encoding:
None
Status Affected:
Encoding:
None
1110
0011
nnnn
nnnn
1110
0111
nnnn
nnnn
Description:
If the Carry bit is ‘0’, then the
program will branch.
Description:
If the Negative bit is ‘0’, then the
program will branch.
The 2’s complement number ‘2n’ is
added to the PC. Since the PC will
have incremented to fetch the next
instruction, the new address will be
PC+2+2n. This instruction is then
a two-cycle instruction.
The 2’s complement number ‘2n’ is
added to the PC. Since the PC will
have incremented to fetch the next
instruction, the new address will be
PC+2+2n. This instruction is then
a two-cycle instruction.
Words:
Cycles:
1
Words:
Cycles:
1
1(2)
1(2)
Q Cycle Activity:
If Jump:
Q Cycle Activity:
If Jump:
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Decode
Read literal
‘n’
Process
Data
Write to PC
Decode
Read literal
‘n’
Process
Data
Write to PC
No
No
No
No
No
No
No
No
operation
operation
operation
operation
operation
operation
operation
operation
If No Jump:
Q1
If No Jump:
Q1
Q2
Q3
Q4
Q2
Q3
Q4
Decode
Read literal
‘n’
Process
Data
No
operation
Decode
Read literal
‘n’
Process
Data
No
operation
HERE
BNC Jump
HERE
BNN Jump
Example:
Example:
Before Instruction
Before Instruction
PC
=
address (HERE)
PC
=
address (HERE)
After Instruction
After Instruction
If Carry
PC
If Carry
PC
=
=
=
=
0;
If Negative
PC
If Negative
PC
=
=
=
=
0;
address (Jump)
1;
address (HERE+2)
address (Jump)
1;
address (HERE+2)
2003 Microchip Technology Inc.
Advance Information
DS39612A-page 287
PIC18F6X2X/8X2X
BNOV
Branch if Not Overflow
BNZ
Branch if Not Zero
Syntax:
[ label ] BNOV
-128 ≤ n ≤ 127
n
Syntax:
[ label ] BNZ
-128 ≤ n ≤ 127
if zero bit is ’0’
n
Operands:
Operation:
Operands:
Operation:
if overflow bit is ’0’
(PC) + 2 + 2n → PC
(PC) + 2 + 2n → PC
Status Affected:
Encoding:
None
Status Affected:
Encoding:
None
1110
0101
nnnn
nnnn
1110
0001
nnnn
nnnn
Description:
If the Overflow bit is ‘0’, then the
program will branch.
Description:
If the Zero bit is ‘0’, then the
program will branch.
The 2’s complement number ‘2n’ is
added to the PC. Since the PC will
have incremented to fetch the next
instruction, the new address will be
PC+2+2n. This instruction is then
a two-cycle instruction.
The 2’s complement number ‘2n’ is
added to the PC. Since the PC will
have incremented to fetch the next
instruction, the new address will be
PC+2+2n. This instruction is then
a two-cycle instruction.
Words:
Cycles:
1
Words:
Cycles:
1
1(2)
1(2)
Q Cycle Activity:
If Jump:
Q Cycle Activity:
If Jump:
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Decode
Read literal
‘n’
Process
Data
Write to PC
Decode
Read literal
‘n’
Process
Data
Write to PC
No
No
No
No
No
No
No
No
operation
operation
operation
operation
operation
operation
operation
operation
If No Jump:
Q1
If No Jump:
Q1
Q2
Q3
Q4
Q2
Q3
Q4
Decode
Read literal
‘n’
Process
Data
No
operation
Decode
Read literal
‘n’
Process
Data
No
operation
HERE
BNOV Jump
HERE
BNZ Jump
Example:
Example:
Before Instruction
Before Instruction
PC
=
address (HERE)
PC
=
address (HERE)
After Instruction
After Instruction
If Overflow
PC
If Overflow
PC
=
=
=
=
0;
If Zero
PC
If Zero
PC
=
=
=
=
0;
address (Jump)
1;
address (HERE+2)
address (Jump)
1;
address (HERE+2)
DS39612A-page 288
Advance Information
2003 Microchip Technology Inc.
PIC18F6X2X/8X2X
BRA
Unconditional Branch
[ label ] BRA
BSF
Bit Set f
Syntax:
n
Syntax:
[ label ] BSF f,b[,a]
Operands:
Operation:
Status Affected:
Encoding:
-1024 ≤ n ≤ 1023
(PC) + 2 + 2n → PC
None
Operands:
0 ≤ f ≤ 255
0 ≤ b ≤ 7
a ∈ [0,1]
Operation:
1 → f<b>
1101
0nnn
nnnn
nnnn
Status Affected:
Encoding:
None
Description:
Add the 2’s complement number
‘2n’ to the PC. Since the PC will
have incremented to fetch the next
instruction, the new address will be
PC+2+2n. This instruction is a
two-cycle instruction.
1000
bbba
ffff
ffff
Description:
Bit ‘b’ in register ‘f’ is set. If ‘a’ is 0,
Access Bank will be selected, over-
riding the BSR value. If ‘a’ = 1, then
the bank will be selected as per the
BSR value.
Words:
Cycles:
1
2
Words:
Cycles:
1
1
Q Cycle Activity:
Q1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Q2
Q3
Q4
Decode
Read literal
‘n’
Process
Data
Write to PC
Decode
Read
register ‘f’
Process
Data
Write
register ‘f’
No
No
No
No
operation
operation
operation
operation
BSF
FLAG_REG, 7, 1
Example:
Before Instruction
HERE
BRA Jump
Example:
FLAG_REG
=
=
0x0A
0x8A
Before Instruction
After Instruction
FLAG_REG
PC
=
address (HERE)
address (Jump)
After Instruction
PC
=
2003 Microchip Technology Inc.
Advance Information
DS39612A-page 289
PIC18F6X2X/8X2X
BTFSC
Bit Test File, Skip if Clear
BTFSS
Bit Test File, Skip if Set
Syntax:
[ label ] BTFSC f,b[,a]
Syntax:
[ label ] BTFSS f,b[,a]
Operands:
0 ≤ f ≤ 255
0 ≤ b ≤ 7
a ∈ [0,1]
Operands:
0 ≤ f ≤ 255
0 ≤ b < 7
a ∈ [0,1]
Operation:
skip if (f<b>) = 0
None
Operation:
skip if (f<b>) = 1
None
Status Affected:
Encoding:
Status Affected:
Encoding:
1011
bbba
ffff
ffff
1010
bbba
ffff
ffff
Description:
If bit ‘b’ in register ‘f’ is 0, then the
next instruction is skipped.
Description:
If bit ‘b’ in register ‘f’ is 1, then the
next instruction is skipped.
If bit ‘b’ is 0, then the next instruction
fetched during the current instruction
execution is discarded and a NOPis
executed instead, making this a
two-cycle instruction. If ‘a’ is 0, the
Access Bank will be selected, over-
riding the BSR value. If ‘a’ = 1, then
the bank will be selected as per the
BSR value (default).
If bit ‘b’ is 1, then the next instruction
fetched during the current instruc-
tion execution, is discarded and a
NOPis executed instead, making this
a two-cycle instruction. If ‘a’ is 0, the
Access Bank will be selected, over-
riding the BSR value. If ‘a’ = 1, then
the bank will be selected as per the
BSR value (default).
Words:
Cycles:
1
Words:
Cycles:
1
1(2)
1(2)
Note: 3 cycles if skip and followed
by a 2-word instruction.
Note: 3 cycles if skip and followed
by a 2-word instruction.
Q Cycle Activity:
Q1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Q2
Q3
Q4
Decode
Read
Process Data
No
Decode
Read
Process Data
No
register ‘f’
operation
register ‘f’
operation
If skip:
Q1
If skip:
Q1
Q2
Q3
Q4
Q2
Q3
Q4
No
No
No
No
No
No
No
No
operation
operation
operation
operation
operation
operation
operation
operation
If skip and followed by 2-word instruction:
If skip and followed by 2-word instruction:
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
No
No
No
No
No
No
No
No
operation
operation
operation
operation
operation
operation
operation
operation
No
No
No
No
No
No
No
No
operation
operation
operation
operation
operation
operation
operation
operation
HERE
FALSE
TRUE
BTFSC
:
:
FLAG, 1, 0
HERE
FALSE
TRUE
BTFSS
:
:
FLAG, 1, 0
Example:
Example:
Before Instruction
PC
Before Instruction
PC
=
address (HERE)
=
address (HERE)
After Instruction
After Instruction
If FLAG<1>
PC
If FLAG<1>
PC
=
=
=
=
0;
If FLAG<1>
PC
If FLAG<1>
PC
=
=
=
=
0;
address (TRUE)
1;
address (FALSE)
address (FALSE)
1;
address (TRUE)
DS39612A-page 290
Advance Information
2003 Microchip Technology Inc.
PIC18F6X2X/8X2X
BTG
Bit Toggle f
BOV
Branch if Overflow
Syntax:
[ label ] BTG f,b[,a]
Syntax:
[ label ] BOV
-128 ≤ n ≤ 127
n
Operands:
0 ≤ f ≤ 255
0 ≤ b < 7
a ∈ [0,1]
Operands:
Operation:
if overflow bit is ’1’
(PC) + 2 + 2n → PC
Operation:
(f<b>) → f<b>
Status Affected:
Encoding:
None
Status Affected:
Encoding:
None
1110
0100
nnnn
nnnn
0111
bbba
ffff
ffff
Description:
If the Overflow bit is ‘1’, then the
program will branch.
Description:
Bit ‘b’ in data memory location ‘f’ is
inverted. If ‘a’ is 0, the Access Bank
will be selected, overriding the BSR
value. If ‘a’ = 1, then the bank will be
selected as per the BSR value
(default).
The 2’s complement number ‘2n’ is
added to the PC. Since the PC will
have incremented to fetch the next
instruction, the new address will be
PC+2+2n. This instruction is then
a two-cycle instruction.
Words:
Cycles:
1
1
Words:
Cycles:
1
1(2)
Q Cycle Activity:
Q1
Q Cycle Activity:
If Jump:
Q2
Q3
Q4
Decode
Read
register ‘f’
Process
Data
Write
Q1
Q2
Q3
Q4
register ‘f’
Decode
Read literal
‘n’
Process
Data
Write to PC
BTG
PORTC, 4, 0
Example:
No
operation
No
operation
No
operation
No
operation
Before Instruction:
PORTC
=
0111 0101 [0x75]
If No Jump:
Q1
After Instruction:
Q2
Q3
Q4
PORTC
=
0110 0101 [0x65]
Decode
Read literal
‘n’
Process
Data
No
operation
HERE
BOV Jump
Example:
Before Instruction
PC
=
address (HERE)
After Instruction
If Overflow
PC
If Overflow
PC
=
=
=
=
1;
address (Jump)
0;
address (HERE+2)
2003 Microchip Technology Inc.
Advance Information
DS39612A-page 291
PIC18F6X2X/8X2X
BZ
Branch if Zero
[ label ] BZ
CALL
Subroutine Call
Syntax:
n
Syntax:
[ label ] CALL k [,s]
Operands:
Operation:
-128 ≤ n ≤ 127
Operands:
0 ≤ k ≤ 1048575
s ∈ [0,1]
if Zero bit is ’1’
(PC) + 2 + 2n → PC
Operation:
(PC) + 4 → TOS,
k → PC<20:1>,
if s = 1
Status Affected:
Encoding:
None
1110
0000
nnnn
nnnn
(W) → WS,
(STATUS) → STATUSS,
(BSR) → BSRS
Description:
If the Zero bit is ‘1’, then the
program will branch.
The 2’s complement number ‘2n’ is
added to the PC. Since the PC will
have incremented to fetch the next
instruction, the new address will be
PC+2+2n. This instruction is then
a two-cycle instruction.
Status Affected:
None
Encoding:
1st word (k<7:0>)
2nd word(k<19:8>)
1110
1111
110s
k kkk
kkkk
kkkk
7
0
8
k
kkk kkkk
19
Description:
Subroutine call of entire 2 Mbyte
memory range. First, return
address (PC+ 4) is pushed onto the
return stack. If ‘s’ = 1, the W,
Words:
Cycles:
1
1(2)
STATUS and BSR registers are
also pushed into their respective
shadow registers, WS, STATUSS
and BSRS. If ‘s’ = 0, no update
occurs (default). Then, the 20-bit
value ‘k’ is loaded into PC<20:1>.
CALLis a two-cycle instruction.
Q Cycle Activity:
If Jump:
Q1
Q2
Q3
Q4
Decode
Read literal
‘n’
Process
Data
Write to PC
No
operation
No
operation
No
operation
No
operation
Words:
Cycles:
2
2
If No Jump:
Q1
Q2
Q3
Q4
Decode
Read literal
‘n’
Process
Data
No
operation
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read literal Push PC to Read literal
HERE
BZ Jump
Example:
‘k’<7:0>,
stack
‘k’<19:8>,
Write to PC
Before Instruction
PC
=
address (HERE)
1;
address (Jump)
0;
No
operation
No
operation
No
operation
No
operation
After Instruction
If Zero
PC
If Zero
PC
=
=
=
=
HERE
CALL THERE,1
Example:
address (HERE+2)
Before Instruction
PC
=
address (HERE)
After Instruction
PC
TOS
WS
=
=
=
=
address (THERE)
address (HERE + 4)
W
BSR
BSRS
STATUSS=
STATUS
DS39612A-page 292
Advance Information
2003 Microchip Technology Inc.
PIC18F6X2X/8X2X
CLRF
Clear f
CLRWDT
Clear Watchdog Timer
Syntax:
[ label ] CLRF f [,a]
Syntax:
[ label ] CLRWDT
Operands:
0 ≤ f ≤ 255
a ∈ [0,1]
Operands:
Operation:
None
000h → WDT,
000h → WDT postscaler,
1 → TO,
Operation:
000h → f
1 → Z
1 → PD
Status Affected:
Encoding:
Z
Status Affected:
Encoding:
TO, PD
0110
101a
ffff
ffff
0000
0000
0000
0100
Description:
Clears the contents of the specified
register. If ‘a’ is 0, the Access Bank
will be selected, overriding the BSR
value. If ‘a’ = 1, then the bank will
be selected as per the BSR value
(default).
Description:
CLRWDTinstruction resets the
Watchdog Timer. It also resets the
postscaler of the WDT. STATUS
bits TO and PD are set.
Words:
Cycles:
1
1
Words:
Cycles:
1
1
Q Cycle Activity:
Q1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Q2
Q3
Q4
Decode
No
operation
Process
Data
No
operation
Decode
Read
register ‘f’
Process
Data
Write
register ‘f’
CLRWDT
Example:
CLRF
FLAG_REG,1
Example:
Before Instruction
WDT Counter
=
?
Before Instruction
FLAG_REG
=
=
0x5A
0x00
After Instruction
WDT Counter
WDT Postscaler
TO
PD
=
=
=
=
0x00
After Instruction
FLAG_REG
0
1
1
2003 Microchip Technology Inc.
Advance Information
DS39612A-page 293
PIC18F6X2X/8X2X
COMF
Complement f
CPFSEQ
Compare f with W, skip if f = W
Syntax:
[ label ] COMF f [,d [,a]
Syntax:
[ label ] CPFSEQ f [,a]
Operands:
0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
Operands:
0 ≤ f ≤ 255
a ∈ [0,1]
Operation:
(f) – (W),
Operation:
(f) → dest
skip if (f) = (W)
(unsigned comparison)
Status Affected:
Encoding:
N, Z
Status Affected:
Encoding:
None
0001
11da
ffff
ffff
0110
001a
ffff
ffff
Description:
The contents of register ‘f’ are com-
plemented. If ‘d’ is 0, the result is
stored in W. If ‘d’ is 1, the result is
stored back in register ‘f’ (default).
If ‘a’ is 0, the Access Bank will be
selected, overriding the BSR value.
If ‘a’ = 1, then the bank will be
selected as per the BSR value
(default).
Description:
Compares the contents of data
memory location ‘f’ to the contents
of W by performing an unsigned
subtraction.
If ‘f’ = W, then the fetched
instruction is discarded and a NOP
is executed instead, making this a
two-cycle instruction. If ‘a’ is 0, the
Access Bank will be selected, over-
riding the BSR value. If ‘a’ = 1, then
the bank will be selected as per the
BSR value (default).
Words:
Cycles:
1
1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Words:
Cycles:
1
Decode
Read
register ‘f’
Process
Data
Write to
1(2)
destination
Note: 3 cycles if skip and followed
by a 2-word instruction.
COMF
REG, 0, 0
Example:
Before Instruction
Q Cycle Activity:
Q1
REG
=
0x13
Q2
Q3
Q4
After Instruction
Decode
Read
register ‘f’
Process
Data
No
operation
REG
=
0x13
W
=
0xEC
If skip:
Q1
Q2
Q3
Q4
No
No
No
No
operation
operation
operation
operation
If skip and followed by 2-word instruction:
Q1
Q2
Q3
Q4
No
No
No
No
operation
operation
operation
operation
No
No
No
No
operation
operation
operation
operation
HERE
CPFSEQ REG, 0
Example:
NEQUAL
EQUAL
:
:
Before Instruction
PC Address
=
HERE
W
REG
=
=
?
?
After Instruction
If REG
PC
=
=
W;
Address (EQUAL)
If REG
PC
≠
=
W;
Address (NEQUAL)
DS39612A-page 294
Advance Information
2003 Microchip Technology Inc.
PIC18F6X2X/8X2X
CPFSGT
Compare f with W, skip if f > W
CPFSLT
Compare f with W, skip if f < W
Syntax:
[ label ] CPFSGT f [,a]
Syntax:
[ label ] CPFSLT f [,a]
Operands:
0 ≤ f ≤ 255
a ∈ [0,1]
Operands:
0 ≤ f ≤ 255
a ∈ [0,1]
Operation:
(f) − (W),
Operation:
(f) – (W),
skip if (f) > (W)
(unsigned comparison)
skip if (f) < (W)
(unsigned comparison)
Status Affected:
Encoding:
None
Status Affected:
Encoding:
None
0110
010a
ffff
ffff
0110
000a
ffff
ffff
Description:
Compares the contents of data
memory location ‘f’ to the contents
of the W by performing an
Description:
Compares the contents of data
memory location ‘f’ to the contents
of W by performing an unsigned
subtraction.
unsigned subtraction.
If the contents of ‘f’ are greater than
the contents of WREG, then the
fetched instruction is discarded and
a NOPis executed instead, making
this a two-cycle instruction. If ‘a’ is
0, the Access Bank will be
selected, overriding the BSR value.
If ‘a’ = 1, then the bank will be
selected as per the BSR value
(default).
If the contents of ‘f’ are less than
the contents of W, then the fetched
instruction is discarded and a NOP
is executed instead, making this a
two-cycle instruction. If ‘a’ is 0, the
Access Bank will be selected. If ‘a’
is 1, the BSR will not be overridden
(default).
Words:
Cycles:
1
1(2)
Words:
Cycles:
1
Note: 3 cycles if skip and followed
by a 2-word instruction.
1(2)
Note: 3 cycles if skip and followed
by a 2-word instruction.
Q Cycle Activity:
Q1
Q2
Q3
Q4
Q Cycle Activity:
Q1
Decode
Read
register ‘f’
Process
Data
No
operation
Q2
Q3
Q4
Decode
Read
register ‘f’
Process
Data
No
operation
If skip:
Q1
Q2
Q3
Q4
If skip:
Q1
No
operation
No
operation
No
operation
No
operation
Q2
Q3
Q4
No
operation
No
operation
No
operation
No
operation
If skip and followed by 2-word instruction:
Q1
Q2
Q3
Q4
If skip and followed by 2-word instruction:
No
No
No
No
Q1
Q2
Q3
Q4
operation
operation
operation
operation
No
No
No
No
No
No
No
No
operation
operation
operation
operation
operation
operation
operation
operation
No
No
No
No
operation
operation
operation
operation
HERE
NLESS
LESS
CPFSLT REG, 1
:
:
Example:
HERE
CPFSGT REG, 0
Example:
NGREATER
GREATER
:
:
Before Instruction
PC
W
=
=
Address (HERE)
?
Before Instruction
After Instruction
PC
=
Address (HERE)
W
=
?
If REG
PC
If REG
PC
<
=
≥
=
W;
Address (LESS)
W;
Address (NLESS)
After Instruction
If REG
PC
>
=
W;
Address (GREATER)
If REG
PC
≤
=
W;
Address (NGREATER)
2003 Microchip Technology Inc.
Advance Information
DS39612A-page 295
PIC18F6X2X/8X2X
DAW
Decimal Adjust W Register
DECF
Decrement f
Syntax:
[ label ] DAW
Syntax:
[ label ] DECF f [,d [,a]
Operands:
Operation:
None
Operands:
0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
If [W<3:0> >9] or [DC = 1] then
(W<3:0>) + 6 → W<3:0>;
else
(W<3:0>) → W<3:0>;
Operation:
(f) – 1 → dest
Status Affected:
Encoding:
C, DC, N, OV, Z
0000
01da
ffff
ffff
If [W<7:4> >9] or [C = 1] then
(W<7:4>) + 6 → W<7:4>;
else
Description:
Decrement register ‘f’. If ‘d’ is 0, the
result is stored in W. If ‘d’ is 1, the
result is stored back in register ‘f’
(default). If ‘a’ is 0, the Access
Bank will be selected, overriding
the BSR value. If ‘a’ = 1, then the
bank will be selected as per the
BSR value (default).
(W<7:4>) → W<7:4>;
Status Affected:
Encoding:
C
0000
0000
0000
0111
Description:
DAW adjusts the eight-bit value in
W resulting from the earlier addition
of two variables (each in packed
BCD format) and produces a
correct packed BCD result.
Words:
Cycles:
1
1
Q Cycle Activity:
Q1
Words:
Cycles:
1
1
Q2
Q3
Q4
Decode
Read
register ‘f’
Process
Data
Write to
destination
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
register W
Process
Data
Write
W
DECF
CNT,
1, 0
Example:
Before Instruction
CNT
Z
=
=
0x01
0
DAW
Example1:
Before Instruction
After Instruction
CNT
Z
=
=
0x00
1
W
C
DC
=
=
=
0xA5
0
0
After Instruction
W
=
0x05
C
DC
=
=
1
0
Example 2:
Before Instruction
W
=
0xCE
C
DC
=
=
0
0
After Instruction
W
=
0x34
C
DC
=
=
1
0
DS39612A-page 296
Advance Information
2003 Microchip Technology Inc.
PIC18F6X2X/8X2X
DECFSZ
Decrement f, skip if 0
DCFSNZ
Decrement f, skip if not 0
Syntax:
[ label ] DECFSZ f [,d [,a]]
Syntax:
[ label ] DCFSNZ f [,d [,a]
Operands:
0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
Operands:
0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
Operation:
(f) – 1 → dest,
skip if result = 0
Operation:
(f) – 1 → dest,
skip if result ≠ 0
Status Affected:
Encoding:
None
Status Affected:
Encoding:
None
0010
11da
ffff
ffff
0100
11da
ffff
ffff
Description:
The contents of register ‘f’ are dec-
remented. If ‘d’ is 0, the result is
placed in W. If ‘d’ is 1, the result is
placed back in register ‘f’ (default).
If the result is 0, the next instruc-
tion which is already fetched is
discarded and a NOPis executed
instead, making it a two-cycle
instruction. If ‘a’ is 0, the Access
Bank will be selected, overriding
the BSR value. If ‘a’ = 1, then the
bank will be selected as per the
BSR value (default).
Description:
The contents of register ‘f’ are dec-
remented. If ‘d’ is 0, the result is
placed in W. If ‘d’ is 1, the result is
placed back in register ‘f’ (default).
If the result is 0, the next instruc-
tion which is already fetched is
discarded and a NOPis executed
instead, making it a two-cycle
instruction. If ‘a’ is 0, the Access
Bank will be selected, overriding
the BSR value. If ‘a’ = 1, then the
bank will be selected as per the
BSR value (default).
Words:
Cycles:
1
Words:
Cycles:
1
1(2)
1(2)
Note: 3 cycles if skip and followed
by a 2-word instruction.
Note: 3 cycles if skip and followed
by a 2-word instruction.
Q Cycle Activity:
Q1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Q2
Q3
Q4
Decode
Read
register ‘f’
Process
Data
Write to
destination
Decode
Read
register ‘f’
Process
Data
Write to
destination
If skip:
Q1
If skip:
Q1
Q2
Q3
Q4
Q2
Q3
Q4
No
No
No
No
No
No
No
No
operation
operation
operation
operation
operation
operation
operation
operation
If skip and followed by 2-word instruction:
If skip and followed by 2-word instruction:
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
No
No
No
No
No
No
No
No
operation
operation
operation
operation
operation
operation
operation
operation
No
No
No
No
No
No
No
No
operation
operation
operation
operation
operation
operation
operation
operation
HERE
DECFSZ
GOTO
CNT, 1, 1
LOOP
HERE
ZERO
NZERO
DCFSNZ TEMP, 1, 0
:
:
Example:
Example:
CONTINUE
Before Instruction
Before Instruction
TEMP
PC
=
Address (HERE)
=
?
After Instruction
After Instruction
CNT
If CNT
PC
If CNT
PC
=
=
=
≠
=
CNT - 1
0;
Address (CONTINUE)
0;
TEMP
If TEMP
PC
If TEMP
PC
=
=
=
≠
=
TEMP - 1,
0;
Address (ZERO)
0;
Address (NZERO)
Address (HERE+2)
2003 Microchip Technology Inc.
Advance Information
DS39612A-page 297
PIC18F6X2X/8X2X
GOTO
Unconditional Branch
INCF
Increment f
Syntax:
[ label ] GOTO k
0 ≤ k ≤ 1048575
k → PC<20:1>
None
Syntax:
[ label ] INCF f [,d [,a]
Operands:
Operation:
Status Affected:
Operands:
0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
Operation:
(f) + 1 → dest
Encoding:
1st word (k<7:0>)
2nd word(k<19:8>)
Status Affected:
Encoding:
C, DC, N, OV, Z
1110
1111
1111
k kkk
kkkk
kkkk
7
0
8
k
kkk kkkk
0010
10da
ffff
ffff
19
Description:
GOTOallows an unconditional
branch anywhere within entire
2 Mbyte memory range. The 20-bit
value ‘k’ is loaded into PC<20:1>.
GOTOis always a two-cycle
instruction.
Description:
The contents of register ‘f’ are
incremented. If ‘d’ is 0, the result is
placed in W. If ‘d’ is 1, the result is
placed back in register ‘f’ (default).
If ‘a’ is 0, the Access Bank will be
selected, overriding the BSR value.
If ‘a’ = 1, then the bank will be
selected as per the BSR value
(default).
Words:
Cycles:
2
2
Q Cycle Activity:
Q1
Words:
Cycles:
1
1
Q2
Q3
Q4
Decode
Read literal
‘k’<7:0>,
No
operation
Read literal
‘k’<19:8>,
Write to PC
Q Cycle Activity:
Q1
Q2
Q3
Q4
No
operation
No
operation
No
operation
No
operation
Decode
Read
register ‘f’
Process
Data
Write to
destination
GOTO THERE
Example:
INCF
CNT, 1, 0
Example:
After Instruction
Before Instruction
PC
=
Address (THERE)
CNT
Z
=
0xFF
=
=
=
0
?
?
C
DC
After Instruction
CNT
Z
C
=
=
=
=
0x00
1
1
1
DC
DS39612A-page 298
Advance Information
2003 Microchip Technology Inc.
PIC18F6X2X/8X2X
INCFSZ
Increment f, skip if 0
INFSNZ
Increment f, skip if not 0
Syntax:
[ label ] INCFSZ f [,d [,a]
Syntax:
[ label ] INFSNZ f [,d [,a]
Operands:
0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
Operands:
0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
Operation:
(f) + 1 → dest,
skip if result = 0
Operation:
(f) + 1 → dest,
skip if result ≠ 0
Status Affected:
Encoding:
None
Status Affected:
Encoding:
None
0011
11da
ffff
ffff
0100
10da
ffff
ffff
Description:
The contents of register ‘f’ are
incremented. If ‘d’ is 0, the result is
placed in W. If ‘d’ is 1, the result is
placed back in register ‘f’ (default).
If the result is 0, the next instruction
which is already fetched is dis-
carded and a NOPis executed
instead, making it a two-cycle
instruction. If ‘a’ is 0, the Access
Bank will be selected, overriding
the BSR value. If ‘a’ = 1, then the
bank will be selected as per the
BSR value (default).
Description:
The contents of register ‘f’ are
incremented. If ‘d’ is 0, the result is
placed in W. If ‘d’ is 1, the result is
placed back in register ‘f’ (default).
If the result is 0, the next instruction
which is already fetched is dis-
carded and a NOPis executed
instead, making it a two-cycle
instruction. If ‘a’ is 0, the Access
Bank will be selected, overriding
the BSR value. If ‘a’ = 1, then the
bank will be selected as per the
BSR value (default).
Words:
Cycles:
1
Words:
Cycles:
1
1(2)
1(2)
Note: 3 cycles if skip and followed
by a 2-word instruction.
Note: 3 cycles if skip and followed
by a 2-word instruction.
Q Cycle Activity:
Q1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Q2
Q3
Q4
Decode
Read
register ‘f’
Process
Data
Write to
destination
Decode
Read
register ‘f’
Process
Data
Write to
destination
If skip:
Q1
If skip:
Q1
Q2
Q3
Q4
Q2
Q3
Q4
No
No
No
No
No
No
No
No
operation
operation
operation
operation
operation
operation
operation
operation
If skip and followed by 2-word instruction:
If skip and followed by 2-word instruction:
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
No
No
No
No
No
No
No
No
operation
operation
operation
operation
operation
operation
operation
operation
No
No
No
No
No
No
No
No
operation
operation
operation
operation
operation
operation
operation
operation
HERE
NZERO
ZERO
INCFSZ
:
:
CNT, 1, 0
HERE
ZERO
NZERO
INFSNZ REG, 1, 0
Example:
Example:
Before Instruction
Before Instruction
PC
=
Address (HERE)
PC
=
Address (HERE)
After Instruction
After Instruction
CNT
If CNT
PC
If CNT
PC
=
=
=
≠
=
CNT + 1
0;
Address (ZERO)
0;
Address (NZERO)
REG
If REG
PC
If REG
PC
=
≠
=
=
=
REG + 1
0;
Address (NZERO)
0;
Address (ZERO)
2003 Microchip Technology Inc.
Advance Information
DS39612A-page 299
PIC18F6X2X/8X2X
IORLW
Inclusive OR literal with W
IORWF
Inclusive OR W with f
Syntax:
[ label ] IORLW k
0 ≤ k ≤ 255
Syntax:
[ label ] IORWF f [,d [,a]
Operands:
Operation:
Status Affected:
Encoding:
Operands:
0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
(W) .OR. k → W
N, Z
Operation:
(W) .OR. (f) → dest
0000
1001
kkkk
kkkk
Status Affected:
Encoding:
N, Z
Description:
The contents of W are OR’ed with
the eight-bit literal ‘k’. The result is
placed in W.
0001
00da
ffff
ffff
Description:
Inclusive OR W with register ‘f’. If
‘d’ is 0, the result is placed in W. If
‘d’ is 1, the result is placed back in
register ‘f’ (default). If ‘a’ is 0, the
Access Bank will be selected, over-
riding the BSR value. If ‘a’ = 1, then
the bank will be selected as per the
BSR value (default).
Words:
Cycles:
1
1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
literal ‘k’
Process
Data
Write to W
Words:
Cycles:
1
1
IORLW
0x35
Example:
Before Instruction
Q Cycle Activity:
Q1
W
=
0x9A
Q2
Q3
Q4
Decode
Read
register ‘f’
Process
Data
Write to
destination
After Instruction
W
=
0xBF
IORWF RESULT, 0, 1
Example:
Before Instruction
RESULT =
0x13
0x91
W
=
After Instruction
RESULT =
0x13
0x93
W
=
DS39612A-page 300
Advance Information
2003 Microchip Technology Inc.
PIC18F6X2X/8X2X
LFSR
Load FSR
MOVF
Move f
Syntax:
[ label ] LFSR f,k
Syntax:
[ label ] MOVF f [,d [,a]
Operands:
0 ≤ f ≤ 2
Operands:
0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
0 ≤ k ≤ 4095
Operation:
k → FSRf
Operation:
f → dest
Status Affected:
Encoding:
None
Status Affected:
Encoding:
N, Z
1110
1111
1110
0000
00ff
k kkk
11
kkkk
k kkk
0101
00da
ffff
ffff
7
Description:
The 12-bit literal ‘k’ is loaded into
the file select register pointed to
by ‘f’.
Description:
The contents of register ‘f’ are
moved to a destination dependent
upon the status of ‘d’. If ‘d’ is 0, the
result is placed in W. If ‘d’ is 1, the
result is placed back in register ‘f’
(default). Location ‘f’ can be any-
where in the 256-byte bank. If ‘a’ is
0, the Access Bank will be
Words:
Cycles:
2
2
Q Cycle Activity:
Q1
Q2
Q3
Q4
selected, overriding the BSR value.
If ‘a’ = 1, then the bank will be
selected as per the BSR value
(default).
Decode
Read literal
‘k’ MSB
Process
Data
Write
literal ‘k’
MSB to
FSRfH
Decode
Read literal
‘k’ LSB
Process
Data
Write literal
‘k’ to FSRfL
Words:
Cycles:
1
1
Q Cycle Activity:
Q1
LFSR 2, 0x3AB
Example:
Q2
Q3
Q4
After Instruction
Decode
Read
register ‘f’
Process
Data
Write W
FSR2H
FSR2L
=
=
0x03
0xAB
MOVF
REG, 0, 0
Example:
Before Instruction
REG
W
=
=
0x22
0xFF
After Instruction
REG
W
=
=
0x22
0x22
2003 Microchip Technology Inc.
Advance Information
DS39612A-page 301
PIC18F6X2X/8X2X
MOVFF
Move f to f
MOVLB
Move literal to low nibble in BSR
Syntax:
[ label ] MOVFF fs,fd
Syntax:
[ label ] MOVLB k
0 ≤ k ≤ 255
k → BSR
Operands:
0 ≤ fs ≤ 4095
0 ≤ fd ≤ 4095
Operands:
Operation:
Status Affected:
Encoding:
Operation:
(fs) → fd
None
Status Affected:
None
0000
0001
kkkk
kkkk
Encoding:
1st word (source)
2nd word (destin.)
Description:
The 8-bit literal ‘k’ is loaded into
the Bank Select Register (BSR).
1100
1111
ffff
ffff
ffff
ffff
ffffs
ffffd
Words:
Cycles:
1
1
Description:
The contents of source register ‘fs’
are moved to destination register
‘fd’. Location of source ‘fs’ can be
anywhere in the 4096-byte data
space (000h to FFFh), and location
of destination ‘fd’ can also be any-
where from 000h to FFFh.
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read literal
‘k’
Process
Data
Write
literal ‘k’ to
BSR
Either source or destination can be
W (a useful special situation).
MOVFFis particularly useful for
transferring a data memory location
to a peripheral register (such as the
transmit buffer or an I/O port).
The MOVFFinstruction cannot use
the PCL, TOSU, TOSH or TOSL as
the destination register
MOVLB
5
Example:
Before Instruction
BSR register
=
=
0x02
0x05
After Instruction
BSR register
Words:
Cycles:
2
2 (3)
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
register ‘f’
(src)
Process
Data
No
operation
Decode
No
operation
No
operation
Write
register ‘f’
(dest)
No dummy
read
MOVFF
REG1, REG2
Example:
Before Instruction
REG1
REG2
=
=
0x33
0x11
After Instruction
REG1
REG2
=
=
0x33
0x33
DS39612A-page 302
Advance Information
2003 Microchip Technology Inc.
PIC18F6X2X/8X2X
MOVLW
Move literal to W
MOVWF
Move W to f
Syntax:
[ label ] MOVLW k
0 ≤ k ≤ 255
k → W
Syntax:
[ label ] MOVWF f [,a]
Operands:
Operation:
Status Affected:
Encoding:
Operands:
0 ≤ f ≤ 255
a ∈ [0,1]
Operation:
(W) → f
None
Status Affected:
Encoding:
None
0000
1110
kkkk
kkkk
0110
111a
ffff
ffff
Description:
The eight-bit literal ‘k’ is loaded into
W.
Description:
Move data from W to register ‘f’.
Location ‘f’ can be anywhere in the
256-byte bank. If ‘a’ is 0, the
Access Bank will be selected, over-
riding the BSR value. If ‘a’ = 1, then
the bank will be selected as per the
BSR value (default).
Words:
Cycles:
1
1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
literal ‘k’
Process
Data
Write to W
Words:
Cycles:
1
1
MOVLW
0x5A
Example:
Q Cycle Activity:
Q1
After Instruction
Q2
Q3
Q4
W
=
0x5A
Decode
Read
register ‘f’
Process
Data
Write
register 'f'
MOVWF
REG, 0
Example:
Before Instruction
W
REG
=
=
0x4F
0xFF
After Instruction
W
REG
=
=
0x4F
0x4F
2003 Microchip Technology Inc.
Advance Information
DS39612A-page 303
PIC18F6X2X/8X2X
MULLW
Multiply Literal with W
MULWF
Multiply W with f
Syntax:
[ label ] MULLW
0 ≤ k ≤ 255
k
Syntax:
[ label ] MULWF f [,a]
Operands:
Operation:
Status Affected:
Encoding:
Operands:
0 ≤ f ≤ 255
a ∈ [0,1]
(W) x k → PRODH:PRODL
Operation:
(W) x (f) → PRODH:PRODL
None
Status Affected:
Encoding:
None
0000
1101
kkkk
kkkk
0000
001a
ffff
ffff
Description:
An unsigned multiplication is
carried out between the contents
of W and the 8-bit literal ‘k’. The
16-bit result is placed in
PRODH:PRODL register pair.
PRODH contains the high byte.
W is unchanged.
None of the status flags are
affected.
Note that neither overflow nor
carry is possible in this opera-
tion. A zero result is possible but
not detected.
Description:
An unsigned multiplication is
carried out between the contents
of W and the register file location
‘f’. The 16-bit result is stored in
the PRODH:PRODL register
pair. PRODH contains the high
byte.
Both W and ‘f’ are unchanged.
None of the status flags are
affected.
Note that neither overflow nor
carry is possible in this opera-
tion. A zero result is possible but
not detected. If ‘a’ is 0, the
Access Bank will be selected,
overriding the BSR value. If
‘a’= 1, then the bank will be
selected as per the BSR value
(default).
Words:
Cycles:
1
1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
literal ‘k’
Process
Data
Write
registers
PRODH:
PRODL
Words:
Cycles:
1
1
Q Cycle Activity:
Q1
MULLW
0xC4
Example:
Q2
Q3
Q4
Before Instruction
Decode
Read
register ‘f’
Process
Data
Write
W
PRODH
PRODL
=
=
=
0xE2
registers
PRODH:
PRODL
?
?
After Instruction
W
=
=
=
0xE2
0xAD
0x08
MULWF
REG, 1
Example:
PRODH
PRODL
Before Instruction
W
REG
PRODH
PRODL
=
0xC4
0xB5
?
?
=
=
=
After Instruction
W
=
0xC4
REG
PRODH
PRODL
=
=
=
0xB5
0x8A
0x94
DS39612A-page 304
Advance Information
2003 Microchip Technology Inc.
PIC18F6X2X/8X2X
NEGF
Negate f
NOP
No Operation
Syntax:
[ label ] NEGF f [,a]
Syntax:
[ label ] NOP
None
Operands:
0 ≤ f ≤ 255
a ∈ [0,1]
Operands:
Operation:
Status Affected:
Encoding:
No operation
None
Operation:
( f ) + 1 → f
Status Affected:
Encoding:
N, OV, C, DC, Z
0000
1111
0000
xxxx
0000
xxxx
0000
xxxx
0110
110a
ffff
ffff
Description:
Words:
No operation.
Description:
Location ‘f’ is negated using two’s
complement. The result is placed in
the data memory location ‘f’. If ‘a’ is
0, the Access Bank will be
1
1
Cycles:
Q Cycle Activity:
Q1
selected, overriding the BSR value.
If ‘a’ = 1, then the bank will be
selected as per the BSR value.
Q2
No
Q3
No
Q4
Decode
No
operation
operation
operation
Words:
Cycles:
1
1
Example:
None.
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
register ‘f’
Process
Data
Write
register ‘f’
NEGF
REG, 1
Example:
Before Instruction
REG
=
0011 1010 [0x3A]
1100 0110 [0xC6]
After Instruction
REG
=
2003 Microchip Technology Inc.
Advance Information
DS39612A-page 305
PIC18F6X2X/8X2X
POP
Pop Top of Return Stack
PUSH
Push Top of Return Stack
Syntax:
[ label ] POP
None
Syntax:
[ label ] PUSH
None
Operands:
Operation:
Status Affected:
Encoding:
Operands:
Operation:
Status Affected:
Encoding:
(TOS) → bit bucket
None
(PC+2) → TOS
None
0000
0000
0000
0110
0000
0000
0000
0101
Description:
The TOS value is pulled off the
return stack and is discarded. The
TOS value then becomes the previ-
ous value that was pushed onto the
return stack.
This instruction is provided to
enable the user to properly manage
the return stack to incorporate a
software stack.
Description:
The PC+2 is pushed onto the top of
the return stack. The previous TOS
value is pushed down on the stack.
This instruction allows implement-
ing a software stack by modifying
TOS, and then pushing it onto the
return stack.
Words:
Cycles:
1
1
Words:
Cycles:
1
1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Q Cycle Activity:
Q1
Decode
PUSH PC+2
onto return
stack
No
operation
No
operation
Q2
Q3
Q4
Decode
No
operation
POP TOS
value
No
operation
PUSH
Example:
POP
GOTO
Example:
Before Instruction
NEW
TOS
PC
=
=
00345Ah
000124h
Before Instruction
TOS
=
0031A2h
014332h
Stack (1 level down)=
After Instruction
PC
TOS
=
=
000126h
000126h
00345Ah
After Instruction
Stack (1 level down)=
TOS
PC
=
=
014332h
NEW
DS39612A-page 306
Advance Information
2003 Microchip Technology Inc.
PIC18F6X2X/8X2X
RCALL
Relative Call
RESET
Reset
Syntax:
[ label ] RCALL
-1024 ≤ n ≤ 1023
(PC) + 2 → TOS,
n
Syntax:
[ label ] RESET
Operands:
Operation:
Operands:
Operation:
None
Reset all registers and flags that
are affected by a MCLR Reset.
(PC) + 2 + 2n → PC
Status Affected:
Encoding:
None
Status Affected:
Encoding:
All
1101
1nnn
nnnn
nnnn
0000
0000
1111
1111
Description:
Subroutine call with a jump up to
1K from the current location. First,
return address (PC+2) is pushed
onto the stack. Then, add the 2’s
complement number ‘2n’ to the PC.
Since the PC will have incremented
to fetch the next instruction, the
new address will be PC+2+2n.
This instruction is a two-cycle
instruction.
Description:
This instruction provides a way to
execute a MCLR Reset in software.
Words:
Cycles:
1
1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Start
reset
No
operation
No
operation
Words:
Cycles:
1
2
RESET
Example:
After Instruction
Registers =
Reset Value
Reset Value
Q Cycle Activity:
Q1
Flags*
=
Q2
Q3
Q4
Decode
Read literal
‘n’
Process
Data
Write to PC
Push PC to
stack
No
No
No
No
operation
operation
operation
operation
HERE
RCALL
Jump
Example:
Before Instruction
PC
=
Address (HERE)
After Instruction
PC
TOS
=
=
Address (Jump)
Address (HERE+2)
2003 Microchip Technology Inc.
Advance Information
DS39612A-page 307
PIC18F6X2X/8X2X
RETFIE
Return from Interrupt
RETLW
Return Literal to W
Syntax:
[ label ] RETFIE [s]
s ∈ [0,1]
Syntax:
[ label ] RETLW k
0 ≤ k ≤ 255
Operands:
Operation:
Operands:
Operation:
(TOS) → PC,
1 → GIE/GIEH or PEIE/GIEL,
if s = 1
k → W,
(TOS) → PC,
PCLATU, PCLATH are unchanged
(WS) → W,
(STATUSS) → STATUS,
(BSRS) → BSR,
Status Affected:
Encoding:
None
0000
1100
kkkk
kkkk
PCLATU, PCLATH are unchanged.
Description:
W is loaded with the eight-bit literal
‘k’. The program counter is loaded
from the top of the stack (the return
address). The high address latch
(PCLATH) remains unchanged.
Status Affected:
Encoding:
GIE/GIEH, PEIE/GIEL.
0000
0000
0001
000s
Description:
Return from Interrupt. Stack is
popped and Top-of-Stack (TOS) is
loaded into the PC. Interrupts are
enabled by setting either the high
or low priority global interrupt
enable bit. If ‘s’ = 1, the contents of
the shadow registers WS,
STATUSS and BSRS are loaded
into their corresponding registers,
W, STATUS and BSR. If ‘s’ = 0, no
update of these registers occurs
(default).
Words:
Cycles:
1
2
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
literal ‘k’
Process
Data
Pop PC from
stack, Write
to W
No
No
No
No
operation
operation
operation
operation
Words:
Cycles:
1
2
Example:
CALL TABLE ; W contains table
; offset value
Q Cycle Activity:
Q1
Q2
Q3
Q4
; W now has
; table value
Decode
No
operation
No
operation
Pop PC from
stack
:
TABLE
ADDWF PCL ; W = offset
Set GIEH or
GIEL
RETLW k0
RETLW k1
:
; Begin table
;
No
operation
No
operation
No
operation
No
operation
:
RETLW kn
; End of table
RETFIE
1
Example:
After Interrupt
Before Instruction
PC
W
=
=
=
=
=
TOS
WS
BSRS
STATUSS
1
W
=
0x07
BSR
STATUS
GIE/GIEH, PEIE/GIEL
After Instruction
W
=
value of kn
DS39612A-page 308
Advance Information
2003 Microchip Technology Inc.
PIC18F6X2X/8X2X
RETURN
Return from Subroutine
RLCF
Rotate Left f through Carry
Syntax:
[ label ] RETURN [s]
s ∈ [0,1]
Syntax:
[ label ] RLCF f [,d [,a]
Operands:
Operation:
Operands:
0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
(TOS) → PC,
if s = 1
(WS) → W,
Operation:
(f<n>) → dest<n+1>,
(f<7>) → C,
(STATUSS) → STATUS,
(BSRS) → BSR,
PCLATU, PCLATH are unchanged
(C) → dest<0>
Status Affected:
Encoding:
C, N, Z
Status Affected:
Encoding:
None
0011
01da
ffff
ffff
0000
0000
0001
001s
Description:
The contents of register ‘f’ are
rotated one bit to the left through
the Carry Flag. If ‘d’ is 0, the result
is placed in W. If ‘d’ is 1, the result
is stored back in register ‘f’
(default). If ‘a’ is 0, the Access
Bank will be selected, overriding
the BSR value. If ‘a’ = 1, then the
bank will be selected as per the
BSR value (default).
Description:
Return from subroutine. The stack
is popped and the top of the stack
(TOS) is loaded into the program
counter. If ‘s’= 1, the contents of
the shadow registers WS,
STATUSS and BSRS are loaded
into their corresponding registers,
W, STATUS and BSR. If ‘s’ = 0, no
update of these registers occurs
(default).
register f
C
Words:
Cycles:
1
2
Words:
Cycles:
1
1
Q Cycle Activity:
Q1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Q2
Q3
Q4
Decode
No
Process
Data
Pop PC from
stack
operation
Decode
Read
Process
Write to
No
No
No
No
register ‘f’
Data
destination
operation
operation
operation
operation
RLCF
REG, 0, 0
Example:
Before Instruction
RETURN
Example:
REG
C
=
=
1110 0110
0
After Interrupt
After Instruction
PC = TOS
REG
=
1110 0110
W
C
=
=
1100 1100
1
2003 Microchip Technology Inc.
Advance Information
DS39612A-page 309
PIC18F6X2X/8X2X
RLNCF
Rotate Left f (no carry)
RRCF
Rotate Right f through Carry
Syntax:
[ label ] RLNCF f [,d [,a]
Syntax:
[ label ] RRCF f [,d [,a]
Operands:
0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
Operands:
0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
Operation:
(f<n>) → dest<n+1>,
(f<7>) → dest<0>
Operation:
(f<n>) → dest<n-1>,
(f<0>) → C,
(C) → dest<7>
Status Affected:
Encoding:
N, Z
Status Affected:
Encoding:
C, N, Z
0100
01da
ffff
ffff
0011
00da
ffff
ffff
Description:
The contents of register ‘f’ are
rotated one bit to the left. If ‘d’ is 0,
the result is placed in W. If ‘d’ is 1,
the result is stored back in register
‘f’ (default). If ‘a’ is 0, the Access
Bank will be selected, overriding
the BSR value. If ‘a’ is 1, then the
bank will be selected as per the
BSR value (default).
Description:
The contents of register ‘f’ are
rotated one bit to the right through
the Carry flag. If ‘d’ is 0, the result is
placed in W. If ‘d’ is 1, the result is
placed back in register ‘f’ (default).
If ‘a’ is 0, the Access Bank will be
selected, overriding the BSR value.
If ‘a’ is 1, then the bank will be
selected as per the BSR value
(default).
register f
Words:
Cycles:
1
1
register f
C
Words:
Cycles:
1
1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Q Cycle Activity:
Q1
Decode
Read
register ‘f’
Process
Data
Write to
destination
Q2
Q3
Q4
Decode
Read
Process
Write to
register ‘f’
Data
destination
RLNCF
REG, 1, 0
Example:
Before Instruction
RRCF
REG, 0, 0
Example:
REG
=
1010 1011
0101 0111
After Instruction
Before Instruction
REG
=
REG
C
=
=
1110 0110
0
After Instruction
REG
=
1110 0110
W
C
=
=
0111 0011
0
DS39612A-page 310
Advance Information
2003 Microchip Technology Inc.
PIC18F6X2X/8X2X
RRNCF
Rotate Right f (no carry)
SETF
Set f
Syntax:
[ label ] RRNCF f [,d [,a]
Syntax:
[ label ] SETF f [,a]
Operands:
0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
Operands:
0 ≤ f ≤ 255
a ∈ [0,1]
Operation:
FFh → f
Operation:
(f<n>) → dest<n-1>,
(f<0>) → dest<7>
Status Affected:
Encoding:
None
0110
100a
ffff
ffff
Status Affected:
Encoding:
N, Z
Description:
The contents of the specified regis-
ter are set to FFh. If ‘a’ is 0, the
Access Bank will be selected, over-
riding the BSR value. If ‘a’ is 1, then
the bank will be selected as per the
BSR value (default).
0100
00da
ffff
ffff
Description:
The contents of register ‘f’ are
rotated one bit to the right. If ‘d’ is 0,
the result is placed in W. If ‘d’ is 1,
the result is placed back in regis-
ter ‘f’ (default). If ‘a’ is 0, the Access
Bank will be selected, overriding
the BSR value. If ‘a’ is 1, then the
bank will be selected as per the
BSR value (default).
Words:
Cycles:
1
1
Q Cycle Activity:
Q1
Q2
Q3
Q4
register f
Decode
Read
register ‘f’
Process
Data
Write
register 'f'
Words:
Cycles:
1
1
SETF
REG,1
Example:
Before Instruction
Q Cycle Activity:
Q1
REG
=
=
0x5A
0xFF
Q2
Q3
Q4
After Instruction
REG
Decode
Read
register ‘f’
Process
Data
Write to
destination
RRNCF
REG, 1, 0
Example 1:
Before Instruction
REG
=
1101 0111
1110 1011
RRNCF REG, 0, 0
After Instruction
REG
=
Example 2:
Before Instruction
W
REG
=
=
?
1101 0111
After Instruction
W
REG
=
=
1110 1011
1101 0111
2003 Microchip Technology Inc.
Advance Information
DS39612A-page 311
PIC18F6X2X/8X2X
SLEEP
Enter SLEEP mode
SUBFWB
Subtract f from W with borrow
Syntax:
[ label ] SLEEP
Syntax:
[ label ] SUBFWB f [,d [,a]
Operands:
Operation:
None
Operands:
0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
00h → WDT,
0 → WDT postscaler,
1 → TO,
Operation:
(W) – (f) – (C) → dest
0 → PD
Status Affected:
Encoding:
N, OV, C, DC, Z
Status Affected:
Encoding:
TO, PD
0101
01da
ffff
ffff
0000
0000
0000
0011
Description:
Subtract register ‘f’ and carry flag
(borrow) from W (2’s complement
method). If ‘d’ is 0, the result is
stored in W. If ‘d’ is 1, the result is
stored in register ‘f’ (default). If ‘a’ is
0, the Access Bank will be selected,
overriding the BSR value. If ‘a’ is 1,
then the bank will be selected as
per the BSR value (default).
Description:
The power-down status bit (PD) is
cleared. The time-out status bit
(TO) is set. Watchdog Timer and
its postscaler are cleared.
The processor is put into SLEEP
mode with the oscillator stopped.
Words:
Cycles:
1
1
Words:
Cycles:
1
1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Q Cycle Activity:
Q1
Decode
No
operation
Process
Data
Go to
SLEEP
Q2
Q3
Q4
Decode
Read
register ‘f’
Process
Data
Write to
destination
SLEEP
Example:
SUBFWB
REG, 1, 0
Example 1:
Before Instruction
TO
PD
=
=
?
?
Before Instruction
REG
W
=
=
=
3
2
1
After Instruction
C
TO
=
1 †
After Instruction
PD
=
0
REG
W
C
Z
N
=
=
=
=
=
FF
2
0
0
1
† If WDT causes wake-up, this bit is cleared.
; result is negative
SUBFWB
REG, 0, 0
Example 2:
Before Instruction
REG
W
C
=
=
=
2
5
1
After Instruction
REG
W
C
Z
N
=
=
=
=
=
2
3
1
0
0
; result is positive
SUBFWB
REG, 1, 0
Example 3:
Before Instruction
REG
W
C
=
=
=
1
2
0
After Instruction
REG
W
C
Z
N
=
=
=
=
=
0
2
1
1
0
; result is zero
DS39612A-page 312
Advance Information
2003 Microchip Technology Inc.
PIC18F6X2X/8X2X
SUBLW
Subtract W from literal
SUBWF
Subtract W from f
Syntax:
Syntax:
[ label ] SUBLW k
0 ≤ k ≤ 255
[ label ] SUBWF f [,d [,a]
Operands:
Operation:
Status Affected:
Encoding:
Operands:
0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
k – (W) → W
N, OV, C, DC, Z
Operation:
(f) – (W) → dest
0000
1000
kkkk
kkkk
Status Affected:
Encoding:
N, OV, C, DC, Z
Description:
W is subtracted from the eight-bit
literal ‘k’. The result is placed in
W.
0101
11da
ffff
ffff
Description:
Subtract W from register ‘f’ (2’s
complement method). If ‘d’ is 0,
the result is stored in W. If ‘d’ is 1,
the result is stored back in regis-
ter ‘f’ (default). If ‘a’ is 0, the
Access Bank will be selected,
overriding the BSR value. If ‘a’ is
1, then the bank will be selected
as per the BSR value (default).
Words:
Cycles:
1
1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
literal ‘k’
Process
Data
Write to W
SUBLW 0x02
Example 1:
Words:
Cycles:
1
1
Before Instruction
W
=
1
?
C
=
Q Cycle Activity:
Q1
After Instruction
Q2
Q3
Q4
W
C
Z
=
=
=
=
1
Decode
Read
register ‘f’
Process
Data
Write to
destination
1
0
0
; result is positive
N
SUBWF
REG, 1, 0
Example 1:
SUBLW 0x02
Example 2:
Before Instruction
Before Instruction
REG
W
C
=
=
=
3
2
?
W
C
=
=
2
?
After Instruction
After Instruction
REG
W
C
Z
N
=
=
=
=
=
1
2
1
0
0
W
C
Z
=
=
=
=
0
1
1
0
; result is zero
; result is positive
N
SUBLW 0x02
Example 3:
SUBWF
REG, 0, 0
Example 2:
Before Instruction
Before Instruction
W
C
=
=
3
?
REG
W
C
=
=
=
2
2
?
After Instruction
W
C
Z
=
=
=
=
FF ; (2’s complement)
After Instruction
0
0
1
; result is negative
REG
W
C
=
=
=
=
=
2
0
1
1
0
N
; result is zero
Z
N
SUBWF
REG, 1, 0
Example 3:
Before Instruction
REG
W
C
=
=
=
1
2
?
After Instruction
REG
W
C
Z
N
=
=
=
=
=
FFh ;(2’s complement)
2
0
0
1
; result is negative
2003 Microchip Technology Inc.
Advance Information
DS39612A-page 313
PIC18F6X2X/8X2X
SUBWFB
Syntax:
Subtract W from f with Borrow
SWAPF
Swap f
Syntax:
[ label ] SWAPF f [,d [,a]
[ label ] SUBWFB f [,d [,a]
Operands:
0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
Operands:
0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
Operation:
(f<3:0>) → dest<7:4>,
(f<7:4>) → dest<3:0>
Operation:
(f) – (W) – (C) → dest
Status Affected: N, OV, C, DC, Z
Status Affected:
Encoding:
None
Encoding:
0101
10da
ffff
ffff
0011
10da
ffff
ffff
Description:
Subtract W and the carry flag (bor-
row) from register ‘f’ (2’s complement
method). If ‘d’ is 0, the result is stored
in W. If ‘d’ is 1, the result is stored
back in register ‘f’ (default). If ‘a’ is 0,
the Access Bank will be selected,
overriding the BSR value. If ‘a’ is 1,
then the bank will be selected as per
the BSR value (default).
Description:
The upper and lower nibbles of reg-
ister ‘f’ are exchanged. If ‘d’ is 0,
the result is placed in W. If ‘d’ is 1,
the result is placed in register ‘f’
(default). If ‘a’ is 0, the Access
Bank will be selected, overriding
the BSR value. If ‘a’ is 1, then the
bank will be selected as per the
BSR value (default).
Words:
Cycles:
1
1
Words:
Cycles:
1
1
Q Cycle Activity:
Q1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Q2
Q3
Q4
Decode
Read
register ‘f’
Process
Data
Write to
destination
Decode
Read
register ‘f’
Process
Data
Write to
destination
SUBWFB REG, 1, 0
Example 1:
Before Instruction
SWAPF
REG, 1, 0
Example:
REG
W
C
=
=
=
0x19
0x0D
1
(0001 1001)
(0000 1101)
Before Instruction
REG
=
0x53
0x35
After Instruction
After Instruction
REG
=
REG
W
C
Z
N
=
=
=
=
=
0x0C
0x0D
1
0
0
(0000 1011)
(0000 1101)
; result is positive
SUBWFB REG, 0, 0
Example 2:
Before Instruction
REG
W
C
=
=
=
0x1B
0x1A
0
(0001 1011)
(0001 1010)
After Instruction
REG
W
C
=
=
=
=
=
0x1B
(0001 1011)
0x00
1
1
0
Z
; result is zero
N
SUBWFB REG, 1, 0
Example 3:
Before Instruction
REG
W
C
=
=
=
0x03
0x0E
1
(0000 0011)
(0000 1101)
After Instruction
REG
=
0xF5
(1111 0100)
; [2’s comp]
W
C
Z
=
=
=
=
0x0E
(0000 1101)
0
0
1
N
; result is negative
DS39612A-page 314
Advance Information
2003 Microchip Technology Inc.
PIC18F6X2X/8X2X
TBLRD
Table Read
TBLRD
Example1:
Table Read (cont’d)
TBLRD *+ ;
Syntax:
[ label ] TBLRD ( *; *+; *-; +*)
Operands:
Operation:
None
Before Instruction
TABLAT
TBLPTR
MEMORY(0x00A356)
=
=
=
0x55
0x00A356
0x34
if TBLRD *,
(Prog Mem (TBLPTR)) → TABLAT;
TBLPTR - No Change;
if TBLRD *+,
(Prog Mem (TBLPTR)) → TABLAT;
(TBLPTR) +1 → TBLPTR;
if TBLRD *-,
After Instruction
TABLAT
TBLPTR
=
=
0x34
0x00A357
TBLRD +* ;
Example2:
(Prog Mem (TBLPTR)) → TABLAT;
(TBLPTR) -1 → TBLPTR;
if TBLRD +*,
(TBLPTR) +1 → TBLPTR;
(Prog Mem (TBLPTR)) → TABLAT;
Before Instruction
TABLAT
TBLPTR
=
=
=
=
0xAA
0x01A357
0x12
MEMORY(0x01A357)
MEMORY(0x01A358)
0x34
After Instruction
Status Affected:None
TABLAT
TBLPTR
=
=
0x34
0x01A358
0000
0000
0000
10nn
nn=0 *
=1 *+
=2 *-
=3 +*
Encoding:
Description:
This instruction is used to read the con-
tents of Program Memory (P.M.). To
address the program memory, a pointer
called Table Pointer (TBLPTR) is used.
The TBLPTR (a 21-bit pointer) points
to each byte in the program memory.
TBLPTR has a 2-Mbyte address
range.
TBLPTR[0] = 0: Least Significant
Byte of Program
Memory Word
TBLPTR[0] = 1: Most Significant
Byte of Program
Memory Word
The TBLRDinstruction can modify the
value of TBLPTR as follows:
• no change
• post-increment
• post-decrement
• pre-increment
Words:
Cycles:
1
2
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
No
No
No
operation
operation
operation
No
No operation
No
No operation
operation (Read Program operation (Write TABLAT)
Memory)
2003 Microchip Technology Inc.
Advance Information
DS39612A-page 315
PIC18F6X2X/8X2X
TBLWT
Table Write
TBLWT Table Write (Continued)
Syntax:
[ label ] TBLWT ( *; *+; *-; +*)
Words: 1
Operands:
Operation:
None
Cycles: 2
if TBLWT*,
Q Cycle Activity:
(TABLAT) → Holding Register;
TBLPTR - No Change;
if TBLWT*+,
Q1
Q2
Q3
Q4
Decode
No
No
No
operation
operation
operation
(TABLAT) → Holding Register;
(TBLPTR) +1 → TBLPTR;
if TBLWT*-,
(TABLAT) → Holding Register;
(TBLPTR) -1 → TBLPTR;
if TBLWT+*,
No
operation
No
operation
(Read
No
operation
No
operation
(Write to
Holding
Register )
TABLAT)
(TBLPTR) +1 → TBLPTR;
(TABLAT) → Holding Register;
Example1:
TBLWT *+;
Status Affected: None
Before Instruction
0000
0000
0000
11nn
nn=0 *
=1 *+
=2 *-
=3 +*
Encoding:
TABLAT
TBLPTR
=
=
0x55
0x00A356
HOLDING REGISTER
(0x00A356)
=
0xFF
After Instructions (table write completion)
TABLAT
=
0x55
Description:
This instruction uses the 3 LSBs of
TBLPTR to determine which of the 8
holding registers the TABLAT is writ-
ten to. The holding registers are used
to program the contents of Program
Memory (P.M.). (Refer to Section 5.0
for additional details on programming
FLASH memory.)
The TBLPTR (a 21-bit pointer) points
to each byte in the program memory.
TBLPTR has a 2-MByte address
range. The LSb of the TBLPTR
selects which byte of the program
memory location to access.
TBLPTR
=
0x00A357
HOLDING REGISTER
(0x00A356)
=
0x55
Example 2:
TBLWT +*;
Before Instruction
TABLAT
TBLPTR
HOLDING REGISTER
(0x01389A)
HOLDING REGISTER
(0x01389B)
=
=
0x34
0x01389A
=
=
0xFF
0xFF
After Instruction (table write completion)
TABLAT
TBLPTR
HOLDING REGISTER
(0x01389A)
HOLDING REGISTER
(0x01389B)
=
=
0x34
0x01389B
=
=
0xFF
0x34
TBLPTR[0] = 0:Least Significant
Byte of Program
Memory Word
TBLPTR[0] = 1:Most Significant
Byte of Program
Memory Word
The TBLWT instruction can modify
the value of TBLPTR as follows:
• no change
• post-increment
• post-decrement
• pre-increment
DS39612A-page 316
Advance Information
2003 Microchip Technology Inc.
PIC18F6X2X/8X2X
TSTFSZ
Test f, skip if 0
XORLW
Exclusive OR literal with W
Syntax:
[ label ] TSTFSZ f [,a]
Syntax:
[ label ] XORLW k
0 ≤ k ≤ 255
Operands:
0 ≤ f ≤ 255
a ∈ [0,1]
Operands:
Operation:
Status Affected:
Encoding:
(W) .XOR. k → W
N, Z
Operation:
skip if f = 0
None
Status Affected:
Encoding:
0000
1010
kkkk
kkkk
0110
011a
ffff
ffff
Description:
The contents of W are XORed
with the 8-bit literal ‘k’. The result
is placed in W.
Description:
If ‘f’ = 0, the next instruction,
fetched during the current instruc-
tion execution is discarded and a
NOPis executed, making this a two-
cycle instruction. If ‘a’ is 0, the
Access Bank will be selected, over-
riding the BSR value. If ‘a’ is 1,
then the bank will be selected as
per the BSR value (default).
Words:
Cycles:
1
1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
literal ‘k’
Process
Data
Write to W
Words:
Cycles:
1
1(2)
Example:
XORLW 0xAF
Note: 3 cycles if skip and followed
by a 2-word instruction.
Before Instruction
W
=
0xB5
Q Cycle Activity:
Q1
After Instruction
Q2
Q3
Q4
W
=
0x1A
Decode
Read
register ‘f’
Process
Data
No
operation
If skip:
Q1
Q2
Q3
Q4
No
No
No
No
operation
operation
operation
operation
If skip and followed by 2-word instruction:
Q1
Q2
Q3
Q4
No
No
No
No
operation
operation
operation
operation
No
No
No
No
operation
operation
operation
operation
HERE
NZERO
ZERO
TSTFSZ CNT, 1
:
:
Example:
Before Instruction
PC
=
Address (HERE)
After Instruction
If CNT
=
=
≠
=
0x00,
PC
Address (ZERO)
0x00,
If CNT
PC
Address (NZERO)
2003 Microchip Technology Inc.
Advance Information
DS39612A-page 317
PIC18F6X2X/8X2X
XORWF
Exclusive OR W with f
Syntax:
[ label ] XORWF f [,d [,a]
Operands:
0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
Operation:
(W) .XOR. (f) → dest
Status Affected:
Encoding:
N, Z
0001
10da
ffff
ffff
Description:
Exclusive OR the contents of W
with register ‘f’. If ‘d’ is 0, the result
is stored in W. If ‘d’ is 1, the result is
stored back in the register ‘f’
(default). If ‘a’ is 0, the Access
Bank will be selected, overriding
the BSR value. If ‘a’ is 1, then the
bank will be selected as per the
BSR value (default).
Words:
Cycles:
1
1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
register ‘f’
Process
Data
Write to
destination
XORWF
REG, 1, 0
Example:
Before Instruction
REG
W
=
=
0xAF
0xB5
After Instruction
REG
W
=
=
0x1A
0xB5
DS39612A-page 318
Advance Information
2003 Microchip Technology Inc.
PIC18F6X2X/8X2X
26.1 MPLAB Integrated Development
Environment Software
26.0 DEVELOPMENT SUPPORT
The PICmicro® microcontrollers are supported with a
full range of hardware and software development tools:
The MPLAB IDE software brings an ease of software
development previously unseen in the 8/16-bit micro-
controller market. The MPLAB IDE is a Windows®
based application that contains:
• Integrated Development Environment
- MPLAB® IDE Software
• Assemblers/Compilers/Linkers
- MPASMTM Assembler
• An interface to debugging tools
- simulator
- MPLAB C17 and MPLAB C18 C Compilers
- MPLINKTM Object Linker/
MPLIBTM Object Librarian
- programmer (sold separately)
- emulator (sold separately)
- in-circuit debugger (sold separately)
• A full-featured editor with color coded context
• A multiple project manager
- MPLAB C30 C Compiler
- MPLAB ASM30 Assembler/Linker/Library
• Simulators
• Customizable data windows with direct edit of
contents
- MPLAB SIM Software Simulator
- MPLAB dsPIC30 Software Simulator
• Emulators
• High level source code debugging
• Mouse over variable inspection
• Extensive on-line help
- MPLAB ICE 2000 In-Circuit Emulator
- MPLAB ICE 4000 In-Circuit Emulator
• In-Circuit Debugger
The MPLAB IDE allows you to:
• Edit your source files (either assembly or C)
- MPLAB ICD 2
• One touch assemble (or compile) and download
to PICmicro emulator and simulator tools
(automatically updates all project information)
• Device Programmers
- PRO MATE® II Universal Device Programmer
- PICSTART® Plus Development Programmer
• Low Cost Demonstration Boards
- PICDEMTM 1 Demonstration Board
- PICDEM.netTM Demonstration Board
- PICDEM 2 Plus Demonstration Board
- PICDEM 3 Demonstration Board
- PICDEM 4 Demonstration Board
- PICDEM 17 Demonstration Board
- PICDEM 18R Demonstration Board
- PICDEM LIN Demonstration Board
- PICDEM USB Demonstration Board
• Evaluation Kits
• Debug using:
- source files (assembly or C)
- absolute listing file (mixed assembly and C)
- machine code
MPLAB IDE supports multiple debugging tools in a
single development paradigm, from the cost effective
simulators, through low cost in-circuit debuggers, to
full-featured emulators. This eliminates the learning
curve when upgrading to tools with increasing flexibility
and power.
26.2 MPASM Assembler
®
- KEELOQ
The MPASM assembler is a full-featured, universal
macro assembler for all PICmicro MCUs.
- PICDEM MSC
- microID®
- CAN
The MPASM assembler generates relocatable object
files for the MPLINK object linker, Intel® standard HEX
files, MAP files to detail memory usage and symbol ref-
erence, absolute LST files that contain source lines and
generated machine code and COFF files for
debugging.
- PowerSmart®
- Analog
The MPASM assembler features include:
• Integration into MPLAB IDE projects
• User defined macros to streamline assembly code
• Conditional assembly for multi-purpose source
files
• Directives that allow complete control over the
assembly process
2003 Microchip Technology Inc.
Advance Information
DS39612A-page 319
PIC18F6X2X/8X2X
26.3 MPLAB C17 and MPLAB C18
C Compilers
26.6 MPLAB ASM30 Assembler, Linker,
and Librarian
The MPLAB C17 and MPLAB C18 Code Development
MPLAB ASM30 assembler produces relocatable
machine code from symbolic assembly language for
dsPIC30F devices. MPLAB C30 compiler uses the
assembler to produce it’s object file. The assembler
generates relocatable object files that can then be
archived or linked with other relocatable object files and
archives to create an executable file. Notable features
of the assembler include:
Systems are complete ANSI
C
compilers for
Microchip’s PIC17CXXX and PIC18CXXX family of
microcontrollers. These compilers provide powerful
integration capabilities, superior code optimization and
ease of use not found with other compilers.
For easy source level debugging, the compilers provide
symbol information that is optimized to the MPLAB IDE
debugger.
• Support for the entire dsPIC30F instruction set
• Support for fixed-point and floating-point data
• Command line interface
26.4 MPLINK Object Linker/
MPLIB Object Librarian
• Rich directive set
• Flexible macro language
The MPLINK object linker combines relocatable
objects created by the MPASM assembler and the
MPLAB C17 and MPLAB C18 C compilers. It can link
relocatable objects from pre-compiled libraries, using
directives from a linker script.
• MPLAB IDE compatibility
26.7 MPLAB SIM Software Simulator
The MPLAB SIM software simulator allows code devel-
opment in a PC hosted environment by simulating the
PICmicro series microcontrollers on an instruction
level. On any given instruction, the data areas can be
examined or modified and stimuli can be applied from
a file, or user defined key press, to any pin. The execu-
tion can be performed in Single-Step, Execute Until
Break, or Trace mode.
The MPLIB object librarian manages the creation and
modification of library files of pre-compiled code. When
a routine from a library is called from a source file, only
the modules that contain that routine will be linked in
with the application. This allows large libraries to be
used efficiently in many different applications.
The object linker/library features include:
• Efficient linking of single libraries instead of many
smaller files
The MPLAB SIM simulator fully supports symbolic
debugging using the MPLAB C17 and MPLAB C18
C Compilers, as well as the MPASM assembler. The
software simulator offers the flexibility to develop and
debug code outside of the laboratory environment,
making it an excellent, economical software
development tool.
• Enhanced code maintainability by grouping
related modules together
• Flexible creation of libraries with easy module
listing, replacement, deletion and extraction
26.5 MPLAB C30 C Compiler
26.8 MPLAB SIM30 Software Simulator
The MPLAB C30 C compiler is a full-featured, ANSI
compliant, optimizing compiler that translates standard
ANSI C programs into dsPIC30F assembly language
source. The compiler also supports many command-
line options and language extensions to take full
advantage of the dsPIC30F device hardware capabili-
ties, and afford fine control of the compiler code
generator.
The MPLAB SIM30 software simulator allows code
development in a PC hosted environment by simulating
the dsPIC30F series microcontrollers on an instruction
level. On any given instruction, the data areas can be
examined or modified and stimuli can be applied from
a file, or user defined key press, to any of the pins.
The MPLAB SIM30 simulator fully supports symbolic
debugging using the MPLAB C30 C Compiler and
MPLAB ASM30 assembler. The simulator runs in either
a Command Line mode for automated tasks, or from
MPLAB IDE. This high speed simulator is designed to
debug, analyze and optimize time intensive DSP
routines.
MPLAB C30 is distributed with a complete ANSI C
standard library. All library functions have been vali-
dated and conform to the ANSI C library standard. The
library includes functions for string manipulation,
dynamic memory allocation, data conversion, time-
keeping, and math functions (trigonometric, exponen-
tial and hyperbolic). The compiler provides symbolic
information for high level source debugging with the
MPLAB IDE.
DS39612A-page 320
Advance Information
2003 Microchip Technology Inc.
PIC18F6X2X/8X2X
26.9 MPLAB ICE 2000
High Performance Universal
26.11 MPLAB ICD 2 In-Circuit Debugger
Microchip’s In-Circuit Debugger, MPLAB ICD 2, is a
powerful, low cost, run-time development tool,
connecting to the host PC via an RS-232 or high speed
USB interface. This tool is based on the FLASH
PICmicro MCUs and can be used to develop for these
and other PICmicro microcontrollers. The MPLAB
ICD 2 utilizes the in-circuit debugging capability built
into the FLASH devices. This feature, along with
In-Circuit Emulator
The MPLAB ICE 2000 universal in-circuit emulator is
intended to provide the product development engineer
with a complete microcontroller design tool set for
PICmicro microcontrollers. Software control of the
MPLAB ICE 2000 in-circuit emulator is advanced by
the MPLAB Integrated Development Environment,
which allows editing, building, downloading and source
debugging from a single environment.
Microchip’s In-Circuit Serial ProgrammingTM (ICSPTM
)
protocol, offers cost effective in-circuit FLASH debug-
ging from the graphical user interface of the MPLAB
Integrated Development Environment. This enables a
designer to develop and debug source code by setting
breakpoints, single-stepping and watching variables,
CPU status and peripheral registers. Running at full
speed enables testing hardware and applications in
real-time. MPLAB ICD 2 also serves as a development
programmer for selected PICmicro devices.
The MPLAB ICE 2000 is a full-featured emulator sys-
tem with enhanced trace, trigger and data monitoring
features. Interchangeable processor modules allow the
system to be easily reconfigured for emulation of differ-
ent processors. The universal architecture of the
MPLAB ICE in-circuit emulator allows expansion to
support new PICmicro microcontrollers.
The MPLAB ICE 2000 in-circuit emulator system has
been designed as a real-time emulation system with
advanced features that are typically found on more
expensive development tools. The PC platform and
Microsoft® Windows 32-bit operating system were
chosen to best make these features available in a
simple, unified application.
26.12 PRO MATE II Universal Device
Programmer
The PRO MATE II is a universal, CE compliant device
programmer with programmable voltage verification at
VDDMIN and VDDMAX for maximum reliability. It features
an LCD display for instructions and error messages
and a modular detachable socket assembly to support
various package types. In Stand-Alone mode, the
PRO MATE II device programmer can read, verify, and
program PICmicro devices without a PC connection. It
can also set code protection in this mode.
26.10 MPLAB ICE 4000
High Performance Universal
In-Circuit Emulator
The MPLAB ICE 4000 universal in-circuit emulator is
intended to provide the product development engineer
with a complete microcontroller design tool set for high-
end PICmicro microcontrollers. Software control of the
MPLAB ICE in-circuit emulator is provided by the
MPLAB Integrated Development Environment, which
allows editing, building, downloading and source
debugging from a single environment.
26.13 PICSTART Plus Development
Programmer
The PICSTART Plus development programmer is an
easy-to-use, low cost, prototype programmer. It con-
nects to the PC via a COM (RS-232) port. MPLAB
Integrated Development Environment software makes
using the programmer simple and efficient. The
PICSTART Plus development programmer supports
most PICmicro devices up to 40 pins. Larger pin count
devices, such as the PIC16C92X and PIC17C76X,
may be supported with an adapter socket. The
PICSTART Plus development programmer is CE
compliant.
The MPLAB ICD 4000 is a premium emulator system,
providing the features of MPLAB ICE 2000, but with
increased emulation memory and high speed perfor-
mance for dsPIC30F and PIC18XXXX devices. Its
advanced emulator features include complex triggering
and timing, up to 2 Mb of emulation memory, and the
ability to view variables in real-time.
The MPLAB ICE 4000 in-circuit emulator system has
been designed as a real-time emulation system with
advanced features that are typically found on more
expensive development tools. The PC platform and
Microsoft Windows 32-bit operating system were cho-
sen to best make these features available in a simple,
unified application.
2003 Microchip Technology Inc.
Advance Information
DS39612A-page 321
PIC18F6X2X/8X2X
26.14 PICDEM 1 PICmicro
Demonstration Board
26.17 PICDEM 3 PIC16C92X
Demonstration Board
The PICDEM 1 demonstration board demonstrates the
capabilities of the PIC16C5X (PIC16C54 to
PIC16C58A), PIC16C61, PIC16C62X, PIC16C71,
PIC16C8X, PIC17C42, PIC17C43 and PIC17C44. All
necessary hardware and software is included to run
basic demo programs. The sample microcontrollers
provided with the PICDEM 1 demonstration board can
be programmed with a PRO MATE II device program-
mer, or a PICSTART Plus development programmer.
The PICDEM 1 demonstration board can be connected
to the MPLAB ICE in-circuit emulator for testing. A pro-
totype area extends the circuitry for additional applica-
tion components. Features include an RS-232
interface, a potentiometer for simulated analog input,
push button switches and eight LEDs.
The PICDEM 3 demonstration board supports the
PIC16C923 and PIC16C924 in the PLCC package. All
the necessary hardware and software is included to run
the demonstration programs.
26.18 PICDEM 4 8/14/18-Pin
Demonstration Board
The PICDEM 4 can be used to demonstrate the capa-
bilities of the 8-, 14-, and 18-pin PIC16XXXX and
PIC18XXXX MCUs, including the PIC16F818/819,
PIC16F87/88, PIC16F62XA and the PIC18F1320 fam-
ily of microcontrollers. PICDEM 4 is intended to show-
case the many features of these low pin count parts,
including LIN and Motor Control using ECCP. Special
provisions are made for low power operation with the
supercapacitor circuit, and jumpers allow on-board
hardware to be disabled to eliminate current draw in
this mode. Included on the demo board are provisions
for Crystal, RC or Canned Oscillator modes, a five volt
regulator for use with a nine volt wall adapter or battery,
DB-9 RS-232 interface, ICD connector for program-
ming via ICSP and development with MPLAB ICD 2,
2x16 liquid crystal display, PCB footprints for H-Bridge
motor driver, LIN transceiver and EEPROM. Also
included are: header for expansion, eight LEDs, four
potentiometers, three push buttons and a prototyping
area. Included with the kit is a PIC16F627A and a
PIC18F1320. Tutorial firmware is included along with
the User’s Guide.
26.15 PICDEM.net Internet/Ethernet
Demonstration Board
The PICDEM.net demonstration board is an Internet/
Ethernet demonstration board using the PIC18F452
microcontroller and TCP/IP firmware. The board
supports any 40-pin DIP device that conforms to the
standard pinout used by the PIC16F877 or
PIC18C452. This kit features a user friendly TCP/IP
stack, web server with HTML, a 24L256 Serial
EEPROM for Xmodem download to web pages into
Serial EEPROM, ICSP/MPLAB ICD 2 interface con-
nector, an Ethernet interface, RS-232 interface, and a
16 x 2 LCD display. Also included is the book and
CD-ROM “TCP/IP Lean, Web Servers for Embedded
Systems,” by Jeremy Bentham
26.19 PICDEM 17 Demonstration Board
The PICDEM 17 demonstration board is an evaluation
board that demonstrates the capabilities of several
Microchip microcontrollers, including PIC17C752,
PIC17C756A, PIC17C762 and PIC17C766. A pro-
grammed sample is included. The PRO MATE II device
programmer, or the PICSTART Plus development pro-
grammer, can be used to reprogram the device for user
tailored application development. The PICDEM 17
demonstration board supports program download and
execution from external on-board FLASH memory. A
generous prototype area is available for user hardware
expansion.
26.16 PICDEM 2 Plus
Demonstration Board
The PICDEM 2 Plus demonstration board supports
many 18-, 28-, and 40-pin microcontrollers, including
PIC16F87X and PIC18FXX2 devices. All the neces-
sary hardware and software is included to run the dem-
onstration programs. The sample microcontrollers
provided with the PICDEM 2 demonstration board can
be programmed with a PRO MATE II device program-
mer, PICSTART Plus development programmer, or
MPLAB ICD 2 with a Universal Programmer Adapter.
The MPLAB ICD 2 and MPLAB ICE in-circuit emulators
may also be used with the PICDEM 2 demonstration
board to test firmware. A prototype area extends the
circuitry for additional application components. Some
of the features include an RS-232 interface, a 2 x 16
LCD display, a piezo speaker, an on-board temperature
sensor, four LEDs, and sample PIC18F452 and
PIC16F877 FLASH microcontrollers.
DS39612A-page 322
Advance Information
2003 Microchip Technology Inc.
PIC18F6X2X/8X2X
26.20 PICDEM 18R PIC18C601/801
Demonstration Board
26.23 PICDEM USB PIC16C7X5
Demonstration Board
The PICDEM 18R demonstration board serves to assist
development of the PIC18C601/801 family of Microchip
microcontrollers. It provides hardware implementation
of both 8-bit Multiplexed/De-multiplexed and 16-bit
Memory modes. The board includes 2 Mb external
FLASH memory and 128 Kb SRAM memory, as well as
serial EEPROM, allowing access to the wide range of
memory types supported by the PIC18C601/801.
The PICDEM USB Demonstration Board shows off the
capabilities of the PIC16C745 and PIC16C765 USB
microcontrollers. This board provides the basis for
future USB products.
26.24 Evaluation and
Programming Tools
In addition to the PICDEM series of circuits, Microchip
has a line of evaluation kits and demonstration software
for these products.
26.21 PICDEM LIN PIC16C43X
Demonstration Board
• KEELOQ evaluation and programming tools for
Microchip’s HCS Secure Data Products
The powerful LIN hardware and software kit includes a
series of boards and three PICmicro microcontrollers.
The small footprint PIC16C432 and PIC16C433 are
used as slaves in the LIN communication and feature
on-board LIN transceivers. A PIC16F874 FLASH
microcontroller serves as the master. All three micro-
controllers are programmed with firmware to provide
LIN bus communication.
• CAN developers kit for automotive network
applications
• Analog design boards and filter design software
• PowerSmart battery charging evaluation/
calibration kits
• IrDA® development kit
• microID development and rfLabTM development
software
• SEEVAL® designer kit for memory evaluation and
endurance calculations
26.22 PICkitTM 1 FLASH Starter Kit
A complete "development system in a box", the PICkit
FLASH Starter Kit includes a convenient multi-section
board for programming, evaluation, and development
of 8/14-pin FLASH PIC® microcontrollers. Powered via
USB, the board operates under a simple Windows GUI.
The PICkit 1 Starter Kit includes the user's guide (on
CD ROM), PICkit 1 tutorial software and code for vari-
ous applications. Also included are MPLAB® IDE (Inte-
grated Development Environment) software, software
and hardware "Tips 'n Tricks for 8-pin FLASH PIC®
Microcontrollers" Handbook and a USB Interface
Cable. Supports all current 8/14-pin FLASH PIC
microcontrollers, as well as many future planned
devices.
• PICDEM MSC demo boards for Switching mode
power supply, high power IR driver, delta sigma
ADC, and flow rate sensor
Check the Microchip web page and the latest Product
Line Card for the complete list of demonstration and
evaluation kits.
2003 Microchip Technology Inc.
Advance Information
DS39612A-page 323
PIC18F6X2X/8X2X
NOTES:
DS39612A-page 324
Advance Information
2003 Microchip Technology Inc.
PIC18F6X2X/8X2X
27.0 ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings(†)
Ambient temperature under bias.............................................................................................................-55°C to +125°C
Storage temperature .............................................................................................................................. -65°C to +150°C
Voltage on any pin with respect to VSS (except VDD, MCLR, and RA4) ......................................... -0.3V to (VDD + 0.3V)
Voltage on VDD with respect to VSS ......................................................................................................... -0.3V to +5.5V
Voltage on MCLR with respect to VSS (Note 2) ......................................................................................... 0V to +13.25V
Voltage on RA4 with respect to Vss............................................................................................................... 0V to +8.5V
Total power dissipation (Note 1) ...............................................................................................................................1.0W
Maximum current out of VSS pin ...........................................................................................................................300 mA
Maximum current into VDD pin ..............................................................................................................................250 mA
Input clamp current, IIK (VI < 0 or VI > VDD)...................................................................................................................... 20 mA
Output clamp current, IOK (VO < 0 or VO > VDD) .............................................................................................................. 20 mA
Maximum output current sunk by any I/O pin..........................................................................................................25 mA
Maximum output current sourced by any I/O pin ....................................................................................................25 mA
Maximum current sunk by all ports .......................................................................................................................200 mA
Maximum current sourced by all ports ..................................................................................................................200 mA
Note 1: Power dissipation is calculated as follows:
Pdis = VDD x {IDD – ∑ IOH} + ∑ {(VDD – VOH) x IOH} + ∑(VOL x IOL)
2: Voltage spikes below VSS at the MCLR/VPP pin, inducing currents greater than 80 mA, may cause latchup.
Thus, a series resistor of 50-100Ω should be used when applying a “low” level to the MCLR/VPP pin, rather
than pulling this pin directly to VSS.
† NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at those or any other conditions above those
indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for
extended periods may affect device reliability.
2003 Microchip Technology Inc.
Advance Information
DS39612A-page 325
PIC18F6X2X/8X2X
FIGURE 27-1:
PIC18F6X2X/8X2XVOLTAGE-FREQUENCYGRAPH(INDUSTRIAL,EXTENDED)
6.0V
5.5V
5.0V
4.5V
4.0V
PIC18F6X2X/8X2X
4.2V
3.5V
3.0V
2.5V
2.0V
25 MHz
(Extended)
40 MHz
(Industrial)
Frequency
FIGURE 27-2:
PIC18LF6X2X/8X2X VOLTAGE-FREQUENCY GRAPH (INDUSTRIAL)
6.0V
5.5V
5.0V
4.5V
4.0V
PIC18LF6X2X/8X2X
4.2V
3.5V
3.0V
2.5V
2.0V
40 MHz
4 MHz
Frequency
FMAX = (16.36 MHz/V) (VDDAPPMIN - 2.0V) + 4 MHz
Note: VDDAPPMIN is the minimum voltage of the PICmicro® device in the application.
DS39612A-page 326
Advance Information
2003 Microchip Technology Inc.
PIC18F6X2X/8X2X
27.1 DC Characteristics: Supply Voltage
PIC18F6X2X/8X2X (Industrial, Extended)
PIC18LF6X2X/8X2X (Industrial)
PIC18LF6X2X/8X2X
Standard Operating Conditions (unless otherwise stated)
(Industrial)
Operating temperature
-40°C ≤ TA ≤ +85°C for industrial
Standard Operating Conditions (unless otherwise stated)
PIC18F6X2X/8X2X
Operating temperature
-40°C ≤ TA ≤ +85°C for industrial
-40°C ≤ TA ≤ +125°C for extended
(Industrial, Extended)
Param
Symbol
No.
Characteristic
Supply Voltage
Min
Typ
Max Units
Conditions
D001
VDD
PIC18LF6X2X/8X2X 2.0
PIC18F6X2X/8X2X 4.2
—
—
—
5.5
5.5
—
V
V
V
HS, XT, RC and LP Osc mode
D002
D003
VDR
RAM Data Retention
1.5
(1)
Voltage
VPOR
VDD Start Voltage
to ensure internal
Power-on Reset signal
—
—
—
0.7
—
V
See section on Power-on Reset for details
D004
D005
SVDD
VBOR
VDD Rise Rate
to ensure internal
Power-on Reset signal
0.05
V/ms See section on Power-on Reset for details
Brown-out Reset Voltage
BORV1:BORV0 = 11
BORV1:BORV0 = 10
BORV1:BORV0 = 01
BORV1:BORV0 = 00
1.98
2.67
4.16
4.45
—
—
—
—
2.14
2.89
4.5
V
V
V
V
4.83
Legend:
Shading of rows is to assist in readability of the table.
Note 1: This is the limit to which VDD can be lowered in SLEEP mode or during a device RESET without losing RAM data.
2003 Microchip Technology Inc.
Advance Information
DS39612A-page 327
PIC18F6X2X/8X2X
27.2 DC Characteristics: Power-Down and Supply Current
PIC18F6X2X/8X2X (Industrial, Extended)
PIC18LF6X2X/8X2X (Industrial)
PIC18LF6X2X/8X2X
Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C ≤ TA ≤ +85°C for industrial
(Industrial)
Standard Operating Conditions (unless otherwise stated)
PIC18F6X2X/8X2X
Operating temperature
-40°C ≤ TA ≤ +85°C for industrial
-40°C ≤ TA ≤ +125°C for extended
(Industrial, Extended)
Param
No.
Device
Power-down Current (IPD)
Typ
Max Units
Conditions
(1)
PIC18LF6X2X/8X2X 0.2
1
1
µA
µA
µA
µA
µA
µA
µA
µA
µA
-40°C
25°C
85°C
-40°C
25°C
85°C
-40°C
25°C
85°C
VDD = 2.0V,
(SLEEP mode)
0.2
1.2
5
PIC18LF6X2X/8X2X 0.4
1
VDD = 3.0V,
(SLEEP mode)
0.4
1
1.8
8
All devices 0.7
2
VDD = 5.0V,
(SLEEP mode)
0.7
3.0
2
15
Legend:
Shading of rows is to assist in readability of the table.
Note 1: The power-down current in SLEEP mode does not depend on the oscillator type. Power-down current is measured with
the part in SLEEP mode, with all I/O pins in high-impedance state and tied to VDD or VSS, and all features that add delta
current disabled (such as WDT, Timer1 Oscillator, BOR, etc.).
2: The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading
and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on
the current consumption.
The test conditions for all IDD measurements in active operation mode are:
OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD;
MCLR = VDD; WDT enabled/disabled as specified.
3: For RC oscillator configurations, current through REXT is not included. The current through the resistor can be estimated
by the formula Ir = VDD/2REXT (mA) with REXT in kΩ.
DS39612A-page 328
Advance Information
2003 Microchip Technology Inc.
PIC18F6X2X/8X2X
27.2 DC Characteristics: Power-Down and Supply Current
PIC18F6X2X/8X2X (Industrial, Extended)
PIC18LF6X2X/8X2X (Industrial) (Continued)
PIC18LF6X2X/8X2X
Standard Operating Conditions (unless otherwise stated)
(Industrial)
Operating temperature
-40°C ≤ TA ≤ +85°C for industrial
Standard Operating Conditions (unless otherwise stated)
PIC18F6X2X/8X2X
Operating temperature
-40°C ≤ TA ≤ +85°C for industrial
-40°C ≤ TA ≤ +125°C for extended
(Industrial, Extended)
Param
No.
Device
Supply Current (IDD)
Typ
Max Units
Conditions
(2,3)
PIC18LF6X2X/8X2X 165
350
350
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
mA
mA
mA
-40°C
165
25°C
85°C
-40°C
25°C
85°C
-40°C
25°C
85°C
-40°C
25°C
85°C
-40°C
25°C
85°C
-40°C
25°C
85°C
VDD = 2.0V
VDD = 3.0V
VDD = 5.0V
VDD = 2.0V
VDD = 3.0V
VDD = 5.0V
170
350
PIC18LF6X2X/8X2X 360
750
FOSC = 1 MHZ,
EC oscillator
340
750
300
750
All devices 800
1700
1700
1700
1200
1200
1300
730
700
PIC18LF6X2X/8X2X 600
600
640
PIC18LF6X2X/8X2X 1000 2500
1000 2500
FOSC = 4 MHz,
EC oscillator
1000 2500
All devices 2.2
5.0
5.0
5.0
2.1
2.0
Legend:
Shading of rows is to assist in readability of the table.
Note 1: The power-down current in SLEEP mode does not depend on the oscillator type. Power-down current is measured with
the part in SLEEP mode, with all I/O pins in high-impedance state and tied to VDD or VSS, and all features that add delta
current disabled (such as WDT, Timer1 Oscillator, BOR, etc.).
2: The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading
and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on
the current consumption.
The test conditions for all IDD measurements in active operation mode are:
OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD;
MCLR = VDD; WDT enabled/disabled as specified.
3: For RC oscillator configurations, current through REXT is not included. The current through the resistor can be estimated
by the formula Ir = VDD/2REXT (mA) with REXT in kΩ.
2003 Microchip Technology Inc.
Advance Information
DS39612A-page 329
PIC18F6X2X/8X2X
27.2 DC Characteristics: Power-Down and Supply Current
PIC18F6X2X/8X2X (Industrial, Extended)
PIC18LF6X2X/8X2X (Industrial) (Continued)
PIC18LF6X2X/8X2X
Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C ≤ TA ≤ +85°C for industrial
(Industrial)
Standard Operating Conditions (unless otherwise stated)
PIC18F6X2X/8X2X
Operating temperature
-40°C ≤ TA ≤ +85°C for industrial
-40°C ≤ TA ≤ +125°C for extended
(Industrial, Extended)
Param
No.
Device
Supply Current (IDD)
Typ
Max Units
Conditions
(2,3)
All devices 9.3
15
15
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
µA
-40°C
9.5
25°C
85°C
-40°C
25°C
85°C
-40°C
25°C
85°C
-40°C
25°C
85°C
-10°C
25°C
70°C
-10°C
25°C
70°C
-10°C
25°C
70°C
VDD = 4.2V
VDD = 5.0V
VDD = 4.2V
10
15
FOSC = 25 MHZ,
EC oscillator
All devices 11.8
20
12
12
20
20
All devices
All devices
14
14
15
19
19
20
15
15
15
28
28
28
75
75
75
25
25
25
FOSC = 40 MHZ,
EC oscillator
25
25
VDD = 5.0V
VDD = 2.0V
VDD = 3.0V
VDD = 5.0V
25
PIC18LF6X2X/8X2X
PIC18LF6X2X/8X2X
All devices
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
µA
µA
µA
FOSC = 32 kHz,
Timer1 as clock
µA
µA
µA
µA
µA
Legend:
Shading of rows is to assist in readability of the table.
Note 1: The power-down current in SLEEP mode does not depend on the oscillator type. Power-down current is measured with
the part in SLEEP mode, with all I/O pins in high-impedance state and tied to VDD or VSS, and all features that add delta
current disabled (such as WDT, Timer1 Oscillator, BOR, etc.).
2: The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading
and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on
the current consumption.
The test conditions for all IDD measurements in active operation mode are:
OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD;
MCLR = VDD; WDT enabled/disabled as specified.
3: For RC oscillator configurations, current through REXT is not included. The current through the resistor can be estimated
by the formula Ir = VDD/2REXT (mA) with REXT in kΩ.
DS39612A-page 330
Advance Information
2003 Microchip Technology Inc.
PIC18F6X2X/8X2X
27.2 DC Characteristics: Power-Down and Supply Current
PIC18F6X2X/8X2X (Industrial, Extended)
PIC18LF6X2X/8X2X (Industrial) (Continued)
PIC18LF6X2X/8X2X
Standard Operating Conditions (unless otherwise stated)
(Industrial)
Operating temperature
-40°C ≤ TA ≤ +85°C for industrial
Standard Operating Conditions (unless otherwise stated)
PIC18F6X2X/8X2X
Operating temperature
-40°C ≤ TA ≤ +85°C for industrial
-40°C ≤ TA ≤ +125°C for extended
(Industrial, Extended)
Param
No.
Device
Typ
Max Units
Conditions
Module Differential Currents (∆IWDT, ∆IBOR, ∆ILVD, ∆IOSCB, ∆IAD)
D022
(∆IWDT)
Watchdog Timer <1
2.0
1.5
3
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
-40°C
25°C
VDD = 2.0V
VDD = 3.0V
VDD = 5.0V
<1
<1
3
85°C
10
-40°C
2.5
3
6
25°C
15
85°C
15
12
12
25
-40°C
20
25°C
25
85°C
VDD = 3.0V
VDD = 5.0V
VDD = 2.0V
VDD = 3.0V
VDD = 5.0V
D022A
(∆IBOR)
D022B
(∆ILVD)
Brown-out Reset
35
45
33
35
45
50
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-10°C
65
Low Voltage Detect
45
50
65
D025
Timer1 Oscillator 5.2
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
2
VDD = 2.0V
VDD = 3.0V
VDD = 5.0V
32 kHz on Timer1
(∆IOSCB)
5.2
25°C
5.2
70°C
5.8
-10°C
32 kHz on Timer1
32 kHz on Timer1
5.8
25°C
5.8
70°C
7.2
-10°C
7.2
25°C
7.2
70°C
VDD = 2.0V
VDD = 3.0V
VDD = 5.0V
D026
(∆IAD)
A/D Converter <1
25°C
A/D on, not converting
<1
<1
2
25°C
2
25°C
Legend:
Shading of rows is to assist in readability of the table.
Note 1: The power-down current in SLEEP mode does not depend on the oscillator type. Power-down current is measured with
the part in SLEEP mode, with all I/O pins in high-impedance state and tied to VDD or VSS, and all features that add delta
current disabled (such as WDT, Timer1 Oscillator, BOR, etc.).
2: The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading
and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on
the current consumption.
The test conditions for all IDD measurements in active operation mode are:
OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD;
MCLR = VDD; WDT enabled/disabled as specified.
3: For RC oscillator configurations, current through REXT is not included. The current through the resistor can be estimated
by the formula Ir = VDD/2REXT (mA) with REXT in kΩ.
2003 Microchip Technology Inc.
Advance Information
DS39612A-page 331
PIC18F6X2X/8X2X
27.3 DC Characteristics: PIC18F6X2X/8X2X (Industrial, Extended)
PIC18LF6X2X/8X2X (Industrial)
Standard Operating Conditions (unless otherwise stated)
DC CHARACTERISTICS
Operating temperature -40°C ≤ TA ≤ +85°C for industrial
-40°C ≤ TA ≤ +125°C for extended
Param
Symbol
No.
Characteristic
Min
Max
Units
Conditions
VIL
Input Low Voltage
I/O ports:
with TTL buffer
D030
D030A
D031
VSS
—
0.15 VDD
0.8
V
V
VDD < 4.5V
4.5V ≤ VDD ≤ 5.5V
with Schmitt Trigger buffer
RC3 and RC4
VSS
VSS
0.2 VDD
0.3 VDD
V
V
D032
MCLR
VSS
VSS
0.2 VDD
0.3 VDD
V
V
D032A
OSC1 (in XT, HS and LP modes)
and T1OSI
D033
OSC1 (in RC and EC mode)(1)
Input High Voltage
I/O ports:
VSS
0.2 VDD
V
VIH
D040
with TTL buffer
0.25 VDD +
0.8V
VDD
VDD
V
V
VDD < 4.5V
D040A
D041
2.0
4.5V ≤ VDD ≤ 5.5V
with Schmitt Trigger buffer
RC3 and RC4
0.8 VDD
0.7 VDD
VDD
VDD
V
V
D042
MCLR, OSC1 (EC mode)
0.8 VDD
0.7 VDD
VDD
VDD
V
V
D042A
OSC1 (in XT, HS and LP modes)
and T1OSI
D043
D060
OSC1 (RC mode)(1)
Input Leakage Current(2,3)
I/O ports
0.9 VDD
—
VDD
1
V
IIL
µA VSS ≤ VPIN ≤ VDD,
Pin at hi-impedance
D061
D063
MCLR
—
—
5
5
µA VSS ≤ VPIN ≤ VDD
µA VSS ≤ VPIN ≤ VDD
OSC1
IPU
Weak Pull-up Current
PORTB weak pull-up current
D070
IPURB
50
400
µA VDD = 5V, VPIN = VSS
Note 1: In RC oscillator configuration, the OSC1/CLKI pin is a Schmitt Trigger input. It is not recommended that the
PICmicro device be driven with an external clock while in RC mode.
2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified
levels represent normal operating conditions. Higher leakage current may be measured at different input
voltages.
3: Negative current is defined as current sourced by the pin.
4: Parameter is characterized but not tested.
DS39612A-page 332
Advance Information
2003 Microchip Technology Inc.
PIC18F6X2X/8X2X
27.3 DC Characteristics: PIC18F6X2X/8X2X (Industrial, Extended)
PIC18LF6X2X/8X2X (Industrial) (Continued)
Standard Operating Conditions (unless otherwise stated)
DC CHARACTERISTICS
Operating temperature -40°C ≤ TA ≤ +85°C for industrial
-40°C ≤ TA ≤ +125°C for extended
Param
Symbol
No.
Characteristic
Min
Max
Units
Conditions
VOL
VOH
VOD
Output Low Voltage
I/O ports
D080
—
—
—
—
0.6
0.6
0.6
0.6
V
V
V
V
IOL = 8.5 mA, VDD = 4.5V,
-40°C to +85°C
IOL = 7.0 mA, VDD = 4.5V,
-40°C to +125°C
D080A
D083
OSC2/CLKO
(RC mode)
IOL = 1.6 mA, VDD = 4.5V,
-40°C to +85°C
D083A
IOL = 1.2 mA, VDD = 4.5V,
-40°C to +125°C
Output High Voltage(3)
D090
I/O ports
VDD – 0.7
VDD – 0.7
VDD – 0.7
VDD – 0.7
—
—
—
V
V
V
V
V
IOH = -3.0 mA, VDD = 4.5V,
-40°C to +85°C
IOH = -2.5 mA, VDD = 4.5V,
-40°C to +125°C
D090A
D092
OSC2/CLKO
(RC mode)
—
IOH = -1.3 mA, VDD = 4.5V,
-40°C to +85°C
D092A
D150
—
IOH = -1.0 mA, VDD = 4.5V,
-40°C to +125°C
RA4 pin
Open Drain High Voltage
8.5
Capacitive Loading Specs
on Output Pins
D100(4)
COSC2 OSC2 pin
—
15
pF In XT, HS and LP modes
when external clock is used
to drive OSC1
D101
D102
CIO
CB
All I/O pins and OSC2
(in RC mode)
—
—
50
pF To meet the AC Timing
Specifications
pF In I2C mode
SCL, SDA
400
Note 1: In RC oscillator configuration, the OSC1/CLKI pin is a Schmitt Trigger input. It is not recommended that the
PICmicro device be driven with an external clock while in RC mode.
2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified
levels represent normal operating conditions. Higher leakage current may be measured at different input
voltages.
3: Negative current is defined as current sourced by the pin.
4: Parameter is characterized but not tested.
2003 Microchip Technology Inc.
Advance Information
DS39612A-page 333
PIC18F6X2X/8X2X
TABLE 27-1: COMPARATOR SPECIFICATIONS
Operating Conditions: 3.0V < VDD < 5.5V, -40°C < TA < +125°C (unless otherwise stated)
Param
No.
Characteristics
Sym
Min
Typ
Max
Units
Comments
D300
Input Offset Voltage
Input Common Mode Voltage
VIOFF
VICM
—
0
± 5.0
± 10
VDD – 1.5
—
mV
V
D301
D302
-
-
Common Mode Rejection Ratio CMRR
55
—
dB
Response Time(1)
TRESP
300
300A
150
400
600
ns
ns
PIC18F6X2X/8X2X
PIC18LF6X2X/8X2X
301
Comparator Mode Change to
Output Valid
TMC2OV
—
—
10
µs
Note 1: Response time measured with one comparator input at (VDD – 1.5)/2 while the other input transitions from
VSS to VDD.
TABLE 27-2: VOLTAGE REFERENCE SPECIFICATIONS
Operating Conditions: 3.0V < VDD < 5.5V, -40°C < TA < +125°C (unless otherwise stated)
Spec
No.
Characteristics
Resolution
Sym
Min
Typ
Max
Units
Comments
D310
VRES
VDD/24
—
VDD/32
LSb
D311
Absolute Accuracy
VRAA
—
—
—
—
1/4
1/2
LSb Low Range (VRR = 1)
LSb High Range (VRR = 0)
D312
310
Unit Resistor Value (R)
Settling Time(1)
VRUR
TSET
—
—
2k
—
—
Ω
µs
10
Note 1: Settling time measured while VRR = 1and VR<3:0> transitions from 0000to 1111.
DS39612A-page 334
Advance Information
2003 Microchip Technology Inc.
PIC18F6X2X/8X2X
FIGURE 27-3:
LOW VOLTAGE DETECT CHARACTERISTICS
VDD
(LVDIF can be
cleared in software)
VLVD
(LVDIF set by hardware)
LVDIF
TABLE 27-3: LOW VOLTAGE DETECT CHARACTERISTICS
Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C ≤ TA ≤ +85°C for industrial
-40°C ≤ TA ≤ +125°C for extended
Param
No.
Symbol
Characteristic
Min
Typ† Max
Units
Conditions
LVV = 0001
LVV = 0010
LVV = 0011
LVV = 0100
LVV = 0101
LVV = 0110
LVV = 0111
LVV = 1000
LVV = 1001
LVV = 1010
LVV = 1011
LVV = 1100
LVV = 1101
LVV = 1110
1.98
2.18
2.37
2.48
2.67
2.77
2.98
3.27
3.47
3.57
3.76
3.96
4.16
4.45
—
2.06
2.27
2.47
2.58
2.78
2.89
3.1
2.14
2.36
2.57
2.68
2.89
3.01
3.22
3.55
3.75
3.87
4.08
4.3
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
T ≥ 25°C
D420
VLVD
LVD Voltage on
VDD transition high
to low
T ≥ 25°C
T ≥ 25°C
3.41
3.61
3.72
3.92
4.13
4.33
4.64
1.22
4.5
4.83
—
D423
VBG
Bandgap Reference Voltage
Value
†
Production tested at TAMB = 25°C. Specifications over temp. limits ensured by characterization.
2003 Microchip Technology Inc.
Advance Information
DS39612A-page 335
PIC18F6X2X/8X2X
TABLE 27-4: MEMORY PROGRAMMING REQUIREMENTS
Standard Operating Conditions (unless otherwise stated)
DC Characteristics
Operating temperature -40°C ≤ TA ≤ +85°C for industrial
-40°C ≤ TA ≤ +125°C for extended
Param
Sym
No.
Characteristic
Min
Typ†
Max Units
Conditions
Internal Program Memory
Programming Specifications
(Note 1)
VPP
IPP
9.00
—
—
—
—
13.25
5
V
(Note 2)
D110
D112
D113
Voltage on MCLR/VPP pin
Current into MCLR/VPP pin
µA
mA
IDDP
—
10
Supply Current during
Programming
Data EEPROM Memory
Cell Endurance
D120
ED
100K
10K
1M
100K
—
—
—
E/W -40°C to +85°C
E/W +85°C to +125°C
D120A ED
Cell Endurance
D121 VDRW VDD for Read/Write
VMIN
5.5
V
Using EECON to read/write
VMIN = Minimum operating
voltage
D122 TDEW Erase/Write Cycle Time
D123 TRETD Characteristic Retention
D123A TRETD Characteristic Retention
Program FLASH Memory
—
40
4
—
—
—
ms
—
—
Year -40°C to +85°C (Note 3)
Year 25°C (Note3)
100
D130
EP
Cell Endurance
Cell Endurance
VDD for Read
10K
1000
VMIN
100K
10K
—
—
—
E/W -40°C to +85°C
E/W +85°C to +125°C
D130A EP
D131
D132
VPR
VIE
5.5
V
VMIN = Minimum operating
voltage
VDD for Block Erase
4.5
4.5
—
—
5.5
5.5
V
V
Using ICSP port
Using ICSP port
D132A VIW
VDD for Externally Timed Erase
or Write
D132B VPEW VDD for Self-timed Write
VMIN
—
5.5
V
VMIN = Minimum operating
voltage
D133
TIE
ICSP Block Erase Cycle Time
—
1
5
—
—
ms VDD > 4.5V
ms VDD > 4.5V
D133A TIW
ICSP Erase or Write Cycle Time
(externally timed)
—
D133A TIW
Self-timed Write Cycle Time
—
40
2.5
—
—
—
—
ms
D134 TRETD Characteristic Retention
D134A TRETD Characteristic Retention
Year -40°C to +85°C (Note3)
Year 25°C (Note3)
100
—
†
Data in “Typ” column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance
only and are not tested.
Note 1: These specifications are for programming the on-chip program memory through the use of table write
instructions.
2: The pin may be kept in this range at times other than programming but it is not recommended.
3: Retention time is valid provided no other specifications are violated.
DS39612A-page 336
Advance Information
2003 Microchip Technology Inc.
PIC18F6X2X/8X2X
27.4 AC (Timing) Characteristics
27.4.1 TIMING PARAMETER SYMBOLOGY
The timing parameter symbols have been created
following one of the following formats:
1. TppS2ppS
2. TppS
T
3. TCC:ST
4. Ts
(I2C specifications only)
(I2C specifications only)
F
Frequency
T
Time
Lowercase letters (pp) and their meanings:
pp
cc
ck
cs
di
CCP1
CLKO
CS
osc
rd
OSC1
RD
rw
sc
ss
t0
RD or WR
SCK
SDI
do
dt
SDO
SS
Data in
I/O port
MCLR
T0CKI
T1CKI
WR
io
t1
mc
wr
Uppercase letters and their meanings:
S
F
Fall
P
R
V
Z
Period
H
High
Rise
I
Invalid (Hi-impedance)
Low
Valid
L
Hi-impedance
I2C only
AA
output access
Bus free
High
Low
High
Low
BUF
TCC:ST (I2C specifications only)
CC
HD
Hold
SU
Setup
ST
DAT
STA
DATA input hold
START condition
STO
STOP condition
2003 Microchip Technology Inc.
Advance Information
DS39612A-page 337
PIC18F6X2X/8X2X
27.4.2
TIMING CONDITIONS
The temperature and voltages specified in Table 27-5
apply to all timing specifications, unless otherwise
noted. Figure 27-4 specifies the load conditions for the
timing specifications.
TABLE 27-5: TEMPERATURE AND VOLTAGE SPECIFICATIONS - AC
Standard Operating Conditions (unless otherwise stated)
Operating temperature
-40°C ≤ TA ≤ +85°C for industrial
-40°C ≤ TA ≤ +125°C for extended
AC CHARACTERISTICS
Operating voltage VDD range as described in DC spec Section 27.1 and
Section 27.3.
LC parts operate for industrial temperatures only.
FIGURE 27-4:
LOAD CONDITIONS FOR DEVICE TIMING SPECIFICATIONS
Load condition 1 Load condition 2
VDD/2
CL
RL
Pin
VSS
CL
Pin
RL = 464Ω
CL = 50 pF for all pins except OSC2/CLKO
and including D and E outputs as ports
VSS
DS39612A-page 338
Advance Information
2003 Microchip Technology Inc.
PIC18F6X2X/8X2X
27.4.3
TIMING DIAGRAMS AND SPECIFICATIONS
FIGURE 27-5:
EXTERNAL CLOCK TIMING (ALL MODES EXCEPT PLL)
Q4
Q1
Q2
Q3
Q4
Q1
OSC1
CLKO
1
3
4
3
4
2
TABLE 27-6: EXTERNAL CLOCK TIMING REQUIREMENTS
Param. No. Symbol
Characteristic
Min
Max
Units
Conditions
(1)
1A
FOSC
External CLKI Frequency
Oscillator Frequency
DC
DC
DC
0.1
4
25
40
4
MHz
MHz
MHz
MHz
MHz
MHz
MHz
kHz
EC, ECIO
EC, ECIO
RC osc
(1)
4
XT osc
25
10
6.25
200
HS osc
4
HS + PLL osc
HS + PLL osc
LP Osc mode
4
5
(1)
1
TOSC
External CLKI Period
Oscillator Period
25
—
—
ns
ns
ns
ns
EC, ECIO
EC, ECIO
RC osc
(1)
160
250
250
—
10,000
XT osc
25
100
100
250
250
160
ns
ns
ns
HS osc
HS + PLL osc
HS + PLL osc
25
—
µs
LP osc
(1)
2
3
TCY
Instruction Cycle Time
100
30
2.5
10
—
—
—
ns
ns
µs
ns
ns
ns
ns
TCY = 4/FOSC
XT osc
TosL,
TosH
External Clock in (OSC1)
High or Low Time
—
LP osc
—
HS osc
XT osc
4
TosR,
TosF
External Clock in (OSC1) Rise
or Fall Time
20
50
7.5
—
LP osc
—
HS osc
Note 1: Instruction cycle period (TCY) equals four times the input oscillator time base period for all configurations except PLL. All
specified values are based on characterization data for that particular oscillator type under standard operating condi-
tions with the device executing code. Exceeding these specified limits may result in an unstable oscillator operation
and/or higher than expected current consumption. All devices are tested to operate at “min.” values with an external
clock applied to the OSC1/CLKI pin. When an external clock input is used, the “max.” cycle time limit is “DC” (no clock)
for all devices.
TABLE 27-7: PLL CLOCK TIMING SPECIFICATIONS (VDD = 4.2 TO 5.5V)
Param. No. Sym
Characteristic
Min
Typ†
Max
Units
Conditions
FOSC
Oscillator Frequency Range
4
—
10
MHz HS mode
FSYS
On-chip VCO System Frequency
PLL Start-up Time (Lock Time)
CLKO Stability (Jitter)
16
—
-2
—
—
—
40
2
MHz HS mode
t
ms
%
rc
∆CLK
+2
†
Data in “Typ” column is at 5V, 25°C, unless otherwise stated. These parameters are for design guidance only and are
not tested.
2003 Microchip Technology Inc.
Advance Information
DS39612A-page 339
PIC18F6X2X/8X2X
FIGURE 27-6:
CLKO AND I/O TIMING
Q1
Q2
Q3
Q4
OSC1
11
10
CLKO
13
14
12
19
18
16
I/O pin
(input)
15
17
I/O pin
(output)
New Value
Old Value
20, 21
Refer to Figure 27-4 for load conditions.
Note:
TABLE 27-8: CLKO AND I/O TIMING REQUIREMENTS
Param.
No.
Symbol
Characteristic
Min
Typ
Max
Units Conditions
10
TosH2ckL OSC1 ↑ to CLKO ↓
TosH2ckH OSC1 ↑ to CLKO ↑
—
75
75
35
35
—
—
—
50
—
—
200
200
100
100
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
(Note 1)
(Note 1)
(Note 1)
(Note 1)
(Note 1)
(Note 1)
(Note 1)
11
—
12
13
14
15
16
17
18
18A
TckR
TckF
CLKO rise time
CLKO fall time
—
—
TckL2ioV CLKO ↓ to Port out valid
TioV2ckH Port in valid before CLKO ↑
—
0.5 TCY + 20
0.25 TCY + 25
—
—
TckH2ioI
Port in hold after CLKO ↑
0
TosH2ioV OSC1 ↑ (Q1 cycle) to Port out valid
—
150
—
TosH2ioI
OSC1 ↑ (Q2 cycle) to
Port input invalid
(I/O in hold time)
PIC18F6X2X/8X2X
PIC18LF6X2X/8X2X
100
200
—
19
TioV2osH Port input valid to OSC1 ↑
0
—
—
ns
(I/O in setup time)
20
TioR
TioF
Port output rise time
Port output fall time
INT pin high or low time
PIC18F6X2X/8X2X
PIC18LF6X2X/8X2X
PIC18F6X2X/8X2X
PIC18LF6X2X/8X2X
—
—
10
—
10
—
—
—
25
60
25
60
—
—
ns
ns
ns
ns
ns
ns
ns
20A
21
—
21A
22††
23††
24††
—
TINP
TCY
TCY
20
TRBP
TRCP
RB7:RB4 change INT high or low time
RC7:RC4 change INT high or low time
†† These parameters are asychronous events not related to any internal clock edges.
Note 1: Measurements are taken in RC mode, where CLKO output is 4 x TOSC.
DS39612A-page 340
Advance Information
2003 Microchip Technology Inc.
PIC18F6X2X/8X2X
FIGURE 27-7:
PROGRAM MEMORY READ TIMING DIAGRAM
Q1
Q2
Q3
Q4
Q1
Q2
OSC1
A<19:16>
BA0
Address
Address
Address
Address
Data from External
AD<15:0>
163
162
150
151
160
155
161
166
167
168
ALE
164
169
171
CE
OE
171A
165
Operating Conditions: 2.0V < VCC < 5.5V, -40°C < TA < 125°C unless otherwise stated.
TABLE 27-9: CLKO AND I/O TIMING REQUIREMENTS
Param.
Symbol
Characteristics
Min
Typ
Max
Units
No
150
TadV2alL Address out valid to ALE ↓ (address
0.25 TCY – 10
—
—
ns
setup time)
151
TalL2adl
ALE ↓ to address out invalid (address hold
time)
5
—
—
ns
155
160
161
162
163
164
165
166
167
168
169
171
171A
TalL2oeL ALE ↓ to OE ↓
10
0.125 TCY
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
TadZ2oeL AD high-Z to OE ↓ (bus release to OE)
ToeH2adD OE ↑ to AD driven
0
—
—
—
0.125 TCY – 5
—
TadV2oeH LS Data valid before OE ↑ (data setup time)
ToeH2adl OE ↑ to data in invalid (data hold time)
20
—
—
0
—
—
—
TalH2alL
ALE pulse width
TCY
0.5 TCY
0.25 TCY
—
—
ToeL2oeH OE pulse width
0.5 TCY – 5
—
—
TalH2alH ALE ↑ to ALE ↑ (cycle time)
—
Tacc
Address valid to data valid
0.75 TCY – 25
—
0.5 TCY – 25
0.625 TCY + 10
—
Toe
OE ↓ to data valid
—
TalL2oeH ALE ↓ to OE ↑
TalH2csL Chip Enable active to ALE ↓
TubL2oeH AD valid to Chip Enable active
0.625 TCY – 10
0.25 TCY – 20
—
—
—
—
10
2003 Microchip Technology Inc.
Advance Information
DS39612A-page 341
PIC18F6X2X/8X2X
FIGURE 27-8:
PROGRAM MEMORY WRITE TIMING DIAGRAM
Q1
Q2
Q3
Q4
Q1
Q2
OSC1
A<19:16>
BA0
Address
Address
Address
166
Data
156
Address
AD<15:0>
153
150
151
ALE
CE
171
171A
154
WRH or
WRL
157A
157
UB or LB
Operating Conditions: 2.0V < VCC < 5.5V, -40°C < TA < 125°C unless otherwise stated.
TABLE 27-10: PROGRAM MEMORY WRITE TIMING REQUIREMENTS
Param.
Symbol
Characteristics
Min
Typ
Max
Units
No
150
TadV2alL Address out valid to ALE ↓ (address setup time)
TalL2adl ALE ↓ to address out invalid (address hold time)
TwrH2adl WRn ↑ to data out invalid (data hold time)
0.25 TCY – 10
—
—
—
—
—
—
—
—
—
—
—
10
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
151
153
154
156
157
157A
166
171
171A
5
5
—
TwrL
WRn pulse width
0.5 TCY – 5
0.5 TCY – 10
0.25 TCY
0.125 TCY – 5
—
0.5 TCY
—
TadV2wrH Data valid before WRn ↑ (data setup time)
TbsV2wrL Byte select valid before WRn ↓ (byte select setup time)
TwrH2bsI WRn ↑ to byte select invalid (byte select hold time)
TalH2alH ALE ↑ to ALE ↑ (cycle time)
—
—
0.25 TCY
—
TalH2csL Chip Enable active to ALE ↓
0.25 TCY – 20
—
TubL2oeH AD valid to Chip Enable active
—
DS39612A-page 342
Advance Information
2003 Microchip Technology Inc.
PIC18F6X2X/8X2X
FIGURE 27-9:
RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP
TIMER TIMING
VDD
MCLR
30
Internal
POR
33
PWRT
Time-out
32
OSC
Time-out
Internal
RESET
Watchdog
Timer
Reset
31
34
34
I/O Pins
Note:
Refer to Figure 27-4 for load conditions.
FIGURE 27-10:
BROWN-OUT RESET TIMING
BVDD
VDD
35
VBGAP = 1.2V
VIRVST
Enable Internal Reference Voltage
Internal Reference Voltage stable
36
TABLE 27-11: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER
AND BROWN-OUT RESET REQUIREMENTS
Param.
No.
Symbol
Characteristic
Min
Typ
Max
Units
Conditions
30
TmcL
TWDT
MCLR Pulse Width (low)
2
7
—
—
µs
31
Watchdog Timer Time-out Period
(No Postscaler)
18
33
ms
32
33
34
TOST
Oscillation Start-up Timer Period
Power-up Timer Period
1024 TOSC
—
72
2
1024 TOSC
—
ms
µs
TOSC = OSC1 period
TPWRT
28
—
132
—
TIOZ
I/O high-impedance from MCLR Low
or Watchdog Timer Reset
35
36
TBOR
Brown-out Reset Pulse Width
200
—
—
—
µs
µs
VDD ≤ BVDD (see D005)
TIVRST
Time for Internal Reference
Voltage to become stable
20
50
37
TLVD
Low Voltage Detect Pulse Width
200
—
—
µs
VDD ≤ VLVD
2003 Microchip Technology Inc.
Advance Information
DS39612A-page 343
PIC18F6X2X/8X2X
FIGURE 27-11:
TIMER0 AND TIMER1 EXTERNAL CLOCK TIMINGS
T0CKI
41
40
42
T1OSO/T13CKI
46
45
47
48
TMR0 or
TMR1
Note:
Refer to Figure 27-4 for load conditions.
TABLE 27-12: TIMER0 AND TIMER1 EXTERNAL CLOCK REQUIREMENTS
Param.
No.
Symbol
Characteristic
Min
Max
Units
Conditions
40
Tt0H
T0CKI High Pulse Width No Prescaler
With Prescaler
0.5 TCY + 20
10
—
—
—
—
—
—
ns
ns
ns
ns
ns
41
42
Tt0L
Tt0P
T0CKI Low Pulse Width No Prescaler
With Prescaler
0.5 TCY + 20
10
T0CKI Period
No Prescaler
TCY + 10
With Prescaler
Greater of:
20 ns or TCY + 40
N
ns N = prescale
value
(1, 2, 4,..., 256)
45
46
Tt1H
Tt1L
T13CKI
High Time
Synchronous, no prescaler
0.5 TCY + 20
—
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Synchronous, PIC18F6X2X/8X2X
10
with prescaler
PIC18LF6X2X/8X2X
25
—
Asynchronous PIC18F6X2X/8X2X
PIC18LF6X2X/8X2X
30
—
50
0.5 TCY + 5
10
—
T13CKI
Low Time
Synchronous, no prescaler
Synchronous, PIC18F6X2X/8X2X
—
—
with prescaler
PIC18LF6X2X/8X2X
25
—
Asynchronous PIC18F6X2X/8X2X
PIC18LF6X2X/8X2X
30
—
TBD
TBD
—
47
48
Tt1P
Ft1
T13CKI
Input
Period
Synchronous
Greater of:
20 ns or TCY + 40
N
ns N = prescale
value (1, 2, 4, 8)
Asynchronous
60
DC
—
50
ns
kHz
—
T13CKI Oscillator Input Frequency Range
Tcke2tmrI Delay from External T13CKI Clock Edge to
Timer Increment
2 TOSC
7 TOSC
DS39612A-page 344
Advance Information
2003 Microchip Technology Inc.
PIC18F6X2X/8X2X
FIGURE 27-12:
CAPTURE/COMPARE/PWM TIMINGS (ALL CCP MODULES)
CCPx
(Capture Mode)
50
51
52
54
CCPx
(Compare or PWM Mode)
53
Refer to Figure 27-4 for load conditions.
Note:
TABLE 27-13: CAPTURE/COMPARE/PWM REQUIREMENTS (ALL CCP MODULES)
Param.
Symbol
Characteristic
Min
Max Units
Conditions
No.
50
TccL
CCPx Input
Low Time
No Prescaler
0.5 TCY + 20
—
—
—
—
—
—
—
ns
ns
ns
ns
ns
ns
With
Prescaler
PIC18F6X2X/8X2X
PIC18LF6X2X/8X2X
10
20
51
TccH
CCPx Input
High Time
No Prescaler
0.5 TCY + 20
With
PIC18F6X2X/8X2X
10
20
Prescaler
PIC18LF6X2X/8X2X
52
53
TccP
TccR
CCPx Input Period
3 TCY + 40
N
ns N = prescale
value (1,4 or 16)
CCPx Output Rise Time
PIC18F6X2X/8X2X
PIC18LF6X2X/8X2X
PIC18F6X2X/8X2X
PIC18LF6X2X/8X2X
—
—
—
—
25
45
25
45
ns
ns
ns
ns
54
TccF
CCPx Output Fall Time
2003 Microchip Technology Inc.
Advance Information
DS39612A-page 345
PIC18F6X2X/8X2X
FIGURE 27-13:
PARALLEL SLAVE PORT TIMING (PIC18F8X2X)
RE2/CS
RE0/RD
RE1/WR
65
RD7:RD0
62
64
63
Note:
Refer to Figure 27-4 for load conditions.
TABLE 27-14: PARALLEL SLAVE PORT REQUIREMENTS (PIC18F8X2X)
Param.
Symbol
Characteristic
Min
Max Units
Conditions
No.
62
TdtV2wrH Data in valid before WR ↑ or CS ↑
20
25
—
—
ns
ns
(setup time)
Extended Temp. range
63
64
TwrH2dtI
WR ↑ or CS ↑ to data–in PIC18F6X2X/8X2X
invalid (hold time)
20
35
—
—
ns
ns
PIC18LF6X2X/8X2X
TrdL2dtV RD ↓ and CS ↓ to data–out valid
—
—
80
90
ns
ns
Extended Temp. range
65
66
TrdH2dtI
TibfINH
RD ↑ or CS ↓ to data–out invalid
10
—
30
ns
Inhibit of the IBF flag bit being cleared from
3 TCY
WR ↑ or CS ↑
DS39612A-page 346
Advance Information
2003 Microchip Technology Inc.
PIC18F6X2X/8X2X
FIGURE 27-14:
EXAMPLE SPI MASTER MODE TIMING (CKE = 0)
SS
70
SCK
(CKP = 0)
71
72
78
79
79
78
SCK
(CKP = 1)
80
MSb
bit 6 - - - - - -1
LSb
SDO
SDI
75, 76
MSb In
74
bit 6 - - - -1
LSb In
73
Note: Refer to Figure 27-4 for load conditions.
TABLE 27-15: EXAMPLE SPI MODE REQUIREMENTS (MASTER MODE, CKE = 0)
Param.
Symbol
Characteristic
Min
Max Units Conditions
No.
70
TssL2scH, SS ↓ to SCK ↓ or SCK ↑ input
TssL2scL
TCY
—
ns
71
TscH
SCK input high time
(Slave mode)
Continuous
Single Byte
Continuous
Single Byte
1.25 TCY + 30
—
—
—
—
—
ns
71A
72
40
1.25 TCY + 30
40
ns (Note 1)
TscL
SCK input low time
(Slave mode)
ns
72A
73
ns (Note 1)
TdiV2scH, Setup time of SDI data input to SCK edge
TdiV2scL
100
ns
73A
74
TB2B
Last clock edge of Byte 1 to the 1st clock edge of 1.5 TCY + 40
Byte 2
—
—
ns (Note 2)
TscH2diL, Hold time of SDI data input to SCK edge
TscL2diL
100
ns
75
TdoR
SDO data output rise time PIC18F6X2X/8X2X
PIC18LF6X2X/8X2X
—
—
—
—
—
—
—
—
25
45
25
25
45
25
50
100
ns
ns
ns
ns
ns
ns
ns
ns
76
78
TdoF
TscR
SDO data output fall time
SCK output rise time
(Master mode)
PIC18F6X2X/8X2X
PIC18LF6X2X/8X2X
79
80
TscF
SCK output fall time (Master mode)
TscH2doV, SDO data output valid after PIC18F6X2X/8X2X
TscL2doV SCK edge
PIC18LF6X2X/8X2X
Note 1: Requires the use of Parameter #73A.
2: Only if Parameter #71A and #72A are used.
2003 Microchip Technology Inc.
Advance Information
DS39612A-page 347
PIC18F6X2X/8X2X
FIGURE 27-15:
EXAMPLE SPI MASTER MODE TIMING (CKE = 1)
SS
81
SCK
(CKP = 0)
71
72
79
78
73
SCK
(CKP = 1)
80
bit 6 - - - - - -1
LSb
MSb
SDO
SDI
75, 76
bit 6 - - - -1
MSb In
74
LSb In
Note: Refer to Figure 27-4 for load conditions.
TABLE 27-16: EXAMPLE SPI MODE REQUIREMENTS (MASTER MODE, CKE = 1)
Param.
No.
Symbol
TscH
TscL
Characteristic
Min
Max Units Conditions
71
SCK input high time
Continuous
Single Byte
Continuous
Single Byte
1.25 TCY + 30
—
—
—
—
—
ns
(Slave mode)
71A
72
40
1.25 TCY + 30
40
ns (Note 1)
SCK input low time
(Slave mode)
ns
72A
73
ns (Note 1)
TdiV2scH, Setup time of SDI data input to SCK edge
TdiV2scL
100
ns
73A
74
TB2B
Last clock edge of Byte 1 to the 1st clock edge of 1.5 TCY + 40
Byte 2
—
—
ns (Note 2)
TscH2diL, Hold time of SDI data input to SCK edge
TscL2diL
100
ns
75
TdoR
SDO data output rise time PIC18F6X2X/8X2X
PIC18LF6X2X/8X2X
—
25
45
25
25
45
25
50
100
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
76
78
TdoF
TscR
SDO data output fall time
—
—
SCK output rise time
(Master mode)
PIC18F6X2X/8X2X
PIC18LF6X2X/8X2X
79
80
TscF
SCK output fall time (Master mode)
—
—
TscH2doV, SDO data output valid after PIC18F6X2X/8X2X
TscL2doV SCK edge
PIC18LF6X2X/8X2X
81
TdoV2scH, SDO data output setup to SCK edge
TdoV2scL
TCY
Note 1: Requires the use of Parameter #73A.
2: Only if Parameter #71A and #72A are used.
DS39612A-page 348
Advance Information
2003 Microchip Technology Inc.
PIC18F6X2X/8X2X
FIGURE 27-16:
EXAMPLE SPI SLAVE MODE TIMING (CKE = 0)
SS
70
SCK
(CKP = 0)
83
71
72
78
79
79
78
SCK
(CKP = 1)
80
bit 6 - - - - - -1
MSb
LSb
SDO
SDI
77
75, 76
MSb In
74
bit 6 - - - -1
LSb In
73
Note:
Refer to Figure 27-4 for load conditions.
TABLE 27-17: EXAMPLE SPI MODE REQUIREMENTS (SLAVE MODE TIMING, CKE = 0)
Param.
No.
Symbol
Characteristic
Min
Max Units Conditions
70
TssL2scH, SS ↓ to SCK ↓ or SCK ↑ input
TssL2scL
TCY
—
ns
71
TscH
SCK input high time
(Slave mode)
Continuous
Single Byte
Continuous
Single Byte
1.25 TCY + 30
—
—
—
—
—
ns
71A
72
40
1.25 TCY + 30
40
ns (Note 1)
TscL
SCK input low time
(Slave mode)
ns
72A
73
ns (Note 1)
TdiV2scH, Setup time of SDI data input to SCK edge
TdiV2scL
100
ns
73A
74
TB2B
Last clock edge of Byte 1 to the first clock edge of Byte 2
1.5 TCY + 40
100
—
—
ns (Note 2)
TscH2diL, Hold time of SDI data input to SCK edge
TscL2diL
ns
75
TdoR
SDO data output rise time
PIC18F6X2X/8X2X
PIC18F6X2X/8X2X
—
25
45
25
50
25
45
25
50
100
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
76
77
78
TdoF
SDO data output fall time
—
10
—
TssH2doZ SS ↑ to SDO output hi-impedance
TscR
SCK output rise time (Master mode) PIC18F6X2X/8X2X
PIC18F6X2X/8X2X
79
80
TscF
SCK output fall time (Master mode)
—
—
TscH2doV, SDO data output valid after SCK
TscL2doV edge
PIC18F6X2X/8X2X
PIC18F6X2X/8X2X
83
TscH2ssH, SS ↑ after SCK edge
TscL2ssH
1.5 TCY + 40
Note 1: Requires the use of Parameter #73A.
2: Only if Parameter #71A and #72A are used.
2003 Microchip Technology Inc.
Advance Information
DS39612A-page 349
PIC18F6X2X/8X2X
FIGURE 27-17:
EXAMPLE SPI SLAVE MODE TIMING (CKE = 1)
82
SS
70
SCK
83
(CKP = 0)
71
72
SCK
(CKP = 1)
80
MSb
bit 6 - - - - - -1
LSb
SDO
SDI
75, 76
77
MSb In
74
bit 6 - - - -1
LSb In
Note: Refer to Figure 27-4 for load conditions.
TABLE 27-18: EXAMPLE SPI SLAVE MODE REQUIREMENTS (CKE = 1)
Param.
No.
Symbol
Characteristic
Min
Max Units Conditions
70
TssL2scH, SS ↓ to SCK ↓ or SCK ↑ input
TssL2scL
TCY
—
ns
71
TscH
TscL
TB2B
SCK input high time
(Slave mode)
Continuous
Single Byte
Continuous
Single Byte
1.25 TCY + 30
—
—
—
—
—
—
ns
71A
72
40
1.25 TCY + 30
40
ns (Note 1)
ns
SCK input low time
(Slave mode)
72A
73A
74
ns (Note 1)
ns (Note 2)
ns
Last clock edge of Byte 1 to the first clock edge of Byte 2 1.5 TCY + 40
TscH2diL, Hold time of SDI data input to SCK edge
TscL2diL
100
75
TdoR
SDO data output rise time
PIC18F6X2X/8X2X
PIC18LF6X2X/8X2X
—
25
45
25
50
25
45
25
50
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
76
77
78
TdoF
SDO data output fall time
—
TssH2doZ SS ↑ to SDO output hi-impedance
TscR
10
SCK output rise time
(Master mode)
PIC18F6X2X/8X2X
—
PIC18LF6X2X/8X2X
—
79
80
TscF
SCK output fall time (Master mode)
—
TscH2doV, SDO data output valid after SCK PIC18F6X2X/8X2X
TscL2doV edge
—
PIC18LF6X2X/8X2X
—
100
50
82
83
TssL2doV SDO data output valid after SS PIC18F6X2X/8X2X
—
—
↓ edge
PIC18LF6X2X/8X2X
100
—
TscH2ssH, SS ↑ after SCK edge
TscL2ssH
1.5 TCY + 40
Note 1: Requires the use of Parameter #73A.
2: Only if Parameter #71A and #72A are used.
DS39612A-page 350
Advance Information
2003 Microchip Technology Inc.
PIC18F6X2X/8X2X
FIGURE 27-18:
I2C BUS START/STOP BITS TIMING
SCL
SDA
91
93
90
92
STOP
Condition
START
Condition
Note: Refer to Figure 27-4 for load conditions.
TABLE 27-19: I2C BUS START/STOP BITS REQUIREMENTS (SLAVE MODE)
Param.
Symbol
Characteristic
Min
Max
Units
Conditions
No.
90
TSU:STA START condition
Setup time
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
4700
600
—
—
—
—
—
—
—
—
ns
Only relevant for Repeated
START condition
91
92
93
THD:STA START condition
Hold time
4000
600
ns
ns
ns
After this period, the first
clock pulse is generated
TSU:STO STOP condition
Setup time
4700
600
THD:STO STOP condition
Hold time
4000
600
FIGURE 27-19:
I2C BUS DATA TIMING
103
102
100
101
SCL
90
106
107
91
92
SDA
In
110
109
109
SDA
Out
Note: Refer to Figure 27-4 for load conditions.
2003 Microchip Technology Inc.
Advance Information
DS39612A-page 351
PIC18F6X2X/8X2X
TABLE 27-20: I2C BUS DATA REQUIREMENTS (SLAVE MODE)
Param.
Symbol
Characteristic
Min
Max Units
Conditions
No.
100
THIGH
Clock high time
100 kHz mode
4.0
—
µs
PIC18F6X2X/8X2X must
operate at a minimum of
1.5 MHz
400 kHz mode
0.6
—
µs
PIC18F6X2X/8X2X must
operate at a minimum of
10 MHz
SSP Module
1.5 TCY
4.7
—
—
101
TLOW
Clock low time
100 kHz mode
µs
µs
PIC18F6X2X/8X2X must
operate at a minimum of
1.5 MHz
400 kHz mode
SSP Module
1.3
—
PIC18F6X2X/8X2X must
operate at a minimum of
10 MHz
1.5 TCY
—
—
102
103
TR
TF
SDA and SCL rise 100 kHz mode
time
1000
ns
ns
400 kHz mode
20 + 0.1 CB 300
CB is specified to be from
10 to 400 pF
SDA and SCL fall 100 kHz mode
time
—
300
ns
ns
400 kHz mode
20 + 0.1 CB 300
CB is specified to be from
10 to 400 pF
90
TSU:STA
THD:STA
START condition
setup time
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
4.7
0.6
4.0
0.6
0
—
—
µs
µs
µs
µs
ns
µs
ns
ns
µs
µs
ns
ns
µs
µs
Only relevant for Repeated
START condition
91
START condition
hold time
—
After this period, the first
clock pulse is generated
—
106
107
92
THD:DAT Data input hold
time
—
0
0.9
—
TSU:DAT
TSU:STO
TAA
Data input setup
time
250
100
4.7
0.6
—
(Note 2)
—
STOP condition
setup time
—
—
109
110
Output valid from
clock
3500
—
(Note 1)
—
TBUF
Bus free time
4.7
1.3
—
Time the bus must be free
before a new transmission
can start
—
D102
CB
Bus capacitive loading
—
400
pF
Note 1: As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region
(min. 300 ns) of the falling edge of SCL to avoid unintended generation of START or STOP conditions.
2: A fast mode I2C bus device can be used in a standard mode I2C bus system but the requirement
TSU:DAT ≥ 250 ns must then be met. This will automatically be the case if the device does not stretch the
low period of the SCL signal. If such a device does stretch the low period of the SCL signal, it must output
the next data bit to the SDA line.
TR max. + TSU:DAT = 1000 + 250 = 1250 ns (according to the standard mode I2C bus specification) before
the SCL line is released.
DS39612A-page 352
Advance Information
2003 Microchip Technology Inc.
PIC18F6X2X/8X2X
FIGURE 27-20:
MASTER SSP I2C BUS START/STOP BITS TIMING WAVEFORMS
SCL
SDA
93
91
90
92
STOP
Condition
START
Condition
Note: Refer to Figure 27-4 for load conditions.
TABLE 27-21: MASTER SSP I2C BUS START/STOP BITS REQUIREMENTS
Param.
Symbol
Characteristic
Min
Max Units
Conditions
No.
90
TSU:STA START condition
Setup time
100 kHz mode
400 kHz mode
1 MHz mode(1) 2(TOSC)(BRG + 1)
2(TOSC)(BRG + 1)
2(TOSC)(BRG + 1)
—
—
—
—
—
—
—
—
—
—
—
—
ns Only relevant for
Repeated START
condition
91
92
93
THD:STA START condition
Hold time
100 kHz mode
400 kHz mode
1 MHz mode(1) 2(TOSC)(BRG + 1)
2(TOSC)(BRG + 1)
ns After this period, the
first clock pulse is
generated
2(TOSC)(BRG + 1)
TSU:STO STOP condition
Setup time
100 kHz mode
400 kHz mode
1 MHz mode(1) 2(TOSC)(BRG + 1)
2(TOSC)(BRG + 1)
ns
2(TOSC)(BRG + 1)
THD:STO STOP condition
Hold time
100 kHz mode
400 kHz mode
2(TOSC)(BRG + 1)
ns
2(TOSC)(BRG + 1)
1 MHz mode(1) 2(TOSC)(BRG + 1)
Note 1: Maximum pin capacitance = 10 pF for all I2C pins.
FIGURE 27-21:
MASTER SSP I2C BUS DATA TIMING
103
102
100
101
SCL
90
106
91
92
107
SDA
In
110
109
109
SDA
Out
Note: Refer to Figure 27-4 for load conditions.
2003 Microchip Technology Inc.
Advance Information
DS39612A-page 353
PIC18F6X2X/8X2X
TABLE 27-22: MASTER SSP I2C BUS DATA REQUIREMENTS
Param.
Symbol
Characteristic
Min
Max Units
Conditions
No.
100
THIGH
Clock high time 100 kHz mode
400 kHz mode
2(TOSC)(BRG + 1)
2(TOSC)(BRG + 1)
—
—
ms
ms
ms
ms
ms
ms
ns
1 MHz mode(1) 2(TOSC)(BRG + 1)
—
101
102
103
90
TLOW
TR
Clock low time
100 kHz mode
400 kHz mode
2(TOSC)(BRG + 1)
2(TOSC)(BRG + 1)
—
—
1 MHz mode(1) 2(TOSC)(BRG + 1)
—
SDA and SCL
rise time
100 kHz mode
400 kHz mode
1 MHz mode(1)
100 kHz mode
400 kHz mode
1 MHz mode(1)
—
1000
300
300
300
300
100
—
CB is specified to be from
10 to 400 pF
20 + 0.1 CB
ns
—
—
ns
TF
SDA and SCL
fall time
ns
CB is specified to be from
10 to 400 pF
20 + 0.1 CB
—
ns
ns
TSU:STA START condition 100 kHz mode
2(TOSC)(BRG + 1)
2(TOSC)(BRG + 1)
ms Only relevant for
setup time
Repeated START
400 kHz mode
—
ms
condition
ms
1 MHz mode(1) 2(TOSC)(BRG + 1)
—
91
THD:STA START condition 100 kHz mode
2(TOSC)(BRG + 1)
2(TOSC)(BRG + 1)
—
ms After this period, the first
hold time
clock pulse is generated
400 kHz mode
—
ms
1 MHz mode(1) 2(TOSC)(BRG + 1)
—
ms
ns
106
107
92
THD:DAT Data input
hold time
100 kHz mode
400 kHz mode
1 MHz mode(1)
100 kHz mode
400 kHz mode
1 MHz mode(1)
0
—
0
0.9
—
ms
ns
TBD
250
TSU:DAT Data input
setup time
—
ns
ns
(Note 2)
100
—
TBD
—
ns
TSU:STO STOP condition 100 kHz mode
2(TOSC)(BRG + 1)
2(TOSC)(BRG + 1)
1 MHz mode(1) 2(TOSC)(BRG + 1)
—
ms
ms
ms
ns
setup time
400 kHz mode
—
—
109
110
D102
TAA
TBUF
CB
Output validfrom 100 kHz mode
clock
—
—
3500
1000
—
400 kHz mode
1 MHz mode(1)
100 kHz mode
400 kHz mode
1 MHz mode(1)
ns
—
ns
Bus free time
4.7
1.3
TBD
—
—
ms Time the bus must be free
before a new transmission
can start
ms
—
ms
—
Bus capacitive loading
400
pF
Note 1: Maximum pin capacitance = 10 pF for all I2C pins.
2: A fast mode I2C bus device can be used in a standard mode I2C bus system but parameter #107 ≥ 250 ns
must then be met. This will automatically be the case if the device does not stretch the low period of the SCL
signal. If such a device does stretch the low period of the SCL signal, it must output the next data bit to the
SDA line, parameter #102.+ parameter #107 = 1000 + 250 = 1250 ns (for 100 kHz mode), before the SCL
line is released.
DS39612A-page 354
Advance Information
2003 Microchip Technology Inc.
PIC18F6X2X/8X2X
FIGURE 27-22:
USART SYNCHRONOUS TRANSMISSION (MASTER/SLAVE) TIMING
RC6/TX1/CK1
pin
121
121
RC7/RX1/DT1
pin
120
Note: Refer to Figure 27-4 for load conditions.
122
TABLE 27-23: USART SYNCHRONOUS TRANSMISSION REQUIREMENTS
Param.
Symbol
Characteristic
Min
Max Units Conditions
No.
120
TckH2dtV SYNC XMIT (MASTER & SLAVE)
Clock high to data out valid
PIC18F6X2X/8X2X
PIC18LF6X2X/8X2X
PIC18F6X2X/8X2X
PIC18LF6X2X/8X2X
PIC18F6X2X/8X2X
PIC18LF6X2X/8X2X
—
—
—
—
—
—
40
100
20
ns
ns
ns
ns
ns
ns
121
122
Tckrf
Tdtrf
Clock out rise time and fall time
(Master mode)
50
Data out rise time and fall time
20
50
FIGURE 27-23:
USART SYNCHRONOUS RECEIVE (MASTER/SLAVE) TIMING
RC6/TX1/CK1
pin
125
RC7/RX1/DT1
pin
126
Note: Refer to Figure 27-4 for load conditions.
TABLE 27-24: USART SYNCHRONOUS RECEIVE REQUIREMENTS
Param.
Symbol
Characteristic
Min
Max
Units
Conditions
No.
125
TdtV2ckl SYNC RCV (MASTER & SLAVE)
Data hold before CK ↓ (DT hold time)
Data hold after CK ↓ (DT hold time)
10
15
—
—
ns
ns
126
TckL2dtl
2003 Microchip Technology Inc.
Advance Information
DS39612A-page 355
PIC18F6X2X/8X2X
TABLE 27-25: A/D CONVERTER CHARACTERISTICS: PIC18F6X2X/8X2X (INDUSTRIAL, EXTENDED)
PIC18LF6X2X/8X2X (INDUSTRIAL)
Param
No.
Symbol
Characteristic
Resolution
Min
Typ
Max
Units
Conditions
A01
NR
—
—
—
—
10
TBD
bit VREF = VDD ≥ 3.0V
bit VREF = VDD < 3.0V
A03
A04
A05
A06
EIL
Integral linearity error
Differential linearity error
Full scale error
—
—
—
—
<±1
TBD
LSb VREF = VDD ≥ 3.0V
LSb VREF = VDD < 3.0V
EDL
EFS
EOFF
—
—
—
—
<±1
TBD
LSb VREF = VDD ≥ 3.0V
LSb VREF = VDD < 3.0V
—
—
—
—
<±1
TBD
LSb VREF = VDD ≥ 3.0V
LSb VREF = VDD < 3.0V
Offset error
—
—
—
—
<±1
TBD
LSb VREF = VDD ≥ 3.0V
LSb VREF = VDD < 3.0V
A10
A20
A20A
A21
A22
A25
A30
—
Monotonicity
guaranteed(3)
—
V
VSS ≤ VAIN ≤ VREF
VREF
Reference voltage
(VREFH – VREFL)
0V
3V
—
—
—
—
V
For 10-bit resolution
VREFH Reference voltage High
VREFL Reference voltage Low
AVSS
—
—
—
—
AVDD + 0.3V
AVDD
V
AVSS – 0.3V
AVSS – 0.3V
—
V
VAIN
ZAIN
Analog input voltage
VREF + 0.3V
10.0
V
Recommended impedance of
analog voltage source
kΩ
A40
A50
IAD
A/D conversion PIC18F6X2X/8X2X
—
—
180
90
—
—
µA Average current
current (VDD)
consumption when
PIC18LF6X2X/8X2X
µA
A/D is on (Note 1)
IREF
VREF input current (Note 2)
10
—
1000
µA During VAIN acquisition.
Based on differential of
VHOLD to VAIN. To
charge CHOLD, see
Section 20.0.
—
—
10
µA During A/D conversion
cycle.
Note 1: When A/D is off, it will not consume any current other than minor leakage current. The power-down current
spec includes any such leakage from the A/D module.
VREF current is from RA2/AN2/VREF- and RA3/AN3/VREF+ pins or AVDD and AVSS pins, whichever is selected
as reference input.
2: Vss ≤ VAIN ≤ VREF
3: The A/D conversion result never decreases with an increase in the input voltage, and has no missing codes.
DS39612A-page 356
Advance Information
2003 Microchip Technology Inc.
PIC18F6X2X/8X2X
FIGURE 27-24:
A/D CONVERSION TIMING
BSF ADCON0, GO
(Note 2)
131
130
Q4
132
A/D CLK
. . .
. . .
9
8
7
2
1
0
A/D DATA
ADRES
NEW_DATA
TCY
OLD_DATA
ADIF
GO
DONE
SAMPLING STOPPED
SAMPLE
Note 1: If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts.
This allows the SLEEPinstruction to be executed.
2: This is a minimal RC delay (typically 100 ns) which also disconnects the holding capacitor from the analog input.
TABLE 27-26: A/D CONVERSION REQUIREMENTS
Param.
Symbol
Characteristic
Min
Max
Units
Conditions
No.
130
TAD
A/D clock period
PIC18F6X2X/8X2X
1.6
20(5)
20(5)
6.0
µs TOSC based, VREF ≥ 3.0V
µs TOSC based, VREF full range
µs A/D RC mode
PIC18LF6X2X/8X2X 3.0
PIC18F6X2X/8X2X 2.0
PIC18LF6X2X/8X2X 3.0
9.0
µs A/D RC mode
131
132
TCNV
TACQ
Conversion time (not including acquisition
time) (Note 1)
11
12
TAD
Acquisition time (Note 3)
15
10
—
—
µs -40°C ≤ Temp ≤ 125°C
µs 0°C ≤ Temp ≤ 125°C
135
136
TSWC
TAMP
Switching time from convert → sample
Amplifier settling time (Note 2)
—
1
(Note 4)
—
µs This may be used if the
“new” input voltage has not
changed by more than 1 LSb
(i.e., 5 mV @ 5.12V) from the
last sampled voltage (as
stated on CHOLD).
Note 1: ADRES register may be read on the following TCY cycle.
2: See Section 20.0 for minimum conditions when input voltage has changed more than 1 LSb.
3: The time for the holding capacitor to acquire the “New” input voltage when the voltage changes full scale
after the conversion (AVDD to AVSS, or AVSS to AVDD). The source impedance (RS) on the input channels is
50Ω.
4: On the next Q4 cycle of the device clock.
5: The time of the A/D clock period is dependent on the device frequency and the TAD clock divider.
2003 Microchip Technology Inc.
Advance Information
DS39612A-page 357
PIC18F6X2X/8X2X
NOTES:
DS39612A-page 358
Advance Information
2003 Microchip Technology Inc.
PIC18F6X2X/8X2X
28.0 DC AND AC
CHARACTERISTICS GRAPHS
AND TABLES
Graphs are not available at this time.
2003 Microchip Technology Inc.
Advance Information
DS39612A-page 359
PIC18F6X2X/8X2X
NOTES:
DS39612A-page 360
Advance Information
2003 Microchip Technology Inc.
PIC18F6X2X/8X2X
29.0 PACKAGING INFORMATION
29.1 Package Marking Information
Example
64-Lead TQFP
PIC18F6621-I/PT
0343017
XXXXXXXXXX
XXXXXXXXXX
XXXXXXXXXX
YYWWNNN
Example
80-Lead TQFP
XXXXXXXXXXXX
XXXXXXXXXXXX
YYWWNNN
PIC18F8621-E/PT
0342017
Legend: XX...X Customer specific information*
Y
Year code (last digit of calendar year)
YY
WW
NNN
Year code (last 2 digits of calendar year)
Week code (week of January 1 is week ‘01’)
Alphanumeric traceability code
Note: In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line thus limiting the number of available characters
for customer specific information.
*
Standard PICmicro device marking consists of Microchip part number, year code, week code, and
traceability code. For PICmicro device marking beyond this, certain price adders apply. Please check
with your Microchip Sales Office. For QTP devices, any special marking adders are included in QTP
price.
2003 Microchip Technology Inc.
Advance Information
DS39612A-page 361
PIC18F6X2X/8X2X
29.2 Package Details
The following sections give the technical details of the
packages.
64-Lead Plastic Thin Quad Flatpack (PT) 10x10x1 mm Body, 1.0/0.10 mm Lead Form (TQFP)
E
E1
#leads=n1
p
D1
D
2
1
B
n
°
CH x 45
α
A
c
A2
L
φ
β
A1
(F)
Units
INCHES
NOM
MILLIMETERS*
Dimension Limits
MIN
MAX
MIN
NOM
64
MAX
n
p
Number of Pins
Pitch
64
.020
16
0.50
16
Pins per Side
Overall Height
n1
A
.039
.043
.039
.006
.024
.039
3.5
.047
1.00
0.95
1.10
1.00
0.15
0.60
1.00
3.5
1.20
Molded Package Thickness
Standoff
A2
A1
L
(F)
φ
.037
.002
.018
.041
.010
.030
1.05
0.25
0.75
§
0.05
0.45
Foot Length
Footprint (Reference)
Foot Angle
0
.463
.463
.390
.390
.005
.007
.025
5
7
.482
.482
.398
.398
.009
.011
.045
15
0
11.75
11.75
9.90
9.90
0.13
0.17
0.64
5
7
12.25
12.25
10.10
10.10
0.23
0.27
1.14
15
Overall Width
E
D
.472
.472
.394
.394
.007
.009
.035
10
12.00
12.00
10.00
10.00
0.18
0.22
0.89
10
Overall Length
Molded Package Width
Molded Package Length
Lead Thickness
E1
D1
c
Lead Width
B
CH
α
Pin 1 Corner Chamfer
Mold Draft Angle Top
Mold Draft Angle Bottom
β
5
10
15
5
10
15
* Controlling Parameter
§ Significant Characteristic
Notes:
Dimensions D1 and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.010” (0.254mm) per side.
JEDEC Equivalent: MS-026
Drawing No. C04-085
DS39612A-page 362
Advance Information
2003 Microchip Technology Inc.
PIC18F6X2X/8X2X
80-Lead Plastic Thin Quad Flatpack (PT) 12x12x1 mm Body, 1.0/0.10 mm Lead Form (TQFP)
E
E1
#leads=n1
p
D1
D
2
B
c
1
n
°
CH x 45
A
α
A2
φ
β
L
A1
(F)
Units
INCHES
NOM
MILLIMETERS*
Dimension Limits
MIN
MAX
MIN
NOM
80
MAX
n
p
Number of Pins
Pitch
80
.020
20
0.50
20
Pins per Side
Overall Height
n1
A
.039
.037
.002
.018
.043
.039
.004
.024
.039
3.5
.047
1.00
0.95
1.10
1.00
0.10
0.60
1.00
3.5
1.20
Molded Package Thickness
Standoff
A2
A1
L
(F)
φ
.041
.006
.030
1.05
0.15
0.75
§
0.05
0.45
Foot Length
Footprint (Reference)
Foot Angle
0
.541
.541
.463
.463
.004
.007
.025
5
7
.561
.561
.482
.482
.008
.011
.045
15
0
13.75
13.75
11.75
11.75
0.09
0.17
0.64
5
7
14.25
14.25
12.25
12.25
0.20
0.27
1.14
15
Overall Width
E
D
.551
.551
.472
.472
.006
.009
.035
10
14.00
14.00
12.00
12.00
0.15
0.22
0.89
10
Overall Length
Molded Package Width
Molded Package Length
Lead Thickness
E1
D1
c
Lead Width
B
CH
α
Pin 1 Corner Chamfer
Mold Draft Angle Top
Mold Draft Angle Bottom
β
5
10
15
5
10
15
* Controlling Parameter
§ Significant Characteristic
Notes:
Dimensions D1 and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.010” (0.254mm) per side.
JEDEC Equivalent: MS-026
Drawing No. C04-092
2003 Microchip Technology Inc.
Advance Information
DS39612A-page 363
PIC18F6X2X/8X2X
NOTES:
DS39612A-page 364
Advance Information
2003 Microchip Technology Inc.
PIC18F6X2X/8X2X
APPENDIX A: REVISION HISTORY
APPENDIX B: DEVICE
DIFFERENCES
Revision A (July 2003)
The differences between the devices listed in this data
sheet are shown in Table B-1.
Original data sheet for PIC18F6X2X/8X2X family.
TABLE B-1:
DEVICE DIFFERENCES
Feature
PIC18F6525
PIC18F6621
PIC18F8525
PIC18F8621
On-chip Program Memory (Kbytes)
I/O Ports
48K
64K
48K
64K
Ports A, B, C, D,
E, F, G
Ports A, B, C, D,
E, F, G
Ports A, B, C, D,
E, F, G, H, J
Ports A, B, C, D,
E, F, G, H, J
A/D Channels
12
No
12
No
16
Yes
16
Yes
External Memory Interface
Package Types
64-pin TQFP
64-pin TQFP
80-pin TQFP
80-pin TQFP
2003 Microchip Technology Inc.
Advance Information
DS39612A-page 365
PIC18F6X2X/8X2X
APPENDIX C: CONVERSION
CONSIDERATIONS
APPENDIX D: MIGRATION FROM
MID-RANGE TO
ENHANCED DEVICES
This appendix discusses the considerations for con-
verting from previous versions of a device to the ones
listed in this data sheet. Typically, these changes are
due to the differences in the process technology used.
An example of this type of conversion is from a
PIC17C756 to a PIC18F8720.
A detailed discussion of the differences between the
mid-range MCU devices (i.e., PIC16CXXX) and the
enhanced devices (i.e., PIC18FXXX) is provided in
AN716, “Migrating Designs from PIC16C74A/74B to
PIC18C442.” The changes discussed, while device
specific, are generally applicable to all mid-range to
enhanced device migrations.
Not Applicable
This Application Note is available as Literature Number
DS00716.
DS39612A-page 366
Advance Information
2003 Microchip Technology Inc.
PIC18F6X2X/8X2X
APPENDIX E: MIGRATION FROM
HIGH-END TO
ENHANCED DEVICES
A detailed discussion of the migration pathway and dif-
ferences between the high-end MCU devices (i.e.,
PIC17CXXX) and the enhanced devices (i.e.,
PIC18FXXXX) is provided in AN726, “PIC17CXXX to
PIC18CXXX Migration.” This Application Note is
available as Literature Number DS00726.
2003 Microchip Technology Inc.
Advance Information
DS39612A-page 367
PIC18F6X2X/8X2X
NOTES:
DS39612A-page 368
Advance Information
2003 Microchip Technology Inc.
PIC18F6X2X/8X2X
INDEX
Comparator Analog Input Model .............................. 247
Comparator I/O Operating Modes ........................... 244
Comparator Output .................................................. 246
Comparator Voltage Reference ............................... 250
Compare Mode Operation ....................................... 154
Enhanced PWM ....................................................... 163
Low Voltage Detect (LVD) ....................................... 254
Low Voltage Detect with External Input ................... 254
MCLR/VPP/RG5 Pin ................................................. 123
A
A/D ................................................................................... 235
A/D Converter Interrupt, Configuring ....................... 239
Acquisition Requirements ........................................ 240
Acquisition Time ....................................................... 240
ADCON0 Register .................................................... 235
ADCON1 Register .................................................... 235
ADCON2 Register .................................................... 235
ADRESH Register ............................................ 235, 238
ADRESL Register ............................................ 235, 238
Analog Port Pins ...................................................... 130
Analog Port Pins, Configuring .................................. 241
Associated Register Summary ................................. 242
Calculating Minimum Required Acquisition Time
(Example) ......................................................... 240
Configuring the Module ............................................ 239
Conversion Clock (TAD) ........................................... 241
Conversion Status (GO/DONE Bit) .......................... 238
Conversion TAD Cycles ............................................ 242
Conversions ............................................................. 241
Converter Characteristics ........................................ 356
ECCP2 Special Event Trigger .................................. 241
Equations ................................................................. 240
Minimum Charging Time .......................................... 240
Special Event Trigger (ECCP) ................................. 162
TAD vs. Device Operating Frequencies (Table) ....... 241
Absolute Maximum Ratings ............................................. 325
AC (Timing) Characteristics ............................................. 337
Load Conditions for Device Timing
Specifications ................................................... 338
Parameter Symbology ............................................. 337
Temperature and Voltage Specifications ................. 338
Timing Conditions .................................................... 338
ACKSTAT Status Flag ..................................................... 205
ADCON0 Register ............................................................ 235
GO/DONE Bit ........................................................... 238
ADCON1 Register ............................................................ 235
ADCON2 Register ............................................................ 235
ADDLW ............................................................................ 283
ADDWF ............................................................................ 283
ADDWFC ......................................................................... 284
ADRESH Register .................................................... 235, 238
ADRESL Register .................................................... 235, 238
Analog-to-Digital Converter. See A/D.
2
MSSP (I C Master Mode) ........................................ 199
2
MSSP (I C Mode) .................................................... 184
MSSP (SPI Mode) ................................................... 175
On-Chip Reset Circuit ................................................ 31
PIC18F6525/6621 ....................................................... 9
PIC18F8525/8621 ..................................................... 10
PLL ............................................................................ 23
PORT/LAT/TRIS Operation ..................................... 105
PORTC (Peripheral Output Override) ...................... 111
PORTD and PORTE (Parallel Slave Port) ............... 130
PORTD in I/O Port Mode ......................................... 113
PORTD in System Bus Mode .................................. 114
PORTE in I/O Mode ................................................. 117
PORTE in System Bus Mode .................................. 117
PORTG (Peripheral Output Override) ...................... 122
PORTJ in I/O Mode ................................................. 127
PWM Operation (Simplified) .................................... 156
RA3:RA0 and RA5 Pins ........................................... 106
RA4/T0CKI Pin ........................................................ 106
RA6 Pin (as I/O) ....................................................... 106
RB2:RB0 Pins .......................................................... 109
RB3 Pin ................................................................... 109
RB7:RB4 Pins .......................................................... 108
Reads from FLASH Program Memory ....................... 67
RF1/AN6/C2OUT and RF2/AN7/C1OUT Pins ......... 119
RF6:RF3 and RF0 Pins ........................................... 120
RF7 Pin .................................................................... 120
RH3:RH0 Pins in I/O Mode ...................................... 124
RH3:RH0 Pins in System Bus Mode ....................... 125
RH7:RH4 Pins in I/O Mode ...................................... 124
RJ4:RJ0 Pins in System Bus Mode ......................... 128
RJ7:RJ6 Pins in System Bus Mode ......................... 128
Single Comparator ................................................... 245
Table Read Operation ............................................... 63
Table Write Operation ................................................ 64
Table Writes to FLASH Program Memory ................. 69
Timer0 in 16-bit Mode .............................................. 134
Timer0 in 8-bit Mode ................................................ 134
Timer1 ..................................................................... 138
Timer1 (16-bit R/W Mode) ....................................... 138
Timer2 ..................................................................... 144
Timer3 ..................................................................... 146
Timer3 (16-bit R/W Mode) ....................................... 146
Timer4 ..................................................................... 150
USART Receive ....................................................... 225
USART Transmit ...................................................... 223
Voltage Reference Output Buffer Example .............. 251
Watchdog Timer ...................................................... 270
BN .................................................................................... 286
BNC ................................................................................. 287
BNN ................................................................................. 287
BNOV ............................................................................... 288
BNZ .................................................................................. 288
BOR. See Brown-out Reset.
ANDLW ............................................................................ 284
ANDWF ............................................................................ 285
Assembler
MPASM Assembler .................................................. 319
Auto Wake-up on Sync Break Character ......................... 227
B
Baud Rate Generator ....................................................... 201
BC .................................................................................... 285
BCF .................................................................................. 286
BF Status Flag ................................................................. 205
Block Diagrams
16-bit Byte Select Mode ............................................. 77
16-bit Byte Write Mode .............................................. 75
16-bit Word Write Mode ............................................. 76
A/D ........................................................................... 238
Analog Input Model .................................................. 239
Baud Rate Generator ............................................... 201
Capture Mode Operation ......................................... 153
2003 Microchip Technology Inc.
Advance Information
DS39612A-page 369
PIC18F6X2X/8X2X
BOV ..................................................................................291
BRA ..................................................................................289
Break Character (12-bit) Transmit and Receive ...............228
BRG. See Baud Rate Generator.
Brown-out Reset (BOR) ............................................. 32, 259
BSF ..................................................................................289
BTFSC .............................................................................290
BTFSS ..............................................................................290
BTG ..................................................................................291
BZ .....................................................................................292
Code Protection ........................................................259, 273
COMF .............................................................................. 294
Comparator ...................................................................... 243
Analog Input Connection Considerations ................ 247
Associated Registers ............................................... 248
Configuration ........................................................... 244
Effects of RESET ..................................................... 247
Interrupts .................................................................. 246
Operation ................................................................. 245
Operation During SLEEP ......................................... 247
Outputs .................................................................... 245
Reference ................................................................ 245
External Signal ................................................ 245
C
C Compilers
MPLAB C17 .............................................................320
MPLAB C18 .............................................................320
MPLAB C30 .............................................................320
CALL ................................................................................292
Capture (CCP Module) .....................................................153
Associated Registers ...............................................155
CCP Pin Configuration .............................................153
CCPR1H:CCPR1L Registers ...................................153
Software Interrupt .....................................................153
Timer1/Timer3 Mode Selection ................................153
Capture (ECCP Module) ..................................................162
Capture/Compare/PWM (CCP) ........................................151
Capture Mode. See Capture.
Internal Signal .................................................. 245
Response Time ........................................................ 245
Comparator Specifications ............................................... 334
Comparator Voltage Reference ....................................... 249
Accuracy and Error .................................................. 250
Associated Registers ............................................... 251
Configuring .............................................................. 249
Connection Considerations ...................................... 250
Effects of RESET ..................................................... 250
Operation During SLEEP ......................................... 250
Compare (CCP Module) .................................................. 154
Associated Registers ............................................... 155
CCP Pin Configuration ............................................. 154
CCPR1 Register ...................................................... 154
Software Interrupt .................................................... 154
Special Event Trigger .............................................. 154
Timer1/Timer3 Mode Selection ................................ 154
Compare (ECCP Module) ................................................ 162
Special Event Trigger ...............................139, 147, 162
Configuration Bits ............................................................ 259
Context Saving During Interrupts ..................................... 104
Control Registers
CCP Mode and Timer Resources ............................152
CCPRxH Register ....................................................152
CCPRxL Register .....................................................152
Compare Mode. See Compare.
Interconnect Configurations .....................................152
Module Configuration ...............................................152
PWM Mode. See PWM.
Clocking Scheme/Instruction Cycle ....................................46
CLRF ................................................................................293
CLRWDT ..........................................................................293
Code Examples
EECON1 and EECON2 ............................................. 64
TABLAT (Table Latch) Register ................................. 66
TBLPTR (Table Pointer) Register .............................. 66
Conversion Considerations .............................................. 366
CPFSEQ .......................................................................... 294
CPFSGT .......................................................................... 295
CPFSLT ........................................................................... 295
16 x 16 Signed Multiply Routine .................................88
16 x 16 Unsigned Multiply Routine .............................88
8 x 8 Signed Multiply Routine .....................................87
8 x 8 Unsigned Multiply Routine .................................87
Changing Between Capture Prescalers ...................153
Data EEPROM Read .................................................83
Data EEPROM Refresh Routine ................................84
Data EEPROM Write ..................................................83
Erasing a FLASH Program Memory Row ..................68
Fast Register Stack ....................................................46
How to Clear RAM (Bank 1) Using
D
Data EEPROM Memory
Associated Registers ................................................. 85
EEADR Register ........................................................ 81
EEADRH Register ..................................................... 81
EECON1 Register ...................................................... 81
EECON2 Register ...................................................... 81
Operation During Code Protect ................................. 84
Protection Against Spurious Write ............................. 84
Reading ..................................................................... 83
Using .......................................................................... 84
Write Verify ................................................................ 84
Writing ........................................................................ 83
Data Memory ..................................................................... 49
General Purpose Registers ....................................... 49
Map for PIC18F6X2X/8X2X Devices ......................... 50
Special Function Registers ........................................ 49
DAW ................................................................................ 296
DC Characteristics ........................................................... 332
Power-down and Supply Current ............................. 328
Supply Voltage ......................................................... 327
DCFSNZ .......................................................................... 297
Indirect Addressing ............................................58
Implementing a Real-Time Clock Using a
Timer1 Interrupt Service ..................................140
Initializing PORTA ....................................................105
Initializing PORTB ....................................................108
Initializing PORTC ....................................................111
Initializing PORTD ....................................................113
Initializing PORTE ....................................................116
Initializing PORTF ....................................................119
Initializing PORTG ....................................................122
Initializing PORTH ....................................................124
Initializing PORTJ .....................................................127
Loading the SSPBUF (SSPSR) Register .................178
Reading a FLASH Program Memory Word ................67
Saving STATUS, WREG and
BSR Registers in RAM .....................................104
Writing to FLASH Program Memory ..................... 70–71
DS39612A-page 370
Advance Information
2003 Microchip Technology Inc.
PIC18F6X2X/8X2X
DECF ............................................................................... 296
DECFSZ ........................................................................... 297
Demonstration Boards
G
General Call Address Support ......................................... 198
GOTO .............................................................................. 298
PICDEM 1 ................................................................ 322
PICDEM 17 .............................................................. 322
PICDEM 18R PIC18C601/801 ................................. 323
PICDEM 2 Plus ........................................................ 322
PICDEM 3 PIC16C92X ............................................ 322
PICDEM 4 ................................................................ 322
PICDEM LIN PIC16C43X ........................................ 323
PICDEM USB PIC16C7X5 ....................................... 323
PICDEM.net Internet/Ethernet ................................. 322
Development Support ...................................................... 319
Device Differences ........................................................... 365
Direct Addressing ............................................................... 59
Direct Addressing ....................................................... 57
H
Hardware Multiplier ............................................................ 87
Introduction ................................................................ 87
Operation ................................................................... 87
Performance Comparison .......................................... 87
I
I/O Ports ........................................................................... 105
2
I C Mode
General Call Address Support ................................. 198
Master Mode
Operation ......................................................... 200
Master Mode Transmit Sequence ............................ 200
Read/Write Bit Information (R/W Bit) ................188, 189
Serial Clock (RC3/SCK/SCL) ................................... 189
ID Locations ..............................................................259, 276
INCF ................................................................................ 298
INCFSZ ............................................................................ 299
In-Circuit Debugger .......................................................... 276
Resources (Table) ................................................... 276
In-Circuit Serial Programming (ICSP) .......................259, 276
Indirect Addressing ............................................................ 59
INDF and FSR Registers ........................................... 58
Operation ................................................................... 58
Indirect Addressing Operation ........................................... 59
Indirect File Operand ......................................................... 49
INFSNZ ............................................................................ 299
Instruction Flow/Pipelining ................................................. 47
Instruction Format ............................................................ 279
Instruction Set .................................................................. 277
ADDLW .................................................................... 283
ADDWF .................................................................... 283
ADDWFC ................................................................. 284
ANDLW .................................................................... 284
ANDWF .................................................................... 285
BC ............................................................................ 285
BCF ......................................................................... 286
BN ............................................................................ 286
BNC ......................................................................... 287
BNN ......................................................................... 287
BNOV ...................................................................... 288
BNZ ......................................................................... 288
BOV ......................................................................... 291
BRA ......................................................................... 289
BSF .......................................................................... 289
BTFSC ..................................................................... 290
BTFSS ..................................................................... 290
BTG ......................................................................... 291
BZ ............................................................................ 292
CALL ........................................................................ 292
CLRF ....................................................................... 293
CLRWDT ................................................................. 293
COMF ...................................................................... 294
CPFSEQ .................................................................. 294
CPFSGT .................................................................. 295
CPFSLT ................................................................... 295
DAW ........................................................................ 296
DCFSNZ .................................................................. 297
DECF ....................................................................... 296
DECFSZ .................................................................. 297
GOTO ...................................................................... 298
E
ECCP
Capture and Compare Modes .................................. 162
Standard PWM Mode ............................................... 162
Electrical Characteristics .................................................. 325
Enhanced Capture/Compare/PWM (ECCP) .................... 159
and Program Memory modes .................................. 160
Capture Mode. See Capture (ECCP Module).
Outputs and Configuration ....................................... 160
Pin Configurations for ECCP1 ................................. 160
Pin Configurations for ECCP2 ................................. 161
Pin Configurations for ECCP3 ................................. 161
PWM Mode. See PWM (ECCP Module).
Timer Resources ...................................................... 162
Enhanced PWM Mode. See PWM (ECCP Module). ........ 162
Enhanced Universal Synchronous Asynchronous
Receiver Transmitter (USART) ................................ 215
Errata ................................................................................... 5
Evaluation and Programming Tools ................................. 323
Extended Microcontroller Mode ......................................... 73
External Memory Interface ................................................. 73
16-bit Byte Select Mode ............................................. 77
16-bit Byte Write Mode .............................................. 75
16-bit Mode ................................................................ 75
16-bit Mode Timing .................................................... 78
16-bit Word Write Mode ............................................. 76
PIC18F8X2X External Bus - I/O Port Functions ........ 74
Program Memory Modes and External
Memory Interface ............................................... 73
F
Firmware Instructions ....................................................... 277
FLASH Program Memory ................................................... 63
Associated Registers ................................................. 71
Control Registers ....................................................... 64
Erase Sequence ........................................................ 68
Erasing ....................................................................... 68
Operation During Code Protect .................................. 71
Reading ...................................................................... 67
Table Pointer
Boundaries Based on Operation ........................ 66
Table Pointer Boundaries .......................................... 66
Table Reads and Table Writes .................................. 63
Write Sequence ......................................................... 69
Writing To ................................................................... 69
Protection Against Spurious Writes ................... 71
Unexpected Termination .................................... 71
Write Verify ........................................................ 71
2003 Microchip Technology Inc.
Advance Information
DS39612A-page 371
PIC18F6X2X/8X2X
INCF .........................................................................298
INCFSZ ....................................................................299
INFSNZ ....................................................................299
IORLW .....................................................................300
IORWF .....................................................................300
LFSR ........................................................................301
MOVF .......................................................................301
MOVFF .....................................................................302
MOVLB .....................................................................302
MOVLW ....................................................................303
MOVWF ...................................................................303
MULLW ....................................................................304
MULWF ....................................................................304
NEGF .......................................................................305
NOP .........................................................................305
POP ..........................................................................306
PUSH .......................................................................306
RCALL ......................................................................307
RESET .....................................................................307
RETFIE ....................................................................308
RETLW .....................................................................308
RETURN ..................................................................309
RLCF ........................................................................309
RLNCF .....................................................................310
RRCF .......................................................................310
RRNCF .....................................................................311
SETF ........................................................................311
SLEEP ......................................................................312
SUBFWB ..................................................................312
SUBLW ....................................................................313
SUBWF ....................................................................313
SUBWFB ..................................................................314
SWAPF ....................................................................314
TBLRD .....................................................................315
TBLWT .....................................................................316
TSTFSZ ....................................................................317
XORLW ....................................................................317
XORWF ....................................................................318
Summary Table ........................................................280
INT Interrupt (RB3/INT3:RB0/INT0). See Interrupt Sources.
INTCON Registers .............................................................91
IORLW ............................................................................. 300
IORWF ............................................................................. 300
IPR Registers ................................................................... 100
K
Key Features
Easy Migration ............................................................. 7
Expanded Memory ....................................................... 7
External Memory Interface ........................................... 7
Other Special Features ................................................ 7
L
LFSR ................................................................................ 301
Low Voltage Detect .......................................................... 253
Characteristics ......................................................... 335
Converter Characteristics ........................................ 335
Effects of a RESET .................................................. 257
Operation ................................................................. 256
Current Consumption ....................................... 257
During SLEEP ................................................. 257
Reference Voltage Set Point ........................... 257
Typical Application ................................................... 253
Low Voltage ICSP Programming ..................................... 276
LVD. See Low Voltage Detect. ........................................ 253
M
Master SSP (MSSP) Module Overview ........................... 175
Master Synchronous Serial Port (MSSP). See MSSP.
Master Synchronous Serial Port. See MSSP.
Memory
Mode Memory Access ............................................... 42
Memory Maps for PIC18F6X2X/8X2X
Program Memory Modes ........................................... 43
Memory Organization
Data Memory ............................................................. 49
Program Memory ....................................................... 41
Modes ................................................................ 41
Memory Programming Requirements .............................. 336
Microcontroller Mode ......................................................... 73
Microprocessor Mode ........................................................ 73
Microprocessor with Boot Block Mode ............................... 73
Migration from High-End to Enhanced Devices ............... 367
Migration from Mid-Range to Enhanced Devices ............ 366
MOVF .............................................................................. 301
MOVFF ............................................................................ 302
MOVLB ............................................................................ 302
MOVLW ........................................................................... 303
MOVWF ........................................................................... 303
MPLAB ASM30 Assembler, Linker, Librarian .................. 320
MPLAB ICD 2 In-Circuit Debugger .................................. 321
MPLAB ICE 2000 High Performance Universal
In-Circuit Emulator ................................................... 321
MPLAB ICE 4000 High Performance Universal
In-Circuit Emulator ................................................... 321
MPLAB Integrated Development
Environment Software ............................................. 319
MPLINK Object Linker/MPLIB Object Librarian ............... 320
MSSP ............................................................................... 175
ACK Pulse ........................................................188, 189
Clock Stretching ....................................................... 194
10-bit Slave Receive Mode (SEN = 1) ............. 194
10-bit Slave Transmit Mode ............................. 194
7-bit Slave Receive Mode (SEN = 1) ............... 194
7-bit Slave Transmit Mode ............................... 194
2
Inter-Integrated Circuit. See I C.
Interrupt Sources ..............................................................259
A/D Conversion Complete ........................................239
Capture Complete (CCP) .........................................153
Compare Complete (CCP) .......................................154
INT0 .........................................................................104
Interrupt-on-Change (RB7:RB4) ..............................108
PORTB, Interrupt-on-Change ..................................104
RB3/INT3:RB0/INT0 Pins, External .........................104
TMR0 .......................................................................104
TMR0 Overflow ........................................................135
TMR1 Overflow ................................................ 137, 139
TMR2 to PR2 Match .................................................144
TMR2 to PR2 Match (PWM) .................... 143, 156, 162
TMR3 Overflow ................................................ 145, 147
TMR4 to PR4 Match .................................................150
TMR4 to PR4 Match (PWM) ....................................149
Interrupts ............................................................................89
Control Registers .......................................................91
Enable Registers ........................................................97
Flag Registers ............................................................94
Logic ...........................................................................90
Priority Registers ......................................................100
Reset Control Registers ...........................................103
DS39612A-page 372
Advance Information
2003 Microchip Technology Inc.
PIC18F6X2X/8X2X
Clock Synchronization and the CKP bit
Oscillator Selection .......................................................... 259
Oscillator, Timer1 ..............................................137, 139, 147
Oscillator, Timer3 ............................................................. 145
Oscillator, WDT ................................................................ 269
(SEN = 1) ......................................................... 195
Control Registers (general) ...................................... 175
Enabling SPI I/O ...................................................... 179
2
I C Mode .................................................................. 184
P
Acknowledge Sequence Timing ....................... 208
Baud Rate Generator ....................................... 201
Bus Collision
Packaging ........................................................................ 361
Details ...................................................................... 362
Marking .................................................................... 361
Parallel Slave Port (PSP) ..........................................113, 130
Associated Registers ............................................... 132
RE0/AD8/RD/P2D Pin ............................................. 130
RE1/AD9/WR/P2C Pin ............................................. 130
RE2/AD10/CS/P2B Pin ............................................ 130
Select (PSPMODE Bit) .....................................113, 130
Phase Locked Loop (PLL) ................................................. 23
PICkit 1 FLASH Starter Kit ............................................... 323
PICSTART Plus Development Programmer .................... 321
PIE Registers ..................................................................... 97
Pin Functions
During a Repeated
START Condition ..................... 212
Bus Collision During a START Condition ......... 210
Bus Collision During a STOP Condition ........... 213
Clock Arbitration ............................................... 202
Effect of a RESET ............................................ 209
2
I C Clock Rate w/BRG ..................................... 201
Master Mode .................................................... 199
Reception ................................................. 205
Repeated START Timing ......................... 204
Master Mode START Condition ....................... 203
Master Mode Transmission .............................. 205
Multi-Master Communication, Bus Collision
AVDD .......................................................................... 20
AVSS .......................................................................... 20
MCLR/VPP/RG5 ......................................................... 11
OSC1/CLKI ................................................................ 11
OSC2/CLKO/RA6 ...................................................... 11
RA0/AN0 .................................................................... 12
RA1/AN1 .................................................................... 12
RA2/AN2/VREF- ......................................................... 12
RA3/AN3/VREF+ ........................................................ 12
RA4/T0CKI ................................................................ 12
RA5/AN4/LVDIN ........................................................ 12
RA6 ............................................................................ 12
RB0/INT0 ................................................................... 13
RB1/INT1 ................................................................... 13
RB2/INT2 ................................................................... 13
RB3/INT3/CCP2/P2A ................................................. 13
RB4/KBI0 ................................................................... 13
RB5/KBI1/PGM .......................................................... 13
RB6/KBI2/PGC .......................................................... 13
RB7/KBI3/PGD .......................................................... 13
RC0/T1OSO/T13CKI ................................................. 14
RC1/T1OSI/CCP2/P2A .............................................. 14
RC2/CCP1/P1A ......................................................... 14
RC3/SCK/SCL ........................................................... 14
RC4/SDI/SDA ............................................................ 14
RC5/SDO ................................................................... 14
RC6/TX1/CK1 ............................................................ 14
RC7/RX1/DT1 ............................................................ 14
RD0/AD0/PSP0 ......................................................... 15
RD1/AD1/PSP1 ......................................................... 15
RD2/AD2/PSP2 ......................................................... 15
RD3/AD3/PSP3 ......................................................... 15
RD4/AD4/PSP4 ......................................................... 15
RD5/AD5/PSP5 ......................................................... 15
RD6/AD6/PSP6 ......................................................... 15
RD7/AD7/PSP7 ......................................................... 15
RE0/AD8/RD/P2D ...................................................... 16
RE1/AD9/WR/P2C ..................................................... 16
RE2/AD10/CS/P2B .................................................... 16
RE3/AD11/P3C .......................................................... 16
RE4/AD12/P3B .......................................................... 16
RE5/AD13/P1C .......................................................... 16
RE6/AD14/P1B .......................................................... 16
RE7/AD15/CCP2/P2A ............................................... 16
RF0/AN5 .................................................................... 17
RF1/AN6/C2OUT ....................................................... 17
and Arbitration ......................................... 209
Multi-Master Mode ........................................... 209
Registers .......................................................... 184
SLEEP Operation ............................................. 209
STOP Condition Timing ................................... 208
Module Operation .................................................... 188
Operation ................................................................. 178
Slave Mode .............................................................. 188
Addressing ....................................................... 188
Reception ......................................................... 189
Transmission .................................................... 189
SPI Master Mode ..................................................... 180
SPI Mode ................................................................. 175
SPI Slave Mode ....................................................... 181
SSPBUF ................................................................... 180
SSPSR ..................................................................... 180
Typical Connection .................................................. 179
MSSP Module
SPI Master/Slave Connection .................................. 179
MULLW ............................................................................ 304
MULWF ............................................................................ 304
N
NEGF ............................................................................... 305
NOP ................................................................................. 305
O
OPCODE Field Descriptions ............................................ 278
OPTION_REG Register
PSA Bit ..................................................................... 135
T0CS Bit ................................................................... 135
T0PS2:T0PS0 Bits ................................................... 135
T0SE Bit ................................................................... 135
Oscillator Configuration ...................................................... 21
EC .............................................................................. 21
ECIO .......................................................................... 21
ECIO+PLL .................................................................. 21
ECIO+SPLL ............................................................... 21
HS .............................................................................. 21
HS+PLL ...................................................................... 21
HS+SPLL ................................................................... 21
LP ............................................................................... 21
RC .............................................................................. 21
RCIO .......................................................................... 21
XT .............................................................................. 21
2003 Microchip Technology Inc.
Advance Information
DS39612A-page 373
PIC18F6X2X/8X2X
RF2/AN7/C1OUT .......................................................17
RF3/AN8 ....................................................................17
RF4/AN9 ....................................................................17
RF5/AN10/CVREF .......................................................17
RF6/AN11 ..................................................................17
RF7/SS .......................................................................17
RG0/CCP3/P3A .........................................................18
RG1/TX2/CK2 ............................................................18
RG2/RX2/DT2 ............................................................18
RG3/CCP4/P3D .........................................................18
RG4/CCP5/P1D .........................................................18
RH0/A16 .....................................................................19
RH1/A17 .....................................................................19
RH2/A18 .....................................................................19
RH3/A19 .....................................................................19
RH4/AN12/P3C ..........................................................19
RH5/AN13/P3B ..........................................................19
RH6/AN14/P1C ..........................................................19
RH7/AN15/P1B ..........................................................19
RJ0/ALE .....................................................................20
RJ1/OE .......................................................................20
RJ2/WRL ....................................................................20
RJ3/WRH ...................................................................20
RJ4/BA0 .....................................................................20
RJ5/CE .......................................................................20
RJ6/LB .......................................................................20
RJ7/UB .......................................................................20
VDD .............................................................................20
VSS .............................................................................20
Pinout I/O Descriptions ......................................................11
PIR Registers .....................................................................94
PLL Lock Time-out .............................................................32
Pointer, FSR .......................................................................58
POP ..................................................................................306
POR. See Power-on Reset.
PORTE
Analog Port Pins ...................................................... 130
Associated Registers ............................................... 118
Functions ................................................................. 118
LATE Register ......................................................... 116
PORTE Register ...................................................... 116
PSP Mode Select (PSPMODE Bit) ...................113, 130
RE0/AD8/RD/P2D Pin ............................................. 130
RE1/AD9/WR/P2C Pin ............................................. 130
RE2/AD10/CS/P2B Pin ............................................ 130
TRISE Register ........................................................ 116
PORTF
Associated Registers ............................................... 121
Functions ................................................................. 121
LATF Register .......................................................... 119
PORTF Register ...................................................... 119
TRISF Register ........................................................ 119
PORTG
Associated Registers ............................................... 123
Functions ................................................................. 123
LATG Register ......................................................... 122
PORTG Register ...................................................... 122
TRISG Register ....................................................... 122
PORTH
Associated Registers ............................................... 126
Functions ................................................................. 126
LATH Register ......................................................... 124
PORTH Register ...................................................... 124
TRISH Register ........................................................ 124
PORTJ
Associated Registers ............................................... 129
Functions ................................................................. 129
LATJ Register .......................................................... 127
PORTJ Register ....................................................... 127
TRISJ Register ........................................................ 127
PORTA
Postscaler, WDT
Associated Registers ...............................................107
Functions ..................................................................107
LATA Register ..........................................................105
PORTA Register ......................................................105
TRISA Register ........................................................105
PORTB
Associated Registers ...............................................110
Functions ..................................................................110
LATB Register ..........................................................108
PORTB Register ......................................................108
RB3/INT3:RB0/INT0 Pins, External .........................104
TRISB Register ........................................................108
PORTC
Associated Registers ...............................................112
Functions ..................................................................112
LATC Register ..........................................................111
PORTC Register ......................................................111
RC3/SCK/SCL Pin ...................................................189
TRISC Register ........................................................111
PORTD .............................................................................130
Associated Registers ...............................................115
Functions ..................................................................115
LATD Register ..........................................................113
Parallel Slave Port (PSP) Function ..........................113
PORTD Register ......................................................113
TRISD Register ........................................................113
Assignment (PSA Bit) .............................................. 135
Rate Select (T0PS2:T0PS0 Bits) ............................. 135
Switching Between Timer0 and WDT ...................... 135
Power-down Mode. See SLEEP.
Power-on Reset (POR) ...............................................32, 259
Oscillator Start-up Timer (OST) ..........................32, 259
Power-up Timer (PWRT) ....................................32, 259
Time-out Sequence ................................................... 32
Prescaler
Timer2 ...................................................................... 163
Prescaler, Capture ........................................................... 153
Prescaler, Timer0 ............................................................. 135
Assignment (PSA Bit) .............................................. 135
Rate Select (T0PS2:T0PS0 Bits) ............................. 135
Switching Between Timer0 and WDT ...................... 135
Prescaler, Timer2 ............................................................. 156
PRO MATE II Universal Device Programmer .................. 321
Product Identification System .......................................... 381
Program Counter
PCL, PCLATH and PCLATU Register ....................... 46
DS39612A-page 374
Advance Information
2003 Microchip Technology Inc.
PIC18F6X2X/8X2X
Program Memory
Extended Microcontroller Mode ................................. 41
CONFIG1H (Configuration 1 High) .......................... 261
CONFIG2H (Configuration 2 High) .......................... 262
CONFIG2L (Configuration 2 Low) ........................... 262
CONFIG3H (Configuration 3 High) .......................... 263
CONFIG3L (Configuration 3 Low) ......................43, 263
CONFIG4L (Configuration 4 Low) ........................... 264
CONFIG5H (Configuration 5 High) .......................... 265
CONFIG5L (Configuration 5 Low) ........................... 265
CONFIG6H (Configuration 6 High) .......................... 266
CONFIG6L (Configuration 6 Low) ........................... 266
CONFIG7H (Configuration 7 High) .......................... 267
CONFIG7L (Configuration 7 Low) ........................... 267
CVRCON (Comparator Voltage
Instructions ................................................................. 47
Two-Word .......................................................... 48
Interrupt Vector .......................................................... 41
Map and Stack for PIC18FX525 ................................ 42
Map and Stack for PIC18FX621 ................................ 42
Microcontroller Mode ................................................. 41
Microprocessor Mode ................................................ 41
Microprocessor with Boot Block Mode ....................... 41
RESET Vector ............................................................ 41
Program Verification ......................................................... 273
Program Verification and Code Protection
Associated Registers ............................................... 273
Configuration Register Protection ............................ 276
Data EEPROM Code Protection .............................. 276
Memory Code Protection ......................................... 274
Programming, Device Instructions ................................... 277
PSP. See Parallel Slave Port.
Reference Control) .......................................... 249
Device ID Register 1 ................................................ 268
Device ID Register 2 ................................................ 268
ECCPxAS (ECCP Auto Shutdown Control) ............. 171
ECCPxDEL (PWM Configuration) ........................... 170
EECON1 (Data EEPROM Control 1) ....................65, 82
INTCON (Interrupt Control) ........................................ 91
INTCON2 (Interrupt Control 2) ................................... 92
INTCON3 (Interrupt Control 3) ................................... 93
IPR1 (Peripheral Interrupt Priority 1) ....................... 100
IPR2 (Peripheral Interrupt Priority 2) ....................... 101
IPR3 (Peripheral Interrupt Priority 3) ....................... 102
LVDCON (LVD Control) ........................................... 255
MEMCON (Memory Control) ..................................... 73
OSCCON (Oscillator Configuration) .......................... 25
PIE1 (Peripheral Interrupt Enable 1) .......................... 97
PIE2 (Peripheral Interrupt Enable 2) .......................... 98
PIE3 (Peripheral Interrupt Enable 3) .......................... 99
PIR1 (Peripheral Interrupt Request 1) ....................... 94
PIR2 (Peripheral Interrupt Request 2) ....................... 95
PIR3 (Peripheral Interrupt Request 3) ....................... 96
PSPCON (Parallel Slave Port Control) .................... 131
RCON (RESET Control) ............................................ 61
RCON (Reset Control) ............................................. 103
RCSTAx (Receive Status and Control) .................... 217
Pulse Width Modulation. See PWM (CCP Module)
and PWM (ECCP Module).
PUSH ............................................................................... 306
PWM (CCP Module) ......................................................... 156
Associated Registers ............................................... 157
CCPR1H:CCPR1L Registers ................................... 162
CCPR4H:CCPR4L Registers ................................... 156
Duty Cycle ........................................................ 156, 163
Example Frequencies/Resolutions .................. 157, 163
Period ............................................................... 156, 162
Setup for PWM Operation ........................................ 157
TMR2 to PR2 Match .................................143, 156, 162
TMR4 to PR4 Match ................................................ 149
PWM (ECCP Module) ...................................................... 162
Associated Registers ............................................... 174
Direction Change in Full-Bridge Output Mode ......... 168
Effects of a RESET .................................................. 173
Enhanced PWM Auto Shutdown .............................. 170
Full-Bridge Application Example .............................. 168
Full-Bridge Mode ...................................................... 167
Half-Bridge Mode ..................................................... 165
Half-Bridge Output Mode Applications Example ...... 166
Output Configurations .............................................. 164
Output Relationships (Active High) .......................... 164
Output Relationships (Active Low) ........................... 165
Programmable Dead Band Delay ............................ 170
Setup for PWM Operation ........................................ 173
Start-up Considerations ........................................... 172
2
SSPCON1 (MSSP Control 1) in I C Mode .............. 186
SSPCON1 (MSSP Control 1) in SPI Mode .............. 177
2
SSPCON2 (MSSP Control 2) in I C Mode .............. 187
2
SSPSTAT (MSSP Status) in I C Mode .................... 185
SSPSTAT (MSSP Status) in SPI Mode ................... 176
STATUS .................................................................... 60
STKPTR (Stack Pointer) ............................................ 45
Summary ..............................................................53–56
T0CON (Timer0 Control) ......................................... 133
T1CON (Timer 1 Control) ........................................ 137
T2CON (Timer 2 Control) ........................................ 143
T3CON (Timer3 Control) ......................................... 145
T4CON (Timer 4 Control) ........................................ 149
TXSTAx (Transmit Status and Control) ................... 216
WDTCON (Watchdog Timer Control) ...................... 269
RESET ......................................................................259, 307
Reset ................................................................................. 31
MCLR Reset (normal operation) ................................ 31
MCLR Reset (SLEEP) ............................................... 31
Power-on Reset ......................................................... 31
Programmable Brown-out Reset (BOR) .................... 31
RESET Instruction ..................................................... 31
Stack Full Reset ......................................................... 31
Stack Underflow Reset .............................................. 31
Watchdog Timer (WDT) Reset .................................. 31
Q
Q Clock .................................................................... 156, 163
R
RAM. See Data Memory.
RC Oscillator ...................................................................... 22
RCALL .............................................................................. 307
RCON Registers .............................................................. 103
Register File ....................................................................... 49
Registers
ADCON0 (A/D Control 0) ......................................... 235
ADCON1 (A/D Control 1) ......................................... 236
ADCON2 (A/D Control 2) ......................................... 237
BAUDCONx (Baud Rate Control) ............................ 218
CCPxCON
(Capture/Compare/PWM Control) ............ 151, 159
CMCON (Comparator Control) ................................ 243
2003 Microchip Technology Inc.
Advance Information
DS39612A-page 375
PIC18F6X2X/8X2X
RETFIE ............................................................................308
RETLW .............................................................................308
RETURN ..........................................................................309
Revision History ...............................................................365
RLCF ................................................................................309
RLNCF .............................................................................310
RRCF ...............................................................................310
RRNCF .............................................................................311
Timer0 .............................................................................. 133
16-bit Mode Timer Reads and Writes ...................... 135
Associated Registers ............................................... 135
Clock Source Edge Select (T0SE Bit) ..................... 135
Clock Source Select (T0CS Bit) ............................... 135
Operation ................................................................. 135
Overflow Interrupt .................................................... 135
Prescaler. See Prescaler, Timer0.
Timer1 .............................................................................. 137
16-bit Read/Write Mode ........................................... 139
Associated Registers ............................................... 141
Operation ................................................................. 138
Oscillator ...........................................................137, 139
Overflow Interrupt .............................................137, 139
Special Event Trigger (ECCP) ..........................139, 162
TMR1H Register ...................................................... 137
TMR1L Register ....................................................... 137
Use as a Real-Time Clock ....................................... 140
Timer2 .............................................................................. 143
Associated Registers ............................................... 144
Operation ................................................................. 143
Postscaler. See Postscaler, Timer2.
S
SCK ..................................................................................175
SDI ...................................................................................175
SDO .................................................................................175
Serial Clock, SCK .............................................................175
Serial Data In (SDI) ..........................................................175
Serial Data Out (SDO) .....................................................175
Serial Peripheral Interface. See SPI Mode.
SETF ................................................................................311
Slave Select (SS) .............................................................175
Slave Select Synchronization ...........................................181
SLEEP .............................................................. 259, 271, 312
Software Simulator (MPLAB SIM) ....................................320
Software Simulator (MPLAB SIM30) ................................320
Special Event Trigger. See Compare (ECCP Mode).
Special Event Trigger. See Compare (ECCP Module).
Special Features of the CPU ............................................259
Configuration Registers .................................... 261–267
Special Function Registers ................................................49
Map ............................................................................51
SPI Mode
Associated Registers ...............................................183
Bus Mode Compatibility ...........................................183
Effects of a RESET ..................................................183
Master Mode ............................................................180
Master/Slave Connection .........................................179
Serial Clock ..............................................................175
Serial Data In ...........................................................175
Serial Data Out .........................................................175
Slave Mode ..............................................................181
Slave Select .............................................................175
Slave Select Synchronization ...................................181
SLEEP Operation .....................................................183
SPI Clock .................................................................180
SS ....................................................................................175
SSP
PR2 Register ............................................143, 156, 162
Prescaler. See Prescaler, Timer2.
SSP Clock Shift ................................................143, 144
TMR2 Register ......................................................... 143
TMR2 to PR2 Match Interrupt ...........143, 144, 156, 162
Timer3 .............................................................................. 145
Associated Registers ............................................... 147
Operation ................................................................. 146
Oscillator ...........................................................145, 147
Overflow Interrupt .............................................145, 147
Special Event Trigger (ECCP) ................................. 147
TMR3H Register ...................................................... 145
TMR3L Register ....................................................... 145
Timer4 .............................................................................. 149
Associated Registers ............................................... 150
Operation ................................................................. 149
Postscaler. See Postscaler, Timer4.
PR4 Register ........................................................... 149
Prescaler. See Prescaler, Timer4.
SSP Clock Shift ....................................................... 150
TMR4 Register ......................................................... 149
TMR4 to PR4 Match Interrupt ...........................149, 150
Timing Diagrams
TMR2 Output for Clock Shift ............................ 143, 144
TMR4 Output for Clock Shift ....................................150
SSPOV Status Flag ..........................................................205
SSPSTAT Register
R/W Bit ............................................................. 188, 189
STATUS Bits
A/D Conversion ........................................................ 357
Acknowledge Sequence .......................................... 208
Asynchronous Reception ......................................... 226
Asynchronous Transmission .................................... 224
Asynchronous Transmission (Back to Back) ........... 224
Auto Wake-up Bit (WUE) During
Significance and Initialization Condition for
Normal Operation ............................................ 227
Auto Wake-up Bit (WUE) During SLEEP ................. 227
Automatic Baud Rate Calculation ............................ 222
Baud Rate Generator with Clock Arbitration ............ 202
BRG Reset Due to SDA Arbitration During
START Condition ............................................. 211
Brown-out Reset (BOR) ........................................... 343
Bus Collision During a Repeated
START Condition (Case 1) .............................. 212
Bus Collision During a Repeated
START Condition (Case 2) .............................. 212
Bus Collision During a START Condition
RCON Register ..................................................33
SUBFWB ..........................................................................312
SUBLW ............................................................................313
SUBWF ............................................................................313
SUBWFB ..........................................................................314
SWAPF ............................................................................314
T
Table Pointer Operations (Table) .......................................66
TBLRD .............................................................................315
TBLWT .............................................................................316
Time-out in Various Situations ...........................................33
(SCL = 0) ......................................................... 211
DS39612A-page 376
Advance Information
2003 Microchip Technology Inc.
PIC18F6X2X/8X2X
Bus Collision During a STOP Condition
(Case 1) ........................................................... 213
Bus Collision During a STOP Condition
(Case 2) ........................................................... 213
Bus Collision During START Condition
(SDA only) ........................................................ 210
Bus Collision for Transmit and Acknowledge ........... 209
Capture/Compare/PWM (CCP) ................................ 345
CLKO and I/O .......................................................... 340
Clock Synchronization ............................................. 195
Clock/Instruction Cycle .............................................. 46
Example SPI Master Mode (CKE = 0) ..................... 347
Example SPI Master Mode (CKE = 1) ..................... 348
Example SPI Slave Mode (CKE = 0) ....................... 349
Example SPI Slave Mode (CKE = 1) ....................... 350
External Clock (All Modes except PLL) .................... 339
External Memory Bus Timing for SLEEP
SPI Mode Timing (Master Mode) ............................. 180
STOP Condition Receive or Transmit Mode ............ 208
Synchronous Reception (Master Mode, SREN) ...... 231
Synchronous Transmission ..................................... 229
Synchronous Transmission (Through TXEN) .......... 230
Time-out Sequence on POR w/PLL Enabled
(MCLR Tied to VDD via 1 kΩ Resistor) .............. 40
Time-out Sequence on Power-up
(MCLR Not Tied to VDD): Case 1 ...................... 39
Time-out Sequence on Power-up
(MCLR Not Tied to VDD): Case 2 ...................... 39
Time-out Sequence on Power-up (MCLR Tied
to VDD via 1 kΩ Resistor) .................................. 39
Timer0 and Timer1 External Clock .......................... 344
Timing for Transition Between Timer1 and
OSC1 (EC with PLL) .......................................... 27
Timing for Transition Between Timer1 and
(Microprocessor Mode) ...................................... 79
External Memory Bus Timing for TBLRD
OSC1 (HS with PLL) .......................................... 27
Transition Between Timer1 and OSC1
(Extended Microcontroller Mode) ....................... 78
External Memory Bus Timing for TBLRD
(HS, XT, LP) ...................................................... 26
Transition Between Timer1 and OSC1
(Microprocessor Mode) ...................................... 78
Full-Bridge PWM Output .......................................... 167
Half-Bridge Output ................................................... 165
(RC, EC) ............................................................ 28
Transition from OSC1 to Timer1 Oscillator ................ 26
USART Synchronous Receive (Master/Slave) ........ 355
USART Synchronous Transmission
2
I C Bus Data ............................................................ 351
2
I C Bus START/STOP Bits ...................................... 351
(Master/Slave) ................................................. 355
Wake-up from SLEEP via Interrupt .......................... 272
Timing Specifications ....................................................... 339
A/D Conversion Requirements ................................ 357
Capture/Compare/PWM Requirements ................... 345
CLKO and I/O Requirements ............................340, 341
Example SPI Mode Requirements
2
I C Master Mode (7 or 10-bit Transmission) ............ 206
2
I C Master Mode (7-bit Reception) .......................... 207
2
I C Master Mode First START Bit Timing ................ 203
2
I C Slave Mode (10-bit Reception, SEN = 0) ........... 192
2
I C Slave Mode (10-bit Reception, SEN = 1) ........... 197
2
I C Slave Mode (10-bit Transmission) ..................... 193
2
I C Slave Mode (7-bit Reception, SEN = 0) ............. 190
(Master Mode, CKE = 0) .................................. 347
Example SPI Mode Requirements
(Master Mode, CKE = 1) .................................. 348
Example SPI Mode Requirements
(Slave Mode CKE = 0) ..................................... 349
Example SPI Slave Mode Requirements
2
I C Slave Mode (7-bit Reception, SEN = 1) ............. 196
2
I C Slave Mode (7-bit Transmission) ....................... 191
Low Voltage Detect .................................................. 256
2
Master SSP I C Bus Data ........................................ 353
2
Master SSP I C Bus START/STOP Bits .................. 353
Parallel Slave Port (PSP) ......................................... 346
Parallel Slave Port (PSP) Read ............................... 132
Parallel Slave Port (PSP) Write ............................... 131
Program Memory Read ............................................ 341
Program Memory Write ............................................ 342
PWM Auto Shutdown (PRSEN = 0,
(CKE = 1) ......................................................... 350
External Clock Requirements .................................. 339
2
I C Bus Data Requirements (Slave Mode) .............. 352
2
I C Bus START/STOP Bits Requirements .............. 351
2
Master SSP I C Bus Data Requirements ................ 354
2
Master SSP I C Bus START/STOP Bits
Auto Restart Disabled) ..................................... 172
PWM Auto Shutdown (PRSEN = 1,
Auto Restart Enabled) ...................................... 172
PWM Direction Change ........................................... 169
PWM Direction Change at Near
100% Duty Cycle ............................................. 169
PWM Output ............................................................ 156
Repeat START Condition ........................................ 204
RESET, Watchdog Timer (WDT),
Requirements .................................................. 353
Parallel Slave Port Requirements ............................ 346
PLL Clock ................................................................ 339
Program Memory Write Requirements .................... 342
RESET, Watchdog Timer, Oscillator Start-up
Timer, Power-up Timer and
Brown-out Reset Requirements ...................... 343
Timer0 and Timer1 External Clock
Requirements .................................................. 344
USART Synchronous Receive Requirements ......... 355
USART Synchronous Transmission
Oscillator Start-up Timer (OST) and
Power-up Timer (PWRT) ................................. 343
Send Break Character Sequence ............................ 228
Slave Mode General Call Address Sequence
(7 or 10-bit Address Mode) .............................. 198
Slave Synchronization ............................................. 181
Slow Rise Time (MCLR Tied to VDD
Requirements .................................................. 355
TRISE Register
PSPMODE Bit ...................................................113, 130
TSTFSZ ........................................................................... 317
Two-Word Instructions
via 1 kΩ Resistor) ............................................... 40
SPI Mode (Slave Mode with CKE = 0) ..................... 182
SPI Mode (Slave Mode with CKE = 1) ..................... 182
Example Cases .......................................................... 48
TXSTAx Register
BRGH Bit ................................................................. 219
2003 Microchip Technology Inc.
Advance Information
DS39612A-page 377
PIC18F6X2X/8X2X
U
V
USART
Voltage Reference Specifications .................................... 334
Asynchronous Mode ................................................223
12-bit Break Transmit and Receive ..................228
Associated Registers, Receive ........................226
Associated Registers, Transmit .......................224
Auto Wake-up on Sync Break ..........................227
Receiver ...........................................................225
Setting up 9-bit Mode with Address Detect ......225
Transmitter .......................................................223
Baud Rate Generator (BRG) ....................................219
Associated Registers .......................................219
Auto Baud Rate Detect ....................................222
Baud Rate Error, Calculating ...........................219
Baud Rates, Asynchronous Modes ..................220
High Baud Rate Select (BRGH Bit) ..................219
Sampling ..........................................................219
Synchronous Master Mode ......................................229
Associated Registers, Reception .....................231
Associated Registers, Transmit .......................230
Reception .........................................................231
Transmission ....................................................229
Synchronous Slave Mode ........................................232
Associated Registers, Receive ........................233
Associated Registers, Transmit .......................232
Reception .........................................................233
Transmission ....................................................232
W
Wake-up from SLEEP ...............................................259, 271
Using Interrupts ....................................................... 271
Watchdog Timer (WDT) ............................................259, 269
Associated Registers ............................................... 270
Control Register ....................................................... 269
Postscaler ................................................................ 270
Programming Considerations .............................64, 269
RC Oscillator ............................................................ 269
Time-out Period ....................................................... 269
WCOL .............................................................................. 203
WCOL Status Flag ....................................203, 204, 205, 208
WDT ................................................................................. 269
WWW, On-Line Support ...................................................... 5
X
XORLW ............................................................................ 317
XORWF ........................................................................... 318
DS39612A-page 378
Advance Information
2003 Microchip Technology Inc.
PIC18F6X2X/8X2X
ON-LINE SUPPORT
SYSTEMS INFORMATION AND
UPGRADE HOT LINE
Microchip provides on-line support on the Microchip
World Wide Web site.
The Systems Information and Upgrade Line provides
system users a listing of the latest versions of all of
Microchip's development systems software products.
Plus, this line provides information on how customers
can receive the most current upgrade kits. The Hot Line
Numbers are:
The web site is used by Microchip as a means to make
files and information easily available to customers. To
view the site, the user must have access to the Internet
and a web browser, such as Netscape® or Microsoft®
Internet Explorer. Files are also available for FTP
download from our FTP site.
1-800-755-2345 for U.S. and most of Canada, and
1-480-792-7302 for the rest of the world.
Connecting to the Microchip Internet
Web Site
042003
The Microchip web site is available at the following
URL:
www.microchip.com
The file transfer site is available by using an FTP ser-
vice to connect to:
ftp://ftp.microchip.com
The web site and file transfer site provide a variety of
services. Users may download files for the latest
Development Tools, Data Sheets, Application Notes,
User's Guides, Articles and Sample Programs. A vari-
ety of Microchip specific business information is also
available, including listings of Microchip sales offices,
distributors and factory representatives. Other data
available for consideration is:
• Latest Microchip Press Releases
• Technical Support Section with Frequently Asked
Questions
• Design Tips
• Device Errata
• Job Postings
• Microchip Consultant Program Member Listing
• Links to other useful web sites related to
Microchip Products
• Conferences for products, Development Systems,
technical information and more
• Listing of seminars and events
2003 Microchip Technology Inc.
Advance Information
DS39612A-page 379
PIC18F6X2X/8X2X
READER RESPONSE
It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip prod-
uct. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation
can better serve you, please FAX your comments to the Technical Publications Manager at (480) 792-4150.
Please list the following information, and use this outline to provide us with your comments about this document.
To:
Technical Publications Manager
Reader Response
Total Pages Sent ________
RE:
From:
Name
Company
Address
City / State / ZIP / Country
Telephone: (_______) _________ - _________
FAX: (______) _________ - _________
Application (optional):
Would you like a reply?
Y
N
PIC18F6X2X/8X2X
DS39612A
Literature Number:
Device:
Questions:
1. What are the best features of this document?
2. How does this document meet your hardware and software development needs?
3. Do you find the organization of this document easy to follow? If not, why?
4. What additions to the document do you think would enhance the structure and subject?
5. What deletions from the document could be made without affecting the overall usefulness?
6. Is there any incorrect or misleading information (what and where)?
7. How would you improve this document?
DS39612A-page 380
Advance Information
2003 Microchip Technology Inc.
PIC18F6X2X/8X2X
PIC18F6X2X/8X2X PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
X
/XX
XXX
PART NO.
Device
−
Examples:
Temperature Package
Range
Pattern
a) PIC18LF6621 - I/PT 301 = Industrial
temp., TQFP package, Extended VDD
limits, QTP pattern #301.
b) PIC18F8621 - E/PT = Extended temp.,
TQFP package, standard VDD limits.
(1)
(2)
Device
PIC18F6X2X/8X2X , PIC18F6X2X/8X2XT ;
VDD range 4.2V to 5.5V
(1)
(2)
PIC18LF6X2X/8X2X , PIC18LF6X2X/8X2XT
VDD range 2.0V to 5.5V
;
Temperature
Range
I
E
=
=
-40°C to +85°C (Industrial)
-40°C to +125°C (Extended)
Note 1: F
LF
2: T
=
=
Standard Voltage Range
Extended Voltage Range
Package
Pattern
PT
=
TQFP (Thin Quad Flatpack)
=
in tape and reel
QTP, SQTP, Code or Special Requirements
(blank otherwise)
2003 Microchip Technology Inc.
Advance Information
DS39612A-page 381
WORLDWIDE SALES AND SERVICE
Korea
AMERICAS
ASIA/PACIFIC
168-1, Youngbo Bldg. 3 Floor
Samsung-Dong, Kangnam-Ku
Seoul, Korea 135-882
Tel: 82-2-554-7200 Fax: 82-2-558-5932 or
82-2-558-5934
Corporate Office
Australia
2355 West Chandler Blvd.
Chandler, AZ 85224-6199
Tel: 480-792-7200
Suite 22, 41 Rawson Street
Epping 2121, NSW
Australia
Fax: 480-792-7277
Technical Support: 480-792-7627
Web Address: http://www.microchip.com
Tel: 61-2-9868-6733
Fax: 61-2-9868-6755
Singapore
200 Middle Road
#07-02 Prime Centre
Singapore, 188980
Tel: 65-6334-8870 Fax: 65-6334-8850
China - Beijing
Unit 915
Bei Hai Wan Tai Bldg.
No. 6 Chaoyangmen Beidajie
Beijing, 100027, No. China
Tel: 86-10-85282100
Fax: 86-10-85282104
Atlanta
3780 Mansell Road, Suite 130
Alpharetta, GA 30022
Tel: 770-640-0034
Fax: 770-640-0307
Taiwan
Kaohsiung Branch
30F - 1 No. 8
Min Chuan 2nd Road
Kaohsiung 806, Taiwan
Tel: 886-7-536-4818
Fax: 886-7-536-4803
Boston
China - Chengdu
2 Lan Drive, Suite 120
Westford, MA 01886
Tel: 978-692-3848
Fax: 978-692-3821
Rm. 2401-2402, 24th Floor,
Ming Xing Financial Tower
No. 88 TIDU Street
Chengdu 610016, China
Tel: 86-28-86766200
Taiwan
Taiwan Branch
11F-3, No. 207
Tung Hua North Road
Taipei, 105, Taiwan
Tel: 886-2-2717-7175 Fax: 886-2-2545-0139
Chicago
333 Pierce Road, Suite 180
Itasca, IL 60143
Tel: 630-285-0071
Fax: 630-285-0075
Fax: 86-28-86766599
China - Fuzhou
Unit 28F, World Trade Plaza
No. 71 Wusi Road
Dallas
Fuzhou 350001, China
Tel: 86-591-7503506
Fax: 86-591-7503521
EUROPE
Austria
Durisolstrasse 2
A-4600 Wels
Austria
Tel: 43-7242-2244-399
Fax: 43-7242-2244-393
Denmark
Regus Business Centre
Lautrup hoj 1-3
4570 Westgrove Drive, Suite 160
Addison, TX 75001
Tel: 972-818-7423
Fax: 972-818-2924
China - Hong Kong SAR
Unit 901-6, Tower 2, Metroplaza
223 Hing Fong Road
Kwai Fong, N.T., Hong Kong
Tel: 852-2401-1200
Fax: 852-2401-3431
Detroit
Tri-Atria Office Building
32255 Northwestern Highway, Suite 190
Farmington Hills, MI 48334
Tel: 248-538-2250
China - Shanghai
Room 701, Bldg. B
Far East International Plaza
No. 317 Xian Xia Road
Shanghai, 200051
Tel: 86-21-6275-5700
Fax: 86-21-6275-5060
China - Shenzhen
Rm. 1812, 18/F, Building A, United Plaza
No. 5022 Binhe Road, Futian District
Shenzhen 518033, China
Tel: 86-755-82901380
Fax: 86-755-8295-1393
China - Shunde
Fax: 248-538-2260
Ballerup DK-2750 Denmark
Tel: 45-4420-9895 Fax: 45-4420-9910
Kokomo
France
2767 S. Albright Road
Kokomo, IN 46902
Tel: 765-864-8360
Fax: 765-864-8387
Parc d’Activite du Moulin de Massy
43 Rue du Saule Trapu
Batiment A - ler Etage
91300 Massy, France
Tel: 33-1-69-53-63-20
Fax: 33-1-69-30-90-79
Los Angeles
18201 Von Karman, Suite 1090
Irvine, CA 92612
Tel: 949-263-1888
Fax: 949-263-1338
Germany
Steinheilstrasse 10
D-85737 Ismaning, Germany
Tel: 49-89-627-144-0
Fax: 49-89-627-144-44
Phoenix
2355 West Chandler Blvd.
Chandler, AZ 85224-6199
Tel: 480-792-7966
Fax: 480-792-4338
Room 401, Hongjian Building
No. 2 Fengxiangnan Road, Ronggui Town
Shunde City, Guangdong 528303, China
Tel: 86-765-8395507 Fax: 86-765-8395571
Italy
Via Quasimodo, 12
20025 Legnano (MI)
Milan, Italy
China - Qingdao
Rm. B505A, Fullhope Plaza,
No. 12 Hong Kong Central Rd.
Qingdao 266071, China
Tel: 86-532-5027355 Fax: 86-532-5027205
San Jose
Tel: 39-0331-742611
Fax: 39-0331-466781
Netherlands
P. A. De Biesbosch 14
NL-5152 SC Drunen, Netherlands
Tel: 31-416-690399
2107 North First Street, Suite 590
San Jose, CA 95131
Tel: 408-436-7950
Fax: 408-436-7955
India
Toronto
Divyasree Chambers
1 Floor, Wing A (A3/A4)
No. 11, O’Shaugnessey Road
Bangalore, 560 025, India
Tel: 91-80-2290061 Fax: 91-80-2290062
Japan
6285 Northam Drive, Suite 108
Mississauga, Ontario L4V 1X5, Canada
Tel: 905-673-0699
Fax: 31-416-690340
United Kingdom
505 Eskdale Road
Winnersh Triangle
Fax: 905-673-6509
Wokingham
Berkshire, England RG41 5TU
Tel: 44-118-921-5869
Fax: 44-118-921-5820
Benex S-1 6F
3-18-20, Shinyokohama
Kohoku-Ku, Yokohama-shi
Kanagawa, 222-0033, Japan
Tel: 81-45-471- 6166 Fax: 81-45-471-6122
07/28/03
DS39612A-page 382
Advance Information
2003 Microchip Technology Inc.
PIC18F6X2X/8X2X
Table of Contents
1.0 Device Overview .......................................................................................................................................................................... 7
2.0 Oscillator Configurations ............................................................................................................................................................ 21
3.0 Reset.......................................................................................................................................................................................... 31
4.0 Memory Organization................................................................................................................................................................. 41
5.0 FLASH Program Memory........................................................................................................................................................... 63
6.0 External Memory Interface ......................................................................................................................................................... 73
7.0 Data EEPROM Memory ............................................................................................................................................................. 81
8.0 8 X 8 Hardware Multiplier........................................................................................................................................................... 87
9.0 Interrupts .................................................................................................................................................................................... 89
10.0 I/O Ports ................................................................................................................................................................................... 105
11.0 Timer0 Module ......................................................................................................................................................................... 133
12.0 Timer1 Module ......................................................................................................................................................................... 137
13.0 Timer2 Module ......................................................................................................................................................................... 143
14.0 Timer3 Module ......................................................................................................................................................................... 145
15.0 Timer4 Module ......................................................................................................................................................................... 149
16.0 Capture/Compare/PWM (CCP) Modules ................................................................................................................................. 151
17.0 Enhanced Capture/Compare/PWM (ECCP) Module................................................................................................................ 159
18.0 Master Synchronous Serial Port (MSSP) Module .................................................................................................................... 175
19.0 Enhanced Universal Synchronous Asynchronous Receiver Transmitter (USART) ................................................................. 215
20.0 10-bit Analog-to-Digital Converter (A/D) Module...................................................................................................................... 235
21.0 Comparator Module.................................................................................................................................................................. 243
22.0 Comparator Voltage Reference Module................................................................................................................................... 249
23.0 Low Voltage Detect .................................................................................................................................................................. 253
24.0 Special Features of the CPU.................................................................................................................................................... 259
25.0 Instruction Set Summary.......................................................................................................................................................... 277
26.0 Development Support............................................................................................................................................................... 319
27.0 Electrical Characteristics.......................................................................................................................................................... 325
28.0 DC and AC Characteristics Graphs and Tables....................................................................................................................... 359
29.0 Packaging Information.............................................................................................................................................................. 361
Appendix A: Revision History............................................................................................................................................................. 365
Appendix B: Device Differences ........................................................................................................................................................ 365
Appendix C: Conversion Considerations ........................................................................................................................................... 366
Appendix D: Migration from Mid-range to Enhanced Devices ........................................................................................................... 366
Appendix E: Migration from High-end to Enhanced Devices ............................................................................................................. 367
INDEX................................................................................................................................................................................................ 369
On-Line Support................................................................................................................................................................................. 379
Systems Information and Upgrade Hot Line ...................................................................................................................................... 379
Reader Response.............................................................................................................................................................................. 380
PIC18F6X2X/8X2X Product Identification System............................................................................................................................. 381
2003 Microchip Technology Inc.
DS00000A-page 1-1
PIC18F6X2X/8X2X
DS00000A-page 1-2
2003 Microchip Technology Inc.
相关型号：
PIC18F8525-EPTSQTP
64/80-Pin High Performance, 64-Kbyte Enhanced FLASH Microcontrollers with A/D
MICROCHIP
PIC18F8525-I/PT
64/80-Pin High-Performance, 64-Kbyte Enhanced Flash Microcontrollers with A/D
MICROCHIP
PIC18F8525-I/PTQTP
64/80-Pin High-Performance, 64-Kbyte Enhanced Flash Microcontrollers with A/D
MICROCHIP
PIC18F8525-I/PTSQTP
64/80-Pin High-Performance, 64-Kbyte Enhanced Flash Microcontrollers with A/D
MICROCHIP
PIC18F8525-IPTQTP
64/80-Pin High Performance, 64-Kbyte Enhanced FLASH Microcontrollers with A/D
MICROCHIP
PIC18F8525-IPTSQTP
64/80-Pin High Performance, 64-Kbyte Enhanced FLASH Microcontrollers with A/D
MICROCHIP
PIC18F8525T-E/PT
64/80-Pin High-Performance, 64-Kbyte Enhanced Flash Microcontrollers with A/D
MICROCHIP
PIC18F8525T-E/PTQTP
64/80-Pin High-Performance, 64-Kbyte Enhanced Flash Microcontrollers with A/D
MICROCHIP
PIC18F8525T-E/PTSQTP
64/80-Pin High-Performance, 64-Kbyte Enhanced Flash Microcontrollers with A/D
MICROCHIP
PIC18F8525T-I/PT
64/80-Pin High-Performance, 64-Kbyte Enhanced Flash Microcontrollers with A/D
MICROCHIP
PIC18F8525T-I/PTQTP
64/80-Pin High-Performance, 64-Kbyte Enhanced Flash Microcontrollers with A/D
MICROCHIP
PIC18F8525T-I/PTSQTP
64/80-Pin High-Performance, 64-Kbyte Enhanced Flash Microcontrollers with A/D
MICROCHIP
©2020 ICPDF网 联系我们和版权申明