PIC18LF1320I/SOQTP [MICROCHIP]
18/20/28-Pin High-Performance, Enhanced Flash Microcontrollers;
| 型号： | PIC18LF1320I/SOQTP |
| 厂家： | 
MICROCHIP |
| 描述： | 18/20/28-Pin High-Performance, Enhanced Flash Microcontrollers 微控制器 |
| 文件： | 总308页 (文件大小：5130K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PIC18F1220/1320
Data Sheet
18/20/28-Pin High-Performance,
Enhanced Flash Microcontrollers
with 10-Bit A/D and nanoWatt Technology
© 2007 Microchip Technology Inc.
DS39605F
Note the following details of the code protection feature on Microchip devices:
•
Microchip products meet the specification contained in their particular Microchip Data Sheet.
•
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
•
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
•
•
Microchip is willing to work with the customer who is concerned about the integrity of their code.
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
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OTHERWISE, RELATED TO THE INFORMATION,
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
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Trademarks
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DS39605F-page ii
© 2007 Microchip Technology Inc.
PIC18F1220/1320
18/20/28-Pin High-Performance, Enhanced Flash MCUs
with 10-bit A/D and nanoWatt Technology
Low-Power Features:
Peripheral Highlights:
• Power Managed modes:
• High current sink/source 25 mA/25 mA
• Three external interrupts
- Run: CPU on, peripherals on
- Idle: CPU off, peripherals on
- Sleep: CPU off, peripherals off
• Power Consumption modes:
- PRI_RUN: 150 μA, 1 MHz, 2V
- PRI_IDLE: 37 μA, 1 MHz, 2V
- SEC_RUN: 14 μA, 32 kHz, 2V
- SEC_IDLE: 5.8 μA, 32 kHz, 2V
- RC_RUN: 110 μA, 1 MHz, 2V
- RC_IDLE: 52 μA, 1 MHz, 2V
- Sleep: 0.1 μA, 1 MHz, 2V
• Enhanced Capture/Compare/PWM (ECCP) module:
- One, two or four PWM outputs
- Selectable polarity
- Programmable dead time
- Auto-Shutdown and Auto-Restart
- Capture is 16-bit, max resolution 6.25 ns (TCY/16)
- Compare is 16-bit, max resolution 100 ns (TCY)
• Compatible 10-bit, up to 13-channel Analog-to-
Digital Converter module (A/D) with programmable
acquisition time
• Enhanced USART module:
- Supports RS-485, RS-232 and LIN 1.2
- Auto-Wake-up on Start bit
- Auto-Baud Detect
• Timer1 Oscillator: 1.1 μA, 32 kHz, 2V
• Watchdog Timer: 2.1 μA
• Two-Speed Oscillator Start-up
Oscillators:
Special Microcontroller Features:
• Four Crystal modes:
• 100,000 erase/write cycle Enhanced Flash
program memory typical
- LP, XT, HS: up to 25 MHz
- HSPLL: 4-10 MHz (16-40 MHz internal)
• 1,000,000 erase/write cycle Data EEPROM
memory typical
• Two External RC modes, up to 4 MHz
• Two External Clock modes, up to 40 MHz
• Flash/Data EEPROM Retention: > 40 years
• Self-programmable under software control
• Priority levels for interrupts
• Internal oscillator block:
- 8 user-selectable frequencies: 31 kHz, 125 kHz,
250 kHz, 500 kHz, 1 MHz, 2 MHz, 4 MHz, 8 MHz
• 8 x 8 Single-Cycle Hardware Multiplier
• Extended Watchdog Timer (WDT):
- Programmable period from 41 ms to 131s
- 2% stability over VDD and Temperature
- 125 kHz to 8 MHz calibrated to 1%
- Two modes select one or two I/O pins
- OSCTUNE – Allows user to shift frequency
• Secondary oscillator using Timer1 @ 32 kHz
• Fail-Safe Clock Monitor
• Single-supply 5V In-Circuit Serial Programming™
(ICSP™) via two pins
- Allows for safe shutdown if peripheral clock stops
• In-Circuit Debug (ICD) via two pins
• Wide operating voltage range: 2.0V to 5.5V
Program Memory
Data Memory
SRAM EEPROM
10-bit
A/D (ch)
ECCP
(PWM)
Timers
8/16-bit
Device
I/O
EUSART
Flash
# Single-Word
Instructions
(bytes)
(bytes)
(bytes)
PIC18F1220
PIC18F1320
4K
8K
2048
4096
256
256
256
256
16
16
7
7
1
1
Y
Y
1/3
1/3
© 2007 Microchip Technology Inc.
DS39605F-page 1
PIC18F1220/1320
Pin Diagrams
20-Pin SSOP
18-Pin PDIP, SOIC
RA0/AN0
1
2
3
4
5
6
7
8
20
19
18
17
16
15
14
13
RB3/CCP1/P1A
RA0/AN0
1
2
3
4
5
6
18
17
16
15
14
13
RB3/CCP1/P1A
RB2/P1B/INT2
RA1/AN1/LVDIN
RB2/P1B/INT2
OSC1/CLKI/RA7
OSC2/CLKO/RA6
VDD
RA1/AN1/LVDIN
RA4/T0CKI
RA4/T0CKI
OSC1/CLKI/RA7
OSC2/CLKO/RA6
VDD/AVDD
MCLR/VPP/RA5
MCLR/VPP/RA5
VSS
AVSS
VSS/AVSS
RA2/AN2/VREF-
RA3/AN3/VREF+
RB0/AN4/INT0
AVDD
RB7/PGD/T1OSI/
P1D/KBI3
RB7/PGD/T1OSI/
P1D/KBI3
RB6/PGC/T1OSO/
T13CKI/P1C/KBI2
RA2/AN2/VREF-
RB6/PGC/T1OSO/
T13CKI/P1C/KBI2
7
8
12
11
RA3/AN3/VREF+
RB5/PGM/KBI1
RB1/AN5/TX/
CK/INT1
RB4/AN6/RX/
DT/KBI0
RB5/PGM/KBI1
RB0/AN4/INT0
9
10
9
12
11
RB4/AN6/RX/
DT/KBI0
RB1/AN5/TX/
CK/INT1
10
28-Pin QFN
MCLR/VPP/RA5
21
20
19
18
17
16
15
1
2
3
OSC1/CLKI/RA7
OSC2/CLKO/RA6
NC
VSS
NC
VDD
NC
4
5
6
7
PIC18F1X20
AVDD
AVSS
NC
RB7/PGD/T1OSI/P1D/KBI3
RB6/PGC/T1OSO/T13CKI/P1C/KBI2
RA2/AN2/VREF-
DS39605F-page 2
© 2007 Microchip Technology Inc.
PIC18F1220/1320
Table of Contents
1.0 Device Overview .......................................................................................................................................................................... 5
2.0 Oscillator Configurations ............................................................................................................................................................ 11
3.0 Power Managed Modes ............................................................................................................................................................. 19
4.0 Reset.......................................................................................................................................................................................... 33
5.0 Memory Organization................................................................................................................................................................. 41
6.0 Flash Program Memory.............................................................................................................................................................. 57
7.0 Data EEPROM Memory ............................................................................................................................................................. 67
8.0 8 x 8 Hardware Multiplier............................................................................................................................................................ 71
9.0 Interrupts .................................................................................................................................................................................... 73
10.0 I/O Ports ..................................................................................................................................................................................... 87
11.0 Timer0 Module ........................................................................................................................................................................... 99
12.0 Timer1 Module ......................................................................................................................................................................... 103
13.0 Timer2 Module ......................................................................................................................................................................... 109
14.0 Timer3 Module ......................................................................................................................................................................... 111
15.0 Enhanced Capture/Compare/PWM (ECCP) Module................................................................................................................ 115
16.0 Enhanced Addressable Universal Synchronous Asynchronous Receiver Transmitter (EUSART).......................................... 131
17.0 10-Bit Analog-to-Digital Converter (A/D) Module ..................................................................................................................... 155
18.0 Low-Voltage Detect.................................................................................................................................................................. 165
19.0 Special Features of the CPU.................................................................................................................................................... 171
20.0 Instruction Set Summary.......................................................................................................................................................... 191
21.0 Development Support............................................................................................................................................................... 233
22.0 Electrical Characteristics.......................................................................................................................................................... 237
23.0 DC and AC Characteristics Graphs and Tables....................................................................................................................... 267
24.0 Packaging Information.............................................................................................................................................................. 285
Appendix A: Revision History............................................................................................................................................................. 291
Appendix B: Device Differences ........................................................................................................................................................ 291
Appendix C: Conversion Considerations ........................................................................................................................................... 292
Appendix D: Migration from Baseline to Enhanced Devices.............................................................................................................. 292
Appendix E: Migration from Mid-Range to Enhanced Devices.......................................................................................................... 293
Appendix F: Migration from High-End to Enhanced Devices............................................................................................................. 293
Index .................................................................................................................................................................................................. 295
The Microchip Web Site..................................................................................................................................................................... 303
Customer Change Notification Service .............................................................................................................................................. 303
Customer Support.............................................................................................................................................................................. 303
Reader Response.............................................................................................................................................................................. 304
PIC18F1220/1320 Product Identification System .............................................................................................................................. 305
© 2007 Microchip Technology Inc.
DS39605F-page 3
PIC18F1220/1320
TO OUR VALUED CUSTOMERS
It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip
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enhanced as new volumes and updates are introduced.
If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via
E-mail at docerrors@microchip.com or fax the Reader Response Form in the back of this data sheet to (480) 792-4150. We
welcome your feedback.
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DS39605F-page 4
© 2007 Microchip Technology Inc.
PIC18F1220/1320
Besides its availability as a clock source, the internal
oscillator block provides a stable reference source that
gives the family additional features for robust
operation:
1.0
DEVICE OVERVIEW
This document contains device specific information for
the following devices:
• Fail-Safe Clock Monitor: This option constantly
monitors the main clock source against a reference
signal provided by the internal oscillator. If a clock fail-
ure occurs, the controller is switched to the internal
oscillator block, allowing for continued low-speed
operation, or a safe application shutdown.
• PIC18F1220
• PIC18F1320
This family offers the advantages of all PIC18 microcon-
trollers – namely, high computational performance at an
economical price – with the addition of high endurance
Enhanced Flash program memory. On top of these fea-
tures, the PIC18F1220/1320 family introduces design
enhancements that make these microcontrollers a logical
choice for many high-performance, power sensitive
applications.
• Two-Speed Start-up: This option allows the internal
oscillator to serve as the clock source from Power-
on Reset, or wake-up from Sleep mode, until the
primary clock source is available. This allows for
code execution during what would otherwise be the
clock start-up interval and can even allow an appli-
cation to perform routine background activities and
return to Sleep without returning to full power
operation.
1.1
New Core Features
1.1.1
nanoWatt TECHNOLOGY
All of the devices in the PIC18F1220/1320 family incor-
porate a range of features that can significantly reduce
power consumption during operation. Key items include:
1.2
Other Special Features
• Alternate Run Modes: By clocking the controller
from the Timer1 source or the internal oscillator
block, power consumption during code execution
can be reduced by as much as 90%.
• Memory Endurance: The Enhanced Flash cells for
both program memory and data EEPROM are rated
to last for many thousands of erase/write cycles –
up to 100,000 for program memory and 1,000,000
for EEPROM. Data retention without refresh is
conservatively estimated to be greater than
40 years.
• Multiple Idle Modes: The controller can also run
with its CPU core disabled, but the peripherals are
still active. In these states, power consumption can
be reduced even further, to as little as 4% of normal
operation requirements.
• Self-programmability: These devices can write to
their own program memory spaces under internal
software control. By using a bootloader routine
located in the protected Boot Block at the top of pro-
gram memory, it becomes possible to create an
application that can update itself in the field.
• On-the-fly Mode Switching: The power managed
modes are invoked by user code during operation,
allowing the user to incorporate power-saving ideas
into their application’s software design.
• Enhanced CCP module: In PWM mode, this
module provides 1, 2 or 4 modulated outputs for
controlling half-bridge and full-bridge drivers. Other
features include auto-shutdown, for disabling PWM
outputs on interrupt or other select conditions and
auto-restart, to reactivate outputs once the condition
has cleared.
• Lower Consumption in Key Modules: The power
requirements for both Timer1 and the Watchdog
Timer have been reduced by up to 80%, with typical
values of 1.1 and 2.1 μA, respectively.
1.1.2
MULTIPLE OSCILLATOR OPTIONS
AND FEATURES
• Enhanced USART: This serial communication
module features automatic wake-up on Start bit and
automatic baud rate detection and supports RS-232,
RS-485 and LIN 1.2 protocols, making it ideally
suited for use in Local Interconnect Network (LIN)
bus applications.
All of the devices in the PIC18F1220/1320 family offer
nine different oscillator options, allowing users a wide
range of choices in developing application hardware.
These include:
• Four Crystal modes, using crystals or ceramic
resonators.
• 10-bit A/D Converter: This module incorporates
programmable acquisition time, allowing for a
channel to be selected and a conversion to be
initiated without waiting for a sampling period and
thus, reduce code overhead.
• Two External Clock modes, offering the option of
using two pins (oscillator input and a divide-by-4
clock output), or one pin (oscillator input, with the
second pin reassigned as general I/O).
• Two External RC Oscillator modes, with the same
pin options as the External Clock modes.
• Extended Watchdog Timer (WDT): This enhanced
version incorporates a 16-bit prescaler, allowing a
time-out range from 4 ms to over 2 minutes that is
stable across operating voltage and temperature.
• An internal oscillator block, which provides an
8 MHz clock (±2% accuracy) and an INTRC source
(approximately 31 kHz, stable over temperature and
VDD), as well as a range of 6 user-selectable clock
frequencies (from 125 kHz to 4 MHz) for a total of
8 clock frequencies.
© 2007 Microchip Technology Inc.
DS39605F-page 5
PIC18F1220/1320
A block diagram of the PIC18F1220/1320 device
architecture is provided in Figure 1-1. The pinouts for
this device family are listed in Table 1-2.
1.3
Details on Individual Family
Members
Devices in the PIC18F1220/1320 family are available
in 18-pin, 20-pin and 28-pin packages. A block diagram
for this device family is shown in Figure 1-1.
The devices are differentiated from each other only in
the amount of on-chip Flash program memory
(4 Kbytes for the PIC18F1220 device, 8 Kbytes for the
PIC18F1320 device). These and other features are
summarized in Table 1-1.
TABLE 1-1:
DEVICE FEATURES
Features
PIC18F1220
PIC18F1320
Operating Frequency
DC – 40 MHz
DC – 40 MHz
Program Memory (Bytes)
Program Memory (Instructions)
Data Memory (Bytes)
4096
8192
2048
4096
256
256
Data EEPROM Memory (Bytes)
Interrupt Sources
256
256
15
15
I/O Ports
Ports A, B
Ports A, B
Timers
4
4
Enhanced Capture/Compare/PWM Modules
Serial Communications
10-bit Analog-to-Digital Module
1
1
Enhanced USART
7 input channels
Enhanced USART
7 input channels
POR, BOR,
POR, BOR,
RESETInstruction, Stack Full,
Stack Underflow (PWRT, OST), Stack Underflow (PWRT, OST),
RESETInstruction, Stack Full,
Resets (and Delays)
MCLR (optional), WDT
MCLR (optional), WDT
Programmable Low-Voltage Detect
Programmable Brown-out Reset
Instruction Set
Yes
Yes
Yes
Yes
75 Instructions
75 Instructions
18-pin SDIP
18-pin SOIC
20-pin SSOP
28-pin QFN
18-pin SDIP
18-pin SOIC
20-pin SSOP
28-pin QFN
Packages
DS39605F-page 6
© 2007 Microchip Technology Inc.
PIC18F1220/1320
FIGURE 1-1:
PIC18F1220/1320 BLOCK DIAGRAM
Data Bus<8>
PORTA
Data Latch
Table Pointer <2>
inc/dec logic
21
8
8
8
8
RA0/AN0
Data RAM
21
RA1/AN1/LVDIN
RA2/AN2/VREF-
RA3/AN3/VREF+
21
Address Latch
20
PCLATU PCLATH
PCU PCH PCL
12(2)
Address Latch
Address<12>
Program Memory
(4 Kbytes)
Program Counter
4
BSR
12
FSR0
4
PIC18F1220
RA4/T0CKI
Bank0, F
(8 Kbytes)
PIC18F1320
MCLR/VPP/RA5(1)
FSR1
FSR2
31 Level Stack
Data Latch
16
12
OSC2/CLKO/RA6(2)
inc/dec
logic
OSC2/CLKI/RA7(2)
Decode
Table Latch
8
ROM Latch
PORTB
RB0/AN4/INT0
Instruction
Register
RB1/AN5/TX/CK/INT1
RB2/P1B/INT2
8
Instruction
Decode &
Control
PRODH PRODL
8 x 8 Multiply
RB3/CCP1/P1A
3
RB4/AN6/RX/DT/KBI0
RB5/PGM/KBI1
8
WREG
8
BIT OP
8
OSC1(2)
OSC2(2)
T1OSI
Power-up
Timer
8
Timing
Generation
RB6/PGC/T1OSO/
T13CKI/P1C/KBI2
Oscillator
Start-up Timer
8
INTRC
Oscillator
RB7/PGD/T1OSI/
P1D/KBI3
ALU<8>
Power-on
Reset
T1OSO
8
Watchdog
Timer
Precision
Voltage
Reference
Brown-out
Reset
Low-Voltage
Programming
MCLR(1)
VDD, VSS
Fail-Safe
Clock Monitor
In-Circuit
Debugger
Timer1
Timer2
Timer3
A/D Converter
Timer0
Enhanced
USART
Enhanced
CCP
Data EEPROM
Note 1: RA5 is available only when the MCLR Reset is disabled.
2: OSC1, OSC2, CLKI and CLKO are only available in select oscillator modes and when these pins are not being used as digital
I/O. Refer to Section 2.0 “Oscillator Configurations” for additional information.
© 2007 Microchip Technology Inc.
DS39605F-page 7
PIC18F1220/1320
TABLE 1-2:
PIC18F1220/1320 PINOUT I/O DESCRIPTIONS
Pin Number
Pin
Type
Buffer
Type
Pin Name
Description
PDIP/
SSOP QFN
SOIC
MCLR/VPP/RA5
MCLR
4
4
1
Master Clear (input) or programming voltage (input).
Master Clear (Reset) input. This pin is an active-low
Reset to the device.
I
ST
VPP
RA5
P
I
—
ST
Programming voltage input.
Digital input.
OSC1/CLKI/RA7
OSC1
16
18
21
Oscillator crystal or external clock input.
Oscillator crystal input or external clock source
input. ST buffer when configured in RC mode,
CMOS otherwise.
I
I
ST
CMOS
ST
CLKI
RA7
External clock source input. Always associated with
pin function OSC1. (See related OSC1/CLKI,
OSC2/CLKO pins.)
I/O
General purpose I/O pin.
OSC2/CLKO/RA6
OSC2
15
17
20
Oscillator crystal or clock output.
O
O
—
—
Oscillator crystal output. Connects to crystal or
resonator in Crystal Oscillator mode.
In RC, EC and INTRC modes, OSC2 pin outputs
CLKO, which has 1/4 the frequency of OSC1 and
denotes instruction cycle rate.
CLKO
RA6
I/O
ST
General purpose I/O pin.
PORTA is a bidirectional I/O port.
RA0/AN0
RA0
1
2
1
2
26
27
I/O
I
ST
Analog
Digital I/O.
Analog input 0.
AN0
RA1/AN1/LVDIN
RA1
I/O
ST
Digital I/O.
AN1
LVDIN
I
I
Analog
Analog
Analog input 1.
Low-Voltage Detect input.
RA2/AN2/VREF-
RA2
6
7
3
7
8
3
7
8
I/O
I
I
ST
Analog
Analog
Digital I/O.
Analog input 2.
A/D reference voltage (low) input.
AN2
VREF-
RA3/AN3/VREF+
RA3
I/O
I
I
ST
Analog
Analog
Digital I/O.
Analog input 3.
A/D reference voltage (high) input.
AN3
VREF+
RA4/T0CKI
RA4
28
I/O
I
ST/OD
ST
Digital I/O. Open-drain when configured as output.
Timer0 external clock input.
T0CKI
RA5
RA6
RA7
See the MCLR/VPP/RA5 pin.
See the OSC2/CLKO/RA6 pin.
See the OSC1/CLKI/RA7 pin.
Legend: TTL = TTL compatible input
CMOS = CMOS compatible input or output
ST
O
OD
=
=
=
Schmitt Trigger input with CMOS levels
Output
Open-drain (no P diode to VDD)
I
P
= Input
= Power
DS39605F-page 8
© 2007 Microchip Technology Inc.
PIC18F1220/1320
TABLE 1-2:
PIC18F1220/1320 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number
Pin
Type
Buffer
Type
Pin Name
Description
PDIP/
SSOP QFN
SOIC
PORTB is a bidirectional I/O port. PORTB can be software
programmed for internal weak pull-ups on all inputs.
RB0/AN4/INT0
RB0
8
9
9
I/O
I
I
TTL
Analog
ST
Digital I/O.
Analog input 4.
External interrupt 0.
AN4
INT0
RB1/AN5/TX/CK/INT1
9
10
10
RB1
AN5
TX
CK
INT1
I/O
I
O
I/O
I
TTL
Analog
—
ST
ST
Digital I/O.
Analog input 5.
EUSART asynchronous transmit.
EUSART synchronous clock (see related RX/DT).
External interrupt 1.
RB2/P1B/INT2
RB2
17
18
10
19
20
11
23
24
12
I/O
O
I
TTL
—
ST
Digital I/O.
Enhanced CCP1/PWM output.
External interrupt 2.
P1B
INT2
RB3/CCP1/P1A
RB3
I/O
I/O
O
TTL
ST
—
Digital I/O.
CCP1
P1A
Capture 1 input/Compare 1 output/PWM 1 output.
Enhanced CCP1/PWM output.
RB4/AN6/RX/DT/KBI0
RB4
AN6
RX
DT
KBI0
I/O
I
I
I/O
I
TTL
Analog
ST
ST
TTL
Digital I/O.
Analog input 6.
EUSART asynchronous receive.
EUSART synchronous data (see related TX/CK).
Interrupt-on-change pin.
RB5/PGM/KBI1
RB5
11
12
12
13
13
15
I/O
I/O
I
TTL
ST
TTL
Digital I/O.
PGM
KBI1
Low-Voltage ICSP Programming enable pin.
Interrupt-on-change pin.
RB6/PGC/T1OSO/
T13CKI/P1C/KBI2
RB6
I/O
I/O
O
I
O
I
TTL
ST
—
ST
—
Digital I/O.
PGC
T1OSO
T13CKI
P1C
In-Circuit Debugger and ICSP programming clock pin.
Timer1 oscillator output.
Timer1/Timer3 external clock output.
Enhanced CCP1/PWM output.
Interrupt-on-change pin.
KBI2
TTL
RB7/PGD/T1OSI/
P1D/KBI3
RB7
13
14
16
I/O
I/O
I
O
I
TTL
ST
CMOS
—
Digital I/O.
PGD
T1OSI
P1D
KBI3
In-Circuit Debugger and ICSP programming data pin.
Timer1 oscillator input.
Enhanced CCP1/PWM output.
Interrupt-on-change pin.
TTL
VSS
VDD
NC
5
5, 6
3, 5
P
P
—
—
—
Ground reference for logic and I/O pins.
Positive supply for logic and I/O pins.
No connect.
14
—
15, 16 17, 19
18
—
—
Legend: TTL = TTL compatible input
CMOS = CMOS compatible input or output
ST
O
OD
=
=
=
Schmitt Trigger input with CMOS levels
Output
Open-drain (no P diode to VDD)
I
P
= Input
= Power
© 2007 Microchip Technology Inc.
DS39605F-page 9
PIC18F1220/1320
NOTES:
DS39605F-page 10
© 2007 Microchip Technology Inc.
PIC18F1220/1320
FIGURE 2-1:
CRYSTAL/CERAMIC
RESONATOROPERATION
(XT, LP, HS OR HSPLL
CONFIGURATION)
2.0
2.1
OSCILLATOR
CONFIGURATIONS
Oscillator Types
(1)
C1
C2
OSC1
The PIC18F1220 and PIC18F1320 devices can be
operated in ten different oscillator modes. The user can
program the configuration bits, FOSC3:FOSC0, in
Configuration Register 1H to select one of these ten
modes:
To
Internal
Logic
(3)
RF
XTAL
Sleep
(2)
RS
1. LP
Low-Power Crystal
(1)
PIC18FXXXX
2. XT
Crystal/Resonator
OSC2
3. HS
High-Speed Crystal/Resonator
Note 1: See Table 2-1 and Table 2-2 for initial
4. HSPLL
High-Speed Crystal/Resonator
with PLL enabled
values of C1 and C2.
2: A series resistor (RS) may be required for
5. RC
External Resistor/Capacitor with
FOSC/4 output on RA6
AT strip cut crystals.
3: RF varies with the oscillator mode chosen.
6. RCIO
7. INTIO1
8. INTIO2
External Resistor/Capacitor with
I/O on RA6
Internal Oscillator with FOSC/4
output on RA6 and I/O on RA7
TABLE 2-1:
CAPACITOR SELECTION FOR
CERAMIC RESONATORS
Internal Oscillator with I/O on RA6
and RA7
Typical Capacitor Values Used:
9. EC
External Clock with FOSC/4 output
External Clock with I/O on RA6
10. ECIO
Mode
Freq
OSC1
OSC2
XT
455 kHz
2.0 MHz
4.0 MHz
56 pF
47 pF
33 pF
56 pF
47 pF
33 pF
2.2
Crystal Oscillator/Ceramic
Resonators
HS
8.0 MHz
16.0 MHz
27 pF
22 pF
27 pF
22 pF
In XT, LP, HS or HSPLL Oscillator modes, a crystal or
ceramic resonator is connected to the OSC1 and
OSC2 pins to establish oscillation. Figure 2-1 shows
the pin connections.
Capacitor values are for design guidance only.
These capacitors were tested with the resonators
listed below for basic start-up and operation. These
values are not optimized.
The oscillator design requires the use of a parallel cut
crystal.
Different capacitor values may be required to produce
acceptable oscillator operation. The user should test
the performance of the oscillator over the expected
VDD and temperature range for the application.
Note:
Use of a series cut crystal may give a
frequency out of the crystal manufacturer’s
specifications.
See the notes following Table 2-2 for additional
information.
Resonators Used:
455 kHz
2.0 MHz
4.0 MHz
8.0 MHz
16.0 MHz
© 2007 Microchip Technology Inc.
DS39605F-page 11
PIC18F1220/1320
An external clock source may also be connected to the
OSC1 pin in the HS mode, as shown in Figure 2-2.
TABLE 2-2:
CAPACITOR SELECTION FOR
CRYSTAL OSCILLATOR
Typical Capacitor Values
FIGURE 2-2:
EXTERNAL CLOCK INPUT
OPERATION (HS OSC
CONFIGURATION)
Crystal
Freq
Tested:
Osc Type
C1
C2
LP
XT
HS
32 kHz
200 kHz
1 MHz
4 MHz
4 MHz
8 MHz
20 MHz
33 pF
15 pF
33 pF
27 pF
27 pF
22 pF
15 pF
33 pF
15 pF
33 pF
27 pF
27 pF
22 pF
15 pF
OSC1
Clock from
Ext. System
PIC18FXXXX
(HS Mode)
OSC2
Open
2.3
HSPLL
Capacitor values are for design guidance only.
A Phase Locked Loop (PLL) circuit is provided as an
option for users who wish to use a lower frequency
crystal oscillator circuit, or to clock the device up to its
highest rated frequency from a crystal oscillator. This
may be useful for customers who are concerned with
EMI due to high-frequency crystals.
These capacitors were tested with the crystals listed
below for basic start-up and operation. These values
are not optimized.
Different capacitor values may be required to produce
acceptable oscillator operation. The user should test
the performance of the oscillator over the expected
VDD and temperature range for the application.
The HSPLL mode makes use of the HS mode oscillator
for frequencies up to 10 MHz. A PLL then multiplies the
oscillator output frequency by 4 to produce an internal
clock frequency up to 40 MHz.
See the notes following this table for additional
information.
The PLL is enabled only when the oscillator configura-
tion bits are programmed for HSPLL mode. If
programmed for any other mode, the PLL is not
enabled.
Crystals Used:
32 kHz
200 kHz
1 MHz
4 MHz
8 MHz
20 MHz
FIGURE 2-3:
PLL BLOCK DIAGRAM
HS Oscillator Enable
Note 1: Higher capacitance increases the stability
of oscillator, but also increases the start-up
time.
PLL Enable
(from Configuration Register 1H)
2: When operating below 3V VDD, or when
using certain ceramic resonators at any
voltage, it may be necessary to use the
HS mode or switch to a crystal oscillator.
OSC2
OSC1
Phase
Comparator
FIN
Crystal
Osc
FOUT
3: Since each resonator/crystal has its own
characteristics, the user should consult
the resonator/crystal manufacturer for
Loop
Filter
appropriate
values
of
external
components.
÷4
VCO
4: RS may be required to avoid overdriving
SYSCLK
crystals with low drive level specification.
5: Always verify oscillator performance over
the VDD and temperature range that is
expected for the application.
DS39605F-page 12
© 2007 Microchip Technology Inc.
PIC18F1220/1320
2.4
External Clock Input
2.5
RC Oscillator
The EC and ECIO Oscillator modes require an external
clock source to be connected to the OSC1 pin. There is
no oscillator start-up time required after a Power-on
Reset, or after an exit from Sleep mode.
For timing insensitive applications, the “RC” and
“RCIO” device options offer additional cost savings.
The RC oscillator frequency is a function of the supply
voltage, the resistor (REXT) and capacitor (CEXT) val-
ues and the operating temperature. In addition to this,
the oscillator frequency will vary from unit to unit due to
normal manufacturing variation. Furthermore, the dif-
ference in lead frame capacitance between package
types will also affect the oscillation frequency, espe-
cially for low CEXT values. The user also needs to take
into account variation, due to tolerance of external
R and C components used. Figure 2-6 shows how the
R/C combination is connected.
In the EC Oscillator mode, the oscillator frequency
divided by 4 is available on the OSC2 pin. This signal
may be used for test purposes, or to synchronize other
logic. Figure 2-4 shows the pin connections for the EC
Oscillator mode.
FIGURE 2-4:
EXTERNAL CLOCK INPUT
OPERATION
(EC CONFIGURATION)
In the RC Oscillator mode, the oscillator frequency
divided by 4 is available on the OSC2 pin. This signal
may be used for test purposes, or to synchronize other
logic.
OSC1/CLKI
Clock from
Ext. System
PIC18FXXXX
OSC2/CLKO
FOSC/4
FIGURE 2-6:
RC OSCILLATOR MODE
VDD
The ECIO Oscillator mode functions like the EC mode,
except that the OSC2 pin becomes an additional gen-
eral purpose I/O pin. The I/O pin becomes bit 6 of
PORTA (RA6). Figure 2-5 shows the pin connections
for the ECIO Oscillator mode.
REXT
Internal
OSC1
Clock
CEXT
VSS
PIC18FXXXX
FIGURE 2-5:
EXTERNAL CLOCK INPUT
OPERATION
OSC2/CLKO
FOSC/4
(ECIO CONFIGURATION)
Recommended values: 3 kΩ ≤ REXT ≤ 100 kΩ
CEXT > 20 pF
OSC1/CLKI
PIC18FXXXX
I/O (OSC2)
Clock from
Ext. System
The RCIO Oscillator mode (Figure 2-7) functions like
the RC mode, except that the OSC2 pin becomes an
additional general purpose I/O pin. The I/O pin
becomes bit 6 of PORTA (RA6).
RA6
FIGURE 2-7:
RCIO OSCILLATOR MODE
VDD
REXT
Internal
OSC1
Clock
CEXT
PIC18FXXXX
VSS
I/O (OSC2)
RA6
Recommended values: 3 kΩ ≤ REXT ≤ 100 kΩ
CEXT > 20 pF
© 2007 Microchip Technology Inc.
DS39605F-page 13
PIC18F1220/1320
2.6.2
INTRC OUTPUT FREQUENCY
2.6
Internal Oscillator Block
The internal oscillator block is calibrated at the factory
to produce an INTOSC output frequency of 8.0 MHz
(see Table 22-6). This changes the frequency of the
INTRC source from its nominal 31.25 kHz. Peripherals
and features that depend on the INTRC source will be
affected by this shift in frequency.
The PIC18F1220/1320 devices include an internal
oscillator block, which generates two different clock
signals; either can be used as the system’s clock
source. This can eliminate the need for external
oscillator circuits on the OSC1 and/or OSC2 pins.
The main output (INTOSC) is an 8 MHz clock source,
which can be used to directly drive the system clock. It
also drives a postscaler, which can provide a range of
clock frequencies from 125 kHz to 4 MHz. The
INTOSC output is enabled when a system clock
frequency from 125 kHz to 8 MHz is selected.
Once set during factory calibration, the INTRC
frequency will remain within ±2% as temperature and
VDD change across their full specified operating
ranges.
2.6.3
OSCTUNE REGISTER
The other clock source is the internal RC oscillator
(INTRC), which provides a 31 kHz output. The INTRC
oscillator is enabled by selecting the internal oscillator
block as the system clock source, or when any of the
following are enabled:
The internal oscillator’s output has been calibrated at
the factory, but can be adjusted in the user’s applica-
tion. This is done by writing to the OSCTUNE register
(Register 2-1). The tuning sensitivity is constant
throughout the tuning range.
• Power-up Timer
When the OSCTUNE register is modified, the INTOSC
and INTRC frequencies will begin shifting to the new
frequency. The INTRC clock will reach the new
frequency within 8 clock cycles (approximately
8 * 32 μs = 256 μs). The INTOSC clock will stabilize
within 1 ms. Code execution continues during this shift.
There is no indication that the shift has occurred.
Operation of features that depend on the INTRC clock
source frequency, such as the WDT, Fail-Safe Clock
Monitor and peripherals, will also be affected by the
change in frequency.
• Fail-Safe Clock Monitor
• Watchdog Timer
• Two-Speed Start-up
These features are discussed in greater detail in
Section 19.0 “Special Features of the CPU”.
The clock source frequency (INTOSC direct, INTRC
direct or INTOSC postscaler) is selected by configuring
the IRCF bits of the OSCCON register (Register 2-2).
2.6.1
INTIO MODES
Using the internal oscillator as the clock source can
eliminate the need for up to two external oscillator pins,
which can then be used for digital I/O. Two distinct
configurations are available:
• In INTIO1 mode, the OSC2 pin outputs FOSC/4,
while OSC1 functions as RA7 for digital input and
output.
• In INTIO2 mode, OSC1 functions as RA7 and
OSC2 functions as RA6, both for digital input and
output.
DS39605F-page 14
© 2007 Microchip Technology Inc.
PIC18F1220/1320
REGISTER 2-1:
OSCTUNE: OSCILLATOR TUNING REGISTER
U-0
—
U-0
—
R/W-0
TUN5
R/W-0
TUN4
R/W-0
TUN3
R/W-0
TUN2
R/W-0
TUN1
R/W-0
TUN0
bit 7
bit 0
bit 7-6
bit 5-0
Unimplemented: Read as ‘0’
TUN<5:0>: Frequency Tuning bits
011111= Maximum frequency
•
•
•
•
000001
000000= Center frequency. Oscillator module is running at the calibrated frequency.
111111
•
•
•
•
100000= Minimum frequency
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
PIC18F1220/1320 devices offer only the Timer1
oscillator as a secondary oscillator. This oscillator, in all
power managed modes, is often the time base for
functions such as a real-time clock.
2.7
Clock Sources and Oscillator
Switching
Like previous PIC18 devices, the PIC18F1220/1320
devices include a feature that allows the system clock
source to be switched from the main oscillator to an
alternate low-frequency clock source. PIC18F1220/
1320 devices offer two alternate clock sources. When
enabled, these give additional options for switching to
the various power managed operating modes.
Most often, a 32.768 kHz watch crystal is connected
between the RB6/T1OSO and RB7/T1OSI pins. Like
the LP mode oscillator circuit, loading capacitors are
also connected from each pin to ground. These pins
are also used during ICSP operations.
The Timer1 oscillator is discussed in greater detail in
Section 12.2 “Timer1 Oscillator”.
Essentially, there are three clock sources for these
devices:
In addition to being a primary clock source, the internal
oscillator block is available as a power managed
mode clock source. The INTRC source is also used as
the clock source for several special features, such as
the WDT and Fail-Safe Clock Monitor.
• Primary oscillators
• Secondary oscillators
• Internal oscillator block
The primary oscillators include the External Crystal
and Resonator modes, the External RC modes, the
External Clock modes and the internal oscillator block.
The particular mode is defined on POR by the contents
of Configuration Register 1H. The details of these
modes are covered earlier in this chapter.
The clock sources for the PIC18F1220/1320 devices
are shown in Figure 2-8. See Section 12.0 “Timer1
Module” for further details of the Timer1 oscillator. See
Section 19.1 “Configuration Bits” for configuration
register details.
The secondary oscillators are those external sources
not connected to the OSC1 or OSC2 pins. These
sources may continue to operate even after the
controller is placed in a power managed mode.
© 2007 Microchip Technology Inc.
DS39605F-page 15
PIC18F1220/1320
when the internal oscillator block has stabilized and is
providing the system clock in RC Clock modes or
during Two-Speed Start-ups. The T1RUN bit
(T1CON<6>) indicates when the Timer1 oscillator is
providing the system clock in Secondary Clock modes.
In power managed modes, only one of these three bits
will be set at any time. If none of these bits are set, the
INTRC is providing the system clock, or the internal
oscillator block has just started and is not yet stable.
2.7.1
OSCILLATOR CONTROL REGISTER
The OSCCON register (Register 2-2) controls several
aspects of the system clock’s operation, both in full
power operation and in power managed modes.
The System Clock Select bits, SCS1:SCS0, select the
clock source that is used when the device is operating in
power managed modes. The available clock sources are
the primary clock (defined in Configuration Register 1H),
the secondary clock (Timer1 oscillator) and the internal
oscillator block. The clock selection has no effect until a
SLEEP instruction is executed and the device enters a
power managed mode of operation. The SCS bits are
cleared on all forms of Reset.
The IDLEN bit controls the selective shutdown of the
controller’s CPU in power managed modes. The uses
of these bits are discussed in more detail in
Section 3.0 “Power Managed Modes”.
Note 1: The Timer1 oscillator must be enabled to
select the secondary clock source. The
Timer1 oscillator is enabled by setting the
T1OSCEN bit in the Timer1 Control regis-
ter (T1CON<3>). If the Timer1 oscillator
is not enabled, then any attempt to select
The Internal Oscillator Select bits, IRCF2:IRCF0, select
the frequency output of the internal oscillator block that
is used to drive the system clock. The choices are the
INTRC source, the INTOSC source (8 MHz), or one of
the six frequencies derived from the INTOSC
postscaler (125 kHz to 4 MHz). If the internal oscillator
block is supplying the system clock, changing the
states of these bits will have an immediate change on
the internal oscillator’s output.
a
secondary clock source when
executing a SLEEP instruction will be
ignored.
2: It is recommended that the Timer1 oscil-
lator be operating and stable before exe-
cuting the SLEEP instruction or a very
long delay may occur while the Timer1
oscillator starts.
The OSTS, IOFS and T1RUN bits indicate which clock
source is currently providing the system clock. The
OSTS indicates that the Oscillator Start-up Timer has
timed out and the primary clock is providing the system
clock in Primary Clock modes. The IOFS bit indicates
FIGURE 2-8:
PIC18F1220/1320 CLOCK DIAGRAM
PIC18F1220/1320
Clock
Control
CONFIG1H<3:0>
HSPLL
OSCCON<1:0>
Peripherals
Primary Oscillator
OSC2
4 x PLL
Sleep
LP, XT, HS, RC, EC
T1OSC
OSC1
Secondary Oscillator
T1OSO
Clock Source Option
for Other Modules
T1OSCEN
Enable
Oscillator
T1OSI
OSCCON<6:4>
Internal Oscillator
CPU
8
OSCCON<6:4>
111
4 MHz
110
101
Internal
Oscillator
Block
2 MHz
1 MHz
IDLEN
100
011
010
001
000
500 kHz
250 kHz
125 kHz
31 kHz
8 MHz
(INTOSC)
INTRC
Source
WDT, FSCM
DS39605F-page 16
© 2007 Microchip Technology Inc.
PIC18F1220/1320
REGISTER 2-2:
OSCCON REGISTER
R/W-0
IDLEN
R/W-0
IRCF2
R/W-0
IRCF1
R/W-0
IRCF0
R(1)
R-0
R/W-0
SCS1
R/W-0
SCS0
OSTS
IOFS
bit 7
bit 0
bit 7
IDLEN: Idle Enable bits
1= Idle mode enabled; CPU core is not clocked in power managed modes
0= Run mode enabled; CPU core is clocked in Run modes, but not Sleep mode
bit 6-4 IRCF2:IRCF0: Internal Oscillator Frequency Select bits
111= 8 MHz (8 MHz source drives clock directly)
110= 4 MHz
101= 2 MHz
100= 1 MHz
011= 500 kHz
010= 250 kHz
001= 125 kHz
000= 31 kHz (INTRC source drives clock directly)
bit 3
bit 2
OSTS: Oscillator Start-up Time-out Status bit
1= Oscillator Start-up Timer time-out has expired; primary oscillator is running
0= Oscillator Start-up Timer time-out is running; primary oscillator is not ready
IOFS: INTOSC Frequency Stable bit
1= INTOSC frequency is stable
0= INTOSC frequency is not stable
bit 1-0 SCS1:SCS0: System Clock Select bits
1x= Internal oscillator block (RC modes)
01= Timer1 oscillator (Secondary modes)
00= Primary oscillator (Sleep and PRI_IDLE modes)
Note 1: Depends on state of the IESO bit in Configuration Register 1H.
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
© 2007 Microchip Technology Inc.
DS39605F-page 17
PIC18F1220/1320
If the Sleep mode is selected, all clock sources are
stopped. Since all the transistor switching currents
have been stopped, Sleep mode achieves the lowest
current consumption of the device (only leakage
currents).
2.7.2
OSCILLATOR TRANSITIONS
The PIC18F1220/1320 devices contain circuitry to
prevent clocking “glitches” when switching between
clock sources. A short pause in the system clock
occurs during the clock switch. The length of this pause
is between 8 and 9 clock periods of the new clock
source. This ensures that the new clock source is
stable and that its pulse width will not be less than the
shortest pulse width of the two clock sources.
Enabling any on-chip feature that will operate during
Sleep will increase the current consumed during Sleep.
The INTRC is required to support WDT operation. The
Timer1 oscillator may be operating to support a real-
time clock. Other features may be operating that do not
require a system clock source (i.e., INTn pins, A/D
conversions and others).
Clock transitions are discussed in greater detail in
Section 3.1.2 “Entering Power Managed Modes”.
2.8
Effects of Power Managed Modes
on the Various Clock Sources
2.9
Power-up Delays
Power-up delays are controlled by two timers, so that
no external Reset circuitry is required for most applica-
tions. The delays ensure that the device is kept in
Reset until the device power supply is stable under nor-
mal circumstances and the primary clock is operating
and stable. For additional information on power-up
delays, see Sections 4.1 through 4.5.
When the device executes a SLEEP instruction, the
system is switched to one of the power managed
modes, depending on the state of the IDLEN and
SCS1:SCS0 bits of the OSCCON register. See
Section 3.0 “Power Managed Modes” for details.
When PRI_IDLE mode is selected, the designated pri-
mary oscillator continues to run without interruption.
For all other power managed modes, the oscillator
using the OSC1 pin is disabled. The OSC1 pin (and
OSC2 pin, if used by the oscillator) will stop oscillating.
The first timer is the Power-up Timer (PWRT), which
provides a fixed delay on power-up (parameter 33,
Table 22-8) if enabled in Configuration Register 2L.
The second timer is the Oscillator Start-up Timer
(OST), intended to keep the chip in Reset until the
crystal oscillator is stable (LP, XT and HS modes). The
OST does this by counting 1024 oscillator cycles
before allowing the oscillator to clock the device.
In Secondary Clock modes (SEC_RUN and
SEC_IDLE), the Timer1 oscillator is operating and
providing the system clock. The Timer1 oscillator may
also run in all power managed modes if required to
clock Timer1 or Timer3.
When the HSPLL Oscillator mode is selected, the
device is kept in Reset for an additional 2 ms following
the HS mode OST delay, so the PLL can lock to the
incoming clock frequency.
In Internal Oscillator modes (RC_RUN and RC_IDLE),
the internal oscillator block provides the system clock
source. The INTRC output can be used directly to
provide the system clock and may be enabled to
support various special features, regardless of the
power managed mode (see Section 19.2 “Watchdog
Timer (WDT)” through Section 19.4 “Fail-Safe Clock
Monitor”). The INTOSC output at 8 MHz may be used
directly to clock the system, or may be divided down
first. The INTOSC output is disabled if the system clock
is provided directly from the INTRC output.
There is a delay of 5 to 10 μs following POR while the
controller becomes ready to execute instructions. This
delay runs concurrently with any other delays. This
may be the only delay that occurs when any of the EC,
RC or INTIO modes are used as the primary clock
source.
TABLE 2-3:
OSC1 AND OSC2 PIN STATES IN SLEEP MODE
OSC1 Pin
Oscillator Mode
OSC2 Pin
RC, INTIO1
RCIO, INTIO2
ECIO
Floating, external resistor should pull high
Floating, external resistor should pull high
Floating, pulled by external clock
At logic low (clock/4 output)
Configured as PORTA, bit 6
Configured as PORTA, bit 6
At logic low (clock/4 output)
EC
Floating, pulled by external clock
LP, XT and HS
Feedback inverter disabled at quiescent
voltage level
Feedback inverter disabled at quiescent
voltage level
Note:
See Table 4-1 in Section 4.0 “Reset” for time-outs due to Sleep and MCLR Reset.
DS39605F-page 18
© 2007 Microchip Technology Inc.
PIC18F1220/1320
For PIC18F1220/1320 devices, the power managed
modes are invoked by using the existing SLEEP
instruction. All modes exit to PRI_RUN mode when trig-
gered by an interrupt, a Reset or a WDT time-out
(PRI_RUN mode is the normal full power execution
mode; the CPU and peripherals are clocked by the pri-
mary oscillator source). In addition, power managed
Run modes may also exit to Sleep mode, or their
corresponding Idle mode.
3.0
POWER MANAGED MODES
The PIC18F1220/1320 devices offer a total of six oper-
ating modes for more efficient power management
(see Table 3-1). These provide a variety of options for
selective power conservation in applications where
resources may be limited (i.e., battery powered
devices).
There are three categories of power managed modes:
• Sleep mode
• Idle modes
• Run modes
3.1
Selecting Power Managed Modes
Selecting a power managed mode requires deciding if
the CPU is to be clocked or not and selecting a clock
source. The IDLEN bit controls CPU clocking, while the
SCS1:SCS0 bits select a clock source. The individual
modes, bit settings, clock sources and affected
modules are summarized in Table 3-1.
These categories define which portions of the device
are clocked and sometimes, what speed. The Run and
Idle modes may use any of the three available clock
sources (primary, secondary or INTOSC multiplexer);
the Sleep mode does not use a clock source.
The clock switching feature offered in other PIC18
devices (i.e., using the Timer1 oscillator in place of the
primary oscillator) and the Sleep mode offered by all
PIC® devices (where all system clocks are stopped) are
both offered in the PIC18F1220/1320 devices
(SEC_RUN and Sleep modes, respectively). However,
additional power managed modes are available that
allow the user greater flexibility in determining what
portions of the device are operating. The power man-
aged modes are event driven; that is, some specific
event must occur for the device to enter or (more
particularly) exit these operating modes.
3.1.1
CLOCK SOURCES
The clock source is selected by setting the SCS bits of
the OSCCON register (Register 2-2). Three clock
sources are available for use in power managed Idle
modes: the primary clock (as configured in Configuration
Register 1H), the secondary clock (Timer1 oscillator)
and the internal oscillator block. The secondary and
internal oscillator block sources are available for the
power managed modes (PRI_RUN mode is the normal
full power execution mode; the CPU and peripherals are
clocked by the primary oscillator source).
TABLE 3-1:
Mode
POWER MANAGED MODES
OSCCON Bits
Module Clocking
Available Clock and Oscillator Source
IDLEN SCS1:SCS0
CPU
Peripherals
<7>
<1:0>
Sleep
0
0
00
00
Off
Off
None – All clocks are disabled
Primary – LP, XT, HS, HSPLL, RC, EC, INTRC(1)
PRI_RUN
Clocked
Clocked
This is the normal full power execution mode.
SEC_RUN
RC_RUN
PRI_IDLE
SEC_IDLE
RC_IDLE
0
0
1
1
1
01
1x
00
01
1x
Clocked
Clocked
Off
Clocked
Clocked
Clocked
Clocked
Clocked
Secondary – Timer1 Oscillator
Internal Oscillator Block(1)
Primary – LP, XT, HS, HSPLL, RC, EC
Secondary – Timer1 Oscillator
Internal Oscillator Block(1)
Off
Off
Note 1: Includes INTOSC and INTOSC postscaler, as well as the INTRC source.
© 2007 Microchip Technology Inc.
DS39605F-page 19
PIC18F1220/1320
3.1.2
ENTERING POWER MANAGED
MODES
Note 1: Caution should be used when modifying a
single IRCF bit. If VDD is less than 3V, it is
possible to select a higher clock speed
than is supported by the low VDD.
Improper device operation may result if
the VDD/FOSC specifications are violated.
In general, entry, exit and switching between power
managed clock sources requires clock source
switching. In each case, the sequence of events is the
same.
Any change in the power managed mode begins with
loading the OSCCON register and executing a SLEEP
instruction. The SCS1:SCS0 bits select one of three
power managed clock sources; the primary clock (as
defined in Configuration Register 1H), the secondary
clock (the Timer1 oscillator) and the internal oscillator
block (used in RC modes). Modifying the SCS bits will
have no effect until a SLEEP instruction is executed.
Entry to the power managed mode is triggered by the
execution of a SLEEPinstruction.
2: Executing a SLEEP instruction does not
necessarily place the device into Sleep
mode; executing a SLEEP instruction is
simply a trigger to place the controller into
a power managed mode selected by the
OSCCON register, one of which is Sleep
mode.
3.1.3
MULTIPLE SLEEP COMMANDS
The power managed mode that is invoked with the
SLEEPinstruction is determined by the settings of the
IDLEN and SCS bits at the time the instruction is exe-
cuted. If another SLEEP instruction is executed, the
device will enter the power managed mode specified by
these same bits at that time. If the bits have changed,
the device will enter the new power managed mode
specified by the new bit settings.
Figure 3-5 shows how the system is clocked while
switching from the primary clock to the Timer1 oscilla-
tor. When the SLEEPinstruction is executed, clocks to
the device are stopped at the beginning of the next
instruction cycle. Eight clock cycles from the new clock
source are counted to synchronize with the new clock
source. After eight clock pulses from the new clock
source are counted, clocks from the new clock source
resume clocking the system. The actual length of the
pause is between eight and nine clock periods from the
new clock source. This ensures that the new clock
source is stable and that its pulse width will not be less
than the shortest pulse width of the two clock sources.
3.1.4
COMPARISONS BETWEEN RUN
AND IDLE MODES
Clock source selection for the Run modes is identical to
the corresponding Idle modes. When a SLEEPinstruc-
tion is executed, the SCS bits in the OSCCON register
are used to switch to a different clock source. As a
result, if there is a change of clock source at the time a
SLEEPinstruction is executed, a clock switch will occur.
Three bits indicate the current clock source: OSTS and
IOFS in the OSCCON register and T1RUN in the
T1CON register. Only one of these bits will be set while
in a power managed mode. When the OSTS bit is set,
the primary clock is providing the system clock. When
the IOFS bit is set, the INTOSC output is providing a
stable 8 MHz clock source and is providing the system
clock. When the T1RUN bit is set, the Timer1 oscillator
is providing the system clock. If none of these bits are
set, then either the INTRC clock source is clocking the
system, or the INTOSC source is not yet stable.
In Idle modes, the CPU is not clocked and is not run-
ning. In Run modes, the CPU is clocked and executing
code. This difference modifies the operation of the
WDT when it times out. In Idle modes, a WDT time-out
results in a wake from power managed modes. In Run
modes, a WDT time-out results in a WDT Reset (see
Table 3-2).
During a wake-up from an Idle mode, the CPU starts
executing code by entering the corresponding Run
mode until the primary clock becomes ready. When the
primary clock becomes ready, the clock source is auto-
matically switched to the primary clock. The IDLEN and
SCS bits are unchanged during and after the wake-up.
If the internal oscillator block is configured as the pri-
mary clock source in Configuration Register 1H, then
both the OSTS and IOFS bits may be set when in
PRI_RUN or PRI_IDLE modes. This indicates that the
primary clock (INTOSC output) is generating a stable
8 MHz output. Entering an RC power managed mode
(same frequency) would clear the OSTS bit.
Figure 3-2 shows how the system is clocked during the
clock source switch. The example assumes the device
was in SEC_IDLE or SEC_RUN mode when a wake is
triggered (the primary clock was configured in HSPLL
mode).
DS39605F-page 20
© 2007 Microchip Technology Inc.
PIC18F1220/1320
TABLE 3-2:
COMPARISON BETWEEN POWER MANAGED MODES
Power
Managed
Mode
Clock during Wake-up
(while primary becomes
ready)
WDT Time-out
causes a ...
Peripherals are
Clocked by ...
CPU is Clocked by ...
Sleep
Not clocked (not running) Wake-up
Not clocked
None or INTOSC multiplexer
if Two-Speed Start-up or
Fail-Safe Clock Monitor are
enabled
Any Idle mode Not clocked (not running) Wake-up
Primary, Secondary or Unchanged from Idle mode
INTOSC multiplexer
(CPU operates as in
corresponding Run mode)
Any Run mode Primary or secondary
clocks or INTOSC
Reset
Primary or secondary Unchanged from Run mode
clocks or INTOSC
multiplexer
multiplexer
If the Idle Enable bit, IDLEN (OSCCON<7>), is set to a
‘1’ when a SLEEP instruction is executed, the
peripherals will be clocked from the clock source
selected using the SCS1:SCS0 bits; however, the CPU
will not be clocked. Since the CPU is not executing
instructions, the only exits from any of the Idle modes
are by interrupt, WDT time-out or a Reset.
3.2
Sleep Mode
The power managed Sleep mode in the PIC18F1220/
1320 devices is identical to that offered in all other PIC
microcontrollers. It is entered by clearing the IDLEN
and SCS1:SCS0 bits (this is the Reset state) and
executing the SLEEPinstruction. This shuts down the
primary oscillator and the OSTS bit is cleared (see
Figure 3-1).
When a wake event occurs, CPU execution is delayed
approximately 10 μs while it becomes ready to execute
code. When the CPU begins executing code, it is
clocked by the same clock source as was selected in
the power managed mode (i.e., when waking from
RC_IDLE mode, the internal oscillator block will clock
the CPU and peripherals until the primary clock source
becomes ready – this is essentially RC_RUN mode).
This continues until the primary clock source becomes
ready. When the primary clock becomes ready, the
OSTS bit is set and the system clock source is
switched to the primary clock (see Figure 3-4). The
IDLEN and SCS bits are not affected by the wake-up.
When a wake event occurs in Sleep mode (by interrupt,
Reset or WDT time-out), the system will not be clocked
until the primary clock source becomes ready (see
Figure 3-2), or it will be clocked from the internal
oscillator block if either the Two-Speed Start-up or the
Fail-Safe Clock Monitor are enabled (see Section 19.0
“Special Features of the CPU”). In either case, the
OSTS bit is set when the primary clock is providing the
system clocks. The IDLEN and SCS bits are not
affected by the wake-up.
3.3
Idle Modes
While in any Idle mode or the Sleep mode, a WDT
time-out will result in a WDT wake-up to full power
operation.
The IDLEN bit allows the microcontroller’s CPU to be
selectively shut down while the peripherals continue to
operate. Clearing IDLEN allows the CPU to be clocked.
Setting IDLEN disables clocks to the CPU, effectively
stopping program execution (see Register 2-2). The
peripherals continue to be clocked regardless of the
setting of the IDLEN bit.
There is one exception to how the IDLEN bit functions.
When all the low-power OSCCON bits are cleared
(IDLEN:SCS1:SCS0 = 000), the device enters Sleep
mode upon the execution of the SLEEPinstruction. This
is both the Reset state of the OSCCON register and the
setting that selects Sleep mode. This maintains
compatibility with other PIC devices that do not offer
power managed modes.
© 2007 Microchip Technology Inc.
DS39605F-page 21
PIC18F1220/1320
FIGURE 3-1:
TIMING TRANSITION FOR ENTRY TO SLEEP MODE
Q1 Q2 Q3 Q4 Q1
OSC1
CPU
Clock
Peripheral
Clock
Sleep
Program
Counter
PC
PC + 2
FIGURE 3-2:
TRANSITION TIMING FOR WAKE FROM SLEEP (HSPLL)
Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
Q1 Q2 Q3 Q4 Q1 Q2
OSC1
(1)
(1)
TOST
TPLL
PLL Clock
Output
CPU Clock
Peripheral
Clock
Program
Counter
PC + 4
PC + 6
PC
PC + 2
PC + 8
Wake Event
OSTS bit Set
Note 1: TOST = 1024 TOSC; TPLL = 2 ms (approx). These intervals are not shown to scale.
DS39605F-page 22
© 2007 Microchip Technology Inc.
PIC18F1220/1320
When a wake event occurs, the CPU is clocked from
the primary clock source. A delay of approximately
10 μs is required between the wake event and code
execution starts. This is required to allow the CPU to
become ready to execute instructions. After the wake-
up, the OSTS bit remains set. The IDLEN and SCS bits
are not affected by the wake-up (see Figure 3-4).
3.3.1
PRI_IDLE MODE
This mode is unique among the three Low-Power Idle
modes, in that it does not disable the primary system
clock. For timing sensitive applications, this allows for
the fastest resumption of device operation with its more
accurate primary clock source, since the clock source
does not have to “warm up” or transition from another
oscillator.
PRI_IDLE mode is entered by setting the IDLEN bit,
clearing the SCS bits and executing a SLEEPinstruc-
tion. Although the CPU is disabled, the peripherals
continue to be clocked from the primary clock source
specified in Configuration Register 1H. The OSTS bit
remains set in PRI_IDLE mode (see Figure 3-3).
FIGURE 3-3:
TRANSITION TIMING TO PRI_IDLE MODE
Q3
Q4
Q1
Q1
Q2
OSC1
CPU Clock
Peripheral
Clock
Program
Counter
PC
PC + 2
FIGURE 3-4:
TRANSITION TIMING FOR WAKE FROM PRI_IDLE MODE
Q1
Q3
Q4
Q2
OSC1
CPU Start-up Delay
CPU Clock
Peripheral
Clock
Program
Counter
PC + 2
PC
Wake Event
© 2007 Microchip Technology Inc.
DS39605F-page 23
PIC18F1220/1320
When a wake event occurs, the peripherals continue to
be clocked from the Timer1 oscillator. After a 10 μs
delay following the wake event, the CPU begins exe-
cuting code, being clocked by the Timer1 oscillator. The
microcontroller operates in SEC_RUN mode until the
primary clock becomes ready. When the primary clock
becomes ready, a clock switchback to the primary clock
occurs (see Figure 3-6). When the clock switch is com-
plete, the T1RUN bit is cleared, the OSTS bit is set and
the primary clock is providing the system clock. The
IDLEN and SCS bits are not affected by the wake-up.
The Timer1 oscillator continues to run.
3.3.2
SEC_IDLE MODE
In SEC_IDLE mode, the CPU is disabled, but the
peripherals continue to be clocked from the Timer1
oscillator. This mode is entered by setting the Idle bit,
modifying bits, SCS1:SCS0 = 01 and executing a
SLEEPinstruction. When the clock source is switched
(see Figure 3-5) to the Timer1 oscillator, the primary
oscillator is shut down, the OSTS bit is cleared and the
T1RUN bit is set.
Note:
The Timer1 oscillator should already be
running prior to entering SEC_IDLE mode.
If the T1OSCEN bit is not set when the
SLEEPinstruction is executed, the SLEEP
instruction will be ignored and entry to
SEC_IDLE mode will not occur. If the
Timer1 oscillator is enabled, but not yet
running, peripheral clocks will be delayed
until the oscillator has started; in such sit-
uations, initial oscillator operation is far
from stable and unpredictable operation
may result.
FIGURE 3-5:
TIMING TRANSITION FOR ENTRY TO SEC_IDLE MODE
Q1 Q2 Q3 Q4 Q1
1
2
3
4
5
6
7
8
T1OSI
OSC1
Clock Transition
CPU
Clock
Peripheral
Clock
Program
Counter
PC
PC + 2
FIGURE 3-6:
TIMING TRANSITION FOR WAKE FROM SEC_RUN MODE (HSPLL)
Q3
Q4
Q1
Q2 Q3 Q4 Q1 Q2 Q3
Q1
Q2
T1OSI
OSC1
(1)
TOST
(1)
TPLL
PLL Clock
Output
1
2
3
4
5
6
7
8
Clock Transition
CPU Clock
Peripheral
Clock
Program
Counter
PC + 4
PC + 6
PC
PC + 2
OSTS bit Set
Note 1: TOST = 1024 TOSC; TPLL = 2 ms (approx). These intervals are not shown to scale.
Wake from Interrupt Event
DS39605F-page 24
© 2007 Microchip Technology Inc.
PIC18F1220/1320
instruction was executed and the INTOSC source was
already stable, the IOFS bit will remain set. If the IRCF
bits are all clear, the INTOSC output is not enabled and
the IOFS bit will remain clear; there will be no indication
of the current clock source.
3.3.3
RC_IDLE MODE
In RC_IDLE mode, the CPU is disabled, but the periph-
erals continue to be clocked from the internal oscillator
block using the INTOSC multiplexer. This mode allows
for controllable power conservation during Idle periods.
When a wake event occurs, the peripherals continue to
be clocked from the INTOSC multiplexer. After a 10 μs
delay following the wake event, the CPU begins exe-
cuting code, being clocked by the INTOSC multiplexer.
The microcontroller operates in RC_RUN mode until
the primary clock becomes ready. When the primary
clock becomes ready, a clock switchback to the primary
clock occurs (see Figure 3-8). When the clock switch is
complete, the IOFS bit is cleared, the OSTS bit is set
and the primary clock is providing the system clock.
The IDLEN and SCS bits are not affected by the wake-
up. The INTRC source will continue to run if either the
WDT or the Fail-Safe Clock Monitor is enabled.
This mode is entered by setting the IDLEN bit, setting
SCS1 (SCS0 is ignored) and executing a SLEEP
instruction. The INTOSC multiplexer may be used to
select a higher clock frequency by modifying the IRCF
bits before executing the SLEEPinstruction. When the
clock source is switched to the INTOSC multiplexer
(see Figure 3-7), the primary oscillator is shut down
and the OSTS bit is cleared.
If the IRCF bits are set to a non-zero value (thus,
enabling the INTOSC output), the IOFS bit becomes
set after the INTOSC output becomes stable, in about
1 ms. Clocks to the peripherals continue while the
INTOSC source stabilizes. If the IRCF bits were
previously at a non-zero value before the SLEEP
FIGURE 3-7:
TIMING TRANSITION TO RC_IDLE MODE
Q1 Q2 Q3 Q4 Q1
1
2
3
4
5
6
7
8
INTRC
OSC1
Clock Transition
CPU
Clock
Peripheral
Clock
Program
Counter
PC
PC + 2
FIGURE 3-8:
TIMING TRANSITION FOR WAKE FROM RC_RUN MODE (RC_RUN TO PRI_RUN)
Q3
Q4
Q1
Q2 Q3 Q4 Q1 Q2 Q3
Q4
Q1
Q2
INTOSC
Multiplexer
OSC1
(1)
TOST
(1)
TPLL
PLL Clock
Output
1
2
3
4
5
6
7
8
Clock Transition
CPU Clock
Peripheral
Clock
Program
Counter
PC + 4
PC + 6
PC
PC + 2
OSTS bit Set
Note 1: TOST = 1024 TOSC; TPLL = 2 ms (approx). These intervals are not shown to scale.
Wake from Interrupt Event
© 2007 Microchip Technology Inc.
DS39605F-page 25
PIC18F1220/1320
SEC_RUN mode is entered by clearing the IDLEN bit,
setting SCS1:SCS0 = 01 and executing a SLEEP
instruction. The system clock source is switched to the
Timer1 oscillator (see Figure 3-9), the primary oscilla-
tor is shut down, the T1RUN bit (T1CON<6>) is set and
the OSTS bit is cleared.
3.4
Run Modes
If the IDLEN bit is clear when a SLEEP instruction is
executed, the CPU and peripherals are both clocked
from the source selected using the SCS1:SCS0 bits.
While these operating modes may not afford the power
conservation of Idle or Sleep modes, they do allow the
device to continue executing instructions by using a
lower frequency clock source. RC_RUN mode also
offers the possibility of executing code at a frequency
greater than the primary clock.
Note:
The Timer1 oscillator should already be
running prior to entering SEC_RUN mode.
If the T1OSCEN bit is not set when the
SLEEPinstruction is executed, the SLEEP
instruction will be ignored and entry to
SEC_RUN mode will not occur. If the
Timer1 oscillator is enabled, but not yet
running, system clocks will be delayed
until the oscillator has started; in such
situations, initial oscillator operation is far
from stable and unpredictable operation
may result.
Wake-up from a power managed Run mode can be
triggered by an interrupt, or any Reset, to return to full
power operation. As the CPU is executing code in Run
modes, several additional exits from Run modes are
possible. They include exit to Sleep mode, exit to a cor-
responding Idle mode and exit by executing a RESET
instruction. While the device is in any of the power
managed Run modes, a WDT time-out will result in a
WDT Reset.
When a wake event occurs, the peripherals and CPU
continue to be clocked from the Timer1 oscillator while
the primary clock is started. When the primary clock
becomes ready, a clock switchback to the primary clock
occurs (see Figure 3-6). When the clock switch is com-
plete, the T1RUN bit is cleared, the OSTS bit is set and
the primary clock is providing the system clock. The
IDLEN and SCS bits are not affected by the wake-up.
The Timer1 oscillator continues to run.
3.4.1
PRI_RUN MODE
The PRI_RUN mode is the normal full power execution
mode. If the SLEEPinstruction is never executed, the
microcontroller operates in this mode (a SLEEPinstruc-
tion is executed to enter all other power managed
modes). All other power managed modes exit to
PRI_RUN mode when an interrupt or WDT time-out
occur.
Firmware can force an exit from SEC_RUN mode. By
clearing the T1OSCEN bit (T1CON<3>), an exit from
SEC_RUN back to normal full power operation is trig-
gered. The Timer1 oscillator will continue to run and
provide the system clock, even though the T1OSCEN
bit is cleared. The primary clock is started. When the
primary clock becomes ready, a clock switchback to the
primary clock occurs (see Figure 3-6). When the clock
switch is complete, the Timer1 oscillator is disabled, the
T1RUN bit is cleared, the OSTS bit is set and the pri-
mary clock is providing the system clock. The IDLEN
and SCS bits are not affected by the wake-up.
There is no entry to PRI_RUN mode. The OSTS bit is
set. The IOFS bit may be set if the internal oscillator
block is the primary clock source (see Section 2.7.1
“Oscillator Control Register”).
3.4.2
SEC_RUN MODE
The SEC_RUN mode is the compatible mode to the
“clock switching” feature offered in other PIC18
devices. In this mode, the CPU and peripherals are
clocked from the Timer1 oscillator. This gives users the
option of lower power consumption while still using a
high accuracy clock source.
FIGURE 3-9:
TIMING TRANSITION FOR ENTRY TO SEC_RUN MODE
Q1 Q2 Q3 Q4 Q1
Q2
Q3
Q4
Q1
Q2
Q3
1
2
3
4
5
6
7
8
T1OSI
OSC1
Clock Transition
CPU
Clock
Peripheral
Clock
Program
Counter
PC
PC + 2
PC + 2
DS39605F-page 26
© 2007 Microchip Technology Inc.
PIC18F1220/1320
3.4.3
RC_RUN MODE
Note:
Caution should be used when modifying a
single IRCF bit. If VDD is less than 3V, it is
possible to select a higher clock speed
than is supported by the low VDD.
Improper device operation may result if
the VDD/FOSC specifications are violated.
In RC_RUN mode, the CPU and peripherals are
clocked from the internal oscillator block using the
INTOSC multiplexer and the primary clock is shut
down. When using the INTRC source, this mode pro-
vides the best power conservation of all the Run
modes, while still executing code. It works well for user
applications which are not highly timing sensitive, or do
not require high-speed clocks at all times.
If the IRCF bits are all clear, the INTOSC output is not
enabled and the IOFS bit will remain clear; there will be
no indication of the current clock source. The INTRC
source is providing the system clocks.
If the primary clock source is the internal oscillator
block (either of the INTIO1 or INTIO2 oscillators), there
are no distinguishable differences between PRI_RUN
and RC_RUN modes during execution. However, a
clock switch delay will occur during entry to and exit
from RC_RUN mode. Therefore, if the primary clock
source is the internal oscillator block, the use of
RC_RUN mode is not recommended.
If the IRCF bits are changed from all clear (thus,
enabling the INTOSC output), the IOFS bit becomes
set after the INTOSC output becomes stable. Clocks to
the system continue while the INTOSC source
stabilizes, in approximately 1 ms.
If the IRCF bits were previously at a non-zero value
before the SLEEP instruction was executed and the
INTOSC source was already stable, the IOFS bit will
remain set.
This mode is entered by clearing the IDLEN bit, setting
SCS1 (SCS0 is ignored) and executing a SLEEP
instruction. The IRCF bits may select the clock
frequency before the SLEEP instruction is executed.
When the clock source is switched to the INTOSC
multiplexer (see Figure 3-10), the primary oscillator is
shut down and the OSTS bit is cleared.
When a wake event occurs, the system continues to be
clocked from the INTOSC multiplexer while the primary
clock is started. When the primary clock becomes
ready, a clock switch to the primary clock occurs (see
Figure 3-8). When the clock switch is complete, the
IOFS bit is cleared, the OSTS bit is set and the primary
clock is providing the system clock. The IDLEN and
SCS bits are not affected by the wake-up. The INTRC
source will continue to run if either the WDT or the
Fail-Safe Clock Monitor is enabled.
The IRCF bits may be modified at any time to immedi-
ately change the system clock speed. Executing a
SLEEPinstruction is not required to select a new clock
frequency from the INTOSC multiplexer.
FIGURE 3-10:
TIMING TRANSITION TO RC_RUN MODE
Q4 Q1 Q2 Q3 Q4 Q1
Q2
Q3
Q4
Q1
Q2
Q3
1
2
3
4
5
6
7
8
INTRC
OSC1
Clock Transition
CPU
Clock
Peripheral
Clock
Program
Counter
PC
PC + 2
PC + 4
© 2007 Microchip Technology Inc.
DS39605F-page 27
PIC18F1220/1320
3.4.4
EXIT TO IDLE MODE
3.5
Wake from Power Managed Modes
An exit from a power managed Run mode to its
corresponding Idle mode is executed by setting the
IDLEN bit and executing a SLEEPinstruction. The CPU
is halted at the beginning of the instruction following the
SLEEPinstruction. There are no changes to any of the
clock source status bits (OSTS, IOFS or T1RUN).
While the CPU is halted, the peripherals continue to be
clocked from the previously selected clock source.
An exit from any of the power managed modes is trig-
gered by an interrupt, a Reset or a WDT time-out. This
section discusses the triggers that cause exits from
power managed modes. The clocking subsystem
actions are discussed in each of the power managed
modes (see Sections 3.2 through 3.4).
Note:
If application code is timing sensitive, it
should wait for the OSTS bit to become set
before continuing. Use the interval during
the low-power exit sequence (before
OSTS is set) to perform timing insensitive
“housekeeping” tasks.
3.4.5
EXIT TO SLEEP MODE
An exit from a power managed Run mode to Sleep
mode is executed by clearing the IDLEN and
SCS1:SCS0 bits and executing a SLEEP instruction.
The code is no different than the method used to invoke
Sleep mode from the normal operating (full power)
mode.
Device behavior during Low-Power mode exits is
summarized in Table 3-3.
3.5.1
EXIT BY INTERRUPT
The primary clock and internal oscillator block are
disabled. The INTRC will continue to operate if the
WDT is enabled. The Timer1 oscillator will continue to
run, if enabled in the T1CON register (Register 12-1).
All clock source status bits are cleared (OSTS, IOFS
and T1RUN).
Any of the available interrupt sources can cause the
device to exit a power managed mode and resume full
power operation. To enable this functionality, an inter-
rupt source must be enabled by setting its enable bit in
one of the INTCON or PIE registers. The exit sequence
is initiated when the corresponding interrupt flag bit is
set. On all exits from Low-Power mode by interrupt,
code execution branches to the interrupt vector if the
GIE/GIEH bit (INTCON<7>) is set. Otherwise, code
execution continues or resumes without branching
(see Section 9.0 “Interrupts”).
DS39605F-page 28
© 2007 Microchip Technology Inc.
PIC18F1220/1320
TABLE 3-3:
ACTIVITY AND EXIT DELAY ON WAKE FROM SLEEP MODE OR ANY IDLE MODE
(BY CLOCK SOURCES)
Power
Managed
Mode Exit
Delay
Activity during Wake-up from
Power Managed Mode
ClockReady
Status Bit
(OSCCON)
Clock in Power Primary System
Managed Mode
Clock
Exit by Interrupt
Exit by Reset
LP, XT, HS
HSPLL
EC, RC, INTRC(1)
INTOSC(2)
CPU and peripherals Not clocked or
OSTS
Primary System
Clock
(PRI_IDLE mode)
clocked by primary
clock and executing
instructions.
Two-Speed Start-up
(if enabled)(3)
5-10 μs(5)
.
—
IOFS
LP, XT, HS
OST
OST + 2 ms
5-10 μs(5)
1 ms(4)
CPU and peripherals
clocked by selected
power managed mode
clock and executing
instructions until
OSTS
HSPLL
T1OSC or
INTRC(1)
EC, RC, INTRC(1)
INTOSC(2)
—
IOFS
primary clock source
becomes ready.
LP, XT, HS
OST
OSTS
HSPLL
OST + 2 ms
5-10 μs(5)
None
INTOSC(2)
EC, RC, INTRC(1)
INTOSC(2)
—
IOFS
LP, XT, HS
OST
Not clocked or
OSTS
Two-Speed Start-up (if
enabled) until primary
clock source becomes
HSPLL
OST + 2 ms
5-10 μs(5)
1 ms(4)
Sleep mode
EC, RC, INTRC(1)
INTOSC(2)
—
ready(3)
.
IOFS
Note 1: In this instance, refers specifically to the INTRC clock source.
2: Includes both the INTOSC 8 MHz source and postscaler derived frequencies.
3: Two-Speed Start-up is covered in greater detail in Section 19.3 “Two-Speed Start-up”.
4: Execution continues during the INTOSC stabilization period.
5: Required delay when waking from Sleep and all Idle modes. This delay runs concurrently with any other
required delays (see Section 3.3 “Idle Modes”).
© 2007 Microchip Technology Inc.
DS39605F-page 29
PIC18F1220/1320
3.5.2
EXIT BY RESET
3.5.4
EXIT WITHOUT AN OSCILLATOR
START-UP DELAY
Normally, the device is held in Reset by the Oscillator
Start-up Timer (OST) until the primary clock (defined in
Configuration Register 1H) becomes ready. At that
time, the OSTS bit is set and the device begins
executing code.
Certain exits from power managed modes do not
invoke the OST at all. These are:
• PRI_IDLE mode, where the primary clock source
is not stopped; or
Code execution can begin before the primary clock
becomes ready. If either the Two-Speed Start-up (see
Section 19.3 “Two-Speed Start-up”) or Fail-Safe
Clock Monitor (see Section 19.4 “Fail-Safe Clock
Monitor”) are enabled in Configuration Register 1H,
the device may begin execution as soon as the Reset
source has cleared. Execution is clocked by the
INTOSC multiplexer driven by the internal oscillator
block. Since the OSCCON register is cleared following
all Resets, the INTRC clock source is selected. A
higher speed clock may be selected by modifying the
IRCF bits in the OSCCON register. Execution is
clocked by the internal oscillator block until either the
primary clock becomes ready, or a power managed
mode is entered before the primary clock becomes
ready; the primary clock is then shut down.
• the primary clock source is not any of LP, XT, HS
or HSPLL modes.
In these cases, the primary clock source either does
not require an oscillator start-up delay, since it is
already running (PRI_IDLE), or normally does not
require an oscillator start-up delay (RC, EC and INTIO
Oscillator modes).
However, a fixed delay (approximately 10 μs) following
the wake event is required when leaving Sleep and Idle
modes. This delay is required for the CPU to prepare
for execution. Instruction execution resumes on the first
clock cycle following this delay.
3.6
INTOSC Frequency Drift
The factory calibrates the internal oscillator block
output (INTOSC) for 8 MHz (see Table 22-6). However,
this frequency may drift as VDD or temperature
changes, which can affect the controller operation in a
variety of ways.
3.5.3
EXIT BY WDT TIME-OUT
A WDT time-out will cause different actions, depending
on which power managed mode the device is in when
the time-out occurs.
If the device is not executing code (all Idle modes and
Sleep mode), the time-out will result in a wake from the
power managed mode (see Sections 3.2 through 3.4).
It is possible to adjust the INTOSC frequency by
modifying the value in the OSCTUNE register
(Register 2-1). This has the side effect that the INTRC
clock source frequency is also affected. However, the
features that use the INTRC source often do not require
an exact frequency. These features include the Fail-Safe
Clock Monitor, the Watchdog Timer and the RC_RUN/
RC_IDLE modes when the INTRC clock source is
selected.
If the device is executing code (all Run modes), the
time-out will result in a WDT Reset (see Section 19.2
“Watchdog Timer (WDT)”).
The WDT timer and postscaler are cleared by
executing a SLEEPor CLRWDTinstruction, the loss of a
currently selected clock source (if the Fail-Safe Clock
Monitor is enabled) and modifying the IRCF bits in the
OSCCON register if the internal oscillator block is the
system clock source.
Being able to adjust the INTOSC requires knowing
when an adjustment is required, in which direction it
should be made and in some cases, how large a
change is needed. Three examples follow but other
techniques may be used.
DS39605F-page 30
© 2007 Microchip Technology Inc.
PIC18F1220/1320
3.6.1
EXAMPLE – EUSART
3.6.3
EXAMPLE – CCP IN CAPTURE
MODE
An adjustment may be indicated when the EUSART
begins to generate framing errors, or receives data with
errors while in Asynchronous mode. Framing errors
indicate that the system clock frequency is too high –
try decrementing the value in the OSCTUNE register to
reduce the system clock frequency. Errors in data may
suggest that the system clock speed is too low –
increment OSCTUNE.
A CCP module can use free running Timer1 (or
Timer3), clocked by the internal oscillator block and an
external event with a known period (i.e., AC power
frequency). The time of the first event is captured in the
CCPRxH:CCPRxL registers and is recorded for use
later. When the second event causes a capture, the
time of the first event is subtracted from the time of the
second event. Since the period of the external event is
known, the time difference between events can be
calculated.
3.6.2
EXAMPLE – TIMERS
This technique compares system clock speed to some
reference clock. Two timers may be used; one timer is
clocked by the peripheral clock, while the other is
clocked by a fixed reference source, such as the
Timer1 oscillator.
If the measured time is much greater than the
calculated time, the internal oscillator block is running
too fast – decrement OSCTUNE. If the measured time
is much less than the calculated time, the internal
oscillator block is running too slow – increment
OSCTUNE.
Both timers are cleared, but the timer clocked by the
reference generates interrupts. When an interrupt
occurs, the internally clocked timer is read and both
timers are cleared. If the internally clocked timer value
is greater than expected, then the internal oscillator
block is running too fast – decrement OSCTUNE.
© 2007 Microchip Technology Inc.
DS39605F-page 31
PIC18F1220/1320
NOTES:
DS39605F-page 32
© 2007 Microchip Technology Inc.
PIC18F1220/1320
Most registers are not affected by a WDT wake-up,
since this is viewed as the resumption of normal
operation. Status bits from the RCON register
(Register 4-1), RI, TO, PD, POR and BOR, are set or
cleared differently in different Reset situations, as
indicated in Table 4-2. These bits are used in software
to determine the nature of the Reset. See Table 4-3 for
a full description of the Reset states of all registers.
4.0
RESET
The PIC18F1220/1320 devices differentiate between
various kinds of Reset:
a) Power-on Reset (POR)
b) MCLR Reset during normal operation
c) MCLR Reset during Sleep
d) Watchdog Timer (WDT) Reset (during
execution)
A simplified block diagram of the On-Chip Reset Circuit
is shown in Figure 4-1.
e) Programmable Brown-out Reset (BOR)
f) RESETInstruction
The Enhanced MCU devices have a MCLR noise filter
in the MCLR Reset path. The filter will detect and
ignore small pulses.
g) Stack Full Reset
h) Stack Underflow Reset
The MCLR pin is not driven low by any internal Resets,
including the WDT.
Most registers are unaffected by a Reset. Their status
is unknown on POR and unchanged by all other
Resets. The other registers are forced to a “Reset
state”, depending on the type of Reset that occurred.
The MCLR input provided by the MCLR pin can be
disabled with the MCLRE bit in Configuration
Register 3H (CONFIG3H<7>).
FIGURE 4-1:
SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT
RESET
Instruction
Stack
Pointer
Stack Full/Underflow Reset
External Reset
MCLRE
MCLR
( )_IDLE
Sleep
WDT
Time-out
VDD Rise
Detect
POR Pulse
BOR
VDD
Brown-out
Reset
S
OST/PWRT
OST
10-bit Ripple Counter
1024 Cycles
Chip_Reset
R
Q
OSC1
32 μs
65.5 ms
PWRT
11-bit Ripple Counter
INTRC(1)
Enable PWRT
(2)
Enable OST
Note 1: This is a separate oscillator from the RC oscillator of the CLKI pin.
2: See Table 4-1 for time-out situations.
© 2007 Microchip Technology Inc.
DS39605F-page 33
PIC18F1220/1320
4.1
Power-on Reset (POR)
4.3
Oscillator Start-up Timer (OST)
A Power-on Reset pulse is generated on-chip when
VDD rise is detected. To take advantage of the POR
circuitry, just tie the MCLR pin through a resistor (1k to
10 kΩ) to VDD. This will eliminate external RC compo-
nents usually needed to create a Power-on Reset
delay. A minimum rise rate for VDD is specified
(parameter D004). For a slow rise time, see Figure 4-2.
The Oscillator Start-up Timer (OST) provides a 1024
oscillator cycle (from OSC1 input) delay after the
PWRT delay is over (parameter 33). This ensures that
the crystal oscillator or resonator has started and
stabilized.
The OST time-out is invoked only for XT, LP, HS and
HSPLL modes and only on Power-on Reset, or on exit
from most low-power modes.
When the device starts normal operation (i.e., exits the
Reset condition), device operating parameters (volt-
age, frequency, temperature, etc.) must be met to
ensure operation. If these conditions are not met, the
device must be held in Reset until the operating
conditions are met.
4.4
PLL Lock Time-out
With the PLL enabled in its PLL mode, the time-out
sequence following a Power-on Reset is slightly
different from other oscillator modes. A portion of the
Power-up Timer is used to provide a fixed time-out that
is sufficient for the PLL to lock to the main oscillator fre-
quency. This PLL lock time-out (TPLL) is typically 2 ms
and follows the Oscillator Start-up Time-out.
FIGURE 4-2:
EXTERNAL POWER-ON
RESET CIRCUIT (FOR
SLOW VDD POWER-UP)
VDD
VDD
D
4.5
Brown-out Reset (BOR)
A configuration bit, BOR, can disable (if clear/
programmed), or enable (if set) the Brown-out Reset
circuitry. If VDD falls below VBOR (parameter D005) for
greater than TBOR (parameter 35), the brown-out situa-
tion will reset the chip. A Reset may not occur if VDD
falls below VBOR for less than TBOR. The chip will
remain in Brown-out Reset until VDD rises above VBOR.
If the Power-up Timer is enabled, it will be invoked after
VDD rises above VBOR; it then will keep the chip in
Reset for an additional time delay, TPWRT
(parameter 33). If VDD drops below VBOR while the
Power-up Timer is running, the chip will go back into a
Brown-out Reset and the Power-up Timer will be initial-
ized. Once VDD rises above VBOR, the Power-up Timer
will execute the additional time delay. Enabling BOR
Reset does not automatically enable the PWRT.
R
R1
MCLR
PIC18FXXXX
C
Note 1: External Power-on Reset circuit is required
only if the VDD power-up slope is too slow.
The diode D helps discharge the capacitor
quickly when VDD powers down.
2: R < 40 kΩ is recommended to make sure that
the voltage drop across R does not violate
the device’s electrical specification.
3: R1 ≥ 1 kΩ will limit any current flowing into
MCLR from external capacitor C, in the event
of MCLR/VPP pin breakdown due to Electro-
static Discharge (ESD) or Electrical
Overstress (EOS).
4.6
Time-out Sequence
On power-up, the time-out sequence is as follows:
First, after the POR pulse has cleared, PWRT time-out
is invoked (if enabled). Then, the OST is activated. The
total time-out will vary based on oscillator configuration
and the status of the PWRT. For example, in RC mode
with the PWRT disabled, there will be no time-out at all.
Figure 4-3, Figure 4-4, Figure 4-5, Figure 4-6 and
Figure 4-7 depict time-out sequences on power-up.
4.2
Power-up Timer (PWRT)
The Power-up Timer (PWRT) of the PIC18F1220/1320 is
an 11-bit counter, which uses the INTRC source as the
clock input. This yields a count of 2048 x 32 μs = 65.6 ms.
While the PWRT is counting, the device is held in Reset.
The power-up time delay will vary from chip-to-chip due
to VDD, temperature and process variation. See DC
parameter 33 for details.
Since the time-outs occur from the POR pulse, if MCLR
is kept low long enough, all time-outs will expire. Bring-
ing MCLR high will begin execution immediately
(Figure 4-5). This is useful for testing purposes or to
synchronize more than one PIC18FXXXX device
operating in parallel.
The PWRT is enabled by clearing configuration bit,
PWRTEN.
Table 4-2 shows the Reset conditions for some Special
Function Registers, while Table 4-3 shows the Reset
conditions for all the registers.
DS39605F-page 34
© 2007 Microchip Technology Inc.
PIC18F1220/1320
TABLE 4-1:
Oscillator
TIME-OUT IN VARIOUS SITUATIONS
Power-up(2) and Brown-out
PWRTEN = 0 PWRTEN = 1
Exit from
Low-Power Mode
Configuration
HSPLL
66 ms(1) + 1024 TOSC + 2 ms(2)
66 ms(1) + 1024 TOSC
66 ms(1)
1024 TOSC + 2 ms(2)
1024 TOSC
1024 TOSC + 2 ms(2)
1024 TOSC
HS, XT, LP
EC, ECIO
5-10 μs(3)
5-10 μs(3)
RC, RCIO
66 ms(1)
66 ms(1)
5-10 μs(3)
5-10 μs(3)
INTIO1, INTIO2
5-10 μs(3)
5-10 μs(3)
Note 1: 66 ms (65.5 ms) is the nominal Power-up Timer (PWRT) delay.
2: 2 ms is the nominal time required for the 4x PLL to lock.
3: The program memory bias start-up time is always invoked on POR, wake-up from Sleep, or on any exit
from power managed mode that disables the CPU and instruction execution.
REGISTER 4-1:
RCON REGISTER BITS AND POSITIONS
R/W-0
IPEN
U-0
—
U-0
—
R/W-1
RI
R/W-1
TO
R/W-1
PD
R/W-1
POR
R/W-1
BOR
bit 7
Note: Refer to Section 5.14 “RCON Register” for bit definitions.
bit 0
TABLE 4-2:
STATUS BITS, THEIR SIGNIFICANCE AND THE INITIALIZATION CONDITION FOR
RCON REGISTER
Program
Counter
RCON
Register
Condition
RI TO PD POR BOR STKFUL STKUNF
Power-on Reset
RESETInstruction
Brown-out
0000h
0000h
0000h
0000h
0--1 1100
0--0 uuuu
0--1 11u-
0--u 1uuu
1
0
1
u
1
u
1
1
1
u
1
u
0
u
u
u
0
u
0
u
0
u
u
u
0
u
u
u
MCLR during Power Managed
Run modes
MCLR during Power Managed
Idle modes and Sleep
0000h
0000h
0--u 10uu
0--u 0uuu
u
u
1
0
0
u
u
u
u
u
u
u
u
u
u
u
WDT Time-out during Full
Power or Power Managed Run
MCLR during Full Power
Execution
Stack Full Reset (STVR = 1)
0000h
0--u uuuu
u
u
u
u
u
1
u
u
1
Stack Underflow Reset
(STVR = 1)
Stack Underflow Error (not an
actual Reset, STVR = 0)
0000h
PC + 2
PC + 2
u--u uuuu
u--u 00uu
u--u u0uu
u
u
u
u
0
u
u
0
0
u
u
u
u
u
u
u
u
u
1
u
u
WDT Time-out during Power
Managed Idle or Sleep
Interrupt Exit from Power
Managed modes
Legend: u= unchanged, x= unknown, – = unimplemented bit, read as ‘0’
Note 1: When the wake-up is due to an interrupt and the GIEH or GIEL bits are set, the PC is loaded with the
interrupt vector (0x000008h or 0x000018h).
© 2007 Microchip Technology Inc.
DS39605F-page 35
PIC18F1220/1320
TABLE 4-3:
INITIALIZATION CONDITIONS FOR ALL REGISTERS
MCLR Resets
WDT Reset
RESET Instruction
Stack Resets
Applicable
Devices
Power-on Reset,
Brown-out Reset
Wake-up via WDT
or Interrupt
Register
TOSU
1220
1320
1320
1320
1320
1320
1320
1320
1320
1320
1320
1320
1320
1320
1320
1320
1320
1320
1320
1320
1320
1320
1320
1320
1320
1320
1320
1320
1320
1320
1320
1320
---0 0000
0000 0000
0000 0000
00-0 0000
---0 0000
0000 0000
0000 0000
--00 0000
0000 0000
0000 0000
0000 0000
xxxx xxxx
xxxx xxxx
0000 000x
1111 -1-1
11-0 0-00
N/A
---0 0000
0000 0000
0000 0000
00-0 0000
---0 0000
0000 0000
0000 0000
--00 0000
0000 0000
0000 0000
0000 0000
uuuu uuuu
uuuu uuuu
0000 000u
1111 -1-1
11-0 0-00
N/A
---0 uuuu(3)
uuuu uuuu(3)
uuuu uuuu(3)
uu-u uuuu(3)
---u uuuu
uuuu uuuu
PC + 2(2)
--uu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu(1)
uuuu -u-u(1)
uu-u u-uu(1)
N/A
TOSH
1220
1220
1220
1220
1220
1220
1220
1220
1220
1220
1220
1220
1220
1220
1220
1220
1220
1220
1220
1220
1220
1220
1220
1220
1220
1220
1220
1220
1220
1220
TOSL
STKPTR
PCLATU
PCLATH
PCL
TBLPTRU
TBLPTRH
TBLPTRL
TABLAT
PRODH
PRODL
INTCON
INTCON2
INTCON3
INDF0
POSTINC0
POSTDEC0
PREINC0
PLUSW0
FSR0H
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
---- 0000
xxxx xxxx
xxxx xxxx
N/A
---- 0000
uuuu uuuu
uuuu uuuu
N/A
---- uuuu
uuuu uuuu
uuuu uuuu
N/A
FSR0L
WREG
INDF1
POSTINC1
POSTDEC1
PREINC1
PLUSW1
FSR1H
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
---- 0000
xxxx xxxx
---- 0000
uuuu uuuu
---- uuuu
uuuu uuuu
FSR1L
Legend: u= unchanged, x= unknown, -= unimplemented bit, read as ‘0’, q= value depends on condition.
Shaded cells indicate conditions do not apply for the designated device.
Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).
2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the
interrupt vector (0008h or 0018h).
3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are
updated with the current value of the PC. The STKPTR is modified to point to the next location in the
hardware stack.
4: See Table 4-2 for Reset value for specific condition.
5: Bits 6 and 7 of PORTA, LATA and TRISA are enabled, depending on the Oscillator mode selected. When
not enabled as PORTA pins, they are disabled and read ‘0’.
6: Bit 5 of PORTA is enabled if MCLR is disabled.
DS39605F-page 36
© 2007 Microchip Technology Inc.
PIC18F1220/1320
TABLE 4-3:
Register
INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)
MCLR Resets
WDT Reset
Applicable
Devices
Power-on Reset,
Brown-out Reset
Wake-up via WDT
or Interrupt
RESET Instruction
Stack Resets
BSR
1220
1320
1320
1320
1320
1320
1320
1320
1320
1320
1320
1320
1320
1320
1320
1320
1320
1320
1320
1320
1320
1320
1320
1320
1320
1320
1320
1320
1320
1320
1320
1320
1320
---- 0000
N/A
---- 0000
N/A
---- uuuu
N/A
INDF2
1220
1220
1220
1220
1220
1220
1220
1220
1220
1220
1220
1220
1220
1220
1220
1220
1220
1220
1220
1220
1220
1220
1220
1220
1220
1220
1220
1220
1220
1220
1220
POSTINC2
POSTDEC2
PREINC2
PLUSW2
FSR2H
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
---- 0000
xxxx xxxx
---x xxxx
0000 0000
xxxx xxxx
1111 1111
0000 q000
--00 0101
---- ---0
0--1 11q0
xxxx xxxx
xxxx xxxx
0000 0000
0000 0000
1111 1111
-000 0000
xxxx xxxx
xxxx xxxx
00-0 0000
-000 0000
0-00 0000
xxxx xxxx
xxxx xxxx
0000 0000
0000 0000
0000 0000
---- 0000
uuuu uuuu
---u uuuu
0000 0000
uuuu uuuu
1111 1111
0000 q000
--00 0101
---- ---0
0--q qquu
uuuu uuuu
uuuu uuuu
u0uu uuuu
0000 0000
1111 1111
-000 0000
uuuu uuuu
uuuu uuuu
00-0 0000
-000 0000
0-00 0000
uuuu uuuu
uuuu uuuu
0000 0000
0000 0000
0000 0000
---- uuuu
uuuu uuuu
---u uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu qquu
--uu uuuu
---- ---u
u--u qquu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
1111 1111
-uuu uuuu
uuuu uuuu
uuuu uuuu
uu-u uuuu
-uuu uuuu
u-uu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
FSR2L
STATUS
TMR0H
TMR0L
T0CON
OSCCON
LVDCON
WDTCON
RCON(4)
TMR1H
TMR1L
T1CON
TMR2
PR2
T2CON
ADRESH
ADRESL
ADCON0
ADCON1
ADCON2
CCPR1H
CCPR1L
CCP1CON
PWM1CON
ECCPAS
Legend: u= unchanged, x= unknown, -= unimplemented bit, read as ‘0’, q= value depends on condition.
Shaded cells indicate conditions do not apply for the designated device.
Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).
2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the
interrupt vector (0008h or 0018h).
3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are
updated with the current value of the PC. The STKPTR is modified to point to the next location in the
hardware stack.
4: See Table 4-2 for Reset value for specific condition.
5: Bits 6 and 7 of PORTA, LATA and TRISA are enabled, depending on the Oscillator mode selected. When
not enabled as PORTA pins, they are disabled and read ‘0’.
6: Bit 5 of PORTA is enabled if MCLR is disabled.
© 2007 Microchip Technology Inc.
DS39605F-page 37
PIC18F1220/1320
TABLE 4-3:
INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)
MCLR Resets
WDT Reset
RESET Instruction
Stack Resets
Applicable
Devices
Power-on Reset,
Brown-out Reset
Wake-up via WDT
or Interrupt
Register
TMR3H
TMR3L
T3CON
SPBRGH
SPBRG
RCREG
TXREG
TXSTA
RCSTA
BAUDCTL
EEADR
EEDATA
EECON2
EECON1
IPR2
1220
1320
1320
1320
1320
1320
1320
1320
1320
1320
1320
1320
1320
1320
1320
1320
1320
1320
1320
1320
1320
1320
1320
1320
1320
1320
1320
1320
xxxx xxxx
xxxx xxxx
0-00 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0010
0000 000x
-1-1 0-00
0000 0000
0000 0000
0000 0000
xx-0 x000
1--1 -11-
0--0 -00-
0--0 -00-
-111 -111
-000 -000
-000 -000
--00 0000
1111 1111
11-1 1111(5)
xxxx xxxx
xx-x xxxx(5)
xxxx xxxx
xx0x 0000(5,6)
uuuu uuuu
uuuu uuuu
u-uu uuuu
0000 0000
0000 0000
0000 0000
0000 0000
0000 0010
0000 000x
-1-1 0-00
0000 0000
0000 0000
0000 0000
uu-0 u000
1--1 -11-
0--0 -00-
0--0 -00-
-111 -111
-000 -000
-000 -000
--00 0000
1111 1111
11-1 1111(5)
uuuu uuuu
uu-u uuuu(5)
uuuu uuuu
uu0u 0000(5,6)
uuuu uuuu
uuuu uuuu
u-uu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
-u-u u-uu
uuuu uuuu
uuuu uuuu
0000 0000
uu-0 u000
u--u -uu-
u--u -uu-(1)
u--u -uu-
-uuu -uuu
-uuu -uuu(1)
-uuu -uuu
--uu uuuu
uuuu uuuu
uu-u uuuu(5)
uuuu uuuu
uu-u uuuu(5)
uuuu uuuu
uuuu uuuu(5,6)
1220
1220
1220
1220
1220
1220
1220
1220
1220
1220
1220
1220
1220
1220
1220
1220
1220
1220
1220
1220
1220
1220
1220
1220
1220
1220
PIR2
PIE2
IPR1
PIR1
PIE1
OSCTUNE
TRISB
TRISA(5)
LATB
LATA(5)
PORTB
PORTA(5,6)
Legend: u= unchanged, x= unknown, -= unimplemented bit, read as ‘0’, q= value depends on condition.
Shaded cells indicate conditions do not apply for the designated device.
Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).
2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the
interrupt vector (0008h or 0018h).
3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are
updated with the current value of the PC. The STKPTR is modified to point to the next location in the
hardware stack.
4: See Table 4-2 for Reset value for specific condition.
5: Bits 6 and 7 of PORTA, LATA and TRISA are enabled, depending on the Oscillator mode selected. When
not enabled as PORTA pins, they are disabled and read ‘0’.
6: Bit 5 of PORTA is enabled if MCLR is disabled.
DS39605F-page 38
© 2007 Microchip Technology Inc.
PIC18F1220/1320
FIGURE 4-3:
TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD, VDD RISE < TPWRT)
VDD
MCLR
INTERNAL POR
TPWRT
PWRT TIME-OUT
OST TIME-OUT
TOST
INTERNAL RESET
FIGURE 4-4:
TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 1
VDD
MCLR
INTERNAL POR
TPWRT
PWRT TIME-OUT
OST TIME-OUT
TOST
INTERNAL RESET
FIGURE 4-5:
TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 2
VDD
MCLR
INTERNAL POR
TPWRT
PWRT TIME-OUT
OST TIME-OUT
TOST
INTERNAL RESET
© 2007 Microchip Technology Inc.
DS39605F-page 39
PIC18F1220/1320
FIGURE 4-6:
SLOW RISE TIME (MCLR TIED TO VDD, VDD RISE > TPWRT)
5V
1V
0V
VDD
MCLR
INTERNAL POR
TPWRT
PWRT TIME-OUT
TOST
OST TIME-OUT
INTERNAL RESET
FIGURE 4-7:
TIME-OUT SEQUENCE ON POR W/PLL ENABLED (MCLR TIED TO VDD)
VDD
MCLR
INTERNAL POR
TPWRT
PWRT TIME-OUT
OST TIME-OUT
TOST
TPLL
PLL TIME-OUT
INTERNAL RESET
Note:
TOST = 1024 clock cycles.
TPLL ≈ 2 ms max. First three stages of the PWRT timer.
DS39605F-page 40
© 2007 Microchip Technology Inc.
PIC18F1220/1320
5.1
Program Memory Organization
5.0
MEMORY ORGANIZATION
A 21-bit program counter is capable of addressing the
2-Mbyte program memory space. Accessing a location
between the physically implemented memory and the
2-Mbyte address will cause a read of all ‘0’s (a NOP
instruction).
There are three memory types in Enhanced MCU
devices. These memory types are:
• Program Memory
• Data RAM
• Data EEPROM
The PIC18F1220 has 4 Kbytes of Flash memory and
can store up to 2,048 single-word instructions.
Data and program memory use separate busses,
which allows for concurrent access of these types.
The PIC18F1320 has 8 Kbytes of Flash memory and
can store up to 4,096 single-word instructions.
Additional detailed information for Flash program mem-
ory and data EEPROM is provided in Section 6.0
“Flash Program Memory” and Section 7.0 “Data
EEPROM Memory”, respectively.
The Reset vector address is at 0000h and the interrupt
vector addresses are at 0008h and 0018h.
The program memory maps for the PIC18F1220 and
PIC18F1320 devices are shown in Figure 5-1 and
Figure 5-2, respectively.
FIGURE 5-2:
PROGRAM MEMORY MAP
AND STACK FOR
PIC18F1320
FIGURE 5-1:
PROGRAM MEMORY MAP
AND STACK FOR
PIC18F1220
PC<20:0>
PC<20:0>
21
21
CALL,RCALL,RETURN
RETFIE,RETLW
CALL,RCALL,RETURN
RETFIE,RETLW
Stack Level 1
Stack Level 1
•
•
•
•
•
•
Stack Level 31
Reset Vector
Stack Level 31
Reset Vector
0000h
0000h
High Priority Interrupt Vector
Low Priority Interrupt Vector
0008h
0018h
High Priority Interrupt Vector
Low Priority Interrupt Vector
0008h
0018h
On-Chip
Program Memory
On-Chip
Program Memory
0FFFh
1000h
1FFFh
2000h
Read ‘0’
Read ‘0’
1FFFFFh
200000h
1FFFFFh
200000h
© 2007 Microchip Technology Inc.
DS39605F-page 41
PIC18F1220/1320
5.2.2
RETURN STACK POINTER
(STKPTR)
5.2
Return Address Stack
The return address stack allows any combination of up
to 31 program calls and interrupts to occur. The PC
(Program Counter) is pushed onto the stack when a
CALLor RCALLinstruction is executed, or an interrupt
is Acknowledged. The PC value is pulled off the stack
on a RETURN, RETLWor a RETFIEinstruction. PCLATU
and PCLATH are not affected by any of the RETURNor
CALLinstructions.
The STKPTR register (Register 5-1) contains the stack
pointer value, the STKFUL (Stack Full) status bit and
the STKUNF (Stack Underflow) status bits. The value
of the Stack Pointer can be 0 through 31. The Stack
Pointer increments before values are pushed onto the
stack and decrements after values are popped off the
stack. At Reset, the Stack Pointer value will be zero.
The user may read and write the Stack Pointer value.
This feature can be used by a Real-Time Operating
System for return stack maintenance.
The stack operates as a 31-word by 21-bit RAM and a
5-bit stack pointer, with the Stack Pointer initialized to
00000B after all Resets. There is no RAM associated
with Stack Pointer, 00000B. This is only a Reset value.
During a CALLtype instruction, causing a push onto the
stack, the Stack Pointer is first incremented and the
RAM location pointed to by the Stack Pointer
(STKPTR) register is written with the contents of the PC
(already pointing to the instruction following the CALL).
During a RETURNtype instruction, causing a pop from
the stack, the contents of the RAM location pointed to
by the STKPTR are transferred to the PC and then the
Stack Pointer is decremented.
After the PC is pushed onto the stack 31 times (without
popping any values off the stack), the STKFUL bit is
set. The STKFUL bit is cleared by software or by a
POR.
The action that takes place when the stack becomes
full depends on the state of the STVR (Stack Overflow
Reset Enable) configuration bit. (Refer to Section 19.1
“Configuration Bits” for a description of the device
configuration bits.) If STVR is set (default), the 31st
push will push the (PC + 2) value onto the stack, set the
STKFUL bit and reset the device. The STKFUL bit will
remain set and the Stack Pointer will be set to zero.
The stack space is not part of either program or data
space. The Stack Pointer is readable and writable and
the address on the top of the stack is readable and
writable through the top-of-stack Special File
Registers. Data can also be pushed to or popped from
the stack using the top-of-stack SFRs. Status bits
indicate if the stack is full, has overflowed or
underflowed.
If STVR is cleared, the STKFUL bit will be set on the
31st push and the Stack Pointer will increment to 31.
Any additional pushes will not overwrite the 31st push
and STKPTR will remain at 31.
When the stack has been popped enough times to
unload the stack, the next pop will return a value of zero
to the PC and sets the STKUNF bit, while the Stack
Pointer remains at zero. The STKUNF bit will remain
set until cleared by software or a POR occurs.
5.2.1
TOP-OF-STACK ACCESS
The top of the stack is readable and writable. Three
register locations, TOSU, TOSH and TOSL, hold the
contents of the stack location pointed to by the
STKPTR register (Figure 5-3). This allows users to
implement a software stack if necessary. After a CALL,
RCALLor interrupt, the software can read the pushed
value by reading the TOSU, TOSH and TOSL registers.
These values can be placed on a user defined software
stack. At return time, the software can replace the
TOSU, TOSH and TOSL and do a return.
Note:
Returning a value of zero to the PC on an
underflow has the effect of vectoring the
program to the Reset vector, where the
stack conditions can be verified and
appropriate actions can be taken. This is
not the same as a Reset, as the contents
of the SFRs are not affected.
The user must disable the global interrupt enable bits
while accessing the stack to prevent inadvertent stack
corruption.
FIGURE 5-3:
RETURN ADDRESS STACK AND ASSOCIATED REGISTERS
Return Address Stack
11111
11110
11101
STKPTR<4:0>
TOSU
00h
TOSH
1Ah
TOSL
34h
00010
00011
001A34h 00010
000D58h 00001
00000
Top-of-Stack
DS39605F-page 42
© 2007 Microchip Technology Inc.
PIC18F1220/1320
REGISTER 5-1:
STKPTR REGISTER
R/C-0 R/C-0
U-0
—
R/W-0
SP4
R/W-0
SP3
R/W-0
SP2
R/W-0
SP1
R/W-0
SP0
STKFUL STKUNF
bit 7
bit 0
bit 7(1)
bit 6(1)
STKFUL: Stack Full Flag bit
1= Stack became full or overflowed
0= Stack has not become full or overflowed
STKUNF: Stack Underflow Flag bit
1= Stack underflow occurred
0= Stack underflow did not occur
bit 5
Unimplemented: Read as ‘0’
bit 4-0
SP4:SP0: Stack Pointer Location bits
Note 1: Bit 7 and bit 6 are cleared by user software or by a POR.
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented
‘0’ = Bit is cleared
C = Clearable only bit
x = Bit is unknown
5.2.3
PUSH AND POP INSTRUCTIONS
5.2.4
STACK FULL/UNDERFLOW RESETS
Since the Top-of-Stack (TOS) is readable and writable,
the ability to push values onto the stack and pull values
off the stack, without disturbing normal program execu-
tion, is a desirable option. To push the current PC value
onto the stack, a PUSH instruction can be executed.
This will increment the Stack Pointer and load the cur-
rent PC value onto the stack. TOSU, TOSH and TOSL
can then be modified to place data or a return address
on the stack.
These Resets are enabled by programming the STVR
bit in Configuration Register 4L. When the STVR bit is
cleared, a full or underflow condition will set the appro-
priate STKFUL or STKUNF bit, but not cause a device
Reset. When the STVR bit is set, a full or underflow
condition will set the appropriate STKFUL or STKUNF
bit and then cause a device Reset. The STKFUL or
STKUNF bits are cleared by the user software or a
Power-on Reset.
The ability to pull the TOS value off of the stack and
replace it with the value that was previously pushed
onto the stack, without disturbing normal execution, is
achieved by using the POPinstruction. The POPinstruc-
tion discards the current TOS by decrementing the
Stack Pointer. The previous value pushed onto the
stack then becomes the TOS value.
© 2007 Microchip Technology Inc.
DS39605F-page 43
PIC18F1220/1320
5.3
Fast Register Stack
5.4
PCL, PCLATH and PCLATU
A “fast return” option is available for interrupts. A fast
register stack is provided for the Status, WREG and
BSR registers and is only one in depth. The stack is not
readable or writable and is loaded with the current
value of the corresponding register when the processor
vectors for an interrupt. The values in the registers are
then loaded back into the working registers, if the
RETFIE, FAST instruction is used to return from the
interrupt.
The Program Counter (PC) specifies the address of the
instruction to fetch for execution. The PC is 21-bits
wide. The low byte, known as the PCL register, is both
readable and writable. The high byte, or PCH register,
contains the PC<15:8> bits and is not directly readable
or writable. Updates to the PCH register may be per-
formed through the PCLATH register. The upper byte is
called PCU. This register contains the PC<20:16> bits
and is not directly readable or writable. Updates to the
PCU register may be performed through the PCLATU
register.
All interrupt sources will push values into the stack
registers. If both low and high priority interrupts are
enabled, the stack registers cannot be used reliably to
return from low priority interrupts. If a high priority inter-
rupt occurs while servicing a low priority interrupt, the
stack register values stored by the low priority interrupt
will be overwritten. Users must save the key registers
in software during a low priority interrupt.
The contents of PCLATH and PCLATU will be
transferred to the program counter by any operation
that writes PCL. Similarly, the upper two bytes of the
program counter will be transferred to PCLATH and
PCLATU by an operation that reads PCL. This is useful
for computed offsets to the PC (see Section 5.8.1
“Computed GOTO”).
If interrupt priority is not used, all interrupts may use the
fast register stack for returns from interrupt.
The PC addresses bytes in the program memory. To
prevent the PC from becoming misaligned with word
instructions, the LSB of PCL is fixed to a value of ‘0’.
The PC increments by 2 to address sequential
instructions in the program memory.
If no interrupts are used, the fast register stack can be
used to restore the Status, WREG and BSR registers at
the end of a subroutine call. To use the fast register
stack for a subroutine call, a CALL LABEL, FAST
instruction must be executed to save the Status,
WREG and BSR registers to the fast register stack. A
RETURN, FASTinstruction is then executed to restore
these registers from the fast register stack.
The CALL, RCALL, GOTOand program branch instruc-
tions write to the program counter directly. For these
instructions, the contents of PCLATH and PCLATU are
not transferred to the program counter.
Example 5-1 shows a source code example that uses
the fast register stack during a subroutine call and
return.
EXAMPLE 5-1:
FAST REGISTER STACK
CODE EXAMPLE
CALL SUB1, FAST
;STATUS, WREG, BSR
;SAVED IN FAST REGISTER
;STACK
•
•
SUB1
•
•
RETURN, FAST
;RESTORE VALUES SAVED
;IN FAST REGISTER STACK
DS39605F-page 44
© 2007 Microchip Technology Inc.
PIC18F1220/1320
5.5
Clocking Scheme/Instruction
Cycle
5.6
Instruction Flow/Pipelining
An “Instruction Cycle” consists of four Q cycles (Q1,
Q2, Q3 and Q4). The instruction fetch and execute are
pipelined such that fetch takes one instruction cycle,
while decode and execute takes another instruction
cycle. However, due to the pipelining, each instruction
effectively executes in one cycle. If an instruction
causes the program counter to change (e.g., GOTO),
then two cycles are required to complete the instruction
(Example 5-2).
The clock input (from OSC1) is internally divided by
four to generate four non-overlapping quadrature
clocks, namely Q1, Q2, Q3 and Q4. Internally, the
Program Counter (PC) is incremented every Q1, the
instruction is fetched from the program memory and
latched into the instruction register in Q4. The instruc-
tion is decoded and executed during the following Q1
through Q4. The clocks and instruction execution flow
are shown in Figure 5-4.
A fetch cycle begins with the Program Counter (PC)
incrementing in Q1.
In the execution cycle, the fetched instruction is latched
into the “Instruction Register” (IR) in cycle Q1. This
instruction is then decoded and executed during the
Q2, Q3 and Q4 cycles. Data memory is read during Q2
(operand read) and written during Q4 (destination
write).
FIGURE 5-4:
CLOCK/INSTRUCTION CYCLE
Q2
Q3
Q4
Q2
Q3
Q4
Q2
Q3
Q4
Q1
Q1
Q1
OSC1
Q1
Q2
Q3
Internal
Phase
Clock
Q4
PC
PC
PC + 2
PC + 4
OSC2/CLKO
(RC Mode)
Execute INST (PC – 2)
Fetch INST (PC)
Execute INST (PC)
Fetch INST (PC + 2)
Execute INST (PC + 2)
Fetch INST (PC + 4)
EXAMPLE 5-2:
INSTRUCTION PIPELINE FLOW
TCY0
TCY1
TCY2
TCY3
TCY4
TCY5
1. MOVLW 55h
2. MOVWF PORTB
3. BRA SUB_1
Fetch 1
Execute 1
Fetch 2
Execute 2
Fetch 3
Execute 3
Fetch 4
4. BSF
PORTA, BIT3 (Forced NOP)
Flush (NOP)
5. Instruction @ address SUB_1
Fetch SUB_1 Execute SUB_1
All instructions are single cycle, except for any program branches. These take two cycles, since the fetch instruction
is “flushed” from the pipeline, while the new instruction is being fetched and then executed.
© 2007 Microchip Technology Inc.
DS39605F-page 45
PIC18F1220/1320
The CALL and GOTO instructions have the absolute
program memory address embedded into the instruc-
tion. Since instructions are always stored on word
boundaries, the data contained in the instruction is a
word address. The word address is written to
PC<20:1>, which accesses the desired byte address in
program memory. Instruction #2 in Figure 5-5 shows
how the instruction ‘GOTO 000006h’ is encoded in the
program memory. Program branch instructions, which
encode a relative address offset, operate in the same
manner. The offset value stored in a branch instruction
represents the number of single-word instructions that
the PC will be offset by. Section 20.0 “Instruction Set
Summary” provides further details of the instruction
set.
5.7
Instructions in Program Memory
The program memory is addressed in bytes. Instruc-
tions are stored as two bytes or four bytes in program
memory. The Least Significant Byte of an instruction
word is always stored in a program memory location
with an even address (LSB = 0). Figure 5-5 shows an
example of how instruction words are stored in the pro-
gram memory. To maintain alignment with instruction
boundaries, the PC increments in steps of 2 and the
LSB will always read ‘0’ (see Section 5.4 “PCL,
PCLATH and PCLATU”).
FIGURE 5-5:
INSTRUCTIONS IN PROGRAM MEMORY
Word Address
LSB = 1
LSB = 0
↓
Program Memory
Byte Locations →
000000h
000002h
000004h
000006h
000008h
00000Ah
00000Ch
00000Eh
000010h
000012h
000014h
Instruction 1:
Instruction 2:
0Fh
EFh
F0h
C1h
F4h
55h
03h
00h
23h
56h
MOVLW
GOTO
055h
000006h
Instruction 3:
MOVFF
123h, 456h
instruction is executed by itself (first word was skipped),
it will execute as a NOP. This action is necessary when
the two-word instruction is preceded by a conditional
instruction that results in a skip operation. A program
example that demonstrates this concept is shown in
Example 5-3. Refer to Section 20.0 “Instruction Set
Summary” for further details of the instruction set.
5.7.1
TWO-WORD INSTRUCTIONS
PIC18F1220/1320 devices have four two-word
instructions: MOVFF, CALL, GOTOand LFSR. The second
word of these instructions has the 4 MSBs set to ‘1’s and
is decoded as a NOPinstruction. The lower 12 bits of the
second word contain data to be used by the instruction.
If the first word of the instruction is executed, the data in
the second word is accessed. If the second word of the
EXAMPLE 5-3:
TWO-WORD INSTRUCTIONS
CASE 1:
Object Code
Source Code
0110 0110 0000 0000 TSTFSZ
1100 0001 0010 0011 MOVFF
1111 0100 0101 0110
REG1
; is RAM location 0?
REG1, REG2 ; No, skip this word
; Execute this word as a NOP
; continue code
0010 0100 0000 0000 ADDWF
REG3
CASE 2:
Object Code
Source Code
0110 0110 0000 0000 TSTFSZ
1100 0001 0010 0011 MOVFF
1111 0100 0101 0110
REG1
; is RAM location 0?
REG1, REG2 ; Yes, execute this word
; 2nd word of instruction
0010 0100 0000 0000 ADDWF
REG3
; continue code
DS39605F-page 46
© 2007 Microchip Technology Inc.
PIC18F1220/1320
5.8
Look-up Tables
5.9
Data Memory Organization
Look-up tables are implemented two ways:
The data memory is implemented as static RAM. Each
register in the data memory has a 12-bit address,
allowing up to 4096 bytes of data memory. Figure 5-6
shows the data memory organization for the
PIC18F1220/1320 devices.
• Computed GOTO
• Table Reads
5.8.1
COMPUTED GOTO
The data memory map is divided into as many as
16 banks that contain 256 bytes each. The lower 4 bits
of the Bank Select Register (BSR<3:0>) select which
bank will be accessed. The upper 4 bits for the BSR are
not implemented.
A computed GOTOis accomplished by adding an offset
to the program counter (see Example 5-4).
A look-up table can be formed with an ADDWF PCL
instruction and a group of RETLW 0xnn instructions.
WREG is loaded with an offset into the table before
executing a call to that table. The first instruction of the
called routine is the ADDWF PCLinstruction. The next
instruction executed will be one of the RETLW 0xnn
instructions, that returns the value 0xnnto the calling
function.
The data memory contains Special Function Registers
(SFR) and General Purpose Registers (GPR). The
SFRs are used for control and status of the controller
and peripheral functions, while GPRs are used for data
storage and scratch pad operations in the user’s appli-
cation. The SFRs start at the last location of Bank 15
(FFFh) and extend towards F80h. Any remaining space
beyond the SFRs in the Bank may be implemented as
GPRs. GPRs start at the first location of Bank 0 and
grow upwards. Any read of an unimplemented location
will read as ‘0’s.
The offset value (in WREG) specifies the number of
bytes that the program counter should advance and
should be multiples of 2 (LSB = 0).
In this method, only one data byte may be stored in
each instruction location and room on the return
address stack is required.
The entire data memory may be accessed directly or
indirectly. Direct addressing may require the use of the
BSR register. Indirect addressing requires the use of a
File Select Register (FSRn) and a corresponding Indi-
rect File Operand (INDFn). Each FSR holds a 12-bit
address value that can be used to access any location
in the Data Memory map without banking. See
Section 5.12 “Indirect Addressing, INDF and FSR
Registers” for indirect addressing details.
EXAMPLE 5-4:
COMPUTED GOTO USING
AN OFFSET VALUE
MOVFW
CALL
OFFSET
TABLE
ORG
TABLE
0xnn00
ADDWF
RETLW
RETLW
RETLW
.
PCL
0xnn
0xnn
0xnn
The instruction set and architecture allow operations
across all banks. This may be accomplished by indirect
addressing or by the use of the MOVFFinstruction. The
MOVFF instruction is a two-word/two-cycle instruction
that moves a value from one register to another.
.
.
To ensure that commonly used registers (SFRs and
select GPRs) can be accessed in a single cycle,
regardless of the current BSR values, an Access Bank
is implemented. A segment of Bank 0 and a segment of
Bank 15 comprise the Access RAM. Section 5.10
“Access Bank” provides a detailed description of the
Access RAM.
5.8.2
TABLE READS/TABLE WRITES
A better method of storing data in program memory
allows two bytes of data to be stored in each instruction
location.
Look-up table data may be stored two bytes per pro-
gram word by using table reads and writes. The Table
Pointer (TBLPTR) register specifies the byte address
and the Table Latch (TABLAT) register contains the
data that is read from or written to program memory.
Data is transferred to/from program memory, one byte
at a time.
5.9.1
GENERAL PURPOSE
REGISTER FILE
Enhanced MCU devices may have banked memory in
the GPR area. GPRs are not initialized by a Power-on
Reset and are unchanged on all other Resets.
The table read/table write operation is discussed
further in Section 6.1 “Table Reads and Table
Writes”.
Data RAM is available for use as GPR registers by all
instructions. The second half of Bank 15 (F80h to
FFFh) contains SFRs. All other banks of data memory
contain GPRs, starting with Bank 0.
© 2007 Microchip Technology Inc.
DS39605F-page 47
PIC18F1220/1320
FIGURE 5-6:
DATA MEMORY MAP FOR PIC18F1220/1320 DEVICES
BSR<3:0>
Data Memory Map
000h
07Fh
080h
0FFh
00h
FFh
Access RAM
GPR
= 0000
Bank 0
Access Bank
00h
Access RAM Low
7Fh
80h
= 0001
= 1110
Access RAM High
(SFRs)
Bank 1
to
Bank 14
Unused
Read ‘00h’
FFh
When a = 0,
The BSR is ignored and the
Access Bank is used.
The first 128 bytes are
General Purpose RAM
(from Bank 0).
EFFh
F00h
F7Fh
F80h
FFFh
00h
FFh
Unused
SFR
= 1111
The second 128 bytes are
Special Function Registers
(from Bank 15).
Bank 15
When a = 1,
The BSR specifies the Bank
used by the instruction.
DS39605F-page 48
© 2007 Microchip Technology Inc.
PIC18F1220/1320
The SFRs can be classified into two sets: those asso-
ciated with the “core” function and those related to the
peripheral functions. Those registers related to the
“core” are described in this section, while those related
to the operation of the peripheral features are
described in the section of that peripheral feature.
5.9.2
SPECIAL FUNCTION REGISTERS
The Special Function Registers (SFRs) are registers
used by the CPU and peripheral modules for controlling
the desired operation of the device. These registers are
implemented as static RAM. A list of these registers is
given in Table 5-1 and Table 5-2.
The SFRs are typically distributed among the peripherals
whose functions they control.
The unused SFR locations will be unimplemented and
read as ‘0’s.
TABLE 5-1:
Address
FFFh
SPECIAL FUNCTION REGISTER MAP FOR PIC18F1220/1320 DEVICES
Name
TOSU
Address
Name
INDF2(2)
Address
FBFh
FBEh
FBDh
FBCh
FBBh
FBAh
FB9h
Name
Address
F9Fh
F9Eh
F9Dh
F9Ch
F9Bh
F9Ah
F99h
F98h
F97h
F96h
F95h
F94h
F93h
F92h
F91h
F90h
F8Fh
F8Eh
F8Dh
F8Ch
F8Bh
F8Ah
F89h
F88h
F87h
F86h
F85h
F84h
F83h
F82h
F81h
F80h
Name
IPR1
PIR1
PIE1
—
FDFh
CCPR1H
FFEh
FFDh
FFCh
FFBh
FFAh
TOSH
FDEh POSTINC2(2)
FDDh POSTDEC2(2)
FDCh PREINC2(2)
FDBh PLUSW2(2)
CCPR1L
TOSL
CCP1CON
STKPTR
PCLATU
PCLATH
PCL
—
—
—
—
—
OSCTUNE
—
FDAh
FD9h
FD8h
FD7h
FD6h
FD5h
FD4h
FD3h
FD2h
FD1h
FD0h
FCFh
FCEh
FCDh
FCCh
FCBh
FCAh
FC9h
FC8h
FC7h
FC6h
FC5h
FC4h
FC3h
FC2h
FC1h
FC0h
FSR2H
FSR2L
STATUS
TMR0H
TMR0L
T0CON
—
FF9h
—
FF8h
TBLPTRU
TBLPTRH
TBLPTRL
TABLAT
PRODH
PRODL
INTCON
INTCON2
INTCON3
INDF0(2)
FB8h
—
FF7h
FB7h PWM1CON
—
FF6h
FB6h
FB5h
FB4h
FB3h
FB2h
FB1h
FB0h
FAFh
FAEh
FADh
FACh
FABh
FAAh
FA9h
FA8h
FA7h
FA6h
FA5h
FA4h
FA3h
FA2h
FA1h
FA0h
ECCPAS
—
—
FF5h
—
FF4h
—
—
FF3h
OSCCON
LVDCON
WDTCON
RCON
TMR1H
TMR1L
T1CON
TMR2
TMR3H
TMR3L
T3CON
SPBRGH
SPBRG
RCREG
TXREG
TXSTA
RCSTA
BAUDCTL
EEADR
EEDATA
EECON2
EECON1
—
TRISB
TRISA
—
FF2h
FF1h
FF0h
—
FEFh
—
FEEh POSTINC0(2)
FEDh POSTDEC0(2)
FECh PREINC0(2)
FEBh PLUSW0(2)
—
—
—
PR2
—
FEAh
FE9h
FE8h
FE7h
FE6h POSTINC1(2)
FE5h POSTDEC1(2)
FE4h PREINC1(2)
FE3h PLUSW1(2)
FSR0H
FSR0L
WREG
INDF1(2)
T2CON
—
LATB
LATA
—
—
—
—
—
—
—
—
ADRESH
ADRESL
ADCON0
ADCON1
ADCON2
—
—
—
—
FE2h
FE1h
FE0h
FSR1H
FSR1L
BSR
IPR2
—
PIR2
PORTB
PORTA
PIE2
Note 1: Unimplemented registers are read as ‘0’.
2: This is not a physical register.
© 2007 Microchip Technology Inc.
DS39605F-page 49
PIC18F1220/1320
TABLE 5-2:
File Name
TOSU
REGISTER FILE SUMMARY (PIC18F1220/1320)
Value on
POR, BOR
Details on
page:
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
—
—
—
Top-of-Stack Upper Byte (TOS<20:16>)
---0 0000
0000 0000
0000 0000
00-0 0000
---0 0000
0000 0000
0000 0000
--00 0000
0000 0000
0000 0000
0000 0000
xxxx xxxx
xxxx xxxx
0000 000x
1111 -1-1
11-0 0-00
N/A
36, 42
36, 42
36, 42
36, 43
36, 44
36, 44
36, 44
36, 60
36, 60
36, 60
36, 60
36, 71
36, 71
36, 75
36, 76
36, 77
36, 53
36, 53
36, 53
36, 53
36, 53
36, 53
36, 53
36
TOSH
Top-of-Stack High Byte (TOS<15:8>)
Top-of-Stack Low Byte (TOS<7:0>)
TOSL
STKPTR
PCLATU
PCLATH
PCL
STKFUL
—
STKUNF
—
—
bit 21(3)
Return Stack Pointer
Holding Register for PC<20:16>
Holding Register for PC<15:8>
PC Low Byte (PC<7:0>)
TBLPTRU
TBLPTRH
TBLPTRL
TABLAT
PRODH
PRODL
INTCON
INTCON2
INTCON3
INDF0
—
—
bit 21
Program Memory Table Pointer Upper Byte (TBLPTR<20:16>)
Program Memory Table Pointer High Byte (TBLPTR<15:8>)
Program Memory Table Pointer Low Byte (TBLPTR<7:0>)
Program Memory Table Latch
Product Register High Byte
Product Register Low Byte
GIE/GIEH PEIE/GIEL
TMR0IE
INTEDG1
—
INT0IE
INTEDG2
INT2IE
RBIE
—
TMR0IF
TMR0IP
—
INT0IF
—
RBIF
RBIP
RBPU
INTEDG0
INT1IP
INT2IP
INT1IE
INT2IF
INT1IF
Uses contents of FSR0 to address data memory – value of FSR0 not changed (not a physical register)
Uses contents of FSR0 to address data memory – value of FSR0 post-incremented (not a physical register)
POSTINC0
N/A
POSTDEC0 Uses contents of FSR0 to address data memory– value of FSR0 post-decremented (not a physical register)
N/A
PREINC0
PLUSW0
FSR0H
Uses contents of FSR0 to address data memory – value of FSR0 pre-incremented (not a physical register)
Uses contents of FSR0 to address data memory – value of FSR0 offset by W (not a physical register)
N/A
N/A
—
—
—
—
Indirect Data Memory Address Pointer 0 High
---- 0000
xxxx xxxx
xxxx xxxx
N/A
FSR0L
Indirect Data Memory Address Pointer 0 Low Byte
Working Register
WREG
INDF1
Uses contents of FSR1 to address data memory – value of FSR1 not changed (not a physical register)
Uses contents of FSR1 to address data memory – value of FSR1 post-incremented (not a physical register)
36, 53
36, 53
36, 53
36, 53
36, 53
36, 53
36, 53
37, 52
37, 53
37, 53
37, 53
37, 53
37, 53
37, 53
37, 53
37, 55
37, 101
37, 101
37, 99
37, 17
37, 167
37, 180
POSTINC1
N/A
POSTDEC1 Uses contents of FSR1 to address data memory – value of FSR1 post-decremented (not a physical register)
N/A
PREINC1
PLUSW1
FSR1H
FSR1L
Uses contents of FSR1 to address data memory – value of FSR1 pre-incremented (not a physical register)
Uses contents of FSR1 to address data memory – value of FSR1 offset by W (not a physical register)
N/A
N/A
—
—
—
—
Indirect Data Memory Address Pointer 1 High
---- 0000
xxxx xxxx
---- 0000
N/A
Indirect Data Memory Address Pointer 1 Low Byte
BSR
—
—
—
—
Bank Select Register
INDF2
Uses contents of FSR2 to address data memory – value of FSR2 not changed (not a physical register)
Uses contents of FSR2 to address data memory – value of FSR2 post-incremented (not a physical register)
POSTINC2
N/A
POSTDEC2 Uses contents of FSR2 to address data memory – value of FSR2 post-decremented (not a physical register)
N/A
PREINC2
PLUSW2
FSR2H
Uses contents of FSR2 to address data memory – value of FSR2 pre-incremented (not a physical register)
Uses contents of FSR2 to address data memory – value of FSR2 offset by W (not a physical register)
N/A
N/A
—
—
—
—
Indirect Data Memory Address Pointer 2 High
---- 0000
xxxx xxxx
---x xxxx
0000 0000
xxxx xxxx
1111 1111
0000 q000
--00 0101
--- ---0
FSR2L
Indirect Data Memory Address Pointer 2 Low Byte
STATUS
TMR0H
—
—
—
N
OV
Z
DC
C
Timer0 Register High Byte
Timer0 Register Low Byte
TMR0L
T0CON
TMR0ON
IDLEN
—
T08BIT
IRCF2
—
T0CS
IRCF1
IVRST
—
T0SE
IRCF0
LVDEN
—
PSA
OSTS
LVDL3
—
T0PS2
IOFS
LVDL2
—
T0PS1
SCS1
LVDL1
—
T0PS0
SCS0
OSCCON
LVDCON
WDTCON
LVDL0
—
—
SWDTEN
RCON
IPEN
—
—
RI
TO
PD
POR
BOR
0--1 11q0 35, 56, 84
Legend: x= unknown, u= unchanged, – = unimplemented, q= value depends on condition
Note 1: RA6 and associated bits are configured as port pins in RCIO, ECIO and INTIO2 (with port function on RA6) Oscillator mode only and read ‘0’
in all other oscillator modes.
2: RA7 and associated bits are configured as port pins in INTIO2 Oscillator mode only and read ‘0’ in all other modes.
3: Bit 21 of the PC is only available in Test mode and Serial Programming modes.
4: The RA5 port bit is only available when MCLRE fuse (CONFIG3H<7>) is programmed to ‘0’. Otherwise, RA5 reads ‘0’. This bit is read-only.
DS39605F-page 50
© 2007 Microchip Technology Inc.
PIC18F1220/1320
TABLE 5-2:
REGISTER FILE SUMMARY (PIC18F1220/1320) (CONTINUED)
Value on
POR, BOR
Details on
page:
File Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
TMR1H
TMR1L
Timer1 Register High Byte
Timer1 Register Low Byte
xxxx xxxx
xxxx xxxx
0000 0000
0000 0000
1111 1111
37, 108
37, 108
37, 103
37, 109
37, 109
37, 109
37, 164
37, 164
37, 155
37, 156
37, 157
37. 116
37, 116
37, 115
37, 126
37, 127
38, 113
38, 113
38, 111
38
T1CON
RD16
T1RUN
T1CKPS1
T1CKPS0 T1OSCEN
T1SYNC
TMR2ON
TMR1CS
T2CKPS1
TMR1ON
TMR2
Timer2 Register
PR2
Timer2 Period Register
TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0
T2CON
—
T2CKPS0 -000 0000
xxxx xxxx
ADRESH
ADRESL
ADCON0
ADCON1
ADCON2
CCPR1H
CCPR1L
CCP1CON
PWM1CON
ECCPAS
TMR3H
TMR3L
A/D Result Register High Byte
A/D Result Register Low Byte
xxxx xxxx
VCFG1
—
VCFG0
PCFG6
—
—
CHS2
PCFG4
ACQT1
CHS1
PCFG3
ACQT0
CHS0
PCFG2
ADCS2
GO/DONE
PCFG1
ADON
PCFG0
ADCS0
00-0 0000
-000 0000
0-00 0000
xxxx xxxx
xxxx xxxx
0000 0000
0000 0000
0000 0000
xxxx xxxx
xxxx xxxx
0-00 0000
0000 0000
0000 0000
0000 0000
PCFG5
ACQT2
ADFM
ADCS1
Capture/Compare/PWM Register 1 High Byte
Capture/Compare/PWM Register 1 Low Byte
P1M1
P1M0
PDC6
DC1B1
PDC5
DC1B0
PDC4
CCP1M3
PDC3
CCP1M2
PDC2
CCP1M1
PDC1
CCP1M0
PDC0
PRSEN
ECCPASE ECCPAS2 ECCPAS1 ECCPAS0
Timer3 Register High Byte
PSSAC1
PSSAC0
PSSBD1
PSSBD0
Timer3 Register Low Byte
T3CON
RD16
—
T3CKPS1
T3CKPS0
T3CCP1
T3SYNC
TMR3CS
TMR3ON
SPBRGH
SPBRG
RCREG
EUSART Baud Rate Generator High Byte
EUSART Baud Rate Generator Low Byte
EUSART Receive Register
38, 135
38, 143,
142
TXREG
EUSART Transmit Register
0000 0000
38, 140,
142
TXSTA
RCSTA
BAUDCTL
EEADR
EEDATA
EECON2
EECON1
IPR2
CSRC
SPEN
—
TX9
RX9
TXEN
SREN
—
SYNC
CREN
SCKP
SENDB
ADDEN
BRG16
BRGH
FERR
—
TRMT
OERR
WUE
TX9D
RX9D
0000 0010
0000 000x
-1-1 0-00
0000 0000
0000 0000
38, 132
38, 133
38
RCIDL
ABDEN
EEPROM Address Register
EEPROM Data Register
38, 67
38, 70
EEPROM Control Register 2 (not a physical register)
0000 0000 38, 58, 67
xx-0 x000 38, 59, 68
EEPGD
OSCFIP
OSCFIF
OSCFIE
—
CFGS
—
—
—
FREE
EEIP
EEIF
EEIE
TXIP
TXIF
TXIE
TUN4
WRERR
—
WREN
LVDIP
WR
RD
—
TMR3IP
TMR3IF
TMR3IE
TMR2IP
TMR2IF
TMR2IE
TUN1
1--1 -11-
0--0 -00-
0--0 -00-
-111 -111
-000 -000
-000 -000
--00 0000
1111 1111
11-1 1111
xxxx xxxx
xx-x xxxx
xxxx xxxx
xx0x 0000
38, 83
38, 79
38, 81
38, 82
38, 78
38, 80
38, 15
38, 98
38, 89
38, 98
38, 89
38, 98
38, 89
PIR2
—
—
—
LVDIF
—
PIE2
—
—
—
LVDIE
—
IPR1
ADIP
ADIF
ADIE
—
RCIP
RCIF
RCIE
TUN5
—
CCP1IP
CCP1IF
CCP1IE
TUN2
TMR1IP
TMR1IF
TMR1IE
TUN0
PIR1
—
—
PIE1
—
—
OSCTUNE
TRISB
TRISA
LATB
—
TUN3
Data Direction Control Register for PORTB
TRISA7(2)
TRISA6(1)
—
Data Direction Control Register for PORTA
Read/Write PORTB Data Latch
LATA<7>(2) LATA<6>(1)
LATA
—
Read/Write PORTA Data Latch
PORTB
PORTA
Read PORTB pins, Write PORTB Data Latch
RA7(2) RA6(1) RA5(4)
Read PORTA pins, Write PORTA Data Latch
Legend: x= unknown, u= unchanged, – = unimplemented, q= value depends on condition
Note 1: RA6 and associated bits are configured as port pins in RCIO, ECIO and INTIO2 (with port function on RA6) Oscillator mode only and read ‘0’
in all other oscillator modes.
2: RA7 and associated bits are configured as port pins in INTIO2 Oscillator mode only and read ‘0’ in all other modes.
3: Bit 21 of the PC is only available in Test mode and Serial Programming modes.
4: The RA5 port bit is only available when MCLRE fuse (CONFIG3H<7>) is programmed to ‘0’. Otherwise, RA5 reads ‘0’. This bit is read-only.
© 2007 Microchip Technology Inc.
DS39605F-page 51
PIC18F1220/1320
5.10
Access Bank
5.11 Bank Select Register (BSR)
The Access Bank is an architectural enhancement
which is very useful for C compiler code optimization.
The techniques used by the C compiler may also be
useful for programs written in assembly.
The need for a large general purpose memory space
dictates a RAM banking scheme. The data memory is
partitioned into as many as sixteen banks. When using
direct addressing, the BSR should be configured for the
desired bank.
This data memory region can be used for:
BSR<3:0> holds the upper 4 bits of the 12-bit RAM
address. The BSR<7:4> bits will always read ‘0’s and
writes will have no effect (see Figure 5-7).
• Intermediate computational values
• Local variables of subroutines
• Faster context saving/switching of variables
• Common variables
A MOVLBinstruction has been provided in the instruction
set to assist in selecting banks.
• Faster evaluation/control of SFRs (no banking)
If the currently selected bank is not implemented, any
read will return all ‘0’s and all writes are ignored. The
Status register bits will be set/cleared as appropriate for
the instruction performed.
The Access Bank is comprised of the last 128 bytes in
Bank 15 (SFRs) and the first 128 bytes in Bank 0.
These two sections will be referred to as Access RAM
High and Access RAM Low, respectively. Figure 5-6
indicates the Access RAM areas.
Each Bank extends up to FFh (256 bytes). All data
memory is implemented as static RAM.
A bit in the instruction word specifies if the operation is
to occur in the bank specified by the BSR register or in
the Access Bank. This bit is denoted as the ‘a’ bit (for
access bit).
A MOVFFinstruction ignores the BSR, since the 12-bit
addresses are embedded into the instruction word.
Section 5.12 “Indirect Addressing, INDF and FSR
Registers” provides a description of indirect address-
ing, which allows linear addressing of the entire RAM
space.
When forced in the Access Bank (a = 0), the last
address in Access RAM Low is followed by the first
address in Access RAM High. Access RAM High maps
the Special Function Registers, so these registers can
be accessed without any software overhead. This is
useful for testing status flags and modifying control bits.
FIGURE 5-7:
DIRECT ADDRESSING
Direct Addressing
(3)
From Opcode
BSR<7:4>
BSR<3:0>
7
0
0
0
0
0
(2)
(3)
Bank Select
Location Select
00h
01h
100h
0Eh
E00h
0Fh
F00h
000h
Data
Memory(1)
0FFh
1FFh
EFFh
FFFh
Bank 0
Bank 1
Bank 14 Bank 15
Note 1: For register file map detail, see Table 5-1.
2: The access bit of the instruction can be used to force an override of the selected bank (BSR<3:0>) to the registers
of the Access Bank.
3: The MOVFFinstruction embeds the entire 12-bit address in the instruction.
DS39605F-page 52
© 2007 Microchip Technology Inc.
PIC18F1220/1320
If INDF0, INDF1 or INDF2 are read indirectly via an
FSR, all ‘0’s are read (zero bit is set). Similarly, if
INDF0, INDF1 or INDF2 are written to indirectly, the
operation will be equivalent to a NOPinstruction and the
Status bits are not affected.
5.12 Indirect Addressing, INDF and
FSR Registers
Indirect addressing is a mode of addressing data mem-
ory, where the data memory address in the instruction
is not fixed. An FSR register is used as a pointer to the
data memory location that is to be read or written. Since
this pointer is in RAM, the contents can be modified by
the program. This can be useful for data tables in the
data memory and for software stacks. Figure 5-8
shows how the fetched instruction is modified prior to
being executed.
5.12.1
INDIRECT ADDRESSING
OPERATION
Each FSR register has an INDF register associated with
it, plus four additional register addresses. Performing an
operation using one of these five registers determines
how the FSR will be modified during indirect addressing.
Indirect addressing is possible by using one of the
INDF registers. Any instruction, using the INDF regis-
ter, actually accesses the register pointed to by the File
Select Register, FSR. Reading the INDF register itself,
indirectly (FSR = 0), will read 00h. Writing to the INDF
register indirectly, results in a no operation (NOP). The
FSR register contains a 12-bit address, which is shown
in Figure 5-9.
When data access is performed using one of the five
INDFn locations, the address selected will configure
the FSRn register to:
• Do nothing to FSRn after an indirect access (no
change) – INDFn
• Auto-decrement FSRn after an indirect access
(post-decrement) – POSTDECn
• Auto-increment FSRn after an indirect access
(post-increment) – POSTINCn
The INDFn register is not a physical register. Address-
ing INDFn actually addresses the register whose
address is contained in the FSRn register (FSRn is a
pointer). This is indirect addressing.
• Auto-increment FSRn before an indirect access
(pre-increment) – PREINCn
• Use the value in the WREG register as an offset
to FSRn. Do not modify the value of the WREG or
the FSRn register after an indirect access (no
change) – PLUSWn
Example 5-5 shows a simple use of indirect addressing
to clear the RAM in Bank 1 (locations 100h-1FFh) in a
minimum number of instructions.
EXAMPLE 5-5:
HOW TO CLEAR RAM
(BANK 1) USING
INDIRECT ADDRESSING
When using the auto-increment or auto-decrement
features, the effect on the FSR is not reflected in the
Status register. For example, if the indirect address
causes the FSR to equal ‘0’, the Z bit will not be set.
LFSR
FSR0,0x100
POSTINC0
;
NEXT
CLRF
; Clear INDF
; register then
; inc pointer
; All done with
; Bank1?
Auto-incrementing or auto-decrementing an FSR affects
all 12 bits. That is, when FSRnL overflows from an
increment, FSRnH will be incremented automatically.
BTFSS FSR0H, 1
Adding these features allows the FSRn to be used as a
stack pointer, in addition to its uses for table operations
in data memory.
GOTO
CONTINUE
NEXT
; NO, clear next
; YES, continue
Each FSR has an address associated with it that
performs an indexed indirect access. When a data
access to this INDFn location (PLUSWn) occurs, the
FSRn is configured to add the signed value in the
WREG register and the value in FSR to form the
address before an indirect access. The FSR value is
not changed. The WREG offset range is -128 to +127.
There are three indirect addressing registers. To
address the entire data memory space (4096 bytes),
these registers are 12-bit wide. To store the 12 bits of
addressing information, two 8-bit registers are required:
1. FSR0: composed of FSR0H:FSR0L
2. FSR1: composed of FSR1H:FSR1L
3. FSR2: composed of FSR2H:FSR2L
If an FSR register contains a value that points to one of
the INDFn, an indirect read will read 00h (zero bit is
set), while an indirect write will be equivalent to a NOP
(Status bits are not affected).
In addition, there are registers INDF0, INDF1 and
INDF2, which are not physically implemented. Reading
or writing to these registers activates indirect address-
ing, with the value in the corresponding FSR register
being the address of the data. If an instruction writes a
value to INDF0, the value will be written to the address
pointed to by FSR0H:FSR0L. A read from INDF1 reads
the data from the address pointed to by
FSR1H:FSR1L. INDFn can be used in code anywhere
an operand can be used.
If an indirect addressing write is performed when the tar-
get address is an FSRnH or FSRnL register, the data is
written to the FSR register, but no pre- or post-increment/
decrement is performed.
© 2007 Microchip Technology Inc.
DS39605F-page 53
PIC18F1220/1320
FIGURE 5-8:
INDIRECT ADDRESSING OPERATION
0h
RAM
Instruction
Executed
Opcode
Address
12
FFFh
File Address = Access of an Indirect Addressing Register
BSR<3:0>
12
12
Instruction
Fetched
4
8
Opcode
File
FSR
FIGURE 5-9:
INDIRECT ADDRESSING
Indirect Addressing
FSRnH:FSRnL
3
0
7
0
0
11
Location Select
0000h
Data
Memory(1)
0FFFh
Note 1: For register file map detail, see Table 5-1.
DS39605F-page 54
© 2007 Microchip Technology Inc.
PIC18F1220/1320
It is recommended that only BCF, BSF, SWAPF, MOVFF
and MOVWFinstructions are used to alter the Status reg-
ister, because these instructions do not affect the Z, C,
DC, OV or N bits in the Status register.
5.13 Status Register
The Status register, shown in Register 5-2, contains the
arithmetic status of the ALU. As with any other SFR, it
can be the operand for any instruction.
For other instructions that do not affect Status bits, see
the instruction set summaries in Table 20-1.
If the Status register is the destination for an instruction
that affects the Z, DC, C, OV or N bits, the results of the
instruction are not written; instead, the status is
updated according to the instruction performed. There-
fore, the result of an instruction with the Status register
as its destination may be different than intended. As an
example, CLRFSTATUSwill set the Z bit and leave the
remaining Status bits unchanged (‘000u u1uu’).
Note:
The C and DC bits operate as the borrow
and digit borrow bits, respectively, in
subtraction.
REGISTER 5-2:
STATUS REGISTER
U-0
—
U-0
—
U-0
—
R/W-x
R/W-x
OV
R/W-x
Z
R/W-x
DC
R/W-x
C
N
bit 7
bit 0
bit 7-5
bit 4
Unimplemented: Read as ‘0’
N: Negative bit
This bit is used for signed arithmetic (2’s complement). It indicates whether the result was
negative (ALU MSB = 1).
1= Result was negative
0= Result was positive
bit 3
OV: Overflow bit
This bit is used for signed arithmetic (2’s complement). It indicates an overflow of the
7-bit magnitude, which causes the sign bit (bit 7) to change state.
1= Overflow occurred for signed arithmetic (in this arithmetic operation)
0= No overflow occurred
bit 2
bit 1
Z: Zero bit
1= The result of an arithmetic or logic operation is zero
0= The result of an arithmetic or logic operation is not zero
DC: Digit carry/borrow bit
For ADDWF, ADDLW, SUBLWand SUBWFinstructions:
1= A carry-out from the 4th low-order bit of the result occurred
0= No carry-out from the 4th low-order bit of the result
Note:
For borrow, the polarity is reversed. A subtraction is executed by adding the
2’s complement of the second operand. For rotate (RRF, RLF) instructions, this bit
is loaded with either the bit 4 or bit 3 of the source register.
bit 0
C: Carry/borrow bit
For ADDWF, ADDLW, SUBLWand SUBWFinstructions:
1= A carry-out from the Most Significant bit of the result occurred
0= No carry-out from the Most Significant bit of the result occurred
Note:
For borrow, the polarity is reversed. A subtraction is executed by adding the
2’s complement of the second operand. For rotate (RRF, RLF) instructions, this bit
is loaded with either the high or low-order bit of the source register.
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
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5.14 RCON Register
Note 1: If the BOR configuration bit is set (Brown-
out Reset enabled), the BOR bit is ‘1’ on
a Power-on Reset. After a Brown-out
Reset has occurred, the BOR bit will be
cleared and must be set by firmware to
indicate the occurrence of the next
Brown-out Reset.
The Reset Control (RCON) register contains flag bits
that allow differentiation between the sources of a
device Reset. These flags include the TO, PD, POR,
BOR and RI bits. This register is readable and writable.
2: It is recommended that the POR bit be set
after
a Power-on Reset has been
detected, so that subsequent Power-on
Resets may be detected.
REGISTER 5-3:
RCON REGISTER
R/W-0
IPEN
U-0
—
U-0
—
R/W-1
RI
R-1
TO
R-1
PD
R/W-0
POR
R/W-0
BOR
bit 7
bit 0
bit 7
IPEN: Interrupt Priority Enable bit
1= Enable priority levels on interrupts
0= Disable priority levels on interrupts (PIC16CXXX Compatibility mode)
bit 6-5 Unimplemented: Read as ‘0’
bit 4
RI: RESETInstruction Flag bit
1= The RESETinstruction was not executed (set by firmware only)
0= The RESETinstruction was executed causing a device Reset
(must be set in software after a Brown-out Reset occurs)
bit 3
bit 2
bit 1
bit 0
TO: Watchdog Time-out Flag bit
1= Set by power-up, CLRWDTinstruction or SLEEPinstruction
0= A WDT time-out occurred
PD: Power-down Detection Flag bit
1= Set by power-up or by the CLRWDTinstruction
0= Cleared by execution of the SLEEPinstruction
POR: Power-on Reset Status bit
1= A Power-on Reset has not occurred (set by firmware only)
0= A Power-on Reset occurred (must be set in software after a Power-on Reset occurs)
BOR: Brown-out Reset Status bit
1= A Brown-out Reset has not occurred (set by firmware only)
0= A Brown-out Reset occurred (must be set in software after a Brown-out Reset occurs)
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
DS39605F-page 56
© 2007 Microchip Technology Inc.
PIC18F1220/1320
The program memory space is 16 bits wide, while the
data RAM space is 8 bits wide. Table reads and table
writes move data between these two memory spaces
through an 8-bit register (TABLAT).
6.0
FLASH PROGRAM MEMORY
The Flash program memory is readable, writable and
erasable during normal operation over the entire VDD
range.
Table read operations retrieve data from program
memory and place it into TABLAT in the data RAM
space. Figure 6-1 shows the operation of a table read
with program memory and data RAM.
A read from program memory is executed on one byte
at a time. A write to program memory is executed on
blocks of 8 bytes at a time. Program memory is erased
in blocks of 64 bytes at a time. A “Bulk Erase” operation
may not be issued from user code.
Table write operations store data from TABLAT in the
data memory space into holding registers in program
memory. The procedure to write the contents of the
holding registers into program memory is detailed in
Section 6.5 “Writing to Flash Program Memory”.
Figure 6-2 shows the operation of a table write with
program memory and data RAM.
While writing or erasing program memory, instruction
fetches cease until the operation is complete. The
program memory cannot be accessed during the write
or erase, therefore, code cannot execute. An internal
programming timer terminates program memory writes
and erases.
Table operations work with byte entities. A table block
containing data, rather than program instructions, is not
required to be word aligned. Therefore, a table block
can start and end at any byte address. If a table write is
being used to write executable code into program
memory, program instructions will need to be word
aligned (TBLPTRL<0> = 0).
A value written to program memory does not need to be
a valid instruction. Executing a program memory
location that forms an invalid instruction results in a
NOP.
6.1
Table Reads and Table Writes
The EEPROM on-chip timer controls the write and
erase times. The write and erase voltages are gener-
ated by an on-chip charge pump rated to operate over
the voltage range of the device for byte or word
operations.
In order to read and write program memory, there are
two operations that allow the processor to move bytes
between the program memory space and the data
RAM:
• Table Read (TBLRD)
• Table Write (TBLWT)
FIGURE 6-1:
TABLE READ OPERATION
Instruction: TBLRD*
Program Memory
(1)
Table Pointer
Table Latch (8-bit)
TABLAT
TBLPTRU TBLPTRH TBLPTRL
Program Memory
(TBLPTR)
Note 1: Table Pointer points to a byte in program memory.
© 2007 Microchip Technology Inc.
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FIGURE 6-2:
TABLE WRITE OPERATION
Instruction: TBLWT*
Program Memory
Holding Registers
(1)
Table Pointer
Table Latch (8-bit)
TABLAT
TBLPTRU TBLPTRH TBLPTRL
Program Memory
(TBLPTR)
Note 1: Table Pointer actually points to one of eight holding registers, the address of which is determined by
TBLPTRL<2:0>. The process for physically writing data to the program memory array is discussed
in Section 6.5 “Writing to Flash Program Memory”.
The WREN bit enables and disables erase and write
operations. When set, erase and write operations are
allowed. When clear, erase and write operations are
disabled – the WR bit cannot be set while the WREN bit
is clear. This process helps to prevent accidental writes
to memory due to errant (unexpected) code execution.
6.2
Control Registers
Several control registers are used in conjunction with
the TBLRDand TBLWTinstructions. These include the:
• EECON1 register
• EECON2 register
• TABLAT register
• TBLPTR registers
Firmware should keep the WREN bit clear at all times,
except when starting erase or write operations. Once
firmware has set the WR bit, the WREN bit may be
cleared. Clearing the WREN bit will not affect the
operation in progress.
6.2.1
EECON1 AND EECON2 REGISTERS
EECON1 is the control register for memory accesses.
The WRERR bit is set when a write operation is
interrupted by a Reset. In these situations, the user can
check the WRERR bit and rewrite the location. It will be
necessary to reload the data and address registers
(EEDATA and EEADR) as these registers have cleared
as a result of the Reset.
EECON2 is not a physical register. Reading EECON2
will read all ‘0’s. The EECON2 register is used
exclusively in the memory write and erase sequences.
Control bit, EEPGD, determines if the access will be to
program or data EEPROM memory. When clear,
operations will access the data EEPROM memory.
When set, program memory is accessed.
Control bits, RD and WR, start read and erase/write
operations, respectively. These bits are set by firmware
and cleared by hardware at the completion of the
operation.
Control bit, CFGS, determines if the access will be to
the configuration registers, or to program memory/data
EEPROM memory. When set, subsequent operations
access configuration registers. When CFGS is clear,
the EEPGD bit selects either program Flash or data
EEPROM memory.
The RD bit cannot be set when accessing program
memory (EEPGD = 1). Program memory is read using
table read instructions. See Section 6.3 “Reading the
Flash Program Memory” regarding table reads.
The FREE bit controls program memory erase opera-
tions. When the FREE bit is set, the erase operation is
initiated on the next WR command. When FREE is
clear, only writes are enabled.
Note:
Interrupt flag bit, EEIF in the PIR2 register,
is set when the write is complete. It must
be cleared in software.
DS39605F-page 58
© 2007 Microchip Technology Inc.
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REGISTER 6-1:
EECON1 REGISTER
R/W-x
R/W-x
CFGS
U-0
—
R/W-0
FREE
R/W-x
R/W-0
WREN
R/S-0
WR
R/S-0
RD
EEPGD
WRERR
bit 7
bit 0
bit 7
bit 6
EEPGD: Flash Program or Data EEPROM Memory Select bit
1= Access program Flash memory
0= Access data EEPROM memory
CFGS: Flash Program/Data EE or Configuration Select bit
1= Access configuration registers
0= Access program Flash or data EEPROM memory
bit 5
bit 4
Unimplemented: Read as ‘0’
FREE: Flash Row Erase Enable bit
1= Erase the program memory row addressed by TBLPTR on the next WR command
(cleared by completion of erase operation – TBLPTR<5:0> are ignored)
0= Perform write only
bit 3
WRERR: EEPROM Error Flag bit
1= A write operation was prematurely terminated (any Reset during self-timed programming)
0= The write operation completed normally
Note:
When a WRERR occurs, the EEPGD and CFGS bits are not cleared. This allows
tracing of the error condition.
bit 2
bit 1
WREN: Write Enable bit
1= Allows erase or write cycles
0= Inhibits erase or write cycles
WR: Write Control bit
1= Initiates a data EEPROM erase/write cycle or a program memory erase cycle or write cycle.
(The operation is self-timed and the bit is cleared by hardware once write is complete. The
WR bit can only be set (not cleared) in software.)
0= Write cycle completed
bit 0
RD: Read Control bit
1= Initiates a memory read
(Read takes one cycle. RD is cleared in hardware. The RD bit can only be set (not cleared)
in software. RD bit cannot be set when EEPGD = 1.)
0= Read completed
Legend:
R = Readable bit
W = Writable bit
x = Bit is unknown
S = Settable only
-n = Value at POR
U = Unimplemented bit, read as ‘0’
‘1’ = Bit is set ‘0’ = Bit is cleared
© 2007 Microchip Technology Inc.
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6.2.2
TABLAT – TABLE LATCH REGISTER
6.2.4
TABLE POINTER BOUNDARIES
The Table Latch (TABLAT) is an 8-bit register mapped
into the SFR space. The table latch is used to hold 8-bit
data during data transfers between program memory
and data RAM.
TBLPTR is used in reads, writes and erases of the
Flash program memory.
When a TBLRD is executed, all 22 bits of the Table
Pointer determine which byte is read from program or
configuration memory into TABLAT.
6.2.3
TBLPTR – TABLE POINTER
REGISTER
When a TBLWTis executed, the three LSbs of the Table
Pointer (TBLPTR<2:0>) determine which of the eight
program memory holding registers is written to. When
the timed write to program memory (long write) begins,
the 19 MSbs of the Table Pointer (TBLPTR<21:3>) will
determine which program memory block of 8 bytes is
written to (TBLPTR<2:0> are ignored). For more detail,
see Section 6.5 “Writing to Flash Program Memory”.
The Table Pointer (TBLPTR) addresses a byte within
the program memory. The TBLPTR is comprised of
three SFR registers: Table Pointer Upper Byte, Table
Pointer High Byte and Table Pointer Low Byte
(TBLPTRU:TBLPTRH:TBLPTRL). These three regis-
ters join to form a 22-bit wide pointer. The low-order
21 bits allow the device to address up to 2 Mbytes of
program memory space. Setting the 22nd bit allows
access to the device ID, the user ID and the
configuration bits.
When an erase of program memory is executed, the
16 MSbs of the Table Pointer (TBLPTR<21:6>) point to
the 64-byte block that will be erased. The Least
Significant bits (TBLPTR<5:0>) are ignored.
The Table Pointer (TBLPTR) register is used by the
TBLRDand TBLWTinstructions. These instructions can
update the TBLPTR in one of four ways based on the
table operation. These operations are shown in
Table 6-1. These operations on the TBLPTR only affect
the low-order 21 bits.
Figure 6-3 describes the relevant boundaries of
TBLPTR based on Flash program memory operations.
TABLE 6-1:
Example
TABLE POINTER OPERATIONS WITH TBLRD AND TBLWT INSTRUCTIONS
Operation on Table Pointer
TBLRD*
TBLWT*
TBLPTR is not modified
TBLRD*+
TBLWT*+
TBLPTR is incremented after the read/write
TBLPTR is decremented after the read/write
TBLPTR is incremented before the read/write
TBLRD*-
TBLWT*-
TBLRD+*
TBLWT+*
FIGURE 6-3:
TABLE POINTER BOUNDARIES BASED ON OPERATION
21
16 15
TBLPTRH
8
7
TBLPTRL
0
TBLPTRU
ERASE – TBLPTR<21:6>
LONG WRITE – TBLPTR<21:3>
READ or WRITE – TBLPTR<21:0>
DS39605F-page 60
© 2007 Microchip Technology Inc.
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The internal program memory is typically organized by
words. The Least Significant bit of the address selects
between the high and low bytes of the word. Figure 6-4
shows the interface between the internal program
memory and the TABLAT.
6.3
Reading the Flash Program
Memory
The TBLRD instruction is used to retrieve data from
program memory and place it into data RAM. Table
reads from program memory are performed one byte at
a time.
TBLPTR points to a byte address in program space.
Executing a TBLRDinstruction places the byte pointed
to into TABLAT. In addition, TBLPTR can be modified
automatically for the next table read operation.
FIGURE 6-4:
READS FROM FLASH PROGRAM MEMORY
Program Memory
Odd (High) Byte
Even (Low) Byte
TBLPTR
TBLPTR
LSB = 0
LSB = 1
Instruction Register
(IR)
TABLAT
Read Register
EXAMPLE 6-1:
READING A FLASH PROGRAM MEMORY WORD
MOVLW
MOVWF
MOVLW
MOVWF
MOVLW
MOVWF
CODE_ADDR_UPPER
TBLPTRU
CODE_ADDR_HIGH
TBLPTRH
CODE_ADDR_LOW
TBLPTRL
; Load TBLPTR with the base
; address of the word
READ_WORD
TBLRD*+
MOVFW
; read into TABLAT and increment TBLPTR
; get data
TABLAT
MOVWF
WORD_EVEN
TBLRD*+
MOVFW
; read into TABLAT and increment TBLPTR
; get data
TABLAT
MOVWF
WORD_ODD
© 2007 Microchip Technology Inc.
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6.4.1
FLASH PROGRAM MEMORY
ERASE SEQUENCE
6.4
Erasing Flash Program Memory
The minimum erase block size is 32 words or 64 bytes
under firmware control. Only through the use of an
external programmer, or through ICSP control, can
larger blocks of program memory be bulk erased. Word
erase in Flash memory is not supported.
The sequence of events for erasing a block of internal
program memory location is:
1. Load Table Pointer with address of row being
erased.
When initiating an erase sequence from the micro-
controller itself, a block of 64 bytes of program memory
is erased. The Most Significant 16 bits of the
TBLPTR<21:6> point to the block being erased.
TBLPTR<5:0> are ignored.
2. Set the EECON1 register for the erase operation:
• set EEPGD bit to point to program memory;
• clear the CFGS bit to access program
memory;
• set WREN bit to enable writes;
• set FREE bit to enable the erase.
3. Disable interrupts.
The EECON1 register commands the erase operation.
The EEPGD bit must be set to point to the Flash
program memory. The CFGS bit must be clear to
access program Flash and data EEPROM memory.
The WREN bit must be set to enable write operations.
The FREE bit is set to select an erase operation. The
WR bit is set as part of the required instruction
sequence (as shown in Example 6-2) and starts the
actual erase operation. It is not necessary to load the
TABLAT register with any data as it is ignored.
4. Write 55h to EECON2.
5. Write AAh to EECON2.
6. Set the WR bit. This will begin the row erase
cycle.
7. The CPU will stall for duration of the erase
(about 2 ms using internal timer).
8. Execute a NOP.
For protection, the write initiate sequence using
EECON2 must be used.
9. Re-enable interrupts.
A long write is necessary for erasing the internal Flash.
Instruction execution is halted while in a long write
cycle. The long write will be terminated by the internal
programming timer.
EXAMPLE 6-2:
ERASING A FLASH PROGRAM MEMORY ROW
MOVLW
MOVWF
MOVLW
MOVWF
MOVLW
MOVWF
CODE_ADDR_UPPER
TBLPTRU
CODE_ADDR_HIGH
TBLPTRH
CODE_ADDR_LOW
TBLPTRL
; load TBLPTR with the base
; address of the memory block
ERASE_ROW
BSF
BSF
BSF
BCF
MOVLW
MOVWF
MOVLW
MOVWF
BSF
EECON1, EEPGD
EECON1, WREN
EECON1, FREE
INTCON, GIE
55h
EECON2
AAh
EECON2
EECON1, WR
; point to FLASH program memory
; enable write to memory
; enable Row Erase operation
; disable interrupts
; write 55H
Required
Sequence
; write AAH
; start erase (CPU stall)
NOP
BSF
INTCON, GIE
; re-enable interrupts
DS39605F-page 62
© 2007 Microchip Technology Inc.
PIC18F1220/1320
Since the Table Latch (TABLAT) is only a single byte,
the TBLWT instruction must be executed 8 times for
each programming operation. All of the table write
operations will essentially be short writes, because only
the holding registers are written. At the end of updating
8 registers, the EECON1 register must be written to, to
start the programming operation with a long write.
6.5
Writing to Flash Program Memory
The programming block size is 4 words or 8 bytes.
Word or byte programming is not supported.
Table writes are used internally to load the holding
registers needed to program the Flash memory. There
are 8 holding registers used by the table writes for
programming.
The long write is necessary for programming the
internal Flash. Instruction execution is halted while in a
long write cycle. The long write will be terminated by
the internal programming timer.
FIGURE 6-5:
TABLE WRITES TO FLASH PROGRAM MEMORY
TABLAT
Write Register
8
8
8
8
TBLPTR = xxxxx0
TBLPTR = xxxxx2
TBLPTR = xxxxx7
Holding Register
TBLPTR = xxxxx1
Holding Register
Holding Register
Holding Register
Program Memory
8. Disable interrupts.
6.5.1
FLASH PROGRAM MEMORY WRITE
SEQUENCE
9. Write 55h to EECON2.
10. Write AAh to EECON2.
The sequence of events for programming an internal
program memory location should be:
11. Set the WR bit. This will begin the write cycle.
12. The CPU will stall for duration of the write (about
2 ms using internal timer).
1. Read 64 bytes into RAM.
2. Update data values in RAM as necessary.
3. Load Table Pointer with address being erased.
13. Execute a NOP.
14. Re-enable interrupts.
4. Do the row erase procedure (see Section 6.4.1
“Flash Program Memory Erase Sequence”).
15. Repeat steps 6-14 seven times to write
64 bytes.
5. Load Table Pointer with address of first byte
being written.
16. Verify the memory (table read).
6. Write the first 8 bytes into the holding registers
with auto-increment.
This procedure will require about 18 ms to update one
row of 64 bytes of memory. An example of the required
code is given in Example 6-3.
7. Set the EECON1 register for the write operation:
• set EEPGD bit to point to program memory;
• clear the CFGS bit to access program
memory;
• set WREN bit to enable byte writes.
© 2007 Microchip Technology Inc.
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EXAMPLE 6-3:
WRITING TO FLASH PROGRAM MEMORY
MOVLW
D'64
; number of bytes in erase block
MOVWF
MOVLW
MOVWF
MOVLW
MOVWF
MOVLW
MOVWF
MOVLW
MOVWF
MOVLW
MOVWF
COUNTER
BUFFER_ADDR_HIGH
FSR0H
BUFFER_ADDR_LOW
FSR0L
CODE_ADDR_UPPER
TBLPTRU
CODE_ADDR_HIGH
TBLPTRH
CODE_ADDR_LOW
TBLPTRL
; point to buffer
; Load TBLPTR with the base
; address of the memory block
; 6 LSB = 0
READ_BLOCK
TBLRD*+
MOVF
MOVWF
; read into TABLAT, and inc
; get data
; store data and increment FSR0
; done?
TABLAT, W
POSTINC0
DECFSZ COUNTER
GOTO
READ_BLOCK
; repeat
MODIFY_WORD
MOVLW
MOVWF
MOVLW
MOVWF
MOVLW
MOVWF
MOVLW
MOVWF
DATA_ADDR_HIGH
FSR0H
DATA_ADDR_LOW
FSR0L
NEW_DATA_LOW
POSTINC0
NEW_DATA_HIGH
INDF0
; point to buffer
; update buffer word and increment FSR0
; update buffer word
ERASE_BLOCK
MOVLW
MOVWF
MOVLW
MOVWF
MOVLW
MOVWF
BCF
BSF
BSF
BSF
BCF
MOVLW
MOVWF
MOVLW
MOVWF
BSF
CODE_ADDR_UPPER
TBLPTRU
CODE_ADDR_HIGH
TBLPTRH
CODE_ADDR_LOW
TBLPTRL
EECON1, CFGS
EECON1, EEPGD
EECON1, WREN
EECON1, FREE
INTCON, GIE
55h
; load TBLPTR with the base
; address of the memory block
; 6 LSB = 0
; point to PROG/EEPROM memory
; point to FLASH program memory
; enable write to memory
; enable Row Erase operation
; disable interrupts
; Required sequence
; write 55H
EECON2
AAh
EECON2
EECON1, WR
; write AAH
; start erase (CPU stall)
NOP
BSF
INTCON, GIE
; re-enable interrupts
WRITE_BUFFER_BACK
MOVLW
8
; number of write buffer groups of 8 bytes
; point to buffer
MOVWF
MOVLW
MOVWF
COUNTER_HI
BUFFER_ADDR_HIGH
FSR0H
MOVLW
MOVWF
BUFFER_ADDR_LOW
FSR0L
PROGRAM_LOOP
MOVLW
8
; number of bytes in holding register
MOVWF
COUNTER
DS39605F-page 64
© 2007 Microchip Technology Inc.
PIC18F1220/1320
EXAMPLE 6-3:
WRITING TO FLASH PROGRAM MEMORY (CONTINUED)
WRITE_WORD_TO_HREGS
MOVF
MOVWF
TBLWT+*
POSTINC0, W
TABLAT
; get low byte of buffer data and increment FSR0
; present data to table latch
; short write
; to internal TBLWT holding register, increment
TBLPTR
DECFSZ COUNTER
; loop until buffers are full
GOTO
PROGRAM_MEMORY
WRITE_WORD_TO_HREGS
BCF
INTCON, GIE
55h
EECON2
AAh
EECON2
EECON1, WR
; disable interrupts
; required sequence
; write 55H
MOVLW
MOVWF
MOVLW
MOVWF
BSF
; write AAH
; start program (CPU stall)
NOP
BSF
INTCON, GIE
; re-enable interrupts
; loop until done
DECFSZ COUNTER_HI
GOTO PROGRAM_LOOP
BCF
EECON1, WREN
; disable write to memory
6.5.2
WRITE VERIFY
6.6
Flash Program Operation During
Code Protection
Depending on the application, good programming
practice may dictate that the value written to the mem-
ory should be verified against the original value. This
should be used in applications where excessive writes
can stress bits near the specification limit.
See Section 19.0 “Special Features of the CPU” for
details on code protection of Flash program memory.
6.5.3
UNEXPECTED TERMINATION OF
WRITE OPERATION
If a write is terminated by an unplanned event, such as
loss of power or an unexpected Reset, the memory
location just programmed should be verified and repro-
grammed if needed. The WRERR bit is set when a
write operation is interrupted by a MCLR Reset, or a
WDT Time-out Reset during normal operation. In these
situations, users can check the WRERR bit and rewrite
the location.
TABLE 6-2:
Name
REGISTERS ASSOCIATED WITH PROGRAM FLASH MEMORY
Value on
Value on:
POR, BOR
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
all other
Resets
TBLPTRU
—
—
bit 21 Program Memory Table Pointer Upper Byte (TBLPTR<20:16>) --00 0000 --00 0000
TBPLTRH Program Memory Table Pointer High Byte (TBLPTR<15:8>)
TBLPTRL Program Memory Table Pointer High Byte (TBLPTR<7:0>)
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 000x 0000 000u
TABLAT
INTCON GIE/GIEH PEIE/GIEL TMR0IE
EECON2 EEPROM Control Register 2 (not a physical register)
Program Memory Table Latch
INTE
RBIE
TMR0IF
INTF
RBIF
—
—
EECON1
IPR2
EEPGD
OSCFIP
OSCFIF
OSCFIE
CFGS
—
—
—
—
—
FREE
EEIP
EEIF
EEIE
WRERR
WREN
LVDIP
LVDIF
LVDIE
WR
RD
—
xx-0 x000 uu-0 u000
1--1 -11- 1--1 -11-
0--0 -00- 0--0 -00-
0--0 -00- 0--0 -00-
—
—
—
TMR3IP
TMR3IF
TMR3IE
PIR2
—
—
PIE2
—
—
Legend:
x= unknown, u= unchanged, – = unimplemented, read as ‘0’.
Shaded cells are not used during Flash/EEPROM access.
© 2007 Microchip Technology Inc.
DS39605F-page 65
PIC18F1220/1320
NOTES:
DS39605F-page 66
© 2007 Microchip Technology Inc.
PIC18F1220/1320
Control bit, CFGS, determines if the access will be to
the configuration registers or to program memory/data
EEPROM memory. When set, subsequent operations
access configuration registers. When CFGS is clear,
the EEPGD bit selects either program Flash or data
EEPROM memory.
7.0
DATA EEPROM MEMORY
The data EEPROM is readable and writable during
normal operation over the entire VDD range. The data
memory is not directly mapped in the register file
space. Instead, it is indirectly addressed through the
Special Function Registers (SFR).
The WREN bit enables and disables erase and write
operations. When set, erase and write operations are
allowed. When clear, erase and write operations are
disabled – the WR bit cannot be set while the WREN bit
is clear. This mechanism helps to prevent accidental
writes to memory due to errant (unexpected) code
execution.
There are four SFRs used to read and write the
program and data EEPROM memory. These registers
are:
• EECON1
• EECON2
• EEDATA
• EEADR
Firmware should keep the WREN bit clear at all times,
except when starting erase or write operations. Once
firmware has set the WR bit, the WREN bit may be
cleared. Clearing the WREN bit will not affect the
operation in progress.
The EEPROM data memory allows byte read and write.
When interfacing to the data memory block, EEDATA
holds the 8-bit data for read/write and EEADR holds the
address of the EEPROM location being accessed.
These devices have 256 bytes of data EEPROM with
an address range from 00h to FFh.
The WRERR bit is set when a write operation is
interrupted by a Reset. In these situations, the user can
check the WRERR bit and rewrite the location. It is
necessary to reload the data and address registers
(EEDATA and EEADR), as these registers have
cleared as a result of the Reset.
The EEPROM data memory is rated for high erase/
write cycle endurance. A byte write automatically
erases the location and writes the new data (erase-
before-write). The write time is controlled by an on-chip
timer. The write time will vary with voltage and
temperature, as well as from chip to chip. Please
refer to parameter D122 (Table 22-1 in Section 22.0
“Electrical Characteristics”) for exact limits.
Control bits, RD and WR, start read and erase/write
operations, respectively. These bits are set by firmware
and cleared by hardware at the completion of the
operation.
The RD bit cannot be set when accessing program
memory (EEPGD = 1). Program memory is read using
table read instructions. See Section 6.1 “Table Reads
and Table Writes” regarding table reads.
7.1
EEADR
The address register can address 256 bytes of data
EEPROM.
Note:
Interrupt flag bit, EEIF in the PIR2 register,
is set when write is complete. It must be
cleared in software.
7.2
EECON1 and EECON2 Registers
EECON1 is the control register for memory accesses.
EECON2 is not a physical register. Reading EECON2
will read all ‘0’s. The EECON2 register is used
exclusively in the memory write and erase sequences.
Control bit, EEPGD, determines if the access will be to
program or data EEPROM memory. When clear,
operations will access the data EEPROM memory.
When set, program memory is accessed.
© 2007 Microchip Technology Inc.
DS39605F-page 67
PIC18F1220/1320
REGISTER 7-1:
EECON1 REGISTER
R/W-x
R/W-x
CFGS
U-0
—
R/W-0
FREE
R/W-x
R/W-0
WREN
R/S-0
WR
R/S-0
RD
EEPGD
WRERR
bit 7
bit 0
bit 7
bit 6
EEPGD: Flash Program or Data EEPROM Memory Select bit
1= Access program Flash memory
0= Access data EEPROM memory
CFGS: Flash Program/Data EEPROM or Configuration Select bit
1= Access configuration or calibration registers
0= Access program Flash or data EEPROM memory
bit 5
bit 4
Unimplemented: Read as ‘0’
FREE: Flash Row Erase Enable bit
1= Erase the program memory row addressed by TBLPTR on the next WR command
(cleared by completion of erase operation)
0= Perform write only
bit 3
WRERR: EEPROM Error Flag bit
1= A write operation was prematurely terminated
(MCLR or WDT Reset during self-timed erase or program operation)
0= The write operation completed normally
Note:
When a WRERR occurs, the EEPGD or FREE bits are not cleared. This allows
tracing of the error condition.
bit 2
bit 1
WREN: Erase/Write Enable bit
1= Allows erase/write cycles
0= Inhibits erase/write cycles
WR: Write Control bit
1= Initiates a data EEPROM erase/write cycle, or a program memory erase cycle, or write cycle.
(The operation is self-timed and the bit is cleared by hardware once write is complete. The
WR bit can only be set (not cleared) in software.)
0= Write cycle is completed
bit 0
RD: Read Control bit
1= Initiates a memory read
(Read takes one cycle. RD is cleared in hardware. The RD bit can only be set (not cleared)
in software. RD bit cannot be set when EEPGD = 1.)
0= Read completed
Legend:
R = Readable bit
W = Writable bit
x = Bit is unknown
S = Settable only
-n = Value at POR
U = Unimplemented bit, read as ‘0’
‘1’ = Bit is set ‘0’ = Bit is cleared
DS39605F-page 68
© 2007 Microchip Technology Inc.
PIC18F1220/1320
After a write sequence has been initiated, EECON1,
EEADR and EEDATA cannot be modified. The WR bit
will be inhibited from being set unless the WREN bit is
set. The WREN bit must be set on a previous instruc-
tion. Both WR and WREN cannot be set with the same
instruction.
7.3
Reading the Data EEPROM
Memory
To read a data memory location, the user must write the
address to the EEADR register, clear the EEPGD
control bit (EECON1<7>) and then set control bit, RD
(EECON1<0>). The data is available for the very next
instruction cycle; therefore, the EEDATA register can
be read by the next instruction. EEDATA will hold this
value until another read operation, or until it is written to
by the user (during a write operation).
At the completion of the write cycle, the WR bit is
cleared in hardware and the EEPROM Interrupt Flag bit
(EEIF) is set. The user may either enable this interrupt
or poll this bit. EEIF must be cleared by software.
7.5
Write Verify
7.4
Writing to the Data EEPROM
Memory
Depending on the application, good programming
practice may dictate that the value written to the
memory should be verified against the original value.
This should be used in applications where excessive
writes can stress bits near the specification limit.
To write an EEPROM data location, the address must
first be written to the EEADR register and the data
written to the EEDATA register. The sequence in
Example 7-2 must be followed to initiate the write cycle.
The write will not begin if this sequence is not exactly
followed (write 55h to EECON2, write AAh to EECON2,
then set WR bit) for each byte. It is strongly recom-
mended that interrupts be disabled during this
code segment.
7.6
Protection Against Spurious Write
There are conditions when the device may not want to
write to the data EEPROM memory. To protect against
spurious EEPROM writes, various mechanisms have
been built-in. On power-up, the WREN bit is cleared.
Also, the Power-up Timer (72 ms duration) prevents
EEPROM write.
Additionally, the WREN bit in EECON1 must be set to
enable writes. This mechanism prevents accidental
writes to data EEPROM due to unexpected code exe-
cution (i.e., runaway programs). The WREN bit should
be kept clear at all times, except when updating the
EEPROM. The WREN bit is not cleared by hardware.
The write initiate sequence and the WREN bit together
help prevent an accidental write during brown-out,
power glitch or software malfunction.
EXAMPLE 7-1:
DATA EEPROM READ
MOVLW
MOVWF
BCF
BSF
MOVF
DATA_EE_ADDR
EEADR
EECON1, EEPGD
EECON1, RD
EEDATA, W
;
; Data Memory Address to read
; Point to DATA memory
; EEPROM Read
; W = EEDATA
EXAMPLE 7-2:
DATA EEPROM WRITE
MOVLW
MOVWF
DATA_EE_ADDR
EEADR
;
; Data Memory Address to write
MOVLW
MOVWF
BCF
BSF
BCF
MOVLW
MOVWF
MOVLW
MOVWF
BSF
DATA_EE_DATA
EEDATA
EECON1, EEPGD
EECON1, WREN
INTCON, GIE
55h
EECON2
AAh
EECON2
EECON1, WR
INTCON, GIE
;
; Data Memory Value to write
; Point to DATA memory
; Enable writes
; Disable Interrupts
;
; Write 55h
;
; Write AAh
; Set WR bit to begin write
; Enable Interrupts
Required
Sequence
BSF
SLEEP
BCF
; Wait for interrupt to signal write complete
; Disable writes
EECON1, WREN
© 2007 Microchip Technology Inc.
DS39605F-page 69
PIC18F1220/1320
7.7
Operation During Code-Protect
7.8
Using the Data EEPROM
Data EEPROM memory has its own code-protect bits in
configuration words. External read and write
operations are disabled if either of these mechanisms
are enabled.
The data EEPROM is a high endurance, byte address-
able array that has been optimized for the storage of fre-
quently changing information (e.g., program variables or
other data that are updated often). Frequently changing
values will typically be updated more often than specifi-
cation D124. If this is not the case, an array refresh must
be performed. For this reason, variables that change
infrequently (such as constants, IDs, calibration, etc.)
should be stored in Flash program memory.
The microcontroller itself can both read and write to the
internal data EEPROM, regardless of the state of the
code-protect configuration bit. Refer to Section 19.0
“Special Features of the CPU” for additional
information.
A simple data EEPROM refresh routine is shown in
Example 7-3.
Note: If data EEPROM is only used to store
constants and/or data that changes rarely,
an array refresh is likely not required. See
specification D124.
EXAMPLE 7-3:
DATA EEPROM REFRESH ROUTINE
CLRF
BCF
BCF
BCF
BSF
EEADR
; Start at address 0
EECON1, CFGS
EECON1, EEPGD
INTCON, GIE
EECON1, WREN
; Set for memory
; Set for Data EEPROM
; Disable interrupts
; Enable writes
; Loop to refresh array
; Read current address
;
; Write 55h
;
; Write AAh
; Set WR bit to begin write
; Wait for write to complete
Loop
BSF
EECON1, RD
55h
EECON2
AAh
EECON2
EECON1, WR
EECON1, WR
$-2
MOVLW
MOVWF
MOVLW
MOVWF
BSF
BTFSC
BRA
INCFSZ EEADR, F
; Increment address
BRA
Loop
; Not zero, do it again
BCF
BSF
EECON1, WREN
INTCON, GIE
; Disable writes
; Enable interrupts
TABLE 7-1:
REGISTERS ASSOCIATED WITH DATA EEPROM MEMORY
Value on
all other
Resets
Value on:
POR, BOR
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
INTCON
EEADR
EEDATA
GIE/GIEH PEIE/GIEL TMR0IE
EEPROM Address Register
EEPROM Data Register
INTE
RBIE
TMR0IF
INTF
RBIF
0000 000x 0000 000u
0000 0000 0000 0000
0000 0000 0000 0000
EECON2 EEPROM Control Register 2 (not a physical register)
—
—
EECON1
IPR2
EEPGD
OSCFIP
OSCFIF
OSCFIE
CFGS
—
—
—
—
—
FREE
EEIP
EEIF
EEIE
WRERR WREN
WR
RD
—
xx-0 x000 uu-0 u000
1--1 -11- 1--1 -11-
0--0 -00- 0--0 -00-
0--0 -00- 0--0 -00-
—
—
—
LVDIP
LVDIF
LVDIE
TMR3IP
TMR3IF
TMR3IE
PIR2
—
—
PIE2
—
—
Legend: x= unknown, u= unchanged, – = unimplemented, read as ‘0’. Shaded cells are not used during Flash/EEPROM access.
DS39605F-page 70
© 2007 Microchip Technology Inc.
PIC18F1220/1320
Making the 8 x 8 multiplier execute in a single cycle
gives the following advantages:
8.0
8.1
8 x 8 HARDWARE MULTIPLIER
Introduction
• Higher computational throughput
• Reduces code size requirements for multiply
algorithms
An 8 x 8 hardware multiplier is included in the ALU of
the PIC18F1220/1320 devices. By making the multiply
a hardware operation, it completes in a single instruc-
tion cycle. This is an unsigned multiply that gives a
16-bit result. The result is stored into the 16-bit product
register pair (PRODH:PRODL). The multiplier does not
affect any flags in the Status register.
The performance increase allows the device to be used
in applications previously reserved for Digital Signal
Processors.
Table 8-1 shows a performance comparison between
Enhanced devices using the single-cycle hardware
multiply and performing the same function without the
hardware multiply.
TABLE 8-1:
Routine
PERFORMANCE COMPARISON
Program
Time
Cycles
(Max)
Multiply Method
Memory
(Words)
@ 40 MHz @ 10 MHz @ 4 MHz
Without hardware multiply
Hardware multiply
13
1
69
1
6.9 μs
100 ns
9.1 μs
600 ns
24.2 μs
2.8 μs
25.4 μs
4 μs
27.6 μs
400 ns
36.4 μs
2.4 μs
69 μs
1 μs
91 μs
6 μs
8 x 8 unsigned
8 x 8 signed
Without hardware multiply
Hardware multiply
33
6
91
6
Without hardware multiply
Hardware multiply
21
28
52
35
242
28
254
40
96.8 μs
11.2 μs
102.6 μs
16 μs
242 μs
28 μs
254 μs
40 μs
16 x 16 unsigned
16 x 16 signed
Without hardware multiply
Hardware multiply
EXAMPLE 8-2:
8 x 8 SIGNED MULTIPLY
ROUTINE
8.2
Operation
Example 8-1 shows the sequence to do an 8 x 8
unsigned multiply. Only one instruction is required
when one argument of the multiply is already loaded in
the WREG register.
MOVF
MULWF
ARG1, W
ARG2
; ARG1 * ARG2 ->
; PRODH:PRODL
; Test Sign Bit
; PRODH = PRODH
BTFSC
SUBWF
ARG2, SB
PRODH, F
Example 8-2 shows the sequence to do an 8 x 8 signed
multiply. To account for the sign bits of the arguments,
each argument’s Most Significant bit (MSb) is tested
and the appropriate subtractions are done.
;
- ARG1
MOVF
BTFSC
SUBWF
ARG2, W
ARG1, SB
PRODH, F
; Test Sign Bit
; PRODH = PRODH
;
- ARG2
EXAMPLE 8-1:
8 x 8 UNSIGNED
MULTIPLY ROUTINE
MOVF
MULWF
ARG1, W
ARG2
;
; ARG1 * ARG2 ->
; PRODH:PRODL
© 2007 Microchip Technology Inc.
DS39605F-page 71
PIC18F1220/1320
Example 8-3 shows the sequence to do a 16 x 16
unsigned multiply. Equation 8-1 shows the algorithm
that is used. The 32-bit result is stored in four registers,
RES3:RES0.
EQUATION 8-2:
16 x 16 SIGNED
MULTIPLICATION
ALGORITHM
RES3:RES0
=
=
ARG1H:ARG1L • ARG2H:ARG2L
16
EQUATION 8-1:
16 x 16 UNSIGNED
MULTIPLICATION
ALGORITHM
(ARG1H • ARG2H • 2 ) +
8
(ARG1H • ARG2L • 2 ) +
8
(ARG1L • ARG2H • 2 ) +
(ARG1L • ARG2L) +
(-1 • ARG2H<7> • ARG1H:ARG1L • 2 ) +
(-1 • ARG1H<7> • ARG2H:ARG2L • 2
16
RES3:RES0
16
=
=
ARG1H:ARG1L • ARG2H:ARG2L
(ARG1H • ARG2H • 2 ) +
)
16
8
(ARG1H • ARG2L • 2 ) +
(ARG1L • ARG2H • 2 ) +
(ARG1L • ARG2L)
8
EXAMPLE 8-4:
16 x 16 SIGNED
MULTIPLY ROUTINE
MOVF
MULWF
ARG1L, W
ARG2L
EXAMPLE 8-3:
16 x 16 UNSIGNED
MULTIPLY ROUTINE
; ARG1L * ARG2L ->
; PRODH:PRODL
;
;
MOVFF
MOVFF
PRODH, RES1
PRODL, RES0
MOVF
MULWF
ARG1L, W
ARG2L
; ARG1L * ARG2L ->
; PRODH:PRODL
;
;
;
;
MOVF
MULWF
ARG1H, W
ARG2H
MOVFF
MOVFF
PRODH, RES1
PRODL, RES0
; ARG1H * ARG2H ->
; PRODH:PRODL
;
;
;
;
MOVFF
MOVFF
PRODH, RES3
PRODL, RES2
MOVF
MULWF
ARG1H, W
ARG2H
; ARG1H * ARG2H ->
; PRODH:PRODL
;
;
MOVF
MULWF
ARG1L, W
ARG2H
MOVFF
MOVFF
PRODH, RES3
PRODL, RES2
; ARG1L * ARG2H ->
; PRODH:PRODL
;
; Add cross
; products
;
;
;
MOVF
ADDWF
MOVF
ADDWFC RES2, F
CLRF WREG
ADDWFC RES3, F
PRODL, W
RES1, F
PRODH, W
MOVF
MULWF
ARG1L, W
ARG2H
; ARG1L * ARG2H ->
; PRODH:PRODL
;
; Add cross
; products
;
;
;
MOVF
ADDWF
MOVF
PRODL, W
RES1, F
PRODH, W
;
ADDWFC RES2, F
CLRF WREG
ADDWFC RES3,F
MOVF
MULWF
ARG1H, W
ARG2L
;
; ARG1H * ARG2L ->
; PRODH:PRODL
;
; Add cross
; products
;
;
;
;
MOVF
ADDWF
MOVF
ADDWFC RES2, F
CLRF WREG
ADDWFC RES3, F
PRODL, W
RES1, F
PRODH, W
MOVF
ARG1H, W
;
MULWF
ARG2L
; ARG1H * ARG2L ->
; PRODH:PRODL
;
; Add cross
; products
MOVF
ADDWF
MOVF
PRODL, W
RES1, F
PRODH, W
;
;
ADDWFC RES2, F
CLRF WREG
ADDWFC RES3, F
;
;
;
BTFSS
BRA
MOVF
SUBWF
MOVF
ARG2H, 7
SIGN_ARG1
ARG1L, W
RES2
; ARG2H:ARG2L neg?
; no, check ARG1
;
;
;
Example 8-4 shows the sequence to do a 16 x 16
signed multiply. Equation 8-2 shows the algorithm
used. The 32-bit result is stored in four registers,
RES3:RES0. To account for the sign bits of the argu-
ments, each argument pairs’ Most Significant bit (MSb)
is tested and the appropriate subtractions are done.
ARG1H, W
SUBWFB RES3
SIGN_ARG1
BTFSS
BRA
ARG1H, 7
CONT_CODE
ARG2L, W
RES2
; ARG1H:ARG1L neg?
; no, done
;
;
;
MOVF
SUBWF
MOVF
ARG2H, W
SUBWFB RES3
;
CONT_CODE
:
DS39605F-page 72
© 2007 Microchip Technology Inc.
PIC18F1220/1320
When the IPEN bit is cleared (default state), the
interrupt priority feature is disabled and interrupts are
compatible with PIC mid-range devices. In
Compatibility mode, the interrupt priority bits for each
source have no effect. INTCON<6> is the PEIE bit,
which enables/disables all peripheral interrupt sources.
INTCON<7> is the GIE bit, which enables/disables all
interrupt sources. All interrupts branch to address
000008h in Compatibility mode.
9.0
INTERRUPTS
The PIC18F1220/1320 devices have multiple interrupt
sources and an interrupt priority feature that allows
each interrupt source to be assigned a high priority
level or a low priority level. The high priority interrupt
vector is at 000008h and the low priority interrupt vector
is at 000018h. High priority interrupt events will
interrupt any low priority interrupts that may be in
progress.
When an interrupt is responded to, the global interrupt
enable bit is cleared to disable further interrupts. If the
IPEN bit is cleared, this is the GIE bit. If interrupt priority
levels are used, this will be either the GIEH or GIEL bit.
High priority interrupt sources can interrupt a low
priority interrupt. Low priority interrupts are not
processed while high priority interrupts are in progress.
There are ten registers which are used to control
interrupt operation. These registers are:
• RCON
• INTCON
• INTCON2
• INTCON3
• PIR1, PIR2
• PIE1, PIE2
• IPR1, IPR2
The return address is pushed onto the stack and the
PC is loaded with the interrupt vector address
(000008h or 000018h). Once in the Interrupt Service
Routine, the source(s) of the interrupt can be deter-
mined by polling the interrupt flag bits. The interrupt
flag bits must be cleared in software before re-enabling
interrupts to avoid recursive interrupts.
It is recommended that the Microchip header files
supplied with MPLAB® IDE be used for the symbolic bit
names in these registers. This allows the assembler/
compiler to automatically take care of the placement of
these bits within the specified register.
The “return from interrupt” instruction, RETFIE, exits
the interrupt routine and sets the GIE bit (GIEH or
GIEL, if priority levels are used), which re-enables
interrupts.
In general, each interrupt source has three bits to
control its operation. The functions of these bits are:
For external interrupt events, such as the INT pins or
the PORTB input change interrupt, the interrupt latency
will be three to four instruction cycles. The exact
latency is the same for one or two-cycle instructions.
Individual interrupt flag bits are set, regardless of the
status of their corresponding enable bit or the GIE bit.
• Flag bit to indicate that an interrupt event
occurred
• Enable bit that allows program execution to
branch to the interrupt vector address when the
flag bit is set
• Priority bit to select high priority or low priority
(INT0 has no priority bit and is always high priority)
Note:
Do not use the MOVFFinstruction to modify
any of the interrupt control registers while
any interrupt is enabled. Doing so may
cause erratic microcontroller behavior.
The interrupt priority feature is enabled by setting the
IPEN bit (RCON<7>). When interrupt priority is
enabled, there are two bits which enable interrupts
globally. Setting the GIEH bit (INTCON<7>) enables all
interrupts that have the priority bit set (high priority).
Setting the GIEL bit (INTCON<6>) enables all
interrupts that have the priority bit cleared (low priority).
When the interrupt flag, enable bit and appropriate
global interrupt enable bit are set, the interrupt will
vector immediately to address 000008h or 000018h,
depending on the priority bit setting. Individual
interrupts can be disabled through their corresponding
enable bits.
© 2007 Microchip Technology Inc.
DS39605F-page 73
PIC18F1220/1320
FIGURE 9-1:
INTERRUPT LOGIC
Wake-up if in Low-Power Mode
TMR0IF
TMR0IE
TMR0IP
RBIF
RBIE
RBIP
INT0IF
INT0IE
Interrupt to CPU
Vector to Location
0008h
INT1IF
INT1IE
INT1IP
INT2IF
INT2IE
INT2IP
INT0IF
INT0IE
GIEH/GIE
ADIF
ADIE
ADIP
IPEN
IPEN
RCIF
RCIE
RCIP
GIEL/PEIE
IPEN
Additional Peripheral Interrupts
High Priority Interrupt Generation
Low Priority Interrupt Generation
INT0IF
INT0IE
Interrupt to CPU
Vector to Location
0018h
TMR0IF
TMR0IE
TMR0IP
ADIF
ADIE
ADIP
RBIF
RBIE
RBIP
GIEL\PEIE
GIE\GIEH
RCIF
RCIE
RCIP
INT0IF
INT0IE
INT1IF
INT1IE
INT1IP
Additional Peripheral Interrupts
INT2IF
INT2IE
INT2IP
DS39605F-page 74
© 2007 Microchip Technology Inc.
PIC18F1220/1320
9.1
INTCON Registers
Note:
Interrupt flag bits are set when an interrupt
condition occurs, regardless of the state of
its corresponding enable bit or the global
interrupt enable bit. User software should
ensure the appropriate interrupt flag bits
are clear prior to enabling an interrupt.
This feature allows for software polling.
The INTCON registers are readable and writable
registers, which contain various enable, priority and
flag bits.
REGISTER 9-1:
INTCON REGISTER
R/W-0 R/W-0
R/W-0
R/W-0
R/W-0
RBIE
R/W-0
R/W-0
INT0IF
R/W-x
RBIF
GIE/GIEH PEIE/GIEL
bit 7
TMR0IE
INT0IE
TMR0IF
bit 0
bit 7
GIE/GIEH: Global Interrupt Enable bit
When IPEN = 0:
1= Enables all unmasked interrupts
0= Disables all interrupts
When IPEN = 1:
1= Enables all high priority interrupts
0= Disables all interrupts
bit 6
PEIE/GIEL: Peripheral Interrupt Enable bit
When IPEN = 0:
1= Enables all unmasked peripheral interrupts
0= Disables all peripheral interrupts
When IPEN = 1:
1= Enables all low priority peripheral interrupts
0= Disables all low priority peripheral interrupts
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
TMR0IE: TMR0 Overflow Interrupt Enable bit
1= Enables the TMR0 overflow interrupt
0= Disables the TMR0 overflow interrupt
INT0IE: INT0 External Interrupt Enable bit
1= Enables the INT0 external interrupt
0= Disables the INT0 external interrupt
RBIE: RB Port Change Interrupt Enable bit
1= Enables the RB port change interrupt
0= Disables the RB port change interrupt
TMR0IF: TMR0 Overflow Interrupt Flag bit
1= TMR0 register has overflowed (must be cleared in software)
0= TMR0 register did not overflow
INT0IF: INT0 External Interrupt Flag bit
1= The INT0 external interrupt occurred (must be cleared in software)
0= The INT0 external interrupt did not occur
RBIF: RB Port Change Interrupt Flag bit
1= At least one of the RB7:RB4 pins changed state (must be cleared in software)
0= None of the RB7:RB4 pins have changed state
Note:
A mismatch condition will continue to set this bit. Reading PORTB will end the
mismatch condition and allow the bit to be cleared.
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
© 2007 Microchip Technology Inc.
DS39605F-page 75
PIC18F1220/1320
REGISTER 9-2:
INTCON2 REGISTER
R/W-1
RBPU
R/W-1
R/W-1
R/W-1
U-0
—
R/W-1
U-0
—
R/W-1
RBIP
INTEDG0 INTEDG1 INTEDG2
TMR0IP
bit 7
bit 0
bit 7
bit 6
bit 5
bit 4
RBPU: PORTB Pull-up Enable bit
1= All PORTB pull-ups are disabled
0= PORTB pull-ups are enabled by individual port latch values
INTEDG0: External Interrupt 0 Edge Select bit
1= Interrupt on rising edge
0= Interrupt on falling edge
INTEDG1: External Interrupt 1 Edge Select bit
1= Interrupt on rising edge
0= Interrupt on falling edge
INTEDG2: External Interrupt 2 Edge Select bit
1= Interrupt on rising edge
0= Interrupt on falling edge
bit 3
bit 2
Unimplemented: Read as ‘0’
TMR0IP: TMR0 Overflow Interrupt Priority bit
1= High priority
0= Low priority
bit 1
bit 0
Unimplemented: Read as ‘0’
RBIP: RB Port Change Interrupt Priority bit
1= High priority
0= Low priority
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
Note:
Interrupt flag bits are set when an interrupt condition occurs, regardless of the state
of its corresponding enable bit or the global interrupt enable bit. User software
should ensure the appropriate interrupt flag bits are clear prior to enabling an
interrupt. This feature allows for software polling.
DS39605F-page 76
© 2007 Microchip Technology Inc.
PIC18F1220/1320
REGISTER 9-3:
INTCON3 REGISTER
R/W-1
R/W-1
U-0
—
R/W-0
R/W-0
U-0
—
R/W-0
INT2IF
R/W-0
INT1IF
INT2IP
INT1IP
INT2IE
INT1IE
bit 7
bit 0
bit 7
bit 6
INT2IP: INT2 External Interrupt Priority bit
1= High priority
0= Low priority
INT1IP: INT1 External Interrupt Priority bit
1= High priority
0= Low priority
bit 5
bit 4
Unimplemented: Read as ‘0’
INT2IE: INT2 External Interrupt Enable bit
1= Enables the INT2 external interrupt
0= Disables the INT2 external interrupt
bit 3
INT1IE: INT1 External Interrupt Enable bit
1= Enables the INT1 external interrupt
0= Disables the INT1 external interrupt
bit 2
bit 1
Unimplemented: Read as ‘0’
INT2IF: INT2 External Interrupt Flag bit
1= The INT2 external interrupt occurred (must be cleared in software)
0= The INT2 external interrupt did not occur
bit 0
INT1IF: INT1 External Interrupt Flag bit
1= The INT1 external interrupt occurred (must be cleared in software)
0= The INT1 external interrupt did not occur
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
Note:
Interrupt flag bits are set when an interrupt condition occurs, regardless of the state
of its corresponding enable bit or the global interrupt enable bit. User software
should ensure the appropriate interrupt flag bits are clear prior to enabling an
interrupt. This feature allows for software polling.
© 2007 Microchip Technology Inc.
DS39605F-page 77
PIC18F1220/1320
9.2
PIR Registers
Note 1: Interrupt flag bits are set when an interrupt
condition occurs, regardless of the state of
its corresponding enable bit or the Global
Interrupt Enable bit, GIE (INTCON<7>).
The PIR registers contain the individual flag bits for the
peripheral interrupts. Due to the number of peripheral
interrupt sources, there are two Peripheral Interrupt
Request (Flag) registers (PIR1, PIR2).
2: User software should ensure the appropri-
ate interrupt flag bits are cleared prior to
enabling an interrupt and after servicing
that interrupt.
REGISTER 9-4:
PIR1: PERIPHERAL INTERRUPT REQUEST (FLAG) REGISTER 1
U-0
—
R/W-0
ADIF
R-0
R-0
U-0
—
R/W-0
R/W-0
R/W-0
RCIF
TXIF
CCP1IF
TMR2IF
TMR1IF
bit 7
bit 0
bit 7
bit 6
Unimplemented: Read as ‘0’
ADIF: A/D Converter Interrupt Flag bit
1= An A/D conversion completed (must be cleared in software)
0= The A/D conversion is not complete
bit 5
bit 4
RCIF: EUSART Receive Interrupt Flag bit
1= The EUSART receive buffer, RCREG, is full (cleared when RCREG is read)
0= The EUSART receive buffer is empty
TXIF: EUSART Transmit Interrupt Flag bit
1= The EUSART transmit buffer, TXREG, is empty (cleared when TXREG is written)
0= The EUSART transmit buffer is full
bit 3
bit 2
Unimplemented: Read as ‘0’
CCP1IF: CCP1 Interrupt Flag bit
Capture mode:
1= A TMR1 register capture occurred (must be cleared in software)
0= No TMR1 register capture occurred
Compare mode:
1= A TMR1 register compare match occurred (must be cleared in software)
0= No TMR1 register compare match occurred
PWM mode:
Unused in this mode.
bit 1
bit 0
TMR2IF: TMR2 to PR2 Match Interrupt Flag bit
1= TMR2 to PR2 match occurred (must be cleared in software)
0= No TMR2 to PR2 match occurred
TMR1IF: TMR1 Overflow Interrupt Flag bit
1= TMR1 register overflowed (must be cleared in software)
0= TMR1 register did not overflow
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
DS39605F-page 78
© 2007 Microchip Technology Inc.
PIC18F1220/1320
REGISTER 9-5:
PIR2: PERIPHERAL INTERRUPT REQUEST (FLAG) REGISTER 2
R/W-0
OSCFIF
bit 7
U-0
—
U-0
—
R/W-0
EEIF
U-0
—
R/W-0
LVDIF
R/W-0
U-0
—
TMR3IF
bit 0
bit 7
OSCFIF: Oscillator Fail Interrupt Flag bit
1= System oscillator failed, clock input has changed to INTOSC (must be cleared in software)
0= System clock operating
bit 6-5 Unimplemented: Read as ‘0’
bit 4
EEIF: Data EEPROM/Flash Write Operation Interrupt Flag bit
1= The write operation is complete (must be cleared in software)
0= The write operation is not complete or has not been started
bit 3
bit 2
Unimplemented: Read as ‘0’
LVDIF: Low-Voltage Detect Interrupt Flag bit
1= A low-voltage condition occurred (must be cleared in software)
0= The device voltage is above the Low-Voltage Detect trip point
bit 1
bit 0
TMR3IF: TMR3 Overflow Interrupt Flag bit
1= TMR3 register overflowed (must be cleared in software)
0= TMR3 register did not overflow
Unimplemented: Read as ‘0’
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
© 2007 Microchip Technology Inc.
DS39605F-page 79
PIC18F1220/1320
9.3
PIE Registers
The PIE registers contain the individual enable bits for
the peripheral interrupts. Due to the number of
peripheral interrupt sources, there are two Peripheral
Interrupt Enable registers (PIE1, PIE2). When
IPEN = 0, the PEIE bit must be set to enable any of
these peripheral interrupts.
REGISTER 9-6:
PIE1: PERIPHERAL INTERRUPT ENABLE REGISTER 1
U-0
—
R/W-0
ADIE
R/W-0
RCIE
R/W-0
TXIE
U-0
—
R/W-0
R/W-0
R/W-0
TMR1IE
bit 0
CCP1IE
TMR2IE
bit 7
bit 7
bit 6
Unimplemented: Read as ‘0’
ADIE: A/D Converter Interrupt Enable bit
1= Enables the A/D interrupt
0= Disables the A/D interrupt
bit 5
bit 4
RCIE: EUSART Receive Interrupt Enable bit
1= Enables the EUSART receive interrupt
0= Disables the EUSART receive interrupt
TXIE: EUSART Transmit Interrupt Enable bit
1= Enables the EUSART transmit interrupt
0= Disables the EUSART transmit interrupt
bit 3
bit 2
Unimplemented: Read as ‘0’
CCP1IE: CCP1 Interrupt Enable bit
1= Enables the CCP1 interrupt
0= Disables the CCP1 interrupt
bit 1
bit 0
TMR2IE: TMR2 to PR2 Match Interrupt Enable bit
1= Enables the TMR2 to PR2 match interrupt
0= Disables the TMR2 to PR2 match interrupt
TMR1IE: TMR1 Overflow Interrupt Enable bit
1= Enables the TMR1 overflow interrupt
0= Disables the TMR1 overflow interrupt
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
DS39605F-page 80
© 2007 Microchip Technology Inc.
PIC18F1220/1320
REGISTER 9-7:
PIE2: PERIPHERAL INTERRUPT ENABLE REGISTER 2
R/W-0
OSCFIE
bit 7
U-0
—
U-0
—
R/W-0
EEIE
U-0
—
R/W-0
LVDIE
R/W-0
U-0
—
TMR3IE
bit 0
bit 7
OSCFIE: Oscillator Fail Interrupt Enable bit
1= Enabled
0= Disabled
bit 6-5
bit 4
Unimplemented: Read as ‘0’
EEIE: Data EEPROM/Flash Write Operation Interrupt Enable bit
1= Enabled
0= Disabled
bit 3
bit 2
Unimplemented: Read as ‘0’
LVDIE: Low-Voltage Detect Interrupt Enable bit
1= Enabled
0= Disabled
bit 1
bit 0
TMR3IE: TMR3 Overflow Interrupt Enable bit
1= Enabled
0= Disabled
Unimplemented: Read as ‘0’
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
© 2007 Microchip Technology Inc.
DS39605F-page 81
PIC18F1220/1320
9.4
IPR Registers
The IPR registers contain the individual priority bits for
the peripheral interrupts. Due to the number of
peripheral interrupt sources, there are two Peripheral
Interrupt Priority registers (IPR1, IPR2). Using the
priority bits requires that the Interrupt Priority Enable
(IPEN) bit be set.
REGISTER 9-8:
IPR1: PERIPHERAL INTERRUPT PRIORITY REGISTER 1
U-0
—
R/W-1
ADIP
R/W-1
RCIP
R/W-1
TXIP
U-0
—
R/W-1
R/W-1
R/W-1
TMR1IP
bit 0
CCP1IP
TMR2IP
bit 7
bit 7
bit 6
Unimplemented: Read as ‘0’
ADIP: A/D Converter Interrupt Priority bit
1= High priority
0= Low priority
bit 5
bit 4
RCIP: EUSART Receive Interrupt Priority bit
1= High priority
0= Low priority
TXIP: EUSART Transmit Interrupt Priority bit
1= High priority
0= Low priority
bit 3
bit 2
Unimplemented: Read as ‘0’
CCP1IP: CCP1 Interrupt Priority bit
1= High priority
0= Low priority
bit 1
bit 0
TMR2IP: TMR2 to PR2 Match Interrupt Priority bit
1= High priority
0= Low priority
TMR1IP: TMR1 Overflow Interrupt Priority bit
1= High priority
0= Low priority
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
DS39605F-page 82
© 2007 Microchip Technology Inc.
PIC18F1220/1320
REGISTER 9-9:
IPR2: PERIPHERAL INTERRUPT PRIORITY REGISTER 2
R/W-1
OSCFIP
bit 7
U-0
—
U-0
—
R/W-1
EEIP
U-0
—
R/W-1
LVDIP
R/W-1
U-0
—
TMR3IP
bit 0
bit 7
OSCFIP: Oscillator Fail Interrupt Priority bit
1= High priority
0= Low priority
bit 6-5
bit 4
Unimplemented: Read as ‘0’
EEIP: Data EEPROM/Flash Write Operation Interrupt Priority bit
1= High priority
0= Low priority
bit 3
bit 2
Unimplemented: Read as ‘0’
LVDIP: Low-Voltage Detect Interrupt Priority bit
1= High priority
0= Low priority
bit 1
bit 0
TMR3IP: TMR3 Overflow Interrupt Priority bit
1= High priority
0= Low priority
Unimplemented: Read as ‘0’
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
© 2007 Microchip Technology Inc.
DS39605F-page 83
PIC18F1220/1320
9.5
RCON Register
The RCON register contains bits used to determine the
cause of the last Reset or wake-up from a low-power
mode. RCON also contains the bit that enables
interrupt priorities (IPEN).
REGISTER 9-10: RCON REGISTER
R/W-0
IPEN
U-0
—
U-0
—
R/W-1
RI
R-1
TO
R-1
PD
R/W-0
POR
R/W-0
BOR
bit 7
bit 0
bit 7
IPEN: Interrupt Priority Enable bit
1= Enable priority levels on interrupts
0= Disable priority levels on interrupts (PIC16CXXX Compatibility mode)
bit 6-5 Unimplemented: Read as ‘0’
bit 4
bit 3
bit 2
bit 1
bit 0
RI: RESETInstruction Flag bit
For details of bit operation, see Register 5-3.
TO: Watchdog Time-out Flag bit
For details of bit operation, see Register 5-3.
PD: Power-down Detection Flag bit
For details of bit operation, see Register 5-3.
POR: Power-on Reset Status bit
For details of bit operation, see Register 5-3.
BOR: Brown-out Reset Status bit
For details of bit operation, see Register 5-3.
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
DS39605F-page 84
© 2007 Microchip Technology Inc.
PIC18F1220/1320
9.6
INTn Pin Interrupts
9.7
TMR0 Interrupt
External interrupts on the RB0/INT0, RB1/INT1 and
RB2/INT2 pins are edge-triggered: either rising if the
corresponding INTEDGx bit is set in the INTCON2 reg-
ister, or falling if the INTEDGx bit is clear. When a valid
edge appears on the RBx/INTx pin, the corresponding
flag bit, INTxF, is set. This interrupt can be disabled by
clearing the corresponding enable bit, INTxE. Flag bit,
INTxF, must be cleared in software in the Interrupt
Service Routine before re-enabling the interrupt. All
external interrupts (INT0, INT1 and INT2) can wake-up
the processor from low-power modes if bit INTxE was
set prior to going into low-power modes. If the Global
Interrupt Enable bit, GIE, is set, the processor will
branch to the interrupt vector following wake-up.
In 8-bit mode (which is the default), an overflow
(FFh → 00h) in the TMR0 register will set flag bit,
TMR0IF. In 16-bit mode, an overflow (FFFFh → 0000h)
in the TMR0H:TMR0L registers will set flag bit,
TMR0IF. The interrupt can be enabled/disabled by
setting/clearing enable bit, TMR0IE (INTCON<5>).
Interrupt priority for Timer0 is determined by the value
contained in the interrupt priority bit, TMR0IP
(INTCON2<2>). See Section 11.0 “Timer0 Module”
for further details on the Timer0 module.
9.8
PORTB Interrupt-on-Change
An input change on PORTB<7:4> sets flag bit, RBIF
(INTCON<0>). The interrupt can be enabled/disabled
by setting/clearing enable bit, RBIE (INTCON<3>).
Interrupt priority for PORTB interrupt-on-change is
determined by the value contained in the interrupt
priority bit, RBIP (INTCON2<0>).
Interrupt priority for INT1 and INT2 is determined by the
value contained in the interrupt priority bits, INT1IP
(INTCON3<6>) and INT2IP (INTCON3<7>). There is
no priority bit associated with INT0. It is always a high
priority interrupt source.
9.9
Context Saving During Interrupts
During interrupts, the return PC address is saved on the
stack. Additionally, the WREG, Status and BSR registers
are saved on the fast return stack. If a fast return from
interrupt is not used (see Section 5.3 “Fast Register
Stack”), the user may need to save the WREG, Status
and BSR registers on entry to the Interrupt Service
Routine. Depending on the user’s application, other
registers may also need to be saved. Example 9-1
saves and restores the WREG, Status and BSR
registers during an Interrupt Service Routine.
EXAMPLE 9-1:
SAVING STATUS, WREG AND BSR REGISTERS IN RAM
MOVWF
MOVFF
MOVFF
;
W_TEMP
STATUS, STATUS_TEMP
BSR, BSR_TEMP
; W_TEMP is in virtual bank
; STATUS_TEMP located anywhere
; BSR_TMEP located anywhere
; USER ISR CODE
;
MOVFF
MOVF
MOVFF
BSR_TEMP, BSR
W_TEMP, W
STATUS_TEMP, STATUS
; Restore BSR
; Restore WREG
; Restore STATUS
© 2007 Microchip Technology Inc.
DS39605F-page 85
PIC18F1220/1320
NOTES:
DS39605F-page 86
© 2007 Microchip Technology Inc.
PIC18F1220/1320
The Data Latch register (LATA) is also memory
mapped. Read-modify-write operations on the LATA
register read and write the latched output value for
PORTA.
10.0 I/O PORTS
Depending on the device selected and features
enabled, there are up to five ports available. Some pins
of the I/O ports are multiplexed with an alternate
function from the peripheral features on the device. In
general, when a peripheral is enabled, that pin may not
be used as a general purpose I/O pin.
The RA4 pin is multiplexed with the Timer0 module
clock input to become the RA4/T0CKI pin.
The sixth pin of PORTA (MCLR/VPP/RA5) is an input
only pin. Its operation is controlled by the MCLRE
configuration bit in Configuration Register 3H
(CONFIG3H<7>). When selected as a port pin
(MCLRE = 0), it functions as a digital input only pin; as
such, it does not have TRIS or LAT bits associated with
its operation. Otherwise, it functions as the device’s
Master Clear input. In either configuration, RA5 also
functions as the programming voltage input during
programming.
Each port has three registers for its operation. These
registers are:
• TRIS register (data direction register)
• PORT register (reads the levels on the pins of the
device)
• LAT register (output latch)
The Data Latch (LATA) register is useful for read-
modify-write operations on the value that the I/O pins
are driving.
Note:
On a Power-on Reset, RA5 is enabled as a
digital input only if Master Clear functionality
is disabled.
A simplified model of a generic I/O port without the
interfaces to other peripherals is shown in Figure 10-1.
Pins RA6 and RA7 are multiplexed with the main oscil-
lator pins; they are enabled as oscillator or I/O pins by
the selection of the main oscillator in Configuration
Register 1H (see Section 19.1 “Configuration Bits”
for details). When they are not used as port pins, RA6
and RA7 and their associated TRIS and LAT bits are
read as ‘0’.
FIGURE 10-1:
GENERIC I/O PORT
OPERATION
RD LAT
Data
Bus
D
Q
The other PORTA pins are multiplexed with analog
inputs, the analog VREF+ and VREF- inputs and the LVD
input. The operation of pins RA3:RA0 as A/D converter
inputs is selected by clearing/setting the control bits in
the ADCON1 register (A/D Control Register 1).
I/O pin(1)
WR LAT
or Port
CK
Data Latch
D
Q
Note:
On a Power-on Reset, RA3:RA0 are
configured as analog inputs and read as
‘0’. RA4 is always a digital pin.
WR TRIS
RD TRIS
CK
TRIS Latch
Input
Buffer
The RA4/T0CKI pin is a Schmitt Trigger input and an
open-drain output. All other PORTA pins have TTL
input levels and full CMOS output drivers.
Q
D
The TRISA register controls the direction of the RA
pins, even when they are being used as analog inputs.
The user must ensure the bits in the TRISA register are
maintained set when using them as analog inputs.
EN
RD Port
Note 1: I/O pins have diode protection to VDD and VSS.
EXAMPLE 10-1:
INITIALIZING PORTA
CLRF
PORTA
LATA
0x7F
; Initialize PORTA by
; clearing output
; data latches
; Alternate method
; to clear output
; data latches
10.1 PORTA, TRISA and LATA
Registers
CLRF
PORTA is an 8-bit wide, bidirectional port. The corre-
sponding data direction register is TRISA. Setting a
TRISA bit (= 1) will make the corresponding PORTA pin
an input (i.e., put the corresponding output driver in a
high-impedance mode). Clearing a TRISA bit (= 0) will
make the corresponding PORTA pin an output (i.e., put
the contents of the output latch on the selected pin).
MOVLW
MOVWF
MOVLW
; Configure A/D
ADCON1 ; for digital inputs
0xD0
; Value used to
; initialize data
; direction
; Set RA<3:0> as outputs
; RA<7:4> as inputs
MOVWF
TRISA
Reading the PORTA register reads the status of the
pins, whereas writing to it will write to the port latch.
© 2007 Microchip Technology Inc.
DS39605F-page 87
PIC18F1220/1320
FIGURE 10-2:
BLOCK DIAGRAM OF
RA3:RA0 PINS
FIGURE 10-4:
BLOCK DIAGRAM OF
RA4/T0CKI PIN
RD LATA
RD LATA
Data
Bus
Data
Bus
D
Q
D
Q
WR LATA
or
PORTA
WR LATA
or
PORTA
VDD
Q
I/O pin(1)
Q
Data Latch
CK
CK
P
N
Data Latch
I/O pin(1)
N
D
Q
Q
VSS
D
Q
WR TRISA
RD TRISA
Schmitt
Trigger
Input
WR TRISA
CK
VSS
Q
CK
Analog
Input
Mode
TRIS Latch
TRIS Latch
Buffer
RD TRISA
Schmitt
Trigger
Input
Q
D
Q
D
Buffer
EN
EN
RD PORTA
RD PORTA
TMR0 Clock Input
Note 1: I/O pins have protection diodes to VDD and VSS.
To A/D Converter and LVD Modules
Note 1: I/O pins have protection diodes to VDD and VSS.
FIGURE 10-5:
BLOCK DIAGRAM OF
OSC1/CLKI/RA7 PIN
FIGURE 10-3:
BLOCK DIAGRAM OF
OSC2/CLKO/RA6 PIN
RA7 Enable
RA6 Enable
To Oscillator
Data
Bus
Data
Bus
RD LATA
RD LATA
D
WR LATA
or
Q
Q
D
WR LATA
or
Q
Q
VDD
P
VDD
P
PORTA
PORTA
CK
CK
Data Latch
Data Latch
I/O pin(1)
N
N
I/O pin(1)
D
Q
D
Q
WR
TRISA
WR
TRISA
VSS
VSS
CK
Q
CK
Q
TRIS Latch
TRIS Latch
Schmitt
Trigger
Input
RD
TRISA
RD
TRISA
Schmitt
Trigger
Input
Buffer
ECIO or
RA7
Enable
RCIO
Enable
Buffer
Q
D
Q
D
EN
EN
RD PORTA
RD PORTA
Note 1: I/O pins have protection diodes to VDD and VSS.
Note 1: I/O pins have protection diodes to VDD and VSS.
DS39605F-page 88
© 2007 Microchip Technology Inc.
PIC18F1220/1320
FIGURE 10-6:
MCLR/VPP/RA5 PIN BLOCK DIAGRAM
MCLRE
Data Bus
MCLR/VPP/RA5
RD TRISA
Schmitt
Trigger
RD LATA
Latch
Q
D
EN
RD PORTA
High-Voltage Detect
HV
Internal MCLR
Filter
Low-Level
MCLR Detect
TABLE 10-1: PORTA FUNCTIONS
Name
RA0/AN0
Bit#
Buffer
Function
bit 0
bit 1
bit 2
bit 3
bit 4
ST
ST
ST
ST
ST
Input/output port pin or analog input.
RA1/AN1/LVDIN
RA2/AN2/VREF-
RA3/AN3/VREF+
RA4/T0CKI
Input/output port pin, analog input or Low-Voltage Detect input.
Input/output port pin, analog input or VREF-.
Input/output port pin, analog input or VREF+.
Input/output port pin or external clock input for Timer0.
Output is open-drain type.
MCLR/VPP/RA5
bit 5
ST
Master Clear input or programming voltage input (if MCLR is enabled); input
only port pin or programming voltage input (if MCLR is disabled).
OSC2/CLKO/RA6
OSC1/CLKI/RA7
bit 6
bit 7
ST
ST
OSC2, clock output or I/O pin.
OSC1, clock input or I/O pin.
Legend: TTL = TTL input, ST = Schmitt Trigger input
TABLE 10-2: SUMMARY OF REGISTERS ASSOCIATED WITH PORTA
Value on
all other
Resets
Value on
POR, BOR
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PORTA
LATA
RA7(1)
LATA7(1) LATA6(1)
TRISA7(1) TRISA6(1)
RA6(1)
RA5(2)
—
RA4
RA3
RA2
RA1
RA0 xx0x 0000 uu0u 0000
xx-x xxxx uu-u uuuu
11-1 1111 11-1 1111
LATA Data Output Register
PORTA Data Direction Register
TRISA
ADCON1
—
—
PCFG6 PCFG5 PCFG4 PCFG3 PCFG2 PCFG1 PCFG0 -000 0000 -000 0000
Legend: x= unknown, u= unchanged, – = unimplemented locations read as ‘0’. Shaded cells are not used by PORTA.
Note 1: RA7:RA6 and their associated latch and data direction bits are enabled as I/O pins based on oscillator
configuration; otherwise, they are read as ‘0’.
2: RA5 is an input only if MCLR is disabled.
© 2007 Microchip Technology Inc.
DS39605F-page 89
PIC18F1220/1320
This interrupt can wake the device from Sleep. The
user, in the Interrupt Service Routine, can clear the
interrupt in the following manner:
10.2 PORTB, TRISB and LATB
Registers
PORTB is an 8-bit wide, bidirectional port. The corre-
sponding data direction register is TRISB. Setting a
TRISB bit (= 1) will make the corresponding PORTB
pin an input (i.e., put the corresponding output driver in
a high-impedance mode). Clearing a TRISB bit (= 0)
will make the corresponding PORTB pin an output (i.e.,
put the contents of the output latch on the selected pin).
a) Any read or write of PORTB (except with the
MOVFF instruction). This will end the mismatch
condition.
b) Clear flag bit, RBIF.
A mismatch condition will continue to set flag bit, RBIF.
Reading PORTB will end the mismatch condition and
allow flag bit, RBIF, to be cleared.
The Data Latch register (LATB) is also memory
mapped. Read-modify-write operations on the LATB
register read and write the latched output value for
PORTB.
The interrupt-on-change feature is recommended for
wake-up on key depression operation and operations
where PORTB is only used for the interrupt-on-change
feature. Polling of PORTB is not recommended while
using the interrupt-on-change feature.
EXAMPLE 10-2:
INITIALIZING PORTB
CLRF
PORTB
LATB
0x70
; Initialize PORTB by
; clearing output
; data latches
; Alternate method
; to clear output
; data latches
FIGURE 10-7:
BLOCK DIAGRAM OF
RB0/AN4/INT0 PIN
CLRF
VDD
RBPU(2)
Weak
Pull-up
P
Analog Input Mode
Data Bus
MOVLW
MOVWF
MOVLW
; Set RB0, RB1, RB4 as
ADCON1 ; digital I/O pins
0xCF
D
Q
; Value used to
; initialize data
; direction
; Set RB<3:0> as inputs
; RB<5:4> as outputs
; RB<7:6> as inputs
I/O
WR LATB
or PORTB
pin(1)
CK
Data Latch
MOVWF
TRISB
D
Q
WR TRISB
CK
TRIS Latch
TTL
Input
Buffer
Pins RB0-RB2 are multiplexed with INT0-INT2; pins
RB0, RB1 and RB4 are multiplexed with A/D inputs;
pins RB1 and RB4 are multiplexed with EUSART; and
pins RB2, RB3, RB6 and RB7 are multiplexed with
ECCP.
RD TRISB
RD LATB
Each of the PORTB pins has a weak internal pull-up. A
single control bit can turn on all the pull-ups. This is
performed by clearing bit, RBPU (INTCON2<7>). The
weak pull-up is automatically turned off when the port
pin is configured as an output. The pull-ups are
disabled on a Power-on Reset.
Q
D
EN
RD PORTB
Schmitt Trigger
Buffer
INTx
Note:
On a Power-on Reset, RB4:RB0 are
configured as analog inputs by default and
read as ‘0’; RB7:RB5 are configured as
digital inputs.
To A/D Converter
Note 1: I/O pins have diode protection to VDD and VSS.
2: To enable weak pull-ups, set the appropriate TRIS
bit(s) and clear the RBPU bit (INTCON2<7>).
Four of the PORTB pins (RB7:RB4) have an interrupt-
on-change feature. Only pins configured as inputs can
cause this interrupt to occur (i.e., any RB7:RB4 pin
configured as an output is excluded from the interrupt-
on-change comparison). The input pins (of RB7:RB4)
are compared with the old value latched on the last
read of PORTB. The “mismatch” outputs of RB7:RB4
are OR’ed together to generate the RB Port Change
Interrupt with Flag bit, RBIF (INTCON<0>).
DS39605F-page 90
© 2007 Microchip Technology Inc.
PIC18F1220/1320
FIGURE 10-8:
BLOCK DIAGRAM OF RB1/AN5/TX/CK/INT1 PIN
EUSART Enable
1
0
TX/CK Data
TX/CK TRIS
VDD
Weak
RBPU(2)
Analog Input Mode
P
Pull-up
Data Latch
Data Bus
D
Q
RB1 pin(1)
WR LATB
or
PORTB
CK
TRIS Latch
D
Q
WR TRISB
CK
TTL
Input
Buffer
RD TRISB
RD LATB
Q
D
RD PORTB
EN
RD PORTB
Schmitt
Trigger
Input
Buffer
INT1/CK Input
Analog Input
Mode
To A/D Converter
Note 1: I/O pins have diode protection to VDD and VSS.
2: To enable weak pull-ups, set the appropriate TRIS bit(s) and clear the RBPU bit (INTCON2<7>).
© 2007 Microchip Technology Inc.
DS39605F-page 91
PIC18F1220/1320
FIGURE 10-9:
BLOCK DIAGRAM OF RB2/P1B/INT2 PIN
VDD
Weak
RBPU(2)
P
Pull-up
P1B Enable
P1B Data
1
0
P1B/D Tri-State
Auto-Shutdown
Data Latch
Data Bus
D
Q
RB2 pin(1)
WR LATB or
PORTB
CK
TRIS Latch
D
Q
TTL
Input
Buffer
WR TRISB
CK
RD TRISB
RD LATB
D
Q
RD PORTB
EN
Schmitt
Trigger
RD PORTB
INT2 Input
Note 1: I/O pins have diode protection to VDD and VSS.
2: To enable weak pull-ups, set the appropriate TRIS bit(s) and clear the RBPU bit (INTCON2<7>).
DS39605F-page 92
© 2007 Microchip Technology Inc.
PIC18F1220/1320
FIGURE 10-10:
BLOCK DIAGRAM OF RB3/CCP1/P1A PIN
ECCP1(3) pin Output Enable
ECCP1(4) pin Input Enable
RBPU(2)
VDD
Weak
P
Pull-up
P1A/C Tri-State Auto-Shutdown
ECCP1/P1A Data Out
VDD
P
1
0
RD LATB
Data Bus
D
Q
WR LATB or
PORTB
RB3 pin
Q
CK
Data Latch
N
D
Q
Q
VSS
WR TRISB
CK
TTL Input
Buffer
TRIS Latch
RD TRISB
Q
D
EN
RD PORTB
ECCP1 Input
Schmitt
Trigger
Note 1: I/O pins have diode protection to VDD and VSS.
2: To enable weak pull-ups, set the appropriate TRIS bit(s) and clear the RBPU bit (INTCON2<7>).
3: ECCP1 pin output enable active for any PWM mode and Compare mode, where CCP1M<3:0> = 1000or 1001.
4: ECCP1 pin input enable active for Capture mode only.
© 2007 Microchip Technology Inc.
DS39605F-page 93
PIC18F1220/1320
FIGURE 10-11:
BLOCK DIAGRAM OF RB4/AN6/RX/DT/KBI0 PIN
EUSART Enabled
VDD
RBPU(2)
Analog Input Mode
DT TRIS
Weak
P
Pull-up
DT Data
1
0
RD LATB
Data Bus
D
Q
Q
WR LATB or
PORTB
RB4 pin
CK
Data Latch
D
Q
Q
WR TRISB
CK
TRIS Latch
TTL
Input
Buffer
RD TRISB
Q
D
Q1
EN
RD PORTB
Set RBIF
Q
D
From other
RB7:RB4 pins
RD PORTB
Q3
EN
Schmitt
Trigger
RX/DT Input
Analog Input
Mode
To A/D Converter
Note 1: I/O pins have diode protection to VDD and VSS.
2: To enable weak pull-ups, set the appropriate TRIS bit(s) and clear the RBPU bit (INTCON2<7>).
DS39605F-page 94
© 2007 Microchip Technology Inc.
PIC18F1220/1320
FIGURE 10-12:
BLOCK DIAGRAM OF RB5/PGM/KBI1 PIN
VDD
RBPU(2)
Weak
P
Pull-up
Data Latch
Data Bus
D
Q
I/O pin(1)
WR LATB
or PORTB
CK
TRIS Latch
D
Q
WR TRISB
TTL
CK
Input
Buffer
ST
Buffer
RD TRISB
RD LATB
Latch
Q
D
RD PORTB
Set RBIF
EN
Q1
Q
D
RD PORTB
Q3
From other
RB7:RB5 and
RB4 pins
EN
RB7:RB5 in Serial Programming Mode
Note 1: I/O pins have diode protection to VDD and VSS.
2: To enable weak pull-ups, set the appropriate TRIS bit(s) and clear the RBPU bit
(INTCON2<7>).
© 2007 Microchip Technology Inc.
DS39605F-page 95
PIC18F1220/1320
FIGURE 10-13:
BLOCK DIAGRAM OF RB6/PGC/T1OSO/T13CKI/P1C/KBI2 PIN
ECCP1 P1C/D Enable
VDD
Weak
RBPU(2)
P
Pull-up
P1B/D Tri-State Auto-Shutdown
P1C Data
1
0
RD LATB
Data Bus
D
Q
Q
WR LATB or
PORTB
RB6 pin
CK
Data Latch
D
Q
Q
WR TRISB
CK
Timer1
Oscillator
TRIS Latch
From RB7 pin
TTL
Buffer
Schmitt
Trigger
RD TRISB
T1OSCEN
Q
D
Q1
EN
RD PORTB
Set RBIF
Q
D
From other
RB7:RB4 pins
RD PORTB
Q3
EN
PGC
T13CKI
Note 1: I/O pins have diode protection to VDD and VSS.
2: To enable weak pull-ups, set the appropriate TRIS bit(s) and clear the RBPU bit (INTCON2<7>).
DS39605F-page 96
© 2007 Microchip Technology Inc.
PIC18F1220/1320
FIGURE 10-14:
BLOCK DIAGRAM OF RB7/PGD/T1OSI/P1D/KBI3 PIN
VDD
Weak
ECCP1 P1C/D Enable
RBPU(2)
P
Pull-up
P1B/D Tri-State Auto-Shutdown
P1D Data
To RB6 pin
1
0
RD LATB
Data Bus
D
Q
Q
WR LATB or
PORTB
RB7 pin
CK
Data Latch
D
Q
Q
WR TRISB
T1OSCEN
CK
TRIS Latch
TTL
Input
Buffer
Schmitt
Trigger
RD TRISB
Q
D
Q1
EN
RD PORTB
Set RBIF
Q
D
From other
RB7:RB4 pins
RD PORTB
Q3
EN
PGD
Note 1: I/O pins have diode protection to VDD and VSS.
2: To enable weak pull-ups, set the appropriate TRIS bit(s) and clear the RBPU bit (INTCON2<7>).
© 2007 Microchip Technology Inc.
DS39605F-page 97
PIC18F1220/1320
TABLE 10-3: PORTB FUNCTIONS
Name
RB0/AN4/INT0
Bit#
Buffer
Function
bit 0
TTL(1)/ST(2) Input/output port pin, analog input or external interrupt
input 0.
RB1/AN5/TX/CK/INT1
bit 1
TTL(1)/ST(2) Input/output port pin, analog input, Enhanced USART
Asynchronous Transmit, Addressable USART
Synchronous Clock or external interrupt input 1.
RB2/P1B/INT2
bit 2
bit 3
bit 4
TTL(1)/ST(2) Input/output port pin or external interrupt input 2.
Internal software programmable weak pull-up.
TTL(1)/ST(3) Input/output port pin or Capture1 input/Compare1 output/
PWM output. Internal software programmable weak pull-up.
TTL(1)/ST(4) Input/output port pin (with interrupt-on-change), analog input,
Enhanced USART Asynchronous Receive or Addressable
USART Synchronous Data.
RB3/CCP1/P1A
RB4/AN6/RX/DT/KBI0
RB5/PGM/KBI1
bit 5
TTL(1)/ST(5) Input/output port pin (with interrupt-on-change).
Internal software programmable weak pull-up.
Low-Voltage ICSP enable pin.
RB6/PGC/T1OSO/T13CKI/
P1C/KBI2
bit 6 TTL(1)/ST(5,6) Input/output port pin (with interrupt-on-change), Timer1/
Timer3 clock input or Timer1oscillator output.
Internal software programmable weak pull-up.
Serial programming clock.
RB7/PGD/T1OSI/P1D/KBI3
bit 7
TTL(1)/ST(5) Input/output port pin (with interrupt-on-change) or Timer1
oscillator input. Internal software programmable weak pull-up.
Serial programming data.
Legend: TTL = TTL input, ST = Schmitt Trigger input
Note 1: This buffer is a TTL input when configured as a port input pin.
2: This buffer is a Schmitt Trigger input when configured as the external interrupt.
3: This buffer is a Schmitt Trigger input when configured as the CCP1 input.
4: This buffer is a Schmitt Trigger input when used as EUSART receive input.
5: This buffer is a Schmitt Trigger input when used in Serial Programming mode.
6: This buffer is a TTL input when used as the T13CKI input.
TABLE 10-4: SUMMARY OF REGISTERS ASSOCIATED WITH PORTB
Value on
all other
Resets
Value on
POR, BOR
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PORTB
LATB
RB7
RB6
RB5
RB4
RB3
RB2
RB1
RB0
xxxq qqqq
xxxx xxxx
1111 1111
0000 000x
1111 -1-1
uuuu uuuu
uuuu uuuu
1111 1111
0000 000u
1111 -1-1
11-0 0-00
-000 0000
LATB Data Output Register
TRISB
PORTB Data Direction Register
GIE/GIEH PEIE/GIEL TMR0IE
INTCON
INTCON2
INTCON3
ADCON1
Legend:
INT0IE
RBIE
—
TMR0IF INT0IF
RBIF
RBIP
RBPU
INT2IP
—
INTEDG0 INTEDG1 INTEDG2
TMR0IP
—
—
INT1IP
PCFG6
—
INT2IE
PCFG4
INT1IE
INT2IF
INT1IF 11-0 0-00
PCFG5
PCFG3 PCFG2 PCFG1 PCFG0 -000 0000
x= unknown, u= unchanged, q= value depends on condition. Shaded cells are not used by PORTB.
DS39605F-page 98
© 2007 Microchip Technology Inc.
PIC18F1220/1320
Figure 11-1 shows a simplified block diagram of the
Timer0 module in 8-bit mode and Figure 11-2 shows a
simplified block diagram of the Timer0 module in 16-bit
mode.
11.0 TIMER0 MODULE
The Timer0 module has the following features:
• Software selectable as an 8-bit or 16-bit timer/
counter
The T0CON register (Register 11-1) is a readable and
writable register that controls all the aspects of Timer0,
including the prescale selection.
• Readable and writable
• Dedicated 8-bit software programmable prescaler
• Clock source selectable to be external or internal
• Interrupt-on-overflow from FFh to 00h in 8-bit
mode and FFFFh to 0000h in 16-bit mode
• Edge select for external clock
REGISTER 11-1: T0CON: TIMER0 CONTROL REGISTER
R/W-1
TMR0ON
bit 7
R/W-1
R/W-1
T0CS
R/W-1
T0SE
R/W-1
PSA
R/W-1
T0PS2
R/W-1
T0PS1
R/W-1
T0PS0
T08BIT
bit 0
bit 7
bit 6
bit 5
bit 4
bit 3
TMR0ON: Timer0 On/Off Control bit
1= Enables Timer0
0= Stops Timer0
T08BIT: Timer0 8-bit/16-bit Control bit
1= Timer0 is configured as an 8-bit timer/counter
0= Timer0 is configured as a 16-bit timer/counter
T0CS: Timer0 Clock Source Select bit
1= Transition on T0CKI pin
0= Internal instruction cycle clock (CLKO)
T0SE: Timer0 Source Edge Select bit
1= Increment on high-to-low transition on T0CKI pin
0= Increment on low-to-high transition on T0CKI pin
PSA: Timer0 Prescaler Assignment bit
1= TImer0 prescaler is NOT assigned. Timer0 clock input bypasses prescaler.
0= Timer0 prescaler is assigned. Timer0 clock input comes from prescaler output.
bit 2-0 T0PS2:T0PS0: Timer0 Prescaler Select bits
111= 1:256 Prescale value
110= 1:128 Prescale value
101= 1:64 Prescale value
100= 1:32 Prescale value
011= 1:16 Prescale value
010= 1:8 Prescale value
001= 1:4 Prescale value
000= 1:2 Prescale value
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
© 2007 Microchip Technology Inc.
DS39605F-page 99
PIC18F1220/1320
FIGURE 11-1:
TIMER0 BLOCK DIAGRAM IN 8-BIT MODE
Data Bus
TMR0
FOSC/4
0
1
RA4/T0CKI
pin
8
1
Sync with
Internal
Clocks
Programmable
Prescaler
0
(2 TCY Delay)
T0SE
3
PSA
Set Interrupt
Flag bit TMR0IF
on Overflow
T0PS2, T0PS1, T0PS0
T0CS
Note:
Upon Reset, Timer0 is enabled in 8-bit mode with clock input from T0CKI maximum prescale.
FIGURE 11-2:
TIMER0 BLOCK DIAGRAM IN 16-BIT MODE
RA4/T0CKI
pin
FOSC/4
0
1
Sync with
Internal
Clocks
Set Interrupt
Flag bit TMR0IF
on Overflow
TMR0
High Byte
1
TMR0L
Programmable
Prescaler
0
8
(2 TCY Delay)
T0SE
3
Read TMR0L
Write TMR0L
T0PS2, T0PS1, T0PS0
T0CS
PSA
8
8
TMR0H
8
Data Bus<7:0>
Note:
Upon Reset, Timer0 is enabled in 8-bit mode with clock input from T0CKI maximum prescale.
DS39605F-page 100
© 2007 Microchip Technology Inc.
PIC18F1220/1320
11.2.1
SWITCHING PRESCALER
ASSIGNMENT
11.1 Timer0 Operation
Timer0 can operate as a timer or as a counter.
The prescaler assignment is fully under software
control (i.e., it can be changed “on-the-fly” during
program execution).
Timer mode is selected by clearing the T0CS bit. In
Timer mode, the Timer0 module will increment every
instruction cycle (without prescaler). If the TMR0 regis-
ter is written, the increment is inhibited for the following
two instruction cycles. The user can work around this
by writing an adjusted value to the TMR0 register.
11.3 Timer0 Interrupt
The TMR0 interrupt is generated when the TMR0 reg-
ister overflows from FFh to 00h in 8-bit mode, or FFFFh
to 0000h in 16-bit mode. This overflow sets the TMR0IF
bit. The interrupt can be masked by clearing the
TMR0IE bit. The TMR0IF bit must be cleared in soft-
ware by the Timer0 module Interrupt Service Routine
before re-enabling this interrupt. The TMR0 interrupt
cannot awaken the processor from Low-Power Sleep
mode, since the timer requires clock cycles even when
T0CS is set.
Counter mode is selected by setting the T0CS bit. In
Counter mode, Timer0 will increment either on every
rising or falling edge of pin RA4/T0CKI. The increment-
ing edge is determined by the Timer0 Source Edge
Select bit (T0SE). Clearing the T0SE bit selects the
rising edge.
When an external clock input is used for Timer0, it must
meet certain requirements. The requirements ensure
the external clock can be synchronized with the internal
phase clock (TOSC). Also, there is a delay in the actual
incrementing of Timer0 after synchronization.
11.4 16-Bit Mode Timer Reads
and Writes
11.2 Prescaler
TMR0H is not the high byte of the timer/counter in
16-bit mode, but is actually a buffered version of the
high byte of Timer0 (refer to Figure 11-2). The high byte
of the Timer0 counter/timer is not directly readable nor
writable. TMR0H is updated with the contents of the
high byte of Timer0 during a read of TMR0L. This pro-
vides the ability to read all 16 bits of Timer0, without
having to verify that the read of the high and low byte
were valid due to a rollover between successive reads
of the high and low byte.
An 8-bit counter is available as a prescaler for the Timer0
module. The prescaler is not readable or writable.
The PSA and T0PS2:T0PS0 bits determine the
prescaler assignment and prescale ratio.
Clearing bit PSA will assign the prescaler to the Timer0
module. When the prescaler is assigned to the Timer0
module, prescale values of 1:2, 1:4, ..., 1:256 are
selectable.
When assigned to the Timer0 module, all instructions
writing to the TMR0 register (e.g., CLRF TMR0, MOVWF
TMR0, BSF TMR0, x, ..., etc.) will clear the prescaler
count.
A write to the high byte of Timer0 must also take place
through the TMR0H Buffer register. Timer0 high byte is
updated with the contents of TMR0H when a write
occurs to TMR0L. This allows all 16 bits of Timer0 to be
updated at once.
Note:
Writing to TMR0 when the prescaler is
assigned to Timer0 will clear the prescaler
count, but will not change the prescaler
assignment.
TABLE 11-1: REGISTERS ASSOCIATED WITH TIMER0
Value on
all other
Resets
Value on
POR, BOR
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
TMR0L
TMR0H
INTCON
T0CON
TRISA
Timer0 Module Low Byte Register
Timer0 Module High Byte Register
xxxx xxxx uuuu uuuu
0000 0000 0000 0000
0000 000x 0000 000u
1111 1111 1111 1111
11-1 1111 11-1 1111
GIE/GIEH PEIE/GIEL TMR0IE INT0IE
RBIE
PSA
TMR0IF INT0IF
T0PS2 T0PS1
RBIF
TMR0ON
T08BIT
T0CS
—
T0SE
T0PS0
(1)
(1)
RA7
RA6
PORTA Data Direction Register
Legend:
x= unknown, u= unchanged, – = unimplemented locations read as ‘0’. Shaded cells are not used by Timer0.
Note 1: RA6 and RA7 are enabled as I/O pins, depending on the oscillator mode selected in Configuration Word 1H.
© 2007 Microchip Technology Inc.
DS39605F-page 101
PIC18F1220/1320
NOTES:
DS39605F-page 102
© 2007 Microchip Technology Inc.
PIC18F1220/1320
Register 12-1 details the Timer1 Control register. This
register controls the operating mode of the Timer1
module and contains the Timer1 Oscillator Enable bit
(T1OSCEN). Timer1 can be enabled or disabled by
setting or clearing control bit, TMR1ON (T1CON<0>).
12.0 TIMER1 MODULE
The Timer1 module timer/counter has the following
features:
• 16-bit timer/counter
(two 8-bit registers: TMR1H and TMR1L)
The Timer1 oscillator can be used as a secondary clock
source in power managed modes. When the T1RUN bit
is set, the Timer1 oscillator is providing the system
clock. If the Fail-Safe Clock Monitor is enabled and the
Timer1 oscillator fails while providing the system clock,
polling the T1RUN bit will indicate whether the clock is
being provided by the Timer1 oscillator or another
source.
• Readable and writable (both registers)
• Internal or external clock select
• Interrupt-on-overflow from FFFFh to 0000h
• Reset from CCP module special event trigger
• Status of system clock operation
Figure 12-1 is a simplified block diagram of the Timer1
module.
Timer1 can also be used to provide Real-Time Clock
(RTC) functionality to applications, with only a minimal
addition of external components and code overhead.
REGISTER 12-1: T1CON: TIMER1 CONTROL REGISTER
R/W-0
RD16
R-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
T1RUN T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON
bit 0
bit 7
bit 7
bit 6
RD16: 16-bit Read/Write Mode Enable bit
1= Enables register read/write of TImer1 in one 16-bit operation
0= Enables register read/write of Timer1 in two 8-bit operations
T1RUN: Timer1 System Clock Status bit
1= System clock is derived from Timer1 oscillator
0= System clock is derived from another source
bit 5-4 T1CKPS1:T1CKPS0: Timer1 Input Clock Prescale Select bits
11= 1:8 Prescale value
10= 1:4 Prescale value
01= 1:2 Prescale value
00= 1:1 Prescale value
bit 3
bit 2
T1OSCEN: Timer1 Oscillator Enable bit
1= Timer1 oscillator is enabled
0= Timer1 oscillator is shut off
The oscillator inverter and feedback resistor are turned off to eliminate power drain.
T1SYNC: Timer1 External Clock Input Synchronization Select bit
When TMR1CS = 1:
1= Do not synchronize external clock input
0= Synchronize external clock input
When TMR1CS = 0:
This bit is ignored. Timer1 uses the internal clock when TMR1CS = 0.
bit 1
bit 0
TMR1CS: Timer1 Clock Source Select bit
1= External clock from pin RB6/PGC/T1OSO/T13CKI/P1C/KBI2 (on the rising edge)
0= Internal clock (Fosc/4)
TMR1ON: Timer1 On bit
1= Enables Timer1
0= Stops Timer1
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
© 2007 Microchip Technology Inc.
DS39605F-page 103
PIC18F1220/1320
When TMR1CS = 0, Timer1 increments every instruc-
tion cycle. When TMR1CS = 1, Timer1 increments on
every rising edge of the external clock input, or the
Timer1 oscillator, if enabled.
12.1 Timer1 Operation
Timer1 can operate in one of these modes:
• As a timer
• As a synchronous counter
• As an asynchronous counter
When the Timer1 oscillator is enabled (T1OSCEN is
set), the RB7/PGD/T1OSI/P1D/KBI3 and RB6/T1OSO/
T13CKI/P1C/KBI2 pins become inputs. That is, the
TRISB7:TRISB6 values are ignored and the pins read
as ‘0’.
The operating mode is determined by the clock select
bit, TMR1CS (T1CON<1>).
Timer1 also has an internal “Reset input”. This Reset
can be generated by the CCP module (see
Section 15.4.4 “Special Event Trigger”).
FIGURE 12-1:
TIMER1 BLOCK DIAGRAM
CCP Special Event Trigger
TMR1IF
Overflow
Interrupt
Flag bit
Synchronized
TMR1
CLR
0
Clock Input
TMR1L
TMR1H
T1OSC
1
TMR1ON
On/Off
T1SYNC
1
T13CKI/T1OSO
T1OSI
Synchronize
det
T1OSCEN
Enable
Oscillator
Prescaler
1, 2, 4, 8
FOSC/4
Internal
Clock
(1)
0
2
Peripheral Clocks
T1CKPS1:T1CKPS0
TMR1CS
Note 1: When enable bit, T1OSCEN, is cleared, the inverter and feedback resistor are turned off. This eliminates
power drain.
FIGURE 12-2:
TIMER1 BLOCK DIAGRAM: 16-BIT READ/WRITE MODE
Data Bus<7:0>
8
TMR1H
8
8
Write TMR1L
Read TMR1L
CCP Special Event Trigger
TMR1IF
Overflow
Interrupt
Synchronized
Clock Input
TMR1
8
0
CLR
Timer 1
High Byte
TMR1L
Flag bit
1
TMR1ON
on/off
T1SYNC
T1OSC
T13CKI/T1OSO
1
Synchronize
Prescaler
1, 2, 4, 8
T1OSCEN
det
FOSC/4
Internal
Clock
Enable
0
(1)
T1OSI
Oscillator
2
Peripheral Clocks
TMR1CS
T1CKPS1:T1CKPS0
Note 1: When enable bit, T1OSCEN, is cleared, the inverter and feedback resistor are turned off. This eliminates power drain.
DS39605F-page 104
© 2007 Microchip Technology Inc.
PIC18F1220/1320
FIGURE 12-3:
EXTERNAL
12.2 Timer1 Oscillator
COMPONENTS FOR THE
TIMER1 LP OSCILLATOR
A crystal oscillator circuit is built-in between pins T1OSI
(input) and T1OSO (amplifier output). It is enabled by
setting control bit, T1OSCEN (T1CON<3>). The oscil-
lator is a low-power oscillator rated for 32 kHz crystals.
It will continue to run during all power managed modes.
The circuit for a typical LP oscillator is shown in
Figure 12-3. Table 12-1 shows the capacitor selection
for the Timer1 oscillator.
C1
22 pF
PIC18FXXXX
PGD
PGD/T1OSI
XTAL
32.768 kHz
The user must provide a software time delay to ensure
proper start-up of the Timer1 oscillator.
PGC/T1OSO
C2
22 pF
PGC
Note:
The Timer1 oscillator shares the T1OSI
and T1OSO pins with the PGD and PGC
pins used for programming and
debugging.
Note:
See the Notes with Table 12-1 for additional
information about capacitor selection.
When using the Timer1 oscillator, In-Circuit
Serial Programming (ICSP) may not
function correctly (high voltage or low
voltage), or the In-Circuit Debugger (ICD)
may not communicate with the controller.
As a result of using either ICSP or ICD, the
Timer1 crystal may be damaged.
TABLE 12-1: CAPACITOR SELECTION FOR
THE TIMER OSCILLATOR
Osc Type
Freq
C1
C2
LP
32 kHz
22 pF(1)
22 pF(1)
Note 1: Microchip suggests this value as a starting
point in validating the oscillator circuit.
Oscillator operation should then be tested
to ensure expected performance under
all expected conditions (VDD and
temperature).
If ICSP or ICD operations are required, the
crystal should be disconnected from the
circuit (disconnect either lead), or installed
after programming. The oscillator loading
capacitors may remain in-circuit during
ICSP or ICD operation.
2: Higher capacitance increases the stability
of the oscillator, but also increases the
start-up time.
3: Since each resonator/crystal has its own
characteristics, the user should consult
the resonator/crystal manufacturer for
appropriate
values
of
external
components.
4: Capacitor values are for design guidance
only.
© 2007 Microchip Technology Inc.
DS39605F-page 105
PIC18F1220/1320
12.3 Timer1 Oscillator Layout
Considerations
12.5 Resetting Timer1 Using a CCP
Trigger Output
The Timer1 oscillator circuit draws very little power
during operation. Due to the low-power nature of the
oscillator, it may also be sensitive to rapidly changing
signals in close proximity.
If the CCP module is configured in Compare mode
to generate
a
“special
event
trigger”
(CCP1M3:CCP1M0 = 1011), this signal will reset
Timer1 and start an A/D conversion, if the A/D mod-
ule is enabled (see Section 15.4.4 “Special Event
Trigger” for more information).
The oscillator circuit, shown in Figure 12-3, should be
located as close as possible to the microcontroller.
There should be no circuits passing within the oscillator
circuit boundaries other than VSS or VDD.
Note:
The special event triggers from the CCP1
module will not set interrupt flag bit,
TMR1IF (PIR1<0>).
If a high-speed circuit must be located near the oscilla-
tor (such as the CCP1 pin in output compare or PWM
mode, or the primary oscillator using the OSC2 pin), a
grounded guard ring around the oscillator circuit, as
shown in Figure 12-4, may be helpful when used on a
single sided PCB, or in addition to a ground plane.
Timer1 must be configured for either Timer or Synchro-
nized Counter mode to take advantage of this feature.
If Timer1 is running in Asynchronous Counter mode,
this Reset operation may not work.
In the event that a write to Timer1 coincides with a
special event trigger from CCP1, the write will take
precedence.
FIGURE 12-4:
OSCILLATOR CIRCUIT
WITH GROUNDED
GUARD RING
In this mode of operation, the CCPR1H:CCPR1L regis-
ter pair effectively becomes the period register for
Timer1.
RA1
RB2
12.6 Timer1 16-Bit Read/Write Mode
RA4
C2
X1
C3
OSC1
OSC2
Timer1 can be configured for 16-bit reads and writes
(see Figure 12-2). When the RD16 control bit
(T1CON<7>) is set, the address for TMR1H is mapped
to a buffer register for the high byte of Timer1. A read
from TMR1L will load the contents of the high byte of
Timer1 into the Timer1 high byte buffer. This provides
the user with the ability to accurately read all 16 bits of
Timer1 without having to determine whether a read of
the high byte, followed by a read of the low byte, is
valid, due to a rollover between reads.
MCLR
C1
VSS
VDD
RA2
RA3
RB7
RB6
C4
X2
C5
A write to the high byte of Timer1 must also take place
through the TMR1H Buffer register. Timer1 high byte is
updated with the contents of TMR1H when a write
occurs to TMR1L. This allows a user to write all 16 bits
to both the high and low bytes of Timer1 at once.
RB0
RB5
Note: Not drawn to scale.
The high byte of Timer1 is not directly readable or
writable in this mode. All reads and writes must take
place through the Timer1 High Byte Buffer register.
Writes to TMR1H do not clear the Timer1 prescaler.
The prescaler is only cleared on writes to TMR1L.
12.4 Timer1 Interrupt
The TMR1 register pair (TMR1H:TMR1L) increments
from 0000h to FFFFh and rolls over to 0000h. The
Timer1 interrupt, if enabled, is generated on overflow,
which is latched in interrupt flag bit, TMR1IF
(PIR1<0>). This interrupt can be enabled/disabled by
setting/clearing Timer1 Interrupt Enable bit, TMR1IE
(PIE1<0>).
DS39605F-page 106
© 2007 Microchip Technology Inc.
PIC18F1220/1320
Since the register pair is 16 bits wide, counting up to
overflow the register directly from a 32.768 kHz clock
would take 2 seconds. To force the overflow at the
required one-second intervals, it is necessary to pre-
load it; the simplest method is to set the MSb of TMR1H
with a BSFinstruction. Note that the TMR1L register is
never preloaded or altered; doing so may introduce
cumulative error over many cycles.
12.7 Using Timer1 as a
Real-Time Clock
Adding an external LP oscillator to Timer1 (such as the
one described in Section 12.2 “Timer1 Oscillator”,
above), gives users the option to include RTC function-
ality to their applications. This is accomplished with an
inexpensive watch crystal to provide an accurate time
base and several lines of application code to calculate
the time. When operating in Sleep mode and using a
battery or supercapacitor as a power source, it can
completely eliminate the need for a separate RTC
device and battery backup.
For this method to be accurate, Timer1 must operate in
Asynchronous mode and the Timer1 overflow interrupt
must be enabled (PIE1<0> = 1), as shown in the
routine, RTCinit. The Timer1 oscillator must also be
enabled and running at all times.
The application code routine, RTCisr, shown in
Example 12-1, demonstrates a simple method to
increment a counter at one-second intervals using an
Interrupt Service Routine. Incrementing the TMR1 reg-
ister pair to overflow, triggers the interrupt and calls the
routine, which increments the seconds counter by one;
additional counters for minutes and hours are
incremented as the previous counter overflow.
EXAMPLE 12-1:
IMPLEMENTING A REAL-TIME CLOCK USING A TIMER1 INTERRUPT SERVICE
RTCinit
MOVLW
MOVWF
CLRF
0x80
TMR1H
TMR1L
; Preload TMR1 register pair
; for 1 second overflow
MOVLW
MOVWF
CLRF
b’00001111’
T1OSC
secs
; Configure for external clock,
; Asynchronous operation, external oscillator
; Initialize timekeeping registers
;
CLRF
mins
MOVLW
MOVWF
BSF
.12
hours
PIE1, TMR1IE
; Enable Timer1 interrupt
RETURN
RTCisr
BSF
BCF
INCF
MOVLW
TMR1H, 7
PIR1, TMR1IF
secs, F
.59
; Preload for 1 sec overflow
; Clear interrupt flag
; Increment seconds
; 60 seconds elapsed?
CPFSGT secs
RETURN
; No, done
CLRF
INCF
MOVLW
secs
mins, F
.59
; Clear seconds
; Increment minutes
; 60 minutes elapsed?
CPFSGT mins
RETURN
; No, done
CLRF
INCF
MOVLW
mins
hours, F
.23
; clear minutes
; Increment hours
; 24 hours elapsed?
CPFSGT hours
RETURN
; No, done
MOVLW
MOVWF
RETURN
.01
hours
; Reset hours to 1
; Done
© 2007 Microchip Technology Inc.
DS39605F-page 107
PIC18F1220/1320
TABLE 12-2: REGISTERS ASSOCIATED WITH TIMER1 AS A TIMER/COUNTER
Value on
all other
Resets
Value on
POR, BOR
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
INTCON GIE/GIEH PEIE/GIEL TMR0IE
INT0IE
TXIF
RBIE
—
TMR0IF
INT0IF
RBIF
0000 000x 0000 000u
PIR1
—
—
—
ADIF
ADIE
ADIP
RCIF
RCIE
RCIP
CCP1IF TMR2IF TMR1IF -000 -000 -000 -000
CCP1IE TMR2IE TMR1IE -000 -000 -000 -000
CCP1IP TMR2IP TMR1IP -111 -111 -111 -111
PIE1
TXIE
TXIP
—
IPR1
—
TMR1L
Holding Register for the Least Significant Byte of the 16-bit TMR1 Register
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
TMR1H Holding Register for the Most Significant Byte of the 16-bit TMR1 Register
T1CON
RD16
T1RUN T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 0000 0000 u0uu uuuu
Legend:
x= unknown, u= unchanged, – = unimplemented, read as ‘0’. Shaded cells are not used by the Timer1 module.
DS39605F-page 108
© 2007 Microchip Technology Inc.
PIC18F1220/1320
13.1 Timer2 Operation
13.0 TIMER2 MODULE
Timer2 can be used as the PWM time base for the
PWM mode of the CCP module. The TMR2 register is
readable and writable and is cleared on any device
Reset. The input clock (FOSC/4) has a prescale option
of 1:1, 1:4 or 1:16, selected by control bits,
T2CKPS1:T2CKPS0 (T2CON<1:0>). The match out-
put of TMR2 goes through a 4-bit postscaler (which
gives a 1:1 to 1:16 scaling inclusive) to generate a
TMR2 interrupt (latched in flag bit, TMR2IF (PIR1<1>)).
The Timer2 module timer has the following features:
• 8-bit timer (TMR2 register)
• 8-bit period register (PR2)
• Readable and writable (both registers)
• Software programmable prescaler (1:1, 1:4, 1:16)
• Software programmable postscaler (1:1 to 1:16)
• Interrupt on TMR2 match with PR2
Timer2 has a control register shown in Register 13-1.
TMR2 can be shut off by clearing control bit, TMR2ON
(T2CON<2>), to minimize power consumption.
Figure 13-1 is a simplified block diagram of the Timer2
module. Register 13-1 shows the Timer2 Control
register. The prescaler and postscaler selection of
Timer2 are controlled by this register.
The prescaler and postscaler counters are cleared
when any of the following occurs:
• A write to the TMR2 register
• A write to the T2CON register
• Any device Reset (Power-on Reset, MCLR Reset,
Watchdog Timer Reset or Brown-out Reset)
TMR2 is not cleared when T2CON is written.
REGISTER 13-1: T2CON: TIMER2 CONTROL REGISTER
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0
bit 0
bit 7
bit 7
Unimplemented: Read as ‘0’
bit 6-3 TOUTPS3:TOUTPS0: Timer2 Output Postscale Select bits
0000= 1:1 Postscale
0001= 1:2 Postscale
•
•
•
1111= 1:16 Postscale
bit 2
TMR2ON: Timer2 On bit
1= Timer2 is on
0= Timer2 is off
bit 1-0 T2CKPS1:T2CKPS0: Timer2 Clock Prescale Select bits
00= Prescaler is 1
01= Prescaler is 4
1x= Prescaler is 16
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
© 2007 Microchip Technology Inc.
DS39605F-page 109
PIC18F1220/1320
13.2 Timer2 Interrupt
13.3 Output of TMR2
The Timer2 module has an 8-bit period register, PR2.
Timer2 increments from 00h until it matches PR2 and
then resets to 00h on the next increment cycle. PR2 is
a readable and writable register. The PR2 register is
initialized to FFh upon Reset.
The output of TMR2 (before the postscaler) is fed to the
Synchronous Serial Port module, which optionally uses
it to generate the shift clock.
FIGURE 13-1:
TIMER2 BLOCK DIAGRAM
Sets Flag
TMR2
bit TMR2IF
(1)
Output
Prescaler
Reset
EQ
TMR2
FOSC/4
1:1, 1:4, 1:16
Postscaler
1:1 to 1:16
2
Comparator
PR2
T2CKPS1:T2CKPS0
4
TOUTPS3:TOUTPS0
TABLE 13-1: REGISTERS ASSOCIATED WITH TIMER2 AS A TIMER/COUNTER
Value on
all other
Resets
Value on
POR, BOR
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
INTCON GIE/GIEH PEIE/GIEL TMR0IE
INT0IE
TXIF
RBIE
—
TMR0IF
CCP1IF
INT0IF
RBIF
0000 000x 0000 000u
PIR1
—
—
—
ADIF
ADIE
ADIP
RCIF
RCIE
RCIP
TMR2IF
TMR1IF -000 -000 -000 -000
TMR1IE -000 -000 -000 -000
TMR1IP -111 -111 -111 -111
0000 0000 0000 0000
PIE1
TXIE
TXIP
—
CCP1IE TMR2IE
CCP1IP TMR2IP
IPR1
—
TMR2
T2CON
PR2
Timer2 Module Register
—
TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 -000 0000
Timer2 Period Register 1111 1111 1111 1111
x= unknown, u= unchanged, – = unimplemented, read as ‘0’. Shaded cells are not used by the Timer2 module.
Legend:
DS39605F-page 110
© 2007 Microchip Technology Inc.
PIC18F1220/1320
Figure 14-1 is a simplified block diagram of the Timer3
module.
14.0 TIMER3 MODULE
The Timer3 module timer/counter has the following
features:
Register 14-1 shows the Timer3 Control register. This
register controls the operating mode of the Timer3
module and sets the CCP clock source.
• 16-bit timer/counter
(two 8-bit registers; TMR3H and TMR3L)
Register 12-1 shows the Timer1 Control register. This
register controls the operating mode of the Timer1
module, as well as contains the Timer1 Oscillator
Enable bit (T1OSCEN), which can be a clock source for
Timer3.
• Readable and writable (both registers)
• Internal or external clock select
• Interrupt-on-overflow from FFFFh to 0000h
• Reset from CCP module trigger
REGISTER 14-1: T3CON: TIMER3 CONTROL REGISTER
R/W-0
RD16
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
T3CKPS1 T3CKPS0 T3CCP1 T3SYNC TMR3CS TMR3ON
bit 0
bit 7
bit 7
bit 6
RD16: 16-bit Read/Write Mode Enable bit
1= Enables register read/write of Timer3 in one 16-bit operation
0= Enables register read/write of Timer3 in two 8-bit operations
Unimplemented: Read as ‘0’
bit 5-4 T3CKPS1:T3CKPS0: Timer3 Input Clock Prescale Select bits
11= 1:8 Prescale value
10= 1:4 Prescale value
01= 1:2 Prescale value
00= 1:1 Prescale value
bit 3
bit 2
T3CCP1: Timer3 and Timer1 to CCP1 Enable bits
1= Timer3 is the clock source for compare/capture CCP module
0= Timer1 is the clock source for compare/capture CCP module
T3SYNC: Timer3 External Clock Input Synchronization Control bit
(Not usable if the system clock comes from Timer1/Timer3.)
When TMR3CS = 1:
1= Do not synchronize external clock input
0= Synchronize external clock input
When TMR3CS = 0:
This bit is ignored. Timer3 uses the internal clock when TMR3CS = 0.
bit 1
bit 0
TMR3CS: Timer3 Clock Source Select bit
1= External clock input from Timer1 oscillator or T13CKI
(on the rising edge after the first falling edge)
0= Internal clock (FOSC/4)
TMR3ON: Timer3 On bit
1= Enables Timer3
0= Stops Timer3
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
© 2007 Microchip Technology Inc.
DS39605F-page 111
PIC18F1220/1320
When TMR3CS = 0, Timer3 increments every instruc-
tion cycle. When TMR3CS = 1, Timer3 increments on
every rising edge of the Timer1 external clock input or
the Timer1 oscillator, if enabled.
14.1 Timer3 Operation
Timer3 can operate in one of these modes:
• As a timer
• As a synchronous counter
• As an asynchronous counter
When the Timer1 oscillator is enabled (T1OSCEN is
set), the RB7/PGD/T1OSI/P1D/KBI3 and RB6/PGC/
T1OSO/T13CKI/P1C/KBI2 pins become inputs. That
is, the TRISB7:TRISB6 value is ignored and the pins
are read as ‘0’.
The operating mode is determined by the clock select
bit, TMR3CS (T3CON<1>).
Timer3 also has an internal “Reset input”. This Reset
can be generated by the CCP module (see
Section 15.4.4 “Special Event Trigger”).
FIGURE 14-1:
TIMER3 BLOCK DIAGRAM
CCP Special Event Trigger
T3CCPx
TMR3IF
Overflow
Interrupt
Synchronized
Clock Input
0
Flag bit
CLR
TMR3H
T1OSC
TMR3L
1
TMR3ON
On/Off
T3SYNC
T1OSO/
T13CKI
1
Synchronize
det
Prescaler
1, 2, 4, 8
T1OSCEN
Enable
Oscillator
FOSC/4
Internal
Clock
0
(1)
T1OSI
2
Peripheral Clocks
TMR3CS
T3CKPS1:T3CKPS0
Note 1: When enable bit, T1OSCEN, is cleared, the inverter and feedback resistor are turned off. This eliminates power drain.
FIGURE 14-2:
TIMER3 BLOCK DIAGRAM CONFIGURED IN 16-BIT READ/WRITE MODE
Data Bus<7:0>
8
TMR3H
8
8
Write TMR3L
Read TMR3L
CCP Special Event Trigger
T3CCPx
Synchronized
Clock Input
8
TMR3
Set TMR3IF Flag bit
on Overflow
0
CLR
Timer3
High Byte
TMR3L
1
To Timer1 Clock Input
TMR3ON
On/Off
T3SYNC
T1OSC
T1OSO/
T13CKI
1
Synchronize
det
Prescaler
1, 2, 4, 8
T1OSCEN
Enable
Oscillator
FOSC/4
Internal
Clock
0
(1)
T1OSI
2
Peripheral
Clocks
T3CKPS1:T3CKPS0
TMR3CS
Note 1: When the T1OSCEN bit is cleared, the inverter and feedback resistor are turned off. This eliminates power drain.
DS39605F-page 112
© 2007 Microchip Technology Inc.
PIC18F1220/1320
14.2 Timer1 Oscillator
14.4 Resetting Timer3 Using a CCP
Trigger Output
The Timer1 oscillator may be used as the clock source
for Timer3. The Timer1 oscillator is enabled by setting
the T1OSCEN (T1CON<3>) bit. The oscillator is a low-
power oscillator rated for 32 kHz crystals. See
Section 12.2 “Timer1 Oscillator” for further details.
If the CCP module is configured in Compare mode
to
generate
a
“special
event
trigger”
(CCP1M3:CCP1M0 = 1011), this signal will reset
Timer3. See Section 15.4.4 “Special Event Trigger”
for more information.
14.3 Timer3 Interrupt
Note:
The special event triggers from the CCP
module will not set interrupt flag bit,
TMR3IF (PIR1<0>).
The TMR3 register pair (TMR3H:TMR3L) increments
from 0000h to FFFFh and rolls over to 0000h. The
TMR3 interrupt, if enabled, is generated on overflow,
which is latched in interrupt flag bit, TMR3IF
(PIR2<1>). This interrupt can be enabled/disabled by
setting/clearing TMR3 Interrupt Enable bit, TMR3IE
(PIE2<1>).
Timer3 must be configured for either Timer or Synchro-
nized Counter mode to take advantage of this feature.
If Timer3 is running in Asynchronous Counter mode,
this Reset operation may not work. In the event that a
write to Timer3 coincides with a special event trigger
from CCP1, the write will take precedence. In this mode
of operation, the CCPR1H:CCPR1L register pair
effectively becomes the period register for Timer3.
TABLE 14-1: REGISTERS ASSOCIATED WITH TIMER3 AS A TIMER/COUNTER
Value on
all other
Resets
Value on
POR, BOR
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
INTCON
GIE/
GIEH
PEIE/
GIEL
TMR0IE
INT0IE
RBIE
TMR0IF
INT0IF
RBIF
0000 000x 0000 000u
PIR2
OSCFIF
OSCFIE
OSCFIP
—
—
—
—
—
—
EEIF
EEIE
EEIP
—
—
—
LVDIF
LVDIE
LVDIP
TMR3IF
TMR3IE
TMR3IP
—
—
—
0--0 -00- 0--0 -00-
0--0 -00- 0--0 -00-
1--1 -11- 1--1 -11-
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
PIE2
IPR2
TMR3L
TMR3H
T1CON
T3CON
Legend:
Holding Register for the Least Significant Byte of the 16-bit TMR3 Register
Holding Register for the Most Significant Byte of the 16-bit TMR3 Register
RD16
RD16
T1RUN T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 0000 0000 u0uu uuuu
T3CKPS1 T3CKPS0 T3CCP1 T3SYNC TMR3CS TMR3ON 0-00 0000 u-uu uuuu
—
x= unknown, u= unchanged, – = unimplemented, read as ‘0’. Shaded cells are not used by the Timer3 module.
© 2007 Microchip Technology Inc.
DS39605F-page 113
PIC18F1220/1320
NOTES:
DS39605F-page 114
© 2007 Microchip Technology Inc.
PIC18F1220/1320
The control register for CCP1 is shown in Register 15-1.
15.0 ENHANCED CAPTURE/
COMPARE/PWM (ECCP)
MODULE
In addition to the expanded functions of the CCP1CON
register, the ECCP module has two additional
registers associated with Enhanced PWM operation
and auto-shutdown features:
The Enhanced CCP module is implemented as a
standard CCP module with Enhanced PWM
capabilities. These capabilities allow for 2 or 4 output
channels, user-selectable polarity, dead-band control
and automatic shutdown and restart and are discussed
in detail in Section 15.5 “Enhanced PWM Mode”.
• PWM1CON
• ECCPAS
REGISTER 15-1: CCP1CON REGISTER FOR ENHANCED CCP OPERATION
R/W-0
P1M1
R/W-0
P1M0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
DC1B1
DC1B0
CCP1M3 CCP1M2 CCP1M1 CCP1M0
bit 0
bit 7
bit 7-6
P1M1:P1M0: PWM Output Configuration bits
If CCP1M<3:2> = 00, 01, 10:
xx= P1A assigned as Capture/Compare input; P1B, P1C, P1D assigned as port pins
If CCP1M<3:2> = 11:
00= Single output; P1A modulated; P1B, P1C, P1D assigned as port pins
01= Full-bridge output forward; P1D modulated; P1A active; P1B, P1C inactive
10= Half-bridge output; P1A, P1B modulated with dead-band control; P1C, P1D assigned as
port pins
11= Full-bridge output reverse; P1B modulated; P1C active; P1A, P1D inactive
bit 5-4
DC1B1:DC1B0: PWM Duty Cycle Least Significant bits
Capture mode:
Unused.
Compare mode:
Unused.
PWM mode:
These bits are the two LSbs of the PWM duty cycle. The eight MSbs are found in CCPR1L.
bit 3-0
CCP1M3:CCP1M0: ECCP1 Mode Select bits
0000= Capture/Compare/PWM off (resets ECCP module)
0001= Unused (reserved)
0010= Compare mode, toggle output on match (ECCP1IF bit is set)
0011= Unused (reserved)
0100= Capture mode, every falling edge
0101= Capture mode, every rising edge
0110= Capture mode, every 4th rising edge
0111= Capture mode, every 16th rising edge
1000= Compare mode, set output on match (ECCP1IF bit is set)
1001= Compare mode, clear output on match (ECCP1IF bit is set)
1010= Compare mode, generate software interrupt on match (ECCP1IF bit is set,
ECCP1 pin returns to port pin operation)
1011= Compare mode, trigger special event (ECCP1IF bit is set; ECCP resets TMR1 or
TMR3 and starts an A/D conversion if the A/D module is enabled)
1100= PWM mode; P1A, P1C active-high; P1B, P1D active-high
1101= PWM mode; P1A, P1C active-high; P1B, P1D active-low
1110= PWM mode; P1A, P1C active-low; P1B, P1D active-high
1111= PWM mode; P1A, P1C active-low; P1B, P1D active-low
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
© 2007 Microchip Technology Inc.
DS39605F-page 115
PIC18F1220/1320
To configure I/O pins as PWM outputs, the proper PWM
mode must be selected by setting the P1Mn and
15.1 ECCP Outputs
The Enhanced CCP module may have up to four
outputs, depending on the selected operating mode.
These outputs, designated P1A through P1D, are
multiplexed with I/O pins on PORTB. The pin
assignments are summarized in Table 15-1.
CCP1Mn
bits
(CCP1CON<7:6>
and
<3:0>,
respectively). The appropriate TRISB direction bits for
the port pins must also be set as outputs.
TABLE 15-1: PIN ASSIGNMENTS FOR VARIOUS ECCP MODES
CCP1CON
Configuration
ECCP Mode
RB3
RB2
RB6
RB7
Compatible CCP
Dual PWM
00xx 11xx
10xx 11xx
x1xx 11xx
CCP1
P1A
RB2/INT2 RB6/PGC/T1OSO/T13CKI/KBI2
RB7/PGD/T1OSI/KBI3
RB7/PGD/T1OSI/KBI3
P1D
P1B
P1B
RB6/PGC/T1OSO/T13CKI/KBI2
P1C
Quad PWM
P1A
Legend:
x= Don’t care. Shaded cells indicate pin assignments not used by ECCP in a given mode.
Note 1: TRIS register values must be configured appropriately.
15.3.1
CCP PIN CONFIGURATION
15.2 CCP Module
In Capture mode, the RB3/CCP1/P1A pin should be
configured as an input by setting the TRISB<3> bit.
Capture/Compare/PWM Register 1 (CCPR1) is com-
prised of two 8-bit registers: CCPR1L (low byte) and
CCPR1H (high byte). The CCP1CON register controls
the operation of CCP1. All are readable and writable.
Note:
If the RB3/CCP1/P1A is configured as an
output, a write to the port can cause a
capture condition.
TABLE 15-2: CCP MODE – TIMER
RESOURCE
15.3.2
TIMER1/TIMER3 MODE SELECTION
CCP Mode
Timer Resource
The timers that are to be used with the capture feature
(either Timer1 and/or Timer3) must be running in Timer
mode or Synchronized Counter mode. In Asynchro-
nous Counter mode, the capture operation may not
work. The timer to be used with the CCP module is
selected in the T3CON register.
Capture
Compare
PWM
Timer1 or Timer3
Timer1 or Timer3
Timer2
15.3 Capture Mode
15.3.3
SOFTWARE INTERRUPT
In Capture mode, CCPR1H:CCPR1L captures the 16-bit
value of the TMR1 or TMR3 registers when an event
occurs on pin RB3/CCP1/P1A. An event is defined as
one of the following:
When the Capture mode is changed, a false capture
interrupt may be generated. The user should keep bit,
CCP1IE (PIE1<2>), clear while changing capture
modes to avoid false interrupts and should clear the
flag bit, CCP1IF, following any such change in
operating mode.
• every falling edge
• every rising edge
• every 4th rising edge
• every 16th rising edge
The event is selected by control bits, CCP1M3:CCP1M0
(CCP1CON<3:0>). When a capture is made, the inter-
rupt request flag bit, CCP1IF (PIR1<2>), is set; it must
be cleared in software. If another capture occurs before
the value in register CCPR1 is read, the old captured
value is overwritten by the new captured value.
DS39605F-page 116
© 2007 Microchip Technology Inc.
PIC18F1220/1320
recommended method for switching between capture
prescalers. This example also clears the prescaler
counter and will not generate the “false” interrupt.
15.3.4
CCP PRESCALER
There are four prescaler settings, specified by bits
CCP1M3:CCP1M0. Whenever the CCP module is
turned off or the CCP module is not in Capture mode,
the prescaler counter is cleared. This means that any
Reset will clear the prescaler counter.
EXAMPLE 15-1:
CHANGING BETWEEN
CAPTURE PRESCALERS
CLRF
MOVLW
CCP1CON
NEW_CAPT_PS
; Turn CCP module off
; Load WREG with the
; new prescaler mode
; value and CCP ON
; Load CCP1CON with
; this value
Switching from one capture prescaler to another may
generate an interrupt. Also, the prescaler counter will
not be cleared; therefore, the first capture may be from
a
non-zero prescaler. Example 15-1 shows the
MOVWF
CCP1CON
FIGURE 15-1:
CAPTURE MODE OPERATION BLOCK DIAGRAM
TMR3H
TMR3L
CCPR1L
TMR1L
Set Flag bit CCP1IF
T3CCP1
T3CCP1
TMR3
Enable
Prescaler
÷ 1, 4, 16
CCP1 pin
CCPR1H
TMR1
Enable
and
Edge Detect
TMR1H
CCP1CON<3:0>
Q’s
15.4.2
TIMER1/TIMER3 MODE SELECTION
15.4 Compare Mode
Timer1 and/or Timer3 must be running in Timer mode
or Synchronized Counter mode if the CCP module is
using the compare feature. In Asynchronous Counter
mode, the compare operation may not work.
In Compare mode, the 16-bit CCPR1 register value is
constantly compared against either the TMR1 register
pair value, or the TMR3 register pair value. When a
match occurs, the RB3/CCP1/P1A pin:
• Is driven high
15.4.3
SOFTWARE INTERRUPT MODE
• Is driven low
When generate software interrupt is chosen, the RB3/
CCP1/P1A pin is not affected. CCP1IF is set and an
interrupt is generated (if enabled).
• Toggles output (high-to-low or low-to-high)
• Remains unchanged (interrupt only)
The action on the pin is based on the value of control
bits, CCP1M3:CCP1M0. At the same time, interrupt
flag bit, CCP1IF, is set.
15.4.4
SPECIAL EVENT TRIGGER
In this mode, an internal hardware trigger is generated,
which may be used to initiate an action.
15.4.1
CCP PIN CONFIGURATION
The special event trigger output of CCP1 resets the
TMR1 register pair. This allows the CCPR1 register to
effectively be a 16-bit programmable period register for
Timer1.
The user must configure the RB3/CCP1/P1A pin as an
output by clearing the TRISB<3> bit.
Note:
Clearing the CCP1CON register will force
the RB3/CCP1/P1A compare output latch
to the default low level. This is not the
PORTB I/O data latch.
The special event trigger also sets the GO/DONE bit
(ADCON0<1>). This starts a conversion of the
currently selected A/D channel if the A/D is on.
© 2007 Microchip Technology Inc.
DS39605F-page 117
PIC18F1220/1320
FIGURE 15-2:
COMPARE MODE OPERATION BLOCK DIAGRAM
Special Event Trigger will:
Reset Timer1 or Timer3, but does not set Timer1 or Timer3 interrupt flag bit
and set bit GO/DONE (ADCON0<2>), which starts an A/D conversion.
Special Event Trigger
Set Flag bit CCP1IF
CCPR1H CCPR1L
Comparator
Q
S
R
Output
Logic
Match
RB3/CCP1/P1A pin
TRISB<3>
Output Enable
1
CCP1CON<3:0>
Mode Select
0
T3CCP1
TMR1H TMR1L
TMR3H TMR3L
TABLE 15-3: REGISTERS ASSOCIATED WITH CAPTURE, COMPARE, TIMER1 AND TIMER3
Value on
all other
Resets
Value on
POR, BOR
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
INTCON
PIR1
GIE/GIEH PEIE/GIEL TMR0IE
INT0IE
TXIF
RBIE
—
TMR0IF
CCP1IF
INT0IF
RBIF
0000 000x 0000 000u
—
—
—
ADIF
ADIE
ADIP
RCIF
RCIE
RCIP
TMR2IF
TMR1IF -000 -000 -000 -000
PIE1
TXIE
TXIP
—
CCP1IE TMR2IE TMR1IE -000 -000 -000 -000
CCP1IP TMR2IP TMR1IP -111 -111 -111 -111
1111 1111 1111 1111
IPR1
—
TRISB
TMR1L
TMR1H
T1CON
CCPR1L
PORTB Data Direction Register
Holding Register for the Least Significant Byte of the 16-bit TMR1 Register
Holding Register for the Most Significant Byte of the 16-bit TMR1 Register
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
RD16
T1RUN T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 0000 0000 uuuu uuuu
Capture/Compare/PWM Register 1 (LSB)
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
CCPR1H Capture/Compare/PWM Register 1 (MSB)
CCP1CON
TMR3L
P1M1
P1M0
DC1B1
DC1B0
CCP1M3 CCP1M2 CCP1M1 CCP1M0 0000 0000 0000 0000
Holding Register for the Least Significant Byte of the 16-bit TMR3 Register
Holding Register for the Most Significant Byte of the 16-bit TMR3 Register
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
TMR3H
T3CON
RD16
—
T3CKPS1 T3CKPS0 T3CCP1 T3SYNC TMR3CS TMR3ON 0-00 0000 u-uu uuuu
CHS2 CHS1 CHS0 GO/DONE ADON 00-0 0000 00-0 0000
ADCON0
Legend:
VCFG1
VCFG0
—
x= unknown, u= unchanged, – = unimplemented, read as ‘0’. Shaded cells are not used by Capture and Timer1.
DS39605F-page 118
© 2007 Microchip Technology Inc.
PIC18F1220/1320
15.5.2
PWM DUTY CYCLE
15.5 Enhanced PWM Mode
The PWM duty cycle is specified by writing to the
CCPR1L register and to the CCP1CON<5:4> bits. Up
to 10-bit resolution is available. The CCPR1L contains
the eight MSbs and the CCP1CON<5:4> contains the
two LSbs. This 10-bit value is represented by
CCPR1L:CCP1CON<5:4>. The PWM duty cycle is
calculated by the equation:
The Enhanced PWM Mode provides additional PWM
output options for a broader range of control applica-
tions. The module is an upwardly compatible version of
the standard CCP module and offers up to four outputs,
designated P1A through P1D. Users are also able to
select the polarity of the signal (either active-high or
active-low). The module’s output mode and polarity are
configured by setting the P1M1:P1M0 and
CCP1M3CCP1M0 bits of the CCP1CON register
(CCP1CON<7:6> and CCP1CON<3:0>, respectively).
EQUATION 15-2: PWM DUTY CYCLE
PWM Duty Cycle = (CCPR1L:CCP1CON<5:4>) •
TOSC • (TMR2 Prescale Value)
Figure 15-3 shows a simplified block diagram of PWM
operation. All control registers are double-buffered and
are loaded at the beginning of a new PWM cycle (the
period boundary when Timer2 resets) in order to prevent
glitches on any of the outputs. The exception is the PWM
Delay register, ECCP1DEL, which is loaded at either the
duty cycle boundary or the boundary period (whichever
comes first). Because of the buffering, the module waits
until the assigned timer resets instead of starting imme-
diately. This means that Enhanced PWM waveforms do
not exactly match the standard PWM waveforms, but
are instead offset by one full instruction cycle (4 TOSC).
CCPR1L and CCP1CON<5:4> can be written to at any
time, but the duty cycle value is not copied into
CCPR1H until a match between PR2 and TMR2 occurs
(i.e., the period is complete). In PWM mode, CCPR1H
is a read-only register.
The CCPR1H register and a 2-bit internal latch are
used to double-buffer the PWM duty cycle. This
double-buffering is essential for glitchless PWM
operation. When the CCPR1H and 2-bit latch match
TMR2, concatenated with an internal 2-bit Q clock or
two bits of the TMR2 prescaler, the CCP1 pin is
cleared. The maximum PWM resolution (bits) for a
given PWM frequency is given by the equation:
As before, the user must manually configure the
appropriate TRIS bits for output.
EQUATION 15-3: PWM RESOLUTION
15.5.1
PWM PERIOD
FOSC
log
The PWM period is specified by writing to the PR2
register. The PWM period can be calculated using the
equation:
(
)
FPWM
bits
PWM Resolution (max) =
log(2)
EQUATION 15-1: PWM PERIOD
Note:
If the PWM duty cycle value is longer than
the PWM period, the CCP1 pin will not be
cleared.
PWM Period = [(PR2) + 1] • 4 • TOSC •
(TMR2 Prescale Value)
PWM frequency is defined as 1/[PWM period]. When
TMR2 is equal to PR2, the following three events occur
on the next increment cycle:
15.5.3
PWM OUTPUT CONFIGURATIONS
The P1M1:P1M0 bits in the CCP1CON register allow
one of four configurations:
• TMR2 is cleared
• Single Output
• The CCP1 pin is set (if PWM duty cycle = 0%, the
CCP1 pin will not be set)
• Half-Bridge Output
• Full-Bridge Output, Forward mode
• Full-Bridge Output, Reverse mode
• The PWM duty cycle is copied from CCPR1L into
CCPR1H
The Single Output mode is the Standard PWM mode
discussed in Section 15.5 “Enhanced PWM Mode”.
The Half-Bridge and Full-Bridge Output modes are
covered in detail in the sections that follow.
Note:
The Timer2 postscaler (see Section 13.0
“Timer2 Module”) is not used in the
determination of the PWM frequency. The
postscaler could be used to have a servo
update rate at a different frequency than
the PWM output.
The general relationship of the outputs in all
configurations is summarized in Figure 15-4.
TABLE 15-4: EXAMPLE PWM FREQUENCIES AND RESOLUTIONS AT 40 MHz
PWM Frequency
2.44 kHz
9.77 kHz
39.06 kHz
156.25 kHz
312.50 kHz
416.67 kHz
Timer Prescaler (1, 4, 16)
PR2 Value
16
FFh
10
4
1
1
3Fh
8
1
1Fh
7
1
FFh
10
FFh
10
17h
6.58
Maximum Resolution (bits)
© 2007 Microchip Technology Inc.
DS39605F-page 119
PIC18F1220/1320
FIGURE 15-3:
SIMPLIFIED BLOCK DIAGRAM OF THE ENHANCED PWM MODULE
CCP1CON<5:4>
P1M1<1:0>
CCP1M<3:0>
4
Duty Cycle Registers
2
CCPR1L
CCP1/P1A
RB3/CCP1/P1A
RB2/P1B/INT2
TRISB<3>
TRISB<2>
TRISB<6>
TRISB<7>
CCPR1H (Slave)
Comparator
P1B
Output
Controller
R
Q
RB6/PGC/T1OSO/T13CKI/
P1C/KBI2
P1C
(Note 1)
TMR2
S
P1D
RB7/PGD/T1OSI/P1D/KBI3
Comparator
PR2
Clear Timer,
set CCP1 pin and
latch D.C.
CCP1DEL
Note:
The 8-bit TMR2 register is concatenated with the 2-bit internal Q clock, or 2 bits of the prescaler to create the
10-bit time base.
FIGURE 15-4:
PWM OUTPUT RELATIONSHIPS (ACTIVE-HIGH STATE)
0
PR2+1
Duty
Cycle
SIGNAL
CCP1CON<7:6>
Period
P1A Modulated
P1A Modulated
P1B Modulated
P1A Active
(Single Output)
(Half-Bridge)
00
10
(1)
(1)
Delay
Delay
P1B Inactive
P1C Inactive
P1D Modulated
P1A Inactive
P1B Modulated
P1C Active
(Full-Bridge,
Forward)
01
(Full-Bridge,
Reverse)
11
P1D Inactive
DS39605F-page 120
© 2007 Microchip Technology Inc.
PIC18F1220/1320
FIGURE 15-5:
PWM OUTPUT RELATIONSHIPS (ACTIVE-LOW STATE)
0
PR2+1
Duty
Cycle
SIGNAL
CCP1CON<7:6>
Period
P1A Modulated
P1A Modulated
P1B Modulated
P1A Active
(Single Output)
(Half-Bridge)
00
10
(1)
(1)
Delay
Delay
P1B Inactive
P1C Inactive
P1D Modulated
P1A Inactive
P1B Modulated
P1C Active
(Full-Bridge,
Forward)
01
(Full-Bridge,
Reverse)
11
P1D Inactive
Relationships:
•
•
•
Period = 4 * TOSC * (PR2 + 1) * (TMR2 Prescale Value)
Duty Cycle = TOSC * (CCPR1L<7:0>:CCP1CON<5:4>) * (TMR2 Prescale Value)
Delay = 4 * TOSC * (PWM1CON<6:0>)
Note 1: Dead-band delay is programmed using the PWM1CON register (Section 15.5.6 “Programmable Dead-Band
Delay”).
© 2007 Microchip Technology Inc.
DS39605F-page 121
PIC18F1220/1320
The TRISB<3> and TRISB<2> bits must be cleared to
configure P1A and P1B as outputs.
15.5.4
HALF-BRIDGE MODE
In the Half-Bridge Output mode, two pins are used as
outputs to drive push-pull loads. The PWM output
signal is output on the RB3/CCP1/P1A pin, while the
complementary PWM output signal is output on the
RB2/P1B/INT2 pin (Figure 15-6). This mode can be
used for half-bridge applications, as shown in
Figure 15-7, or for full-bridge applications, where four
power switches are being modulated with two PWM
signals.
FIGURE 15-6:
HALF-BRIDGE PWM
OUTPUT (ACTIVE-HIGH)
Period
Period
Duty Cycle
P1A
P1B
td
In Half-Bridge Output mode, the programmable dead-
band delay can be used to prevent shoot-through
current in half-bridge power devices. The value of bits,
PDC6:PDC0 (PWM1CON<6:0>), sets the number of
instruction cycles before the output is driven active. If the
value is greater than the duty cycle, the corresponding
output remains inactive during the entire cycle. See
Section 15.5.6 “Programmable Dead-Band Delay”
for more details of the dead-band delay operations.
td
(1)
(1)
(1)
td = Dead-Band Delay
Note 1: At this time, the TMR2 register is equal to the
PR2 register.
FIGURE 15-7:
EXAMPLES OF HALF-BRIDGE OUTPUT MODE APPLICATIONS
Standard Half-Bridge Circuit (“Push-Pull”)
PIC18F1220/1320
FET
Driver
+
V
-
P1A
Load
FET
Driver
+
V
-
P1B
Half-Bridge Output Driving a Full-Bridge Circuit
V+
PIC18F1220/1320
FET
Driver
FET
Driver
P1A
Load
FET
FET
Driver
Driver
P1B
V-
DS39605F-page 122
© 2007 Microchip Technology Inc.
PIC18F1220/1320
The TRISB<3:2> and TRISB<7:6> bits must be cleared
to make the P1A, P1B, P1C and P1D pins output.
15.5.5
FULL-BRIDGE MODE
In Full-Bridge Output mode, four pins are used as
outputs; however, only two outputs are active at a time.
In the Forward mode, pin RB3/CCP1/P1A is continu-
ously active and pin RB7/PGD/T1OSI/P1D/KBI3 is
modulated. In the Reverse mode, pin RB6/PGC/
T1OSO/T13CKI/P1C/KBI2 is continuously active and
pin RB2/P1B/INT2 is modulated. These are illustrated
in Figure 15-8.
FIGURE 15-8:
FULL-BRIDGE PWM OUTPUT (ACTIVE-HIGH)
Forward Mode
Period
P1A
Duty Cycle
P1B
P1C
P1D
(1)
(1)
Reverse Mode
Period
Duty Cycle
P1A
P1B
P1C
P1D
(1)
(1)
Note 1: At this time, the TMR2 register is equal to the PR2 register.
© 2007 Microchip Technology Inc.
DS39605F-page 123
PIC18F1220/1320
FIGURE 15-9:
EXAMPLE OF FULL-BRIDGE APPLICATION
V+
PIC18F1220/1320
QC
QA
FET
Driver
FET
Driver
P1A
Load
P1B
FET
Driver
FET
Driver
P1C
P1D
QD
QB
V-
Figure 15-11 shows an example where the PWM direc-
tion changes from forward to reverse, at a near 100%
duty cycle. At time t1, the output P1A and P1D become
inactive, while output P1C becomes active. In this
example, since the turn-off time of the power devices is
longer than the turn-on time, a shoot-through current
may flow through power devices QC and QD (see
Figure 15-9) for the duration of ‘t’. The same phenom-
enon will occur to power devices QA and QB for PWM
direction change from reverse to forward.
15.5.5.1
Direction Change in Full-Bridge Mode
In the Full-Bridge Output mode, the P1M1 bit in the
CCP1CON register allows the user to control the
Forward/Reverse direction. When the application
firmware changes this direction control bit, the module
will assume the new direction on the next PWM cycle.
Just before the end of the current PWM period, the
modulated outputs (P1B and P1D) are placed in their
inactive state, while the unmodulated outputs (P1A and
P1C) are switched to drive in the opposite direction.
This occurs in a time interval of (4 TOSC * (Timer2
Prescale Value) before the next PWM period begins.
The Timer2 prescaler will be either 1,4 or 16, depend-
ing on the value of the T2CKPS bit (T2CON<1:0>).
During the interval from the switch of the unmodulated
outputs to the beginning of the next period, the
modulated outputs (P1B and P1D) remain inactive.
This relationship is shown in Figure 15-10.
If changing PWM direction at high duty cycle is required
for an application, one of the following requirements
must be met:
1. Reduce PWM for
changing directions.
a PWM period before
2. Use switch drivers that can drive the switches off
faster than they can drive them on.
Other options to prevent shoot-through current may
exist.
Note that in the Full-Bridge Output mode, the ECCP
module does not provide any dead-band delay. In
general, since only one output is modulated at all times,
dead-band delay is not required. However, there is a
situation where a dead-band delay might be required.
This situation occurs when both of the following
conditions are true:
1. The direction of the PWM output changes when
the duty cycle of the output is at or near 100%.
2. The turn-off time of the power switch, including
the power device and driver circuit, is greater
than the turn-on time.
DS39605F-page 124
© 2007 Microchip Technology Inc.
PIC18F1220/1320
FIGURE 15-10:
PWM DIRECTION CHANGE (ACTIVE-HIGH)
(1)
PWM Period
PWM Period
SIGNAL
P1A
P1B
DC
P1C
P1D
(2)
One Timer2 Count
DC
Note 1: The direction bit in the CCP1 Control register (CCP1CON<7>) is written any time during the PWM cycle.
2: When changing directions, the P1A and P1C toggle one Timer2 count before the end of the current PWM cycle.
The modulated P1B and P1D signals are inactive at this time.
FIGURE 15-11:
PWM DIRECTION CHANGE AT NEAR 100% DUTY CYCLE (ACTIVE-HIGH)
Forward Period
Reverse Period
t1
P1A
P1B
DC
P1C
P1D
DC
t
ON
External Switch C
External Switch D
t
OFF
Potential
Shoot-Through
Current
t = t
– t
ON
OFF
Note 1:
t
is the turn-on delay of power switch QC and its driver.
ON
2: t
is the turn-off delay of power switch QD and its driver.
OFF
© 2007 Microchip Technology Inc.
DS39605F-page 125
PIC18F1220/1320
A shutdown event can be caused by the INT0, INT1 or
INT2 pins (or any combination of these three sources).
The auto-shutdown feature can be disabled by not
selecting any auto-shutdown sources. The auto-
shutdown sources to be used are selected using the
ECCPAS2:ECCPAS0 bits (bits <6:4> of the ECCPAS
register).
15.5.6
PROGRAMMABLE DEAD-BAND
DELAY
In half-bridge applications where all power switches are
modulated at the PWM frequency at all times, the
power switches normally require more time to turn off
than to turn on. If both the upper and lower power
switches are switched at the same time (one turned on
and the other turned off), both switches may be on for
a short period of time until one switch completely turns
off. During this brief interval, a very high current (shoot-
through current) may flow through both power
switches, shorting the bridge supply. To avoid this
potentially destructive shoot-through current from flow-
ing during switching, turning on either of the power
switches is normally delayed to allow the other switch
to completely turn off.
When a shutdown occurs, the output pins are
asynchronously placed in their shutdown states, spec-
ified by the PSSAC1:PSSAC0 and PSSBD1:PSSBD0
bits (ECCPAS<3:0>). Each pin pair (P1A/P1C and
P1B/P1D) may be set to drive high, drive low or be tri-
stated (not driving). The ECCPASE bit (ECCPAS<7>)
is also set to hold the Enhanced PWM outputs in their
shutdown states.
The ECCPASE bit is set by hardware when a shutdown
event occurs. If automatic restarts are not enabled, the
ECCPASE bit is cleared by firmware when the cause of
the shutdown clears. If automatic restarts are enabled,
the ECCPASE bit is automatically cleared when the
cause of the auto-shutdown has cleared.
In the Half-Bridge Output mode, a digitally programmable
dead-band delay is available to avoid shoot-through
current from destroying the bridge power switches. The
delay occurs at the signal transition from the non-active
state to the active state. See Figure 15-6 for an illustra-
tion. The lower seven bits of the PWM1CON register
(Register 15-2) sets the delay period in terms of
microcontroller instruction cycles (TCY or 4 TOSC).
If the ECCPASE bit is set when a PWM period begins,
the PWM outputs remain in their shutdown state for that
entire PWM period. When the ECCPASE bit is cleared,
the PWM outputs will return to normal operation at the
beginning of the next PWM period.
15.5.7
ENHANCED PWM
AUTO-SHUTDOWN
Note:
Writing to the ECCPASE bit is disabled
while a shutdown condition is active.
When the ECCP is programmed for any of the
Enhanced PWM modes, the active output pins may be
configured for auto-shutdown. Auto-shutdown immedi-
ately places the Enhanced PWM output pins into a
defined shutdown state when a shutdown event
occurs.
REGISTER 15-2: PWM1CON: PWM CONFIGURATION REGISTER
R/W-0
R/W-0
PDC6
R/W-0
PDC5
R/W-0
PDC4
R/W-0
PDC3
R/W-0
PDC2
R/W-0
PDC1
R/W-0
PDC0
PRSEN
bit 7
bit 0
bit 7
PRSEN: PWM Restart Enable bit
1= Upon auto-shutdown, the ECCPASE bit clears automatically once the shutdown event
goes away; the PWM restarts automatically
0= Upon auto-shutdown, ECCPASE must be cleared in software to restart the PWM
bit 6-0
PDC<6:0>: PWM Delay Count bits
Number of FOSC/4 (4 * TOSC) cycles between the scheduled time when a PWM signal should
transition active and the actual time it transitions active.
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
DS39605F-page 126
© 2007 Microchip Technology Inc.
PIC18F1220/1320
REGISTER 15-3: ECCPAS: ENHANCED CAPTURE/COMPARE/PWM/AUTO-SHUTDOWN
CONTROL REGISTER
R/W-0 R/W-0
ECCPASE ECCPAS2 ECCPAS1 ECCPAS0 PSSAC1 PSSAC0 PSSBD1 PSSBD0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
bit 7
bit 0
bit 7
bit 6
bit 5
bit 4
bit 3-2
ECCPASE: ECCP Auto-Shutdown Event Status bit
0= ECCP outputs are operating
1= A shutdown event has occurred; ECCP outputs are in shutdown state
ECCPAS2: ECCP Auto-Shutdown bit 2
0= INT0 pin has no effect
1= INT0 pin low causes shutdown
ECCPAS1: ECCP Auto-Shutdown bit 1
0= INT2 pin has no effect
1= INT2 pin low causes shutdown
ECCPAS0: ECCP Auto-Shutdown bit 0
0= INT1 pin has no effect
1= INT1 pin low causes shutdown
PSSACn: Pins A and C Shutdown State Control bits
00= Drive Pins A and C to ‘0’
01= Drive Pins A and C to ‘1’
1x= Pins A and C tri-state
bit 1-0
PSSBDn: Pins B and D Shutdown State Control bits
00= Drive Pins B and D to ‘0’
01= Drive Pins B and D to ‘1’
1x= Pins B and D tri-state
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
© 2007 Microchip Technology Inc.
DS39605F-page 127
PIC18F1220/1320
15.5.7.1
Auto-Shutdown and
Automatic Restart
15.5.8
START-UP CONSIDERATIONS
When the ECCP module is used in the PWM mode, the
application hardware must use the proper external pull-
up and/or pull-down resistors on the PWM output pins.
When the microcontroller is released from Reset, all of
the I/O pins are in the high-impedance state. The
external circuits must keep the power switch devices in
the off state, until the microcontroller drives the I/O pins
with the proper signal levels, or activates the PWM
output(s).
The auto-shutdown feature can be configured to allow
automatic restarts of the module, following a shutdown
event. This is enabled by setting the PRSEN bit of the
PWM1CON register (PWM1CON<7>).
In Shutdown mode with PRSEN = 1(Figure 15-12), the
ECCPASE bit will remain set for as long as the cause
of the shutdown continues. When the shutdown
condition clears, the ECCPASE bit is automatically
cleared. If PRSEN = 0(Figure 15-13), once a shutdown
condition occurs, the ECCPASE bit will remain set until
it is cleared by firmware. Once ECCPASE is cleared,
the Enhanced PWM will resume at the beginning of the
next PWM period.
The CCP1M1:CCP1M0 bits (CCP1CON<1:0>) allow
the user to choose whether the PWM output signals are
active-high or active-low for each pair of PWM output
pins (P1A/P1C and P1B/P1D). The PWM output
polarities must be selected before the PWM pins are
configured as outputs. Changing the polarity configura-
tion while the PWM pins are configured as outputs is
not recommended, since it may result in damage to the
application circuits.
Note:
Writing to the ECCPASE bit is disabled
while a shutdown condition is active.
Independent of the PRSEN bit setting, the ECCPASE
bit cannot be cleared as long as the cause of the
shutdown persists.
The P1A, P1B, P1C and P1D output latches may not be
in the proper states when the PWM module is initialized.
Enabling the PWM pins for output at the same time as
the ECCP module may cause damage to the application
circuit. The ECCP module must be enabled in the proper
output mode and complete a full PWM cycle, before con-
figuring the PWM pins as outputs. The completion of a
full PWM cycle is indicated by the TMR2IF bit being set
as the second PWM period begins.
The Auto-Shutdown mode can be forced by writing a ‘1’
to the ECCPASE bit.
FIGURE 15-12:
PWM AUTO-SHUTDOWN (PRSEN = 1, AUTO-RESTART ENABLED)
PWM Period
PWM Period
PWM Period
PWM Activity
Dead Time
Duty Cycle
Dead Time
Duty Cycle
Dead Time
Duty Cycle
Shutdown Event
ECCPASE bit
FIGURE 15-13:
PWM AUTO-SHUTDOWN (PRSEN = 0, AUTO-RESTART DISABLED)
PWM Period
PWM Period
PWM Period
PWM Activity
Dead Time
Duty Cycle
Dead Time
Duty Cycle
Dead Time
Duty Cycle
Shutdown Event
ECCPASE bit
ECCPASE
Cleared by Firmware
DS39605F-page 128
© 2007 Microchip Technology Inc.
PIC18F1220/1320
15.5.9
SETUP FOR PWM OPERATION
15.5.10 OPERATION IN LOW-POWER
MODES
The following steps should be taken when configuring
the ECCP1 module for PWM operation:
In the Low-Power Sleep mode, all clock sources are
disabled. Timer2 will not increment and the state of the
module will not change. If the ECCP pin is driving a
value, it will continue to drive that value. When the
device wakes up, it will continue from this state. If Two-
Speed Start-ups are enabled, the initial start-up
frequency may not be stable if the INTOSC is being
used.
1. Configure the PWM pins P1A and P1B (and
P1C and P1D, if used) as inputs by setting the
corresponding TRISB bits.
2. Set the PWM period by loading the PR2 register.
3. Configure the ECCP module for the desired
PWM mode and configuration by loading the
CCP1CON register with the appropriate values:
In PRI_IDLE mode, the primary clock will continue to
clock the ECCP module without change.
• Select one of the available output
configurations and direction with the
P1M1:P1M0 bits.
In all other low-power modes, the selected low-power
mode clock will clock Timer2. Other low-power mode
clocks will most likely be different than the primary
clock frequency.
• Select the polarities of the PWM output
signals with the CCP1M3:CCP1M0 bits.
4. Set the PWM duty cycle by loading the CCPR1L
register and CCP1CON<5:4> bits.
15.5.10.1 Operation with Fail-Safe
Clock Monitor
5. For Half-Bridge Output mode, set the dead-
band delay by loading PWM1CON<6:0> with
the appropriate value.
If the Fail-Safe Clock Monitor is enabled
(CONFIG1H<6> is programmed), a clock failure will
force the device into the Low-Power RC_RUN mode
and the OSCFIF bit (PIR2<7>) will be set. The ECCP
will then be clocked from the INTRC clock source,
which may have a different clock frequency than the
primary clock. By loading the IRCF2:IRCF0 bits on
Resets, the user can enable the INTOSC at a high
clock speed in the event of a clock failure.
6. If auto-shutdown operation is required, load the
ECCPAS register:
• Select the auto-shutdown sources using the
ECCPAS<2:0> bits.
• Select the shutdown states of the PWM
output pins using PSSAC1:PSSAC0 and
PSSBD1:PSSBD0 bits.
• Set the ECCPASE bit (ECCPAS<7>).
See the previous section for additional details.
7. If auto-restart operation is required, set the
PRSEN bit (PWM1CON<7>).
15.5.11 EFFECTS OF A RESET
8. Configure and start TMR2:
Both power-on and subsequent Resets will force all
ports to input mode and the CCP registers to their
Reset states.
• Clear the TMR2 interrupt flag bit by clearing
the TMR2IF bit (PIR1<1>).
• Set the TMR2 prescale value by loading the
T2CKPS bits (T2CON<1:0>).
This forces the Enhanced CCP module to reset to a
state compatible with the standard CCP module.
• Enable Timer2 by setting the TMR2ON bit
(T2CON<2>).
9. Enable PWM outputs after a new PWM cycle
has started:
• Wait until TMR2 overflows (TMR2IF bit is set).
• Enable the CCP1/P1A, P1B, P1C and/or P1D
pin outputs by clearing the respective TRISB
bits.
• Clear the ECCPASE bit (ECCPAS<7>).
© 2007 Microchip Technology Inc.
DS39605F-page 129
PIC18F1220/1320
TABLE 15-5: REGISTERS ASSOCIATED WITH ENHANCED PWM AND TIMER2
Value on
all other
Resets
Value on
POR, BOR
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
INTCON
RCON
PIR1
GIE/GIEH PEIE/GIEL TMR0IE
INT0IE
RI
RBIE
TO
—
TMR0IF
PD
INT0IF
POR
RBIF
BOR
0000 000x 0000 000u
0--1 11qq 0--q qquu
IPEN
—
—
—
ADIF
ADIE
ADIP
RCIF
RCIE
RCIP
TXIF
TXIE
TXIP
CCP1IF TMR2IF TMR1IF -000 -000 -000 -000
CCP1IE TMR2IE TMR1IE -000 -000 -000 -000
CCP1IP TMR2IP TMR1IP -111 -111 -111 -111
0000 0000 0000 0000
PIE1
—
—
IPR1
—
—
TMR2
Timer2 Module Register
Timer2 Module Period Register
PR2
1111 1111 1111 1111
T2CON
TRISB
CCPR1H
CCPR1L
CCP1CON
ECCPAS
—
TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 -000 0000
PORTB Data Direction Register
1111 1111 1111 1111
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
Enhanced Capture/Compare/PWM Register 1 High Byte
Enhanced Capture/Compare/PWM Register 1 Low Byte
P1M1
P1M0
DC1B1
DC1B0
CCP1M3 CCP1M2 CCP1M1 CCP1M0 0000 0000 0000 0000
ECCPASE ECCPAS2 ECCPAS1 ECCPAS0 PSSAC1 PSSAC0 PSSBD1 PSSBD0 0000 0000 0000 0000
PWM1CON PRSEN
PDC6
IRCF2
PDC5
IRCF1
PDC4
IRCF0
PDC3
OSTS
PDC2
IOFS
PDC1
SCS1
PDC0
SCS0
0000 0000 uuuu uuuu
0000 qq00 0000 qq00
OSCCON
IDLEN
Legend:
x= unknown, u= unchanged, – = unimplemented, read as ‘0’.
Shaded cells are not used by the ECCP module in Enhanced PWM mode.
DS39605F-page 130
© 2007 Microchip Technology Inc.
PIC18F1220/1320
16.1 Asynchronous Operation in Power
Managed Modes
16.0 ENHANCED ADDRESSABLE
UNIVERSAL SYNCHRONOUS
ASYNCHRONOUS RECEIVER
TRANSMITTER (EUSART)
The EUSART may operate in Asynchronous mode
while the peripheral clocks are being provided by the
internal oscillator block. This makes it possible to
remove the crystal or resonator that is commonly
connected as the primary clock on the OSC1 and
OSC2 pins.
The Enhanced Addressable Universal Synchronous
Asynchronous Receiver Transmitter (EUSART) mod-
ule can be configured as a full-duplex asynchronous
system that can communicate with peripheral devices,
such as CRT terminals and personal computers. It can
also be configured as a half-duplex synchronous
system that can communicate with peripheral devices,
such as A/D or D/A integrated circuits, serial
EEPROMs, etc.
The factory calibrates the internal oscillator block out-
put (INTOSC) for 8 MHz (see Table 22-6). However,
this frequency may drift as VDD or temperature
changes and this directly affects the asynchronous
baud rate. Two methods may be used to adjust the
baud rate clock, but both require a reference clock
source of some kind.
The Enhanced Addressable USART module
implements additional features, including automatic
baud rate detection and calibration, automatic wake-up
on Sync Break reception and 12-bit Break character
transmit. These features make it ideally suited for use
in Local Interconnect Network (LIN) bus systems.
The first (preferred) method uses the OSCTUNE
register to adjust the INTOSC output back to 8 MHz.
Adjusting the value in the OSCTUNE register allows for
fine resolution changes to the system clock source (see
Section 3.6 “INTOSC Frequency Drift” for more
information).
The EUSART can be configured in the following
modes:
The other method adjusts the value in the Baud Rate
Generator (BRG). There may not be fine enough
resolution when adjusting the Baud Rate Generator to
compensate for a gradual change in the peripheral
clock frequency.
• Asynchronous (full duplex) with:
- Auto-wake-up on character reception
- Auto-baud calibration
- 12-bit Break character transmission
• Synchronous – Master (half duplex) with
selectable clock polarity
• Synchronous – Slave (half duplex) with selectable
clock polarity
The RB1/AN5/TX/CK/INT1 and RB4/AN6/RX/DT/KBI0
pins must be configured as follows for use with the
Universal Synchronous Asynchronous Receiver
Transmitter:
• SPEN (RCSTA<7>) bit must be set ( = 1),
• PCFG6:PCFG5 (ADCON1<5:6>) must be set ( = 1),
• TRISB<4> bit must be set ( = 1) and
• TRISB<1> bit must be set ( = 1).
Note:
The EUSART control will automatically
reconfigure the pin from input to output as
needed.
The operation of the Enhanced USART module is
controlled through three registers:
• Transmit Status and Control (TXSTA)
• Receive Status and Control (RCSTA)
• Baud Rate Control (BAUDCTL)
These are detailed in on the following pages in
Register 16-1, Register 16-2 and Register 16-3,
respectively.
© 2007 Microchip Technology Inc.
DS39605F-page 131
PIC18F1220/1320
REGISTER 16-1: TXSTA: TRANSMIT STATUS AND CONTROL REGISTER
R/W-0
CSRC
R/W-0
TX9
R/W-0
TXEN
R/W-0
SYNC
U-0
R/W-0
BRGH
R-1
R/W-0
TX9D
SENDB
TRMT
bit 7
bit 0
bit 7
CSRC: Clock Source Select bit
Asynchronous mode:
Don’t care.
Synchronous mode:
1= Master mode (clock generated internally from BRG)
0= Slave mode (clock from external source)
bit 6
bit 5
TX9: 9-bit Transmit Enable bit
1= Selects 9-bit transmission
0= Selects 8-bit transmission
TXEN: Transmit Enable bit
1= Transmit enabled
0= Transmit disabled
Note:
SREN/CREN overrides TXEN in Sync mode.
bit 4
bit 3
SYNC: EUSART Mode Select bit
1= Synchronous mode
0= Asynchronous mode
SENDB: Send Break Character bit
Asynchronous mode:
1= Send Sync Break on next transmission (cleared by hardware upon completion)
0= Sync Break transmission completed
Synchronous mode:
Don’t care.
bit 2
BRGH: High Baud Rate Select bit
Asynchronous mode:
1= High speed
0= Low speed
Synchronous mode:
Unused in this mode.
bit 1
bit 0
TRMT: Transmit Shift Register Status bit
1= TSR Idle
0= TSR busy
TX9D: 9th bit of Transmit Data
Can be address/data bit or a parity bit.
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
DS39605F-page 132
© 2007 Microchip Technology Inc.
PIC18F1220/1320
REGISTER 16-2: RCSTA: RECEIVE STATUS AND CONTROL REGISTER
R/W-0
SPEN
R/W-0
RX9
R/W-0
SREN
R/W-0
CREN
R/W-0
R-0
R-0
R-x
ADDEN
FERR
OERR
RX9D
bit 7
bit 0
bit 7
bit 6
bit 5
SPEN: Serial Port Enable bit
1= Serial port enabled (configures RX/DT and TX/CK pins as serial port pins)
0= Serial port disabled (held in Reset)
RX9: 9-bit Receive Enable bit
1= Selects 9-bit reception
0= Selects 8-bit reception
SREN: Single Receive Enable bit
Asynchronous mode:
Don’t care.
Synchronous mode – Master:
1= Enables single receive
0= Disables single receive
This bit is cleared after reception is complete.
Synchronous mode – Slave:
Don’t care.
bit 4
CREN: Continuous Receive Enable bit
Asynchronous mode:
1= Enables receiver
0= Disables receiver
Synchronous mode:
1= Enables continuous receive until enable bit, CREN, is cleared (CREN overrides SREN)
0= Disables continuous receive
bit 3
ADDEN: Address Detect Enable bit
Asynchronous mode 9-bit (RX9 = 1):
1= Enables address detection, generates RCIF interrupt and loads RCREG when RX9D is set
0= Disables address detection, all bytes are received and ninth bit can be used as parity bit
Asynchronous mode 8-bit (RX9 = 0):
Don’t care.
bit 2
bit 1
bit 0
FERR: Framing Error bit
1= Framing error (can be updated by reading RCREG register and receiving next valid byte)
0= No framing error
OERR: Overrun Error bit
1= Overrun error (can be cleared by clearing bit CREN)
0= No overrun error
RX9D: 9th bit of Received Data
This can be address/data bit or a parity bit and must be calculated by user firmware.
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
© 2007 Microchip Technology Inc.
DS39605F-page 133
PIC18F1220/1320
REGISTER 16-3: BAUDCTL: BAUD RATE CONTROL REGISTER
U-0
—
R-1
U-0
—
R/W-0
SCKP
R/W-0
U-0
—
R/W-0
WUE
R/W-0
RCIDL
BRG16
ABDEN
bit 7
bit 0
bit 7
bit 6
Unimplemented: Read as ‘0’
RCIDL: Receive Operation Idle Status bit
1= Receiver is Idle
0= Receiver is busy
bit 5
bit 4
Unimplemented: Read as ‘0’
SCKP: Synchronous Clock Polarity Select bit
Asynchronous mode:
Unused in this mode.
Synchronous mode:
1= Idle state for clock (CK) is a high level
0= Idle state for clock (CK) is a low level
bit 3
BRG16: 16-bit Baud Rate Register Enable bit
1= 16-bit Baud Rate Generator – SPBRGH and SPBRG
0= 8-bit Baud Rate Generator – SPBRG only (Compatible mode), SPBRGH value ignored
bit 2
bit 1
Unimplemented: Read as ‘0’
WUE: Wake-up Enable bit
Asynchronous mode:
1= EUSART will continue to sample the RX pin – interrupt generated on falling edge; bit
cleared in hardware on following rising edge
0= RX pin not monitored or rising edge detected
Synchronous mode:
Unused in this mode.
bit 0
ABDEN: Auto-Baud Detect Enable bit
Asynchronous mode:
1= Enable baud rate measurement on the next character – requires reception of a Sync byte
(55h); cleared in hardware upon completion
0= Baud rate measurement disabled or completed
Synchronous mode:
Unused in this mode.
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
DS39605F-page 134
© 2007 Microchip Technology Inc.
PIC18F1220/1320
16.2.1
POWER MANAGED MODE
OPERATION
16.2 EUSART Baud Rate Generator
(BRG)
The system clock is used to generate the desired baud
rate; however, when a power managed mode is
entered, the clock source may be operating at a differ-
ent frequency than in PRI_RUN mode. In Sleep mode,
no clocks are present and in PRI_IDLE mode, the
primary clock source continues to provide clocks to the
Baud Rate Generator; however, in other power
managed modes, the clock frequency will probably
change. This may require the value in SPBRG to be
adjusted.
The BRG is a dedicated 8-bit or 16-bit generator, that
supports both the Asynchronous and Synchronous
modes of the EUSART. By default, the BRG operates
in 8-bit mode; setting the BRG16 bit (BAUDCTL<3>)
selects 16-bit mode.
The SPBRGH:SPBRG register pair controls the period
of a free running timer. In Asynchronous mode, bits
BRGH (TXSTA<2>) and BRG16 also control the baud
rate. In Synchronous mode, bit BRGH is ignored.
Table 16-1 shows the formula for computation of the
baud rate for different EUSART modes which only
apply in Master mode (internally generated clock).
If the system clock is changed during an active receive
operation, a receive error or data loss may result. To
avoid this problem, check the status of the RCIDL bit
and make sure that the receive operation is Idle before
changing the system clock.
Given the desired baud rate and FOSC, the nearest
integer value for the SPBRGH:SPBRG registers can be
calculated using the formulas in Table 16-1. From this,
the error in baud rate can be determined. An example
calculation is shown in Example 16-1. Typical baud
rates and error values for the various asynchronous
modes are shown in Table 16-2. It may be
advantageous to use the high baud rate (BRGH = 1),
or the 16-bit BRG to reduce the baud rate error, or
achieve a slow baud rate for a fast oscillator frequency.
16.2.2
SAMPLING
The data on the RB4/AN6/RX/DT/KBI0 pin is sampled
three times by a majority detect circuit to determine if a
high or a low level is present at the RX pin.
Writing a new value to the SPBRGH:SPBRG registers
causes the BRG timer to be reset (or cleared). This
ensures the BRG does not wait for a timer overflow
before outputting the new baud rate.
TABLE 16-1: BAUD RATE FORMULAS
Configuration Bits
BRG/EUSART Mode
Baud Rate Formula
SYNC
BRG16
BRGH
0
0
0
0
1
1
0
0
1
1
0
1
0
1
0
1
x
x
8-bit/Asynchronous
8-bit/Asynchronous
16-bit/Asynchronous
16-bit/Asynchronous
8-bit/Synchronous
16-bit/Synchronous
FOSC/[64 (n + 1)]
FOSC/[16 (n + 1)]
FOSC/[4 (n + 1)]
Legend: x= Don’t care, n = value of SPBRGH:SPBRG register pair
EXAMPLE 16-1: CALCULATING BAUD RATE ERROR
For a device with FOSC of 16 MHz, desired baud rate of 9600, Asynchronous mode, 8-bit BRG:
Desired Baud Rate FOSC/(64 ([SPBRGH:SPBRG] + 1))
Solving for SPBRGH:SPBRG:
=
X
=
=
=
((FOSC/Desired Baud Rate)/64) – 1
((16000000/9600)/64) – 1
[25.042] = 25
Calculated Baud Rate= 16000000/(64 (25 + 1))
=
=
=
9615
Error
(Calculated Baud Rate – Desired Baud Rate)/Desired Baud Rate
(9615 – 9600)/9600 = 0.16%
© 2007 Microchip Technology Inc.
DS39605F-page 135
PIC18F1220/1320
TABLE 16-2: REGISTERS ASSOCIATED WITH BAUD RATE GENERATOR
Value on
POR, BOR
Value on all
other Resets
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
TXSTA
CSRC
SPEN
—
TX9
RX9
TXEN
SREN
—
SYNC
CREN
SCKP
SENDB
ADDEN
BRG16
BRGH
FERR
—
TRMT
OERR
WUE
TX9D
RX9D
0000 -010
0000 -00x
0000 -010
0000 -00x
-1-1 0-00
0000 0000
0000 0000
RCSTA
BAUDCTL
RCIDL
ABDEN -1-1 0-00
0000 0000
SPBRGH Baud Rate Generator Register High Byte
SPBRG
Baud Rate Generator Register Low Byte
x= unknown, – = unimplemented, read as ‘0’. Shaded cells are not used by the BRG.
0000 0000
Legend:
TABLE 16-3: BAUD RATES FOR ASYNCHRONOUS MODES
SYNC = 0, BRGH = 0, BRG16 = 0
BAUD
RATE
(K)
FOSC = 40.000 MHz
FOSC = 20.000 MHz
FOSC = 10.000 MHz
FOSC = 8.000 MHz
Actual
Rate
(K)
SPBRG Actual
value
SPBRG Actual
value
(decimal)
SPBRG Actual
value
(decimal)
SPBRG
value
%
%
Error
%
Error
%
Error
Rate
(K)
Rate
(K)
Rate
(K)
Error
(decimal)
(decimal)
0.3
1.2
—
—
—
—
—
—
—
255
129
31
15
4
—
—
—
129
64
15
7
—
1201
2403
9615
—
—
-0.16
-0.16
-0.16
—
—
103
51
12
—
—
—
1.221
1.73
0.16
1.73
1.73
8.51
-9.58
1.202
2.404
9.766
19.531
52.083
78.125
0.16
0.16
1.73
1.73
-9.58
-32.18
2.4
2.441
9.615
19.531
56.818
125.000
1.73
0.16
1.73
-1.36
8.51
255
64
31
10
4
2.404
9.6
9.766
19.2
57.6
115.2
19.531
62.500
104.167
2
—
—
—
2
1
—
—
—
SYNC = 0, BRGH = 0, BRG16 = 0
BAUD
RATE
(K)
FOSC = 4.000 MHz
FOSC = 2.000 MHz
FOSC = 1.000 MHz
Actual
Rate
(K)
SPBRG Actual
value
SPBRG Actual
value
(decimal)
SPBRG
value
(decimal)
%
%
Error
%
Error
Rate
(K)
Rate
(K)
Error
(decimal)
0.3
1.2
0.300
1.202
0.16
0.16
207
51
25
6
300
1201
2403
—
-0.16
-0.16
-0.16
—
103
25
12
—
300
1201
—
-0.16
-0.16
—
51
12
—
—
—
—
—
2.4
2.404
0.16
9.6
8.929
-6.99
8.51
—
—
19.2
57.6
115.2
20.833
62.500
62.500
2
—
—
—
—
—
8.51
0
—
—
—
—
—
-45.75
0
—
—
—
—
—
DS39605F-page 136
© 2007 Microchip Technology Inc.
PIC18F1220/1320
TABLE 16-3: BAUD RATES FOR ASYNCHRONOUS MODES (CONTINUED)
SYNC = 0, BRGH = 1, BRG16 = 0
BAUD
RATE
(K)
FOSC = 40.000 MHz
FOSC = 20.000 MHz FOSC = 10.000 MHz
FOSC = 8.000 MHz
Actual
Rate
(K)
SPBRG Actual
value
SPBRG Actual
SPBRG Actual
value
(decimal)
SPBRG
value
(decimal)
%
%
Error
%
Error
%
Error
Rate
(K)
value
Rate
(K)
Rate
(K)
Error
(decimal)
(decimal)
2.4
9.6
—
—
—
255
129
42
—
—
—
129
64
2.441
9.615
1.73
0.16
1.73
-1.36
8.51
255
64
31
10
4
2403
9615
19230
55555
—
-0.16
-0.16
-0.16
3.55
—
207
51
25
8
9.766
1.73
0.16
0.94
-1.36
9.615
0.16
0.16
-1.36
-1.36
19.2
57.6
115.2
19.231
58.140
113.636
19.231
56.818
113.636
19.531
56.818
125.000
21
21
10
—
SYNC = 0, BRGH = 1, BRG16 = 0
BAUD
RATE
(K)
FOSC = 4.000 MHz
FOSC = 2.000 MHz
FOSC = 1.000 MHz
Actual
Rate
(K)
SPBRG Actual
value
SPBRG Actual
value
(decimal)
SPBRG
value
(decimal)
%
%
Error
%
Error
Rate
(K)
Rate
(K)
Error
(decimal)
0.3
1.2
—
—
—
207
103
25
12
3
—
1201
2403
9615
—
—
-0.16
-0.16
-0.16
—
—
103
51
12
—
300
1201
2403
—
-0.16
-0.16
-0.16
—
207
51
25
—
1.202
0.16
0.16
0.16
0.16
8.51
8.51
2.4
2.404
9.6
9.615
19.2
57.6
115.2
19.231
62.500
125.000
—
—
—
—
—
—
—
—
—
1
—
—
—
—
—
—
SYNC = 0, BRGH = 0, BRG16 = 1
BAUD
RATE
(K)
FOSC = 40.000 MHz
FOSC = 20.000 MHz
FOSC = 10.000 MHz
FOSC = 8.000 MHz
Actual
Rate
(K)
SPBRG Actual
value
(decimal)
SPBRG Actual
value
(decimal)
SPBRG Actual
value
(decimal)
SPBRG
value
%
Error
%
Error
%
Error
%
Error
Rate
(K)
Rate
(K)
Rate
(K)
(decimal)
0.3
1.2
0.300
1.200
0.00
0.02
0.06
0.16
0.16
0.94
-1.36
8332
2082
1040
259
129
42
0.300
1.200
0.02
-0.03
-0.03
0.16
4165
1041
520
129
64
0.300
1.200
0.02
-0.03
0.16
0.16
1.73
-1.36
8.51
2082
520
259
64
300
1201
2403
9615
19230
55555
—
-0.04
-0.16
-0.16
-0.16
-0.16
3.55
—
1665
415
207
51
2.4
2.402
2.399
2.404
9.6
9.615
9.615
9.615
19.2
57.6
115.2
19.231
58.140
113.636
19.231
56.818
113.636
0.16
19.531
56.818
125.000
31
25
-1.36
-1.36
21
10
8
21
10
4
—
SYNC = 0, BRGH = 0, BRG16 = 1
BAUD
RATE
(K)
FOSC = 4.000 MHz
FOSC = 2.000 MHz
FOSC = 1.000 MHz
Actual
Rate
(K)
SPBRG Actual
value
SPBRG Actual
value
(decimal)
SPBRG
value
(decimal)
%
%
Error
%
Error
Rate
(K)
Rate
(K)
Error
(decimal)
0.3
1.2
0.300
1.202
0.04
0.16
0.16
0.16
0.16
8.51
8.51
832
207
103
25
12
3
300
1201
2403
9615
—
-0.16
-0.16
-0.16
-0.16
—
415
103
51
12
—
300
1201
2403
—
-0.16
-0.16
-0.16
—
207
51
25
—
2.4
2.404
9.6
9.615
19.2
57.6
115.2
19.231
62.500
125.000
—
—
—
—
—
—
—
—
—
1
—
—
—
—
—
—
© 2007 Microchip Technology Inc.
DS39605F-page 137
PIC18F1220/1320
TABLE 16-3: BAUD RATES FOR ASYNCHRONOUS MODES (CONTINUED)
SYNC = 0, BRGH = 1, BRG16 = 1 or SYNC = 1, BRG16 = 1
BAUD
RATE
(K)
FOSC = 40.000 MHz
FOSC = 20.000 MHz
FOSC = 10.000 MHz
FOSC = 8.000 MHz
Actual
Rate
(K)
SPBRG Actual
value
SPBRG Actual
value
(decimal)
SPBRG Actual
value
(decimal)
SPBRG
value
(decimal)
%
%
Error
%
Error
%
Error
Rate
(K)
Rate
(K)
Rate
(K)
Error
(decimal)
0.3
1.2
0.300
1.200
0.00
0.00
0.02
0.06
-0.03
0.35
-0.22
33332
8332
4165
1040
520
0.300
1.200
0.00
0.02
0.02
-0.03
0.16
-0.22
0.94
16665
4165
2082
520
259
86
0.300
1.200
0.00
0.02
0.06
0.16
0.16
0.94
-1.36
8332
2082
1040
259
129
42
300
1200
-0.01
-0.04
-0.04
-0.16
-0.16
0.79
6665
1665
832
207
103
34
2.4
2.400
2.400
2.402
2400
9.6
9.606
9.596
9.615
9615
19.2
57.6
115.2
19.193
57.803
114.943
19.231
57.471
116.279
19.231
58.140
113.636
19230
57142
117647
172
86
42
21
-2.12
16
SYNC = 0, BRGH = 1, BRG16 = 1 or SYNC = 1, BRG16 = 1
FOSC = 4.000 MHz FOSC = 2.000 MHz FOSC = 1.000 MHz
BAUD
RATE
(K)
Actual
Rate
(K)
SPBRG Actual
SPBRG Actual
SPBRG
value
(decimal)
%
Error
%
Error
%
Error
value
Rate
(K)
value
Rate
(K)
(decimal)
(decimal)
0.3
1.2
0.300
1.200
0.01
0.04
0.16
0.16
0.16
2.12
-3.55
3332
832
415
103
51
300
1201
2403
9615
19230
55555
—
-0.04
-0.16
-0.16
-0.16
-0.16
3.55
—
1665
415
207
51
300
1201
2403
9615
19230
—
-0.04
-0.16
-0.16
-0.16
-0.16
—
832
207
103
25
2.4
2.404
9.6
9.615
19.2
57.6
115.2
19.231
58.824
111.111
25
12
16
8
—
8
—
—
—
—
DS39605F-page 138
© 2007 Microchip Technology Inc.
PIC18F1220/1320
16.2.3
AUTO-BAUD RATE DETECT
Note 1: It is up to the user to determine that the
incoming character baud rate is within the
range of the selected BRG clock source.
Some combinations of oscillator frequency
and EUSART baud rates are not possible
due to bit error rates. Overall system
timing and communication baud rates
must be taken into consideration when
using the Auto-Baud Rate Detection
feature.
The Enhanced USART module supports the automatic
detection and calibration of baud rate. This feature is
active only in Asynchronous mode and while the WUE
bit is clear.
The automatic baud rate measurement sequence
(Figure 16-1) begins whenever a Start bit is received and
the ABDEN bit is set. The calculation is self-averaging.
In the Auto-Baud Rate Detect (ABD) mode, the clock to
the BRG is reversed. Rather than the BRG clocking the
incoming RX signal, the RX signal is timing the BRG. In
ABD mode, the internal Baud Rate Generator is used
as a counter to time the bit period of the incoming serial
byte stream.
16.2.4
RECEIVING A SYNC (AUTO-BAUD
RATE DETECT)
To receive a Sync (Auto-Baud Rate Detect):
1. Configure the EUSART for asynchronous receive.
TXEN should remain clear. SPBRGH:SPBRG
may be left as is. The controller should operate in
either PRI_RUN or PRI_IDLE.
Once the ABDEN bit is set, the state machine will clear
the BRG and look for a Start bit. The Auto-Baud Detect
must receive a byte with the value 55h (ASCII “U”,
which is also the LIN bus Sync character), in order to
calculate the proper bit rate. The measurement is taken
over both a low and a high bit time in order to minimize
any effects caused by asymmetry of the incoming sig-
nal. After a Start bit, the SPBRG begins counting up
using the preselected clock source on the first rising
edge of RX. After eight bits on the RX pin, or the fifth
rising edge, an accumulated value totalling the proper
BRG period is left in the SPBRGH:SPBRG registers.
Once the 5th edge is seen (should correspond to the
Stop bit), the ABDEN bit is automatically cleared.
2. Enable RXIF interrupts. Set RCIE, PEIE, GIE.
3. Enable Auto-Baud Rate Detect. Set ABDEN.
4. When the next RCIF interrupt occurs, the
received baud rate has been measured. Read
RCREG to clear RCIF and discard. Check
SPBRGH:SPBRG for
a valid value. The
EUSART is ready for normal communications.
Return from the interrupt. Allow the primary
clock to run (PRI_RUN or PRI_IDLE).
5. Process subsequent RCIF interrupts normally
as in asynchronous reception. Remain in
PRI_RUN or PRI_IDLE until communications
are complete.
While calibrating the baud rate period, the BRG
registers are clocked at 1/8th the preconfigured clock
rate. Note that the BRG clock will be configured by the
BRG16 and BRGH bits. Independent of the BRG16 bit
setting, both the SPBRG and SPBRGH will be used as
a 16-bit counter. This allows the user to verify that no
carry occurred for 8-bit modes, by checking for 00h in
the SPBRGH register. Refer to Table 16-4 for counter
clock rates to the BRG.
TABLE 16-4: BRG COUNTER CLOCK
RATES
BRG16 BRGH
BRG Counter Clock
0
0
1
1
0
1
0
1
FOSC/512
FOSC/128
FOSC/128
FOSC/32
While the ABD sequence takes place, the EUSART
state machine is held in Idle. The RCIF interrupt is set
once the fifth rising edge on RX is detected. The value
in the RCREG needs to be read to clear the RCIF
interrupt. RCREG content should be discarded.
Note: During the ABD sequence, SPBRG and
SPBRGH are both used as a 16-bit counter,
independent of BRG16 setting.
© 2007 Microchip Technology Inc.
DS39605F-page 139
PIC18F1220/1320
FIGURE 16-1:
AUTOMATIC BAUD RATE CALCULATION
XXXXh
0000h
001Ch
Edge #5
Stop Bit
BRG Value
Edge #1
Edge #2
Bit 3
Edge #3
Bit 5
Edge #4
Bit 7
Bit 6
RX pin
Bit 1
Start
Bit 0
Bit 2
Bit 4
BRG Clock
Auto-Cleared
Set by User
ABDEN bit
RCIF bit
(Interrupt)
Read
RCREG
XXXXh
XXXXh
1Ch
00h
SPBRG
SPBRGH
Note 1: The ABD sequence requires the EUSART module to be configured in Asynchronous mode and WUE = 0.
16.3.1
EUSART ASYNCHRONOUS
TRANSMITTER
16.3 EUSART Asynchronous Mode
The Asynchronous mode of operation is selected by
clearing the SYNC bit (TXSTA<4>). In this mode, the
EUSART uses standard Non-Return-to-Zero (NRZ) for-
mat (one Start bit, eight or nine data bits and one Stop
bit). The most common data format is 8 bits. An on-chip
dedicated 8-bit/16-bit Baud Rate Generator can be
used to derive standard baud rate frequencies from the
oscillator.
The EUSART transmitter block diagram is shown in
Figure 16-2. The heart of the transmitter is the Transmit
(Serial) Shift Register (TSR). The shift register obtains
its data from the Read/Write Transmit Buffer register,
TXREG. The TXREG register is loaded with data in
software. The TSR register is not loaded until the Stop
bit has been transmitted from the previous load. As
soon as the Stop bit is transmitted, the TSR is loaded
with new data from the TXREG register (if available).
The EUSART transmits and receives the LSb first. The
EUSART’s transmitter and receiver are functionally
independent, but use the same data format and baud
rate. The Baud Rate Generator produces a clock, either
x16 or x64 of the bit shift rate, depending on the BRGH
and BRG16 bits (TXSTA<2> and BAUDCTL<3>). Parity
is not supported by the hardware, but can be
implemented in software and stored as the 9th data bit.
Once the TXREG register transfers the data to the TSR
register (occurs in one TCY), the TXREG register is
empty and flag bit, TXIF (PIR1<4>), is set. This interrupt
can be enabled/disabled by setting/clearing enable bit,
TXIE (PIE1<4>). Flag bit, TXIF, will be set, regardless of
the state of enable bit, TXIE, and cannot be cleared in
software. Flag bit, TXIF, is not cleared immediately upon
loading the Transmit Buffer register, TXREG. TXIF
becomes valid in the second instruction cycle following
the load instruction. Polling TXIF immediately following a
load of TXREG will return invalid results.
Asynchronous mode is available in all low-power
modes; it is available in Sleep mode only when auto-
wake-up on Sync Break is enabled. When in PRI_IDLE
mode, no changes to the Baud Rate Generator values
are required; however, other low-power mode clocks
may operate at another frequency than the primary
clock. Therefore, the Baud Rate Generator values may
need to be adjusted.
While flag bit, TXIF, indicates the status of the TXREG
register, another bit, TRMT (TXSTA<1>), shows the
status of the TSR register. Status bit, TRMT, is a read-
only bit, which is set when the TSR register is empty.
No interrupt logic is tied to this bit, so the user has to
poll this bit in order to determine if the TSR register is
empty.
When operating in Asynchronous mode, the EUSART
module consists of the following important elements:
• Baud Rate Generator
• Sampling Circuit
Note 1: The TSR register is not mapped in data
• Asynchronous Transmitter
• Asynchronous Receiver
memory, so it is not available to the user.
2: Flag bit, TXIF, is set when enable bit,
• Auto-Wake-up on Sync Break Character
• 12-bit Break Character Transmit
• Auto-Baud Rate Detection
TXEN, is set.
DS39605F-page 140
© 2007 Microchip Technology Inc.
PIC18F1220/1320
To set up an Asynchronous Transmission:
5. Enable the transmission by setting bit TXEN,
which will also set bit TXIF.
1. Initialize the SPBRGH:SPBRG registers for the
appropriate baud rate. Set or clear the BRGH
and BRG16 bits, as required, to achieve the
desired baud rate.
6. If 9-bit transmission is selected, the ninth bit
should be loaded in bit TX9D.
7. Load data to the TXREG register (starts
transmission).
2. Enable the asynchronous serial port by clearing
bit SYNC and setting bit SPEN.
If using interrupts, ensure that the GIE and PEIE bits in
the INTCON register (INTCON<7:6>) are set.
3. If interrupts are desired, set enable bit TXIE.
4. If 9-bit transmission is desired, set transmit bit
TX9. Can be used as address/data bit.
FIGURE 16-2:
EUSART TRANSMIT BLOCK DIAGRAM
Data Bus
TXREG Register
TXIF
TXIE
8
RB1/AN5/TX/CK/INT1 pin
LSb
MSb
(8)
Pin Buffer
0
•
•
•
and Control
TSR Register
Interrupt
Baud Rate CLK
SPBRG
TXEN
TRMT
SPEN
BRG16
SPBRGH
TX9
TX9D
Baud Rate Generator
FIGURE 16-3:
ASYNCHRONOUS TRANSMISSION
Write to TXREG
Word 1
BRG Output
(Shift Clock)
RB1/AN5/TX/
CK/INT1 (pin)
Start bit
bit 0
bit 1
Word 1
bit 7/8
Stop bit
TXIF bit
(Transmit Buffer
Reg. Empty Flag)
1 TCY
Word 1
Transmit Shift Reg
TRMT bit
(Transmit Shift
Reg. Empty Flag)
© 2007 Microchip Technology Inc.
DS39605F-page 141
PIC18F1220/1320
FIGURE 16-4:
ASYNCHRONOUS TRANSMISSION (BACK TO BACK)
Write to TXREG
Word 2
Start bit
Word 1
BRG Output
(Shift Clock)
RB1/AN5/TX/
CK/INT1 (pin)
Start bit
Word 2
bit 0
bit 1
bit 7/8
bit 0
Stop bit
Word 2
1 TCY
Word 1
TXIF bit
(Interrupt Reg. Flag)
1 TCY
TRMT bit
(Transmit Shift
Reg. Empty Flag)
Word 1
Transmit Shift Reg.
Transmit Shift Reg.
Note:
This timing diagram shows two consecutive transmissions.
TABLE 16-5: REGISTERS ASSOCIATED WITH ASYNCHRONOUS TRANSMISSION
Value on
all other
Resets
Value on
POR, BOR
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
INTCON
PIR1
GIE/GIEH PEIE/GIEL TMR0IE INT0IE
RBIE
—
TMR0IF INT0IF
RBIF
0000 000x 0000 000u
-000 -000 -000 -000
-000 -000 -000 -000
-111 -111 -111 -111
0000 -00x 0000 -00x
0000 0000 0000 0000
0000 0010 0000 0010
-1-1 0-00 -1-1 0-00
0000 0000 0000 0000
0000 0000 0000 0000
—
—
ADIF
ADIE
ADIP
RX9
RCIF
RCIE
RCIP
SREN
TXIF
TXIE
TXIP
CCP1IF TMR2IF TMR1IF
CCP1IE TMR2IE TMR1IE
CCP1IP TMR2IP TMR1IP
PIE1
—
IPR1
—
—
RCSTA
TXREG
TXSTA
BAUDCTL
SPEN
CREN ADDEN
FERR
OERR
RX9D
EUSART Transmit Register
CSRC
—
TX9
TXEN
—
SYNC SENDB BRGH
SCKP BRG16
TRMT
WUE
TX9D
RCIDL
—
ABDEN
SPBRGH Baud Rate Generator Register High Byte
SPBRG
Baud Rate Generator Register Low Byte
Legend:
x= unknown, – = unimplemented locations read as ‘0’. Shaded cells are not used for asynchronous transmission.
DS39605F-page 142
© 2007 Microchip Technology Inc.
PIC18F1220/1320
16.3.2
EUSART ASYNCHRONOUS
RECEIVER
16.3.3
SETTING UP 9-BIT MODE WITH
ADDRESS DETECT
The receiver block diagram is shown in Figure 16-5.
The data is received on the RB4/AN6/RX/DT/KBI0 pin
and drives the data recovery block. The data recovery
block is actually a high-speed shifter, operating at x16
times the baud rate, whereas the main receive serial
shifter operates at the bit rate or at FOSC. This mode
would typically be used in RS-232 systems.
This mode would typically be used in RS-485 systems.
To set up an Asynchronous Reception with Address
Detect Enable:
1. Initialize the SPBRGH:SPBRG registers for the
appropriate baud rate. Set or clear the BRGH
and BRG16 bits, as required, to achieve the
desired baud rate.
To set up an Asynchronous Reception:
2. Enable the asynchronous serial port by clearing
the SYNC bit and setting the SPEN bit.
1. Initialize the SPBRGH:SPBRG registers for the
appropriate baud rate. Set or clear the BRGH
and BRG16 bits, as required, to achieve the
desired baud rate.
3. If interrupts are required, set the RCEN bit and
select the desired priority level with the RCIP bit.
4. Set the RX9 bit to enable 9-bit reception.
5. Set the ADDEN bit to enable address detect.
6. Enable reception by setting the CREN bit.
2. Enable the asynchronous serial port by clearing
bit SYNC and setting bit SPEN.
3. If interrupts are desired, set enable bit RCIE.
4. If 9-bit reception is desired, set bit RX9.
5. Enable the reception by setting bit CREN.
7. The RCIF bit will be set when reception is
complete. The interrupt will be Acknowledged if
the RCIE and GIE bits are set.
6. Flag bit, RCIF, will be set when reception is
complete and an interrupt will be generated if
enable bit RCIE was set.
8. Read the RCSTA register to determine if any
error occurred during reception, as well as read
bit 9 of data (if applicable).
7. Read the RCSTA register to get the 9th bit (if
enabled) and determine if any error occurred
during reception.
9. Read RCREG to determine if the device is being
addressed.
10. If any error occurred, clear the CREN bit.
8. Read the 8-bit received data by reading the
RCREG register.
11. If the device has been addressed, clear the
ADDEN bit to allow all received data into the
receive buffer and interrupt the CPU.
9. If any error occurred, clear the error by clearing
enable bit CREN.
10. If using interrupts, ensure that the GIE and PEIE
bits in the INTCON register (INTCON<7:6>) are
set.
FIGURE 16-5:
EUSART RECEIVE BLOCK DIAGRAM
CREN
OERR
FERR
x64 Baud Rate CLK
SPBRGH SPBRG
÷ 64
RSR Register
• • •
MSb
Stop
LSb
Start
BRG16
or
÷ 16
(8)
7
1
0
or
Baud Rate Generator
÷ 4
RX9
RB4/AN6/RX/DT/KBI0
Pin Buffer
and Control
Data
Recovery
RX9D
RCREG Register
FIFO
SPEN
8
Interrupt
RCIF
RCIE
Data Bus
© 2007 Microchip Technology Inc.
DS39605F-page 143
PIC18F1220/1320
To set up an Asynchronous Transmission:
5. Enable the transmission by setting bit TXEN,
which will also set bit TXIF.
1. Initialize the SPBRG register for the appropriate
baud rate. If a high-speed baud rate is desired,
set bit BRGH (see Section 16.2 “EUSART
Baud Rate Generator (BRG)”).
6. If 9-bit transmission is selected, the ninth bit
should be loaded in bit TX9D.
7. Load data to the TXREG register (starts
transmission).
2. Enable the asynchronous serial port by clearing
bit SYNC and setting bit SPEN.
If using interrupts, ensure that the GIE and PEIE bits in
the INTCON register (INTCON<7:6>) are set.
3. If interrupts are desired, set enable bit TXIE.
4. If 9-bit transmission is desired, set transmit bit
TX9. Can be used as address/data bit.
FIGURE 16-6:
ASYNCHRONOUS RECEPTION
Start
bit
Start
bit
Start
bit
RX (pin)
bit 0 bit 1
bit 7/8
bit 7/8 Stop
bit
Stop
bit
Stop
bit
bit 0
bit 7/8
Rcv Shift
Reg
Rcv Buffer Reg
Word 2
RCREG
Word 1
RCREG
Read Rcv
Buffer Reg
RCREG
RCIF
(Interrupt Flag)
OERR bit
CREN
Note:
This timing diagram shows three words appearing on the RX input. The RCREG (receive buffer) is read after
the third word, causing the OERR (overrun) bit to be set.
TABLE 16-6: REGISTERS ASSOCIATED WITH ASYNCHRONOUS RECEPTION
Value on
all other
Resets
Value on
POR, BOR
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
INTCON
PIR1
GIE/GIEH PEIE/GIEL TMR0IE INT0IE
RBIE
—
TMR0IF INT0IF
RBIF
0000 000x
0000 000u
-000 -000
-000 -000
-111 -111
0000 000x
0000 0000
0000 0010
-1-1 0-00
0000 0000
0000 0000
—
—
ADIF
ADIE
ADIP
RX9
RCIF
RCIE
RCIP
SREN
TXIF
TXIE
TXIP
CCP1IF TMR2IF TMR1IF -000 -000
CCP1IE TMR2IE TMR1IE -000 -000
CCP1IP TMR2IP TMR1IP -111 -111
PIE1
—
IPR1
—
—
RCSTA
RCREG
TXSTA
BAUDCTL
SPEN
CREN ADDEN FERR
OERR
RX9D
0000 000x
0000 0000
0000 0010
EUSART Receive Register
CSRC
—
TX9
TXEN
—
SYNC SENDB BRGH
TRMT
WUE
TX9D
RCIDL
SCKP BRG16
—
ABDEN -1-1 0-00
0000 0000
SPBRGH Baud Rate Generator Register High Byte
SPBRG
Baud Rate Generator Register Low Byte
0000 0000
Legend:
x= unknown, – = unimplemented locations read as ‘0’. Shaded cells are not used for asynchronous reception.
DS39605F-page 144
© 2007 Microchip Technology Inc.
PIC18F1220/1320
and cause data or framing errors. To work properly,
therefore, the initial character in the transmission must
be all ‘0’s. This can be 00h (8 bytes) for standard RS-232
devices, or 000h (12 bits) for LIN bus.
16.3.4
AUTO-WAKE-UP ON SYNC BREAK
CHARACTER
During Sleep mode, all clocks to the EUSART are
suspended. Because of this, the Baud Rate Generator
is inactive and a proper byte reception cannot be per-
formed. The auto-wake-up feature allows the controller
to wake-up due to activity on the RX/DT line while the
EUSART is operating in Asynchronous mode.
Oscillator start-up time must also be considered,
especially in applications using oscillators with longer
start-up intervals (i.e., LP, XT or HS/PLL mode). The
Sync Break (or Wake-up Signal) character must be of
sufficient length and be followed by a sufficient period,
to allow enough time for the selected oscillator to start
and provide proper initialization of the EUSART.
The auto-wake-up feature is enabled by setting the
WUE bit (BAUDCTL<1>). Once set, the typical receive
sequence on RX/DT is disabled and the EUSART
remains in an Idle state, monitoring for a wake-up event
independent of the CPU mode. A wake-up event con-
sists of a high-to-low transition on the RX/DT line. (This
coincides with the start of a Sync Break or a Wake-up
Signal character for the LIN protocol.)
16.3.4.2
Special Considerations Using
the WUE Bit
The timing of WUE and RCIF events may cause some
confusion when it comes to determining the validity of
received data. As noted, setting the WUE bit places the
EUSART in an Idle mode. The wake-up event causes
a receive interrupt by setting the RCIF bit. The WUE bit
is cleared after this when a rising edge is seen on RX/
DT. The interrupt condition is then cleared by reading
the RCREG register. Ordinarily, the data in RCREG will
be dummy data and should be discarded.
Following a wake-up event, the module generates an
RCIF interrupt. The interrupt is generated synchro-
nously to the Q clocks in normal operating modes
(Figure 16-7) and asynchronously if the device is in
Sleep mode (Figure 16-8). The interrupt condition is
cleared by reading the RCREG register.
The WUE bit is automatically cleared once a low-to-high
transition is observed on the RX line, following the wake-
up event. At this point, the EUSART module is in Idle
mode and returns to normal operation. This signals to
the user that the Sync Break event is over.
The fact that the WUE bit has been cleared (or is still
set) and the RCIF flag is set should not be used as an
indicator of the integrity of the data in RCREG. Users
should consider implementing a parallel method in
firmware to verify received data integrity.
To assure that no actual data is lost, check the RCIDL
bit to verify that a receive operation is not in process. If
a receive operation is not occurring, the WUE bit may
then be set just prior to entering the Sleep mode.
16.3.4.1
Special Considerations Using
Auto-Wake-up
Since auto-wake-up functions by sensing rising edge
transitions on RX/DT, information with any state changes
before the Stop bit may signal a false end-of-character
FIGURE 16-7:
AUTO-WAKE-UP BIT (WUE) TIMINGS DURING NORMAL OPERATION
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
OSC1
WUE bit
Cleared by hardware
Bit Set by User
RX/DT Line
RCIF
Cleared due to User Read of RCREG
Note 1: The EUSART remains in Idle while the WUE bit is set.
FIGURE 16-8:
AUTO-WAKE-UP BIT (WUE) TIMINGS DURING SLEEP
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
Q1
Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
OSC1
WUE bit
Enters Sleep
Cleared by hardware
Bit Set by User
RX/DT Line
RCIF
Note 1
Cleared due to User Read of RCREG
Sleep Ends
Note 1: If the wake-up event requires a long oscillator warm-up time, the WUE bit may be cleared while the primary clock is still starting.
2: The EUSART remains in Idle while the WUE bit is set.
© 2007 Microchip Technology Inc.
DS39605F-page 145
PIC18F1220/1320
4. If 9-bit transmission is desired, set transmit bit
TX9. Can be used as address/data bit.
16.3.5
BREAK CHARACTER SEQUENCE
The Enhanced USART module has the capability of
sending the special Break character sequences that
are required by the LIN bus standard. The Break char-
acter transmit consists of a Start bit, followed by twelve
‘0’ bits and a Stop bit. The Frame Break character is
sent whenever the SENDB and TXEN bits (TXSTA<3>
and TXSTA<5>) are set while the Transmit Shift
register is loaded with data. Note that the value of data
written to TXREG will be ignored and all ‘0’s will be
transmitted.
5. Enable the transmission by setting bit TXEN,
which will also set bit TXIF.
6. Set the SENDB bit.
7. Load a byte into TXREG. This triggers sending a
Break signal. The Break signal is complete
when TRMT is set. SENDB will also be cleared.
See Figure 16-9 for the timing of the Break signal
sequence.
16.3.6
RECEIVING A BREAK CHARACTER
The SENDB bit is automatically reset by hardware after
the corresponding Stop bit is sent. This allows the user
to preload the transmit FIFO with the next transmit byte
following the Break character (typically, the Sync
character in the LIN specification).
The Enhanced USART module can receive a Break
character in two ways.
The first method forces configuration of the baud rate
at a frequency of 9/13 the typical speed. This allows for
the Stop bit transition to be at the correct sampling
location (12 bits for Break versus Start bit and 8 data
bits for typical data).
Note that the data value written to the TXREG for the
Break character is ignored. The write simply serves the
purpose of initiating the proper sequence.
The TRMT bit indicates when the transmit operation is
active or Idle, just as it does during normal transmis-
sion. See Figure 16-9 for the timing of the Break
character sequence.
The second method uses the auto-wake-up feature
described in Section 16.3.4 “Auto-Wake-up on Sync
Break Character”. By enabling this feature, the
EUSART will sample the next two transitions on RX/DT,
cause an RCIF interrupt and receive the next data byte
followed by another interrupt.
16.3.5.1
Transmitting A Break Signal
The Enhanced USART module has the capability of
sending the Break signal that is required by the LIN bus
standard. The Break signal consists of a Start bit,
followed by twelve ‘0’ bits and a Stop bit. The Break sig-
nal is sent whenever the SENDB (TXSTA<3>) and
TXEN (TXSTA<5>) bits are set and TXREG is loaded
with data. The data written to TXREG will be ignored
and all ‘0’s will be transmitted.
Note that following a Break character, the user will
typically want to enable the Auto-Baud Rate Detect
feature. For both methods, the user can set the ABD bit
before placing the EUSART in its Sleep mode.
16.3.6.1
Transmitting a Break Sync
The following sequence will send a message frame
header made up of a Break, followed by an auto-baud
Sync byte. This sequence is typical of a LIN bus master.
SENDB is automatically cleared by hardware when the
Break signal has been sent. This allows the user to
preload the transmit FIFO with the next transmit byte
following the Break character (typically, the Sync
character in the LIN specification).
1. Configure the EUSART for the desired mode.
2. Set the TXEN and SENDB bits to set up the
Break character.
3. Load the TXREG with a dummy character to
initiate transmission (the value is ignored).
The TRMT bit indicates when the transmit operation is
active or Idle, just as it does during normal
transmission.
4. Write ‘55h’ to TXREG to load the Sync character
into the transmit FIFO buffer.
To send a Break Signal:
5. After the Break has been sent, the SENDB bit is
reset by hardware. The Sync character now
transmits in the preconfigured mode. When the
TXREG becomes empty, as indicated by the
TXIF, the next data byte can be written to TXREG.
1. Configure the EUSART for asynchronous trans-
missions (steps 1-5). Initialize the SPBRG register
for the appropriate baud rate. If a high-speed baud
rate is desired, set bit BRGH (see Section 16.2
“EUSART Baud Rate Generator (BRG)”).
2. Enable the asynchronous serial port by clearing
bit SYNC and setting bit SPEN.
3. If interrupts are desired, set enable bit TXIE.
DS39605F-page 146
© 2007 Microchip Technology Inc.
PIC18F1220/1320
7. Enable Auto-Baud Rate Detect. Set ABDEN.
16.3.6.2
Receiving a Break Sync
8. Return from the interrupt. Allow the primary
clock to start and stabilize (PRI_RUN or
PRI_IDLE).
To receive a Break Sync:
1. Configure the EUSART for asynchronous
transmit and receive. TXEN should remain
clear. SPBRGH:SPBRG may be left as is.
9. When the next RCIF interrupt occurs, the
received baud rate has been measured. Read
RCREG to clear RCIF and discard. Check
2. Enable auto-wake-up. Set WUE.
3. Enable RXIF interrupts. Set RCIE, PEIE, GIE.
SPBRGH:SPBRG for
a valid value. The
4. The controller may be placed in any power
managed mode.
EUSART is ready for normal communications.
Return from the interrupt. Allow the primary
clock to run (PRI_RUN or PRI_IDLE).
5. An RCIF will be generated at the beginning of
the Break signal. When the interrupt is received,
read RCREG to clear RCIF and discard. Allow
the controller to return to PRI_RUN mode.
10. Process subsequent RCIF interrupts normally
as in asynchronous reception. TXEN should
now be set if transmissions are needed. TXIF
and TXIE may be set if transmit interrupts are
desired. Remain in PRI_RUN or PRI_IDLE until
communications are complete. Clear TXEN and
return to step 2.
6. Wait for the RX line to go high at the end of the
Break signal. Wait for any of the following: WUE
to clear automatically (poll), RB4/RX to go high
(poll) or for RBIF to be set (poll or interrupt). If
RBIF is used, check to be sure that RB4/RX is
high before continuing.
FIGURE 16-9:
SEND BREAK CHARACTER SEQUENCE
Write to TXREG
Dummy Write
BRG Output
(Shift Clock)
TX (pin)
Start Bit
Bit 0
Bit 1
Break
Bit 11
Stop Bit
TXIF bit
TRMT bit
SENDB
© 2007 Microchip Technology Inc.
DS39605F-page 147
PIC18F1220/1320
Once the TXREG register transfers the data to the TSR
register (occurs in one TCYCLE), the TXREG is empty
and interrupt bit, TXIF (PIR1<4>), is set. The interrupt
can be enabled/disabled by setting/clearing enable bit,
TXIE (PIE1<4>). Flag bit, TXIF, will be set, regardless
of the state of enable bit, TXIE and cannot be cleared
in software. It will reset only when new data is loaded
into the TXREG register.
16.4 EUSART Synchronous Master
Mode
The Synchronous Master mode is entered by setting
the CSRC bit (TXSTA<7>). In this mode, the data is
transmitted in a half-duplex manner (i.e., transmission
and reception do not occur at the same time). When
transmitting data, the reception is inhibited and vice
versa. Synchronous mode is entered by setting bit,
SYNC (TXSTA<4>). In addition, enable bit, SPEN
(RCSTA<7>), is set in order to configure the RB1/AN5/
TX/CK/INT1 and RB4/AN6/RX/DT/KBI0 I/O pins to CK
(clock) and DT (data) lines, respectively.
While flag bit, TXIF, indicates the status of the TXREG
register, another bit, TRMT (TXSTA<1>), shows the
status of the TSR register. TRMT is a read-only bit,
which is set when the TSR is empty. No interrupt logic is
tied to this bit, so the user has to poll this bit in order to
determine if the TSR register is empty. The TSR is not
mapped in data memory, so it is not available to the user.
The Master mode indicates that the processor trans-
mits the master clock on the CK line. Clock polarity is
selected with the SCKP bit (BAUDCTL<5>); setting
SCKP sets the Idle state on CK as high, while clearing
the bit sets the Idle state as low. This option is provided
to support Microwire devices with this module.
To set up a Synchronous Master Transmission:
1. Initialize the SPBRGH:SPBRG registers for the
appropriate baud rate. Set or clear the BRGH
and BRG16 bits, as required, to achieve the
desired baud rate.
16.4.1
EUSART SYNCHRONOUS MASTER
TRANSMISSION
2. Enable the synchronous master serial port by
setting bits SYNC, SPEN and CSRC.
The EUSART transmitter block diagram is shown in
Figure 16-2. The heart of the transmitter is the Transmit
(Serial) Shift Register (TSR). The shift register obtains
its data from the Read/Write Transmit Buffer register,
TXREG. The TXREG register is loaded with data in
software. The TSR register is not loaded until the last
bit has been transmitted from the previous load. As
soon as the last bit is transmitted, the TSR is loaded
with new data from the TXREG (if available).
3. If interrupts are desired, set enable bit TXIE.
4. If 9-bit transmission is desired, set bit TX9.
5. Enable the transmission by setting bit TXEN.
6. If 9-bit transmission is selected, the ninth bit
should be loaded in bit TX9D.
7. Start transmission by loading data to the TXREG
register.
8. If using interrupts, ensure that the GIE and PEIE
bits in the INTCON register (INTCON<7:6>) are
set.
FIGURE 16-10:
SYNCHRONOUS TRANSMISSION
Q1 Q2 Q3Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1Q2 Q3 Q4 Q1 Q2 Q3 Q4
Q3 Q4 Q1 Q2 Q3Q4 Q1Q2 Q3Q4 Q1 Q2Q3Q4 Q1 Q2Q3 Q4Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
RB4/AN6/RX/
DT/KBI0 pin
bit 0
bit 1
bit 2
bit 7
bit 0
bit 1
bit 7
Word 2
Word 1
RB1/AN5/TX/
CK/INT1 pin
(SCKP = 0)
RB1/AN5/TX/
CK/INT1 pin
(SCKP = 1)
Write to
TXREG Reg
Write Word 1
Write Word 2
TXIF bit
(Interrupt Flag)
TRMT bit
TXEN bit
‘1’
‘1’
Note:
Sync Master mode, SPBRG = 0, continuous transmission of two 8-bit words.
DS39605F-page 148
© 2007 Microchip Technology Inc.
PIC18F1220/1320
FIGURE 16-11:
SYNCHRONOUS TRANSMISSION (THROUGH TXEN)
RB4/AN6/RX/DT/KBI0 pin
bit 0
bit 2
bit 1
bit 6
bit 7
RB1/AN5/TX/CK/INT1 pin
Write to
TXREG reg
TXIF bit
TRMT bit
TXEN bit
TABLE 16-7: REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER TRANSMISSION
Value on
all other
Resets
Value on
POR, BOR
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
INTCON
PIR1
GIE/GIEH PEIE/GIEL TMR0IE INT0IE
RBIE
—
TMR0IF
INT0IF
RBIF
0000 000x
-000 -000
-000 -000
-111 -111
0000 -00x
0000 0000
0000 0010
-1-1 0-00
0000 0000
0000 0000
0000 000u
-000 -000
-000 -000
-111 -111
0000 -00x
0000 0000
0000 0010
-1-1 0-00
0000 0000
0000 0000
—
—
ADIF
ADIE
ADIP
RX9
RCIF
RCIE
RCIP
SREN
TXIF
TXIE
TXIP
CCP1IF TMR2IF TMR1IF
CCP1IE TMR2IE TMR1IE
CCP1IP TMR2IP TMR1IP
PIE1
—
IPR1
—
—
RCSTA
TXREG
TXSTA
BAUDCTL
SPEN
CREN ADDEN
FERR
OERR
RX9D
EUSART Transmit Register
CSRC
—
TX9
TXEN
—
SYNC SENDB
SCKP BRG16
BRGH
—
TRMT
WUE
TX9D
RCIDL
ABDEN
SPBRGH Baud Rate Generator Register High Byte
SPBRG
Baud Rate Generator Register Low Byte
Legend:
x= unknown, – = unimplemented, read as ‘0’. Shaded cells are not used for synchronous master transmission.
© 2007 Microchip Technology Inc.
DS39605F-page 149
PIC18F1220/1320
3. Ensure bits CREN and SREN are clear.
4. If interrupts are desired, set enable bit RCIE.
5. If 9-bit reception is desired, set bit RX9.
16.4.2
EUSART SYNCHRONOUS MASTER
RECEPTION
Once Synchronous mode is selected, reception is
enabled by setting either the Single Receive Enable bit,
SREN (RCSTA<5>), or the Continuous Receive
Enable bit, CREN (RCSTA<4>). Data is sampled on the
RB4/AN6/RX/DT/KBI0 pin on the falling edge of the
clock.
6. If a single reception is required, set bit SREN.
For continuous reception, set bit CREN.
7. Interrupt flag bit, RCIF, will be set when reception
is complete and an interrupt will be generated if
the enable bit, RCIE, was set.
If enable bit, SREN, is set, only a single word is
received. If enable bit, CREN, is set, the reception is
continuous until CREN is cleared. If both bits are set,
then CREN takes precedence.
8. Read the RCSTA register to get the 9th bit (if
enabled) and determine if any error occurred
during reception.
9. Read the 8-bit received data by reading the
RCREG register.
To set up a Synchronous Master Reception:
10. If any error occurred, clear the error by clearing
bit CREN.
1. Initialize the SPBRGH:SPBRG registers for the
appropriate baud rate. Set or clear the BRGH
and BRG16 bits, as required, to achieve the
desired baud rate.
11. If using interrupts, ensure that the GIE and PEIE
bits in the INTCON register (INTCON<7:6>) are
set.
2. Enable the synchronous master serial port by
setting bits SYNC, SPEN and CSRC.
FIGURE 16-12:
SYNCHRONOUS RECEPTION (MASTER MODE, SREN)
Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4Q1 Q2 Q3 Q4 Q1Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
RB4/AN6/RX/
DT/KBI0 pin
bit 0
bit 1
bit 2
bit 3
bit 4
bit 5
bit 6
bit 7
RB1/AN5/TX/
CK/INT1 pin
(SCKP = 0)
RB1/AN5/TX/
CK/INT1 pin
(SCKP = 1)
Write to
bit SREN
SREN bit
CREN bit
‘0’
‘0’
RCIF bit
(Interrupt)
Read
RXREG
Note:
Timing diagram demonstrates Sync Master mode with bit SREN = 1and bit BRGH = 0.
DS39605F-page 150
© 2007 Microchip Technology Inc.
PIC18F1220/1320
TABLE 16-8: REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER RECEPTION
Value on
all other
Resets
Value on
POR, BOR
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
INTCON
PIR1
GIE/GIEH PEIE/GIEL TMR0IE INT0IE
RBIE
—
TMR0IF INT0IF
RBIF
0000 000x 0000 000u
—
—
ADIF
ADIE
ADIP
RX9
RCIF
RCIE
RCIP
SREN
TXIF
TXIE
TXIP
CCP1IF TMR2IF TMR1IF -000 -000 -000 -000
CCP1IE TMR2IE TMR1IE -000 -000 -000 -000
CCP1IP TMR2IP TMR1IP -111 -111 -111 -111
PIE1
—
IPR1
—
—
RCSTA
RCREG
TXSTA
BAUDCTL
SPEN
CREN ADDEN
FERR
OERR
RX9D
0000 000x 0000 000x
0000 0000 0000 0000
0000 0010 0000 0010
-1-1 0-00 -1-1 0-00
0000 0000 0000 0000
0000 0000 0000 0000
EUSART Receive Register
CSRC
—
TX9
TXEN
—
SYNC
SCKP
SENDB
BRG16
BRGH
—
TRMT
WUE
TX9D
RCIDL
ABDEN
SPBRGH Baud Rate Generator Register High Byte
SPBRG
Baud Rate Generator Register Low Byte
Legend:
x= unknown, – = unimplemented, read as ‘0’. Shaded cells are not used for synchronous master reception.
© 2007 Microchip Technology Inc.
DS39605F-page 151
PIC18F1220/1320
To set up a Synchronous Slave Transmission:
16.5 EUSART Synchronous
Slave Mode
1. Enable the synchronous slave serial port by
setting bits SYNC and SPEN and clearing bit
CSRC.
Synchronous Slave mode is entered by clearing bit,
CSRC (TXSTA<7>). This mode differs from the
Synchronous Master mode in that the shift clock is
supplied externally at the RB1/AN5/TX/CK/INT1 pin
(instead of being supplied internally in Master mode).
This allows the device to transfer or receive data while
in any low-power mode.
2. Clear bits CREN and SREN.
3. If interrupts are desired, set enable bit TXIE.
4. If 9-bit transmission is desired, set bit TX9.
5. Enable the transmission by setting enable bit
TXEN.
6. If 9-bit transmission is selected, the ninth bit
should be loaded in bit TX9D.
16.5.1
EUSART SYNCHRONOUS
SLAVE TRANSMIT
7. Start transmission by loading data to the TXREG
register.
The operation of the Synchronous Master and Slave
modes are identical, except in the case of the Sleep
mode.
8. If using interrupts, ensure that the GIE and PEIE
bits in the INTCON register (INTCON<7:6>) are
set.
If two words are written to the TXREG and then the
SLEEPinstruction is executed, the following will occur:
a) The first word will immediately transfer to the
TSR register and transmit.
b) The second word will remain in the TXREG
register.
c) Flag bit, TXIF, will not be set.
d) When the first word has been shifted out of TSR,
the TXREG register will transfer the second
word to the TSR and flag bit, TXIF, will now be
set.
e) If enable bit, TXIE, is set, the interrupt will wake
the chip from Sleep. If the global interrupt is
enabled, the program will branch to the interrupt
vector.
TABLE 16-9: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE TRANSMISSION
Value on
all other
Resets
Value on
POR, BOR
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
INTCON
PIR1
GIE/GIEH PEIE/GIEL TMR0IE INT0IE
RBIE
—
TMR0IF INT0IF
RBIF
0000 000x 0000 000u
—
—
ADIF
ADIE
ADIP
RX9
RCIF
RCIE
RCIP
SREN
TXIF
TXIE
TXIP
CCP1IF TMR2IF TMR1IF -000 -000 -000 -000
CCP1IE TMR2IE TMR1IE -000 -000 -000 -000
CCP1IP TMR2IP TMR1IP -111 -111 -111 -111
PIE1
—
IPR1
—
—
RCSTA
TXREG
TXSTA
BAUDCTL
SPEN
CREN ADDEN
FERR
OERR
RX9D
0000 000x 0000 000x
0000 0000 0000 0000
0000 0010 0000 0010
EUSART Transmit Register
CSRC
—
TX9
TXEN
—
SYNC SENDB
SCKP BRG16
BRGH
—
TRMT
WUE
TX9D
RCIDL
ABDEN -1-1 0-00 -1-1 0-00
0000 0000 0000 0000
SPBRGH Baud Rate Generator Register High Byte
SPBRG Baud Rate Generator Register Low Byte
0000 0000 0000 0000
Legend: x= unknown, – = unimplemented, read as ‘0’. Shaded cells are not used for synchronous slave transmission.
DS39605F-page 152
© 2007 Microchip Technology Inc.
PIC18F1220/1320
To set up a Synchronous Slave Reception:
16.5.2
EUSART SYNCHRONOUS SLAVE
RECEPTION
1. Enable the synchronous master serial port by
setting bits SYNC and SPEN and clearing bit
CSRC.
The operation of the Synchronous Master and Slave
modes is identical, except in the case of Sleep, or any
Idle mode and bit SREN, which is a “don’t care” in
Slave mode.
2. If interrupts are desired, set enable bit RCIE.
3. If 9-bit reception is desired, set bit RX9.
4. To enable reception, set enable bit CREN.
If receive is enabled by setting the CREN bit prior to
entering Sleep or any Idle mode, then a word may be
received while in this low-power mode. Once the word
is received, the RSR register will transfer the data to the
RCREG register; if the RCIE enable bit is set, the inter-
rupt generated will wake the chip from low-power
mode. If the global interrupt is enabled, the program will
branch to the interrupt vector.
5. Flag bit, RCIF, will be set when reception is
complete. An interrupt will be generated if
enable bit, RCIE, was set.
6. Read the RCSTA register to get the 9th bit (if
enabled) and determine if any error occurred
during reception.
7. Read the 8-bit received data by reading the
RCREG register.
8. If any error occurred, clear the error by clearing
bit CREN.
9. If using interrupts, ensure that the GIE and PEIE
bits in the INTCON register (INTCON<7:6>) are
set.
TABLE 16-10: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE RECEPTION
Value on
all other
Resets
Value on
POR, BOR
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
INTCON
PIR1
GIE/GIEH PEIE/GIEL TMR0IE INT0IE
RBIE
—
TMR0IF INT0IF
RBIF
0000 000x 0000 000u
—
—
ADIF
ADIE
ADIP
RX9
RCIF
RCIE
RCIP
SREN
TXIF
TXIE
TXIP
CCP1IF TMR2IF TMR1IF -000 -000 -000 -000
CCP1IE TMR2IE TMR1IE -000 -000 -000 -000
CCP1IP TMR2IP TMR1IP -111 -111 -111 -111
PIE1
—
IPR1
—
—
RCSTA
RCREG
TXSTA
BAUDCTL
SPEN
CREN ADDEN
FERR
OERR
RX9D
0000 000x 0000 000x
0000 0000 0000 0000
0000 0010 0000 0010
EUSART Receive Register
CSRC
—
TX9
TXEN
—
SYNC
SCKP
SENDB
BRG16
BRGH
—
TRMT
WUE
TX9D
RCIDL
ABDEN -1-1 0-00 -1-1 0-00
0000 0000 0000 0000
SPBRGH Baud Rate Generator Register High Byte
SPBRG Baud Rate Generator Register Low Byte
0000 0000 0000 0000
Legend: x= unknown, – = unimplemented, read as ‘0’. Shaded cells are not used for synchronous slave reception.
© 2007 Microchip Technology Inc.
DS39605F-page 153
PIC18F1220/1320
NOTES:
DS39605F-page 154
© 2007 Microchip Technology Inc.
PIC18F1220/1320
The module has five registers:
17.0 10-BIT ANALOG-TO-DIGITAL
CONVERTER (A/D) MODULE
• A/D Result High Register (ADRESH)
• A/D Result Low Register (ADRESL)
• A/D Control Register 0 (ADCON0)
• A/D Control Register 1 (ADCON1)
• A/D Control Register 2 (ADCON2)
The Analog-to-Digital (A/D) converter module has
seven inputs for the PIC18F1220/1320 devices. This
module allows conversion of an analog input signal to
a corresponding 10-bit digital number.
A new feature for the A/D converter is the addition of
programmable acquisition time. This feature allows the
user to select a new channel for conversion and to set
the GO/DONE bit immediately. When the GO/DONE bit
is set, the selected channel is sampled for the pro-
grammed acquisition time before a conversion is actu-
ally started. This removes the firmware overhead that
may have been required to allow for an acquisition
(sampling) period (see Register 17-3 and Section 17.3
“Selecting and Configuring Automatic Acquisition
Time”).
The ADCON0 register, shown in Register 17-1,
controls the operation of the A/D module. The
ADCON1 register, shown in Register 17-2, configures
the functions of the port pins. The ADCON2 register,
shown in Register 17-3, configures the A/D clock
source, programmed acquisition time and justification.
REGISTER 17-1: ADCON0: A/D CONTROL REGISTER 0
R/W-0
R/W-0
U-0
—
R/W-0
CHS2
R/W-0
CHS1
R/W-0
CHS0
R/W-0
R/W-0
ADON
VCFG1
VCFG0
GO/DONE
bit 7
bit 0
bit 7-6 VCFG<1:0>: Voltage Reference Configuration bits
A/D VREF+
AVDD
A/D VREF-
AVSS
00
01
10
11
External VREF+
AVDD
AVSS
External VREF-
External VREF-
External VREF+
bit 5
Unimplemented: Read as ‘0’
bit 4-2 CHS2:CHS0: Analog Channel Select bits
000= Channel 0 (AN0)
001= Channel 1 (AN1)
010= Channel 2 (AN2)
011= Channel 3 (AN3)
100= Channel 4 (AN4)
101= Channel 5 (AN5)
110= Channel 6 (AN6)
111= Unimplemented(1)
bit 1
bit 0
GO/DONE: A/D Conversion Status bit
When ADON = 1:
1= A/D conversion in progress
0= A/D Idle
ADON: A/D On bit
1= A/D converter module is enabled
0= A/D converter module is disabled
Note 1: Performing a conversion on unimplemented channels returns full-scale results.
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
© 2007 Microchip Technology Inc.
DS39605F-page 155
PIC18F1220/1320
REGISTER 17-2: ADCON1: A/D CONTROL REGISTER 1
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
PCFG6
PCFG5
PCFG4
PCFG3
PCFG2 PCFG1
PCFG0
bit 7
bit 0
bit 7
bit 6
Unimplemented: Read as ‘0’
PCFG6: A/D Port Configuration bit – AN6
1= Pin configured as a digital port
0= Pin configured as an analog channel – digital input disabled and reads ‘0’
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
PCFG5: A/D Port Configuration bit – AN5
1= Pin configured as a digital port
0= Pin configured as an analog channel – digital input disabled and reads ‘0’
PCFG4: A/D Port Configuration bit – AN4
1= Pin configured as a digital port
0= Pin configured as an analog channel – digital input disabled and reads ‘0’
PCFG3: A/D Port Configuration bit – AN3
1= Pin configured as a digital port
0= Pin configured as an analog channel – digital input disabled and reads ‘0’
PCFG2: A/D Port Configuration bit – AN2
1= Pin configured as a digital port
0= Pin configured as an analog channel – digital input disabled and reads ‘0’
PCFG1: A/D Port Configuration bit – AN1
1= Pin configured as a digital port
0= Pin configured as an analog channel – digital input disabled and reads ‘0’
PCFG0: A/D Port Configuration bit – AN0
1= Pin configured as a digital port
0= Pin configured as an analog channel – digital input disabled and reads ‘0’
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
DS39605F-page 156
© 2007 Microchip Technology Inc.
PIC18F1220/1320
REGISTER 17-3: ADCON2: A/D CONTROL REGISTER 2
R/W-0
ADFM
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
ACQT2
ACQT1
ACQT0
ADCS2
ADCS1
ADCS0
bit 7
bit 0
bit 7
ADFM: A/D Result Format Select bit
1= Right justified
0= Left justified
bit 6
Unimplemented: Read as ‘0’
bit 5-3
ACQT2:ACQT0: A/D Acquisition Time Select bits
(1)
000= 0 TAD
001= 2 TAD
010= 4 TAD
011= 6 TAD
100= 8 TAD
101= 12 TAD
110= 16 TAD
111= 20 TAD
bit 2-0
ADCS2:ADCS0: A/D Conversion Clock Select bits
000= FOSC/2
001= FOSC/8
010= FOSC/32
011= FRC (clock derived from A/D RC oscillator)(1)
100= FOSC/4
101= FOSC/16
110= FOSC/64
111= FRC (clock derived from A/D RC oscillator)(1)
Note:
If the A/D FRC clock source is selected, a delay of one TCY (instruction cycle) is
added before the A/D clock starts. This allows the SLEEPinstruction to be executed
before starting a conversion.
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
© 2007 Microchip Technology Inc.
DS39605F-page 157
PIC18F1220/1320
The analog reference voltage is software selectable to
either the device’s positive and negative supply voltage
(AVDD and AVSS), or the voltage level on the
RA3/AN3/VREF+ and RA2/AN2/VREF- pins.
A device Reset forces all registers to their Reset state.
This forces the A/D module to be turned off and any
conversion in progress is aborted.
Each port pin associated with the A/D converter can be
configured as an analog input, or as a digital I/O. The
ADRESH and ADRESL registers contain the result of
the A/D conversion. When the A/D conversion is com-
plete, the result is loaded into the ADRESH/ADRESL
registers, the GO/DONE bit (ADCON0 register) is
cleared and A/D Interrupt Flag bit, ADIF, is set. The block
diagram of the A/D module is shown in Figure 17-1.
The A/D converter has a unique feature of being able
to operate while the device is in Sleep mode. To oper-
ate in Sleep, the A/D conversion clock must be derived
from the A/D’s internal RC oscillator.
The output of the sample and hold is the input into the
converter, which generates the result via successive
approximation.
FIGURE 17-1:
A/D BLOCK DIAGRAM
AVDD
CHS2:CHS0
111
110
AN6(1)
101
AN5
100
AN4
VAIN
011
(Input Voltage)
10-bit
Converter
A/D
AN3/VREF+
010
AN2/VREF-
001
VCFG1:VCFG0
AN1
000
AVDD
AN0
x0
x1
1x
VREFH
VREFL
Reference
Voltage
0x
AVSS
Note 1: I/O pins have diode protection to VDD and VSS.
DS39605F-page 158
© 2007 Microchip Technology Inc.
PIC18F1220/1320
The value in the ADRESH/ADRESL registers is not
modified for a Power-on Reset. The ADRESH/ADRESL
registers will contain unknown data after a Power-on
Reset.
To do an A/D Conversion:
1. Configure the A/D module:
• Configure analog pins, voltage reference and
digital I/O (ADCON1)
After the A/D module has been configured as desired,
the selected channel must be acquired before the con-
version is started. The analog input channels must
have their corresponding TRIS bits selected as an
input. To determine acquisition time, see Section 17.1
“A/D Acquisition Requirements”. After this acquisi-
tion time has elapsed, the A/D conversion can be
started. An acquisition time can be programmed to
occur between setting the GO/DONE bit and the actual
start of the conversion.
• Select A/D input channel (ADCON0)
• Select A/D acquisition time (ADCON2)
• Select A/D conversion clock (ADCON2)
• Turn on A/D module (ADCON0)
2. Configure A/D interrupt (if desired):
• Clear ADIF bit
• Set ADIE bit
• Set GIE bit
3. Wait the required acquisition time (if required).
4. Start conversion:
• Set GO/DONE bit (ADCON0 register)
5. Wait for A/D conversion to complete, by either:
• Polling for the GO/DONE bit to be cleared
OR
• Waiting for the A/D interrupt
6. Read A/D Result registers (ADRESH:ADRESL);
clear bit, ADIF, if required.
7. For the next conversion, go to step 1 or step 2,
as required. The A/D conversion time per bit is
defined as TAD. A minimum wait of 2 TAD is
required before the next acquisition starts.
FIGURE 17-2:
ANALOG INPUT MODEL
VDD
Sampling
Switch
VT = 0.6V
ANx
SS
RIC ≤ 1k
RSS
Rs
CPIN
VAIN
ILEAKAGE
± 500 nA
CHOLD = 120 pF
VT = 0.6V
5 pF
VSS
Legend:
CPIN
VT
= input capacitance
= threshold voltage
6V
5V
VDD 4V
3V
ILEAKAGE = leakage current at the pin due to
various junctions
RIC
= interconnect resistance
= sampling switch
2V
SS
CHOLD
RSS
= sample/hold capacitance (from DAC)
= sampling switch resistance
5
6
7
8 9 10 11
Sampling Switch (kΩ)
© 2007 Microchip Technology Inc.
DS39605F-page 159
PIC18F1220/1320
Example 17-1 shows the calculation of the minimum
required acquisition time, TACQ. This calculation is
based on the following application system
assumptions:
17.1 A/D Acquisition Requirements
For the A/D converter to meet its specified accuracy,
the charge holding capacitor (CHOLD) must be allowed
to fully charge to the input channel voltage level. The
analog input model is shown in Figure 17-2. The
source impedance (RS) and the internal sampling
switch (RSS) impedance directly affect the time
required to charge the capacitor CHOLD. The sampling
switch (RSS) impedance varies over the device voltage
(VDD). The source impedance affects the offset voltage
at the analog input (due to pin leakage current). The
maximum recommended impedance for analog
sources is 2.5 kΩ. After the analog input channel is
selected (changed), the channel must be sampled for
at least the minimum acquisition time before starting a
conversion.
CHOLD
Rs
Conversion Error
VDD
Temperature
VHOLD
=
=
≤
=
=
=
120 pF
2.5 kΩ
1/2 LSb
5V → RSS = 7 kΩ
50°C (system max.)
0V @ time = 0
17.2 A/D VREF+ and VREF- References
If external voltage references are used instead of the
internal AVDD and AVSS sources, the source imped-
ance of the VREF+ and VREF- voltage sources must be
considered. During acquisition, currents supplied by
these sources are insignificant. However, during
conversion, the A/D module sinks and sources current
through the reference sources.
Note:
When the conversion is started, the
holding capacitor is disconnected from the
input pin.
In order to maintain the A/D accuracy, the voltage
reference source impedances should be kept low to
reduce voltage changes. These voltage changes occur
as reference currents flow through the reference
source impedance. The maximum recommended
impedance of the VREF+ and VREF- external
reference voltage sources is 250Ω.
To calculate the minimum acquisition time,
Equation 17-1 may be used. This equation assumes
that 1/2 LSb error is used (1024 steps for the A/D). The
1/2 LSb error is the maximum error allowed for the A/D
to meet its specified resolution.
EQUATION 17-1: ACQUISITION TIME
TACQ
=
=
Amplifier Settling Time + Holding Capacitor Charging Time + Temperature Coefficient
TAMP + TC + TCOFF
EQUATION 17-2: A/D MINIMUM CHARGING TIME
(-TC/CHOLD(RIC + RSS + RS))
VHOLD = (ΔVREF – (ΔVREF/2048)) • (1 – e
)
or
TC
=
-(CHOLD)(RIC + RSS + RS) ln(1/2048)
EXAMPLE 17-1:
CALCULATING THE MINIMUM REQUIRED ACQUISITION TIME
TACQ
TAMP
=
=
TAMP + TC + TCOFF
5 μs
TCOFF = (Temp – 25ºC)(0.05 μs/ºC)
(50ºC – 25ºC)(0.05 μs/ºC)
1.25 μs
Temperature coefficient is only required for temperatures > 25ºC. Below 25ºC, TCOFF = 0 μs.
TC
=
-(CHOLD)(RIC + RSS + RS) ln(1/2047) μs
-(120 pF) (1 kΩ + 7 kΩ + 2.5 kΩ) ln(0.0004883) μs
9.61 μs
5 μs + 1.25 μs + 9.61 μs
12.86 μs
TACQ
=
DS39605F-page 160
© 2007 Microchip Technology Inc.
PIC18F1220/1320
17.3 Selecting and Configuring
Automatic Acquisition Time
17.4 Selecting the A/D Conversion
Clock
The ADCON2 register allows the user to select an
acquisition time that occurs each time the GO/DONE
bit is set.
The A/D conversion time per bit is defined as TAD. The
A/D conversion requires 11 TAD per 10-bit conversion.
The source of the A/D conversion clock is software
selectable. There are seven possible options for TAD:
When the GO/DONE bit is set, sampling is stopped and
a conversion begins. The user is responsible for ensur-
ing the required acquisition time has passed between
selecting the desired input channel and setting the
GO/DONE bit. This occurs when the ACQT2:ACQT0
bits (ADCON2<5:3>) remain in their Reset state (‘000’)
and is compatible with devices that do not offer
programmable acquisition times.
• 2 TOSC
• 4 TOSC
• 8 TOSC
• 16 TOSC
• 32 TOSC
• 64 TOSC
• Internal RC oscillator
If desired, the ACQT bits can be set to select a
programmable acquisition time for the A/D module.
When the GO/DONE bit is set, the A/D module contin-
ues to sample the input for the selected acquisition
time, then automatically begins a conversion. Since the
acquisition time is programmed, there may be no need
to wait for an acquisition time between selecting a
channel and setting the GO/DONE bit.
For correct A/D conversions, the A/D conversion clock
(TAD) must be as short as possible, but greater than the
minimum TAD (approximately 2 μs, see parameter 130
for more information).
Table 17-1 shows the resultant TAD times derived from
the device operating frequencies and the A/D clock
source selected.
In either case, when the conversion is completed, the
GO/DONE bit is cleared, the ADIF flag is set and the
A/D begins sampling the currently selected channel
again. If an acquisition time is programmed, there is
nothing to indicate if the acquisition time has ended or
if the conversion has begun.
TABLE 17-1: TAD vs. DEVICE OPERATING FREQUENCIES
AD Clock Source (TAD)
Maximum Device Frequency
Operation
ADCS2:ADCS0
PIC18F1220/1320
PIC18LF1220/1320(4)
2 TOSC
4 TOSC
8 TOSC
16 TOSC
32 TOSC
64 TOSC
RC(3)
000
100
001
101
010
110
x11
1.25 MHz
2.50 MHz
5.00 MHz
10.0 MHz
20.0 MHz
40.0 MHz
1.00 MHz(1)
666 kHz
1.33 MHz
2.66 MHz
5.33 MHz
10.65 MHz
21.33 MHz
1.00 MHz(2)
Note 1: The RC source has a typical TAD time of 4 μs.
2: The RC source has a typical TAD time of 6 μs.
3: For device frequencies above 1 MHz, the device must be in Sleep for the entire conversion or the A/D
accuracy may be out of specification.
4: Low-power devices only.
© 2007 Microchip Technology Inc.
DS39605F-page 161
PIC18F1220/1320
17.5 Operation in Low-Power Modes
17.6 Configuring Analog Port Pins
The selection of the automatic acquisition time and the
A/D conversion clock is determined, in part, by the low-
power mode clock source and frequency while in a
low-power mode.
The ADCON1, TRISA and TRISB registers all configure
the A/D port pins. The port pins needed as analog inputs
must have their corresponding TRIS bits set (input). If
the TRIS bit is cleared (output), the digital output level
(VOH or VOL) will be converted.
If the A/D is expected to operate while the device is
in
a
low-power mode, the ACQT2:ACQT0 and
The A/D operation is independent of the state of the
CHS2:CHS0 bits and the TRIS bits.
ADCS2:ADCS0 bits in ADCON2 should be updated in
accordance with the low-power mode clock that will be
used. After the low-power mode is entered (either of
the Run modes), an A/D acquisition or conversion may
be started. Once an acquisition or conversion is
started, the device should continue to be clocked by the
same low-power mode clock source until the conver-
sion has been completed. If desired, the device may be
placed into the corresponding low-power (ANY)_IDLE
mode during the conversion.
Note 1: When reading the Port register, all pins
configured as analog input channels will
read as cleared (a low level). Pins con-
figured as digital inputs will convert an
analog input. Analog levels on a digitally
configured input will be accurately
converted.
2: Analog levels on any pin defined as a
digital input may cause the digital input
buffer to consume current out of the
device’s specification limits.
If the low-power mode clock frequency is less than
1 MHz, the A/D RC clock source should be selected.
Operation in the Low-Power Sleep mode requires the
A/D RC clock to be selected. If bits, ACQT2:ACQT0, are
set to ‘000’ and a conversion is started, the conversion
will be delayed one instruction cycle to allow execution
of the SLEEPinstruction and entry to Low-Power Sleep
mode. The IDLEN and SCS bits in the OSCCON register
must have already been cleared prior to starting the
conversion.
DS39605F-page 162
© 2007 Microchip Technology Inc.
PIC18F1220/1320
Clearing the GO/DONE bit during a conversion will
abort the current conversion. The A/D Result register
pair will NOT be updated with the partially completed
17.7 A/D Conversions
Figure 17-3 shows the operation of the A/D converter
after the GO bit has been set and the ACQT2:ACQT0
bits are cleared. A conversion is started after the follow-
ing instruction to allow entry into Low-Power Sleep
mode before the conversion begins.
A/D
conversion
sample.
This
means
the
ADRESH:ADRESL registers will continue to contain
the value of the last completed conversion (or the last
value written to the ADRESH:ADRESL registers).
Figure 17-4 shows the operation of the A/D converter
after the GO bit has been set and the ACQT2:ACQT0
bits are set to ‘010’ and selecting a 4 TAD acquisition
time before the conversion starts.
After the A/D conversion is completed or aborted, a
2 TAD wait is required before the next acquisition can
be started. After this wait, acquisition on the selected
channel is automatically started.
Note:
The GO/DONE bit should NOT be set in
the same instruction that turns on the A/D.
FIGURE 17-3:
A/D CONVERSION TAD CYCLES (ACQT<2:0> = 000, TACQ = 0)
TCY – TAD
TAD7 TAD8 TAD9 TAD10 TAD11
TAD1 TAD2 TAD3 TAD4 TAD5 TAD6
b7
b6
b4
b1
b0
b2
b9
b8
b5
b3
Conversion Starts
Holding capacitor is disconnected from analog input (typically 100 ns)
Set GO bit
Next Q4: ADRESH/ADRESL is loaded, GO bit is cleared,
ADIF bit is set, holding capacitor is connected to analog input.
FIGURE 17-4:
A/D CONVERSION TAD CYCLES (ACQT<2:0> = 010, TACQ = 4 TAD)
TAD Cycles
TACQT Cycles
7
8
9
10
b1
11
b0
1
2
3
4
1
2
3
4
5
6
b7
b6
b3
b2
b8
b5
b4
b9
Automatic
Acquisition
Time
Conversion Starts
(Holding capacitor is disconnected)
Set GO bit
(Holding capacitor continues
acquiring input)
Next Q4: ADRESH:ADRESL is loaded, GO bit is cleared,
ADIF bit is set, holding capacitor is reconnected to analog input.
© 2007 Microchip Technology Inc.
DS39605F-page 163
PIC18F1220/1320
software overhead (moving ADRESH/ADRESL to the
desired location). The appropriate analog input
channel must be selected and the minimum acquisition
period is either timed by the user, or an appropriate
TACQ time selected before the “special event trigger”
sets the GO/DONE bit (starts a conversion).
17.8 Use of the CCP1 Trigger
An A/D conversion can be started by the “special event
trigger” of the CCP1 module. This requires that the
CCP1M3:CCP1M0 bits (CCP1CON<3:0>) be pro-
grammed as ‘1011’ and that the A/D module is enabled
(ADON bit is set). When the trigger occurs, the
GO/DONE bit will be set, starting the A/D acquisition
and conversion and the Timer1 (or Timer3) counter will
be reset to zero. Timer1 (or Timer3) is reset to auto-
matically repeat the A/D acquisition period with minimal
If the A/D module is not enabled (ADON is cleared), the
“special event trigger” will be ignored by the A/D
module, but will still reset the Timer1 (or Timer3)
counter.
TABLE 17-2: SUMMARY OF A/D REGISTERS
Value on
Value on
POR, BOR
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
all other
Resets
INTCON
GIE/
GIEH
PEIE/
GIEL
TMR0IE
INT0IE
RBIE
TMR0IF
INT0IF
RBIF
0000 0000 0000 0000
PIR1
PIE1
IPR1
PIR2
PIE2
IPR2
—
—
ADIF
ADIE
ADIP
—
RCIF
RCIE
RCIP
—
TXIF
TXIE
TXIP
EEIF
EEIE
EEIP
—
—
—
—
—
—
CCP1IF
CCP1IE
CCP1IP
LVDIF
TMR2IF
TMR2IE
TMR2IP
TMR3IF
TMR3IE
TMR3IP
TMR1IF -000 -000 -000 -000
TMR1IE -000 -000 -000 -000
TMR1IP -111 -111 -111 -111
—
OSCFIF
OSCFIE
OSCFIP
—
—
—
0--0 -00- 0--0 -00-
0--0 -00- 0--0 -00-
—
—
LVDIE
—
—
LVDIP
1--1 -11- 1--1 -11-
ADRESH A/D Result Register High Byte
ADRESL A/D Result Register Low Byte
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
ADCON0
ADCON1
ADCON2
PORTA
TRISA
VCFG1
—
VCFG0
PCFG6
—
—
CHS2
PCFG4
ACQT1
RA4
CHS1
CHS0 GO/DONE ADON
00-0 0000 00-0 0000
PCFG5
ACQT2
PCFG3 PCFG2
ACQT0 ADCS2
PCFG1
ADCS1
RA1
PCFG0 -000 0000 -000 0000
ADCS0 0-00 0000 0-00 0000
ADFM
(3)
(2)
(1)
RA7
RA6
RA5
RA3
RA2
RA0
qq0x 0000 uu0u 0000
qq-1 1111 11-1 1111
xxxx xxxx uuuu uuuu
1111 1111 1111 1111
xxxx xxxx uuuu uuuu
(3)
(2)
TRISA7
TRISA6
—
PORTA Data Direction Register
PORTB
TRISB
Read PORTB pins, Write LATB Latch
PORTB Data Direction Register
PORTB Output Data Latch
LATB
Legend:
x= unknown, u= unchanged, q= depends on CONFIG1H<3:0>, – = unimplemented, read as ‘0’.
Shaded cells are not used for A/D conversion.
Note 1: RA5 port bit is available only as an input pin when the MCLRE bit in the configuration register is ‘0’.
2: RA6 and TRISA6 are available only when the primary oscillator mode selection offers RA6 as a port pin; otherwise, RA6
always reads ‘0’, TRISA6 always reads ‘1’ and writes to both are ignored (see CONFIG1H<3:0>).
3: RA7 and TRISA7 are available only when the internal RC oscillator is configured as the primary oscillator in
CONFIG1H<3:0>; otherwise, RA7 always reads ‘0’, TRISA7 always reads ‘1’ and writes to both are ignored.
DS39605F-page 164
© 2007 Microchip Technology Inc.
PIC18F1220/1320
Figure 18-1 shows a possible application voltage curve
(typically for batteries). Over time, the device voltage
decreases. When the device voltage equals voltage VA,
the LVD logic generates an interrupt. This occurs at
time TA. The application software then has the time,
until the device voltage is no longer in valid operating
range, to shut down the system. Voltage point VB is the
minimum valid operating voltage specification. This
occurs at time TB. The difference, TB – TA, is the total
time for shutdown.
18.0 LOW-VOLTAGE DETECT
In many applications, the ability to determine if the
device voltage (VDD) is below a specified voltage level
is a desirable feature. A window of operation for the
application can be created, where the application soft-
ware can do “housekeeping tasks”, before the device
voltage exits the valid operating range. This can be
done using the Low-Voltage Detect module.
This module is a software programmable circuitry,
where a device voltage trip point can be specified.
When the voltage of the device becomes lower then the
specified point, an interrupt flag is set. If the interrupt is
enabled, the program execution will branch to the inter-
rupt vector address and the software can then respond
to that interrupt source.
The block diagram for the LVD module is shown in
Figure 18-2 (following page). A comparator uses an
internally generated reference voltage as the set point.
When the selected tap output of the device voltage
crosses the set point (is lower than), the LVDIF bit is set.
Each node in the resistor divider represents a “trip
point” voltage. The “trip point” voltage is the minimum
supply voltage level at which the device can operate
before the LVD module asserts an interrupt. When the
supply voltage is equal to the trip point, the voltage
tapped off of the resistor array is equal to the 1.2V
internal reference voltage generated by the voltage
reference module. The comparator then generates an
interrupt signal setting the LVDIF bit. This voltage is
software programmable to any one of 16 values (see
Figure 18-2). The trip point is selected by
programming the LVDL3:LVDL0 bits (LVDCON<3:0>).
The Low-Voltage Detect circuitry is completely under
software control. This allows the circuitry to be turned
off by the software, which minimizes the current
consumption for the device.
FIGURE 18-1:
TYPICAL LOW-VOLTAGE DETECT APPLICATION
VA
VB
Legend: VA = LVD trip point
VB = Minimum valid device
operating voltage
TB
TA
Time
© 2007 Microchip Technology Inc.
DS39605F-page 165
PIC18F1220/1320
FIGURE 18-2:
LOW-VOLTAGE DETECT (LVD) BLOCK DIAGRAM
VDD
LVDIN
LVD Control
Register
LVDIF
Internally Generated
LVDEN
Reference Voltage
1.2V
The LVD module has an additional feature that allows
the user to supply the trip voltage to the module from
an external source. This mode is enabled when bits,
LVDL3:LVDL0, are set to ‘1111’. In this state, the com-
parator input is multiplexed from the external input pin,
LVDIN (Figure 18-3). This gives users flexibility,
because it allows them to configure the Low-Voltage
Detect interrupt to occur at any voltage in the valid
operating range.
FIGURE 18-3:
LOW-VOLTAGE DETECT (LVD) WITH EXTERNAL INPUT BLOCK DIAGRAM
VDD
VDD
LVD Control
Register
LVDIN
LVDEN
Externally Generated
Trip Point
LVD
VxEN
BODEN
EN
BGAP
DS39605F-page 166
© 2007 Microchip Technology Inc.
PIC18F1220/1320
18.1 Control Register
The Low-Voltage Detect Control register controls the
operation of the Low-Voltage Detect circuitry.
REGISTER 18-1: LVDCON REGISTER
U-0
—
U-0
—
R-0
R/W-0
R/W-0
LVDL3
R/W-1
LVDL2
R/W-0
LVDL1
R/W-1
LVDL0
IRVST
LVDEN
bit 7
bit 0
bit 7-6 Unimplemented: Read as ‘0’
bit 5
bit 4
IRVST: Internal Reference Voltage Stable Flag bit
1= Indicates that the Low-Voltage Detect logic will generate the interrupt flag at the specified
voltage range
0= Indicates that the Low-Voltage Detect logic will not generate the interrupt flag at the
specified voltage range and the LVD interrupt should not be enabled
LVDEN: Low-Voltage Detect Power Enable bit
1= Enables LVD, powers up LVD circuit
0= Disables LVD, powers down LVD circuit
bit 3-0 LVDL3:LVDL0: Low-Voltage Detection Limit bits
1111= External analog input is used (input comes from the LVDIN pin)
1110= 4.04V-5.15V
1101= 3.76V-4.79V
1100= 3.58V-4.56V
1011= 3.41V-4.34V
1010= 3.23V-4.11V
1001= 3.14V-4.00V
1000= 2.96V-3.77V
0111= 2.70V-3.43V
0110= 2.53V-3.21V
0101= 2.43V-3.10V
0100= 2.25V-2.86V
0011= 2.16V-2.75V
0010= 1.99V-2.53V
0001= Reserved
0000= Reserved
Note:
LVDL3:LVDL0 modes, which result in a trip point below the valid operating voltage
of the device, are not tested.
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
© 2007 Microchip Technology Inc.
DS39605F-page 167
PIC18F1220/1320
The following steps are needed to set up the LVD
module:
18.2 Operation
Depending on the power source for the device voltage,
the voltage normally decreases relatively slowly. This
means that the LVD module does not need to be
constantly operating. To decrease the current require-
ments, the LVD circuitry only needs to be enabled for
short periods, where the voltage is checked. After
doing the check, the LVD module may be disabled.
1. Write the value to the LVDL3:LVDL0 bits
(LVDCON register), which selects the desired
LVD trip point.
2. Ensure that LVD interrupts are disabled (the
LVDIE bit is cleared or the GIE bit is cleared).
3. Enable the LVD module (set the LVDEN bit in
the LVDCON register).
Each time that the LVD module is enabled, the circuitry
requires some time to stabilize. After the circuitry has
stabilized, all status flags may be cleared. The module
will then indicate the proper state of the system.
4. Wait for the LVD module to stabilize (the IRVST
bit to become set).
5. Clear the LVD interrupt flag, which may have
falsely become set, until the LVD module has
stabilized (clear the LVDIF bit).
6. Enable the LVD interrupt (set the LVDIE and the
GIE bits).
Figure 18-4 shows typical waveforms that the LVD
module may be used to detect.
FIGURE 18-4:
LOW-VOLTAGE DETECT WAVEFORMS
CASE 1:
LVDIF may not be set.
VDD
VLVD
LVDIF
Enable LVD
Internally Generated
Reference Stable
TIVRST
LVDIF cleared in software
CASE 2:
VDD
VLVD
LVDIF
Enable LVD
TIVRST
Internally Generated
Reference Stable
LVDIF cleared in software
LVDIF cleared in software,
LVDIF remains set since LVD condition still exists
DS39605F-page 168
© 2007 Microchip Technology Inc.
PIC18F1220/1320
18.2.1
REFERENCE VOLTAGE SET POINT
18.3 Operation During Sleep
The internal reference voltage of the LVD module may
be used by other internal circuitry (the programmable
Brown-out Reset). If these circuits are disabled (lower
current consumption), the reference voltage circuit
requires a time to become stable before a low-voltage
condition can be reliably detected. This time is invariant
of system clock speed. This start-up time is specified in
electrical specification parameter 36. The low-voltage
interrupt flag will not be enabled until a stable reference
voltage is reached. Refer to the waveform in Figure 18-4.
When enabled, the LVD circuitry continues to operate
during Sleep. If the device voltage crosses the trip
point, the LVDIF bit will be set and the device will wake-
up from Sleep. Device execution will continue from the
interrupt vector address if interrupts have been globally
enabled.
18.4 Effects of a Reset
A device Reset forces all registers to their Reset state.
This forces the LVD module to be turned off.
18.2.2
CURRENT CONSUMPTION
When the module is enabled, the LVD comparator and
voltage divider are enabled and will consume static cur-
rent. The voltage divider can be tapped from multiple
places in the resistor array. Total current consumption,
when enabled, is specified in electrical specification
parameter D022B.
© 2007 Microchip Technology Inc.
DS39605F-page 169
PIC18F1220/1320
NOTES:
DS39605F-page 170
© 2007 Microchip Technology Inc.
PIC18F1220/1320
The inclusion of an internal RC oscillator also provides
the additional benefits of a Fail-Safe Clock Monitor
(FSCM) and Two-Speed Start-up. FSCM provides for
background monitoring of the peripheral clock and
automatic switchover in the event of its failure. Two-
Speed Start-up enables code to be executed almost
immediately on start-up, while the primary clock source
completes its start-up delays.
19.0 SPECIAL FEATURES OF
THE CPU
PIC18F1220/1320 devices include several features
intended to maximize system reliability, minimize cost
through elimination of external components and offer
code protection. These are:
• Oscillator Selection
• Resets:
All of these features are enabled and configured by
setting the appropriate configuration register bits.
- Power-on Reset (POR)
- Power-up Timer (PWRT)
- Oscillator Start-up Timer (OST)
- Brown-out Reset (BOR)
• Interrupts
19.1 Configuration Bits
The configuration bits can be programmed (read as
‘0’), or left unprogrammed (read as ‘1’), to select vari-
ous device configurations. These bits are mapped
starting at program memory location 300000h.
• Watchdog Timer (WDT)
• Fail-Safe Clock Monitor
• Two-Speed Start-up
• Code Protection
The user will note that address 300000h is beyond the
user program memory space. In fact, it belongs to the
configuration memory space (300000h-3FFFFFh),
which can only be accessed using table reads and
table writes.
• ID Locations
• In-Circuit Serial Programming
Programming the configuration registers is done in a
manner similar to programming the Flash memory. The
EECON1 register WR bit starts a self-timed write to the
configuration register. In normal operation mode, a
TBLWT instruction, with the TBLPTR pointing to the
configuration register, sets up the address and the data
for the configuration register write. Setting the WR bit
starts a long write to the configuration register. The con-
figuration registers are written a byte at a time. To write
or erase a configuration cell, a TBLWTinstruction can
write a ‘1’ or a ‘0’ into the cell. For additional details on
Flash programming, refer to Section 6.5 “Writing to
Flash Program Memory”.
Several oscillator options are available to allow the part
to fit the application. The RC oscillator option saves
system cost, while the LP crystal option saves power.
These are discussed in detail in Section 2.0 “Oscillator
Configurations”.
A complete discussion of device Resets and interrupts
is available in previous sections of this data sheet.
In addition to their Power-up and Oscillator Start-up
Timers provided for Resets, PIC18F1220/1320 devices
have a Watchdog Timer, which is either permanently
enabled via the configuration bits, or software
controlled (if configured as disabled).
TABLE 19-1: CONFIGURATION BITS AND DEVICE IDS
Default/
Unprogrammed
Value
File Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
300001h CONFIG1H
300002h CONFIG2L
300003h CONFIG2H
IESO
—
FSCM
—
—
—
—
—
FOSC3
BORV1
FOSC2
BORV0
FOSC1
BOR
FOSC0
PWRTEN
WDT
—
11-- 1111
---- 1111
---1 1111
1--- ----
1--- -1-1
---- --11
11-- ----
---- --11
111- ----
---- --11
-1-- ----
—
—
—
WDTPS3 WDTPS2 WDTPS1 WDTPS0
300005h CONFIG3H MCLRE
300006h CONFIG4L DEBUG
—
—
—
—
—
—
—
LVP
—
—
—
—
—
STVR
CP0
300008h CONFIG5L
300009h CONFIG5H
30000Ah CONFIG6L
—
CPD
—
—
—
—
—
CP1
—
CPB
—
—
—
—
—
—
—
—
—
—
WRT1
—
WRT0
—
30000Bh CONFIG6H WRTD
WRTB
—
WRTC
—
—
—
—
30000Ch CONFIG7L
30000Dh CONFIG7H
—
—
—
—
—
EBTR1
—
EBTR0
—
EBTRB
DEV1
DEV9
—
—
—
—
(1)
(1)
3FFFFEh DEVID1
DEV2
DEV10
DEV0
DEV8
REV4
DEV7
REV3
DEV6
REV2
DEV5
REV1
DEV4
REV0
DEV3
xxxx xxxx
(1)
3FFFFFh DEVID2
0000 0111
Legend:
x= unknown, u= unchanged, – = unimplemented. Shaded cells are unimplemented, read as ‘0’.
Note 1: See Register 19-14 for DEVID1 values. DEVID registers are read-only and cannot be programmed by the user.
© 2007 Microchip Technology Inc.
DS39605F-page 171
PIC18F1220/1320
REGISTER 19-1: CONFIG1H:CONFIGURATIONREGISTER1HIGH(BYTEADDRESS300001h)
R/P-1
IESO
R/P-1
U-0
—
U-0
—
R/P-1
R/P-1
R/P-1
R/P-1
FSCM
FOSC3
FOSC2
FOSC1
FOSC0
bit 7
bit 0
bit 7
bit 6
IESO: Internal External Switchover bit
1= Internal External Switchover mode enabled
0= Internal External Switchover mode disabled
FSCM: Fail-Safe Clock Monitor Enable bit
1= Fail-Safe Clock Monitor enabled
0= Fail-Safe Clock Monitor disabled
bit 5-4 Unimplemented: Read as ‘0’
bit 3-0 FOSC<3:0>: Oscillator Selection bits
11xx= External RC oscillator, CLKO function on RA6
1001= Internal RC oscillator, CLKO function on RA6 and port function on RA7
1000= Internal RC oscillator, port function on RA6 and port function on RA7
0111= External RC oscillator, port function on RA6
0110= HS oscillator, PLL enabled (clock frequency = 4 x FOSC1)
0101= EC oscillator, port function on RA6
0100= EC oscillator, CLKO function on RA6
0010= HS oscillator
0001= XT oscillator
0000= LP oscillator
Legend:
R = Readable bit
P = Programmable bit U = Unimplemented bit, read as ‘0’
u = Unchanged from programmed state
-n = Value when device is unprogrammed
DS39605F-page 172
© 2007 Microchip Technology Inc.
PIC18F1220/1320
REGISTER 19-2: CONFIG2L:CONFIGURATION REGISTER 2 LOW (BYTE ADDRESS300002h)
U-0
—
U-0
—
U-0
—
U-0
—
R/P-1
R/P-1
R/P-1
BOR
R/P-1
PWRTEN
bit 0
BORV1
BORV0
bit 7
bit 7-4 Unimplemented: Read as ‘0’
bit 3-2 BORV1:BORV0: Brown-out Reset Voltage bits
11= Reserved
10= VBOR set to 2.7V
01= VBOR set to 4.2V
00= VBOR set to 4.5V
bit 1
bit 0
BOR: Brown-out Reset Enable bit(1)
1= Brown-out Reset enabled
0= Brown-out Reset disabled
PWRTEN: Power-up Timer Enable bit(1)
1= PWRT disabled
0= PWRT enabled
Note 1: The Power-up Timer is decoupled from Brown-out Reset, allowing these features to
be independently controlled.
Legend:
R = Readable bit
P = Programmable bit
U = Unimplemented bit, read as ‘0’
-n = Value when device is unprogrammed
u = Unchanged from programmed state
© 2007 Microchip Technology Inc.
DS39605F-page 173
PIC18F1220/1320
REGISTER 19-3: CONFIG2H: CONFIGURATION REGISTER 2 HIGH (BYTE ADDRESS 300003h)
U-0
—
U-0
—
U-0
—
R/P-1
R/P-1
R/P-1
R/P-1
R/P-1
WDTPS3 WDTPS2 WDTPS1 WDTPS0 WDTEN
bit 0
bit 7
bit 7-5 Unimplemented: Read as ‘0’
bit 4-1 WDTPS<3:0>: Watchdog Timer Postscale Select bits
1111= 1:32,768
1110= 1:16,384
1101= 1:8,192
1100= 1:4,096
1011= 1:2,048
1010= 1:1,024
1001= 1:512
1000= 1:256
0111= 1:128
0110= 1:64
0101= 1:32
0100= 1:16
0011= 1:8
0010= 1:4
0001= 1:2
0000= 1:1
bit 0
WDT: Watchdog Timer Enable bit
1= WDT enabled
0= WDT disabled (control is placed on the SWDTEN bit)
Legend:
R = Readable bit
P = Programmable bit
U = Unimplemented bit, read as ‘0’
-n = Value when device is unprogrammed
u = Unchanged from programmed state
DS39605F-page 174
© 2007 Microchip Technology Inc.
PIC18F1220/1320
REGISTER 19-4: CONFIG3H:CONFIGURATIONREGISTER3HIGH(BYTEADDRESS300005h)
R/P-1
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
MCLRE
bit 7
bit 0
bit 7
MCLRE: MCLR Pin Enable bit
1= MCLR pin enabled, RA5 input pin disabled
0= RA5 input pin enabled, MCLR disabled
bit 6-0 Unimplemented: Read as ‘0’
Legend:
R = Readable bit
P = Programmable bit U = Unimplemented bit, read as ‘0’
-n = Value when device is unprogrammed
u = Unchanged from programmed state
REGISTER 19-5: CONFIG4L:CONFIGURATION REGISTER 4 LOW (BYTE ADDRESS300006h)
R/P-1
U-0
—
U-0
—
U-0
—
U-0
—
R/P-1
LVP
U-0
—
R/P-1
STVR
DEBUG
bit 7
bit 0
bit 7
DEBUG: Background Debugger Enable bit (see note)
1= Background debugger disabled, RB6 and RB7 configured as general purpose I/O pins
0= Background debugger enabled, RB6 and RB7 are dedicated to In-Circuit Debug
bit 6-3 Unimplemented: Read as ‘0’
bit 2
LVP: Low-Voltage ICSP Enable bit
1= Low-Voltage ICSP enabled
0= Low-Voltage ICSP disabled
bit 1
bit 0
Unimplemented: Read as ‘0’
STVR: Stack Full/Underflow Reset Enable bit
1= Stack full/underflow will cause Reset
0= Stack full/underflow will not cause Reset
Legend:
R = Readable bit
C = Clearable bit
U = Unimplemented bit, read as ‘0’
-n = Value when device is unprogrammed
u = Unchanged from programmed state
Note:
The Timer1 oscillator shares the T1OSI and T1OSO pins with the PGD and PGC
pins used for programming and debugging.
When using the Timer1 oscillator, In-Circuit Serial Programming (ICSP) may not
function correctly (high voltage or low voltage), or the In-Circuit Debugger (ICD) may
not communicate with the controller. As a result of using either ICSP or ICD, the
Timer1 crystal may be damaged.
If ICSP or ICD operations are required, the crystal should be disconnected from the
circuit (disconnect either lead) or installed after programming. The oscillator loading
capacitors may remain in-circuit during ICSP or ICD operation.
© 2007 Microchip Technology Inc.
DS39605F-page 175
PIC18F1220/1320
REGISTER 19-6: CONFIG5L:CONFIGURATION REGISTER 5 LOW (BYTE ADDRESS300008h)
U-0
—
U-0
—
U-0
—
U-0
—
R/C-1
—
R/C-1
—
R/C-1
CP1
R/C-1
CP0
bit 7
bit 0
bit 7-2 Unimplemented: Read as ‘0’
bit 1
bit 0
bit 1
bit 0
CP1: Code Protection bit (PIC18F1320)
1= Block 1 (001000-001FFFh) not code-protected
0= Block 1 (001000-001FFFh) code-protected
CP0: Code Protection bit (PIC18F1320)
1= Block 0 (00200-000FFFh) not code-protected
0= Block 0 (00200-000FFFh) code-protected
CP1: Code Protection bit (PIC18F1220)
1= Block 1 (000800-000FFFh) not code-protected
0= Block 1 (000800-000FFFh) code-protected
CP0: Code Protection bit (PIC18F1220)
1= Block 0 (000200-0007FFh) not code-protected
0= Block 0 (000200-0007FFh) code-protected
Legend:
R = Readable bit
C = Clearable bit
U = Unimplemented bit, read as ‘0’
u = Unchanged from programmed state
-n = Value when device is unprogrammed
REGISTER 19-7: CONFIG5H:CONFIGURATIONREGISTER5HIGH(BYTEADDRESS300009h)
R/C-1
CPD
R/C-1
CPB
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
bit 7
bit 0
bit 7
bit 6
CPD: Data EEPROM Code Protection bit
1= Data EEPROM not code-protected
0= Data EEPROM code-protected
CPB: Boot Block Code Protection bit
1= Boot Block (000000-0001FFh) not code-protected
0= Boot Block (000000-0001FFh) code-protected
bit 5-0 Unimplemented: Read as ‘0’
Legend:
R = Readable bit
C = Clearable bit
U = Unimplemented bit, read as ‘0’
-n = Value when device is unprogrammed
u = Unchanged from programmed state
DS39605F-page 176
© 2007 Microchip Technology Inc.
PIC18F1220/1320
REGISTER 19-8: CONFIG6L:CONFIGURATIONREGISTER6LOW(BYTEADDRESS30000Ah)
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
R/P-1
R/P-1
WRT1
WRT0
bit 7
bit 0
bit 7-2 Unimplemented: Read as ‘0’
bit 1
bit 0
bit 1
bit 0
WRT1: Write Protection bit (PIC18F1320)
1= Block 1 (001000-001FFFh) not write-protected
0= Block 1 (001000-001FFFh) write-protected
WRT0: Write Protection bit (PIC18F1320)
1= Block 0 (00200-000FFFh) not write-protected
0= Block 0 (00200-000FFFh) write-protected
WRT1: Write Protection bit (PIC18F1220)
1= Block 1 (000800-000FFFh) not write-protected
0= Block 1 (000800-000FFFh) write-protected
WRT0: Write Protection bit (PIC18F1220)
1= Block 0 (000200-0007FFh) not write-protected
0= Block 0 (000200-0007FFh) write-protected
Legend:
R = Readable bit
P = Programmable bit
U = Unimplemented bit, read as ‘0’
u = Unchanged from programmed state
-n = Value when device is unprogrammed
REGISTER 19-9: CONFIG6H:CONFIGURATION REGISTER6 HIGH(BYTEADDRESS30000Bh)
R/P-1
R/P-1
R-1
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
WRTD
WRTB
WRTC
bit 7
bit 0
bit 7
bit 6
bit 5
WRTD: Data EEPROM Write Protection bit
1= Data EEPROM not write-protected
0= Data EEPROM write-protected
WRTB: Boot Block Write Protection bit
1= Boot Block (000000-0001FFh) not write-protected
0= Boot Block (000000-0001FFh) write-protected
WRTC: Configuration Register Write Protection bit
1= Configuration registers (300000-3000FFh) not write-protected
0= Configuration registers (300000-3000FFh) write-protected
Note:
This bit is read-only in normal execution mode; it can be written only in Program mode.
bit 4-0 Unimplemented: Read as ‘0’
Legend:
R = Readable bit
P = Programmable bit U = Unimplemented bit, read as ‘0’
-n = Value when device is unprogrammed
u = Unchanged from programmed state
© 2007 Microchip Technology Inc.
DS39605F-page 177
PIC18F1220/1320
REGISTER 19-10: CONFIG7L:CONFIGURATIONREGISTER7LOW(BYTEADDRESS30000Ch)
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
R/P-1
R/P-1
EBTR1
EBTR0
bit 7
bit 0
bit 7-2 Unimplemented: Read as ‘0’
bit 1
bit 0
bit 1
bit 0
EBTR1: Table Read Protection bit (PIC18F1320)
1= Block 1 (001000-001FFFh) not protected from table reads executed in other blocks
0= Block 1 (001000-001FFFh) protected from table reads executed in other blocks
EBTR0: Table Read Protection bit (PIC18F1320)
1= Block 0 (00200-000FFFh) not protected from table reads executed in other blocks
0= Block 0 (00200-000FFFh) protected from table reads executed in other blocks
EBTR1: Table Read Protection bit (PIC18F1220)
1= Block 1 (000800-000FFFh) not protected from table reads executed in other blocks
0= Block 1 (000800-000FFFh) protected from table reads executed in other blocks
EBTR0: Table Read Protection bit (PIC18F1220)
1= Block 0 (000200-0007FFh) not protected from table reads executed in other blocks
0= Block 0 (000200-0007FFh) protected from table reads executed in other blocks
Legend:
R = Readable bit
P = Programmable bit
U = Unimplemented bit, read as ‘0’
u = Unchanged from programmed state
-n = Value when device is unprogrammed
REGISTER 19-11: CONFIG7H:CONFIGURATION REGISTER7 HIGH(BYTEADDRESS30000Dh)
U-0
—
R/P-1
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
EBTRB
bit 7
bit 0
bit 7
bit 6
Unimplemented: Read as ‘0’
EBTRB: Boot Block Table Read Protection bit
1= Boot Block (000000-0001FFh) not protected from table reads executed in other blocks
0= Boot Block (000000-0001FFh) protected from table reads executed in other blocks
bit 5-0 Unimplemented: Read as ‘0’
Legend:
R = Readable bit
P = Programmable bit U = Unimplemented bit, read as ‘0’
-n = Value when device is unprogrammed
u = Unchanged from programmed state
DS39605F-page 178
© 2007 Microchip Technology Inc.
PIC18F1220/1320
REGISTER 19-12: DEVID1: DEVICE ID REGISTER 1 FOR PIC18F1220/1320 DEVICES
R
R
R
R
R
R
R
R
DEV2
DEV1
DEV0
REV4
REV3
REV2
REV1
REV0
bit 7
bit 0
bit 7-5 DEV2:DEV0: Device ID bits
111= PIC18F1220
110= PIC18F1320
bit 4-0 REV4:REV0: Revision ID bits
These bits are used to indicate the device revision.
Legend:
R = Read-only bit
P = Programmable bit U = Unimplemented bit, read as ‘0’
u = Unchanged from programmed state
-n = Value when device is unprogrammed
REGISTER 19-13: DEVID2: DEVICE ID REGISTER 2 FOR PIC18F1220/1320 DEVICES
R
R
R
R
R
R
R
R
DEV10
DEV9
DEV8
DEV7
DEV6
DEV5
DEV4
DEV3
bit 7
bit 0
bit 7-0 DEV10:DEV3: Device ID bits
These bits are used with the DEV2:DEV0 bits in the Device ID Register 1 to identify the
part number.
0000 0111= PIC18F1220/1320 devices
Note:
These values for DEV10:DEV3 may be shared with other devices. The specific
device is always identified by using the entire DEV10:DEV0 bit sequence.
Legend:
R = Read-only bit
P = Programmable bit U = Unimplemented bit, read as ‘0’
u = Unchanged from programmed state
-n = Value when device is unprogrammed
© 2007 Microchip Technology Inc.
DS39605F-page 179
PIC18F1220/1320
19.2 Watchdog Timer (WDT)
Note 1: The CLRWDT and SLEEP instructions
clear the WDT and postscaler counts
when executed.
For PIC18F1220/1320 devices, the WDT is driven by the
INTRC source. When the WDT is enabled, the clock
source is also enabled. The nominal WDT period is 4 ms
and has the same stability as the INTRC oscillator.
2: Changing the setting of the IRCF bits
(OSCCON<6:4>) clears the WDT and
postscaler counts.
The 4 ms period of the WDT is multiplied by a 16-bit
postscaler. Any output of the WDT postscaler is selected
by a multiplexer, controlled by bits in Configuration
Register 2H. Available periods range from 4 ms to
131.072 seconds (2.18 minutes). The WDT and
postscaler are cleared when any of the following events
occur: execute a SLEEPor CLRWDTinstruction, the IRCF
bits (OSCCON<6:4>) are changed or a clock failure has
occurred.
3: When a CLRWDT instruction is executed
the postscaler count will be cleared.
19.2.1
CONTROL REGISTER
Register 19-14 shows the WDTCON register. This is a
readable and writable register, which contains a control
bit that allows software to override the WDT enable
configuration bit, only if the configuration bit has
disabled the WDT.
Adjustments to the internal oscillator clock period using
the OSCTUNE register also affect the period of the
WDT by the same factor. For example, if the INTRC
period is increased by 3%, then the WDT period is
increased by 3%.
FIGURE 19-1:
WDT BLOCK DIAGRAM
Enable WDT
SWDTEN
WDTEN
INTRC Control
WDT Counter
Wake-up
from Sleep
÷125
INTRC Oscillator
(31 kHz)
CLRWDT
All Device
Resets
WDT
Reset
Reset
WDT
Programmable Postscaler
1:1 to 1:32,768
4
WDTPS<3:0>
Sleep
REGISTER 19-14: WDTCON REGISTER
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
R/W-0
SWDTEN
bit 0
bit 7
bit 7-1 Unimplemented: Read as ‘0’
bit 0
SWDTEN: Software Controlled Watchdog Timer Enable bit
1= Watchdog Timer is on
0= Watchdog Timer is off
Note:
This bit has no effect if the configuration bit, WDTEN (CONFIG2H<0>), is enabled.
Legend:
R = Readable bit
W = Writable bit
-n = Value at POR
U = Unimplemented bit, read as ‘0’
DS39605F-page 180
© 2007 Microchip Technology Inc.
PIC18F1220/1320
TABLE 19-2: SUMMARY OF WATCHDOG TIMER REGISTERS
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
CONFIG2H
RCON
—
IPEN
—
—
—
—
—
—
—
WDTPS3
WDTPS2
WDTPS2
PD
WDTPS0
POR
WDTEN
BOR
RI
—
TO
—
WDTCON
Legend:
—
—
SWDTEN
Shaded cells are not used by the Watchdog Timer.
In all other power managed modes, Two-Speed Start-up
is not used. The device will be clocked by the currently
selected clock source until the primary clock source
becomes available. The setting of the IESO bit is
ignored.
19.3 Two-Speed Start-up
The Two-Speed Start-up feature helps to minimize the
latency period from oscillator start-up to code execution
by allowing the microcontroller to use the INTRC oscil-
lator as a clock source until the primary clock source is
available. It is enabled by setting the IESO bit in
Configuration Register 1H (CONFIG1H<7>).
19.3.1
SPECIAL CONSIDERATIONS FOR
USING TWO-SPEED START-UP
Two-Speed Start-up is available only if the primary oscil-
lator mode is LP, XT, HS or HSPLL (crystal-based
modes). Other sources do not require an OST start-up
delay; for these, Two-Speed Start-up is disabled.
While using the INTRC oscillator in Two-Speed Start-
up, the device still obeys the normal command
sequences for entering power managed modes, includ-
ing serial SLEEP instructions (refer to Section 3.1.3
“Multiple Sleep Commands”). In practice, this means
that user code can change the SCS1:SCS0 bit settings
and issue SLEEPcommands before the OST times out.
This would allow an application to briefly wake-up, per-
form routine “housekeeping” tasks and return to Sleep
before the device starts to operate from the primary
oscillator.
When enabled, Resets and wake-ups from Sleep mode
cause the device to configure itself to run from the
internal oscillator block as the clock source, following
the time-out of the Power-up Timer after a Power-on
Reset is enabled. This allows almost immediate code
execution while the primary oscillator starts and the
OST is running. Once the OST times out, the device
automatically switches to PRI_RUN mode.
User code can also check if the primary clock source is
currently providing the system clocking by checking the
status of the OSTS bit (OSCCON<3>). If the bit is set,
the primary oscillator is providing the system clock.
Otherwise, the internal oscillator block is providing the
clock during wake-up from Reset or Sleep mode.
Because the OSCCON register is cleared on Reset
events, the INTOSC (or postscaler) clock source is not
initially available after a Reset event; the INTRC clock
is used directly at its base frequency. To use a higher
clock speed on wake-up, the INTOSC or postscaler
clock sources can be selected to provide a higher clock
speed by setting bits, IFRC2:IFRC0, immediately after
Reset. For wake-ups from Sleep, the INTOSC or
postscaler clock sources can be selected by setting
IFRC2:IFRC0 prior to entering Sleep mode.
FIGURE 19-2:
TIMING TRANSITION FOR TWO-SPEED START-UP (INTOSC TO HSPLL)
Q3
Q4
Q1
Q2 Q3 Q4 Q1 Q2 Q3 Q4
Q1
Q2
INTOSC
Multiplexer
OSC1
(1)
TOST
(1)
TPLL
PLL Clock
Output
1
2
3
4
5
6
7
8
Clock Transition
CPU Clock
Peripheral
Clock
Program
Counter
PC + 4
PC
PC + 2
PC + 6
OSTS bit Set
Note 1: TOST = 1024 TOSC; TPLL = 2 ms (approx). These intervals are not shown to scale.
Wake from Interrupt Event
© 2007 Microchip Technology Inc.
DS39605F-page 181
PIC18F1220/1320
Since the postscaler frequency from the internal oscil-
lator block may not be sufficiently stable, it may be
desirable to select another clock configuration and
enter an alternate power managed mode (see
Section 19.3.1 “Special Considerations for Using
Two-Speed Start-up” and Section 3.1.3 “Multiple
Sleep Commands” for more details). This can be
done to attempt a partial recovery, or execute a
controlled shutdown.
19.4 Fail-Safe Clock Monitor
The Fail-Safe Clock Monitor (FSCM) allows the micro-
controller to continue operation, in the event of an
external oscillator failure, by automatically switching
the system clock to the internal oscillator block. The
FSCM function is enabled by setting the Fail-Safe
Clock Monitor Enable bit, FSCM (CONFIG1H<6>).
When FSCM is enabled, the INTRC oscillator runs at
all times to monitor clocks to peripherals and provide
an instant backup clock in the event of a clock failure.
Clock monitoring (shown in Figure 19-3) is accom-
plished by creating a sample clock signal, which is the
INTRC output divided by 64. This allows ample time
between FSCM sample clocks for a peripheral clock
edge to occur. The peripheral system clock and the
sample clock are presented as inputs to the Clock
Monitor latch (CM). The CM is set on the falling edge of
the system clock source, but cleared on the rising edge
of the sample clock.
To use a higher clock speed on wake-up, the INTOSC
or postscaler clock sources can be selected to provide
a higher clock speed by setting bits, IFRC2:IFRC0,
immediately after Reset. For wake-ups from Sleep, the
INTOSC or postscaler clock sources can be selected
by setting IFRC2:IFRC0 prior to entering Sleep mode.
Adjustments to the internal oscillator block, using the
OSCTUNE register, also affect the period of the FSCM
by the same factor. This can usually be neglected, as
the clock frequency being monitored is generally much
higher than the sample clock frequency.
The FSCM will detect failures of the primary or second-
ary clock sources only. If the internal oscillator block
fails, no failure would be detected, nor would any action
be possible.
FIGURE 19-3:
FSCM BLOCK DIAGRAM
Clock Monitor
Latch (CM)
(edge-triggered)
Peripheral
Clock
S
Q
19.4.1
FSCM AND THE WATCHDOG TIMER
Both the FSCM and the WDT are clocked by the
INTRC oscillator. Since the WDT operates with a
separate divider and counter, disabling the WDT has
no effect on the operation of the INTRC oscillator when
the FSCM is enabled.
INTRC
Source
C
Q
÷ 64
(32 μs)
488 Hz
(2.048 ms)
As already noted, the clock source is switched to the
INTOSC clock when a clock failure is detected.
Depending on the frequency selected by the
IRCF2:IRCF0 bits, this may mean a substantial change
in the speed of code execution. If the WDT is enabled
with a small prescale value, a decrease in clock speed
allows a WDT time-out to occur and a subsequent
device Reset. For this reason, Fail-Safe Clock events
also reset the WDT and postscaler, allowing it to start
timing from when execution speed was changed and
decreasing the likelihood of an erroneous time-out.
Clock
Failure
Detected
Clock failure is tested for on the falling edge of the sam-
ple clock. If a sample clock falling edge occurs while
CM is still set, a clock failure has been detected
(Figure 19-4). This causes the following:
• the FSCM generates an oscillator fail interrupt by
setting bit, OSCFIF (PIR2<7>);
• the system clock source is switched to the internal
oscillator block (OSCCON is not updated to show
the current clock source – this is the Fail-Safe
condition); and
• the WDT is reset.
DS39605F-page 182
© 2007 Microchip Technology Inc.
PIC18F1220/1320
19.4.2
EXITING FAIL-SAFE OPERATION
19.4.3
FSCM INTERRUPTS IN POWER
MANAGED MODES
The Fail-Safe condition is terminated by either a device
Reset, or by entering a power managed mode. On
Reset, the controller starts the primary clock source
specified in Configuration Register 1H (with any
required start-up delays that are required for the
oscillator mode, such as OST or PLL timer). The
INTOSC multiplexer provides the system clock until the
primary clock source becomes ready (similar to a Two-
Speed Start-up). The clock system source is then
switched to the primary clock (indicated by the OSTS
bit in the OSCCON register becoming set). The Fail-
Safe Clock Monitor then resumes monitoring the
peripheral clock.
As previously mentioned, entering a power managed
mode clears the Fail-Safe condition. By entering a
power managed mode, the clock multiplexer selects
the clock source selected by the OSCCON register.
Fail-Safe monitoring of the power managed clock
source resumes in the power managed mode.
If an oscillator failure occurs during power managed
operation, the subsequent events depend on whether
or not the oscillator failure interrupt is enabled. If
enabled (OSCFIF = 1), code execution will be clocked
by the INTOSC multiplexer. An automatic transition
back to the failed clock source will not occur.
The primary clock source may never become ready
during start-up. In this case, operation is clocked by the
INTOSC multiplexer. The OSCCON register will remain
in its Reset state until a power managed mode is
entered.
If the interrupt is disabled, the device will not exit the
power managed mode on oscillator failure. Instead, the
device will continue to operate as before, but clocked
by the INTOSC multiplexer. While in Idle mode, subse-
quent interrupts will cause the CPU to begin executing
instructions while being clocked by the INTOSC multi-
plexer. The device will not transition to a different clock
source until the Fail-Safe condition is cleared.
Entering a power managed mode by loading the
OSCCON register and executing a SLEEP instruction
will clear the Fail-Safe condition. When the Fail-Safe
condition is cleared, the clock monitor will resume
monitoring the peripheral clock.
FIGURE 19-4:
FSCM TIMING DIAGRAM
Sample Clock
Oscillator
Failure
System
Clock
Output
CM Output
(Q)
Failure
Detected
OSCFIF
CM Test
CM Test
CM Test
Note:
The system clock is normally at a much higher frequency than the sample clock. The relative frequencies in
this example have been chosen for clarity.
© 2007 Microchip Technology Inc.
DS39605F-page 183
PIC18F1220/1320
19.4.4
POR OR WAKE FROM SLEEP
Note:
The same logic that prevents false oscilla-
tor failure interrupts on POR or wake from
Sleep will also prevent the detection of the
oscillator’s failure to start at all following
these events. This can be avoided by
monitoring the OSTS bit and using a
timing routine to determine if the oscillator
is taking too long to start. Even so, no
oscillator failure interrupt will be flagged.
The FSCM is designed to detect oscillator failure at any
point after the device has exited Power-on Reset
(POR) or Low-Power Sleep mode. When the primary
system clock is EC, RC or INTRC modes, monitoring
can begin immediately following these events.
For oscillator modes involving a crystal or resonator
(HS, HSPLL, LP or XT), the situation is somewhat dif-
ferent. Since the oscillator may require a start-up time
considerably longer than the FCSM sample clock time,
a false clock failure may be detected. To prevent this,
the internal oscillator block is automatically configured
as the system clock and functions until the primary
clock is stable (the OST and PLL timers have timed
out). This is identical to Two-Speed Start-up mode.
Once the primary clock is stable, the INTRC returns to
its role as the FSCM source
As noted in Section 19.3.1 “Special Considerations
for Using Two-Speed Start-up”, it is also possible to
select another clock configuration and enter an alter-
nate power managed mode while waiting for the
primary system clock to become stable. When the new
powered managed mode is selected, the primary clock
is disabled.
DS39605F-page 184
© 2007 Microchip Technology Inc.
PIC18F1220/1320
Each of the three blocks has three protection bits
associated with them. They are:
19.5 Program Verification and
Code Protection
• Code-Protect bit (CPn)
The overall structure of the code protection on the
PIC18 Flash devices differs significantly from other PIC
devices.
• Write-Protect bit (WRTn)
• External Block Table Read bit (EBTRn)
Figure 19-5 shows the program memory organization
for 4 and 8-Kbyte devices and the specific code protec-
tion bit associated with each block. The actual locations
of the bits are summarized in Table 19-3.
The user program memory is divided into three blocks.
One of these is a boot block of 512 bytes. The remain-
der of the memory is divided into two blocks on binary
boundaries.
FIGURE 19-5:
CODE-PROTECTED PROGRAM MEMORY FOR PIC18F1220/1320
MEMORY SIZE/DEVICE
Block Code
Protection
Controlled By:
Block Code
Protection
Controlled By:
Address
Range
4 Kbytes
8 Kbytes
Address
Range
(PIC18F1220) (PIC18F1320)
000000h
0001FFh
000000h
0001FFh
CPB, WRTB, EBTRB
CP0, WRT0, EBTR0
Boot Block
Block 0
Boot Block
Block 0
CPB, WRTB, EBTRB
CP0, WRT0, EBTR0
000200h
000200h
0007FFh
000800h
CP1, WRT1, EBTR1
Block 1
000FFFh
001000h
000FFFh
001000h
Block 1
CP1, WRT1, EBTR1
(Unimplemented
Memory Space)
Unimplemented
001FFFh
002000h
Read ‘0’s
Unimplemented
(Unimplemented
Memory Space)
Read ‘0’s
1FFFFFh
1FFFFFh
TABLE 19-3: SUMMARY OF CODE PROTECTION REGISTERS
File Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
300008h
CONFIG5L
CONFIG5H
CONFIG6L
—
CPD
—
—
CPB
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
CP1
—
CP0
—
300009h
30000Ah
30000Bh
30000Ch
30000Dh
—
WRT1
—
WRT0
—
CONFIG6H WRTD
WRTB
—
WRTC
—
CONFIG7L
CONFIG7H
—
—
EBTR1
—
EBTR0
—
EBTRB
—
Legend: Shaded cells are unimplemented.
© 2007 Microchip Technology Inc.
DS39605F-page 185
PIC18F1220/1320
19.5.1
PROGRAM MEMORY
CODE PROTECTION
Note:
Code protection bits may only be written to
a ‘0’ from a ‘1’ state. It is not possible to
write a ‘1’ to a bit in the ‘0’ state. Code pro-
tection bits are only set to ‘1’ by a full Chip
Erase or Block Erase function. The full
Chip Erase and Block Erase functions can
only be initiated via ICSP or an external
programmer.
The program memory may be read to, or written from,
any location using the table read and table write
instructions. The device ID may be read with table
reads. The configuration registers may be read and
written with the table read and table write instructions.
In normal execution mode, the CPn bits have no direct
effect. CPn bits inhibit external reads and writes. A
block of user memory may be protected from table
writes if the WRTn configuration bit is ‘0’. The EBTRn
bits control table reads. For a block of user memory
with the EBTRn bit set to ‘0’, a table read instruction
that executes from within that block is allowed to read.
A table read instruction that executes from a location
outside of that block is not allowed to read and will
result in reading ‘0’s. Figures 19-6 through 19-8
illustrate table write and table read protection.
FIGURE 19-6:
TABLE WRITE (WRTn) DISALLOWED: PIC18F1320
Register Values
Program Memory
Configuration Bit Settings
000000h
WRTB, EBTRB = 11
0001FFh
000200h
TBLPTR = 0002FFh
WRT0, EBTR0 = 01
PC = 0007FEh
TBLWT *
TBLWT *
000FFFh
001000h
PC = 0017FEh
WRT1, EBTR1 = 11
001FFFh
Results: All table writes disabled to Blockn whenever WRTn = 0.
DS39605F-page 186
© 2007 Microchip Technology Inc.
PIC18F1220/1320
FIGURE 19-7:
EXTERNAL BLOCK TABLE READ (EBTRn) DISALLOWED: PIC18F1320
Register Values
Program Memory
Configuration Bit Settings
000000h
WRTB, EBTRB = 11
0001FFh
000200h
TBLPTR = 0002FFh
WRT0, EBTR0 = 10
000FFFh
001000h
PC = 001FFEh
TBLRD *
WRT1, EBTR1 = 11
001FFFh
Results: All table reads from external blocks to Blockn are disabled whenever EBTRn = 0.
TABLAT register returns a value of ‘0’.
FIGURE 19-8:
EXTERNAL BLOCK TABLE READ (EBTRn) ALLOWED: PIC18F1320
Register Values
Program Memory
Configuration Bit Settings
000000h
WRTB, EBTRB = 11
0001FFh
000200h
TBLPTR = 0002FFh
PC = 0007FEh
WRT0, EBTR0 = 10
TBLRD *
000FFFh
001000h
WRT1, EBTR1 = 11
001FFFh
Results: Table reads permitted within Blockn, even when EBTRBn = 0.
TABLAT register returns the value of the data at the location TBLPTR.
© 2007 Microchip Technology Inc.
DS39605F-page 187
PIC18F1220/1320
19.5.2
DATA EEPROM
CODE PROTECTION
TABLE 19-4: ICSP/ICD CONNECTIONS
Signal
Pin
RB7/PGD/T1OSI/ Shared with T1OSC – protect
P1D/KBI3 crystal
Notes
The entire data EEPROM is protected from external
reads and writes by two bits: CPD and WRTD. CPD
inhibits external reads and writes of data EEPROM.
WRTD inhibits external writes to data EEPROM. The
CPU can continue to read and write data EEPROM,
regardless of the protection bit settings.
PGD
PGC
RB6/PGC/T1OSO/ Shared with T1OSC – protect
T13CKI/P1C/KBI2 crystal
MCLR
VDD
MCLR/VPP/RA5
VDD
VSS
19.5.3
CONFIGURATION REGISTER
PROTECTION
VSS
PGM
RB5/PGM/KBI1
Optional – pull RB5 low is
LVP enabled
The configuration registers can be write-protected. The
WRTC bit controls protection of the configuration
registers. In normal execution mode, the WRTC bit is
readable only. WRTC can only be written via ICSP or
an external programmer.
19.8 In-Circuit Debugger
When the DEBUG bit in configuration register,
CONFIG4L, is programmed to a ‘0’, the In-Circuit
Debugger functionality is enabled. This function allows
simple debugging functions when used with MPLAB®
IDE. When the microcontroller has this feature
enabled, some resources are not available for general
use. Table 19-5 shows which resources are required by
the background debugger.
19.6 ID Locations
Eight memory locations (200000h-200007h) are
designated as ID locations, where the user can store
checksum or other code identification numbers. These
locations are both readable and writable during normal
execution through the TBLRDand TBLWTinstructions,
or during program/verify. The ID locations can be read
when the device is code-protected.
TABLE 19-5: DEBUGGER RESOURCES
I/O pins:
RB6, RB7
Stack:
2 levels
512 bytes
10 bytes
19.7
In-Circuit Serial Programming
Program Memory:
Data Memory:
PIC18F1220/1320 microcontrollers can be serially
programmed while in the end application circuit. This is
simply done with two lines for clock and data and three
other lines for power, ground and the programming
voltage. This allows customers to manufacture boards
with unprogrammed devices and then program the
microcontroller just before shipping the product. This
also allows the most recent firmware or a custom
firmware to be programmed (see Table 19-4).
To use the In-Circuit Debugger function of the
microcontroller, the design must implement In-Circuit
Serial Programming connections to MCLR/VPP, VDD,
VSS, RB7 and RB6. This will interface to the In-Circuit
Debugger module available from Microchip, or one of the
third party development tool companies (see the note fol-
lowing Section 19.7 “In-Circuit Serial Programming”
for more information).
Note:
The Timer1 oscillator shares the T1OSI
and T1OSO pins with the PGD and PGC
pins used for programming and
debugging.
When using the Timer1 oscillator, In-Circuit
Serial Programming (ICSP) may not
function correctly (high voltage or low
voltage), or the In-Circuit Debugger (ICD)
may not communicate with the controller.
As a result of using either ICSP or ICD, the
Timer1 crystal may be damaged.
If ICSP or ICD operations are required, the
crystal should be disconnected from the
circuit (disconnect either lead), or installed
after programming. The oscillator loading
capacitors may remain in-circuit during
ICSP or ICD operation.
DS39605F-page 188
© 2007 Microchip Technology Inc.
PIC18F1220/1320
If Low-Voltage Programming mode will not be used, the
LVP bit can be cleared and RB5/PGM/KBI1 becomes
available as the digital I/O pin RB5. The LVP bit may be
set or cleared only when using standard high-voltage
programming (VIHH applied to the MCLR/VPP/RA5 pin).
Once LVP has been disabled, only the standard high-
voltage programming is available and must be used to
program the device.
19.9 Low-Voltage ICSP Programming
The LVP bit in configuration register, CONFIG4L,
enables Low-Voltage Programming (LVP). When LVP
is enabled, the microcontroller can be programmed
without requiring high voltage being applied to the
MCLR/VPP/RA5 pin, but the RB5/PGM/KBI1 pin is then
dedicated to controlling Program mode entry and is not
available as a general purpose I/O pin.
Memory that is not code-protected can be erased,
using either a Block Erase, or erased row by row, then
written at any specified VDD. If code-protected memory
is to be erased, a Block Erase is required. If a Block
Erase is to be performed when using Low-Voltage
Programming, the device must be supplied with VDD of
4.5V to 5.5V.
LVP is enabled in erased devices.
While programming using LVP, VDD is applied to the
MCLR/VPP/RA5 pin as in normal execution mode. To
enter Programming mode, VDD is applied to the PGM
pin.
Note 1: High-voltage programming is always
available, regardless of the state of the
LVP bit or the PGM pin, by applying VIHH
to the MCLR pin.
2: When Low-Voltage Programming is
enabled, the RB5 pin can no longer be
used as a general purpose I/O pin.
3: When LVP is enabled, externally pull the
PGM pin to VSS to allow normal program
execution.
© 2007 Microchip Technology Inc.
DS39605F-page 189
PIC18F1220/1320
NOTES:
DS39605F-page 190
© 2007 Microchip Technology Inc.
PIC18F1220/1320
The control instructions may use some of the following
operands:
20.0 INSTRUCTION SET SUMMARY
The PIC18 instruction set adds many enhancements to
the previous PIC instruction sets, while maintaining an
easy migration from these PIC instruction sets.
• A program memory address (specified by ‘n’)
• The mode of the CALLor RETURNinstructions
(specified by ‘s’)
Most instructions are a single program memory word
(16 bits), but there are three instructions that require
two program memory locations.
• The mode of the table read and table write
instructions (specified by ‘m’)
• No operand required
(specified by ‘—’)
Each single-word instruction is a 16-bit word divided
into an opcode, which specifies the instruction type and
one or more operands, which further specify the
operation of the instruction.
All instructions are a single word, except for three
double-word instructions. These three instructions
were made double-word instructions so that all the
required information is available in these 32 bits. In the
second word, the 4 MSbs are ‘1’s. If this second word
is executed as an instruction (by itself), it will execute
as a NOP.
The instruction set is highly orthogonal and is grouped
into four basic categories:
• Byte-oriented operations
• Bit-oriented operations
• Literal operations
All single-word instructions are executed in a single
instruction cycle, unless a conditional test is true, or the
program counter is changed as a result of the instruc-
tion. In these cases, the execution takes two instruction
cycles, with the additional instruction cycle(s) executed
as a NOP.
• Control operations
The PIC18 instruction set summary in Table 20-1 lists
byte-oriented, bit-oriented, literal and control
operations. Table 20-1 shows the opcode field
descriptions.
The double-word instructions execute in two instruction
cycles.
Most byte-oriented instructions have three operands:
1. The file register (specified by ‘f’)
One instruction cycle consists of four oscillator periods.
Thus, for an oscillator frequency of 4 MHz, the normal
instruction execution time is 1 μs. If a conditional test is
true, or the program counter is changed as a result of
an instruction, the instruction execution time is 2 μs.
Two-word branch instructions (if true) would take 3 μs.
2. The destination of the result
(specified by ‘d’)
3. The accessed memory
(specified by ‘a’)
The file register designator ‘f’ specifies which file
register is to be used by the instruction.
Figure 20-1 shows the general formats that the
instructions can have.
The destination designator ‘d’ specifies where the
result of the operation is to be placed. If ‘d’ is zero, the
result is placed in the WREG register. If ‘d’ is one, the
result is placed in the file register specified in the
instruction.
All examples use the format ‘nnh’ to represent a hexa-
decimal number, where ‘h’ signifies a hexadecimal
digit.
The Instruction Set Summary, shown in Table 20-1,
lists the instructions recognized by the Microchip
Assembler (MPASMTM). Section 20.2 “Instruction
Set” provides a description of each instruction.
All bit-oriented instructions have three operands:
1. The file register (specified by ‘f’)
2. The bit in the file register
(specified by ‘b’)
20.1 Read-Modify-Write Operations
3. The accessed memory
(specified by ‘a’)
Any instruction that specifies a file register as part of
the instruction performs a Read-Modify-Write (R-M-W)
operation. The register is read, the data is modified and
the result is stored according to either the instruction or
the destination designator ‘d’. A read operation is
performed on a register even if the instruction writes to
that register.
The bit field designator ‘b’ selects the number of the bit
affected by the operation, while the file register desig-
nator ‘f’ represents the number of the file in which the
bit is located.
The literal instructions may use some of the following
operands:
For example, a “BCF PORTB,1” instruction will read
PORTB, clear bit 1 of the data, then write the result
back to PORTB. The read operation would have the
unintended result that any condition that sets the RBIF
flag would be cleared. The R-M-W operation may also
copy the level of an input pin to its corresponding output
latch.
• A literal value to be loaded into a file register
(specified by ‘k’)
• The desired FSR register to load the literal value
into (specified by ‘f’)
• No operand required
(specified by ‘—’)
© 2007 Microchip Technology Inc.
DS39605F-page 191
PIC18F1220/1320
TABLE 20-1: OPCODE FIELD DESCRIPTIONS
Field
Description
a
RAM access bit
a = 0: RAM location in Access RAM (BSR register is ignored)
a = 1: RAM bank is specified by BSR register
bbb
BSR
d
Bit address within an 8-bit file register (0 to 7).
Bank Select Register. Used to select the current RAM bank.
Destination select bit
d = 0: store result in WREG
d = 1: store result in file register f
dest
f
Destination either the WREG register or the specified register file location.
8-bit register file address (0x00 to 0xFF).
fs
12-bit register file address (0x000 to 0xFFF). This is the source address.
12-bit register file address (0x000 to 0xFFF). This is the destination address.
Literal field, constant data or label (may be either an 8-bit, 12-bit or a 20-bit value).
Label name.
fd
k
label
mm
The mode of the TBLPTR register for the table read and table write instructions.
Only used with table read and table write instructions:
*
No change to register (such as TBLPTR with table reads and writes)
Post-Increment register (such as TBLPTR with table reads and writes)
Post-Decrement register (such as TBLPTR with table reads and writes)
Pre-Increment register (such as TBLPTR with table reads and writes)
*+
*-
+*
n
The relative address (2’s complement number) for relative branch instructions, or the direct address for
call/branch and return instructions.
PRODH
PRODL
s
Product of Multiply High Byte.
Product of Multiply Low Byte.
Fast Call/Return mode select bit
s = 0: do not update into/from shadow registers
s = 1: certain registers loaded into/from shadow registers (Fast mode)
u
Unused or unchanged.
WREG
x
Working register (accumulator).
Don’t care (‘0’ or ‘1’).
The assembler will generate code with x = 0. It is the recommended form of use for compatibility with all
Microchip software tools.
TBLPTR
21-bit Table Pointer (points to a program memory location).
8-bit Table Latch.
TABLAT
TOS
Top-of-Stack.
PC
Program Counter.
PCL
Program Counter Low Byte.
Program Counter High Byte.
Program Counter High Byte Latch.
Program Counter Upper Byte Latch.
Global Interrupt Enable bit.
Watchdog Timer.
PCH
PCLATH
PCLATU
GIE
WDT
TO
Time-out bit.
PD
Power-down bit.
C, DC, Z, OV, N
ALU Status bits: Carry, Digit Carry, Zero, Overflow, Negative.
Optional.
[
]
)
(
Contents.
→
< >
∈
Assigned to.
Register bit field.
In the set of.
italics
User defined term (font is Courier).
DS39605F-page 192
© 2007 Microchip Technology Inc.
PIC18F1220/1320
FIGURE 20-1:
GENERAL FORMAT FOR INSTRUCTIONS
Byte-oriented file register operations
Example Instruction
15
10
OPCODE
9
8
7
0
ADDWF MYREG, W, B
d
a
f (FILE #)
d = 0for result destination to be WREG register
d = 1for result destination to be file register (f)
a = 0to force Access Bank
a = 1for BSR to select bank
f = 8-bit file register address
Byte to Byte move operations (2-word)
15
12 11
0
0
OPCODE
f (Source FILE #)
MOVFF MYREG1, MYREG2
15
12 11
1111
f (Destination FILE #)
f = 12-bit file register address
Bit-oriented file register operations
15 12 11 9 8
OPCODE b (BIT #)
7
0
BSF MYREG, bit, B
a
f (FILE #)
b = 3-bit position of bit in file register (f)
a = 0to force Access Bank
a = 1for BSR to select bank
f = 8-bit file register address
Literal operations
15
8
7
0
MOVLW 0x7F
OPCODE
k (literal)
k = 8-bit immediate value
Control operations
CALL, GOTO and Branch operations
15
8 7
0
GOTO Label
OPCODE
12 11
n<7:0> (literal)
15
0
1111
n<19:8> (literal)
n = 20-bit immediate value
15
15
8
7
0
CALL MYFUNC
OPCODE
12 11
n<7:0> (literal)
S
0
n<19:8> (literal)
S = Fast bit
11 10
15
0
0
BRA MYFUNC
BC MYFUNC
OPCODE
n<10:0> (literal)
15
OPCODE
8 7
n<7:0> (literal)
© 2007 Microchip Technology Inc.
DS39605F-page 193
PIC18F1220/1320
TABLE 20-1: PIC18FXXXX INSTRUCTION SET
16-Bit Instruction Word
MSb LSb
Mnemonic,
Operands
Status
Affected
Description
Cycles
Notes
BYTE-ORIENTED FILE REGISTER OPERATIONS
ADDWF f, d, a Add WREG and f
ADDWFC f, d, a Add WREG and Carry bit to f
1
1
1
1
1
0010 01da ffff ffff C, DC, Z, OV, N 1, 2
0010 00da ffff ffff C, DC, Z, OV, N 1, 2
ANDWF
CLRF
COMF
f, d, a AND WREG with f
f, a Clear f
f, d, a Complement f
0001 01da ffff ffff Z, N
0110 101a ffff ffff Z
0001 11da ffff ffff Z, N
1,2
2
1, 2
4
CPFSEQ f, a
CPFSGT f, a
CPFSLT f, a
Compare f with WREG, skip =
Compare f with WREG, skip >
Compare f with WREG, skip <
1 (2 or 3) 0110 001a ffff ffff None
1 (2 or 3) 0110 010a ffff ffff None
1 (2 or 3) 0110 000a ffff ffff None
4
1, 2
DECF
f, d, a Decrement f
1
0000 01da ffff ffff C, DC, Z, OV, N 1, 2, 3, 4
DECFSZ f, d, a Decrement f, Skip if 0
DCFSNZ f, d, a Decrement f, Skip if Not 0
1 (2 or 3) 0010 11da ffff ffff None
1 (2 or 3) 0100 11da ffff ffff None
1, 2, 3, 4
1, 2
INCF
f, d, a Increment f
1
0010 10da ffff ffff C, DC, Z, OV, N 1, 2, 3, 4
INCFSZ
INFSNZ
IORWF
MOVF
f, d, a Increment f, Skip if 0
f, d, a Increment f, Skip if Not 0
f, d, a Inclusive OR WREG with f
f, d, a Move f
fs, fd Move fs (source) to 1st word
fd (destination) 2nd word
1 (2 or 3) 0011 11da ffff ffff None
1 (2 or 3) 0100 10da ffff ffff None
4
1, 2
1, 2
1
1
1
2
0001 00da ffff ffff Z, N
0101 00da ffff ffff Z, N
1100 ffff ffff ffff None
1111 ffff ffff ffff
MOVFF
MOVWF f, a
Move WREG to f
Multiply WREG with f
Negate f
1
1
1
1
1
1
1
1
1
0110 111a ffff ffff None
0000 001a ffff ffff None
0110 110a ffff ffff C, DC, Z, OV, N 1, 2
0011 01da ffff ffff C, Z, N
0100 01da ffff ffff Z, N
0011 00da ffff ffff C, Z, N
0100 00da ffff ffff Z, N
0110 100a ffff ffff None
MULWF
NEGF
RLCF
RLNCF
RRCF
RRNCF
SETF
f, a
f, a
f, d, a Rotate Left f through Carry
f, d, a Rotate Left f (No Carry)
f, d, a Rotate Right f through Carry
f, d, a Rotate Right f (No Carry)
1, 2
f, a
Set f
SUBFWB f, d, a Subtract f from WREG with
borrow
0101 01da ffff ffff C, DC, Z, OV, N 1, 2
SUBWF
f, d, a Subtract WREG from f
1
1
0101 11da ffff ffff C, DC, Z, OV, N
0101 10da ffff ffff C, DC, Z, OV, N 1, 2
SUBWFB f, d, a Subtract WREG from f with
borrow
SWAPF
TSTFSZ f, a
f, d, a Swap nibbles in f
Test f, skip if 0
1
0011 10da ffff ffff None
4
1, 2
1 (2 or 3) 0110 011a ffff ffff None
XORWF f, d, a Exclusive OR WREG with f
1
0001 10da ffff ffff Z, N
BIT-ORIENTED FILE REGISTER OPERATIONS
BCF
BSF
BTFSC
BTFSS
BTG
f, b, a Bit Clear f
f, b, a Bit Set f
f, b, a Bit Test f, Skip if Clear
f, b, a Bit Test f, Skip if Set
f, d, a Bit Toggle f
1
1
1001 bbba ffff ffff None
1000 bbba ffff ffff None
1, 2
1, 2
3, 4
3, 4
1, 2
1 (2 or 3) 1011 bbba ffff ffff None
1 (2 or 3) 1010 bbba ffff ffff None
1
0111 bbba ffff ffff None
Note 1: When a Port register is modified as a function of itself (e.g., MOVF PORTB, 1, 0), the value used will be that
value present on the pins themselves. For example, if the data latch is ‘1’ for a pin configured as input and is
driven low by an external device, the data will be written back with a ‘0’.
2: If this instruction is executed on the TMR0 register (and where applicable, d = 1), the prescaler will be cleared
if assigned.
3: If Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The second
cycle is executed as a NOP.
4: Some instructions are 2-word instructions. The second word of these instructions will be executed as a NOP,
unless the first word of the instruction retrieves the information embedded in these 16 bits. This ensures that all
program memory locations have a valid instruction.
5: If the table write starts the write cycle to internal memory, the write will continue until terminated.
DS39605F-page 194
© 2007 Microchip Technology Inc.
PIC18F1220/1320
TABLE 20-1: PIC18FXXXX INSTRUCTION SET (CONTINUED)
16-Bit Instruction Word
LSb
Mnemonic,
Operands
Status
Affected
Description
Cycles
Notes
MSb
CONTROL OPERATIONS
BC
BN
n
n
n
n
n
n
n
n
Branch if Carry
1 (2)
1 (2)
1 (2)
1 (2)
1 (2)
1 (2)
1 (2)
2
1110 0010 nnnn nnnn None
1110 0110 nnnn nnnn None
1110 0011 nnnn nnnn None
1110 0111 nnnn nnnn None
1110 0101 nnnn nnnn None
1110 0001 nnnn nnnn None
1110 0100 nnnn nnnn None
1101 0nnn nnnn nnnn None
1110 0000 nnnn nnnn None
1110 110s kkkk kkkk None
1111 kkkk kkkk kkkk
Branch if Negative
Branch if Not Carry
Branch if Not Negative
Branch if Not Overflow
Branch if Not Zero
Branch if Overflow
Branch Unconditionally
Branch if Zero
BNC
BNN
BNOV
BNZ
BOV
BRA
BZ
n
n, s
1 (2)
2
CALL
Call subroutine 1st word
2nd word
CLRWDT
DAW
GOTO
—
—
n
Clear Watchdog Timer
Decimal Adjust WREG
Go to address 1st word
2nd word
1
1
2
0000 0000 0000 0100 TO, PD
0000 0000 0000 0111 C
1110 1111 kkkk kkkk None
1111 kkkk kkkk kkkk
NOP
NOP
POP
PUSH
RCALL
RESET
RETFIE
—
—
—
—
n
No Operation
No Operation
1
1
1
1
2
1
2
0000 0000 0000 0000 None
1111 xxxx xxxx xxxx None
0000 0000 0000 0110 None
0000 0000 0000 0101 None
1101 1nnn nnnn nnnn None
0000 0000 1111 1111 All
0000 0000 0001 000s GIE/GIEH,
PEIE/GIEL
4
Pop top of return stack (TOS)
Push top of return stack (TOS)
Relative Call
Software device Reset
Return from interrupt enable
s
RETLW
RETURN
SLEEP
k
s
—
Return with literal in WREG
Return from Subroutine
Go into Standby mode
2
2
1
0000 1100 kkkk kkkk None
0000 0000 0001 001s None
0000 0000 0000 0011 TO, PD
Note 1: When a Port register is modified as a function of itself (e.g., MOVF PORTB, 1, 0), the value used will be that
value present on the pins themselves. For example, if the data latch is ‘1’ for a pin configured as input and is
driven low by an external device, the data will be written back with a ‘0’.
2: If this instruction is executed on the TMR0 register (and where applicable, d = 1), the prescaler will be cleared
if assigned.
3: If Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The second
cycle is executed as a NOP.
4: Some instructions are 2-word instructions. The second word of these instructions will be executed as a NOP,
unless the first word of the instruction retrieves the information embedded in these 16 bits. This ensures that all
program memory locations have a valid instruction.
5: If the table write starts the write cycle to internal memory, the write will continue until terminated.
© 2007 Microchip Technology Inc.
DS39605F-page 195
PIC18F1220/1320
TABLE 20-1: PIC18FXXXX INSTRUCTION SET (CONTINUED)
16-Bit Instruction Word
Mnemonic,
Operands
Status
Affected
Description
Cycles
Notes
MSb
LSb
LITERAL OPERATIONS
ADDLW
ANDLW
IORLW
LFSR
k
k
k
f, k
Add literal and WREG
AND literal with WREG
Inclusive OR literal with WREG
Move literal (12-bit) 2nd word
1
0000 1111 kkkk
0000 1011 kkkk
0000 1001 kkkk
1110 1110 00ff
1111 0000 kkkk
0000 0001 0000
0000 1110 kkkk
0000 1101 kkkk
0000 1100 kkkk
0000 1000 kkkk
0000 1010 kkkk
kkkk C, DC, Z, OV, N
kkkk Z, N
kkkk Z, N
kkkk None
kkkk
kkkk None
kkkk None
kkkk None
kkkk None
kkkk C, DC, Z, OV, N
kkkk Z, N
1
1
2
to FSRx
1st word
MOVLB
MOVLW
MULLW
RETLW
SUBLW
XORLW
k
k
k
k
k
k
Move literal to BSR<3:0>
Move literal to WREG
Multiply literal with WREG
Return with literal in WREG
Subtract WREG from literal
1
1
1
2
1
Exclusive OR literal with WREG 1
DATA MEMORY ↔ PROGRAM MEMORY OPERATIONS
TBLRD*
Table read
2
0000 0000 0000
0000 0000 0000
0000 0000 0000
0000 0000 0000
0000 0000 0000
0000 0000 0000
0000 0000 0000
0000 0000 0000
1000 None
1001 None
1010 None
1011 None
1100 None
1101 None
1110 None
1111 None
TBLRD*+
TBLRD*-
TBLRD+*
TBLWT*
TBLWT*+
TBLWT*-
TBLWT+*
Table read with post-increment
Table read with post-decrement
Table read with pre-increment
Table write
Table write with post-increment
Table write with post-decrement
Table write with pre-increment
2 (5)
Note 1: When a Port register is modified as a function of itself (e.g., MOVF PORTB, 1, 0), the value used will be that
value present on the pins themselves. For example, if the data latch is ‘1’ for a pin configured as input and is
driven low by an external device, the data will be written back with a ‘0’.
2: If this instruction is executed on the TMR0 register (and where applicable, d = 1), the prescaler will be cleared
if assigned.
3: If Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The second
cycle is executed as a NOP.
4: Some instructions are 2-word instructions. The second word of these instructions will be executed as a NOP,
unless the first word of the instruction retrieves the information embedded in these 16 bits. This ensures that all
program memory locations have a valid instruction.
5: If the table write starts the write cycle to internal memory, the write will continue until terminated.
DS39605F-page 196
© 2007 Microchip Technology Inc.
PIC18F1220/1320
20.2 Instruction Set
ADDLW
ADD literal to W
ADDWF
ADD W to f
Syntax:
[ label ] ADDLW
0 ≤ k ≤ 255
k
Syntax:
[ label ] ADDWF
f [,d [,a]]
Operands:
Operation:
Status Affected:
Encoding:
Operands:
0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
(W) + k → W
N, OV, C, DC, Z
Operation:
(W) + (f) → dest
0000
1111
kkkk
kkkk
Status Affected:
Encoding:
N, OV, C, DC, Z
Description:
The contents of W are added to the
8-bit literal ‘k’ and the result is
placed in W.
0010
01da
ffff
ffff
Description:
Add W to register ‘f’. If ‘d’ is ‘0’, the
result is stored in W. If ‘d’ is ‘1’, the
result is stored back in register ‘f’
(default). If ‘a’ is ‘0’, the Access
Bank will be selected. If ‘a’ is ‘1’,
the BSR is used.
Words:
Cycles:
1
1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
literal ‘k’
Process
Data
Write to W
Words:
Cycles:
1
1
Q Cycle Activity:
Q1
ADDLW
0x15
Example:
Q2
Q3
Q4
Before Instruction
Decode
Read
register ‘f’
Process
Data
Write to
destination
W
=
0x10
After Instruction
W
=
0x25
ADDWF
REG, W
Example:
Before Instruction
W
REG
=
=
0x17
0xC2
After Instruction
W
REG
=
=
0xD9
0xC2
© 2007 Microchip Technology Inc.
DS39605F-page 197
PIC18F1220/1320
ADDWFC
ADD W and Carry bit to f
ANDLW
AND literal with W
Syntax:
[ label ] ADDWFC
f [,d [,a]]
Syntax:
[ label ] ANDLW
0 ≤ k ≤ 255
k
Operands:
0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
Operands:
Operation:
Status Affected:
Encoding:
(W) .AND. k → W
N, Z
Operation:
(W) + (f) + (C) → dest
0000
1011
kkkk
kkkk
Status Affected:
Encoding:
N, OV, C, DC, Z
Description:
The contents of W are AND’ed with
the 8-bit literal ‘k’. The result is
placed in W.
0010
00da
ffff
ffff
Description:
Add W, the Carry flag and data
memory location ‘f’. If ‘d’ is ‘0’, the
result is placed in W. If ‘d’ is ‘1’, the
result is placed in data memory
location ‘f’. If ‘a’ is ‘0’, the Access
Bank will be selected. If ‘a’ is ‘1’, the
BSR will not be overridden.
Words:
Cycles:
1
1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read literal
‘k’
Process
Data
Write to W
Words:
Cycles:
1
1
ANDLW
0x5F
Example:
Q Cycle Activity:
Q1
Before Instruction
Q2
Q3
Q4
W
=
0xA3
0x03
Decode
Read
register ‘f’
Process
Data
Write to
destination
After Instruction
W
=
ADDWFC
REG, W
Example:
Before Instruction
Carry bit =
1
REG
W
=
0x02
0x4D
=
After Instruction
Carry bit =
0
0x02
0x50
REG
W
=
=
DS39605F-page 198
© 2007 Microchip Technology Inc.
PIC18F1220/1320
ANDWF
AND W with f
BC
Branch if Carry
Syntax:
[ label ] ANDWF
f [,d [,a]]
Syntax:
[ label ] BC
n
Operands:
0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
Operands:
Operation:
-128 ≤ n ≤ 127
if Carry bit is ‘1’
(PC) + 2 + 2n → PC
Operation:
(W) .AND. (f) → dest
Status Affected:
Encoding:
None
Status Affected:
Encoding:
N, Z
1110
0010
nnnn
nnnn
0001
01da
ffff
ffff
Description:
If the Carry bit is ‘1’, then the
Description:
The contents of W are AND’ed with
register ‘f’. If ‘d’ is ‘0’, the result is
stored in W. If ‘d’ is ‘1’, the result is
stored back in register ‘f’ (default).
If ‘a’ is ‘0’, the Access Bank will be
selected. If ‘a’ is ‘1’, the BSR will
not be overridden (default).
program will branch.
The 2’s complement number ‘2n’ is
added to the PC. Since the PC will
have incremented to fetch the next
instruction, the new address will be
PC + 2 + 2n. This instruction is then
a two-cycle instruction.
Words:
Cycles:
1
1
Words:
Cycles:
1
1(2)
Q Cycle Activity:
Q1
Q Cycle Activity:
If Jump:
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Decode
Read
register ‘f’
Process
Data
Write to
destination
Decode
Read literal
‘n’
Process
Data
Write to PC
No
operation
No
operation
No
operation
No
operation
ANDWF
REG, W
Example:
Before Instruction
If No Jump:
Q1
W
REG
=
=
0x17
0xC2
Q2
Q3
Q4
Decode
Read literal
‘n’
Process
Data
No
operation
After Instruction
W
REG
=
=
0x02
0xC2
HERE
BC JUMP
Example:
Before Instruction
PC
=
address (HERE)
After Instruction
If Carry
=
=
=
=
1;
PC
address (JUMP)
If Carry
PC
0;
address (HERE + 2)
© 2007 Microchip Technology Inc.
DS39605F-page 199
PIC18F1220/1320
BCF
Bit Clear f
BN
Branch if Negative
[ label ] BN
Syntax:
[ label ] BCF f,b[,a]
Syntax:
n
Operands:
0 ≤ f ≤ 255
0 ≤ b ≤ 7
a ∈ [0,1]
Operands:
Operation:
-128 ≤ n ≤ 127
if Negative bit is ‘1’
(PC) + 2 + 2n → PC
Operation:
0 → f<b>
Status Affected:
Encoding:
None
Status Affected:
Encoding:
None
1110
0110
nnnn
nnnn
1001
bbba
ffff
ffff
Description:
If the Negative bit is ‘1’, then the
program will branch.
Description:
Bit ‘b’ in register ‘f’ is cleared. If ‘a’
is ‘0’, the Access Bank will be
selected, overriding the BSR value.
If ‘a’ = 1, then the bank will be
selected as per the BSR value
(default).
The 2’s complement number ‘2n’ is
added to the PC. Since the PC will
have incremented to fetch the next
instruction, the new address will be
PC + 2 + 2n. This instruction is then
a two-cycle instruction.
Words:
Cycles:
1
1
Words:
Cycles:
1
1(2)
Q Cycle Activity:
Q1
Q Cycle Activity:
If Jump:
Q2
Q3
Q4
Decode
Read
register ‘f’
Process
Data
Write
register ‘f’
Q1
Q2
Q3
Q4
Decode
Read literal
‘n’
Process
Data
Write to PC
BCF
FLAG_REG, 7
Example:
No
operation
No
operation
No
operation
No
operation
Before Instruction
FLAG_REG
=
=
0xC7
0x47
If No Jump:
Q1
After Instruction
FLAG_REG
Q2
Q3
Q4
Decode
Read literal
‘n’
Process
Data
No
operation
HERE
BN Jump
Example:
Before Instruction
PC
=
address (HERE)
After Instruction
If Negative
=
=
=
=
1;
PC
address (Jump)
If Negative
PC
0;
address (HERE + 2)
DS39605F-page 200
© 2007 Microchip Technology Inc.
PIC18F1220/1320
BNC
Branch if Not Carry
BNN
Branch if Not Negative
Syntax:
[ label ] BNC
-128 ≤ n ≤ 127
if Carry bit is ‘0’
n
Syntax:
[ label ] BNN
-128 ≤ n ≤ 127
n
Operands:
Operation:
Operands:
Operation:
if Negative bit is ‘0’
(PC) + 2 + 2n → PC
(PC) + 2 + 2n → PC
Status Affected:
Encoding:
None
Status Affected:
Encoding:
None
1110
0011
nnnn
nnnn
1110
0111
nnnn
nnnn
Description:
If the Carry bit is ‘0’, then the
program will branch.
Description:
If the Negative bit is ‘0’, then the
program will branch.
The 2’s complement number ‘2n’ is
added to the PC. Since the PC will
have incremented to fetch the next
instruction, the new address will be
PC + 2 + 2n. This instruction is then
a two-cycle instruction.
The 2’s complement number ‘2n’ is
added to the PC. Since the PC will
have incremented to fetch the next
instruction, the new address will be
PC + 2 + 2n. This instruction is then
a two-cycle instruction.
Words:
Cycles:
1
Words:
Cycles:
1
1(2)
1(2)
Q Cycle Activity:
If Jump:
Q Cycle Activity:
If Jump:
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Decode
Read literal
‘n’
Process
Data
Write to PC
Decode
Read literal
‘n’
Process
Data
Write to PC
No
No
No
No
No
No
No
No
operation
operation
operation
operation
operation
operation
operation
operation
If No Jump:
Q1
If No Jump:
Q1
Q2
Q3
Q4
Q2
Q3
Q4
Decode
Read literal
‘n’
Process
Data
No
operation
Decode
Read literal
‘n’
Process
Data
No
operation
HERE
BNC Jump
HERE
BNN Jump
Example:
Example:
Before Instruction
Before Instruction
PC
=
address (HERE)
PC
=
address (HERE)
After Instruction
After Instruction
If Carry
=
=
=
=
0;
If Negative
=
=
=
=
0;
PC
address (Jump)
PC
address (Jump)
If Carry
PC
1;
If Negative
PC
1;
address (HERE + 2)
address (HERE + 2)
© 2007 Microchip Technology Inc.
DS39605F-page 201
PIC18F1220/1320
BNOV
Branch if Not Overflow
BNZ
Branch if Not Zero
Syntax:
[ label ] BNOV
-128 ≤ n ≤ 127
n
Syntax:
[ label ] BNZ
-128 ≤ n ≤ 127
if Zero bit is ‘0’
n
Operands:
Operation:
Operands:
Operation:
if Overflow bit is ‘0’
(PC) + 2 + 2n → PC
(PC) + 2 + 2n → PC
Status Affected:
Encoding:
None
Status Affected:
Encoding:
None
1110
0101
nnnn
nnnn
1110
0001
nnnn
nnnn
Description:
If the Overflow bit is ‘0’, then the
program will branch.
Description:
If the Zero bit is ‘0’, then the
program will branch.
The 2’s complement number ‘2n’ is
added to the PC. Since the PC will
have incremented to fetch the next
instruction, the new address will be
PC + 2 + 2n. This instruction is then
a two-cycle instruction.
The 2’s complement number ‘2n’ is
added to the PC. Since the PC will
have incremented to fetch the next
instruction, the new address will be
PC + 2 + 2n. This instruction is then
a two-cycle instruction.
Words:
Cycles:
1
Words:
Cycles:
1
1(2)
1(2)
Q Cycle Activity:
If Jump:
Q Cycle Activity:
If Jump:
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Decode
Read literal
‘n’
Process
Data
Write to PC
Decode
Read literal
‘n’
Process
Data
Write to PC
No
No
No
No
No
No
No
No
operation
operation
operation
operation
operation
operation
operation
operation
If No Jump:
Q1
If No Jump:
Q1
Q2
Q3
Q4
Q2
Q3
Q4
Decode
Read literal
‘n’
Process
Data
No
operation
Decode
Read literal
‘n’
Process
Data
No
operation
HERE
BNOV Jump
HERE
BNZ Jump
Example:
Example:
Before Instruction
Before Instruction
PC
=
address (HERE)
PC
=
address (HERE)
After Instruction
After Instruction
If Overflow
=
=
=
=
0;
If Zero
=
=
=
=
0;
PC
address (Jump)
PC
address (Jump)
If Overflow
PC
1;
If Zero
PC
1;
address (HERE + 2)
address (HERE + 2)
DS39605F-page 202
© 2007 Microchip Technology Inc.
PIC18F1220/1320
BRA
Unconditional Branch
[ label ] BRA
BSF
Bit Set f
Syntax:
n
Syntax:
[ label ] BSF f,b[,a]
Operands:
Operation:
Status Affected:
Encoding:
-1024 ≤ n ≤ 1023
(PC) + 2 + 2n → PC
None
Operands:
0 ≤ f ≤ 255
0 ≤ b ≤ 7
a ∈ [0,1]
Operation:
1 → f<b>
None
1101
0nnn
nnnn
nnnn
Status Affected:
Encoding:
Description:
Add the 2’s complement number
‘2n’ to the PC. Since the PC will
have incremented to fetch the next
instruction, the new address will be
PC + 2 + 2n. This instruction is a
two-cycle instruction.
1000
bbba
ffff
ffff
Description:
Bit ‘b’ in register ‘f’ is set. If ‘a’ is ‘0’,
the Access Bank will be selected,
overriding the BSR value. If ‘a’ = 1,
then the bank will be selected as
per the BSR value.
Words:
Cycles:
1
2
Words:
Cycles:
1
1
Q Cycle Activity:
Q1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Q2
Q3
Q4
Decode
Read literal
‘n’
Process
Data
Write to PC
Decode
Read
register ‘f’
Process
Data
Write
register ‘f’
No
No
No
No
operation
operation
operation
operation
BSF
FLAG_REG, 7
Example:
Before Instruction
HERE
BRA Jump
Example:
FLAG_REG
=
=
0x0A
0x8A
Before Instruction
After Instruction
FLAG_REG
PC
=
=
address (HERE)
address (Jump)
After Instruction
PC
© 2007 Microchip Technology Inc.
DS39605F-page 203
PIC18F1220/1320
BTFSC
Bit Test File, Skip if Clear
BTFSS
Bit Test File, Skip if Set
Syntax:
[ label ] BTFSC f,b[,a]
Syntax:
[ label ] BTFSS f,b[,a]
Operands:
0 ≤ f ≤ 255
0 ≤ b ≤ 7
a ∈ [0,1]
Operands:
0 ≤ f ≤ 255
0 ≤ b < 7
a ∈ [0,1]
Operation:
skip if (f<b>) = 0
Operation:
skip if (f<b>) = 1
Status Affected:
Encoding:
None
Status Affected:
Encoding:
None
1011
bbba
ffff
ffff
1010
bbba
ffff
ffff
Description:
If bit ‘b’ in register ‘f’ is ‘0’, then the
next instruction is skipped.
Description:
If bit ‘b’ in register ‘f’ is ‘1’, then the
next instruction is skipped.
If bit ‘b’ is ‘0’, then the next
If bit ‘b’ is ‘1’, then the next
instruction fetched during the current
instruction execution is discarded
and a NOPis executed instead,
making this a two-cycle instruction. If
‘a’ is ‘0’, the Access Bank will be
selected, overriding the BSR value. If
‘a’ = 1, then the bank will be selected
as per the BSR value (default).
instruction fetched during the current
instruction execution is discarded
and a NOPis executed instead,
making this a two-cycle instruction. If
‘a’ is ‘0’, the Access Bank will be
selected, overriding the BSR value. If
‘a’ = 1, then the bank will be selected
as per the BSR value (default).
Words:
Cycles:
1
Words:
Cycles:
1
1(2)
1(2)
Note: 3 cycles if skip and followed
by a 2-word instruction.
Note: 3 cycles if skip and followed
by a 2-word instruction.
Q Cycle Activity:
Q1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Q2
Q3
Q4
Decode
Read
register ‘f’
Process
Data
No
operation
Decode
Read
register ‘f’
Process
Data
No
operation
If skip:
Q1
If skip:
Q1
Q2
Q3
Q4
Q2
Q3
Q4
No
No
No
No
No
No
No
No
operation
operation
operation
operation
operation
operation
operation
operation
If skip and followed by 2-word instruction:
If skip and followed by 2-word instruction:
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
No
No
No
No
No
No
No
No
operation
operation
operation
operation
operation
operation
operation
operation
No
No
No
No
No
No
No
No
operation
operation
operation
operation
operation
operation
operation
operation
HERE
FALSE
TRUE
BTFSC
:
:
FLAG, 1
HERE
FALSE
TRUE
BTFSS
:
:
FLAG, 1
Example:
Example:
Before Instruction
PC
Before Instruction
PC
=
address (HERE)
=
address (HERE)
After Instruction
After Instruction
If FLAG<1>
=
=
=
=
0;
If FLAG<1>
=
=
=
=
0;
PC
address (TRUE)
1;
PC
address (FALSE)
1;
If FLAG<1>
PC
If FLAG<1>
PC
address (FALSE)
address (TRUE)
DS39605F-page 204
© 2007 Microchip Technology Inc.
PIC18F1220/1320
BTG
Bit Toggle f
BOV
Branch if Overflow
Syntax:
[ label ] BTG f,b[,a]
Syntax:
[ label ] BOV
-128 ≤ n ≤ 127
n
Operands:
0 ≤ f ≤ 255
0 ≤ b < 7
a ∈ [0,1]
Operands:
Operation:
if Overflow bit is ‘1’
(PC) + 2 + 2n → PC
Operation:
(f<b>) → f<b>
Status Affected:
Encoding:
None
Status Affected:
Encoding:
None
1110
0100
nnnn
nnnn
0111
bbba
ffff
ffff
Description:
If the Overflow bit is ‘1’, then the
program will branch.
Description:
Bit ‘b’ in data memory location ‘f’ is
inverted. If ‘a’ is ‘0’, the Access Bank
will be selected, overriding the BSR
value. If ‘a’ = 1, then the bank will be
selected as per the BSR value
(default).
The 2’s complement number ‘2n’ is
added to the PC. Since the PC will
have incremented to fetch the next
instruction, the new address will be
PC + 2 + 2n. This instruction is then
a two-cycle instruction.
Words:
Cycles:
1
1
Words:
Cycles:
1
1(2)
Q Cycle Activity:
Q1
Q Cycle Activity:
If Jump:
Q2
Q3
Q4
Decode
Read
register ‘f’
Process
Data
Write
Q1
Q2
Q3
Q4
register ‘f’
Decode
Read literal
‘n’
Process
Data
Write to PC
BTG
PORTB,
4
Example:
No
operation
No
operation
No
operation
No
operation
Before Instruction:
PORTB
=
0111 0101 [0x75]
If No Jump:
Q1
After Instruction:
Q2
Q3
Q4
PORTB
=
0110 0101 [0x65]
Decode
Read literal
‘n’
Process
Data
No
operation
HERE
BOV JUMP
Example:
Before Instruction
PC
=
address (HERE)
After Instruction
If Overflow
=
=
=
=
1;
PC
address (JUMP)
If Overflow
PC
0;
address (HERE + 2)
© 2007 Microchip Technology Inc.
DS39605F-page 205
PIC18F1220/1320
BZ
Branch if Zero
[ label ] BZ
CALL
Subroutine Call
Syntax:
n
Syntax:
[ label ] CALL k [,s]
Operands:
Operation:
-128 ≤ n ≤ 127
Operands:
0 ≤ k ≤ 1048575
s ∈ [0,1]
if Zero bit is ‘1’
(PC) + 2 + 2n → PC
Operation:
(PC) + 4 → TOS,
k → PC<20:1>,
if s = 1
Status Affected:
Encoding:
None
1110
0000
nnnn
nnnn
(W) → WS,
(Status) → STATUSS,
(BSR) → BSRS
Description:
If the Zero bit is ‘1’, then the
program will branch.
The 2’s complement number ‘2n’ is
added to the PC. Since the PC will
have incremented to fetch the next
instruction, the new address will be
PC + 2 + 2n. This instruction is then
a two-cycle instruction.
Status Affected:
None
Encoding:
1st word (k<7:0>)
2nd word(k<19:8>)
1110
1111
110s
k kkk
kkkk
kkkk
7
0
8
k
kkk kkkk
19
Description:
Subroutine call of entire 2-Mbyte
memory range. First, return
address (PC + 4) is pushed onto
the return stack. If ‘s’ = 1, the W,
Words:
Cycles:
1
1(2)
Status and BSR registers are also
pushed into their respective
Q Cycle Activity:
If Jump:
shadow registers, WS, STATUSS
and BSRS. If ‘s’ = 0, no update
occurs (default). Then, the 20-bit
value ‘k’ is loaded into PC<20:1>.
CALLis a two-cycle instruction.
Q1
Q2
Q3
Q4
Decode
Read literal
‘n’
Process
Data
Write to PC
No
operation
No
operation
No
operation
No
operation
Words:
Cycles:
2
2
If No Jump:
Q1
Q2
Q3
Q4
Decode
Read literal
‘n’
Process
Data
No
operation
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read literal Push PC to Read literal
HERE
BZ Jump
Example:
‘k’<7:0>,
stack
‘k’<19:8>,
Write to PC
Before Instruction
PC
=
address (HERE)
No
No
No
No
operation
operation
operation
operation
After Instruction
If Zero
=
=
=
=
1;
PC
address (Jump)
HERE
CALL THERE, FAST
Example:
If Zero
PC
0;
address (HERE + 2)
Before Instruction
PC
=
address (HERE)
After Instruction
PC
=
=
=
=
address (THERE)
TOS
WS
address (HERE + 4)
W
BSR
BSRS
STATUSS = Status
DS39605F-page 206
© 2007 Microchip Technology Inc.
PIC18F1220/1320
CLRF
Clear f
CLRWDT
Clear Watchdog Timer
Syntax:
[ label ] CLRF f [,a]
Syntax:
[ label ] CLRWDT
Operands:
0 ≤ f ≤ 255
a ∈ [0,1]
Operands:
Operation:
None
000h → WDT,
000h → WDT postscaler,
1 → TO,
Operation:
000h → f
1 → Z
1 → PD
Status Affected:
Encoding:
Z
Status Affected:
Encoding:
TO, PD
0110
101a
ffff
ffff
0000
0000
0000
0100
Description:
Clears the contents of the specified
register. If ‘a’ is ‘0’, the Access
Bank will be selected, overriding
the BSR value. If ‘a’ = 1, then the
bank will be selected as per the
BSR value (default).
Description:
CLRWDTinstruction resets the
Watchdog Timer. It also resets the
postscaler of the WDT. Status bits,
TO and PD, are set.
Words:
Cycles:
1
1
Words:
Cycles:
1
1
Q Cycle Activity:
Q1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Q2
Q3
Q4
Decode
No
operation
Process
Data
No
operation
Decode
Read
register ‘f’
Process
Data
Write
register ‘f’
CLRWDT
Example:
CLRF
FLAG_REG
Example:
Before Instruction
WDT Counter
=
?
Before Instruction
FLAG_REG
=
=
0x5A
0x00
After Instruction
After Instruction
FLAG_REG
WDT Counter
WDT Postscaler
TO
PD
=
=
=
=
0x00
0
1
1
© 2007 Microchip Technology Inc.
DS39605F-page 207
PIC18F1220/1320
COMF
Complement f
CPFSEQ
Compare f with W, skip if f = W
Syntax:
[ label ] COMF f [,d [,a]]
Syntax:
[ label ] CPFSEQ f [,a]
Operands:
0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
Operands:
0 ≤ f ≤ 255
a ∈ [0,1]
Operation:
(f) – (W),
Operation:
(f) → dest
skip if (f) = (W)
(unsigned comparison)
Status Affected:
Encoding:
N, Z
Status Affected:
Encoding:
None
0001
11da
ffff
ffff
0110
001a
ffff
ffff
Description:
The contents of register ‘f’ are
complemented. If ‘d’ is ‘0’, the
result is stored in W. If ‘d’ is ‘1’, the
result is stored back in register ‘f’
(default). If ‘a’ is ‘0’, the Access
Bank will be selected, overriding
the BSR value. If ‘a’ = 1, then the
bank will be selected as per the
BSR value (default).
Description:
Compares the contents of data
memory location ‘f’ to the contents
of W by performing an unsigned
subtraction.
If ‘f’ = W, then the fetched
instruction is discarded and a NOP
is executed instead, making this a
two-cycle instruction. If ‘a’ is ‘0’, the
Access Bank will be selected,
overriding the BSR value. If ‘a’ = 1,
then the bank will be selected as
per the BSR value (default).
Words:
Cycles:
1
1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Words:
Cycles:
1
Decode
Read
register ‘f’
Process
Data
Write to
1(2)
destination
Note: 3 cycles if skip and followed
by a 2-word instruction.
COMF
REG, W
Example:
Before Instruction
Q Cycle Activity:
Q1
REG
=
0x13
Q2
Q3
Q4
After Instruction
Decode
Read
register ‘f’
Process
Data
No
operation
REG
=
0x13
W
=
0xEC
If skip:
Q1
Q2
Q3
Q4
No
No
No
No
operation
operation
operation
operation
If skip and followed by 2-word instruction:
Q1
Q2
Q3
Q4
No
No
No
No
operation
operation
operation
operation
No
No
No
No
operation
operation
operation
operation
HERE
CPFSEQ REG
Example:
NEQUAL
EQUAL
:
:
Before Instruction
PC Address
=
=
=
HERE
?
?
W
REG
After Instruction
If REG
=
=
≠
=
W;
PC
Address (EQUAL)
If REG
PC
W;
Address (NEQUAL)
DS39605F-page 208
© 2007 Microchip Technology Inc.
PIC18F1220/1320
CPFSGT
Compare f with W, skip if f > W
CPFSLT
Compare f with W, skip if f < W
Syntax:
[ label ] CPFSGT f [,a]
Syntax:
[ label ] CPFSLT f [,a]
Operands:
0 ≤ f ≤ 255
a ∈ [0,1]
Operands:
0 ≤ f ≤ 255
a ∈ [0,1]
Operation:
(f) – (W),
Operation:
(f) – (W),
skip if (f) > (W)
(unsigned comparison)
skip if (f) < (W)
(unsigned comparison)
Status Affected:
Encoding:
None
Status Affected:
Encoding:
None
0110
010a
ffff
ffff
0110
000a
ffff
ffff
Description:
Compares the contents of data
memory location ‘f’ to the contents
of W by performing an unsigned
subtraction.
Description:
Compares the contents of data
memory location ‘f’ to the contents
of W by performing an unsigned
subtraction.
If the contents of ‘f’ are greater than
the contents of WREG, then the
fetched instruction is discarded and
a NOPis executed instead, making
this a two-cycle instruction. If ‘a’ is
‘0’, the Access Bank will be
selected, overriding the BSR value.
If ‘a’ = 1, then the bank will be
selected as per the BSR value
(default).
If the contents of ‘f’ are less than
the contents of W, then the fetched
instruction is discarded and a NOP
is executed instead, making this a
two-cycle instruction. If ‘a’ is ‘0’, the
Access Bank will be selected. If ‘a’
is ‘1’, the BSR will not be
overridden (default).
Words:
Cycles:
1
1(2)
Words:
Cycles:
1
Note: 3 cycles if skip and followed
by a 2-word instruction.
1(2)
Note: 3 cycles if skip and followed
by a 2-word instruction.
Q Cycle Activity:
Q1
Q2
Q3
Q4
Q Cycle Activity:
Q1
Decode
Read
register ‘f’
Process
Data
No
operation
Q2
Q3
Q4
Decode
Read
register ‘f’
Process
Data
No
operation
If skip:
Q1
Q2
Q3
Q4
If skip:
Q1
No
operation
No
operation
No
operation
No
operation
Q2
Q3
Q4
No
operation
No
operation
No
operation
No
operation
If skip and followed by 2-word instruction:
Q1
Q2
Q3
Q4
If skip and followed by 2-word instruction:
No
No
No
No
Q1
Q2
Q3
Q4
operation
operation
operation
operation
No
No
No
No
No
No
No
No
operation
operation
operation
operation
operation
operation
operation
operation
No
No
No
No
operation
operation
operation
operation
HERE
NLESS
LESS
CPFSLT REG
:
:
Example:
HERE
CPFSGT REG
Example:
NGREATER
GREATER
:
:
Before Instruction
PC
W
=
=
Address (HERE)
?
Before Instruction
After Instruction
PC
=
=
Address (HERE)
?
W
If REG
<
=
≥
=
W;
PC
Address (LESS)
W;
After Instruction
If REG
PC
If REG
>
=
≤
=
W;
Address (NLESS)
PC
Address (GREATER)
W;
If REG
PC
Address (NGREATER)
© 2007 Microchip Technology Inc.
DS39605F-page 209
PIC18F1220/1320
DAW
Decimal Adjust W Register
DECF
Decrement f
Syntax:
[ label ] DAW
Syntax:
[ label ] DECF f [,d [,a]]
Operands:
Operation:
None
Operands:
0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
If [W<3:0> > 9] or [DC = 1] then
(W<3:0>) + 6 → W<3:0>;
else
(W<3:0>) → W<3:0>;
Operation:
(f) – 1 → dest
Status Affected:
Encoding:
C, DC, N, OV, Z
0000
01da
ffff
ffff
If [W<7:4> > 9] or [C = 1] then
(W<7:4>) + 6 → W<7:4>;
else
Description:
Decrement register ‘f’. If ‘d’ is ‘0’,
the result is stored in W. If ‘d’ is ‘1’,
the result is stored back in register
‘f’ (default). If ‘a’ is ‘0’, the Access
Bank will be selected, overriding
the BSR value. If ‘a’ = 1, then the
bank will be selected as per the
BSR value (default).
(W<7:4>) → W<7:4>;
Status Affected:
Encoding:
C, DC
0000
0000
0000
0111
Description:
DAW adjusts the eight-bit value in
W, resulting from the earlier addi-
tion of two variables (each in
packed BCD format) and produces
a correct packed BCD result. The
Carry bit may be set by DAWregard-
less of its setting prior to the DAW
instruction.
Words:
Cycles:
1
1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
register ‘f’
Process
Data
Write to
destination
Words:
Cycles:
1
1
DECF
CNT
Example:
Q Cycle Activity:
Q1
Before Instruction
Q2
Q3
Q4
CNT
Z
=
0x01
0
Decode
Read
register W
Process
Data
Write
W
=
After Instruction
DAW
Example 1:
CNT
Z
=
=
0x00
1
Before Instruction
W
=
=
=
0xA5
0
0
C
DC
After Instruction
W
=
=
=
0x05
1
0
C
DC
Example 2:
Before Instruction
W
=
=
=
0xCE
0
0
C
DC
After Instruction
W
=
=
=
0x34
1
0
C
DC
DS39605F-page 210
© 2007 Microchip Technology Inc.
PIC18F1220/1320
DECFSZ
Decrement f, skip if 0
DCFSNZ
Decrement f, skip if not 0
Syntax:
[ label ] DECFSZ f [,d [,a]]
Syntax:
[ label ] DCFSNZ f [,d [,a]]
Operands:
0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
Operands:
Operation:
0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
Operation:
(f) – 1 → dest,
skip if result = 0
(f) – 1 → dest,
skip if result ≠ 0
Status Affected:
Encoding:
None
Status Affected:
Encoding:
None
0010
11da
ffff
ffff
0100
11da
ffff
ffff
Description:
The contents of register ‘f’ are
decremented. If ‘d’ is ‘0’, the result
is placed in W. If ‘d’ is ‘1’, the result
is placed back in register ‘f’
(default).
Description:
The contents of register ‘f’ are
decremented. If ‘d’ is ‘0’, the result
is placed in W. If ‘d’ is ‘1’, the result
is placed back in register ‘f’
(default).
If the result is ‘0’, the next instruc-
tion, which is already fetched, is
discarded and a NOPis executed
instead, making it a two-cycle
instruction. If ‘a’ is ‘0’, the Access
Bank will be selected, overriding
the BSR value. If ‘a’ = 1, then the
bank will be selected as per the
BSR value (default).
If the result is not ‘0’, the next
instruction, which is already
fetched, is discarded and a NOPis
executed instead, making it a two-
cycle instruction. If ‘a’ is ‘0’, the
Access Bank will be selected,
overriding the BSR value. If ‘a’ = 1,
then the bank will be selected as
per the BSR value (default).
Words:
Cycles:
1
Words:
Cycles:
1
1(2)
1(2)
Note: 3 cycles if skip and followed
by a 2-word instruction.
Note: 3 cycles if skip and followed
by a 2-word instruction.
Q Cycle Activity:
Q1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Q2
Q3
Q4
Decode
Read
register ‘f’
Process
Data
Write to
destination
Decode
Read
register ‘f’
Process
Data
Write to
destination
If skip:
Q1
If skip:
Q1
Q2
Q3
Q4
Q2
Q3
Q4
No
No
No
No
No
No
No
No
operation
operation
operation
operation
operation
operation
operation
operation
If skip and followed by 2-word instruction:
If skip and followed by 2-word instruction:
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
No
No
No
No
No
No
No
No
operation
operation
operation
operation
operation
operation
operation
operation
No
No
No
No
No
No
No
No
operation
operation
operation
operation
operation
operation
operation
operation
HERE
DECFSZ
GOTO
CNT
LOOP
HERE
ZERO
NZERO
DCFSNZ TEMP
:
:
Example:
Example:
CONTINUE
Before Instruction
Before Instruction
TEMP
PC
=
Address (HERE)
=
?
After Instruction
After Instruction
CNT
=
=
=
≠
=
CNT – 1
0;
TEMP
If TEMP
PC
If TEMP
PC
=
=
=
≠
=
TEMP – 1,
0;
If CNT
PC
Address (CONTINUE)
0;
Address (ZERO)
0;
If CNT
PC
Address (HERE + 2)
Address (NZERO)
© 2007 Microchip Technology Inc.
DS39605F-page 211
PIC18F1220/1320
GOTO
Unconditional Branch
INCF
Increment f
Syntax:
[ label ] GOTO k
0 ≤ k ≤ 1048575
k → PC<20:1>
None
Syntax:
[ label ] INCF f [,d [,a]]
Operands:
Operation:
Status Affected:
Operands:
0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
Operation:
(f) + 1 → dest
Encoding:
1st word (k<7:0>)
2nd word(k<19:8>)
Status Affected:
Encoding:
C, DC, N, OV, Z
1110
1111
1111
k kkk
kkkk
kkkk
7
0
8
k
kkk kkkk
0010
10da
ffff
ffff
19
Description:
GOTOallows an unconditional
Description:
The contents of register ‘f’ are
incremented. If ‘d’ is ‘0’, the result
is placed in W. If ‘d’ is ‘1’, the result
is placed back in register ‘f’
(default). If ‘a’ is ‘0’, the Access
Bank will be selected, overriding
the BSR value. If ‘a’ = 1, then the
bank will be selected as per the
BSR value (default).
branch anywhere within the entire
2-Mbyte memory range. The 20-bit
value ‘k’ is loaded into PC<20:1>.
GOTOis always a two-cycle
instruction.
Words:
Cycles:
2
2
Q Cycle Activity:
Q1
Words:
Cycles:
1
1
Q2
Q3
Q4
Decode
Read literal
‘k’<7:0>,
No
operation
Read literal
‘k’<19:8>,
Write to PC
Q Cycle Activity:
Q1
Q2
Q3
Q4
No
operation
No
operation
No
operation
No
operation
Decode
Read
register ‘f’
Process
Data
Write to
destination
GOTO THERE
Example:
INCF
CNT
Example:
After Instruction
Before Instruction
PC
=
Address (THERE)
CNT
=
0xFF
Z
=
=
=
0
?
?
C
DC
After Instruction
CNT
=
=
=
=
0x00
Z
1
1
1
C
DC
DS39605F-page 212
© 2007 Microchip Technology Inc.
PIC18F1220/1320
INCFSZ
Increment f, skip if 0
INFSNZ
Increment f, skip if not 0
Syntax:
[ label ] INCFSZ f [,d [,a]]
Syntax:
[ label ] INFSNZ f [,d [,a]]
Operands:
0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
Operands:
Operation:
0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
Operation:
(f) + 1 → dest,
skip if result = 0
(f) + 1 → dest,
skip if result ≠ 0
Status Affected:
Encoding:
None
Status Affected:
Encoding:
None
0011
11da
ffff
ffff
0100
10da
ffff
ffff
Description:
The contents of register ‘f’ are
incremented. If ‘d’ is ‘0’, the result
is placed in W. If ‘d’ is ‘1’, the result
is placed back in register ‘f’
(default).
Description:
The contents of register ‘f’ are
incremented. If ‘d’ is ‘0’, the result
is placed in W. If ‘d’ is ‘1’, the result
is placed back in register ‘f’
(default).
If the result is ‘0’, the next instruc-
tion, which is already fetched, is
discarded and a NOPis executed
instead, making it a two-cycle
instruction. If ‘a’ is ‘0’, the Access
Bank will be selected, overriding
the BSR value. If ‘a’ = 1, then the
bank will be selected as per the
BSR value (default).
If the result is not ‘0’, the next
instruction, which is already
fetched, is discarded and a NOPis
executed instead, making it a
two-cycle instruction. If ‘a’ is ‘0’, the
Access Bank will be selected, over-
riding the BSR value. If ‘a’ = 1, then
the bank will be selected as per the
BSR value (default).
Words:
Cycles:
1
Words:
Cycles:
1
1(2)
1(2)
Note: 3 cycles if skip and followed
by a 2-word instruction.
Note: 3 cycles if skip and followed
by a 2-word instruction.
Q Cycle Activity:
Q1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Q2
Q3
Q4
Decode
Read
register ‘f’
Process
Data
Write to
destination
Decode
Read
register ‘f’
Process
Data
Write to
destination
If skip:
Q1
If skip:
Q1
Q2
Q3
Q4
Q2
Q3
Q4
No
No
No
No
No
No
No
No
operation
operation
operation
operation
operation
operation
operation
operation
If skip and followed by 2-word instruction:
If skip and followed by 2-word instruction:
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
No
No
No
No
No
No
No
No
operation
operation
operation
operation
operation
operation
operation
operation
No
No
No
No
No
No
No
No
operation
operation
operation
operation
operation
operation
operation
operation
HERE
NZERO
ZERO
INCFSZ
:
:
CNT
HERE
ZERO
NZERO
INFSNZ REG
Example:
Example:
Before Instruction
Before Instruction
PC
=
Address (HERE)
PC
=
Address (HERE)
After Instruction
After Instruction
CNT
If CNT
PC
If CNT
PC
=
=
=
≠
=
CNT + 1
REG
If REG
PC
If REG
PC
=
≠
=
=
=
REG + 1
0;
0;
Address (ZERO)
0;
Address (NZERO)
Address (NZERO)
0;
Address (ZERO)
© 2007 Microchip Technology Inc.
DS39605F-page 213
PIC18F1220/1320
IORLW
Inclusive OR literal with W
IORWF
Inclusive OR W with f
Syntax:
[ label ] IORLW k
0 ≤ k ≤ 255
Syntax:
[ label ] IORWF f [,d [,a]]
Operands:
Operation:
Status Affected:
Encoding:
Operands:
0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
(W) .OR. k → W
N, Z
Operation:
(W) .OR. (f) → dest
0000
1001
kkkk
kkkk
Status Affected:
Encoding:
N, Z
Description:
The contents of W are OR’ed with
the eight-bit literal ‘k’. The result is
placed in W.
0001
00da
ffff
ffff
Description:
Inclusive OR W with register ‘f’. If
‘d’ is ‘0’, the result is placed in W. If
‘d’ is ‘1’, the result is placed back in
register ‘f’ (default). If ‘a’ is ‘0’, the
Access Bank will be selected, over-
riding the BSR value. If ‘a’ = 1, then
the bank will be selected as per the
BSR value (default).
Words:
Cycles:
1
1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
literal ‘k’
Process
Data
Write to W
Words:
Cycles:
1
1
IORLW
0x35
Example:
Before Instruction
Q Cycle Activity:
Q1
W
=
0x9A
Q2
Q3
Q4
Decode
Read
register ‘f’
Process
Data
Write to
destination
After Instruction
W
=
0xBF
IORWF RESULT, W
Example:
Before Instruction
RESULT =
0x13
0x91
W
=
After Instruction
RESULT =
0x13
0x93
W
=
DS39605F-page 214
© 2007 Microchip Technology Inc.
PIC18F1220/1320
LFSR
Load FSR
MOVF
Move f
Syntax:
[ label ] LFSR f,k
Syntax:
[ label ] MOVF f [,d [,a]]
Operands:
0 ≤ f ≤ 2
Operands:
0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
0 ≤ k ≤ 4095
Operation:
k → FSRf
Operation:
f → dest
N, Z
Status Affected:
Encoding:
None
Status Affected:
Encoding:
1110
1111
1110
0000
00ff
k kkk
11
kkkk
k kkk
0101
00da
ffff
ffff
7
Description:
The 12-bit literal ‘k’ is loaded into
the file select register pointed to
by ‘f’.
Description:
The contents of register ‘f’ are
moved to a destination dependent
upon the status of ‘d’. If ‘d’ is ‘f’, the
result is placed in W. If ‘d’ is ‘f’, the
result is placed back in register ‘f’
(default). Location ‘f’ can be any-
where in the 256-byte bank. If ‘a’ is
‘0’, the Access Bank will be
Words:
Cycles:
2
2
Q Cycle Activity:
Q1
Q2
Q3
Q4
selected, overriding the BSR value.
If ‘a’ = 1, then the bank will be
selected as per the BSR value
(default).
Decode
Read literal
‘k’ MSB
Process
Data
Write literal
‘k’ MSB to
FSRfH
Decode
Read literal
‘k’ LSB
Process
Data
Write literal
‘k’ to FSRfL
Words:
Cycles:
1
1
LFSR 2, 0x3AB
Example:
Q Cycle Activity:
Q1
After Instruction
Q2
Q3
Q4
FSR2H
FSR2L
=
=
0x03
0xAB
Decode
Read
register ‘f’
Process
Data
Write W
MOVF
REG, W
Example:
Before Instruction
REG
W
=
=
0x22
0xFF
After Instruction
REG
W
=
=
0x22
0x22
© 2007 Microchip Technology Inc.
DS39605F-page 215
PIC18F1220/1320
MOVFF
Move f to f
MOVLB
Move literal to low nibble in BSR
Syntax:
[ label ] MOVFF fs,fd
Syntax:
[ label ] MOVLB k
0 ≤ k ≤ 255
k → BSR
Operands:
0 ≤ fs ≤ 4095
0 ≤ fd ≤ 4095
Operands:
Operation:
Status Affected:
Encoding:
Operation:
(fs) → fd
None
Status Affected:
None
0000
0001
kkkk
kkkk
Encoding:
1st word (source)
2nd word (destin.)
Description:
The 8-bit literal ‘k’ is loaded into
the Bank Select Register (BSR).
1100
1111
ffff
ffff
ffff
ffff
ffffs
ffffd
Words:
Cycles:
1
1
Description:
The contents of source register ‘fs’
are moved to destination register
‘fd’. Location of source ‘fs’ can be
anywhere in the 4096-byte data
space (000h to FFFh) and location
of destination ‘fd’ can also be
anywhere from 000h to FFFh.
Either source or destination can be
W (a useful special situation).
MOVFFis particularly useful for
transferring a data memory location
to a peripheral register (such as the
transmit buffer or an I/O port).
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read literal
‘k’
Process
Data
Write
literal ‘k’ to
BSR
MOVLB
5
Example:
Before Instruction
BSR register
=
=
0x02
0x05
After Instruction
BSR register
The MOVFFinstruction cannot use
the PCL, TOSU, TOSH or TOSL as
the destination register.
The MOVFFinstruction should not
be used to modify interrupt settings
while any interrupt is enabled (see
page 73).
Words:
Cycles:
2
2 (3)
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
register ‘f’
(src)
Process
Data
No
operation
Decode
No
operation
No
operation
Write
register ‘f’
(dest)
No dummy
read
MOVFF
REG1, REG2
Example:
Before Instruction
REG1
REG2
=
=
0x33
0x11
After Instruction
REG1
REG2
=
=
0x33,
0x33
DS39605F-page 216
© 2007 Microchip Technology Inc.
PIC18F1220/1320
MOVLW
Move literal to W
MOVWF
Move W to f
Syntax:
[ label ] MOVLW k
0 ≤ k ≤ 255
k → W
Syntax:
[ label ] MOVWF f [,a]
Operands:
Operation:
Status Affected:
Encoding:
Operands:
0 ≤ f ≤ 255
a ∈ [0,1]
Operation:
(W) → f
None
None
Status Affected:
Encoding:
0000
1110
kkkk
kkkk
0110
111a
ffff
ffff
Description:
The eight-bit literal ‘k’ is loaded
into W.
Description:
Move data from W to register ‘f’.
Location ‘f’ can be anywhere in the
256-byte bank. If ‘a’ is ‘0’, the
Access Bank will be selected, over-
riding the BSR value. If ‘a’ = 1, then
the bank will be selected as per the
BSR value (default).
Words:
Cycles:
1
1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
literal ‘k’
Process
Data
Write to W
Words:
Cycles:
1
1
MOVLW
0x5A
Example:
Q Cycle Activity:
Q1
After Instruction
Q2
Q3
Q4
W
=
0x5A
Decode
Read
register ‘f’
Process
Data
Write
register ‘f’
MOVWF
REG
Example:
Before Instruction
W
REG
=
=
0x4F
0xFF
After Instruction
W
REG
=
=
0x4F
0x4F
© 2007 Microchip Technology Inc.
DS39605F-page 217
PIC18F1220/1320
MULLW
Multiply Literal with W
MULWF
Multiply W with f
Syntax:
[ label ] MULLW
0 ≤ k ≤ 255
k
Syntax:
[ label ] MULWF f [,a]
Operands:
Operation:
Status Affected:
Encoding:
Operands:
0 ≤ f ≤ 255
a ∈ [0,1]
(W) x k → PRODH:PRODL
Operation:
(W) x (f) → PRODH:PRODL
None
Status Affected:
Encoding:
None
0000
1101
kkkk
kkkk
0000
001a
ffff
ffff
Description:
An unsigned multiplication is
carried out between the contents
of W and the 8-bit literal ‘k’. The
16-bit result is placed in the
PRODH:PRODL register pair.
PRODH contains the high byte.
W is unchanged.
None of the Status flags are
affected.
Note that neither Overflow nor
Carry is possible in this opera-
tion. A Zero result is possible but
not detected.
Description:
An unsigned multiplication is
carried out between the contents
of W and the register file location
‘f’. The 16-bit result is stored in
the PRODH:PRODL register
pair. PRODH contains the high
byte.
Both W and ‘f’ are unchanged.
None of the Status flags are
affected.
Note that neither Overflow nor
Carry is possible in this opera-
tion. A Zero result is possible,
but not detected. If ‘a’ is ‘0’, the
Access Bank will be selected,
overriding the BSR value. If
‘a’ = 1, then the bank will be
selected as per the BSR value
(default).
Words:
Cycles:
1
1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
literal ‘k’
Process
Data
Write
registers
PRODH:
PRODL
Words:
Cycles:
1
1
Q Cycle Activity:
Q1
MULLW
0xC4
Example:
Q2
Q3
Q4
Before Instruction
Decode
Read
register ‘f’
Process
Data
Write
W
PRODH
PRODL
=
=
=
0xE2
registers
PRODH:
PRODL
?
?
After Instruction
W
PRODH
PRODL
=
=
=
0xE2
0xAD
0x08
MULWF
REG
Example:
Before Instruction
W
=
=
=
=
0xC4
0xB5
?
?
REG
PRODH
PRODL
After Instruction
W
=
=
=
=
0xC4
0xB5
0x8A
0x94
REG
PRODH
PRODL
DS39605F-page 218
© 2007 Microchip Technology Inc.
PIC18F1220/1320
NEGF
Negate f
NOP
No Operation
Syntax:
[ label ] NEGF f [,a]
Syntax:
[ label ] NOP
Operands:
0 ≤ f ≤ 255
a ∈ [0,1]
Operands:
None
Operation:
No operation
None
Operation:
(f) + 1 → f
Status Affected:
Encoding:
Status Affected:
Encoding:
N, OV, C, DC, Z
0000
1111
0000
xxxx
0000
xxxx
0000
xxxx
0110
110a
ffff
ffff
Description:
Words:
No operation.
Description:
Location ‘f’ is negated using two’s
complement. The result is placed in
the data memory location ‘f’. If ‘a’ is
‘0’, the Access Bank will be
1
1
Cycles:
Q Cycle Activity:
Q1
selected, overriding the BSR value.
If ‘a’ = 1, then the bank will be
selected as per the BSR value.
Q2
No
Q3
No
Q4
Decode
No
operation
operation
operation
Words:
Cycles:
1
1
Example:
None.
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
register ‘f’
Process
Data
Write
register ‘f’
NEGF
REG, 1
Example:
Before Instruction
REG
=
0011 1010 [0x3A]
1100 0110 [0xC6]
After Instruction
REG
=
© 2007 Microchip Technology Inc.
DS39605F-page 219
PIC18F1220/1320
POP
Pop Top of Return Stack
PUSH
Push Top of Return Stack
Syntax:
[ label ] POP
None
Syntax:
[ label ] PUSH
None
Operands:
Operation:
Status Affected:
Encoding:
Operands:
Operation:
Status Affected:
Encoding:
(TOS) → bit bucket
None
(PC + 2) → TOS
None
0000
0000
0000
0110
0000
0000
0000
0101
Description:
The TOS value is pulled off the
return stack and is discarded. The
TOS value then becomes the
previous value that was pushed
onto the return stack.
This instruction is provided to
enable the user to properly manage
the return stack to incorporate a
software stack.
Description:
The PC + 2 is pushed onto the top
of the return stack. The previous
TOS value is pushed down on the
stack.
This instruction allows implement-
ing a software stack by modifying
TOS and then pushing it onto the
return stack.
Words:
Cycles:
1
1
Words:
Cycles:
1
1
Q Cycle Activity:
Q1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Q2
Q3
Q4
Decode
Push
No
No
PC + 2 onto
return stack
operation
operation
Decode
No
operation
Pop TOS
value
No
operation
PUSH
Example:
POP
GOTO
Example:
NEW
Before Instruction
Before Instruction
TOS
PC
=
=
0x00345A
0x000124
TOS
=
=
0x0031A2
0x014332
Stack (1 level down)
After Instruction
After Instruction
PC
=
=
=
0x000126
0x000126
0x00345A
TOS
TOS
PC
=
=
0x014332
NEW
Stack (1 level down)
DS39605F-page 220
© 2007 Microchip Technology Inc.
PIC18F1220/1320
RCALL
Relative Call
RESET
Reset
Syntax:
[ label ] RCALL
-1024 ≤ n ≤ 1023
(PC) + 2 → TOS,
n
Syntax:
[ label ] RESET
Operands:
Operation:
Operands:
Operation:
None
Reset all registers and flags that
are affected by a MCLR Reset.
(PC) + 2 + 2n → PC
Status Affected:
Encoding:
None
Status Affected:
Encoding:
All
1101
1nnn
nnnn
nnnn
0000
0000
1111
1111
Description:
Subroutine call with a jump up to 1K
from the current location. First,
Description:
This instruction provides a way to
execute a MCLR Reset in software.
return address (PC + 2) is pushed
onto the stack. Then, add the 2’s
complement number ‘2n’ to the PC.
Since the PC will have incremented
to fetch the next instruction, the new
address will be PC + 2 + 2n. This
instruction is a two-cycle instruction.
Words:
Cycles:
1
1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Start
Reset
No
operation
No
operation
Words:
Cycles:
1
2
RESET
Example:
After Instruction
Registers =
Q Cycle Activity:
Q1
Reset Value
Reset Value
Q2
Q3
Q4
Flags*
=
Decode
Read literal
‘n’
Process
Data
Write to PC
Push PC to
stack
No
No
No
No
operation
operation
operation
operation
HERE
RCALL
Jump
Example:
Before Instruction
PC
=
Address (HERE)
After Instruction
PC
=
Address (Jump)
Address (HERE + 2)
TOS =
© 2007 Microchip Technology Inc.
DS39605F-page 221
PIC18F1220/1320
RETFIE
Return from Interrupt
RETLW
Return Literal to W
Syntax:
[ label ] RETFIE [s]
s ∈ [0,1]
Syntax:
[ label ] RETLW k
0 ≤ k ≤ 255
Operands:
Operation:
Operands:
Operation:
(TOS) → PC,
1 → GIE/GIEH or PEIE/GIEL,
if s = 1
k → W,
(TOS) → PC,
PCLATU, PCLATH are unchanged
(WS) → W,
(STATUSS) → Status,
(BSRS) → BSR,
Status Affected:
Encoding:
None
0000
1100
kkkk
kkkk
PCLATU, PCLATH are unchanged.
Description:
W is loaded with the eight-bit literal
‘k’. The program counter is loaded
from the top of the stack (the return
address). The high address latch
(PCLATH) remains unchanged.
Status Affected:
Encoding:
GIE/GIEH, PEIE/GIEL.
0000
0000
0001
000s
Description:
Return from interrupt. Stack is
popped and Top-of-Stack (TOS) is
loaded into the PC. Interrupts are
enabled by setting either the high
or low priority global interrupt
enable bit. If ‘s’ = 1, the contents of
the shadow registers, WS,
STATUSS and BSRS, are loaded
into their corresponding registers,
W, Status and BSR. If ‘s’ = 0, no
update of these registers occurs
(default).
Words:
Cycles:
1
2
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
literal ‘k’
Process
Data
Pop PC
from stack,
Write to W
No
No
No
No
operation
operation
operation
operation
Words:
Cycles:
1
2
Example:
CALL TABLE ; W contains table
; offset value
Q Cycle Activity:
Q1
Q2
Q3
Q4
; W now has
; table value
Decode
No
operation
No
operation
Pop PC
from stack
:
TABLE
ADDWF PCL ; W = offset
Set GIEH or
GIEL
RETLW k0
RETLW k1
:
; Begin table
;
No
operation
No
operation
No
operation
No
operation
:
RETLW kn
; End of table
RETFIE
1
Example:
After Interrupt
Before Instruction
PC
W
=
=
=
=
=
TOS
WS
W
=
0x07
BSR
Status
GIE/GIEH, PEIE/GIEL
BSRS
STATUSS
1
After Instruction
W
=
value of kn
DS39605F-page 222
© 2007 Microchip Technology Inc.
PIC18F1220/1320
RETURN
Return from Subroutine
RLCF
Rotate Left f through Carry
Syntax:
[ label ] RETURN [s]
s ∈ [0,1]
Syntax:
[ label ] RLCF f [,d [,a]]
Operands:
Operation:
Operands:
Operation:
0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
(TOS) → PC,
if s = 1
(WS) → W,
(STATUSS) → Status,
(BSRS) → BSR,
PCLATU, PCLATH are unchanged
(f<n>) → dest<n + 1>,
(f<7>) → C,
(C) → dest<0>
Status Affected:
Encoding:
C, N, Z
Status Affected:
Encoding:
None
0011
01da
ffff
ffff
0000
0000
0001
001s
Description:
The contents of register ‘f’ are
rotated one bit to the left through
the Carry flag. If ‘d’ is ‘0’, the result
is placed in W. If ‘d’ is ‘1’, the result
is stored back in register ‘f’
(default). If ‘a’ is ‘0’, the Access
Bank will be selected, overriding
the BSR value. If ‘a’ = 1, then the
bank will be selected as per the
BSR value (default).
Description:
Return from subroutine. The stack
is popped and the top of the stack
is loaded into the program counter.
If ‘s’= 1, the contents of the shadow
registers, WS, STATUSS and
BSRS, are loaded into their corre-
sponding registers, W, Status and
BSR. If ‘s’ = 0, no update of these
registers occurs (default).
Words:
Cycles:
1
2
register f
C
Words:
Cycles:
1
1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Q Cycle Activity:
Q1
Decode
No
operation
Process
Data
Pop PC
from stack
Q2
Q3
Q4
No
No
No
No
Decode
Read
Process
Write to
operation
operation
operation
operation
register ‘f’
Data
destination
RLCF
REG, W
Example:
RETURN
Example:
Before Instruction
REG
C
=
=
1110 0110
0
After Interrupt
PC
=
TOS
After Instruction
REG
=
=
=
1110 0110
1100 1100
1
W
C
© 2007 Microchip Technology Inc.
DS39605F-page 223
PIC18F1220/1320
RLNCF
Rotate Left f (no carry)
RRCF
Rotate Right f through Carry
Syntax:
[ label ] RLNCF f [,d [,a]]
Syntax:
[ label ] RRCF f [,d [,a]]
Operands:
0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
Operands:
0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
Operation:
(f<n>) → dest<n + 1>,
(f<7>) → dest<0>
Operation:
(f<n>) → dest<n – 1>,
(f<0>) → C,
(C) → dest<7>
Status Affected:
Encoding:
N, Z
Status Affected:
Encoding:
C, N, Z
0100
01da
ffff
ffff
0011
00da
ffff
ffff
Description:
The contents of register ‘f’ are
rotated one bit to the left. If ‘d’ is ‘0’,
the result is placed in W. If ‘d’ is ‘1’,
the result is stored back in register
‘f’ (default). If ‘a’ is ‘0’, the Access
Bank will be selected, overriding
the BSR value. If ‘a’ is ‘1’, then the
bank will be selected as per the
BSR value (default).
Description:
The contents of register ‘f’ are
rotated one bit to the right through
the Carry flag. If ‘d’ is ‘0’, the result
is placed in W. If ‘d’ is ‘1’, the result
is placed back in register ‘f’
(default). If ‘a’ is ‘0’, the Access
Bank will be selected, overriding
the BSR value. If ‘a’ is ‘1’, then the
bank will be selected as per the
BSR value (default).
register f
Words:
Cycles:
1
1
register f
C
Words:
Cycles:
1
1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Q Cycle Activity:
Q1
Decode
Read
register ‘f’
Process
Data
Write to
destination
Q2
Q3
Q4
Decode
Read
register ‘f’
Process
Data
Write to
destination
RLNCF
REG
Example:
Before Instruction
RRCF
REG, W
Example:
REG
=
1010 1011
0101 0111
After Instruction
Before Instruction
REG
=
REG
C
=
=
1110 0110
0
After Instruction
REG
=
=
=
1110 0110
0111 0011
0
W
C
DS39605F-page 224
© 2007 Microchip Technology Inc.
PIC18F1220/1320
RRNCF
Rotate Right f (no carry)
SETF
Set f
Syntax:
[ label ] RRNCF f [,d [,a]]
Syntax:
[ label ] SETF f [,a]
Operands:
0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
Operands:
0 ≤ f ≤ 255
a ∈ [0,1]
Operation:
FFh → f
None
Operation:
(f<n>) → dest<n – 1>,
(f<0>) → dest<7>
Status Affected:
Encoding:
0110
100a
ffff
ffff
Status Affected:
Encoding:
N, Z
Description:
The contents of the specified
0100
00da
ffff
ffff
register are set to FFh. If ‘a’ is ‘0’,
the Access Bank will be selected,
overriding the BSR value. If ‘a’ is
‘1’, then the bank will be selected
as per the BSR value (default).
Description:
The contents of register ‘f’ are
rotated one bit to the right. If ‘d’ is
‘0’, the result is placed in W. If ‘d’ is
‘1’, the result is placed back in
register ‘f’ (default). If ‘a’ is ‘0’, the
Access Bank will be selected,
overriding the BSR value. If ‘a’ is
‘1’, then the bank will be selected
as per the BSR value (default).
Words:
Cycles:
1
1
Q Cycle Activity:
Q1
Q2
Q3
Q4
register f
Decode
Read
register ‘f’
Process
Data
Write
register ‘f’
Words:
Cycles:
1
1
SETF
REG
Example:
Before Instruction
Q Cycle Activity:
Q1
REG
=
=
0x5A
0xFF
Q2
Q3
Q4
After Instruction
REG
Decode
Read
register ‘f’
Process
Data
Write to
destination
RRNCF
REG, 1, 0
Example 1:
Before Instruction
REG
=
1101 0111
After Instruction
REG
=
1110 1011
RRNCF REG, W
Example 2:
Before Instruction
W
REG
=
=
?
1101 0111
After Instruction
W
REG
=
=
1110 1011
1101 0111
© 2007 Microchip Technology Inc.
DS39605F-page 225
PIC18F1220/1320
SLEEP
Enter Sleep mode
SUBFWB
Subtract f from W with borrow
Syntax:
[ label ] SLEEP
Syntax:
[ label ] SUBFWB f [,d [,a]]
Operands:
Operation:
None
Operands:
0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
00h → WDT,
0 → WDT postscaler,
1 → TO,
Operation:
(W) – (f) – (C) → dest
0 → PD
Status Affected:
Encoding:
N, OV, C, DC, Z
Status Affected:
Encoding:
TO, PD
0101
01da
ffff
ffff
0000
0000
0000
0011
Description:
Subtract register ‘f’ and Carry flag
(borrow) from W (2’s complement
method). If ‘d’ is ‘0’, the result is
stored in W. If ‘d’ is ‘1’, the result is
stored in register ‘f’ (default). If ‘a’ is
‘0’, the Access Bank will be
selected, overriding the BSR value.
If ‘a’ is ‘1’, then the bank will be
selected as per the BSR value
(default).
Description:
The Power-down status bit (PD) is
cleared. The Time-out status bit
(TO) is set. The Watchdog Timer
and its postscaler are cleared.
The processor is put into Sleep
mode with the oscillator stopped.
Words:
Cycles:
1
1
Q Cycle Activity:
Q1
Words:
Cycles:
1
1
Q2
Q3
Q4
Decode
No
operation
Process
Data
Go to
Sleep
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
register ‘f’
Process
Data
Write to
destination
SLEEP
Example:
Before Instruction
SUBFWB REG
Example 1:
TO
PD
=
=
?
?
Before Instruction
After Instruction
REG
W
C
=
=
=
0x03
0x02
0x01
TO
PD
=
=
1†
0
After Instruction
† If WDT causes wake-up, this bit is cleared.
REG
W
C
=
=
=
=
=
0xFF
0x02
0x00
0x00
Z
N
0x01
; result is negative
REG, 0, 0
SUBFWB
Example 2:
Before Instruction
REG
=
=
=
2
5
1
W
C
After Instruction
REG
W
C
=
=
=
=
=
2
3
1
0
0
Z
N
; result is positive
SUBFWB
REG, 1, 0
Example 3:
Before Instruction
REG
=
=
=
1
2
0
W
C
After Instruction
REG
W
C
=
=
=
=
=
0
2
1
1
0
Z
; result is zero
N
DS39605F-page 226
© 2007 Microchip Technology Inc.
PIC18F1220/1320
SUBWF
Subtract W from f
SUBLW
Subtract W from literal
Syntax:
[ label ] SUBWF f [,d [,a]]
Syntax:
[ label ] SUBLW k
0 ≤ k ≤ 255
Operands:
0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
Operands:
Operation:
Status Affected:
Encoding:
k – (W) → W
N, OV, C, DC, Z
Operation:
(f) – (W) → dest
0000
1000
kkkk
kkkk
Status Affected:
Encoding:
N, OV, C, DC, Z
Description:
W is subtracted from the eight-bit
literal ‘k’. The result is placed
in W.
0101
11da
ffff
ffff
Description:
Subtract W from register ‘f’ (2’s
complement method). If ‘d’ is ‘0’,
the result is stored in W. If ‘d’ is
‘1’, the result is stored back in
register ‘f’ (default). If ‘a’ is ‘0’, the
Access Bank will be selected,
overriding the BSR value. If ‘a’ is
‘1’, then the bank will be selected
as per the BSR value (default).
Words:
Cycles:
1
1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
literal ‘k’
Process
Data
Write to W
SUBLW 0x02
Example 1:
Words:
Cycles:
1
1
Before Instruction
W
C
=
=
1
?
Q Cycle Activity:
Q1
After Instruction
Q2
Q3
Q4
W
C
Z
=
=
=
=
1
Decode
Read
register ‘f’
Process
Data
Write to
destination
1
0
0
; result is positive
N
SUBWF REG
Example 1:
SUBLW 0x02
Example 2:
Before Instruction
Before Instruction
REG
W
C
=
=
=
3
2
?
W
C
=
=
2
?
After Instruction
After Instruction
REG
W
C
=
=
=
=
=
1
2
1
0
0
W
C
Z
=
=
=
=
0
1
1
0
; result is zero
; result is positive
Z
N
N
SUBLW 0x02
Example 3:
SUBWF REG, W
Example 2:
Before Instruction
Before Instruction
W
C
=
=
3
?
REG
W
=
=
=
2
2
?
After Instruction
C
W
C
Z
=
=
=
=
FF ; (2’s complement)
After Instruction
0
0
1
; result is negative
REG
W
C
=
=
=
=
=
2
0
1
1
0
N
; result is zero
Z
N
SUBWF REG
Example 3:
Before Instruction
REG
W
C
=
=
=
0x01
0x02
?
After Instruction
REG
W
C
=
=
=
=
=
0xFFh ;(2’s complement)
0x02
0x00 ;result is negative
0x00
0x01
Z
N
© 2007 Microchip Technology Inc.
DS39605F-page 227
PIC18F1220/1320
SUBWFB
Syntax:
Subtract W from f with Borrow
SWAPF
Swap f
[ label ] SUBWFB f [,d [,a]]
Syntax:
[ label ] SWAPF f [,d [,a]]
Operands:
0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
Operands:
0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
Operation:
(f) – (W) – (C) → dest
Operation:
(f<3:0>) → dest<7:4>,
(f<7:4>) → dest<3:0>
Status Affected: N, OV, C, DC, Z
Status Affected:
Encoding:
None
Encoding:
0101
10da
ffff
ffff
0011
10da
ffff
ffff
Description:
Subtract W and the Carry flag
(borrow) from register ‘f’ (2’s comple-
ment method). If ‘d’ is ‘0’, the result is
stored in W. If ‘d’ is ‘1’, the result is
stored back in register ‘f’ (default). If
‘a’ is ‘0’, the Access Bank will be
selected, overriding the BSR value. If
‘a’ is ‘1’, then the bank will be
selected as per the BSR value
(default).
Description:
The upper and lower nibbles of
register ‘f’ are exchanged. If ‘d’ is
‘0’, the result is placed in W. If ‘d’ is
‘1’, the result is placed in register ‘f’
(default). If ‘a’ is ‘0’, the Access
Bank will be selected, overriding
the BSR value. If ‘a’ is ‘1’, then the
bank will be selected as per the
BSR value (default).
Words:
Cycles:
1
1
Words:
Cycles:
1
1
Q Cycle Activity:
Q1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Q2
Q3
Q4
Decode
Read
register ‘f’
Process
Data
Write to
destination
Decode
Read
register ‘f’
Process
Data
Write to
destination
SUBWFB REG, 1, 0
Example 1:
SWAPF
REG
Example:
Before Instruction
Before Instruction
REG
=
=
=
0x19
0x0D
0x01
(0001 1001)
(0000 1101)
REG
=
0x53
0x35
W
C
After Instruction
After Instruction
REG
=
REG
=
=
=
=
=
0x0C
0x0D
0x01
0x00
0x00
(0000 1011)
(0000 1101)
W
C
Z
N
; result is positive
SUBWFB REG, 0, 0
Example 2:
Before Instruction
REG
W
=
=
=
0x1B
0x1A
0x00
(0001 1011)
(0001 1010)
C
After Instruction
REG
W
C
=
=
=
=
=
0x1B
0x00
0x01
0x01
0x00
(0001 1011)
Z
; result is zero
N
SUBWFB REG, 1, 0
Example 3:
Before Instruction
REG
W
=
=
=
0x03
0x0E
0x01
(0000 0011)
(0000 1101)
C
After Instruction
REG
=
0xF5
(1111 0100)
; [2’s comp]
W
=
=
=
=
0x0E
0x00
0x00
0x01
(0000 1101)
C
Z
N
; result is negative
DS39605F-page 228
© 2007 Microchip Technology Inc.
PIC18F1220/1320
TBLRD
Table Read
TBLRD
Table Read (Continued)
TBLRD *+ ;
Syntax:
[ label ] TBLRD ( *; *+; *-; +*)
Example 1:
Operands:
Operation:
None
Before Instruction
TABLAT
TBLPTR
MEMORY(0x00A356)
=
=
=
0x55
0x00A356
0x34
if TBLRD *,
(Prog Mem (TBLPTR)) → TABLAT;
TBLPTR – No Change;
if TBLRD *+,
(Prog Mem (TBLPTR)) → TABLAT;
(TBLPTR) + 1 → TBLPTR;
if TBLRD *-,
After Instruction
TABLAT
TBLPTR
=
=
0x34
0x00A357
TBLRD +* ;
Example 2:
(Prog Mem (TBLPTR)) → TABLAT;
(TBLPTR) – 1 → TBLPTR;
if TBLRD +*,
(TBLPTR) + 1 → TBLPTR;
(Prog Mem (TBLPTR)) → TABLAT;
Before Instruction
TABLAT
TBLPTR
=
=
=
=
0xAA
0x01A357
0x12
MEMORY(0x01A357)
MEMORY(0x01A358)
0x34
After Instruction
Status Affected: None
TABLAT
TBLPTR
=
=
0x34
0x01A358
0000
0000
0000
10nn
nn = 0*
= 1*+
Encoding:
= 2*-
= 3+*
Description:
This instruction is used to read the
contents of Program Memory (P.M.). To
address the program memory, a pointer
called Table Pointer (TBLPTR) is used.
The TBLPTR (a 21-bit pointer) points
to each byte in the program memory.
TBLPTR has a 2-Mbyte address
range.
TBLPTR[0] = 0: Least Significant
Byte of Program
Memory Word
TBLPTR[0] = 1: Most Significant
Byte of Program
Memory Word
The TBLRDinstruction can modify the
value of TBLPTR as follows:
• no change
• post-increment
• post-decrement
• pre-increment
Words:
Cycles:
1
2
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
No
No
No
operation
operation
operation
No
No operation
No
No operation
(Write
TABLAT)
operation (Read Program operation
Memory)
© 2007 Microchip Technology Inc.
DS39605F-page 229
PIC18F1220/1320
TBLWT
Table Write
TBLWT
Table Write (Continued)
Syntax:
[ label ] TBLWT ( *; *+; *-; +*)
Words: 1
Cycles: 2
Q Cycle Activity:
Q1
Operands:
Operation:
None
if TBLWT*,
(TABLAT) → Holding Register;
TBLPTR – No Change;
if TBLWT*+,
Q2
Q3
Q4
Decode
No
No
No
operation
operation
operation
(TABLAT) → Holding Register;
(TBLPTR) + 1 → TBLPTR;
if TBLWT*-,
(TABLAT) → Holding Register;
(TBLPTR) – 1 → TBLPTR;
if TBLWT+*,
No
operation
No
operation
(Read
No
operation
No
operation
(Write to
Holding
Register)
TABLAT)
(TBLPTR) + 1 → TBLPTR;
(TABLAT) → Holding Register;
Example 1:
TBLWT *+;
Before Instruction
Status Affected: None
TABLAT
TBLPTR
=
=
0x55
0000
0000
0000
11nn
nn = 0*
= 1*+
= 2*-
= 3+*
Encoding:
0x00A356
HOLDING REGISTER
(0x00A356)
=
0xFF
After Instructions (table write completion)
TABLAT
TBLPTR
HOLDING REGISTER
(0x00A356)
=
=
0x55
0x00A357
Description:
This instruction uses the 3 LSBs of
TBLPTR to determine which of the
8 holding registers the TABLAT is
written to. The holding registers are
used to program the contents of
Program Memory (P.M.). (Refer
to Section 6.0 “Flash Program
Memory” for additional details on
programming Flash memory.)
=
0x55
Example 2:
TBLWT +*;
Before Instruction
TABLAT
TBLPTR
HOLDING REGISTER
(0x01389A)
HOLDING REGISTER
(0x01389B)
=
=
0x34
0x01389A
=
=
0xFF
0xFF
The TBLPTR (a 21-bit pointer) points
to each byte in the program memory.
TBLPTR has a 2-Mbyte address
range. The LSb of the TBLPTR
selects which byte of the program
memory location to access.
After Instruction (table write completion)
TABLAT
=
0x34
TBLPTR
=
0x01389B
HOLDING REGISTER
(0x01389A)
=
=
0xFF
0x34
HOLDING REGISTER
(0x01389B)
TBLPTR[0] = 0:Least Significant
Byte of Program
Memory Word
TBLPTR[0] = 1:Most Significant
Byte of Program
Memory Word
The TBLWT instruction can modify the
value of TBLPTR as follows:
• no change
• post-increment
• post-decrement
• pre-increment
DS39605F-page 230
© 2007 Microchip Technology Inc.
PIC18F1220/1320
TSTFSZ
Test f, skip if 0
XORLW
Exclusive OR literal with W
Syntax:
[ label ] TSTFSZ f [,a]
Syntax:
[ label ] XORLW k
Operands:
0 ≤ f ≤ 255
a ∈ [0,1]
Operands:
0 ≤ k ≤ 255
(W) .XOR. k → W
N, Z
Operation:
Operation:
skip if f = 0
Status Affected:
Encoding:
Status Affected:
Encoding:
None
0000
1010
kkkk
kkkk
0110
011a
ffff
ffff
Description:
The contents of W are XOR’ed
with the 8-bit literal ‘k’. The result
is placed in W.
Description:
If ‘f’ = 0, the next instruction,
fetched during the current
instruction execution is discarded
and a NOPis executed, making this
a two-cycle instruction. If ‘a’ is ‘0’,
the Access Bank will be selected,
overriding the BSR value. If ‘a’ is
‘1’, then the bank will be selected
as per the BSR value (default).
Words:
Cycles:
1
1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
literal ‘k’
Process
Data
Write to W
Words:
Cycles:
1
1(2)
Example:
XORLW 0xAF
= 0xB5
Note: 3 cycles if skip and followed
by a 2-word instruction.
Before Instruction
W
Q Cycle Activity:
Q1
After Instruction
Q2
Q3
Q4
W
=
0x1A
Decode
Read
register ‘f’
Process
Data
No
operation
If skip:
Q1
Q2
Q3
Q4
No
No
No
No
operation
operation
operation
operation
If skip and followed by 2-word instruction:
Q1
Q2
Q3
Q4
No
No
No
No
operation
operation
operation
operation
No
No
No
No
operation
operation
operation
operation
HERE
NZERO
ZERO
TSTFSZ CNT
:
:
Example:
Before Instruction
PC
=
Address (HERE)
After Instruction
If CNT
=
=
≠
=
0x00,
PC
Address (ZERO)
0x00,
If CNT
PC
Address (NZERO)
© 2007 Microchip Technology Inc.
DS39605F-page 231
PIC18F1220/1320
XORWF
Exclusive OR W with f
Syntax:
[ label ] XORWF f [,d [,a]]
Operands:
0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
Operation:
(W) .XOR. (f) → dest
Status Affected:
Encoding:
N, Z
0001
10da
ffff
ffff
Description:
Exclusive OR the contents of W
with register ‘f’. If ‘d’ is ‘0’, the result
is stored in W. If ‘d’ is ‘1’, the result
is stored back in the register ‘f’
(default). If ‘a’ is ‘0’, the Access
Bank will be selected, overriding
the BSR value. If ‘a’ is ‘1’, then the
bank will be selected as per the
BSR value (default).
Words:
Cycles:
1
1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
register ‘f’
Process
Data
Write to
destination
XORWF
REG
Example:
Before Instruction
REG
W
=
=
0xAF
0xB5
After Instruction
REG
W
=
=
0x1A
0xB5
DS39605F-page 232
© 2007 Microchip Technology Inc.
PIC18F1220/1320
21.1 MPLAB Integrated Development
Environment Software
21.0 DEVELOPMENT SUPPORT
The PIC® microcontrollers are supported with a full
range of hardware and software development tools:
The MPLAB IDE software brings an ease of software
development previously unseen in the 8/16-bit micro-
controller market. The MPLAB IDE is a Windows®
operating system-based application that contains:
• Integrated Development Environment
- MPLAB® IDE Software
• Assemblers/Compilers/Linkers
- MPASMTM Assembler
• A single graphical interface to all debugging tools
- Simulator
- MPLAB C18 and MPLAB C30 C Compilers
- MPLINKTM Object Linker/
MPLIBTM Object Librarian
- Programmer (sold separately)
- Emulator (sold separately)
- In-Circuit Debugger (sold separately)
• A full-featured editor with color-coded context
• A multiple project manager
- MPLAB ASM30 Assembler/Linker/Library
• Simulators
- MPLAB SIM Software Simulator
• Emulators
• Customizable data windows with direct edit of
contents
- MPLAB ICE 2000 In-Circuit Emulator
- MPLAB REAL ICE™ In-Circuit Emulator
• In-Circuit Debugger
• High-level source code debugging
• Visual device initializer for easy register
initialization
- MPLAB ICD 2
• Mouse over variable inspection
• Device Programmers
• Drag and drop variables from source to watch
windows
- PICSTART® Plus Development Programmer
- MPLAB PM3 Device Programmer
- PICkit™ 2 Development Programmer
• Extensive on-line help
• Integration of select third party tools, such as
HI-TECH Software C Compilers and IAR
C Compilers
• Low-Cost Demonstration and Development
Boards and Evaluation Kits
The MPLAB IDE allows you to:
• Edit your source files (either assembly or C)
• One touch assemble (or compile) and download
to PIC MCU emulator and simulator tools
(automatically updates all project information)
• Debug using:
- Source files (assembly or C)
- Mixed assembly and C
- Machine code
MPLAB IDE supports multiple debugging tools in a
single development paradigm, from the cost-effective
simulators, through low-cost in-circuit debuggers, to
full-featured emulators. This eliminates the learning
curve when upgrading to tools with increased flexibility
and power.
© 2007 Microchip Technology Inc.
DS39605F-page 233
PIC18F1220/1320
21.2 MPASM Assembler
21.5 MPLAB ASM30 Assembler, Linker
and Librarian
The MPASM Assembler is a full-featured, universal
macro assembler for all PIC MCUs.
MPLAB ASM30 Assembler produces relocatable
machine code from symbolic assembly language for
dsPIC30F devices. MPLAB C30 C Compiler uses the
assembler to produce its object file. The assembler
generates relocatable object files that can then be
archived or linked with other relocatable object files and
archives to create an executable file. Notable features
of the assembler include:
The MPASM Assembler generates relocatable object
files for the MPLINK Object Linker, Intel® standard HEX
files, MAP files to detail memory usage and symbol
reference, absolute LST files that contain source lines
and generated machine code and COFF files for
debugging.
The MPASM Assembler features include:
• Integration into MPLAB IDE projects
• Support for the entire dsPIC30F instruction set
• Support for fixed-point and floating-point data
• Command line interface
• User-defined macros to streamline
assembly code
• Rich directive set
• Conditional assembly for multi-purpose
source files
• Flexible macro language
• MPLAB IDE compatibility
• Directives that allow complete control over the
assembly process
21.6 MPLAB SIM Software Simulator
21.3 MPLAB C18 and MPLAB C30
C Compilers
The MPLAB SIM Software Simulator allows code
development in a PC-hosted environment by simulat-
ing the PIC MCUs and dsPIC® DSCs on an instruction
level. On any given instruction, the data areas can be
examined or modified and stimuli can be applied from
a comprehensive stimulus controller. Registers can be
logged to files for further run-time analysis. The trace
buffer and logic analyzer display extend the power of
the simulator to record and track program execution,
actions on I/O, most peripherals and internal registers.
The MPLAB C18 and MPLAB C30 Code Development
Systems are complete ANSI
C
compilers for
Microchip’s PIC18 family of microcontrollers and the
dsPIC30, dsPIC33 and PIC24 family of digital signal
controllers. These compilers provide powerful integra-
tion capabilities, superior code optimization and ease
of use not found with other compilers.
For easy source level debugging, the compilers provide
symbol information that is optimized to the MPLAB IDE
debugger.
The MPLAB SIM Software Simulator fully supports
symbolic debugging using the MPLAB C18 and
MPLAB C30 C Compilers, and the MPASM and
MPLAB ASM30 Assemblers. The software simulator
offers the flexibility to develop and debug code outside
of the hardware laboratory environment, making it an
excellent, economical software development tool.
21.4 MPLINK Object Linker/
MPLIB Object Librarian
The MPLINK Object Linker combines relocatable
objects created by the MPASM Assembler and the
MPLAB C18 C Compiler. It can link relocatable objects
from precompiled libraries, using directives from a
linker script.
The MPLIB Object Librarian manages the creation and
modification of library files of precompiled code. When
a routine from a library is called from a source file, only
the modules that contain that routine will be linked in
with the application. This allows large libraries to be
used efficiently in many different applications.
The object linker/library features include:
• Efficient linking of single libraries instead of many
smaller files
• Enhanced code maintainability by grouping
related modules together
• Flexible creation of libraries with easy module
listing, replacement, deletion and extraction
DS39605F-page 234
© 2007 Microchip Technology Inc.
PIC18F1220/1320
21.7 MPLAB ICE 2000
High-Performance
21.9 MPLAB ICD 2 In-Circuit Debugger
Microchip’s In-Circuit Debugger, MPLAB ICD 2, is a
powerful, low-cost, run-time development tool,
connecting to the host PC via an RS-232 or high-speed
USB interface. This tool is based on the Flash PIC
MCUs and can be used to develop for these and other
PIC MCUs and dsPIC DSCs. The MPLAB ICD 2 utilizes
the in-circuit debugging capability built into the Flash
devices. This feature, along with Microchip’s In-Circuit
Serial ProgrammingTM (ICSPTM) protocol, offers cost-
effective, in-circuit Flash debugging from the graphical
user interface of the MPLAB Integrated Development
Environment. This enables a designer to develop and
debug source code by setting breakpoints, single step-
ping and watching variables, and CPU status and
peripheral registers. Running at full speed enables
testing hardware and applications in real time. MPLAB
ICD 2 also serves as a development programmer for
selected PIC devices.
In-Circuit Emulator
The MPLAB ICE 2000 In-Circuit Emulator is intended
to provide the product development engineer with a
complete microcontroller design tool set for PIC
microcontrollers. Software control of the MPLAB ICE
2000 In-Circuit Emulator is advanced by the MPLAB
Integrated Development Environment, which allows
editing, building, downloading and source debugging
from a single environment.
The MPLAB ICE 2000 is a full-featured emulator
system with enhanced trace, trigger and data monitor-
ing features. Interchangeable processor modules allow
the system to be easily reconfigured for emulation of
different processors. The architecture of the MPLAB
ICE 2000 In-Circuit Emulator allows expansion to
support new PIC microcontrollers.
The MPLAB ICE 2000 In-Circuit Emulator system has
been designed as a real-time emulation system with
advanced features that are typically found on more
expensive development tools. The PC platform and
Microsoft® Windows® 32-bit operating system were
chosen to best make these features available in a
simple, unified application.
21.10 MPLAB PM3 Device Programmer
The MPLAB PM3 Device Programmer is a universal,
CE compliant device programmer with programmable
voltage verification at VDDMIN and VDDMAX for
maximum reliability. It features a large LCD display
(128 x 64) for menus and error messages and a modu-
lar, detachable socket assembly to support various
package types. The ICSP™ cable assembly is included
as a standard item. In Stand-Alone mode, the MPLAB
PM3 Device Programmer can read, verify and program
PIC devices without a PC connection. It can also set
code protection in this mode. The MPLAB PM3
connects to the host PC via an RS-232 or USB cable.
The MPLAB PM3 has high-speed communications and
optimized algorithms for quick programming of large
memory devices and incorporates an SD/MMC card for
file storage and secure data applications.
21.8 MPLAB REAL ICE In-Circuit
Emulator System
MPLAB REAL ICE In-Circuit Emulator System is
Microchip’s next generation high-speed emulator for
Microchip Flash DSC® and MCU devices. It debugs and
programs PIC® and dsPIC® Flash microcontrollers with
the easy-to-use, powerful graphical user interface of the
MPLAB Integrated Development Environment (IDE),
included with each kit.
The MPLAB REAL ICE probe is connected to the design
engineer’s PC using a high-speed USB 2.0 interface and
is connected to the target with either a connector
compatible with the popular MPLAB ICD 2 system
(RJ11) or with the new high speed, noise tolerant, low-
voltage differential signal (LVDS) interconnection
(CAT5).
MPLAB REAL ICE is field upgradeable through future
firmware downloads in MPLAB IDE. In upcoming
releases of MPLAB IDE, new devices will be supported,
and new features will be added, such as software break-
points and assembly code trace. MPLAB REAL ICE
offers significant advantages over competitive emulators
including low-cost, full-speed emulation, real-time
variable watches, trace analysis, complex breakpoints, a
ruggedized probe interface and long (up to three meters)
interconnection cables.
© 2007 Microchip Technology Inc.
DS39605F-page 235
PIC18F1220/1320
21.11 PICSTART Plus Development
Programmer
21.13 Demonstration, Development and
Evaluation Boards
The PICSTART Plus Development Programmer is an
easy-to-use, low-cost, prototype programmer. It
connects to the PC via a COM (RS-232) port. MPLAB
Integrated Development Environment software makes
using the programmer simple and efficient. The
PICSTART Plus Development Programmer supports
most PIC devices in DIP packages up to 40 pins.
Larger pin count devices, such as the PIC16C92X and
PIC17C76X, may be supported with an adapter socket.
The PICSTART Plus Development Programmer is CE
compliant.
A wide variety of demonstration, development and
evaluation boards for various PIC MCUs and dsPIC
DSCs allows quick application development on fully func-
tional systems. Most boards include prototyping areas for
adding custom circuitry and provide application firmware
and source code for examination and modification.
The boards support a variety of features, including LEDs,
temperature sensors, switches, speakers, RS-232
interfaces, LCD displays, potentiometers and additional
EEPROM memory.
The demonstration and development boards can be
used in teaching environments, for prototyping custom
circuits and for learning about various microcontroller
applications.
21.12 PICkit 2 Development Programmer
The PICkit™ 2 Development Programmer is a low-cost
programmer and selected Flash device debugger with
an easy-to-use interface for programming many of
Microchip’s baseline, mid-range and PIC18F families of
Flash memory microcontrollers. The PICkit 2 Starter Kit
includes a prototyping development board, twelve
sequential lessons, software and HI-TECH’s PICC™
Lite C compiler, and is designed to help get up to speed
quickly using PIC® microcontrollers. The kit provides
everything needed to program, evaluate and develop
applications using Microchip’s powerful, mid-range
Flash memory family of microcontrollers.
In addition to the PICDEM™ and dsPICDEM™ demon-
stration/development board series of circuits, Microchip
has a line of evaluation kits and demonstration software
®
for analog filter design, KEELOQ security ICs, CAN,
IrDA®, PowerSmart® battery management, SEEVAL®
evaluation system, Sigma-Delta ADC, flow rate
sensing, plus many more.
Check the Microchip web page (www.microchip.com)
and the latest “Product Selector Guide” (DS00148) for
the complete list of demonstration, development and
evaluation kits.
DS39605F-page 236
© 2007 Microchip Technology Inc.
PIC18F1220/1320
22.0 ELECTRICAL CHARACTERISTICS
(†)
Absolute Maximum Ratings
Ambient temperature under bias.............................................................................................................-40°C to +125°C
Storage temperature .............................................................................................................................. -65°C to +150°C
Voltage on any pin with respect to VSS (except VDD, MCLR and RA4) .......................................... -0.3V to (VDD + 0.3V)
Voltage on VDD with respect to VSS ......................................................................................................... -0.3V to +5.5V
Voltage on MCLR with respect to VSS (Note 2) ......................................................................................... 0V to +13.25V
Voltage on RA4 with respect to Vss............................................................................................................... 0V to +8.5V
Total power dissipation (Note 1) ...............................................................................................................................1.0W
Maximum current out of VSS pin ...........................................................................................................................300 mA
Maximum current into VDD pin ..............................................................................................................................250 mA
Input clamp current, IIK (VI < 0 or VI > VDD)...................................................................................................................... 20 mA
Output clamp current, IOK (VO < 0 or VO > VDD) .............................................................................................................. 20 mA
Maximum output current sunk by any I/O pin..........................................................................................................25 mA
Maximum output current sourced by any I/O pin ....................................................................................................25 mA
Maximum current sunk by all ports .......................................................................................................................200 mA
Maximum current sourced by all ports ..................................................................................................................200 mA
Note 1: Power dissipation is calculated as follows:
Pdis = VDD x {IDD – ∑ IOH} + ∑ {(VDD – VOH) x IOH} + ∑(VOL x IOL)
2: Voltage spikes below VSS at the MCLR/VPP pin, inducing currents greater than 80 mA, may cause latch-up.
Thus, a series resistor of 50-100Ω should be used when applying a “low” level to the MCLR/VPP pin, rather
than pulling this pin directly to VSS.
† NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at those or any other conditions above those
indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for
extended periods may affect device reliability.
© 2007 Microchip Technology Inc.
DS39605F-page 237
PIC18F1220/1320
FIGURE 22-1:
PIC18F1220/1320 VOLTAGE-FREQUENCY GRAPH (INDUSTRIAL)
6.0V
5.5V
5.0V
4.5V
4.0V
PIC18F1X20
4.2V
3.5V
3.0V
2.5V
2.0V
40 MHz
Frequency
FIGURE 22-2:
PIC18LF1220/1320 VOLTAGE-FREQUENCY GRAPH (INDUSTRIAL)
6.0V
5.5V
5.0V
4.5V
4.0V
PIC18LF1X20
4.2V
3.5V
3.0V
2.5V
2.0V
40 MHz
4 MHz
Frequency
FMAX = (16.36 MHz/V) (VDDAPPMIN – 2.0V) + 4 MHz
Note: VDDAPPMIN is the minimum voltage of the PIC® device in the application.
DS39605F-page 238
© 2007 Microchip Technology Inc.
PIC18F1220/1320
FIGURE 22-3:
PIC18F1220/1320 VOLTAGE-FREQUENCY GRAPH (EXTENDED)
6.0V
5.5V
5.0V
4.5V
4.0V
PIC18F1X20-E
4.2V
3.5V
3.0V
2.5V
2.0V
25 MHz
Frequency
© 2007 Microchip Technology Inc.
DS39605F-page 239
PIC18F1220/1320
22.1 DC Characteristics: Supply Voltage
PIC18F1220/1320 (Industrial)
PIC18LF1220/1320 (Industrial)
PIC18LF1220/1320
Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C ≤ TA ≤ +85°C for industrial
(Industrial)
Standard Operating Conditions (unless otherwise stated)
PIC18F1220/1320
Operating temperature
-40°C ≤ TA ≤ +85°C for industrial
-40°C ≤ TA ≤ +125°C for extended
(Industrial, Extended)
Param
Symbol
No.
Characteristic
Supply Voltage
Min
Typ
Max Units
Conditions
VDD
D001
PIC18LF1220/1320 2.0
PIC18F1220/1320 4.2
—
—
—
5.5
5.5
—
V
V
V
HS, XT, RC and LP Oscillator mode
D002
D003
D004
VDR
RAM Data Retention
1.5
(1)
Voltage
VPOR
SVDD
VBOR
VDD Start Voltage to ensure
—
—
—
0.7
—
V
See Section 4.1 “Power-on Reset (POR)”
for details.
internal Power-on Reset signal
VDD Rise Rate to ensure
0.05
V/ms See Section 4.1 “Power-on Reset (POR)”
internal Power-on Reset signal
for details.
Brown-out Reset Voltage
D005D
PIC18LF1220/1320 Industrial Low Voltage (-10°C to +85°C)
BORV1:BORV0 = 11
BORV1:BORV0 = 10
BORV1:BORV0 = 01
BORV1:BORV0 = 00
N/A
2.50
3.88
4.18
N/A
2.72
4.22
4.54
N/A
2.94
4.56
4.90
V
V
V
V
Reserved
(Note 2)
(Note 2)
D005F
PIC18LF1220/1320 Industrial Low Voltage (-40°C to -10°C)
BORV1:BORV0 = 11
BORV1:BORV0 = 10
BORV1:BORV0 = 01
BORV1:BORV0 = 00
N/A
2.34
3.63
3.90
N/A
2.72
4.22
4.54
N/A
3.10
4.81
5.18
V
V
V
V
Reserved
(Note 2)
(Note 2)
D005G
D005H
D005J
PIC18F1220/1320 Industrial (-10°C to +85°C)
BORV1:BORV0 = 1x
BORV1:BORV0 = 01
BORV1:BORV0 = 00
N/A
3.88
4.18
N/A
4.22
4.54
N/A
4.56
4.90
V
V
V
Reserved
(Note 2)
(Note 2)
PIC18F1220/1320 Industrial (-40°C to -10°C)
BORV1:BORV0 = 1x
BORV1:BORV0 = 01
BORV1:BORV0 = 00
N/A
N/A
3.90
N/A
N/A
4.54
N/A
N/A
5.18
V
V
V
Reserved
Reserved
(Note 2)
PIC18F1220/1320 Extended (-10°C to +85°C)
BORV1:BORV0 = 1x
BORV1:BORV0 = 01
BORV1:BORV0 = 00
N/A
3.88
4.18
N/A
4.22
4.54
N/A
4.56
4.90
V
V
V
Reserved
(Note 3)
(Note 3)
D005K
PIC18F1220/1320 Extended (-40°C to -10°C, +85°C to +125°C)
BORV1:BORV0 = 1x
BORV1:BORV0 = 01
BORV1:BORV0 = 00
N/A
N/A
3.90
N/A
N/A
4.54
N/A
N/A
5.18
V
V
V
Reserved
Reserved
(Note 3)
Legend:
Shading of rows is to assist in readability of the table.
Note 1: This is the limit to which VDD can be lowered in Sleep mode, or during a device Reset, without losing RAM data.
2: When BOR is on and BORV<1:0> = 0x, the device will operate correctly at 40 MHz for any VDD at which the BOR allows
execution (low-voltage and industrial devices only).
3: When BOR is on and BORV<1:0> = 0x, the device will operate correctly at 25 MHz for any VDD at which the BOR allows
execution (extended devices only).
DS39605F-page 240
© 2007 Microchip Technology Inc.
PIC18F1220/1320
22.2 DC Characteristics: Power-Down and Supply Current
PIC18F1220/1320 (Industrial)
PIC18LF1220/1320 (Industrial)
PIC18LF1220/1320
Standard Operating Conditions (unless otherwise stated)
(Industrial)
Operating temperature
-40°C ≤ TA ≤ +85°C for industrial
Standard Operating Conditions (unless otherwise stated)
PIC18F1220/1320
Operating temperature
-40°C ≤ TA ≤ +85°C for industrial
-40°C ≤ TA ≤ +125°C for extended
(Industrial, Extended)
Param
No.
Device
Power-Down Current (IPD)
Typ
Max Units
Conditions
(1)
PIC18LF1220/1320 0.1
0.5
0.5
1.9
0.5
0.5
1.9
2.0
2.0
6.5
50
μA
μA
μA
μA
μA
μA
μA
μA
μA
μA
-40°C
+25°C
+85°C
-40°C
VDD = 2.0V,
(Sleep mode)
0.1
0.2
PIC18LF1220/1320 0.1
VDD = 3.0V,
(Sleep mode)
0.1
+ 25°C
+85°C
-40°C
0.3
All devices 0.1
0.1
0.4
+25°C
+85°C
+125°C
VDD = 5.0V,
(Sleep mode)
Extended devices 11.2
(2,3)
Supply Current (IDD)
PIC18LF1220/1320
8
40
40
40
68
68
68
80
80
80
80
μA
μA
μA
μA
μA
μA
μA
μA
μA
μA
-40°C
9
+25°C
+85°C
-40°C
VDD = 2.0V
VDD = 3.0V
11
25
25
20
55
55
50
50
PIC18LF1220/1320
All devices
FOSC = 31 kHz
(RC_RUN mode,
+25°C
+85°C
-40°C
Internal oscillator source)
+25°C
+85°C
+125°C
VDD = 5.0V
Extended devices
Legend:
Shading of rows is to assist in readability of the table.
Note 1: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with
the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS and all features that add delta
current disabled (such as WDT, Timer1 Oscillator, BOR, etc.).
2: The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading
and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on
the current consumption.
The test conditions for all IDD measurements in active operation mode are:
OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD;
MCLR = VDD; WDT enabled/disabled as specified.
3: For RC oscillator configurations, current through REXT is not included. The current through the resistor can be estimated
by the formula Ir = VDD/2REXT (mA) with REXT in kΩ.
4: Standard low-cost 32 kHz crystals have an operating temperature range of -10°C to +70°C. Extended temperature
crystals are available at a much higher cost.
© 2007 Microchip Technology Inc.
DS39605F-page 241
PIC18F1220/1320
22.2 DC Characteristics: Power-Down and Supply Current
PIC18F1220/1320 (Industrial)
PIC18LF1220/1320 (Industrial) (Continued)
PIC18LF1220/1320
Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C ≤ TA ≤ +85°C for industrial
(Industrial)
Standard Operating Conditions (unless otherwise stated)
PIC18F1220/1320
Operating temperature
-40°C ≤ TA ≤ +85°C for industrial
-40°C ≤ TA ≤ +125°C for extended
(Industrial, Extended)
Param
No.
Device
Supply Current (IDD)
Typ
Max Units
Conditions
(2,3)
PIC18LF1220/1320 140
220
220
220
330
330
330
550
550
550
650
600
600
600
900
900
900
1.8
μA
μA
μA
μA
μA
μA
μA
μA
μA
μA
μA
μA
μA
μA
μA
μA
mA
mA
mA
mA
-40°C
145
+25°C
+85°C
-40°C
+25°C
+85°C
-40°C
+25°C
+85°C
+125°C
-40°C
+25°C
+85°C
-40°C
+25°C
+85°C
-40°C
VDD = 2.0V
VDD = 3.0V
155
PIC18LF1220/1320 215
FOSC = 1 MHz
(RC_RUN mode,
225
235
Internal oscillator source)
All devices 385
390
VDD = 5.0V
405
Extended devices 410
PIC18LF1220/1320 410
425
VDD = 2.0V
VDD = 3.0V
435
PIC18LF1220/1320 650
FOSC = 4 MHz
(RC_RUN mode,
670
680
Internal oscillator source)
All devices 1.2
1.2
1.2
1.8
+25°C
+85°C
+125°C
VDD = 5.0V
1.8
Extended devices 1.2
1.8
Legend:
Shading of rows is to assist in readability of the table.
Note 1: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with
the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS and all features that add delta
current disabled (such as WDT, Timer1 Oscillator, BOR, etc.).
2: The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading
and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on
the current consumption.
The test conditions for all IDD measurements in active operation mode are:
OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD;
MCLR = VDD; WDT enabled/disabled as specified.
3: For RC oscillator configurations, current through REXT is not included. The current through the resistor can be estimated
by the formula Ir = VDD/2REXT (mA) with REXT in kΩ.
4: Standard low-cost 32 kHz crystals have an operating temperature range of -10°C to +70°C. Extended temperature
crystals are available at a much higher cost.
DS39605F-page 242
© 2007 Microchip Technology Inc.
PIC18F1220/1320
22.2 DC Characteristics: Power-Down and Supply Current
PIC18F1220/1320 (Industrial)
PIC18LF1220/1320 (Industrial) (Continued)
PIC18LF1220/1320
Standard Operating Conditions (unless otherwise stated)
(Industrial)
Operating temperature
-40°C ≤ TA ≤ +85°C for industrial
Standard Operating Conditions (unless otherwise stated)
PIC18F1220/1320
Operating temperature
-40°C ≤ TA ≤ +85°C for industrial
-40°C ≤ TA ≤ +125°C for extended
(Industrial, Extended)
Param
No.
Device
Supply Current (IDD)
Typ
Max Units
Conditions
(2,3)
PIC18LF1220/1320 4.7
8
μA
μA
μA
μA
μA
μA
μA
μA
μA
μA
μA
μA
μA
μA
μA
μA
μA
μA
μA
μA
-40°C
5.0
8
+25°C
+85°C
-40°C
+25°C
+85°C
-40°C
+25°C
+85°C
+125°C
-40°C
+25°C
+85°C
-40°C
+25°C
+85°C
-40°C
+25°C
+85°C
+125°C
VDD = 2.0V
VDD = 3.0V
5.8
11
PIC18LF1220/1320 7.0
11
FOSC = 31 kHz
(RC_IDLE mode,
7.8
8.7
11
15
Internal oscillator source)
All devices
12
14
14
25
75
85
95
16
16
VDD = 5.0V
22
Extended devices
PIC18LF1220/1320
75
150
150
150
180
180
180
380
380
380
435
VDD = 2.0V
VDD = 3.0V
PIC18LF1220/1320 110
FOSC = 1 MHz
(RC_IDLE mode,
125
135
All devices 180
195
Internal oscillator source)
VDD = 5.0V
200
Extended devices 350
Legend:
Shading of rows is to assist in readability of the table.
Note 1: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with
the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS and all features that add delta
current disabled (such as WDT, Timer1 Oscillator, BOR, etc.).
2: The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading
and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on
the current consumption.
The test conditions for all IDD measurements in active operation mode are:
OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD;
MCLR = VDD; WDT enabled/disabled as specified.
3: For RC oscillator configurations, current through REXT is not included. The current through the resistor can be estimated
by the formula Ir = VDD/2REXT (mA) with REXT in kΩ.
4: Standard low-cost 32 kHz crystals have an operating temperature range of -10°C to +70°C. Extended temperature
crystals are available at a much higher cost.
© 2007 Microchip Technology Inc.
DS39605F-page 243
PIC18F1220/1320
22.2 DC Characteristics: Power-Down and Supply Current
PIC18F1220/1320 (Industrial)
PIC18LF1220/1320 (Industrial) (Continued)
PIC18LF1220/1320
Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C ≤ TA ≤ +85°C for industrial
(Industrial)
Standard Operating Conditions (unless otherwise stated)
PIC18F1220/1320
Operating temperature
-40°C ≤ TA ≤ +85°C for industrial
-40°C ≤ TA ≤ +125°C for extended
(Industrial, Extended)
Param
No.
Device
Supply Current (IDD)
Typ
Max Units
Conditions
(2,3)
PIC18LF1220/1320 140
275
275
275
375
375
375
800
800
800
800
250
250
250
350
350
350
1.0
μA
μA
μA
μA
μA
μA
μA
μA
μA
μA
μA
μA
μA
μA
μA
μA
mA
mA
mA
mA
-40°C
140
+25°C
+85°C
-40°C
+25°C
+85°C
-40°C
+25°C
+85°C
+125°C
-40°C
+25°C
+85°C
-40°C
+25°C
+85°C
-40°C
VDD = 2.0V
VDD = 3.0V
150
PIC18LF1220/1320 220
FOSC = 4 MHz
(RC_IDLE mode,
220
220
Internal oscillator source)
All devices 390
400
VDD = 5.0V
380
Extended devices 410
PIC18LF1220/1320 150
150
VDD = 2.0V
VDD = 3.0V
160
PIC18LF1220/1320 340
FOSC = 1 MHZ
(PRI_RUN mode,
EC oscillator)
300
280
All devices 0.72
0.63
1.0
+25°C
+85°C
+125°C
VDD = 5.0V
0.58
1.0
Extended devices 0.53
1.0
Legend:
Shading of rows is to assist in readability of the table.
Note 1: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with
the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS and all features that add delta
current disabled (such as WDT, Timer1 Oscillator, BOR, etc.).
2: The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading
and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on
the current consumption.
The test conditions for all IDD measurements in active operation mode are:
OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD;
MCLR = VDD; WDT enabled/disabled as specified.
3: For RC oscillator configurations, current through REXT is not included. The current through the resistor can be estimated
by the formula Ir = VDD/2REXT (mA) with REXT in kΩ.
4: Standard low-cost 32 kHz crystals have an operating temperature range of -10°C to +70°C. Extended temperature
crystals are available at a much higher cost.
DS39605F-page 244
© 2007 Microchip Technology Inc.
PIC18F1220/1320
22.2 DC Characteristics: Power-Down and Supply Current
PIC18F1220/1320 (Industrial)
PIC18LF1220/1320 (Industrial) (Continued)
PIC18LF1220/1320
Standard Operating Conditions (unless otherwise stated)
(Industrial)
Operating temperature
-40°C ≤ TA ≤ +85°C for industrial
Standard Operating Conditions (unless otherwise stated)
PIC18F1220/1320
Operating temperature
-40°C ≤ TA ≤ +85°C for industrial
-40°C ≤ TA ≤ +125°C for extended
(Industrial, Extended)
Param
No.
Device
Supply Current (IDD)
Typ
Max Units
Conditions
(2,3)
PIC18LF1220/1320 415
600
600
600
1.0
1.0
1.0
2.0
2.0
2.0
2.0
9.0
10.0
μA
μA
-40°C
425
+25°C
+85°C
-40°C
VDD = 2.0V
VDD = 3.0V
435
μA
PIC18LF1220/1320 0.87
mA
mA
mA
mA
mA
mA
mA
mA
mA
FOSC = 4 MHz
(PRI_RUN mode,
EC oscillator)
0.75
+25°C
+85°C
-40°C
0.75
All devices 1.6
1.6
+25°C
+85°C
+125°C
+125°C
+125°C
VDD = 5.0V
1.5
Extended devices 1.5
Extended devices 6.3
9.7
VDD = 4.2V
VDD = 5.0V
FOSC = 25 MHz
(PRI_RUN mode,
EC oscillator)
All devices 9.4
12
12
12
15
15
15
mA
mA
mA
mA
mA
mA
-40°C
+25°C
+85°C
-40°C
+25°C
+85°C
9.5
VDD = 4.2V
VDD = 5.0V
FOSC = 40 MHZ
(PRI_RUN mode,
EC oscillator)
9.6
All devices 11.9
12.1
12.2
Legend:
Shading of rows is to assist in readability of the table.
Note 1: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with
the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS and all features that add delta
current disabled (such as WDT, Timer1 Oscillator, BOR, etc.).
2: The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading
and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on
the current consumption.
The test conditions for all IDD measurements in active operation mode are:
OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD;
MCLR = VDD; WDT enabled/disabled as specified.
3: For RC oscillator configurations, current through REXT is not included. The current through the resistor can be estimated
by the formula Ir = VDD/2REXT (mA) with REXT in kΩ.
4: Standard low-cost 32 kHz crystals have an operating temperature range of -10°C to +70°C. Extended temperature
crystals are available at a much higher cost.
© 2007 Microchip Technology Inc.
DS39605F-page 245
PIC18F1220/1320
22.2 DC Characteristics: Power-Down and Supply Current
PIC18F1220/1320 (Industrial)
PIC18LF1220/1320 (Industrial) (Continued)
PIC18LF1220/1320
Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C ≤ TA ≤ +85°C for industrial
(Industrial)
Standard Operating Conditions (unless otherwise stated)
PIC18F1220/1320
Operating temperature
-40°C ≤ TA ≤ +85°C for industrial
-40°C ≤ TA ≤ +125°C for extended
(Industrial, Extended)
Param
No.
Device
Supply Current (IDD)
Typ
Max Units
Conditions
(2,3)
PIC18LF1220/1320
35
35
35
55
50
60
50
μA
μA
μA
μA
μA
μA
μA
μA
μA
μA
μA
μA
μA
μA
μA
μA
μA
μA
μA
μA
mA
mA
-40°C
50
+25°C
+85°C
-40°C
VDD = 2.0V
VDD = 3.0V
60
PIC18LF1220/1320
80
FOSC = 1 MHz
(PRI_IDLE mode,
EC oscillator)
80
+25°C
+85°C
-40°C
100
150
150
150
300
180
180
180
280
280
280
525
525
525
800
3.0
All devices 105
110
+25°C
+85°C
+125°C
-40°C
VDD = 5.0V
115
Extended devices 125
PIC18LF1220/1320 135
140
+25°C
+85°C
-40°C
VDD = 2.0V
VDD = 3.0V
140
PIC18LF1220/1320 215
FOSC = 4 MHz
(PRI_IDLE mode,
EC oscillator)
225
+25°C
+85°C
-40°C
230
All devices 410
420
430
+25°C
+85°C
+125°C
+125°C
+125°C
VDD = 5.0V
Extended devices 450
Extended devices 2.2
2.7
VDD = 4.2V
VDD = 5.0V
FOSC = 25 MHz
(PRI_IDLE mode,
EC oscillator)
3.5
Legend:
Shading of rows is to assist in readability of the table.
Note 1: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with
the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS and all features that add delta
current disabled (such as WDT, Timer1 Oscillator, BOR, etc.).
2: The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading
and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on
the current consumption.
The test conditions for all IDD measurements in active operation mode are:
OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD;
MCLR = VDD; WDT enabled/disabled as specified.
3: For RC oscillator configurations, current through REXT is not included. The current through the resistor can be estimated
by the formula Ir = VDD/2REXT (mA) with REXT in kΩ.
4: Standard low-cost 32 kHz crystals have an operating temperature range of -10°C to +70°C. Extended temperature
crystals are available at a much higher cost.
DS39605F-page 246
© 2007 Microchip Technology Inc.
PIC18F1220/1320
22.2 DC Characteristics: Power-Down and Supply Current
PIC18F1220/1320 (Industrial)
PIC18LF1220/1320 (Industrial) (Continued)
PIC18LF1220/1320
Standard Operating Conditions (unless otherwise stated)
(Industrial)
Operating temperature
-40°C ≤ TA ≤ +85°C for industrial
Standard Operating Conditions (unless otherwise stated)
PIC18F1220/1320
Operating temperature
-40°C ≤ TA ≤ +85°C for industrial
-40°C ≤ TA ≤ +125°C for extended
(Industrial, Extended)
Param
No.
Device
Supply Current (IDD)
Typ
Max Units
Conditions
(2,3)
All devices 3.2
4.1
4.1
4.1
5.1
5.1
5.1
9
mA
mA
mA
mA
mA
mA
μA
μA
μA
μA
μA
μA
μA
μA
μA
-40°C
3.2
+25°C
+85°C
-40°C
+25°C
+85°C
-10°C
+25°C
+70°C
-10°C
+25°C
+70°C
-10°C
+25°C
+70°C
VDD = 4.2 V
VDD = 5.0V
VDD = 2.0V
VDD = 3.0V
VDD = 5.0V
FOSC = 40 MHz
(PRI_IDLE mode,
EC oscillator)
3.3
All devices 4.0
4.1
4.1
PIC18LF1220/1320 5.1
5.8
9
7.9
11
12
12
14
20
20
25
PIC18LF1220/1320 7.9
(4)
FOSC = 32 kHz
8.9
(SEC_RUN mode,
Timer1 as clock)
10.5
All devices 12.5
16.3
18.4
Legend:
Shading of rows is to assist in readability of the table.
Note 1: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with
the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS and all features that add delta
current disabled (such as WDT, Timer1 Oscillator, BOR, etc.).
2: The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading
and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on
the current consumption.
The test conditions for all IDD measurements in active operation mode are:
OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD;
MCLR = VDD; WDT enabled/disabled as specified.
3: For RC oscillator configurations, current through REXT is not included. The current through the resistor can be estimated
by the formula Ir = VDD/2REXT (mA) with REXT in kΩ.
4: Standard low-cost 32 kHz crystals have an operating temperature range of -10°C to +70°C. Extended temperature
crystals are available at a much higher cost.
© 2007 Microchip Technology Inc.
DS39605F-page 247
PIC18F1220/1320
22.2 DC Characteristics: Power-Down and Supply Current
PIC18F1220/1320 (Industrial)
PIC18LF1220/1320 (Industrial) (Continued)
PIC18LF1220/1320
Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C ≤ TA ≤ +85°C for industrial
(Industrial)
Standard Operating Conditions (unless otherwise stated)
PIC18F1220/1320
Operating temperature
-40°C ≤ TA ≤ +85°C for industrial
-40°C ≤ TA ≤ +125°C for extended
(Industrial, Extended)
Param
No.
Device
Supply Current (IDD)
Typ
Max Units
Conditions
(2,3)
PIC18LF1220/1320 9.2
15
15
18
30
30
35
80
80
80
μA
μA
μA
μA
μA
μA
μA
μA
μA
-10°C
9.6
+25°C
+70°C
-10°C
+25°C
+70°C
-10°C
+25°C
+70°C
VDD = 2.0V
VDD = 3.0V
VDD = 5.0V
12.7
PIC18LF1220/1320
All devices
22
21
20
50
45
45
(4)
FOSC = 32 kHz
(SEC_IDLE mode,
Timer1 as clock)
Legend:
Shading of rows is to assist in readability of the table.
Note 1: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with
the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS and all features that add delta
current disabled (such as WDT, Timer1 Oscillator, BOR, etc.).
2: The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading
and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on
the current consumption.
The test conditions for all IDD measurements in active operation mode are:
OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD;
MCLR = VDD; WDT enabled/disabled as specified.
3: For RC oscillator configurations, current through REXT is not included. The current through the resistor can be estimated
by the formula Ir = VDD/2REXT (mA) with REXT in kΩ.
4: Standard low-cost 32 kHz crystals have an operating temperature range of -10°C to +70°C. Extended temperature
crystals are available at a much higher cost.
DS39605F-page 248
© 2007 Microchip Technology Inc.
PIC18F1220/1320
22.2 DC Characteristics: Power-Down and Supply Current
PIC18F1220/1320 (Industrial)
PIC18LF1220/1320 (Industrial) (Continued)
PIC18LF1220/1320
Standard Operating Conditions (unless otherwise stated)
(Industrial)
Operating temperature
-40°C ≤ TA ≤ +85°C for industrial
Standard Operating Conditions (unless otherwise stated)
PIC18F1220/1320
Operating temperature
-40°C ≤ TA ≤ +85°C for industrial
-40°C ≤ TA ≤ +125°C for extended
(Industrial, Extended)
Param
No.
Device
Typ
Max Units
Conditions
Module Differential Currents (ΔIWDT, ΔIBOR, ΔILVD, ΔIOSCB, ΔIAD)
D022
(ΔIWDT)
Watchdog Timer 1.5
4.0
4.0
μA
μA
μA
μA
μA
μA
μA
μA
μA
μA
μA
μA
μA
μA
μA
μA
μA
μA
μA
μA
μA
μA
μA
μA
μA
μA
-40°C
+25°C
2.2
3.1
2.5
3.3
4.7
3.7
4.5
6.1
VDD = 2.0V
VDD = 3.0V
VDD = 5.0V
5.0
+85°C
6.0
-40°C
6.0
+25°C
7.0
+85°C
10.0
10.0
13.0
35.0
45.0
25.0
35.0
45.0
3.5
-40°C
+25°C
+85°C
D022A
(ΔIBOR)
Brown-out Reset
19
24
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C
VDD = 3.0V
VDD = 5.0V
VDD = 2.0V
VDD = 3.0V
VDD = 5.0V
D022B
(ΔILVD)
Low-Voltage Detect 8.5
16
20
D025
(ΔIOSCB)
Timer1 Oscillator 1.7
(4)
(4)
1.8
3.5
+25°C
VDD = 2.0V
VDD = 3.0V
VDD = 5.0V
32 kHz on Timer1
32 kHz on Timer1
32 kHz on Timer1
2.1
4.5
+85°C
2.2
4.5
-40°C
2.6
4.5
+25°C
2.8
5.5
+85°C
3.0
6.0
-40°C
(4)
3.3
6.0
+25°C
3.6
7.0
+85°C
D026
(ΔIAD)
A/D Converter 1.0
3.0
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
VDD = 2.0V
VDD = 3.0V
VDD = 5.0V
VDD = 5.0V
1.0
2.0
1.0
4.0
A/D on, not converting
10.0
8.0
μA -40°C to +125°C
Legend:
Shading of rows is to assist in readability of the table.
Note 1: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with
the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS and all features that add delta
current disabled (such as WDT, Timer1 Oscillator, BOR, etc.).
2: The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading
and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on
the current consumption.
The test conditions for all IDD measurements in active operation mode are:
OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD;
MCLR = VDD; WDT enabled/disabled as specified.
3: For RC oscillator configurations, current through REXT is not included. The current through the resistor can be estimated
by the formula Ir = VDD/2REXT (mA) with REXT in kΩ.
4: Standard low-cost 32 kHz crystals have an operating temperature range of -10°C to +70°C. Extended temperature
crystals are available at a much higher cost.
© 2007 Microchip Technology Inc.
DS39605F-page 249
PIC18F1220/1320
22.3 DC Characteristics: PIC18F1220/1320 (Industrial)
PIC18LF1220/1320 (Industrial)
Standard Operating Conditions (unless otherwise stated)
DC CHARACTERISTICS
Operating temperature -40°C ≤ TA ≤ +85°C for industrial
-40°C ≤ TA ≤ +125°C for extended
Param
Symbol
No.
Characteristic
Min
Max
Units
Conditions
VIL
Input Low Voltage
I/O ports:
with TTL buffer
D030
VSS
—
0.15 VDD
0.8
V
V
V
V
V
VDD < 4.5V
D030A
D031
4.5V ≤ VDD ≤ 5.5V
with Schmitt Trigger buffer
MCLR
VSS
VSS
VSS
0.2 VDD
0.2 VDD
0.3 VDD
D032
D032A
OSC1(inXT, HSandLPmodes)
and T1OSI
D033
OSC1 (in RC and EC mode)(1)
Input High Voltage
I/O ports:
VSS
0.2 VDD
V
VIH
D040
with TTL buffer
0.25 VDD + 0.8V
2.0
VDD
VDD
V
V
VDD < 4.5V
D040A
4.5V ≤ VDD ≤ 5.5V
D041
D042
D042A
with Schmitt Trigger buffer
MCLR, OSC1 (EC mode)
0.8 VDD
0.8 VDD
1.6 VDD
VDD
VDD
VDD
V
V
V
OSC1 (in XT, HS and LP modes)
and T1OSI
D043
D060
OSC1 (RC mode)(1)
Input Leakage Current(2,3)
I/O ports
0.9 VDD
—
VDD
1
V
IIL
μA VSS ≤ VPIN ≤ VDD,
Pin at high-impedance
D061
D063
MCLR
—
—
5
5
μA VSS ≤ VPIN ≤ VDD
μA VSS ≤ VPIN ≤ VDD
OSC1
IPU
Weak Pull-up Current
PORTB weak pull-up current
D070
IPURB
50
400
μA VDD = 5V, VPIN = VSS
Note 1: In RC oscillator configuration, the OSC1/CLKI pin is a Schmitt Trigger input. It is not recommended that the
PIC® device be driven with an external clock while in RC mode.
2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified
levels represent normal operating conditions. Higher leakage current may be measured at different input
voltages.
3: Negative current is defined as current sourced by the pin.
4: Parameter is characterized but not tested.
DS39605F-page 250
© 2007 Microchip Technology Inc.
PIC18F1220/1320
22.3 DC Characteristics: PIC18F1220/1320 (Industrial)
PIC18LF1220/1320 (Industrial) (Continued)
Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C ≤ TA ≤ +85°C for industrial
-40°C ≤ TA ≤ +125°C for extended
DC CHARACTERISTICS
Param
Symbol
No.
Characteristic
Min
Max
Units
Conditions
VOL
VOH
VOD
Output Low Voltage
D080
D083
I/O ports
—
—
0.6
0.6
V
V
IOL = 8.5 mA, VDD = 4.5V,
-40°C to +85°C
OSC2/CLKO
(RC mode)
Output High Voltage(3)
IOL = 1.6 mA, VDD = 4.5V,
-40°C to +85°C
D090
D092
D150
I/O ports
VDD – 0.7
VDD – 0.7
—
—
—
V
V
V
IOH = -3.0 mA, VDD = 4.5V,
-40°C to +85°C
OSC2/CLKO
(RC mode)
IOH = -1.3 mA, VDD = 4.5V,
-40°C to +85°C
RA4 pin
Open-Drain High Voltage
8.5
Capacitive Loading Specs
on Output Pins
D100(4)
—
COSC2 OSC2 pin
15
pF In XT, HS and LP modes
when external clock is
used to drive OSC1
D101
D102
CIO
CB
All I/O pins and OSC2
(in RC mode)
—
—
50
pF To meet the AC timing
specifications
pF In I2C mode
SCL, SDA
400
Note 1: In RC oscillator configuration, the OSC1/CLKI pin is a Schmitt Trigger input. It is not recommended that the
PIC® device be driven with an external clock while in RC mode.
2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified
levels represent normal operating conditions. Higher leakage current may be measured at different input
voltages.
3: Negative current is defined as current sourced by the pin.
4: Parameter is characterized but not tested.
© 2007 Microchip Technology Inc.
DS39605F-page 251
PIC18F1220/1320
TABLE 22-1: MEMORY PROGRAMMING REQUIREMENTS
Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C ≤ TA ≤ +85°C for industrial
DC CHARACTERISTICS
Param
Sym
No.
Characteristic
Min
Typ†
Max
Units
Conditions
Internal Program Memory
Programming Specifications(1)
D110
D112
D113
VPP
IPP
Voltage on MCLR/VPP pin
Current into MCLR/VPP pin
9.00
—
—
—
—
13.25
5
V
(Note 2)
μA
mA
IDDP
Supply Current during
Programming
—
10
Data EEPROM Memory
D120
ED
Byte Endurance
100K
VMIN
1M
—
—
E/W -40°C to +85°C
D121 VDRW VDD for Read/Write
5.5
V
Using EECON to read/write
VMIN = Minimum operating
voltage
D122 TDEW Erase/Write Cycle Time
D123 TRETD Characteristic Retention
—
4
—
—
ms
40
—
Year Provided no other
specifications are violated
D124
TREF
Number of Total Erase/Write
Cycles before Refresh(3)
1M
10M
—
E/W -40°C to +85°C
Program Flash Memory
Cell Endurance
D130
D131
EP
10K
100K
—
—
E/W -40°C to +85°C
VPR
VDD for Read
VMIN
5.5
V
VMIN = Minimum operating
voltage
D132
VIE
VDD for Block Erase
4.5
4.5
—
—
5.5
5.5
V
V
Using ICSP port
Using ICSP port
D132A VIW
VDD for Externally Timed Erase
or Write
D132B VPEW VDD for Self-Timed Write
VMIN
—
5.5
V
VMIN = Minimum operating
voltage
D133
TIE
ICSP™ Block Erase Cycle Time
—
1
4
—
—
ms VDD > 4.5V
ms VDD > 4.5V
D133A TIW
ICSP Erase or Write Cycle Time
(externally timed)
—
D133A TIW
Self-Timed Write Cycle Time
—
2
—
—
ms
D134 TRETD Characteristic Retention
40
—
Year Provided no other
specifications are violated
†
Data in “Typ” column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance
only and are not tested.
Note 1: These specifications are for programming the on-chip program memory through the use of table write
instructions.
2: The pin may be kept in this range at times other than programming, but it is not recommended.
3: Refer to Section 7.8 “Using the Data EEPROM” for a more detailed discussion on data EEPROM
endurance.
DS39605F-page 252
© 2007 Microchip Technology Inc.
PIC18F1220/1320
FIGURE 22-4:
LOW-VOLTAGE DETECT CHARACTERISTICS
VDD
(LVDIF can be
cleared in software)
VLVD
(LVDIF set by hardware)
LVDIF
TABLE 22-2: LOW-VOLTAGE DETECT CHARACTERISTICS
PIC18LF1220/1320
Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C ≤ TA ≤ +85°C for industrial
(Industrial)
Standard Operating Conditions (unless otherwise stated)
PIC18F1220/1320
Operating temperature
-40°C ≤ TA ≤ +85°C for industrial
-40°C ≤ TA ≤ +125°C for extended
(Industrial, Extended)
Param
Symbol
No.
Characteristic
Min
Typ†
Max
Units
Conditions
D420D
LVD Voltage on VDD Transition High-to-Low
PIC18LF1220/1320 LVDL<3:0> = 0000
LVDL<3:0> = 0001
Industrial Low Voltage (-10°C to +85°C)
N/A
N/A
N/A
N/A
N/A
N/A
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
Reserved
Reserved
LVDL<3:0> = 0010
2.08
2.26
2.35
2.55
2.64
2.82
3.09
3.29
3.38
3.56
3.75
3.93
4.23
2.26
2.45
2.55
2.77
2.87
3.07
3.36
3.57
3.67
3.87
4.07
4.28
4.60
2.44
2.65
2.76
2.99
3.10
3.31
3.63
3.86
3.96
4.18
4.40
4.62
4.96
LVDL<3:0> = 0011
LVDL<3:0> = 0100
LVDL<3:0> = 0101
LVDL<3:0> = 0110
LVDL<3:0> = 0111
LVDL<3:0> = 1000
LVDL<3:0> = 1001
LVDL<3:0> = 1010
LVDL<3:0> = 1011
LVDL<3:0> = 1100
LVDL<3:0> = 1101
LVDL<3:0> = 1110
Legend:
Shading of rows is to assist in readability of the table.
†
Production tested at TAMB = 25°C. Specifications over temperature limits ensured by characterization.
© 2007 Microchip Technology Inc.
DS39605F-page 253
PIC18F1220/1320
TABLE 22-2: LOW-VOLTAGE DETECT CHARACTERISTICS (CONTINUED)
PIC18LF1220/1320
Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C ≤ TA ≤ +85°C for industrial
(Industrial)
Standard Operating Conditions (unless otherwise stated)
PIC18F1220/1320
Operating temperature
-40°C ≤ TA ≤ +85°C for industrial
-40°C ≤ TA ≤ +125°C for extended
(Industrial, Extended)
Param
Symbol
No.
Characteristic
Min
Typ†
Max
Units
Conditions
D420F
LVD Voltage on VDD Transition High-to-Low
PIC18LF1220/1320 LVDL<3:0> = 0000
LVDL<3:0> = 0001
Industrial Low Voltage (-40°C to -10°C)
N/A
N/A
N/A
N/A
N/A
N/A
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
Reserved
Reserved
LVDL<3:0> = 0010
1.99
2.16
2.25
2.43
2.53
2.70
2.96
3.14
3.23
3.41
3.58
3.76
4.04
2.26
2.45
2.55
2.77
2.87
3.07
3.36
3.57
3.67
3.87
4.07
4.28
4.60
2.53
2.75
2.86
3.10
3.21
3.43
3.77
4.00
4.11
4.34
4.56
4.79
5.15
LVDL<3:0> = 0011
LVDL<3:0> = 0100
LVDL<3:0> = 0101
LVDL<3:0> = 0110
LVDL<3:0> = 0111
LVDL<3:0> = 1000
LVDL<3:0> = 1001
LVDL<3:0> = 1010
LVDL<3:0> = 1011
LVDL<3:0> = 1100
LVDL<3:0> = 1101
LVDL<3:0> = 1110
LVD Voltage on VDD Transition High-to-Low
PIC18F1220/1320 LVDL<3:0> = 1101
LVDL<3:0> = 1110
Industrial (-10°C to +85°C)
3.93
4.23
4.28
4.60
4.62
4.96
V
V
D420G
D420H
D420J
LVD Voltage on VDD Transition High-to-Low
PIC18F1220/1320 LVDL<3:0> = 1101
LVDL<3:0> = 1110
Industrial (-40°C to -10°C)
3.76
4.04
4.28
4.60
4.79
5.15
V
V
LVD Voltage on VDD Transition High-to-Low
PIC18F1220/1320 LVDL<3:0> = 1101
LVDL<3:0> = 1110
Extended (-10°C to +85°C)
3.94
4.23
4.28
4.60
4.62
4.96
V
V
LVD Voltage on VDD Transition High-to-Low
PIC18F1220/1320 LVDL<3:0> = 1101
LVDL<3:0> = 1110
Extended (-40°C to -10°C, +85°C to +125°C)
3.77
4.05
4.28
4.60
4.79
5.15
V
V
D420K
Legend:
Shading of rows is to assist in readability of the table.
†
Production tested at TAMB = 25°C. Specifications over temperature limits ensured by characterization.
DS39605F-page 254
© 2007 Microchip Technology Inc.
PIC18F1220/1320
22.4 AC (Timing) Characteristics
22.4.1 TIMING PARAMETER SYMBOLOGY
The timing parameter symbols have been created
following one of the following formats:
1. TppS2ppS
2. TppS
T
3. TCC:ST
4. Ts
(I2C specifications only)
(I2C specifications only)
F
Frequency
T
Time
Lowercase letters (pp) and their meanings:
pp
cc
ck
cs
di
CCP1
CLKO
CS
osc
rd
OSC1
RD
rw
sc
ss
t0
RD or WR
SCK
SDI
do
dt
SDO
SS
Data in
I/O port
MCLR
T0CKI
T13CKI
WR
io
t1
mc
wr
Uppercase letters and their meanings:
S
F
Fall
P
R
V
Z
Period
H
High
Rise
I
L
Invalid (High-Impedance)
Low
Valid
High-Impedance
I2C only
AA
output access
Bus free
High
Low
High
Low
BUF
TCC:ST (I2C specifications only)
CC
HD
Hold
SU
Setup
ST
DAT
STA
DATA input hold
Start condition
STO
Stop condition
© 2007 Microchip Technology Inc.
DS39605F-page 255
PIC18F1220/1320
22.4.2
TIMING CONDITIONS
The temperature and voltages specified in Table 22-3
apply to all timing specifications unless otherwise
noted. Figure 22-5 specifies the load conditions for the
timing specifications.
TABLE 22-3: TEMPERATURE AND VOLTAGE SPECIFICATIONS – AC
Standard Operating Conditions (unless otherwise stated)
Operating temperature
-40°C ≤ TA ≤ +85°C for industrial
-40°C ≤ TA ≤ +125°C for extended
AC CHARACTERISTICS
Operating voltage VDD range as described in DC spec Section 22.1 and
Section 22.3.
LF parts operate for industrial temperatures only.
FIGURE 22-5:
LOAD CONDITIONS FOR DEVICE TIMING SPECIFICATIONS
Load Condition 1 Load Condition 2
VDD/2
CL
RL
Pin
VSS
CL
pin
RL = 464Ω
CL = 50 pF for all pins except OSC2/CLKO
VSS
DS39605F-page 256
© 2007 Microchip Technology Inc.
PIC18F1220/1320
22.4.3
TIMING DIAGRAMS AND SPECIFICATIONS
FIGURE 22-6:
EXTERNAL CLOCK TIMING (ALL MODES EXCEPT PLL)
Q4
Q1
1
Q2
Q3
Q4
Q1
OSC1
CLKO
3
4
3
4
2
TABLE 22-4: EXTERNAL CLOCK TIMING REQUIREMENTS
Param.
Symbol
Characteristic
Min
Max
Units
Conditions
No.
1A
FOSC
External CLKI Frequency(1)
DC
40
MHz EC, ECIO (LF and Industrial)
DC
DC
DC
DC
1
25
4
MHz EC, ECIO (Extended)
MHz RC oscillator
Oscillator Frequency(1)
1
MHz XT oscillator
25
10
33
—
—
—
—
MHz HS oscillator
MHz HS + PLL oscillator
kHz LP Oscillator mode
DC
25
1
TOSC
External CLKI Period(1)
Oscillator Period(1)
ns
ns
ns
ns
EC, ECIO (LF and Industrial)
EC, ECIO (Extended)
RC oscillator
40
250
1000
XT oscillator
25
100
—
1000
ns
ns
HS oscillator
HS + PLL oscillator
30
100
30
2.5
10
—
—
—
μs
ns
ns
μs
ns
ns
ns
ns
LP oscillator
TCY = 4/FOSC
XT oscillator
LP oscillator
HS oscillator
XT oscillator
LP oscillator
HS oscillator
2
3
TCY
Instruction Cycle Time(1)
TosL,
TosH
External Clock in (OSC1)
High or Low Time
—
—
—
4
TosR,
TosF
External Clock in (OSC1)
Rise or Fall Time
20
50
7.5
—
—
Note 1: Instruction cycle period (TCY) equals four times the input oscillator time base period for all configurations
except PLL. All specified values are based on characterization data for that particular oscillator type under
standard operating conditions, with the device executing code. Exceeding these specified limits may result
in an unstable oscillator operation and/or higher than expected current consumption. All devices are tested
to operate at “min.” values with an external clock applied to the OSC1/CLKI pin. When an external clock
input is used, the “max.” cycle time limit is “DC” (no clock) for all devices.
© 2007 Microchip Technology Inc.
DS39605F-page 257
PIC18F1220/1320
TABLE 22-5: PLL CLOCK TIMING SPECIFICATIONS, HS/HSPLL MODE (VDD = 4.2V TO 5.5V)
Param
Sym
Characteristic
Min
Typ†
Max
Units
Conditions
No.
F10
FOSC Oscillator Frequency Range
FSYS On-Chip VCO System Frequency
TPLL PLL Start-up Time (Lock Time)
ΔCLK CLKO Stability (Jitter)
4
—
—
—
—
10
40
2
MHz HS and HSPLL mode only
MHz HSPLL mode only
F11
F12
F13
16
—
-2
ms
%
HSPLL mode only
HSPLL mode only
+2
†
Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance
only and are not tested.
TABLE 22-6: INTERNAL RC ACCURACY: PIC18F1220/1320 (INDUSTRIAL)
PIC18LF1220/1320 (INDUSTRIAL)
PIC18LF1220/1320
Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C ≤ TA ≤ +85°C for industrial
(Industrial)
Standard Operating Conditions (unless otherwise stated)
PIC18F1220/1320
Operating temperature
-40°C ≤ TA ≤ +85°C for industrial
-40°C ≤ TA ≤ +125°C for extended
(Industrial)
Param
No.
Device
Min
Typ
Max
Units
Conditions
(1)
INTOSC Accuracy @ Freq = 8 MHz, 4 MHz, 2 MHz, 1 MHz, 500 kHz, 250 kHz, 125 kHz
PIC18LF1220/1320
-2
-5
+/-1
—
2
5
%
%
%
%
%
%
+25°C
VDD = 2.7-3.3V
-10°C to +85°C VDD = 2.7-3.3V
-40°C to +85°C VDD = 2.7-3.3V
-10
-2
—
10
2
PIC18F1220/1320PIC18F
1220/1320
+/-1
—
+25°C
VDD = 4.5-5.5V
-5
5
-10°C to +85°C VDD = 4.5-5.5V
-40°C to +85°C VDD = 4.5-5.5V
-10
—
10
(2)
INTRC Accuracy @ Freq = 31 kHz
PIC18LF1220/1320 26.562
—
—
35.938
35.938
kHz -40°C to +85°C VDD = 2.7-3.3V
kHz -40°C to +85°C VDD = 4.5-5.5V
PIC18F1220/1320PIC18F 26.562
1220/1320
Legend:
Shading of rows is to assist in readability of the table.
Note 1: Frequency calibrated at 25°C. OSCTUNE register can be used to compensate for temperature and VDD drift.
2: INTRC frequency after calibration.
3: Change of INTRC frequency as VDD changes.
DS39605F-page 258
© 2007 Microchip Technology Inc.
PIC18F1220/1320
FIGURE 22-7:
CLKO AND I/O TIMING
Q1
Q2
Q3
Q4
OSC1
11
10
CLKO
13
14
12
18
19
16
I/O pin
(Input)
15
17
I/O pin
(Output)
New Value
Old Value
20, 21
Refer to Figure 22-5 for load conditions.
Note:
TABLE 22-7: CLKO AND I/O TIMING REQUIREMENTS
Param.
Symbol
Characteristic
Min
Typ
Max
Units Conditions
No.
10
TosH2ckL OSC1↑ to CLKO↓
TosH2ckH OSC1↑ to CLKO↑
—
—
—
—
—
75
75
35
35
—
—
—
50
—
—
—
200
200
100
100
ns
ns
ns
ns
(Note 1)
(Note 1)
(Note 1)
(Note 1)
(Note 1)
(Note 1)
(Note 1)
11
12
13
14
15
16
17
18
18A
19
TckR
TckF
CLKO Rise Time
CLKO Fall Time
TckL2ioV CLKO↓ to Port Out Valid
TioV2ckH Port In Valid before CLKO↑
TckH2ioI Port In Hold after CLKO↑
TosH2ioV OSC1↑ (Q1 cycle) to Port Out Valid
0.5 TCY + 20 ns
0.25 TCY + 25
—
—
ns
ns
ns
ns
ns
ns
0
—
150
—
TosH2ioI OSC1↑ (Q2 cycle) to Port
PIC18F1X20
100
200
0
Input Invalid (I/O in hold time)
PIC18LF1X20
—
TioV2osH Port Input Valid to OSC1↑
—
(I/O in setup time)
20
TioR
TioF
Port Output Rise Time
PIC18F1X20
PIC18LF1X20
PIC18F1X20
PIC18LF1X20
—
—
—
—
10
—
10
—
25
60
25
60
ns
ns
ns
ns
20A
21
Port Output Fall Time
21A
Note 1: Measurements are taken in RC mode, where CLKO output is 4 x TOSC.
© 2007 Microchip Technology Inc.
DS39605F-page 259
PIC18F1220/1320
FIGURE 22-8:
RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND
POWER-UP TIMER TIMING
VDD
MCLR
30
Internal
POR
33
PWRT
Time-out
32
OSC
Time-out
Internal
Reset
Watchdog
Timer
Reset
31
34
34
I/O pins
Note:
Refer to Figure 22-5 for load conditions.
FIGURE 22-9:
BROWN-OUT RESET TIMING
BVDD
VDD
35
VBGAP = 1.2V
VIRVST
Enable Internal
Reference Voltage
Internal Reference
Voltage Stable
36
DS39605F-page 260
© 2007 Microchip Technology Inc.
PIC18F1220/1320
TABLE 22-8: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER
AND BROWN-OUT RESET REQUIREMENTS
Param.
No.
Symbol
Characteristic
Min
Typ
Max
Units
Conditions
30
TmcL
TWDT
MCLR Pulse Width (low)
2
—
—
μs
31
Watchdog Timer Time-out Period
(No postscaler)
3.48
4.00
4.71
ms
32
33
34
TOST
TPWRT
TIOZ
Oscillation Start-up Timer Period
Power-up Timer Period
1024 TOSC
—
65.5
2
1024 TOSC
—
ms
μs
TOSC = OSC1 period
—
—
132
—
I/O High-Impedance from MCLR
Low or Watchdog Timer Reset
35
36
TBOR
Brown-out Reset Pulse Width
200
—
—
—
μs VDD ≤ BVDD (see D005)
μs
TIVRST
Time for Internal Reference
Voltage to become stable
20
50
37
TLVD
Low-Voltage Detect Pulse Width
200
—
—
μs
VDD ≤ VLVD
FIGURE 22-10:
TIMER0 AND TIMER1 EXTERNAL CLOCK TIMINGS
T0CKI
41
40
42
T1OSO/T13CKI
46
45
47
48
TMR0 or
TMR1
Note:
Refer to Figure 22-5 for load conditions.
© 2007 Microchip Technology Inc.
DS39605F-page 261
PIC18F1220/1320
TABLE 22-9: TIMER0 AND TIMER1 EXTERNAL CLOCK REQUIREMENTS
Param
Symbol
Characteristic
Min
Max Units Conditions
No.
40
Tt0H
T0CKI High Pulse Width
No prescaler
With prescaler
No prescaler
With prescaler
No prescaler
With prescaler
0.5 TCY + 20
10
—
—
—
—
—
—
ns
ns
ns
ns
ns
41
42
Tt0L
Tt0P
T0CKI Low Pulse Width
T0CKI Period
0.5 TCY + 20
10
TCY + 10
Greater of:
20 ns or TCY + 40
N
ns N = prescale
value
(1, 2, 4,..., 256)
45
46
47
Tt1H
Tt1L
T13CKI High Time Synchronous, no prescaler
Synchronous, PIC18F1X20
0.5 TCY + 20
—
—
—
—
—
—
—
—
—
—
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
10
with prescaler
PIC18LF1X20
25
Asynchronous PIC18F1X20
PIC18LF1X20
30
50
T13CKI Low Time Synchronous, no prescaler
0.5 TCY + 5
Synchronous, PIC18F1X20
with prescaler
PIC18LF1X20
10
25
30
50
Asynchronous PIC18F1X20
PIC18LF1X20
Tt1P
Ft1
T13CKI Input
Period
Synchronous
Greater of:
20 ns or TCY + 40
N
ns N = prescale
value
(1, 2, 4, 8)
Asynchronous
60
DC
—
50
ns
kHz
—
T13CKI Oscillator Input Frequency Range
48
Tcke2tmrI Delay from External T13CKI Clock Edge to
Timer Increment
2 TOSC
7 TOSC
FIGURE 22-11:
CAPTURE/COMPARE/PWM TIMINGS (ALL CCP MODULES)
CCPx
(Capture Mode)
50
51
52
54
CCPx
(Compare or PWM Mode)
53
Note:
Refer to Figure 22-5 for load conditions.
DS39605F-page 262
© 2007 Microchip Technology Inc.
PIC18F1220/1320
TABLE 22-10: CAPTURE/COMPARE/PWM REQUIREMENTS (ALL CCP MODULES)
Param.
No.
Symbol
Characteristic
Min
Max
Units
Conditions
50
51
TccL
CCPx Input Low No prescaler
Time
0.5 TCY + 20
—
—
—
—
—
—
—
ns
ns
ns
ns
ns
ns
ns
With prescaler PIC18F1X20
10
PIC18LF1X20
20
TccH
CCPx Input High No prescaler
Time
0.5 TCY + 20
With prescaler PIC18F1X20
PIC18LF1X20
10
20
52
53
TccP
TccR
CCPx Input Period
3 TCY + 40
N
N = prescale
value (1, 4 or 16)
CCPx Output Fall Time
CCPx Output Fall Time
PIC18F1X20
PIC18LF1X20
PIC18F1X20
PIC18LF1X20
—
—
—
—
25
45
25
45
ns
ns
ns
ns
54
TccF
FIGURE 22-12:
EUSART SYNCHRONOUS TRANSMISSION (MASTER/SLAVE) TIMING
RB1/AN5/TX/
CK/INT1 pin
121
121
RB4/AN6/RX/
DT/KBI0 pin
120
Refer to Figure 22-5 for load conditions.
122
Note:
TABLE 22-11: EUSART SYNCHRONOUS TRANSMISSION REQUIREMENTS
Param.
Symbol
Characteristic
Min
Max
Units Conditions
No.
120
TckH2dtV SYNC XMIT (MASTER & SLAVE)
Clock High to Data Out Valid
PIC18F1X20
PIC18LF1X20
PIC18F1X20
PIC18LF1X20
PIC18F1X20
PIC18LF1X20
—
—
—
—
—
—
40
100
20
ns
ns
ns
ns
ns
ns
121
122
Tckrf
Tdtrf
Clock Out Rise Time and Fall Time
(Master mode)
50
Data Out Rise Time and Fall Time
20
50
© 2007 Microchip Technology Inc.
DS39605F-page 263
PIC18F1220/1320
FIGURE 22-13:
EUSART SYNCHRONOUS RECEIVE (MASTER/SLAVE) TIMING
RB1/AN5/TX/
CK/INT1 pin
125
RB4/AN6/RX/
DT/KBI0 pin
126
Note:
Refer to Figure 22-5 for load conditions.
TABLE 22-12: EUSART SYNCHRONOUS RECEIVE REQUIREMENTS
Param.
Symbol
Characteristic
Min
Max
Units
Conditions
No.
125
TdtV2ckl SYNC RCV (MASTER & SLAVE)
Data Hold before CK↓ (DT hold time)
Data Hold after CK↓ (DT hold time)
10
15
—
—
ns
ns
126
TckL2dtl
TABLE 22-13: A/D CONVERTER CHARACTERISTICS: PIC18F1220/1320 (INDUSTRIAL)
PIC18LF1220/1320 (INDUSTRIAL)
Param
No.
Symbol
Characteristic
Min
Typ
Max
Units
Conditions
A01
NR
Resolution
—
—
—
—
—
—
10
bit ΔVREF ≥ 3.0V
A03
A04
A06
A07
A10
A20
EIL
Integral Linearity Error
Differential Linearity Error
Offset Error
—
<±1
<±1
<±1
<±1
LSb ΔVREF ≥ 3.0V
LSb ΔVREF ≥ 3.0V
LSb ΔVREF ≥ 3.0V
LSb ΔVREF ≥ 3.0V
—
EDL
EOFF
EGN
—
—
—
Gain Error
—
Monotonicity
guaranteed(2)
ΔVREF Reference Voltage Range
3
—
AVDD – AVSS
V
For 10-bit resolution
(VREFH – VREFL)
A21
A22
A25
A28
A29
A30
VREFH Reference Voltage High
VREFL Reference Voltage Low
AVSS + 3.0V
AVSS – 0.3V
VREFL
—
—
—
—
—
—
AVDD + 0.3V
AVDD – 3.0V
VREFH
V
V
For 10-bit resolution
For 10-bit resolution
VAIN
Analog Input Voltage
Analog Supply Voltage
Analog Supply Voltage
V
AVDD
AVSS
ZAIN
VDD – 0.3
VSS – 0.3
—
VDD + 0.3
VSS + 0.3
2.5
V
V
Recommended Impedance of
Analog Voltage Source
kΩ
A40
A50
IAD
A/D Conversion PIC18F1X20
—
—
180
90
—
—
μA Average current
Current (VDD)
consumption when
PIC18LF1X20
μA
A/D is on (Note 1)
IREF
VREF Input Current (Note 3)
—
—
—
—
±5
±150
μA During VAIN acquisition.
μA During A/D conversion
cycle.
Note 1: When A/D is off, it will not consume any current other than minor leakage current. The power-down current
specification includes any such leakage from the A/D module.
2: The A/D conversion result never decreases with an increase in the input voltage and has no missing codes.
3: VREFH current is from RA3/AN3/VREF+ pin or AVDD, whichever is selected as the VREFH source.
VREFL current is from RA2/AN2/VREF- pin or AVSS, whichever is selected as the VREFL source.
DS39605F-page 264
© 2007 Microchip Technology Inc.
PIC18F1220/1320
FIGURE 22-14:
A/D CONVERSION TIMING
BSF ADCON0, GO
(Note 2)
131
130
Q4
A/D CLK(1)
132
. . .
. . .
9
8
7
2
1
0
A/D DATA
ADRES
NEW_DATA
TCY
OLD_DATA
ADIF
GO
DONE
Sampling Stopped
SAMPLE
Note 1: If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts.
This allows the SLEEPinstruction to be executed.
2: This is a minimal RC delay (typically 100 ns), which also disconnects the holding capacitor from the analog input.
TABLE 22-14: A/D CONVERSION REQUIREMENTS
Param
Symbol
Characteristic
Min
Max
Units
Conditions
No.
130
TAD
A/D Clock Period
PIC18F1X20
1.6
3.0
2.0
3.0
11
20(5)
20(5)
6.0
μs TOSC based, VREF ≥ 3.0V
μs TOSC based, VREF full range
μs A/D RC mode
PIC18LF1X20
PIC18F1X20
PIC18LF1X20
9.0
μs A/D RC mode
131
132
TCNV
TACQ
Conversion Time
(not including acquisition time) (Note 1)
Acquisition Time (Note 3)
12
TAD
15
10
—
—
μs -40°C ≤ Temp ≤ +125°C
μs 0°C ≤ Temp ≤ +125°C
135
136
TSWC
TAMP
Switching Time from Convert → Sample
Amplifier Settling Time (Note 2)
—
1
(Note 4)
—
μs This may be used if the
“new” input voltage has not
changed by more than 1 LSb
(i.e., 5 mV @ 5.12V) from the
last sampled voltage (as
stated on CHOLD).
Note 1: ADRES register may be read on the following TCY cycle.
2: See Section 17.0 “10-Bit Analog-to-Digital Converter (A/D) Module” for minimum conditions when input
voltage has changed more than 1 LSb.
3: The time for the holding capacitor to acquire the “New” input voltage, when the voltage changes full scale after
the conversion (AVDD to AVSS, or AVSS to AVDD). The source impedance (RS) on the input channels is 50Ω.
4: On the next Q4 cycle of the device clock.
5: The time of the A/D clock period is dependent on the device frequency and the TAD clock divider.
© 2007 Microchip Technology Inc.
DS39605F-page 265
PIC18F1220/1320
NOTES:
DS39605F-page 266
© 2007 Microchip Technology Inc.
PIC18F1220/1320
23.0 DC AND AC CHARACTERISTICS GRAPHS AND TABLES
Note:
The graphs and tables provided following this note are a statistical summary based on a limited number of
samples and are provided for informational purposes only. The performance characteristics listed herein
are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified
operating range (e.g., outside specified power supply range) and therefore, outside the warranted range.
“Typical” represents the mean of the distribution at 25°C. “Maximum” or “minimum” represents (mean + 3σ) or (mean – 3σ)
respectively, where σ is a standard deviation, over the whole temperature range.
FIGURE 23-1:
TYPICAL IDD vs. FOSC OVER VDD PRI_RUN, EC MODE, +25°C
0.5
Typical:
statistical mean @ 25°C
Maximum: mean + 3σ (-40°C to +125°C)
Minimum: mean – 3σ (-40°C to +125°C)
0.4
0.3
0.2
0.1
5.5V
5.0V
4.5V
4.0V
3.5V
3.0V
2.5V
2.0V
0.0
0.00
0.02
0.04
0.06
0.08
0.10
0.12
0.14
0.16
0.18
0.20
FOSC (MHz)
FIGURE 23-2:
MAXIMUM IDD vs. FOSC OVER VDD PRI_RUN, EC MODE, -40°C TO +85°C
0.7
Typical:
statistical mean @ 25°C
Maximum: mean + 3σ (-40°C to +125°C)
Minimum: mean – 3σ (-40°C to +125°C)
0.6
0.5
0.4
0.3
0.2
0.1
5.5V
5.0V
4.5V
4.0V
3.5V
3.0V
2.5V
2.0V
0.0
0.00
0.02
0.04
0.06
0.08
0.10
0.12
0.14
0.16
0.18
0.20
FOSC (MHz)
© 2007 Microchip Technology Inc.
DS39605F-page 267
PIC18F1220/1320
FIGURE 23-3:
MAXIMUM IDD vs. FOSC OVER VDD PRI_RUN, EC MODE, -40°C TO +125°C
0.7
Typical:
statistical mean @ 25°C
Maximum: mean + 3σ (-40°C to +125°C)
Minimum: mean – 3σ (-40°C to +125°C)
0.6
0.5
0.4
0.3
0.2
0.1
5.5V
5.0V
4.5V
4.0V
3.5V
3.0V
2.5V
2.0V
0.0
0.00
0.02
0.04
0.06
0.08
0.10
0.12
0.14
0.16
0.18
0.20
FOSC (MHz)
FIGURE 23-4:
TYPICAL IDD vs. FOSC OVER VDD PRI_RUN, EC MODE, +25°C
2.0
Typical:
statistical mean @ 25°C
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
Maximum: mean + 3σ (-40°C to +125°C)
Minimum: mean – 3σ (-40°C to +125°C)
5.5V
5.0V
4.5V
4.0V
3.5V
3.0V
2.5V
2.0V
0.0
1.0
1.5
2.0
2.5
(MHz)
3.0
3.5
4.0
F
OSC
DS39605F-page 268
© 2007 Microchip Technology Inc.
PIC18F1220/1320
FIGURE 23-5:
MAXIMUM IDD vs. FOSC OVER VDD PRI_RUN, EC MODE, -40°C TO +125°C
2.5
Typical:
statistical mean @ 25°C
Maximum: mean + 3σ (-40°C to +125°C)
Minimum: mean – 3σ (-40°C to +125°C)
2.0
1.5
1.0
0.5
5.5V
5.0V
4.5V
4.0V
3.5V
3.0V
2.5V
2.0V
0.0
1.0
1.5
2.0
2.5
3.0
3.5
4.0
FOSC (MHz)
FIGURE 23-6:
TYPICAL IDD vs. FOSC OVER VDD PRI_RUN, EC MODE, +25°C
16
Typical:
statistical mean @ 25°C
Maximum: mean + 3σ (-40°C to +125°C)
Minimum: mean – 3σ (-40°C to +125°C)
14
12
10
8
5.5V
5.0V
4.5V
4.0V
6
3.5V
4
3.0V
2
2.5V
2.0V
0
4
8
12
16
20
24
28
32
36
40
F
(MHz)
OSC
© 2007 Microchip Technology Inc.
DS39605F-page 269
PIC18F1220/1320
FIGURE 23-7:
MAXIMUM IDD vs. FOSC OVER VDD PRI_RUN, EC MODE, -40°C TO +125°C
16
Typical:
statistical mean @ 25°C
14
12
10
8
Maximum: mean + 3σ (-40°C to +125°C)
Minimum: mean – 3σ (-40°C to +125°C)
5.5V
5.0V
4.0V
4.5V
3.5V
6
4
3.0V
2
2.5V
2.0V
0
4
8
12
16
20
24
28
32
36
40
FOSC (MHz)
FIGURE 23-8:
TYPICAL IDD vs. FOSC OVER VDD PRI_IDLE, EC MODE, +25°C
0.035
Typical:
statistical mean @ 25°C
Maximum: mean + 3σ (-40°C to +125°C)
Minimum: mean – 3σ (-40°C to +125°C)
5.5V
0.030
0.025
0.020
0.015
0.010
0.005
5.0V
4.5V
4.0V
3.5V
3.0V
2.5V
2.0V
0.000
0.00
0.02
0.04
0.06
0.08
0.10
0.12
0.14
0.16
0.18
0.20
FOSC (MHz)
DS39605F-page 270
© 2007 Microchip Technology Inc.
PIC18F1220/1320
FIGURE 23-9:
MAXIMUM IDD vs. FOSC OVER VDD PRI_IDLE, EC MODE, -40°C TO +85°C
0.045
Typical:
statistical mean @ 25°C
Maximum: mean + 3σ (-40°C to +125°C)
Minimum: mean – 3σ (-40°C to +125°C)
0.040
0.035
0.030
0.025
0.020
0.015
0.010
0.005
5.5V
5.0V
4.5V
4.0V
3.5V
3.0V
2.5V
2.0V
0.000
0.00
0.02
0.04
0.06
0.08
0.10
0.12
0.14
0.16
0.18
0.20
FOSC (MHz)
FIGURE 23-10:
MAXIMUM IDD vs. FOSC OVER VDD PRI_IDLE, EC MODE, -40°C TO +125°C
0.100
Typical:
statistical mean @ 25°C
Maximum: mean + 3σ (-40°C to +125°C)
Minimum: mean – 3σ (-40°C to +125°C)
0.090
0.080
0.070
0.060
0.050
0.040
0.030
0.020
0.010
5.5V
5.0V
4.5V
4.0V
3.5V
3.0V
2.5V
2.0V
0.000
0.00
0.02
0.04
0.06
0.08
0.10
0.12
0.14
0.16
0.18
0.20
FOSC (MHz)
© 2007 Microchip Technology Inc.
DS39605F-page 271
PIC18F1220/1320
FIGURE 23-11:
TYPICAL IDD vs. FOSC OVER VDD PRI_IDLE, EC MODE, +25°C
600
Typical:
statistical mean @ 25°C
Maximum: mean + 3σ (-40°C to +125°C)
Minimum: mean – 3σ (-40°C to +125°C)
500
400
300
200
100
5.5V
5.0V
4.5V
4.0V
3.5V
3.0V
2.5V
2.0V
0
1.0
1.5
2.0
2.5
(MHz)
3.0
3.5
4.0
F
OSC
FIGURE 23-12:
MAXIMUM IDD vs. FOSC OVER VDD PRI_IDLE, EC MODE, -40°C TO +125°C
600
Typical:
statistical mean @ 25°C
Maximum: mean + 3σ (-40°C to +125°C)
Minimum: mean – 3σ (-40°C to +125°C)
5.5V
500
400
300
200
100
5.0V
4.5V
4.0V
3.5V
3.0V
2.5V
2.0V
0
1.0
1.5
2.0
2.5
3.0
3.5
4.0
FOSC (MHz)
DS39605F-page 272
© 2007 Microchip Technology Inc.
PIC18F1220/1320
FIGURE 23-13:
TYPICAL IDD vs. FOSC OVER VDD PRI_IDLE, EC MODE, +25°C
6.0
Typical:
statistical mean @ 25°C
Maximum: mean + 3σ (-40°C to +125°C)
Minimum: mean – 3σ (-40°C to +125°C)
5.5
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
5.5V
5.0V
4.5V
4.0V
3.5V
3.0V
2.5V
2.0V
4
8
12
16
20
24
28
32
36
40
FOSC (MHz)
FIGURE 23-14:
MAXIMUM IDD vs. FOSC OVER VDD PRI_IDLE, EC MODE, -40°C TO +125°C
6.0
5.5
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
Typical:
statistical mean @ 25°C
Maximum: mean + 3σ (-40°C to +125°C)
Minimum: mean – 3σ (-40°C to +125°C)
5.5V
5.0V
4.5V
4.0V
3.5V
3.0V
2.5V
2.0V
0.0
4
8
12
16
20
24
28
32
36
40
FOSC (MHz)
© 2007 Microchip Technology Inc.
DS39605F-page 273
PIC18F1220/1320
FIGURE 23-15:
TYPICAL IPD vs. VDD (+25°C), 125 kHz TO 8 MHz RC_RUN MODE,
ALL PERIPHERALS DISABLED
3000
Typical:
statistical mean @ 25°C
Maximum: mean + 3σ (-40°C to +125°C)
Minimum: mean – 3σ (-40°C to +125°C)
8 MHz
2500
2000
1500
1000
500
250 kHz and 500 kHz curves are
bounded by 125 kHz and 1 MHz
4 MHz
2 MHz
1 MHz
125 kHz
0
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
VDD (V)
FIGURE 23-16:
MAXIMUM IPD vs. VDD (-40°C TO +125°C), 125 kHz TO 8 MHz RC_RUN MODE,
ALL PERIPHERALS DISABLED
3500
8 MHz
3000
2500
250 kHz and 500 kHz curves are
bounded by 125 kHz and 1 MHz
Typical:
statistical mean @ 25°C
Maximum: mean + 3σ (-40°C to +125°C)
Minimum: mean – 3σ (-40°C to +125°C)
2000
1500
1000
500
0
4 MHz
2 MHz
1 MHz
125 kHz
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
VDD (V)
DS39605F-page 274
© 2007 Microchip Technology Inc.
PIC18F1220/1320
FIGURE 23-17:
TYPICAL AND MAXIMUM IPD vs. VDD (-40°C TO +125°C), 31.25 kHz RC_RUN MODE,
ALL PERIPHERALS DISABLED
100
Max (+125°C)
Max (+85°C)
Typ (+25°C)
10
Typical:
statistical mean @ 25°C
Maximum: mean + 3σ (-40°C to +125°C)
Minimum: mean – 3σ (-40°C to +125°C)
1
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
VDD (V)
FIGURE 23-18:
TYPICAL IPD vs. VDD (+25°C), 125 kHz TO 8 MHz RC_IDLE MODE,
ALL PERIPHERALS DISABLED
800
750
700
650
250 kHz and 500 kHz curves are
bounded by 125 kHz and 1 MHz
8 MHz
4 MHz
Typical:
statistical mean @ 25°C
Maximum: mean + 3σ (-40°C to +125°C)
Minimum: mean – 3σ (-40°C to +125°C)
600
550
500
450
400
350
300
250
200
150
100
2 MHz
1 MHz
125 kHz
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
VDD (V)
© 2007 Microchip Technology Inc.
DS39605F-page 275
PIC18F1220/1320
FIGURE 23-19:
MAXIMUM IPD vs. VDD (-40°C TO +125°C), 125 kHz TO 8 MHz RC_IDLE MODE,
ALL PERIPHERALS DISABLED
800
750
700
650
600
550
500
450
400
350
300
250
200
150
8 MHz
250 kHz and 500 kHz curves are
bounded by 125 kHz and 1 MHz
4 MHz
2 MHz
1 MHz
125 kHz
Typical:
statistical mean @ 25°C
Maximum: mean + 3σ (-40°C to +125°C)
Minimum: mean – 3σ (-40°C to +125°C)
100
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
VDD (V)
FIGURE 23-20:
TYPICAL AND MAXIMUM IPD vs. VDD (-40°C TO +125°C), 31.25 kHz RC_IDLE MODE,
ALL PERIPHERALS DISABLED
100
Max (+125°C)
Max (+85°C)
Typ (+25°C)
10
Typical:
statistical mean @ 25°C
Maximum: mean + 3σ (-40°C to +125°C)
Minimum: mean – 3σ (-40°C to +125°C)
1
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
VDD (V)
DS39605F-page 276
© 2007 Microchip Technology Inc.
PIC18F1220/1320
FIGURE 23-21:
IPD SEC_RUN MODE, -10°C TO +70°C, 32.768 kHz XTAL, 2 x 22 pF,
ALL PERIPHERALS DISABLED
80
Typical:
statistical mean @ 25°C
Maximum: mean + 3σ (-40°C to +125°C)
Minimum: mean – 3σ (-40°C to +125°C)
70
60
50
40
30
20
10
0
Max (+70°C)
Typ (+25°C)
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
VDD (V)
FIGURE 23-22:
IPD SEC_IDLE MODE, -10°C TO +70°C, 32.768 kHz, 2 x 22 pF,
ALL PERIPHERALS DISABLED
20
18
16
14
12
10
8
Typical:
statistical mean @ 25°C
Maximum: mean + 3σ (-40°C to +125°C)
Minimum: mean – 3σ (-40°C to +125°C)
Max (+70°C)
Typ (+25°C)
6
4
2
0
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
VDD (V)
© 2007 Microchip Technology Inc.
DS39605F-page 277
PIC18F1220/1320
FIGURE 23-23:
TOTAL IPD, -40°C TO +125°C SLEEP MODE, ALL PERIPHERALS DISABLED
100
Max (+125°C)
Max (+85°C)
10
1
0.1
0.01
Typ (+25°C)
Typical:
statistical mean @ 25°C
Maximum: mean + 3σ (-40°C to +125°C)
Minimum: mean – 3σ (-40°C to +125°C)
0.001
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
VDD (V)
FIGURE 23-24:
VOH vs. IOH OVER TEMPERATURE (-40°C TO +125°C), VDD = 3.0V
3.0
2.5
2.0
1.5
1.0
0.5
Max (+125°C)
Typ (+25°C)
Min (+125°C)
0.0
0
5
10
15
20
25
IOH (-mA)
DS39605F-page 278
© 2007 Microchip Technology Inc.
PIC18F1220/1320
FIGURE 23-25:
VOH vs. IOH OVER TEMPERATURE (-40°C TO +125°C), VDD = 5.0V
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
Max (+125°C)
Typ (+25°C)
Min (+125°C)
0.0
0
5
10
15
20
25
IOH (-mA)
FIGURE 23-26:
VOL vs. IOL OVER TEMPERATURE (-40°C TO +125°C), VDD = 3.0V
3.0
Max (+125°C)
2.5
2.0
1.5
1.0
0.5
Max (+85°C)
Typ (+25°C)
Min (+125°C)
0.0
0
5
10
15
20
25
IOL (-mA)
© 2007 Microchip Technology Inc.
DS39605F-page 279
PIC18F1220/1320
FIGURE 23-27:
VOL vs. IOL OVER TEMPERATURE (-40°C TO +125°C), VDD = 5.0V
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
Max (+125°C)
Max (+85°C)
Typ (+25°C)
Min (+125°C)
0.0
0
5
10
15
20
25
IOL (-mA)
FIGURE 23-28:
ΔIPD TIMER1 OSCILLATOR, -10°C TO +70°C SLEEP MODE,
TMR1 COUNTER DISABLED
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
Max (-10°C to +70°C)
Typ (+25°C)
Typical:
statistical mean @ 25°C
Maximum: mean + 3σ (-40°C to +125°C)
Minimum: mean – 3σ (-40°C to +125°C)
0.0
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
VDD (V)
DS39605F-page 280
© 2007 Microchip Technology Inc.
PIC18F1220/1320
FIGURE 23-29:
ΔIPD FSCM vs. VDD OVER TEMPERATURE PRI_IDLE MODE,
EC OSCILLATOR AT 32 kHz, -40°C TO +125°C
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
Max (-40°C)
Typ (+25°C)
Typical:
statistical mean @ 25°C
Maximum: mean + 3σ (-40°C to +125°C)
Minimum: mean – 3σ (-40°C to +125°C)
0.0
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
V
DD
(V)
FIGURE 23-30:
ΔIPD WDT, -40°C TO +125°C SLEEP MODE, ALL PERIPHERALS DISABLED
14
Typical:
statistical mean @ 25°C
Maximum: mean + 3σ (-40°C to +125°C)
Minimum: mean – 3σ (-40°C to +125°C)
12
10
8
Max (+125°C)
6
Max (+85°C)
Typ (+25°C)
4
2
0
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
V
DD
(V)
© 2007 Microchip Technology Inc.
DS39605F-page 281
PIC18F1220/1320
FIGURE 23-31:
ΔIPD LVD vs. VDD SLEEP MODE, LVDL3:LVDL0 = 0001 (2V)
50
45
40
35
30
25
20
15
10
Typical:
statistical mean @ 25°C
Maximum: mean + 3σ (-40°C to +125°C)
Minimum: mean – 3σ (-40°C to +125°C)
Max (+125°C)
Max (+85°C)
Typ (+25°C)
Low-Voltage Detection Range
5
0
Normal Operating Range
3.5 4.0
2.0
2.5
3.0
4.5
5.0
5.5
VDD (V)
FIGURE 23-32:
ΔIPD BOR vs. VDD, -40°C TO +125°C SLEEP MODE,
BORV1:BORV0 = 11 (2V)
40
35
30
25
20
15
10
Typical:
statistical mean @ 25°C
Maximum: mean + 3σ (-40°C to +125°C)
Minimum: mean – 3σ (-40°C to +125°C)
Max (+125°C)
Typ (+25°C)
Device may be in Reset
5
0
Device is Operating
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
V
DD (V)
DS39605F-page 282
© 2007 Microchip Technology Inc.
PIC18F1220/1320
FIGURE 23-33:
ΔIPD A/D, -40°C TO +125°C SLEEP MODE, A/D ENABLED (NOT CONVERTING)
10
Max (+125°C)
1
Max (+85°C)
0.1
0.01
Typical:
statistical mean @ 25°C
Maximum: mean + 3σ (-40°C to +125°C)
Minimum: mean – 3σ (-40°C to +125°C)
Typ (+25°C)
0.001
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
VDD (V)
FIGURE 23-34:
AVERAGE FOSC vs. VDD FOR VARIOUS R’s EXTERNAL RC MODE,
C = 20 pF, TEMPERATURE = +25°C
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
Operation above 4 MHz is not recomended
5.1K
10K
33K
100K
0.0
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
V
DD
(V)
© 2007 Microchip Technology Inc.
DS39605F-page 283
PIC18F1220/1320
FIGURE 23-35:
AVERAGE FOSC vs. VDD FOR VARIOUS R’s EXTERNAL RC MODE,
C = 100 pF, TEMPERATURE = +25°C
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
5.1K
10K
33K
100K
0.0
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
V
DD
(V)
FIGURE 23-36:
AVERAGE FOSC vs. VDD FOR VARIOUS R’s EXTERNAL RC MODE,
C = 300 pF, TEMPERATURE = +25°C
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
5.1K
10K
33K
100K
0.0
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
V
DD
(V)
DS39605F-page 284
© 2007 Microchip Technology Inc.
PIC18F1220/1320
24.0 PACKAGING INFORMATION
24.1 Package Marking Information
18-Lead PDIP
Example
XXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXX
YYWWNNN
PIC18F1320-I/P
0710017
e3
18-Lead SOIC
Example
XXXXXXXXXXXX
XXXXXXXXXXXX
XXXXXXXXXXXX
PIC18F1220-
E/SO
e
3
0710017
YYWWNNN
20-Lead SSOP
Example
E/SS
XXXXXXXXXXX
XXXXXXXXXXX
PIC18F1220-
e
3
YYWWNNN
0710017
28-Lead QFN
Example
XXXXXXXX
XXXXXXXX
YYWWNNN
18F1320
3
e
-I/ML
0710017
Legend: XX...X Customer-specific information
Y
YY
Year code (last digit of calendar year)
Year code (last 2 digits of calendar year)
WW
NNN
Week code (week of January 1 is week ‘01’)
Alphanumeric traceability code
e
3
Pb-free JEDEC designator for Matte Tin (Sn)
This package is Pb-free. The Pb-free JEDEC designator (
can be found on the outer packaging for this package.
*
)
3
e
Note: In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
© 2007 Microchip Technology Inc.
DS39605F-page 285
PIC18F1220/1320
24.2 Package Details
The following sections give the technical details of the packages.
18-Lead Plastic Dual In-Line (P) – 300 mil Body [PDIP]
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
N
NOTE 1
E1
2
3
1
D
E
A2
A
L
c
A1
b1
e
b
eB
Units
INCHES
NOM
18
Dimension Limits
MIN
MAX
Number of Pins
Pitch
N
e
.100 BSC
–
Top to Seating Plane
A
–
.210
.195
–
Molded Package Thickness
Base to Seating Plane
Shoulder to Shoulder Width
Molded Package Width
Overall Length
A2
A1
E
.115
.015
.300
.240
.880
.115
.008
.045
.014
–
.130
–
.310
.250
.900
.130
.010
.060
.018
–
.325
.280
.920
.150
.014
.070
.022
.430
E1
D
Tip to Seating Plane
Lead Thickness
L
c
Upper Lead Width
b1
b
Lower Lead Width
Overall Row Spacing §
eB
Notes:
1. Pin 1 visual index feature may vary, but must be located within the hatched area.
2. § Significant Characteristic.
3. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" per side.
4. Dimensioning and tolerancing per ASME Y14.5M.
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
Microchip Technology Drawing C04-007B
DS39605F-page 286
© 2007 Microchip Technology Inc.
PIC18F1220/1320
18-Lead Plastic Small Outline (SO) – Wide, 7.50 mm Body [SOIC]
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
D
N
E
E1
NOTE 1
1
2
3
e
b
α
h
h
c
φ
A2
A
β
A1
L
L1
Units
MILLIMETERS
Dimension Limits
MIN
NOM
MAX
Number of Pins
Pitch
N
e
18
1.27 BSC
Overall Height
A
–
–
2.65
–
Molded Package Thickness
Standoff §
A2
A1
E
2.05
0.10
–
–
0.30
Overall Width
10.30 BSC
Molded Package Width
Overall Length
E1
D
h
7.50 BSC
11.55 BSC
Chamfer (optional)
Foot Length
0.25
0.40
–
0.75
1.27
L
–
Footprint
L1
φ
1.40 REF
Foot Angle
0°
0.20
0.31
5°
–
–
–
–
–
8°
Lead Thickness
Lead Width
c
0.33
0.51
15°
b
Mold Draft Angle Top
Mold Draft Angle Bottom
α
β
5°
15°
Notes:
1. Pin 1 visual index feature may vary, but must be located within the hatched area.
2. § Significant Characteristic.
3. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.15 mm per side.
4. Dimensioning and tolerancing per ASME Y14.5M.
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
REF: Reference Dimension, usually without tolerance, for information purposes only.
Microchip Technology Drawing C04-051B
© 2007 Microchip Technology Inc.
DS39605F-page 287
PIC18F1220/1320
20-Lead Plastic Shrink Small Outline (SS) – 5.30 mm Body [SSOP]
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
D
N
E
E1
NOTE 1
1
2
e
b
c
A2
A
φ
A1
L1
L
Units
MILLIMETERS
Dimension Limits
MIN
NOM
MAX
Number of Pins
Pitch
N
e
20
0.65 BSC
Overall Height
Molded Package Thickness
Standoff
A
–
–
1.75
–
2.00
1.85
–
A2
A1
E
1.65
0.05
7.40
5.00
6.90
0.55
Overall Width
Molded Package Width
Overall Length
Foot Length
7.80
5.30
7.20
0.75
1.25 REF
–
8.20
5.60
7.50
0.95
E1
D
L
Footprint
L1
c
Lead Thickness
Foot Angle
0.09
0°
0.25
8°
φ
4°
Lead Width
b
0.22
–
0.38
Notes:
1. Pin 1 visual index feature may vary, but must be located within the hatched area.
2. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.20 mm per side.
3. Dimensioning and tolerancing per ASME Y14.5M.
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
REF: Reference Dimension, usually without tolerance, for information purposes only.
Microchip Technology Drawing C04-072B
DS39605F-page 288
© 2007 Microchip Technology Inc.
PIC18F1220/1320
28-Lead Plastic Quad Flat, No Lead Package (ML) – 6x6 mm Body [QFN]
with 0.55 mm Contact Length
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
D
D2
EXPOSED
PAD
e
E
b
E2
2
1
2
1
K
N
N
NOTE 1
L
BOTTOM VIEW
TOP VIEW
A
A3
A1
Units
MILLIMETERS
NOM
Dimension Limits
MIN
MAX
Number of Pins
N
e
28
Pitch
0.65 BSC
0.90
Overall Height
Standoff
A
0.80
0.00
1.00
0.05
A1
A3
E
0.02
Contact Thickness
Overall Width
0.20 REF
6.00 BSC
3.70
Exposed Pad Width
Overall Length
Exposed Pad Length
Contact Width
Contact Length
Contact-to-Exposed Pad
E2
D
3.65
4.20
6.00 BSC
3.70
D2
b
3.65
0.23
0.50
0.20
4.20
0.35
0.70
–
0.30
L
0.55
K
–
Notes:
1. Pin 1 visual index feature may vary, but must be located within the hatched area.
2. Package is saw singulated.
3. Dimensioning and tolerancing per ASME Y14.5M.
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
REF: Reference Dimension, usually without tolerance, for information purposes only.
Microchip Technology Drawing C04-105B
© 2007 Microchip Technology Inc.
DS39605F-page 289
PIC18F1220/1320
NOTES:
DS39605F-page 290
© 2007 Microchip Technology Inc.
PIC18F1220/1320
Revision F (February 2007)
APPENDIX A: REVISION HISTORY
This revision includes updates to the packaging
diagrams.
Revision A (August 2002)
Original data sheet for PIC18F1220/1320 devices.
APPENDIX B: DEVICE
DIFFERENCES
Revision B (November 2002)
This revision includes significant changes to
Section 2.0, Section 3.0 and Section 19.0, as well as
updates to the Electrical Specifications in Section 22.0
and includes minor corrections to the data sheet text.
The differences between the devices listed in this data
sheet are shown in Table B-1.
Revision C (May 2004)
This revision includes updates to the Electrical Specifi-
cations in Section 22.0, the DC and AC Characteristics
Graphs and Tables in Section 23.0 and includes minor
corrections to the data sheet text.
Revision D (October 2006)
This revision includes updates to the packaging
diagrams.
Revision E (January 2007)
This revision includes updates to the packaging
diagrams.
TABLE B-1:
DEVICE DIFFERENCES
Features
PIC18F1220
PIC18F1320
Program Memory (Bytes)
Program Memory (Instructions)
Interrupt Sources
4096
8192
2048
4096
15
Ports A, B
1
15
Ports A, B
1
I/O Ports
Enhanced Capture/Compare/PWM Modules
10-bit Analog-to-Digital Module
7 input channels
7 input channels
18-pin SDIP
18-pin SOIC
20-pin SSOP
28-pin QFN
18-pin SDIP
18-pin SOIC
20-pin SSOP
28-pin QFN
Packages
© 2007 Microchip Technology Inc.
DS39605F-page 291
PIC18F1220/1320
APPENDIX C: CONVERSION
CONSIDERATIONS
APPENDIX D: MIGRATION FROM
BASELINE TO
ENHANCED DEVICES
This appendix discusses the considerations for con-
verting from previous versions of a device to the ones
listed in this data sheet. Typically, these changes are
due to the differences in the process technology used.
An example of this type of conversion is from a
PIC16C74A to a PIC16C74B.
This section discusses how to migrate from a baseline
device (i.e., PIC16C5X) to an enhanced MCU device
(i.e., PIC18FXXX).
The following are the list of modifications over the
PIC16C5X microcontroller family:
Not Applicable
Not Currently Available
DS39605F-page 292
© 2007 Microchip Technology Inc.
PIC18F1220/1320
APPENDIX E: MIGRATION FROM
MID-RANGE TO
APPENDIX F: MIGRATION FROM
HIGH-END TO
ENHANCED DEVICES
ENHANCED DEVICES
A detailed discussion of the differences between the
mid-range MCU devices (i.e., PIC16CXXX) and the
enhanced devices (i.e., PIC18FXXX) is provided in
AN716, “Migrating Designs from PIC16C74A/74B to
PIC18C442”. The changes discussed, while device
specific, are generally applicable to all mid-range to
enhanced device migrations.
A detailed discussion of the migration pathway and
differences between the high-end MCU devices (i.e.,
PIC17CXXX) and the enhanced devices (i.e.,
PIC18FXXX) is provided in AN726, “PIC17CXXX to
PIC18CXXX Migration”.
This Application Note is available as Literature Number
DS00726.
This Application Note is available as Literature Number
DS00716.
© 2007 Microchip Technology Inc.
DS39605F-page 293
PIC18F1220/1320
NOTES:
DS39605F-page 294
© 2007 Microchip Technology Inc.
PIC18F1220/1320
INDEX
Generic I/O Port Operation ........................................ 87
Low-Voltage Detect (LVD) ....................................... 166
Low-Voltage Detect (LVD) with External Input ........ 166
MCLR/VPP/RA5 Pin ................................................... 89
On-Chip Reset Circuit ................................................ 33
OSC1/CLKI/RA7 Pin .................................................. 88
OSC2/CLKO/RA6 Pin ................................................ 88
PIC18F1220/1320 ....................................................... 7
PLL ............................................................................ 12
RA3:RA0 Pins ............................................................ 88
RA4/T0CKI Pin .......................................................... 88
RB0/AN4/INT0 Pin ..................................................... 90
RB1/AN5/TX/CK/INT1 Pin ......................................... 91
RB2/P1B/INT2 Pin ..................................................... 92
RB3/CCP1/P1A Pin ................................................... 93
RB4/AN6/RX/DT/KBI0 Pin ......................................... 94
RB5/PGM/KBI1 Pin .................................................... 95
RB6/PGC/T1OSO/T13CKI/P1C/KBI2 Pin .................. 96
RB7/PGD/T1OSI/P1D/KBI3 Pin ................................. 97
Reads from Flash Program Memory .......................... 61
System Clock ............................................................. 16
Table Read Operation ............................................... 57
Table Write Operation ................................................ 58
Table Writes to Flash Program Memory .................... 63
Timer0 in 16-Bit Mode ............................................. 100
Timer0 in 8-Bit Mode ............................................... 100
Timer1 ..................................................................... 104
Timer1 (16-Bit Read/Write Mode) ............................ 104
Timer2 ..................................................................... 110
Timer3 ..................................................................... 112
Timer3 (16-bit Read/Write Mode) ............................ 112
WDT ........................................................................ 180
BN .................................................................................... 200
BNC ................................................................................. 201
BNN ................................................................................. 201
BNOV ............................................................................... 202
BNZ .................................................................................. 202
BOR. See Brown-out Reset.
A
A/D ................................................................................... 155
A/D Converter Interrupt, Configuring ....................... 159
Acquisition Requirements ........................................ 160
ADCON0 Register .................................................... 155
ADCON1 Register .................................................... 155
ADCON2 Register .................................................... 155
ADRESH Register .................................................... 155
ADRESH/ADRESL Registers .................................. 158
ADRESL Register .................................................... 155
Analog Port Pins, Configuring .................................. 162
Associated Registers ............................................... 164
Configuring the Module ............................................ 159
Conversion Clock (Tad) ........................................... 161
Conversion Requirements ....................................... 265
Conversion Status (GO/DONE Bit) .......................... 158
Conversions ............................................................. 163
Converter Characteristics ........................................ 264
Operation in Low-Power Modes ............................... 162
Selecting, Configuring Automatic
Acquisition Time ............................................... 161
Special Event Trigger (CCP) .................................... 117
Special Event Trigger (CCP1) .................................. 164
Use of the CCP1 Trigger .......................................... 164
Vref+ and Vref- References ..................................... 160
Absolute Maximum Ratings ............................................. 237
AC (Timing) Characteristics ............................................. 255
Conditions ................................................................ 256
Load Conditions for Device
Timing Specifications ....................................... 256
Parameter Symbology ............................................. 255
Temperature and Voltage Specifications ................. 256
ADCON0 Register ............................................................ 155
GO/DONE Bit ........................................................... 158
ADCON1 Register ............................................................ 155
ADCON2 Register ............................................................ 155
ADDLW ............................................................................ 197
ADDWF ............................................................................ 197
ADDWFC ......................................................................... 198
ADRESH Register ............................................................ 155
ADRESH/ADRESL Registers ........................................... 158
ADRESL Register ............................................................ 155
Analog-to-Digital Converter. See A/D.
BOV ................................................................................. 205
BRA ................................................................................. 203
Break Character (12-bit) Transmit and Receive .............. 146
Brown-out Reset (BOR) ..............................................34, 171
BSF .................................................................................. 203
BTFSC ............................................................................. 204
BTFSS ............................................................................. 204
BTG ................................................................................. 205
BZ .................................................................................... 206
ANDLW ............................................................................ 198
ANDWF ............................................................................ 199
Assembler
MPASM Assembler .................................................. 234
Auto-Wake-up on Sync Break Character ......................... 145
C
C Compilers
B
MPLAB C18 ............................................................. 234
MPLAB C30 ............................................................. 234
CALL ................................................................................ 206
Capture (CCP Module) .................................................... 116
CCP Pin Configuration ............................................. 116
CCPR1H:CCPR1L Registers ................................... 116
Software Interrupt .................................................... 116
Timer1/Timer3 Mode Selection ................................ 116
Capture, Compare, Timer1 and Timer3
BC .................................................................................... 199
BCF .................................................................................. 200
Block Diagrams
A/D ........................................................................... 158
Analog Input Model .................................................. 159
Capture Mode Operation ......................................... 117
Compare Mode Operation ....................................... 118
Enhanced PWM ....................................................... 120
EUSART Receive .................................................... 143
EUSART Transmit ................................................... 141
Fail-Safe Clock Monitor ............................................ 182
Associated Registers ............................................... 118
© 2007 Microchip Technology Inc.
DS39605F-page 295
PIC18F1220/1320
Capture/Compare/PWM (CCP)
Data Memory ..................................................................... 47
General Purpose Registers ....................................... 47
Map for PIC18F1220/1320 Devices ........................... 48
Special Function Registers ........................................ 49
DAW ................................................................................ 210
DC and AC Characteristics
Capture Mode. See Capture.
CCP1 ........................................................................116
CCPR1H Register ............................................116
CCPR1L Register ............................................116
Compare Mode. See Compare.
Timer Resources ......................................................116
Clock Sources ....................................................................15
Selection Using OSCCON Register ...........................16
Clocking Scheme ...............................................................45
CLRF ................................................................................207
CLRWDT ..........................................................................207
Code Examples
Graphs and Tables .................................................. 267
DC Characteristics ........................................................... 250
Power-Down and Supply Current ............................ 241
Supply Voltage ......................................................... 240
DCFSNZ .......................................................................... 211
DECF ............................................................................... 210
DECFSZ .......................................................................... 211
Details on Individual Family Members ................................. 6
Development Support ...................................................... 233
Device Differences ........................................................... 291
Direct Addressing ............................................................... 54
16 x 16 Signed Multiply Routine .................................72
16 x 16 Unsigned Multiply Routine .............................72
8 x 8 Signed Multiply Routine .....................................71
8 x 8 Unsigned Multiply Routine .................................71
Changing Between Capture Prescalers ...................117
Computed GOTO Using an Offset Value ...................47
Data EEPROM Read .................................................69
Data EEPROM Refresh Routine ................................70
Data EEPROM Write ..................................................69
Erasing a Flash Program Memory Row .....................62
Fast Register Stack ....................................................44
How to Clear RAM (Bank 1) Using
E
Effects of Power Managed Modes on
Various Clock Sources .............................................. 18
Electrical Characteristics .................................................. 237
Enhanced Capture/Compare/PWM (ECCP) .................... 115
Outputs .................................................................... 116
PWM Mode. See PWM (ECCP Module).
Enhanced PWM Mode. See PWM (ECCP Module). ........ 119
Enhanced Universal Synchronous Asynchronous
Receiver Transmitter (EUSART) ............................. 131
Equations
16 x 16 Signed Multiplication Algorithm ..................... 72
16 x 16 Unsigned Multiplication Algorithm ................. 72
A/D Minimum Charging Time ................................... 160
Acquisition Time ...................................................... 160
Errata ................................................................................... 4
EUSART
Indirect Addressing ............................................53
Implementing a Real-Time Clock Using a
Timer1 Interrupt Service ..................................107
Initializing PORTA ......................................................87
Initializing PORTB ......................................................90
Reading a Flash Program Memory Word ...................61
Saving Status, WREG and
BSR Registers in RAM .......................................85
Writing to Flash Program Memory ....................... 64–65
Code Protection ...............................................................171
COMF ...............................................................................208
Compare (CCP Module) ...................................................117
CCP Pin Configuration .............................................117
CCPR1 Register .......................................................117
Software Interrupt .....................................................117
Special Event Trigger ....................................... 113, 117
Timer1/Timer3 Mode Selection ................................117
Compare (CCP1 Module)
Asynchronous Mode ................................................ 140
12-bit Break Transmit and Receive ................. 146
Associated Registers, Receive ........................ 144
Associated Registers, Transmit ....................... 142
Auto-Wake-up on Sync Break ......................... 145
Receiver .......................................................... 143
Setting up 9-bit Mode with
Address Detect ........................................ 143
Transmitter ....................................................... 140
Baud Rate Generator (BRG) ................................... 135
Associated Registers ....................................... 136
Auto-Baud Rate Detect .................................... 139
Baud Rate Error, Calculating ........................... 135
Baud Rates, Asynchronous Modes ................. 136
High Baud Rate Select (BRGH Bit) ................. 135
Power Managed Mode Operation .................... 135
Sampling .......................................................... 135
Serial Port Enable (SPEN Bit) ................................. 131
Synchronous Master Mode ...................................... 148
Associated Registers, Reception ..................... 151
Associated Registers, Transmit ....................... 149
Reception ........................................................ 150
Transmission ................................................... 148
Synchronous Slave Mode ........................................ 152
Associated Registers, Receive ........................ 153
Associated Registers, Transmit ....................... 152
Reception ........................................................ 153
Transmission ................................................... 152
Special Event Trigger ...............................................164
Computed GOTO ...............................................................47
Configuration Bits .............................................................171
Context Saving During Interrupts .......................................85
Conversion Considerations ..............................................292
CPFSEQ ..........................................................................208
CPFSGT ...........................................................................209
CPFSLT ...........................................................................209
Customer Change Notification Service ............................302
Customer Notification Service ..........................................302
Customer Support ............................................................302
D
Data EEPROM Memory .....................................................67
Associated Registers .................................................70
EEADR Register ........................................................67
EECON1 Register ......................................................67
EECON2 Register ......................................................67
Operation During Code-Protect ..................................70
Protection Against Spurious Write .............................69
Reading ......................................................................69
Using ..........................................................................70
Write Verify .................................................................69
Writing ........................................................................69
DS39605F-page 296
© 2007 Microchip Technology Inc.
PIC18F1220/1320
BRA ......................................................................... 203
BSF .......................................................................... 203
BTFSC ..................................................................... 204
BTFSS ..................................................................... 204
BTG ......................................................................... 205
BZ ............................................................................ 206
CALL ........................................................................ 206
CLRF ....................................................................... 207
CLRWDT ................................................................. 207
COMF ...................................................................... 208
CPFSEQ .................................................................. 208
CPFSGT .................................................................. 209
CPFSLT ................................................................... 209
DAW ........................................................................ 210
DCFSNZ .................................................................. 211
DECF ....................................................................... 210
DECFSZ .................................................................. 211
General Format ........................................................ 193
GOTO ...................................................................... 212
INCF ........................................................................ 212
INCFSZ .................................................................... 213
INFSNZ .................................................................... 213
IORLW ..................................................................... 214
IORWF ..................................................................... 214
LFSR ....................................................................... 215
MOVF ...................................................................... 215
MOVFF .................................................................... 216
MOVLB .................................................................... 216
MOVLW ................................................................... 217
MOVWF ................................................................... 217
MULLW .................................................................... 218
MULWF .................................................................... 218
NEGF ....................................................................... 219
NOP ......................................................................... 219
POP ......................................................................... 220
PUSH ....................................................................... 220
RCALL ..................................................................... 221
RESET ..................................................................... 221
RETFIE .................................................................... 222
RETLW .................................................................... 222
RETURN .................................................................. 223
RLCF ....................................................................... 223
RLNCF ..................................................................... 224
RRCF ....................................................................... 224
RRNCF .................................................................... 225
SETF ....................................................................... 225
SLEEP ..................................................................... 226
SUBFWB ................................................................. 226
SUBLW .................................................................... 227
SUBWF .................................................................... 227
SUBWFB ................................................................. 228
SWAPF .................................................................... 228
TBLRD ..................................................................... 229
TBLWT .................................................................... 230
TSTFSZ ................................................................... 231
XORLW ................................................................... 231
XORWF ................................................................... 232
Summary Table ....................................................... 194
F
Fail-Safe Clock Monitor .................................................... 171
Exiting Operation ..................................................... 183
Interrupts in Power Managed Modes ....................... 183
POR or Wake from Sleep ........................................ 184
WDT During Oscillator Failure ................................. 182
Fail-Safe Clock Monitor (FSCM) ...................................... 182
Fast Register Stack ............................................................ 44
Firmware Instructions ....................................................... 191
Flash Program Memory ...................................................... 57
Associated Registers ................................................. 65
Control Registers ....................................................... 58
Erase Sequence ........................................................ 62
Erasing ....................................................................... 62
Operation During Code-Protect ................................. 65
Reading ...................................................................... 61
Table Latch ................................................................ 60
Table Pointer .............................................................. 60
Boundaries Based on Operation ........................ 60
Table Pointer Boundaries .......................................... 60
Table Reads and Table Writes .................................. 57
Write Sequence ......................................................... 63
Writing to .................................................................... 63
Unexpected Termination .................................... 65
Write Verify ........................................................ 65
G
GOTO ............................................................................... 212
H
Hardware Multiplier ............................................................ 71
Introduction ................................................................ 71
Operation ................................................................... 71
Performance Comparison .......................................... 71
I
I/O Ports ............................................................................. 87
ID Locations ............................................................. 171, 188
INCF ................................................................................. 212
INCFSZ ............................................................................ 213
In-Circuit Debugger .......................................................... 188
In-Circuit Serial Programming (ICSP) ...................... 171, 188
Indirect Addressing ............................................................ 54
INDF and FSR Registers ........................................... 53
Operation ................................................................... 53
Indirect Addressing Operation ............................................ 54
Indirect File Operand .......................................................... 47
INFSNZ ............................................................................ 213
Initialization Conditions for All Registers ...................... 36–38
Instruction Cycle ................................................................. 45
Instruction Flow/Pipelining ................................................. 45
Instruction Set .................................................................. 191
ADDLW .................................................................... 197
ADDWF .................................................................... 197
ADDWFC ................................................................. 198
ANDLW .................................................................... 198
ANDWF .................................................................... 199
BC ............................................................................ 199
BCF .......................................................................... 200
BN ............................................................................ 200
BNC ......................................................................... 201
BNN ......................................................................... 201
BNOV ....................................................................... 202
BNZ .......................................................................... 202
BOV ......................................................................... 205
INTCON Register
RBIF Bit ..................................................................... 90
INTCON Registers ............................................................. 75
© 2007 Microchip Technology Inc.
DS39605F-page 297
PIC18F1220/1320
Internal Oscillator Block .....................................................14
Adjustment .................................................................14
INTIO Modes ..............................................................14
INTRC Output Frequency ..........................................14
OSCTUNE Register ...................................................14
Internal RC Oscillator
MPLAB PM3 Device Programmer ................................... 235
MPLAB REAL ICE In-Circuit Emulator System ................ 235
MPLINK Object Linker/MPLIB Object Librarian ............... 234
MULLW ............................................................................ 218
MULWF ............................................................................ 218
N
Use with WDT ..........................................................180
Internet Address ...............................................................302
Interrupt Sources ..............................................................171
A/D Conversion Complete ........................................159
Capture Complete (CCP) .........................................116
Compare Complete (CCP) .......................................117
Interrupt-on-Change (RB7:RB4) ................................90
INTn Pin .....................................................................85
PORTB, Interrupt-on-Change ....................................85
TMR0 .........................................................................85
TMR0 Overflow ........................................................101
TMR1 Overflow ........................................................103
TMR2 to PR2 Match .................................................110
TMR2 to PR2 Match (PWM) ............................ 109, 119
TMR3 Overflow ................................................ 111, 113
Interrupts ............................................................................73
Enable Bits
NEGF ............................................................................... 219
New Core Features
Multiple Oscillator Options and Features ..................... 5
nanoWatt Technology .................................................. 5
NOP ................................................................................. 219
O
Opcode Field Descriptions ............................................... 192
OPTION_REG Register
PSA Bit .................................................................... 101
T0CS Bit .................................................................. 101
T0PS2:T0PS0 Bits ................................................... 101
T0SE Bit ................................................................... 101
Oscillator Configuration ...................................................... 11
Crystal/Ceramic Resonator ........................................ 11
EC .............................................................................. 11
ECIO .......................................................................... 11
External Clock Input ................................................... 13
HS .............................................................................. 11
HSPLL ..................................................................11, 12
INTIO1 ....................................................................... 11
INTIO2 ....................................................................... 11
LP .............................................................................. 11
RC .........................................................................11, 13
RCIO .......................................................................... 11
XT .............................................................................. 11
Oscillator Selection .......................................................... 171
Oscillator Start-up Timer (OST) ............................18, 34, 171
Oscillator Switching ............................................................ 15
Oscillator Transitions ......................................................... 18
Oscillator, Timer1 ......................................................103, 113
Oscillator, Timer3 ............................................................. 111
Other Special Features ........................................................ 5
(CCP1IE Bit) ....................................................116
Flag Bits
CCP1 Flag (CCP1IF Bit) ..................................116
CCP1IF Flag (CCP1IF Bit) ...............................117
Interrupt-on-Change (RB7:RB4)
Flag (RBIF Bit) ...........................................90
Logic ...........................................................................74
INTOSC Frequency Drift ....................................................30
IORLW .............................................................................214
IORWF .............................................................................214
IPR Registers .....................................................................82
L
LFSR ................................................................................215
Low-Voltage Detect ..........................................................165
Characteristics .........................................................253
Effects of a Reset .....................................................169
Operation .................................................................168
Current Consumption .......................................169
P
Packaging ........................................................................ 285
Details ...................................................................... 286
Marking Information ................................................. 285
PICSTART Plus Development Programmer .................... 236
PIE Registers ..................................................................... 80
Pin Functions
Reference Voltage Set Point ............................169
Operation During Sleep ............................................169
LVD. See Low-Voltage Detect. ........................................165
M
Memory Organization .........................................................41
Data Memory ..............................................................47
Program Memory .......................................................41
Memory Programming Requirements ..............................252
Microchip Internet Web Site .............................................302
Migration from Baseline to Enhanced Devices ................292
Migration from High-End to Enhanced Devices ...............293
Migration from Mid-Range to Enhanced Devices .............293
MOVF ...............................................................................215
MOVFF .............................................................................216
MOVLB .............................................................................216
MOVLW ............................................................................217
MOVWF ...........................................................................217
MPLAB ASM30 Assembler, Linker, Librarian ..................234
MPLAB ICD 2 In-Circuit Debugger ...................................235
MPLAB ICE 2000 High-Performance
MCLR/Vpp/RA5 ........................................................... 8
OSC1/CLKI/RA7 .......................................................... 8
OSC2/CLKO/RA6 ........................................................ 8
RA0/AN0 ...................................................................... 8
RA1/AN1/LVDIN .......................................................... 8
RA2/AN2/Vref- ............................................................. 8
RA3/AN3/VREF+ ........................................................... 8
RA4/T0CKI ................................................................... 8
RB0/AN4/INT0 ............................................................. 9
RB1/AN5/TX/CK/INT1 ................................................. 9
RB2/P1B/INT2 ............................................................. 9
RB3/CCP1/P1A ........................................................... 9
RB4/AN6/RX/DT/KBI0 ................................................. 9
RB5/PGM/KBI1 ............................................................ 9
RB6/PGC/T1OSO/T13CKI/P1C/KBI2 .......................... 9
RB7/PGD/T1OSI/P1D/KBI3 ......................................... 9
Vdd .............................................................................. 9
Vss ............................................................................... 9
Universal In-Circuit Emulator ...................................235
MPLAB Integrated Development
Environment Software ..............................................233
DS39605F-page 298
© 2007 Microchip Technology Inc.
PIC18F1220/1320
Pinout I/O Descriptions
Duty Cycle ............................................................... 119
Example Frequencies/Resolutions .......................... 119
Period ...................................................................... 119
TMR2 to PR2 Match .........................................109, 119
PWM (ECCP Module) ...................................................... 119
Associated Registers ............................................... 130
Direction Change in Full-Bridge Output Mode ......... 124
Effects of a Reset .................................................... 129
Enhanced PWM Auto-Shutdown ............................. 126
Full-Bridge Application Example .............................. 124
Full-Bridge PWM Output (Active-High) Diagram ..... 123
Half-Bridge Output (Active-High) Diagram ............... 122
Half-Bridge Output Mode Applications Example ...... 122
Operation in Low-Power Modes .............................. 129
Output Configurations .............................................. 119
Output Relationships (Active-High) .......................... 120
Output Relationships (Active-Low) .......................... 121
Programmable Dead-Band Delay ............................ 126
PWM Direction Change (Active-High) Diagram ....... 125
PWM Direction Change at Near
PIC18F1220/1320 ........................................................ 8
PIR Registers ..................................................................... 78
PLL Lock Time-out ............................................................. 34
Pointer, FSR ....................................................................... 53
POP .................................................................................. 220
POR. See Power-on Reset.
PORTA
Associated Registers ................................................. 89
Functions ................................................................... 89
LATA Register ............................................................ 87
PORTA Register ........................................................ 87
TRISA Register .......................................................... 87
PORTB
Associated Registers ................................................. 98
Functions ................................................................... 98
LATB Register ............................................................ 90
PORTB Register ........................................................ 90
RB7:RB4 Interrupt-on-Change Flag
(RBIF Bit) ........................................................... 90
TRISB Register .......................................................... 90
Postscaler
100% Duty Cycle (Active-High) Diagram ......... 125
Setup for PWM Operation ........................................ 129
Start-up Considerations ........................................... 128
Timer2 ...................................................................... 109
WDT
Q
Assignment (PSA Bit) ...................................... 101
Rate Select (T0PS2:T0PS0 Bits) ..................... 101
Power Managed Modes ..................................................... 19
Comparison between Run and Idle Modes ................ 20
Entering ...................................................................... 20
Idle Modes ................................................................. 21
Multiple Sleep Commands ......................................... 20
Run Modes ................................................................. 26
Selecting .................................................................... 19
Sleep Mode ................................................................ 21
Summary (table) ........................................................ 19
Wake from .................................................................. 28
Power-on Reset (POR) .............................................. 34, 171
Power-up Delays ................................................................ 18
Power-up Timer (PWRT) .......................................18, 34, 171
Prescaler
Capture .................................................................... 117
Timer0 ...................................................................... 101
Assignment (PSA Bit) ...................................... 101
Rate Select (T0PS2:T0PS0 Bits) ..................... 101
Timer2 ...................................................................... 119
Product Identification System ........................................... 304
Program Counter
Q Clock ............................................................................ 119
R
RAM. See Data Memory.
RCALL ............................................................................. 221
RCIO Oscillator .................................................................. 13
RCON Register
Bit Status During Initialization .................................... 35
RCSTA Register
SPEN Bit .................................................................. 131
Reader Response ............................................................ 303
Register File ....................................................................... 47
Register File Summary .................................................50–51
Registers
ADCON0 (A/D Control 0) ......................................... 155
ADCON1 (A/D Control 1) ......................................... 156
ADCON2 (A/D Control 2) ......................................... 157
BAUDCTL (Baud Rate Control) ............................... 134
CCP1CON (Enhanced CCP1 Control) .................... 115
CONFIG1H (Configuration 1 High) .......................... 172
CONFIG2H (Configuration 2 High) .......................... 174
CONFIG2L (Configuration 2 Low) ........................... 173
CONFIG3H (Configuration 3 High) .......................... 175
CONFIG4L (Configuration 4 Low) ........................... 175
CONFIG5H (Configuration 5 High) .......................... 176
CONFIG5L (Configuration 5 Low) ........................... 176
CONFIG6H (Configuration 6 High) .......................... 177
CONFIG6L (Configuration 6 Low) ........................... 177
CONFIG7H (Configuration 7 High) .......................... 178
CONFIG7L (Configuration 7 Low) ........................... 178
DEVID1 (Device ID 1) .............................................. 179
DEVID2 (Device ID 2) .............................................. 179
ECCPAS (ECCP Auto-Shutdown Control) .............. 127
EECON1 (Data EEPROM Control 1) ....................59, 68
INTCON (Interrupt Control) ........................................ 75
INTCON2 (Interrupt Control 2) ................................... 76
INTCON3 (Interrupt Control 3) ................................... 77
IPR1 (Peripheral Interrupt Priority 1) ......................... 82
IPR2 (Peripheral Interrupt Priority 2) ......................... 83
LVDCON (LVD Control) ........................................... 167
OSCCON (Oscillator Control) .................................... 17
PCL Register .............................................................. 44
PCLATH Register ...................................................... 44
PCLATU Register ...................................................... 44
Program Memory
Instructions in ............................................................. 46
Interrupt Vector .......................................................... 41
Map and Stack for PIC18F1220 ................................. 41
Map and Stack for PIC18F1320 ................................. 41
Reset Vector .............................................................. 41
Program Verification and Code Protection ....................... 185
Associated Registers ............................................... 185
Configuration Register ............................................. 188
Data EEPROM ......................................................... 188
Program Memory ..................................................... 186
Programming, Device Instructions ................................... 191
PUSH ............................................................................... 220
PUSH and POP Instructions .............................................. 43
PWM (CCP Module)
CCPR1H:CCPR1L Registers ................................... 119
© 2007 Microchip Technology Inc.
DS39605F-page 299
PIC18F1220/1320
OSCTUNE (Oscillator Tuning) ...................................15
PIE1 (Peripheral Interrupt Enable 1) ..........................80
PIE2 (Peripheral Interrupt Enable 2) ..........................81
PIR1 (Peripheral Interrupt Request (Flag) 1) .............78
PIR2 (Peripheral Interrupt Request (Flag) 2) .............79
PWM1CON (PWM Configuration) ............................126
RCON (Reset Control) ......................................... 56, 84
RCSTA (Receive Status and Control) ......................133
Status .........................................................................55
STKPTR (Stack Pointer) ............................................43
T0CON (Timer0 Control) ............................................99
T1CON (Timer 1 Control) .........................................103
T2CON (Timer 2 Control) .........................................109
T3CON (Timer3 Control) ..........................................111
TXSTA (Transmit Status and Control) .....................132
WDTCON (Watchdog Timer Control) .......................180
RESET .............................................................................221
Reset .......................................................................... 33, 171
RETFIE ............................................................................222
RETLW .............................................................................222
RETURN ..........................................................................223
Return Address Stack ........................................................42
and Associated Registers ..........................................42
Return Stack Pointer (STKPTR) ........................................42
Revision History ...............................................................291
RLCF ................................................................................223
RLNCF .............................................................................224
RRCF ...............................................................................224
RRNCF .............................................................................225
Timer1 .............................................................................. 103
16-Bit Read/Write Mode .......................................... 106
Associated Registers ............................................... 108
Interrupt ................................................................... 106
Operation ................................................................. 104
Oscillator ...........................................................103, 105
Layout Considerations ..................................... 106
Overflow Interrupt .................................................... 103
Resetting, Using a Special Event Trigger
Output (CCP) ................................................... 106
Special Event Trigger (CCP) ................................... 117
TMR1H Register ...................................................... 103
TMR1L Register ....................................................... 103
Use as a Real-Time Clock ....................................... 107
Timer2 .............................................................................. 109
Associated Registers ............................................... 110
Operation ................................................................. 109
Output ...................................................................... 110
Postscaler. See Postscaler, Timer2.
PR2 Register ....................................................109, 119
Prescaler. See Prescaler, Timer2.
TMR2 Register ......................................................... 109
TMR2 to PR2 Match Interrupt ...................109, 110, 119
Timer3 .............................................................................. 111
Associated Registers ............................................... 113
Operation ................................................................. 112
Oscillator ...........................................................111, 113
Overflow Interrupt .............................................111, 113
Special Event Trigger (CCP) ................................... 113
TMR3H Register ...................................................... 111
TMR3L Register ....................................................... 111
Timing Diagrams
S
SETF ................................................................................225
SLEEP ..............................................................................226
Sleep
OSC1 and OSC2 Pin States ......................................18
Software Simulator (MPLAB SIM) ....................................234
Special Event Trigger. See Compare
A/D Conversion ........................................................ 265
Asynchronous Reception ......................................... 144
Asynchronous Transmission .................................... 141
Asynchronous Transmission (Back to Back) ........... 142
Auto-Wake-up Bit (WUE) During
Special Features of the CPU ............................................171
Configuration Registers .................................... 172–178
Special Function Registers ................................................49
Map ............................................................................49
Stack Full/Underflow Resets ..............................................43
SUBFWB ..........................................................................226
SUBLW ............................................................................227
SUBWF ............................................................................227
SUBWFB ..........................................................................228
SWAPF ............................................................................228
Normal Operation ............................................ 145
Auto-Wake-up Bit (WUE) During Sleep ................... 145
Brown-out Reset (BOR) ........................................... 260
Capture/Compare/PWM (All CCP Modules) ............ 262
CLKO and I/O .......................................................... 259
Clock/Instruction Cycle .............................................. 45
EUSART Synchronous Receive
(Master/Slave) ................................................. 264
EUSART SynchronousTransmission
(Master/Slave) ................................................. 263
External Clock (All Modes Except PLL) ................... 257
Fail-Safe Clock Monitor ........................................... 183
Low-Voltage Detect ................................................. 168
Low-Voltage Detect Characteristics ......................... 253
PWM Auto-Shutdown (PRSEN = 0,
T
TABLAT Register ...............................................................60
Table Pointer Operations (table) ........................................60
TBLPTR Register ...............................................................60
TBLRD .............................................................................229
TBLWT .............................................................................230
Time-out Sequence ............................................................34
Timer0 ................................................................................99
16-Bit Mode Timer Reads and Writes ......................101
Associated Registers ...............................................101
Clock Source Edge Select (T0SE Bit) ......................101
Clock Source Select (T0CS Bit) ...............................101
Operation .................................................................101
Overflow Interrupt .....................................................101
Prescaler. See Prescaler, Timer0.
Auto-Restart Disabled) .................................... 128
PWM Auto-Shutdown (PRSEN = 1,
Auto-Restart Enabled) ..................................... 128
Reset, Watchdog Timer (WDT), Oscillator Start-up
Timer (OST) and Power-up Timer (PWRT) ..... 260
Send Break Character Sequence ............................ 147
Slow Rise Time (MCLR Tied to VDD,
VDD Rise > TPWRT) ............................................ 40
Synchronous Reception
(Master Mode, SREN) ..................................... 150
Synchronous Transmission ..................................... 148
Synchronous Transmission (Through TXEN) .......... 149
Switching Prescaler Assignment ..............................101
DS39605F-page 300
© 2007 Microchip Technology Inc.
PIC18F1220/1320
Time-out Sequence on POR w/PLL Enabled
(MCLR Tied to VDD) ........................................... 40
Time-out Sequence on Power-up
(MCLR Not Tied to Vdd), Case 1 ....................... 39
Time-out Sequence on Power-up
Top-of-Stack Access .......................................................... 42
TSTFSZ ........................................................................... 231
Two-Speed Start-up ..................................................171, 181
Two-Word Instructions ....................................................... 46
Example Cases .......................................................... 46
TXSTA Register
(MCLR Not Tied to Vdd), Case 2 ....................... 39
Time-out Sequence on Power-up
BRGH Bit ................................................................. 135
(MCLR Tied to Vdd, Vdd Rise pwrt) ................... 39
Timer0 and Timer1 External Clock .......................... 261
Transition for Entry to SEC_IDLE Mode .................... 24
Transition for Entry to SEC_RUN Mode .................... 26
Transition for Entry to Sleep Mode ............................ 22
Transition for Two-Speed Start-up
(INTOSC to HSPLL) ......................................... 181
Transition for Wake from PRI_IDLE Mode ................. 23
Transition for Wake from RC_RUN Mode
W
Watchdog Timer (WDT) ............................................171, 180
Associated Registers ............................................... 181
Control Register ....................................................... 180
During Oscillator Failure .......................................... 182
Programming Considerations .................................. 180
WWW Address ................................................................ 302
WWW, On-Line Support ...................................................... 4
(RC_RUN to PRI_RUN) ..................................... 25
Transition for Wake from SEC_RUN Mode
X
XORLW ............................................................................ 231
XORWF ........................................................................... 232
(HSPLL) ............................................................. 24
Transition for Wake from Sleep (HSPLL) ................... 22
Transition to PRI_IDLE Mode .................................... 23
Transition to RC_IDLE Mode ..................................... 25
Transition to RC_RUN Mode ..................................... 27
Timing Diagrams and Specifications ................................ 257
Capture/Compare/PWM Requirements
(All CCP Modules) ........................................... 263
CLKO and I/O Requirements ................................... 259
EUSART Synchronous Receive Requirements ....... 264
EUSART Synchronous
Transmission Requirements ............................ 263
External Clock Requirements .................................. 257
Internal RC Accuracy ............................................... 258
PLL Clock, HS/HSPLL Mode
(VDD = 4.2V to 5.5V) ........................................ 258
Reset, Watchdog Timer, Oscillator
Start-up Timer, Power-up Timer and
Brown-out Reset Requirements ....................... 261
Timer0 and Timer1 External Clock
Requirements ................................................... 262
© 2007 Microchip Technology Inc.
DS39605F-page 301
PIC18F1220/1320
NOTES:
DS39605F-page 302
© 2007 Microchip Technology Inc.
PIC18F1220/1320
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CUSTOMER SUPPORT
Microchip provides online support via our WWW site at
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Technical support is available through the web site
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To register, access the Microchip web site at
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© 2007 Microchip Technology Inc.
DS39605F-page 303
PIC18F1220/1320
READER RESPONSE
It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip prod-
uct. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation
can better serve you, please FAX your comments to the Technical Publications Manager at (480) 792-4150.
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PIC18F1220/1320
DS39605F
Literature Number:
Device:
Questions:
1. What are the best features of this document?
2. How does this document meet your hardware and software development needs?
3. Do you find the organization of this document easy to follow? If not, why?
4. What additions to the document do you think would enhance the structure and subject?
5. What deletions from the document could be made without affecting the overall usefulness?
6. Is there any incorrect or misleading information (what and where)?
7. How would you improve this document?
DS39605F-page 304
© 2007 Microchip Technology Inc.
PIC18F1220/1320
PIC18F1220/1320 PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
X
/XX
XXX
PART NO.
Device
−
Examples:
Temperature Package
Range
Pattern
a) PIC18LF1320-I/P 301 = Industrial
temp., PDIP package, Extended
VDD limits, QTP pattern #301.
(1)
b) PIC18LF1220-I/SO
=
Industrial
Device
PIC18F1220/1320
PIC18F1220/1320T
,
(2)
temp., SOIC package, Extended
VDD limits.
;
VDD range 4.2V to 5.5V
(1)
PIC18LF1220/1320
PIC18LF1220/1320T
,
(2)
;
VDD range 2.5V to 5.5V
Note 1: F = Standard Voltage range
Temperature
Range
I
E
=
=
-40°C to +85°C (Industrial)
-40°C to +125°C (Extended)
LF = Wide Voltage Range
2:
T
= in tape and reel – SOIC
package only
Package
Pattern
SO = SOIC
PDIP
SS = SSOP
ML = QFN
P
=
QTP, SQTP, Code or Special Requirements
(blank otherwise)
© 2007 Microchip Technology Inc.
DS39605F-page 305
WORLDWIDE SALES AND SERVICE
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12/08/06
DS39605F-page 306
© 2007 Microchip Technology Inc.
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