PIC18LF4450T-I/P [MICROCHIP]
28/40/44-Pin, High-Performance, 12 MIPS, Enhanced Flash, USB Microcontrollers with nanoWatt Technology; 28 /40/ 44引脚,高性能, 12 MIPS ,增强型闪存, USB微控制器采用纳瓦技术型号: | PIC18LF4450T-I/P |
厂家: | MICROCHIP |
描述: | 28/40/44-Pin, High-Performance, 12 MIPS, Enhanced Flash, USB Microcontrollers with nanoWatt Technology |
文件: | 总324页 (文件大小:5692K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
PIC18F2450/4450
Data Sheet
24/40/44-Pin High-Performance,
12 MIPS, Enhanced Flash,
USB Microcontrollers
with nanoWatt Technology
© 2008 Microchip Technology Inc.
DS39760D
Note the following details of the code protection feature on Microchip devices:
•
Microchip products meet the specification contained in their particular Microchip Data Sheet.
•
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
•
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
•
•
Microchip is willing to work with the customer who is concerned about the integrity of their code.
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION,
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
QUALITY, PERFORMANCE, MERCHANTABILITY OR
FITNESS FOR PURPOSE. Microchip disclaims all liability
arising from this information and its use. Use of Microchip
devices in life support and/or safety applications is entirely at
the buyer’s risk, and the buyer agrees to defend, indemnify and
hold harmless Microchip from any and all damages, claims,
suits, or expenses resulting from such use. No licenses are
conveyed, implicitly or otherwise, under any Microchip
intellectual property rights.
Trademarks
The Microchip name and logo, the Microchip logo, Accuron,
dsPIC, KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro,
PICSTART, PRO MATE, rfPIC and SmartShunt are registered
trademarks of Microchip Technology Incorporated in the
U.S.A. and other countries.
FilterLab, Linear Active Thermistor, MXDEV, MXLAB,
SEEVAL, SmartSensor and The Embedded Control Solutions
Company are registered trademarks of Microchip Technology
Incorporated in the U.S.A.
Analog-for-the-Digital Age, Application Maestro, CodeGuard,
dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN,
ECONOMONITOR, FanSense, In-Circuit Serial
Programming, ICSP, ICEPIC, Mindi, MiWi, MPASM, MPLAB
Certified logo, MPLIB, MPLINK, mTouch, PICkit, PICDEM,
32
PICDEM.net, PICtail, PIC logo, PowerCal, PowerInfo,
PowerMate, PowerTool, REAL ICE, rfLAB, Select Mode, Total
Endurance, UNI/O, WiperLock and ZENA are trademarks of
Microchip Technology Incorporated in the U.S.A. and other
countries.
SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.
All other trademarks mentioned herein are property of their
respective companies.
© 2008, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.
Printed on recycled paper.
Microchip received ISO/TS-16949:2002 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
DS39760D-page ii
© 2008 Microchip Technology Inc.
PIC18F2450/4450
28/40/44-Pin High-Performance, 12 MIPS, Enhanced Flash,
USB Microcontrollers with nanoWatt Technology
Universal Serial Bus Features:
Peripheral Highlights:
• USB V2.0 Compliant
• High-Current Sink/Source: 25 mA/25 mA
• Three External Interrupts
• Low Speed (1.5 Mb/s) and Full Speed (12 Mb/s)
• Supports Control, Interrupt, Isochronous and
Bulk Transfers
• Three Timer modules (Timer0 to Timer2)
• Capture/Compare/PWM (CCP) module:
- Capture is 16-bit, max. resolution 5.2 ns
- Compare is 16-bit, max. resolution 83.3 ns
- PWM output: PWM resolution is 1 to 10-bit
• Enhanced USART module:
• Supports Up to 32 Endpoints (16 bidirectional)
• 256-Byte Dual Access RAM for USB
• On-Chip USB Transceiver with On-Chip Voltage
Regulator
• Interface for Off-Chip USB Transceiver
- LIN bus support
• 10-Bit, Up to 13-Channel Analog-to-Digital Converter
module (A/D):
Power-Managed Modes:
- Up to 100 ksps sampling rate
- Programmable acquisition time
• Run: CPU on, Peripherals on
• Idle: CPU off, Peripherals on
• Sleep: CPU off, Peripherals off
Special Microcontroller Features:
• Idle mode Currents Down to 5.8 μA Typical
• Sleep mode Currents Down to 0.1 μA Typical
• Timer1 Oscillator: 1.8 μA Typical, 32 kHz, 2V
• Watchdog Timer: 2.1 μA Typical
• C Compiler Optimized Architecture with Optional
Extended Instruction Set
• Flash Memory Retention: > 40 Years
• Self-Programmable under Software Control
• Priority Levels for Interrupts
• Two-Speed Oscillator Start-up
• 8 x 8 Single-Cycle Hardware Multiplier
• Extended Watchdog Timer (WDT):
- Programmable period from 4 ms to 131s
• Programmable Code Protection
Flexible Oscillator Structure:
• Four Crystal modes, including High-Precision PLL
for USB
• Two External Clock modes, up to 48 MHz
• Internal 31 kHz Oscillator
• Single-Supply In-Circuit Serial Programming™
(ICSP™) via Two Pins
• Secondary Oscillator using Timer1 @ 32 kHz
• In-Circuit Debug (ICD) via Two Pins
• Dual Oscillator Options allow Microcontroller and
USB module to Run at Different Clock Speeds
• Optional Dedicated ICD/ICSP Port
(44-pin TQFP devices only)
• Fail-Safe Clock Monitor:
• Wide Operating Voltage Range (2.0V to 5.5V)
- Allows for safe shutdown if any clock stops
Program Memory
Data
Memory
SRAM
(bytes)
10-Bit A/D
(ch)
Timers
8/16-Bit
Device
I/O
CCP
EUSART
Flash
(bytes)
# Single-Word
Instructions
PIC18F2450
PIC18F4450
16K
16K
8192
8192
768*
768*
23
34
10
13
1
1
1
1
1/2
1/2
*
Includes 256 bytes of dual access RAM used by USB module and shared with data memory.
© 2008 Microchip Technology Inc.
DS39760D-page 1
PIC18F2450/4450
Pin Diagrams
28-Pin SPDIP, SOIC
MCLR/VPP/RE3
RA0/AN0
1
2
28
27
26
25
24
23
22
21
20
19
18
17
16
15
RB7/KBI3/PGD
RB6/KBI2/PGC
RB5/KBI1/PGM
RB4/AN11/KBI0
RB3/AN9/VPO
RB2/AN8/INT2/VMO
RB1/AN10/INT1
RB0/AN12/INT0
VDD
RA1/AN1
3
4
5
RA2/AN2/VREF-
RA3/AN3/VREF+
RA4/T0CKI/RCV
RA5/AN4/HLVDIN
VSS
6
7
8
9
OSC1/CLKI
OSC2/CLKO/RA6
RC0/T1OSO/T1CKI
RC1/T1OSI/UOE
RC2/CCP1
10
11
12
13
14
VSS
RC7/RX/DT
RC6/TX/CK
RC5/D+/VP
RC4/D-/VM
VUSB
28-Pin QFN
28272625242322
RA2/AN2/VREF-
RA3/AN3/VREF+
RA4/T0CKI/RCV
RA5/AN4/HLVDIN
VSS
1
2
3
4
5
6
7
21
RB3/AN9/VPO
RB2/AN8/INT2/VMO
RB1/AN10/INT1
RB0/AN12/INT0
VDD
20
19
18
17
16
15
PIC18F2450
OSC1/CLKI
OSC2/CLKO/RA6
VSS
RC7/RX/DT
8
9 10 111213 14
DS39760D-page 2
© 2008 Microchip Technology Inc.
PIC18F2450/4450
Pin Diagrams (Continued)
40-Pin PDIP
MCLR/VPP/RE3
1
2
3
4
5
6
7
8
RB7/KBI3/PGD
RB6/KBI2/PGC
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
RA0/AN0
RA1/AN1
RA2/AN2/VREF-
RB5/KBI1/PGM
RB4/AN11/KBI0
RB3/AN9/VPO
RA3/AN3/VREF+
RA4/T0CKI/RCV
RB2/AN8/INT2/VMO
RA5/AN4/HLVDIN
RE0/AN5
RB1/AN10/INT1
RB0/AN12/INT0
VDD
RE1/AN6
RE2/AN7
9
10
11
12
13
14
15
16
17
18
19
20
VSS
VDD
VSS
RD7
RD6
RD5
RD4
RC7/RX/DT
RC6/TX/CK
RC5/D+/VP
OSC1/CLKI
OSC2/CLKO/RA6
RC0/T1OSO/T1CKI
RC1/T1OSI/UOE
RC2/CCP1
VUSB
RD0
RC4/D-/VM
RD3
RD1
RD2
44-Pin QFN
1
2
3
4
5
6
7
8
9
33
32
31
30
29
28
27
26
25
24
23
OSC2/CLKO/RA6
OSC1/CLKI
VSS
AVSS
VDD
RC7/RX/DT
RD4
RD5
RD6
RD7
VSS
PIC18F4450
AVDD
RE2/AN7
RE1/AN6
RE0/AN5
RA5/AN4/HLVDIN
RA4/T0CKI/RCV
AVDD
VDD
RB0/AN12/INT0
RB1/AN10/INT1
RB2/AN8/INT2/VMO
10
11
© 2008 Microchip Technology Inc.
DS39760D-page 3
PIC18F2450/4450
Pin Diagrams (Continued)
44-Pin TQFP
(1)
NC/ICRST(1)/ICVPP
RC7/RX/DT
1
2
3
4
5
6
7
8
9
10
11
33
32
31
30
29
28
27
26
25
24
23
RC0/T1OSO/T1CKI
OSC2/CLKO/RA6
OSC1/CLKI
VSS
RD4
RD5
RD6
RD7
VSS
VDD
PIC18F4450
VDD
RE2/AN7
RE1/AN6
RE0/AN5
RA5/AN4/HLVDIN
RA4/T0CKI/RCV
RB0/AN12/INT0
RB1/AN10/INT1
RB2/AN8/INT2/VMO
RB3/AN9/VPO
Note 1: Special ICPORT features are available in select circumstances. For more information, see
Section 18.9 “Special ICPORT Features (Designated Packages Only)”.
DS39760D-page 4
© 2008 Microchip Technology Inc.
PIC18F2450/4450
Table of Contents
1.0 Device Overview .......................................................................................................................................................................... 7
2.0 Oscillator Configurations ............................................................................................................................................................ 23
3.0 Power-Managed Modes ............................................................................................................................................................. 33
4.0 Reset.......................................................................................................................................................................................... 41
5.0 Memory Organization................................................................................................................................................................. 53
6.0 Flash Program Memory.............................................................................................................................................................. 73
7.0 8 x 8 Hardware Multiplier............................................................................................................................................................ 83
8.0 Interrupts .................................................................................................................................................................................... 85
9.0 I/O Ports ..................................................................................................................................................................................... 99
10.0 Timer0 Module ......................................................................................................................................................................... 111
11.0 Timer1 Module ......................................................................................................................................................................... 115
12.0 Timer2 Module ......................................................................................................................................................................... 121
13.0 Capture/Compare/PWM (CCP) Module ................................................................................................................................... 123
14.0 Universal Serial Bus (USB) ...................................................................................................................................................... 129
15.0 Enhanced Universal Synchronous Receiver Transmitter (EUSART)....................................................................................... 153
16.0 10-Bit Analog-to-Digital Converter (A/D) Module ..................................................................................................................... 175
17.0 High/Low-Voltage Detect (HLVD)............................................................................................................................................. 185
18.0 Special Features of the CPU.................................................................................................................................................... 191
19.0 Instruction Set Summary.......................................................................................................................................................... 213
20.0 Development Support............................................................................................................................................................... 263
21.0 Electrical Characteristics.......................................................................................................................................................... 267
22.0 Packaging Information.............................................................................................................................................................. 295
Appendix A: Revision History............................................................................................................................................................. 307
Appendix B: Device Differences ........................................................................................................................................................ 308
Appendix C: Conversion Considerations ........................................................................................................................................... 309
Appendix D: Migration From Baseline to Enhanced Devices ............................................................................................................ 309
Appendix E: Migration From Mid-Range to Enhanced Devices......................................................................................................... 310
Appendix F: Migration From High-End to Enhanced Devices............................................................................................................ 310
Index ................................................................................................................................................................................................. 311
The Microchip Web Site..................................................................................................................................................................... 319
Customer Change Notification Service .............................................................................................................................................. 319
Customer Support.............................................................................................................................................................................. 319
Reader Response.............................................................................................................................................................................. 320
Product Identification System ............................................................................................................................................................ 321
© 2008 Microchip Technology Inc.
DS39760D-page 5
PIC18F2450/4450
TO OUR VALUED CUSTOMERS
It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip
products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and
enhanced as new volumes and updates are introduced.
If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via
E-mail at docerrors@microchip.com or fax the Reader Response Form in the back of this data sheet to (480) 792-4150. We
welcome your feedback.
Most Current Data Sheet
To obtain the most up-to-date version of this data sheet, please register at our Worldwide Web site at:
http://www.microchip.com
You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page.
The last character of the literature number is the version number, (e.g., DS30000A is version A of document DS30000).
Errata
An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current
devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision
of silicon and revision of document to which it applies.
To determine if an errata sheet exists for a particular device, please check with one of the following:
•
•
Microchip’s Worldwide Web site; http://www.microchip.com
Your local Microchip sales office (see last page)
When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are
using.
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Register on our web site at www.microchip.com to receive the most current information on all of our products.
DS39760D-page 6
© 2008 Microchip Technology Inc.
PIC18F2450/4450
1.1.3
MULTIPLE OSCILLATOR OPTIONS
AND FEATURES
1.0
DEVICE OVERVIEW
This document contains device-specific information for
the following devices:
All of the devices in the PIC18F2450/4450 family offer
twelve different oscillator options, allowing users a wide
range of choices in developing application hardware.
These include:
• PIC18F2450
• PIC18F4450
This family of devices offers the advantages of all
PIC18 microcontrollers – namely, high computational
performance at an economical price – with the addi-
tion of high-endurance, Enhanced Flash program
memory. In addition to these features, the
PIC18F2450/4450 family introduces design enhance-
ments that make these microcontrollers a logical
choice for many high-performance, power sensitive
applications.
• Four Crystal modes using crystals or ceramic
resonators.
• Four External Clock modes, offering the option of
using two pins (oscillator input and a divide-by-4
clock output) or one pin (oscillator input, with the
second pin reassigned as general I/O).
• An INTRC source (approximately 31 kHz, stable
over temperature and VDD). This option frees an
oscillator pin for use as an additional general
purpose I/O.
1.1
New Core Features
• A Phase Lock Loop (PLL) frequency multiplier,
available to both the High-Speed Crystal and
External Oscillator modes, which allows a wide
range of clock speeds from 4 MHz to 48 MHz.
1.1.1
nanoWatt TECHNOLOGY
All of the devices in the PIC18F2450/4450 family
incorporate a range of features that can significantly
reduce power consumption during operation. Key
items include:
• Asynchronous dual clock operation, allowing the
USB module to run from a high-frequency
oscillator while the rest of the microcontroller is
clocked from an internal low-power oscillator.
• Alternate Run Modes: By clocking the controller
from the Timer1 source or the internal RC
oscillator, power consumption during code
execution can be reduced by as much as 90%.
The internal oscillator provides a stable reference
source that gives the family additional features for
robust operation:
• Multiple Idle Modes: The controller can also run
with its CPU core disabled but the peripherals still
active. In these states, power consumption can be
reduced even further, to as little as 4% of normal
operation requirements.
• Fail-Safe Clock Monitor: This option constantly
monitors the main clock source against a
reference signal provided by the internal
oscillator. If a clock failure occurs, the controller is
switched to the internal oscillator, allowing for
continued low-speed operation or a safe
application shutdown.
• On-the-Fly Mode Switching: The power-
managed modes are invoked by user code during
operation, allowing the user to incorporate
power-saving ideas into their application’s
software design.
• Two-Speed Start-up: This option allows the
internal oscillator to serve as the clock source
from Power-on Reset, or wake-up from Sleep
mode, until the primary clock source is available.
• Low Consumption in Key Modules: The
power requirements for both Timer1 and the
Watchdog Timer are minimized. See
Section 21.0 “Electrical Characteristics” for
values.
1.1.2
UNIVERSAL SERIAL BUS (USB)
Devices in the PIC18F2450/4450 family incorporate a
fully featured Universal Serial Bus communications
module that is compliant with the USB Specification
Revision 2.0. The module supports both low-speed and
full-speed communication for all supported data
transfer types. It also incorporates its own on-chip
transceiver and 3.3V regulator and supports the use of
external transceivers and voltage regulators.
© 2008 Microchip Technology Inc.
DS39760D-page 7
PIC18F2450/4450
1.2
Other Special Features
1.3
Details on Individual Family
Members
• Memory Endurance: The Enhanced Flash cells
for program memory are rated to last for many
thousands of erase/write cycles – up to 100,000.
Devices in the PIC18F2450/4450 family are available
in 28-pin and 40/44-pin packages. Block diagrams for
the two groups are shown in Figure 1-1 and Figure 1-2.
• Self-Programmability: These devices can write
to their own program memory spaces under
internal software control. By using a bootloader
routine, located in the protected Boot Block at the
top of program memory, it becomes possible to
create an application that can update itself in the
field.
The devices are differentiated from each other in the
following two ways:
1. A/D channels (10 for 28-pin devices, 13 for
40/44-pin devices).
2. I/O ports (3 bidirectional ports and 1 input only
port on 28-pin devices, 5 bidirectional ports on
40/44-pin devices).
• Extended Instruction Set: The PIC18F2450/
4450 family introduces an optional extension to
the PIC18 instruction set, which adds 8 new
instructions and an Indexed Literal Offset
Addressing mode. This extension, enabled as a
device configuration option, has been specifically
designed to optimize re-entrant application code
originally developed in high-level languages such
as C.
All other features for devices in this family are identical.
These are summarized in Table 1-1.
The pinouts for all devices are listed in Table 1-2 and
Table 1-3.
Like all Microchip PIC18 devices, members of the
PIC18F2450/4450 family are available as both standard
and low-voltage devices. Standard devices with
Enhanced Flash memory, designated with an “F” in the
part number (such as PIC18F2450), accommodate an
operating VDD range of 4.2V to 5.5V. Low-voltage parts,
designated by “LF” (such as PIC18LF2450), function
over an extended VDD range of 2.0V to 5.5V.
• Enhanced Addressable USART: This serial
communication module is capable of standard
RS-232 operation and provides support for the LIN
bus protocol. Other enhancements include
Automatic Baud Rate Detection and a 16-bit Baud
Rate Generator for improved resolution.
• 10-Bit A/D Converter: This module incorporates
programmable acquisition time, allowing for a
channel to be selected and a conversion to be
initiated, without waiting for a sampling period and
thus, reducing code overhead.
• Dedicated ICD/ICSP Port: These devices
introduce the use of debugger and programming
pins that are not multiplexed with other micro-
controller features. Offered as an option in select
packages, this feature allows users to develop I/O
intensive applications while retaining the ability to
program and debug in the circuit.
DS39760D-page 8
© 2008 Microchip Technology Inc.
PIC18F2450/4450
TABLE 1-1:
DEVICE FEATURES
Features
PIC18F2450
PIC18F4450
Operating Frequency
Program Memory (Bytes)
Program Memory (Instructions)
Data Memory (Bytes)
Interrupt Sources
DC – 48 MHz
DC – 48 MHz
16384
16384
8192
8192
768
768
13
13
I/O Ports
Ports A, B, C, (E)
Ports A, B, C, D, E
Timers
3
3
Capture/Compare/PWM Modules
Enhanced USART
1
1
1
1
Universal Serial Bus (USB) Module
10-Bit Analog-to-Digital Module
Resets (and Delays)
1
1
10 Input Channels
13 Input Channels
POR, BOR,
RESETInstruction,
Stack Full,
POR, BOR,
RESETInstruction,
Stack Full,
Stack Underflow (PWRT, OST),
MCLR (optional),
WDT
Stack Underflow (PWRT, OST),
MCLR (optional),
WDT
Programmable Low-Voltage Detect
Programmable Brown-out Reset
Instruction Set
Yes
Yes
Yes
Yes
75 Instructions;
75 Instructions;
83 with Extended Instruction Set 83 with Extended Instruction Set
enabled
enabled
Packages
28-Pin SPDIP
28-Pin SOIC
28-Pin QFN
40-Pin PDIP
44-Pin QFN
44-Pin TQFP
© 2008 Microchip Technology Inc.
DS39760D-page 9
PIC18F2450/4450
FIGURE 1-1:
PIC18F2450 (28-PIN) BLOCK DIAGRAM
Data Bus<8>
Table Pointer<21>
PORTA
RA0/AN0
RA1/AN1
Data Latch
8
8
inc/dec logic
21
RA2/AN2/VREF-
RA3/AN3/VREF+
RA4/T0CKI/RCV
RA5/AN4/HLVDIN
OSC2/CLKO/RA6
Data Memory
(2 Kbytes)
PCLATU PCLATH
Address Latch
20
PCU PCH PCL
Program Counter
12
Data Address<12>
31 Level Stack
STKPTR
4
BSR
12
FSR0
FSR1
FSR2
4
Address Latch
Access
Bank
Program Memory
(24/32 Kbytes)
12
Data Latch
PORTB
RB0/AN12/INT0
RB1/AN10/INT1
RB2/AN8/INT2/VMO
RB3/AN9/VPO
RB4/AN11/KBI0
RB5/KBI1/PGM
RB6/KBI2/PGC
RB7/KBI3/PGD
inc/dec
logic
8
Table Latch
Address
Decode
ROM Latch
IR
Instruction Bus <16>
8
Instruction
Decode &
Control
State Machine
Control Signals
PRODH PRODL
8 x 8 Multiply
PORTC
RC0/T1OSO/T1CKI
RC1/T1OSI/UOE
RC2/CCP1
RC4/D-/VM
RC5/D+/VP
3
8
OSC1(2)
OSC2(2)
T1OSI
Power-up
Timer
Internal
Oscillator
Block
BITOP
8
W
8
8
Oscillator
Start-up Timer
RC6/TX/CK
RC7/RX/DT
INTRC
Oscillator
8
8
Power-on
Reset
ALU<8>
8
Watchdog
Timer
T1OSO
Brown-out
Reset
MCLR(1)
VDD, VSS
Single-Supply
Programming
In-Circuit
Fail-Safe
Clock Monitor
Debugger
PORTE
Band Gap
Reference
USB Voltage
Regulator
VUSB
MCLR/VPP/RE3(1)
BOR
HLVD
ADC
10-Bit
Timer0
Timer1
Timer2
EUSART
CCP1
USB
Note 1: RE3 is multiplexed with MCLR and is only available when the MCLR Resets are disabled.
2: OSC1/CLKI and OSC2/CLKO are only available in select oscillator modes and when these pins are not being used as digital I/O. Refer
to Section 2.0 “Oscillator Configurations” for additional information.
DS39760D-page 10
© 2008 Microchip Technology Inc.
PIC18F2450/4450
FIGURE 1-2:
PIC18F4450 (40/44-PIN) BLOCK DIAGRAM
Data Bus<8>
PORTA
Table Pointer<21>
RA0/AN0
RA1/AN1
Data Latch
8
8
inc/dec logic
RA2/AN2/VREF-
RA3/AN3/VREF+
RA4/T0CKI/RCV
RA5/AN4/HLVDIN
OSC2/CLKO/RA6
Data Memory
(2 Kbytes)
PCLATU PCLATH
21
Address Latch
20
PCU PCH PCL
Program Counter
12
Data Address<12>
PORTB
PORTC
PORTD
31 Level Stack
STKPTR
RB0/AN12/INT0
RB1/AN10/INT1
RB2/AN8/INT2/VMO
RB3/AN9/VPO
RB4/AN11/KBI0
RB5/KBI1/PGM
RB6/KBI2/PGC
RB7/KBI3/PGD
4
BSR
12
4
Address Latch
Access
Bank
FSR0
FSR1
FSR2
Program Memory
(24/32 Kbytes)
12
Data Latch
inc/dec
logic
8
Table Latch
Address
Decode
ROM Latch
IR
Instruction Bus <16>
RC0/T1OSO/T1CKI
RC1/T1OSI/UOE
RC2/CCP1
RC4/D-/VM
RC5/D+/VP
RC6/TX/CK
RC7/RX/DT
8
Instruction
Decode &
Control
State Machine
Control Signals
PRODH PRODL
8 x 8 Multiply
RD0
RD1
RD2
RD3
RD4
RD5
RD6
RD7
3
VDD, VSS
8
Internal
Oscillator
Block
Power-up
Timer
OSC1(2)
OSC2(2)
T1OSI
BITOP
8
W
8
8
Oscillator
Start-up Timer
INTRC
Oscillator
8
8
Power-on
Reset
T1OSO
ALU<8>
8
Watchdog
Timer
ICPGC(3)
ICPGD(3)
ICPORTS(3)
ICRST(3)
MCLR(1)
Single-Supply
Programming
Brown-out
Reset
PORTE
In-Circuit
Debugger
RE0/AN5
RE1/AN6
Fail-Safe
Clock Monitor
Band Gap
Reference
RE2/AN7
MCLR/VPP/RE3(1)
USB Voltage
Regulator
VUSB
BOR
HLVD
Timer0
Timer1
Timer2
ADC
10-Bit
EUSART
CCP1
USB
Note 1: RE3 is multiplexed with MCLR and is only available when the MCLR Resets are disabled.
2: OSC1/CLKI and OSC2/CLKO are only available in select oscillator modes and when these pins are not being used as digital I/O. Refer
to Section 2.0 “Oscillator Configurations” for additional information.
3: These pins are only available on 44-pin TQFP under certain conditions. Refer to Section 18.9 “Special ICPORT Features (Designated
Packages Only)” for additional information.
© 2008 Microchip Technology Inc.
DS39760D-page 11
PIC18F2450/4450
TABLE 1-2:
PIC18F2450 PINOUT I/O DESCRIPTIONS
Pin Number
Pin Buffer
Type Type
Pin Name
Description
SPDIP,
QFN
SOIC
MCLR/VPP/RE3
MCLR
1
26
Master Clear (input) or programming voltage (input).
Master Clear (Reset) input. This pin is an active-low
Reset to the device.
I
ST
ST
VPP
RE3
P
I
Programming voltage input.
Digital input.
OSC1/CLKI
OSC1
9
6
7
Oscillator crystal or external clock input.
I
I
Analog
Analog
Oscillator crystal input or external clock source input.
External clock source input. Always associated with pin
function OSC1. (See OSC2/CLKO pin.)
CLKI
OSC2/CLKO/RA6
OSC2
10
Oscillator crystal or clock output.
O
O
—
—
Oscillator crystal output. Connects to crystal or resonator
in Crystal Oscillator mode.
In select modes, OSC2 pin outputs CLKO which has
1/4 the frequency of OSC1 and denotes the instruction
cycle rate.
CLKO
RA6
I/O
TTL
General purpose I/O pin.
Legend: TTL = TTL compatible input
ST = Schmitt Trigger input with CMOS levels
= Output
CMOS = CMOS compatible input or output
I
= Input
O
P
= Power
DS39760D-page 12
© 2008 Microchip Technology Inc.
PIC18F2450/4450
TABLE 1-2:
PIC18F2450 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number
Pin Buffer
Type Type
Pin Name
Description
PORTA is a bidirectional I/O port.
SPDIP,
QFN
SOIC
RA0/AN0
RA0
2
3
4
27
28
1
I/O
I
TTL
Analog
Digital I/O.
Analog input 0.
AN0
RA1/AN1
RA1
I/O
I
TTL
Analog
Digital I/O.
Analog input 1.
AN1
RA2/AN2/VREF-
RA2
I/O
TTL
Digital I/O.
AN2
VREF-
I
I
Analog
Analog
Analog input 2.
A/D reference voltage (low) input.
RA3/AN3/VREF+
RA3
5
6
2
3
I/O
I
I
TTL
Analog
Analog
Digital I/O.
Analog input 3.
A/D reference voltage (high) input.
AN3
VREF+
RA4/T0CKI/RCV
RA4
I/O
I
I
ST
ST
TTL
Digital I/O.
Timer0 external clock input.
External USB transceiver RCV input.
T0CKI
RCV
RA5/AN4/HLVDIN
RA5
7
4
I/O
TTL
Digital I/O.
AN4
HLVDIN
I
I
Analog
Analog
Analog input 4.
High/Low-Voltage Detect input.
RA6
—
—
—
—
See the OSC2/CLKO/RA6 pin.
Legend: TTL = TTL compatible input
ST = Schmitt Trigger input with CMOS levels
= Output
CMOS = CMOS compatible input or output
I
= Input
O
P
= Power
© 2008 Microchip Technology Inc.
DS39760D-page 13
PIC18F2450/4450
TABLE 1-2:
PIC18F2450 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number
Pin Buffer
Type Type
Pin Name
Description
SPDIP,
QFN
SOIC
PORTB is a bidirectional I/O port. PORTB can be software
programmed for internal weak pull-ups on all inputs.
RB0/AN12/INT0
RB0
21
22
23
18
19
20
I/O
I
I
TTL
Analog
ST
Digital I/O.
Analog input 12.
External interrupt 0.
AN12
INT0
RB1/AN10/INT1
RB1
I/O
I
I
TTL
Analog
ST
Digital I/O.
Analog input 10.
External interrupt 1.
AN10
INT1
RB2/AN8/INT2/VMO
RB2
AN8
INT2
VMO
I/O
I
I
TTL
Analog
ST
Digital I/O.
Analog input 8.
External interrupt 2.
External USB transceiver VMO output.
O
—
RB3/AN9/VPO
RB3
24
25
26
27
28
21
22
23
24
25
I/O
I
O
TTL
Analog
—
Digital I/O.
Analog input 9.
External USB transceiver VPO output.
AN9
VPO
RB4/AN11/KBI0
RB4
I/O
I
I
TTL
Analog
TTL
Digital I/O.
Analog input 11.
Interrupt-on-change pin.
AN11
KBI0
RB5/KBI1/PGM
RB5
I/O
I
I/O
TTL
TTL
ST
Digital I/O.
Interrupt-on-change pin.
Low-Voltage ICSP™ Programming enable pin.
KBI1
PGM
RB6/KBI2/PGC
RB6
I/O
I
I/O
TTL
TTL
ST
Digital I/O.
Interrupt-on-change pin.
In-Circuit Debugger and ICSP programming clock pin.
KBI2
PGC
RB7/KBI3/PGD
RB7
I/O
I
I/O
TTL
TTL
ST
Digital I/O.
Interrupt-on-change pin.
In-Circuit Debugger and ICSP programming data pin.
KBI3
PGD
Legend: TTL = TTL compatible input
ST = Schmitt Trigger input with CMOS levels
= Output
CMOS = CMOS compatible input or output
I
= Input
O
P
= Power
DS39760D-page 14
© 2008 Microchip Technology Inc.
PIC18F2450/4450
TABLE 1-2:
PIC18F2450 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number
Pin Buffer
Type Type
Pin Name
Description
SPDIP,
QFN
SOIC
PORTC is a bidirectional I/O port.
RC0/T1OSO/T1CKI
RC0
11
12
8
9
I/O
O
I
ST
—
ST
Digital I/O.
Timer1 oscillator output.
Timer1external clock input.
T1OSO
T1CKI
RC1/T1OSI/UOE
RC1
I/O
I
O
ST
CMOS
—
Digital I/O.
Timer1 oscillator input.
External USB transceiver OE output.
T1OSI
UOE
RC2/CCP1
RC2
13
15
10
12
I/O
I/O
ST
ST
Digital I/O.
CCP1
Capture 1 input/Compare 1 output/PWM1 output.
RC4/D-/VM
RC4
D-
VM
I
I/O
I
TTL
—
TTL
Digital input.
USB differential minus line (input/output).
External USB transceiver VM input.
RC5/D+/VP
16
17
18
13
14
15
RC5
D+
VP
I
TTL
—
TTL
Digital input.
USB differential plus line (input/output).
External USB transceiver VP input.
I/O
O
RC6/TX/CK
RC6
TX
CK
I/O
O
I/O
ST
—
ST
Digital I/O.
EUSART asynchronous transmit.
EUSART synchronous clock (see RX/DT).
RC7/RX/DT
RC7
I/O
I
I/O
ST
ST
ST
Digital I/O.
EUSART asynchronous receive.
EUSART synchronous data (see TX/CK).
RX
DT
RE3
—
—
11
—
P
—
—
See MCLR/VPP/RE3 pin.
VUSB
14
Internal USB 3.3V voltage regulator. Output, positive supply
for internal USB transceiver.
VSS
VDD
8, 19 5, 16
20 17
P
P
—
—
Ground reference for logic and I/O pins.
Positive supply for logic and I/O pins.
CMOS = CMOS compatible input or output
Legend: TTL = TTL compatible input
ST = Schmitt Trigger input with CMOS levels
= Output
I
= Input
O
P
= Power
© 2008 Microchip Technology Inc.
DS39760D-page 15
PIC18F2450/4450
TABLE 1-3:
Pin Name
PIC18F4450 PINOUT I/O DESCRIPTIONS
Pin Number
Pin Buffer
Type Type
Description
PDIP QFN TQFP
MCLR/VPP/RE3
MCLR
1
18
18
Master Clear (input) or programming voltage (input).
Master Clear (Reset) input. This pin is an
active-low Reset to the device.
Programming voltage input.
I
ST
VPP
RE3
P
I
—
ST
Digital input.
OSC1/CLKI
OSC1
13
14
32
33
30
31
Oscillator crystal or external clock input.
I
I
Analog
Analog
Oscillator crystal input or external clock source input.
External clock source input. Always associated with
pin function OSC1. (See OSC2/CLKO pin.)
CLKI
OSC2/CLKO/RA6
OSC2
Oscillator crystal or clock output.
O
O
—
—
Oscillator crystal output. Connects to crystal or
resonator in Crystal Oscillator mode.
In select modes, OSC2 pin outputs CLKO which has
1/4 the frequency of OSC1 and denotes the instruction
cycle rate.
CLKO
RA6
I/O
TTL
General purpose I/O pin.
Legend: TTL = TTL compatible input
ST = Schmitt Trigger input with CMOS levels
= Output
CMOS = CMOS compatible input or output
I
= Input
O
P
= Power
Note 1: These pins are No Connect unless the ICPRT Configuration bit is set. For NC/ICPORTS, the pin is No
Connect unless ICPRT is set and the DEBUG Configuration bit is cleared.
DS39760D-page 16
© 2008 Microchip Technology Inc.
PIC18F2450/4450
TABLE 1-3:
Pin Name
PIC18F4450 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number
Pin Buffer
Type Type
Description
PDIP QFN TQFP
PORTA is a bidirectional I/O port.
RA0/AN0
RA0
2
3
4
19
20
21
19
20
21
I/O
I
TTL
Analog
Digital I/O.
Analog input 0.
AN0
RA1/AN1
RA1
I/O
I
TTL
Analog
Digital I/O.
Analog input 1.
AN1
RA2/AN2/VREF-
RA2
I/O
TTL
Digital I/O.
AN2
VREF-
I
I
Analog
Analog
Analog input 2.
A/D reference voltage (low) input.
RA3/AN3/VREF+
RA3
5
6
22
23
24
—
22
23
24
—
I/O
I
I
TTL
Analog
Analog
Digital I/O.
Analog input 3.
A/D reference voltage (high) input.
AN3
VREF+
RA4/T0CKI/RCV
RA4
I/O
I
I
ST
ST
TTL
Digital I/O.
Timer0 external clock input.
External USB transceiver RCV input.
T0CKI
RCV
RA5/AN4/HLVDIN
RA5
7
I/O
I
I
TTL
Analog
Analog
Digital I/O.
Analog input 4.
High/Low-Voltage Detect input.
AN4
HLVDIN
RA6
—
—
—
See the OSC2/CLKO/RA6 pin.
Legend: TTL = TTL compatible input
ST = Schmitt Trigger input with CMOS levels
= Output
CMOS = CMOS compatible input or output
I
= Input
O
P
= Power
Note 1: These pins are No Connect unless the ICPRT Configuration bit is set. For NC/ICPORTS, the pin is No
Connect unless ICPRT is set and the DEBUG Configuration bit is cleared.
© 2008 Microchip Technology Inc.
DS39760D-page 17
PIC18F2450/4450
TABLE 1-3:
Pin Name
PIC18F4450 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number
Pin Buffer
Type Type
Description
PDIP QFN TQFP
PORTB is a bidirectional I/O port. PORTB can be
software programmed for internal weak pull-ups on all
inputs.
RB0/AN12/INT0
RB0
33
34
35
9
8
9
I/O
I
I
TTL
Analog
ST
Digital I/O.
Analog input 12.
External interrupt 0.
AN12
INT0
RB1/AN10/INT1
RB1
10
11
I/O
I
I
TTL
Analog
ST
Digital I/O.
Analog input 10.
External interrupt 1.
AN10
INT1
RB2/AN8/INT2/VMO
10
RB2
AN8
INT2
VMO
I/O
I
I
TTL
Analog
ST
Digital I/O.
Analog input 8.
External interrupt 2.
External USB transceiver VMO output.
O
—
RB3/AN9/VPO
RB3
36
37
38
39
40
12
14
15
16
17
11
14
15
16
17
I/O
I
O
TTL
Analog
—
Digital I/O.
Analog input 9.
External USB transceiver VPO output.
AN9
VPO
RB4/AN11/KBI0
RB4
I/O
I
I
TTL
Analog
TTL
Digital I/O.
Analog input 11.
Interrupt-on-change pin.
AN11
KBI0
RB5/KBI1/PGM
RB5
I/O
I
I/O
TTL
TTL
ST
Digital I/O.
Interrupt-on-change pin.
Low-Voltage ICSP™ Programming enable pin.
KBI1
PGM
RB6/KBI2/PGC
RB6
I/O
I
I/O
TTL
TTL
ST
Digital I/O.
Interrupt-on-change pin.
In-Circuit Debugger and ICSP programming clock pin.
KBI2
PGC
RB7/KBI3/PGD
RB7
I/O
I
I/O
TTL
TTL
ST
Digital I/O.
Interrupt-on-change pin.
In-Circuit Debugger and ICSP programming data pin.
KBI3
PGD
Legend: TTL = TTL compatible input
ST = Schmitt Trigger input with CMOS levels
= Output
CMOS = CMOS compatible input or output
I
= Input
O
P
= Power
Note 1: These pins are No Connect unless the ICPRT Configuration bit is set. For NC/ICPORTS, the pin is No
Connect unless ICPRT is set and the DEBUG Configuration bit is cleared.
DS39760D-page 18
© 2008 Microchip Technology Inc.
PIC18F2450/4450
TABLE 1-3:
Pin Name
PIC18F4450 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number
Pin Buffer
Type Type
Description
PDIP QFN TQFP
PORTC is a bidirectional I/O port.
RC0/T1OSO/T1CKI
RC0
15
16
34
35
32
35
I/O
O
I
ST
—
ST
Digital I/O.
Timer1 oscillator output.
Timer1 external clock input.
T1OSO
T1CKI
RC1/T1OSI/UOE
RC1
I/O
I
O
ST
CMOS
—
Digital I/O.
Timer1 oscillator input.
External USB transceiver OE output.
T1OSI
UOE
RC2/CCP1
RC2
17
23
36
42
36
42
I/O
I/O
ST
ST
Digital I/O.
CCP1
Capture 1 input/Compare 1 output/PWM1 output.
RC4/D-/VM
RC4
D-
VM
I
I/O
I
TTL
—
TTL
Digital input.
USB differential minus line (input/output).
External USB transceiver VM input.
RC5/D+/VP
24
25
26
43
44
1
43
44
1
RC5
D+
VP
I
I/O
I
TTL
—
TTL
Digital input.
USB differential plus line (input/output).
External USB transceiver VP input.
RC6/TX/CK
RC6
I/O
O
I/O
ST
—
ST
Digital I/O.
TX
CK
EUSART asynchronous transmit.
EUSART synchronous clock (see RX/DT).
RC7/RX/DT
RC7
I/O
I
I/O
ST
ST
ST
Digital I/O.
EUSART asynchronous receive.
EUSART synchronous data (see TX/CK).
RX
DT
Legend: TTL = TTL compatible input
ST = Schmitt Trigger input with CMOS levels
= Output
CMOS = CMOS compatible input or output
I
= Input
O
P
= Power
Note 1: These pins are No Connect unless the ICPRT Configuration bit is set. For NC/ICPORTS, the pin is No
Connect unless ICPRT is set and the DEBUG Configuration bit is cleared.
© 2008 Microchip Technology Inc.
DS39760D-page 19
PIC18F2450/4450
TABLE 1-3:
Pin Name
PIC18F4450 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number
Pin Buffer
Type Type
Description
PDIP QFN TQFP
PORTD is a bidirectional I/O port.
RD0
RD1
RD2
RD3
RD4
RD5
RD6
RD7
19
20
21
22
27
28
29
30
38
39
40
41
2
38
39
40
41
2
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
ST
ST
ST
ST
ST
ST
ST
ST
Digital I/O.
Digital I/O.
Digital I/O.
Digital I/O.
Digital I/O.
Digital I/O.
Digital I/O.
3
3
4
4
5
5
Digital I/O.
Legend: TTL = TTL compatible input
ST = Schmitt Trigger input with CMOS levels
= Output
CMOS = CMOS compatible input or output
I
= Input
O
P
= Power
Note 1: These pins are No Connect unless the ICPRT Configuration bit is set. For NC/ICPORTS, the pin is No
Connect unless ICPRT is set and the DEBUG Configuration bit is cleared.
DS39760D-page 20
© 2008 Microchip Technology Inc.
PIC18F2450/4450
TABLE 1-3:
Pin Name
PIC18F4450 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number
Pin Buffer
Type Type
Description
PDIP QFN TQFP
PORTE is a bidirectional I/O port.
RE0/AN5
RE0
8
9
25
26
27
—
25
26
27
—
I/O
I
ST
Analog
Digital I/O.
Analog input 5.
AN5
RE1/AN6
RE1
I/O
I
ST
Analog
Digital I/O.
Analog input 6.
AN6
RE2/AN7
RE2
10
I/O
I
ST
Analog
Digital I/O.
Analog input 7.
AN7
RE3
VSS
—
—
P
—
—
See MCLR/VPP/RE3 pin.
12, 31 6, 30, 6, 29
31
Ground reference for logic and I/O pins.
VDD
11, 32 7, 8, 7, 28
28, 29
P
P
—
—
Positive supply for logic and I/O pins.
VUSB
18
37
37
Internal USB 3.3V voltage regulator output. Positive
supply for internal USB transceiver.
NC/ICCK/ICPGC(1)
ICCK
—
—
12
No Connect or dedicated ICD/ICSP™ port clock.
In-Circuit Debugger clock.
I/O
I/O
ST
ST
ICPGC
ICSP programming clock.
NC/ICDT/ICPGD(1)
—
—
—
—
—
—
—
13
13
33
34
—
No Connect or dedicated ICD/ICSP port clock.
In-Circuit Debugger data.
ICDT
ICPGD
I/O
I/O
ST
ST
ICSP programming data.
(1)
NC/ICRST/ICVPP
No Connect or dedicated ICD/ICSP port Reset.
Master Clear (Reset) input.
ICRST
ICVPP
NC/ICPORTS(1)
ICPORTS
I
P
—
—
Programming voltage input.
P
—
No Connect or 28-pin device emulation.
Enable 28-pin device emulation when connected
to VSS.
NC
—
—
No Connect.
Legend: TTL = TTL compatible input
ST = Schmitt Trigger input with CMOS levels
= Output
CMOS = CMOS compatible input or output
I
= Input
O
P
= Power
Note 1: These pins are No Connect unless the ICPRT Configuration bit is set. For NC/ICPORTS, the pin is No
Connect unless ICPRT is set and the DEBUG Configuration bit is cleared.
© 2008 Microchip Technology Inc.
DS39760D-page 21
PIC18F2450/4450
NOTES:
DS39760D-page 22
© 2008 Microchip Technology Inc.
PIC18F2450/4450
2.2
Oscillator Types
2.0
2.1
OSCILLATOR
CONFIGURATIONS
PIC18F2450/4450 devices can be operated in twelve
distinct oscillator modes. In contrast with the non-USB
PIC18 enhanced microcontrollers, four of these modes
involve the use of two oscillator types at once. Users
can program the FOSC3:FOSC0 Configuration bits to
select one of these modes:
Overview
Devices in the PIC18F2450/4450 family incorporate a
different oscillator and microcontroller clock system
than the non-USB PIC18F devices. The addition of the
USB module, with its unique requirements for a stable
clock source, make it necessary to provide a separate
clock source that is compliant with both USB low-speed
and full-speed specifications.
1. XT
2. XTPLL Crystal/Resonator with PLL Enabled
3. HS High-Speed Crystal/Resonator
Crystal/Resonator
4. HSPLL High-Speed Crystal/Resonator
with PLL Enabled
To accommodate these requirements, PIC18F2450/
4450 devices include a new clock branch to provide a
48 MHz clock for full-speed USB operation. Since it is
driven from the primary clock source, an additional
system of prescalers and postscalers has been added
to accommodate a wide range of oscillator frequencies.
An overview of the oscillator structure is shown in
Figure 2-1.
5. EC
External Clock with FOSC/4 Output
External Clock with I/O on RA6
6. ECIO
7. ECPLL External Clock with PLL Enabled
and FOSC/4 Output on RA6
8. ECPIO External Clock with PLL Enabled,
I/O on RA6
9. INTHS Internal Oscillator used as
Microcontroller Clock Source, HS
Other oscillator features used in PIC18 enhanced
microcontrollers, such as the internal RC oscillator and
clock switching, remain the same. They are discussed
later in this chapter.
Oscillator used as USB Clock Source
10. INTXT Internal Oscillator used as
Microcontroller Clock Source, XT
Oscillator used as USB Clock Source
2.1.1
OSCILLATOR CONTROL
11. INTIO
Internal Oscillator used as
The operation of the oscillator in PIC18F2450/4450
devices is controlled through two Configuration registers
and two control registers. Configuration registers,
CONFIG1L and CONFIG1H, select the oscillator mode
and USB prescaler/postscaler options. As Configuration
bits, these are set when the device is programmed and
left in that configuration until the device is
reprogrammed.
Microcontroller Clock Source, EC
Oscillator used as USB Clock Source,
Digital I/O on RA6
12. INTCKO Internal Oscillator used as
Microcontroller Clock Source, EC
Oscillator used as USB Clock Source,
FOSC/4 Output on RA6
The OSCCON register (Register 2-1) selects the Active
Clock mode; it is primarily used in controlling clock
switching in power-managed modes. Its use is
discussed in Section 2.4.1 “Oscillator Control
Register”.
© 2008 Microchip Technology Inc.
DS39760D-page 23
PIC18F2450/4450
Because of the timing requirements imposed by USB,
an internal clock of either 6 MHz or 48 MHz is required
while the USB module is enabled. Fortunately, the
microcontroller and other peripherals are not required
to run at this clock speed when using the primary
oscillator. There are numerous options to achieve the
USB module clock requirement and still provide flexi-
bility for clocking the rest of the device from the primary
oscillator source. These are detailed in Section 2.3
“Oscillator Settings for USB”.
2.2.1
OSCILLATOR MODES AND
USB OPERATION
Because of the unique requirements of the USB
module, a different approach to clock operation is
necessary. In previous PIC® microcontrollers, all core
and peripheral clocks were driven by a single oscillator
source; the usual sources were primary, secondary or
the internal oscillator. With PIC18F2450/4450 devices,
the primary oscillator becomes part of the USB module
and cannot be associated to any other clock source.
Thus, the USB module must be clocked from the
primary clock source; however, the microcontroller
core and other peripherals can be separately clocked
from the secondary or internal oscillators as before.
FIGURE 2-1:
PIC18F2450/4450 CLOCK DIAGRAM
PIC18F2450/4450
PLLDIV<2:0>
USB Clock Source
÷ 12
÷ 10
111
110
USBDIV
÷ 6
÷ 5
÷ 4
÷ 3
101
(4 MHz Input Only)
0
1
Primary Oscillator
100
011
010
96 MHz
PLL
÷ 2
OSC2
OSC1
Sleep
÷ 2
÷ 1
FSEN
001
000
1
HSPLL, ECPLL,
XTPLL, ECPIO
USB
Peripheral
CPUDIV<1:0>
0
÷ 4
÷ 6
11
10
÷ 4
÷ 3
÷ 2
CPUDIV<1:0>
01
00
÷ 4
11
÷ 3
10
CPU
XT, HS, EC, ECIO
1
÷ 2
01
0
Primary
Clock
÷ 1
00
IDLEN
Peripherals
FOSC3:FOSC0
Secondary Oscillator
T1OSO
T1OSI
T1OSC
T1OSCEN
Enable
Oscillator
OSCCON<6:4>
Internal Oscillator
Clock
Control
Internal RC Oscillator
31.25 kHz
FOSC3:FOSC0
OSCCON<1:0>
Clock Source Option
for Other Modules
WDT, PWRT, FSCM
and Two-Speed Start-up
DS39760D-page 24
© 2008 Microchip Technology Inc.
PIC18F2450/4450
2.2.2
CRYSTAL OSCILLATOR/CERAMIC
RESONATORS
TABLE 2-2:
CAPACITOR SELECTION FOR
CRYSTAL OSCILLATOR
In HS, HSPLL, XT and XTPLL Oscillator modes, a
crystal or ceramic resonator is connected to the OSC1
and OSC2 pins to establish oscillation. Figure 2-2
shows the pin connections.
Typical Capacitor Values
Crystal
Freq
Tested:
Osc Type
C1
C2
XT
HS
4 MHz
4 MHz
8 MHz
20 MHz
27 pF
27 pF
22 pF
15 pF
27 pF
27 pF
22 pF
15 pF
The oscillator design requires the use of a parallel cut
crystal.
Note:
Use of a series cut crystal may give a fre-
quency out of the crystal manufacturer’s
specifications.
Capacitor values are for design guidance only.
These capacitors were tested with the crystals listed
below for basic start-up and operation. These values
are not optimized.
FIGURE 2-2:
CRYSTAL/CERAMIC
RESONATOROPERATION
(XT, HS OR HSPLL
Different capacitor values may be required to produce
acceptable oscillator operation. The user should test
the performance of the oscillator over the expected
VDD and temperature range for the application.
CONFIGURATION)
(1)
C1
OSC1
To
Internal
Logic
See the notes following this table for additional
information.
(3)
RF
XTAL
Crystals Used:
Sleep
(2)
RS
(1)
4 MHz
8 MHz
20 MHz
PIC18FXXXX
C2
OSC2
Note 1: See Table 2-1 and Table 2-2 for initial values of
C1 and C2.
2: A series resistor (RS) may be required for AT
strip cut crystals.
Note 1: Higher capacitance increases the stability
of oscillator but also increases the start-up
time.
3: RF varies with the oscillator mode chosen.
2: When operating below 3V VDD, or when
using certain ceramic resonators at any
voltage, it may be necessary to use the
HS mode or switch to a crystal oscillator.
TABLE 2-1:
CAPACITOR SELECTION FOR
CERAMIC RESONATORS
Typical Capacitor Values Used:
3: Since each resonator/crystal has its own
characteristics, the user should consult
the resonator/crystal manufacturer for
Mode
Freq
OSC1
OSC2
XT
HS
4.0 MHz
33 pF
33 pF
8.0 MHz
16.0 MHz
27 pF
22 pF
27 pF
22 pF
appropriate
values
of
external
components.
Capacitor values are for design guidance only.
4: Rs may be required to avoid overdriving
crystals with low drive level specification.
These capacitors were tested with the resonators
listed below for basic start-up and operation. These
values are not optimized.
5: Always verify oscillator performance over
the VDD and temperature range that is
expected for the application.
Different capacitor values may be required to produce
acceptable oscillator operation. The user should test
the performance of the oscillator over the expected
VDD and temperature range for the application.
An internal postscaler allows users to select a clock
frequency other than that of the crystal or resonator.
Frequency division is determined by the CPUDIV
Configuration bits. Users may select a clock frequency
of the oscillator frequency, or 1/2, 1/3 or 1/4 of the
frequency.
See the notes following Table 2-2 for additional
information.
Resonators Used:
An external clock may also be used when the micro-
controller is in HS Oscillator mode. In this case, the
OSC2/CLKO pin is left open (Figure 2-3).
4.0 MHz
8.0 MHz
16.0 MHz
© 2008 Microchip Technology Inc.
DS39760D-page 25
PIC18F2450/4450
FIGURE 2-3:
EXTERNAL CLOCK INPUT
2.2.4
PLL FREQUENCY MULTIPLIER
OPERATION (HS OSC
CONFIGURATION)
PIC18F2450/4450 devices include a Phase Locked
Loop (PLL) circuit. This is provided specifically for USB
applications with lower speed oscillators and can also
be used as a microcontroller clock source.
OSC1
Clock from
Ext. System
The PLL is enabled in HSPLL, XTPLL, ECPLL and
ECPIO Oscillator modes. It is designed to produce a
fixed 96 MHz reference clock from a fixed 4 MHz input.
The output can then be divided and used for both the
USB and the microcontroller core clock. Because the
PLL has a fixed frequency input and output, there are
eight prescaling options to match the oscillator input
frequency to the PLL.
PIC18FXXXX
(HS Mode)
OSC2
Open
2.2.3
EXTERNAL CLOCK INPUT
The EC, ECIO, ECPLL and ECPIO Oscillator modes
require an external clock source to be connected to the
OSC1 pin. There is no oscillator start-up time required
after a Power-on Reset or after an exit from Sleep
mode.
There is also a separate postscaler option for deriving
the microcontroller clock from the PLL. This allows the
USB peripheral and microcontroller to use the same
oscillator input and still operate at different clock
speeds. In contrast to the postscaler for XT, HS and EC
modes, the available options are 1/2, 1/3, 1/4 and 1/6
of the PLL output.
In the EC and ECPLL Oscillator modes, the oscillator
frequency divided by 4 is available on the OSC2 pin.
This signal may be used for test purposes or to
synchronize other logic. Figure 2-4 shows the pin
connections for the EC Oscillator mode.
The HSPLL, ECPLL and ECPIO modes make use of
the HS mode oscillator for frequencies up to 48 MHz.
The prescaler divides the oscillator input by up to 12 to
produce the 4 MHz drive for the PLL. The XTPLL mode
can only use an input frequency of 4 MHz which drives
the PLL directly.
FIGURE 2-4:
EXTERNAL CLOCK
INPUT OPERATION
(EC AND ECPLL
CONFIGURATION)
FIGURE 2-6:
PLL BLOCK DIAGRAM
(HS MODE)
OSC1/CLKI
Clock from
Ext. System
PIC18FXXXX
OSC2/CLKO
FOSC/4
HS/EC/ECIO/XT Oscillator Enable
PLL Enable
(from CONFIG1H Register)
The ECIO and ECPIO Oscillator modes function like the
EC and ECPLL modes, except that the OSC2 pin
becomes an additional general purpose I/O pin. The I/O
pin becomes bit 6 of PORTA (RA6). Figure 2-5 shows
the pin connections for the ECIO Oscillator mode.
OSC2
Phase
Oscillator
and
Comparator
FIN
OSC1
FOUT
Prescaler
FIGURE 2-5:
EXTERNAL CLOCK
INPUT OPERATION
(ECIO AND ECPIO
CONFIGURATION)
Loop
Filter
VCO
÷24
SYSCLK
OSC1/CLKI
PIC18FXXXX
I/O (OSC2)
Clock from
Ext. System
RA6
The internal postscaler for reducing clock frequency in
XT and HS modes is also available in EC and ECIO
modes.
DS39760D-page 26
© 2008 Microchip Technology Inc.
PIC18F2450/4450
2.2.5
INTERNAL OSCILLATOR
2.3
Oscillator Settings for USB
The PIC18F2450/4450 devices include an internal RC
oscillator (INTRC) which provides a nominal 31 kHz out-
put. INTRC is enabled if it is selected as the device clock
source; it is also enabled automatically when any of the
following are enabled:
When the PIC18F2450/4450 is used for USB
connectivity, it must have either a 6 MHz or 48 MHz
clock for USB operation, depending on whether Low-
Speed or Full-Speed mode is being used. This may
require some forethought in selecting an oscillator
frequency and programming the device.
• Power-up Timer
• Fail-Safe Clock Monitor
• Watchdog Timer
The full range of possible oscillator configurations
compatible with USB operation is shown in Table 2-3.
• Two-Speed Start-up
2.3.1
LOW-SPEED OPERATION
These features are discussed in greater detail in
The USB clock for Low-Speed mode is derived from the
primary oscillator chain and not directly from the PLL. It
is divided by 4 to produce the actual 6 MHz clock.
Because of this, the microcontroller can only use a
clock frequency of 24 MHz when the USB module is
active and the controller clock source is one of the
primary oscillator modes (XT, HS or EC, with or without
the PLL).
Section 18.0 “Special Features of the CPU”.
2.2.5.1
Internal Oscillator Modes
When the internal oscillator is used as the micro-
controller clock source, one of the other oscillator
modes (External Clock or External Crystal/Resonator)
must be used as the USB clock source. The choice of
USB clock source is determined by the particular
internal oscillator mode.
This restriction does not apply if the microcontroller
clock source is the secondary oscillator or internal
oscillator.
There are four distinct modes available:
1. INTHS mode: The USB clock is provided by the
oscillator in HS mode.
2.3.2
RUNNING DIFFERENT USB AND
MICROCONTROLLER CLOCKS
2. INTXT mode: The USB clock is provided by the
oscillator in XT mode.
The USB module, in either mode, can run
asynchronously with respect to the microcontroller core
and other peripherals. This means that applications can
use the primary oscillator for the USB clock while the
microcontroller runs from a separate clock source at a
lower speed. If it is necessary to run the entire application
from only one clock source, full-speed operation provides
a greater selection of microcontroller clock frequencies.
3. INTCKO mode: The USB clock is provided by an
external clock input on OSC1/CLKI; the OSC2/
CLKO pin outputs FOSC/4.
4. INTIO mode: The USB clock is provided by an
external clock input on OSC1/CLKI; the OSC2/
CLKO pin functions as a digital I/O (RA6).
Of these four modes, only INTIO mode frees up an
additional pin (OSC2/CLKO/RA6) for port I/O use.
© 2008 Microchip Technology Inc.
DS39760D-page 27
PIC18F2450/4450
TABLE 2-3:
OSCILLATOR CONFIGURATION OPTIONS FOR USB OPERATION
Input Oscillator
Frequency
PLL Division
(PLLDIV2:PLLDIV0)
Clock Mode
(FOSC3:FOSC0)
MCU Clock Division
(CPUDIV1:CPUDIV0)
Microcontroller
Clock Frequency
None (00)
÷2 (01)
÷3 (10)
÷4 (11)
None (00)
÷2 (01)
÷3 (10)
÷4 (11)
÷2 (00)
÷3 (01)
÷4 (10)
÷6 (11)
None (00)
÷2 (01)
÷3 (10)
÷4 (11)
÷2 (00)
÷3 (01)
÷4 (10)
÷6 (11)
None (00)
÷2 (01)
÷3 (10)
÷4 (11)
÷2 (00)
÷3 (01)
÷4 (10)
÷6 (11)
None (00)
÷2 (01)
÷3 (10)
÷4 (11)
÷2 (00)
÷3 (01)
÷4 (10)
÷6 (11)
None (00)
÷2 (01)
÷3 (10)
÷4 (11)
÷2 (00)
÷3 (01)
÷4 (10)
÷6 (11)
48 MHz
24 MHz
16 MHz
12 MHz
48 MHz
24 MHz
16 MHz
12 MHz
48 MHz
32 MHz
24 MHz
16 MHz
40 MHz
20 MHz
13.33 MHz
10 MHz
48 MHz
32 MHz
24 MHz
16 MHz
24 MHz
12 MHz
8 MHz
(1)
48 MHz
N/A
EC, ECIO
EC, ECIO
48 MHz
40 MHz
24 MHz
20 MHz
16 MHz
÷12 (111)
÷10 (110)
÷6 (101)
÷5 (100)
÷4 (011)
ECPLL, ECPIO
EC, ECIO
ECPLL, ECPIO
HS, EC, ECIO
6 MHz
48 MHz
32 MHz
24 MHz
16 MHz
20 MHz
10 MHz
6.67 MHz
5 MHz
HSPLL, ECPLL, ECPIO
HS, EC, ECIO
48 MHz
32 MHz
24 MHz
16 MHz
16 MHz
8 MHz
HSPLL, ECPLL, ECPIO
HS, EC, ECIO
5.33 MHz
4 MHz
48 MHz
32 MHz
24 MHz
16 MHz
HSPLL, ECPLL, ECPIO
Legend:
All clock frequencies, except 24 MHz, are exclusively associated with full-speed USB operation (USB clock of 48 MHz).
Bold is used to highlight clock selections that are compatible with low-speed USB operation (system clock of 24 MHz,
USB clock of 6 MHz).
Note 1: Only valid when the USBDIV Configuration bit is cleared.
DS39760D-page 28
© 2008 Microchip Technology Inc.
PIC18F2450/4450
TABLE 2-3:
OSCILLATOR CONFIGURATION OPTIONS FOR USB OPERATION (CONTINUED)
Input Oscillator
Frequency
PLL Division
(PLLDIV2:PLLDIV0)
Clock Mode
(FOSC3:FOSC0)
MCU Clock Division
(CPUDIV1:CPUDIV0)
Microcontroller
Clock Frequency
None (00)
÷2 (01)
÷3 (10)
÷4 (11)
÷2 (00)
÷3 (01)
÷4 (10)
÷6 (11)
None (00)
÷2 (01)
÷3 (10)
÷4 (11)
÷2 (00)
÷3 (01)
÷4 (10)
÷6 (11)
None (00)
÷2 (01)
÷3 (10)
÷4 (11)
÷2 (00)
÷3 (01)
÷4 (10)
÷6 (11)
12 MHz
6 MHz
HS, EC, ECIO
HSPLL, ECPLL, ECPIO
HS, EC, ECIO
4 MHz
3 MHz
12 MHz
÷3 (010)
÷2 (001)
÷1 (000)
48 MHz
32 MHz
24 MHz
16 MHz
8 MHz
4 MHz
2.67 MHz
2 MHz
8 MHz
48 MHz
32 MHz
24 MHz
16 MHz
4 MHz
HSPLL, ECPLL, ECPIO
XT, HS, EC, ECIO
2 MHz
1.33 MHz
1 MHz
4 MHz
48 MHz
32 MHz
24 MHz
16 MHz
HSPLL, ECPLL, XTPLL,
ECPIO
Legend:
All clock frequencies, except 24 MHz, are exclusively associated with full-speed USB operation (USB clock of 48 MHz).
Bold is used to highlight clock selections that are compatible with low-speed USB operation (system clock of 24 MHz,
USB clock of 6 MHz).
Note 1: Only valid when the USBDIV Configuration bit is cleared.
© 2008 Microchip Technology Inc.
DS39760D-page 29
PIC18F2450/4450
INTRC always remains the clock source for features
such as the Watchdog Timer and the Fail-Safe Clock
Monitor.
2.4
Clock Sources and Oscillator
Switching
Like previous PIC18 enhanced devices, the
PIC18F2450/4450 family includes a feature that allows
the device clock source to be switched from the main
oscillator to an alternate, low-frequency clock source.
PIC18F2450/4450 devices offer two alternate clock
sources. When an alternate clock source is enabled,
the various power-managed operating modes are
available.
The OSTS and T1RUN bits indicate which clock source
is currently providing the device clock. The OSTS bit
indicates that the Oscillator Start-up Timer (OST) has
timed out and the primary clock is providing the device
clock in primary clock modes. The T1RUN bit
(T1CON<6>) indicates when the Timer1 oscillator is
providing the device clock in secondary clock modes. In
power-managed modes, only one of these three bits will
be set at any time. If none of these bits are set, the
INTRC is providing the clock or the internal oscillator has
just started and is not yet stable.
Essentially, there are three clock sources for these
devices:
• Primary oscillators
• Secondary oscillators
• Internal oscillator
The IDLEN bit determines if the device goes into Sleep
mode, or one of the Idle modes, when the SLEEP
instruction is executed.
The primary oscillators include the External Crystal
and Resonator modes, the External Clock modes and
the internal oscillator. The particular mode is defined by
the FOSC3:FOSC0 Configuration bits. The details of
these modes are covered earlier in this chapter.
The use of the flag and control bits in the OSCCON
register is discussed in more detail in Section 3.0
“Power-Managed Modes”.
Note 1: The Timer1 oscillator must be enabled to
select the secondary clock source. The
Timer1 oscillator is enabled by setting the
T1OSCEN bit in the Timer1 Control regis-
ter (T1CON<3>). If the Timer1 oscillator is
not enabled, then any attempt to select a
secondary clock source will be ignored.
The secondary oscillators are those external sources
not connected to the OSC1 or OSC2 pins. These
sources may continue to operate even after the
controller is placed in a power-managed mode.
PIC18F2450/4450 devices offer the Timer1 oscillator
as a secondary oscillator. This oscillator, in all power-
managed modes, is often the time base for functions
such as a Real-Time Clock (RTC). Most often, a
32.768 kHz watch crystal is connected between the
RC0/T1OSO/T1CKI and RC1/T1OSI/UOE pins. Like
the XT and HS Oscillator mode circuits, loading
capacitors are also connected from each pin to ground.
The Timer1 oscillator is discussed in greater detail in
Section 11.3 “Timer1 Oscillator”.
2: It is recommended that the Timer1
oscillator be operating and stable prior to
switching to it as the clock source; other-
wise, a very long delay may occur while
the Timer1 oscillator starts.
2.4.2
OSCILLATOR TRANSITIONS
PIC18F2450/4450 devices contain circuitry to prevent
clock “glitches” when switching between clock sources.
A short pause in the device clock occurs during the
clock switch. The length of this pause is the sum of two
cycles of the old clock source and three to four cycles
of the new clock source. This formula assumes that the
new clock source is stable.
In addition to being a primary clock source, the internal
oscillator is available as a power-managed mode
clock source. The INTRC source is also used as the
clock source for several special features, such as the
WDT and Fail-Safe Clock Monitor.
2.4.1
OSCILLATOR CONTROL REGISTER
Clock transitions are discussed in greater detail in
Section 3.1.2 “Entering Power-Managed Modes”.
The OSCCON register (Register 2-1) controls several
aspects of the device clock’s operation, both in full-power
operation and in power-managed modes.
The System Clock Select bits, SCS1:SCS0, select the
clock source. The available clock sources are the primary
clock (defined by the FOSC3:FOSC0 Configuration bits),
the secondary clock (Timer1 oscillator) and the internal
oscillator. The clock source changes immediately, after
one or more of the bits is written to, following a brief clock
transition interval. The SCS bits are cleared on all forms
of Reset.
DS39760D-page 30
© 2008 Microchip Technology Inc.
PIC18F2450/4450
REGISTER 2-1:
OSCCON: OSCILLATOR CONTROL REGISTER
R/W-0
IDLEN
bit 7
U-0
—
U-0
—
U-0
—
R(1)
U-0
—
R/W-0
SCS1
R/W-0
SCS0
OSTS
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7
IDLEN: Idle Enable bit
1= Device enters Idle mode on SLEEPinstruction
0= Device enters Sleep mode on SLEEPinstruction
bit 6-4
bit 3
Unimplemented: Read as ‘0’
OSTS: Oscillator Start-up Time-out Status bit(1)
1= Oscillator Start-up Timer time-out has expired; primary oscillator is running
0= Oscillator Start-up Timer time-out is running; primary oscillator is not ready
bit 2
Unimplemented: Read as ‘0’
bit 1-0
SCS1:SCS0: System Clock Select bits
1x= Internal oscillator
01= Timer1 oscillator
00= Primary oscillator
Note 1: Depends on the state of the IESO Configuration bit.
© 2008 Microchip Technology Inc.
DS39760D-page 31
PIC18F2450/4450
Enabling any on-chip feature that will operate during
Sleep will increase the current consumed during Sleep.
The INTRC is required to support WDT operation. The
Timer1 oscillator may be operating to support a Real-
Time Clock. Other features may be operating that do
not require a device clock source (i.e., PSP, INTx pins
and others). Peripherals that may add significant
current consumption are listed in Section 21.2 “DC
Characteristics: Power-Down and Supply Current”.
2.5
Effects of Power-Managed Modes
on the Various Clock Sources
When PRI_IDLE mode is selected, the designated
primary oscillator continues to run without interruption.
For all other power-managed modes, the oscillator
using the OSC1 pin is disabled. Unless the USB
module is enabled, the OSC1 pin (and OSC2 pin if
used by the oscillator) will stop oscillating.
In secondary clock modes (SEC_RUN and
SEC_IDLE), the Timer1 oscillator is operating and
providing the device clock. The Timer1 oscillator may
also run in all power-managed modes if required to
clock Timer1.
2.6
Power-up Delays
Power-up delays are controlled by two timers, so that no
external Reset circuitry is required for most applications.
The delays ensure that the device is kept in Reset until
the device power supply is stable under normal circum-
stances and the primary clock is operating and stable.
For additional information on power-up delays, see
Section 4.5 “Device Reset Timers”.
In internal oscillator modes (RC_RUN and RC_IDLE),
the internal oscillator provides the device clock source.
The 31 kHz INTRC output can be used directly to
provide the clock and may be enabled to support various
special features regardless of the power-managed
mode (see Section 18.2 “Watchdog Timer (WDT)”,
Section 18.3 “Two-Speed Start-up” and Section 18.4
“Fail-Safe Clock Monitor” for more information on
WDT, Fail-Safe Clock Monitor and Two-Speed Start-up).
The first timer is the Power-up Timer (PWRT), which
provides a fixed delay on power-up (parameter 33,
Table 21-10). It is enabled by clearing (= 0) the
PWRTEN Configuration bit.
The second timer is the Oscillator Start-up Timer
(OST), intended to keep the chip in Reset until the
crystal oscillator is stable (XT and HS modes). The
OST does this by counting 1024 oscillator cycles
before allowing the oscillator to clock the device.
Regardless of the Run or Idle mode selected, the USB
clock source will continue to operate. If the device is
operating from a crystal or resonator-based oscillator,
that oscillator will continue to clock the USB module.
The core and all other modules will switch to the new
clock source.
When the HSPLL Oscillator mode is selected, the
device is kept in Reset for an additional 2 ms following
the HS mode OST delay, so the PLL can lock to the
incoming clock frequency.
If the Sleep mode is selected, all clock sources are
stopped. Since all the transistor switching currents
have been stopped, Sleep mode achieves the lowest
current consumption of the device (only leakage
currents).
There is a delay of interval, TCSD (parameter 38,
Table 21-10), following POR, while the controller
becomes ready to execute instructions. This delay runs
concurrently with any other delays. This may be the
only delay that occurs when any of the EC or internal
oscillator modes are used as the primary clock source.
Sleep mode should never be invoked while the USB
module is operating and connected. The only exception
is when the device has been issued a “Suspend” com-
mand over the USB. Once the module has suspended
operation and shifted to a low-power state, the
microcontroller may be safely put into Sleep mode.
TABLE 2-4:
OSC1 AND OSC2 PIN STATES IN SLEEP MODE
Oscillator Mode
OSC1 Pin
OSC2 Pin
INTCKO
INTIO
Floating, pulled by external clock
Floating, pulled by external clock
Floating, pulled by external clock
Floating, pulled by external clock
At logic low (clock/4 output)
Configured as PORTA, bit 6
Configured as PORTA, bit 6
At logic low (clock/4 output)
ECIO, ECPIO
EC
XT and HS
Feedback inverter disabled at quiescent
voltage level
Feedback inverter disabled at quiescent
voltage level
Note:
See Table 4-2 in Section 4.0 “Reset” for time-outs due to Sleep and MCLR Reset.
DS39760D-page 32
© 2008 Microchip Technology Inc.
PIC18F2450/4450
3.1.1
CLOCK SOURCES
3.0
POWER-MANAGED MODES
The SCS1:SCS0 bits allow the selection of one of three
clock sources for power-managed modes. They are:
PIC18F2450/4450 devices offer a total of seven
operating modes for more efficient power
management. These modes provide a variety of
options for selective power conservation in applications
where resources may be limited (i.e., battery-powered
devices).
• The primary clock, as defined by the
FOSC3:FOSC0 Configuration bits
• The secondary clock (the Timer1 oscillator)
• The internal oscillator (for RC modes)
There are three categories of power-managed modes:
3.1.2
ENTERING POWER-MANAGED
MODES
• Run modes
• Idle modes
• Sleep mode
Switching from one power-managed mode to another
begins by loading the OSCCON register. The
SCS1:SCS0 bits select the clock source and determine
which Run or Idle mode is to be used. Changing these
bits causes an immediate switch to the new clock
source, assuming that it is running. The switch may
also be subject to clock transition delays. These are
discussed in Section 3.1.3 “Clock Transitions and
Status Indicators” and subsequent sections.
These categories define which portions of the device
are clocked and sometimes, what speed. The Run and
Idle modes may use any of the three available clock
sources (primary, secondary or internal oscillator); the
Sleep mode does not use a clock source.
The power-managed modes include several power-
saving features offered on previous PIC®
microcontrollers. One is the clock switching feature,
offered in other PIC18 devices, allowing the controller
to use the Timer1 oscillator in place of the primary
oscillator. Also included is the Sleep mode, offered by
all PIC microcontrollers, where all device clocks are
stopped.
Entry to the power-managed Idle or Sleep modes is
triggered by the execution of a SLEEPinstruction. The
actual mode that results depends on the status of the
IDLEN bit.
Depending on the current mode and the mode being
switched to, a change to a power-managed mode does
not always require setting all of these bits. Many
transitions may be done by changing the oscillator
select bits, or changing the IDLEN bit, prior to issuing a
SLEEP instruction. If the IDLEN bit is already
configured correctly, it may only be necessary to
perform a SLEEP instruction to switch to the desired
mode.
3.1
Selecting Power-Managed Modes
Selecting
a power-managed mode requires two
decisions: if the CPU is to be clocked or not and the
selection of clock source. The IDLEN bit
a
(OSCCON<7>) controls CPU clocking, while the
SCS1:SCS0 bits (OSCCON<1:0>) select the clock
source. The individual modes, bit settings, clock sources
and affected modules are summarized in Table 3-1.
TABLE 3-1:
Mode
POWER-MANAGED MODES
OSCCON Bits Module Clocking
CPU Peripherals
Off Off
Clocked Clocked Primary – all oscillator modes.
This is the normal full-power execution mode.
Available Clock and Oscillator Source
IDLEN(1)
SCS1:SCS0
Sleep
0
N/A
None – all clocks are disabled
PRI_RUN
N/A
00
SEC_RUN
RC_RUN
PRI_IDLE
SEC_IDLE
RC_IDLE
N/A
N/A
1
01
1x
00
01
1x
Clocked Clocked Secondary – Timer1 oscillator
Clocked Clocked Internal oscillator(2)
Off
Off
Off
Clocked Primary – all oscillator modes
Clocked Secondary – Timer1 oscillator
Clocked Internal oscillator(2)
1
1
Note 1: IDLEN reflects its value when the SLEEPinstruction is executed.
2: Clock is INTRC source.
© 2008 Microchip Technology Inc.
DS39760D-page 33
PIC18F2450/4450
3.1.3
CLOCK TRANSITIONS AND
STATUS INDICATORS
3.2.1
PRI_RUN MODE
The PRI_RUN mode is the normal, full-power execu-
tion mode of the microcontroller. This is also the default
mode upon a device Reset unless Two-Speed Start-up
is enabled (see Section 18.3 “Two-Speed Start-up”
for details). In this mode, the OSTS bit is set.
The length of the transition between clock sources is
the sum of two cycles of the old clock source and three
to four cycles of the new clock source. This formula
assumes that the new clock source is stable.
Two bits indicate the current clock source and its
status. They are:
3.2.2
SEC_RUN MODE
The SEC_RUN mode is the compatible mode to the
“clock switching” feature offered in other PIC18
devices. In this mode, the CPU and peripherals are
clocked from the Timer1 oscillator. This gives users the
option of lower power consumption while still using a
high accuracy clock source.
• OSTS (OSCCON<3>)
• T1RUN (T1CON<6>)
In general, only one of these bits will be set while in a
given power-managed mode. When the OSTS bit is
set, the primary clock is providing the device clock.
When the T1RUN bit is set, the Timer1 oscillator is
providing the clock.
SEC_RUN mode is entered by setting the SCS1:SCS0
bits to ‘01’. The device clock source is switched to the
Timer1 oscillator (see Figure 3-1), the primary
oscillator is shut down, the T1RUN bit (T1CON<6>) is
set and the OSTS bit is cleared.
Note:
Executing a SLEEP instruction does not
necessarily place the device into Sleep
mode. It acts as the trigger to place the
controller into either the Sleep mode, or
one of the Idle modes, depending on the
setting of the IDLEN bit.
Note:
The Timer1 oscillator should already be
running prior to entering SEC_RUN mode.
If the T1OSCEN bit is not set when the
SCS1:SCS0 bits are set to ‘01’, entry to
SEC_RUN mode will not occur. If the
Timer1 oscillator is enabled but not yet
running, device clocks will be delayed until
the oscillator has started. In such
situations, initial oscillator operation is far
from stable and unpredictable operation
may result.
3.1.4
MULTIPLE SLEEP COMMANDS
The power-managed mode that is invoked with the
SLEEP instruction is determined by the setting of the
IDLEN bit at the time the instruction is executed. If
another SLEEPinstruction is executed, the device will
enter the power-managed mode specified by IDLEN at
that time. If IDLEN has changed, the device will enter
the new power-managed mode specified by the new
setting.
3.2
Run Modes
In the Run modes, clocks to both the core and
peripherals are active. The difference between these
modes is the clock source.
DS39760D-page 34
© 2008 Microchip Technology Inc.
PIC18F2450/4450
On transitions from SEC_RUN mode to PRI_RUN
mode, the peripherals and CPU continue to be clocked
from the Timer1 oscillator while the primary clock is
started. When the primary clock becomes ready, a
clock switch back to the primary clock occurs (see
Figure 3-2). When the clock switch is complete, the
T1RUN bit is cleared, the OSTS bit is set and the
primary clock is providing the clock. The IDLEN and
SCS bits are not affected by the wake-up; the Timer1
oscillator continues to run.
FIGURE 3-1:
TRANSITION TIMING FOR ENTRY TO SEC_RUN MODE
Q1 Q2 Q3 Q4 Q1
Q2
Q3
Q4
Q1
Q2
Q3
1
2
3
n-1
n
T1OSI
OSC1
Clock Transition(1)
CPU
Clock
Peripheral
Clock
Program
Counter
PC
PC + 2
PC + 4
Note 1: Clock transition typically occurs within 2-4 TOSC.
FIGURE 3-2:
TRANSITION TIMING FROM SEC_RUN MODE TO PRI_RUN MODE (HSPLL)
Q1
Q2
Q3
Q4
Q1
Q2 Q3 Q4 Q1 Q2 Q3
T1OSI
OSC1
(1)
TOST
(1)
TPLL
1
2
n-1
n
PLL Clock
Output
Clock(2)
Transition
CPU Clock
Peripheral
Clock
Program
Counter
PC + 2
PC + 4
PC
SCS1:SCS0 bits Changed
OSTS bit Set
Note 1: TOST = 1024 TOSC; TPLL = 2 ms (approx). These intervals are not shown to scale.
2: Clock transition typically occurs within 2-4 TOSC.
© 2008 Microchip Technology Inc.
DS39760D-page 35
PIC18F2450/4450
This mode is entered by setting SCS1 to ‘1’. Although
it is ignored, it is recommended that SCS0 also be
cleared; this is to maintain software compatibility with
future devices. When the clock source is switched to
the INTRC (see Figure 3-3), the primary oscillator is
shut down and the OSTS bit is cleared.
3.2.3
RC_RUN MODE
In RC_RUN mode, the CPU and peripherals are
clocked from the internal oscillator; the primary clock is
shut down. When using the INTRC source, this mode
provides the best power conservation of all the Run
modes while still executing code. It works well for user
applications which are not highly timing sensitive or do
not require high-speed clocks at all times.
On transitions from RC_RUN mode to PRI_RUN mode,
the device continues to be clocked from the INTRC
while the primary clock is started. When the primary
clock becomes ready, a clock switch to the primary
clock occurs (see Figure 3-4). When the clock switch is
complete, the OSTS bit is set and the primary clock is
providing the device clock. The IDLEN and SCS bits
are not affected by the switch. The INTRC source will
continue to run if either the WDT or the Fail-Safe Clock
Monitor is enabled.
If the primary clock source is the internal oscillator
(INTRC), there are no distinguishable differences
between the PRI_RUN and RC_RUN modes during
execution. However, a clock switch delay will occur dur-
ing entry to and exit from RC_RUN mode. Therefore, if
the primary clock source is the internal oscillator, the
use of RC_RUN mode is not recommended.
FIGURE 3-3:
TRANSITION TIMING TO RC_RUN MODE
Q1 Q2 Q3 Q4 Q1
Q2
Q3
Q4
Q1
Q2
Q3
1
2
3
n-1
n
INTRC
OSC1
Clock Transition(1)
CPU
Clock
Peripheral
Clock
Program
Counter
PC
PC + 2
PC + 4
Note 1: Clock transition typically occurs within 2-4 TOSC.
FIGURE 3-4:
TRANSITION TIMING FROM RC_RUN MODE TO PRI_RUN MODE
Q3
Q4
Q1
Q2 Q3 Q4 Q1 Q2 Q3
Q1
Q2
INTRC
OSC1
(1)
TOST
(1)
TPLL
1
2
n-1
n
PLL Clock
Output
Clock(2)
Transition
CPU Clock
Peripheral
Clock
Program
Counter
PC
PC + 2
PC + 4
SCS1:SCS0 bits Changed
OSTS bit Set
Note 1: TOST = 1024 TOSC; TPLL = 2 ms (approx). These intervals are not shown to scale.
2: Clock transition typically occurs within 2-4 TOSC.
DS39760D-page 36
© 2008 Microchip Technology Inc.
PIC18F2450/4450
3.3
Sleep Mode
3.4
Idle Modes
The power-managed Sleep mode in the PIC18F2450/
4450 devices is identical to the legacy Sleep mode
offered in all other PIC microcontrollers. It is entered by
clearing the IDLEN bit (the default state on device
Reset) and executing the SLEEPinstruction. This shuts
down the selected oscillator (Figure 3-5). All clock
source status bits are cleared.
The Idle modes allow the controller’s CPU to be
selectively shut down while the peripherals continue to
operate. Selecting a particular Idle mode allows users
to further manage power consumption.
If the IDLEN bit is set to ‘1’ when a SLEEPinstruction is
executed, the peripherals will be clocked from the clock
source selected using the SCS1:SCS0 bits; however, the
CPU will not be clocked. The clock source status bits are
not affected. Setting IDLEN and executing a SLEEP
instruction provides a quick method of switching from a
given Run mode to its corresponding Idle mode.
Entering the Sleep mode from any other mode does not
require a clock switch. This is because no clocks are
needed once the controller has entered Sleep. If the
WDT is selected, the INTRC source will continue to
operate. If the Timer1 oscillator is enabled, it will also
continue to run.
If the WDT is selected, the INTRC source will continue
to operate. If the Timer1 oscillator is enabled, it will also
continue to run.
When a wake event occurs in Sleep mode (by interrupt,
Reset or WDT time-out), the device will not be clocked
until the clock source selected by the SCS1:SCS0 bits
becomes ready (see Figure 3-6), or it will be clocked
from the internal oscillator if either the Two-Speed
Start-up or the Fail-Safe Clock Monitor are enabled
(see Section 18.0 “Special Features of the CPU”). In
either case, the OSTS bit is set when the primary clock
is providing the device clocks. The IDLEN and SCS bits
are not affected by the wake-up.
Since the CPU is not executing instructions, the only
exits from any of the Idle modes are by interrupt, WDT
time-out or a Reset. When a wake event occurs, CPU
execution is delayed by an interval of TCSD
(parameter 38, Table 21-10) while it becomes ready to
execute code. When the CPU begins executing code,
it resumes with the same clock source for the current
Idle mode. For example, when waking from RC_IDLE
mode, the internal oscillator will clock the CPU and
peripherals (in other words, RC_RUN mode). The
IDLEN and SCS bits are not affected by the wake-up.
While in any Idle mode or Sleep mode, a WDT time-out
will result in a WDT wake-up to the Run mode currently
specified by the SCS1:SCS0 bits.
FIGURE 3-5:
TRANSITION TIMING FOR ENTRY TO SLEEP MODE
Q1 Q2 Q3 Q4 Q1
OSC1
CPU
Clock
Peripheral
Clock
Sleep
Program
Counter
PC
PC + 2
FIGURE 3-6:
TRANSITION TIMING FOR WAKE FROM SLEEP (HSPLL)
Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
Q2 Q3 Q4 Q1 Q2
Q1
OSC1
(1)
(1)
TOST
TPLL
PLL Clock
Output
CPU Clock
Peripheral
Clock
Program
Counter
PC
OSTS bit Set
PC + 2
PC + 4
PC + 6
Wake Event
Note 1: TOST = 1024 TOSC; TPLL = 2 ms (approx). These intervals are not shown to scale.
© 2008 Microchip Technology Inc.
DS39760D-page 37
PIC18F2450/4450
3.4.1
PRI_IDLE MODE
3.4.2
SEC_IDLE MODE
This mode is unique among the three low-power Idle
modes in that it does not disable the primary device
clock. For timing sensitive applications, this allows for
the fastest resumption of device operation, with its
more accurate primary clock source, since the clock
source does not have to “warm up” or transition from
another oscillator.
In SEC_IDLE mode, the CPU is disabled but the
peripherals continue to be clocked from the Timer1
oscillator. This mode is entered from SEC_RUN by
setting the IDLEN bit and executing
a SLEEP
instruction. If the device is in another Run mode, set
IDLEN first, then set SCS1:SCS0 to ‘01’ and execute
SLEEP. When the clock source is switched to the
Timer1 oscillator, the primary oscillator is shut down,
the OSTS bit is cleared and the T1RUN bit is set.
PRI_IDLE mode is entered from PRI_RUN mode by
setting the IDLEN bit and executing
a SLEEP
instruction. If the device is in another Run mode, set
IDLEN first, then clear the SCS bits and execute
SLEEP. Although the CPU is disabled, the peripherals
continue to be clocked from the primary clock source
specified by the FOSC3:FOSC0 Configuration bits.
The OSTS bit remains set (see Figure 3-7).
When a wake event occurs, the peripherals continue to
be clocked from the Timer1 oscillator. After an interval of
TCSD following the wake event, the CPU begins execut-
ing code being clocked by the Timer1 oscillator. The
IDLEN and SCS bits are not affected by the wake-up;
the Timer1 oscillator continues to run (see Figure 3-8).
When a wake event occurs, the CPU is clocked from the
primary clock source. A delay of interval TCSD is
required between the wake event and when code
execution starts. This is required to allow the CPU to
become ready to execute instructions. After the wake-
up, the OSTS bit remains set. The IDLEN and SCS bits
are not affected by the wake-up (see Figure 3-8).
Note:
The Timer1 oscillator should already be
running prior to entering SEC_IDLE mode.
If the T1OSCEN bit is not set when the
SLEEP instruction is executed, the SLEEP
instruction will be ignored and entry to
SEC_IDLE mode will not occur. If the
Timer1 oscillator is enabled but not yet run-
ning, peripheral clocks will be delayed until
the oscillator has started. In such situations,
initial oscillator operation is far from stable
and unpredictable operation may result.
FIGURE 3-7:
TRANSITION TIMING FOR ENTRY TO IDLE MODE
Q3
Q4
Q1
Q1
Q2
OSC1
CPU Clock
Peripheral
Clock
Program
Counter
PC
PC + 2
FIGURE 3-8:
TRANSITION TIMING FOR WAKE FROM IDLE TO RUN MODE
Q1
Q3
Q4
Q2
OSC1
TCSD
CPU Clock
Peripheral
Clock
Program
Counter
PC
Wake Event
DS39760D-page 38
© 2008 Microchip Technology Inc.
PIC18F2450/4450
A fixed delay of interval, TCSD, following the wake
event, is required when leaving Sleep and Idle modes.
This delay is required for the CPU to prepare for execu-
tion. Instruction execution resumes on the first clock
cycle following this delay.
3.4.3
RC_IDLE MODE
In RC_IDLE mode, the CPU is disabled but the periph-
erals continue to be clocked from the internal oscillator,
INTRC. This mode allows for controllable power
conservation during Idle periods.
From RC_RUN, this mode is entered by setting the
IDLEN bit and executing a SLEEP instruction. If the
device is in another Run mode, first set IDLEN, then set
the SCS1 bit and execute SLEEP. Although its value is
ignored, it is recommended that SCS0 also be cleared;
this is to maintain software compatibility with future
devices. When the clock source is switched to the
INTRC, the primary oscillator is shut down and the
OSTS bit is cleared.
3.5.2
EXIT BY WDT TIME-OUT
A WDT time-out will cause different actions depending
on which power-managed mode the device is in when
the time-out occurs.
If the device is not executing code (all Idle modes and
Sleep mode), the time-out will result in an exit from the
power-managed mode (see Section 3.2 “Run
Modes” and Section 3.3 “Sleep Mode”). If the device
is executing code (all Run modes), the time-out will
result in a WDT Reset (see Section 18.2 “Watchdog
Timer (WDT)”).
When a wake event occurs, the peripherals continue to
be clocked from the INTRC. After a delay of TCSD
following the wake event, the CPU begins executing
code being clocked by the INTRC. The IDLEN and SCS
bits are not affected by the wake-up. The INTRC source
will continue to run if either the WDT or the Fail-Safe
Clock Monitor is enabled.
3.5.3
EXIT BY RESET
Normally, the device is held in Reset by the Oscillator
Start-up Timer (OST) until the primary clock becomes
ready. At that time, the OSTS bit is set and the device
begins executing code.
3.5
Exiting Idle and Sleep Modes
The exit delay time from Reset to the start of code
execution depends on both the clock sources before
and after the wake-up and the type of oscillator if the
new clock source is the primary clock. Exit delays are
summarized in Table 3-2.
An exit from Sleep mode or any of the Idle modes is
triggered by an interrupt, a Reset or a WDT time-out.
This section discusses the triggers that cause exits
from power-managed modes. The clocking subsystem
actions are discussed in each of the power-managed
modes (see Section 3.2 “Run Modes”, Section 3.3
“Sleep Mode” and Section 3.4 “Idle Modes”).
Code execution can begin before the primary clock
becomes ready. If either the Two-Speed Start-up (see
Section 18.3 “Two-Speed Start-up”) or Fail-Safe
Clock Monitor (see Section 18.4 “Fail-Safe Clock
Monitor”) is enabled, the device may begin execution
as soon as the Reset source has cleared. Execution is
clocked by the INTRC driven by the internal oscillator.
Execution is clocked by the internal oscillator until
either the primary clock becomes ready or a power-
managed mode is entered before the primary clock
becomes ready; the primary clock is then shut down.
3.5.1
EXIT BY INTERRUPT
Any of the available interrupt sources can cause the
device to exit from an Idle mode, or the Sleep mode, to
a Run mode. To enable this functionality, an interrupt
source must be enabled by setting its enable bit in one
of the INTCON or PIE registers. The exit sequence is
initiated when the corresponding interrupt flag bit is set.
On all exits from Idle or Sleep modes by interrupt, code
execution branches to the interrupt vector if the GIE/
GIEH bit (INTCON<7>) is set. Otherwise, code execution
continues or resumes without branching (see
Section 8.0 “Interrupts”).
© 2008 Microchip Technology Inc.
DS39760D-page 39
PIC18F2450/4450
In these instances, the primary clock source either
does not require an oscillator start-up delay, since it is
already running (PRI_IDLE), or normally does not
require an oscillator start-up delay (EC and any internal
oscillator modes). However, a fixed delay of interval
TCSD following the wake event is still required when
leaving Sleep and Idle modes to allow the CPU to
prepare for execution. Instruction execution resumes
on the first clock cycle following this delay.
3.5.4
EXIT WITHOUT AN OSCILLATOR
START-UP DELAY
Certain exits from power-managed modes do not
invoke the OST at all. There are two cases:
• PRI_IDLE mode, where the primary clock source
is not stopped; and
• The primary clock source is not any of the XT or
HS modes
TABLE 3-2:
EXIT DELAY ON WAKE-UP BY RESET FROM SLEEP MODE OR ANY IDLE MODE
(BY CLOCK SOURCES)
Microcontroller Clock Source
Clock Ready Status
Exit Delay
Bit (OSCCON)
Before Wake-up
After Wake-up
XT, HS
XTPLL, HSPLL
EC
Primary Device Clock
(PRI_IDLE mode)
None
OSTS
OSTS
OSTS
OSTS
INTRC(1)
(3)
XT, HS
TOST
(3)
(3)
(3)
XTPLL, HSPLL
EC
TOST + trc
T1OSC or INTRC(1)
(2)
TCSD
INTRC(1)
TIOBST
(4)
(3)
XT, HS
TOST
XTPLL, HSPLL
EC
TOST + trc
INTRC(1)
(2)
TCSD
INTRC(1)
None
(3)
XT, HS
TOST
XTPLL, HSPLL
EC
TOST + trc
None
(Sleep mode)
(2)
TCSD
(4)
INTRC(1)
TIOBST
Note 1: In this instance, refers specifically to the 31 kHz INTRC clock source.
2: TCSD (parameter 38, Table 21-10) is a required delay when waking from Sleep and all Idle modes and runs
concurrently with any other required delays (see Section 3.4 “Idle Modes”).
3: TOST is the Oscillator Start-up Timer period (parameter 32, Table 21-10). trc is the PLL lock time-out
(parameter F12, Table 21-7); it is also designated as TPLL.
4: Execution continues during TIOBST (parameter 39, Table 21-10), the INTRC stabilization period.
DS39760D-page 40
© 2008 Microchip Technology Inc.
PIC18F2450/4450
A simplified block diagram of the on-chip Reset circuit
is shown in Figure 4-1.
4.0
RESET
The PIC18F2450/4450 devices differentiate between
various kinds of Reset:
4.1
RCON Register
a) Power-on Reset (POR)
Device Reset events are tracked through the RCON
register (Register 4-1). The lower five bits of the
register indicate that a specific Reset event has
occurred. In most cases, these bits can only be cleared
by the event and must be set by the application after
the event. The state of these flag bits, taken together,
can be read to indicate the type of Reset that just
occurred. This is described in more detail in
Section 4.6 “Reset State of Registers”.
b) MCLR Reset during normal operation
c) MCLR Reset during power-managed modes
d) Watchdog Timer (WDT) Reset (during
execution)
e) Programmable Brown-out Reset (BOR)
f) RESETInstruction
g) Stack Full Reset
h) Stack Underflow Reset
The RCON register also has control bits for setting
interrupt priority (IPEN) and software control of the
BOR (SBOREN). Interrupt priority is discussed in
Section 8.0 “Interrupts”. BOR is covered in
Section 4.4 “Brown-out Reset (BOR)”.
This section discusses Resets generated by MCLR,
POR and BOR, and covers the operation of the various
start-up timers. Stack Reset events are covered in
Section 5.1.2.4 “Stack Full and Underflow Resets”.
WDT Resets are covered in Section 18.2 “Watchdog
Timer (WDT)”.
FIGURE 4-1:
SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT
RESETInstruction
Stack Full/Underflow Reset
Stack
Pointer
External Reset
MCLRE
MCLR
( )_IDLE
Sleep
WDT
Time-out
VDD Rise
Detect
POR Pulse
BOREN
VDD
Brown-out
Reset
S
OST/PWRT
OST
10-Bit Ripple Counter
1024 Cycles
Chip_Reset
R
Q
OSC1
32 μs
65.5 ms
PWRT
11-Bit Ripple Counter
INTRC(1)
Enable PWRT
(2)
Enable OST
Note 1: This is the INTRC source from the internal oscillator and is separate from the RC oscillator of the CLKI pin.
2: See Table 4-2 for time-out situations.
© 2008 Microchip Technology Inc.
DS39760D-page 41
PIC18F2450/4450
REGISTER 4-1:
RCON: RESET CONTROL REGISTER
R/W-0
IPEN
R/W-1(1)
U-0
—
R/W-1
RI
R-1
TO
R-1
PD
R/W-0(2)
POR
R/W-0
BOR
SBOREN
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
-n = Value at POR
bit 7
bit 6
IPEN: Interrupt Priority Enable bit
1= Enable priority levels on interrupts
0= Disable priority levels on interrupts (PIC16CXXX Compatibility mode)
SBOREN: BOR Software Enable bit(1)
If BOREN1:BOREN0 = 01:
1= BOR is enabled
0= BOR is disabled
If BOREN1:BOREN0 = 00, 10 or 11:
Bit is disabled and read as ‘0’.
bit 5
bit 4
Unimplemented: Read as ‘0’
RI: RESETInstruction Flag bit
1= The RESETinstruction was not executed (set by firmware only)
0= The RESET instruction was executed causing a device Reset (must be set in software after a
Brown-out Reset occurs)
bit 3
bit 2
bit 1
bit 0
TO: Watchdog Time-out Flag bit
1= Set by power-up, CLRWDTinstruction or SLEEPinstruction
0= A WDT time-out occurred
PD: Power-Down Detection Flag bit
1= Set by power-up or by the CLRWDTinstruction
0= Set by execution of the SLEEPinstruction
POR: Power-on Reset Status bit(2)
1= A Power-on Reset has not occurred (set by firmware only)
0= A Power-on Reset occurred (must be set in software after a Power-on Reset occurs)
BOR: Brown-out Reset Status bit
1= A Brown-out Reset has not occurred (set by firmware only)
0= A Brown-out Reset occurred (must be set in software after a Brown-out Reset occurs)
Note 1: If SBOREN is enabled, its Reset state is ‘1’; otherwise, it is ‘0’.
2: The actual Reset value of POR is determined by the type of device Reset. See the notes following this
register and Section 4.6 “Reset State of Registers” for additional information.
Note 1: It is recommended that the POR bit be set after a Power-on Reset has been detected so that subsequent
Power-on Resets may be detected.
2: Brown-out Reset is said to have occurred when BOR is ‘0’ and POR is ‘1’ (assuming that POR was set to
‘1’ by software immediately after a Power-on Rest).
DS39760D-page 42
© 2008 Microchip Technology Inc.
PIC18F2450/4450
FIGURE 4-2:
EXTERNAL POWER-ON
RESET CIRCUIT (FOR
SLOW VDD POWER-UP)
4.2
Master Clear Reset (MCLR)
The MCLR pin provides a method for triggering an
external Reset of the device. A Reset is generated by
holding the pin low. These devices have a noise filter in
the MCLR Reset path which detects and ignores small
pulses.
VDD
VDD
The MCLR pin is not driven low by any internal Resets,
including the WDT.
D
R
R1
MCLR
In PIC18F2450/4450 devices, the MCLR input can be
disabled with the MCLRE Configuration bit. When
MCLR is disabled, the pin becomes a digital input. See
Section 9.5 “PORTE, TRISE and LATE Registers”
for more information.
PIC18FXXXX
C
Note 1: External Power-on Reset circuit is required
only if the VDD power-up slope is too slow.
The diode D helps discharge the capacitor
quickly when VDD powers down.
4.3
Power-on Reset (POR)
A
Power-on Reset pulse is generated on-chip
2: R < 40 kΩ is recommended to make sure that
the voltage drop across R does not violate
the device’s electrical specification.
whenever VDD rises above a certain threshold. This
allows the device to start in the initialized state when
VDD is adequate for operation.
3: R1 ≥ 1 kΩ will limit any current flowing into
MCLR from external capacitor C, in the event
of MCLR/VPP pin breakdown, due to Electro-
static Discharge (ESD) or Electrical
Overstress (EOS).
To take advantage of the POR circuitry, tie the MCLR pin
through a resistor (1 kΩ to 10 kΩ) to VDD. This will
eliminate external RC components usually needed to
create a Power-on Reset delay. A minimum rise rate for
VDD is specified (parameter D004, Section269 “DC
Characteristics”). For a slow rise time, see Figure 4-2.
When the device starts normal operation (i.e., exits the
Reset condition), device operating parameters (volt-
age, frequency, temperature, etc.) must be met to
ensure operation. If these conditions are not met, the
device must be held in Reset until the operating
conditions are met.
POR events are captured by the POR bit (RCON<1>).
The state of the bit is set to ‘0’ whenever a Power-on
Reset occurs; it does not change for any other Reset
event. POR is not reset to ‘1’ by any hardware event.
To capture multiple events, the user manually resets
the bit to ‘1’ in software following any Power-on Reset.
© 2008 Microchip Technology Inc.
DS39760D-page 43
PIC18F2450/4450
Placing the BOR under software control gives the user
the additional flexibility of tailoring the application to its
environment without having to reprogram the device to
change BOR configuration. It also allows the user to
tailor device power consumption in software by eliminat-
ing the incremental current that the BOR consumes.
While the BOR current is typically very small, it may have
some impact in low-power applications.
4.4
Brown-out Reset (BOR)
PIC18F2450/4450 devices implement a BOR circuit
that provides the user with a number of configuration
and power-saving options. The BOR is controlled by
the
BORV1:BORV0
and
BOREN1:BOREN0
Configuration bits. There are a total of four BOR
configurations which are summarized in Table 4-1.
The BOR threshold is set by the BORV1:BORV0 bits. If
BOR is enabled (any values of BOREN1:BOREN0
except ‘00’), any drop of VDD below VBOR (parameter
D005, Section 269 “DC Characteristics: Supply
Voltage”) for greater than TBOR (parameter 35,
Table 21-10) will reset the device. A Reset may or may
not occur if VDD falls below VBOR for less than TBOR.
The chip will remain in Brown-out Reset until VDD rises
above VBOR.
Note:
Even when BOR is under software control,
the BOR Reset voltage level is still set by
the BORV1:BORV0 Configuration bits. It
cannot be changed in software.
4.4.2
DETECTING BOR
When Brown-out Reset is enabled, the BOR bit always
resets to ‘0’ on any Brown-out Reset or Power-on
Reset event. This makes it difficult to determine if a
Brown-out Reset event has occurred just by reading
the state of BOR alone. A more reliable method is to
simultaneously check the state of both POR and BOR.
This assumes that the POR bit is reset to ‘1’ in software
immediately after any Power-on Reset event. IF BOR
is ‘0’ while POR is ‘1’, it can be reliably assumed that a
Brown-out Reset event has occurred.
If the Power-up Timer is enabled, it will be invoked after
VDD rises above VBOR; it then will keep the chip in
Reset for an additional time delay, TPWRT
(parameter 33, Table 21-10). If VDD drops below VBOR
while the Power-up Timer is running, the chip will go
back into a Brown-out Reset and the Power-up Timer
will be initialized. Once VDD rises above VBOR, the
Power-up Timer will execute the additional time delay.
4.4.3
DISABLING BOR IN SLEEP MODE
BOR and the Power-on Timer (PWRT) are
independently configured. Enabling BOR Reset does
not automatically enable the PWRT.
When BOREN1:BOREN0 = 10, the BOR remains
under hardware control and operates as previously
described. Whenever the device enters Sleep mode,
however, the BOR is automatically disabled. When the
device returns to any other operating mode, BOR is
automatically re-enabled.
4.4.1
SOFTWARE ENABLED BOR
When BOREN1:BOREN0 = 01, the BOR can be
enabled or disabled by the user in software. This is
done with the control bit, SBOREN (RCON<6>).
Setting SBOREN enables the BOR to function as
previously described. Clearing SBOREN disables the
BOR entirely. The SBOREN bit operates only in this
mode; otherwise, it is read as ‘0’.
This mode allows for applications to recover from
brown-out situations, while actively executing code,
when the device requires BOR protection the most. At
the same time, it saves additional power in Sleep mode
by eliminating the small incremental BOR current.
TABLE 4-1:
BOREN1
BOR CONFIGURATIONS
BOR Configuration
Status of
SBOREN
BOR Operation
BOREN0
(RCON<6>)
0
0
1
0
1
0
Unavailable BOR disabled; must be enabled by reprogramming the Configuration bits.
Available BOR enabled in software; operation controlled by SBOREN.
Unavailable BOR enabled in hardware in Run and Idle modes, disabled during
Sleep mode.
1
1
Unavailable BOR enabled in hardware; must be disabled by reprogramming the
Configuration bits.
DS39760D-page 44
© 2008 Microchip Technology Inc.
PIC18F2450/4450
4.5.3
PLL LOCK TIME-OUT
4.5
Device Reset Timers
With the PLL enabled in its PLL mode, the time-out
sequence following a Power-on Reset is slightly differ-
ent from other oscillator modes. A separate timer is
used to provide a fixed time-out that is sufficient for the
PLL to lock to the main oscillator frequency. This PLL
lock time-out (TPLL) is typically 2 ms and follows the
oscillator start-up time-out.
PIC18F2450/4450 devices incorporate three separate
on-chip timers that help regulate the Power-on Reset
process. Their main function is to ensure that the
device clock is stable before code is executed. These
timers are:
• Power-up Timer (PWRT)
• Oscillator Start-up Timer (OST)
• PLL Lock Time-out
4.5.4
TIME-OUT SEQUENCE
On power-up, the time-out sequence is as follows:
4.5.1
POWER-UP TIMER (PWRT)
1. After the POR condition has cleared, PWRT
time-out is invoked (if enabled).
The Power-up Timer (PWRT) of the PIC18F2450/4450
devices is an 11-bit counter which uses the INTRC
source as the clock input. This yields an approximate
time interval of 2048 x 32 μs = 65.6 ms. While the
PWRT is counting, the device is held in Reset.
2. Then, the OST is activated.
The total time-out will vary based on oscillator configu-
ration and the status of the PWRT. Figure 4-3,
Figure 4-4, Figure 4-5, Figure 4-6 and Figure 4-7 all
depict time-out sequences on power-up, with the
Power-up Timer enabled and the device operating in
HS Oscillator mode. Figure 4-3 through Figure 4-6 also
apply to devices operating in XT mode. For devices in
RC mode and with the PWRT disabled, on the other
hand, there will be no time-out at all.
The power-up time delay depends on the INTRC clock
and will vary from chip to chip due to temperature and
process variation. See DC parameter 33 (Table 21-10)
for details.
The PWRT is enabled by clearing the PWRTEN
Configuration bit.
Since the time-outs occur from the POR pulse, if MCLR
is kept low long enough, all time-outs will expire.
Bringing MCLR high will begin execution immediately
(Figure 4-5). This is useful for testing purposes or to
synchronize more than one PIC18FXXXX device
operating in parallel.
4.5.2
OSCILLATOR START-UP
TIMER (OST)
The Oscillator Start-up Timer (OST) provides
a
1024 oscillator cycle (from OSC1 input) delay after the
PWRT delay is over (parameter 33, Table 21-10). This
ensures that the crystal oscillator or resonator has
started and stabilized.
The OST time-out is invoked only for XT, HS and
HSPLL modes and only on Power-on Reset or on exit
from most power-managed modes.
TABLE 4-2:
Oscillator
TIME-OUT IN VARIOUS SITUATIONS
Power-up(2) and Brown-out
Exit from
Configuration
Power-Managed Mode
PWRTEN = 0
PWRTEN = 1
HS, XT
66 ms(1) + 1024 TOSC
66 ms(1) + 1024 TOSC + 2 ms(2)
66 ms(1)
1024 TOSC
1024 TOSC + 2 ms(2)
1024 TOSC
1024 TOSC + 2 ms(2)
HSPLL, XTPLL
EC, ECIO
—
2 ms(2)
—
—
2 ms(2)
—
ECPLL, ECPIO
INTIO, INTCKO
INTHS, INTXT
66 ms(1) + 2 ms(2)
66 ms(1)
66 ms(1) + 1024 TOSC
1024 TOSC
1024 TOSC
Note 1: 66 ms (65.5 ms) is the nominal Power-up Timer (PWRT) delay.
2: 2 ms is the nominal time required for the PLL to lock.
© 2008 Microchip Technology Inc.
DS39760D-page 45
PIC18F2450/4450
FIGURE 4-3:
TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD, VDD RISE < TPWRT)
VDD
MCLR
INTERNAL POR
TPWRT
PWRT TIME-OUT
OST TIME-OUT
TOST
INTERNAL RESET
FIGURE 4-4:
TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 1
VDD
MCLR
INTERNAL POR
TPWRT
PWRT TIME-OUT
OST TIME-OUT
TOST
INTERNAL RESET
FIGURE 4-5:
TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 2
VDD
MCLR
INTERNAL POR
TPWRT
PWRT TIME-OUT
OST TIME-OUT
TOST
INTERNAL RESET
DS39760D-page 46
© 2008 Microchip Technology Inc.
PIC18F2450/4450
FIGURE 4-6:
SLOW RISE TIME (MCLR TIED TO VDD, VDD RISE > TPWRT)
5V
1V
0V
VDD
MCLR
INTERNAL POR
TPWRT
PWRT TIME-OUT
TOST
OST TIME-OUT
INTERNAL RESET
FIGURE 4-7:
TIME-OUT SEQUENCE ON POR w/PLL ENABLED (MCLR TIED TO VDD)
VDD
MCLR
INTERNAL POR
TPWRT
PWRT TIME-OUT
OST TIME-OUT
TOST
TPLL
PLL TIME-OUT
INTERNAL RESET
Note:
TOST = 1024 clock cycles.
TPLL ≈ 2 ms max. First three stages of the Power-up Timer.
© 2008 Microchip Technology Inc.
DS39760D-page 47
PIC18F2450/4450
POR and BOR, are set or cleared differently in different
Reset situations as indicated in Table 4-3. These bits
are used in software to determine the nature of the
Reset.
4.6
Reset State of Registers
Most registers are unaffected by a Reset. Their status
is unknown on POR and unchanged by all other
Resets. The other registers are forced to a “Reset
state” depending on the type of Reset that occurred.
Table 4-4 describes the Reset states for all of the
Special Function Registers. These are categorized by
Power-on and Brown-out Resets, Master Clear and
WDT Resets and WDT wake-ups.
Most registers are not affected by a WDT wake-up,
since this is viewed as the resumption of normal oper-
ation. Status bits from the RCON register, RI, TO, PD,
TABLE 4-3:
STATUS BITS, THEIR SIGNIFICANCE AND THE INITIALIZATION CONDITION
FOR RCON REGISTER
RCON Register
STKPTR Register
Program
Counter
Condition
SBOREN RI
TO
PD POR BOR STKFUL STKUNF
Power-on Reset
RESETinstruction
Brown-out Reset
0000h
0000h
0000h
0000h
1
1
0
1
u
1
u
1
1
1
u
1
u
0
u
u
u
0
u
0
u
0
u
u
u
0
u
u
u
u(2)
u(2)
u(2)
MCLR Reset during power-managed
Run modes
MCLR Reset during power-managed
Idle modes and Sleep mode
0000h
0000h
0000h
u(2)
u(2)
u(2)
u
u
u
1
0
u
0
u
u
u
u
u
u
u
u
u
u
u
u
u
u
WDT time-out during full-power or
power-managed Run modes
MCLR Reset during full-power
execution
Stack Full Reset (STVREN = 1)
0000h
0000h
u(2)
u(2)
u
u
u
u
u
u
u
u
u
u
1
u
u
1
Stack Underflow Reset
(STVREN = 1)
Stack Underflow Error (not an actual
Reset, STVREN = 0)
0000h
PC + 2
u(2)
u(2)
u(2)
u
u
u
u
0
u
u
0
0
u
u
u
u
u
u
u
u
u
1
u
u
WDT time-out during power-managed
Idle or Sleep modes
Interrupt exit from
PC + 2(1)
power-managed modes
Legend: u= unchanged
Note 1: When the wake-up is due to an interrupt and the GIEH or GIEL bit is set, the PC is loaded with the
interrupt vector (008h or 0018h).
2: Reset state is ‘1’ for POR and unchanged for all other Resets when software BOR is enabled
(BOREN1:BOREN0 Configuration bits = 01and SBOREN = 1); otherwise, the Reset state is ‘0’.
DS39760D-page 48
© 2008 Microchip Technology Inc.
PIC18F2450/4450
TABLE 4-4:
Register
INITIALIZATION CONDITIONS FOR ALL REGISTERS
MCLR Resets,
WDT Reset,
Power-on Reset,
Brown-out Reset
Wake-up via WDT
or Interrupt
Applicable Devices
RESET Instruction,
Stack Resets
TOSU
2450
2450
2450
2450
2450
2450
2450
2450
2450
2450
2450
2450
2450
2450
2450
2450
2450
2450
2450
2450
2450
2450
2450
2450
2450
2450
2450
2450
2450
2450
2450
2450
4450
4450
4450
4450
4450
4450
4450
4450
4450
4450
4450
4450
4450
4450
4450
4450
4450
4450
4450
4450
4450
4450
4450
4450
4450
4450
4450
4450
4450
4450
4450
4450
---0 0000
0000 0000
0000 0000
00-0 0000
---0 0000
0000 0000
0000 0000
--00 0000
0000 0000
0000 0000
0000 0000
xxxx xxxx
xxxx xxxx
0000 000x
1111 -1-1
11-0 0-00
N/A
---0 0000
0000 0000
0000 0000
uu-0 0000
---0 0000
0000 0000
0000 0000
--00 0000
0000 0000
0000 0000
0000 0000
uuuu uuuu
uuuu uuuu
0000 000u
1111 -1-1
11-0 0-00
N/A
---0 uuuu(1)
uuuu uuuu(1)
uuuu uuuu(1)
uu-u uuuu(1)
---u uuuu
uuuu uuuu
PC + 2(3)
--uu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu(2)
uuuu -u-u(2)
uu-u u-uu(2)
N/A
TOSH
TOSL
STKPTR
PCLATU
PCLATH
PCL
TBLPTRU
TBLPTRH
TBLPTRL
TABLAT
PRODH
PRODL
INTCON
INTCON2
INTCON3
INDF0
POSTINC0
POSTDEC0
PREINC0
PLUSW0
FSR0H
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
---- 0000
xxxx xxxx
xxxx xxxx
N/A
---- 0000
uuuu uuuu
uuuu uuuu
N/A
---- uuuu
uuuu uuuu
uuuu uuuu
N/A
FSR0L
WREG
INDF1
POSTINC1
POSTDEC1
PREINC1
PLUSW1
FSR1H
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
---- 0000
xxxx xxxx
---- 0000
---- 0000
uuuu uuuu
---- 0000
---- uuuu
uuuu uuuu
---- uuuu
FSR1L
BSR
Legend: u= unchanged, x= unknown, -= unimplemented bit, read as ‘0’, q= value depends on condition.
Shaded cells indicate conditions do not apply for the designated device.
Note 1: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are
updated with the current value of the PC. The STKPTR is modified to point to the next location in the
hardware stack.
2: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).
3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the
interrupt vector (0008h or 0018h).
4: See Table 4-3 for Reset value for specific condition.
5: PORTA<6>, LATA<6> and TRISA<6> are enabled depending on the oscillator mode selected. When not
enabled as PORTA pins, they are disabled and read ‘0’.
© 2008 Microchip Technology Inc.
DS39760D-page 49
PIC18F2450/4450
TABLE 4-4:
INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)
MCLR Resets,
WDT Reset,
RESET Instruction,
Stack Resets
Power-on Reset,
Brown-out Reset
Wake-up via WDT
or Interrupt
Register
Applicable Devices
INDF2
2450
2450
2450
2450
2450
2450
2450
2450
2450
2450
2450
2450
2450
2450
2450
2450
2450
2450
2450
2450
2450
2450
2450
2450
2450
2450
2450
2450
2450
2450
2450
2450
4450
4450
4450
4450
4450
4450
4450
4450
4450
4450
4450
4450
4450
4450
4450
4450
4450
4450
4450
4450
4450
4450
4450
4450
4450
4450
4450
4450
4450
4450
4450
4450
N/A
N/A
N/A
POSTINC2
POSTDEC2
PREINC2
PLUSW2
FSR2H
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
---- 0000
xxxx xxxx
---x xxxx
0000 0000
xxxx xxxx
1111 1111
0--- q-00
0-00 0101
---- ---0
0q-1 11q0
xxxx xxxx
xxxx xxxx
0000 0000
0000 0000
1111 1111
-000 0000
xxxx xxxx
xxxx xxxx
--00 0000
--00 qqqq
0-00 0000
xxxx xxxx
xxxx xxxx
--00 0000
01-0 0-00
0000 0000
0000 0000
---- 0000
uuuu uuuu
---u uuuu
0000 0000
uuuu uuuu
1111 1111
0--- 0-q0
0-00 0101
---- ---0
0q-q qquu
uuuu uuuu
uuuu uuuu
u0uu uuuu
0000 0000
1111 1111
-000 0000
uuuu uuuu
uuuu uuuu
--00 0000
--00 qqqq
0-00 0000
uuuu uuuu
uuuu uuuu
--00 0000
01-0 0-00
0000 0000
0000 0000
---- uuuu
uuuu uuuu
---u uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
u--- u-qu
u-uu uuuu
---- ---u
uq-u qquu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
1111 1111
-uuu uuuu
uuuu uuuu
uuuu uuuu
--uu uuuu
--uu uuuu
u-uu uuuu
uuuu uuuu
uuuu uuuu
--uu uuuu
uu-u u-uu
uuuu uuuu
uuuu uuuu
FSR2L
STATUS
TMR0H
TMR0L
T0CON
OSCCON
HLVDCON
WDTCON
RCON(4)
TMR1H
TMR1L
T1CON
TMR2
PR2
T2CON
ADRESH
ADRESL
ADCON0
ADCON1
ADCON2
CCPR1H
CCPR1L
CCP1CON
BAUDCON
SPBRG
RCREG
Legend: u= unchanged, x= unknown, -= unimplemented bit, read as ‘0’, q= value depends on condition.
Shaded cells indicate conditions do not apply for the designated device.
Note 1: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are
updated with the current value of the PC. The STKPTR is modified to point to the next location in the
hardware stack.
2: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).
3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the
interrupt vector (0008h or 0018h).
4: See Table 4-3 for Reset value for specific condition.
5: PORTA<6>, LATA<6> and TRISA<6> are enabled depending on the oscillator mode selected. When not
enabled as PORTA pins, they are disabled and read ‘0’.
DS39760D-page 50
© 2008 Microchip Technology Inc.
PIC18F2450/4450
TABLE 4-4:
Register
INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)
MCLR Resets,
WDT Reset,
Power-on Reset,
Brown-out Reset
Wake-up via WDT
or Interrupt
Applicable Devices
RESET Instruction,
Stack Resets
TXREG
TXSTA
RCSTA
EECON2
EECON1
IPIR2
2450
2450
2450
2450
2450
2450
2450
2450
2450
2450
2450
2450
2450
2450
2450
2450
2450
2450
2450
2450
2450
2450
2450
2450
2450
2450
2450
2450
2450
2450
2450
2450
4450
4450
4450
4450
4450
4450
4450
4450
4450
4450
4450
4450
4450
4450
4450
4450
4450
4450
4450
4450
4450
4450
4450
4450
4450
4450
4450
4450
4450
4450
4450
4450
0000 0000
0000 0010
0000 000x
0000 0000
-x-0 x00-
1-1- -1--
0-0- -0--
0-0- -0--
-111 -111
-000 -000
-000 -000
---- -111
1111 1111
11-- -111
1111 1111
-111 1111(5)
---- -xxx
xxxx xxxx
xx-- -xxx
xxxx xxxx
-xxx xxxx(5)
---- x000
xxxx xxxx
xxxx -xxx
xxxx xxxx
-x0x 0000(5)
---0 0000
---0 0000
---0 0000
---0 0000
---0 0000
---0 0000
0000 0000
0000 0010
0000 000x
0000 0000
-u-0 u00-
1-1- -1--
0-0- -0--
0-0- -0--
-111 -111
-000 -000
-000 -000
---- -111
1111 1111
11-- -111
1111 1111
-111 1111(5)
---- -uuu
uuuu uuuu
uu-- -uuu
uuuu uuuu
-uuu uuuu(5)
---- x000
uuuu uuuu
uuuu -uuu
uuuu uuuu
-u0u 0000(5)
---0 0000
---0 0000
---0 0000
---0 0000
---0 0000
---0 0000
uuuu uuuu
uuuu uuuu
uuuu uuuu
0000 0000
-u-0 u00-
u-u- -u--
u-u- -u--(2)
u-u- -u--
-uuu -uuu
-uuu -uuu(2)
-uuu -uuu
---- -uuu
uuuu uuuu
uu-- -uuu
uuuu uuuu
-uuu uuuu(5)
---- -uuu
uuuu uuuu
uu-- -uuu
uuuu uuuu
-uuu uuuu(5)
---- uuuu
uuuu uuuu
uuuu -uuu
uuuu uuuu
-uuu uuuu(5)
---u uuuu
---u uuuu
---u uuuu
---u uuuu
---u uuuu
---u uuuu
PIR2
PIE2
IPR1
PIR1
PIE1
TRISE
TRISD
TRISC
TRISB
TRISA(5)
LATE
LATD
LATC
LATB
LATA(5)
PORTE
PORTD
PORTC
PORTB
PORTA(5)
UEP15
UEP14
UEP13
UEP12
UEP11
UEP10
Legend: u= unchanged, x= unknown, -= unimplemented bit, read as ‘0’, q= value depends on condition.
Shaded cells indicate conditions do not apply for the designated device.
Note 1: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are
updated with the current value of the PC. The STKPTR is modified to point to the next location in the
hardware stack.
2: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).
3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the
interrupt vector (0008h or 0018h).
4: See Table 4-3 for Reset value for specific condition.
5: PORTA<6>, LATA<6> and TRISA<6> are enabled depending on the oscillator mode selected. When not
enabled as PORTA pins, they are disabled and read ‘0’.
© 2008 Microchip Technology Inc.
DS39760D-page 51
PIC18F2450/4450
TABLE 4-4:
INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)
MCLR Resets,
WDT Reset,
RESET Instruction,
Stack Resets
Power-on Reset,
Brown-out Reset
Wake-up via WDT
or Interrupt
Register
Applicable Devices
UEP9
UEP8
UEP7
UEP6
UEP5
UEP4
UEP3
UEP2
UEP1
UEP0
UCFG
UADDR
UCON
USTAT
UEIE
2450
2450
2450
2450
2450
2450
2450
2450
2450
2450
2450
2450
2450
2450
2450
2450
2450
2450
2450
2450
4450
4450
4450
4450
4450
4450
4450
4450
4450
4450
4450
4450
4450
4450
4450
4450
4450
4450
4450
4450
---0 0000
---0 0000
---0 0000
---0 0000
---0 0000
---0 0000
---0 0000
---0 0000
---0 0000
---0 0000
00-0 0000
-000 0000
-0x0 000-
-xxx xxx-
0--0 0000
0--0 0000
-000 0000
-000 0000
---- -xxx
xxxx xxxx
---0 0000
---0 0000
---0 0000
---0 0000
---0 0000
---0 0000
---0 0000
---0 0000
---0 0000
---0 0000
00-0 0000
-000 0000
-0x0 000-
-xxx xxx-
0--0 0000
0--0 0000
-000 0000
-000 0000
---- -xxx
xxxx xxxx
---u uuuu
---u uuuu
---u uuuu
---u uuuu
---u uuuu
---u uuuu
---u uuuu
---u uuuu
---u uuuu
---u uuuu
uu-u uuuu
-uuu uuuu
-uuu uuu-
-uuu uuu-
u--u uuuu
u--u uuuu
-uuu uuuu
-uuu uuuu
---- -uuu
uuuu uuuu
UEIR
UIE
UIR
UFRMH
UFRML
Legend: u= unchanged, x= unknown, -= unimplemented bit, read as ‘0’, q= value depends on condition.
Shaded cells indicate conditions do not apply for the designated device.
Note 1: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are
updated with the current value of the PC. The STKPTR is modified to point to the next location in the
hardware stack.
2: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).
3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the
interrupt vector (0008h or 0018h).
4: See Table 4-3 for Reset value for specific condition.
5: PORTA<6>, LATA<6> and TRISA<6> are enabled depending on the oscillator mode selected. When not
enabled as PORTA pins, they are disabled and read ‘0’.
DS39760D-page 52
© 2008 Microchip Technology Inc.
PIC18F2450/4450
5.1
Program Memory Organization
5.0
MEMORY ORGANIZATION
PIC18 microcontrollers implement a 21-bit program
counter which is capable of addressing a 2-Mbyte
program memory space. Accessing a location between
the upper boundary of the physically implemented
memory and the 2-Mbyte address will return all ‘0’s (a
NOPinstruction).
There are two types of memory in PIC18F2450/4450
microcontroller devices:
• Program Memory
• Data RAM
As Harvard architecture devices, the data and program
memories use separate busses; this allows for
concurrent access of the two memory spaces.
The PIC18F2450 and PIC18F4450 each have 16 Kbytes
of Flash memory and can store up to 8192 single-word
instructions.
Additional detailed information on the operation of the
Flash program memory is provided in Section 6.0
“Flash Program Memory”.
PIC18 devices have two interrupt vectors. The Reset
vector address is at 0000h and the interrupt vector
addresses are at 0008h and 0018h.
The program memory maps for PIC18F2450 and
PIC18F4450 devices are shown in Figure 5-1.
FIGURE 5-1:
PROGRAM MEMORY MAP AND STACK FOR PIC18F2450/4450 DEVICES
PIC18F2450/4450
PC<20:0>
21
CALL, RCALL, RETURN,
RETFIE, RETLW, CALLW,
ADDULNK, SUBULNK
Stack Level 1
•
•
•
Stack Level 31
Reset Vector
0000h
0008h
High-Priority Interrupt Vector
Low-Priority Interrupt Vector 0018h
On-Chip
Program Memory
3FFFh
4000h
Read ‘0’
1FFFFFh
200000h
© 2008 Microchip Technology Inc.
DS39760D-page 53
PIC18F2450/4450
The stack operates as a 31-word by 21-bit RAM and a
5-bit Stack Pointer, STKPTR. The stack space is not
part of either program or data space. The Stack Pointer
is readable and writable and the address on the top of
the stack is readable and writable through the Top-of-
Stack Special Function Registers. Data can also be
pushed to, or popped from the stack, using these
registers.
5.1.1
PROGRAM COUNTER
The Program Counter (PC) specifies the address of the
instruction to fetch for execution. The PC is 21 bits wide
and is contained in three separate 8-bit registers. The
low byte, known as the PCL register, is both readable
and writable. The high byte, or PCH register, contains
the PC<15:8> bits; it is not directly readable or writable.
Updates to the PCH register are performed through the
PCLATH register. The upper byte is called PCU. This
register contains the PC<20:16> bits; it is also not
directly readable or writable. Updates to the PCU
register are performed through the PCLATU register.
A CALLtype instruction causes a push onto the stack.
The Stack Pointer is first incremented and the location
pointed to by the Stack Pointer is written with the
contents of the PC (already pointing to the instruction
following the CALL). A RETURNtype instruction causes
a pop from the stack. The contents of the location
pointed to by the STKPTR are transferred to the PC
and then the Stack Pointer is decremented.
The contents of PCLATH and PCLATU are transferred
to the program counter by any operation that writes
PCL. Similarly, the upper two bytes of the program
counter are transferred to PCLATH and PCLATU by an
operation that reads PCL. This is useful for computed
offsets to the PC (see Section 5.1.4.1 “Computed
GOTO”).
The Stack Pointer is initialized to ‘00000’ after all
Resets. There is no RAM associated with the location
corresponding to a Stack Pointer value of ‘00000’; this
is only a Reset value. Status bits indicate if the stack is
full, has overflowed or has underflowed.
The PC addresses bytes in the program memory. To
prevent the PC from becoming misaligned with word
instructions, the Least Significant bit of PCL is fixed to
a value of ‘0’. The PC increments by 2 to address
sequential instructions in the program memory.
5.1.2.1
Only the top of the return address stack (TOS) is
readable and writable. set of three registers,
Top-of-Stack Access
A
The CALL, RCALL and GOTO program branch
instructions write to the program counter directly. For
these instructions, the contents of PCLATH and
PCLATU are not transferred to the program counter.
TOSU:TOSH:TOSL, hold the contents of the stack loca-
tion pointed to by the STKPTR register (Figure 5-2). This
allows users to implement a software stack if necessary.
After a CALL, RCALLor interrupt, the software can read
the pushed value by reading the TOSU:TOSH:TOSL
registers. These values can be placed on a user-defined
software stack. At return time, the software can return
these values to TOSU:TOSH:TOSL and do a return.
5.1.2
RETURN ADDRESS STACK
The return address stack allows any combination of up
to 31 program calls and interrupts to occur. The PC is
pushed onto the stack when a CALL or RCALL
instruction is executed or an interrupt is Acknowledged.
The PC value is pulled off the stack on a RETURN,
RETLWor a RETFIEinstruction. PCLATU and PCLATH
are not affected by any of the RETURN or CALL
instructions.
The user must disable the global interrupt enable bits
while accessing the stack to prevent inadvertent stack
corruption.
FIGURE 5-2:
RETURN ADDRESS STACK AND ASSOCIATED REGISTERS
Return Address Stack<20:0>
11111
11110
11101
Top-of-Stack Registers
Stack Pointer
STKPTR<4:0>
TOSU
00h
TOSH
1Ah
TOSL
34h
00010
00011
00010
00001
00000
001A34h
000D58h
Top-of-Stack
DS39760D-page 54
© 2008 Microchip Technology Inc.
PIC18F2450/4450
When the stack has been popped enough times to
unload the stack, the next pop will return a value of zero
to the PC and sets the STKUNF bit, while the Stack
Pointer remains at zero. The STKUNF bit will remain
set until cleared by software or until a POR occurs.
5.1.2.2
Return Stack Pointer (STKPTR)
The STKPTR register (Register 5-1) contains the Stack
Pointer value, the STKFUL (Stack Full) status bit and
the STKUNF (Stack Underflow) status bit. The value of
the Stack Pointer can be 0 through 31. The Stack
Pointer increments before values are pushed onto the
stack and decrements after values are popped off the
stack. On Reset, the Stack Pointer value will be zero.
The user may read and write the Stack Pointer value.
This feature can be used by a Real-Time Operating
System (RTOS) for return stack maintenance.
Note:
Returning a value of zero to the PC on an
underflow has the effect of vectoring the
program to the Reset vector, where the
stack conditions can be verified and
appropriate actions can be taken. This is
not the same as a Reset, as the contents
of the SFRs are not affected.
After the PC is pushed onto the stack 31 times (without
popping any values off the stack), the STKFUL bit is
set. The STKFUL bit is cleared by software or by a
POR.
5.1.2.3
PUSHand POPInstructions
Since the Top-of-Stack is readable and writable, the
ability to push values onto the stack and pull values off
the stack, without disturbing normal program execu-
tion, is a desirable feature. The PIC18 instruction set
includes two instructions, PUSH and POP, that permit
the TOS to be manipulated under software control.
TOSU, TOSH and TOSL can be modified to place data
or a return address on the stack.
The action that takes place when the stack becomes
full depends on the state of the STVREN (Stack
Overflow Reset Enable) Configuration bit. (Refer to
Section 18.1 “Configuration Bits” for a description of
the device Configuration bits.) If STVREN is set
(default), the 31st push will push the (PC + 2) value
onto the stack, set the STKFUL bit and reset the
device. The STKFUL bit will remain set and the Stack
Pointer will be set to zero.
The PUSHinstruction places the current PC value onto
the stack. This increments the Stack Pointer and loads
the current PC value onto the stack.
If STVREN is cleared, the STKFUL bit will be set on the
31st push and the Stack Pointer will increment to 31.
Any additional pushes will not overwrite the 31st push
and the STKPTR will remain at 31.
The POP instruction discards the current TOS by
decrementing the Stack Pointer. The previous value
pushed onto the stack then becomes the TOS value.
REGISTER 5-1:
STKPTR: STACK POINTER REGISTER
R/C-0
STKFUL(1)
bit 7
R/C-0
STKUNF(1)
U-0
—
R/W-0
SP4
R/W-0
SP3
R/W-0
SP2
R/W-0
SP1
R/W-0
SP0
bit 0
Legend:
C = Clearable bit
W = Writable bit
‘1’ = Bit is set
R = Readable bit
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
-n = Value at POR
bit 7
bit 6
STKFUL: Stack Full Flag bit(1)
1= Stack became full or overflowed
0= Stack has not become full or overflowed
STKUNF: Stack Underflow Flag bit(1)
1= Stack underflow occurred
0= Stack underflow did not occur
bit 5
Unimplemented: Read as ‘0’
bit 4-0
SP4:SP0: Stack Pointer Location bits
Note 1: Bit 7 and bit 6 are cleared by user software or by a POR.
© 2008 Microchip Technology Inc.
DS39760D-page 55
PIC18F2450/4450
5.1.2.4
Stack Full and Underflow Resets
5.1.4
LOOK-UP TABLES IN PROGRAM
MEMORY
Device Resets on stack overflow and stack underflow
conditions are enabled by setting the STVREN bit in
Configuration Register 4L. When STVREN is set, a full
or underflow condition will set the appropriate STKFUL
or STKUNF bit and then cause a device Reset. When
STVREN is cleared, a full or underflow condition will set
the appropriate STKFUL or STKUNF bit but not cause
a device Reset. The STKFUL or STKUNF bits are
cleared by user software or a Power-on Reset.
There may be programming situations that require the
creation of data structures, or look-up tables, in
program memory. For PIC18 devices, look-up tables
can be implemented in two ways:
• Computed GOTO
• Table Reads
5.1.4.1
Computed GOTO
5.1.3
FAST REGISTER STACK
A computed GOTOis accomplished by adding an offset
to the program counter. An example is shown in
Example 5-2.
A Fast Register Stack is provided for the STATUS,
WREG and BSR registers to provide a “fast return”
option for interrupts. Each stack is only one level deep
and is neither readable nor writable. It is loaded with the
current value of the corresponding register when the
processor vectors for an interrupt. All interrupt sources
will push values into the stack registers. The values in
the registers are then loaded back into their associated
registers if the RETFIE, FAST instruction is used to
return from the interrupt.
A look-up table can be formed with an ADDWF PCL
instruction and a group of RETLW nninstructions. The
W register is loaded with an offset into the table before
executing a call to that table. The first instruction of the
called routine is the ADDWF PCLinstruction. The next
instruction executed will be one of the RETLW nn
instructions that returns the value ‘nn’ to the calling
function.
If both low and high-priority interrupts are enabled, the
stack registers cannot be used reliably to return from
low-priority interrupts. If a high-priority interrupt occurs
while servicing a low-priority interrupt, the stack
register values stored by the low-priority interrupt will
be overwritten. In these cases, users must save the key
registers in software during a low-priority interrupt.
The offset value (in WREG) specifies the number of
bytes that the program counter should advance and
should be multiples of 2 (LSb = 0).
In this method, only one data byte may be stored in
each instruction location and room on the return
address stack is required.
If interrupt priority is not used, all interrupts may use the
Fast Register Stack for returns from interrupt. If no
interrupts are used, the Fast Register Stack can be
used to restore the STATUS, WREG and BSR registers
at the end of a subroutine call. To use the Fast Register
Stack for a subroutine call, a CALL label, FAST
instruction must be executed to save the STATUS,
WREG and BSR registers to the Fast Register Stack. A
RETURN,FASTinstruction is then executed to restore
these registers from the Fast Register Stack.
EXAMPLE 5-2:
COMPUTED GOTO USING
AN OFFSET VALUE
MOVF
CALL
OFFSET, W
TABLE
ORG
TABLE
nn00h
ADDWF
RETLW
RETLW
RETLW
.
PCL
nnh
nnh
nnh
.
.
Example 5-1 shows a source code example that uses
the Fast Register Stack during a subroutine call and
return.
5.1.4.2
Table Reads and Table Writes
A better method of storing data in program memory
allows two bytes of data to be stored in each instruction
location.
EXAMPLE 5-1:
FAST REGISTER STACK
CODE EXAMPLE
CALL SUB1, FAST
;STATUS, WREG, BSR
;SAVED IN FAST REGISTER
;STACK
Look-up table data may be stored two bytes per
program word by using table reads and writes. The
Table Pointer (TBLPTR) register specifies the byte
address and the Table Latch (TABLAT) register
contains the data that is read from or written to program
memory. Data is transferred to or from program
memory one byte at a time.
•
•
SUB1
•
•
RETURN, FAST ;RESTORE VALUES SAVED
;IN FAST REGISTER STACK
Table read and table write operations are discussed
further in Section 6.1 “Table Reads and Table
Writes”.
DS39760D-page 56
© 2008 Microchip Technology Inc.
PIC18F2450/4450
5.2.2
INSTRUCTION FLOW/PIPELINING
5.2
PIC18 Instruction Cycle
An “Instruction Cycle” consists of four Q cycles: Q1
through Q4. The instruction fetch and execute are
pipelined in such a manner that a fetch takes one
instruction cycle, while the decode and execute takes
another instruction cycle. However, due to the
pipelining, each instruction effectively executes in one
cycle. If an instruction causes the program counter to
change (e.g., GOTO), then two cycles are required to
complete the instruction (Example 5-3).
5.2.1
CLOCKING SCHEME
The microcontroller clock input, whether from an
internal or external source, is internally divided by four
to generate four non-overlapping quadrature clocks
(Q1, Q2, Q3 and Q4). Internally, the program counter is
incremented on every Q1; the instruction is fetched
from the program memory and latched into the Instruc-
tion Register (IR) during Q4. The instruction is decoded
and executed during the following Q1 through Q4. The
clocks and instruction execution flow are shown in
Figure 5-3.
A fetch cycle begins with the Program Counter (PC)
incrementing in Q1.
In the execution cycle, the fetched instruction is latched
into the Instruction Register (IR) in cycle Q1. This
instruction is then decoded and executed during the
Q2, Q3 and Q4 cycles. Data memory is read during Q2
(operand read) and written during Q4 (destination
write).
FIGURE 5-3:
CLOCK/INSTRUCTION CYCLE
Q2
Q3
Q4
Q2
Q3
Q4
Q2
Q3
Q4
Q1
Q1
Q1
OSC1
Q1
Q2
Q3
Q4
Internal
Phase
Clock
PC
PC
PC + 2
PC + 4
OSC2/CLKO
(RC mode)
Execute INST (PC – 2)
Fetch INST (PC)
Execute INST (PC)
Fetch INST (PC + 2)
Execute INST (PC + 2)
Fetch INST (PC + 4)
EXAMPLE 5-3:
INSTRUCTION PIPELINE FLOW
TCY0
TCY1
TCY2
TCY3
TCY4
TCY5
1. MOVLW 55h
2. MOVWF PORTB
3. BRA SUB_1
Fetch 1
Execute 1
Fetch 2
Execute 2
Fetch 3
Execute 3
Fetch 4
4. BSF
PORTA, BIT3 (Forced NOP)
Flush (NOP)
Fetch SUB_1 Execute SUB_1
5. Instruction @ address SUB_1
Note:
All instructions are single cycle, except for any program branches. These take two cycles since the fetch
instruction is “flushed” from the pipeline while the new instruction is being fetched and then executed.
© 2008 Microchip Technology Inc.
DS39760D-page 57
PIC18F2450/4450
The CALL and GOTO instructions have the absolute
program memory address embedded into the
instruction. Since instructions are always stored on word
boundaries, the data contained in the instruction is a
word address. The word address is written to PC<20:1>,
which accesses the desired byte address in program
memory. Instruction #2 in Figure 5-4 shows how the
instruction, GOTO 0006h, is encoded in the program
memory. Program branch instructions, which encode a
relative address offset, operate in the same manner. The
offset value stored in a branch instruction represents the
number of single-word instructions that the PC will be
offset by. Section 19.0 “Instruction Set Summary”
provides further details of the instruction set.
5.2.3
INSTRUCTIONS IN PROGRAM
MEMORY
The program memory is addressed in bytes.
Instructions are stored as two bytes or four bytes in
program memory. The Least Significant Byte of an
instruction word is always stored in a program memory
location with an even address (LSb = 0). To maintain
alignment with instruction boundaries, the PC
increments in steps of 2 and the LSb will always read
‘0’ (see Section 5.1.1 “Program Counter”).
Figure 5-4 shows an example of how instruction words
are stored in the program memory.
FIGURE 5-4:
INSTRUCTIONS IN PROGRAM MEMORY
Word Address
LSB = 1
LSB = 0
↓
Program Memory
Byte Locations →
000000h
000002h
000004h
000006h
000008h
00000Ah
00000Ch
00000Eh
000010h
000012h
000014h
Instruction 1:
Instruction 2:
MOVLW
GOTO
055h
0006h
0Fh
EFh
F0h
C1h
F4h
55h
03h
00h
23h
56h
Instruction 3:
MOVFF
123h, 456h
used by the instruction sequence. If the first word is
skipped for some reason and the second word is
executed by itself, a NOP is executed instead. This is
necessary for cases when the two-word instruction is
preceded by a conditional instruction that changes the
PC. Example 5-4 shows how this works.
5.2.4
TWO-WORD INSTRUCTIONS
The standard PIC18 instruction set has four two-word
instructions: CALL, MOVFF, GOTO and LSFR. In all
cases, the second word of the instructions always has
‘1111’ as its four Most Significant bits; the other 12 bits
are literal data, usually a data memory address.
Note:
See Section 5.5 “Program Memory and
the Extended Instruction Set” for
information on two-word instruction in the
extended instruction set.
The use of ‘1111’ in the 4 MSbs of an instruction
specifies a special form of NOP. If the instruction is
executed in proper sequence, immediately after the
first word, the data in the second word is accessed and
EXAMPLE 5-4:
CASE 1:
TWO-WORD INSTRUCTIONS
Object Code
Source Code
0110 0110 0000 0000 TSTFSZ
REG1
REG1, REG2 ; No, skip this word
; Execute this word as a NOP
; continue code
; is RAM location 0?
1100 0001 0010 0011
1111 0100 0101 0110
0010 0100 0000 0000
CASE 2:
MOVFF
ADDWF
REG3
Object Code
Source Code
TSTFSZ
0110 0110 0000 0000
1100 0001 0010 0011
1111 0100 0101 0110
0010 0100 0000 0000
REG1
; is RAM location 0?
MOVFF
REG1, REG2 ; Yes, execute this word
; 2nd word of instruction
ADDWF
REG3
; continue code
DS39760D-page 58
© 2008 Microchip Technology Inc.
PIC18F2450/4450
5.3.2
BANK SELECT REGISTER (BSR)
5.3
Data Memory Organization
Large areas of data memory require an efficient
addressing scheme to make rapid access to any
address possible. Ideally, this means that an entire
address does not need to be provided for each read or
write operation. For PIC18 devices, this is
accomplished with a RAM banking scheme. This
divides the memory space into 16 contiguous banks of
256 bytes. Depending on the instruction, each location
can be addressed directly by its full 12-bit address, or
an 8-bit low-order address and a 4-bit Bank Pointer.
Note:
The operation of some aspects of data
memory are changed when the PIC18
extended instruction set is enabled. See
Section 5.6 “Data Memory and the
Extended Instruction Set” for more
information.
The data memory in PIC18 devices is implemented as
static RAM. Each register in the data memory has a
12-bit address, allowing up to 4096 bytes of data
memory. The memory space is divided into as many as
16 banks that contain 256 bytes each. PIC18F2450/
4450 devices implement three complete banks, for a
total of 768 bytes. Figure 5-5 shows the data memory
organization for the devices.
Most instructions in the PIC18 instruction set make use
of the Bank Pointer, known as the Bank Select Register
(BSR). This SFR holds the 4 Most Significant bits of a
location’s address; the instruction itself includes the
8 Least Significant bits. Only the four lower bits of the
BSR are implemented (BSR3:BSR0). The upper four
bits are unused; they will always read ‘0’ and cannot be
written to. The BSR can be loaded directly by using the
MOVLBinstruction.
The data memory contains Special Function Registers
(SFRs) and General Purpose Registers (GPRs). The
SFRs are used for control and status of the controller
and peripheral functions, while GPRs are used for data
storage and scratchpad operations in the user’s
application. Any read of an unimplemented location will
read as ‘0’s.
The value of the BSR indicates the bank in data
memory. The eight bits in the instruction show the loca-
tion in the bank and can be thought of as an offset from
the bank’s lower boundary. The relationship between
the BSR’s value and the bank division in data memory
is shown in Figure 5-6.
The instruction set and architecture allow operations
across all banks. The entire data memory may be
accessed by Direct, Indirect or Indexed Addressing
modes. Addressing modes are discussed later in this
subsection.
Since up to 16 registers may share the same low-order
address, the user must always be careful to ensure that
the proper bank is selected before performing a data
read or write. For example, writing what should be
program data to an 8-bit address of F9h, while the BSR
is 0Fh, will end up resetting the program counter.
To ensure that commonly used registers (SFRs and
select GPRs) can be accessed in a single cycle, PIC18
devices implement an Access Bank. This is a 256-byte
memory space that provides fast access to SFRs and
the lower portion of GPR Bank 0 without using the
While any bank can be selected, only those banks that
are actually implemented can be read or written to.
Writes to unimplemented banks are ignored, while
reads from unimplemented banks will return ‘0’s. Even
so, the STATUS register will still be affected as if the
operation was successful. The data memory map in
Figure 5-6 indicates which banks are implemented.
BSR. Section 5.3.3 “Access Bank” provides
detailed description of the Access RAM.
a
5.3.1
USB RAM
Bank 4 of the data memory is actually mapped to
special dual port RAM. When the USB module is
disabled, the GPRs in these banks are used like any
other GPR in the data memory space.
In the core PIC18 instruction set, only the MOVFF
instruction fully specifies the 12-bit address of the
source and target registers. This instruction ignores the
BSR completely when it executes. All other instructions
include only the low-order address as an operand and
must use either the BSR or the Access Bank to locate
their target registers.
When the USB module is enabled, the memory in this
bank is allocated as buffer RAM for USB operation.
This area is shared between the microcontroller core
and the USB Serial Interface Engine (SIE) and is used
to transfer data directly between the two.
It is theoretically possible to use this area of USB RAM
that is not allocated as USB buffers for normal scratch-
pad memory or other variable storage. In practice, the
dynamic nature of buffer allocation makes this risky at
best. Bank 4 is also used for USB buffer management
when the module is enabled and should not be used for
any other purposes during that time.
Additional information on USB RAM and buffer
operation is provided in Section 14.0 “Universal
Serial Bus (USB)”.
© 2008 Microchip Technology Inc.
DS39760D-page 59
PIC18F2450/4450
FIGURE 5-5:
DATA MEMORY MAP FOR PIC18F2450/4450 DEVICES
When a = 0:
The BSR is ignored and the
BSR<3:0>
Data Memory Map
Access Bank is used.
000h
05Fh
060h
0FFh
100h
00h
Access RAM
GPR
= 0000
= 0001
= 0010
The first 96 bytes are
general purpose RAM
(from Bank 0).
Bank 0
FFh
00h
GPR
The remaining 160 bytes are
Special Function Registers
(from Bank 15).
Bank 1
Bank 2
1FFh
200h
FFh
00h
Unused
Read as 00h
When a = 1:
FFh
00h
2FFh
300h
The BSR specifies the bank
used by the instruction.
= 0011
Unused
Read as 00h
Bank 3
Bank 4
Bank 5
3FFh
400h
FFh
00h
= 0100
= 0101
GPR(1)
4FFh
800h
FFh
00h
Access Bank
00h
Access RAM Low
5Fh
60h
Access RAM High
(SFRs)
FFh
to
Unused
Read as 00h
= 1110
Bank 14
EFFh
F00h
F5Fh
F60h
FFFh
FFh
00h
Unused
SFR
= 1111
Bank 15
FFh
Note 1: This bank also serve as RAM buffer for USB operation. See Section 5.3.1 “USB RAM” for more
information.
DS39760D-page 60
© 2008 Microchip Technology Inc.
PIC18F2450/4450
FIGURE 5-6:
USE OF THE BANK SELECT REGISTER (DIRECT ADDRESSING)
Data Memory
(2)
(1)
From Opcode
BSR
000h
100h
7
0
7
0
00h
Bank 0
Bank 1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
1
1
FFh
00h
(2)
Bank Select
FFh
00h
200h
300h
Bank 2
FFh
00h
Bank 3
through
Bank 13
FFh
00h
E00h
Bank 14
Bank 15
FFh
00h
F00h
FFFh
FFh
Note 1: The Access RAM bit of the instruction can be used to force an override of the selected bank (BSR<3:0>) to
the registers of the Access Bank.
2: The MOVFF instruction embeds the entire 12-bit address in the instruction.
however, the instruction is forced to use the Access
Bank address map; the current value of the BSR is
ignored entirely.
5.3.3
ACCESS BANK
While the use of the BSR, with an embedded 8-bit
address, allows users to address the entire range of
data memory, it also means that the user must always
ensure that the correct bank is selected. Otherwise,
data may be read from or written to the wrong location.
This can be disastrous if a GPR is the intended target
of an operation but an SFR is written to instead.
Verifying and/or changing the BSR for each read or
write to data memory can become very inefficient.
Using this “forced” addressing allows the instruction to
operate on a data address in a single cycle without
updating the BSR first. For 8-bit addresses of 60h and
above, this means that users can evaluate and operate
on SFRs more efficiently. The Access RAM below 60h
is a good place for data values that the user might need
to access rapidly, such as immediate computational
results or common program variables. Access RAM
also allows for faster and more code efficient context
saving and switching of variables.
To streamline access for the most commonly used data
memory locations, the data memory is configured with
an Access Bank, which allows users to access a
mapped block of memory without specifying a BSR.
The Access Bank consists of the first 96 bytes of
memory (00h-5Fh) in Bank 0 and the last 160 bytes of
memory (60h-FFh) in Block 15. The lower half is known
as the “Access RAM” and is composed of GPRs. The
upper half is where the device’s SFRs are mapped.
These two areas are mapped contiguously in the
Access Bank and can be addressed in a linear fashion
by an 8-bit address (Figure 5-5).
The mapping of the Access Bank is slightly different
when the extended instruction set is enabled (XINST
Configuration bit = 1). This is discussed in more detail
in Section 5.6.3 “Mapping the Access Bank in
Indexed Literal Offset Mode”.
5.3.4
GENERAL PURPOSE
REGISTER FILE
PIC18 devices may have banked memory in the GPR
area. This is data RAM which is available for use by all
instructions. GPRs start at the bottom of Bank 0
(address 000h) and grow upwards towards the bottom of
the SFR area. GPRs are not initialized by a Power-on
Reset and are unchanged on all other Resets.
The Access Bank is used by core PIC18 instructions
that include the Access RAM bit (the ‘a’ parameter in
the instruction). When ‘a’ is equal to ‘1’, the instruction
uses the BSR and the 8-bit address included in the
opcode for the data memory address. When ‘a’ is ‘0’,
© 2008 Microchip Technology Inc.
DS39760D-page 61
PIC18F2450/4450
peripheral functions. The Reset and interrupt registers
are described in their respective chapters, while the
ALU’s STATUS register is described later in this
section. Registers related to the operation of a
peripheral feature are described in the chapter for that
peripheral.
5.3.5
SPECIAL FUNCTION REGISTERS
The Special Function Registers (SFRs) are registers
used by the CPU and peripheral modules for controlling
the desired operation of the device. These registers are
implemented as static RAM in the data memory space.
SFRs start at the top of data memory and extend
downward to occupy the top segment of Bank 15, from
F60h to FFFh. A list of these registers is given in
Table 5-1 and Table 5-2.
The SFRs are typically distributed among the
peripherals whose functions they control. Unused SFR
locations are unimplemented and read as ‘0’s.
The SFRs can be classified into two sets: those
associated with the “core” device functionality (ALU,
Resets and interrupts) and those related to the
TABLE 5-1:
SPECIAL FUNCTION REGISTER MAP FOR PIC18F2450/4450 DEVICES
Address
Name
Address
Name
Address
Name
Address
Name
Address
Name
(1)
FFFh
FFEh
FFDh
TOSU
TOSH
TOSL
FDFh
INDF2
FBFh
FBEh
CCPR1H
CCPR1L
F9Fh
F9Eh
F9Dh
F9Ch
F9Bh
F9Ah
F99h
F98h
F97h
F96h
F95h
F94h
F93h
F92h
F91h
F90h
F8Fh
F8Eh
F8Dh
F8Ch
F8Bh
F8Ah
F89h
F88h
F87h
F86h
F85h
F84h
IPR1
PIR1
PIE1
F7Fh
F7Eh
F7Dh
F7Ch
F7Bh
F7Ah
F79h
F78h
F77h
F76h
F75h
F74h
F73h
F72h
F71h
F70h
F6Fh
F6Eh
F6Dh
F6Ch
F6Bh
F6Ah
F69h
F68h
F67h
F66h
F65h
F64h
F63h
F62h
F61h
F60h
UEP15
UEP14
UEP13
UEP12
UEP11
UEP10
UEP9
UEP8
UEP7
UEP6
UEP5
UEP4
UEP3
UEP2
UEP1
UEP0
UCFG
UADDR
UCON
USTAT
UEIE
(1)
(1)
FDEh POSTINC2
FDDh POSTDEC2
FBDh CCP1CON
(1)
(2)
(2)
FFCh
FFBh
FFAh
FF9h
STKPTR
PCLATU
PCLATH
PCL
FDCh PREINC2
FBCh
FBBh
FBAh
FB9h
—
—
—
—
—
(1)
(2)
(2)
(2)
(2)
FDBh PLUSW2
—
(2)
FDAh
FD9h
FD8h
FD7h
FD6h
FD5h
FD4h
FD3h
FSR2H
FSR2L
—
(2)
—
(2)
FF8h TBLPTRU
FF7h TBLPTRH
STATUS
TMR0H
TMR0L
T0CON
FB8h BAUDCON
—
(2)
(2)
FB7h
FB6h
FB5h
FB4h
FB3h
FB2h
FB1h
FB0h
FAFh
FAEh
FADh
FACh
FABh
FAAh
FA9h
FA8h
—
—
—
—
—
—
—
—
(2)
(2)
(2)
(2)
(2)
(2)
(3)
FF6h
FF5h
FF4h
FF3h
FF2h
FF1h
FF0h
FEFh
TBLPTRL
TABLAT
PRODH
PRODL
TRISE
TRISD
(3)
(2)
—
TRISC
TRISB
TRISA
OSCCON
INTCON
INTCON2
INTCON3
FD2h HLVDCON
FD1h WDTCON
(2)
—
(2)
FD0h
FCFh
FCEh
FCDh
FCCh
FCBh
FCAh
FC9h
FC8h
FC7h
FC6h
FC5h
FC4h
FC3h
FC2h
FC1h
FC0h
RCON
TMR1H
TMR1L
T1CON
TMR2
SPBRGH
SPBRG
RCREG
TXREG
TXSTA
—
(1)
(2)
INDF0
—
(1)
(1)
(2)
FEEh POSTINC0
—
(3)
FEDh POSTDEC0
LATE
(1)
(3)
FECh PREINC0
LATD
(1)
FEBh PLUSW0
PR2
RCSTA
LATC
LATB
LATA
(2)
FEAh
FE9h
FE8h
FE7h
FSR0H
FSR0L
WREG
T2CON
—
UEIR
(2)
(2)
—
—
UIE
(2)
(2)
(2)
—
—
—
UIR
(1)
(2)
(1)
(2)
INDF1
—
FA7h EECON2
—
UFRMH
UFRML
(1)
(1)
(2)
(2)
FE6h POSTINC1
—
FA6h
FA5h
FA4h
FA3h
FA2h
FA1h
FA0h
EECON1
—
(2)
(2)
(2)
(2)
(2)
(2)
FE5h POSTDEC1
—
—
—
—
—
—
(1)
(2)
FE4h PREINC1
ADRESH
ADRESL
ADCON0
ADCON1
ADCON2
PORTE
—
(1)
(3)
(2)
FE3h PLUSW1
F83h PORTD
—
(2)
FE2h
FE1h
FE0h
FSR1H
FSR1L
BSR
IPR2
PIR2
PIE2
F82h
F81h
F80h
PORTC
PORTB
PORTA
—
(2)
—
(2)
—
Note 1: Not a physical register.
2: Unimplemented registers are read as ‘0’.
3: These registers are implemented only on 40/44-pin devices.
DS39760D-page 62
© 2008 Microchip Technology Inc.
PIC18F2450/4450
TABLE 5-2:
File Name
TOSU
REGISTER FILE SUMMARY (PIC18F2450/4450)
Value on
POR, BOR on Page:
Details
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
—
—
—
Top-of-Stack Upper Byte (TOS<20:16>)
---0 0000 49, 54
0000 0000 49, 54
0000 0000 49, 54
00-0 0000 49, 55
---0 0000 49, 54
0000 0000 49, 54
0000 0000 49, 54
--00 0000 49, 76
0000 0000 49, 76
0000 0000 49, 76
0000 0000 49, 76
xxxx xxxx 49, 83
xxxx xxxx 49, 83
0000 000x 49, 87
1111 -1-1 49, 88
11-0 0-00 49, 89
TOSH
Top-of-Stack High Byte (TOS<15:8>)
Top-of-Stack Low Byte (TOS<7:0>)
TOSL
STKPTR
PCLATU
PCLATH
PCL
STKFUL
—
STKUNF
—
—
—
SP4
SP3
SP2
SP1
SP0
Holding Register for PC<20:16>
Holding Register for PC<15:8>
PC Low Byte (PC<7:0>)
TBLPTRU
TBLPTRH
TBLPTRL
TABLAT
PRODH
PRODL
INTCON
INTCON2
INTCON3
INDF0
—
—
bit 21(1)
Program Memory Table Pointer Upper Byte (TBLPTR<20:16>)
Program Memory Table Pointer High Byte (TBLPTR<15:8>)
Program Memory Table Pointer Low Byte (TBLPTR<7:0>)
Program Memory Table Latch
Product Register High Byte
Product Register Low Byte
GIE/GIEH
RBPU
PEIE/GIEL
INTEDG0
INT1IP
TMR0IE
INTEDG1
—
INT0IE
INTEDG2
INT2IE
RBIE
—
TMR0IF
TMR0IP
—
INT0IF
—
RBIF
RBIP
INT2IP
INT1IE
INT2IF
INT1IF
Uses contents of FSR0 to address data memory – value of FSR0 not changed (not a physical register)
Uses contents of FSR0 to address data memory – value of FSR0 post-incremented (not a physical register)
N/A
N/A
N/A
N/A
N/A
49, 68
49, 69
49, 69
49, 69
49, 69
POSTINC0
POSTDEC0 Uses contents of FSR0 to address data memory – value of FSR0 post-decremented (not a physical register)
PREINC0
PLUSW0
Uses contents of FSR0 to address data memory – value of FSR0 pre-incremented (not a physical register)
Uses contents of FSR0 to address data memory – value of FSR0 pre-incremented (not a physical register) –
value of FSR0 offset by W
FSR0H
FSR0L
—
—
—
—
Indirect Data Memory Address Pointer 0 High Byte
---- 0000 49, 68
xxxx xxxx 49, 68
Indirect Data Memory Address Pointer 0 Low Byte
Working Register
WREG
xxxx xxxx
N/A
49,
INDF1
Uses contents of FSR1 to address data memory – value of FSR1 not changed (not a physical register)
Uses contents of FSR1 to address data memory – value of FSR1 post-incremented (not a physical register)
49, 68
49, 69
49, 69
49, 69
49, 69
POSTINC1
N/A
POSTDEC1 Uses contents of FSR1 to address data memory – value of FSR1 post-decremented (not a physical register)
N/A
PREINC1
PLUSW1
Uses contents of FSR1 to address data memory – value of FSR1 pre-incremented (not a physical register)
N/A
Uses contents of FSR1 to address data memory – value of FSR1 pre-incremented (not a physical register) –
value of FSR1 offset by W
N/A
FSR1H
FSR1L
BSR
—
—
—
—
Indirect Data Memory Address Pointer 1 High Byte
---- 0000 49, 68
xxxx xxxx 49, 68
---- 0000 49, 59
Indirect Data Memory Address Pointer 1 Low Byte
—
—
—
—
Bank Select Register
INDF2
Uses contents of FSR2 to address data memory – value of FSR2 not changed (not a physical register)
Uses contents of FSR2 to address data memory – value of FSR2 post-incremented (not a physical register)
N/A
N/A
N/A
N/A
N/A
50, 68
50, 69
50, 69
50, 69
50, 69
POSTINC2
POSTDEC2 Uses contents of FSR2 to address data memory – value of FSR2 post-decremented (not a physical register)
PREINC2
PLUSW2
Uses contents of FSR2 to address data memory – value of FSR2 pre-incremented (not a physical register)
Uses contents of FSR2 to address data memory – value of FSR2 pre-incremented (not a physical register) –
value of FSR2 offset by W
FSR2H
FSR2L
STATUS
TMR0H
TMR0L
T0CON
—
—
—
—
Indirect Data Memory Address Pointer 2 High Byte
---- 0000 50, 68
xxxx xxxx 50, 68
---x xxxx 50, 66
0000 0000 50, 113
xxxx xxxx 50, 113
1111 1111 50, 111
Indirect Data Memory Address Pointer 2 Low Byte
—
—
—
N
OV
Z
DC
C
Timer0 Register High Byte
Timer0 Register Low Byte
TMR0ON
T08BIT
T0CS
T0SE
PSA
T0PS2
T0PS1
T0PS0
Legend:
Note 1:
x= unknown, u= unchanged, -= unimplemented, q= value depends on condition. Shaded cells are unimplemented, read as ‘0’.
Bit 21 of the TBLPTRU allows access to the device Configuration bits.
2:
3:
The SBOREN bit is only available when BOREN<1:0> = 01; otherwise, the bit reads as ‘0’.
These registers and/or bits are not implemented on 28-pin devices and are read as ‘0’. Reset values are shown for 40/44-pin devices;
individual unimplemented bits should be interpreted as ‘-’.
4:
5:
6:
RA6 is configured as a port pin based on various primary oscillator modes. When the port pin is disabled, all of the associated bits read ‘0’.
RE3 is only available as a port pin when the MCLRE Configuration bit is clear; otherwise, the bit reads as ‘0’.
RC5 and RC4 are only available as port pins when the USB module is disabled (UCON<3> = 0).
© 2008 Microchip Technology Inc.
DS39760D-page 63
PIC18F2450/4450
TABLE 5-2:
File Name
REGISTER FILE SUMMARY (PIC18F2450/4450) (CONTINUED)
Value on
POR, BOR on Page:
Details
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
OSCCON
IDLEN
—
—
IRVST
—
—
HLVDEN
—
OSTS
HLVDL3
—
—
HLVDL2
—
SCS1
HLVDL1
—
SCS0
HLVDL0
SWDTEN
BOR
0--- q-00 50, 31
0-00 0101 50, 185
HLVDCON
WDTCON
RCON
VDIRMAG
—
—
—
--- ---0
50, 204
IPEN
SBOREN(2)
—
RI
TO
PD
POR
0q-1 11q0 50, 42
xxxx xxxx 50, 120
xxxx xxxx 50, 120
0000 0000 50, 115
0000 0000 50, 122
1111 1111 50, 122
TMR1H
TMR1L
T1CON
TMR2
Timer1 Register High Byte
Timer1 Register Low Byte
RD16
T1RUN
T1CKPS1
T1CKPS0
T1OSCEN
T1SYNC
TMR2ON
TMR1CS
T2CKPS1
TMR1ON
Timer2 Register
PR2
Timer2 Period Register
T2OUTPS3 T2OUTPS2 T2OUTPS1 T2OUTPS0
T2CON
ADRESH
ADRESL
ADCON0
ADCON1
ADCON2
CCPR1H
CCPR1L
CCP1CON
BAUDCON
SPBRGH
SPBRG
RCREG
TXREG
TXSTA
RCSTA
EECON2
EECON1
IPR2
—
T2CKPS0 -000 0000 50, 121
xxxx xxxx 50, 184
A/D Result Register High Byte
A/D Result Register Low Byte
xxxx xxxx 50, 184
—
—
—
—
—
CHS3
VCFG1
ACQT2
CHS2
VCFG0
ACQT1
CHS1
PCFG3
ACQT0
CHS0
PCFG2
ADCS2
GO/DONE
PCFG1
ADON
PCFG0
ADCS0
--00 0000 50, 175
--00 qqqq 50, 176
0-00 0000 50, 177
xxxx xxxx 50, 124
xxxx xxxx 50, 124
--00 0000 50, 123,
01-0 0-00 51, 156,
0000 0000 50, 157
0000 0000 50, 157
0000 0000 50, 165
0000 0000 51, 163
0000 0010 51, 154
0000 000x 51, 155
0000 0000 51, 74
-x-0 x00- 51, 75
1-1- -1-- 51, 95
0-0- -0-- 51, 91
0-0- -0-- 51, 93
-111 -111 51, 94
-000 -000 51, 90
-000 -000 51, 92
---- -111 51, 110
1111 1111 51, 108
11-- -111 51, 106
1111 1111 51, 103
-111 1111 51, 100
---- -xxx 51, 110
xxxx xxxx 51, 108
xx-- -xxx 51, 106
xxxx xxxx 51, 103
-xxx xxxx 51, 100
---- x000 51, 109
xxxx xxxx 51, 108
ADFM
ADCS1
Capture/Compare/PWM Register 1 High Byte
Capture/Compare/PWM Register 1 Low Byte
—
—
DC1B1
—
DC1B0
SCKP
CCP1M3
BRG16
CCP1M2
—
CCP1M1
WUE
CCP1M0
ABDEN
ABDOVF
RCIDL
EUSART Baud Rate Generator Register High Byte
EUSART Baud Rate Generator Register Low Byte
EUSART Receive Register
EUSART Transmit Register
CSRC
SPEN
TX9
RX9
TXEN
SREN
SYNC
CREN
SENDB
ADDEN
BRGH
FERR
TRMT
OERR
TX9D
RX9D
Data Memory Control Register 2 (not a physical register)
—
OSCFIP
OSCFIF
OSCFIE
—
CFGS
—
—
USBIP
USBIF
USBIE
RCIP
RCIF
RCIE
—
FREE
—
WRERR
—
WREN
HLVDIP
HLVDIF
HLVDIE
CCP1IP
CCP1IF
CCP1IE
TRISE2
TRISD2
TRISC2
TRISB2
TRISA2
LATE2
LATD2
LATC2
LATB2
LATA2
WR
—
—
—
PIR2
—
—
—
—
—
PIE2
—
—
—
—
—
IPR1
ADIP
ADIF
ADIE
—
TXIP
TXIF
TXIE
—
—
TMR2IP
TMR2IF
TMR2IE
TRISE1
TRISD1
TRISC1
TRISB1
TRISA1
LATE1
LATD1
LATC1
LATB1
LATA1
RE1(3)
RD1
TMR1IP
TMR1IF
TMR1IE
TRISE0
TRISD0
TRISC0
TRISB0
TRISA0
LATE0
LATD0
LATC0
LATB0
LATA0
RE0(3)
RD0
PIR1
—
—
PIE1
—
—
TRISE(3)
TRISD(3)
TRISC
—
—
TRISD7
TRISC7
TRISB7
—
TRISD6
TRISC6
TRISB6
TRISA6(4)
—
TRISD5
—
TRISD4
—
TRISD3
—
TRISB
TRISB5
TRISA5
—
TRISB4
TRISA4
—
TRISB3
TRISA3
—
TRISA
LATE(3)
LATD(3)
LATC
—
LATD7
LATC7
LATB7
—
LATD6
LATC6
LATB6
LATA6(4)
—
LATD5
—
LATD4
—
LATD3
—
LATB
LATB5
LATA5
—
LATB4
LATA4
—
LATB3
LATA3
RE3(5)
RD3
LATA
PORTE
PORTD(3)
—
RE2(3)
RD7
RD6
RD5
RD4
RD2
Legend:
Note 1:
x= unknown, u= unchanged, -= unimplemented, q= value depends on condition. Shaded cells are unimplemented, read as ‘0’.
Bit 21 of the TBLPTRU allows access to the device Configuration bits.
2:
3:
The SBOREN bit is only available when BOREN<1:0> = 01; otherwise, the bit reads as ‘0’.
These registers and/or bits are not implemented on 28-pin devices and are read as ‘0’. Reset values are shown for 40/44-pin devices;
individual unimplemented bits should be interpreted as ‘-’.
4:
5:
6:
RA6 is configured as a port pin based on various primary oscillator modes. When the port pin is disabled, all of the associated bits read ‘0’.
RE3 is only available as a port pin when the MCLRE Configuration bit is clear; otherwise, the bit reads as ‘0’.
RC5 and RC4 are only available as port pins when the USB module is disabled (UCON<3> = 0).
DS39760D-page 64
© 2008 Microchip Technology Inc.
PIC18F2450/4450
TABLE 5-2:
REGISTER FILE SUMMARY (PIC18F2450/4450) (CONTINUED)
Value on
POR, BOR on Page:
Details
File Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PORTC
PORTB
PORTA
UEP15
UEP14
UEP13
UEP12
UEP11
UEP10
UEP9
UEP8
UEP7
UEP6
UEP5
UEP4
UEP3
UEP2
UEP1
UEP0
UCFG
UADDR
UCON
USTAT
UEIE
RC7
RB7
—
RC6
RB6
RA6(4)
—
RC5(6)
RB5
RA5
—
RC4(6)
RB4
—
RC2
RB2
RA2
RC1
RC0
RB0
RA0
xxxx -xxx 51, 106
xxxx xxxx 51, 100
-x0x 0000 51, 100
RB3
RA3
RB1
RA4
RA1
—
EPHSHK
EPHSHK
EPHSHK
EPHSHK
EPHSHK
EPHSHK
EPHSHK
EPHSHK
EPHSHK
EPHSHK
EPHSHK
EPHSHK
EPHSHK
EPHSHK
EPHSHK
EPHSHK
UPUEN
ADDR4
PKTDIS
ENDP1
BTOEE
BTOEF
IDLEIE
EPCONDIS EPOUTEN
EPCONDIS EPOUTEN
EPCONDIS EPOUTEN
EPCONDIS EPOUTEN
EPCONDIS EPOUTEN
EPCONDIS EPOUTEN
EPCONDIS EPOUTEN
EPCONDIS EPOUTEN
EPCONDIS EPOUTEN
EPCONDIS EPOUTEN
EPCONDIS EPOUTEN
EPCONDIS EPOUTEN
EPCONDIS EPOUTEN
EPCONDIS EPOUTEN
EPCONDIS EPOUTEN
EPCONDIS EPOUTEN
EPINEN
EPINEN
EPINEN
EPINEN
EPINEN
EPINEN
EPINEN
EPINEN
EPINEN
EPINEN
EPINEN
EPINEN
EPINEN
EPINEN
EPINEN
EPINEN
PPB1
EPSTALL ---0 0000 51, 135
EPSTALL ---0 0000 51, 135
EPSTALL ---0 0000 51, 135
EPSTALL ---0 0000 51, 135
EPSTALL ---0 0000 51, 135
EPSTALL ---0 0000 51, 135
EPSTALL ---0 0000 52, 135
EPSTALL ---0 0000 52, 135
EPSTALL ---0 0000 52, 135
EPSTALL ---0 0000 52, 135
EPSTALL ---0 0000 52, 135
EPSTALL ---0 0000 52, 135
EPSTALL ---0 0000 52, 135
EPSTALL ---0 0000 52, 135
EPSTALL ---0 0000 52, 135
EPSTALL ---0 0000 52, 135
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
UTEYE
—
UOEMON
ADDR6
PPBRST
ENDP3
—
—
UTRDIS
ADDR3
USBEN
ENDP0
DFN8EE
DFN8EF
TRNIE
TRNIF
—
FSEN
ADDR2
RESUME
DIR
PPB0
ADDR0
—
00-0 0000 52, 132
-000 0000 52, 136
-0x0 000- 52, 130
-xxx xxx- 52, 134
0--0 0000 52, 148
0--0 0000 52, 147
-000 0000 52, 146
-000 0000 52, 144
---- -xxx 52, 136
xxxx xxxx 52, 136
ADDR5
SE0
ENDP2
—
ADDR1
SUSPND
PPBI
—
—
—
BTSEE
BTSEF
—
CRC16EE
CRC16EF
ACTVIE
ACTVIF
FRM10
FRM2
CRC5EE
CRC5EF
UERRIE
UERRIF
FRM9
PIDEE
PIDEF
URSTIE
URSTIF
FRM8
FRM0
UEIR
—
—
UIE
SOFIE
SOFIF
—
STALLIE
STALLIF
—
UIR
—
IDLEIF
UFRMH
UFRML
—
—
FRM7
FRM6
FRM5
FRM4
FRM3
FRM1
Legend:
Note 1:
x= unknown, u= unchanged, -= unimplemented, q= value depends on condition. Shaded cells are unimplemented, read as ‘0’.
Bit 21 of the TBLPTRU allows access to the device Configuration bits.
2:
3:
The SBOREN bit is only available when BOREN<1:0> = 01; otherwise, the bit reads as ‘0’.
These registers and/or bits are not implemented on 28-pin devices and are read as ‘0’. Reset values are shown for 40/44-pin devices;
individual unimplemented bits should be interpreted as ‘-’.
4:
5:
6:
RA6 is configured as a port pin based on various primary oscillator modes. When the port pin is disabled, all of the associated bits read ‘0’.
RE3 is only available as a port pin when the MCLRE Configuration bit is clear; otherwise, the bit reads as ‘0’.
RC5 and RC4 are only available as port pins when the USB module is disabled (UCON<3> = 0).
© 2008 Microchip Technology Inc.
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PIC18F2450/4450
It is recommended that only BCF, BSF, SWAPF, MOVFF
and MOVWFinstructions are used to alter the STATUS
register because these instructions do not affect the Z,
C, DC, OV or N bits in the STATUS register.
5.3.6
STATUS REGISTER
The STATUS register, shown in Register 5-2, contains
the arithmetic status of the ALU. As with any other SFR,
it can be the operand for any instruction.
For other instructions that do not affect Status bits, see
the instruction set summaries in Table 19-2 and
Table 19-3.
If the STATUS register is the destination for an instruction
that affects the Z, DC, C, OV or N bits, the results of the
instruction are not written; instead, the STATUS register
is updated according to the instruction performed.
Therefore, the result of an instruction with the STATUS
register as its destination may be different than intended.
As an example, CLRF STATUSwill set the Z bit and leave
the remaining Status bits unchanged (‘000u u1uu’).
Note:
The C and DC bits operate as the Borrow
and Digit Borrow bits, respectively, in
subtraction.
REGISTER 5-2:
STATUS REGISTER
U-0
—
U-0
U-0
—
R/W-x
N
R/W-x
OV
R/W-x
Z
R/W-x
DC(1)
R/W-x
C(2)
—
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7-5
bit 4
Unimplemented: Read as ‘0’
N: Negative bit
This bit is used for signed arithmetic (2’s complement). It indicates whether the result was
negative (ALU MSB = 1).
1= Result was negative
0= Result was positive
bit 3
OV: Overflow bit
This bit is used for signed arithmetic (2’s complement). It indicates an overflow of the 7-bit
magnitude which causes the sign bit (bit 7 of the result) to change state.
1= Overflow occurred for signed arithmetic (in this arithmetic operation)
0= No overflow occurred
bit 2
bit 1
Z: Zero bit
1= The result of an arithmetic or logic operation is zero
0= The result of an arithmetic or logic operation is not zero
DC: Digit Carry/Borrow bit(1)
For ADDWF, ADDLW, SUBLWand SUBWFinstructions:
1= A carry-out from the 4th low-order bit of the result occurred
0= No carry-out from the 4th low-order bit of the result
bit 0
C: Carry/Borrow bit(2)
For ADDWF, ADDLW, SUBLWand SUBWFinstructions:
1= A carry-out from the Most Significant bit of the result occurred
0= No carry-out from the Most Significant bit of the result occurred
Note 1: For borrow, the polarity is reversed. A subtraction is executed by adding the 2’s complement of the second
operand. For rotate (RRF, RLF) instructions, this bit is loaded with either bit 4 or bit 3 of the source register.
2: For borrow, the polarity is reversed. A subtraction is executed by adding the 2’s complement of the second
operand. For rotate (RRF, RLF) instructions, this bit is loaded with either the high or low-order bit of the
source register.
DS39760D-page 66
© 2008 Microchip Technology Inc.
PIC18F2450/4450
Purpose Register File”) or a location in the Access
Bank (Section 5.3.3 “Access Bank”) as the data
source for the instruction.
5.4
Data Addressing Modes
Note:
The execution of some instructions in the
core PIC18 instruction set are changed
when the PIC18 extended instruction
set is enabled. See Section 5.6 “Data
Memory and the Extended Instruction
Set” for more information.
The Access RAM bit ‘a’ determines how the address is
interpreted. When ‘a’ is ‘1’, the contents of the BSR
(Section 5.3.2 “Bank Select Register (BSR)”) are
used with the address to determine the complete 12-bit
address of the register. When ‘a’ is ‘0’, the address is
interpreted as being a register in the Access Bank.
Addressing that uses the Access RAM is sometimes
also known as Direct Forced Addressing mode.
While the program memory can be addressed in only
one way – through the program counter – information
in the data memory space can be addressed in several
ways. For most instructions, the addressing mode is
fixed. Other instructions may use up to three modes,
depending on which operands are used and whether or
not the extended instruction set is enabled.
A few instructions, such as MOVFF, include the entire
12-bit address (either source or destination) in their
opcodes. In these cases, the BSR is ignored entirely.
The destination of the operation’s results is determined
by the destination bit ‘d’. When ‘d’ is ‘1’, the results are
stored back in the source register, overwriting its origi-
nal contents. When ‘d’ is ‘0’, the results are stored in
the W register. Instructions without the ‘d’ argument
have a destination that is implicit in the instruction; their
destination is either the target register being operated
on or the W register.
The addressing modes are:
• Inherent
• Literal
• Direct
• Indirect
An additional addressing mode, Indexed Literal Offset,
is available when the extended instruction set is
enabled (XINST Configuration bit = 1). Its operation is
discussed in greater detail in Section 5.6.1 “Indexed
Addressing with Literal Offset”.
5.4.3
INDIRECT ADDRESSING
Indirect Addressing allows the user to access a location
in data memory without giving a fixed address in the
instruction. This is done by using File Select Registers
(FSRs) as pointers to the locations to be read or written
to. Since the FSRs are themselves located in RAM as
Special Function Registers, they can also be directly
manipulated under program control. This makes FSRs
very useful in implementing data structures, such as
tables and arrays in data memory.
5.4.1
INHERENT AND LITERAL
ADDRESSING
Many PIC18 control instructions do not need any
argument at all; they either perform an operation that
globally affects the device or they operate implicitly on
one register. This addressing mode is known as
Inherent Addressing. Examples include SLEEP, RESET
and DAW.
The registers for Indirect Addressing are also
implemented with Indirect File Operands (INDFs) that
permit automatic manipulation of the pointer value with
auto-incrementing, auto-decrementing or offsetting
with another value. This allows for efficient code, using
loops, such as the example of clearing an entire RAM
bank in Example 5-5.
Other instructions work in a similar way but require an
additional explicit argument in the opcode. This is
known as Literal Addressing mode because they
require some literal value as an argument. Examples
include ADDLWand MOVLW, which respectively, add or
move a literal value to the W register. Other examples
include CALL and GOTO, which include a 20-bit
program memory address.
EXAMPLE 5-5:
HOW TO CLEAR RAM
(BANK 1) USING
INDIRECT ADDRESSING
5.4.2
DIRECT ADDRESSING
LFSR
CLRF
FSR0, 100h
POSTINC0
;
Direct Addressing mode specifies all or part of the
source and/or destination address of the operation
within the opcode itself. The options are specified by
the arguments accompanying the instruction.
NEXT
; Clear INDF
; register then
; inc pointer
; All done with
; Bank1?
BTFSS FSR0H, 1
In the core PIC18 instruction set, bit-oriented and byte-
oriented instructions use some version of Direct
Addressing by default. All of these instructions include
some 8-bit literal address as their Least Significant
Byte. This address specifies either a register address in
one of the banks of data RAM (Section 5.3.4 “General
BRA
CONTINUE
NEXT
; NO, clear next
; YES, continue
© 2008 Microchip Technology Inc.
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PIC18F2450/4450
mapped in the SFR space but are not physically
implemented. Reading or writing to a particular INDF
register actually accesses its corresponding FSR
register pair. A read from INDF1, for example, reads
the data at the address indicated by FSR1H:FSR1L.
Instructions that use the INDF registers as operands
actually use the contents of their corresponding FSR as
a pointer to the instruction’s target. The INDF operand
is just a convenient way of using the pointer.
5.4.3.1
FSR Registers and the
INDF Operand
At the core of Indirect Addressing are three sets of
registers: FSR0, FSR1 and FSR2. Each represents a
pair of 8-bit registers: FSRnH and FSRnL. The four
upper bits of the FSRnH register are not used, so each
FSR pair holds a 12-bit value. This represents a value
that can address the entire range of the data memory
in a linear fashion. The FSR register pairs, then, serve
as pointers to data memory locations.
Because Indirect Addressing uses a full 12-bit address,
data RAM banking is not necessary. Thus, the current
contents of the BSR and the Access RAM bit have no
effect on determining the target address.
Indirect Addressing is accomplished with a set of
Indirect File Operands, INDF0 through INDF2. These
can be thought of as “virtual” registers; they are
FIGURE 5-7:
INDIRECT ADDRESSING
000h
Using an instruction with one of the
indirect addressing registers as the
operand....
Bank 0
Bank 1
ADDWF, INDF1, 1
100h
200h
300h
Bank 2
FSR1H:FSR1L
...uses the 12-bit address stored in
the FSR pair associated with that
register....
7
0
7
0
x x x x 1 1 1 0
1 1 0 0 1 1 0 0
Bank 3
through
Bank 13
...to determine the data memory
location to be used in that operation.
E00h
In this case, the FSR1 pair contains
ECCh. This means the contents of
location ECCh will be added to that
of the W register and stored back in
ECCh.
Bank 14
Bank 15
F00h
FFFh
Data Memory
DS39760D-page 68
© 2008 Microchip Technology Inc.
PIC18F2450/4450
5.4.3.2
FSR Registers and POSTINC,
5.4.3.3
Operations by FSRs on FSRs
POSTDEC, PREINC and PLUSW
Indirect Addressing operations that target other FSRs
or virtual registers represent special cases. For
example, using an FSR to point to one of the virtual
registers will not result in successful operations. As a
specific case, assume that FSR0H:FSR0L contains
FE7h, the address of INDF1. Attempts to read the
value of INDF1, using INDF0 as an operand, will return
00h. Attempts to write to INDF1, using INDF0 as the
operand, will result in a NOP.
In addition to the INDF operand, each FSR register pair
also has four additional indirect operands. Like INDF,
these are “virtual” registers that cannot be indirectly
read or written to. Accessing these registers actually
accesses the associated FSR register pair, but also
performs a specific action on it stored value. They are:
• POSTDEC: accesses the FSR value, then
automatically decrements it by ‘1’ afterwards
On the other hand, using the virtual registers to write to
an FSR pair may not occur as planned. In these cases,
the value will be written to the FSR pair but without any
incrementing or decrementing. Thus, writing to INDF2
or POSTDEC2 will write the same value to the
FSR2H:FSR2L.
• POSTINC: accesses the FSR value, then
automatically increments it by ‘1’ afterwards
• PREINC: increments the FSR value by ‘1’, then
uses it in the operation
• PLUSW: adds the signed value of the W register
(range of -127 to 128) to that of the FSR and uses
the new value in the operation.
Since the FSRs are physical registers mapped in the
SFR space, they can be manipulated through all direct
operations. Users should proceed cautiously when
working on these registers, particularly if their code
uses Indirect Addressing.
In this context, accessing an INDF register uses the
value in the FSR registers without changing them.
Similarly, accessing a PLUSW register gives the FSR
value offset by that in the W register; neither value is
actually changed in the operation. Accessing the other
virtual registers changes the value of the FSR
registers.
Similarly, operations by Indirect Addressing are
generally permitted on all other SFRs. Users should
exercise the appropriate caution that they do not
inadvertently change settings that might affect the
operation of the device.
Operations on the FSRs with POSTDEC, POSTINC
and PREINC affect the entire register pair; that is,
rollovers of the FSRnL register from FFh to 00h carry
over to the FSRnH register. On the other hand, results
of these operations do not change the value of any
flags in the STATUS register (e.g., Z, N, OV, etc.).
The PLUSW register can be used to implement a form
of Indexed Addressing in the data memory space. By
manipulating the value in the W register, users can
reach addresses that are fixed offsets from pointer
addresses. In some applications, this can be used to
implement some powerful program control structure,
such as software stacks, inside of data memory.
© 2008 Microchip Technology Inc.
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PIC18F2450/4450
When using the extended instruction set, this
addressing mode requires the following:
5.5
Program Memory and the
Extended Instruction Set
• The use of the Access Bank is forced (‘a’ = 0);
and
The operation of program memory is unaffected by the
use of the extended instruction set.
• The file address argument is less than or equal
to 5Fh.
Enabling the extended instruction set adds eight
additional two-word commands to the existing
PIC18 instruction set: ADDFSR, ADDULNK, CALLW,
MOVSF, MOVSS, PUSHL, SUBFSRand SUBULNK.These
instructions are executed as described in
Section 5.2.4 “Two-Word Instructions”.
Under these conditions, the file address of the
instruction is not interpreted as the lower byte of an
address (used with the BSR in Direct Addressing), or
as an 8-bit address in the Access Bank. Instead, the
value is interpreted as an offset value to an Address
Pointer specified by FSR2. The offset and the contents
of FSR2 are added to obtain the target address of the
operation.
5.6
Data Memory and the Extended
Instruction Set
Enabling the PIC18 extended instruction set (XINST
Configuration bit = 1) significantly changes certain
aspects of data memory and its addressing.
Specifically, the use of the Access Bank for many of the
core PIC18 instructions is different. This is due to the
introduction of a new addressing mode for the data
memory space. This mode also alters the behavior of
Indirect Addressing using FSR2 and its associated
operands.
5.6.2
INSTRUCTIONS AFFECTED BY
INDEXED LITERAL OFFSET MODE
Any of the core PIC18 instructions that can use Direct
Addressing are potentially affected by the Indexed
Literal Offset Addressing mode. This includes all byte-
oriented and bit-oriented instructions, or almost one-half
of the standard PIC18 instruction set. Instructions that
only use Inherent or Literal Addressing modes are
unaffected.
What does not change is just as important. The size of
the data memory space is unchanged, as well as its
linear addressing. The SFR map remains the same.
Core PIC18 instructions can still operate in both Direct
and Indirect Addressing mode; inherent and literal
instructions do not change at all. Indirect Addressing
with FSR0 and FSR1 also remains unchanged.
Additionally, byte-oriented and bit-oriented instructions
are not affected if they do not use the Access Bank
(Access RAM bit is ‘1’) or include a file address of 60h
or above. Instructions meeting these criteria will
continue to execute as before. A comparison of the
different possible addressing modes when the
extended instruction set is enabled in shown in
Figure 5-8.
5.6.1
INDEXED ADDRESSING WITH
LITERAL OFFSET
Those who desire to use byte-oriented or bit-oriented
instructions in the Indexed Literal Offset mode should
note the changes to assembler syntax for this mode.
This is described in more detail in Section 19.2.1
“Extended Instruction Syntax”.
Enabling the PIC18 extended instruction set changes
the behavior of Indirect Addressing using the FSR2
register pair and its associated file operands. Under the
proper conditions, instructions that use the Access
Bank – that is, most bit-oriented and byte-oriented
instructions – can invoke a form of Indexed Addressing
using an offset specified in the instruction. This special
addressing mode is known as Indexed Addressing with
Literal Offset or Indexed Literal Offset mode.
DS39760D-page 70
© 2008 Microchip Technology Inc.
PIC18F2450/4450
FIGURE 5-8:
COMPARING ADDRESSING OPTIONS FOR BIT-ORIENTED AND
BYTE-ORIENTED INSTRUCTIONS (EXTENDED INSTRUCTION SET ENABLED)
EXAMPLE INSTRUCTION: ADDWF, f, d, a (Opcode: 0010 01da ffff ffff)
000h
When a = 0 and f ≥ 60h:
The instruction executes in
Direct Forced mode. ‘f’ is inter-
preted as a location in the
Access RAM between 060h
and 0FFh. This is the same as
the SFRs or locations F60h to
0FFh (Bank 15) of data
memory.
060h
080h
Bank 0
100h
00h
60h
Bank 1
through
Bank 14
Valid range
for ‘f’
FFh
F00h
F60h
Access RAM
Locations below 60h are not
available in this addressing
mode.
Bank 15
SFRs
FFFh
Data Memory
When a = 0 and f ≤ 5Fh:
000h
080h
100h
Bank 0
The instruction executes in
Indexed Literal Offset mode. ‘f’
is interpreted as an offset to the
address value in FSR2. The
two are added together to
obtain the address of the target
register for the instruction. The
address can be anywhere in
the data memory space.
001001da ffffffff
Bank 1
through
Bank 14
FSR2H
FSR2L
F00h
F60h
Bank 15
Note that in this mode, the
correct syntax is now:
SFRs
ADDWF [k], d
where ‘k’ is the same as ‘f’.
FFFh
Data Memory
BSR
000h
080h
100h
00000000
When a = 1 (all values of f):
Bank 0
The instruction executes in
Direct mode (also known as
Direct Long mode). ‘f’ is inter-
preted as a location in one of
the 16 banks of the data
memory space. The bank is
designated by the Bank Select
Register (BSR). The address
can be in any implemented
bank in the data memory
space.
001001da ffffffff
Bank 1
through
Bank 14
F00h
F60h
Bank 15
SFRs
FFFh
Data Memory
© 2008 Microchip Technology Inc.
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PIC18F2450/4450
Remapping of the Access Bank applies only to
operations using the Indexed Literal Offset mode.
Operations that use the BSR (Access RAM bit is ‘1’) will
continue to use Direct Addressing as before. Any
indirect or indexed operation that explicitly uses any of
the indirect file operands (including FSR2) will continue
to operate as standard Indirect Addressing. Any
instruction that uses the Access Bank, but includes a
register address of greater than 05Fh, will use Direct
Addressing and the normal Access Bank map.
5.6.3
MAPPING THE ACCESS BANK IN
INDEXED LITERAL OFFSET MODE
The use of Indexed Literal Offset Addressing mode
effectively changes how the lower portion of Access
RAM (00h to 5Fh) is mapped. Rather than containing
just the contents of the bottom half of Bank 0, this mode
maps the contents from Bank 0 and a user-defined
“window” that can be located anywhere in the data
memory space. The value of FSR2 establishes the
lower boundary of the addresses mapped into the
window, while the upper boundary is defined by FSR2
plus 95 (5Fh). Addresses in the Access RAM above
5Fh are mapped as previously described (see
Section 5.3.3 “Access Bank”). An example of Access
Bank remapping in this addressing mode is shown in
Figure 5-9.
5.6.4
BSR IN INDEXED LITERAL
OFFSET MODE
Although the Access Bank is remapped when the
extended instruction set is enabled, the operation of the
BSR remains unchanged. Direct Addressing, using the
BSR to select the data memory bank, operates in the
same manner as previously described.
FIGURE 5-9:
REMAPPING THE ACCESS BANK WITH INDEXED LITERAL
OFFSET ADDRESSING
Example Situation:
000h
ADDWF f, d, a
FSR2H:FSR2L = 120h
Bank 0
Locations in the region
from the FSR2 Pointer
(120h) to the pointer plus
05Fh (17Fh) are mapped
to the bottom of the
Access RAM (000h-05Fh).
100h
120h
17Fh
Window
Bank 1
00h
Bank 1 “Window”
200h
5Fh
60h
Special Function Registers
at F60h through FFFh are
mapped to 60h through
FFh as usual.
Bank 2
through
Bank 14
SFRs
Bank 0 addresses below
5Fh are not available in
this mode. They can still
be addressed by using the
BSR.
FFh
Access Bank
F00h
F60h
Bank 15
SFRs
FFFh
Data Memory
DS39760D-page 72
© 2008 Microchip Technology Inc.
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6.1
Table Reads and Table Writes
6.0
FLASH PROGRAM MEMORY
In order to read and write program memory, there are
two operations that allow the processor to move bytes
between the program memory space and the data RAM:
The Flash program memory is readable, writable and
erasable, during normal operation over the entire VDD
range.
• Table Read (TBLRD)
• Table Write (TBLWT)
A read from program memory is executed on one byte
at a time. A write to program memory is executed on
blocks of 16 bytes at a time. Program memory is
erased in blocks of 64 bytes at a time. A Bulk Erase
operation may not be issued from user code.
The program memory space is 16 bits wide, while the
data RAM space is 8 bits wide. Table reads and table
writes move data between these two memory spaces
through an 8-bit register (TABLAT).
Writing or erasing program memory will cease
instruction fetches until the operation is complete. The
program memory cannot be accessed during the write
or erase, therefore, code cannot execute. An internal
programming timer terminates program memory writes
and erases.
Table read operations retrieve data from program
memory and place it into the data RAM space.
Figure 6-1 shows the operation of a table read with
program memory and data RAM.
Table write operations store data from the data memory
space into holding registers in program memory. The
procedure to write the contents of the holding registers
into program memory is detailed in Section 6.5 “Writing
to Flash Program Memory”. Figure 6-2 shows the
operation of a table write with program memory and data
RAM.
A value written to program memory does not need to be
a valid instruction. Executing a program memory
location that forms an invalid instruction results in a
NOP.
Table operations work with byte entities. A table block
containing data, rather than program instructions, is not
required to be word-aligned. Therefore, a table block can
start and end at any byte address. If a table write is being
used to write executable code into program memory,
program instructions will need to be word-aligned.
FIGURE 6-1:
TABLE READ OPERATION
Instruction: TBLRD*
Program Memory
(1)
Table Pointer
Table Latch (8-bit)
TABLAT
TBLPTRU TBLPTRH TBLPTRL
Program Memory
(TBLPTR)
Note 1: Table Pointer register points to a byte in program memory.
© 2008 Microchip Technology Inc.
DS39760D-page 73
PIC18F2450/4450
FIGURE 6-2:
TABLE WRITE OPERATION
Instruction: TBLWT*
Program Memory
Holding Registers
(1)
Table Pointer
Table Latch (8-bit)
TABLAT
TBLPTRU TBLPTRH TBLPTRL
Program Memory
(TBLPTR)
Note 1: Table Pointer actually points to one of 16 holding registers, the address of which is determined by
TBLPTRL<3:0>. The process for physically writing data to the program memory array is discussed
in Section 6.5 “Writing to Flash Program Memory”.
The FREE bit, when set, will allow a program memory
erase operation. When FREE is set, the erase
operation is initiated on the next WR command. When
FREE is clear, only writes are enabled.
6.2
Control Registers
Several control registers are used in conjunction with
the TBLRDand TBLWTinstructions. These include the:
• EECON1 register
• EECON2 register
• TABLAT register
• TBLPTR registers
The WREN bit, when set, will allow a write operation.
On power-up, the WREN bit is clear. The WRERR bit is
set in hardware when the WREN bit is set and cleared
when the internal programming timer expires and the
write operation is complete.
6.2.1
EECON1 AND EECON2 REGISTERS
Note:
During normal operation, the WRERR is
read as ‘1’. This can indicate that a write
operation was prematurely terminated by
The EECON1 register (Register 6-1) is the control
register for memory accesses. The EECON2 register is
not a physical register; it is used exclusively in the
memory write and erase sequences. Reading
EECON2 will read all ‘0’s.
a
Reset or
a write operation was
attempted improperly.
The WR control bit initiates write operations. The bit
cannot be cleared, only set, in software; it is cleared in
hardware at the completion of the write operation.
The CFGS control bit determines if the access will be
to the Configuration/Calibration registers or to program
memory.
DS39760D-page 74
© 2008 Microchip Technology Inc.
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REGISTER 6-1:
EECON1: MEMORY CONTROL REGISTER 1
U-0
—
R/W-x
CFGS
U-0
—
R/W-0
FREE
R/W-x
WRERR(1)
R/W-0
WREN
R/S-0
WR
U-0
—
bit 7
bit 0
Legend:
S = Settable bit
W = Writable bit
‘1’ = Bit is set
R = Readable bit
-n = Value at POR
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7
bit 6
Unimplemented: Read as ‘0’
CFGS: Flash Program or Configuration Select bit
1= Access Configuration registers
0= Access Flash program
bit 5
bit 4
Unimplemented: Read as ‘0’
FREE: Flash Row Erase Enable bit
1= Erase the program memory row addressed by TBLPTR on the next WR command
(cleared by completion of erase operation)
0= Perform write-only
bit 3
WRERR: Flash Program Error Flag bit(1)
1= A write operation is prematurely terminated (any Reset during self-timed programming in normal
operation or an improper write attempt)
0= The write operation completed
bit 2
bit 1
WREN: Flash Program Write Enable bit
1= Allows write cycles to Flash program
0= Inhibits write cycles to Flash program
WR: Write Control bit
1= Initiates a program memory erase cycle or write cycle
(The operation is self-timed and the bit is cleared by hardware once write is complete.
The WR bit can only be set (not cleared) in software.)
0= Write cycle complete
bit 0
Unimplemented: Read as ‘0’
Note 1: When a WRERR occurs, the CFGS bit is not cleared. This allows tracing of the error condition.
© 2008 Microchip Technology Inc.
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6.2.2
TABLE LATCH REGISTER (TABLAT)
6.2.4
TABLE POINTER BOUNDARIES
The Table Latch (TABLAT) is an 8-bit register mapped
into the SFR space. The Table Latch register is used to
hold 8-bit data during data transfers between program
memory and data RAM.
TBLPTR is used in reads, writes and erases of the
Flash program memory.
When a TBLRDis executed, all 22 bits of the TBLPTR
determine which byte is read from program memory
into TABLAT.
6.2.3
TABLE POINTER REGISTER
(TBLPTR)
When a TBLWTis executed, the four LSbs of the Table
Pointer register (TBLPTR<3:0>) determine which of the
16 program memory holding registers is written to.
When the timed write to program memory begins (via
the WR bit), the 16 MSbs of the TBLPTR
(TBLPTR<21:4>) determine which program memory
block of 16 bytes is written to. For more detail, see
Section 6.5 “Writing to Flash Program Memory”.
The Table Pointer (TBLPTR) register addresses a byte
within the program memory. The TBLPTR is comprised
of three SFR registers: Table Pointer Upper Byte, Table
Pointer High Byte and Table Pointer Low Byte
(TBLPTRU:TBLPTRH:TBLPTRL). These three registers
join to form a 22-bit wide pointer. The low-order 21 bits
allow the device to address up to 2 Mbytes of program
memory space. The 22nd bit allows access to the device
ID, the user ID and the Configuration bits.
When an erase of program memory is executed, the
16 MSbs of the Table Pointer register (TBLPTR<21:6>)
point to the 64-byte block that will be erased. The Least
Significant bits (TBLPTR<5:0>) are ignored.
The Table Pointer, TBLPTR, is used by the TBLRDand
TBLWTinstructions. These instructions can update the
TBLPTR in one of four ways based on the table opera-
tion. These operations are shown in Table 6-1. These
operations on the TBLPTR only affect the low-order
21 bits.
Figure 6-3 describes the relevant boundaries of the
TBLPTR based on Flash program memory operations.
TABLE 6-1:
Example
TABLE POINTER OPERATIONS WITH TBLRD AND TBLWT INSTRUCTIONS
Operation on Table Pointer
TBLRD*
TBLWT*
TBLPTR is not modified
TBLRD*+
TBLWT*+
TBLPTR is incremented after the read/write
TBLPTR is decremented after the read/write
TBLPTR is incremented before the read/write
TBLRD*-
TBLWT*-
TBLRD+*
TBLWT+*
FIGURE 6-3:
TABLE POINTER BOUNDARIES BASED ON OPERATION
21
16 15
TBLPTRH
8
7
TBLPTRL
0
TBLPTRU
TABLE ERASE
TBLPTR<21:6>
TABLE WRITE – TBLPTR<21:4>
TABLE READ – TBLPTR<21:0>
DS39760D-page 76
© 2008 Microchip Technology Inc.
PIC18F2450/4450
TBLPTR points to a byte address in program space.
Executing TBLRD places the byte pointed to into
TABLAT. In addition, TBLPTR can be modified
automatically for the next table read operation.
6.3
Reading the Flash Program
Memory
The TBLRD instruction is used to retrieve data from
program memory and places it into data RAM. Table
reads from program memory are performed one byte at
a time.
The internal program memory is typically organized by
words. The Least Significant bit of the address selects
between the high and low bytes of the word. Figure 6-4
shows the interface between the internal program
memory and the TABLAT.
FIGURE 6-4:
READS FROM FLASH PROGRAM MEMORY
Program Memory
(Even Byte Address)
(Odd Byte Address)
TBLPTR = xxxxx1
TBLPTR = xxxxx0
Instruction Register
TABLAT
Read Register
FETCH
TBLRD
(IR)
EXAMPLE 6-1:
READING A FLASH PROGRAM MEMORY WORD
MOVLW
CODE_ADDR_UPPER
TBLPTRU
CODE_ADDR_HIGH
TBLPTRH
CODE_ADDR_LOW
TBLPTRL
; Load TBLPTR with the base
; address of the word
MOVWF
MOVLW
MOVWF
MOVLW
MOVWF
READ_WORD
TBLRD*+
MOVF
MOVWF
TBLRD*+
MOVF
; read into TABLAT and increment
; get data
TABLAT, W
WORD_EVEN
; read into TABLAT and increment
; get data
TABLAT, W
WORD_ODD
MOVF
© 2008 Microchip Technology Inc.
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6.4.1
FLASH PROGRAM MEMORY
ERASE SEQUENCE
6.4
Erasing Flash Program Memory
The minimum erase block is 32 words or 64 bytes. Only
through the use of an external programmer, or through
ICSP control, can larger blocks of program memory be
Bulk Erased. Word Erase in the Flash array is not
supported.
The sequence of events for erasing a block of internal
program memory is:
1. Load Table Pointer register with address of row
being erased.
When initiating an erase sequence from the
microcontroller itself, a block of 64 bytes of program
memory is erased. The Most Significant 16 bits of the
TBLPTR<21:6> point to the block being erased.
TBLPTR<5:0> are ignored.
2. Set the EECON1 register for the erase operation:
• clear the CFGS bit to access program memory;
• set WREN bit to enable writes;
• set FREE bit to enable the erase.
3. Disable interrupts.
The EECON1 register commands the erase operation.
The WREN bit must be set to enable write operations.
The FREE bit is set to select an erase operation.
4. Write 55h to EECON2.
5. Write 0AAh to EECON2.
6. Set the WR bit. This will begin the Row Erase
cycle.
For protection, the write initiate sequence for EECON2
must be used.
7. The CPU will stall for duration of the erase
(about 2 ms using internal timer).
A long write is necessary for erasing the internal Flash.
Instruction execution is halted while in a long write
cycle. The long write will be terminated by the internal
programming timer.
8. Re-enable interrupts.
EXAMPLE 6-2:
ERASING A FLASH PROGRAM MEMORY ROW
MOVLW
MOVWF
MOVLW
MOVWF
MOVLW
MOVWF
CODE_ADDR_UPPER
TBLPTRU
CODE_ADDR_HIGH
TBLPTRH
CODE_ADDR_LOW
TBLPTRL
; load TBLPTR with the base
; address of the memory block
ERASE_ROW
BCF
BSF
BSF
BCF
MOVLW
MOVWF
MOVLW
MOVWF
BSF
EECON1, CFGS
EECON1, WREN
EECON1, FREE
INTCON, GIE
55h
EECON2
0AAh
EECON2
EECON1, WR
INTCON, GIE
; access Flash program memory
; enable write to memory
; enable Row Erase operation
; disable interrupts
Required
Sequence
; write 55h
; write 0AAh
; start erase (CPU stall)
; re-enable interrupts
BSF
DS39760D-page 78
© 2008 Microchip Technology Inc.
PIC18F2450/4450
The long write is necessary for programming the
internal Flash. Instruction execution is halted while in a
long write cycle. The long write will be terminated by
the internal programming timer.
6.5
Writing to Flash Program Memory
The minimum programming block is 8 words or
16 bytes. Word or byte programming is not supported.
Table writes are used internally to load the holding
registers needed to program the Flash memory. There
are 16 holding registers used by the table writes for
programming.
The write/erase voltages are generated by an on-chip
charge pump, rated to operate over the voltage range
of the device.
Note:
The default value of the holding registers on
device Resets and after write operations is
FFh. A write of FFh to a holding register
does not modify that byte. This means that
individual bytes of program memory may be
modified, provided that the change does not
attempt to change any bit from a ‘0’ to a ‘1’.
When modifying individual bytes, it is not
necessary to load all 16 holding registers
before executing a write operation.
Since the Table Latch (TABLAT) is only a single byte, the
TBLWTinstruction may need to be executed 16 times for
each programming operation. All of the table write oper-
ations will essentially be short writes because only the
holding registers are written. At the end of updating the
16 holding registers, the EECON1 register must be
written to in order to start the programming operation
with a long write.
FIGURE 6-5:
TABLE WRITES TO FLASH PROGRAM MEMORY
TABLAT
Write Register
8
8
8
8
TBLPTR = xxxxx0
TBLPTR = xxxxx1
TBLPTR = xxxxx2
TBLPTR = xxxxxF
Holding Register
Holding Register
Holding Register
Holding Register
Program Memory
10. Write 0AAh to EECON2.
6.5.1
FLASH PROGRAM MEMORY WRITE
SEQUENCE
11. Set the WR bit. This will begin the write cycle.
12. The CPU will stall for duration of the write (about
2 ms using internal timer).
The sequence of events for programming an internal
program memory location should be:
13. Re-enable interrupts.
1. Read 64 bytes into RAM.
14. Repeat steps 6 through 14 once more to write
64 bytes.
2. Update data values in RAM as necessary.
3. Load Table Pointer register with address being
erased.
15. Verify the memory (table read).
This procedure will require about 8 ms to update one
row of 64 bytes of memory. An example of the required
code is given in Example 6-3.
4. Execute the Row Erase procedure.
5. Load Table Pointer register with address of first
byte being written.
Note:
Before setting the WR bit, the Table
Pointer address needs to be within the
intended address range of the 16 bytes in
the holding register.
6. Write 16 bytes into the holding registers with
auto-increment.
7. Set the EECON1 register for the write operation:
• clear the CFGS bit to access program memory;
• set WREN to enable byte writes.
8. Disable interrupts.
9. Write 55h to EECON2.
© 2008 Microchip Technology Inc.
DS39760D-page 79
PIC18F2450/4450
EXAMPLE 6-3:
WRITING TO FLASH PROGRAM MEMORY
MOVLW
MOVWF
MOVLW
MOVWF
MOVLW
MOVWF
MOVLW
MOVWF
MOVLW
MOVWF
MOVLW
MOVWF
D'64’
COUNTER
BUFFER_ADDR_HIGH
FSR0H
BUFFER_ADDR_LOW
FSR0L
CODE_ADDR_UPPER
TBLPTRU
CODE_ADDR_HIGH
TBLPTRH
CODE_ADDR_LOW
TBLPTRL
; number of bytes in erase block
; point to buffer
; Load TBLPTR with the base
; address of the memory block
READ_BLOCK
TBLRD*+
MOVF
MOVWF
DECFSZ
BRA
; read into TABLAT, and inc
; get data
; store data
; done?
TABLAT, W
POSTINC0
COUNTER
READ_BLOCK
; repeat
MODIFY_WORD
MOVLW
MOVWF
MOVLW
MOVWF
MOVLW
MOVWF
MOVLW
MOVWF
DATA_ADDR_HIGH
FSR0H
DATA_ADDR_LOW
FSR0L
NEW_DATA_LOW
POSTINC0
NEW_DATA_HIGH
INDF0
; point to buffer
; update buffer word
ERASE_BLOCK
MOVLW
MOVWF
MOVLW
MOVWF
MOVLW
MOVWF
BCF
BSF
BSF
BCF
CODE_ADDR_UPPER
TBLPTRU
CODE_ADDR_HIGH
TBLPTRH
CODE_ADDR_LOW
TBLPTRL
EECON1, CFGS
EECON1, WREN
EECON1, FREE
INTCON, GIE
; load TBLPTR with the base
; address of the memory block
; access Flash program memory
; enable write to memory
; enable Row Erase operation
; disable interrupts
MOVLW
MOVWF
MOVLW
MOVWF
BSF
55h
EECON2
0AAh
EECON2
EECON1, WR
INTCON, GIE
Required
Sequence
; write 55h
; write 0AAh
; start erase (CPU stall)
; re-enable interrupts
; dummy read decrement
; point to buffer
BSF
TBLRD*-
MOVLW
MOVWF
MOVLW
MOVWF
MOVLW
MOVWF
BUFFER_ADDR_HIGH
FSR0H
BUFFER_ADDR_LOW
FSR0L
D’4’
COUNTER1
WRITE_BUFFER_BACK
MOVLW
D’16’
; number of bytes in holding register
MOVWF
WRITE_BYTE_TO_HREGS
MOVF
COUNTER
POSTINC0, W
TABLAT
; get low byte of buffer data
; present data to table latch
; write data, perform a short write
; to internal TBLWT holding register.
; loop until buffers are full
MOVWF
TBLWT+*
DECFSZ
BRA
COUNTER
WRITE_WORD_TO_HREGS
DS39760D-page 80
© 2008 Microchip Technology Inc.
PIC18F2450/4450
EXAMPLE 6-3:
WRITING TO FLASH PROGRAM MEMORY (CONTINUED)
PROGRAM_MEMORY
BCF
BSF
BCF
EECON1, CFGS
EECON1, WREN
INTCON, GIE
; access Flash program memory
; enable write to memory
; disable interrupts
MOVLW
MOVWF
MOVLW
MOVWF
BSF
DECFSZ
BRA
BSF
55h
EECON2
0AAh
EECON2
EECON1, WR
COUNTER1
WRITE_BUFFER_BACK
INTCON, GIE
EECON1, WREN
Required
Sequence
; write 55h
; write 0AAh
; start program (CPU stall)
; re-enable interrupts
; disable write to memory
BCF
6.5.2
WRITE VERIFY
6.5.4
PROTECTION AGAINST SPURIOUS
WRITES
Depending on the application, good programming
practice may dictate that the value written to the
memory should be verified against the original value.
This should be used in applications where excessive
writes can stress bits near the specification limit.
To protect against spurious writes to Flash program
memory, the write initiate sequence must also be
followed. See Section 18.0 “Special Features of the
CPU” for more detail.
6.5.3
UNEXPECTED TERMINATION OF
WRITE OPERATION
6.6
Flash Program Operation During
Code Protection
If a write is terminated by an unplanned event, such as
loss of power or an unexpected Reset, the memory
location just programmed should be verified and
reprogrammed if needed. If the write operation is
interrupted by a MCLR Reset or a WDT time-out Reset
during normal operation, the user can check the
WRERR bit and rewrite the location(s) as needed.
See Section 18.5 “Program Verification and Code
Protection” for details on code protection of Flash
program memory.
TABLE 6-2:
Name
REGISTERS ASSOCIATED WITH PROGRAM FLASH MEMORY
Reset
Values
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
on Page:
TBLPTRU
—
—
bit 21 Program Memory Table Pointer Upper Byte (TBLPTR<20:16>)
49
49
49
49
49
51
51
51
51
51
TBPLTRH Program Memory Table Pointer High Byte (TBLPTR<15:8>)
TBLPTRL Program Memory Table Pointer Low Byte (TBLPTR<7:0>)
TABLAT
INTCON
Program Memory Table Latch
GIE/GIEH PEIE/GIEL TMR0IE
INT0IE
RBIE
TMR0IF
INT0IF
RBIF
EECON2 Data Memory Control Register 2 (not a physical register)
EECON1
IPR2
—
CFGS
—
—
FREE
—
WRERR
WREN
HLVDIP
HLVDIF
HLVDIE
WR
—
—
—
—
—
OSCFIP
OSCFIF
OSCFIE
USBIP
USBIF
USBIE
—
—
—
PIR2
—
—
—
PIE2
—
—
—
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used during Flash access.
© 2008 Microchip Technology Inc.
DS39760D-page 81
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NOTES:
DS39760D-page 82
© 2008 Microchip Technology Inc.
PIC18F2450/4450
EXAMPLE 7-1:
8 x 8 UNSIGNED
MULTIPLY ROUTINE
7.0
7.1
8 x 8 HARDWARE MULTIPLIER
Introduction
MOVF
MULWF
ARG1, W
ARG2
;
; ARG1 * ARG2 ->
; PRODH:PRODL
All PIC18 devices include an 8 x 8 hardware multiplier
as part of the ALU. The multiplier performs an unsigned
operation and yields a 16-bit result that is stored in the
product register pair, PRODH:PRODL. The multiplier’s
operation does not affect any flags in the STATUS
register.
EXAMPLE 7-2:
8 x 8 SIGNED MULTIPLY
ROUTINE
Making multiplication a hardware operation allows it to
be completed in a single instruction cycle. This has the
advantages of higher computational throughput and
reduced code size for multiplication algorithms and
allows the PIC18 devices to be used in many applica-
tions previously reserved for digital signal processors.
A comparison of various hardware and software
multiply operations, along with the savings in memory
and execution time, is shown in Table 7-1.
MOVF
MULWF
ARG1, W
ARG2
; ARG1 * ARG2 ->
; PRODH:PRODL
; Test Sign Bit
; PRODH = PRODH
BTFSC
SUBWF
ARG2, SB
PRODH, F
;
- ARG1
MOVF
BTFSC
SUBWF
ARG2, W
ARG1, SB
PRODH, F
; Test Sign Bit
; PRODH = PRODH
;
- ARG2
7.2
Operation
Example 7-1 shows the instruction sequence for an
8 x 8 unsigned multiplication. Only one instruction is
required when one of the arguments is already loaded
in the WREG register.
Example 7-2 shows the sequence to do an 8 x 8 signed
multiplication. To account for the sign bits of the
arguments, each argument’s Most Significant bit (MSb)
is tested and the appropriate subtractions are done.
TABLE 7-1:
Routine
PERFORMANCE COMPARISON FOR VARIOUS MULTIPLY OPERATIONS
Program
Memory
(Words)
Time
Cycles
(Max)
Multiply Method
@ 40 MHz @ 10 MHz @ 4 MHz
Without hardware multiply
Hardware multiply
13
1
69
1
6.9 μs
100 ns
9.1 μs
600 ns
24.2 μs
2.8 μs
25.4 μs
4.0 μs
27.6 μs
400 ns
36.4 μs
2.4 μs
69 μs
1 μs
8 x 8 unsigned
8 x 8 signed
Without hardware multiply
Hardware multiply
33
6
91
6
91 μs
6 μs
Without hardware multiply
Hardware multiply
21
28
52
35
242
28
254
40
96.8 μs
11.2 μs
102.6 μs
16.0 μs
242 μs
28 μs
254 μs
40 μs
16 x 16 unsigned
16 x 16 signed
Without hardware multiply
Hardware multiply
© 2008 Microchip Technology Inc.
DS39760D-page 83
PIC18F2450/4450
Example 7-3 shows the sequence to do a 16 x 16
unsigned multiplication. Equation 7-1 shows the
algorithm that is used. The 32-bit result is stored in four
registers (RES3:RES0).
EQUATION 7-2:
16 x 16 SIGNED
MULTIPLICATION
ALGORITHM
RES3:RES0=ARG1H:ARG1L • ARG2H:ARG2L
16
= (ARG1H • ARG2H • 2 ) +
(ARG1H • ARG2L • 2 ) +
(ARG1L • ARG2H • 2 ) +
(ARG1L • ARG2L) +
(-1 • ARG2H<7> • ARG1H:ARG1L • 2 ) +
(-1 • ARG1H<7> • ARG2H:ARG2L • 2
8
EQUATION 7-1:
16 x 16 UNSIGNED
MULTIPLICATION
ALGORITHM
8
16
RES3:RES0
=
=
ARG1H:ARG1L • ARG2H:ARG2L
16
)
16
(ARG1H • ARG2H • 2 ) +
8
(ARG1H • ARG2L • 2 ) +
8
(ARG1L • ARG2H • 2 ) +
EXAMPLE 7-4:
16 x 16 SIGNED
MULTIPLY ROUTINE
(ARG1L • ARG2L)
MOVF
ARG1L, W
MULWF
ARG2L
; ARG1L * ARG2L ->
; PRODH:PRODL
;
;
EXAMPLE 7-3:
16 x 16 UNSIGNED
MULTIPLY ROUTINE
MOVFF
MOVFF
PRODH, RES1
PRODL, RES0
MOVF
MULWF
ARG1L, W
ARG2L
; ARG1L * ARG2L->
; PRODH:PRODL
;
;
;
;
MOVF
MULWF
ARG1H, W
ARG2H
MOVFF
MOVFF
PRODH, RES1
PRODL, RES0
; ARG1H * ARG2H ->
; PRODH:PRODL
;
;
;
;
MOVFF
MOVFF
PRODH, RES3
PRODL, RES2
MOVF
MULWF
ARG1H, W
ARG2H
; ARG1H * ARG2H->
; PRODH:PRODL
;
;
MOVF
MULWF
ARG1L,W
ARG2H
MOVFF
MOVFF
PRODH, RES3
PRODL, RES2
; ARG1L * ARG2H ->
; PRODH:PRODL
;
; Add cross
; products
;
;
;
MOVF
ADDWF
MOVF
ADDWFC RES2, F
CLRF WREG
ADDWFC RES3, F
PRODL, W
RES1, F
PRODH, W
MOVF
MULWF
ARG1L, W
ARG2H
; ARG1L * ARG2H->
; PRODH:PRODL
;
; Add cross
; products
;
;
;
MOVF
ADDWF
MOVF
PRODL, W
RES1, F
PRODH, W
;
ADDWFC RES2, F
CLRF WREG
ADDWFC RES3, F
MOVF
MULWF
ARG1H, W
ARG2L
;
; ARG1H * ARG2L ->
; PRODH:PRODL
;
; Add cross
; products
;
;
;
;
MOVF
ADDWF
MOVF
ADDWFC RES2, F
CLRF WREG
ADDWFC RES3, F
PRODL, W
RES1, F
PRODH, W
MOVF
MULWF
ARG1H, W
ARG2L
;
; ARG1H * ARG2L->
; PRODH:PRODL
;
; Add cross
; products
;
;
;
MOVF
ADDWF
MOVF
PRODL, W
RES1, F
PRODH, W
;
;
ADDWFC RES2, F
CLRF WREG
ADDWFC RES3, F
BTFSS
BRA
MOVF
SUBWF
MOVF
ARG2H, 7
SIGN_ARG1
ARG1L, W
RES2
; ARG2H:ARG2L neg?
; no, check ARG1
;
;
;
Example 7-4 shows the sequence to do a 16 x 16
signed multiply. Equation 7-2 shows the algorithm
used. The 32-bit result is stored in four registers
(RES3:RES0). To account for the sign bits of the
arguments, the MSb for each argument pair is tested
and the appropriate subtractions are done.
ARG1H, W
SUBWFB RES3
SIGN_ARG1
BTFSS
BRA
ARG1H, 7
CONT_CODE
ARG2L, W
RES2
; ARG1H:ARG1L neg?
; no, done
;
;
;
MOVF
SUBWF
MOVF
ARG2H, W
SUBWFB RES3
;
CONT_CODE
:
DS39760D-page 84
© 2008 Microchip Technology Inc.
PIC18F2450/4450
When an interrupt is responded to, the global interrupt
enable bit is cleared to disable further interrupts. If the
IPEN bit is cleared, this is the GIE bit. If interrupt priority
levels are used, this will be either the GIEH or GIEL bit.
High-priority interrupt sources can interrupt a low-
priority interrupt. Low-priority interrupts are not
processed while high-priority interrupts are in progress.
8.0
INTERRUPTS
The PIC18F2450/4450 devices have multiple interrupt
sources and an interrupt priority feature that allows
each interrupt source to be assigned a high-priority
level or a low-priority level. The high-priority interrupt
vector is at 000008h and the low-priority interrupt vec-
tor is at 000018h. High-priority interrupt events will
interrupt any low-priority interrupts that may be in
progress.
The return address is pushed onto the stack and the PC
is loaded with the interrupt vector address (000008h or
000018h). Once in the Interrupt Service Routine, the
source(s) of the interrupt can be determined by polling
the interrupt flag bits. The interrupt flag bits must be
cleared in software before re-enabling interrupts to avoid
recursive interrupts.
There are ten registers which are used to control
interrupt operation. These registers are:
• RCON
• INTCON
The “return from interrupt” instruction, RETFIE, exits
the interrupt routine and sets the GIE bit (GIEH or GIEL
if priority levels are used) which re-enables interrupts.
• INTCON2
• INTCON3
• PIR1, PIR2
• PIE1, PIE2
• IPR1, IPR2
For external interrupt events, such as the INTx pins or
the PORTB input change interrupt, the interrupt latency
will be three to four instruction cycles. The exact
latency is the same for one or two-cycle instructions.
Individual interrupt flag bits are set regardless of the
status of their corresponding enable bit or the GIE bit.
It is recommended that the Microchip header files
supplied with MPLAB® IDE be used for the symbolic bit
names in these registers. This allows the assembler/
compiler to automatically take care of the placement of
these bits within the specified register.
Note:
Do not use the MOVFFinstruction to modify
any of the interrupt control registers while
any interrupt is enabled. Doing so may
cause erratic microcontroller behavior.
Each interrupt source has three bits to control its
operation. The functions of these bits are:
• Flag bit to indicate that an interrupt event
occurred
8.1
USB Interrupts
• Enable bit that allows program execution to
branch to the interrupt vector address when the
flag bit is set
Unlike other peripherals, the USB module is capable of
generating a wide range of interrupts for many types of
events. These include several types of normal commu-
nication and status events and several module level
error events.
• Priority bit to select high priority or low priority
The interrupt priority feature is enabled by setting the
IPEN bit (RCON<7>). When interrupt priority is
enabled, there are two bits which enable interrupts
globally. Setting the GIEH bit (INTCON<7>) enables all
interrupts that have the priority bit set (high priority).
Setting the GIEL bit (INTCON<6>) enables all
interrupts that have the priority bit cleared (low priority).
When the interrupt flag, enable bit and appropriate
global interrupt enable bit are set, the interrupt will
vector immediately to address 000008h or 000018h,
depending on the priority bit setting. Individual inter-
rupts can be disabled through their corresponding
enable bits.
To handle these events, the USB module is equipped
with its own interrupt logic. The logic functions in a
manner similar to the microcontroller level interrupt
funnel, with each interrupt source having separate flag
and enable bits. All events are funneled to a single
device level interrupt, USBIF (PIR2<5>). Unlike the
device level interrupt logic, the individual USB interrupt
events cannot be individually assigned their own prior-
ity. This is determined at the device level interrupt
funnel for all USB events by the USBIP bit.
For additional details on USB interrupt logic, refer to
Section 14.5 “USB Interrupts”.
When the IPEN bit is cleared (default state), the
interrupt priority feature is disabled and interrupts are
compatible with PIC® mid-range microcontrollers. In
Compatibility mode, the interrupt priority bits for each
source have no effect. INTCON<6> is the PEIE bit
which enables/disables all peripheral interrupt sources.
INTCON<7> is the GIE bit which enables/disables all
interrupt sources. All interrupts branch to address
000008h in Compatibility mode.
© 2008 Microchip Technology Inc.
DS39760D-page 85
PIC18F2450/4450
FIGURE 8-1:
INTERRUPT LOGIC
Wake-up if in Sleep Mode
TMR0IF
TMR0IE
TMR0IP
RBIF
RBIE
RBIP
INT0IF
INT0IE
Interrupt to CPU
Vector to Location
0008h
INT1IF
INT1IE
INT1IP
INT2IF
INT2IE
INT2IP
Peripheral Interrupt Flag bit
Peripheral Interrupt Enable bit
Peripheral Interrupt Priority bit
GIE/GIEH
TMR1IF
TMR1IE
TMR1IP
IPEN
From USB
Interrupt Logic
IPEN
USBIF
USBIE
USBIP
PEIE/GIEL
IPEN
Additional Peripheral Interrupts
High-Priority Interrupt Generation
Low-Priority Interrupt Generation
Peripheral Interrupt Flag bit
Peripheral Interrupt Enable bit
Peripheral Interrupt Priority bit
Interrupt to CPU
Vector to Location
0018h
TMR0IF
TMR0IE
TMR0IP
TMR1IF
TMR1IE
TMR1IP
RBIF
RBIE
From USB
Interrupt Logic
USBIF
USBIE
USBIP
RBIP
PEIE/GIEL
GIE/GIEH
INT1IF
INT1IE
INT1IP
Additional Peripheral Interrupts
INT2IF
INT2IE
INT2IP
DS39760D-page 86
© 2008 Microchip Technology Inc.
PIC18F2450/4450
8.2
INTCON Registers
Note:
Interrupt flag bits are set when an interrupt
condition occurs regardless of the state of
its corresponding enable bit or the global
interrupt enable bit. User software should
ensure the appropriate interrupt flag bits
are clear prior to enabling an interrupt.
This feature allows for software polling.
The INTCON registers are readable and writable
registers which contain various enable, priority and flag
bits.
REGISTER 8-1:
INTCON: INTERRUPT CONTROL REGISTER
R/W-0
GIE/GIEH
bit 7
R/W-0
R/W-0
R/W-0
R/W-0
RBIE
R/W-0
R/W-0
INT0IF
R/W-x
RBIF(1)
PEIE/GIEL
TMR0IE
INT0IE
TMR0IF
bit 0
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
-n = Value at POR
bit 7
GIE/GIEH: Global Interrupt Enable bit
When IPEN = 0:
1= Enables all unmasked interrupts
0= Disables all interrupts
When IPEN = 1:
1= Enables all high-priority interrupts
0= Disables all interrupts
bit 6
PEIE/GIEL: Peripheral Interrupt Enable bit
When IPEN = 0:
1= Enables all unmasked peripheral interrupts
0= Disables all peripheral interrupts
When IPEN = 1:
1= Enables all low-priority peripheral interrupts
0= Disables all low-priority peripheral interrupts
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
TMR0IE: TMR0 Overflow Interrupt Enable bit
1= Enables the TMR0 overflow interrupt
0= Disables the TMR0 overflow interrupt
INT0IE: INT0 External Interrupt Enable bit
1= Enables the INT0 external interrupt
0= Disables the INT0 external interrupt
RBIE: RB Port Change Interrupt Enable bit
1= Enables the RB port change interrupt
0= Disables the RB port change interrupt
TMR0IF: TMR0 Overflow Interrupt Flag bit
1= TMR0 register has overflowed (must be cleared in software)
0= TMR0 register did not overflow
INT0IF: INT0 External Interrupt Flag bit
1= The INT0 external interrupt occurred (must be cleared in software)
0= The INT0 external interrupt did not occur
RBIF: RB Port Change Interrupt Flag bit(1)
1= At least one of the RB7:RB4 pins changed state (must be cleared in software)
0= None of the RB7:RB4 pins have changed state
Note 1: A mismatch condition will continue to set this bit. Reading PORTB and waiting 1 TCY will end the mismatch
condition and allow the bit to be cleared.
© 2008 Microchip Technology Inc.
DS39760D-page 87
PIC18F2450/4450
REGISTER 8-2:
INTCON2: INTERRUPT CONTROL REGISTER 2
R/W-1
RBPU
R/W-1
R/W-1
R/W-1
U-0
—
R/W-1
U-0
—
R/W-1
RBIP
INTEDG0
INTEDG1
INTEDG2
TMR0IP
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
-n = Value at POR
bit 7
bit 6
bit 5
bit 4
RBPU: PORTB Pull-up Enable bit
1= All PORTB pull-ups are disabled
0= PORTB pull-ups are enabled by individual port latch values
INTEDG0: External Interrupt 0 Edge Select bit
1= Interrupt on rising edge
0= Interrupt on falling edge
INTEDG1: External Interrupt 1 Edge Select bit
1= Interrupt on rising edge
0= Interrupt on falling edge
INTEDG2: External Interrupt 2 Edge Select bit
1= Interrupt on rising edge
0= Interrupt on falling edge
bit 3
bit 2
Unimplemented: Read as ‘0’
TMR0IP: TMR0 Overflow Interrupt Priority bit
1= High priority
0= Low priority
bit 1
bit 0
Unimplemented: Read as ‘0’
RBIP: RB Port Change Interrupt Priority bit
1= High priority
0= Low priority
Note:
Interrupt flag bits are set when an interrupt condition occurs regardless of the state of its corresponding
enable bit or the global interrupt enable bit. User software should ensure the appropriate interrupt flag bits
are clear prior to enabling an interrupt. This feature allows for software polling.
DS39760D-page 88
© 2008 Microchip Technology Inc.
PIC18F2450/4450
REGISTER 8-3:
INTCON3: INTERRUPT CONTROL REGISTER 3
R/W-1
INT2IP
bit 7
R/W-1
U-0
—
R/W-0
R/W-0
U-0
—
R/W-0
INT2IF
R/W-0
INT1IF
INT1IP
INT2IE
INT1IE
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7
bit 6
INT2IP: INT2 External Interrupt Priority bit
1= High priority
0= Low priority
INT1IP: INT1 External Interrupt Priority bit
1= High priority
0= Low priority
bit 5
bit 4
Unimplemented: Read as ‘0’
INT2IE: INT2 External Interrupt Enable bit
1= Enables the INT2 external interrupt
0= Disables the INT2 external interrupt
bit 3
INT1IE: INT1 External Interrupt Enable bit
1= Enables the INT1 external interrupt
0= Disables the INT1 external interrupt
bit 2
bit 1
Unimplemented: Read as ‘0’
INT2IF: INT2 External Interrupt Flag bit
1= The INT2 external interrupt occurred (must be cleared in software)
0= The INT2 external interrupt did not occur
bit 0
INT1IF: INT1 External Interrupt Flag bit
1= The INT1 external interrupt occurred (must be cleared in software)
0= The INT1 external interrupt did not occur
Note:
Interrupt flag bits are set when an interrupt condition occurs regardless of the state of its corresponding
enable bit or the global interrupt enable bit. User software should ensure the appropriate interrupt flag bits
are clear prior to enabling an interrupt. This feature allows for software polling.
© 2008 Microchip Technology Inc.
DS39760D-page 89
PIC18F2450/4450
8.3
PIR Registers
Note 1: Interrupt flag bits are set when an interrupt
condition occurs regardless of the state of
its corresponding enable bit or the Global
Interrupt Enable bit, GIE (INTCON<7>).
The PIR registers contain the individual flag bits for the
peripheral interrupts. Due to the number of peripheral
interrupt sources, there are two Peripheral Interrupt
Request (Flag) registers (PIR1 and PIR2).
2: User software should ensure the
appropriate interrupt flag bits are cleared
prior to enabling an interrupt and after
servicing that interrupt.
REGISTER 8-4:
PIR1: PERIPHERAL INTERRUPT REQUEST (FLAG) REGISTER 1
U-0
—
R/W-0
ADIF
R-0
R-0
U-0
—
R/W-0
R/W-0
R/W-0
RCIF
TXIF
CCP1IF
TMR2IF
TMR1IF
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7
bit 6
Unimplemented: Read as ‘0’
ADIF: A/D Converter Interrupt Flag bit
1= An A/D conversion completed (must be cleared in software)
0= The A/D conversion is not complete
bit 5
bit 4
RCIF: EUSART Receive Interrupt Flag bit
1= The EUSART receive buffer, RCREG, is full (cleared when RCREG is read)
0= The EUSART receive buffer is empty
TXIF: EUSART Transmit Interrupt Flag bit
1= The EUSART transmit buffer, TXREG, is empty (cleared when TXREG is written)
0= The EUSART transmit buffer is full
bit 3
bit 2
Unimplemented: Read as ‘0’
CCP1IF: CCP1 Interrupt Flag bit
Capture mode:
1= A TMR1 register capture occurred (must be cleared in software)
0= No TMR1 register capture occurred
Compare mode:
1= A TMR1 register compare match occurred (must be cleared in software)
0= No TMR1 register compare match occurred
PWM mode:
Unused in this mode.
bit 1
bit 0
TMR2IF: TMR2 to PR2 Match Interrupt Flag bit
1= TMR2 to PR2 match occurred (must be cleared in software)
0= No TMR2 to PR2 match occurred
TMR1IF: TMR1 Overflow Interrupt Flag bit
1= TMR1 register overflowed (must be cleared in software)
0= TMR1 register did not overflow
DS39760D-page 90
© 2008 Microchip Technology Inc.
PIC18F2450/4450
REGISTER 8-5:
PIR2: PERIPHERAL INTERRUPT REQUEST (FLAG) REGISTER 2
R/W-0
OSCFIF
bit 7
U-0
—
R/W-0
USBIF
U-0
—
U-0
—
R/W-0
U-0
—
U-0
—
HLVDIF
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7
OSCFIF: Oscillator Fail Interrupt Flag bit
1= System oscillator failed, clock input has changed to INTRC (must be cleared in software)
0= System clock operating
bit 6
bit 5
Unimplemented: Read as ‘0’
USBIF: USB Interrupt Flag bit
1= USB has requested an interrupt (must be cleared in software)
0= No USB interrupt request
bit 4-3
bit 2
Unimplemented: Read as ‘0’
HLVDIF: High/Low-Voltage Detect Interrupt Flag bit
1= A high/low-voltage condition occurred
0= No high/low-voltage event has occurred
bit 1-0
Unimplemented: Read as ‘0’
© 2008 Microchip Technology Inc.
DS39760D-page 91
PIC18F2450/4450
8.4
PIE Registers
The PIE registers contain the individual enable bits for
the peripheral interrupts. Due to the number of
peripheral interrupt sources, there are two Peripheral
Interrupt Enable registers (PIE1 and PIE2). When
IPEN = 0, the PEIE bit must be set to enable any of
these peripheral interrupts.
REGISTER 8-6:
PIE1: PERIPHERAL INTERRUPT ENABLE REGISTER 1
U-0
—
R/W-0
ADIE
R/W-0
RCIE
R/W-0
TXIE
U-0
—
R/W-0
R/W-0
R/W-0
CCP1IE
TMR2IE
TMR1IE
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7
bit 6
Unimplemented: Read as ‘0’
ADIE: A/D Converter Interrupt Enable bit
1= Enables the A/D interrupt
0= Disables the A/D interrupt
bit 5
bit 4
RCIE: EUSART Receive Interrupt Enable bit
1= Enables the EUSART receive interrupt
0= Disables the EUSART receive interrupt
TXIE: EUSART Transmit Interrupt Enable bit
1= Enables the EUSART transmit interrupt
0= Disables the EUSART transmit interrupt
bit 3
bit 2
Unimplemented: Read as ‘0’
CCP1IE: CCP1 Interrupt Enable bit
1= Enables the CCP1 interrupt
0= Disables the CCP1 interrupt
bit 1
bit 0
TMR2IE: TMR2 to PR2 Match Interrupt Enable bit
1= Enables the TMR2 to PR2 match interrupt
0= Disables the TMR2 to PR2 match interrupt
TMR1IE: TMR1 Overflow Interrupt Enable bit
1= Enables the TMR1 overflow interrupt
0= Disables the TMR1 overflow interrupt
DS39760D-page 92
© 2008 Microchip Technology Inc.
PIC18F2450/4450
REGISTER 8-7:
PIE2: PERIPHERAL INTERRUPT ENABLE REGISTER 2
R/W-0
OSCFIE
bit 7
U-0
—
R/W-0
USBIE
U-0
—
U-0
—
R/W-0
U-0
—
U-0
—
HLVDIE
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7
OSCFIE: Oscillator Fail Interrupt Enable bit
1= Enabled
0= Disabled
bit 6
bit 5
Unimplemented: Read as ‘0’
USBIE: USB Interrupt Enable bit
1= Enabled
0= Disabled
bit 4-3
bit 2
Unimplemented: Read as ‘0’
HLVDIE: High/Low-Voltage Detect Interrupt Enable bit
1= Enabled
0= Disabled
bit 1-0
Unimplemented: Read as ‘0’
© 2008 Microchip Technology Inc.
DS39760D-page 93
PIC18F2450/4450
8.5
IPR Registers
The IPR registers contain the individual priority bits for
the peripheral interrupts. Due to the number of
peripheral interrupt sources, there are two Peripheral
Interrupt Priority registers (IPR1 and IPR2). Using the
priority bits requires that the Interrupt Priority Enable
(IPEN) bit be set.
REGISTER 8-8:
IPR1: PERIPHERAL INTERRUPT PRIORITY REGISTER 1
U-0
—
R/W-1
ADIP
R/W-1
RCIP
R/W-1
TXIP
U-0
—
R/W-1
R/W-1
R/W-1
CCP1IP
TMR2IP
TMR1IP
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7
bit 6
Unimplemented: Read as ‘0’
ADIP: A/D Converter Interrupt Priority bit
1= High priority
0= Low priority
bit 5
bit 4
RCIP: EUSART Receive Interrupt Priority bit
1= High priority
0= Low priority
TXIP: EUSART Transmit Interrupt Priority bit
1= High priority
0= Low priority
bit 3
bit 2
Unimplemented: Read as ‘0’
CCP1IP: CCP1 Interrupt Priority bit
1= High priority
0= Low priority
bit 1
bit 0
TMR2IP: TMR2 to PR2 Match Interrupt Priority bit
1= High priority
0= Low priority
TMR1IP: TMR1 Overflow Interrupt Priority bit
1= High priority
0= Low priority
DS39760D-page 94
© 2008 Microchip Technology Inc.
PIC18F2450/4450
REGISTER 8-9:
IPR2: PERIPHERAL INTERRUPT PRIORITY REGISTER 2
R/W-1
OSCFIP
bit 7
U-0
—
R/W-1
USBIP
U-0
—
U-0
—
R/W-1
U-0
—
U-0
—
HLVDIP
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7
OSCFIP: Oscillator Fail Interrupt Priority bit
1= High priority
0= Low priority
bit 6
bit 5
Unimplemented: Read as ‘0’
USBIP: USB Interrupt Priority bit
1= High priority
0= Low priority
bit 4-3
bit 2
Unimplemented: Read as ‘0’
HLVDIP: High/Low-Voltage Detect Interrupt Priority bit
1= High priority
0= Low priority
bit 1-0
Unimplemented: Read as ‘0’
© 2008 Microchip Technology Inc.
DS39760D-page 95
PIC18F2450/4450
8.6
RCON Register
The RCON register contains flag bits which are used to
determine the cause of the last Reset or wake-up from
Idle or Sleep modes. RCON also contains the IPEN bit
which enables interrupt priorities.
REGISTER 8-10: RCON: RESET CONTROL REGISTER
R/W-0
IPEN
R/W-1(1)
U-0
—
R/W-1
RI
R-1
TO
R-1
PD
R/W-0(2)
POR
R/W-0
BOR
SBOREN
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
-n = Value at POR
bit 7
bit 6
IPEN: Interrupt Priority Enable bit
1= Enable priority levels on interrupts
0= Disable priority levels on interrupts (PIC16CXXX Compatibility mode)
SBOREN: BOR Software Enable bit(1)
For details of bit operation, see Register 4-1.
Unimplemented: Read as ‘0’
bit 5
bit 4
RI: RESETInstruction Flag bit
For details of bit operation, see Register 4-1.
TO: Watchdog Time-out Flag bit
bit 3
bit 2
bit 1
bit 0
For details of bit operation, see Register 4-1.
PD: Power-Down Detection Flag bit
For details of bit operation, see Register 4-1.
POR: Power-on Reset Status bit(2)
For details of bit operation, see Register 4-1.
BOR: Brown-out Reset Status bit
For details of bit operation, see Register 4-1.
Note 1: If SBOREN is enabled, its Reset state is ‘1’; otherwise, it is ‘0’. See Register 4-1 for additional information.
2: The actual Reset value of POR is determined by the type of device Reset. See Register 4-1 for additional
information.
DS39760D-page 96
© 2008 Microchip Technology Inc.
PIC18F2450/4450
8.7
INTx Pin Interrupts
8.8
TMR0 Interrupt
External interrupts on the RB0/AN12/INT0, RB1/AN10/
INT1and RB2/AN8/INT2/VMO pins are edge-triggered.
If the corresponding INTEDGx bit in the INTCON2
register is set (= 1), the interrupt is triggered by a rising
edge; if the bit is clear, the trigger is on the falling edge.
When a valid edge appears on the RBx/INTx pin, the
corresponding flag bit, INTxIF, is set. This interrupt can
be disabled by clearing the corresponding enable bit,
INTxIE. Flag bit, INTxIF, must be cleared in software in
the Interrupt Service Routine before re-enabling the
interrupt.
In 8-bit mode (which is the default), an overflow in the
TMR0 register (FFh → 00h) will set flag bit, TMR0IF. In
16-bit mode, an overflow in the TMR0H:TMR0L
register pair (FFFFh → 0000h) will set TMR0IF. The
interrupt can be enabled/disabled by setting/clearing
enable bit, TMR0IE (INTCON<5>). Interrupt priority for
Timer0 is determined by the value contained in the
interrupt priority bit, TMR0IP (INTCON2<2>). See
Section 12.0 “Timer2 Module” for further details on
the Timer0 module.
8.9
PORTB Interrupt-on-Change
All external interrupts (INT0, INT1 and INT2) can wake-
up the processor from the power-managed modes if bit,
INTxIE, was set prior to going into the power-managed
modes. If the Global Interrupt Enable bit, GIE, is set, the
processor will branch to the interrupt vector following
wake-up.
An input change on PORTB<7:4> sets flag bit, RBIF
(INTCON<0>). The interrupt can be enabled/disabled
by setting/clearing enable bit, RBIE (INTCON<3>).
Interrupt priority for PORTB interrupt-on-change is
determined by the value contained in the interrupt
priority bit, RBIP (INTCON2<0>).
Interrupt priority for INT1 and INT2 is determined by
the value contained in the interrupt priority bits,
INT1IP (INTCON3<6>) and INT2IP (INTCON3<7>).
There is no priority bit associated with INT0. It is
always a high-priority interrupt source.
8.10 Context Saving During Interrupts
During interrupts, the return PC address is saved on
the stack. Additionally, the WREG, STATUS and BSR
registers are saved on the Fast Return Stack. If a fast
return from interrupt is not used (see Section 5.3
“Data Memory Organization”), the user may need to
save the WREG, STATUS and BSR registers on entry
to the Interrupt Service Routine. Depending on the
user’s application, other registers may also need to be
saved. Example 8-1 saves and restores the WREG,
STATUS and BSR registers during an Interrupt Service
Routine.
EXAMPLE 8-1:
SAVING STATUS, WREG AND BSR REGISTERS IN RAM
MOVWF
MOVFF
MOVFF
;
W_TEMP
STATUS, STATUS_TEMP
BSR, BSR_TEMP
; W_TEMP is in virtual bank
; STATUS_TEMP located anywhere
; BSR_TMEP located anywhere
; USER ISR CODE
;
MOVFF
MOVF
MOVFF
BSR_TEMP, BSR
W_TEMP, W
STATUS_TEMP, STATUS
; Restore BSR
; Restore WREG
; Restore STATUS
© 2008 Microchip Technology Inc.
DS39760D-page 97
PIC18F2450/4450
NOTES:
DS39760D-page 98
© 2008 Microchip Technology Inc.
PIC18F2450/4450
Reading the PORTA register reads the status of the
pins; writing to it will write to the port latch.
9.0
I/O PORTS
Depending on the device selected and features
enabled, there are up to five ports available. Some pins
of the I/O ports are multiplexed with an alternate
function from the peripheral features on the device. In
general, when a peripheral is enabled, that pin may not
be used as a general purpose I/O pin.
The Output Latch register (LATA) is also memory
mapped. Read-modify-write operations on the LATA
register read and write the latched output value for
PORTA.
The RA4 pin is multiplexed with the Timer0 module
clock input to become the RA4/T0CKI pin. The RA6 pin
is multiplexed with the main oscillator pin; it is enabled
as an oscillator or I/O pin by the selection of the main
oscillator in Configuration Register 1H (see
Section 18.1 “Configuration Bits” for details). When
not used as a port pin, RA6 and its associated TRIS
and LAT bits are read as ‘0’.
Each port has three registers for its operation. These
registers are:
• TRIS register (Data Direction register)
• PORT register (reads the levels on the pins of the
device)
• LAT register (Output Latch register)
RA4 is also multiplexed with the USB module; it serves
as a receiver input from an external USB transceiver.
For details on configuration of the USB module, see
Section 14.2 “USB Status and Control”.
The Output Latch register (LATA) is useful for read-
modify-write operations on the value driven by the I/O
pins.
A simplified model of a generic I/O port, without the
interfaces to other peripherals, is shown in Figure 9-1.
Several PORTA pins are multiplexed with analog inputs.
The operation of pins RA5 and RA3:RA0 as A/D
Converter inputs is selected by clearing/setting the
control bits in the ADCON1 register (A/D Control
Register 1).
FIGURE 9-1:
GENERIC I/O PORT
OPERATION
Note:
On a Power-on Reset, RA5 and RA3:RA0
are configured as analog inputs and read
as ‘0’. RA4 is configured as a digital input.
RD LAT
Data
Bus
D
Q
All other PORTA pins have TTL input levels and full
CMOS output drivers.
I/O pin(1)
WR LAT
or
PORT
CK
Data Latch
The TRISA register controls the direction of the RA
pins, even when they are being used as analog inputs.
The user must ensure the bits in the TRISA register are
maintained set when using them as analog inputs.
D
Q
WR TRIS
RD TRIS
CK
TRIS Latch
EXAMPLE 9-1:
INITIALIZING PORTA
Input
Buffer
CLRF
PORTA
LATA
0Fh
; Initialize PORTA by
; clearing output
; data latches
; Alternate method
; to clear output
; data latches
CLRF
Q
D
MOVLW
MOVWF
MOVLW
; Configure A/D
EN
ADCON1 ; for digital inputs
RD PORT
0CFh
; Value used to
; initialize data
; direction
Note 1: I/O pins have diode protection to VDD and VSS.
MOVWF
TRISA
; Set RA<3:0> as inputs
; RA<5:4> as outputs
9.1
PORTA, TRISA and LATA Registers
PORTA is an 8-bit wide, bidirectional port. The
corresponding Data Direction register is TRISA. Setting
a TRISA bit (= 1) will make the corresponding PORTA
pin an input (i.e., put the corresponding output driver in
a high-impedance mode). Clearing a TRISA bit (= 0)
will make the corresponding PORTA pin an output (i.e.,
put the contents of the output latch on the selected pin).
© 2008 Microchip Technology Inc.
DS39760D-page 99
PIC18F2450/4450
TABLE 9-1:
Pin
PORTA I/O SUMMARY
TRIS
Function
I/O
I/O Type
Description
Setting
RA0/AN0
RA0
0
1
1
OUT
IN
DIG
TTL
ANA
LATA<0> data output; not affected by analog input.
PORTA<0> data input; disabled when analog input enabled.
AN0
RA1
IN
A/D input channel 0. Default configuration on POR; does not affect
digital output.
RA1/AN1
0
1
1
OUT
IN
DIG
TTL
ANA
LATA<1> data output; not affected by analog input.
PORTA<1> data input; reads ‘0’ on POR.
AN1
RA2
IN
A/D input channel 1. Default configuration on POR; does not affect
digital output.
RA2/AN2/
VREF-
0
1
1
OUT
IN
DIG
TTL
ANA
LATA<2> data output; not affected by analog input.
PORTA<2> data input. Disabled when analog functions enabled.
AN2
IN
A/D input channel 2. Default configuration on POR; not affected by
analog output.
VREF-
RA3
1
0
1
1
1
0
1
1
x
0
1
1
1
x
x
IN
OUT
IN
ANA
DIG
TTL
ANA
ANA
DIG
ST
A/D voltage reference low input.
RA3/AN3/
VREF+
LATA<3> data output; not affected by analog input.
PORTA<3> data input; disabled when analog input enabled.
A/D input channel 3. Default configuration on POR.
A/D voltage reference high input.
AN3
VREF+
RA4
IN
IN
RA4/T0CKI/
RCV
OUT
IN
LATA<4> data output; not affected by analog input.
PORTA<4> data input; disabled when analog input enabled.
Timer0 clock input.
T0CKI
RCV
RA5
IN
ST
IN
TTL
DIG
TTL
ANA
ANA
ANA
DIG
External USB transceiver RCV input.
RA5/AN4/
HLVDIN
OUT
IN
LATA<5> data output; not affected by analog input.
PORTA<5> data input; disabled when analog input enabled.
A/D input channel 4. Default configuration on POR.
High/Low-Voltage Detect external trip point input.
Main oscillator feedback output connection (all XT and HS modes).
AN4
HLVDIN
OSC2
CLKO
IN
IN
OSC2/CLKO/
RA6
OUT
OUT
System cycle clock output (FOSC/4); available in EC, ECPLL and
INTCKO modes.
RA6
0
1
OUT
IN
DIG
TTL
LATA<6> data output. Available only in ECIO, ECPIO and INTIO
modes; otherwise, reads as ‘0’.
PORTA<6> data input. Available only in ECIO, ECPIO and INTIO
modes; otherwise, reads as ‘0’.
Legend:
OUT = Output, IN = Input, ANA = Analog Signal, DIG = Digital Output, ST = Schmitt Buffer Input,
TTL = TTL Buffer Input, x= Don’t care (TRIS bit does not affect port direction or is overridden for this option)
TABLE 9-2:
Name
SUMMARY OF REGISTERS ASSOCIATED WITH PORTA
Reset
Values
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
on Page:
PORTA
LATA
—
—
—
—
—
RA6(1)
LATA6(1)
TRISA6(1) TRISA5
RA5
RA4
RA3
RA2
RA1
RA0
LATA0
TRISA0
PCFG0
—
51
51
51
50
52
LATA5
LATA4
LATA3
TRISA3
PCFG3
LATA2
TRISA2
PCFG2
LATA1
TRISA1
PCFG1
TRISA
ADCON1
UCON
TRISA4
VCFG0
PKTDIS
—
VCFG1
SE0
PPBRST
USBEN RESUME SUSPND
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PORTA.
Note 1: RA6 and its associated latch and data direction bits are enabled as I/O pins based on oscillator
configuration; otherwise, they are read as ‘0’.
DS39760D-page 100
© 2008 Microchip Technology Inc.
PIC18F2450/4450
A mismatch condition will continue to set flag bit, RBIF.
Reading PORTB will end the mismatch condition and
allow flag bit, RBIF, to be cleared.
9.2
PORTB, TRISB and LATB
Registers
PORTB is an 8-bit wide, bidirectional port. The
corresponding Data Direction register is TRISB. Setting
a TRISB bit (= 1) will make the corresponding PORTB
pin an input (i.e., put the corresponding output driver in
a high-impedance mode). Clearing a TRISB bit (= 0)
will make the corresponding PORTB pin an output (i.e.,
put the contents of the output latch on the selected pin).
The interrupt-on-change feature is recommended for
wake-up on key depression operation and operations
where PORTB is only used for the interrupt-on-change
feature. Polling of PORTB is not recommended while
using the interrupt-on-change feature.
Pins, RB2 and RB3, are multiplexed with the USB
peripheral and serve as the differential signal outputs
for an external USB transceiver (TRIS configuration).
Refer to Section 14.2.2.2 “External Transceiver” for
additional information on configuring the USB module
for operation with an external transceiver.
The Output Latch register (LATB) is also memory
mapped. Read-modify-write operations on the LATB
register read and write the latched output value for
PORTB.
Each of the PORTB pins has a weak internal pull-up. A
single control bit can turn on all the pull-ups. This is
performed by clearing bit, RBPU (INTCON2<7>). The
weak pull-up is automatically turned off when the port
pin is configured as an output. The pull-ups are
disabled on a Power-on Reset.
EXAMPLE 9-2:
INITIALIZING PORTB
CLRF
PORTB
LATB
0Eh
; Initialize PORTB by
; clearing output
; data latches
; Alternate method
; to clear output
; data latches
CLRF
Note:
On a Power-on Reset, RB4:RB0 are
configured as analog inputs by default and
read as ‘0’; RB7:RB5 are configured as
digital inputs.
MOVLW
MOVWF
; Set RB<4:0> as
ADCON1 ; digital I/O pins
; (required if config bit
; PBADEN is set)
; Value used to
; initialize data
; direction
; Set RB<3:0> as inputs
; RB<5:4> as outputs
; RB<7:6> as inputs
By programming the Configuration bit,
PBADEN (CONFIG3H<1>), RB4:RB0 will
alternatively be configured as digital inputs
on POR.
MOVLW
MOVWF
0CFh
TRISB
Four of the PORTB pins (RB7:RB4) have an interrupt-
on-change feature. Only pins configured as inputs can
cause this interrupt to occur. Any RB7:RB4 pin
configured as an output is excluded from the interrupt-
on-change comparison. The pins are compared with
the old value latched on the last read of PORTB. The
“mismatch” outputs of RB7:RB4 are ORed together to
generate the RB Port Change Interrupt with Flag bit,
RBIF (INTCON<0>).
The interrupt-on-change can be used to wake the
device from Sleep. The user, in the Interrupt Service
Routine, can clear the interrupt in the following manner:
a) Any read or write of PORTB (except with the
MOVFF (ANY), PORTB instruction). This will
end the mismatch condition.
b) Wait one or more instruction cycles.
c) Clear flag bit, RBIF.
© 2008 Microchip Technology Inc.
DS39760D-page 101
PIC18F2450/4450
TABLE 9-3:
PORTB I/O SUMMARY
TRIS
Setting
Pin
Function
I/O
I/O Type
Description
RB0/AN12/
INT0
RB0
0
1
OUT
IN
DIG
TTL
LATB<0> data output; not affected by analog input.
PORTB<0> data input; weak pull-up when RBPU bit is cleared.
(1)
Disabled when analog input enabled.
(1)
AN12
INT0
RB1
1
1
0
1
IN
IN
ANA
ST
A/D input channel 12.
External interrupt 0 input.
RB1/AN10/
INT1
OUT
IN
DIG
TTL
LATB<1> data output; not affected by analog input.
PORTB<1> data input; weak pull-up when RBPU bit is cleared.
Disabled when analog input enabled.
(1)
(1)
AN10
INT1
RB2
1
1
0
1
IN
IN
ANA
ST
A/D input channel 10.
External interrupt 1 input.
RB2/AN8/
INT2/VMO
OUT
IN
DIG
TTL
LATB<2> data output; not affected by analog input.
PORTB<2> data input; weak pull-up when RBPU bit is cleared.
Disabled when analog input enabled.
(1)
(1)
AN8
INT2
VMO
RB3
1
1
0
0
1
IN
IN
ANA
ST
A/D input channel 8.
External interrupt 2 input.
OUT
OUT
IN
DIG
DIG
TTL
External USB transceiver VMO data output.
LATB<3> data output; not affected by analog input.
PORTB<3> data input; weak pull-up when RBPU bit is cleared.
RB3/AN9/VPO
(1)
Disabled when analog input enabled.
(1)
AN9
VPO
RB4
1
0
0
1
IN
OUT
OUT
IN
ANA
DIG
DIG
TTL
A/D input channel 9.
External USB transceiver VPO data output.
RB4/AN11/
KBI0
LATB<4> data output; not affected by analog input.
PORTB<4> data input; weak pull-up when RBPU bit is cleared.
Disabled when analog input enabled.
(1)
(1)
AN11
KBI0
RB5
1
1
0
1
1
x
IN
IN
ANA
TTL
DIG
TTL
TTL
ST
A/D input channel 11.
Interrupt-on-pin change.
RB5/KBI1/
PGM
OUT
IN
LATB<5> data output.
PORTB<5> data input; weak pull-up when RBPU bit is cleared.
Interrupt-on-pin change.
KBI1
PGM
IN
IN
Single-Supply Programming mode entry (ICSP™). Enabled by LVP
Configuration bit; all other pin functions disabled.
RB6/KBI2/
PGC
RB6
0
1
1
x
0
1
1
x
x
OUT
IN
DIG
TTL
TTL
ST
LATB<6> data output.
PORTB<6> data input; weak pull-up when RBPU bit is cleared.
Interrupt-on-pin change.
KBI2
PGC
RB7
IN
(2)
IN
Serial execution (ICSP) clock input for ICSP and ICD operation.
RB7/KBI3/
PGD
OUT
IN
DIG
TTL
TTL
DIG
ST
LATB<7> data output.
PORTB<7> data input; weak pull-up when RBPU bit is cleared.
Interrupt-on-pin change.
KBI3
PGD
IN
(2)
OUT
IN
Serial execution data output for ICSP and ICD operation.
(2)
Serial execution data input for ICSP and ICD operation.
Legend:
OUT = Output, IN = Input, ANA = Analog Signal, DIG = Digital Output, ST = Schmitt Buffer Input,
TTL = TTL Buffer Input, x= Don’t care (TRIS bit does not affect port direction or is overridden for this option)
Note 1: Configuration on POR is determined by PBADEN Configuration bit. Pins are configured as analog inputs when
PBADEN is set and digital inputs when PBADEN is cleared.
2: All other pin functions are disabled when ICSP™ or ICD operation is enabled.
DS39760D-page 102
© 2008 Microchip Technology Inc.
PIC18F2450/4450
TABLE 9-4:
Name
SUMMARY OF REGISTERS ASSOCIATED WITH PORTB
Reset
Values
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
on Page:
PORTB
LATB
RB7
RB6
RB5
RB4
RB3
RB2
RB1
RB0
51
51
51
49
49
49
50
52
LATB7
TRISB7
LATB6
TRISB6
LATB5
TRISB5
LATB4
TRISB4
INT0IE
LATB3
LATB2
LATB1
LATB0
TRISB
TRISB3 TRISB2 TRISB1 TRISB0
INTCON
INTCON2
INTCON3
ADCON1
UCON
GIE/GIEH PEIE/GIEL TMR0IE
RBIE
—
TMR0IF
TMR0IP
—
INT0IF
—
RBIF
RBIP
INT1IF
PCFG0
—
RBPU
INT2IP
—
INTEDG0 INTEDG1 INTEDG2
INT1IP
—
—
INT2IE
VCFG0
PKTDIS
INT1IE
PCFG3
INT2IF
PCFG1
VCFG1
SE0
PCFG2
—
PPBRST
USBEN RESUME SUSPND
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PORTB.
© 2008 Microchip Technology Inc.
DS39760D-page 103
PIC18F2450/4450
When enabling peripheral functions on PORTC pins
other than RC4 and RC5, care should be taken in
defining the TRIS bits. Some peripherals override the
TRIS bit to make a pin an output, while other
peripherals override the TRIS bit to make a pin an
input. The user should refer to the corresponding
peripheral section for the correct TRIS bit settings.
9.3
PORTC, TRISC and LATC
Registers
PORTC is
a 7-bit wide, bidirectional port. The
corresponding Data Direction register is TRISC.
Setting a TRISC bit (= 1) will make the corresponding
PORTC pin an input (i.e., put the corresponding output
driver in a high-impedance mode). Clearing a TRISC
bit (= 0) will make the corresponding PORTC pin an
output (i.e., put the contents of the output latch on the
selected pin).
Note:
On a Power-on Reset, these pins, except
RC4 and RC5, are configured as digital
inputs. To use pins RC4 and RC5 as
digital inputs, the USB module must be
disabled (UCON<3> = 0) and the on-chip
USB transceiver must be disabled
(UCFG<3> = 1).
In PIC18F2450/4450 devices, the RC3 pin is not
implemented.
The Output Latch register (LATC) is also memory
mapped. Read-modify-write operations on the LATC
register read and write the latched output value for
PORTC.
The contents of the TRISC register are affected by
peripheral overrides. Reading TRISC always returns
the current contents, even though a peripheral device
may be overriding one or more of the pins.
PORTC is primarily multiplexed with serial
communication modules, including the EUSART and
the USB module (Table 9-5). Except for RC4 and RC5,
PORTC uses Schmitt Trigger input buffers.
EXAMPLE 9-3:
INITIALIZING PORTC
CLRF
PORTC
LATC
07h
; Initialize PORTC by
; clearing output
; data latches
; Alternate method
; to clear output
; data latches
; Value used to
; initialize data
; direction
Pins RC4 and RC5 are multiplexed with the USB
module. Depending on the configuration of the module,
they can serve as the differential data lines for the on-
chip USB transceiver, or the data inputs from an
external USB transceiver. Both RC4 and RC5 have
TTL input buffers instead of the Schmitt Trigger buffers
on the other pins.
CLRF
MOVLW
MOVWF
Unlike other PORTC pins, RC4 and RC5 do not have
TRISC bits associated with them. As digital ports, they
can only function as digital inputs. When configured for
USB operation, the data direction is determined by the
configuration and status of the USB module at a given
time. If an external transceiver is used, RC4 and RC5
always function as inputs from the transceiver. If the
on-chip transceiver is used, the data direction is
determined by the operation being performed by the
module at that time.
TRISC
; RC<5:0> as outputs
; RC<7:6> as inputs
When the external transceiver is enabled, RC2 also
serves as the output enable control to the transceiver.
Additional information on configuring USB options is
provided in Section 14.2.2.2 “External Transceiver”.
DS39760D-page 104
© 2008 Microchip Technology Inc.
PIC18F2450/4450
TABLE 9-5:
PORTC I/O SUMMARY
TRIS
Setting
Pin
Function
I/O
I/O Type
Description
RC0/T1OSO/
T1CKI
RC0
0
1
x
OUT
IN
DIG
ST
LATC<0> data output.
PORTC<0> data input.
T1OSO
OUT
ANA
Timer1 oscillator output; enabled when Timer1 oscillator enabled.
Disables digital I/O.
T1CKI
RC1
1
0
1
x
IN
OUT
IN
ST
DIG
ST
Timer1 counter input.
LATC<1> data output.
PORTC<1> data input.
RC1/T1OSI/
UOE
T1OSI
IN
ANA
Timer1 oscillator input; enabled when Timer1 oscillator enabled.
Disables digital I/O.
UOE
RC2
0
0
1
0
1
OUT
OUT
IN
DIG
DIG
ST
External USB transceiver OE output.
LATC<2> data output.
RC2/CCP1
RC4/D-/VM
PORTC<2> data input.
CCP1
OUT
IN
DIG
ST
CCP1 Compare and PWM output; takes priority over port data.
CCP1 Capture input.
(1)
RC4
D-
—
IN
TTL
PORTC<4> data input; disabled when USB module or on-chip
transceiver is enabled.
(1)
—
OUT
IN
XCVR USB bus differential minus line output (internal transceiver).
XCVR USB bus differential minus line input (internal transceiver).
(1)
—
(1)
VM
—
IN
TTL
TTL
External USB transceiver VM input.
(1)
RC5/D+/VP
RC6/TX/CK
RC5
—
IN
PORTC<5> data input; disabled when USB module or on-chip
transceiver is enabled.
(1)
D+
—
OUT
IN
XCVR USB bus differential plus line output (internal transceiver).
XCVR USB bus differential plus line input (internal transceiver).
(1)
—
(1)
VP
—
IN
TTL
DIG
ST
External USB transceiver VP input.
LATC<6> data output.
RC6
0
1
0
OUT
IN
PORTC<6> data input.
TX
CK
OUT
DIG
Asynchronous serial transmit data output (EUSART module); takes
priority over port data. User must configure as output.
0
OUT
DIG
Synchronous serial clock output (EUSART module); takes priority
over port data.
1
0
1
1
1
1
IN
OUT
IN
ST
DIG
ST
Synchronous serial clock input (EUSART module).
LATC<7> data output.
RC7/RX/DT
RC7
PORTC<7> data input.
RX
DT
IN
ST
Asynchronous serial receive data input (EUSART module).
Synchronous serial data output (EUSART module).
OUT
IN
DIG
ST
Synchronous serial data input (EUSART module). User must
configure as an input.
Legend:
OUT = Output, IN = Input, ANA = Analog Signal, DIG = Digital Output, ST = Schmitt Buffer Input,
TTL = TTL Buffer Input, XCVR = USB Transceiver, x= Don’t care (TRIS bit does not affect port direction or is
overridden for this option)
Note 1: RC4 and RC5 do not have corresponding TRISC bits. In Port mode, these pins are input only. USB data direction is
determined by the USB configuration.
© 2008 Microchip Technology Inc.
DS39760D-page 105
PIC18F2450/4450
TABLE 9-6:
SUMMARY OF REGISTERS ASSOCIATED WITH PORTC
Reset
Values
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
on Page:
PORTC
LATC
RC7
RC6
RC5(1)
—
RC4(1)
—
—
—
—
RC2
RC1
RC0
51
51
51
52
LATC7
LATC6
LATC2
LATC1
LATC0
TRISC
UCON
TRISC7 TRISC6
PPBRST
—
—
TRISC2 TRISC1 TRISC0
—
SE0
PKTDIS USBEN RESUME SUSPND
—
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PORTC.
Note 1: RC5 and RC4 are only available as port pins when the USB module is disabled (UCON<3> = 0).
DS39760D-page 106
© 2008 Microchip Technology Inc.
PIC18F2450/4450
EXAMPLE 9-4:
INITIALIZING PORTD
9.4
PORTD, TRISD and LATD
Registers
CLRF
PORTD
; Initialize PORTD by
; clearing output
; data latches
; Alternate method
; to clear output
; data latches
; Value used to
; initialize data
; direction
Note:
PORTD is only available on 40/44-pin
devices.
CLRF
LATD
PORTD is an 8-bit wide, bidirectional port. The
corresponding Data Direction register is TRISD.
Setting a TRISD bit (= 1) will make the corresponding
PORTD pin an input (i.e., put the corresponding output
driver in a high-impedance mode). Clearing a TRISD
bit (= 0) will make the corresponding PORTD pin an
output (i.e., put the contents of the output latch on the
selected pin).
MOVLW
MOVWF
0CFh
TRISD
; Set RD<3:0> as inputs
; RD<5:4> as outputs
; RD<7:6> as inputs
The Output Latch register (LATD) is also memory
mapped. Read-modify-write operations on the LATD
register read and write the latched output value for
PORTD.
All pins on PORTD are implemented with Schmitt
Trigger input buffers. Each pin is individually
configurable as an input or output.
Note:
On a Power-on Reset, these pins are
configured as digital inputs.
© 2008 Microchip Technology Inc.
DS39760D-page 107
PIC18F2450/4450
TABLE 9-7:
PORTD I/O SUMMARY
TRIS
Setting
Pin
Function
I/O
I/O Type
Description
RD0
RD0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
OUT
IN
DIG
ST
LATD<0> data output.
PORTD<0> data input.
LATD<1> data output.
PORTD<1> data input.
LATD<2> data output.
PORTD<2> data input.
LATD<3> data output.
PORTD<3> data input.
LATD<4> data output.
PORTD<4> data input.
LATD<5> data output
PORTD<5> data input
LATD<6> data output.
PORTD<6> data input.
LATD<7> data output.
PORTD<7> data input.
RD1
RD2
RD3
RD4
RD5
RD6
RD7
RD1
RD2
RD3
RD4
RD5
RD6
RD7
OUT
IN
DIG
ST
OUT
IN
DIG
ST
OUT
IN
DIG
ST
OUT
IN
DIG
ST
OUT
IN
DIG
ST
OUT
IN
DIG
ST
OUT
IN
DIG
ST
Legend:
OUT = Output, IN = Input, DIG = Digital Output, ST = Schmitt Buffer Input
TABLE 9-8:
Name
SUMMARY OF REGISTERS ASSOCIATED WITH PORTD
Reset
Values
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
on Page:
PORTD(1)
LATD(1)
TRISD(1)
RD7
RD6
RD5
RD4
RD3
RD2
RD1
RD0
51
51
51
LATD7
TRISD7
LATD6
TRISD6
LATD5
TRISD5
LATD4
TRISD4
LATD3
TRISD3
LATD2
TRISD2
LATD1
TRISD1
LATD0
TRISD0
Note 1: These registers and/or bits are unimplemented on 28-pin devices.
DS39760D-page 108
© 2008 Microchip Technology Inc.
PIC18F2450/4450
functions as a digital input only pin; as such, it does not
have TRIS or LAT bits associated with its operation.
Otherwise, it functions as the device’s Master Clear input.
In either configuration, RE3 also functions as the
programming voltage input during programming.
9.5
PORTE, TRISE and LATE
Registers
Depending on the particular PIC18F2450/4450 device
selected, PORTE is implemented in two different ways.
For 40/44-pin devices, PORTE is a 4-bit wide port.
Three pins (RE0/AN5, RE1/AN6 and RE2/AN7) are
individually configurable as inputs or outputs. These
pins have Schmitt Trigger input buffers. When selected
as an analog input, these pins will read as ‘0’s.
Note:
On a Power-on Reset, RE3 is enabled as
digital input only if Master Clear
functionality is disabled.
a
EXAMPLE 9-5:
INITIALIZING PORTE
The corresponding Data Direction register is TRISE.
Setting a TRISE bit (= 1) will make the corresponding
PORTE pin an input (i.e., put the corresponding output
driver in a high-impedance mode). Clearing a TRISE bit
(= 0) will make the corresponding PORTE pin an output
(i.e., put the contents of the output latch on the selected
pin).
CLRF
PORTE
LATE
0Ah
; Initialize PORTE by
; clearing output
; data latches
; Alternate method
; to clear output
; data latches
CLRF
MOVLW
MOVWF
MOVLW
; Configure A/D
ADCON1 ; for digital inputs
03h
TRISE controls the direction of the RE pins, even when
they are being used as analog inputs. The user must
make sure to keep the pins configured as inputs when
using them as analog inputs.
; Value used to
; initialize data
; direction
; Set RE<0> as inputs
; RE<1> as inputs
; RE<2> as outputs
MOVWF
TRISC
Note:
On a Power-on Reset, RE2:RE0 are
configured as analog inputs.
9.5.1
PORTE IN 28-PIN DEVICES
The Output Latch register (LATE) is also memory
mapped. Read-modify-write operations on the LATE
register read and write the latched output value for
PORTE.
For 28-pin devices, PORTE is only available when
Master Clear functionality is disabled (MCLRE = 0). In
these cases, PORTE is a single bit, input only port
comprised of RE3 only. The pin operates as previously
described.
The fourth pin of PORTE (MCLR/VPP/RE3) is an input
only pin. Its operation is controlled by the MCLRE Config-
uration bit. When selected as a port pin (MCLRE = 0), it
REGISTER 9-1:
PORTE REGISTER
U-0
—
U-0
U-0
—
U-0
—
R/W-x
RE3(1,2)
R/W-0
RE2(3)
R/W-0
RE1(3)
R/W-0
RE0(3)
—
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7-4
bit 3-0
Unimplemented: Read as ‘0’
RE3:RE0: PORTE Data Input bits(1,2,3)
Note 1: implemented only when Master Clear functionality is disabled (MCLRE Configuration bit = 0); otherwise,
read as ‘0’.
2: RE3 is the only PORTE bit implemented on both 28-pin and 40/44-pin devices. All other bits are
implemented only when PORTE is implemented (i.e., 40/44-pin devices).
3: Unimplemented in 28-pin devices; read as ‘0’.
© 2008 Microchip Technology Inc.
DS39760D-page 109
PIC18F2450/4450
TABLE 9-9:
Pin
PORTE I/O SUMMARY
TRIS
Function
I/O
I/O Type
Description
Setting
RE0/AN5
RE0
0
1
1
0
1
1
0
1
1
OUT
IN
DIG
ST
LATE<0> data output; not affected by analog input.
PORTE<0> data input; disabled when analog input enabled.
A/D input channel 5; default configuration on POR.
LATE<1> data output; not affected by analog input.
PORTE<1> data input; disabled when analog input enabled.
A/D input channel 6; default configuration on POR.
LATE<2> data output; not affected by analog input.
PORTE<2> data input; disabled when analog input enabled.
A/D input channel 7; default configuration on POR.
AN5
RE1
IN
ANA
DIG
ST
RE1/AN6
RE2/AN7
OUT
IN
AN6
RE2
IN
ANA
DIG
ST
OUT
IN
AN7
IN
ANA
ST
(1)
MCLR/VPP/
RE3
MCLR
—
IN
External Master Clear input; enabled when MCLRE Configuration bit
is set.
(1)
VPP
—
IN
IN
ANA
ST
High-voltage detection, used for ICSP™ mode entry detection.
Always available regardless of pin mode.
(1)
RE3
—
PORTE<3> data input; enabled when MCLRE Configuration bit
is clear.
Legend:
OUT = Output, IN = Input, ANA = Analog Signal, DIG = Digital Output, ST = Schmitt Buffer Input.
Note 1: RE3 does not have a corresponding TRISE<3> bit. This pin is always an input regardless of mode.
TABLE 9-10: SUMMARY OF REGISTERS ASSOCIATED WITH PORTE
Reset
Values
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
on Page:
PORTE
LATE(3)
TRISE(3)
ADCON1
—
—
—
—
—
—
—
—
—
—
—
—
RE3(1,2)
—
RE2(3)
LATE2
TRISE2
PCFG2
RE1(3)
LATE1
TRISE1
PCFG1
RE0(3)
LATE0
TRISE0
PCFG0
51
51
51
50
—
—
—
VCFG1
VCFG0
PCFG3
Legend: — = unimplemented, read as ‘0’
Note 1: Implemented only when Master Clear functionality is disabled (MCLRE Configuration bit = 0); otherwise,
read as ‘0’.
2: RE3 is the only PORTE bit implemented on both 28-pin and 40/44-pin devices. All other bits are
implemented only when PORTE is implemented (i.e., 40/44-pin devices).
3: These registers and/or bits are unimplemented on 28-pin devices.
DS39760D-page 110
© 2008 Microchip Technology Inc.
PIC18F2450/4450
The T0CON register (Register 10-1) controls all
aspects of the module’s operation, including the
prescale selection. It is both readable and writable.
10.0 TIMER0 MODULE
The Timer0 module incorporates the following features:
• Software selectable operation as a timer or
counter in both 8-bit or 16-bit modes
A simplified block diagram of the Timer0 module in 8-bit
mode is shown in Figure 10-1. Figure 10-2 shows a sim-
plified block diagram of the Timer0 module in 16-bit
mode.
• Readable and writable registers
• Dedicated 8-bit, software programmable
prescaler
• Selectable clock source (internal or external)
• Edge select for external clock
• Interrupt on overflow
REGISTER 10-1: T0CON: TIMER0 CONTROL REGISTER
R/W-1
R/W-1
R/W-1
T0CS
R/W-1
T0SE
R/W-1
PSA
R/W-1
T0PS2
R/W-1
T0PS1
R/W-1
T0PS0
TMR0ON
T08BIT
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2-0
TMR0ON: Timer0 On/Off Control bit
1= Enables Timer0
0= Stops Timer0
T08BIT: Timer0 8-Bit/16-Bit Control bit
1= Timer0 is configured as an 8-bit timer/counter
0= Timer0 is configured as a 16-bit timer/counter
T0CS: Timer0 Clock Source Select bit
1= Transition on T0CKI pin
0= Internal instruction cycle clock (CLKO)
T0SE: Timer0 Source Edge Select bit
1= Increment on high-to-low transition on T0CKI pin
0= Increment on low-to-high transition on T0CKI pin
PSA: Timer0 Prescaler Assignment bit
1= TImer0 prescaler is not assigned. Timer0 clock input bypasses prescaler.
0= Timer0 prescaler is assigned. Timer0 clock input comes from prescaler output.
T0PS2:T0PS0: Timer0 Prescaler Select bits
111= 1:256 Prescale value
110= 1:128 Prescale value
101= 1:64 Prescale value
100= 1:32 Prescale value
011= 1:16 Prescale value
010= 1:8 Prescale value
001= 1:4 Prescale value
000= 1:2 Prescale value
© 2008 Microchip Technology Inc.
DS39760D-page 111
PIC18F2450/4450
internal phase clock (TOSC). There is a delay between
synchronization and the onset of incrementing the
timer/counter.
10.1 Timer0 Operation
Timer0 can operate as either a timer or a counter; the
mode is selected by clearing the T0CS bit
(T0CON<5>). In Timer mode, the module increments
on every clock by default unless a different prescaler
value is selected (see Section 10.3 “Prescaler”). If
the TMR0 register is written to, the increment is
inhibited for the following two instruction cycles. The
user can work around this by writing an adjusted value
to the TMR0 register.
10.2 Timer0 Reads and Writes in
16-Bit Mode
TMR0H is not the actual high byte of Timer0 in 16-bit
mode; it is actually a buffered version of the real high
byte of Timer0, which is not directly readable nor
writable (refer to Figure 10-2). TMR0H is updated with
the contents of the high byte of Timer0 during a read of
TMR0L. This provides the ability to read all 16 bits of
Timer0 without having to verify that the read of the high
and low byte were valid, due to a rollover between
successive reads of the high and low byte.
The Counter mode is selected by setting the T0CS bit
(= 1). In Counter mode, Timer0 increments either on
every rising or falling edge of pin RA4/T0CKI. The
incrementing edge is determined by the Timer0 Source
Edge Select bit, T0SE (T0CON<4>); clearing this bit
selects the rising edge. Restrictions on the external
clock input are discussed below.
Similarly, a write to the high byte of Timer0 must also
take place through the TMR0H Buffer register. The high
byte is updated with the contents of TMR0H when a
write occurs to TMR0L. This allows all 16 bits of Timer0
to be updated at once.
An external clock source can be used to drive Timer0;
however, it must meet certain requirements to ensure
that the external clock can be synchronized with the
FIGURE 10-1:
TIMER0 BLOCK DIAGRAM (8-BIT MODE)
FOSC/4
0
1
1
0
Set
TMR0IF
on Overflow
Sync with
Internal
Clocks
TMR0L
8
Programmable
Prescaler
T0CKI pin
(2 TCY Delay)
T0SE
T0CS
3
T0PS2:T0PS0
PSA
8
Internal Data Bus
Note: Upon Reset, Timer0 is enabled in 8-bit mode with clock input from T0CKI maximum prescale.
FIGURE 10-2:
TIMER0 BLOCK DIAGRAM (16-BIT MODE)
FOSC/4
0
1
Sync with
Internal
Clocks
Set
TMR0
High Byte
1
TMR0L
TMR0IF
on Overflow
Programmable
Prescaler
T0CKI pin
0
8
(2 TCY Delay)
T0SE
T0CS
3
Read TMR0L
Write TMR0L
T0PS2:T0PS0
PSA
8
8
TMR0H
8
8
Internal Data Bus
Note: Upon Reset, Timer0 is enabled in 8-bit mode with clock input from T0CKI maximum prescale.
DS39760D-page 112
© 2008 Microchip Technology Inc.
PIC18F2450/4450
10.3.1
SWITCHING PRESCALER
ASSIGNMENT
10.3 Prescaler
An 8-bit counter is available as a prescaler for the Timer0
module. The prescaler is not directly readable or writable;
its value is set by the PSA and T0PS2:T0PS0 bits
(T0CON<3:0>) which determine the prescaler
assignment and prescale ratio.
The prescaler assignment is fully under software
control and can be changed “on-the-fly” during program
execution.
10.4 Timer0 Interrupt
Clearing the PSA bit assigns the prescaler to the
Timer0 module. When it is assigned, prescale values
from 1:2 through 1:256, in power-of-2 increments, are
selectable.
The TMR0 interrupt is generated when the TMR0
register overflows from FFh to 00h in 8-bit mode, or
from FFFFh to 0000h in 16-bit mode. This overflow sets
the TMR0IF flag bit. The interrupt can be masked by
clearing the TMR0IE bit (INTCON<5>). Before re-
enabling the interrupt, the TMR0IF bit must be cleared
in software by the Interrupt Service Routine.
When assigned to the Timer0 module, all instructions
writing to the TMR0 register (e.g., CLRF TMR0, MOVWF
TMR0, BSF TMR0,etc.) clear the prescaler count.
Note:
Writing to TMR0 when the prescaler is
assigned to Timer0 will clear the prescaler
count but will not change the prescaler
assignment.
Since Timer0 is shut down in Sleep mode, the TMR0
interrupt cannot awaken the processor from Sleep.
TABLE 10-1: REGISTERS ASSOCIATED WITH TIMER0
Reset
Values
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
on Page:
TMR0L
Timer0 Register Low Byte
Timer0 Register High Byte
50
50
49
50
51
TMR0H
INTCON
T0CON
TRISA
GIE/GIEH PEIE/GIEL TMR0IE
INT0IE
T0SE
RBIE
PSA
TMR0IF
T0PS2
INT0IF
T0PS1
TRISA1
RBIF
T0PS0
TRISA0
TMR0ON
—
T08BIT
TRISA6(1) TRISA5
T0CS
TRISA4
TRISA3
TRISA2
Legend: — = unimplemented locations, read as ‘0’. Shaded cells are not used by Timer0.
Note 1: RA6 is configured as a port pin based on various primary oscillator modes. When the port pin is disabled,
all of the associated bits read ‘0’.
© 2008 Microchip Technology Inc.
DS39760D-page 113
PIC18F2450/4450
NOTES:
DS39760D-page 114
© 2008 Microchip Technology Inc.
PIC18F2450/4450
A simplified block diagram of the Timer1 module is
shown in Figure 11-1. A block diagram of the module’s
operation in Read/Write mode is shown in Figure 11-2.
11.0 TIMER1 MODULE
The Timer1 timer/counter module incorporates these
features:
The module incorporates its own low-power oscillator
to provide an additional clocking option. The Timer1
oscillator can also be used as a low-power clock source
for the microcontroller in power-managed operation.
• Software selectable operation as a 16-bit timer or
counter
• Readable and writable 8-bit registers (TMR1H
and TMR1L)
Timer1 can also be used to provide Real-Time Clock
(RTC) functionality to applications with only a minimal
addition of external components and code overhead.
• Selectable clock source (internal or external) with
device clock or Timer1 oscillator internal options
• Interrupt on overflow
Timer1 is controlled through the T1CON Control
register (Register 11-1). It also contains the Timer1
Oscillator Enable bit (T1OSCEN). Timer1 can be
enabled or disabled by setting or clearing control bit,
TMR1ON (T1CON<0>).
• Module Reset on CCP Special Event Trigger
• Device clock status flag (T1RUN)
REGISTER 11-1: T1CON: TIMER1 CONTROL REGISTER
R/W-0
RD16
R-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
T1RUN
T1CKPS1
T1CKPS0
T1OSCEN
T1SYNC
TMR1CS
TMR1ON
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7
RD16: 16-Bit Read/Write Mode Enable bit
1= Enables register read/write of Timer1 in one 16-bit operation
0= Enables register read/write of Timer1 in two 8-bit operations
bit 6
T1RUN: Timer1 System Clock Status bit
1= Device clock is derived from Timer1 oscillator
0= Device clock is derived from another source
bit 5-4
T1CKPS1:T1CKPS0: Timer1 Input Clock Prescale Select bits
11= 1:8 Prescale value
10= 1:4 Prescale value
01= 1:2 Prescale value
00= 1:1 Prescale value
bit 3
bit 2
T1OSCEN: Timer1 Oscillator Enable bit
1= Timer1 oscillator is enabled
0= Timer1 oscillator is shut off
The oscillator inverter and feedback resistor are turned off to eliminate power drain.
T1SYNC: Timer1 External Clock Input Synchronization Select bit
When TMR1CS = 1:
1= Do not synchronize external clock input
0= Synchronize external clock input
When TMR1CS = 0:
This bit is ignored. Timer1 uses the internal clock when TMR1CS = 0.
bit 1
bit 0
TMR1CS: Timer1 Clock Source Select bit
1= External clock from RC0/T1OSO/T1CKI pin (on the rising edge)
0= Internal clock (FOSC/4)
TMR1ON: Timer1 On bit
1= Enables Timer1
0= Stops Timer1
© 2008 Microchip Technology Inc.
DS39760D-page 115
PIC18F2450/4450
cycle (FOSC/4). When the bit is set, Timer1 increments
on every rising edge of the Timer1 external clock input
or the Timer1 oscillator, if enabled.
11.1 Timer1 Operation
Timer1 can operate in one of these modes:
• Timer
When Timer1 is enabled, the RC1/T1OSI/UOE and
RC0/T1OSO/T1CKI pins become inputs. This means
the values of TRISC<1:0> are ignored and the pins are
read as ‘0’.
• Synchronous Counter
• Asynchronous Counter
The operating mode is determined by the clock select
bit, TMR1CS (T1CON<1>). When TMR1CS is cleared
(= 0), Timer1 increments on every internal instruction
FIGURE 11-1:
TIMER1 BLOCK DIAGRAM
Timer1 Oscillator
On/Off
1
T1OSO/T1CKI
T1OSI
1
Synchronize
Prescaler
FOSC/4
Internal
Clock
0
Detect
1, 2, 4, 8
0
2
Sleep Input
T1OSCEN(1)
T1CKPS1:T1CKPS0
T1SYNC
Timer1
On/Off
TMR1CS
TMR1ON
Set
TMR1
High Byte
Clear TMR1
(CCP Special Event Trigger)
TMR1L
TMR1IF
on Overflow
Note 1: When enable bit, T1OSCEN, is cleared, the inverter and feedback resistor are turned off to eliminate power drain.
FIGURE 11-2:
TIMER1 BLOCK DIAGRAM (16-BIT READ/WRITE MODE)
Timer1 Oscillator
1
0
T1OSO/T1CKI
T1OSI
1
Synchronize
Prescaler
FOSC/4
Internal
Clock
Detect
1, 2, 4, 8
0
2
Sleep Input
T1OSCEN(1)
T1CKPS1:T1CKPS0
T1SYNC
Timer1
On/Off
TMR1CS
TMR1ON
Set
TMR1IF
on Overflow
TMR1
High Byte
Clear TMR1
(CCP Special Event Trigger)
TMR1L
8
Read TMR1L
Write TMR1L
8
8
TMR1H
8
8
Internal Data Bus
Note 1: When enable bit, T1OSCEN, is cleared, the inverter and feedback resistor are turned off to eliminate power drain.
DS39760D-page 116
© 2008 Microchip Technology Inc.
PIC18F2450/4450
TABLE 11-1: CAPACITOR SELECTION FOR
THETIMEROSCILLATOR(2,3,4)
11.2 Timer1 16-Bit Read/Write Mode
Timer1 can be configured for 16-bit reads and writes
(see Figure 11-2). When the RD16 control bit
(T1CON<7>) is set, the address for TMR1H is mapped
to a buffer register for the high byte of Timer1. A read
from TMR1L will load the contents of the high byte of
Timer1 into the Timer1 high byte buffer. This provides
the user with the ability to accurately read all 16 bits of
Timer1 without having to determine whether a read of
the high byte, followed by a read of the low byte, has
become invalid due to a rollover between reads.
Osc Type
Freq
C1
C2
LP
32 kHz
27 pF(1)
27 pF(1)
Note 1: Microchip suggests these values as a
starting point in validating the oscillator
circuit.
2: Higher capacitance increases the stability
of the oscillator but also increases the
start-up time.
A write to the high byte of Timer1 must also take place
through the TMR1H Buffer register. The Timer1 high
byte is updated with the contents of TMR1H when a
write occurs to TMR1L. This allows a user to write all
16 bits to both the high and low bytes of Timer1 at once.
3: Since each resonator/crystal has its own
characteristics, the user should consult
the resonator/crystal manufacturer for
appropriate
values
of
external
components.
The high byte of Timer1 is not directly readable or
writable in this mode. All reads and writes must take
place through the Timer1 High Byte Buffer register.
Writes to TMR1H do not clear the Timer1 prescaler.
The prescaler is only cleared on writes to TMR1L.
4: Capacitor values are for design guidance
only.
11.3.1
USING TIMER1 AS A CLOCK
SOURCE
The Timer1 oscillator is also available as a clock source
in power-managed modes. By setting the clock select
bits, SCS1:SCS0 (OSCCON<1:0>), to ‘01’, the device
switches to SEC_RUN mode. Both the CPU and
peripherals are clocked from the Timer1 oscillator. If the
IDLEN bit (OSCCON<7>) is cleared and a SLEEP
instruction is executed, the device enters SEC_IDLE
mode. Additional details are available in Section 3.0
“Power-Managed Modes”.
11.3 Timer1 Oscillator
An on-chip crystal oscillator circuit is incorporated
between pins T1OSI (input) and T1OSO (amplifier
output). It is enabled by setting the Timer1 Oscillator
Enable bit, T1OSCEN (T1CON<3>). The oscillator is a
low-power circuit rated for 32 kHz crystals. It will
continue to run during all power-managed modes. The
circuit for a typical LP oscillator is shown in Figure 11-3.
Table 11-1 shows the capacitor selection for the Timer1
oscillator.
Whenever the Timer1 oscillator is providing the clock
source, the Timer1 system clock status flag, T1RUN
(T1CON<6>), is set. This can be used to determine the
controller’s current clocking mode. It can also indicate
the clock source being currently used by the Fail-Safe
Clock Monitor. If the Clock Monitor is enabled and the
Timer1 oscillator fails while providing the clock, polling
the T1RUN bit will indicate whether the clock is being
provided by the Timer1 oscillator or another source.
The user must provide a software time delay to ensure
proper start-up of the Timer1 oscillator.
FIGURE 11-3:
EXTERNAL
COMPONENTS FOR THE
TIMER1 LP OSCILLATOR
C1
33 pF
PIC18FXXXX
11.3.2
LOW-POWER TIMER1 OPTION
T1OSI
The Timer1 oscillator can operate at two distinct levels
of power consumption based on device configuration.
When the LPT1OSC Configuration bit is set, the Timer1
oscillator operates in a low-power mode. When
LPT1OSC is not set, Timer1 operates at a higher power
level. Power consumption for a particular mode is
relatively constant, regardless of the device’s operating
mode. The default Timer1 configuration is the higher
power mode.
XTAL
32.768 kHz
T1OSO
C2
33 pF
Note:
See the Notes with Table 11-1 for additional
information about capacitor selection.
As the Low-Power Timer1 mode tends to be more
sensitive to interference, high noise environments may
cause some oscillator instability. The low-power option
is, therefore, best suited for low noise applications
where power conservation is an important design
consideration.
© 2008 Microchip Technology Inc.
DS39760D-page 117
PIC18F2450/4450
11.3.3
TIMER1 OSCILLATOR LAYOUT
CONSIDERATIONS
11.5 Resetting Timer1 Using the CCP
Special Event Trigger
The Timer1 oscillator circuit draws very little power
during operation. Due to the low-power nature of the
oscillator, it may also be sensitive to rapidly changing
signals in close proximity.
If the CCP module is configured in Compare mode
to
generate
a
Special
Event
Trigger
(CCP1M3:CCP1M0 = 1011), this signal will reset
Timer1. The trigger from CCP1 will also start an A/D
conversion if the A/D module is enabled (see
Section 13.3.4 “Special Event Trigger” for more
information).
The oscillator circuit, shown in Figure 11-3, should be
located as close as possible to the microcontroller.
There should be no circuits passing within the oscillator
circuit boundaries other than VSS or VDD.
The module must be configured as either a timer or a
synchronous counter to take advantage of this feature.
When used this way, the CCPRH:CCPRL register pair
effectively becomes a period register for Timer1.
If a high-speed circuit must be located near the oscilla-
tor (such as the CCP1 pin in Output Compare or PWM
mode, or the primary oscillator using the OSC2 pin), a
grounded guard ring around the oscillator circuit, as
shown in Figure 11-4, may be helpful when used on a
single-sided PCB or in addition to a ground plane.
If Timer1 is running in Asynchronous Counter mode,
this Reset operation may not work.
In the event that a write to Timer1 coincides with a
Special Event Trigger, the write operation will take
precedence.
FIGURE 11-4:
OSCILLATOR CIRCUIT
WITH GROUNDED
GUARD RING
Note:
The Special Event Triggers from the CCP1
module will not set the TMR1IF interrupt
flag bit (PIR1<0>).
VDD
VSS
11.6 Using Timer1 as a Real-Time
Clock
OSC1
OSC2
Adding an external LP oscillator to Timer1 (such as the
one described in Section 11.3 “Timer1 Oscillator”)
gives users the option to include RTC functionality to
their applications. This is accomplished with an
inexpensive watch crystal to provide an accurate time
base and several lines of application code to calculate
the time. When operating in Sleep mode and using a
battery or supercapacitor as a power source, it can
completely eliminate the need for a separate RTC
device and battery backup.
RC0
RC1
RC2
Note: Not drawn to scale.
The application code routine, RTCisr, shown in
Example 11-1, demonstrates a simple method to
increment a counter at one-second intervals using an
Interrupt Service Routine. Incrementing the TMR1
register pair to overflow triggers the interrupt and calls
the routine which increments the seconds counter by
one. Additional counters for minutes and hours are
incremented as the previous counter overflows.
11.4 Timer1 Interrupt
The TMR1 register pair (TMR1H:TMR1L) increments
from 0000h to FFFFh and rolls over to 0000h. The
Timer1 interrupt, if enabled, is generated on overflow
which is latched in interrupt flag bit, TMR1IF
(PIR1<0>). This interrupt can be enabled or disabled
by setting or clearing the Timer1 Interrupt Enable bit,
TMR1IE (PIE1<0>).
Since the register pair is 16 bits wide, counting up to
overflow the register directly from a 32.768 kHz clock
would take 2 seconds. To force the overflow at the
required one-second intervals, it is necessary to
preload it. The simplest method is to set the MSb of
TMR1H with a BSF instruction. Note that the TMR1L
register is never preloaded or altered; doing so may
introduce cumulative error over many cycles.
For this method to be accurate, Timer1 must operate in
Asynchronous mode and the Timer1 overflow interrupt
must be enabled (PIE1<0> = 1) as shown in the
routine, RTCinit. The Timer1 oscillator must also be
enabled and running at all times.
DS39760D-page 118
© 2008 Microchip Technology Inc.
PIC18F2450/4450
following a later Timer1 increment. This can be done by
monitoring TMR1L within the interrupt routine until it
increments, and then updating the TMR1H:TMR1L reg-
ister pair while the clock is low, or one-half of the period
of the clock source. Assuming that Timer1 is being
used as a Real-Time Clock, the clock source is a
32.768 kHz crystal oscillator. In this case, one-half
period of the clock is 15.25 μs.
11.7 Considerations in Asynchronous
Counter Mode
Following a Timer1 interrupt and an update to the
TMR1 registers, the Timer1 module uses a falling edge
on its clock source to trigger the next register update on
the rising edge. If the update is completed after the
clock input has fallen, the next rising edge will not be
counted.
The Real-Time Clock application code in Example 11-1
shows a typical ISR for Timer1, as well as the optional
code required if the update cannot be done reliably
within the required interval.
If the application can reliably update TMR1 before the
timer input goes low, no additional action is needed.
Otherwise, an adjusted update can be performed
EXAMPLE 11-1:
IMPLEMENTING A REAL-TIME CLOCK USING A TIMER1 INTERRUPT SERVICE
RTCinit
MOVLW
MOVWF
CLRF
80h
TMR1H
TMR1L
; Preload TMR1 register pair
; for 1 second overflow
MOVLW
MOVWF
CLRF
b’00001111’
T1CON
secs
; Configure for external clock,
; Asynchronous operation, external oscillator
; Initialize timekeeping registers
;
CLRF
mins
MOVLW
MOVWF
BSF
.12
hours
PIE1, TMR1IE
; Enable Timer1 interrupt
RETURN
RTCisr
; Insert the next 4 lines of code when TMR1
; cannot be reliably updated before clock pulse goes low
; wait for TMR1L to become clear
; (may already be clear)
BTFSC
BRA
TMR1L,0
$-2
BTFSS
BRA
TMR1L,0
$-2
; wait for TMR1L to become set
; TMR1 has just incremented
; If TMR1 update can be completed before clock pulse goes low
; Start ISR here
BSF
BCF
INCF
MOVLW
CPFSGT
RETURN
CLRF
TMR1H, 7
PIR1, TMR1IF
secs, F
.59
; Preload for 1 sec overflow
; Clear interrupt flag
; Increment seconds
; 60 seconds elapsed?
secs
; No, done
secs
mins, F
.59
; Clear seconds
; Increment minutes
; 60 minutes elapsed?
INCF
MOVLW
CPFSGT
RETURN
CLRF
mins
; No, done
mins
hours, F
.23
; clear minutes
; Increment hours
; 24 hours elapsed?
INCF
MOVLW
CPFSGT
RETURN
CLRF
hours
; No, done
; Reset hours
; Done
hours
RETURN
© 2008 Microchip Technology Inc.
DS39760D-page 119
PIC18F2450/4450
TABLE 11-2: REGISTERS ASSOCIATED WITH TIMER1 AS A TIMER/COUNTER
Reset
Values
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
on Page:
INTCON
PIR1
GIE/GIEH PEIE/GIEL TMR0IE
INT0IE
TXIF
RBIE
—
TMR0IF
CCP1IF
CCP1IE
CCP1IP
INT0IF
TMR2IF
TMR2IE
TMR2IP
RBIF
49
51
51
51
50
50
50
—
—
—
ADIF
ADIE
ADIP
RCIF
RCIE
RCIP
TMR1IF
TMR1IE
TMR1IP
PIE1
TXIE
TXIP
—
IPR1
—
TMR1L
TMR1H
T1CON
Timer1 Register Low Byte
TImer1 Register High Byte
RD16
T1RUN T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the Timer1 module.
DS39760D-page 120
© 2008 Microchip Technology Inc.
PIC18F2450/4450
12.1 Timer2 Operation
12.0 TIMER2 MODULE
In normal operation, TMR2 is incremented from 00h on
each clock (FOSC/4). A 2-bit counter/prescaler on the
clock input gives direct input, divide-by-4 and divide-by-
16 prescale options. These are selected by the prescaler
control bits, T2CKPS1:T2CKPS0 (T2CON<1:0>). The
value of TMR2 is compared to that of the period register,
PR2, on each clock cycle. When the two values match,
the comparator generates a match signal as the timer
output. This signal also resets the value of TMR2 to 00h
on the next cycle and drives the output counter/
postscaler (see Section 12.2 “Timer2 Interrupt”).
The Timer2 module timer incorporates the following
features:
• 8-Bit Timer and Period Registers (TMR2 and
PR2, respectively)
• Readable and Writable (both registers)
• Software Programmable Prescaler (1:1, 1:4 and
1:16)
• Software Programmable Postscaler (1:1 through
1:16)
• Interrupt on TMR2 to PR2 Match
The TMR2 and PR2 registers are both directly readable
and writable. The TMR2 register is cleared on any
device Reset, while the PR2 register initializes at FFh.
Both the prescaler and postscaler counters are cleared
on the following events:
The module is controlled through the T2CON register
(Register 12-1) which enables or disables the timer and
configures the prescaler and postscaler. Timer2 can be
shut off by clearing control bit, TMR2ON (T2CON<2>),
to minimize power consumption.
• a write to the TMR2 register
• a write to the T2CON register
A simplified block diagram of the module is shown in
Figure 12-1.
• any device Reset (Power-on Reset, MCLR Reset,
Watchdog Timer Reset or Brown-out Reset)
TMR2 is not cleared when T2CON is written.
REGISTER 12-1: T2CON: TIMER2 CONTROL REGISTER
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
T2OUTPS3 T2OUTPS2 T2OUTPS1 T2OUTPS0
TMR2ON
T2CKPS1
T2CKPS0
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7
Unimplemented: Read as ‘0’
bit 6-3
T2OUTPS3:T2OUTPS0: Timer2 Output Postscale Select bits
0000= 1:1 Postscale
0001= 1:2 Postscale
•
•
•
1111= 1:16 Postscale
bit 2
TMR2ON: Timer2 On bit
1= Timer2 is on
0= Timer2 is off
bit 1-0
T2CKPS1:T2CKPS0: Timer2 Clock Prescale Select bits
00= Prescaler is 1
01= Prescaler is 4
1x= Prescaler is 16
© 2008 Microchip Technology Inc.
DS39760D-page 121
PIC18F2450/4450
A range of 16 postscale options (from 1:1 through 1:16
inclusive) can be selected with the postscaler control
bits, T2OUTPS3:T2OUTPS0 (T2CON<6:3>).
12.2 Timer2 Interrupt
Timer2 also can generate an optional device interrupt.
The Timer2 output signal (TMR2 to PR2 match)
provides the input for the 4-bit output counter/
postscaler. This counter generates the TMR2 match
interrupt flag which is latched in TMR2IF (PIR1<1>).
The interrupt is enabled by setting the TMR2 Match
Interrupt Enable bit, TMR2IE (PIE1<1>).
12.3 TMR2 Output
The unscaled output of TMR2 is available primarily to
the CCP module, where it is used as a time base for
operations in PWM mode.
FIGURE 12-1:
TIMER2 BLOCK DIAGRAM
4
1:1 to 1:16
Set TMR2IF
Postscaler
T2OUTPS3:T2OUTPS0
2
TMR2 Output
T2CKPS1:T2CKPS0
(to PWM)
TMR2/PR2
Match
Reset
TMR2
1:1, 1:4, 1:16
Prescaler
Comparator
PR2
FOSC/4
8
8
8
Internal Data Bus
TABLE 12-1: REGISTERS ASSOCIATED WITH TIMER2 AS A TIMER/COUNTER
Reset
Values
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
on Page:
INTCON GIE/GIEH PEIE/GIEL TMR0IE
INT0IE
TXIF
RBIE
—
TMR0IF
CCP1IF
CCP1IE
CCP1IP
INT0IF
TMR2IF
TMR2IE
TMR2IP
RBIF
49
51
51
51
50
50
50
PIR1
PIE1
IPR1
—
—
—
ADIF
ADIE
ADIP
RCIF
RCIE
RCIP
TMR1IF
TMR1IE
TMR1IP
TXIE
TXIP
—
—
TMR2 Timer2 Register
T2CON
PR2
—
T2OUTPS3 T2OUTPS2 T2OUTPS1 T2OUTPS0 TMR2ON T2CKPS1 T2CKPS0
Timer2 Period Register
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the Timer2 module.
DS39760D-page 122
© 2008 Microchip Technology Inc.
PIC18F2450/4450
13.0 CAPTURE/COMPARE/PWM
(CCP) MODULE
PIC18F2450/4450 devices have one CCP (Capture/
Compare/PWM) module. The module contains a 16-bit
register, which can operate as a 16-bit Capture register,
a 16-bit Compare register or a PWM Master/Slave Duty
Cycle register.
REGISTER 13-1: CCP1CON: CAPTURE/COMPARE/PWM CONTROL REGISTER
U-0
—
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
DC1B1
DC1B0
CCP1M3
CCP1M2
CCP1M1
CCP1M0
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7-6
bit 5-4
Unimplemented: Read as ‘0’
DC1B1:DC1B0: PWM Duty Cycle for CCP Module bits
Capture mode:
Unused.
Compare mode:
Unused.
PWM mode:
These bits are the two LSbs (bit 1 and bit 0) of the 10-bit PWM duty cycle. The eight MSbs of the duty
cycle are found in CCPR1L.
bit 3-0
CCP1M3:CCP1M0: CCP Module Mode Select bits
0000= Capture/Compare/PWM disabled (resets CCP module)
0001= Reserved
0010= Compare mode: toggle output on match (CCP1IF bit is set)
0011= Reserved
0100= Capture mode: every falling edge
0101= Capture mode: every rising edge
0110= Capture mode: every 4th rising edge
0111= Capture mode: every 16th rising edge
1000= Compare mode: initialize CCP1 pin low; on compare match, force CCP1 pin high
(CCP1IF bit is set)
1001= Compare mode: initialize CCP1 pin high; on compare match, force CCP1 pin low
(CCP1IF bit is set)
1010= Compare mode: generate software interrupt on compare match (CCP1IF bit is set,
CCP1 pin reflects I/O state)
1011= Compare mode: trigger special event, reset timer and start A/D conversion on CCP1 match
(CCP1IF bit is set)
11xx= PWM mode
© 2008 Microchip Technology Inc.
DS39760D-page 123
PIC18F2450/4450
13.2.1
CCP1 PIN CONFIGURATION
13.1 CCP Module Configuration
In Capture mode, the CCP1 pin should be configured
as an input by setting the corresponding TRIS direction
bit.
The Capture/Compare/PWM module is associated with
a control register (generically, CCP1CON) and a data
register (CCPR1). The data register, in turn, is
comprised of two 8-bit registers: CCPR1L (low byte)
and CCPR1H (high byte). All registers are both
readable and writable.
Note:
If RC2/CCP1 is configured as an output, a
write to the port can cause a capture
condition.
13.1.1
CCP MODULE AND TIMER
RESOURCES
13.2.2
SOFTWARE INTERRUPT
When the Capture mode is changed, a false capture
interrupt may be generated. The user should keep the
CCP1IE interrupt enable bit clear to avoid false
interrupts. The interrupt flag bit, CCP1IF, should also
be cleared following any such change in operating
mode.
The CCP module utilizes Timer1 or Timer2, depending
on the mode selected. Timer1 is available to the mod-
ule in Capture or Compare modes, while Timer2 is
available for modules in PWM mode.
TABLE 13-1: CCP MODE – TIMER
RESOURCE
13.2.3
CCP PRESCALER
There are four prescaler settings in Capture mode.
They are specified as part of the operating mode
selected by the mode select bits (CCP1M3:CCP1M0).
Whenever the CCP module is turned off or Capture
mode is disabled, the prescaler counter is cleared. This
means that any Reset will clear the prescaler counter.
CCP Mode
Timer Resource
Capture
Compare
PWM
Timer1
Timer1
Timer2
In Timer1 in Asynchronous Counter mode, the capture
operation will not work.
Switching from one capture prescaler to another may
generate an interrupt. Also, the prescaler counter will
not be cleared, therefore, the first capture may be from
13.2 Capture Mode
a
non-zero prescaler. Example 13-1 shows the
In Capture mode, the CCPR1H:CCPR1L register pair
captures the 16-bit value of the TMR1 register when an
event occurs on the corresponding CCP1 pin. An event
is defined as one of the following:
recommended method for switching between capture
prescalers. This example also clears the prescaler
counter and will not generate the “false” interrupt.
EXAMPLE 13-1:
CHANGING BETWEEN
CAPTURE PRESCALERS
(CCP1 SHOWN)
• every falling edge
• every rising edge
• every 4th rising edge
• every 16th rising edge
CLRF
CCP1CON
; Turn CCP module off
; Load WREG with the
; new prescaler mode
; value and CCP ON
; Load CCP1CON with
; this value
MOVLW NEW_CAPT_PS
The event is selected by the mode select bits,
CCP1M3:CCP1M0 (CCP1CON<3:0>). When a capture
is made, the interrupt request flag bit, CCP1IF, is set; it
must be cleared in software. If another capture occurs
before the value in register CCPR1 is read, the old
captured value is overwritten by the new captured value.
MOVWF CCP1CON
FIGURE 13-1:
CAPTURE MODE OPERATION BLOCK DIAGRAM
Set CCP1IF
CCP1 pin
Prescaler
÷ 1, 4, 16
and
Edge Detect
CCPR1H
CCPR1L
TMR1L
TMR1
Enable
TMR1H
4
CCP1CON<3:0>
Q1:Q4
4
DS39760D-page 124
© 2008 Microchip Technology Inc.
PIC18F2450/4450
13.3.3
SOFTWARE INTERRUPT MODE
13.3 Compare Mode
When the Generate Software Interrupt mode is chosen
(CCP1M3:CCP1M0 = 1010), the CCP1 pin is not
affected. Only a CCP interrupt is generated, if enabled,
and the CCP1IE bit is set.
In Compare mode, the 16-bit CCPR1 register value is
constantly compared against the TMR1 register pair
value. When a match occurs, the CCP1 pin can be:
• driven high
• driven low
13.3.4
SPECIAL EVENT TRIGGER
• toggled (high-to-low or low-to-high)
The CCP module is equipped with a Special Event
Trigger. This is an internal hardware signal generated
in Compare mode to trigger actions by other modules.
The Special Event Trigger is enabled by selecting
the Compare Special Event Trigger mode
(CCP1M3:CCP1M0 = 1011).
• remain unchanged (that is, reflects the state of the
I/O latch)
The action on the pin is based on the value of the mode
select bits (CCP1M3:CCP1M0). At the same time, the
interrupt flag bit, CCP1IF, is set.
For the CCP module, the Special Event Trigger resets
the Timer1 register pair. This allows the CCPR1
registers to serve as a programmable period register
for the Timer1.
13.3.1
CCP1 PIN CONFIGURATION
The user must configure the CCP1 pin as an output by
clearing the appropriate TRIS bit.
The Special Event Trigger for CCP1 can also start an
A/D conversion. In order to do this, the A/D Converter
must already be enabled.
Note:
Clearing the CCP1CON register will force
the RC2 compare output latch to the
default low level.
13.3.2
TIMER1 MODE SELECTION
Timer1 must be running in Timer mode, or
Synchronized Counter mode, if the CCP module is
using the compare feature. In Asynchronous Counter
mode, the compare operation may not work.
FIGURE 13-2:
COMPARE MODE OPERATION BLOCK DIAGRAM
Special Event Trigger
(Timer1 Reset)
Set CCP1IF
CCPR1H
CCPR1L
CCP1 pin
S
R
Q
Output
Logic
Compare
Match
Comparator
TRIS
Output Enable
4
CCP1CON<3:0>
TMR1H
TMR1L
© 2008 Microchip Technology Inc.
DS39760D-page 125
PIC18F2450/4450
TABLE 13-2: REGISTERS ASSOCIATED WITH CAPTURE, COMPARE, TIMER1
Reset
Values
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
on Page:
INTCON
RCON
GIE/GIEH PEIE/GIEL TMR0IE
INT0IE
RI
RBIE
TO
—
TMR0IF
PD
INT0IF
POR
RBIF
BOR
49
50
51
51
51
51
50
50
50
50
50
50
IPEN
—
SBOREN(1)
—
PIR1
ADIF
RCIF
RCIE
RCIP
—
TXIF
TXIE
TXIP
—
CCP1IF TMR2IF TMR1IF
CCP1IE TMR2IE TMR1IE
CCP1IP TMR2IP TMR1IP
PIE1
—
ADIE
—
IPR1
—
ADIP
—
TRISC
TMR1L
TMR1H
T1CON
CCPR1L
CCPR1H
CCP1CON
TRISC7
TRISC6
—
TRISC2
TRISC1
TRISC0
Timer1 Register Low Byte
Timer1 Register High Byte
RD16
T1RUN T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON
Capture/Compare/PWM Register 1 Low Byte
Capture/Compare/PWM Register 1 High Byte
—
—
DC1B1
DC1B0
CCP1M3 CCP1M2 CCP1M1 CCP1M0
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by capture/compare and Timer1.
Note 1: The SBOREN bit is only available when BOREN<1:0> = 01; otherwise, the bit reads as ‘0’.
DS39760D-page 126
© 2008 Microchip Technology Inc.
PIC18F2450/4450
13.4.1
PWM PERIOD
13.4 PWM Mode
The PWM period is specified by writing to the PR2
register. The PWM period can be calculated using the
following formula:
In Pulse-Width Modulation (PWM) mode, the CCP1 pin
produces up to a 10-bit resolution PWM output.
Figure 13-3 shows a simplified block diagram of the
CCP module in PWM mode.
EQUATION 13-1:
For a step-by-step procedure on how to set up the CCP
module for PWM operation, see Section 13.4.3
“Setup for PWM Operation”.
PWM Period = [(PR2) + 1] • 4 • TOSC •
(TMR2 Prescale Value)
PWM frequency is defined as 1/[PWM period].
FIGURE 13-3:
SIMPLIFIED PWM BLOCK
DIAGRAM
When TMR2 is equal to PR2, the following three events
occur on the next increment cycle:
CCP1CON<5:4>
Duty Cycle Registers
• TMR2 is cleared
CCPR1L
• The CCP1 pin is set (exception: if PWM duty
cycle = 0%, the CCP1 pin will not be set)
• The PWM duty cycle is latched from CCPR1L into
CCPR1H
CCPR1H (Slave)
Comparator
Note:
The Timer2 postscalers (see Section 12.0
“Timer2 Module”) are not used in the
determination of the PWM frequency. The
postscaler could be used to have a servo
update rate at a different frequency than
the PWM output.
Q
R
S
CCP1
Output
(Note 1)
TMR2
Corresponding
TRIS bit
Comparator
PR2
Clear Timer,
CCP1 pin and
latch D.C.
13.4.2
PWM DUTY CYCLE
The PWM duty cycle is specified by writing to the
CCPR1L register and to the CCP1CON<5:4> bits. Up
to 10-bit resolution is available. The CCPR1L contains
the eight MSbs and the CCP1CON<5:4> bits contain
the two LSbs. This 10-bit value is represented by
CCPR1L:CCP1CON<5:4>. Equation 13-2 is used to
calculate the PWM duty cycle in time:
Note 1: The 8-bit TMR2 value is concatenated with the 2-bit
internal Q clock, or 2 bits of the prescaler, to create
the 10-bit time base.
A PWM output (Figure 13-4) has a time base (period)
and a time that the output stays high (duty cycle).
The frequency of the PWM is the inverse of the
period (1/period).
EQUATION 13-2:
PWM Duty Cycle = (CCPR1L:CCP1CON<5:4>) •
TOSC • (TMR2 Prescale Value)
FIGURE 13-4:
PWM OUTPUT
Period
CCPR1L and CCP1CON<5:4> can be written to at any
time, but the duty cycle value is not latched into
CCPR1H until after a match between PR2 and TMR2
occurs (i.e., the period is complete). In PWM mode,
CCPR1H is a read-only register.
Duty Cycle
TMR2 = PR2
TMR2 = Duty Cycle
TMR2 = PR2
© 2008 Microchip Technology Inc.
DS39760D-page 127
PIC18F2450/4450
The CCPR1H register and a 2-bit internal latch are
used to double-buffer the PWM duty cycle. This
double-buffering is essential for glitchless PWM
operation.
13.4.3
SETUP FOR PWM OPERATION
The following steps should be taken when configuring
the CCP module for PWM operation:
1. Set the PWM period by writing to the PR2
register.
When the CCPR1H and 2-bit latch match TMR2,
concatenated with an internal 2-bit Q clock or 2 bits of
the TMR2 prescaler, the CCP1 pin is cleared.
2. Set the PWM duty cycle by writing to the
CCPR1L register and CCP1CON<5:4> bits.
The maximum PWM resolution (bits) for a given PWM
frequency is given by the equation:
3. Make the CCP1 pin an output by clearing the
appropriate TRIS bit.
4. Set the TMR2 prescale value, then enable
Timer2 by writing to T2CON.
EQUATION 13-3:
FOSC
⎛
⎞
⎠
5. Configure the CCP module for PWM operation.
log ---------------
⎝
FPWM
PWM Resolution (max)
= ----------------------------- b i t s
log(2)
Note:
If the PWM duty cycle value is longer than
the PWM period, the CCP1 pin will not be
cleared.
TABLE 13-3: EXAMPLE PWM FREQUENCIES AND RESOLUTIONS AT 40 MHz
PWM Frequency
2.44 kHz
9.77 kHz
39.06 kHz 156.25 kHz 312.50 kHz 416.67 kHz
Timer Prescaler (1, 4, 16)
PR2 Value
16
FFh
10
4
1
1
3Fh
8
1
1Fh
7
1
FFh
10
FFh
10
17h
6.58
Maximum Resolution (bits)
TABLE 13-4: REGISTERS ASSOCIATED WITH PWM AND TIMER2
Reset
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Values
on Page:
INTCON
RCON
PIR1
GIE/GIEH PEIE/GIEL TMR0IE
INT0IE
RI
RBIE
TO
—
TMR0IF
PD
INT0IF
POR
RBIF
BOR
49
50
51
51
51
51
50
50
50
50
50
50
IPEN
—
SBOREN(1)
ADIF
—
RCIF
RCIE
RCIP
—
TXIF
TXIE
TXIP
—
CCP1IF
CCP1IE
CCP1IP
TRISC2
TMR2IF TMR1IF
TMR2IE TMR1IE
TMR2IP TMR1IP
TRISC1 TRISC0
PIE1
—
ADIE
—
IPR1
—
ADIP
—
TRISC
TMR2
PR2
TRISC7
TRISC6
—
Timer2 Register
Timer2 Period Register
T2CON
—
T2OUTPS3 T2OUTPS2 T2OUTPS1 T2OUTPS0 TMR2ON T2CKPS1 T2CKPS0
CCPR1L Capture/Compare/PWM Register 1 Low Byte
CCPR1H Capture/Compare/PWM Register 1 High Byte
CCP1CON
—
—
DC1B1
DC1B0
CCP1M3 CCP1M2 CCP1M1 CCP1M0
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PWM or Timer2.
Note 1: The SBOREN bit is only available when BOREN<1:0> = 01; otherwise, the bit reads as ‘0’.
DS39760D-page 128
© 2008 Microchip Technology Inc.
PIC18F2450/4450
any USB host and the PIC® microcontroller. The SIE can
be interfaced directly to the USB, utilizing the internal
transceiver, or it can be connected through an external
transceiver. An internal 3.3V regulator is also available
to power the internal transceiver in 5V applications.
14.0 UNIVERSAL SERIAL BUS
(USB)
This section describes the details of the USB peripheral.
Because of the very specific nature of the module,
knowledge of USB is expected. Some high-level USB
information is provided in Section 14.9 “Overview of
USB” only for application design reference. Designers
are encouraged to refer to the official specification
published by the USB Implementers Forum (USB-IF) for
the latest information. USB Specification Revision 2.0 is
the most current specification at the time of publication
of this document.
Some special hardware features have been included to
improve performance. Dual port memory in the
device’s data memory space (USB RAM) has been
supplied to share direct memory access between the
microcontroller core and the SIE. Buffer descriptors are
also provided, allowing users to freely program
endpoint memory usage within the USB RAM space.
Figure 14-1 presents a general overview of the USB
peripheral and its features.
14.1 Overview of the USB Peripheral
The PIC18F2450/4450 device family contains a full-
speed and low-speed, compatible USB Serial Interface
Engine (SIE) that allows fast communication between
FIGURE 14-1:
USB PERIPHERAL AND OPTIONS
PIC18F2450/4450 Family
3.3V Regulator
External 3.3V
Supply
VUSB
(3)
EN
VREGEN
P
External
Pull-ups
(2)
FSEN
UPUEN
P
(Full
Speed)
(Low
Speed)
Internal Pull-ups
UTRDIS
Transceiver
FS
USB Bus
USB Clock from the
Oscillator Module
D+
D-
OE
External
Transceiver
(1)
UOE
VM
VP
RCV
USB Control and
Configuration
(1)
USB Bus
(1)
(1)
(1)
USB
SIE
VMO
(1)
VPO
256-Byte
USB RAM
Note 1: This signal is only available if the internal transceiver is disabled (UTRDIS = 1).
2: The pull-ups can be supplied either from the VUSB pin or from an external 3.3V supply.
3: Do not enable the internal regulator when using an external 3.3V supply.
© 2008 Microchip Technology Inc.
DS39760D-page 129
PIC18F2450/4450
In addition, the USB Control register contains a status
bit, SE0 (UCON<5>), which is used to indicate the
occurrence of a single-ended zero on the bus. When
the USB module is enabled, this bit should be
monitored to determine whether the differential data
lines have come out of a single-ended zero condition.
This helps to differentiate the initial power-up state from
the USB Reset signal.
14.2 USB Status and Control
The operation of the USB module is configured and
managed through three control registers. In addition, a
total of 22 registers are used to manage the actual USB
transactions. The registers are:
• USB Control register (UCON)
• USB Configuration register (UCFG)
• USB Transfer Status register (USTAT)
• USB Device Address register (UADDR)
• Frame Number registers (UFRMH:UFRML)
• Endpoint Enable registers 0 through 15 (UEPn)
The overall operation of the USB module is controlled
by the USBEN bit (UCON<3>). Setting this bit activates
the module and resets all of the PPBI bits in the Buffer
Descriptor Table to ‘0’. This bit also activates the on-
chip voltage regulator, if enabled. Thus, this bit can be
used as a soft attach/detach to the USB. Although all
status and control bits are ignored when this bit is clear,
the module needs to be fully preconfigured prior to
setting this bit.
14.2.1
USB CONTROL REGISTER (UCON)
The USB Control register (Register 14-1) contains bits
needed to control the module behavior during transfers.
The register contains bits that control the following:
• Main USB Peripheral Enable
• Ping-Pong Buffer Pointer Reset
• Control of the Suspend Mode
• Packet Transfer Disable
REGISTER 14-1: UCON: USB CONTROL REGISTER
U-0
—
R/W-0
R-x
R/C-0
R/W-0
R/W-0
R/W-0
U-0
—
PPBRST
SE0
PKTDIS
USBEN
RESUME
SUSPND
bit 7
bit 0
Legend:
C = Clearable bit
W = Writable bit
‘1’ = Bit is set
R = Readable bit
-n = Value at POR
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7
bit 6
Unimplemented: Read as ‘0’
PPBRST: Ping-Pong Buffers Reset bit
1= Reset all Ping-Pong Buffer Pointers to the EVEN Buffer Descriptor (BD) banks
0= Ping-Pong Buffer Pointers not being reset
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
SE0: Live Single-Ended Zero Flag bit
1= Single-ended zero active on the USB bus
0= No single-ended zero detected
PKTDIS: Packet Transfer Disable bit
1= SIE token and packet processing disabled, automatically set when a SETUP token is received
0= SIE token and packet processing enabled
USBEN: USB Module Enable bit
1= USB module and supporting circuitry enabled (device attached)
0= USB module and supporting circuitry disabled (device detached)
RESUME: Resume Signaling Enable bit
1= Resume signaling activated
0= Resume signaling disabled
SUSPND: Suspend USB bit
1= USB module and supporting circuitry in Power Conserve mode, SIE clock inactive
0= USB module and supporting circuitry in normal operation, SIE clock clocked at the configured rate
Unimplemented: Read as ‘0’
DS39760D-page 130
© 2008 Microchip Technology Inc.
PIC18F2450/4450
The PPBRST bit (UCON<6>) controls the Reset status
when Double-Buffering mode (ping-pong buffering) is
used. When the PPBRST bit is set, all Ping-Pong
Buffer Pointers are set to the EVEN buffers. PPBRST
has to be cleared by firmware. This bit is ignored in
buffering modes not using ping-pong buffering.
The UCFG register also contains two bits which aid in
module testing, debugging and USB certifications.
These bits control output enable state monitoring and
eye pattern generation.
Note:
The USB speed, transceiver and pull-up
should only be configured during the mod-
ule setup phase. It is not recommended to
switch these settings while the module is
enabled.
The PKTDIS bit (UCON<4>) is a flag indicating that the
SIE has disabled packet transmission and reception.
This bit is set by the SIE when a SETUP token is
received to allow setup processing. This bit cannot be
set by the microcontroller, only cleared; clearing it
allows the SIE to continue transmission and/or
reception. Any pending events within the Buffer
Descriptor Table will still be available, indicated within
the USTAT register’s FIFO buffer.
14.2.2.1
Internal Transceiver
The USB peripheral has a built-in, USB 2.0, full-speed
and low-speed compliant transceiver, internally con-
nected to the SIE. This feature is useful for low-cost,
single chip applications. The UTRDIS bit (UCFG<3>)
controls the transceiver; it is enabled by default
(UTRDIS = 0). The FSEN bit (UCFG<2>) controls the
transceiver speed; setting the bit enables full-speed
operation. The on-chip USB pull-up resistors are con-
trolled by the UPUEN bit (UCFG<4>). They can only be
selected when the on-chip transceiver is enabled.
The RESUME bit (UCON<2>) allows the peripheral to
perform a remote wake-up by executing Resume
signaling. To generate a valid remote wake-up,
firmware must set RESUME for 10 ms and then clear
the bit. For more information on Resume signaling, see
Sections 7.1.7.5, 11.4.4 and 11.9 in the USB 2.0
Specification.
The USB specification requires 3.3V operation for
communications; however, the rest of the chip may be
running at a higher voltage. Thus, the transceiver is
supplied power from a separate source, VUSB.
The SUSPND bit (UCON<1>) places the module and
supporting circuitry (i.e., voltage regulator) in a low-
power mode. The input clock to the SIE is also
disabled. This bit should be set by the software in
response to an IDLEIF interrupt. It should be reset by
the microcontroller firmware after an ACTVIF interrupt
is observed. When this bit is active, the device remains
attached to the bus but the transceiver outputs remain
Idle. The voltage on the VUSB pin may vary depending
on the value of this bit. Setting this bit before a IDLEIF
request will result in unpredictable bus behavior.
14.2.2.2
External Transceiver
This module provides support for use with an off-chip
transceiver. The off-chip transceiver is intended for
applications where physical conditions dictate the
location of the transceiver to be away from the SIE. For
example, applications that require isolation from the
USB could use an external transceiver through some
isolation to the microcontroller’s SIE (Figure 14-2).
External transceiver operation is enabled by setting the
UTRDIS bit.
Note:
While in Suspend mode, a typical bus
powered USB device is limited to 500 μA
of current. This is the complete current
drawn by the PIC microcontroller and its
supporting circuitry. Care should be taken
to assure minimum current draw when the
device enters Suspend mode.
FIGURE 14-2:
TYPICAL EXTERNAL
TRANSCEIVER WITH
ISOLATION
VDD Isolated
from USB
PIC®
14.2.2
USB CONFIGURATION REGISTER
(UCFG)
3.3V Derived
from USB
Microcontroller
VDD
Prior to communicating over USB, the module’s
associated internal and/or external hardware must be
configured. Most of the configuration is performed with
the UCFG register (Register 14-2). The separate USB
voltage regulator (see Section 14.2.2.8 “Internal
Regulator”) is controlled through the Configuration
registers.
VUSB
1.5 kΩ
VM
VP
RCV
VMO
VPO
Isolation
Transceiver
D+
D-
UOE
The UFCG register contains most of the bits that
control the system level behavior of the USB module.
These include:
Note: The above setting shows a simplified schematic
for a full-speed configuration using an external
transceiver with isolation.
• Bus Speed (full speed versus low speed)
• On-Chip Transceiver Enable
• Ping-Pong Buffer Usage
© 2008 Microchip Technology Inc.
DS39760D-page 131
PIC18F2450/4450
REGISTER 14-2: UCFG: USB CONFIGURATION REGISTER
R/W-0
R/W-0
UOEMON(1)
U-0
—
R/W-0
UPUEN(2,3) UTRDIS(2)
R/W-0
R/W-0
FSEN(2)
R/W-0
PPB1
R/W-0
PPB0
UTEYE
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7
bit 6
UTEYE: USB Eye Pattern Test Enable bit
1= Eye pattern test enabled
0= Eye pattern test disabled
UOEMON: USB OE Monitor Enable bit(1)
1= UOE signal active; it indicates intervals during which the D+/D- lines are driving
0= UOE signal inactive
bit 5
bit 4
Unimplemented: Read as ‘0’
UPUEN: USB On-Chip Pull-up Enable bit(2,3)
1= On-chip pull-up enabled (pull-up on D+ with FSEN = 1or D- with FSEN = 0)
0= On-chip pull-up disabled
bit 3
UTRDIS: On-Chip Transceiver Disable bit(2)
1= On-chip transceiver disabled; digital transceiver interface enabled
0= On-chip transceiver active
bit 2
FSEN: Full-Speed Enable bit(2)
1= Full-speed device: controls transceiver edge rates; requires input clock at 48 MHz
0= Low-speed device: controls transceiver edge rates; requires input clock at 6 MHz
bit 1-0
PPB1:PPB0: Ping-Pong Buffers Configuration bits
11= Enabled for all endpoints except Endpoint 0
10= EVEN/ODD ping-pong buffers enabled for all endpoints
01= EVEN/ODD ping-pong buffer enabled for OUT Endpoint 0
00= EVEN/ODD ping-pong buffers disabled
Note 1: If UTRDIS is set, the UOE signal will be active independent of the UOEMON bit setting.
2: The UPUEN, UTRDIS and FSEN bits should never be changed while the USB module is enabled. These
values must be preconfigured prior to enabling the module.
3: This bit is only valid when the on-chip transceiver is active (UTRDIS = 0); otherwise, it is ignored.
There are 6 signals from the module to communicate
with and control an external transceiver:
The VPO and VMO signals are outputs from the SIE to
the external transceiver. The RCV signal is the output
from the external transceiver to the SIE; it represents
the differential signals from the serial bus translated
into a single pulse train. The VM and VP signals are
used to report conditions on the serial bus to the SIE
that can’t be captured with the RCV signal. The
combinations of states of these signals and their
interpretation are listed in Table 14-1 and Table 14-2.
• VM: Input from the single-ended D- line
• VP: Input from the single-ended D+ line
• RCV: Input from the differential receiver
• VMO: Output to the differential line driver
• VPO: Output to the differential line driver
• UOE: Output enable
DS39760D-page 132
© 2008 Microchip Technology Inc.
PIC18F2450/4450
TABLE 14-1: DIFFERENTIAL OUTPUTS TO
TRANSCEIVER
14.2.2.6
USB Output Enable Monitor
The USB OE monitor provides indication as to whether
the SIE is listening to the bus or actively driving the bus.
This is enabled by default when using an external
transceiver or when UCFG<6> = 1.
VPO
VMO
Bus State
0
0
1
1
0
1
0
1
Single-Ended Zero
Differential ‘0’
The USB OE monitoring is useful for initial system
debugging, as well as scope triggering during eye
pattern generation tests.
Differential ‘1’
Illegal Condition
14.2.2.7
Eye Pattern Test Enable
TABLE 14-2: SINGLE-ENDED INPUTS
FROM TRANSCEIVER
An automatic eye pattern test can be generated by the
module when the UCFG<7> bit is set. The eye pattern
output will be observable based on module settings,
meaning that the user is first responsible for configuring
the SIE clock settings, pull-up resistor and Transceiver
mode. In addition, the module has to be enabled.
VP
VM
Bus State
0
0
1
1
0
1
0
1
Single-Ended Zero
Low Speed
High Speed
Error
Once UTEYE is set, the module emulates a switch from
a receive to transmit state and will start transmitting a
J-K-J-K bit sequence (K-J-K-J for full speed). The
sequence will be repeated indefinitely while the Eye
Pattern Test mode is enabled.
The UOE signal toggles the state of the external
transceiver. This line is pulled low by the device to
enable the transmission of data from the SIE to an
external device.
Note that this bit should never be set while the module
is connected to an actual USB system. This test mode
is intended for board verification to aid with USB certi-
fication tests. It is intended to show a system developer
the noise integrity of the USB signals which can be
affected by board traces, impedance mismatches and
proximity to other system components. It does not
properly test the transition from a receive to a transmit
state. Although the eye pattern is not meant to replace
the more complex USB certification test, it should aid
during first order system debugging.
14.2.2.3
Internal Pull-up Resistors
The PIC18F2450/4450 devices have built-in pull-up
resistors designed to meet the requirements for low-
speed and full-speed USB. The UPUEN bit (UCFG<4>)
enables the internal pull-ups. Figure 14-1 shows the
pull-ups and their control.
14.2.2.4
Pull-up Resistors
The PIC18F2450/4450 devices require an external
pull-up resistor to meet the requirements for low-speed
and full-speed USB. Either an external 3.3V supply or
the VUSB pin may be used to pull up D+ or D-. The pull-
up resistor must be 1.5 kΩ (±5%) as required by the
USB specifications. Figure 14-3 shows an example
with the VUSB pin.
14.2.2.8
Internal Regulator
The PIC18F2450/4450 devices have a built-in 3.3V
regulator to provide power to the internal transceiver and
provide a source for the external pull-ups. An external
220 nF (±20%) capacitor is required for stability.
FIGURE 14-3:
EXTERNAL CIRCUITRY
Note:
The drive from VUSB is sufficient to only
drive an external pull-up in addition to the
internal transceiver.
PIC®
Host
Controller/HUB
Microcontroller
VUSB
The regulator is disabled by default and can be enabled
through the VREGEN Configuration bit. When enabled,
the voltage is visible on pin VUSB. When the regulator
is disabled, a 3.3V source must be provided through
the VUSB pin for the internal transceiver. If the internal
transceiver is disabled, VUSB is not used.
1.5 kΩ
D+
D-
Note 1: Do not enable the internal regulator if an
Note: The above setting shows a typical connection for a
full-speed configuration using an on-chip regulator
and an external pull-up resistor.
external regulator is connected to VUSB.
2: VDD must be greater than or equal to
VUSB at all times, even with the regulator
disabled.
14.2.2.5
Ping-Pong Buffer Configuration
The usage of ping-pong buffers is configured using the
PPB1:PPB0 bits. Refer to Section 14.4.4 “Ping-Pong
Buffering” for a complete explanation of the ping-pong
buffers.
© 2008 Microchip Technology Inc.
DS39760D-page 133
PIC18F2450/4450
Clearing the transfer complete flag bit, TRNIF, causes
the SIE to advance the FIFO. If the next data in the
FIFO holding register is valid, the SIE will reassert the
interrupt within 6 TCY of clearing TRNIF. If no additional
data is present, TRNIF will remain clear; USTAT data
will no longer be reliable.
14.2.3
USB STATUS REGISTER (USTAT)
The USB Status register reports the transaction status
within the SIE. When the SIE issues a USB transfer
complete interrupt, USTAT should be read to determine
the status of the transfer. USTAT contains the transfer
endpoint number, direction and Ping-Pong Buffer
Pointer value (if used).
Note:
If an endpoint request is received while the
USTAT FIFO is full, the SIE will
automatically issue a NAK back to the
host.
Note:
The data in the USB Status register is valid
only when the TRNIF interrupt flag is
asserted.
The USTAT register is actually a read window into a
four-byte status FIFO, maintained by the SIE. It allows
the microcontroller to process one transfer while the
SIE processes additional endpoints (Figure 14-4).
When the SIE completes using a buffer for reading or
writing data, it updates the USTAT register. If another
USB transfer is performed before a transaction
complete interrupt is serviced, the SIE will store the
status of the next transfer into the status FIFO.
FIGURE 14-4:
USTAT FIFO
USTAT from SIE
Clearing TRNIF
Advances FIFO
4-Byte FIFO
for USTAT
Data Bus
REGISTER 14-3: USTAT: USB STATUS REGISTER
U-0
—
R-x
R-x
R-x
R-x
R-x
DIR
R-x
PPBI(1)
U-0
—
ENDP3
ENDP2
ENDP1
ENDP0
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7
Unimplemented: Read as ‘0’
bit 6-3
ENDP3:ENDP0: Encoded Number of Last Endpoint Activity bits
(represents the number of the BDT updated by the last USB transfer)
1111= Endpoint 15
1110= Endpoint 14
....
0001= Endpoint 1
0000= Endpoint 0
bit 2
bit 1
bit 0
DIR: Last BD Direction Indicator bit
1= The last transaction was an IN token
0= The last transaction was an OUT or SETUP token
PPBI: Ping-Pong BD Pointer Indicator bit(1)
1= The last transaction was to the ODD BD bank
0= The last transaction was to the EVEN BD bank
Unimplemented: Read as ‘0’
Note 1: This bit is only valid for endpoints with available EVEN and ODD BD registers.
DS39760D-page 134
© 2008 Microchip Technology Inc.
PIC18F2450/4450
transactions. For Endpoint 0, this bit should always be
cleared since the USB specifications identify
Endpoint 0 as the default control endpoint.
14.2.4
USB ENDPOINT CONTROL
Each of the 16 possible bidirectional endpoints has its
own independent control register, UEPn (where ‘n’ rep-
resents the endpoint number). Each register has an
identical complement of control bits. The prototype is
shown in Register 14-4.
The EPOUTEN bit (UEPn<2>) is used to enable or dis-
able USB OUT transactions from the host. Setting this
bit enables OUT transactions. Similarly, the EPINEN bit
(UEPn<1>) enables or disables USB IN transactions
from the host.
The EPHSHK bit (UEPn<4>) controls handshaking for
the endpoint; setting this bit enables USB handshaking.
Typically, this bit is always set except when using
isochronous endpoints.
The EPSTALL bit (UEPn<0>) is used to indicate a
STALL condition for the endpoint. If a STALL is issued
on a particular endpoint, the EPSTALL bit for that end-
point pair will be set by the SIE. This bit remains set
until it is cleared through firmware, or until the SIE is
reset.
The EPCONDIS bit (UEPn<3>) is used to enable or
disable USB control operations (SETUP) through the
endpoint. Clearing this bit enables SETUP
transactions. Note that the corresponding EPINEN and
EPOUTEN bits must be set to enable IN and OUT
REGISTER 14-4: UEPn: USB ENDPOINT n CONTROL REGISTER (UEP0 THROUGH UEP15)
U-0
—
U-0
—
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
EPSTALL(1)
bit 0
EPHSHK EPCONDIS
EPOUTEN
EPINEN
bit 7
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7-5
bit 4
Unimplemented: Read as ‘0’
EPHSHK: Endpoint Handshake Enable bit
1= Endpoint handshake enabled
0= Endpoint handshake disabled (typically used for isochronous endpoints)
bit 3
EPCONDIS: Bidirectional Endpoint Control bit
If EPOUTEN = 1 and EPINEN = 1:
1= Disable Endpoint n from control transfers; only IN and OUT transfers allowed
0= Enable Endpoint n for control (SETUP) transfers; IN and OUT transfers also allowed
bit 2
bit 1
bit 0
EPOUTEN: Endpoint Output Enable bit
1= Endpoint n output enabled
0= Endpoint n output disabled
EPINEN: Endpoint Input Enable bit
1= Endpoint n input enabled
0= Endpoint n input disabled
EPSTALL: Endpoint Stall Indicator bit
1= Endpoint n has issued one or more STALL packets
0= Endpoint n has not issued any STALL packets
© 2008 Microchip Technology Inc.
DS39760D-page 135
PIC18F2450/4450
14.2.5
USB ADDRESS REGISTER
(UADDR)
FIGURE 14-5:
IMPLEMENTATION OF
USB RAM IN DATA
MEMORY SPACE
The USB Address register contains the unique USB
address that the peripheral will decode when active.
UADDR is reset to 00h when a USB Reset is received,
indicated by URSTIF, or when a Reset is received from
the microcontroller. The USB address must be written
by the microcontroller during the USB setup phase
(enumeration) as part of the Microchip USB firmware
support.
000h
Banks 0
to 1
User Data
1FFh
200h
Banks 2
to 3
Unused
3FFh
400h
Buffer Descriptors,
14.2.6
USB FRAME NUMBER REGISTERS
(UFRMH:UFRML)
Bank 4
USB Data or User Data
4FFh
500h
The Frame Number registers contain the 11-bit frame
number. The low-order byte is contained in UFRML,
while the three high-order bits are contained in
UFRMH. The register pair is updated with the current
frame number whenever a SOF token is received. For
the microcontroller, these registers are read-only. The
Frame Number register is primarily used for
isochronous transfers.
USB Data or
User Data
7FFh
800h
Banks 5
to 14
Unused
14.3 USB RAM
USB data moves between the microcontroller core and
the SIE through a memory space known as the USB
RAM. This is a special dual port memory that is
mapped into the normal data memory space in Bank 4
(400h to 4FFh) for a total of 256 bytes (Figure 14-5).
Some portion of Bank 4 (400h through 4FFh) is used
specifically for endpoint buffer control, while the
remaining portion is available for USB data. Depending
on the type of buffering being used, all but 8 bytes of
Bank 4 may also be available for use as USB buffer
space.
F00h
F80h
FFFh
Bank15
SFRs
Although USB RAM is available to the microcontroller
as data memory, the sections that are being accessed
by the SIE should not be accessed by the
microcontroller. A semaphore mechanism is used to
determine the access to a particular buffer at any given
time. This is discussed in Section 14.4.1.1 “Buffer
Ownership”.
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14.4.1
BD STATUS AND CONFIGURATION
14.4 Buffer Descriptors and the Buffer
Descriptor Table
Buffer descriptors not only define the size of an
endpoint buffer, but also determine its configuration
and control. Most of the configuration is done with the
BD Status register, BDnSTAT. Each BD has its own
unique and correspondingly numbered BDnSTAT
register.
The registers in Bank 4 are used specifically for end-
point buffer control in a structure known as the Buffer
Descriptor Table (BDT). This provides a flexible method
for users to construct and control endpoint buffers of
various lengths and configuration.
The BDT is composed of Buffer Descriptors (BD) which
are used to define and control the actual buffers in the
USB RAM space. Each BD, in turn, consists of four
registers, where n represents one of the 64 possible
BDs (range of 0 to 63):
FIGURE 14-6:
EXAMPLE OF A BUFFER
DESCRIPTOR
Address Registers
Contents
(xxh)
10h
80h
04h
400h
BD0STAT
BD0CNT
401h
402h
403h
Size of Block
• BDnSTAT: BD Status register
Buffer
Descriptor
BD0ADRL
BD0ADRH
• BDnCNT: BD Byte Count register
• BDnADRL: BD Address Low register
• BDnADRH: BD Address High register
Starting
Address
480h
BDs always occur as a four-byte block in the sequence,
BDnSTAT:BDnCNT:BDnADRL:BDnADRH. The address
of BDnSTAT is always an offset of (4n – 1) (in
hexadecimal) from 400h, with n being the buffer
descriptor number.
USB Data
Buffer
48Fh
Depending on the buffering configuration used
(Section 14.4.4 “Ping-Pong Buffering”), there are up
to 32, 33 or 64 sets of buffer descriptors. At a minimum,
the BDT must be at least 8 bytes long. This is because
the USB specification mandates that every device must
have Endpoint 0 with both input and output for initial
setup. Depending on the endpoint and buffering
configuration, the BDT can be as long as 256 bytes.
Note:
Memory regions are not to scale.
Unlike other control registers, the bit configuration for
the BDnSTAT register is context sensitive. There are
two distinct configurations, depending on whether the
microcontroller or the USB module is modifying the BD
and buffer at a particular time. Only three bit definitions
are shared between the two.
Although they can be thought of as Special Function
Registers, the Buffer Descriptor Status and Address
registers are not hardware mapped, as conventional
microcontroller SFRs in Bank 15 are. If the endpoint cor-
responding to a particular BD is not enabled, its registers
are not used. Instead of appearing as unimplemented
addresses, however, they appear as available RAM.
Only when an endpoint is enabled by setting the
UEPn<1> bit does the memory at those addresses
become functional as BD registers. As with any address
in the data memory space, the BD registers have an
indeterminate value on any device Reset.
14.4.1.1
Buffer Ownership
Because the buffers and their BDs are shared between
the CPU and the USB module, a simple semaphore
mechanism is used to distinguish which is allowed to
update the BD and associated buffers in memory.
This is done by using the UOWN bit (BDnSTAT<7>) as
a semaphore to distinguish which is allowed to update
the BD and associated buffers in memory. UOWN is the
only bit that is shared between the two configurations
of BDnSTAT.
A total of 256 bytes of address space in Bank 4 is
available for BDT and USB data RAM. In Ping-Pong
Buffer mode, all the 16 bidirectional endpoints can not
be implemented where BDT itself can be as long as
256 bytes. In the majority of USB applications, few
endpoints are required to be implemented. Hence, a
small portion of the 256 bytes will be used for BDT and
the rest can be used for USB data.
When UOWN is clear, the BD entry is “owned” by the
microcontroller core. When the UOWN bit is set, the BD
entry and the buffer memory are “owned” by the USB
peripheral. The core should not modify the BD or its
corresponding data buffer during this time. Note that
the microcontroller core can still read BDnSTAT while
the SIE owns the buffer and vice versa.
The buffer descriptors have a different meaning based
on the source of the register update. Prior to placing
ownership with the USB peripheral, the user can con-
figure the basic operation of the peripheral through the
BDnSTAT bits. During this time, the byte count and
buffer location registers can also be set.
An example of a BD for a 16-byte buffer, starting at
480h, is shown in Figure 14-6. A particular set of BD
registers is only valid if the corresponding endpoint has
been enabled using the UEPn register. All BD registers
are available in USB RAM. The BD for each endpoint
should be set up prior to enabling the endpoint.
© 2008 Microchip Technology Inc.
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When UOWN is set, the user can no longer depend on
the values that were written to the BDs. From this point,
the SIE updates the BDs as necessary, overwriting the
original BD values. The BDnSTAT register is updated
by the SIE with the token PID and the transfer count,
BDnCNT, is updated.
the USB RAM and the USB transfer complete interrupt
flag will not be set. The SIE will send an ACK token
back to the host to Acknowledge receipt, however. The
effects of the DTSEN bit on the SIE are summarized in
Table 14-3.
The Buffer Stall bit, BSTALL (BDnSTAT<2>), provides
support for control transfers, usually one-time stalls on
Endpoint 0. It also provides support for the
SET_FEATURE/CLEAR_FEATURE commands speci-
fied in Chapter 9 of the USB specification; typically,
continuous STALLs to any endpoint other than the
default control endpoint.
The BDnSTAT byte of the BDT should always be the
last byte updated when preparing to arm an endpoint.
The SIE will clear the UOWN bit when a transaction
has completed. The only exception to this is when KEN
is enabled and/or BSTALL is enabled.
No hardware mechanism exists to block access when
the UOWN bit is set. Thus, unexpected behavior can
occur if the microcontroller attempts to modify memory
when the SIE owns it. Similarly, reading such memory
may produce inaccurate data until the USB peripheral
returns ownership to the microcontroller.
The BSTALL bit enables buffer stalls. Setting BSTALL
causes the SIE to return a STALL token to the host if a
received token would use the BD in that location. The
EPSTALL bit in the corresponding UEPn control
register is set and a STALL interrupt is generated when
a STALL is issued to the host. The UOWN bit remains
set and the BDs are not changed unless a SETUP
token is received. In this case, the STALL condition is
cleared and the ownership of the BD is returned to the
microcontroller core.
14.4.1.2
BDnSTAT Register (CPU Mode)
When UOWN = 0, the microcontroller core owns the
BD. At this point, the other seven bits of the register
take on control functions.
The BD9:BD8 bits (BDnSTAT<1:0>) store the two most
significant digits of the SIE byte count; the lower 8 digits
are stored in the corresponding BDnCNT register. See
Section 14.4.2 “BD Byte Count” for more
information.
The Data Toggle Sync Enable bit, DTSEN
(BDnSTAT<3>), controls data toggle parity checking.
Setting DTSEN enables data toggle synchronization by
the SIE. When enabled, it checks the data packet’s
parity against the value of DTS (BDnSTAT<6>). If a
packet arrives with an incorrect synchronization, the
data will essentially be ignored. It will not be written to
TABLE 14-3: EFFECT OF DTSEN BIT ON ODD/EVEN (DATA0/DATA1) PACKET RECEPTION
BDnSTAT Settings
Device Response after Receiving Packet
Handshake UOWN TRNIF BDnSTAT and USTAT Status
Updated
OUT Packet
from Host
DTSEN
DTS
DATA0
1
1
1
1
0
x
0
0
1
1
x
x
ACK
ACK
ACK
ACK
ACK
NAK
0
1
0
1
0
1
1
0
1
0
1
0
DATA1
Not Updated
Updated
DATA1
DATA0
Not Updated
Updated
Either
Either, with error
Not Updated
Legend: x= don’t care
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REGISTER 14-5: BDnSTAT: BUFFER DESCRIPTOR n STATUS REGISTER (BD0STAT THROUGH
BD63STAT), CPU MODE (DATA IS WRITTEN TO THE SIDE)
R/W-x
UOWN(1)
R/W-x
DTS(2)
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
BC9
R/W-x
BC8
(3)
(3)
—
—
DTSEN
BSTALL
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7
bit 6
UOWN: USB Own bit(1)
0= The microcontroller core owns the BD and its corresponding buffer
DTS: Data Toggle Synchronization bit(2)
1= Data 1 packet
0= Data 0 packet
bit 5-4
bit 3
Reserved: These bits should always be programmed to ‘0’(3)
DTSEN: Data Toggle Synchronization Enable bit
1= Data toggle synchronization is enabled; data packets with incorrect Sync value will be ignored
except for a SETUP transaction, which is accepted even if the data toggle bits do not match.
0= No data toggle synchronization is performed
bit 2
BSTALL: Buffer Stall Enable bit
1= Buffer stall enabled; STALL handshake issued if a token is received that would use the BD in the
given location (UOWN bit remains set, BD value is unchanged)
0= Buffer stall disabled
bit 1-0
BC9:BC8: Byte Count 9 and 8 bits
The byte count bits represent the number of bytes that will be transmitted for an IN token or received
during an OUT token. Together with BC<7:0>, the valid byte counts are 0-1023.
Note 1: This bit must be initialized by the user to the desired value prior to enabling the USB module.
2: This bit is ignored unless DTSEN = 1.
3: If these bits are set, USB communication may not work. Hence, these bits should always be maintained
as ‘0’.
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byte count, the data packet will be rejected and a NAK
handshake will be generated. When this happens, the
byte count will not be updated.
14.4.1.3
BDnSTAT Register (SIE Mode)
When the BD and its buffer are owned by the SIE, most
of the bits in BDnSTAT take on a different meaning. The
configuration is shown in Register 14-6. Once UOWN is
set, any data or control settings previously written there
by the user will be overwritten with data from the SIE.
The 10-bit byte count is distributed over two registers.
The lower 8 bits of the count reside in the BDnCNT
register. The upper two bits reside in BDnSTAT<1:0>.
This represents a valid byte range of 0 to 1023.
The BDnSTAT register is updated by the SIE with the
token Packet Identifier (PID) which is stored in
BDnSTAT<5:3>. The transfer count in the
corresponding BDnCNT register is updated. Values
that overflow the 8-bit register carry over to the two
most significant digits of the count, stored in
BDnSTAT<1:0>.
14.4.3
BD ADDRESS VALIDATION
The BD Address register pair contains the starting RAM
address location for the corresponding endpoint buffer.
For an endpoint starting location to be valid, it must fall
in the range of the USB RAM, 400h to 4FFh. No
mechanism is available in hardware to validate the BD
address.
14.4.2
BD BYTE COUNT
If the value of the BD address does not point to an
address in the USB RAM, or if it points to an address
within another endpoint’s buffer, data is likely to be lost
or overwritten. Similarly, overlapping a receive buffer
(OUT endpoint) with a BD location in use can yield
The byte count represents the total number of bytes
that will be transmitted during an IN transfer. After an IN
transfer, the SIE will return the number of bytes sent to
the host.
For an OUT transfer, the byte count represents the
maximum number of bytes that can be received and
stored in USB RAM. After an OUT transfer, the SIE will
return the actual number of bytes received. If the
number of bytes received exceeds the corresponding
unexpected
results.
When
developing
USB
applications, the user may want to consider the
inclusion of software-based address validation in their
code.
REGISTER 14-6: BDnSTAT: BUFFER DESCRIPTOR n STATUS REGISTER (BD0STAT THROUGH
BD63STAT), SIE MODE (DATA RETURNED BY THE SIDE TO THE
MICROCONTROLLER)
R/W-x
U-x
—
R/W-x
PID3
R/W-x
PID2
R/W-x
PID1
R/W-x
PID0
R/W-x
BC9
R/W-x
BC8
UOWN
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7
UOWN: USB Own bit
1= The SIE owns the BD and its corresponding buffer
Reserved: Not written by the SIE
bit 6
bit 5-2
PID3:PID0: Packet Identifier bits
The received token PID value of the last transfer (IN, OUT or SETUP transactions only).
BC9:BC8: Byte Count 9 and 8 bits
bit 1-0
These bits are updated by the SIE to reflect the actual number of bytes received on an OUT transfer
and the actual number of bytes transmitted on an IN transfer.
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by the SIE), the pointer is toggled to the ODD BD. After
the completion of the next transaction, the pointer is
toggled back to the EVEN BD and so on.
14.4.4
PING-PONG BUFFERING
An endpoint is defined to have a ping-pong buffer when
it has two sets of BD entries: one set for an EVEN
transfer and one set for an ODD transfer. This allows
the CPU to process one BD while the SIE is processing
the other BD. Double-buffering BDs in this way allows
for maximum throughput to/from the USB.
The EVEN/ODD status of the last transaction is stored
in the PPBI bit of the USTAT register. The user can
reset all Ping-Pong Pointers to EVEN using the
PPBRST bit.
Figure 14-7 shows the three different modes of
operation and how USB RAM is filled with the BDs.
The USB module supports three modes of operation:
• No ping-pong support
BDs have a fixed relationship to a particular endpoint,
depending on the buffering configuration. The mapping
of BDs to endpoints is detailed in Table 14-4. This
relationship also means that gaps may occur in the
BDT if endpoints are not enabled contiguously. This
theoretically means that the BDs for disabled endpoints
could be used as buffer space. In practice, users
should avoid using such spaces in the BDT unless a
method of validating BD addresses is implemented.
• Ping-pong buffer support for OUT Endpoint 0 only
• Ping-pong buffer support for all endpoints
The ping-pong buffer settings are configured using the
PPB1:PPB0 bits in the UCFG register.
The USB module keeps track of the Ping-Pong Pointer
individually for each endpoint. All pointers are initially
reset to the EVEN BD when the module is enabled.
After the completion of a transaction (UOWN cleared
FIGURE 14-7:
BUFFER DESCRIPTOR TABLE MAPPING FOR BUFFERING MODES
PPB1:PPB0 = 10
Ping-Pong Buffers on All EPs
PPB1:PPB0 = 01
Ping-Pong Buffer on EP0 OUT
400h
PPB1:PPB0 = 00
No Ping-Pong Buffers
400h
400h
EP0 OUT EVEN
Descriptor
EP0 OUT
Descriptor
EP0 OUT EVEN
Descriptor
EP0 OUT ODD
Descriptor
EP0 IN
Descriptor
EP0 OUT ODD
Descriptor
EP0 IN EVEN
Descriptor
EP1 OUT
Descriptor
EP0 IN
Descriptor
EP1 IN
Descriptor
EP0 IN ODD
Descriptor
EP1 OUT
Descriptor
EP1 OUT EVEN
Descriptor
EP1 IN
Descriptor
EP1 OUT ODD
Descriptor
EP15 IN
Descriptor
47Fh
EP1 IN EVEN
Descriptor
EP15 IN
Descriptor
483h
EP1 IN ODD
Descriptor
Available
as
Data RAM
Available
as
Data RAM
EP15 IN ODD
Descriptor
4FFh
4FFh
4FFh
Maximum Memory Used: 256 bytes
Maximum BDs: 64 (BD0 to BD63)
Maximum Memory Used: 128 bytes
Maximum BDs: 32 (BD0 to BD31)
Maximum Memory Used: 132 bytes
Maximum BDs: 33 (BD0 to BD32)
Note:
Memory area not shown to scale.
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TABLE 14-4: ASSIGNMENT OF BUFFER DESCRIPTORS FOR THE DIFFERENT
BUFFERING MODES
BDs Assigned to Endpoint
Mode 0
(No Ping-Pong)
Mode 1
(Ping-Pong on EP0 OUT)
Mode 2
(Ping-Pong on all EPs)
Endpoint
Out
In
Out
In
Out
In
0
1
0
1
0 (E), 1 (O)
2
0 (E), 1 (O)
4 (E), 5 (O)
2 (E), 3 (O)
6 (E), 7 (O)
2
3
3
4
2
4
5
5
6
8 (E), 9 (O)
10 (E), 11 (O)
14 (E), 15 (O)
18 (E), 19 (O)
22 (E), 23 (O)
26 (E), 27 (O)
30 (E), 31 (O)
34 (E), 35 (O)
38 (E), 39 (O)
42 (E), 43 (O)
46 (E), 47 (O)
50 (E), 51 (O)
54 (E), 55 (O)
58 (E), 59 (O)
62 (E), 63 (O)
3
6
7
7
8
12 (E), 13 (O)
16 (E), 17 (O)
20 (E), 21 (O)
24 (E), 25 (O)
28 (E), 29 (O)
32 (E), 33 (O)
36 (E), 37 (O)
40 (E), 41 (O)
44 (E), 45 (O)
48 (E), 49 (O)
52 (E), 53 (O)
56 (E), 57 (O)
60 (E), 61 (O)
4
8
9
9
10
12
14
16
18
20
22
24
26
28
30
32
5
10
12
14
16
18
20
22
24
26
28
30
11
13
15
17
19
21
23
25
27
29
31
11
13
15
17
19
21
23
25
27
29
31
6
7
8
9
10
11
12
13
14
15
Legend: (E) = EVEN transaction buffer, (O) = ODD transaction buffer
TABLE 14-5: SUMMARY OF USB BUFFER DESCRIPTOR TABLE REGISTERS
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
BC9
Bit 0
BDnSTAT(1)
UOWN
DTS(4)
PID3(2)
PID2(2)
PID1(2)
PID0(2)
BC8
DTSEN(3)
BSTALL(3)
BDnCNT(1)
Byte Count
BDnADRL(1) Buffer Address Low
BDnADRH(1) Buffer Address High
Note 1: For buffer descriptor registers, n may have a value of 0 to 63. For the sake of brevity, all 64 registers are
shown as one generic prototype. All registers have indeterminate Reset values (xxxx xxxx).
2: Bits 5 through 2 of the BDnSTAT register are used by the SIE to return PID3:PID0 values once the register
is turned over to the SIE (UOWN bit is set). Once the registers have been under SIE control, the values
written for DTSEN and BSTALL are no longer valid.
3: Prior to turning the buffer descriptor over to the SIE (UOWN bit is cleared), bits 3 and 2 of the BDnSTAT
register are used to configure the DTSEN and BSTALL settings.
4: This bit is ignored unless DTSEN = 1.
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Figure 14-8 shows the interrupt logic for the USB
module. There are two layers of interrupt registers in
the USB module. The top level consists of overall USB
status interrupts; these are enabled and flagged in the
UIE and UIR registers, respectively. The second level
consists of USB error conditions, which are enabled
and flagged in the UEIR and UEIE registers. An
interrupt condition in any of these triggers a USB Error
Interrupt Flag (UERRIF) in the top level.
14.5 USB Interrupts
The USB module can generate multiple interrupt
conditions. To accommodate all of these interrupt
sources, the module is provided with its own interrupt
logic structure, similar to that of the microcontroller.
USB interrupts are enabled with one set of control regis-
ters and trapped with a separate set of flag registers. All
sources are funneled into a single USB interrupt
request, USBIF (PIR2<5>), in the microcontroller’s
interrupt logic.
Interrupts may be used to trap routine events in a USB
transaction. Figure 14-9 shows some common events
within a USB frame and their corresponding interrupts.
FIGURE 14-8:
USB INTERRUPT LOGIC FUNNEL
Top Level USB Interrupts
Second Level USB Interrupts
(USB Status Interrupts)
(USB Error Conditions)
UIR (Flag) and UIE (Enable) Registers
UEIR (Flag) and UEIE (Enable) Registers
SOFIF
SOFIE
BTSEF
BTSEE
TRNIF
TRNIE
USBIF
BTOEF
BTOEE
IDLEIF
IDLEIE
DFN8EF
DFN8EE
UERRIF
UERRIE
CRC16EF
CRC16EE
STALLIF
STALLIE
CRC5EF
CRC5EE
PIDEF
PIDEE
ACTVIF
ACTVIE
URSTIF
URSTIE
FIGURE 14-9:
EXAMPLE OF A USB TRANSACTION AND INTERRUPT EVENTS
To Host
ACK
From Host
From Host
Data
Set TRNIF
Set TRNIF
Set TRNIF
SETUPToken
From Host
IN Token
To Host
Data
From Host
ACK
USB Reset
URSTIF
From Host
From Host
To Host
ACK
Start-of-Frame (SOF)
OUT Token Empty Data
Transaction
SOFIF
Transaction
Complete
SOF
RESET
Differential Data
SOF
SETUP
DATA
STATUS
Control Transfer(1)
1 ms Frame
Note 1:
The control transfer shown here is only an example showing events that can occur for every transaction. Typical control transfers
will spread across multiple frames.
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When the USB module is in the Low-Power Suspend
mode (UCON<1> = 1), the SIE does not get clocked.
When in this state, the SIE cannot process packets,
and therefore, cannot detect new interrupt conditions
other than the Activity Detect Interrupt, Flag ACTVIF.
The ACTVIF bit is typically used by USB firmware to
detect when the microcontroller should bring the USB
module out of the Low-Power Suspend mode
(UCON<1> = 0).
14.5.1
USB INTERRUPT STATUS
REGISTER (UIR)
The USB Interrupt Status register (Register 14-7)
contains the flag bits for each of the USB status
interrupt sources. Each of these sources has a
corresponding interrupt enable bit in the UIE register. All
of the USB status flags are ORed together to generate
the USBIF interrupt flag for the microcontroller’s
interrupt funnel.
Once an interrupt bit has been set by the SIE, it must
be cleared by software by writing a ‘0’. The flag bits
can also be set in software which can aid in firmware
debugging.
REGISTER 14-7: UIR: USB INTERRUPT STATUS REGISTER
U-0
—
R/W-0
SOFIF
R/W-0
R/W-0
IDLEIF(1)
R/W-0
TRNIF(2)
R/W-0
ACTVIF(3)
R-0
UERRIF(4)
R/W-0
STALLIF
URSTIF
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7
bit 6
Unimplemented: Read as ‘0’
SOFIF: Start-of-Frame Token Interrupt bit
1= A Start-of-Frame token received by the SIE
0= No Start-of-Frame token received by the SIE
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
STALLIF: A STALL Handshake Interrupt bit
1= A STALL handshake was sent by the SIE
0= A STALL handshake has not been sent
IDLEIF: Idle Detect Interrupt bit(1)
1= Idle condition detected (constant Idle state of 3 ms or more)
0= No Idle condition detected
TRNIF: Transaction Complete Interrupt bit(2)
1= Processing of pending transaction is complete; read USTAT register for endpoint information
0= Processing of pending transaction is not complete or no transaction is pending
ACTVIF: Bus Activity Detect Interrupt bit(3)
1= Activity on the D+/D- lines was detected
0= No activity detected on the D+/D- lines
UERRIF: USB Error Condition Interrupt bit(4)
1= An unmasked error condition has occurred
0= No unmasked error condition has occurred.
URSTIF: USB Reset Interrupt bit
1= Valid USB Reset occurred; 00h is loaded into UADDR register
0= No USB Reset has occurred
Note 1: Once an Idle state is detected, the user may want to place the USB module in Suspend mode.
2: Clearing this bit will cause the USTAT FIFO to advance (valid only for IN, OUT and SETUP tokens).
3: This bit is typically unmasked only following the detection of a UIDLE interrupt event.
4: Only error conditions enabled through the UEIE register will set this bit. This bit is a status bit only and
cannot be set or cleared by the user.
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© 2008 Microchip Technology Inc.
PIC18F2450/4450
14.5.1.1
Bus Activity Detect Interrupt Bit
(ACTVIF)
EXAMPLE 14-1:
CLEARING ACTVIF BIT
(UIR<2>)
The ACTVIF bit cannot be cleared immediately after
the USB module wakes up from Suspend or while the
USB module is suspended. A few clock cycles are
required to synchronize the internal hardware state
machine before the ACTVIF bit can be cleared by
firmware. Clearing the ACTVIF bit before the internal
hardware is synchronized may not have an effect on
the value of ACTVIF. Additionally, if the USB module
uses the clock from the 96 MHz PLL source, then after
clearing the SUSPND bit, the USB module may not be
immediately operational while waiting for the 96 MHz
PLL to lock. The application code should clear the
ACTVIF bit as shown in Example 14-1.
Assembly:
BCF
UCON, SUSPND
LOOP:
BTFSS
BRA
BCF
UIR, ACTVIF
DONE
UIR, ACTVIF
LOOP
BRA
DONE
C:
UCONbits.SUSPND = 0;
while (UIRbits.ACTVIF){UIRbits.ACTVIF = 0};
Only one ACTVIF interrupt is generated when resum-
ing from the USB bus Idle condition. If user firmware
clears the ACTVIF bit, the bit will not immediately
become set again, even when there is continuous bus
traffic. Bus traffic must cease long enough to generate
another IDLEIF condition before another ACTVIF
interrupt can be generated.
© 2008 Microchip Technology Inc.
DS39760D-page 145
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The values in this register only affect the propagation
of an interrupt condition to the microcontroller’s
interrupt logic. The flag bits are still set by their
interrupt conditions, allowing them to be polled and
serviced without actually generating an interrupt.
14.5.2
USB INTERRUPT ENABLE
REGISTER (UIE)
The USB Interrupt Enable register (Register 14-8)
contains the enable bits for the USB status interrupt
sources. Setting any of these bits will enable the
respective interrupt source in the UIR register.
REGISTER 14-8: UIE: USB INTERRUPT ENABLE REGISTER
U-0
—
R/W-0
SOFIE
R/W-0
R/W-0
R/W-0
TRNIE
R/W-0
R/W-0
R/W-0
STALLIE
IDLEIE
ACTVIE
UERRIE
URSTIE
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7
bit 6
Unimplemented: Read as ‘0’
SOFIE: Start-of-Frame Token Interrupt Enable bit
1= Start-of-Frame token interrupt enabled
0= Start-of-Frame token interrupt disabled
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
STALLIE: STALL Handshake Interrupt Enable bit
1= STALL interrupt enabled
0= STALL interrupt disabled
IDLEIE: Idle Detect Interrupt Enable bit
1= Idle detect interrupt enabled
0= Idle detect interrupt disabled
TRNIE: Transaction Complete Interrupt Enable bit
1= Transaction interrupt enabled
0= Transaction interrupt disabled
ACTVIE: Bus Activity Detect Interrupt Enable bit
1= Bus activity detect interrupt enabled
0= Bus activity detect interrupt disabled
UERRIE: USB Error Interrupt Enable bit
1= USB error interrupt enabled
0= USB error interrupt disabled
URSTIE: USB Reset Interrupt Enable bit
1= USB Reset interrupt enabled
0= USB Reset interrupt disabled
DS39760D-page 146
© 2008 Microchip Technology Inc.
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Each error bit is set as soon as the error condition is
detected. Thus, the interrupt will typically not
correspond with the end of a token being processed.
14.5.3
USB ERROR INTERRUPT STATUS
REGISTER (UEIR)
The USB Error Interrupt Status register (Register 14-9)
contains the flag bits for each of the error sources
within the USB peripheral. Each of these sources is
controlled by a corresponding interrupt enable bit in
the UEIE register. All of the USB error flags are ORed
together to generate the USB Error Interrupt Flag
(UERRIF) at the top level of the interrupt logic.
Once an interrupt bit has been set by the SIE, it must
be cleared by software by writing a ‘0’.
REGISTER 14-9: UEIR: USB ERROR INTERRUPT STATUS REGISTER
R/C-0
U-0
—
U-0
—
R/C-0
R/C-0
R/C-0
R/C-0
R/C-0
BTSEF
BTOEF
DFN8EF
CRC16EF
CRC5EF
PIDEF
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
C = Clearable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7
BTSEF: Bit Stuff Error Flag bit
1= A bit stuff error has been detected
0= No bit stuff error
bit 6-5
bit 4
Unimplemented: Read as ‘0’
BTOEF: Bus Turnaround Time-out Error Flag bit
1= Bus turnaround time-out has occurred (more than 16 bit times of Idle from previous EOP elapsed)
0= No bus turnaround time-out
bit 3
bit 2
bit 1
bit 0
DFN8EF: Data Field Size Error Flag bit
1= The data field was not an integral number of bytes
0= The data field was an integral number of bytes
CRC16EF: CRC16 Failure Flag bit
1= The CRC16 failed
0= The CRC16 passed
CRC5EF: CRC5 Host Error Flag bit
1= The token packet was rejected due to a CRC5 error
0= The token packet was accepted
PIDEF: PID Check Failure Flag bit
1= PID check failed
0= PID check passed
© 2008 Microchip Technology Inc.
DS39760D-page 147
PIC18F2450/4450
As with the UIE register, the enable bits only affect the
propagation of an interrupt condition to the
microcontroller’s interrupt logic. The flag bits are still
set by their interrupt conditions, allowing them to be
polled and serviced without actually generating an
interrupt.
14.5.4
USB ERROR INTERRUPT ENABLE
REGISTER (UEIE)
The USB Error Interrupt Enable register (Register 14-10)
contains the enable bits for each of the USB error
interrupt sources. Setting any of these bits will enable the
respective error interrupt source in the UEIR register to
propagate into the UERR bit at the top level of the
interrupt logic.
REGISTER 14-10: UEIE: USB ERROR INTERRUPT ENABLE REGISTER
R/W-0
U-0
—
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
PIDEE
BTSEE
BTOEE
DFN8EE
CRC16EE
CRC5EE
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7
BTSEE: Bit Stuff Error Interrupt Enable bit
1= Bit stuff error interrupt enabled
0= Bit stuff error interrupt disabled
bit 6-5
bit 4
Unimplemented: Read as ‘0’
BTOEE: Bus Turnaround Time-out Error Interrupt Enable bit
1= Bus turnaround time-out error interrupt enabled
0= Bus turnaround time-out error interrupt disabled
bit 3
bit 2
bit 1
bit 0
DFN8EE: Data Field Size Error Interrupt Enable bit
1= Data field size error interrupt enabled
0= Data field size error interrupt disabled
CRC16EE: CRC16 Failure Interrupt Enable bit
1= CRC16 failure interrupt enabled
0= CRC16 failure interrupt disabled
CRC5EE: CRC5 Host Error Interrupt Enable bit
1= CRC5 host error interrupt enabled
0= CRC5 host error interrupt disabled
PIDEE: PID Check Failure Interrupt Enable bit
1= PID check failure interrupt enabled
0= PID check failure interrupt disabled
DS39760D-page 148
© 2008 Microchip Technology Inc.
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In order to meet compliance specifications, the USB
module (and the D+ or D- pull-up resistor) should not
be enabled until the host actively drives VBUS high. One
of the I/O pins may be used for this purpose.
14.6 USB Power Modes
Many USB applications will likely have several different
sets of power requirements and configuration. The
most common power modes encountered are Bus
Power Only, Self-Power Only and Dual Power with
Self-Power Dominance. The most common cases are
presented here.
The application should never source any current onto
the 5V VBUS pin of the USB cable.
FIGURE 14-11:
SELF-POWER ONLY
Attach Sense
14.6.1
BUS POWER ONLY
VBUS
~5V
I/O pin
VDD
In Bus Power Only mode, all power for the application
is drawn from the USB (Figure 14-10). This is
effectively the simplest power method for the device.
100 kΩ
VSELF
~5V
In order to meet the inrush current requirements of the
USB 2.0 specifications, the total effective capacitance
appearing across VBUS and ground must be no more
than 10 μF; otherwise, some kind of inrush limiting is
required. For more details, see Section 7.2.4 of the
USB 2.0 specification.
100 kΩ
VUSB
VSS
According to the USB 2.0 specification, all USB devices
must also support a Low-Power Suspend mode. In the
USB Suspend mode, devices must consume no more
than 500 A (or 2.5 mA for high-powered devices that
are capable of remote wake-up) from the 5V VBUS line
of the USB cable.
14.6.3
DUAL POWER WITH SELF-POWER
DOMINANCE
Some applications may require a dual power option.
This allows the application to use internal power prima-
rily, but switch to power from the USB when no internal
power is available. Figure 14-12 shows a simple Dual
Power with Self-Power Dominance example, which
automatically switches between Self-Power Only and
USB Bus Power Only modes.
The host signals the USB device to enter the Suspend
mode by stopping all USB traffic to that device for more
than 3 ms. This condition will set the IDLEIF bit in the
UIR register.
During the USB Suspend mode, the D+ or D- pull-up
resistor must remain active, which will consume some
of the allowed suspend current: 500A/2.5 mA budget.
FIGURE 14-12:
DUAL POWER EXAMPLE
100 kΩ
Attach Sense
I/O pin
FIGURE 14-10:
BUS POWER ONLY
VBUS
~5V
VDD
VBUS
~5V
VDD
100 kΩ
VUSB
VSS
VSELF
~5V
VUSB
VSS
Dual power devices must also meet all of the special
requirements for inrush current and Suspend mode
current, and must not enable the USB module until
VBUS is driven high. For descriptions of those require-
ments, see Section 14.6.1 “Bus Power Only” and
Section 14.6.2 “Self-Power Only”. Additionally, dual
power devices must never source current onto the 5V
VUSB pin of the USB cable.
14.6.2
SELF-POWER ONLY
In Self-Power Only mode, the USB application provides
its own power, with very little power being pulled from
the USB. Figure 14-11 shows an example. Note that an
attach indication is added to show when the USB has
been connected and the host is actively powering
VBUS.
Note:
Users should keep in mind the limits for
devices drawing power from the USB.
According to USB Specification 2.0, this
cannot exceed 100 mA per low-power
device or 500 mA per high-power device.
© 2008 Microchip Technology Inc.
DS39760D-page 149
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14.7 Oscillator
14.8 USB Firmware and Drivers
The USB module has specific clock requirements. For
full-speed operation, the clock source must be 48 MHz.
Even so, the microcontroller core and other peripherals
are not required to run at that clock speed or even from
the same clock source. Available clocking options are
described in detail in Section 2.3 “Oscillator Settings
for USB”.
Microchip provides a number of application-specific
resources, such as USB firmware and driver support.
Refer to www.microchip.com for the latest firmware and
driver support.
TABLE 14-6: REGISTERS ASSOCIATED WITH USB MODULE OPERATION(1)
Details
on Page:
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
INTCON
IPR2
GIE/GIEH PEIE/GIEL
TMR0IE
USBIP
USBIF
USBIE
SE0
—
INT0IE
—
RBIE
—
TMR0IF
HLVDIP
HLVDIF
HLVDIE
RESUME
FSEN
INT0IF
—
RBIF
—
49
51
51
51
52
52
52
52
52
52
52
52
52
52
52
52
52
52
52
52
52
52
52
52
51
51
51
51
51
51
OSCFIP
—
PIR2
OSCFIF
—
—
—
—
—
PIE2
OSCFIE
—
—
—
—
—
—
UCON
UCFG
USTAT
UADDR
UFRML
UFRMH
UIR
PPBRST
PKTDIS
UPUEN
ENDP1
ADDR4
FRM4
—
USBEN
UTRDIS
ENDP0
ADDR3
FRM3
—
SUSPND
PPB1
—
UTEYE
—
UOEMON
PPB0
ENDP3
ADDR6
FRM6
—
ENDP2
ADDR5
FRM5
—
DIR
PPBI
—
—
ADDR2
FRM2
ADDR1
FRM1
ADDR0
FRM0
FRM7
—
FRM10
ACTVIF
ACTVIE
CRC16EF
CRC16EE
FRM9
FRM8
—
SOFIF
SOFIE
—
STALLIF
STALLIE
—
IDLEIF
IDLEIE
BTOEF
BTOEE
TRNIF
TRNIE
DFN8EF
DFN8EE
UERRIF
UERRIE
CRC5EF
CRC5EE
EPINEN
EPINEN
EPINEN
EPINEN
EPINEN
EPINEN
EPINEN
EPINEN
EPINEN
EPINEN
EPINEN
EPINEN
EPINEN
EPINEN
EPINEN
EPINEN
URSTIF
URSTIE
PIDEF
UIE
—
UEIR
BTSEF
BTSEE
—
UEIE
—
—
PIDEE
UEP0
UEP1
UEP2
UEP3
UEP4
UEP5
UEP6
UEP7
UEP8
UEP9
UEP10
UEP11
UEP12
UEP13
UEP14
UEP15
Legend:
—
—
EPHSHK EPCONDIS EPOUTEN
EPHSHK EPCONDIS EPOUTEN
EPHSHK EPCONDIS EPOUTEN
EPHSHK EPCONDIS EPOUTEN
EPHSHK EPCONDIS EPOUTEN
EPHSHK EPCONDIS EPOUTEN
EPHSHK EPCONDIS EPOUTEN
EPHSHK EPCONDIS EPOUTEN
EPHSHK EPCONDIS EPOUTEN
EPHSHK EPCONDIS EPOUTEN
EPHSHK EPCONDIS EPOUTEN
EPHSHK EPCONDIS EPOUTEN
EPHSHK EPCONDIS EPOUTEN
EPHSHK EPCONDIS EPOUTEN
EPHSHK EPCONDIS EPOUTEN
EPHSHK EPCONDIS EPOUTEN
EPSTALL
EPSTALL
EPSTALL
EPSTALL
EPSTALL
EPSTALL
EPSTALL
EPSTALL
EPSTALL
EPSTALL
EPSTALL
EPSTALL
EPSTALL
EPSTALL
EPSTALL
EPSTALL
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
— = unimplemented, read as ‘0’. Shaded cells are not used by the USB module.
Note 1: This table includes only those hardware mapped SFRs located in Bank 15 of the data memory space. The Buffer
Descriptor registers, which are mapped into Bank 4 and are not true SFRs, are listed separately in Table 14-5.
DS39760D-page 150
© 2008 Microchip Technology Inc.
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14.9.3
TRANSFERS
14.9 Overview of USB
There are four transfer types defined in the USB
specification.
This section presents some of the basic USB concepts
and useful information necessary to design a USB
device. Although much information is provided in this
section, there is a plethora of information provided
within the USB specifications and class specifications.
Thus, the reader is encouraged to refer to the USB
specifications for more information (www.usb.org). If
you are very familiar with the details of USB, then this
section serves as a basic, high-level refresher of USB.
• Isochronous: This type provides a transfer
method for large amounts of data (up to
1023 bytes) with timely delivery ensured;
however, the data integrity is not ensured. This is
good for streaming applications where small data
loss is not critical, such as audio.
• Bulk: This type of transfer method allows for large
amounts of data to be transferred with ensured
data integrity; however, the delivery timeliness is
not ensured.
14.9.1
LAYERED FRAMEWORK
USB device functionality is structured into a layered
framework graphically shown in Figure 14-13. Each
level is associated with a functional level within the
device. The highest layer, other than the device, is the
configuration. A device may have multiple configura-
tions. For example, a particular device may have
multiple power requirements based on Self-Power Only
or Bus Power Only modes.
• Interrupt: This type of transfer provides for
ensured timely delivery for small blocks of data;
plus data integrity is ensured.
• Control: This type provides for device setup
control.
While full-speed devices support all transfer types,
low-speed devices are limited to interrupt and control
transfers only.
For each configuration, there may be multiple
interfaces. Each interface could support a particular
mode of that configuration.
14.9.4
POWER
Below the interface is the endpoint(s). Data is directly
moved at this level. There can be as many as
16 bidirectional endpoints. Endpoint 0 is always a
control endpoint and by default, when the device is on
the bus, Endpoint 0 must be available to configure the
device.
Power is available from the Universal Serial Bus. The
USB specification defines the bus power requirements.
Devices may either be self-powered or bus powered.
Self-powered devices draw power from an external
source, while bus powered devices use power supplied
from the bus.
14.9.2
FRAMES
Information communicated on the bus is grouped into
1 ms time slots, referred to as frames. Each frame can
contain many transactions to various devices and
endpoints. Figure 14-9 shows an example of
transaction within a frame.
a
FIGURE 14-13:
USB LAYERS
Device
To Other Configurations (if any)
Configuration
To Other Interfaces (if any)
Interface
Endpoint
Interface
Endpoint
Endpoint
Endpoint
Endpoint
© 2008 Microchip Technology Inc.
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The USB specification limits the power taken from the
bus. Each device is ensured 100 mA at approximately 5V
(one-unit load). Additional power may be requested, up
to a maximum of 500 mA. Note that power above a one-
unit load is a request and the host or hub is not obligated
to provide the extra current. Thus, a device capable of
consuming more than a one-unit load must be able to
maintain a low-power configuration of a one-unit load or
less, if necessary.
14.9.6.2
Configuration Descriptor
The configuration descriptor provides information on
the power requirements of the device and how many
different interfaces are supported when in this
configuration. There may be more than one configura-
tion for a device (i.e., low-power and high-power
configurations).
14.9.6.3
Interface Descriptor
The USB specification also defines a Suspend mode.
In this situation, current must be limited to 500 μA,
averaged over 1 second. A device must enter a
Suspend state after 3 ms of inactivity (i.e., no SOF
tokens for 3 ms). A device entering Suspend mode
must drop current consumption within 10 ms after
Suspend mode. Likewise, when signaling a wake-up,
the device must signal a wake-up within 10 ms of
drawing current above the Suspend limit.
The interface descriptor details the number of
endpoints used in this interface, as well as the class of
the interface. There may be more than one interface for
a configuration.
14.9.6.4
Endpoint Descriptor
The endpoint descriptor identifies the transfer type
(Section 14.9.3 “Transfers”) and direction, as well as
some other specifics for the endpoint. There may be
many endpoints in a device and endpoints may be
shared in different configurations.
14.9.5
ENUMERATION
When the device is initially attached to the bus, the host
enters an enumeration process in an attempt to identify
the device. Essentially, the host interrogates the device,
gathering information such as power consumption, data
rates and sizes, protocol and other descriptive
information; descriptors contain this information. A
typical enumeration process would be as follows:
14.9.6.5
String Descriptor
Many of the previous descriptors reference one or
more string descriptors. String descriptors provide
human readable information about the layer
(Section 14.9.1
“Layered
Framework”)
they
describe. Often these strings show up in the host to
help the user identify the device. String descriptors are
generally optional to save memory and are encoded in
a unicode format.
1. USB Reset: Reset the device. Thus, the device
is not configured and does not have an address
(address 0).
2. Get Device Descriptor: The host requests a
small portion of the device descriptor.
14.9.7
BUS SPEED
3. USB Reset: Reset the device again.
Each USB device must indicate its bus presence and
speed to the host. This is accomplished through a
1.5 kΩ resistor which is connected to the bus at the
time of the attachment event.
4. Set Address: The host assigns an address to the
device.
5. Get Device Descriptor: The host retrieves the
device descriptor, gathering info such as
manufacturer, type of device, maximum control
packet size.
Depending on the speed of the device, the resistor
either pulls up the D+ or D- line to 3.3V. For a low-
speed device, the pull-up resistor is connected to the
D- line. For a full-speed device, the pull-up resistor is
connected to the D+ line.
6. Get configuration descriptors.
7. Get any other descriptors.
8. Set a configuration.
14.9.8
CLASS SPECIFICATIONS AND
DRIVERS
The exact enumeration process depends on the host.
USB specifications include class specifications which
operating system vendors optionally support.
Examples of classes include Audio, Mass Storage,
Communications and Human Interface (HID). In most
cases, a driver is required at the host side to ‘talk’ to the
USB device. In custom applications, a driver may need
to be developed. Fortunately, drivers are available for
most common host systems for the most common
classes of devices. Thus, these drivers can be reused.
14.9.6
DESCRIPTORS
There are eight different standard descriptor types of
which five are most important for this device.
14.9.6.1
Device Descriptor
The device descriptor provides general information,
such as manufacturer, product number, serial number,
the class of the device and the number of configurations.
There is only one device descriptor.
DS39760D-page 152
© 2008 Microchip Technology Inc.
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The pins of the Enhanced USART are multiplexed
with PORTC. In order to configure RC6/TX/CK and
RC7/RX/DT as an EUSART:
15.0 ENHANCED UNIVERSAL
SYNCHRONOUS RECEIVER
TRANSMITTER (EUSART)
• bit SPEN (RCSTA<7>) must be set (= 1)
• bit TRISC<7> must be set (= 1)
The Universal Synchronous Asynchronous Receiver
Transmitter (USART) module is one of the two serial
I/O modules. (USART is also known as a Serial
Communications Interface or SCI.) The USART can be
configured as a full-duplex asynchronous system that
can communicate with peripheral devices, such as
CRT terminals and personal computers. It can also be
configured as a half-duplex synchronous system that
can communicate with peripheral devices, such as A/D
or D/A integrated circuits, serial EEPROMs and so on.
• bit TRISC<6> must be cleared (= 0) for
Asynchronous and Synchronous Master modes
or set (= 1) for Synchronous Slave mode
Note:
The EUSART control will automatically
reconfigure the pin from input to output as
needed.
The operation of the Enhanced USART module is
controlled through three registers:
The Enhanced Universal Synchronous Receiver
Transmitter (EUSART) module implements additional
features, including Automatic Baud Rate Detection
(ABD) and calibration, automatic wake-up on Sync
Break reception and 12-bit Break character transmit.
These features make it ideally suited for use in Local
Interconnect Network bus (LIN bus) systems.
• Transmit Status and Control (TXSTA)
• Receive Status and Control (RCSTA)
• Baud Rate Control (BAUDCON)
These are detailed on the following pages in
Register 15-1, Register 15-2 and Register 15-3,
respectively.
The EUSART can be configured in the following
modes:
• Asynchronous (full-duplex) with:
- Auto-wake-up on character reception
- Auto-baud calibration
- 12-bit Break character transmission
• Synchronous – Master (half-duplex) with
selectable clock polarity
• Synchronous – Slave (half-duplex) with selectable
clock polarity
© 2008 Microchip Technology Inc.
DS39760D-page 153
PIC18F2450/4450
REGISTER 15-1: TXSTA: TRANSMIT STATUS AND CONTROL REGISTER
R/W-0
CSRC
R/W-0
TX9
R/W-0
TXEN(1)
R/W-0
SYNC
R/W-0
R/W-0
BRGH
R-1
R/W-0
TX9D
SENDB
TRMT
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7
CSRC: Clock Source Select bit
Asynchronous mode:
Don’t care.
Synchronous mode:
1= Master mode (clock generated internally from BRG)
0= Slave mode (clock from external source)
bit 6
bit 5
bit 4
bit 3
TX9: 9-Bit Transmit Enable bit
1= Selects 9-bit transmission
0= Selects 8-bit transmission
TXEN: Transmit Enable bit(1)
1= Transmit enabled
0= Transmit disabled
SYNC: EUSART Mode Select bit
1= Synchronous mode
0= Asynchronous mode
SENDB: Send Break Character bit
Asynchronous mode:
1= Send Sync Break on next transmission (cleared by hardware upon completion)
0= Sync Break transmission completed
Synchronous mode:
Don’t care.
bit 2
BRGH: High Baud Rate Select bit
Asynchronous mode:
1= High speed
0= Low speed
Synchronous mode:
Unused in this mode.
bit 1
bit 0
TRMT: Transmit Shift Register Status bit
1= TSR empty
0= TSR full
TX9D: 9th bit of Transmit Data
Can be address/data bit or a parity bit.
Note 1: SREN/CREN overrides TXEN in Sync mode with the exception that SREN has no effect in Synchronous
Slave mode.
DS39760D-page 154
© 2008 Microchip Technology Inc.
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REGISTER 15-2: RCSTA: RECEIVE STATUS AND CONTROL REGISTER
R/W-0
SPEN
R/W-0
RX9
R/W-0
SREN
R/W-0
CREN
R/W-0
R-0
R-0
R-x
ADDEN
FERR
OERR
RX9D
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7
bit 6
bit 5
SPEN: Serial Port Enable bit
1= Serial port enabled (configures RX/DT and TX/CK pins as serial port pins)
0= Serial port disabled (held in Reset)
RX9: 9-Bit Receive Enable bit
1= Selects 9-bit reception
0= Selects 8-bit reception
SREN: Single Receive Enable bit
Asynchronous mode:
Don’t care.
Synchronous mode – Master:
1= Enables single receive
0= Disables single receive
This bit is cleared after reception is complete.
Synchronous mode – Slave:
Don’t care.
bit 4
CREN: Continuous Receive Enable bit
Asynchronous mode:
1= Enables receiver
0= Disables receiver
Synchronous mode:
1= Enables continuous receive until enable bit CREN is cleared (CREN overrides SREN)
0= Disables continuous receive
bit 3
ADDEN: Address Detect Enable bit
Asynchronous mode 9-bit (RX9 = 1):
1= Enables address detection, enables interrupt and loads the receive buffer when RSR<8> is set
0= Disables address detection, all bytes are received and ninth bit can be used as parity bit
Asynchronous mode 8-bit (RX9 = 0):
Don’t care.
bit 2
bit 1
bit 0
FERR: Framing Error bit
1= Framing error (can be updated by reading RCREG register and receiving next valid byte)
0= No framing error
OERR: Overrun Error bit
1= Overrun error (can be cleared by clearing bit CREN)
0= No overrun error
RX9D: 9th bit of Received Data
This can be address/data bit or a parity bit and must be calculated by user firmware.
© 2008 Microchip Technology Inc.
DS39760D-page 155
PIC18F2450/4450
REGISTER 15-3: BAUDCON: BAUD RATE CONTROL REGISTER
R/W-0
R-1
U-0
—
R/W-0
SCKP
R/W-0
U-0
—
R/W-0
WUE
R/W-0
ABDOVF
RCIDL
BRG16
ABDEN
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7
bit 6
ABDOVF: Auto-Baud Acquisition Rollover Status bit
1= A BRG rollover has occurred during Auto-Baud Rate Detect mode (must be cleared in software)
0= No BRG rollover has occurred
RCIDL: Receive Operation Idle Status bit
1= Receive operation is Idle
0= Receive operation is active
bit 5
bit 4
Unimplemented: Read as ‘0’
SCKP: Synchronous Clock Polarity Select bit
Asynchronous mode:
Unused in this mode.
Synchronous mode:
1= Idle state for clock (CK) is a high level
0= Idle state for clock (CK) is a low level
bit 3
BRG16: 16-Bit Baud Rate Register Enable bit
1= 16-bit Baud Rate Generator – SPBRGH and SPBRG
0= 8-bit Baud Rate Generator – SPBRG only (Compatible mode), SPBRGH value ignored
bit 2
bit 1
Unimplemented: Read as ‘0’
WUE: Wake-up Enable bit
Asynchronous mode:
1= EUSART will continue to sample the RX pin – interrupt generated on falling edge; bit cleared in
hardware on following rising edge
0= RX pin not monitored or rising edge detected
Synchronous mode:
Unused in this mode.
bit 0
ABDEN: Auto-Baud Detect Enable bit
Asynchronous mode:
1= Enable baud rate measurement on the next character. Requires reception of a Sync field (55h);
cleared in hardware upon completion.
0= Baud rate measurement disabled or completed
Synchronous mode:
Unused in this mode.
DS39760D-page 156
© 2008 Microchip Technology Inc.
PIC18F2450/4450
the high baud rate (BRGH = 1) or the 16-bit BRG to
reduce the baud rate error, or achieve a slow baud rate
for a fast oscillator frequency.
15.1 Baud Rate Generator (BRG)
The BRG is a dedicated, 8-bit or 16-bit generator that
supports both the Asynchronous and Synchronous
modes of the EUSART. By default, the BRG operates
in 8-bit mode. Setting the BRG16 bit (BAUDCON<3>)
selects 16-bit mode.
Writing a new value to the SPBRGH:SPBRG registers
causes the BRG timer to be reset (or cleared). This
ensures the BRG does not wait for a timer overflow
before outputting the new baud rate.
The SPBRGH:SPBRG register pair controls the period
of a free-running timer. In Asynchronous mode, bits
BRGH (TXSTA<2>) and BRG16 (BAUDCON<3>) also
control the baud rate. In Synchronous mode, BRGH is
ignored. Table 15-1 shows the formula for computation
of the baud rate for different EUSART modes which
only apply in Master mode (internally generated clock).
15.1.1
OPERATION IN POWER-MANAGED
MODES
The device clock is used to generate the desired baud
rate. When one of the power-managed modes is
entered, the new clock source may be operating at a
different frequency. This may require an adjustment to
the value in the SPBRG register pair.
Given the desired baud rate and FOSC, the nearest
integer value for the SPBRGH:SPBRG registers can be
calculated using the formulas in Table 15-1. From this,
the error in baud rate can be determined. An example
calculation is shown in Example 15-1. Typical baud rates
and error values for the various Asynchronous modes
are shown in Table 15-2. It may be advantageous to use
15.1.2
SAMPLING
The data on the RX pin is sampled three times by a
majority detect circuit to determine if a high or a low
level is present at the RX pin.
TABLE 15-1: BAUD RATE FORMULAS
Configuration Bits
BRG/EUSART Mode
Baud Rate Formula
SYNC
BRG16
BRGH
0
0
0
0
1
1
0
0
1
1
0
1
0
1
0
1
x
x
8-Bit/Asynchronous
8-Bit/Asynchronous
16-Bit/Asynchronous
16-Bit/Asynchronous
8-Bit/Synchronous
16-Bit/Synchronous
FOSC/[64 (n + 1)]
FOSC/[16 (n + 1)]
FOSC/[4 (n + 1)]
Legend: x= Don’t care, n = Value of SPBRGH:SPBRG register pair
© 2008 Microchip Technology Inc.
DS39760D-page 157
PIC18F2450/4450
EXAMPLE 15-1:
CALCULATING BAUD RATE ERROR
For a device with FOSC of 16 MHz, desired baud rate of 9600, Asynchronous mode, 8-bit BRG:
Desired Baud Rate
=
FOSC/(64 ([SPBRGH:SPBRG] + 1)
Solving for SPBRGH:SPBRG:
X
=
=
=
=
=
=
=
((FOSC/Desired Baud Rate)/64) – 1
((16000000/9600)/64) – 1
[25.042] = 25
16000000/(64 (25 + 1))
9615
Calculated Baud Rate
Error
(Calculated Baud Rate – Desired Baud Rate)/Desired Baud Rate
(9615 – 9600)/9600 = 0.16%
TABLE 15-2: REGISTERS ASSOCIATED WITH BAUD RATE GENERATOR
Reset
Values
on Page:
Name
TXSTA
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
CSRC
SPEN
TX9
RX9
TXEN
SREN
—
SYNC
CREN
SCKP
SENDB
ADDEN
BRG16
BRGH
FERR
—
TRMT
OERR
WUE
TX9D
RX9D
51
51
51
50
50
RCSTA
BAUDCON
SPBRGH
SPBRG
ABDOVF RCIDL
ABDEN
EUSART Baud Rate Generator Register High Byte
EUSART Baud Rate Generator Register Low Byte
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the BRG.
DS39760D-page 158
© 2008 Microchip Technology Inc.
PIC18F2450/4450
TABLE 15-3: BAUD RATES FOR ASYNCHRONOUS MODES
SYNC = 0, BRGH = 0, BRG16 = 0
BAUD
RATE
(K)
FOSC = 40.000 MHz
FOSC = 20.000 MHz FOSC = 10.000 MHz
FOSC = 8.000 MHz
Actual
Rate
(K)
SPBRG Actual
value
SPBRG Actual
SPBRG Actual
value
(decimal)
SPBRG
value
(decimal)
%
%
Error
%
Error
%
Error
Rate
(K)
value
Rate
(K)
Rate
(K)
Error
(decimal)
(decimal)
0.3
1.2
—
—
—
—
—
—
—
255
129
31
15
4
—
—
—
129
64
15
7
—
1.201
2.403
9.615
—
—
-0.16
-0.16
-0.16
—
—
103
51
12
—
—
—
1.221
1.73
0.16
1.73
1.73
8.51
-9.58
1.202
2.404
9.766
19.531
52.083
78.125
0.16
0.16
1.73
1.73
-9.58
-32.18
2.4
2.441
9.615
19.531
56.818
125.000
1.73
0.16
1.73
-1.36
8.51
255
64
31
10
4
2.404
9.6
9.766
19.2
57.6
115.2
19.531
62.500
104.167
2
—
—
—
2
1
—
—
—
SYNC = 0, BRGH = 0, BRG16 = 0
BAUD
RATE
(K)
FOSC = 4.000 MHz
FOSC = 2.000 MHz
FOSC = 1.000 MHz
Actual
Rate
(K)
SPBRG Actual
value
SPBRG Actual
value
(decimal)
SPBRG
value
(decimal)
%
%
Error
%
Error
Rate
(K)
Rate
(K)
Error
(decimal)
0.3
1.2
0.300
1.202
0.16
0.16
207
51
25
6
0.300
1.201
2.403
—
-0.16
-0.16
-0.16
—
103
25
12
—
0.300
1.201
—
-0.16
-0.16
—
51
12
—
—
—
—
—
2.4
2.404
0.16
9.6
8.929
-6.99
8.51
—
—
19.2
57.6
115.2
20.833
62.500
62.500
2
—
—
—
—
—
8.51
0
—
—
—
—
—
-45.75
0
—
—
—
—
—
SYNC = 0, BRGH = 1, BRG16 = 0
BAUD
RATE
(K)
FOSC = 40.000 MHz
FOSC = 20.000 MHz
FOSC = 10.000 MHz
FOSC = 8.000 MHz
Actual
Rate
(K)
SPBRG Actual
value
(decimal)
SPBRG Actual
value
(decimal)
SPBRG Actual
value
(decimal)
SPBRG
value
%
Error
%
Error
%
Error
%
Error
Rate
(K)
Rate
(K)
Rate
(K)
(decimal)
0.3
1.2
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
2.4
—
—
—
—
—
—
2.441
9.615
19.531
56.818
125.000
1.73
0.16
1.73
-1.36
8.51
255
64
31
10
4
2.403
9.615
19.230
55.555
—
-0.16
-0.16
-0.16
3.55
—
207
51
25
8
9.6
9.766
19.231
58.140
113.636
1.73
0.16
0.94
-1.36
255
129
42
9.615
19.231
56.818
113.636
0.16
0.16
-1.36
-1.36
129
64
21
10
19.2
57.6
115.2
21
—
SYNC = 0, BRGH = 1, BRG16 = 0
BAUD
RATE
(K)
FOSC = 4.000 MHz
FOSC = 2.000 MHz
FOSC = 1.000 MHz
Actual
Rate
(K)
SPBRG Actual
value
SPBRG Actual
value
(decimal)
SPBRG
value
(decimal)
%
%
Error
%
Error
Rate
(K)
Rate
(K)
Error
(decimal)
0.3
1.2
—
—
—
207
103
25
12
3
—
1.201
2.403
9.615
—
—
-0.16
-0.16
-0.16
—
—
103
51
12
—
0.300
1.201
2.403
—
-0.16
-0.16
-0.16
—
207
51
25
—
1.202
0.16
0.16
0.16
0.16
8.51
8.51
2.4
2.404
9.6
9.615
19.2
57.6
115.2
19.231
62.500
125.000
—
—
—
—
—
—
—
—
—
1
—
—
—
—
—
—
© 2008 Microchip Technology Inc.
DS39760D-page 159
PIC18F2450/4450
TABLE 15-3: BAUD RATES FOR ASYNCHRONOUS MODES (CONTINUED)
SYNC = 0, BRGH = 0, BRG16 = 1
BAUD
RATE
(K)
FOSC = 40.000 MHz
FOSC = 20.000 MHz
FOSC = 10.000 MHz
FOSC = 8.000 MHz
Actual
Rate
(K)
SPBRG Actual
value
SPBRG Actual
value
(decimal)
SPBRG Actual
value
(decimal)
SPBRG
value
(decimal)
%
%
Error
%
Error
%
Error
Rate
(K)
Rate
(K)
Rate
(K)
Error
(decimal)
0.3
1.2
0.300
1.200
0.00
0.02
0.06
0.16
0.16
0.94
-1.36
8332
2082
1040
259
129
42
0.300
1.200
0.02
-0.03
-0.03
0.16
4165
1041
520
129
64
0.300
1.200
0.02
-0.03
0.16
0.16
1.73
-1.36
8.51
2082
520
259
64
0.300
1.201
2.403
9.615
19.230
55.555
—
-0.04
-0.16
-0.16
-0.16
-0.16
3.55
—
1665
415
207
51
2.4
2.402
2.399
2.404
9.6
9.615
9.615
9.615
19.2
57.6
115.2
19.231
58.140
113.636
19.231
56.818
113.636
0.16
19.531
56.818
125.000
31
25
-1.36
-1.36
21
10
8
21
10
4
—
SYNC = 0, BRGH = 0, BRG16 = 1
BAUD
RATE
(K)
FOSC = 4.000 MHz
FOSC = 2.000 MHz
FOSC = 1.000 MHz
Actual
Rate
(K)
SPBRG Actual
value
SPBRG Actual
value
(decimal)
SPBRG
value
(decimal)
%
%
Error
%
Error
Rate
(K)
Rate
(K)
Error
(decimal)
0.3
1.2
0.300
1.202
0.04
0.16
0.16
0.16
0.16
8.51
8.51
832
207
103
25
12
3
0.300
1.201
2.403
9.615
—
-0.16
-0.16
-0.16
-0.16
—
415
103
51
12
—
0.300
1.201
2.403
—
-0.16
-0.16
-0.16
—
207
51
25
—
2.4
2.404
9.6
9.615
19.2
57.6
115.2
19.231
62.500
125.000
—
—
—
—
—
—
—
—
—
1
—
—
—
—
—
—
SYNC = 0, BRGH = 1, BRG16 = 1 or SYNC = 1, BRG16 = 1
FOSC = 20.000 MHz FOSC = 10.000 MHz
BAUD
RATE
(K)
FOSC = 40.000 MHz
FOSC = 8.000 MHz
Actual
Rate
(K)
SPBRG Actual
SPBRG Actual
SPBRG Actual
value
SPBRG
value
(decimal)
%
Error
%
%
%
Error
value
(decimal)
Rate
(K)
value
Rate
(K)
Rate
(K)
Error
Error
(decimal)
(decimal)
0.3
1.2
0.300
1.200
0.00
0.00
0.02
0.06
-0.03
0.35
-0.22
33332
8332
4165
1040
520
0.300
1.200
0.00
0.02
0.02
-0.03
0.16
-0.22
0.94
16665
4165
2082
520
259
86
0.300
1.200
0.00
0.02
0.06
0.16
0.16
0.94
-1.36
8332
2082
1040
259
129
42
0.300
1.200
-0.01
-0.04
-0.04
-0.16
-0.16
0.79
6665
1665
832
207
103
34
2.4
2.400
2.400
2.402
2.400
9.6
9.606
9.596
9.615
9.615
19.2
57.6
115.2
19.193
57.803
114.943
19.231
57.471
116.279
19.231
58.140
113.636
19.230
57.142
117.647
172
86
42
21
-2.12
16
SYNC = 0, BRGH = 1, BRG16 = 1 or SYNC = 1, BRG16 = 1
FOSC = 4.000 MHz FOSC = 2.000 MHz FOSC = 1.000 MHz
BAUD
RATE
(K)
Actual
Rate
(K)
SPBRG Actual
SPBRG Actual
SPBRG
value
(decimal)
%
Error
%
Error
%
Error
value
Rate
(K)
value
Rate
(K)
(decimal)
(decimal)
0.3
1.2
0.300
1.200
0.01
0.04
0.16
0.16
0.16
2.12
-3.55
3332
832
415
103
51
0.300
1.201
2.403
9.615
19.230
55.555
—
-0.04
-0.16
-0.16
-0.16
-0.16
3.55
—
1665
415
207
51
0.300
1.201
2.403
9.615
19.230
—
-0.04
-0.16
-0.16
-0.16
-0.16
—
832
207
103
25
2.4
2.404
9.6
9.615
19.2
57.6
115.2
19.231
58.824
111.111
25
12
16
8
—
8
—
—
—
—
DS39760D-page 160
© 2008 Microchip Technology Inc.
PIC18F2450/4450
While the ABD sequence takes place, the EUSART
state machine is held in Idle. The RCIF interrupt is set
once the fifth rising edge on RX is detected. The value
in the RCREG needs to be read to clear the RCIF
interrupt. ThecontentsofRCREGshouldbediscarded.
15.1.3
AUTO-BAUD RATE DETECT
The Enhanced USART module supports the automatic
detection and calibration of baud rate. This feature is
active only in Asynchronous mode and while the WUE
bit is clear.
Note 1: If the WUE bit is set with the ABDEN bit,
Auto-Baud Rate Detection will occur on
the byte following the Break character.
The automatic baud rate measurement sequence
(Figure 15-1) begins whenever a Start bit is received and
the ABDEN bit is set. The calculation is self-averaging.
2: It is up to the user to determine that the
incoming character baud rate is within the
range of the selected BRG clock source.
Some combinations of oscillator fre-
quency and EUSART baud rates are not
possible due to bit error rates. Overall
system timing and communication baud
rates must be taken into consideration
when using the Auto-Baud Rate
Detection feature.
In the Auto-Baud Rate Detect (ABD) mode, the clock to
the BRG is reversed. Rather than the BRG clocking the
incoming RX signal, the RX signal is timing the BRG. In
ABD mode, the internal Baud Rate Generator is used
as a counter to time the bit period of the incoming serial
byte stream.
Once the ABDEN bit is set, the state machine will clear
the BRG and look for a Start bit. The Auto-Baud Rate
Detection must receive a byte with the value 55h
(ASCII “U”, which is also the LIN bus Sync character)
in order to calculate the proper bit rate. The measure-
ment is taken over both a low and a high bit time in
order to minimize any effects caused by asymmetry of
the incoming signal. After a Start bit, the SPBRG begins
counting up, using the preselected clock source on the
first rising edge of RX. After eight bits on the RX pin, or
the fifth rising edge, an accumulated value totalling the
proper BRG period is left in the SPBRGH:SPBRG
register pair. Once the 5th edge is seen (this should
correspond to the Stop bit), the ABDEN bit is
automatically cleared.
TABLE 15-4: BRG COUNTER
CLOCK RATES
BRG16 BRGH
BRG Counter Clock
0
0
1
0
1
FOSC/512
FOSC/128
FOSC/128
FOSC/32
0
1
1
Note:
During the ABD sequence, SPBRG and
SPBRGH are both used as a 16-bit counter,
independent of the BRG16 setting.
If a rollover of the BRG occurs (an overflow from FFFFh
to 0000h), the event is trapped by the ABDOVF status
bit (BAUDCON<7>). It is set in hardware by BRG roll-
overs and can be set or cleared by the user in software.
ABD mode remains active after rollover events and the
ABDEN bit remains set (Figure 15-2).
15.1.3.1
ABD and EUSART Transmission
Since the BRG clock is reversed during ABD
acquisition, the EUSART transmitter cannot be used
during ABD. This means that whenever the ABDEN bit
is set, TXREG cannot be written to. Users should also
ensure that ABDEN does not become set during a
transmit sequence. Failing to do this may result in
unpredictable EUSART operation.
While calibrating the baud rate period, the BRG
registers are clocked at 1/8th the preconfigured clock
rate. Note that the BRG clock will be configured by the
BRG16 and BRGH bits. Independent of the BRG16 bit
setting, both the SPBRG and SPBRGH will be used as
a 16-bit counter. This allows the user to verify that no
carry occurred for 8-bit modes by checking for 00h in
the SPBRGH register. Refer to Table 15-4 for counter
clock rates to the BRG.
© 2008 Microchip Technology Inc.
DS39760D-page 161
PIC18F2450/4450
FIGURE 15-1:
AUTOMATIC BAUD RATE CALCULATION
BRG Value
XXXXh
0000h
001Ch
Edge #5
Stop bit
Edge #2
bit 3
Edge #3
bit 5
bit 4
Edge #4
bit 7
Edge #1
RX pin
bit 1
Start
bit 2
bit 6
bit 0
BRG Clock
Auto-Cleared
Set by User
ABDEN bit
RCIF bit
(Interrupt)
Read
RCREG
XXXXh
XXXXh
1Ch
00h
SPBRG
SPBRGH
Note: The ABD sequence requires the EUSART module to be configured in Asynchronous mode and WUE = 0.
FIGURE 15-2:
BRG OVERFLOW SEQUENCE
BRG Clock
ABDEN bit
RX pin
Start
bit 0
ABDOVF bit
BRG Value
FFFFh
XXXXh
0000h
0000h
DS39760D-page 162
© 2008 Microchip Technology Inc.
PIC18F2450/4450
Once the TXREG register transfers the data to the TSR
register (occurs in one TCY), the TXREG register is
empty and the TXIF flag bit (PIR1<4>) is set. This inter-
rupt can be enabled or disabled by setting or clearing
the interrupt enable bit, TXIE (PIE1<4>). TXIF will be
set regardless of the state of TXIE; it cannot be cleared
in software. TXIF is also not cleared immediately upon
loading TXREG but becomes valid in the second
instruction cycle following the load instruction. Polling
TXIF immediately following a load of TXREG will return
invalid results.
15.2 EUSART Asynchronous Mode
The Asynchronous mode of operation is selected by
clearing the SYNC bit (TXSTA<4>). In this mode, the
EUSART uses the standard Non-Return-to-Zero (NRZ)
format (one Start bit, eight or nine data bits and one
Stop bit). The most common data format is eight bits.
An on-chip dedicated 8-bit/16-bit Baud Rate Generator
can be used to derive standard baud rate frequencies
from the oscillator.
The EUSART transmits and receives the LSb first. The
EUSART’s transmitter and receiver are functionally
independent but use the same data format and baud
rate. The Baud Rate Generator produces a clock,
either x16 or x64 of the bit shift rate depending on the
While TXIF indicates the status of the TXREG register,
another bit, TRMT (TXSTA<1>), shows the status of
the TSR register. TRMT is a read-only bit which is set
when the TSR register is empty. No interrupt logic is
tied to this bit so the user has to poll this bit in order to
determine if the TSR register is empty.
BRGH
and
BRG16
bits
(TXSTA<2>
and
BAUDCON<3>). Parity is not supported by the hard-
ware but can be implemented in software and stored as
the ninth data bit.
Note 1: The TSR register is not mapped in data
memory so it is not available to the user.
When operating in Asynchronous mode, the EUSART
module consists of the following important elements:
2: Flag bit, TXIF, is set when enable bit,
TXEN, is set.
• Baud Rate Generator
• Sampling Circuit
To set up an Asynchronous Transmission:
• Asynchronous Transmitter
• Asynchronous Receiver
• Auto-Wake-up on Sync Break Character
• 12-Bit Break Character Transmit
• Auto-Baud Rate Detection
1. Initialize the SPBRGH:SPBRG registers for the
appropriate baud rate. Set or clear the BRGH
and BRG16 bits, as required, to achieve the
desired baud rate.
2. Enable the asynchronous serial port by clearing
bit, SYNC, and setting bit, SPEN.
15.2.1
EUSART ASYNCHRONOUS
TRANSMITTER
3. If interrupts are desired, set enable bit, TXIE.
4. If 9-bit transmission is desired, set transmit bit,
TX9. Can be used as address/data bit.
The EUSART transmitter block diagram is shown in
Figure 15-3. The heart of the transmitter is the Transmit
(Serial) Shift Register (TSR). The Shift register obtains
its data from the Read/Write Transmit Buffer register,
TXREG. The TXREG register is loaded with data in
software. The TSR register is not loaded until the Stop
bit has been transmitted from the previous load. As
soon as the Stop bit is transmitted, the TSR is loaded
with new data from the TXREG register (if available).
5. Enable the transmission by setting bit, TXEN,
which will also set bit, TXIF.
6. If 9-bit transmission is selected, the ninth bit
should be loaded in bit, TX9D.
7. Load data to the TXREG register (starts
transmission).
8. If using interrupts, ensure that the GIE and PEIE
bits in the INTCON register (INTCON<7:6>) are
set.
FIGURE 15-3:
EUSART TRANSMIT BLOCK DIAGRAM
Data Bus
TXREG Register
TXIF
TXIE
8
MSb
(8)
LSb
Pin Buffer
and Control
TX pin
0
•
•
•
TSR Register
Interrupt
Baud Rate CLK
SPBRG
TXEN
TRMT
SPEN
BRG16
SPBRGH
TX9
TX9D
Baud Rate Generator
© 2008 Microchip Technology Inc.
DS39760D-page 163
PIC18F2450/4450
FIGURE 15-4:
ASYNCHRONOUS TRANSMISSION
Write to TXREG
Word 1
BRG Output
(Shift Clock)
TX
(pin)
Start bit
bit 0
bit 1
Word 1
bit 7/8
Stop bit
TXIF bit
(Transmit Buffer
Reg. Empty Flag)
1 TCY
Word 1
Transmit Shift Reg
TRMT bit
(Transmit Shift
Reg. Empty Flag)
FIGURE 15-5:
ASYNCHRONOUS TRANSMISSION (BACK-TO-BACK)
Write to TXREG
Word 2
Start bit
Word 1
BRG Output
(Shift Clock)
TX
(pin)
Start bit
Word 2
bit 0
bit 1
bit 7/8
bit 0
Stop bit
1 TCY
Word 1
TXIF bit
(Interrupt Reg. Flag)
1 TCY
Word 1
Transmit Shift Reg.
Word 2
Transmit Shift Reg.
TRMT bit
(Transmit Shift
Reg. Empty Flag)
Note:
This timing diagram shows two consecutive transmissions.
TABLE 15-5: REGISTERS ASSOCIATED WITH ASYNCHRONOUS TRANSMISSION
Reset
Valueson
Page:
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
INTCON
PIR1
GIE/GIEH PEIE/GIEL TMR0IE
INT0IE
TXIF
RBIE
—
TMR0IF
CCP1IF
INT0IF
RBIF
49
51
51
51
51
51
51
51
50
50
—
—
ADIF
ADIE
ADIP
RX9
RCIF
RCIE
RCIP
SREN
TMR2IF
TMR1IF
PIE1
TXIE
—
CCP1IE TMR2IE TMR1IE
CCP1IP TMR2IP TMR1IP
IPR1
—
TXIP
—
RCSTA
TXREG
TXSTA
SPEN
CREN
ADDEN
FERR
OERR
RX9D
EUSART Transmit Register
CSRC
TX9
TXEN
—
SYNC
SCKP
SENDB
BRG16
BRGH
—
TRMT
WUE
TX9D
BAUDCON ABDOVF
RCIDL
ABDEN
SPBRGH EUSART Baud Rate Generator Register High Byte
SPBRG EUSART Baud Rate Generator Register Low Byte
Legend: — = unimplemented locations read as ‘0’. Shaded cells are not used for asynchronous transmission.
DS39760D-page 164
© 2008 Microchip Technology Inc.
PIC18F2450/4450
15.2.2
EUSART ASYNCHRONOUS
RECEIVER
15.2.3
SETTING UP 9-BIT MODE WITH
ADDRESS DETECT
The receiver block diagram is shown in Figure 15-6.
The data is received on the RX pin and drives the data
recovery block. The data recovery block is actually a
high-speed shifter operating at x16 times the baud rate,
whereas the main receive serial shifter operates at the
bit rate or at FOSC. This mode would typically be used
in RS-232 systems.
This mode would typically be used in RS-485 systems.
To set up an Asynchronous Reception with Address
Detect Enable:
1. Initialize the SPBRGH:SPBRG registers for the
appropriate baud rate. Set or clear the BRGH
and BRG16 bits, as required, to achieve the
desired baud rate.
To set up an Asynchronous Reception:
2. Enable the asynchronous serial port by clearing
the SYNC bit and setting the SPEN bit.
1. Initialize the SPBRGH:SPBRG registers for the
appropriate baud rate. Set or clear the BRGH
and BRG16 bits, as required, to achieve the
desired baud rate.
3. If interrupts are required, set the RCEN bit and
select the desired priority level with the RCIP bit.
4. Set the RX9 bit to enable 9-bit reception.
5. Set the ADDEN bit to enable address detect.
6. Enable reception by setting the CREN bit.
2. Enable the asynchronous serial port by clearing
bit, SYNC, and setting bit, SPEN.
3. If interrupts are desired, set enable bit, RCIE.
4. If 9-bit reception is desired, set bit, RX9.
5. Enable the reception by setting bit, CREN.
7. The RCIF bit will be set when reception is
complete. The interrupt will be Acknowledged if
the RCIE and GIE bits are set.
6. Flag bit, RCIF, will be set when reception is
complete and an interrupt will be generated if
enable bit, RCIE, was set.
8. Read the RCSTA register to determine if any
error occurred during reception, as well as read
bit 9 of data (if applicable).
7. Read the RCSTA register to get the ninth bit (if
enabled) and determine if any error occurred
during reception.
9. Read RCREG to determine if the device is being
addressed.
10. If any error occurred, clear the CREN bit.
8. Read the 8-bit received data by reading the
RCREG register.
11. If the device has been addressed, clear the
ADDEN bit to allow all received data into the
receive buffer and interrupt the CPU.
9. If any error occurred, clear the error by clearing
enable bit, CREN.
10. If using interrupts, ensure that the GIE and PEIE
bits in the INTCON register (INTCON<7:6>) are
set.
FIGURE 15-6:
EUSART RECEIVE BLOCK DIAGRAM
CREN
OERR
FERR
x64 Baud Rate CLK
SPBRGH SPBRG
÷ 64
or
RSR Register
• • •
MSb
Stop
LSb
Start
BRG16
÷ 16
(8)
7
1
0
or
÷ 4
Baud Rate Generator
RX9
Pin Buffer
and Control
Data
Recovery
RX
RX9D
RCREG Register
FIFO
SPEN
8
Interrupt
RCIF
RCIE
Data Bus
© 2008 Microchip Technology Inc.
DS39760D-page 165
PIC18F2450/4450
FIGURE 15-7:
ASYNCHRONOUS RECEPTION
Start
bit
Start
bit
Start
bit
RX (pin)
bit 0
bit 7/8
bit 0 bit 1
bit 7/8
Stop
bit
Stop
bit
Stop
bit
bit 7/8
Rcv Shift Reg
Rcv Buffer Reg
Word 2
RCREG
Word 1
RCREG
Read Rcv
Buffer Reg
RCREG
RCIF
(Interrupt Flag)
OERR bit
CREN
Note:
This timing diagram shows three words appearing on the RX input. The RCREG (Receive Buffer) is read after the third word
causing the OERR (Overrun Error) bit to be set.
TABLE 15-6: REGISTERS ASSOCIATED WITH ASYNCHRONOUS RECEPTION
Reset
Values
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
on Page:
INTCON
PIR1
GIE/GIEH PEIE/GIEL TMR0IE
INT0IE
TXIF
RBIE
—
TMR0IF
CCP1IF
INT0IF
RBIF
49
51
51
51
51
50
51
51
50
50
—
—
ADIF
ADIE
ADIP
RX9
RCIF
RCIE
RCIP
SREN
TMR2IF TMR1IF
PIE1
TXIE
—
CCP1IE TMR2IE TMR1IE
CCP1IP TMR2IP TMR1IP
IPR1
—
TXIP
—
RCSTA
RCREG
TXSTA
BAUDCON
SPBRGH
SPBRG
SPEN
CREN
ADDEN
FERR
OERR
RX9D
EUSART Receive Register
CSRC
TX9
TXEN
—
SYNC
SCKP
SENDB
BRG16
BRGH
—
TRMT
WUE
TX9D
ABDOVF
RCIDL
ABDEN
EUSART Baud Rate Generator Register High Byte
EUSART Baud Rate Generator Register Low Byte
Legend: — = unimplemented locations read as ‘0’. Shaded cells are not used for asynchronous reception.
DS39760D-page 166
© 2008 Microchip Technology Inc.
PIC18F2450/4450
(EOC) and cause data or framing errors. To work prop-
erly, therefore, the initial character in the transmission
must be all ‘0’s. This can be 00h (8 bits) for standard
RS-232 devices or 000h (12 bits) for LIN bus.
15.2.4
AUTO-WAKE-UP ON SYNC BREAK
CHARACTER
During Sleep mode, all clocks to the EUSART are
suspended. Therefore, the Baud Rate Generator is
inactive and proper byte reception cannot be
performed. The auto-wake-up feature allows the
controller to wake-up due to activity on the RX/DT line
while the EUSART is operating in Asynchronous mode.
Oscillator start-up time must also be considered,
especially in applications using oscillators with longer
start-up intervals (i.e., XT or HS mode). The Sync
Break (or Wake-up Signal) character must be of
sufficient length and be followed by a sufficient interval
to allow enough time for the selected oscillator to start
and provide proper initialization of the EUSART.
The auto-wake-up feature is enabled by setting the
WUE bit (BAUDCON<1>). Once set, the typical receive
sequence on RX/DT is disabled and the EUSART
remains in an Idle state, monitoring for a wake-up event
independent of the CPU mode. A wake-up event
consists of a high-to-low transition on the RX/DT line.
(This coincides with the start of a Sync Break or a
Wake-up Signal character for the LIN protocol.)
15.2.4.2
Special Considerations Using
the WUE Bit
The timing of WUE and RCIF events may cause some
confusion when it comes to determining the validity of
received data. As noted, setting the WUE bit places the
EUSART in an Idle mode. The wake-up event causes
a receive interrupt by setting the RCIF bit. The WUE bit
is cleared after this when a rising edge is seen on RX/
DT. The interrupt condition is then cleared by reading
the RCREG register. Ordinarily, the data in RCREG will
be dummy data and should be discarded.
Following a wake-up event, the module generates an
RCIF interrupt. The interrupt is generated synchro-
nously to the Q clocks in normal operating modes
(Figure 15-8) and asynchronously if the device is in
Sleep mode (Figure 15-9). The interrupt condition is
cleared by reading the RCREG register.
The WUE bit is automatically cleared once a low-to-high
transition is observed on the RX line following the wake-
up event. At this point, the EUSART module is in Idle
mode and returns to normal operation. This signals to
the user that the Sync Break event is over.
The fact that the WUE bit has been cleared (or is still
set) and the RCIF flag is set should not be used as an
indicator of the integrity of the data in RCREG. Users
should consider implementing a parallel method in
firmware to verify received data integrity.
To assure that no actual data is lost, check the RCIDL
bit to verify that a receive operation is not in process. If
a receive operation is not occurring, the WUE bit may
then be set just prior to entering the Sleep mode.
15.2.4.1
Special Considerations Using
Auto-Wake-up
Since auto-wake-up functions by sensing rising edge
transitions on RX/DT, information with any state changes
before the Stop bit may signal a false End-of-Character
FIGURE 15-8:
AUTO-WAKE-UP BIT (WUE) TIMINGS DURING NORMAL OPERATION
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
OSC1
WUE bit(1)
RX/DT Line
RCIF
Bit set by user
Auto-Cleared
Cleared due to user read of RCREG
Note 1: The EUSART remains in Idle while the WUE bit is set.
FIGURE 15-9:
AUTO-WAKE-UP BIT (WUE) TIMINGS DURING SLEEP
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
Q1
Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
OSC1
WUE bit(2)
RX/DT Line
RCIF
Bit set by user
Auto-Cleared
Note 1
Cleared due to user read of RCREG
Sleep Ends
Sleep Command Executed
Note 1: If the wake-up event requires long oscillator warm-up time, the auto-clear of the WUE bit can occur while the stposc signal is still active.
This sequence should not depend on the presence of Q clocks.
2: The EUSART remains in Idle while the WUE bit is set.
© 2008 Microchip Technology Inc.
DS39760D-page 167
PIC18F2450/4450
3. Load the TXREG with a dummy character to
initiate transmission (the value is ignored).
15.2.5
BREAK CHARACTER SEQUENCE
The EUSART module has the capability of sending the
special Break character sequences that are required by
the LIN bus standard. The Break character transmit
consists of a Start bit, followed by twelve ‘0’ bits and a
Stop bit. The Frame Break character is sent whenever
the SENDB and TXEN bits (TXSTA<3> and
TXSTA<5>) are set while the Transmit Shift Register is
loaded with data. Note that the value of data written to
TXREG will be ignored and all ‘0’s will be transmitted.
4. Write ‘55h’ to TXREG to load the Sync character
into the transmit FIFO buffer.
5. After the Break has been sent, the SENDB bit is
reset by hardware. The Sync character now
transmits in the preconfigured mode.
When the TXREG becomes empty, as indicated by the
TXIF, the next data byte can be written to TXREG.
15.2.6
RECEIVING A BREAK CHARACTER
The SENDB bit is automatically reset by hardware after
the corresponding Stop bit is sent. This allows the user
to preload the transmit FIFO with the next transmit byte
following the Break character (typically, the Sync
character in the LIN specification).
The Enhanced USART module can receive a Break
character in two ways.
The first method forces configuration of the baud rate
at a frequency of 9/13 the typical speed. This allows for
the Stop bit transition to be at the correct sampling
location (13 bits for Break versus Start bit and eight
data bits for typical data).
Note that the data value written to the TXREG for the
Break character is ignored. The write simply serves the
purpose of initiating the proper sequence.
The TRMT bit indicates when the transmit operation is
active or Idle, just as it does during normal transmission.
See Figure 15-10 for the timing of the Break character
sequence.
The second method uses the auto-wake-up feature
described in Section 15.2.4 “Auto-Wake-up on Sync
Break Character”. By enabling this feature, the
EUSART will sample the next two transitions on RX/DT,
cause an RCIF interrupt and receive the next data byte
followed by another interrupt.
15.2.5.1
Break and Sync Transmit Sequence
The following sequence will send a message frame
header made up of a Break, followed by an Auto-Baud
Sync byte. This sequence is typical of a LIN bus master.
Note that following a Break character, the user will
typically want to enable the Auto-Baud Rate Detect
feature. For both methods, the user can set the ABD bit
once the TXIF interrupt is observed.
1. Configure the EUSART for the desired mode.
2. Set the TXEN and SENDB bits to set up the
Break character.
FIGURE 15-10:
SEND BREAK CHARACTER SEQUENCE
Write to TXREG
Dummy Write
BRG Output
(Shift Clock)
TX (pin)
Start bit
bit 0
bit 1
Break
bit 11
Stop bit
TXIF bit
(Transmit Buffer
Reg. Empty Flag)
TRMT bit
(Transmit Shift
Reg. Empty Flag)
SENDB sampled here
Auto-Cleared
SENDB
(Transmit Shift
Reg. Empty Flag)
DS39760D-page 168
© 2008 Microchip Technology Inc.
PIC18F2450/4450
Once the TXREG register transfers the data to the TSR
register (occurs in one TCYCLE), the TXREG register is
empty and the TXIF flag bit (PIR1<4>) is set. The
interrupt can be enabled or disabled by setting or
clearing the interrupt enable bit, TXIE (PIE1<4>). TXIF
is set regardless of the state of enable bit, TXIE; it
cannot be cleared in software. It will reset only when
new data is loaded into the TXREG register.
15.3 EUSART Synchronous
Master Mode
The Synchronous Master mode is entered by setting
the CSRC bit (TXSTA<7>). In this mode, the data is
transmitted in a half-duplex manner (i.e., transmission
and reception do not occur at the same time). When
transmitting data, the reception is inhibited and vice
versa. Synchronous mode is entered by setting bit,
SYNC (TXSTA<4>). In addition, enable bit, SPEN
(RCSTA<7>), is set in order to configure the TX and RX
pins to CK (clock) and DT (data) lines, respectively.
While flag bit, TXIF, indicates the status of the TXREG
register, another bit, TRMT (TXSTA<1>), shows the
status of the TSR register. TRMT is a read-only bit which
is set when the TSR is empty. No interrupt logic is tied to
this bit so the user must poll this bit in order to determine
if the TSR register is empty. The TSR is not mapped in
data memory so it is not available to the user.
The Master mode indicates that the processor
transmits the master clock on the CK line. Clock
polarity is selected with the SCKP bit (BAUDCON<4>).
Setting SCKP sets the Idle state on CK as high, while
clearing the bit sets the Idle state as low. This option is
provided to support Microwire devices with this module.
To set up a Synchronous Master Transmission:
1. Initialize the SPBRGH:SPBRG registers for the
appropriate baud rate. Set or clear the BRG16
bit, as required, to achieve the desired baud
rate.
15.3.1
EUSART SYNCHRONOUS MASTER
TRANSMISSION
2. Enable the synchronous master serial port by
setting bits, SYNC, SPEN and CSRC.
The EUSART transmitter block diagram is shown in
Figure 15-3. The heart of the transmitter is the Transmit
(Serial) Shift Register (TSR). The Shift register obtains
its data from the Read/Write Transmit Buffer register,
TXREG. The TXREG register is loaded with data in
software. The TSR register is not loaded until the last
bit has been transmitted from the previous load. As
soon as the last bit is transmitted, the TSR is loaded
with new data from the TXREG (if available).
3. If interrupts are desired, set enable bit, TXIE.
4. If 9-bit transmission is desired, set bit, TX9.
5. Enable the transmission by setting bit, TXEN.
6. If 9-bit transmission is selected, the ninth bit
should be loaded in bit, TX9D.
7. Start transmission by loading data to the TXREG
register.
8. If using interrupts, ensure that the GIE and PEIE
bits in the INTCON register (INTCON<7:6>) are
set.
FIGURE 15-11:
SYNCHRONOUS TRANSMISSION
Q1 Q2 Q3Q4 Q1 Q2 Q3 Q4 Q1Q2 Q3 Q4 Q1Q2 Q3 Q4 Q1 Q2 Q3 Q4
Q3 Q4 Q1 Q2 Q3Q4 Q1Q2 Q3Q4 Q1 Q2Q3Q4 Q1 Q2Q3 Q4Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
RC7/RX/DT pin
bit 0
bit 1
bit 2
bit 7
bit 0
bit 1
bit 7
Word 2
Word 1
RC6/TX/CK pin
(SCKP = 0)
RC6/TX/CK pin
(SCKP = 1)
Write to
TXREG Reg
Write Word 1
Write Word 2
TXIF bit
(Interrupt Flag)
TRMT bit
‘1’
‘1’
TXEN bit
Note: Sync Master mode (SPBRG = 0), continuous transmission of two 8-bit words.
© 2008 Microchip Technology Inc.
DS39760D-page 169
PIC18F2450/4450
FIGURE 15-12:
SYNCHRONOUS TRANSMISSION (THROUGH TXEN)
RC7/RX/DT pin
bit 0
bit 2
bit 1
bit 6
bit 7
RC6/TX/CK pin
Write to
TXREG reg
TXIF bit
TRMT bit
TXEN bit
TABLE 15-7: REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER TRANSMISSION
Reset
Values
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
on Page:
INTCON
PIR1
GIE/GIEH PEIE/GIEL TMR0IE
INT0IE
TXIF
RBIE
—
TMR0IF
INT0IF
RBIF
49
51
51
51
51
51
51
51
50
50
—
—
ADIF
ADIE
ADIP
RX9
RCIF
RCIE
RCIP
SREN
CCP1IF TMR2IF TMR1IF
CCP1IE TMR2IE TMR1IE
CCP1IP TMR2IP TMR1IP
PIE1
TXIE
—
IPR1
—
TXIP
—
RCSTA
TXREG
TXSTA
SPEN
CREN
ADDEN
FERR
OERR
RX9D
EUSART Transmit Register
CSRC
TX9
TXEN
—
SYNC
SCKP
SENDB
BRG16
BRGH
—
TRMT
WUE
TX9D
BAUDCON ABDOVF
RCIDL
ABDEN
SPBRGH
SPBRG
EUSART Baud Rate Generator Register High Byte
EUSART Baud Rate Generator Register Low Byte
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used for synchronous master transmission.
DS39760D-page 170
© 2008 Microchip Technology Inc.
PIC18F2450/4450
3. Ensure bits, CREN and SREN, are clear.
4. If interrupts are desired, set enable bit, RCIE.
5. If 9-bit reception is desired, set bit, RX9.
15.3.2
EUSART SYNCHRONOUS MASTER
RECEPTION
Once Synchronous mode is selected, reception is
enabled by setting either the Single Receive Enable bit,
SREN (RCSTA<5>), or the Continuous Receive
Enable bit, CREN (RCSTA<4>). Data is sampled on the
RX pin on the falling edge of the clock.
6. If a single reception is required, set bit, SREN.
For continuous reception, set bit, CREN.
7. Interrupt flag bit, RCIF, will be set when reception
is complete and an interrupt will be generated if
the enable bit, RCIE, was set.
If enable bit, SREN, is set, only a single word is
received. If enable bit, CREN, is set, the reception is
continuous until CREN is cleared. If both bits are set,
then CREN takes precedence.
8. Read the RCSTA register to get the ninth bit (if
enabled) and determine if any error occurred
during reception.
9. Read the 8-bit received data by reading the
RCREG register.
To set up a Synchronous Master Reception:
1. Initialize the SPBRGH:SPBRG registers for the
appropriate baud rate. Set or clear the BRG16
bit, as required, to achieve the desired baud rate.
10. If any error occurred, clear the error by clearing
bit, CREN.
11. If using interrupts, ensure that the GIE and PEIE
bits in the INTCON register (INTCON<7:6>) are
set.
2. Enable the synchronous master serial port by
setting bits, SYNC, SPEN and CSRC.
FIGURE 15-13:
SYNCHRONOUS RECEPTION (MASTER MODE, SREN)
Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4Q1 Q2 Q3 Q4 Q1Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
RC7/RX/DT
pin
bit 0
bit 1
bit 2
bit 3
bit 4
bit 5
bit 6
bit 7
RC6/TX/CK pin
(SCKP = 0)
RC6/TX/CK pin
(SCKP = 1)
Write to
SREN bit
SREN bit
CREN bit
‘0’
‘0’
RCIF bit
(Interrupt)
Read
RXREG
Note: Timing diagram demonstrates Sync Master mode with SREN bit = 1and BRGH bit = 0.
TABLE 15-8: REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER RECEPTION
Reset
Values
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
on Page:
INTCON
PIR1
GIE/GIEH PEIE/GIEL
TMR0IE
RCIF
INT0IE
TXIF
RBIE
—
TMR0IF INT0IF
RBIF
49
51
51
51
51
50
51
51
51
50
—
—
ADIF
ADIE
ADIP
RX9
CCP1IF TMR2IF TMR1IF
CCP1IE TMR2IE TMR1IE
CCP1IP TMR2IP TMR1IP
PIE1
RCIE
TXIE
—
IPR1
—
RCIP
TXIP
—
RCSTA
RCREG
TXSTA
SPEN
SREN
CREN
ADDEN
FERR
OERR
RX9D
EUSART Receive Register
CSRC
TX9
TXEN
—
SYNC
SCKP
SENDB
BRG16
BRGH
—
TRMT
WUE
TX9D
BAUDCON ABDOVF
RCIDL
ABDEN
SPBRGH EUSART Baud Rate Generator Register High Byte
SPBRG EUSART Baud Rate Generator Register Low Byte
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used for synchronous master reception.
© 2008 Microchip Technology Inc.
DS39760D-page 171
PIC18F2450/4450
To set up a Synchronous Slave Transmission:
15.4 EUSART Synchronous
Slave Mode
1. Enable the synchronous slave serial port by
setting bits, SYNC and SPEN, and clearing bit,
CSRC.
Synchronous Slave mode is entered by clearing bit,
CSRC (TXSTA<7>). This mode differs from the
Synchronous Master mode in that the shift clock is
supplied externally at the CK pin (instead of being
supplied internally in Master mode). This allows the
device to transfer or receive data while in any low-power
mode.
2. Clear bits, CREN and SREN.
3. If interrupts are desired, set enable bit, TXIE.
4. If 9-bit transmission is desired, set bit, TX9.
5. Enable the transmission by setting enable bit,
TXEN.
6. If 9-bit transmission is selected, the ninth bit
should be loaded in bit, TX9D.
15.4.1
EUSART SYNCHRONOUS
SLAVE TRANSMIT
7. Start transmission by loading data to the TXREG
register.
The operation of the Synchronous Master and Slave
modes is identical, except in the case of Sleep mode.
8. If using interrupts, ensure that the GIE and PEIE
bits in the INTCON register (INTCON<7:6>) are
set.
If two words are written to the TXREG register and then
the SLEEPinstruction is executed, the following will occur:
a) The first word will immediately transfer to the
TSR register and transmit.
b) The second word will remain in the TXREG
register.
c) Flag bit, TXIF, will not be set.
d) When the first word has been shifted out of TSR,
the TXREG register will transfer the second word
to the TSR and flag bit, TXIF, will now be set.
e) If enable bit, TXIE, is set, the interrupt will wake
the chip from Sleep. If the global interrupt is
enabled, the program will branch to the interrupt
vector.
TABLE 15-9: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE TRANSMISSION
Reset
Values
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
on Page:
INTCON
PIR1
GIE/GIEH PEIE/GIEL TMR0IE
INT0IE
TXIF
RBIE
—
TMR0IF
CCP1IF
CCP1IE
CCP1IP
FERR
INT0IF
RBIF
49
51
51
51
51
51
51
51
50
50
—
—
ADIF
ADIE
ADIP
RX9
RCIF
RCIE
RCIP
SREN
TMR2IF
TMR1IF
PIE1
TXIE
—
TMR2IE TMR1IE
TMR2IP TMR1IP
IPR1
—
TXIP
—
RCSTA
TXREG
TXSTA
SPEN
CREN
ADDEN
OERR
RX9D
EUSART Transmit Register
CSRC
TX9
TXEN
—
SYNC
SCKP
SENDB
BRG16
BRGH
—
TRMT
WUE
TX9D
BAUDCON ABDOVF
RCIDL
ABDEN
SPBRGH
SPBRG
EUSART Baud Rate Generator Register High Byte
EUSART Baud Rate Generator Register Low Byte
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used for synchronous slave transmission.
DS39760D-page 172
© 2008 Microchip Technology Inc.
PIC18F2450/4450
To set up a Synchronous Slave Reception:
15.4.2
EUSART SYNCHRONOUS SLAVE
RECEPTION
1. Enable the synchronous master serial port by
setting bits, SYNC and SPEN, and clearing bit,
CSRC.
The operation of the Synchronous Master and Slave
modes is identical, except in the case of Sleep or any
Idle mode and bit, SREN, which is a “don’t care” in
Slave mode.
2. If interrupts are desired, set enable bit, RCIE.
3. If 9-bit reception is desired, set bit, RX9.
4. To enable reception, set enable bit, CREN.
If receive is enabled by setting the CREN bit prior to
entering Sleep or any Idle mode, then a word may be
received while in this low-power mode. Once the word
is received, the RSR register will transfer the data to the
RCREG register. If the RCIE enable bit is set, the
interrupt generated will wake the chip from the low-
power mode. If the global interrupt is enabled, the
program will branch to the interrupt vector.
5. Flag bit RCIF will be set when reception is
complete. An interrupt will be generated if
enable bit, RCIE, was set.
6. Read the RCSTA register to get the ninth bit (if
enabled) and determine if any error occurred
during reception.
7. Read the 8-bit received data by reading the
RCREG register.
8. If any error occurred, clear the error by clearing
bit, CREN.
9. If using interrupts, ensure that the GIE and PEIE
bits in the INTCON register (INTCON<7:6>) are
set.
TABLE 15-10: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE RECEPTION
Reset
Values
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
on Page:
INTCON
PIR1
GIE/GIEH PEIE/GIEL TMR0IE
INT0IE
TXIF
RBIE
—
TMR0IF
CCP1IF
INT0IF
RBIF
49
51
51
51
51
50
51
51
50
50
—
—
ADIF
ADIE
ADIP
RX9
RCIF
RCIE
RCIP
SREN
TMR2IF TMR1IF
PIE1
TXIE
—
CCP1IE TMR2IE TMR1IE
CCP1IP TMR2IP TMR1IP
IPR1
—
TXIP
—
RCSTA
RCREG
TXSTA
SPEN
CREN
ADDEN
FERR
OERR
RX9D
EUSART Receive Register
CSRC
TX9
TXEN
—
SYNC
SCKP
SENDB
BRG16
BRGH
—
TRMT
WUE
TX9D
BAUDCON ABDOVF
RCIDL
ABDEN
SPBRGH
SPBRG
EUSART Baud Rate Generator Register High Byte
EUSART Baud Rate Generator Register Low Byte
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used for synchronous slave reception.
© 2008 Microchip Technology Inc.
DS39760D-page 173
PIC18F2450/4450
NOTES:
DS39760D-page 174
© 2008 Microchip Technology Inc.
PIC18F2450/4450
The ADCON0 register, shown in Register 16-1,
controls the operation of the A/D module. The
ADCON1 register, shown in Register 16-2, configures
the functions of the port pins. The ADCON2 register,
shown in Register 16-3, configures the A/D clock
source, programmed acquisition time and justification.
16.0 10-BIT ANALOG-TO-DIGITAL
CONVERTER (A/D) MODULE
The Analog-to-Digital (A/D) Converter module has
10 inputs for the 28-pin devices and 13 for the 40/44-pin
devices. This module allows conversion of an analog
input signal to a corresponding 10-bit digital number.
The module has five registers:
• A/D Result High Register (ADRESH)
• A/D Result Low Register (ADRESL)
• A/D Control Register 0 (ADCON0)
• A/D Control Register 1 (ADCON1)
• A/D Control Register 2 (ADCON2)
REGISTER 16-1: ADCON0: A/D CONTROL REGISTER 0
U0
—
U-0
—
R/W-0
CHS3
R/W-0
CHS2
R/W-0
CHS1
R/W-0
CHS0
R/W-0
R/W-0
ADON
GO/DONE
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7-6
bit 5-2
Unimplemented: Read as ‘0’
CHS3:CHS0: Analog Channel Select bits
0000= Channel 0 (AN0)
0001= Channel 1 (AN1)
0010= Channel 2 (AN2)
0011= Channel 3 (AN3)
0100= Channel 4 (AN4)
0101= Channel 5 (AN5)(1,2)
0110= Channel 6 (AN6)(1,2)
0111= Channel 7 (AN7)(1,2)
1000= Channel 8 (AN8)
1001= Channel 9 (AN9)
1010= Channel 10 (AN10)
1011= Channel 11 (AN11)
1100= Channel 12 (AN12
1101= Unimplemented(2)
1110= Unimplemented(2)
1111= Unimplemented(2)
bit 1
bit 0
GO/DONE: A/D Conversion Status bit
When ADON = 1:
1= A/D conversion in progress
0= A/D Idle
ADON: A/D On bit
1= A/D Converter module is enabled
0= A/D Converter module is disabled
Note 1: These channels are not implemented on 28-pin devices.
2: Performing a conversion on unimplemented channels will return a floating input measurement.
© 2008 Microchip Technology Inc.
DS39760D-page 175
PIC18F2450/4450
REGISTER 16-2: ADCON1: A/D CONTROL REGISTER 1
U-0
—
U-0
—
R/W-0
R/W-0
R/W-0(1)
PCFG3
R/W(1)
R/W(1)
R/W(1)
VCFG1
VCFG0
PCFG2
PCFG1
PCFG0
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7-6
bit 5
Unimplemented: Read as ‘0’
VCFG1: Voltage Reference Configuration bit (VREF- source)
1= VREF- (AN2)
0= VSS
bit 4
VCFG0: Voltage Reference Configuration bit (VREF+ source)
1= VREF+ (AN3)
0= VDD
bit 3-0
PCFG3:PCFG0: A/D Port Configuration Control bits:
PCFG3:
PCFG0
0000(1)
0001
0010
0011
0100
0101
0110
0111(1)
1000
1001
1010
1011
1100
1101
1110
1111
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
D
D
D
D
D
A
A
A
D
D
D
D
A
A
A
A
D
D
D
A
A
A
A
A
D
D
A
A
A
A
A
A
D
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
A
D
D
D
D
D
D
D
A
A
D
D
D
D
D
D
A
A
A
D
D
D
D
D
A
A
A
A
D
D
D
D
A
A
A
A
A
D
D
D
A
A
A
A
A
A
D
D
A
A
A
A
A
A
A
D
A = Analog input
D = Digital I/O
Note 1: The POR value of the PCFG bits depends on the value of the PBADEN Configuration bit. When
PBADEN = 1, PCFG<3:0> = 0000; when PBADEN = 0, PCFG<3:0> = 0111.
2: AN5 through AN7 are available only on 40/44-pin devices.
DS39760D-page 176
© 2008 Microchip Technology Inc.
PIC18F2450/4450
REGISTER 16-3: ADCON2: A/D CONTROL REGISTER 2
R/W-0
ADFM
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
ACQT2
ACQT1
ACQT0
ADCS2
ADCS1
ADCS0
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7
ADFM: A/D Result Format Select bit
1= Right justified
0= Left justified
bit 6
Unimplemented: Read as ‘0’
bit 5-3
ACQT2:ACQT0: A/D Acquisition Time Select bits
111= 20 TAD
110= 16 TAD
101= 12 TAD
100= 8 TAD
011= 6 TAD
010= 4 TAD
001= 2 TAD
(1)
000= 0 TAD
bit 2-0
ADCS2:ADCS0: A/D Conversion Clock Select bits
111= FRC (clock derived from A/D RC oscillator)(1)
110= FOSC/64
101= FOSC/16
100= FOSC/4
011= FRC (clock derived from A/D RC oscillator)(1)
010= FOSC/32
001= FOSC/8
000= FOSC/2
Note 1: If the A/D FRC clock source is selected, a delay of one TCY (instruction cycle) is added before the A/D
clock starts. This allows the SLEEPinstruction to be executed before starting a conversion.
© 2008 Microchip Technology Inc.
DS39760D-page 177
PIC18F2450/4450
The analog reference voltage is software selectable to
either the device’s positive and negative supply voltage
(VDD and VSS) or the voltage level on the RA3/AN3/
VREF+ and RA2/AN2/VREF- pins.
A device Reset forces all registers to their Reset state.
This forces the A/D module to be turned off and any
conversion in progress is aborted.
Each port pin associated with the A/D Converter can be
configured as an analog input or as a digital I/O. The
ADRESH and ADRESL registers contain the result of
the A/D conversion. When the A/D conversion is com-
plete, the result is loaded into the ADRESH:ADRESL
register pair, the GO/DONE bit (ADCON0 register) is
cleared and A/D Interrupt Flag bit, ADIF, is set. The block
diagram of the A/D module is shown in Figure 16-1.
The A/D Converter has a unique feature of being able
to operate while the device is in Sleep mode. To
operate in Sleep, the A/D conversion clock must be
derived from the A/D’s internal RC oscillator.
The output of the sample and hold is the input into the
converter, which generates the result via successive
approximation.
FIGURE 16-1:
A/D BLOCK DIAGRAM
CHS3:CHS0
1100
AN12
1011
AN11
1010
AN10
1001
AN9
1000
AN8
0111
AN7(1)
0110
AN6(1)
0101
AN5(1)
0100
AN4
VAIN
0011
(Input Voltage)
10-Bit
A/D
Converter
AN3
0010
AN2
0001
VCFG1:VCFG0
AN1
(2)
0000
VDD
AN0
X0
X1
1X
VREF+
VREF-
Reference
Voltage
0X
(2)
VSS
Note 1: Channels AN5 through AN7 are not available on 28-pin devices.
2: I/O pins have diode protection to VDD and VSS.
DS39760D-page 178
© 2008 Microchip Technology Inc.
PIC18F2450/4450
The value in the ADRESH:ADRESL registers is not
modified for a Power-on Reset. The ADRESH:ADRESL
registers will contain unknown data after a Power-on
Reset.
5. Wait for A/D conversion to complete, by either:
• Polling for the GO/DONE bit to be cleared
OR
• Waiting for the A/D interrupt
After the A/D module has been configured as desired, the
selected channel must be acquired before the conver-
sion is started. The analog input channels must have
their corresponding TRIS bits selected as an input. To
determine acquisition time, see Section 16.1 “A/D
Acquisition Requirements”. After this acquisition time
has elapsed, the A/D conversion can be started. An
acquisition time can be programmed to occur between
setting the GO/DONE bit and the actual start of the
conversion.
6. Read A/D Result registers (ADRESH:ADRESL);
clear bit, ADIF, if required.
7. For next conversion, go to step 1 or step 2, as
required. The A/D conversion time per bit is
defined as TAD. A minimum wait of 3 TAD is
required before the next acquisition starts.
FIGURE 16-2:
A/D TRANSFER FUNCTION
The following steps should be followed to perform an
A/D conversion:
3FFh
3FEh
1. Configure the A/D module:
• Configure analog pins, voltage reference and
digital I/O (ADCON1)
• Select A/D input channel (ADCON0)
• Select A/D acquisition time (ADCON2)
• Select A/D conversion clock (ADCON2)
• Turn on A/D module (ADCON0)
2. Configure A/D interrupt (if desired):
• Clear ADIF bit
003h
002h
001h
000h
• Set ADIE bit
• Set GIE bit
3. Wait the required acquisition time (if required).
4. Start conversion:
Analog Input Voltage
• Set GO/DONE bit (ADCON0 register)
FIGURE 16-3:
ANALOG INPUT MODEL
VDD
Sampling
Switch
VT = 0.6V
ANx
SS
RIC ≤ 1k
RSS
Rs
CPIN
VAIN
ILEAKAGE
±100 nA
CHOLD = 25 pF
VT = 0.6V
5 pF
VSS
Legend: CPIN
= Input Capacitance
= Threshold Voltage
VT
6V
5V
4V
3V
2V
ILEAKAGE = Leakage Current at the pin due to
various junctions
VDD
RIC
= Interconnect Resistance
= Sampling Switch
SS
CHOLD
RSS
= Sample/hold Capacitance (from DAC)
= Sampling Switch Resistance
1
2
3
4
Sampling Switch (kΩ)
© 2008 Microchip Technology Inc.
DS39760D-page 179
PIC18F2450/4450
To calculate the minimum acquisition time,
Equation 16-1 may be used. This equation assumes
that 1/2 LSb error is used (1024 steps for the A/D). The
1/2 LSb error is the maximum error allowed for the A/D
to meet its specified resolution.
16.1 A/D Acquisition Requirements
For the A/D Converter to meet its specified accuracy,
the charge holding capacitor (CHOLD) must be allowed
to fully charge to the input channel voltage level. The
analog input model is shown in Figure 16-3. The
source impedance (RS) and the internal sampling
switch (RSS) impedance directly affect the time
required to charge the capacitor CHOLD. The sampling
switch (RSS) impedance varies over the device voltage
(VDD). The source impedance affects the offset voltage
at the analog input (due to pin leakage current). The
maximum recommended impedance for analog
sources is 2.5 kΩ. After the analog input channel is
selected (changed), the channel must be sampled for
at least the minimum acquisition time before starting a
conversion.
Example 16-3 shows the calculation of the minimum
required acquisition time TACQ. This calculation is
based on the following application system
assumptions:
CHOLD
Rs
Conversion Error
VDD
Temperature
=
=
≤
=
=
25 pF
2.5 kΩ
1/2 LSb
5V → RSS = 2 kΩ
85°C (system max.)
Note:
When the conversion is started, the
holding capacitor is disconnected from the
input pin.
EQUATION 16-1: ACQUISITION TIME
TACQ
=
=
Amplifier Settling Time + Holding Capacitor Charging Time + Temperature Coefficient
TAMP + TC + TCOFF
EQUATION 16-2: A/D MINIMUM CHARGING TIME
VHOLD
or
TC
=
=
(VREF – (VREF/2048)) • (1 – e(-TC/CHOLD(RIC + RSS + RS))
)
-(CHOLD)(RIC + RSS + RS) ln(1/2048)
EQUATION 16-3: CALCULATING THE MINIMUM REQUIRED ACQUISITION TIME
TACQ
TAMP
TCOFF
=
=
=
TAMP + TC + TCOFF
0.2 μs
(Temp – 25°C)(0.02 μs/°C)
(85°C – 25°C)(0.02 μs/°C)
1.2 μs
Temperature coefficient is only required for temperatures > 25°C. Below 25°C, TCOFF = 0 ms.
TC
=
-(CHOLD)(RIC + RSS + RS) ln(1/2047) μs
-(25 pF) (1 kΩ + 2 kΩ + 2.5 kΩ) ln(0.0004883) μs
1.05 μs
TACQ
=
0.2 μs + 1 μs + 1.2 μs
2.4 μs
DS39760D-page 180
© 2008 Microchip Technology Inc.
PIC18F2450/4450
16.2 Selecting and Configuring
Acquisition Time
16.3 Selecting the A/D Conversion
Clock
The ADCON2 register allows the user to select an
acquisition time that occurs each time the GO/DONE
bit is set. It also gives users the option to use an
automatically determined acquisition time.
The A/D conversion time per bit is defined as TAD. The
A/D conversion requires 11 TAD per 10-bit conversion.
The source of the A/D conversion clock is software
selectable. There are seven possible options for TAD:
Acquisition time may be set with the ACQT2:ACQT0 bits
(ADCON2<5:3>) which provide a range of 2 to 20 TAD.
When the GO/DONE bit is set, the A/D module
continues to sample the input for the selected acquisition
time, then automatically begins a conversion. Since the
acquisition time is programmed, there may be no need
to wait for an acquisition time between selecting a
channel and setting the GO/DONE bit.
• 2 TOSC
• 4 TOSC
• 8 TOSC
• 16 TOSC
• 32 TOSC
• 64 TOSC
• Internal RC Oscillator
Manual
acquisition
is
selected
when
For correct A/D conversions, the A/D conversion clock
(TAD) must be as short as possible but greater than the
minimum TAD (see parameter 130 in Table 21-18 for
more information).
ACQT2:ACQT0 = 000. When the GO/DONE bit is set,
sampling is stopped and a conversion begins. The user
is responsible for ensuring the required acquisition time
has passed between selecting the desired input
channel and setting the GO/DONE bit. This option is
also the default Reset state of the ACQT2:ACQT0 bits
and is compatible with devices that do not offer
programmable acquisition times.
Table 16-1 shows the resultant TAD times derived from
the device operating frequencies and the A/D clock
source selected.
In either case, when the conversion is completed, the
GO/DONE bit is cleared, the ADIF flag is set and the
A/D begins sampling the currently selected channel
again. If an acquisition time is programmed, there is
nothing to indicate if the acquisition time has ended or
if the conversion has begun.
TABLE 16-1: TAD vs. DEVICE OPERATING FREQUENCIES
AD Clock Source (TAD)
Maximum Device Frequency
Operation
ADCS2:ADCS0
PIC18FX450
PIC18LFX450(4)
2 TOSC
4 TOSC
8 TOSC
16 TOSC
32 TOSC
64 TOSC
RC(3)
000
100
001
101
010
110
x11
2.86 MHz
5.71 MHz
11.43 MHz
22.86 MHz
45.71 MHz
48.0 MHz
1.00 MHz(1)
1.43 MHz
2.86 MHz
5.72 MHz
11.43 MHz
22.86 MHz
45.71 MHz
1.00 MHz(2)
Note 1: The RC source has a typical TAD time of 1.2 μs.
2: The RC source has a typical TAD time of 2.5 μs.
3: For device frequencies above 1 MHz, the device must be in Sleep for the entire conversion or the A/D
accuracy may be out of specification.
4: Low-power devices only.
© 2008 Microchip Technology Inc.
DS39760D-page 181
PIC18F2450/4450
16.4 Operation in Power-Managed
Modes
16.5 Configuring Analog Port Pins
The ADCON1, TRISA, TRISB and TRISE registers all
configure the A/D port pins. The port pins needed as
analog inputs must have their corresponding TRIS bits
set (input). If the TRIS bit is cleared (output), the digital
output level (VOH or VOL) will be converted.
The selection of the automatic acquisition time and
A/D conversion clock is determined in part by the clock
source and frequency while in a power-managed
mode.
The A/D operation is independent of the state of the
CHS3:CHS0 bits and the TRIS bits.
If the A/D is expected to operate while the device is in
a power-managed mode, the ACQT2:ACQT0 and
ADCS2:ADCS0 bits in ADCON2 should be updated in
accordance with the clock source to be used in that
mode. After entering the mode, an A/D acquisition or
conversion may be started. Once started, the device
should continue to be clocked by the same clock
source until the conversion has been completed.
Note 1: When reading the PORT register, all pins
configured as analog input channels will
read as cleared (a low level). Pins config-
ured as digital inputs will convert as ana-
log inputs. Analog levels on a digitally
configured input will be accurately
converted.
If desired, the device may be placed into the
corresponding Idle mode during the conversion. If the
device clock frequency is less than 1 MHz, the A/D RC
clock source should be selected.
2: Analog levels on any pin defined as a
digital input may cause the digital input
buffer to consume current out of the
device’s specification limits.
Operation in the Sleep mode requires the A/D FRC
clock to be selected. If bits ACQT2:ACQT0 are set to
‘000’ and a conversion is started, the conversion will be
delayed one instruction cycle to allow execution of the
SLEEPinstruction and entry to Sleep mode. The IDLEN
bit (OSCCON<7>) must have already been cleared
prior to starting the conversion.
3: The PBADEN bit in Configuration
Register 3H configures PORTB pins to
reset as analog or digital pins by control-
ling how the PCFG0 bits in ADCON1 are
reset.
DS39760D-page 182
© 2008 Microchip Technology Inc.
PIC18F2450/4450
After the A/D conversion is completed or aborted, a
2 TAD wait is required before the next acquisition can be
started. After this wait, acquisition on the selected
channel is automatically started.
16.6 A/D Conversions
Figure 16-4 shows the operation of the A/D Converter
after the GO/DONE bit has been set and the
ACQT2:ACQT0 bits are cleared. A conversion is
started after the following instruction to allow entry into
Sleep mode before the conversion begins.
Note:
The GO/DONE bit should NOT be set in
the same instruction that turns on the A/D.
Figure 16-5 shows the operation of the A/D Converter
after the GO/DONE bit has been set, the
ACQT2:ACQT0 bits are set to ‘010’ and selecting a
4 TAD acquisition time before the conversion starts.
16.7 Discharge
The discharge phase is used to initialize the value of
the capacitor array. The array is discharged before
every sample. This feature helps to optimize the unity-
gain amplifier as the circuit always needs to charge the
capacitor array, rather than charge/discharge based on
previous measurement values.
Clearing the GO/DONE bit during a conversion will
abort the current conversion. The A/D Result register
pair will NOT be updated with the partially completed
A/D
conversion
sample.
This
means
the
ADRESH:ADRESL registers will continue to contain
the value of the last completed conversion (or the last
value written to the ADRESH:ADRESL registers).
FIGURE 16-4:
A/D CONVERSION TAD CYCLES (ACQT<2:0> = 000, TACQ = 0)
TCY - TAD
TAD6 TAD7 TAD8 TAD9 TAD10 TAD11 TAD1
TAD1 TAD2 TAD3 TAD4 TAD5
b7
b6
b4
b1
b0
b9
b8
b5
b3
b2
Conversion starts
Discharge
Holding capacitor is disconnected from analog input (typically 100 ns)
Set GO/DONE bit
On the following cycle:
ADRESH:ADRESL is loaded, GO/DONE bit is cleared,
ADIF bit is set, holding capacitor is connected to analog input.
FIGURE 16-5:
A/D CONVERSION TAD CYCLES (ACQT<2:0> = 010, TACQ = 4 TAD)
TACQ Cycles
TAD Cycles
7
8
9
10
b1
11 TAD1
b0
1
2
3
4
1
2
3
4
5
6
b7
b6
b3
b2
b8
b5
b4
b9
Automatic
Acquisition
Time
Discharge
Conversion starts
(Holding capacitor is disconnected)
Set GO/DONE bit
(Holding capacitor continues
acquiring input)
On the following cycle:
ADRESH:ADRESL is loaded, GO/DONE bit is cleared,
ADIF bit is set, holding capacitor is connected to analog input.
© 2008 Microchip Technology Inc.
DS39760D-page 183
PIC18F2450/4450
(moving ADRESH:ADRESL to the desired location).
The appropriate analog input channel must be selected
and the minimum acquisition period is either timed by
the user, or an appropriate TACQ time selected before
the Special Event Trigger sets the GO/DONE bit (starts
a conversion).
16.8 Use of the CCP1 Trigger
An A/D conversion can be started by the Special Event
Trigger of the CCP1 module. This requires that the
CCP1M3:CCP1M0
bits
(CCP1CON<3:0>)
be
programmed as ‘1011’ and that the A/D module is
enabled (ADON bit is set). When the trigger occurs, the
GO/DONE bit will be set, starting the A/D acquisition
and conversion, and the Timer1 counter will be reset to
zero. Timer1 is reset to automatically repeat the A/D
acquisition period with minimal software overhead
If the A/D module is not enabled (ADON is cleared), the
Special Event Trigger will be ignored by the A/D module
but will still reset the Timer1 counter.
TABLE 16-2: REGISTERS ASSOCIATED WITH A/D OPERATION
Reset
Values
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
on Page:
INTCON
PIR1
PIE1
GIE/GIEH PEIE/GIEL TMR0IE
INT0IE
TXIF
TXIE
TXIP
—
RBIE
—
TMR0IF
CCP1IF
CCP1IE
CCP1IP
HLVDIF
HLVDIE
HLVDIP
INT0IF
TMR2IF
TMR2IE
TMR2IP
—
RBIF
TMR1IF
TMR1IE
TMR1IP
—
49
51
51
51
51
51
51
50
50
50
50
50
51
51
51
51
51
51
51
51
—
—
ADIF
ADIE
ADIP
—
RCIF
RCIE
—
IPR1
PIR2
PIE2
—
RCIP
—
OSCFIF
OSCFIE
OSCFIP
USBIF
USBIE
USBIP
—
—
—
—
—
—
IPR2
—
—
—
—
—
ADRESH A/D Result Register High Byte
ADRESL A/D Result Register Low Byte
ADCON0
ADCON1
ADCON2
PORTA
TRISA
—
—
—
—
CHS3
VCFG1
ACQT2
RA5
CHS2
VCFG0
ACQT1
RA4
CHS1
PCFG3
ACQT0
RA3
CHS0 GO/DONE ADON
PCFG2
ADCS2
RA2
PCFG1
ADCS1
RA1
PCFG0
ADCS0
RA0
ADFM
—
—
RA6(2)
—
TRISA6(2) TRISA5
TRISA4
RB4
TRISA3
RB3
TRISA2
RB2
TRISA1
RB1
TRISA0
RB0
PORTB
TRISB
RB7
TRISB7
LATB7
—
RB6
TRISB6
LATB6
—
RB5
TRISB5
LATB5
—
TRISB4
LATB4
—
TRISB3
LATB3
RE3(1,3)
—
TRISB2
LATB2
RE2(4)
TRISB1
LATB1
RE1(4)
TRISB0
LATB0
RE0(4)
LATB
PORTE
TRISE(4)
LATE(4)
—
—
—
—
TRISE2(4) TRISE1(4) TRISE0(4)
LATE2(4) LATE1(4) LATE0(4)
—
—
—
—
—
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used for A/D conversion.
Note 1: Implemented only when Master Clear functionality is disabled (MCLRE Configuration bit = 0).
2: RA6 and its associated latch and data direction bits are enabled as I/O pins based on oscillator
configuration; otherwise, they are read as ‘0’.
3: RE3 port bit is available only as an input pin when the MCLRE Configuration bit is ‘0’.
4: These registers and/or bits are not implemented on 28-pin devices.
DS39760D-page 184
© 2008 Microchip Technology Inc.
PIC18F2450/4450
The High/Low-Voltage Detect Control register
(Register 17-1) completely controls the operation of the
HLVD module. This allows the circuitry to be “turned
off” by the user under software control which minimizes
the current consumption for the device.
17.0 HIGH/LOW-VOLTAGE DETECT
(HLVD)
PIC18F2450/4450 devices have a High/Low-Voltage
Detect module (HLVD). This is a programmable circuit
that allows the user to specify both a device voltage trip
point and the direction of change from that point. If the
device experiences an excursion past the trip point in
that direction, an interrupt flag is set. If the interrupt is
enabled, the program execution will branch to the
interrupt vector address and the software can then
respond to the interrupt.
The block diagram for the HLVD module is shown in
Figure 17-1.
REGISTER 17-1: HLVDCON: HIGH/LOW-VOLTAGE DETECT CONTROL REGISTER
R/W-0
U-0
—
R-0
R/W-0
R/W-0
HLVDL3(1)
R/W-1
HLVDL2(1)
R/W-0
HLVDL1(1)
R/W-1
HLVDL0(1)
VDIRMAG
IRVST
HLVDEN
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7
VDIRMAG: Voltage Direction Magnitude Select bit
1= Event occurs when voltage equals or exceeds trip point (HLVDL3:HLDVL0)
0= Event occurs when voltage equals or falls below trip point (HLVDL3:HLVDL0)
bit 6
bit 5
Unimplemented: Read as ‘0’
IRVST: Internal Reference Voltage Stable Flag bit
1= Indicates that the voltage detect logic will generate the interrupt flag at the specified voltage
trip point
0= Indicates that the voltage detect logic will not generate the interrupt flag at the specified voltage
trip point and the LVD interrupt should not be enabled
bit 4
HLVDEN: High/Low-Voltage Detect Power Enable bit
1= HLVD enabled
0= HLVD disabled
bit 3-0
HLVDL3:HLVDL0: Voltage Detection Limit bits(1)
1111= Reserved
1110= Maximum setting
.
.
.
0000= Minimum setting
Note 1: See Table 21-4 in Section 21.0 “Electrical Characteristics” for specifications.
© 2008 Microchip Technology Inc.
DS39760D-page 185
PIC18F2450/4450
The module is enabled by setting the HLVDEN bit.
Each time that the HLVD module is enabled, the
circuitry requires some time to stabilize. The IRVST bit
is a read-only bit and is used to indicate when the circuit
is stable. The module can only generate an interrupt
after the circuit is stable and IRVST is set.
event, depending on the configuration of the module.
When the supply voltage is equal to the trip point, the
voltage tapped off of the resistor array is equal to the
internal reference voltage generated by the voltage
reference module. The comparator then generates an
interrupt signal by setting the HLVDIF bit.
The VDIRMAG bit determines the overall operation of
the module. When VDIRMAG is cleared, the module
monitors for drops in VDD below a predetermined set
point. When the bit is set, the module monitors for rises
in VDD above the set point.
The trip point voltage is software programmable to any
one of 16 values. The trip point is selected by
programming
the
HLVDL3:HLVDL0
bits
(HLVDCON<3:0>).
The HLVD module has an additional feature that allows
the user to supply the trip voltage to the module from an
external source. This mode is enabled when bits,
HLVDL3:HLVDL0, are set to ‘1111’. In this state, the
comparator input is multiplexed from the external input
pin, HLVDIN. This gives users flexibility because it
allows them to configure the High/Low-Voltage Detect
interrupt to occur at any voltage in the valid operating
range.
17.1 Operation
When the HLVD module is enabled, a comparator uses
an internally generated reference voltage as the set
point. The set point is compared with the trip point,
where each node in the resistor divider represents a
trip point voltage. The “trip point” voltage is the voltage
level at which the device detects a high or low-voltage
FIGURE 17-1:
HLVD MODULE BLOCK DIAGRAM (WITH EXTERNAL INPUT)
Externally Generated
Trip Point
VDD
VDD
HLVDL3:HLVDL0
HLVDCON
Register
VDIRMAG
HLVDEN
HLVDIN
Set
HLVDIF
HLVDEN
BOREN
Internal Voltage
Reference
1.2V Typical
DS39760D-page 186
© 2008 Microchip Technology Inc.
PIC18F2450/4450
Depending on the application, the HLVD module does
not need to be operating constantly. To decrease the
current requirements, the HLVD circuitry may only
need to be enabled for short periods where the voltage
is checked. After doing the check, the HLVD module
may be disabled.
17.2 HLVD Setup
The following steps are needed to set up the HLVD
module:
1. Disable the module by clearing the HLVDEN bit
(HLVDCON<4>).
2. Write the value to the HLVDL3:HLVDL0 bits that
selects the desired HLVD trip point.
17.4 HLVD Start-up Time
3. Set the VDIRMAG bit to detect high voltage
The internal reference voltage of the HLVD module,
specified in electrical specification parameter D420 (see
Table 21-4 in Section 21.0 “Electrical Characteris-
tics”), may be used by other internal circuitry, such as
the Programmable Brown-out Reset. If the HLVD or
other circuits using the voltage reference are disabled to
lower the device’s current consumption, the reference
voltage circuit will require time to become stable before
a low or high-voltage condition can be reliably detected.
This start-up time, TIRVST, is an interval that is
independent of device clock speed. It is specified in
electrical specification parameter 36 (Table 21-10).
(VDIRMAG = 1) or low voltage (VDIRMAG = 0).
4. Enable the HLVD module by setting the
HLVDEN bit.
5. Clear the HLVD Interrupt Flag, HLVDIF
(PIR2<2>), which may have been set from a
previous interrupt.
6. Enable the HLVD interrupt, if interrupts are
desired, by setting the HLVDIE and GIE/GIEH
bits (PIE2<2> and INTCON<7>). An interrupt
will not be generated until the IRVST bit is set.
The HLVD interrupt flag is not enabled until TIRVST has
expired and a stable reference voltage is reached. For
this reason, brief excursions beyond the set point may
not be detected during this interval. Refer to Figure 17-2
or Figure 17-3.
17.3 Current Consumption
When the module is enabled, the HLVD comparator
and voltage divider are enabled and will consume static
current. The total current consumption, when enabled,
is specified in electrical specification parameter D022
(Section 270 “DC Characteristics”).
FIGURE 17-2:
LOW-VOLTAGE DETECT OPERATION (VDIRMAG = 0)
CASE 1:
HLVDIF may not be set
VDD
VHLVD
HLVDIF
Enable HLVD
IRVST
TIRVST
HLVDIF Cleared in Software
Internal Reference is Stable
CASE 2:
VDD
VHLVD
HLVDIF
Enable HLVD
TIRVST
IRVST
Internal Reference is Stable
HLVDIF Cleared in Software
HLVDIF Cleared in Software,
HLVDIF Remains Set since HLVD Condition still Exists
© 2008 Microchip Technology Inc.
DS39760D-page 187
PIC18F2450/4450
FIGURE 17-3:
HIGH-VOLTAGE DETECT OPERATION (VDIRMAG = 1)
CASE 1:
HLVDIF may not be Set
VHLVD
VDD
HLVDIF
Enable HLVD
IRVST
TIRVST
HLVDIF Cleared in Software
Internal Reference is Stable
CASE 2:
VHLVD
VDD
HLVDIF
Enable HLVD
TIRVST
IRVST
Internal Reference is Stable
HLVDIF Cleared in software
HLVDIF Cleared in Software,
HLVDIF Remains Set since HLVD Condition still Exists
FIGURE 17-4:
TYPICAL
17.5 Applications
HIGH/LOW-VOLTAGE
DETECT APPLICATION
In many applications, the ability to detect a drop below
or rise above a particular threshold is desirable. For
example, the HLVD module could be periodically
enabled to detect Universal Serial Bus (USB) attach or
detach. This assumes the device is powered by a lower
voltage source than the USB when detached. An attach
would indicate a high-voltage detect from, for example,
3.3V to 5V (the voltage on USB) and vice versa for a
detach. This feature could save a design a few extra
components and an attach signal (input pin).
VA
VB
For general battery applications, Figure 17-4 shows a
possible voltage curve. Over time, the device voltage
decreases. When the device voltage reaches voltage,
VA, the HLVD logic generates an interrupt at time, TA.
The interrupt could cause the execution of an ISR,
which would allow the application to perform “house-
keeping tasks” and perform a controlled shutdown
before the device voltage exits the valid operating
range at TB. The HLVD, thus, would give the applica-
tion a time window, represented by the difference
between TA and TB, to safely exit.
TB
Legend: VA = HLVD trip point
TA
Time
VB = Minimum valid device
operating voltage
DS39760D-page 188
© 2008 Microchip Technology Inc.
PIC18F2450/4450
17.6 Operation During Sleep
17.7 Effects of a Reset
When enabled, the HLVD circuitry continues to operate
during Sleep. If the device voltage crosses the trip
point, the HLVDIF bit will be set and the device will
wake-up from Sleep. Device execution will continue
from the interrupt vector address if interrupts have
been globally enabled.
A device Reset forces all registers to their Reset state.
This forces the HLVD module to be turned off.
TABLE 17-1: REGISTERS ASSOCIATED WITH HIGH/LOW-VOLTAGE DETECT MODULE
Reset
Values
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
on Page:
HLVDCON VDIRMAG
—
IRVST
HLVDEN HLVDL3 HLVDL2 HLVDL1 HLVDL0
50
49
51
51
51
INTCON
PIR2
GIE/GIEH PEIE/GIEL TMR0IE
INT0IE
—
RBIE
—
TMR0IF
HLVDIF
HLVDIE
HLVDIP
INT0IF
—
RBIF
—
OSCFIF
OSCFIE
OSCFIP
—
—
—
USBIF
USBIE
USBIP
PIE2
—
—
—
—
IPR2
—
—
—
—
Legend: — = unimplemented, read as ‘0’. Shaded cells are unused by the HLVD module.
© 2008 Microchip Technology Inc.
DS39760D-page 189
PIC18F2450/4450
NOTES:
DS39760D-page 190
© 2008 Microchip Technology Inc.
PIC18F2450/4450
In addition to their Power-up and Oscillator Start-up
Timers provided for Resets, PIC18F2450/4450 devices
have a Watchdog Timer, which is either permanently
enabled via the Configuration bits or software
controlled (if configured as disabled).
18.0 SPECIAL FEATURES OF THE
CPU
PIC18F2450/4450 devices include several features
intended to maximize reliability and minimize cost
through elimination of external components. These are:
The inclusion of an internal RC oscillator also provides
the additional benefits of a Fail-Safe Clock Monitor
(FSCM) and Two-Speed Start-up. FSCM provides for
background monitoring of the peripheral clock and
automatic switchover in the event of its failure. Two-
Speed Start-up enables code to be executed almost
immediately on start-up, while the primary clock source
completes its start-up delays.
• Oscillator Selection
• Resets:
- Power-on Reset (POR)
- Power-up Timer (PWRT)
- Oscillator Start-up Timer (OST)
- Brown-out Reset (BOR)
• Interrupts
All of these features are enabled and configured by
setting the appropriate Configuration register bits.
• Watchdog Timer (WDT)
• Fail-Safe Clock Monitor (FSCM)
• Two-Speed Start-up
• Code Protection
• ID Locations
• In-Circuit Serial Programming (ICSP)
The oscillator can be configured for the application
depending on frequency, power, accuracy and cost. All
of the options are discussed in detail in Section 2.0
“Oscillator Configurations”.
A complete discussion of device Resets and interrupts
is available in previous sections of this data sheet.
© 2008 Microchip Technology Inc.
DS39760D-page 191
PIC18F2450/4450
Programming the Configuration registers is done in a
manner similar to programming the Flash memory. The
WR bit in the EECON1 register starts a self-timed write
to the Configuration register. In normal operation mode,
a TBLWT instruction, with the TBLPTR pointing to the
Configuration register, sets up the address and the
data for the Configuration register write. Setting the WR
bit starts a long write to the Configuration register. The
Configuration registers are written a byte at a time. To
write or erase a configuration cell, a TBLWTinstruction
can write a ‘1’ or a ‘0’ into the cell. For additional details
on Flash programming, refer to Section 6.5 “Writing
to Flash Program Memory”.
18.1 Configuration Bits
The Configuration bits can be programmed (read as
‘0’) or left unprogrammed (read as ‘1’) to select various
device configurations. These bits are mapped starting
at program memory location 300000h.
The user will note that address 300000h is beyond the
user program memory space. In fact, it belongs to the
configuration memory space (300000h-3FFFFFh), which
can only be accessed using table reads and table writes.
TABLE 18-1: CONFIGURATION BITS AND DEVICE IDs
Default/
Unprogrammed
Value
File Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
300000h CONFIG1L
300001h CONFIG1H
300002h CONFIG2L
300003h CONFIG2H
—
IESO
—
—
FCMEN
—
USBDIV CPUDIV1 CPUDIV0 PLLDIV2 PLLDIV1 PLLDIV0
FOSC3 FOSC2 FOSC1 FOSC0
BORV0 BOREN1 BOREN0 PWRTEN
WDTPS3 WDTPS2 WDTPS1 WDTPS0 WDTEN
--00 0111
00-- 0111
--01 1111
---1 1111
1--- -01-
100- 01-1
---- --11
-1-- ----
---- --11
-11- ----
---- --11
-1-- ----
—
—
VREGEN BORV1
—
—
—
—
300005h CONFIG3H MCLRE
—
—
—
—
BBSIZ
—
LPT1OSC PBADEN
—
STVREN
CP0
(2)
300006h CONFIG4L DEBUG XINST ICPRT
LVP
—
—
CP1
—
300008h CONFIG5L
300009h CONFIG5H
30000Ah CONFIG6L
30000Bh CONFIG6H
30000Ch CONFIG7L
30000Dh CONFIG7H
3FFFFEh DEVID1
—
—
—
CPB
—
—
—
—
—
—
—
—
—
—
—
—
—
WRT1
—
WRT0
—
—
WRTB
—
WRTC
—
—
—
—
—
—
—
—
EBTR1
—
EBTR0
—
—
EBTRB
DEV1
DEV9
—
—
—
—
(1)
DEV2
DEV10
DEV0
DEV8
REV4
DEV7
REV3
DEV6
REV2
DEV5
REV1
DEV4
REV0
DEV3
xxxx xxxx
(1)
3FFFFFh DEVID2
0001 0010
Legend:
x= unknown, u= unchanged, - = unimplemented. Shaded cells are unimplemented, read as ‘0’.
Note 1: See Register 18-13 and Register 18-14 for device ID values. DEVID registers are read-only and cannot be programmed
by the user.
2: Available only on PIC18F4450 devices in 44-pin TQFP packages. Always leave this bit clear in all other devices.
DS39760D-page 192
© 2008 Microchip Technology Inc.
PIC18F2450/4450
REGISTER 18-1: CONFIG1L: CONFIGURATION REGISTER 1 LOW (BYTE ADDRESS 300000h)
U-0
—
U-0
—
R/P-0
R/P-0
R/P-0
R/P-1
R/P-1
R/P-1
USBDIV
CPUDIV1
CPUDIV0
PLLDIV2
PLLDIV1
PLLDIV0
bit 7
bit 0
Legend:
R = Readable bit
P = Programmable bit
U = Unimplemented bit, read as ‘0’
-n = Value when device is unprogrammed
u = Unchanged from programmed state
bit 7-6
bit 5
Unimplemented: Read as ‘0’
USBDIV: USB Clock Selection bit (used in Full-Speed USB mode only; UCFG:FSEN = 1)
1= USB clock source comes from the 96 MHz PLL divided by 2
0= USB clock source comes directly from the primary oscillator block with no postscale
bit 4-3
CPUDIV1:CPUDIV0: System Clock Postscaler Selection bits
For XT, HS, EC and ECIO Oscillator modes:
11= Primary oscillator divided by 4 to derive system clock
10= Primary oscillator divided by 3 to derive system clock
01= Primary oscillator divided by 2 to derive system clock
00= Primary oscillator used directly for system clock (no postscaler)
For XTPLL, HSPLL, ECPLL and ECPIO Oscillator modes:
11= 96 MHz PLL divided by 6 to derive system clock
10= 96 MHz PLL divided by 4 to derive system clock
01= 96 MHz PLL divided by 3 to derive system clock
00= 96 MHz PLL divided by 2 to derive system clock
bit 2-0
PLLDIV2:PLLDIV0: PLL Prescaler Selection bits
111= Divide by 12 (48 MHz oscillator input)
110= Divide by 10 (40 MHz oscillator input)
101= Divide by 6 (24 MHz oscillator input)
100= Divide by 5 (20 MHz oscillator input)
011= Divide by 4 (16 MHz oscillator input)
010= Divide by 3 (12 MHz oscillator input)
001= Divide by 2 (8 MHz oscillator input)
000= No prescale (4 MHz oscillator input drives PLL directly)
© 2008 Microchip Technology Inc.
DS39760D-page 193
PIC18F2450/4450
REGISTER 18-2: CONFIG1H: CONFIGURATION REGISTER 1 HIGH (BYTE ADDRESS 300001h)
R/P-0
IESO
R/P-0
U-0
—
U-0
—
R/P-0
FOSC3(1)
R/P-1
FOSC2(1)
R/P-1
FOSC1(1)
R/P-1
FOSC0(1)
FCMEN
bit 7
bit 0
Legend:
R = Readable bit
P = Programmable bit
U = Unimplemented bit, read as ‘0’
-n = Value when device is unprogrammed
u = Unchanged from programmed state
bit 7
bit 6
IESO: Internal/External Oscillator Switchover bit
1= Oscillator Switchover mode enabled
0= Oscillator Switchover mode disabled
FCMEN: Fail-Safe Clock Monitor Enable bit
1= Fail-Safe Clock Monitor enabled
0= Fail-Safe Clock Monitor disabled
bit 5-4
bit 3-0
Unimplemented: Read as ‘0’
FOSC3:FOSC0: Oscillator Selection bits(1)
111x= HS oscillator, PLL enabled (HSPLL)
110x= HS oscillator (HS)
1011= Internal oscillator, HS oscillator used by USB (INTHS)
1010= Internal oscillator, XT used by USB (INTXT)
1001= Internal oscillator, CLKO function on RA6, EC used by USB (INTCKO)
1000= Internal oscillator, port function on RA6, EC used by USB (INTIO)
0111= EC oscillator, PLL enabled, CLKO function on RA6 (ECPLL)
0110= EC oscillator, PLL enabled, port function on RA6 (ECPIO)
0101= EC oscillator, CLKO function on RA6 (EC)
0100= EC oscillator, port function on RA6 (ECIO)
001x= XT oscillator, PLL enabled (XTPLL)
000x= XT oscillator (XT)
Note 1: The microcontroller and USB module both use the selected oscillator as their clock source in XT, HS and
EC modes. The USB module uses the indicated XT, HS or EC oscillator as its clock source whenever the
microcontroller uses the internal oscillator.
DS39760D-page 194
© 2008 Microchip Technology Inc.
PIC18F2450/4450
REGISTER 18-3: CONFIG2L: CONFIGURATION REGISTER 2 LOW (BYTE ADDRESS 300002h)
U-0
—
U-0
—
R/P-0
R/P-1
BORV1(1)
R/P-1
BORV0(1)
R/P-1
BOREN1(2)
R/P-1
R/P-1
VREGEN
BOREN0(2) PWRTEN(2)
bit 7
bit 0
Legend:
R = Readable bit
P = Programmable bit
U = Unimplemented bit, read as ‘0’
-n = Value when device is unprogrammed
u = Unchanged from programmed state
bit 7-6
bit 5
Unimplemented: Read as ‘0’
VREGEN: USB Internal Voltage Regulator Enable bit
1= USB voltage regulator enabled
0= USB voltage regulator disabled
bit 4-3
BORV1:BORV0: Brown-out Reset Voltage bits(1)
11= Minimum setting
.
.
.
00= Maximum setting
bit 2-1
bit 0
BOREN1:BOREN0: Brown-out Reset Enable bits(2)
11= Brown-out Reset enabled in hardware only (SBOREN is disabled)
10= Brown-out Reset enabled in hardware only and disabled in Sleep mode (SBOREN is disabled)
01= Brown-out Reset enabled and controlled by software (SBOREN is enabled)
00= Brown-out Reset disabled in hardware and software
PWRTEN: Power-up Timer Enable bit(2)
1= PWRT disabled
0= PWRT enabled
Note 1: See Section 21.0 “Electrical Characteristics” for the specifications.
2: The Power-up Timer is decoupled from Brown-out Reset, allowing these features to be independently
controlled.
© 2008 Microchip Technology Inc.
DS39760D-page 195
PIC18F2450/4450
REGISTER 18-4: CONFIG2H: CONFIGURATION REGISTER 2 HIGH (BYTE ADDRESS 300003h)
U-0
—
U-0
—
U-0
—
R/P-1
R/P-1
R/P-1
R/P-1
R/P-1
WDTPS3
WDTPS2
WDTPS1
WDTPS0
WDTEN
bit 7
bit 0
Legend:
R = Readable bit
P = Programmable bit
U = Unimplemented bit, read as ‘0’
-n = Value when device is unprogrammed
u = Unchanged from programmed state
bit 7-5
bit 4-1
Unimplemented: Read as ‘0’
WDTPS3:WDTPS0: Watchdog Timer Postscale Select bits
1111= 1:32,768
1110= 1:16,384
1101= 1:8,192
1100= 1:4,096
1011= 1:2,048
1010= 1:1,024
1001= 1:512
1000= 1:256
0111= 1:128
0110= 1:64
0101= 1:32
0100= 1:16
0011= 1:8
0010= 1:4
0001= 1:2
0000= 1:1
bit 0
WDTEN: Watchdog Timer Enable bit
1= WDT enabled
0= WDT disabled (control is placed on the SWDTEN bit)
DS39760D-page 196
© 2008 Microchip Technology Inc.
PIC18F2450/4450
REGISTER 18-5: CONFIG3H: CONFIGURATION REGISTER 3 HIGH (BYTE ADDRESS 300005h)
R/P-1
U-0
—
U-0
—
U-0
—
U-0
—
R/P-0
R/P-1
U-0
—
MCLRE
LPT1OSC
PBADEN
bit 7
bit 0
Legend:
R = Readable bit
P = Programmable bit
U = Unimplemented bit, read as ‘0’
-n = Value when device is unprogrammed
u = Unchanged from programmed state
bit 7
MCLRE: MCLR Pin Enable bit
1= MCLR pin enabled, RA5 input pin disabled
0= RA5 input pin enabled, MCLR pin disabled
bit 6-3
bit 2
Unimplemented: Read as ‘0’
LPT1OSC: Low-Power Timer1 Oscillator Enable bit
1= Timer1 configured for low-power operation
0= Timer1 configured for higher power operation
bit 1
bit 0
PBADEN: PORTB A/D Enable bit
(Affects ADCON1 Reset state. ADCON1 controls PORTB<4:0> pin configuration.)
1= PORTB<4:0> pins are configured as analog input channels on Reset
0= PORTB<4:0> pins are configured as digital I/O on Reset
Unimplemented: Read as ‘0’
© 2008 Microchip Technology Inc.
DS39760D-page 197
PIC18F2450/4450
REGISTER 18-6: CONFIG4L: CONFIGURATION REGISTER 4 LOW (BYTE ADDRESS 300006h)
R/P-1
R/P-0
R/P-0
ICPRT(1)
U-0
—
R/P-0
R/P-1
LVP
U-0
—
R/P-1
DEBUG
XINST
BBSIZ
STVREN
bit 7
bit 0
Legend:
R = Readable bit
P = Programmable bit
U = Unimplemented bit, read as ‘0’
-n = Value when device is unprogrammed
u = Unchanged from programmed state
bit 7
bit 6
bit 5
DEBUG: Background Debugger Enable bit
1= Background debugger disabled, RB6 and RB7 configured as general purpose I/O pins
0= Background debugger enabled, RB6 and RB7 are dedicated to In-Circuit Debug
XINST: Extended Instruction Set Enable bit
1= Instruction set extension and Indexed Addressing mode enabled
0= Instruction set extension and Indexed Addressing mode disabled (Legacy mode)
ICPRT: Dedicated In-Circuit Debug/Programming Port (ICPORT) Enable bit(1)
1= ICPORT enabled
0= ICPORT disabled
bit 4
bit 3
Unimplemented: Read as ‘0’
BBSIZ: Boot Block Size Select bit
1= 2 kW boot block size
0= 1 kW boot block size
bit 2
LVP: Single-Supply ICSP™ Enable bit
1= Single-Supply ICSP enabled
0= Single-Supply ICSP disabled
bit 1
bit 0
Unimplemented: Read as ‘0’
STVREN: Stack Full/Underflow Reset Enable bit
1= Stack full/underflow will cause Reset
0= Stack full/underflow will not cause Reset
Note 1: Available only on PIC18F4450 devices in 44-pin TQFP packages. Always leave this bit clear in all other
devices.
DS39760D-page 198
© 2008 Microchip Technology Inc.
PIC18F2450/4450
REGISTER 18-7: CONFIG5L: CONFIGURATION REGISTER 5 LOW (BYTE ADDRESS 300008h)
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
R/C-1
CP1
R/C-1
CP0
bit 7
bit 0
Legend:
R = Readable bit
C = Clearable bit
U = Unimplemented bit, read as ‘0’
-n = Value when device is unprogrammed
u = Unchanged from programmed state
bit 7-2
bit 1
Unimplemented: Read as ‘0’
CP1: Code Protection bit
1= Block 1 (002000-003FFFh) is not code-protected
0= Block 1 (002000-003FFFh) is code-protected
bit 0
CP0: Code Protection bit
1= Block 0 (000800-001FFFh) or (001000-001FFFh) is not code-protected
0= Block 0 (000800-001FFFh) or (001000-001FFFh) is code-protected
REGISTER 18-8: CONFIG5H: CONFIGURATION REGISTER 5 HIGH (BYTE ADDRESS 300009h)
U-0
—
R/C-1
CPB
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
bit 7
bit 0
Legend:
R = Readable bit
C = Clearable bit
U = Unimplemented bit, read as ‘0’
-n = Value when device is unprogrammed
u = Unchanged from programmed state
bit 7
bit 6
Unimplemented: Read as ‘0’
CPB: Boot Block Code Protection bit
1= Boot block (000000-0007FFh) or (000000-000FFFh) is not code-protected
0= Boot block (000000-0007FFh) or (000000-000FFFh) is code-protected
bit 5-0
Unimplemented: Read as ‘0’
© 2008 Microchip Technology Inc.
DS39760D-page 199
PIC18F2450/4450
REGISTER 18-9: CONFIG6L: CONFIGURATION REGISTER 6 LOW (BYTE ADDRESS 30000Ah)
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
R/C-1
WRT1
R/C-1
WRT0
bit 7
bit 0
Legend:
R = Readable bit
C = Clearable bit
U = Unimplemented bit, read as ‘0’
-n = Value when device is unprogrammed
u = Unchanged from programmed state
bit 7-2
bit 1
Unimplemented: Read as ‘0’
WRT1: Write Protection bit
1= Block 1 (002000-003FFFh) is not write-protected
0= Block 1 (002000-003FFFh) is write-protected
bit 0
WRT0: Write Protection bit
1= Block 0 (000800-001FFFh) or (001000-001FFFh) is not write-protected
0= Block 0 (000800-001FFFh) or (001000-001FFFh) is write-protected
REGISTER 18-10: CONFIG6H: CONFIGURATION REGISTER 6 HIGH (BYTE ADDRESS 30000Bh)
U-0
—
R/C-1
R-1
WRTC(1)
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
WRTB
bit 7
bit 0
Legend:
R = Readable bit
C = Clearable bit
U = Unimplemented bit, read as ‘0’
-n = Value when device is unprogrammed
u = Unchanged from programmed state
bit 7
bit 6
Unimplemented: Read as ‘0’
WRTB: Boot Block Write Protection bit
1= Boot block (000000-0007FFh) or (000000-000FFFh) is not write-protected
0= Boot block (000000-0007FFh) or (000000-000FFFh) is write-protected
bit 5
WRTC: Configuration Register Write Protection bit(1)
1= Configuration registers (300000-3000FFh) are not write-protected
0= Configuration registers (300000-3000FFh) are write-protected
bit 4-0
Unimplemented: Read as ‘0’
Note 1: This bit is read-only in normal execution mode; it can be written only in Program mode.
DS39760D-page 200
© 2008 Microchip Technology Inc.
PIC18F2450/4450
REGISTER 18-11: CONFIG7L: CONFIGURATION REGISTER 7 LOW (BYTE ADDRESS 30000Ch)
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
R/C-1
R/C-1
EBTR1
EBTR0
bit 7
bit 0
Legend:
R = Readable bit
C = Clearable bit
U = Unimplemented bit, read as ‘0’
-n = Value when device is unprogrammed
u = Unchanged from programmed state
bit 7-2
bit 1
Unimplemented: Read as ‘0’
EBTR1: Table Read Protection bit
1= Block 1 (002000-003FFFh) is not protected from table reads executed in other blocks
0= Block 1 (002000-003FFFh) is protected from table reads executed in other blocks
bit 0
EBTR0: Table Read Protection bit
1= Block 0 (000800-001FFFh) or (001000-001FFFh) is not protected from table reads executed in
other blocks
0= Block 0 (000800-001FFFh) or (001000-001FFFh) is protected from table reads executed in other
blocks
REGISTER 18-12: CONFIG7H: CONFIGURATION REGISTER 7 HIGH (BYTE ADDRESS 30000Dh)
U-0
—
R/C-1
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
EBTRB
bit 7
bit 0
Legend:
R = Readable bit
C = Clearable bit
U = Unimplemented bit, read as ‘0’
-n = Value when device is unprogrammed
u = Unchanged from programmed state
bit 7
bit 6
Unimplemented: Read as ‘0’
EBTRB: Boot Block Table Read Protection bit
1= Boot block (000000-0007FFh) or (000000-000FFFh) is not protected from table reads executed
in other blocks
0= Boot block (000000-0007FFh) or (000000-000FFFh) is protected from table reads executed in
other blocks
bit 5-0
Unimplemented: Read as ‘0’
© 2008 Microchip Technology Inc.
DS39760D-page 201
PIC18F2450/4450
REGISTER 18-13: DEVID1: DEVICE ID REGISTER 1 FOR PIC18F2450/4450 DEVICES
R
R
R
R
R
R
R
R
DEV2
DEV1
DEV0
REV4
REV3
REV2
REV1
REV0
bit 7
bit 0
Legend:
R = Read-only bit
P = Programmable bit
U = Unimplemented bit, read as ‘0’
-n = Value when device is unprogrammed
u = Unchanged from programmed state
bit 7-5
bit 4-0
DEV2:DEV0: Device ID bits
001= PIC18F2450
000= PIC18F4450
REV4:REV0: Revision ID bits
These bits are used to indicate the device revision.
REGISTER 18-14: DEVID2: DEVICE ID REGISTER 2 FOR PIC18F2450/4450 DEVICES
R
R
R
R
R
R
R
R
DEV10(1)
DEV9(1)
DEV8(1)
DEV7(1)
DEV6(1)
DEV5(1)
DEV4(1)
DEV3(1)
bit 7
bit 0
Legend:
R = Read-only bit
P = Programmable bit
U = Unimplemented bit, read as ‘0’
-n = Value when device is unprogrammed
u = Unchanged from programmed state
bit 7-0
DEV10:DEV3: Device ID bits(1)
These bits are used with the DEV2:DEV0 bits in the DEVID1 register to identify the part number.
0010 0100= PIC18F2450/4450 devices
Note 1: These values for DEV10:DEV3 may be shared with other devices. The specific device is always identified
by using the entire DEV10:DEV0 bit sequence.
DS39760D-page 202
© 2008 Microchip Technology Inc.
PIC18F2450/4450
18.2 Watchdog Timer (WDT)
Note 1: The CLRWDT and SLEEP instructions
clear the WDT and postscaler counts
when executed.
For PIC18F2450/4450 devices, the WDT is driven by
the INTRC source. When the WDT is enabled, the
clock source is also enabled. The nominal WDT period
is 4 ms and has the same stability as the INTRC
oscillator.
2: When a CLRWDT instruction is executed,
the postscaler count will be cleared.
18.2.1
CONTROL REGISTER
The 4 ms period of the WDT is multiplied by a 16-bit
postscaler. Any output of the WDT postscaler is
Register 18-15 shows the WDTCON register. This is a
readable and writable register which contains a control
bit that allows software to override the WDT enable
Configuration bit, but only if the Configuration bit has
disabled the WDT.
selected by
a multiplexer, controlled by bits in
Configuration Register 2H. Available periods range
from 4 ms to 131.072 seconds (2.18 minutes). The
WDT and postscaler are cleared when any of the
following events occur: a SLEEPor CLRWDTinstruction
is executed or a clock failure has occurred.
FIGURE 18-1:
WDT BLOCK DIAGRAM
Enable WDT
SWDTEN
WDTEN
INTRC Control
WDT Counter
Wake-up from
Power-Managed
Modes
÷128
INTRC Source
WDT
Reset
Reset
CLRWDT
All Device Resets
Programmable Postscaler
1:1 to 1:32,768
WDT
4
WDTPS<3:0>
SLEEP
© 2008 Microchip Technology Inc.
DS39760D-page 203
PIC18F2450/4450
REGISTER 18-15: WDTCON: WATCHDOG TIMER CONTROL REGISTER
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
R/W-0
SWDTEN(1)
bit 0
bit 7
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7-1
bit 0
Unimplemented: Read as ‘0’
SWDTEN: Software Controlled Watchdog Timer Enable bit(1)
1= Watchdog Timer is on
0= Watchdog Timer is off
Note 1: This bit has no effect if the Configuration bit, WDTEN, is enabled.
TABLE 18-2: SUMMARY OF WATCHDOG TIMER REGISTERS
Reset
Values
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
on Page:
RCON
WDTCON
IPEN
—
SBOREN(1)
—
—
—
RI
—
TO
—
PD
—
POR
—
BOR
50
SWDTEN
50
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the Watchdog Timer.
Note 1: The SBOREN bit is only available when BOREN<1:0> = 01; otherwise, the bit reads as ‘0’.
DS39760D-page 204
© 2008 Microchip Technology Inc.
PIC18F2450/4450
In all other power-managed modes, Two-Speed Start-up
is not used. The device will be clocked by the currently
selected clock source until the primary clock source
becomes available. The setting of the IESO bit is
ignored.
18.3 Two-Speed Start-up
The Two-Speed Start-up feature helps to minimize the
latency period, from oscillator start-up to code
execution, by allowing the microcontroller to use the
INTRC oscillator as a clock source until the primary
clock source is available. It is enabled by setting the
IESO Configuration bit.
18.3.1
SPECIAL CONSIDERATIONS FOR
USING TWO-SPEED START-UP
Two-Speed Start-up should be enabled only if the
primary oscillator mode is XT, HS, XTPLL or HSPLL
(Crystal-Based modes). Other sources do not require an
Oscillator Start-up Timer delay; for these, Two-Speed
Start-up should be disabled.
While using the INTRC oscillator in Two-Speed Start-up,
the device still obeys the normal command sequences
for entering power-managed modes, including serial
SLEEP instructions (refer to Section 3.1.4 “Multiple
Sleep Commands”). In practice, this means that user
code can change the SCS1:SCS0 bit settings or issue
SLEEPinstructions before the OST times out. This would
allow an application to briefly wake-up, perform routine
“housekeeping” tasks and return to Sleep before the
device starts to operate from the primary oscillator.
When enabled, Resets and wake-ups from Sleep mode
cause the device to configure itself to run from the
internal oscillator as the clock source, following the
time-out of the Power-up Timer after a Power-on Reset
is enabled. This allows almost immediate code
execution while the primary oscillator starts and the
OST is running. Once the OST times out, the device
automatically switches to PRI_RUN mode.
User code can also check if the primary clock source is
currently providing the device clocking by checking the
status of the OSTS bit (OSCCON<3>). If the bit is set,
the primary oscillator is providing the clock. Otherwise,
the internal oscillator is providing the clock during
wake-up from Reset or Sleep mode.
Because the OSCCON register is cleared on Reset
events, the INTRC clock is used directly at its base
frequency.
FIGURE 18-2:
TIMING TRANSITION FOR TWO-SPEED START-UP (INTRC TO HSPLL)
Q3
Q4
Q1
Q2 Q3 Q4 Q1 Q2 Q3
Q1
Q2
INTRC
OSC1
(1)
(1)
TPLL
TOST
1
2
n-1
n
PLL Clock
Output
Clock
Transition
CPU Clock
Peripheral
Clock
Program
Counter
PC
PC + 2
PC + 4
PC + 6
OSTS bit Set
Wake from Interrupt Event
Note 1: TOST = 1024 TOSC; TPLL = 2 ms (approx). These intervals are not shown to scale.
© 2008 Microchip Technology Inc.
DS39760D-page 205
PIC18F2450/4450
The FSCM will detect failures of the primary or
secondary clock sources only. If the internal oscillator
fails, no failure would be detected, nor would any action
be possible.
18.4 Fail-Safe Clock Monitor
The Fail-Safe Clock Monitor (FSCM) allows the
microcontroller to continue operation in the event of an
external oscillator failure by automatically switching the
device clock to the internal oscillator. The FSCM function
is enabled by setting the FCMEN Configuration bit.
18.4.1
FSCM AND THE WATCHDOG TIMER
Both the FSCM and the WDT are clocked by the
INTRC oscillator. Since the WDT operates with a
separate divider and counter, disabling the WDT has
no effect on the operation of the INTRC oscillator when
the FSCM is enabled.
When FSCM is enabled, the INTRC oscillator runs at all
times to monitor clocks to peripherals and provide a
backup clock in the event of a clock failure. Clock
monitoring (shown in Figure 18-3) is accomplished by
creating a sample clock signal, which is the INTRC output
divided by 64. This allows ample time between FSCM
sample clocks for a peripheral clock edge to occur. The
peripheral device clock and the sample clock are
presented as inputs to the Clock Monitor latch (CM). The
CM is set on the falling edge of the device clock source,
but cleared on the rising edge of the sample clock.
If the WDT is enabled with a small prescale value, a
decrease in clock speed allows a WDT time-out to
occur and a subsequent device Reset. For this reason,
Fail-Safe Clock Monitor events also reset the WDT and
postscaler, allowing it to start timing from when execu-
tion speed was changed and decreasing the likelihood
of an erroneous time-out.
FIGURE 18-3:
FSCM BLOCK DIAGRAM
18.4.2
EXITING FAIL-SAFE OPERATION
Clock Monitor
Latch (CM)
The fail-safe condition is terminated by either a device
Reset or by entering a power-managed mode. On
Reset, the controller starts the primary clock source
specified in Configuration Register 1H (with any start-
up delays that are required for the oscillator mode,
such as OST or PLL timer). The INTRC provides the
device clock until the primary clock source becomes
ready (similar to a Two-Speed Start-up). The clock
source is then switched to the primary clock (indicated
by the OSTS bit in the OSCCON register becoming
set). The Fail-Safe Clock Monitor then resumes
monitoring the peripheral clock.
(edge-triggered)
Peripheral
Clock
S
Q
INTRC
Source
Q
÷ 64
C
488 Hz
(2.048 ms)
(32 μs)
Clock
Failure
Detected
Clock failure is tested for on the falling edge of the
sample clock. If a sample clock falling edge occurs
while CM is still set, a clock failure has been detected
(Figure 18-4). This causes the following:
The primary clock source may never become ready
during start-up. In this case, operation is clocked by the
INTRC. The OSCCON register will remain in its Reset
state until a power-managed mode is entered.
• the FSCM generates an oscillator fail interrupt by
setting bit, OSCFIF (PIR2<7>);
• the device clock source is switched to the internal
oscillator (OSCCON is not updated to show the cur-
rent clock source – this is the fail-safe condition); and
• the WDT is reset.
DS39760D-page 206
© 2008 Microchip Technology Inc.
PIC18F2450/4450
FIGURE 18-4:
FSCM TIMING DIAGRAM
Sample Clock
Oscillator
Failure
Device
Clock
Output
CM Output
(Q)
Failure
Detected
OSCFIF
CM Test
CM Test
CM Test
Note:
The device clock is normally at a much higher frequency than the sample clock. The relative frequencies in this
example have been chosen for clarity.
considerably longer than the FCSM sample clock time,
a false clock failure may be detected. To prevent this,
the internal oscillator is automatically configured as the
device clock and functions until the primary clock is
stable (the OST and PLL timers have timed out). This
is identical to Two-Speed Start-up mode. Once the
primary clock is stable, the INTRC returns to its role as
the FSCM source.
18.4.3
FSCM INTERRUPTS IN
POWER-MANAGED MODES
By entering a power-managed mode, the clock multi-
plexer selects the clock source selected by the OSCCON
register. Fail-Safe Clock Monitoring of the power-
managed clock source resumes in the power-managed
mode.
If an oscillator failure occurs during power-managed
operation, the subsequent events depend on whether
or not the oscillator failure interrupt is enabled. If
enabled (OSCFIF = 1), code execution will be clocked
by the INTRC. An automatic transition back to the failed
clock source will not occur.
Note:
The same logic that prevents false oscilla-
tor failure interrupts on POR or wake from
Sleep will also prevent the detection of the
oscillator’s failure to start at all following
these events. This can be avoided by
monitoring the OSTS bit and using a
timing routine to determine if the oscillator
is taking too long to start. Even so, no
oscillator failure interrupt will be flagged.
If the interrupt is disabled, subsequent interrupts while
in Idle mode will cause the CPU to begin executing
instructions while being clocked by the INTRC source.
18.4.4
POR OR WAKE-UP FROM SLEEP
As noted in Section 18.3.1 “Special Considerations
for Using Two-Speed Start-up”, it is also possible to
select another clock configuration and enter an alternate
power-managed mode while waiting for the primary
clock to become stable. When the new power-managed
mode is selected, the primary clock is disabled.
The FSCM is designed to detect oscillator failure at any
point after the device has exited Power-on Reset
(POR) or low-power Sleep mode. When the primary
device clock is either EC or INTRC, monitoring can
begin immediately following these events.
For oscillator modes involving a crystal or resonator
(HS, HSPLL or XT), the situation is somewhat different.
Since the oscillator may require a start-up time
© 2008 Microchip Technology Inc.
DS39760D-page 207
PIC18F2450/4450
Each of the three blocks has three code protection bits
associated with them. They are:
18.5 Program Verification and
Code Protection
• Code-Protect bit (CPx)
The overall structure of the code protection on the
PIC18 Flash devices differs significantly from other
PIC® microcontrollers.
• Write-Protect bit (WRTx)
• External Block Table Read bit (EBTRx)
Figure 18-5 shows the program memory organization
for 24 and 32-Kbyte devices and the specific code
protection bit associated with each block. The actual
locations of the bits are summarized in Table 18-3.
The user program memory is divided into three blocks.
One of these is a boot block of 1 or 2 Kbytes. The
remainder of the memory is divided into two blocks on
binary boundaries.
FIGURE 18-5:
CODE-PROTECTED PROGRAM MEMORY FOR PIC18F2450/4450
MEMORY SIZE/DEVICE
Block Code Protection
Controlled By:
16 Kbytes
(PIC18F2450/4450)
Address
Range
000000h
0007FFh
000FFFh
Boot Block
Block 0
CPB, WRTB, EBTRB
CP0, WRT0, EBTR0
CP1, WRT1, EBTR1
001000h
001FFFh
002000h
Block 1
003FFFh
Unimplemented
Read ‘0’s
Unimplemented
Read ‘0’s
Unimplemented
Read ‘0’s
(Unimplemented Memory Space)
1FFFFFh
TABLE 18-3: SUMMARY OF CODE PROTECTION REGISTERS
File Name
300008h
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
CONFIG5L
CONFIG5H
CONFIG6L
CONFIG6H
CONFIG7L
CONFIG7H
—
—
—
—
—
—
—
CPB
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
CP1
—
CP0
—
300009h
30000Ah
30000Bh
30000Ch
30000Dh
—
WRT1
—
WRT0
—
WRTB
—
WRTC
—
EBTR1
—
EBTR0
—
EBTRB
—
Legend: Shaded cells are unimplemented.
DS39760D-page 208
© 2008 Microchip Technology Inc.
PIC18F2450/4450
A table read instruction that executes from a location
outside of that block is not allowed to read and will
result in reading ‘0’s. Figure 18-6 through Figure 18-8
illustrate table write and table read protection.
18.5.1
PROGRAM MEMORY
CODE PROTECTION
The program memory may be read to or written from
any location using the table read and table write
instructions. The device ID may be read with table
reads. The Configuration registers may be read and
written with the table read and table write instructions.
Note:
Code protection bits may only be written to
a ‘0’ from a ‘1’ state. It is not possible to
write a ‘1’ to a bit in the ‘0’ state. Code
protection bits are only set to ‘1’ by a full
Chip Erase or Block Erase function. The
full Chip Erase and Block Erase functions
can only be initiated via ICSP operation or
an external programmer.
In normal execution mode, the CPx bits have no direct
effect. CPx bits inhibit external reads and writes. A
block of user memory may be protected from table
writes if the WRTx Configuration bit is ‘0’. The EBTRx
bits control table reads. For a block of user memory
with the EBTRx bit set to ‘0’, a table read instruction
that executes from within that block is allowed to read.
FIGURE 18-6:
TABLE WRITE (WRTx) DISALLOWED
Register Values
Program Memory
Configuration Bit Settings
000000h
0007FFh
WRTB, EBTRB = 11
WRT0, EBTR0 = 01
WRT1, EBTR1 = 11
000FFFh
001000h
TBLPTR = 0008FFh
PC = 001FFEh
TBLWT*
001FFFh
002000h
003FFFh
WRT2, EBTR2 = 11
WRT3, EBTR3 = 11
Results: All table writes disabled to Blockn whenever WRTx = 0.
© 2008 Microchip Technology Inc.
DS39760D-page 209
PIC18F2450/4450
FIGURE 18-7:
EXTERNAL BLOCK TABLE READ (EBTRx) DISALLOWED
Register Values
Program Memory
Configuration Bit Settings
000000h
0007FFh
000FFFh
WRTB, EBTRB = 11
001000h
WRT0, EBTR0 = 10
WRT1, EBTR1 = 11
TBLPTR = 0008FFh
PC = 003FFEh
001FFFh
002000h
TBLRD*
003FFFh
Results: All table reads from external blocks to Blockn are disabled whenever EBTRx = 0.
TABLAT register returns a value of ‘0’.
FIGURE 18-8:
EXTERNAL BLOCK TABLE READ (EBTRx) ALLOWED
Register Values
Program Memory
Configuration Bit Settings
000000h
0007FFh
000FFFh
WRTB, EBTRB = 11
WRT0, EBTR0 = 10
001000h
TBLPTR = 0008FFh
PC = 001FFEh
TBLRD*
001FFFh
002000h
WRT1, EBTR1 = 11
003FFFh
Results: Table reads permitted within Blockn, even when EBTRBx = 0.
TABLAT register returns the value of the data at the location TBLPTR.
DS39760D-page 210
© 2008 Microchip Technology Inc.
PIC18F2450/4450
To use the In-Circuit Debugger function of the
microcontroller, the design must implement In-Circuit
Serial Programming connections to MCLR/VPP/RE3,
VDD, VSS, RB7 and RB6. This will interface to the
In-Circuit Debugger module available from Microchip
or one of the third party development tool companies.
18.5.2
CONFIGURATION REGISTER
PROTECTION
The Configuration registers can be write-protected.
The WRTC bit controls protection of the Configuration
registers. In normal execution mode, the WRTC bit is
readable only. WRTC can only be written via ICSP
operation or an external programmer.
18.9 Special ICPORT Features
(Designated Packages Only)
18.6 ID Locations
Under specific circumstances, the No Connect (NC)
pins of PIC18F4450 devices in 44-pin TQFP packages
can provide additional functionality. These features are
controlled by device Configuration bits and are
available only in this package type and pin count.
Eight memory locations (200000h-200007h) are
designated as ID locations, where the user can store
checksum or other code identification numbers. These
locations are both readable and writable during normal
execution through the TBLRD and TBLWT instructions
or during program/verify. The ID locations can be read
when the device is code-protected.
18.9.1
DEDICATED ICD/ICSP PORT
The 44-pin TQFP devices can use NC pins to provide an
alternate port for In-Circuit Debugging (ICD) and In-
Circuit Serial Programming (ICSP). These pins are
collectively known as the dedicated ICSP/ICD port, since
they are not shared with any other function of the device.
18.7
In-Circuit Serial Programming
PIC18F2450/4450 microcontrollers can be serially
programmed while in the end application circuit. This is
simply done with two lines for clock and data and three
other lines for power, ground and the programming
voltage. This allows customers to manufacture boards
with unprogrammed devices and then program the
microcontroller just before shipping the product. This
also allows the most recent firmware or a custom
firmware to be programmed.
When implemented, the dedicated port activates three
NC pins to provide an alternate device Reset, data and
clock ports. None of these ports overlap with standard
I/O pins, making the I/O pins available to the user’s
application.
The dedicated ICSP/ICD port is enabled by setting the
ICPRT Configuration bit. The port functions the same
way as the legacy ICSP/ICD port on RB6/RB7.
Table 18-5 identifies the functionally equivalent pins for
ICSP and ICD purposes.
18.8 In-Circuit Debugger
When the DEBUG Configuration bit is programmed to
a ‘0’, the In-Circuit Debugger functionality is enabled.
This function allows simple debugging functions when
used with MPLAB® IDE. When the microcontroller has
this feature enabled, some resources are not available
for general use. Table 18-4 shows which resources are
required by the background debugger.
TABLE 18-5: EQUIVALENT PINS FOR
LEGACY AND DEDICATED
ICD/ICSP™ PORTS
Pin Name
Pin
Pin Function
Legacy
Port
Dedicated
Port
Type
TABLE 18-4: DEBUGGER RESOURCES
I/O pins:
RB6, RB7
2 levels
MCLR/VPP/ NC/ICRST/
P
Device Reset and
Programming
Enable
RE3
ICVPP
Stack:
Program Memory:
Data Memory:
512 bytes
10 bytes
RB6/KBI2/
PGC
NC/ICCK/
ICPGC
I
Serial Clock
RB7/KBI3/
PGD
NC/ICDT/
ICPGD
I/O Serial Data
Legend: I = Input, O = Output, P = Power
© 2008 Microchip Technology Inc.
DS39760D-page 211
PIC18F2450/4450
Even when the dedicated port is enabled, the ICSP and
ICD functions remain available through the legacy port.
When VIHH is seen on the MCLR/VPP/RE3 pin, the
state of the ICRST/ICVPP pin is ignored.
Note 1: High-Voltage Programming is always
available, regardless of the state of the
LVP bit, by applying VIHH to the MCLR pin.
2: While in Low-Voltage ICSP Programming
mode, the RB5 pin can no longer be used
as a general purpose I/O pin and should
be held low during normal operation.
Note 1: The ICPRT Configuration bit can only be
programmed through the default ICSP
port.
2: The ICPRT Configuration bit must be
maintained clear for all 28-pin and 40-pin
devices; otherwise, unexpected operation
may occur.
3: When using Low-Voltage ICSP Program-
ming (LVP) and the pull-ups on PORTB
are enabled, bit 5 in the TRISB register
must be cleared to disable the pull-up on
RB5 and ensure the proper operation of
the device.
18.9.2
28-PIN EMULATION
PIC18F4450 devices in 44-pin TQFP packages also
have the ability to change their configuration under
external control for debugging purposes. This allows
the device to behave as if it were a PIC18F2450/4450
28-pin device.
4: If the device Master Clear is disabled,
verify that either of the following is done to
ensure proper entry into ICSP mode:
a) Disable Low-Voltage Programming
(CONFIG4L<2> = 0); or
This 28-pin Configuration mode is controlled through a
single pin, NC/ICPORTS. Connecting this pin to VSS
forces the device to function as a 28-pin device.
Features normally associated with the 40/44-pin
devices are disabled, along with their corresponding
control registers and bits. On the other hand,
connecting the pin to VDD forces the device to function
in its default configuration.
b) Make certain that RB5/KBI1/PGM
is held low during entry into ICSP.
If Single-Supply ICSP Programming mode will not be
used, the LVP bit can be cleared. RB5/KBI1/PGM then
becomes available as the digital I/O pin, RB5. The LVP
bit may be set or cleared only when using standard
high-voltage programming (VIHH applied to the MCLR/
VPP/RE3 pin). Once LVP has been disabled, only the
standard high-voltage programming is available and
must be used to program the device.
The configuration option is only available when
background debugging and the dedicated ICD/ICSP
port are both enabled (DEBUG Configuration bit is
clear and ICPRT Configuration bit is set). When
disabled, NC/ICPORTS is a No Connect pin.
Memory that is not code-protected can be erased using
either a Block Erase, or erased row by row, then written
at any specified VDD. If code-protected memory is to be
erased, a Block Erase is required. If a Block Erase is to
be performed when using Low-Voltage Programming,
the device must be supplied with VDD of 4.5V to 5.5V.
18.10 Single-Supply ICSP Programming
The LVP Configuration bit enables Single-Supply
ICSP Programming (formerly known as Low-Voltage
ICSP Programming or LVP). When Single-Supply
Programming is enabled, the microcontroller can be
programmed without requiring high voltage being
applied to the MCLR/VPP/RE3 pin, but the RB5/KBI1/
PGM pin is then dedicated to controlling Program
mode entry and is not available as a general purpose
I/O pin.
While programming using Single-Supply Program-
ming, VDD is applied to the MCLR/VPP/RE3 pin as in
normal execution mode. To enter Programming mode,
VDD is applied to the PGM pin.
DS39760D-page 212
© 2008 Microchip Technology Inc.
PIC18F2450/4450
The literal instructions may use some of the following
operands:
19.0 INSTRUCTION SET SUMMARY
PIC18F2450/4450 devices incorporate the standard
set of 75 PIC18 core instructions, as well as an
extended set of eight new instructions for the
optimization of code that is recursive or that utilizes a
software stack. The extended set is discussed later in
this section.
• A literal value to be loaded into a file register
(specified by ‘k’)
• The desired FSR register to load the literal value
into (specified by ‘f’)
• No operand required
(specified by ‘—’)
19.1 Standard Instruction Set
The control instructions may use some of the following
operands:
The standard PIC18 instruction set adds many
enhancements to the previous PIC MCU instruction
sets, while maintaining an easy migration from these
PIC MCU instruction sets. Most instructions are a
single program memory word (16 bits) but there are
four instructions that require two program memory
locations.
• A program memory address (specified by ‘n’)
• The mode of the CALLor RETURNinstructions
(specified by ‘s’)
• The mode of the table read and table write
instructions (specified by ‘m’)
• No operand required
(specified by ‘—’)
Each single-word instruction is a 16-bit word divided
into an opcode, which specifies the instruction type and
one or more operands, which further specify the
operation of the instruction.
All instructions are a single word, except for four
double-word instructions. These instructions were
made double-word to contain the required information
in 32 bits. In the second word, the 4 MSbs are ‘1’s. If
this second word is executed as an instruction (by
itself), it will execute as a NOP.
The instruction set is highly orthogonal and is grouped
into four basic categories:
• Byte-oriented operations
• Bit-oriented operations
• Literal operations
All single-word instructions are executed in a single
instruction cycle, unless a conditional test is true or the
program counter is changed as a result of the instruc-
tion. In these cases, the execution takes two instruction
cycles with the additional instruction cycle(s) executed
as a NOP.
• Control operations
The PIC18 instruction set summary in Table 19-2 lists
byte-oriented, bit-oriented, literal and control
operations. Table 19-1 shows the opcode field
descriptions.
The double-word instructions execute in two instruction
cycles.
Most byte-oriented instructions have three operands:
One instruction cycle consists of four oscillator periods.
Thus, for an oscillator frequency of 4 MHz, the normal
instruction execution time is 1 μs. If a conditional test is
true, or the program counter is changed as a result of
an instruction, the instruction execution time is 2 μs.
Two-word branch instructions (if true) would take 3 μs.
1. The file register (specified by ‘f’)
2. The destination of the result (specified by ‘d’)
3. The accessed memory (specified by ‘a’)
The file register designator, ‘f’, specifies which file
register is to be used by the instruction. The destination
designator, ‘d’, specifies where the result of the
operation is to be placed. If ‘d’ is ‘0’, the result is placed
in the WREG register. If ‘d’ is ‘1’, the result is placed in
the file register specified in the instruction.
Figure 19-1 shows the general formats that the
instructions can have. All examples use the convention
‘nnh’ to represent a hexadecimal number.
The instruction set summary, shown in Table 19-2, lists
the standard instructions recognized by the Microchip
MPASMTM Assembler.
All bit-oriented instructions have three operands:
1. The file register (specified by ‘f’)
Section 19.1.1 “Standard Instruction Set” provides
a description of each instruction.
2. The bit in the file register (specified by ‘b’)
3. The accessed memory (specified by ‘a’)
The bit field designator ‘b’ selects the number of the bit
affected by the operation, while the file register
designator, ‘f’, represents the number of the file in
which the bit is located.
© 2008 Microchip Technology Inc.
DS39760D-page 213
PIC18F2450/4450
TABLE 19-1: OPCODE FIELD DESCRIPTIONS
Field
Description
a
RAM access bit
a = 0: RAM location in Access RAM (BSR register is ignored)
a = 1: RAM bank is specified by BSR register
bbb
Bit address within an 8-bit file register (0 to 7).
BSR
Bank Select Register. Used to select the current RAM bank.
ALU Status bits: Carry, Digit Carry, Zero, Overflow, Negative.
C, DC, Z, OV, N
d
Destination select bit
d = 0: store result in WREG
d = 1: store result in file register f
dest
f
Destination: either the WREG register or the specified register file location.
8-bit register file address (00h to FFh) or 2-bit FSR designator (0h to 3h).
12-bit register file address (000h to FFFh). This is the source address.
12-bit register file address (000h to FFFh). This is the destination address.
Global Interrupt Enable bit.
f
f
s
d
GIE
k
Literal field, constant data or label (may be either an 8-bit, 12-bit or a 20-bit value).
Label name.
label
mm
The mode of the TBLPTR register for the table read and table write instructions.
Only used with table read and table write instructions:
*
No change to register (such as TBLPTR with table reads and writes)
Post-Increment register (such as TBLPTR with table reads and writes)
Post-Decrement register (such as TBLPTR with table reads and writes)
Pre-Increment register (such as TBLPTR with table reads and writes)
*+
*-
+*
n
The relative address (2’s complement number) for relative branch instructions or the direct address for
Call/Branch and Return instructions.
PC
Program Counter.
PCL
Program Counter Low Byte.
Program Counter High Byte.
Program Counter High Byte Latch.
Program Counter Upper Byte Latch.
Power-Down bit.
PCH
PCLATH
PCLATU
PD
PRODH
PRODL
s
Product of Multiply High Byte.
Product of Multiply Low Byte.
Fast Call/Return mode select bit
s = 0: do not update into/from shadow registers
s = 1: certain registers loaded into/from shadow registers (Fast mode)
TBLPTR
TABLAT
TO
21-bit Table Pointer (points to a program memory location).
8-bit Table Latch.
Time-out bit.
TOS
u
Top-of-Stack.
Unused or unchanged.
Watchdog Timer.
WDT
WREG
x
Working register (accumulator).
Don’t care (‘0’ or ‘1’). The assembler will generate code with x = 0. It is the recommended form of use for
compatibility with all Microchip software tools.
z
z
{
7-bit offset value for indirect addressing of register files (source).
7-bit offset value for indirect addressing of register files (destination).
Optional argument.
s
d
}
[text]
(text)
[expr]<n>
→
Indicates an indexed address.
The contents of text.
Specifies bit nof the register indicated by the pointer, expr.
Assigned to.
< >
Register bit field.
∈
In the set of.
italics
User-defined term (font is Courier New).
DS39760D-page 214
© 2008 Microchip Technology Inc.
PIC18F2450/4450
FIGURE 19-1:
GENERAL FORMAT FOR INSTRUCTIONS
Byte-oriented file register operations
Example Instruction
15
10
OPCODE
9
8
7
0
ADDWF MYREG, W, B
d
a
f (FILE #)
d = 0for result destination to be WREG register
d = 1for result destination to be file register (f)
a = 0to force Access Bank
a = 1for BSR to select bank
f = 8-bit file register address
Byte to Byte move operations (2-word)
15
12 11
0
0
MOVFF MYREG1, MYREG2
OPCODE
f (Source FILE #)
15
12 11
1111
f (Destination FILE #)
f = 12-bit file register address
Bit-oriented file register operations
15 12 11 9 8
OPCODE b (BIT #)
7
0
BSF MYREG, bit, B
a
f (FILE #)
b = 3-bit position of bit in file register (f)
a = 0to force Access Bank
a = 1for BSR to select bank
f = 8-bit file register address
Literal operations
15
8
7
0
MOVLW 7Fh
OPCODE
k = 8-bit immediate value
k (literal)
Control operations
CALL, GOTO and Branch operations
15
8 7
0
GOTO Label
OPCODE
12 11
n<7:0> (literal)
15
0
1111
n<19:8> (literal)
n = 20-bit immediate value
15
15
8
7
0
CALL MYFUNC
OPCODE
12 11
S
n<7:0> (literal)
0
1111
S = Fast bit
n<19:8> (literal)
15
15
11 10
0
0
BRA MYFUNC
BC MYFUNC
OPCODE
n<10:0> (literal)
8 7
OPCODE
n<7:0> (literal)
© 2008 Microchip Technology Inc.
DS39760D-page 215
PIC18F2450/4450
TABLE 19-2: PIC18FXXXX INSTRUCTION SET
16-Bit Instruction Word
MSb LSb
Mnemonic,
Operands
Status
Affected
Description
Cycles
Notes
BYTE-ORIENTED OPERATIONS
ADDWF f, d, a Add WREG and f
ADDWFC f, d, a Add WREG and Carry bit to f
1
1
1
1
1
0010 01da ffff ffff C, DC, Z, OV, N 1, 2
0010 00da ffff ffff C, DC, Z, OV, N 1, 2
ANDWF
CLRF
COMF
f, d, a AND WREG with f
f, a Clear f
f, d, a Complement f
0001 01da ffff ffff Z, N
0110 101a ffff ffff
0001 11da ffff ffff Z, N
1,2
2
1, 2
4
Z
CPFSEQ f, a
Compare f with WREG, Skip = 1 (2 or 3) 0110 001a ffff ffff None
Compare f with WREG, Skip > 1 (2 or 3) 0110 010a ffff ffff None
Compare f with WREG, Skip < 1 (2 or 3) 0110 000a ffff ffff None
CPFSGT
CPFSLT
DECF
f, a
f, a
4
1, 2
f, d, a Decrement f
f, d, a Decrement f, Skip if 0
f, d, a Decrement f, Skip if Not 0
f, d, a Increment f
1
0000 01da ffff ffff C, DC, Z, OV, N 1, 2, 3, 4
DECFSZ
DCFSNZ
INCF
1 (2 or 3) 0010 11da ffff ffff None
1 (2 or 3) 0100 11da ffff ffff None
1
1, 2, 3, 4
1, 2
0010 10da ffff ffff C, DC, Z, OV, N 1, 2, 3, 4
INCFSZ
INFSNZ
IORWF
MOVF
f, d, a Increment f, Skip if 0
f, d, a Increment f, Skip if Not 0
f, d, a Inclusive OR WREG with f
f, d, a Move f
1 (2 or 3) 0011 11da ffff ffff None
1 (2 or 3) 0100 10da ffff ffff None
4
1, 2
1, 2
1
1
1
2
0001 00da ffff ffff Z, N
0101 00da ffff ffff Z, N
1100 ffff ffff ffff None
1111 ffff ffff ffff
MOVFF
f , f
Move f (source) to 1st word
s
d
s
f (destination) 2nd word
d
MOVWF
MULWF
NEGF
RLCF
RLNCF
RRCF
f, a
f, a
f, a
Move WREG to f
Multiply WREG with f
Negate f
1
1
1
1
1
1
1
1
1
0110 111a ffff ffff None
0000 001a ffff ffff None
0110 110a ffff ffff C, DC, Z, OV, N
0011 01da ffff ffff C, Z, N
0100 01da ffff ffff Z, N
0011 00da ffff ffff C, Z, N
0100 00da ffff ffff Z, N
0110 100a ffff ffff None
0101 01da ffff ffff C, DC, Z, OV, N
1, 2
1, 2
f, d, a Rotate Left f through Carry
f, d, a Rotate Left f (No Carry)
f, d, a Rotate Right f through Carry
f, d, a Rotate Right f (No Carry)
RRNCF
SETF
f, a
Set f
1, 2
SUBFWB f, d, a Subtract f from WREG with
Borrow
SUBWF
f, d, a Subtract WREG from f
1
1
0101 11da ffff ffff C, DC, Z, OV, N 1, 2
0101 10da ffff ffff C, DC, Z, OV, N
SUBWFB f, d, a Subtract WREG from f with
Borrow
SWAPF
TSTFSZ
XORWF
f, d, a Swap Nibbles in f
f, a Test f, Skip if 0
f, d, a Exclusive OR WREG with f
1
0011 10da ffff ffff None
4
1, 2
1 (2 or 3) 0110 011a ffff ffff None
0001 10da ffff ffff Z, N
1
Note 1: When a PORT register is modified as a function of itself (e.g., MOVF PORTB, 1, 0), the value used will be that
value present on the pins themselves. For example, if the data latch is ‘1’ for a pin configured as an input and is
driven low by an external device, the data will be written back with a ‘0’.
2: If this instruction is executed on the TMR0 register (and where applicable, ‘d’ = 1), the prescaler will be cleared if
assigned.
3: If the Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The
second cycle is executed as a NOP.
4: Some instructions are two-word instructions. The second word of these instructions will be executed as a NOP
unless the first word of the instruction retrieves the information embedded in these 16 bits. This ensures that all
program memory locations have a valid instruction.
DS39760D-page 216
© 2008 Microchip Technology Inc.
PIC18F2450/4450
TABLE 19-2: PIC18FXXXX INSTRUCTION SET (CONTINUED)
16-Bit Instruction Word
Mnemonic,
Operands
Status
Affected
Description
Cycles
Notes
MSb LSb
BIT-ORIENTED OPERATIONS
BCF
BSF
BTFSC
BTFSS
BTG
f, b, a Bit Clear f
f, b, a Bit Set f
f, b, a Bit Test f, Skip if Clear
f, b, a Bit Test f, Skip if Set
f, d, a Bit Toggle f
1
1
1001 bbba ffff ffff None
1000 bbba ffff ffff None
1, 2
1, 2
3, 4
3, 4
1, 2
1 (2 or 3) 1011 bbba ffff ffff None
1 (2 or 3) 1010 bbba ffff ffff None
1
0111 bbba ffff ffff None
CONTROL OPERATIONS
BC
BN
n
n
n
n
n
n
n
n
Branch if Carry
1 (2)
1 (2)
1 (2)
1 (2)
1 (2)
1 (2)
1 (2)
2
1110 0010 nnnn nnnn None
1110 0110 nnnn nnnn None
1110 0011 nnnn nnnn None
1110 0111 nnnn nnnn None
1110 0101 nnnn nnnn None
1110 0001 nnnn nnnn None
1110 0100 nnnn nnnn None
1101 0nnn nnnn nnnn None
1110 0000 nnnn nnnn None
1110 110s kkkk kkkk None
1111 kkkk kkkk kkkk
Branch if Negative
Branch if Not Carry
Branch if Not Negative
Branch if Not Overflow
Branch if Not Zero
Branch if Overflow
Branch Unconditionally
Branch if Zero
BNC
BNN
BNOV
BNZ
BOV
BRA
BZ
n
n, s
1 (2)
2
CALL
Call Subroutine 1st word
2nd word
CLRWDT
DAW
GOTO
—
—
n
Clear Watchdog Timer
Decimal Adjust Wreg
Go To Address 1st word
2nd word
1
1
2
0000 0000 0000 0100 TO, PD
0000 0000 0000 0111
C
1110 1111 kkkk kkkk None
1111 kkkk kkkk kkkk
NOP
NOP
POP
PUSH
RCALL
RESET
RETFIE
—
—
—
—
n
No Operation
No Operation
Pop Top of Return Stack (TOS)
Push Top of Return Stack (TOS) 1
Relative Call
Software Device Reset
Return from Interrupt Enable
1
1
1
0000 0000 0000 0000 None
1111 xxxx xxxx xxxx None
0000 0000 0000 0110 None
0000 0000 0000 0101 None
1101 1nnn nnnn nnnn None
0000 0000 1111 1111 All
0000 0000 0001 000s GIE/GIEH,
PEIE/GIEL
4
2
1
2
s
RETLW
RETURN
SLEEP
k
s
—
Return with Literal in WREG
Return from Subroutine
Go into Standby mode
2
2
1
0000 1100 kkkk kkkk None
0000 0000 0001 001s None
0000 0000 0000 0011 TO, PD
Note 1: When a PORT register is modified as a function of itself (e.g., MOVF PORTB, 1, 0), the value used will be that
value present on the pins themselves. For example, if the data latch is ‘1’ for a pin configured as an input and is
driven low by an external device, the data will be written back with a ‘0’.
2: If this instruction is executed on the TMR0 register (and where applicable, ‘d’ = 1), the prescaler will be cleared if
assigned.
3: If the Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The
second cycle is executed as a NOP.
4: Some instructions are two-word instructions. The second word of these instructions will be executed as a NOP
unless the first word of the instruction retrieves the information embedded in these 16 bits. This ensures that all
program memory locations have a valid instruction.
© 2008 Microchip Technology Inc.
DS39760D-page 217
PIC18F2450/4450
TABLE 19-2: PIC18FXXXX INSTRUCTION SET (CONTINUED)
16-Bit Instruction Word
Mnemonic,
Operands
Status
Affected
Description
Cycles
Notes
MSb
LSb
LITERAL OPERATIONS
ADDLW
ANDLW
IORLW
LFSR
k
k
k
f, k
Add Literal and WREG
AND Literal with WREG
Inclusive OR Literal with WREG 1
Move Literal (12-bit) 2nd word
to FSR(f) 1st word
Move Literal to BSR<3:0>
Move Literal to WREG
Multiply Literal with WREG
Return with Literal in WREG
Subtract WREG from Literal
Exclusive OR Literal with
WREG
1
1
0000 1111 kkkk
0000 1011 kkkk
0000 1001 kkkk
1110 1110 00ff
1111 0000 kkkk
0000 0001 0000
0000 1110 kkkk
0000 1101 kkkk
0000 1100 kkkk
0000 1000 kkkk
0000 1010 kkkk
kkkk C, DC, Z, OV, N
kkkk Z, N
kkkk Z, N
kkkk None
kkkk
kkkk None
kkkk None
kkkk None
kkkk None
kkkk C, DC, Z, OV, N
kkkk Z, N
2
MOVLB
MOVLW
MULLW
RETLW
SUBLW
XORLW
k
k
k
k
k
k
1
1
1
2
1
1
DATA MEMORY ↔ PROGRAM MEMORY OPERATIONS
TBLRD*
Table Read
2
0000 0000 0000
0000 0000 0000
0000 0000 0000
0000 0000 0000
0000 0000 0000
0000 0000 0000
0000 0000 0000
0000 0000 0000
1000 None
1001 None
1010 None
1011 None
1100 None
1101 None
1110 None
1111 None
TBLRD*+
TBLRD*-
TBLRD+*
TBLWT*
TBLWT*+
TBLWT*-
TBLWT+*
Table Read with Post-Increment
Table Read with Post-Decrement
Table Read with Pre-Increment
Table Write
Table Write with Post-Increment
Table Write with Post-Decrement
Table Write with Pre-Increment
2
Note 1: When a PORT register is modified as a function of itself (e.g., MOVF PORTB, 1, 0), the value used will be that
value present on the pins themselves. For example, if the data latch is ‘1’ for a pin configured as an input and is
driven low by an external device, the data will be written back with a ‘0’.
2: If this instruction is executed on the TMR0 register (and where applicable, ‘d’ = 1), the prescaler will be cleared if
assigned.
3: If the Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The
second cycle is executed as a NOP.
4: Some instructions are two-word instructions. The second word of these instructions will be executed as a NOP
unless the first word of the instruction retrieves the information embedded in these 16 bits. This ensures that all
program memory locations have a valid instruction.
DS39760D-page 218
© 2008 Microchip Technology Inc.
PIC18F2450/4450
19.1.1
STANDARD INSTRUCTION SET
ADDLW
ADD Literal to W
ADDWF
ADD W to f
Syntax:
ADDLW
k
Syntax:
ADDWF
f {,d {,a}}
Operands:
Operation:
Status Affected:
Encoding:
Description:
0 ≤ k ≤ 255
Operands:
0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
(W) + k → W
N, OV, C, DC, Z
Operation:
(W) + (f) → dest
0000
1111
kkkk
kkkk
Status Affected:
Encoding:
N, OV, C, DC, Z
The contents of W are added to the
8-bit literal ‘k’ and the result is placed in
W.
0010
01da
ffff
ffff
Description:
Add W to register ‘f’. If ‘d’ is ‘0’, the
result is stored in W. If ‘d’ is ‘1’, the
result is stored back in register ‘f’
(default).
Words:
Cycles:
1
1
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank (default).
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f ≤ 95 (5Fh). See
Section 19.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
literal ‘k’
Process
Data
Write to W
Example:
ADDLW
15h
Before Instruction
10h
After Instruction
25h
W
=
Words:
Cycles:
1
1
W
=
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
register ‘f’
Process
Data
Write to
destination
Example:
ADDWF
REG, 0, 0
Before Instruction
W
=
17h
REG
=
0C2h
After Instruction
W
REG
=
=
0D9h
0C2h
Note:
All PIC18 instructions may take an optional label argument, preceding the instruction mnemonic, for use in
symbolic addressing. If a label is used, the instruction format then becomes: {label} instruction argument(s).
© 2008 Microchip Technology Inc.
DS39760D-page 219
PIC18F2450/4450
ADDWFC
ADD W and Carry bit to f
ANDLW
AND Literal with W
Syntax:
ADDWFC
f {,d {,a}}
Syntax:
ANDLW
k
Operands:
0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
Operands:
Operation:
Status Affected:
Encoding:
Description:
0 ≤ k ≤ 255
(W) .AND. k → W
N, Z
Operation:
(W) + (f) + (C) → dest
0000
1011
kkkk
kkkk
Status Affected:
Encoding:
N, OV, C, DC, Z
The contents of W are ANDed with the
8-bit literal ‘k’. The result is placed in W.
0010
00da
ffff
ffff
Description:
Add W, the Carry flag and data memory
location ‘f’. If ‘d’ is ‘0’, the result is
placed in W. If ‘d’ is ‘1’, the result is
placed in data memory location ‘f’.
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank (default).
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f ≤ 95 (5Fh). See
Section 19.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
Words:
Cycles:
1
1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read literal
‘k’
Process
Data
Write to W
Example:
ANDLW
05Fh
Before Instruction
W
=
A3h
03h
After Instruction
W
=
Words:
Cycles:
1
1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
register ‘f’
Process
Data
Write to
destination
Example:
ADDWFC
REG, 0, 1
Before Instruction
Carry bit =
1
02h
4Dh
REG
W
=
=
After Instruction
Carry bit =
0
02h
50h
REG
W
=
=
DS39760D-page 220
© 2008 Microchip Technology Inc.
PIC18F2450/4450
ANDWF
AND W with f
BC
Branch if Carry
Syntax:
ANDWF
f {,d {,a}}
Syntax:
BC
n
Operands:
0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
Operands:
Operation:
-128 ≤ n ≤ 127
if Carry bit is ‘1’,
(PC) + 2 + 2n → PC
Operation:
(W) .AND. (f) → dest
Status Affected:
Encoding:
None
Status Affected:
Encoding:
N, Z
1110
0010
nnnn
nnnn
0001
01da
ffff
ffff
Description:
If the Carry bit is ‘1’, then the program
will branch.
Description:
The contents of W are ANDed with
register ‘f’. If ‘d’ is ‘0’, the result is stored
in W. If ‘d’ is ‘1’, the result is stored back
in register ‘f’ (default).
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank (default).
The 2’s complement number ‘2n’ is
added to the PC. Since the PC will have
incremented to fetch the next
instruction, the new address will be
PC + 2 + 2n. This instruction is then a
two-cycle instruction.
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f ≤ 95 (5Fh). See
Section 19.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
Words:
Cycles:
1
1(2)
Q Cycle Activity:
If Jump:
Q1
Q2
Q3
Q4
Decode
Read literal
‘n’
Process
Data
Write to PC
Words:
Cycles:
1
1
No
No
No
No
operation
operation
operation
operation
Q Cycle Activity:
Q1
If No Jump:
Q1
Q2
Q3
Q4
Q2
Q3
Q4
Decode
Read
register ‘f’
Process
Data
Write to
destination
Decode
Read literal
‘n’
Process
Data
No
operation
Example:
ANDWF
REG, 0, 0
Example:
HERE
BC
5
Before Instruction
Before Instruction
W
REG
=
=
17h
C2h
PC
=
address (HERE)
After Instruction
After Instruction
W
REG
=
=
02h
C2h
If Carry
PC
If Carry
PC
=
=
=
=
1;
address (HERE + 12)
0;
address (HERE + 2)
© 2008 Microchip Technology Inc.
DS39760D-page 221
PIC18F2450/4450
BCF
Bit Clear f
BN
Branch if Negative
BN
Syntax:
BCF f, b {,a}
Syntax:
n
Operands:
0 ≤ f ≤ 255
0 ≤ b ≤ 7
a ∈ [0,1]
Operands:
Operation:
-128 ≤ n ≤ 127
if Negative bit is ‘1’,
(PC) + 2 + 2n → PC
Operation:
0 → f<b>
Status Affected:
Encoding:
None
Status Affected:
Encoding:
None
1110
0110
nnnn
nnnn
1001
bbba
ffff
ffff
Description:
If the Negative bit is ‘1’, then the
Description:
Bit ‘b’ in register ‘f’ is cleared.
program will branch.
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank (default).
The 2’s complement number ‘2n’ is
added to the PC. Since the PC will have
incremented to fetch the next
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f ≤ 95 (5Fh). See
Section 19.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
instruction, the new address will be
PC + 2 + 2n. This instruction is then a
two-cycle instruction.
Words:
Cycles:
1
1(2)
Q Cycle Activity:
If Jump:
Words:
Cycles:
1
1
Q1
Q2
Q3
Q4
Decode
Read literal
‘n’
Process
Data
Write to PC
Q Cycle Activity:
Q1
Q2
Q3
Q4
No
No
No
No
Decode
Read
register ‘f’
Process
Data
Write
register ‘f’
operation
operation
operation
operation
If No Jump:
Q1
Q2
Q3
Q4
Example:
BCF
FLAG_REG, 7, 0
C7h
47h
Decode
Read literal
‘n’
Process
Data
No
operation
Before Instruction
FLAG_REG =
After Instruction
FLAG_REG =
Example:
HERE
BN Jump
Before Instruction
PC
=
address (HERE)
After Instruction
If Negative
PC
If Negative
PC
=
=
=
=
1;
address (Jump)
0;
address (HERE + 2)
DS39760D-page 222
© 2008 Microchip Technology Inc.
PIC18F2450/4450
BNC
Branch if Not Carry
BNC
BNN
Branch if Not Negative
Syntax:
n
Syntax:
BNN
n
Operands:
Operation:
-128 ≤ n ≤ 127
Operands:
Operation:
-128 ≤ n ≤ 127
if Carry bit is ‘0’,
(PC) + 2 + 2n → PC
if Negative bit is ‘0’,
(PC) + 2 + 2n → PC
Status Affected:
Encoding:
None
Status Affected:
Encoding:
None
1110
0011
nnnn
nnnn
1110
0111
nnnn
nnnn
Description:
If the Carry bit is ‘0’, then the program
will branch.
Description:
If the Negative bit is ‘0’, then the
program will branch.
The 2’s complement number ‘2n’ is
added to the PC. Since the PC will have
incremented to fetch the next
instruction, the new address will be
PC + 2 + 2n. This instruction is then a
two-cycle instruction.
The 2’s complement number ‘2n’ is
added to the PC. Since the PC will have
incremented to fetch the next
instruction, the new address will be
PC + 2 + 2n. This instruction is then a
two-cycle instruction.
Words:
Cycles:
1
Words:
Cycles:
1
1(2)
1(2)
Q Cycle Activity:
If Jump:
Q Cycle Activity:
If Jump:
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Decode
Read literal
‘n’
Process
Data
Write to PC
Decode
Read literal
‘n’
Process
Data
Write to PC
No
No
No
No
No
No
No
No
operation
operation
operation
operation
operation
operation
operation
operation
If No Jump:
Q1
If No Jump:
Q1
Q2
Q3
Q4
Q2
Q3
Q4
Decode
Read literal
‘n’
Process
Data
No
operation
Decode
Read literal
‘n’
Process
Data
No
operation
Example:
HERE
BNC Jump
Example:
HERE
BNN Jump
Before Instruction
Before Instruction
PC
=
address (HERE)
PC
=
address (HERE)
After Instruction
After Instruction
If Carry
PC
If Carry
PC
=
=
=
=
0;
If Negative
PC
If Negative
PC
=
=
=
=
0;
address (Jump)
address (Jump)
1;
1;
address (HERE + 2)
address (HERE + 2)
© 2008 Microchip Technology Inc.
DS39760D-page 223
PIC18F2450/4450
BNOV
Branch if Not Overflow
BNOV
BNZ
Branch if Not Zero
BNZ
Syntax:
n
Syntax:
n
Operands:
Operation:
-128 ≤ n ≤ 127
Operands:
Operation:
-128 ≤ n ≤ 127
if Overflow bit is ‘0’,
(PC) + 2 + 2n → PC
if Zero bit is ‘0’,
(PC) + 2 + 2n → PC
Status Affected:
Encoding:
None
Status Affected:
Encoding:
None
1110
0101
nnnn
nnnn
1110
0001
nnnn
nnnn
Description:
If the Overflow bit is ‘0’, then the
program will branch.
Description:
If the Zero bit is ‘0’, then the program
will branch.
The 2’s complement number ‘2n’ is
added to the PC. Since the PC will have
incremented to fetch the next
instruction, the new address will be
PC + 2 + 2n. This instruction is then a
two-cycle instruction.
The 2’s complement number ‘2n’ is
added to the PC. Since the PC will have
incremented to fetch the next
instruction, the new address will be
PC + 2 + 2n. This instruction is then a
two-cycle instruction.
Words:
Cycles:
1
Words:
Cycles:
1
1(2)
1(2)
Q Cycle Activity:
If Jump:
Q Cycle Activity:
If Jump:
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Decode
Read literal
‘n’
Process
Data
Write to PC
Decode
Read literal
‘n’
Process
Data
Write to PC
No
No
No
No
No
No
No
No
operation
operation
operation
operation
operation
operation
operation
operation
If No Jump:
Q1
If No Jump:
Q1
Q2
Q3
Q4
Q2
Q3
Q4
Decode
Read literal
‘n’
Process
Data
No
operation
Decode
Read literal
‘n’
Process
Data
No
operation
Example:
HERE
BNOV Jump
Example:
HERE
BNZ Jump
Before Instruction
Before Instruction
PC
=
address (HERE)
PC
=
address (HERE)
After Instruction
After Instruction
If Overflow
PC
If Overflow
PC
=
=
=
=
0;
If Zero
PC
If Zero
PC
=
=
=
=
0;
address (Jump)
address (Jump)
1;
1;
address (HERE + 2)
address (HERE + 2)
DS39760D-page 224
© 2008 Microchip Technology Inc.
PIC18F2450/4450
BRA
Unconditional Branch
BRA
BSF
Bit Set f
Syntax:
n
Syntax:
BSF f, b {,a}
Operands:
Operation:
Status Affected:
Encoding:
Description:
-1024 ≤ n ≤ 1023
(PC) + 2 + 2n → PC
None
Operands:
0 ≤ f ≤ 255
0 ≤ b ≤ 7
a ∈ [0,1]
Operation:
1 → f<b>
1101
0nnn
nnnn
nnnn
Status Affected:
Encoding:
None
1000
Bit ‘b’ in register ‘f’ is set.
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank (default).
Add the 2’s complement number ‘2n’ to
the PC. Since the PC will have
incremented to fetch the next
instruction, the new address will be
PC + 2 + 2n. This instruction is a
two-cycle instruction.
bbba
ffff
ffff
Description:
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f ≤ 95 (5Fh). See
Section 19.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
Words:
Cycles:
1
2
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read literal
‘n’
Process
Data
Write to PC
Words:
Cycles:
1
1
No
operation
No
operation
No
operation
No
operation
Q Cycle Activity:
Q1
Q2
Q3
Q4
Example:
HERE
BRA Jump
Decode
Read
register ‘f’
Process
Data
Write
register ‘f’
Before Instruction
PC
=
=
address (HERE)
address (Jump)
After Instruction
PC
Example:
BSF
FLAG_REG, 7, 1
0Ah
8Ah
Before Instruction
FLAG_REG
After Instruction
FLAG_REG
=
=
© 2008 Microchip Technology Inc.
DS39760D-page 225
PIC18F2450/4450
BTFSC
Bit Test File, Skip if Clear
BTFSS
Bit Test File, Skip if Set
Syntax:
BTFSC f, b {,a}
Syntax:
BTFSS f, b {,a}
Operands:
0 ≤ f ≤ 255
0 ≤ b ≤ 7
a ∈ [0,1]
Operands:
0 ≤ f ≤ 255
0 ≤ b < 7
a ∈ [0,1]
Operation:
skip if (f<b>) = 0
Operation:
skip if (f<b>) = 1
Status Affected:
Encoding:
None
Status Affected:
Encoding:
None
1011
bbba
ffff
ffff
1010
bbba
ffff
ffff
Description:
If bit ‘b’ in register ‘f’ is ‘0’, then the next
instruction is skipped. If bit ‘b’ is ‘0’, then
the next instruction fetched during the
current instruction execution is discarded
and a NOPis executed instead, making
this a two-cycle instruction.
Description:
If bit ‘b’ in register ‘f’ is ‘1’, then the next
instruction is skipped. If bit ‘b’ is ‘1’, then
the next instruction fetched during the
current instruction execution is discarded
and a NOPis executed instead, making
this a two-cycle instruction.
If ‘a’ is ‘0’, the Access Bank is selected. If
‘a’ is ‘1’, the BSR is used to select the
GPR bank (default).
If ‘a’ is ‘0’, the Access Bank is selected. If
‘a’ is ‘1’, the BSR is used to select the
GPR bank (default).
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates in
Indexed Literal Offset Addressing
mode whenever f ≤ 95 (5Fh).
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f ≤ 95 (5Fh).
See Section 19.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
See Section 19.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
Words:
Cycles:
1
Words:
Cycles:
1
1(2)
1(2)
Note: 3 cycles if skip and followed
by a 2-word instruction.
Note: 3 cycles if skip and followed
by a 2-word instruction.
Q Cycle Activity:
Q1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Q2
Q3
Q4
Decode
Read
register ‘f’
Process
Data
No
operation
Decode
Read
register ‘f’
Process
Data
No
operation
If skip:
Q1
If skip:
Q1
Q2
Q3
Q4
Q2
Q3
Q4
No
No
No
No
No
No
No
No
operation
operation
operation
operation
operation
operation
operation
operation
If skip and followed by 2-word instruction:
If skip and followed by 2-word instruction:
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
No
No
No
No
No
No
No
No
operation
operation
operation
operation
operation
operation
operation
operation
No
No
No
No
No
No
No
No
operation
operation
operation
operation
operation
operation
operation
operation
Example:
HERE
FALSE
TRUE
BTFSC
:
:
FLAG, 1, 0
Example:
HERE
FALSE
TRUE
BTFSS
:
:
FLAG, 1, 0
Before Instruction
PC
Before Instruction
PC
=
address (HERE)
=
address (HERE)
After Instruction
After Instruction
If FLAG<1>
PC
If FLAG<1>
PC
=
=
=
=
0;
If FLAG<1>
PC
If FLAG<1>
PC
=
=
=
=
0;
address (TRUE)
1;
address (FALSE)
1;
address (FALSE)
address (TRUE)
DS39760D-page 226
© 2008 Microchip Technology Inc.
PIC18F2450/4450
BTG
Bit Toggle f
BOV
Branch if Overflow
Syntax:
BTG f, b {,a}
Syntax:
BOV
n
Operands:
0 ≤ f ≤ 255
0 ≤ b < 7
a ∈ [0,1]
Operands:
Operation:
-128 ≤ n ≤ 127
if Overflow bit is ‘1’,
(PC) + 2 + 2n → PC
Operation:
(f<b>) → f<b>
Status Affected:
Encoding:
None
Status Affected:
Encoding:
None
1110
0100
nnnn
nnnn
0111
bbba
ffff
ffff
Description:
If the Overflow bit is ‘1’, then the
Description:
Bit ‘b’ in data memory location ‘f’ is
inverted.
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank (default).
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f ≤ 95 (5Fh). See
Section 19.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
program will branch.
The 2’s complement number ‘2n’ is
added to the PC. Since the PC will have
incremented to fetch the next
instruction, the new address will be
PC + 2 + 2n. This instruction is then a
two-cycle instruction.
Words:
Cycles:
1
1(2)
Q Cycle Activity:
If Jump:
Words:
Cycles:
1
1
Q1
Q2
Q3
Q4
Decode
Read literal
‘n’
Process
Data
Write to PC
Q Cycle Activity:
Q1
No
operation
No
operation
No
operation
No
operation
Q2
Q3
Q4
Decode
Read
Process
Data
Write
register ‘f’
If No Jump:
Q1
register ‘f’
Q2
Q3
Q4
Decode
Read literal
‘n’
Process
Data
No
operation
Example:
BTG
PORTC, 4, 0
Before Instruction:
PORTC
After Instruction:
PORTC
=
0111 0101 [75h]
0110 0101 [65h]
Example:
HERE
BOV Jump
Before Instruction
=
PC
=
address (HERE)
After Instruction
If Overflow
PC
If Overflow
PC
=
=
=
=
1;
address (Jump)
0;
address (HERE + 2)
© 2008 Microchip Technology Inc.
DS39760D-page 227
PIC18F2450/4450
BZ
Branch if Zero
BZ
CALL
Subroutine Call
Syntax:
n
Syntax:
CALL k {,s}
Operands:
Operation:
-128 ≤ n ≤ 127
Operands:
0 ≤ k ≤ 1048575
s ∈ [0,1]
if Zero bit is ‘1’,
(PC) + 2 + 2n → PC
Operation:
(PC) + 4 → TOS,
k → PC<20:1>;
if s = 1,
Status Affected:
Encoding:
None
1110
0000
nnnn
nnnn
(W) → WS,
(STATUS) → STATUSS,
(BSR) → BSRS
Description:
If the Zero bit is ‘1’, then the program
will branch.
The 2’s complement number ‘2n’ is
added to the PC. Since the PC will have
incremented to fetch the next
instruction, the new address will be
PC + 2 + 2n. This instruction is then a
two-cycle instruction.
Status Affected:
None
Encoding:
1st word (k<7:0>)
2nd word(k<19:8>)
1110
1111
110s
k kkk
kkkk
kkkk
7
0
8
k
kkk kkkk
19
Description:
Subroutine call of entire 2-Mbyte
memory range. First, return address
(PC + 4) is pushed onto the return
stack. If ‘s’ = 1, the W, STATUS and
BSR
Words:
Cycles:
1
1(2)
Q Cycle Activity:
If Jump:
registers are also pushed into their
respective shadow registers, WS,
STATUSS and BSRS. If ‘s’ = 0, no
update occurs (default). Then, the
20-bit value ‘k’ is loaded into PC<20:1>.
CALLis a two-cycle instruction.
Q1
Q2
Q3
Q4
Decode
Read literal
‘n’
Process
Data
Write to PC
No
operation
No
operation
No
operation
No
operation
Words:
Cycles:
2
2
If No Jump:
Q1
Q2
Q3
Q4
Q Cycle Activity:
Q1
Decode
Read literal
‘n’
Process
Data
No
operation
Q2
Q3
Q4
Decode
Read literal Push PC to Read literal
‘k’<7:0>,
stack
‘k’<19:8>,
Write to PC
Example:
HERE
BZ Jump
Before Instruction
No
operation
No
operation
No
operation
No
operation
PC
=
address (HERE)
After Instruction
If Zero
PC
If Zero
PC
=
=
=
=
1;
address (Jump)
Example:
HERE
CALL THERE,1
0;
address (HERE + 2)
Before Instruction
PC
=
address (HERE)
After Instruction
PC
=
=
=
=
address (THERE)
TOS
WS
address (HERE + 4)
W
BSR
BSRS
STATUSS = STATUS
DS39760D-page 228
© 2008 Microchip Technology Inc.
PIC18F2450/4450
CLRF
Clear f
CLRWDT
Clear Watchdog Timer
Syntax:
CLRF f {,a}
Syntax:
CLRWDT
None
Operands:
0 ≤ f ≤ 255
a ∈ [0,1]
Operands:
Operation:
000h → WDT,
000h → WDT postscaler,
1 → TO,
Operation:
000h → f,
1 → Z
1 → PD
Status Affected:
Encoding:
Z
Status Affected:
Encoding:
TO, PD
0110
101a
ffff
ffff
0000
0000
0000
0100
Description:
Clears the contents of the specified
register.
Description:
CLRWDTinstruction resets the
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank (default).
Watchdog Timer. It also resets the
postscaler of the WDT. Status bits, TO
and PD, are set.
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f ≤ 95 (5Fh). See
Section 19.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
Words:
Cycles:
1
1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
No
Process
Data
No
operation
operation
Words:
Cycles:
1
1
Example:
CLRWDT
Q Cycle Activity:
Q1
Before Instruction
Q2
Q3
Q4
WDT Counter
After Instruction
WDT Counter
WDT Postscaler
TO
=
?
Decode
Read
register ‘f’
Process
Data
Write
register ‘f’
=
=
=
=
00h
0
1
Example:
CLRF
FLAG_REG,1
PD
1
Before Instruction
FLAG_REG
After Instruction
FLAG_REG
=
=
5Ah
00h
© 2008 Microchip Technology Inc.
DS39760D-page 229
PIC18F2450/4450
CPFSEQ
Compare f with W, Skip if f = W
COMF
Complement f
Syntax:
CPFSEQ f {,a}
Syntax:
COMF f {,d {,a}}
Operands:
0 ≤ f ≤ 255
a ∈ [0,1]
Operands:
0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
Operation:
(f) – (W),
skip if (f) = (W)
(unsigned comparison)
Operation:
(f) → dest
Status Affected:
Encoding:
N, Z
Status Affected:
Encoding:
None
0001
11da
ffff
ffff
0110
001a
ffff
ffff
Description:
The contents of register ‘f’ are
Description:
Compares the contents of data memory
location ‘f’ to the contents of W by
performing an unsigned subtraction.
If ‘f’ = W, then the fetched instruction is
discarded and a NOPis executed
instead, making this a two-cycle
instruction.
complemented. If ‘d’ is ‘0’, the result is
stored in W. If ‘d’ is ‘1’, the result is
stored back in register ‘f’ (default).
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank (default).
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f ≤ 95 (5Fh). See
Section 19.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank (default).
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f ≤ 95 (5Fh). See
Section 19.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
Words:
Cycles:
1
1
Q Cycle Activity:
Q1
Words:
Cycles:
1
Q2
Q3
Q4
1(2)
Decode
Read
register ‘f’
Process
Data
Write to
destination
Note: 3 cycles if skip and followed
by a 2-word instruction.
Q Cycle Activity:
Q1
Example:
COMF
REG, 0, 0
Q2
Read
register ‘f’
Q3
Process
Data
Q4
No
operation
Decode
Before Instruction
REG
=
13h
After Instruction
If skip:
Q1
REG
W
=
=
13h
ECh
Q2
No
Q3
No
Q4
No
No
operation
operation
operation
operation
If skip and followed by 2-word instruction:
Q1
No
Q2
No
Q3
No
Q4
No
operation
No
operation
No
operation
No
operation
No
operation
operation
operation
operation
Example:
HERE
CPFSEQ REG, 0
NEQUAL
EQUAL
:
:
Before Instruction
PC Address
=
=
=
HERE
?
?
W
REG
After Instruction
If REG
PC
If REG
PC
=
=
≠
=
W;
Address (EQUAL)
W;
Address (NEQUAL)
DS39760D-page 230
© 2008 Microchip Technology Inc.
PIC18F2450/4450
CPFSGT
Compare f with W, Skip if f > W
CPFSLT
Compare f with W, Skip if f < W
Syntax:
CPFSGT f {,a}
Syntax:
CPFSLT f {,a}
Operands:
0 ≤ f ≤ 255
a ∈ [0,1]
Operands:
0 ≤ f ≤ 255
a ∈ [0,1]
Operation:
(f) – (W),
skip if (f) > (W)
(unsigned comparison)
Operation:
(f) – (W),
skip if (f) < (W)
(unsigned comparison)
Status Affected:
Encoding:
None
Status Affected:
Encoding:
None
0110
0110
010a
ffff
ffff
000a
ffff
ffff
Description:
Compares the contents of data memory
location ‘f’ to the contents of the W by
performing an unsigned subtraction.
If the contents of ‘f’ are greater than the
contents of WREG, then the fetched
instruction is discarded and a NOPis
executed instead, making this a
Description:
Compares the contents of data memory
location ‘f’ to the contents of W by
performing an unsigned subtraction.
If the contents of ‘f’ are less than the
contents of W, then the fetched
instruction is discarded and a NOPis
executed instead, making this a
two-cycle instruction.
two-cycle instruction.
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank (default).
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f ≤ 95 (5Fh). See
Section 19.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank (default).
Words:
Cycles:
1
1(2)
Note: 3 cycles if skip and followed
by a 2-word instruction.
Q Cycle Activity:
Q1
Q2
Q3
Q4
Words:
Cycles:
1
Decode
Read
register ‘f’
Process
Data
No
operation
1(2)
Note: 3 cycles if skip and followed
by a 2-word instruction.
If skip:
Q1
Q2
Q3
Q4
Q Cycle Activity:
Q1
No
operation
No
operation
No
operation
No
operation
Q2
Read
register ‘f’
Q3
Process
Data
Q4
No
operation
Decode
If skip and followed by 2-word instruction:
If skip:
Q1
Q1
Q2
Q3
Q4
Q2
No
Q3
No
Q4
No
No
operation
No
operation
No
operation
No
operation
No
operation
operation
operation
operation
No
operation
No
operation
No
operation
No
operation
If skip and followed by 2-word instruction:
Q1
No
operation
No
Q2
No
operation
No
Q3
No
operation
No
Q4
No
operation
No
Example:
HERE
NLESS
LESS
CPFSLT REG, 1
:
:
operation
operation
operation
operation
Before Instruction
PC
W
=
=
Address (HERE)
Example:
HERE
NGREATER
GREATER
CPFSGT REG, 0
:
:
?
After Instruction
If REG
PC
If REG
PC
<
=
≥
=
W;
Before Instruction
Address (LESS)
W;
PC
W
=
=
Address (HERE)
Address (NLESS)
?
After Instruction
If REG
PC
If REG
PC
>
=
≤
=
W;
Address (GREATER)
W;
Address (NGREATER)
© 2008 Microchip Technology Inc.
DS39760D-page 231
PIC18F2450/4450
DAW
Decimal Adjust W Register
DECF
Decrement f
Syntax:
DAW
None
Syntax:
DECF f {,d {,a}}
Operands:
Operation:
Operands:
0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
If [W<3:0> > 9] or [DC = 1] then,
(W<3:0>) + 6 → W<3:0>;
else,
Operation:
(f) – 1 → dest
(W<3:0>) → W<3:0>
Status Affected:
Encoding:
C, DC, N, OV, Z
0000
01da
ffff
ffff
If [W<7:4> + DC > 9] or [C = 1] then,
(W<7:4>) + 6 + DC → W<7:4>;
else,
Description:
Decrement register ‘f’. If ‘d’ is ‘0’, the
result is stored in W. If ‘d’ is ‘1’, the
result is stored back in register ‘f’
(default).
(W<7:4>) + DC → W<7:4>
Status Affected:
Encoding:
C
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank (default).
0000
0000
0000
0111
Description:
DAW adjusts the 8-bit value in W,
resulting from the earlier addition of two
variables (each in packed BCD format)
and produces a correct packed BCD
result.
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f ≤ 95 (5Fh). See
Section 19.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
Words:
Cycles:
1
1
Q Cycle Activity:
Q1
Words:
Cycles:
1
1
Q2
Q3
Q4
Decode
Read
register W
Process
Data
Write
W
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
register ‘f’
Process
Data
Write to
destination
Example 1:
DAW
Before Instruction
W
=
A5h
0
Example:
DECF
CNT,
1, 0
C
=
=
DC
0
Before Instruction
After Instruction
CNT
Z
=
01h
0
W
=
=
=
05h
1
0
=
C
After Instruction
DC
CNT
Z
=
=
00h
1
Example 2:
Before Instruction
W
=
=
=
CEh
0
0
C
DC
After Instruction
W
=
=
=
34h
1
0
C
DC
DS39760D-page 232
© 2008 Microchip Technology Inc.
PIC18F2450/4450
DECFSZ
Decrement f, Skip if 0
DCFSNZ
Decrement f, Skip if Not 0
Syntax:
DECFSZ f {,d {,a}}
Syntax:
DCFSNZ f {,d {,a}}
Operands:
0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
Operands:
0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
Operation:
(f) – 1 → dest,
Operation:
(f) – 1 → dest,
skip if result = 0
skip if result ≠ 0
Status Affected:
Encoding:
None
Status Affected:
Encoding:
None
0100
The contents of register ‘f’ are
0010
11da
ffff
ffff
11da
ffff
ffff
Description:
The contents of register ‘f’ are
Description:
decremented. If ‘d’ is ‘0’, the result is
placed in W. If ‘d’ is ‘1’, the result is
placed back in register ‘f’ (default).
If the result is ‘0’, the next instruction,
which is already fetched, is discarded
and a NOPis executed instead, making
it a two-cycle instruction.
decremented. If ‘d’ is ‘0’, the result is
placed in W. If ‘d’ is ‘1’, the result is
placed back in register ‘f’ (default).
If the result is not ‘0’, the next
instruction, which is already fetched, is
discarded and a NOPis executed
instead, making it a two-cycle
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank (default).
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f ≤ 95 (5Fh). See
Section 19.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
instruction.
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank (default).
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f ≤ 95 (5Fh). See
Section 19.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
Words:
Cycles:
1
Words:
Cycles:
1
1(2)
Note: 3 cycles if skip and followed
by a 2-word instruction.
1(2)
Note: 3 cycles if skip and followed
by a 2-word instruction.
Q Cycle Activity:
Q1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Q2
Q3
Q4
Decode
Read
register ‘f’
Process
Data
Write to
destination
Decode
Read
Process
Data
Write to
destination
register ‘f’
If skip:
Q1
If skip:
Q1
Q2
Q3
Q4
Q2
Q3
Q4
No
No
No
No
operation
operation
operation
operation
No
No
No
No
operation
operation
operation
operation
If skip and followed by 2-word instruction:
If skip and followed by 2-word instruction:
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
No
No
No
No
operation
operation
operation
operation
No
No
No
No
operation
operation
operation
operation
No
No
No
No
operation
operation
operation
operation
No
No
No
No
operation
operation
operation
operation
Example:
HERE
DECFSZ
GOTO
CNT, 1, 1
LOOP
Example:
HERE
ZERO
NZERO
DCFSNZ TEMP, 1, 0
:
:
CONTINUE
Before Instruction
PC
After Instruction
Before Instruction
TEMP
After Instruction
=
Address (HERE)
=
?
CNT
=
CNT – 1
0;
If CNT
=
=
≠
=
TEMP
If TEMP
PC
If TEMP
PC
=
=
=
≠
=
TEMP – 1,
0;
Address (ZERO)
0;
Address (NZERO)
PC
Address (CONTINUE)
0;
If CNT
PC
Address (HERE + 2)
© 2008 Microchip Technology Inc.
DS39760D-page 233
PIC18F2450/4450
GOTO
Unconditional Branch
GOTO
INCF
Increment f
Syntax:
k
Syntax:
INCF f {,d {,a}}
Operands:
Operation:
Status Affected:
0 ≤ k ≤ 1048575
k → PC<20:1>
None
Operands:
0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
Operation:
(f) + 1 → dest
Encoding:
1st word (k<7:0>)
2nd word(k<19:8>)
Status Affected:
Encoding:
C, DC, N, OV, Z
1110
1111
1111
kkk
k kkk
kkkk
kkkk
kkkk
7
0
8
k
0010
10da
ffff
ffff
19
Description:
GOTOallows an unconditional branch
anywhere within the entire
2-Mbyte memory range. The 20-bit
value ‘k’ is loaded into PC<20:1>. GOTO
is always a two-cycle instruction.
Description:
The contents of register ‘f’ are
incremented. If ‘d’ is ‘0’, the result is
placed in W. If ‘d’ is ‘1’, the result is
placed back in register ‘f’ (default).
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank (default).
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f ≤ 95 (5Fh). See
Section 19.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
Words:
Cycles:
2
2
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read literal
‘k’<7:0>,
No
operation
Read literal
‘k’<19:8>,
Write to PC
No
operation
No
No
No
Words:
Cycles:
1
1
operation
operation
operation
Q Cycle Activity:
Q1
Example:
GOTO THERE
Q2
Q3
Q4
After Instruction
Decode
Read
register ‘f’
Process
Data
Write to
destination
PC
=
Address (THERE)
Example:
INCF
CNT, 1, 0
Before Instruction
CNT
Z
=
FFh
0
=
=
=
C
?
DC
?
After Instruction
CNT
Z
=
00h
1
=
=
=
C
1
DC
1
DS39760D-page 234
© 2008 Microchip Technology Inc.
PIC18F2450/4450
INFSNZ
Increment f, Skip if Not 0
INCFSZ
Increment f, Skip if 0
Syntax:
INFSNZ f {,d {,a}}
Syntax:
INCFSZ f {,d {,a}}
Operands:
0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
Operands:
0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
Operation:
(f) + 1 → dest,
skip if result ≠ 0
Operation:
(f) + 1 → dest,
skip if result = 0
Status Affected:
Encoding:
None
0100
The contents of register ‘f’ are
incremented. If ‘d’ is ‘0’, the result is
placed in W. If ‘d’ is ‘1’, the result is
placed back in register ‘f’ (default).
If the result is not ‘0’, the next
Status Affected:
Encoding:
None
10da
ffff
ffff
0011
11da
ffff
ffff
Description:
Description:
The contents of register ‘f’ are
incremented. If ‘d’ is ‘0’, the result is
placed in W. If ‘d’ is ‘1’, the result is
placed back in register ‘f’. (default)
If the result is ‘0’, the next instruction,
which is already fetched, is discarded
and a NOPis executed instead, making
it a two-cycle instruction.
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank (default).
instruction, which is already fetched, is
discarded and a NOPis executed
instead, making it a two-cycle
instruction.
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank (default).
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f ≤ 95 (5Fh). See
Section 19.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f ≤ 95 (5Fh). See
Section 19.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
Words:
Cycles:
1
Words:
Cycles:
1
1(2)
1(2)
Note: 3 cycles if skip and followed
by a 2-word instruction.
Note: 3 cycles if skip and followed
by a 2-word instruction.
Q Cycle Activity:
Q1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Q2
Q3
Q4
Decode
Read
register ‘f’
Process
Data
Write to
destination
Decode
Read
register ‘f’
Process
Data
Write to
destination
If skip:
Q1
If skip:
Q1
Q2
Q3
Q4
Q2
Q3
Q4
No
No
No
No
No
No
No
No
operation
operation
operation
operation
operation
operation
operation
operation
If skip and followed by 2-word instruction:
If skip and followed by 2-word instruction:
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
No
No
No
No
No
No
No
No
operation
operation
operation
operation
operation
operation
operation
operation
No
No
No
No
No
No
No
No
operation
operation
operation
operation
operation
operation
operation
operation
Example:
HERE
NZERO
ZERO
INCFSZ
:
:
CNT, 1, 0
Example:
HERE
ZERO
NZERO
INFSNZ REG, 1, 0
Before Instruction
PC
After Instruction
Before Instruction
PC
After Instruction
=
Address (HERE)
=
Address (HERE)
REG
If REG
PC
If REG
PC
=
REG + 1
CNT
If CNT
PC
If CNT
PC
=
CNT + 1
≠
=
=
=
0;
=
=
≠
=
0;
Address (NZERO)
0;
Address (ZERO)
Address (ZERO)
0;
Address (NZERO)
© 2008 Microchip Technology Inc.
DS39760D-page 235
PIC18F2450/4450
IORLW
Inclusive OR Literal with W
IORLW
IORWF
Inclusive OR W with f
Syntax:
k
Syntax:
IORWF f {,d {,a}}
Operands:
Operation:
Status Affected:
Encoding:
Description:
0 ≤ k ≤ 255
(W) .OR. k → W
N, Z
Operands:
0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
Operation:
(W) .OR. (f) → dest
0000
1001
kkkk
kkkk
Status Affected:
Encoding:
N, Z
The contents of W are ORed with the
8-bit literal ‘k’. The result is placed in W.
0001
00da
ffff
ffff
Description:
Inclusive OR W with register ‘f’. If ‘d’ is
‘0’, the result is placed in W. If ‘d’ is ‘1’,
the result is placed back in register ‘f’
(default).
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank (default).
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f ≤ 95 (5Fh). See
Section 19.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
Words:
Cycles:
1
1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
Process
Data
Write to W
literal ‘k’
Example:
IORLW
35h
Before Instruction
W
=
9Ah
BFh
After Instruction
W
=
Words:
Cycles:
1
1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
register ‘f’
Process
Data
Write to
destination
Example:
IORWF RESULT, 0, 1
Before Instruction
RESULT =
13h
91h
W
=
After Instruction
RESULT =
13h
93h
W
=
DS39760D-page 236
© 2008 Microchip Technology Inc.
PIC18F2450/4450
LFSR
Load FSR
MOVF
Move f
Syntax:
LFSR f, k
Syntax:
MOVF f {,d {,a}}
Operands:
0 ≤ f ≤ 2
0 ≤ k ≤ 4095
Operands:
0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
Operation:
k → FSRf
Operation:
f → dest
Status Affected:
Encoding:
None
Status Affected:
Encoding:
N, Z
0101
1110
1111
1110
0000
00ff
k kkk
k kkk
11
kkkk
00da
ffff
ffff
7
Description:
The 12-bit literal ‘k’ is loaded into the
File Select Register pointed to by ‘f’.
Description:
The contents of register ‘f’ are moved to
a destination dependent upon the
status of ‘d’. If ‘d’ is ‘0’, the result is
placed in W. If ‘d’ is ‘1’, the result is
placed back in register ‘f’ (default).
Location ‘f’ can be anywhere in the
256-byte bank.
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank (default).
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f ≤ 95 (5Fh). See
Section 19.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
Words:
Cycles:
2
2
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read literal
‘k’ MSB
Process
Data
Write
literal ‘k’ MSB
to FSRfH
Decode
Read literal
‘k’ LSB
Process
Data
Write literal ‘k’
to FSRfL
Example:
LFSR 2, 3ABh
After Instruction
FSR2H
FSR2L
=
=
03h
ABh
Words:
Cycles:
1
1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
register ‘f’
Process
Data
Write W
Example:
MOVF
REG, 0, 0
Before Instruction
REG
W
=
=
22h
FFh
After Instruction
REG
W
=
=
22h
22h
© 2008 Microchip Technology Inc.
DS39760D-page 237
PIC18F2450/4450
MOVFF
Move f to f
MOVFF f ,f
MOVLB
Move Literal to Low Nibble in BSR
MOVLW
Syntax:
Syntax:
k
s
d
Operands:
0 ≤ f ≤ 4095
Operands:
Operation:
Status Affected:
Encoding:
Description:
0 ≤ k ≤ 255
k → BSR
None
s
0 ≤ f ≤ 4095
d
Operation:
(f ) → f
s
d
Status Affected:
None
0000
0001
kkkk
kkkk
Encoding:
1st word (source)
2nd word (destin.)
The 8-bit literal ‘k’ is loaded into the
Bank Select Register (BSR). The value
of BSR<7:4> always remains ‘0’
1100
1111
ffff
ffff
ffff
ffff
ffff
ffff
s
d
Description:
The contents of source register ‘f ’ are
regardless of the value of k :k .
s
7 4
moved to destination register ‘f ’.
d
Words:
Cycles:
1
1
Location of source ‘f ’ can be anywhere
s
in the 4096-byte data space (000h to
FFFh) and location of destination ‘f ’
can also be anywhere from 000h to
FFFh.
Either source or destination can be W
(a useful special situation).
d
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
literal ‘k’
Process
Data
Write literal
‘k’ to BSR
MOVFFis particularly useful for
transferring a data memory location to a
peripheral register (such as the transmit
buffer or an I/O port).
The MOVFFinstruction cannot use the
PCL, TOSU, TOSH or TOSL as the
destination register.
Example:
MOVLB
5
Before Instruction
BSR Register =
After Instruction
BSR Register =
02h
05h
Words:
Cycles:
2
2
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
register ‘f’
(src)
Process
Data
No
operation
Decode
No
operation
No
operation
Write
register ‘f’
(dest)
No dummy
read
Example:
MOVFF
REG1, REG2
Before Instruction
REG1
REG2
=
=
33h
11h
After Instruction
REG1
REG2
=
=
33h
33h
DS39760D-page 238
© 2008 Microchip Technology Inc.
PIC18F2450/4450
MOVLW
Move Literal to W
MOVLW
MOVWF
Move W to f
Syntax:
k
Syntax:
MOVWF f {,a}
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
0 ≤ k ≤ 255
k → W
None
Operands:
0 ≤ f ≤ 255
a ∈ [0,1]
Operation:
(W) → f
Status Affected:
Encoding:
None
0110
Move data from W to register ‘f’.
Location ‘f’ can be anywhere in the
256-byte bank.
0000
1110
kkkk
kkkk
111a
ffff
ffff
The 8-bit literal ‘k’ is loaded into W.
Description:
1
1
Cycles:
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank (default).
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f ≤ 95 (5Fh). See
Section 19.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
literal ‘k’
Process
Data
Write to W
Example:
MOVLW
5Ah
After Instruction
W
=
5Ah
Words:
Cycles:
1
1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
register ‘f’
Process
Data
Write
register ‘f’
Example:
MOVWF
REG, 0
Before Instruction
W
REG
=
=
4Fh
FFh
After Instruction
W
REG
=
=
4Fh
4Fh
© 2008 Microchip Technology Inc.
DS39760D-page 239
PIC18F2450/4450
MULLW
Multiply Literal with W
MULWF
Multiply W with f
Syntax:
MULLW
k
Syntax:
MULWF f {,a}
Operands:
Operation:
Status Affected:
Encoding:
Description:
0 ≤ k ≤ 255
Operands:
0 ≤ f ≤ 255
a ∈ [0,1]
(W) x k → PRODH:PRODL
Operation:
(W) x (f) → PRODH:PRODL
None
Status Affected:
Encoding:
None
0000
1101
kkkk
kkkk
0000
001a
ffff
ffff
An unsigned multiplication is carried
out between the contents of W and the
8-bit literal ‘k’. The 16-bit result is
placed in PRODH:PRODL register pair.
PRODH contains the high byte.
W is unchanged.
None of the Status flags are affected.
Note that neither Overflow nor Carry is
possible in this operation. A zero result
is possible but not detected.
Description:
An unsigned multiplication is carried
out between the contents of W and the
register file location ‘f’. The 16-bit
result is stored in the PRODH:PRODL
register pair. PRODH contains the
high byte. Both W and ‘f’ are
unchanged.
None of the Status flags are affected.
Note that neither Overflow nor Carry is
possible in this operation. A zero
result is possible but not detected.
If ‘a’ is ‘0’, the Access Bank is
selected. If ‘a’ is ‘1’, the BSR is used
to select the GPR bank (default).
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction
operates in Indexed Literal Offset
Addressing mode whenever
Words:
Cycles:
1
1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
literal ‘k’
Process
Data
Write
registers
PRODH:
PRODL
f ≤ 95 (5Fh). See Section 19.2.3
“Byte-Oriented and Bit-Oriented
Instructions in Indexed Literal Offset
Mode” for details.
Example:
MULLW
0C4h
Before Instruction
Words:
Cycles:
1
1
W
PRODH
PRODL
=
=
=
E2h
?
?
After Instruction
Q Cycle Activity:
Q1
W
PRODH
PRODL
=
=
=
E2h
ADh
08h
Q2
Q3
Q4
Decode
Read
register ‘f’
Process
Data
Write
registers
PRODH:
PRODL
Example:
MULWF
REG, 1
Before Instruction
W
=
=
=
=
C4h
REG
B5h
?
PRODH
PRODL
?
After Instruction
W
=
=
=
=
C4h
B5h
8Ah
94h
REG
PRODH
PRODL
DS39760D-page 240
© 2008 Microchip Technology Inc.
PIC18F2450/4450
NEGF
Negate f
NOP
No Operation
Syntax:
NEGF f {,a}
Syntax:
NOP
Operands:
0 ≤ f ≤ 255
a ∈ [0,1]
Operands:
Operation:
None
No operation
Operation:
(f) + 1 → f
Status Affected:
Encoding:
None
0000
1111
Status Affected:
Encoding:
N, OV, C, DC, Z
0000
xxxx
0000
xxxx
0000
xxxx
0110
110a
ffff
ffff
Description:
Location ‘f’ is negated using two’s
complement. The result is placed in the
data memory location ‘f’.
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank (default).
Description:
Words:
No operation.
1
1
Cycles:
Q Cycle Activity:
Q1
Q2
Q3
No
operation
Q4
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f ≤ 95 (5Fh). See
Section 19.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
Decode
No
operation
No
operation
Example:
None.
Words:
Cycles:
1
1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
register ‘f’
Process
Data
Write
register ‘f’
Example:
NEGF
REG, 1
Before Instruction
REG
After Instruction
REG
=
0011 1010 [3Ah]
1100 0110 [C6h]
=
© 2008 Microchip Technology Inc.
DS39760D-page 241
PIC18F2450/4450
POP
Pop Top of Return Stack
PUSH
Push Top of Return Stack
Syntax:
POP
Syntax:
PUSH
Operands:
Operation:
Status Affected:
Encoding:
Description:
None
Operands:
Operation:
Status Affected:
Encoding:
Description:
None
(TOS) → bit bucket
(PC + 2) → TOS
None
None
0000
0000
0000
0110
0000
0000
0000
0101
The TOS value is pulled off the return
stack and is discarded. The TOS value
then becomes the previous value that
was pushed onto the return stack.
This instruction is provided to enable
the user to properly manage the return
stack to incorporate a software stack.
The PC + 2 is pushed onto the top of
the return stack. The previous TOS
value is pushed down on the stack.
This instruction allows implementing a
software stack by modifying TOS and
then pushing it onto the return stack.
Words:
Cycles:
1
1
Words:
Cycles:
1
1
Q Cycle Activity:
Q1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Q2
Q3
Q4
Decode
Push PC + 2
onto return
stack
No
operation
No
operation
Decode
No
operation
Pop TOS
value
No
operation
Example:
POP
Example:
PUSH
GOTO
NEW
Before Instruction
Before Instruction
TOS
Stack (1 level down)
TOS
PC
=
=
345Ah
0124h
=
=
0031A2h
014332h
After Instruction
After Instruction
PC
=
=
=
0126h
0126h
345Ah
TOS
TOS
PC
=
=
014332h
NEW
Stack (1 level down)
DS39760D-page 242
© 2008 Microchip Technology Inc.
PIC18F2450/4450
RCALL
Relative Call
RCALL
RESET
Reset
Syntax:
n
Syntax:
RESET
None
Operands:
Operation:
-1024 ≤ n ≤ 1023
Operands:
Operation:
(PC) + 2 → TOS,
(PC) + 2 + 2n → PC
Reset all registers and flags that are
affected by a MCLR Reset.
Status Affected:
Encoding:
None
Status Affected:
Encoding:
All
0000
1101
1nnn
nnnn
nnnn
0000
1111
1111
Description:
Subroutine call with a jump up to 1K
from the current location. First, return
address (PC + 2) is pushed onto the
stack. Then, add the 2’s complement
number ‘2n’ to the PC. Since the PC will
have incremented to fetch the next
instruction, the new address will be
PC + 2 + 2n. This instruction is a
two-cycle instruction.
Description:
This instruction provides a way to
execute a MCLR Reset in software.
Words:
Cycles:
1
1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Start
No
No
Reset
operation
operation
Words:
Cycles:
1
2
Example:
RESET
Q Cycle Activity:
Q1
After Instruction
Registers =
Q2
Q3
Q4
Reset Value
Reset Value
Flags*
=
Decode
Read literal
‘n’
Process
Data
Write to PC
Push PC to
stack
No
No
No
No
operation
operation
operation
operation
Example:
HERE
RCALL Jump
Before Instruction
PC
After Instruction
PC
TOS =
=
Address (HERE)
=
Address (Jump)
Address (HERE + 2)
© 2008 Microchip Technology Inc.
DS39760D-page 243
PIC18F2450/4450
RETFIE
Return from Interrupt
RETLW
Return Literal to W
RETLW
Syntax:
RETFIE {s}
Syntax:
k
Operands:
Operation:
s ∈ [0,1]
Operands:
Operation:
0 ≤ k ≤ 255
(TOS) → PC,
k → W,
1 → GIE/GIEH or PEIE/GIEL;
if s = 1,
(TOS) → PC,
PCLATU, PCLATH are unchanged
(WS) → W,
(STATUSS) → STATUS,
(BSRS) → BSR,
Status Affected:
Encoding:
None
0000
1100
kkkk
kkkk
PCLATU, PCLATH are unchanged
Description:
W is loaded with the 8-bit literal ‘k’. The
program counter is loaded from the top
of the stack (the return address). The
high address latch (PCLATH) remains
unchanged.
Status Affected:
Encoding:
GIE/GIEH, PEIE/GIEL.
0000
0000
0001
000s
Description:
Return from interrupt. Stack is popped
and Top-of-Stack (TOS) is loaded into
the PC. Interrupts are enabled by
setting either the high or low-priority
global interrupt enable bit. If ‘s’ = 1, the
contents of the shadow registers WS,
STATUSS and BSRS are loaded into
their corresponding registers, W,
Words:
Cycles:
1
2
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
literal ‘k’
Process
Data
Pop PC from
stack, Write
to W
STATUS and BSR. If ‘s’ = 0, no update
of these registers occurs (default).
No
operation
No
No
No
Words:
Cycles:
1
2
operation
operation
operation
Q Cycle Activity:
Q1
Example:
Q2
Q3
Q4
CALL TABLE ; W contains table
; offset value
Decode
No
operation
No
operation
Pop PC from
stack
; W now has
; table value
Set GIEH or
GIEL
:
No
operation
No
operation
No
operation
No
operation
TABLE
ADDWF PCL ; W = offset
RETLW k0
RETLW k1
:
; Begin table
;
Example:
RETFIE
1
After Interrupt
:
PC
=
=
=
=
=
TOS
WS
RETLW kn
; End of table
W
BSR
STATUS
BSRS
STATUSS
1
Before Instruction
GIE/GIEH, PEIE/GIEL
W
=
07h
After Instruction
W
=
value of kn
DS39760D-page 244
© 2008 Microchip Technology Inc.
PIC18F2450/4450
RETURN
Return from Subroutine
RLCF
Rotate Left f through Carry
Syntax:
RETURN {s}
Syntax:
RLCF f {,d {,a}}
Operands:
Operation:
s ∈ [0,1]
Operands:
0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
(TOS) → PC;
if s = 1,
(WS) → W,
Operation:
(f<n>) → dest<n + 1>,
(f<7>) → C,
(C) → dest<0>
(STATUSS) → STATUS,
(BSRS) → BSR,
PCLATU, PCLATH are unchanged
Status Affected:
Encoding:
C, N, Z
Status Affected:
Encoding:
None
0011
01da
ffff
ffff
0000
0000
0001
001s
Description:
The contents of register ‘f’ are rotated
one bit to the left through the Carry
flag. If ‘d’ is ‘0’, the result is placed in
W. If ‘d’ is ‘1’, the result is stored back
in register ‘f’ (default).
If ‘a’ is ‘0’, the Access Bank is
selected. If ‘a’ is ‘1’, the BSR is used to
select the GPR bank (default).
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction
operates in Indexed Literal Offset
Addressing mode whenever
Description:
Return from subroutine. The stack is
popped and the top of the stack (TOS)
is loaded into the program counter. If
‘s’= 1, the contents of the shadow
registers WS, STATUSS and BSRS are
loaded into their corresponding
registers, W, STATUS and BSR. If
‘s’ = 0, no update of these registers
occurs (default).
Words:
Cycles:
1
2
f ≤ 95 (5Fh). See Section 19.2.3
“Byte-Oriented and Bit-Oriented
Instructions in Indexed Literal Offset
Mode” for details.
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
No
operation
Process
Data
Pop PC
register f
C
from stack
No
No
No
No
operation
operation
operation
operation
Words:
Cycles:
1
1
Q Cycle Activity:
Q1
Example:
RETURN
Q2
Read
register ‘f’
Q3
Q4
After Instruction:
Decode
Process
Data
Write to
destination
PC = TOS
Example:
RLCF
REG, 0, 0
Before Instruction
REG
C
=
=
1110 0110
0
After Instruction
REG
W
C
=
=
=
1110 0110
1100 1100
1
© 2008 Microchip Technology Inc.
DS39760D-page 245
PIC18F2450/4450
RLNCF
Rotate Left f (No Carry)
RRCF
Rotate Right f through Carry
Syntax:
RLNCF f {,d {,a}}
Syntax:
RRCF f {,d {,a}}
Operands:
0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
Operands:
0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
Operation:
(f<n>) → dest<n + 1>,
(f<7>) → dest<0>
Operation:
(f<n>) → dest<n – 1>,
(f<0>) → C,
(C) → dest<7>
Status Affected:
Encoding:
N, Z
Status Affected:
Encoding:
C, N, Z
0100
01da
ffff
ffff
0011
00da
ffff
ffff
Description:
The contents of register ‘f’ are rotated
one bit to the left. If ‘d’ is ‘0’, the result
is placed in W. If ‘d’ is ‘1’, the result is
stored back in register ‘f’ (default).
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank (default).
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f ≤ 95 (5Fh). See
Section 19.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
Description:
The contents of register ‘f’ are rotated
one bit to the right through the Carry
flag. If ‘d’ is ‘0’, the result is placed in W.
If ‘d’ is ‘1’, the result is placed back in
register ‘f’ (default).
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank (default).
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f ≤ 95 (5Fh). See
Section 19.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
register f
register f
C
Words:
Cycles:
1
1
Words:
Cycles:
1
1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Q Cycle Activity:
Q1
Decode
Read
register ‘f’
Process
Data
Write to
destination
Q2
Q3
Q4
Decode
Read
register ‘f’
Process
Data
Write to
destination
Example:
RLNCF
REG, 1, 0
Before Instruction
REG
After Instruction
Example:
RRCF
REG, 0, 0
=
1010 1011
0101 0111
Before Instruction
REG
=
REG
C
=
=
1110 0110
0
After Instruction
REG
W
C
=
=
=
1110 0110
0111 0011
0
DS39760D-page 246
© 2008 Microchip Technology Inc.
PIC18F2450/4450
RRNCF
Rotate Right f (No Carry)
SETF
Set f
Syntax:
RRNCF f {,d {,a}}
Syntax:
SETF f {,a}
Operands:
0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
Operands:
0 ≤ f ≤ 255
a ∈ [0,1]
Operation:
FFh → f
Operation:
(f<n>) → dest<n – 1>,
(f<0>) → dest<7>
Status Affected:
Encoding:
None
0110
100a
ffff
ffff
Status Affected:
Encoding:
N, Z
Description:
The contents of the specified register
are set to FFh.
0100
00da
ffff
ffff
Description:
The contents of register ‘f’ are rotated
one bit to the right. If ‘d’ is ‘0’, the result
is placed in W. If ‘d’ is ‘1’, the result is
placed back in register ‘f’ (default).
If ‘a’ is ‘0’, the Access Bank will be
selected, overriding the BSR value. If ‘a’
is ‘1’, then the bank will be selected as
per the BSR value (default).
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f ≤ 95 (5Fh). See
Section 19.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank (default).
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f ≤ 95 (5Fh). See
Section 19.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
Words:
Cycles:
1
1
Q Cycle Activity:
Q1
Q2
Q3
Q4
register f
Decode
Read
register ‘f’
Process
Data
Write
register ‘f’
Words:
Cycles:
1
1
Example:
SETF
REG,1
Q Cycle Activity:
Q1
Before Instruction
REG
After Instruction
REG
=
=
5Ah
FFh
Q2
Q3
Q4
Decode
Read
register ‘f’
Process
Data
Write to
destination
Example 1:
RRNCF
REG, 1, 0
Before Instruction
REG
After Instruction
REG
=
1101 0111
1110 1011
RRNCF REG, 0, 0
=
Example 2:
Before Instruction
W
REG
=
=
?
1101 0111
After Instruction
W
REG
=
=
1110 1011
1101 0111
© 2008 Microchip Technology Inc.
DS39760D-page 247
PIC18F2450/4450
SLEEP
Enter Sleep Mode
SUBFWB
Subtract f from W with Borrow
Syntax:
SLEEP
None
Syntax:
SUBFWB f {,d {,a}}
Operands:
Operation:
Operands:
0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
00h → WDT,
0 → WDT postscaler,
1 → TO,
Operation:
(W) – (f) – (C) → dest
0 → PD
Status Affected:
Encoding:
N, OV, C, DC, Z
Status Affected:
Encoding:
TO, PD
0101
01da
ffff
ffff
0000
0000
0000
0011
Description:
Subtract register ‘f’ and Carry flag
(borrow) from W (2’s complement
method). If ‘d’ is ‘0’, the result is stored
in W. If ‘d’ is ‘1’, the result is stored in
register ‘f’ (default).
Description:
The Power-Down status bit (PD) is
cleared. The Time-out status bit (TO)
is set. Watchdog Timer and its
postscaler are cleared.
If ‘a’ is ‘0’, the Access Bank is
selected. If ‘a’ is ‘1’, the BSR is used
to select the GPR bank (default).
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction
operates in Indexed Literal Offset
Addressing mode whenever
f ≤ 95 (5Fh). See Section 19.2.3
“Byte-Oriented and Bit-Oriented
Instructions in Indexed Literal Offset
Mode” for details.
The processor is put into Sleep mode
with the oscillator stopped.
Words:
Cycles:
1
1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
No
operation
Process
Data
Go to
Sleep
Example:
SLEEP
Words:
Cycles:
1
1
Before Instruction
TO
PD
=
=
?
?
Q Cycle Activity:
Q1
Q2
Q3
Q4
After Instruction
Decode
Read
register ‘f’
Process
Data
Write to
destination
TO
PD
=
=
1 †
0
Example 1:
SUBFWB
REG, 1, 0
†
If WDT causes wake-up, this bit is cleared.
Before Instruction
REG
W
C
=
=
=
3
2
1
After Instruction
REG
W
C
=
FF
2
=
=
=
=
0
Z
0
1
N
; result is negative
Example 2:
SUBFWB
REG, 0, 0
Before Instruction
REG
W
=
=
=
2
5
1
C
After Instruction
REG
W
C
=
2
3
1
0
=
=
=
=
Z
N
0
; result is positive
Example 3:
SUBFWB
REG, 1, 0
Before Instruction
REG
W
=
=
=
1
2
0
C
After Instruction
REG
W
C
=
0
2
1
1
0
=
=
=
=
Z
; result is zero
N
DS39760D-page 248
© 2008 Microchip Technology Inc.
PIC18F2450/4450
SUBLW
Subtract W from Literal
SUBLW
SUBWF
Subtract W from f
Syntax:
k
Syntax:
SUBWF f {,d {,a}}
Operands:
Operation:
Status Affected:
Encoding:
Description
0 ≤ k ≤ 255
Operands:
0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
k – (W) → W
N, OV, C, DC, Z
Operation:
(f) – (W) → dest
0000
1000
kkkk
kkkk
Status Affected:
Encoding:
N, OV, C, DC, Z
0101 11da
W is subtracted from the 8-bit
literal ‘k’. The result is placed in W.
ffff
ffff
Description:
Subtract W from register ‘f’ (2’s
complement method). If ‘d’ is ‘0’, the
result is stored in W. If ‘d’ is ‘1’, the
result is stored back in register ‘f’
(default).
Words:
Cycles:
1
1
Q Cycle Activity:
Q1
Q2
Q3
Q4
If ‘a’ is ‘0’, the Access Bank is
selected. If ‘a’ is ‘1’, the BSR is used
to select the GPR bank (default).
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction
operates in Indexed Literal Offset
Addressing mode whenever
f ≤ 95 (5Fh). See Section 19.2.3
“Byte-Oriented and Bit-Oriented
Instructions in Indexed Literal Offset
Mode” for details.
Decode
Read
literal ‘k’
Process
Data
Write to W
Example 1:
SUBLW 02h
Before Instruction
W
C
=
=
01h
?
After Instruction
W
C
Z
=
01h
=
=
=
1
0
0
; result is positive
N
Words:
Cycles:
1
1
Example 2:
SUBLW 02h
Before Instruction
W
C
=
=
02h
?
Q Cycle Activity:
Q1
Q2
Q3
Q4
After Instruction
Decode
Read
register ‘f’
Process
Data
Write to
destination
W
C
Z
=
00h
=
=
=
1
1
0
; result is zero
N
Example 1:
SUBWF
REG, 1, 0
Before Instruction
Example 3:
SUBLW 02h
REG
W
=
3
2
?
Before Instruction
=
=
W
C
=
=
03h
?
C
After Instruction
After Instruction
REG
W
C
=
1
2
1
0
0
W
C
Z
=
FFh ; (2’s complement)
=
=
=
=
=
=
=
0
0
1
; result is negative
; result is positive
Z
N
N
Example 2:
Before Instruction
SUBWF
REG, 0, 0
REG
W
=
=
=
2
2
?
C
After Instruction
REG
W
C
=
2
0
1
1
0
=
=
=
=
; result is zero
Z
N
Example 3:
Before Instruction
SUBWF
REG, 1, 0
REG
W
=
=
=
1
2
?
C
After Instruction
REG
W
C
=
FFh ;(2’s complement)
2
0
0
1
=
=
=
=
; result is negative
Z
N
© 2008 Microchip Technology Inc.
DS39760D-page 249
PIC18F2450/4450
SUBWFB
Subtract W from f with Borrow
SWAPF
Swap f
Syntax:
SUBWFB f {,d {,a}}
Syntax:
SWAPF f {,d {,a}}
Operands:
0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
Operands:
0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
Operation:
(f) – (W) – (C) → dest
Operation:
(f<3:0>) → dest<7:4>,
(f<7:4>) → dest<3:0>
Status Affected:
Encoding:
N, OV, C, DC, Z
0101
10da
ffff
ffff
Status Affected:
Encoding:
None
Description:
Subtract W and the Carry flag (borrow)
from register ‘f’ (2’s complement
method). If ‘d’ is ‘0’, the result is stored
in W. If ‘d’ is ‘1’, the result is stored back
in register ‘f’ (default).
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank (default).
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f ≤ 95 (5Fh). See
Section 19.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
0011
10da
ffff
ffff
Description:
The upper and lower nibbles of register
‘f’ are exchanged. If ‘d’ is ‘0’, the result
is placed in W. If ‘d’ is ‘1’, the result is
placed in register ‘f’ (default).
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank (default).
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f ≤ 95 (5Fh). See
Section 19.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
Words:
Cycles:
1
1
Words:
Cycles:
1
1
Q Cycle Activity:
Q1
Q Cycle Activity:
Q1
Q2
Read
register ‘f’
Q3
Process
Data
Q4
Decode
Write to
Q2
Q3
Q4
destination
Decode
Read
register ‘f’
Process
Data
Write to
destination
Example 1:
SUBWFB REG, 1, 0
Before Instruction
REG
W
=
=
=
19h
0Dh
1
(0001 1001)
(0000 1101)
Example:
SWAPF
REG, 1, 0
C
Before Instruction
After Instruction
REG
After Instruction
=
53h
35h
REG
W
C
=
0Ch
0Dh
1
(0000 1011)
(0000 1101)
=
=
=
=
REG
=
Z
0
N
0
; result is positive
Example 2:
SUBWFB REG, 0, 0
Before Instruction
REG
W
=
=
=
1Bh
1Ah
0
(0001 1011)
(0001 1010)
C
After Instruction
REG
W
C
=
1Bh
00h
1
(0001 1011)
=
=
=
=
Z
1
; result is zero
N
0
Example 3:
Before Instruction
SUBWFB REG, 1, 0
REG
W
=
=
=
03h
0Eh
1
(0000 0011)
(0000 1101)
C
After Instruction
REG
=
F5h
(1111 0100)
; [2’s comp]
W
C
Z
=
=
=
=
0Eh
0
0
1
(0000 1101)
N
; result is negative
DS39760D-page 250
© 2008 Microchip Technology Inc.
PIC18F2450/4450
TBLRD
Table Read
TBLRD
Example 1:
Before Instruction
Table Read (Continued)
Syntax:
TBLRD ( *; *+; *-; +*)
None
TBLRD *+ ;
Operands:
Operation:
TABLAT
TBLPTR
MEMORY (00A356h)
=
=
=
55h
00A356h
34h
if TBLRD *,
(Prog Mem (TBLPTR)) → TABLAT,
TBLPTR – No Change;
if TBLRD *+,
(Prog Mem (TBLPTR)) → TABLAT,
(TBLPTR) + 1 → TBLPTR;
if TBLRD *-,
(Prog Mem (TBLPTR)) → TABLAT,
(TBLPTR) – 1 → TBLPTR;
if TBLRD +*,
(TBLPTR) + 1 → TBLPTR,
(Prog Mem (TBLPTR)) → TABLAT
After Instruction
TABLAT
TBLPTR
=
=
34h
00A357h
Example 2:
TBLRD +* ;
Before Instruction
TABLAT
TBLPTR
MEMORY (01A357h)
MEMORY (01A358h)
After Instruction
=
=
=
=
AAh
01A357h
12h
34h
TABLAT
TBLPTR
=
=
34h
01A358h
Status Affected: None
Encoding:
0000
0000
0000
10nn
nn=0 *
=1 *+
=2 *-
=3 +*
Description:
This instruction is used to read the contents
of Program Memory (P.M.). To address the
program memory, a pointer called Table
Pointer (TBLPTR) is used.
The TBLPTR (a 21-bit pointer) points to
each byte in the program memory. TBLPTR
has a 2-Mbyte address range.
TBLPTR<0> = 0: Least Significant Byte of
Program Memory Word
TBLPTR<0> = 1: Most Significant Byte of
Program Memory Word
The TBLRDinstruction can modify the value
of TBLPTR as follows:
•
•
•
•
no change
post-increment
post-decrement
pre-increment
Words:
Cycles:
1
2
Q Cycle Activity:
Q1
Q2
No
Q3
No
Q4
Decode
No
operation
operation
operation
No
No operation
No
No operation
(Write
TABLAT)
operation (Read Program operation
Memory)
© 2008 Microchip Technology Inc.
DS39760D-page 251
PIC18F2450/4450
TBLWT
Table Write
TBLWT
Table Write (Continued)
Syntax:
TBLWT ( *; *+; *-; +*)
None
Example 1:
TBLWT *+;
Operands:
Operation:
Before Instruction
if TBLWT*,
TABLAT
TBLPTR
HOLDING REGISTER
(00A356h)
=
=
55h
00A356h
(TABLAT) → Holding Register,
TBLPTR – No Change;
if TBLWT*+,
(TABLAT) → Holding Register,
(TBLPTR) + 1 → TBLPTR;
if TBLWT*-,
(TABLAT) → Holding Register,
(TBLPTR) – 1 → TBLPTR;
if TBLWT+*,
(TBLPTR) + 1 → TBLPTR,
(TABLAT) → Holding Register
=
FFh
After Instructions (table write completion)
TABLAT
TBLPTR
HOLDING REGISTER
(00A356h)
=
=
55h
00A357h
=
55h
Example 2:
TBLWT +*;
Before Instruction
TABLAT
TBLPTR
=
=
34h
01389Ah
HOLDING REGISTER
(01389Ah)
HOLDING REGISTER
(01389Bh)
Status Affected: None
=
FFh
Encoding:
0000
0000
0000
11nn
nn=0 *
=1 *+
=2 *-
=3 +*
=
FFh
After Instruction (table write completion)
TABLAT
TBLPTR
HOLDING REGISTER
(01389Ah)
HOLDING REGISTER
(01389Bh)
=
=
34h
01389Bh
Description:
This instruction uses the 3 LSBs of TBLPTR
to determine which of the 8 holding
registers the TABLAT is written to. The
holding registers are used to program the
contents of Program Memory (P.M.). (Refer
to Section 6.0 “Flash Program Memory”
for additional details on programming Flash
memory.)
=
=
FFh
34h
The TBLPTR (a 21-bit pointer) points to
each byte in the program memory. TBLPTR
has a 2-Mbyte address range. The LSb of
the TBLPTR selects which byte of the
program memory location to access.
TBLPTR<0> = 0: Least Significant Byte of
Program Memory Word
TBLPTR<0> = 1: Most Significant Byte of
Program Memory Word
The TBLWT instruction can modify the
value of TBLPTR as follows:
•
•
•
•
no change
post-increment
post-decrement
pre-increment
Words:
1
2
Cycles:
Q Cycle Activity:
Q1
Q2
No
Q3
No
Q4
No
Decode
operation operation operation
No
No No No
operation operation operation operation
(Read
TABLAT)
(Write to
Holding
Register)
DS39760D-page 252
© 2008 Microchip Technology Inc.
PIC18F2450/4450
TSTFSZ
Test f, Skip if 0
XORLW
Exclusive OR Literal with W
Syntax:
TSTFSZ f {,a}
Syntax:
XORLW k
Operands:
0 ≤ f ≤ 255
a ∈ [0,1]
Operands:
Operation:
Status Affected:
Encoding:
Description:
0 ≤ k ≤ 255
(W) .XOR. k → W
N, Z
Operation:
skip if f = 0
Status Affected:
Encoding:
None
0000
1010
kkkk
kkkk
0110
011a
ffff
ffff
The contents of W are XORed with
the 8-bit literal ‘k’. The result is placed
in W.
Description:
If ‘f’ = 0, the next instruction fetched
during the current instruction execution
is discarded and a NOPis executed,
making this a two-cycle instruction.
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank (default).
Words:
1
1
Cycles:
Q Cycle Activity:
Q1
Q2
Q3
Q4
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f ≤ 95 (5Fh). See
Section 19.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
Decode
Read
literal ‘k’
Process
Data
Write to W
Example:
XORLW
0AFh
Before Instruction
W
=
B5h
1Ah
Words:
Cycles:
1
After Instruction
1(2)
W
=
Note: 3 cycles if skip and followed
by a 2-word instruction.
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
register ‘f’
Process
Data
No
operation
If skip:
Q1
Q2
Q3
Q4
No
No
No
No
operation
operation
operation
operation
If skip and followed by 2-word instruction:
Q1
Q2
Q3
Q4
No
No
No
No
operation
operation
operation
operation
No
No
No
No
operation
operation
operation
operation
Example:
HERE
NZERO
ZERO
TSTFSZ CNT, 1
:
:
Before Instruction
PC
=
Address (HERE)
After Instruction
If CNT
PC
If CNT
PC
=
=
≠
=
00h,
Address (ZERO)
00h,
Address (NZERO)
© 2008 Microchip Technology Inc.
DS39760D-page 253
PIC18F2450/4450
XORWF
Exclusive OR W with f
Syntax:
XORWF f {,d {,a}}
Operands:
0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
Operation:
(W) .XOR. (f) → dest
Status Affected:
Encoding:
N, Z
0001
10da
ffff
ffff
Description:
Exclusive OR the contents of W with
register ‘f’. If ‘d’ is ‘0’, the result is stored
in W. If ‘d’ is ‘1’, the result is stored back
in the register ‘f’ (default).
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank (default).
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f ≤ 95 (5Fh). See
Section 19.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
Words:
Cycles:
1
1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
register ‘f’
Process
Data
Write to
destination
Example:
XORWF
REG, 1, 0
Before Instruction
REG
W
=
=
AFh
B5h
After Instruction
REG
W
=
=
1Ah
B5h
DS39760D-page 254
© 2008 Microchip Technology Inc.
PIC18F2450/4450
A summary of the instructions in the extended
instruction set is provided in Table 19-3. Detailed
descriptions are provided in Section 19.2.2
“Extended Instruction Set”. The opcode field
descriptions in Table 19-1 (page 214) apply to both the
standard and extended PIC18 instruction sets.
19.2 Extended Instruction Set
In addition to the standard 75 instructions of the PIC18
instruction set, PIC18F2450/4450 devices also provide
an optional extension to the core CPU functionality.
The added features include eight additional
instructions that augment indirect and indexed
addressing operations and the implementation of
Indexed Literal Offset Addressing mode for many of the
standard PIC18 instructions.
Note:
The instruction set extension and the
Indexed Literal Offset Addressing mode
were designed for optimizing applications
written in C; the user may likely never use
these instructions directly in assembler.
The syntax for these commands is pro-
vided as a reference for users who may be
reviewing code that has been generated
by a compiler.
The additional features of the extended instruction set
are disabled by default. To enable them, users must set
the XINST Configuration bit.
The instructions in the extended set can all be
classified as literal operations, which either manipulate
the File Select Registers, or use them for Indexed
Addressing. Two of the instructions, ADDFSR and
SUBFSR, each have an additional special instantiation
for using FSR2. These versions (ADDULNK and
SUBULNK) allow for automatic return after execution.
19.2.1
EXTENDED INSTRUCTION SYNTAX
Most of the extended instructions use indexed
arguments, using one of the File Select Registers and
some offset to specify a source or destination register.
When an argument for an instruction serves as part of
Indexed Addressing, it is enclosed in square brackets
(“[ ]”). This is done to indicate that the argument is used
as an index or offset. The MPASM™ Assembler will
flag an error if it determines that an index or offset value
is not bracketed.
The extended instructions are specifically implemented
to optimize re-entrant program code (that is, code that
is recursive or that uses a software stack) written in
high-level languages, particularly C. Among other
things, they allow users working in high-level
languages to perform certain operations on data
structures more efficiently. These include:
When the extended instruction set is enabled, brackets
are also used to indicate index arguments in byte-
oriented and bit-oriented instructions. This is in addition
to other changes in their syntax. For more details, see
Section 19.2.3.1 “Extended Instruction Syntax with
Standard PIC18 Commands”.
• Dynamic allocation and deallocation of software
stack space when entering and leaving
subroutines
• Function Pointer invocation
• Software Stack Pointer manipulation
• Manipulation of variables located in a software
stack
Note:
In the past, square brackets have been
used to denote optional arguments in the
PIC18 and earlier instruction sets. In this
text and going forward, optional
arguments are denoted by braces (“{ }”).
TABLE 19-3: EXTENSIONS TO THE PIC18 INSTRUCTION SET
16-Bit Instruction Word
MSb LSb
Mnemonic,
Operands
Status
Affected
Description
Cycles
ADDFSR
ADDULNK
CALLW
f, k
k
Add Literal to FSR
Add Literal to FSR2 and Return
Call Subroutine using WREG
1
2
2
2
1110 1000 ffkk kkkk
1110 1000 11kk kkkk
0000 0000 0001 0100
1110 1011 0zzz zzzz
1111 ffff ffff ffff
1110 1011 1zzz zzzz
1111 xxxx xzzz zzzz
1110 1010 kkkk kkkk
None
None
None
None
MOVSF
zs, fd Move zs (source) to 1st word
fd (destination) 2nd word
zs, zd Move zs (source) to 1st word
zd (destination) 2nd word
MOVSS
PUSHL
2
1
None
None
k
Store Literal at FSR2,
Decrement FSR2
SUBFSR
SUBULNK
f, k
k
Subtract Literal from FSR
Subtract Literal from FSR2 and
Return
1
2
1110 1001 ffkk kkkk
1110 1001 11kk kkkk
None
None
© 2008 Microchip Technology Inc.
DS39760D-page 255
PIC18F2450/4450
19.2.2
EXTENDED INSTRUCTION SET
ADDFSR
Add Literal to FSR
ADDULNK
Add Literal to FSR2 and Return
Syntax:
ADDFSR f, k
Syntax:
ADDULNK k
Operands:
0 ≤ k ≤ 63
f ∈ [ 0, 1, 2 ]
Operands:
Operation:
0 ≤ k ≤ 63
FSR2 + k → FSR2,
(TOS) → PC
None
Operation:
FSR(f) + k → FSR(f)
Status Affected:
Encoding:
None
Status Affected:
Encoding:
1110
1000
ffkk
kkkk
1110
1000
11kk
kkkk
Description:
The 6-bit literal ‘k’ is added to the
contents of the FSR specified by ‘f’.
Description:
The 6-bit literal ‘k’ is added to the
contents of FSR2. A RETURNis then
executed by loading the PC with the
TOS.
Words:
1
1
Cycles:
The instruction takes two cycles to
execute; a NOPis performed during
the second cycle.
This may be thought of as a special
case of the ADDFSRinstruction,
where f = 3 (binary ‘11’); it operates
only on FSR2.
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
literal ‘k’
Process
Data
Write to
FSR
Example:
ADDFSR 2, 23h
Words:
1
2
Before Instruction
FSR2
After Instruction
FSR2
Cycles:
=
03FFh
0422h
Q Cycle Activity:
Q1
Q2
Q3
Q4
=
Decode
Read
Process
Data
Write to
FSR
literal ‘k’
No
No
No
No
Operation
Operation
Operation
Operation
Example:
ADDULNK 23h
Before Instruction
FSR2
PC
=
=
03FFh
0100h
After Instruction
FSR2
PC
=
=
0422h
(TOS)
Note:
All PIC18 instructions may take an optional label argument preceding the instruction mnemonic for use in
symbolic addressing. If a label is used, the instruction syntax then becomes: {label} instruction argument(s).
DS39760D-page 256
© 2008 Microchip Technology Inc.
PIC18F2450/4450
CALLW
Subroutine Call Using WREG
MOVSF
Move Indexed to f
Syntax:
CALLW
None
Syntax:
MOVSF [z ], f
s
d
Operands:
Operation:
Operands:
0 ≤ z ≤ 127
s
0 ≤ f ≤ 4095
d
(PC + 2) → TOS,
(W) → PCL,
Operation:
((FSR2) + z ) → f
s
d
(PCLATH) → PCH,
(PCLATU) → PCU
Status Affected:
None
Encoding:
1st word (source)
2nd word (destin.)
Status Affected:
Encoding:
None
1110
1111
1011
ffff
0zzz
ffff
zzzz
ffff
s
d
0000
0000
0001
0100
Description
First, the return address (PC + 2) is
pushed onto the return stack. Next, the
contents of W are written to PCL; the
existing value is discarded. Then the
contents of PCLATH and PCLATU are
latched into PCH and PCU,
respectively. The second cycle is
executed as a NOPinstruction while the
new next instruction is fetched.
Description:
The contents of the source register are
moved to destination register ‘f ’. The
d
actual address of the source register is
determined by adding the 7-bit literal
offset ‘z ’ in the first word to the value of
s
FSR2. The address of the destination
register is specified by the 12-bit literal
‘f ’ in the second word. Both addresses
d
can be anywhere in the 4096-byte data
space (000h to FFFh).
The MOVSFinstruction cannot use the
PCL, TOSU, TOSH or TOSL as the
destination register.
If the resultant source address points to
an indirect addressing register, the
value returned will be 00h.
Unlike CALL, there is no option to
update W, STATUS or BSR.
Words:
Cycles:
1
2
Q Cycle Activity:
Q1
Q2
Q3
Q4
Words:
Cycles:
2
2
Decode
Read
WREG
Push PC to
stack
No
operation
No
operation
No
operation
No
operation
No
operation
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Determine
Determine
Read
source addr source addr source reg
Example:
HERE
CALLW
Decode
No
operation
No
operation
Write
register ‘f’
(dest)
Before Instruction
PC
=
address (HERE)
PCLATH =
PCLATU =
10h
00h
06h
No dummy
read
W
=
After Instruction
PC
=
001006h
Example:
MOVSF
[05h], REG2
TOS
=
address (HERE + 2)
PCLATH =
PCLATU =
W
10h
00h
06h
Before Instruction
FSR2
=
80h
33h
=
Contents
of 85h
REG2
=
=
11h
After Instruction
FSR2
=
80h
Contents
of 85h
REG2
=
=
33h
33h
© 2008 Microchip Technology Inc.
DS39760D-page 257
PIC18F2450/4450
MOVSS
Move Indexed to Indexed
PUSHL
Store Literal at FSR2, Decrement FSR2
Syntax:
MOVSS [z ], [z ]
Syntax:
PUSHL k
s
d
Operands:
0 ≤ z ≤ 127
s
Operands:
Operation:
0 ≤ k ≤ 255
0 ≤ z ≤ 127
d
k → (FSR2),
FSR2 – 1→ FSR2
Operation:
((FSR2) + z ) → ((FSR2) + z )
s d
Status Affected:
None
Status Affected: None
Encoding:
1st word (source)
2nd word (dest.)
Encoding:
1111
1010
kkkk
kkkk
1110
1111
1011
xxxx
1zzz
xzzz
zzzz
zzzz
s
d
Description:
The 8-bit literal ‘k’ is written to the data
memory address specified by FSR2. FSR2
is decremented by ‘1’ after the operation.
This instruction allows users to push values
onto a software stack.
Description
The contents of the source register are
moved to the destination register. The
addresses of the source and destination
registers are determined by adding the
7-bit literal offsets ‘z ’ or ‘z ’,
Words:
Cycles:
1
1
s
d
respectively, to the value of FSR2. Both
registers can be located anywhere in
the 4096-byte data memory space
(000h to FFFh).
Q Cycle Activity:
Q1
Q2
Q3
Q4
The MOVSSinstruction cannot use the
PCL, TOSU, TOSH or TOSL as the
destination register.
Decode
Read ‘k’
Process
data
Write to
destination
If the resultant source address points to
an indirect addressing register, the
value returned will be 00h. If the
resultant destination address points to
an indirect addressing register, the
instruction will execute as a NOP.
Example:
PUSHL 08h
Before Instruction
FSR2H:FSR2L
Memory (01ECh)
=
=
01ECh
00h
After Instruction
Words:
2
2
FSR2H:FSR2L
Memory (01ECh)
=
=
01EBh
08h
Cycles:
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Determine
Determine
Read
source addr source addr source reg
Decode
Determine
dest addr
Determine
dest addr
Write
to dest reg
Example:
MOVSS [05h], [06h]
Before Instruction
FSR2
=
=
=
80h
33h
11h
Contents
of 85h
Contents
of 86h
After Instruction
FSR2
Contents
of 85h
Contents
of 86h
=
=
=
80h
33h
33h
DS39760D-page 258
© 2008 Microchip Technology Inc.
PIC18F2450/4450
SUBFSR
Subtract Literal from FSR
SUBULNK
Subtract Literal from FSR2 and Return
Syntax:
SUBFSR f, k
0 ≤ k ≤ 63
Syntax:
SUBULNK k
Operands:
Operands:
Operation:
0 ≤ k ≤ 63
f ∈ [ 0, 1, 2 ]
FSRf – k → FSRf
None
FSR2 – k → FSR2,
(TOS) → PC
Operation:
Status Affected:
Encoding:
Status Affected: None
1110
1001
ffkk
kkkk
Encoding:
1110
1001
11kk
kkkk
Description:
The 6-bit literal ‘k’ is subtracted from
the contents of the FSR specified by
‘f’.
Description:
The 6-bit literal ‘k’ is subtracted from the
contents of the FSR2. A RETURNis then
executed by loading the PC with the TOS.
The instruction takes two cycles to
execute; a NOPis performed during the
second cycle.
This may be thought of as a special case of
the SUBFSRinstruction, where f = 3 (binary
‘11’); it operates only on FSR2.
Words:
1
1
Cycles:
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
register ‘f’
Process
Data
Write to
destination
Words:
1
2
Cycles:
Q Cycle Activity:
Q1
Example:
SUBFSR 2, 23h
03FFh
Q2
Q3
Q4
Before Instruction
FSR2
After Instruction
FSR2
Decode
Read
register ‘f’
Process
Data
Write to
destination
=
No
Operation
No
Operation
No
Operation
No
Operation
=
03DCh
Example:
SUBULNK 23h
Before Instruction
FSR2
PC
=
=
03FFh
0100h
After Instruction
FSR2
PC
=
=
03DCh
(TOS)
© 2008 Microchip Technology Inc.
DS39760D-page 259
PIC18F2450/4450
19.2.3
BYTE-ORIENTED AND
BIT-ORIENTED INSTRUCTIONS IN
INDEXED LITERAL OFFSET MODE
19.2.3.1
Extended Instruction Syntax with
Standard PIC18 Commands
When the extended instruction set is enabled, the file
register argument, ‘f’, in the standard byte-oriented and
bit-oriented commands is replaced with the literal offset
value, ‘k’. As already noted, this occurs only when ‘f’ is
less than or equal to 5Fh. When an offset value is used,
it must be indicated by square brackets (“[ ]”). As with
the extended instructions, the use of brackets indicates
to the compiler that the value is to be interpreted as an
index or an offset. Omitting the brackets, or using a
value greater than 5Fh within brackets, will generate an
error in the MPASM Assembler.
Note: Enabling the PIC18 instruction set
extension may cause legacy applications
to behave erratically or fail entirely.
In addition to eight new commands in the extended set,
enabling the extended instruction set also enables
Indexed Literal Offset Addressing mode (Section 5.6.1
“Indexed Addressing with Literal Offset”). This has
a significant impact on the way that many commands of
the standard PIC18 instruction set are interpreted.
When the extended set is disabled, addresses
embedded in opcodes are treated as literal memory
locations: either as a location in the Access Bank
(‘a’ = 0) or in a GPR bank designated by the BSR
(‘a’ = 1). When the extended instruction set is enabled
and ‘a’ = 0, however, a file register argument of 5Fh or
less is interpreted as an offset from the pointer value in
FSR2 and not as a literal address. For practical
purposes, this means that all instructions that use the
Access RAM bit as an argument – that is, all byte-
oriented and bit-oriented instructions, or almost half of
the core PIC18 instructions – may behave differently
when the extended instruction set is enabled.
If the index argument is properly bracketed for Indexed
Literal Offset Addressing mode, the Access RAM
argument is never specified; it will automatically be
assumed to be ‘0’. This is in contrast to standard
operation (extended instruction set disabled) when ‘a’
is set on the basis of the target address. Declaring the
Access RAM bit in this mode will also generate an error
in the MPASM Assembler.
The destination argument, ‘d’, functions as before.
In the latest versions of the MPASM assembler,
language support for the extended instruction set must
be explicitly invoked. This is done with either the
command line option, /y, or the PE directive in the
source listing.
When the content of FSR2 is 00h, the boundaries of the
Access RAM are essentially remapped to their original
values. This may be useful in creating backward
compatible code. If this technique is used, it may be
necessary to save the value of FSR2 and restore it
when moving back and forth between C and assembly
routines in order to preserve the Stack Pointer. Users
must also keep in mind the syntax requirements of the
extended instruction set (see Section 19.2.3.1
“Extended Instruction Syntax with Standard PIC18
Commands”).
19.2.4
CONSIDERATIONS WHEN
ENABLING THE EXTENDED
INSTRUCTION SET
It is important to note that the extensions to the
instruction set may not be beneficial to all users. In
particular, users who are not writing code that uses a
software stack may not benefit from using the
extensions to the instruction set.
Although the Indexed Literal Offset Addressing mode
can be very useful for dynamic stack and pointer
manipulation, it can also be very annoying if a simple
arithmetic operation is carried out on the wrong
register. Users who are accustomed to the PIC18
programming must keep in mind that, when the
extended instruction set is enabled, register addresses
of 5Fh or less are used for Indexed Literal Offset
Addressing.
Additionally, the Indexed Literal Offset Addressing
mode may create issues with legacy applications
written to the PIC18 assembler. This is because
instructions in the legacy code may attempt to address
registers in the Access Bank below 5Fh. Since these
addresses are interpreted as literal offsets to FSR2
when the instruction set extension is enabled, the
application may read or write to the wrong data
addresses.
Representative examples of typical byte-oriented and
bit-oriented instructions in the Indexed Literal Offset
Addressing mode are provided on the following page to
show how execution is affected. The operand
conditions shown in the examples are applicable to all
instructions of these types.
When porting an application to the PIC18F2450/4450,
it is very important to consider the type of code. A large,
re-entrant application that is written in ‘C’ and would
benefit from efficient compilation will do well when
using the instruction set extensions. Legacy applica-
tions that heavily use the Access Bank will most likely
not benefit from using the extended instruction set.
DS39760D-page 260
© 2008 Microchip Technology Inc.
PIC18F2450/4450
ADD W to Indexed
(Indexed Literal Offset mode)
Bit Set Indexed
(Indexed Literal Offset mode)
ADDWF
BSF
Syntax:
ADDWF
[k] {,d}
Syntax:
BSF [k], b
Operands:
0 ≤ k ≤ 95
d ∈ [0,1]
Operands:
0 ≤ f ≤ 95
0 ≤ b ≤ 7
Operation:
(W) + ((FSR2) + k) → dest
Operation:
1 → ((FSR2) + k)<b>
Status Affected:
Encoding:
N, OV, C, DC, Z
Status Affected:
Encoding:
None
1000
0010
01d0
kkkk
kkkk
bbb0
kkkk
kkkk
Description:
The contents of W are added to the
contents of the register indicated by
FSR2, offset by the value ‘k’.
If ‘d’ is ‘0’, the result is stored in W. If ‘d’
is ‘1’, the result is stored back in
register ‘f’ (default).
Description:
Bit ‘b’ of the register indicated by FSR2,
offset by the value ‘k’, is set.
Words:
Cycles:
1
1
Q Cycle Activity:
Q1
Words:
Cycles:
1
1
Q2
Q3
Q4
Decode
Read
register ‘f’
Process
Data
Write to
destination
Q Cycle Activity:
Q1
Q2
Q3
Q4
Example:
BSF
[FLAG_OFST], 7
Decode
Read ‘k’
Process
Data
Write to
destination
Before Instruction
FLAG_OFST
FSR2
Contents
of 0A0Ah
=
=
0Ah
0A00h
Example:
ADDWF
[OFST],0
=
55h
D5h
Before Instruction
After Instruction
W
OFST
FSR2
=
=
=
17h
Contents
of 0A0Ah
2Ch
=
0A00h
Contents
of 0A2Ch
=
20h
After Instruction
W
=
=
37h
20h
Contents
of 0A2Ch
Set Indexed
(Indexed Literal Offset mode)
SETF
Syntax:
SETF [k]
Operands:
Operation:
Status Affected:
Encoding:
Description:
0 ≤ k ≤ 95
FFh → ((FSR2) + k)
None
0110
1000
kkkk
kkkk
The contents of the register indicated by
FSR2, offset by ‘k’, are set to FFh.
Words:
Cycles:
1
1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read ‘k’
Process
Data
Write
register
Example:
SETF
[OFST]
2Ch
Before Instruction
OFST
FSR2
=
=
0A00h
Contents
of 0A2Ch
=
00h
After Instruction
Contents
of 0A2Ch
=
FFh
© 2008 Microchip Technology Inc.
DS39760D-page 261
PIC18F2450/4450
To develop software for the extended instruction set,
the user must enable support for the instructions and
the Indexed Addressing mode in their language tool(s).
Depending on the environment being used, this may be
done in several ways:
19.2.5
SPECIAL CONSIDERATIONS WITH
MICROCHIP MPLAB® IDE TOOLS
The latest versions of Microchip’s software tools have
been designed to fully support the extended instruction
set of the PIC18F2450/4450 family of devices. This
includes the MPLAB C18
Assembly language and
Development Environment (IDE).
• A menu option, or dialog box within the
environment, that allows the user to configure the
language tool and its settings for the project
C
compiler, MPASM
MPLAB Integrated
• A command line option
When selecting target device for software
a
• A directive in the source code
development, MPLAB IDE will automatically set default
Configuration bits for that device. The default setting for
the XINST Configuration bit is ‘0’, disabling the
extended instruction set and Indexed Literal Offset
Addressing mode. For proper execution of applications
developed to take advantage of the extended
instruction set, XINST must be set during
programming.
These options vary between different compilers,
assemblers and development environments. Users are
encouraged to review the documentation accompany-
ing their development systems for the appropriate
information.
DS39760D-page 262
© 2008 Microchip Technology Inc.
PIC18F2450/4450
20.1 MPLAB Integrated Development
Environment Software
20.0 DEVELOPMENT SUPPORT
The PIC® microcontrollers are supported with a full
range of hardware and software development tools:
The MPLAB IDE software brings an ease of software
development previously unseen in the 8/16-bit micro-
controller market. The MPLAB IDE is a Windows®
operating system-based application that contains:
• Integrated Development Environment
- MPLAB® IDE Software
• Assemblers/Compilers/Linkers
- MPASMTM Assembler
• A single graphical interface to all debugging tools
- Simulator
- MPLAB C18 and MPLAB C30 C Compilers
- MPLINKTM Object Linker/
MPLIBTM Object Librarian
- Programmer (sold separately)
- Emulator (sold separately)
- In-Circuit Debugger (sold separately)
• A full-featured editor with color-coded context
• A multiple project manager
- MPLAB ASM30 Assembler/Linker/Library
• Simulators
- MPLAB SIM Software Simulator
• Emulators
• Customizable data windows with direct edit of
contents
- MPLAB ICE 2000 In-Circuit Emulator
- MPLAB REAL ICE™ In-Circuit Emulator
• In-Circuit Debugger
• High-level source code debugging
• Visual device initializer for easy register
initialization
- MPLAB ICD 2
• Mouse over variable inspection
• Device Programmers
• Drag and drop variables from source to watch
windows
- PICSTART® Plus Development Programmer
- MPLAB PM3 Device Programmer
- PICkit™ 2 Development Programmer
• Extensive on-line help
• Integration of select third party tools, such as
HI-TECH Software C Compilers and IAR
C Compilers
• Low-Cost Demonstration and Development
Boards and Evaluation Kits
The MPLAB IDE allows you to:
• Edit your source files (either assembly or C)
• One touch assemble (or compile) and download
to PIC MCU emulator and simulator tools
(automatically updates all project information)
• Debug using:
- Source files (assembly or C)
- Mixed assembly and C
- Machine code
MPLAB IDE supports multiple debugging tools in a
single development paradigm, from the cost-effective
simulators, through low-cost in-circuit debuggers, to
full-featured emulators. This eliminates the learning
curve when upgrading to tools with increased flexibility
and power.
© 2008 Microchip Technology Inc.
DS39760D-page 263
PIC18F2450/4450
20.2 MPASM Assembler
20.5 MPLAB ASM30 Assembler, Linker
and Librarian
The MPASM Assembler is a full-featured, universal
macro assembler for all PIC MCUs.
MPLAB ASM30 Assembler produces relocatable
machine code from symbolic assembly language for
dsPIC30F devices. MPLAB C30 C Compiler uses the
assembler to produce its object file. The assembler
generates relocatable object files that can then be
archived or linked with other relocatable object files and
archives to create an executable file. Notable features
of the assembler include:
The MPASM Assembler generates relocatable object
files for the MPLINK Object Linker, Intel® standard HEX
files, MAP files to detail memory usage and symbol
reference, absolute LST files that contain source lines
and generated machine code and COFF files for
debugging.
The MPASM Assembler features include:
• Integration into MPLAB IDE projects
• Support for the entire dsPIC30F instruction set
• Support for fixed-point and floating-point data
• Command line interface
• User-defined macros to streamline
assembly code
• Rich directive set
• Conditional assembly for multi-purpose
source files
• Flexible macro language
• MPLAB IDE compatibility
• Directives that allow complete control over the
assembly process
20.6 MPLAB SIM Software Simulator
20.3 MPLAB C18 and MPLAB C30
C Compilers
The MPLAB SIM Software Simulator allows code
development in a PC-hosted environment by simulat-
ing the PIC MCUs and dsPIC® DSCs on an instruction
level. On any given instruction, the data areas can be
examined or modified and stimuli can be applied from
a comprehensive stimulus controller. Registers can be
logged to files for further run-time analysis. The trace
buffer and logic analyzer display extend the power of
the simulator to record and track program execution,
actions on I/O, most peripherals and internal registers.
The MPLAB C18 and MPLAB C30 Code Development
Systems are complete ANSI
C
compilers for
Microchip’s PIC18 and PIC24 families of microcontrol-
lers and the dsPIC30 and dsPIC33 family of digital sig-
nal controllers. These compilers provide powerful
integration capabilities, superior code optimization and
ease of use not found with other compilers.
For easy source level debugging, the compilers provide
symbol information that is optimized to the MPLAB IDE
debugger.
The MPLAB SIM Software Simulator fully supports
symbolic debugging using the MPLAB C18 and
MPLAB C30 C Compilers, and the MPASM and
MPLAB ASM30 Assemblers. The software simulator
offers the flexibility to develop and debug code outside
of the hardware laboratory environment, making it an
excellent, economical software development tool.
20.4 MPLINK Object Linker/
MPLIB Object Librarian
The MPLINK Object Linker combines relocatable
objects created by the MPASM Assembler and the
MPLAB C18 C Compiler. It can link relocatable objects
from precompiled libraries, using directives from a
linker script.
The MPLIB Object Librarian manages the creation and
modification of library files of precompiled code. When
a routine from a library is called from a source file, only
the modules that contain that routine will be linked in
with the application. This allows large libraries to be
used efficiently in many different applications.
The object linker/library features include:
• Efficient linking of single libraries instead of many
smaller files
• Enhanced code maintainability by grouping
related modules together
• Flexible creation of libraries with easy module
listing, replacement, deletion and extraction
DS39760D-page 264
© 2008 Microchip Technology Inc.
PIC18F2450/4450
20.7 MPLAB ICE 2000
High-Performance
20.9 MPLAB ICD 2 In-Circuit Debugger
Microchip’s In-Circuit Debugger, MPLAB ICD 2, is a
powerful, low-cost, run-time development tool,
connecting to the host PC via an RS-232 or high-speed
USB interface. This tool is based on the Flash PIC
MCUs and can be used to develop for these and other
PIC MCUs and dsPIC DSCs. The MPLAB ICD 2 utilizes
the in-circuit debugging capability built into the Flash
devices. This feature, along with Microchip’s In-Circuit
Serial ProgrammingTM (ICSPTM) protocol, offers cost-
effective, in-circuit Flash debugging from the graphical
user interface of the MPLAB Integrated Development
Environment. This enables a designer to develop and
debug source code by setting breakpoints, single step-
ping and watching variables, and CPU status and
peripheral registers. Running at full speed enables
testing hardware and applications in real time. MPLAB
ICD 2 also serves as a development programmer for
selected PIC devices.
In-Circuit Emulator
The MPLAB ICE 2000 In-Circuit Emulator is intended
to provide the product development engineer with a
complete microcontroller design tool set for PIC
microcontrollers. Software control of the MPLAB ICE
2000 In-Circuit Emulator is advanced by the MPLAB
Integrated Development Environment, which allows
editing, building, downloading and source debugging
from a single environment.
The MPLAB ICE 2000 is a full-featured emulator
system with enhanced trace, trigger and data monitor-
ing features. Interchangeable processor modules allow
the system to be easily reconfigured for emulation of
different processors. The architecture of the MPLAB
ICE 2000 In-Circuit Emulator allows expansion to
support new PIC microcontrollers.
The MPLAB ICE 2000 In-Circuit Emulator system has
been designed as a real-time emulation system with
advanced features that are typically found on more
expensive development tools. The PC platform and
Microsoft® Windows® 32-bit operating system were
chosen to best make these features available in a
simple, unified application.
20.10 MPLAB PM3 Device Programmer
The MPLAB PM3 Device Programmer is a universal,
CE compliant device programmer with programmable
voltage verification at VDDMIN and VDDMAX for
maximum reliability. It features a large LCD display
(128 x 64) for menus and error messages and a modu-
lar, detachable socket assembly to support various
package types. The ICSP™ cable assembly is included
as a standard item. In Stand-Alone mode, the MPLAB
PM3 Device Programmer can read, verify and program
PIC devices without a PC connection. It can also set
code protection in this mode. The MPLAB PM3
connects to the host PC via an RS-232 or USB cable.
The MPLAB PM3 has high-speed communications and
optimized algorithms for quick programming of large
memory devices and incorporates an SD/MMC card for
file storage and secure data applications.
20.8 MPLAB REAL ICE In-Circuit
Emulator System
MPLAB REAL ICE In-Circuit Emulator System is
Microchip’s next generation high-speed emulator for
Microchip Flash DSC and MCU devices. It debugs and
programs PIC® Flash MCUs and dsPIC® Flash DSCs
with the easy-to-use, powerful graphical user interface of
the MPLAB Integrated Development Environment (IDE),
included with each kit.
The MPLAB REAL ICE probe is connected to the design
engineer’s PC using a high-speed USB 2.0 interface and
is connected to the target with either a connector
compatible with the popular MPLAB ICD 2 system
(RJ11) or with the new high-speed, noise tolerant, Low-
Voltage Differential Signal (LVDS) interconnection
(CAT5).
MPLAB REAL ICE is field upgradeable through future
firmware downloads in MPLAB IDE. In upcoming
releases of MPLAB IDE, new devices will be supported,
and new features will be added, such as software break-
points and assembly code trace. MPLAB REAL ICE
offers significant advantages over competitive emulators
including low-cost, full-speed emulation, real-time
variable watches, trace analysis, complex breakpoints, a
ruggedized probe interface and long (up to three meters)
interconnection cables.
© 2008 Microchip Technology Inc.
DS39760D-page 265
PIC18F2450/4450
20.11 PICSTART Plus Development
Programmer
20.13 Demonstration, Development and
Evaluation Boards
The PICSTART Plus Development Programmer is an
easy-to-use, low-cost, prototype programmer. It
connects to the PC via a COM (RS-232) port. MPLAB
Integrated Development Environment software makes
using the programmer simple and efficient. The
PICSTART Plus Development Programmer supports
most PIC devices in DIP packages up to 40 pins.
Larger pin count devices, such as the PIC16C92X and
PIC17C76X, may be supported with an adapter socket.
The PICSTART Plus Development Programmer is CE
compliant.
A wide variety of demonstration, development and
evaluation boards for various PIC MCUs and dsPIC
DSCs allows quick application development on fully func-
tional systems. Most boards include prototyping areas for
adding custom circuitry and provide application firmware
and source code for examination and modification.
The boards support a variety of features, including LEDs,
temperature sensors, switches, speakers, RS-232
interfaces, LCD displays, potentiometers and additional
EEPROM memory.
The demonstration and development boards can be
used in teaching environments, for prototyping custom
circuits and for learning about various microcontroller
applications.
20.12 PICkit 2 Development Programmer
The PICkit™ 2 Development Programmer is a low-cost
programmer and selected Flash device debugger with
an easy-to-use interface for programming many of
Microchip’s baseline, mid-range and PIC18F families of
Flash memory microcontrollers. The PICkit 2 Starter Kit
includes a prototyping development board, twelve
sequential lessons, software and HI-TECH’s PICC™
Lite C compiler, and is designed to help get up to speed
quickly using PIC® microcontrollers. The kit provides
everything needed to program, evaluate and develop
applications using Microchip’s powerful, mid-range
Flash memory family of microcontrollers.
In addition to the PICDEM™ and dsPICDEM™ demon-
stration/development board series of circuits, Microchip
has a line of evaluation kits and demonstration software
®
for analog filter design, KEELOQ security ICs, CAN,
IrDA®, PowerSmart battery management, SEEVAL®
evaluation system, Sigma-Delta ADC, flow rate
sensing, plus many more.
Check the Microchip web page (www.microchip.com)
for the complete list of demonstration, development
and evaluation kits.
DS39760D-page 266
© 2008 Microchip Technology Inc.
PIC18F2450/4450
21.0 ELECTRICAL CHARACTERISTICS
(†)
Absolute Maximum Ratings
Ambient temperature under bias...............................................................................................................-40°C to +85°C
Storage temperature .............................................................................................................................. -65°C to +150°C
Voltage on any pin with respect to VSS (except VDD and MCLR) ................................................... -0.3V to (VDD + 0.3V)
Voltage on VDD with respect to VSS ......................................................................................................... -0.3V to +7.5V
Voltage on MCLR with respect to VSS (Note 2) ......................................................................................... 0V to +13.25V
Total power dissipation (Note 1) ...............................................................................................................................1.0W
Maximum current out of VSS pin ...........................................................................................................................300 mA
Maximum current into VDD pin ..............................................................................................................................250 mA
Input clamp current, IIK (VI < 0 or VI > VDD)...................................................................................................................... ±20 mA
Output clamp current, IOK (VO < 0 or VO > VDD) .............................................................................................................. ±20 mA
Maximum output current sunk by any I/O pin..........................................................................................................25 mA
Maximum output current sourced by any I/O pin ....................................................................................................25 mA
Maximum current sunk by all ports .......................................................................................................................200 mA
Maximum current sourced by all ports ..................................................................................................................200 mA
Note 1: Power dissipation is calculated as follows:
Pdis = VDD x {IDD – ∑ IOH} + ∑ {(VDD – VOH) x IOH} + ∑(VOL x IOL)
2: Voltage spikes below VSS at the MCLR/VPP/RE3 pin, inducing currents greater than 80 mA, may cause
latch-up. Thus, a series resistor of 50-100Ω should be used when applying a “low” level to the MCLR/VPP/
RE3 pin, rather than pulling this pin directly to VSS.
† NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at those or any other conditions above those
indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for
extended periods may affect device reliability.
© 2008 Microchip Technology Inc.
DS39760D-page 267
PIC18F2450/4450
FIGURE 21-1:
PIC18F2450/4450 VOLTAGE-FREQUENCY GRAPH (INDUSTRIAL)
6.0V
5.5V
5.0V
4.5V
4.0V
PIC18F2450/4450
4.2V
3.5V
3.0V
2.5V
2.0V
48 MHz
Frequency
FIGURE 21-2:
PIC18LF2450/4450 VOLTAGE-FREQUENCY GRAPH (INDUSTRIAL)
6.0V
5.5V
5.0V
4.5V
4.0V
PIC18LF2450/4450
4.2V
3.5V
3.0V
2.5V
2.0V
40 MHz
48 MHz
4 MHz
Frequency
For 2.0V ≤ VDD < 4.2V: FMAX = (16.36 MHz/V) (VDDAPPMIN – 2.0V) + 4 MHz
For 4.2V ≤ VDD: FMAX = 48 MHz
Note: VDDAPPMIN is the minimum voltage of the PIC® device in the application.
DS39760D-page 268
© 2008 Microchip Technology Inc.
PIC18F2450/4450
21.1 DC Characteristics: Supply Voltage
PIC18F2450/4450 (Industrial)
PIC18LF2450/4450 (Industrial)
PIC18LF2450/4450
Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C ≤ TA ≤ +85°C for industrial
(Industrial)
PIC18F2450/4450
Standard Operating Conditions (unless otherwise stated)
(Industrial)
Operating temperature
-40°C ≤ TA ≤ +85°C for industrial
Param
Symbol
No.
Characteristic
Supply Voltage
Min Typ Max Units
Conditions
D001
VDD
2.0
3.0
—
—
5.5
5.5
V
V
EC, HS, XT and Internal Oscillator modes
HSPLL, XTPLL, ECPIO and ECPLL
Oscillator modes
D002
D003
VDR
RAM Data Retention
Voltage
1.5
—
—
—
—
V
V
(1)
VPOR
VDD Start Voltage
to ensure internal Power-on
Reset signal
0.7
See Section 4.3 “Power-on Reset (POR)”
for details
D004
D005
SVDD
VBOR
VDD Rise Rate
to Ensure Internal Power-on
Reset Signal
0.05
—
—
V/ms See Section 4.3 “Power-on Reset (POR)”
for details
Brown-out Reset Voltage
BORV1:BORV0 = 11
BORV1:BORV0 = 10
BORV1:BORV0 = 01
BORV1:BORV0 = 00
2.00 2.11 2.22
2.65 2.79 2.93
4.11 4.33 4.55
4.36 4.59 4.82
V
V
V
V
Legend: Shading of rows is to assist in readability of the table.
Note 1: This is the limit to which VDD can be lowered in Sleep mode, or during a device Reset, without losing RAM data.
© 2008 Microchip Technology Inc.
DS39760D-page 269
PIC18F2450/4450
21.2 DC Characteristics: Power-Down and Supply Current
PIC18F2450/4450 (Industrial)
PIC18LF2450/4450 (Industrial)
PIC18LF2450/4450
Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C ≤ TA ≤ +85°C for industrial
(Industrial)
PIC18F2450/4450
Standard Operating Conditions (unless otherwise stated)
(Industrial)
Operating temperature
-40°C ≤ TA ≤ +85°C for industrial
Param
No.
Device
Typ Max Units
Conditions
(1)
Power-Down Current (IPD)
PIC18LF2450/4450 0.1
0.95
1.0
5.0
1.4
2.0
8.0
19
μA
μA
μA
μA
μA
μA
μA
μA
μA
-40°C
+25°C
+85°C
-40°C
+25°C
+85°C
-40°C
+25°C
+85°C
VDD = 2.0V
(Sleep mode)
0.1
0.1
PIC18LF2450/4450 0.1
VDD = 3.0V
(Sleep mode)
0.1
1.5
All devices 0.1
VDD = 5.0V
(Sleep mode)
0.1
2.5
2.0
15
Legend: Shading of rows is to assist in readability of the table.
Note 1: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured
with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS and all features that
add delta current disabled (such as WDT, Timer1 Oscillator, BOR, etc.).
2: The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin
loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have
an impact on the current consumption.
The test conditions for all IDD measurements in active operation mode are:
OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD or VSS;
MCLR = VDD; WDT enabled/disabled as specified.
3: Standard low-cost 32 kHz crystals have an operating temperature range of -10°C to +70°C. Extended
temperature crystals are available at a much higher cost.
4: BOR and HLVD enable internal band gap reference. With both modules enabled, current consumption will be
less than the sum of both specifications.
DS39760D-page 270
© 2008 Microchip Technology Inc.
PIC18F2450/4450
21.2 DC Characteristics: Power-Down and Supply Current
PIC18F2450/4450 (Industrial)
PIC18LF2450/4450 (Industrial) (Continued)
PIC18LF2450/4450
Standard Operating Conditions (unless otherwise stated)
(Industrial)
Operating temperature
-40°C ≤ TA ≤ +85°C for industrial
PIC18F2450/4450
Standard Operating Conditions (unless otherwise stated)
(Industrial)
Operating temperature
Typ Max Units
-40°C ≤ TA ≤ +85°C for industrial
Param
No.
Device
Conditions
(2)
Supply Current (IDD)
PIC18LF2450/4450 10
32
30
29
63
60
57
168
160
152
8
μA
μA
μA
μA
μA
μA
μA
μA
μA
μA
μA
μA
μA
μA
μA
μA
μA
μA
-40°C
10
+25°C
+85°C
-40°C
+25°C
+85°C
-40°C
+25°C
+85°C
-40°C
+25°C
+85°C
-40°C
+25°C
+85°C
-40°C
+25°C
+85°C
VDD = 2.0V
VDD = 3.0V
VDD = 5.0V
VDD = 2.0V
VDD = 3.0V
VDD = 5.0V
12
PIC18LF2450/4450 35
FOSC = 31 kHz
(RC_RUN mode,
INTRC source)
30
25
All devices 95
75
65
PIC18LF2450/4450 2.3
2.5
8
3.3
11
PIC18LF2450/4450 3.3
11
FOSC = 31 kHz
(RC_IDLE mode,
INTRC source)
3.6
11
4.0
15
16
16
36
All devices 6.5
7.0
9.0
Legend: Shading of rows is to assist in readability of the table.
Note 1: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured
with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS and all features that
add delta current disabled (such as WDT, Timer1 Oscillator, BOR, etc.).
2: The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin
loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have
an impact on the current consumption.
The test conditions for all IDD measurements in active operation mode are:
OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD or VSS;
MCLR = VDD; WDT enabled/disabled as specified.
3: Standard low-cost 32 kHz crystals have an operating temperature range of -10°C to +70°C. Extended
temperature crystals are available at a much higher cost.
4: BOR and HLVD enable internal band gap reference. With both modules enabled, current consumption will be
less than the sum of both specifications.
© 2008 Microchip Technology Inc.
DS39760D-page 271
PIC18F2450/4450
21.2 DC Characteristics: Power-Down and Supply Current
PIC18F2450/4450 (Industrial)
PIC18LF2450/4450 (Industrial) (Continued)
PIC18LF2450/4450
Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C ≤ TA ≤ +85°C for industrial
(Industrial)
PIC18F2450/4450
Standard Operating Conditions (unless otherwise stated)
(Industrial)
Operating temperature
-40°C ≤ TA ≤ +85°C for industrial
Param
No.
Device
Typ Max Units
Conditions
(2)
Supply Current (IDD)
PIC18LF2450/4450 200
500
500
500
650
650
650
1.6
1.5
1.4
2.0
2.0
2.0
3.0
3.0
3.0
6.0
6.0
6.0
35
μA
μA
-40°C
200
+25°C
+85°C
-40°C
+25°C
+85°C
-40°C
+25°C
+85°C
-40°C
+25°C
+85°C
-40°C
+25°C
+85°C
-40°C
+25°C
+85°C
-40°C
+25°C
+85°C
-40°C
+25°C
+85°C
-40°C
+25°C
+85°C
-40°C
+25°C
+85°C
VDD = 2.0V
VDD = 3.0V
VDD = 5.0V
VDD = 2.0V
VDD = 3.0V
VDD = 5.0V
VDD = 4.2V
VDD = 5.0V
VDD = 4.2V
VDD = 5.0V
200
μA
PIC18LF2450/4450 500
μA
FOSC = 1 MHZ
(PRI_RUN,
EC oscillator)
400
μA
360
μA
All devices 1.0
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
0.9
0.8
PIC18LF2450/4450 0.53
0.53
0.55
PIC18LF2450/4450 1.0
FOSC = 4 MHz
(PRI_RUN,
EC oscillator)
0.9
0.9
All devices 2.0
1.9
1.8
All devices 11.0
11.0
35
FOSC = 40 MHZ
(PRI_RUN,
EC oscillator)
11.3
35
All devices 14.0
40
14.0
40
14.5
40
All devices 20
40
20
40
FOSC = 48 MHZ
(PRI_RUN,
EC oscillator)
20
40
All devices 25
50
25
25
50
50
Legend: Shading of rows is to assist in readability of the table.
Note 1: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured
with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS and all features that
add delta current disabled (such as WDT, Timer1 Oscillator, BOR, etc.).
2: The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin
loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have
an impact on the current consumption.
The test conditions for all IDD measurements in active operation mode are:
OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD or VSS;
MCLR = VDD; WDT enabled/disabled as specified.
3: Standard low-cost 32 kHz crystals have an operating temperature range of -10°C to +70°C. Extended
temperature crystals are available at a much higher cost.
4: BOR and HLVD enable internal band gap reference. With both modules enabled, current consumption will be
less than the sum of both specifications.
DS39760D-page 272
© 2008 Microchip Technology Inc.
PIC18F2450/4450
21.2 DC Characteristics: Power-Down and Supply Current
PIC18F2450/4450 (Industrial)
PIC18LF2450/4450 (Industrial) (Continued)
PIC18LF2450/4450
Standard Operating Conditions (unless otherwise stated)
(Industrial)
Operating temperature
-40°C ≤ TA ≤ +85°C for industrial
PIC18F2450/4450
Standard Operating Conditions (unless otherwise stated)
(Industrial)
Operating temperature
Typ Max Units
-40°C ≤ TA ≤ +85°C for industrial
Param
No.
Device
Conditions
(2)
Supply Current (IDD)
PIC18LF2450/4450 50
130
120
115
270
250
240
480
450
430
475
450
430
900
850
810
1.5
1.4
1.3
16
μA
μA
-40°C
50
+25°C
+85°C
-40°C
+25°C
+85°C
-40°C
+25°C
+85°C
-40°C
+25°C
+85°C
-40°C
+25°C
+85°C
-40°C
+25°C
+85°C
-40°C
+25°C
+85°C
-40°C
+25°C
+85°C
-40°C
+25°C
+85°C
-40°C
+25°C
+85°C
VDD = 2.0V
VDD = 3.0V
VDD = 5.0V
VDD = 2.0V
VDD = 3.0V
VDD = 5.0V
VDD = 4.2V
VDD = 5.0V
VDD = 4.2V
VDD = 5.0V
50
μA
PIC18LF2450/4450 75
μA
FOSC = 1 MHz
(PRI_IDLE mode,
EC oscillator)
80
μA
80
μA
All devices 150
μA
150
μA
150
μA
PIC18LF2450/4450 190
μA
195
μA
200
μA
PIC18LF2450/4450 295
μA
FOSC = 4 MHz
(PRI_IDLE mode,
EC oscillator)
300
μA
310
μA
All devices 560
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
570
580
All devices 4.4
4.5
16
FOSC = 40 MHz
(PRI_IDLE mode,
EC oscillator)
4.6
16
All devices 5.5
18
5.6
18
5.8
18
All devices 8.0
18
8.1
18
FOSC = 48 MHz
(PRI_IDLE mode,
EC oscillator)
8.2
All devices 9.8
10.0
18
21
21
10.5
21
Legend: Shading of rows is to assist in readability of the table.
Note 1: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured
with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS and all features that
add delta current disabled (such as WDT, Timer1 Oscillator, BOR, etc.).
2: The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin
loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have
an impact on the current consumption.
The test conditions for all IDD measurements in active operation mode are:
OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD or VSS;
MCLR = VDD; WDT enabled/disabled as specified.
3: Standard low-cost 32 kHz crystals have an operating temperature range of -10°C to +70°C. Extended
temperature crystals are available at a much higher cost.
4: BOR and HLVD enable internal band gap reference. With both modules enabled, current consumption will be
less than the sum of both specifications.
© 2008 Microchip Technology Inc.
DS39760D-page 273
PIC18F2450/4450
21.2 DC Characteristics: Power-Down and Supply Current
PIC18F2450/4450 (Industrial)
PIC18LF2450/4450 (Industrial) (Continued)
PIC18LF2450/4450
Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C ≤ TA ≤ +85°C for industrial
(Industrial)
PIC18F2450/4450
Standard Operating Conditions (unless otherwise stated)
(Industrial)
Operating temperature
-40°C ≤ TA ≤ +85°C for industrial
Param
No.
Device
Typ Max Units
Conditions
(2)
Supply Current (IDD)
PIC18LF2450/4450 13
40
40
40
76
70
67
150
150
150
12
12
12
15
15
15
25
μA
μA
μA
μA
μA
μA
μA
μA
μA
μA
μA
μA
μA
μA
μA
μA
μA
μA
-40°C
15
+25°C
+85°C
-40°C
+25°C
+85°C
-40°C
+25°C
+85°C
-40°C
+25°C
+85°C
-40°C
+25°C
+85°C
-40°C
+25°C
+85°C
VDD = 2.0V
VDD = 3.0V
VDD = 5.0V
VDD = 2.0V
VDD = 3.0V
VDD = 5.0V
17
(3)
PIC18LF2450/4450 40
FOSC = 32 kHz
32
(SEC_RUN mode,
Timer1 as clock)
25
All devices 100
80
70
PIC18LF2450/4450 5.6
7.0
8.3
(3)
PIC18LF2450/4450 6.5
FOSC = 32 kHz
8.0
(SEC_IDLE mode,
Timer1 as clock)
9.5
All devices 8.7
10.2
25
36
13.0
Legend: Shading of rows is to assist in readability of the table.
Note 1: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured
with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS and all features that
add delta current disabled (such as WDT, Timer1 Oscillator, BOR, etc.).
2: The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin
loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have
an impact on the current consumption.
The test conditions for all IDD measurements in active operation mode are:
OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD or VSS;
MCLR = VDD; WDT enabled/disabled as specified.
3: Standard low-cost 32 kHz crystals have an operating temperature range of -10°C to +70°C. Extended
temperature crystals are available at a much higher cost.
4: BOR and HLVD enable internal band gap reference. With both modules enabled, current consumption will be
less than the sum of both specifications.
DS39760D-page 274
© 2008 Microchip Technology Inc.
PIC18F2450/4450
21.2 DC Characteristics: Power-Down and Supply Current
PIC18F2450/4450 (Industrial)
PIC18LF2450/4450 (Industrial) (Continued)
PIC18LF2450/4450
Standard Operating Conditions (unless otherwise stated)
(Industrial)
Operating temperature
-40°C ≤ TA ≤ +85°C for industrial
PIC18F2450/4450
Standard Operating Conditions (unless otherwise stated)
(Industrial)
Operating temperature
Typ Max Units
Module Differential Currents (ΔIWDT, ΔIBOR, ΔILVD, ΔIOSCB, ΔIAD)
-40°C ≤ TA ≤ +85°C for industrial
Param
No.
Device
Conditions
D022
(ΔIWDT)
Watchdog Timer 1.3
3.8
3.8
3.8
4.6
4.6
4.6
10
μA
μA
μA
μA
μA
μA
μA
μA
μA
μA
μA
-40°C
+25°C
1.5
2.3
1.8
2.0
3.0
3.3
3.6
VDD = 2.0V
VDD = 3.0V
VDD = 5.0V
+85°C
-40°C
+25°C
+85°C
-40°C
10
+25°C
3.9
10
+85°C
(4)
D022A
(ΔIBOR)
Brown-out Reset
40
45
52
-40°C to +85°C
-40°C to +85°C
VDD = 3.0V
VDD = 5.0V
63
Sleep mode,
BOREN1:BOREN0 = 10
0
2
μA
-40°C to +85°C
D022B
(ΔILVD)
High/Low-Voltage 22
47
58
μA
μA
μA
μA
μA
μA
μA
μA
μA
μA
μA
μA
μA
μA
μA
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C
VDD = 2.0V
VDD = 3.0V
VDD = 5.0V
(4)
Detect
25
29
69
D025
(ΔIOSCB)
Timer1 Oscillator 1.5
4.5
4.5
4.5
6.0
6.0
6.0
8.0
8.0
8.0
2.0
2.0
2.0
(3)
1.2
+25°C
VDD = 2.0V
VDD = 3.0V
VDD = 5.0V
32 kHz on Timer1
1.6
+85°C
1.7
-40°C
(3)
1.8
+25°C
32 kHz on Timer1
2.0
+85°C
1.4
-40°C
(3)
1.5
+25°C
32 kHz on Timer1
1.9
+85°C
D026
(ΔIAD)
A/D Converter 0.2
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
VDD = 2.0V
VDD = 3.0V
VDD = 5.0V
0.2
0.2
A/D on, not converting
Legend: Shading of rows is to assist in readability of the table.
Note 1: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured
with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS and all features that
add delta current disabled (such as WDT, Timer1 Oscillator, BOR, etc.).
2: The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin
loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have
an impact on the current consumption.
The test conditions for all IDD measurements in active operation mode are:
OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD or VSS;
MCLR = VDD; WDT enabled/disabled as specified.
3: Standard low-cost 32 kHz crystals have an operating temperature range of -10°C to +70°C. Extended
temperature crystals are available at a much higher cost.
4: BOR and HLVD enable internal band gap reference. With both modules enabled, current consumption will be
less than the sum of both specifications.
© 2008 Microchip Technology Inc.
DS39760D-page 275
PIC18F2450/4450
21.2 DC Characteristics: Power-Down and Supply Current
PIC18F2450/4450 (Industrial)
PIC18LF2450/4450 (Industrial) (Continued)
PIC18LF2450/4450
Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C ≤ TA ≤ +85°C for industrial
(Industrial)
PIC18F2450/4450
Standard Operating Conditions (unless otherwise stated)
(Industrial)
Operating temperature
Typ Max Units
USB and Related Module Differential Currents (ΔIUSBx, ΔIPLL, ΔIUREG)
-40°C ≤ TA ≤ +85°C for industrial
Param
No.
Device
Conditions
ΔIUSBX
ΔIPLL
USB Module 8.0
14.5
20
mA
mA
mA
mA
μA
+25°C
+25°C
+25°C
+25°C
+25°C
VDD = 3.3V
VDD = 5.0V
VDD = 3.3V
VDD = 5.0V
VDD = 5.0V
with On-Chip Transceiver
12.4
96 MHz PLL 1.2
3.0
4.8
125
(Oscillator Module)
1.2
ΔIUREG
USB Internal Voltage 80
USB Idle,
Regulator
UCON<SUSPND> = 1
Legend: Shading of rows is to assist in readability of the table.
Note 1: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured
with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS and all features that
add delta current disabled (such as WDT, Timer1 Oscillator, BOR, etc.).
2: The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin
loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have
an impact on the current consumption.
The test conditions for all IDD measurements in active operation mode are:
OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD or VSS;
MCLR = VDD; WDT enabled/disabled as specified.
3: Standard low-cost 32 kHz crystals have an operating temperature range of -10°C to +70°C. Extended
temperature crystals are available at a much higher cost.
4: BOR and HLVD enable internal band gap reference. With both modules enabled, current consumption will be
less than the sum of both specifications.
DS39760D-page 276
© 2008 Microchip Technology Inc.
PIC18F2450/4450
21.2 DC Characteristics: Power-Down and Supply Current
PIC18F2450/4450 (Industrial)
PIC18LF2450/4450 (Industrial) (Continued)
PIC18LF2450/4450
Standard Operating Conditions (unless otherwise stated)
(Industrial)
Operating temperature
-40°C ≤ TA ≤ +85°C for industrial
PIC18F2450/4450
Standard Operating Conditions (unless otherwise stated)
(Industrial)
Operating temperature
Typ Max Units
-40°C ≤ TA ≤ +85°C for industrial
Param
No.
Device
Conditions
(2)
ITUSB
Total USB Run Currents (ITUSB)
Primary Run with USB 29
65
65
65
mA
mA
mA
-40°C
+25°C
+85°C
VDD = 5.0V
VDD = 5.0V
VDD = 5.0V
EC+PLL 4 MHz input,
48 MHz PRI_RUN,
USB module enabled in
Full-Speed mode,
USB VREG enabled,
no bus traffic
Module, PLL and USB
29
Voltage Regulator
29
Legend: Shading of rows is to assist in readability of the table.
Note 1: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured
with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS and all features that
add delta current disabled (such as WDT, Timer1 Oscillator, BOR, etc.).
2: The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin
loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have
an impact on the current consumption.
The test conditions for all IDD measurements in active operation mode are:
OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD or VSS;
MCLR = VDD; WDT enabled/disabled as specified.
3: Standard low-cost 32 kHz crystals have an operating temperature range of -10°C to +70°C. Extended
temperature crystals are available at a much higher cost.
4: BOR and HLVD enable internal band gap reference. With both modules enabled, current consumption will be
less than the sum of both specifications.
© 2008 Microchip Technology Inc.
DS39760D-page 277
PIC18F2450/4450
21.3 DC Characteristics: PIC18F2450/4450 (Industrial)
PIC18LF2450/4450 (Industrial)
Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C ≤ TA ≤ +85°C for industrial
DC CHARACTERISTICS
Param
Sym
No.
Characteristic
Min
Max
Units
Conditions
VIL
VIH
IIL
Input Low Voltage
I/O Ports (except RC4/RC5 in
USB mode):
D030
with TTL Buffer
VSS
—
0.15 VDD
0.8
V
V
V
V
V
VDD < 4.5V
D030A
D032
4.5V ≤ VDD ≤ 5.5V
MCLR
VSS
VSS
VSS
0.2 VDD
0.3 VDD
0.2 VDD
D032A
D033
OSC1 and T1OSI
OSC1
XT, HS, HSPLL modes(1)
EC mode(1)
Input High Voltage
I/O Ports (except RC4/RC5 in
USB mode):
D040
with TTL Buffer
0.25 VDD + 0.8V
2.0
VDD
VDD
VDD
VDD
VDD
V
V
V
V
V
VDD < 4.5V
D040A
D042
4.5V ≤ VDD ≤ 5.5V
MCLR
0.8 VDD
0.7 VDD
0.8 VDD
D042A
D043
OSC1 and T1OSI
XT, HS, HSPLL modes(1)
EC mode(1)
OSC1
Input Leakage Current(2,3)
I/O Ports (except D+ and D-)
D060
—
—
—
—
±200
±50
±1
nA VDD = 5V
nA VDD = 3V
D061
D063
MCLR
μA Vss ≤ VPIN ≤ VDD
μA Vss ≤ VPIN ≤ VDD
OSC1
±1
IPU
Weak Pull-up Current
PORTB Weak Pull-up Current
D070
IPURB
50
400
μA VDD = 5V, VPIN = VSS
Note 1: In RC oscillator configuration, the OSC1/CLKI pin is a Schmitt Trigger input. It is not recommended that the
PIC® microcontroller be driven with an external clock while in RC mode.
2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified
levels represent normal operating conditions. Higher leakage current may be measured at different input
voltages.
3: Negative current is defined as current sourced by the pin.
4: Parameter is characterized but not tested.
DS39760D-page 278
© 2008 Microchip Technology Inc.
PIC18F2450/4450
21.3 DC Characteristics: PIC18F2450/4450 (Industrial)
PIC18LF2450/4450 (Industrial) (Continued)
Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C ≤ TA ≤ +85°C for industrial
DC CHARACTERISTICS
Param
Sym
No.
Characteristic
Min
Max
Units
Conditions
VOL
Output Low Voltage
D080
D083
I/O Ports (except RC4/RC5 in
USB mode)
—
—
0.6
0.6
V
V
IOL = 8.5 mA, VDD = 4.5V,
-40°C to +85°C
OSC2/CLKO
IOL = 1.6 mA, VDD = 4.5V,
(EC, ECIO modes)
Output High Voltage(3)
-40°C to +85°C
VOH
D090
D092
I/O Ports (except RC4/RC5 in
USB mode)
VDD – 0.7
VDD – 0.7
—
—
V
V
IOH = -3.0 mA, VDD = 4.5V,
-40°C to +85°C
OSC2/CLKO
IOH = -1.3 mA, VDD = 4.5V,
(EC, ECIO, ECPIO modes)
-40°C to +85°C
Capacitive Loading Specs
on Output Pins
D100(4) COSC2 OSC2 pin
—
—
15
50
pF In XT and HS modes
when external clock is
used to drive OSC1
D101
CIO
All I/O pins and OSC2
(in RC mode)
pF To meet the AC Timing
Specifications
Note 1: In RC oscillator configuration, the OSC1/CLKI pin is a Schmitt Trigger input. It is not recommended that the
PIC® microcontroller be driven with an external clock while in RC mode.
2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified
levels represent normal operating conditions. Higher leakage current may be measured at different input
voltages.
3: Negative current is defined as current sourced by the pin.
4: Parameter is characterized but not tested.
© 2008 Microchip Technology Inc.
DS39760D-page 279
PIC18F2450/4450
TABLE 21-1: MEMORY PROGRAMMING REQUIREMENTS
Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C ≤ TA ≤ +85°C for industrial
DC Characteristics
Param
Sym
No.
Characteristic
Min
Typ†
Max
Units
Conditions
Internal Program Memory
Programming Specifications(1)
D110
D113
VIHH
IDDP
Voltage on MCLR/VPP/RE3 pin
9.00
—
—
—
13.25
10
V
(Note 2)
Supply Current during
Programming
mA
Program Flash Memory
Cell Endurance
D130
D131
EP
10K
100K
—
—
E/W -40°C to +85°C
VPR
VDD for Read
VMIN
5.5
V
VMIN = Minimum operating
voltage
D132
VIE
VDD for Block Erase
4.5
3.0
—
—
5.5
5.5
V
V
Using ICSP™ port
Using ICSP port
D132A VIW
VDD for Externally Timed Erase
or Write
D132B VPEW VDD for Self-Timed Write
VMIN
—
5.5
V
VMIN = Minimum operating
voltage
D133
TIE
ICSP™ Block Erase Cycle Time
—
1
4
—
—
ms VDD > 4.5V
ms VDD > 4.5V
D133A TIW
ICSP Erase or Write Cycle Time
(externally timed)
—
D133A TIW
Self-Timed Write Cycle Time
—
2
—
—
ms
D134 TRETD Characteristic Retention
40
100
Year Provided no other
specifications are violated
†
Data in “Typ” column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance
only and are not tested.
Note 1: These specifications are for programming the on-chip program memory through the use of table write
instructions.
2: Required only if Single-Supply Programming is disabled.
DS39760D-page 280
© 2008 Microchip Technology Inc.
PIC18F2450/4450
TABLE 21-2: USB MODULE SPECIFICATIONS
Operating Conditions: -40°C < TA < +85°C (unless otherwise stated).
Param
Sym
Characteristic
Min
Typ
Max
Units
Comments
No.
D313
VUSB
USB Voltage
3.0
—
3.6
V
Voltage on bus must be in this
range for proper USB
operation
D314
D315
D316
D317
D318
IIL
Input Leakage on D+ or D-
pin
—
—
—
—
—
±1
0.8
—
μA
V
VSS ≤ VPIN ≤ VDD;
pin at high-impedance
VILUSB Input Low Voltage for USB
Buffer
For VUSB range
For VUSB range
VIHUSB Input High Voltage for USB
Buffer
2.0
1.3
—
V
VCRS
Crossover Voltage
2.0
0.2
V
Voltage range for D+ and D-
crossover to occur
VDIFS
Differential Input Sensitivity
—
—
V
The difference between D+
and D- must exceed this value
while VCM is met
D319
VCM
Differential Common Mode
Range
0.8
2.5
V
D320
D321
D322
ZOUT
VOL
Driver Output Impedance
Voltage Output Low
28
0.0
2.8
—
—
—
44
0.3
3.6
Ω
V
V
1.5 kΩ load connected to 3.6V
VOH
Voltage Output High
15 kΩ load connected to
ground
TABLE 21-3: USB INTERNAL VOLTAGE REGULATOR SPECIFICATIONS
Operating Conditions: -40°C < TA < +85°C (unless otherwise stated).
Param
Sym
Characteristics
Min
Typ
Max
Units
Comments
No.
D323
D324
VUSBANA Regulator Output Voltage
3.0
—
3.6
—
V
VDD > 4.0V(1)
Low ESR
CUSB
External Filter Capacitor
Value
220
470
nF
Note 1: If device VDD is less than 4.0V, the internal USB voltage regulator should be disabled and an external
3.0-3.6V supply should be provided on VUSB.
© 2008 Microchip Technology Inc.
DS39760D-page 281
PIC18F2450/4450
FIGURE 21-3:
HIGH/LOW-VOLTAGE DETECT CHARACTERISTICS
For VDIRMAG = 1:
VDD
VHLVD
(HLVDIF set by hardware)
(HLVDIF can be
cleared in software)
VHLVD
VDD
For VDIRMAG = 0:
HLVDIF
TABLE 21-4: HIGH/LOW-VOLTAGE DETECT CHARACTERISTICS
Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C ≤ TA ≤ +85°C for industrial
Param
No.
Sym
Characteristic
Min
Typ
Max Units
Conditions
D420
HLVD Voltage on VDD HLVDL<3:0> = 0000 2.06
2.17 2.28
2.23 2.34
2.36 2.48
2.44 2.56
2.60 2.73
2.79 2.93
2.89 3.04
3.12 3.28
3.39 3.56
3.55 3.73
3.71 3.90
3.90 4.10
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
Transition High-to-Low
HLVDL<3:0> = 0001 2.12
HLVDL<3:0> = 0010 2.24
HLVDL<3:0> = 0011 2.32
HLVDL<3:0> = 0100 2.47
HLVDL<3:0> = 0101 2.65
HLVDL<3:0> = 0110 2.74
HLVDL<3:0> = 0111 2.96
HLVDL<3:0> = 1000 3.22
HLVDL<3:0> = 1001 3.37
HLVDL<3:0> = 1010 3.52
HLVDL<3:0> = 1011 3.70
HLVDL<3:0> = 1100 3.90
HLVDL<3:0> = 1101 4.11
HLVDL<3:0> = 1110 4.36
4.11
4.32
4.33 4.55
4.59 4.82
DS39760D-page 282
© 2008 Microchip Technology Inc.
PIC18F2450/4450
21.4 AC (Timing) Characteristics
21.4.1 TIMING PARAMETER SYMBOLOGY
The timing parameter symbols have been created
using one of the following formats:
1. TppS2ppS
2. TppS
T
F
Frequency
T
Time
Lowercase letters (pp) and their meanings:
pp
mc
osc
wr
t0
MCLR
OSC1
WR
cc
ck
dt
CCP1
CLKO
Data in
I/O port
T0CKI
T1CKI
io
t1
:Uppercase Letters and their meanings
S
F
H
I
Fall
P
R
V
Z
Period
High
Rise
Invalid (High-Impedance)
Low
Valid
L
High-Impedance
High
Low
High
Low
© 2008 Microchip Technology Inc.
DS39760D-page 283
PIC18F2450/4450
21.4.2
TIMING CONDITIONS
Note:
Because of space limitations, the generic
terms “PIC18FXXXX” and “PIC18LFXXXX”
are used throughout this section to refer to
the PIC18F2450/4450 and PIC18LF2450/
4450 families of devices specifically and
only those devices.
The temperature and voltages specified in Table 21-5
apply to all timing specifications unless otherwise
noted. Figure 21-4 specifies the load conditions for the
timing specifications.
TABLE 21-5: TEMPERATURE AND VOLTAGE SPECIFICATIONS – AC
Standard Operating Conditions (unless otherwise stated)
Operating temperature
-40°C ≤ TA ≤ +85°C for industrial
AC CHARACTERISTICS
Operating voltage VDD range as described in DC spec Section 21.1 and
Section 21.3 .
LF parts operate for industrial temperatures only.
FIGURE 21-4:
LOAD CONDITIONS FOR DEVICE TIMING SPECIFICATIONS
Load Condition 1 Load Condition 2
VDD/2
CL
RL
Pin
VSS
CL
Pin
RL = 464Ω
CL = 50 pF for all pins except OSC2/CLKO
and including D and E outputs as ports
VSS
DS39760D-page 284
© 2008 Microchip Technology Inc.
PIC18F2450/4450
21.4.3
TIMING DIAGRAMS AND SPECIFICATIONS
FIGURE 21-5:
EXTERNAL CLOCK TIMING (ALL MODES EXCEPT PLL)
Q4
Q1
1
Q2
Q3
Q4
Q1
OSC1
CLKO
3
4
3
4
2
TABLE 21-6: EXTERNAL CLOCK TIMING REQUIREMENTS
Param.
Symbol
Characteristic
Min
Max
Units
Conditions
No.
1A
FOSC
External CLKI Frequency(1)
Oscillator Frequency(1)
DC
0.2
4
48
1
MHz EC, ECIO Oscillator modes
MHz XT, XTPLL Oscillator modes
MHz HS Oscillator mode
25
4
25
MHz HSPLL Oscillator mode
1
TOSC
TCY
External CLKI Period(1)
Oscillator Period(1)
20.8
1,000
40
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
EC, ECIO Oscillator modes
XT Oscillator mode
HS Oscillator mode
HSPLL Oscillator mode
TCY = 4/FOSC
5,000
250
250
—
40
2
3
Instruction Cycle Time(1)
83.3
30
TosL,
TosH
External Clock in (OSC1)
High or Low Time
—
XT Oscillator mode
HS Oscillator mode
XT Oscillator mode
HS Oscillator mode
10
—
4
TosR,
TosF
External Clock in (OSC1)
Rise or Fall Time
—
20
—
7.5
Note 1: Instruction cycle period (TCY) equals four times the input oscillator time base period for all configurations
except PLL. All specified values are based on characterization data for that particular oscillator type under
standard operating conditions with the device executing code. Exceeding these specified limits may result
in an unstable oscillator operation and/or higher than expected current consumption. All devices are tested
to operate at “min.” values with an external clock applied to the OSC1/CLKI pin. When an external clock
input is used, the “max.” cycle time limit is “DC” (no clock) for all devices.
© 2008 Microchip Technology Inc.
DS39760D-page 285
PIC18F2450/4450
TABLE 21-7: PLL CLOCK TIMING SPECIFICATIONS (VDD = 3.0V TO 5.5V)
Param
Sym
Characteristic
Min
Typ†
Max
Units Conditions
No.
F10
FOSC Oscillator Frequency Range
4
—
—
96
—
—
48
—
MHz
MHz
ms
F11
F12
F13
FSYS On-Chip VCO System Frequency
trc
PLL Start-up Time (lock time)
—
2
ΔCLK CLKO Stability (jitter)
-0.25
+0.25
%
†
Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance
only and are not tested.
TABLE 21-8: AC CHARACTERISTICS: INTERNAL RC ACCURACY
PIC18F2450/4450 (INDUSTRIAL)
PIC18LF2450/4450 (INDUSTRIAL)
PIC18LF2450/4450
Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C ≤ TA ≤ +85°C for industrial
(Industrial)
PIC18F2450/4450
Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C ≤ TA ≤ +85°C for industrial
(Industrial)
Param
No.
Device
Min
Typ
Max
Units
Conditions
(1)
INTRC Accuracy @ Freq = 31 kHz
PIC18LF2450/4450 26.562
PIC18F2450/4450 26.562
—
—
35.938
35.938
kHz
kHz
-40°C to +85°C
-40°C to +85°C
VDD = 2.7-3.3V
VDD = 4.5-5.5V
Legend:
Shading of rows is to assist in readability of the table.
Note 1: INTRC frequency after calibration.
DS39760D-page 286
© 2008 Microchip Technology Inc.
PIC18F2450/4450
FIGURE 21-6:
CLKO AND I/O TIMING
Q1
Q2
Q3
Q4
OSC1
11
10
CLKO
12
16
13
14
18
19
I/O pin
(Input)
15
17
I/O pin
(Output)
New Value
Old Value
20, 21
Refer to Figure 21-4 for load conditions.
Note:
TABLE 21-9: CLKO AND I/O TIMING REQUIREMENTS
Param
Symbol
Characteristic
Min
Typ
Max
Units Conditions
No.
10
TosH2ckL OSC1 ↑ to CLKO ↓
TosH2ckH OSC1 ↑ to CLKO ↑
—
—
—
—
—
75
75
35
35
—
—
—
50
—
—
200
200
100
100
ns (Note 1)
ns (Note 1)
ns (Note 1)
ns (Note 1)
11
12
13
14
15
16
17
18
18A
TckR
TckF
CLKO Rise Time
CLKO Fall Time
TckL2ioV CLKO ↓ to Port Out Valid
TioV2ckH Port In Valid before CLKO ↑
TckH2ioI Port In Hold after CLKO ↑
TosH2ioV OSC1 ↑ (Q1 cycle) to Port Out Valid
0.5 TCY + 20 ns (Note 1)
0.25 TCY + 25
—
—
ns (Note 1)
ns (Note 1)
ns
0
—
150
—
TosH2ioI OSC1 ↑ (Q2 cycle) to
Port Input Invalid
PIC18FXXXX
100
200
ns
PIC18LFXXXX
—
ns VDD = 2.0V
(I/O in hold time)
19
TioV2osH Port Input Valid to OSC1 ↑ (I/O in setup
0
—
—
ns
time)
20
TioR
TioF
Port Output Rise Time
Port Output Fall Time
PIC18FXXXX
PIC18LFXXXX
PIC18FXXXX
PIC18LFXXXX
—
—
10
—
10
—
—
—
25
60
25
60
—
—
ns
20A
21
ns VDD = 2.0V
—
ns
21A
22†
23†
—
ns VDD = 2.0V
TINP
INTx Pin High or Low Time
TCY
TCY
ns
ns
TRBP
RB7:RB4 Change Interrupt High or Low
Time
†
These parameters are asynchronous events not related to any internal clock edges.
Note 1: Measurements are taken in RC mode, where CLKO output is 4 x TOSC.
© 2008 Microchip Technology Inc.
DS39760D-page 287
PIC18F2450/4450
FIGURE 21-7:
RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND
POWER-UP TIMER TIMING
VDD
MCLR
30
Internal
POR
33
PWRT
Time-out
32
Oscillator
Time-out
Internal
Reset
Watchdog
Timer
Reset
31
34
34
I/O pins
Note:
Refer to Figure 21-4 for load conditions.
FIGURE 21-8:
BROWN-OUT RESET TIMING
BVDD
VDD
35
VBGAP = 1.2V
VIRVST
Enable Internal
Reference Voltage
Internal Reference
Voltage Stable
36
TABLE 21-10: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER
AND BROWN-OUT RESET REQUIREMENTS
Param.
No.
Symbol
Characteristic
Min
Typ
Max
Units
Conditions
30
TmcL
TWDT
MCLR Pulse Width (low)
2
—
—
μs
31
Watchdog Timer Time-out Period
(no postscaler)
—
4.00
4.6
ms
32
33
34
TOST
Oscillator Start-up Timer Period
1024 TOSC
—
65.5
2
1024 TOSC
—
ms
μs
TOSC = OSC1 period
TPWRT Power-up Timer Period
—
—
75
—
TIOZ
I/O High-Impedance from MCLR
Low or Watchdog Timer Reset
35
36
TBOR
Brown-out Reset Pulse Width
200
—
—
—
μs VDD ≤ BVDD (see D005)
μs
TIRVST Time for Internal Reference
Voltage to become Stable
20
50
37
38
39
TLVD
TCSD
Low-Voltage Detect Pulse Width
CPU Start-up Time
200
5
—
—
1
—
10
—
μs
μs
VDD ≤ VLVD
TIOBST Time for INTRC to Stabilize
—
ms
DS39760D-page 288
© 2008 Microchip Technology Inc.
PIC18F2450/4450
FIGURE 21-9:
TIMER0 AND TIMER1 EXTERNAL CLOCK TIMINGS
T0CKI
41
40
42
T1OSO/T1CKI
46
45
47
48
TMR0 or
TMR1
Note:
Refer to Figure 21-4 for load conditions.
TABLE 21-11: TIMER0 AND TIMER1 EXTERNAL CLOCK REQUIREMENTS
Param
Symbol
Characteristic
Min
Max Units
Conditions
No.
40
Tt0H
T0CKI High Pulse Width
No prescaler
With prescaler
No prescaler
With prescaler
No prescaler
With prescaler
0.5 TCY + 20
10
—
—
—
—
—
—
ns
ns
ns
ns
ns
41
42
Tt0L
Tt0P
T0CKI Low Pulse Width
T0CKI Period
0.5 TCY + 20
10
TCY + 10
Greater of:
20 ns or
ns N = prescale
value
(TCY + 40)/N
(1, 2, 4,..., 256)
45
46
Tt1H
Tt1L
T1CKI High
Time
Synchronous, no prescaler
0.5 TCY + 20
—
—
—
—
—
—
—
—
—
—
—
ns
Synchronous,
with prescaler
PIC18FXXXX
10
ns
PIC18LFXXXX
25
ns VDD = 2.0V
Asynchronous PIC18FXXXX
PIC18LFXXXX
30
ns
50
ns VDD = 2.0V
T1CKI Low
Time
Synchronous, no prescaler
0.5 TCY + 5
ns
Synchronous,
with prescaler
PIC18FXXXX
10
25
30
50
ns
PIC18LFXXXX
ns VDD = 2.0V
ns
Asynchronous PIC18FXXXX
PIC18LFXXXX
ns VDD = 2.0V
47
48
Tt1P
Ft1
T1CKI Input
Period
Synchronous
Greater of:
20 ns or
(TCY + 40)/N
ns N = prescale
value (1, 2, 4, 8)
Asynchronous
60
DC
—
50
ns
kHz
—
T1CKI Oscillator Input Frequency Range
Tcke2tmrI Delay from External T1CKI Clock Edge to Timer
Increment
2 TOSC
7 TOSC
© 2008 Microchip Technology Inc.
DS39760D-page 289
PIC18F2450/4450
FIGURE 21-10:
CAPTURE/COMPARE/PWM TIMINGS (CCP MODULE)
CCP1
(Capture Mode)
50
51
52
54
CCP1
(Compare or PWM Mode)
53
Refer to Figure 21-4 for load conditions.
Note:
TABLE 21-12: CAPTURE/COMPARE/PWM REQUIREMENTS
Param
Symbol
Characteristic
Min
Max
Units
Conditions
No.
50
TccL
CCP1 Input
Low Time
No prescaler
0.5 TCY + 20
—
—
—
—
—
—
—
ns
ns
ns
ns
ns
ns
ns
With
PIC18FXXXX
10
prescaler
PIC18LFXXXX
20
VDD = 2.0V
VDD = 2.0V
51
TccH
CCP1 Input
High Time
No prescaler
0.5 TCY + 20
With
PIC18FXXXX
10
20
prescaler
PIC18LFXXXX
52
53
TccP
TccR
CCP1 Input Period
3 TCY + 40
N
N = prescale
value (1, 4 or 16)
CCP1 Output Fall Time
PIC18FXXXX
PIC18LFXXXX
PIC18FXXXX
PIC18LFXXXX
—
—
—
—
25
45
25
45
ns
ns
ns
ns
VDD = 2.0V
VDD = 2.0V
54
TccF
CCP1 Output Fall Time
DS39760D-page 290
© 2008 Microchip Technology Inc.
PIC18F2450/4450
FIGURE 21-11:
EUSART SYNCHRONOUS TRANSMISSION (MASTER/SLAVE) TIMING
RC6/TX/CK
pin
121
121
RC7/RX/DT
pin
120
Note: Refer to Figure 21-4 for load conditions.
122
TABLE 21-13: EUSART SYNCHRONOUS TRANSMISSION REQUIREMENTS
Param
Symbol
Characteristic
Min
Max
Units Conditions
No.
120
TckH2dtV SYNC XMIT (MASTER & SLAVE)
Clock High to Data Out Valid
PIC18FXXXX
—
—
—
—
—
—
40
100
20
ns
PIC18LFXXXX
ns VDD = 2.0V
ns
121
122
Tckrf
Tdtrf
Clock Out Rise Time and Fall Time PIC18FXXXX
(Master mode)
PIC18LFXXXX
50
ns VDD = 2.0V
ns
Data Out Rise Time and Fall Time
PIC18FXXXX
20
PIC18LFXXXX
50
ns VDD = 2.0V
FIGURE 21-12:
EUSART SYNCHRONOUS RECEIVE (MASTER/SLAVE) TIMING
RC6/TX/CK
pin
125
RC7/RX/DT
pin
126
Note: Refer to Figure 21-4 for load conditions.
TABLE 21-14: EUSART SYNCHRONOUS RECEIVE REQUIREMENTS
Param.
Symbol
Characteristic
Min
Max
Units
Conditions
No.
125
TDTV2CKL SYNC RCV (MASTER & SLAVE)
Data Hold before CK ↓ (DT hold time)
10
15
—
—
ns
ns
126
TCKL2DTL Data Hold after CK ↓ (DT hold time)
© 2008 Microchip Technology Inc.
DS39760D-page 291
PIC18F2450/4450
FIGURE 21-13:
USB SIGNAL TIMING
USB Data Differential Lines
90%
VCRS
10%
TLF, TFF
TLR, TFR
TABLE 21-15: USB LOW-SPEED TIMING REQUIREMENTS
Param
Symbol
Characteristic
Min
Typ
Max
Units
Conditions
No.
TLR
Transition Rise Time
75
75
80
—
—
—
300
300
125
ns
ns
%
CL = 200 to 600 pF
CL = 200 to 600 pF
TLF
Transition Fall Time
TLRFM
Rise/Fall Time Matching
TABLE 21-16: USB FULL-SPEED REQUIREMENTS
Param
Symbol
Characteristic
Min
Typ
Max
Units
Conditions
No.
TFR
Transition Rise Time
4
4
—
—
—
20
20
ns
ns
%
CL = 50 pF
CL = 50 pF
TFF
Transition Fall Time
TFRFM
Rise/Fall Time Matching
90
111.1
DS39760D-page 292
© 2008 Microchip Technology Inc.
PIC18F2450/4450
TABLE 21-17: A/D CONVERTER CHARACTERISTICS: PIC18F2450/4450 (INDUSTRIAL)
PIC18LF2450/4450 (INDUSTRIAL)
Param
No.
Symbol
Characteristic
Min
Typ
Max
Units
Conditions
A01
A03
A04
A06
A07
A10
A20
NR
Resolution
—
—
—
—
—
—
10
bit ΔVREF ≥ 3.0V
EIL
Integral Linearity Error
Differential Linearity Error
Offset Error
—
<±1
<±1
<±2
<±1
LSb ΔVREF ≥ 3.0V
LSb ΔVREF ≥ 3.0V
LSb ΔVREF ≥ 3.0V
LSb ΔVREF ≥ 3.0V
EDL
EOFF
EGN
—
—
—
Gain Error
—
Monotonicity
Guaranteed(1)
—
VSS ≤ VAIN ≤ VREF
ΔVREF Reference Voltage Range
1.8
3
—
—
—
—
V
V
VDD < 3.0V
VDD ≥ 3.0V
(VREFH – VREFL)
A21
A22
A25
A30
VREFH Reference Voltage High
VSS
—
VREFH
VDD – 3.0V
VREFH
V
V
VREFL
VAIN
Reference Voltage Low
Analog Input Voltage
VSS – 0.3V
VREFL
—
—
—
—
V
ZAIN
Recommended Impedance of
Analog Voltage Source
2.5
kΩ
A50
IREF
VREF Input Current(2)
—
—
—
—
5
150
μA During VAIN acquisition.
μA During A/D conversion
cycle.
Note 1: The A/D conversion result never decreases with an increase in the input voltage and has no missing codes.
2: VREFH current is from RA3/AN3/VREF+ pin or VDD, whichever is selected as the VREFH source.
VREFL current is from RA2/AN2/VREF- pin or VSS, whichever is selected as the VREFL source.
FIGURE 21-14:
A/D CONVERSION TIMING
BSF ADCON0, GO
(Note 2)
131
130
Q4
132
A/D CLK
. . .
. . .
9
8
7
2
1
0
A/D DATA
ADRES
NEW_DATA
OLD_DATA
(1)
TCY
ADIF
GO
DONE
SAMPLING STOPPED
SAMPLE
Note 1: If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the SLEEPinstruction
to be executed.
2: This is a minimal RC delay (typically 100 ns), which also disconnects the holding capacitor from the analog input.
© 2008 Microchip Technology Inc.
DS39760D-page 293
PIC18F2450/4450
TABLE 21-18: A/D CONVERSION REQUIREMENTS
Param
Symbol
Characteristic
Min
Max
Units
Conditions
No.
130
TAD
A/D Clock Period
PIC18FXXXX
0.7
1.4
25(1)
25(1)
μs TOSC based, VREF ≥ 3.0V
PIC18LFXXXX
μs VDD = 2.0V,
TOSC based, VREF full range
PIC18FXXXX
2.0
3.0
6.0
9.0
μs A/D RC mode
PIC18LFXXXX
μs VDD = 2.0V,
A/D RC mode
131
132
TCNV
TACQ
Conversion Time
11
12
TAD
(not including acquisition time)(2)
Acquisition Time(3)
15
10
—
—
μs -40°C to +85°C
μs
0°C ≤ to ≤ +85°C
135
137
TSWC
TDIS
Switching Time from Convert → Sample
—
(Note 4)
Discharge Time
0.2
—
μs
Note 1: The time of the A/D clock period is dependent on the device frequency and the TAD clock divider.
2: ADRES registers may be read on the following TCY cycle.
3: The time for the holding capacitor to acquire the “New” input voltage when the voltage changes full scale
after the conversion (VDD to VSS or VSS to VDD). The source impedance (RS) on the input channels is 50Ω.
4: On the following cycle of the device clock.
DS39760D-page 294
© 2008 Microchip Technology Inc.
PIC18F2450/4450
22.0 PACKAGING INFORMATION
22.1 Package Marking Information
28-Lead SPDIP (Skinny DIP)
Example
e
3
PIC18F2450-I/SP
0810017
XXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXX
YYWWNNN
28-Lead SOIC
Example
e
3
XXXXXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXXXXX
PIC18F2450-E/SO
0810017
YYWWNNN
28-Lead QFN
Example
XXXXXXXX
XXXXXXXX
YYWWNNN
18F2450
3
e
-I/ML
0810017
Legend: XX...X Customer-specific information
Y
Year code (last digit of calendar year)
YY
WW
NNN
Year code (last 2 digits of calendar year)
Week code (week of January 1 is week ‘01’)
Alphanumeric traceability code
e
3
Pb-free JEDEC designator for Matte Tin (Sn)
*
This package is Pb-free. The Pb-free JEDEC designator (
can be found on the outer packaging for this package.
)
3
e
Note: In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
© 2008 Microchip Technology Inc.
DS39760D-page 295
PIC18F2450/4450
Package Marking Information (Continued)
40-Lead PDIP
Example
e
3
XXXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXXX
YYWWNNN
PIC18F4450-I/P
0810017
44-Lead TQFP
Example
-I/PT
XXXXXXXXXX
XXXXXXXXXX
XXXXXXXXXX
YYWWNNN
PIC18F4450
e
3
0810017
44-Lead QFN
Example
XXXXXXXXXX
XXXXXXXXXX
XXXXXXXXXX
YYWWNNN
PIC18F4450
e3
-I/ML
0810017
DS39760D-page 296
© 2008 Microchip Technology Inc.
PIC18F2450/4450
22.2 Package Details
The following sections give the technical details of the packages.
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ꢀꢁ ꢂꢃꢄꢅꢀꢅ ꢃ!"ꢆꢇꢅꢃꢄ#ꢈ$ꢅ%ꢈꢆ&"ꢉꢈꢅ'ꢆꢊꢅ ꢆꢉꢊ(ꢅ)"&ꢅ'"!&ꢅ)ꢈꢅꢇꢋꢌꢆ&ꢈ#ꢅ*ꢃ&ꢍꢃꢄꢅ&ꢍꢈꢅꢍꢆ&ꢌꢍꢈ#ꢅꢆꢉꢈꢆꢁ
ꢎꢁ ꢏꢅꢐꢃꢑꢄꢃ%ꢃꢌꢆꢄ&ꢅ,ꢍꢆꢉꢆꢌ&ꢈꢉꢃ!&ꢃꢌꢁ
-ꢁ ꢒꢃ'ꢈꢄ!ꢃꢋꢄ!ꢅꢒꢅꢆꢄ#ꢅ.ꢀꢅ#ꢋꢅꢄꢋ&ꢅꢃꢄꢌꢇ"#ꢈꢅ'ꢋꢇ#ꢅ%ꢇꢆ!ꢍꢅꢋꢉꢅꢓꢉꢋ&ꢉ"!ꢃꢋꢄ!ꢁꢅꢔꢋꢇ#ꢅ%ꢇꢆ!ꢍꢅꢋꢉꢅꢓꢉꢋ&ꢉ"!ꢃꢋꢄ!ꢅ!ꢍꢆꢇꢇꢅꢄꢋ&ꢅꢈ$ꢌꢈꢈ#ꢅꢁꢕꢀꢕ/ꢅꢓꢈꢉꢅ!ꢃ#ꢈꢁ
ꢖꢁ ꢒꢃ'ꢈꢄ!ꢃꢋꢄꢃꢄꢑꢅꢆꢄ#ꢅ&ꢋꢇꢈꢉꢆꢄꢌꢃꢄꢑꢅꢓꢈꢉꢅꢗꢐꢔ.ꢅ0ꢀꢖꢁꢘꢔꢁ
1ꢐ,2 1ꢆ!ꢃꢌꢅꢒꢃ'ꢈꢄ!ꢃꢋꢄꢁꢅꢙꢍꢈꢋꢉꢈ&ꢃꢌꢆꢇꢇꢊꢅꢈ$ꢆꢌ&ꢅ ꢆꢇ"ꢈꢅ!ꢍꢋ*ꢄꢅ*ꢃ&ꢍꢋ"&ꢅ&ꢋꢇꢈꢉꢆꢄꢌꢈ!ꢁ
ꢔꢃꢌꢉꢋꢌꢍꢃꢓ ꢙꢈꢌꢍꢄꢋꢇꢋꢑꢊ ꢒꢉꢆ*ꢃꢄꢑ ,ꢕꢖꢞꢕꢜꢕ1
© 2008 Microchip Technology Inc.
DS39760D-page 297
PIC18F2450/4450
ꢀꢁꢂꢃꢄꢅꢆꢇꢍꢎꢅꢏꢐꢊꢑꢇꢈꢙꢅꢎꢎꢇ#ꢓꢐꢎꢊꢋꢄꢇꢕꢈ#ꢖꢇMꢇ$ꢊꢆꢄ%ꢇ&'(ꢘꢇꢙꢙꢇꢚꢛꢆꢌꢇꢜꢈ#ꢔ)
!ꢛꢐꢄ" 3ꢋꢉꢅ&ꢍꢈꢅ'ꢋ!&ꢅꢌ"ꢉꢉꢈꢄ&ꢅꢓꢆꢌ4ꢆꢑꢈꢅ#ꢉꢆ*ꢃꢄꢑ!(ꢅꢓꢇꢈꢆ!ꢈꢅ!ꢈꢈꢅ&ꢍꢈꢅꢔꢃꢌꢉꢋꢌꢍꢃꢓꢅꢂꢆꢌ4ꢆꢑꢃꢄꢑꢅꢐꢓꢈꢌꢃ%ꢃꢌꢆ&ꢃꢋꢄꢅꢇꢋꢌꢆ&ꢈ#ꢅꢆ&ꢅ
ꢍ&&ꢓ255***ꢁ'ꢃꢌꢉꢋꢌꢍꢃꢓꢁꢌꢋ'5ꢓꢆꢌ4ꢆꢑꢃꢄꢑ
D
N
E
E1
NOTE 1
1
2
3
e
b
h
α
h
c
φ
A2
A
L
A1
L1
β
6ꢄꢃ&!
ꢔꢚ99ꢚꢔ.ꢙ.ꢝꢐ
ꢒꢃ'ꢈꢄ!ꢃꢋꢄꢅ9ꢃ'ꢃ&!
ꢔꢚ7
7:ꢔ
ꢔꢗ;
7"')ꢈꢉꢅꢋ%ꢅꢂꢃꢄ!
ꢂꢃ&ꢌꢍ
7
ꢈ
ꢎ<
ꢀꢁꢎꢜꢅ1ꢐ,
: ꢈꢉꢆꢇꢇꢅ8ꢈꢃꢑꢍ&
ꢔꢋꢇ#ꢈ#ꢅꢂꢆꢌ4ꢆꢑꢈꢅꢙꢍꢃꢌ4ꢄꢈ!!
ꢐ&ꢆꢄ#ꢋ%%ꢅꢅꢏ
ꢗ
M
ꢎꢁꢕꢘ
ꢕꢁꢀꢕ
M
M
M
ꢎꢁ?ꢘ
M
ꢕꢁ-ꢕ
ꢗꢎ
ꢗꢀ
.
: ꢈꢉꢆꢇꢇꢅ>ꢃ#&ꢍ
ꢀꢕꢁ-ꢕꢅ1ꢐ,
ꢔꢋꢇ#ꢈ#ꢅꢂꢆꢌ4ꢆꢑꢈꢅ>ꢃ#&ꢍ
: ꢈꢉꢆꢇꢇꢅ9ꢈꢄꢑ&ꢍ
,ꢍꢆ'%ꢈꢉꢅ@ꢋꢓ&ꢃꢋꢄꢆꢇA
3ꢋꢋ&ꢅ9ꢈꢄꢑ&ꢍ
.ꢀ
ꢒ
ꢍ
ꢜꢁꢘꢕꢅ1ꢐ,
ꢀꢜꢁꢛꢕꢅ1ꢐ,
ꢕꢁꢎꢘ
ꢕꢁꢖꢕ
M
M
ꢕꢁꢜꢘ
ꢀꢁꢎꢜ
9
3ꢋꢋ&ꢓꢉꢃꢄ&
9ꢀ
ꢀ
ꢀꢁꢖꢕꢅꢝ.3
3ꢋꢋ&ꢅꢗꢄꢑꢇꢈꢅꢙꢋꢓ
9ꢈꢆ#ꢅꢙꢍꢃꢌ4ꢄꢈ!!
9ꢈꢆ#ꢅ>ꢃ#&ꢍ
ꢔꢋꢇ#ꢅꢒꢉꢆ%&ꢅꢗꢄꢑꢇꢈꢅꢙꢋꢓ
ꢔꢋꢇ#ꢅꢒꢉꢆ%&ꢅꢗꢄꢑꢇꢈꢅ1ꢋ&&ꢋ'
ꢕꢟ
ꢕꢁꢀ<
ꢕꢁ-ꢀ
ꢘꢟ
M
M
M
M
M
<ꢟ
ꢌ
)
ꢁ
ꢕꢁ--
ꢕꢁꢘꢀ
ꢀꢘꢟ
ꢂ
ꢘꢟ
ꢀꢘꢟ
!ꢛꢐꢄꢏ"
ꢀꢁ ꢂꢃꢄꢅꢀꢅ ꢃ!"ꢆꢇꢅꢃꢄ#ꢈ$ꢅ%ꢈꢆ&"ꢉꢈꢅ'ꢆꢊꢅ ꢆꢉꢊ(ꢅ)"&ꢅ'"!&ꢅ)ꢈꢅꢇꢋꢌꢆ&ꢈ#ꢅ*ꢃ&ꢍꢃꢄꢅ&ꢍꢈꢅꢍꢆ&ꢌꢍꢈ#ꢅꢆꢉꢈꢆꢁ
ꢎꢁ ꢏꢅꢐꢃꢑꢄꢃ%ꢃꢌꢆꢄ&ꢅ,ꢍꢆꢉꢆꢌ&ꢈꢉꢃ!&ꢃꢌꢁ
-ꢁ ꢒꢃ'ꢈꢄ!ꢃꢋꢄ!ꢅꢒꢅꢆꢄ#ꢅ.ꢀꢅ#ꢋꢅꢄꢋ&ꢅꢃꢄꢌꢇ"#ꢈꢅ'ꢋꢇ#ꢅ%ꢇꢆ!ꢍꢅꢋꢉꢅꢓꢉꢋ&ꢉ"!ꢃꢋꢄ!ꢁꢅꢔꢋꢇ#ꢅ%ꢇꢆ!ꢍꢅꢋꢉꢅꢓꢉꢋ&ꢉ"!ꢃꢋꢄ!ꢅ!ꢍꢆꢇꢇꢅꢄꢋ&ꢅꢈ$ꢌꢈꢈ#ꢅꢕꢁꢀꢘꢅ''ꢅꢓꢈꢉꢅ!ꢃ#ꢈꢁ
ꢖꢁ ꢒꢃ'ꢈꢄ!ꢃꢋꢄꢃꢄꢑꢅꢆꢄ#ꢅ&ꢋꢇꢈꢉꢆꢄꢌꢃꢄꢑꢅꢓꢈꢉꢅꢗꢐꢔ.ꢅ0ꢀꢖꢁꢘꢔꢁ
1ꢐ,2 1ꢆ!ꢃꢌꢅꢒꢃ'ꢈꢄ!ꢃꢋꢄꢁꢅꢙꢍꢈꢋꢉꢈ&ꢃꢌꢆꢇꢇꢊꢅꢈ$ꢆꢌ&ꢅ ꢆꢇ"ꢈꢅ!ꢍꢋ*ꢄꢅ*ꢃ&ꢍꢋ"&ꢅ&ꢋꢇꢈꢉꢆꢄꢌꢈ!ꢁ
ꢝ.32 ꢝꢈ%ꢈꢉꢈꢄꢌꢈꢅꢒꢃ'ꢈꢄ!ꢃꢋꢄ(ꢅ"!"ꢆꢇꢇꢊꢅ*ꢃ&ꢍꢋ"&ꢅ&ꢋꢇꢈꢉꢆꢄꢌꢈ(ꢅ%ꢋꢉꢅꢃꢄ%ꢋꢉ'ꢆ&ꢃꢋꢄꢅꢓ"ꢉꢓꢋ!ꢈ!ꢅꢋꢄꢇꢊꢁ
ꢔꢃꢌꢉꢋꢌꢍꢃꢓ ꢙꢈꢌꢍꢄꢋꢇꢋꢑꢊ ꢒꢉꢆ*ꢃꢄꢑ ,ꢕꢖꢞꢕꢘꢎ1
DS39760D-page 298
© 2008 Microchip Technology Inc.
PIC18F2450/4450
ꢀꢁꢂꢃꢄꢅꢆꢇꢍꢎꢅꢏꢐꢊꢑꢇ*ꢓꢅꢆꢇ+ꢎꢅꢐ%ꢇ!ꢛꢇꢃꢄꢅꢆꢇꢍꢅꢑꢉꢅ,ꢄꢇꢕ-ꢃꢖꢇMꢇ./.ꢇꢙꢙꢇꢚꢛꢆꢌꢇꢜ*+!
0ꢊꢐ1ꢇꢘ'((ꢇꢙꢙꢇ)ꢛꢋꢐꢅꢑꢐꢇꢃꢄꢋ,ꢐ1
!ꢛꢐꢄ" 3ꢋꢉꢅ&ꢍꢈꢅ'ꢋ!&ꢅꢌ"ꢉꢉꢈꢄ&ꢅꢓꢆꢌ4ꢆꢑꢈꢅ#ꢉꢆ*ꢃꢄꢑ!(ꢅꢓꢇꢈꢆ!ꢈꢅ!ꢈꢈꢅ&ꢍꢈꢅꢔꢃꢌꢉꢋꢌꢍꢃꢓꢅꢂꢆꢌ4ꢆꢑꢃꢄꢑꢅꢐꢓꢈꢌꢃ%ꢃꢌꢆ&ꢃꢋꢄꢅꢇꢋꢌꢆ&ꢈ#ꢅꢆ&ꢅ
ꢍ&&ꢓ255***ꢁ'ꢃꢌꢉꢋꢌꢍꢃꢓꢁꢌꢋ'5ꢓꢆꢌ4ꢆꢑꢃꢄꢑ
D
D2
EXPOSED
PAD
e
E
b
E2
2
1
2
1
K
N
N
NOTE 1
L
BOTTOM VIEW
TOP VIEW
A
A3
A1
6ꢄꢃ&!
ꢒꢃ'ꢈꢄ!ꢃꢋꢄꢅ9ꢃ'ꢃ&!
ꢔꢚ99ꢚꢔ.ꢙ.ꢝꢐ
7:ꢔ
ꢔꢚ7
ꢔꢗ;
7"')ꢈꢉꢅꢋ%ꢅꢂꢃꢄ!
ꢂꢃ&ꢌꢍ
: ꢈꢉꢆꢇꢇꢅ8ꢈꢃꢑꢍ&
ꢐ&ꢆꢄ#ꢋ%%ꢅ
,ꢋꢄ&ꢆꢌ&ꢅꢙꢍꢃꢌ4ꢄꢈ!!
: ꢈꢉꢆꢇꢇꢅ>ꢃ#&ꢍ
.$ꢓꢋ!ꢈ#ꢅꢂꢆ#ꢅ>ꢃ#&ꢍ
: ꢈꢉꢆꢇꢇꢅ9ꢈꢄꢑ&ꢍ
.$ꢓꢋ!ꢈ#ꢅꢂꢆ#ꢅ9ꢈꢄꢑ&ꢍ
,ꢋꢄ&ꢆꢌ&ꢅ>ꢃ#&ꢍ
,ꢋꢄ&ꢆꢌ&ꢅ9ꢈꢄꢑ&ꢍ
,ꢋꢄ&ꢆꢌ&ꢞ&ꢋꢞ.$ꢓꢋ!ꢈ#ꢅꢂꢆ#
7
ꢈ
ꢗ
ꢗꢀ
ꢗ-
.
.ꢎ
ꢒ
ꢎ<
ꢕꢁ?ꢘꢅ1ꢐ,
ꢕꢁꢛꢕ
ꢕꢁ<ꢕ
ꢕꢁꢕꢕ
ꢀꢁꢕꢕ
ꢕꢁꢕꢘ
ꢕꢁꢕꢎ
ꢕꢁꢎꢕꢅꢝ.3
?ꢁꢕꢕꢅ1ꢐ,
-ꢁꢜꢕ
?ꢁꢕꢕꢅ1ꢐ,
-ꢁꢜꢕ
ꢕꢁ-ꢕ
ꢕꢁꢘꢘ
M
-ꢁ?ꢘ
ꢖꢁꢎꢕ
ꢒꢎ
)
9
-ꢁ?ꢘ
ꢕꢁꢎ-
ꢕꢁꢘꢕ
ꢕꢁꢎꢕ
ꢖꢁꢎꢕ
ꢕꢁ-ꢘ
ꢕꢁꢜꢕ
M
C
!ꢛꢐꢄꢏ"
ꢀꢁ ꢂꢃꢄꢅꢀꢅ ꢃ!"ꢆꢇꢅꢃꢄ#ꢈ$ꢅ%ꢈꢆ&"ꢉꢈꢅ'ꢆꢊꢅ ꢆꢉꢊ(ꢅ)"&ꢅ'"!&ꢅ)ꢈꢅꢇꢋꢌꢆ&ꢈ#ꢅ*ꢃ&ꢍꢃꢄꢅ&ꢍꢈꢅꢍꢆ&ꢌꢍꢈ#ꢅꢆꢉꢈꢆꢁ
ꢎꢁ ꢂꢆꢌ4ꢆꢑꢈꢅꢃ!ꢅ!ꢆ*ꢅ!ꢃꢄꢑ"ꢇꢆ&ꢈ#ꢁ
-ꢁ ꢒꢃ'ꢈꢄ!ꢃꢋꢄꢃꢄꢑꢅꢆꢄ#ꢅ&ꢋꢇꢈꢉꢆꢄꢌꢃꢄꢑꢅꢓꢈꢉꢅꢗꢐꢔ.ꢅ0ꢀꢖꢁꢘꢔꢁ
1ꢐ,2 1ꢆ!ꢃꢌꢅꢒꢃ'ꢈꢄ!ꢃꢋꢄꢁꢅꢙꢍꢈꢋꢉꢈ&ꢃꢌꢆꢇꢇꢊꢅꢈ$ꢆꢌ&ꢅ ꢆꢇ"ꢈꢅ!ꢍꢋ*ꢄꢅ*ꢃ&ꢍꢋ"&ꢅ&ꢋꢇꢈꢉꢆꢄꢌꢈ!ꢁ
ꢝ.32 ꢝꢈ%ꢈꢉꢈꢄꢌꢈꢅꢒꢃ'ꢈꢄ!ꢃꢋꢄ(ꢅ"!"ꢆꢇꢇꢊꢅ*ꢃ&ꢍꢋ"&ꢅ&ꢋꢇꢈꢉꢆꢄꢌꢈ(ꢅ%ꢋꢉꢅꢃꢄ%ꢋꢉ'ꢆ&ꢃꢋꢄꢅꢓ"ꢉꢓꢋ!ꢈ!ꢅꢋꢄꢇꢊꢁ
ꢔꢃꢌꢉꢋꢌꢍꢃꢓ ꢙꢈꢌꢍꢄꢋꢇꢋꢑꢊ ꢒꢉꢆ*ꢃꢄꢑ ,ꢕꢖꢞꢀꢕꢘ1
© 2008 Microchip Technology Inc.
DS39760D-page 299
PIC18F2450/4450
ꢀꢁꢂꢃꢄꢅꢆꢇꢍꢎꢅꢏꢐꢊꢑꢇ*ꢓꢅꢆꢇ+ꢎꢅꢐ%ꢇ!ꢛꢇꢃꢄꢅꢆꢇꢍꢅꢑꢉꢅ,ꢄꢇꢕ-ꢃꢖꢇMꢇ./.ꢇꢙꢙꢇꢚꢛꢆꢌꢇꢜ*+!
0ꢊꢐ1ꢇꢘ'((ꢇꢙꢙꢇ)ꢛꢋꢐꢅꢑꢐꢇꢃꢄꢋ,ꢐ1
!ꢛꢐꢄ" 3ꢋꢉꢅ&ꢍꢈꢅ'ꢋ!&ꢅꢌ"ꢉꢉꢈꢄ&ꢅꢓꢆꢌ4ꢆꢑꢈꢅ#ꢉꢆ*ꢃꢄꢑ!(ꢅꢓꢇꢈꢆ!ꢈꢅ!ꢈꢈꢅ&ꢍꢈꢅꢔꢃꢌꢉꢋꢌꢍꢃꢓꢅꢂꢆꢌ4ꢆꢑꢃꢄꢑꢅꢐꢓꢈꢌꢃ%ꢃꢌꢆ&ꢃꢋꢄꢅꢇꢋꢌꢆ&ꢈ#ꢅꢆ&ꢅ
ꢍ&&ꢓ255***ꢁ'ꢃꢌꢉꢋꢌꢍꢃꢓꢁꢌꢋ'5ꢓꢆꢌ4ꢆꢑꢃꢄꢑ
DS39760D-page 300
© 2008 Microchip Technology Inc.
PIC18F2450/4450
2ꢘꢂꢃꢄꢅꢆꢇꢍꢎꢅꢏꢐꢊꢑꢇꢒꢓꢅꢎꢇꢔꢋꢂꢃꢊꢋꢄꢇꢕꢍꢖꢇMꢇ.ꢘꢘꢇꢙꢊꢎꢇꢚꢛꢆꢌꢇꢜꢍꢒꢔꢍ
!ꢛꢐꢄ" 3ꢋꢉꢅ&ꢍꢈꢅ'ꢋ!&ꢅꢌ"ꢉꢉꢈꢄ&ꢅꢓꢆꢌ4ꢆꢑꢈꢅ#ꢉꢆ*ꢃꢄꢑ!(ꢅꢓꢇꢈꢆ!ꢈꢅ!ꢈꢈꢅ&ꢍꢈꢅꢔꢃꢌꢉꢋꢌꢍꢃꢓꢅꢂꢆꢌ4ꢆꢑꢃꢄꢑꢅꢐꢓꢈꢌꢃ%ꢃꢌꢆ&ꢃꢋꢄꢅꢇꢋꢌꢆ&ꢈ#ꢅꢆ&ꢅ
ꢍ&&ꢓ255***ꢁ'ꢃꢌꢉꢋꢌꢍꢃꢓꢁꢌꢋ'5ꢓꢆꢌ4ꢆꢑꢃꢄꢑ
N
NOTE 1
E1
1 2 3
D
E
A2
A
L
c
b1
b
A1
e
eB
6ꢄꢃ&!
ꢚ7,8.ꢐ
ꢒꢃ'ꢈꢄ!ꢃꢋꢄꢅ9ꢃ'ꢃ&!
ꢔꢚ7
7:ꢔ
ꢔꢗ;
7"')ꢈꢉꢅꢋ%ꢅꢂꢃꢄ!
ꢂꢃ&ꢌꢍ
7
ꢈ
ꢖꢕ
ꢁꢀꢕꢕꢅ1ꢐ,
ꢙꢋꢓꢅ&ꢋꢅꢐꢈꢆ&ꢃꢄꢑꢅꢂꢇꢆꢄꢈ
ꢔꢋꢇ#ꢈ#ꢅꢂꢆꢌ4ꢆꢑꢈꢅꢙꢍꢃꢌ4ꢄꢈ!!
1ꢆ!ꢈꢅ&ꢋꢅꢐꢈꢆ&ꢃꢄꢑꢅꢂꢇꢆꢄꢈ
ꢐꢍꢋ"ꢇ#ꢈꢉꢅ&ꢋꢅꢐꢍꢋ"ꢇ#ꢈꢉꢅ>ꢃ#&ꢍ
ꢔꢋꢇ#ꢈ#ꢅꢂꢆꢌ4ꢆꢑꢈꢅ>ꢃ#&ꢍ
: ꢈꢉꢆꢇꢇꢅ9ꢈꢄꢑ&ꢍ
ꢙꢃꢓꢅ&ꢋꢅꢐꢈꢆ&ꢃꢄꢑꢅꢂꢇꢆꢄꢈ
9ꢈꢆ#ꢅꢙꢍꢃꢌ4ꢄꢈ!!
6ꢓꢓꢈꢉꢅ9ꢈꢆ#ꢅ>ꢃ#&ꢍ
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!ꢛꢐꢄꢏ"
ꢀꢁ ꢂꢃꢄꢅꢀꢅ ꢃ!"ꢆꢇꢅꢃꢄ#ꢈ$ꢅ%ꢈꢆ&"ꢉꢈꢅ'ꢆꢊꢅ ꢆꢉꢊ(ꢅ)"&ꢅ'"!&ꢅ)ꢈꢅꢇꢋꢌꢆ&ꢈ#ꢅ*ꢃ&ꢍꢃꢄꢅ&ꢍꢈꢅꢍꢆ&ꢌꢍꢈ#ꢅꢆꢉꢈꢆꢁ
ꢎꢁ ꢏꢅꢐꢃꢑꢄꢃ%ꢃꢌꢆꢄ&ꢅ,ꢍꢆꢉꢆꢌ&ꢈꢉꢃ!&ꢃꢌꢁ
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ꢖꢁ ꢒꢃ'ꢈꢄ!ꢃꢋꢄꢃꢄꢑꢅꢆꢄ#ꢅ&ꢋꢇꢈꢉꢆꢄꢌꢃꢄꢑꢅꢓꢈꢉꢅꢗꢐꢔ.ꢅ0ꢀꢖꢁꢘꢔꢁ
1ꢐ,2 1ꢆ!ꢃꢌꢅꢒꢃ'ꢈꢄ!ꢃꢋꢄꢁꢅꢙꢍꢈꢋꢉꢈ&ꢃꢌꢆꢇꢇꢊꢅꢈ$ꢆꢌ&ꢅ ꢆꢇ"ꢈꢅ!ꢍꢋ*ꢄꢅ*ꢃ&ꢍꢋ"&ꢅ&ꢋꢇꢈꢉꢆꢄꢌꢈ!ꢁ
ꢔꢃꢌꢉꢋꢌꢍꢃꢓ ꢙꢈꢌꢍꢄꢋꢇꢋꢑꢊ ꢒꢉꢆ*ꢃꢄꢑ ,ꢕꢖꢞꢕꢀ?1
© 2008 Microchip Technology Inc.
DS39760D-page 301
PIC18F2450/4450
22ꢂꢃꢄꢅꢆꢇꢍꢎꢅꢏꢐꢊꢑꢇ31ꢊꢋꢇ*ꢓꢅꢆꢇ+ꢎꢅꢐ4ꢅꢑꢉꢇꢕꢍ3ꢖꢇMꢇ5ꢘ/5ꢘ/5ꢇꢙꢙꢇꢚꢛꢆꢌ%ꢇꢀ'ꢘꢘꢇꢙꢙꢇꢜ3*+ꢍ
!ꢛꢐꢄ" 3ꢋꢉꢅ&ꢍꢈꢅ'ꢋ!&ꢅꢌ"ꢉꢉꢈꢄ&ꢅꢓꢆꢌ4ꢆꢑꢈꢅ#ꢉꢆ*ꢃꢄꢑ!(ꢅꢓꢇꢈꢆ!ꢈꢅ!ꢈꢈꢅ&ꢍꢈꢅꢔꢃꢌꢉꢋꢌꢍꢃꢓꢅꢂꢆꢌ4ꢆꢑꢃꢄꢑꢅꢐꢓꢈꢌꢃ%ꢃꢌꢆ&ꢃꢋꢄꢅꢇꢋꢌꢆ&ꢈ#ꢅꢆ&ꢅ
ꢍ&&ꢓ255***ꢁ'ꢃꢌꢉꢋꢌꢍꢃꢓꢁꢌꢋ'5ꢓꢆꢌ4ꢆꢑꢃꢄꢑ
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ꢔꢋꢇ#ꢈ#ꢅꢂꢆꢌ4ꢆꢑꢈꢅꢙꢍꢃꢌ4ꢄꢈ!!
ꢐ&ꢆꢄ#ꢋ%%ꢅꢅ
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M
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9ꢈꢆ#ꢅꢙꢍꢃꢌ4ꢄꢈ!!
9ꢈꢆ#ꢅ>ꢃ#&ꢍ
ꢔꢋꢇ#ꢅꢒꢉꢆ%&ꢅꢗꢄꢑꢇꢈꢅꢙꢋꢓ
ꢔꢋꢇ#ꢅꢒꢉꢆ%&ꢅꢗꢄꢑꢇꢈꢅ1ꢋ&&ꢋ'
ꢕꢁꢕꢛ
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ꢀꢎꢟ
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ꢀꢀꢟ
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!ꢛꢐꢄꢏ"
ꢀꢁ ꢂꢃꢄꢅꢀꢅ ꢃ!"ꢆꢇꢅꢃꢄ#ꢈ$ꢅ%ꢈꢆ&"ꢉꢈꢅ'ꢆꢊꢅ ꢆꢉꢊ(ꢅ)"&ꢅ'"!&ꢅ)ꢈꢅꢇꢋꢌꢆ&ꢈ#ꢅ*ꢃ&ꢍꢃꢄꢅ&ꢍꢈꢅꢍꢆ&ꢌꢍꢈ#ꢅꢆꢉꢈꢆꢁ
ꢎꢁ ,ꢍꢆ'%ꢈꢉ!ꢅꢆ&ꢅꢌꢋꢉꢄꢈꢉ!ꢅꢆꢉꢈꢅꢋꢓ&ꢃꢋꢄꢆꢇDꢅ!ꢃEꢈꢅ'ꢆꢊꢅ ꢆꢉꢊꢁ
-ꢁ ꢒꢃ'ꢈꢄ!ꢃꢋꢄ!ꢅꢒꢀꢅꢆꢄ#ꢅ.ꢀꢅ#ꢋꢅꢄꢋ&ꢅꢃꢄꢌꢇ"#ꢈꢅ'ꢋꢇ#ꢅ%ꢇꢆ!ꢍꢅꢋꢉꢅꢓꢉꢋ&ꢉ"!ꢃꢋꢄ!ꢁꢅꢔꢋꢇ#ꢅ%ꢇꢆ!ꢍꢅꢋꢉꢅꢓꢉꢋ&ꢉ"!ꢃꢋꢄ!ꢅ!ꢍꢆꢇꢇꢅꢄꢋ&ꢅꢈ$ꢌꢈꢈ#ꢅꢕꢁꢎꢘꢅ''ꢅꢓꢈꢉꢅ!ꢃ#ꢈꢁ
ꢖꢁ ꢒꢃ'ꢈꢄ!ꢃꢋꢄꢃꢄꢑꢅꢆꢄ#ꢅ&ꢋꢇꢈꢉꢆꢄꢌꢃꢄꢑꢅꢓꢈꢉꢅꢗꢐꢔ.ꢅ0ꢀꢖꢁꢘꢔꢁ
1ꢐ,2 1ꢆ!ꢃꢌꢅꢒꢃ'ꢈꢄ!ꢃꢋꢄꢁꢅꢙꢍꢈꢋꢉꢈ&ꢃꢌꢆꢇꢇꢊꢅꢈ$ꢆꢌ&ꢅ ꢆꢇ"ꢈꢅ!ꢍꢋ*ꢄꢅ*ꢃ&ꢍꢋ"&ꢅ&ꢋꢇꢈꢉꢆꢄꢌꢈ!ꢁ
ꢝ.32 ꢝꢈ%ꢈꢉꢈꢄꢌꢈꢅꢒꢃ'ꢈꢄ!ꢃꢋꢄ(ꢅ"!"ꢆꢇꢇꢊꢅ*ꢃ&ꢍꢋ"&ꢅ&ꢋꢇꢈꢉꢆꢄꢌꢈ(ꢅ%ꢋꢉꢅꢃꢄ%ꢋꢉ'ꢆ&ꢃꢋꢄꢅꢓ"ꢉꢓꢋ!ꢈ!ꢅꢋꢄꢇꢊꢁ
ꢔꢃꢌꢉꢋꢌꢍꢃꢓ ꢙꢈꢌꢍꢄꢋꢇꢋꢑꢊ ꢒꢉꢆ*ꢃꢄꢑ ,ꢕꢖꢞꢕꢜ?1
DS39760D-page 302
© 2008 Microchip Technology Inc.
PIC18F2450/4450
22ꢂꢃꢄꢅꢆꢇꢍꢎꢅꢏꢐꢊꢑꢇ31ꢊꢋꢇ*ꢓꢅꢆꢇ+ꢎꢅꢐ4ꢅꢑꢉꢇꢕꢍ3ꢖꢇMꢇ5ꢘ/5ꢘ/5ꢇꢙꢙꢇꢚꢛꢆꢌ%ꢇꢀ'ꢘꢘꢇꢙꢙꢇꢜ3*+ꢍ
!ꢛꢐꢄ" 3ꢋꢉꢅ&ꢍꢈꢅ'ꢋ!&ꢅꢌ"ꢉꢉꢈꢄ&ꢅꢓꢆꢌ4ꢆꢑꢈꢅ#ꢉꢆ*ꢃꢄꢑ!(ꢅꢓꢇꢈꢆ!ꢈꢅ!ꢈꢈꢅ&ꢍꢈꢅꢔꢃꢌꢉꢋꢌꢍꢃꢓꢅꢂꢆꢌ4ꢆꢑꢃꢄꢑꢅꢐꢓꢈꢌꢃ%ꢃꢌꢆ&ꢃꢋꢄꢅꢇꢋꢌꢆ&ꢈ#ꢅꢆ&ꢅ
ꢍ&&ꢓ255***ꢁ'ꢃꢌꢉꢋꢌꢍꢃꢓꢁꢌꢋ'5ꢓꢆꢌ4ꢆꢑꢃꢄꢑ
© 2008 Microchip Technology Inc.
DS39760D-page 303
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22ꢂꢃꢄꢅꢆꢇꢍꢎꢅꢏꢐꢊꢑꢇ*ꢓꢅꢆꢇ+ꢎꢅꢐ%ꢇ!ꢛꢇꢃꢄꢅꢆꢇꢍꢅꢑꢉꢅ,ꢄꢇꢕ-ꢃꢖꢇMꢇꢁ/ꢁꢇꢙꢙꢇꢚꢛꢆꢌꢇꢜ*+!
!ꢛꢐꢄ" 3ꢋꢉꢅ&ꢍꢈꢅ'ꢋ!&ꢅꢌ"ꢉꢉꢈꢄ&ꢅꢓꢆꢌ4ꢆꢑꢈꢅ#ꢉꢆ*ꢃꢄꢑ!(ꢅꢓꢇꢈꢆ!ꢈꢅ!ꢈꢈꢅ&ꢍꢈꢅꢔꢃꢌꢉꢋꢌꢍꢃꢓꢅꢂꢆꢌ4ꢆꢑꢃꢄꢑꢅꢐꢓꢈꢌꢃ%ꢃꢌꢆ&ꢃꢋꢄꢅꢇꢋꢌꢆ&ꢈ#ꢅꢆ&ꢅ
ꢍ&&ꢓ255***ꢁ'ꢃꢌꢉꢋꢌꢍꢃꢓꢁꢌꢋ'5ꢓꢆꢌ4ꢆꢑꢃꢄꢑ
D2
D
EXPOSED
PAD
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2
1
2
1
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L
TOP VIEW
BOTTOM VIEW
A
A3
A1
6ꢄꢃ&!
ꢔꢚ99ꢚꢔ.ꢙ.ꢝꢐ
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ꢂꢃ&ꢌꢍ
: ꢈꢉꢆꢇꢇꢅ8ꢈꢃꢑꢍ&
ꢐ&ꢆꢄ#ꢋ%%ꢅ
,ꢋꢄ&ꢆꢌ&ꢅꢙꢍꢃꢌ4ꢄꢈ!!
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!ꢛꢐꢄꢏ"
ꢀꢁ ꢂꢃꢄꢅꢀꢅ ꢃ!"ꢆꢇꢅꢃꢄ#ꢈ$ꢅ%ꢈꢆ&"ꢉꢈꢅ'ꢆꢊꢅ ꢆꢉꢊ(ꢅ)"&ꢅ'"!&ꢅ)ꢈꢅꢇꢋꢌꢆ&ꢈ#ꢅ*ꢃ&ꢍꢃꢄꢅ&ꢍꢈꢅꢍꢆ&ꢌꢍꢈ#ꢅꢆꢉꢈꢆꢁ
ꢎꢁ ꢂꢆꢌ4ꢆꢑꢈꢅꢃ!ꢅ!ꢆ*ꢅ!ꢃꢄꢑ"ꢇꢆ&ꢈ#ꢁ
-ꢁ ꢒꢃ'ꢈꢄ!ꢃꢋꢄꢃꢄꢑꢅꢆꢄ#ꢅ&ꢋꢇꢈꢉꢆꢄꢌꢃꢄꢑꢅꢓꢈꢉꢅꢗꢐꢔ.ꢅ0ꢀꢖꢁꢘꢔꢁ
1ꢐ,2 1ꢆ!ꢃꢌꢅꢒꢃ'ꢈꢄ!ꢃꢋꢄꢁꢅꢙꢍꢈꢋꢉꢈ&ꢃꢌꢆꢇꢇꢊꢅꢈ$ꢆꢌ&ꢅ ꢆꢇ"ꢈꢅ!ꢍꢋ*ꢄꢅ*ꢃ&ꢍꢋ"&ꢅ&ꢋꢇꢈꢉꢆꢄꢌꢈ!ꢁ
ꢝ.32 ꢝꢈ%ꢈꢉꢈꢄꢌꢈꢅꢒꢃ'ꢈꢄ!ꢃꢋꢄ(ꢅ"!"ꢆꢇꢇꢊꢅ*ꢃ&ꢍꢋ"&ꢅ&ꢋꢇꢈꢉꢆꢄꢌꢈ(ꢅ%ꢋꢉꢅꢃꢄ%ꢋꢉ'ꢆ&ꢃꢋꢄꢅꢓ"ꢉꢓꢋ!ꢈ!ꢅꢋꢄꢇꢊꢁ
ꢔꢃꢌꢉꢋꢌꢍꢃꢓ ꢙꢈꢌꢍꢄꢋꢇꢋꢑꢊ ꢒꢉꢆ*ꢃꢄꢑ ,ꢕꢖꢞꢀꢕ-1
DS39760D-page 304
© 2008 Microchip Technology Inc.
PIC18F2450/4450
22ꢂꢃꢄꢅꢆꢇꢍꢎꢅꢏꢐꢊꢑꢇ*ꢓꢅꢆꢇ+ꢎꢅꢐ%ꢇ!ꢛꢇꢃꢄꢅꢆꢇꢍꢅꢑꢉꢅ,ꢄꢇꢕ-ꢃꢖꢇMꢇꢁ/ꢁꢇꢙꢙꢇꢚꢛꢆꢌꢇꢜ*+!
!ꢛꢐꢄ" 3ꢋꢉꢅ&ꢍꢈꢅ'ꢋ!&ꢅꢌ"ꢉꢉꢈꢄ&ꢅꢓꢆꢌ4ꢆꢑꢈꢅ#ꢉꢆ*ꢃꢄꢑ!(ꢅꢓꢇꢈꢆ!ꢈꢅ!ꢈꢈꢅ&ꢍꢈꢅꢔꢃꢌꢉꢋꢌꢍꢃꢓꢅꢂꢆꢌ4ꢆꢑꢃꢄꢑꢅꢐꢓꢈꢌꢃ%ꢃꢌꢆ&ꢃꢋꢄꢅꢇꢋꢌꢆ&ꢈ#ꢅꢆ&ꢅ
ꢍ&&ꢓ255***ꢁ'ꢃꢌꢉꢋꢌꢍꢃꢓꢁꢌꢋ'5ꢓꢆꢌ4ꢆꢑꢃꢄꢑ
© 2008 Microchip Technology Inc.
DS39760D-page 305
PIC18F2450/4450
NOTES:
DS39760D-page 306
© 2008 Microchip Technology Inc.
PIC18F2450/4450
Revision C (August 2007)
APPENDIX A: REVISION HISTORY
The Electrical Specifications in Section 21.2 “DC
Characteristics: Power-Down and Supply Current”
have been updated and the package diagrams in
Section 22.2 “Package Details” have been updated.
Revision A (January 2006)
Original data sheet for PIC18F2450/4450 devices.
Revision B (January 2007)
Revision D (March 2008)
Example 11-1 and Figure 14-1 have been updated,
Section 14.5.1.1 “Bus Activity Detect Interrupt Bit
(ACTVIF)” and Section 14.2.2.3 “Internal Pull-up
Resistors” have been added, the Electrical Specifi-
cations in Section 21.0 “Electrical Characteris-
tics” have been updated, the package diagrams in
Section 22.2 “Package Details” have been updated
and there have been minor corrections to the data
sheet text.
Minor edits to Section 14.0 “Universal Serial Bus
(USB)”, Section 16.0 “10-Bit Analog-to-Digital
Converter (A/D) Module”, Section 18.0 “Special
Features of the CPU” and Section 21.0 “Electrical
Characteristics”.
© 2008 Microchip Technology Inc.
DS39760D-page 307
PIC18F2450/4450
APPENDIX B: DEVICE
DIFFERENCES
The differences between the devices listed in this data
sheet are shown in Table B-1.
TABLE B-1:
DEVICE DIFFERENCES
Features
PIC18F2450
PIC18F4450
Program Memory (Bytes)
Program Memory (Instructions)
Interrupt Sources
16384
16384
8192
8192
13
13
I/O Ports
Ports A, B, C, (E)
1
Ports A, B, C, D, E
1
Capture/Compare/PWM Modules
10-Bit Analog-to-Digital Module
Packages
10 Input Channels
13 Input Channels
28-Pin SPDIP
28-Pin SOIC
28-Pin QFN
40-Pin PDIP
44-Pin TQFP
44-Pin QFN
DS39760D-page 308
© 2008 Microchip Technology Inc.
PIC18F2450/4450
APPENDIX C: CONVERSION
CONSIDERATIONS
APPENDIX D: MIGRATION FROM
BASELINE TO
ENHANCED DEVICES
This appendix discusses the considerations for
converting from previous versions of a device to the
ones listed in this data sheet. Typically, these changes
are due to the differences in the process technology
used. An example of this type of conversion is from a
PIC16C74A to a PIC16C74B.
This section discusses how to migrate from a Baseline
device (i.e., PIC16C5X) to an Enhanced MCU device
(i.e., PIC18FXXX).
The following are the list of modifications over the
PIC16C5X microcontroller family:
Not Applicable
Not Currently Available
© 2008 Microchip Technology Inc.
DS39760D-page 309
PIC18F2450/4450
APPENDIX E: MIGRATION FROM
MID-RANGE TO
APPENDIX F: MIGRATION FROM
HIGH-END TO
ENHANCED DEVICES
ENHANCED DEVICES
A detailed discussion of the differences between the
Mid-Range MCU devices (i.e., PIC16CXXX) and the
Enhanced devices (i.e., PIC18FXXX) is provided in
AN716, “Migrating Designs from PIC16C74A/74B to
PIC18C442”. The changes discussed, while device
specific, are generally applicable to all Mid-Range to
Enhanced device migrations.
A detailed discussion of the migration pathway and
differences between the High-End MCU devices (i.e.,
PIC17CXXX) and the Enhanced devices (i.e.,
PIC18FXXX) is provided in AN726, “PIC17CXXX to
PIC18CXXX Migration”. This Application Note is
available as Literature Number DS00726.
This Application Note is available as Literature Number
DS00716.
DS39760D-page 310
© 2008 Microchip Technology Inc.
PIC18F2450/4450
INDEX
Generic I/O Port ......................................................... 99
High/Low-Voltage Detect with External Input .......... 186
Interrupt Logic ............................................................ 86
On-Chip Reset Circuit ................................................ 41
PIC18F2450 .............................................................. 10
PIC18F4450 .............................................................. 11
PLL (HS Mode) .......................................................... 26
PWM Operation (Simplified) .................................... 127
Reads from Flash Program Memory ......................... 77
Table Read Operation ............................................... 73
Table Write Operation ............................................... 74
Table Writes to Flash Program Memory .................... 79
Timer0 in 16-Bit Mode ............................................. 112
Timer0 in 8-Bit Mode ............................................... 112
Timer1 ..................................................................... 116
Timer1 (16-Bit Read/Write Mode) ............................ 116
Timer2 ..................................................................... 122
Typical External Transceiver with Isolation ............. 131
USB Interrupt Logic Funnel ..................................... 143
USB Peripheral and Options ................................... 129
USTAT FIFO ............................................................ 134
Watchdog Timer ...................................................... 203
BN .................................................................................... 222
BNC ................................................................................. 223
BNN ................................................................................. 223
BNOV .............................................................................. 224
BNZ ................................................................................. 224
BOR. See Brown-out Reset.
A
A/D ................................................................................... 175
Acquisition Requirements ........................................ 180
ADCON0 Register .................................................... 175
ADCON1 Register .................................................... 175
ADCON2 Register .................................................... 175
ADRESH Register ............................................ 175, 178
ADRESL Register .................................................... 175
Analog Port Pins, Configuring .................................. 182
Associated Registers ............................................... 184
Configuring the Module ............................................ 179
Conversion Clock (TAD) ........................................... 181
Conversion Requirements ....................................... 294
Conversion Status (GO/DONE Bit) .......................... 178
Conversions ............................................................. 183
Converter Characteristics ........................................ 293
Converter Interrupt, Configuring .............................. 179
Discharge ................................................................. 183
Operation in Power-Managed Modes ...................... 182
Selecting and Configuring Acquisition Time ............ 181
Special Event Trigger (CCP1) .................................. 184
Use of the CCP1 Trigger .......................................... 184
Absolute Maximum Ratings ............................................. 267
AC (Timing) Characteristics ............................................. 283
Load Conditions for Device Timing
Specifications ................................................... 284
Parameter Symbology ............................................. 283
Temperature and Voltage Specifications ................. 284
Timing Conditions .................................................... 284
AC Characteristics
BOV ................................................................................. 227
BRA ................................................................................. 225
Brown-out Reset (BOR) ..................................................... 44
Detecting ................................................................... 44
Disabling in Sleep Mode ............................................ 44
Software Enabled ...................................................... 44
BSF .................................................................................. 225
BTFSC ............................................................................. 226
BTFSS ............................................................................. 226
BTG ................................................................................. 227
BZ .................................................................................... 228
Internal RC Accuracy ............................................... 286
ADCON0 Register ............................................................ 175
GO/DONE Bit ........................................................... 178
ADCON1 Register ............................................................ 175
ADCON2 Register ............................................................ 175
ADDFSR .......................................................................... 256
ADDLW ............................................................................ 219
ADDULNK ........................................................................ 256
ADDWF ............................................................................ 219
ADDWFC ......................................................................... 220
ADRESH Register ............................................................ 175
ADRESL Register .................................................... 175, 178
Analog-to-Digital Converter. See A/D.
C
C Compilers
MPLAB C18 ............................................................. 264
MPLAB C30 ............................................................. 264
CALL ................................................................................ 228
CALLW ............................................................................ 257
Capture (CCP Module) .................................................... 124
Associated Registers ............................................... 126
CCP1 Pin Configuration .......................................... 124
CCPR1H:CCPR1L Registers .................................. 124
Prescaler ................................................................. 124
Software Interrupt .................................................... 124
Capture/Compare/PWM (CCP) ....................................... 123
Capture Mode. See Capture.
ANDLW ............................................................................ 220
ANDWF ............................................................................ 221
Assembler
MPASM Assembler .................................................. 264
Auto-Wake-up on Sync Break Character ......................... 167
B
BC .................................................................................... 221
BCF .................................................................................. 222
Block Diagrams
A/D ........................................................................... 178
Analog Input Model .................................................. 179
Capture Mode Operation ......................................... 124
Compare Mode Operation ....................................... 125
Device Clock .............................................................. 24
EUSART Receive .................................................... 165
EUSART Transmit ................................................... 163
External Power-on Reset Circuit
CCP Mode and Timer Resources ............................ 124
CCPR1H Register ................................................... 124
CCPR1L Register .................................................... 124
Compare Mode. See Compare.
Module Configuration .............................................. 124
Clock Sources .................................................................... 30
Selection Using OSCCON Register .......................... 30
CLRF ............................................................................... 229
CLRWDT ......................................................................... 229
(Slow VDD Power-up) ......................................... 43
Fail-Safe Clock Monitor ............................................ 206
© 2008 Microchip Technology Inc.
DS39760D-page 311
PIC18F2450/4450
Code Examples
DAW ................................................................................ 232
DC Characteristics ........................................................... 278
Power-Down and Supply Current ............................ 270
Supply Voltage ........................................................ 269
DCFSNZ .......................................................................... 233
DECF ............................................................................... 232
DECFSZ .......................................................................... 233
Dedicated ICD/ICSP Port ................................................ 211
Demonstration, Development and
Evaluation Boards ................................................... 266
Development Support ...................................................... 263
Device Differences ........................................................... 308
Device Overview .................................................................. 7
Features (table) ........................................................... 9
New Core Features ...................................................... 7
Other Special Features ................................................ 8
Direct Addressing .............................................................. 68
16 x 16 Signed Multiply Routine ................................84
16 x 16 Unsigned Multiply Routine ............................84
8 x 8 Signed Multiply Routine ....................................83
8 x 8 Unsigned Multiply Routine ................................83
Changing Between Capture Prescalers ...................124
Computed GOTO Using an Offset Value ...................56
Erasing a Flash Program Memory Row .....................78
Fast Register Stack ....................................................56
How to Clear RAM (Bank 1) Using
Indirect Addressing ............................................67
Implementing a Real-Time Clock Using
a Timer1 Interrupt Service ...............................119
Initializing PORTA ......................................................99
Initializing PORTB ....................................................101
Initializing PORTC ....................................................104
Initializing PORTD ....................................................107
Initializing PORTE ....................................................109
Reading a Flash Program Memory Word ..................77
Saving STATUS, WREG and
E
Effect on Standard PIC MCU
Instructions .............................................................. 260
Electrical Characteristics ................................................. 267
Enhanced Universal Synchronous Receiver
Transmitter (USART). See EUSART.
Equations
BSR Registers in RAM .......................................97
Writing to Flash Program Memory ....................... 80–81
Code Protection ...............................................................191
COMF ...............................................................................230
Compare (CCP Module) ...................................................125
Associated Registers ...............................................126
CCP1 Pin Configuration ...........................................125
CCPR1 Register ......................................................125
Software Interrupt ....................................................125
Special Event Trigger ...............................................125
Timer1 Mode Selection ............................................125
Configuration Bits .............................................................192
Configuration Register Protection ....................................211
Context Saving During Interrupts .......................................97
Conversion Considerations ..............................................309
CPFSEQ ..........................................................................230
CPFSGT ...........................................................................231
CPFSLT ...........................................................................231
Crystal Oscillator/Ceramic Resonator ................................25
Customer Change Notification Service ............................319
Customer Notification Service ..........................................319
Customer Support ............................................................319
A/D Acquisition Time ............................................... 180
A/D Minimum Charging Time ................................... 180
Calculating the Minimum Required
A/D Acquisition Time ....................................... 180
Errata ................................................................................... 6
EUSART
Asynchronous Mode ................................................ 163
Associated Registers, Receive ........................ 166
Associated Registers, Transmit ....................... 164
Auto-Wake-up on Sync Break ......................... 167
Break Character Sequence ............................. 168
Receiver .......................................................... 165
Receiving a Break Character ........................... 168
Setting Up 9-Bit Mode with
Address Detect ........................................ 165
Transmitter ...................................................... 163
Baud Rate Generator (BRG) ................................... 157
Associated Registers ....................................... 158
Auto-Baud Rate Detect .................................... 161
Baud Rate Error, Calculating ........................... 158
Baud Rates, Asynchronous Modes ................. 159
High Baud Rate Select (BRGH Bit) ................. 157
Operation in Power-Managed Modes .............. 157
Sampling .......................................................... 157
Synchronous Master Mode ...................................... 169
Associated Registers, Receive ........................ 171
Associated Registers, Transmit ....................... 170
Reception ........................................................ 171
Transmission ................................................... 169
Synchronous Slave Mode ........................................ 172
Associated Registers, Receive ........................ 173
Associated Registers, Transmit ....................... 172
Reception ........................................................ 173
Transmission ................................................... 172
D
Data Addressing Modes .....................................................67
Comparing Addressing Modes with
the Extended Instruction Set Enabled ................71
Direct ..........................................................................67
Indexed Literal Offset .................................................70
BSR Operation ...................................................72
Instructions Affected ..........................................70
Mapping the Access Bank .................................72
Indirect .......................................................................67
Inherent and Literal ....................................................67
Data Memory ......................................................................59
Access Bank ..............................................................61
and the Extended Instruction Set ...............................70
Bank Select Register (BSR) .......................................59
General Purpose Registers ........................................61
Map for PIC18F2450/4450 Devices ...........................60
Special Function Registers ........................................62
Map ....................................................................62
USB RAM ...................................................................59
DS39760D-page 312
© 2008 Microchip Technology Inc.
PIC18F2450/4450
Extended Instruction Set .................................................. 255
ADDFSR .................................................................. 256
ADDULNK ................................................................ 256
CALLW ..................................................................... 257
Considerations for Use ............................................ 260
MOVSF .................................................................... 257
MOVSS .................................................................... 258
PUSHL ..................................................................... 258
SUBFSR .................................................................. 259
SUBULNK ................................................................ 259
Syntax ...................................................................... 255
Use with MPLAB IDE Tools ..................................... 262
External Clock Input ........................................................... 26
I
I/O Ports ............................................................................ 99
ID Locations ............................................................. 191, 211
Idle Modes ......................................................................... 37
INCF ................................................................................ 234
INCFSZ ............................................................................ 235
In-Circuit Debugger .......................................................... 211
In-Circuit Serial Programming (ICSP) ...................... 191, 211
Indexed Literal Offset Addressing
and Standard PIC18 Instructions ............................. 260
Indexed Literal Offset Mode ............................................. 260
Indirect Addressing ............................................................ 68
INFSNZ ............................................................................ 235
Initialization Conditions for all Registers ...................... 49–52
Instruction Cycle ................................................................ 57
Clocking Scheme ....................................................... 57
Flow/Pipelining .......................................................... 57
Instruction Set .................................................................. 213
ADDLW .................................................................... 219
ADDWF ................................................................... 219
ADDWF (Indexed Literal Offset mode) .................... 261
ADDWFC ................................................................. 220
ANDLW .................................................................... 220
ANDWF ................................................................... 221
BC ............................................................................ 221
BCF ......................................................................... 222
BN ............................................................................ 222
BNC ......................................................................... 223
BNN ......................................................................... 223
BNOV ...................................................................... 224
BNZ ......................................................................... 224
BOV ......................................................................... 227
BRA ......................................................................... 225
BSF .......................................................................... 225
BSF (Indexed Literal Offset mode) .......................... 261
BTFSC ..................................................................... 226
BTFSS ..................................................................... 226
BTG ......................................................................... 227
BZ ............................................................................ 228
CALL ........................................................................ 228
CLRF ....................................................................... 229
CLRWDT ................................................................. 229
COMF ...................................................................... 230
CPFSEQ .................................................................. 230
CPFSGT .................................................................. 231
CPFSLT ................................................................... 231
DAW ........................................................................ 232
DCFSNZ .................................................................. 233
DECF ....................................................................... 232
DECFSZ .................................................................. 233
General Format ....................................................... 215
GOTO ...................................................................... 234
INCF ........................................................................ 234
INCFSZ .................................................................... 235
INFSNZ .................................................................... 235
IORLW ..................................................................... 236
IORWF ..................................................................... 236
LFSR ....................................................................... 237
MOVF ...................................................................... 237
MOVFF .................................................................... 238
MOVLB .................................................................... 238
MOVLW ................................................................... 239
F
Fail-Safe Clock Monitor ............................................ 191, 206
Exiting Operation ..................................................... 206
Interrupts in Power-Managed Modes ....................... 207
POR or Wake-up From Sleep .................................. 207
WDT During Oscillator Failure ................................. 206
Fast Register Stack ............................................................ 56
Firmware Instructions ....................................................... 213
Flash Program Memory ..................................................... 73
Associated Registers ................................................. 81
Control Registers ....................................................... 74
EECON1 and EECON2 ..................................... 74
TABLAT (Table Latch) Register ......................... 76
TBLPTR (Table Pointer) Register ...................... 76
Erase Sequence ........................................................ 78
Erasing ....................................................................... 78
Operation During Code-Protect ................................. 81
Protection Against Spurious Writes ........................... 81
Reading ...................................................................... 77
Table Pointer
Boundaries Based on Operation ........................ 76
Table Pointer Boundaries .......................................... 76
Table Reads and Table Writes .................................. 73
Unexpected Termination of Write .............................. 81
Write Sequence ......................................................... 79
Write Verify ................................................................ 81
Writing To ................................................................... 79
FSCM. See Fail-Safe Clock Monitor.
G
GOTO .............................................................................. 234
H
Hardware Multiplier ............................................................ 83
Introduction ................................................................ 83
Operation ................................................................... 83
Performance Comparison .......................................... 83
High/Low-Voltage Detect ................................................. 185
Applications .............................................................. 188
Associated Registers ............................................... 189
Characteristics ......................................................... 282
Current Consumption ............................................... 187
Effects of a Reset ..................................................... 189
Operation ................................................................. 186
During Sleep .................................................... 189
Setup ........................................................................ 187
Start-up Time ........................................................... 187
Typical Application ................................................... 188
HLVD. See High/Low-Voltage Detect.
© 2008 Microchip Technology Inc.
DS39760D-page 313
PIC18F2450/4450
MOVWF ...................................................................239
MULLW ....................................................................240
MULWF ....................................................................240
NEGF .......................................................................241
NOP .........................................................................241
Opcode Field Descriptions .......................................214
POP .........................................................................242
PUSH .......................................................................242
RCALL .....................................................................243
RESET .....................................................................243
RETFIE ....................................................................244
RETLW ....................................................................244
RETURN ..................................................................245
RLCF ........................................................................245
RLNCF .....................................................................246
RRCF .......................................................................246
RRNCF ....................................................................247
SETF ........................................................................247
SETF (Indexed Literal Offset mode) ........................261
SLEEP .....................................................................248
Standard Instructions ...............................................213
SUBFWB ..................................................................248
SUBLW ....................................................................249
SUBWF ....................................................................249
SUBWFB ..................................................................250
SWAPF ....................................................................250
TBLRD .....................................................................251
TBLWT .....................................................................252
TSTFSZ ...................................................................253
XORLW ....................................................................253
XORWF ....................................................................254
INTCON Register
M
Master Clear Reset (MCLR) .............................................. 43
Memory Organization ........................................................ 53
Data Memory ............................................................. 59
Program Memory ....................................................... 53
Memory Programming Requirements .............................. 280
Microchip Internet Web Site ............................................. 319
Migration from Baseline to Enhanced Devices ................ 309
Migration from High-End to Enhanced Devices ............... 310
Migration from Mid-Range to Enhanced Devices ............ 310
MOVF .............................................................................. 237
MOVFF ............................................................................ 238
MOVLB ............................................................................ 238
MOVLW ........................................................................... 239
MOVSF ............................................................................ 257
MOVSS ............................................................................ 258
MOVWF ........................................................................... 239
MPLAB ASM30 Assembler, Linker, Librarian .................. 264
MPLAB ICD 2 In-Circuit Debugger .................................. 265
MPLAB ICE 2000 High-Performance
Universal In-Circuit Emulator ................................... 265
MPLAB Integrated Development
Environment Software ............................................. 263
MPLAB PM3 Device Programmer ................................... 265
MPLAB REAL ICE In-Circuit Emulator System ............... 265
MPLINK Object Linker/MPLIB Object Librarian ............... 264
MULLW ............................................................................ 240
MULWF ............................................................................ 240
N
NEGF ............................................................................... 241
NOP ................................................................................. 241
RBIF Bit ....................................................................101
INTCON Registers .............................................................87
Internal Oscillator Block
O
Oscillator Configuration ..................................................... 23
EC .............................................................................. 23
ECIO .......................................................................... 23
ECPIO ....................................................................... 23
ECPLL ....................................................................... 23
HS .............................................................................. 23
HSPLL ....................................................................... 23
INTCKO ..................................................................... 23
Internal Oscillator Block ............................................. 27
INTHS ........................................................................ 23
INTIO ......................................................................... 23
INTXT ........................................................................ 23
Oscillator Modes and USB Operation ........................ 24
XT .............................................................................. 23
XTPLL ........................................................................ 23
Oscillator Selection .......................................................... 191
Oscillator Settings for USB ................................................ 27
Oscillator Start-up Timer (OST) ................................... 32, 45
Oscillator Switching ........................................................... 30
Oscillator Transitions ......................................................... 30
Oscillator, Timer1 ............................................................. 115
INTHS, INTXT, INTCKO and INTIO Modes ...............27
Internal RC Oscillator
Use with WDT ..........................................................203
Internet Address ...............................................................319
Interrupt Sources ..............................................................191
A/D Conversion Complete .......................................179
Capture Complete (CCP) .........................................124
Compare Complete (CCP) .......................................125
Interrupt-on-Change (RB7:RB4) ..............................101
INTx Pin .....................................................................97
PORTB, Interrupt-on-Change ....................................97
TMR0 .........................................................................97
TMR0 Overflow ........................................................113
TMR1 Overflow ........................................................115
TMR2 to PR2 Match (PWM) ....................................127
Interrupts ............................................................................85
USB ............................................................................85
Interrupts, Flag Bits
Interrupt-on-Change (RB7:RB4)
Flag (RBIF Bit) .................................................101
INTOSC, INTRC. See Internal Oscillator Block.
IORLW .............................................................................236
IORWF .............................................................................236
IPR Registers .....................................................................94
P
Packaging Information ..................................................... 295
Details ...................................................................... 297
Marking .................................................................... 295
PICkit 2 Development Programmer ................................. 266
PICSTART Plus Development Programmer .................... 266
PIE Registers ..................................................................... 92
L
LFSR ................................................................................237
Low-Voltage ICSP Programming. See Single-Supply
ICSP Programming.
DS39760D-page 314
© 2008 Microchip Technology Inc.
PIC18F2450/4450
Pin Functions
MCLR/VPP/RE3 .................................................... 12, 16
PORTB
Associated Registers ............................................... 103
I/O Summary ........................................................... 102
LATB Register ......................................................... 101
PORTB Register ...................................................... 101
RB7:RB4 Interrupt-on-Change Flag
NC/ICCK/ICPGC ........................................................ 21
NC/ICDT/ICPGD ........................................................ 21
NC/ICPORTS ............................................................. 21
NC/ICRST/ICVPP ....................................................... 21
OSC1/CLKI .......................................................... 12, 16
OSC2/CLKO/RA6 ................................................ 12, 16
RA0/AN0 .............................................................. 13, 17
RA1/AN1 .............................................................. 13, 17
RA2/AN2/VREF- .................................................... 13, 17
RA3/AN3/VREF+ ................................................... 13, 17
RA4/T0CKI/RCV .................................................. 13, 17
RA5/AN4/HLVDIN ................................................ 13, 17
RB0/AN12/INT0 ................................................... 14, 18
RB1/AN10/INT1 ................................................... 14, 18
RB2/AN8/INT2/VMO ............................................ 14, 18
RB3/AN9/VPO ..................................................... 14, 18
RB4/AN11/KBI0 ................................................... 14, 18
RB5/KBI1/PGM .................................................... 14, 18
RB6/KBI2/PGC .................................................... 14, 18
RB7/KBI3/PGD .................................................... 14, 18
RC0/T1OSO/T1CKI ............................................. 15, 19
RC1/T1OSI/UOE .................................................. 15, 19
RC2/CCP1 ........................................................... 15, 19
RC4/D-/VM ........................................................... 15, 19
RC5/D+/VP .......................................................... 15, 19
RC6/TX/CK .......................................................... 15, 19
RC7/RX/DT .......................................................... 15, 19
RD0 ............................................................................ 20
RD1 ............................................................................ 20
RD2 ............................................................................ 20
RD3 ............................................................................ 20
RD4 ............................................................................ 20
RD5 ............................................................................ 20
RD6 ............................................................................ 20
RD7 ............................................................................ 20
RE0/AN5 .................................................................... 21
RE1/AN6 .................................................................... 21
RE2/AN7 .................................................................... 21
VDD ...................................................................... 15, 21
VSS ....................................................................... 15, 21
VUSB ..................................................................... 15, 21
Pinout I/O Descriptions
(RBIF Bit) ......................................................... 101
TRISB Register ........................................................ 101
PORTC
Associated Registers ............................................... 106
I/O Summary ........................................................... 105
LATC Register ......................................................... 104
PORTC Register ...................................................... 104
TRISC Register ....................................................... 104
PORTD
Associated Registers ............................................... 108
I/O Summary ........................................................... 108
LATD Register ......................................................... 107
PORTD Register ...................................................... 107
TRISD Register ....................................................... 107
PORTE
Associated Registers ............................................... 110
I/O Summary ........................................................... 110
LATE Register ......................................................... 109
PORTE Register ...................................................... 109
TRISE Register ........................................................ 109
Postscaler, WDT
Assignment (PSA Bit) .............................................. 113
Rate Select (T0PS2:T0PS0 Bits) ............................. 113
Power-Managed Modes ..................................................... 33
and A/D Operation ................................................... 182
Clock Sources ........................................................... 33
Clock Transitions and Status Indicators .................... 34
Effects on Various Clock Sources ............................. 32
Entering ..................................................................... 33
Exiting Idle and Sleep Modes .................................... 39
by Interrupt ........................................................ 39
by Reset ............................................................ 39
by WDT Time-out .............................................. 39
Without an Oscillator Start-up Delay ................. 40
Idle ............................................................................. 37
Idle Modes
PRI_IDLE .......................................................... 38
RC_IDLE ........................................................... 39
SEC_IDLE ......................................................... 38
Multiple Sleep Commands ......................................... 34
Run Modes ................................................................ 34
PRI_RUN ........................................................... 34
RC_RUN ............................................................ 36
SEC_RUN ......................................................... 34
Selecting .................................................................... 33
Sleep ......................................................................... 37
Summary (table) ........................................................ 33
Power-on Reset (POR) ...................................................... 43
Power-up Delays ............................................................... 32
Power-up Timer (PWRT) ............................................. 32, 45
Prescaler, Timer0 ............................................................ 113
Assignment (PSA Bit) .............................................. 113
Rate Select (T0PS2:T0PS0 Bits) ............................. 113
Prescaler, Timer2 ............................................................ 128
PIC18F2450 ............................................................... 12
PIC18F4450 ............................................................... 16
PIR Registers ..................................................................... 90
PLL Frequency Multiplier ................................................... 26
HSPLL, XTPLL, ECPLL and
ECPIO Oscillator Modes .................................... 26
PLL Lock Time-out ............................................................. 45
POP ................................................................................. 242
POR. See Power-on Reset.
PORTA
Associated Registers ............................................... 100
I/O Summary ............................................................ 100
LATA Register ............................................................ 99
PORTA Register ........................................................ 99
TRISA Register .......................................................... 99
© 2008 Microchip Technology Inc.
DS39760D-page 315
PIC18F2450/4450
PRI_IDLE Mode .................................................................38
PRI_RUN Mode .................................................................34
Program Counter ................................................................54
PCL, PCH and PCU Registers ...................................54
PCLATH and PCLATU Registers ..............................54
Program Memory
HLVDCON (High/Low-Voltage
Detect Control) ................................................ 185
INTCON (Interrupt Control) ........................................ 87
INTCON2 (Interrupt Control 2) ................................... 88
INTCON3 (Interrupt Control 3) ................................... 89
IPR1 (Peripheral Interrupt Priority 1) ......................... 94
IPR2 (Peripheral Interrupt Priority 2) ......................... 95
OSCCON (Oscillator Control) .................................... 31
PIE1 (Peripheral Interrupt Enable 1) .......................... 92
PIE2 (Peripheral Interrupt Enable 2) .......................... 93
PIR1 (Peripheral Interrupt Request (Flag) 1) ............. 90
PIR2 (Peripheral Interrupt Request (Flag) 2) ............. 91
PORTE .................................................................... 109
RCON (Reset Control) ......................................... 42, 96
RCSTA (Receive Status and Control) ..................... 155
STATUS .................................................................... 66
STKPTR (Stack Pointer) ............................................ 55
T0CON (Timer0 Control) ......................................... 111
T1CON (Timer1 Control) ......................................... 115
T2CON (Timer2 Control) ......................................... 121
TXSTA (Transmit Status and Control) ..................... 154
UCFG (USB Configuration) ..................................... 132
UCON (USB Control) ............................................... 130
UEIE (USB Error Interrupt Enable) .......................... 148
UEIR (USB Error Interrupt Status) ........................... 147
UEPn (USB Endpoint n Control) .............................. 135
UIE (USB Interrupt Enable) ..................................... 146
UIR (USB Interrupt Status) ...................................... 144
USTAT (USB Status) ............................................... 134
WDTCON (Watchdog Timer Control) ...................... 204
RESET ............................................................................. 243
Reset State of Registers .................................................... 48
Reset Timers ..................................................................... 45
Oscillator Start-up Timer (OST) ................................. 45
PLL Lock Time-out ..................................................... 45
Power-up Timer (PWRT) ........................................... 45
Resets ........................................................................ 41, 191
Brown-out Reset (BOR) ........................................... 191
Oscillator Start-up Timer (OST) ............................... 191
Power-on Reset (POR) ............................................ 191
Power-up Timer (PWRT) ......................................... 191
RETFIE ............................................................................ 244
RETLW ............................................................................ 244
RETURN .......................................................................... 245
Return Address Stack ........................................................ 54
and Associated Registers .......................................... 54
Return Stack Pointer (STKPTR) ........................................ 55
Revision History ............................................................... 307
RLCF ............................................................................... 245
RLNCF ............................................................................. 246
RRCF ............................................................................... 246
RRNCF ............................................................................ 247
and the Extended Instruction Set ...............................70
Code Protection .......................................................209
Instructions .................................................................58
Two-Word ..........................................................58
Interrupt Vector ..........................................................53
Look-up Tables ..........................................................56
Map and Stack (diagram) ...........................................53
Reset Vector ..............................................................53
Program Verification and Code Protection .......................208
Associated Registers ...............................................208
Programming, Device Instructions ...................................213
Pulse-Width Modulation. See PWM (CCP Module).
PUSH ...............................................................................242
PUSH and POP Instructions ..............................................55
PUSHL .............................................................................258
PWM (CCP Module)
Associated Registers ...............................................128
Duty Cycle ................................................................127
Example Frequencies/Resolutions ..........................128
Period .......................................................................127
Setup for PWM Operation ........................................128
TMR2 to PR2 Match ................................................127
Q
Q Clock ............................................................................128
R
RAM. See Data Memory.
RC_IDLE Mode ..................................................................39
RC_RUN Mode ..................................................................36
RCALL ..............................................................................243
RCON Register
Bit Status During Initialization ....................................48
Reader Response ............................................................320
Register File Summary ................................................. 63–65
Registers
ADCON0 (A/D Control 0) .........................................175
ADCON1 (A/D Control 1) .........................................176
ADCON2 (A/D Control 2) .........................................177
BAUDCON (Baud Rate Control) ..............................156
BDnSTAT (Buffer Descriptor n Status,
CPU Mode) ......................................................139
BDnSTAT (Buffer Descriptor n Status,
SIE Mode) ........................................................140
CCP1CON (Capture/Compare/PWM Control) .........123
CONFIG1H (Configuration 1 High) ..........................194
CONFIG1L (Configuration 1 Low) ............................193
CONFIG2H (Configuration 2 High) ..........................196
CONFIG2L (Configuration 2 Low) ............................195
CONFIG3H (Configuration 3 High) ..........................197
CONFIG4L (Configuration 4 Low) ............................198
CONFIG5H (Configuration 5 High) ..........................199
CONFIG5L (Configuration 5 Low) ............................199
CONFIG6H (Configuration 6 High) ..........................200
CONFIG6L (Configuration 6 Low) ............................200
CONFIG7H (Configuration 7 High) ..........................201
CONFIG7L (Configuration 7 Low) ............................201
DEVID1 (Device ID 1) ..............................................202
DEVID2 (Device ID 2) ..............................................202
EECON1 (Memory Control 1) ....................................75
S
SEC_IDLE Mode ............................................................... 38
SEC_RUN Mode ................................................................ 34
SETF ................................................................................ 247
Single-Supply ICSP Programming ................................... 212
SLEEP ............................................................................. 248
Sleep
OSC1 and OSC2 Pin States ...................................... 32
Sleep Mode ........................................................................ 37
Software Simulator (MPLAB SIM) ................................... 264
Special Event Trigger. See Compare (CCP Module).
Special Features of the CPU ........................................... 191
Special ICPORT Features ............................................... 211
DS39760D-page 316
© 2008 Microchip Technology Inc.
PIC18F2450/4450
Stack Full/Underflow Resets .............................................. 56
STATUS Register .............................................................. 66
SUBFSR .......................................................................... 259
SUBFWB .......................................................................... 248
SUBLW ............................................................................ 249
SUBULNK ........................................................................ 259
SUBWF ............................................................................ 249
SUBWFB .......................................................................... 250
SWAPF ............................................................................ 250
Capture/Compare/PWM (CCP) ............................... 290
CLKO and I/O .......................................................... 287
Clock/Instruction Cycle .............................................. 57
EUSART Synchronous Receive
(Master/Slave) ................................................. 291
EUSART Synchronous Transmission
(Master/Slave) ................................................. 291
External Clock (All Modes Except PLL) ................... 285
Fail-Safe Clock Monitor ........................................... 207
High/Low-Voltage Detect Characteristics ................ 282
High-Voltage Detect (VDIRMAG = 1) ...................... 188
Low-Voltage Detect (VDIRMAG = 0) ....................... 187
PWM Output ............................................................ 127
Reset, Watchdog Timer (WDT), Oscillator
T
T0CON Register
PSA Bit ..................................................................... 113
T0CS Bit ................................................................... 112
T0PS2:T0PS0 Bits ................................................... 113
T0SE Bit ................................................................... 112
Table Pointer Operations (table) ........................................ 76
Table Reads/Table Writes ................................................. 56
TBLRD ............................................................................. 251
TBLWT ............................................................................. 252
Time-out in Various Situations (table) ................................ 45
Time-out Sequence ............................................................ 45
Timer0 .............................................................................. 111
16-Bit Mode Timer Reads and Writes ...................... 112
Associated Registers ............................................... 113
Clock Source Edge Select (T0SE Bit) ...................... 112
Clock Source Select (T0CS Bit) ............................... 112
Operation ................................................................. 112
Overflow Interrupt .................................................... 113
Prescaler .................................................................. 113
Switching Assignment ...................................... 113
Prescaler. See Prescaler, Timer0.
Timer1 .............................................................................. 115
16-Bit Read/Write Mode ........................................... 117
Associated Registers ....................................... 120, 126
Interrupt .................................................................... 118
Operation ................................................................. 116
Oscillator .......................................................... 115, 117
Layout Considerations ..................................... 118
Low-Power Option ........................................... 117
Using Timer1 as a Clock Source ..................... 117
Overflow Interrupt .................................................... 115
Resetting, Using a Special Event
Start-up Timer (OST) and Power-up
Timer (PWRT) ................................................. 288
Send Break Character Sequence ............................ 168
Slow Rise Time (MCLR Tied to VDD,
VDD Rise > TPWRT) ............................................ 47
Synchronous Reception
(Master Mode, SREN) ..................................... 171
Synchronous Transmission ..................................... 169
Synchronous Transmission (Through TXEN) .......... 170
Time-out Sequence on POR w/PLL Enabled
(MCLR Tied to VDD) .......................................... 47
Time-out Sequence on Power-up
(MCLR Not Tied to VDD), Case 1 ...................... 46
Time-out Sequence on Power-up
(MCLR Not Tied to VDD), Case 2 ...................... 46
Time-out Sequence on Power-up
(MCLR Tied to VDD, VDD Rise TPWRT) .............. 46
Timer0 and Timer1 External Clock .......................... 289
Transition for Entry to Idle Mode ............................... 38
Transition for Entry to SEC_RUN Mode .................... 35
Transition for Entry to Sleep Mode ............................ 37
Transition for Two-Speed Start-up
(INTRC to HSPLL) ........................................... 205
Transition for Wake From Idle to Run Mode .............. 38
Transition for Wake From Sleep (HSPLL) ................. 37
Transition From RC_RUN Mode to
PRI_RUN Mode ................................................. 36
Transition From SEC_RUN Mode to
PRI_RUN Mode (HSPLL) .................................. 35
Transition to RC_RUN Mode ..................................... 36
USB Signal .............................................................. 292
Timing Diagrams and Specifications ............................... 285
Capture/Compare/PWM
Trigger Output (CCP) ....................................... 118
TMR1H Register ...................................................... 115
TMR1L Register ....................................................... 115
Use as a Real-Time Clock ....................................... 118
Timer2 .............................................................................. 121
Associated Registers ............................................... 122
Interrupt .................................................................... 122
Operation ................................................................. 121
Output ...................................................................... 122
PR2 Register ............................................................ 127
TMR2 to PR2 Match Interrupt .................................. 127
Timing Diagrams
Requirements (CCP) ....................................... 290
CLKO and I/O Requirements ................................... 287
EUSART Synchronous Receive
Requirements .................................................. 291
EUSART Synchronous Transmission
Requirements .................................................. 291
External Clock Requirements .................................. 285
PLL Clock ................................................................ 286
Reset, Watchdog Timer, Oscillator Start-up
A/D Conversion ........................................................ 293
Asynchronous Reception ......................................... 166
Asynchronous Transmission .................................... 164
Asynchronous Transmission
Timer, Power-up Timer and Brown-out
Reset Requirements ........................................ 288
Timer0 and Timer1 External Clock
(Back-to-Back) ................................................. 164
Automatic Baud Rate Calculation ............................ 162
Auto-Wake-up Bit (WUE) During
Normal Operation ............................................ 167
Auto-Wake-up Bit (WUE) During Sleep ................... 167
BRG Overflow Sequence ......................................... 162
Brown-out Reset (BOR) ........................................... 288
Requirements .................................................. 289
USB Full-Speed Requirements ............................... 292
USB Low-Speed Requirements ............................... 292
Top-of-Stack Access .......................................................... 54
TQFP Packages and Special Features ........................... 211
TSTFSZ ........................................................................... 253
© 2008 Microchip Technology Inc.
DS39760D-page 317
PIC18F2450/4450
Two-Speed Start-up ................................................. 191, 205
Two-Word Instructions
Example Cases ..........................................................58
TXSTA Register
Layered Framework ................................................. 151
Oscillator Requirements .......................................... 150
Output Enable Monitor ............................................. 133
Overview .......................................................... 129, 151
Ping-Pong Buffer Configuration ............................... 133
Power ...................................................................... 151
Power Modes ........................................................... 149
Bus Power Only ............................................... 149
Dual Power with Self-Power
BRGH Bit .................................................................157
U
Universal Serial Bus ...........................................................59
Address Register (UADDR) .....................................136
Associated Registers ...............................................150
Buffer Descriptor Table ............................................137
Buffer Descriptors ....................................................137
Address Validation ...........................................140
Assignment in Different
Dominance .............................................. 149
Self-Power Only ............................................... 149
Pull-up Resistors ...................................................... 133
RAM ......................................................................... 136
Memory Map .................................................... 136
Speed ...................................................................... 152
Status and Control ................................................... 130
Status Register (USTAT) ......................................... 134
Transfer Types ......................................................... 151
UFRMH:UFRML Registers ...................................... 136
Buffering Modes .......................................142
BDnSTAT Register (CPU Mode) .....................138
BDnSTAT Register (SIE Mode) .......................140
Byte Count .......................................................140
Example ...........................................................137
Memory Map ....................................................141
Ownership ........................................................137
Ping-Pong Buffering .........................................141
Register Summary ...........................................142
Status and Configuration .................................137
Class Specifications and Drivers .............................152
Descriptors ...............................................................152
Endpoint Control ......................................................135
Enumeration .............................................................152
External Transceiver ................................................131
Eye Pattern Test Enable ..........................................133
Firmware and Drivers ...............................................150
Frame Number Registers .........................................136
Frames .....................................................................151
Internal Transceiver .................................................131
Internal Voltage Regulator .......................................133
Interrupts ..................................................................143
and USB Transactions .....................................143
USB
Internal Voltage Regulator Specifications ................ 281
Module Specifications .............................................. 281
USB. See Universal Serial Bus.
W
Watchdog Timer (WDT) ........................................... 191, 203
Associated Registers ............................................... 204
Control Register ....................................................... 203
During Oscillator Failure .......................................... 206
Programming Considerations .................................. 203
WWW Address ................................................................ 319
WWW, On-Line Support ...................................................... 6
X
XORLW ............................................................................ 253
XORWF ........................................................................... 254
DS39760D-page 318
© 2008 Microchip Technology Inc.
PIC18F2450/4450
THE MICROCHIP WEB SITE
CUSTOMER SUPPORT
Microchip provides online support via our WWW site at
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© 2008 Microchip Technology Inc.
DS39760D-page 319
PIC18F2450/4450
READER RESPONSE
It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip prod-
uct. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation
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PIC18F2450/4450
DS39760D
Literature Number:
Device:
Questions:
1. What are the best features of this document?
2. How does this document meet your hardware and software development needs?
3. Do you find the organization of this document easy to follow? If not, why?
4. What additions to the document do you think would enhance the structure and subject?
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6. Is there any incorrect or misleading information (what and where)?
7. How would you improve this document?
DS39760D-page 320
© 2008 Microchip Technology Inc.
PIC18F2450/4450
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
PART NO.
Device
X
/XX
XXX
Examples:
Temperature
Range
Package
Pattern
a)
PIC18LF4450-I/P 301 = Industrial temp., PDIP
package, Extended VDD limits, QTP pattern
#301.
b)
c)
PIC18LF2450-I/SO = Industrial temp., SOIC
package, Extended VDD limits.
Device
PIC18F2450(1), PIC18F4450(1)
,
PIC18F4450-I/P = Industrial temp., PDIP
package, normal VDD limits.
PIC18F2450T(2), PIC18F4450T(2)
VDD range 4.2V to 5.5V
;
PIC18LF2450(1), PIC18LF4450(1)
PIC18LF2450T(2), PIC18LF4450T(2)
VDD range 2.0V to 5.5V
,
;
Temperature Range
Package
I
E
=
=
-40°C to +85°C (Industrial)
-40°C to +125°C (Extended)
PT
SO
SP
P
=
=
=
=
=
TQFP (Thin Quad Flatpack)
Note 1:
2:
F
LF
T
=
=
=
Standard Voltage Range
Wide Voltage Range
in tape and reel TQFP
packages only.
SOIC
Skinny Plastic DIP
PDIP
QFN
ML
Pattern
QTP, SQTP, Code or Special Requirements
(blank otherwise)
© 2008 Microchip Technology Inc.
DS39760D-page 321
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Fax: 86-756-3210049
01/02/08
DS39760D-page 322
© 2008 Microchip Technology Inc.
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