PIC18LF8493-I/PT [MICROCHIP]
64/80-Pin High Performance, Flash Microcontrollers with LCD Driver, 12-Bit ADC and nanoWatt Technology; 八十〇分之六十四引脚高性能，闪存微控制器与LCD驱动器， 12位ADC和纳瓦技术
| 型号： | PIC18LF8493-I/PT |
| 厂家： | 
MICROCHIP |
| 描述： | 64/80-Pin High Performance, Flash Microcontrollers with LCD Driver, 12-Bit ADC and nanoWatt Technology |
| 文件： | 总58页 (文件大小：936K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PIC18F6393/6493/8393/8493
Data Sheet
64/80-Pin High Performance,
Flash Microcontrollers with LCD Driver,
12-Bit ADC and nanoWatt Technology
© 2009 Microchip Technology Inc.
DS39896B
Note the following details of the code protection feature on Microchip devices:
•
Microchip products meet the specification contained in their particular Microchip Data Sheet.
•
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
•
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
•
•
Microchip is willing to work with the customer who is concerned about the integrity of their code.
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
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OTHERWISE, RELATED TO THE INFORMATION,
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Trademarks
The Microchip name and logo, the Microchip logo, dsPIC,
KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART,
rfPIC and UNI/O are registered trademarks of Microchip
Technology Incorporated in the U.S.A. and other countries.
FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor,
MXDEV, MXLAB, SEEVAL and The Embedded Control
Solutions Company are registered trademarks of Microchip
Technology Incorporated in the U.S.A.
Analog-for-the-Digital Age, Application Maestro, CodeGuard,
dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN,
ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial
Programming, ICSP, Mindi, MiWi, MPASM, MPLAB Certified
logo, MPLIB, MPLINK, mTouch, Octopus, Omniscient Code
Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit,
32
PICtail, PIC logo, REAL ICE, rfLAB, Select Mode, Total
Endurance, TSHARC, UniWinDriver, WiperLock and ZENA
are trademarks of Microchip Technology Incorporated in the
U.S.A. and other countries.
SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.
All other trademarks mentioned herein are property of their
respective companies.
© 2009, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.
Printed on recycled paper.
Microchip received ISO/TS-16949:2002 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
DS39896B-page 2
© 2009 Microchip Technology Inc.
PIC18F6393/6493/8393/8493
64/80-Pin High-Performance, Flash Microcontrollers
with LCD Driver, 12-Bit ADC and nanoWatt Technology
LCD Driver Module Features:
Peripheral Highlights:
• Direct Driving of LCD Panel
• 12-Bit, Up to 12-Channel Analog-to-Digital (A/D)
Converter module:
- Auto-acquisition capability
- Conversion available during Sleep
• High-Current Sink/Source 25 mA/25 mA
• Four External Interrupts
• Up to 192 Pixels: Software Selectable
• Programmable LCD Timing module:
- Multiple LCD timing sources available
- Up to four commons: Static, 1/2, 1/3 or
1/4 multiplex
• Four Input Change Interrupts
- Static, 1/2 or 1/3 bias configuration
• Can Drive LCD Panel while in Sleep mode for
Low-Power Operation
• Four 8-Bit/16-Bit Timer/Counter modules
• Real-Time Clock (RTC) Software module:
- Configurable 24-hour clock, calendar, automatic
100-year or 12,800-year, day-of-week calculator
- Uses Timer1
• Up to Two Capture/Compare/PWM (CCP) modules
• Master Synchronous Serial Port (MSSP) module
Supporting Three-Wire SPI (all four modes) and
I2C™ Master and Slave modes
• Addressable USART module:
- Supports RS-485 and RS-232
• Enhanced Addressable USART module:
- Supports RS-485, RS-232 and LIN 1.2
- Auto-wake-up on Start bit
Power-Managed Modes:
• Run: CPU On, Peripherals On
• Idle: CPU Off, Peripherals On
• Sleep: CPU Off, Peripherals Off
• Run mode Current Down to 14 μA Typical
• Idle mode Currents Down to 5.8 μA Typical
• Sleep mode Currents Down to 0.1 μA Typical
• Timer1 Oscillator: 1.8 μA, 32 kHz, 2V
• Watchdog Timer: 2.1 μA Typical
• Two-Speed Oscillator Start-up
- Auto-Baud Detect
• Dual Analog Comparators with Input Multiplexing
Flexible Oscillator Structure:
• Four Crystal modes:
- LP: Up to 200 kHz
- XT: Up to 4 MHz
- HS: Up to 40 MHz
- HSPLL: 4-10 MHz (16-40 MHz internal)
• 4x Phase Lock Loop (available for crystal and
internal oscillators)
Special Microcontroller Features:
• C Compiler Optimized Architecture:
- Optional extended instruction set designed to
optimize re-entrant code
• 1000 Erase/Write Cycle Flash Program Memory
Typical
• Two External RC modes, Up to 4 MHz
• Two External Clock modes, Up to 40 MHz
• Internal Oscillator Block:
- Eight selectable frequencies, from 31 kHz to 8 MHz
- Provides a complete range of clock speeds
from 31 kHz to 32 MHz when used with PLL
- User-tunable to compensate for frequency drift
• Secondary Oscillator Using Timer1 at 32 kHz
• Fail-Safe Clock Monitor:
• Flash Retention: 100 Years Typical
• Priority Levels for Interrupts
• 8 x 8 Single-Cycle Hardware Multiplier
• Extended Watchdog Timer (WDT):
- Programmable period from 4 ms to 132s
- 2% stability over VDD and temperature
• In-Circuit Serial Programming™ (ICSP™) via Two Pins
• In-Circuit Debug (ICD) via Two Pins
• Wide Operating Voltage Range: 2.0V to 5.5V
- Allows for safe shutdown of device if primary
or secondary clock fails
Note:
This document is supplemented by the
“PIC18F6390/6490/8390/8490 Data Sheet”
(DS39629). See Section 1.0 “Device
Overview”.
© 2009 Microchip Technology Inc.
DS39896B-page 3
PIC18F6393/6493/8393/8493
Data
Memory
Program Memory
MSSP
12-Bit
A/D
(channels)
LCD
(pixel)
CCP
(PWM)
Timers
8/16-Bit
Device
I/O
Comparators
Flash # Single-Word SRAM
(bytes) Instructions (bytes)
Master
SPI
2
I C™
PIC18F6393
8K
4096
8192
4096
8192
768
768
768
768
50
50
66
66
128
128
192
192
12
12
12
12
2
2
2
2
Y
Y
Y
Y
Y
Y
Y
Y
1/1
1/1
1/1
1/1
2
2
2
2
1/3
1/3
1/3
1/3
PIC18F6493 16K
PIC18F8393 8K
PIC18F8493 16K
Pin Diagrams
64-Pin TQFP
64 63 62 61 60 59 58 57 56 55 54 53 52 51
50 49
RB0/INT0
LCDBIAS2
48
1
RB1/INT1/SEG8
RB2/INT2/SEG9
RB3/INT3/SEG10
RB4/KBI0/SEG11
RB5/KBI1
LCDBIAS1
RG0/SEG30
47
46
45
44
43
42
41
40
39
38
37
36
35
2
3
RG1/TX2/CK2/SEG29
RG2/RX2/DT2/SEG28
RG3/SEG27
4
5
6
RB6/KBI2/PGC
VSS
MCLR/VPP/RG5
RG4/SEG26
7
PIC18F6393
PIC18F6493
8
VSS
OSC2/CLKO/RA6
OSC1/CLKI/RA7
VDD
9
VDD
10
11
12
13
14
15
16
RF7/SS/SEG25
RF6/AN11/SEG24
RF5/AN10/CVREF/SEG23
RF4/AN9/SEG22
RF3/AN8/SEG21
RF2/AN7/C1OUT/SEG20
RB7/KBI3/PGD
RC5/SDO/SEG12
RC4/SDI/SDA
RC3/SCK/SCL
RC2/CCP1/SEG13
34
33
17 18 19 20 21 22 23 24 25 26 27 28
29 30 31 32
Note 1: RE7 is the alternate pin for CCP2 multiplexing.
DS39896B-page 4
© 2009 Microchip Technology Inc.
PIC18F6393/6493/8393/8493
Pin Diagrams (Continued)
80-Pin TQFP
80 79 78
77 76 75 74 73 72 71 70 69 68 67 66 65
64 63 62 61
RH2/SEG45
1
RJ2/SEG34
RJ3/SEG35
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
RH3/SEG44
2
RB0/INT0
LCDBIAS2
3
RB1/INT1/SEG8
LCDBIAS1
4
RG0/SEG30
5
RB2/INT2/SEG9
RB3/INT3/SEG10
RB4/KBI0/SEG11
RB5/KBI1
RG1/TX2/CK2/SEG29
6
RG2/RX2/DT2/SEG28
7
RG3/SEG27
8
RB6/KBI2/PGC
VSS
MCLR/VPP/RG5
9
RG4/SEG26
PIC18F8393
PIC18F8493
10
VSS
VDD
OSC2/CLKO/RA6
OSC1/CLKI/RA7
VDD
11
12
13
14
15
16
17
18
19
20
RF7/SS/SEG25
RB7/KBI3/PGD
RC5/SDO/SEG12
RC4/SDI/SDA
RC3/SCK/SCL
RC2/CCP1/SEG13
RJ7/SEG36
RF6/AN11/SEG24
RF5/AN10/CVREF/SEG23
RF4/AN9/SEG22
RF3/AN8/SEG21
RF2/AN7/C1OUT/SEG20
RH7/SEG43
RJ6/SEG37
RH6/SEG42
40
21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39
Note 1: RE7 is the alternate pin for CCP2 multiplexing.
© 2009 Microchip Technology Inc.
DS39896B-page 5
PIC18F6393/6493/8393/8493
Table of Contents
1.0 Device Overview .......................................................................................................................................................................... 9
2.0 12-Bit Analog-to-Digital Converter (A/D) Module ....................................................................................................................... 31
3.0 Special Features of the CPU...................................................................................................................................................... 41
4.0 Electrical Characteristics ........................................................................................................................................................... 43
5.0 Packaging Information................................................................................................................................................................ 47
Appendix A: Revision History............................................................................................................................................................... 49
Appendix B: Device Differences........................................................................................................................................................... 49
Appendix C: Conversion Considerations ............................................................................................................................................. 50
Appendix D: Migration from Baseline to Enhanced Devices................................................................................................................ 50
Appendix E: migration from Mid-Range to Enhanced Devices ............................................................................................................ 51
Appendix F: Migration from High-End to Enhanced Devices............................................................................................................... 51
The Microchip Web Site....................................................................................................................................................................... 55
Customer Change Notification Service ................................................................................................................................................ 55
Customer Support................................................................................................................................................................................ 55
Reader Response ................................................................................................................................................................................ 56
Product Identification System............................................................................................................................................................... 57
DS39896B-page 6
© 2009 Microchip Technology Inc.
PIC18F6393/6493/8393/8493
TO OUR VALUED CUSTOMERS
It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip
products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and
enhanced as new volumes and updates are introduced.
If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via
E-mail at docerrors@microchip.com or fax the Reader Response Form in the back of this data sheet to (480) 792-4150. We
welcome your feedback.
Most Current Data Sheet
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http://www.microchip.com
You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page.
The last character of the literature number is the version number, (e.g., DS30000A is version A of document DS30000).
Errata
An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current
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of silicon and revision of document to which it applies.
To determine if an errata sheet exists for a particular device, please check with one of the following:
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When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are
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© 2009 Microchip Technology Inc.
DS39896B-page 7
PIC18F6393/6493/8393/8493
NOTES:
DS39896B-page 8
© 2009 Microchip Technology Inc.
PIC18F6393/6493/8393/8493
1.2
Details on Individual Family
Members
1.0
DEVICE OVERVIEW
This document contains device-specific information for
the following devices:
Devices in the PIC18F6393/6493/8393/8493 family are
available in 64-pin (PIC18F6X93) and 80-pin
(PIC18F8X93) packages. Block diagrams for the two
groups are shown in Figure 1-1 and Figure 1-2,
respectively.
• PIC18F6393
• PIC18F6493
• PIC18F8393
• PIC18F8493
Note: This data sheet documents only the devices’
features and specifications that are in addition
to the features and specifications of the
PIC18F6390/6490/8390/8490 devices. For
The devices are differentiated from each other in the
following ways:
• I/O Ports:
- 64-pin devices – 7 bidirectional ports
- 80-pin devices – 9 bidirectional ports
• LCD Pixels:
information
on
the
features
and
specifications shared by the PIC18F6393/
6493/8393/8493 and PIC18F6390/6490/
8390/8490 devices, see the “PIC18F6390/
6490/8390/8490 Data Sheet” (DS39629).
- 64-pin devices – 128 (32 SEGs x 4 COMs)
pixels can be driven
- 80-pin devices – 192 (48 SEGs x 4 COMs)
pixels can be driven
This family offers the advantages of all PIC18
microcontrollers
–
namely, high computational
• Flash Program Memory:
performance at an economical price. In addition to
these features, the PIC18F6393/6493/8393/8493
family introduces design enhancements that
make these microcontrollers a logical choice for many
high-performance, power-sensitive applications.
- PIC18FX393 devices – 8 Kbytes
- PIC18FX493 devices – 16 Kbytes
All other features for devices in this family are identical.
These are summarized in Table 1-1.
The pinouts for all devices are listed in Table 1-2 and
Table 1-3.
1.1
Special Features
• 12-Bit A/D Converter: This module incorporates
programmable acquisition time, allowing for a
channel to be selected and a conversion to be
initiated without waiting for a sampling period and
thus, reduces code overhead.
Like all Microchip PIC18 devices, members of the
PIC18F6393/6493/8393/8493 family are available as
both standard and low-voltage devices. Standard
devices with Flash memory, designated with an “F” in
the part number (such as PIC18F6393), accommodate
an operating VDD range of 4.2V to 5.5V. Low-voltage
parts, designated by “LF” (such as PIC18LF6490),
function over an extended VDD range of 2.0V to 5.5V.
© 2009 Microchip Technology Inc.
DS39896B-page 9
PIC18F6393/6493/8393/8493
TABLE 1-1:
DEVICE FEATURES
Features
PIC18F6393
PIC18F6493
PIC18F8393
PIC18F8493
Operating Frequency
Program Memory (Bytes)
Program Memory (Instructions)
Data Memory (Bytes)
Interrupt Sources
DC – 40 MHz
DC – 40 MHz
DC – 40 MHz
DC – 40 MHz
8K
4096
768
22
16K
8192
768
22
8K
4096
768
22
16K
8192
768
22
I/O Ports
Ports A, B, C, D, E, Ports A, B, C, D, E, Ports A, B, C, D, E, Ports A, B, C, D, E,
F, G
F, G
F, G, H, J
F, G, H, J
Number of Pixels the LCD Driver
Can Drive
128 (32 SEGs x
4 COMs)
128 (32 SEGs x
4 COMs)
192 (48 SEGs x
4 COMs)
192 (48 SEGs x
4 COMs)
Timers
4
4
4
4
Capture/Compare/PWM Modules
Serial Communications
2
2
2
2
MSSP, AUSART,
MSSP, AUSART,
MSSP, AUSART,
MSSP, AUSART,
Enhanced USART Enhanced USART Enhanced USART Enhanced USART
12-Bit Analog-to-Digital Module
Resets (and Delays)
12 Input Channels 12 Input Channels 12 Input Channels 12 Input Channels
POR, BOR,
POR, BOR,
POR, BOR,
POR, BOR,
RESETInstruction, RESETInstruction, RESETInstruction, RESETInstruction,
Stack Full,
Stack Underflow
(PWRT, OST),
Stack Full,
Stack Underflow
(PWRT, OST),
Stack Full,
Stack Underflow
(PWRT, OST),
Stack Full,
Stack Underflow
(PWRT, OST),
MCLR (optional), MCLR (optional), MCLR (optional), MCLR (optional),
WDT
WDT
WDT
WDT
Programmable Low-Voltage Detect
Programmable Brown-out Reset
Instruction Set
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
75 Instructions;
75 Instructions;
75 Instructions;
75 Instructions;
83 with Extended 83 with Extended 83 with Extended 83 with Extended
Instruction Set
Enabled
Instruction Set
Enabled
Instruction Set
Enabled
Instruction Set
Enabled
Packages
64-Pin TQFP
64-Pin TQFP
80-Pin TQFP
80-Pin TQFP
DS39896B-page 10
© 2009 Microchip Technology Inc.
PIC18F6393/6493/8393/8493
FIGURE 1-1:
PIC18F6X93 (64-PIN) BLOCK DIAGRAM
Data Bus<8>
PORTA
Table Pointer<21>
RA0/AN0
RA1/AN1
Data Latch
RA2/AN2/VREF-/SEG16
RA3/AN3/VREF+/SEG17
RA4/T0CKI/SEG14
RA5/AN4/HLVDIN/SEG15
OSC2/CLKO(3)/RA6
OSC1/CLKI(3)/RA7
8
8
inc/dec logic
21
Data Memory
(3.9 Kbytes)
PCLATH
PCLATU
Address Latch
20
PCU PCH PCL
Program Counter
12
PORTB
RB0/INT0
Data Address<12>
RB1/INT1/SEG8
RB2/INT2/SEG9
RB3/INT3/SEG10
RB4/KBI0/SEG11
RB5/KBI1
31 Level Stack
STKPTR
4
BSR
12
FSR0
FSR1
FSR2
4
Address Latch
Access
Bank
Program Memory
(48/64 Kbytes)
RB6/KBI2/PGC
RB7/KBI3/PGD
12
Data Latch
inc/dec
logic
PORTC
8
RC0/T1OSO/T13CKI
RC1/T1OSI/CCP2(1)
RC2/CCP1/SEG13
RC3/SCK/SCL
RC4/SDI/SDA
RC5/SDO/SEG12
RC6/TX1/CK1
Table Latch
Address
Decode
ROM Latch
IR
Instruction Bus <16>
RC7/RX1/DT1
8
PORTD
PORTE
State Machine
Control Signals
Instruction
Decode and
Control
RD7/SEG7:RD0/SEG0
PRODH PRODL
8 x 8 Multiply
3
8
LCDBIAS1
LCDBIAS2
LCDBIAS3
BITOP
8
W
8
8
COM0
Internal
Oscillator
Block
OSC1(3)
OSC2(3)
T1OSI
Power-up
Timer
RE4/COM1
RE5/COM2
RE6/COM3
RE7/CCP2(1)/SEG31
8
8
Oscillator
Start-up Timer
ALU<8>
8
INTRC
Oscillator
Power-on
Reset
PORTF
8 MHz
Oscillator
RF0/AN5/SEG18
RF1/AN6/C2OUT/SEG19
RF2/AN7/C1OUT/SEG20
RF3/AN8/SEG21
RF4/AN9/SEG22
RF5/AN10/CVREF/SEG23
RF6/AN11/SEG24
RF7/SS/SEG25
Watchdog
Timer
T1OSO
Precision
Band Gap
Reference
Brown-out
Reset
Fail-Safe
MCLR(2)
VDD, VSS
Single-Supply
Programming
In-Circuit
Clock Monitor
Debugger
PORTG
ADC
12-Bit
BOR
RG0/SEG30
RG1/TX2/CK2/SEG29
Timer0
Timer1
Timer2
Timer3
HLVD
RG2/RX2/DT2/SEG28
RG3/SEG27
RG4/SEG26
MCLR/VPP/RG5(2)
LCD
Driver
MSSP
Comparators
CCP1
CCP2
EUSART1
AUSART2
Note 1: CCP2 is multiplexed with RC1 when Configuration bit, CCP2MX, is set, or RE7 when CCP2MX is not set.
2: RG5 is only available when MCLR functionality is disabled.
3: OSC1/CLKI and OSC2/CLKO are only available in select oscillator modes and when these pins are not being used as digital I/O.
For additional information, see Section 2.0 “Oscillator Configurations” of the “PIC18F6390/6490/8390/8490 Data Sheet” (DS39629).
© 2009 Microchip Technology Inc.
DS39896B-page 11
PIC18F6393/6493/8393/8493
FIGURE 1-2:
PIC18F8X93 (80-PIN) BLOCK DIAGRAM
PORTA
Data Bus<8>
RA0/AN0
Table Pointer<21>
RA1/AN1
RA2/AN2/VREF-/SEG16
RA3/AN3/VREF+/SEG17
RA4/T0CKI/SEG14
RA5/AN4/HLVDIN/SEG15
OSC2/CLKO(3)/RA6
OSC1/CLKI(3)/RA7
Data Latch
8
8
inc/dec logic
21
Data Memory
(3.9 Kbytes)
PCLATH
PCLATU
Address Latch
20
PCU PCH PCL
Program Counter
PORTB
RB0/INT0
12
RB1/INT1/SEG8
RB2/INT2/SEG9
RB3/INT3/SEG10
RB4/KBI0/SEG11
RB5/KBI1
Data Address<12>
31 Level Stack
STKPTR
4
BSR
12
FSR0
FSR1
FSR2
4
Address Latch
Access
Bank
Program Memory
(48/64 Kbytes)
RB6/KBI2/PGC
RB7/KBI3/PGD
12
Data Latch
PORTC
RC0/T1OSO/T13CKI
RC1/T1OSI/CCP2(1)
RC2/CCP1/SEG13
RC3/SCK/SCL
inc/dec
logic
8
Table Latch
RC4/SDI/SDA
Address
Decode
RC5/SDO/SEG12
RC6/TX1/CK1
RC7/RX1/DT1
ROM Latch
IR
Instruction Bus <16>
PORTD
PORTE
8
RD7/SEG7:RD0/SEG0
State Machine
Control Signals
Instruction
Decode and
Control
PRODH PRODL
8 x 8 Multiply
LCDBIAS1
LCDBIAS2
LCDBIAS3
3
8
COM0
RE4/COM1
RE5/COM2
RE6/COM3
RE7/CCP2(1)/SEG31
W
BITOP
8
8
8
Internal
OSC1(3)
OSC2(3)
T1OSI
Power-up
Timer
Oscillator
Block
8
8
PORTF
RF0/AN5/SEG18
Oscillator
Start-up Timer
ALU<8>
RF1/AN6/C2OUT/SEG19
RF2/AN7/C1OUT/SEG20
RF3/AN8/SEG21
RF4/AN9/SEG22
RF5/AN10/CVREF/SEG23
RF6/AN11/SEG24
INTRC
Oscillator
Power-on
Reset
8
8 MHz
Oscillator
Watchdog
Timer
T1OSO
Precision
Band Gap
Reference
Brown-out
Reset
Fail-Safe
MCLR(2)
VDD, VSS
Single-Supply
Programming
In-Circuit
RF7/SS/SEG25
PORTG
RG0/SEG30
RG1/TX2/CK2/SEG29
Clock Monitor
Debugger
RG2/RX2/DT2/SEG28
RG3/SEG27
RG4/SEG26
MCLR/VPP/RG5(2)
PORTH
PORTJ
ADC
12-Bit
BOR
Timer0
Timer1
Timer2
Timer3
RH3/SEG47:RH0/SEG44
RH7/SEG40:RH4/SEG43
HLVD
RJ3/SEG35:RJ0/SEG32
RJ7/SEG36:RJ4/SEG39
LCD
Driver
CCP2
MSSP
Comparators
CCP1
EUSART1
AUSART2
Note 1: CCP2 is multiplexed with RC1 when Configuration bit, CCP2MX, is set and RE7 when CCP2MX is not set.
2: RG5 is only available when MCLR functionality is disabled.
3: OSC1/CLKI and OSC2/CLKO are only available in select oscillator modes and when these pins are not being used as digital I/O.
For additional information, see Section 2.0 “Oscillator Configurations” of the “PIC18F6390/6490/8390/8490 Data Sheet” (DS39629).
DS39896B-page 12
© 2009 Microchip Technology Inc.
PIC18F6393/6493/8393/8493
TABLE 1-2:
PIC18F6X93 PINOUT I/O DESCRIPTIONS
Pin Number
Pin Buffer
Type Type
Pin Name
Description
TQFP
MCLR/VPP/RG5
MCLR
7
Master Clear (input) or programming voltage (input).
Master Clear (Reset) input. This pin is an active-low
Reset to the device.
I
ST
ST
VPP
RG5
P
I
Programming voltage input.
Digital input.
OSC1/CLKI/RA7
OSC1
39
40
Oscillator crystal or external clock input.
Oscillator crystal input or external clock source input.
ST buffer when configured in RC mode; CMOS otherwise.
External clock source input. Always associated
with pin function OSC1. (See related OSC1/CLKI,
OSC2/CLKO pins.)
I
I
ST
CLKI
CMOS
RA7
I/O
TTL
General purpose I/O pin.
OSC2/CLKO/RA6
OSC2
Oscillator crystal or clock output.
O
O
—
—
Oscillator crystal output. Connects to crystal or
resonator in Crystal Oscillator mode.
In RC mode, OSC2 pin outputs CLKO, which has
1/4 the frequency of OSC1 and denotes the
instruction cycle rate.
CLKO
RA6
I/O
TTL
General purpose I/O pin.
Legend: TTL = TTL compatible input
ST = Schmitt Trigger input with CMOS levels
CMOS = CMOS compatible input or output
Analog = Analog input
I
= Input
O
= Output
P
= Power
OD
= Open-Drain (no P diode to VDD)
Note 1: Default assignment for CCP2 when Configuration bit, CCP2MX, is set.
2: Alternate assignment for CCP2 when Configuration bit, CCP2MX, is cleared.
© 2009 Microchip Technology Inc.
DS39896B-page 13
PIC18F6393/6493/8393/8493
TABLE 1-2:
PIC18F6X93 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number
Pin Buffer
Pin Name
Description
Type Type
TQFP
PORTA is a bidirectional I/O port.
RA0/AN0
RA0
24
I/O
I
TTL
Analog
Digital I/O.
Analog input 0.
AN0
RA1/AN1
RA1
23
22
I/O
I
TTL
Analog
Digital I/O.
Analog input 1.
AN1
RA2/AN2/VREF-/SEG16
RA2
I/O
TTL
Digital I/O.
AN2
VREF-
SEG16
I
I
O
Analog
Analog
Analog
Analog input 2.
A/D reference voltage (Low) input.
SEG16 output for LCD.
RA3/AN3/VREF+/SEG17
21
RA3
I/O
TTL
Digital I/O.
AN3
VREF+
SEG17
I
I
O
Analog
Analog
Analog
Analog input 3.
A/D reference voltage (High) input.
SEG17 output for LCD.
RA4/T0CKI/SEG14
RA4
28
27
I/O ST/OD
Digital I/O. Open-drain when configured as output.
Timer0 external clock input.
SEG14 output for LCD.
T0CKI
SEG14
I
ST
O
Analog
RA5/AN4/HLVDIN/SEG15
RA5
I/O
TTL
Digital I/O.
AN4
HLVDIN
SEG15
I
I
O
Analog
Analog
Analog
Analog input 4.
Low-Voltage Detect input.
SEG15 output for LCD.
RA6
RA7
See the OSC2/CLKO/RA6 pin.
See the OSC1/CLKI/RA7 pin.
Legend: TTL = TTL compatible input
ST = Schmitt Trigger input with CMOS levels
CMOS = CMOS compatible input or output
Analog = Analog input
I
= Input
O
= Output
P
= Power
OD
= Open-Drain (no P diode to VDD)
Note 1: Default assignment for CCP2 when Configuration bit, CCP2MX, is set.
2: Alternate assignment for CCP2 when Configuration bit, CCP2MX, is cleared.
DS39896B-page 14
© 2009 Microchip Technology Inc.
PIC18F6393/6493/8393/8493
TABLE 1-2:
PIC18F6X93 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number
TQFP
Pin Buffer
Type Type
Pin Name
Description
PORTB is a bidirectional I/O port. PORTB can be software
programmed for internal weak pull-ups on all inputs.
RB0/INT0
RB0
48
47
I/O
I
TTL
ST
Digital I/O.
External interrupt 0.
INT0
RB1/INT1/SEG8
RB1
I/O
I
O
TTL
ST
Analog
Digital I/O.
External interrupt 1.
SEG8 output for LCD.
INT1
SEG8
RB2/INT2/SEG9
RB2
46
45
44
I/O
I
O
TTL
ST
Analog
Digital I/O.
External interrupt 2.
SEG9 output for LCD.
INT2
SEG9
RB3/INT3/SEG10
RB3
I/O
I
O
TTL
ST
Analog
Digital I/O.
External interrupt 3.
SEG10 output for LCD.
INT3
SEG10
RB4/KBI0/SEG11
RB4
I/O
I
O
TTL
TTL
Analog
Digital I/O.
Interrupt-on-change pin.
SEG11 output for LCD.
KBI0
SEG11
RB5/KBI1
RB5
43
42
I/O
I
TTL
TTL
Digital I/O.
Interrupt-on-change pin.
KBI1
RB6/KBI2/PGC
RB6
I/O
I
I/O
TTL
TTL
ST
Digital I/O.
Interrupt-on-change pin.
In-Circuit Debugger and ICSP™ programming clock pin.
KBI2
PGC
RB7/KBI3/PGD
RB7
37
I/O
I
I/O
TTL
TTL
ST
Digital I/O.
Interrupt-on-change pin.
In-Circuit Debugger and ICSP programming data pin.
KBI3
PGD
Legend: TTL = TTL compatible input
ST = Schmitt Trigger input with CMOS levels
CMOS = CMOS compatible input or output
Analog = Analog input
I
= Input
O
= Output
P
= Power
OD
= Open-Drain (no P diode to VDD)
Note 1: Default assignment for CCP2 when Configuration bit, CCP2MX, is set.
2: Alternate assignment for CCP2 when Configuration bit, CCP2MX, is cleared.
© 2009 Microchip Technology Inc.
DS39896B-page 15
PIC18F6393/6493/8393/8493
TABLE 1-2:
PIC18F6X93 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number
Pin Buffer
Pin Name
Description
Type Type
TQFP
PORTC is a bidirectional I/O port.
RC0/T1OSO/T13CKI
RC0
30
I/O
O
I
ST
—
ST
Digital I/O.
Timer1 oscillator output.
Timer1/Timer3 external clock input.
T1OSO
T13CKI
RC1/T1OSI/CCP2
RC1
29
33
34
35
36
31
32
I/O
I
I/O
ST
CMOS
ST
Digital I/O.
Timer1 oscillator input.
Capture 2 input/Compare 2 output/PWM2 output.
T1OSI
CCP2(1)
RC2/CCP1/SEG13
RC2
I/O
I/O
O
ST
ST
Analog
Digital I/O.
CCP1
SEG13
Capture 1 input/Compare 1 output/PWM1 output.
SEG13 output for LCD.
RC3/SCK/SCL
RC3
I/O
I/O
I/O
ST
ST
ST
Digital I/O.
SCK
SCL
Synchronous serial clock input/output for SPI mode.
Synchronous serial clock input/output for I2C™ mode.
RC4/SDI/SDA
RC4
I/O
I
I/O
ST
ST
ST
Digital I/O.
SDI
SDA
SPI data in.
I2C data I/O.
RC5/SDO/SEG12
RC5
I/O
O
O
ST
—
Analog
Digital I/O.
SPI data out.
SEG12 output for LCD.
SDO
SEG12
RC6/TX1/CK1
RC6
I/O
O
I/O
ST
—
ST
Digital I/O.
TX1
CK1
EUSART1 asynchronous transmit.
EUSART1 synchronous clock (see related RX1/DT1).
RC7/RX1/DT1
RC7
I/O
I
I/O
ST
ST
ST
Digital I/O.
RX1
DT1
EUSART1 asynchronous receive.
EUSART1 synchronous data (see related TX1/CK1).
Legend: TTL = TTL compatible input
ST = Schmitt Trigger input with CMOS levels
CMOS = CMOS compatible input or output
Analog = Analog input
I
= Input
O
= Output
P
= Power
OD
= Open-Drain (no P diode to VDD)
Note 1: Default assignment for CCP2 when Configuration bit, CCP2MX, is set.
2: Alternate assignment for CCP2 when Configuration bit, CCP2MX, is cleared.
DS39896B-page 16
© 2009 Microchip Technology Inc.
PIC18F6393/6493/8393/8493
TABLE 1-2:
PIC18F6X93 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number
TQFP
Pin Buffer
Type Type
Pin Name
Description
PORTD is a bidirectional I/O port.
RD0/SEG0
RD0
58
55
54
53
52
51
50
49
I/O
O
ST
Analog
Digital I/O.
SEG0 output for LCD.
SEG0
RD1/SEG1
RD1
I/O
O
ST
Analog
Digital I/O.
SEG1 output for LCD.
SEG1
RD2/SEG2
RD2
I/O
O
ST
Analog
Digital I/O.
SEG2 output for LCD.
SEG2
RD3/SEG3
RD3
I/O
O
ST
Analog
Digital I/O.
SEG3 output for LCD.
SEG3
RD4/SEG4
RD4
I/O
O
ST
Analog
Digital I/O.
SEG4 output for LCD.
SEG4
RD5/SEG5
RD5
I/O
O
ST
Analog
Digital I/O.
SEG5 output for LCD.
SEG5
RD6/SEG6
RD6
I/O
O
ST
Analog
Digital I/O.
SEG6 output for LCD.
SEG6
RD7/SEG7
RD7
I/O
O
ST
Analog
Digital I/O.
SEG7 output for LCD.
SEG7
Legend: TTL = TTL compatible input
ST = Schmitt Trigger input with CMOS levels
CMOS = CMOS compatible input or output
Analog = Analog input
I
= Input
O
= Output
P
= Power
OD
= Open-Drain (no P diode to VDD)
Note 1: Default assignment for CCP2 when Configuration bit, CCP2MX, is set.
2: Alternate assignment for CCP2 when Configuration bit, CCP2MX, is cleared.
© 2009 Microchip Technology Inc.
DS39896B-page 17
PIC18F6393/6493/8393/8493
TABLE 1-2:
PIC18F6X93 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number
Pin Buffer
Pin Name
Description
Type Type
TQFP
PORTE is a bidirectional I/O port.
BIAS1 input for LCD.
LCDBIAS1
LCDBIAS1
2
I
I
Analog
Analog
Analog
Analog
LCDBIAS2
LCDBIAS2
1
BIAS2 input for LCD.
LCDBIAS3
LCDBIAS3
64
63
62
I
BIAS3 input for LCD.
COM0
COM0
O
COM0 output for LCD.
RE4/COM1
RE4
I/O
O
ST
Analog
Digital I/O.
COM1 output for LCD.
COM1
RE5/COM2
RE5
61
60
59
I/O
O
ST
Analog
Digital I/O.
COM2 output for LCD.
COM2
RE6/COM3
RE6
I/O
O
ST
Analog
Digital I/O.
COM3 output for LCD.
COM3
RE7/CCP2/SEG31
RE7
I/O
I/O
O
ST
ST
Analog
Digital I/O.
CCP2(2)
Capture 2 input/Compare 2 output/PWM2 output.
SEG31 output for LCD.
SEG31
Legend: TTL = TTL compatible input
ST = Schmitt Trigger input with CMOS levels
CMOS = CMOS compatible input or output
Analog = Analog input
I
= Input
O
= Output
P
= Power
OD
= Open-Drain (no P diode to VDD)
Note 1: Default assignment for CCP2 when Configuration bit, CCP2MX, is set.
2: Alternate assignment for CCP2 when Configuration bit, CCP2MX, is cleared.
DS39896B-page 18
© 2009 Microchip Technology Inc.
PIC18F6393/6493/8393/8493
TABLE 1-2:
PIC18F6X93 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number
TQFP
Pin Buffer
Type Type
Pin Name
Description
PORTF is a bidirectional I/O port.
RF0/AN5/SEG18
RF0
18
17
I/O
I
O
ST
Analog
Analog
Digital I/O.
Analog input 5.
SEG18 output for LCD.
AN5
SEG18
RF1/AN6/C2OUT/SEG19
RF1
AN6
C2OUT
SEG19
I/O
I
O
O
ST
Analog
—
Digital I/O.
Analog input 6.
Comparator 2 output.
SEG19 output for LCD.
Analog
RF2/AN7/C1OUT/SEG20
16
RF2
AN7
C1OUT
SEG20
I/O
I
O
O
ST
Analog
—
Digital I/O.
Analog input 7.
Comparator 1 output.
SEG20 output for LCD.
Analog
RF3/AN8/SEG21
RF3
15
14
13
I/O
I
O
ST
Analog
Analog
Digital I/O.
Analog input 8.
SEG21 output for LCD.
AN8
SEG21
RF4/AN9/SEG22
RF4
I/O
I
O
ST
Analog
Analog
Digital I/O.
Analog input 9.
SEG22 output for LCD.
AN9
SEG22
RF5/AN10/CVREF/SEG23
RF5
I/O
I
O
O
ST
Digital I/O.
Analog input 10.
Comparator reference voltage output.
SEG23 output for LCD.
AN10
CVREF
SEG23
Analog
Analog
Analog
RF6/AN11/SEG24
RF6
12
11
I/O
I
O
ST
Analog
Analog
Digital I/O.
Analog input 11.
SEG24 output for LCD.
AN11
SEG24
RF7/SS/SEG25
RF7
SS
SEG25
I/O
I
O
ST
TTL
Analog
Digital I/O.
SPI™ slave select input.
SEG25 output for LCD.
Legend: TTL = TTL compatible input
ST = Schmitt Trigger input with CMOS levels
CMOS = CMOS compatible input or output
Analog = Analog input
I
= Input
O
= Output
P
= Power
OD
= Open-Drain (no P diode to VDD)
Note 1: Default assignment for CCP2 when Configuration bit, CCP2MX, is set.
2: Alternate assignment for CCP2 when Configuration bit, CCP2MX, is cleared.
© 2009 Microchip Technology Inc.
DS39896B-page 19
PIC18F6393/6493/8393/8493
TABLE 1-2:
PIC18F6X93 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number
Pin Buffer
Pin Name
Description
Type Type
TQFP
PORTG is a bidirectional I/O port.
RG0/SEG30
RG0
3
I/O
O
ST
Analog
Digital I/O.
SEG30 output for LCD.
SEG30
RG1/TX2/CK2/SEG29
4
5
RG1
TX2
CK2
I/O
O
I/O
O
ST
—
ST
Digital I/O.
AUSART2 asynchronous transmit.
AUSART2 synchronous clock (see related RX2/DT2).
SEG29 output for LCD.
SEG29
Analog
RG2/RX2/DT2/SEG28
RG2
RX2
DT2
SEG28
I/O
I
I/O
O
ST
ST
ST
Digital I/O.
AUSART2 asynchronous receive.
AUSART2 synchronous data (see related TX2/CK2).
SEG28 output for LCD.
Analog
RG3/SEG27
RG3
6
8
I/O
O
ST
Analog
Digital I/O.
SEG27 output for LCD.
SEG27
RG4/SEG26
RG4
I/O
O
ST
Analog
Digital I/O.
SEG26 output for LCD.
SEG26
RG5
VSS
See MCLR/VPP/RG5 pin.
9, 25, 41, 56
P
P
P
P
—
—
—
—
Ground reference for logic and I/O pins.
Positive supply for logic and I/O pins.
Ground reference for analog modules.
Positive supply for analog modules.
VDD
10, 26, 38, 57
AVSS
AVDD
20
19
Legend: TTL = TTL compatible input
ST = Schmitt Trigger input with CMOS levels
CMOS = CMOS compatible input or output
Analog = Analog input
I
= Input
O
= Output
P
= Power
OD
= Open-Drain (no P diode to VDD)
Note 1: Default assignment for CCP2 when Configuration bit, CCP2MX, is set.
2: Alternate assignment for CCP2 when Configuration bit, CCP2MX, is cleared.
DS39896B-page 20
© 2009 Microchip Technology Inc.
PIC18F6393/6493/8393/8493
TABLE 1-3:
PIC18F8X93 PINOUT I/O DESCRIPTIONS
Pin Number
Pin Buffer
Type Type
Pin Name
Description
TQFP
MCLR/VPP/RG5
MCLR
9
Master Clear (input) or programming voltage (input).
Master Clear (Reset) input. This pin is an active-low
Reset to the device.
I
ST
ST
VPP
RG5
P
I
Programming voltage input.
Digital input.
OSC1/CLKI/RA7
OSC1
49
50
Oscillator crystal or external clock input.
Oscillator crystal input or external clock source input.
ST buffer when configured in RC mode; CMOS otherwise.
External clock source input. Always associated with
pin function OSC1. (See related OSC1/CLKI,
OSC2/CLKO pins.)
I
I
ST
CLKI
CMOS
RA7
I/O
TTL
General purpose I/O pin.
OSC2/CLKO/RA6
OSC2
Oscillator crystal or clock output.
O
O
—
—
Oscillator crystal output. Connects to crystal or
resonator in Crystal Oscillator mode.
In RC mode, OSC2 pin outputs CLKO, which has
1/4 the frequency of OSC1 and denotes the
instruction cycle rate.
CLKO
RA6
I/O
TTL
General purpose I/O pin.
Legend: TTL = TTL compatible input
ST = Schmitt Trigger input with CMOS levels
CMOS = CMOS compatible input or output
Analog = Analog input
I
= Input
O
= Output
P
= Power
OD
= Open-Drain (no P diode to VDD)
Note 1: Default assignment for CCP2 when Configuration bit, CCP2MX, is set.
2: Alternate assignment for CCP2 when Configuration bit, CCP2MX, is cleared.
© 2009 Microchip Technology Inc.
DS39896B-page 21
PIC18F6393/6493/8393/8493
TABLE 1-3:
PIC18F8X93 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number
Pin Buffer
Pin Name
Description
Type Type
TQFP
PORTA is a bidirectional I/O port.
RA0/AN0
RA0
30
I/O
I
TTL
Analog
Digital I/O.
Analog input 0.
AN0
RA1/AN1
RA1
29
28
I/O
I
TTL
Analog
Digital I/O.
Analog input 1.
AN1
RA2/AN2/VREF-/SEG16
RA2
I/O
TTL
Digital I/O.
AN2
VREF-
SEG16
I
I
O
Analog
Analog
Analog
Analog input 2.
A/D reference voltage (Low) input.
SEG16 output for LCD.
RA3/AN3/VREF+/SEG17
27
RA3
I/O
TTL
Digital I/O.
AN3
VREF+
SEG17
I
I
O
Analog
Analog
Analog
Analog input 3.
A/D reference voltage (High) input.
SEG17 output for LCD.
RA4/T0CKI/SEG14
RA4
34
33
I/O ST/OD
Digital I/O. Open-drain when configured as output.
Timer0 external clock input.
SEG14 output for LCD.
T0CKI
SEG14
I
ST
O
Analog
RA5/AN4/HLVDIN/SEG15
RA5
I/O
TTL
Digital I/O.
AN4
HLVDIN
SEG15
I
I
O
Analog
Analog
Analog
Analog input 4.
Low-Voltage Detect input.
SEG15 output for LCD.
RA6
RA7
See the OSC2/CLKO/RA6 pin.
See the OSC1/CLKI/RA7 pin.
Legend: TTL = TTL compatible input
ST = Schmitt Trigger input with CMOS levels
CMOS = CMOS compatible input or output
Analog = Analog input
I
= Input
O
= Output
P
= Power
OD
= Open-Drain (no P diode to VDD)
Note 1: Default assignment for CCP2 when Configuration bit, CCP2MX, is set.
2: Alternate assignment for CCP2 when Configuration bit, CCP2MX, is cleared.
DS39896B-page 22
© 2009 Microchip Technology Inc.
PIC18F6393/6493/8393/8493
TABLE 1-3:
PIC18F8X93 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number
TQFP
Pin Buffer
Type Type
Pin Name
Description
PORTB is a bidirectional I/O port. PORTB can be software
programmed for internal weak pull-ups on all inputs.
RB0/INT0
RB0
58
57
I/O
I
TTL
ST
Digital I/O.
External interrupt 0.
INT0
RB1/INT1/SEG8
RB1
I/O
I
O
TTL
ST
Analog
Digital I/O.
External interrupt 1.
SEG8 output for LCD.
INT1
SEG8
RB2/INT2/SEG9
RB2
56
55
54
I/O
I
O
TTL
ST
Analog
Digital I/O.
External interrupt 2.
SEG9 output for LCD.
INT2
SEG9
RB3/INT3/SEG10
RB3
I/O
I
O
TTL
ST
Analog
Digital I/O.
External interrupt 3.
SEG10 output for LCD.
INT3
SEG10
RB4/KBI0/SEG11
RB4
I/O
I
O
TTL
TTL
Analog
Digital I/O.
Interrupt-on-change pin.
SEG11 output for LCD.
KBI0
SEG11
RB5/KBI1
RB5
53
52
I/O
I
TTL
TTL
Digital I/O.
Interrupt-on-change pin.
KBI1
RB6/KBI2/PGC
RB6
I/O
I
I/O
TTL
TTL
ST
Digital I/O.
Interrupt-on-change pin.
In-Circuit Debugger and ICSP™ programming clock pin.
KBI2
PGC
RB7/KBI3/PGD
RB7
47
I/O
I
I/O
TTL
TTL
ST
Digital I/O.
Interrupt-on-change pin.
In-Circuit Debugger and ICSP programming data pin.
KBI3
PGD
Legend: TTL = TTL compatible input
ST = Schmitt Trigger input with CMOS levels
CMOS = CMOS compatible input or output
Analog = Analog input
I
= Input
O
= Output
P
= Power
OD
= Open-Drain (no P diode to VDD)
Note 1: Default assignment for CCP2 when Configuration bit, CCP2MX, is set.
2: Alternate assignment for CCP2 when Configuration bit, CCP2MX, is cleared.
© 2009 Microchip Technology Inc.
DS39896B-page 23
PIC18F6393/6493/8393/8493
TABLE 1-3:
PIC18F8X93 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number
Pin Buffer
Pin Name
Description
Type Type
TQFP
PORTC is a bidirectional I/O port.
RC0/T1OSO/T13CKI
RC0
36
I/O
O
I
ST
—
ST
Digital I/O.
Timer1 oscillator output.
Timer1/Timer3 external clock input.
T1OSO
T13CKI
RC1/T1OSI/CCP2
RC1
35
43
44
45
46
37
38
I/O
I
I/O
ST
CMOS
ST
Digital I/O.
Timer1 oscillator input.
Capture 2 input/Compare 2 output/PWM2 output.
T1OSI
CCP2(1)
RC2/CCP1/SEG13
RC2
I/O
I/O
O
ST
ST
Analog
Digital I/O.
CCP1
SEG13
Capture 1 input/Compare 1 output/PWM1 output.
SEG13 output for LCD.
RC3/SCK/SCL
RC3
I/O
I/O
I/O
ST
ST
ST
Digital I/O.
SCK
SCL
Synchronous serial clock input/output for SPI mode.
Synchronous serial clock input/output for I2C™ mode.
RC4/SDI/SDA
RC4
I/O
I
I/O
ST
ST
ST
Digital I/O.
SDI
SDA
SPI data in.
I2C data I/O.
RC5/SDO/SEG12
RC5
I/O
O
O
ST
—
Analog
Digital I/O.
SPI data out.
SEG12 output for LCD.
SDO
SEG12
RC6/TX1/CK1
RC6
I/O
O
I/O
ST
—
ST
Digital I/O.
TX1
CK1
EUSART1 asynchronous transmit.
EUSART1 synchronous clock (see related RX1/DT1).
RC7/RX1/DT1
RC7
I/O
I
I/O
ST
ST
ST
Digital I/O.
RX1
DT1
EUSART1 asynchronous receive.
EUSART1 synchronous data (see related TX1/CK1).
Legend: TTL = TTL compatible input
ST = Schmitt Trigger input with CMOS levels
CMOS = CMOS compatible input or output
Analog = Analog input
I
= Input
O
= Output
P
= Power
OD
= Open-Drain (no P diode to VDD)
Note 1: Default assignment for CCP2 when Configuration bit, CCP2MX, is set.
2: Alternate assignment for CCP2 when Configuration bit, CCP2MX, is cleared.
DS39896B-page 24
© 2009 Microchip Technology Inc.
PIC18F6393/6493/8393/8493
TABLE 1-3:
PIC18F8X93 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number
TQFP
Pin Buffer
Type Type
Pin Name
Description
PORTD is a bidirectional I/O port.
RD0/SEG0
RD0
72
69
68
67
66
65
64
63
I/O
O
ST
Analog
Digital I/O.
SEG0 output for LCD.
SEG0
RD1/SEG1
RD1
I/O
O
ST
Analog
Digital I/O.
SEG1 output for LCD.
SEG1
RD2/SEG2
RD2
I/O
O
ST
Analog
Digital I/O.
SEG2 output for LCD.
SEG2
RD3/SEG3
RD3
I/O
O
ST
Analog
Digital I/O.
SEG3 output for LCD.
SEG3
RD4/SEG4
RD4
I/O
O
ST
Analog
Digital I/O.
SEG4 output for LCD.
SEG4
RD5/SEG5
RD5
I/O
O
ST
Analog
Digital I/O.
SEG5 output for LCD.
SEG5
RD6/SEG6
RD6
I/O
O
ST
Analog
Digital I/O.
SEG6 output for LCD.
SEG6
RD7/SEG7
RD7
I/O
O
ST
Analog
Digital I/O.
SEG7 output for LCD.
SEG7
Legend: TTL = TTL compatible input
ST = Schmitt Trigger input with CMOS levels
CMOS = CMOS compatible input or output
Analog = Analog input
I
= Input
O
= Output
P
= Power
OD
= Open-Drain (no P diode to VDD)
Note 1: Default assignment for CCP2 when Configuration bit, CCP2MX, is set.
2: Alternate assignment for CCP2 when Configuration bit, CCP2MX, is cleared.
© 2009 Microchip Technology Inc.
DS39896B-page 25
PIC18F6393/6493/8393/8493
TABLE 1-3:
PIC18F8X93 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number
Pin Buffer
Pin Name
Description
Type Type
TQFP
PORTE is a bidirectional I/O port.
BIAS1 input for LCD.
LCDBIAS1
LCDBIAS1
4
I
I
Analog
Analog
Analog
Analog
LCDBIAS2
LCDBIAS2
3
BIAS2 input for LCD.
LCDBIAS3
LCDBIAS3
78
77
76
I
BIAS3 input for LCD.
COM0
COM0
O
COM0 output for LCD.
RE4/COM1
RE4
I/O
O
ST
Analog
Digital I/O.
COM1 output for LCD.
COM1
RE5/COM2
RE5
75
74
73
I/O
O
ST
Analog
Digital I/O.
COM2 output for LCD.
COM2
RE6/COM3
RE6
I/O
O
ST
Analog
Digital I/O.
COM3 output for LCD.
COM3
RE7/CCP2/SEG31
RE7
I/O
I/O
O
ST
ST
Analog
Digital I/O.
CCP2(2)
Capture 2 input/Compare 2 output/PWM2 output.
SEG31 output for LCD.
SEG31
Legend: TTL = TTL compatible input
ST = Schmitt Trigger input with CMOS levels
CMOS = CMOS compatible input or output
Analog = Analog input
I
= Input
O
= Output
P
= Power
OD
= Open-Drain (no P diode to VDD)
Note 1: Default assignment for CCP2 when Configuration bit, CCP2MX, is set.
2: Alternate assignment for CCP2 when Configuration bit, CCP2MX, is cleared.
DS39896B-page 26
© 2009 Microchip Technology Inc.
PIC18F6393/6493/8393/8493
TABLE 1-3:
PIC18F8X93 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number
TQFP
Pin Buffer
Type Type
Pin Name
Description
PORTF is a bidirectional I/O port.
RF0/AN5/SEG18
RF0
24
23
I/O
I
O
ST
Analog
Analog
Digital I/O.
Analog input 5.
SEG18 output for LCD.
AN5
SEG18
RF1/AN6/C2OUT/SEG19
RF1
AN6
C2OUT
SEG19
I/O
I
O
O
ST
Analog
—
Digital I/O.
Analog input 6.
Comparator 2 output.
SEG19 output for LCD.
Analog
RF2/AN7/C1OUT/SEG20
18
RF2
AN7
C1OUT
SEG20
I/O
I
O
O
ST
Analog
—
Digital I/O.
Analog input 7.
Comparator 1 output.
SEG20 output for LCD.
Analog
RF3/AN8/SEG21
RF3
17
16
15
I/O
I
O
ST
Analog
Analog
Digital I/O.
Analog input 8.
SEG21 output for LCD.
AN8
SEG21
RF4/AN9/SEG22
RF4
I/O
I
O
ST
Analog
Analog
Digital I/O.
Analog input 9.
SEG22 output for LCD.
AN9
SEG22
RF5/AN10/CVREF/SEG23
RF5
I/O
I
O
O
ST
Digital I/O.
Analog input 10.
Comparator reference voltage output.
SEG23 output for LCD.
AN10
CVREF
SEG23
Analog
Analog
Analog
RF6/AN11/SEG24
RF6
14
13
I/O
I
O
ST
Analog
Analog
Digital I/O.
Analog input 11.
SEG24 output for LCD.
AN11
SEG24
RF7/SS/SEG25
RF7
SS
SEG25
I/O
I
O
ST
TTL
Analog
Digital I/O.
SPI slave select input.
SEG25 output for LCD.
Legend: TTL = TTL compatible input
ST = Schmitt Trigger input with CMOS levels
CMOS = CMOS compatible input or output
Analog = Analog input
I
= Input
O
= Output
P
= Power
OD
= Open-Drain (no P diode to VDD)
Note 1: Default assignment for CCP2 when Configuration bit, CCP2MX, is set.
2: Alternate assignment for CCP2 when Configuration bit, CCP2MX, is cleared.
© 2009 Microchip Technology Inc.
DS39896B-page 27
PIC18F6393/6493/8393/8493
TABLE 1-3:
PIC18F8X93 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number
Pin Buffer
Pin Name
Description
Type Type
TQFP
PORTG is a bidirectional I/O port.
RG0/SEG30
RG0
5
I/O
O
ST
Analog
Digital I/O.
SEG30 output for LCD.
SEG30
RG1/TX2/CK2/SEG29
6
7
RG1
TX2
CK2
I/O
O
I/O
O
ST
—
ST
Digital I/O.
AUSART2 asynchronous transmit.
AUSART2 synchronous clock (see related RX2/DT2).
SEG29 output for LCD.
SEG29
Analog
RG2/RX2/DT2/SEG28
RG2
RX2
DT2
SEG28
I/O
I
I/O
O
ST
ST
ST
Digital I/O.
AUSART2 asynchronous receive.
AUSART2 synchronous data (see related TX2/CK2).
SEG28 output for LCD.
Analog
RG3/SEG27
RG3
8
I/O
O
ST
Analog
Digital I/O.
SEG27 output for LCD.
SEG27
RG4/SEG26
RG4
10
I/O
O
ST
Analog
Digital I/O.
SEG26 output for LCD.
SEG26
RG5
See MCLR/VPP/RG5 pin.
Legend: TTL = TTL compatible input
ST = Schmitt Trigger input with CMOS levels
CMOS = CMOS compatible input or output
Analog = Analog input
I
= Input
O
= Output
P
= Power
OD
= Open-Drain (no P diode to VDD)
Note 1: Default assignment for CCP2 when Configuration bit, CCP2MX, is set.
2: Alternate assignment for CCP2 when Configuration bit, CCP2MX, is cleared.
DS39896B-page 28
© 2009 Microchip Technology Inc.
PIC18F6393/6493/8393/8493
TABLE 1-3:
PIC18F8X93 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number
TQFP
Pin Buffer
Type Type
Pin Name
Description
PORTH is a bidirectional I/O port.
RH0/SEG47
RH0
79
80
1
I/O
O
ST
Analog
Digital I/O.
SEG47 output for LCD.
SEG47
RH1/SEG46
RH1
I/O
O
ST
Analog
Digital I/O.
SEG46 output for LCD.
SEG46
RH2/SEG45
RH2
I/O
O
ST
Analog
Digital I/O.
SEG45 output for LCD.
SEG45
RH3/SEG44
RH3
2
I/O
O
ST
Analog
Digital I/O.
SEG44 output for LCD.
SEG44
RH4/SEG40
RH4
22
21
20
19
I/O
O
ST
Analog
Digital I/O.
SEG40 output for LCD.
SEG40
RH5/SEG41
RH5
I/O
O
ST
Analog
Digital I/O.
SEG41 output for LCD.
SEG41
RH6/SEG42
RH6
I/O
O
ST
Analog
Digital I/O.
SEG42 output for LCD.
SEG42
RH7/SEG43
RH7
I/O
O
ST
Analog
Digital I/O.
SEG43 output for LCD.
SEG43
Legend: TTL = TTL compatible input
ST = Schmitt Trigger input with CMOS levels
CMOS = CMOS compatible input or output
Analog = Analog input
I
= Input
O
= Output
P
= Power
OD
= Open-Drain (no P diode to VDD)
Note 1: Default assignment for CCP2 when Configuration bit, CCP2MX, is set.
2: Alternate assignment for CCP2 when Configuration bit, CCP2MX, is cleared.
© 2009 Microchip Technology Inc.
DS39896B-page 29
PIC18F6393/6493/8393/8493
TABLE 1-3:
PIC18F8X93 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number
Pin Buffer
Pin Name
Description
Type Type
TQFP
PORTJ is a bidirectional I/O port.
RJ0/SEG32
RJ0
62
I/O
O
ST
Analog
Digital I/O.
SEG32 output for LCD.
SEG32
RJ1/SEG33
RJ1
61
60
59
39
40
41
42
I/O
O
ST
Analog
Digital I/O.
SEG33 output for LCD.
SEG33
RJ2/SEG34
RJ2
I/O
O
ST
Analog
Digital I/O.
SEG34 output for LCD.
SEG34
RJ3/SEG35
RJ3
I/O
O
ST
Analog
Digital I/O.
SEG35 output for LCD.
SEG35
RJ4/SEG39
RJ4
I/O
O
ST
Analog
Digital I/O.
SEG39 output for LCD.
SEG39
RJ5/SEG38
RJ5
I/O
O
ST
Analog
Digital I/O
SEG38 output for LCD.
SEG38
RJ6/SEG37
RJ6
I/O
O
ST
Analog
Digital I/O.
SEG37 output for LCD.
SEG37
RJ7/SEG36
RJ7
I/O
O
ST
Analog
Digital I/O.
SEG36 output for LCD.
SEG36
VSS
11, 31, 51, 70
P
P
P
P
—
—
—
—
Ground reference for logic and I/O pins.
Positive supply for logic and I/O pins.
Ground reference for analog modules.
Positive supply for analog modules.
VDD
12, 32, 48, 71
AVSS
AVDD
26
25
Legend: TTL = TTL compatible input
ST = Schmitt Trigger input with CMOS levels
CMOS = CMOS compatible input or output
Analog = Analog input
I
= Input
O
= Output
P
= Power
OD
= Open-Drain (no P diode to VDD)
Note 1: Default assignment for CCP2 when Configuration bit, CCP2MX, is set.
2: Alternate assignment for CCP2 when Configuration bit, CCP2MX, is cleared.
DS39896B-page 30
© 2009 Microchip Technology Inc.
PIC18F6393/6493/8393/8493
The ADCON0 register, shown in Register 2-1, controls
2.0
12-BIT ANALOG-TO-DIGITAL
CONVERTER (A/D) MODULE
the operation of the A/D module. The ADCON1
register, shown in Register 2-2, configures the
functions of the port pins. The ADCON2 register,
shown in Register 2-3, configures the A/D clock
source, programmed acquisition time and justification.
The Analog-to-Digital (A/D) Converter module converts
an analog input signal to a 12-bit digital number. The
module has 12 inputs for both PIC18F6393/6493 (64-pin)
and PIC18F8393/8493 (80-pin) devices.
The module has five registers:
• A/D Result High Register (ADRESH)
• A/D Result Low Register (ADRESL)
• A/D Control Register 0 (ADCON0)
• A/D Control Register 1 (ADCON1)
• A/D Control Register 2 (ADCON2)
REGISTER 2-1:
ADCON0: A/D CONTROL REGISTER 0
U-0
—
U-0
—
R/W-0
CHS3
R/W-0
CHS2
R/W-0
CHS1
R/W-0
CHS0
R/W-0
R/W-0
ADON
GO/DONE
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7-6
bit 5-2
Unimplemented: Read as ‘0’
CHS3:CHS0: Analog Channel Select bits
0000= Channel 0 (AN0)
0001= Channel 1 (AN1)
0010= Channel 2 (AN2)
0011= Channel 3 (AN3)
0100= Channel 4 (AN4)
0101= Channel 5 (AN5)
0110= Channel 6 (AN6)
0111= Channel 7 (AN7)
1000= Channel 8 (AN8)
1001= Channel 9 (AN9)
1010= Channel 10 (AN10)
1011= Channel 11 (AN11)
1100= Unimplemented(1)
1101= Unimplemented(1)
1110= Unimplemented(1)
1111= Unimplemented(1)
bit 1
bit 0
GO/DONE: A/D Conversion Status bit
When ADON = 1:
1= A/D conversion in progress
0= A/D Idle
ADON: A/D On bit
1= A/D Converter module is enabled
0= A/D Converter module is disabled
Note 1: Performing a conversion on unimplemented channels will return a floating input measurement.
© 2009 Microchip Technology Inc.
DS39896B-page 31
PIC18F6393/6493/8393/8493
REGISTER 2-2:
ADCON1: A/D CONTROL REGISTER 1
U-0
—
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
VCFG1
VCFG0
PCFG3
PCFG2
PCFG1
PCFG0
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7-6
bit 5-4
Unimplemented: Read as ‘0’
VCFG1:VCFG0: Voltage Reference Configuration bits
A/D VREF+
A/D VREF-
00
01
10
11
AVDD
AVSS
External VREF+
AVDD
AVSS
External VREF-
External VREF-
External VREF+
bit 3-0
PCFG3:PCFG0: A/D Port Configuration Control bits
PCFG<3:0>
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
A
A
A
A
D
D
D
D
D
D
D
D
D
D
D
D
A
A
A
A
A
D
D
D
D
D
D
D
D
D
D
D
A
A
A
A
A
A
D
D
D
D
D
D
D
D
D
D
A
A
A
A
A
A
A
D
D
D
D
D
D
D
D
D
A
A
A
A
A
A
A
A
D
D
D
D
D
D
D
D
A
A
A
A
A
A
A
A
A
D
D
D
D
D
D
D
A
A
A
A
A
A
A
A
A
A
D
D
D
D
D
D
A
A
A
A
A
A
A
A
A
A
A
D
D
D
D
D
A
A
A
A
A
A
A
A
A
A
A
A
D
D
D
D
A
A
A
A
A
A
A
A
A
A
A
A
A
D
D
D
A
A
A
A
A
A
A
A
A
A
A
A
A
A
D
D
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
D
A = Analog input
D = Digital I/O
DS39896B-page 32
© 2009 Microchip Technology Inc.
PIC18F6393/6493/8393/8493
REGISTER 2-3:
ADCON2: A/D CONTROL REGISTER 2
R/W-0
ADFM
bit 7
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
ACQT2
ACQT1
ACQT0
ADCS2
ADCS1
ADCS0
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7
ADFM: A/D Result Format Select bit
1= Right justified
0= Left justified
bit 6
Unimplemented: Read as ‘0’
bit 5-3
ACQT2:ACQT0: A/D Acquisition Time Select bits
111= 20 TAD
110= 16 TAD
101= 12 TAD
100= 8 TAD
011= 6 TAD
010= 4 TAD
001= 2 TAD
(1)
000= 0 TAD
bit 2-0
ADCS2:ADCS0: A/D Conversion Clock Select bits
111= FRC (clock derived from A/D RC oscillator)(1)
110= FOSC/64
101= FOSC/16
100= FOSC/4
011= FRC (clock derived from A/D RC oscillator)(1)
010= FOSC/32
001= FOSC/8
000= FOSC/2
Note 1: If the A/D FRC clock source is selected, a delay of one TCY (instruction cycle) is added before the A/D
clock starts. This allows the SLEEPinstruction to be executed before starting a conversion.
© 2009 Microchip Technology Inc.
DS39896B-page 33
PIC18F6393/6493/8393/8493
The analog reference voltage is software selectable to
either the device’s positive and negative supply voltage
(VDD and VSS), or the voltage level on the RA3/AN3/
VREF+/SEG17 and RA2/AN2/VREF-/SEG16 pins.
A device Reset forces all registers to their Reset state.
This forces the A/D module to be turned off and any
conversion in progress is aborted.
Each port pin associated with the A/D Converter can be
configured as an analog input or a digital I/O. The
ADRESH and ADRESL registers contain the result of
the A/D conversion. When the A/D conversion is com-
plete, the result is loaded into the ADRESH:ADRESL
register pair, the GO/DONE bit (ADCON0<1>) is cleared
and the A/D Interrupt Flag bit, ADIF, is set. The block
diagram of the A/D module is shown in Figure 2-1.
The A/D Converter has a unique feature of being able
to operate while the device is in Sleep mode. To oper-
ate in Sleep, the A/D conversion clock must be derived
from the A/D’s internal RC oscillator.
The output of the sample and hold is the input into the
converter, which generates the result via successive
approximation.
FIGURE 2-1:
A/D BLOCK DIAGRAM
CHS3:CHS0
1011
AN11
1010
AN10
1001
AN9
1000
AN8
0111
AN7
0110
AN6
0101
AN5
0100
AN4
VAIN
0011
(Input Voltage)
12-Bit
A/D
Converter
AN3
0010
AN2
0001
VCFG1:VCFG0
AN1
(1)
0000
AVDD
AN0
X0
X1
1X
VREF+
VREF-
Reference
Voltage
0X
(1)
AVSS
Note 1: I/O pins have diode protection to VDD and VSS.
DS39896B-page 34
© 2009 Microchip Technology Inc.
PIC18F6393/6493/8393/8493
The value in the ADRESH:ADRESL registers is
unknown following Power-on and Brown-out Resets and
is not affected by any other Reset.
5. Wait for A/D conversion to complete by either:
• Polling for the GO/DONE bit to be cleared
OR
After the A/D module has been configured as desired,
the selected channel must be acquired before the
conversion is started. The analog input channels must
have their corresponding TRIS bits selected as an
input. To determine acquisition time, see Section 2.1
“A/D Acquisition Requirements”. After this acquisi-
tion time has elapsed, the A/D conversion can be
started. An acquisition time can be programmed to
occur between setting the GO/DONE bit and the actual
start of the conversion.
• Waiting for the A/D interrupt
6. Read A/D Result registers (ADRESH:ADRESL);
clear bit, ADIF, if required.
7. For the next conversion, go to step 1 or step 2,
as required. The A/D conversion time per bit is
defined as TAD. A minimum wait of 2 TAD is
required before the next acquisition starts.
FIGURE 2-2:
A/D TRANSFER FUNCTION
The following steps should be followed to perform an A/D
conversion:
FFFh
FFEh
1. Configure the A/D module:
• Configure analog pins, voltage reference and
digital I/O (ADCON1)
• Select A/D input channel (ADCON0)
• Select A/D acquisition time (ADCON2)
• Select A/D conversion clock (ADCON2)
• Turn on A/D module (ADCON0)
2. Configure A/D interrupt (if desired):
• Clear ADIF bit
003h
002h
001h
000h
• Set ADIE bit
• Set GIE bit
3. Wait the required acquisition time (if required).
4. Start conversion:
• Set GO/DONE bit (ADCON0<1>)
Analog Input Voltage
FIGURE 2-3:
ANALOG INPUT MODEL
VDD
Sampling
Switch
VT = 0.6V
ANx
SS
RIC ≤ 1k
RSS
Rs
CPIN
5 pF
CHOLD = 25 pF
VSS
VAIN
ILEAKAGE
±100 nA
VT = 0.6V
Legend: CPIN
= Input Capacitance
= Threshold Voltage
6V
5V
4V
3V
2V
VT
ILEAKAGE = Leakage Current at the pin due to
various junctions
VDD
RIC
= Interconnect Resistance
SS
= Sampling Switch
CHOLD
RSS
= Sample/Hold Capacitance (from DAC)
= Sampling Switch Resistance
1
2
3
4
(kΩ)
Sampling Switch
© 2009 Microchip Technology Inc.
DS39896B-page 35
PIC18F6393/6493/8393/8493
To calculate the minimum acquisition time, Equation 2-1
may be used. This equation assumes that 1/2 LSb error
is used (4096 steps for the 12-bit A/D). The 1/2 LSb error
is the maximum error allowed for the A/D to meet its
specified resolution.
2.1
A/D Acquisition Requirements
For the A/D Converter to meet its specified accuracy,
the charge holding capacitor (CHOLD) must be allowed
to fully charge to the input channel voltage level. The
analog input model is shown in Figure 2-3. The source
impedance (RS) and the internal sampling switch (RSS)
impedance directly affect the time required to charge
the capacitor, CHOLD. The sampling switch (RSS)
impedance varies over the device voltage (VDD). The
source impedance affects the offset voltage at the ana-
log input (due to pin leakage current). The maximum
recommended impedance for analog sources is
2.5 kΩ. After the analog input channel is selected
(changed), the channel must be sampled for at least
Equation 2-3 shows the calculation of the minimum
required acquisition time, TACQ. This calculation is
based on the following application system
assumptions:
CHOLD
Rs
Conversion Error
VDD
Temperature
=
=
≤
=
=
25 pF
2.5 kΩ
1/2 LSb
3V → Rss = 4 kΩ
85°C (system max.)
the minimum acquisition time before starting
conversion.
a
Note:
When the conversion is started, the
holding capacitor is disconnected from the
input pin.
EQUATION 2-1:
ACQUISITION TIME
TACQ
=
=
Amplifier Settling Time + Holding Capacitor Charging Time + Temperature Coefficient
TAMP + TC + TCOFF
EQUATION 2-2:
A/D MINIMUM CHARGING TIME
VHOLD
or
TC
=
=
(VREF – (VREF/4096)) • (1 – e(-TC/CHOLD(RIC + RSS + RS))
)
– (CHOLD)(RIC + RSS + RS) ln(1/4096)
EQUATION 2-3:
CALCULATING THE MINIMUM REQUIRED ACQUISITION TIME
TACQ
TAMP
TCOFF
=
=
=
TAMP + TC + TCOFF
0.2 µs
(Temp – 25°C)(0.02 µs/°C)
(85°C – 25°C)(0.02 µs/°C)
1.2 µs
Temperature coefficient is only required for temperatures > 25°C. Below 25°C, TCOFF = 0 µs.
TC
=
-(CHOLD)(RIC + RSS + RS) ln(1/4096) µs
-(25 pF) (1 kΩ + 4 kΩ + 2.5 kΩ) ln(0.0002441) µs
1.56 µs
TACQ
=
0.2 µs + 1.56 μs + 1.2 µs
2.96 µs
DS39896B-page 36
© 2009 Microchip Technology Inc.
PIC18F6393/6493/8393/8493
2.2
Selecting and Configuring
Acquisition Time
2.3
Selecting the A/D Conversion
Clock
The ADCON2 register allows the user to select an
acquisition time that occurs each time the GO/DONE
bit is set. It also gives users the option to use an
automatically determined acquisition time.
The A/D conversion time per bit is defined as TAD. The
A/D conversion requires 13 TAD per 12-bit conversion.
The source of the A/D conversion clock is software
selectable. There are seven possible options for TAD:
Acquisition time may be set with the ACQT2:ACQT0
bits (ADCON2<5:3>), which provide a range of 2 to
20 TAD. When the GO/DONE bit is set, the A/D module
continues to sample the input for the selected acquisi-
tion time, then automatically begins a conversion.
Since the acquisition time is programmed, there may
be no need to wait for an acquisition time between
selecting a channel and setting the GO/DONE bit.
• 2 TOSC
• 4 TOSC
• 8 TOSC
• 16 TOSC
• 32 TOSC
• 64 TOSC
• Internal RC Oscillator
Manual
acquisition
is
selected
when
For correct A/D conversions, the A/D conversion clock
(TAD) must be as short as possible, but greater than the
minimum TAD. (See parameter 130 for more
information.)
ACQT2:ACQT0 = 000. When the GO/DONE bit is set,
sampling is stopped and a conversion begins. The user
is responsible for ensuring the required acquisition time
has passed between selecting the desired input
channel and setting the GO/DONE bit. This option is
also the default Reset state of the ACQT2:ACQT0 bits
and is compatible with devices that do not offer
programmable acquisition times.
Table 2-1 shows the resultant TAD times derived from
the device operating frequencies and the A/D clock
source selected.
In either case, when the conversion is completed, the
GO/DONE bit is cleared, the ADIF flag is set and the
A/D begins sampling the currently selected channel
again. If an acquisition time is programmed, there is
nothing to indicate if the acquisition time has ended or
if the conversion has begun.
TABLE 2-1:
TAD vs. DEVICE OPERATING FREQUENCIES
Assumes TAD Min. = 0.8 μs
A/D Clock Source (TAD)
Operation
ADCS2:ADCS0
Maximum FOSC
2 TOSC
4 TOSC
8 TOSC
16 TOSC
32 TOSC
64 TOSC
RC(1)
000
100
001
101
010
110
x11
2.50 MHz
5.00 MHz
10.00 MHz
20.00 MHz
40.00 MHz
40.00 MHz
1.00 MHz(2)
Note 1: The RC source has a typical TAD time of 2.5 μs.
2: For device frequencies above 1 MHz, the device must be in Sleep for the entire conversion or a FOSC
divider should be used instead; otherwise, the A/D accuracy specification may not be met.
© 2009 Microchip Technology Inc.
DS39896B-page 37
PIC18F6393/6493/8393/8493
2.4
Operation in Power-Managed
Modes
2.5
Configuring Analog Port Pins
The ADCON1, TRISA, TRISF and TRISH registers all
configure the A/D port pins. The port pins needed as
analog inputs must have their corresponding TRIS bits
set (input). If the TRIS bit is cleared (output), the digital
output level (VOH or VOL) will be converted.
The selection of the automatic acquisition time and A/D
conversion clock is determined in part by the clock
source and frequency while in a power-managed mode.
If the A/D is expected to operate while the device is in
a power-managed mode, the ADCS2:ADCS0 bits in
ADCON2 should be updated in accordance with the
clock source to be used. The ACQT2:ACQT0 bits do
not need to be adjusted as the ADCS2:ADCS0 bits
adjust the TAD time for the new clock speed. After enter-
ing the mode, an A/D acquisition or conversion may be
started. Once started, the device should continue to be
clocked by the same clock source until the conversion
has been completed.
The A/D operation is independent of the state of the
CHS3:CHS0 bits and the TRIS bits.
Note 1: When reading the PORT register, all pins
configured as analog input channels will
read as cleared (a low level). Analog con-
version on pins configured as digital pins
can be performed. The voltage on the pin
will be accurately converted.
2: Analog levels on any pin defined as a dig-
ital input may cause the digital input buffer
to consume current out of the device’s
specification limits.
If desired, the device may be placed into the
corresponding Idle mode during the conversion. If the
device clock frequency is less than 1 MHz, the A/D RC
clock source should be selected.
Operation in Sleep mode requires the A/D FRC clock to
be selected. If the ACQT2:ACQT0 bits are set to ‘000’
and a conversion is started, the conversion will be
delayed one instruction cycle to allow execution of the
SLEEPinstruction and entry to Sleep mode. The IDLEN
bit (OSCCON<7>) must have already been cleared
prior to starting the conversion.
DS39896B-page 38
© 2009 Microchip Technology Inc.
PIC18F6393/6493/8393/8493
After the A/D conversion is completed or aborted, a
2 TAD wait is required before the next acquisition can
be started. After this wait, acquisition on the selected
channel is automatically started.
2.6
A/D Conversions
Figure 2-4 shows the operation of the A/D Converter
after the GO/DONE bit has been set and the
ACQT2:ACQT0 bits are cleared. A conversion is
started after the following instruction to allow entry into
Sleep mode before the conversion begins.
Note:
The GO/DONE bit should NOT be set in
the same instruction that turns on the A/D.
Code should wait at least 2 μs after
enabling the A/D before beginning an
acquisition and conversion cycle.
Figure 2-5 shows the operation of the A/D Converter
after the GO/DONE bit has been set, the
ACQT2:ACQT0 bits are set to ‘010’ and a 4 TAD acqui-
sition time has been selected before the conversion
starts.
2.7
Discharge
The discharge phase is used to initialize the value of
the holding capacitor. The array is discharged before
every sample. This feature helps to optimize the unity
gain amplifier, as the circuit always needs to charge the
capacitor array, rather than charge/discharge based on
previous-measure values.
Clearing the GO/DONE bit during a conversion will abort
the current conversion. The A/D Result register pair will
not be updated with the partially completed A/D
conversion sample. This means the ADRESH:ADRESL
registers will continue to contain the value of the last
completed conversion (or the last value written to the
ADRESH:ADRESL registers).
FIGURE 2-4:
A/D CONVERSION TAD CYCLES (ACQT<2:0> = 000, TACQ = 0)
TCY – TAD TAD1 TAD2 TAD3 TAD4 TAD5 TAD6 TAD7 TAD8 TAD9 TAD10 TAD11 TAD12 TAD13 TAD1
b6
b3
b2
b1
b0
b11 b10
b9
Conversion starts
b8
b7
b5
b4
Discharge
(typically 200 ns)
Holding capacitor is disconnected from analog input (typically 100 ns)
Set GO/DONE bit
On the following cycle:
ADRESH:ADRESL are loaded, GO/DONE bit is cleared,
ADIF bit is set, holding capacitor is connected to analog input
FIGURE 2-5:
A/D CONVERSION TAD CYCLES (ACQT<2:0> = 010, TACQ = 4 TAD)
TAD Cycles
TACQT Cycles
6
7
8
9
10
b4 b3
11
b2
12
b1 b0
13 TAD1
1
2
3
4
1
2
3
4
5
b9
b8
b5
b10
b7
b6
b11
Automatic
Acquisition
Time
Discharge
(typically
200 ns)
Conversion starts
(Holding capacitor is disconnected)
Set GO/DONE bit
(Holding capacitor continues
acquiring input)
On the following cycle:
ADRESH:ADRESL are loaded, GO/DONE bit is cleared,
ADIF bit is set, holding capacitor is connected to analog input
© 2009 Microchip Technology Inc.
DS39896B-page 39
PIC18F6393/6493/8393/8493
desired location). The appropriate analog input chan-
nel must be selected and the minimum acquisition
period is either timed by the user, or an appropriate
TACQ time selected before the Special Event Trigger
sets the GO/DONE bit (starts a conversion).
2.8
Use of the ECCP2 Trigger
An A/D conversion can be started by the Special Event
Trigger of the ECCP2 module. This requires that the
CCP2M3:CCP2M0
programmed as ‘1011’ and that the A/D module is
enabled (ADON bit is set). When the trigger occurs, the
GO/DONE bit will be set, starting the A/D acquisition
and conversion, and the Timer1 (or Timer3) counter will
be reset to zero. Timer1 (or Timer3) is reset to automat-
ically repeat the A/D acquisition period with minimal
software overhead (moving ADRESH:ADRESL to the
bits
(CCP2CON<3:0>)
be
If the A/D module is not enabled (ADON is cleared), the
Special Event Trigger will be ignored by the A/D module
but will still reset the Timer1 (or Timer3) counter.
TABLE 2-2:
Name
REGISTERS ASSOCIATED WITH A/D OPERATION
Reset
Values
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
(3)
INTCON
PIR1
PIE1
GIE/GIEH PEIE/GIEL TMR0IE
INT0IE
TX1IF
TX1IE
TX1IP
—
RBIE
TMR0IF
CCP1IF
CCP1IE
CCP1IP
HLVDIF
HLVDIE
HLVDIP
INT0IF
TMR2IF
TMR2IE
TMR2IP
TMR3IF
TMR3IE
TMR3IP
RBIF
(3)
—
—
ADIF
ADIE
ADIP
CMIF
CMIE
CMIP
RC1IF
RC1IE
RC1IP
—
SSP1IF
SSP1IE
SSP1IP
BCL1IF
BCL1IE
BCL1IP
TMR1IF
TMR1IE
TMR1IP
CCP2IF
CCP2IE
CCP2IP
(3)
(3)
IPR1
PIR2
PIE2
—
(3)
OSCFIF
OSCFIE
OSCFIP
(3)
—
—
(3)
IPR2
—
—
(3)
ADRESH A/D Result Register High Byte
ADRESL A/D Result Register Low Byte
(3)
(3)
(3)
(3)
(3)
(3)
(3)
ADCON0
ADCON1
ADCON2
TRISA
—
—
—
—
—
CHS3
VCFG1
ACQT2
CHS2
VCFG0
ACQT1
TRISA4
TRISF4
TRISH4
CHS1
PCFG3
ACQT0
TRISA3
TRISF3
TRISH3
CHS0 GO/DONE ADON
PCFG2
ADCS2
TRISA2
TRISF2
TRISH2
PCFG1
ADCS1
TRISA1
TRISF1
TRISH1
PCFG0
ADCS0
TRISA0
TRISF0
TRISH0
ADFM
TRISA7(1) TRISA6(1) TRISA5
TRISF
TRISH(2)
TRISF7
TRISH7
TRISF6
TRISH6
TRISF5
TRISH5
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used for A/D conversion.
Note 1: PORTA<7:6> and their direction bits are individually configured as port pins based on various primary
oscillator modes. When disabled, these bits read as ‘0’.
2: These registers are not implemented on 64-pin devices.
3: For these Reset values, see the “PIC18F6390/6490/8390/8490 Data Sheet” (DS39629).
DS39896B-page 40
© 2009 Microchip Technology Inc.
PIC18F6393/6493/8393/8493
3.1
Device ID Registers
3.0
SPECIAL FEATURES OF THE
CPU
The Device ID registers are “read-only” registers.
They identify the device type and revision to device
programmers and can be read by firmware using table
reads.
Note:
For additional details on the Configuration
bits, refer to Section 23.1 “Configuration
Bits” in the “PIC18F6390/6490/8390/8490
Data Sheet” (DS39629). Device ID informa-
tion presented in this section is for the
PIC18F6393/6493/8393/8493 devices only.
PIC18F6393/6493/8393/8493 devices include several
features intended to maximize reliability and minimize
cost through elimination of external components.
These include:
• Device ID Registers
TABLE 3-1:
DEVICE IDs
Default/
File Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Unprogrammed
Value
(1)
3FFFFEh DEVID1
3FFFFFh DEVID2
Legend: x= unknown
DEV2
DEV1
DEV9
DEV0
DEV8
REV4
DEV7
REV3
DEV6
REV2
DEV5
REV1
DEV4
REV0
DEV3
xxxx xxxx
(1)
DEV10
xxxx xxxx
Note 1: See Register 3-1 and Register 3-2 for DEVID values. DEVID registers are read-only and cannot be programmed by the user.
© 2009 Microchip Technology Inc.
DS39896B-page 41
PIC18F6393/6493/8393/8493
REGISTER 3-1:
DEVID1: DEVICE ID REGISTER 1 FOR PIC18F6393/6493/8393/8493 DEVICES
R
DEV2
bit 7
R
R
R
R
R
R
R
DEV1
DEV0
REV4
REV3
REV2
REV1
REV0
bit 0
Legend:
R = Read-only bit
P = Programmable bit
U = Unimplemented bit, read as ‘0’
-n = Value when device is unprogrammed
u = Unchanged from programmed state
bit 7-5
bit 4-0
DEV2:DEV0: Device ID bits
See Register 3-2 for a complete listing.
REV4:REV0: Revision ID bits
These bits are used to indicate the device revision.
REGISTER 3-2:
DEVID2: DEVICE ID REGISTER 2 FOR PIC18F6393/6493/8393/8493 DEVICES
R
DEV10
bit 7
R
R
R
R
R
R
R
DEV9
DEV8
DEV7
DEV6
DEV5
DEV4
DEV3
bit 0
Legend:
R = Read-only bit
P = Programmable bit
U = Unimplemented bit, read as ‘0’
-n = Value when device is unprogrammed
u = Unchanged from programmed state
bit 7-0
DEV10:DEV3: Device ID bits
DEV10:DEV3
(DEVID2<7:0>)
DEV2:DEV0
(DEVID1<7:5>)
Device
PIC18F6393
PIC18F6493
PIC18F8393
PIC18F8493
0001 1010
0000 1110
0001 1010
0000 1110
000
000
001
001
DS39896B-page 42
© 2009 Microchip Technology Inc.
PIC18F6393/6493/8393/8493
4.0
ELECTRICAL CHARACTERISTICS
Note: Other than some basic data, this section documents only the PIC18F6393/6493/8393/8493 devices’ specifica-
tions that differ from those of the PIC18F6390/6490/8390/8490 devices. For detailed information on the
electrical specifications shared by the PIC18F6393/6493/8393/8493 and PIC18F6390/6490/8390/8490
devices, see the “PIC18F6390/6490/8390/8490 Data Sheet” (DS39629).
(†)
Absolute Maximum Ratings
Ambient temperature under bias.............................................................................................................-40°C to +125°C
Storage temperature .............................................................................................................................. -65°C to +150°C
Voltage on any pin with respect to VSS (except VDD and MCLR) ................................................... -0.3V to (VDD + 0.3V)
Voltage on VDD with respect to VSS ......................................................................................................... -0.3V to +7.5V
Voltage on MCLR with respect to VSS (Note 2) ......................................................................................... 0V to +13.25V
Total power dissipation (Note 1) ...............................................................................................................................1.0W
Maximum current out of VSS pin ...........................................................................................................................300 mA
Maximum current into VDD pin ..............................................................................................................................250 mA
Input clamp current, IIK (VI < 0 or VI > VDD)...................................................................................................................... ±20 mA
Output clamp current, IOK (VO < 0 or VO > VDD) .............................................................................................................. ±20 mA
Maximum output current sunk by any I/O pin..........................................................................................................25 mA
Maximum output current sourced by any I/O pin ....................................................................................................25 mA
Maximum current sunk by all ports .......................................................................................................................200 mA
Maximum current sourced by all ports ..................................................................................................................200 mA
Note 1: Power dissipation is calculated as follows:
PDIS = VDD x {IDD – ∑ IOH} + ∑ {(VDD – VOH) x IOH} + ∑ (VOL x IOL)
2: Voltage spikes below VSS at the MCLR/VPP/RG5 pin, inducing currents greater than 80 mA, may cause
latch-up. Thus, a series resistor of 50-100Ω should be used when applying a “low” level to the MCLR/VPP/
RG5 pin, rather than pulling this pin directly to VSS.
† NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at those or any other conditions above those
indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for
extended periods may affect device reliability.
© 2009 Microchip Technology Inc.
DS39896B-page 43
PIC18F6393/6493/8393/8493
FIGURE 4-1:
PIC18F6393/6493/8393/8493 VOLTAGE-FREQUENCY GRAPH (INDUSTRIAL)
6.0V
5.5V
5.0V
4.5V
4.0V
PIC18FX393/X493
4.2V
3.5V
3.0V
2.5V
2.0V
40 MHz
Frequency
FIGURE 4-2:
PIC18LF6393/6493/8393/8493 VOLTAGE-FREQUENCY GRAPH (INDUSTRIAL)
6.0V
5.5V
5.0V
PIC18LFX393/X493
4.5V
4.2V
4.0V
3.5V
3.0V
2.5V
2.0V
40 MHz
4 MHz
Frequency
FMAX = (16.36 MHz/V) (VDDAPPMIN – 2.0V) + 4 MHz
Note: VDDAPPMIN is the minimum voltage of the PIC® device in the application.
DS39896B-page 44
© 2009 Microchip Technology Inc.
PIC18F6393/6493/8393/8493
TABLE 4-1:
A/D CONVERTER CHARACTERISTICS: PIC18F6393/6493/8393/8493 (INDUSTRIAL)
Param
Sym
No.
Characteristic
Min
Typ
Max
Units
Conditions
A01
A03
NR
EIL
Resolution
—
—
—
—
—
—
—
—
—
—
12
±2.0
bit
ΔVREF ≥ 3.0V
ΔVREF ≥ 3.0V
Integral Linearity Error
<±1
LSB VDD = 3.0V
LSB VDD = 5.0V
LSB VDD = 3.0V
LSB VDD = 5.0V
LSB VDD = 3.0V
LSB VDD = 5.0V
LSB VDD = 3.0V
LSB VDD = 5.0V
—
—
±2.0
A04
A06
A07
EDL
Differential Linearity Error
<±1
+1.5/-1.0
+1.5/-1.0
±5
ΔVREF ≥ 3.0V
ΔVREF ≥ 3.0V
ΔVREF ≥ 3.0V
—
EOFF Offset Error
<±1
—
±3
EGN
Gain Error
<±1
±2.00
±2.00
—
Guaranteed
—
(1)
A10
A20
—
Monotonicity
VSS ≤ VAIN ≤ VREF
ΔVREF Reference Voltage Range
3
VDD – VSS
V
For 12-bit resolution
(VREFH – VREFL)
A21
A22
A25
A30
VREFH Reference Voltage High
VREFL Reference Voltage Low
VSS + 3.0V
VSS – 0.3V
VREFL
—
—
—
—
VDD + 0.3V
VDD – 3.0V
VREFH
V
V
For 12-bit resolution
For 12-bit resolution
VAIN
ZAIN
Analog Input Voltage
V
Recommended
—
2.5
kΩ
Impedance of Analog
Voltage Source
(2)
A50
IREF
VREF Input Current
—
—
—
—
5
150
μA
μA
During VAIN acquisition.
During A/D conversion
cycle.
Note 1: The A/D conversion result never decreases with an increase in the input voltage and has no missing codes.
2: VREFH current is from the RA3/AN3/VREF+/SEG17 pin or VDD, whichever is selected as the VREFH source. VREFL
current is from the RA2/AN2/VREF-/SEG16 pin or VSS, whichever is selected as the VREFL source.
© 2009 Microchip Technology Inc.
DS39896B-page 45
PIC18F6393/6493/8393/8493
FIGURE 4-3:
A/D CONVERSION TIMING
BSF ADCON0, GO
(Note 2)
131
130
Q4
A/D CLK(1)
132
. . .
. . .
11
10
9
3
2
1
0
A/D DATA
NEW_DATA
TCY
OLD_DATA
ADRES
ADIF
GO
DONE
SAMPLING STOPPED
SAMPLE
Note 1: If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the SLEEPinstruction
to be executed.
2: This is a minimal RC delay (typically 100 ns), which also disconnects the holding capacitor from the analog input.
TABLE 4-2:
A/D CONVERSION REQUIREMENTS
Characteristic
Param
No.
Symbol
Min
Max
Units
Conditions
130
TAD
A/D Clock Period
PIC18FXXXX
0.8
1.4
12.5(1)
25.0(1)
μs TOSC based, VREF ≥ 3.0V
PIC18LFXXXX
μs VDD = 3.0V; TOSC based,
VREF full range
PIC18FXXXX
—
—
13
1
3
μs A/D RC mode
μs VDD = 3.0V; A/D RC mode
TAD
PIC18LFXXXX
131
TCNV
Conversion Time
14
(not including acquisition time)(2)
Acquisition Time(3)
132
135
137
TACQ
TSWC
TDIS
1.4
—
—
(Note 4)
—
μs
Switching Time from Convert → Sample
Discharge Time
0.2
μs
Note 1: The time of the A/D clock period is dependent on the device frequency and the TAD clock divider.
2: ADRES registers may be read on the following TCY cycle.
3: The time for the holding capacitor to acquire the “New” input voltage when the voltage changes full scale
after the conversion (VDD to VSS or VSS to VDD). The source impedance (RS) on the input channels is 50Ω.
4: On the following cycle of the device clock.
DS39896B-page 46
© 2009 Microchip Technology Inc.
PIC18F6393/6493/8393/8493
5.0
PACKAGING INFORMATION
For packaging information, see the “PIC18F6390/6490/
8390/8490 Data Sheet” (DS39629).
© 2009 Microchip Technology Inc.
DS39896B-page 47
PIC18F6393/6493/8393/8493
NOTES:
DS39896B-page 48
© 2009 Microchip Technology Inc.
PIC18F6393/6493/8393/8493
APPENDIX A: REVISION HISTORY
APPENDIX B: DEVICE
DIFFERENCES
Revision A (September 2007)
The differences between the devices listed in this data
sheet are shown in Table B-1.
Original data sheet for the PIC18F6393/6493/8393/
8493 devices.
Revision B (October 2009)
Removed ”Preliminary” marking.
TABLE B-1:
DEVICE DIFFERENCES
Features
PIC18F6393
PIC18F6493
PIC18F8393
PIC18F8493
Number of Pixels the LCD Driver
Can Drive
128 (4 x 32)
128 (4 x 32)
192 (4 x 48)
192 (4 x 48)
I/O Ports
Ports A, B, C, D, E, Ports A, B, C, D, E, Ports A, B, C, D, E, Ports A, B, C, D, E,
F, G
F, G
F, G, H, J
F, G, H, J
Flash Program Memory
Packages
8 Kbytes
16 Kbytes
64-Pin TQFP
8 Kbytes
16 Kbytes
64-Pin TQFP
80-Pin TQFP
80-Pin TQFP
© 2009 Microchip Technology Inc.
DS39896B-page 49
PIC18F6393/6493/8393/8493
APPENDIX C: CONVERSION
CONSIDERATIONS
APPENDIX D: MIGRATION FROM
BASELINE TO
ENHANCED DEVICES
This appendix discusses the considerations for
converting from previous versions of a device to the
ones listed in this data sheet. Typically, these changes
are due to the differences in the process technology
used. An example of this type of conversion is from a
PIC16C74A to a PIC16C74B.
This section discusses how to migrate from a Baseline
device (i.e., PIC16C5X) to an Enhanced MCU device
(i.e., PIC18FXXX).
The following are the list of modifications over the
PIC16C5X microcontroller family:
Not Applicable
Not Currently Available
DS39896B-page 50
© 2009 Microchip Technology Inc.
PIC18F6393/6493/8393/8493
APPENDIX E: MIGRATION FROM
APPENDIX F: MIGRATION FROM
HIGH-END TO
MID-RANGE TO
ENHANCED DEVICES
ENHANCED DEVICES
A detailed discussion of the differences between the
mid-range MCU devices (i.e., PIC16CXXX) and the
enhanced devices (i.e., PIC18FXXX) is provided in
AN716, “Migrating Designs from PIC16C74A/74B to
PIC18C442”. The changes discussed, while device-
specific, are generally applicable to all mid-range to
enhanced device migrations.
A detailed discussion of the migration pathway and
differences between the high-end MCU devices (i.e.,
PIC17CXXX) and the enhanced devices (i.e.,
PIC18FXXX) is provided in AN726, “PIC17CXXX to
PIC18CXXX Migration”. This Application Note is
available as Literature Number DS00726.
This Application Note is available as Literature Number
DS00716.
© 2009 Microchip Technology Inc.
DS39896B-page 51
PIC18F6393/6493/8393/8493
NOTES:
DS39896B-page 52
© 2009 Microchip Technology Inc.
PIC18F6393/6493/8393/8493
INDEX
Voltage-Frequency Graph .......................................... 44
Equations
A/D Acquisition Time .................................................. 36
A/D Minimum Charging Time ..................................... 36
Calculating the Minimum Required Acquisition Time . 36
Errata.................................................................................... 7
A
A/D...................................................................................... 31
A/D Converter Interrupt, Configuring .......................... 35
Acquisition Requirements ........................................... 36
ADCON0 Register....................................................... 31
ADCON1 Register....................................................... 31
ADCON2 Register....................................................... 31
ADRESH Register................................................. 31, 34
ADRESL Register ....................................................... 31
Analog Port Pins, Configuring..................................... 38
Associated Registers .................................................. 40
Configuring the Module............................................... 35
Conversion Clock (TAD) .............................................. 37
Conversion Requirements .......................................... 46
Conversion Status (GO/DONE Bit)............................. 34
Conversions................................................................ 39
Converter Characteristics ........................................... 45
Discharge.................................................................... 39
Operation in Power-Managed Modes ......................... 38
Selecting and Configuring Acquisition Time ............... 37
Special Event Trigger (ECCP2) .................................. 40
Transfer Function........................................................ 35
Use of the ECCP2 Trigger .......................................... 40
Absolute Maximum Ratings ................................................ 43
ADCON0 Register............................................................... 31
GO/DONE Bit.............................................................. 34
ADCON1 Register............................................................... 31
ADCON2 Register............................................................... 31
ADRESH Register............................................................... 31
ADRESL Register ......................................................... 31, 34
Analog-to-Digital Converter. See A/D.
I
Internet Address ................................................................. 55
Interrupt Sources
A/D Conversion Complete.......................................... 35
L
LCD Driver
Features ....................................................................... 3
M
Microchip Internet Web Site................................................ 55
Microcontroller
Special Features........................................................... 3
Migration from Baseline to Enhanced Devices................... 50
Migration from High-End to Enhanced Devices.................. 51
Migration from Mid-Range to Enhanced Devices ............... 51
O
Oscillator Structure
Features ....................................................................... 3
P
Packaging
Information.................................................................. 47
Peripheral Highlights............................................................. 3
Pin Diagrams
64-Pin TQFP................................................................. 4
80-Pin TQFP................................................................. 5
Pin Functions
B
Block Diagrams
A/D.............................................................................. 34
Analog Input Model..................................................... 35
PIC18F6X93 ............................................................... 11
PIC18F8X93 ............................................................... 12
AVDD........................................................................... 20
AVDD........................................................................... 30
AVSS ........................................................................... 20
AVSS ........................................................................... 30
COM0 ................................................................... 18, 26
LCDBIAS1 ............................................................ 18, 26
LCDBIAS2 ............................................................ 18, 26
LCDBIAS3 ............................................................ 18, 26
MCLR/VPP/RG5.................................................... 13, 21
OSC1/CLKI/RA7................................................... 13, 21
OSC2/CLKO/RA6................................................. 13, 21
RA0/AN0............................................................... 14, 22
RA1/AN1............................................................... 14, 22
RA2/AN2/VREF-/SEG16........................................ 14, 22
RA3/AN3/VREF+/SEG17....................................... 14, 22
RA4/T0CKI/SEG14............................................... 14, 22
RA5/AN4/HLVDIN/SEG15.................................... 14, 22
RB0/INT0.............................................................. 15, 23
RB1/INT1/SEG8 ................................................... 15, 23
RB2/INT2/SEG9 ................................................... 15, 23
RB3/INT3/SEG10 ................................................. 15, 23
RB4/KBI0/SEG11 ................................................. 15, 23
RB5/KBI1.............................................................. 15, 23
RB6/KBI2/PGC..................................................... 15, 23
RB7/KBI3/PGD..................................................... 15, 23
RC0/T1OSO/T13CKI............................................ 16, 24
RC1/T1OSI/CCP2 ................................................ 16, 24
RC2/CCP1/SEG13 ............................................... 16, 24
C
Compare (ECCP2 Module)
Special Event Trigger.................................................. 40
Conversion Considerations................................................. 50
Customer Change Notification Service ............................... 55
Customer Notification Service............................................. 55
Customer Support............................................................... 55
D
Device Differences.............................................................. 49
Device ID Registers ............................................................ 41
Device Overview ................................................................... 9
Details of Individual Devices......................................... 9
Features (table)........................................................... 10
Special Features........................................................... 9
Documentation
Most Current Versions .................................................. 7
Related Data Sheet....................................................... 9
E
Electrical Characteristics..................................................... 43
A/D Converter ............................................................. 45
Absolute Maximum Ratings ........................................ 43
Low-Power Voltage-Frequency Graph........................ 44
© 2009 Microchip Technology Inc.
DS39896B-page 53
PIC18F6393/6493/8393/8493
RC3/SCK/SCL ...................................................... 16, 24
RC4/SDI/SDA ....................................................... 16, 24
RC5/SDO/SEG12 ................................................. 16, 24
RC6/TX1/CK1 ....................................................... 16, 24
RC7/RX1/DT1....................................................... 16, 24
RD0/SEG0 ............................................................ 17, 25
RD0/SEG1 ..................................................................17
RD1/SEG1 ..................................................................25
RD2/SEG2 ............................................................ 17, 25
RD3/SEG3 ............................................................ 17, 25
RD4/SEG4 ............................................................ 17, 25
RD5/SEG5 ............................................................ 17, 25
RD6/SEG6 ............................................................ 17, 25
RD7/SEG7 ............................................................ 17, 25
RE4/COM1............................................................ 18, 26
RE5/COM2............................................................ 18, 26
RE6/COM3............................................................ 18, 26
RE7/CCP2/SEG31................................................ 18, 26
RF0/AN5/SEG18................................................... 19, 27
RF1/AN6/C2OUT/SEG19 ..................................... 19, 27
RF2/AN7/C1OUT/SEG20 ..................................... 19, 27
RF3/AN8/SEG21................................................... 19, 27
RF4/AN9/SEG22................................................... 19, 27
RF5/AN10/CVREF/SEG23..................................... 19, 27
RF6/AN11/SEG24................................................. 19, 27
RF7/SS/SEG25..................................................... 19, 27
RG0/SEG30 .......................................................... 20, 28
RG1/TX2/CK2/SEG29 .......................................... 20, 28
RG2/RX2/DT2/SEG28 .......................................... 20, 28
RG3/SEG27 .......................................................... 20, 28
RG4/SEG26 .......................................................... 20, 28
RG5....................................................................... 20, 28
RH0/SEG47 ................................................................29
RH1/SEG46 ................................................................29
RH2/SEG45 ................................................................29
RH3/SEG44 ................................................................29
RH4/SEG40 ................................................................29
RH5/SEG41 ................................................................29
RH6/SEG42 ................................................................29
RH7/SEG43 ................................................................29
RJ0/SEG32.................................................................30
RJ1/SEG33.................................................................30
RJ2/SEG34.................................................................30
RJ3/SEG35.................................................................30
RJ4/SEG39.................................................................30
RJ5/SEG38.................................................................30
RJ6/SEG37.................................................................30
RJ7/SEG36.................................................................30
VDD..............................................................................20
VDD..............................................................................30
VSS..............................................................................20
VSS..............................................................................30
Pinout I/O Descriptions
DEVID1 (Device ID 1)................................................. 42
DEVID2 (Device ID 2)................................................. 42
Revision History.................................................................. 49
S
Special Features of the CPU .............................................. 41
Device ID Registers.................................................... 41
T
Timing Diagrams
A/D Conversion........................................................... 46
W
WWW Address ................................................................... 55
WWW, On-Line Support ....................................................... 7
PIC18F6X93 ...............................................................13
PIC18F8X93 ...............................................................21
Power-Managed Modes
and A/D Operation ......................................................38
Features........................................................................3
Product Identification System..............................................57
R
Reader Response ...............................................................56
Registers
ADCON0 (A/D Control 0)............................................31
ADCON1 (A/D Control 1)............................................32
ADCON2 (A/D Control 2)............................................33
DS39896B-page 54
© 2009 Microchip Technology Inc.
PIC18F6393/6493/8393/8493
THE MICROCHIP WEB SITE
CUSTOMER SUPPORT
Microchip provides online support via our WWW site at
www.microchip.com. This web site is used as a means
to make files and information easily available to
customers. Accessible by using your favorite Internet
browser, the web site contains the following
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Users of Microchip products can receive assistance
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• Distributor or Representative
• Local Sales Office
• Field Application Engineer (FAE)
• Technical Support
• Product Support – Data sheets and errata,
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• Development Systems Information Line
Customers
should
contact
their
distributor,
representative or field application engineer (FAE) for
support. Local sales offices are also available to help
customers. A listing of sales offices and locations is
included in the back of this document.
• General Technical Support – Frequently Asked
Questions (FAQ), technical support requests,
online discussion groups, Microchip consultant
program member listing
Technical support is available through the web site
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• Business of Microchip – Product selector and
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CUSTOMER CHANGE NOTIFICATION
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Microchip’s customer notification service helps keep
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To register, access the Microchip web site at
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Notification and follow the registration instructions.
© 2009 Microchip Technology Inc.
DS39896B-page 55
PIC18F6393/6493/8393/8493
READER RESPONSE
It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip prod-
uct. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation
can better serve you, please FAX your comments to the Technical Publications Manager at (480) 792-4150.
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PIC18F6393/6493/8393/8493
DS39896B
Literature Number:
Device:
Questions:
1. What are the best features of this document?
2. How does this document meet your hardware and software development needs?
3. Do you find the organization of this document easy to follow? If not, why?
4. What additions to the document do you think would enhance the structure and subject?
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6. Is there any incorrect or misleading information (what and where)?
7. How would you improve this document?
DS39896B-page 56
© 2009 Microchip Technology Inc.
PIC18F6393/6493/8393/8493
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
PART NO.
Device
X
/XX
XXX
Examples:
Temperature
Range
Package
Pattern
a)
PIC18LF6393-I/PT 301 = Industrial temp.,
TQFP package, Extended VDD limits,
QTP pattern #301.
b)
c)
PIC18LF6393-I/PT = Industrial temp., TQFP
package, Extended VDD limits.
Device(1), (2)
PIC18F6393, PIC18F6493, PIC18F8393, PIC18F8493 –
VDD range: 4.2V to 5.5V
PIC18LF6393, PIC18LF6493, PIC18LF8393, PIC18LF8493 –
VDD range: 2.0V to 5.5V
PIC18F6393-E/PT = Extended temp., TQFP
package, normal VDD limits.
Temperature Range
I
E
=
=
-40°C to +85°C (Industrial)
-40°C to +125°C (Extended)
Package
Pattern
PT
=
TQFP (Thin Quad Flatpack)
QTP, SQTP, Code or Special Requirements
(blank otherwise)
Note 1:
2:
F
LF
T
=
=
=
Standard Voltage Range
Wide Voltage Range
in tape and reel TQFP
packages only.
© 2009 Microchip Technology Inc.
DS39896B-page 57
WORLDWIDE SALES AND SERVICE
AMERICAS
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EUROPE
Corporate Office
Asia Pacific Office
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Tel: 852-2401-1200
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Santa Clara
China - Xian
Tel: 86-29-8833-7252
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Thailand - Bangkok
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Fax: 66-2-694-1350
Santa Clara, CA
Tel: 408-961-6444
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China - Zhuhai
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Fax: 86-756-3210049
Toronto
Mississauga, Ontario,
Canada
Tel: 905-673-0699
Fax: 905-673-6509
03/26/09
DS39896B-page 58
© 2009 Microchip Technology Inc.
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