PIC24FJ128GA008-I/PT

PIC24FJ128GA010

PIC24FJ128GA010 Family Rev. A4 Silicon Errata

The PIC24FJ128GA010 family Rev. A4 parts you have

received conform functionally to the Device Data Sheet

(DS39747C), except for the anomalies described below.

Any Data Sheet Clarification issues related to the

PIC24FJ128GA010 Family will be reported in a separate

Data Sheet errata. Please check the Microchip web site

for any existing issues.

2. Module: JTAG

The current JTAG programming implementation is

not compatible with third party programmers using

SVF (Serial Vector Format) description language.

JTAG boundary scan is supported by third party

JTAG solutions and is not affected.

Work around

The following silicon errata apply only

to PIC24FJ128GA010 devices with these Device/

Revision IDs:

Program

devices

with

In-Circuit

Serial

Programming™. JTAG programming can be

accomplished using custom JTAG software. The

current implementation may not be supported in

future PIC24F revisions. JTAG boundary scan is

supported.

Part Number

Device ID

Revision ID

PIC24FJ128GA010

PIC24FJ96GA010

PIC24FJ64GA010

PIC24FJ128GA008

PIC24FJ96GA008

PIC24FJ64GA008

PIC24FJ128GA006

PIC24FJ96GA006

PIC24FJ64GA006

040Dh

040Ch

040Bh

040Ah

0409h

0408h

0407h

0406h

0405h

04h

Date Codes that pertain to this issue:

All engineering and production devices.

3

Module: PMP

In Master mode (MODE<1:0> = 11 or 10), back-

to-back operations may cause the PMRD signal to

not be generated. This limitation occurs when the

peripheral is configured for zero wait states

(WAITM<3:0> = 0000).

The Device IDs (DEVID and DEVREV) are located at

the last two implemented addresses in program

memory. They are shown in hexadecimal in the

format “DEVID DEVREV”.

Work around

The PMRD signal will be generated correctly if a

minimum of one instruction cycle delay is inserted

between the back-to-back operations. A NOP

instruction, or any other instruction, is adequate.

Selecting a delay other than zero will also permit

the PMRD signal to be generated.

1. Module: Core

With Doze mode enabled, DOZEN (CLKDIV<11>)

set, and the CPU Peripheral Clock Ratio Select

bits (CLKDIV<14:12>) configured to any value

except 0b000, writes to SFR locations can not be

performed.

Date Codes that pertain to this issue:

All engineering and production devices.

Work around

4. Module: Interrupts

Disable Doze mode, or select 1:1 CPU peripheral

clock ratio before modifying stated SFR locations,

or avoid writing stated locations while Doze mode

is enabled and CPU peripheral clock ratio other

than 1:1 is selected. Configure the device prior to

entering Doze mode and use the mode only to

monitor applications activity.

The device may not exit Doze mode if certain trap

conditions occur. Address error, stack error and

math error traps are affected. Oscillator failure and

all interrupt sources are not affected and can

cause the device to correctly exit Doze mode.

Work around

Date Codes that pertain to this issue:

None.

All engineering and production devices.

Date Codes that pertain to this issue:

All engineering and production devices.

DS80330A-page 1

PIC24FJ128GA010

5. Module: Output Compare

8. Module: UART

The output compare module may output a single

glitch for one TCY after the module is enabled

(OCM<2:0> = 000). This issue occurs when the

output state of the associated Data Latch register

(LATx) is in the opposite state of the Output Com-

pare mode when the peripheral is enabled. It can

also occur when switching between two Output

Compare modes with opposite output states.

UART1 and UART2 hardware flow control options

are not available for the 64-pin variants of the

PIC24FJ128GA010 product family. As a result, the

UxCTS and UxRTS pins not available and the

UEN<1:0> control bits are read as ‘0’ (unimple-

mented). UART2 hardware flow control is not

available for the 80-pin PIC24FJ128GA010

variants. Therefore associated pins and bits are

not available for these devices.

Work around

If the output glitch must be avoided, verify that the

associated data latch value of the OCx pin matches

the initial state of the desired Output Compare

mode. For example, if Output Compare 5 is config-

ured for mode, OCM<2:0> = 001, ensure that the

LATD<4> bit is clear prior to writing the OCM bits.

The port latch output value will match the initial out-

put state of the OC5 pin and avoid the glitch when

the peripheral is enabled.

None.

Date Codes that pertain to this issue:

All engineering and production devices.

9. Module: UART

When the UART is in High-Speed mode

(BRGH = 1), the auto-baud sequence can calculate

the baud rate as if it were in Low-Speed mode.

Date Codes that pertain to this issue:

All engineering and production devices.

Work around

The calculated baud rate can be modified by the

following equation:

6. Module: UART

The timing for transmitting a Sync Break has

changed for this revision of silicon. The Sync

Break is transmitted as soon as the UTXBRK bit is

set. A dummy write to UxTXREG is still required

and must be performed before the Sync Break has

finished transmitting. Otherwise, the UxTX may be

held in the active state until the write has occurred.

New BRG Value = (Auto-Baud BRG + 1) * 4 – 1

The user should verify baud rate error does not

exceed application limits.

Date Codes that pertain to this issue:

All engineering and production devices.

Work around

10. Module: UART

Set the UTXBRK bit when a Sync Break is

required and perform a dummy UxTXREG imme-

diately following. This sequence will avoid holding

the UxTX pin in the active state.

With the auto-baud feature selected, the Sync

Break character (0x55) may be loaded into the

FIFO as data.

Work around

Date Codes that pertain to this issue:

To prevent the Sync Break character from being

loaded into the FIFO, load the UxBRG register with

either 0x0000 or 0xFFFF prior to enabling the

auto-baud feature (ABAUD = 1).

All engineering and production devices.

7. Module: UART

When the UART is in High-Speed mode, BRGH

(UxMODE<3>) is set, some optimal UxBRG

values can cause reception to fail.

Date Codes that pertain to this issue:

All engineering and production devices.

Work around

Test UxBRG values in the application to find a

UxBRG value that works consistently for more

high-speed applications. User should verify that

the UxBRG baud rate error does not exceed the

application limits.

Date Codes that pertain to this issue:

All engineering and production devices.

DS80330A-page 2

PIC24FJ128GA010

11. Module: A/D

14. Module: SPI

Gain error may be as high as 5 LSbs for external

references (VREF+ and VREF-) and 6 LSbs for

internal reference (AVDD and AVSS).

Master mode receptions using the SPI1 and SPI2

modules may not function correctly for bit rates

above 8 Mbps if the master has the SMP bit

(SPIxCON1<9>) cleared (master samples data at

the middle of the serial clock period).

Work around

Determine gain error from a known reference

voltage and compensate the A/D result in

software.

In this case, the data transmitted by the slave is

received, shifted right by one bit, by the master.

For example, if the data transmitted by the slave

was 0xAAAA, the data received by the master

would be 0x5555 (0xAAAA shifted right by one bit).

Date Codes that pertain to this issue:

All engineering and production devices.

Work around

12. Module: A/D

Users may set up the SPI module so that the bit

rate is 8 Mbps or lower.

With the External Interrupt 0 (INT0) selected to start

an A/D conversion (SSRC<2:0> = 001), the device

may not wake-up from Sleep or Idle mode if more

than one conversion is selected per interrupt

(SMPI<3:0> <> 0000). Interrupts are generated

correctly if the device is not in a Sleep or Idle mode.

Alternatively, the bit rate can be configured higher

than 8 Mbps, but the SMP bit (SPIxCON1<9>) of

the SPI master must be set (master samples data

at the end of the serial clock period).

Date Codes that pertain to this issue:

Work around

All engineering and production devices.

Configure the A/D to generate an interrupt after

every conversion (SMPI<3:0> = 0000). Use

another wake-up source, such as the WDT or

another interrupt source, to exit the Sleep or Idle

mode. Alternatively, perform A/D conversions in

Run mode.

15. Module: SPI

A frame synchronization pulse may not be output

in SPI Master mode if the pulse is selected to

coincide with the first bit clock (SPIFE = 1). SCKx

and SDOx waveforms are not affected.

Date Codes that pertain to this issue:

Work around

All engineering and production devices.

Select the frame sychronization pulses to proceed

the first bit clock (SPIFE = 0). The frame pulses

will output correctly as described in the product

data sheet.

13. Module: SPI

The Enhanced SPI modes, selected by setting the

Enhanced

Buffer

Enable

bit,

SPIBEN

Date Codes that pertain to this issue:

(SPIxCON2<0>), are not available.

All engineering and production devices.

Work around

Use Standard SPI mode by clearing the SPI

Enhanced Buffer Enable bit, SPIBEN.

Date Codes that pertain to this issue:

All engineering and production devices.

DS80330A-page 3

PIC24FJ128GA010

16. Module: SPI

19. Module: Core

In SPI Slave mode (MSTEN = 0), with the slave

select option enabled (SSEN = 1), the peripheral

may accept transfers regardless of the SSx pin

state. The received data in SSPxBUF will be

accurate but not intended for the device.

If a clock failure occurs when the device is in Idle

mode, the oscillator failure trap does not vector to

the Trap Service Routine. Instead, the device will

simply wake-up from Idle mode and continue code

execution if the Fail-Safe Clock Monitor (FSCM) is

enabled.

Work around

If the Slave select option is required (e.g., device

one of multiple SPI slave nodes on an SPI

network), two potential work arounds exist:

Whenever the device wakes up from Idle (assum-

ing the FSCM is enabled), the user software

should check the status of the OSCFAIL bit

(INTCON1<1>) to determine whether a clock fail-

ure occurred and then perform an appropriate

clock switch operation.

1. Configure the port associated with SSx to an

input and periodically read the PORT register. If

the pin is read ‘0’, disable the SPI peripheral

(SPIEN = 0). Enable the peripheral (SPIEN = 1)

if the pin is read as a logic ‘1’.

Date Codes that pertain to this issue:

2. Read the pin associated with SSx after a trans-

fer is complete, indicated by the SPIxF bit

being set. If the port pin is read as a digital ‘1’,

read SSPxBUF and discard the contents.

All engineering and production devices.

20. Module: Core

On a Brown-out Reset, both the BOR and POR

bits may be set. This may cause the Brown-out

Reset condition to be indistinguishable from the

Power-on Reset.

Date Codes that pertain to this issue:

All engineering and production devices.

17. Module: Oscillator

Work around

The Two-Speed Start-up feature may not be

available on exit from Sleep mode with the IESO

(Internal/External Switchover mode) enabled.

Upon wake-up, the device will wait for the clock

source used prior to entering Sleep mode to

become ready.

None.

Date Codes that pertain to this issue:

All engineering and production devices.

21. Module: Ports

Work around

RC15 may output a digital ‘0’ after a Reset until the

Configuration Word settings are processed. The

duration of time for this effect is TRST which is

nominally 20 µs.

None.

Date Codes that pertain to this issue:

All engineering and production devices.

After the Configuration Word is processed, RC15

is put into its reset state as a digital input.

18. Module: Core

Work around

The CLKDIV register Reset value is incorrect. The

register will reset with unimplemented bits equal to

‘1’ for all Resets.

Connect components not adversely affected by a

digital 0 signal to RC15.

Date Codes that pertain to this issue:

Work around

All engineering and production devices.

Mask out unimplemented bits to maintain software

compatibility with future device revisions.

Date Codes that pertain to this issue:

All engineering and production devices.

DS80330A-page 4

PIC24FJ128GA010

22. Module: I²C™

25. Module: UART

During I²C Slave mode transactions, the Data/

Address bit, D/A, may not update during the data

frame. This affects both 7 and 10-Bit Addressing

modes.

The auto-baud may miscalculate for certain baud

rates and clock speed combinations, resulting in a

BRG value that is 1 greater or less than the

expected value. When UxBRG is less than 50, this

can result in transmission and reception failures

due to introducing error greater than 1%.

I²C slave receptions are not affected by this issue.

Work around

Use the Read/Write bit, R/W, and the Transmit

Buffer Full Status Bit, TBF, to determine whether

address or data information is being received.

Test auto-baud calculations at various clock speed

and baud rate combinations that would be used in

applications. If an inaccurate UxBRG value is

generated, manually correct the baud rate in user

code.

For more information, see Figure 24-30 and

Figure 24-31 in “Section 24. Inter-Integrated

Circuit™ (I²C™)” (DS39702A).

Date Codes that pertain to this issue:

All engineering and production devices.

26. Module: UART

23. Module: I²C

When the UART is in 4x mode (BRGH = 1) and

using two Stop bits (STSEL = 1), it may sample the

first Stop bit instead of the second one.

When the I²C module is operating in Slave mode,

after the ACKSTAT bit is set when receiving a

NACK from the master, it may be cleared by the

reception of a Start or Stop bit.

This issue does not affect the other UART

configurations.

Work around

Store the value of the ACKSTAT bit immediately

after receiving a NACK from the master.

Use the 16x baud rate option (BRGH = 0) and

adjust the baud rate accordingly.

Date Codes that pertain to this issue:

All engineering and production devices.

24. Module: UART

27. Module: SPI

When an auto-baud is detected, the receive inter-

rupt may occur twice. The first interrupt occurs at

the beginning of the Start bit and the second after

reception of the Sync field character.

In SPI Master mode, the Disable SCK Pin bit,

DISSCK, may not disable the SPI clock. As a

result, the PIC^®microcontroller must provide the

SPI clock in Master mode.

Work around

If a receive interrupt occurs, check the URXDA bit

(UxSTA<0>) to ensure that valid data is available.

On the first interrupt, no data will be present. The

second interrupt will have the Sync field character

(55h) in the receive FIFO.

None.

Date Codes that pertain to this issue:

All engineering and production devices.

Date Codes that pertain to this issue:

All engineering and production devices.

DS80330A-page 5

PIC24FJ128GA010

28. Module: Output Compare

30. Module: RTCC

In PWM mode, the output compare module may

miss a compare event when the current duty cycle

register (OCxRS) value is 0x0000 (0% duty cycle)

and the OCxRS register is updated with a value of

0x0001. The compare event is only missed the first

time a value of 0x0001 is written to OCxRS and the

PWM output remains low for one PWM period.

Subsequent PWM high and low times occur as

expected.

When performing writes to the ALCFGRPT regis-

ter, some bits may become corrupted. The error

occurs because of desynchronization between the

CPU clock domain and the RTCC clock domain.

The error causes data from the instruction follow-

ing the ALCFGRPT instruction to overwrite the

data in ALCFGRPT.

Work around

Always follow writes to the ALCFGRPT register

with an additional write of the same data to a

dummy location. These writes can be performed to

RAM locations, W registers or unimplemented

SFR space.

Work around

If the current OCxRS register value is 0x0000,

avoid writing a value of 0x0001 to OCxRS.

Instead, write a value of 0x0002. In this case, how-

ever, the duty cycle will be slightly different from

the desired value.

The optimal way to perform the work around:

1. Read ALCFGRPT into a RAM location.

Date Codes that pertain to this issue:

2. Modify the ALCFGRPT data, as required, in

RAM.

All engineering and production devices.

3. Move the RAM value into ALCFGRPT and a

dummy location in back-to-back instructions.

29. Module: RTCC

The RTCC alarm repeat will generate an incorrect

number of pin toggles. If the repeat count (x) is

even, it will toggle the alarm pin ‘x’ times. If the

repeat count is odd, one less than x toggles will be

observed (x – 1).

Date Codes that pertain to this issue:

All engineering and production devices.

31. Module: CRC

If a CRC FIFO overflow occurs, the VWORD indi-

cator will reset to ‘1’ instead of ‘0’. Further writes to

the FIFO will cause the VWORD indicator to reset

to ‘0’ after seven writes are performed.

Work around

None at this time.

Date Codes that pertain to this issue:

Work around

All engineering and production devices.

Poll the CRCFUL bit (CRCCON<7>) to ensure that

no writes are performed on the FIFO when it is full.

Date Codes that pertain to this issue:

All engineering and production devices.

DS80330A-page 6

PIC24FJ128GA010

32. Module: I/O Pins

The I/O pin output, VOL, meets the specifications in

Table 1 below:

TABLE 1:

DC CHARACTERISTICS: I/O PIN OUTPUT SPECIFICATIONS

Standard Operating Conditions: 2.0V to 3.6V (unless otherwise stated)

DC CHARACTERISTICS

Operating temperature

-40°C ≤ TA ≤ +85°C for Industrial

Param

No.

Sym

Characteristic

Min

Typ⁽¹⁾Max

Units

Conditions

VOL

Output Low Voltage

DO10

All I/O Pins

—

.55

.4

V

IOL = 8.5 mA, VDD = 3.6V

IOL = 7.8 mA, VDD = 3.6V

IOL = 6.0 mA, VDD = 2.0V

IOL = 5.0 mA, VDD = 2.0V

.55

.4

Note 1: Data in “Typ” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only

and are not tested.

Work around

None.

DS80330A-page 7

PIC24FJ128GA010

REVISION HISTORY

Rev A Document (9/2007)

Initial release of this document. Includes silicon issues

1 (Core), 2 (JTAG), 3 (PMP), 4 (Interrupts), 5 (Output

Compare), 6-10 (UART), 11-12 (A/D), 13-16 (SPI),

17 (Oscillator), 18-20 (Core), 21 (Ports), 22-23 (I²C™),

24-26 (UART), 27 (SPI), 28 (Output Compare), 29-30

(RTCC), 31 (CRC) and 32 (I/O Pins).

DS80330A-page 8

Note the following details of the code protection feature on Microchip devices:

•

Microchip products meet the specification contained in their particular Microchip Data Sheet.

•

Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the

intended manner and under normal conditions.

•

There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our

knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data

Sheets. Most likely, the person doing so is engaged in theft of intellectual property.

•

Microchip is willing to work with the customer who is concerned about the integrity of their code.

Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not

mean that we are guaranteeing the product as “unbreakable.”

Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our

products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts

allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.

Information contained in this publication regarding device

applications and the like is provided only for your convenience

and may be superseded by updates. It is your responsibility to

ensure that your application meets with your specifications.

MICROCHIP MAKES NO REPRESENTATIONS OR

WARRANTIES OF ANY KIND WHETHER EXPRESS OR

IMPLIED, WRITTEN OR ORAL, STATUTORY OR

OTHERWISE, RELATED TO THE INFORMATION,

INCLUDING BUT NOT LIMITED TO ITS CONDITION,

QUALITY, PERFORMANCE, MERCHANTABILITY OR

FITNESS FOR PURPOSE. Microchip disclaims all liability

arising from this information and its use. Use of Microchip

devices in life support and/or safety applications is entirely at

the buyer’s risk, and the buyer agrees to defend, indemnify and

hold harmless Microchip from any and all damages, claims,

suits, or expenses resulting from such use. No licenses are

conveyed, implicitly or otherwise, under any Microchip

intellectual property rights.

Trademarks

The Microchip name and logo, the Microchip logo, Accuron,

dsPIC, KEELOQ, KEELOQ logo, microID, MPLAB, PIC,

PICmicro, PICSTART, PRO MATE, rfPIC and SmartShunt are

registered trademarks of Microchip Technology Incorporated

in the U.S.A. and other countries.

AmpLab, FilterLab, Linear Active Thermistor, Migratable

Memory, MXDEV, MXLAB, SEEVAL, SmartSensor and The

Embedded Control Solutions Company are registered

trademarks of Microchip Technology Incorporated in the

U.S.A.

Analog-for-the-Digital Age, Application Maestro, CodeGuard,

dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN,

ECONOMONITOR, FanSense, FlexROM, fuzzyLAB,

In-Circuit Serial Programming, ICSP, ICEPIC, Mindi, MiWi,

MPASM, MPLAB Certified logo, MPLIB, MPLINK, PICkit,

PICDEM, PICDEM.net, PICLAB, PICtail, PowerCal,

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Mode, Smart Serial, SmartTel, Total Endurance, UNI/O,

WiperLock and ZENA are trademarks of Microchip

Technology Incorporated in the U.S.A. and other countries.

SQTP is a service mark of Microchip Technology Incorporated

in the U.S.A.

All other trademarks mentioned herein are property of their

respective companies.

Printed on recycled paper.

Microchip received ISO/TS-16949:2002 certification for its worldwide

headquarters, design and wafer fabrication facilities in Chandler and

Tempe, Arizona; Gresham, Oregon and design centers in California

and India. The Company’s quality system processes and procedures

are for its PIC^®MCUs and dsPIC^®DSCs, KEELOQ^®code hopping

devices, Serial EEPROMs, microperipherals, nonvolatile memory and

analog products. In addition, Microchip’s quality system for the design

and manufacture of development systems is ISO 9001:2000 certified.

DS80330A-page 9

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09/10/07

DS80330A-page 10


型号：	PIC24FJ128GA008-I/PT
厂家：	MICROCHIP
描述：	16-BIT, FLASH, 32 MHz, MICROCONTROLLER, PQFP80, 12 X 12 MM, 1 MM HEIGHT, PLASTIC, TQFP-80
文件：	总10页 (文件大小：344K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

PIC24FJ128GA008-I/PT [MICROCHIP]

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