PIC24FJ128GA308 [MICROCHIP]
64/80/100-Pin, General Purpose, 16-Bit Flash Microcontrollers with LCD Controller and nanoWatt XLP Technology; 八十〇分之六十四/ 100-引脚，通用， 16位闪存微控制器与LCD控制器，并采用nanoWatt XLP技术
| 型号： | PIC24FJ128GA308 |
| 厂家： | 
MICROCHIP |
| 描述： | 64/80/100-Pin, General Purpose, 16-Bit Flash Microcontrollers with LCD Controller and nanoWatt XLP Technology |
| 文件： | 总406页 (文件大小：3268K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PIC24FJ128GA310 FAMILY
64/80/100-Pin, General Purpose, 16-Bit Flash Microcontrollers
with LCD Controller and nanoWatt XLP Technology
Extreme Low-Power Features:
Peripheral Features (continued):
• Multiple Power Management Options for Extreme
Power Reduction:
• Seven Input Capture modules, each with a
Dedicated 16-Bit Timer
- VBAT allows the device to transition to a back-up
battery for the lowest power consumption with
RTCC
- Deep Sleep allows near total power-down, with
the ability to wake-up on external triggers
- Sleep and Idle modes selectively shut down
peripherals and/or core for substantial power
reduction and fast wake-up
• Seven Output Compare/PWM modules, each with a
Dedicated 16-Bit Timer
• Enhanced Parallel Master/Slave Port (EPMP/EPSP)
• Hardware Real-Time Clock/Calendar (RTCC):
- Runs in Deep Sleep and VBAT modes
• Two 3-Wire/4-Wire SPI modules (support 4 Frame
modes) with 8-Level FIFO Buffer
2
• Two I C™ modules Support Multi-Master/Slave
- Doze mode allows CPU to run at a lower clock
speed than peripherals
mode and 7-Bit/10-Bit Addressing
• Four UART modules:
• Alternate Clock modes Allow On-the-Fly Switching to
a Lower Clock Speed for Selective Power Reduction
• Extreme Low-Power Current Consumption for
Deep Sleep:
- WDT: 270 nA @ 3.3V typical
- RTCC: 400 nA @ 32 kHz, 3.3V typical
- Deep Sleep current, 40 na, 3.3V typical
- Support RS-485, RS-232 and LIN/J2602
- On-chip hardware encoder/decoder for IrDA®
- Auto-wake-up on Auto-Baud Detect
- 4-level deep FIFO buffer
• Programmable 32-bit Cyclic Redundancy Check
(CRC) Generator
• Digital Signal Modulator Providers On-Chip FSK and
PSK Modulation for a Digital Signal Stream
• Configurable Open-Drain Outputs on Digital I/O Pins
• High-Current Sink/Source (18 mA/18 mA) on All I/O Pins
Peripheral Features:
• LCD Display Controller:
- Up to 60 segments by 8 commons
- Internal charge pump and low-power, internal
resistor biasing
Analog Features:
• 10/12-Bit, 24-Channel Analog-to-Digital (A/D) Converter:
- Conversion rate of 500 ksps (10-bit), 200 ksps (12-bit)
- Conversion available during Sleep and Idle
• Three Rail-to-Rail Enhanced Analog Comparators
with Programmable Input/Output Configuration
• On-Chip Programmable Voltage Reference
• Charge Time Measurement Unit (CTMU):
- Operation in Sleep mode
• Up to Five External Interrupt Sources
• Peripheral Pin Select (PPS): Allows Independent I/O
Mapping of Many Peripherals
• Five 16-Bit Timers/Counters with Prescaler:
- Can be paired as 32-bit timers/counters
• Six-Channel DMA supports All Peripheral modules
- Minimizes CPU overhead and increases data
throughput
- Used for capacitive touch sensing, up to 24 channels
- Time measurement down to 1 ns resolution
- CTMU temperature sensing
Memory
Remappable Peripherals
Device
PIC24FJ128GA310
PIC24FJ128GA308
PIC24FJ128GA306
PIC24FJ64GA310
PIC24FJ64GA308
PIC24FJ64GA306
100
80
128K
8K
8K
8K
8K
8K
8K
5
5
5
5
5
5
7
7
7
7
7
7
7
7
7
7
7
7
4
4
4
4
4
4
2
2
2
2
2
2
2
2
2
2
2
2
24
16
16
24
16
16
3
3
3
3
3
3
24
16
16
24
16
16
Y
Y
Y
Y
Y
Y
480
368
240
480
368
240
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
128K
128K
64K
64
100
80
64K
64
64K
2010-2011 Microchip Technology Inc.
DS39996F-page 1
PIC24FJ128GA310 FAMILY
High-Performance CPU:
Special Microcontroller Features:
• Modified Harvard Architecture
• Up to 16 MIPS Operation @ 32 MHz
• 8 MHz Internal Oscillator:
- 4x PLL option
- Multiple clock divide options
• Operating Voltage Range of 2.0V to 3.6V
• Two On-Chip Voltage Regulators (1.8V and 1.2V) for
Regular and Extreme Low-Power Operation
• 20,000 Erase/Write Cycle Endurance Flash Program
Memory, typical
• Flash Data Retention: 20 Years Minimum
• Self-Programmable under Software Control
• Programmable Reference Clock Output
• In-Circuit Serial Programming™ (ICSP™) and
In-Circuit Emulation (ICE) via 2 Pins
- Fast start-up
• 17-Bit x 17-Bit Single-Cycle Hardware
Fractional/Integer Multiplier
• 32-Bit by 16-Bit Hardware Divider
• 16 x 16-Bit Working Register Array
• C Compiler Optimized Instruction Set Architecture
• Two Address Generation Units for Separate Read
and Write Addressing of Data Memory
• JTAG Boundary Scan Support
• Fail-Safe Clock Monitor Operation:
- Detects clock failure and switches to on-chip,
low-power RC oscillator
• Power-on Reset (POR), Power-up Timer (PWRT)
and Oscillator Start-up Timer (OST)
• Brown-out Reset (BOR) with Operation below VBOR
• Low-Voltage Detect (LVD)
• Flexible Watchdog Timer (WDT) with its own
RC Oscillator for Reliable Operation
• Standard and Ultra Low-Power Watchdog Timers
(WDT) for Reliable Operation in Standard and Deep
Sleep modes
DS39996F-page 2
2010-2011 Microchip Technology Inc.
PIC24FJ128GA310 FAMILY
Pin Diagrams
64-Pin TQFP, QFN
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
SOSCO/RPI37/SCKLI/RC14
1
PMD5/CTED4/LCDBIAS2/CN63/RE5
SOSCI/RC13
PMD6/LCDBIAS1/CN64/RE6
PMD7/LCDBIAS0/CN65/RE7
2
RP11/SEG17/CN49/RD0
3
RP12/C3INC/SEG16/PMA14/CS1/CN56/RD11
RP3/SEG15/PMA15/C3IND/CS2/CN55/RD10
RP4/SEG14/PMACK2/CN54/RD9
RP2/SEG13/RTCC/CN53/RD8
C1IND/RP21/SEG0/PMA5/CN8/RG6
4
V
LCAP1/C1INC/RP26/PMA4/CN9/RG7
LCAP2/C2IND/RP19/PMA3/CN10/RG8
MCLR
5
V
6
7
VSS
C2INC/RP27/SEG1/PMA2/CN11/RG9
8
PIC24FJXXXGA306
OSCO/CLKO/CN22/RC15
OSCI/CLKI/CN23/RC12
VSS
9
VDD
10
11
12
13
14
15
16
VDD
PGEC3/AN5/C1INA/RP18/SEG2/CN7/RB5
PGED3/AN4/C1INB/RP28/SEG3/CN6/RB4
AN3/C2INA/SEG4/CN5/RB3
SEG28/CN72/SCL1/RG2
SEG47/CN73/SDA1/RG3
INT0/CN84/RF6
AN2/C2INB/CTCMP/CTED13/RP13/SEG5/CN4/RB2
PGEC1/CVREF-/AN1/RP1/SEG6/CTED12/CN3/RB1
PGED1/CVREF+/AN0/RP0/SEG7/PMA6/CN2/RB0
RP30/CN70/RF2
RP16/SEG12/CN71/RF3
Legend:
Note:
RPn and RPIn represent remappable pins for Peripheral Pin Select feature. Shaded pins indicate pins that are tolerant up to +5.5V.
Pinouts are subject to change.
2010-2011 Microchip Technology Inc.
DS39996F-page 3
PIC24FJ128GA310 FAMILY
Pin Diagrams (continued)
80-Pin TQFP
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
RPI37/SOSCO/SCKLI/RC14
SOSCI/RC13
RP11/SEG17/CN49/RD0
1
PMD5/CTED4/LCDBIAS2/CN63/RE5
PMD6/LCDBIAS1/CN64/RE6
PMD7/LCDBIAS0/CN65/RE7
RPI38/SEG32/CN45/RC1
RPI40/SEG33/CN47/RC3
C1IND/RP21/SEG0/PMA5/CN8/RG6
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
RP12/C3INC/SEG16/PMA14/CS1/CN56/RD11
RP3/SEG15/C3IND/PMA15/CS2/CN55/RD10
RP4/SEG14/PMACK2/CN54/RD9
RP2/SEG13/RTCC/CN53/RD8
RPI35/SEG43/PMBE1/CN44/RA15
RPI36/SEG42/PMA22/CN43/RA14
VLCAP1/C1INC/RP26/PMA4/CN9/RG7
V
LCAP2/C2IND/RP19/PMA3/CN10/RG8
MCLR
VSS
C2INC/RP27/SEG1/PMA2/CN11/RG9
PIC24FJXXXGA308
OSCO/CLKO/CN22/RC15
OSCI/CLKI/CN23/RC12
VSS
VDD
VDD
TMS/RPI33/SEG34/PMCS1/CN66/RE8
TDO/RPI34/SEG35/PMA19/CN67/RE9
PGEC3/AN5/C1INA/RP18/SEG2/CN7/RB5
PGED3/AN4/C1INB/RP28/SEG3/CN6/RB4
AN3/C2INA/SEG4/CN5/RB3
SEG28/SCL1/CN72/RG2
SEG47/SDA1/CN73/RG3
INT0/CN84/RF6
CN83/RF7
AN2/C2INB/RP13/CTCMP/SEG5/CTED13/CN4/RB2
PGEC1/CVREF-/AN1/RP1/SEG6/CTED12/CN3/RB1
PGED1/CVREF+/AN0/RP0/SEG7/CN2/RB0
RP15/SEG41/CN74/RF8
RP30/SEG40/CN70/RF2
RP16/SEG12/CN71/RF3
Legend:
Note:
RPn and RPIn represent remappable pins for Peripheral Pin Select feature. Shaded pins indicate pins that are tolerant up to +5.5V.
Pinouts are subject to change.
DS39996F-page 4
2010-2011 Microchip Technology Inc.
PIC24FJ128GA310 FAMILY
Pin Diagrams (continued)
100-Pin TQFP
V
SS
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
1
SEG51/CTED3/CN82/RG15
RPI37/SOSCO/SCLKI/RC14
SOSCI/RC13
RP11/SEG17/CN49/RD0
RP12/SEG16/C3INC/PMA14/CS1/CN56/RD11
RP3/SEG15/C3IND/PMA15/CS2/CN55/RD10
RP4/SEG14/PMACK2/CN54/RD9
RP2/SEG13/RTCC/CN53/RD8
RPI35/SEG43/PMBE1/CN44/RA15
RPI36/SEG42/PMA22/CN43/RA14
VDD
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
CTED4/PMD5/LCDBIAS2/CN63/RE5
PMD6/LCDBIAS1/CN64/RE6
PMD7/LCDBIAS0/CN65/RE7
RPI38/SEG32/CN45/RC1
RPI39/SEG52/CN46/RC2
RPI40/SEG33/CN47/RC3
AN16/RPI41/SEG53/PMCS2/CN48/RC4
AN17/C1IND/RP21/SEG0/PMA5/CN8/RG6
LCAP1/AN18/C1INC/RP26/PMA4/CN9/RG7
LCAP2/AN19/C2IND/RP19/PMA3/CN10/RG8
MCLR
VSS
V
V
OSCO/CLKO/CN22/RC15
PIC24FJXXXGA310
OSCI/CLKI/CN23/RC12
VDD
TDO/CN38/RA5
TDI/PMA21/CN37/RA4
SDA2/SEG57/PMA20/CN36/RA3
SCL2/SEG56/CN35/RA2
SCL1/SEG28/CN72/RG2
SDA1/SEG47/CN73/RG3
INT0/CN84/RF6
AN20/C2INC/RP27/SEG1/PMA2/CN11/RG9
VSS
VDD
TMS/CTED0/SEG49/CN33/RA0
RPI33/SEG34/PMCS1/CN66/RE8
AN21/RPI34/SEG35/PMA19/CN67/RE9
PGEC3/AN5/C1INA/RP18/SEG2/CN7/RB5
PGED3/AN4/C1INB/RP28/SEG3/CN6/RB4
AN3/C2INA/SEG4/CN5/RB3
CN83/RF7
AN2/C2INB/RP13/SEG5/CTED13/CTCMP/CN4/RB2
PGEC1/CVREF-/AN1/RP1/SEG6/CTED12/CN3/RB1
PGED1/CVREF+/AN0/RP0/SEG7/CN2/RB0
RP15/SEG41/CN74/RF8
RP30/SEG40/CN70/RF2
RP16/SEG12/CN71/RF3
Legend:
Note:
RPn and RPIn represent remappable pins for Peripheral Pin Select feature. Shaded pins indicate pins that are tolerant up to +5.5V.
Pinouts are subject to change.
2010-2011 Microchip Technology Inc.
DS39996F-page 5
PIC24FJ128GA310 FAMILY
Pin Diagrams (continued)
121-Pin BGA (Top View)
1
2
3
4
5
6
7
8
9
10
11
A
RE4
RE3
RG13
RE0
RG0
RF1
VBAT
N/C
RD12
RD2
RD1
B
C
D
E
N/C
RG15
VDD
RE2
RE1
RA7
RA6
RF0
N/C
VCAP/
RD5
RD4
RD3
N/C
VSS
RC14
RD11
VDDCORE
RE6
RG12
RG14
RD7
RC13
RC1
RC4
RE7
RC3
RG8
RE5
RG6
RG9
N/C
RC2
RG7
N/C
N/C
VSS
N/C
RG1
N/C
RD6
N/C
N/C
RD13
RA15
VDD
RD0
RD8
N/C
RD9
VSS
RD10
RA14
F
MCLR
OSCI/
RC12
OSCO/
RC15
G
RE8
RE9
RA0
N/C
VDD
VSS
VSS
N/C
RA5
RA3
RA4
H
J
RB5
RB3
RB4
RB2
N/C
N/C
N/C
VDD
RA1
N/C
RF7
N/C
RF6
N/C
RG2
RF8
RA2
RG3
RB7
AVDD
RB11
RB12
K
L
RB1
RB6
RB0
RA9
RA10
AVSS
RB8
RB9
N/C
RF12
RF13
RB14
RB13
VDD
RD15
RD14
RF3
RF4
RF2
RF5
RB10
RB15
Legend:
Note:
Shaded pins indicate pins that are tolerant up to +5.5V.
See Table 1 for complete pinout descriptions. Pinouts are subject to change.
DS39996F-page 6
2010-2011 Microchip Technology Inc.
PIC24FJ128GA310 FAMILY
TABLE 1:
COMPLETE PIN FUNCTION DESCRIPTIONS FOR 121-PIN DEVICES
Pin
Function
Pin
Function
A1
A2
SEG63/PMD4/LVDIN/CTED8/CN62/RE4
COM0/PMD3/CTED9/CN61/RE3
SEG62/CTED10/CN80/RG13
COM3/PMD0/CN58/RE0
SEG50/PMD8/CN77/RG0
SEG48/COM4/PMD10/CN69/RF1
VBAT
E1
E2
E3
E4
E5
E6
E7
E8
E9
E10
E11
AN16/RPI41/SEG53/PMCS2/CN48/RC4
RPI40/SEG33/CN47/RC3
AN17/C1IND/RP21/SEG0/PMA5/CN8/RG6
RPI39/SEG52/CN46/RC2
N/C
A3
A4
A5
A6
SEG46/PMD9/CN78/RG1
N/C
A7
A8
N/C
RPI35/SEG43/PMBE1/CN44/RA15
RP2/SEG13/RTCC/CN53/RD8
RP4/SEG14/PMACK2/CN54/RD9
RPI36/SEG42/PMA22/CN43/RA14
A9
RPI42/SEG44/PMD12/CN57/RD12
RP23/SEG21/PMACK1/CN51/RD2
RP24/SEG20/CN50/RD1
A10
A11
B1
B2
N/C
F1
F2
MCLR
SEG51/CTED3/CN82/RG15
COM1/PMD2/CN60/RE2
COM2/PMD1/CN59/RE1
AN22/SEG59/PMA17/CN40/RA7
SEG27/PMD11/CN68/RF0
VCAP
VLCAP2/AN19/C2IND/RP19/PMA3/CN10/RG8
B3
F3
AN20/C2INC/RP27/SEG1/PMA2/CN11/RG9
B4
F4
VLCAP1/AN18/C1INC/RP26/PMA4/CN9/RG7
B5
F5
VSS
B6
F6
N/C
B7
F7
N/C
B8
RP20/SEG24/PMRD/CN14/RD5
RP22/SEG22/PMBE0/CN52/RD3
VSS
F8
VDD
B9
F9
OSCI/CLKI/CN23/RC12
B10
B11
C1
F10
F11
G1
G2
G3
G4
G5
G6
G7
G8
G9
G10
G11
H1
H2
H3
H4
H5
H6
H7
H8
H9
H10
H11
VSS
RPI37/SOSCO/SCLKI/RC14
PMD6/LCDBIAS1/CN64/RE6
VDD
OSCO/CLKO/CN22/RC15
RPI33/SEG34/PMCS1/CN66/RE8
C2
AN21/RPI34/SEG35/PMPA19/CN67/RE9
C3
SEG61/CN79/RG12
TMS/SEG49/CTED0/CN33/RA0
C4
SEG60/PMA16/CTED11/CN81/RG14
AN23/SEG58/CN39/RA6
N/C
N/C
C5
VDD
C6
VSS
C7
C3INA/SEG26/PMD15/CN16/RD7
RP25/SEG23/PMWR/CN13/RD4
N/C
VSS
C8
N/C
C9
TDO/CN38/RA5
C10
C11
D1
SOSCI/RC13
SDA2/SEG57/PMA20/CN36/RA3
RP12/SEG16/C3INC/PMA14/CS1/CN56/RD11
RPI38/SEG32/CN45/RC1
PMD7/LCDBIAS0/CN65/RE7
PMD5/CTED4/LCDBIAS2/CN63/RE5
N/C
TDI/PMA21/CN37/RA4
PGEC3/AN5/C1INA/RP18/SEG2/CN7/RB5
D2
PGED3/AN4/C1INB/RP28/SEG3/CN6/RB4
D3
N/C
D4
N/C
D5
N/C
N/C
D6
N/C
VDD
D7
C3INB/SEG25/PMD14/CN15/RD6
SEG45/PMD13/CN19/RD13
RP11/SEG17/CN49/RD0
N/C
N/C
D8
CN83/RF7
D9
INT0/CN84/RF6
SCL1/SEG28/CN72/RG2
SCL2/SEG56/CN35/RA2
D10
D11
Legend:
Note:
RP3/SEG15/C3IND/PMA15/CS2/CN55/RD10
RPn and RPIn represent remappable pins for Peripheral Pin Select functions.
Pinouts are subject to change.
2010-2011 Microchip Technology Inc.
DS39996F-page 7
PIC24FJ128GA310 FAMILY
TABLE 1:
COMPLETE PIN FUNCTION DESCRIPTIONS FOR 121-PIN DEVICES (CONTINUED)
Pin
Function
Pin
Function
J1
J2
AN3/C2INA/SEG4/CN5/RB3
K7
K8
K9
K10
K11
L1
AN14/RP14/SEG8/CTPLS/CTED5/PMA1/CN32/RB14
VDD
AN2/C2INB/RP13/SEG5/CTCMP/CTED13/CN4/RB2
PGED2/AN7/RP7/CN25/RB7
AVDD
J3
RP5/SEG39/CN21/RD15
J4
RP16/SEG12/CN71/RF3
J5
AN11/PMA12/CN29/RB11
TCK/CN34/RA1
RP30/SEG40/CN70/RF2
J6
PGEC2/AN6/RP6/LCDBIAS3/CN24/RB6
VREF-/SEG36/PMA7/CN41/RA9
AVSS
J7
AN12/SEG18/CTED2/PMA11/CN30/RB12
N/C
L2
J8
L3
J9
N/C
L4
AN9/RP9/COM6/SEG30/T1CK/CN27/RB9
CVREF/AN10/COM5/SEG29/PMA13/CN28/RB10
RP31/SEG54/CN76/RF13
J10
J11
K1
RP15/SEG41/CN74/RF8
L5
SDA1/SEG47/CN73/RG3
PGEC1/CVREF-/AN1/RP1/SEG6/CTED12/CN3/RB1
PGD1/CVREF+/AN0/RP0/SEG7/CN2/RB0
VREF+/SEG37/PMA6/CN42/RA10
AN8/RP8/COM7/SEG31/CN26/RB8
N/C
L6
L7
AN13/SEG19/CTED1/PMA10/CN31/RB13
AN15/RP29/SEG9/CTED6/REFO/PMA0/CN12/RB15
RPI43/SEG38/CN20/RD14
K2
L8
K3
L9
K4
L10
L11
RP10/SEG10/PMA9/CN17/RF4
RP17/SEG11/PMA8/CN18/RF5
K5
K6
RPI32/SEG55/CTED7/PMA18/CN75/RF12
Legend:
Note:
RPn and RPIn represent remappable pins for Peripheral Pin Select functions.
Pinouts are subject to change.
DS39996F-page 8
2010-2011 Microchip Technology Inc.
PIC24FJ128GA310 FAMILY
Table of Contents
1.0 Device Overview ........................................................................................................................................................................ 11
2.0 Guidelines for Getting Started with 16-bit Microcontrollers ........................................................................................................ 29
3.0 CPU ........................................................................................................................................................................................... 35
4.0 Memory Organization................................................................................................................................................................. 41
5.0 Direct Memory Access Controller (DMA) ................................................................................................................................... 75
6.0 Flash Program Memory.............................................................................................................................................................. 83
7.0 Resets ........................................................................................................................................................................................ 89
8.0 Interrupt Controller ..................................................................................................................................................................... 95
9.0 Oscillator Configuration............................................................................................................................................................ 145
10.0 Power-Saving Features............................................................................................................................................................ 155
11.0 I/O Ports ................................................................................................................................................................................... 167
12.0 Timer1 ...................................................................................................................................................................................... 197
13.0 Timer2/3 and Timer4/5 ............................................................................................................................................................ 199
14.0 Input Capture with Dedicated Timers....................................................................................................................................... 205
15.0 Output Compare with Dedicated Timers .................................................................................................................................. 211
16.0 Serial Peripheral Interface (SPI)............................................................................................................................................... 221
2
17.0 Inter-Integrated Circuit™ (I C™).............................................................................................................................................. 233
18.0 Universal Asynchronous Receiver Transmitter (UART)........................................................................................................... 241
19.0 Data Signal Modulator.............................................................................................................................................................. 249
20.0 Enhanced Parallel Master Port (EPMP)................................................................................................................................... 253
21.0 Liquid Crystal Display (LCD) Controller.................................................................................................................................... 265
22.0 Real-Time Clock and Calendar (RTCC) .................................................................................................................................. 275
23.0 32-Bit Programmable Cyclic Redundancy Check (CRC) Generator........................................................................................ 289
24.0 12-Bit A/D Converter with Threshold Scan............................................................................................................................... 295
25.0 Triple Comparator Module........................................................................................................................................................ 315
26.0 Comparator Voltage Reference................................................................................................................................................ 321
27.0 Charge Time Measurement Unit (CTMU) ................................................................................................................................ 323
28.0 High/Low-Voltage Detect (HLVD)............................................................................................................................................. 331
29.0 Section Special Features ........................................................................................................................................................ 333
30.0 Development Support............................................................................................................................................................... 347
31.0 Instruction Set Summary.......................................................................................................................................................... 351
32.0 Electrical Characteristics.......................................................................................................................................................... 359
33.0 Packaging Information.............................................................................................................................................................. 377
Appendix A: Revision History............................................................................................................................................................. 393
Index .................................................................................................................................................................................................. 395
The Microchip Web Site..................................................................................................................................................................... 401
Customer Change Notification Service .............................................................................................................................................. 401
Customer Support.............................................................................................................................................................................. 401
Reader Response.............................................................................................................................................................................. 402
Product Identification System ............................................................................................................................................................ 403
2010-2011 Microchip Technology Inc.
DS39996F-page 9
PIC24FJ128GA310 FAMILY
TO OUR VALUED CUSTOMERS
It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip
products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and
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If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via
E-mail at docerrors@microchip.com or fax the Reader Response Form in the back of this data sheet to (480) 792-4150. We
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The last character of the literature number is the version number, (e.g., DS30000A is version A of document DS30000).
Errata
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DS39996F-page 10
2010-2011 Microchip Technology Inc.
PIC24FJ128GA310 FAMILY
Many of these new low-power modes also support the
continuous operation of the low-power, on-chip
Real-Time Clock/Calendar (RTCC), making it possible
for an application to keep time while the device is
otherwise asleep.
1.0
DEVICE OVERVIEW
This document contains device-specific information for
the following devices:
• PIC24FJ64GA306
• PIC24FJ64GA308
• PIC24FJ64GA310
• PIC24FJ128GA306
• PIC24FJ128GA308
• PIC24FJ128GA310
Aside from these new features, PIC24FJ128GA310 fam-
ily devices also include all of the legacy power-saving
features of previous PIC24F microcontrollers, such as:
The PIC24FJ128GA310 family adds many new fea-
tures to Microchip‘s 16-bit microcontrollers, including
new ultra low-power features, Direct Memory Access
(DMA) for peripherals, and a built-in LCD Controller
and Driver. Together, these provide a wide range of
powerful features in one economical and power-saving
package.
• On-the-Fly Clock Switching, allowing the selection
of a lower-power clock during run time
• Doze Mode Operation, for maintaining peripheral
clock speed while slowing the CPU clock
• Instruction-Based Power-Saving Modes, for quick
invocation of Idle and the many Sleep modes.
1.1.3
OSCILLATOR OPTIONS AND
FEATURES
1.1
Core Features
All of the devices in the PIC24FJ128GA310 family offer
five different oscillator options, allowing users a range
of choices in developing application hardware. These
include:
1.1.1
16-BIT ARCHITECTURE
Central to all PIC24F devices is the 16-bit modified
Harvard architecture, first introduced with Microchip’s
dsPIC® Digital Signal Controllers (DSCs). The PIC24F
CPU core offers a wide range of enhancements, such
as:
• Two Crystal modes
• Two External Clock modes
• A Phase Lock Loop (PLL) frequency multiplier,
which allows clock speeds of up to 32 MHz
• 16-bit data and 24-bit address paths with the
ability to move information between data and
memory spaces
• A Fast Internal Oscillator (FRC) (nominal 8 MHz
output) with multiple frequency divider options
• Linear addressing of up to 12 Mbytes (program
space) and 32 Kbytes (data)
• A separate Low-Power Internal RC Oscillator
(LPRC) (31 kHz nominal) for low-power,
timing-insensitive applications.
• A 16-element working register array with built-in
software stack support
• A 17 x 17 hardware multiplier with support for
integer math
The internal oscillator block also provides a stable
reference source for the Fail-Safe Clock Monitor
(FSCM). This option constantly monitors the main clock
source against a reference signal provided by the inter-
nal oscillator and enables the controller to switch to the
internal oscillator, allowing for continued low-speed
operation or a safe application shutdown.
• Hardware support for 32 by 16-bit division
• An instruction set that supports multiple
addressing modes and is optimized for high-level
languages, such as ‘C’
• Operational performance up to 16 MIPS
1.1.4
EASY MIGRATION
1.1.2
nanoWatt XLP POWER-SAVING
TECHNOLOGY
Regardless of the memory size, all devices share the
same rich set of peripherals, allowing for a smooth
migration path as applications grow and evolve. The
consistent pinout scheme used throughout the entire
family also aids in migrating from one device to the next
larger, or even in jumping from 64-pin to 100-pin
devices.
The PIC24FJ128GA310 family of devices introduces a
greatly-expanded range of power-saving operating
modes for the ultimate in power conservation. The new
modes include:
• Retention Sleep, with essential circuits being
powered from a separate low-voltage regulator
The PIC24F family is pin compatible with devices in the
dsPIC33 family, and shares some compatibility with the
pinout schema for PIC18 and dsPIC30. This extends
the ability of applications to grow from the relatively
simple, to the powerful and complex, yet still selecting
a Microchip device.
• Deep Sleep without RTCC, for the lowest possible
power consumption under software control
• VBAT mode (with or without RTCC), to continue
operation limited operation from a back-up battery
when VDD is removed
2010-2011 Microchip Technology Inc.
DS39996F-page 11
PIC24FJ128GA310 FAMILY
• Enhanced Parallel Master/Parallel Slave Port:
This module allows rapid and transparent access
to the microcontroller data bus, and enables the
CPU to directly address external data memory. The
parallel port can function in Master or Slave mode,
accommodating data widths of 4, 8 or 16 bits, and
address widths up to 23 bits in Master modes.
1.2
DMA Controller
PIC24FJ128GA310 family devices also introduce a
new Direct Memory Access Controller (DMA) to the
PIC24F architecture. This module acts in concert with
the CPU, allowing data to move between data memory
and peripherals without the intervention of the CPU,
increasing data throughput and decreasing execution
time overhead. Six independently programmable chan-
nels make it possible to service multiple peripherals at
virtually the same time, with each channel peripheral
performing a different operation. Many types of data
transfer operations are supported.
• Real-Time Clock and Calendar (RTCC): This
module implements a full-featured clock and
calendar with alarm functions in hardware, freeing
up timer resources and program memory space
for use of the core application.
• Data Signal Modulator (DSM): The Data Signal
Modulator (DSM) allows the user to mix a digital
data stream (the “modulator signal”) with a carrier
signal to produce a modulated output.
1.3
LCD Controller
With the PIC24FJ128GA310 family of devices,
Microchip introduces its versatile Liquid Crystal Display
(LCD) controller and driver to the PIC24F family. The
on-chip LCD driver includes many features that make
the integration of displays in low-power applications
easier. These include an integrated voltage regulator
with charge pump and an integrated internal resistor
ladder that allows contrast control in software and
display operation above device VDD.
1.5
Details on Individual Family
Members
Devices in the PIC24FJ128GA310 family are available
in 64-pin, 80-pin and 100-pin packages. The general
block diagram for all devices is shown in Figure 1-1.
The devices are differentiated from each other in
six ways:
1.4
Other Special Features
1. Flash program memory (64 Kbytes for
PIC24FJ64GA3XX devices and 128 Kbytes for
PIC24FJ128GA3XX devices).
• Peripheral Pin Select: The Peripheral Pin Select
(PPS) feature allows most digital peripherals to be
mapped over a fixed set of digital I/O pins. Users
may independently map the input and/or output of
any one of the many digital peripherals to any one
of the I/O pins.
2. Available I/O pins and ports (53 pins on 6 ports
for 64-pin devices, 69 pins on 7 ports for 80-pin
devices and 85 pins on 7 ports for 100-pin
devices).
3. Available Interrupt-on-Change Notification (ICN)
inputs (52 on 64-pin devices, 66 on 80-pin
devices and 82 on 100-pin devices).
• Communications: The PIC24FJ128GA310 family
incorporates a range of serial communication
peripherals to handle a range of application
requirements. There are two independent I2C™
modules that support both Master and Slave
modes of operation. Devices also have, through
the PPS feature, four independent UARTs with
built-in IrDA® encoders/decoders and two SPI
modules.
4. Available remappable pins (29 pins on 64-pin
devices, 40 on 80-pin devices and 44 pins on
100-pin devices).
5. Maximum available drivable LCD pixels (272 on
64-pin devices, 368 on 80-pin devices and
480 on 100-pin devices.)
• Analog Features: All members of the
PIC24FJ128GA310 family include the new 12-bit
A/D Converter (A/D) module and a triple compara-
tor module. The A/D module incorporates a range
of new features that allow the converter to assess
and make decisions on incoming data, reducing
CPU overhead for routine A/D conversions. The
comparator module includes three analog com-
parators that are configurable for a wide range of
operations.
6. Analog input channels (16 channels for 64-pin
and 80-pin devices, and 24 channels for 100-pin
devices).
All other features for devices in this family are identical.
These are summarized in Table 1-1, Table 1-2 and
Table 1-3.
A
list of the pin features available on the
PIC24FJ128GA310 family devices, sorted by function,
is shown in Table 1-4. Note that this table shows the pin
location of individual peripheral features and not how
they are multiplexed on the same pin. This information
is provided in the pinout diagrams in the beginning of
the data sheet. Multiplexed features are sorted by the
priority given to a feature, with the highest priority
peripheral being listed first.
• CTMU Interface: In addition to their other analog
features, members of the PIC24FJ128GA310
family include the CTMU interface module. This
provides a convenient method for precision time
measurement and pulse generation, and can
serve as an interface for capacitive sensors.
PIC24FJDS39996F-page 12
2010-2011 Microchip Technology Inc.
PIC24FJ128GA310 FAMILY
TABLE 1-1:
DEVICE FEATURES FOR THE PIC24FJ128GA310 FAMILY: 64-PIN
Features
PIC24FJ64GA306
PIC24FJ128GA306
Operating Frequency
DC – 32 MHz
Program Memory (bytes)
Program Memory (instructions)
Data Memory (bytes)
64K
128K
22,016
44,032
8K
Interrupt Sources (soft vectors/
NMI traps)
65 (61/4)
I/O Ports
Ports B, C, D, E, F, G
53
Total I/O Pins
Remappable Pins
30 (29 I/O, 1 Input only)
Timers:
Total Number (16-bit)
32-Bit (from paired 16-bit timers)
Input Capture Channels
Output Compare/PWM Channels
Input Change Notification Interrupt
Serial Communications:
UART
5(1)
2
7(1)
7(1)
52
4(1)
2(1)
2
SPI (3-wire/4-wire)
I2C™
Digital Signal Modulator
ParallelCommunications (EPMP/PSP)
JTAG Boundary Scan
Yes
Yes
Yes
16
12/10-Bit Analog-to-Digital Converter
(A/D) Module (input channels)
Analog Comparators
CTMU Interface
3
Yes
LCD Controller (available pixels)
Resets (and Delays)
240 (30 SEG x 8 COM)
Core POR, VDD POR, VBAT POR,BOR, RESETInstruction,
MCLR, WDT; Illegal Opcode, REPEATInstruction,
Hardware Traps, Configuration Word Mismatch
(OST, PLL Lock)
Instruction Set
Packages
76 Base Instructions, Multiple Addressing Mode Variations
64-Pin TQFP and QFN
Note 1: Peripherals are accessible through remappable pins.
2010-2011 Microchip Technology Inc.
DS39996F-page 13
PIC24FJ128GA310 FAMILY
TABLE 1-2:
DEVICE FEATURES FOR THE PIC24FJ128GA310 FAMILY: 80-PIN
Features
PIC24FJ64GA308
PIC24FJ128GA308
Operating Frequency
DC – 32 MHz
Program Memory (bytes)
Program Memory (instructions)
Data Memory (bytes)
64K
128K
22,016
44,032
8K
Interrupt Sources (soft vectors/
NMI traps)
65 (61/4)
I/O Ports
Ports A, B, C, D, E, F, G
69
Total I/O Pins
Remappable Pins
40 (31 I/O, 9 Input only)
Timers:
Total Number (16-bit)
32-Bit (from paired 16-bit timers)
Input Capture Channels
Output Compare/PWM Channels
Input Change Notification Interrupt
Serial Communications:
UART
5(1)
2
7(1)
7(1)
66
4(1)
2(1)
2
SPI (3-wire/4-wire)
I2C™
Digital Signal Modulator
ParallelCommunications (EPMP/PSP)
JTAG Boundary Scan
Yes
Yes
Yes
16
12/10-Bit Analog-to-Digital Converter
(A/D) Module (input channels)
Analog Comparators
CTMU Interface
3
Yes
LCD Controller (available pixels)
Resets (and Delays)
368 (46 SEG x 8 COM)
Core POR, VDD POR, VBAT POR,BOR, RESETInstruction,
MCLR, WDT; Illegal Opcode, REPEATInstruction,
Hardware Traps, Configuration Word Mismatch
(OST, PLL Lock)
Instruction Set
Packages
76 Base Instructions, Multiple Addressing Mode Variations
80-Pin TQFP and QFN
Note 1: Peripherals are accessible through remappable pins.
PIC24FJDS39996F-page 14
2010-2011 Microchip Technology Inc.
PIC24FJ128GA310 FAMILY
TABLE 1-3:
DEVICE FEATURES FOR THE PIC24FJ128GA310 FAMILY: 100-PIN DEVICES
Features
PIC24FJ64GA310
PIC24FJ128GA310
Operating Frequency
DC – 32 MHz
Program Memory (bytes)
Program Memory (instructions)
Data Memory (bytes)
64K
128K
22,016
44,032
8K
Interrupt Sources (soft vectors/NMI
traps)
66 (62/4)
I/O Ports
Ports A, B, C, D, E, F, G
85
Total I/O Pins
Remappable Pins
Timers:
44 (32 I/O, 12 input only)
Total Number (16-bit)
32-Bit (from paired 16-bit timers)
Input Capture Channels
Output Compare/PWM Channels
Input Change Notification Interrupt
Serial Communications:
UART
5(1)
2
7(1)
7(1)
82
4(1)
2(1)
2
SPI (3-wire/4-wire)
I2C™
Digital Signal Modulator
Yes
Yes
Parallel Communications
(EPMP/PSP)
JTAG Boundary Scan
Yes
24
12/10-Bit Analog-to-Digital Converter
(A/D) Module (input channels)
Analog Comparators
CTMU Interface
3
Yes
LCD Controller (available pixels)
Resets (and delays)
480 (60 SEG x 8 COM)
Core POR, VDD POR, VBAT POR,BOR, RESETInstruction,
MCLR, WDT; Illegal Opcode, REPEATInstruction,
Hardware Traps, Configuration Word Mismatch
(OST, PLL Lock)
Instruction Set
Packages
76 Base Instructions, Multiple Addressing Mode Variations
100-Pin TQFP and 121-Pin BGA
Note 1: Peripherals are accessible through remappable pins.
2010-2011 Microchip Technology Inc.
DS39996F-page 15
PIC24FJ128GA310 FAMILY
FIGURE 1-1:
PIC24FJ128GA310 FAMILY GENERAL BLOCK DIAGRAM
Data Bus
Interrupt
Controller
PORTA(1)
(12 I/O)
16
16
16
8
EDS and
Table Data
Access Control
Data Latch
Data RAM
DMA
Controller
PCH
PCL
23
Program Counter
Address
Latch
PORTB
(16 I/O)
Repeat
Control
Logic
Stack
Control
Logic
16
23
16
16
Read AGU
Write AGU
Address Latch
PORTC(1)
(8 I/O)
Program Memory/
Extended Data
Space
Data Latch
Address Bus
24
16
EA MUX
16
16
Inst Latch
PORTD(1)
(16 I/O)
Literal
Data
Inst Register
DMA
Data Bus
Instruction
Control Signals
Decode and
Control
PORTE(1)
(10 I/O)
Divide
Support
16 x 16
OSCO/CLKO
OSCI/CLKI
W Reg Array
17x17
Multiplier
Power-up
Timer
Timing
Generation
Oscillator
Start-up Timer
REFO
FRC/LPRC
Oscillators
PORTF(1)
(10 I/O)
16-Bit ALU
16
Power-on
Reset
Precision
Band Gap
Reference
Watchdog
Timer
LVD & BOR(2)
Voltage
Regulators
PORTG(1)
(12 I/O)
VCAP VBAT
Timer2/3(3)
VDD, VSS
MCLR
Digital
12-Bit
Timer1
Comparators(3)
Timer4/5(3)
RTCC
Modulator
A/D
EPMP/PSP
I2C™
1/2
OC/PWM
1-7(3)
SPI
1/2(3)
IC
1-7(3)
UART
1/2/3/4(3)
LCD
Driver
ICNs(1)
CTMU
Note 1: Not all I/O pins or features are implemented on all device pinout configurations. See Table 1-4 for specific implementations by pin count
2: BOR functionality is provided when the on-board voltage regulator is enabled.
.
3: These peripheral I/Os are only accessible through remappable pins.
PIC24FJDS39996F-page 16
2010-2011 Microchip Technology Inc.
PIC24FJ128GA310 FAMILY
TABLE 1-4:
PIC24FJ128GA310 FAMILY PINOUT DESCRIPTIONS
Pin Number/Grid Locator
Pin
Function
Input
Buffer
I/O
Description
64-Pin
80-Pin
TQFP
100-Pin 121-Pin
TQFP
TQFP
BGA
AN0
16
15
15
14
13
12
11
17
18
21
22
23
24
27
28
29
30
—
—
—
—
—
—
—
—
19
20
11
12
5
20
19
19
18
17
16
15
21
22
27
28
29
30
33
34
35
36
—
—
—
—
—
—
—
—
25
26
15
16
7
25
24
24
23
22
21
20
26
27
32
33
34
35
41
42
43
44
9
K2
K1
K1
J2
I
I
ANA
ANA
ANA
ANA
ANA
ANA
ANA
ANA
ANA
ANA
ANA
ANA
ANA
ANA
ANA
ANA
ANA
ANA
ANA
ANA
ANA
ANA
ANA
ANA
ANA
—
A/D Analog Inputs.
A/D Analog Inputs.
AN1
AN1-
AN2
I
I
AN3
J1
I
AN4
H2
H1
L1
J3
I
AN5
I
AN6
I
AN7
I
AN8
K4
L4
L5
J5
I
AN9
I
AN10
AN11
AN12
AN13
AN14
AN15
AN16
AN17
AN18
AN19
AN20
AN21
AN22
AN23
AVDD
AVSS
C1INA
C1INB
C1INC
C1IND
C2INA
C2INB
C2INC
C2IND
C3INA
C3INB
C3INC
C3IND
CLKI
I
I
J7
I
L7
K7
L8
E1
E3
F4
F2
F3
G2
B5
C5
J4
I
I
I
I
10
11
12
14
19
92
91
30
31
20
21
11
10
22
23
14
12
84
83
71
70
63
64
I
I
I
I
I
I
I
P
P
I
Positive Supply for Analog modules.
Ground Reference for Analog modules.
Comparator 1 Input A.
L3
—
H1
H2
F4
E3
J1
ANA
ANA
ANA
ANA
ANA
ANA
ANA
ANA
ANA
ANA
ANA
ANA
ANA
—
I
Comparator 1 Input B.
I
Comparator 1 Input C.
4
6
I
Comparator 1 Input D.
13
14
8
17
18
10
8
I
Comparator 2 Input A.
J2
I
Comparator 2 Input B.
F3
F2
C7
D7
C11
D11
F9
F11
I
Comparator 2 Input C.
6
I
Comparator 2 Input D.
55
54
45
44
39
40
69
68
57
56
49
50
I
Comparator 3 Input A.
I
Comparator 3 Input B.
I
Comparator 3 Input C.
I
Comparator 3 Input D.
I
Main Clock Input Connection.
System Clock Output.
CLKO
O
Legend:
TTL = TTL input buffer
ANA = Analog level input/output
ST = Schmitt Trigger input buffer
I C™ = I C/SMBus input buffer
2
2
2010-2011 Microchip Technology Inc.
DS39996F-page 17
PIC24FJ128GA310 FAMILY
TABLE 1-4:
PIC24FJ128GA310 FAMILY PINOUT DESCRIPTIONS (CONTINUED)
Pin Number/Grid Locator
Pin
Function
Input
Buffer
I/O
Description
64-Pin
80-Pin
TQFP
100-Pin 121-Pin
TQFP
TQFP
BGA
CN2
16
15
14
13
12
11
4
20
19
18
17
16
15
6
25
24
23
22
21
20
10
11
12
14
44
81
82
83
84
49
50
80
47
48
64
63
26
27
32
33
34
35
41
42
43
17
38
58
59
60
61
91
92
28
29
66
K2
K1
J2
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
Interrupt-on-Change Inputs.
CN3
CN4
CN5
J1
CN6
H2
H1
E3
F4
F2
F3
L8
CN7
CN8
CN9
5
7
CN10
CN11
CN12
CN13
CN14
CN15
CN16
CN17
CN18
CN19
CN20
CN21
CN22
CN23
CN24
CN25
CN26
CN27
CN28
CN29
CN30
CN31
CN32
CN33
CN34
CN35
CN36
CN37
CN38
CN39
CN40
CN41
CN42
CN43
6
8
8
10
36
66
67
68
69
39
40
65
37
38
50
49
21
22
27
28
29
30
33
34
35
—
—
—
—
—
—
—
—
23
24
52
30
52
53
54
55
31
32
—
—
—
40
39
17
18
21
22
23
24
27
28
29
—
—
—
—
—
—
—
—
—
—
—
C8
B8
D7
C7
L10
L11
D8
L9
K9
F11
F9
L1
J3
K4
L4
L5
J5
J7
L7
K7
G3
J6
H11
G10
G11
G9
C5
B5
L2
K3
E11
Legend:
TTL = TTL input buffer
ANA = Analog level input/output
ST = Schmitt Trigger input buffer
I C™ = I C/SMBus input buffer
2
2
PIC24FJDS39996F-page 18
2010-2011 Microchip Technology Inc.
PIC24FJ128GA310 FAMILY
TABLE 1-4:
PIC24FJ128GA310 FAMILY PINOUT DESCRIPTIONS (CONTINUED)
Pin Number/Grid Locator
Pin
Function
Input
Buffer
I/O
Description
64-Pin 80-Pin 100-Pin 121-Pin
TQFP
TQFP
TQFP
BGA
CN44
CN45
CN46
CN47
CN48
CN49
CN50
CN51
CN52
CN53
CN54
CN55
CN56
CN57
CN58
CN59
CN60
CN61
CN62
CN63
CN64
CN65
CN66
CN67
CN68
CN69
CN70
CN71
CN72
CN73
CN74
CN75
CN76
CN77
CN78
CN79
CN80
CN81
CN82
CN83
CN84
—
—
—
—
—
46
49
50
51
42
43
44
45
—
60
61
62
63
64
1
53
4
67
6
E8
D1
E4
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
Interrupt-on-Change Inputs.
—
5
7
8
E2
—
58
61
62
63
54
55
56
57
64
76
77
78
79
80
1
9
E1
72
76
77
78
68
69
70
71
79
93
94
98
99
100
3
D9
A11
A10
B9
E9
E10
D11
C11
A9
A4
B4
119
A2
A1
D3
C1
D2
G1
G2
B6
2
2
4
3
3
5
—
—
58
59
34
33
37
36
—
—
—
—
—
—
—
—
—
—
35
13
14
72
73
42
41
47
46
43
—
—
75
74
—
—
—
—
44
45
18
19
87
88
52
51
57
56
53
40
39
90
89
96
97
95
1
A6
K11
K10
H10
J11
J10
K6
L6
A5
E6
C3
A3
C4
B2
54
55
H8
H9
Legend:
TTL = TTL input buffer
ANA = Analog level input/output
ST = Schmitt Trigger input buffer
I C™ = I C/SMBus input buffer
2
2
2010-2011 Microchip Technology Inc.
DS39996F-page 19
PIC24FJ128GA310 FAMILY
TABLE 1-4:
PIC24FJ128GA310 FAMILY PINOUT DESCRIPTIONS (CONTINUED)
Pin Number/Grid Locator
Pin
Function
Input
Buffer
I/O
Description
64-Pin
80-Pin
TQFP
100-Pin 121-Pin
TQFP
TQFP
BGA
COM0
COM1
COM2
COM3
COM4
COM5
COM6
COM7
CS1
63
62
61
60
59
23
22
21
45
79
78
77
76
73
29
28
27
57
99
98
94
93
88
34
33
32
71
A2
B3
B4
A4
A6
L5
O
O
—
—
—
—
—
—
—
—
LCD Driver Common Outputs.
O
O
O
O
L4
O
K4
C11
O
I/O
ST/TTL Parallel Master Port Chip Select 1 Strobe (shared
with PMA14)
CS2
44
56
70
D11
O
—
Parallel Master Port Chip Select 2 Strobe (shared
with PMA15)
CTCMP
CTED0
CTED1
CTED2
CTED3
CTED4
CTED5
CTED6
CTED7
CTED8
CTED9
CTED10
CTED11
CTED12
CTED13
CTPLS
CVREF
14
—
28
27
—
1
18
—
34
33
—
1
23
17
42
41
1
J2
G3
L7
J7
I
I
ANA
ANA
ANA
ANA
ANA
ANA
ANA
ANA
ANA
ANA
ANA
ANA
ANA
ANA
ANA
—
CTMU Comparator 2 Input (Pulse mode).
CTMU External Edge Inputs.
I
I
B2
D3
K7
L8
47
A1
A2
A3
C4
K1
J2
I
3
I
29
30
—
64
63
—
—
15
14
29
23
16
15
35
3
35
36
—
80
79
—
—
19
18
35
29
20
19
45
3
43
44
40
100
99
97
95
24
23
43
34
25
24
55
5
I
I
I
I
I
I
I
I
I
K7
L5
K2
K1
H9
D2
C1
D3
L1
A1
F1
O
O
I
CTMU Pulse Output.
—
Comparator Voltage Reference Output.
Comparator/A/D Reference Voltage (low) Input.
Comparator/A/D Reference Voltage (high) Input.
External Interrupt Input 0.
CVREF+
CVREF-
INT0
ANA
ANA
ST
I
I
LCDBIAS0
LCDBIAS1
LCDBIAS2
LCDBIAS3
LVDIN
I
ANA
ANA
ANA
ANA
ANA
ST
Bias Inputs for LCD Driver Charge Pump.
2
2
4
I
1
1
3
I
17
64
7
21
80
9
26
100
13
I
I
Low-Voltage Detect Input.
MCLR
I
Master Clear (device Reset) Input. This line is
brought low to cause a Reset.
OSCI
39
40
49
50
63
64
F9
I
ANA
—
Main Oscillator Input Connection.
Main Oscillator Output Connection.
OSCO
F11
O
Legend:
TTL = TTL input buffer
ANA = Analog level input/output
ST = Schmitt Trigger input buffer
I C™ = I C/SMBus input buffer
2
2
PIC24FJDS39996F-page 20
2010-2011 Microchip Technology Inc.
PIC24FJ128GA310 FAMILY
TABLE 1-4:
PIC24FJ128GA310 FAMILY PINOUT DESCRIPTIONS (CONTINUED)
Pin Number/Grid Locator
Pin
Function
Input
Buffer
I/O
Description
64-Pin
80-Pin
TQFP
100-Pin 121-Pin
TQFP
TQFP
BGA
PGEC1
PGED1
PGEC2
PGED2
PGEC3
PGED3
PMA0
15
19
20
21
22
15
16
36
35
24
K1
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
ST
ST
ST
ST
ST
ST
ST
ST
In-Circuit Debugger/Emulator/ICSP™ Programming
Clock.
16
17
18
11
12
30
29
25
26
27
20
21
44
43
K2
L1
J3
In-Circuit Debugger/Emulator/ICSP Programming
Data.
In-Circuit Debugger/Emulator/ICSP Programming
Clock.
In-Circuit Debugger/Emulator/ICSP Programming
Data.
H1
H2
L8
K7
In-Circuit Debugger/Emulator/ICSP Programming
Clock.
In-Circuit Debugger/Emulator/ICSP Programming
Data.
Parallel Master Port Address Bit 0 Input (Buffered
Slave modes) and Output (Master modes).
PMA1
Parallel Master Port Address Bit 1 Input (Buffered
Slave modes) and Output (Master modes).
PMA2
8
10
8
14
12
11
10
29
28
50
49
42
41
35
34
71
70
95
92
40
19
59
60
66
77
69
78
67
18
9
F3
F2
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
I
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Parallel Master Port Address (bits<22:2>).
PMA3
6
PMA4
5
7
F4
PMA5
4
6
E3
PMA6
16
22
32
31
28
27
24
23
45
44
—
—
—
—
—
—
—
50
43
51
—
—
—
24
23
40
39
34
33
30
29
57
56
—
—
—
14
—
—
52
62
55
63
53
13
—
K3
PMA7
L2
PMA8
L11
L10
L7
PMA9
PMA10
PMA11
PMA12
PMA13
PMA14
PMA15
PMA16
PMA17
PMA18
PMA19
PMA20
PMA21
PMA22
PMACK1
PMACK2
PMBE0
PMBE1
PMCS1
PMCS2
J7
J5
L5
C11
D11
C4
B5
K6
G2
G10
G11
E11
A10
E10
B9
ST/TTL Parallel Master Port Acknowledge Input 1.
ST/TTL Parallel Master Port Acknowledge Input 2.
I
O
O
I/O
O
—
—
Parallel Master Port Byte Enable 0 Strobe.
Parallel Master Port Byte Enable 1 Strobe.
E8
G1
E1
ST/TTL Parallel Master Port Chip Select 1 Strobe.
Parallel Master Port Chip Select 2 Strobe.
—
Legend:
TTL = TTL input buffer
ANA = Analog level input/output
ST = Schmitt Trigger input buffer
I C™ = I C/SMBus input buffer
2
2
2010-2011 Microchip Technology Inc.
DS39996F-page 21
PIC24FJ128GA310 FAMILY
TABLE 1-4:
PIC24FJ128GA310 FAMILY PINOUT DESCRIPTIONS (CONTINUED)
Pin Number/Grid Locator
Pin
Function
Input
Buffer
I/O
Description
64-Pin
80-Pin
TQFP
100-Pin 121-Pin
TQFP
TQFP
BGA
PMD0
PMD1
PMD2
PMD3
PMD4
PMD5
PMD6
PMD7
PMD8
PMD9
PMD10
PMD11
PMD12
PMD13
PMD14
PMD15
PMRD
PMWR
RA0
60
61
62
63
64
1
76
77
78
79
80
1
93
94
98
99
100
3
A4
B4
B3
A2
A1
D3
C1
D2
A5
E6
A6
B6
A9
D8
D7
C7
B8
C8
G3
J6
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
ST/TTL Parallel Master Port Data (Demultiplexed Master
mode) or Address/Data (Multiplexed Master modes).
ST/TTL
ST/TTL
ST/TTL
ST/TTL
ST/TTL
ST/TTL
ST/TTL
ST/TTL
ST/TTL
ST/TTL
ST/TTL
ST/TTL
ST/TTL
ST/TTL
ST/TTL
2
2
4
3
3
5
—
—
—
—
—
—
—
—
53
52
—
—
—
—
—
—
—
—
—
—
—
—
75
74
73
72
64
65
68
69
67
66
—
—
—
—
—
—
—
—
23
24
52
53
90
89
88
87
79
80
83
84
82
81
17
38
58
59
60
61
91
92
28
29
66
67
—
—
Parallel Master Port Read Strobe.
Parallel Master Port Write Strobe.
PORTA Digital I/O.
O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
RA1
RA2
H11
G10
G11
G9
C5
B5
L2
RA3
RA4
RA5
RA6
RA7
RA9
RA10
RA14
RA15
K3
E11
E8
Legend:
TTL = TTL input buffer
ANA = Analog level input/output
ST = Schmitt Trigger input buffer
I C™ = I C/SMBus input buffer
2
2
PIC24FJDS39996F-page 22
2010-2011 Microchip Technology Inc.
PIC24FJ128GA310 FAMILY
TABLE 1-4:
PIC24FJ128GA310 FAMILY PINOUT DESCRIPTIONS (CONTINUED)
Pin Number/Grid Locator
Pin
Function
Input
Buffer
I/O
Description
64-Pin
80-Pin
TQFP
100-Pin 121-Pin
TQFP
TQFP
BGA
RB0
16
15
14
13
12
11
17
18
21
22
23
24
27
28
29
30
—
—
—
—
39
47
48
40
46
49
50
51
52
53
54
55
42
43
44
45
—
—
—
—
20
19
18
17
16
15
21
22
27
28
29
30
33
34
35
36
4
25
24
23
22
21
20
26
27
32
33
34
35
41
42
43
44
6
K2
K1
J2
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
PORTB Digital I/O.
RB1
RB2
RB3
J1
RB4
H2
H1
L1
RB5
RB6
RB7
J3
RB8
K4
L4
RB9
RB10
RB11
RB12
RB13
RB14
RB15
RC1
RC2
RC3
RC4
RC12
RC13
RC14
RC15
RD0
RD1
RD2
RD3
RD4
RD5
RD6
RD7
RD8
RD9
RD10
RD11
RD12
RD13
RD14
RD15
L5
J5
J7
L7
K7
L8
D1
E4
E2
E1
F9
PORTC Digital I/O.
—
5
7
8
—
49
59
60
50
58
61
62
63
66
67
68
69
54
55
56
57
64
65
37
38
9
63
73
74
64
72
76
77
78
81
82
83
84
68
69
70
71
79
80
47
48
C10
B11
F11
D9
A11
A10
B9
C8
B8
D7
C7
E9
E10
D11
C11
A9
D8
L9
I
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
PORTD Digital I/O.
K9
Legend:
TTL = TTL input buffer
ANA = Analog level input/output
ST = Schmitt Trigger input buffer
I C™ = I C/SMBus input buffer
2
2
2010-2011 Microchip Technology Inc.
DS39996F-page 23
PIC24FJ128GA310 FAMILY
TABLE 1-4:
PIC24FJ128GA310 FAMILY PINOUT DESCRIPTIONS (CONTINUED)
Pin Number/Grid Locator
Pin
Function
Input
Buffer
I/O
Description
64-Pin
80-Pin
TQFP
100-Pin 121-Pin
TQFP
TQFP
BGA
RE0
RE1
RE2
RE3
RE4
RE5
RE6
RE7
RE8
RE9
REFO
RF0
60
61
62
63
64
1
76
77
78
79
80
1
93
94
98
99
100
3
A4
B4
B3
A2
A1
D3
C1
D2
G1
G2
L8
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
—
PORTE Digital I/O.
2
2
4
3
3
5
—
—
30
58
59
34
33
31
32
35
—
—
—
—
—
—
37
36
4
13
14
36
72
73
42
41
39
40
45
44
43
—
—
75
74
47
46
6
18
19
44
87
88
52
51
49
50
55
54
53
40
39
90
89
57
56
10
11
12
14
96
97
95
1
Reference Clock Output.
PORTF Digital I/O.
B6
A6
K11
K10
L10
L11
H9
H8
J10
K6
L6
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
RF1
RF2
RF3
RF4
RF5
RF6
RF7
RF8
RF12
RF13
RG0
RG1
RG2
RG3
RG6
RG7
RG8
RG9
RG12
RG13
RG14
RG15
PORTG Digital I/O.
A5
E6
H10
J11
E3
F4
5
7
6
8
F2
8
10
—
—
—
—
F3
—
—
—
—
C3
A3
C4
B2
Legend:
TTL = TTL input buffer
ANA = Analog level input/output
ST = Schmitt Trigger input buffer
I C™ = I C/SMBus input buffer
2
2
PIC24FJDS39996F-page 24
2010-2011 Microchip Technology Inc.
PIC24FJ128GA310 FAMILY
TABLE 1-4:
PIC24FJ128GA310 FAMILY PINOUT DESCRIPTIONS (CONTINUED)
Pin Number/Grid Locator
Pin
Function
Input
Buffer
I/O
Description
64-Pin
80-Pin
TQFP
100-Pin 121-Pin
TQFP
TQFP
BGA
RP0
16
15
42
44
43
—
17
18
21
22
31
46
45
14
29
—
33
32
11
6
20
19
54
56
55
38
21
22
27
28
39
58
57
18
35
43
41
40
15
8
25
24
68
70
69
48
26
27
32
33
49
72
71
23
43
53
51
50
20
12
82
10
78
77
76
81
11
14
21
44
52
39
40
18
19
67
66
74
6
K2
K1
E9
D11
E10
K9
L1
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
Remappable Peripheral (input or output).
RP1
RP2
RP3
RP4
RP5
RP6
RP7
J3
RP8
K4
L4
RP9
RP10
RP11
RP12
RP13
RP14
RP15
RP16
RP17
RP18
RP19
RP20
RP21
RP22
RP23
RP24
RP25
RP26
RP27
RP28
RP29
RP30
RP31
RPI32
RPI33
RPI34
RPI35
RPI36
RPI37
RPI38
RPI39
RPI40
RPI41
RPI42
RPI43
L10
D9
C11
J2
K7
J10
K10
L11
H1
F2
53
4
67
6
B8
E3
B9
A10
A11
C8
F4
51
50
49
52
5
63
62
61
66
7
8
10
16
36
42
—
—
13
14
53
52
60
4
F3
12
30
34
—
—
—
—
—
—
48
—
—
—
—
—
—
H2
L8
K11
L6
K6
G1
G2
E8
E11
B11
D1
E4
E2
E1
A9
L9
Remappable Peripheral (input only).
I
I
I
I
I
I
—
5
7
I
8
I
—
64
37
9
I
79
47
I
I
Legend:
TTL = TTL input buffer
ANA = Analog level input/output
ST = Schmitt Trigger input buffer
I C™ = I C/SMBus input buffer
2
2
2010-2011 Microchip Technology Inc.
DS39996F-page 25
PIC24FJ128GA310 FAMILY
TABLE 1-4:
PIC24FJ128GA310 FAMILY PINOUT DESCRIPTIONS (CONTINUED)
Pin Number/Grid Locator
Pin
Function
Input
Buffer
I/O
Description
64-Pin
80-Pin
TQFP
100-Pin 121-Pin
TQFP
TQFP
BGA
RTCC
SCL1
42
37
32
48
36
31
4
54
47
40
60
46
39
6
68
57
58
74
56
59
10
14
20
21
22
23
24
25
43
44
49
50
51
68
69
70
71
72
41
42
76
77
78
81
82
83
84
87
57
34
33
32
6
E9
H10
H11
B11
J11
G10
E3
O
—
Real-Time Clock Alarm/Seconds Pulse Output.
I2C1 Synchronous Serial Clock Input/Output.
I2C2 Synchronous Serial Clock Input/Output.
2
I/O
I/O
I C
2
SCL2
I C
SCLKI
SDA1
2
I/O
I/O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
I C
I2C1 Data Input/Output.
I2C2 Data Input/Output.
LCD Driver Segment Outputs.
2
SDA2
I C
SEG0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
SEG1
8
10
15
16
17
18
19
20
35
36
39
40
41
54
55
56
57
58
33
34
61
62
63
66
67
68
69
72
47
29
28
27
4
F3
SEG2
11
12
13
14
15
16
29
30
31
32
33
42
43
44
45
46
27
28
49
50
51
52
53
54
55
58
37
23
22
21
—
—
—
H1
H2
J1
SEG3
SEG4
SEG5
J2
SEG6
K1
SEG7
K2
SEG8
K7
SEG9
L8
SEG10
SEG11
SEG12
SEG13
SEG14
SEG15
SEG16
SEG17
SEG18
SEG19
SEG20
SEG21
SEG22
SEG23
SEG24
SEG25
SEG26
SEG27
SEG28
SEG29
SEG30
SEG31
SEG32
SEG33
SEG34
L10
L11
K10
E9
E10
D11
C11
D9
J7
L7
A11
A10
B9
C8
B8
D7
C7
B6
H10
L5
L4
K4
D1
E2
5
8
13
18
G1
Legend:
TTL = TTL input buffer
ANA = Analog level input/output
ST = Schmitt Trigger input buffer
I C™ = I C/SMBus input buffer
2
2
PIC24FJDS39996F-page 26
2010-2011 Microchip Technology Inc.
PIC24FJ128GA310 FAMILY
TABLE 1-4:
PIC24FJ128GA310 FAMILY PINOUT DESCRIPTIONS (CONTINUED)
Pin Number/Grid Locator
Pin
Function
Input
Buffer
I/O
Description
64-Pin
80-Pin
TQFP
100-Pin 121-Pin
TQFP
TQFP
BGA
SEG35
SEG36
SEG37
SEG38
SEG39
SEG40
SEG41
SEG42
SEG43
SEG44
SEG45
SEG46
SEG47
SEG48
SEG49
SEG50
SEG51
SEG52
SEG53
SEG54
SEG55
SEG56
SEG57
SEG58
SEG59
SEG60
SEG61
SEG62
SEG63
SOSCI
SOSCO
T1CK
—
—
—
—
—
—
—
—
—
—
—
—
36
59
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
47
48
22
27
28
24
23
14
23
24
37
38
42
43
52
53
64
65
74
46
73
—
75
—
—
—
—
—
—
—
—
—
—
—
—
—
59
60
28
33
34
14
13
19
28
29
47
48
52
53
66
67
79
80
89
56
88
17
90
1
G2
L2
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
I
—
—
LCD Driver Segment Outputs.
K3
—
L9
—
K9
—
K11
J10
E11
E8
—
—
—
—
A9
—
D8
E6
—
—
J11
A6
—
—
G3
A5
—
—
B2
—
7
E4
—
9
E1
—
39
40
58
59
91
92
95
96
97
100
73
74
33
38
60
61
17
L6
—
K6
—
H11
G10
C5
B5
—
—
—
—
C4
C3
A3
—
—
—
A1
—
C10
B11
L4
ANA
ANA
ST
ST
ST
—
Secondary Oscillator/Timer1 Clock Input.
Secondary Oscillator/Timer1 Clock Output.
Timer1 Clock.
O
I
TCK
J6
I
JTAG Test Clock/Programming Clock Input.
JTAG Test Data/Programming Data Input.
JTAG Test Data Output.
TDI
G11
G9
G3
I
TDO
O
I
TMS
ST
JTAG Test Mode Select Input.
Legend:
TTL = TTL input buffer
ANA = Analog level input/output
ST = Schmitt Trigger input buffer
I C™ = I C/SMBus input buffer
2
2
2010-2011 Microchip Technology Inc.
DS39996F-page 27
PIC24FJ128GA310 FAMILY
TABLE 1-4:
PIC24FJ128GA310 FAMILY PINOUT DESCRIPTIONS (CONTINUED)
Pin Number/Grid Locator
Pin
Function
Input
Buffer
I/O
Description
64-Pin
80-Pin
TQFP
100-Pin 121-Pin
TQFP
TQFP
BGA
VBAT
VCAP
57
56
71
70
86
85
A7
B7
P
P
—
—
Back-up Battery.
External Filter Capacitor Connection (regulator
enabled).
VDD
10, 26,
38
12, 32,
48
2, 16,
37, 46,
62
C2, F8,
G5, H6,
K8
P
—
Positive Supply for Peripheral Digital Logic and I/O
Pins.
VLCAP1
VLCAP2
VREF+
5
6
7
8
11
12
29
F4
F2
K3
I
I
I
ANA
ANA
ANA
LCD Drive Charge Pump Capacitor Inputs.
—
24
Comparator/A/D Reference Voltage (low) Input
(default).
VREF-
Vss
—
23
28
L2
I
ANA
—
Comparator/A/D Reference Voltage (high) Input
(default).
9, 25, 41 11, 31,
51
15, 36, B10, F5,
45, 65, F10, G6,
P
Ground Reference for Logic and I/O Pins.
75
G7
Legend:
TTL = TTL input buffer
ANA = Analog level input/output
ST = Schmitt Trigger input buffer
I C™ = I C/SMBus input buffer
2
2
PIC24FJDS39996F-page 28
2010-2011 Microchip Technology Inc.
PIC24FJ128GA310 FAMILY
FIGURE 2-1:
RECOMMENDED
MINIMUM CONNECTIONS
2.0
2.1
GUIDELINES FOR GETTING
STARTED WITH 16-BIT
MICROCONTROLLERS
(2)
C2
VDD
Basic Connection Requirements
Getting started with the PIC24FJ128GA310 family
family of 16-bit microcontrollers requires attention to a
minimal set of device pin connections before
proceeding with development.
R1
R2
MCLR
VCAP
(1)
C1
C7
The following pins must always be connected:
PIC24FJXXXX
• All VDD and VSS pins
(see Section 2.2 “Power Supply Pins”)
VDD
VSS
VDD
(2)
(2)
C3
C6
• All AVDD and AVSS pins, regardless of whether or
not the analog device features are used
VSS
(see Section 2.2 “Power Supply Pins”)
• MCLR pin
(see Section 2.3 “Master Clear (MCLR) Pin”)
(2)
(2)
C4
C5
• VCAP pin
(see Section 2.4 “Voltage Regulator Pin (VCAP)”)
These pins must also be connected if they are being
used in the end application:
Key (all values are recommendations):
C1 through C6: 0.1 F, 20V ceramic
C7: 10 F, 6.3V or greater, tantalum or ceramic
R1: 10 kΩ
• PGECx/PGEDx pins used for In-Circuit Serial
Programming™ (ICSP™) and debugging purposes
(see Section 2.5 “ICSP Pins”)
R2: 100Ω to 470Ω
• OSCI and OSCO pins when an external oscillator
source is used
(see Section 2.6 “External Oscillator Pins”)
Note 1: See Section 2.4 “Voltage Regulator Pin
(VCAP)” for details on selecting the proper
capacitor for Vcap.
2: The example shown is for a PIC24F device
with five VDD/VSS and AVDD/AVSS pairs.
Other devices may have more or less pairs;
adjust the number of decoupling capacitors
appropriately.
Additionally, the following pins may be required:
• VREF+/VREF- pins used when external voltage
reference for analog modules is implemented
Note:
The AVDD and AVSS pins must always be
connected, regardless of whether any of
the analog modules are being used.
The minimum mandatory connections are shown in
Figure 2-1.
2010-2011 Microchip Technology Inc.
DS39996F-page 29
PIC24FJ128GA310 FAMILY
2.2
Power Supply Pins
2.3
Master Clear (MCLR) Pin
The MCLR pin provides two specific device
functions: device Reset, and device programming
and debugging. If programming and debugging are
2.2.1
DECOUPLING CAPACITORS
The use of decoupling capacitors on every pair of
power supply pins, such as VDD, VSS, AVDD and
AVSS is required.
not required in the end application,
a
direct
connection to VDD may be all that is required. The
addition of other components, to help increase the
application’s resistance to spurious Resets from
Consider the following criteria when using decoupling
capacitors:
voltage sags, may be beneficial.
A
typical
• Value and type of capacitor: A 0.1 F (100 nF),
10-20V capacitor is recommended. The capacitor
should be a low-ESR device with a resonance
frequency in the range of 200 MHz and higher.
Ceramic capacitors are recommended.
configuration is shown in Figure 2-1. Other circuit
designs may be implemented, depending on the
application’s requirements.
During programming and debugging, the resistance
and capacitance that can be added to the pin must
be considered. Device programmers and debuggers
drive the MCLR pin. Consequently, specific voltage
levels (VIH and VIL) and fast signal transitions must
not be adversely affected. Therefore, specific values
of R1 and C1 will need to be adjusted based on the
application and PCB requirements. For example, it is
recommended that the capacitor, C1, be isolated
from the MCLR pin during programming and
debugging operations by using a jumper (Figure 2-2).
The jumper is replaced for normal run-time
operations.
• Placement on the printed circuit board: The
decoupling capacitors should be placed as close
to the pins as possible. It is recommended to
place the capacitors on the same side of the
board as the device. If space is constricted, the
capacitor can be placed on another layer on the
PCB using a via; however, ensure that the trace
length from the pin to the capacitor is no greater
than 0.25 inch (6 mm).
• Handling high-frequency noise: If the board is
experiencing high-frequency noise (upward of
tens of MHz), add a second ceramic type capaci-
tor in parallel to the above described decoupling
capacitor. The value of the second capacitor can
be in the range of 0.01 F to 0.001 F. Place this
second capacitor next to each primary decoupling
capacitor. In high-speed circuit designs, consider
implementing a decade pair of capacitances as
close to the power and ground pins as possible
(e.g., 0.1 F in parallel with 0.001 F).
Any components associated with the MCLR pin
should be placed within 0.25 inch (6 mm) of the pin.
FIGURE 2-2:
EXAMPLE OF MCLR PIN
CONNECTIONS
VDD
• Maximizing performance: On the board layout
from the power supply circuit, run the power and
return traces to the decoupling capacitors first,
and then to the device pins. This ensures that the
decoupling capacitors are first in the power chain.
Equally important is to keep the trace length
between the capacitor and the power pins to a
minimum, thereby reducing PCB trace
R1
R2
MCLR
PIC24FXXXX
JP
C1
inductance.
Note 1: R1 10 k is recommended. A suggested
starting value is 10 k. Ensure that the
MCLR pin VIH and VIL specifications are met.
2.2.2
TANK CAPACITORS
On boards with power traces running longer than six
inches in length, it is suggested to use a tank capacitor
for integrated circuits including microcontrollers to
supply a local power source. The value of the tank
capacitor should be determined based on the trace
resistance that connects the power supply source to
the device, and the maximum current drawn by the
device in the application. In other words, select the tank
capacitor so that it meets the acceptable voltage sag at
the device. Typical values range from 4.7 F to 47 F.
2: R2 470 will limit any current flowing into
MCLR from the external capacitor, C, in the
event of MCLR pin breakdown, due to
Electrostatic Discharge (ESD) or Electrical
Overstress (EOS). Ensure that the MCLR pin
VIH and VIL specifications are met.
DS39996F-page 30
2010-2011 Microchip Technology Inc.
PIC24FJ128GA310 FAMILY
FIGURE 2-3:
FREQUENCY vs. ESR
PERFORMANCE FOR
SUGGESTED VCAP
2.4
Voltage Regulator Pin (VCAP)
A low-ESR (< 5Ω) capacitor is required on the VCAP pin
to stabilize the output voltage of the on-chip voltage
regulator . The VCAP pin must not be connected to VDD
and must use a capacitor of 10 µF connected to ground.
The type can be ceramic or tantalum. Suitable examples
of capacitors are shown in Table 2-1. Capacitors with
equivalent specification can be used.
10
1
0.1
The placement of this capacitor should be close to
VCAP. It is recommended that the trace length not
exceed 0.25 inch (6 mm). Refer to Section 32.0
0.01
“Electrical
Characteristics”
for
additional
information.
0.001
0.01
0.1
1
10
100
1000 10,000
Designers may use Figure 2-3 to evaluate ESR
equivalence of candidate devices.
Frequency (MHz)
Note:
Typical data measurement at 25°C, 0V DC bias.
Refer to Section 29.2 “On-Chip Voltage Regulator”
for details on connecting and using the on-chip
regulator.
.
TABLE 2-1:
Make
SUITABLE CAPACITOR EQUIVALENTS
Nominal
Part #
Base Tolerance Rated Voltage Temp. Range
Capacitance
TDK
TDK
C3216X7R1C106K
C3216X5R1C106K
10 µF
10 µF
10 µF
10 µF
10 µF
10 µF
±10%
±10%
±10%
±10%
±10%
±10%
16V
16V
16V
16V
16V
16V
-55 to 125ºC
-55 to 85ºC
-55 to 125ºC
-55 to 85ºC
-55 to 125ºC
-55 to 85ºC
Panasonic
Panasonic
Murata
ECJ-3YX1C106K
ECJ-4YB1C106K
GRM32DR71C106KA01L
GRM31CR61C106KC31L
Murata
2010-2011 Microchip Technology Inc.
DS39996F-page 31
PIC24FJ128GA310 FAMILY
2.4.1
CONSIDERATIONS FOR CERAMIC
CAPACITORS
FIGURE 2-4:
DC BIAS VOLTAGE vs.
CAPACITANCE
CHARACTERISTICS
In recent years, large value, low-voltage, surface-mount
ceramic capacitors have become very cost effective in
sizes up to a few tens of microfarad. The low-ESR, small
physical size and other properties make ceramic
capacitors very attractive in many types of applications.
10
0
-10
-20
-30
-40
-50
-60
-70
16V Capacitor
10V Capacitor
Ceramic capacitors are suitable for use with the inter-
nal voltage regulator of this microcontroller. However,
some care is needed in selecting the capacitor to
ensure that it maintains sufficient capacitance over the
intended operating range of the application.
6.3V Capacitor
-80
0
1
2
3
4
5
6
7
8
9
10 11 12
13 14 15
16 17
DC Bias Voltage (VDC)
Typical low-cost, 10 F ceramic capacitors are available
in X5R, X7R and Y5V dielectric ratings (other types are
also available, but are less common). The initial toler-
ance specifications for these types of capacitors are
often specified as ±10% to ±20% (X5R and X7R), or
-20%/+80% (Y5V). However, the effective capacitance
that these capacitors provide in an application circuit will
also vary based on additional factors, such as the
applied DC bias voltage and the temperature. The total
in-circuit tolerance is, therefore, much wider than the
initial tolerance specification.
When selecting a ceramic capacitor to be used with the
internal voltage regulator, it is suggested to select a
high-voltage rating, so that the operating voltage is a
small percentage of the maximum rated capacitor volt-
age. For example, choose a ceramic capacitor rated at
16V for the 2.5V or 1.8V core voltage. Suggested
capacitors are shown in Table 2-1.
2.5
ICSP Pins
The X5R and X7R capacitors typically exhibit satisfac-
tory temperature stability (ex: ±15% over a wide
temperature range, but consult the manufacturer’s data
sheets for exact specifications). However, Y5V capaci-
tors typically have extreme temperature tolerance
specifications of +22%/-82%. Due to the extreme tem-
perature tolerance, a 10 F nominal rated Y5V type
capacitor may not deliver enough total capacitance to
meet minimum internal voltage regulator stability and
transient response requirements. Therefore, Y5V
capacitors are not recommended for use with the
internal regulator if the application must operate over a
wide temperature range.
The PGECx and PGEDx pins are used for In-Circuit
Serial Programming (ICSP) and debugging purposes.
It is recommended to keep the trace length between
the ICSP connector and the ICSP pins on the device as
short as possible. If the ICSP connector is expected to
experience an ESD event, a series resistor is recom-
mended, with the value in the range of a few tens of
ohms, not to exceed 100Ω.
Pull-up resistors, series diodes and capacitors on the
PGECx and PGEDx pins are not recommended as they
will interfere with the programmer/debugger communi-
cations to the device. If such discrete components are
an application requirement, they should be removed
from the circuit during programming and debugging.
Alternatively, refer to the AC/DC characteristics and
timing requirements information in the respective
device Flash programming specification for information
on capacitive loading limits and pin input voltage high
(VIH) and input low (VIL) requirements.
In addition to temperature tolerance, the effective
capacitance of large value ceramic capacitors can vary
substantially, based on the amount of DC voltage
applied to the capacitor. This effect can be very signifi-
cant, but is often overlooked or is not always
documented.
Typical DC bias voltage vs. capacitance graph for X7R
type capacitors is shown in Figure 2-4.
For device emulation, ensure that the “Communication
Channel Select” (i.e., PGECx/PGEDx pins),
programmed into the device, matches the physical
connections for the ICSP to the Microchip
debugger/emulator tool.
For more information on available Microchip
development tools connection requirements, refer to
Section 30.0 “Development Support”.
DS39996F-page 32
2010-2011 Microchip Technology Inc.
PIC24FJ128GA310 FAMILY
FIGURE 2-5:
SUGGESTED
2.6
External Oscillator Pins
PLACEMENT OF THE
OSCILLATOR CIRCUIT
Many microcontrollers have options for at least two
oscillators: a high-frequency primary oscillator and a
low-frequency
secondary
oscillator
(refer to
Single-Sided and In-line Layouts:
Section 9.0 “Oscillator Configuration” for details).
Copper Pour
(tied to ground)
Primary Oscillator
Crystal
The oscillator circuit should be placed on the same
side of the board as the device. Place the oscillator
circuit close to the respective oscillator pins with no
more than 0.5 inch (12 mm) between the circuit
components and the pins. The load capacitors should
be placed next to the oscillator itself, on the same side
of the board.
DEVICE PINS
Primary
OSCI
OSCO
GND
Oscillator
C1
C2
`
`
Use a grounded copper pour around the oscillator cir-
cuit to isolate it from surrounding circuits. The
grounded copper pour should be routed directly to the
MCU ground. Do not run any signal traces or power
traces inside the ground pour. Also, if using a two-sided
board, avoid any traces on the other side of the board
where the crystal is placed.
SOSCO
SOSC I
Secondary
Oscillator
Crystal
`
Layout suggestions are shown in Figure 2-5. In-line
packages may be handled with a single-sided layout
that completely encompasses the oscillator pins. With
fine-pitch packages, it is not always possible to com-
pletely surround the pins and components. A suitable
solution is to tie the broken guard sections to a mirrored
ground layer. In all cases, the guard trace(s) must be
returned to ground.
Sec Oscillator: C2
Sec Oscillator: C1
Fine-Pitch (Dual-Sided) Layouts:
Top Layer Copper Pour
(tied to ground)
In planning the application’s routing and I/O assign-
ments, ensure that adjacent port pins, and other
signals in close proximity to the oscillator, are benign
(i.e., free of high frequencies, short rise and fall times
and other similar noise).
Bottom Layer
Copper Pour
(tied to ground)
OSCO
For additional information and design guidance on
oscillator circuits, please refer to these Microchip
Application Notes, available at the corporate web site
(www.microchip.com):
C2
Oscillator
Crystal
GND
• AN826, “Crystal Oscillator Basics and Crystal
Selection for rfPIC™ and PICmicro® Devices”
C1
• AN849, “Basic PICmicro® Oscillator Design”
OSCI
• AN943, “Practical PICmicro® Oscillator Analysis
and Design”
• AN949, “Making Your Oscillator Work”
DEVICE PINS
2010-2011 Microchip Technology Inc.
DS39996F-page 33
PIC24FJ128GA310 FAMILY
If your application needs to use certain A/D pins as
analog input pins during the debug session, the user
application must modify the appropriate bits during
initialization of the A/D module, as follows:
2.7
Configuration of Analog and
Digital Pins During ICSP
Operations
If an ICSP compliant emulator is selected as a debug-
ger, it automatically initializes all of the A/D input pins
(ANx) as “digital” pins. Depending on the particular
device, this is done by setting all bits in the ADnPCFG
register(s), or clearing all bit in the ANSx registers.
• For devices with an ADnPCFG register, clear the
bits corresponding to the pin(s) to be configured
as analog. Do not change any other bits, particu-
larly those corresponding to the PGECx/PGEDx
pair, at any time.
All PIC24F devices will have either one or more
ADnPCFG registers or several ANSx registers (one for
each port); no device will have both. Refer to
Section 11.2 “Configuring Analog Port Pins
(ANSx)” for more specific information.
• For devices with ANSx registers, set the bits
corresponding to the pin(s) to be configured as
analog. Do not change any other bits, particularly
those corresponding to the PGECx/PGEDx pair,
at any time.
The bits in these registers that correspond to the A/D
pins that initialized the emulator must not be changed
by the user application firmware; otherwise,
communication errors will result between the debugger
and the device.
When a Microchip debugger/emulator is used as a
programmer, the user application firmware must
correctly configure the ADnPCFG or ANSx registers.
Automatic initialization of this register is only done
during debugger operation. Failure to correctly
configure the register(s) will result in all A/D pins being
recognized as analog input pins, resulting in the port
value being read as a logic ‘0’, which may affect user
application functionality.
2.8
Unused I/Os
Unused I/O pins should be configured as outputs and
driven to a logic low state. Alternatively, connect a 1 kΩ
to 10 kΩ resistor to VSS on unused pins and drive the
output to logic low.
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The core supports Inherent (no operand), Relative,
Literal and Memory Direct Addressing modes, along
3.0
CPU
Note:
This data sheet summarizes the features of
this group of PIC24F devices. It is not
with three other groups of addressing modes. All
modes support Register Direct and various Register
Indirect modes. Each group offers up to seven
addressing modes. Instructions are associated with
predefined addressing modes depending upon their
functional requirements.
intended to be a comprehensive reference
source. For more information, refer to the
“PIC24F Family Reference Manual”,
Section 44. “CPU with Extended Data
Space (EDS)” (DS39732). The information
in this data sheet supersedes the
information in the FRM.
For most instructions, the core is capable of executing
a data (or program data) memory read, a working reg-
ister (data) read, a data memory write and a program
(instruction) memory read per instruction cycle. As a
result, three parameter instructions can be supported,
allowing trinary operations (that is, A + B = C) to be
executed in a single cycle.
The PIC24F CPU has a 16-bit (data) modified Harvard
architecture with an enhanced instruction set and a
24-bit instruction word with a variable length opcode
field. The Program Counter (PC) is 23 bits wide and
addresses up to 4M instructions of user program
memory space. A single-cycle instruction prefetch
mechanism is used to help maintain throughput and
provides predictable execution. All instructions execute
in a single cycle, with the exception of instructions that
change the program flow, the double-word move
(MOV.D) instruction and the table instructions.
Overhead-free program loop constructs are supported
using the REPEATinstructions, which are interruptible
at any point.
A high-speed, 17-bit x 17-bit multiplier has been
included to significantly enhance the core arithmetic
capability and throughput. The multiplier supports
Signed, Unsigned and Mixed mode, 16-bit x 16-bit or
8-bit
x 8-bit, integer multiplication. All multiply
instructions execute in a single cycle.
The 16-bit ALU has been enhanced with integer divide
assist hardware that supports an iterative non-restoring
divide algorithm. It operates in conjunction with the
REPEATinstruction looping mechanism and a selection
of iterative divide instructions to support 32-bit (or
16-bit), divided by 16-bit, integer signed and unsigned
division. All divide operations require 19 cycles to
complete but are interruptible at any cycle boundary.
PIC24F devices have sixteen, 16-bit working registers
in the programmer’s model. Each of the working
registers can act as a data, address or address offset
register. The 16th working register (W15) operates as a
Software Stack Pointer for interrupts and calls.
The PIC24F has a vectored exception scheme with up
to 8 sources of non-maskable traps and up to 118 inter-
rupt sources. Each interrupt source can be assigned to
one of seven priority levels.
The lower 32 Kbytes of the data space can be
accessed linearly. The upper 32 Kbytes of the data
space are referred to as extended data space to which
the extended data RAM, EPMP memory space or
program memory can be mapped.
A block diagram of the CPU is shown in Figure 3-1.
The Instruction Set Architecture (ISA) has been
significantly enhanced beyond that of the PIC18, but
maintains an acceptable level of backward compatibil-
ity. All PIC18 instructions and addressing modes are
supported, either directly, or through simple macros.
Many of the ISA enhancements have been driven by
compiler efficiency needs.
3.1
Programmer’s Model
The programmer’s model for the PIC24F is shown in
Figure 3-2. All registers in the programmer’s model are
memory mapped and can be manipulated directly by
instructions. A description of each register is provided
in Table 3-1. All registers associated with the
programmer’s model are memory mapped.
2010-2011 Microchip Technology Inc.
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FIGURE 3-1:
PIC24F CPU CORE BLOCK DIAGRAM
EDS and Table
Data Access
Control Block
Data Bus
Interrupt
Controller
16
16
16
8
Data Latch
23
Data RAM
Up to 0x7FFF
16
PCH
Program Counter
PCL
23
Address
Latch
Loop
Control
Logic
Stack
Control
Logic
23
16
RAGU
WAGU
Address Latch
Program Memory/
Extended Data
Space
EA MUX
Address Bus
24
Data Latch
ROM Latch
16
16
Instruction
Decode and
Control
Instruction Reg
Control Signals
to Various Blocks
Hardware
Multiplier
16 x 16
W Register Array
Divide
Support
16
16-Bit ALU
16
To Peripheral Modules
TABLE 3-1:
CPU CORE REGISTERS
Register(s) Name
Description
W0 through W15
PC
Working Register Array
23-Bit Program Counter
ALU STATUS Register
SR
SPLIM
Stack Pointer Limit Value Register
Table Memory Page Address Register
Repeat Loop Counter Register
CPU Control Register
TBLPAG
RCOUNT
CORCON
DISICNT
DSRPAG
DSWPAG
Disable Interrupt Count Register
Data Space Read Page Register
Data Space Write Page Register
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FIGURE 3-2:
PROGRAMMER’S MODEL
15
0
W0 (WREG)
W1
Divider Working Registers
W2
Multiplier Registers
W3
W4
W5
W6
W7
Working/Address
Registers
W8
W9
W10
W11
W12
W13
W14
W15
Frame Pointer
Stack Pointer
0
Stack Pointer Limit
Value Register
0
SPLIM
22
0
0
PC
Program Counter
7
0
0
Table Memory Page
Address Register
TBLPAG
9
Data Space Read Page Register
Data Space Write Page Register
DSRPAG
DSWPAG
8
0
0
15
15
Repeat Loop Counter
Register
RCOUNT
SRH
SRL
0
IPL
— — — — — — —
ALU STATUS Register (SR)
DC
RA N OV Z C
2
1 0
15
0
— — — — — — — — — — — — IPL3
CPU Control Register (CORCON)
Disable Interrupt Count Register
———
13
0
DISICNT
Registers or bits are shadowed for PUSH.Sand POP.Sinstructions.
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3.2
CPU Control Registers
REGISTER 3-1:
SR: ALU STATUS REGISTER
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
R/W-0
DC
bit 15
bit 8
R/W-0(1)
IPL2(2)
bit 7
R/W-0(1)
IPL1(2)
R/W-0(1)
IPL0(2)
R-0
RA
R/W-0
N
R/W-0
OV
R/W-0,
Z
R/W-0
C
bit 0
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
-n = Value at POR
bit 15-9
bit 8
Unimplemented: Read as ‘0’
DC: ALU Half Carry/Borrow bit
1= A carry out from the 4th low-order bit (for byte-sized data) or 8th low-order bit (for word-sized data)
of the result occurred
0= No carry out from the 4th or 8th low-order bit of the result has occurred
bit 7-5
IPL<2:0>: CPU Interrupt Priority Level Status bits(1,2)
111= CPU interrupt priority level is 7 (15); user interrupts are disabled
110= CPU interrupt priority level is 6 (14)
101= CPU interrupt priority level is 5 (13)
100= CPU interrupt priority level is 4 (12)
011= CPU interrupt priority level is 3 (11)
010= CPU interrupt priority level is 2 (10)
001= CPU interrupt priority level is 1 (9)
000= CPU interrupt priority level is 0 (8)
bit 4
bit 3
bit 2
bit 1
bit 0
RA: REPEATLoop Active bit
1= REPEATloop in progress
0= REPEATloop not in progress
N: ALU Negative bit
1= Result was negative
0= Result was not negative (zero or positive)
OV: ALU Overflow bit
1= Overflow occurred for signed (2’s complement) arithmetic in this arithmetic operation
0= No overflow has occurred
Z: ALU Zero bit
1= An operation, which affects the Z bit, has set it at some time in the past
0= The most recent operation, which affects the Z bit, has cleared it (i.e., a non-zero result)
C: ALU Carry/Borrow bit
1= A carry out from the Most Significant bit of the result occurred
0= No carry out from the Most Significant bit of the result occurred
Note 1: The IPL Status bits are read-only when NSTDIS (INTCON1<15>) = 1.
2: The IPL Status bits are concatenated with the IPL3 (CORCON<3>) bit to form the CPU Interrupt Priority
Level (IPL). The value in parentheses indicates the IPL when IPL3 = 1.
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REGISTER 3-2:
CORCON: CPU CORE CONTROL REGISTER
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
bit 15
bit 8
bit 0
U-0
—
U-0
—
U-0
—
U-0
—
R/C-0
IPL3(1)
R-1
r
U-0
—
U-0
—
bit 7
Legend:
C = Clearable bit
W = Writable bit
‘1’ = Bit is set
r = Reserved bit
R = Readable bit
-n = Value at POR
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-4
bit 3
Unimplemented: Read as ‘0’
IPL3: CPU Interrupt Priority Level Status bit(1)
1= CPU interrupt priority level is greater than 7
0= CPU interrupt priority level is 7 or less
bit 2
Reserved: Read as ‘1’
bit 1-0
Unimplemented: Read as ‘0’
Note 1: The IPL3 bit is concatenated with the IPL<2:0> bits (SR<7:5>) to form the CPU interrupt priority level; see
Register 3-1 for bit description.
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3.3.2
DIVIDER
3.3
Arithmetic Logic Unit (ALU)
The divide block supports signed and unsigned integer
divide operations with the following data sizes:
The PIC24F ALU is 16 bits wide and is capable of addi-
tion, subtraction, bit shifts and logic operations. Unless
otherwise mentioned, arithmetic operations are 2’s
complement in nature. Depending on the operation, the
ALU may affect the values of the Carry (C), Zero (Z),
Negative (N), Overflow (OV) and Digit Carry (DC)
Status bits in the SR register. The C and DC Status bits
operate as Borrow and Digit Borrow bits, respectively,
for subtraction operations.
1. 32-bit signed/16-bit signed divide
2. 32-bit unsigned/16-bit unsigned divide
3. 16-bit signed/16-bit signed divide
4. 16-bit unsigned/16-bit unsigned divide
The quotient for all divide instructions ends up in W0
and the remainder in W1. Sixteen-bit signed and
unsigned DIV instructions can specify any W register
for both the 16-bit divisor (Wn), and any W register
(aligned) pair (W(m + 1):Wm) for the 32-bit dividend.
The divide algorithm takes one cycle per bit of divisor,
so both 32-bit/16-bit and 16-bit/16-bit instructions take
the same number of cycles to execute.
The ALU can perform 8-bit or 16-bit operations,
depending on the mode of the instruction that is used.
Data for the ALU operation can come from the W
register array, or data memory, depending on the
addressing mode of the instruction. Likewise, output
data from the ALU can be written to the W register array
or a data memory location.
3.3.3
MULTI-BIT SHIFT SUPPORT
The PIC24F CPU incorporates hardware support for
both multiplication and division. This includes a
dedicated hardware multiplier and support hardware
for 16-bit divisor division.
The PIC24F ALU supports both single bit and
single-cycle, multi-bit arithmetic and logic shifts.
Multi-bit shifts are implemented using a shifter block,
capable of performing up to a 15-bit arithmetic right
shift, or up to a 15-bit left shift, in a single cycle. All
multi-bit shift instructions only support Register Direct
Addressing for both the operand source and result
destination.
3.3.1
MULTIPLIER
The ALU contains a high-speed, 17-bit x 17-bit
multiplier. It supports unsigned, signed or mixed sign
operation in several multiplication modes:
A full summary of instructions that use the shift
operation is provided in Table 3-2.
1. 16-bit x 16-bit signed
2. 16-bit x 16-bit unsigned
3. 16-bit signed x 5-bit (literal) unsigned
4. 16-bit unsigned x 16-bit unsigned
5. 16-bit unsigned x 5-bit (literal) unsigned
6. 16-bit unsigned x 16-bit signed
7. 8-bit unsigned x 8-bit unsigned
TABLE 3-2:
Instruction
INSTRUCTIONS THAT USE THE SINGLE BIT AND MULTI-BIT SHIFT OPERATION
Description
ASR
SL
Arithmetic shift right source register by one or more bits.
Shift left source register by one or more bits.
LSR
Logical shift right source register by one or more bits.
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from either the 23-bit Program Counter (PC) during pro-
gram execution, or from table operation or data space
remapping, as described in Section 4.3 “Interfacing
Program and Data Memory Spaces”.
4.0
MEMORY ORGANIZATION
As Harvard architecture devices, PIC24F micro-
controllers feature separate program and data memory
spaces and busses. This architecture also allows direct
access of program memory from the data space during
code execution.
User access to the program memory space is restricted
to the lower half of the address range (000000h to
7FFFFFh). The exception is the use of TBLRD/TBLWT
operations, which use TBLPAG<7> to permit access to
the Configuration bits and Device ID sections of the
configuration memory space.
4.1
Program Memory Space
The program address memory space of the
PIC24FJ128GA310 family devices is 4M instructions.
The space is addressable by a 24-bit value derived
Memory maps for the PIC24FJ128GA310 family of
devices are shown in Figure 4-1.
FIGURE 4-1:
PROGRAM SPACE MEMORY MAP FOR PIC24FJ128GA310 FAMILY DEVICES
PIC24FJ64GA3XX
PIC24F128GA3XX
000000h
000002h
000004h
GOTOInstruction
Reset Address
GOTOInstruction
Reset Address
Interrupt Vector Table
Reserved
Interrupt Vector Table
0000FEh
000100h
000104h
Reserved
Alternate Vector Table
Alternate Vector Table
0001FEh
000200h
User Flash
Program Memory
(22K instructions)
User Flash
Program Memory
(44K instructions)
00ABFEh
00AC00h
Flash Config Words
0157FEh
015800h
Flash Config Words
Unimplemented
Unimplemented
Read ‘0’
Read ‘0’
7FFFFEh
800000h
Reserved
Reserved
F7FFFEh
F80000h
Device Config Registers
Reserved
Device Config Registers
Reserved
F8000Eh
F80010h
FEFFFEh
FF0000h
DEVID (2)
DEVID (2)
FFFFFEh
Note:
Memory areas are not shown to scale.
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4.1.1
PROGRAM MEMORY
ORGANIZATION
4.1.3
FLASH CONFIGURATION WORDS
In PIC24FJ128GA310 family devices, the top four words
of on-chip program memory are reserved for configura-
tion information. On device Reset, the configuration
information is copied into the appropriate Configuration
register. The addresses of the Flash Configuration Word
for devices in the PIC24FJ128GA310 family are shown
in Table 4-1. Their location in the memory map is shown
with the other memory vectors in Figure 4-1.
The program memory space is organized in
word-addressable blocks. Although it is treated as
24 bits wide, it is more appropriate to think of each
address of the program memory as a lower and upper
word, with the upper byte of the upper word being
unimplemented. The lower word always has an even
address, while the upper word has an odd address
(Figure 4-2).
The Configuration Words in program memory are a
compact format. The actual Configuration bits are
mapped in several different registers in the configuration
memory space. Their order in the Flash Configuration
Words does not reflect a corresponding arrangement in
the configuration space. Additional details on the device
Configuration Words are provided in Section 29.0
“Special Features”.
Program memory addresses are always word-aligned
on the lower word and addresses are incremented or
decremented by two during code execution. This
arrangement also provides compatibility with data
memory space addressing and makes it possible to
access data in the program memory space.
4.1.2
HARD MEMORY VECTORS
TABLE 4-1:
FLASH CONFIGURATION
WORDS FOR
PIC24FJ128GA310 FAMILY
DEVICES
All PIC24F devices reserve the addresses between
000000h and 000200h for hard-coded program execu-
tion vectors. A hardware Reset vector is provided to
redirect code execution from the default value of the
PC on device Reset to the actual start of code. A GOTO
instruction is programmed by the user at 000000h with
the actual address for the start of code at 000002h.
Program
Configuration Word
Memory
Device
Addresses
(Words)
PIC24F devices also have two interrupt vector tables,
located from 000004h to 0000FFh and 000100h to
0001FFh. These vector tables allow each of the many
device interrupt sources to be handled by separate
ISRs. A more detailed discussion of the interrupt vector
tables is provided in Section 8.1 “Interrupt Vector
Table”.
PIC24FJ64GA3XX
22,016 00ABF8h:00ABFEh
PIC24FJ128GA3XX
44,032 0157F8h:0157FEh
FIGURE 4-2:
PROGRAM MEMORY ORGANIZATION
least significant word
8
msw
Address
PC Address
(lsw Address)
most significant word
23
16
0
0x000000
0x000002
00000000
0x000001
0x000003
0x000005
0x000007
00000000
00000000
0x000004
0x000006
00000000
Program Memory
‘Phantom’ Byte
(read as ‘0’)
Instruction Width
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The upper half of data memory address space (8000h to
FFFFh) is used as a window into the Extended Data
Space (EDS). This allows the microcontroller to directly
access a greater range of data beyond the standard
16-bit address range. EDS is discussed in detail in
Section 4.2.5 “Extended Data Space (EDS)”.
4.2
Data Memory Space
Note:
This data sheet summarizes the features of
this group of PIC24F devices. It is not
intended to be a comprehensive reference
source. For more information, refer to the
“PIC24F Family Reference Manual”,
Section 45. “Data Memory with
Extended Data Space (EDS)” (DS39733).
The information in this data sheet
supersedes the information in the FRM.
The lower half of DS is compatible with previous PIC24F
microcontrollers without EDS. All PIC24FJ128GA310
family devices implement 8 Kbytes of data RAM in the
lower half of DS, from 0800h to 27FFh.
4.2.1
DATA SPACE WIDTH
The PIC24F core has a 16-bit wide data memory space,
addressable as a single linear range. The data space is
accessed using two Address Generation Units (AGUs),
one each for read and write operations. The data space
memory map is shown in Figure 4-3.
The data memory space is organized in
byte-addressable, 16-bit wide blocks. Data is aligned
in data memory and registers as 16-bit words, but all
data space EAs resolve to bytes. The Least Significant
Bytes (LSBs) of each word have even addresses, while
the Most Significant Bytes (MSBs) have odd
addresses.
The 16-bit wide data addresses in the data memory
space point to bytes within the Data Space (DS). This
gives a DS address range of 64 Kbytes or 32K words.
The lower half (0000h to 7FFFh) is used for
implemented (on-chip) memory addresses.
FIGURE 4-3:
DATA SPACE MEMORY MAP FOR PIC24FJ128GA310 FAMILY DEVICES
MSB
LSB
Address
MSB
LSB
Address
0000h
0001h
SFR
Space
SFR Space
07FFh
0801h
07FEh
0800h
Near
Data Space
1FFFh
2001h
1FFEh
2000h
8 Kbytes Data RAM
Unimplemented
(1)
Lower 32 Kbytes
Data Space
2800h
2801h
EDS Page 0x1
(32 Kbytes)
Internal Extended
Data RAM (66 Kbytes)
EDS Page 0x2
(32 Kbytes)
7FFFh
8001h
7FFEh
8000h
EPMP Memory Space
EDS Page 0x3 (2 Kbytes)
EDS Page 0x4
EDS Window
Upper 32 Kbytes
Data Space
EDS Page 0x1FF
EDS Page 0x200
Program Space Visibility
Area to Access Lower
Word of Program Memory
EDS Page 0x2FF
EDS Page 0x300
FFFFh
FFFEh
Program Space Visibility
Area to Access Upper
Word of Program Memory
EDS Page 0x3FF
Note:
Memory areas not shown to scale.
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A Sign-Extend instruction (SE) is provided to allow
users to translate 8-bit signed data to 16-bit signed
values. Alternatively, for 16-bit unsigned data, users
can clear the MSB of any W register by executing a
Zero-Extend (ZE) instruction on the appropriate
address.
4.2.2
DATA MEMORY ORGANIZATION
AND ALIGNMENT
To maintain backward compatibility with PIC® MCUs and
improve data space memory usage efficiency, the
PIC24F instruction set supports both word and byte
operations. As a consequence of byte accessibility, all
EA calculations are internally scaled to step through
word-aligned memory. For example, the core recognizes
that Post-Modified Register Indirect Addressing mode
[Ws++] will result in a value of Ws + 1 for byte operations
and Ws + 2 for word operations.
Although most instructions are capable of operating on
word or byte data sizes, it should be noted that some
instructions operate only on words.
4.2.3
NEAR DATA SPACE
The 8-Kbyte area between 0000h and 1FFFh is
referred to as the near data space. Locations in this
space are directly addressable via a 13-bit absolute
address field within all memory direct instructions. The
remainder of the data space is addressable indirectly.
Additionally, the whole data space is addressable using
MOV instructions, which support Memory Direct
Addressing with a 16-bit address field.
Data byte reads will read the complete word, which
contains the byte, using the LSB of any EA to deter-
mine which byte to select. The selected byte is placed
onto the LSB of the data path. That is, data memory
and registers are organized as two parallel, byte-wide
entities with shared (word) address decode but
separate write lines. Data byte writes only write to the
corresponding side of the array or register which
matches the byte address.
4.2.4
SPECIAL FUNCTION REGISTER
(SFR) SPACE
All word accesses must be aligned to an even address.
Mis-aligned word data fetches are not supported, so
care must be taken when mixing byte and word
operations or translating from 8-bit MCU code. If a
misaligned read or write is attempted, an address error
trap will be generated. If the error occurred on a read,
the instruction underway is completed; if it occurred on
a write, the instruction will be executed but the write will
not occur. In either case, a trap is then executed, allow-
ing the system and/or user to examine the machine
state prior to execution of the address Fault.
The first 2 Kbytes of the near data space, from 0000h
to 07FFh, are primarily occupied with Special Function
Registers (SFRs). These are used by the PIC24F core
and peripheral modules for controlling the operation of
the device.
SFRs are distributed among the modules that they con-
trol and are generally grouped together by module.
Much of the SFR space contains unused addresses;
these are read as ‘0’. A diagram of the SFR space,
showing where the SFRs are actually implemented, is
shown in Table 4-2. Each implemented area indicates
a 32-byte region where at least one address is imple-
mented as an SFR. A complete list of implemented
SFRs, including their addresses, is shown in Tables 4-3
through 4-34.
All byte loads into any W register are loaded into the
LSB. The Most Significant Byte (MSB) is not modified.
TABLE 4-2:
IMPLEMENTED REGIONS OF SFR DATA SPACE
SFR Space Address
xx00
xx20
xx40
xx60
xx80
xxA0
xxC0
xxE0
000h
100h
200h
300h
400h
500h
600h
700h
Core
ICN
Interrupts
—
—
Timers
Capture
—
Compare
UART
DMA
I2C™
UART
SPI/UART
—
—
—
I/O
A/D/CTMU
—
—
—
—
—
—
—
—
—
—
—
ANA
—
LCD
—
LCD
EPMP
—
RTC/CMP
—
CRC
System
—
PPS
—
NVM/PMD
—
—
—
—
Legend: — = No implemented SFRs in this block
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TABLE 4-3:
CPU CORE REGISTERS MAP
All
Resets
File Name
Addr
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
WREG0
WREG1
WREG2
WREG3
WREG4
WREG5
WREG6
WREG7
WREG8
WREG9
WREG10
WREG11
WREG12
WREG13
WREG14
WREG15
SPLIM
0000
0002
0004
0006
0008
000A
000C
000E
0010
0012
0014
0016
0018
001A
001C
001E
0020
002E
0030
0032
0034
0036
0042
0044
0052
0054
Working Register 0
Working Register 1
Working Register 2
Working Register 3
Working Register 4
Working Register 5
Working Register 6
Working Register 7
Working Register 8
Working Register 9
Working Register 10
Working Register 11
Working Register 12
Working Register 13
Working Register 14
Working Register 15
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0800
xxxx
0000
0000
0001
0001
xxxx
0000
0004
xxxx
0000
Stack Pointer Limit Value Register
Program Counter Low Word Register
PCL
PCH
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Program Counter Register High Byte
Extended Data Space Read Page Address Register
Extended Data Space Write Page Address Register
DSRPAG
DSWPAG
RCOUNT
SR
—
Repeat Loop Counter Register
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
DC
—
IPL2
—
IPL1
—
IPL0
—
RA
—
N
OV
r
Z
C
CORCON
DISICNT
TBLPAG
IPL3
—
—
Disable Interrupts Counter Register
Table Memory Page Address Register
—
—
—
—
—
—
Legend: — = unimplemented, read as ‘0’; r = reserved, do not modify. Reset values are shown in hexadecimal.
TABLE 4-4:
ICN REGISTER MAP
File
Addr
Name
All
Resets
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
—
—
CNPD1 0056 CN15PDE
CNPD2 0058 CN31PDE
CN14PDE
CN30PDE
CN13PDE
CN29PDE
CN12PDE
CN28PDE
CN11PDE
CN10PDE
CN9PDE
CN8PDE
CN7PDE
CN6PDE
CN5PDE
CN4PDE
CN3PDE
CN2PDE
0000
(1)
(1)
(1)
CN27PDE CN26PDE CN25PDE CN24PDE
CN23PDE
CN22PDE CN21PDE CN20PDE CN19PDE
CN18PDE CN17PDE CN16PDE 0000
(2)
(1)
(1)
(1)
(1)
(1)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
CNPD3 005A CN47PDE(1) CN46PDE
CNPD4 005C CN63PDE CN62PDE
CNPD5 005E CN79PDE(2) CN78PDE
CN45PDE
CN44PDE
CN43PDE CN42PDE CN41PDE CN40PDE
CN39PDE
CN55PDE
CN71PDE
—
CN38PDE
CN37PDE CN36PDE CN35PDE
CN34PDE
CN33PDE
CN32PDE 0000
(2)
CN61PDE
CN60PDE
CN59PDE CN58PDE CN57PDE CN56PDE
CN54PDE
CN70PDE
—
CN53PDE CN52PDE CN51PDE
CN50PDE CN49PDE CN48PDE
0000
(1)
(1)
(2)
(2)
(1)
(1)
(1)
CN77PDE
—
CN76PDE
—
CN75PDE CN74PDE
CN73PDE CN72PDE
CN69PDE CN68PDE CN67PDE
CN66PDE
CN82PDE
CN2IE
CN65PDE CN64PDE 0000
(1)
(2)
(2)
(2)
CNPD6 0060
CNEN1 0062
CNEN2 0064
—
—
—
—
—
—
—
CN84PDE CN83PDE
CN4IE CN3IE
CN81PDE CN80PDE
0000
0000
0000
0000
0000
0000
0000
0000
CN15IE
CN31IE
CN14IE
CN30IE
CN13IE
CN29IE
CN12IE
CN28IE
CN11IE
CN27IE
CN10IE
CN26IE
CN9IE
CN25IE
CN8IE
CN24IE
CN7IE
CN6IE
CN5IE
—
—
(1)
(1)
(1)
CN23IE
CN22IE
CN21IE
CN37IE
CN20IE
CN36IE
CN19IE
CN35IE
CN18IE
CN17IE
CN16IE
CN32IE
(1)
(1)
(1)
(1)
(1)
(1)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
CNEN3 0066 CN47IE(1)
CNEN4 0068 CN63IE
CNEN5 006A CN79IE(2)
CNEN6 006C
CN46IE
CN62IE
CN45IE
CN61IE
CN44IE
CN60IE
CN43IE
CN59IE
CN42IE
CN58IE
CN41IE
CN57IE
CN73IE
—
CN40IE
CN56IE
CN72IE
—
CN39IE
CN38IE
CN34IE
CN50IE
CN33IE
CN49IE
CN65IE
(2)
CN55IE
CN71IE
—
CN54IE
CN70IE
—
CN53IE
CN69IE
—
CN52IE
CN68IE
CN84IE
CN4PUE
CN51IE
CN48IE
CN64IE
(1)
(1)
(2)
(2)
(1)
(1)
(1)
CN78IE
—
CN77IE
—
CN76IE
—
CN75IE
—
CN74IE
—
CN67IE
CN83IE
CN66IE
(1)
(2)
(2)
(2)
—
CN82IE
CN2PUE
CN81IE
—
CN80IE
—
CNPU1 006E CN15PUE
CN14PUE
CN30PUE
CN13PUE
CN29PUE
CN12PUE
CN28PUE
CN11PUE
CN10PUE
CN9PUE
CN8PUE
CN7PUE
CN23PUE
CN6PUE
CN5PUE
CN3PUE
(1)
(1)
(1)
CNPU2 0070 CN31PUE
CN27PUE CN26PUE CN25PUE CN24PUE
CN22PUE CN21PUE CN20PUE CN19PUE
CN18PUE CN17PUE CN16PUE 0000
(1)
(1)
(1)
(1)
(1)
(1)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
CNPU3 0072 CN47PUE(1) CN46PUE
CN45PUE
CN44PUE
CN43PUE CN42PUE CN41PUE CN40PUE
CN39PUE
CN55PUE
CN71PUE
—
CN38PUE
CN37PUE CN36PUE CN35PUE
CN34PUE
CN33PUE
CN32PUE 0000
(2)
CNPU4 0074 CN63PUE
CN62PUE
CN61PUE
CN60PUE
CN59PUE CN58PUE CN57PUE CN56PUE
CN54PUE
CN70PUE
—
CN53PUE CN52PUE CN51PUE
CN50PUE CN49PUE CN48PUE
0000
(1)
(1)
(2)
(2)
(1)
(1)
(1)
CNPU5 0076 CN79PUE(2) CN78PUE
CN77PUE
—
CN76PUE
—
CN75PUE CN74PUE
CN73PUE CN72PUE
CN69PUE CN68PUE CN67PUE
CN66PUE
CN82PUE
CN65PUE CN64PUE 0000
(1)
(2)
(2)
(2)
CNPU6 0078
—
—
—
—
—
—
—
CN84PUE CN83PUE
CN81PUE CN80PUE
0000
Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1: These bits are unimplemented in 64-pin devices, read as ‘0’.
2: These bits are unimplemented in 64-pin and 80-pin devices, read as ‘0’.
TABLE 4-5:
INTERRUPT CONTROLLER REGISTER MAP
File
Addr
Name
All
Resets
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
INTCON1 0080 NSTDIS
—
DISI
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
MATHERR ADDRERR STKERR OSCFAIL
—
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
4444
INTCON2
IFS0
0082
0084
0086
0088
008A
008C
008E
0090
0092
0094
0096
0098
009A
009C
009E
00A0
00A2
00A4
00A6
00A8
00AA
00AC
00AE
00B0
00B2
00B4
00B6
00B8
00BA
00BC
00BE
00C2
ALTIVT
—
INT4EP
DMA0IF
INT1IF
DMA3IF
—
INT3EP
T1IF
CNIF
—
INT2EP
OC1IF
CMIF
—
INT1EP
IC1IF
INT0EP
INT0IF
DMA1IF
U2RXIF
DMA4IF
RTCIF
—
AD1IF
INT2IF
PMPIF
DMA5IF
CTMUIF
—
U1TXIF
T5IF
—
U1RXIF
T4IF
OC7IF
—
SPI1IF
OC4IF
OC6IF
—
SPF1IF
OC3IF
OC5IF
—
T3IF
T2IF
—
OC2IF
IC7IF
IC4IF
INT4IF
—
IC2IF
—
IFS1
U2TXIF
—
DMA2IF
IC6IF
—
MI2C1IF SI2C1IF
IFS2
IC5IF
—
IC3IF
INT3IF
—
SPI2IF
SPF2IF
—
IFS3
—
—
—
MI2C2IF SI2C2IF
IFS4
—
—
—
—
—
LVDIF
U4RXIF
—
—
—
CRCIF
U3TXIF
—
U2ERIF
U3RXIF
—
U1ERIF
U3ERIF
—
—
IFS5
—
—
—
—
—
U4TXIF
—
U4ERIF
—
—
—
—
—
IFS6
—
—
—
—
—
—
—
—
LCDIF
—
—
IFS7
—
—
—
—
—
—
—
—
—
—
JTAGIF
IC2IE
—
—
—
—
—
IEC0
IEC1
IEC2
IEC3
IEC4
IEC5
IEC6
IEC7
IPC0
IPC1
IPC2
IPC3
IPC4
IPC5
IPC6
IPC7
IPC8
IPC9
IPC10
IPC11
IPC12
IPC13
IPC15
—
DMA1IE
U2RXIE
DMA4IE
RTCIE
—
AD1IE
INT2IE
PMPIE
DMA5IE
CTMUIE
—
U1TXIE
T5IE
—
U1RXIE
T4IE
OC7IE
—
SPI1IE
OC4IE
OC6IE
—
SPF1IE
OC3IE
OC5IE
—
T3IE
T2IE
—
OC2IE
IC7IE
IC4IE
INT4IE
—
DMA0IE
INT1IE
DMA3IE
—
T1IE
CNIE
—
OC1IE
CMIE
—
IC1IE
INT0IE
U2TXIE
—
DMA2IE
IC6IE
—
MI2C1IE SI2C1IE
IC5IE
—
IC3IE
INT3IE
—
SPI2IE
SPF2IE
—
—
—
—
MI2C2IE SI2C2IE
—
—
—
—
—
LVDIE
U4RXIE
—
—
—
CRCIE
U3TXIE
—
U2ERIE
U3RXIE
—
U1ERIE
U3ERIE
—
—
—
—
—
—
—
U4TXIE
—
U4ERIE
—
—
—
—
—
—
—
—
—
—
—
—
—
LCDIE
—
—
—
—
—
—
—
—
—
—
—
—
JTAGIE
IC1IP1
IC2IP1
—
—
—
—
—
T1IP2
T2IP2
T1IP1
T2IP1
T1IP0
T2IP0
—
OC1IP2
OC2IP2
SPI1IP2
OC1IP1
OC2IP1
SPI1IP1
OC1IP0
OC2IP0
SPI1IP0
—
IC1IP2
IC2IP2
IC1IP0
IC2IP0
—
INT0IP2
INT0IP1
INT0IP0
—
—
—
—
DMA0IP2 DMA0IP1 DMA0IP0 4444
T3IP2 T3IP1 T3IP0 4444
—
U1RXIP2 U1RXIP1 U1RXIP0
—
—
SPF1IP2 SPF1IP1 SPF1IP0
AD1IP2 AD1IP1 AD1IP0
MI2C1IP2 MI2C1IP1 MI2C1IP0
—
—
—
CNIP2
—
—
CNIP1
—
—
CNIP0
—
—
DMA1IP2 DMA1IP1 DMA1IP0
—
—
U1TXIP2 U1TXIP1 U1TXIP0 0044
SI2C1IP2 SI2C1IP1 SI2C1IP0 4444
—
—
CMIP2
IC7IP2
OC4IP2
CMIP1
IC7IP1
OC4IP1
CMIP0
IC7IP0
OC4IP0
—
—
—
—
—
—
—
—
—
INT1IP2
DMA2IP2 DMA2IP1 DMA2IP0 4444
T5IP2 T5IP1 T5IP0 4444
INT1IP1
INT1IP0
4404
—
T4IP2
T4IP1
T4IP0
—
—
OC3IP2
INT2IP2
SPI2IP2
IC3IP2
OC5IP2
PMPIP2
OC3IP1
INT2IP1
SPI2IP1
IC3IP1
OC5IP1
PMPIP1
OC3IP0
INT2IP0
SPI2IP0
IC3IP0
—
—
U2TXIP2 U2TXIP1 U2TXIP0
—
U2RXIP2 U2RXIP1 U2RXIP0
—
—
—
—
IC5IP2
OC7IP2
—
—
IC5IP1
OC7IP1
—
—
IC5IP0
OC7IP0
—
—
—
—
—
—
—
SPF2IP2 SPF2IP1 SPF2IP0 0044
DMA3IP2 DMA3IP1 DMA3IP0 4444
—
—
IC4IP2
OC6IP2
IC4IP1
OC6IP1
IC4IP0
OC6IP0
—
—
—
—
—
OC5IP0
PMPIP0
—
IC6IP2
—
IC6IP1
—
IC6IP0
—
4444
0440
0440
0440
0440
—
—
DMA4IP2 DMA4IP1 DMA4IP0
MI2C2IP2 MI2C2IP1 MI2C2IP0
—
—
—
—
—
—
—
—
SI2C2IP2 SI2C2IP1 SI2C2IP0
INT3IP2 INT3IP1 INT3IP0
DMA5IP2 DMA5IP1 DMA5IP0
—
—
—
—
—
—
—
—
—
INT4IP2
RTCIP2
INT4IP1
RTCIP1
INT4IP0
RTCIP0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
TABLE 4-5:
INTERRUPT CONTROLLER REGISTER MAP (CONTINUED)
File
Addr
Name
All
Resets
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
IPC16
IPC18
IPC19
IPC20
IPC21
IPC22
IPC25
IPC29
00C4
00C8
00CA
00CC
00CE
00D0
00D6
00DE
—
—
—
—
—
—
—
—
CRCIP2
—
CRCIP1
—
CRCIP0
—
—
—
U2ERIP2 U2ERIP1 U2ERIP0
—
—
—
—
—
—
—
—
—
U1ERIP2 U1ERIP1 U1ERIP0
—
—
—
—
—
—
—
—
—
LVDIP2
—
—
LVDIP1
—
—
LVDIP0
—
4440
0004
0040
4440
4000
—
—
—
—
—
—
—
—
—
—
—
—
—
CTMUIP2 CTMUIP1 CTMUIP0
U3ERIP2 U3ERIP1 U3ERIP0
U3TXIP2 U3TXIP1 U3TXIP0
U4ERIP2 U4ERIP1 U4ERIP0
—
U3RXIP2 U3RXIP1 U3RXIP0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
U4TXIP2 U4TXIP1 U4TXIP0
U4RXIP2 U4RXIP1 U4RXIP0 0044
—
—
—
—
—
—
—
LCDIP2
—
LCDIP1
—
LCDIP0
—
0004
0040
—
—
—
—
—
JTAGIP2 JTAGIP1 JTAGIP0
INTTREG 00E0 CPUIRQ
VHOLD
ILR3
ILR2
ILR1
ILR0
VECNUM6 VECNUM5 VECNUM4 VECNUM3 VECNUM2 VECNUM1 VECNUM0 0000
Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
TABLE 4-6:
TIMER REGISTER MAP
All
Resets
File Name Addr
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
TMR1
PR1
0100
0102
0104
0106
0108
010A
010C
010E
0110
0112
0114
0116
0118
011A
011C
011E
0120
Timer1 Register
0000
FFFF
0000
0000
0000
0000
FFFF
FFFF
0000
0000
0000
0000
0000
FFFF
FFFF
0000
0000
Timer1 Period Register
T1CON
TMR2
TMR3HLD
TMR3
PR2
TON
—
TSIDL
—
—
—
TIECS1
TIECS0
—
TGATE TCKPS1 TCKPS0
—
TSYNC
TCS
—
Timer2 Register
Timer3 Holding Register (for 32-bit timer operations only)
Timer3 Register
Timer2 Period Register
PR3
Timer3 Period Register
T2CON
T3CON
TMR4
TMR5HLD
TMR5
PR4
TON
TON
—
—
TSIDL
TSIDL
—
—
—
—
—
—
—
—
—
—
—
—
TGATE TCKPS1 TCKPS0
TGATE TCKPS1 TCKPS0
T32
—
—
—
TCS
TCS
—
—
Timer4 Register
Timer5 Holding Register (for 32-bit operations only)
Timer5 Register
Timer4 Period Register
PR5
Timer5 Period Register
T4CON
T5CON
TON
TON
—
—
TSIDL
TSIDL
—
—
—
—
—
—
—
—
—
—
—
—
TGATE TCKPS1 TCKPS0
TGATE TCKPS1 TCKPS0
T45
—
—
—
TCS
TCS
—
—
Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
TABLE 4-7:
INPUT CAPTURE REGISTER MAP
File
Addr
Name
All
Resets
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
IC1CON1 0140
IC1CON2 0142
—
—
—
—
ICSIDL
—
ICTSEL2 ICTSEL1 ICTSEL0
—
—
—
—
ICI1
ICI0
—
ICOV
ICBNE
ICM2
ICM1
ICM0
0000
—
—
—
IC32
ICTRIG TRIGSTAT
SYNCSEL4 SYNCSEL3 SYNCSEL2 SYNCSEL1 SYNCSEL0 000D
IC1BUF
IC1TMR
0144
0146
Input Capture 1 Buffer Register
Timer Value 1 Register
0000
xxxx
IC2CON1 0148
IC2CON2 014A
—
—
—
—
ICSIDL
—
ICTSEL2 ICTSEL1 ICTSEL0
—
—
—
—
ICI1
ICI0
—
ICOV
ICBNE
ICM2
ICM1
ICM0
0000
—
—
—
IC32
ICTRIG TRIGSTAT
SYNCSEL4 SYNCSEL3 SYNCSEL2 SYNCSEL1 SYNCSEL0 000D
IC2BUF
IC2TMR
014C
014E
Input Capture 2 Buffer Register
Timer Value 2 Register
0000
xxxx
IC3CON1 0150
IC3CON2 0152
—
—
—
—
ICSIDL
—
ICTSEL2 ICTSEL1 ICTSEL0
—
—
—
—
ICI1
ICI0
—
ICOV
ICBNE
ICM2
ICM1
ICM0
0000
—
—
—
IC32
ICTRIG TRIGSTAT
SYNCSEL4 SYNCSEL3 SYNCSEL2 SYNCSEL1 SYNCSEL0 000D
IC3BUF
IC3TMR
0154
0156
Input Capture 3 Buffer Register
Timer Value 3 Register
0000
xxxx
IC4CON1 0158
IC4CON2 015A
—
—
—
—
ICSIDL
—
ICTSEL2 ICTSEL1 ICTSEL0
—
—
—
—
ICI1
ICI0
—
ICOV
ICBNE
ICM2
ICM1
ICM0
0000
—
—
—
IC32
ICTRIG TRIGSTAT
SYNCSEL4 SYNCSEL3 SYNCSEL2 SYNCSEL1 SYNCSEL0 000D
IC4BUF
IC4TMR
015C
015E
Input Capture 4 Buffer Register
Timer Value 4 Register
0000
xxxx
IC5CON1 0160
IC5CON2 0162
—
—
—
—
ICSIDL
—
ICTSEL2 ICTSEL1 ICTSEL0
—
—
—
—
ICI1
ICI0
—
ICOV
ICBNE
ICM2
ICM1
ICM0
0000
—
—
—
IC32
ICTRIG TRIGSTAT
SYNCSEL4 SYNCSEL3 SYNCSEL2 SYNCSEL1 SYNCSEL0 000D
IC5BUF
IC5TMR
0164
0166
Input Capture 5 Buffer Register
Timer Value 5 Register
0000
xxxx
IC6CON1 0168
IC6CON2 016A
—
—
—
—
ICSIDL
—
ICTSEL2 ICTSEL1 ICTSEL0
—
—
—
—
ICI1
ICI0
—
ICOV
ICBNE
ICM2
ICM1
ICM0
0000
—
—
—
IC32
ICTRIG TRIGSTAT
SYNCSEL4 SYNCSEL3 SYNCSEL2 SYNCSEL1 SYNCSEL0 000D
IC6BUF
IC6TMR
016C
016E
Input Capture 6 Buffer Register
Timer Value 6 Register
0000
xxxx
IC7CON1 0170
IC7CON2 0172
—
—
—
—
ICSIDL
—
ICTSEL2 ICTSEL1 ICTSEL0
—
—
—
—
ICI1
ICI0
—
ICOV
ICBNE
ICM2
ICM1
ICM0
0000
—
—
—
IC32
ICTRIG TRIGSTAT
SYNCSEL4 SYNCSEL3 SYNCSEL2 SYNCSEL1 SYNCSEL0 000D
IC7BUF
IC7TMR
0174
0176
Input Capture 7 Buffer Register
Timer Value 7 Register
0000
xxxx
Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
TABLE 4-8:
OUTPUT COMPARE REGISTER MAP
All
Resets
File Name Addr
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
OC1CON1 0190
OC1CON2 0192
—
—
OCSIDL OCTSEL2 OCTSEL1 OCTSEL0 ENFLT2
OCINV DCB1 DCB0
ENFLT1
OC32
ENFLT0
OCFLT2
OCFLT1
OCFLT0
TRIGMODE
OCM2
OCM1
OCM0
0000
FLTMD FLTOUT FLTTRIEN
—
OCTRIG TRIGSTAT OCTRIS SYNCSEL4 SYNCSEL3 SYNCSEL2 SYNCSEL1 SYNCSEL0 000C
OC1RS
OC1R
0194
0196
0198
Output Compare 1 Secondary Register
Output Compare 1 Register
Timer Value 1 Register
0000
0000
xxxx
0000
OC1TMR
OC2CON1 019A
OC2CON2 019C
—
—
OCSIDL OCTSEL2 OCTSEL1 OCTSEL0 ENFLT2
ENFLT1
OC32
ENFLT0
OCFLT2
OCFLT1
OCFLT0
TRIGMODE
OCM2
OCM1
OCM0
FLTMD FLTOUT FLTTRIEN OCINV DCB1 DCB0
—
OCTRIG TRIGSTAT OCTRIS SYNCSEL4 SYNCSEL3 SYNCSEL2 SYNCSEL1 SYNCSEL0 000C
OC2RS
OC2R
019E
01A0
01A2
Output Compare 2 Secondary Register
Output Compare 2 Register
Timer Value 2 Register
0000
0000
xxxx
0000
OC2TMR
OC3CON1 01A4
OC3CON2 01A6
—
—
OCSIDL OCTSEL2 OCTSEL1 OCTSEL0 ENFLT2
ENFLT1
OC32
ENFLT0
OCFLT2
OCFLT1
OCFLT0
TRIGMODE
OCM2
OCM1
OCM0
FLTMD FLTOUT FLTTRIEN OCINV DCB1 DCB0
—
OCTRIG TRIGSTAT OCTRIS SYNCSEL4 SYNCSEL3 SYNCSEL2 SYNCSEL1 SYNCSEL0 000C
OC3RS
OC3R
01A8
01AA
01AC
Output Compare 3 Secondary Register
Output Compare 3 Register
Timer Value 3 Register
0000
0000
xxxx
0000
OC3TMR
OC4CON1 01AE
OC4CON2 01B0
—
—
OCSIDL OCTSEL2 OCTSEL1 OCTSEL0 ENFLT2
ENFLT1
OC32
ENFLT0
OCFLT2
OCFLT1
OCFLT0
TRIGMODE
OCM2
OCM1
OCM0
FLTMD FLTOUT FLTTRIEN OCINV DCB1 DCB0
—
OCTRIG TRIGSTAT OCTRIS SYNCSEL4 SYNCSEL3 SYNCSEL2 SYNCSEL1 SYNCSEL0 000C
OC4RS
OC4R
01B2
01B4
01B6
Output Compare 4 Secondary Register
Output Compare 4 Register
Timer Value 4 Register
0000
0000
xxxx
0000
OC4TMR
OC5CON1 01B8
—
—
OCSIDL OCTSEL2 OCTSEL1 OCTSEL0 ENFLT2
OCINV DCB1 DCB0
ENFLT1
OC32
ENFLT0
OCFLT1
OCFLT1
OCFLT0
TRIGMODE
OCM2
OCM1
OCM0
OC5CON2 01BA FLTMD FLTOUT FLTTRIEN
—
OCTRIG TRIGSTAT OCTRIS SYNCSEL4 SYNCSEL3 SYNCSEL2 SYNCSEL1 SYNCSEL0 000C
OC5RS
OC5R
01BC
01BE
01C0
Output Compare 5 Secondary Register
Output Compare 5 Register
Timer Value 5 Register
0000
0000
xxxx
0000
OC5TMR
OC6CON1 01C2
OC6CON2 01C4
—
—
OCSIDL OCTSEL2 OCTSEL1 OCTSEL0 ENFLT2
ENFLT1
OC32
ENFLT0
OCFLT2
OCFLT1
OCFLT0
TRIGMODE
OCM2
OCM1
OCM0
FLTMD FLTOUT FLTTRIEN OCINV DCB1 DCB0
—
OCTRIG TRIGSTAT OCTRIS SYNCSEL4 SYNCSEL3 SYNCSEL2 SYNCSEL1 SYNCSEL0 000C
OC6RS
OC6R
01C6
01C8
01CA
Output Compare 6 Secondary Register
Output Compare 6 Register
Timer Value 6 Register
0000
0000
xxxx
OC6TMR
Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
TABLE 4-8:
OUTPUT COMPARE REGISTER MAP (CONTINUED)
All
Resets
File Name Addr
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
OC7CON1 01CC
—
—
OCSIDL OCTSEL2 OCTSEL1 OCTSEL0 ENFLT2
OCINV DCB1 DCB0
ENFLT1
OC32
ENFLT0
OCFLT2
OCFLT1
OCFLT0
TRIGMODE
OCM2
OCM1
OCM0
0000
OC7CON2 01CE FLTMD FLTOUT FLTTRIEN
—
OCTRIG TRIGSTAT OCTRIS SYNCSEL4 SYNCSEL3 SYNCSEL2 SYNCSEL1 SYNCSEL0 000C
OC7RS
OC7R
01D0
01D2
01D4
Output Compare 7 Secondary Register
Output Compare 7 Register
Timer Value 7 Register
0000
0000
xxxx
OC7TMR
Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
TABLE 4-9:
I2C™ REGISTER MAP
All
Resets
File Name
Addr
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
I2C1RCV
I2C1TRN
I2C1BRG
I2C1CON
0200
0202
0204
0206
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Receive Register
Transmit Register
0000
00FF
0000
1000
—
—
—
—
Baud Rate Generator Register
I2CEN
I2CSIDL SCLREL
IPMIEN
A10M
DISSLW
SMEN
GCEN
STREN
I2COV
ACKDT
D/A
ACKEN
P
RCEN
S
PEN
R/W
RSEN
RBF
SEN
TBF
I2C1STAT
I2C1ADD
I2C1MSK
I2C2RCV
I2C2TRN
I2C2BRG
I2C2CON
0208
020A
020C
0210
0212
0214
0216
ACKSTAT TRSTAT
—
—
—
—
—
—
—
—
—
—
—
—
—
—
BCL
—
GCSTAT
ADD10
IWCOL
0000
0000
0000
0000
00FF
0000
1000
—
—
—
—
—
—
—
—
Address Register
—
—
Address Mask Register
—
—
—
—
—
—
—
Receive Register
Transmit Register
—
—
—
—
—
—
—
Baud Rate Generator Register
I2CEN
I2CSIDL SCLREL
IPMIEN
A10M
DISSLW
SMEN
GCEN
STREN
I2COV
ACKDT
D/A
ACKEN
P
RCEN
S
PEN
R/W
RSEN
RBF
SEN
TBF
I2C2STAT
I2C2ADD
I2C2MSK
0218
021A
021C
ACKSTAT TRSTAT
—
—
—
—
—
—
—
—
—
BCL
—
GCSTAT
ADD10
IWCOL
0000
0000
0000
—
—
—
—
Address Register
—
Address Mask Register
Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
TABLE 4-10: UART REGISTER MAPS
All
Resets
File Name
Addr
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
U1MODE
U1STA
0220
0222
0224
0226
0228
0230
0232
0234
0236
0238
0250
0252
0254
0256
0258
02B0
02B2
02B4
02B6
02B8
UARTEN
—
USIDL
IREN
—
RTSMD
UTXBRK
—
—
UTXEN
—
UEN1
UTXBF
—
UEN0
TRMT
WAKE
LPBACK
ABAUD
RXINV
RIDLE
BRGH
PERR
PDSEL1
FERR
PDSEL0
OERR
STSEL
0000
0110
xxxx
0000
0000
0000
0110
xxxx
0000
0000
0000
0110
xxxx
0000
0000
0000
0110
xxxx
0000
0000
UTXISEL1 UTXINV UTXISEL0
URXISEL1 URXISEL0 ADDEN
URXDA
U1TXREG
U1RXREG
U1BRG
—
—
—
—
—
—
—
Transmit Register
Receive Register
—
—
—
—
Baud Rate Generator Prescaler Register
U2MODE
U2STA
UARTEN
—
USIDL
IREN
—
RTSMD
UTXBRK
—
—
UTXEN
—
UEN1
UTXBF
—
UEN0
TRMT
WAKE
LPBACK
ABAUD
RXINV
RIDLE
BRGH
PERR
PDSEL1
FERR
PDSEL0
OERR
STSEL
UTXISEL1 UTXINV UTXISEL0
URXISEL1 URXISEL0 ADDEN
URXDA
U2TXREG
U2RXREG
U2BRG
—
—
—
—
—
—
—
Transmit Register
Receive Register
—
—
—
—
Baud Rate Generator Prescaler Register
U3MODE
U3STA
UARTEN
—
USIDL
IREN
—
RTSMD
UTXBRK
—
—
UTXEN
—
UEN1
UTXBF
—
UEN0
TRMT
WAKE
LPBACK
ABAUD
RXINV
RIDLE
BRGH
PERR
PDSEL1
FERR
PDSEL0
OERR
STSEL
UTXISEL1 UTXINV UTXISEL0
URXISEL1 URXISEL0 ADDEN
URXDA
U3TXREG
U3RXREG
U3BRG
—
—
—
—
—
—
—
Transmit Register
Receive Register
—
—
—
—
Baud Rate Generator Prescaler Register
U4MODE
U4STA
UARTEN
—
USIDL
IREN
—
RTSMD
UTXBRK
—
—
UTXEN
—
UEN1
UTXBF
—
UEN0
TRMT
WAKE
LPBACK
ABAUD
RXINV
RIDLE
BRGH
PERR
PDSEL1
FERR
PDSEL0
OERR
STSEL
UTXISEL1 UTXINV UTXISEL0
URXISEL1 URXISEL0 ADDEN
URXDA
U4TXREG
U4RXREG
U4BRG
—
—
—
—
—
—
—
Transmit Register
Receive Register
—
—
—
—
Baud Rate Generator Prescaler Register
Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
TABLE 4-11: SPI REGISTER MAP
All
Resets
File Name Addr
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
SPI1STAT
SPI1CON1
SPI1CON2
SPI1BUF
0240
0242
0244
0248
0260
0262
0264
0268
SPIEN
—
—
—
SPISIDL
—
—
—
SPIBEC2 SPIBEC1 SPIBEC0 SRMPT SPIROV SRXMPT SISEL2
SISEL1
SPRE1
—
SISEL0
SPRE0
—
SPITBF SPIRBF
0000
0000
0000
0000
0000
0000
0000
0000
DISSCK DISSDO MODE16
SMP
—
CKE
—
SSEN
—
CKP
—
MSTEN
—
SPRE2
—
PPRE1
SPIFE
PPRE0
FRMEN SPIFSD SPIFPOL
—
—
—
SPIBEN
Transmit and Receive Buffer
SPIBEC2 SPIBEC1 SPIBEC0 SRMPT SPIROV SRXMPT SISEL2
SPI2STAT
SPI2CON1
SPI2CON2
SPI2BUF
SPIEN
—
—
—
SPISIDL
—
—
—
SISEL1
SPRE1
—
SISEL0
SPRE0
—
SPITBF SPIRBF
DISSCK DISSDO MODE16
SMP
—
CKE
—
SSEN
—
CKP
—
MSTEN
—
SPRE2
—
PPRE1
SPIFE
PPRE0
FRMEN SPIFSD SPIFPOL
—
—
—
SPIBEN
Transmit and Receive Buffer
Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
TABLE 4-12: PORTA REGISTER MAP(1)
File
Name
All
Resets
Addr
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7(2)
Bit 6(2)
Bit 5(2)
Bit 4(2)
Bit 3(2)
Bit2(2)
Bit 1(2)
Bit 0(2)
TRISA
PORTA
LATA
02C0 TRISA15 TRISA14
—
—
—
—
—
—
—
—
—
—
—
—
TRISA10 TRISA9
—
—
—
—
TRISA7
RA7
TRISA6
RA6
TRISA5
RA5
TRISA4
RA4
TRISA3
RA3
TRISA2
RA2
TRISA1
RA1
TRISA0
RA0
C6FF
xxxx
xxxx
0000
02C2
02C4
02C6
RA15
LATA15
ODA15
RA14
LATA14
ODA14
RA10
LATA10
ODA10
RA9
LATA9
ODA9
LATA7
ODA7
LATA6
ODA6
LATA5
ODA5
LATA4
ODA4
LATA3
ODA3
LATA2
ODA2
LATA1
ODA1
LATA0
ODA0
ODCA
Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. Reset values shown are for 100-pin devices.
Note 1: PORTA and all associated bits are unimplemented in 64-pin devices and read as ‘0’.
2: These bits are also unimplemented in 80-pin devices, read as ‘0’.
TABLE 4-13: PORTB REGISTER MAP
File
Name
All
Resets
Addr
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
TRISB
PORTB
LATB
02C8
02CA
02CC
02CE
TRISB15 TRISB14 TRISB13 TRISB12 TRISB11 TRISB10 TRISB9
TRISB8
RB8
TRISB7
RB7
TRISB6
RB6
TRISB5
RB5
TRISB4
RB4
TRISB3 TRISB2
TRISB1
RB1
TRISB0
RB0
FFFF
xxxx
xxxx
0000
RB15
LATB15 LATB14 LATB13 LATB12
ODB15 ODB14 ODB13 ODB12
RB14
RB13
RB12
RB11
LATB11
ODB11
RB10
LATB10
ODB10
RB9
RB3
RB2
LATB9
ODB9
LATB8
ODB8
LATB7
ODB7
LATB6
ODB6
LATB5
ODB5
LATB4
ODB4
LATB3
ODB3
LATB2
ODB2
LATB1
ODB1
LATB0
ODB0
ODCB
Legend: Reset values are shown in hexadecimal.
TABLE 4-14: PORTC REGISTER MAP
File
Name
All
Resets
Addr
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4(1)
Bit 3(2)
Bit 2(1)
Bit 1(2)
Bit 0
TRISC
PORTC
LATC
02D0 TRISC15
02D2 RC15(3,4) RC14(5) RC13(5)
—
—
TRISC12
RC12(3)
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
TRISC4 TRISC3 TRISC2 TRISC1
—
—
—
—
901E
xxxx
xxxx
0000
RC4
RC3
RC2
RC1
02D4
02D6
LATC15 LATC14 LATC13 LATC12
ODC15 ODC14 ODC13 ODC12
LATC4
ODC4
LATC3
ODC3
LATC2
ODC2
LATC1
ODC1
ODCC
Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. Reset values shown are for 100-pin devices.
Note 1: These bits are unimplemented in 64-pin and 80-pin devices, read as ‘0’.
2: These bits are unimplemented in 64-pin devices, read as ‘0’.
3: RC12 and RC15 are only available when the primary oscillator is disabled or when EC mode is selected (POSCMD<1:0> Configuration bits = 11 or 00); otherwise read as ‘0’.
4: RC15 is only available when the POSCMD<1:0> Configuration bits = 11 or 00and the OSCIOFN Configuration bit = 1.
5: RC13 and RC14 are input ports only and cannot be used as output ports.
TABLE 4-15: PORTD REGISTER MAP
File
Name
All
Resets
Addr
Bit 15(1) Bit 14(1) Bit 13(1) Bit 12(1)
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
TRISD
PORTD
LATD
02D8
02DA
02DC
02DE
TRISD15 TRISD14 TRISD13 TRISD12 TRISD11 TRISD10 TRISD9 TRISD8 TRISD7 TRISD6 TRISD5 TRISD4 TRISD3 TRISD2 TRISD1 TRISD0
FFFF
xxxx
xxxx
0000
RD15
LATD15 LATD14 LATD13 LATD12 LATD11 LATD10
ODD15 ODD14 ODD13 ODD12 ODD11 ODD10
RD14
RD13
RD12
RD11
RD10
RD9
RD8
RD7
RD6
RD5
RD4
RD3
RD2
RD1
RD0
LATD9
ODD9
LATD8
ODD8
LATD7
ODD7
LATD6
ODD6
LATD5
ODD5
LATD4
ODD4
LATD3
ODD3
LATD2
ODD2
LATD1
ODD1
LATD0
ODD0
ODCD
Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. Reset values shown are for 100-pin devices.
Note 1: These bits are unimplemented in 64-pin devices, read as ‘0’.
TABLE 4-16: PORTE REGISTER MAP
File
Name
All
Resets
Addr
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9(1)
Bit 8(1)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
TRISE
PORTE
LATE
02E0
02E2
02E4
02E6
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
TRISE9
RE9
TRISE8
RE8
TRISE7
RE7
TRISE6
RE6
TRISE5
RE5
TRISE4
RE4
TRISE3
RE3
TRISE2
RE2
TRISE1
RE1
TRISE0
RE0
03FF
xxxx
xxxx
0000
LATE9
ODE9
LATE8
ODE8
LATE7
ODE7
LATE6
ODE6
LATE5
ODE5
LATE4
ODE4
LATE3
ODE3
LATE2
ODE2
LATE1
ODE1
LATE0
ODE0
ODCE
Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. Reset values shown are for 100-pin devices.
Note 1: These bits are unimplemented in 64-pin devices, read as ‘0’.
TABLE 4-17: PORTF REGISTER MAP
File
Name
All
Resets
Addr
Bit 15
Bit 14
Bit 13(1) Bit 12(1)
Bit 11
Bit 10
Bit 9
Bit 8(2)
Bit 7(2)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
TRISF
PORTF
LATF
02E8
02EA
02EC
02EE
—
—
—
—
—
—
—
—
TRISF13 TRISF12
—
—
—
—
—
—
—
—
—
—
—
—
TRISF8
RF8
TRISF7
RF7
TRISF6
RF6
TRISF5
RF5
TRISF4
RF4
TRISF3
RF3
TRISF2
RF2
TRISF1
RF1
TRISF0
RF0
31FF
xxxx
xxxx
0000
RF13
LATF13
ODF13
RF12
LATF12
ODF12
LATF8
ODF8
LATF7
ODF7
LATF6
ODF6
LATF5
ODF5
LATF4
ODF4
LATF3
ODF3
LATF2
ODF2
LATF1
ODF1
LATF0
ODF0
ODCF
Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. Reset values shown are for 100-pin devices.
Note 1: These bits are unimplemented in 64-pin devices, read as ‘0’.
2: These bits are unimplemented in 64-pin and 80-pin devices, read as ‘0’.
TABLE 4-18: PORTG REGISTER MAP
File
Name
All
Resets
Addr Bit 15(1) Bit 14(1) Bit 13(1) Bit 12(1)
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1(2)
Bit 0(2)
TRISG
PORTG
LATG
02F0 TRISG15 TRISG14 TRISG13 TRISG12
—
—
—
—
—
—
—
—
TRISG9 TRISG8 TRISG7 TRISG6
—
—
—
—
—
—
—
—
TRISG3 TRISG2 TRISG1 TRISG0
F3CF
xxxx
xxxx
0000
02F2
02F4 LATG15 LATG14 LATG13 LATG12
02F6 ODG15 ODG14 ODG13 ODG12
RG15
RG14
RG13
RG12
RG9
RG8
RG7
LATG7
ODG7
RG6
LATG6
ODG6
RG3
RG2
LATG2
ODG2
RG1
RG0
LATG9
ODG9
LATG8
ODG8
LATG1
ODG1
LATG0
ODG0
LATG3
ODG3
ODCG
Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. Reset values shown are for 100-pin devices.
Note 1: These bits are unimplemented in 64-pin and 80-pin devices, read as ‘0’.
2: These bits are unimplemented in 64-pin devices, read as ‘0’.
TABLE 4-19: PAD CONFIGURATION REGISTER MAP (PADCFG1)
All
Resets
File Name Addr
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PADCFG1 02FC
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
PMPTTL
0000
Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
TABLE 4-20: A/D REGISTER MAP
All
Resets
File Name
Addr
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
ADC1BUF0
ADC1BUF1
ADC1BUF2
ADC1BUF3
ADC1BUF4
ADC1BUF5
ADC1BUF6
ADC1BUF7
ADC1BUF8
ADC1BUF9
0300
0302
0304
0306
0308
030A
030C
030E
0310
0312
A/D Data Buffer 0/Threshold for Channel 0
A/D Data Buffer 1/Threshold for Channel 1
A/D Data Buffer 2/Threshold for Channel 2
A/D Data Buffer 3/Threshold for Channel 3
A/D Data Buffer 4/Threshold for Channel 4
A/D Data Buffer 5/Threshold for Channel 5
A/D Data Buffer 6/Threshold for Channel 6
A/D Data Buffer 7/Threshold for Channel 7
A/D Data Buffer 8/Threshold for Channel 8
A/D Data Buffer 9/Threshold for Channel 9
A/D Data Buffer 10/Threshold for Channel 10
A/D Data Buffer 11/Threshold for Channel 11
A/D Data Buffer 12/Threshold for Channel 12
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
0000
0000
0000
ADC1BUF10 0314
ADC1BUF11 0316
ADC1BUF12 0318
ADC1BUF13 031A
ADC1BUF14 031C
ADC1BUF15 031E
ADC1BUF16 0320
ADC1BUF17 0322
ADC1BUF18 0324
ADC1BUF19 0326
ADC1BUF20 0328
ADC1BUF21 032A
ADC1BUF22 032C
ADC1BUF23 032E
ADC1BUF24 0330
ADC1BUF25 0332
A/D Data Buffer 13/Threshold for Channel 13/Threshold for Channel 0 in Windowed Compare
A/D Data Buffer 14/Threshold for Channel 14/Threshold for Channel 1 in Windowed Compare
A/D Data Buffer 15/Threshold for Channel 15/Threshold for Channel 2 in Windowed Compare
A/D Data Buffer 16/Threshold for Channel 16/Threshold for Channel 3 in Windowed Compare(1)
A/D Data Buffer 17/Threshold for Channel 17/Threshold for Channel 4 in Windowed Compare(1)
A/D Data Buffer 18/Threshold for Channel 18/Threshold for Channel 5 in Windowed Compare(1)
A/D Data Buffer 19/Threshold for Channel 19/Threshold for Channel 6 in Windowed Compare(1)
A/D Data Buffer 20/Threshold for Channel 20/Threshold for Channel 7 in Windowed Compare(1)
A/D Data Buffer 21/Threshold for Channel 21/Threshold for Channel 8 in Windowed Compare(1)
A/D Data Buffer 22/Threshold for Channel 22/Threshold for Channel 9 in Windowed Compare(1)
A/D Data Buffer 23/Threshold for Channel 23/Threshold for Channel 10 in Windowed Compare(1)
A/D Data Buffer 24/Threshold for Channel 24/Threshold for Channel 11 in Windowed Compare
A/D Data Buffer 25/Threshold for Channel 25/Threshold for Channel 12 in Windowed Compare
AD1CON1
AD1CON2
AD1CON3
AD1CHS
0340
0342
0344
0348
034E
0350
ADON
—
ADSIDL DMABM
DMAEN MODE12 FORM1 FORM0
SSRC3
BUFS
SSRC2
SMPI4
ADCS6
SSRC1
SMPI3
ADCS5
SSRC0
SMPI2
ADCS4
—
ASAM
SMPI0
ADCS2
SAMP
BUFM
ADCS1
DONE
ALTS
PVCFG1 PVCFG0 NVCFG0 OFFCAL BUFREGEN CSCNA
—
—
SMPI1
ADCS3
ADRC EXTSAM PUMPEN SAMC4 SAMC3 SAMC2 SAMC1 SAMC0
ADCS7
ADCS0
CH0NB2 CH0NB1 CH0NB0 CH0SB4 CH0SB3 CH0SB2 CH0SB1 CH0SB0 CH0NA2 CH0NA1 CH0NA0 CH0SA4 CH0SA3 CH0SA2 CH0SA1 CH0SA0 0000
AD1CSSH
AD1CSSL
—
CSS30
CSS14
CSS29
CSS13
CSS28
CSS12
CSS27
CSS11
CSS26
CSS10
CSS25
CSS9
CSS24
CSS8
CSS23
CSS7
CSS22
CSS6
CSS21
CSS5
CSS20
CSS4
CSS19
CSS3
CSS18
CSS2
CSS17
CSS1
CSS16
CSS0
0000
0000
CSS15
Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1: These bits are unimplemented in 64-pin and 80-pin devices, read as ‘0’.
TABLE 4-20: A/D REGISTER MAP (CONTINUED)
All
Resets
File Name
Addr
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
AD1CON4
AD1CON5
AD1CHITH
AD1CHITL
0352
0354
0356
0358
—
ASEN
—
—
LPEN
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
DMABL2 DMABL1 DMABL0 0000
WM0 CM1 CM0 0000
CTMREQ BGREQ
ASINT1 ASINT0
WM1
—
—
—
—
CHH25(1) CHH24(1) CHH23(1) CHH22(1) CHH21(1) CHH20(1) CHH19(1) CHH18(1) CHH17(1) CHH16(1) 0000
CHH15
—
CHH14
CHH13
CHH12
CHH11
CHH10
CHH9 CHH8 CHH7 CHH6 CHH5 CHH4 CHH3 CHH2 CHH1 CHH0 0000
AD1CTMENH 0360
CTMEN30 CTMEN29 CTMEN28 CTMEN27 CTMEN26 CTMEN25 CTMEN24 CTMEN23 CTMEN22 CTMEN21 CTMEN20 CTMEN19 CTMEN18 CTMEN17 CTMEN16 0000
AD1CTMENL 0362 CTMEN15 CTMEN14 CTMEN13 CTMEN12 CTMEN11 CTMEN10 CTMEN9 CTMEN8 CTMEN7 CTMEN6 CTMEN5 CTMEN4 CTMEN3 CTMEN2 CTMEN1 CTMEN0 0000
AD1DMBUF
0364
Conversion Data Buffer (Extended Buffer mode)
xxxx
Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1: These bits are unimplemented in 64-pin and 80-pin devices, read as ‘0’.
TABLE 4-21: CTMU REGISTER MAP
All
Resets
File Name Addr
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
CTMUCON1 035A CTMUEN
—
CTMUSIDL
TGEN
EDGEN EDGSEQEN IDISSEN
CTTRIG
—
—
—
—
—
—
—
—
—
—
0000
0000
CTMUCON2 035C EDG1MOD EDG1POL EDG1SEL3 EDG1SEL2 EDG1SEL1 EDG1SEL0 EDG2STAT EDG1STAT EDG2MOD EDG2POL EDG2SEL3 EDG2SEL2 EDG2SEL1 EDG2SEL0
CTMUICON 035E ITRIM5 ITRIM4 ITRIM3 ITRIM2 ITRIM1 ITRIM0 IRNG1 IRNG0
Legend: — = unimplemented, read as ‘ ’. Reset values are shown in hexadecimal.
—
—
—
—
—
—
—
—
0000
0
TABLE 4-22: ANALOG CONFIGURATION REGISTER MAP
All
Resets
File Name Addr
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
ANCFG
ANSA
ANSB
ANSC
ANSD
ANSE
ANSG
04DE
04E0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
VBG6EN VBG2EN VBGEN
0000
00C0
FFFF
0010
0CC0
02F0
03C0
ANSA7(1) ANSA6(1)
—
ANSB2
—
—
ANSB1
—
—
ANSB0
—
04E2 ANSB15 ANSB14 ANSB13 ANSB12 ANSB11 ANSB10 ANSB9
ANSB8
—
ANSB7
—
ANSB6
—
ANSB5
—
ANSB4
ANSC4(1)
—
ANSB3
—
04E4
04E6
04E8
04EC
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
ANSD11 ANSD10
—
ANSD7
ANSE7
ANSG7
ANSD6
ANSE6
ANSG6
—
—
—
—
—
—
—
—
—
ANSE9(2)
—
ANSE5
—
ANSE4
—
—
—
—
—
ANSG9
ANSG8
—
—
—
—
Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1: These bits are unimplemented in 64-pin and 80-pin devices, read as ‘0’.
2: These bits are unimplemented in 64-pin devices. In 80-pin devices, this bit needs to be cleared to get digital functionality on RE9.
TABLE 4-23: DMA REGISTER MAP
All
Resets
File Name
Addr
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
DMACON
DMABUF
DMAL
0380
0382
0384
0386
0388
DMAEN
—
—
—
—
—
—
—
—
—
—
—
—
—
—
PRSSEL 0000
0000
DMA Transfer Data Buffer
DMA High Address Limit
DMA Low Address Limit
0000
DMAH
0000
DMACH0
DMAINT0
—
—
—
—
—
—
NULLW RELOAD CHREQ SAMODE1 SAMODE0 DAMODE1 DAMODE0 TRMODE1 TRMODE0 BYTE
LOWIF DONEIF HALFIF OVRUNIF
CHEN
0000
038A DBUFWF
CHSEL5 CHSEL4 CHSEL3 CHSEL2 CHSEL1 CHSEL0 HIGHIF
—
—
HALFEN 0000
0000
DMASRC0 038C
DMA Channel 0 Source Address
DMA Channel 0 Destination Address
DMA Channel 0 Transaction Count
DMADST0
DMACNT0
DMACH1
DMAINT1
DMASRC1
DMADST1
DMACNT1
DMACH2
DMAINT2
DMASRC2
DMADST2
DMACNT2
DMACH3
DMAINT3
038E
0390
0392
0000
0001
—
—
—
—
—
—
NULLW RELOAD CHREQ SAMODE1 SAMODE0 DAMODE1 DAMODE0 TRMODE1 TRMODE0 BYTE
CHEN
0000
0394 DBUFWF
CHSEL5 CHSEL4 CHSEL3 CHSEL2 CHSEL1 CHSEL0 HIGHIF LOWIF DONEIF HALFIF OVRUNIF
—
—
HALFEN 0000
0000
0396
0398
039A
DMA Channel 1 Source Address
DMA Channel 1 Destination Address
DMA Channel 1 Transaction Count
0000
0001
039C
—
—
—
—
—
—
NULLW RELOAD CHREQ SAMODE1 SAMODE0 DAMODE1 DAMODE0 TRMODE1 TRMODE0 BYTE
CHEN
0000
039E DBUFWF
CHSEL5 CHSEL4 CHSEL3 CHSEL2 CHSEL1 CHSEL0 HIGHIF LOWIF DONEIF HALFIF OVRUNIF
—
—
HALFEN 0000
0000
03A0
03A2
03A4
DMA Channel 2 Source Address
DMA Channel 2 Destination Address
DMA Channel 2 Transaction Count
0000
0001
03A6
03A8 DBUFWF
DMASRC3 03AA
—
—
—
—
—
—
NULLW RELOAD CHREQ SAMODE1 SAMODE0 DAMODE1 DAMODE0 TRMODE1 TRMODE0 BYTE
CHEN
0000
CHSEL5 CHSEL4 CHSEL3 CHSEL2 CHSEL1 CHSEL0 HIGHIF LOWIF DONEIF HALFIF OVRUNIF
—
—
HALFEN 0000
0000
DMA Channel 3 Source Address
DMA Channel 3 Destination Address
DMA Channel 3 Transaction Count
DMADST3
DMACNT3
DMACH4
DMAINT4
DMASRC4
DMADST4
DMACNT4
DMACH5
DMAINT5
03AC
03AE
03B0
0000
0001
—
—
—
—
—
—
NULLW RELOAD CHREQ SAMODE1 SAMODE0 DAMODE1 DAMODE0 TRMODE1 TRMODE0 BYTE
CHEN
0000
03B2 DBUFWF
CHSEL5 CHSEL4 CHSEL3 CHSEL2 CHSEL1 CHSEL0 HIGHIF LOWIF DONEIF HALFIF OVRUNIF
—
—
HALFEN 0000
0000
03B4
03B6
03B8
DMA Channel 4 Source Address
DMA Channel 4 Destination Address
DMA Channel 4 Transaction Count
0000
0001
03BA
—
—
—
—
—
—
—
NULLW RELOAD CHREQ SAMODE1 SAMODE0 DAMODE1 DAMODE0 TRMODE1 TRMODE0 BYTE
CHEN
0000
03BC DBUFWF
CHSEL4 CHSEL3 CHSEL2 CHSEL1 CHSEL0 HIGHIF LOWIF DONEIF HALFIF OVRUNIF
—
—
HALFEN 0000
0000
DMASRC5 03BE
DMA Channel 5 Source Address
DMA Channel 5 Destination Address
DMA Channel 5 Transaction Count
DMADST5
DMACNT5
03C0
03C2
0000
0001
Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
TABLE 4-24: LCD REGISTER MAP
All
Resets
File Name
Addr
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
LCDREG
0580
0582
0584
0586
0590
0592
0594
CPEN
LCDIRE
LCDEN
—
—
—
—
—
—
—
—
—
—
—
BIAS2
BIAS1
BIAS0
—
MODE13 CKSEL1 CKSEL0 0000
LCDREF
LCDCST2 LCDCST1 LCDCST0 VLCD3PE VLCD2PE VLCD1PE LRLAP1 LRLAP0 LRLBP1 LRLBP0
LRLAT2
LMUX2
LP2
LRLAT1
LMUX1
LP1
LRLAT0
LMUX0
LP0
0000
0000
0000
0000
0000
LCDCON
—
LCDSIDL
—
—
—
—
—
—
—
SLPEN
BIASMD
S06C0
WERR
LCDA
CS1
WA
CS0
LCDPS
—
—
—
—
—
—
WFT
LP3
LCDDATA0
LCDDATA1
LCDDATA2
LCDDATA3
LCDDATA4
LCDDATA5
LCDDATA6
LCDDATA7
LCDDATA8
LCDDATA9
S15C0
S14C0
S30C0
S13C0
S12C0
S28C0
S11C0
S27C0
S10C0
S26C0
S09C0
S25C0
S08C0
S24C0
S07C0
S23C0
S05C0
S04C0
S03C0
S19C0
S02C0
S01C0
S00C0
S31C0
S29C0
S22C0
S21C0
S20C0
S18C0
S17C0
S16C0
S47C0 S46C0(1) S45C0(1) S44C0(1) S43C0(1) S42C0(1) S41C0(1) S40C0(1) S39C0(1) S38C0(1) S37C0(1) S36C0(1) S35C0(1) S34C0(1) S33C0(1) S32C0(1) 0000
0596 S63C0(2) S62C0(2) S61C0(2) S60C0(2) S59C0(2) S58C0(2) S57C0(2) S56C0(2) S55C0(2) S54C0(2) S53C0(2) S52C0(2) S51C0(2) S50C0(1) S49C0(2) S48C0
0000
0000
0000
0598
059A
059C
S15C1
S14C1
S13C1
S12C1
S11C1
S10C1
S09C1
S08C1
S07C1
S06C1
S05C1
S04C1
S03C1
S02C1
S01C1
S00C1
S31C1
S30C1
S29C1
S28C1
S27C1
S26C1
S25C1
S24C1
S23C1
S22C1
S21C1
S20C1
S19C1
S18C1
S17C1
S16C1
S47C1 S46C1(1) S45C1(1) S44C1(1) S43C1(1) S42C1(1) S41C1(1) S40C1(1) S39C1(1) S38C1(1) S37C1(1) S36C1(1) S35C1(1) S34C1(1) S33C1(1) S32C1(1) 0000
059E S63C1(2) S62C1(2) S61C1(2) S60C1(2) S59C1(2) S58C1(2) S57C1(2) S56C1(2) S55C1(2) S54C1(2) S53C1(2) S52C1(2) S51C1(2) S50C1(1) S49C1(2) S48C1
0000
0000
0000
05A0
05A2
S15C2
S31C2
S14C2
S30C2
S13C2
S29C2
S12C2
S28C2
S11C2
S27C2
S10C2
S26C2
S09C2
S25C2
S08C2
S24C2
S07C2
S23C2
S06C2
S22C2
S05C2
S21C2
S04C2
S20C2
S03C2
S19C2
S02C2
S18C2
S01C2
S17C2
S00C2
S16C2
LCDDATA10 05A4
LCDDATA11 05A6 S63C2(2) S62C2(2) S61C2(2) S60C2(2) S59C2(2) S58C2(2) S57C2(2) S56C2(2) S55C2(2) S54C2(2) S53C2(2) S52C2(2) S51C2(2) S50C2(1) S49C2(2) S48C2
S47C2 S46C2(1) S45C2(1) S44C2(1) S43C2(1) S42C2(1) S41C2(1) S40C2(1) S39C2(1) S38C2(1) S37C2(1) S36C2(1) S35C2(1) S34C2(1) S33C2(1) S32C2(1) 0000
0000
0000
0000
LCDDATA12 05A8
LCDDATA13 05AA
LCDDATA14 05AC
S15C3
S14C3
S13C3
S12C3
S11C3
S10C3
S09C3
S08C3
S07C3
S06C3
S05C3
S04C3
S03C3
S02C3
S01C3
S00C3
S31C3
S30C3
S29C3
S28C3
S27C3
S26C3
S25C3
S24C3
S23C3
S22C3
S21C3
S20C3
S19C3
S18C3
S17C3
S16C3
S47C3 S46C3(1) S45C3(1) S44C3(1) S43C3(1) S42C3(1) S41C3(1) S40C3(1) S39C3(1) S38C3(1) S37C3(1) S36C3(1) S35C3(1) S34C3(1) S33C3(1) S32C3(1) 0000
LCDDATA15 05AE S63C3(2) S62C3(2) S61C3(2) S60C3(2) S59C3(2) S58C3(2) S57C3(2) S56C3(2) S55C3(2) S54C3(2) S53C3(2) S52C3(2) S51C3(2) S50C3(1) S49C3(2) S48C3
0000
0000
0000
0000
0000
0000
0000
LCDSE3
LCDSE2
LCDSE1
LCDSE0
058E
058C
058A
0588
SE63(2)
SE62(2)
SE46(1)
SE30
SE61(2)
SE45(1)
SE29
SE60(2)
SE44(1)
SE28
SE59(2)
SE43(1)
SE27
SE58(2)
SE42(1)
SE26
SE57(2)
SE41(1)
SE25
SE56(2)
SE40(1)
SE24
SE55(2)
SE39(1)
SE23
SE54(2)
SE38(1)
SE22
SE53(2)
SE37(1)
SE21
SE52(2)
SE36(1)
SE20
SE51(2)
SE35(1)
SE019
SE03
SE50(1)
SE34(1)
SE18
SE49(2)
SE33(1)
SE17
SE48
SE32(1)
SE16
SE47
SE31
SE15
SE14
SE13
SE12
SE11
SE10
SE09
SE08
SE07
SE06
SE05
SE04
SE02
SE01
SE00
LCDDATA16 05B0
LCDDATA17 05B2
LCDDATA18 05B4
S15C4
S31C4
S14C4
S30C4
S13C4
S29C4
S12C4
S28C4
S11C4
S27C4
S10C4
S26C4
S09C4
S25C4
S08C4
S24C4
S07C4
S23C4
S06C4
S22C4
S05C4
S21C4
S04C4
S20C4
S03C4
S19C4
S02C4
S18C4
S01C4
S17C4
S00C4
S16C4
S47C4 S46C4(1) S45C4(1) S44C4(1) S43C4(1) S42C4(1) S41C4(1) S40C4(1) S39C4(1) S38C4(1) S37C4(1) S36C4(1) S35C4(1) S34C4(1) S33C4(1) S32C4(1) 0000
LCDDATA19 05B6 S63C4(2) S62C4(2) S61C4(2) S60C4(2) S59C4(2) S58C4(2) S57C4(2) S56C4(2) S55C4(2) S54C4(2) S53C4(2) S52C4(2) S51C4(2) S50C4(1) S49C4(2) S48C4
0000
0000
0000
LCDDATA20 05B8
LCDDATA21 05BA
LCDDATA22 05BC
S15C5
S14C5
S13C5
S12C5
S11C5
S10C5
S09C5
S08C5
S07C5
S06C5
S05C5
S04C5
S03C5
S02C5
S01C5
S00C5
S31C5
S30C5
S29C5
S28C5
S27C5
S26C5
S25C5
S24C5
S23C5
S22C5
S21C5
S20C5
S19C5
S18C5
S17C5
S16C5
S47C5 S46C5(1) S45C5(1) S44C5(1) S43C5(1) S42C5(1) S41C5(1) S40C5(1) S39C5(1) S38C5(1) S37C5(1) S36C5(1) S35C5(1) S34C5(1) S33C5(1) S32C5(1) 0000
LCDDATA23 05BE S63C5(2) S62C5(2) S61C5(2) S60C5(2) S59C5(2) S58C5(2) S57C5(2) S56C5(2) S55C5(2) S54C5(2) S53C5(2) S52C5(2) S51C5(2) S50C5(1) S49C5(2) S48C5
0000
Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1: These bits are unimplemented in 64-pin devices, read as ‘0’.
2: These bits are unimplemented in 64-pin and 80-pin devices, devices, read as ‘0’.
TABLE 4-24: LCD REGISTER MAP (CONTINUED)
All
Resets
File Name
Addr
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
LCDDATA24 05C0
LCDDATA25 05C2
LCDDATA26 05C4
S15C6
S31C6
S14C6
S30C6
S13C6
S29C6
S12C6
S28C6
S11C6
S27C6
S10C6
S26C6
S09C6
S25C6
S08C6
S24C6
S07C6
S23C6
S06C6
S22C6
S05C6
S21C6
S04C6
S20C6
S03C6
S19C6
S02C6
S18C6
S01C6
S17C6
S00C6
S16C6
0000
0000
S47C6 S46C6(1) S45C6(1) S44C6(1) S43C6(1) S42C6(1) S41C6(1) S40C6(1) S39C6(1) S38C6(1) S37C6(1) S36C6(1) S35C6(1) S34C6(1) S33C6(1) S32C6(1) 0000
LCDDATA27 05C6 S63C6(2) S62C6(2) S61C6(2) S60C6(2) S59C6(2) S58C6(2) S57C6(2) S56C6(2) S55C6(2) S54C6(2) S53C6(2) S52C6(2) S51C6(2) S50C6(1) S49C6(2) S48C6
0000
0000
0000
LCDDATA28 05C8
LCDDATA29 05CA
LCDDATA30 05CC
S15C7
S14C7
S13C7
S12C7
S11C7
S10C7
S09C7
S08C7
S07C7
S06C7
S05C7
S04C7
S03C7
S02C7
S01C7
S00C7
S31C7
S30C7
S29C7
S28C7
S27C7
S26C7
S25C7
S24C7
S23C7
S22C7
S21C7
S20C7
S19C7
S18C7
S17C7
S16C7
S47C7 S46C7(1) S45C7(1) S44C7(1) S43C7(1) S42C7(1) S41C7(1) S40C7(1) S39C7(1) S38C7(1) S37C7(1) S36C7(1) S35C7(1) S34C7(1) S33C7(1) S32C7(1) 0000
LCDDATA31 05CE S63C7(2) S62C7(2) S61C7(2) S60C7(2) S59C7(2) S58C7(2) S57C7(2) S56C7(2) S55C7(2) S54C7(2) S53C7(2) S52C7(2) S51C7(2) S50C7(1) S49C7(2) S48C7
0000
Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1: These bits are unimplemented in 64-pin devices, read as ‘0’.
2: These bits are unimplemented in 64-pin and 80-pin devices, devices, read as ‘0’.
TABLE 4-25: PARALLEL MASTER/SLAVE PORT REGISTER MAP
All
Resets
File Name Addr
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PMCON1
PMCON2
PMCON3
PMCON4
0600
0602
PMPEN
BUSY
—
—
PSIDL ADRMUX1 ADRMUX0
—
—
MODE1
—
MODE0
—
CSF1
CSF0
ALP
ALMODE
—
BUSKEEP IRQM1
IRQM0
0000
ERROR TIMEOUT
—
—
RADDR23 RADDR22 RADDR21 RADDR20 RADDR19 RADDR18 RADDR17 RADDR16 0000
0604 PTWREN PTRDEN PTBE1EN PTBE0EN
0606 PTEN15 PTEN14 PTEN13 PTEN12
CSDIS CSP CSPTEN BEP
PMCS1BS 060A BASE23 BASE22 BASE21 BASE20
AWAITM1 AWAITM0 AWAITE
—
PTEN22
PTEN6
PTSZ1
—
PTEN21
PTEN5
PTSZ0
—
PTEN20
PTEN4
—
PTEN19
PTEN3
—
PTEN18
PTEN2
—
PTEN17
PTEN1
—
PTEN16
PTEN0
—
0000
0000
0000
0200
PTEN11
—
PTEN10
WRSP
BASE18
—
PTEN9
RDSP
BASE17
—
PTEN8
SM
PTEN7
ACKP
PMCS1CF 0608
BASE19
BASE16
—
BASE15
—
BASE11
—
—
—
PMCS1MD 060C
PMCS2CF 060E
ACKM1
CSDIS
ACKM0 AMWAIT2 AMWAIT1 AMWAIT0
DWAITB1 DWAITB0 DWAITM3 DWAITM2 DWAITM1 DWAITM0 DWAITE1 DWAITE0 0000
CSP
CSPTEN
BEP
—
WRSP
BASE18
—
RDSP
BASE17
—
SM
ACKP
PTSZ1
—
PTSZ0
—
—
—
—
—
—
—
—
—
—
0000
0600
PMCS2BS 0610 BASE23
BASE22 BASE21 BASE20
BASE19
BASE16
—
BASE15
BASE11
PMCS2MD 0612
PMDOUT1 0614
PMDOUT2 0616
ACKM1
ACKM0 AMWAIT2 AMWAIT1 AMWAIT0
Data Out Register 1<15:8>
Data Out Register 2<15:8>
Data In Register 1<15:8>
DWAITB1 DWAITB0 DWAITM3 DWAITM2 DWAITM1 DWAITM0 DWAITE1 DWAITE0 0000
Data Out Register 1<7:0>
Data Out Register 2<7:0>
Data In Register 1<7:0>
Data In Register 2<7:0>
xxxx
xxxx
xxxx
xxxx
008F
PMDIN1
PMDIN2
PMSTAT
0618
061A
061C
Data In Register 2<15:8>
IBF
IBOV
—
—
IB3F
IB2F
IB1F
IB0F
OBE
OBUF
—
—
OB3E
OB2E
OB1E
OB0E
Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
TABLE 4-26: REAL-TIME CLOCK AND CALENDAR (RTCC) REGISTER MAP
All
Resets
File Name Addr
0620
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
ALRMVAL
ALCFGRPT 0622 ALRMEN CHIME
RTCVAL 0624
RCFGCAL 0626 RTCEN
RTCPWC 0628 PWCEN PWCPOL PWCPRE PWSPRE RTCLK1 RTCLK0 RTCOUT1 RTCOUT0
Alarm Value Register Window Based on ALRMPTR<1:0>
AMASK2 AMASK1 AMASK0 ALRMPTR1 ALRMPTR0 ARPT7 ARPT6
RTCC Value Register Window Based on RTCPTR<1:0>
xxxx
AMASK3
ARPT5
ARPT4
ARPT3
ARPT2 ARPT1 ARPT0 0000
xxxx
—
RTCWREN RTCSYNC HALFSEC RTCOE RTCPTR1 RTCPTR0
CAL7
—
CAL6
—
CAL5
—
CAL4
—
CAL3
—
CAL2
—
CAL1
—
CAL0 Note 1
—
Note 1
Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1: The status of the RCFGCAL and RTCPWR registers on POR is ‘0000’, and on other Resets, it is unchanged.
TABLE 4-27: DATA SIGNAL MODULATOR (DSM) REGISTER MAP
All
Resets
File Name Addr
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
MDCON
MDSRC
MDCAR
062A
062C
MDEN
—
—
—
MDSIDL
—
—
—
—
—
—
—
—
—
—
—
—
—
MDOE
—
MDSLR MDOPOL
—
—
—
MDBIT
MS0
0020
000x
0000
SODIS
—
—
—
MS3
CL3
MS2
CL2
MS1
CL1
062E CHODIS CHPOL CHSYNC
CH3
CH2
CH1
CH0
CLODIS
CLPOL CLSYNC
CL0
Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
TABLE 4-28: COMPARATORS REGISTER MAP
All
Resets
File Name
Addr
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
CMSTAT
CVRCON
CM1CON
CM2CON
CM3CON
0630
0632
0634
0636
0638
CMIDL
—
—
—
—
—
—
—
—
C3EVT
C2EVT
C1EVT
—
—
—
CVRR
—
—
—
CVR3
—
C3OUT
CVR2
—
C2OUT
CVR1
CCH1
CCH1
CCH1
C1OUT
CVR0
CCH0
CCH0
CCH0
0000
0000
0000
0000
0000
—
—
—
—
—
—
CVREFP CVREFM1 CVREFM0 CVREN CVROE
CVRSS
CREF
CREF
CREF
CON
CON
CON
COE
COE
COE
CPOL
CPOL
CPOL
—
—
—
CEVT
CEVT
CEVT
COUT
COUT
COUT
EVPOL1 EVPOL0
EVPOL1 EVPOL0
EVPOL1 EVPOL0
—
—
—
—
—
—
Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
TABLE 4-29: CRC REGISTER MAP
All
Resets
File Name
Addr
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
CRCCON1
0640
CRCEN
—
CSIDL VWORD4 VWORD3 VWORD2 VWORD1 VWORD0 CRCFUL CRCMPT CRCISEL CRCGO LENDIAN
—
—
—
0040
PLEN2
PLEN1
PLEN0
CRCCON2
CRCXORL
CRCXORH
CRCDATL
CRCDATH
0642
0644
0646
0648
064A
—
—
—
DWIDTH4 DWIDTH3 DWIDTH2 DWIDTH1 DWIDTH0
—
X7
—
X6
—
X5
PLEN4
X4
PLEN3
X3
0000
0000
0000
0000
0000
0000
0000
X15
X31
X14
X30
X13
X29
X12
X28
X11
X27
X10
X26
X9
X8
X2
X1
—
X25
X24
X23
X22
X21
X20
X19
X18
X17
X16
CRC Data Input Register Low
CRC Data Input Register High
CRC Result Register Low
CRC Result Register High
CRCWDATL 064C
CRCWDATH 064E
Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
TABLE 4-30: PERIPHERAL PIN SELECT REGISTER MAP
File
Name
All
Resets
Addr
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
RPINR0
RPINR1
RPINR2
RPINR3
RPINR4
RPINR7
RPINR8
RPINR9
RPINR10
RPINR11
RPINR17
RPINR18
RPINR19
RPINR20
0680
0682
0684
0686
0688
068E
0690
0692
0694
0696
06A2
06A4
06A6
06A8
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
INT1R5
INT3R5
—
INT1R4
INT3R4
—
INT1R3
INT3R3
—
INT1R2
INT3R2
—
INT1R1
INT3R1
—
INT1R0
INT3R0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
3F3F
3F3F
3F3F
3F3F
3F3F
3F3F
3F3F
3F3F
003F
INT2R5
INT4R5
INT2R4
INT4R4
INT2R3
INT4R3
INT2R2
INT4R2
INT2R1
INT4R1
INT2R0
INT4R0
T3CKR5
T5CKR5
IC2R5
IC4R5
IC6R5
—
T3CKR4
T5CKR4
IC2R4
IC4R4
IC6R4
—
T3CKR3
T5CKR3
IC2R3
IC4R3
IC6R3
—
T3CKR2
T5CKR2
IC2R2
IC4R2
IC6R2
—
T3CKR1
T5CKR1
IC2R1
IC4R1
IC6R1
—
T3CKR0
T5CKR0
IC2R0
IC4R0
IC6R0
—
T2CKR5 T2CKR4 T2CKR3 T2CKR2 T2CKR1 T2CKR0
T4CKR5 T4CKR4 T4CKR3 T4CKR2 T4CKR1 T4CKR0
IC1R5
IC3R5
IC5R5
IC7R5
IC1R4
IC3R4
IC5R4
IC7R4
IC1R3
IC3R3
IC5R3
IC7R3
IC1R2
IC3R2
IC5R2
IC7R2
IC1R1
IC3R1
IC5R1
IC7R1
IC1R0
IC3R0
IC5R0
IC7R0
OCFBR5 OCFBR4 OCFBR3 OCFBR2 OCFBR1 OCFBR0
U3RXR5 U3RXR4 U3RXR3 U3RXR2 U3RXR1 U3RXR0
OCFAR5 OCFAR4 OCFAR3 OCFAR2 OCFAR1 OCFAR0 3F3F
—
—
—
—
—
—
3F00
3F3F
3F3F
3F3F
3F3F
3F3F
003F
3F3F
003F
U1CTSR5 U1CTSR4 U1CTSR3 U1CTSR2 U1CTSR1 U1CTSR0
U2CTSR5 U2CTSR4 U2CTSR3 U2CTSR2 U2CTSR1 U2CTSR0
U1RXR5 U1RXR4 U1RXR3 U1RXR2 U1RXR1 U1RXR0
U2RXR5 U2RXR4 U2RXR3 U2RXR2 U2RXR1 U2RXR0
SCK1R5
SCK1R4
SCK1R3
SCK1R2
SCK1R1
SCK1R0
SDI1R5
SS1R5
SDI2R5
SS2R5
SDI1R4
SS1R4
SDI2R4
SS2R4
SDI1R3
SS1R3
SDI2R3
SS2R3
SDI1R2
SS1R2
SDI2R2
SS2R2
SDI1R1
SS1R1
SDI2R1
SS2R1
SDI1R0
SS1R0
SDI2R0
SS2R0
RPINR21 06AA
RPINR22 06AC
RPINR23 06AE
U3CTSR5 U3CTSR4 U3CTSR3 U3CTSR2 U3CTSR1 U3CTSR0
SCK2R5
T1CKR5
SCK2R4
T1CKR4
SCK2R3
T1CKR3
SCK2R2
T1CKR2
SCK2R1
T1CKR1
SCK2R0
T1CKR0
RPINR27
06B6
U4CTSR5 U4CTSR4 U4CTSR3 U4CTSR2 U4CTSR1 U4CTSR0
U4RXR5 U4RXR4 U4RXR3 U4RXR2 U4RXR1 U4RXR0
MDMIR5 MDMIR4 MDMIR3 MDMIR2 MDMIR1 MDMIR0
RPINR30 06BC
RPINR31 06BE
—
—
—
—
—
—
MDC2R5 MDC2R4 MDC2R3 MDC2R2 MDC2R1 MDC2R0
MDC1R5 MDC1R4 MDC1R3 MDC1R2 MDC1R1 MDC1R0 3F3F
Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1: These bits are unimplemented in 64-pin devices, read as ‘0’.
2: These bits are unimplemented in 64-pin and 80-pin devices, read as ‘0’.
TABLE 4-30: PERIPHERAL PIN SELECT REGISTER MAP (CONTINUED)
File
Name
All
Resets
Addr
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
RPOR0
RPOR1
RPOR2
RPOR3
RPOR4
RPOR5
RPOR6
RPOR7
RPOR8
RPOR9
RPOR10
RPOR11
RPOR12
RPOR13
RPOR14
RPOR15
06C0
06C2
06C4
06C6
06C8
06CA
06CC
06CE
06D0
06D2
06D4
06D6
06D8
06DA
06DC
06DE
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
RP1R5
RP3R5
RP1R4
RP3R4
RP1R3
RP3R3
RP1R2
RP3R2
RP1R1
RP3R1
RP1R0
RP3R0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
RP0R5
RP2R5
RP4R5
RP6R5
RP8R5
RP0R4
RP2R4
RP4R4
RP6R4
RP8R4
RP0R3
RP2R3
RP4R3
RP6R3
RP8R3
RP0R2
RP2R2
RP4R2
RP6R2
RP8R2
RP0R1
RP2R1
RP4R1
RP6R1
RP8R1
RP0R0
RP2R0
RP4R0
RP6R0
RP8R0
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
RP5R5(1) RP5R4(1) RP5R3(1) RP5R2(1) RP5R1(1) RP5R0(1)
RP7R5
RP9R5
RP11R5
RP13R5
RP7R4
RP9R4
RP11R4
RP13R4
RP7R3
RP9R3
RP11R3
RP13R3
RP7R2
RP9R2
RP11R2
RP13R2
RP7R1
RP9R1
RP11R1
RP13R1
RP7R0
RP9R0
RP11R0
RP13R0
RP10R5 RP10R4 RP10R3 RP10R2 RP10R1 RP10R0
RP12R5 RP12R4 RP12R3 RP12R2 RP12R1 RP12R0
RP14R5 RP14R4 RP14R3 RP14R2 RP14R1 RP14R0
RP16R5 RP16R4 RP16R3 RP16R2 RP16R1 RP16R0
RP18R5 RP18R4 RP18R3 RP18R2 RP18R1 RP18R0
RP20R5 RP20R4 RP20R3 RP20R2 RP20R1 RP20R0
RP22R5 RP22R4 RP22R3 RP22R2 RP22R1 RP22R0
RP24R5 RP24R4 RP24R3 RP24R2 RP24R1 RP24R0
RP26R5 RP26R4 RP26R3 RP26R2 RP26R1 RP26R0
RP28R5 RP28R4 RP28R3 RP28R2 RP28R1 RP28R0
RP30R5 RP30R4 RP30R3 RP30R2 RP30R1 RP30R0
RP15R5(1) RP15R4(1) RP15R3(1) RP15R2(1) RP15R1(1) RP15R0(1)
RP17R5
RP19R5
RP21R5
RP23R5
RP25R5
RP27R5
RP29R5
RP17R4
RP19R4
RP21R4
RP23R4
RP25R4
RP27R4
RP29R4
RP17R3
RP19R3
RP21R3
RP23R3
RP25R3
RP27R3
RP29R3
RP17R2
RP19R2
RP21R2
RP23R2
RP25R2
RP27R2
RP29R2
RP17R1
RP19R1
RP21R1
RP23R1
RP25R1
RP27R1
RP29R1
RP17R0
RP19R0
RP21R0
RP23R0
RP25R0
RP27R0
RP29R0
RP31R5(2) RP31R4(2) RP31R3(2) RP31R2(2) RP31R1(2) RP31R0(2)
Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1: These bits are unimplemented in 64-pin devices, read as ‘0’.
2: These bits are unimplemented in 64-pin and 80-pin devices, read as ‘0’.
TABLE 4-31: SYSTEM CONTROL (CLOCK AND RESET) REGISTER MAP
All
Resets
File Name Addr
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
RCON
0740 TRAPR IOPUWR
—
RETEN
COSC0
DOZE0
—
—
—
DPSLP
NOSC2
CM
VREGS
EXTR
SWR
SWDTEN WDTO
SLEEP
CF
IDLE
BOR
POR
Note 1
OSCCON
CLKDIV
OSCTUN
0742
0744
0748
—
ROI
COSC2
DOZE2
—
COSC1
DOZE1
—
NOSC1
NOSC0 CLKLOCK IOLOCK
LOCK
—
—
—
POSCEN SOSCEN OSWEN Note 2
DOZEN RCDIV2 RCDIV1 RCDIV0
—
—
—
—
—
—
TUN2
—
—
TUN1
—
—
3100
0000
0000
0000
Note 1
—
—
—
—
—
TUN5
—
TUN4
—
TUN3
—
TUN0
—
REFOCON 074E
ROEN
LVDEN
—
—
ROSSLP ROSEL
RODIV3 RODIV2 RODIV1 RODIV0
—
—
LVDCON
RCON2
0756
0762
—
LSIDL
—
—
—
—
—
—
—
—
—
—
—
DIR
—
BGVST
—
IRVST
—
—
LVDL3
LVDL2
LVDL1
LVDL0
VBAT
—
r
VDDBOR VDDPOR VBPOR
Legend: — = unimplemented, read as ‘0’; r = reserved. Reset values are shown in hexadecimal.
Note 1: The Reset value of the RCON register is dependent on the type of Reset event. See Section 7.0 “Resets” for more information.
2: The Reset value of the OSCCON register is dependent on both the type of Reset event and the device configuration. See Section 9.0 “Oscillator Configuration” for more information.
TABLE 4-32: DEEP SLEEP REGISTER MAP
All
Resets
File Name Addr
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
DSCON
0758
075A
075C
075E
DSEN
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
r
DSBOR RELEASE 0000(1)
DSWAKE
DSGPR0
DSGPR1
DSINT0
DSFLT
DSWDT DSRTCC DSMCLR
—
—
0000(1)
0000(1)
0000(1)
Deep Sleep Semaphore Data 0
Deep Sleep Semaphore Data 1
Legend: — = unimplemented, read as ‘0’; r = reserved. Reset values are shown in hexadecimal.
Note 1: These registers are only reset on a VDD POR event.
TABLE 4-33: NVM REGISTER MAP
All
Resets
File Name Addr
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
NVMCON
NVMKEY
0760
0766
WR
—
WREN
—
WRERR
—
—
—
—
—
—
—
—
—
—
—
—
ERASE
—
—
NVMOP3 NVMOP2 NVMOP1 NVMOP0 0000(1)
NVMKEY Register<7:0>
0000
Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1: The Reset value shown is for POR only. The value on other Reset states is dependent on the state of memory write or erase operations at the time of Reset.
TABLE 4-34: PMD REGISTER MAP
All
Resets
File Name Addr
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PMD1
PMD2
PMD3
PMD4
PMD6
PMD7
0770
0772
0774
0776
077A
077C
T5MD
—
T4MD
IC7MD
—
T3MD
IC6MD
—
T2MD
IC5MD
—
T1MD
—
—
—
I2C1MD
—
U2MD
OC7MD
—
U1MD
SPI2MD SPI1MD
—
—
ADC1MD 0000
IC4MD
IC3MD
IC2MD
IC1MD
OC6MD OC5MD OC4MD OC3MD OC2MD OC1MD 0000
—
DSMMD CMPMD RTCCMD PMPMD CRCMD
—
—
—
—
U3MD
—
I2C2MD
—
—
0000
0000
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
UPWMMD U4MD
REFOMD CTMUMD LVDMD
—
—
—
—
LCDMD
—
—
—
—
—
—
—
—
SPI3MD 0000
0000
—
—
—
—
DMA1MD DMA0MD
—
Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
PIC24FJ128GA310 FAMILY
The data addressing range of PIC24FJ128GA310 family
devices depends on the version of the Enhanced
Parallel Master Port implemented on a particular device;
this is in turn a function of device pin count. Table 4-35
lists the total memory accessible by each of the devices
in this family. For more details on accessing external
memory using EPMP, refer to the “PIC24F Family Refer-
ence Manual”, Section 42. “Enhanced Parallel Master
Port (EPMP)” (DS39730).
4.2.5
EXTENDED DATA SPACE (EDS)
The Extended Data Space (EDS) allows PIC24F
devices to address a much larger range of data than
would otherwise be possible with a 16-bit address
range. EDS includes any additional internal data mem-
ory not directly accessible by the lower 32-Kbyte data
address space, and any external memory through
EPMP.
In addition, EDS also allows read access to the
program memory space. This feature is called Program
Space Visibility (PSV), and is discussed in detail in
Section 4.3.3 “Reading Data from Program Memory
Using EDS”.
.
TABLE 4-35: TOTAL ACCESSIBLE DATA
MEMORY
External RAM
Internal
RAM
Family
Access Using
EPMP
Figure 4-4 displays the entire EDS space. The EDS is
organized as pages, called EDS pages, with one page
equal to size of the EDS window (32 Kbytes). A partic-
ular EDS page is selected through the Data Space
Read register (DSRPAG) or Data Space Write register
(DSWPAG). For PSV, only the DSRPAG register is
used. The combination of the DSRPAG register value
and the 16-bit wide data address forms a 24-bit
Effective Address (EA).
PIC24FJXXXGA310
PIC24FJXXXGA308
PIC24FJXXXGA306
8K
8K
8K
Up to 16 MB
Up to 64K
Up to 64K
Note:
Accessing Page 0 in the EDS window will
generate an address error trap as Page 0
is the base data memory (data locations
0800h to 7FFFh in the lower data space).
FIGURE 4-4:
EXTENDED DATA SPACE
0000h
Special
Function
Registers
0800h
Internal
Data
Memory
Space
(up to
30 Kbytes)
EDS Pages
8000h
008000h
FF8000h
000000h
7F8000h
000001h
7F8001h
32-Kbyte
EDS
Window
Program
Space
Access
(Lower
Word)
Program
Space
Access
(Lower
Word)
Program
Space
Access
(Upper
Word)
Program
Space
Access
(Upper
External
Memory
Access
using
External
Memory
Access
using
Word)
EPMP(1)
EPMP(1)
00FFFEh
FFFFFEh
007FFEh
7FFFFEh
007FFFh
7FFFFFh
FFFEh
DSxPAG
= 001h
DSx PAG
= 1FFh
DSRPAG
= 200h
DSRPAG
= 2FFh
DSRPAG
= 300h
DSRPAG
= 3FFh
EPMP Memory Space(1)
The range of addressable memory available is dependent on the device pin count and EPMP implementation.
Program Memory
Note 1:
2010-2011 Microchip Technology Inc.
DS39996F-page 65
PIC24FJ128GA310 FAMILY
Example 4-1 shows how to read a byte, word and
double-word from EDS.
4.2.5.1
Data Read from EDS
In order to read the data from the EDS space, first, an
Address Pointer is set up by loading the required EDS
page number into the DSRPAG register and assigning
the offset address to one of the W registers. Once the
above assignment is done, the EDS window is enabled
by setting bit 15 of the working register, assigned with
the offset address; then, the contents of the pointed
EDS location can be read.
Note:
All read operations from EDS space have
an overhead of one instruction cycle.
Therefore, a minimum of two instruction
cycles is required to complete an EDS
read. EDS reads under the REPEAT
instruction; the first two accesses take
three cycles and the subsequent
accesses take one cycle.
Figure 4-5 illustrates how the EDS space address is
generated for read operations.
When the Most Significant bit (MSBs) of EA is ‘1’ and
DSRPAG<9> = 0, the lower 9 bits of DSRPAG are con-
catenated to the lower 15 bits of EA to form a 24-bit
EDS space address for read operations.
FIGURE 4-5:
EDS ADDRESS GENERATION FOR READ OPERATIONS
Select
1
Wn
0
9
8
DSRPAG Reg
9 Bits
15 Bits
24-Bit EA
0= Extended SRAM and EPMP
Wn<0> is Byte Select
EXAMPLE 4-1:
EDS READ CODE IN ASSEMBLY
; Set the EDS page from where the data to be read
mov
mov
mov
bset
#0x0002 , w0
w0 , DSRPAG
;page 2 is selected for read
#0x0800 , w1 ;select the location (0x800) to be read
w1 , #15 ;set the MSB of the base address, enable EDS mode
;Read a byte from the selected location
mov.b
mov.b
[w1++] ,
[w1++] , w3
w2 ;read Low byte
;read High byte
;Read a word from the selected location
mov [w1] , w2
;
;Read Double - word from the selected location
mov.d
[w1] , w2
;two word read, stored in w2 and w3
DS39996F-page 66
2010-2011 Microchip Technology Inc.
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While developing code in assembly, care must be taken
to update the page registers when an Address Pointer
crosses the page boundary. The ‘C’ compiler keeps
track of the addressing, and increments or decrements
the Page registers accordingly while accessing
contiguous data memory locations.
4.2.5.2
Data Write into EDS
In order to write data to EDS space, such as in EDS
reads, an Address Pointer is set up by loading the
required EDS page number into the DSWPAG register,
and assigning the offset address to one of the W regis-
ters. Once the above assignment is done, then the
EDS window is enabled by setting bit 15 of the working
register, assigned with the offset address, and the
accessed location can be written.
Note 1: All write operations to EDS are executed
in a single cycle.
2: Use of Read/Modify/Write operation on
any EDS location under a REPEAT
instruction is not supported. For example,
BCLR, BSW, BTG, RLC f, RLNC f,
RRC f, RRNC f, ADD f, SUB f,
SUBR f, AND f, IOR f, XOR f,
ASR f, ASL f.
Figure 4-2 illustrates how the EDS space address is
generated for write operations.
When the MSBs of EA are ‘1’, the lower 9 bits of
DSWPAG are concatenated to the lower 15 bits of EA
to form a 24-bit EDS address for write operations.
Example 4-2 shows how to write a byte, word and
double-word to EDS.
3: Use the DSRPAG register while
The Page registers (DSRPAG/DSWPAG) do not
update automatically while crossing a page boundary,
when the rollover happens from 0xFFFF to 0x8000.
performing Read/Modify/Write operations.
FIGURE 4-6:
EDS ADDRESS GENERATION FOR WRITE OPERATIONS
Select
Wn
1
8
0
DSWPAG Reg
9 Bits
15 Bits
24-Bit EA
Wn<0> is Byte Select
EXAMPLE 4-2:
EDS WRITE CODE IN ASSEMBLY
; Set the EDS page where the data to be written
mov
mov
mov
bset
#0x0002 , w0
w0 , DSWPAG
;page 2 is selected for write
#0x0800 , w1 ;select the location (0x800) to be written
w1 , #15 ;set the MSB of the base address, enable EDS mode
;Write a byte to the selected location
mov
mov
mov.b
mov.b
#0x00A5 , w2
#0x003C , w3
w2 , [w1++]
w3 , [w1++]
;write Low byte
;write High byte
;Write a word to the selected location
mov
mov
#0x1234 , w2
w2 , [w1]
;
;
;Write a Double - word to the selected location
mov
mov
mov.d
#0x1122 , w2
#0x4455 , w3
w2 , [w1]
;2 EDS writes
2010-2011 Microchip Technology Inc.
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TABLE 4-36: EDS MEMORY ADDRESS WITH DIFFERENT PAGES AND ADDRESSES
Source/Destination
DSRPAG
DSWPAG
Address while
Indirect
Addressing
24-Bit EA
Pointing to EDS
(Data Space Read (Data Space Write
Comment
Register)
Register)
x(1)
x(1)
0000h to 1FFFh
2000h to 7FFFh
000000h to
001FFFh
Near data space(2)
002000h to
007FFFh
001h
002h
001h
002h
008000h to
00FFFEh
010000h to
017FFEh
003h
003h
018000h to
0187FEh
•
•
EPMP memory space
•
•
•
•
8000h to FFFFh
•
•
•
•
•
•
•
•
FF8000h to
FFFFFEh
1FFh
1FFh
000h
000h
Invalid Address
Address error trap(3)
Note 1: If the source/destination address is below 8000h, the DSRPAG and DSWPAG registers are not considered.
2: This data space can also be accessed by Direct Addressing.
3: When the source/destination address is above 8000h and DSRPAG/DSWPAG are ‘0’, an address error
trap will occur.
example, if it is desirable to cause a stack error trap
when the stack grows beyond address 2000h in RAM,
initialize the SPLIM with the value, 1FFEh.
4.2.6
SOFTWARE STACK
Apart from its use as a working register, the W15
register in PIC24F devices is also used as a Software
Stack Pointer (SSP). The pointer always points to the
first available free word and grows from lower to higher
addresses. It pre-decrements for stack pops and
post-increments for stack pushes, as shown in
Figure 4-7. Note that for a PC push during any CALL
instruction, the MSB of the PC is zero-extended before
the push, ensuring that the MSB is always clear.
Similarly, a Stack Pointer underflow (stack error) trap is
generated when the Stack Pointer address is found to
be less than 0800h. This prevents the stack from
interfering with the SFR space.
A write to the SPLIM register should not be immediately
followed by an indirect read operation using W15.
FIGURE 4-7:
CALLSTACK FRAME
Note:
A PC push during exception processing
will concatenate the SRL register to the
MSB of the PC prior to the push.
0000h
15
0
The Stack Pointer Limit Value register (SPLIM), associ-
ated with the Stack Pointer, sets an upper address
boundary for the stack. SPLIM is uninitialized at Reset.
As is the case for the Stack Pointer, SPLIM<0> is
forced to ‘0’ as all stack operations must be
word-aligned. Whenever an EA is generated using
W15 as a source or destination pointer, the resulting
address is compared with the value in SPLIM. If the
contents of the Stack Pointer (W15) and the SPLIM reg-
ister are equal, and a push operation is performed, a
stack error trap will not occur. The stack error trap will
occur on a subsequent push operation. Thus, for
PC<15:0>
000000000
W15 (before CALL)
PC<22:16>
<Free Word>
W15 (after CALL)
POP : [--W15]
PUSH: [W15++]
DS39996F-page 68
2010-2011 Microchip Technology Inc.
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4.3.1
ADDRESSING PROGRAM SPACE
4.3
Interfacing Program and Data
Memory Spaces
Since the address ranges for the data and program
spaces are 16 and 24 bits, respectively, a method is
needed to create a 23-bit or 24-bit program address
from 16-bit data registers. The solution depends on the
interface method to be used.
The PIC24F architecture uses a 24-bit wide program
space and 16-bit wide data space. The architecture is
also a modified Harvard scheme, meaning that data
can also be present in the program space. To use this
data successfully, it must be accessed in a way that
preserves the alignment of information in both spaces.
For table operations, the 8-bit Table Memory Page
Address register (TBLPAG) is used to define a 32K word
region within the program space. This is concatenated
with a 16-bit EA to arrive at a full 24-bit program space
address. In this format, the MSBs of TBLPAG is used to
determine if the operation occurs in the user memory
Aside from normal execution, the PIC24F architecture
provides two methods by which program space can be
accessed during operation:
• Using table instructions to access individual bytes
or words anywhere in the program space
(TBLPAG<7>
(TBLPAG<7> = 1).
= 0) or the configuration memory
• Remapping a portion of the program space into
the data space (program space visibility)
For remapping operations, the 10-bit Extended Data
Space Read register (DSRPAG) is used to define a
16K word page in the program space. When the Most
Significant bit (MSb) of the EA is ‘1’, and the MSb (bit 9)
of DSRPAG is ‘1’, the lower 8 bits of DSRPAG are con-
catenated with the lower 15 bits of the EA to form a
23-bit program space address. The DSRPAG<8> bit
decides whether the lower word (when bit is ‘0’) or the
higher word (when bit is ‘1’) of program memory is
mapped. Unlike table operations, this strictly limits
remapping operations to the user memory area.
Table instructions allow an application to read or write
to small areas of the program memory. This makes the
method ideal for accessing data tables that need to be
updated from time to time. It also allows access to all
bytes of the program word. The remapping method
allows an application to access a large block of data on
a read-only basis, which is ideal for look ups from a
large table of static data. It can only access the least
significant word of the program word.
Table 4-37 and Figure 4-8 show how the program EA is
created for table operations and remapping accesses
from the data EA. Here, P<23:0> refers to a program
space word, whereas D<15:0> refers to a data space
word.
TABLE 4-37: PROGRAM SPACE ADDRESS CONSTRUCTION
Program Space Address
Access
Space
Access Type
<23>
<22:16>
<15>
<14:1>
<0>
Instruction Access
(Code Execution)
User
User
0
PC<22:1>
0
0xx xxxx xxxx xxxx xxxx xxx0
TBLPAG<7:0> Data EA<15:0>
0xxx xxxx
TBLRD/TBLWT
(Byte/Word Read/Write)
xxxx xxxx xxxx xxxx
Data EA<15:0>
Configuration
TBLPAG<7:0>
1xxx xxxx
xxxx xxxx xxxx xxxx
Data EA<14:0>(1)
Program Space Visibility User
(Block Remap/Read)
0
0
DSRPAG<7:0>(2)
xxxx xxxx
xxx xxxx xxxx xxxx
Note 1: Data EA<15> is always ‘1’ in this case, but is not used in calculating the program space address. Bit 15 of
the address is DSRPAG<0>.
2: DSRPAG<9> is always ‘1’ in this case. DSRPAG<8> decides whether the lower word or higher word of
program memory is read. When DSRPAG<8> is ‘0’, the lower word is read and when it is ‘1’, the higher
word is read.
2010-2011 Microchip Technology Inc.
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FIGURE 4-8:
DATA ACCESS FROM PROGRAM SPACE ADDRESS GENERATION
Program Counter
Program Counter
23 Bits
0
0
EA
1/0
(2)
1/0
TBLPAG
8 Bits
Table Operations
16 Bits
24 Bits
Select
1
1/0
EA
(1)
Program Space Visibility
(Remapping)
0
DSRPAG<7:0>
8 Bits
1-Bit
15 Bits
23 Bits
User/Configuration
Space Select
Byte Select
Note 1: DSRPAG<8> acts as word select. DSRPAG<9> should always be ‘1’ to map program memory to data memory.
2: The instructions, TBLRDH/TBLWTH/TBLRDL/TBLWTL, decide if the higher or lower word of program memory is
accessed. TBLRDH/TBLWTHinstructions access the higher word and TBLRDL/TBLWTLinstructions access the
lower word. Table read operations are permitted in the configuration memory space.
DS39996F-page 70
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2. TBLRDH (Table Read High): In Word mode, it
maps the entire upper word of a program address
(P<23:16>) to a data address. Note that
D<15:8>, the ‘phantom’ byte, will always be ‘0’.
4.3.2
DATA ACCESS FROM PROGRAM
MEMORY USING TABLE
INSTRUCTIONS
The TBLRDL and TBLWTL instructions offer a direct
method of reading or writing the lower word of any
address within the program space without going through
data space. The TBLRDH and TBLWTH instructions are
the only method to read or write the upper 8 bits of a
program space word as data.
In Byte mode, it maps the upper or lower byte of
the program word to D<7:0> of the data
address, as above. Note that the data will
always be ‘0’ when the upper ‘phantom’ byte is
selected (byte select = 1).
In a similar fashion, two table instructions, TBLWTH
and TBLWTL, are used to write individual bytes or
words to a program space address. The details of
their operation are described in Section 6.0 “Flash
Program Memory”.
The PC is incremented by two for each successive
24-bit program word. This allows program memory
addresses to directly map to data space addresses.
Program memory can thus be regarded as two, 16-bit
word-wide address spaces, residing side by side, each
with the same address range. TBLRDL and TBLWTL
access the space which contains the least significant
data word, and TBLRDHand TBLWTHaccess the space
which contains the upper data byte.
For all table operations, the area of program memory
space to be accessed is determined by the Table
Memory Page Address register (TBLPAG). TBLPAG
covers the entire program memory space of the
device, including user and configuration spaces. When
TBLPAG<7> = 0, the table page is located in the user
memory space. When TBLPAG<7> = 1, the page is
located in configuration space.
Two table instructions are provided to move byte or
word-sized (16-bit) data to and from program space.
Both function as either byte or word operations.
1. TBLRDL (Table Read Low): In Word mode, it
maps the lower word of the program space
location (P<15:0>) to a data address (D<15:0>).
Note:
Only table read operations will execute in
the configuration memory space where
Device IDs are located. Table write
operations are not allowed.
In Byte mode, either the upper or lower byte of
the lower program word is mapped to the lower
byte of a data address. The upper byte is
selected when byte select is ‘1’; the lower byte
is selected when it is ‘0’.
FIGURE 4-9:
ACCESSING PROGRAM MEMORY WITH TABLE INSTRUCTIONS
Program Space
TBLPAG
02
Data EA<15:0>
23
15
0
000000h
23
16
8
0
00000000
00000000
00000000
00000000
020000h
030000h
‘Phantom’ Byte
TBLRDH.B (Wn<0> = 0)
TBLRDL.B (Wn<0> = 1)
TBLRDL.B (Wn<0> = 0)
TBLRDL.W
The address for the table operation is determined by the data EA
within the page defined by the TBLPAG register.
Only read operations are shown; write operations are also valid in
the user memory area.
800000h
2010-2011 Microchip Technology Inc.
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Table 4-38 provides the corresponding 23-bit EDS
address for program memory with EDS page and
source addresses.
4.3.3
READING DATA FROM PROGRAM
MEMORY USING EDS
The upper 32 Kbytes of data space may optionally be
mapped into any 16K word page of the program space.
This provides transparent access of stored constant
data from the data space without the need to use
special instructions (i.e., TBLRDL/H).
For operations that use PSV and are executed outside
a REPEATloop, the MOV and MOV.Dinstructions will
require one instruction cycle in addition to the specified
execution time. All other instructions will require two
instruction cycles in addition to the specified execution
time.
Program space access through the data space occurs
when the MSb of EA is ‘1’ and the DSRPAG<9> is also
‘1’. The lower 8 bits of DSRPAG are concatenated to the
Wn<14:0> bits to form a 23-bit EA to access program
memory. The DSRPAG<8> decides which word should
be addressed; when the bit is ‘0’, the lower word and
when ‘1’, the upper word of the program memory is
accessed.
For operations that use PSV, which are executed inside
a REPEAT loop, there will be some instances that
require two instruction cycles in addition to the
specified execution time of the instruction:
• Execution in the first iteration
• Execution in the last iteration
The entire program memory is divided into 512 EDS
pages, from 200h to 3FFh, each consisting of 16K words
of data. Pages, 200h to 2FFh, correspond to the lower
words of the program memory, while 300h to 3FFh
correspond to the upper words of the program memory.
• Execution prior to exiting the loop due to an
interrupt
• Execution upon re-entering the loop after an
interrupt is serviced
Any other iteration of the REPEAT loop will allow the
instruction accessing data, using PSV, to execute in a
single cycle.
Using this EDS technique, the entire program memory
can be accessed. Previously, the access to the upper
word of the program memory was not supported.
TABLE 4-38: EDS PROGRAM ADDRESS WITH DIFFERENT PAGES AND ADDRESSES
DSRPAG
Source Address while
Indirect Addressing
23-Bit EA Pointing to
EDS
(Data Space Read
Register)
Comment
200h
8000h to FFFFh
000000h to 007FFEh
Lower words of 4M program
instructions; (8 Mbytes) for
read operations only.
•
•
•
•
•
•
2FFh
7F8000h to 7FFFFEh
300h
000001h to 007FFFh
Upper words of 4M program
instructions (4 Mbytes remaining;
4 Mbytes are phantom bytes) for
read operations only.
•
•
•
•
•
•
3FFh
7F8001h to 7FFFFFh
000h
Invalid Address
Address error trap(1)
Note 1: When the source/destination address is above 8000h and DSRPAG/DSWPAG is ‘0’, an address error trap
will occur.
EXAMPLE 4-3:
EDS READ CODE FROM PROGRAM MEMORY IN ASSEMBLY
; Set the EDS page from where the data to be read
mov
mov
mov
bset
#0x0202 , w0
w0 , DSRPAG
#0x000A , w1
w1 , #15
;page 0x202, consisting lower words, is selected for read
;select the location (0x0A) to be read
;set the MSB of the base address, enable EDS mode
;Read a byte from the selected location
mov.b
mov.b
[w1++] , w2
[w1++] , w3
;read Low byte
;read High byte
;Read a word from the selected location
mov
[w1] , w2
;
;Read Double - word from the selected location
mov.d [w1] , w2 ;two word read, stored in w2 and w3
DS39996F-page 72
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FIGURE 4-10:
PROGRAM SPACE VISIBILITY OPERATION TO ACCESS LOWER WORD
When DSRPAG<9:8> = 10and EA<15> = 1
Program Space
Data Space
DSRPAG
202h
23
15
0
000000h
0000h
Data EA<14:0>
010000h
017FFEh
The data in the page
designated by DSRPAG
is mapped into the
upper half of the data
memory space....
8000h
EDS Window
...while the lower
15 bits of the EA
specify an exact
address within the
EDS area. This corre-
sponds exactly to the
same lower 15 bits of
the actual program
space address.
FFFFh
7FFFFEh
FIGURE 4-11:
PROGRAM SPACE VISIBILITY OPERATION TO ACCESS UPPER WORD
When DSRPAG<9:8> = 11and EA<15> = 1
Program Space
Data Space
DSRPAG
302h
23
15
0
000000h
0000h
Data EA<14:0>
010001h
017FFFh
The data in the page
designated by DSRPAG
is mapped into the
upper half of the data
memory space....
8000h
EDS Window
...while the lower
15 bits of the EA
specify an exact
address within the
EDS area. This corre-
sponds exactly to the
same lower 15 bits of
the actual program
space address.
FFFFh
7FFFFEh
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NOTES:
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The controller also monitors CPU instruction process-
ing directly, allowing it to be aware of when the CPU
requires access to peripherals on the DMA bus, and
automatically relinquishing control to the CPU as
needed. This increases the effective bandwidth for
handling data without DMA operations causing a
processor stall. This makes the controller essentially
transparent to the user.
5.0
DIRECT MEMORY ACCESS
CONTROLLER (DMA)
Note:
This data sheet summarizes the features
of the PIC24FJ128GA310 family of
devices. It is not intended to be a compre-
hensive reference source. To complement
the information in this data sheet, refer to
the “PIC24F Family Reference Manual”,
Section 54. “Direct Memory Access
Controller (DMA)” (DS39742). The infor-
mation in this data sheet supersedes the
information in the FRM.
The DMA Controller has these features:
• Six multiple independent and independently
programmable channels
• Concurrent operation with the CPU (no DMA
caused Wait states)
The Direct Memory Access Controller (DMA) is
designed to service high-data-throughput peripherals
operating on the SFR bus, allowing them to access
data memory directly and alleviating the need for CPU
intensive management. By allowing these data inten-
sive peripherals to share their own data path, the main
data bus is also de-loaded, resulting in additional
power savings.
• DMA bus arbitration
• Five Programmable Address modes
• Four Programmable Transfer modes
• Four Flexible Internal Data Transfer modes
• Byte or word support for data transfer
• 16-Bit Source and Destination Address register
for each channel, dynamically updated and
reloadable
The DMA Controller functions both as a peripheral and
a direct extension of the CPU. It is located on the micro-
controller data bus between the CPU and
DMA-enabled peripherals, with direct access to SRAM.
This partitions the SFR bus into two buses, allowing the
DMA Controller access to the DMA-capable peripher-
als located on the new DMA SFR bus. The controller
serves as a master device on the DMA SFR bus,
controlling data flow from DMA capable peripherals.
• 16-Bit Transaction Count register, dynamically
updated and reloadable
• Upper and Lower Address Limit registers
• Counter half-full level interrupt
• Software triggered transfer
• Null Write mode for symmetric buffer operations
A simplified block diagram of the DMA Controller is
shown if Figure 5-1.
FIGURE 5-1:
DMA FUNCTIONAL BLOCK DIAGRAM
CPU Execution Monitoring
To DMA-Enabled
Peripherals
To I/O Ports
and Peripherals
DMACON
DMAH
Control
Logic
DMAL
DMABUF
Data
Bus
DMACH0
DMAINT0
DMASRC0
DMADST0
DMACNT0
DMACH1
DMAINT1
DMASRC1
DMADST1
DMACNT1
DMACH2
DMACHn
DMAINTn
DMASRCn
DMADSTn
DMACNTn
DMAINT2
DMASRC2
DMADST2
DMACNT2
Channel 4
Channel 5
Channel 0
Channel 1
Data RAM
Data RAM
Address Generation
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Since the source and destination addresses for any
transaction can be programmed independently of the
trigger source, the DMA Controller can use any trigger
to perform an operation on any peripheral. This also
allows DMA channels to be cascaded to perform more
complex transfer operations.
5.1
Summary of DMA Operations
The DMA Controller is capable of moving data between
addresses according to a number of different parame-
ters. Each of these parameters can be independently
configured for any transaction; in addition, any or all of
the DMA channels can independently perform a differ-
ent transaction at the same time. Transactions are
classified by these parameters:
5.1.4
TRANSFER MODE
The DMA Controller supports four types of data trans-
fers, based on the volume of data to be moved for each
trigger.
• Source and destination (SFRs and data RAM)
• Data Size (byte or word)
• Trigger source
• One-Shot: A single transaction occurs for each
trigger.
• Transfer mode (One-Shot, Repeated or
Continuous)
• Continuous: A series of back-to-back transactions
occur for each trigger; the number of transactions
is determined by the DMACNT transaction
counter.
• Addressing modes (fixed address or address
blocks, with or without address increment/
decrement)
• Repeated One-Shot: A single transaction is per-
formed repeatedly, once per trigger, until the DMA
channel is disabled.
In addition, the DMA controller provides channel priority
arbitration for all channels.
5.1.1
SOURCE AND DESTINATION
• Repeated Continuous: A series of transactions
are performed repeatedly, one cycle per trigger,
until the DMA channel is disabled.
Using the DMA Controller, data may be moved
between any two addresses in the data space. The
SFR space (0000h to 07FFh) or the data RAM space
(0800h to FFFFh) can serve as either the source or the
destination. Data can be moved between these areas
in either direction, or between addresses in either area.
The four different combinations are shown in
Figure 5-2.
All transfer modes allow the option to have the source
and destination addresses and counter value automat-
ically reloaded after the completion of a transaction.
Repeated mode transfers do this automatically.
5.1.5
ADDRESSING MODES
If it is necessary to protect areas of data RAM, the DMA
Controller allows the user to set upper and lower address
boundaries for operations in the data space above the
SFR space. The boundaries are set by the DMAH and
DMAL Limit registers. If a DMA channel attempts an
operation outside of the address boundaries, the
transaction is terminated and an interrupt is generated.
The DMA Controller also supports transfers between
single addresses or address ranges. The four basic
options are:
• Fixed-to-Fixed: Between two constant addresses
• Fixed-to-Block: From a constant source address
to a range of destination addresses
• Block-to-Fixed: From a range of source
addresses to a single, constant destination
address
5.1.2
DATA SIZE
The DMA Controller can handle both 8-bit and 16-bit
transactions. Size is user-selectable using the SIZE bit
(DMACHn<1>). By default, each channel is configured
for word-size transactions. When byte-size transac-
tions are chosen, the LSb of the source and/or
destination address determines if the data represents
the upper or lower byte of the data RAM location.
• Block-to-Block: From a range to source
addresses to a range of destination addresses
The option to select auto-increment or auto-decrement
of source and/or destination addresses is available for
Block Addressing modes.
In addition to the four basic modes, the DMA Controller
also supports Peripheral Indirect Addressing (PIA)
mode, where the source or destination address is gen-
erated jointly by the DMA controller and a PIA capable
peripheral. When enabled, the DMA channel provides
a base source and/or destination address, while the
peripheral provides a fixed-range offset address.
5.1.3
TRIGGER SOURCE
The DMA Controller can use any one of the device’s
60 interrupt sources to initiate a transaction. The DMA
trigger sources are listed in reverse order their natural
interrupt priority, and are shown in Table 5-1.
For PIC24FJ128GA310 family devices, the 12-bit A/D
Converter module is the only PIA-capable peripheral.
Details for its use in PIA mode are provided in
Section 24.0 “12-Bit A/D Converter with Threshold
Scan”.
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FIGURE 5-2:
TYPES OF DMA DATA TRANSFERS
Peripheral to Memory
SFR Area
Memory to Peripheral
SFR Area
DMASRCn
DMADSTn
07FFh
0800h
07FFh
0800h
Data RAM
Data RAM
DMAL
DMAL
DMA RAM Area
DMA RAM Area
DMADSTn
DMAH
DMASRCn
DMAH
Peripheral to Peripheral
SFR Area
Memory to Memory
SFR Area
DMASRCn
DMADSTn
07FFh
0800h
07FFh
0800h
Data RAM
Data RAM
DMAL
DMAL
DMAH
DMA RAM Area
DMA RAM Area
DMASRCn
DMADSTn
DMAH
Note:
Relative sizes of memory areas are not shown to scale.
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5.1.6
CHANNEL PRIORITY
5.3
Peripheral Module Disable
Each DMA channel functions independently of the oth-
ers, but also competes with the others for access to the
data and DMA busses. When access collisions occur,
the DMA Controller arbitrates between the channels
using a user-selectable priority scheme. Two schemes
are available:
Unlike other peripheral modules, the channels of the
DMA Controller cannot be individually powered down
using the Peripheral Module Disable (PMD) registers.
Instead, the channels are controlled as two groups.
The DMA0MD bit (PMD7<4>) selectively controls
DMACH0 through DMACH3. The DMA1MD bit
(PMD7<5>) controls DMACH4 and DMACH5. Setting
both bits effectively disables the DMA Controller.
• Round-Robin: When two or more channels col-
lide, the lower-numbered channel receives priority
on the first collision. On subsequent collisions, the
higher numbered channels each receive priority,
based on their channel number.
5.4
Registers
The DMA Controller uses a number of registers to con-
trol its operation. The number of registers depends on
the number of channels implemented for a particular
device.
• Fixed: When two or more channels collide, the
lowest numbered channel always receives
priority, regardless of past history.
There are always four module level registers (one
control and three buffer/address):
5.2
Typical Setup
To set up a DMA channel for a basic data transfer:
• DMACON: DMA Control Register (Register 5-1)
1. Enable the DMA Controller (DMAEN = 1) and
select an appropriate channel priority scheme
by setting or clearing PRSSEL.
• DMAH and DMAL: High and Low Address Limit
Registers
• DMABUF: DMA Data Buffer
2. Program DMAH and DMAL with appropriate
upper and lower address boundaries for data
RAM operations.
Each of the DMA channels implements five registers
(two control and three buffer/address):
• DMACHn: DMA Channel Control Register
(Register 5-2)
3. Select the DMA channel to be used and disable
its operation (CHEN = 0).
• DMAINTn: DMA Channel Interrupt Control Register
(Register 5-3)
4. Program the appropriate Source and Destination
addresses for the transaction into the channel’s
DMASRCn and DMADSTn registers. For PIA
mode addressing, use the base address value.
• DMASRCn: Data Source Address Pointer for
Channel n
5. Program the DMACNTn register for the number
of triggers per transfer (One-Shot or Continuous
modes), or the number of words (bytes) to be
transferred (Repeated modes).
• DMADSTn: Data Destination Source for Channel n
• DMACNTn: Transaction Counter for Channel n
For PIC24FJ128GA310 family devices, there are a
total of 34 registers.
6. Set or clear the SIZE bit to select the data size.
7. Program the TRMODE bits to select the Data
Transfer mode.
8. Program the SAMODE and DAMODE bits to
select the addressing mode.
9. Enable the DMA channel by setting CHEN.
10. Enable the trigger source interrupt.
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REGISTER 5-1:
DMACON: DMA ENGINE CONTROL REGISTER
R/W-0
DMAEN
bit 15
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
bit 8
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
R/W-0
PRSSEL
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15
DMAEN: DMA Module Enable bit
1= Enables module
0= Disables module and terminates all active DMA operation(s)
bit 14-1
bit 0
Unimplemented: Read as ‘0’
PRSSEL: Channel Priority Scheme Selection bit
1= Round-robin scheme
0= Fixed priority scheme
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REGISTER 5-2:
DMACHn: DMA CHANNEL n CONTROL REGISTER
U-0
—
U-0
—
U-0
—
r-0
r
R/W-0
—
R/W-0
R/W-0
RELOAD(1)
R/W-0
CHREQ(3)
NULLW
bit 15
bit 8
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
SIZE
R/W-0
CHEN
SAMODE1
bit 7
SAMODE0
DAMODE1
DAMODE0
TRMODE1
TRMODE0
bit 0
Legend:
r = Reserved bit
W = Writable bit
‘1’ = Bit is set
R = Readable bit
-n = Value at POR
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-12
bit 12
Unimplemented: Read as ‘0’
Reserved: Maintain as ‘0’
Unimplemented: Read as ‘0’
NULLW: Null Write Mode bit
bit 11
bit 10
1= A dummy write is initiated to DMASRC for every write to DMADST
0= No dummy write is initiated
bit 9
RELOAD: Address and Count Reload bit(1)
1= DMASRC, DMADST, and DMACNT registers are reloaded to their previous values upon the start
of the next operation
0= DMASRC, DMADST and DMACNT are not reloaded on the start of the next operation(2)
bit 8
CHREQ: DMA Channel Software Request bit(3)
1= A DMA request is initiated by software; automatically cleared upon completion of a DMA transfer
0= No DMA request is pending
bit 7-6
SAMODE<1:0>: Source Address Mode Selection bits
11= DMASRC is used in Peripheral Indirect Addressing and remains unchanged
10= DMASRC is decremented based on SIZE bit after a transfer completion
01= DMASRC is incremented based on SIZE bit after a transfer completion
00= DMASRC remains unchanged after a transfer completion
bit 5-4
bit 3-2
DAMODE<1:0>: Destination Address Mode Selection bits
11= DMADST is used in Peripheral Indirect Addressing and remains unchanged
10= DMADST is decremented based on SIZE bit after a transfer completion
01= DMADST is incremented based on SIZE bit after a transfer completion
00= DMADST remains unchanged after a transfer completion
TRMODE<1:0>: Transfer Mode Selection bits
11= Repeated Continuous
10= Continuous
01= Repeated One-Shot
00= One-Shot
bit 1
bit 0
SIZE: Data Size Selection bit
1= Byte (8-bit)
0= Word (16-bit)
CHEN: DMA Channel Enable bit
1= The corresponding channel is enabled
0= The corresponding channel is disabled
Note 1: Only the original DMACNT is required to be stored to recover the original DMASRC and DMADST.
2: DMASRC, DMADST and DMACNT are always reloaded in Repeated mode transfers (DMACHn<2> = 1),
regardless of the state of the RELOAD bit.
3: The number of transfers executed while CHREQ is set depends on the configuration of TRMODE<1:0>.
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REGISTER 5-3:
DMAINTn: DMA CHANNEL n INTERRUPT REGISTER
R-0
DBUFWF(1)
bit 15
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
CHSEL5
CHSEL4
CHSEL3
CHSEL2
CHSEL1
CHSEL0
bit 8
R/W-0
HIGHIF(1,2)
R/W-0
LOWIF(1,2)
R/W-0
DONEIF(1)
R/W-0
HALFIF(1)
R/W-0
OVRUNIF(1)
U-0
—
U-0
—
R/W-0
HALFEN
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15
DBUFWF: Buffered Data Write Flag bit(1)
1= The content of the DMA buffer has not been written to the location specified in DMADST, or
DMASRC in Null Write mode
0= The content of the DMA buffer has been written to the location specified in DMADST, or DMASRC
in Null Write mode
bit 14
Unimplemented: Read as ‘0’
bit 13-8
CHSEL<5:0>: DMA Channel Trigger Selection bits
See Table 5-1 for a complete list.
bit 7
bit 6
bit 5
HIGHIF: DMA High Address Limit Interrupt Flag bit(1,2)
1= The DMA channel has attempted to access an address higher than DMAH, or the upper limit of the
data RAM space.
0= The DMA channel has not invoked the high address limit interrupt.
LOWIF: DMA Low Address Limit Interrupt Flag bit(1,2)
1= The DMA channel has attempted to access the DMA SFR address lower than DMAL, but above
the SFR range (07FFh)
0= The DMA channel has not invoked the low address limit interrupt
DONEIF: DMA Complete Operation Interrupt Flag bit(1)
If CHEN = 1:
1= The previous DMA session has ended with completion
0= The current DMA session has not yet completed
If CHEN = 0:
1= The previous DMA session has ended with completion
0= The previous DMA session has ended without completion
bit 4
bit 3
HALFIF: DMA 50% Water Mark Level Interrupt Flag bit(1)
1= DMACNT has reached the halfway point to 0000h
0= DMACNT has not reached the halfway point
OVRUNIF: DMA Channel Overrun Flag bit(1)
1= The DMA channel is triggered while it is still completing the operation based on the previous trigger
0= The overrun condition has not occurred
bit 2-1
bit 0
Unimplemented: Read as ‘0’
HALFEN: Halfway Completion Water Mark bit
1= Interrupts are invoked when DMACNT has reached its halfway point and at completion
0= An interrupt is invoked only at the completion of the transfer
Note 1: Setting these flags in software does not generate an interrupt.
2: Testing for address limit violations (DMASRC or DMADST is either greater than DMAH or less than
DMAL) is NOT done before the actual access.
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TABLE 5-1:
CHSEL<5:0>
DMA TRIGGER SOURCES
Trigger (Interrupt)
CHSEL<5:0>
Trigger (Interrupt)
000000
000001
000010
000011
000100
000101
000110
000111
001000
001001
001010
001011
001100
001101
001110
001111
010000
010001
010010
010011
010100
010101
010110
010111
011000
011001
011010
011011
011100
011101
011110
011111
(Unimplemented)
JTAG
100000
100001
100010
100011
100100
100101
100110
100111
101000
101001
101010
101011
101100
101101
101110
101111
110000
110001
110010
110011
110100
110101
110110
110111
111000
111001
111010
111011
111100
111101
111110
111111
UART2 Transmit
UART2 Receive
External Interrupt 2
Timer5
LCD
UART4 Transmit
UART4 Receive
UART4 Error
UART3 Transmit
UART3 Receive
UART3 Error
CTMU Event
HLVD
Timer4
Output Compare 4
Output Compare 3
DMA Channel 2
Input Capture 7
External Interrupt 1
Interrupt-on-Change
Comparators Event
I2C1 Master Event
I2C1 Slave Event
DMA Channel 1
A/D Converter
UART1 Transmit
UART1 Receive
SPI1 Event
CRC Done
UART2 Error
UART1 Error
RTCC
DMA Channel 5
External Interrupt 4
External Interrupt 3
I2C2 Master Event
I2C2 Slave Event
DMA Channel 4
EPMP
SPI1 Error
Timer3
Timer2
Output Compare 7
Output Compare 6
Output Compare 5
Input Capture 6
Input Capture 5
Input Capture 4
Input Capture 3
DMA Channel 3
SPI2 Event
Output Compare 2
Input Capture 2
DMA Channel 0
Timer1
Output Compare 1
Input Capture 1
External Interrupt 0
(Unimplemented)
(Unimplemented)
(Unimplemented)
SPI2 Error
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microcontroller just before shipping the product. This
also allows the most recent firmware or a custom
firmware to be programmed.
6.0
FLASH PROGRAM MEMORY
Note:
This data sheet summarizes the features of
this group of PIC24F devices. It is not
intended to be a comprehensive reference
source. For more information, refer to the
“PIC24F Family Reference Manual”,
RTSP is accomplished using TBLRD (table read) and
TBLWT (table write) instructions. With RTSP, the user
may write program memory data in blocks of 64 instruc-
tions (192 bytes) at a time and erase program memory
in blocks of 512 instructions (1536 bytes) at a time.
Section
4.
“Program
Memory”
(DS39715). The information in this data
sheet supersedes the information in the
FRM.
6.1
Table Instructions and Flash
Programming
The PIC24FJ128GA310 family of devices contains
internal Flash program memory for storing and execut-
ing application code. The program memory is readable,
writable and erasable. The Flash can be programmed
in four ways:
Regardless of the method used, all programming of
Flash memory is done with the table read and write
instructions. These allow direct read and write access to
the program memory space from the data memory while
the device is in normal operating mode. The 24-bit target
address in the program memory is formed using the
TBLPAG<7:0> bits and the Effective Address (EA) from
a W register, specified in the table instruction, as shown
in Figure 6-1.
• In-Circuit Serial Programming™ (ICSP™)
• Run-Time Self-Programming (RTSP)
• JTAG
• Enhanced In-Circuit Serial Programming
(Enhanced ICSP)
The TBLRDLand the TBLWTLinstructions are used to
read or write to bits<15:0> of program memory.
TBLRDLand TBLWTLcan access program memory in
both Word and Byte modes.
ICSP allows a PIC24FJ128GA310 family device to be
serially programmed while in the end application circuit.
This is simply done with two lines for the programming
clock and programming data (named PGECx and
PGEDx, respectively), and three other lines for power
(VDD), ground (VSS) and Master Clear (MCLR). This
allows customers to manufacture boards with
unprogrammed devices and then program the
The TBLRDHand TBLWTHinstructions are used to read
or write to bits<23:16> of program memory. TBLRDH
and TBLWTHcan also access program memory in Word
or Byte mode.
FIGURE 6-1:
ADDRESSING FOR TABLE REGISTERS
24 Bits
Program Counter
Using
Program
Counter
0
0
Working Reg EA
Using
Table
Instruction
1
/
0
TBLPAG Reg
8 Bits
16 Bits
User/Configuration
Space Select
Byte
Select
24-Bit EA
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6.2
RTSP Operation
6.3
JTAG Operation
The PIC24F Flash program memory array is organized
into rows of 64 instructions or 192 bytes. RTSP allows
the user to erase blocks of eight rows (512 instructions)
at a time and to program one row at a time. It is also
possible to program single words.
The PIC24F family supports JTAG boundary scan.
Boundary scan can improve the manufacturing
process by verifying pin to PCB connectivity.
6.4
Enhanced In-Circuit Serial
Programming
The 8-row erase blocks and single row write blocks are
edge-aligned, from the beginning of program memory, on
boundaries of 1536 bytes and 192 bytes, respectively.
Enhanced In-Circuit Serial Programming uses an
on-board bootloader, known as the program executive,
to manage the programming process. Using an SPI
data frame format, the program executive can erase,
program and verify program memory. For more
information on Enhanced ICSP, see the device
programming specification.
When data is written to program memory using TBLWT
instructions, the data is not written directly to memory.
Instead, data written using table writes is stored in
holding latches until the programming sequence is
executed.
Any number of TBLWT instructions can be executed
and a write will be successfully performed. However,
64 TBLWTinstructions are required to write the full row
of memory.
6.5
Control Registers
There are two SFRs used to read and write the
program Flash memory: NVMCON and NVMKEY.
To ensure that no data is corrupted during a write, any
unused address should be programmed with
FFFFFFh. This is because the holding latches reset to
an unknown state, so if the addresses are left in the
Reset state, they may overwrite the locations on rows
which were not rewritten.
The NVMCON register (Register 6-1) controls which
blocks are to be erased, which memory type is to be
programmed and when the programming cycle starts.
NVMKEY is a write-only register that is used for write
protection. To start a programming or erase sequence,
the user must consecutively write 55h and AAh to the
NVMKEY register. Refer to Section 6.6 “Programming
Operations” for further details.
The basic sequence for RTSP programming is to set up
a Table Pointer, then do a series of TBLWTinstructions
to load the buffers. Programming is performed by
setting the control bits in the NVMCON register.
6.6
Programming Operations
Data can be loaded in any order and the holding regis-
ters can be written to multiple times before performing
a write operation. Subsequent writes, however, will
wipe out any previous writes.
A complete programming sequence is necessary for
programming or erasing the internal Flash in RTSP
mode. During a programming or erase operation, the
processor stalls (Waits) until the operation is finished.
Setting the WR bit (NVMCON<15>) starts the opera-
tion and the WR bit is automatically cleared when the
operation is finished.
Note:
Writing to a location multiple times without
erasing is not recommended.
All of the table write operations are single-word writes
(2 instruction cycles), because only the buffers are writ-
ten. A programming cycle is required for programming
each row.
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REGISTER 6-1:
NVMCON: FLASH MEMORY CONTROL REGISTER
R/S-0, HC(1)
WR
R/W-0(1)
WREN
R-0, HSC(1)
WRERR
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
bit 15
bit 8
U-0
—
R/W-0(1)
ERASE
U-0
—
U-0
—
R/W-0(1)
R/W-0(1)
R/W-0(1)
R/W-0(1)
NVMOP3(2) NVMOP2(2) NVMOP1(2) NVMOP0(2)
bit 7
bit 0
Legend:
S = Settable bit
W = Writable bit
‘1’ = Bit is set
HC = Hardware Clearable bit
R = Readable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘0’ = Bit is cleared
x = Bit is unknown
HSC = Hardware Settable/Clearable bit
bit 15
WR: Write Control bit(1)
1= Initiates a Flash memory program or erase operation; the operation is self-timed and the bit is
cleared by hardware once the operation is complete
0= Program or erase operation is complete and inactive
bit 14
bit 13
WREN: Write Enable bit(1)
1= Enable Flash program/erase operations
0= Inhibit Flash program/erase operations
WRERR: Write Sequence Error Flag bit(1)
1= An improper program or erase sequence attempt or termination has occurred (bit is set
automatically on any set attempt of the WR bit)
0= The program or erase operation completed normally
bit 12-7
bit 6
Unimplemented: Read as ‘0’
ERASE: Erase/Program Enable bit(1)
1= Perform the erase operation specified by NVMOP<3:0> on the next WR command
0= Perform the program operation specified by NVMOP<3:0> on the next WR command
bit 5-4
bit 3-0
Unimplemented: Read as ‘0’
NVMOP<3:0>: NVM Operation Select bits(1,2)
1111= Memory bulk erase operation (ERASE = 1) or no operation (ERASE = 0)(3)
0011= Memory word program operation (ERASE = 0) or no operation (ERASE = 1)
0010= Memory page erase operation (ERASE = 1) or no operation (ERASE = 0)
0001= Memory row program operation (ERASE = 0) or no operation (ERASE = 1)
Note 1: These bits can only be reset on a Power-on Reset.
2: All other combinations of NVMOP<3:0> are unimplemented.
3: Available in ICSP™ mode only; refer to the device programming specification.
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4. Write the first 64 instructions from data RAM into
the program memory buffers (see Example 6-3).
6.6.1
PROGRAMMING ALGORITHM FOR
FLASH PROGRAM MEMORY
5. Write the program block to Flash memory:
The user can program one row of Flash program memory
at a time. To do this, it is necessary to erase the 8-row
erase block containing the desired row. The general
process is:
a) Set the NVMOP bits to ‘0001’ to configure
for row programming. Clear the ERASE bit
and set the WREN bit.
b) Write 55h to NVMKEY.
c) Write AAh to NVMKEY.
1. Read eight rows of program memory
(512 instructions) and store in data RAM.
d) Set the WR bit. The programming cycle
begins and the CPU stalls for the duration
of the write cycle. When the write to Flash
memory is done, the WR bit is cleared
automatically.
2. Update the program data in RAM with the
desired new data.
3. Erase the block (see Example 6-1):
a) Set the NVMOP bits (NVMCON<3:0>) to
‘0010’ to configure for block erase. Set the
ERASE (NVMCON<6>) and WREN
(NVMCON<14>) bits.
6. Repeat Steps 4 and 5, using the next available
64 instructions from the block in data RAM by
incrementing the value in TBLPAG, until all
512 instructions are written back to Flash
memory.
b) Write the starting address of the block to be
erased into the TBLPAG and W registers.
c) Write 55h to NVMKEY.
d) Write AAh to NVMKEY.
For protection against accidental operations, the write
initiate sequence for NVMKEY must be used to allow
any erase or program operation to proceed. After the
programming command has been executed, the user
must wait for the programming time until programming
is complete. The two instructions following the start of
the programming sequence should be NOPs, as shown
in Example 6-4.
e) Set the WR bit (NVMCON<15>). The erase
cycle begins and the CPU stalls for the dura-
tion of the erase cycle. When the erase is
done, the WR bit is cleared automatically.
EXAMPLE 6-1:
ERASING A PROGRAM MEMORY BLOCK (ASSEMBLY LANGUAGE CODE)
; Set up NVMCON for block erase operation
MOV
MOV
#0x4042, W0 ;
W0, NVMCON
; Initialize NVMCON
; Init pointer to row to be ERASED
MOV
MOV
MOV
#tblpage(PROG_ADDR), W0
W0, TBLPAG
#tbloffset(PROG_ADDR), W0
;
; Initialize Program Memory (PM) Page Boundary SFR
; Initialize in-page EA<15:0> pointer
; Set base address of erase block
; Block all interrupts with priority <7
; for next 5 instructions
TBLWTL W0, [W0]
DISI #5
MOV.B #0x55, W0
MOV W0, NVMKEY
MOV.B #0xAA, W1 ;
; Write the 0x55 key
MOV
BSET
NOP
NOP
W1, NVMKEY
NVMCON, #WR
; Write the 0xAA key
; Start the erase sequence
; Insert two NOPs after the erase
; command is asserted
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EXAMPLE 6-2:
ERASING A PROGRAM MEMORY BLOCK (‘C’ LANGUAGE CODE)
// C example using MPLAB C30
unsigned long progAddr = 0xXXXXXX;
unsigned int offset;
// Address of row to write
//Set up pointer to the first memory location to be written
TBLPAG = progAddr>>16;
// Initialize PM Page Boundary SFR
offset = progAddr & 0xFFFF;
__builtin_tblwtl(offset, 0x0000);
// Initialize lower word of address
// Set base address of erase block
// with dummy latch write
NVMCON = 0x4042;
asm("DISI #5");
// Initialize NVMCON
// Block all interrupts with priority <7
// for next 5 instructions
__builtin_write_NVM();
// check function to perform unlock
// sequence and set WR
EXAMPLE 6-3:
LOADING THE WRITE BUFFERS
; Set up NVMCON for row programming operations
MOV
MOV
#0x4001, W0
W0, NVMCON
;
; Initialize NVMCON
; Set up a pointer to the first program memory location to be written
; program memory selected, and writes enabled
MOV
MOV
MOV
#0x0000, W0
W0, TBLPAG
#0x6000, W0
;
; Initialize PM Page Boundary SFR
; An example program memory address
; Perform the TBLWT instructions to write the latches
; 0th_program_word
MOV
MOV
#LOW_WORD_0, W2
#HIGH_BYTE_0, W3
;
;
TBLWTL W2, [W0]
TBLWTH W3, [W0++]
; Write PM low word into program latch
; Write PM high byte into program latch
; 1st_program_word
MOV
MOV
#LOW_WORD_1, W2
#HIGH_BYTE_1, W3
;
;
TBLWTL W2, [W0]
TBLWTH W3, [W0++]
; Write PM low word into program latch
; Write PM high byte into program latch
;
2nd_program_word
MOV
MOV
#LOW_WORD_2, W2
#HIGH_BYTE_2, W3
;
;
TBLWTL W2, [W0]
TBLWTH W3, [W0++]
; Write PM low word into program latch
; Write PM high byte into program latch
•
•
•
; 63rd_program_word
MOV
MOV
#LOW_WORD_63, W2
#HIGH_BYTE_63, W3
;
;
TBLWTL W2, [W0]
TBLWTH W3, [W0]
; Write PM low word into program latch
; Write PM high byte into program latch
EXAMPLE 6-4:
INITIATING A PROGRAMMING SEQUENCE
DISI
#5
; Block all interrupts with priority <7
; for next 5 instructions
MOV.B
MOV
MOV.B
MOV
BSET
NOP
#0x55, W0
W0, NVMKEY
#0xAA, W1
W1, NVMKEY
NVMCON, #WR
; Write the 0x55 key
;
; Write the 0xAA key
; Start the programming sequence
; Required delays
NOP
BTSC
BRA
NVMCON, #15
$-2
; and wait for it to be
; completed
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write latches and specify the lower 16 bits of the pro-
gram memory address to write to. To configure the
NVMCON register for a word write, set the NVMOP bits
(NVMCON<3:0>) to ‘0011’. The write is performed by
executing the unlock sequence and setting the WR bit
(see Example 6-5). An equivalent procedure in ‘C’
compiler, using the MPLAB C30 compiler and built-in
hardware functions, is shown in Example 6-6.
6.6.2
PROGRAMMING A SINGLE WORD
OF FLASH PROGRAM MEMORY
If a Flash location has been erased, it can be pro-
grammed using table write instructions to write an
instruction word (24-bit) into the write latch. The
TBLPAG register is loaded with the 8 Most Significant
Bytes (MSBs) of the Flash address. The TBLWTLand
TBLWTH instructions write the desired data into the
EXAMPLE 6-5:
PROGRAMMING A SINGLE WORD OF FLASH PROGRAM MEMORY
; Setup a pointer to data Program Memory
MOV
MOV
MOV
#tblpage(PROG_ADDR), W0
W0, TBLPAG
#tbloffset(PROG_ADDR), W0
;
;Initialize PM Page Boundary SFR
;Initialize a register with program memory address
MOV
MOV
#LOW_WORD_N, W2
#HIGH_BYTE_N, W3
;
;
TBLWTL W2, [W0]
TBLWTH W3, [W0++]
; Write PM low word into program latch
; Write PM high byte into program latch
; Setup NVMCON for programming one word to data Program Memory
MOV
MOV
#0x4003, W0
W0, NVMCON
;
; Set NVMOP bits to 0011
DISI
MOV.B
MOV
MOV.B
MOV
#5
; Disable interrupts while the KEY sequence is written
; Write the key sequence
#0x55, W0
W0, NVMKEY
#0xAA, W0
W0, NVMKEY
NVMCON, #WR
BSET
NOP
; Start the write cycle
; Required delays
NOP
EXAMPLE 6-6:
PROGRAMMING A SINGLE WORD OF FLASH PROGRAM MEMORY
(‘C’ LANGUAGE CODE)
// C example using MPLAB C30
unsigned int offset;
unsigned long progAddr = 0xXXXXXX;
unsigned int progDataL = 0xXXXX;
unsigned char progDataH = 0xXX;
// Address of word to program
// Data to program lower word
// Data to program upper byte
//Set up NVMCON for word programming
NVMCON = 0x4003;
// Initialize NVMCON
//Set up pointer to the first memory location to be written
TBLPAG = progAddr>>16;
// Initialize PM Page Boundary SFR
offset = progAddr & 0xFFFF;
// Initialize lower word of address
//Perform TBLWT instructions to write latches
__builtin_tblwtl(offset, progDataL);
__builtin_tblwth(offset, progDataH);
asm(“DISI #5”);
// Write to address low word
// Write to upper byte
// Block interrupts with priority <7
// for next 5 instructions
// C30 function to perform unlock
// sequence and set WR
__builtin_write_NVM();
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Any active source of Reset will make the SYSRST
signal active. Many registers associated with the CPU
7.0
RESETS
Note:
This data sheet summarizes the features of
this group of PIC24F devices. It is not
intended to be a comprehensive reference
source. For more information, refer to the
“PIC24F Family Reference Manual”,
Section 7. “Reset” (DS39712). The infor-
mation in this data sheet supersedes the
information in the FRM.
and peripherals are forced to a known Reset state.
Most registers are unaffected by a Reset; their status is
unknown on POR and unchanged by all other Resets.
Note:
Refer to the specific peripheral or CPU
section of this manual for register Reset
states.
All types of device Reset will set a corresponding status
bit in the RCON register to indicate the type of Reset
(see Register 7-1). In addition, Reset events occurring
while an extreme power-saving feature is in use (such
as VBAT) will set one or more status bits in the RCON2
register (Register 7-2). A POR will clear all bits, except
for the BOR and POR (RCON<1:0>) bits, which are
set. The user may set or clear any bit at any time during
code execution. The RCON bits only serve as status
bits. Setting a particular Reset status bit in software will
not cause a device Reset to occur.
The Reset module combines all Reset sources and
controls the device Master Reset Signal, SYSRST. The
following is a list of device Reset sources:
• POR: Power-on Reset
• MCLR: Pin Reset
• SWR: RESETInstruction
• WDT: Watchdog Timer Reset
• BOR: Brown-out Reset
• CM: Configuration Mismatch Reset
• TRAPR: Trap Conflict Reset
• IOPUWR: Illegal Opcode Reset
• UWR: Uninitialized W Register Reset
The RCON register also has other bits associated with
the Watchdog Timer and device power-saving states.
The function of these bits is discussed in other sections
of this data sheet.
A simplified block diagram of the Reset module is
shown in Figure 7-1.
Note:
The status bits in the RCON registers
should be cleared after they are read so
that the next RCON register values after a
device Reset will be meaningful.
FIGURE 7-1:
RESET SYSTEM BLOCK DIAGRAM
RESET
Instruction
Glitch Filter
MCLR
WDT
Module
Sleep or Idle
POR
BOR
VDD Rise
Detect
SYSRST
VDD
Brown-out
Reset
Enable Voltage Regulator
Trap Conflict
Illegal Opcode
Configuration Mismatch
Uninitialized W Register
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REGISTER 7-1:
RCON: RESET CONTROL REGISTER
R/W-0
TRAPR(1)
R/W-0
IOPUWR(1)
U-0
—
R/W-0
RETEN(2)
U-0
—
R/W-0
DPSLP(1)
R/W-0
CM(1)
R/W-0
VREGS(3)
bit 15
bit 8
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-1
R/W-1
EXTR(1)
SWR(1)
SWDTEN(4)
WDTO(1)
SLEEP(1)
IDLE(1)
BOR(1)
POR(1)
bit 7
bit 0
Legend:
U = Unimplemented bit, read as ‘0’
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
HS = Hardware Settable bit
‘0’ = Bit is cleared
x = Bit is unknown
bit 15
bit 14
TRAPR: Trap Reset Flag bit(1)
1= A Trap Conflict Reset has occurred
0= A Trap Conflict Reset has not occurred
IOPUWR: Illegal Opcode or Uninitialized W Access Reset Flag bit(1)
1= An illegal opcode detection, an illegal address mode or uninitialized W register is used as an
Address Pointer and caused a Reset
0= An illegal opcode or uninitialized W Reset has not occurred
bit 13-10
bit 12
Unimplemented: Read as ‘0’
RETEN: Retention Mode Enable bit(2)
1= Retention mode is enabled while device is in Sleep modes (1.2V regulator supplies to the core)
0= Retention mode is disabled; normal voltage levels are present
bit 11
bit 10
Unimplemented: Read as ‘0’
DPSLP: Deep Sleep Flag bit(1)
1= Device has been in Deep Sleep mode
0= Device has not been in Deep Sleep mode
bit 9
bit 8
bit 7
bit 6
CM: Configuration Word Mismatch Reset Flag bit(1)
1= A Configuration Word Mismatch Reset has occurred
0= A Configuration Word Mismatch Reset has not occurred
VREGS: Program Memory Power During Sleep bit(3)
1= Program memory bias voltage remains powered during Sleep
0= Program memory bias voltage is powered down during Sleep
EXTR: External Reset (MCLR) Pin bit(1)
1= A Master Clear (pin) Reset has occurred
0= A Master Clear (pin) Reset has not occurred
SWR: Software Reset (Instruction) Flag bit(1)
1= A RESETinstruction has been executed
0= A RESETinstruction has not been executed
Note 1: All of the Reset status bits may be set or cleared in software. Setting one of these bits in software does not
cause a device Reset.
2: If the LPCFG Configuration bit is 1’ (unprogrammed), the retention regulator is disabled and the RETEN bit
has no effect.
3: Re-enabling the regulator after it enters Standby mode will add a delay, TVREG, when waking up from
Sleep. Applications that do not use the voltage regulator should set this bit to prevent this delay from
occurring.
4: If the FWDTEN Configuration bit is ‘1’ (unprogrammed), the WDT is always enabled, regardless of the
SWDTEN bit setting.
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REGISTER 7-1:
RCON: RESET CONTROL REGISTER (CONTINUED)
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
SWDTEN: Software Enable/Disable of WDT bit(4)
1= WDT is enabled
0= WDT is disabled
WDTO: Watchdog Timer Time-out Flag bit(1)
1= WDT time-out has occurred
0= WDT time-out has not occurred
SLEEP: Wake From Sleep Flag bit(1)
1= Device has been in Sleep mode
0= Device has not been in Sleep mode
IDLE: Wake-up From Idle Flag bit(1)
1= Device has been in Idle mode
0= Device has not been in Idle mode
BOR: Brown-out Reset Flag bit(1)
1= A Brown-out Reset has occurred (also set after a Power-on Reset).
0= A Brown-out Reset has not occurred
POR: Power-on Reset Flag bit(1)
1= A Power-on Reset has occurred
0= A Power-on Reset has not occurred
Note 1: All of the Reset status bits may be set or cleared in software. Setting one of these bits in software does not
cause a device Reset.
2: If the LPCFG Configuration bit is 1’ (unprogrammed), the retention regulator is disabled and the RETEN bit
has no effect.
3: Re-enabling the regulator after it enters Standby mode will add a delay, TVREG, when waking up from
Sleep. Applications that do not use the voltage regulator should set this bit to prevent this delay from
occurring.
4: If the FWDTEN Configuration bit is ‘1’ (unprogrammed), the WDT is always enabled, regardless of the
SWDTEN bit setting.
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REGISTER 7-2:
RCON2: RESET AND SYSTEM CONTROL REGISTER 2
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
bit 15
bit 8
U-0
—
U-0
—
U-0
—
r-0
r
R/CO-1
R/CO-1
R/CO-1
R/CO-0
VBAT(1)
VDDBOR(1) VDDPOR(1,2) VBPOR(1,3)
bit 7
bit 0
Legend:
CO = Clearable Only bit
W = Writable bit
r = Reserved bit
R = Readable bit
-n = Value at POR
U = Unimplemented bit, read as ‘0’
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-5
bit 4
Unimplemented: Read as ‘0’
Reserved: Maintain as ‘0’
bit 3
VDDBOR: VDD Brown-out Reset Flag bit(1)
1= A VDD Brown-out Reset has occurred (set by hardware)
0= A VDD Brown-out Reset has not occurred
bit 2
bit 1
VDDPOR: VDD Power-On Reset Flag bit(1,2)
1= A VDD Power-up Reset has occurred (set by hardware)
0= A VDD Power-up Reset has not occurred
VBPOR: VBPOR Flag bit(1,3)
1= A VBAT POR has occurred (no battery connected to VBAT pin, or VBAT power below Deep Sleep
Semaphore retention level, set by hardware)
0= A VBAT POR has not occurred
bit 0
VBAT: VBAT Flag bit(1)
1= A POR exit has occurred while power was applied to VBAT pin (set by hardware)
0= A POR exit from VBAT has not occurred
Note 1: This bit is set in hardware only; it can only be cleared in software.
2: Indicates a VDD POR. Setting the POR bit (RCON<0>) indicates a VCORE POR.
3: This bit is set when the device is originally powered up, even if power is present on VBAT.
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TABLE 7-1:
RESET FLAG BIT OPERATION
Setting Event
Flag Bit
Clearing Event
TRAPR (RCON<15>)
IOPUWR (RCON<14>)
CM (RCON<9>)
Trap Conflict Event
POR
POR
POR
POR
POR
Illegal Opcode or Uninitialized W Register Access
Configuration Mismatch Reset
MCLR Reset
EXTR (RCON<7>)
SWR (RCON<6>)
WDTO (RCON<4>)
RESETInstruction
WDT Time-out
CLRWDT, PWRSAV
Instruction, POR
SLEEP (RCON<3>)
DPSLP (RCON<10>)
IDLE (RCON<2>)
BOR (RCON<1>)
POR (RCON<0>)
PWRSAV #0Instruction
PWRSAV #0Instruction while DSEN bit set
PWRSAV #1Instruction
POR, BOR
POR
POR
POR
—
POR
—
Note:
All Reset flag bits may be set or cleared by the user software.
7.1
Special Function Register Reset
States
7.3
Brown-out Reset (BOR)
PIC24FJ128GA310 family devices implement a BOR
circuit that provides the user with several configuration
and power-saving options. The BOR is controlled by
the BOREN (CW3<12>) Configuration bit.
Most of the Special Function Registers (SFRs) associ-
ated with the PIC24F CPU and peripherals are reset to a
particular value at a device Reset. The SFRs are
grouped by their peripheral or CPU function and their
Reset values are specified in each section of this manual.
When BOR is enabled, any drop of VDD below the BOR
threshold results in a device BOR. Threshold levels are
described in Section 32.1 “DC Characteristics”
(Parameter DC17).
The Reset value for each SFR does not depend on the
type of Reset, with the exception of four registers. The
Reset value for the Reset Control register, RCON, will
depend on the type of device Reset. The Reset value
for the Oscillator Control register, OSCCON, will
depend on the type of Reset and the programmed
values of the FNOSC bits in Flash Configuration
Word 2 (CW2) (see Table 7-2). The RCFGCAL and
NVMCON registers are only affected by a POR.
7.4
Clock Source Selection at Reset
If clock switching is enabled, the system clock source
at device Reset is chosen, as shown in Table 7-2. If
clock switching is disabled, the system clock source is
always selected according to the Oscillator Configura-
tion bits. Refer to the “PIC24F Family Reference
Manual”, Section 6.0 “Oscillator” (DS39700) for
further details.
7.2
Device Reset Times
The Reset times for various types of device Reset are
summarized in Table 7-3. Note that the system Reset
signal, SYSRST, is released after the POR delay time
expires.
TABLE 7-2:
OSCILLATOR SELECTION vs.
TYPE OF RESET (CLOCK
SWITCHING ENABLED)
The time at which the device actually begins to execute
code will also depend on the system oscillator delays,
which include the Oscillator Start-up Timer (OST) and
the PLL lock time. The OST and PLL lock times occur
in parallel with the applicable SYSRST delay times.
Reset Type
Clock Source Determinant
POR
BOR
FNOSC Configuration bits
(CW2<10:8>)
MCLR
WDTO
SWR
COSC Control bits
(OSCCON<14:12>)
The Fail-Safe Clock Monitor (FSCM) delay determines
the time at which the FSCM begins to monitor the
system clock source after the SYSRST signal is
released.
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TABLE 7-3:
Reset Type
POR
RESET DELAY TIMES FOR VARIOUS DEVICE RESETS
System Clock
Delay
Clock Source
SYSRST Delay
Notes
1, 2, 3
EC
TPOR + TSTARTUP + TRST
TPOR + TSTARTUP + TRST
TPOR + TSTARTUP + TRST
TPOR + TSTARTUP + TRST
TPOR + TSTARTUP + TRST
TPOR + TSTARTUP + TRST
TPOR + TSTARTUP + TRST
TSTARTUP + TRST
TSTARTUP + TRST
TSTARTUP + TRST
TSTARTUP + TRST
TSTARTUP + TRST
TSTARTUP + TRST
TSTARTUP + TRST
TRST
—
ECPLL
TLOCK
1, 2, 3, 5
1, 2, 3, 4, 8
1, 2, 3, 4, 5, 8
1, 2, 3, 6, 7
1, 2, 3, 5, 6
1, 2, 3, 6
2, 3
XT, HS, SOSC
XTPLL, HSPLL
FRC, FRCDIV
FRCPLL
TOST
TOST + TLOCK
TFRC
TFRC + TLOCK
LPRC
TLPRC
BOR
EC
—
ECPLL
TLOCK
2, 3, 5
2, 3, 4, 8
2, 3, 4, 5, 8
2, 3, 6, 7
2, 3, 5, 6
2, 3, 6
3
XT, HS, SOSC
XTPLL, HSPLL
FRC, FRCDIV
FRCPLL
TOST
TOST + TLOCK
TFRC
TFRC + TLOCK
LPRC
TLPRC
—
MCLR
WDT
Any Clock
Any Clock
Any clock
TRST
—
3
Software
TRST
—
3
Illegal Opcode Any Clock
Uninitialized W Any Clock
TRST
—
3
TRST
—
3
Trap Conflict
Any Clock
TRST
—
3
Note 1: TPOR = Power-on Reset delay (10 s nominal).
2: TSTARTUP = TVREG (10 s nominal when VREGS = 1and when VREGS = 0;depends upon
WDTWIN<1:0> bits setting).
3: TRST = Internal State Reset time (2 s nominal).
4: TOST = Oscillator Start-up Timer (OST). A 10-bit counter counts 1024 oscillator periods before releasing
the oscillator clock to the system.
5: TLOCK = PLL lock time.
6: TFRC and TLPRC = RC oscillator start-up times.
7: If Two-speed Start-up is enabled, regardless of the primary oscillator selected, the device starts with FRC
so the system clock delay is just TFRC, and in such cases, FRC start-up time is valid. It switches to the
primary oscillator after its respective clock delay.
8: TOST = Oscillator Start-up Timer (OST). A 10-bit counter waits 1024 oscillator periods before releasing the
oscillator clock to the system.
The device will not begin to execute code until a valid
clock source has been released to the system. There-
fore, the oscillator and PLL start-up delays must be
considered when the Reset delay time must be known.
7.4.1
POR AND LONG OSCILLATOR
START-UP TIMES
The oscillator start-up circuitry and its associated delay
timers are not linked to the device Reset delays that
occur at power-up. Some crystal circuits (especially
low-frequency crystals) will have a relatively long
start-up time. Therefore, one or more of the following
conditions is possible after SYSRST is released:
7.4.2
FAIL-SAFE CLOCK MONITOR
(FSCM) AND DEVICE RESETS
If the FSCM is enabled, it will begin to monitor the
system clock source when SYSRST is released. If a
valid clock source is not available at this time, the
device will automatically switch to the FRC oscillator
and the user can switch to the desired crystal oscillator
in the Trap Service Routine (TSR).
• The oscillator circuit has not begun to oscillate.
• The Oscillator Start-up Timer has not expired (if a
crystal oscillator is used).
• The PLL has not achieved a lock (if PLL is used).
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8.1.1
ALTERNATE INTERRUPT VECTOR
TABLE
8.0
INTERRUPT CONTROLLER
Note:
This data sheet summarizes the features of
this group of PIC24F devices. It is not
intended to be a comprehensive reference
source. For more information, refer to the
“PIC24F Family Reference Manual”,
Section 8. “Interrupts” (DS39707). The
information in this data sheet supersedes
the information in the FRM.
The Alternate Interrupt Vector Table (AIVT) is located
after the IVT, as shown in Figure 8-1. The ALTIVT
(INTCON2<15>) control bit provides access to the
AIVT. If the ALTIVT bit is set, all interrupt and exception
processes will use the alternate vectors instead of the
default vectors. The alternate vectors are organized in
the same manner as the default vectors.
The AIVT supports emulation and debugging efforts by
providing a means to switch between an application
and a support environment without requiring the inter-
rupt vectors to be reprogrammed. This feature also
enables switching between applications for evaluation
of different software algorithms at run time. If the AIVT
is not needed, the AIVT should be programmed with
the same addresses used in the IVT.
The PIC24F interrupt controller reduces the numerous
peripheral interrupt request signals to a single interrupt
request signal to the PIC24F CPU. It has the following
features:
• Up to 8 processor exceptions and software traps
• Seven user-selectable priority levels
• Interrupt Vector Table (IVT) with up to 118 vectors
• Unique vector for each interrupt or exception
source
8.2
Reset Sequence
A device Reset is not a true exception because the
interrupt controller is not involved in the Reset process.
The PIC24F devices clear their registers in response to
a Reset, which forces the PC to zero. The micro-
controller then begins program execution at location,
000000h. The user programs a GOTOinstruction at the
Reset address, which redirects program execution to
the appropriate start-up routine.
• Fixed priority within a specified user priority level
• Alternate Interrupt Vector Table (AIVT) for debug
support
• Fixed interrupt entry and return latencies
8.1
Interrupt Vector Table
The Interrupt Vector Table (IVT) is shown in Figure 8-1.
The IVT resides in program memory, starting at location,
000004h. The IVT contains 126 vectors, consisting of
8 non-maskable trap vectors, plus up to 118 sources of
interrupt. In general, each interrupt source has its own
vector. Each interrupt vector contains a 24-bit wide
address. The value programmed into each interrupt vec-
tor location is the starting address of the associated
Interrupt Service Routine (ISR).
Note:
Any unimplemented or unused vector
locations in the IVT and AIVT should be
programmed with the address of a default
interrupt handler routine that contains a
RESETinstruction.
Interrupt vectors are prioritized in terms of their natural
priority; this is linked to their position in the vector table.
All other things being equal, lower addresses have a
higher natural priority. For example, the interrupt asso-
ciated with Vector 0 will take priority over interrupts at
any other vector address.
PIC24FJ128GA310
family
devices
implement
non-maskable traps and unique interrupts. These are
summarized in Table 8-1 and Table 8-2.
2010-2011 Microchip Technology Inc.
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FIGURE 8-1:
PIC24F INTERRUPT VECTOR TABLE
Reset – GOTOInstruction
Reset – GOTOAddress
Reserved
000000h
000002h
000004h
Oscillator Fail Trap Vector
Address Error Trap Vector
Stack Error Trap Vector
Math Error Trap Vector
Reserved
Reserved
Reserved
Interrupt Vector 0
Interrupt Vector 1
—
000014h
—
—
Interrupt Vector 52
Interrupt Vector 53
Interrupt Vector 54
—
00007Ch
00007Eh
000080h
(1)
Interrupt Vector Table (IVT)
—
—
Interrupt Vector 116
Interrupt Vector 117
Reserved
0000FCh
0000FEh
000100h
000102h
Reserved
Reserved
Oscillator Fail Trap Vector
Address Error Trap Vector
Stack Error Trap Vector
Math Error Trap Vector
Reserved
Reserved
Reserved
Interrupt Vector 0
Interrupt Vector 1
—
000114h
—
—
Interrupt Vector 52
Interrupt Vector 53
Interrupt Vector 54
—
00017Ch
00017Eh
000180h
(1)
Alternate Interrupt Vector Table (AIVT)
—
—
Interrupt Vector 116
Interrupt Vector 117
Start of Code
0001FEh
000200h
Note 1: See Table 8-2 for the interrupt vector list.
TABLE 8-1:
TRAP VECTOR DETAILS
IVT Address
Vector Number
AIVT Address
Trap Source
0
1
2
3
4
5
6
7
000004h
000006h
000008h
00000Ah
00000Ch
00000Eh
000010h
000012h
000104h
000106h
000108h
00010Ah
00010Ch
00010Eh
000110h
000112h
Reserved
Oscillator Failure
Address Error
Stack Error
Math Error
Reserved
Reserved
Reserved
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TABLE 8-2:
IMPLEMENTED INTERRUPT VECTORS
Interrupt Bit Locations
Enable
Vector
Number
IVT
Address
AIVT
Address
Interrupt Source
Flag
Priority
ADC1 Conversion Done
Comparator Event
CRC Generator
13
18
67
77
4
00002Eh
000038h
00009Ah
0000AEh
00001Ch
000030h
000044h
00005Ch
000070h
00008Eh
000014h
00003Ch
00004Eh
00007Eh
000080h
000036h
000034h
000078h
000076h
000016h
00001Eh
00005Eh
000060h
000062h
000064h
000040h
0000FEh
00003Ah
0000DCh
0000A4h
000018h
000020h
000046h
000048h
000066h
000068h
00006Ah
00006Eh
000090h
000026h
000028h
000054h
000056h
00012Eh
000138h
00019Ah
0001AEh
00011Ch
000130h
000144h
00015Ch
000170h
00018Eh
000114h
00013Ch
00014Eh
00017Eh
000180h
000136h
000134h
000178h
000176h
000116h
00011Eh
00015Eh
000160h
000162h
000164h
000140h
0001FEh
00013Ah
0001DCh
0001A4h
000118h
000120h
000146h
000148h
000166h
000168h
00016Ah
00016Eh
000190h
000126h
000128h
000154h
000156h
IFS0<13>
IFS1<2>
IFS4<3>
IFS4<13>
IFS0<4>
IFS0<14>
IFS1<8>
IFS2<4>
IFS2<14>
IFS3<13>
IFS0<0>
IFS1<4>
IFS1<13>
IFS3<5>
IFS3<6>
IFS1<1>
IFS1<0>
IFS3<2>
IFS3<1>
IFS0<1>
IFS0<5>
IFS2<5>
IFS2<6>
IFS2<7>
IFS2<8>
IFS1<6>
IFS7<5>
IFS1<3>
IFS6<4>
IFS4<8>
IFS0<2>
IFS0<6>
IFS1<9>
IFS1<10>
IFS2<9>
IFS2<10>
IFS2<11>
IFS2<13>
IFS3<14>
IFS0<9>
IFS0<10>
IFS2<0>
IFS2<1>
IEC0<13>
IEC1<2>
IEC4<3>
IEC4<13>
IEC0<4>
IEC0<14>
IEC1<8>
IEC2<4>
IEC2<14>
IEC3<13>
IEC0<0>
IEC1<4>
IEC1<13>
IEC3<5>
IEC3<6>
IEC1<1>
IEC1<0>
IEC3<2>
IEC3<1>
IEC0<1>
IEC0<5>
IEC2<5>
IEC2<6>
IEC2<7>
IEC2<8>
IEC1<6>
IEC7<5>
IEC1<3>
IEC6<4>
IEC4<8>
IEC0<2>
IEC0<6>
IEC1<9>
IEC1<10>
IEC2<9>
IEC2<10>
IEC2<11>
IEC2<13>
IEC3<14>
IEC0<9>
IEC0<10>
IEC2<0>
IEC2<1>
IPC3<6:4>
IPC4<10:8>
IPC16<14:12>
IPC19<6:4>
IPC1<2:0>
CTMU Event
DMA Channel 0
DMA Channel 1
14
24
36
46
61
0
IPC3<10:8>
IPC6<2:0>
DMA Channel 2
DMA Channel 3
IPC9<2:0>
DMA Channel 4
IPC11<10:8>
IPC15<6:4>
IPC0<2:0>
DMA Channel 5
External Interrupt 0
External Interrupt 1
External Interrupt 2
External Interrupt 3
External Interrupt 4
I2C1 Master Event
I2C1 Slave Event
I2C2 Master Event
I2C2 Slave Event
Input Capture 1
20
29
53
54
17
16
50
49
1
IPC5<2:0>
IPC7<6:4>
IPC13<6:4>
IPC13<10:8>
IPC4<6:4>
IPC4<2:0>
IPC12<10:8>
IPC12<6:4>
IPC0<6:4>
Input Capture 2
5
IPC1<6:4>
Input Capture 3
37
38
39
40
22
117
19
100
72
2
IPC9<6:4>
Input Capture 4
IPC9<10:8>
IPC9<14:12>
IPC10<2:0>
IPC5<10:8>
IPC29<6:4>
IPC4<14:12>
IPC25<2:0>
IPC18<2:0>
IPC0<10:8>
IPC1<10:8>
IPC6<6:4>
Input Capture 5
Input Capture 6
Input Capture 7
JTAG
Input Change Notification (ICN)
LCD Controller
Low-Voltage Detect (LVD)
Output Compare 1
Output Compare 2
Output Compare 3
Output Compare 4
Output Compare 5
Output Compare 6
Output Compare 7
Enhanced Parallel Master Port (EPMP)
Real-Time Clock and Calendar (RTCC)
SPI1 Error
6
25
26
41
42
43
45
62
9
IPC6<10:8>
IPC10<6:4>
IPC10<10:8>
IPC10<14:12>
IPC11<6:4>
IPC15<10:8>
IPC2<6:4>
SPI1 Event
10
32
33
IPC2<10:8>
IPC8<2:0>
SPI2 Error
SPI2 Event
IPC8<6:4>
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TABLE 8-2:
IMPLEMENTED INTERRUPT VECTORS (CONTINUED)
Interrupt Bit Locations
Enable
Vector
Number
IVT
Address
AIVT
Address
Interrupt Source
Flag
Priority
Timer1
3
00001Ah
000022h
000024h
00004Ah
00004Ch
000096h
00002Ah
00002Ch
000098h
000050h
000052h
0000B6h
0000B8h
0000BAh
0000C2h
0000C4h
0000C6h
00011Ah
000122h
000124h
00014Ah
00014Ch
000196h
00012Ah
00012Ch
000198h
000150h
000152h
0001B6h
0001B8h
0001BAh
0001C2h
0001C4h
0001C6h
IFS0<3>
IFS0<7>
IFS0<8>
IFS1<11>
IFS1<12>
IFS4<1>
IFS0<11>
IFS0<12>
IFS4<2>
IFS1<14>
IFS1<15>
IFS5<1>
IFS5<2>
IFS5<3>
IFS5<7>
IFS5<8>
IFS5<9>
IEC0<3>
IEC0<7>
IEC0<8>
IEC1<11>
IEC1<12>
IEC4<1>
IEC0<11>
IEC0<12>
IEC4<2>
IEC1<14>
IEC1<15>
IEC5<1>
IEC5<2>
IEC5<3>
IEC5<7>
IEC5<8>
IEC5<9>
IPC0<14:12>
IPC1<14:12>
IPC2<2:0>
Timer2
7
Timer3
8
Timer4
27
28
65
11
12
66
30
31
81
82
83
87
88
89
IPC6<14:12>
IPC7<2:0>
Timer5
UART1 Error
UART1 Receiver
UART1 Transmitter
UART2 Error
UART2 Receiver
UART2 Transmitter
UART3 Error
UART3 Receiver
UART3 Transmitter
UART4 Error
UART4 Receiver
UART4 Transmitter
IPC16<6:4>
IPC2<14:12>
IPC3<2:0>
IPC16<10:8>
IPC7<10:8>
IPC7<14:12>
IPC20<6:4>
IPC20<10:8>
IPC20<14:12>
IPC21<14:12>
IPC22<2:0>
IPC22<6:4>
The IPCx registers are used to set the interrupt priority
level for each source of interrupt. Each user interrupt
source can be assigned to one of eight priority levels.
8.3
Interrupt Control and Status
Registers
The PIC24FJ128GA310 family of devices implements
a total of 43 registers for the interrupt controller:
The INTTREG register contains the associated
interrupt vector number and the new CPU interrupt
priority level, which are latched into the Vector
Number (VECNUM<6:0>) and the Interrupt Level
(ILR<3:0>) bit fields in the INTTREG register. The
new interrupt priority level is the priority of the
pending interrupt.
• INTCON1
• INTCON2
• IFS0 through IFS7
• IEC0 through IEC7
• IPC0 through IPC13, ICP15 and ICP16, ICP18
through ICP23, ICP25 and ICP29
The interrupt sources are assigned to the IFSx, IECx
and IPCx registers in the order of their vector numbers,
as shown in Table 8-2. For example, the INT0 (External
Interrupt 0) is shown as having a vector number and a
natural order priority of 0. Thus, the INT0IF status bit is
found in IFS0<0>, the INT0IE enable bit in IEC0<0>
and the INT0IP<2:0> priority bits in the first position of
IPC0 (IPC0<2:0>).
• INTTREG
Global interrupt control functions are controlled from
INTCON1 and INTCON2. INTCON1 contains the Inter-
rupt Nesting Disable (NSTDIS) bit, as well as the
control and status flags for the processor trap sources.
The INTCON2 register controls the external interrupt
request signal behavior and the use of the Alternate
Interrupt Vector Table (AIVT).
Although they are not specifically part of the interrupt
control hardware, two of the CPU Control registers con-
tain bits that control interrupt functionality. The ALU
STATUS Register (SR) contains the IPL<2:0> bits
(SR<7:5>). These indicate the current CPU interrupt
priority level. The user can change the current CPU
priority level by writing to the IPL bits.
The IFSx registers maintain all of the interrupt request
flags. Each source of interrupt has a status bit, which is
set by the respective peripherals or an external signal
and is cleared via software.
The IECx registers maintain all of the interrupt enable
bits. These control bits are used to individually enable
interrupts from the peripherals or external signals.
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The CORCON register contains the IPL3 bit, which
priority level are latched into INTTREG. This informa-
tion can be used to determine a specific interrupt
source if a generic ISR is used for multiple vectors
(such as when ISR remapping is used in bootloader
applications) or to check if another interrupt is pending
while in an ISR.
together with the IPL<2:0> bits, indicate the current
CPU priority level. IPL3 is a read-only bit so that trap
events cannot be masked by the user software.
The interrupt controller has the Interrupt Controller Test
register, INTTREG, which displays the status of the
interrupt controller. When an interrupt request occurs,
it’s associated vector number and the new interrupt
All interrupt registers are described in Register 8-1
through Register 8-44 in the succeeding pages.
REGISTER 8-1:
SR: ALU STATUS REGISTER (IN CPU)
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
R-0
DC(1)
bit 15
bit 8
R/W-0
IPL2(2,3)
bit 7
R/W-0
IPL1(2,3)
R/W-0
IPL0(2,3)
R-0
RA(1)
R/W-0
N(1)
R/W-0
OV(1)
R/W-0
Z(1)
R/W-0
C(1)
bit 0
Legend:
HSC = Hardware Settable/Clearable bit
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-9
bit 7-5
Unimplemented: Read as ‘0’
IPL<2:0>: CPU Interrupt Priority Level Status bits(2,3)
111= CPU interrupt priority level is 7 (15); user interrupts are disabled
110= CPU interrupt priority level is 6 (14)
101= CPU interrupt priority level is 5 (13)
100= CPU interrupt priority level is 4 (12)
011= CPU interrupt priority level is 3 (11)
010= CPU interrupt priority level is 2 (10)
001= CPU interrupt priority level is 1 (9)
000= CPU interrupt priority level is 0 (8)
Note 1: See Register 3-1 for the description of the remaining bits (bits 8, 4, 3, 2, 1 and 0) that are not dedicated to
interrupt control functions.
2: The IPL bits are concatenated with the IPL3 (CORCON<3>) bit to form the CPU interrupt priority level.
The value in parentheses indicates the interrupt priority level if IPL3 = 1.
3: The IPL Status bits are read-only when NSTDIS (INTCON1<15>) = 1.
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REGISTER 8-2:
CORCON: CPU CONTROL REGISTER
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
bit 15
bit 8
bit 0
U-0
—
U-0
—
U-0
—
U-0
—
R/C-0
IPL3(1)
r-1
r
U-0
—
U-0
—
bit 7
Legend:
r = Reserved bit
W = Writable bit
‘1’ = Bit is set
R = Readable bit
-n = Value at POR
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-4
bit 3
Unimplemented: Read as ‘0’
IPL3: CPU Interrupt Priority Level Status bit(1)
1= CPU interrupt priority level is greater than 7
0= CPU interrupt priority level is 7 or less
bit 2
Reserved: Read as ‘1’
bit 1-0
Unimplemented: Read as ‘0’
Note 1: The IPL3 bit is concatenated with the IPL<2:0> bits (SR<7:5>) to form the CPU interrupt priority level; see
Register 3-2 for bit description.
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REGISTER 8-3:
INTCON1: INTERRUPT CONTROL REGISTER 1
R/W-0
NSTDIS
bit 15
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
bit 8
bit 0
U-0
—
U-0
—
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
U-0
—
MATHERR
ADDRERR
STKERR
OSCFAIL
bit 7
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15
NSTDIS: Interrupt Nesting Disable bit
1= Interrupt nesting is disabled
0= Interrupt nesting is enabled
bit 14-5
bit 4
Unimplemented: Read as ‘0’
MATHERR: Arithmetic Error Trap Status bit
1= Overflow trap has occurred
0= Overflow trap has not occurred
bit 3
bit 2
bit 1
bit 0
ADDRERR: Address Error Trap Status bit
1= Address error trap has occurred
0= Address error trap has not occurred
STKERR: Stack Error Trap Status bit
1= Stack error trap has occurred
0= Stack error trap has not occurred
OSCFAIL: Oscillator Failure Trap Status bit
1= Oscillator failure trap has occurred
0= Oscillator failure trap has not occurred
Unimplemented: Read as ‘0’
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REGISTER 8-4:
INTCON2: INTERRUPT CONTROL REGISTER 2
R/W-0
R-0, HSC
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
ALTIVT
DISI
bit 15
bit 8
U-0
—
U-0
—
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
INT4EP
INT3EP
INT2EP
INT1EP
INT0EP
bit 7
bit 0
Legend:
HSC = Hardware Settable/Clearable bit
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15
bit 14
ALTIVT: Enable Alternate Interrupt Vector Table bit
1= Use Alternate Interrupt Vector Table
0= Use standard (default) Interrupt Vector Table
DISI: DISIInstruction Status bit
1= DISIinstruction is active
0= DISIinstruction is not active
bit 13-5
bit 4
Unimplemented: Read as ‘0’
INT4EP: External Interrupt 4 Edge Detect Polarity Select bit
1= Interrupt on negative edge
0= Interrupt on positive edge
bit 3
bit 2
bit 1
bit 0
INT3EP: External Interrupt 3 Edge Detect Polarity Select bit
1= Interrupt on negative edge
0= Interrupt on positive edge
INT2EP: External Interrupt 2 Edge Detect Polarity Select bit
1= Interrupt on negative edge
0= Interrupt on positive edge
INT1EP: External Interrupt 1 Edge Detect Polarity Select bit
1= Interrupt on negative edge
0= Interrupt on positive edge
INT0EP: External Interrupt 0 Edge Detect Polarity Select bit
1= Interrupt on negative edge
0= Interrupt on positive edge
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REGISTER 8-5:
IFS0: INTERRUPT FLAG STATUS REGISTER 0
U-0
—
R/W-0
R/W-0
AD1IF
R/W-0
R/W-0
R/W-0
SPI1IF
R/W-0
R/W-0
T3IF
DMA1IF
U1TXIF
U1RXIF
SPF1IF
bit 15
bit 8
R/W-0
T2IF
R/W-0
OC2IF
R/W-0
IC2IF
R/W-0
R/W-0
T1IF
R/W-0,
OC1IF
R/W-0
IC1IF
R/W-0
INT0IF
DMA0IF
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
-n = Value at POR
bit 15
bit 14
Unimplemented: Read as ‘0’
AD1IF: A/D Conversion Complete Interrupt Flag Status bit
1= Interrupt request has occurred
0= Interrupt request has not occurred
bit 13
bit 12
bit 11
bit 10
bit 9
DMA1IF: DMA Channel 1 Interrupt Flag Status bit
1= Interrupt request has occurred
0= Interrupt request has not occurred
U1TXIF: UART1 Transmitter Interrupt Flag Status bit
1= Interrupt request has occurred
0= Interrupt request has not occurred
U1RXIF: UART1 Receiver Interrupt Flag Status bit
1= Interrupt request has occurred
0= Interrupt request has not occurred
SPI1IF: SPI1 Event Interrupt Flag Status bit
1= Interrupt request has occurred
0= Interrupt request has not occurred
SPF1IF: SPI1 Fault Interrupt Flag Status bit
1= Interrupt request has occurred
0= Interrupt request has not occurred
bit 8
T3IF: Timer3 Interrupt Flag Status bit
1= Interrupt request has occurred
0= Interrupt request has not occurred
bit 7
T2IF: Timer2 Interrupt Flag Status bit
1= Interrupt request has occurred
0= Interrupt request has not occurred
bit 6
OC2IF: Output Compare Channel 2 Interrupt Flag Status bit
1= Interrupt request has occurred
0= Interrupt request has not occurred
bit 5
IC2IF: Input Capture Channel 2 Interrupt Flag Status bit
1= Interrupt request has occurred
0= Interrupt request has not occurred
bit 4
DMA0IF: DMA Channel 0 Interrupt Flag Status bit
1= Interrupt request has occurred
0= Interrupt request has not occurred
bit 3
T1IF: Timer1 Interrupt Flag Status bit
1= Interrupt request has occurred
0= Interrupt request has not occurred
2010-2011 Microchip Technology Inc.
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REGISTER 8-5:
IFS0: INTERRUPT FLAG STATUS REGISTER 0 (CONTINUED)
bit 2
bit 1
bit 0
OC1IF: Output Compare Channel 1 Interrupt Flag Status bit
1= Interrupt request has occurred
0= Interrupt request has not occurred
IC1IF: Input Capture Channel 1 Interrupt Flag Status bit
1= Interrupt request has occurred
0= Interrupt request has not occurred
INT0IF: External Interrupt 0 Flag Status bit
1= Interrupt request has occurred
0= Interrupt request has not occurred
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REGISTER 8-6:
IFS1: INTERRUPT FLAG STATUS REGISTER 1
R/W-0
U2TXIF
bit 15
R/W-0
R/W-0
INT2IF
R/W-0
T5IF
R/W-0
T4IF
R/W-0
OC4IF
R/W-0
OC3IF
R/W-0
U2RXIF
DMA2IF
bit 8
R/W-0
—
R/W-0
IC7IF
U-0
—
R/W-0
INT1IF
R/W-0
CNIF
R/W-0
CMIF
R/W-0
R/W-0
MI2C1IF
SI2C1IF
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
-n = Value at POR
bit 15
bit 14
bit 13
bit 12
bit 11
bit 10
bit 9
U2TXIF: UART2 Transmitter Interrupt Flag Status bit
1= Interrupt request has occurred
0= Interrupt request has not occurred
U2RXIF: UART2 Receiver Interrupt Flag Status bit
1= Interrupt request has occurred
0= Interrupt request has not occurred
INT2IF: External Interrupt 2 Flag Status bit
1= Interrupt request has occurred
0= Interrupt request has not occurred
T5IF: Timer5 Interrupt Flag Status bit
1= Interrupt request has occurred
0= Interrupt request has not occurred
T4IF: Timer4 Interrupt Flag Status bit
1= Interrupt request has occurred
0= Interrupt request has not occurred
OC4IF: Output Compare Channel 4 Interrupt Flag Status bit
1= Interrupt request has occurred
0= Interrupt request has not occurred
OC3IF: Output Compare Channel 3 Interrupt Flag Status bit
1= Interrupt request has occurred
0= Interrupt request has not occurred
bit 8
DMA2IF: DMA Channel 2 Interrupt Flag Status bit
1= Interrupt request has occurred
0= Interrupt request has not occurred
bit 7
bit 6
Unimplemented: Read as ‘0’
IC7IF: Input Capture Channel 7 Interrupt Flag Status bit
1= Interrupt request has occurred
0= Interrupt request has not occurred
bit 5
bit 4
Unimplemented: Read as ‘0’
INT1IF: External Interrupt 1 Flag Status bit
1= Interrupt request has occurred
0= Interrupt request has not occurred
bit 3
CNIF: Input Change Notification Interrupt Flag Status bit
1= Interrupt request has occurred
0= Interrupt request has not occurred
2010-2011 Microchip Technology Inc.
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REGISTER 8-6:
IFS1: INTERRUPT FLAG STATUS REGISTER 1 (CONTINUED)
bit 2
bit 1
bit 0
CMIF: Comparator Interrupt Flag Status bit
1= Interrupt request has occurred
0= Interrupt request has not occurred
MI2C1IF: Master I2C1 Event Interrupt Flag Status bit
1= Interrupt request has occurred
0= Interrupt request has not occurred
SI2C1IF: Slave I2C1 Event Interrupt Flag Status bit
1= Interrupt request has occurred
0= Interrupt request has not occurred
DS39996F-page 106
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REGISTER 8-7:
IFS2: INTERRUPT FLAG STATUS REGISTER 2
U-0
—
R/W-0
R/W-0
PMPIF
U-0
—
R/W-0
OC7IF
R/W-0
OC6IF
R/W-0
OC5IF
R/W-0
IC6IF
DMA4IF
bit 15
bit 8
R/W-0
IC5IF
R/W-0
IC4IF
R/W-0
IC3IF
R/W-0
U-0
—
U-0
—
R/W-0
SPI2IF
R/W-0
DMA3IF
SPF2IF
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
-n = Value at POR
bit 15
bit 14
Unimplemented: Read as ‘0’
DMA4IF: DMA Channel 4 Interrupt Flag Status bit
1= Interrupt request has occurred
0= Interrupt request has not occurred
bit 13
PMPIF: Parallel Master Port Interrupt Flag Status bit
1= Interrupt request has occurred
0= Interrupt request has not occurred
bit 12
bit 11
Unimplemented: Read as ‘0’
OC7IF: Output Compare Channel 7 Interrupt Flag Status bit
1= Interrupt request has occurred
0= Interrupt request has not occurred
bit 10
bit 9
bit 8
bit 7
bit 6
bit 5
bit 4
bit 3-2
OC6IF: Output Compare Channel 6 Interrupt Flag Status bit
1= Interrupt request has occurred
0= Interrupt request has not occurred
OC5IF: Output Compare Channel 5 Interrupt Flag Status bit
1= Interrupt request has occurred
0= Interrupt request has not occurred
IC6IF: Input Capture Channel 6 Interrupt Flag Status bit
1= Interrupt request has occurred
0= Interrupt request has not occurred
IC5IF: Input Capture Channel 5 Interrupt Flag Status bit
1= Interrupt request has occurred
0= Interrupt request has not occurred
IC4IF: Input Capture Channel 4 Interrupt Flag Status bit
1= Interrupt request has occurred
0= Interrupt request has not occurred
IC3IF: Input Capture Channel 3 Interrupt Flag Status bit
1= Interrupt request has occurred
0= Interrupt request has not occurred
DMA3IF: DMA Channel 3 Interrupt Flag Status bit
1= Interrupt request has occurred
0= Interrupt request has not occurred
Unimplemented: Read as ‘0’
2010-2011 Microchip Technology Inc.
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REGISTER 8-7:
IFS2: INTERRUPT FLAG STATUS REGISTER 2 (CONTINUED)
bit 1
SPI2IF: SPI2 Event Interrupt Flag Status bit
1= Interrupt request has occurred
0= Interrupt request has not occurred
bit 0
SPF2IF: SPI2 Fault Interrupt Flag Status bit
1= Interrupt request has occurred
0= Interrupt request has not occurred
REGISTER 8-8:
IFS3: INTERRUPT FLAG STATUS REGISTER 3
U-0
—
R/W-0
RTCIF
R/W-0
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
DMA5IF
bit 15
bit 8
bit 0
U-0
—
R/W-0
INT4IF
R/W-0
INT3IF
U-0
—
U-0
—
R/W-0
R/W-0
U-0
—
MI2C2IF
SI2C2IF
bit 7
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
-n = Value at POR
bit 15
bit 14
Unimplemented: Read as ‘0’
RTCIF: Real-Time Clock/Calendar Interrupt Flag Status bit
1= Interrupt request has occurred
0= Interrupt request has not occurred
bit 13
DMA5IF: DMA Channel 5 Interrupt Flag Status bit
1= Interrupt request has occurred
0= Interrupt request has not occurred
bit 12-7
bit 6
Unimplemented: Read as ‘0’
INT4IF: External Interrupt 4 Flag Status bit
1= Interrupt request has occurred
0= Interrupt request has not occurred
bit 5
INT3IF: External Interrupt 3 Flag Status bit
1= Interrupt request has occurred
0= Interrupt request has not occurred
bit 4-3
bit 2
Unimplemented: Read as ‘0’
MI2C2IF: Master I2C2 Event Interrupt Flag Status bit
1= Interrupt request has occurred
0= Interrupt request has not occurred
bit 1
bit 0
SI2C2IF: Slave I2C2 Event Interrupt Flag Status bit
1= Interrupt request has occurred
0= Interrupt request has not occurred
Unimplemented: Read as ‘0’
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REGISTER 8-9:
IFS4: INTERRUPT FLAG STATUS REGISTER 4
U-0
—
U-0
—
R/W-0
U-0
—
U-0
—
U-0
—
U-0
—
R/W-0
LVDIF
CTMUIF
bit 15
bit 8
U-0
—
U-0
—
U-0
—
U-0
—
R/W-0
CRCIF
R/W-0
R/W-0
U-0
—
U2ERIF
U1ERIF
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-14
bit 13
Unimplemented: Read as ‘0’
CTMUIF: CTMU Interrupt Flag Status bit
1= Interrupt request has occurred
0= Interrupt request has not occurred
bit 12-9
bit 8
Unimplemented: Read as ‘0’
LVDIF: Low-Voltage Detect Interrupt Flag Status bit
1= Interrupt request has occurred
0= Interrupt request has not occurred
bit 7-4
bit 3
Unimplemented: Read as ‘0’
CRCIF: CRC Generator Interrupt Flag Status bit
1= Interrupt request has occurred
0= Interrupt request has not occurred
bit 2
bit 1
bit 0
U2ERIF: UART2 Error Interrupt Flag Status bit
1= Interrupt request has occurred
0= Interrupt request has not occurred
U1ERIF: UART1 Error Interrupt Flag Status bit
1= Interrupt request has occurred
0= Interrupt request has not occurred
Unimplemented: Read as ‘0’
2010-2011 Microchip Technology Inc.
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REGISTER 8-10: IFS5: INTERRUPT FLAG STATUS REGISTER 5
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
R/W-0
R/W-0
U4TXIF
U4RXIF
bit 15
bit 8
R/W-0
U-0
—
U-0
—
U-0
—
R/W-0
R/W-0
R/W-0
U-0
—
U4ERIF
U3TXIF
U3RXIF
U3ERIF
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-10
bit 9
Unimplemented: Read as ‘0’
U4TXIF: UART4 Transmitter Interrupt Flag Status bit
1= Interrupt request has occurred
0= Interrupt request has not occurred
bit 8
bit 7
U4RXIF: UART4 Receiver Interrupt Flag Status bit
1= Interrupt request has occurred
0= Interrupt request has not occurred
U4ERIF: UART4 Error Interrupt Flag Status bit
1= Interrupt request has occurred
0= Interrupt request has not occurred
bit 6-4
bit 3
Unimplemented: Read as ‘0’
U3TXIF: UART3 Transmitter Interrupt Flag Status bit
1= Interrupt request has occurred
0= Interrupt request has not occurred
bit 2
bit 1
bit 0
U3RXIF: UART3 Receiver Interrupt Flag Status bit
1= Interrupt request has occurred
0= Interrupt request has not occurred
U3ERIF: UART3 Error Interrupt Flag Status bit
1= Interrupt request has occurred
0= Interrupt request has not occurred
Unimplemented: Read as ‘0’
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REGISTER 8-11: IFS6: INTERRUPT FLAG STATUS REGISTER 6
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
bit 15
bit 8
bit 0
U-0
—
U-0
—
U-0
—
R/W-0
LCDIF
U-0
—
U-0
—
U-0
—
U-0
—
bit 7
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-5
bit 4
Unimplemented: Read as ‘0’
LCDIF: LCD Controller Interrupt Flag Status bit
1= Interrupt request has occurred
0= Interrupt request has not occurred
bit 3-0
Unimplemented: Read as ‘0’
REGISTER 8-12: IFS7: INTERRUPT FLAG STATUS REGISTER 7
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
bit 15
bit 8
bit 0
U-0
—
U-0
—
R/W-0
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
JTAGIF
bit 7
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-6
bit 5
Unimplemented: Read as ‘0’
JTAGIF: JTAG Controller Interrupt Flag Status bit
1= Interrupt request has occurred
0= Interrupt request has not occurred
bit 4-0
Unimplemented: Read as ‘0’
2010-2011 Microchip Technology Inc.
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REGISTER 8-13: IEC0: INTERRUPT ENABLE CONTROL REGISTER 0
U-0
—
R/W-0
R/W-0
AD1IE
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
T3IE
DMA1IE
U1TXIE
U1RXIE
SPI1IE
SPF1IE
bit 15
bit 8
R/W-0
T2IE
R/W-0
OC2IE
R/W-0
IC2IE
R/W-0
R/W-0
T1IE
R/W-0
OC1IE
R/W-0
IC1IE
R/W-0
DMA0IE
INT0IE
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
-n = Value at POR
bit 15
bit 14
Unimplemented: Read as ‘0’
DMA1IE: DMA Channel 1 Interrupt Flag Enable bit
1= Interrupt request is enabled
0= Interrupt request is not enabled
bit 13
bit 12
bit 11
bit 10
bit 9
AD1IE: A/D Conversion Complete Interrupt Enable bit
1= Interrupt request is enabled
0= Interrupt request is not enabled
U1TXIE: UART1 Transmitter Interrupt Enable bit
1= Interrupt request is enabled
0= Interrupt request is not enabled
U1RXIE: UART1 Receiver Interrupt Enable bit
1= Interrupt request is enabled
0= Interrupt request is not enabled
SPI1IE: SPI1 Transfer Complete Interrupt Enable bit
1= Interrupt request is enabled
0= Interrupt request is not enabled
SPF1IE: SPI1 Fault Interrupt Enable bit
1= Interrupt request is enabled
0= Interrupt request is not enabled
bit 8
T3IE: Timer3 Interrupt Enable bit
1= Interrupt request is enabled
0= Interrupt request is not enabled
bit 7
T2IE: Timer2 Interrupt Enable bit
1= Interrupt request is enabled
0= Interrupt request is not enabled
bit 6
OC2IE: Output Compare Channel 2 Interrupt Enable bit
1= Interrupt request is enabled
0= Interrupt request is not enabled
bit 5
IC2IE: Input Capture Channel 2 Interrupt Enable bit
1= Interrupt request is enabled
0= Interrupt request is not enabled
bit 4
DMA0IE: DMA Channel 0 Interrupt Flag Enable bit
1= Interrupt request is enabled
0= Interrupt request is not enabled
bit 3
T1IE: Timer1 Interrupt Enable bit
1= Interrupt request is enabled
0= Interrupt request is not enabled
DS39996F-page 112
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REGISTER 8-13: IEC0: INTERRUPT ENABLE CONTROL REGISTER 0 (CONTINUED)
bit 2
bit 1
bit 0
OC1IE: Output Compare Channel 1 Interrupt Enable bit
1= Interrupt request is enabled
0= Interrupt request is not enabled
IC1IE: Input Capture Channel 1 Interrupt Enable bit
1= Interrupt request is enabled
0= Interrupt request is not enabled
INT0IE: External Interrupt 0 Enable bit
1= Interrupt request is enabled
0= Interrupt request is not enabled
2010-2011 Microchip Technology Inc.
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REGISTER 8-14: IEC1: INTERRUPT ENABLE CONTROL REGISTER 1
R/W-0
R/W-0
R/W-0
INT2IE(1)
R/W-0
T5IE
R/W-0
T4IE
R/W-0
OC4IE
R/W-0
OC3IE
R/W-0
U2TXIE
U2RXIE
DMA2IE
bit 15
bit 8
U-0
—
R/W-0
IC7IE
U-0
—
R/W-0
INT1IE(1)
R/W-0
CNIE
R/W-0
CMIE
R/W-0
R/W-0
MI2C1IE
SI2C1IE
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
-n = Value at POR
bit 15
bit 14
bit 13
bit 12
bit 11
bit 10
bit 9
U2TXIE: UART2 Transmitter Interrupt Enable bit
1= Interrupt request is enabled
0= Interrupt request is not enabled
U2RXIE: UART2 Receiver Interrupt Enable bit
1= Interrupt request is enabled
0= Interrupt request is not enabled
INT2IE: External Interrupt 2 Enable bit(1)
1= Interrupt request is enabled
0= Interrupt request is not enabled
T5IE: Timer5 Interrupt Enable bit
1= Interrupt request is enabled
0= Interrupt request is not enabled
T4IE: Timer4 Interrupt Enable bit
1= Interrupt request is enabled
0= Interrupt request is not enabled
OC4IE: Output Compare Channel 4 Interrupt Enable bit
1= Interrupt request is enabled
0= Interrupt request is not enabled
OC3IE: Output Compare Channel 3 Interrupt Enable bit
1= Interrupt request is enabled
0= Interrupt request is not enabled
bit 8
DMA2IE: DMA Channel 2 Interrupt Flag Enable bit
1= Interrupt request is enabled
0= Interrupt request is not enabled
bit 7
bit 6
Unimplemented: Read as ‘0’
IC7IE: Input Capture Channel 7 Interrupt Enable bit
1= Interrupt request is enabled
0= Interrupt request is not enabled
bit 5
bit 4
Unimplemented: Read as ‘0’
INT1IE: External Interrupt 1 Enable bit(1)
1= Interrupt request is enabled
0= Interrupt request is not enabled
Note 1: If an external interrupt is enabled, the interrupt input must also be configured to an available RPx or RPIx
pin. See Section 11.4 “Peripheral Pin Select (PPS)” for more information.
DS39996F-page 114
2010-2011 Microchip Technology Inc.
PIC24FJ128GA310 FAMILY
REGISTER 8-14: IEC1: INTERRUPT ENABLE CONTROL REGISTER 1 (CONTINUED)
bit 3
bit 2
bit 1
bit 0
CNIE: Input Change Notification Interrupt Enable bit
1= Interrupt request is enabled
0= Interrupt request is not enabled
CMIE: Comparator Interrupt Enable bit
1= Interrupt request is enabled
0= Interrupt request is not enabled
MI2C1IE: Master I2C1 Event Interrupt Enable bit
1= Interrupt request is enabled
0= Interrupt request is not enabled
SI2C1IE: Slave I2C1 Event Interrupt Enable bit
1= Interrupt request is enabled
0= Interrupt request is not enabled
Note 1: If an external interrupt is enabled, the interrupt input must also be configured to an available RPx or RPIx
pin. See Section 11.4 “Peripheral Pin Select (PPS)” for more information.
2010-2011 Microchip Technology Inc.
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REGISTER 8-15: IEC2: INTERRUPT ENABLE CONTROL REGISTER 2
U-0
—
R/W-0
R/W-0
U-0
—
R/W-0
OC7IE
R/W-0
OC6IE
R/W-0
OC5IE
R/W-0
IC6IE
DMA4IE
PMPIE
bit 15
bit 8
R/W-0
IC5IE
R/W-0
IC4IE
R/W-0
IC3IE
R/W-0
U-0
—
U-0
—
R/W-0
R/W-0
DMA3IE
SPI2IE
SPF2IE
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
-n = Value at POR
bit 15
bit 14
Unimplemented: Read as ‘0’
DMA4IE: DMA Channel 4 Interrupt Flag Enable bit
1= Interrupt request is enabled
0= Interrupt request is not enabled
bit 13
PMPIE: Parallel Master Port Interrupt Enable bit
1= Interrupt request is enabled
0= Interrupt request is not enabled
bit 12
bit 11
Unimplemented: Read as ‘0’
OC7IE: Output Compare Channel 7 Interrupt Enable bit
1= Interrupt request is enabled
0= Interrupt request is not enabled
bit 10
bit 9
bit 8
bit 7
bit 6
bit 5
bit 4
bit 3-2
OC6IE: Output Compare Channel 6 Interrupt Enable bit
1= Interrupt request is enabled
0= Interrupt request is not enabled
OC5IE: Output Compare Channel 5 Interrupt Enable bit
1= Interrupt request is enabled
0= Interrupt request is not enabled
IC6IE: Input Capture Channel 6 Interrupt Enable bit
1= Interrupt request is enabled
0= Interrupt request is not enabled
IC5IE: Input Capture Channel 5 Interrupt Enable bit
1= Interrupt request is enabled
0= Interrupt request is not enabled
IC4IE: Input Capture Channel 4 Interrupt Enable bit
1= Interrupt request is enabled
0= Interrupt request is not enabled
IC3IE: Input Capture Channel 3 Interrupt Enable bit
1= Interrupt request is enabled
0= Interrupt request is not enabled
DMA3IF: DMA Channel 3 Interrupt Flag Enable bit
1= Interrupt request is enabled
0= Interrupt request is not enabled
Unimplemented: Read as ‘0’
DS39996F-page 116
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REGISTER 8-15: IEC2: INTERRUPT ENABLE CONTROL REGISTER 2
bit 1
SPI2IE: SPI2 Event Interrupt Enable bit
1= Interrupt request is enabled
0= Interrupt request is not enabled
bit 0
SPF2IE: SPI2 Fault Interrupt Enable bit
1= Interrupt request is enabled
0= Interrupt request is not enabled
REGISTER 8-16: IEC3: INTERRUPT ENABLE CONTROL REGISTER 3
U-0
—
R/W-0
RTCIE
R/W-0
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
DMA5IE
bit 15
bit 8
bit 0
U-0
—
R/W-0
INT4IE(1)
R/W-0
INT3IE(1)
U-0
—
U-0
—
R/W-0
R/W-0
U-0
—
MI2C2IE
SI2C2IE
bit 7
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
-n = Value at POR
bit 15
bit 14
Unimplemented: Read as ‘0’
RTCIE: Real-Time Clock/Calendar Interrupt Enable bit
1= Interrupt request is enabled
0= Interrupt request is not enabled
bit 13
DMA5IE: DMA Channel 5 Interrupt Flag Enable bit
1= Interrupt request is enabled
0= Interrupt request is not enabled
bit 12-7
bit 6
Unimplemented: Read as ‘0’
INT4IE: External Interrupt 4 Enable bit(1)
1= Interrupt request is enabled
0= Interrupt request is not enabled
bit 5
INT3IE: External Interrupt 3 Enable bit(1)
1= Interrupt request is enabled
0= Interrupt request is not enabled
bit 4-3
bit 2
Unimplemented: Read as ‘0’
MI2C2IE: Master I2C2 Event Interrupt Enable bit
1= Interrupt request is enabled
0= Interrupt request is not enabled
bit 1
SI2C2IE: Slave I2C2 Event Interrupt Enable bit
1= Interrupt request is enabled
0= Interrupt request is not enabled
bit 0
Unimplemented: Read as ‘0’
Note 1: If an external interrupt is enabled, the interrupt input must also be configured to an available RPx or RPIx
pin. See Section 11.4 “Peripheral Pin Select (PPS)” for more information.
2010-2011 Microchip Technology Inc.
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REGISTER 8-17: IEC4: INTERRUPT ENABLE CONTROL REGISTER 4
U-0
—
U-0
—
R/W-0
U-0
—
U-0
—
U-0
—
U-0
—
R/W-0
LVDIE
CTMUIE
bit 15
bit 8
U-0
—
U-0
—
U-0
—
U-0
—
R/W-0
R/W-0
R/W-0
U-0
—
CRCIE
U2ERIE
U1ERIE
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-14
bit 13
Unimplemented: Read as ‘0’
CTMUIE: CTMU Interrupt Enable bit
1= Interrupt request is enabled
0= Interrupt request is not enabled
bit 12-9
bit 8
Unimplemented: Read as ‘0’
LVDIE: Low-Voltage Detect Interrupt Enable bit
1= Interrupt request is enabled
0= Interrupt request is not enabled
bit 7-4
bit 3
Unimplemented: Read as ‘0’
CRCIE: CRC Generator Interrupt Enable bit
1= Interrupt request is enabled
0= Interrupt request is not enabled
bit 2
U2ERIE: UART2 Error Interrupt Enable bit
1= Interrupt request is enabled
0= Interrupt request is not enabled
bit 1
bit 0
U1ERIE: UART1 Error Interrupt Enable bit
1= Interrupt request is enabled
0= Interrupt request is not enabled
Unimplemented: Read as ‘0’
DS39996F-page 118
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REGISTER 8-18: IEC5: INTERRUPT ENABLE CONTROL REGISTER 5
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
R/W-0
R/W-0
U4TXIE
U4RXIE
bit 15
bit 8
R/W-0
U-0
—
U-0
—
U-0
—
R/W-0
R/W-0
R/W-0
U-0
—
U4ERIE
U3TXIE
U3RXIE
U3ERIE
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-10
bit 9
Unimplemented: Read as ‘0’
U4TXIE: UART4 Transmitter Interrupt Enable bit
1= Interrupt request is enabled
0= Interrupt request is not enabled
bit 8
bit 7
U4RXIE: UART4 Receiver Interrupt Enable bit
1= Interrupt request is enabled
0= Interrupt request is not enabled
U4ERIE: UART4 Error Interrupt Enable bit
1= Interrupt request is enabled
0= Interrupt request is not enabled
bit 6-4
bit 3
Unimplemented: Read as ‘0’
U3TXIE: UART3 Transmitter Interrupt Enable bit
1= Interrupt request is enabled
0= Interrupt request is not enabled
bit 2
bit 1
bit 0
U3RXIE: UART3 Receiver Interrupt Enable bit
1= Interrupt request is enabled
0= Interrupt request is not enabled
U3ERIE: UART3 Error Interrupt Enable bit
1= Interrupt request is enabled
0= Interrupt request is not enabled
Unimplemented: Read as ‘0’
2010-2011 Microchip Technology Inc.
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REGISTER 8-19: IEC6: INTERRUPT ENABLE CONTROL REGISTER 6
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
bit 15
bit 8
bit 0
U-0
—
U-0
—
U-0
—
R/W-0
LCDIE
U-0
—
U-0
—
U-0
—
U-0
—
bit 7
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-5
bit 4
Unimplemented: Read as ‘0’
LCDIE: LCD Controller Interrupt Enable bit
1= Interrupt request is enabled
0= Interrupt request is not enabled
bit 3-0
Unimplemented: Read as ‘0’
REGISTER 8-20: IEC7: INTERRUPT ENABLE CONTROL REGISTER 7
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
bit 15
bit 8
bit 0
U-0
—
U-0
—
R/W-0
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
JTAGIE
bit 7
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-6
bit 5
Unimplemented: Read as ‘0’
JTAGIE: JATG Interrupt Enable bit
1= Interrupt request is enabled
0= Interrupt request is not enabled
bit 4-0
Unimplemented: Read as ‘0’
DS39996F-page 120
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REGISTER 8-21: IPC0: INTERRUPT PRIORITY CONTROL REGISTER 0
U-0
—
R/W-1
T1IP2
R/W-0
T1IP1
R/W-0
T1IP0
U-0
—
R/W-1
R/W-0
R/W-0
OC1IP2
OC1IP1
OC1IP0
bit 15
bit 8
U-0
—
R/W-1
IC1IP2
R/W-0
IC1IP1
R/W-0
IC1IP0
U-0
—
R/W-1
R/W-0
R/W-0
INT0IP2
INT0IP1
INT0IP0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
-n = Value at POR
bit 15
Unimplemented: Read as ‘0’
T1IP<2:0>: Timer1 Interrupt Priority bits
bit 14-12
111= Interrupt is Priority 7 (highest priority interrupt)
•
•
•
001= Interrupt is Priority 1
000= Interrupt source is disabled
bit 11
Unimplemented: Read as ‘0’
bit 10-8
OC1IP<2:0>: Output Compare Channel 1 Interrupt Priority bits
111= Interrupt is Priority 7 (highest priority interrupt)
•
•
•
001= Interrupt is Priority 1
000= Interrupt source is disabled
bit 7
Unimplemented: Read as ‘0’
bit 6-4
IC1IP<2:0>: Input Capture Channel 1 Interrupt Priority bits
111= Interrupt is Priority 7 (highest priority interrupt)
•
•
•
001= Interrupt is Priority 1
000= Interrupt source is disabled
bit 3
Unimplemented: Read as ‘0’
bit 2-0
INT0IP<2:0>: External Interrupt 0 Priority bits
111= Interrupt is Priority 7 (highest priority interrupt)
•
•
•
001= Interrupt is Priority 1
000= Interrupt source is disabled
2010-2011 Microchip Technology Inc.
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REGISTER 8-22: IPC1: INTERRUPT PRIORITY CONTROL REGISTER 1
U-0
—
R/W-1
T2IP2
R/W-0
T2IP1
R/W-0
T2IP0
U-0
—
R/W-1
R/W-0
R/W-0
OC2IP2
OC2IP1
OC2IP0
bit 15
bit 8
U-0
—
R/W-1
IC2IP2
R/W-0
IC2IP1
R/W-0
IC2IP0
U-0
—
R/W-1
R/W-0
R/W-0
DMA0IP2
DMA0IP1
DMA0IP0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
-n = Value at POR
bit 15
Unimplemented: Read as ‘0’
T2IP<2:0>: Timer2 Interrupt Priority bits
bit 14-12
111= Interrupt is Priority 7 (highest priority interrupt)
•
•
•
001= Interrupt is Priority 1
000= Interrupt source is disabled
bit 11
Unimplemented: Read as ‘0’
bit 10-8
OC2IP<2:0>: Output Compare Channel 2 Interrupt Priority bits
111= Interrupt is Priority 7 (highest priority interrupt)
•
•
•
001= Interrupt is Priority 1
000= Interrupt source is disabled
bit 7
Unimplemented: Read as ‘0’
bit 6-4
IC2IP<2:0>: Input Capture Channel 2 Interrupt Priority bits
111= Interrupt is Priority 7 (highest priority interrupt)
•
•
•
001= Interrupt is Priority 1
000= Interrupt source is disabled
bit 3
Unimplemented: Read as ‘0’
bit 2-0
DMA0IP<2:0>: DMA Channel 0 Interrupt Priority bits
111= Interrupt is Priority 7 (highest priority interrupt)
•
•
•
001= Interrupt is Priority 1
000= Interrupt source is disabled
DS39996F-page 122
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REGISTER 8-23: IPC2: INTERRUPT PRIORITY CONTROL REGISTER 2
U-0
—
R/W-1
R/W-0
R/W-0
U-0
—
R/W-1
R/W-0
R/W-0
U1RXIP2
U1RXIP1
U1RXIP0
SPI1IP2
SPI1IP1
SPI1IP0
bit 15
bit 8
U-0
—
R/W-1
R/W-0
R/W-0
U-0
—
R/W-1
T3IP2
R/W-0
T3IP1
R/W-0
T3IP0
SPF1IP2
SPF1IP1
SPF1IP0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
-n = Value at POR
bit 15
Unimplemented: Read as ‘0’
bit 14-12
U1RXIP<2:0>: UART1 Receiver Interrupt Priority bits
111= Interrupt is Priority 7 (highest priority interrupt)
•
•
•
001= Interrupt is Priority 1
000= Interrupt source is disabled
bit 11
Unimplemented: Read as ‘0’
bit 10-8
SPI1IP<2:0>: SPI1 Event Interrupt Priority bits
111= Interrupt is Priority 7 (highest priority interrupt)
•
•
•
001= Interrupt is Priority 1
000= Interrupt source is disabled
bit 7
Unimplemented: Read as ‘0’
bit 6-4
SPF1IP<2:0>: SPI1 Fault Interrupt Priority bits
111= Interrupt is Priority 7 (highest priority interrupt)
•
•
•
001= Interrupt is Priority 1
000= Interrupt source is disabled
bit 3
Unimplemented: Read as ‘0’
bit 2-0
T3IP<2:0>: Timer3 Interrupt Priority bits
111= Interrupt is Priority 7 (highest priority interrupt)
•
•
•
001= Interrupt is Priority 1
000= Interrupt source is disabled
2010-2011 Microchip Technology Inc.
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REGISTER 8-24: IPC3: INTERRUPT PRIORITY CONTROL REGISTER 3
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
R/W-1
R/W-0
R/W-0
DMA1IP2
DMA1IP1
DMA1IP0
bit 15
bit 8
U-0
—
R/W-1
R/W-0
R/W-0
U-0
—
R/W-1
R/W-0
R/W-0
AD1IP2
AD1IP1
AD1IP0
U1TXIP2
U1TXIP1
U1TXIP0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
-n = Value at POR
bit 15-11
bit 10-8
Unimplemented: Read as ‘0’
DMA1IP<2:0>: DMA Channel 1 Interrupt Priority bits
111= Interrupt is Priority 7 (highest priority interrupt)
•
•
•
001= Interrupt is Priority 1
000= Interrupt source is disabled
bit 7
Unimplemented: Read as ‘0’
bit 6-4
AD1IP<2:0>: A/D Conversion Complete Interrupt Priority bits
111= Interrupt is Priority 7 (highest priority interrupt)
•
•
•
001= Interrupt is Priority 1
000= Interrupt source is disabled
bit 3
Unimplemented: Read as ‘0’
bit 2-0
U1TXIP<2:0>: UART1 Transmitter Interrupt Priority bits
111= Interrupt is Priority 7 (highest priority interrupt)
•
•
•
001= Interrupt is Priority 1
000= Interrupt source is disabled
DS39996F-page 124
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REGISTER 8-25: IPC4: INTERRUPT PRIORITY CONTROL REGISTER 4
U-0
—
R/W-1
CNIP2
R/W-0
CNIP1
R/W-0
CNIP0
U-0
—
R/W-1
CMIP2
R/W-0
CMIP1
R/W-0
CMIP0
bit 15
bit 8
U-0
—
R/W-1
R/W-0
R/W-0
U-0
—
R/W-1
R/W-0
R/W-0
MI2C1IP2
MI2C1IP1
MI2C1IP0
SI2C1IP2
SI2C1IP1
SI2C1IP0
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15
Unimplemented: Read as ‘0’
bit 14-12
CNIP<2:0>: Input Change Notification Interrupt Priority bits
111= Interrupt is Priority 7 (highest priority interrupt)
•
•
•
001= Interrupt is Priority 1
000= Interrupt source is disabled
bit 11
Unimplemented: Read as ‘0’
bit 10-8
CMIP<2:0>: Comparator Interrupt Priority bits
111= Interrupt is Priority 7 (highest priority interrupt)
•
•
•
001= Interrupt is Priority 1
000= Interrupt source is disabled
bit 7
Unimplemented: Read as ‘0’
bit 6-4
MI2C1IP<2:0>: Master I2C1 Event Interrupt Priority bits
111= Interrupt is Priority 7 (highest priority interrupt)
•
•
•
001= Interrupt is Priority 1
000= Interrupt source is disabled
bit 3
Unimplemented: Read as ‘0’
bit 2-0
SI2C1IP<2:0>: Slave I2C1 Event Interrupt Priority bits
111= Interrupt is Priority 7 (highest priority interrupt)
•
•
•
001= Interrupt is Priority 1
000= Interrupt source is disabled
2010-2011 Microchip Technology Inc.
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REGISTER 8-26: IPC5: INTERRUPT PRIORITY CONTROL REGISTER 5
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
R/W-1
IC7IP2
R/W-0
IC7IP1
R/W-0
IC7IP0
bit 15
bit 8
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
R/W-1
R/W-0
R/W-0
INT1IP2
INT1IP1
INT1IP0
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-11
bit 10-8
Unimplemented: Read as ‘0’
IC7IP<2:0>: Input Capture Channel 7 Interrupt Priority bits
111= Interrupt is Priority 7 (highest priority interrupt)
•
•
•
001= Interrupt is Priority 1
000= Interrupt source is disabled
bit 7-3
bit 2-0
Unimplemented: Read as ‘0’
INT1IP<2:0>: External Interrupt 1 Priority bits
111= Interrupt is Priority 7 (highest priority interrupt)
•
•
•
001= Interrupt is Priority 1
000= Interrupt source is disabled
DS39996F-page 126
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REGISTER 8-27: IPC6: INTERRUPT PRIORITY CONTROL REGISTER 6
U-0
—
R/W-1
T4IP2
R/W-0
T4IP1
R/W-0
T4IP0
U-0
—
R/W-1
R/W-0
R/W-0
OC4IP2
OC4IP1
OC4IP0
bit 15
bit 8
U-0
—
R/W-1
R/W-0
R/W-0
U-0
—
R/W-1
R/W-0
R/W-0
OC3IP2
OC3IP1
OC3IP0
DMA2IP2
DMA2IP1
DMA2IP0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
-n = Value at POR
bit 15
Unimplemented: Read as ‘0’
T4IP<2:0>: Timer4 Interrupt Priority bits
bit 14-12
111= Interrupt is Priority 7 (highest priority interrupt)
•
•
•
001= Interrupt is Priority 1
000= Interrupt source is disabled
bit 11
Unimplemented: Read as ‘0’
bit 10-8
OC4IP<2:0>: Output Compare Channel 4 Interrupt Priority bits
111= Interrupt is Priority 7 (highest priority interrupt)
•
•
•
001= Interrupt is Priority 1
000= Interrupt source is disabled
bit 7
Unimplemented: Read as ‘0’
bit 6-4
OC3IP<2:0>: Output Compare Channel 3 Interrupt Priority bits
111= Interrupt is Priority 7 (highest priority interrupt)
•
•
•
001= Interrupt is Priority 1
000= Interrupt source is disabled
bit 3
Unimplemented: Read as ‘0’
bit 2-0
DMA2IP<2:0>: DMA Channel 2 Interrupt Priority bits
111= Interrupt is Priority 7 (highest priority interrupt)
•
•
•
001= Interrupt is Priority 1
000= Interrupt source is disabled
2010-2011 Microchip Technology Inc.
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REGISTER 8-28: IPC7: INTERRUPT PRIORITY CONTROL REGISTER 7
U-0
—
R/W-1
R/W-0
R/W-0
U-0
—
R/W-1
R/W-0
R/W-0
U2TXIP2
U2TXIP1
U2TXIP0
U2RXIP2
U2RXIP1
U2RXIP0
bit 15
bit 8
U-0
—
R/W-1
R/W-0
R/W-0
U-0
—
R/W-1
T5IP2
R/W-0
T5IP1
R/W-0
T5IP0
INT2IP2
INT2IP1
INT2IP0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
-n = Value at POR
bit 15
Unimplemented: Read as ‘0’
bit 14-12
U2TXIP<2:0>: UART2 Transmitter Interrupt Priority bits
111= Interrupt is Priority 7 (highest priority interrupt)
•
•
•
001= Interrupt is Priority 1
000= Interrupt source is disabled
bit 11
Unimplemented: Read as ‘0’
bit 10-8
U2RXIP<2:0>: UART2 Receiver Interrupt Priority bits
111= Interrupt is Priority 7 (highest priority interrupt)
•
•
•
001= Interrupt is Priority 1
000= Interrupt source is disabled
bit 7
Unimplemented: Read as ‘0’
bit 6-4
INT2IP<2:0>: External Interrupt 2 Priority bits
111= Interrupt is Priority 7 (highest priority interrupt)
•
•
•
001= Interrupt is Priority 1
000= Interrupt source is disabled
bit 3
Unimplemented: Read as ‘0’
bit 2-0
T5IP<2:0>: Timer5 Interrupt Priority bits
111= Interrupt is Priority 7 (highest priority interrupt)
•
•
•
001= Interrupt is Priority 1
000= Interrupt source is disabled
DS39996F-page 128
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REGISTER 8-29: IPC8: INTERRUPT PRIORITY CONTROL REGISTER 8
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
bit 15
bit 8
U-0
—
R/W-1
R/W-0
R/W-0
U-0
—
R/W-1
R/W-0
R/W-0
SPI2IP2
SPI2IP1
SPI2IP0
SPF2IP2
SPF2IP1
SPF2IP0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
-n = Value at POR
bit 15-7
bit 6-4
Unimplemented: Read as ‘0’
SPI2IP<2:0>: SPI2 Event Interrupt Priority bits
111= Interrupt is Priority 7 (highest priority interrupt)
•
•
•
001= Interrupt is Priority 1
000= Interrupt source is disabled
bit 3
Unimplemented: Read as ‘0’
bit 2-0
SPF2IP<2:0>: SPI2 Fault Interrupt Priority bits
111= Interrupt is Priority 7 (highest priority interrupt)
•
•
•
001= Interrupt is Priority 1
000= Interrupt source is disabled
2010-2011 Microchip Technology Inc.
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REGISTER 8-30: IPC9: INTERRUPT PRIORITY CONTROL REGISTER 9
U-0
—
R/W-1
IC5IP2
R/W-0
IC5IP1
R/W-0
IC5IP0
U-0
—
R/W-1
IC4IP2
R/W-0
IC4IP1
R/W-0
IC4IP0
bit 15
bit 8
U-0
—
R/W-1
IC3IP2
R/W-0
IC3IP1
R/W-0
IC3IP0
U-0
—
R/W-1
R/W-0
R/W-0
DMA3IP2
DMA3IP1
DMA3IP0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
-n = Value at POR
bit 15
Unimplemented: Read as ‘0’
bit 14-12
IC5IP<2:0>: Input Capture Channel 5 Interrupt Priority bits
111= Interrupt is Priority 7 (highest priority interrupt)
•
•
•
001= Interrupt is Priority 1
000= Interrupt source is disabled
bit 11
Unimplemented: Read as ‘0’
bit 10-8
IC4IP<2:0>: Input Capture Channel 4 Interrupt Priority bits
111= Interrupt is Priority 7 (highest priority interrupt)
•
•
•
001= Interrupt is Priority 1
000= Interrupt source is disabled
bit 7
Unimplemented: Read as ‘0’
bit 6-4
IC3IP<2:0>: Input Capture Channel 3 Interrupt Priority bits
111= Interrupt is Priority 7 (highest priority interrupt)
•
•
•
001= Interrupt is Priority 1
000= Interrupt source is disabled
bit 3
Unimplemented: Read as ‘0’
bit 2-0
DMA3IP<2:0>: DMA Channel 3 Interrupt Priority bits
111= Interrupt is Priority 7 (highest priority interrupt)
•
•
•
001= Interrupt is Priority 1
000= Interrupt source is disabled
DS39996F-page 130
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REGISTER 8-31: IPC10: INTERRUPT PRIORITY CONTROL REGISTER 10
U-0
—
R/W-1
R/W-0
R/W-0
U-0
—
R/W-1
R/W-0
R/W-0
OC7IP2
OC7IP1
OC7IP0
OC6IP2
OC6IP1
OC6IP0
bit 15
bit 8
U-0
—
R/W-1
R/W-0
R/W-0
U-0
—
R/W-1
IC6IP2
R/W-0
IC6IP1
R/W-0
IC6IP0
OC5IP2
OC5IP1
OC5IP0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
-n = Value at POR
bit 15
Unimplemented: Read as ‘0’
bit 14-12
OC7IP<2:0>: Output Compare Channel 7 Interrupt Priority bits
111= Interrupt is Priority 7 (highest priority interrupt)
•
•
•
001= Interrupt is Priority 1
000= Interrupt source is disabled
bit 11
Unimplemented: Read as ‘0’
bit 10-8
OC6IP<2:0>: Output Compare Channel 6 Interrupt Priority bits
111= Interrupt is Priority 7 (highest priority interrupt)
•
•
•
001= Interrupt is Priority 1
000= Interrupt source is disabled
bit 7
Unimplemented: Read as ‘0’
bit 6-4
OC5IP<2:0>: Output Compare Channel 5 Interrupt Priority bits
111= Interrupt is Priority 7 (highest priority interrupt)
•
•
•
001= Interrupt is Priority 1
000= Interrupt source is disabled
bit 3
Unimplemented: Read as ‘0’
bit 2-0
IC6IP<2:0>: Input Capture Channel 6 Interrupt Priority bits
111= Interrupt is Priority 7 (highest priority interrupt)
•
•
•
001= Interrupt is Priority 1
000= Interrupt source is disabled
2010-2011 Microchip Technology Inc.
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REGISTER 8-32: IPC11: INTERRUPT PRIORITY CONTROL REGISTER 11
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
R/W-1
R/W-0
R/W-0
DMA4IP2
DMA4IP1
DMA4IP0
bit 15
bit 8
U-0
—
R/W-1
R/W-0
R/W-0
U-0
—
U-0
—
U-0
—
U-0
—
PMPIP2
PMPIP1
PMPIP0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
-n = Value at POR
bit 15-11
bit 10-8
Unimplemented: Read as ‘0’
DMA4IP<2:0>: DMA Channel 4 Interrupt Priority bits
111= Interrupt is Priority 7 (highest priority interrupt)
•
•
•
001= Interrupt is Priority 1
000= Interrupt source is disabled
bit 7
Unimplemented: Read as ‘0’
bit 6-4
PMPIP<2:0>: Parallel Master Port Interrupt Priority bits
111= Interrupt is Priority 7 (highest priority interrupt)
•
•
•
001= Interrupt is Priority 1
000= Interrupt source is disabled
bit 3-0
Unimplemented: Read as ‘0’
DS39996F-page 132
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REGISTER 8-33: IPC12: INTERRUPT PRIORITY CONTROL REGISTER 12
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
R/W-1
R/W-0
R/W-0
MI2C2IP2
MI2C2IP1
MI2C2IP0
bit 15
bit 8
U-0
—
R/W-1
R/W-0
R/W-0
U-0
—
U-0
—
U-0
—
U-0
—
SI2C2IP2
SI2C2IP1
SI2C2IP0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
-n = Value at POR
bit 15-11
bit 10-8
Unimplemented: Read as ‘0’
MI2C2IP<2:0>: Master I2C2 Event Interrupt Priority bits
111= Interrupt is Priority 7 (highest priority interrupt)
•
•
•
001= Interrupt is Priority 1
000= Interrupt source is disabled
bit 7
Unimplemented: Read as ‘0’
bit 6-4
SI2C2IP<2:0>: Slave I2C2 Event Interrupt Priority bits
111= Interrupt is Priority 7 (highest priority interrupt)
•
•
•
001= Interrupt is Priority 1
000= Interrupt source is disabled
bit 3-0
Unimplemented: Read as ‘0’
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REGISTER 8-34: IPC13: INTERRUPT PRIORITY CONTROL REGISTER 13
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
R/W-1
R/W-0
R/W-0
INT4IP2
INT4IP1
INT4IP0
bit 15
bit 8
U-0
—
R/W-1
R/W-0
R/W-0
U-0
—
U-0
—
U-0
—
U-0
—
INT3IP2
INT3IP1
INT3IP0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
-n = Value at POR
bit 15-11
bit 10-8
Unimplemented: Read as ‘0’
INT4IP<2:0>: External Interrupt 4 Priority bits
111= Interrupt is Priority 7 (highest priority interrupt)
•
•
•
001= Interrupt is Priority 1
000= Interrupt source is disabled
bit 7
Unimplemented: Read as ‘0’
bit 6-4
INT3IP<2:0>: External Interrupt 3 Priority bits
111= Interrupt is Priority 7 (highest priority interrupt)
•
•
•
001= Interrupt is Priority 1
000= Interrupt source is disabled
bit 3-0
Unimplemented: Read as ‘0’
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REGISTER 8-35: IPC15: INTERRUPT PRIORITY CONTROL REGISTER 15
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
R/W-1
R/W-0
R/W-0
RTCIP2
RTCIP1
RTCIP0
bit 15
bit 8
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
R/W-1
R/W-0
R/W-0
DMA5IP2
DMA5IP1
DMA5IP0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
-n = Value at POR
bit 15-11
bit 10-8
Unimplemented: Read as ‘0’
RTCIP<2:0>: Real-Time Clock and Calendar Interrupt Priority bits
111= Interrupt is Priority 7 (highest priority interrupt)
•
•
•
001= Interrupt is Priority 1
000= Interrupt source is disabled
bit 7
Unimplemented: Read as ‘0’
bit 6-4
DMA5IP<2:0>: DMA Channel 5 Interrupt Priority bits
111= Interrupt is Priority 7 (highest priority interrupt)
•
•
•
001= Interrupt is Priority 1
000= Interrupt source is disabled
bit 3-0
Unimplemented: Read as ‘0’
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REGISTER 8-36: IPC16: INTERRUPT PRIORITY CONTROL REGISTER 16
U-0
—
R/W-1
R/W-0
R/W-0
U-0
—
R/W-1
R/W-0
R/W-0
CRCIP2
CRCIP1
CRCIP0
U2ERIP2
U2ERIP1
U2ERIP0
bit 15
bit 8
U-0
—
R/W-1
R/W-0
R/W-0
U-0
—
U-0
—
U-0
—
U-0
—
U1ERIP2
U1ERIP1
U1ERIP0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
-n = Value at POR
bit 15
Unimplemented: Read as ‘0’
bit 14-12
CRCIP<2:0>: CRC Generator Error Interrupt Priority bits
111= Interrupt is Priority 7 (highest priority interrupt)
•
•
•
001= Interrupt is Priority 1
000= Interrupt source is disabled
bit 11
Unimplemented: Read as ‘0’
bit 10-8
U2ERIP<2:0>: UART2 Error Interrupt Priority bits
111= Interrupt is Priority 7 (highest priority interrupt)
•
•
•
001= Interrupt is Priority 1
000= Interrupt source is disabled
bit 7
Unimplemented: Read as ‘0’
bit 6-4
U1ERIP<2:0>: UART1 Error Interrupt Priority bits
111= Interrupt is Priority 7 (highest priority interrupt)
•
•
•
001= Interrupt is Priority 1
000= Interrupt source is disabled
bit 3-0
Unimplemented: Read as ‘0’
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REGISTER 8-37: IPC18: INTERRUPT PRIORITY CONTROL REGISTER 18
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
bit 15
bit 8
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
R/W-1
R/W-0
R/W-0
LVDIP2
LVDIP1
LVDIP0
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-3
bit 2-0
Unimplemented: Read as ‘0’
LVDIP<2:0>: Low-Voltage Detect Interrupt Priority bits
111= Interrupt is Priority 7 (highest priority interrupt)
•
•
•
001= Interrupt is Priority 1
000= Interrupt source is disabled
REGISTER 8-38: IPC19: INTERRUPT PRIORITY CONTROL REGISTER 19
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
bit 15
bit 8
bit 0
U-0
—
R/W-1
R/W-0
R/W-0
U-0
—
U-0
—
U-0
—
U-0
—
CTMUIP2
CTMUIP1
CTMUIP0
bit 7
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-7
bit 6-4
Unimplemented: Read as ‘0’
CTMUIP<2:0>: CTMU Interrupt Priority bits
111= Interrupt is Priority 7 (highest priority interrupt)
•
•
•
001= Interrupt is Priority 1
000= Interrupt source is disabled
bit 3-0
Unimplemented: Read as ‘0’
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REGISTER 8-39: IPC20: INTERRUPT PRIORITY CONTROL REGISTER 20
U-0
—
R/W-1
R/W-0
R/W-0
U-0
—
R/W-1
R/W-0
R/W-0
U3TXIP2
U3TXIP1
U3TXIP0
U3RXIP2
U3RXIP1
U3RXIP0
bit 15
bit 8
U-0
—
R/W-1
R/W-0
R/W-0
U-0
—
U-0
—
U-0
—
U-0
—
U3ERIP2
U3ERIP1
U3ERIP0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
-n = Value at POR
bit 15
Unimplemented: Read as ‘0’
bit 14-12
U3TXIP<2:0>: UART3 Transmitter Interrupt Priority bits
111= Interrupt is Priority 7 (highest priority interrupt)
•
•
•
001= Interrupt is Priority 1
000= Interrupt source is disabled
bit 11
Unimplemented: Read as ‘0’
bit 10-8
U3RXIP<2:0>: UART3 Receiver Interrupt Priority bits
111= Interrupt is Priority 7 (highest priority interrupt)
•
•
•
001= Interrupt is Priority 1
000= Interrupt source is disabled
bit 7
Unimplemented: Read as ‘0’
bit 6-4
U3ERIP<2:0>: UART3 Error Interrupt Priority bits
111= Interrupt is Priority 7 (highest priority interrupt)
•
•
•
001= Interrupt is Priority 1
000= Interrupt source is disabled
bit 3-0
Unimplemented: Read as ‘0’
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REGISTER 8-40: IPC21: INTERRUPT PRIORITY CONTROL REGISTER 21
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
R/W-1
R/W-0
R/W-0
U4ERIP2
U4ERIP1
U4ERIP0
bit 15
bit 8
bit 0
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
bit 7
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
-n = Value at POR
bit 15
Unimplemented: Read as ‘0’
bit 14-12
U4ERIP<2:0>: UART4 Error Interrupt Priority bits
111= Interrupt is Priority 7 (highest priority interrupt)
•
•
•
001= Interrupt is Priority 1
000= Interrupt source is disabled
bit 11-0
Unimplemented: Read as ‘0’
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REGISTER 8-41: IPC22: INTERRUPT PRIORITY CONTROL REGISTER 22
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
bit 15
bit 8
U-0
—
R/W-1
R/W-0
R/W-0
U-0
—
R/W-1
R/W-0
R/W-0
U4TXIP2
U4TXIP1
U4TXIP0
U4RXIP2
U4RXIP1
U4RXIP0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
-n = Value at POR
bit 15-7
bit 6-4
Unimplemented: Read as ‘0’
U4TXIP<2:0>: UART4 Transmitter Interrupt Priority bits
111= Interrupt is Priority 7 (highest priority interrupt)
•
•
•
001= Interrupt is Priority 1
000= Interrupt source is disabled
bit 3
Unimplemented: Read as ‘0’
bit 2-0
U4RXIP<2:0>: UART4 Receiver Interrupt Priority bits
111= Interrupt is Priority 7 (highest priority interrupt)
•
•
•
001= Interrupt is Priority 1
000= Interrupt source is disabled
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REGISTER 8-42: IPC25: INTERRUPT PRIORITY CONTROL REGISTER 25
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
bit 15
bit 8
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
R/W-1
R/W-0
R/W-0
LCDIP2
LCDIP1
LCDIP0
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-3
bit 2-0
Unimplemented: Read as ‘0’
LCDIP<2:0>: LCD Controller Interrupt Priority bits
111= Interrupt is Priority 7 (highest priority interrupt)
•
•
•
001= Interrupt is Priority 1
000= Interrupt source is disabled
REGISTER 8-43: IPC29: INTERRUPT PRIORITY CONTROL REGISTER 29
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
bit 15
bit 8
bit 0
U-0
—
U-0
—
U-0
—
U-0
—
R/W-1
R/W-0
R/W-0
U-0
—
JTAGIP2
JTAGIP1
JTAGIP0
bit 7
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
-n = Value at POR
bit 15-7
bit 6-4
Unimplemented: Read as ‘0’
JTAGIP<2:0>: JTAG Interrupt Priority bits
111= Interrupt is Priority 7 (highest priority interrupt)
•
•
•
001= Interrupt is Priority 1
000= Interrupt source is disabled
bit 3-0
Unimplemented: Read as ‘0’
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REGISTER 8-44: INTTREG: INTERRUPT CONTROLLER TEST REGISTER
R-0, HSC
CPUIRQ
U-0
—
R/W-0
U-0
—
R-0, HSC
ILR3
R-0, HSC
ILR2
R-0, HSC
ILR1
R-0, HSC
ILR0
VHOLD
bit 15
bit 8
U-0
—
R-0, HSC
R-0, HSC
R-0, HSC
R-0, HSC
R-0, HSC
R-0, HSC
R-0, HSC
VECNUM6
VECNUM5
VECNUM4
VECNUM3
VECNUM2
VECNUM1
VECNUM0
bit 7
bit 0
Legend:
HSC = Hardware Settable/Clearable bit
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15
CPUIRQ: Interrupt Request from Interrupt Controller CPU bit
1= An interrupt request has occurred but has not yet been Acknowledged by the CPU. This happens
when the CPU priority is higher than the interrupt priority
0= No interrupt request is unacknowledged
bit 14
bit 13
Unimplemented: Read as ‘0’
VHOLD: Vector Number Capture Configuration bit
1= The VECNUM bits contain the value of the highest priority pending interrupt
0= The VECNUM bits contain the value of the last Acknowledged interrupt (i.e., the last interrupt that
has occurred with higher priority than the CPU, even if other interrupts are pending)
bit 12
Unimplemented: Read as ‘0’
bit 11-8
ILR<3:0>: New CPU Interrupt Priority Level bits
1111= CPU interrupt priority level is 15
•
•
•
0001= CPU interrupt priority level is 1
0000= CPU interrupt priority level is 0
bit 7
Unimplemented: Read as ‘0’
bit 6-0
VECNUM<5:0>: Vector Number of Pending Interrupt or Last Acknowledged Interrupt bits
VHOLD = 1: The VECNUM bits indicate the vector number (from 0 to 118) of the last interrupt to occur
VHOLD = 0: The VECNUM bits indicate the vector number (from 0 to 118) of the interrupt request
currently being handled
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8.4.3
TRAP SERVICE ROUTINE (TSR)
8.4
Interrupt Setup Procedures
A Trap Service Routine (TSR) is coded like an ISR,
except that the appropriate trap status flag in the
INTCON1 register must be cleared to avoid re-entry
into the TSR.
8.4.1
INITIALIZATION
To configure an interrupt source:
1. Set the NSTDIS (INTCON1<15>) control bit if
nested interrupts are not desired.
8.4.4
INTERRUPT DISABLE
2. Select the user-assigned priority level for the
interrupt source by writing the control bits in the
appropriate IPCx register. The priority level will
depend on the specific application and type of
interrupt source. If multiple priority levels are not
desired, the IPCx register control bits for all
enabled interrupt sources may be programmed
to the same non-zero value.
All user interrupts can be disabled using the following
procedure:
1. Push the current SR value onto the software
stack using the PUSHinstruction.
2. Force the CPU to Priority Level 7 by inclusive
ORing the value 0Eh with SRL.
To enable user interrupts, the POPinstruction may be
used to restore the previous SR value.
Note:
At a device Reset, the IPCx registers are
initialized, such that all user interrupt
sources are assigned to Priority Level 4.
Note that only user interrupts with a priority level of 7 or
less can be disabled. Trap sources (Level 8-15) cannot
be disabled.
3. Clear the interrupt flag status bit associated with
the peripheral in the associated IFSx register.
The DISI instruction provides a convenient way to
disable interrupts of Priority Levels 1-6 for a fixed
period of time. Level 7 interrupt sources are not
disabled by the DISIinstruction.
4. Enable the interrupt source by setting the
interrupt enable control bit associated with the
source in the appropriate IECx register.
8.4.2
INTERRUPT SERVICE ROUTINE
(ISR)
The method that is used to declare an Interrupt Service
Routine (ISR) and initialize the IVT with the correct vec-
tor address will depend on the programming language
(i.e., ‘C’ or assembler) and the language development
toolsuite that is used to develop the application. In
general, the user must clear the interrupt flag in the
appropriate IFSx register for the source of the interrupt
that the ISR handles; otherwise, the ISR will be
re-entered immediately after exiting the routine. If the
ISR is coded in assembly language, it must be termi-
nated using a RETFIEinstruction to unstack the saved
PC value, SRL value and old CPU priority level.
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NOTES:
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• Software-controllable switching between various
clock sources
9.0
OSCILLATOR
CONFIGURATION
• Software-controllable postscaler for selective
clocking of CPU for system power savings
Note:
This data sheet summarizes the features of
this group of PIC24F devices. It is not
intended to be a comprehensive reference
source. For more information, refer to the
“PIC24F Family Reference Manual”,
“Section 6. Oscillator” (DS39700).
• A Fail-Safe Clock Monitor (FSCM) that detects
clock failure and permits safe application recovery
or shutdown
• A separate and independently configurable system
clock output for synchronizing external hardware
A simplified diagram of the oscillator system is shown
in Figure 9-1.
The oscillator system for PIC24FJ128GA310 family
devices has the following features:
• A total of four external and internal oscillator options
as clock sources, providing 11 different clock modes
• On-chip 4x PLL to boost internal operating frequency
on select internal and external oscillator sources
FIGURE 9-1:
PIC24FJ128GA310 FAMILY CLOCK DIAGRAM
Primary Oscillator
REFOCON<15:8>
XT, HS, EC
OSCO
OSCI
Reference Clock
Generator
XTPLL, HSPLL,
ECPLL, FRCPLL
4 x PLL
REFO
8 MHz
4 MHz
FRC
Oscillator
FRCDIV
8 MHz
(nominal)
Peripherals
CLKDIV<10:8>
FRC
CLKO
CPU
LPRC
LPRC
Oscillator
31 kHz (nominal)
Secondary Oscillator
SOSC
SOSCO
SOSCI
CLKDIV<14:12>
SOSCEN
Enable
Oscillator
Clock Control Logic
Fail-Safe
Clock
Monitor
WDT, PWRT
Clock Source Option
for Other Modules
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9.1
CPU Clocking Scheme
9.2
Initial Configuration on POR
The system clock source can be provided by one of
four sources:
The oscillator source (and operating mode) that is
used at a device Power-on Reset event is selected
using Configuration bit settings. The Oscillator
Configuration bit settings are located in the
Configuration registers in the program memory (refer
to Section 29.0 “Special Features” for further
details). The Primary Oscillator Configuration bits,
POSCMD<1:0> (Configuration Word 2<1:0>), and
the Initial Oscillator Select Configuration bits,
FNOSC<2:0> (Configuration Word 2<10:8>), select
the oscillator source that is used at a Power-on Reset.
The FRC Primary Oscillator (FRCDIV) with postscaler
is the default (unprogrammed) selection. The second-
ary oscillator, or one of the internal oscillators, may be
chosen by programming these bit locations.
• Primary Oscillator (POSC) on the OSCI and
OSCO pins
• Secondary Oscillator (SOSC) on the SOSCI and
SOSCO pins
• Fast Internal RC (FRC) Oscillator
• Low-Power Internal RC (LPRC) Oscillator
The primary oscillator and FRC sources have the
option of using the internal 4x PLL. The frequency of
the FRC clock source can optionally be reduced by the
programmable clock divider. The selected clock source
generates the processor and peripheral clock sources.
The processor clock source is divided by two to pro-
duce the internal instruction cycle clock, FCY. In this
document, the instruction cycle clock is also denoted
by FOSC/2. The internal instruction cycle clock, FOSC/2,
can be provided on the OSCO I/O pin for some
operating modes of the primary oscillator.
The Configuration bits allow users to choose between
the various clock modes, shown in Table 9-1.
9.2.1
CLOCK SWITCHING MODE
CONFIGURATION BITS
The FCKSM Configuration bits (Configuration
Word 2<7:6>) are used to jointly configure device clock
switching and the Fail-Safe Clock Monitor (FSCM).
Clock switching is enabled only when FCKSM1 is
programmed (‘0’). The FSCM is enabled only when the
FCKSM<1:0> bits are both programmed (‘00’).
TABLE 9-1:
CONFIGURATION BIT VALUES FOR CLOCK SELECTION
Oscillator Mode
Oscillator Source
POSCMD<1:0>
FNOSC<2:0>
Note
1, 2
Fast RC Oscillator with Postscaler
(FRCDIV)
Internal
11
111
(Reserved)
Internal
Internal
xx
11
11
110
101
100
1
1
1
Low-Power RC Oscillator (LPRC)
Secondary (Timer1) Oscillator
(SOSC)
Secondary
Primary Oscillator (XT) with PLL
Module (XTPLL)
Primary
Primary
01
00
011
011
Primary Oscillator (EC) with PLL
Module (ECPLL)
Primary Oscillator (HS)
Primary Oscillator (XT)
Primary Oscillator (EC)
Primary
Primary
Primary
Internal
10
01
00
11
010
010
010
001
Fast RC Oscillator with PLL Module
(FRCPLL)
1
1
Fast RC Oscillator (FRC)
Internal
11
000
Note 1: OSCO pin function is determined by the OSCIOFCN Configuration bit.
2: This is the default oscillator mode for an unprogrammed (erased) device.
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The CLKDIV register (Register 9-2) controls the
features associated with Doze mode, as well as the
postscaler for the FRC oscillator.
9.3
Control Registers
The operation of the oscillator is controlled by three
Special Function Registers:
The OSCTUN register (Register 9-3) allows the user to
fine tune the FRC oscillator over a range of approxi-
mately ±12%. Each bit increment or decrement
changes the factory calibrated frequency of the FRC
oscillator by a fixed amount.
• OSCCON
• CLKDIV
• OSCTUN
The OSCCON register (Register 9-1) is the main con-
trol register for the oscillator. It controls clock source
switching and allows the monitoring of clock sources.
REGISTER 9-1:
OSCCON: OSCILLATOR CONTROL REGISTER
U-0
—
R-0
R-0
R-0
U-0
—
R/W-x(1)
NOSC2
R/W-x(1)
NOSC1
R/W-x(1)
NOSC0
COSC2
COSC1
COSC0
bit 15
bit 8
R/SO-0
R/W-0
IOLOCK(2)
R-0(3)
LOCK
U-0
—
R/CO-0
CF
R/W-0
R/W-0
R/W-0
CLKLOCK
bit 7
POSCEN
SOSCEN
OSWEN
bit 0
Legend:
CO = Clearable Only bit
W = Writable bit
SO = Settable Only bit
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
R = Readable bit
-n = Value at POR
‘1’ = Bit is set
bit 15
Unimplemented: Read as ‘0’
bit 14-12
COSC<2:0>: Current Oscillator Selection bits
111= Fast RC Oscillator with Postscaler (FRCDIV)
110= Reserved
101= Low-Power RC Oscillator (LPRC)
100= Secondary Oscillator (SOSC)
011= Primary Oscillator with PLL module (XTPLL, HSPLL, ECPLL)
010= Primary Oscillator (XT, HS, EC)
001= Fast RC Oscillator with Postscaler and PLL module (FRCPLL)
000= Fast RC Oscillator (FRC)
bit 11
Unimplemented: Read as ‘0’
bit 10-8
NOSC<2:0>: New Oscillator Selection bits(1)
111= Fast RC Oscillator with Postscaler (FRCDIV)
110= Reserved
101= Low-Power RC Oscillator (LPRC)
100= Secondary Oscillator (SOSC)
011= Primary Oscillator with PLL module (XTPLL, HSPLL, ECPLL)
010= Primary Oscillator (XT, HS, EC)
001= Fast RC Oscillator with Postscaler and PLL module (FRCPLL)
000= Fast RC Oscillator (FRC)
Note 1: Reset values for these bits are determined by the FNOSC Configuration bits.
2: The state of the IOLOCK bit can only be changed once an unlocking sequence has been executed. In
addition, if the IOL1WAY Configuration bit is ‘1’ once the IOLOCK bit is set, it cannot be cleared.
3: This bit also resets to ‘0’ during any valid clock switch or whenever a Non-PLL Clock mode is selected.
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REGISTER 9-1:
OSCCON: OSCILLATOR CONTROL REGISTER (CONTINUED)
bit 7
CLKLOCK: Clock Selection Lock Enabled bit
If FSCM is enabled (FCKSM1 = 1):
1= Clock and PLL selections are locked
0= Clock and PLL selections are not locked and may be modified by setting the OSWEN bit
If FSCM is disabled (FCKSM1 = 0):
Clock and PLL selections are never locked and may be modified by setting the OSWEN bit.
bit 6
bit 5
IOLOCK: I/O Lock Enable bit(2)
1= I/O lock is active
0= I/O lock is not active
LOCK: PLL Lock Status bit(3)
1= PLL module is in lock or PLL module start-up timer is satisfied
0= PLL module is out of lock, PLL start-up timer is running or PLL is disabled
bit 4
bit 3
Unimplemented: Read as ‘0’
CF: Clock Fail Detect bit
1= FSCM has detected a clock failure
0= No clock failure has been detected
bit 2
bit 1
bit 0
POSCEN: Primary Oscillator Sleep Enable bit
1= Primary oscillator continues to operate during Sleep mode
0= Primary oscillator is disabled during Sleep mode
SOSCEN: 32 kHz Secondary Oscillator (SOSC) Enable bit
1= Enable secondary oscillator
0= Disable secondary oscillator
OSWEN: Oscillator Switch Enable bit
1= Initiate an oscillator switch to a clock source specified by the NOSC<2:0> bits
0= Oscillator switch is complete
Note 1: Reset values for these bits are determined by the FNOSC Configuration bits.
2: The state of the IOLOCK bit can only be changed once an unlocking sequence has been executed. In
addition, if the IOL1WAY Configuration bit is ‘1’ once the IOLOCK bit is set, it cannot be cleared.
3: This bit also resets to ‘0’ during any valid clock switch or whenever a Non-PLL Clock mode is selected.
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REGISTER 9-2:
CLKDIV: CLOCK DIVIDER REGISTER
R/W-0
ROI
R/W-0
R/W-0
R/W-0
R/W-0
DOZEN(1)
R/W-0
R/W-0
R/W-1
DOZE2
DOZE1
DOZE0
RCDIV2
RCDIV1
RCDIV0
bit 15
bit 8
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
-n = Value at POR
bit 15
ROI: Recover on Interrupt bit
1= Interrupts clear the DOZEN bit and reset the CPU peripheral clock ratio to 1:1
0= Interrupts have no effect on the DOZEN bit
bit 14-12
DOZE<2:0>: CPU Peripheral Clock Ratio Select bits
111= 1:128
110= 1:64
101= 1:32
100= 1:16
011= 1:8
010= 1:4
001= 1:2
000= 1:1
bit 11
DOZEN: DOZE Enable bit(1)
1= DOZE<2:0> bits specify the CPU peripheral clock ratio
0= CPU peripheral clock ratio set to 1:1
bit 10-8
RCDIV<2:0>: FRC Postscaler Select bits
111= 31.25 kHz (divide by 256)
110= 125 kHz (divide by 64)
101= 250 kHz (divide by 32)
100= 500 kHz (divide by 16)
011= 1 MHz (divide by 8)
010= 2 MHz (divide by 4)
001= 4 MHz (divide by 2)
000= 8 MHz (divide by 1)
bit 7-0
Unimplemented: Read as ‘0’
Note 1: This bit is automatically cleared when the ROI bit is set and an interrupt occurs.
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REGISTER 9-3:
OSCTUN: FRC OSCILLATOR TUNE REGISTER
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
bit 15
bit 8
U-0
—
U-0
—
R/W-0
TUN5(1)
R/W-0
TUN4(1)
R/W-0
TUN3(1)
R/W-0
TUN2(1)
R/W-0
TUN1(1)
R/W-0
TUN0(1)
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-6
bit 5-0
Unimplemented: Read as ‘0’
TUN<5:0>: FRC Oscillator Tuning bits(1)
011111= Maximum frequency deviation
011110=
000001=
000000= Center frequency, oscillator is running at factory calibrated frequency
111111=
100001=
100000= Minimum frequency deviation
Note 1: Increments or decrements of TUN<5:0> may not change the FRC frequency in equal steps over the FRC
tuning range and may not be monotonic.
9.4.1
ENABLING CLOCK SWITCHING
9.4
Clock Switching Operation
To enable clock switching, the FCKSM Configuration bits
in CW2 must be programmed to ‘00’. (Refer to
Section 29.1 “Configuration Bits” for further details.)
If the FCKSM Configuration bits are unprogrammed
(‘1x’), the clock switching function and Fail-Safe Clock
Monitor function are disabled. This is the default setting.
With few limitations, applications are free to switch
between any of the four clock sources (POSC, SOSC,
FRC and LPRC) under software control and at any
time. To limit the possible side effects that could result
from this flexibility, PIC24F devices have a safeguard
lock built into the switching process.
The NOSCx control bits (OSCCON<10:8>) do not
control the clock selection when clock switching is dis-
abled. However, the COSCx bits (OSCCON<14:12>)
will reflect the clock source selected by the FNOSCx
Configuration bits.
Note:
The Primary Oscillator mode has three
different submodes (XT, HS and EC)
which are determined by the POSCMDx
Configuration bits. While an application
can switch to and from Primary Oscillator
mode in software, it cannot switch
between the different primary submodes
without reprogramming the device.
The OSWEN control bit (OSCCON<0>) has no effect
when clock switching is disabled. It is held at ‘0’ at all
times.
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A recommended code sequence for a clock switch
includes the following:
9.4.2
OSCILLATOR SWITCHING
SEQUENCE
1. Disable interrupts during the OSCCON register
unlock and write sequence.
At a minimum, performing a clock switch requires this
basic sequence:
2. Execute the unlock sequence for the OSCCON
high byte by writing 78h and 9Ah to
1. If
desired,
read
the
COSCx
bits
(OSCCON<14:12>) to determine the current
oscillator source.
OSCCON<15:8>
instructions.
in
two
back-to-back
2. Perform the unlock sequence to allow a write to
the OSCCON register high byte.
3. Write new oscillator source to the NOSCx bits in
the instruction immediately following the unlock
sequence.
3. Write the appropriate value to the NOSCx bits
(OSCCON<10:8>) for the new oscillator source.
4. Execute the unlock sequence for the OSCCON
low byte by writing 46h and 57h to
OSCCON<7:0> in two back-to-back instructions.
4. Perform the unlock sequence to allow a write to
the OSCCON register low byte.
5. Set the OSWEN bit to initiate the oscillator
switch.
5. Set the OSWEN bit in the instruction immediately
following the unlock sequence.
Once the basic sequence is completed, the system
clock hardware responds automatically as follows:
6. Continue to execute code that is not
clock-sensitive (optional).
1. The clock switching hardware compares the
COSCx bits with the new value of the NOSCx
bits. If they are the same, then the clock switch
is a redundant operation. In this case, the
OSWEN bit is cleared automatically and the
clock switch is aborted.
7. Invoke an appropriate amount of software delay
(cycle counting) to allow the selected oscillator
and/or PLL to start and stabilize.
8. Check to see if OSWEN is ‘0’. If it is, the switch
was successful. If OSWEN is still set, then
check the LOCK bit to determine the cause of
failure.
2. If a valid clock switch has been initiated, the
LOCK (OSCCON<5>) and CF (OSCCON<3>)
bits are cleared.
The core sequence for unlocking the OSCCON register
and initiating a clock switch is shown in Example 9-1.
3. The new oscillator is turned on by the hardware
if it is not currently running. If a crystal oscillator
must be turned on, the hardware will wait until
the OST expires. If the new source is using the
PLL, then the hardware waits until a PLL lock is
detected (LOCK = 1).
EXAMPLE 9-1:
BASIC CODE SEQUENCE
FOR CLOCK SWITCHING
;Place the new oscillator selection in W0
;OSCCONH (high byte) Unlock Sequence
MOV
MOV
MOV
MOV.b
MOV.b
#OSCCONH, w1
#0x78, w2
#0x9A, w3
w2, [w1]
4. The hardware waits for 10 clock cycles from the
new clock source and then performs the clock
switch.
w3, [w1]
5. The hardware clears the OSWEN bit to indicate a
successful clock transition. In addition, the
NOSCx bits values are transferred to the COSCx
bits.
;Set new oscillator selection
MOV.b WREG, OSCCONH
;OSCCONL (low byte) unlock sequence
MOV
MOV
MOV
MOV.b
MOV.b
#OSCCONL, w1
#0x46, w2
#0x57, w3
w2, [w1]
6. The old clock source is turned off at this time, with
the exception of LPRC (if WDT or FSCM are
enabled) or SOSC (if SOSCEN remains set).
w3, [w1]
Note 1: The processor will continue to execute
code throughout the clock switching
sequence. Timing-sensitive code should
not be executed during this time.
;Start oscillator switch operation
BSET OSCCON,#0
2: Direct clock switches between any
Primary Oscillator mode with PLL and
FRCPLL mode are not permitted. This
applies to clock switches in either direc-
tion. In these instances, the application
must switch to FRC mode as a transition
clock source between the two PLL modes.
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In general, the crystal circuit connections should be as
short as possible. It is also good practice to surround
the crystal circuit with a ground loop or ground plane.
For more information on crystal circuit design, please
refer to Section 6 “Oscillator” (DS39700) of the
“PIC24F Family Reference Manual”. Additional infor-
mation is also available in these Microchip Application
Notes:
9.5
Secondary Oscillator (SOSC)
9.5.1
BASIC SOSC OPERATION
PIC24FJ128GA310 family devices do not have to set the
SOSCEN bit to use the secondary oscillator. Any module
requiring the SOSC (such as RTCC, Timer1 or DSWDT)
will automatically turn on the SOSC when the clock signal
is needed. The SOSC, however, has a long start-up time.
To avoid delays for peripheral start-up, the SOSC can be
manually started using the SOSCEN bit.
• AN826, “Crystal Oscillator Basics and Crystal
Selection for rfPIC® and PICmicro® Devices”
(DS00826)
• AN849, “Basic PICmicro® Oscillator Design”
To use the secondary oscillator, the SOSCSEL<1:0> bits
(CW3<9:8>) must be configured in an oscillator mode –
either ‘11’ or ‘01’. Setting the SOSCSEL bits to ‘00’
configures the SOSC pins for Digital mode, enabling
digital I/O functionality on the pins. Digital functionality
will not be available if the SOSC is configured in either of
the oscillator modes.
(DS00849).
9.6
Reference Clock Output
In addition to the CLKO output (FOSC/2) available in
certain oscillator modes, the device clock in the
PIC24FJ128GA310 family devices can also be config-
ured to provide a reference clock output signal to a port
pin. This feature is available in all oscillator configura-
tions and allows the user to select a greater range of
clock submultiples to drive external devices in the
application.
9.5.2
LOW-POWER SOSC OPERATION
The secondary oscillator can operate in two distinct
levels of power consumption, based on device configu-
ration. In Low-Power mode, the oscillator operates in a
low drive strength, low-power state. By default, the
oscillator uses a higher drive strength, and therefore,
requires more power. The Secondary Oscillator Mode
Configuration bits, SOSCSEL<1:0> (CW3<9:8>),
determine the oscillator’s power mode. Programming
the SOSCSEL bits to ‘01’ selects low-power operation.
This reference clock output is controlled by the
REFOCON register (Register 9-4). Setting the ROEN
bit (REFOCON<15>) makes the clock signal available
on the REFO pin. The RODIV bits (REFOCON<11:8>)
enable the selection of 16 different clock divider
options.
The lower drive strength of this mode makes the SOSC
more sensitive to noise and requires a longer start-up
time. When Low-Power mode is used, care must be
taken in the design and layout of the SOSC circuit to
ensure that the oscillator starts up and oscillates
properly.
The ROSSLP and ROSEL bits (REFOCON<13:12>)
control the availability of the reference output during
Sleep mode. The ROSEL bit determines if the oscillator
on OSC1 and OSC2, or the current system clock source,
is used for the reference clock output. The ROSSLP bit
determines if the reference source is available on REFO
when the device is in Sleep mode.
9.5.3
EXTERNAL (DIGITAL) CLOCK
MODE (SCLKI)
To use the reference clock output in Sleep mode, both
the ROSSLP and ROSEL bits must be set. The device
clock must also be configured for one of the primary
modes (EC, HS or XT). Otherwise, if the POSCEN bit
is also not set, the oscillator on OSC1 and OSC2 will be
powered down when the device enters Sleep mode.
Clearing the ROSEL bit allows the reference output
frequency to change as the system clock changes
during any clock switches.
The SOSC can also be configured to run from an
external 32 kHz clock source, rather than the internal
oscillator. In this mode, also referred to as Digital mode,
the clock source provided on the SCLKI pin is used to
clock any modules that are configured to use the
secondary oscillator. In this mode, the crystal driving
circuit is disabled and the SOSCEN bit (OSCCON<1>)
has no effect.
9.5.4
SOSC LAYOUT CONSIDERATIONS
The pinout limitations on low pin count devices, such as
those in the PIC24FJ128GA310 family, may make the
SOSC more susceptible to noise than other PIC24FJ
devices. Unless proper care is taken in the design and
layout of the SOSC circuit, this external noise may
introduce inaccuracies into the oscillator’s period.
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REGISTER 9-4:
REFOCON: REFERENCE OSCILLATOR CONTROL REGISTER
R/W-0
ROEN
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
ROSSLP
ROSEL
RODIV3
RODIV2
RODIV1
RODIV0
bit 15
bit 8
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15
ROEN: Reference Oscillator Output Enable bit
1= Reference oscillator is enabled on REFO pin
0= Reference oscillator is disabled
bit 14
bit 13
Unimplemented: Read as ‘0’
ROSSLP: Reference Oscillator Output Stop in Sleep bit
1= Reference oscillator continues to run in Sleep
0= Reference oscillator is disabled in Sleep
bit 12
ROSEL: Reference Oscillator Source Select bit
1= Primary oscillator is used as the base clock. Note that the crystal oscillator must be enabled using
the FOSC<2:0> bits; the crystal maintains the operation in Sleep mode.
0= System clock is used as the base clock; base clock reflects any clock switching of the device
bit 11-8
RODIV<3:0>: Reference Oscillator Divisor Select bits
1111= Base clock value divided by 32,768
1110= Base clock value divided by 16,384
1101= Base clock value divided by 8,192
1100= Base clock value divided by 4,096
1011= Base clock value divided by 2,048
1010= Base clock value divided by 1,024
1001= Base clock value divided by 512
1000= Base clock value divided by 256
0111= Base clock value divided by 128
0110= Base clock value divided by 64
0101= Base clock value divided by 32
0100= Base clock value divided by 16
0011= Base clock value divided by 8
0010= Base clock value divided by 4
0001= Base clock value divided by 2
0000= Base clock value
bit 7-0
Unimplemented: Read as ‘0’
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NOTES:
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10.1 Overview of Power-Saving Modes
10.0 POWER-SAVING FEATURES
In addition to full-power operation, otherwise known as
Run mode, the PIC24FJ128GA310 family of devices
offers three Instruction-Based, Power-Saving modes
and one Hardware-Based mode:
Note:
This data sheet summarizes the features
of this group of PIC24FJ devices. It is not
intended to be
a
comprehensive
reference source. For more information,
refer to the “PIC24F Family Reference
Manual”, “Section 57. Power-Saving
Features with VBAT” (DS30622).
• Idle
• Sleep (Sleep and Low-Voltage Sleep)
• Deep Sleep
• VBAT (with and without RTCC)
The PIC24FJ128GA310 family of devices provides the
ability to manage power consumption by selectively
managing clocking to the CPU and the peripherals. In
general, a lower clock frequency and a reduction in the
number of circuits being clocked reduces consumed
power.
All four modes can be activated by powering down dif-
ferent functional areas of the microcontroller, allowing
progressive reductions of operating and Idle power
consumption. In addition, three of the modes can be
tailored for more power reduction, at a trade-off of
some operating features. Table 10-1 lists all of the
operating modes, in order of increasing power savings.
Table 10-2 summarizes how the microcontroller exits
the different modes. Specific information is provided in
the following sections.
PIC24FJ128GA310 family devices manage power
consumption with five strategies:
• Instruction-Based Power Reduction Modes
• Hardware-Based Power Reduction Features
• Clock Frequency Control
• Software Controlled Doze Mode
• Selective Peripheral Control in Software
Combinations of these methods can be used to
selectively tailor an application’s power consumption,
while still maintaining critical application features, such
as timing-sensitive communications.
TABLE 10-1: OPERATING MODES FOR PIC24FJ128GA310 FAMILY DEVICES
Active Systems
DSGPR0/
DSGPR1
Retention
Mode
Entry
Data RAM
Retention
Core
Peripherals
RTCC(1)
Run (default)
Idle
N/A
Y
N
Y
Y
Y
Y
Y
Y
Y
Y
Instruction
Sleep:
Sleep
Instruction
N
N
S(2)
S(2)
Y
Y
Y
Y
Y
Y
Low-Voltage Sleep
Instruction +
RETEN bit
Deep Sleep:
Deep Sleep
Instruction +
DSEN bit +
N
N
N
N
N
N
Y
Y
Y
Y
VBAT:
with RTCC
Hardware
Note 1: If RTCC is otherwise enabled in firmware.
2: A select peripheral can operate during this mode from LPRC or some external clock.
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TABLE 10-2: EXITING POWER SAVING MODES
Exit Conditions
Code
Mode
Interrupts
All INT0
Resets
POR
Execution
RTCC
Alarm
VDD
Restore
Resumes(2)
WDT
All
MCLR
Idle
Y
Y
Y
Y
N
N
Y
Y
Y
N
Y
Y
Y
N
Y
Y
Y
N
Y
Y
Y(1)
N/A
N/A
N/A
Y
Next instruction
Sleep (all modes)
Deep Sleep
VBAT
Y
N
N
Y
Y
N
Reset vector
Reset vector
N
Note 1: Deep Sleep WDT.
2: Code execution resumption is also valid for all the exit conditions; for example, a MCLR and POR exit will
cause code execution from the Reset vector.
Sleep and Idle modes can be exited as a result of an
enabled interrupt, WDT time-out or a device Reset.
When the device exits these modes, it is said to
“wake-up”.
10.1.1
INSTRUCTION-BASED
POWER-SAVING MODES
Three of the power-saving modes are entered through
the execution of the PWRSAV instruction. Sleep mode
stops clock operation and halts all code execution. Idle
mode halts the CPU and code execution, but allows
peripheral modules to continue operation. Deep Sleep
mode stops clock operation, code execution and all
peripherals, except RTCC and DSWDT. It also freezes
I/O states and removes power to Flash memory and
may remove power to SRAM.
The features enabled with the low-voltage/retention
regulator results in some changes to the way that Sleep
mode behaves. See Section 10.3 “Sleep Mode”.
10.1.1.1
Interrupts Coincident with Power
Save Instructions
Any interrupt that coincides with the execution of a
PWRSAV instruction will be held off until entry into
Sleep/Deep Sleep or Idle mode has completed. The
device will then wake-up from Sleep/Deep Sleep or Idle
mode.
The assembly syntax of the PWRSAVinstruction is shown
in Example 10-1. Sleep and Idle modes are entered
directly with a single assembler command. Deep Sleep
requires an additional sequence to unlock and enable
the entry into Deep Sleep, which is described in
Section 10.4.1 “Entering Deep Sleep Mode”.
Note: SLEEP_MODE and IDLE_MODE are
constants defined in the assembler
include file for the selected device.
To enter Deep Sleep, the DSCON<0> bit
should be cleared before setting the
DSEN bit,
EXAMPLE 10-1:
PWRSAVINSTRUCTION SYNTAX
// Syntax to enter Sleep mode:
PWRSAV
//
#SLEEP_MODE
; Put the device into SLEEP mode
//Synatx to enter Idle mode:
PWRSAV
//
#IDLE_MODE
; Put the device into IDLE mode
// Syntax to enter Deep Sleep mode:
// First use the unlock sequence to set the DSEN bit (see Example 10-2)
CLR
DSCON
CLR
DSCON
; (repeat the command)
BSET
BSET
PWRSAV
DSCON, #DSEN
DSCON, #DSEN
; Enable Deep Sleep
; Enable Deep Sleep (repeat the command)
; Put the device into Deep SLEEP mode
#SLEEP_MODE
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10.1.2
HARDWARE-BASED
POWER-SAVING MODE
10.3 Sleep Mode
Sleep mode includes these features:
The hardware-based VBAT mode does not require any
action by the user during code development. Instead, it
is a hardware design feature that allows the micro-
controller to retain critical data (using the DSGPRn
registers) and maintain the RTCC when VDD is removed
from the application. This is accomplished by supplying
a backup power source to a specific power pin. VBAT
mode is described in more detail in Section 10.5 “Vbat
Mode”.
• The system clock source is shut down. If an
on-chip oscillator is used, it is turned off.
• The device current consumption will be reduced
to a minimum provided that no I/O pin is sourcing
current.
• The I/O pin directions and states are frozen.
• The Fail-Safe Clock Monitor does not operate
during Sleep mode since the system clock source
is disabled.
10.1.3
LOW-VOLTAGE/RETENTION
REGULATOR
• The LPRC clock will continue to run in Sleep
mode if the WDT or RTCC, with LPRC as clock
source, is enabled.
PIC24FJ128GA310 family devices incorporate
a
second on-chip voltage regulator, designed to provide
power to select microcontroller features at 1.2V nomi-
nal. This regulator allows features, such as data RAM
and the WDT, to be maintained in power-saving modes
where they would otherwise be inactive, or maintain
them at a lower power than would otherwise be the
case.
• The WDT, if enabled, is automatically cleared
prior to entering Sleep mode.
• Some device features or peripherals may
continue to operate in Sleep mode. This includes
items, such as the input change notification on the
I/O ports, or peripherals that use an external clock
input. Any peripheral that requires the system
clock source for its operation will be disabled in
Sleep mode.
The low-voltage/retention regulator is only available
when Sleep or Deep Sleep modes are invoked. It is
controlled by the LPCFG Configuration bit (CW1<10>)
and in firmware by the RETEN bit (RCON<12>).
LPCFG must be programmed (= 0) and the RETEN bit
must be set (= 1) for the regulator to be enabled.
The device will wake-up from Sleep mode on any of
these events:
• On any interrupt source that is individually
enabled
• On any form of device Reset
• On a WDT time-out
10.2 Idle Mode
Idle mode has these features:
On wake-up from Sleep, the processor will restart with
the same clock source that was active when Sleep
mode was entered.
• The CPU will stop executing instructions.
• The WDT is automatically cleared.
• The system clock source remains active. By
default, all peripheral modules continue to operate
normally from the system clock source, but can
also be selectively disabled (see Section 10.8
“Selective Peripheral Module Control”).
10.3.1
LOW-VOLTAGE/RETENTION SLEEP
MODE
Low-Voltage/Retention Sleep mode functions as Sleep
mode with the same features and wake-up triggers.
The difference is that the low-voltage/retention regula-
tor allows core digital logic voltage (VCORE) to drop to
1.2V nominal. This permits an incremental reduction of
power consumption over what would be required if
VCORE was maintained at a 1.8V (minimum) level.
• If the WDT or FSCM is enabled, the LPRC will
also remain active.
The device will wake from Idle mode on any of these
events:
• Any interrupt that is individually enabled
• Any device Reset
Low-Voltage Sleep mode requires a longer wake-up
time than Sleep mode, due to the additional time
required to bring VCORE back to 1.8V (known as TREG).
In addition, the use of the low-voltage/retention regula-
tor limits the amount of current that can be sourced to
any active peripherals, such as the RTCC/LCD, etc.
• A WDT time-out
On wake-up from Idle, the clock is re-applied to the
CPU and instruction execution begins immediately,
starting with the instruction following the PWRSAV
instruction or the first instruction in the ISR.
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The sequence to enter Deep Sleep mode is:
10.4 Deep Sleep Mode
1. If the application requires the Deep Sleep WDT,
enable it and configure its clock source. For
more information on Deep Sleep WDT, see
Section 10.4.5 “Deep Sleep WDT”.
Deep Sleep mode provides the lowest levels of power
consumption available from the Instruction-Based
modes.
Deep Sleep modes have these features:
2. If the application requires Deep Sleep BOR,
enable it by programming the DSBOREN
Configuration bit (FDS<6>).
• The system clock source is shut down. If an
on-chip oscillator is used, it is turned off.
• The device current consumption will be reduced
to a minimum.
3. If the application requires wake-up from Deep
Sleep on RTCC alarm, enable and configure the
RTCC module. For more information on RTCC,
see 22.0 “Real-Time Clock and Calendar
(RTCC)”.
• The I/O pin directions and states are frozen.
• The Fail-Safe Clock Monitor does not operate
during Sleep mode since the system clock source
is disabled.
4. If needed, save any critical application context
data by writing it to the DSGPR0 and DSGPR1
registers (optional).
• The LPRC clock will continue to run in Deep
Sleep mode if the WDT or RTCC with LPRC as
clock source is enabled.
5. Enable Deep Sleep mode by setting the DSEN
bit (DSCON<15>).
• The dedicated Deep Sleep WDT and BOR
systems, if enabled, are used.
Note:
A repeat sequence is required to set the
DSEN bit. The repeat sequence (repeating
the instruction twice) is required to write
into any of the Deep Sleep registers
(DSCON, DSWAKE, DSGPR0, DSGPR1).
This is required to avoid the user from
entering Deep Sleep by mistake. Any write
to these registers has to be done twice to
actually complete the write (see
Example 10-2).
• The RTCC and its clock source continue to run, if
enabled. All other peripherals are disabled.
Entry into Deep Sleep mode is completely under
software control. Exit from the Deep Sleep modes can
be triggered from any of the following events:
• POR event
• MCLR event
• RTCC alarm (If the RTCC is present)
• External Interrupt 0
6. Enter Deep Sleep mode by issuing 3 NOP
commands, and then a PWRSAV #0instruction.
• Deep Sleep Watchdog Timer (DSWDT) time-out
10.4.1
ENTERING DEEP SLEEP MODE
Any time the DSEN bit is set, all bits in the DSWAKE
register will be automatically cleared.
Deep Sleep mode is entered by setting the DSEN bit in
the DSCON register, and then executing a Sleep
command (PWRSAV#SLEEP_MODE) within one instruc-
tion cycle, to minimize the chance that Deep Sleep will
be spuriously entered.
EXAMPLE 10-2:
THE REPEAT SEQUENCE
Example 1:
mov #8000, w2
mov w2, DSCON
mov w2, DSCON
; enable DS
If the PWRSAV command is not given within one
instruction cycle, the DSEN bit will be cleared by the
hardware and must be set again by the software before
entering Deep Sleep mode. The DSEN bit is also
automatically cleared when exiting Deep Sleep mode.
; second write required to
actually write to DSCON
Example 2:
bset
nop
DSCON, #15
Note: To re-enter Deep Sleep after a Deep Sleep
wake-up, allow a delay of at least 3 TCY
after clearing the RELEASE bit.
nop
nop
bset
DSCON, #15 ; enable DS (two writes required)
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10.4.2
EXITING DEEP SLEEP MODES
10.4.3
SAVING CONTEXT DATA WITH THE
DSGPRn REGISTERS
Deep Sleep modes exit on any one of the following events:
As exiting Deep Sleep mode causes a POR, most
Special Function Registers reset to their default POR
values. In addition, because VCORE power is not sup-
plied in Deep Sleep mode, information in data RAM
may be lost when exiting this mode.
• POR event on VDD supply. If there is no DSBOR
circuit to re-arm the VDD supply POR circuit, the
external VDD supply must be lowered to the
natural arming voltage of the POR circuit.
• DSWDT time-out. When the DSWDT timer times
out, the device exits Deep Sleep.
Applications which require critical data to be saved
prior to Deep Sleep may use the Deep Sleep General
Purpose registers, DSGPR0 and DSGPR1, or data
EEPROM (if available). Unlike other SFRs, the
contents of these registers are preserved while the
device is in Deep Sleep mode. After exiting Deep
Sleep, software can restore the data by reading the
registers and clearing the RELEASE bit (DSCON<0>).
• RTCC alarm (if RTCEN = 1).
• Assertion (‘0’) of the MCLR pin.
• Assertion of the INT0 pin (if the interrupt was
enabled before Deep Sleep mode was entered).
The polarity configuration is used to determine the
assertion level (‘0’ or ‘1’) of the pin that will cause
an exit from Deep Sleep mode. Exiting from Deep
Sleep mode requires a change on the INT0 pin
while in Deep Sleep mode.
10.4.4
I/O PINS IN DEEP SLEEP MODES
During Deep Sleep, the general purpose I/O pins retain
their previous states and the Secondary Oscillator
(SOSC) will remain running, if enabled. Pins that are
configured as inputs (TRISx bit set), prior to entry into
Deep Sleep, remain high-impedance during Deep
Sleep. Pins that are configured as outputs (TRISx bit
clear), prior to entry into Deep Sleep, remain as output
pins during Deep Sleep. While in this mode, they
continue to drive the output level determined by their
corresponding LATx bit at the time of entry into Deep
Sleep.
Note:
Any interrupt pending, when entering
Deep Sleep mode, is cleared.
Exiting Deep Sleep generally does not retain the state
of the device and is equivalent to a Power-on Reset
(POR) of the device. Exceptions to this include the
RTCC (if present), which remains operational through
the wake-up, the DSGPRx registers and DSWDT.
Wake-up events that occur from the time Deep Sleep
exits, until the time the POR sequence completes, are
not ignored. The DSWAKE register will capture ALL
wake-up events, from DSEN set to RELEASE clear.
Once the device wakes back up, all I/O pins continue to
maintain their previous states, even after the device
has finished the POR sequence and is executing
application code again. Pins configured as inputs
during Deep Sleep remain high-impedance, and pins
configured as outputs continue to drive their previous
value. After waking up, the TRIS and LAT registers, and
the SOSCEN bit (OSCCON<1>) are reset. If firmware
modifies any of these bits or registers, the I/O will not
immediately go to the newly configured states. Once
the firmware clears the RELEASE bit (DSCON<0>),
the I/O pins are “released”. This causes the I/O pins to
take the states configured by their respective TRIS and
LAT bit values.
The sequence for exiting Deep Sleep mode is:
1. After a wake-up event, the device exits Deep
Sleep and performs a POR. The DSEN bit is
cleared automatically. Code execution resumes
at the Reset vector.
2. To determine if the device exited Deep Sleep,
read the Deep Sleep bit, DPSLP (RCON<10>).
This bit will be set if there was an exit from Deep
Sleep mode. If the bit is set, clear it.
3. Determine the wake-up source by reading the
DSWAKE register.
4. Determine if a DSBOR event occurred during
Deep Sleep mode by reading the DSBOR bit
(DSCON<1>).
This means that keeping the SOSC running after
waking up requires the SOSCEN bit to be set before
clearing RELEASE.
5. If application context data has been saved, read
it back from the DSGPR0 and DSGPR1 registers.
If the Deep Sleep BOR (DSBOR) is enabled, and a
DSBOR or a true POR event occurs during Deep
Sleep, the I/O pins will be immediately released, similar
to clearing the RELEASE bit. All previous state
information will be lost, including the general purpose
DSGPR0 and DSGPR1 contents.
6. Clear the RELEASE bit (DSCON<0>).
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If a MCLR Reset event occurs during Deep Sleep, the
DSGPRx, DSCON and DSWAKE registers will remain
valid, and the RELEASE bit will remain set. The state
of the SOSC will also be retained. The I/O pins,
however, will be reset to their MCLR Reset state. Since
RELEASE is still set, changes to the SOSCEN bit
(OSCCON<1>) cannot take effect until the RELEASE
bit is cleared.
10.4.6
CHECKING AND CLEARING THE
STATUS OF DEEP SLEEP
Upon entry into Deep Sleep mode, the status bit,
DPSLP (RCON<10>), becomes set and must be
cleared by the software.
On power-up, the software should read this status bit to
determine if the Reset was due to an exit from Deep
Sleep mode, and clear the bit if it is set. Of the four
possible combinations of DPSLP and POR bit states,
three cases can be considered:
In all other Deep Sleep wake-up cases, application
firmware must clear the RELEASE bit in order to
reconfigure the I/O pins.
• Both the DPSLP and POR bits are cleared. In this
case, the Reset was due to some event other
than a Deep Sleep mode exit.
10.4.5
DEEP SLEEP WDT
To enable the DSWDT in Deep Sleep mode, program
the Configuration bit, DSWDTEN (CW4<7>). The
device WDT need not be enabled for the DSWDT to
function. Entry into Deep Sleep modes automatically
reset the DSWDT.
• The DPSLP bit is clear, but the POR bit is set; this
is a normal POR.
• Both the DPSLP and POR bits are set. This
means that Deep Sleep mode was entered, the
device was powered down and Deep Sleep mode
was exited.
The DSWDT clock source is selected by the
DSWDTOSC Configuration bit (CW4<4>). The post-
scaler options are programmed by the DSWDPS<4:0>
Configuration bits (FDS<3:0>). The minimum time-out
period that can be achieved is 1 ms and the maximum is
25.7 days. For more details on the FDS Configuration
register and DSWDT configuration options, refer to 29.0
“Special Features”.
10.4.7
POWER-ON RESETS (PORs)
VDD voltage is monitored to produce PORs. Since
exiting from Deep Sleep mode functionally looks like a
POR, the technique described in Section 10.4.6
“Checking and Clearing the Status of Deep Sleep”
should be used to distinguish between Deep Sleep and
a true POR event. When a true POR occurs, the entire
device, including all Deep Sleep logic (Deep Sleep
registers, RTCC, DSWDT, etc.) is reset.
10.4.5.1
Switching Clocks in Deep Sleep
Mode
Both the RTCC and the DSWDT may run from either
SOSC or the LPRC clock source. This allows both the
RTCC and DSWDT to run without requiring both the
LPRC and SOSC to be enabled together, reducing
power consumption.
10.5 VBAT Mode
This mode represents the lowest power state that the
microcontroller can achieve and still resume operation.
VBAT mode is automatically triggered when the micro-
controller’s main power supply on VDD fails. When this
happens, the microcontroller’s on-chip power switch
connects to a back-up power source, such as a battery,
supplied to the VBAT pin. This maintains a few key
systems at an extremely low-power draw until VDD is
restored.
Running the RTCC from LPRC will result in a loss of
accuracy in the RTCC, of approximately 5 to 10%. If a
more accurate RTCC is required, it must be run from
the SOSC clock source. The RTCC clock source is
selected with the RTCOSC Configuration bit (FDS<5>).
Under certain circumstances, it is possible for the
DSWDT clock source to be off when entering Deep
Sleep mode. In this case, the clock source is turned on
automatically (if DSWDT is enabled), without the need
for software intervention. However, this can cause a
delay in the start of the DSWDT counters. In order to
avoid this delay when using SOSC as a clock source,
the application can activate SOSC prior to entering
Deep Sleep mode.
The power supplied on VBAT only runs two systems: the
RTCC and the Deep Sleep Semaphore registers
(DSGPR0 and DSGPR1). To maintain these systems
during a sudden loss of VDD, it is essential to connect a
power source, other than VDD or AVDD, to the VBAT pin.
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When the RTCC is enabled, it continues to operate with
With VBPOR set, the user should clear it, and the next
time, this bit will only set when VDD = 0and the VBAT
pin has gone below level (0.4V-0.6V).
the same clock source (SOSC or LPRC) that was
selected prior to entering VBAT mode. There is no pro-
vision to switch to a lower power clock source after the
mode switch.
10.5.3
I/O PINS DURING VBAT MODES
All I/O pins should be maintained at VSS level; no I/O
pins should be given VDD (refer to “Absolute Maximum
Ratings”) during VBAT mode. The only exceptions are
the SOSCI and SOSCO pins, which maintain their states
if the secondary oscillator is being used as the RTCC
clock source. It is the user’s responsibility to restore the
I/O pins to their proper states, using the TRIS and LAT
bits, once VDD has been restored.
Since the loss of VDD is usually an unforeseen event, it
is recommended that the contents of the Deep Sleep
Semaphore registers be loaded with the data to be
retained at an early point in code execution.
10.5.1
VBAT MODE WITH NO RTCC
By disabling RTCC operation during VBAT mode, power
consumption is reduced to the lowest of all
power-saving modes. In this mode, only the Deep
Sleep Semaphore registers are maintained.
10.5.4
SAVING CONTEXT DATA WITH THE
DSGPRn REGISTERS
10.5.2
WAKE-UP FROM VBAT MODES
As with Deep Sleep mode, all SFRs are reset to their
POR values after VDD has been restored. Only the
Deep Sleep Semaphore registers are preserved. Appli-
cations which require critical data to be saved should
save it in DSGPR0 and DSGPR1.
When VDD is restored to a device in VBAT mode, it auto-
matically wakes. Wake-up occurs with a POR, after
which the device starts executing code from the Reset
vector. All SFRs, except the Deep Sleep Semaphores
and RTCC registers are reset to their POR values. If
the RTCC was not configured to run during VBAT mode,
it will remain disabled and RTCC will not run. Wake-up
timing is similar to that for a normal POR.
Note:
If the VBAT mode is not used, the
recommendation is to connect the VBAT
pin to VDD.
When the VBAT mode is used (connected
to the battery), as well as when it is not
used, it is always recommended to
connect a 0.1 µF capacitor from the VBAT
pin to ground. The capacitor should be
located very close to the VBAT pin.
To differentiate a wake-up from VBAT mode from other
POR states, check the VBAT status bit (RCON2<0>). If
this bit is set while the device is starting to execute the
code from Reset vector, it indicates that there has been
an exit from VBAT mode. The application must clear the
VBAT bit to ensure that future VBAT wake-up events are
captured.
The BOR should be enabled for the reliable operation
of the VBAT.
If a POR occurs without a power source connected to
the VBAT pin, the VBPOR bit (RCON2<1>) is set. If this
bit is set on a POR, it indicates that a battery needs to
be connected to the VBAT pin.
In addition, if the VBAT power source falls below the
level needed for Deep Sleep Semaphore operation
while in VBAT mode (e.g., the battery has been
drained), the VBPOR bit will be set. VBPOR is also set
when the microcontroller is powered up the very first
time, even if power is supplied to VBAT.
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REGISTER 10-1: DSCON: DEEP SLEEP CONTROL REGISTER(1)
R/W-0
DSEN
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
bit 15
bit 8
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
r-0
r
R/W-0
DSBOR(2)
R/C-0, HS
RELEASE
bit 7
bit 0
Legend:
C = Clearable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
R = Readable bit
-n = Value at POR
HS = Hardware Settable bit
‘0’ = Bit is cleared
r = Reserved bit
x = Bit is unknown
bit 15
DSEN: Deep Sleep Enable bit
1= Enters Deep Sleep on execution of PWRSAV #0
0= Enters normal Sleep on execution of PWRSAV #0
bit 14-3
bit 2
Unimplemented: Read as ‘0’
Reserved: Maintain as ‘0’
bit 1
DSBOR: Deep Sleep BOR Event bit(2)
1= The DSBOR was active and a BOR event was detected during Deep Sleep
0= The DSBOR was not active or was active but did not detect a BOR event during Deep Sleep
bit 0
RELEASE: I/O Pin State Release bit
1= Upon waking from Deep Sleep, I/O pins maintain their states previous to Deep Sleep entry
0= Release I/O pins from their state previous to Deep Sleep entry, and allow their respective TRIS and
LAT bits to control their states
Note 1: All register bits are reset only in the case of a POR event outside of Deep Sleep mode.
2: Unlike all other events, a Deep Sleep BOR event will NOT cause a wake-up from Deep Sleep; this
re-arms POR.
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REGISTER 10-2: DSWAKE: DEEP SLEEP WAKE-UP SOURCE REGISTER(1)
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
R/W-0, HS
DSINT0
bit 15
bit 8
R/W-0, HS
DSFLT
U-0
—
U-0
—
R/W-0, HS
DSWDT
R/W-0, HS
DSRTCC
R/W-0, HS
DSMCLR
U-0
—
U-0
—
bit 7
bit 0
Legend:
HS = Hardware Settable bit
W = Writable bit
R = Readable bit
-n = Value at POR
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
‘1’ = Bit is set
bit 15-9
bit 8
Unimplemented: Read as ‘0’
DSINT0: Interrupt-on-Change bit
1= Interrupt-on-change was asserted during Deep Sleep
0= Interrupt-on-change was not asserted during Deep Sleep
bit 7
DSFLT: Deep Sleep Fault Detected bit
1= A Fault occurred during Deep Sleep and some Deep Sleep configuration settings may have been
corrupted
0= No Fault was detected during Deep Sleep
bit 6-5
bit 4
Unimplemented: Read as ‘0’
DSWDT: Deep Sleep Watchdog Timer Time-out bit
1= The Deep Sleep Watchdog Timer timed out during Deep Sleep
0= The Deep Sleep Watchdog Timer did not time out during Deep Sleep
bit 3
DSRTCC: Real-Time Clock and Calendar Alarm bit
1= The Real-Time Clock and Calendar triggered an alarm during Deep Sleep
0= The Real-Time Clock and Calendar did not trigger an alarm during Deep Sleep
bit 2
DSMCLR: MCLR Event bit
1= The MCLR pin was active and was asserted during Deep Sleep
0= The MCLR pin was not active, or was active, but not asserted during Deep Sleep
bit 1-0
Unimplemented: Read as ‘0’
Note 1: All register bits are cleared when the DSEN (DSCON<15>) bit is set.
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REGISTER 10-3: RCON2: RESET AND SYSTEM CONTROL REGISTER 2
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
bit 15
bit 8
U-0
—
U-0
—
U-0
—
r-0
r
R/CO-1
R/CO-1
R/CO-1
R/CO-0
VBAT(1)
VDDBOR(1) VDDPOR(1,2) VBPOR(1,3)
bit 7
bit 0
Legend:
CO = Clearable Only bit
W = Writable bit
r = Reserved bit
R = Readable bit
-n = Value at POR
U = Unimplemented bit, read as ‘0’
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-5
bit 4
Unimplemented: Read as ‘0’
Reserved: Maintain as ‘0’
bit 3
VDDBOR: VDD Brown-out Reset Flag bit(1)
1= A VDD Brown-out Reset has occurred (set by hardware)
0= A VDD Brown-out Reset has not occurred
bit 2
bit 1
VDDPOR: VDD Power-On Reset Flag bit(1,2)
1= A VDD Power-up Reset has occurred (set by hardware)
0= A VDD Power-up Reset has not occurred
VBPOR: VBPOR Flag bit(1,3)
1= A VBAT POR has occurred (no battery connected to the VBAT pin, or VBAT power below Deep Sleep
Semaphore retention level, set by hardware)
0= A VBAT POR has not occurred
bit 0
VBAT: VBAT Flag bit(1)
1= A POR exit has occurred while power applied to the VBAT pin (set by hardware)
0= A POR exit from VBAT has not occurred
Note 1: This bit is set in hardware only; it can only be cleared in software.
2: Indicates a VDD POR. Setting the POR bit (RCON<0>) indicates a VCORE POR.
3: This bit is set when the device is originally powered up, even if power is present on VBAT. It is recom-
mended that the user clear this flag, and the next time, this bit will only set when the VBAT voltage goes
below 0.4-0.6V with VDD = 0.
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10.6 Clock Frequency and Clock
Switching
10.8 Selective Peripheral Module
Control
In Run and Idle modes, all PIC24FJ devices allow for a
wide range of clock frequencies to be selected under
application control. If the system clock configuration is
not locked, users can choose low-power or
high-precision oscillators by simply changing the NOSC
bits. The process of changing a system clock during
operation, as well as limitations to the process, are
discussed in more detail in 9.0 “Oscillator Configura-
tion”.
Idle and Doze modes allow users to substantially
reduce power consumption by slowing or stopping the
CPU clock. Even so, peripheral modules still remain
clocked, and thus, consume power. There may be
cases where the application needs what these modes
do not provide: the allocation of power resources to
CPU processing with minimal power consumption from
the peripherals.
PIC24F devices address this requirement by allowing
peripheral modules to be selectively disabled, reducing
or eliminating their power consumption. This can be
done with two control bits:
10.7 Doze Mode
Generally, changing clock speed and invoking one of
the power-saving modes are the preferred strategies
for reducing power consumption. There may be
circumstances, however, where this is not practical. For
example, it may be necessary for an application to
maintain uninterrupted synchronous communication,
even while it is doing nothing else. Reducing system
clock speed may introduce communication errors,
• The Peripheral Enable bit, generically named,
“XXXEN”, located in the module’s main control
SFR.
• The Peripheral Module Disable (PMD) bit,
generically named, “XXXMD”, located in one of
the PMD Control registers (XXXMD bits are in
PMD1, PMD2, PMD3, PMD4, PMD6, PMD7
registers).
while using
a
power-saving mode may stop
communications completely.
Both bits have similar functions in enabling or disabling
its associated module. Setting the PMD bit for a module
disables all clock sources to that module, reducing its
power consumption to an absolute minimum. In this
state, the control and status registers associated with
the peripheral will also be disabled, so writes to those
registers will have no effect and read values will be
invalid. Many peripheral modules have a corresponding
PMD bit.
Doze mode is a simple and effective alternative method
to reduce power consumption while the device is still
executing code. In this mode, the system clock
continues to operate from the same source and at the
same speed. Peripheral modules continue to be
clocked at the same speed while the CPU clock speed
is reduced. Synchronization between the two clock
domains is maintained, allowing the peripherals to
access the SFRs while the CPU executes code at a
slower rate.
In contrast, disabling a module by clearing its XXXEN
bit disables its functionality, but leaves its registers
available to be read and written to. Power consumption
is reduced, but not by as much as the PMD bits are
used. Most peripheral modules have an enable bit;
exceptions include capture, compare and RTCC.
Doze mode is enabled by setting the DOZEN bit
(CLKDIV<11>). The ratio between peripheral and core
clock speed is determined by the DOZE<2:0> bits
(CLKDIV<14:12>). There are eight possible
configurations, from 1:1 to 1:128, with 1:1 being the
default.
To achieve more selective power savings, peripheral
modules can also be selectively disabled when the
device enters Idle mode. This is done through the control
bit of the generic name format, “XXXIDL”. By default, all
modules that can operate during Idle mode will do so.
Using the disable on Idle feature disables the module
while in Idle mode, allowing further reduction of power
consumption during Idle mode, enhancing power
savings for extremely critical power applications.
It is also possible to use Doze mode to selectively reduce
power consumption in event driven applications. This
allows clock-sensitive functions, such as synchronous
communications, to continue without interruption while
the CPU Idles, waiting for something to invoke an
interrupt routine. Enabling the automatic return to
full-speed CPU operation on interrupts is enabled by set-
ting the ROI bit (CLKDIV<15>). By default, interrupt
events have no effect on Doze mode operation.
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NOTES:
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When a peripheral is enabled and the peripheral is
actively driving an associated pin, the use of the pin as
11.0 I/O PORTS
Note:
This data sheet summarizes the features of
this group of PIC24F devices. It is not
a general purpose output pin is disabled. The I/O pin
may be read, but the output driver for the parallel port
bit will be disabled. If a peripheral is enabled, but the
peripheral is not actively driving a pin, that pin may be
driven by a port.
intended to be a comprehensive reference
source. For more information, refer to the
“PIC24F Family Reference Manual”,
Section 12. “I/O Ports with Peripheral
Pin Select (PPS)” (DS39711). The infor-
mation in this data sheet supersedes the
information in the FRM.
All port pins have three registers directly associated
with their operation as digital I/O and one register asso-
ciated with their operation as analog input. The Data
Direction register (TRISx) determines whether the pin
is an input or an output. If the data direction bit is a ‘1’,
then the pin is an input. All port pins are defined as
inputs after a Reset. Reads from the Output Latch reg-
ister (LATx), read the latch; writes to the latch, write the
latch. Reads from the port (PORTx), read the port pins;
writes to the port pins, write the latch.
All of the device pins (except VDD, VSS, MCLR and
OSCI/CLKI) are shared between the peripherals and
the parallel I/O ports. All I/O input ports feature Schmitt
Trigger (ST) inputs for improved noise immunity.
11.1 Parallel I/O (PIO) Ports
Any bit and its associated data and control registers
that are not valid for a particular device will be
disabled. That means the corresponding LATx and
TRISx registers, and the port pin will read as zeros.
A parallel I/O port that shares a pin with a peripheral is,
in general, subservient to the peripheral. The periph-
eral’s output buffer data and control signals are
provided to a pair of multiplexers. The multiplexers
select whether the peripheral or the associated port
has ownership of the output data and control signals of
the I/O pin. The logic also prevents “loop through”, in
which a port’s digital output can drive the input of a
peripheral that shares the same pin. Figure 11-1 shows
how ports are shared with other peripherals and the
associated I/O pin to which they are connected.
When a pin is shared with another peripheral or func-
tion that is defined as an input only, it is regarded as a
dedicated port because there is no other competing
source of inputs. RC13 and RC14 can be input ports
only; they cannot be configured as outputs.
FIGURE 11-1:
BLOCK DIAGRAM OF A TYPICAL SHARED PORT STRUCTURE
Peripheral Module
Output Multiplexers
Peripheral Input Data
Peripheral Module Enable
Peripheral Output Enable
Peripheral Output Data
I/O
1
0
Output Enable
Output Data
1
0
PIO Module
Read TRIS
Data Bus
WR TRIS
D
Q
I/O Pin
CK
TRIS Latch
D
Q
WR LAT +
WR PORT
CK
Data Latch
Read LAT
Input Data
Read PORT
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11.1.1
I/O PORT WRITE/READ TIMING
11.2 Configuring Analog Port Pins
(ANSx)
One instruction cycle is required between a port direction
change or port write operation and a read operation of
the same port. Typically, this instruction would be a NOP.
The ANSx and TRISx registers control the operation of
the pins with analog function. Each port pin with analog
function is associated with one of the ANS bits (see
Register 11-1 through Register 11-6), which decides if
the pin function should be analog or digital. Refer to
Table 11-1 for detailed behavior of the pin for different
ANSx and TRISx bit settings.
11.1.2
OPEN-DRAIN CONFIGURATION
In addition to the PORT, LAT and TRIS registers for data
control, each port pin can also be individually configured
for either a digital or open-drain output. This is controlled
by the Open-Drain Control register, ODCx, associated
with each port. Setting any of the bits configures the
corresponding pin to act as an open-drain output.
When reading the PORT register, all pins configured as
analog input channels will read as cleared (a low level).
The open-drain feature allows the generation of
outputs higher than VDD (e.g., 5V) on any desired
digital only pins by using external pull-up resistors. The
maximum open-drain voltage allowed is the same as
the maximum VIH specification.
11.2.1
ANALOG INPUT PINS AND
VOLTAGE CONSIDERATIONS
The voltage tolerance of pins used as device inputs is
dependent on the pin’s input function. Most input pins are
able to handle DC voltages of up to 5.5V, a level typical
for digital logic circuits. However, several pins can only
tolerate voltages up to VDD. Voltage excursions beyond
VDD on these pins should always be avoided.
Table 11-2 summarizes the different voltage tolerances.
Refer to Section 32.0 “Electrical Characteristics” for
more details.
TABLE 11-1: CONFIGURING ANALOG/DIGITAL FUNCTION OF AN I/O PIN
Pin Function
ANSx Setting
TRISx Setting
Comments
Analog Input
Analog Output
Digital Input
1
1
0
1
1
1
It is recommended to keep ANSx = 1.
It is recommended to keep ANSx = 1.
Firmware must wait at least one instruction cycle
after configuring a pin as a digital input before a valid
input value can be read.
Digital Output
0
0
Make sure to disable the analog output function on
the pin if any is present.
TABLE 11-2: INPUT VOLTAGE LEVELS FOR PORT OR PIN TOLERATED DESCRIPTION INPUT
Port or Pin
Tolerated Input
Description
PORTA<15:14, 7:0>(1)
PORTB<15:7, 5:2>
PORTC<3:1>(1)
PORTD<15:8, 5:0>(1)
PORTE<9:8, 4:0>(1)
PORTF<13:12, 8:0>(1)
PORTG<15:12, 9, 6:0>(1)
PORTA<10:9>(1)
Tolerates input levels above VDD; useful
for most standard logic.
5.5V
PORTB<6, 1:0>
PORTC<15:12, 4>(1)
VDD
Only VDD input levels are tolerated.
PORTD<7:6>
PORTE<7:5>(1)
PORTG<8:7>
Note 1: Not all of these pins are implemented in 64-pin or 80-pin devices. Refer to Section 1.0 “Device Overview”
for a complete description of port pin implementation.
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REGISTER 11-1: ANSA: PORTA ANALOG FUNCTION SELECTION REGISTER
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
bit 15
bit 8
bit 0
R/W-1
ANSA7(1)
R/W-1
ANSA6(1)
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
bit 7
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
-n = Value at POR
bit 15-8
bit 7-6
Unimplemented: Read as ‘0’
ANSA<7:6>: Analog Function Selection bits(1)
1= Pin is configured in Analog mode; I/O port read is disabled
0= Pin is configured in Digital mode; I/O port read is enabled
bit 5-0
Unimplemented: Read as ‘0’
Note 1: These bits are not available in 64-pin and 80-pin devices.
REGISTER 11-2: ANSB: PORTB ANALOG FUNCTION SELECTION REGISTER
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
ANSB15
ANSB14
ANSB13
ANSB12
ANSB11
ANSB10
ANSB9
ANSB8
bit 15
bit 8
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
ANSB7
ANSB6
ANSB5
ANSB4
ANSB3
ANSB2
ANSB1
ANSB0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
-n = Value at POR
bit 15-0
ANSB<15:0>: Analog Function Selection bits
1= Pin is configured in Analog mode; I/O port read is disabled
0= Pin is configured in Digital mode; I/O port read is enabled
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REGISTER 11-3: ANSC: PORTC ANALOG FUNCTION SELECTION REGISTER
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
bit 15
bit 8
bit 0
U-0
—
U-0
—
U-0
—
R/W-1
ANSC4(1)
U-0
—
U-0
—
U-0
—
U-0
—
bit 7
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-5
bit 4
Unimplemented: Read as ‘0’
ANSC4: Analog Function Selection bit(1)
1= Pin is configured in Analog mode; I/O port read is disabled
0= Pin is configured in Digital mode; I/O port read is enabled
bit 3-0
Unimplemented: Read as ‘0’
Note 1: This bit is not available in 64-pin and 80-pin devices.
REGISTER 11-4: ANSD: PORTD ANALOG FUNCTION SELECTION REGISTER
U-0
—
U-0
—
U-0
—
U-0
—
R/W-1
R/W-1
U-0
—
U-0
—
ANSD11
ANSD10
bit 15
bit 8
bit 0
R/W-1
R/W-1
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
ANSD7
ANSD6
bit 7
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
-n = Value at POR
bit 15-12
bit 11
Unimplemented: Read as ‘0’
ANSD<11:10>: Analog Function Selection bit
1= Pin is configured in Analog mode; I/O port read is disabled
0= Pin is configured in Digital mode; I/O port read is enabled
bit 9-8
bit 7-6
Unimplemented: Read as ‘0’
ANSD<7:6>: Analog Function Selection bit
1= Pin is configured in Analog mode; I/O port read is disabled
0= Pin is configured in Digital mode; I/O port read is enabled
bit 5-0
Unimplemented: Read as ‘0’
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REGISTER 11-5: ANSE: PORTE ANALOG FUNCTION SELECTION REGISTER(1)
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
R/W-1
ANSE9(2)
U-0
—
bit 15
bit 8
bit 0
R/W-1
R/W-1
R/W-1
R/W-1
U-0
—
U-0
—
U-0
—
U-0
—
ANSE7
ANSE6
ANSE5
ANSE4
bit 7
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
-n = Value at POR
bit 15-10
bit 9
Unimplemented: Read as ‘0’
ANSE9: Analog Function Selection bits(2)
1= Pin is configured in Analog mode; I/O port read is disabled
0= Pin is configured in Digital mode; I/O port read is enabled
bit 8
Unimplemented: Read as ‘0’
bit 7-4
ANSE<7:4>: Analog Function Selection bits(1)
1= Pin is configured in Analog mode; I/O port read is disabled
0= Pin is configured in Digital mode; I/O port read is enabled
bit 3-0
Unimplemented: Read as ‘0’
Note 1: This register is not available in 64-pin and 80-pin devices.
2: This bit is unimplemented on 64-pin devices. In 80-pin devices, this bit needs to be cleared to get digital
functionality on RE9.
REGISTER 11-6: ANSG: PORTG ANALOG FUNCTION SELECTION REGISTER
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
R/W-1
R/W-1
ANSG9
ANSG8
bit 15
bit 8
R/W-1
R/W-1
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
ANSG7
ANSG6
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
-n = Value at POR
bit 15-10
bit 9-6
Unimplemented: Read as ‘0’
ANSG<9:6>: Analog Function Selection bits
1= Pin is configured in Analog mode; I/O port read is disabled
0= Pin is configured in Digital mode; I/O port read is enabled
bit 5-0
Unimplemented: Read as ‘0’
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Each CN pin has both a weak pull-up and a weak
11.3 Input Change Notification
pull-down connected to it. The pull-ups act as a current
source that is connected to the pin, while the
pull-downs act as a current sink that is connected to the
pin. These eliminate the need for external resistors
when push button or keypad devices are connected.
The pull-ups and pull-downs are separately enabled
using the CNPU1 through CNPU6 registers (for
pull-ups) and the CNPD1 through CNPD6 registers (for
pull-downs). Each CN pin has individual control bits for
its pull-up and pull-down. Setting a control bit enables
the weak pull-up or pull-down for the corresponding
pin.
The input change notification function of the I/O ports
allows the PIC24FJ128GA310 family of devices to gen-
erate interrupt requests to the processor in response to
a Change-of-State (COS) on selected input pins. This
feature is capable of detecting input Change-of-States,
even in Sleep mode when the clocks are disabled.
Depending on the device pin count, there are up to
82 external inputs that may be selected (enabled) for
generating an interrupt request on a Change-of-State.
Registers, CNEN1 through CNEN6, contain the inter-
rupt enable control bits for each of the CN input pins.
Setting any of these bits enables a CN interrupt for the
corresponding pins.
When the internal pull-up is selected, the pin pulls up to
VDD – 1.1V (typical). When the internal pull-down is
selected, the pin pulls down to VSS.
Note:
Pull-ups on change notification pins
should always be disabled whenever the
port pin is configured as a digital output.
EXAMPLE 11-1:
PORT WRITE/READ IN ASSEMBLY
MOV
MOV
NOP
0xFF00, W0
W0, TRISB
; Configure PORTB<15:8> as inputs
; and PORTB<7:0> as outputs
; Delay 1 cycle
BTSS PORTB, #13
; Next Instruction
EXAMPLE 11-2:
PORT WRITE/READ IN ‘C’
TRISB = 0xFF00;
Nop();
// Configure PORTB<15:8> as inputs and PORTB<7:0> as outputs
// Delay 1 cycle
If (PORTBbits.RB13){ };
// Next Instruction
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PPS is not available for these peripherals:
• I2C™ (input and output)
11.4 Peripheral Pin Select (PPS)
A major challenge in general purpose devices is provid-
ing the largest possible set of peripheral features while
minimizing the conflict of features on I/O pins. In an
application that needs to use more than one peripheral
multiplexed on a single pin, inconvenient work arounds
in application code, or a complete redesign, may be the
only option.
• Change notification inputs
• RTCC alarm output(s)
• EPMP signals (input and output)
• LCD signals
• Analog inputs
• INT0
The Peripheral Pin Select (PPS) feature provides an
alternative to these choices by enabling the user’s
peripheral set selection and its placement on a wide
range of I/O pins. By increasing the pinout options
available on a particular device, users can better tailor
the microcontroller to their entire application, rather
than trimming the application to fit the device.
A key difference between pin select and non-pin select
peripherals is that pin select peripherals are not asso-
ciated with a default I/O pin. The peripheral must
always be assigned to a specific I/O pin before it can be
used. In contrast, non-pin select peripherals are always
available on a default pin, assuming that the peripheral
is active and not conflicting with another peripheral.
The Peripheral Pin Select feature operates over a fixed
subset of digital I/O pins. Users may independently
map the input and/or output of any one of many digital
peripherals to any one of these I/O pins. PPS is per-
formed in software and generally does not require the
device to be reprogrammed. Hardware safeguards are
included that prevent accidental or spurious changes to
the peripheral mapping once it has been established.
11.4.2.1
Peripheral Pin Select Function
Priority
Pin-selectable peripheral outputs (e.g., OC, UART
transmit) will take priority over general purpose digital
functions on a pin, such as EPMP and port I/O. Special-
ized digital outputs (e.g., USB on USB-enabled
devices) will take priority over PPS outputs on the same
pin. The pin diagrams list peripheral outputs in the
order of priority. Refer to them for priority concerns on
a particular pin.
11.4.1
AVAILABLE PINS
The PPS feature is used with a range of up to 44 pins,
depending on the particular device and its pin count.
Pins that support the Peripheral Pin Select feature
include the designation, “RPn” or “RPIn”, in their full pin
designation, where “n” is the remappable pin number.
“RP” is used to designate pins that support both remap-
pable input and output functions, while “RPI” indicates
pins that support remappable input functions only.
Unlike PIC24F devices with fixed peripherals,
pin-selectable peripheral inputs will never take owner-
ship of a pin. The pin’s output buffer will be controlled
by the TRISx setting or by a fixed peripheral on the pin.
If the pin is configured in Digital mode then the PPS
input will operate correctly. If an analog function is
enabled on the pin, the PPS input will be disabled.
PIC24FJ128GA310 family devices support a larger
number of remappable input only pins than remappable
input/output pins. In this device family, there are up to
32 remappable input/output pins, depending on the pin
count of the particular device selected. These pins are
numbered, RP0 through RP31. Remappable input only
pins are numbered above this range, from RPI32 to
RPI43 (or the upper limit for that particular device).
11.4.3
CONTROLLING PERIPHERAL PIN
SELECT
PPS features are controlled through two sets of Special
Function Registers (SFRs): one to map peripheral
inputs and one to map outputs. Because they are
separately controlled, a particular peripheral’s input
and output (if the peripheral has both) can be placed on
any selectable function pin without constraint.
See Table 1-4 for a summary of pinout options in each
package offering.
The association of a peripheral to a peripheral-selectable
pin is handled in two different ways, depending on if an
input or an output is being mapped.
11.4.2
AVAILABLE PERIPHERALS
The peripherals managed by the PPS are all digital
only peripherals. These include general serial commu-
nications (UART and SPI), general purpose timer clock
inputs, timer related peripherals (input capture and out-
put compare) and external interrupt inputs. Also
included are the outputs of the comparator module,
since these are discrete digital signals.
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Each register contains two sets of 6-bit fields, with each
set associated with one of the pin-selectable peripher-
als. Programming a given peripheral’s bit field, with an
appropriate 6-bit value, maps the RPn/RPIn pin with
that value to that peripheral. For any given device, the
valid range of values for any of the bit fields corre-
sponds to the maximum number of Peripheral Pin
Selections supported by the device.
11.4.3.1
Input Mapping
The inputs of the Peripheral Pin Select options are
mapped on the basis of the peripheral; that is, a control
register associated with a peripheral dictates the pin it
will be mapped to. The RPINRx registers are used to
configure peripheral input mapping (see Register 11-7
through Register 11-26).
TABLE 11-3: SELECTABLE INPUT SOURCES (MAPS INPUT TO FUNCTION)(1)
Function Mapping
Bits
Input Name
Function Name
Register
DSM Modulation Input
DSM Carrier 1 Input
DSM Carrier 2 Input
External Interrupt 1
External Interrupt 2
External Interrupt 3
External Interrupt 4
Input Capture 1
MDMIN
MDCIN1
MDCIN2
INT1
RPINR30
RPINR31
RPINR31
RPINR0
RPINR1
RPINR1
RPINR2
RPINR7
RPINR7
RPINR8
RPINR8
RPINR9
RPINR9
RPINR10
RPINR11
RPINR11
RPINR20
RPINR20
RPINR21
RPINR22
RPINR22
RPINR23
RPINR23
RPINR3
RPINR3
RPINR4
RPINR4
RPINR18
RPINR18
RPINR19
RPINR19
RPINR21
RPINR17
RPINR27
RPINR27
MDMIR<5:0>
MDC1R<5:0>
MDC2R<5:0>
INT1R<5:0>
INT2R<5:0>
INT3R<5:0>
INT4R<5:0>
IC1R<5:0>
INT2
INT3
INT4
IC1
Input Capture 2
IC2
IC2R<5:0>
Input Capture 3
IC3
IC3R<5:0>
Input Capture 4
IC4
IC4R<5:0>
Input Capture 5
IC5
IC5R<5:0>
Input Capture 6
IC6
IC6R<5:0>
Input Capture 7
IC7
IC7R<5:0>
Output Compare Fault A
Output Compare Fault B
SPI1 Clock Input
OCFA
OCFB
SCK1IN
SDI1
OCFAR<5:0>
OCFBR<5:0>
SCK1R<5:0>
SDI1R<5:0>
SS1R<5:0>
SCK2R<5:0>
SDI2R<5:0>
SS2R<5:0>
T1CKR<5:0>
T2CKR<5:0>
T3CKR<5:0>
T4CKR<5:0>
T5CKR<5:0>
U1CTSR<5:0>
U1RXR<5:0>
U2CTSR<5:0>
U2RXR<5:0>
U3CTSR<5:0>
U3RXR<5:0>
U4CTSR<5:0>
U4RXR<5:0>
SPI1 Data Input
SPI1 Slave Select Input
SPI2 Clock Input
SS1IN
SCK2IN
SDI2
SPI2 Data Input
SPI2 Slave Select Input
Timer1 External Clock
Timer2 External Clock
Timer3 External Clock
Timer4 External Clock
Timer5 External Clock
UART1 Clear To Send
UART1 Receive
SS2IN
T1CK
T2CK
T3CK
T4CK
T5CK
U1CTS
U1RX
U2CTS
U2RX
U3CTS
U3RX
U4CTS
U4RX
UART2 Clear To Send
UART2 Receive
UART3 Clear To Send
UART3 Receive
UART4 Clear To Send
UART4 Receive
Note 1: Unless otherwise noted, all inputs use the Schmitt Trigger (ST) input buffers.
DS39996F-page 174
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corresponds to one of the peripherals and that
peripheral’s output is mapped to the pin (see
Table 11-4).
11.4.3.2
Output Mapping
In contrast to inputs, the outputs of the Peripheral Pin
Select options are mapped on the basis of the pin. In
this case, a control register associated with a particular
pin dictates the peripheral output to be mapped. The
RPORx registers are used to control output mapping.
Each register contains two 6-bit fields, with each field
being associated with one RPn pin (see Register 11-27
through Register 11-42). The value of the bit field
Because of the mapping technique, the list of peripher-
als for output mapping also includes a null value of
‘000000’. This permits any given pin to remain discon-
nected from the output of any of the pin-selectable
peripherals.
TABLE 11-4: SELECTABLE OUTPUT SOURCES (MAPS FUNCTION TO OUTPUT)
Output Function Number(1)
Function
Output Name
0
1
NULL(2)
C1OUT
C2OUT
U1TX
Null
Comparator 1 Output
Comparator 2 Output
UART1 Transmit
2
3
4
U1RTS(3)
UART1 Request To Send
UART2 Transmit
5
U2TX
6
U2RTS(3)
SDO1
UART2 Request To Send
SPI1 Data Output
7
8
SCK1OUT
SS1OUT
SDO2
SPI1 Clock Output
SPI1 Slave Select Output
SPI2 Data Output
9
10
11
12
18
19
20
21
22
23
24
28
29
30
31
36
37
38-63
SCK2OUT
SS2OUT
OC1
SPI2 Clock Output
SPI2 Slave Select Output
Output Compare 1
Output Compare 2
Output Compare 3
Output Compare 4
Output Compare 5
Output Compare 6
Output Compare 7
UART3 Transmit
OC2
OC3
OC4
OC5
OC6
OC7
U3TX
U3RTS(3)
UART3 Request To Send
UART4 Transmit
U4TX
U4RTS(3)
C3OUT
MDOUT
(unused)
UART4 Request To Send
Comparator 3 Output
DSM Modulator Output
NC
Note 1: Setting the RPORx register with the listed value assigns that output function to the associated RPn pin.
2: The NULL function is assigned to all RPn outputs at device Reset and disables the RPn output function.
3: IrDA® BCLK functionality uses this output.
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11.4.3.3
Mapping Limitations
11.4.4.1
Control Register Lock
The control schema of the Peripheral Pin Select is
extremely flexible. Other than systematic blocks that
prevent signal contention, caused by two physical pins
being configured as the same functional input or two
functional outputs configured as the same pin, there
are no hardware enforced lock outs. The flexibility
extends to the point of allowing a single input to drive
multiple peripherals or a single functional output to
drive multiple output pins.
Under normal operation, writes to the RPINRx and
RPORx registers are not allowed. Attempted writes will
appear to execute normally, but the contents of the
registers will remain unchanged. To change these reg-
isters, they must be unlocked in hardware. The register
lock is controlled by the IOLOCK bit (OSCCON<6>).
Setting IOLOCK prevents writes to the control
registers; clearing IOLOCK allows writes.
To set or clear IOLOCK, a specific command sequence
must be executed:
11.4.3.4
Mapping Exceptions for
1. Write 46h to OSCCON<7:0>.
PIC24FJ128GA310 Family Devices
2. Write 57h to OSCCON<7:0>.
Although the PPS registers theoretically allow for up to
64 remappable I/O pins, not all of these are imple-
mented in all devices. For PIC24FJ128GA310 family
devices, the maximum number of remappable pins
available is 44, which includes 12 input only pins. In
addition, some pins in the RP and RPI sequences are
unimplemented in lower pin count devices. The
differences in available remappable pins are
summarized in Table 11-5.
3. Clear (or set) IOLOCK as a single operation.
Unlike the similar sequence with the oscillator’s LOCK
bit, IOLOCK remains in one state until changed. This
allows all of the Peripheral Pin Selects to be configured
with a single unlock sequence, followed by an update
to all control registers, then locked with a second lock
sequence.
11.4.4.2
Continuous State Monitoring
When developing applications that use remappable
pins, users should also keep these things in mind:
In addition to being protected from direct writes, the
contents of the RPINRx and RPORx registers are
constantly monitored in hardware by shadow registers.
If an unexpected change in any of the registers occurs
(such as cell disturbances caused by ESD or other
external events), a Configuration Mismatch Reset will
be triggered.
• For the RPINRx registers, bit combinations corre-
sponding to an unimplemented pin for a particular
device are treated as invalid; the corresponding
module will not have an input mapped to it. For all
PIC24FJ128GA310 family devices, this includes
all values greater than 43 (‘101011’).
• For RPORx registers, the bit fields corresponding
to an unimplemented pin will also be
unimplemented. Writing to these fields will have
no effect.
11.4.4.3
Configuration Bit Pin Select Lock
As an additional level of safety, the device can be con-
figured to prevent more than one write session to the
RPINRx and RPORx registers. The IOL1WAY
(CW2<4>) Configuration bit blocks the IOLOCK bit
from being cleared after it has been set once. If
IOLOCK remains set, the register unlock procedure will
not execute and the Peripheral Pin Select Control reg-
isters cannot be written to. The only way to clear the bit
and re-enable peripheral remapping is to perform a
device Reset.
11.4.4
CONTROLLING CONFIGURATION
CHANGES
Because peripheral remapping can be changed during
run time, some restrictions on peripheral remapping
are needed to prevent accidental configuration
changes. PIC24F devices include three features to
prevent alterations to the peripheral map:
In the default (unprogrammed) state, IOL1WAY is set,
restricting users to one write session. Programming
IOL1WAY allows users unlimited access (with the
proper use of the unlock sequence) to the Peripheral
Pin Select registers.
• Control register lock sequence
• Continuous state monitoring
• Configuration bit remapping lock
TABLE 11-5: REMAPPABLE PIN EXCEPTIONS FOR PIC24FJ128GA310 FAMILY DEVICES
RP Pins (I/O)
Unimplemented
RPI Pins
Unimplemented
Device
Total
Total
PIC24FJXXXGA306
PIC24FJXXXGA308
PIC24FJXXXGA310
29
31
32
RP5, RP15, RP31
1
9
RPI32-36, RPI38-43
RPI32, RPI39, RPI41
—
RP15
—
12
DS39996F-page 176
2010-2011 Microchip Technology Inc.
PIC24FJ128GA310 FAMILY
Along these lines, configuring a remappable pin for a
specific peripheral does not automatically turn that
feature on. The peripheral must be specifically config-
ured for operation, and enabled as if it were tied to a
fixed pin. Where this happens in the application code
(immediately following device Reset and peripheral con-
figuration, or inside the main application routine)
depends on the peripheral and its use in the application.
11.4.5
CONSIDERATIONS FOR
PERIPHERAL PIN SELECTION
The ability to control Peripheral Pin Selection intro-
duces several considerations into application design
that could be overlooked. This is particularly true for
several common peripherals that are available only as
remappable peripherals.
The main consideration is that the Peripheral Pin
Selects are not available on default pins in the device’s
default (Reset) state. Since all RPINRx registers reset
to ‘111111’ and all RPORx registers reset to ‘000000’,
all Peripheral Pin Select inputs are tied to VSS and all
Peripheral Pin Select outputs are disconnected.
A final consideration is that Peripheral Pin Select func-
tions neither override analog inputs nor reconfigure
pins with analog functions for digital I/O. If a pin is
configured as an analog input on device Reset, it must
be explicitly reconfigured as digital I/O when used with
a Peripheral Pin Select.
Note:
In tying Peripheral Pin Select inputs to
RP63, RP63 need not exist on a device for
the registers to be reset to it.
Example 11-3 shows a configuration for bidirectional
communication with flow control using UART1. The
following input and output functions are used:
This situation requires the user to initialize the device
with the proper peripheral configuration before any
other application code is executed. Since the IOLOCK
bit resets in the unlocked state, it is not necessary to
execute the unlock sequence after the device has
come out of Reset. For application safety, however, it is
best to set IOLOCK and lock the configuration after
writing to the control registers.
• Input Functions: U1RX, U1CTS
• Output Functions: U1TX, U1RTS
EXAMPLE 11-3:
CONFIGURING UART1
INPUT AND OUTPUT
FUNCTIONS
// Unlock Registers
asm volatile( "MOV
#OSCCON,
#0x46,
#0x57,
w1
w2
w3
[w1] \n"
[w1] \n"
\n"
\n"
\n"
Because the unlock sequence is timing-critical, it must
be executed as an assembly language routine in the
same manner as changes to the oscillator configura-
tion. If the bulk of the application is written in ‘C’, or
another high-level language, the unlock sequence
should be performed by writing in-line assembly.
"MOV
"MOV
"MOV.b w2,
"MOV.b w3,
"BCLR OSCCON,#6") ;
// or use C30 built-in macro:
Choosing the configuration requires the review of all
Peripheral Pin Selects and their pin assignments,
especially those that will not be used in the application.
In all cases, unused pin-selectable peripherals should
be disabled completely. Unused peripherals should
have their inputs assigned to an unused RPn/RPIn pin
function. I/O pins with unused RPn functions should be
configured with the null peripheral output.
// __builtin_write_OSCCONL(OSCCON & 0xbf);
// Configure Input Functions (Table 11-2))
// Assign U1RX To Pin RP0
RPINR18bits.U1RXR = 0;
// Assign U1CTS To Pin RP1
RPINR18bits.U1CTSR = 1;
The assignment of a peripheral to a particular pin does
not automatically perform any other configuration of the
pin’s I/O circuitry. In theory, this means adding a
pin-selectable output to a pin may mean inadvertently
driving an existing peripheral input when the output is
driven. Users must be familiar with the behavior of
other fixed peripherals that share a remappable pin and
know when to enable or disable them. To be safe, fixed
digital peripherals that share the same pin should be
disabled when not in use.
// Configure Output Functions (Table 11-4)
// Assign U1TX To Pin RP2
RPOR1bits.RP2R = 3;
// Assign U1RTS To Pin RP3
RPOR1bits.RP3R = 4;
// Lock Registers
asm volatile
("MOV
"MOV
"MOV
"MOV.b w2,
"MOV.b w3,
#OSCCON,
#0x46,
#0x57,
w1 \n"
w2 \n"
w3 \n"
[w1]\n"
[w1]\n"
#6" ;
"BSET
OSCCON,
// or use C30 built-in macro:
// __builtin_write_OSCCONL(OSCCON | 0x40);
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11.4.6
PERIPHERAL PIN SELECT
REGISTERS
Note:
Input and output register values can only
be changed if IOLOCK (OSCCON<6>) = 0.
See Section 11.4.4.1 “Control Register
Lock” for a specific command sequence.
The PIC24FJ128GA310 family of devices implements
a total of 35 registers for remappable peripheral
configuration:
• Input Remappable Peripheral Registers (19)
• Output Remappable Peripheral Registers (16)
REGISTER 11-7: RPINR0: PERIPHERAL PIN SELECT INPUT REGISTER 0
U-0
—
U-0
—
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
INT1R5
INT1R4
INT1R3
INT1R2
INT1R1
INT1R0
bit 15
bit 8
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-14
bit 13-8
bit 7-0
Unimplemented: Read as ‘0’
INT1R<5:0>: Assign External Interrupt 1 (INT1) to Corresponding RPn or RPIn Pin bits
Unimplemented: Read as ‘0’
REGISTER 11-8: RPINR1: PERIPHERAL PIN SELECT INPUT REGISTER 1
U-0
—
U-0
—
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
INT3R5
INT3R4
INT3R3
INT3R2
INT3R1
INT3R0
bit 15
bit 8
U-0
—
U-0
—
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
INT2R5
INT2R4
INT2R3
INT2R2
INT2R1
INT2R0
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-14
bit 13-8
bit 7-6
Unimplemented: Read as ‘0’
INT3R<5:0>: Assign External Interrupt 3 (INT3) to Corresponding RPn or RPIn Pin bits
Unimplemented: Read as ‘0’
bit 5-0
INT2R<5:0>: Assign External Interrupt 2 (INT2) to Corresponding RPn or RPIn Pin bits
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REGISTER 11-9: RPINR2: PERIPHERAL PIN SELECT INPUT REGISTER 2
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
bit 15
bit 8
U-0
—
U-0
—
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
INT4R5
INT4R4
INT4R3
INT4R2
INT4R1
INT4R0
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-6
bit 5-0
Unimplemented: Read as ‘0’
INT4R<5:0>: Assign External Interrupt 4 (INT4) to Corresponding RPn or RPIn Pin bits
REGISTER 11-10: RPINR3: PERIPHERAL PIN SELECT INPUT REGISTER 3
U-0
—
U-0
—
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
T3CKR5
T3CKR4
T3CKR3
T3CKR2
T3CKR1
T3CKR0
bit 15
bit 8
U-0
—
U-0
—
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
T2CKR5
T2CKR4
T2CKR3
T2CKR2
T2CKR1
T2CKR0
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-14
bit 13-8
bit 7-6
Unimplemented: Read as ‘0’
T3CKR<5:0>: Assign Timer3 External Clock (T3CK) to Corresponding RPn or RPIn Pin bits
Unimplemented: Read as ‘0’
bit 5-0
T2CKR<5:0>: Assign Timer2 External Clock (T2CK) to Corresponding RPn or RPIn Pin bits
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REGISTER 11-11: RPINR4: PERIPHERAL PIN SELECT INPUT REGISTER 4
U-0
—
U-0
—
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
T5CKR5
T5CKR4
T5CKR3
T5CKR2
T5CKR1
T5CKR0
bit 15
bit 8
U-0
—
U-0
—
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
T4CKR5
T4CKR4
T4CKR3
T4CKR2
T4CKR1
T4CKR0
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-14
bit 13-8
bit 7-6
Unimplemented: Read as ‘0’
T5CKR<5:0>: Assign Timer5 External Clock (T5CK) to Corresponding RPn or RPIn Pin bits
Unimplemented: Read as ‘0’
bit 5-0
T4CKR<5:0>: Assign Timer4 External Clock (T4CK) to Corresponding RPn or RPIn Pin bits
REGISTER 11-12: RPINR7: PERIPHERAL PIN SELECT INPUT REGISTER 7
U-0
—
U-0
—
R/W-1
IC2R5
R/W-1
IC2R4
R/W-1
IC2R3
R/W-1
IC2R2
R/W-1
IC2R1
R/W-1
IC2R0
bit 8
bit 15
U-0
—
U-0
—
R/W-1
IC1R5
R/W-1
IC1R4
R/W-1
IC1R3
R/W-1
IC1R2
R/W-1
IC1R1
R/W-1
IC1R0
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-14
bit 13-8
bit 7-6
Unimplemented: Read as ‘0’
IC2R<5:0>: Assign Input Capture 2 (IC2) to Corresponding RPn or RPIn Pin bits
Unimplemented: Read as ‘0’
bit 5-0
IC1R<5:0>: Assign Input Capture 1 (IC1) to Corresponding RPn or RPIn Pin bits
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REGISTER 11-13: RPINR8: PERIPHERAL PIN SELECT INPUT REGISTER 8
U-0
—
U-0
—
R/W-1
IC4R5
R/W-1
IC4R4
R/W-1
IC4R3
R/W-1
IC4R2
R/W-1
IC4R1
R/W-1
IC4R0
bit 15
bit 8
U-0
—
U-0
—
R/W-1
IC3R5
R/W-1
IC3R4
R/W-1
IC3R3
R/W-1
IC3R2
R/W-1
IC3R1
R/W-1
IC3R0
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-14
bit 13-8
bit 7-6
Unimplemented: Read as ‘0’
IC4R<5:0>: Assign Input Capture 4 (IC4) to Corresponding RPn or RPIn Pin bits
Unimplemented: Read as ‘0’
bit 5-0
IC3R<5:0>: Assign Input Capture 3 (IC3) to Corresponding RPn or RPIn Pin bits
REGISTER 11-14: RPINR9: PERIPHERAL PIN SELECT INPUT REGISTER 9
U-0
—
U-0
—
R/W-1
IC6R5
R/W-1
IC6R4
R/W-1
IC6R3
R/W-1
IC6R2
R/W-1
IC6R1
R/W-1
IC6R0
bit 15
bit 8
U-0
—
U-0
—
R/W-1
IC5R5
R/W-1
IC5R4
R/W-1
IC5R3
R/W-1
IC5R2
R/W-1
IC5R1
R/W-1
IC5R0
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-14
bit 13-8
bit 7-6
Unimplemented: Read as ‘0’
IC6R<5:0>: Assign Input Capture 6 (IC6) to Corresponding RPn or RPIn Pin bits
Unimplemented: Read as ‘0’
bit 5-0
IC5R<5:0>: Assign Input Capture 5 (IC5) to Corresponding RPn or RPIn Pin bits
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REGISTER 11-15: RPINR10: PERIPHERAL PIN SELECT INPUT REGISTER 10
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
bit 15
bit 8
U-0
—
U-0
—
R/W-1
IC7R5
R/W-1
IC7R4
R/W-1
IC7R3
R/W-1
IC7R2
R/W-1
IC7R1
R/W-1
IC7R0
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-6
bit 5-0
Unimplemented: Read as ‘0’
IC7R<5:0>: Assign Input Capture 7 (IC7) to Corresponding RPn or RPIn Pin bits
REGISTER 11-16: RPINR11: PERIPHERAL PIN SELECT INPUT REGISTER 11
U-0
—
U-0
—
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
OCFBR5
OCFBR4
OCFBR3
OCFBR2
OCFBR1
OCFBR0
bit 15
bit 8
U-0
—
U-0
—
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
OCFAR5
OCFAR4
OCFAR3
OCFAR2
OCFAR1
OCFAR0
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-14
bit 13-8
bit 7-6
Unimplemented: Read as ‘0’
OCFBR<5:0>: Assign Output Compare Fault B (OCFB) to Corresponding RPn or RPIn Pin bits
Unimplemented: Read as ‘0’
bit 5-0
OCFAR<5:0>: Assign Output Compare Fault A (OCFA) to Corresponding RPn or RPIn Pin bits
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REGISTER 11-17: RPINR17: PERIPHERAL PIN SELECT INPUT REGISTER 17
U-0
—
U-0
—
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
U3RXR5
U3RXR4
U3RXR3
U3RXR2
U3RXR1
U3RXR0
bit 15
bit 8
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-14
bit 13-8
bit 7-0
Unimplemented: Read as ‘0’
U3RXR<5:0>: Assign UART3 Receive (U3RX) to Corresponding RPn or RPIn Pin bits
Unimplemented: Read as ‘0’
REGISTER 11-18: RPINR18: PERIPHERAL PIN SELECT INPUT REGISTER 18
U-0
—
U-0
—
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
U1CTSR5
U1CTSR4
U1CTSR3
U1CTSR2
U1CTSR1
U1CTSR0
bit 15
bit 8
U-0
—
U-0
—
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
U1RXR5
U1RXR4
U1RXR3
U1RXR2
U1RXR1
U1RXR0
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-14
bit 13-8
bit 7-6
Unimplemented: Read as ‘0’
U1CTSR<5:0>: Assign UART1 Clear to Send (U1CTS) to Corresponding RPn or RPIn Pin bits
Unimplemented: Read as ‘0’
bit 5-0
U1RXR<5:0>: Assign UART1 Receive (U1RX) to Corresponding RPn or RPIn Pin bits
2010-2011 Microchip Technology Inc.
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REGISTER 11-19: RPINR19: PERIPHERAL PIN SELECT INPUT REGISTER 19
U-0
—
U-0
—
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
U2CTSR5
U2CTSR4
U2CTSR3
U2CTSR2
U2CTSR1
U2CTSR0
bit 15
bit 8
U-0
—
U-0
—
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
U2RXR5
U2RXR4
U2RXR3
U2RXR2
U2RXR1
U2RXR0
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-14
bit 13-8
bit 7-6
Unimplemented: Read as ‘0’
U2CTSR<5:0>: Assign UART2 Clear to Send (U2CTS) to Corresponding RPn or RPIn Pin bits
Unimplemented: Read as ‘0’
bit 5-0
U2RXR<5:0>: Assign UART2 Receive (U2RX) to Corresponding RPn or RPIn Pin bits
REGISTER 11-20: RPINR20: PERIPHERAL PIN SELECT INPUT REGISTER 20
U-0
—
U-0
—
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
SCK1R0
bit 8
SCK1R5
SCK1R4
SCK1R3
SCK1R2
SCK1R1
bit 15
U-0
—
U-0
—
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
SDI1R5
SDI1R4
SDI1R3
SDI1R2
SDI1R1
SDI1R0
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-14
bit 13-8
bit 7-6
Unimplemented: Read as ‘0’
SCK1R<5:0>: Assign SPI2 Clock Input (SCK2IN) to Corresponding RPn or RPIn Pin bits
Unimplemented: Read as ‘0’
bit 5-0
SDI1R<5:0>: Assign SPI2 Data Input (SDI2) to Corresponding RPn or RPIn Pin bits
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REGISTER 11-21: RPINR21: PERIPHERAL PIN SELECT INPUT REGISTER 21
U-0
—
U-0
—
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
U3CTSR5
U3CTSR4
U3CTSR3
U3CTSR2
U3CTSR1
U3CTSR0
bit 15
bit 8
U-0
—
U-0
—
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
SS1R5
SS1R4
SS1R3
SS1R2
SS1R1
SS1R0
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-14
bit 13-8
bit 7-6
Unimplemented: Read as ‘0’
U3CTSR<5:0>: Assign UART3 Clear to Send (U3CTS) to Corresponding RPn or RPIn Pin bits
Unimplemented: Read as ‘0’
bit 5-0
SS1R<5:0>: Assign SPI1 Slave Select Input (SS1IN) to Corresponding RPn or RPIn Pin bits
REGISTER 11-22: RPINR22: PERIPHERAL PIN SELECT INPUT REGISTER 22
U-0
—
U-0
—
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
T1CKR0
bit 8
T1CKR5
T1CKR4
T1CKR3
T1CKR2
T1CKR1
bit 15
U-0
—
U-0
—
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
SDI2R5
SDI2R4
SDI2R3
SDI2R2
SDI2R1
SDI2R0
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-14
bit 13-8
bit 7-6
Unimplemented: Read as ‘0’
T1CKR<5:0>: Assign Timer1External Clock (T1CK) to Corresponding RPn or RPIn Pin bits
Unimplemented: Read as ‘0’
bit 5-0
SDI2R<5:0>: Assign SPI2 Data Input (SDI2) to Corresponding RPn or RPIn Pin bits
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REGISTER 11-23: RPINR23: PERIPHERAL PIN SELECT INPUT REGISTER 23
U-0
—
U-0
—
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
T1CKR5
T1CKR4
T1CKR3
T1CKR2
T1CKR1
T1CKR0
bit 15
bit 8
U-0
—
U-0
—
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
SS2R5
SS2R4
SS2R3
SS2R2
SS2R1
SS2R0
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-14
bit 13-8
bit 7-6
Unimplemented: Read as ‘0’
T1CKR<5:0>:
Unimplemented: Read as ‘0’
bit 5-0
SS2R<5:0>: Assign SPI2 Slave Select Input (SS2IN) to Corresponding RPn or RPIn Pin bits
REGISTER 11-24: RPINR27: PERIPHERAL PIN SELECT INPUT REGISTER 27
U-0
—
U-0
—
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
U4CTSR0
bit 8
U4CTSR5
U4CTSR4
U4CTSR3
U4CTSR2
U4CTSR1
bit 15
U-0
—
U-0
—
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
U4RXR5
U4RXR4
U4RXR3
U4RXR2
U4RXR1
U4RXR0
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-14
bit 13-8
bit 7-6
Unimplemented: Read as ‘0’
U4CTSR<5:0>: Assign UART4 Clear-to-send Input (U4CTS) to Corresponding RPn or RPIn Pin bits
Unimplemented: Read as ‘0’
bit 5-0
U4RXR<5:0>: Assign UART4 Receive Input (U4RX) to Corresponding RPn or RPIn Pin bits
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REGISTER 11-25: RPINR30: PERIPHERAL PIN SELECT INPUT REGISTER 30
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
bit 15
bit 8
U-0
—
U-0
—
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
MDMIR5
MDMIR4
MDMIR3
MDMIR2
MDMIR1
MDMIR0
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-6
bit 5-0
Unimplemented: Read as ‘0’
MDMIR<5:0>: Assign TX Modulation Input (MDMI) to Corresponding RPn or RPIn Pin bits
REGISTER 11-26: RPINR31: PERIPHERAL PIN SELECT INPUT REGISTER 31
U-0
—
U-0
—
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
MDC2R5
MDC2R4
MDC2R3
MDC2R2
MDC2R1
MDC2R0
bit 15
bit 8
U-0
—
U-0
—
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
MDC1R5
MDC1R4
MDC1R3
MDC1R2
MDC21R1
MDC1R0
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-14
bit 13-8
bit 7-6
Unimplemented: Read as ‘0’
MDC2R<5:0>: Assign TX Carrier 2 Input (MDCIN2) to Corresponding RPn or RPIn Pin bits
Unimplemented: Read as ‘0’
bit 5-0
MDC1R<5:0>: Assign SPI3 Data Input (MDCIN1) to Corresponding RPn or RPIn Pin bits
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REGISTER 11-27: RPOR0: PERIPHERAL PIN SELECT OUTPUT REGISTER 0
U-0
—
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
RP1R5
RP1R4
RP1R3
RP1R2
RP1R1
RP1R0
bit 15
bit 8
U-0
—
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
RP0R5
RP0R4
RP0R3
RP0R2
RP0R1
RP0R0
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-14
bit 13-8
Unimplemented: Read as ‘0’
RP1R<5:0>: RP1 Output Pin Mapping bits
Peripheral output number n is assigned to pin, RP1 (see Table 11-4 for peripheral function numbers).
Unimplemented: Read as ‘0’
bit 7-6
bit 5-0
RP0R<5:0>: RP0 Output Pin Mapping bits
Peripheral output number n is assigned to pin, RP0 (see Table 11-4 for peripheral function numbers).
REGISTER 11-28: RPOR1: PERIPHERAL PIN SELECT OUTPUT REGISTER 1
U-0
—
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
RP3R5
RP3R4
RP3R3
RP3R2
RP3R1
RP3R0
bit 15
bit 8
U-0
—
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
RP2R5
RP2R4
RP2R3
RP2R2
RP2R1
RP2R0
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-14
bit 13-8
Unimplemented: Read as ‘0’
RP3R<5:0>: RP3 Output Pin Mapping bits
Peripheral output number n is assigned to pin, RP3 (see Table 11-4 for peripheral function numbers).
Unimplemented: Read as ‘0’
bit 7-6
bit 5-0
RP2R<5:0>: RP2 Output Pin Mapping bits
Peripheral output number n is assigned to pin, RP2 (see Table 11-4 for peripheral function numbers).
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REGISTER 11-29: RPOR2: PERIPHERAL PIN SELECT OUTPUT REGISTER 2
U-0
—
U-0
—
R/W-0
RP5R5(1)
R/W-0
RP5R4(1)
R/W-0
RP5R3(1)
R/W-0
RP5R2(1)
R/W-0
RP5R1(1)
R/W-0
RP5R0(1)
bit 15
bit 8
U-0
—
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
RP4R5
RP4R4
RP4R3
RP4R2
RP4R1
RP4R0
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-14
bit 13-8
Unimplemented: Read as ‘0’
RP5R<5:0>: RP5 Output Pin Mapping bits(1)
Peripheral output number n is assigned to pin, RP5 (see Table 11-4 for peripheral function numbers).
Unimplemented: Read as ‘0’
bit 7-6
bit 5-0
RP4R<5:0>: RP4 Output Pin Mapping bits
Peripheral output number n is assigned to pin, RP4 (see Table 11-4 for peripheral function numbers).
Note 1: These bits are unimplemented in 64-pin devices; read as ‘0’.
REGISTER 11-30: RPOR3: PERIPHERAL PIN SELECT OUTPUT REGISTER 3
U-0
—
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
RP7R5
RP7R4
RP7R3
RP7R2
RP7R1
RP7R0
bit 15
bit 8
U-0
—
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
RP6R5
RP6R4
RP6R3
RP6R2
RP6R1
RP6R0
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-14
bit 13-8
Unimplemented: Read as ‘0’
RP7R<5:0>: RP7 Output Pin Mapping bits
Peripheral output number n is assigned to pin, RP7 (see Table 11-4 for peripheral function numbers).
Unimplemented: Read as ‘0’
bit 7-6
bit 5-0
RP6R<5:0>: RP6 Output Pin Mapping bits
Peripheral output number n is assigned to pin, RP6 (see Table 11-4 for peripheral function numbers).
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REGISTER 11-31: RPOR4: PERIPHERAL PIN SELECT OUTPUT REGISTER 4
U-0
—
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
RP9R5
RP9R4
RP9R3
RP9R2
RP9R1
RP9R0
bit 15
bit 8
U-0
—
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
RP8R5
RP8R4
RP8R3
RP8R2
RP8R1
RP8R0
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-14
bit 13-8
Unimplemented: Read as ‘0’
RP9R<5:0>: RP9 Output Pin Mapping bits
Peripheral output number n is assigned to pin, RP9 (see Table 11-4 for peripheral function numbers).
Unimplemented: Read as ‘0’
bit 7-6
bit 5-0
RP8R<5:0>: RP8 Output Pin Mapping bits
Peripheral output number n is assigned to pin, RP8 (see Table 11-4 for peripheral function numbers).
REGISTER 11-32: RPOR5: PERIPHERAL PIN SELECT OUTPUT REGISTER 5
U-0
—
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
RP11R5
RP11R4
RP11R3
RP11R2
RP11R1
RP11R0
bit 15
bit 8
U-0
—
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
RP10R5
RP10R4
RP10R3
RP10R2
RP10R1
RP10R0
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-14
bit 13-8
Unimplemented: Read as ‘0’
RP11R<5:0>: RP11 Output Pin Mapping bits
Peripheral output number n is assigned to pin, RP11 (see Table 11-4 for peripheral function numbers).
Unimplemented: Read as ‘0’
bit 7-6
bit 5-0
RP10R<5:0>: RP10 Output Pin Mapping bits
Peripheral output number n is assigned to pin, RP10 (see Table 11-4 for peripheral function numbers).
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REGISTER 11-33: RPOR6: PERIPHERAL PIN SELECT OUTPUT REGISTER 6
U-0
—
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
RP13R5
RP13R4
RP13R3
RP13R2
RP13R1
RP13R0
bit 15
bit 8
U-0
—
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
RP12R5
RP12R4
RP12R3
RP12R2
RP12R1
RP12R0
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-14
bit 13-8
Unimplemented: Read as ‘0’
RP13R<5:0>: RP13 Output Pin Mapping bits
Peripheral output number n is assigned to pin, RP13 (see Table 11-4 for peripheral function numbers).
Unimplemented: Read as ‘0’
bit 7-6
bit 5-0
RP12R<5:0>: RP12 Output Pin Mapping bits
Peripheral output number n is assigned to pin, RP12 (see Table 11-4 for peripheral function numbers).
REGISTER 11-34: RPOR7: PERIPHERAL PIN SELECT OUTPUT REGISTER 7
U-0
—
U-0
—
R/W-0
RP15R5(1)
R/W-0
RP15R4(1)
R/W-0
RP15R3(1)
R/W-0
RP15R2(1)
R/W-0
RP15R1(1)
R/W-0
RP15R0(1)
bit 15
bit 8
U-0
—
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
RP14R5
RP14R4
RP14R3
RP14R2
RP14R1
RP14R0
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-14
bit 13-8
Unimplemented: Read as ‘0’
RP15R<5:0>: RP15 Output Pin Mapping bits(1)
Peripheral output number n is assigned to pin, RP0 (see Table 11-4 for peripheral function numbers).
Unimplemented: Read as ‘0’
bit 7-6
bit 5-0
RP14R<5:0>: RP14 Output Pin Mapping bits
Peripheral output number n is assigned to pin, RP14 (see Table 11-4 for peripheral function numbers).
Note 1: These bits are unimplemented in 64-pin devices; read as ‘0’.
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REGISTER 11-35: RPOR8: PERIPHERAL PIN SELECT OUTPUT REGISTER 8
U-0
—
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
RP17R5
RP17R4
RP17R3
RP17R2
RP17R1
RP17R0
bit 15
bit 8
U-0
—
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
RP16R5
RP16R4
RP16R3
RP16R2
RP16R1
RP16R0
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-14
bit 13-8
Unimplemented: Read as ‘0’
RP17R<5:0>: RP17 Output Pin Mapping bits
Peripheral output number n is assigned to pin, RP17 (see Table 11-4 for peripheral function numbers).
Unimplemented: Read as ‘0’
bit 7-6
bit 5-0
RP16R<5:0>: RP16 Output Pin Mapping bits
Peripheral output number n is assigned to pin, RP16 (see Table 11-4 for peripheral function numbers).
REGISTER 11-36: RPOR9: PERIPHERAL PIN SELECT OUTPUT REGISTER 9
U-0
—
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
RP19R5
RP19R4
RP19R3
RP19R2
RP19R1
RP19R0
bit 15
bit 8
U-0
—
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
RP18R5
RP18R4
RP18R3
RP18R2
RP18R1
RP18R0
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-14
bit 13-8
Unimplemented: Read as ‘0’
RP19R<5:0>: RP19 Output Pin Mapping bits
Peripheral output number n is assigned to pin, RP19 (see Table 11-4 for peripheral function numbers).
Unimplemented: Read as ‘0’
bit 7-6
bit 5-0
RP18R<5:0>: RP18 Output Pin Mapping bits
Peripheral output number n is assigned to pin, RP18 (see Table 11-4 for peripheral function numbers).
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REGISTER 11-37: RPOR10: PERIPHERAL PIN SELECT OUTPUT REGISTER 10
U-0
—
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
RP21R5
RP21R4
RP21R3
RP21R2
RP21R1
RP21R0
bit 15
bit 8
U-0
—
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
RP20R5
RP20R4
RP20R3
RP20R2
RP20R1
RP20R0
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-14
bit 13-8
Unimplemented: Read as ‘0’
RP21R<5:0>: RP21 Output Pin Mapping bits
Peripheral output number n is assigned to pin, RP21 (see Table 11-4 for peripheral function numbers).
Unimplemented: Read as ‘0’
bit 7-6
bit 5-0
RP20R<5:0>: RP20 Output Pin Mapping bits
Peripheral output number n is assigned to pin, RP20 (see Table 11-4 for peripheral function numbers).
REGISTER 11-38: RPOR11: PERIPHERAL PIN SELECT OUTPUT REGISTER 11
U-0
—
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
RP23R5
RP23R4
RP23R3
RP23R2
RP23R1
RP23R0
bit 15
bit 8
U-0
—
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
RP22R5
RP22R4
RP22R3
RP22R2
RP22R1
RP22R0
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-14
bit 13-8
Unimplemented: Read as ‘0’
RP23R<5:0>: RP23 Output Pin Mapping bits
Peripheral output number n is assigned to pin, RP23 (see Table 11-4 for peripheral function numbers).
Unimplemented: Read as ‘0’
bit 7-6
bit 5-0
RP22R<5:0>: RP22 Output Pin Mapping bits
Peripheral output number n is assigned to pin, RP22 (see Table 11-4 for peripheral function numbers).
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REGISTER 11-39: RPOR12: PERIPHERAL PIN SELECT OUTPUT REGISTER 12
U-0
—
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
RP25R5
RP25R4
RP25R3
RP25R2
RP25R1
RP25R0
bit 15
bit 8
U-0
—
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
RP24R5
RP24R4
RP24R3
RP24R2
RP24R1
RP24R0
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-14
bit 13-8
Unimplemented: Read as ‘0’
RP25R<5:0>: RP25 Output Pin Mapping bits
Peripheral output number n is assigned to pin, RP25 (see Table 11-4 for peripheral function numbers).
Unimplemented: Read as ‘0’
bit 7-6
bit 5-0
RP24R<5:0>: RP24 Output Pin Mapping bits
Peripheral output number n is assigned to pin, RP24 (see Table 11-4 for peripheral function numbers).
REGISTER 11-40: RPOR13: PERIPHERAL PIN SELECT OUTPUT REGISTER 13
U-0
—
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
RP27R5
RP27R4
RP27R3
RP27R2
RP27R1
RP27R0
bit 15
bit 8
U-0
—
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
RP26R5
RP26R4
RP26R3
RP26R2
RP26R1
RP26R0
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-14
bit 13-8
Unimplemented: Read as ‘0’
RP27R<5:0>: RP27 Output Pin Mapping bits
Peripheral output number n is assigned to pin, RP27 (see Table 11-4 for peripheral function numbers).
Unimplemented: Read as ‘0’
bit 7-6
bit 5-0
RP26R<5:0>: RP26 Output Pin Mapping bits
Peripheral output number n is assigned to pin, RP26 (see Table 11-4 for peripheral function numbers).
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REGISTER 11-41: RPOR14: PERIPHERAL PIN SELECT OUTPUT REGISTER 14
U-0
—
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
RP29R5
RP29R4
RP29R3
RP29R2
RP29R1
RP29R0
bit 15
bit 8
U-0
—
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
RP28R5
RP28R4
RP28R3
RP28R2
RP28R1
RP28R0
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-14
bit 13-8
Unimplemented: Read as ‘0’
RP29R<5:0>: RP29 Output Pin Mapping bits
Peripheral output number n is assigned to pin, RP29 (see Table 11-4 for peripheral function numbers).
Unimplemented: Read as ‘0’
bit 7-6
bit 5-0
RP28R<5:0>: RP28 Output Pin Mapping bits
Peripheral output number n is assigned to pin, RP28 (see Table 11-4 for peripheral function numbers).
REGISTER 11-42: RPOR15: PERIPHERAL PIN SELECT OUTPUT REGISTER 15
U-0
—
U-0
—
R/W-0
RP31R5(1)
R/W-0
RP31R4(1)
R/W-0
RP31R3(1)
R/W-0
RP31R2(1)
R/W-0
RP31R1(1)
R/W-0
RP31R0(1)
bit 15
bit 8
U-0
—
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
RP30R5
RP30R4
RP30R3
RP30R2
RP30R1
RP30R0
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-14
bit 13-8
Unimplemented: Read as ‘0’
RP31R<5:0>: RP31 Output Pin Mapping bits(1)
Peripheral output number n is assigned to pin, RP31 (see Table 11-4 for peripheral function numbers).
Unimplemented: Read as ‘0’
bit 7-6
bit 5-0
RP30R<5:0>: RP30 Output Pin Mapping bits
Peripheral output number n is assigned to pin, RP30 (see Table 11-4 for peripheral function numbers).
Note 1: These bits are unimplemented in 64-pin and 80-pin devices; read as ‘0’.
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NOTES:
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Figure 12-1 presents a block diagram of the 16-bit
timer module.
12.0 TIMER1
Note:
This data sheet summarizes the features of
this group of PIC24F devices. It is not
To configure Timer1 for operation:
1. Set the TON bit (= 1).
intended to be a comprehensive reference
source. For more information, refer to the
“PIC24F Family Reference Manual”,
Section 14. “Timers” (DS39704). The
information in this data sheet supersedes
the information in the FRM.
2. Select the timer prescaler ratio using the
TCKPS<1:0> bits.
3. Set the Clock and Gating modes using the TCS,
TECS and TGATE bits.
4. Set or clear the TSYNC bit to configure
synchronous or asynchronous operation.
The Timer1 module is a 16-bit timer, which can serve
as the time counter for the Real-Time Clock (RTC) or
operate as a free-running, interval timer/counter.
Timer1 can operate in three modes:
5. Load the timer period value into the PR1
register.
6. If interrupts are required, set the interrupt enable
bit, T1IE. Use the priority bits, T1IP<2:0>, to set
the interrupt priority.
• 16-Bit Timer
• 16-Bit Synchronous Counter
• 16-Bit Asynchronous Counter
Timer1 also supports these features:
• Timer Gate Operation
• Selectable Prescaler Settings
• Timer Operation during CPU Idle and Sleep
modes
• Interrupt on 16-Bit Period Register Match or
Falling Edge of External Gate Signal
FIGURE 12-1:
16-BIT TIMER1 MODULE BLOCK DIAGRAM
TGATE
LPRC
Clock
Input Select
1
0
D
Q
Q
SOSCO
Set T1IF
CK
Reset
Equal
TMR1
SOSCI
Comparator
PR1
SOSCSEL<1:0>
SOSCEN
Clock Input Select Detail
T1ECS<1:0>
2
Gate
Output
TCKPS<1:0>
2
SOSC
Input
TON
T1CK Input
LPRC Input
Prescaler
1, 8, 64, 256
Gate
Sync
0
1
Clock
Output
to TMR1
Sync
TCY
TSYNC
TGATE
TCS
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REGISTER 12-1: T1CON: TIMER1 CONTROL REGISTER(1)
R/W-0
TON
U-0
—
R/W-0
TSIDL
U-0
—
U-0
—
U-0
—
R/W-0
R/W-0
TIECS1
TIECS0
bit 15
bit 8
U-0
—
R/W-0
R/W-0
R/W-0
U-0
—
R/W-0
R/W-0
TCS
U-0
—
TGATE
TCKPS1
TCKPS0
TSYNC
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15
TON: Timer1 On bit
1= Starts 16-bit Timer1
0= Stops 16-bit Timer1
bit 14
bit 13
Unimplemented: Read as ‘0’
TSIDL: Stop in Idle Mode bit
1= Discontinue module operation when device enters Idle mode
0= Continue module operation in Idle mode
bit 12-10
bit 9-8
Unimplemented: Read as ‘0’
TIECS<1:0>: Timer1 Extended Clock Source Select bits (selected when TCS = 1)
11= Unimplemented, do not use
10= LPRC Oscillator
01= T1CK external clock input
00= SOSC
bit 7
bit 6
Unimplemented: Read as ‘0’
TGATE: Timer1 Gated Time Accumulation Enable bit
When TCS = 1:
This bit is ignored.
When TCS = 0:
1= Gated time accumulation is enabled
0= Gated time accumulation is disabled
bit 5-4
TCKPS<1:0>: Timer1 Input Clock Prescale Select bits
11= 1:256
10= 1:64
01= 1:8
00= 1:1
bit 3
bit 2
Unimplemented: Read as ‘0’
TSYNC: Timer1 External Clock Input Synchronization Select bit
When TCS = 1:
1= Synchronize external clock input
0= Do not synchronize external clock input
When TCS = 0:
This bit is ignored.
bit 1
bit 0
TCS: Timer1 Clock Source Select bit
1= Extended clock selected by the timer
0= Internal clock (FOSC/2)
Unimplemented: Read as ‘0’
Note 1: Changing the value of T1CON while the timer is running (TON = 1) causes the timer prescale counter to
reset and is not recommended.
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To configure Timer2/3 or Timer4/5 for 32-bit operation:
1. Set the T32 or T45 bit (T2CON<3> or
13.0 TIMER2/3 AND TIMER4/5
Note:
This data sheet summarizes the features of
T4CON<3> = 1).
this group of PIC24F devices. It is not
intended to be a comprehensive reference
source. For more information, refer to the
“PIC24F Family Reference Manual”,
Section 14. “Timers” (DS39704). The
information in this data sheet supersedes
the information in the FRM.
2. Select the prescaler ratio for Timer2 or Timer4
using the TCKPS<1:0> bits.
3. Set the Clock and Gating modes using the TCS
and TGATE bits. If TCS is set to an external
clock, RPINRx (TxCK) must be configured to
an available RPn/RPIn pin. For more informa-
tion, see Section 11.4 “Peripheral Pin Select
(PPS)”.
The Timer2/3 and Timer4/5 modules are 32-bit timers,
which can also be configured as four independent, 16-bit
timers with selectable operating modes.
4. Load the timer period value. PR3 (or PR5) will
contain the most significant word (msw) of the
value, while PR2 (or PR4) contains the least
significant word (lsw).
As 32-bit timers, Timer2/3 and Timer4/5 can each
operate in three modes:
5. If interrupts are required, set the interrupt enable
bit, T3IE or T5IE. Use the priority bits, T3IP<2:0>
or T5IP<2:0>, to set the interrupt priority. Note
that while Timer2 or Timer4 controls the timer, the
interrupt appears as a Timer3 or Timer5 interrupt.
• Two independent 16-bit timers with all 16-bit
operating modes (except Asynchronous Counter
mode)
• Single 32-bit timer
• Single 32-bit synchronous counter
6. Set the TON bit (= 1).
They also support these features:
The timer value, at any point, is stored in the register
pair, TMR<3:2> (or TMR<5:4>). TMR3 (TMR5) always
contains the most significant word of the count, while
TMR2 (TMR4) contains the least significant word.
• Timer Gate Operation
• Selectable Prescaler Settings
• Timer Operation during Idle and Sleep modes
• Interrupt on a 32-Bit Period Register Match
To configure any of the timers for individual 16-bit
operation:
• A/D Event Trigger (only on Timer2/3 in 32-bit
mode and Timer3 in 16-bit mode)
1. Clear the T32 bit corresponding to that timer
(T2CON<3> for Timer2 and Timer3 or
T4CON<3> for Timer4 and Timer5).
Individually, all four of the 16-bit timers can function as
synchronous timers or counters. They also offer the
features listed above, except for the A/D Event Trigger.
This trigger is implemented only on Timer2/3 in 32-bit
mode and Timer3 in 16-bit mode. The operating modes
and enabled features are determined by setting the
appropriate bit(s) in the T2CON, T3CON, T4CON and
T5CON registers. T2CON and T4CON are shown in
generic form in Register 13-1; T3CON and T5CON are
shown in Register 13-2.
2. Select the timer prescaler ratio using the
TCKPS<1:0> bits.
3. Set the Clock and Gating modes using the TCS
and TGATE bits. See Section 11.4 “Peripheral
Pin Select (PPS)” for more information.
4. Load the timer period value into the PRx register.
5. If interrupts are required, set the interrupt enable
bit, TxIE. Use the priority bits, TxIP<2:0>, to set
the interrupt priority.
For 32-bit timer/counter operation, Timer2 and Timer4
are the least significant word; Timer3 and Timer4 are
the most significant word of the 32-bit timers.
6. Set the TON (TxCON<15> = 1) bit.
Note:
For 32-bit operation, T3CON and T5CON
control bits are ignored. Only T2CON and
T4CON control bits are used for setup and
control. Timer2 and Timer4 clock and gate
inputs are utilized for the 32-bit timer
modules, but an interrupt is generated
with the Timer3 or Timer5 interrupt flags.
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FIGURE 13-1:
TIMER2/3 AND TIMER4/5 (32-BIT) BLOCK DIAGRAM
TCKPS<1:0>
2
TON
T2CK
(T4CK)
1x
01
00
Prescaler
1, 8, 64, 256
Gate
Sync
TCY
(2)
TGATE
TGATE
(2)
TCS
1
0
Q
D
Set T3IF (T5IF)
Q
CK
PR3
PR2
(PR5)
(PR4)
(3)
A/D Event Trigger
Equal
MSB
Comparator
LSB
TMR2
(TMR4)
TMR3
(TMR5)
Sync
Reset
16
(1)
(1)
Read TMR2 (TMR4)
Write TMR2 (TMR4)
16
16
TMR3HLD
(TMR5HLD)
Data Bus<15:0>
Note 1: The 32-Bit Timer Configuration bit, T32, must be set for 32-bit timer/counter operation. All control bits are
respective to the T2CON and T4CON registers.
2: The timer clock input must be assigned to an available RPn/RPIn pin before use. See Section 11.4 “Peripheral
Pin Select (PPS)” for more information.
3: The A/D event trigger is available only on Timer 2/3 in 32-bit mode and Timer 3 in 16-bit mode.
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FIGURE 13-2:
TIMER2 AND TIMER4 (16-BIT SYNCHRONOUS) BLOCK DIAGRAM
TCKPS<1:0>
TON
2
T2CK
(T4CK)
1x
Prescaler
1, 8, 64, 256
Gate
Sync
01
00
TGATE
(1)
TCS
TGATE
TCY
(1)
Q
D
1
0
Set T2IF (T4IF)
Q
CK
Reset
Equal
TMR2 (TMR4)
Sync
Comparator
PR2 (PR4)
Note 1: The timer clock input must be assigned to an available RPn/RPIn pin before use. See Section 11.4 “Peripheral
Pin Select (PPS)” for more information.
FIGURE 13-3:
TIMER3 AND TIMER5 (16-BIT ASYNCHRONOUS) BLOCK DIAGRAM
TCKPS<1:0>
2
TON
T3CK
(T5CK)
1x
01
00
Sync
Prescaler
1, 8, 64, 256
TGATE
(1)
TCS
TGATE
TCY
(1)
Q
Q
D
1
0
Set T3IF (T5IF)
CK
Reset
Equal
TMR3 (TMR5)
(2)
A/D Event Trigger
Comparator
PR3 (PR5)
Note 1: The timer clock input must be assigned to an available RPn/RPIn pin before use. See Section 11.4 “Peripheral
Pin Select (PPS)” for more information.
2: The A/D event trigger is available only on Timer3.
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REGISTER 13-1: TxCON: TIMER2 AND TIMER4 CONTROL REGISTER(3)
R/W-0
TON
U-0
—
R/W-0
TSIDL
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
bit 15
bit 8
bit 0
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
T32(1)
U-0
—
R/W-0
TCS(2)
U-0
—
TGATE
TCKPS1
TCKPS0
bit 7
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
-n = Value at POR
bit 15
TON: Timerx On bit
When TxCON<3> = 1:
1= Starts 32-bit Timerx/y
0= Stops 32-bit Timerx/y
When TxCON<3> = 0:
1= Starts 16-bit Timerx
0= Stops 16-bit Timerx
bit 14
bit 13
Unimplemented: Read as ‘0’
TSIDL: Stop in Idle Mode bit
1= Discontinue module operation when device enters Idle mode
0= Continue module operation in Idle mode
bit 12-7
bit 6
Unimplemented: Read as ‘0’
TGATE: Timerx Gated Time Accumulation Enable bit
When TCS = 1:
This bit is ignored.
When TCS = 0:
1= Gated time accumulation is enabled
0= Gated time accumulation is disabled
bit 5-4
bit 3
TCKPS<1:0>: Timerx Input Clock Prescale Select bits
11= 1:256
10= 1:64
01= 1:8
00= 1:1
T32: 32-Bit Timer Mode Select bit(1)
1= Timerx and Timery form a single 32-bit timer
0= Timerx and Timery act as two 16-bit timers
In 32-bit mode, T3CON control bits do not affect 32-bit timer operation.
bit 2
bit 1
Unimplemented: Read as ‘0’
TCS: Timerx Clock Source Select bit(2)
1= External clock is from pin, TxCK (on the rising edge)
0= Internal clock (FOSC/2)
bit 0
Unimplemented: Read as ‘0’
Note 1: In T4CON, the T45 bit is implemented instead of T32 to select 32-bit mode. In 32-bit mode, the T3CON or
T5CON control bits do not affect 32-bit timer operation.
2: If TCS = 1, RPINRx (TxCK) must be configured to an available RPn/RPIn pin. For more information, see
Section 11.4 “Peripheral Pin Select (PPS)”.
3: Changing the value of TxCON while the timer is running (TON = 1) causes the timer prescale counter to
reset and is not recommended.
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REGISTER 13-2: TyCON: TIMER3 AND TIMER5 CONTROL REGISTER(3)
R/W-0
TON(1)
U-0
—
R/W-0
TSIDL(1)
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
bit 15
bit 8
bit 0
U-0
—
R/W-0
TGATE(1)
R/W-0
TCKPS1(1)
R/W-0
TCKPS0(1)
U-0
—
U-0
—
R/W-0
TCS(1,2)
U-0
—
bit 7
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
-n = Value at POR
bit 15
TON: Timery On bit(1)
1= Starts 16-bit Timery
0= Stops 16-bit Timery
bit 14
bit 13
Unimplemented: Read as ‘0’
TSIDL: Stop in Idle Mode bit(1)
1= Discontinue module operation when device enters Idle mode
0= Continue module operation in Idle mode
bit 12-7
bit 6
Unimplemented: Read as ‘0’
TGATE: Timery Gated Time Accumulation Enable bit(1)
When TCS = 1:
This bit is ignored.
When TCS = 0:
1= Gated time accumulation is enabled
0= Gated time accumulation is disabled
bit 5-4
TCKPS<1:0>: Timery Input Clock Prescale Select bits(1)
11= 1:256
10= 1:64
01= 1:8
00= 1:1
bit 3-2
bit 1
Unimplemented: Read as ‘0’
TCS: Timery Clock Source Select bit(1,2)
1= External clock from pin, TyCK (on the rising edge)
0= Internal clock (FOSC/2)
bit 0
Unimplemented: Read as ‘0’
Note 1: When 32-bit operation is enabled (T2CON<3> or T4CON<3> = 1), these bits have no effect on Timery
operation; all timer functions are set through T2CON and T4CON.
2: If TCS = 1, RPINRx (TxCK) must be configured to an available RPn/RPIn pin. See Section 11.4 “Peripheral
Pin Select (PPS)” for more information.
3: Changing the value of TyCON while the timer is running (TON = 1) causes the timer prescale counter to
reset and is not recommended.
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NOTES:
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14.1 General Operating Modes
14.0 INPUT CAPTURE WITH
DEDICATED TIMERS
14.1.1
SYNCHRONOUS AND TRIGGER
MODES
Note:
This data sheet summarizes the features of
this group of PIC24F devices. It is not
intended to be a comprehensive reference
source. For more information, refer to the
“PIC24F Family Reference Manual”,
Section 34. “Input Capture with
Dedicated Timer” (DS39722). The infor-
mation in this data sheet supersedes the
information in the FRM.
When the input capture module operates in a
Free-Running mode, the internal 16-bit counter,
ICxTMR, counts up continuously, wrapping around
from FFFFh to 0000h on each overflow. Its period is
synchronized to the selected external clock source.
When a capture event occurs, the current 16-bit value
of the internal counter is written to the FIFO buffer.
In Synchronous mode, the module begins capturing
events on the ICx pin as soon as its selected clock
source is enabled. Whenever an event occurs on the
selected sync source, the internal counter is reset. In
Trigger mode, the module waits for a Sync event from
another internal module to occur before allowing the
internal counter to run.
Devices in the PIC24FJ128GA310 family contain
seven independent input capture modules. Each of the
modules offers a wide range of configuration and
operating options for capturing external pulse events
and generating interrupts.
Key features of the input capture module include:
Standard, free-running operation is selected by setting
the SYNCSEL bits (ICxCON2<4:0>) to ‘00000’ and
clearing the ICTRIG bit (ICxCON2<7>). Synchronous
and Trigger modes are selected any time the
SYNCSEL bits are set to any value except ‘00000’.
The ICTRIG bit selects either Synchronous or Trigger
mode; setting the bit selects Trigger mode operation. In
both modes, the SYNCSEL bits determine the
sync/trigger source.
• Hardware configurable for 32-bit operation in all
modes by cascading two adjacent modules
• Synchronous and Trigger modes of output
compare operation, with up to 30 user-selectable
sync/trigger sources available
• A 4-level FIFO buffer for capturing and holding
timer values for several events
• Configurable interrupt generation
• Up to 6 clock sources available for each module,
driving a separate internal 16-bit counter
When the SYNCSEL bits are set to ‘00000’ and
ICTRIG is set, the module operates in Software Trigger
mode. In this case, capture operations are started by
manually setting the TRIGSTAT bit (ICxCON2<6>).
The module is controlled through two registers:
ICxCON1 (Register 14-1) and ICxCON2 (Register 14-2).
A general block diagram of the module is shown in
Figure 14-1.
FIGURE 14-1:
INPUT CAPTURE BLOCK DIAGRAM
ICM<2:0>
ICI1<:0>
Event and
Interrupt
Logic
Set ICXIF
Prescaler
Counter
1:1/4/16
Edge Detect Logic
and
Clock Synchronizer
(1)
ICX Pin
ICTSEL<2:0>
Increment
16
IC Clock
Sources
Clock
Select
ICXTMR
4-Level FIFO Buffer
16
16
Reset
Sync and
Trigger
Logic
ICXBUF
Sync and
Trigger Sources
SYNCSEL<4:0>
Trigger
System Bus
ICOV, ICBNE
Note 1: The ICx inputs must be assigned to an available RPn/RPIn pin before use. See Section 11.4 “Peripheral Pin Select
(PPS)” for more information.
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For 32-bit cascaded operations, the setup procedure is
slightly different:
14.1.2
CASCADED (32-BIT) MODE
By default, each module operates independently with
its own 16-bit timer. To increase resolution, adjacent
even and odd modules can be configured to function as
a single 32-bit module. (For example, Modules 1 and 2
are paired, as are Modules 3 and 4, and so on.) The
odd numbered module (ICx) provides the Least Signif-
icant 16 bits of the 32-bit register pairs and the even
module (ICy) provides the Most Significant 16 bits.
Wrap-arounds of the ICx registers cause an increment
of their corresponding ICy registers.
1. Set the IC32 bits for both modules
(ICyCON2<8>) and (ICxCON2<8>), enabling
the even numbered module first. This ensures
the modules will start functioning in unison.
2. Set the ICTSEL and SYNCSEL bits for both
modules to select the same sync/trigger and
time base source. Set the even module first,
then the odd module. Both modules must use
the same ICTSEL and SYNCSEL bits settings.
3. Clear the ICTRIG bit of the even module
(ICyCON2<7>). This forces the module to run in
Synchronous mode with the odd module,
regardless of its trigger setting.
Cascaded operation is configured in hardware by
setting the IC32 bits (ICxCON2<8>) for both modules.
14.2 Capture Operations
4. Use the odd module’s ICI bits (ICxCON1<6:5>)
to set the desired interrupt frequency.
The input capture module can be configured to capture
timer values and generate interrupts on rising edges on
ICx or all transitions on ICx. Captures can be config-
ured to occur on all rising edges or just some (every 4th
or 16th). Interrupts can be independently configured to
generate on each event or a subset of events.
5. Use the ICTRIG bit of the odd module
(ICxCON2<7>) to configure Trigger or
Synchronous mode operation.
Note:
For Synchronous mode operation, enable
the sync source as the last step. Both
input capture modules are held in Reset
until the sync source is enabled.
To set up the module for capture operations:
1. Configure the ICx input for one of the available
Peripheral Pin Select pins.
6. Use the ICM bits of the odd module
(ICxCON1<2:0>) to set the desired Capture
mode.
2. If Synchronous mode is to be used, disable the
sync source before proceeding.
3. Make sure that any previous data has been
removed from the FIFO by reading ICxBUF until
the ICBNE bit (ICxCON1<3>) is cleared.
The module is ready to capture events when the time
base and the sync/trigger source are enabled. When
the ICBNE bit (ICxCON1<3>) becomes set, at least
one capture value is available in the FIFO. Read input
capture values from the FIFO until the ICBNE clears
to ‘0’.
4. Set the SYNCSEL bits (ICxCON2<4:0>) to the
desired sync/trigger source.
5. Set the ICTSEL bits (ICxCON1<12:10>) for the
desired clock source.
For 32-bit operation, read both the ICxBUF and
ICyBUF for the full 32-bit timer value (ICxBUF for the
lsw, ICyBUF for the msw). At least one capture value is
available in the FIFO buffer when the odd module’s
ICBNE bit (ICxCON1<3>) becomes set. Continue to
read the buffer registers until ICBNE is cleared
(performed automatically by hardware).
6. Set the ICI bits (ICxCON1<6:5>) to the desired
interrupt frequency
7. Select Synchronous or Trigger mode operation:
a) Check that the SYNCSEL bits are not set to
‘00000’.
b) For Synchronous mode, clear the ICTRIG
bit (ICxCON2<7>).
c) For Trigger mode, set ICTRIG, and clear the
TRIGSTAT bit (ICxCON2<6>).
8. Set the ICM bits (ICxCON1<2:0>) to the desired
operational mode.
9. Enable the selected sync/trigger source.
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REGISTER 14-1: ICxCON1: INPUT CAPTURE x CONTROL REGISTER 1
U-0
—
U-0
—
U-0
—
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
ICSIDL
ICTSEL2
ICTSEL1
ICTSEL0
bit 15
bit 8
U-0
—
R/W-0
ICI1
R/W-0
ICI0
R-0, HSC
ICOV
R-0, HSC
ICBNE
R/W-0
ICM2(1)
R/W-0
ICM1(1)
R/W-0
ICM0(1)
bit 7
bit 0
Legend:
HSC = Hardware Settable/Clearable bit
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-14
bit 13
Unimplemented: Read as ‘0’
ICSIDL: Input Capture x Module Stop in Idle Control bit
1= Input capture module Halts in CPU Idle mode
0= Input capture module continues to operate in CPU Idle mode
bit 12-10
ICTSEL<2:0>: Input Capture Timer Select bits
111= System clock (FOSC/2)
110= Reserved
101= Reserved
100= Timer1
011= Timer5
010= Timer4
001= Timer2
000= Timer3
bit 9-7
bit 6-5
Unimplemented: Read as ‘0’
ICI<1:0>: Select Number of Captures per Interrupt bits
11= Interrupt on every fourth capture event
10= Interrupt on every third capture event
01= Interrupt on every second capture event
00= Interrupt on every capture event
bit 4
ICOV: Input Capture x Overflow Status Flag bit (read-only)
1= Input capture overflow has occurred
0= No input capture overflow has occurred
bit 3
ICBNE: Input Capture x Buffer Empty Status bit (read-only)
1= Input capture buffer is not empty, at least one more capture value can be read
0= Input capture buffer is empty
bit 2-0
ICM<2:0>: Input Capture Mode Select bits(1)
111= Interrupt mode: input capture functions as an interrupt pin only when the device is in Sleep or
Idle mode (rising edge detect only, all other control bits are not applicable)
110= Unused (module is disabled)
101= Prescaler Capture mode: capture on every 16th rising edge
100= Prescaler Capture mode: capture on every 4th rising edge
011= Simple Capture mode: capture on every rising edge
010= Simple Capture mode: capture on every falling edge
001= Edge Detect Capture mode: capture on every edge (rising and falling); ICI<1:0> bits do not
control interrupt generation for this mode
000= Input capture module is turned off
Note 1: The ICx input must also be configured to an available RPn/RPIn pin. For more information, see
Section 11.4 “Peripheral Pin Select (PPS)”.
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REGISTER 14-2: ICxCON2: INPUT CAPTURE x CONTROL REGISTER 2
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
R/W-0
IC32
bit 15
bit 8
R/W-0
R/W-0 HS
TRIGSTAT
U-0
—
R/W-0
R/W-1
R/W-1
R/W-0
R/W-1
ICTRIG
SYNCSEL4 SYNCSEL3 SYNCSEL2 SYNCSEL1 SYNCSEL0
bit 0
bit 7
Legend:
HS = Hardware Settable bit
W = Writable bit
R = Readable bit
-n = Value at POR
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
‘1’ = Bit is set
bit 15-9
bit 8
Unimplemented: Read as ‘0’
IC32: Cascade Two IC Modules Enable bit (32-bit operation)
1= ICx and ICy operate in cascade as a 32-bit module (this bit must be set in both modules)
0= ICx functions independently as a 16-bit module
bit 7
bit 6
bit 5
ICTRIG: ICx Sync/Trigger Select bit
1= Trigger ICx from the source designated by the SYNCSELx bits
0= Synchronize ICx with the source designated by the SYNCSELx bits
TRIGSTAT: Timer Trigger Status bit
1= Timer source has been triggered and is running (set in hardware, can be set in software)
0= Timer source has not been triggered and is being held clear
Unimplemented: Read as ‘0’
Note 1: Use these inputs as trigger sources only and never as sync sources.
2: Never use an IC module as its own trigger source, by selecting this mode.
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REGISTER 14-2: ICxCON2: INPUT CAPTURE x CONTROL REGISTER 2 (CONTINUED)
bit 4-0
SYNCSEL<4:0>: Synchronization/Trigger Source Selection bits
11111= Reserved
11110= Reserved(2)
11101= Reserved(2)
11100= CTMU(1)
11011= A/D(1)
11010= Comparator 3(1)
11001= Comparator 2(1)
11000= Comparator 1(1)
10111= Reserved(2)
10110= Input Capture 7(2)
10101= Input Capture 6(2)
10100= Input Capture 5(2)
10011= Input Capture 4(2)
10010= Input Capture 3(2)
10001= Input Capture 2(2)
10000= Input Capture 1(2)
01111= Timer5
01110= Timer4
01101= Timer3
01100= Timer2
01011= Timer1
01010= Reserved
01001= Reserved
01000= Reserved
00111= Output Compare 7
•
•
•
00010= Output Compare 2
00001= Output Compare 1
00000= Not synchronized to any other module
Note 1: Use these inputs as trigger sources only and never as sync sources.
2: Never use an IC module as its own trigger source, by selecting this mode.
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NOTES:
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In Synchronous mode, the module begins performing
its compare or PWM operation as soon as its selected
clock source is enabled. Whenever an event occurs on
the selected sync source, the module’s internal counter
is reset. In Trigger mode, the module waits for a sync
event from another internal module to occur before
allowing the counter to run.
15.0 OUTPUT COMPARE WITH
DEDICATED TIMERS
Note:
This data sheet summarizes the features of
this group of PIC24F devices. It is not
intended to be a comprehensive reference
source. For more information, refer to the
“PIC24F Family Reference Manual”,
Section 35. “Output Compare with
Dedicated Timer” (DS39723). The infor-
mation in this data sheet supersedes the
information in the FRM.
Free-Running mode is selected by default or any time
that the SYNCSEL bits (OCxCON2<4:0>) are set to
‘00000’. Synchronous or Trigger modes are selected
any time the SYNCSEL bits are set to any value except
‘00000’. The OCTRIG bit (OCxCON2<7>) selects
either Synchronous or Trigger mode; setting the bit
selects Trigger mode operation. In both modes, the
SYNCSEL bits determine the sync/trigger source.
Devices in the PIC24FJ128GA310 family all feature
seven independent output compare modules. Each of
these modules offers a wide range of configuration and
operating options for generating pulse trains on internal
device events, and can produce pulse-width modulated
waveforms for driving power applications.
15.1.2
CASCADED (32-BIT) MODE
By default, each module operates independently with
its own set of 16-Bit Timer and Duty Cycle registers. To
increase resolution, adjacent even and odd modules
can be configured to function as a single 32-bit module.
(For example, Modules 1 and 2 are paired, as are
Modules 3 and 4, and so on.) The odd numbered
module (OCx) provides the Least Significant 16 bits of
the 32-bit register pairs and the even module (OCy)
provides the Most Significant 16 bits. Wrap-arounds of
the OCx registers cause an increment of their
corresponding OCy registers.
Key features of the output compare module include:
• Hardware configurable for 32-bit operation in all
modes by cascading two adjacent modules
• Synchronous and Trigger modes of output
compare operation, with up to 31 user-selectable
trigger/sync sources available
• Two separate Period registers (a main register,
OCxR, and a secondary register, OCxRS) for
greater flexibility in generating pulses of varying
widths
Cascaded operation is configured in hardware by set-
ting the OC32 bit (OCxCON2<8>) for both modules.
For more details on cascading, refer to the “PIC24F
Family Reference Manual”, Section 35. “Output
Compare with Dedicated Timer” (DS39723).
• Configurable for single pulse or continuous pulse
generation on an output event, or continuous
PWM waveform generation
• Up to 6 clock sources available for each module,
driving a separate internal 16-bit counter
15.1 General Operating Modes
15.1.1
SYNCHRONOUS AND TRIGGER
MODES
When the output compare module operates in a
Free-Running mode, the internal 16-bit counter,
OCxTMR, runs counts up continuously, wrapping
around from 0xFFFF to 0x0000 on each overflow. Its
period is synchronized to the selected external clock
source. Compare or PWM events are generated each
time a match between the internal counter and one of
the Period registers occurs.
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FIGURE 15-1:
OUTPUT COMPARE BLOCK DIAGRAM (16-BIT MODE)
OCMx
OCINV
OCxCON1
OCxCON2
OCTRIS
FLTOUT
FLTTRIEN
FLTMD
ENFLT<2:0>
OCFLT<2:0>
DCB<1:0>
OCTSELx
SYNCSELx
TRIGSTAT
TRIGMODE
OCTRIG
OCxR and
DCB<1:0>
OCx Pin(1)
Match Event
Match Event
Comparator
Increment
Clock
Select
OC Clock
Sources
OC Output and
OCxTMR
Comparator
OCxRS
Fault Logic
Reset
OCFA/OCFB(2)
Match Event
Trigger and
Sync Sources
Trigger and
Sync Logic
Reset
OCx Interrupt
Note 1: The OCx outputs must be assigned to an available RPn pin before use. See Section 11.4 “Peripheral Pin Select
(PPS)” for more information.
2: The OCFA/OCFB Fault inputs must be assigned to an available RPn/RPIn pin before use. See Section 11.4
“Peripheral Pin Select (PPS)” for more information.
3. Write the rising edge value to OCxR and the
15.2 Compare Operations
falling edge value to OCxRS.
In Compare mode (Figure 15-1), the output compare
4. Set the Timer Period register, PRy, to a value
module can be configured for single-shot or continuous
equal to or greater than the value in OCxRS.
pulse generation. It can also repeatedly toggle an
5. Set the OCM<2:0> bits for the appropriate
output pin on each timer event.
compare operation (= 0xx).
To set up the module for compare operations:
6. For Trigger mode operations, set OCTRIG to
1. Configure the OCx output for one of the
available Peripheral Pin Select pins.
enable Trigger mode. Set or clear TRIGMODE
to configure trigger operation and TRIGSTAT to
select a hardware or software trigger. For
Synchronous mode, clear OCTRIG.
2. Calculate the required values for the OCxR and
(for Double Compare modes) OCxRS Duty
Cycle registers:
7. Set the SYNCSEL<4:0> bits to configure the
trigger or synchronization source. If free-running
timer operation is required, set the SYNCSEL
bits to ‘00000’ (no sync/trigger source).
a) Determine the instruction clock cycle time.
Take into account the frequency of the
external clock to the timer source (if one is
used) and the timer prescaler settings.
8. Select the time base source with the
OCTSEL<2:0> bits. If necessary, set the TON
bits for the selected timer, which enables the
compare time base to count. Synchronous
mode operation starts as soon as the time base
is enabled; Trigger mode operation starts after a
trigger source event occurs.
b) Calculate time to the rising edge of the
output pulse relative to the timer start value
(0000h).
c) Calculate the time to the falling edge of the
pulse based on the desired pulse width and
the time to the rising edge of the pulse.
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For 32-bit cascaded operation, these steps are also
necessary:
15.3 Pulse-Width Modulation (PWM)
Mode
1. Set the OC32 bits for both registers
(OCyCON2<8>) and (OCxCON2<8>). Enable
the even numbered module first to ensure the
modules will start functioning in unison.
In PWM mode, the output compare module can be
configured for edge-aligned or center-aligned pulse
waveform generation. All PWM operations are
double-buffered (buffer registers are internal to the
module and are not mapped into SFR space).
2. Clear the OCTRIG bit of the even module
(OCyCON2<7>), so the module will run in
Synchronous mode.
To configure the output compare module for PWM
operation:
3. Configure the desired output and Fault settings
for OCy.
1. Configure the OCx output for one of the
available Peripheral Pin Select pins.
4. Force the output pin for OCx to the output state
by clearing the OCTRIS bit.
2. Calculate the desired duty cycles and load them
into the OCxR register.
5. If Trigger mode operation is required, configure
the trigger options in OCx by using the OCTRIG
(OCxCON2<7>), TRIGMODE (OCxCON1<3>)
and SYNCSEL (OCxCON2<4:0>) bits.
3. Calculate the desired period and load it into the
OCxRS register.
4. Select the current OCx as the synchronization
source by writing 0x1F to the SYNCSEL<4:0>
bits (OCxCON2<4:0>) and ‘0’ to the OCTRIG bit
(OCxCON2<7>).
6. Configure the desired Compare or PWM mode
of operation (OCM<2:0>) for OCy first, then for
OCx.
5. Select
a clock source by writing to the
Depending on the output mode selected, the module
holds the OCx pin in its default state and forces a tran-
sition to the opposite state when OCxR matches the
timer. In Double Compare modes, OCx is forced back
to its default state when a match with OCxRS occurs.
The OCxIF interrupt flag is set after an OCxR match in
Single Compare modes and after each OCxRS match
in Double Compare modes.
OCTSEL<2:0> bits (OCxCON<12:10>).
6. Enable interrupts, if required, for the timer and
output compare modules. The output compare
interrupt is required for PWM Fault pin
utilization.
7. Select the desired PWM mode in the OCM<2:0>
bits (OCxCON1<2:0>).
Single-shot pulse events only occur once, but may be
repeated by simply rewriting the value of the
OCxCON1 register. Continuous pulse events continue
indefinitely until terminated.
8. Appropriate Fault inputs may be enabled by
using the ENFLT<2:0> bits as described in
Register 15-1.
9. If a timer is selected as a clock source, set the
selected timer prescale value. The selected
timer’s prescaler output is used as the clock
input for the OCx timer, and not the selected
timer output.
Note:
This peripheral contains input and output
functions that may need to be configured
by the Peripheral Pin Select. See
Section 11.4 “Peripheral Pin Select
(PPS)” for more information.
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FIGURE 15-2:
OUTPUT COMPARE BLOCK DIAGRAM (DOUBLE-BUFFERED, 16-BIT PWM MODE)
OCxCON1
OCxCON2
OCMx
OCINV
OCTSELx
OCTRIS
FLTOUT
OCxR and
DCB<1:0>
SYNCSELx
TRIGSTAT
TRIGMODE
OCTRIG
FLTTRIEN
FLTMD
ENFLT<2:0>
OCFLT<2:0>
DCB<1:0>
Rollover/Reset
OCxR and
DCB<1:0> Buffers
OCx Pin(1)
Comparator
Match
Event
Increment
Clock
Select
OC Clock
Sources
OC Output and
Fault Logic
OCxTMR
Comparator
OCxRS Buffer
Rollover
Reset
OCFA/OCFB(2)
Match
Event
Match Event
Trigger and
Sync Logic
Trigger and
Sync Sources
Rollover/Reset
OCxRS
OCx Interrupt
Reset
Note 1: The OCx outputs must be assigned to an available RPn pin before use. See Section 11.4 “Peripheral Pin Select
(PPS)” for more information.
2: The OCFA/OCFB Fault inputs must be assigned to an available RPn/RPIn pin before use. See Section 11.4
“Peripheral Pin Select (PPS)” for more information.
15.3.1
PWM PERIOD
The PWM period is specified by writing to PRy, the
Timer Period register. The PWM period can be
calculated using Equation 15-1.
EQUATION 15-1: CALCULATING THE PWM PERIOD(1)
PWM Period = [(PRy) + 1 • TCY • (Timer Prescale Value)
where:
PWM Frequency = 1/[PWM Period]
Note 1: Based on TCY = TOSC * 2; Doze mode and PLL are disabled.
Note:
A PRy value of N will produce a PWM period of N + 1 time base count cycles. For example, a value of
7, written into the PRy register, will yield a period consisting of 8 time base cycles.
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• If OCxR, OCxRS, and PRy are all loaded with
0000h, the OCx pin will remain low (0% duty
cycle).
15.3.2
PWM DUTY CYCLE
The PWM duty cycle is specified by writing to the
OCxRS and OCxR registers. The OCxRS and OCxR
registers can be written to at any time, but the duty
cycle value is not latched until a match between PRy
and TMRy occurs (i.e., the period is complete). This
provides a double buffer for the PWM duty cycle and is
essential for glitchless PWM operation.
• If OCxRS is greater than PRy, the pin will remain
high (100% duty cycle).
See Example 15-1 for PWM mode timing details.
Table 15-1 and Table 15-2 show example PWM
frequencies and resolutions for a device operating at
4 MIPS and 10 MIPS, respectively.
Some important boundary parameters of the PWM duty
cycle include:
EQUATION 15-2: CALCULATION FOR MAXIMUM PWM RESOLUTION(1)
FCY
log10
FPWM • (Timer Prescale Value)
(
)
Maximum PWM Resolution (bits) =
bits
(2)
log10
Note 1: Based on FCY = FOSC/2; Doze mode and PLL are disabled.
EXAMPLE 15-1:
PWM PERIOD AND DUTY CYCLE CALCULATIONS(1)
1. Find the Timer Period register value for a desired PWM frequency of 52.08 kHz, where FOSC = 8 MHz with PLL
(32 MHz device clock rate) and a Timer2 prescaler setting of 1:1.
TCY = 2 * TOSC = 62.5 ns
PWM Period = 1/PWM Frequency = 1/52.08 kHz = 19.2 ms
PWM Period = (PR2 + 1) • TCY • (Timer2 Prescale Value)
19.2 ms = PR2 + 1) • 62.5 ns • 1
PR2 = 306
2. Find the maximum resolution of the duty cycle that can be used with a 52.08 kHz frequency and a 32 MHz
device clock rate:
PWM Resolution = log10(FCY/FPWM)/log102) bits
= (log10(16 MHz/52.08 kHz)/log102) bits
= 8.3 bits
Note 1: Based on TCY = 2 * TOSC; Doze mode and PLL are disabled.
TABLE 15-1: EXAMPLE PWM FREQUENCIES AND RESOLUTIONS AT 4 MIPS (FCY = 4 MHz)(1)
PWM Frequency
7.6 Hz
61 Hz
122 Hz
977 Hz
3.9 kHz
31.3 kHz
125 kHz
Timer Prescaler Ratio
Period Register Value
Resolution (bits)
8
1
FFFFh
16
1
1
1
1
007Fh
7
1
001Fh
5
FFFFh
16
7FFFh
15
0FFFh
12
03FFh
10
Note 1: Based on FCY = FOSC/2; Doze mode and PLL are disabled.
TABLE 15-2: EXAMPLE PWM FREQUENCIES AND RESOLUTIONS AT 16 MIPS (FCY = 16 MHz)(1)
PWM Frequency
30.5 Hz
244 Hz
488 Hz
3.9 kHz
15.6 kHz
125 kHz
500 kHz
Timer Prescaler Ratio
Period Register Value
Resolution (bits)
8
1
FFFFh
16
1
1
1
1
007Fh
7
1
001Fh
5
FFFFh
16
7FFFh
15
0FFFh
12
03FFh
10
Note 1: Based on FCY = FOSC/2; Doze mode and PLL are disabled.
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REGISTER 15-1: OCxCON1: OUTPUT COMPARE x CONTROL REGISTER 1
U-0
—
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
ENFLT2(2)
R/W-0
ENFLT1(2)
OCSIDL
OCTSEL2
OCTSEL1
OCTSEL0
bit 15
bit 8
R/W-0
R/W-0, HSC R/W-0, HSC R/W-0, HSC
R/W-0
R/W-0
R/W-0
R/W-0
ENFLT0(2) OCFLT2(2,3) OCFLT1(2,4) OCFLT0(2,4) TRIGMODE
OCM2(1)
OCM1(1)
OCM0(1)
bit 7
bit 0
Legend:
HSC = Hardware Settable/Clearable bit
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-14
bit 13
Unimplemented: Read as ‘0’
OCSIDL: Stop Output Compare x in Idle Mode Control bit
1= Output Compare x Halts in CPU Idle mode
0= Output Compare x continues to operate in CPU Idle mode
bit 12-10
OCTSEL<2:0>: Output Compare x Timer Select bits
111= Peripheral clock (FCY)
110= Reserved
101= Reserved
100= Timer1 clock (only synchronous clock is supported)
011= Timer5 clock
010= Timer4 clock
001= Timer3 clock
000= Timer2 clock
bit 9
bit 8
bit 7
bit 6
bit 5
ENFLT2: Fault Input 2 Enable bit(2)
1= Fault 2 (Comparator 1/2/3 out) is enabled(3)
0= Fault 2 is disabled
ENFLT1: Fault Input 1 Enable bit(2)
1= Fault 1 (OCFB pin) is enabled(4)
0= Fault 1 is disabled
ENFLT0: Fault Input 0 Enable bit(2)
1= Fault 0 (OCFA pin) is enabled(4)
0= Fault 0 is disabled
OCFLT2: PWM Fault 2 (Comparator 1/2/3) Condition Status bit(2,3)
1= PWM Fault 2 has occurred
0= No PWM Fault 2 has occurred
OCFLT1: PWM Fault 1 (OCFB pin) Condition Status bit(2,4)
1= PWM Fault 1 has occurred
0= No PWM Fault 1 has occurred
Note 1: The OCx output must also be configured to an available RPn pin. For more information, see Section 11.4
“Peripheral Pin Select (PPS)”.
2: The Fault input enable and Fault status bits are valid when OCM<2:0> = 111or 110.
3: The Comparator 1 output controls the OC1-OC3 channels; Comparator 2 output controls the OC4-OC6
channels; Comparator 3 output controls the OC7-OC9 channels.
4: The OCFA/OCFB Fault input must also be configured to an available RPn/RPIn pin. For more information,
see Section 11.4 “Peripheral Pin Select (PPS)”.
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REGISTER 15-1: OCxCON1: OUTPUT COMPARE x CONTROL REGISTER 1 (CONTINUED)
bit 4
OCFLT0: PWM Fault 0 (OCFA pin) Condition Status bit(2,4)
1= PWM Fault 0 has occurred
0= No PWM Fault 0 has occurred
bit 3
TRIGMODE: Trigger Status Mode Select bit
1= TRIGSTAT (OCxCON2<6>) is cleared when OCxRS = OCxTMR or in software
0= TRIGSTAT is only cleared by software
bit 2-0
OCM<2:0>: Output Compare x Mode Select bits(1)
111= Center-Aligned PWM mode on OCx(2)
110= Edge-Aligned PWM mode on OCx(2)
101= Double Compare Continuous Pulse mode: Initialize the OCx pin low; toggle the OCx state
continuously on alternate matches of OCxR and OCxRS
100= Double Compare Single-Shot mode: Initialize the OCx pin low; toggle the OCx state on matches
of OCxR and OCxRS for one cycle
011= Single Compare Continuous Pulse mode: Compare events continuously toggle the OCx pin
010= Single Compare Single-Shot mode: Initialize OCx pin high; compare event forces the OCx pin low
001= Single Compare Single-Shot mode: Initialize OCx pin low; compare event forces the OCx pin high
000= Output compare channel is disabled
Note 1: The OCx output must also be configured to an available RPn pin. For more information, see Section 11.4
“Peripheral Pin Select (PPS)”.
2: The Fault input enable and Fault status bits are valid when OCM<2:0> = 111or 110.
3: The Comparator 1 output controls the OC1-OC3 channels; Comparator 2 output controls the OC4-OC6
channels; Comparator 3 output controls the OC7-OC9 channels.
4: The OCFA/OCFB Fault input must also be configured to an available RPn/RPIn pin. For more information,
see Section 11.4 “Peripheral Pin Select (PPS)”.
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REGISTER 15-2: OCxCON2: OUTPUT COMPARE x CONTROL REGISTER 2
R/W-0
R/W-0
R/W-0
R/W-0
U-0
—
R/W-0
DCB1(3)
R/W-0
DCB0(3)
R/W-0
OC32
FLTMD
FLTOUT
FLTTRIEN
OCINV
bit 15
bit 8
R/W-0
R/W-0 HS
TRIGSTAT
R/W-0
R/W-0
R/W-1
R/W-1
R/W-0
R/W-0
OCTRIG
OCTRIS
SYNCSEL4 SYNCSEL3 SYNCSEL2 SYNCSEL1 SYNCSEL0
bit 0
bit 7
Legend:
HS = Hardware Settable bit
W = Writable bit
R = Readable bit
-n = Value at POR
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
‘1’ = Bit is set
bit 15
FLTMD: Fault Mode Select bit
1= Fault mode is maintained until the Fault source is removed and the corresponding OCFLT0 bit is
cleared in software
0= Fault mode is maintained until the Fault source is removed and a new PWM period starts
bit 14
bit 13
bit 12
FLTOUT: Fault Out bit
1= PWM output is driven high on a Fault
0= PWM output is driven low on a Fault
FLTTRIEN: Fault Output State Select bit
1= Pin is forced to an output on a Fault condition
0= Pin I/O condition is unaffected by a Fault
OCINV: OCMP Invert bit
1= OCx output is inverted
0= OCx output is not inverted
bit 11
Unimplemented: Read as ‘0’
bit 10-9
DCB<11:0>: PWM Duty Cycle Least Significant bits(3)
11= Delay OCx falling edge by ¾ of the instruction cycle
10= Delay OCx falling edge by ½ of the instruction cycle
01= Delay OCx falling edge by ¼ of the instruction cycle
00= OCx falling edge occurs at the start of the instruction cycle
bit 8
bit 7
bit 6
bit 5
OC32: Cascade Two OC Modules Enable bit (32-bit operation)
1= Cascade module operation is enabled
0= Cascade module operation is disabled
OCTRIG: OCx Trigger/Sync Select bit
1= Trigger OCx from the source designated by the SYNCSELx bits
0= Synchronize OCx with the source designated by the SYNCSELx bits
TRIGSTAT: Timer Trigger Status bit
1= Timer source has been triggered and is running
0= Timer source has not been triggered and is being held clear
OCTRIS: OCx Output Pin Direction Select bit
1= OCx pin is tri-stated
0= Output compare peripheral x is connected to an OCx pin
Note 1: Never use an OC module as its own trigger source, either by selecting this mode or another equivalent
SYNCSELx setting.
2: Use these inputs as trigger sources only and never as sync sources.
3: The DCB<1:0> bits are double-buffered in the PWM modes only (OCM<2:0> (OCxCON1<2:0>) = 111, 110).
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REGISTER 15-2: OCxCON2: OUTPUT COMPARE x CONTROL REGISTER 2 (CONTINUED)
bit 4-0
SYNCSEL<4:0>: Trigger/Synchronization Source Selection bits
11111= This OC module(1)
11110= Input Capture 9(2)
11101= Input Capture 6(2)
11100= CTMU(2)
11011= A/D(2)
11010= Comparator 3(2)
11001= Comparator 2(2)
11000= Comparator 1(2)
10111= Input Capture 4(2)
10110= Input Capture 3(2)
10101= Input Capture 2(2)
10100= Input Capture 1(2)
10011= Input Capture 8(2)
10010= Input Capture 7(2)
1000x= Reserved
01111= Timer5
01110= Timer4
01101= Timer3
01100= Timer2
01011= Timer1
01010= Input Capture 5(2)
01001= Output Compare 9(1)
01000= Output Compare 8(1)
00111= Output Compare 7(1)
00110= Output Compare 6(1)
00101= Output Compare 5(1)
00100= Output Compare 4(1)
00011= Output Compare 3(1)
00010= Output Compare 2(1)
00001= Output Compare 1(1)
00000= Not synchronized to any other module
Note 1: Never use an OC module as its own trigger source, either by selecting this mode or another equivalent
SYNCSELx setting.
2: Use these inputs as trigger sources only and never as sync sources.
3: The DCB<1:0> bits are double-buffered in the PWM modes only (OCM<2:0> (OCxCON1<2:0>) = 111, 110).
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NOTES:
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The module also supports a basic framed SPI protocol
while operating in either Master or Slave mode. A total
of four framed SPI configurations are supported.
16.0 SERIAL PERIPHERAL
INTERFACE (SPI)
Note:
This data sheet summarizes the features of
this group of PIC24F devices. It is not
The SPI serial interface consists of four pins:
• SDIx: Serial Data Input
intended to be a comprehensive reference
source. For more information, refer to the
“PIC24F Family Reference Manual”,
Section 23. “Serial Peripheral Interface
(SPI)” (DS39699). The information in this
data sheet supersedes the information in
the FRM.
• SDOx: Serial Data Output
• SCKx: Shift Clock Input or Output
• SSx: Active-Low Slave Select or Frame
Synchronization I/O Pulse
The SPI module can be configured to operate using 2,
3 or 4 pins. In the 3-pin mode, SSx is not used. In the
2-pin mode, both SDOx and SSx are not used.
The Serial Peripheral Interface (SPI) module is a
synchronous serial interface useful for communicating
with other peripheral or microcontroller devices. These
peripheral devices may be serial EEPROMs, shift
registers, display drivers, A/D Converters, etc. The SPI
module is compatible with the SPI and SIOP Motorola®
interfaces. All devices of the PIC24FJ128GA310 family
include two SPI modules.
Block diagrams of the module in Standard and
Enhanced modes are shown in Figure 16-1 and
Figure 16-2.
Note:
In this section, the SPI modules are
referred to together as SPIx or separately
as SPI1, SPI2 or SPI3. Special Function
Registers will follow a similar notation. For
example, SPIxCON1 and SPIxCON2
refer to the control registers for any of the
3 SPI modules.
The module supports operation in two buffer modes. In
Standard mode, data is shifted through a single serial
buffer. In Enhanced Buffer mode, data is shifted
through an 8-level FIFO buffer.
Note:
Do not perform read-modify-write opera-
tions (such as bit-oriented instructions) on
the SPIxBUF register in either Standard or
Enhanced Buffer mode.
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To set up the SPI module for the Standard Master mode
of operation:
To set up the SPI module for the Standard Slave mode
of operation:
1. If using interrupts:
1. Clear the SPIxBUF register.
2. If using interrupts:
a) Clear the SPIxIF bit in the respective IFS
register.
a) Clear the SPIxIF bit in the respective IFS
register.
b) Set the SPIxIE bit in the respective IEC
register.
b) Set the SPIxIE bit in the respective IEC
register.
c) Write the SPIxIP bits in the respective IPC
register to set the interrupt priority.
c) Write the SPIxIP bits in the respective IPC
register to set the interrupt priority.
2. Write the desired settings to the SPIxCON1
and SPIxCON2 registers with MSTEN
(SPIxCON1<5>) = 1.
3. Write the desired settings to the SPIxCON1
and SPIxCON2 registers with MSTEN
(SPIxCON1<5>) = 0.
3. Clear the SPIROV bit (SPIxSTAT<6>).
4. Enable SPI operation by setting the SPIEN bit
(SPIxSTAT<15>).
4. Clear the SMP bit.
5. If the CKE bit (SPIxCON1<8>) is set, then the
SSEN bit (SPIxCON1<7>) must be set to enable
the SSx pin.
5. Write the data to be transmitted to the SPIxBUF
register. Transmission (and reception) will start
as soon as data is written to the SPIxBUF
register.
6. Clear the SPIROV bit (SPIxSTAT<6>).
7. Enable SPI operation by setting the SPIEN bit
(SPIxSTAT<15>).
FIGURE 16-1:
SPIx MODULE BLOCK DIAGRAM (STANDARD MODE)
SCKx
1:1 to 1:8
Secondary
Prescaler
1:1/4/16/64
Primary
Prescaler
FCY
SSx/FSYNCx
Sync
Control
Clock
Select
Edge
Control
SPIxCON1<1:0>
SPIxCON1<4:2>
Shift Control
SDOx
SDIx
Enable
Master Clock
bit 0
SPIxSR
Transfer
Transfer
SPIxBUF
Write SPIxBUF
Read SPIxBUF
16
Internal Data Bus
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To set up the SPI module for the Enhanced Buffer
Master mode of operation:
To set up the SPI module for the Enhanced Buffer
Slave mode of operation:
1. If using interrupts:
1. Clear the SPIxBUF register.
2. If using interrupts:
a) Clear the SPIxIF bit in the respective IFS
register.
a) Clear the SPIxIF bit in the respective IFS
register.
b) Set the SPIxIE bit in the respective IEC
register.
b) Set the SPIxIE bit in the respective IEC
register.
c) Write the SPIxIP bits in the respective IPC
register.
c) Write the SPIxIP bits in the respective IPC
register to set the interrupt priority.
2. Write the desired settings to the SPIxCON1
and SPIxCON2 registers with MSTEN
(SPIxCON1<5>) = 1.
3. Write the desired settings to the SPIxCON1
and SPIxCON2 registers with MSTEN
(SPIxCON1<5>) = 0.
3. Clear the SPIROV bit (SPIxSTAT<6>).
4. Select Enhanced Buffer mode by setting the
SPIBEN bit (SPIxCON2<0>).
4. Clear the SMP bit.
5. If the CKE bit is set, then the SSEN bit must be
set, thus enabling the SSx pin.
5. Enable SPI operation by setting the SPIEN bit
(SPIxSTAT<15>).
6. Clear the SPIROV bit (SPIxSTAT<6>).
6. Write the data to be transmitted to the SPIxBUF
register. Transmission (and reception) will start
as soon as data is written to the SPIxBUF
register.
7. Select Enhanced Buffer mode by setting the
SPIBEN bit (SPIxCON2<0>).
8. Enable SPI operation by setting the SPIEN bit
(SPIxSTAT<15>).
FIGURE 16-2:
SPIx MODULE BLOCK DIAGRAM (ENHANCED MODE)
SCKx
1:1/4/16/64
Primary
1:1 to 1:8
Secondary
Prescaler
FCY
Prescaler
SSx/FSYNCx
Sync
Select
Edge
Control
Clock
Control
SPIxCON1<1:0>
SPIxCON1<4:2>
Shift Control
SDOx
SDIx
Enable
Master Clock
bit 0
SPIxSR
Transfer
Transfer
8-Level FIFO
Receive Buffer
8-Level FIFO
Transmit Buffer
SPIXBUF
Write SPIxBUF
Read SPIxBUF
16
Internal Data Bus
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REGISTER 16-1: SPIxSTAT: SPIx STATUS AND CONTROL REGISTER
R/W-0
SPIEN(1)
U-0
—
R/W-0
U-0
—
U-0
—
R-0, HSC
SPIBEC2
R-0, HSC
SPIBEC1
R-0, HSC
SPIBEC0
SPISIDL
bit 15
bit 8
R-0, HSC
SRMPT
R/C-0, HS
SPIROV
R-0, HSC
SRXMPT
R/W-0
R/W-0
R/W-0
R-0, HSC
SPITBF
R-0, HSC
SPIRBF
SISEL2
SISEL1
SISEL0
bit 7
bit 0
Legend:
C = Clearable bit
W = Writable bit
‘1’ = Bit is set
HS = Hardware Settable bit
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
R = Readable bit
-n = Value at POR
HSC = Hardware Settable/Clearable bit
bit 15
SPIEN: SPIx Enable bit(1)
1= Enables module and configures SCKx, SDOx, SDIx and SSx as serial port pins
0= Disables module
bit 14
bit 13
Unimplemented: Read as ‘0’
SPISIDL: Stop in Idle Mode bit
1= Discontinue module operation when device enters Idle mode
0= Continue module operation in Idle mode
bit 12-11
bit 10-8
Unimplemented: Read as ‘0’
SPIBEC<2:0>: SPIx Buffer Element Count bits (valid in Enhanced Buffer mode)
Master mode:
Number of SPI transfers pending.
Slave mode:
Number of SPI transfers unread.
bit 7
bit 6
SRMPT: Shift Register (SPIxSR) Empty bit (valid in Enhanced Buffer mode)
1= SPIx Shift register is empty and ready to send or receive
0= SPIx Shift register is not empty
SPIROV: Receive Overflow Flag bit
1= A new byte/word is completely received and discarded
The user software has not read the previous data in the SPIxBUF register.
0= No overflow has occurred
bit 5
SRXMPT: Receive FIFO Empty bit (valid in Enhanced Buffer mode)
1= Receive FIFO is empty
0= Receive FIFO is not empty
bit 4-2
SISEL<2:0>: SPIx Buffer Interrupt Mode bits (valid in Enhanced Buffer mode)
111= Interrupt when the SPIx transmit buffer is full (SPITBF bit is set)
110= Interrupt when the last bit is shifted into SPIxSR; as a result, the TX FIFO is empty
101= Interrupt when the last bit is shifted out of SPIxSR; now the transmit is complete
100= Interrupt when one data is shifted into the SPIxSR; as a result, the TX FIFO has one open spot
011= Interrupt when the SPIx receive buffer is full (SPIRBF bit is set)
010= Interrupt when the SPIx receive buffer is 3/4 or more full
001= Interrupt when data is available in the receive buffer (SRMPT bit is set)
000= Interrupt when the last data in the receive buffer is read; as a result, the buffer is empty (SRXMPT
bit is set)
Note 1: If SPIEN = 1, these functions must be assigned to available RPn/RPIn pins before use. See Section 11.4
“Peripheral Pin Select (PPS)” for more information.
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REGISTER 16-1: SPIxSTAT: SPIx STATUS AND CONTROL REGISTER (CONTINUED)
bit 1
SPITBF: SPIx Transmit Buffer Full Status bit
1= Transmit has not yet started, SPIxTXB is full
0= Transmit has started, SPIxTXB is empty
In Standard Buffer mode:
Automatically set in hardware when the CPU writes to the SPIxBUF location, loading the SPIxTXB.
Automatically cleared in hardware when the SPIx module transfers data from SPIxTXB to SPIxSR.
In Enhanced Buffer mode:
Automatically set in hardware when the CPU writes to the SPIxBUF location, loading the last available
buffer location. Automatically cleared in hardware when a buffer location is available for a CPU write.
bit 0
SPIRBF: SPIx Receive Buffer Full Status bit
1= Receive is complete, SPIxRXB is full
0= Receive is not complete, SPIxRXB is empty
In Standard Buffer mode:
Automatically set in hardware when SPIx transfers data from SPIxSR to SPIxRXB. Automatically
cleared in hardware when the core reads the SPIxBUF location, reading SPIxRXB.
In Enhanced Buffer mode:
Automatically set in hardware when SPIx transfers data from the SPIxSR to the buffer, filling the last
unread buffer location. Automatically cleared in hardware when a buffer location is available for a trans-
fer from SPIxSR.
Note 1: If SPIEN = 1, these functions must be assigned to available RPn/RPIn pins before use. See Section 11.4
“Peripheral Pin Select (PPS)” for more information.
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REGISTER 16-2: SPIXCON1: SPIx CONTROL REGISTER 1
U-0
—
U-0
—
U-0
—
R/W-0
DISSCK(1)
R/W-0
DISSDO(2)
R/W-0
R/W-0
SMP
R/W-0
CKE(3)
MODE16
bit 15
bit 8
R/W-0
SSEN(4)
R/W-0
CKP
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
MSTEN
SPRE2
SPRE1
SPRE0
PPRE1
PPRE0
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-13
bit 12
Unimplemented: Read as ‘0’
DISSCK: Disable SCKx Pin bit (SPI Master modes only)(1)
1= Internal SPI clock is disabled; pin functions as I/O
0= Internal SPI clock is enabled
bit 11
bit 10
bit 9
DISSDO: Disable SDOx Pin bit(2)
1= SDOx pin is not used by the module; pin functions as I/O
0= SDOx pin is controlled by the module
MODE16: Word/Byte Communication Select bit
1= Communication is word-wide (16 bits)
0= Communication is byte-wide (8 bits)
SMP: SPIx Data Input Sample Phase bit
Master mode:
1= Input data is sampled at the end of data output time
0= Input data is sampled at the middle of data output time
Slave mode:
SMP must be cleared when SPIx is used in Slave mode.
bit 8
bit 7
bit 6
bit 5
CKE: SPIx Clock Edge Select bit(3)
1= Serial output data changes on transition from active clock state to Idle clock state (see bit 6)
0= Serial output data changes on transition from Idle clock state to active clock state (see bit 6)
SSEN: Slave Select Enable (Slave mode) bit(4)
1= SSx pin is used for Slave mode
0= SSx pin is not used by the module; pin is controlled by the port function
CKP: Clock Polarity Select bit
1= Idle state for the clock is a high level; active state is a low level
0= Idle state for the clock is a low level; active state is a high level
MSTEN: Master Mode Enable bit
1= Master mode
0= Slave mode
Note 1: If DISSCK = 0, SCKx must be configured to an available RPn pin. See Section 11.4 “Peripheral Pin
Select (PPS)” for more information.
2: If DISSDO = 0, SDOx must be configured to an available RPn pin. See Section 11.4 “Peripheral Pin
Select (PPS)” for more information.
3: The CKE bit is not used in the Framed SPI modes. The user should program this bit to ‘0’ for the Framed
SPI modes (FRMEN = 1).
4: If SSEN = 1, SSx must be configured to an available RPn/PRIn pin. See Section 11.4 “Peripheral Pin
Select (PPS)” for more information.
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REGISTER 16-2: SPIXCON1: SPIx CONTROL REGISTER 1 (CONTINUED)
bit 4-2 SPRE<2:0>: Secondary Prescale bits (Master mode)
111= Secondary prescale 1:1
110= Secondary prescale 2:1
.
.
.
000= Secondary prescale 8:1
bit 1-0
PPRE<1:0>: Primary Prescale bits (Master mode)
11= Primary prescale 1:1
10= Primary prescale 4:1
01= Primary prescale 16:1
00= Primary prescale 64:1
Note 1: If DISSCK = 0, SCKx must be configured to an available RPn pin. See Section 11.4 “Peripheral Pin
Select (PPS)” for more information.
2: If DISSDO = 0, SDOx must be configured to an available RPn pin. See Section 11.4 “Peripheral Pin
Select (PPS)” for more information.
3: The CKE bit is not used in the Framed SPI modes. The user should program this bit to ‘0’ for the Framed
SPI modes (FRMEN = 1).
4: If SSEN = 1, SSx must be configured to an available RPn/PRIn pin. See Section 11.4 “Peripheral Pin
Select (PPS)” for more information.
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REGISTER 16-3: SPIxCON2: SPIx CONTROL REGISTER 2
R/W-0
R/W-0
R/W-0
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
FRMEN
SPIFSD
SPIFPOL
bit 15
bit 8
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
R/W-0
SPIFE
R/W-0
SPIBEN
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
-n = Value at POR
bit 15
bit 14
bit 13
FRMEN: Framed SPIx Support bit
1= Framed SPIx support is enabled
0= Framed SPIx support is disabled
SPIFSD: Frame Sync Pulse Direction Control on SSx Pin bit
1= Frame sync pulse input (slave)
0= Frame sync pulse output (master)
SPIFPOL: Frame Sync Pulse Polarity bit (Frame mode only)
1= Frame sync pulse is active-high
0= Frame sync pulse is active-low
bit 12-2
bit 1
Unimplemented: Read as ‘0’
SPIFE: Frame Sync Pulse Edge Select bit
1= Frame sync pulse coincides with the first bit clock
0= Frame sync pulse precedes the first bit clock
bit 0
SPIBEN: Enhanced Buffer Enable bit
1= Enhanced buffer is enabled
0= Enhanced buffer is disabled (Legacy mode)
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FIGURE 16-3:
SPI MASTER/SLAVE CONNECTION (STANDARD MODE)
Processor 1 (SPI Master)
Processor 2 (SPI Slave)
SDOx
SDIx
Serial Receive Buffer
(SPIxRXB)
Serial Receive Buffer
(2)
(SPIxRXB)
SDIx
SDOx
Shift Register
(SPIxSR)
Shift Register
(SPIxSR)
(2)
LSb
MSb
MSb
LSb
Serial Transmit Buffer
(SPIxTXB)
Serial Transmit Buffer
(2)
(SPIxTXB)
Serial Clock
SCKx
SCKx
SPIx Buffer
(SPIxBUF)
SPIx Buffer
(SPIxBUF)
(2)
(2)
(1)
SSx
SSEN (SPIxCON1<7>) = 1and MSTEN (SPIxCON1<5>) = 0
MSTEN (SPIxCON1<5>) = 1)
Note 1: Using the SSx pin in Slave mode of operation is optional.
2: User must write transmit data to read the received data from SPIxBUF. The SPIxTXB and SPIxRXB registers
are memory mapped to SPIxBUF.
FIGURE 16-4:
SPI MASTER/SLAVE CONNECTION (ENHANCED BUFFER MODES)
Processor 1 (SPI Enhanced Buffer Master)
Processor 2 (SPI Enhanced Buffer Slave)
SDIx
SDOx
SDIx
SDOx
Shift Register
(SPIxSR)
Shift Register
(SPIxSR)
LSb
MSb
MSb
LSb
8-Level FIFO Buffer
8-Level FIFO Buffer
Serial Clock
SPIx Buffer
SPIx Buffer
(SPIxBUF)
(2)
SCKx
SSx
SCKx
(2)
(SPIxBUF)
(1)
SSx
MSTEN (SPIxCON1<5>) = 1and
SPIBEN (SPIxCON2<0>) = 1
SSEN (SPIxCON1<7>) = 1,
MSTEN (SPIxCON1<5>) = 0and
SPIBEN (SPIxCON2<0>) = 1
Note 1: Using the SSx pin in Slave mode of operation is optional.
2: User must write transmit data to read the received data from SPIxBUF. The SPIxTXB and SPIxRXB registers are
memory mapped to SPIxBUF.
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FIGURE 16-5:
FIGURE 16-6:
FIGURE 16-7:
FIGURE 16-8:
SPI MASTER, FRAME MASTER CONNECTION DIAGRAM
PIC24F
Processor 2
(SPI Master, Frame Master)
SDOx
SDIx
SDIx
SDOx
Serial Clock
SCKx
SSx
SCKx
SSx
Frame Sync
Pulse
SPI MASTER, FRAME SLAVE CONNECTION DIAGRAM
PIC24F
Processor 2
SPI Master, Frame Slave)
SDOx
SDIx
SDIx
SDOx
Serial Clock
SCKx
SSx
SCKx
SSx
Frame Sync
Pulse
SPI SLAVE, FRAME MASTER CONNECTION DIAGRAM
PIC24F
(SPI Slave, Frame Master)
Processor 2
SDOx
SDIx
SDIx
SDOx
Serial Clock
SCKx
SSx
SCKx
SSx
Frame Sync.
Pulse
SPI SLAVE, FRAME SLAVE CONNECTION DIAGRAM
PIC24F
(SPI Slave, Frame Slave)
Processor 2
SDOx
SDIx
SDIx
SDOx
Serial Clock
SCKx
SSx
SCKx
SSx
Frame Sync
Pulse
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EQUATION 16-1: RELATIONSHIP BETWEEN DEVICE AND SPI CLOCK SPEED(1)
FCY
FSCK =
Primary Prescaler x Secondary Prescaler
Note 1: Based on FCY = FOSC/2; Doze mode and PLL are disabled.
TABLE 16-1: SAMPLE SCKx FREQUENCIES(1,2)
Secondary Prescaler Settings
FCY = 16 MHz
1:1
2:1
4:1
6:1
8:1
1:1
4:1
Invalid
4000
1000
250
8000
2000
500
4000
1000
250
63
2667
667
167
42
2000
500
125
31
Primary Prescaler Settings
FCY = 5 MHz
16:1
64:1
125
1:1
4:1
5000
1250
313
78
2500
625
156
39
1250
313
78
833
208
52
625
156
39
Primary Prescaler Settings
16:1
64:1
20
13
10
Note 1: Based on FCY = FOSC/2; Doze mode and PLL are disabled.
2: SCKx frequencies are shown in kHz.
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NOTES:
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17.1 Communicating as a Master in a
Single Master Environment
17.0 INTER-INTEGRATED
2
CIRCUIT™ (I C™)
The details of sending a message in Master mode
depends on the communications protocol for the device
being communicated with. Typically, the sequence of
events is as follows:
Note:
This data sheet summarizes the features of
this group of PIC24F devices. It is not
intended to be a comprehensive reference
source. For more information, refer to the
“PIC24F Family Reference Manual”,
Section 24. “Inter-Integrated Circuit™
(I2C™)” (DS39702). The information in this
data sheet supersedes the information in
the FRM.
1. Assert a Start condition on SDAx and SCLx.
2. Send the I2C device address byte to the slave
with a write indication.
3. Wait for and verify an Acknowledge from the
slave.
The Inter-Integrated Circuit™ (I2C™) module is a serial
interface useful for communicating with other periph-
eral or microcontroller devices. These peripheral
devices may be serial EEPROMs, display drivers, A/D
Converters, etc.
4. Send the first data byte (sometimes known as
the command) to the slave.
5. Wait for and verify an Acknowledge from the
slave.
6. Send the serial memory address low byte to the
slave.
The I2C module supports these features:
7. Repeat Steps 4 and 5 until all data bytes are
sent.
• Independent master and slave logic
• 7-bit and 10-bit device addresses
• General call address as defined in the I2C protocol
8. Assert a Repeated Start condition on SDAx and
SCLx.
• Clock stretching to provide delays for the
processor to respond to a slave data request
9. Send the device address byte to the slave with
a read indication.
• Both 100 kHz and 400 kHz bus specifications
• Configurable address masking
10. Wait for and verify an Acknowledge from the
slave.
• Multi-Master modes to prevent loss of messages
in arbitration
11. Enable master reception to receive serial
memory data.
• Bus Repeater mode, allowing the acceptance of
all messages as a slave regardless of the address
12. Generate an ACK or NACK condition at the end
of a received byte of data.
• Automatic SCL
13. Generate a Stop condition on SDAx and SCLx.
A block diagram of the module is shown in Figure 17-1.
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FIGURE 17-1:
I2C™ BLOCK DIAGRAM
Internal
Data Bus
I2CxRCV
Read
Shift
Clock
SCLx
SDAx
I2CxRSR
LSB
Address Match
Write
Read
Match Detect
I2CxMSK
Write
Read
I2CxADD
Start and Stop
Bit Detect
Write
Start and Stop
Bit Generation
I2CxSTAT
I2CxCON
Read
Write
Collision
Detect
Acknowledge
Generation
Read
Clock
Stretching
Write
Read
I2CxTRN
LSB
Shift Clock
Reload
Control
Write
Read
BRG Down Counter
TCY/2
I2CxBRG
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17.2 Setting Baud Rate When
Operating as a Bus Master
17.3 Slave Address Masking
The I2CxMSK register (Register 17-3) designates
address bit positions as “don’t care” for both 7-Bit and
10-Bit Addressing modes. Setting a particular bit loca-
tion (= 1) in the I2CxMSK register causes the slave
module to respond whether the corresponding address
bit value is a ‘0’ or a ‘1’. For example, when I2CxMSK
is set to ‘00100000’, the slave module will detect both
addresses, ‘0000000’ and ‘0100000’.
To compute the Baud Rate Generator reload value, use
Equation 17-1.
EQUATION 17-1: COMPUTING BAUD RATE
RELOAD VALUE(1,2)
FCY
FSCL =
FCY
10,000,000
I2CxBRG + 1 +
To enable address masking, the Intelligent Peripheral
Management Interface (IPMI) must be disabled by
clearing the IPMIEN bit (I2CxCON<11>).
or:
FCY
FSCL
FCY
10,000,000
–
– 1
I2CxBRG =
(
)
Note:
As a result of changes in the I2C™ proto-
col, the addresses in Table 17-2 are
reserved and will not be Acknowledged in
Slave mode. This includes any address
mask settings that include any of these
addresses.
Note 1: Based on FCY = FOSC/2; Doze mode and
PLL are disabled.
2: These clock rate values are for guidance
only. The actual clock rate can be affected
by various system level parameters. The
actual clock rate should be measured in
its intended application.
TABLE 17-1: I2C™ CLOCK RATES(1,2)
I2CxBRG Value
Required System FSCL
FCY
Actual FSCL
(Decimal)
(Hexadecimal)
9D
100 kHz
100 kHz
100 kHz
400 kHz
400 kHz
400 kHz
400 kHz
1 MHz
16 MHz
8 MHz
4 MHz
16 MHz
8 MHz
4 MHz
2 MHz
16 MHz
8 MHz
4 MHz
157
78
39
37
18
9
100 kHz
100 kHz
99 kHz
4E
27
25
12
9
404 kHz
404 kHz
385 kHz
385 kHz
1.026 MHz
1.026 MHz
0.909 MHz
4
4
13
6
D
1 MHz
6
1 MHz
3
3
Note 1: Based on FCY = FOSC/2; Doze mode and PLL are disabled.
2: These clock rate values are for guidance only. The actual clock rate can be affected by various system
level parameters. The actual clock rate should be measured in its intended application.
TABLE 17-2: I2C™ RESERVED ADDRESSES(1)
Slave Address R/W Bit
Description
0000 000
0000 000
0000 001
0000 01x
0000 1xx
1111 0xx
1111 1xx
0
1
x
x
x
x
x
General Call Address(2)
Start Byte
CBus Address
Reserved
HS Mode Master Code
10-Bit Slave Upper Byte(3)
Reserved
Note 1: The address bits listed here will never cause an address match, independent of address mask settings.
2: The address will be Acknowledged only if GCEN = 1.
3: A match on this address can only occur on the upper byte in 10-Bit Addressing mode.
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REGISTER 17-1: I2CxCON: I2Cx CONTROL REGISTER
R/W-0
I2CEN
U-0
—
R/W-0
R/W-1, HC
SCLREL
R/W-0
R/W-0
A10M
R/W-0
R/W-0
SMEN
I2CSIDL
IPMIEN
DISSLW
bit 15
bit 8
R/W-0
GCEN
R/W-0
R/W-0
R/W-0, HC
ACKEN
R/W-0, HC
RCEN
R/W-0, HC
PEN
R/W-0, HC
RSEN
R/W-0, HC
SEN
STREN
ACKDT
bit 7
bit 0
Legend:
HC = Hardware Clearable bit
W = Writable bit
R = Readable bit
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
-n = Value at POR
‘1’ = Bit is set
bit 15
I2CEN: I2Cx Enable bit
1= Enables the I2Cx module and configures the SDAx and SCLx pins as serial port pins
0= Disables the I2Cx module; all I2C™ pins are controlled by port functions
bit 14
bit 13
Unimplemented: Read as ‘0’
I2CSIDL: Stop in Idle Mode bit
1= Discontinues module operation when device enters an Idle mode
0= Continues module operation in Idle mode
bit 12
SCLREL: SCLx Release Control bit (when operating as I2C slave)
1= Releases SCLx clock
0= Holds SCLx clock low (clock stretch)
If STREN = 1:
Bit is R/W (i.e., software may write ‘0’ to initiate stretch and write ‘1’ to release clock). Hardware is clear
at the beginning of slave transmission. Hardware is clear at the end of slave reception.
If STREN = 0:
Bit is R/S (i.e., software may only write ‘1’ to release clock). Hardware is clear at the beginning of slave
transmission.
bit 11
bit 10
bit 9
IPMIEN: Intelligent Platform Management Interface (IPMI) Enable bit
1= IPMI Support mode is enabled; all addresses are Acknowledged
0= IPMI mode is disabled
A10M: 10-Bit Slave Addressing bit
1= I2CxADD is a 10-bit slave address
0= I2CxADD is a 7-bit slave address
DISSLW: Disable Slew Rate Control bit
1= Slew rate control is disabled
0= Slew rate control is enabled
bit 8
SMEN: SMBus Input Levels bit
1= Enables I/O pin thresholds compliant with SMBus specifications
0= Disables the SMBus input thresholds
bit 7
GCEN: General Call Enable bit (when operating as I2C slave)
1= Enables interrupt when a general call address is received in the I2CxRSR (module is enabled for
reception)
0= General call address is disabled
bit 6
STREN: SCLx Clock Stretch Enable bit (when operating as I2C slave)
Used in conjunction with the SCLREL bit.
1= Enables software or receive clock stretching
0= Disables software or receive clock stretching
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REGISTER 17-1: I2CxCON: I2Cx CONTROL REGISTER (CONTINUED)
bit 5
ACKDT: Acknowledge Data bit (when operating as I2C master; applicable during master receive)
Value that will be transmitted when the software initiates an Acknowledge sequence.
1= Sends NACK during Acknowledge
0= Sends ACK during Acknowledge
bit 4
ACKEN: Acknowledge Sequence Enable bit
(when operating as I2C master; applicable during master receive)
1= Initiates Acknowledge sequence on SDAx and SCLx pins and transmits the ACKDT data bit.
Hardware is clear at the end of the master Acknowledge sequence.
0= Acknowledge sequence is not in progress
bit 3
bit 2
bit 1
bit 0
RCEN: Receive Enable bit (when operating as I2C master)
1= Enables Receive mode for I2C. Hardware is clear at the end of the eighth bit of the master receive
data byte.
0= Receive sequence is not in progress
PEN: Stop Condition Enable bit (when operating as I2C master)
1= Initiates Stop condition on the SDAx and SCLx pins. Hardware is clear at the end of the master
Stop sequence.
0= Stop condition is not in progress
RSEN: Repeated Start Condition Enable bit (when operating as I2C master)
1= Initiates Repeated Start condition on the SDAx and SCLx pins. Hardware is clear at the end of the
master Repeated Start sequence.
0= Repeated Start condition is not in progress
SEN: Start Condition Enable bit (when operating as I2C master)
1= Initiates Start condition on SDAx and SCLx pins. Hardware is clear at the end of the master Start
sequence.
0= Start condition is not in progress
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REGISTER 17-2: I2CxSTAT: I2Cx STATUS REGISTER
R-0, HSC
ACKSTAT
bit 15
R-0, HSC
TRSTAT
U-0
—
U-0
—
U-0
—
R/C-0, HS
BCL
R-0, HSC
GCSTAT
R-0, HSC
ADD10
bit 8
R/C-0, HS R/C-0, HS R-0, HSC R/C-0, HSC R/C-0, HSC
R-0, HSC
R/W
R-0, HSC
RBF
R-0, HSC
TBF
IWCOL
bit 7
I2COV
D/A
P
S
bit 0
Legend:
C = Clearable bit
W = Writable bit
‘1’ = Bit is set
HS = Hardware Settable bit
R = Readable bit
-n = Value at POR
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
HSC = Hardware Settable/Clearable bit
bit 15
bit 14
ACKSTAT: Acknowledge Status bit
1= NACK was detected last
0= ACK was detected last
Hardware is set or cleared at the end of Acknowledge.
TRSTAT: Transmit Status bit
(when operating as I2C™ master; applicable to master transmit operation.)
1= Master transmit is in progress (8 bits + ACK)
0= Master transmit is not in progress
Hardware is set at the beginning of master transmission; hardware is clear at the end of slave Acknowledge.
bit 13-11
bit 10
Unimplemented: Read as ‘0’
BCL: Master Bus Collision Detect bit
1= A bus collision has been detected during a master operation
0= No collision
Hardware is set at the detection of a bus collision.
bit 9
bit 8
bit 7
bit 6
bit 5
GCSTAT: General Call Status bit
1= General call address was received
0= General call address was not received
Hardware is set when the address matches the general call address; hardware is clear at Stop detection.
ADD10: 10-Bit Address Status bit
1= 10-bit address was matched
0= 10-bit address was not matched
Hardware is set at the match of the 2nd byte of the matched 10-bit address; hardware is clear at Stop detection.
IWCOL: Write Collision Detect bit
1= An attempt to write to the I2CxTRN register failed because the I2C module is busy
0= No collision
Hardware is set at an occurrence of write to I2CxTRN while busy (cleared by software).
I2COV: Receive Overflow Flag bit
1= A byte was received while the I2CxRCV register is still holding the previous byte
0= No overflow
Hardware is set at an attempt to transfer I2CxRSR to I2CxRCV (cleared by software).
D/A: Data/Address bit (when operating as I2C slave)
1= Indicates that the last byte received was data
0= Indicates that the last byte received was a device address
Hardware is clear at the device address match. Hardware is set after a transmission finishes or by
reception of a slave byte.
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REGISTER 17-2: I2CxSTAT: I2Cx STATUS REGISTER (CONTINUED)
bit 4
bit 3
bit 2
bit 1
P: Stop bit
1= Indicates that a Stop bit has been detected last
0= Stop bit was not detected last
Hardware is set or clear when Start, Repeated Start or Stop is detected.
S: Start bit
1= Indicates that a Start (or Repeated Start) bit has been detected last
0= Start bit was not detected last
Hardware is set or clear when Start, Repeated Start or Stop is detected.
R/W: Read/Write Information bit (when operating as I2C slave)
1= Read: Indicates the data transfer is output from the slave
0= Write: Indicates the data transfer is input to the slave
Hardware is set or clear after the reception of an I2C device address byte.
RBF: Receive Buffer Full Status bit
1= Receive is complete, I2CxRCV is full
0= Receive is not complete, I2CxRCV is empty
Hardware is set when I2CxRCV is written with the received byte; hardware is clear when the software
reads I2CxRCV.
bit 0
TBF: Transmit Buffer Full Status bit
1= Transmit is in progress, I2CxTRN is full
0= Transmit is complete, I2CxTRN is empty
Hardware is set when software writes to I2CxTRN; hardware is clear at the completion of data transmission.
REGISTER 17-3: I2CxMSK: I2Cx SLAVE MODE ADDRESS MASK REGISTER
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
R/W-0
R/W-0
AMSK9
AMSK8
bit 15
bit 8
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
AMSK7
AMSK6
AMSK5
AMSK4
AMSK3
AMSK2
AMSK1
AMSK0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
-n = Value at POR
bit 15-10
bit 9-0
Unimplemented: Read as ‘0’
AMSK<9:0>: Mask for Address Bit x Select bits
1= Enables masking for bit x of the incoming message address; bit match is not required in this position
0= Disables masking for bit x; bit match is required in this position
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• Fully Integrated Baud Rate Generator with 16-Bit
Prescaler
18.0 UNIVERSAL ASYNCHRONOUS
RECEIVER TRANSMITTER
(UART)
• Baud Rates Ranging from 15 bps to 1 Mbps at
16 MIPS
• 4-Deep, First-In-First-Out (FIFO) Transmit Data
Buffer
Note:
This data sheet summarizes the features of
this group of PIC24F devices. It is not
intended to be a comprehensive reference
source. For more information, refer to the
“PIC24F Family Reference Manual”,
Section 21. “UART” (DS39708). The
information in this data sheet supersedes
the information in the FRM.
• 4-Deep FIFO Receive Data Buffer
• Parity, Framing and Buffer Overrun Error Detection
• Support for 9-bit mode with Address Detect
(9th bit = 1)
• Transmit and Receive Interrupts
• Loopback mode for Diagnostic Support
• Support for Sync and Break Characters
• Supports Automatic Baud Rate Detection
• IrDA® Encoder and Decoder Logic
• 16x Baud Clock Output for IrDA Support
The Universal Asynchronous Receiver Transmitter
(UART) module is one of the serial I/O modules available
in the PIC24F device family. The UART is a full-duplex,
asynchronous system that can communicate with
peripheral devices, such as personal computers,
LIN/J2602, RS-232 and RS-485 interfaces. The module
also supports a hardware flow control option with the
UxCTS and UxRTS pins, and includes an IrDA® encoder
and decoder.
A simplified block diagram of the UART is shown in
Figure 18-1. The UART module consists of these key
important hardware elements:
• Baud Rate Generator
The primary features of the UART module are:
• Asynchronous Transmitter
• Asynchronous Receiver
• Full-Duplex, 8 or 9-Bit Data Transmission through
the UxTX and UxRX Pins
• Even, Odd or No Parity Options (for 8-bit data)
• One or Two Stop bits
• Hardware Flow Control Option with the UxCTS
and UxRTS Pins
FIGURE 18-1:
UART SIMPLIFIED BLOCK DIAGRAM
Baud Rate Generator
®
IrDA
UxRTS/BCLKx
UxCTS
Hardware Flow Control
UARTx Receiver
UxRX
UxTX
UARTx Transmitter
Note:
The UART inputs and outputs must all be assigned to available RPn/RPIn pins before use. See Section 11.4
“Peripheral Pin Select (PPS)” for more information.
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The maximum baud rate (BRGH = 0) possible is
FCY/16 (for UxBRG = 0) and the minimum baud rate
18.1 UART Baud Rate Generator (BRG)
The UART module includes a dedicated, 16-bit Baud
Rate Generator. The UxBRG register controls the
period of a free-running, 16-bit timer. Equation 18-1
shows the formula for computation of the baud rate with
BRGH = 0.
possible is FCY/(16 * 65536).
Equation 18-2 shows the formula for computation of
the baud rate with BRGH = 1.
EQUATION 18-2: UART BAUD RATE WITH
BRGH = 1(1,2)
EQUATION 18-1: UART BAUD RATE WITH
BRGH = 0(1,2)
FCY
Baud Rate =
FCY
Baud Rate =
4 • (UxBRG + 1)
16 • (UxBRG + 1)
FCY
– 1
UxBRG =
FCY
4 • Baud Rate
– 1
UxBRG =
16 • Baud Rate
Note 1: FCY denotes the instruction cycle clock
frequency.
Note 1: FCY denotes the instruction cycle clock
frequency (FOSC/2).
2: Based on FCY = FOSC/2; Doze mode
2: Based on FCY = FOSC/2; Doze mode
and PLL are disabled.
and PLL are disabled.
The maximum baud rate (BRGH = 1) possible is FCY/4
(for UxBRG = 0) and the minimum baud rate possible
is FCY/(4 * 65536).
Example 18-1 shows the calculation of the baud rate
error for the following conditions:
• FCY = 4 MHz
Writing a new value to the UxBRG register causes the
BRG timer to be reset (cleared). This ensures the BRG
does not wait for a timer overflow before generating the
new baud rate.
• Desired Baud Rate = 9600
EXAMPLE 18-1:
BAUD RATE ERROR CALCULATION (BRGH = 0)(1)
Desired Baud Rate = FCY/(16 (BRGx + 1))
Solving for BRGx Value:
BRGx
BRGx
BRGx
= ((FCY/Desired Baud Rate)/16) – 1
= ((4000000/9600)/16) – 1
= 25
Calculated Baud Rate = 4000000/(16 (25 + 1))
= 9615
Error
= (Calculated Baud Rate – Desired Baud Rate)
Desired Baud Rate
= (9615 – 9600)/9600
= 0.16%
Note 1: Based on FCY = FOSC/2; Doze mode and PLL are disabled.
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18.2 Transmitting in 8-Bit Data Mode
18.5 Receiving in 8-Bit or 9-Bit Data
Mode
1. Set up the UART:
a) Write appropriate values for data, parity and
Stop bits.
1. Set up the UART (as described in Section 18.2
“Transmitting in 8-Bit Data Mode”).
b) Write appropriate baud rate value to the
UxBRG register.
2. Enable the UART.
3. A receive interrupt will be generated when one
or more data characters have been received as
per interrupt control bit, URXISELx.
c) Set up transmit and receive interrupt enable
and priority bits.
2. Enable the UART.
4. Read the OERR bit to determine if an overrun
error has occurred. The OERR bit must be reset
in software.
3. Set the UTXEN bit (causes a transmit interrupt,
two cycles after being set).
5. Read UxRXREG.
4. Write a data byte to the lower byte of the
UxTXREG word. The value will be immediately
transferred to the Transmit Shift Register (TSR)
and the serial bit stream will start shifting out
with the next rising edge of the baud clock.
The act of reading the UxRXREG character will move
the next character to the top of the receive FIFO,
including a new set of PERR and FERR values.
5. Alternatively, the data byte may be transferred
while UTXEN = 0 and then the user may set
UTXEN. This will cause the serial bit stream to
begin immediately because the baud clock will
start from a cleared state.
18.6 Operation of UxCTS and UxRTS
Control Pins
UARTx Clear to Send (UxCTS) and Request to Send
(UxRTS) are the two hardware controlled pins that are
associated with the UART module. These two pins
allow the UART to operate in Simplex and Flow Control
mode. They are implemented to control the transmis-
sion and reception between the Data Terminal
Equipment (DTE). The UEN<1:0> bits in the UxMODE
register configure these pins.
6. A transmit interrupt will be generated as per
interrupt control bit, UTXISELx.
18.3 Transmitting in 9-Bit Data Mode
1. Set up the UART (as described in Section 18.2
“Transmitting in 8-Bit Data Mode”).
2. Enable the UART.
18.7 Infrared Support
3. Set the UTXEN bit (causes a transmit interrupt).
4. Write UxTXREG as a 16-bit value only.
The UART module provides two types of infrared UART
support: one is the IrDA clock output to support an
external IrDA encoder and decoder device (legacy
module support), and the other is the full implementa-
tion of the IrDA encoder and decoder. Note that
because the IrDA modes require a 16x baud clock, they
will only work when the BRGH bit (UxMODE<3>) is ‘0’.
5. A word write to UxTXREG triggers the transfer
of the 9-bit data to the TSR. The serial bit stream
will start shifting out with the first rising edge of
the baud clock.
6. A transmit interrupt will be generated as per the
setting of control bit, UTXISELx.
18.7.1
IrDA CLOCK OUTPUT FOR
EXTERNAL IrDA SUPPORT
18.4 Break and Sync Transmit
Sequence
To support external IrDA encoder and decoder devices,
the BCLKx pin (same as the UxRTS pin) can be
configured to generate the 16x baud clock. With
UEN<1:0> = 11, the BCLKx pin will output the 16x
baud clock if the UART module is enabled. It can be
used to support the IrDA codec chip.
The following sequence will send a message frame
header, made up of a Break, followed by an auto-baud
Sync byte.
1. Configure the UART for the desired mode.
2. Set UTXEN and UTXBRK to set up the Break
character.
18.7.2
BUILT-IN IrDA ENCODER AND
DECODER
3. Load the UxTXREG with a dummy character to
initiate transmission (value is ignored).
The UART has full implementation of the IrDA encoder
and decoder as part of the UART module. The built-in
IrDA encoder and decoder functionality is enabled
using the IREN bit (UxMODE<12>). When enabled
(IREN = 1), the receive pin (UxRX) acts as the input
from the infrared receiver. The transmit pin (UxTX) acts
as the output to the infrared transmitter.
4. Write ‘55h’ to UxTXREG; this loads the Sync
character into the transmit FIFO.
5. After the Break has been sent, the UTXBRK bit
is reset by hardware. The Sync character now
transmits.
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REGISTER 18-1: UxMODE: UARTx MODE REGISTER
R/W-0
UARTEN(1)
bit 15
U-0
—
R/W-0
USIDL
R/W-0
IREN(2)
R/W-0
U-0
—
R/W-0
UEN1
R/W-0
UEN0
RTSMD
bit 8
R/W-0, HC
WAKE
R/W-0
R/W-0, HC
ABAUD
R/W-0
RXINV
R/W-0
BRGH
R/W-0
R/W-0
R/W-0
LPBACK
PDSEL1
PDSEL0
STSEL
bit 7
bit 0
Legend:
HC = Hardware Clearable bit
W = Writable bit
R = Readable bit
-n = Value at POR
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
‘1’ = Bit is set
bit 15
UARTEN: UARTx Enable bit(1)
1= UARTx is enabled; all UARTx pins are controlled by UARTx as defined by UEN<1:0>
0= UARTx is disabled; all UARTx pins are controlled by port latches; UARTx power consumption is minimal
bit 14
bit 13
Unimplemented: Read as ‘0’
USIDL: Stop in Idle Mode bit
1= Discontinue module operation when device enters Idle mode
0= Continue module operation in Idle mode
bit 12
bit 11
IREN: IrDA® Encoder and Decoder Enable bit(2)
1= IrDA encoder and decoder are enabled
0= IrDA encoder and decoder are disabled
RTSMD: Mode Selection for UxRTS Pin bit
1= UxRTS pin is in Simplex mode
0= UxRTS pin is in Flow Control mode
bit 10
Unimplemented: Read as ‘0’
UEN<1:0>: UARTx Enable bits
bit 9-8
11= UxTX, UxRX and BCLKx pins are enabled and used; UxCTS pin is controlled by port latches
10= UxTX, UxRX, UxCTS and UxRTS pins are enabled and used
01= UxTX, UxRX and UxRTS pins are enabled and used; UxCTS pin is controlled by port latches
00= UxTX and UxRX pins are enabled and used; UxCTS and UxRTS/BCLKx pins are controlled by port
latches
bit 7
WAKE: Wake-up on Start Bit Detect During Sleep Mode Enable bit
1= UARTx will continue to sample the UxRX pin; interrupt is generated on the falling edge, bit is cleared
in hardware on the following rising edge
0= No wake-up is enabled
bit 6
bit 5
LPBACK: UARTx Loopback Mode Select bit
1= Enable Loopback mode
0= Loopback mode is disabled
ABAUD: Auto-Baud Enable bit
1= Enable baud rate measurement on the next character – requires reception of a Sync field (55h);
cleared in hardware upon completion
0= Baud rate measurement is disabled or completed
Note 1: If UARTEN = 1, the peripheral inputs and outputs must be configured to an available RPn/RPIn pin. See
Section 11.4 “Peripheral Pin Select (PPS)” for more information.
2: This feature is only available for the 16x BRG mode (BRGH = 0).
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REGISTER 18-1: UxMODE: UARTx MODE REGISTER (CONTINUED)
bit 4
RXINV: Receive Polarity Inversion bit
1= UxRX Idle state is ‘0’
0= UxRX Idle state is ‘1’
bit 3
BRGH: High Baud Rate Enable bit
1= High-Speed mode (4 BRG clock cycles per bit)
0= Standard Speed mode (16 BRG clock cycles per bit)
bit 2-1
PDSEL<1:0>: Parity and Data Selection bits
11= 9-bit data, no parity
10= 8-bit data, odd parity
01= 8-bit data, even parity
00= 8-bit data, no parity
bit 0
STSEL: Stop Bit Selection bit
1= Two Stop bits
0= One Stop bit
Note 1: If UARTEN = 1, the peripheral inputs and outputs must be configured to an available RPn/RPIn pin. See
Section 11.4 “Peripheral Pin Select (PPS)” for more information.
2: This feature is only available for the 16x BRG mode (BRGH = 0).
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REGISTER 18-2: UxSTA: UARTx STATUS AND CONTROL REGISTER
R/W-0
UTXISEL1
bit 15
R/W-0
UTXINV(1)
R/W-0
U-0
—
R/W-0 HC
UTXBRK
R/W-0
UTXEN(2)
R-0, HSC
UTXBF
R-1, HSC
TRMT(3)
UTXISEL0
bit 8
R/W-0
URXISEL1
bit 7
R/W-0
R/W-0
R-1, HSC
RIDLE
R-0, HSC
PERR
R-0, HSC
FERR
R/C-0, HS
OERR
R-0, HSC
URXDA
URXISEL0
ADDEN
bit 0
Legend:
C = Clearable bit
W = Writable bit
‘1’ = Bit is set
HSC = Hardware Settable/Clearable bit
U = Unimplemented bit, read as ‘0’
R = Readable bit
-n = Value at POR
‘0’ = Bit is cleared
x = Bit is unknown
HS = Hardware Settable bit HC = Hardware Clearable bit
bit 15,13
UTXISEL<1:0>: Transmission Interrupt Mode Selection bits
11= Reserved; do not use
10= Interrupt when a character is transferred to the Transmit Shift Register (TSR), and as a result, the
transmit buffer becomes empty
01= Interrupt when the last character is shifted out of the Transmit Shift Register; all transmit
operations are completed
00= Interrupt when a character is transferred to the Transmit Shift Register (this implies there is at least
one character open in the transmit buffer)
bit 14
UTXINV: IrDA® Encoder Transmit Polarity Inversion bit(1)
IREN = 0:
1= UxTX is Idle ‘0’
0= UxTX is Idle ‘1’
IREN = 1:
1= UxTX is Idle ‘1’
0= UxTX is Idle ‘0’
bit 12
bit 11
Unimplemented: Read as ‘0’
UTXBRK: Transmit Break bit
1= Send Sync Break on next transmission – Start bit, followed by twelve ‘0’ bits, followed by Stop bit;
cleared by hardware upon completion
0= Sync Break transmission is disabled or completed
bit 10
UTXEN: Transmit Enable bit(2)
1= Transmit is enabled, UxTX pin is controlled by UARTx
0= Transmit is disabled, any pending transmission is aborted and the buffer is reset; UxTX pin is
controlled by the port.
bit 9
bit 8
UTXBF: Transmit Buffer Full Status bit (read-only)
1= Transmit buffer is full
0= Transmit buffer is not full, at least one more character can be written
TRMT: Transmit Shift Register Empty bit (read-only)(3)
1= Transmit Shift Register is empty and transmit buffer is empty (the last transmission has completed)
0= Transmit Shift Register is not empty, a transmission is in progress or queued
Note 1: The value of the bit only affects the transmit properties of the module when the IrDA® encoder is enabled
(IREN = 1).
2: If UARTEN = 1, the peripheral inputs and outputs must be configured to an available RPn/RPIn pin. See
Section 11.4 “Peripheral Pin Select (PPS)” for more information.
3: The TRMT bit will be active only after two instruction, cycles once the UTXREG is loaded.
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REGISTER 18-2: UxSTA: UARTx STATUS AND CONTROL REGISTER (CONTINUED)
bit 7-6
URXISEL<1:0>: Receive Interrupt Mode Selection bits
11= Interrupt is set on an RSR transfer, making the receive buffer full (i.e., has 4 data characters)
10= Interrupt is set on an RSR transfer, making the receive buffer 3/4 full (i.e., has 3 data characters)
0x= Interrupt is set when any character is received and transferred from the RSR to the receive buffer;
receive buffer has one or more characters
bit 5
bit 4
bit 3
bit 2
bit 1
ADDEN: Address Character Detect bit (bit 8 of received data = 1)
1= Address Detect mode is enabled (if 9-bit mode is not selected, this does not take effect)
0= Address Detect mode is disabled
RIDLE: Receiver Idle bit (read-only)
1= Receiver is Idle
0= Receiver is active
PERR: Parity Error Status bit (read-only)
1= Parity error has been detected for the current character (character at the top of the receive FIFO)
0= Parity error has not been detected
FERR: Framing Error Status bit (read-only)
1= Framing error has been detected for the current character (character at the top of the receive FIFO)
0= Framing error has not been detected
OERR: Receive Buffer Overrun Error Status bit (clear/read-only)
1= Receive buffer has overflowed
0= Receive buffer has not overflowed (clearing a previously set OERR bit (1 0transition); will reset
the receiver buffer and the RSR to the empty state
bit 0
URXDA: Receive Buffer Data Available bit (read-only)
1= Receive buffer has data, at least one more character can be read
0= Receive buffer is empty
Note 1: The value of the bit only affects the transmit properties of the module when the IrDA® encoder is enabled
(IREN = 1).
2: If UARTEN = 1, the peripheral inputs and outputs must be configured to an available RPn/RPIn pin. See
Section 11.4 “Peripheral Pin Select (PPS)” for more information.
3: The TRMT bit will be active only after two instruction, cycles once the UTXREG is loaded.
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NOTES:
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The modulated output signal is generated by perform-
19.0 DATA SIGNAL MODULATOR
ing a logical AND operation of both the carrier and
modulator signals and then it is provided to the MDOUT
pin. Using this method, the DSM can generate the
following types of key modulation schemes:
Note:
This data sheet summarizes the features of
this group of PIC24F devices. It is not
intended to be a comprehensive reference
source. For more information, refer to the
“PIC24F Family Reference Manual”,
Section 55. “Data Signal Modulator
(DSM)” (DS39744). The information in this
data sheet supersedes the information in
the FRM.
• Frequency Shift Keying (FSK)
• Phase Shift Keying (PSK)
• On-Off Keying (OOK)
Figure 19-1 shows a simplified block diagram of the
Data Signal Modulator peripheral.
The Data Signal Modulator (DSM) allows the user to
mix a digital data stream (the “modulator signal”) with a
carrier signal to produce a modulated output. Both the
carrier and the modulator signals are supplied to the
DSM module, either internally from the output of a
peripheral, or externally through an input pin.
FIGURE 19-1:
SIMPLIFIED BLOCK DIAGRAM OF THE DATA SIGNAL MODULATOR
MDCH<3:0>
MDEN
EN
VSS
MDCIN1
Data Signal
Modulator
MDCIN2
REFO Clock
OC/PWM1
OC/PWM2
OC/PWM3
OC/PWM4
OC/PWM5
OC/PWM6
OC/PWM7
CARH
CHPOL
D
SYNC
Q
MDMS<3:0>
1
0
MDBIT
MDMIN
SSP1 (SDO)
SSP2 (SDO)
UART1 (TX)
UART2 (TX)
UART3 (TX)
UART4 (TX)
OC/PWM1
OC/PWM2
OC/PWM3
OC/PWM4
OC/PWM5
OC/PWM6
OC/PWM7
CHSYNC
MOD
MDOUT
MDOE
MDOPOL
D
SYNC
MDCL<3:0>
Q
1
VSS
MDCIN1
MDCIN2
REFO Clock
OC/PWM1
OC/PWM2
OC/PWM3
OC/PWM4
OC/PWM5
OC/PWM6
OC/PWM7
0
CARL
CLSYNC
CLPOL
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REGISTER 19-1: MDCON: MODULATOR CONTROL REGISTER
R/W-0
MDEN
U-0
—
R/W-0
MSIDL
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
bit 15
bit 8
U-0
—
R/W-0
MDOE
R/W-0
R/W-0
U-0
—
U-0
—
U-0
—
R/W-0
MDBIT(1)
MDSLR
MDOPOL
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15
MDEN: Modulator Module Enable bit
1= Modulator module is enabled and mixing input signals
0= Modulator module is disabled and has no output
bit 14
bit 13
Unimplemented: Read as ‘0’
MSIDL: Modulator Stop in Idle Mode bit
1= Discontinue module operation when device enters Idle mode
0= Continue module operation in Idle mode
bit 12-7
bit 6
Unimplemented: Read as ‘0’
MDOE: Modulator Module Pin Output Enable bit
1= Modulator pin output is enabled
0= Modulator pin output is disabled
bit 5
bit 4
MDSLR: MDOUT Pin Slew Rate Limiting bit
1= MDOUT pin slew rate limiting is enabled
0= MDOUT pin slew rate limiting is disabled
MDOPOL: Modulator Output Polarity Select bit
1= Modulator output signal is inverted
0= Modulator output signal is not inverted
bit 3-1
bit 0
Unimplemented: Read as ‘0’
MDBIT: Manual Modulation Input bit(1)
1= Carrier is modulated
0= Carrier is not modulated
Note 1: The MDBIT must be selected as the modulation source (MDSRC<3:0> = 0000).
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REGISTER 19-2: MDSRC: MODULATOR SOURCE CONTROL REGISTER
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
bit 15
bit 8
R/W-x
SODIS(1)
U-0
—
U-0
—
U-0
—
R/W-x
MS3(2)
R/W-x
MS2(2)
R/W-x
MS1(2)
R/W-x
MS0(2)
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-8
bit 7
Unimplemented: Read as ‘0’
SODIS: Modulation Source Output Disable bit(1)
1= Output signal driving the peripheral output pin (selected by MDMS<3:0>) is disabled
0= Output signal driving the peripheral output pin (selected by MDMS<3:0>) is enabled
bit 6-4
bit 3-0
Unimplemented: Read as ‘0’
MS<3:0> Modulation Source Selection bits(2)
1111= Unimplemented
1110= Output Compare/PWM Module 7 output
1101= Output Compare/PWM Module 6 output
1100= Output Compare/PWM Module 5 output
1011= Output Compare/PWM Module 4 output
1010= Output Compare/PWM Module 3 output
1001= Output Compare/PWM Module 2 output
1000= Output Compare/PWM Module 1 output
0111= UART4 TX output
0110= UART3 TX output
0101= UART2 TX output
0100= UART1 TX output
0011= SPI2 module output (SDO2)
0010= SPI1 module output (SDO1)
0001= Input on MDMIN pin
0000= Manual modulation using MDBIT (MDCON<0>)
Note 1: This bit is only affected by a POR.
2: These bits are not affected by a POR.
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REGISTER 19-3: MDCAR: MODULATOR CARRIER CONTROL REGISTER
R/W-x
R/W-x
R/W-x
U-0
—
R/W-x
CH3(1)
R/W-x
CH2(1)
R/W-x
CH1(1)
R/W-x
CH0(1)
CHODIS
CHPOL
CHSYNC
bit 15
bit 8
R/W-0
R/W-x
R/W-x
U-0
—
R/W-x
CL3(1)
R/W-x
CL2(1)
R/W-x
CL1(1)
R/W-x
CL0(1)
CLODIS
CLPOL
CLSYNC
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
-n = Value at POR
bit 15
bit 14
bit 13
CHODIS: Modulator High Carrier Output Disable bit
1= Output signal driving the peripheral output pin (selected by CH<3:0>) is disabled
0= Output signal driving the peripheral output pin is enabled
CHPOL: Modulator High Carrier Polarity Select bit
1= Selected high carrier signal is inverted
0= Selected high carrier signal is not inverted
CHSYNC: Modulator High Carrier Synchronization Enable bit
1= Modulator waits for a falling edge on the high carrier before allowing a switch to the low carrier
0= Modulator output is not synchronized to the high time carrier signal(1)
bit 12
Unimplemented: Read as ‘0’
bit 11-8
CH<3:0> Modulator Data High Carrier Selection bits(1)
1111
. . . = Reserved
1011
1010= Output Compare/PWM Module 7 output
1001= Output Compare/PWM Module 6 output
1000= Output Compare/PWM Module 5 output
0111= Output Compare/PWM Module 4 output
0110= Output Compare/PWM Module 3 output
0101= Output Compare/PWM Module 2 output
0100= Output Compare/PWM Module 1 output
0011= Reference clock (REFO) output
0010= Input on MDCIN2 pin
0001= Input on MDCIN1 pin
0000= VSS
bit 7
bit 6
bit 5
CLODIS: Modulator Low Carrier Output Disable bit
1= Output signal driving the peripheral output pin (selected by CL<3:0>) is disabled
0= Output signal driving the peripheral output pin is enabled
CLPOL: Modulator Low Carrier Polarity Select bit
1= Selected low carrier signal is inverted
0= Selected low carrier signal is not inverted
CLSYNC: Modulator Low Carrier Synchronization Enable bit
1= Modulator waits for a falling edge on the low carrier before allowing a switch to the high carrier
0= Modulator output is not synchronized to the low time carrier signal(1)
bit 4
Unimplemented: Read as ‘0’
bit 3-0
CL<3:0> Modulator Data Low Carrier Selection bits(1)
Bit settings are identical to those for CH<3:0>.
Note 1: Narrowed carrier pulse widths or spurs may occur in the signal stream if the carrier is not synchronized.
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• Programmable Address Wait States
20.0 ENHANCED PARALLEL
MASTER PORT (EPMP)
• Programmable Data Wait States (per chip select)
• Programmable Polarity on Control Signals
Note:
This data sheet summarizes the features of
(per chip select)
this group of PIC24F devices. It is not
intended to be a comprehensive reference
source. For more information, refer to the
“PIC24F Family Reference Manual”,
Section 42. “Enhanced Parallel Master
Port (EPMP)” (DS39730). The informa-
tion in this data sheet supersedes the
information in the FRM.
• Legacy Parallel Slave Port Support
• Enhanced Parallel Slave Support
- Address Support
- 4-Byte Deep Auto-Incrementing Buffer
20.1 Specific Package Variations
While all PIC24FJ128GA310 family devices implement
the EPMP, I/O pin constraints place some limits on
16-Bit Master mode operations in some package types.
This is reflected in the number of dedicated Chip Select
pins implemented and the number of dedicated
address lines that are available. The differences are
summarized in Table 20-1. All available EPMP pin
functions are summarized in Table 20-2.
The Enhanced Parallel Master Port (EPMP) module
provides a parallel, 4-bit (Master mode only), 8-bit
(Master and Slave modes) or 16-bit (Master mode only)
data bus interface to communicate with off-chip mod-
ules, such as memories, FIFOs, LCD controllers and
other microcontrollers. This module can serve as either
the master or the slave on the communication bus.
For 64-pin devices, the dedicated Chip Select pins
(PMCS1 and PMCS2) are not implemented. In addi-
tion, only 16 address lines (PMA<15:0>) are available.
If required, PMA14 and PMA15 can be remapped to
function as PMCS1 and PMCS2, respectively.
For EPMP Master modes, all external addresses are
mapped into the internal Extended Data Space (EDS).
This is done by allocating a region of the EDS for each
chip select, and then assigning each chip select to a
particular external resource, such as a memory or
external controller. This region should not be assigned
to another device resource, such as RAM or SFRs. To
perform a write or read on an external resource, the
CPU simply performs a write or read within the address
range assigned for the EPMP.
For 80-pin devices, the dedicated PMCS2 pin is not
implemented. It also only implements 16 address lines
(PMA<15:0>). If required, PMA15 can be remapped to
function as PMCS2.
The memory space addressable by the device
depends on the number of address lines available, as
well as the number of Chip Select signals required for
the application. Devices with lower pin counts are more
affected by Chip Select requirements, as these take
away address lines. Table 20-1 shows the maximum
addressable range for each pin count.
Key features of the EPMP module are:
• Extended Data Space (EDS) interface allows
direct access from the CPU
• Up to 23 Programmable Address Lines
• Up to 2 Chip Select lines
• Up to 2 Acknowledgement Lines
(one per chip select)
• 4-bit, 8-bit or 16-bit wide Data Bus
• Programmable Strobe Options (per chip select)
- Individual Read and Write Strobes or;
- Read/Write Strobe with Enable Strobe
• Programmable Address/Data Multiplexing
TABLE 20-1: EPMP FEATURE DIFFERENCES BY DEVICE PIN COUNT
Dedicated Chip Select
Address
Address Range (bytes)
Device
Lines
CS1
CS2
No CS
64K
1 CS
2 CS
PIC24FJXXXGA306 (64-pin)
PIC24FJXXXGA308 (80-pin)
PIC24FJXXXGA310 (100-pin)
—
X
—
—
X
16
16
23
32K
16K
32K
64K
X
16M
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TABLE 20-2: ENHANCED PARALLEL MASTER PORT PIN DESCRIPTIONS
Pin Name
Type
Description
(Alternate Function)
PMA<22:16>
O
O
Address Bus bits<22:16>
Address Bus bit 15
PMA<15>
(PMCS2)
PMA<14>
(PMCS1)
PMA<13:8>
PMA<7:3>
I/O
O
Data Bus bit 15 (16-bit port with multiplexed addressing)
Chip Select 2 (alternate location)
Address Bus bit 14
O
I/O
O
Data Bus bit 14 (16-bit port with multiplexed addressing)
Chip Select 1 (alternate location)
Address Bus bits<13:8>
O
I/O
O
Data Bus bits<13:8> (16-bit port with multiplexed addressing)
Address Bus bits<7:3>
PMA<2>
(PMALU)
O
Address Bus bit 2
O
Address Latch Upper Strobe for Multiplexed Address
Address Bus bit 1
I/O
O
PMA<1>
(PMALH)
Address Latch High Strobe for Multiplexed Address
Address Bus bit 0
I/O
O
PMA<0>
(PMALL)
Address Latch Low Strobe for Multiplexed Address
Data Bus bits<15:8> (demultiplexed addressing)
Data Bus bits<7:4>
PMD<15:8>
I/O
I/O
O
PMD<7:4>
Address Bus bits<7:4> (4-bit port with 1-phase multiplexed addressing)
Data Bus bits<3:0>
PMD<3:0>
PMCS1(1)
PMCS2(2)
PMWR
I/O
I/O
O
Chip Select 1
Chip Select 2
Write Strobe(3)
Enable Signal(3)
Read Strobe(3)
I/O
I/O
I/O
I/O
O
(PMENB)
PMRD
(PMRD/PMWR)
PMBE1
Read/Write Signal(3)
Byte Indicator
PMBE0
O
Nibble or Byte Indicator
PMACK1
PMACK2
I
Acknowledgment Signal 1
I
Acknowledgment Signal 2
Note 1: These pins are implemented in 80-pin and 100-pin devices only.
2: These pins are implemented in 100-pin devices only.
3: Signal function depends on the setting of the MODE<1:0> and SM bits (PMCON1<9:8> and PMCSxCF<8>).
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REGISTER 20-1: PMCON1: EPMP CONTROL REGISTER 1
R/W-0
U-0
—
R/W-0
PSIDL
R/W-0
R/W-0
U-0
—
R/W-0
R/W-0
PMPEN
ADRMUX1
ADRMUX0
MODE1
MODE0
bit 15
bit 8
R/W-0
CSF1
R/W-0
CSF0
R/W-0
ALP
R/W-0
U-0
—
R/W-0
R/W-0
R/W-0
ALMODE
BUSKEEP
IRQM1
IRQM0
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15
PMPEN: Parallel Master Port Enable bit
1= EPMP is enabled
0= EPMP is disabled
bit 14
bit 13
Unimplemented: Read as ‘0’
PSIDL: Stop in Idle Mode bit
1= Discontinue module operation when device enters Idle mode
0= Continue module operation in Idle mode
bit 12-11
ADRMUX<1:0>: Address/Data Multiplexing Selection bits
11= Lower address bits are multiplexed with data bits using 3 address phases
10= Lower address bits are multiplexed with data bits using 2 address phases
01= Lower address bits are multiplexed with data bits using 1 address phase
00= Address and data appear on separate pins
bit 10
Unimplemented: Read as ‘0’
bit 9-8
MODE<1:0>: Parallel Port Mode Select bits
11= Master mode
10= Enhanced PSP; pins used are PMRD, PMWR, PMCS, PMD<7:0> and PMA<1:0>
01= Buffered PSP; pins used are PMRD, PMWR, PMCS and PMD<7:0>
00= Legacy Parallel Slave Port; PMRD, PMWR, PMCS and PMD<7:0> pins are used
bit 7-6
CSF<1:0>: Chip Select Function bits
11= Reserved
10= PMA<15> is used for Chip Select 2, PMA<14> is used for Chip Select 1
01= PMA<15> is used for Chip Select 2, PMCS1 is used for Chip Select 1
00= PMCS2 is used for Chip Select 2, PMCS1 is used for Chip Select 1
bit 5
bit 4
ALP: Address Latch Polarity bit
1= Active-high (PMALL, PMALH and PMALU)
0= Active-low (PMALL, PMALH and PMALU)
ALMODE: Address Latch Strobe Mode bit
1= Enable “smart” address strobes (each address phase is only present if the current access would
cause a different address in the latch than the previous address)
0= Disable “smart” address strobes
bit 3
bit 2
Unimplemented: Read as ‘0’
BUSKEEP: Bus Keeper bit
1= Data bus keeps its last value when not actively being driven
0= Data bus is in a high-impedance state when not actively being driven
bit 1-0
IRQM<1:0>: Interrupt Request Mode bits
11= Interrupt is generated when Read Buffer 3 is read or Write Buffer 3 is written (Buffered PSP mode),
or on a read or write operation when PMA<1:0> = 11(Addressable PSP mode only)
10= Reserved
01= Interrupt is generated at the end of a read/write cycle
00= No interrupt is generated
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REGISTER 20-2: PMCON2: EPMP CONTROL REGISTER 2
R-0, HSC
BUSY
U-0
—
R/C-0, HS
ERROR
R/C-0, HS
TIMEOUT
U-0
—
U-0
—
U-0
—
U-0
—
bit 15
bit 8
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
RADDR23(1) RADDR22(1) RADDR21(1) RADDR20(1) RADDR19(1) RADDR18(1) RADDR17(1) RADDR16(1)
bit 7
bit 0
Legend:
HS = Hardware Settable bit HSC = Hardware Settable/Clearable bit
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 15
BUSY: Busy bit (Master mode only)
1= Port is busy
0= Port is not busy
bit 14
bit 13
Unimplemented: Read as ‘0’
ERROR: Error bit
1= Transaction error (illegal transaction was requested)
0= Transaction completed successfully
bit 12
TIMEOUT: Time-out bit
1= Transaction timed out
0= Transaction completed successfully
bit 11-8
bit 7-0
Unimplemented: Read as ‘0’
RADDR<23:16>: Parallel Master Port Reserved Address Space bits(1)
Note 1: If RADDR<23:16> = 00000000, then the last EDS address for Chip Select 2 will be FFFFFFh.
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REGISTER 20-3: PMCON3: EPMP CONTROL REGISTER 3
R/W-0
R/W-0
R/W-0
R/W-0
U-0
—
R/W-0
R/W-0
R/W-0
PTWREN
PTRDEN
PTBE1EN
PTBE0EN
AWAITM1
AWAITM0
AWAITE
bit 15
bit 8
U-0
—
R/W-0
PTEN22(1)
R/W-0
PTEN21(1)
R/W-0
PTEN20(1)
R/W-0
PTEN19(1)
R/W-0
PTEN18(1)
R/W-0
PTEN17(1)
R/W-0
PTEN16(1)
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15
bit 14
bit 13
bit 12
PTWREN: Write/Enable Strobe Port Enable bit
1= PMWR/PMENB port is enabled
0= PMWR/PMENB port is disabled
PTRDEN: Read/Write Strobe Port Enable bit
1= PMRD/PMWR port is enabled
0= PMRD/PMWR port is disabled
PTBE1EN: High Nibble/Byte Enable Port Enable bit
1= PMBE1 port is enabled
0= PMBE1 port is disabled
PTBE0EN: Low Nibble/Byte Enable Port Enable bit
1= PMBE0 port is enabled
0= PMBE0 port is disabled
bit 11
Unimplemented: Read as ‘0’
bit 10-9
AWAITM<1:0>: Address Latch Strobe Wait States bits
11= Wait of 3½ TCY
10= Wait of 2½ TCY
01= Wait of 1½ TCY
00= Wait of ½ TCY
bit bit 8
AWAITE: Address Hold After Address Latch Strobe Wait States bits
1= Wait of 1¼ TCY
0= Wait of ¼ TCY
bit 7
Unimplemented: Read as ‘0’
bit 6-0
PTEN<22:16>: EPMP Address Port Enable bits(1)
1= PMA<22:16> function as EPMP address lines
0= PMA<22:16> function as port I/Os
Note 1: These bits are not available in 80 and 64-pin devices (PIC24FJXXXGA306, PIC24FJXXXGA308).
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REGISTER 20-4: PMCON4: EPMP CONTROL REGISTER 4
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
PTEN15
PTEN14
PTEN13
PTEN12
PTEN11
PTEN10
PTEN9
PTEN8
bit 15
bit 8
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
PTEN7
PTEN6
PTEN5
PTEN4
PTEN3
PTEN2
PTEN1
PTEN0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
-n = Value at POR
bit 15
PTEN15: PMA15 Port Enable bit
1= PMA15 functions as either Address Line 15 or Chip Select 2
0= PMA15 functions as port I/O
bit 14
PTEN14: PMA14 Port Enable bit
1= PMA14 functions as either Address Line 14 or Chip Select 1
0= PMA14 functions as port I/O
bit 13-3
bit 2-0
PTEN<13:3>: EPMP Address Port Enable bits
1= PMA<13:3> function as EPMP address lines
0= PMA<13:3> function as port I/Os
PTEN<2:0>: PMALU/PMALH/PMALL Strobe Enable bits
1= PMA<2:0> function as either address lines or address latch strobes
0= PMA<2:0> function as port I/Os
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REGISTER 20-5: PMCSxCF: CHIP SELECT x CONFIGURATION REGISTER
R/W-0
CSDIS
R/W-0
CSP
R/W-0
R/W-0
BEP
U-0
—
R/W-0
WRSP
R/W-0
RDSP
R/W-0
SM
CSPTEN
bit 15
bit 8
R/W-0
ACKP
R/W-0
R/W-0
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
PTSZ1
PTSZ0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
-n = Value at POR
bit 15
bit 14
bit 13
bit 12
CSDIS: Chip Select x Disable bit
1= Disable the Chip Select x functionality
0= Enable the Chip Select x functionality
CSP: Chip Select x Polarity bit
1= Active-high (PMCSx)
0= Active-low (PMCSx)
CSPTEN: PMCSx Port Enable bit
1= PMCSx port is enabled
0= PMCSx port is disabled
BEP: Chip Select x Nibble/Byte Enable Polarity bit
1= Nibble/Byte enable is active-high (PMBE0, PMBE1)
0= Nibble/Byte enable is active-low (PMBE0, PMBE1)
bit 11
bit 10
Unimplemented: Read as ‘0’
WRSP: Chip Select x Write Strobe Polarity bit
For Slave modes and Master mode when SM = 0:
1= Write strobe is active-high (PMWR)
0= Write strobe is active-low (PMWR)
For Master mode when SM = 1:
1= Enable strobe is active-high (PMENB)
0= Enable strobe is active-low (PMENB)
bit 9
RDSP: Chip Select x Read Strobe Polarity bit
For Slave modes and Master mode when SM = 0:
1= Read strobe is active-high (PMRD)
0= Read strobe is active-low (PMRD)
For Master mode when SM = 1:
1= Read/write strobe is active-high (PMRD/PMWR)
0= Read/Write strobe is active-low (PMRD/PMWR)
bit 8
SM: Chip Select x Strobe Mode bit
1= Read/write and enable strobes (PMRD/PMWR and PMENB)
0= Read and write strobes (PMRD and PMWR)
bit 7
ACKP: Chip Select x Acknowledge Polarity bit
1= ACK is active-high (PMACK1)
0= ACK is active-low (PMACK1)
bit 6-5
PTSZ<1:0>: Chip Select x Port Size bits
11= Reserved
10= 16-bit port size (PMD<15:0>)
01= 4-bit port size (PMD<3:0>)
00= 8-bit port size (PMD<7:0>)
bit 4-0
Unimplemented: Read as ‘0’
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REGISTER 20-6: PMCSxBS: CHIP SELECT x BASE ADDRESS REGISTER(2)
R/W(1)
R/W(1)
R/W(1)
R/W(1)
R/W(1)
R/W(1)
R/W(1)
R/W(1)
BASE23
BASE22
BASE21
BASE20
BASE19
BASE18
BASE17
BASE16
bit 15
bit 8
R/W(1)
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
BASE15
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
-n = Value at POR
bit 15-8
bit 6-0
BASE<23:15>: Chip Select x Base Address bits(1)
Unimplemented: Read as ‘0’
Note 1: The value at POR is 0080h for PMCS1BS and 0880h for PMCS2BS.
2: If the whole PMCS2BS register is written together as 0x0000, then the last EDS address for the Chip
Select 1 will be FFFFFFh. In this case, Chip Select 2 should not be used. PMCS1BS has no such feature.
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REGISTER 20-7: PMCSxMD: CHIP SELECT x MODE REGISTER
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
U-0
—
U-0
—
U-0
—
ACKM1
ACKM0
AMWAIT2
AMWAIT1
AMWAIT0
bit 15
bit 8
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
DWAITB1
DWAITB0
DWAITM3
DWAITM2
DWAITM1
DWAITM0
DWAITE1
DWAITE0
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-14
ACKM<1:0>: Chip Select x Acknowledge Mode bits
11= Reserved
10= PMACKx is used to determine when a read/write operation is complete
01= PMACKx is used to determine when a read/write operation is complete with time-out
(If DWAITM<3:0> = 0000, the maximum time-out is 255 TCY or else it is DWAITM<3:0> cycles.)
00= PMACKx is not used
bit 13-11
AMWAIT<2:0>: Chip Select x Alternate Master Wait States bits
111= Wait of 10 alternate master cycles
. . .
001= Wait of 4 alternate master cycles
000= Wait of 3 alternate master cycles
bit 10-8
bit 7-6
Unimplemented: Read as ‘0’
DWAITB<1:0>: Chip Select x Data Setup Before Read/Write Strobe Wait States bits
11= Wait of 3¼ TCY
10= Wait of 2¼ TCY
01= Wait of 1¼ TCY
00= Wait of ¼ TCY
bit 5-2
DWAITM<3:0>: Chip Select x Data Read/Write Strobe Wait States bits
For Write Operations:
1111= Wait of 15½ TCY
. . .
0001= Wait of 1½ TCY
0000= Wait of ½ TCY
For Read Operations:
1111= Wait of 15¾ TCY
. . .
0001= Wait of 1¾ TCY
0000= Wait of ¾ TCY
bit 1-0
DWAITE<1:0>: Chip Select x Data Hold After Read/Write Strobe Wait States bits
For Write Operations:
11= Wait of 3¼ TCY
10= Wait of 2¼ TCY
01= Wait of 1¼ TCY
00= Wait of ¼ TCY
For Read Operations:
11= Wait of 3 TCY
10= Wait of 2 TCY
01= Wait of 1 TCY
00= Wait of 0 TCY
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REGISTER 20-8: PMSTAT: EPMP STATUS REGISTER (SLAVE MODE ONLY)
R-0, HSC
IBF
R/W-0 HS
IBOV
U-0
—
U-0
—
R-0, HSC
IB3F(1)
R-0, HSC
IB2F(1)
R-0, HSC
IB1F(1)
R-0, HSC
IB0F(1)
bit 15
bit 8
R-1, HSC
OBE
R/W-0 HS
OBUF
U-0
—
U-0
—
R-1, HSC
OB3E
R-1, HSC
OB2E
R-1, HSC
OB1E
R-1, HSC
OB0E
bit 7
bit 0
Legend:
HS = Hardware Settable bit
W = Writable bit
HSC = Hardware Settable/Clearable bit
U = Unimplemented bit, read as ‘0’
R = Readable bit
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15
bit 14
IBF: Input Buffer Full Status bit
1= All writable Input Buffer registers are full
0= Some or all of the writable Input Buffer registers are empty
IBOV: Input Buffer Overflow Status bit
1= A write attempt to a full Input register occurred (must be cleared in software)
0= No overflow occurred
bit 13-12
bit 11-8
Unimplemented: Read as ‘0’
IB3F:IB0F: Input Buffer x Status Full bits(1)
1= Input buffer contains unread data (reading the buffer will clear this bit)
0= Input buffer does not contain unread data
bit 7
bit 6
OBE: Output Buffer Empty Status bit
1= All readable Output Buffer registers are empty
0= Some or all of the readable Output Buffer registers are full
OBUF: Output Buffer Underflow Status bit
1= A read occurred from an empty output register (must be cleared in software)
0= No underflow occurred
bit 5-4
bit 3-0
Unimplemented: Read as ‘0’
OB3E:OB0E: Output Buffer x Status Empty bit
1= Output buffer is empty (writing data to the buffer will clear this bit)
0= Output buffer contains untransmitted data
Note 1: Even though an individual bit represents the byte in the buffer, the bits corresponding to the word (Byte 0
and 1, or Byte 2 and 3) get cleared, even on byte reading.
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REGISTER 20-9: PADCFG1: PAD CONFIGURATION CONTROL REGISTER
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
bit 15
bit 8
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
R/W-0
PMPTTL
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-1
bit 0
Unimplemented: Read as ‘0’
PMPTTL: EPMP Module TTL Input Buffer Select bit
1= EPMP module inputs (PMDx, PMCS1) use TTL input buffers
0= EPMP module inputs use Schmitt Trigger input buffers
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NOTES:
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The module has these features:
21.0 LIQUID CRYSTAL DISPLAY
(LCD) CONTROLLER
• Direct driving of LCD panel
• Three LCD clock sources with selectable prescaler
Note:
This data sheet summarizes the features of
• Up to eight commons:
this group of PIC24F devices. It is not
intended to be a comprehensive reference
source. For more information, refer to the
“PIC24F Family Reference Manual”,
Section 52. “Liquid Crystal Display
(LCD)” (DS39740). The information in this
data sheet supersedes the information in
the FRM.
- Static (One common)
- 1/2 multiplex (two commons)
- 1/3 multiplex (three commons)
- 1/8 multiplex (eight commons)
• Ability to drive from 30 (in 64-pin devices) to
64 (100-pin) segments, depending on the
Multiplexing mode selected
• Static, 1/2 or 1/3 LCD bias
The Liquid Crystal Display (LCD) Controller generates
the data and timing control required to directly drive a
static or multiplexed LCD panel. In 100-pin devices
(PIC24FJXXXGA310), the module can drive panels of
up to eight commons and up to 60 segments when 5 to
8 commons are used, or up to 64 segments when 1 to
4 commons are used.
• On-chip bias generator with dedicated charge
pump to support a range of fixed and variable bias
options
• Internal resistors for bias voltage generation
• Software contrast control for LCD using internal
biasing
A simplified block diagram of the module is shown in
Figure 21-1.
FIGURE 21-1:
LCD CONTROLLER MODULE BLOCK DIAGRAM
Data Bus
LCD DATA
32 x 16 (= 8 x 64)
LCDDATA31
LCDDATA30
512
to
64
.
.
.
64
SEG<63:0>
MUX
LCDDATA1
LCDDATA0
16
Bias
Voltage
To I/O Pins
Timing Control
8
LCDCON
LCDPS
LCDSEx
COM<7:0>
LCD Bias Generation
LCDREG
LCDREF
Resistor Ladder
FRC Oscillator
LPRC Oscillator
SOSC
LCD Clock
LCD
Charge Pump
Source Select
(Secondary Oscillator)
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21.1 Registers
The LCD controller has up to 40 registers:
• LCD Control Register (LCDCON)
• LCD Charge Pump Control Register (LCDREG)
• LCD Phase Register (LCDPS)
• LCD Voltage Ladder Control Register (LCDREF)
• Four LCD Segment Enable Registers
(LCDSE3:LCDSE0)
• Up to 32 LCD Data Registers
(LCDDATA31:LCDDATA0)
REGISTER 21-1: LCDCON: LCD CONTROL REGISTER
R/W-0
U-0
—
R/W-0
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
LCDEN
LCDSIDL
bit 15
bit 8
U-0
—
R/W-0
R/C-0
R/W-0
CS1
R/W-0
CS0
R/W-0
R/W-0
R/W-0
SLPEN
WERR
LMUX2
LMUX1
LMUX0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
-n = Value at POR
bit 15
LCDEN: LCD Driver Enable bit
1= LCD driver module is enabled
0= LCD driver module is disabled
bit 14
bit 13
Unimplemented: Read as ‘0’
LCDSIDL: Stop LCD Drive in CPU Idle Mode Control bit
1= LCD driver Halts in CPU Idle mode
0= LCD driver continues to operate in CPU Idle mode
bit 12-7
bit 6
Unimplemented: Read as ‘0’
SLPEN: LCD Driver Enable in Sleep mode bit
1= LCD driver module is disabled in Sleep mode
0= LCD driver module is enabled in Sleep mode
bit 5
WERR: LCD Write Failed Error bit
1= LCDDATAx register is written while WA (LCDPS<4>) = 0(must be cleared in software)
0= No LCD write error
bit 4-3
CS<1:0>: Clock Source Select bits
00= FRC
01= LPRC
1x= SOSC
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REGISTER 21-1: LCDCON: LCD CONTROL REGISTER (CONTINUED)
bit 2-0 LMUX<2:0>: Commons Select bits
LMUX<2:0>
Multiplex
Bias
111
110
101
100
011
010
001
000
1/8 MUX (COM<7:0>)
1/7 MUX (COM<6:0>)
1/6 MUX (COM<5:0>)
1/5 MUX (COM<4:0>)
1/4 MUX (COM<3:0>)
1/3 MUX (COM<2:0>)
1/2 MUX (COM<1:0>)
Static (COM0)
1/3
1/3
1/3
1/3
1/3
1/2 or 1/3
1/2 or 1/3
Static
Note:
For multiplex above 4 commons, COM4, COM5, COM6 and COM7 also have segment
functionality. Therefore, if the COM is enabled in multiplexing, the segment will not be
available on that pin.
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REGISTER 21-2: LCDREG: LCD CHARGE PUMP CONTROL REGISTER
RW-0
CPEN(1)
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
bit 15
bit 8
U-0
—
U-0
—
RW-1
RW-1
RW-1
RW-1
RW-0
RW-0
BIAS2
BIAS1
BIAS0
MODE13
CKSEL1
CKSEL0
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15
CPEN: 3.6V Charge Pump Enable bit(1)
1= The regulator generates the highest (3.6V) voltage
0= Highest voltage in the system is supplied externally (AVDD)
bit 14-6
bit 5-3
Unimplemented: Read as ‘0’
BIAS<2:0>: Regulator Voltage Output Control bits
111= 3.60V peak (offset on LCDBIAS0 of 0V)
110= 3.47V peak (offset on LCDBIAS0 of 0.13V)
101= 3.34V peak (offset on LCDBIAS0 of 0.26V)
100= 3.21V peak (offset on LCDBIAS0 of 0.39V)
011= 3.08V peak (offset on LCDBIAS0 of 0.52V)
010= 2.95V peak (offset on LCDBIAS0 of 0.65V)
001= 2.82V peak (offset on LCDBIAS0 of 0.78V)
000= 2.69V peak (offset on LCDBIAS0 of 0.91V)
bit 2
MODE13: 1/3 LCD Bias Enable bit
1= Regulator output supports 1/3 LCD Bias mode
0= Regulator output supports Static LCD Bias mode
bit 1-0
CLKSEL<1:0>: Regulator Clock Select Control bits
11= LPRC 31 kHz
10= 8 MHz FRC
01= SOSC
00= Disable regulator and float regulator voltage output
Note 1: When using the charge pump, the LCDBIASx pins and the VLCAP1/VLACAP2 pins should be made analog,
and the respective TRIS bits should be set as inputs.
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REGISTER 21-3: LCDPS: LCD PHASE REGISTER
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
bit 15
bit 8
R/W-0
WFT
R/W-0
R-0
R-0
WA
R/W-0
LP3
R/W-0
LP2
R/W-0
LP1
R/W-0
LP0
BIASMD
LCDA
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
-n = Value at POR
bit 15-8
bit 7
Unimplemented: Read as ‘0’
WFT: Waveform Type Select bit
1= Type-B waveform (phase changes on each frame boundary)
0= Type-A waveform (phase changes within each common type)
bit 6
BIASMD: Bias Mode Select bit
When LMUX<2:0> = 000 or 011 through 111:
0= Static Bias mode (do not set this bit to ‘1’)
When LMUX<2:0> = 001 or 010:
1= 1/2 Bias mode
0= 1/3 Bias mode
bit 5
LCDA: LCD Active Status bit
1= LCD driver module is active
0= LCD driver module is inactive
bit 4
WA: LCD Write Allow Status bit
1= Write into the LCDDATAx registers is allowed
0= Write into the LCDDATAx registers is not allowed
bit 3-0
LP<3:0>: LCD Prescaler Select bits
1111 = 1:16
1110= 1:15
1101= 1:14
1100= 1:13
1011= 1:12
1010= 1:11
1001= 1:10
1000= 1:9
0111= 1:8
0110= 1:7
0101= 1:6
0100= 1:5
0011= 1:4
0010= 1:3
0001= 1:2
0000= 1:1
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REGISTER 21-4: LCDSEx: LCD SEGMENT x ENABLE REGISTER
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
SE(n+15)
SE(n+14)
SE(n+13)
SE(n+12)
SE(n+11)
SE(n+10)
SE(n+9)
SE(n+8)
bit 15
bit 8
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
SE(n)
SE(n+7)
SE(n+6)
SE(n+5)
SE(n+4)
SE(n+3)
SE(n+2)
SE(n+1)
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
-n = Value at POR
bit 7-0
SE(n + 15):SE(n): Segment Enable bits
For LCDSE0: n = 0
For LCDSE1: n = 16
For LCDSE2: n = 32
For LCDSE3: n = 48(1)
1= Segment function of the pin is enabled, digital I/O is disabled
0= Segment function of the pin is disabled, digital I/O is enabled
Note 1: For the SEG49 to work correctly, the JTAG needs to be disabled.
REGISTER 21-5: LCDDATAx: LCD DATA x REGISTER
R/W-0
S(n+15)Cy
bit 15
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
S(n+14)Cy
S(n+13)Cy
S(n+12)Cy
S(n+11)Cy
S(n+10)Cy
S(n+9)Cy
S(n+8)Cy
bit 8
R/W-0
S(n+7)Cy
bit 7
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
S(n+6)Cy
S(n+5)Cy
S(n+4)Cy
S(n+3)Cy
S(n+2)Cy
S(n+1)Cy
S(n)Cy
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-0
S(n + 15)Cy:S(n)Cy: Pixel On bits
For registers, LCDDATA0 through LCDDATA3: n = (16x), y = 0
For registers, LCDDATA4 through LCDDATA7: n = (16(x - 4)), y = 1
For registers, LCDDATA8 through LCDDATA11: n = (16(x - 8)), y = 2
For registers, LCDDATA12 through LCDDATA15: n = (16(x - 12)), y = 3
For registers, LCDDATA16 through LCDDATA19: n = (16(x-16)), y = 4
For registers, LCDDATA20 through LCDDATA23: n = (16(x - 20)), y = 5
For registers, LCDDATA24 through LCDDATA27: n = (16(x - 24)), y = 6
For registers, LCDDATA28 through LCDDATA31: n = (16(x - 28)), y = 7
1= Pixel is on
0= Pixel is off
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TABLE 21-1: LCDDATA REGISTERS AND BITS FOR SEGMENT AND COM COMBINATIONS
Segments
COM Lines
0 to 15
16 to 31
32 to 47
48 to 64
LCDDATA0
S00C0:S15C0
LCDDATA1
S16C0:S31C0
LCDDATA2
S32C0:S47C0
LCDDATA3
S48C0:S63C0
0
1
2
3
4
5
6
7
LCDDATA4
S00C1:S15C1
LCDDATA5
S16C1:S31C1
LCDDATA6
S32C1:S47C1
LCDDATA7
S48C1:S63C1
LCDDATA8
S00C2:S15C2
LCDDATA9
S16C2:S31C2
LCDDATA10
S32C2:S47C2
LCDDATA11
S48C2:S63C2
LCDDATA12
S00C3:S15C3
LCDDATA13
S16C3:S31C3
LCDDATA14
S32C3:S47C3
LCDDATA15
S48C3:S63C3
LCDDATA16
S00C4:S15C4
LCDDATA17
S16C4:S31C4
LCDDATA18
S32C4:S47C4
LCDDATA19
S48C4:S59C4
LCDDATA20
S00C5:S15C5
LCDDATA21
S16C5:S31C5
LCDDATA22
S32C5:S47C5
LCDDATA23
S48C5:S69C5
LCDDATA24
S00C6:S15C6
LCDDATA25
S16C6:S31C6
LCDDATA26
S32C6:S47C6
LCDDATA27
S48C6:S59C6
LCDDATA28
S00C7:S15C7
LCDDATA29
S16C7:S31C7
LCDDATA30
S32C7:S47C7
LCDDATA31
S48C7:S59C7
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REGISTER 21-6: LCDREF: LCD REFERENCE LADDER CONTROL REGISTER
R/W-0
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
VLCD1E(1)
LCDIRE
LCDCST2
LCDCST1
LCDCST0 VLCD3PE(1) VLCD2E(1)
bit 15
bit 8
R/W-0
R/W-0
R/W-0
R/W-0
U-0
—
R/W-0
R/W-0
R/W-0
LRLAP1
LRLAP0
LRLBP1
LRLBP0
LRLAT2
LRLAT1
LRLAT0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
-n = Value at POR
bit 15
LCDIRE: LCD Internal Reference Enable bit
1= Internal LCD reference is enabled and connected to the internal contrast control circuit
0= Internal LCD reference is disabled
bit 14
Unimplemented: Read as ‘0’
bit 13-11
LCDCST<2:0>: LCD Contrast Control bits
Selects the resistance of the LCD contrast control resistor ladder:
111= Resistor ladder is at maximum resistance (minimum contrast)
110= Resistor ladder is at 6/7th of maximum resistance
101= Resistor ladder is at 5/7th of maximum resistance
100= Resistor ladder is at 4/7th of maximum resistance
011= Resistor ladder is at 3/7th of maximum resistance
010= Resistor ladder is at 2/7th of maximum resistance
001= Resistor ladder is at 1/7th of maximum resistance
000= Minimum resistance (maximum contrast); resistor ladder is shorted
bit 10
bit 9
VLCD3PE: Bias 3 Pin Enable bit(1)
1= Bias 3 level is connected to the external pin, LCDBIAS3
0= Bias 3 level is internal (internal resistor ladder)
VLCD2PE: Bias 2 Pin Enable bit(1)
1= Bias 2 level is connected to the external pin, LCDBIAS2
0= Bias 2 level is internal (internal resistor ladder)
bit 8
VLCD1PE: Bias 1 Pin Enable bit(1)
1= Bias 1 level is connected to the external pin, LCDBIAS1
0= Bias 1 level is internal (internal resistor ladder)
bit 7-6
LRLAP<1:0>: LCD Reference Ladder A Time Power Control bits
During Time Interval A:
11= Internal LCD reference ladder is powered in High-Power mode
10= Internal LCD reference ladder is powered in Medium Power mode
01= Internal LCD reference ladder is powered in Low-Power mode
00= Internal LCD reference ladder is powered down and unconnected
bit 5-4
LRLBP<1:0>: LCD Reference Ladder B Time Power Control bits
During Time Interval B:
11= Internal LCD reference ladder is powered in High-Power mode
10= Internal LCD reference ladder is powered in Medium Power mode
01= Internal LCD reference ladder is powered in Low-Power mode
00= Internal LCD reference ladder is powered down and unconnected
bit 3
Unimplemented: Read as ‘0’
Note 1: When using the external resistor ladder biasing, the LCDBIASx pins should be made analog and the
respective TRIS bits should be set as inputs.
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REGISTER 21-6: LCDREF: LCD REFERENCE LADDER CONTROL REGISTER (CONTINUED)
bit 2-0
LRLAT<2:0>: LCD Reference Ladder A Time Interval Control bits
Sets the number of 32 clock counts when the A Time Interval Power mode is active.
For Type-A Waveforms (WFT = 0):
111= Internal LCD reference ladder is in A Power mode for 7 clocks and B Power mode for 9 clocks
110= Internal LCD reference ladder is in A Power mode for 6 clocks and B Power mode for 10 clocks
101= Internal LCD reference ladder is in A Power mode for 5 clocks and B Power mode for 11 clocks
100= Internal LCD reference ladder is in A Power mode for 4 clocks and B Power mode for 12 clocks
011= Internal LCD reference ladder is in A Power mode for 3 clocks and B Power mode for 13 clocks
010= Internal LCD reference ladder is in A Power mode for 2 clocks and B Power mode for 14 clocks
001= Internal LCD reference ladder is in A Power mode for 1 clock and B Power mode for 15 clocks
000= Internal LCD reference ladder is always in B Power mode
For Type-B Waveforms (WFT = 1):
111= Internal LCD reference ladder is in A Power mode for 7 clocks and B Power mode for 25 clocks
110= Internal LCD reference ladder is in A Power mode for 6 clocks and B Power mode for 26 clocks
101= Internal LCD reference ladder is in A Power mode for 5 clocks and B Power mode for 27 clocks
100= Internal LCD reference ladder is in A Power mode for 4 clocks and B Power mode for 28 clocks
011= Internal LCD reference ladder is in A Power mode for 3 clocks and B Power mode for 29 clocks
010= Internal LCD reference ladder is in A Power mode for 2 clocks and B Power mode for 30 clocks
001= Internal LCD reference ladder is in A Power mode for 1 clock and B Power mode for 31 clocks
000= Internal LCD reference ladder is always in B Power mode
Note 1: When using the external resistor ladder biasing, the LCDBIASx pins should be made analog and the
respective TRIS bits should be set as inputs.
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NOTES:
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• BCD format for smaller software overhead
• Optimized for long-term battery operation
• User calibration of the 32.768 kHz clock
crystal/32K INTRC frequency with periodic
auto-adjust
22.0 REAL-TIME CLOCK AND
CALENDAR (RTCC)
Note:
This data sheet summarizes the features of
this group of PIC24F devices. It is not
intended to be a comprehensive reference
source. For more information on the
Real-Time Clock and Calendar, refer to the
“PIC24F Family Reference Manual”,
Section 29. “Real-Time Clock and
Calendar (RTCC)” (DS39696).
• Optimized for long term battery operation
• Fractional second synchronization
• Calibration to within ±2.64 seconds error per
month
• Calibrates up to 260 ppm of crystal error
• Ability to periodically wake up external devices
without CPU intervention (external power control)
The RTCC provides the user with a Real-Time Clock
and Calendar (RTCC) function that can be calibrated.
• Power control output for external circuit control
• Calibration takes effect every 15 seconds
• Runs from any one of the following:
- External Real-Time Clock (RTC) of 32.768 kHz
- Internal 31.25 kHz LPRC clock
Key features of the RTCC module are:
• Operates in Deep Sleep mode
• Selectable clock source
• Provides hours, minutes and seconds using
24-hour format
- 50 Hz or 60 Hz external input
• Visibility of one half second period
• Provides calendar – weekday, date, month and
year
22.1 RTCC Source Clock
The user can select between the SOSC crystal
oscillator, LPRC internal oscillator or an external
50 Hz/60 Hz power line input as the clock reference for
the RTCC module. This gives the user an option to
trade off system cost, accuracy and power
consumption, based on the overall system needs.
• Alarm-configurable for half a second, one second,
10 seconds, one minute, 10 minutes, one hour,
one day, one week, one month or one year
• Alarm repeat with decrementing counter
• Alarm with indefinite repeat chime
• Year 2000 to 2099 leap year correction
FIGURE 22-1:
RTCC BLOCK DIAGRAM
Input from
SOSC/LPRC
Oscillator or
External Source
RTCC Clock Domain
CPU Clock Domain
RCFGCAL
RTCC Prescalers
0.5 Sec
ALCFGRPT
YEAR
MTHDY
WKDYHR
MINSEC
RTCC Timer
RTCVAL
Alarm
Event
Comparator
Alarm Registers with Masks
Repeat Counter
ALMTHDY
ALWDHR
ALRMVAL
ALMINSEC
RTCOE
RTCC
RTCOUT<1:0>
Interrupt
RTCC Interrupt Logic
Alarm
Pulse
00
1s
01
10
Clock Source
RTCC
Pin
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TABLE 22-2: ALRMVAL REGISTER
22.2 RTCC Module Registers
MAPPING
The RTCC module registers are organized into three
categories:
Alarm Value Register Window
ALRMPTR
<1:0>
• RTCC Control Registers
• RTCC Value Registers
• Alarm Value Registers
ALRMVAL<15:8> ALRMVAL<7:0>
00
01
10
11
ALRMMIN
ALRMWD
ALRMMNTH
—
ALRMSEC
ALRMHR
ALRMDAY
—
22.2.1
REGISTER MAPPING
To limit the register interface, the RTCC Timer and
Alarm Time registers are accessed through
corresponding register pointers. The RTCC Value
register window (RTCVALH and RTCVALL) uses the
RTCPTR bits (RCFGCAL<9:8>) to select the desired
Timer register pair (see Table 22-1).
Considering that the 16-bit core does not distinguish
between 8-bit and 16-bit read operations, the user must
be aware that when reading either the ALRMVALH or
ALRMVALL bytes, the ALRMPTR<1:0> value will be
decremented. The same applies to the RTCVALH or
RTCVALL bytes with the RTCPTR<1:0> being
decremented.
By writing the RTCVALH byte, the RTCC Pointer value,
the RTCPTR<1:0> bits decrement by one until they
reach ‘00’. Once they reach ‘00’, the MINUTES and
SECONDS value will be accessible through RTCVALH
and RTCVALL until the pointer value is manually
changed.
Note:
This only applies to read operations and
not write operations.
22.2.2
WRITE LOCK
TABLE 22-1: RTCVAL REGISTER MAPPING
In order to perform a write to any of the RTCC Timer
registers, the RTCWREN bit (RCFGCAL1<13>) must
be set (see Example 22-1).
RTCC Value Register Window
RTCPTR<1:0>
RTCVAL<15:8> RTCVAL<7:0>
Note:
To avoid accidental writes to the timer, it is
recommended that the RTCWREN bit
(RCFGCAL1<13>) is kept clear at any
other time. For the RTCWREN bit to be
set, there is only one instruction cycle time
window allowed between the 55h/AA
sequence and the setting of RTCWREN;
therefore, it is recommended that code
follow the procedure in Example 22-1.
00
01
10
11
MINUTES
WEEKDAY
MONTH
—
SECONDS
HOURS
DAY
YEAR
The Alarm Value register window (ALRMVALH and
ALRMVALL) uses the ALRMPTR bits
(ALCFGRPT<9:8>) to select the desired Alarm register
pair (see Table 22-2).
22.2.3
SELECTING RTCC CLOCK SOURCE
By writing the ALRMVALH byte, the Alarm Pointer
value, ALRMPTR<1:0> bits, decrement by one until
they reach ‘00’. Once they reach ‘00’, the ALRMMIN
and ALRMSEC value will be accessible through
ALRMVALH and ALRMVALL until the pointer value is
manually changed.
The clock source for the RTCC module can be selected
using the RTCLK<1:0> bits in the RTCPWC register.
When the bits are set to ‘00’, the Secondary Oscillator
(SOSC) is used as the reference clock and when the bits
are ‘01’, LPRC is used as the reference clock. When
RTCLK<1:0> = 10 and 11, the external power line
(50 Hz and 60 Hz) is used as the clock source.
EXAMPLE 22-1:
SETTING THE RTCWREN BIT
asm volatile(“push w7”);
asm volatile(“push w8”);
asm volatile(“disi #5”);
asm volatile(“mov #0x55, w7”);
asm volatile(“mov w7, _NVMKEY”);
asm volatile(“mov #0xAA, w8”);
asm volatile(“mov w8, _NVMKEY”);
asm volatile(“bset _RCFGCAL1, #13”); //set the RTCWREN bit
asm volatile(“pop w8”);
asm volatile(“pop w7”);
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22.3 Registers
22.3.1 RTCC CONTROL REGISTERS
REGISTER 22-1: RCFGCAL: RTCC CALIBRATION/CONFIGURATION REGISTER(1)
R/W-0
RTCEN(2)
U-0
—
R/W-0
R-0, HSC
RTCSYNC HALFSEC(3)
R-0, HSC
R/W-0
R/W-0
R/W-0
RTCWREN
RTCOE
RTCPTR1
RTCPTR0
bit 15
bit 8
R/W-0
CAL7
R/W-0
CAL6
R/W-0
CAL5
R/W-0
CAL4
R/W-0
CAL3
R/W-0
CAL2
R/W-0
CAL1
R/W-0
CAL0
bit 7
bit 0
Legend:
HSC = Hardware Settable/Clearable bit
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15
RTCEN: RTCC Enable bit(2)
1= RTCC module is enabled
0= RTCC module is disabled
bit 14
bit 13
Unimplemented: Read as ‘0’
RTCWREN: RTCC Value Registers Write Enable bit
1= RTCVALH and RTCVALL registers can be written to by the user
0= RTCVALH and RTCVALL registers are locked out from being written to by the user
bit 12
RTCSYNC: RTCC Value Registers Read Synchronization bit
1= RTCVALH, RTCVALL and ALCFGRPT registers can change while reading due to a rollover ripple
resulting in an invalid data read. If the register is read twice and results in the same data, the data
can be assumed to be valid.
0= RTCVALH, RTCVALL or ALCFGRPT registers can be read without concern over a rollover ripple
bit 11
bit 10
bit 9-8
HALFSEC: Half Second Status bit(3)
1= Second half period of a second
0= First half period of a second
RTCOE: RTCC Output Enable bit
1= RTCC output is enabled
0= RTCC output is disabled
RTCPTR<1:0>: RTCC Value Register Window Pointer bits
Points to the corresponding RTCC Value registers when reading the RTCVALH and RTCVALL registers.
The RTCPTR<1:0> value decrements on every read or write of RTCVALH until it reaches ‘00’.
RTCVAL<15:8>:
11= Reserved
10= MONTH
01= WEEKDAY
00= MINUTES
RTCVAL<7:0>:
11= YEAR
10= DAY
01= HOURS
00= SECONDS
Note 1: The RCFGCAL register is only affected by a POR.
2: A write to the RTCEN bit is only allowed when RTCWREN = 1.
3: This bit is read-only; it is cleared to ‘0’ on a write to the lower half of the MINSEC register.
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REGISTER 22-1: RCFGCAL: RTCC CALIBRATION/CONFIGURATION REGISTER(1) (CONTINUED)
bit 7-0
CAL<7:0>: RTC Drift Calibration bits
01111111= Maximum positive adjustment; adds 127 RTC clock pulses every 15 seconds
.
.
.
01111111= Minimum positive adjustment; adds 1 RTC clock pulse every 15 seconds
00000000= No adjustment
11111111= Minimum negative adjustment; subtracts 1 RTC clock pulse every 15 seconds
.
.
.
10000000= Maximum negative adjustment; subtracts 128 RTC clock pulses every 15 seconds
Note 1: The RCFGCAL register is only affected by a POR.
2: A write to the RTCEN bit is only allowed when RTCWREN = 1.
3: This bit is read-only; it is cleared to ‘0’ on a write to the lower half of the MINSEC register.
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REGISTER 22-2: RTCPWC: RTCC POWER CONTROL REGISTER(1)
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
PWCEN
PWCPOL
PWCPRE
PWSPRE
RTCLK1(2)
RTCLK0(2)
RTCOUT1
RTCOUT0
bit 15
bit 8
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
-n = Value at POR
bit 15
PWCEN: Power Control Enable bit
1= Power control is enabled
0= Power control is disabled
bit 14
PWCPOL: Power Control Enable bit
1= Power control is enabled
0= Power control is disabled
bit 13
PWCPRE: Power Control/Stability Prescaler bits
1= PWC stability window clock is divide-by-2 of source RTCC clock
0= PWC stability window clock is divide-by-1 of source RTCC clock
bit 12
PWSPRE: Power Control Sample Prescaler bits
1= PWC sample window clock is divide-by-2 of source RTCC clock
0= PWC sample window clock is divide-by-1 of source RTCC clock
bit 11-10
RTCLK<1:0>: RTCC Clock Source Select bits(2)
11= External power line (60 Hz)
10= External power line source (50 Hz)
01= Internal LPRC Oscillator
00= External Secondary Oscillator (SOSC)
bit 9-8
RTCOUT<1:0>: RTCC Output Source Select bits
11= Power control
10= RTCC clock
01= RTCC seconds clock
00= RTCC alarm pulse
bit 7-0
Unimplemented: Read as ‘0’
Note 1: The RTCPWC register is only affected by a POR.
2: When a new value is written to these register bits, the lower half of the MINSEC register should also be
written to properly reset the clock prescalers in the RTCC.
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REGISTER 22-3: ALCFGRPT: ALARM CONFIGURATION REGISTER
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
ALRMEN
CHIME
AMASK3
AMASK2
AMASK1
AMASK0
ALRMPTR1 ALRMPTR0
bit 8
bit 15
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
ARPT7
ARPT6
ARPT5
ARPT4
ARPT3
ARPT2
ARPT1
ARPT0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
-n = Value at POR
bit 15
ALRMEN: Alarm Enable bit
1= Alarm is enabled (cleared automatically after an alarm event whenever ARPT<7:0> = 00h and
CHIME = 0)
0= Alarm is disabled
bit 14
CHIME: Chime Enable bit
1= Chime is enabled; ARPT<7:0> bits are allowed to roll over from 00h to FFh
0= Chime is disabled; ARPT<7:0> bits stop once they reach 00h
bit 13-10
AMASK<3:0>: Alarm Mask Configuration bits
0000= Every half second
0001= Every second
0010= Every 10 seconds
0011= Every minute
0100= Every 10 minutes
0101= Every hour
0110= Once a day
0111= Once a week
1000= Once a month
1001= Once a year (except when configured for February 29th, once every 4 years)
101x= Reserved – do not use
11xx= Reserved – do not use
bit 9-8
ALRMPTR<1:0>: Alarm Value Register Window Pointer bits
Points to the corresponding Alarm Value registers when reading the ALRMVALH and ALRMVALL registers.
The ALRMPTR<1:0> value decrements on every read or write of ALRMVALH until it reaches ‘00’.
ALRMVAL<15:8>:
00= ALRMMIN
01= ALRMWD
10= ALRMMNTH
11= PWCSTAB
ALRMVAL<7:0>:
00= ALRMSEC
01= ALRMHR
10= ALRMDAY
11= PWCSAMP
bit 7-0
ARPT<7:0>: Alarm Repeat Counter Value bits
11111111= Alarm will repeat 255 more times
.
.
.
00000000= Alarm will not repeat
The counter decrements on any alarm event; it is prevented from rolling over from 00h to FFh unless
CHIME = 1.
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22.3.2
RTCVAL REGISTER MAPPINGS
REGISTER 22-4: YEAR: YEAR VALUE REGISTER(1)
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
bit 15
bit 8
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
YRTEN3
YRTEN2
YRTEN2
YRTEN1
YRONE3
YRONE2
YRONE1
YRONE0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
-n = Value at POR
bit 15-8
bit 7-4
Unimplemented: Read as ‘0’
YRTEN<3:0>: Binary Coded Decimal Value of Year’s Tens Digit bits
Contains a value from 0 to 9.
bit 3-0
YRONE<3:0>: Binary Coded Decimal Value of Year’s Ones Digit bits
Contains a value from 0 to 9.
Note 1: A write to the YEAR register is only allowed when RTCWREN = 1.
REGISTER 22-5: MTHDY: MONTH AND DAY VALUE REGISTER(1)
U-0
—
U-0
—
U-0
—
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
MTHTEN0
MTHONE3
MTHONE2
MTHONE1
MTHONE0
bit 15
bit 8
U-0
—
U-0
—
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
DAYTEN1
DAYTEN0
DAYONE3
DAYONE2
DAYONE1
DAYONE0
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-13
bit 12
Unimplemented: Read as ‘0’
MTHTEN0: Binary Coded Decimal Value of Month’s Tens Digit bit
Contains a value of ‘0’ or ‘1’.
bit 11-8
MTHONE<3:0>: Binary Coded Decimal Value of Month’s Ones Digit bits
Contains a value from 0 to 9.
bit 7-6
bit 5-4
Unimplemented: Read as ‘0’
DAYTEN<1:0>: Binary Coded Decimal Value of Day’s Tens Digit bits
Contains a value from 0 to 3.
bit 3-0
DAYONE<3:0>: Binary Coded Decimal Value of Day’s Ones Digit bits
Contains a value from 0 to 9.
Note 1: A write to this register is only allowed when RTCWREN = 1.
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REGISTER 22-6: WKDYHR: WEEKDAY AND HOURS VALUE REGISTER(1)
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
R/W-x
R/W-x
R/W-x
WDAY2
WDAY1
WDAY0
bit 15
bit 8
U-0
—
U-0
—
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
HRTEN1
HRTEN0
HRONE3
HRONE2
HRONE1
HRONE0
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-11
bit 10-8
Unimplemented: Read as ‘0’
WDAY<2:0>: Binary Coded Decimal Value of Weekday Digit bits
Contains a value from 0 to 6.
bit 7-6
bit 5-4
Unimplemented: Read as ‘0’
HRTEN<1:0>: Binary Coded Decimal Value of Hour’s Tens Digit bits
Contains a value from 0 to 2.
bit 3-0
HRONE<3:0>: Binary Coded Decimal Value of Hour’s Ones Digit bits
Contains a value from 0 to 9.
Note 1: A write to this register is only allowed when RTCWREN = 1.
REGISTER 22-7: MINSEC: MINUTES AND SECONDS VALUE REGISTER
U-0
—
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
MINTEN2
MINTEN1
MINTEN0
MINONE3
MINONE2
MINONE1
MINONE0
bit 15
bit 8
U-0
—
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
SECTEN2
SECTEN1
SECTEN0
SECONE3
SECONE2
SECONE1
SECONE0
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15
Unimplemented: Read as ‘0’
bit 14-12
MINTEN<2:0>: Binary Coded Decimal Value of Minute’s Tens Digit bits
Contains a value from 0 to 5.
bit 11-8
MINONE<3:0>: Binary Coded Decimal Value of Minute’s Ones Digit bits
Contains a value from 0 to 9.
bit 7
Unimplemented: Read as ‘0’
bit 6-4
SECTEN<2:0>: Binary Coded Decimal Value of Second’s Tens Digit bits
Contains a value from 0 to 5.
bit 3-0
SECONE<3:0>: Binary Coded Decimal Value of Second’s Ones Digit bits
Contains a value from 0 to 9.
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22.3.3
ALRMVAL REGISTER MAPPINGS
REGISTER 22-8: ALMTHDY: ALARM MONTH AND DAY VALUE REGISTER(1)
U-0
—
U-0
—
U-0
—
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
MTHTEN0
MTHONE3
MTHONE2
MTHONE1
MTHONE0
bit 15
bit 8
U-0
—
U-0
—
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
DAYTEN1
DAYTEN0
DAYONE3
DAYONE2
DAYONE1
DAYONE0
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-13
bit 12
Unimplemented: Read as ‘0’
MTHTEN0: Binary Coded Decimal Value of Month’s Tens Digit bit
Contains a value of ‘0’ or ‘1’.
bit 11-8
MTHONE<3:0>: Binary Coded Decimal Value of Month’s Ones Digit bits
Contains a value from 0 to 9.
bit 7-6
bit 5-4
Unimplemented: Read as ‘0’
DAYTEN<1:0>: Binary Coded Decimal Value of Day’s Tens Digit bits
Contains a value from 0 to 3.
bit 3-0
DAYONE<3:0>: Binary Coded Decimal Value of Day’s Ones Digit bits
Contains a value from 0 to 9.
Note 1: A write to this register is only allowed when RTCWREN = 1.
REGISTER 22-9: ALWDHR: ALARM WEEKDAY AND HOURS VALUE REGISTER(1)
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
R/W-x
R/W-x
R/W-x
WDAY2
WDAY1
WDAY0
bit 15
bit 8
U-0
—
U-0
—
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
HRTEN1
HRTEN0
HRONE3
HRONE2
HRONE1
HRONE0
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-11
bit 10-8
Unimplemented: Read as ‘0’
WDAY<2:0>: Binary Coded Decimal Value of Weekday Digit bits
Contains a value from 0 to 6.
bit 7-6
bit 5-4
Unimplemented: Read as ‘0’
HRTEN<1:0>: Binary Coded Decimal Value of Hour’s Tens Digit bits
Contains a value from 0 to 2.
bit 3-0
HRONE<3:0>: Binary Coded Decimal Value of Hour’s Ones Digit bits
Contains a value from 0 to 9.
Note 1: A write to this register is only allowed when RTCWREN = 1.
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REGISTER 22-10: ALMINSEC: ALARM MINUTES AND SECONDS VALUE REGISTER
U-0
—
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
MINTEN2
MINTEN1
MINTEN0
MINONE3
MINONE2
MINONE1
MINONE0
bit 15
bit 8
U-0
—
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
SECTEN2
SECTEN1
SECTEN0
SECONE3
SECONE2
SECONE1
SECONE0
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15
Unimplemented: Read as ‘0’
bit 14-12
MINTEN<2:0>: Binary Coded Decimal Value of Minute’s Tens Digit bits
Contains a value from 0 to 5.
bit 11-8
MINONE<3:0>: Binary Coded Decimal Value of Minute’s Ones Digit bits
Contains a value from 0 to 9.
bit 7
Unimplemented: Read as ‘0’
bit 6-4
SECTEN<2:0>: Binary Coded Decimal Value of Second’s Tens Digit bits
Contains a value from 0 to 5.
bit 3-0
SECONE<3:0>: Binary Coded Decimal Value of Second’s Ones Digit bits
Contains a value from 0 to 9.
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REGISTER 22-11: RTCCSWT: POWER CONTROL AND SAMPLE WINDOW TIMER REGISTER(1)
R/W-x
PWCSTAB7
bit 15
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
PWCSTAB6
PWCSTAB5
PWCSTAB4
PWCSTAB3
PWCSTAB2
PWCSTAB1
PWCSTAB0
bit 8
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
PWCSAMP7
bit 7
PWCSAMP6
PWCSAMP5
PWCSAMP4
PWCSAMP3
PWCSAMP2
PWCSAMP1
PWCSAMP0
bit 0
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
-n = Value at POR
bit 15-8
bit 7-0
PWCSTAB<7:0>: Power Control Stability Window Timer bits
11111111= Stability Window is 255 TPWCCLK clock periods
11111110= Stability Window is 254 TPWCCLK clock periods
...
00000001= Stability Window is 1 TPWCCLK clock period
00000000= No Stability Window; Sample Window starts when the alarm event triggers
(2)
PWCSAMP<7:0>: Power Control Sample Window Timer bits
11111111= Sample Window is always enabled, even when PWCEN = 0
11111110= Sample Window is 254 TPWCCLK clock periods
...
00000001= Sample Window is 1 TPWCCLK clock period
00000000= No Sample Window
Note 1: A write to this register is only allowed when RTCWREN = 1.
2: The Sample Window always starts when the Stability Window timer expires, except when its initial value is 00h.
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22.5.1
CONFIGURING THE ALARM
22.4 Calibration
The alarm feature is enabled using the ALRMEN bit.
This bit is cleared when an alarm is issued. Writes to
ALRMVAL should only take place when ALRMEN = 0.
The real-time crystal input can be calibrated using the
periodic auto-adjust feature. When properly calibrated,
the RTCC can provide an error of less than 3 seconds
per month. This is accomplished by finding the number
of error clock pulses and storing the value into the
lower half of the RCFGCAL register. The 8-bit signed
value loaded into the lower half of RCFGCAL is
multiplied by four and will either be added or subtracted
from the RTCC timer, once every minute. Refer to the
steps below for RTCC calibration:
As shown in Figure 22-2, the interval selection of the
alarm is configured through the AMASK bits
(ALCFGRPT<13:10>). These bits determine which and
how many digits of the alarm must match the clock
value for the alarm to occur.
The alarm can also be configured to repeat based on a
preconfigured interval. The amount of times this
occurs, once the alarm is enabled, is stored in the
ARPT<7:0> bits (ALCFGRPT<7:0>). When the value
of the ARPT bits equals 00h and the CHIME bit
(ALCFGRPT<14>) is cleared, the repeat function is
disabled and only a single alarm will occur. The alarm
can be repeated, up to 255 times, by loading
ARPT<7:0> with FFh.
1. Using another timer resource on the device, the
user must find the error of the 32.768 kHz crystal.
2. Once the error is known, it must be converted to
the number of error clock pulses per minute.
3. a) If the oscillator is faster than ideal (negative
result form Step 2), the RCFGCAL register value
must be negative. This causes the specified
number of clock pulses to be subtracted from
the timer counter, once every minute.
After each alarm is issued, the value of the ARPT bits
is decremented by one. Once the value has reached
00h, the alarm will be issued one last time, after which,
the ALRMEN bit will be cleared automatically and the
alarm will turn off.
b) If the oscillator is slower than ideal (positive
result from Step 2), the RCFGCAL register value
must be positive. This causes the specified
number of clock pulses to be subtracted from
the timer counter, once every minute.
Indefinite repetition of the alarm can occur if the
CHIME bit = 1. Instead of the alarm being disabled
when the value of the ARPT bits reaches 00h, it rolls
over to FFh and continues counting indefinitely while
CHIME is set.
EQUATION 22-1:
(Ideal Frequency† – Measured Frequency) * 60 =
Clocks per Minute
22.5.2
ALARM INTERRUPT
†
Ideal Frequency = 32,768 Hz
At every alarm event, an interrupt is generated. In
addition, an alarm pulse output is provided that
operates at half the frequency of the alarm. This output
is completely synchronous to the RTCC clock and can
be used as a trigger clock to other peripherals.
Writes to the lower half of the RCFGCAL register
should only occur when the timer is turned off, or
immediately after the rising edge of the seconds pulse,
except when SECONDS = 00, 15, 30 or 45. This is due
to the auto-adjust of the RTCC at 15 second intervals.
Note:
Changing any of the registers, other than
the RCFGCAL and ALCFGRPT registers,
and the CHIME bit while the alarm is
enabled (ALRMEN = 1), can result in a
false alarm event leading to a false alarm
interrupt. To avoid a false alarm event, the
timer and alarm values should only be
changed while the alarm is disabled
(ALRMEN = 0). It is recommended that
the ALCFGRPT register and CHIME bit be
changed when RTCSYNC = 0.
Note:
It is up to the user to include, in the error
value, the initial error of the crystal: drift
due to temperature and drift due to crystal
aging.
22.5 Alarm
• Configurable from half second to one year
• Enabled using the ALRMEN bit
(ALCFGRPT<15>)
• One-time alarm and repeat alarm options
available
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FIGURE 22-2:
ALARM MASK SETTINGS
Day of
the
Week
Alarm Mask Setting
(AMASK<3:0>)
Month
Day
Hours
Minutes
Seconds
0000- Every half second
0001- Every second
0010- Every 10 seconds
0011- Every minute
0100- Every 10 minutes
0101- Every hour
s
s
s
s
s
s
s
s
s
s
s
s
s
s
s
m
m
m
m
m
m
m
m
m
m
m
0110- Every day
h
h
h
h
h
h
h
h
0111- Every week
1000- Every month
d
d
d
d
(1)
1001- Every year
m
m
d
Note 1: Annually, except when configured for February 29.
22.6 POWER CONTROL
22.7 RTCC VBAT OPERATION
The RTCC includes a power control feature that allows
the device to periodically wake-up an external device,
wait for the device to be stable before sampling
wake-up events from that device, and then shut down
the external device. This can be done completely
autonomously by the RTCC, without the need to wake
from the current lower power mode (Sleep, Deep
Sleep, etc.).
The RTCC can operate in VBAT mode when there is a
power loss on the VDD pin. The RTCC will continue to
operate if the VBAT pin is powered on (it is usually
connected to the battery).
Note:
It is recommended to connect the VBAT
pin to VDD if the VBAT mode is not used
(not connected to the battery).
The VBAT BOR can be enabled/disabled using the
VBTBOR bit in the CW3 Configuration register
(CW3<7>). If the VBTBOR enable bit is cleared, the
VBAT BOR is always disabled and there will be no indi-
cation of a VBAT BOR. If the VBTBOR bit is set, the
RTCC can receive a Reset and the RTCEN bit will get
cleared; it can happen anywhere between 1.95-1.4V
(typical).
To use this feature:
1. Enable the RTCC (RTCEN = 1).
2. Set the PWCEN bit (RTCPWC<15>).
3. Configure the RTCC pin to drive the PWC control
signal (RTCOE = 1and RTCOUT<1:0> = 11).
The polarity of the PWC control signal may be chosen
using the PWCPOL bit (RTCPWC<14>). An active-low
or active-high signal may be used with the appropriate
external switch to turn on or off the power to one or
more external devices. The active-low setting may also
be used in conjunction with an open-drain setting on
the RTCC pin, in order to drive the ground pin(s) of the
external device directly (with the appropriate external
VDD pull-up device), without the need for external
switches. Finally, the CHIME bit should be set to enable
the PWC periodicity.
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NOTES:
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The 32-bit programmable CRC generator provides a
hardware implemented method of quickly generating
checksums for various networking and security
applications. It offers the following features:
23.0 32-BIT PROGRAMMABLE
CYCLIC REDUNDANCY CHECK
(CRC) GENERATOR
• User-programmable CRC polynomial equation,
up to 32 bits
Note:
This data sheet summarizes the features of
this group of PIC24F devices. It is not
intended to be a comprehensive reference
source. For more information, refer to the
“PIC24F Family Reference Manual”,
Section 41. “32-Bit Programmable
Cyclic Redundancy Check (CRC)”
(DS39729). The information in this data
sheet supersedes the information in the
FRM.
• Programmable shift direction (little or big-endian)
• Independent data and polynomial lengths
• Configurable interrupt output
• Data FIFO
Figure 23-1 displays a simplified block diagram of the
CRC generator. A simple version of the CRC shift
engine is displayed in Figure 23-2.
FIGURE 23-1:
CRC BLOCK DIAGRAM
CRCDATH
CRCDATL
FIFO Empty
Variable FIFO
(4x32, 8x16 or 16x8)
Event
CRCISEL
1
0
CRCWDATH
CRCWDATL
CRC
Interrupt
LENDIAN
Shift Buffer
1
0
CRC Shift Engine
Shift
Complete
Event
Shifter Clock
2 * FCY
FIGURE 23-2:
CRC SHIFT ENGINE DETAIL
CRC Shift Engine
CRCWDATH
CRCWDATL
Read/Write Bus
X1
(1)
X0
Xn
Shift Buffer
Data
(1)
Bit 0
Bit 1
Bit n
Note 1: n = PLEN<4:1> + 1.
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23.1.2
DATA INTERFACE
23.1 User Interface
The module incorporates a FIFO that works with a
variable data width. Input data width can be configured
to any value between 1 and 32 bits using the
DWIDTH<4:0> bits (CRCCON2<12:8>). When the
data width is greater than 15, the FIFO is 4 words deep.
When the DWITDH bits are between 15 and 8, the
FIFO is 8 words deep. When the DWIDTH bits are less
than 8, the FIFO is 16 words deep.
23.1.1
POLYNOMIAL INTERFACE
The CRC module can be programmed for CRC
polynomials of up to the 32nd order, using up to 32 bits.
Polynomial length, which reflects the highest exponent
in the equation, is selected by the PLEN<4:0> bits
(CRCCON2<4:0>).
The CRCXORL and CRCXORH registers control which
exponent terms are included in the equation. Setting a
particular bit includes that exponent term in the equa-
tion. Functionally, this includes an XOR operation on
the corresponding bit in the CRC engine. Clearing the
bit disables the XOR.
The data for which the CRC is to be calculated must
first be written into the FIFO. Even if the data width is
less than 8, the smallest data element that can be writ-
ten into the FIFO is 1 byte. For example, if the DWIDTH
bits are 5, then the size of the data is
DWIDTH<4:0> + 1 or 6. The data is written as a whole
byte; the two unused upper bits are ignored by the
module.
For example, consider two CRC polynomials, one a
16-bit and the other a 32-bit equation.
Once data is written into the MSb of the CRCDAT reg-
isters (that is, the MSb as defined by the data width),
the value of the VWORD<4:0> bits (CRCCON1<12:8>)
increments by one. For example, if the DWIDTH bits
are 24, the VWORD bits will increment when bit 7 of
CRCDATH is written. Therefore, CRCDATL must
always be written to before CRCDATH.
EQUATION 23-1: 16-BIT, 32-BIT CRC
POLYNOMIALS
X16 + X12 + X5 + 1
and
X32+X26 + X23 + X22 + X16 + X12 + X11 + X10 +
X8 + X7 + X5 + X4 + X2 + X + 1
The CRC engine starts shifting data when the CRCGO
bit is set and the value of the VWORD bits is greater
than zero.
Each word is copied out of the FIFO into a buffer regis-
ter, which decrements the VWORD bits. The data is
then shifted out of the buffer. The CRC engine contin-
ues shifting at a rate of two bits per instruction cycle,
until the VWORD bits reach zero. This means that for a
given data width, it takes half that number of instruc-
tions for each word to complete the calculation. For
example, it takes 16 cycles to calculate the CRC for a
single word of 32-bit data.
To program these polynomial into the CRC generator,
set the register bits, as shown in Table 23-1.
Note that the appropriate positions are set to ‘1’ to indi-
cate that they are used in the equation (for example,
X26 and X23). The ‘0’ bit required by the equation is
always XORed; thus, X0 is a don’t care. For a poly-
nomial of length 32, it is assumed that the 32nd bit will
be used. Therefore, the X<31:1> bits do not have the
32nd bit.
When the VWORD bits reach the maximum value for
the configured value of the DWIDTH bits (4, 8 or 16),
the CRCFUL bit becomes set. When the VWORD bits
reach zero, the CRCMPT bit becomes set. The FIFO is
emptied and the VWORD<4:0> bits are set to ‘00000’
whenever CRCEN is ‘0’.
At least one instruction cycle must pass after a write to
CRCWDAT before a read of the VWORD bits is done.
TABLE 23-1: CRC SETUP EXAMPLES FOR 16 AND 32-BIT POLYNOMIALS
Bit Values
CRC Control Bits
16-Bit Polynomial
32-Bit Polynomial
PLEN<4:0>
X<31:16>
X<15:0>
01111
11111
0000 0000 0000 0001
0001 0000 0010 000X
0000 0100 1100 0001
0001 1101 1011 011x
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3. Preload the FIFO by writing to the CRCDATL
and CRCDATH registers until the CRCFUL bit is
23.1.3
DATA SHIFT DIRECTION
The LENDIAN bit (CRCCON1<3>) is used to control
the shift direction. By default, the CRC will shift data
through the engine, MSb first. Setting LENDIAN (= 1)
causes the CRC to shift data, LSb first. This setting
allows better integration with various communication
schemes and removes the overhead of reversing the
bit order in software. Note that this only changes the
direction the data is shifted into the engine. The result
of the CRC calculation will still be a normal CRC result,
not a reverse CRC result.
set or no data is left.
4. Clear old results by writing 00h to CRCWDATL
and CRCWDATH. The CRCWDAT registers can
also be left unchanged to resume a previously
halted calculation.
5. Set the CRCGO bit to start calculation.
6. Write remaining data into the FIFO as space
becomes available.
7. When the calculation completes, CRCGO is
automatically cleared. An interrupt will be
generated if CRCISEL = 1.
23.1.4
INTERRUPT OPERATION
The module generates an interrupt that is configurable
by the user for either of two conditions.
8. Read CRCWDATL and CRCWDATH for the
result of the calculation.
If CRCISEL is ‘0’, an interrupt is generated when the
VWORD<4:0> bits make a transition from a value of ‘1’
to ‘0’. If CRCISEL is ‘1’, an interrupt will be generated
after the CRC operation finishes and the module sets
the CRCGO bit to ‘0’. Manually setting CRCGO to ‘0’
will not generate an interrupt. Note that when an
interrupt occurs, the CRC calculation would not yet be
complete. The module will still need (PLEN + 1)/2 clock
cycles after the interrupt is generated until the CRC
calculation is finished.
There are eight registers used to control programmable
CRC operation:
• CRCCON1
• CRCCON2
• CRCXORL
• CRCXORH
• CRCDATL
• CRCDATH
• CRCWDATL
• CRCWDATH
23.1.5
TYPICAL OPERATION
The
CRCCON1
and
CRCCON2
registers
To use the module for a typical CRC calculation:
1. Set the CRCEN bit to enable the module.
(Register 23-1 and Register 23-2) control the operation
of the module and configure the various settings.
2. Configure the module for desired operation:
a) Program the desired polynomial using the
CRCXORL and CRCXORH registers, and the
PLEN<4:0> bits.
The CRCXOR registers (Register 23-3 and
Register 23-4) select the polynomial terms to be used
in the CRC equation. The CRCDAT and CRCWDAT
registers are each register pairs that serve as buffers
for the double-word input data and CRC processed
output, respectively.
b) Configure the data width and shift direction
using the DWIDTH and LENDIAN bits.
c) Select the desired Interrupt mode using the
CRCISEL bit.
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REGISTER 23-1: CRCCON1: CRC CONTROL 1 REGISTER
R/W-0
U-0
—
R/W-0
CSIDL
R-0, HSC
VWORD4
R-0, HSC
VWORD3
R-0, HSC
VWORD2
R-0, HSC
VWORD1
R-0, HSC
VWORD0
CRCEN
bit 15
bit 8
R-0, HSC
CRCFUL
R-1, HSC
CRCMPT
R/W-0
R/W-0, HC
CRCGO
R/W-0
U-0
—
U-0
—
U-0
—
CRCISEL
LENDIAN
bit 7
bit 0
Legend:
HC = Hardware Clearable bit
W = Writable bit
HSC = Hardware Settable/Clearable bit
U = Unimplemented bit, read as ‘0’
R = Readable bit
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15
CRCEN: CRC Enable bit
1= Enables module
0= Disables module; all state machines, pointers and CRCWDAT/CRCDATH registers reset; other
SFRs are NOT reset
bit 14
bit 13
Unimplemented: Read as ‘0’
CSIDL: CRC Stop in Idle Mode bit
1= Discontinue module operation when device enters Idle mode
0= Continue module operation in Idle mode
bit 12-8
bit 7
VWORD<4:0>: Pointer Value bits
Indicates the number of valid words in the FIFO. Has a maximum value of 8 when PLEN<4:0> 7 or 16
when PLEN<4:0> 7.
CRCFUL: FIFO Full bit
1= FIFO is full
0= FIFO is not full
bit 6
CRCMPT: FIFO Empty bit
1= FIFO is empty
0= FIFO is not empty
bit 5
CRCISEL: CRC Interrupt Selection bit
1= Interrupt on FIFO is empty; the final word of data is still shifting through the CRC
0= Interrupt on shift is complete and results are ready
bit 4
CRCGO: Start CRC bit
1= Start CRC serial shifter
0= CRC serial shifter is turned off
bit 3
LENDIAN: Data Shift Direction Select bit
1= Data word is shifted into the CRC, starting with the LSb (little endian)
0= Data word is shifted into the CRC, starting with the MSb (big endian)
bit 2-0
Unimplemented: Read as ‘0’
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REGISTER 23-2: CRCCON2: CRC CONTROL 2 REGISTER
U-0
—
U-0
—
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
DWIDTH4
DWIDTH3
DWIDTH2
DWIDTH1
DWIDTH0
bit 15
bit 8
U-0
—
U-0
—
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
PLEN4
PLEN3
PLEN2
PLEN1
PLEN0
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-13
bit 12-8
Unimplemented: Read as ‘0’
DWIDTH<4:0>: Data Word Width Configuration bits
Configures the width of the data word (Data Word Width – 1).
Unimplemented: Read as ‘0’
bit 7-5
bit 4-0
PLEN<4:0>: Polynomial Length Configuration bits
Configures the length of the polynomial (Polynomial Length – 1).
REGISTER 23-3: CRCXORL: CRC XOR POLYNOMIAL REGISTER, LOW BYTE
R/W-0
X15
R/W-0
X14
R/W-0
X13
R/W-0
X12
R/W-0
X11
R/W-0
X10
R/W-0
X9
R/W-0
X8
bit 15
bit 8
R/W-0
X7
R/W-0
X6
R/W-0
X5
R/W-0
X4
R/W-0
X3
R/W-0
X2
R/W-0
X1
U-0
—
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-1
bit 0
X<15:1>: XOR of Polynomial Term xn Enable bits
Unimplemented: Read as ‘0’
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REGISTER 23-4: CRCXORH: CRC XOR HIGH REGISTER
R/W-0
X31
R/W-0
X30
R/W-0
X29
R/W-0
X28
R/W-0
X27
R/W-0
X26
R/W-0
X25
R/W-0
X24
bit 15
bit 8
R/W-0
X23
R/W-0
X22
R/W-0
X21
R/W-0
X20
R/W-0
X19
R/W-0
X18
R/W-0
X17
R/W-0
X16
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-0
X<31:16>: XOR of Polynomial Term xn Enable bits
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24.1 Basic Operation
24.0 12-BIT A/D CONVERTER WITH
THRESHOLD SCAN
To perform a standard A/D conversion:
1. Configure the module:
Note:
This data sheet summarizes the features
of this group of PIC24F devices. It is not
intended to be a comprehensive refer-
ence source. For more information on the
12-Bit A/D Converter, refer to the “PIC24F
Family Reference Manual”, Section 51.
“12-Bit A/D Converter with Threshold
Detect” (DS39739).
a) Configure port pins as analog inputs by
setting the appropriate bits in the ANSELn
registers (see Section 11.2 “Configuring
Analog Port Pins (ANSx)” for more
information).
b) Select the voltage reference source to
match expected range on analog inputs
(AD1CON2<15:13>).
The 12-bit A/D Converter has the following key
features:
c) Select the positive and negative multiplexer
inputs for each channel (AD1CHS<15:0>).
• Successive Approximation Register (SAR)
Conversion
d) Select the analog conversion clock to match
the desired data rate with the processor
clock (AD1CON3<7:0>).
• Conversion Speeds of up to 200 ksps
• Up to 32 Analog Input Channels (internal and
external)
e) Select the appropriate sample/conversion
sequence
(AD1CON1<7:5>
and
• Selectable 10-Bit or 12-Bit (default) Conversion
Resolution
AD1CON3<12:8>).
f) For Channel A scanning operations, select
the positive channels to be included
(AD1CSSH and AD1CSSL registers).
• Multiple Internal Reference Input Channels
• External Voltage Reference Input Pins
g) Select how conversion results are
presented in the buffer (AD1CON1<9:8>
and AD1CON5 register).
• Unipolar Differential Sample-and-Hold (S/H)
Amplifier
• Automated Threshold Scan and Compare
Operation to Pre-Evaluate Conversion Results
h) Select the interrupt rate (AD1CON2<5:2>).
i) Turn on A/D module (AD1CON1<15>).
2. Configure the A/D interrupt (if required):
a) Clear the AD1IF bit (IFS0<13>).
• Selectable Conversion Trigger Source
• Fixed Length (one word per channel),
Configurable Conversion Result Buffer
• Four Options for Results Alignment
• Configurable Interrupt Generation
b) Enable the AD1IE interrupt (IEC0<13>).
c) Select the A/D interrupt priority (IPC3<6:4>).
• Enhanced DMA Operations with Indirect Address
Generation
3. If the module is configured for manual sampling,
set the SAMP bit (AD1CON1<1>) to begin
sampling.
• Operation During CPU Sleep and Idle modes
The 12-bit A/D Converter module is an enhanced ver-
sion of the 10-bit module offered in earlier PIC24
devices. It is a Successive Approximation Register
(SAR) Converter, enhanced with 12-bit resolution, a
wide range of automatic sampling options, tighter inte-
gration with other analog modules and a configurable
results buffer.
It also includes a unique Threshold Detect feature that
allows the module itself to make simple decisions
based on the conversion results, and enhanced opera-
tion with the DMA Controller through Peripheral Indirect
Addressing (PIA).
A simplified block diagram for the module is shown in
Figure 24-1.
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FIGURE 24-1:
12-BIT A/D CONVERTER BLOCK DIAGRAM (PIC24FJ128GA310 FAMILY)
Internal Data Bus
16
AVDD
AVSS
VREF+
VREF-
VBG
VR+
VR-
Comparator
VINH
VINL
VR- VR+
DAC
S/H
AN0
AN1
AN2
12-Bit SAR
Conversion Logic
Data Formatting
VINH
Extended DMA data
AN14
AN15
ADC1BUF0:
ADC1BUF25
(1)
(2)
AN16
VINL
AD1CON1
AD1CON2
AD1CON3
AD1CON4
AD1CON5
AD1CHS
(1)
AN21
(1)
AN22
VINH
AD1CHITL
(1)
AN23
AD1CHITH
AD1CSSL
AD1CSSH
VBG
VINL
VBG/2
VBG/6
VBAT/2
AD1DMBUF
Sample Control
AVDD
AVSS
Control Logic
Conversion Control
16
Input MUX Control
CTMU
DMA Data Bus
Note 1: AN16 through AN23 are implemented on 100-pin devices only.
2: A/D result buffers are numbered in hexadecimal; ADC1BUF0 through ADC1BUF19 represent Buffers 1 through 26.
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The IA is created by combining the base address within
a channel buffer with three to five bits (depending on
24.2 Extended DMA Operations
In addition to the standard features available on all
12-bit A/D Converters, PIC24FJ128GA310 family
devices implement a limited extension of DMA func-
tionality. This extension adds features that work with
the device’s DMA Controller to expand the A/D
module’s data storage abilities beyond the module’s
built-in buffer.
the buffer size) to identify the channel. The base
address ranges from zero to seven bits wide, depend-
ing on the buffer size. The address is right-padded with
a ‘0’ in order to maintain address alignment in the data
space. The concatenated channel and base address
bits are then left-padded with zeroes, as necessary, to
complete the 11-bit IA.
The Extended DMA functionality is controlled by the
DMAEN bit (AD1CON1<10>); setting this bit enables
the functionality. The DMABM bit (AD1CON1<11>)
configures how the DMA feature operates.
The IA is configured to auto-increment during write
operations by using the SMPI bits (AD1CON2<6:2>).
As with PIA operations for any DMA-enabled module,
the base destination address in the DMADST register
must be masked properly to accommodate the IA.
Table 24-1 shows how complete addresses are
formed. Note that the address masking varies for each
buffer size option. Because of masking requirements,
some address ranges may not be available for certain
buffer sizes. Users should verify that the DMA base
address is compatible with the buffer size selected.
24.2.1
EXTENDED BUFFER MODE
Extended Buffer mode (DMABM = 1) is useful for stor-
ing the results of conversions on the upper channels
(i.e., 26 and above), which do not have their own
memory mapped buffers inside the A/D module. It can
also be used to store the conversion results on any A/D
channel in any implemented address in data RAM.
Figure 24-2 shows how the parts of the address define
the buffer locations in data memory. In this case, the
module “allocates” 256 bytes of data RAM (1000h to
1100h) for 32 buffers of four words each. However, this
is not a hard allocation and nothing prevents these
locations from being used for other purposes. For
example, in the current case, if Analog Channels 1, 3
and 8 are being sampled and converted, conversion
data will only be written to the channel buffers, starting
at 1008h, 1018h and 1040h. The holes in PIA buffer
space can be used for any other purpose. It is the
user’s responsibility to keep track of buffer locations
and preventing data overwrites.
In Extended Buffer mode, all data from the A/D Buffer
register, and channels above 26, is mapped into data
RAM. Conversion data is written to a destination
specified by the DMA Controller, specifically by the
DMADST register. This allows users to read the con-
version results of channels above 26, which do not
have their own memory mapped A/D buffer locations,
from data memory.
When using Extended Buffer mode, always set the
BUFREGEN bit to disable FIFO operation. In addition,
disable the Split Buffer mode by clearing the BUFM bit.
24.2.2
PIA MODE
24.3 A/D Operation with VBAT
When DMABM = 0, the A/D module is configured to
function with the DMA controller for Peripheral Indirect
Addressing (PIA) mode operations. In this mode, the
A/D module generates an 11-bit Indirect Address (IA).
This is ORed with the destination address in the DMA
Controller to define where the A/D conversion data will
be stored.
One of the A/D channels is connected to the VBAT pin
to monitor the VBAT voltage. This allows monitoring the
VBAT pin voltage (battery voltage) with no external con-
nection. The voltage measured, using the A/D VBAT
monitor, is VBAT/2. The voltage can be calculated by
reading A/D = ((VBAT/2)/VDD) * 1024 for 10-bit A/D and
((VBAT/2)/VDD) * 4096 for 12 bit A/D.
In PIA mode, the buffer space is created as a series of
contiguous smaller buffers, one per analog channel. The
size of the channel buffer determines how many analog
channels can be accommodated. The size of the buffer
is selected by the DMABL bits (AD1CON4<2:0>). The
size options range from a single word per buffer to
128 words. Each channel is allocated a buffer of this
size, regardless of whether or not the channel will
actually have conversion data.
When using the VBAT A/D monitor:
• Connect the A/D channel to ground to discharge
the sample capacitor.
• Because of the high-impedance of VBAT, select
higher sampling time to get an accurate reading.
Since the VBAT pin is connected to the A/D during
sampling, to prolong the VBAT battery life, the
recommendation is to select the VBAT channel when
needed.
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• AD1CSSH and AD1CSSL (Register 24-10 and
Register 24-11)
24.4 Registers
The 12-bit A/D Converter is controlled through a total of
13 registers:
• AD1CTMENH and AD1CTMENL (Register 24-12
and Register 24-13)
• AD1CON1 through AD1CON5 (Register 24-1
through Register 24-5)
• AD1DMBUF (not shown) – The 16-bit conversion
buffer for Extended Buffer mode
• AD1CS (Register 24-6)
• AD1CHITH and AD1CHITL (Register 24-8 and
Register 24-9)
TABLE 24-1: INDIRECT ADDRESS GENERATION IN PIA MODE
Available
Input
Channels
Buffer Size per
Channel (words)
Generated Offset
Address (lower 11 bits)
Allowable DMADST
Addresses
DMABL<2:0>
000
001
010
011
100
101
110
111
1
2
000 00cc ccc0
000 0ccc ccn0
000 cccc cnn0
00c cccc nnn0
0cc cccn nnn0
ccc ccnn nnn0
ccc cnnn nnn0
ccc nnnn nnn0
32
32
32
32
32
32
16
8
xxxx xxxx xx00 0000
xxxx xxxx x000 0000
xxxx xxxx 0000 0000
xxxx xxx0 0000 0000
xxxx xx00 0000 0000
xxxx x000 0000 0000
xxxx x000 0000 0000
xxxx x000 0000 0000
4
8
16
32
64
128
Legend: ccc= Channel number (three to five bits), n= Base buffer address (zero to seven bits),
x= User-definable range of DMADST for base address, 0= Masked bits of DMADST for IA.
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FIGURE 24-2:
EXAMPLE OF BUFFER ADDRESS GENERATION IN PIA MODE
(4-WORD BUFFERS PER CHANNEL)
DMABL<2:0> = 010
(16-Word Buffer Size)
A/D Module
(PIA Mode)
Data RAM
BBA Channel
1000h
1008h
1010h
1018h
Ch 0 Buffer (4 Words)
Ch 1 Buffer (4 Words)
Ch 2 Buffer (4 Words)
Ch 3 Buffer (4 Words)
ccccc (0-31)
000 cccc cnn0 (IA)
nn (0-3)
(Buffer Base Address)
Destination
Range
1038h
Ch 7 Buffer (4 Words)
1000h (DMA Base Address)
Ch 8 Buffer (4 Words) 1040h
10F0h
10F8h
Ch 29 Buffer (4 Words)
Ch 29 Buffer (4 Words)
Ch 31 Buffer (4 Words)
DMADST
1100h
DMA Channel
Buffer Address
Channel Address
Address Mask
DMA Base Address
0001 0000 0000 0000
0001 0000 0000 0010
0001 0000 0000 0100
0001 0000 0000 0110
0001 0000 0000 1000
0001 0000 0000 1010
1000h
Ch 0, Word 0
Ch 0, Word 1
Ch 0, Word 2
Ch 0, Word 3
Ch 1, Word 0
Ch 1, Word 1
Ch 1, Word 2
Ch 1, Word 3
1002h
1004h
1006h
1008h
100Ah
100Ch 0001 0000 0000 1100
100Eh 0001 0000 0000 1110
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REGISTER 24-1: AD1CON1: A/D CONTROL REGISTER 1
R/W-0
ADON
U-0
—
R/W-0
R/W-0
DMABM(1)
R/W-0
R/W-0
R/W-0
R/W-0
ADSIDL
DMAEN
MODE12
FORM1
FORM0
bit 15
bit 8
R/W-0
R/W-0
R/W-0
R/W-0
U-0
—
R/W-0
ASAM
R/W-0, HCS R/C-0, HCS
SAMP DONE
bit 0
SSRC3
SSRC2
SSRC1
SSRC0
bit 7
Legend:
U = Unimplemented bit, read as ‘0’
R = Readable bit
W = Writable bit
‘1’ = Bit is set
HSC = Hardware Settable/Clearable bit
‘0’ = Bit is cleared x = Bit is unknown
-n = Value at POR
bit 15
ADON: A/D Operating Mode bit
1= A/D Converter module is operating
0= A/D Converter is off
bit 14
bit 13
Unimplemented: Read as ‘0’
ADSIDL: Stop in Idle Mode bit
1= Discontinue module operation when device enters Idle mode
0= Continue module operation in Idle mode
bit 12
bit 11
bit 10
bit 9-8
DMABM: Extended DMA Buffer Mode Select bit(1)
1= Extended Buffer mode: Buffer address is defined by the DMAnDST register
0= PIA mode: Buffer addresses are defined by the DMA controller and AD1CON4<2:0>
DMAEN: Extended DMA/Buffer Enable bit
1= Extended DMA and buffer features are enabled
0= Extended features are disabled
MODE12: 12-Bit Operation Mode bit
1= 12-bit A/D operation
0= 10-bit A/D operation
FORM<1:0>: Data Output Format bits (see formats following)
11= Fractional result, signed, left-justified
10= Absolute fractional result, unsigned, left-justified
01= Decimal result, signed, right-justified
00= Absolute decimal result, unsigned, right-justified
bit 7-4
SSRC<3:0>: Sample Clock Source Select bits
1xxx= Unimplemented, do not use
0111= Internal counter ends sampling and starts conversion (auto-convert). Do not use in
Auto-Scan mode
0110= Unimplemented
0101= TMR1
0100= CTMU
0011= TMR5
0010= TMR3
0001= INT0
0000= The SAMP bit must be cleared by software to start conversion
bit 3
bit 2
Unimplemented: Read as ‘0’
ASAM: A/D Sample Auto-Start bit
1= Sampling begins immediately after last conversion; SAMP bit is auto-set
0= Sampling begins when SAMP bit is manually set
Note 1: This bit is only available when Extended DMA/Buffer features are available (DMAEN = 1).
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REGISTER 24-1: AD1CON1: A/D CONTROL REGISTER 1 (CONTINUED)
bit 1
SAMP: A/D Sample Enable bit
1= A/D Sample-and-Hold amplifiers are sampling
0= A/D Sample-and-Hold amplifiers are holding
bit 0
DONE: A/D Conversion Status bit
1= A/D conversion cycle has completed
0= A/D conversion has not started or is in progress
Note 1: This bit is only available when Extended DMA/Buffer features are available (DMAEN = 1).
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REGISTER 24-2: AD1CON2: A/D CONTROL REGISTER 2
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
U-0
—
U-0
—
PVCFG1
PVCFG0
NVCFG0
OFFCAL
BUFREGEN
CSCNA
bit 15
bit 8
R/W-0
BUFS(1)
R/W-0
SMPI4
R/W-0
SMPI3
R/W-0
SMPI2
R/W-0
SMPI1
R/W-0
SMPI0
R/W-0
BUFM(1)
R/W-0
ALTS
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
-n = Value at POR
bit 15-14
PVCFG<1:0>: Converter Positive Voltage Reference Configuration bits
1x= Unimplemented, do not use
01= External VREF+
00= AVDD
bit 13
bit 12
bit 11
bit 10
NVCFG0: Converter Negative Voltage Reference Configuration bits
1= External VREF-
0= AVSS
OFFCAL: Offset Calibration Mode Select bit
1= Inverting and non-inverting inputs of channel Sample-and-Hold are connected to AVSS
0= Inverting and non-inverting inputs of channel Sample-and-Hold are connected to normal inputs
BUFREGEN: A/D Buffer Register Enable bit
1= Conversion result is loaded into the buffer location determined by the converted channel
0= A/D result buffer is treated as a FIFO
CSCNA: Scan Input Selections for CH0+ During Sample A bit
1= Scan inputs
0= Do not scan inputs
bit 9-8
bit 7
Unimplemented: Read as ‘0’
BUFS: Buffer Fill Status bit(1)
1= A/D is filling the upper half of the buffer; user should access data in the lower half
0= A/D is filling the lower half of the buffer; user should access data in the upper half
bit 6-2
SMPI<4:0>: Interrupt Sample/DMA Increment Rate Select bits
When DMAEN = 1:
0001= For 2-channel DMA A/D operation
0000= For 1-channel DMA A/D operation
When DMAEN = 0:
Selects the number of sample/conversions per each interrupt
11111= Interrupt/address increment at the completion of conversion for each 32nd sample
11110= Interrupt/address increment at the completion of conversion for each 31st sample
00001= Interrupt/address increment at the completion of conversion for every other sample
00000= Interrupt/address increment at the completion of conversion for each sample
Note 1: These bits are only applicable when the buffer is used in FIFO mode (BUFREGEN = 0). In addition, BUFS
is only used when BUFM = 1.
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REGISTER 24-2: AD1CON2: A/D CONTROL REGISTER 2 (CONTINUED)
bit 1
BUFM: Buffer Fill Mode Select bit(1)
1= A/D buffer is two, 13-word buffers, starting at ADC1BUF0 and ADC1BUF12, and sequential
conversions fill the buffers alternately (Split mode)
0= A/D buffer is a single, 26-word buffer and fills sequentially from ADC1BUF0 (FIFO mode)
bit 0
ALTS: Alternate Input Sample Mode Select bit
1= Uses channel input selects for Sample A on first sample and Sample B on next sample
0= Always uses channel input selects for Sample A
Note 1: These bits are only applicable when the buffer is used in FIFO mode (BUFREGEN = 0). In addition, BUFS
is only used when BUFM = 1.
REGISTER 24-3: AD1CON3: A/D CONTROL REGISTER 3
R/W-0
ADRC
R-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
EXTSAM
PUMPEN
SAMC4
SAMC3
SAMC2
SAMC1
SAMC0
bit 15
bit 8
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
ADCS7
ADCS6
ADCS5
ADCS4
ADCS3
ADCS2
ADCS1
ADCS0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
-n = Value at POR
bit 15
bit 14
bit 13
bit 12-8
ADRC: A/D Conversion Clock Source bit
1= RC Clock
0= Clock derived from system clock
EXTSAM: Extended Sampling Time bit
1= A/D is still sampling after SAMP = 0
0= A/D is finished sampling
PUMPEN: Charge Pump Enable bit
1= Charge pump for switches is enabled
0= Charge pump for switches is disabled
SAMC<4:0>: Auto-Sample Time Select bits
11111
00001
= 31 TAD
= 1 TAD
= 0 TAD
00000
bit 7-0
ADCS<7:0>: A/D Conversion Clock Select bits
11111111
= Reserved
01000000
00111111 = 64·TCY = TAD
00000001 = 2·TCY = TAD
00000000 = TCY = TAD
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REGISTER 24-4: AD1CON4: A/D CONTROL REGISTER 4
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
bit 15
bit 8
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
R/W-0
DMABL2(1)
R/W-0
DMABL1(1)
R/W-0
DMABL0(1)
bit 0
bit 7
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-3
bit 2-0
Unimplemented: Read as ‘0’
DMABL<2:0>: DMA Buffer Size Select bits(1)
111= Allocates 128 words of buffer to each analog input
110= Allocates 64 words of buffer to each analog input
101= Allocates 32 words of buffer to each analog input
100= Allocates 16 words of buffer to each analog input
011= Allocates 8 words of buffer to each analog input
010= Allocates 4 words of buffer to each analog input
001= Allocates 2 words of buffer to each analog input
000= Allocates 1 word of buffer to each analog input
Note 1: The DMABL<2:0> bits are only used when AD1CON1<11> = 1and AD1CON<12> = 0; otherwise, their
value is ignored.
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REGISTER 24-5: AD1CON5: A/D CONTROL REGISTER 5
R/W-0
ASEN
R/W-0
LPEN
R/W-0
R/W-0
U-0
—
U-0
—
R/W-0
R/W-0
CTMREQ
BGREQ
ASINT1
ASINT0
bit 15
bit 8
U-0
—
U-0
—
U-0
—
U-0
—
R/W-0
WM1
R/W-0
WM0
R/W-0
CM1
R/W-0
CM0
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15
bit 14
bit 13
bit 12
ASEN: Auto-Scan Enable bit
1= Auto-scan is enabled
0= Auto-scan is disabled
LPEN: Low-Power Enable bit
1= Low power is enabled after scan
0= Full power is enabled after scan
CTMREQ: CTMU Request bit
1= CTMU is enabled when the A/D is enabled and active
0= CTMU is not enabled by the A/D
BGREQ: Band Gap Request bit
1= Band gap is enabled when the A/D is enabled and active
0= Band gap is not enabled by the A/D
bit 11-10
bit 9-8
Unimplemented: Read as ‘0’
ASINT<1:0>: Auto-Scan (Threshold Detect) Interrupt Mode bits
11= Interrupt after Threshold Detect sequence completed and valid compare has occurred
10= Interrupt after valid compare has occurred
01= Interrupt after Threshold Detect sequence completed
00= No interrupt
bit 7-4
bit 3-2
Unimplemented: Read as ‘0’
WM<1:0>: Write Mode bits
11= Reserved
10= Auto-compare only (conversion results are not saved, but interrupts are generated when a valid
match occurs, as defined by the CM and ASINT bits)
01= Convert and save (conversion results are saved to locations as determined by the register bits
when a match occurs, as defined by the CM bits)
00= Legacy operation (conversion data is saved to a location determined by the buffer register bits)
bit 1-0
CM<1:0>: Compare Mode bits
11= Outside Window mode (valid match occurs if the conversion result is outside of the window defined by
the corresponding buffer pair)
10= Inside Window mode (valid match occurs if the conversion result is inside the window defined by the
corresponding buffer pair)
01= Greater Than mode (valid match occurs if the result is greater than the value in the corresponding
buffer register)
00= Less Than mode (valid match occurs if the result is less than the value in the corresponding buffer
register)
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REGISTER 24-6: AD1CHS: A/D SAMPLE SELECT REGISTER
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
CH0NB2
CH0NB1
CH0NB0
CH0SB4
CH0SB3
CH0SB2
CH0SB1
CH0SB0
bit 15
bit 8
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
CH0NA2
CH0NA1
CH0NA0
CH0SA4
CH0SA3
CH0SA2
CH0SA1
CH0SA0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
-n = Value at POR
bit 15-13
bit 12-8
CH0NB<2:0>: Sample B Channel 0 Negative Input Select bits
1xx= Unimplemented
011= Unimplemented
010= AN1
001= Unimplemented
000= VREF-/AVSS
CH0SB<4:0>: Sample B Channel 0 Positive Input Select bits
11111= VBAT/2(1)
(1)
11110= AVDD
11101= AVSS
(1)
11100= Band gap reference (VBG)(1)
11011= VBG/2(1)
11010= VBG/6(1)
11001= CTMU
11000= CTMU temperature sensor input (does not require AD1CTMENH<8> to be set)
10111= AN23(2)
10110= AN22(2)
10101= AN21(2)
10100= AN20(2)
10011= AN19(2)
10010= AN18(2)
10001= AN17(2)
10000= AN16(2)
01111= AN15
01110= AN14
01101= AN13
01100= AN12
01011= AN11
01010= AN10
01001= AN9
01000= AN8
00111= AN7
00110= AN6
00101= AN5
00100= AN4
00011= AN3
00010= AN2
00001= AN1
00000= AN0
Note 1: These input channels do not have corresponding memory mapped result buffers.
2: These channels are implemented in 100-pin devices only.
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REGISTER 24-6: AD1CHS: A/D SAMPLE SELECT REGISTER (CONTINUED)
bit 7-5
CH0NA<2:0>: Sample A Channel 0 Negative Input Select bits
Same definitions as for CHONB<2:0>.
bit 4-0
CH0SA<4:0>: Sample A Channel 0 Positive Input Select bits
Same definitions as for CHOSB<4:0>.
Note 1: These input channels do not have corresponding memory mapped result buffers.
2: These channels are implemented in 100-pin devices only.
REGISTER 24-7: ANCFG: A/D BAND GAP REFERENCE CONFIGURATION
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
bit 15
bit 8
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
R/W-0
R/W-0
R/W-0
VBG6EN
VBG2EN
VBGEN
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-3
bit 2
Unimplemented: Read as ‘0’
VBG6EN: A/D Input VBG/6 Enable bit
1= Band gap voltage, divided by six reference (VBG/6), is enabled
0= Band gap, divided by six reference (VBG/6), is disabled
bit 1
bit 0
VBG2EN: A/D Input VBG/6 Enable bit
1= Band gap voltage, divided by two reference (VBG/6), is enabled
0= Band gap, divided by two reference (VBG/6), is disabled
VBGEN: A/D Input VBG/6 Enable bit
1= Band gap voltage reference (VBG/6) is enabled
0= Band gap reference (VBG/6) is disabled
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REGISTER 24-8: AD1CHITH: A/D SCAN COMPARE HIT REGISTER (HIGH WORD)
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
R/W-0
R/W-0
CHH25
CHH24
bit 15
bit 8
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
CHH23
CHH22
CHH21
CHH20
CHH19
CHH18
CHH17
CHH16
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
-n = Value at POR
bit 15-10
bit 9-0
Unimplemented: Read as ‘0’
CHH<25:16>: A/D Compare Hit bits
If CM<1:0> = 11:
1= A/D Result Buffer n has been written with data or a match has occurred
0= A/D Result Buffer n has not been written with data
For All Other Values of CM<1:0>:
1= A match has occurred on A/D Result Channel n
0= No match has occurred on A/D Result Channel n
REGISTER 24-9: AD1CHITL: A/D SCAN COMPARE HIT REGISTER (LOW WORD)
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
CHH9
R/W-0
CHH8
CHH15
CHH14
CHH13
CHH12
CHH11
CHH10
bit 15
bit 8
R/W-0
CHH7
R/W-0
CHH6
R/W-0
CHH5
R/W-0
CHH4
R/W-0
CHH3
R/W-0
CHH2
R/W-0
CHH1
R/W-0
CHH0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
-n = Value at POR
bit 15-0
CHH<15:0>: A/D Compare Hit bits
If CM<1:0> = 11:
1= A/D Result Buffer n has been written with data or a match has occurred
0= A/D Result Buffer n has not been written with data
For all other values of CM<1:0>:
1= A match has occurred on A/D Result Channel n
0= No match has occurred on A/D Result Channel n
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REGISTER 24-10: AD1CSSH: A/D INPUT SCAN SELECT REGISTER (HIGH WORD)
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
CSS30
CSS29
CSS28
CSS27
CSS26
CSS25
CSS24
bit 15
bit 8
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
CSS23
CSS22
CSS21
CSS20
CSS19
CSS18
CSS17
CSS16
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
-n = Value at POR
bit 15
Unimplemented: Read as ‘0’
CSS<30:16>: A/D Input Scan Selection bits
bit 14-0
1= Include corresponding channel for input scan
0= Skip channel for input scan
REGISTER 24-11: AD1CSSL: A/D INPUT SCAN SELECT REGISTER (LOW WORD)
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
CSS9
R/W-0
CSS8
CSS15
CSS14
CSS13
CSS12
CSS11
CSS10
bit 15
bit 8
R/W-0
CSS7
R/W-0
CSS6
R/W-0
CSS5
R/W-0
CSS4
R/W-0
CSS3
R/W-0
CSS2
R/W-0
CSS1
R/W-0
CSS0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
-n = Value at POR
bit 15-0
CSS<15:0>: A/D Input Scan Selection bits
1= Include corresponding channel for input scan
0= Skip channel for input scan
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REGISTER 24-12: AD1CTMENH: CTMU ENABLE REGISTER (HIGH WORD)(1)
R/W-0
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
CTMEN30
CTMEN29
CTMEN28
CTMEN27
CTMEN26
CTMEN25
CTMEN24
bit 15
bit 8
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
CTMEN23
CTMEN22
CTMEN21
CTMEN20
CTMEN19
CTMEN18
CTMEN17
CTMEN16
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-0
CTMEN<31:16>: CTMU Enabled During Conversion bits
1= CTMU is enabled and connected to the selected channel during conversion
0= CTMU is not connected to this channel
Note 1: The actual number of channels available depends on which channels are implemented on a specific
device; refer to the device data sheet for details. Unimplemented channels are read as ‘0’.
REGISTER 24-13: AD1CTMENL: CTMU ENABLE REGISTER (LOW WORD)(1)
R/W-0
CTMEN15
bit 15
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
CTMEN8
bit 8
CTMEN14
CTMEN13
CTMEN12
CTMUEN11
CTMEN10
CTMEN9
R/W-0
CTMEN7
bit 7
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
CTMEN6
CTMEN5
CTMEN4
CTMEN3
CTMEN2
CTMEN1
CTMEN0
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-0
CTMEN<15:0>: CTMU Enabled During Conversion bits
1= CTMU is enabled and connected to the selected channel during conversion
0= CTMU is not connected to this channel
Note 1: The actual number of channels available depends on which channels are implemented on a specific
device; refer to the device data sheet for details. Unimplemented channels are read as ‘0’.
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FIGURE 24-3:
10-BIT A/D CONVERTER ANALOG INPUT MODEL
RIC 250
Sampling
Switch
RSS 3 k
ANx
RSS
Rs
CHOLD
= 4.4 pF
CPIN
VA
ILEAKAGE
500 nA
VSS
Legend: CPIN
= Input Capacitance
= Threshold Voltage
VT
ILEAKAGE = Leakage Current at the pin due to
various junctions
= Interconnect Resistance
RIC
RSS
= Sampling Switch Resistance
CHOLD
= Sample/Hold Capacitance (from DAC)
Note: The CPIN value depends on the device package and is not tested. The effect of CPIN is negligible if Rs 5 k.
EQUATION 24-1: A/D CONVERSION CLOCK PERIOD
TAD = TCY (ADCS + 1)
TAD
TCY
– 1
ADCS =
Note: Based on TCY = 2/FOSC; Doze mode and PLL are disabled.
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FIGURE 24-4:
12-BIT A/D TRANSFER FUNCTION
Output Code
(Binary (Decimal))
1111 1111 1111(4095)
1111 1111 1110(4094)
0010 0000 0011(2051)
0010 0000 0010(2050)
0010 0000 0001(2049)
0010 0000 0000(2048)
0001 1111 1111(2047)
0001 1111 1110(2046)
0001 1111 1101(2045)
0000 0000 0001(1)
0000 0000 0000(0)
Voltage Level
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FIGURE 24-5:
10-BIT A/D TRANSFER FUNCTION
Output Code
(Binary (Decimal))
11 1111 1111(1023)
11 1111 1110(1022)
10 0000 0011(515)
10 0000 0010(514)
10 0000 0001(513)
10 0000 0000(512)
01 1111 1111(511)
01 1111 1110(510)
01 1111 1101(509)
00 0000 0001(1)
00 0000 0000(0)
Voltage Level
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NOTES:
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voltage reference input from one of the internal band
gap references or the comparator voltage reference
generator (VBG, VBG/2, VBG/6 and CVREF).
25.0 TRIPLE COMPARATOR
MODULE
Note:
This data sheet summarizes the features of
this group of PIC24F devices. It is not
The comparator outputs may be directly connected to
the CxOUT pins. When the respective COE equals ‘1’,
the I/O pad logic makes the unsynchronized output of
the comparator available on the pin.
intended to be a comprehensive reference
source. For more information, refer to the
“PIC24F Family Reference Manual”,
Section 46. “Scalable Comparator
Module” (DS39734). The information in
this data sheet supersedes the information
in the FRM.
A simplified block diagram of the module in shown in
Figure 25-1. Diagrams of the possible individual
comparator configurations are shown in Figure 25-2.
Each comparator has its own control register,
CMxCON (Register 25-1), for enabling and configuring
its operation. The output and event status of all three
comparators is provided in the CMSTAT register
(Register 25-2).
The triple comparator module provides three dual input
comparators. The inputs to the comparator can be
configured to use any one of five external analog inputs
(CxINA, CxINB, CxINC, CxIND and VREF+) and a
FIGURE 25-1:
TRIPLE COMPARATOR MODULE BLOCK DIAGRAM
EVPOL<1:0>
CCH<1:0>
CEVT
Trigger/Interrupt
Logic
Input
Select
Logic
COE
CPOL
VIN-
C1
00
01
VIN+
CXINB
CXINC
CXIND
VBG
C1OUT
Pin
COUT
CEVT
-
10
11
EVPOL<1:0>
CPOL
00
01
10
VBG/2
VBG/6
Trigger/Interrupt
Logic
COE
VIN-
11
VREF+
C2
VIN+
C2OUT
Pin
(1)
COUT
CEVT
CVREFM<1:0>
EVPOL<1:0>
CPOL
0
1
CXINA
+
0
1
Trigger/Interrupt
Logic
VREF+
COE
VIN-
CVREF
C3
VIN+
(1)
CVREFP
C3OUT
Pin
COUT
CREF
Note 1: Refer to the CVRCON register (Register 26-1) for bit details.
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FIGURE 25-2:
INDIVIDUAL COMPARATOR CONFIGURATIONS WHEN CREF = 0
Comparator Off
CEN = 0, CREF = x, CCH<1:0> = xx
COE
VIN-
Cx
VIN+
Off (Read as ‘0’)
CxOUT
Pin
Comparator CxINB > CxINA Compare
Comparator CxINC > CxINA Compare
CEN = 1, CCH<1:0> = 00, CVREFM<1:0> = xx
CEN = 1, CCH<1:0> = 01, CVREFM<1:0> = xx
COE
COE
COE
COE
VIN-
VIN-
CXINB
CXINC
Cx
Cx
VIN+
VIN+
CXINA
CXINA
CxOUT
Pin
CxOUT
Pin
Comparator VBG > CxINA Compare
CEN = 1, CCH<1:0> = 11, CVREFM<1:0> = 00
Comparator CxIND > CxINA Compare
CEN = 1, CCH<1:0> = 10, CVREFM<1:0> = xx
COE
VIN-
VIN-
VBG
CXIND
Cx
Cx
VIN+
VIN+
CXINA
CXINA
CxOUT
Pin
CxOUT
Pin
Comparator VBG > CxINA Compare
CEN = 1, CCH<1:0> = 11, CVREFM<1:0> = 01
Comparator VBG > CxINA Compare
CEN = 1, CCH<1:0> = 11, CVREFM<1:0> = 10
COE
VIN-
VIN-
VBG/2
VBG/6
Cx
Cx
VIN+
VIN+
CXINA
CXINA
CxOUT
Pin
CxOUT
Pin
Comparator CxIND > CxINA Compare
CEN = 1, CCH<1:0> = 11, CVREFM<1:0> = 11
COE
VIN-
VREF+
Cx
VIN+
CXINA
CxOUT
Pin
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FIGURE 25-3:
INDIVIDUAL COMPARATOR CONFIGURATIONS WHEN CREF = 1AND CVREFP = 0
Comparator CxINC > CVREF Compare
Comparator CxINB > CVREF Compare
CEN = 1, CCH<1:0> = 00, CVREFM<1:0> = xx
CEN = 1, CCH<1:0> = 01, CVREFM<1:0> = xx
COE
COE
VIN-
VIN-
CXINC
CXINB
Cx
Cx
VIN+
VIN+
CVREF
CVREF
CxOUT
Pin
CxOUT
Pin
Comparator VBG > CVREF Compare
CEN = 1, CCH<1:0> = 11, CVREFM<1:0> = 00
Comparator CxIND > CVREF Compare
CEN = 1, CCH<1:0> = 10, CVREFM<1:0> = xx
COE
COE
VIN-
VIN-
VBG
CXIND
Cx
Cx
VIN+
VIN+
CVREF
CVREF
CxOUT
Pin
CxOUT
Pin
Comparator VBG > CVREF Compare
CEN = 1, CCH<1:0> = 11, CVREFM<1:0> = 10
Comparator VBG > CVREF Compare
CEN = 1, CCH<1:0> = 11, CVREFM<1:0> = 01
COE
COE
VIN-
VIN-
VBG/6
VBG/2
Cx
Cx
VIN+
VIN+
CVREF
CVREF
CxOUT
Pin
CxOUT
Pin
Comparator CxIND > CVREF Compare
CEN = 1, CCH<1:0> = 11, CVREFM<1:0> = 11
COE
VIN-
VREF+
Cx
VIN+
CVREF
CxOUT
Pin
FIGURE 25-4:
INDIVIDUAL COMPARATOR CONFIGURATIONS WHEN CREF = 1AND CVREFP = 1
Comparator CxINC > CVREF Compare
CEN = 1, CCH<1:0> = 01, CVREFM<1:0> = xx
Comparator CxINB > CVREF Compare
CEN = 1, CCH<1:0> = 00, CVREFM<1:0> = xx
COE
COE
VIN-
VIN-
CXINC
CXINB
Cx
Cx
VIN+
VIN+
VREF+
VREF+
CxOUT
Pin
CxOUT
Pin
Comparator VBG > CVREF Compare
CEN = 1, CCH<1:0> = 11, CVREFM<1:0> = 00
Comparator CxIND > CVREF Compare
CEN = 1, CCH<1:> = 10, CVREFM<1:0> = xx
COE
COE
VIN-
VIN-
VBG
CXIND
Cx
Cx
VIN+
VIN+
VREF+
VREF+
CxOUT
Pin
CxOUT
Pin
Comparator VBG > CVREF Compare
CEN = 1, CCH<1:0> = 11, CVREFM<1:0> = 10
Comparator VBG > CVREF Compare
CEN = 1, CCH<1:0> = 11, CVREFM<1:0> = 01
COE
COE
VIN-
VIN-
VBG/6
VBG/2
Cx
Cx
VIN+
VIN+
VREF+
VREF+
CxOUT
Pin
CxOUT
Pin
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REGISTER 25-1: CMxCON: COMPARATOR x CONTROL REGISTERS
(COMPARATORS 1 THROUGH 3)
R/W-0
CEN
R/W-0
COE
R/W-0
CPOL
U-0
—
U-0
—
U-0
—
R/W-0, HS
CEVT
R-0, HSC
COUT
bit 15
bit 8
R/W-0
R/W-0
U-0
—
R/W-0
CREF
U-0
—
U-0
—
R/W-0
CCH1
R/W-0
CCH0
EVPOL1
EVPOL0
bit 7
bit 0
Legend:
HS = Hardware Settable bit
W = Writable bit
HSC = Hardware Settable/Clearable bit
U = Unimplemented bit, read as ‘0’
R = Readable bit
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15
bit 14
bit 13
CEN: Comparator Enable bit
1= Comparator is enabled
0= Comparator is disabled
COE: Comparator Output Enable bit
1= Comparator output is present on the CxOUT pin
0= Comparator output is internal only
CPOL: Comparator Output Polarity Select bit
1= Comparator output is inverted
0= Comparator output is not inverted
bit 12-10
bit 9
Unimplemented: Read as ‘0’
CEVT: Comparator Event bit
1= Comparator event that is defined by EVPOL<1:0> has occurred; subsequent triggers and interrupts
are disabled until the bit is cleared
0= Comparator event has not occurred
bit 8
COUT: Comparator Output bit
When CPOL = 0:
1= VIN+ > VIN-
0= VIN+ < VIN-
When CPOL = 1:
1= VIN+ < VIN-
0= VIN+ > VIN-
bit 7-6
EVPOL<1:0>: Trigger/Event/Interrupt Polarity Select bits
11= Trigger/event/interrupt is generated on any change of the comparator output (while CEVT = 0)
10= Trigger/event/interrupt is generated on transition of the comparator output:
If CPOL = 0 (non-inverted polarity):
High-to-low transition only.
If CPOL = 1 (inverted polarity):
Low-to-high transition only.
01= Trigger/event/interrupt is generated on transition of comparator output:
If CPOL = 0 (non-inverted polarity):
Low-to-high transition only.
If CPOL = 1 (inverted polarity):
High-to-low transition only.
00= Trigger/event/interrupt generation is disabled
Unimplemented: Read as ‘0’
bit 5
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REGISTER 25-1: CMxCON: COMPARATOR x CONTROL REGISTERS
(COMPARATORS 1 THROUGH 3) (CONTINUED)
bit 4
CREF: Comparator Reference Select bits (non-inverting input)
1= Non-inverting input connects to the internal CVREF voltage
0= Non-inverting input connects to the CXINA pin
bit 3-2
bit 1-0
Unimplemented: Read as ‘0’
CCH<1:0>: Comparator Channel Select bits
11= Inverting input of the comparator connects to the internal selectable reference voltage specified
by the CVREFM<1:0> bits in the CVRCON register
10= Inverting input of the comparator connects to the CXIND pin
01= Inverting input of the comparator connects to the CXINC pin
00= Inverting input of the comparator connects to the CXINB pin
REGISTER 25-2: CMSTAT: COMPARATOR MODULE STATUS REGISTER
R/W-0
U-0
—
U-0
—
U-0
—
U-0
—
R-0, HSC
C3EVT
R-0, HSC
C2EVT
R-0, HSC
C1EVT
CMIDL
bit 15
bit 8
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
R-0, HSC
C3OUT
R-0, HSC
C2OUT
R-0, HSC
C1OUT
bit 7
bit 0
Legend:
HSC = Hardware Settable/Clearable bit
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15
CMIDL: Comparator Stop in Idle Mode bit
1= Discontinue operation of all comparators when device enters Idle mode
0= Continue operation of all enabled comparators in Idle mode
bit 14-11
bit 10
Unimplemented: Read as ‘0’
C3EVT: Comparator 3 Event Status bit (read-only)
Shows the current event status of Comparator 3 (CM3CON<9>).
C2EVT: Comparator 2 Event Status bit (read-only)
Shows the current event status of Comparator 2 (CM2CON<9>).
C1EVT: Comparator 1 Event Status bit (read-only)
Shows the current event status of Comparator 1 (CM1CON<9>).
Unimplemented: Read as ‘0’
bit 9
bit 8
bit 7-3
bit 2
C3OUT: Comparator 3 Output Status bit (read-only)
Shows the current output of Comparator 3 (CM3CON<8>).
C2OUT: Comparator 2 Output Status bit (read-only)
Shows the current output of Comparator 2 (CM2CON<8>).
C1OUT: Comparator 1 Output Status bit (read-only)
Shows the current output of Comparator 1 (CM1CON<8>).
bit 1
bit 0
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NOTES:
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26.1 Configuring the Comparator
Voltage Reference
26.0 COMPARATOR VOLTAGE
REFERENCE
The voltage reference module is controlled through the
Note:
This data sheet summarizes the features of
CVRCON register (Register 26-1). The comparator
voltage reference provides two ranges of output
voltage, each with 16 distinct levels. The range to be
used is selected by the CVRR bit (CVRCON<5>). The
primary difference between the ranges is the size of the
steps selected by the CVREF Selection bits
(CVR<3:0>), with one range offering finer resolution.
this group of PIC24F devices. It is not
intended to be a comprehensive reference
source. For more information, refer to the
“PIC24F Family Reference Manual”,
Section 19. “Dual Comparator Module”
(DS39710). The information in this data
sheet supersedes the information in the
FRM.
The comparator reference supply voltage can come
from either VDD and VSS, or the external VREF+ and
VREF-. The voltage source is selected by the CVRSS
bit (CVRCON<4>).
The settling time of the comparator voltage reference
must be considered when changing the CVREF
output.
FIGURE 26-1:
COMPARATOR VOLTAGE REFERENCE BLOCK DIAGRAM
CVRSS = 1
VREF+
AVDD
8R
CVRSS = 0
CVR<3:0>
R
CVREN
R
R
R
16 Steps
CVREF
CVROE
R
R
R
CVREF
Pin
CVRR
VREF-
8R
CVRSS = 1
CVRSS = 0
AVSS
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REGISTER 26-1: CVRCON: COMPARATOR VOLTAGE REFERENCE CONTROL REGISTER
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
R/W-0
R/W-0
R/W-0
CVREFP
CVREFM1
CVREFM0
bit 15
bit 8
R/W-0
R/W-0
R/W-0
CVRR
R/W-0
R/W-0
CVR3
R/W-0
CVR2
R/W-0
CVR1
R/W-0
CVR0
CVREN
CVROE
CVRSS
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
-n = Value at POR
bit 15-11
bit 10
Unimplemented: Read as ‘0’
CVREFP: Voltage Reference Select bit (valid only when CREF is ‘1’)
1= VREF+ is used as a reference voltage to the comparators
0= The CVR (4-bit DAC) within this module provides the the reference voltage to the comparators
bit 9-8
CVREFM<1:0>: Band Gap Reference Source Select bits (valid only when CCH<1:0> = 11)
00= Band gap voltage is provided as an input to the comparators
01= Band gap voltage, divided by two, is provided as an input to the comparators
10= Band gap voltage, divided by six, is provided as an input to the comparators
11= VREF+ pin is provided as an input to the comparators
bit 7
bit 6
bit 5
bit 4
bit 3-0
CVREN: Comparator Voltage Reference Enable bit
1= CVREF circuit is powered on
0= CVREF circuit is powered down
CVROE: Comparator VREF Output Enable bit
1= CVREF voltage level is output on the CVREF pin
0= CVREF voltage level is disconnected from the CVREF pin
CVRR: Comparator VREF Range Selection bit
1= CVRSRC range should be 0 to 0.625 CVRSRC with CVRSRC/24 step size
0= CVRSRC range should be 0.25 to 0.719 CVRSRC with CVRSRC/32 step size
CVRSS: Comparator VREF Source Selection bit
1= Comparator reference source, CVRSRC = VREF+ – VREF-
0= Comparator reference source, CVRSRC = AVDD – AVSS
CVR<3:0>: Comparator VREF Value Selection 0 CVR<3:0> 15 bits
When CVRR = 1:
CVREF = (CVR<3:0>/24) (CVRSRC)
When CVRR = 0:
CVREF = 1/4 (CVRSRC) + (CVR<3:0>/32) (CVRSRC)
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27.1 Measuring Capacitance
27.0 CHARGE TIME
MEASUREMENT UNIT (CTMU)
The CTMU module measures capacitance by
generating an output pulse with a width equal to the
time between edge events on two separate input
channels. The pulse edge events to both input
channels can be selected from four sources: two
internal peripheral modules (OC1 and Timer1) and up
to 13 external pins (CTEDG1 through CTEDG13). This
pulse is used with the module’s precision current
source to calculate capacitance according to the
relationship:
Note:
This data sheet summarizes the features of
this group of PIC24F devices. It is not
intended to be a comprehensive reference
source. For more information on the
Charge Measurement Unit, refer to the
“PIC24F Family Reference Manual”,
Section 11. “Charge Time Measurement
Unit (CTMU)” (DS39724).
The Charge Time Measurement Unit (CTMU) is a
flexible analog module that provides charge
measurement, accurate differential time measurement
between pulse sources and asynchronous pulse
generation. Its key features include:
EQUATION 27-1:
dV
I = C ------
dT
For capacitance measurements, the A/D Converter
samples an external capacitor (CAPP) on one of its
input channels after the CTMU output’s pulse. A
precision resistor (RPR) provides current source
calibration on a second A/D channel. After the pulse
ends, the converter determines the voltage on the
capacitor. The actual calculation of capacitance is
performed in software by the application.
• Thirteen external edge input trigger sources
• Polarity control for each edge source
• Control of edge sequence
• Control of response to edge levels or edge
transitions
• Time measurement resolution of one nanosecond
• Accurate current source suitable for capacitive
measurement
Figure 27-1 illustrates the external connections used
for capacitance measurements, and how the CTMU
and A/D modules are related in this application. This
example also shows the edge events coming from
Timer1, but other configurations using external edge
sources are possible. A detailed discussion on
measuring capacitance and time with the CTMU
module is provided in the “PIC24F Family Reference
Manual”, Section 11. “Charge Time Measurement
Unit (CTMU)”.
Together with other on-chip analog modules, the CTMU
can be used to precisely measure time, measure
capacitance, measure relative changes in capacitance
or generate output pulses that are independent of the
system clock. The CTMU module is ideal for interfacing
with capacitive-based touch sensors.
The CTMU is controlled through three registers:
CTMUCON1,
CTMUCON2
and
CTMUICON.
CTMUCON1 enables the module and controls the mode
of operation of the CTMU, as well as controlling edge
sequencing. CTMUCON2 controls edge source selec-
tion and edge source polarity selection. The CTMUICON
register selects the current range of current source and
trims the current.
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FIGURE 27-1:
TYPICAL CONNECTIONS AND INTERNAL CONFIGURATION FOR
CAPACITANCE MEASUREMENT
PIC24F Device
Timer1
CTMU
EDG1
EDG2
Current Source
Output Pulse
A/D Converter
ANx
ANY
CAPP
RPR
When the module is configured for pulse generation
delay by setting the TGEN bit (CTMUCON1<12>), the
internal current source is connected to the B input of
Comparator 2. A capacitor (CDELAY) is connected to
the Comparator 2 pin, C2INB, and the comparator
voltage reference, CVREF, is connected to C2INA.
CVREF is then configured for a specific trip point. The
module begins to charge CDELAY when an edge event
is detected. When CDELAY charges above the CVREF
trip point, a pulse is output on CTPLS. The length of the
pulse delay is determined by the value of CDELAY and
the CVREF trip point.
27.2 Measuring Time
Time measurements on the pulse width can be similarly
performed using the A/D module’s internal capacitor
(CAD) and a precision resistor for current calibration.
Figure 27-2 displays the external connections used for
time measurements, and how the CTMU and A/D
modules are related in this application. This example
also shows both edge events coming from the external
CTEDG pins, but other configurations using internal
edge sources are possible.
27.3 Pulse Generation and Delay
Figure 27-3 illustrates the external connections for
pulse generation, as well as the relationship of the
different analog modules required. While CTED1 is
shown as the input pulse source, other options are
available. A detailed discussion on pulse generation
with the CTMU module is provided in the “PIC24F
Family Reference Manual”.
The CTMU module can also generate an output pulse
with edges that are not synchronous with the device’s
system clock. More specifically, it can generate a pulse
with a programmable delay from an edge event input to
the module.
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FIGURE 27-2:
TYPICAL CONNECTIONS AND INTERNAL CONFIGURATION FOR TIME
MEASUREMENT
PIC24F Device
CTMU
CTEDX
CTEDX
EDG1
EDG2
Current Source
Output Pulse
A/D Converter
CAD
ANx
RPR
FIGURE 27-3:
TYPICAL CONNECTIONS AND INTERNAL CONFIGURATION FOR PULSE
DELAY GENERATION
PIC24F Device
CTMU
CTEDX
EDG1
CTPLS
Current Source
Comparator
-
C2INB
C2
CDELAY
CVREF
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REGISTER 27-1: CTMUCON1: CTMU CONTROL REGISTER 1
R/W-0
U-0
—
R/W-0
R/W-0
TGEN
R/W-0
R/W-0
R/W-0
R/W-0
CTMUEN
CTMUSIDL
EDGEN
EDGSEQEN
IDISSEN
CTTRIG
bit 15
bit 8
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15
CTMUEN: CTMU Enable bit
1= Module is enabled
0= Module is disabled
bit 14
bit 13
Unimplemented: Read as ‘0’
CTMUSIDL: Stop in Idle Mode bit
1= Discontinue module operation when device enters Idle mode
0= Continue module operation in Idle mode
bit 12
bit 11
bit 10
bit 9
TGEN: Time Generation Enable bit
1= Enables edge delay generation
0= Disables edge delay generation
EDGEN: Edge Enable bit
1= Edges are not blocked
0= Edges are blocked
EDGSEQEN: Edge Sequence Enable bit
1= Edge 1 event must occur before Edge 2 event can occur
0= No edge sequence is needed
IDISSEN: Analog Current Source Control bit
1= Analog current source output is grounded
0= Analog current source output is not grounded
bit 8
CTTRIG: Trigger Control bit
1= Trigger output is enabled
0= Trigger output is disabled
bit 7-0
Unimplemented: Read as ‘0’
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REGISTER 27-2: CTMUCON2: CTMU CONTROL REGISTER 2
R/W-0
EDG1MOD
bit 15
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
EDG1POL
EDG1SEL3 EDG1SEL2 EDG1SEL1 EDG1SEL0 EDG2STAT EDG1STAT
bit 8
R/W-0
EDG2MOD
bit 7
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
U-0
—
U-0
—
EDG2POL
EDG2SEL3 EDG2SEL2 EDG2SEL1 EDG2SEL0
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15
EDG1MOD: Edge 1 Edge-Sensitive Select bit
1= Input is edge-sensitive
0= Input is level-sensitive
bit 14
EDG1POL: Edge 1 Polarity Select bit
1= Edge 1 is programmed for a positive edge response
0= Edge 1 is programmed for a negative edge response
bit 13-10
EDG1SEL<3:0>: Edge 1 Source Select bits
1111= Edge 1 source is Comparator 3 output
1110= Edge 1 source is Comparator 2 output
1101= Edge 1 source is Comparator 1 output
1100= Edge 1 source is IC3
1011= Edge 1 source is IC2
1010= Edge 1 source is IC1
1001= Edge 1 source is CTED8
1000= Edge 1 source is CTED7(1)
0111= Edge 1 source is CTED6
0110= Edge 1 source is CTED5
0101= Edge 1 source is CTED4
0100= Edge 1 source is CTED3(1)
0011= Edge 1 source is CTED1
0010= Edge 1 source is CTED2
0001= Edge 1 source is OC1
0000= Edge 1 source is Timer1
bit 9
bit 8
EDG2STAT: Edge 2 Status bit
Indicates the status of Edge 2 and can be written to control current source.
1= Edge 2 has occurred
0= Edge 2 has not occurred
EDG1STAT: Edge 1 Status bit
Indicates the status of Edge 1 and can be written to control current source.
1= Edge 1 has occurred
0= Edge 1 has not occurred
bit 7
bit 6
EDG2MOD: Edge 2 Edge-Sensitive Select bit
1= Input is edge-sensitive
0= Input is level-sensitive
EDG2POL: Edge 2 Polarity Select bit
1= Edge 2 is programmed for a positive edge
0= Edge 2 is programmed for a positive edge
Note 1: Edge sources, CTED3, CTED7, CTED10 and CTED11, are available in 100-pin devices only.
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REGISTER 27-2: CTMUCON2: CTMU CONTROL REGISTER 2 (CONTINUED)
bit 5-2
EDG2SEL<3:0>: Edge 2 Source Select bits
1111= Edge 2 source is Comparator 3 output
1110= Edge 2 source is Comparator 2 output
1101= Edge 2 source is Comparator 1 output
1100= Unimplemented Do not use
1011= Edge 2 source is IC3
1010= Edge 2 source is IC2
1001= Edge 2 source is IC1
1000= Edge 2 source is CTED13
0111= Edge 2 source is CTED12
0110= Edge 2 source is CTED11(1)
0101= Edge 2 source is CTED10(1)
0100= Edge 2 source is CTED9
0011= Edge 2 source is CTED1
0010= Edge 2 source is CTED2
0001= Edge 2 source is OC1
0000= Edge 2 source is Timer1
bit 1-0
Unimplemented: Read as ‘0’
Note 1: Edge sources, CTED3, CTED7, CTED10 and CTED11, are available in 100-pin devices only.
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REGISTER 27-3: CTMUICON: CTMU CURRENT CONTROL REGISTER
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
IRNG1
R/W-0
IRNG0
ITRIM5
ITRIM4
ITRIM3
ITRIM2
ITRIM1
ITRIM0
bit 15
bit 8
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
-n = Value at POR
bit 15-10
ITRIM<5:0>: Current Source Trim bits
011111= Maximum positive change from nominal current
011110
.
.
.
000001= Minimum positive change from nominal current
000000= Nominal current output specified by IRNG<1:0>
111111= Minimum negative change from nominal current
.
.
.
100010
100001= Maximum negative change from nominal current
bit 9-8
bit 7-0
IRNG<1:0>: Current Source Range Select bits
11= 100 × Base Current
10= 10 × Base Current
01= Base current level (0.55 A nominal)
00= 1000 x Base Current
Unimplemented: Read as ‘0’
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NOTES:
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An interrupt flag is set if the device experiences an
28.0 HIGH/LOW-VOLTAGE DETECT
(HLVD)
excursion past the trip point in the direction of change.
If the interrupt is enabled, the program execution will
branch to the interrupt vector address and the software
can then respond to the interrupt.
Note:
This data sheet summarizes the features
of this group of PIC24F devices. It is not
intended to be comprehensive
a
The HLVD Control register (see Register 28-1)
completely controls the operation of the HLVD module.
This allows the circuitry to be “turned off” by the user
under software control, which minimizes the current
consumption for the device.
reference source. For more information
on the High/Low-Voltage Detect, refer to
the “PIC24F Family Reference Manual”,
Section 36. “High-Level Integration
with Programmable High/Low-Voltage
Detect (HLVD)” (DS39725).
The High/Low-Voltage Detect (HLVD) module is a
programmable circuit that allows the user to specify
both the device voltage trip point and the direction of
change.
FIGURE 28-1:
HIGH/LOW-VOLTAGE DETECT (HLVD) MODULE BLOCK DIAGRAM
Externally Generated
Trip Point
VDD
VDD
HLVDL<3:0>
LVDIN
HLVDEN
VDIR
Set
HLVDIF
Band Gap
1.2V Typical
HLVDEN
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REGISTER 28-1: HLVDCON: HIGH/LOW-VOLTAGE DETECT CONTROL REGISTER
R/W-0
U-0
—
R/W-0
LSIDL
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
HLVDEN
bit 15
bit 8
R/W-0
VDIR
R/W-0
R/W-0
IRVST
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
BGVST
HLVDL3
HLVDL2
HLVDL1
HLVDL0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
-n = Value at POR
bit 15
HLVDEN: High/Low-Voltage Detect Power Enable bit
1= HLVD is enabled
0= HLVD is disabled
bit 14
bit 13
Unimplemented: Read as ‘0’
LSIDL: HLVD Stop in Idle Mode bit
1= Discontinue module operation when device enters Idle mode
0= Continue module operation in Idle mode
bit 12-8
bit 7
Unimplemented: Read as ‘0’
VDIR: Voltage Change Direction Select bit
1= Event occurs when voltage equals or exceeds trip point (HLVDL<3:0>)
0= Event occurs when voltage equals or falls below trip point (HLVDL<3:0>)
bit 6
bit 5
BGVST: Band Gap Voltage Stable Flag bit
1= Indicates that the band gap voltage is stable
0= Indicates that the band gap voltage is unstable
IRVST: Internal Reference Voltage Stable Flag bit
1= Internal reference voltage is stable; the High-Voltage Detect logic generates the interrupt flag at the
specified voltage range
0= Internal reference voltage is unstable; the High-Voltage Detect logic will not generate the interrupt
flag at the specified voltage range and the HLVD interrupt should not be enabled
bit 4
Unimplemented: Read as ‘0’
bit 3-0
HLVDL<3:0>: High/Low-Voltage Detection Limit bits
1111= External analog input is used (input comes from the LVDIN pin)
1110= Trip point 1(1)
1101= Trip point 2(1)
1100= Trip point 3(1)
.
.
.
0100= Trip point 11(1)
00xx= Unused
Note 1: For the actual trip point, see Section 32.0 “Electrical Characteristics”.
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29.1.1
CONSIDERATIONS FOR
CONFIGURING PIC24FJ128GA310
FAMILY DEVICES
29.0 SPECIAL FEATURES
Note:
This data sheet summarizes the features of
this group of PIC24F devices. It is not
intended to be a comprehensive reference
source. For more information, refer to the
following sections of the “PIC24F Family
Reference Manual”. The information in this
data sheet supersedes the information in
the FRMs.
In PIC24FJ128GA310 family devices, the configuration
bytes are implemented as volatile memory. This means
that configuration data must be programmed each time
the device is powered up. Configuration data is stored
in the three words at the top of the on-chip program
memory space, known as the Flash Configuration
Words. Their specific locations are shown in
Table 29-1. These are packed representations of the
actual device Configuration bits, whose actual
locations are distributed among several locations in
configuration space. The configuration data is automat-
ically loaded from the Flash Configuration Words to the
proper Configuration registers during device Resets.
•
Section 9. “Watchdog Timer (WDT)”
(DS39697)
• Section 32. “High-Level Device
Integration” (DS39719)
• Section 33. “Programming and
Diagnostics” (DS39716)
Note:
Configuration data is reloaded on all types
of device Resets.
PIC24FJ128GA310 family devices include several
features intended to maximize application flexibility and
reliability, and minimize cost through elimination of
external components. These are:
When creating applications for these devices, users
should always specifically allocate the location of the
Flash Configuration Word for configuration data. This is
to make certain that program code is not stored in this
address when the code is compiled.
• Flexible Configuration
• Watchdog Timer (WDT)
• Code Protection
• JTAG Boundary Scan Interface
• In-Circuit Serial Programming™
• In-Circuit Emulation
The upper byte of all Flash Configuration Words in pro-
gram memory should always be ‘0000 0000’. This
makes them appear to be NOP instructions in the
remote event that their locations are ever executed by
accident. Since Configuration bits are not implemented
in the corresponding locations, writing ‘0’s to these
locations has no effect on device operation.
29.1 Configuration Bits
The Configuration bits can be programmed (read as ‘0’),
or left unprogrammed (read as ‘1’), to select various
device configurations. These bits are mapped starting at
program memory location, F80000h. A detailed explana-
tion of the various bit functions is provided in
Register 29-1 through Register 29-6.
Note:
Performing a page erase operation on the
last page of program memory clears the
Flash Configuration Words, enabling code
protection as a result. Therefore, users
should avoid performing page erase
operations on the last page of program
memory.
Note that address, F80000h, is beyond the user program
memory space. In fact, it belongs to the configuration
memory space (800000h-FFFFFFh) which can only be
accessed using table reads and table writes.
TABLE 29-1: FLASH CONFIGURATION WORD LOCATIONS FOR PIC24FJ128GA310 FAMILY
DEVICES
Configuration Word Addresses
Device
1
2
3
4
PIC24FJ64GA3XX
PIC24FJ128GA3XX
ABFEh
ABFCh
157FCh
ABFAh
ABF8h
157FEh
157FAh
157F8h
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REGISTER 29-1: CW1: FLASH CONFIGURATION WORD 1
U-1
—
U-1
—
U-1
—
U-1
—
U-1
—
U-1
—
U-1
—
U-1
—
bit 23
bit 16
r-x
r
R/PO-1
R/PO-1
GCP
R/PO-1
GWRP
R/PO-1
DEBUG
R/PO-1
LPCFG
R/PO-1
ICS1
R/PO-1
ICS0
JTAGEN
bit 15
bit 8
R/PO-1
WINDIS
R/PO-1
R/PO-1
R/PO-1
FWPSA
R/PO-1
R/PO-1
R/PO-1
R/PO-1
FWDTEN1
FWDTEN0
WDTPS3
WDTPS2
WDTPS1
WDTPS0
bit 7
bit 0
Legend:
r = Reserved bit
W = Writable bit
‘1’ = Bit is set
R = Readable bit
-n = Value at POR
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 23-16
bit 15
Unimplemented: Read as ‘1’
Reserved: The value is unknown; program as ‘0’
JTAGEN: JTAG Port Enable bit
bit 14
1= JTAG port is enabled
0= JTAG port is disabled
bit 13
bit 12
GCP: General Segment Program Memory Code Protection bit
1= Code protection is disabled
0= Code protection is enabled for the entire program memory space
GWRP: General Segment Code Flash Write Protection bit
1= Writes to program memory are allowed
0= Writes to program memory are not allowed
DEBUG: Background Debugger Enable bit
bit 11
bit 10
1= Device resets into Operational mode
0= Device resets into Debug mode
LPCFG: Low-Voltage/Retention Regulator Configuration bit
1= Low-voltage/retention regulator is always disabled
0= Low-power, low-voltage/retention regulator is enabled and controlled in firmware by the RETEN bit
bit 9-8
ICS<1:0>: Emulator Pin Placement Select bits
11= Emulator functions are shared with PGEC1/PGED1
10= Emulator functions are shared with PGEC2/PGED2
01= Emulator functions are shared with PGEC3/PGED3
00= Reserved; do not use
bit 7
WINDIS: Windowed Watchdog Timer Disable bit
1= Standard Watchdog Timer is enabled
0= Windowed Watchdog Timer is enabled; (FWDTEN<1:0> must not be ‘00’)
bit 6-5
FWDTEN<1:0>: Watchdog Timer Configuration bits
11= WDT is always enabled; SWDTEN bit has no effect
10= WDT is enabled and controlled in firmware by the SWDTEN bit
01= WDT is enabled only in Run mode and disabled in Sleep modes; SWDTEN bit is disabled
00= WDT is disabled; SWDTEN bit is disabled
bit 4
FWPSA: WDT Prescaler Ratio Select bit
1= Prescaler ratio of 1:128
0= Prescaler ratio of 1:32
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REGISTER 29-1: CW1: FLASH CONFIGURATION WORD 1 (CONTINUED)
bit 3-0 WDTPS<3:0>: Watchdog Timer Postscaler Select bits
1111= 1:32,768
1110= 1:16,384
1101= 1:8,192
1100= 1:4,096
1011= 1:2,048
1010= 1:1,024
1001= 1:512
1000= 1:256
0111= 1:128
0110= 1:64
0101= 1:32
0100= 1:16
0011= 1:8
0010= 1:4
0001= 1:2
0000= 1:1
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REGISTER 29-2: CW2: FLASH CONFIGURATION WORD 2
U-1
—
U-1
—
U-1
—
U-1
—
U-1
—
U-1
—
U-1
—
U-1
—
bit 23
bit 16
R/PO-1
IESO
r-1
r
r-1
r
R/PO-1
R/PO-1
R/PO-1
R/PO-1
R/PO-1
ALTVRF1
ALTVRF0
FNOSC2
FNOSC1
FNOSC0
bit 15
bit 8
R/PO-1
R/PO-1
R/PO-1
R/PO-1
r-1
r
r-1
r
R/PO-1
R/PO-1
FCKSM1
FCKSM0
OSCIOFCN
IOL1WAY
POSCMD1
POSCMD0
bit 7
bit 0
Legend:
r = Reserved bit
W = Writable bit
‘1’ = Bit is set
R = Readable bit
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
-n = Value at POR
bit 23-16
bit 15
Unimplemented: Read as ‘1’
IESO: Internal External Switchover bit
1= IESO mode (Two-Speed Start-up) is enabled
0= IESO mode (Two-Speed Start-up) is disabled
bit 14-13
bit 12-11
Reserved: Always maintain as ‘1’
ALTVRF<1:0>: Alternate VREF/CVREF Pins Selection bits
00= Voltage reference input, A/D = RB0/RB1, Comparator = RB0/RB1
01= Voltage reference input, A/D = RB0/RB1, Comparator = RA9, RA10
10= Voltage reference input, A/D = RA9/RA10, Comparator = RB0, RB1
11= Voltage reference input, A/D = RA9/RA10, Comparator = RA9, RA10
bit 10-8
FNOSC<2:0>: Initial Oscillator Select bits
111= Fast RC Oscillator with Postscaler (FRCDIV)
110= Reserved
101= Low-Power RC Oscillator (LPRC)
100= Secondary Oscillator (SOSC)
011= Primary Oscillator with PLL module (XTPLL, HSPLL, ECPLL)
010= Primary Oscillator (XT, HS, EC)
001= Fast RC Oscillator with Postscaler and PLL module (FRCPLL)
000= Fast RC Oscillator (FRC)
bit 7-6
bit 5
FCKSM<1:0>: Clock Switching and Fail-Safe Clock Monitor Configuration bits
1x= Clock switching and Fail-Safe Clock Monitor are disabled
01= Clock switching is enabled, Fail-Safe Clock Monitor is disabled
00= Clock switching is enabled, Fail-Safe Clock Monitor is enabled
OSCIOFCN: OSCO Pin Configuration bit
If POSCMD<1:0> = 11 or 00:
1= OSCO/CLKO/RC15 functions as CLKO (FOSC/2)
0= OSCO/CLKO/RC15 functions as port I/O (RC15)
If POSCMD<1:0> = 10 or 01:
OSCIOFCN has no effect on OSCO/CLKO/RC15.
bit 4
IOL1WAY: IOLOCK One-Way Set Enable bit
1= The IOLOCK bit (OSCCON<6>) can be set once, provided the unlock sequence has been
completed. Once set, the Peripheral Pin Select registers cannot be written to a second time.
0= The IOLOCK bit can be set and cleared as needed, provided the unlock sequence has been
completed
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REGISTER 29-2: CW2: FLASH CONFIGURATION WORD 2 (CONTINUED)
bit 3-2
bit 1-0
Reserved: Always maintain as ‘1’
POSCMD<1:0>: Primary Oscillator Configuration bits
11= Primary Oscillator mode is disabled
10= HS Oscillator mode is selected
01= XT Oscillator mode is selected
00= EC Oscillator mode is selected
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REGISTER 29-3: CW3: FLASH CONFIGURATION WORD 3
U-1
—
U-1
—
U-1
—
U-1
—
U-1
—
U-1
—
U-1
—
U-1
—
bit 23
bit 16
R/PO-1
R/PO-1
R/PO-1
WPDIS
R/PO-1
BOREN
R/PO-1
R/PO-1
r-1
r
R/PO-1
WPEND
WPCFG
WDTWIN1
WDTWIN0
SOSCSEL
bit 15
bit 8
R/PO-1
R/PO-1
WPFP6(3)
R/PO-1
WPFP5
R/PO-1
WPFP4
R/PO-1
WPFP3
R/PO-1
WPFP2
R/PO-1
WPFP1
R/PO-1
WPFP0
VBTBOR
bit 7
bit 0
Legend:
PO = Program Once bit
W = Writable bit
r = Reserved bit
R = Readable bit
-n = Value at POR
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
‘1’ = Bit is set
bit 23-16
bit 15
Unimplemented: Read as ‘1’
WPEND: Segment Write Protection End Page Select bit
1= Protected code segment upper boundary is at the last page of program memory; the lower
boundary is the code page specified by WPFP<6:0>
0= Protected code segment lower boundary is at the bottom of the program memory (000000h); upper
boundary is the code page specified by WPFP<6:0>
bit 14
bit 13
WPCFG: Configuration Word Code Page Write Protection Select bit
1= Last page (at the top of program memory) and Flash Configuration Words are not write-protected(1)
0= Last page and Flash Configuration Words are write-protected provided WPDIS = ‘0’
WPDIS: Segment Write Protection Disable bit
1= Segmented code protection is disabled
0= Segmented code protection is enabled; protected segment is defined by the WPEND, WPCFG and
WPFPx Configuration bits
BOREN: Brown-out Reset Enable bit
bit 12
1= BOR is enabled (all modes except Deep Sleep)
0= BOR is disabled
bit 11-10
WDTWIN<1:0>: Watchdog Timer Window Width Select bits
11= 25%
10= 37.5%
01= 50%
00= 75%
bit 9
bit 8
Reserved: Always maintain as ‘1’
SOSCSEL: SOSC Selection bit
1= SOSC circuit is selected
0= Digital (SCLKI) mode(2)
bit 7
VBTBOR: VBAT BOR Enable bit
1= VBAT BOR is enabled
0= VBAT BOR is disabled
Note 1: Regardless of WPCFG status, if WPEND = 1or if WPFP corresponds to the Configuration Word page, the
Configuration Word page is protected.
2: Ensure that the SCLKI pin is made a digital input while using this configuration (see Table 11-1).
3: For the 62K devices: PIC24FJ64GA310, PIC24FJ64GA308 and PIC24FJ64GA306, bit 6 should be
maintained as ‘0’.
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REGISTER 29-3: CW3: FLASH CONFIGURATION WORD 3 (CONTINUED)
bit 6-0
WPFP<6:0>: Write-Protected Code Segment Boundary Page bits(3)
Designates the 256 instruction words page boundary of the protected code segment.
If WPEND = 1:
Specifies the lower page boundary of the code-protected segment; the last page being the last
implemented page in the device.
If WPEND = 0:
Specifies the upper page boundary of the code-protected segment; Page 0 being the lower boundary.
Note 1: Regardless of WPCFG status, if WPEND = 1or if WPFP corresponds to the Configuration Word page, the
Configuration Word page is protected.
2: Ensure that the SCLKI pin is made a digital input while using this configuration (see Table 11-1).
3: For the 62K devices: PIC24FJ64GA310, PIC24FJ64GA308 and PIC24FJ64GA306, bit 6 should be
maintained as ‘0’.
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REGISTER 29-4: CW4: FLASH CONFIGURATION WORD 4
U-1
—
U-1
—
U-1
—
U-1
—
U-1
—
U-1
—
U-1
—
U-1
—
bit 23
bit 16
r-1
r
r-1
r
r-1
r
r-1
r
r-1
r
r-1
r
r-1
r
R/PO-1
DSSWEN
bit 15
bit 8
R/PO-1
DSWDTEN
bit 7
R/PO-1
R/PO-1
R/PO-1
R/PO-1
R/PO-1
R/PO-1
R/PO-1
DSBOREN DSWDTOSC DSWDPS4
DSWDPS3
DSWDPS2
DSWDPS1
DSWDPS0
bit 0
Legend:
r = Reserved bit
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 23-16
bit 15-9
bit 8
Unimplemented: Read as ‘1’
Reserved: Read as ‘1’
DSSWEN: Deep Sleep Software Control Select bit
1= Deep Sleep operation is enabled and controlled by the DSEN bit
0= Deep Sleep operation is disabled
bit 7
bit 6
bit 5
DSWDTEN: Deep Sleep Watchdog Timer Enable bit
1= Deep Sleep WDT is enabled
0= Deep Sleep WDT is disabled
DSBOREN: Deep Sleep Brown-out Reset Enable bit
1= BOR is enabled in Deep Sleep mode
0= BOR is disabled in Deep Sleep mode (remains active in other Sleep modes)
DSWDTOSC: Deep Sleep Watchdog Timer Clock Select bit
1= Clock source is LPRC
0= Clock source is SOSC
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REGISTER 29-4: CW4: FLASH CONFIGURATION WORD 4 (CONTINUED)
bit 4-0 DSWDPS<4:0>: Deep Sleep Watchdog Timer Postscaler Select bits
11111= 1:68,719,476,736 (25.7 days)
11110= 1:34,359,738,368(12.8 days)
11101= 1:17,179,869,184 (6.4 days)
11100= 1:8,589,934592 (77.0 hours)
11011= 1:4,294,967,296 (38.5 hours)
11010= 1:2,147,483,648 (19.2 hours)
11001= 1:1,073,741,824 (9.6 hours)
11000= 1:536,870,912 (4.8 hours)
10111= 1:268,435,456 (2.4 hours)
10110= 1:134,217,728 (72.2 minutes)
10101= 1:67,108,864 (36.1 minutes)
10100= 1:33,554,432 (18.0 minutes)
10011= 1:16,777,216 (9.0 minutes)
10010= 1:8,388,608 (4.5 minutes)
10001= 1:4,194,304 (135.3 s)
10000= 1:2,097,152 (67.7 s)
01111= 1:1,048,576 (33.825 s)
01110= 1:524,288 (16.912 s)
01101= 1:262,114 (8.456 s)
01100= 1:131,072 (4.228 s)
01011= 1:65,536 (2.114 s)
01010= 1:32,768 (1.057 s)
01001= 1:16,384 (528.5 ms)
01000= 1:8,192 (264.3 ms)
00111= 1:4,096 (132.1 ms)
00110= 1:2,048 (66.1 ms)
00101= 1:1,024 (33 ms)
00100= 1:512 (16.5 ms)
00011= 1:256 (8.3 ms)
00010= 1:128 (4.1 ms)
00001= 1:64 (2.1 ms)
00000= 1:32 (1 ms)
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REGISTER 29-5: DEVID: DEVICE ID REGISTER
U-1
—
U-1
—
U-1
—
U-1
—
U-1
—
U-1
—
U-1
—
U-1
—
bit 23
bit 16
R
R
R
R
R
R
R
R
FAMID7
FAMID6
FAMID5
FAMID4
FAMID3
FAMID2
FAMID1
FAMID0
bit 15
bit 8
R
R
R
R
R
R
R
R
DEV7
DEV6
DEV5
DEV4
DEV3
DEV2
DEV1
DEV0
bit 7
bit 0
Legend: R = Readable bit
U = Unimplemented bit
bit 23-16
bit 15-8
Unimplemented: Read as ‘1’
FAMID<7:0>: Device Family Identifier bits
0100 0110= PIC24FJ128GA310 family
DEV<7:0>: Individual Device Identifier bits
bit 7-0
1110 0000= PIC24FJ64GA306
1110 0010= PIC24FJ128GA306
1110 0100= PIC24FJ64GA308
1110 0110= PIC24FJ128GA308
1110 1000= PIC24FJ64GA310
1110 1010= PIC24FJ128GA310
REGISTER 29-6: DEVREV: DEVICE REVISION REGISTER
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
bit 23
bit 16
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
bit 15
bit 8
U-0
—
U-0
—
U-0
—
U-0
—
R
R
R
R
REV3
REV2
REV1
REV0
bit 0
bit 7
Legend: R = Readable bit
U = Unimplemented bit
bit 23-4
bit 3-0
Unimplemented: Read as ‘0’
REV<3:0>: Device revision identifier bits
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29.2.1
ON-CHIP REGULATOR AND POR
29.2 On-Chip Voltage Regulator
The voltage regulator takes approximately 10 s for it
to generate output. During this time, designated as
TVREG, code execution is disabled. TVREG is applied
every time the device resumes operation after any
power-down, including Sleep mode. TVREG is deter-
mined by the status of the VREGS bit (RCON<8>) and
the WDTWIN Configuration bits (CW3<11:10>). Refer
to Section 32.0 “Electrical Characteristics” for more
information on TVREG.
All PIC24FJ128GA310 family devices power their core
digital logic at a nominal 1.8V. This may create an issue
for designs that are required to operate at a higher
typical voltage, such as 3.3V. To simplify system
design, all devices in the PIC24FJ128GA310 family
incorporate an on-chip regulator that allows the device
to run its core logic from VDD.
This regulator is always enabled. It provides a constant
voltage (1.8V nominal) to the digital core logic, from a
VDD of about 2.1V all the way up to the device’s VDD-
MAX. It does not have the capability to boost VDD levels.
In order to prevent “brown-out” conditions when the
voltage drops too low for the regulator, the Brown-out
Reset occurs. Then the regulator output follows VDD
with a typical voltage drop of 300 mV.
Note:
For more information, see Section 32.0
“Electrical Characteristics”. The infor-
mation in this data sheet supersedes the
information in the FRM.
29.2.2
VOLTAGE REGULATOR STANDBY
MODE
A low-ESR capacitor (such as ceramic) must be
connected to the VCAP pin (Figure 29-1). This helps to
maintain the stability of the regulator. The recommended
value for the filter capacitor (CEFC) is provided in
The on-chip regulator always consumes a small incre-
mental amount of current over IDD/IPD, including when
the device is in Sleep mode, even though the core
digital logic does not require power. To provide addi-
tional savings in applications where power resources
are critical, the regulator can be made to enter Standby
mode on its own whenever the device goes into Sleep
mode. This feature is controlled by the VREGS bit
(RCON<8>). Clearing the VREGS bit enables the
Standby mode. When waking up from Standby mode,
the regulator needs to wait for TVREG to expire before
wake-up.
Section 32.1 “DC Characteristics”
.
FIGURE 29-1:
CONNECTIONS FOR THE
ON-CHIP REGULATOR
(1)
3.3V
PIC24FJXXXGA3XX
VDD
29.2.3
LOW-VOLTAGE/RETENTION
REGULATOR
VCAP
VSS
CEFC
(10 F typ)
When power-saving modes, such as Sleep and Deep
Sleep are used, PIC24FJ128GA310 family devices
may use a separate low-power, low-voltage/retention
regulator to power critical circuits. This regulator, which
operates at 1.2V nominal, maintains power to data
RAM and the RTCC while all other core digital logic is
powered down. It operates only in Sleep, Deep Sleep
and VBAT modes.
Note 1: This is a typical operating voltage. Refer to
Section 32.0 “Electrical Characteristics”
for the full operating ranges of VDD.
The low-voltage/retention regulator is described in more
detail in Section 10.1.3 “Low-Voltage/Retention
Regulator”
.
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The WDT Flag bit, WDTO (RCON<4>), is not auto-
29.3 Watchdog Timer (WDT)
matically cleared following a WDT time-out. To detect
subsequent WDT events, the flag must be cleared in
software.
For PIC24FJ128GA310 family devices, the WDT is
driven by the LPRC oscillator. When the WDT is
enabled, the clock source is also enabled.
Note:
The CLRWDT and PWRSAV instructions
clear the prescaler and postscaler counts
when executed.
The nominal WDT clock source from LPRC is 31 kHz.
This feeds a prescaler that can be configured for either
5-bit (divide-by-32) or 7-bit (divide-by-128) operation.
The prescaler is set by the FWPSA Configuration bit.
With a 31 kHz input, the prescaler yields a nominal
WDT Time-out period (TWDT) of 1 ms in 5-bit mode or
4 ms in 7-bit mode.
29.3.1
WINDOWED OPERATION
The Watchdog Timer has an optional Fixed Window
mode of operation. In this Windowed mode, CLRWDT
instructions can only reset the WDT during the last 1/4
of the programmed WDT period. A CLRWDTinstruction
executed before that window causes a WDT Reset,
similar to a WDT time-out.
A variable postscaler divides down the WDT prescaler
output and allows for a wide range of time-out periods.
The postscaler is controlled by the WDTPS<3:0> Con-
figuration bits (CW1<3:0>), which allows the selection
of a total of 16 settings, from 1:1 to 1:32,768. Using the
prescaler and postscaler time-out periods, ranging
from 1 ms to 131 seconds, can be achieved.
Windowed WDT mode is enabled by programming the
WINDIS Configuration bit (CW1<7>) to ‘0’.
29.3.2
CONTROL REGISTER
The WDT, prescaler and postscaler are reset:
• On any device Reset
The WDT is enabled or disabled by the FWDTEN<1:0>
Configuration bits. When the Configuration bits,
FWDTEN<1:0> = 11, the WDT is always enabled.
• On the completion of a clock switch, whether
invoked by software (i.e., setting the OSWEN bit
after changing the NOSC bits) or by hardware
(i.e., Fail-Safe Clock Monitor)
The WDT can be optionally controlled in software when
the Configuration bits, FWDTEN<1:0> = 10. When
FWDTEN<1:0> = 00, the Watchdog Timer is always
disabled. The WDT is enabled in software by setting
the SWDTEN control bit (RCON<5>). The SWDTEN
control bit is cleared on any device Reset. The software
WDT option allows the user to enable the WDT for
critical code segments and disable the WDT during
non-critical segments for maximum power savings.
• When a PWRSAVinstruction is executed
(i.e., Sleep or Idle mode is entered)
• When the device exits Sleep or Idle mode to
resume normal operation
• By a CLRWDTinstruction during normal execution
If the WDT is enabled, it will continue to run during
Sleep or Idle modes. When the WDT time-out occurs,
the device will wake the device and code execution will
continue from where the PWRSAV instruction was
executed. The corresponding SLEEP or IDLE
(RCON<3:2>) bits will need to be cleared in software
after the device wakes up.
FIGURE 29-2:
WDT BLOCK DIAGRAM
SWDTEN
FWDTEN<1:0>
LPRC Control
Wake from Sleep
FWPSA
WDTPS<3:0>
Prescaler
(5-bit/7-bit)
WDT
Counter
Postscaler
WDT Overflow
1:1 to 1:32.768
LPRC Input
Reset
31 kHz
1 ms/4 ms
All Device Resets
Transition to
New Clock Source
Exit Sleep or
Idle Mode
CLRWDTInstr.
PWRSAVInstr.
Sleep or Idle Mode
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Code segment protection provides an added level of
protection to a designated area of program memory by
disabling the NVM safety interlock whenever a write or
29.4 Program Verification and
Code Protection
PIC24FJ128GA310 family devices provide two compli-
mentary methods to protect application code from
overwrites and erasures. These also help to protect the
device from inadvertent configuration changes during
run time.
erase address falls within a specified range. It does not
override General Segment protection controlled by the
GCP or GWRP bits. For example, if GCP and GWRP
are enabled, enabling segmented code protection for
the bottom half of program memory does not undo
General Segment protection for the top half.
29.4.1
GENERAL SEGMENT PROTECTION
The size and type of protection for the segmented code
range are configured by the WPFPx, WPEND, WPCFG
and WPDIS bits in Configuration Word 3. Code seg-
ment protection is enabled by programming the WPDIS
bit (= 0). The WPFP bits specify the size of the segment
to be protected, by specifying the 512-word code page
that is the start or end of the protected segment. The
specified region is inclusive, therefore, this page will
also be protected.
For all devices in the PIC24FJ128GA310 family, the
on-chip program memory space is treated as a single
block, known as the General Segment (GS). Code pro-
tection for this block is controlled by one Configuration
bit, GCP. This bit inhibits external reads and writes to
the program memory space. It has no direct effect in
normal execution mode.
Write protection is controlled by the GWRP bit in the
Configuration Word. When GWRP is programmed to
‘0’, internal write and erase operations to program
memory are blocked.
The WPEND bit determines if the protected segment
uses the top or bottom of the program space as a
boundary. Programming WPEND (= 0) sets the bottom
of program memory (000000h) as the lower boundary
of the protected segment. Leaving WPEND unpro-
grammed (= 1) protects the specified page through the
last page of implemented program memory, including
the Configuration Word locations.
29.4.2
CODE SEGMENT PROTECTION
In addition to global General Segment protection, a
separate subrange of the program memory space can
be individually protected against writes and erases.
This area can be used for many purposes where a sep-
arate block of write and erase-protected code is
needed, such as bootloader applications. Unlike
common boot block implementations, the specially
protected segment in the PIC24FJ128GA310 family
devices can be located by the user anywhere in the
program space and configured in a wide range of sizes.
A separate bit, WPCFG, is used to protect the last page
of program space, including the Flash Configuration
Words. Programming WPCFG (= 0) protects the last
page in addition to the pages selected by the WPEND
and WPFP<6:0> bits setting. This is useful in circum-
stances where write protection is needed for both the
code segment in the bottom of the memory and the
Flash Configuration Words.
The various options for segment code protection are
shown in Table 29-2.
TABLE 29-2: CODE SEGMENT PROTECTION CONFIGURATION OPTIONS
Segment Configuration Bits
Write/Erase Protection of Code Segment
WPDIS
WPEND
WPCFG
1
x
x
No additional protection is enabled; all program memory protection is configured
by GCP and GWRP.
0
1
x
Addresses from the first address of the code page are defined by WPFP<7:0>
through the end of implemented program memory (inclusive); write/erase
protected, including Flash Configuration Words.
0
0
0
0
1
0
Address 000000h through the last address of the code page is defined by
WPFP<7:0> (inclusive); write/erase protected.
Address 000000h through the last address of code page is defined by
WPFP<7:0> (inclusive); write/erase protected and the last page, including Flash
Configuration Words, are write/erase protected.
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29.4.3
CONFIGURATION REGISTER
PROTECTION
29.6
In-Circuit Serial Programming
PIC24FJ128GA310 family microcontrollers can be
serially programmed while in the end application circuit.
This is simply done with two lines for clock (PGECx)
and data (PGEDx), and three other lines for power
(VDD), ground (VSS) and MCLR. This allows customers
to manufacture boards with unprogrammed devices
and then program the microcontroller just before
shipping the product. This also allows the most recent
firmware or a custom firmware to be programmed.
The Configuration registers are protected against
inadvertent or unwanted changes or reads in two ways.
The primary protection method is the same as that of
the RP registers – shadow registers contain a compli-
mentary value which is constantly compared with the
actual value.
To safeguard against unpredictable events, Configura-
tion bit changes resulting from individual cell level
disruptions (such as ESD events) will cause a parity
error and trigger a device Reset.
29.7 In-Circuit Debugger
When MPLAB® ICD 3 is selected as a debugger, the
in-circuit debugging functionality is enabled. This func-
tion allows simple debugging functions when used with
MPLAB IDE. Debugging functionality is controlled
through the PGECx (Emulation/Debug Clock) and
PGEDx (Emulation/Debug Data) pins.
The data for the Configuration registers is derived from
the Flash Configuration Words in program memory.
When the GCP bit is set, the source data for device
configuration is also protected as a consequence. Even
if General Segment protection is not enabled, the
device configuration can be protected by using the
appropriate code segment protection setting.
To use the in-circuit debugger function of the device,
the design must implement ICSP connections to
MCLR, VDD, VSS and the PGECx/PGEDx pin pair des-
ignated by the ICS Configuration bits. In addition, when
the feature is enabled, some of the resources are not
available for general use. These resources include the
first 80 bytes of data RAM and two I/O pins.
29.5 JTAG Interface
PIC24FJ128GA310 family devices implement a JTAG
interface, which supports boundary scan device
testing.
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30.1 MPLAB Integrated Development
Environment Software
30.0 DEVELOPMENT SUPPORT
The PIC® microcontrollers and dsPIC® digital signal
controllers are supported with a full range of software
and hardware development tools:
The MPLAB IDE software brings an ease of software
development previously unseen in the 8/16/32-bit
microcontroller market. The MPLAB IDE is a Windows®
operating system-based application that contains:
• Integrated Development Environment
- MPLAB® IDE Software
• A single graphical interface to all debugging tools
- Simulator
• Compilers/Assemblers/Linkers
- MPLAB C Compiler for Various Device
Families
- Programmer (sold separately)
- HI-TECH C® for Various Device Families
- MPASMTM Assembler
- MPLINKTM Object Linker/
MPLIBTM Object Librarian
- In-Circuit Emulator (sold separately)
- In-Circuit Debugger (sold separately)
• A full-featured editor with color-coded context
• A multiple project manager
- MPLAB Assembler/Linker/Librarian for
Various Device Families
• Customizable data windows with direct edit of
contents
• Simulators
• High-level source code debugging
• Mouse over variable inspection
- MPLAB SIM Software Simulator
• Emulators
• Drag and drop variables from source to watch
windows
- MPLAB REAL ICE™ In-Circuit Emulator
• In-Circuit Debuggers
• Extensive on-line help
• Integration of select third party tools, such as
IAR C Compilers
- MPLAB ICD 3
- PICkit™ 3 Debug Express
• Device Programmers
- PICkit™ 2 Programmer
- MPLAB PM3 Device Programmer
The MPLAB IDE allows you to:
• Edit your source files (either C or assembly)
• One-touch compile or assemble, and download to
emulator and simulator tools (automatically
updates all project information)
• Low-Cost Demonstration/Development Boards,
Evaluation Kits, and Starter Kits
• Debug using:
- Source files (C or assembly)
- Mixed C and assembly
- Machine code
MPLAB IDE supports multiple debugging tools in a
single development paradigm, from the cost-effective
simulators, through low-cost in-circuit debuggers, to
full-featured emulators. This eliminates the learning
curve when upgrading to tools with increased flexibility
and power.
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30.2 MPLAB C Compilers for Various
Device Families
30.5 MPLINK Object Linker/
MPLIB Object Librarian
The MPLAB C Compiler code development systems
are complete ANSI C compilers for Microchip’s PIC18,
PIC24 and PIC32 families of microcontrollers and the
dsPIC30 and dsPIC33 families of digital signal control-
lers. These compilers provide powerful integration
capabilities, superior code optimization and ease of
use.
The MPLINK Object Linker combines relocatable
objects created by the MPASM Assembler and the
MPLAB C18 C Compiler. It can link relocatable objects
from precompiled libraries, using directives from a
linker script.
The MPLIB Object Librarian manages the creation and
modification of library files of precompiled code. When
a routine from a library is called from a source file, only
the modules that contain that routine will be linked in
with the application. This allows large libraries to be
used efficiently in many different applications.
For easy source level debugging, the compilers provide
symbol information that is optimized to the MPLAB IDE
debugger.
30.3 HI-TECH C for Various Device
Families
The object linker/library features include:
• Efficient linking of single libraries instead of many
smaller files
The HI-TECH C Compiler code development systems
are complete ANSI C compilers for Microchip’s PIC
family of microcontrollers and the dsPIC family of digital
signal controllers. These compilers provide powerful
integration capabilities, omniscient code generation
and ease of use.
• Enhanced code maintainability by grouping
related modules together
• Flexible creation of libraries with easy module
listing, replacement, deletion and extraction
30.6 MPLAB Assembler, Linker and
Librarian for Various Device
Families
For easy source level debugging, the compilers provide
symbol information that is optimized to the MPLAB IDE
debugger.
The compilers include a macro assembler, linker, pre-
processor, and one-step driver, and can run on multiple
platforms.
MPLAB Assembler produces relocatable machine
code from symbolic assembly language for PIC24,
PIC32 and dsPIC devices. MPLAB C Compiler uses
the assembler to produce its object file. The assembler
generates relocatable object files that can then be
archived or linked with other relocatable object files and
archives to create an executable file. Notable features
of the assembler include:
30.4 MPASM Assembler
The MPASM Assembler is a full-featured, universal
macro assembler for PIC10/12/16/18 MCUs.
The MPASM Assembler generates relocatable object
files for the MPLINK Object Linker, Intel® standard HEX
files, MAP files to detail memory usage and symbol
reference, absolute LST files that contain source lines
and generated machine code and COFF files for
debugging.
• Support for the entire device instruction set
• Support for fixed-point and floating-point data
• Command line interface
• Rich directive set
• Flexible macro language
The MPASM Assembler features include:
• Integration into MPLAB IDE projects
• MPLAB IDE compatibility
• User-defined macros to streamline
assembly code
• Conditional assembly for multi-purpose
source files
• Directives that allow complete control over the
assembly process
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30.7 MPLAB SIM Software Simulator
30.9 MPLAB ICD 3 In-Circuit Debugger
System
The MPLAB SIM Software Simulator allows code
development in a PC-hosted environment by simulat-
ing the PIC MCUs and dsPIC® DSCs on an instruction
level. On any given instruction, the data areas can be
examined or modified and stimuli can be applied from
a comprehensive stimulus controller. Registers can be
logged to files for further run-time analysis. The trace
buffer and logic analyzer display extend the power of
the simulator to record and track program execution,
actions on I/O, most peripherals and internal registers.
MPLAB ICD 3 In-Circuit Debugger System is Micro-
chip's most cost effective high-speed hardware
debugger/programmer for Microchip Flash Digital Sig-
nal Controller (DSC) and microcontroller (MCU)
devices. It debugs and programs PIC® Flash microcon-
trollers and dsPIC® DSCs with the powerful, yet easy-
to-use graphical user interface of MPLAB Integrated
Development Environment (IDE).
The MPLAB ICD 3 In-Circuit Debugger probe is con-
nected to the design engineer's PC using a high-speed
USB 2.0 interface and is connected to the target with a
connector compatible with the MPLAB ICD 2 or MPLAB
REAL ICE systems (RJ-11). MPLAB ICD 3 supports all
MPLAB ICD 2 headers.
The MPLAB SIM Software Simulator fully supports
symbolic debugging using the MPLAB C Compilers,
and the MPASM and MPLAB Assemblers. The soft-
ware simulator offers the flexibility to develop and
debug code outside of the hardware laboratory envi-
ronment, making it an excellent, economical software
development tool.
30.10 PICkit 3 In-Circuit Debugger/
Programmer and
30.8 MPLAB REAL ICE In-Circuit
Emulator System
PICkit 3 Debug Express
The MPLAB PICkit 3 allows debugging and program-
ming of PIC® and dsPIC® Flash microcontrollers at a
most affordable price point using the powerful graphical
user interface of the MPLAB Integrated Development
Environment (IDE). The MPLAB PICkit 3 is connected
to the design engineer's PC using a full speed USB
interface and can be connected to the target via an
Microchip debug (RJ-11) connector (compatible with
MPLAB ICD 3 and MPLAB REAL ICE). The connector
uses two device I/O pins and the reset line to imple-
ment in-circuit debugging and In-Circuit Serial Pro-
gramming™.
MPLAB REAL ICE In-Circuit Emulator System is
Microchip’s next generation high-speed emulator for
Microchip Flash DSC and MCU devices. It debugs and
programs PIC® Flash MCUs and dsPIC® Flash DSCs
with the easy-to-use, powerful graphical user interface of
the MPLAB Integrated Development Environment (IDE),
included with each kit.
The emulator is connected to the design engineer’s PC
using a high-speed USB 2.0 interface and is connected
to the target with either a connector compatible with in-
circuit debugger systems (RJ11) or with the new high-
speed, noise tolerant, Low-Voltage Differential Signal
(LVDS) interconnection (CAT5).
The PICkit 3 Debug Express include the PICkit 3, demo
board and microcontroller, hookup cables and CDROM
with user’s guide, lessons, tutorial, compiler and
MPLAB IDE software.
The emulator is field upgradable through future firmware
downloads in MPLAB IDE. In upcoming releases of
MPLAB IDE, new devices will be supported, and new
features will be added. MPLAB REAL ICE offers
significant advantages over competitive emulators
including low-cost, full-speed emulation, run-time
variable watches, trace analysis, complex breakpoints, a
ruggedized probe interface and long (up to three meters)
interconnection cables.
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30.11 PICkit 2 Development
Programmer/Debugger and
PICkit 2 Debug Express
30.13 Demonstration/Development
Boards, Evaluation Kits, and
Starter Kits
The PICkit™ 2 Development Programmer/Debugger is
a low-cost development tool with an easy to use inter-
face for programming and debugging Microchip’s Flash
families of microcontrollers. The full featured
Windows® programming interface supports baseline
A wide variety of demonstration, development and
evaluation boards for various PIC MCUs and dsPIC
DSCs allows quick application development on fully func-
tional systems. Most boards include prototyping areas for
adding custom circuitry and provide application firmware
and source code for examination and modification.
(PIC10F,
PIC12F5xx,
PIC16F5xx),
midrange
(PIC12F6xx, PIC16F), PIC18F, PIC24, dsPIC30,
dsPIC33, and PIC32 families of 8-bit, 16-bit, and 32-bit
microcontrollers, and many Microchip Serial EEPROM
products. With Microchip’s powerful MPLAB Integrated
The boards support a variety of features, including LEDs,
temperature sensors, switches, speakers, RS-232
interfaces, LCD displays, potentiometers and additional
EEPROM memory.
Development Environment (IDE) the PICkit™
2
enables in-circuit debugging on most PIC® microcon-
trollers. In-Circuit-Debugging runs, halts and single
steps the program while the PIC microcontroller is
embedded in the application. When halted at a break-
point, the file registers can be examined and modified.
The demonstration and development boards can be
used in teaching environments, for prototyping custom
circuits and for learning about various microcontroller
applications.
In addition to the PICDEM™ and dsPICDEM™ demon-
stration/development board series of circuits, Microchip
has a line of evaluation kits and demonstration software
The PICkit 2 Debug Express include the PICkit 2, demo
board and microcontroller, hookup cables and CDROM
with user’s guide, lessons, tutorial, compiler and
MPLAB IDE software.
®
for analog filter design, KEELOQ security ICs, CAN,
IrDA®, PowerSmart battery management, SEEVAL®
evaluation system, Sigma-Delta ADC, flow rate
sensing, plus many more.
30.12 MPLAB PM3 Device Programmer
Also available are starter kits that contain everything
needed to experience the specified device. This usually
includes a single application and debug capability, all
on one board.
The MPLAB PM3 Device Programmer is a universal,
CE compliant device programmer with programmable
voltage verification at VDDMIN and VDDMAX for
maximum reliability. It features a large LCD display
(128 x 64) for menus and error messages and a modu-
lar, detachable socket assembly to support various
package types. The ICSP™ cable assembly is included
as a standard item. In Stand-Alone mode, the MPLAB
PM3 Device Programmer can read, verify and program
PIC devices without a PC connection. It can also set
code protection in this mode. The MPLAB PM3
connects to the host PC via an RS-232 or USB cable.
The MPLAB PM3 has high-speed communications and
optimized algorithms for quick programming of large
memory devices and incorporates an MMC card for file
storage and data applications.
Check the Microchip web page (www.microchip.com)
for the complete list of demonstration, development
and evaluation kits.
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The literal instructions that involve data movement may
use some of the following operands:
31.0 INSTRUCTION SET SUMMARY
Note:
This chapter is a brief summary of the
PIC24F instruction set architecture and is
not intended to be a comprehensive
reference source.
• A literal value to be loaded into a W register or file
register (specified by the value of ‘k’)
• The W register or file register where the literal
value is to be loaded (specified by ‘Wb’ or ‘f’)
The PIC24F instruction set adds many enhancements
to the previous PIC® MCU instruction sets, while main-
taining an easy migration from previous PIC MCU
instruction sets. Most instructions are a single program
memory word. Only three instructions require two
program memory locations.
However, literal instructions that involve arithmetic or
logical operations use some of the following operands:
• The first source operand, which is a register, ‘Wb’,
without any address modifier
• The second source operand, which is a literal
value
Each single-word instruction is a 24-bit word divided
into an 8-bit opcode, which specifies the instruction
type and one or more operands, which further specify
the operation of the instruction. The instruction set is
highly orthogonal and is grouped into four basic
categories:
• The destination of the result (only if not the same
as the first source operand), which is typically a
register, ‘Wd’, with or without an address modifier
The control instructions may use some of the following
operands:
• A program memory address
• Word or byte-oriented operations
• Bit-oriented operations
• Literal operations
• The mode of the table read and table write
instructions
All instructions are a single word, except for certain
double-word instructions, which were made
double-word instructions so that all the required infor-
mation is available in these 48 bits. In the second word,
the 8 MSbs are ‘0’s. If this second word is executed as
an instruction (by itself), it will execute as a NOP.
• Control operations
Table 31-1 shows the general symbols used in
describing the instructions. The PIC24F instruction set
summary in Table 31-2 lists all the instructions, along
with the status flags affected by each instruction.
Most word or byte-oriented W register instructions
(including barrel shift instructions) have three
operands:
Most single-word instructions are executed in a single
instruction cycle, unless a conditional test is true or the
program counter is changed as a result of the instruc-
tion. In these cases, the execution takes two instruction
cycles, with the additional instruction cycle(s) executed
as a NOP. Notable exceptions are the BRA (uncondi-
tional/computed branch), indirect CALL/GOTO, all table
reads and writes, and RETURN/RETFIE instructions,
which are single-word instructions but take two or three
cycles.
• The first source operand, which is typically a
register, ‘Wb’, without any address modifier
• The second source operand, which is typically a
register, ‘Ws’, with or without an address modifier
• The destination of the result, which is typically a
register, ‘Wd’, with or without an address modifier
However, word or byte-oriented file register instructions
have two operands:
Certain instructions that involve skipping over the sub-
sequent instruction require either two or three cycles if
the skip is performed, depending on whether the
instruction being skipped is a single-word or two-word
instruction. Moreover, double-word moves require two
cycles. The double-word instructions execute in two
instruction cycles.
• The file register specified by the value, ‘f’
• The destination, which could either be the file
register, ‘f’, or the W0 register, which is denoted
as ‘WREG’
Most bit-oriented instructions (including simple
rotate/shift instructions) have two operands:
• The W register (with or without an address
modifier) or file register (specified by the value of
‘Ws’ or ‘f’)
• The bit in the W register or file register
(specified by a literal value or indirectly by the
contents of register, ‘Wb’)
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TABLE 31-1: SYMBOLS USED IN OPCODE DESCRIPTIONS
Field
Description
#text
(text)
[text]
{ }
Means literal defined by “text”
Means “content of text”
Means “the location addressed by text”
Optional field or operation
<n:m>
.b
Register bit field
Byte mode selection
.d
Double-Word mode selection
.S
Shadow register select
.w
Word mode selection (default)
bit4
4-bit Bit Selection field (used in word addressed instructions) {0...15}
MCU Status bits: Carry, Digit Carry, Negative, Overflow, Sticky Zero
Absolute address, label or expression (resolved by the linker)
File register address {0000h...1FFFh}
1-bit unsigned literal {0,1}
C, DC, N, OV, Z
Expr
f
lit1
lit4
4-bit unsigned literal {0...15}
lit5
5-bit unsigned literal {0...31}
lit8
8-bit unsigned literal {0...255}
lit10
lit14
lit16
lit23
None
PC
10-bit unsigned literal {0...255} for Byte mode, {0:1023} for Word mode
14-bit unsigned literal {0...16383}
16-bit unsigned literal {0...65535}
23-bit unsigned literal {0...8388607}; LSB must be ‘0’
Field does not require an entry, may be blank
Program Counter
Slit10
Slit16
Slit6
Wb
10-bit signed literal {-512...511}
16-bit signed literal {-32768...32767}
6-bit signed literal {-16...16}
Base W register {W0..W15}
Wd
Destination W register { Wd, [Wd], [Wd++], [Wd--], [++Wd], [--Wd] }
Wdo
Destination W register
{ Wnd, [Wnd], [Wnd++], [Wnd--], [++Wnd], [--Wnd], [Wnd+Wb] }
Wm,Wn
Wn
Dividend, Divisor working register pair (direct addressing)
One of 16 working registers {W0..W15}
Wnd
Wns
One of 16 destination working registers {W0..W15}
One of 16 source working registers {W0..W15}
WREG
Ws
W0 (working register used in file register instructions)
Source W register { Ws, [Ws], [Ws++], [Ws--], [++Ws], [--Ws] }
Source W register { Wns, [Wns], [Wns++], [Wns--], [++Wns], [--Wns], [Wns+Wb] }
Wso
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TABLE 31-2: INSTRUCTION SET OVERVIEW
Assembly
Mnemonic
# of
# of
Status Flags
Affected
Assembly Syntax
Description
Words Cycles
ADD
ADDC
AND
ASR
ADD
ADD
ADD
ADD
ADD
ADDC
ADDC
ADDC
ADDC
ADDC
AND
AND
AND
AND
AND
ASR
ASR
ASR
ASR
ASR
BCLR
BCLR
BRA
BRA
BRA
BRA
BRA
BRA
BRA
BRA
BRA
BRA
BRA
BRA
BRA
BRA
BRA
BRA
BRA
BRA
BSET
BSET
BSW.C
BSW.Z
BTG
BTG
BTSC
f
f = f + WREG
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
C, DC, N, OV, Z
C, DC, N, OV, Z
C, DC, N, OV, Z
C, DC, N, OV, Z
C, DC, N, OV, Z
C, DC, N, OV, Z
C, DC, N, OV, Z
C, DC, N, OV, Z
C, DC, N, OV, Z
C, DC, N, OV, Z
N, Z
f,WREG
WREG = f + WREG
#lit10,Wn
Wb,Ws,Wd
Wb,#lit5,Wd
f
Wd = lit10 + Wd
1
Wd = Wb + Ws
1
Wd = Wb + lit5
1
f = f + WREG + (C)
1
f,WREG
WREG = f + WREG + (C)
Wd = lit10 + Wd + (C)
Wd = Wb + Ws + (C)
Wd = Wb + lit5 + (C)
f = f .AND. WREG
1
#lit10,Wn
Wb,Ws,Wd
Wb,#lit5,Wd
f
1
1
1
1
f,WREG
WREG = f .AND. WREG
Wd = lit10 .AND. Wd
Wd = Wb .AND. Ws
1
N, Z
#lit10,Wn
Wb,Ws,Wd
Wb,#lit5,Wd
f
1
N, Z
1
N, Z
Wd = Wb .AND. lit5
1
N, Z
f = Arithmetic Right Shift f
WREG = Arithmetic Right Shift f
Wd = Arithmetic Right Shift Ws
Wnd = Arithmetic Right Shift Wb by Wns
Wnd = Arithmetic Right Shift Wb by lit5
Bit Clear f
1
C, N, OV, Z
C, N, OV, Z
C, N, OV, Z
N, Z
f,WREG
1
Ws,Wd
1
Wb,Wns,Wnd
Wb,#lit5,Wnd
f,#bit4
Ws,#bit4
C,Expr
1
1
N, Z
BCLR
BRA
1
None
Bit Clear Ws
1
None
Branch if Carry
1 (2)
1 (2)
1 (2)
1 (2)
1 (2)
1 (2)
1 (2)
1 (2)
1 (2)
1 (2)
1 (2)
1 (2)
1 (2)
1 (2)
1 (2)
2
None
GE,Expr
GEU,Expr
GT,Expr
GTU,Expr
LE,Expr
LEU,Expr
LT,Expr
LTU,Expr
N,Expr
Branch if Greater than or Equal
Branch if Unsigned Greater than or Equal
Branch if Greater than
Branch if Unsigned Greater than
Branch if Less than or Equal
Branch if Unsigned Less than or Equal
Branch if Less than
None
None
None
None
None
None
None
Branch if Unsigned Less than
Branch if Negative
None
None
NC,Expr
NN,Expr
NOV,Expr
NZ,Expr
OV,Expr
Expr
Branch if Not Carry
None
Branch if Not Negative
Branch if Not Overflow
Branch if Not Zero
None
None
None
Branch if Overflow
None
Branch Unconditionally
Branch if Zero
None
Z,Expr
1 (2)
2
None
Wn
Computed Branch
None
BSET
BSW
f,#bit4
Ws,#bit4
Ws,Wb
Bit Set f
1
None
Bit Set Ws
1
None
Write C bit to Ws<Wb>
Write Z bit to Ws<Wb>
Bit Toggle f
1
None
Ws,Wb
1
None
BTG
f,#bit4
Ws,#bit4
f,#bit4
1
None
Bit Toggle Ws
1
None
BTSC
Bit Test f, Skip if Clear
1
None
(2 or 3)
BTSC
Ws,#bit4
Bit Test Ws, Skip if Clear
1
1
None
(2 or 3)
2010-2011 Microchip Technology Inc.
DS39996F-page 353
PIC24FJ128GA310 FAMILY
TABLE 31-2: INSTRUCTION SET OVERVIEW (CONTINUED)
Assembly
Mnemonic
# of
# of
Status Flags
Affected
Assembly Syntax
f,#bit4
Description
Bit Test f, Skip if Set
Words Cycles
BTSS
BTSS
BTSS
1
1
1
None
(2 or 3)
Ws,#bit4
Bit Test Ws, Skip if Set
1
None
(2 or 3)
BTST
BTST
f,#bit4
Ws,#bit4
Ws,#bit4
Ws,Wb
Bit Test f
1
1
1
1
1
1
1
1
2
1
1
1
1
1
1
1
1
1
1
1
1
1
2
2
1
1
1
1
Z
BTST.C
BTST.Z
BTST.C
BTST.Z
BTSTS
Bit Test Ws to C
C
Bit Test Ws to Z
Z
Bit Test Ws<Wb> to C
Bit Test Ws<Wb> to Z
Bit Test then Set f
Bit Test Ws to C, then Set
Bit Test Ws to Z, then Set
Call Subroutine
C
Ws,Wb
Z
BTSTS
f,#bit4
Z
BTSTS.C Ws,#bit4
BTSTS.Z Ws,#bit4
C
Z
CALL
CLR
CALL
CALL
CLR
lit23
Wn
None
Call Indirect Subroutine
f = 0x0000
None
f
None
CLR
WREG
Ws
WREG = 0x0000
Ws = 0x0000
None
CLR
None
CLRWDT
COM
CLRWDT
Clear Watchdog Timer
WDTO, Sleep
COM
COM
COM
CP
f
f = f
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
N, Z
f,WREG
Ws,Wd
f
WREG = f
N, Z
Wd = Ws
N, Z
CP
Compare f with WREG
Compare Wb with lit5
Compare Wb with Ws (Wb – Ws)
Compare f with 0x0000
Compare Ws with 0x0000
Compare f with WREG, with Borrow
Compare Wb with lit5, with Borrow
C, DC, N, OV, Z
C, DC, N, OV, Z
C, DC, N, OV, Z
C, DC, N, OV, Z
C, DC, N, OV, Z
C, DC, N, OV, Z
C, DC, N, OV, Z
C, DC, N, OV, Z
CP
Wb,#lit5
Wb,Ws
f
CP
CP0
CPB
CP0
CP0
CPB
CPB
CPB
Ws
f
Wb,#lit5
Wb,Ws
Compare Wb with Ws, with Borrow
(Wb – Ws – C)
CPSEQ
CPSGT
CPSLT
CPSNE
CPSEQ
CPSGT
CPSLT
CPSNE
Wb,Wn
Wb,Wn
Wb,Wn
Wb,Wn
Compare Wb with Wn, Skip if =
Compare Wb with Wn, Skip if >
Compare Wb with Wn, Skip if <
Compare Wb with Wn, Skip if
1
1
1
1
1
None
None
None
None
(2 or 3)
1
(2 or 3)
1
(2 or 3)
1
(2 or 3)
DAW
DEC
DAW.B
DEC
Wn
Wn = Decimal Adjust Wn
f = f –1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
C
f
C, DC, N, OV, Z
C, DC, N, OV, Z
C, DC, N, OV, Z
C, DC, N, OV, Z
C, DC, N, OV, Z
C, DC, N, OV, Z
None
DEC
f,WREG
Ws,Wd
f
WREG = f –1
1
DEC
Wd = Ws – 1
1
DEC2
DEC2
f = f – 2
1
DEC2
f,WREG
Ws,Wd
#lit14
Wm,Wn
Wm,Wn
Wm,Wn
Wm,Wn
Wns,Wnd
Ws,Wnd
Ws,Wnd
WREG = f – 2
1
DEC2
Wd = Ws – 2
1
DISI
DIV
DISI
Disable Interrupts for k Instruction Cycles
Signed 16/16-bit Integer Divide
Signed 32/16-bit Integer Divide
Unsigned 16/16-bit Integer Divide
Unsigned 32/16-bit Integer Divide
Swap Wns with Wnd
1
DIV.SW
DIV.SD
DIV.UW
DIV.UD
EXCH
18
18
18
18
1
N, Z, C, OV
N, Z, C, OV
N, Z, C, OV
N, Z, C, OV
None
EXCH
FF1L
FF1R
FF1L
Find First One from Left (MSb) Side
Find First One from Right (LSb) Side
1
C
FF1R
1
C
DS39996F-page 354
2010-2011 Microchip Technology Inc.
PIC24FJ128GA310 FAMILY
TABLE 31-2: INSTRUCTION SET OVERVIEW (CONTINUED)
Assembly
Mnemonic
# of
# of
Status Flags
Affected
Assembly Syntax
Description
Words Cycles
GOTO
GOTO
GOTO
INC
Expr
Go to Address
Go to Indirect
f = f + 1
2
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
2
2
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
2
2
1
1
1
1
1
1
1
None
Wn
None
INC
f
C, DC, N, OV, Z
C, DC, N, OV, Z
C, DC, N, OV, Z
C, DC, N, OV, Z
C, DC, N, OV, Z
C, DC, N, OV, Z
N, Z
INC
f,WREG
WREG = f + 1
Wd = Ws + 1
f = f + 2
INC
Ws,Wd
INC2
IOR
INC2
INC2
INC2
IOR
f
f,WREG
WREG = f + 2
Wd = Ws + 2
f = f .IOR. WREG
Ws,Wd
f
IOR
f,WREG
WREG = f .IOR. WREG
N, Z
IOR
#lit10,Wn
Wb,Ws,Wd
Wb,#lit5,Wd
#lit14
Wd = lit10 .IOR. Wd
N, Z
IOR
Wd = Wb .IOR. Ws
N, Z
IOR
Wd = Wb .IOR. lit5
N, Z
LNK
LSR
LNK
Link Frame Pointer
None
LSR
f
f = Logical Right Shift f
C, N, OV, Z
C, N, OV, Z
C, N, OV, Z
N, Z
LSR
f,WREG
WREG = Logical Right Shift f
Wd = Logical Right Shift Ws
Wnd = Logical Right Shift Wb by Wns
Wnd = Logical Right Shift Wb by lit5
Move f to Wn
LSR
Ws,Wd
LSR
Wb,Wns,Wnd
Wb,#lit5,Wnd
f,Wn
LSR
N, Z
MOV
MOV
None
MOV
[Wns+Slit10],Wnd
f
Move [Wns+Slit10] to Wnd
Move f to f
None
MOV
N, Z
MOV
f,WREG
Move f to WREG
N, Z
MOV
#lit16,Wn
#lit8,Wn
Wn,f
Move 16-bit Literal to Wn
None
MOV.b
MOV
Move 8-bit Literal to Wn
None
Move Wn to f
None
MOV
Wns,[Wns+Slit10]
Wso,Wdo
WREG,f
Move Wns to [Wns+Slit10]
Move Ws to Wd
MOV
None
N, Z
MOV
Move WREG to f
MOV.D
MOV.D
MUL.SS
MUL.SU
MUL.US
MUL.UU
MUL.SU
MUL.UU
MUL
Wns,Wd
Move Double from W(ns):W(ns+1) to Wd
Move Double from Ws to W(nd+1):W(nd)
{Wnd+1, Wnd} = Signed(Wb) * Signed(Ws)
{Wnd+1, Wnd} = Signed(Wb) * Unsigned(Ws)
{Wnd+1, Wnd} = Unsigned(Wb) * Signed(Ws)
{Wnd+1, Wnd} = Unsigned(Wb) * Unsigned(Ws)
{Wnd+1, Wnd} = Signed(Wb) * Unsigned(lit5)
{Wnd+1, Wnd} = Unsigned(Wb) * Unsigned(lit5)
W3:W2 = f * WREG
None
None
None
None
None
None
None
None
None
Ws,Wnd
MUL
Wb,Ws,Wnd
Wb,Ws,Wnd
Wb,Ws,Wnd
Wb,Ws,Wnd
Wb,#lit5,Wnd
Wb,#lit5,Wnd
f
NEG
NEG
f
f = f + 1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
2
1
C, DC, N, OV, Z
C, DC, N, OV, Z
C, DC, N, OV, Z
None
NEG
f,WREG
Ws,Wd
WREG = f + 1
NEG
Wd = Ws + 1
NOP
POP
NOP
No Operation
NOPR
POP
No Operation
None
f
Pop f from Top-of-Stack (TOS)
Pop from Top-of-Stack (TOS) to Wdo
Pop from Top-of-Stack (TOS) to W(nd):W(nd+1)
Pop Shadow Registers
None
POP
Wdo
Wnd
None
POP.D
POP.S
None
All
PUSH
PUSH
f
Push f to Top-of-Stack (TOS)
1
1
1
1
1
1
2
1
None
None
None
None
PUSH
Wso
Wns
Push Wso to Top-of-Stack (TOS)
Push W(ns):W(ns+1) to Top-of-Stack (TOS)
Push Shadow Registers
PUSH.D
PUSH.S
2010-2011 Microchip Technology Inc.
DS39996F-page 355
PIC24FJ128GA310 FAMILY
TABLE 31-2: INSTRUCTION SET OVERVIEW (CONTINUED)
Assembly
Mnemonic
# of
# of
Status Flags
Affected
Assembly Syntax
Description
Words Cycles
PWRSAV
RCALL
PWRSAV
RCALL
RCALL
REPEAT
REPEAT
RESET
RETFIE
RETLW
RETURN
RLC
#lit1
Expr
Wn
Go into Sleep or Idle mode
Relative Call
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
2
WDTO, Sleep
None
Computed Call
2
None
REPEAT
#lit14
Wn
Repeat Next Instruction lit14 + 1 times
Repeat Next Instruction (Wn) + 1 times
Software Device Reset
Return from Interrupt
1
None
1
None
RESET
RETFIE
RETLW
RETURN
RLC
1
None
3 (2)
3 (2)
3 (2)
1
None
#lit10,Wn
Return with Literal in Wn
Return from Subroutine
f = Rotate Left through Carry f
WREG = Rotate Left through Carry f
Wd = Rotate Left through Carry Ws
f = Rotate Left (No Carry) f
WREG = Rotate Left (No Carry) f
Wd = Rotate Left (No Carry) Ws
f = Rotate Right through Carry f
WREG = Rotate Right through Carry f
Wd = Rotate Right through Carry Ws
f = Rotate Right (No Carry) f
WREG = Rotate Right (No Carry) f
Wd = Rotate Right (No Carry) Ws
Wnd = Sign-Extended Ws
f = FFFFh
None
None
f
C, N, Z
RLC
f,WREG
Ws,Wd
f
1
C, N, Z
RLC
1
C, N, Z
RLNC
RRC
RLNC
RLNC
RLNC
RRC
1
N, Z
f,WREG
Ws,Wd
f
1
N, Z
1
N, Z
1
C, N, Z
RRC
f,WREG
Ws,Wd
f
1
C, N, Z
RRC
1
C, N, Z
RRNC
RRNC
RRNC
RRNC
SE
1
N, Z
f,WREG
Ws,Wd
Ws,Wnd
f
1
N, Z
1
N, Z
SE
1
C, N, Z
SETM
SETM
SETM
SETM
SL
1
None
WREG
WREG = FFFFh
1
None
Ws
Ws = FFFFh
1
None
SL
f
f = Left Shift f
1
C, N, OV, Z
C, N, OV, Z
C, N, OV, Z
N, Z
SL
f,WREG
Ws,Wd
Wb,Wns,Wnd
Wb,#lit5,Wnd
f
WREG = Left Shift f
1
SL
Wd = Left Shift Ws
1
SL
Wnd = Left Shift Wb by Wns
Wnd = Left Shift Wb by lit5
f = f – WREG
1
SL
1
N, Z
SUB
SUB
1
C, DC, N, OV, Z
C, DC, N, OV, Z
C, DC, N, OV, Z
C, DC, N, OV, Z
C, DC, N, OV, Z
C, DC, N, OV, Z
C, DC, N, OV, Z
SUB
f,WREG
#lit10,Wn
Wb,Ws,Wd
Wb,#lit5,Wd
f
WREG = f – WREG
1
SUB
Wn = Wn – lit10
1
SUB
Wd = Wb – Ws
1
SUB
Wd = Wb – lit5
1
SUBB
SUBB
SUBB
f = f – WREG – (C)
1
f,WREG
WREG = f – WREG – (C)
1
SUBB
SUBB
SUBB
SUBR
SUBR
SUBR
SUBR
#lit10,Wn
Wb,Ws,Wd
Wb,#lit5,Wd
f
Wn = Wn – lit10 – (C)
Wd = Wb – Ws – (C)
Wd = Wb – lit5 – (C)
f = WREG – f
1
1
1
1
1
1
1
1
1
1
1
1
1
1
C, DC, N, OV, Z
C, DC, N, OV, Z
C, DC, N, OV, Z
C, DC, N, OV, Z
C, DC, N, OV, Z
C, DC, N, OV, Z
C, DC, N, OV, Z
SUBR
f,WREG
WREG = WREG – f
Wd = Ws – Wb
Wb,Ws,Wd
Wb,#lit5,Wd
Wd = lit5 – Wb
SUBBR
SUBBR
SUBBR
f
f = WREG – f – (C)
1
1
1
1
C, DC, N, OV, Z
C, DC, N, OV, Z
f,WREG
WREG = WREG – f – (C)
SUBBR
SUBBR
SWAP.b
SWAP
Wb,Ws,Wd
Wb,#lit5,Wd
Wn
Wd = Ws – Wb – (C)
1
1
1
1
1
1
1
1
1
2
C, DC, N, OV, Z
C, DC, N, OV, Z
None
Wd = lit5 – Wb – (C)
SWAP
Wn = Nibble Swap Wn
Wn = Byte Swap Wn
Wn
None
TBLRDH
TBLRDH
Ws,Wd
Read Prog<23:16> to Wd<7:0>
None
DS39996F-page 356
2010-2011 Microchip Technology Inc.
PIC24FJ128GA310 FAMILY
TABLE 31-2: INSTRUCTION SET OVERVIEW (CONTINUED)
Assembly
Mnemonic
# of
# of
Status Flags
Affected
Assembly Syntax
Description
Words Cycles
TBLRDL
TBLWTH
TBLWTL
ULNK
TBLRDL
TBLWTH
TBLWTL
ULNK
XOR
Ws,Wd
Ws,Wd
Ws,Wd
Read Prog<15:0> to Wd
1
1
1
1
1
1
1
1
1
1
2
2
2
1
1
1
1
1
1
1
None
Write Ws<7:0> to Prog<23:16>
Write Ws to Prog<15:0>
Unlink Frame Pointer
f = f .XOR. WREG
None
None
None
N, Z
XOR
f
XOR
f,WREG
WREG = f .XOR. WREG
Wd = lit10 .XOR. Wd
Wd = Wb .XOR. Ws
N, Z
XOR
#lit10,Wn
Wb,Ws,Wd
Wb,#lit5,Wd
Ws,Wnd
N, Z
XOR
N, Z
XOR
Wd = Wb .XOR. lit5
N, Z
ZE
ZE
Wnd = Zero-Extend Ws
C, Z, N
2010-2011 Microchip Technology Inc.
DS39996F-page 357
PIC24FJ128GA310 FAMILY
NOTES:
DS39996F-page 358
2010-2011 Microchip Technology Inc.
PIC24FJ128GA310 FAMILY
32.0 ELECTRICAL CHARACTERISTICS
This section provides an overview of the PIC24FJ128GA310 family electrical characteristics. Additional information will
be provided in future revisions of this document as it becomes available.
Absolute maximum ratings for the PIC24FJ128GA310 family are listed below. Exposure to these maximum rating
conditions for extended periods may affect device reliability. Functional operation of the device at these, or any other
conditions above the parameters indicated in the operation listings of this specification, is not implied.
(†)
Absolute Maximum Ratings
Ambient temperature under bias.............................................................................................................-40°C to +100°C
Storage temperature .............................................................................................................................. -65°C to +150°C
Voltage on VDD with respect to VSS ......................................................................................................... -0.3V to +4.0V
Voltage on any combined analog and digital pin and MCLR, with respect to VSS ......................... -0.3V to (VDD + 0.3V)
Voltage on any digital only pin with respect to VSS when VDD < 3.0V............................................ -0.3V to (VDD + 0.3V)
Voltage on any digital only pin with respect to VSS when VDD > 3.0V..................................................... -0.3V to (+5.5V)
Maximum current out of VSS pin ...........................................................................................................................300 mA
Maximum current into VDD pin (Note 1)................................................................................................................250 mA
Maximum output current sunk by any I/O pin..........................................................................................................25 mA
Maximum output current sourced by any I/O pin ....................................................................................................25 mA
Maximum current sunk by all ports .......................................................................................................................200 mA
Maximum current sourced by all ports (Note 1)....................................................................................................200 mA
Note 1: Maximum allowable current is a function of device maximum power dissipation (see Table 32-1).
†NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at those or any other conditions above those
indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for
extended periods may affect device reliability.
2010-2011 Microchip Technology Inc.
DS39996F-page 359
PIC24FJ128GA310 FAMILY
32.1 DC Characteristics
FIGURE 32-1:
PIC24FJ128GA310 FAMILY VOLTAGE-FREQUENCY GRAPH (INDUSTRIAL)
3.6V
3.6V
PIC24FJXXXDA1
2.2V
2.0V
2.2V
2.0V
32 MHz
Frequency
VCAP (nominal On-Chip Regulator output voltage) = 1.8V.
Note:
TABLE 32-1: THERMAL OPERATING CONDITIONS
Rating
Symbol
Min
Typ
Max
Unit
PIC24FJ128GA310 family:
Operating Junction Temperature Range
Operating Ambient Temperature Range
TJ
TA
-40
-40
—
—
+125
+85
°C
°C
Power Dissipation:
Internal Chip Power Dissipation: PINT = VDD x (IDD – IOH)
PD
PINT + PI/O
W
W
I/O Pin Power Dissipation:
PI/O = ({VDD – VOH} x IOH) + (VOL x IOL)
Maximum Allowed Power Dissipation
PDMAX
(TJMAX – TA)/JA
TABLE 32-2: THERMAL PACKAGING CHARACTERISTICS
Characteristic
Symbol
Typ
Max
Unit
Note
Package Thermal Resistance, 14x14x1 mm 100-pin TQFP
Package Thermal Resistance, 12x12x1 mm 100-pin TQFP
Package Thermal Resistance, 12x12x1 mm 80-pin TQFP
Package Thermal Resistance, 10x10x1 mm 64-pin TQFP
Package Thermal Resistance, 9x9x0.9 mm 64-pin QFN
Package Thermal Resistance, 10x10x1.1 mm 121-pin BGA
JA
JA
JA
JA
JA
JA
43.0
45.0
48.0
48.3
28.0
40.2
—
—
—
—
—
—
°C/W (Note 1)
°C/W (Note 1)
°C/W (Note 1)
°C/W (Note 1)
°C/W (Note 1)
°C/W (Note 1)
Note 1: Junction to ambient thermal resistance, Theta-JA (JA) numbers are achieved by package simulations.
DS39996F-page 360
2010-2011 Microchip Technology Inc.
PIC24FJ128GA310 FAMILY
TABLE 32-3: DC CHARACTERISTICS: TEMPERATURE AND VOLTAGE SPECIFICATIONS
Standard Operating Conditions: 2V to 3.6V (unless otherwise stated)
DC CHARACTERISTICS
Operating temperature
-40°C TA +85°C for Industrial
Param
No.
Symbol
Characteristic
Min
Typ
Max
Units
Conditions
Operating Voltage
DC10 VDD
Supply Voltage
2
—
—
3.6
—
V
V
With BOR disabled
DC12 VDR
RAM Data Retention
Voltage(1)
1.9
DC16 VPOR
DC17 SVDD
VBOR
VDD Start Voltage
to Ensure Internal
Power-on Reset Signal
VSS
0.05
2
—
—
—
—
—
V
VDD Rise Rate
to Ensure Internal
Power-on Reset Signal
V/ms 0-3.3V in 66 ms
0-2.5V in 50 ms
Brown-out Reset Voltage
on VDD Transition,
High-to-Low
2.2
V
Note 1: This is the limit to which the RAM data can be retained while the on-chip regulator output voltage starts
following the VDD.
TABLE 32-4: DC CHARACTERISTICS: OPERATING CURRENT (IDD)
Standard Operating Conditions: 2V to 3.6V (unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
DC CHARACTERISTICS
Parameter
No.
Operating
Temperature
Typical(1)
Max
Units
VDD
Conditions
Operating Current (IDD)
DC19
DC20A
DC20
0.15
0.15
0.31
0.32
1.2
—
—
mA
mA
mA
mA
mA
mA
mA
mA
A
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
2.0V
3.3V
2.0V
3.3V
2.0V
3.3V
2.0V
3.3V
2.0V
3.3V
0.5 MIPS,
FOSC = 1 MHz
—
1 MIPS,
FOSC = 2 MHz
—
DC23
DC24
DC31
—
4 MIPS,
FOSC = 8 MHz
1.25
4.8
—
6.8
6.9
78
80
16 MIPS,
FOSC = 32 MHz
4.9
26
LPRC (15.5 KIPS)
FOSC = 31 kHz
26
A
Note 1: Data in the “Typical” column is at 3.3V, 25°C unless otherwise stated. Typical parameters are for design
guidance only and are not tested.
2010-2011 Microchip Technology Inc.
DS39996F-page 361
PIC24FJ128GA310 FAMILY
TABLE 32-5: DC CHARACTERISTICS: IDLE CURRENT (IIDLE)
Standard Operating Conditions: 2V to 3.6V (unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
DC CHARACTERISTICS
Parameter
Typical(1)
No.
Operating
Temperature
Max
Units
VDD
Conditions
Idle Current (IIDLE)
DC40
DC43
DC47
DC50
DC51
81
86
—
—
A
A
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
2.0V
3.3V
2.0V
3.3V
2.0V
3.3V
2.0V
3.3V
2.0V
3.3V
1 MIPS,
FOSC = 2 MHz
0.27
0.28
1
—
mA
mA
mA
mA
mA
mA
A
4 MIPS,
FOSC = 8 MHz
—
1.35
1.4
—
16 MIPS,
FOSC = 32 MHz
1.07
0.47
0.48
21
4 MIPS (FRC),
FOSC = 8 MHz
—
76
78
LPRC (15.5 KIPS),
FOSC = 31 kHz
21
A
Note 1: Data in the “Typical” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance
only and are not tested.
DS39996F-page 362
2010-2011 Microchip Technology Inc.
PIC24FJ128GA310 FAMILY
TABLE 32-6: DC CHARACTERISTICS: POWER-DOWN CURRENT (IPD)
Standard Operating Conditions: 2V to 3.6V (unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
DC CHARACTERISTICS
Parameter
Typical(1)
No.
Operating
Temperature
Max
Units
VDD
Conditions
Power-Down Current (IPD)
DC60
DC61
DC70
—
3.7
6.2
13.6
—
—
—
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
-40°C
+25°C
+60°C
+85°C
-40°
2.0V
3.3V
2.0V
3.3V
—
27.5
—
3.8
6.3
13.7
—
—
+25°C
+60°C
+85°C
-40°
Sleep(2)
—
28
—
0.33
2
—
+25°C
+60°C
+85°C
-40°
—
7.7
—
14.5
—
Low-Voltage Sleep(3)
0.34
2
—
+25°C
+60°C
+85°C
-40°
—
7.9
—
15
—
0.01
—
—
+25°C
+60°C
+85°C
-40°
2.0V
3.3V
—
—
1.1
—
Deep Sleep
—
0.04
—
—
+25°C
+60°C
+85°C
-40°C to +85°C
—
—
1.4
2.0
0.4
0V
RTCC with VBAT mode (LPRC/SOSC)(4)
Note 1: Data in the Typical column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance
only and are not tested.
2: The retention low-voltage regulator is disabled; RETEN (RCON<12>) = 0, LPCFG (CW1<10>) = 1.
3: The retention low-voltage regulator is enabled; RETEN (RCON<12>) = 1, LPCFG (CW1<10>) = 0.
4: The VBAT pin is connected to the battery and RTCC is running with VDD = 0.
2010-2011 Microchip Technology Inc.
DS39996F-page 363
PIC24FJ128GA310 FAMILY
TABLE 32-7: DC CHARACTERISTICS: CURRENT (BOR, WDT, DSBOR, DSWDT, LCD)
Standard Operating Conditions: 2V to 3.6V (unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
DC CHARACTERISTICS
Parameter
No.
Operating
Temperature
Typical(1)
Max
Units
VDD
Conditions
Incremental Current Brown-out Reset (BOR)(2)
DC20
3.1
5
A
A
-40°C to +85°C
-40°C to +85°C
2.0V
3.3V
BOR(2)
WDT(2)
4.3
6
Incremental Current Brown-out Reset (WDT)(2)
DC71
0.8
1.5
A
A
-40°C to +85°C
-40°C to +85°C
2.0V
3.3V
0.8
1.5
Incremental Current HLVD (HLVD)(2)
DC75
5.7
15
A
A
-40°C to +85°C
-40°C to +85°C
2.0V
3.3V
HLVD(2)
RTCC(2)
5.7
15
Incremental Current Real-Time Clock and Calendar (RTCC)(2)
DC77
0.4
0.4
1
1
A
A
-40°C to +85°C
-40°C to +85°C
2.0V
3.3V
RTCC with SOSC
Incremental Current Real-Time Clock and Calendar (RTCC)(2)
RTCC(2)
RTCC with LPRC
DC77a
0.4
0.4
1
1
A
A
-40°C to +85°C
-40°C to +85°C
2.0V
3.3V
Incremental Current Deep Sleep BOR ( DSBOR)(2)
DC81
0.07
0.3
A
-40°C to +85°C
2.0V
3.3V
Deep Sleep BOR(2)
Deep Sleep WDT(2)
0.07
0.3
A
-40°C to +85°C
Incremental Current Deep Sleep Watchdog Timer Reset ( DSWDT)(2)
DC80
0.27
0.4
A
A
-40°C to +85°C
-40°C to +85°C
2.0V
3.3V
0.27
0.4
Incremental Current LCD ( LCD)(2)
0.8
3
A
-40°C to +85°C
LCD External/Internal(2,3)
1/8 MUX 1/3 Bias
3.3V
LCD Charge Pump(2,4)
1/8 MUX 1/3 Bias
DC90
20
24
30
40
A
A
-40°C to +85°C
-40°C to +85°C
2.0V
3.3V
VBAT A/D Monitor(5)
DC91 1.5
—
—
A
A
-40°C to +85°C
-40°C to +85°C
3.3V
3.3V
VBAT = 2V
4
VBAT = 3.3V
Note 1: Data in the Typical column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance
only and are not tested.
2: Incremental current while the module is enabled and running.
3: LCD is enabled and running; no glass is connected; the resistor ladder current is not included.
4: LCD is enabled and running; no glass is connected.
5: The A/D channel is connected to the VBAT pin internally, this is the current during A/D VBAT operation.
DS39996F-page 364
2010-2011 Microchip Technology Inc.
PIC24FJ128GA310 FAMILY
TABLE 32-8: DC CHARACTERISTICS: I/O PIN INPUT SPECIFICATIONS
Standard Operating Conditions: 2V to 3.6V (unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
DC CHARACTERISTICS
Param
No.
Symbol
Characteristic
Min
Typ(1)
Max
Units
Conditions
VIL
Input Low Voltage(3)
I/O Pins with ST Buffer
I/O Pins with TTL Buffer
MCLR
DI10
DI11
DI15
DI16
DI17
DI18
DI19
VSS
VSS
VSS
VSS
VSS
VSS
VSS
—
—
—
—
—
—
—
0.2 VDD
0.15 VDD
0.2 VDD
0.2 VDD
0.2 VDD
0.3 VDD
0.8
V
V
V
V
V
V
V
OSCI (XT mode)
OSCI (HS mode)
I/O Pins with I2C™ Buffer
I/O Pins with SMBus Buffer
Input High Voltage(3)
SMBus enabled
VIH
DI20
DI21
I/O Pins with ST Buffer:
with Analog Functions,
Digital Only
0.8 VDD
0.8 VDD
—
—
VDD
5.5
V
V
I/O Pins with TTL Buffer:
with Analog Functions,
Digital Only
0.25 VDD + 0.8
0.25 VDD + 0.8
—
—
VDD
5.5
V
V
DI25
DI26
DI27
DI28
MCLR
0.8 VDD
0.7 VDD
0.7 VDD
—
—
—
VDD
VDD
VDD
V
V
V
OSCI (XT mode)
OSCI (HS mode)
I/O Pins with I2C™ Buffer:
with Analog Functions,
Digital Only
0.7 VDD
0.7 VDD
—
—
VDD
5.5
V
V
DI29
DI30
I/O Pins with SMBus Buffer:
with Analog Functions,
Digital Only
2.5V VPIN VDD
2.1
2.1
VDD
5.5
V
V
ICNPU
CNxx Pull-up Current
CNxx Pull-down Current
Input Leakage Current(2)
I/O Ports
150
150
250
250
550
550
A
A
VDD = 3.3V, VPIN = VSS
VDD = 3.3V, VPIN = VDD
DI30A ICNPD
IIL
DI50
—
—
—
—
—
—
+1
+1
+1
A
A
A
VSS VPIN VDD,
pin at high-impedance
VSS VPIN 5.5,
pin at high-impedance
DI51
Analog Input Pins
VSS VPIN VDD,
pin at high-impedance
DI55
DI56
MCLR
—
—
—
—
+1
+1
A
A
VSS VPIN VDD
OSCI/CLKI
VSS VPIN VDD,
EC, XT and HS modes
Note 1: Data in the “Typ” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only
and are not tested.
2: Negative current is defined as current sourced by the pin.
3: Refer to Table 1-4 for I/O pins buffer types.
2010-2011 Microchip Technology Inc.
DS39996F-page 365
PIC24FJ128GA310 FAMILY
TABLE 32-9: DC CHARACTERISTICS: I/O PIN OUTPUT SPECIFICATIONS
Standard Operating Conditions: 2V to 3.6V (unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
DC CHARACTERISTICS
Param
No.
Symbol
Characteristic
Min
Typ(1)
Max
Units
Conditions
VOL
Output Low Voltage
DO10
DO16
I/O Ports
—
—
—
—
—
—
—
—
0.4
0.4
0.4
0.4
V
V
V
V
IOL = 6.6 mA, VDD = 3.6V
IOL = 5.0 mA, VDD = 2V
IOL = 6.6 mA, VDD = 3.6V
IOL = 5.0 mA, VDD = 2V
OSCO/CLKO
VOH
Output High Voltage
DO20
I/O Ports
3.0
2.4
1.65
1.4
2.4
1.4
—
—
—
—
—
—
—
—
—
—
—
—
V
V
V
V
V
V
IOH = -3.0 mA, VDD = 3.6V
IOH = -6.0 mA, VDD = 3.6V
IOH = -1.0 mA, VDD = 2V
IOH = -3.0 mA, VDD = 2V
IOH = -6.0 mA, VDD = 3.6V
IOH = -1.0 mA, VDD = 2V
DO26
OSCO/CLKO
Note 1: Data in the “Typ” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only
and are not tested.
TABLE 32-10: DC CHARACTERISTICS: PROGRAM MEMORY
Standard Operating Conditions: 2V to 3.6V (unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
DC CHARACTERISTICS
Param
No.
Symbol
Characteristic
Min
Typ(1) Max
Units
Conditions
Program Flash Memory
Cell Endurance
D130
D131
D132B
EP
10000
VMIN
VMIN
—
—
—
—
20
—
3.6
3.6
—
E/W -40C to +85C
VPR
VDD for Read
V
V
VMIN = Minimum operating voltage
VMIN = Minimum operating voltage
VDD for Self-Timed Write
D133A TIW
Self-Timed Word Write
Cycle Time
s
Self-Timed Row Write
Cycle Time
—
1.5
—
—
ms
ms
D133B TIE
Self-Timed Page Erase
Time
20
40
D134
D135
TRETD
IDDP
Characteristic Retention
20
—
—
—
—
Year If no other specifications are violated
mA
Supply Current during
Programming
16
Note 1: Data in the “Typ” column is at 3.3V, 25°C unless otherwise stated.
DS39996F-page 366
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PIC24FJ128GA310 FAMILY
TABLE 32-11: INTERNAL VOLTAGE REGULATOR SPECIFICATIONS
Operating Conditions: -40°C < TA < +85°C (unless otherwise stated)
Param
No.
Symbol
Characteristics
Min
Typ Max Units
Comments
VRGOUT Regulator Output Voltage
—
1.14
4.7
1.8
—
V
V
VBG
Internal Band Gap Reference
External Filter Capacitor Value
1.2 1.26
CEFC
10
—
F Series resistance < 3 Ohm
recommended; < 5 Ohm
required.
TVREG
TBG
—
—
10
1
—
—
s
VREGS = 1with any POR or BOR
Band Gap Reference Start-up
Time
ms
VLVR
Low-Voltage Regulator Output
Voltage
—
1.2
—
V
RETEN = 1, LPCFG = 0
TABLE 32-12: VBAT OPERATING VOLTAGE SPECIFICATIONS
Param
Symbol
Characteristic
Min
Typ
Max
Units
Comments
No.
VBT
Operating Voltage
1.8
1.6
—
—
3.6
3.6
V
V
Battery connected to the VBAT pin
VBTADC
VBAT A/D Monitoring
A/D monitoring the VBAT pin using
the internal A/D channel
Voltage Specification(1)
Note 1: Measuring the A/D value, using the A/D, is represented by the equation:
Measured Voltage = ((VBAT/2)/VDD) * 1024) for 10-bit A/D and
Measured Voltage = ((VBAT/2)VDD) * 4096) for 12-bit A/D.
TABLE 32-13: CTMU CURRENT SOURCE SPECIFICATIONS
Standard Operating Conditions: 2V to 3.6V (unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
DC CHARACTERISTICS
Param
No.
Sym
Characteristic
Min Typ(1) Max Units
Comments
Conditions
IOUT1 CTMU Current
—
—
—
—
—
550
5.5
55
—
—
—
—
—
nA CTMUICON<1:0> = 00
A CTMUICON<1:0> = 01
A CTMUICON<1:0> = 10
A CTMUICON<1:0> = 11(2)
Source, Base Range
IOUT2 CTMU Current
Source, 10x Range
2.5V < VDD < VDDMAX
IOUT3 CTMU Current
Source, 100x Range
IOUT4 CTMU Current
Source, 1000x Range
550
3
V
Voltage Change per
Degree Celsius
mV/°C
Note 1: Nominal value at center point of current trim range (CTMUICON<7:2> = 000000).
2: Do not use this current range with temperature sensing diode.
2010-2011 Microchip Technology Inc.
DS39996F-page 367
PIC24FJ128GA310 FAMILY
TABLE 32-14: HIGH/LOW-VOLTAGE DETECT CHARACTERISTICS
Operating Conditions: -40°C < TA < +85°C (unless otherwise stated)
Param
No.
Symbol
Characteristic
Min
Typ
Max Units
Conditions
DC18 VHLVD
HLVD Voltage on VDD HLVDL<3:0> = 0100(1)
3.45
3.30
3.00
2.80
2.70
2.50
2.40
2.30
2.20
2.10
2.00
—
—
—
—
—
—
—
—
—
—
—
3.75
3.6
V
V
V
V
V
V
V
V
V
V
V
Transition
HLVDL<3:0> = 0101
HLVDL<3:0> = 0110
HLVDL<3:0> = 0111
HLVDL<3:0> = 1000
HLVDL<3:0> = 1001
HLVDL<3:0> = 1010
HLVDL<3:0> = 1011
HLVDL<3:0> = 1100
HLVDL<3:0> = 1101
HLVDL<3:0> = 1110
3.3
3.1
2.95
2.75
2.60
2.5
2.4
2.3
2.2
Note 1: Trip points for values of HLVD<3:0>, from ‘0000’ to ‘0011’, are not implemented.
TABLE 32-15: COMPARATOR DC SPECIFICATIONS
Operating Conditions: 2.0V < VDD < 3.6V, -40°C < TA < +85°C (unless otherwise stated)
Param
No.
Symbol
Characteristic
Min
Typ
Max
Units
Comments
D300
D301
D302
VIOFF
VICM
Input Offset Voltage*
—
0
20
—
—
40
VDD
—
mV
V
Input Common-Mode Voltage*
CMRR
Common-Mode Rejection
Ratio*
55
dB
* Parameters are characterized but not tested.
TABLE 32-16: COMPARATOR VOLTAGE REFERENCE DC SPECIFICATIONS
Operating Conditions: 2.0V < VDD < 3.6V, -40°C < TA < +85°C (unless otherwise stated)
Param
No.
Symbol
Characteristic
Min
Typ
Max
Units
Comments
VRD310 CVRES
VRD311 CVRAA
VRD312 CVRUR
Resolution
VDD/24
—
—
—
VDD/32
AVDD – 1.5
—
LSb
LSb
Absolute Accuracy
Unit Resistor Value (R)
—
2K
DS39996F-page 368
2010-2011 Microchip Technology Inc.
PIC24FJ128GA310 FAMILY
32.2 AC Characteristics and Timing Parameters
The information contained in this section defines the PIC24FJ128GA310 family AC characteristics and timing parameters.
TABLE 32-17: TEMPERATURE AND VOLTAGE SPECIFICATIONS – AC
Standard Operating Conditions: 2V to 3.6V (unless otherwise stated)
AC CHARACTERISTICS
Operating temperature -40°C TA +85°C for Industrial
Operating voltage VDD range as described in Section 32.1 “DC Characteristics”.
FIGURE 32-2:
LOAD CONDITIONS FOR DEVICE TIMING SPECIFICATIONS
Load Condition 1 – for all pins except OSCO
VDD/2
Load Condition 2 – for OSCO
CL
RL
Pin
VSS
CL
Pin
RL = 464
CL = 50 pF for all pins except OSCO
15 pF for OSCO output
VSS
TABLE 32-18: CAPACITIVE LOADING REQUIREMENTS ON OUTPUT PINS
Param
Symbol
Characteristic
Min
Typ(1) Max Units
Conditions
No.
DO50 COSCO
OSCO/CLKO Pin
—
—
15
pF In XT and HS modes when
external clock is used to drive
OSCI
DO56 CIO
DO58 CB
All I/O Pins and OSCO
SCLx, SDAx
—
—
—
—
50
pF EC mode
pF In I2C™ mode
400
Note 1: Data in the “Typ” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance
only and are not tested.
2010-2011 Microchip Technology Inc.
DS39996F-page 369
PIC24FJ128GA310 FAMILY
FIGURE 32-3:
EXTERNAL CLOCK TIMING
Q4
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Q1
Q3
Q2
OSCI
OS20
OS25
OS30 OS30
OS31 OS31
CLKO
OS40
OS41
TABLE 32-19: EXTERNAL CLOCK TIMING REQUIREMENTS
Standard Operating Conditions: 2V to 3.6V (unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
AC CHARACTERISTICS
Param
No.
Symbol
Characteristic
Min
Typ(1)
Max
Units
Conditions
OS10 FOSC
External CLKI Frequency
(External clocks allowed
only in EC mode)
DC
4
—
—
32
8
MHz EC
MHz ECPLL
Oscillator Frequency
3.5
4
10
10
31
—
—
—
—
—
10
8
32
8
MHz XT
MHz XTPLL
MHz HS
MHz HSPLL
33
kHz
SOSC
OS20 TOSC
OS25 TCY
TOSC = 1/FOSC
—
—
—
—
See Parameter OS10 for
FOSC value
Instruction Cycle Time(2)
62.5
—
—
DC
—
ns
ns
OS30 TosL,
TosH
External Clock in (OSCI) 0.45 x TOSC
High or Low Time
EC
EC
OS31 TosR, External Clock in (OSCI)
—
—
20
ns
TosF
OS40 TckR
OS41 TckF
Rise or Fall Time
CLKO Rise Time(3)
CLKO Fall Time(3)
—
—
6
6
10
10
ns
ns
Note 1: Data in the “Typ” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only
and are not tested.
2: Instruction cycle period (TCY) equals two times the input oscillator time base period. All specified values are
based on characterization data for that particular oscillator type, under standard operating conditions, with
the device executing code. Exceeding these specified limits may result in an unstable oscillator operation
and/or higher than expected current consumption. All devices are tested to operate at “Min.” values with an
external clock applied to the OSCI/CLKI pin. When an external clock input is used, the “Max.” cycle time
limit is “DC” (no clock) for all devices.
3: Measurements are taken in EC mode. The CLKO signal is measured on the OSCO pin. CLKO is low for the
Q1-Q2 period (1/2 TCY) and high for the Q3-Q4 period (1/2 TCY).
DS39996F-page 370
2010-2011 Microchip Technology Inc.
PIC24FJ128GA310 FAMILY
TABLE 32-20: PLL CLOCK TIMING SPECIFICATIONS (VDD = 2.2V TO 3.6V)
Standard Operating Conditions: 2V to 3.6V (unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
AC CHARACTERISTICS
Param
No.
Symbol
Characteristic(1)
Min
Typ(2)
Max
Units
Conditions
OS50 FPLLI
PLL Input Frequency
Range(2)
4
4
—
—
—
—
8
8
MHz ECPLL mode
MHz HSPLL mode
MHz XTPLL mode
s
4
8
OS52 TLOCK
OS53 DCLK
PLL Start-up Time
(Lock Time)
—
128
CLKO Stability (Jitter)
-0.25
—
0.25
%
Note 1: These parameters are characterized but not tested in manufacturing.
2: Data in the “Typ” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance
only and are not tested.
TABLE 32-21: INTERNAL RC ACCURACY
Standard Operating Conditions: 2V to 3.6V (unless otherwise stated)
AC CHARACTERISTICS
Operating temperature
-40°C TA +85°C for Industrial
Param
No.
Characteristic
Min
Typ
Max Units
Conditions
F20
FRC Accuracy @
8 MHz(1,2)
-1
—
—
—
1
%
%
%
-10°C TA +85°C 2V VDD 3.6V
-40°C TA -10°C 2V VDD 3.6V
-1.5
-20
1.5
20
F21
LPRC @ 31 kHz
-40°C TA +85°C VCAP (on-chip regulator
output voltage) = 1.8V
Note 1: Frequency is calibrated at 25°C and 3.3V. OSCTUN bits can be used to compensate for temperature drift.
2: To achieve this accuracy, physical stress applied to the microcontroller package (ex., by flexing the PCB)
must be kept to a minimum.
TABLE 32-22: RC OSCILLATOR START-UP TIME
Standard Operating Conditions: 2V to 3.6V (unless otherwise stated)
AC CHARACTERISTICS
Operating temperature
-40°C TA +85°C for Industrial
Param
No.
Characteristic
Min
Typ
Max
Units
Conditions
TFRC
TLPRC
—
—
15
50
—
—
s
s
2010-2011 Microchip Technology Inc.
DS39996F-page 371
PIC24FJ128GA310 FAMILY
FIGURE 32-4:
CLKO AND I/O TIMING CHARACTERISTICS
I/O Pin
(Input)
DI35
DI40
I/O Pin
(Output)
New Value
Old Value
DO31
DO32
Note:
Refer to Figure 32-2 for load conditions.
TABLE 32-23: CLKO AND I/O TIMING REQUIREMENTS
Standard Operating Conditions: 2V to 3.6V (unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
AC CHARACTERISTICS
Param
No.
Symbol
Characteristic
Min
Typ(1)
Max
Units
Conditions
DO31 TIOR
DO32 TIOF
Port Output Rise Time
Port Output Fall Time
—
—
20
10
10
—
25
25
—
ns
ns
ns
DI35
TINP
INTx Pin High or Low
Time (input)
DI40
TRBP
CNx High or Low Time
(input)
2
—
—
TCY
Note 1: Data in the “Typ” column is at 3.3V, 25°C unless otherwise stated.
DS39996F-page 372
2010-2011 Microchip Technology Inc.
PIC24FJ128GA310 FAMILY
TABLE 32-24: RESET AND BROWN-OUT RESET REQUIREMENTS
Standard Operating Conditions: 2V to 3.6V (unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
AC CHARACTERISTICS
Param
No.
Symbol
Characteristic
Min
Typ
Max
Units
Conditions
SY10 TMCL
SY12 TPOR
SY13 TIOZ
MCLR Pulse width (Low)
Power-on Reset Delay
2
—
2
—
—
s
s
ns
—
—
I/O High-Impedance from
MCLR Low or Watchdog
Timer Reset
—
100
SY25 TBOR
Brown-out Reset Pulse
Width
1
—
—
s
VDD VBOR
TRST
Internal State Reset Time
—
—
50
20
—
—
s
s
SY71 TPM
Program Memory Wake-up
Time
Sleep wake-up with
VREGS = 0
—
—
—
—
1
—
—
—
—
s
s
s
s
Sleep wake-up with
VREGS = 1
SY72 TLVR
Low-Voltage Regulator
Wake-up Time
90
Sleep wake-up with
VREGS = 0
70
Sleep wake-up with
VREGS = 1
TDSWU Deep Sleep Wake-up Time
200
VCAP fully discharged before
wake-up
2010-2011 Microchip Technology Inc.
DS39996F-page 373
PIC24FJ128GA310 FAMILY
TABLE 32-25: A/D MODULE SPECIFICATIONS
Standard Operating Conditions: 2V to 3.6V
(unless otherwise stated)
Operating temperature
AC CHARACTERISTICS
-40°C TA +85°C
Param
Symbol
No.
Characteristic
Min.
Typ
Max.
Units
Conditions
Device Supply
AD01 AVDD
AD02 AVSS
Module VDD Supply
Module VSS Supply
Greater of
VDD – 0.3
or 2.2
—
—
Lesser of
VDD + 0.3
or 3.6
V
V
VSS – 0.3
VSS + 0.3
Reference Inputs
AD05 VREFH
AD06 VREFL
AD07 VREF
Reference Voltage High
Reference Voltage Low
AVSS + 1.7
AVSS
—
—
—
AVDD
V
V
V
AVDD – 1.7
AVDD + 0.3
Absolute Reference
Voltage
AVSS – 0.3
Analog Input
AD10 VINH-VINL Full-Scale Input Span
VREFL
—
—
—
VREFH
AVDD + 0.3
AVDD/3
V
V
V
(Note 2)
AD11 VIN
AD12 VINL
Absolute Input Voltage
AVSS – 0.3
AVSS – 0.3
Absolute VINL Input
Voltage
AD13
Leakage Current
—
—
±1.0
—
±610
2.5K
nA
VINL = AVSS = VREFL = 0V,
AVDD = VREFH = 3V,
Source Impedance = 2.5 k
AD17 RIN
RecommendedImpedance
of Analog Voltage Source
10-bit
A/D Accuracy
AD20B Nr
Resolution
—
—
12
±1
—
bits
AD21B INL
Integral Nonlinearity
<±2
LSb VINL = AVSS = VREFL = 0V,
AVDD = VREFH = 3V
AD22B DNL
AD23B GERR
AD24B EOFF
AD25B
Differential Nonlinearity
Gain Error
—
—
—
—
—
±1
±1
—
<±1
±3
LSb VINL = AVSS = VREFL = 0V,
AVDD = VREFH = 3V
LSb VINL = AVSS = VREFL = 0V,
AVDD = VREFH = 3V
Offset Error
±2
LSb VINL = AVSS = VREFL = 0V,
AVDD = VREFH = 3V
Monotonicity(1)
—
—
Guaranteed
Note 1: The A/D conversion result never decreases with an increase in the input voltage and has no missing
codes.
2: Measurements are taken with the external VREF+ and VREF- used as the A/D voltage reference.
DS39996F-page 374
2010-2011 Microchip Technology Inc.
PIC24FJ128GA310 FAMILY
TABLE 32-26: A/D CONVERSION TIMING REQUIREMENTS(1)
Standard Operating Conditions: 2V to 3.6V
(unless otherwise stated)
AC CHARACTERISTICS
Operating temperature -40°C TA +85°C
Param
Symbol
No.
Characteristic
Min.
Typ
Max.
Units
Conditions
Clock Parameters
AD50
AD51
TAD
tRC
A/D Clock Period
A/D Internal RC Oscillator Period
75
—
—
—
—
ns
ns
TCY = 75 ns, AD1CON3
in default state
250
Conversion Rate
AD55
AD56
AD57
tCONV
FCNV
tSAMP
Conversion Time
Throughput Rate
Sample Time
—
—
—
14
—
1
—
200
—
TAD
ksps AVDD > 2.7V
TAD
Clock Parameters
AD61
tPSS
Sample Start Delay from Setting
Sample bit (SAMP)
2
—
3
TAD
Note 1: Because the sample caps will eventually lose charge, clock rates below 10 kHz can affect linearity
performance, especially at elevated temperatures.
2010-2011 Microchip Technology Inc.
DS39996F-page 375
PIC24FJ128GA310 FAMILY
NOTES:
DS39996F-page 376
2010-2011 Microchip Technology Inc.
PIC24FJ128GA310 FAMILY
33.0 PACKAGING INFORMATION
33.1 Package Marking Information
64-Lead QFN (9x9x0.9 mm)
Example
XXXXXXXXXXX
XXXXXXXXXXX
XXXXXXXXXXX
YYWWNNN
PIC24FJ128
GA306-I/MR
e
3
1150017
64-Lead TQFP (10x10x1 mm)
Example
XXXXXXXXXX
XXXXXXXXXX
XXXXXXXXXX
YYWWNNN
PIC24FJ128
GA306-I/
PT
e
3
1120017
80-Lead TQFP (12x12x1mm)
Example
XXXXXXXXXXXX
XXXXXXXXXXXX
YYWWNNN
PIC24F128GA
308-I/PT
e
3
1150017
Legend: XX...X Customer-specific information
Y
YY
WW
NNN
Year code (last digit of calendar year)
Year code (last 2 digits of calendar year)
Week code (week of January 1 is week ‘01’)
Alphanumeric traceability code
e
3
Pb-free JEDEC designator for Matte Tin (Sn)
*
This package is Pb-free. The Pb-free JEDEC designator (
can be found on the outer packaging for this package.
)
e3
Note: In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
2010-2011 Microchip Technology Inc.
DS39996F-page 377
PIC24FJ128GA310 FAMILY
33.2 Package Marking Information
100-Lead TQFP (12x12x1 mm)
Example
310-I/PT
XXXXXXXXXXXX
XXXXXXXXXXXX
YYWWNNN
PIC24FJ128GA
e
3
1110017
100-Lead TQFP (14x14x1mm)
Example
XXXXXXXXXXXX
XXXXXXXXXXXX
YYWWNNN
PIC24FJ128GA
310-I/PF
e
3
1150017
121-BGA (10x10x1.1 mm)
Example
PIC24FJ128
GA310-I/BG
XXXXXXXXXXX
XXXXXXXXXXX
XXXXXXXXXXX
YYWWNNN
e
3
1120017
DS39996F-page 378
2010-2011 Microchip Technology Inc.
PIC24FJ128GA310 FAMILY
33.3 Package Details
The following sections give the technical details of the packages.
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
2010-2011 Microchip Technology Inc.
DS39996F-page 379
PIC24FJ128GA310 FAMILY
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
DS39996F-page 380
2010-2011 Microchip Technology Inc.
PIC24FJ128GA310 FAMILY
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
2010-2011 Microchip Technology Inc.
DS39996F-page 381
PIC24FJ128GA310 FAMILY
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DS39996F-page 382
2010-2011 Microchip Technology Inc.
PIC24FJ128GA310 FAMILY
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2010-2011 Microchip Technology Inc.
DS39996F-page 383
PIC24FJ128GA310 FAMILY
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9 ꢈꢉꢆꢇꢇꢅ?ꢃ#&ꢍ
9 ꢈꢉꢆꢇꢇꢅ7ꢈꢄꢕ&ꢍ
.
ꢑ
.ꢀ
ꢑꢀ
ꢌ
ꢀꢔꢁꢓꢓꢅ1ꢗ+
ꢀꢔꢁꢓꢓꢅ1ꢗ+
ꢀꢎꢁꢓꢓꢅ1ꢗ+
ꢀꢎꢁꢓꢓꢅ1ꢗ+
M
ꢒꢋꢇ#ꢈ#ꢅꢂꢆꢌ4ꢆꢕꢈꢅ?ꢃ#&ꢍ
ꢒꢋꢇ#ꢈ#ꢅꢂꢆꢌ4ꢆꢕꢈꢅ7ꢈꢄꢕ&ꢍ
7ꢈꢆ#ꢅꢘꢍꢃꢌ4ꢄꢈ!!
7ꢈꢆ#ꢅ?ꢃ#&ꢍ
ꢒꢋꢇ#ꢅꢑꢉꢆ%&ꢅꢖꢄꢕꢇꢈꢅꢘꢋꢏ
ꢒꢋꢇ#ꢅꢑꢉꢆ%&ꢅꢖꢄꢕꢇꢈꢅ1ꢋ&&ꢋ'
ꢓꢁꢓꢛ
ꢓꢁꢀꢜ
ꢀꢀꢝ
ꢓꢁꢎꢓ
ꢓꢁꢎꢜ
ꢀꢐꢝ
)
ꢁ
ꢓꢁꢎꢎ
ꢀꢎꢝ
ꢀꢎꢝ
ꢂ
ꢀꢀꢝ
ꢀꢐꢝ
' ꢋꢄꢊ(
ꢀꢁ ꢂꢃꢄꢅꢀꢅ ꢃ!"ꢆꢇꢅꢃꢄ#ꢈ$ꢅ%ꢈꢆ&"ꢉꢈꢅ'ꢆꢊꢅ ꢆꢉꢊ(ꢅ)"&ꢅ'"!&ꢅ)ꢈꢅꢇꢋꢌꢆ&ꢈ#ꢅ*ꢃ&ꢍꢃꢄꢅ&ꢍꢈꢅꢍꢆ&ꢌꢍꢈ#ꢅꢆꢉꢈꢆꢁ
ꢎꢁ +ꢍꢆ'%ꢈꢉ!ꢅꢆ&ꢅꢌꢋꢉꢄꢈꢉ!ꢅꢆꢉꢈꢅꢋꢏ&ꢃꢋꢄꢆꢇ,ꢅ!ꢃ-ꢈꢅ'ꢆꢊꢅ ꢆꢉꢊꢁ
ꢐꢁ ꢑꢃ'ꢈꢄ!ꢃꢋꢄ!ꢅꢑꢀꢅꢆꢄ#ꢅ.ꢀꢅ#ꢋꢅꢄꢋ&ꢅꢃꢄꢌꢇ"#ꢈꢅ'ꢋꢇ#ꢅ%ꢇꢆ!ꢍꢅꢋꢉꢅꢏꢉꢋ&ꢉ"!ꢃꢋꢄ!ꢁꢅꢒꢋꢇ#ꢅ%ꢇꢆ!ꢍꢅꢋꢉꢅꢏꢉꢋ&ꢉ"!ꢃꢋꢄ!ꢅ!ꢍꢆꢇꢇꢅꢄꢋ&ꢅꢈ$ꢌꢈꢈ#ꢅꢓꢁꢎ/ꢅ''ꢅꢏꢈꢉꢅ!ꢃ#ꢈꢁ
ꢔꢁ ꢑꢃ'ꢈꢄ!ꢃꢋꢄꢃꢄꢕꢅꢆꢄ#ꢅ&ꢋꢇꢈꢉꢆꢄꢌꢃꢄꢕꢅꢏꢈꢉꢅꢖꢗꢒ.ꢅ0ꢀꢔꢁ/ꢒꢁ
1ꢗ+2 1ꢆ!ꢃꢌꢅꢑꢃ'ꢈꢄ!ꢃꢋꢄꢁꢅꢘꢍꢈꢋꢉꢈ&ꢃꢌꢆꢇꢇꢊꢅꢈ$ꢆꢌ&ꢅ ꢆꢇ"ꢈꢅ!ꢍꢋ*ꢄꢅ*ꢃ&ꢍꢋ"&ꢅ&ꢋꢇꢈꢉꢆꢄꢌꢈ!ꢁ
ꢙ.32 ꢙꢈ%ꢈꢉꢈꢄꢌꢈꢅꢑꢃ'ꢈꢄ!ꢃꢋꢄ(ꢅ"!"ꢆꢇꢇꢊꢅ*ꢃ&ꢍꢋ"&ꢅ&ꢋꢇꢈꢉꢆꢄꢌꢈ(ꢅ%ꢋꢉꢅꢃꢄ%ꢋꢉ'ꢆ&ꢃꢋꢄꢅꢏ"ꢉꢏꢋ!ꢈ!ꢅꢋꢄꢇꢊꢁ
ꢒꢃꢌꢉꢋꢌꢍꢃꢏ ꢘꢈꢌꢍꢄꢋꢇꢋꢕꢊ ꢑꢉꢆ*ꢃꢄꢕ +ꢓꢔꢞꢓꢛꢎ1
DS39996F-page 384
2010-2011 Microchip Technology Inc.
PIC24FJ128GA310 FAMILY
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
2010-2011 Microchip Technology Inc.
DS39996F-page 385
PIC24FJ128GA310 FAMILY
ꢘꢙꢙꢂꢃꢄꢅꢆꢇꢈꢉꢅꢊꢋꢌꢍꢇꢎꢏꢌꢐꢇꢑꢒꢅꢆꢇꢓꢉꢅꢋꢔꢅꢍꢕꢇꢖꢈꢎꢗꢇMꢇꢘ#ꢚꢘ#ꢚꢘꢇꢛꢛꢇꢜ ꢆ!"ꢇ#$ꢙꢙꢇꢛꢛꢇ%ꢎꢑꢓꢈ&
' ꢋꢄ( 3ꢋꢉꢅ&ꢍꢈꢅ'ꢋ!&ꢅꢌ"ꢉꢉꢈꢄ&ꢅꢏꢆꢌ4ꢆꢕꢈꢅ#ꢉꢆ*ꢃꢄꢕ!(ꢅꢏꢇꢈꢆ!ꢈꢅ!ꢈꢈꢅ&ꢍꢈꢅꢒꢃꢌꢉꢋꢌꢍꢃꢏꢅꢂꢆꢌ4ꢆꢕꢃꢄꢕꢅꢗꢏꢈꢌꢃ%ꢃꢌꢆ&ꢃꢋꢄꢅꢇꢋꢌꢆ&ꢈ#ꢅꢆ&ꢅ
ꢍ&&ꢏ255***ꢁ'ꢃꢌꢉꢋꢌꢍꢃꢏꢁꢌꢋ'5ꢏꢆꢌ4ꢆꢕꢃꢄꢕ
D
D1
e
E
E1
N
b
123
NOTE 2
NOTE 1
c
α
A
φ
L
A1
β
A2
L1
6ꢄꢃ&!
ꢑꢃ'ꢈꢄ!ꢃꢋꢄꢅ7ꢃ'ꢃ&!
ꢒꢚ77ꢚꢒ.ꢘ.ꢙꢗ
89ꢒ
ꢒꢚ8
ꢒꢖ:
8"')ꢈꢉꢅꢋ%ꢅ7ꢈꢆ#!
7ꢈꢆ#ꢅꢂꢃ&ꢌꢍ
9 ꢈꢉꢆꢇꢇꢅ<ꢈꢃꢕꢍ&
8
ꢈ
ꢖ
ꢀꢓꢓ
ꢓꢁꢔꢓꢅ1ꢗ+
M
M
ꢀꢁꢎꢓ
ꢀꢁꢓ/
ꢓꢁꢀ/
ꢓꢁꢜ/
ꢒꢋꢇ#ꢈ#ꢅꢂꢆꢌ4ꢆꢕꢈꢅꢘꢍꢃꢌ4ꢄꢈ!!
ꢗ&ꢆꢄ#ꢋ%%ꢅꢅ
3ꢋꢋ&ꢅ7ꢈꢄꢕ&ꢍ
ꢖꢎ
ꢖꢀ
7
ꢓꢁꢛ/
ꢓꢁꢓ/
ꢓꢁꢔ/
ꢀꢁꢓꢓ
M
ꢓꢁ;ꢓ
3ꢋꢋ&ꢏꢉꢃꢄ&
3ꢋꢋ&ꢅꢖꢄꢕꢇꢈ
7ꢀ
ꢀ
ꢀꢁꢓꢓꢅꢙ.3
ꢐꢁ/ꢝ
ꢓꢝ
ꢜꢝ
9 ꢈꢉꢆꢇꢇꢅ?ꢃ#&ꢍ
9 ꢈꢉꢆꢇꢇꢅ7ꢈꢄꢕ&ꢍ
.
ꢑ
.ꢀ
ꢑꢀ
ꢌ
ꢀꢔꢁꢓꢓꢅ1ꢗ+
ꢀꢔꢁꢓꢓꢅ1ꢗ+
ꢀꢎꢁꢓꢓꢅ1ꢗ+
ꢀꢎꢁꢓꢓꢅ1ꢗ+
M
ꢒꢋꢇ#ꢈ#ꢅꢂꢆꢌ4ꢆꢕꢈꢅ?ꢃ#&ꢍ
ꢒꢋꢇ#ꢈ#ꢅꢂꢆꢌ4ꢆꢕꢈꢅ7ꢈꢄꢕ&ꢍ
7ꢈꢆ#ꢅꢘꢍꢃꢌ4ꢄꢈ!!
7ꢈꢆ#ꢅ?ꢃ#&ꢍ
ꢒꢋꢇ#ꢅꢑꢉꢆ%&ꢅꢖꢄꢕꢇꢈꢅꢘꢋꢏ
ꢒꢋꢇ#ꢅꢑꢉꢆ%&ꢅꢖꢄꢕꢇꢈꢅ1ꢋ&&ꢋ'
ꢓꢁꢓꢛ
ꢓꢁꢀꢐ
ꢀꢀꢝ
ꢓꢁꢎꢓ
ꢓꢁꢎꢐ
ꢀꢐꢝ
)
ꢁ
ꢓꢁꢀ@
ꢀꢎꢝ
ꢀꢎꢝ
ꢂ
ꢀꢀꢝ
ꢀꢐꢝ
' ꢋꢄꢊ(
ꢀꢁ ꢂꢃꢄꢅꢀꢅ ꢃ!"ꢆꢇꢅꢃꢄ#ꢈ$ꢅ%ꢈꢆ&"ꢉꢈꢅ'ꢆꢊꢅ ꢆꢉꢊ(ꢅ)"&ꢅ'"!&ꢅ)ꢈꢅꢇꢋꢌꢆ&ꢈ#ꢅ*ꢃ&ꢍꢃꢄꢅ&ꢍꢈꢅꢍꢆ&ꢌꢍꢈ#ꢅꢆꢉꢈꢆꢁ
ꢎꢁ +ꢍꢆ'%ꢈꢉ!ꢅꢆ&ꢅꢌꢋꢉꢄꢈꢉ!ꢅꢆꢉꢈꢅꢋꢏ&ꢃꢋꢄꢆꢇ,ꢅ!ꢃ-ꢈꢅ'ꢆꢊꢅ ꢆꢉꢊꢁ
ꢐꢁ ꢑꢃ'ꢈꢄ!ꢃꢋꢄ!ꢅꢑꢀꢅꢆꢄ#ꢅ.ꢀꢅ#ꢋꢅꢄꢋ&ꢅꢃꢄꢌꢇ"#ꢈꢅ'ꢋꢇ#ꢅ%ꢇꢆ!ꢍꢅꢋꢉꢅꢏꢉꢋ&ꢉ"!ꢃꢋꢄ!ꢁꢅꢒꢋꢇ#ꢅ%ꢇꢆ!ꢍꢅꢋꢉꢅꢏꢉꢋ&ꢉ"!ꢃꢋꢄ!ꢅ!ꢍꢆꢇꢇꢅꢄꢋ&ꢅꢈ$ꢌꢈꢈ#ꢅꢓꢁꢎ/ꢅ''ꢅꢏꢈꢉꢅ!ꢃ#ꢈꢁ
ꢔꢁ ꢑꢃ'ꢈꢄ!ꢃꢋꢄꢃꢄꢕꢅꢆꢄ#ꢅ&ꢋꢇꢈꢉꢆꢄꢌꢃꢄꢕꢅꢏꢈꢉꢅꢖꢗꢒ.ꢅ0ꢀꢔꢁ/ꢒꢁ
1ꢗ+2 1ꢆ!ꢃꢌꢅꢑꢃ'ꢈꢄ!ꢃꢋꢄꢁꢅꢘꢍꢈꢋꢉꢈ&ꢃꢌꢆꢇꢇꢊꢅꢈ$ꢆꢌ&ꢅ ꢆꢇ"ꢈꢅ!ꢍꢋ*ꢄꢅ*ꢃ&ꢍꢋ"&ꢅ&ꢋꢇꢈꢉꢆꢄꢌꢈ!ꢁ
ꢙ.32 ꢙꢈ%ꢈꢉꢈꢄꢌꢈꢅꢑꢃ'ꢈꢄ!ꢃꢋꢄ(ꢅ"!"ꢆꢇꢇꢊꢅ*ꢃ&ꢍꢋ"&ꢅ&ꢋꢇꢈꢉꢆꢄꢌꢈ(ꢅ%ꢋꢉꢅꢃꢄ%ꢋꢉ'ꢆ&ꢃꢋꢄꢅꢏ"ꢉꢏꢋ!ꢈ!ꢅꢋꢄꢇꢊꢁ
ꢒꢃꢌꢉꢋꢌꢍꢃꢏ ꢘꢈꢌꢍꢄꢋꢇꢋꢕꢊ ꢑꢉꢆ*ꢃꢄꢕ +ꢓꢔꢞꢀꢓꢓ1
DS39996F-page 386
2010-2011 Microchip Technology Inc.
PIC24FJ128GA310 FAMILY
ꢘꢙꢙꢂꢃꢄꢅꢆꢇꢈꢉꢅꢊꢋꢌꢍꢇꢎꢏꢌꢐꢇꢑꢒꢅꢆꢇꢓꢉꢅꢋꢔꢅꢍꢕꢇꢖꢈꢎꢗꢇMꢇꢘ#ꢚꢘ#ꢚꢘꢇꢛꢛꢇꢜ ꢆ!"ꢇ#$ꢙꢙꢇꢛꢛꢇ%ꢎꢑꢓꢈ&
' ꢋꢄ( 3ꢋꢉꢅ&ꢍꢈꢅ'ꢋ!&ꢅꢌ"ꢉꢉꢈꢄ&ꢅꢏꢆꢌ4ꢆꢕꢈꢅ#ꢉꢆ*ꢃꢄꢕ!(ꢅꢏꢇꢈꢆ!ꢈꢅ!ꢈꢈꢅ&ꢍꢈꢅꢒꢃꢌꢉꢋꢌꢍꢃꢏꢅꢂꢆꢌ4ꢆꢕꢃꢄꢕꢅꢗꢏꢈꢌꢃ%ꢃꢌꢆ&ꢃꢋꢄꢅꢇꢋꢌꢆ&ꢈ#ꢅꢆ&ꢅ
ꢍ&&ꢏ255***ꢁ'ꢃꢌꢉꢋꢌꢍꢃꢏꢁꢌꢋ'5ꢏꢆꢌ4ꢆꢕꢃꢄꢕ
2010-2011 Microchip Technology Inc.
DS39996F-page 387
PIC24FJ128GA310 FAMILY
ꢘꢙꢙꢂꢃꢄꢅꢆꢇꢈꢉꢅꢊꢋꢌꢍꢇꢎꢏꢌꢐꢇꢑꢒꢅꢆꢇꢓꢉꢅꢋꢔꢅꢍꢕꢇꢖꢈꢓꢗꢇMꢇꢘꢁꢚꢘꢁꢚꢘꢇꢛꢛꢇꢜ ꢆ!"ꢇ#$ꢙꢙꢇꢛꢛꢇ%ꢎꢑꢓꢈ&
' ꢋꢄ( 3ꢋꢉꢅ&ꢍꢈꢅ'ꢋ!&ꢅꢌ"ꢉꢉꢈꢄ&ꢅꢏꢆꢌ4ꢆꢕꢈꢅ#ꢉꢆ*ꢃꢄꢕ!(ꢅꢏꢇꢈꢆ!ꢈꢅ!ꢈꢈꢅ&ꢍꢈꢅꢒꢃꢌꢉꢋꢌꢍꢃꢏꢅꢂꢆꢌ4ꢆꢕꢃꢄꢕꢅꢗꢏꢈꢌꢃ%ꢃꢌꢆ&ꢃꢋꢄꢅꢇꢋꢌꢆ&ꢈ#ꢅꢆ&ꢅ
ꢍ&&ꢏ255***ꢁ'ꢃꢌꢉꢋꢌꢍꢃꢏꢁꢌꢋ'5ꢏꢆꢌ4ꢆꢕꢃꢄꢕ
D
D1
e
E1
E
b
N
α
NOTE 1
1 23
NOTE 2
A
φ
c
A2
A1
β
L1
L
6ꢄꢃ&!
ꢑꢃ'ꢈꢄ!ꢃꢋꢄꢅ7ꢃ'ꢃ&!
ꢒꢚ77ꢚꢒ.ꢘ.ꢙꢗ
89ꢒ
ꢒꢚ8
ꢒꢖ:
8"')ꢈꢉꢅꢋ%ꢅ7ꢈꢆ#!
7ꢈꢆ#ꢅꢂꢃ&ꢌꢍ
9 ꢈꢉꢆꢇꢇꢅ<ꢈꢃꢕꢍ&
8
ꢈ
ꢖ
ꢀꢓꢓ
ꢓꢁ/ꢓꢅ1ꢗ+
M
M
ꢀꢁꢎꢓ
ꢀꢁꢓ/
ꢓꢁꢀ/
ꢓꢁꢜ/
ꢒꢋꢇ#ꢈ#ꢅꢂꢆꢌ4ꢆꢕꢈꢅꢘꢍꢃꢌ4ꢄꢈ!!
ꢗ&ꢆꢄ#ꢋ%%ꢅꢅ
3ꢋꢋ&ꢅ7ꢈꢄꢕ&ꢍ
ꢖꢎ
ꢖꢀ
7
ꢓꢁꢛ/
ꢓꢁꢓ/
ꢓꢁꢔ/
ꢀꢁꢓꢓ
M
ꢓꢁ;ꢓ
3ꢋꢋ&ꢏꢉꢃꢄ&
3ꢋꢋ&ꢅꢖꢄꢕꢇꢈ
7ꢀ
ꢀ
ꢀꢁꢓꢓꢅꢙ.3
ꢐꢁ/ꢝ
ꢓꢝ
ꢜꢝ
9 ꢈꢉꢆꢇꢇꢅ?ꢃ#&ꢍ
9 ꢈꢉꢆꢇꢇꢅ7ꢈꢄꢕ&ꢍ
.
ꢑ
.ꢀ
ꢑꢀ
ꢌ
ꢀ;ꢁꢓꢓꢅ1ꢗ+
ꢀ;ꢁꢓꢓꢅ1ꢗ+
ꢀꢔꢁꢓꢓꢅ1ꢗ+
ꢀꢔꢁꢓꢓꢅ1ꢗ+
M
ꢒꢋꢇ#ꢈ#ꢅꢂꢆꢌ4ꢆꢕꢈꢅ?ꢃ#&ꢍ
ꢒꢋꢇ#ꢈ#ꢅꢂꢆꢌ4ꢆꢕꢈꢅ7ꢈꢄꢕ&ꢍ
7ꢈꢆ#ꢅꢘꢍꢃꢌ4ꢄꢈ!!
7ꢈꢆ#ꢅ?ꢃ#&ꢍ
ꢒꢋꢇ#ꢅꢑꢉꢆ%&ꢅꢖꢄꢕꢇꢈꢅꢘꢋꢏ
ꢒꢋꢇ#ꢅꢑꢉꢆ%&ꢅꢖꢄꢕꢇꢈꢅ1ꢋ&&ꢋ'
ꢓꢁꢓꢛ
ꢓꢁꢀꢜ
ꢀꢀꢝ
ꢓꢁꢎꢓ
ꢓꢁꢎꢜ
ꢀꢐꢝ
)
ꢁ
ꢓꢁꢎꢎ
ꢀꢎꢝ
ꢀꢎꢝ
ꢂ
ꢀꢀꢝ
ꢀꢐꢝ
' ꢋꢄꢊ(
ꢀꢁ ꢂꢃꢄꢅꢀꢅ ꢃ!"ꢆꢇꢅꢃꢄ#ꢈ$ꢅ%ꢈꢆ&"ꢉꢈꢅ'ꢆꢊꢅ ꢆꢉꢊ(ꢅ)"&ꢅ'"!&ꢅ)ꢈꢅꢇꢋꢌꢆ&ꢈ#ꢅ*ꢃ&ꢍꢃꢄꢅ&ꢍꢈꢅꢍꢆ&ꢌꢍꢈ#ꢅꢆꢉꢈꢆꢁ
ꢎꢁ +ꢍꢆ'%ꢈꢉ!ꢅꢆ&ꢅꢌꢋꢉꢄꢈꢉ!ꢅꢆꢉꢈꢅꢋꢏ&ꢃꢋꢄꢆꢇ,ꢅ!ꢃ-ꢈꢅ'ꢆꢊꢅ ꢆꢉꢊꢁ
ꢐꢁ ꢑꢃ'ꢈꢄ!ꢃꢋꢄ!ꢅꢑꢀꢅꢆꢄ#ꢅ.ꢀꢅ#ꢋꢅꢄꢋ&ꢅꢃꢄꢌꢇ"#ꢈꢅ'ꢋꢇ#ꢅ%ꢇꢆ!ꢍꢅꢋꢉꢅꢏꢉꢋ&ꢉ"!ꢃꢋꢄ!ꢁꢅꢒꢋꢇ#ꢅ%ꢇꢆ!ꢍꢅꢋꢉꢅꢏꢉꢋ&ꢉ"!ꢃꢋꢄ!ꢅ!ꢍꢆꢇꢇꢅꢄꢋ&ꢅꢈ$ꢌꢈꢈ#ꢅꢓꢁꢎ/ꢅ''ꢅꢏꢈꢉꢅ!ꢃ#ꢈꢁ
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DS39996F-page 388
2010-2011 Microchip Technology Inc.
PIC24FJ128GA310 FAMILY
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
2010-2011 Microchip Technology Inc.
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PIC24FJ128GA310 FAMILY
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
DS39996F-page 390
2010-2011 Microchip Technology Inc.
PIC24FJ128GA310 FAMILY
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
2010-2011 Microchip Technology Inc.
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NOTES:
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2010-2011 Microchip Technology Inc.
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APPENDIX A: REVISION HISTORY
Revision A (March 2010)
Original data sheet for the PIC24FJ128GA310 family of
devices.
Revision B (May 2011)
Changes in Reset values for TRISA in Table 4-12. Edits
to the “Special Microcontroller Features:”
Revision C (July 2011)
Updated the values in Section 32.0 “Electrical
Characteristics”.
Special
Function
Register
addresses have been changed. The OCTRIG1 and
OCTRIG2 pins have been removed. Minor text edits
throughout the document.
Revision D (August 2011)
Updated VBAT specification; updated maximum values
for Section 32.0 “Electrical Characteristics”.
Revision E (October 2011)
• Removed the RTCBAT bit from the CW4<9>
register.
• Added the IDD/IPD numbers in the Section 32.0
“Electrical Characteristics”.
• Added details on the VBAT pin capacitor.
• Added Section 24.3 “A/D Operation with Vbat”.
Revision F (November 2011)
Updated the values in Section 32.0 “Electrical
Characteristics”. Minor text edits throughout the
document.
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NOTES:
DS39996F-page 394
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INDEX
Shared I/O Port Structure......................................... 167
SPI Master, Frame Master Connection .................... 230
SPI Master, Frame Slave Connection ...................... 230
A
A/D
Extended DMA Operations ....................................... 297
Operation .................................................................. 295
Registers................................................................... 298
AC Characteristics
SPI Master/Slave Connection (Enhanced
Buffer Modes)................................................... 229
SPI Master/Slave Connection (Standard Mode)....... 229
SPI Slave, Frame Master Connection ...................... 230
SPI Slave, Frame Slave Connection ........................ 230
SPIx Module (Enhanced Mode)................................ 223
SPIx Module (Standard Mode) ................................. 222
System Clock............................................................ 145
Triple Comparator Module........................................ 315
UART (Simplified)..................................................... 241
Watchdog Timer (WDT)............................................ 344
A/D Conversion Timing............................................. 375
Internal RC Accuracy................................................ 371
Load Conditions and Requirements for
Specifications.................................................... 369
Alternate Interrupt Vector Table (AIVT) .............................. 95
Assembler
MPASM Assembler................................................... 348
B
C
Block Diagrams
C Compilers
MPLAB C18.............................................................. 348
Charge Time Measurement Unit. See CTMU.
10-Bit A/D Converter Analog Input Model................. 311
12-Bit A/D Converter................................................. 296
16-Bit Asynchronous Timer3 and Timer5 ................. 201
16-Bit Synchronous Timer2 and Timer4 ................... 201
16-Bit Timer1 Module................................................ 197
32-Bit Timer2/3 and Timer4/5 ................................... 200
Accessing Program Space Using
Table Operations ................................................ 71
Addressing for Table Registers................................... 83
Buffer Address Generation in PIA Mode................... 299
CALL Stack Frame...................................................... 68
Comparator Voltage Reference ................................ 321
CPU Programmer’s Model.......................................... 37
CRC .......................................................................... 289
CRC Shift Engine Detail............................................ 289
CTMU Connections and Internal Configuration
Code Examples
Basic Sequence for Clock Switching........................ 151
Configuring UART1 Input/Output
Functions (PPS) ............................................... 177
EDS Read From Program Memory in Assembly........ 72
EDS Read in Assembly .............................................. 66
EDS Write in Assembly .............................................. 67
Erasing a Program Memory Block (Assembly)........... 86
Erasing a Program Memory Block (C Language)....... 87
Initiating a Programming Sequence ........................... 87
Loading the Write Buffers........................................... 87
Port Read/Write in Assembly.................................... 172
Port Read/Write in C................................................. 172
PWRSAV Instruction Syntax .................................... 156
Setting the RTCWREN Bit........................................ 276
Single-Word Flash Programming ............................... 88
Single-Word Flash Programming (C Language) ........ 88
Code Protection................................................................ 345
Code Segment Protection ........................................ 345
Configuration Options....................................... 345
Configuration Protection........................................... 346
General Segment Protection .................................... 345
Comparator Voltage Reference........................................ 321
Configuring ............................................................... 321
Configuration Bits ............................................................. 333
Core Features..................................................................... 11
CPU
Arithmetic Logic Unit (ALU) ........................................ 40
Control Registers........................................................ 38
Core Registers............................................................ 36
Programmer’s Model .................................................. 35
CRC
Polynomials .............................................................. 290
Setup Examples for 16 and 32-Bit Polynomials ....... 290
User Interface........................................................... 290
CTMU
Measuring Capacitance............................................ 323
Measuring Time........................................................ 324
Pulse Delay and Generation..................................... 324
Customer Change Notification Service............................. 400
Customer Notification Service .......................................... 400
Customer Support............................................................. 400
for Capacitance Measurement.......................... 324
CTMU Typical Connections and Internal
Configuration for Pulse Delay Generation ........ 325
CTMU Typical Connections and Internal
Configuration for Time Measurement ............... 325
Data Access From Program Space Address
Generation .......................................................... 70
Data Signal Modulator .............................................. 249
DMA............................................................................ 75
EDS Address Generation for Read............................. 66
EDS Address Generation for Write............................. 67
High/Low-Voltage Detect (HLVD) ............................. 331
2
I C Module................................................................ 234
Individual Comparator Configurations,
CREF = 0.......................................................... 316
Individual Comparator Configurations,
CREF = 1 and CVREFP = 0 ............................. 317
Individual Comparator Configurations,
CREF = 1 and CVREFP = 1 ............................. 317
Input Capture ............................................................ 205
LCD Controller .......................................................... 265
On-Chip Regulator Connections............................... 343
Output Compare (16-Bit Mode)................................. 212
Output Compare (Double-Buffered,
16-Bit PWM Mode) ........................................... 214
PCI24FJ256GA310 Family (General)......................... 16
PIC24F CPU Core ...................................................... 36
PSV Operation (Lower Word) ..................................... 73
PSV Operation (Upper Word) ..................................... 73
Reset System.............................................................. 89
RTCC........................................................................ 275
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Equations
D
16-Bit, 32-Bit CRC Polynomials................................ 290
Data Memory
Address Space............................................................43
A/D Conversion Clock Period ................................... 311
Baud Rate Reload Calculation.................................. 235
Calculating the PWM Period..................................... 214
Calculation for Maximum PWM Resolution .............. 215
Relationship Between Device and
Extended Data Space (EDS) ......................................65
Memory Map ...............................................................43
Near Data Space ........................................................44
SFR Space..................................................................44
Software Stack............................................................68
Space Organization, Alignment ..................................44
Data Signal Modulator.......................................................249
Data Signal Modulator (DSM) ...........................................249
DC Characteristics
SPI Clock Speed .............................................. 231
UART Baud Rate with BRGH = 0............................. 242
UART Baud Rate with BRGH = 1............................. 242
Errata.................................................................................. 10
Extended Data Space (EDS)............................................ 253
Comparator ...............................................................368
Comparator Voltage Reference ................................368
CTMU Current Source ..............................................367
I/O Pin Input Specifications.......................................365
I/O Pin Output Specifications....................................366
Idle Current ...............................................................362
Operating Current .....................................................361
Power-Down Current ................................................363
Program Memory ......................................................366
Resets.......................................................................364
Temperature and Voltage Specifications..................361
Vbat Operating Voltage Specifications .....................367
Development Support .......................................................347
Device Features
100-Pin........................................................................15
64-Pin..........................................................................13
80-Pin..........................................................................14
Direct Memory Access Controller. See DMA.
DMA ....................................................................................75
Channel Trigger Sources............................................82
Peripheral Module Disable (PMD) ..............................78
Summary of Operations..............................................76
Types of Transfers......................................................77
Typical Setup ..............................................................78
DMA Controller....................................................................12
F
Flash Configuration Word Locations................................. 333
Flash Configuration Words ................................................. 42
Flash Program Memory ...................................................... 83
and Table Instructions ................................................ 83
Enhanced ICSP Operation ......................................... 84
JTAG Operation.......................................................... 84
Programming Algorithm.............................................. 86
Programming Operations............................................ 84
RTSP Operation ......................................................... 84
Single-Word Programming ......................................... 88
H
High/Low-Voltage Detect (HLVD)..................................... 331
I
I/O Ports
Analog Port Pins Configuration (ANSx).................... 168
Analog/Digital Function of an I/O Pin........................ 168
Input Change Notification ......................................... 172
Open-Drain Configuration......................................... 168
Parallel (PIO) ............................................................ 167
Peripheral Pin Select ................................................ 173
Pull-ups and Pull-Downs........................................... 172
Selectable Input Sources.......................................... 174
2
I C
E
Clock Rates .............................................................. 235
Communicating as Master in Single
Electrical Characteristics
Absolute Maximum Ratings ......................................359
Capacitive Loading on Output Pin ............................369
CLKO and I/O Timing................................................372
External Clock Timing ...............................................370
High/Low-Voltage Detect ..........................................368
Internal Voltage Regulator Specifications.................367
PLL Clock Timing Specifications...............................371
RC Oscillator Start-up Time ......................................371
Reset and Brown-out Reset Requirements ..............373
Thermal Conditions...................................................360
V/F Graph .................................................................360
Enhanced Parallel Master Port (EPMP)............................253
Enhanced Parallel Master Port. See EPMP......................253
EPMP
Master Environment ......................................... 233
Reserved Addresses ................................................ 235
Setting Baud Rate as Bus Master............................. 235
Slave Address Masking ............................................ 235
Input Capture
32-Bit Cascaded Mode ............................................. 206
Operations ................................................................ 206
Synchronous and Trigger Modes.............................. 205
Input Capture with Dedicated Timers ............................... 205
Input Voltage Levels for Port or Pin Tolerated
Description Input....................................................... 168
Instruction Set
Overview................................................................... 353
Summary .................................................................. 351
Symbols Used in Opcode Descriptions .................... 352
Interfacing Program and Data Spaces................................ 69
Key Features.............................................................253
Package Variations...................................................253
2
Inter-Integrated Circuit. See I C. ...................................... 233
Internet Address ............................................................... 400
Interrupt Vector Table (IVT)................................................ 95
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Interrupts
Control and Status Registers...................................... 98
Implemented Vectors.................................................. 97
Power-Saving Features.................................................... 155
Clock Frequency and Clock Switching ..................... 165
Doze Mode ............................................................... 165
Instruction-Based Modes.......................................... 156
Deep Sleep....................................................... 158
Idle.................................................................... 157
Sleep ................................................................ 157
Low-Voltage
Reset Sequence ......................................................... 95
Setup and Service Procedures ................................. 143
Trap Vectors ............................................................... 96
Vector Table................................................................ 96
J
Retention Regulator.......................................... 157
Vbat Mode ................................................................ 160
Product Identification System ........................................... 402
Program Memory
JTAG Interface.................................................................. 346
K
Key Features..................................................................... 333
Access Using Table Instructions ................................ 71
Address Construction ................................................. 69
Address Space ........................................................... 41
Flash Configuration Words......................................... 42
Hard Memory Vectors................................................. 42
Memory Maps............................................................. 41
Organization ............................................................... 42
Reading From Program Memory Using EDS ............. 72
Program Verification ......................................................... 345
Pulse-Width Modulation (PWM) Mode.............................. 213
Pulse-Width Modulation. See PWM.
L
LCD Controller .................................................................... 12
Liquid Crystal Display (LCD) Controller ............................ 265
M
Memory Organization.......................................................... 41
Microchip Internet Web Site.............................................. 400
Modulator. See Data Signal Modulator. ............................ 249
MPLAB ASM30 Assembler, Linker, Librarian ................... 348
MPLAB Integrated Development
Environment Software............................................... 347
MPLAB PM3 Device Programmer .................................... 350
MPLAB REAL ICE In-Circuit Emulator System................. 349
MPLINK Object Linker/MPLIB Object Librarian ................ 348
PWM
Duty Cycle and Period.............................................. 214
R
Reader Response............................................................. 401
Real-Time Clock and Calendar (RTCC) ........................... 275
Register Maps
N
Near Data Space ................................................................ 44
A/D Converter............................................................. 56
Analog Configuration.................................................. 57
Comparators............................................................... 61
CPU Core ................................................................... 45
CRC............................................................................ 62
CTMU ......................................................................... 57
Data Signal Modulator (DSM)..................................... 61
Deep Sleep................................................................. 64
DMA............................................................................ 58
O
On-Chip Voltage Regulator............................................... 343
POR .......................................................................... 343
Standby Mode........................................................... 343
Oscillator Configuration
Bit Values for Clock Selection................................... 146
Clock Switching......................................................... 150
Sequence.......................................................... 151
Control Registers ...................................................... 147
CPU Clocking Scheme ............................................. 146
Initial Configuration on POR ..................................... 146
Reference Clock Output............................................ 152
Secondary Oscillator (SOSC) ................................... 152
Output Compare
2
I C .............................................................................. 51
ICN ............................................................................. 46
Input Capture.............................................................. 49
Interrupt Controller...................................................... 47
LCD Controller............................................................ 59
NVM............................................................................ 64
Output Compare......................................................... 50
Pad Configuration....................................................... 55
Parallel Master/Slave Port.......................................... 60
Peripheral Pin Select.................................................. 62
PMD............................................................................ 64
PORTA ....................................................................... 53
PORTB ....................................................................... 53
PORTC....................................................................... 54
PORTD....................................................................... 54
PORTE ....................................................................... 54
PORTF ....................................................................... 55
PORTG....................................................................... 55
RTCC.......................................................................... 61
SPI.............................................................................. 53
System Control........................................................... 63
Timers......................................................................... 48
UART.......................................................................... 52
32-Bit Cascaded Mode ............................................. 211
Synchronous and Trigger Modes.............................. 211
Output Compare with Dedicated Timers........................... 211
P
Packaging ......................................................................... 377
Details....................................................................... 379
Marking ..................................................................... 377
Peripheral Pin Select (PPS).............................................. 173
Available Peripherals and Pins ................................. 173
Configuration Control................................................ 176
Considerations for Use ............................................. 177
Input Mapping ........................................................... 174
Mapping Exceptions.................................................. 176
Output Mapping ........................................................ 175
Peripheral Priority ..................................................... 173
Registers................................................................... 178
Pin Descriptions
121-Pin Devices (BGA)................................................. 7
Pinout Descriptions ............................................................. 17
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Registers
AD1CHITH (A/D Scan Compare Hit, High Word) .....308
IFS2 (Interrupt Flag Status 2)................................... 107
IFS3 (Interrupt Flag Status 3)................................... 108
IFS4 (Interrupt Flag Status 4)................................... 109
IFS5 (Interrupt Flag Status 5)................................... 110
IFS6 (Interrupt Flag Status 6)................................... 111
IFS7 (Interrupt Flag Status 7)................................... 111
INTCON1 (Interrupt Control 1).................................. 101
INTCON2 (Interrupt Control 2).................................. 102
INTTREG (Interrupt Controller Test)......................... 142
IPC0 (Interrupt Priority Control 0)............................. 121
IPC1 (Interrupt Priority Control 1)............................. 122
IPC10 (Interrupt Priority Control 10) ......................... 131
IPC11 (Interrupt Priority Control 11) ......................... 132
IPC12 (Interrupt Priority Control 12) ......................... 133
IPC13 (Interrupt Priority Control 13) ......................... 134
IPC15 (Interrupt Priority Control 15) ......................... 135
IPC16 (Interrupt Priority Control 16) ......................... 136
IPC18 (Interrupt Priority Control 18) ......................... 137
IPC19 (Interrupt Priority Control 19) ......................... 137
IPC2 (Interrupt Priority Control 2)............................. 123
IPC20 (Interrupt Priority Control 20) ......................... 138
IPC21 (Interrupt Priority Control 21) ......................... 139
IPC22 (Interrupt Priority Control 22) ......................... 140
IPC25 (Interrupt Priority Control 25) ......................... 141
IPC29 (Interrupt Priority Control 29) ......................... 141
IPC3 (Interrupt Priority Control 3)............................. 124
IPC4 (Interrupt Priority Control 4)............................. 125
IPC5 (Interrupt Priority Control 5)............................. 126
IPC6 (Interrupt Priority Control 6)............................. 127
IPC7 (Interrupt Priority Control 7)............................. 128
IPC8 (Interrupt Priority Control 8)............................. 129
IPC9 (Interrupt Priority Control 9)............................. 130
LCDCON (LCD Control) ........................................... 266
LCDCREG (LCD Charge Pump Control).................. 268
LCDDATAx (LCD Pixel Data x) ................................ 270
LCDPS (LCD Phase)................................................ 269
LCDREF (LCD Reference Ladder Control) .............. 272
LCDSEx (LCD Segment x Enable)........................... 270
MDCAR (Modulator Carrier Control)......................... 252
MDCON (Modulator Control) .................................... 250
MDSRC (Modulator Source Control) ........................ 251
MINSEC (RTCC Minutes and Seconds Value)......... 282
MTHDY (RTCC Month and Day Value).................... 281
OCxCON1 (Output Compare x Control 1) ................ 216
OCxCON2 (Output Compare x Control 2) ................ 218
OSCCON (Oscillator Control)................................... 147
OSCTUN (FRC Oscillator Tune)............................... 150
PADCFG1 (Pad Configuration Control).................... 263
PMCON1 (EPMP Control 1) ..................................... 255
PMCON2 (EPMP Control 2) ..................................... 256
PMCON3 (EPMP Control 3) ..................................... 257
PMCON4 (EPMP Control 4) ..................................... 258
PMCSxBS (Chip Select x Base Address)................. 260
PMCSxCF (Chip Select x Configuration).................. 259
PMCSxMD (Chip Select x Mode) ............................. 261
PMSTAT (EPMP Status, Slave Mode) ..................... 262
RCFGCAL (RTCC Calibration and Configuration).... 277
RCON (Reset Control)................................................ 90
RCON2 (Reset and System Control 2)..................... 164
RCON2 (Reset Control 2)........................................... 92
REFOCON (Reference Oscillator Control) ............... 153
RPINR0 (PPS Input 0).............................................. 178
RPINR1 (PPS Input 1).............................................. 178
RPINR10 (PPS Input 10).......................................... 182
RPINR11 (PPS Input 11).......................................... 182
AD1CHITL (A/D Scan Compare Hit, Low Word).......308
AD1CHS (A/D Sample Select)..................................306
AD1CON1 (A/D Control 1)........................................300
AD1CON2 (A/D Control 2)........................................302
AD1CON3 (A/D Control 3)........................................303
AD1CON4 (A/D Control 4)........................................304
AD1CON5 (A/D Control 5)........................................305
AD1CSSH (A/D Input Scan Select, High Word) .......309
AD1CSSL (A/D Input Scan Select, Low Word).........309
AD1CTMENH (CTMU Enable, High Word)...............310
AD1CTMENL (CTMU Enable, Low Word) ................310
ALCFGRPT (Alarm Configuration)............................280
ALMINSEC (Alarm Minutes and Seconds Value) .....284
ALMTHDY (Alarm Month and Day Value) ................283
ALWDHR (Alarm Weekday and Hours Value)..........283
ANCFG (A/D Band Gap Reference) .........................307
ANSA (PORTA Analog Function Selection)..............169
ANSB (PORTB Analog Function Selection)..............169
ANSC (PORTC Analog Function Selection) .............170
ANSD (PORTD Analog Function Selection) .............170
ANSE (PORTE Analog Function Selection)..............171
ANSG (PORTG Analog Function Selection).............171
CLKDIV (Clock Divider) ............................................149
CMSTAT (Comparator Status)..................................319
CMxCON (Comparator x Control,
Comparators 1-3)..............................................318
CORCON (CPU Core Control)............................ 39, 100
CRCCON1 (CRC Control 1) .....................................292
CRCCON2 (CRC Control 2) .....................................293
CRCXORH (CRC XOR High) ...................................294
CRCXORL (CRC XOR Polynomial, Low Byte) .........293
CTMUCON1 (CTMU Control 1) ................................326
CTMUCON2 (CTMU Control 2) ................................327
CTMUICON (CTMU Current Control) .......................329
CVRCON (Comparator Voltage
Reference Control)............................................322
CW1 (Flash Configuration Word 1)...........................334
CW2 (Flash Configuration Word 2)...........................336
CW3 (Flash Configuration Word 3)...........................338
CW4 (Flash Configuration Word 4)...........................340
DEVID (Device ID)....................................................342
DEVREV (Device Revision)......................................342
DMACHn (DMA Channel n Control) ...........................80
DMACON (DMA Engine Control)................................79
DMAINTn (DMA Channel n Interrupt) .........................81
DSCON (Deep Sleep Control) ..................................162
DSWAKE (Deep Sleep Wake-up Source) ................163
HLVDCON (High/Low-Voltage Detect Control).........332
I2CxCON (I2Cx Control) ...........................................236
I2CxMSK (I2Cx Slave Mode Address Mask) ............239
I2CxSTAT (I2Cx Status) ...........................................238
ICxCON1 (Input Capture x Control 1) .......................207
ICxCON2 (Input Capture x Control 2) .......................208
IEC0 (Interrupt Enable Control 0) .............................112
IEC1 (Interrupt Enable Control 1) .............................114
IEC2 (Interrupt Enable Control 2) .............................116
IEC3 (Interrupt Enable Control 3) .............................117
IEC4 (Interrupt Enable Control 4) .............................118
IEC5 (Interrupt Enable Control 5) .............................119
IEC6 (Interrupt Enable Control 6) .............................120
IEC7 (Interrupt Enable Control 7) .............................120
IFS0 (Interrupt Flag Status 0) ...................................103
IFS1 (Interrupt Flag Status 1) ...................................105
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RPINR17 (PPS Input 17) .......................................... 183
Revision History................................................................ 393
RTCC
RPINR18 (PPS Input 18) .......................................... 183
RPINR19 (PPS Input 19) .......................................... 184
RPINR2 (PPS Input 2) .............................................. 179
RPINR20 (PPS Input 20) .......................................... 184
RPINR21 (PPS Input 21) .......................................... 185
RPINR22 (PPS Input 22) .......................................... 185
RPINR23 (PPS Input 23) .......................................... 186
RPINR27 (PPS Input 27) .......................................... 186
RPINR3 (PPS Input 3) .............................................. 179
RPINR30 (PPS Input 30) .......................................... 187
RPINR31 (PPS Input 31) .......................................... 187
RPINR4 (PPS Input 4) .............................................. 180
RPINR7 (PPS Input 7) .............................................. 180
RPINR8 (PPS Input 8) .............................................. 181
RPINR9 (PPS Input 9) .............................................. 181
RPOR0 (PPS Output 0) ............................................ 188
RPOR1 (PPS Output 1) ............................................ 188
RPOR10 (PPS Output 10) ........................................ 193
RPOR11 (PPS Output 11) ........................................ 193
RPOR12 (PPS Output 12) ........................................ 194
RPOR13 (PPS Output 13) ........................................ 194
RPOR14 (PPS Output 14) ........................................ 195
RPOR15 (PPS Output 15) ........................................ 195
RPOR2 (PPS Output 2) ............................................ 189
RPOR3 (PPS Output 3) ............................................ 189
RPOR4 (PPS Output 4) ............................................ 190
RPOR5 (PPS Output 5) ............................................ 190
RPOR6 (PPS Output 6) ............................................ 191
RPOR7 (PPS Output 7) ............................................ 191
RPOR8 (PPS Output 8) ............................................ 192
RPOR9 (PPS Output 9) ............................................ 192
RTCCSWT (Power Control and Sample
Window Timer).................................................. 285
RTCPWC (RTCC Power Control)............................. 279
SPIxCON1 (SPIx Control 1)...................................... 226
SPIxCON2 (SPIx Control 2)...................................... 228
SPIxSTAT (SPIx Status and Control) ....................... 224
SR (ALU STATUS) ............................................... 38, 99
T1CON (Timer1 Control)........................................... 198
TxCON (Timer2 and Timer4 Control)........................ 202
TyCON (Timer3 and Timer5 Control)........................ 203
UxMODE (UARTx Mode).......................................... 244
UxSTA (UARTx Status and Control)......................... 246
WKDYHR (RTCC Weekday and Hours Value)......... 282
YEAR (RTCC Year Value)........................................ 281
Alarm Configuration.................................................. 286
Alarm Mask Settings (figure) .................................... 287
Calibration ................................................................ 286
Clock Source Selection ............................................ 276
Power Control........................................................... 287
Register Mapping ..................................................... 276
Source Clock ............................................................ 275
Write Lock................................................................. 276
S
Selective Peripheral Power Control.................................. 165
Serial Peripheral Interface (SPI)....................................... 221
Serial Peripheral Interface. See SPI.
SFR Space ......................................................................... 44
Software Simulator (MPLAB SIM) .................................... 349
Software Stack ................................................................... 68
Special Features................................................................. 12
SPI.................................................................................... 221
T
Timer1 .............................................................................. 197
Timer2/3 and Timer4/5 ..................................................... 199
Timing Diagrams
CLKO and I/O Timing ............................................... 372
External Clock .......................................................... 370
Triple Comparator............................................................. 315
Triple Comparator Module................................................ 315
U
UART................................................................................ 241
Baud Rate Generator (BRG) .................................... 242
Infrared Support........................................................ 243
Operation of UxCTS and UxRTS Pins...................... 243
Receiving
8-Bit or 9-Bit Data Mode................................... 243
Transmitting
8-Bit Data Mode................................................ 243
9-Bit Data Mode................................................ 243
Break and Sync Sequence............................... 243
Universal Asynchronous Receiver Transmitter. See UART.
W
Watchdog Timer (WDT).................................................... 344
Control Register........................................................ 344
Windowed Operation................................................ 344
WWW Address ................................................................. 400
WWW, On-Line Support ..................................................... 10
Resets
BOR (Brown-out Reset).............................................. 89
Brown-out Reset (BOR).............................................. 93
Clock Source Selection............................................... 93
CM (Configuration Mismatch Reset)........................... 89
Delay Times................................................................ 94
Device Times .............................................................. 93
IOPUWR (Illegal Opcode Reset) ................................ 89
MCLR (Pin Reset)....................................................... 89
POR (Power-on Reset)............................................... 89
RCON Flags, Operation.............................................. 93
SFR States.................................................................. 93
SWR (RESET Instruction)........................................... 89
TRAPR (Trap Conflict Reset)...................................... 89
UWR (Uninitialized W Register Reset) ....................... 89
WDT (Watchdog Timer Reset).................................... 89
2010-2011 Microchip Technology Inc.
DS39996F-page 399
PIC24FJ128GA310 FAMILY
NOTES:
DS39996F-page 400
2010-2011 Microchip Technology Inc.
PIC24FJ128GA310 FAMILY
THE MICROCHIP WEB SITE
CUSTOMER SUPPORT
Microchip provides online support via our WWW site at
www.microchip.com. This web site is used as a means
to make files and information easily available to
customers. Accessible by using your favorite Internet
browser, the web site contains the following
information:
Users of Microchip products can receive assistance
through several channels:
• Distributor or Representative
• Local Sales Office
• Field Application Engineer (FAE)
• Technical Support
• Product Support – Data sheets and errata,
application notes and sample programs, design
resources, user’s guides and hardware support
documents, latest software releases and archived
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• Development Systems Information Line
Customers
should
contact
their
distributor,
representative or field application engineer (FAE) for
support. Local sales offices are also available to help
customers. A listing of sales offices and locations is
included in the back of this document.
• General Technical Support – Frequently Asked
Questions (FAQ), technical support requests,
online discussion groups, Microchip consultant
program member listing
Technical support is available through the web site
at: http://microchip.com/support
• Business of Microchip – Product selector and
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CUSTOMER CHANGE NOTIFICATION
SERVICE
Microchip’s customer notification service helps keep
customers current on Microchip products. Subscribers
will receive e-mail notification whenever there are
changes, updates, revisions or errata related to a
specified product family or development tool of interest.
To register, access the Microchip web site at
www.microchip.com. Under “Support”, click on
“Customer Change Notification” and follow the
registration instructions.
2010-2011 Microchip Technology Inc.
DS39996F-page 401
PIC24FJ128GA310 FAMILY
READER RESPONSE
It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip
product. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our
documentation can better serve you, please FAX your comments to the Technical Publications Manager at
(480) 792-4150.
Please list the following information, and use this outline to provide us with your comments about this document.
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RE:
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Telephone: (_______) _________ - _________
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Literature Number: DS39996E
Application (optional):
Would you like a reply?
Y
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Device: PIC24FJ128GA310 Family
Questions:
1. What are the best features of this document?
2. How does this document meet your hardware and software development needs?
3. Do you find the organization of this document easy to follow? If not, why?
4. What additions to the document do you think would enhance the structure and subject?
5. What deletions from the document could be made without affecting the overall usefulness?
6. Is there any incorrect or misleading information (what and where)?
7. How would you improve this document?
DS39996F-page 402
2010-2011 Microchip Technology Inc.
PIC24FJ128GA310 FAMILY
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
Examples:
PIC 24 FJ 128 GA3 10 T - I / PT - XXX
a)
b)
PIC24FJ64GA306-I/MR:
PIC24F device with LCD Controller and nano-
Watt XLP Technology, 64 KB program memory,
64-pin, Industrial temp., QFN package.
Microchip Trademark
Architecture
Flash Memory Family
PIC24FJ128GA308-I/PT:
PIC24F device with LCD Controller and nano-
Watt XLP Technology, 128 KB program
memory, 80-pin, Industrial temp., TQFP
package.
Program Memory Size (KB)
Product Group
Pin Count
Tape and Reel Flag (if applicable)
Temperature Range
Package
c)
PIC24FJ128GA210-I/BG:
PIC24F device with LCD Controller and nano-
Watt XLP Technology, 128 KB program
memory, 121-pin, Industrial temp., BGA
package.
Pattern
Architecture
24 = 16-bit modified Harvard without DSP
Flash Memory Family FJ = Flash program memory
Product Group
Pin Count
GA3 = General-purpose microcontrollers with
LCD Controller and nanoWatt XLP Technology
06 = 64-pin
08 = 80-pin
10 = 100-pin (TQFP) and 121-pin (BGA)
Temperature Range
Package
I
= -40C to +85C (Industrial)
BG = 121-pin (10x10x1.4 mm) BGA package
PT = 100-lead (12x12x1 mm) TQFP (Thin Quad Flatpack)
PF = 100-lead (14x14x1 mm) TQFP (Thin Quad Flatpack)
PT = 80-pin (12x12x1 mm) TQFP (Thin Quad Flatpack)
PT = 64-lead (10x10x1 mm) TQFP (Thin Quad Flatpack)
MR = 64-lead (9x9x0.9 mm) QFN (Quad Flatpack, No Lead)
Pattern
Three-digit QTP, SQTP, Code or Special Requirements
(blank otherwise)
ES = Engineering Sample
2010-2011 Microchip Technology Inc.
DS39996F-page 403
PIC24FJ128GA310 FAMILY
NOTES:
DS39996F-page 404
2010-2011 Microchip Technology Inc.
Note the following details of the code protection feature on Microchip devices:
•
Microchip products meet the specification contained in their particular Microchip Data Sheet.
•
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
•
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
•
•
Microchip is willing to work with the customer who is concerned about the integrity of their code.
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION,
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
QUALITY, PERFORMANCE, MERCHANTABILITY OR
FITNESS FOR PURPOSE. Microchip disclaims all liability
arising from this information and its use. Use of Microchip
devices in life support and/or safety applications is entirely at
the buyer’s risk, and the buyer agrees to defend, indemnify and
hold harmless Microchip from any and all damages, claims,
suits, or expenses resulting from such use. No licenses are
conveyed, implicitly or otherwise, under any Microchip
intellectual property rights.
Trademarks
The Microchip name and logo, the Microchip logo, dsPIC,
KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART,
32
PIC logo, rfPIC and UNI/O are registered trademarks of
Microchip Technology Incorporated in the U.S.A. and other
countries.
FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor,
MXDEV, MXLAB, SEEVAL and The Embedded Control
Solutions Company are registered trademarks of Microchip
Technology Incorporated in the U.S.A.
Analog-for-the-Digital Age, Application Maestro, chipKIT,
chipKIT logo, CodeGuard, dsPICDEM, dsPICDEM.net,
dsPICworks, dsSPEAK, ECAN, ECONOMONITOR,
FanSense, HI-TIDE, In-Circuit Serial Programming, ICSP,
Mindi, MiWi, MPASM, MPLAB Certified logo, MPLIB,
MPLINK, mTouch, Omniscient Code Generation, PICC,
PICC-18, PICDEM, PICDEM.net, PICkit, PICtail, REAL ICE,
rfLAB, Select Mode, Total Endurance, TSHARC,
UniWinDriver, WiperLock and ZENA are trademarks of
Microchip Technology Incorporated in the U.S.A. and other
countries.
SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.
All other trademarks mentioned herein are property of their
respective companies.
© 2010-2011, Microchip Technology Incorporated, Printed in
the U.S.A., All Rights Reserved.
Printed on recycled paper.
ISBN: 978-1-61341-759-1
Microchip received ISO/TS-16949:2009 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
2010-2011 Microchip Technology Inc.
DS39996F-page 405
Worldwide Sales and Service
AMERICAS
ASIA/PACIFIC
ASIA/PACIFIC
EUROPE
Corporate Office
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Technical Support:
http://www.microchip.com/
support
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Los Angeles
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Thailand - Bangkok
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Fax: 66-2-694-1350
Santa Clara
Santa Clara, CA
Tel: 408-961-6444
Fax: 408-961-6445
China - Xian
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Fax: 86-29-8833-7256
Toronto
Mississauga, Ontario,
Canada
China - Xiamen
Tel: 905-673-0699
Fax: 905-673-6509
Tel: 86-592-2388138
Fax: 86-592-2388130
China - Zhuhai
Tel: 86-756-3210040
Fax: 86-756-3210049
08/02/11
DS39996F-page 406
2010-2011 Microchip Technology Inc.
相关型号：
PIC24FJ128GA310
64/80/100-Pin, General Purpose, 16-Bit Flash Microcontrollers with LCD Controller and nanoWatt XLP Technology
MICROCHIP
PIC24FJ128GB106-I/PT
16-BIT, FLASH, 32 MHz, MICROCONTROLLER, PQFP64, 10 X 10 MM, 1 MM HEIGHT, LEAD FREE, PLASTIC, TQFP-64
MICROCHIP
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