PIC24FJ192GA106_技术文档

PIC24FJ256GA110 FAMILY

PIC24FJ256GA110 Family

Silicon Errata and Data Sheet Clarification

The PIC24FJ256GA110 family devices that you have

For example, to identify the silicon revision level using

MPLAB IDE in conjunction with MPLAB ICD 2 or

PICkit™ 3:

received conform functionally to the current Device Data

Sheet (DS39905E), except for the anomalies described

in this document.

1. Using the appropriate interface, connect the

The silicon issues discussed in the following pages are

for silicon revisions with the Device and Revision IDs

listed in Table 1. The silicon issues are summarized in

Table 2.

device

to

the

MPLAB

ICD

2

programmer/debugger or PICkit™ 3.

2. From the main menu in MPLAB IDE, select

Configure>Select Device, and then select the

target part number in the dialog box.

The errata described in this document will be addressed

in future revisions of the PIC24FJ256GA110 family

silicon.

3. Select

the

MPLAB

hardware

tool

(Debugger>Select Tool).

4. Perform a “Connect” operation to the device

(Debugger>Connect). Depending on the devel-

opment tool used, the part number and Device

Revision ID value appear in the Output window.

Note:

This document summarizes all silicon

errata issues from all revisions of silicon,

previous as well as current. Only the

issues indicated in the last column of

Table 2 apply to the current silicon

revision (A6).

Note:

If you are unable to extract the silicon

revision level, please contact your local

Microchip sales office for assistance.

Data Sheet clarifications and corrections start on page 12,

following the discussion of silicon issues.

The

DEVREV

values

for

the

various

The silicon revision level can be identified using the

current version of MPLAB^®IDE and Microchip’s

programmers, debuggers, and emulation tools, which

are available at the Microchip corporate web site

(www.microchip.com).

PIC24FJ256GA110 family silicon revisions are

shown in Table 1.

TABLE 1:

SILICON DEVREV VALUES

Revision ID for

Silicon Revision⁽²⁾

Revision ID for

Silicon Revision⁽²⁾

Device

ID⁽¹⁾

Part Number

ID⁽¹⁾

A3

A5

A6

A3

A5

A6

PIC24FJ256GA110

PIC24FJ192GA110

PIC24FJ128GA110

PIC24FJ64GA110

PIC24FJ256GA108

PIC24FJ192GA108

101Eh

1016h

100Eh

1006h

101Ah

1012h

PIC24FJ128GA108

PIC24FJ64GA108

PIC24FJ256GA106

PIC24FJ192GA106

PIC24FJ128GA106

PIC24FJ64GA106

100Ah

1002h

1018h

1010h

1008h

1000h

01h

03h

04h

01h

03h

04h

Note 1: The Device IDs (DEVID and DEVREV) are located at the last two implemented addresses of configuration

memory space. They are shown in hexadecimal in the format “DEVID DEVREV”.

2: Refer to the “PIC24FJXXXGA0XX Flash Programming Specification” (DS39768) for detailed information

on Device and Revision IDs for your specific device.

 2008-2013 Microchip Technology Inc.

DS80368N-page 1

PIC24FJ256GA110 FAMILY

TABLE 2:

Module

SILICON ISSUE SUMMARY

Affected Revisions⁽¹⁾

Item

Feature

Issue Summary

Number

A3

A5

A6

Core

JTAG

RAM Operation

BOR

1.

2.

3.

RAM issues in Doze mode.

X

BOR issues in enabled on-chip regulator.

JTAG issues in device programming.

Device 

X

Programming

UART

I/O

—

4.

5.

Framing errors in UART.

X

PORTB

RB5 issues in open-drain operation.

Early one-half clock cycles.

SPI

Master mode

—

6.

CTMU

UART

SPI

7.

CTMU issues as a trigger source.

UART error interrupt issue.

UERIF Interrupt

FIFO Error Flags

8.

9.

Error bits settings for receive FIFO.

Errors in enhanced buffer interrupts.

Enhanced Buffer

modes

10.

UART

IrDA^®

11.

12.

Issues in 8-bit mode using IrDA^®endec.

X

IrDA

Framing errors in 8-bit mode using IrDA

endec.

UART

Core

IrDA

13.

14.

15.

16.

17.

18.

19.

Transmission errors in 9-bit mode using IrDA

endec.

X

Instruction Set

Read-After-Write stall conditions inside a

REPEATloop.

X

Memory

ICSP™

RTCC

Program Space 

Visibility

False error trap conditions when accessing

data in the PSV.

—

Inability of the ICSP/ICD port pair to read or

program.

Unexpected decrementing of the Alarm

Repeat Counter.

I²C™

Module

I²C™

Module

Master mode

Slave mode

—

Acknowledgement issues in addressing slave

device.

Acknowledgement issues in Slave mode.

A/D Converter

SPI

20.

21.

Debugging issues on 64-pin devices.

X

Enhanced Buffer

mode

FIFO transfer issues in Enhanced Master

mode.

Core

Code Protection

22.

Applications unable to write when General

Segment Code Protection has been enabled.

X

SPI/PPS

Oscillator

—

23.

24.

ALTRP/ASCK1 functionality is not supported.

X

LPRC

Issues with LPRC automatic restart following

BOR.

CTMU

A/D Trigger

25.

26.

27.

28.

Issues in the CTMU in triggering automatic

A/D conversion.

X

Output 

Compare

—

INTx

Single missed compare events under certain

conditions.

Interrupts

External interrupts missed when writing to

INTCON2.

X

A/D Converter

—

Module continues to draw current when

disabled.

Note 1: Only those issues indicated in the last column apply to the current silicon revision.

DS80368N-page 2

 2008-2013 Microchip Technology Inc.

PIC24FJ256GA110 FAMILY

TABLE 2:

Module

SILICON ISSUE SUMMARY (CONTINUED)

Affected Revisions⁽¹⁾

Item

Feature

Issue Summary

Number

A3

A5

A6

CTMU

—

29.

30.

Disabling module affects band gap.

X

Oscillator

POSCEN bit does not work with 

Primary + PLL modes.

Output 

Compare

Interrupt

31.

32.

33.

Interrupt flag may precede the output pin

change under certain circumstances.

X

UART

Transmit

A TX interrupt may occur before the data

transmission is complete.

Oscillator

Two-Speed

Start-up

This feature is not functional.

Note 1: Only those issues indicated in the last column apply to the current silicon revision.

 2008-2013 Microchip Technology Inc.

DS80368N-page 3

PIC24FJ256GA110 FAMILY

3. Module: JTAG (Device Programming)

Silicon Errata Issues

The JTAGEN Configuration bit can be pro-

grammed to ‘0’ while using the JTAG interface for

device programming. This may cause a situation

where JTAG programming can lock itself out of

being able to program the device.

Note:

This document summarizes all silicon

errata issues from all revisions of silicon,

previous as well as current. Only the

issues indicated by the shaded column in

the following tables apply to the current

silicon revision (A5).

Work around

None.

1. Module: Core (RAM Operation)

Affected Silicon Revisions

A3 A5 A6

If a RAM read is performed on the instruction

immediately prior to enabling Doze mode, an extra

read event may occur when Doze mode is

enabled. This has no effect on most SFRs and on

user RAM space. However, this could cause regis-

ters which also perform some action on a read

(such as auto-incrementing a pointer or removing

data from a FIFO buffer) to repeat that action,

possibly resulting in lost data or unexpected

operation.

X

4

Module: UART

When the UART is operating using two Stop bits

(STSEL = 1), it may sample the first Stop bit

instead of the second one. If the device being com-

municated with is one using one Stop bit in its

communications, this may lead to framing errors.

Work around

Avoid reading registers which perform a second-

ary action (e.g., UART and SPI FIFO buffers, and

the RTCVAL registers) immediately prior to

entering Doze mode.

None.

Affected Silicon Revisions

If this cannot be avoided, execute a NOP

instruction before entering Doze mode.

A3 A5 A6

X

Affected Silicon Revisions

A3 A5 A6

5. Module: I/O (PORTB)

When RB5 is configured as an open-drain output,

it remains in a high-impedance state. The settings

of LATB5 and TRISB5 have no effect on the pin’s

state.

X

2. Module: Core (BOR)

When the on-chip regulator is enabled (ENVREG

tied to VDD), a BOR event may spontaneously

occur under the following circumstances:

Work around

If open-drain operation is not required, configure

RB5 as a regular I/O (ODCB<5> = 0).

• VDD is less than 2.5V, and either:

If open-drain operation is required, there are two

options:

• the internal band gap reference is being used as

a reference with the A/D Converter

(AD1PCFGH<1> or <0> = 0) or comparators

(CMxCON<1:0> = 11); or

• select a different I/O pin for the open-drain

function; or

• the CTMU module is enabled.

• place an external transistor on the pin, and

configure the pin as a regular I/O.

Work around

Affected Silicon Revisions

Limit the following activities to only those times

when the on-chip regulator is not in Tracking mode

(LVDIF (IFS4<8>) = 0):

A3 A5 A6

X

• enabling the CTMU module;

• selecting the internal band gap as a reference

for the A/D Converter or the comparators.

Affected Silicon Revisions

A3 A5 A6

X

DS80368N-page 4

 2008-2013 Microchip Technology Inc.

PIC24FJ256GA110 FAMILY

6. Module: SPIx (Master Mode)

7. Module: CTMU

In Master mode, both the SPIx Interrupt Flag

(SPIxIF) and the SPIRBF bit (SPIxSTAT<0>) may

become set one-half clock cycle early, instead of

on the clock edge. This occurs only under the

following circumstances:

When the CTMU module is selected as the trigger

source (SYNCSEL<4:0> = 11000), the input

capture and/or output compare trigger may not

work.

Work around

• Enhanced Buffer mode is disabled 

(SPIBEN = 0); and

Manually trigger the input capture and/or output

compare module(s) after a CTMU event is

received. Be certain to compensate for any time

latency that results from manually triggering the

module.

• the module is configured for serial data output

changes on transition from clock active to clock

Idle state (CKE = 1)

If the application is using the interrupt flag to deter-

mine when data to be transmitted is written to the

transmit buffer, the data currently in the buffer may

be overwritten.

Affected Silicon Revisions

A3 A5 A6

X

Work around

Before writing to the SPIx buffer, check the SCKx pin

to determine if the last clock edge has passed.

Example 1 (below) demonstrates a method for

doing this. In this example, pin RD1 functions as the

SPIx clock, SCKx, which is configured as Idle low.

Affected Silicon Revisions

A3 A5 A6

X

EXAMPLE 1:

CHECKING THE STATE OF SPIxIF AGAINST THE SPIx CLOCK

while(IFS0bits.SPI1IF == 0){}

while(PORTDbits.RD1 == 1){}

SPI1BUF = 0xFF;

//wait for the transmission to complete

//wait for the last clock to finish

//write new data to the buffer

 2008-2013 Microchip Technology Inc.

DS80368N-page 5

PIC24FJ256GA110 FAMILY

8. Module: UART (UxERIF Interrupt)

11. Module: UART (IrDA^®)

The UART error interrupt may not occur, or occur

at an incorrect time, if multiple errors occur during

a short period of time.

When the UART is operating in 8-bit mode

(PDSEL<1:0> = 0x) and using the IrDA endec

(IREN = 1), the module incorrectly transmits a

data payload of 80h as 00h.

Work around

Work around:

Read the error flags in the UxSTA register when-

ever a byte is received to verify the error status. In

most cases, these bits will be correct, even if the

UART error interrupt fails to occur. For possible

exceptions, refer to Errata # 9.

None.

Affected Silicon Revisions

A3 A5 A6

Affected Silicon Revisions

X

A3 A5 A6

12. Module: UART (IrDA)

X

When the UART is operating in 8-bit mode

(PDSEL<1:0> = 0x) and using the IrDA endec

(IREN = 1), a framing error may occur when

transmitting a data payload of 00h.

9. Module: UART (FIFO Error Flags)

Under certain circumstances, the PERR and

FERR error bits may not be correct for all bytes in

the receive FIFO. This has only been observed

when both of the following conditions are met:

Work around:

None.

• the UART receive interrupt is set to occur when

the FIFO is full or ¾ full 

(UxSTA<7:6> = 1x), and

Affected Silicon Revisions

A3 A5 A6

• more than 2 bytes with an error are received.

X

In these cases, only the first two bytes with a parity

or framing error will have the corresponding bits

indicate correctly. The error bits will not be set after

this.

13. Module: UART (IrDA)

When the UART is operating in 9-bit mode

(PDSEL<1:0> = 1x) and using the IrDA endec

(IREN = 1), the module will incorrectly transmit

10 bits when transmitting data payloads of 00h or

80h.

Work around

None.

Affected Silicon Revisions

Work around:

A3 A5 A6

None.

X

Affected Silicon Revisions

A3 A5 A6

10. Module: SPIx (Enhanced Buffer Modes)

X

If the SPIx event interrupt is configured to occur

when the enhanced FIFO buffer is full

(SISEL<2:0> = 111), the interrupt may actually

occur when the 7th byte is written to the buffer,

instead of the 8th byte. The other enhanced buffer

interrupts function as previously described.

Work around

Do not use the Full Buffer Interrupt mode. The

SPITBF bit (SPIxSTAT<1>) reliably indicates when

the enhanced FIFO buffer is full, and can be polled

instead of using the Full Buffer Interrupt mode.

Affected Silicon Revisions

A3 A5 A6

X

DS80368N-page 6

 2008-2013 Microchip Technology Inc.

PIC24FJ256GA110 FAMILY

14. Module: Core (Instruction Set)

16. Module: ICSP™

If an instruction producing a read-after-write stall

condition is executed inside a REPEAT loop, the

instruction will be executed fewer times than was

intended. For example, this loop:

The ICSP/ICD port pair, PGEC3/PGED3 (RB5/RB4),

cannot be used to read or program the device.

Work around

Use either PGEC2/PGED2 or PGEC1/PGED1.

repeat #0xf

Affected Silicon Revisions

inc [w1],[++w1]

will execute less than 15 times.

A3 A5 A6

Work around

X

Avoid using REPEAT to repetitively execute

instructions that create a stall condition. Instead,

use a software loop using conditional branches.

The MPLAB^®C Compiler will not generate

REPEATloops that cause this erratum.

17. Module: RTCC

Under certain circumstances, the value of the Alarm

Repeat Counter register (ALCFGRPT<7:0>) may

be unexpectedly decremented. This happens only

when a byte write to the upper byte of ALCFGRPT

is performed in the interval between a device

POR/BOR and the first edge from the RTCC clock

source.

Affected Silicon Revisions

A3 A5 A6

X

Work around

15. Module: Memory (Program Space

Visibility)

Do not perform byte writes on ALCFGRPT,

particularly the upper byte.

When accessing data in the PSV area of data

RAM, it is possible to generate a false address

error trap condition by reading data located pre-

cisely at the lower address boundary (8000h). If

data is read using an instruction with an

auto-decrement, the resulting RAM address will be

below the PSV boundary (i.e., at 7FFEh); this will

result in an address error trap.

Alternatively, wait until one period of the SOSC

has completed before performing byte writes to

ALCFGRPT.

Affected Silicon Revisions

A3 A5 A6

X

This false address error can also occur if a 32-bit

MOVinstruction is used to read the data at location

8000h.

Work around

Do not use the first location of a PSV page (address

8000h). The MPLAB^®C Compiler (v3.11 or later)

supports the option “-merrata=psv_trap” to

prevent it from generating code that would cause this

erratum.

Affected Silicon Revisions

A3 A5 A6

X

 2008-2013 Microchip Technology Inc.

DS80368N-page 7

PIC24FJ256GA110 FAMILY

18. Module: I²C™ Module (Master Mode)

20. Module: A/D Converter

Under certain circumstances, a module operating

in Master mode may Acknowledge its own com-

mand addressed to a slave device. This happens

when the following occurs:

When using PGEC1 and PGED1 to debug an

application on any 64-pin devices in this family, all

voltage references will be disabled. This includes

VREF+, VREF-, AVDD and AVSS. Any A/D conversion

will always equal 3FFh.

• 10-Bit Addressing mode is used (A10M = 1),

and:

Note: This issue applies only to 64-pin devices

• the I²C master has the same two upper

address bits (I2CADD<9:8>) as the addressed

slave module.

in this

family

(PIC24FJ256GA106,

PIC24FJ192GA106 and PIC24FJ128GA106).

Work around

In these cases, the master also Acknowledges the

address command and generates an erroneous I C

slave interrupt, as well as the I C master interrupt.

2

Use PGEC2 and PGED2 to debug any A/D

functionality.

2

Affected Silicon Revisions

Work around

Several options are available:

A3 A5 A6

• When using 10-Bit Addressing mode, make

certain that the master and slave devices do not

share the same 2 MSBs of their addresses.

X

21. Module: SPIx (Enhanced Buffer Mode)

If this cannot be avoided:

In Enhanced Master mode, the SRMPT bit

(SPIxSTAT<7>) may erroneously become set for

several clock cycles in the middle of a FIFO transfer,

indicating that the shift register is empty when it is

not. This happens when both SPIx clock prescalers

are set to values other than their maximum

(SPIxCON<4:2> ≠ 000and SPIxCON<1:0> ≠ 00).

• Clear the A10M bit (I2CxCON<10> = 0) prior to

performing a Master mode transmit.

• Read the ADD10 bit (I2CxSTAT<8>) to check

for a full 10-bit match whenever a slave I²C

interrupt occurs on the master module.

Affected Silicon Revisions

Work around

A3 A5 A6

Configure the module to generate an SPIx event

interrupt whenever the last bit is shifted out of the

shift register (SPIxSTAT<4:2> = 101). When the

SPIxIF flag becomes set, the shift register is

empty.

X

19. Module: I²C Module (Slave Mode)

Under certain circumstances, a module operating

in Slave mode may not respond correctly to some

of the special addresses reserved by the I²C

protocol. This happens when the following occurs:

Affected Silicon Revisions

A3 A5 A6

X

• 10-Bit Addressing mode is used (A10M = 1),

and

• bits, A<7:1>, of the Slave address

(I2CADD<7:1>) fall into the range of the

reserved 7-bit address ranges, ‘1111xxx’ or

‘0000xxx’.

In these cases, the Slave module Acknowledges

the command and triggers an I²C slave interrupt; it

does not copy the data into the I2CxRCV register

or set the RBF bit.

Work around

Do not set bits, A<7:1>, of the module’s slave

address equal to ‘1111xxx’ or ‘0000xxx’.

Affected Silicon Revisions

A3 A5 A6

X

DS80368N-page 8

 2008-2013 Microchip Technology Inc.

PIC24FJ256GA110 FAMILY

For WDT issues: Disable the WDT by programming

the FWDTEN bit (CW1<7>). After the application

has initialized, enable the WDT in software by

setting the SWDTEN bit (RCON<5>). Allow

10 microseconds to elapse between application

start-up and setting SWDTEN.

22. Module: Core (Code Protection)

When General Segment Code Protection has

been enabled (GCP Configuration bit is pro-

grammed), applications are unable to write to the

first 512 bytes of the program memory space

(0000h through 0200h). In applications that may

require the interrupt vectors to be changed during

run time, such as bootloaders, modifications to the

interrupt vector tables will not be possible.

Affected Silicon Revisions

A3 A5 A6

X

Work around

Create two new interrupt vector tables, one each

for the IVT and AIVT, in an area of program space

beyond the affected region. Map the addresses in

the old vector tables to the new tables. These new

tables can then be modified as needed to the

actual addresses of the ISRs.

25. Module: CTMU (A/D Trigger)

The CTMU may not trigger an automatic A/D con-

version after the current source is turned off. This

happens even when the A/D trigger control bit,

CTTRIG (CTMUCON<8>), has been set.

Affected Silicon Revisions

Work around

A3 A5 A6

Perform a manual A/D conversion by clearing the

SAMP bit (AD1CON1<1>) immediately after the

CTMU current source has been stopped.

X

23. Module: SPI/PPS

Affected Silicon Revisions

The ALTRP/ASCK1 functionality is not supported

by the A3 revision of this part family.

A3 A5 A6

X

Work around

None.

Affected Silicon Revisions

26. Module: Output Compare

A3 A5 A6

In PWM mode, the output compare module may

miss a compare event when the current duty cycle

register (OCxRS) value is 0000h (0% duty cycle)

and the OCxRS register is updated with a value of

0001h. The compare event is only missed the first

time a value of 0001h is written to OCxRS and the

PWM output remains low for one PWM period.

Subsequent PWM high and low times occur as

expected.

X

24. Module: Oscillator (LPRC)

The LPRC may not automatically restart following

BOR events (i.e., when supply voltage sags to

between the BOR and POR thresholds, then

returns to above the BOR level). When this hap-

pens, systems that use the LPRC clock may not

work. This includes the PLL, Two-Speed Start-up,

Fail-Safe Clock Monitor and the WDT.

Work around

If the current OCxRS register value is 0000h, avoid

writing a value of 0001h to OCxRS. Instead, write

a value of 0002h. In this case, however, the duty

cycle will be slightly different from the desired

value.

Work around

For PLL issues: Select a non-PLL Clock mode as

the initial start-up mode, using the FNOSC Config-

uration bits (CW2<10:8>). After the application has

initialized, switch to a PLL Clock mode in software

using the NOSC bits (OSCCON<10:8>). Allow

10 microseconds to elapse between application

start-up and a software clock switch.

Affected Silicon Revisions

A3 A5 A6

X

 2008-2013 Microchip Technology Inc.

DS80368N-page 9

PIC24FJ256GA110 FAMILY

27. Module: Interrupts (INTx)

29. Module: CTMU

Writing to the INTCON2 register may cause an

external interrupt event (inputs on INT0 through

INT4) to be missed. This only happens when the

interrupt event and the write event occur during

the same clock cycle.

Using the CTMUMD bit (PMD4<2>) to selec-

tively power down the module may reduce the

accuracy of the internal band gap reference

(VBG). In those cases where VBG is used as a

reference for other analog modules, the

accuracy of measurements or comparisons may

be affected.

Work around

If possible, do not write to INTCON2 while any of

the external interrupts are enabled.

Work around

If the A/D Converter or comparators are being

used with VBG selected as a reference, do not set

the CTMUMD bit.

If this cannot be avoided, write the data intended

for INTCON2 to any other register in the inter-

rupt block of the SFR (addresses, 0080h to

00E0h); then write the data to INTCON2.

Affected Silicon Revisions

A3 A5 A6

Be certain to write the data to a register not

being actively used by the application, or to any

of the interrupt flag registers, in order to avoid

spurious interrupts. For example, if the inter-

rupts controlled by IEC5 are not being used in

the application, the code sequence would be:

X

30. Module: Oscillator

IEC5 = 0x1E;

INTCON2 = 0x1E;

IEC5 = 0;

The POSCEN bit (OSCCON<2>) has no effect

when a Primary Oscillator with PLL mode is

selected (COSC<2:0> = 011). If XTPLL, HSPLL

or ECPLL Oscillator mode are selected, and the

device enters Sleep mode, the Primary Oscilla-

tor will be disabled, regardless of the state of the

POSCEN bit.

It is the user’s responsibility to determine an

appropriate register for the particular application.

Affected Silicon Revisions

A3 A5 A6

XT, HS and EC Oscillator modes (without the

PLL) will continue to operate as expected.

X

Work around

None.

28. Module: A/D Converter

Once the A/D module

Affected Silicon Revisions

A3 A5 A6

is

enabled

(AD1CON1<15> = 1), it may continue to draw

extra current even if the module is later disabled

(AD1CON1<15> = 0).

X

Work around

In addition to disabling the module through the

ADON bit, set the corresponding PMD bit

(ADC1MD, PMD1<0>) to power it down

completely.

Disabling the A/D module through the PMD regis-

ter also disables the AD1PCFG registers, which in

turn, affects the state of any port pins with analog

inputs. Users should consider the effect on I/O

ports and other digital peripherals on those ports

when ADC1MD is used for power conservation.

Affected Silicon Revisions

A3 A5 A6

X

DS80368N-page 10

 2008-2013 Microchip Technology Inc.

PIC24FJ256GA110 FAMILY

31. Module: Output Compare (Interrupt)

32. Module: UART

Under certain circumstances, an output com-

pare match may cause the interrupt flag (OCxIF)

to become set prior to the Change-of-State

(COS) of the OCx pin. This has been observed

when all of the following are true:

When using UTXISEL<1:0> = 01 (interrupt when

last character is shifted out of the Transmit Shift

Register), and the final character is being shifted

out through the Transmit Shift Register, the TX

interrupt may occur before the final bit is shifted

out.

•

the module is in One-Shot mode

(OCM<2:0> = 001, 010or 100);

Work around

one of the timer modules is being used as

the time base; and

If it is critical that the interrupt processing occurs

only when all transmit operations are complete,

after which, the following work around can be

implemented:

a timer prescaler other than 1:1 is selected.

If the module is re-initialized by clearing

OCM<2:0> after the One-Shot compare, the

OCx pin may not be driven as expected.

Hold off the interrupt routine processing by adding

a loop at the beginning of the routine that polls the

Transmit Shift Register empty bit, as shown in

Example 2.

Work around

After OCxIF is set, allow an interval (in CPU

cycles) of at least twice the prescaler factor to

elapse before clearing OCM<2:0>. For example,

for a prescaler value of 1:8, allow 16 CPU cycles

to elapse after the interrupt.

Affected Silicon Revisions

A3 A5 A6

X

Affected Silicon Revisions

A3 A5 A6

33. Module: Oscillator (Two-Speed Start-up)

X

Two-Speed Start-up is not functional. Leaving the

IESO Configuration bit in its default state

(Two-Speed Start-up enabled) may result in

unpredictable operation.

Work around

None. Always program the IESO Configuration bit

to disable this feature (CW2<15> = 0).

Affected Silicon Revisions

A3 A5 A6

X

EXAMPLE 2:

DELAYING THE ISR BY POLLING THE TRMT BIT

// in UART2 initialization code

...

U2STAbits.UTXISEL0 = 1;

U2STAbits.UTXISEL1 = 0;

...

// Set to generate TX interrupt when all

// transmit operations are complete.

U2TXInterrupt(void)

{

while(U2STAbits.TRMT==0);

...

// wait for the transmit buffer to be empty

// process interrupt

 2008-2013 Microchip Technology Inc.

DS80368N-page 11

PIC24FJ256GA110 FAMILY

When the regulator is enabled, a low-ESR (< 5Ω)

Data Sheet Clarifications

capacitor is required on the VCAP/VDDCORE pin to

stabilize the voltage regulator output voltage. The

VCAP/VDDCORE pin must not be connected to VDD and

must use a capacitor of 10 µF connected to ground. The

type can be ceramic or tantalum. Suitable examples of

capacitors are shown in Table 2-1. Capacitors with

equivalent specifications can be used.

The following typographic corrections and clarifications

are to be noted for the latest version of the device data

sheet (DS39905E):

Note:

Corrections are shown in bold. Where

possible, the original bold text formatting

has been removed for clarity.

Designers may use Figure 2-3 to evaluate ESR

equivalence of candidate devices.

1. Module: Guidelines for Getting Started

with 16-Bit Microcontrollers

The placement of this capacitor should be close to

VCAP/VDDCORE. It is recommended that the trace

length not exceed 0.25 inch (6 mm). Refer to

Section 28.0 “Electrical Characteristics” for

additional information.

Section 2.4 Voltage Regulator Pins (ENVREG/

DISVREG and VCAP/VDDCORE) has been replaced

with a new and more detailed section. The entire text

follows:

When the regulator is disabled, the VCAP/VDDCORE pin

must be tied to a voltage supply at the VDDCORE level.

Refer to Section 28.0 “Electrical Characteristics” for

information on VDD and VDDCORE.

2.4

Voltage Regulator Pins Voltage

Regulator Pins

(ENVREG/DISVREG and

VCAP/VDDCORE)

FIGURE 2-3

FREQUENCY vs. ESR

PERFORMANCE FOR

SUGGESTED VCAP

Note:

This section applies only to PIC24FJ

devices with an on-chip voltage regulator.

10

1

The on-chip voltage regulator enable/disable pin

(ENVREG or DISVREG, depending on the device

family) must always be connected directly to either a

supply voltage or to ground. The particular connection

is determined by whether or not the regulator is to be

used:

0.1

• For ENVREG, tie to VDD to enable the regulator,

or to ground to disable the regulator

0.01

• For DISVREG, tie to ground to enable the 

regulator or to VDD to disable the regulator

0.001

0.01

0.1

1

10

100

1000 10,000

Frequency (MHz)

Refer to Section 25.2 “On-Chip Voltage Regulator”

for details on connecting and using the on-chip

regulator.

Note:

Typical data measurement at 25°C, 0V DC bias.

.

TABLE 2-1

Make

SUITABLE CAPACITOR EQUIVALENTS

Nominal

Part #

Base Tolerance Rated Voltage Temp. Range

Capacitance

TDK

C3216X7R1C106K

C3216X5R1C106K

10 µF

±10%

16V

-55 to 125ºC

-55 to 85ºC

-55 to 125ºC

-55 to 85ºC

-55 to 125ºC

-55 to 85ºC

Panasonic

Murata

ECJ-3YX1C106K

ECJ-4YB1C106K

GRM32DR71C106KA01L

GRM31CR61C106KC31L

Murata

DS80368N-page 12

 2008-2013 Microchip Technology Inc.

PIC24FJ256GA110 FAMILY

In addition to temperature tolerance, the effective

capacitance of large value ceramic capacitors can vary

substantially, based on the amount of DC voltage

applied to the capacitor. This effect can be very signifi-

cant, but is often overlooked or is not always

documented.

2.4.1

CONSIDERATIONS FOR CERAMIC

CAPACITORS

In recent years, large value, low-voltage, surface

mount ceramic capacitors have become very cost

effective in sizes up to a few tens of microfarad. The

low-ESR, small physical size and other properties

make ceramic capacitors very attractive in many types

of applications.

A typical DC bias voltage vs. capacitance graph for

16V, 10V and 6.3V rated capacitors is shown in

Figure 2-4.

Ceramic capacitors are suitable for use with the inter-

nal voltage regulator of this microcontroller. However,

some care is needed in selecting the capacitor to

ensure that it maintains sufficient capacitance over the

intended operating range of the application.

FIGURE 2-4

DC BIAS VOLTAGE vs.

CAPACITANCE

CHARACTERISTICS

Typical low-cost, 10 µF ceramic capacitors are available

in X5R, X7R and Y5V dielectric ratings (other types are

also available, but are less common). The initial toler-

ance specifications for these types of capacitors are

often specified as ±10% to ±20% (X5R and X7R), or

-20%/+80% (Y5V). However, the effective capacitance

that these capacitors provide in an application circuit

will also vary based on additional factors, such as the

applied DC bias voltage and the temperature. The total

in-circuit tolerance is, therefore, much wider than the

initial tolerance specification.

10

0

-10

-20

-30

-40

-50

-60

-70

16V Capacitor

10V Capacitor

6.3V Capacitor

-80

0

1

2

3

4

5

6

7

8

9

10

11

12

13 14

15

16 17

DC Bias Voltage (VDC)

When selecting a ceramic capacitor to be used with the

internal voltage regulator, it is suggested to select a

high-voltage rating, so that the operating voltage is a

small percentage of the maximum rated capacitor volt-

age. For example, choose a ceramic capacitor rated at

16V for the 2.5V core voltage. Suggested capacitors

are shown in Table 2-1.

The X5R and X7R capacitors typically exhibit satisfac-

tory temperature stability (ex: ±15% over a wide

temperature range, but consult the manufacturer's data

sheets for exact specifications). However, Y5V capaci-

tors typically have extreme temperature tolerance

specifications of +22%/-82%. Due to the extreme

temperature tolerance, a 10 µF nominal rated Y5V type

capacitor may not deliver enough total capacitance to

meet minimum internal voltage regulator stability and

transient response requirements. Therefore, Y5V

capacitors are not recommended for use with the inter-

nal regulator if the application must operate over a wide

temperature range.

 2008-2013 Microchip Technology Inc.

DS80368N-page 13

PIC24FJ256GA110 FAMILY

2. Module: Electrical Specifications

3. Module: Electrical Specifications

In Table 28-3 (Temperature and Voltage Specifica-

tions), the Minimum value for BO10 (Brown-out

Reset Voltage) is changed to 1.80V. Typical and

Maximum values remain unchanged.

Table 28-7 (I/O Pin Input Specifications) is

amended by the addition of the following new

specifications:

• D131 (Maximum Load Current for Internal

Pull-up)

• D160 (Injection Currents)

The new specifications, and accompanying new

footnotes, 5 through 9, are shown below (additions

in bold; bold in existing text has been removed for

clarity).

TABLE 28-7: DC CHARACTERISTICS: I/O PIN INPUT SPECIFICATIONS (PARTIAL

PRESENTATION)

Standard Operating Conditions: 3.0V to 3.6V

(unless otherwise stated)

Operating temperature

DC CHARACTERISTICS

-40°C  TA  +85°C for Industrial

-40°C  TA  +125°C for Extended

(1)

Param. Symbol

Characteristic

Min.

Typ

Max.

Units

Conditions

VDD = 2.0V

D131

IPU

Maximum Load Current 

for Digital High Detection with

Internal Pull-up

—

30

µA

—

100

µA

VDD = 3.3V

IICL

Input Low Injection Current

(5,8)

DI60a

0

—

-5

mA

All pins except VDD,

VSS, AVDD, AVSS, MCLR,

VCAP, RB11, SOSCI,

SOSCO, D+, D-, VUSB

and VBUS

IICH

Input High Injection Current

(6,7,8)

DI60b

DI60c

0

—

+5

mA

All pins except VDD,

VSS, AVDD, AVSS, MCLR,

VCAP, RB11, SOSCI,

SOSCO, D+, D-, VUSB

and VBUS, and all 5V

(7)

tolerant pins

IICT

Total Input Injection Current

(9)

(sum of all I/O and control

pins)

-20

+20

Absoluteinstantaneous

sum of all ± input

injection currents from

all I/O pins

( | IICL + | IICH | )  IICT

Note 1: (existing footnote)

2: (existing footnote)

3: (existing footnote)

4: (existing footnote)

5: Parameter characterized but not tested.

6: Non-5V tolerant pins: VIH source > (VDD + 0.3), 5V tolerant pins: VIH source > 5.5V. Characterized but not

tested.

7: Digital 5V tolerant pins cannot tolerate any “positive” input injection current from input sources greater

than 5.5V.

8: Injection currents > | 0 | can affect the performance of all analog peripherals (e.g., A/D, comparators,

internal band gap reference, etc.)

9: Any number and/or combination of I/O pins not excluded under IICL or IICH conditions is permitted pro-

vided the mathematical “absolute instantaneous” sum of the input injection currents from all pins do not

exceed the specified limit. Characterized but not tested.

DS80368N-page 14

 2008-2013 Microchip Technology Inc.

PIC24FJ256GA110 FAMILY

4. Module: Electrical Specifications

Tables 28-10 and 28-11 (shown below) are added to

Section 28.0 “Electrical Characteristics”, follow-

ing the existing Table 28-9 (Program Memory). All

subsequent tables in the section are renumbered

accordingly. (Bold text in these tables represents

original and unmodified content.)

TABLE 28-10: COMPARATOR SPECIFICATIONS

Operating Conditions: 2.0V < VDD < 3.6V, -40°C < TA < +85°C (unless otherwise stated)

Param

No.

Symbol

Characteristic

Min

Typ

Max

Units

Comments

D300

D301

D302

VIOFF

VICM

Input Offset Voltage*

—

0

10

—

30

VDD

—

mV

V

Input Common Mode Voltage*

CMRR

Common Mode Rejection

Ratio*

55

dB

300

301

TRESP

Response Time*⁽¹⁾

—

150

—

400

10

ns

TMC2OV Comparator Mode Change to

Output Valid*

s

*

Parameters are characterized but not tested.

Note 1: Response time measured with one comparator input at (VDD – 1.5)/2, while the other input transitions from

VSS to VDD.

TABLE 28-11: COMPARATOR VOLTAGE REFERENCE SPECIFICATIONS

Operating Conditions: 2.0V < VDD < 3.6V, -40°C < TA < +85°C (unless otherwise stated)

Param

No.

Symbol

Characteristic

Min

Typ

Max

Units

Comments

VRD310 CVRES

VRD311 CVRAA

VRD312 CVRUR

Resolution

VDD/24

—

2k

—

VDD/32

AVDD – 1.5

—

LSb



Absolute Accuracy

Unit Resistor Value (R)

Settling Time⁽¹⁾

—

VR310

TSET

—

10

s

Note 1: Settling time is measured while CVRR = 1and CVR<3:0> bits transition from ‘0000’ to ‘1111’.

 2008-2013 Microchip Technology Inc.

DS80368N-page 15

PIC24FJ256GA110 FAMILY

5. Module: Electrical Specifications

6. Module: Electrical Specifications

In Section 28.0 “Electrical Characteristics”,

under Absolute Maximum Ratings on Page 269,

the “Ambient temperature under bias” has been

changed to -40°C to +135°C.

In Section 28.0 “Electrical Characteristics”,

Table 28-8 (DC Characteristics: I/O Pin Output

Specifications) has been replaced with Table 3

below:

TABLE 3:

DC CHARACTERISTICS: I/O PIN OUTPUT SPECIFICATIONS

Standard Operating Conditions: 2.0V to 3.6V (unless otherwise stated)

DC CHARACTERISTICS

Operating temperature

-40°C  TA  +85°C for Industrial

-40°C  TA  +125°C for Extended

Param

No.

Sym

Characteristic

Min

Typ⁽¹⁾Max

Units

Conditions

VOL

Output Low Voltage

DO10

DO16

I/O Ports

—

0.4

V

IOL = 8.5 mA, VDD = 3.6V

IOL = 5.0 mA, VDD = 2.0V

I/O Ports

IOL = 8.0 mA, VDD = 3.6V, +125°C

IOL = 4.5 mA, VDD = 2.0V, +125°C

VOH

Output High Voltage

DO20

I/O Ports

3.0

2.4

—

V

IOH = -3.0 mA, VDD = 3.6V

IOH = -6.0 mA, VDD = 3.6V

1.65

1.4

IOH = -1.0 mA, VDD = 2.0V

IOH = -3.0 mA, VDD = 2.0V

DO26

I/O Ports

3.0

IOH = -2.5 mA, VDD = 3.6V, +125°C

IOH = -0.5 mA, VDD = 2.0V, +125°C

1.65

Note 1: Data in “Typ” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only

and are not tested.

DS80368N-page 16

 2008-2013 Microchip Technology Inc.

PIC24FJ256GA110 FAMILY

7. Module: Electrical Specifications

In Section 28.0 “Electrical Characteristics”,

Table 28-13 (External Clock Timing Requirements)

has been replaced with Table 4 below:

TABLE 4:

EXTERNAL CLOCK TIMING REQUIREMENTS

Standard Operating Conditions: 2.50 to 3.6V (unless otherwise stated)

AC CHARACTERISTICS

Operating temperature -40°C  TA  +85°C for Industrial

-40°C  TA  +125°C for Extended

Param

No.

Sym

Characteristic

Min

Typ⁽¹⁾

Max

Units

Conditions

OS10 FOSC External CLKI Frequency

(External clocks allowed 

only in EC mode)

DC

4

DC

4

—

32

8

24

6

MHz EC, -40°C  TA  +85°C

MHz ECPLL, -40°C  TA  +85°C

MHz EC, -40°C  TA  +125°C

MHz ECPLL, -40°C  TA  +125°C

Oscillator Frequency

3

10

31

3

—

10

8

32

33

6

MHz XT

MHz XTPLL, -40°C  TA  +85°C

MHz HS, -40°C  TA  +85°C

kHz SOSC

MHz XTPLL, -40°C  TA  +125°C

MHz HS, -40°C  TA  +125°C

10

24

OS20 TOSC TOSC = 1/FOSC

—

See Parameter OS10

for FOSC value

OS25 TCY

Instruction Cycle Time⁽²⁾

62.5

—

DC

—

ns

OS30 TosL, External Clock in (OSCI)

0.45 x TOSC

EC

TosH High or Low Time

OS31 TosR, External Clock in (OSCI)

—

20

ns

TosF Rise or Fall Time

OS40 TckR CLKO Rise Time⁽³⁾

OS41 TckF CLKO Fall Time⁽³⁾

—

6

10

ns

Note 1: Data in “Typ” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only

and are not tested.

2: Instruction cycle period (TCY) equals two times the input oscillator time base period. All specified values

are based on characterization data for that particular oscillator type under standard operating conditions

with the device executing code. Exceeding these specified limits may result in an unstable oscillator

operation and/or higher than expected current consumption. All devices are tested to operate at “Min.”

values with an external clock applied to the OSCI/CLKI pin. When an external clock input is used, the

“Max.” cycle time limit is “DC” (no clock) for all devices.

3: Measurements are taken in EC mode. The CLKO signal is measured on the OSCO pin. CLKO is low for

the Q1-Q2 period (1/2 TCY) and high for the Q3-Q4 period (1/2 TCY).

 2008-2013 Microchip Technology Inc.

DS80368N-page 17

PIC24FJ256GA110 FAMILY

8. Module: Electrical Specifications

In Section 28.0 “Electrical Characteristics”,

Table 28-16 (Internal RC Oscillator Accuracy) is

amended by the addition of the extended temper-

ature condition to Parameter F20. (Bold text in this

table represents the modified content; bold in

existing text has been removed for clarity.)

TABLE 28-16:

INTERNAL RC OSCILLATOR ACCURACY

Standard Operating Conditions: 2.0V to 3.6V (unless otherwise stated)

AC CHARACTERISTICS

Operating temperature

-40°C  TA +85°C for Industrial

-40°C  TA  +125°C for Extended

Param

Characteristic

Min

Typ

Max

Units

Conditions

No.

F20

FRC Accuracy @ 8 MHz⁽¹⁾

-2

-5

—

2

5

%

+25°C, 3.0V  VDD 3.6V

-40°C  TA +85°C, 

3.0V  VDD 3.6V

-6.5

—

6.5

%

-40°C  TA +125°C, 

3.0V  VDD 3.6V

LPRC Accuracy @ 31 kHz⁽²⁾

-20

—

20

%

-40°C  TA +85°C, 

3.0V  VDD 3.6V

F21

Note 1: Frequency is calibrated at +25°C and 3.3V. OSCTUN bits can be used to compensate for temperature drift.

2: Change of LPRC frequency as VDD changes.

DS80368N-page 18

 2008-2013 Microchip Technology Inc.

PIC24FJ256GA110 FAMILY

9. Module: Product Identification System

The “Product Identification System” section on

Page 329 has been amended by an additional

temperature range. (Bold text in this section

represents the modified content; bold in existing

text has been removed for clarity.)

PRODUCT IDENTIFICATION SYSTEM

To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.

Examples:

PIC 24 FJ 256 GA1 10 T - I / PT - XXX

a)

PIC24FJ128GA106-I/PT:



General purpose PIC24F, 128-Kbyte program

memory, 64-pin, Industrial temp.,TQFP package.

Microchip Trademark

Architecture

b)

PIC24FJ256GA110-I/PT:



General purpose PIC24F, 256-Kbyte program

memory, 100-pin, Industrial temp.,TQFP package.

Flash Memory Family

Program Memory Size (KB)

Product Group

Pin Count

Tape and Reel Flag (if applicable)

Temperature Range

Package

Pattern

Architecture

24 = 16-bit modified Harvard without DSP

Flash Memory Family FJ = Flash program memory

Product Group

Pin Count

GA1 = General purpose microcontrollers

06 = 64-pin

08 = 80-pin

10 = 100-pin

Temperature Range

Package

I

E

=

-40C to +85C (Industrial)

-40C to +125C (Extended)

PF = 100-lead (14x14x1mm) TQFP (Thin Quad Flatpack)

PT = 64-lead, 80-lead, 100-lead (12x12x1 mm)

TQFP (Thin Quad Flatpack)

MR = 64-lead (9x9x0.9 mm) QFN (Quad Flatpack No Leads)

Pattern

Three-digit QTP, SQTP, Code or Special Requirements 

(blank otherwise)

ES = Engineering Sample

 2008-2013 Microchip Technology Inc.

DS80368N-page 19

PIC24FJ256GA110 FAMILY

Rev L Document (11/2011)

APPENDIX A: DOCUMENT

REVISION HISTORY

Added silicon issues 29 (CTMU), 30 (Oscillator),

31 (Output Compare – Interrupt) and 32 (UART) to all

current silicon revisions.

Rev A Document (2/2008)

First revision of this document. Includes silicon issues

1 (Core, RAM Operation), 2 (Core, BOR), 3 (JTAG,

Programming), 4 (UART), 5 (I/O, PORTB), 6 (SPI) and

7 (Input Capture).

Added data sheet clarifications 2, 3 and 4 (Electrical

Specifications).

Rev M Document (10/2012)

Added recently introduced 64 Kbyte devices to the

document. Applicable silicon issues are for other

members of this device family, as indicated in Table 2.

Rev B Document (4/2008)

Revised silicon issues 7 to clarify the requirement for

latency compensation. Added silicon issues 8 (UART –

Interrupt), 9 (UART – FIFO Error Flags) and 10 (SPI –

Enhanced Buffer Modes).

Added silicon issue 33 (Oscillator – Two-Speed

Start-up) to all existing silicon revisions.

Added data sheet clarifications 5, 6, 7 and 8 (Electrical

Specifications) and 9 (Product Identification System).

Rev C Document (7/2008)

Revised silicon issues 4 (UART) and 6 (SPI, Master

Mode) to reflect updated definition of issues. Added sil-

icon issues 11 through 13 (UART, IrDA), 14 (Core,

Instruction Set), 15 (Memory, Program Space Visibil-

ity), 16 (ICSP), 17 (RTCC), 18 (I²C, Master Mode),

19 (I²C Module (Slave Mode) and 20 (A/D Converter).

Rev N Document (1/2013)

Revised data sheet clarification 2 to show minimum

value for BO10 (Brown-out Reset Voltage) as 1.80V

instead of 1.90V.

Rev D Document (10/2008)

Added silicon issue 21 (SPI – Enhanced Buffer Mode).

Rev E Document (04/2009)

Added silicon issue 22 (Core – Code Protection),

23 (SPI/PPS), 24 (Oscillator – LPRC) and 25 (CTMU –

A/D Trigger).

Rev F Document (07/2009)

Added silicon revision A5 to document. Includes exist-

ing silicon issues 1 (Core, RAM Operation), 3 (JTAG,

Programming), 8 (UART – UERIF Interrupt) and

14 (Core – Instruction Set). No additional new issues

added.

Rev G Document (06/2010)

Added silicon issues 26 (Output Compare) and

27 (Interrupts – INTx) to silicon revisions A3 and A5.

Rev H Document (07/2010)

Added silicon issue 28 (A/D Converter) to silicon

revisions A3 and A5.

Rev J Document (09/2010)

Revised silicon issue 28 (A/D Converter) to reflect

updated definition of issues. Added data sheet

clarification issue 1 (Guidelines For Getting Started

with 16-Bit Microcontrollers).

Rev K Document (6/2011)

Added silicon revision A6 to document. Includes all sil-

icon issues currently in revision A5 (1, 3, 14, 27 and

28). No additional new issues added.

DS80368N-page 20

 2008-2013 Microchip Technology Inc.

Note the following details of the code protection feature on Microchip devices:

•

Microchip products meet the specification contained in their particular Microchip Data Sheet.

•

Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the

intended manner and under normal conditions.

•

There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our

knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data

Sheets. Most likely, the person doing so is engaged in theft of intellectual property.

•

Microchip is willing to work with the customer who is concerned about the integrity of their code.

Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not

mean that we are guaranteeing the product as “unbreakable.”

Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our

products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts

allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.

Information contained in this publication regarding device

applications and the like is provided only for your convenience

and may be superseded by updates. It is your responsibility to

ensure that your application meets with your specifications.

MICROCHIP MAKES NO REPRESENTATIONS OR

WARRANTIES OF ANY KIND WHETHER EXPRESS OR

IMPLIED, WRITTEN OR ORAL, STATUTORY OR

OTHERWISE, RELATED TO THE INFORMATION,

INCLUDING BUT NOT LIMITED TO ITS CONDITION,

QUALITY, PERFORMANCE, MERCHANTABILITY OR

FITNESS FOR PURPOSE. Microchip disclaims all liability

arising from this information and its use. Use of Microchip

devices in life support and/or safety applications is entirely at

the buyer’s risk, and the buyer agrees to defend, indemnify and

hold harmless Microchip from any and all damages, claims,

suits, or expenses resulting from such use. No licenses are

conveyed, implicitly or otherwise, under any Microchip

intellectual property rights.

Trademarks

The Microchip name and logo, the Microchip logo, dsPIC,

FlashFlex, KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro,

PICSTART, PIC logo, rfPIC, SST, SST Logo, SuperFlash

and UNI/O are registered trademarks of Microchip Technology

Incorporated in the U.S.A. and other countries.

32

FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor,

MTP, SEEVAL and The Embedded Control Solutions

Company are registered trademarks of Microchip Technology

Incorporated in the U.S.A.

Silicon Storage Technology is a registered trademark of

Microchip Technology Inc. in other countries.

Analog-for-the-Digital Age, Application Maestro, BodyCom,

chipKIT, chipKIT logo, CodeGuard, dsPICDEM,

dsPICDEM.net, dsPICworks, dsSPEAK, ECAN,

ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial

Programming, ICSP, Mindi, MiWi, MPASM, MPF, MPLAB

Certified logo, MPLIB, MPLINK, mTouch, Omniscient Code

Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit,

PICtail, REAL ICE, rfLAB, Select Mode, SQI, Serial Quad I/O,

Total Endurance, TSHARC, UniWinDriver, WiperLock, ZENA

and Z-Scale are trademarks of Microchip Technology

Incorporated in the U.S.A. and other countries.

SQTP is a service mark of Microchip Technology Incorporated

in the U.S.A.

GestIC and ULPP are registered trademarks of Microchip

Technology Germany II GmbH & Co. & KG, a subsidiary of

Microchip Technology Inc., in other countries.

All other trademarks mentioned herein are property of their

respective companies.

Printed on recycled paper.

ISBN: 978-1-62076-943-0

QUALITY MANAGEMENT SYSTEM

CERTIFIED BY DNV

Microchip received ISO/TS-16949:2009 certification for its worldwide

headquarters, design and wafer fabrication facilities in Chandler and

Tempe, Arizona; Gresham, Oregon and design centers in California

and India. The Company’s quality system processes and procedures

are for its PIC^®MCUs and dsPIC^®DSCs, KEELOQ^®code hopping

devices, Serial EEPROMs, microperipherals, nonvolatile memory and

analog products. In addition, Microchip’s quality system for the design

and manufacture of development systems is ISO 9001:2000 certified.

== ISO/TS 16949 ==

 2008-2013 Microchip Technology Inc.

DS80368N-page 21

Worldwide Sales and Service

AMERICAS

ASIA/PACIFIC

EUROPE

Corporate Office

2355 West Chandler Blvd.

Chandler, AZ 85224-6199

Tel: 480-792-7200

Fax: 480-792-7277

Technical Support:

http://www.microchip.com/

support

Asia Pacific Office

Suites 3707-14, 37th Floor

Tower 6, The Gateway

Harbour City, Kowloon

Hong Kong

Tel: 852-2401-1200

Fax: 852-2401-3431

India - Bangalore

Tel: 91-80-3090-4444

Fax: 91-80-3090-4123

Austria - Wels

Tel: 43-7242-2244-39

Fax: 43-7242-2244-393

Denmark - Copenhagen

Tel: 45-4450-2828

Fax: 45-4485-2829

India - New Delhi

Tel: 91-11-4160-8631

Fax: 91-11-4160-8632

France - Paris

Tel: 33-1-69-53-63-20

Fax: 33-1-69-30-90-79

India - Pune

Tel: 91-20-2566-1512

Fax: 91-20-2566-1513

Australia - Sydney

Tel: 61-2-9868-6733

Fax: 61-2-9868-6755

Web Address:

www.microchip.com

Germany - Munich

Tel: 49-89-627-144-0

Fax: 49-89-627-144-44

Japan - Osaka

Tel: 81-6-6152-7160

Fax: 81-6-6152-9310

Atlanta

Duluth, GA

Tel: 678-957-9614

Fax: 678-957-1455

China - Beijing

Tel: 86-10-8569-7000

Fax: 86-10-8528-2104

Italy - Milan

Tel: 39-0331-742611

Fax: 39-0331-466781

Japan - Tokyo

Tel: 81-3-6880- 3770

Fax: 81-3-6880-3771

China - Chengdu

Tel: 86-28-8665-5511

Fax: 86-28-8665-7889

Boston

Westborough, MA

Tel: 774-760-0087

Fax: 774-760-0088

Netherlands - Drunen

Tel: 31-416-690399

Fax: 31-416-690340

Korea - Daegu

Tel: 82-53-744-4301

Fax: 82-53-744-4302

China - Chongqing

Tel: 86-23-8980-9588

Fax: 86-23-8980-9500

Chicago

Itasca, IL

Tel: 630-285-0071

Fax: 630-285-0075

Spain - Madrid

Tel: 34-91-708-08-90

Fax: 34-91-708-08-91

Korea - Seoul

China - Hangzhou

Tel: 86-571-2819-3187

Fax: 86-571-2819-3189

Tel: 82-2-554-7200

Fax: 82-2-558-5932 or

82-2-558-5934

UK - Wokingham

Tel: 44-118-921-5869

Fax: 44-118-921-5820

Cleveland

Independence, OH

Tel: 216-447-0464

Fax: 216-447-0643

China - Hong Kong SAR

Tel: 852-2943-5100

Fax: 852-2401-3431

Malaysia - Kuala Lumpur

Tel: 60-3-6201-9857

Fax: 60-3-6201-9859

Dallas

Addison, TX

Tel: 972-818-7423

Fax: 972-818-2924

China - Nanjing

Tel: 86-25-8473-2460

Fax: 86-25-8473-2470

Malaysia - Penang

Tel: 60-4-227-8870

Fax: 60-4-227-4068

China - Qingdao

Tel: 86-532-8502-7355

Fax: 86-532-8502-7205

Philippines - Manila

Tel: 63-2-634-9065

Fax: 63-2-634-9069

Detroit

Farmington Hills, MI

Tel: 248-538-2250

Fax: 248-538-2260

China - Shanghai

Tel: 86-21-5407-5533

Fax: 86-21-5407-5066

Singapore

Tel: 65-6334-8870

Fax: 65-6334-8850

Indianapolis

Noblesville, IN

Tel: 317-773-8323

Fax: 317-773-5453

China - Shenyang

Tel: 86-24-2334-2829

Fax: 86-24-2334-2393

Taiwan - Hsin Chu

Tel: 886-3-5778-366

Fax: 886-3-5770-955

Los Angeles

China - Shenzhen

Tel: 86-755-8864-2200

Fax: 86-755-8203-1760

Taiwan - Kaohsiung

Tel: 886-7-213-7828

Fax: 886-7-330-9305

Mission Viejo, CA

Tel: 949-462-9523

Fax: 949-462-9608

China - Wuhan

Tel: 86-27-5980-5300

Fax: 86-27-5980-5118

Taiwan - Taipei

Tel: 886-2-2508-8600

Fax: 886-2-2508-0102

Santa Clara

Santa Clara, CA

Tel: 408-961-6444

Fax: 408-961-6445

China - Xian

Tel: 86-29-8833-7252

Fax: 86-29-8833-7256

Thailand - Bangkok

Tel: 66-2-694-1351

Fax: 66-2-694-1350

Toronto

Mississauga, Ontario,

Canada

China - Xiamen

Tel: 905-673-0699

Fax: 905-673-6509

Tel: 86-592-2388138

Fax: 86-592-2388130

China - Zhuhai

Tel: 86-756-3210040

Fax: 86-756-3210049

11/29/12

DS80368N-page 22

 2008-2013 Microchip Technology Inc.


型号：	PIC24FJ192GA106
厂家：	MICROCHIP
描述：	PIC24FJ256GA110 Family Silicon Errata and Data Sheet Clarification PIC24FJ256GA110系列芯片勘误表和数据表澄清
文件：	总22页 (文件大小：392K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

PIC24FJ192GA106 [MICROCHIP]

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