PIC24FJ64GB002-E/ML_技术文档

PIC24FJ64GB004 Family

Data Sheet

28/44-Pin, 16-Bit,

Flash Microcontrollers

with USB On-The-Go (OTG)

and nanoWatt XLP Technology

 2010 Microchip Technology Inc.

DS39940D

Note the following details of the code protection feature on Microchip devices:

•

Microchip products meet the specification contained in their particular Microchip Data Sheet.

•

Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the

intended manner and under normal conditions.

•

There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our

knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data

Sheets. Most likely, the person doing so is engaged in theft of intellectual property.

•

Microchip is willing to work with the customer who is concerned about the integrity of their code.

Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not

mean that we are guaranteeing the product as “unbreakable.”

Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our

products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts

allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.

Information contained in this publication regarding device

applications and the like is provided only for your convenience

and may be superseded by updates. It is your responsibility to

ensure that your application meets with your specifications.

MICROCHIP MAKES NO REPRESENTATIONS OR

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OTHERWISE, RELATED TO THE INFORMATION,

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Trademarks

The Microchip name and logo, the Microchip logo, dsPIC,

KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART,

32

PIC logo, rfPIC and UNI/O are registered trademarks of

Microchip Technology Incorporated in the U.S.A. and other

countries.

FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor,

MXDEV, MXLAB, SEEVAL and The Embedded Control

Solutions Company are registered trademarks of Microchip

Technology Incorporated in the U.S.A.

Analog-for-the-Digital Age, Application Maestro, CodeGuard,

dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN,

ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial

Programming, ICSP, Mindi, MiWi, MPASM, MPLAB Certified

logo, MPLIB, MPLINK, mTouch, Octopus, Omniscient Code

Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit,

PICtail, REAL ICE, rfLAB, Select Mode, Total Endurance,

TSHARC, UniWinDriver, WiperLock and ZENA are

trademarks of Microchip Technology Incorporated in the

U.S.A. and other countries.

SQTP is a service mark of Microchip Technology Incorporated

in the U.S.A.

All other trademarks mentioned herein are property of their

respective companies.

Printed on recycled paper.

ISBN: 978-1-60932-439-1

Microchip received ISO/TS-16949:2002 certification for its worldwide

headquarters, design and wafer fabrication facilities in Chandler and

Tempe, Arizona; Gresham, Oregon and design centers in California

and India. The Company’s quality system processes and procedures

are for its PIC^®MCUs and dsPIC^®DSCs, KEELOQ^®code hopping

devices, Serial EEPROMs, microperipherals, nonvolatile memory and

analog products. In addition, Microchip’s quality system for the design

and manufacture of development systems is ISO 9001:2000 certified.

DS39940D-page 2

 2010 Microchip Technology Inc.

PIC24FJ64GB004 FAMILY

28/44-Pin, 16-Bit, Flash Microcontrollers with

USB On-The-Go (OTG) and nanoWatt XLP Technology

Universal Serial Bus Features:

Power Management Modes:

•

USB v2.0 On-The-Go (OTG) Compliant

Dual Role Capable – can act as either Host or Peripheral

Low-Speed (1.5 Mb/s) and Full-Speed (12 Mb/s) USB

Operation in Host mode

•

Selectable Power Management modes with nanoWatt

XLP Technology for Extremely Low Power:

-

Deep Sleep mode allows near total power-down

(20 nA typical and 500 nA with RTCC or WDT),

along with the ability to wake-up on external triggers

or self-wake on programmable WDT or RTCC alarm

Extreme low-power DSBOR for Deep Sleep,

LPBOR for all other modes

Sleep mode shuts down peripherals and core for

substantial power reduction, fast wake-up

Idle mode shuts down the CPU and peripherals for

significant power reduction, down to 4.5 A typical

Doze mode enables CPU clock to run slower than

peripherals

•

Full-Speed USB Operation in Device mode

High-Precision PLL for USB

0.25% Accuracy using Internal Oscillator – No External

Crystal Required

-

•

Internal Voltage Boost Assist for USB Bus Voltage

Generation

Interface for Off-Chip Charge Pump for USB Bus

Voltage Generation

Supports up to 32 Endpoints (16 bidirectional):

-

USB module can use any RAM location on the

device as USB endpoint buffers

Alternate Clock modes allow on-the-fly switching to

a lower clock speed for selective power reduction

during Run mode down to 15 A typical

•

On-Chip USB Transceiver

Interface for Off-Chip USB Transceiver

Supports Control, Interrupt, Isochronous and Bulk Transfers

On-Chip Pull-up and Pull-Down Resistors

Special Microcontroller Features:

•

Operating Voltage Range of 2.0V to 3.6V

Self-Reprogrammable under Software Control

5.5V Tolerant Input (digital pins only)

High-Current Sink/Source (18 mA/18 mA) on All I/O Pins

Flash Program Memory:

High-Performance CPU:

•

Modified Harvard Architecture

Up to 16 MIPS Operation @ 32 MHz

8 MHz Internal Oscillator with 0.25% Typical Accuracy:

-

10,000 erase/write cycle endurance (minimum)

20-year data retention minimum

Selectable write protection boundary

-

96 MHz PLL

Multiple divide options

•

17-Bit x 17-Bit Single-Cycle Hardware

Fractional/integer Multiplier

•

Fail-Safe Clock Monitor Operation:

-

Detects clock failure and switches to on-chip

FRC oscillator

•

32-Bit by 16-Bit Hardware Divider

16 x 16-Bit Working Register Array

C Compiler Optimized Instruction Set Architecture:

•

On-Chip 2.5V Regulator

Power-on Reset (POR), Power-up Timer (PWRT)

and Oscillator Start-up Timer (OST)

Two Flexible Watchdog Timers (WDT) for Reliable

Operation:

-

76 base instructions

Flexible addressing modes

•

Linear Program Memory Addressing up to 12 Mbytes

Linear Data Memory Addressing up to 64 Kbytes

Two Address Generation Units for Separate Read and

Write Addressing of Data Memory

-

Standard programmable WDT for normal operation

Extreme low-power WDT with programmable

period of 2 ms to 26 days for Deep Sleep mode

•

In-Circuit Serial Programming™ (ICSP™) and

In-Circuit Debug (ICD) via 2 Pins

JTAG Boundary Scan Support

Remappable Peripherals

PIC24FJ

Device

32GB002

64GB002

32GB004

64GB004

28

44

32K

64K

32K

64K

8K

15

25

5

2

9

3

Y

13

 2010 Microchip Technology Inc.

DS39940D-page 3

PIC24FJ64GB004 FAMILY

•

Hardware Real-Time Clock/Calendar (RTCC):

Provides clock, calendar and alarm functions

Analog Features:

-

•

10-Bit, up to 13-Channel Analog-to-Digital (A/D)

Converter:

-

Functions even in Deep Sleep mode

Two 3-Wire/4-Wire SPI modules (support 4 Frame

modes) with 8-Level FIFO Buffer

•

-

500 ksps conversion rate

Conversion available during Sleep and Idle

2

Two I C™ modules support Multi-Master/Slave mode

and 7-Bit/10-Bit Addressing

Two UART modules:

-

•

Three Analog Comparators with Programmable

Input/Output Configuration

Charge Time Measurement Unit (CTMU):

Supports RS-485, RS-232 and LIN/J2602

On-chip hardware encoder/decoder for IrDA^®

Auto-wake-up on Start bit

Auto-Baud Detect (ABD)

4-level deep FIFO buffer

-

Supports capacitive touch sensing for touch

screens and capacitive switches

Provides high-resolution time measurement and

simple temperature sensing

•

Five 16-Bit Timers/Counters with Programmable

Prescaler

Five 16-Bit Capture Inputs, each with a Dedicated Time

Base

Five 16-Bit Compare/PWM Outputs, each with a

Dedicated Time Base

Programmable, 32-Bit Cyclic Redundancy Check (CRC)

Generator

Peripheral Features:

•

Peripheral Pin Select:

-

Allows independent I/O mapping of many peripherals

Up to 25 available pins (44-pin devices)

Continuous hardware integrity checking and safety

interlocks prevent unintentional configuration changes

•

8-Bit Parallel Master Port (PMP/PSP):

•

Configurable Open-Drain Outputs on Digital I/O Pins

Up to 3 External Interrupt Sources

-

Up to 16-bit multiplexed addressing, with up to

11 dedicated address pins on 44-pin devices

Programmable polarity on control lines

Supports legacy Parallel Slave Port

-

Pin Diagrams

28-Pin SPDIP, SOIC, SSOP⁽¹⁾

MCLR

1

2

3

4

5

6

7

8

28

27

26

25

24

23

22

21

20

19

18

17

16

15

VDD

VSS

(2)

PGED3/AN0/C3INC/VREF+/ASDA1 /RP5/PMD7/CTED1/VBUSVLD/VCMPST1/CN2/RA0

PGEC3/AN1/C3IND/VREF-/ASCL1 /RP6/PMD6/CTED2/SESSVLD/VCMPST2/CN3/RA1

(2)

AN9/C3INA/VBUSCHG/RP15/VBUSST/CN11/RB15

AN10/C3INB/CVREF/VCPCON/VBUSON/RP14/CN12/RB14

AN11/C1INC/RP13/PMRD/REFO/SESSEND/CN13/RB13

VUSB

PGEC2/D-/VMIO/RP11/CN15/RB11

PGED2/D+/VPIO/RP10/CN16/RB10

VCAP/VDDCORE

PGED1/AN2/C2INB/DPH/RP0/PMD0/CN4/RB0

PGEC1/AN3/C2INA/DMH/RP1/PMD1/CN5/RB1

AN4/C1INB/DPLN/SDA2/RP2/PMD2/CN6/RB2

AN5/C1INA/DMLN/RTCC/SCL2/RP3/PMWR/CN7/RB3

VSS

OSCI/CLKI/C1IND/PMCS1/CN30/RA2

OSCO/CLKO/PMA0/CN29/RA3

SOSCI/C2IND/RP4/PMBE/CN1/RB4

SOSCO/SCLKI/T1CK/C2INC/PMA1/CN0/RA4

VDD

9

DISVREG

10

11

12

13

14

TDO/SDA1/RP9/PMD3/RCV/CN21/RB9

TCK/USBOEN/SCL1/RP8/PMD4/CN22/RB8

TDI/RP7/PMD5/INT0/CN23/RB7

VBUS

TMS/USBID/CN27/RB5

Legend:

Note 1: Gray shading indicates 5.5V tolerant input pins.

2: Alternative multiplexing for SDA1 and SCL1 when the I2C1SEL bit is set.

RPn represents remappable peripheral pins.

DS39940D-page 4

 2010 Microchip Technology Inc.

PIC24FJ64GB004 FAMILY

Pin Diagrams

28-Pin QFN^(1,3)

28272625242322

PGED1/AN2/C2INB/DPH/RP0/PMD0/CN4/RB0

AN11/C1INC/RP13/PMRD/REFO/SESSEND/CN13/RB13

1

2

3

4

5

6

7

21

20

19

18

17

16

15

PGEC1/AN3/C2INA/DMH/RP1/PMD1/CN5/RB1

AN4/C1INB/DPLN/SDA2/RP2/PMD2/CN6/RB2

VUSB

PGEC2/D-/VMIO/RP11/CN15/RB11

PGED2/D+/VPIO/RP10/CN16/RB10

VCAP/VDDCORE

PIC24FJXXGB002

AN5/C1INA/DMLN/RTCC/SCL2/RP3/PMWR/CN7/RB3

VSS

OSCI/CLKI/C1IND/PMCS1/CN30/RA2

OSCO/CLKO/PMA0/CN29/RA3

DISVREG

TDO/SDA1/RP9/PMD3/RCV/CN21/RB9

8

9 1011 12 1314

Legend:

RPn represents remappable peripheral pins.

Note 1: Gray shading indicates 5.5V tolerant input pins.

2: Alternative multiplexing for SDA1 and SCL1 when the I2C1SEL bit is set.

3: The back pad on QFN devices should be connected to VSS.

 2010 Microchip Technology Inc.

DS39940D-page 5

PIC24FJ64GB004 FAMILY

Pin Diagrams

44-PIN TQFP,

44-Pin QFN^(1,3)

SOSCI/C2IND/RP4/CN1/RB4

TDO/PMA8/RA8

OSCO/CLKO/CN29/RA3

OSCI/CLKI/C1IND/PMCS1/CN30/RA2

VSS

SDA1/RP9/PMD3/RCV/CN21/RB9

33

32

31

30

29

28

1

2

RP22/PMA1/CN18/RC6

RP23/PMA0/CN17/RC7

RP24/PMA5/CN20/RC8

RP25/PMA6/CN19/RC9

3

4

5

VDD

DISVREG

PIC24FJXXGB004

6

7

8

9

AN8/RP18/PMA2/CN10/RC2

AN7/RP17/CN9/RC1

AN6/RP16/CN8/RC0

AN5/C1INA/DMLN/RTCC/SCL2/RP3/PMWR/CN7/RB3

AN4/C1INB/DPLN/SDA2/RP2/PMD2/CN6/RB2

VCAP/VDDCORE

PGED2/D+/VPIO/RP10/CN16/RB10

PGEC2/D-/VMIO/RP11/CN15/RB11

VUSB

27

26

25

24

23

10

11

AN11/C1INC/RP13/REFO/PMRD/SESSEND/CN13/RB13

Legend:

RPn represents remappable peripheral pins.

Note 1: Gray shading indicates 5.5V tolerant input pins.

2: Alternative multiplexing for SDA1 and SCL1 when the I2C1SEL bit is set.

3: The back pad on QFN devices should be connected to VSS.

DS39940D-page 6

 2010 Microchip Technology Inc.

PIC24FJ64GB004 FAMILY

Table of Contents

1.0 Device Overview .......................................................................................................................................................................... 9

2.0 Guidelines for Getting Started with 16-bit Microcontrollers ........................................................................................................ 19

3.0 CPU ........................................................................................................................................................................................... 25

4.0 Memory Organization................................................................................................................................................................. 31

5.0 Flash Program Memory.............................................................................................................................................................. 55

6.0 Resets ........................................................................................................................................................................................ 63

7.0 Interrupt Controller ..................................................................................................................................................................... 69

8.0 Oscillator Configuration............................................................................................................................................................ 107

9.0 Power-Saving Features............................................................................................................................................................ 117

10.0 I/O Ports ................................................................................................................................................................................... 127

11.0 Timer1 ...................................................................................................................................................................................... 149

12.0 Timer2/3 and Timer4/5 ............................................................................................................................................................ 151

13.0 Input Capture with Dedicated Timers....................................................................................................................................... 157

14.0 Output Compare with Dedicated Timers .................................................................................................................................. 161

15.0 Serial Peripheral Interface (SPI)............................................................................................................................................... 171

2

16.0 Inter-Integrated Circuit (I C™) ................................................................................................................................................. 181

17.0 Universal Asynchronous Receiver Transmitter (UART)........................................................................................................... 189

18.0 Universal Serial Bus with On-The-Go Support (USB OTG) ..................................................................................................... 197

19.0 Parallel Master Port (PMP)....................................................................................................................................................... 231

20.0 Real-Time Clock and Calendar (RTCC) .................................................................................................................................. 241

21.0 32-Bit Programmable Cyclic Redundancy Check (CRC) Generator........................................................................................ 253

22.0 10-Bit High-Speed A/D Converter ............................................................................................................................................ 259

23.0 Triple Comparator Module........................................................................................................................................................ 269

24.0 Comparator Voltage Reference................................................................................................................................................ 273

25.0 Charge Time Measurement Unit (CTMU) ................................................................................................................................ 275

26.0 Special Features ...................................................................................................................................................................... 279

27.0 Development Support............................................................................................................................................................... 293

28.0 Instruction Set Summary.......................................................................................................................................................... 297

29.0 Electrical Characteristics.......................................................................................................................................................... 305

30.0 Packaging Information.............................................................................................................................................................. 327

Appendix A: Revision History............................................................................................................................................................. 341

The Microchip Web Site..................................................................................................................................................................... 349

Customer Change Notification Service .............................................................................................................................................. 349

Customer Support.............................................................................................................................................................................. 349

Reader Response.............................................................................................................................................................................. 350

Product Identification System ............................................................................................................................................................ 351

 2010 Microchip Technology Inc.

DS39940D-page 7

PIC24FJ64GB004 FAMILY

TO OUR VALUED CUSTOMERS

It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip

products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and

enhanced as new volumes and updates are introduced.

If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via

E-mail at docerrors@microchip.com or fax the Reader Response Form in the back of this data sheet to (480) 792-4150. We

welcome your feedback.

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The last character of the literature number is the version number, (e.g., DS30000A is version A of document DS30000).

Errata

An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current

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To determine if an errata sheet exists for a particular device, please check with one of the following:

•

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When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are

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DS39940D-page 8

 2010 Microchip Technology Inc.

PIC24FJ64GB004 FAMILY

• Instruction-Based Power-Saving Modes: There

are three instruction-based power-saving modes:

1.0

DEVICE OVERVIEW

This document contains device-specific information for

the following devices:

- Idle Mode – The core is shut down while leaving

the peripherals active.

• PIC24FJ32GB002

• PIC24FJ64GB002

• PIC24FJ32GB004

• PIC24FJ64GB004

- Sleep Mode – The core and peripherals that

require the system clock are shut down, leaving

the peripherals active that use their own clock or

the clock from other devices.

This family expands on the existing line of Microchip‘s

16-bit microcontrollers, combining an expanded

peripheral feature set and enhanced computational

performance with a new connectivity option: USB

On-The-Go (OTG). The PIC24FJ64GB004 family

provides a new platform for high-performance USB

applications which may need more than an 8-bit

platform, but do not require the power of a digital signal

processor.

- Deep Sleep Mode – The core, peripherals

(except RTCC and DSWDT), Flash and SRAM

are shut down for optimal current savings to

extend battery life for portable applications.

1.1.3

OSCILLATOR OPTIONS AND

FEATURES

All of the devices in the PIC24FJ64GB004 family offer

five different oscillator options, allowing users a range

of choices in developing application hardware. These

include:

1.1

Core Features

1.1.1

16-BIT ARCHITECTURE

• Two Crystal modes using crystals or ceramic

resonators.

Central to all PIC24F devices is the 16-bit modified

Harvard architecture, first introduced with Microchip’s

dsPIC^®digital signal controllers. The PIC24F CPU core

offers a wide range of enhancements, such as:

• Two External Clock modes offering the option of a

divide-by-2 clock output.

• A Fast Internal RC Oscillator (FRC) with a

nominal 8 MHz output, which can also be divided

under software control to provide clock speeds as

low as 31 kHz.

• 16-bit data and 24-bit address paths with the

ability to move information between data and

memory spaces

• Linear addressing of up to 12 Mbytes (program

space) and 64 Kbytes (data)

• A Phase Lock Loop (PLL) frequency multiplier

available to the external oscillator modes and the

FRC Oscillator, which allows clock speeds of up

to 32 MHz.

• A 16-element working register array with built-in

software stack support

• A 17 x 17 hardware multiplier with support for

integer math

• A separate Low-Power Internal RC Oscillator

(LPRC) with a fixed 31 kHz output, which pro-

vides a low-power option for timing-insensitive

applications.

• Hardware support for 32 by 16-bit division

• An instruction set that supports multiple

addressing modes and is optimized for high-level

languages, such as ‘C’

The internal oscillator block also provides a stable

reference source for the Fail-Safe Clock Monitor. This

option constantly monitors the main clock source

against a reference signal provided by the internal

oscillator and enables the controller to switch to the

internal oscillator, allowing for continued low-speed

operation or a safe application shutdown.

• Operational performance up to 16 MIPS

1.1.2

POWER-SAVING TECHNOLOGY

All of the devices in the PIC24FJ64GB004 family

incorporate a range of features that can significantly

reduce power consumption during operation. Key

items include:

1.1.4

EASY MIGRATION

Regardless of the memory size, all devices share the

same rich set of peripherals, allowing for a smooth

migration path as applications grow and evolve. The

consistent pinout scheme used throughout the entire

family also aids in migrating from one device to the next

larger device.

• On-the-Fly Clock Switching: The device clock

can be changed under software control to the

Timer1 source or the internal, Low-Power Internal

RC Oscillator during operation, allowing the user

to incorporate power-saving ideas into their

software designs.

• Doze Mode Operation: When timing-sensitive

applications, such as serial communications,

require the uninterrupted operation of peripherals,

the CPU clock speed can be selectively reduced,

allowing incremental power savings without

missing a beat.

The PIC24F family is pin-compatible with devices in the

dsPIC33 family, and shares some compatibility with the

pinout schema for PIC18 and dsPIC30 devices. This

extends the ability of applications to grow from the

relatively simple, to the powerful and complex, yet still

selecting a Microchip device.

 2010 Microchip Technology Inc.

DS39940D-page 9

PIC24FJ64GB004 FAMILY

• Parallel Master/Enhanced Parallel Slave Port:

One of the general purpose I/O ports can be

reconfigured for enhanced parallel data communi-

cations. In this mode, the port can be configured

for both master and slave operations, and

1.2

USB On-The-Go

The PIC24FJ64GB004 family of devices introduces

USB On-The-Go functionality on a single chip to lower

pin count Microchip devices. This module provides

on-chip functionality as a target device compatible with

the USB 2.0 standard, as well as limited stand-alone

functionality as a USB embedded host. By implement-

ing USB Host Negotiation Protocol (HNP), the module

can also dynamically switch between device and host

operation, allowing for a much wider range of versatile

supports 8-bit and 16-bit data transfers with up to

12 external address lines in Master modes.

• Real-Time Clock/Calendar: This module

implements a full-featured clock and calendar with

alarm functions in hardware, freeing up timer

resources and program memory space for the use

of the core application.

USB-enabled applications on

platform.

a

microcontroller

In addition to USB host functionality, PIC24FJ64GB004

family devices provide a true single chip USB solution,

including an on-chip transceiver and a voltage boost

generator for sourcing bus power during host

operations.

1.4

Details on Individual Family

Members

Devices in the PIC24FJ64GB004 family are available

in 28-pin and 44-pin packages. The general block

diagram for all devices is shown in Figure 1-1.

1.3

Other Special Features

The devices are differentiated from each other in

several ways:

• Peripheral Pin Select: The Peripheral Pin Select

feature allows most digital peripherals to be

mapped over a fixed set of digital I/O pins. Users

may independently map the input and/or output of

any one of the many digital peripherals to any one

of the I/O pins.

• Flash Program Memory:

- PIC24FJ32GB0 devices – 32 Kbytes

- PIC24FJ64GB0 devices – 64 Kbytes

• Available I/O Pins and Ports:

- 28-pin devices – 19 pins on two ports

- 44-pin devices – 33 pins on three ports

• Communications: The PIC24FJ64GB004 family

incorporates a range of serial communication

peripherals to handle a range of application

requirements. There are two independent I²C™

modules that support both Master and Slave

modes of operation. Devices also have, through

the Peripheral Pin Select (PPS) feature, two

independent UARTs with built-in IrDA^®

• Available Interrupt-on-Change Notification (ICN)

Inputs:

- 28-pin devices – 19

- 44-pin devices – 29

• Available Remappable Pins:

- 28-pin devices – 15 pins

- 44-pin devices – 25 pins

• Available PMP Address Pins:

- 28-pin devices – 3 pins

- 44-pin devices – 12 pins

• Available A/D Input Channels:

- 28-pin devices – 9 pins

- 44-pin devices – 12 pins

encoder/decoders and two SPI modules.

• Analog Features: All members of the

PIC24FJ64GB004 family include a 10-bit A/D

Converter module and a triple comparator

module. The A/D module incorporates program-

mable acquisition time, allowing for a channel to

be selected and a conversion to be initiated

without waiting for a sampling period, as well as

faster sampling speeds. The comparator module

includes three analog comparators that are

configurable for a wide range of operations.

All other features for devices in this family are identical.

These are summarized in Table 1-1.

• CTMU Interface: This module provides a

convenient method for precision time measure-

ment and pulse generation, and can serve as an

interface for capacitive sensors.

A

list of the pin features available on the

PIC24FJ64GB004 family devices, sorted by function, is

shown in Table 1-2. Note that this table shows the pin

location of individual peripheral features and not how

they are multiplexed on the same pin. This information

is provided in the pinout diagrams in the beginning of

this data sheet. Multiplexed features are sorted by the

priority given to a feature, with the highest priority

peripheral being listed first.

DS39940D-page 10

 2010 Microchip Technology Inc.

PIC24FJ64GB004 FAMILY

TABLE 1-1:

DEVICE FEATURES FOR THE PIC24FJ64GB004 FAMILY

Features

PIC24FJ32GB002 PIC24FJ64GB002 PIC24FJ32GB004 PIC24FJ64GB004

Operating Frequency

DC – 32 MHz

Program Memory (bytes)

Program Memory (instructions)

Data Memory (bytes)

32K

64K

32K

64K

11,008

22,016

11,008

22,016

8,192

Interrupt Sources (soft vectors/

NMI traps)

45 (41/4)

I/O Ports

Ports A and B

Ports A, B, C

Total I/O Pins

19

15

33

25

Remappable Pins

Timers:

Total Number (16-bit)

32-Bit (from paired 16-bit timers)

Input Capture Channels

Output Compare/PWM Channels

Input Change Notification Interrupt

Serial Communications:

UART

5⁽¹⁾

2

5⁽¹⁾

19

29

2⁽¹⁾

2

SPI (3-wire/4-wire)

I²C™

Parallel Communications (PMP/PSP)

JTAG Boundary Scan

Yes

10-Bit Analog-to-Digital Module

(input channels)

9

13

Analog Comparators

CTMU Interface

3

Yes

Resets (and delays)

POR, BOR, RESETInstruction, MCLR, WDT, Illegal Opcode,

REPEATInstruction, Hardware Traps, Configuration Word Mismatch

(PWRT, OST, PLL Lock)

Instruction Set

Packages

76 Base Instructions, Multiple Addressing Mode Variations

28-Pin QFN, SOIC, SSOP and SPDIP

44-Pin QFN and TQFP

Note 1: Peripherals are accessible through remappable pins.

 2010 Microchip Technology Inc.

DS39940D-page 11

PIC24FJ64GB004 FAMILY

FIGURE 1-1:

PIC24FJ64GB004 FAMILY GENERAL BLOCK DIAGRAM

Data Bus

Interrupt

Controller

PORTA⁽¹⁾

(9 I/O)

16

8

Data Latch

Data RAM

PSV & Table

Data Access

Control Block

PCH

PCL

23

Program Counter

Address

Latch

PORTB

(14 I/O)

Stack

Control

Logic

Repeat

Control

Logic

16

23

16

Read AGU

Write AGU

Address Latch

Program Memory

Data Latch

PORTC⁽¹⁾

(10 I/O)

16

EA MUX

Address Bus

24

16

Inst Latch

RP⁽¹⁾

Inst Register

RP0:RP25

Instruction

Decode &

Control

Divide

Support

Control Signals

16 x 16

W Reg Array

OSCO/CLKO

OSCI/CLKI

17 x 17

Multiplier

Power-up

Timer

Timing

Generation

Oscillator

Start-up Timer

FRC/LPRC

Oscillators

REFO

16-Bit ALU

Power-on

Reset

16

Precision

Band Gap

Reference

Watchdog

Timer

DISVREG

BOR and

LVD⁽²⁾

Voltage

Regulator

VDDCORE/VCAP

VDD,VSS

MCLR

10-Bit

Timer2/3⁽³⁾

Comparators⁽³⁾

USB OTG

Timer4/5⁽³⁾

RTCC

Timer1

ADC

PMP/PSP

PWM/OC

1-5⁽³⁾

SPI

1/2⁽³⁾

IC

1-5⁽³⁾

UART

1/2⁽³⁾

I2C

1/2

ICNs⁽¹⁾

CTMU

Note 1: Not all I/O pins or features are implemented on all device pinout configurations. See Table 1-2 for specific implementations by pin count

.

2: BOR functionality is provided when the on-board voltage regulator is enabled.

3: These peripheral I/Os are only accessible through remappable pins.

DS39940D-page 12

 2010 Microchip Technology Inc.

PIC24FJ64GB004 FAMILY

TABLE 1-2:

PIC24FJ64GB004 FAMILY PINOUT DESCRIPTIONS

Pin Number

Input

Buffer

28-Pin

SPDIP/

SOIC/SSOP

Function

I/O

Description

28-Pin

QFN

44-Pin

QFN/TQFP

AN0

2

3

27

28

1

19

20

21

22

23

24

25

26

27

15

14

11

36

20

19

17

16

24

23

11

30

22

21

34

33

15

14

19

20

30

31

I

ANA

A/D Analog Inputs.

AN1

I

AN2

4

I

AN3

5

2

I

AN4

6

3

I

AN5

7

4

I

AN6

—

26

25

24

—

3

—

23

22

21

—

28

27

—

4

I

AN7

I

AN8

I

AN9

I

AN10

AN11

AN12

ASCL1

ASDA1

AVDD

AVSS

C1INA

C1INB

C1INC

C1IND

C2INA

C2INB

C2INC

C2IND

C3INA

C3INB

C3INC

C3IND

CLKI

I

2

I/O

I C

Alternate I2C1 Synchronous Serial Clock Input/Output.

Alternate I2C1 Synchronous Serial Data Input/Output.

Positive Supply for Analog modules.

Ground Reference for Analog modules.

Comparator 1 Input A.

2

I/O

I C

—

7

P

I

—

ANA

—

6

3

I

Comparator 1 Input B.

24

9

21

6

I

Comparator 1 Input C.

I

Comparator 1 Input D.

5

2

I

Comparator 2 Input A.

4

1

I

Comparator 2 Input B.

12

11

26

25

2

9

I

Comparator 2 Input C.

8

I

Comparator 2 Input D.

23

22

27

28

6

I

Comparator 3 Input A.

I

Comparator 3 Input B.

I

Comparator 3 Input C.

3

I

Comparator 3 Input D.

9

I

Main Clock Input Connection.

System Clock Output.

CLKO

10

7

O

Legend:

TTL = TTL input buffer

ANA = Analog level input/output

ST = Schmitt Trigger input buffer

I C™ = I C/SMBus input buffer

2

 2010 Microchip Technology Inc.

DS39940D-page 13

PIC24FJ64GB004 FAMILY

TABLE 1-2:

PIC24FJ64GB004 FAMILY PINOUT DESCRIPTIONS (CONTINUED)

Pin Number

Input

Buffer

28-Pin

SPDIP/

SOIC/SSOP

Function

I/O

Description

28-Pin

QFN

44-Pin

QFN/TQFP

CN0

12

11

2

9

8

34

33

19

20

21

22

23

24

25

26

27

15

14

11

9

I

ST

ANA

—

Interrupt-on-Change Inputs.

CN1

I

CN2

27

28

1

I

CN3

3

I

CN4

4

I

CN5

5

2

I

CN6

6

3

I

CN7

7

4

I

CN8

—

26

25

24

22

21

—

18

17

16

—

14

—

10

9

—

23

22

21

19

18

—

15

14

13

—

11

—

7

I

CN9

I

CN10

CN11

CN12

CN13

CN15

CN16

CN17

CN18

CN19

CN20

CN21

CN22

CN23

CN25

CN26

CN27

CN28

CN29

CN30

CTED1

CTED2

CVREF

D+

I

8

I

3

I

2

I

5

I

4

I

1

I

44

43

37

38

41

36

31

30

19

20

14

8

I

6

I

2

27

28

22

18

19

2

I

CTMU External Edge Input 1.

3

I

CTMU External Edge Input 2.

25

21

22

5

O

I/O

O

I

Comparator Voltage Reference Output.

USB Differential Plus Line (internal transceiver).

USB Differential Minus Line (internal transceiver).

D- External Pull-up Control Output.

D- External Pull-down Control Output.

D+ External Pull-up Control Output.

D+ External Pull-down Control Output.

Voltage Regulator Disable.

—

D-

9

—

DMH

DMLN

DPH

22

24

21

23

6

—

7

4

—

4

1

—

DPLN

DISVREG

6

3

—

19

16

ST

Legend:

TTL = TTL input buffer

ANA = Analog level input/output

ST = Schmitt Trigger input buffer

I C™ = I C/SMBus input buffer

2

DS39940D-page 14

 2010 Microchip Technology Inc.

PIC24FJ64GB004 FAMILY

TABLE 1-2:

PIC24FJ64GB004 FAMILY PINOUT DESCRIPTIONS (CONTINUED)

Pin Number

Input

Buffer

28-Pin

SPDIP/

SOIC/SSOP

Function

I/O

Description

28-Pin

QFN

44-Pin

QFN/TQFP

INT0

16

1

13

26

43

18

I

ST

External Interrupt Input.

MCLR

Master Clear (device Reset) Input. This line is brought low to

cause a Reset.

OSCI

9

10

5

6

7

30

31

22

21

9

I

ANA

ST

Main Oscillator Input Connection.

OSCO

PGEC1

PGED1

PGEC2

PGED2

PGEC3

PGED3

PMA0

O

Main Oscillator Output Connection.

2

I/O

In-Circuit Debugger/Emulator/ICSP™ Programming Clock.

In-Circuit Debugger/Emulator/ICSP Programming Data.

In-Circuit Debugger/Emulator/ICSP Programming Clock.

In-Circuit Debugger/Emulator/ICSP Programming Data.

In-Circuit Debugger/Emulator/ICSP Programming Clock.

In-Circuit Debugger/Emulator/ICSP Programming Data.

4

1

ST

22

21

3

19

18

28

27

7

ST

8

ST

20

19

3

ST

2

ST

10

ST

Parallel Master Port Address Bit 0 Input (Buffered Slave

modes) and Output (Master modes).

PMA1

12

9

2

I/O

ST

Parallel Master Port Address Bit 1 Input (Buffered Slave

modes) and Output (Master modes).

PMA2

PMA3

PMA4

PMA5

PMA6

PMA7

PMA8

PMA9

PMA10

PMCS1

PMBE

PMD0

PMD1

PMD2

PMD3

PMD4

PMD5

PMD6

PMD7

PMRD

PMWR

—

9

—

6

27

38

37

4

O

—

Parallel Master Port Address (Demultiplexed Master modes).

O

5

O

13

32

35

12

30

36

21

22

23

1

O

I/O

O

ST/TTL Parallel Master Port Chip Select 1 Strobe/Address Bit 15.

Parallel Master Port Byte Enable Strobe.

11

4

8

—

1

I/O

O

ST/TTL Parallel Master Port Data (Demultiplexed Master mode) or

Address/Data (Multiplexed Master modes).

5

2

ST/TTL

6

3

ST/TTL

18

17

16

3

15

14

13

28

27

21

4

44

43

20

19

11

24

2

24

7

—

Parallel Master Port Read Strobe.

Parallel Master Port Write Strobe.

O

Legend:

TTL = TTL input buffer

ANA = Analog level input/output

ST = Schmitt Trigger input buffer

I C™ = I C/SMBus input buffer

2

 2010 Microchip Technology Inc.

DS39940D-page 15

PIC24FJ64GB004 FAMILY

TABLE 1-2:

PIC24FJ64GB004 FAMILY PINOUT DESCRIPTIONS (CONTINUED)

Pin Number

Input

Buffer

28-Pin

SPDIP/

SOIC/SSOP

Function

I/O

Description

28-Pin

QFN

44-Pin

QFN/TQFP

RA0

RA1

RA2

RA3

RA4

RA7

RA8

RA9

RA10

RB0

RB1

RB2

RB3

RB4

RB5

RB7

RB8

RB9

RB10

RB11

RB13

RB14

RB15

RC0

RC1

RC2

RC3

RC4

RC5

RC6

RC7

RC8

RC9

RCV

REFO

2

27

28

6

19

20

30

31

34

13

32

35

12

21

22

23

24

33

41

43

44

1

I/O

I

ST

—

PORTA Digital I/O.

3

9

10

12

—

4

7

9

—

1

PORTB Digital I/O.

5

2

6

3

7

4

11

14

16

17

18

21

22

24

25

26

—

18

24

8

11

13

14

15

18

19

21

22

23

—

15

21

8

9

11

14

15

25

26

27

36

37

38

2

PORTC Digital I/O.

3

4

5

1

USB Receive Input (from external transceiver).

Reference Clock Output.

11

O

Legend:

TTL = TTL input buffer

ANA = Analog level input/output

ST = Schmitt Trigger input buffer

I C™ = I C/SMBus input buffer

2

DS39940D-page 16

 2010 Microchip Technology Inc.

PIC24FJ64GB004 FAMILY

TABLE 1-2:

PIC24FJ64GB004 FAMILY PINOUT DESCRIPTIONS (CONTINUED)

Pin Number

Input

Buffer

28-Pin

SPDIP/

SOIC/SSOP

Function

I/O

Description

28-Pin

QFN

44-Pin

QFN/TQFP

RP0

4

1

21

22

23

24

33

19

20

43

44

1

I/O

O

ST

—

Remappable Peripheral (input or output).

RP1

5

2

RP2

6

3

RP3

7

4

RP4

11

2

8

RP5

27

28

13

14

15

18

19

21

22

23

—

4

RP6

3

RP7

16

17

18

21

22

24

25

26

—

7

RP8

RP9

RP10

RP11

RP13

RP14

RP15

RP16

RP17

RP18

RP19

RP20

RP21

RP22

RP23

RP24

RP25

RTCC

SESSEND

SESSVLD

SCL1

SCL2

SDA1

SDA2

SOSCI

SOSCO

T1CK

TCK

8

9

11

14

15

25

26

27

36

37

38

2

3

4

5

24

11

20

44

24

1

Real-Time Clock Alarm/Seconds Pulse Output.

USB VBUS Session End Status Input.

USB VBUS Session Valid Status Input.

I2C1 Synchronous Serial Clock Input/Output.

I2C2 Synchronous Serial Clock Input/Output.

I2C1 Data Input/Output.

24

3

21

28

14

4

I

ST

I

2

17

7

I/O

I

I C

2

I C

2

18

6

15

3

I C

2

23

33

34

13

35

32

12

41

44

I C

I2C2 Data Input/Output.

11

12

17

16

18

14

17

8

ANA

ST

—

Secondary Oscillator/Timer1 Clock Input.

Secondary Oscillator/Timer1 Clock Output.

Timer1 Clock Input.

9

O

9

I

14

13

15

11

14

I

JTAG Test Clock Input.

TDI

I

JTAG Test Data Input.

TDO

O

JTAG Test Data Output.

TMS

I

ST

—

JTAG Test Mode Select Input.

USBID

USBOEN

I

USB OTG ID (OTG mode only).

USB Output Enable Control (for external transceiver).

O

Legend:

TTL = TTL input buffer

ANA = Analog level input/output

ST = Schmitt Trigger input buffer

I C™ = I C/SMBus input buffer

2

 2010 Microchip Technology Inc.

DS39940D-page 17

PIC24FJ64GB004 FAMILY

TABLE 1-2:

PIC24FJ64GB004 FAMILY PINOUT DESCRIPTIONS (CONTINUED)

Pin Number

Input

Buffer

28-Pin

SPDIP/

SOIC/SSOP

Function

I/O

Description

28-Pin

QFN

44-Pin

QFN/TQFP

VBUS

15

26

12

23

42

15

P

O

I

—

USB Voltage, Host mode (5V).

VBUSCHG

VBUSON

VBUSST

VBUSVLD

VCAP

USB External VBUS Control Output

25

22

14

—

USB OTG External Charge Pump Control.

USB OTG Internal Charge Pump Feedback Control.

USB VBUS Valid Status Input.

26

23

15

ANA

ST

—

2

27

19

I

20

17

7

P

O

P

External Filter Capacitor Connection (regulator enabled).

USB OTG VBUS PWM/Charge Output.

VCPCON

VDD

25

22

14

—

13, 28

20

10, 25

17

28, 40

7

—

Positive Supply for Peripheral Digital Logic and I/O Pins.

VDDCORE

—

Positive Supply for Microcontroller Core Logic (regulator

disabled).

VMIO

VPIO

VREF-

VREF+

VSS

22

21

3

19

18

9

8

I/O

I

ST

USB Differential Minus Input/Output (external transceiver).

USB Differential Plus Input/Output (external transceiver).

A/D and Comparator Reference Voltage (low) Input.

A/D and Comparator Reference Voltage (high) Input.

Ground Reference for Logic and I/O Pins.

28

20

ANA

—

2

27

19

I

8, 27

23

5, 24

20

29, 39

10

P

VUSB

P

—

USB Voltage (3.3V).

Legend:

TTL = TTL input buffer

ANA = Analog level input/output

ST = Schmitt Trigger input buffer

I C™ = I C/SMBus input buffer

2

DS39940D-page 18

 2010 Microchip Technology Inc.

PIC24FJ64GB004 FAMILY

FIGURE 2-1:

RECOMMENDED

MINIMUM CONNECTIONS

2.0

2.1

GUIDELINES FOR GETTING

STARTED WITH 16-BIT

MICROCONTROLLERS

(2)

C2

VDD

Basic Connection Requirements

Getting started with the PIC24FJ64GB004 family of

16-bit microcontrollers requires attention to a minimal

set of device pin connections before proceeding with

development.

(1)

R1

R2

(EN/DIS)VREG

VCAP/VDDCORE

MCLR

C1

The following pins must always be connected:

C7

PIC24FXXXX

• All VDD and VSS pins

(see Section 2.2 “Power Supply Pins”)

VDD

VSS

VDD

(2)

C3

C6

• All AVDD and AVSS pins, regardless of whether or

not the analog device features are used

(see Section 2.2 “Power Supply Pins”)

• MCLR pin

(see Section 2.3 “Master Clear (MCLR) Pin”)

(2)

C4

C5

• ENVREG/DISVREG and VCAP/VDDCORE pins

(PIC24FJ devices only)

(see Section 2.4 “Voltage Regulator Pins

(ENVREG/DISVREG and VCAP/VDDCORE)”)

Key (all values are recommendations):

C1 through C6: 0.1 F, 20V ceramic

These pins must also be connected if they are being

used in the end application:

C7: 10 F, 6.3V or greater, tantalum or ceramic

R1: 10 kΩ

• PGECx/PGEDx pins used for In-Circuit Serial

Programming™ (ICSP™) and debugging purposes

(see Section 2.5 “ICSP Pins”)

R2: 100Ω to 470Ω

Note 1: See Section 2.4 “Voltage Regulator Pins

(ENVREG/DISVREG and VCAP/VDDCORE)”

for explanation of ENVREG/DISVREG pin

connections.

• OSCI and OSCO pins when an external oscillator

source is used

(see Section 2.6 “External Oscillator Pins”)

2: The example shown is for a PIC24F device

with five VDD/VSS and AVDD/AVSS pairs.

Other devices may have more or less pairs;

adjust the number of decoupling capacitors

appropriately.

Additionally, the following pins may be required:

• VREF+/VREF- pins used when external voltage

reference for analog modules is implemented

Note:

The AVDD and AVSS pins must always be

connected, regardless of whether any of

the analog modules are being used.

The minimum mandatory connections are shown in

Figure 2-1.

 2010 Microchip Technology Inc.

DS39940D-page 19

PIC24FJ64GB004 FAMILY

2.2

Power Supply Pins

2.3

Master Clear (MCLR) Pin

The MCLR pin provides two specific device

functions: device Reset, and device programming

and debugging. If programming and debugging are

2.2.1

DECOUPLING CAPACITORS

The use of decoupling capacitors on every pair of

power supply pins, such as VDD, VSS, AVDD and

AVSS is required.

not required in the end application,

a

direct

connection to VDD may be all that is required. The

addition of other components, to help increase the

application’s resistance to spurious Resets from

Consider the following criteria when using decoupling

capacitors:

voltage sags, may be beneficial.

A

typical

• Value and type of capacitor: A 0.1 F (100 nF),

10-20V capacitor is recommended. The capacitor

should be a low-ESR device with a resonance

frequency in the range of 200 MHz and higher.

Ceramic capacitors are recommended.

configuration is shown in Figure 2-1. Other circuit

designs may be implemented, depending on the

application’s requirements.

During programming and debugging, the resistance

and capacitance that can be added to the pin must

be considered. Device programmers and debuggers

drive the MCLR pin. Consequently, specific voltage

levels (VIH and VIL) and fast signal transitions must

not be adversely affected. Therefore, specific values

of R1 and C1 will need to be adjusted based on the

application and PCB requirements. For example, it is

recommended that the capacitor, C1, be isolated

from the MCLR pin during programming and

debugging operations by using a jumper (Figure 2-2).

The jumper is replaced for normal run-time

operations.

• Placement on the printed circuit board: The

decoupling capacitors should be placed as close

to the pins as possible. It is recommended to

place the capacitors on the same side of the

board as the device. If space is constricted, the

capacitor can be placed on another layer on the

PCB using a via; however, ensure that the trace

length from the pin to the capacitor is no greater

than 0.25 inch (6 mm).

• Handling high-frequency noise: If the board is

experiencing high-frequency noise (upward of

tens of MHz), add a second ceramic type capaci-

tor in parallel to the above described decoupling

capacitor. The value of the second capacitor can

be in the range of 0.01 F to 0.001 F. Place this

second capacitor next to each primary decoupling

capacitor. In high-speed circuit designs, consider

implementing a decade pair of capacitances as

close to the power and ground pins as possible

(e.g., 0.1 F in parallel with 0.001 F).

Any components associated with the MCLR pin

should be placed within 0.25 inch (6 mm) of the pin.

FIGURE 2-2:

EXAMPLE OF MCLR PIN

CONNECTIONS

VDD

• Maximizing performance: On the board layout

from the power supply circuit, run the power and

return traces to the decoupling capacitors first,

and then to the device pins. This ensures that the

decoupling capacitors are first in the power chain.

Equally important is to keep the trace length

between the capacitor and the power pins to a

minimum, thereby reducing PCB trace

R1

R2

MCLR

PIC24FXXXX

JP

C1

inductance.

Note 1: R1  10 k is recommended. A suggested

starting value is 10 k. Ensure that the

MCLR pin VIH and VIL specifications are met.

2.2.2

TANK CAPACITORS

On boards with power traces running longer than six

inches in length, it is suggested to use a tank capacitor

for integrated circuits including microcontrollers to

supply a local power source. The value of the tank

capacitor should be determined based on the trace

resistance that connects the power supply source to

the device, and the maximum current drawn by the

device in the application. In other words, select the tank

capacitor so that it meets the acceptable voltage sag at

the device. Typical values range from 4.7 F to 47 F.

2: R2  470 will limit any current flowing into

MCLR from the external capacitor, C, in the

event of MCLR pin breakdown, due to

Electrostatic Discharge (ESD) or Electrical

Overstress (EOS). Ensure that the MCLR pin

VIH and VIL specifications are met.

DS39940D-page 20

 2010 Microchip Technology Inc.

PIC24FJ64GB004 FAMILY

FIGURE 2-3:

FREQUENCY vs. ESR

PERFORMANCE FOR

SUGGESTED VCAP

2.4

Voltage Regulator Pins

(ENVREG/DISVREG and

VCAP/VDDCORE)

10

1

Note:

This section applies only to PIC24FJ

devices with an on-chip voltage regulator.

The on-chip voltage regulator enable/disable pin

(ENVREG or DISVREG, depending on the device

family) must always be connected directly to either a

supply voltage or to ground. The particular connection

is determined by whether or not the regulator is to be

used:

0.1

0.01

• For ENVREG, tie to VDD to enable the regulator,

or to ground to disable the regulator

0.001

0.01

0.1

1

10

100

1000 10,000

Frequency (MHz)

• For DISVREG, tie to ground to enable the

regulator or to VDD to disable the regulator

Note:

Data for Murata GRM21BF50J106ZE01 shown.

Measurements at 25°C, 0V DC bias.

Refer to Section 26.2 “On-Chip Voltage Regulator”

for details on connecting and using the on-chip

regulator.

2.5

ICSP Pins

When the regulator is enabled, a low-ESR (<5Ω)

capacitor is required on the VCAP/VDDCORE pin to

stabilize the voltage regulator output voltage. The

VCAP/VDDCORE pin must not be connected to VDD, and

must use a capacitor of 10 F connected to ground. The

type can be ceramic or tantalum. A suitable example is

the Murata GRM21BF50J106ZE01 (10 F, 6.3V) or

equivalent. Designers may use Figure 2-3 to evaluate

ESR equivalence of candidate devices.

The PGECx and PGEDx pins are used for In-Circuit

Serial Programming (ICSP) and debugging purposes.

It is recommended to keep the trace length between

the ICSP connector and the ICSP pins on the device as

short as possible. If the ICSP connector is expected to

experience an ESD event, a series resistor is recom-

mended, with the value in the range of a few tens of

ohms, not to exceed 100Ω.

Pull-up resistors, series diodes and capacitors on the

PGECx and PGEDx pins are not recommended as they

will interfere with the programmer/debugger communi-

cations to the device. If such discrete components are

an application requirement, they should be removed

from the circuit during programming and debugging.

Alternatively, refer to the AC/DC characteristics and

timing requirements information in the respective

device Flash programming specification for information

on capacitive loading limits and pin input voltage high

(VIH) and input low (VIL) requirements.

The placement of this capacitor should be close to

VCAP/VDDCORE. It is recommended that the trace

length not exceed 0.25 inch (6 mm). Refer to

Section 29.0 “Electrical Characteristics” for

additional information.

When the regulator is disabled, the VCAP/VDDCORE pin

must be tied to a voltage supply at the VDDCORE level.

Refer to Section 29.0 “Electrical Characteristics” for

information on VDD and VDDCORE.

For device emulation, ensure that the “Communication

Channel Select” (i.e., PGECx/PGEDx pins) programmed

into the device matches the physical connections for the

ICSP to the Microchip debugger/emulator tool.

For more information on available Microchip

development tools connection requirements, refer to

Section 27.0 “Development Support”.

 2010 Microchip Technology Inc.

DS39940D-page 21

PIC24FJ64GB004 FAMILY

FIGURE 2-4:

SUGGESTED PLACEMENT

OF THE OSCILLATOR

CIRCUIT

2.6

External Oscillator Pins

Many microcontrollers have options for at least two

oscillators: a high-frequency primary oscillator and a

low-frequency

secondary

oscillator

(refer to

Single-Sided and In-line Layouts:

Section 8.0 “Oscillator Configuration” for details).

Copper Pour

(tied to ground)

Primary Oscillator

Crystal

The oscillator circuit should be placed on the same

side of the board as the device. Place the oscillator

circuit close to the respective oscillator pins with no

more than 0.5 inch (12 mm) between the circuit

components and the pins. The load capacitors should

be placed next to the oscillator itself, on the same side

of the board.

DEVICE PINS

Primary

OSCI

OSCO

GND

Oscillator

C1

C2

`

Use a grounded copper pour around the oscillator cir-

cuit to isolate it from surrounding circuits. The

grounded copper pour should be routed directly to the

MCU ground. Do not run any signal traces or power

traces inside the ground pour. Also, if using a two-sided

board, avoid any traces on the other side of the board

where the crystal is placed.

SOSCO

SOSC I

Secondary

Oscillator

Crystal

`

Layout suggestions are shown in Figure 2-4. In-line

packages may be handled with a single-sided layout

that completely encompasses the oscillator pins. With

fine-pitch packages, it is not always possible to com-

pletely surround the pins and components. A suitable

solution is to tie the broken guard sections to a mirrored

ground layer. In all cases, the guard trace(s) must be

returned to ground.

Sec Oscillator: C2

Sec Oscillator: C1

Fine-Pitch (Dual-Sided) Layouts:

Top Layer Copper Pour

(tied to ground)

In planning the application’s routing and I/O assign-

ments, ensure that adjacent port pins and other signals

in close proximity to the oscillator are benign (i.e., free

of high frequencies, short rise and fall times and other

similar noise).

Bottom Layer

Copper Pour

(tied to ground)

OSCO

For additional information and design guidance on

oscillator circuits, please refer to these Microchip

Application Notes, available at the corporate web site

(www.microchip.com):

C2

Oscillator

Crystal

GND

• AN826, “Crystal Oscillator Basics and Crystal

Selection for rfPIC™ and PICmicro^®Devices”

C1

• AN849, “Basic PICmicro^®Oscillator Design”

OSCI

• AN943, “Practical PICmicro^®Oscillator Analysis

and Design”

• AN949, “Making Your Oscillator Work”

DEVICE PINS

DS39940D-page 22

 2010 Microchip Technology Inc.

PIC24FJ64GB004 FAMILY

If your application needs to use certain A/D pins as

analog input pins during the debug session, the user

application must modify the appropriate bits during

initialization of the ADC module, as follows:

2.7

Configuration of Analog and

Digital Pins During ICSP

Operations

If an ICSP compliant emulator is selected as a debug-

ger, it automatically initializes all of the A/D input pins

(ANx) as “digital” pins. Depending on the particular

device, this is done by setting all bits in the ADnPCFG

register(s), or clearing all bit in the ANSx registers.

• For devices with an ADnPCFG register, clear the

bits corresponding to the pin(s) to be configured

as analog. Do not change any other bits, particu-

larly those corresponding to the PGECx/PGEDx

pair, at any time.

All PIC24F devices will have either one or more

ADnPCFG registers or several ANSx registers (one for

each port); no device will have both. Refer to

Section 10.2 “Configuring Analog Port Pins” for

more specific information.

• For devices with ANSx registers, set the bits

corresponding to the pin(s) to be configured as

analog. Do not change any other bits, particularly

those corresponding to the PGECx/PGEDx pair,

at any time.

The bits in these registers that correspond to the A/D

pins that initialized the emulator must not be changed

by the user application firmware; otherwise,

communication errors will result between the debugger

and the device.

When a Microchip debugger/emulator is used as a

programmer, the user application firmware must

correctly configure the ADnPCFG or ANSx registers.

Automatic initialization of this register is only done

during debugger operation. Failure to correctly

configure the register(s) will result in all A/D pins being

recognized as analog input pins, resulting in the port

value being read as a logic '0', which may affect user

application functionality.

2.8

Unused I/Os

Unused I/O pins should be configured as outputs and

driven to a logic low state. Alternatively, connect a 1 kΩ

to 10 kΩ resistor to VSS on unused pins and drive the

output to logic low.

 2010 Microchip Technology Inc.

DS39940D-page 23

PIC24FJ64GB004 FAMILY

NOTES:

DS39940D-page 24

 2010 Microchip Technology Inc.

PIC24FJ64GB004 FAMILY

For most instructions, the core is capable of executing

a data (or program data) memory read, a working reg-

3.0

CPU

Note:

This data sheet summarizes the features

of this group of PIC24F devices. It is not

intended to be a comprehensive reference

source. For more information, refer to the

“PIC24F Family Reference Manual”,

Section 2. “CPU” (DS39703).

ister (data) read, a data memory write and a program

(instruction) memory read per instruction cycle. As a

result, three parameter instructions can be supported,

allowing trinary operations (that is, A + B = C) to be

executed in a single cycle.

A high-speed, 17-bit by 17-bit multiplier has been

included to significantly enhance the core arithmetic

capability and throughput. The multiplier supports

Signed, Unsigned and Mixed mode, 16-bit by 16-bit or

8-bit by 8-bit integer multiplication. All multiply

instructions execute in a single cycle.

The PIC24F CPU has a 16-bit (data), modified Harvard

architecture with an enhanced instruction set and a

24-bit instruction word with a variable length opcode

field. The Program Counter (PC) is 23 bits wide and

addresses up to 4M instructions of user program

memory space. A single-cycle instruction prefetch

mechanism is used to help maintain throughput and

provides predictable execution. All instructions execute

in a single cycle, with the exception of instructions that

change the program flow, the double-word move

(MOV.D) instruction and the table instructions.

Overhead-free program loop constructs are supported

using the REPEATinstructions, which are interruptible at

any point.

The 16-bit ALU has been enhanced with integer divide

assist hardware that supports an iterative non-restoring

divide algorithm. It operates in conjunction with the

REPEATinstruction looping mechanism and a selection

of iterative divide instructions to support 32-bit (or

16-bit), divided by 16-bit, integer signed and unsigned

division. All divide operations require 19 cycles to

complete, but are interruptible at any cycle boundary.

The PIC24F has a vectored exception scheme with up to

8 sources of non-maskable traps and up to 118 interrupt

sources. Each interrupt source can be assigned to one of

seven priority levels.

PIC24F devices have sixteen, 16-bit working registers

in the programmer’s model. Each of the working

registers can act as a data, address or address offset

register. The 16th working register (W15) operates as

a Software Stack Pointer for interrupts and calls.

A block diagram of the CPU is shown in Figure 3-1.

The upper 32 Kbytes of the data space memory map

can optionally be mapped into program space at any

16K word boundary defined by the 8-bit Program Space

Visibility Page Address (PSVPAG) register. The program

to data space mapping feature lets any instruction

access program space as if it were data space.

3.1

Programmer’s Model

The programmer’s model for the PIC24F is shown in

Figure 3-2. All registers in the programmer’s model are

memory mapped and can be manipulated directly by

instructions. A description of each register is provided

in Table 3-1. All registers associated with the

programmer’s model are memory mapped.

The Instruction Set Architecture (ISA) has been

significantly enhanced beyond that of the PIC18, but

maintains an acceptable level of backward compatibility.

All PIC18 instructions and addressing modes are

supported either directly or through simple macros.

Many of the ISA enhancements have been driven by

compiler efficiency needs.

The core supports Inherent (no operand), Relative,

Literal, Memory Direct and three groups of addressing

modes. All modes support Register Direct and various

Register Indirect modes. Each group offers up to seven

addressing modes. Instructions are associated with

predefined addressing modes depending upon their

functional requirements.

 2010 Microchip Technology Inc.

DS39940D-page 25

PIC24FJ64GB004 FAMILY

FIGURE 3-1:

PIC24F CPU CORE BLOCK DIAGRAM

PSV & Table

Data Access

Control Block

Data Bus

Interrupt

Controller

16

8

Data Latch

Data RAM

23

16

PCH

Program Counter

PCL

23

Address

Latch

Loop

Control

Logic

Stack

Control

Logic

23

16

RAGU

WAGU

Address Latch

Program Memory

Data Latch

EA MUX

16

Address Bus

ROM Latch

24

16

Instruction

Decode &

Control

Instruction Reg

Control Signals

to Various Blocks

Hardware

Multiplier

16 x 16

W Register Array

Divide

16

Support

16-Bit ALU

16

To Peripheral Modules

DS39940D-page 26

 2010 Microchip Technology Inc.

PIC24FJ64GB004 FAMILY

TABLE 3-1:

CPU CORE REGISTERS

Register(s) Name

Description

W0 through W15

PC

Working Register Array

23-Bit Program Counter

SR

ALU STATUS Register

SPLIM

Stack Pointer Limit Value Register

Table Memory Page Address Register

Program Space Visibility Page Address Register

Repeat Loop Counter Register

CPU Control Register

TBLPAG

PSVPAG

RCOUNT

CORCON

FIGURE 3-2:

PROGRAMMER’S MODEL

15

0

W0 (WREG)

Divider Working Registers

Multiplier Registers

W1

W2

W3

W4

W5

W6

W7

Working/Address

Registers

W8

W9

W10

W11

W12

W13

W14

W15

Frame Pointer

Stack Pointer

0

Stack Pointer Limit

Value Register

0

SPLIM

22

0

PC

Program Counter

7

0

Table Memory Page

Address Register

TBLPAG

7

Program Space Visibility

Page Address Register

PSVPAG

15

Repeat Loop Counter

Register

RCOUNT

IPL

SRH

SRL

0

— — — — — — —

ALU STATUS Register (SR)

DC

RA N OV Z

C

2 1 0

15

0

— — — — — — — — — — — — IPL3 PSV — —

CPU Control Register (CORCON)

Registers or bits shaded for PUSH.Sand POP.Sinstructions.

 2010 Microchip Technology Inc.

DS39940D-page 27

PIC24FJ64GB004 FAMILY

3.2

CPU Control Registers

REGISTER 3-1:

SR: ALU STATUS REGISTER

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

R/W-0

DC

bit 15

bit 8

R/W-0⁽¹⁾

IPL2⁽²⁾

bit 7

R/W-0⁽¹⁾

IPL1⁽²⁾

R/W-0⁽¹⁾

IPL0⁽²⁾

R-0

RA

R/W-0

N

R/W-0

OV

R/W-0

Z

R/W-0

C

bit 0

Legend:

R = Readable bit

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

-n = Value at POR

bit 15-9

bit 8

Unimplemented: Read as ‘0’

DC: ALU Half Carry/Borrow bit

1= A carry out from the 4th low-order bit (for byte-sized data) or 8th low-order bit (for word-sized data)

of the result occurred

0= No carry out from the 4th or 8th low-order bit of the result has occurred

bit 7-5

IPL<2:0>: CPU Interrupt Priority Level Status bits^(1,2)

111= CPU interrupt priority level is 7 (15); user interrupts disabled

110= CPU interrupt priority level is 6 (14)

101= CPU interrupt priority level is 5 (13)

100= CPU interrupt priority level is 4 (12)

011= CPU interrupt priority level is 3 (11)

010= CPU interrupt priority level is 2 (10)

001= CPU interrupt priority level is 1 (9)

000= CPU interrupt priority level is 0 (8)

bit 4

bit 3

bit 2

bit 1

bit 0

RA: REPEATLoop Active bit

1= REPEATloop in progress

0= REPEATloop not in progress

N: ALU Negative bit

1= Result was negative

0= Result was non-negative (zero or positive)

OV: ALU Overflow bit

1= Overflow occurred for signed (2’s complement) arithmetic in this arithmetic operation

0= No overflow has occurred

Z: ALU Zero bit

1= An operation which effects the Z bit has set it at some time in the past

0= The most recent operation which effects the Z bit has cleared it (i.e., a non-zero result)

C: ALU Carry/Borrow bit

1= A carry out from the Most Significant bit of the result occurred

0= No carry out from the Most Significant bit of the result occurred

Note 1: The IPL Status bits are read-only when NSTDIS (INTCON1<15>) = 1.

2: The IPL Status bits are concatenated with the IPL3 bit (CORCON<3>) to form the CPU Interrupt Priority

Level (IPL). The value in parentheses indicates the IPL when IPL3 = 1.

DS39940D-page 28

 2010 Microchip Technology Inc.

PIC24FJ64GB004 FAMILY

REGISTER 3-2:

CORCON: CPU CONTROL REGISTER

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

bit 15

bit 8

bit 0

U-0

—

U-0

—

U-0

—

U-0

—

R/C-0

IPL3⁽¹⁾

R/W-0

PSV

U-0

—

U-0

—

bit 7

Legend:

C = Clearable bit

W = Writable bit

‘1’ = Bit is set

R = Readable bit

-n = Value at POR

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15-4

bit 3

Unimplemented: Read as ‘0’

IPL3: CPU Interrupt Priority Level Status bit⁽¹⁾

1= CPU interrupt priority level is greater than 7

0= CPU interrupt priority level is 7 or less

bit 2

PSV: Program Space Visibility in Data Space Enable bit

1= Program space visible in data space

0= Program space not visible in data space

bit 1-0

Unimplemented: Read as ‘0’

Note 1: User interrupts are disabled when IPL3 = 1.

The PIC24F CPU incorporates hardware support for

both multiplication and division. This includes a

dedicated hardware multiplier and support hardware

for 16-bit divisor division.

3.3

Arithmetic Logic Unit (ALU)

The PIC24F ALU is 16 bits wide and is capable of addi-

tion, subtraction, bit shifts and logic operations. Unless

otherwise mentioned, arithmetic operations are 2’s

complement in nature. Depending on the operation, the

ALU may affect the values of the Carry (C), Zero (Z),

Negative (N), Overflow (OV) and Digit Carry (DC)

Status bits in the SR register. The C and DC Status bits

operate as Borrow and Digit Borrow bits, respectively,

for subtraction operations.

3.3.1

MULTIPLIER

The ALU contains a high-speed, 17-bit x 17-bit

multiplier. It supports unsigned, signed or mixed sign

operation in several multiplication modes:

1. 16-bit x 16-bit signed

2. 16-bit x 16-bit unsigned

The ALU can perform 8-bit or 16-bit operations,

depending on the mode of the instruction that is used.

Data for the ALU operation can come from the W

register array, or data memory, depending on the

addressing mode of the instruction. Likewise, output

data from the ALU can be written to the W register array

or a data memory location.

3. 16-bit signed x 5-bit (literal) unsigned

4. 16-bit unsigned x 16-bit unsigned

5. 16-bit unsigned x 5-bit (literal) unsigned

6. 16-bit unsigned x 16-bit signed

7. 8-bit unsigned x 8-bit unsigned

 2010 Microchip Technology Inc.

DS39940D-page 29

PIC24FJ64GB004 FAMILY

3.3.2

DIVIDER

3.3.3

MULTI-BIT SHIFT SUPPORT

The divide block supports signed and unsigned integer

divide operations with the following data sizes:

The PIC24F ALU supports both single bit and

single-cycle, multi-bit arithmetic and logic shifts.

Multi-bit shifts are implemented using a shifter block,

capable of performing up to a 15-bit arithmetic right

shift, or up to a 15-bit left shift, in a single cycle. All

multi-bit shift instructions only support Register Direct

Addressing for both the operand source and result

destination.

1. 32-bit signed/16-bit signed divide

2. 32-bit unsigned/16-bit unsigned divide

3. 16-bit signed/16-bit signed divide

4. 16-bit unsigned/16-bit unsigned divide

The quotient for all divide instructions ends up in W0

and the remainder in W1. Sixteen-bit signed and

unsigned DIV instructions can specify any W register

for both the 16-bit divisor (Wn), and any W register

(aligned) pair (W(m + 1):Wm) for the 32-bit dividend.

The divide algorithm takes one cycle per bit of divisor,

so both 32-bit/16-bit and 16-bit/16-bit instructions take

the same number of cycles to execute.

A full summary of instructions that use the shift

operation is provided below in Table 3-2.

TABLE 3-2:

Instruction

INSTRUCTIONS THAT USE THE SINGLE AND MULTI-BIT SHIFT OPERATION

Description

ASR

SL

Arithmetic Shift Right Source Register by One or More Bits.

Shift Left Source Register by One or More Bits.

LSR

Logical Shift Right Source Register by One or More Bits.

DS39940D-page 30

 2010 Microchip Technology Inc.

PIC24FJ64GB004 FAMILY

from either the 23-bit Program Counter (PC) during pro-

gram execution, or from table operation or data space

remapping, as described in Section 4.3 “Interfacing

Program and Data Memory Spaces”.

4.0

MEMORY ORGANIZATION

As Harvard architecture devices, PIC24F micro-

controllers feature separate program and data memory

spaces and busses. This architecture also allows the

direct access of program memory from the data space

during code execution.

User access to the program memory space is restricted

to the lower half of the address range (000000h to

7FFFFFh). The exception is the use of TBLRD/TBLWT

operations which use TBLPAG<7> to permit access to

the Configuration bits and Device ID sections of the

configuration memory space.

4.1

Program Address Space

The program address memory space of the

PIC24FJ64GB004 family devices is 4M instructions.

The space is addressable by a 24-bit value derived

Memory maps for the PIC24FJ64GB004 family of

devices are shown in Figure 4-1.

FIGURE 4-1:

PROGRAM SPACE MEMORY MAP FOR PIC24FJ64GB004 FAMILY DEVICES

PIC24FJ32GB00X

PIC24FJ64GB00X

000000h

000002h

000004h

GOTOInstruction

Reset Address

GOTOInstruction

Reset Address

Interrupt Vector Table

Reserved

Interrupt Vector Table

Reserved

0000FEh

000100h

000104h

0001FEh

000200h

Alternate Vector Table

User Flash

Program Memory

(11K instructions)

User Flash

Program Memory

(22K instructions)

Flash Config Words

0057FEh

005800h

Flash Config Words

00ABFEh

00AC00h

Unimplemented

Read ‘0’

Unimplemented

Read ‘0’

7FFFFFh

800000h

Reserved

F7FFFEh

F80000h

Device Config Registers

Reserved

Device Config Registers

Reserved

F8000Eh

F80010h

FEFFFEh

FF0000h

DEVID (2)

FFFFFFh

Note:

Memory areas are not shown to scale.

 2010 Microchip Technology Inc.

DS39940D-page 31

PIC24FJ64GB004 FAMILY

4.1.1

PROGRAM MEMORY

ORGANIZATION

4.1.3

FLASH CONFIGURATION WORDS

In PIC24FJ64GB004 family devices, the top four words

of on-chip program memory are reserved for configura-

tion information. On device Reset, the configuration

information is copied into the appropriate Configuration

registers. The addresses of the Flash Configuration

Word for devices in the PIC24FJ64GB004 family are

shown in Table 4-1. Their location in the memory map

is shown with the other memory vectors in Figure 4-1.

The program memory space is organized in

word-addressable blocks. Although it is treated as

24 bits wide, it is more appropriate to think of each

address of the program memory as a lower and upper

word, with the upper byte of the upper word being

unimplemented. The lower word always has an even

address, while the upper word has an odd address

(Figure 4-2).

The Configuration Words in program memory are a

compact format. The actual Configuration bits are

mapped in several different registers in the configuration

memory space. Their order in the Flash Configuration

Words do not reflect a corresponding arrangement in the

configuration space. Additional details on the device

Configuration Words are provided in Section 26.1

“Configuration Bits”.

Program memory addresses are always word-aligned

on the lower word and addresses are incremented or

decremented by two during code execution. This

arrangement also provides compatibility with data

memory space addressing and makes it possible to

access data in the program memory space.

4.1.2

HARD MEMORY VECTORS

TABLE 4-1:

FLASH CONFIGURATION

WORDS FOR PIC24FJ64GB004

FAMILY DEVICES

All PIC24F devices reserve the addresses between

00000h and 000200h for hard-coded program execu-

tion vectors. A hardware Reset vector is provided to

redirect code execution from the default value of the

PC on device Reset to the actual start of code. A GOTO

instruction is programmed by the user at 000000h with

the actual address for the start of code at 000002h.

Program

Memory

(Words)

Configuration

Word

Addresses

Device

0057F8h:

0057FEh

PIC24F devices also have two interrupt vector tables,

located from 000004h to 0000FFh and 000100h to

0001FFh. These vector tables allow each of the many

device interrupt sources to be handled by separate

ISRs. A more detailed discussion of the interrupt vector

tables is provided in Section 7.1 “Interrupt Vector

Table”.

PIC24FJ32GB0

PIC24FJ64GB0

11,008

22,016

00ABF8h:

00ABFEh

FIGURE 4-2:

PROGRAM MEMORY ORGANIZATION

least significant word

8

MSW

Address

PC Address

(LSW Address)

most significant word

23

16

0

000000h

000002h

000004h

000006h

00000000

000001h

000003h

000005h

000007h

00000000

Program Memory

‘Phantom’ Byte

(read as ‘0’)

Instruction Width

DS39940D-page 32

 2010 Microchip Technology Inc.

PIC24FJ64GB004 FAMILY

PIC24FJ64GB004 family devices implement a total of

16 Kbytes of data memory. Should an EA point to a

location outside of this area, an all zero word or byte will

be returned.

4.2

Data Address Space

The PIC24F core has a separate, 16-bit wide data mem-

ory space, addressable as a single linear range. The

data space is accessed using two Address Generation

Units (AGUs), one each for read and write operations.

The data space memory map is shown in Figure 4-3.

4.2.1

DATA SPACE WIDTH

The data memory space is organized in

byte-addressable, 16-bit wide blocks. Data is aligned

in data memory and registers as 16-bit words, but all

data space EAs resolve to bytes. The Least Significant

Bytes (LSBs) of each word have even addresses, while

the Most Significant Bytes (MSBs) have odd

addresses.

All Effective Addresses (EAs) in the data memory space

are 16 bits wide and point to bytes within the data space.

This gives a data space address range of 64 Kbytes or

32K words. The lower half of the data memory space

(that is, when EA<15> = 0) is used for implemented

memory addresses, while the upper half (EA<15> = 1) is

reserved for the program space visibility area (see

Section 4.3.3 “Reading Data from Program Memory

Using Program Space Visibility”).

FIGURE 4-3:

DATA SPACE MEMORY MAP FOR PIC24FJ64GB004 FAMILY DEVICES

MSB

Address

LSB

Address

MSB

LSB

0000h

0001h

SFR

Space

SFR Space

Data RAM

07FFh

0801h

07FEh

0800h

Near

Data Space

1FFFh

2001h

1FFEh

2000h

Implemented

Data RAM

27FFh

2801h

27FEh

2800h

Unimplemented

Read as ‘0’

7FFFh

8001h

7FFFh

8000h

Program Space

Visibility Area

FFFFh

FFFEh

Note:

Data memory areas are not shown to scale.

 2010 Microchip Technology Inc.

DS39940D-page 33

PIC24FJ64GB004 FAMILY

A Sign-Extend (SE) instruction is provided to allow

users to translate 8-bit signed data to 16-bit signed

values. Alternatively, for 16-bit unsigned data, users

can clear the MSB of any W register by executing a

Zero-Extend (ZE) instruction on the appropriate

address.

4.2.2

DATA MEMORY ORGANIZATION

AND ALIGNMENT

To maintain backward compatibility with PIC^®devices

and improve data space memory usage efficiency, the

PIC24F instruction set supports both word and byte

operations. As a consequence of byte accessibility, all

Effective Address calculations are internally scaled to

step through word-aligned memory. For example, the

core recognizes that Post-Modified Register Indirect

Addressing mode [Ws++] will result in a value of Ws + 1

for byte operations and Ws + 2 for word operations.

Although most instructions are capable of operating on

word or byte data sizes, it should be noted that some

instructions operate only on words.

4.2.3

NEAR DATA SPACE

The 8-Kbyte area between 0000h and 1FFFh is

referred to as the near data space. Locations in this

space are directly addressable via a 13-bit absolute

address field within all memory direct instructions. The

remainder of the data space is indirectly addressable.

Additionally, the whole data space is addressable using

MOV instructions, which support Memory Direct

Addressing with a 16-bit address field.

Data byte reads will read the complete word which con-

tains the byte using the LSb of any EA to determine

which byte to select. The selected byte is placed onto

the LSB of the data path. That is, data memory and

registers are organized as two parallel, byte-wide

entities with shared (word) address decode, but

separate write lines. Data byte writes only write to the

corresponding side of the array or register which

matches the byte address.

4.2.4

SFR SPACE

All word accesses must be aligned to an even address.

Misaligned word data fetches are not supported, so

care must be taken when mixing byte and word

operations or translating from 8-bit MCU code. If a

misaligned read or write is attempted, an address error

trap will be generated. If the error occurred on a read,

the instruction underway is completed; if it occurred on

a write, the instruction will be executed but the write will

not occur. In either case, a trap is then executed, allow-

ing the system and/or user to examine the machine

state prior to execution of the address Fault.

The first 2 Kbytes of the near data space, from 0000h

to 07FFh, are primarily occupied with Special Function

Registers (SFRs). These are used by the PIC24F core

and peripheral modules for controlling the operation of

the device.

SFRs are distributed among the modules that they

control and are generally grouped together by the

module. Much of the SFR space contains unused

addresses; these are read as ‘0’. A diagram of the SFR

space, showing where SFRs are actually implemented,

is shown in Table 4-2. Each implemented area

indicates a 32-byte region where at least one address

is implemented as an SFR. A complete listing of

implemented SFRs, including their addresses, is

shown in Tables 4-3 through 4-27.

All byte loads into any W register are loaded into the

Least Significant Byte. The Most Significant Byte is not

modified.

TABLE 4-2:

IMPLEMENTED REGIONS OF SFR DATA SPACE

SFR Space Address

xx00

xx20

xx40

xx60

xx80

xxA0

xxC0

xxE0

000h

100h

200h

300h

400h

500h

600h

700h

Core

ICN

Interrupts

Compare

—

Timers

Capture

I²C™

A/D

—

UART

SPI

—

I/O

A/D/CTMU

—

USB

—

PMP

—

RTCC

—

CRC/Comp Comparators

System/DS NVM/PMD

PPS

—

Legend: — = No implemented SFRs in this block

DS39940D-page 34

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PIC24FJ64GB004 FAMILY

4.2.5

SOFTWARE STACK

4.3

Interfacing Program and Data

Memory Spaces

In addition to its use as a working register, the W15

register in PIC24F devices is also used as a Software

Stack Pointer. The pointer always points to the first

available free word and grows from lower to higher

addresses. It predecrements for stack pops and

post-increments for stack pushes, as shown in

Figure 4-4. Note that for a PC push during any CALL

instruction, the MSB of the PC is zero-extended before

the push, ensuring that the MSB is always clear.

The PIC24F architecture uses a 24-bit wide program

space and a 16-bit wide data space. The architecture is

also a modified Harvard scheme, meaning that data

can also be present in the program space. To use this

data successfully, it must be accessed in a way that

preserves the alignment of information in both spaces.

Aside from normal execution, the PIC24F architecture

provides two methods by which program space can be

accessed during operation:

Note:

A PC push during exception processing

will concatenate the SRL register to the

MSB of the PC prior to the push.

• Using table instructions to access individual bytes

or words anywhere in the program space

The Stack Pointer Limit Value (SPLIM) register, associ-

ated with the Stack Pointer, sets an upper address

boundary for the stack. SPLIM is uninitialized at Reset.

As is the case for the Stack Pointer, SPLIM<0> is

forced to ‘0’ because all stack operations must be

word-aligned. Whenever an EA is generated, using

W15 as a source or destination pointer, the resulting

address is compared with the value in SPLIM. If the

contents of the Stack Pointer (W15) and the SPLIM reg-

ister are equal, and a push operation is performed, a

stack error trap will not occur. The stack error trap will

occur on a subsequent push operation. Thus, for

example, if it is desirable to cause a stack error trap

when the stack grows beyond address, 2000h in RAM,

initialize the SPLIM with the value, 1FFEh.

• Remapping a portion of the program space into

the data space (program space visibility)

Table instructions allow an application to read or write

to small areas of the program memory. This makes the

method ideal for accessing data tables that need to be

updated from time to time. It also allows access to all

bytes of the program word. The remapping method

allows an application to access a large block of data on

a read-only basis, which is ideal for look-ups from a

large table of static data; it can only access the least

significant word of the program word.

4.3.1

ADDRESSING PROGRAM SPACE

Since the address ranges for the data and program

spaces are 16 and 24 bits, respectively, a method is

needed to create a 23-bit or 24-bit program address

from 16-bit data registers. The solution depends on the

interface method to be used.

Similarly, a Stack Pointer underflow (stack error) trap is

generated when the Stack Pointer address is found to

be less than 0800h. This prevents the stack from

interfering with the Special Function Register (SFR)

space.

For table operations, the 8-bit Table Memory Page

Address (TBLPAG) register is used to define a 32K word

region within the program space. This is concatenated

with a 16-bit EA to arrive at a full 24-bit program space

address. In this format, the Most Significant bit of

TBLPAG is used to determine if the operation occurs in

the user memory (TBLPAG<7> = 0) or the configuration

memory (TBLPAG<7> = 1).

A write to the SPLIM register should not be immediately

followed by an indirect read operation using W15.

FIGURE 4-4:

CALL STACK FRAME

0000h

15

0

For remapping operations, the 8-bit Program Space

Visibility Page Address (PSVPAG) register is used to

define a 16K word page in the program space. When

the Most Significant bit of the EA is ‘1’, PSVPAG is con-

catenated with the lower 15 bits of the EA to form a

23-bit program space address. Unlike table operations,

this limits remapping operations strictly to the user

memory area.

PC<15:0>

000000000

W15 (before CALL)

PC<22:16>

W15 (after CALL)

POP : [--W15]

PUSH: [W15++]

Table 4-28 and Figure 4-5 show how the program EA is

created for table operations and remapping accesses

from the data EA. Here, P<23:0> refers to a program

space word, whereas D<15:0> refers to a data space

word.

DS39940D-page 50

 2010 Microchip Technology Inc.

PIC24FJ64GB004 FAMILY

TABLE 4-28: PROGRAM SPACE ADDRESS CONSTRUCTION

Program Space Address

Access

Space

Access Type

<23>

<22:16>

<15>

PC<22:1>

<14:1>

<0>

Instruction Access

(Code Execution)

User

0

0xx xxxx xxxx xxxx xxxx xxx0

TBLRD/TBLWT

(Byte/Word Read/Write)

User

TBLPAG<7:0>

0xxx xxxx

Data EA<15:0>

xxxx xxxx xxxx xxxx

Data EA<15:0>

Configuration

User

TBLPAG<7:0>

1xxx xxxx

xxxx xxxx xxxx xxxx

Data EA<14:0>⁽¹⁾

Program Space Visibility

(Block Remap/Read)

0

PSVPAG<7:0>

xxxx xxxx

xxx xxxx xxxx xxxx

Note 1: Data EA<15> is always ‘1’ in this case, but is not used in calculating the program space address. Bit 15 of

the address is PSVPAG<0>.

FIGURE 4-5:

DATA ACCESS FROM PROGRAM SPACE ADDRESS GENERATION

Program Counter⁽¹⁾

Program Counter

23 Bits

0

1/0

EA

Table Operations⁽²⁾

1/0

TBLPAG

8 Bits

16 Bits

24 Bits

Select

1

0

EA

Program Space Visibility⁽¹⁾

(Remapping)

0

PSVPAG

8 Bits

15 Bits

23 Bits

Byte Select

User/Configuration

Space Select

Note 1: The LSb of program space addresses is always fixed as ‘0’ in order to maintain word alignment of

data in the program and data spaces.

2: Table operations are not required to be word-aligned. Table read operations are permitted in the

configuration memory space.

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2. TBLRDH (Table Read High): In Word mode, it

4.3.2

DATA ACCESS FROM PROGRAM

MEMORY USING TABLE

INSTRUCTIONS

maps the entire upper word of a program address

(P<23:16>) to

a data address. Note that

D<15:8>, the ‘phantom’ byte, will always be ‘0’.

The TBLRDL and TBLWTL instructions offer a direct

method of reading or writing the lower word of any

address within the program space without going through

data space. The TBLRDHand TBLWTHinstructions are

the only method to read or write the upper 8 bits of a

program space word as data.

In Byte mode, it maps the upper or lower byte of

the program word to D<7:0> of the data

address, as above. Note that the data will

always be ‘0’ when the upper ‘phantom’ byte is

selected (byte select = 1).

In a similar fashion, two table instructions, TBLWTH

and TBLWTL, are used to write individual bytes or

words to a program space address. The details of

their operation are explained in Section 5.0 “Flash

Program Memory”.

The PC is incremented by two for each successive

24-bit program word. This allows program memory

addresses to directly map to data space addresses.

Program memory can thus be regarded as two, 16-bit

word-wide address spaces, residing side by side, each

with the same address range. TBLRDL and TBLWTL

access the space which contains the least significant

data word, and TBLRDHand TBLWTHaccess the space

which contains the upper data byte.

For all table operations, the area of program memory

space to be accessed is determined by the Table

Memory Page Address register (TBLPAG). TBLPAG

covers the entire program memory space of the

device, including user and configuration spaces. When

TBLPAG<7> = 0, the table page is located in the user

memory space. When TBLPAG<7> = 1, the page is

located in configuration space.

Two table instructions are provided to move byte or

word-sized (16-bit) data to and from program space.

Both function as either byte or word operations.

1. TBLRDL (Table Read Low): In Word mode, it

maps the lower word of the program space

location (P<15:0>) to a data address (D<15:0>).

Note:

Only table read operations will execute in

the configuration memory space, and only

then, in implemented areas, such as the

Device ID. Table write operations are not

allowed.

In Byte mode, either the upper or lower byte of

the lower program word is mapped to the lower

byte of a data address. The upper byte is

selected when the byte select is ‘1’; the lower

byte is selected when it is ‘0’.

FIGURE 4-6:

ACCESSING PROGRAM MEMORY WITH TABLE INSTRUCTIONS

Program Space

TBLPAG

02

Data EA<15:0>

23

15

0

000000h

23

16

8

0

00000000

020000h

030000h

‘Phantom’ Byte

TBLRDH.B (Wn<0> = 0)

TBLRDL.B (Wn<0> = 1)

TBLRDL.B (Wn<0> = 0)

TBLRDL.W

The address for the table operation is determined by the data EA

within the page defined by the TBLPAG register.

Only read operations are shown; write operations are also valid in

the user memory area.

800000h

DS39940D-page 52

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24-bit program word are used to contain the data. The

upper 8 bits of any program space locations used as

data should be programmed with ‘1111 1111’ or

‘0000 0000’ to force a NOP. This prevents possible

issues should the area of code ever be accidentally

executed.

4.3.3

READING DATA FROM PROGRAM

MEMORY USING PROGRAM SPACE

VISIBILITY

The upper 32 Kbytes of data space may optionally be

mapped into any 16K word page of the program space.

This provides transparent access of stored constant

data from the data space without the need to use

special instructions (i.e., TBLRDL/H).

Note:

PSV access is temporarily disabled during

table reads/writes.

Program space access through the data space occurs if

the Most Significant bit (MSb) of the data space EA is ‘1’

and program space visibility is enabled by setting the

PSV bit in the CPU Control register (CORCON<2>). The

location of the program memory space to be mapped

into the data space is determined by the Program Space

Visibility Page Address register (PSVPAG). This 8-bit

register defines any one of 256 possible pages of

16K words in program space. In effect, PSVPAG func-

tions as the upper 8 bits of the program memory

address, with the 15 bits of the EA functioning as the

lower bits. Note that by incrementing the PC by 2 for

each program memory word, the lower 15 bits of data

space addresses directly map to the lower 15 bits in the

corresponding program space addresses.

For operations that use PSV and are executed outside

a REPEATloop, the MOV and MOV.Dinstructions will

require one instruction cycle in addition to the specified

execution time. All other instructions will require two

instruction cycles in addition to the specified execution

time.

For operations that use PSV which are executed inside

a REPEAT loop, there will be some instances that

require two instruction cycles in addition to the

specified execution time of the instruction:

• Execution in the first iteration

• Execution in the last iteration

• Execution prior to exiting the loop due to an

interrupt

• Execution upon re-entering the loop after an

interrupt is serviced

Data reads to this area add an additional cycle to the

instruction being executed, since two program memory

fetches are required.

Any other iteration of the REPEAT loop will allow the

instruction accessing data, using PSV, to execute in a

single cycle.

Although each data space address, 8000h and higher,

maps directly into a corresponding program memory

address (see Figure 4-7), only the lower 16 bits of the

FIGURE 4-7:

PROGRAM SPACE VISIBILITY OPERATION

When CORCON<2> = 1and EA<15> = 1:

Program Space

Data Space

PSVPAG

02

23

15

0

000000h

0000h

Data EA<14:0>

010000h

018000h

The data in the page

designated by

PSVPAG is mapped

into the upper half of

the data memory

space....

8000h

PSV Area

...while the lower

15 bits of the EA

specify an exact

address within the

PSV area. This

FFFFh

corresponds exactly to

the same lower 15 bits

of the actual program

space address.

800000h

 2010 Microchip Technology Inc.

DS39940D-page 53

PIC24FJ64GB004 FAMILY

NOTES:

DS39940D-page 54

 2010 Microchip Technology Inc.

PIC24FJ64GB004 FAMILY

RTSP is accomplished using TBLRD (table read) and

TBLWT (table write) instructions. With RTSP, the user

5.0

FLASH PROGRAM MEMORY

Note:

This data sheet summarizes the features

of this group of PIC24F devices. It is not

intended to be a comprehensive reference

source. For more information, refer to the

“PIC24F Family Reference Manual”,

may write program memory data in blocks of 64 instruc-

tions (192 bytes) at a time and erase program memory

in blocks of 512 instructions (1536 bytes) at a time.

5.1

Table Instructions and Flash

Programming

Section

4.

“Program

Memory”

(DS39715).

Regardless of the method used, all programming of

Flash memory is done with the table read and table

write instructions. These allow direct read and write

access to the program memory space from the data

memory while the device is in normal operating mode.

The 24-bit target address in the program memory is

formed using the TBLPAG<7:0> bits and the Effective

Address (EA) from a W register specified in the table

instruction, as shown in Figure 5-1.

The PIC24FJ64GB004 family of devices contains

internal Flash program memory for storing and executing

application code. The memory is readable, writable and

erasable when operating with VDD over 2.35V. (If the

regulator is disabled, VDDCORE must be over 2.25V.)

It can be programmed in four ways:

• In-Circuit Serial Programming™ (ICSP™)

• Run-Time Self-Programming (RTSP)

The TBLRDLand the TBLWTLinstructions are used to

read or write to bits<15:0> of program memory.

TBLRDLand TBLWTLcan access program memory in

both Word and Byte modes.

• Enhanced In-Circuit Serial Programming

(Enhanced ICSP)

ICSP allows a PIC24FJ64GB004 family device to be

serially programmed while in the end application circuit.

This is simply done with two lines for the programming

clock and programming data (which are named PGECx

and PGEDx, respectively), and three other lines for

power (VDD), ground (VSS) and Master Clear (MCLR).

This allows customers to manufacture boards with

unprogrammed devices and then program the micro-

controller just before shipping the product. This also

allows the most recent firmware or a custom firmware

to be programmed.

The TBLRDHand TBLWTHinstructions are used to read

or write to bits<23:16> of program memory. TBLRDH

and TBLWTHcan also access program memory in Word

or Byte mode.

FIGURE 5-1:

ADDRESSING FOR TABLE REGISTERS

24 Bits

Program Counter

Using

Program

Counter

0

Working Reg EA

Using

Table

Instruction

1/0

TBLPAG Reg

8 Bits

16 Bits

User/Configuration

Space Select

Byte

Select

24-Bit EA

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5.2

RTSP Operation

5.3

JTAG Operation

The PIC24F Flash program memory array is organized

into rows of 64 instructions or 192 bytes. RTSP allows

the user to erase blocks of eight rows (512 instructions)

at a time and to program one row at a time. It is also

possible to program single words.

The PIC24F family supports JTAG boundary scan.

Boundary scan can improve the manufacturing

process by verifying pin to PCB connectivity.

5.4

Enhanced In-Circuit Serial

Programming

The 8-row erase blocks and single row write blocks are

edge-aligned, from the beginning of program memory, on

boundaries of 1536 bytes and 192 bytes, respectively.

Enhanced In-Circuit Serial Programming uses an

on-board bootloader, known as the program executive,

to manage the programming process. Using an SPI

data frame format, the program executive can erase,

program and verify program memory. For more

information on Enhanced ICSP, see the device

programming specification.

When data is written to program memory using TBLWT

instructions, the data is not written directly to memory.

Instead, data written using table writes is stored in

holding latches until the programming sequence is

executed.

Any number of TBLWT instructions can be executed

and a write will be successfully performed. However,

64 TBLWTinstructions are required to write the full row

of memory.

5.5

Control Registers

There are two SFRs used to read and write the

program Flash memory: NVMCON and NVMKEY.

To ensure that no data is corrupted during a write, any

unused addresses should be programmed with

FFFFFFh. This is because the holding latches reset to

an unknown state, so if the addresses are left in the

Reset state, they may overwrite the locations on rows

which were not rewritten.

The NVMCON register (Register 5-1) controls which

blocks are to be erased, which memory type is to be

programmed and when the programming cycle starts.

NVMKEY is a write-only register that is used for write

protection. To start a programming or erase sequence,

the user must consecutively write 55h and AAh to the

NVMKEY register. Refer to Section 5.6 “Programming

Operations” for further details.

The basic sequence for RTSP programming is to set up

a Table Pointer, then do a series of TBLWTinstructions

to load the buffers. Programming is performed by

setting the control bits in the NVMCON register.

5.6

Programming Operations

Data can be loaded in any order and the holding regis-

ters can be written to multiple times before performing

a write operation. Subsequent writes, however, will

wipe out any previous writes.

A complete programming sequence is necessary for

programming or erasing the internal Flash in RTSP

mode. During a programming or erase operation, the

processor stalls (waits) until the operation is finished.

Setting the WR bit (NVMCON<15>) starts the

operation and the WR bit is automatically cleared when

the operation is finished.

Note:

Writing to a location multiple times without

erasing is not recommended.

All of the table write operations are single-word writes

(2 instruction cycles) because only the buffers are writ-

ten. A programming cycle is required for programming

each row.

DS39940D-page 56

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REGISTER 5-1:

NVMCON: FLASH MEMORY CONTROL REGISTER

R/SO-0, HC⁽¹⁾R/W-0⁽¹⁾R/W-0, HS⁽¹⁾

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

WR

bit 15

WREN

WRERR

bit 8

U-0

—

R/W-0⁽¹⁾

ERASE

U-0

—

U-0

—

R/W-0⁽¹⁾

NVMOP3⁽²⁾

R/W-0⁽¹⁾

NVMOP2⁽²⁾

R/W-0⁽¹⁾

NVMOP1⁽²⁾NVMOP0⁽²⁾

R/W-0⁽¹⁾

bit 7

bit 0

Legend:

SO = Settable Only bit

W = Writable bit

‘1’ = Bit is set

HC = Hardware Clearable bit

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

HS = Hardware Settable bit

R = Readable bit

-n = Value at POR

bit 15

WR: Write Control bit⁽¹⁾

1= Initiate a Flash memory program or erase operation. The operation is self-timed and the bit is

cleared by hardware once the operation is complete.

0= Program or erase operation is complete and inactive

bit 14

bit 13

WREN: Write Enable bit⁽¹⁾

1= Enable Flash program/erase operations

0= Inhibit Flash program/erase operations

WRERR: Write Sequence Error Flag bit⁽¹⁾

1= An improper program or erase sequence attempt, or termination has occurred (bit is set

automatically on any set attempt of the WR bit)

0= The program or erase operation completed normally

bit 12-7

bit 6

Unimplemented: Read as ‘0’

ERASE: Erase/Program Enable bit⁽¹⁾

1= Perform the erase operation specified by NVMOP<3:0> on the next WR command

0= Perform the program operation specified by NVMOP<3:0> on the next WR command

bit 5-4

bit 3-0

Unimplemented: Read as ‘0’

NVMOP<3:0>: NVM Operation Select bits^(1,2)

1111= Memory bulk erase operation (ERASE = 1) or no operation (ERASE = 0)⁽³⁾

0011= Memory word program operation (ERASE = 0) or no operation (ERASE = 1)

0010= Memory page erase operation (ERASE = 1) or no operation (ERASE = 0)

0001= Memory row program operation (ERASE = 0) or no operation (ERASE = 1)

Note 1: These bits can only be reset on POR.

2: All other combinations of NVMOP<3:0> are unimplemented.

3: Available in ICSP™ mode only. Refer to the device programming specification.

 2010 Microchip Technology Inc.

DS39940D-page 57

PIC24FJ64GB004 FAMILY

4. Write the first 64 instructions from data RAM into

the program memory buffers (see Example 5-1).

5.6.1

PROGRAMMING ALGORITHM FOR

FLASH PROGRAM MEMORY

5. Write the program block to Flash memory:

The user can program one row of Flash program memory

at a time. To do this, it is necessary to erase the 8-row

erase block containing the desired row. The general

process is as follows:

a) Set the NVMOP bits to ‘0001’ to configure

for row programming. Clear the ERASE bit

and set the WREN bit.

b) Write 55h to NVMKEY.

c) Write AAh to NVMKEY.

1. Read eight rows of program memory

(512 instructions) and store in data RAM.

d) Set the WR bit. The programming cycle

begins and the CPU stalls for the duration

of the write cycle. When the write to Flash

memory is done, the WR bit is cleared

automatically.

2. Update the program data in RAM with the

desired new data.

3. Erase the block (see Example 5-1):

a) Set the NVMOP bits (NVMCON<3:0>) to

‘0010’ to configure for block erase. Set the

ERASE (NVMCON<6>) and WREN

(NVMCON<14>) bits.

6. Repeat steps 4 and 5, using the next available

64 instructions from the block in data RAM by

incrementing the value in TBLPAG, until all

512 instructions are written back to Flash

memory.

b) Write the starting address of the block to be

erased into the TBLPAG and W registers.

c) Write 55h to NVMKEY.

d) Write AAh to NVMKEY.

For protection against accidental operations, the write

initiate sequence for NVMKEY must be used to allow

any erase or program operation to proceed. After the

programming command has been executed, the user

must wait for the programming time until programming

is complete. The two instructions following the start of

the programming sequence should be NOPs, as shown

in Example 5-5.

e) Set the WR bit (NVMCON<15>). The erase

cycle begins and the CPU stalls for the dura-

tion of the erase cycle. When the erase is

done, the WR bit is cleared automatically.

EXAMPLE 5-1:

ERASING A PROGRAM MEMORY BLOCK – ASSEMBLY LANGUAGE CODE

; Set up NVMCON for block erase operation

MOV

#0x4042, W0

W0, NVMCON

;

; Initialize NVMCON

; Init pointer to row to be ERASED

MOV

#tblpage(PROG_ADDR), W0

W0, TBLPAG

#tbloffset(PROG_ADDR), W0

;

; Initialize PM Page Boundary SFR

; Initialize in-page EA[15:0] pointer

; Set base address of erase block

; Block all interrupts with priority <7

; for next 5 instructions

TBLWTL W0, [W0]

DISI

#5

MOV

BSET

NOP

#0x55, W0

W0, NVMKEY

#0xAA, W1

W1, NVMKEY

NVMCON, #WR

; Write the 55 key

;

; Write the AA key

; Start the erase sequence

; Insert two NOPs after the erase

; command is asserted

DS39940D-page 58

 2010 Microchip Technology Inc.

PIC24FJ64GB004 FAMILY

EXAMPLE 5-2:

ERASING A PROGRAM MEMORY BLOCK – ‘C’ LANGUAGE CODE

// C example using MPLAB C30

unsigned long progAddr = 0xXXXXXX;

unsigned int offset;

// Address of row to write

//Set up pointer to the first memory location to be written

TBLPAG = progAddr>>16;

// Initialize PM Page Boundary SFR

offset = progAddr & 0xFFFF;

// Initialize lower word of address

__builtin_tblwtl(offset, 0x0000);

// Set base address of erase block

// with dummy latch write

NVMCON = 0x4042;

// Initialize NVMCON

asm("DISI #5");

// Block all interrupts with priority <7

// for next 5 instructions

__builtin_write_NVM();

// C30 function to perform unlock

// sequence and set WR

EXAMPLE 5-3:

LOADING THE WRITE BUFFERS – ASSEMBLY LANGUAGE CODE

; Set up NVMCON for row programming operations

MOV

#0x4001, W0

W0, NVMCON

;

; Initialize NVMCON

; Set up a pointer to the first program memory location to be written

; program memory selected, and writes enabled

MOV

#0x0000, W0

W0, TBLPAG

#0x6000, W0

;

; Initialize PM Page Boundary SFR

; An example program memory address

; Perform the TBLWT instructions to write the latches

; 0th_program_word

MOV

#LOW_WORD_0, W2

#HIGH_BYTE_0, W3

;

TBLWTL W2, [W0]

TBLWTH W3, [W0++]

; Write PM low word into program latch

; Write PM high byte into program latch

; 1st_program_word

MOV

#LOW_WORD_1, W2

#HIGH_BYTE_1, W3

;

TBLWTL W2, [W0]

TBLWTH W3, [W0++]

; Write PM low word into program latch

; Write PM high byte into program latch

;

2nd_program_word

MOV

#LOW_WORD_2, W2

#HIGH_BYTE_2, W3

;

TBLWTL W2, [W0]

TBLWTH W3, [W0++]

; Write PM low word into program latch

; Write PM high byte into program latch

•

; 63rd_program_word

MOV

#LOW_WORD_31, W2

#HIGH_BYTE_31, W3

;

TBLWTL W2, [W0]

TBLWTH W3, [W0]

; Write PM low word into program latch

; Write PM high byte into program latch

 2010 Microchip Technology Inc.

DS39940D-page 59

PIC24FJ64GB004 FAMILY

EXAMPLE 5-4:

LOADING THE WRITE BUFFERS – ‘C’ LANGUAGE CODE

// C example using MPLAB C30

#define NUM_INSTRUCTION_PER_ROW 64

unsigned int offset;

unsigned int i;

unsigned long progAddr = 0xXXXXXX;

unsigned int progData[2*NUM_INSTRUCTION_PER_ROW];

// Address of row to write

// Buffer of data to write

//Set up NVMCON for row programming

NVMCON = 0x4001;

// Initialize NVMCON

//Set up pointer to the first memory location to be written

TBLPAG = progAddr>>16;

offset = progAddr & 0xFFFF;

// Initialize PM Page Boundary SFR

// Initialize lower word of address

//Perform TBLWT instructions to write necessary number of latches

for(i=0; i < 2*NUM_INSTRUCTION_PER_ROW; i++)

{

__builtin_tblwtl(offset, progData[i++]);

__builtin_tblwth(offset, progData[i]);

offset = offset + 2;

// Write to address low word

// Write to upper byte

// Increment address

}

EXAMPLE 5-5:

INITIATING A PROGRAMMING SEQUENCE – ASSEMBLY LANGUAGE CODE

DISI

#5

; Block all interrupts with priority <7

; for next 5 instructions

MOV

BSET

NOP

BTSC

BRA

#0x55, W0

W0, NVMKEY

#0xAA, W1

W1, NVMKEY

NVMCON, #WR

; Write the 55 key

;

; Write the AA key

; Start the erase sequence

;

NVMCON, #15

$-2

; and wait for it to be

; completed

EXAMPLE 5-6:

INITIATING A PROGRAMMING SEQUENCE – ‘C’ LANGUAGE CODE

// C example using MPLAB C30

asm("DISI #5");

// Block all interrupts with priority < 7

// for next 5 instructions

__builtin_write_NVM();

// Perform unlock sequence and set WR

DS39940D-page 60

 2010 Microchip Technology Inc.

PIC24FJ64GB004 FAMILY

instructions write the desired data into the write latches

and specify the lower 16 bits of the program memory

address to write to. To configure the NVMCON register

for a word write, set the NVMOP bits (NVMCON<3:0>)

to ‘0011’. The write is performed by executing the

unlock sequence and setting the WR bit (see

Example 5-7).

5.6.2

PROGRAMMING A SINGLE WORD

OF FLASH PROGRAM MEMORY

If a Flash location has been erased, it can be pro-

grammed using table write instructions to write an

instruction word (24-bit) into the write latch. The

TBLPAG register is loaded with the 8 Most Significant

Bytes of the Flash address. The TBLWTLand TBLWTH

EXAMPLE 5-7:

PROGRAMMING A SINGLE WORD OF FLASH PROGRAM MEMORY –

ASSEMBLY LANGUAGE CODE

; Setup a pointer to data Program Memory

MOV

#tblpage(PROG_ADDR), W0

W0, TBLPAG

#tbloffset(PROG_ADDR), W0

;

;Initialize PM Page Boundary SFR

;Initialize a register with program memory address

MOV

#LOW_WORD, W2

#HIGH_BYTE, W3

;

TBLWTL W2, [W0]

TBLWTH W3, [W0++]

; Write PM low word into program latch

; Write PM high byte into program latch

; Setup NVMCON for programming one word to data Program Memory

MOV

#0x4003, W0

W0, NVMCON

;

; Set NVMOP bits to 0011

DISI

MOV

BSET

NOP

#5

; Disable interrupts while the KEY sequence is written

; Write the key sequence

#0x55, W0

W0, NVMKEY

#0xAA, W0

W0, NVMKEY

NVMCON, #WR

; Start the write cycle

; Insert two NOPs after the erase

; Command is asserted

EXAMPLE 5-8:

PROGRAMMING A SINGLE WORD OF FLASH PROGRAM MEMORY –

‘C’ LANGUAGE CODE

// C example using MPLAB C30

unsigned int offset;

unsigned long progAddr = 0xXXXXXX;

unsigned int progDataL = 0xXXXX;

unsigned char progDataH = 0xXX;

// Address of word to program

// Data to program lower word

// Data to program upper byte

//Set up NVMCON for word programming

NVMCON = 0x4003;

// Initialize NVMCON

//Set up pointer to the first memory location to be written

TBLPAG = progAddr>>16;

// Initialize PM Page Boundary SFR

offset = progAddr & 0xFFFF;

// Initialize lower word of address

//Perform TBLWT instructions to write latches

__builtin_tblwtl(offset, progDataL);

__builtin_tblwth(offset, progDataH);

asm(“DISI #5”);

// Write to address low word

// Write to upper byte

// Block interrupts with priority < 7

// for next 5 instructions

// C30 function to perform unlock

// sequence and set WR

__builtin_write_NVM();

 2010 Microchip Technology Inc.

DS39940D-page 61

PIC24FJ64GB004 FAMILY

NOTES:

DS39940D-page 62

 2010 Microchip Technology Inc.

PIC24FJ64GB004 FAMILY

Any active source of Reset will make the SYSRST

signal active. Many registers associated with the CPU

6.0

RESETS

Note:

This data sheet summarizes the features

of this group of PIC24F devices. It is not

intended to be a comprehensive reference

source. For more information, refer to the

“PIC24F Family Reference Manual”,

Section 7. “Reset” (DS39712).

and peripherals are forced to a known Reset state.

Most registers are unaffected by a Reset; their status is

unknown on POR and unchanged by all other Resets.

Note:

Refer to the specific peripheral or CPU

section of this manual for register Reset

states.

The Reset module combines all Reset sources and

controls the device Master Reset Signal, SYSRST. The

following is a list of device Reset sources:

All types of device Reset will set a corresponding status

bit in the RCON register to indicate the type of Reset

(see Register 6-1). A Power-on Reset will clear all bits,

except for the BOR and POR bits (RCON<1:0>), which

are set. The user may set or clear any bit at any time

during code execution. The RCON bits only serve as

status bits. Setting a particular Reset status bit in

software will not cause a device Reset to occur.

• POR: Power-on Reset

• MCLR: Pin Reset

• SWR: RESETInstruction

• WDT: Watchdog Timer Reset

• BOR: Brown-out Reset

The RCON register also has other bits associated with

the Watchdog Timer and device power-saving states.

The function of these bits is discussed in other sections

of this data sheet.

• CM: Configuration Mismatch Reset

• TRAPR: Trap Conflict Reset

• IOPUWR: Illegal Opcode Reset

• UWR: Uninitialized W Register Reset

Note:

The status bits in the RCON register

should be cleared after they are read so

that the next RCON register value after a

device Reset will be meaningful.

A simplified block diagram of the Reset module is

shown in Figure 6-1.

FIGURE 6-1:

RESET SYSTEM BLOCK DIAGRAM

RESET

Instruction

Glitch Filter

MCLR

WDT

Module

Sleep or Idle

POR

VDD Rise

Detect

SYSRST

VDD

Brown-out

Reset

BOR

Enable Voltage Regulator

Trap Conflict

Illegal Opcode

Configuration Mismatch

Uninitialized W Register

 2010 Microchip Technology Inc.

Preliminary

DS39940D-page 63

PIC24FJ64GB004 FAMILY

REGISTER 6-1:

RCON: RESET CONTROL REGISTER⁽¹⁾

R/W-0, HS

TRAPR

bit 15

R/W-0, HS

U-0

—

U-0

—

U-0

—

R/CO-0, HS R/W-0, HS

R/W-0

IOPUWR

DPSLP

CM

PMSLP

bit 8

R/W-0, HS

EXTR

R/W-0, HS

SWR

R/W-0

SWDTEN⁽²⁾

R/W-0, HS

WDTO

R/W-0, HS

SLEEP

R/W-0, HS

IDLE

R/W-1, HS

BOR

R/W-1, HS

POR

bit 7

bit 0

Legend:

CO = Clearable Only bit

W = Writable bit

HS = Hardware Settable bit

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

R = Readable bit

-n = Value at POR

‘1’ = Bit is set

bit 15

bit 14

TRAPR: Trap Reset Flag bit

1= A Trap Conflict Reset has occurred

0= A Trap Conflict Reset has not occurred

IOPUWR: Illegal Opcode or Uninitialized W Access Reset Flag bit

1= An illegal opcode detection, an illegal address mode or uninitialized W register used as an Address

Pointer caused a Reset

0= An illegal opcode or uninitialized W Reset has not occurred

bit 13-11

bit 10

Unimplemented: Read as ‘0’

DPSLP: Deep Sleep Mode Flag bit

1= Deep Sleep has occurred

0= Deep Sleep has not occurred

bit 9

bit 8

CM: Configuration Word Mismatch Reset Flag bit

1= A Configuration Word Mismatch Reset has occurred

0= A Configuration Word Mismatch Reset has not occurred

PMSLP: Program Memory Power During Sleep bit

1= Program memory bias voltage remains powered during Sleep

0= Program memory bias voltage is powered down during Sleep and the voltage regulator enters Standby

mode

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

EXTR: External Reset (MCLR) Pin bit

1= A Master Clear (pin) Reset has occurred

0= A Master Clear (pin) Reset has not occurred

SWR: Software Reset (Instruction) Flag bit

1= A RESETinstruction has been executed

0= A RESETinstruction has not been executed

SWDTEN: Software Enable/Disable of WDT bit⁽²⁾

1= WDT is enabled

0= WDT is disabled

WDTO: Watchdog Timer Time-out Flag bit

1= WDT time-out has occurred

0= WDT time-out has not occurred

SLEEP: Wake From Sleep Flag bit

1= Device has been in Sleep mode

0= Device has not been in Sleep mode

IDLE: Wake-up From Idle Flag bit

1= Device has been in Idle mode

0= Device has not been in Idle mode

Note 1: All of the Reset status bits may be set or cleared in software. Setting one of these bits in software does not

cause a device Reset.

2: If the FWDTEN Configuration bit is ‘1’ (unprogrammed), the WDT is always enabled, regardless of the

SWDTEN bit setting.

DS39940D-page 64

Preliminary

 2010 Microchip Technology Inc.

PIC24FJ64GB004 FAMILY

REGISTER 6-1:

RCON: RESET CONTROL REGISTER⁽¹⁾(CONTINUED)

bit 1

BOR: Brown-out Reset Flag bit

1= A Brown-out Reset has occurred. Note that BOR is also set after a Power-on Reset.

0= A Brown-out Reset has not occurred

bit 0

POR: Power-on Reset Flag bit

1= A Power-on Reset has occurred

0= A Power-on Reset has not occurred

Note 1: All of the Reset status bits may be set or cleared in software. Setting one of these bits in software does not

cause a device Reset.

2: If the FWDTEN Configuration bit is ‘1’ (unprogrammed), the WDT is always enabled, regardless of the

SWDTEN bit setting.

TABLE 6-1:

RESET FLAG BIT OPERATION

Setting Event

Flag Bit

Clearing Event

TRAPR (RCON<15>)

IOPUWR (RCON<14>)

CM (RCON<9>)

Trap Conflict Event

POR

Illegal Opcode or Uninitialized W Register Access

Configuration Mismatch Reset

MCLR Reset

POR

EXTR (RCON<7>)

SWR (RCON<6>)

WDTO (RCON<4>)

SLEEP (RCON<3>)

IDLE (RCON<2>)

BOR (RCON<1>)

POR (RCON<0>)

DPSLP (RCON<10>)

POR

RESETInstruction

POR

WDT Time-out

PWRSAVInstruction, POR

PWRSAV #SLEEPInstruction

PWRSAV #IDLEInstruction

POR, BOR

POR

—

POR

—

PWRSAV #SLEEPinstruction with DSCON <DSEN> set

POR

Note: All Reset flag bits may be set or cleared by the user software.

6.1

Clock Source Selection at Reset

6.2

Device Reset Times

If clock switching is enabled, the system clock source at

device Reset is chosen as shown in Table 6-2. If clock

switching is disabled, the system clock source is always

selected according to the oscillator configuration bits.

Refer to Section 8.0 “Oscillator Configuration” for

further details.

The Reset times for various types of device Reset are

summarized in Table 6-3. Note that the System Reset

signal, SYSRST, is released after the POR and PWRT

delay times expire.

The time at which the device actually begins to execute

code will also depend on the system oscillator delays,

which include the Oscillator Start-up Timer (OST) and

the PLL lock time. The OST and PLL lock times occur

in parallel with the applicable SYSRST delay times.

TABLE 6-2:

OSCILLATOR SELECTION vs.

TYPE OF RESET (CLOCK

SWITCHING ENABLED)

The FSCM delay determines the time at which the

FSCM begins to monitor the system clock source after

the SYSRST signal is released.

Reset Type

Clock Source Determinant

POR

BOR

FNOSC Configuration bits

(CW2<10:8>)

MCLR

WDTO

SWR

COSC Control bits

(OSCCON<14:12>)

 2010 Microchip Technology Inc.

Preliminary

DS39940D-page 65

PIC24FJ64GB004 FAMILY

TABLE 6-3:

Reset Type

POR⁽⁶⁾

RESET DELAY TIMES FOR VARIOUS DEVICE RESETS

System Clock

Delay

Clock Source

SYSRST Delay

Notes

1, 2, 3

EC

TPOR + TRST + TPWRT

TPOR+ TRST + TPWRT

TPOR + TRST + TPWRT

TRST + TPWRT

—

FRC, FRCDIV

LPRC

TFRC

TLPRC

TLOCK

1, 2, 3, 4

1, 2, 3, 5

ECPLL

FRCPLL

TFRC + TLOCK 1, 2, 3, 4, 5

TOST 1, 2, 3, 6

TOST + TLOCK 1, 2, 3, 5, 6

XT, HS, SOSC

XTPLL, HSPLL

EC

BOR

—

2, 3

FRC, FRCDIV

LPRC

TRST + TPWRT

TFRC

TLPRC

TLOCK

2, 3, 4

2, 3, 5

TRST + TPWRT

ECPLL

TRST + TPWRT

FRCPLL

TRST + TPWRT

TFRC + TLOCK 2, 3, 4, 5

TOST 2, 3, 6

TFRC + TLOCK 2, 3, 4, 5

XT, HS, SOSC

XTPLL, HSPLL

Any Clock

TRST + TPWRT

All Others

TRST

—

2

Note 1: TPOR = Power-on Reset delay.

2: TRST = Internal State Reset time.

3: TPWRT = 64 ms nominal if regulator is disabled (DISVREG tied to VDD).

4: TFRC and TLPRC = RC Oscillator start-up times.

5: TLOCK = PLL lock time.

6: TOST = Oscillator Start-up Timer (OST). A 10-bit counter waits 1024 oscillator periods before releasing the

oscillator clock to the system.

7: If Two-Speed Start-up is enabled, regardless of the primary oscillator selected, the device starts with FRC,

and in such cases, FRC start-up time is valid.

Note: For detailed operating frequency and timing specifications, see Section 29.0 “Electrical Characteristics”.

DS39940D-page 66

Preliminary

 2010 Microchip Technology Inc.

PIC24FJ64GB004 FAMILY

6.2.1

POR AND LONG OSCILLATOR

START-UP TIMES

6.3

Special Function Register Reset

States

The oscillator start-up circuitry and its associated delay

timers are not linked to the device Reset delays that

occur at power-up. Some crystal circuits (especially

low-frequency crystals) will have a relatively long

start-up time. Therefore, one or more of the following

conditions is possible after SYSRST is released:

Most of the Special Function Registers (SFRs) associ-

ated with the PIC24F CPU and peripherals are reset to a

particular value at a device Reset. The SFRs are

grouped by their peripheral or CPU function and their

Reset values are specified in each section of this manual.

The Reset value for each SFR does not depend on the

type of Reset with the exception of four registers. The

Reset value for the Reset Control register, RCON, will

depend on the type of device Reset. The Reset value

for the Oscillator Control register, OSCCON, will

depend on the type of Reset and the programmed

values of the FNOSC bits in Flash Configuration

Word 2 (CW2); see Table 6-2. The RCFGCAL and

NVMCON registers are only affected by a POR.

• The oscillator circuit has not begun to oscillate.

• The Oscillator Start-up Timer has not expired (if a

crystal oscillator is used).

• The PLL has not achieved a lock (if PLL is used).

The device will not begin to execute code until a valid

clock source has been released to the system. There-

fore, the oscillator and PLL start-up delays must be

considered when the Reset delay time must be known.

6.4

Deep Sleep BOR (DSBOR)

6.2.2

FAIL-SAFE CLOCK MONITOR

(FSCM) AND DEVICE RESETS

Deep Sleep BOR is a very low-power BOR circuitry,

used when the device is in Deep Sleep mode. Due to

low-current consumption, accuracy may vary.

If the FSCM is enabled, it will begin to monitor the

system clock source when SYSRST is released. If a

valid clock source is not available at this time, the

device will automatically switch to the FRC Oscillator

and the user can switch to the desired crystal oscillator

in the Trap Service Routine (TSR).

The DSBOR trip point is around 2.0V. DSBOR is

enabled by configuring CW4<DSBOREN> = 1. DSBOR

will re-arm the POR to ensure the device will reset if VDD

drops below the POR threshold.

 2010 Microchip Technology Inc.

Preliminary

DS39940D-page 67

PIC24FJ64GB004 FAMILY

NOTES:

DS39940D-page 68

Preliminary

 2010 Microchip Technology Inc.

PIC24FJ64GB004 FAMILY

7.1.1

ALTERNATE INTERRUPT VECTOR

TABLE

7.0

INTERRUPT CONTROLLER

Note:

This data sheet summarizes the features

of this group of PIC24F devices. It is not

intended to be a comprehensive reference

source. For more information, refer to the

“PIC24F Family Reference Manual”,

Section 8. “Interrupts” (DS39707).

The Alternate Interrupt Vector Table (AIVT) is located

after the IVT, as shown in Figure 7-1. Access to the

AIVT is provided by the ALTIVT control bit

(INTCON2<15>). If the ALTIVT bit is set, all interrupt

and exception processes will use the alternate vectors

instead of the default vectors. The alternate vectors are

organized in the same manner as the default vectors.

The PIC24F interrupt controller reduces the numerous

peripheral interrupt request signals to a single interrupt

request signal to the PIC24F CPU. It has the following

features:

The AIVT supports emulation and debugging efforts by

providing a means to switch between an application

and a support environment without requiring the inter-

rupt vectors to be reprogrammed. This feature also

enables switching between applications for evaluation

of different software algorithms at run time. If the AIVT

is not needed, the AIVT should be programmed with

the same addresses used in the IVT.

• Up to 8 processor exceptions and software traps

• 7 user-selectable priority levels

• Interrupt Vector Table (IVT) with up to 118 vectors

• A unique vector for each interrupt or exception

source

• Fixed priority within a specified user priority level

7.2

Reset Sequence

• Alternate Interrupt Vector Table (AIVT) for debug

support

A device Reset is not a true exception because the

interrupt controller is not involved in the Reset process.

The PIC24F devices clear their registers in response to

a Reset which forces the PC to zero. The micro-

controller then begins program execution at location

000000h. The user programs a GOTOinstruction at the

Reset address, which redirects program execution to

the appropriate start-up routine.

• Fixed interrupt entry and return latencies

7.1

Interrupt Vector Table

The Interrupt Vector Table (IVT) is shown in Figure 7-1.

The IVT resides in program memory, starting at location

000004h. The IVT contains 126 vectors, consisting of

8 non-maskable trap vectors, plus up to 118 sources of

interrupt. In general, each interrupt source has its own

vector. Each interrupt vector contains a 24-bit wide

address. The value programmed into each interrupt

vector location is the starting address of the associated

Interrupt Service Routine (ISR).

Note:

Any unimplemented or unused vector

locations in the IVT and AIVT should be

programmed with the address of a default

interrupt handler routine that contains a

RESETinstruction.

Interrupt vectors are prioritized in terms of their natural

priority. This is linked to their position in the vector

table. All other things being equal, lower addresses

have a higher natural priority. For example, the inter-

rupt associated with Vector 0 will take priority over

interrupts at any other vector address.

PIC24FJ64GB004

family

devices

implement

non-maskable traps and unique interrupts. These are

summarized in Table 7-1 and Table 7-2.

 2010 Microchip Technology Inc.

DS39940D-page 69

PIC24FJ64GB004 FAMILY

FIGURE 7-1:

PIC24F INTERRUPT VECTOR TABLE

Reset – GOTOInstruction

Reset – GOTOAddress

Reserved

000000h

000002h

000004h

Oscillator Fail Trap Vector

Address Error Trap Vector

Stack Error Trap Vector

Math Error Trap Vector

Reserved

Interrupt Vector 0

Interrupt Vector 1

—

000014h

—

Interrupt Vector 52

Interrupt Vector 53

Interrupt Vector 54

—

00007Ch

00007Eh

000080h

(1)

Interrupt Vector Table (IVT)

—

Interrupt Vector 116

Interrupt Vector 117

Reserved

0000FCh

0000FEh

000100h

000102h

Reserved

Oscillator Fail Trap Vector

Address Error Trap Vector

Stack Error Trap Vector

Math Error Trap Vector

Reserved

Interrupt Vector 0

Interrupt Vector 1

—

000114h

—

(1)

Alternate Interrupt Vector Table (AIVT)

Interrupt Vector 52

Interrupt Vector 53

Interrupt Vector 54

—

00017Ch

00017Eh

000180h

—

Interrupt Vector 116

Interrupt Vector 117

Start of Code

0001FEh

000200h

Note 1: See Table 7-2 for the interrupt vector list.

TABLE 7-1:

TRAP VECTOR DETAILS

IVT Address

Vector Number

AIVT Address

Trap Source

0

1

2

3

4

5

6

7

000004h

000006h

000008h

00000Ah

00000Ch

00000Eh

000010h

000012h

000104h

000106h

000108h

00010Ah

00010Ch

00010Eh

000110h

000112h

Reserved

Oscillator Failure

Address Error

Stack Error

Math Error

Reserved

DS39940D-page 70

 2010 Microchip Technology Inc.

PIC24FJ64GB004 FAMILY

TABLE 7-2:

IMPLEMENTED INTERRUPT VECTORS

Interrupt Bit Locations

Enable

Vector

Number

AIVT

Address

Interrupt Source

IVT Address

Flag

Priority

ADC1 Conversion Done

Comparator Event

CRC Generator

CTMU Event

13

18

67

77

0

00002Eh

000038h

00009Ah

0000AEh

000014h

00003Ch

00004Eh

000036h

000034h

000078h

000076h

000016h

00001Eh

00005Eh

000060h

000062h

00003Ah

0000A4h

000018h

000020h

000046h

000048h

000066h

00006Eh

000090h

000026h

000028h

000054h

000056h

00001Ah

000022h

000024h

00004Ah

00004Ch

000096h

00002Ah

00002Ch

000098h

000050h

000052h

0000C0h

00012Eh

000138h

00019Ah

0001AEh

000114h

00013Ch

00014Eh

000136h

000134h

000178h

000176h

000116h

00011Eh

00015Eh

000160h

000162h

00013Ah

0001A4h

000118h

000120h

000146h

000148h

000166h

00016Eh

000190h

000126h

000128h

000154h

000156h

00011Ah

000122h

000124h

00014Ah

00014Ch

000196h

00012Ah

00012Ch

000198h

000150h

000152h

0001C0h

IFS0<13>

IFS1<2>

IFS4<3>

IFS4<13>

IFS0<0>

IFS1<4>

IFS1<13>

IFS1<1>

IFS1<0>

IFS3<2>

IFS3<1>

IFS0<1>

IFS0<5>

IFS2<5>

IFS2<6>

IFS2<7>

IFS1<3>

IFS4<8>

IFS0<2>

IFS0<6>

IFS1<9>

IFS1<10>

IFS2<9>

IFS2<13>

IFS3<14>

IFS0<9>

IFS0<10>

IFS2<0>

IFS2<1>

IFS0<3>

IFS0<7>

IFS0<8>

IFS1<11>

IFS1<12>

IFS4<1>

IFS0<11>

IFS0<12>

IFS4<2>

IFS1<14>

IFS1<15>

IFS5<6>

IEC0<13>

IEC1<2>

IEC4<3>

IEC4<13>

IEC0<0>

IEC1<4>

IEC1<13>

IEC1<1>

IEC1<0>

IEC3<2>

IEC3<1>

IEC0<1>

IEC0<5>

IEC2<5>

IEC2<6>

IEC2<7>

IEC1<3>

IEC4<8>

IEC0<2>

IEC0<6>

IEC1<9>

IEC1<10>

IEC2<9>

IEC2<13>

IEC3<14>

IEC0<9>

IEC0<10>

IEC2<0>

IEC2<1>

IEC0<3>

IEC0<7>

IEC0<8>

IEC1<11>

IEC1<12>

IEC4<1>

IEC0<11>

IEC0<12>

IEC4<2>

IEC1<14>

IEC1<15>

IEC5<6>

IPC3<6:4>

IPC4<10:8>

IPC16<14:12>

IPC19<6:4>

IPC0<2:0>

External Interrupt 0

External Interrupt 1

External Interrupt 2

I2C1 Master Event

I2C1 Slave Event

I2C2 Master Event

I2C2 Slave Event

Input Capture 1

Input Capture 2

Input Capture 3

Input Capture 4

Input Capture 5

Input Change Notification

LVD Low-Voltage Detect

Output Compare 1

Output Compare 2

Output Compare 3

Output Compare 4

Output Compare 5

Parallel Master Port

Real-Time Clock/Calendar

SPI1 Error

20

29

17

16

50

49

1

IPC5<2:0>

IPC7<6:4>

IPC4<6:4>

IPC4<2:0>

IPC12<10:8>

IPC12<6:4>

IPC0<6:4>

5

IPC1<6:4>

37

38

39

19

72

2

IPC9<6:4>

IPC9<10:8>

IPC9<14:12>

IPC4<14:12>

IPC18<2:0>

IPC0<10:8>

IPC1<10:8>

IPC6<6:4>

6

25

26

41

45

62

9

IPC6<10:8>

IPC10<6:4>

IPC11<6:4>

IPC15<10:8>

IPC2<6:4>

SPI1 Event

10

32

33

3

IPC2<10:8>

IPC8<2:0>

SPI2 Error

SPI2 Event

IPC8<6:4>

Timer1

IPC0<14:12>

IPC1<14:12>

IPC2<2:0>

Timer2

7

Timer3

8

Timer4

27

28

65

11

12

66

30

31

86

IPC6<14:12>

IPC7<2:0>

Timer5

UART1 Error

IPC16<6:4>

IPC2<14:12>

IPC3<2:0>

UART1 Receiver

UART1 Transmitter

UART2 Error

IPC16<10:8>

IPC7<10:8>

IPC7<14:12>

IPC21<10:8>

UART2 Receiver

UART2 Transmitter

USB Interrupt

 2010 Microchip Technology Inc.

DS39940D-page 71

PIC24FJ64GB004 FAMILY

The interrupt sources are assigned to the IFSx, IECx

and IPCx registers in the order of their vector numbers,

as shown in Table 7-2. For example, the INT0 (External

Interrupt 0) is shown as having a vector number and a

natural order priority of 0. Thus, the INT0IF status bit is

found in IFS0<0>, the INT0IE enable bit in IEC0<0>

and the INT0IP<2:0> priority bits in the first position of

IPC0 (IPC0<2:0>).

7.3

Interrupt Control and Status

Registers

The PIC24FJ64GB004 family of devices implements

the following registers for the interrupt controller:

• INTCON1

• INTCON2

• IFS0 through IFS5

• IEC0 through IEC5

Although they are not specifically part of the interrupt

control hardware, two of the CPU control registers

contain bits that control interrupt functionality. The ALU

STATUS Register (SR) contains the IPL<2:0> bits

(SR<7:5>); these indicate the current CPU interrupt

priority level. The user may change the current CPU

priority level by writing to the IPL bits.

• IPC0 through IPC21 (except IPC13, IPC14 and

IPC17)

• INTTREG

Global interrupt control functions are controlled from

INTCON1 and INTCON2. INTCON1 contains the

Interrupt Nesting Disable (NSTDIS) bit, as well as the

control and status flags for the processor trap sources.

The INTCON2 register controls the external interrupt

request signal behavior and the use of the Alternate

Interrupt Vector Table.

The CORCON register contains the IPL3 bit, which,

together with IPL<2:0>, indicates the current CPU

priority level. IPL3 is a read-only bit so that trap events

cannot be masked by the user software.

The interrupt controller has the Interrupt Controller Test

Register (INTTREG) that displays the status of the

interrupt controller. When an interrupt request occurs,

its associated vector number and the new interrupt

priority level are latched into INTTREG.

The IFSx registers maintain all of the interrupt request

flags. Each source of interrupt has a status bit which is

set by the respective peripherals, or an external signal,

and is cleared via software.

The IECx registers maintain all of the interrupt enable

bits. These control bits are used to individually enable

interrupts from the peripherals or external signals.

This information can be used to determine a specific

interrupt source if a generic ISR is used for multiple

vectors – such as when ISR remapping is used in boot-

loader applications. It also could be used to check if

another interrupt is pending while in an ISR.

The IPCx registers are used to set the Interrupt Priority

Level for each source of interrupt. Each user interrupt

source can be assigned to one of eight priority levels.

All interrupt registers are described in Register 7-1

through Register 7-35, on the following pages.

DS39940D-page 72

 2010 Microchip Technology Inc.

PIC24FJ64GB004 FAMILY

REGISTER 7-1:

SR: ALU STATUS REGISTER (IN CPU)

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

R-0

DC⁽¹⁾

bit 15

bit 8

R/W-0

IPL2^(2,3)

bit 7

R/W-0

IPL1^(2,3)

R/W-0

IPL0^(2,3)

R-0

RA⁽¹⁾

R/W-0

N⁽¹⁾

R/W-0

OV⁽¹⁾

R/W-0

Z⁽¹⁾

R/W-0

C⁽¹⁾

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 7-5

IPL<2:0>: CPU Interrupt Priority Level Status bits^(2,3)

111= CPU interrupt priority level is 7 (15). User interrupts disabled.

110= CPU interrupt priority level is 6 (14)

101= CPU interrupt priority level is 5 (13)

100= CPU interrupt priority level is 4 (12)

011= CPU interrupt priority level is 3 (11)

010= CPU interrupt priority level is 2 (10)

001= CPU interrupt priority level is 1 (9)

000= CPU interrupt priority level is 0 (8)

Note 1: See Register 3-1 for the description of the remaining bit(s) that are not dedicated to interrupt control

functions.

2: The IPL bits are concatenated with the IPL3 bit (CORCON<3>) to form the CPU interrupt priority level.

The value in parentheses indicates the interrupt priority level if IPL3 = 1.

3: The IPL Status bits are read-only when NSTDIS (INTCON1<15>) = 1.

REGISTER 7-2:

CORCON: CPU CONTROL REGISTER

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

bit 15

bit 8

bit 0

U-0

—

U-0

—

U-0

—

U-0

—

R/C-0

IPL3⁽²⁾

R/W-0

PSV⁽¹⁾

U-0

—

U-0

—

bit 7

Legend:

C = Clearable bit

W = Writable bit

‘1’ = Bit is set

R = Readable bit

-n = Value at POR

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 3

IPL3: CPU Interrupt Priority Level Status bit⁽²⁾

1= CPU interrupt priority level is greater than 7

0= CPU interrupt priority level is 7 or less

Note 1: See Register 3-2 for the description of the remaining bit(s) that are not dedicated to interrupt control

functions.

2: The IPL3 bit is concatenated with the IPL<2:0> bits (SR<7:5>) to form the CPU interrupt priority level.

 2010 Microchip Technology Inc.

DS39940D-page 73

PIC24FJ64GB004 FAMILY

REGISTER 7-3:

INTCON1: INTERRUPT CONTROL REGISTER 1

R/W-0

NSTDIS

bit 15

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

bit 8

bit 0

U-0

—

U-0

—

U-0

—

R/W-0

U-0

—

MATHERR

ADDRERR

STKERR

OSCFAIL

bit 7

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15

NSTDIS: Interrupt Nesting Disable bit

1= Interrupt nesting is disabled

0= Interrupt nesting is enabled

bit 14-5

bit 4

Unimplemented: Read as ‘0’

MATHERR: Arithmetic Error Trap Status bit

1= Overflow trap has occurred

0= Overflow trap has not occurred

bit 3

bit 2

bit 1

bit 0

ADDRERR: Address Error Trap Status bit

1= Address error trap has occurred

0= Address error trap has not occurred

STKERR: Stack Error Trap Status bit

1= Stack error trap has occurred

0= Stack error trap has not occurred

OSCFAIL: Oscillator Failure Trap Status bit

1= Oscillator failure trap has occurred

0= Oscillator failure trap has not occurred

Unimplemented: Read as ‘0’

DS39940D-page 74

 2010 Microchip Technology Inc.

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REGISTER 7-4:

INTCON2: INTERRUPT CONTROL REGISTER 2

R/W-0

ALTIVT

bit 15

R-0

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

DISI

bit 8

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

R/W-0

INT2EP

INT1EP

INT0EP

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15

bit 14

ALTIVT: Enable Alternate Interrupt Vector Table (AIVT) bit

1= Use Alternate Interrupt Vector Table

0= Use standard (default) Interrupt Vector Table (IVT)

DISI: DISIInstruction Status bit

1= DISIinstruction is active

0= DISIinstruction is not active

bit 13-3

bit 2

Unimplemented: Read as ‘0’

INT2EP: External Interrupt 2 Edge Detect Polarity Select bit

1= Interrupt on negative edge

0= Interrupt on positive edge

bit 1

bit 0

INT1EP: External Interrupt 1 Edge Detect Polarity Select bit

1= Interrupt on negative edge

0= Interrupt on positive edge

INT0EP: External Interrupt 0 Edge Detect Polarity Select bit

1= Interrupt on negative edge

0= Interrupt on positive edge

 2010 Microchip Technology Inc.

DS39940D-page 75

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REGISTER 7-5:

IFS0: INTERRUPT FLAG STATUS REGISTER 0

U-0

—

U-0

—

R/W-0

AD1IF

R/W-0

SPI1IF

R/W-0

T3IF

U1TXIF

U1RXIF

SPF1IF

bit 15

bit 8

R/W-0

T2IF

R/W-0

OC2IF

R/W-0

IC2IF

U-0

—

R/W-0

T1IF

R/W-0

OC1IF

R/W-0

IC1IF

R/W-0

INT0IF

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15-14

bit 13

Unimplemented: Read as ‘0’

AD1IF: A/D Conversion Complete Interrupt Flag Status bit

1= Interrupt request has occurred

0= Interrupt request has not occurred

bit 12

bit 11

bit 10

bit 9

U1TXIF: UART1 Transmitter Interrupt Flag Status bit

1= Interrupt request has occurred

0= Interrupt request has not occurred

U1RXIF: UART1 Receiver Interrupt Flag Status bit

1= Interrupt request has occurred

0= Interrupt request has not occurred

SPI1IF: SPI1 Event Interrupt Flag Status bit

1= Interrupt request has occurred

0= Interrupt request has not occurred

SPF1IF: SPI1 Fault Interrupt Flag Status bit

1= Interrupt request has occurred

0= Interrupt request has not occurred

bit 8

T3IF: Timer3 Interrupt Flag Status bit

1= Interrupt request has occurred

0= Interrupt request has not occurred

bit 7

T2IF: Timer2 Interrupt Flag Status bit

1= Interrupt request has occurred

0= Interrupt request has not occurred

bit 6

OC2IF: Output Compare Channel 2 Interrupt Flag Status bit

1= Interrupt request has occurred

0= Interrupt request has not occurred

bit 5

IC2IF: Input Capture Channel 2 Interrupt Flag Status bit

1= Interrupt request has occurred

0= Interrupt request has not occurred

bit 4

bit 3

Unimplemented: Read as ‘0’

T1IF: Timer1 Interrupt Flag Status bit

1= Interrupt request has occurred

0= Interrupt request has not occurred

bit 2

bit 1

bit 0

OC1IF: Output Compare Channel 1 Interrupt Flag Status bit

1= Interrupt request has occurred

0= Interrupt request has not occurred

IC1IF: Input Capture Channel 1 Interrupt Flag Status bit

1= Interrupt request has occurred

0= Interrupt request has not occurred

INT0IF: External Interrupt 0 Flag Status bit

1= Interrupt request has occurred

0= Interrupt request has not occurred

DS39940D-page 76

 2010 Microchip Technology Inc.

PIC24FJ64GB004 FAMILY

REGISTER 7-6:

IFS1: INTERRUPT FLAG STATUS REGISTER 1

R/W-0

U2TXIF

bit 15

R/W-0

INT2IF

R/W-0

T5IF

R/W-0

T4IF

R/W-0

OC4IF

R/W-0

OC3IF

U-0

—

U2RXIF

bit 8

U-0

—

U-0

—

U-0

—

R/W-0

INT1IF

R/W-0

CNIF

R/W-0

CMIF

R/W-0

MI2C1IF

SI2C1IF

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

-n = Value at POR

bit 15

bit 14

bit 13

bit 12

bit 11

bit 10

bit 9

U2TXIF: UART2 Transmitter Interrupt Flag Status bit

1= Interrupt request has occurred

0= Interrupt request has not occurred

U2RXIF: UART2 Receiver Interrupt Flag Status bit

1= Interrupt request has occurred

0= Interrupt request has not occurred

INT2IF: External Interrupt 2 Flag Status bit

1= Interrupt request has occurred

0= Interrupt request has not occurred

T5IF: Timer5 Interrupt Flag Status bit

1= Interrupt request has occurred

0= Interrupt request has not occurred

T4IF: Timer4 Interrupt Flag Status bit

1= Interrupt request has occurred

0= Interrupt request has not occurred

OC4IF: Output Compare Channel 4 Interrupt Flag Status bit

1= Interrupt request has occurred

0= Interrupt request has not occurred

OC3IF: Output Compare Channel 3 Interrupt Flag Status bit

1= Interrupt request has occurred

0= Interrupt request has not occurred

bit 8-5

bit 4

Unimplemented: Read as ‘0’

INT1IF: External Interrupt 1 Flag Status bit

1= Interrupt request has occurred

0= Interrupt request has not occurred

bit 3

bit 2

bit 1

bit 0

CNIF: Input Change Notification Interrupt Flag Status bit

1= Interrupt request has occurred

0= Interrupt request has not occurred

CMIF: Comparator Interrupt Flag Status bit

1= Interrupt request has occurred

0= Interrupt request has not occurred

MI2C1IF: Master I2C1 Event Interrupt Flag Status bit

1= Interrupt request has occurred

0= Interrupt request has not occurred

SI2C1IF: Slave I2C1 Event Interrupt Flag Status bit

1= Interrupt request has occurred

0= Interrupt request has not occurred

 2010 Microchip Technology Inc.

DS39940D-page 77

PIC24FJ64GB004 FAMILY

REGISTER 7-7:

IFS2: INTERRUPT FLAG STATUS REGISTER 2

U-0

—

U-0

—

R/W-0

PMPIF

U-0

—

U-0

—

U-0

—

R/W-0

OC5IF

U-0

—

bit 15

bit 8

R/W-0

IC5IF

R/W-0

IC4IF

R/W-0

IC3IF

U-0

—

U-0

—

U-0

—

R/W-0

SPI2IF

R/W-0

SPF2IF

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15-14

bit 13

Unimplemented: Read as ‘0’

PMPIF: Parallel Master Port Interrupt Flag Status bit

1= Interrupt request has occurred

0= Interrupt request has not occurred

bit 12-10

bit 9

Unimplemented: Read as ‘0’

OC5IF: Output Compare Channel 5 Interrupt Flag Status bit

1= Interrupt request has occurred

0= Interrupt request has not occurred

bit 8

bit 7

Unimplemented: Read as ‘0’

IC5IF: Input Capture Channel 5 Interrupt Flag Status bit

1= Interrupt request has occurred

0= Interrupt request has not occurred

bit 6

bit 5

IC4IF: Input Capture Channel 4 Interrupt Flag Status bit

1= Interrupt request has occurred

0= Interrupt request has not occurred

IC3IF: Input Capture Channel 3 Interrupt Flag Status bit

1= Interrupt request has occurred

0= Interrupt request has not occurred

bit 4-2

bit 1

Unimplemented: Read as ‘0’

SPI2IF: SPI2 Event Interrupt Flag Status bit

1= Interrupt request has occurred

0= Interrupt request has not occurred

bit 0

SPF2IF: SPI2 Fault Interrupt Flag Status bit

1= Interrupt request has occurred

0= Interrupt request has not occurred

DS39940D-page 78

 2010 Microchip Technology Inc.

PIC24FJ64GB004 FAMILY

REGISTER 7-8:

IFS3: INTERRUPT FLAG STATUS REGISTER 3

U-0

—

R/W-0

RTCIF

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

bit 15

bit 8

bit 0

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

R/W-0,

R/W-0

U-0

—

MI2C2IF

SI2C2IF

bit 7

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15

bit 14

Unimplemented: Read as ‘0’

RTCIF: Real-Time Clock/Calendar Interrupt Flag Status bit

1= Interrupt request has occurred

0= Interrupt request has not occurred

bit 13-3

bit 2

Unimplemented: Read as ‘0’

MI2C2IF: Master I2C2 Event Interrupt Flag Status bit

1= Interrupt request has occurred

0= Interrupt request has not occurred

bit 1

bit 0

SI2C2IF: Slave I2C2 Event Interrupt Flag Status bit

1= Interrupt request has occurred

0= Interrupt request has not occurred

Unimplemented: Read as ‘0’

 2010 Microchip Technology Inc.

DS39940D-page 79

PIC24FJ64GB004 FAMILY

REGISTER 7-9:

IFS4: INTERRUPT FLAG STATUS REGISTER 4

U-0

—

U-0

—

R/W-0

U-0

—

U-0

—

U-0

—

U-0

—

R/W-0

LVDIF

CTMUIF

bit 15

bit 8

U-0

—

U-0

—

U-0

—

U-0

—

R/W-0

CRCIF

R/W-0

U-0

—

U2ERIF

U1ERIF

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15-14

bit 13

Unimplemented: Read as ‘0’

CTMUIF: CTMU Interrupt Flag Status bit

1= Interrupt request has occurred

0= Interrupt request has not occurred

bit 12-9

bit 8

Unimplemented: Read as ‘0’

LVDIF: Low-Voltage Detect Interrupt Flag Status bit

1= Interrupt request has occurred

0= Interrupt request has not occurred

bit 7-4

bit 3

Unimplemented: Read as ‘0’

CRCIF: CRC Generator Interrupt Flag Status bit

1= Interrupt request has occurred

0= Interrupt request has not occurred

bit 2

bit 1

bit 0

U2ERIF: UART2 Error Interrupt Flag Status bit

1= Interrupt request has occurred

0= Interrupt request has not occurred

U1ERIF: UART1 Error Interrupt Flag Status bit

1= Interrupt request has occurred

0= Interrupt request has not occurred

Unimplemented: Read as ‘0’

DS39940D-page 80

 2010 Microchip Technology Inc.

PIC24FJ64GB004 FAMILY

REGISTER 7-10: IFS5: INTERRUPT FLAG STATUS REGISTER 5

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

bit 15

bit 8

bit 0

U-0

—

R/W-0

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

USB1IF

bit 7

Legend:

R = Readable bit

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

-n = Value at POR

bit 15-7

bit 6

Unimplemented: Read as ‘0’

USB1IF: USB1 (USB OTG) Interrupt Flag Status bit

1= Interrupt request has occurred

0= Interrupt request has not occurred

bit 5-0

Unimplemented: Read as ‘0’

 2010 Microchip Technology Inc.

DS39940D-page 81

PIC24FJ64GB004 FAMILY

REGISTER 7-11: IEC0: INTERRUPT ENABLE CONTROL REGISTER 0

U-0

—

U-0

—

R/W-0

AD1IE

R/W-0

T3IE

U1TXIE

U1RXIE

SPI1IE

SPF1IE

bit 15

bit 8

R/W-0

T2IE

R/W-0

OC2IE

R/W-0

IC2IE

U-0

—

R/W-0

T1IE

R/W-0

OC1IE

R/W-0

IC1IE

R/W-0

INT0IE

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15-14

bit 13

Unimplemented: Read as ‘0’

AD1IE: A/D Conversion Complete Interrupt Enable bit

1= Interrupt request is enabled

0= Interrupt request is not enabled

bit 12

bit 11

bit 10

bit 9

U1TXIE: UART1 Transmitter Interrupt Enable bit

1= Interrupt request is enabled

0= Interrupt request is not enabled

U1RXIE: UART1 Receiver Interrupt Enable bit

1= Interrupt request is enabled

0= Interrupt request is not enabled

SPI1IE: SPI1 Transfer Complete Interrupt Enable bit

1= Interrupt request is enabled

0= Interrupt request is not enabled

SPF1IE: SPI1 Fault Interrupt Enable bit

1= Interrupt request is enabled

0= Interrupt request is not enabled

bit 8

T3IE: Timer3 Interrupt Enable bit

1= Interrupt request is enabled

0= Interrupt request is not enabled

bit 7

T2IE: Timer2 Interrupt Enable bit

1= Interrupt request is enabled

0= Interrupt request is not enabled

bit 6

OC2IE: Output Compare Channel 2 Interrupt Enable bit

1= Interrupt request is enabled

0= Interrupt request is not enabled

bit 5

IC2IE: Input Capture Channel 2 Interrupt Enable bit

1= Interrupt request is enabled

0= Interrupt request is not enabled

bit 4

bit 3

Unimplemented: Read as ‘0’

T1IE: Timer1 Interrupt Enable bit

1= Interrupt request is enabled

0= Interrupt request is not enabled

bit 2

bit 1

bit 0

OC1IE: Output Compare Channel 1 Interrupt Enable bit

1= Interrupt request is enabled

0= Interrupt request is not enabled

IC1IE: Input Capture Channel 1 Interrupt Enable bit

1= Interrupt request is enabled

0= Interrupt request is not enabled

INT0IE: External Interrupt 0 Enable bit

1= Interrupt request is enabled

0= Interrupt request is not enabled

DS39940D-page 82

 2010 Microchip Technology Inc.

PIC24FJ64GB004 FAMILY

REGISTER 7-12: IEC1: INTERRUPT ENABLE CONTROL REGISTER 1

R/W-0

INT2IE⁽¹⁾

R/W-0

T5IE

R/W-0

T4IE

R/W-0

OC4IE

R/W-0

OC3IE

U-0

—

U2TXIE

U2RXIE

bit 15

bit 8

U-0

—

U-0

—

U-0

—

R/W-0

INT1IE⁽¹⁾

R/W-0

CNIE

R/W-0

CMIE

R/W-0

MI2C1IE

SI2C1IE

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

-n = Value at POR

bit 15

bit 14

bit 13

bit 12

bit 11

bit 10

bit 9

U2TXIE: UART2 Transmitter Interrupt Enable bit

1= Interrupt request is enabled

0= Interrupt request is not enabled

U2RXIE: UART2 Receiver Interrupt Enable bit

1= Interrupt request is enabled

0= Interrupt request is not enabled

INT2IE: External Interrupt 2 Enable bit⁽¹⁾

1= Interrupt request is enabled

0= Interrupt request is not enabled

T5IE: Timer5 Interrupt Enable bit

1= Interrupt request is enabled

0= Interrupt request is not enabled

T4IE: Timer4 Interrupt Enable bit

1= Interrupt request is enabled

0= Interrupt request is not enabled

OC4IE: Output Compare Channel 4 Interrupt Enable bit

1= Interrupt request is enabled

0= Interrupt request is not enabled

OC3IE: Output Compare Channel 3 Interrupt Enable bit

1= Interrupt request is enabled

0= Interrupt request is not enabled

bit 8-5

bit 4

Unimplemented: Read as ‘0’

INT1IE: External Interrupt 1 Enable bit⁽¹⁾

1= Interrupt request is enabled

0= Interrupt request is not enabled

bit 3

bit 2

bit 1

bit 0

CNIE: Input Change Notification Interrupt Enable bit

1= Interrupt request is enabled

0= Interrupt request is not enabled

CMIE: Comparator Interrupt Enable bit

1= Interrupt request is enabled

0= Interrupt request is not enabled

MI2C1IE: Master I2C1 Event Interrupt Enable bit

1= Interrupt request is enabled

0= Interrupt request is not enabled

SI2C1IE: Slave I2C1 Event Interrupt Enable bit

1= Interrupt request is enabled

0= Interrupt request is not enabled

Note 1: If an external interrupt is enabled, the interrupt input must also be configured to an available RPn or PRIx

pin. See Section 10.4 “Peripheral Pin Select (PPS)” for more information.

 2010 Microchip Technology Inc.

DS39940D-page 83

PIC24FJ64GB004 FAMILY

REGISTER 7-13: IEC2: INTERRUPT ENABLE CONTROL REGISTER 2

U-0

—

U-0

—

R/W-0

U-0

—

U-0

—

U-0

—

R/W-0

OC5IE

U-0

—

PMPIE

bit 15

bit 8

R/W-0

IC5IE

R/W-0

IC4IE

R/W-0

IC3IE

U-0

—

U-0

—

U-0

—

R/W-0

SPI2IE

SPF2IE

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15-14

bit 13

Unimplemented: Read as ‘0’

PMPIE: Parallel Master Port Interrupt Enable bit

1= Interrupt request is enabled

0= Interrupt request is not enabled

bit 12-10

bit 9

Unimplemented: Read as ‘0’

OC5IE: Output Compare Channel 5 Interrupt Enable bit

1= Interrupt request is enabled

0= Interrupt request is not enabled

bit 8

bit 7

Unimplemented: Read as ‘0’

IC5IE: Input Capture Channel 5 Interrupt Enable bit

1= Interrupt request is enabled

0= Interrupt request is not enabled

bit 6

bit 5

IC4IE: Input Capture Channel 4 Interrupt Enable bit

1= Interrupt request is enabled

0= Interrupt request is not enabled

IC3IE: Input Capture Channel 3 Interrupt Enable bit

1= Interrupt request is enabled

0= Interrupt request is not enabled

bit 4-2

bit 1

Unimplemented: Read as ‘0’

SPI2IE: SPI2 Event Interrupt Enable bit

1= Interrupt request is enabled

0= Interrupt request is not enabled

bit 0

SPF2IE: SPI2 Fault Interrupt Enable bit

1= Interrupt request is enabled

0= Interrupt request is not enabled

DS39940D-page 84

 2010 Microchip Technology Inc.

PIC24FJ64GB004 FAMILY

REGISTER 7-14: IEC3: INTERRUPT ENABLE CONTROL REGISTER 3

U-0

—

R/W-0

RTCIE

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

bit 15

bit 8

bit 0

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

R/W-0

U-0

—

MI2C2IE

SI2C2IE

bit 7

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15

bit 14

Unimplemented: Read as ‘0’

RTCIE: Real-Time Clock/Calendar Interrupt Enable bit

1= Interrupt request is enabled

0= Interrupt request is not enabled

bit 13-3

bit 2

Unimplemented: Read as ‘0’

MI2C2IE: Master I2C2 Event Interrupt Enable bit

1= Interrupt request is enabled

0= Interrupt request is not enabled

bit 1

bit 0

SI2C2IE: Slave I2C2 Event Interrupt Enable bit

1= Interrupt request is enabled

0= Interrupt request is not enabled

Unimplemented: Read as ‘0’

 2010 Microchip Technology Inc.

DS39940D-page 85

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REGISTER 7-15: IEC4: INTERRUPT ENABLE CONTROL REGISTER 4

U-0

—

U-0

—

R/W-0

U-0

—

U-0

—

U-0

—

U-0

—

R/W-0

LVDIE

CTMUIE

bit 15

bit 8

U-0

—

U-0

—

U-0

—

U-0

—

R/W-0

U-0

—

CRCIE

U2ERIE

U1ERIE

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15-14

bit 13

Unimplemented: Read as ‘0’

CTMUIE: CTMU Interrupt Enable bit

1= Interrupt request is enabled

0= Interrupt request is not enabled

bit 12-9

bit 8

Unimplemented: Read as ‘0’

LVDIE: Low-Voltage Detect Interrupt Enable bit

1= Interrupt request is enabled

0= Interrupt request is not enabled

bit 7-4

bit 3

Unimplemented: Read as ‘0’

CRCIE: CRC Generator Interrupt Enable bit

1= Interrupt request is enabled

0= Interrupt request is not enabled

bit 2

U2ERIE: UART2 Error Interrupt Enable bit

1= Interrupt request is enabled

0= Interrupt request is not enabled

bit 1

bit 0

U1ERIE: UART1 Error Interrupt Enable bit

1= Interrupt request is enabled

0= Interrupt request is not enabled

Unimplemented: Read as ‘0’

DS39940D-page 86

 2010 Microchip Technology Inc.

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REGISTER 7-16: IEC5: INTERRUPT ENABLE CONTROL REGISTER 5

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

bit 15

bit 8

bit 0

U-0

—

R/W-0

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

USB1IE

bit 7

Legend:

R = Readable bit

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

-n = Value at POR

bit 15-7

bit 6

Unimplemented: Read as ‘0’

USB1IE: USB1 (USB OTG) Interrupt Enable bit

1= Interrupt request is enabled

0= Interrupt request is not enabled

bit 5-0

Unimplemented: Read as ‘0’

 2010 Microchip Technology Inc.

DS39940D-page 87

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REGISTER 7-17: IPC0: INTERRUPT PRIORITY CONTROL REGISTER 0

U-0

—

R/W-1

T1IP2

R/W-0

T1IP1

R/W-0

T1IP0

U-0

—

R/W-1

R/W-0

OC1IP2

OC1IP1

OC1IP0

bit 15

bit 8

U-0

—

R/W-1

IC1IP2

R/W-0

IC1IP1

R/W-0

IC1IP0

U-0

—

R/W-1

R/W-0

INT0IP2

INT0IP1

INT0IP0

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

-n = Value at POR

bit 15

Unimplemented: Read as ‘0’

T1IP<2:0>: Timer1 Interrupt Priority bits

bit 14-12

111= Interrupt is Priority 7 (highest priority interrupt)

•

001= Interrupt is Priority 1

000= Interrupt source is disabled

bit 11

Unimplemented: Read as ‘0’

bit 10-8

OC1IP<2:0>: Output Compare Channel 1 Interrupt Priority bits

111= Interrupt is Priority 7 (highest priority interrupt)

•

001= Interrupt is Priority 1

000= Interrupt source is disabled

bit 7

Unimplemented: Read as ‘0’

bit 6-4

IC1IP<2:0>: Input Capture Channel 1 Interrupt Priority bits

111= Interrupt is Priority 7 (highest priority interrupt)

•

001= Interrupt is Priority 1

000= Interrupt source is disabled

bit 3

Unimplemented: Read as ‘0’

bit 2-0

INT0IP<2:0>: External Interrupt 0 Priority bits

111= Interrupt is Priority 7 (highest priority interrupt)

•

001= Interrupt is Priority 1

000= Interrupt source is disabled

DS39940D-page 88

 2010 Microchip Technology Inc.

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REGISTER 7-18: IPC1: INTERRUPT PRIORITY CONTROL REGISTER 1

U-0

—

R/W-1

T2IP2

R/W-0

T2IP1

R/W-0

T2IP0

U-0

—

R/W-1

R/W-0

OC2IP2

OC2IP1

OC2IP0

bit 15

bit 8

U-0

—

R/W-1

IC2IP2

R/W-0

IC2IP1

R/W-0

IC2IP0

U-0

—

U-0

—

U-0

—

U-0

—

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

-n = Value at POR

bit 15

Unimplemented: Read as ‘0’

T2IP<2:0>: Timer2 Interrupt Priority bits

bit 14-12

111= Interrupt is Priority 7 (highest priority interrupt)

•

001= Interrupt is Priority 1

000= Interrupt source is disabled

bit 11

Unimplemented: Read as ‘0’

bit 10-8

OC2IP<2:0>: Output Compare Channel 2 Interrupt Priority bits

111= Interrupt is Priority 7 (highest priority interrupt)

•

001= Interrupt is Priority 1

000= Interrupt source is disabled

bit 7

Unimplemented: Read as ‘0’

bit 6-4

IC2IP<2:0>: Input Capture Channel 2 Interrupt Priority bits

111= Interrupt is Priority 7 (highest priority interrupt)

•

001= Interrupt is Priority 1

000= Interrupt source is disabled

bit 3-0

Unimplemented: Read as ‘0’

 2010 Microchip Technology Inc.

DS39940D-page 89

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REGISTER 7-19: IPC2: INTERRUPT PRIORITY CONTROL REGISTER 2

U-0

—

R/W-1

R/W-0

U-0

—

R/W-1

R/W-0

U1RXIP2

U1RXIP1

U1RXIP0

SPI1IP2

SPI1IP1

SPI1IP0

bit 15

bit 8

U-0

—

R/W-1

R/W-0

U-0

—

R/W-1

T3IP2

R/W-0

T3IP1

R/W-0

T3IP0

SPF1IP2

SPF1IP1

SPF1IP0

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

-n = Value at POR

bit 15

Unimplemented: Read as ‘0’

bit 14-12

U1RXIP<2:0>: UART1 Receiver Interrupt Priority bits

111= Interrupt is Priority 7 (highest priority interrupt)

•

001= Interrupt is Priority 1

000= Interrupt source is disabled

bit 11

Unimplemented: Read as ‘0’

bit 10-8

SPI1IP<2:0>: SPI1 Event Interrupt Priority bits

111= Interrupt is Priority 7 (highest priority interrupt)

•

001= Interrupt is Priority 1

000= Interrupt source is disabled

bit 7

Unimplemented: Read as ‘0’

bit 6-4

SPF1IP<2:0>: SPI1 Fault Interrupt Priority bits

111= Interrupt is Priority 7 (highest priority interrupt)

•

001= Interrupt is Priority 1

000= Interrupt source is disabled

bit 3

Unimplemented: Read as ‘0’

bit 2-0

T3IP<2:0>: Timer3 Interrupt Priority bits

111= Interrupt is Priority 7 (highest priority interrupt)

•

001= Interrupt is Priority 1

000= Interrupt source is disabled

DS39940D-page 90

 2010 Microchip Technology Inc.

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REGISTER 7-20: IPC3: INTERRUPT PRIORITY CONTROL REGISTER 3

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

bit 15

bit 8

U-0

—

R/W-1

R/W-0

U-0

—

R/W-1

R/W-0

AD1IP2

AD1IP1

AD1IP0

U1TXIP2

U1TXIP1

U1TXIP0

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

-n = Value at POR

bit 15-7

bit 6-4

Unimplemented: Read as ‘0’

AD1IP<2:0>: A/D Conversion Complete Interrupt Priority bits

111= Interrupt is Priority 7 (highest priority interrupt)

•

001= Interrupt is Priority 1

000= Interrupt source is disabled

bit 3

Unimplemented: Read as ‘0’

bit 2-0

U1TXIP<2:0>: UART1 Transmitter Interrupt Priority bits

111= Interrupt is Priority 7 (highest priority interrupt)

•

001= Interrupt is Priority 1

000= Interrupt source is disabled

 2010 Microchip Technology Inc.

DS39940D-page 91

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REGISTER 7-21: IPC4: INTERRUPT PRIORITY CONTROL REGISTER 4

U-0

—

R/W-1

CNIP2

R/W-0

CNIP1

R/W-0

CNIP0

U-0

—

R/W-1

CMIP2

R/W-0

CMIP1

R/W-0

CMIP0

bit 15

bit 8

U-0

—

R/W-1

R/W-0

U-0

—

R/W-1

R/W-0

MI2C1IP2

MI2C1IP1

MI2C1IP0

SI2C1IP2

SI2C1IP1

SI2C1IP0

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15

Unimplemented: Read as ‘0’

bit 14-12

CNIP<2:0>: Input Change Notification Interrupt Priority bits

111= Interrupt is Priority 7 (highest priority interrupt)

•

001= Interrupt is Priority 1

000= Interrupt source is disabled

bit 11

Unimplemented: Read as ‘0’

bit 10-8

CMIP<2:0>: Comparator Interrupt Priority bits

111= Interrupt is Priority 7 (highest priority interrupt)

•

001= Interrupt is Priority 1

000= Interrupt source is disabled

bit 7

Unimplemented: Read as ‘0’

bit 6-4

MI2C1IP<2:0>: Master I2C1 Event Interrupt Priority bits

111= Interrupt is Priority 7 (highest priority interrupt)

•

001= Interrupt is Priority 1

000= Interrupt source is disabled

bit 3

Unimplemented: Read as ‘0’

bit 2-0

SI2C1IP<2:0>: Slave I2C1 Event Interrupt Priority bits

111= Interrupt is Priority 7 (highest priority interrupt)

•

001= Interrupt is Priority 1

000= Interrupt source is disabled

DS39940D-page 92

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REGISTER 7-22: IPC5: INTERRUPT PRIORITY CONTROL REGISTER 5

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

bit 15

bit 8

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

R/W-1

R/W-0

INT1IP2

INT1IP1

INT1IP0

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15-3

bit 2-0

Unimplemented: Read as ‘0’

INT1IP<2:0>: External Interrupt 1 Priority bits

111= Interrupt is Priority 7 (highest priority interrupt)

•

001= Interrupt is Priority 1

000= Interrupt source is disabled

 2010 Microchip Technology Inc.

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REGISTER 7-23: IPC6: INTERRUPT PRIORITY CONTROL REGISTER 6

U-0

—

R/W-1

T4IP2

R/W-0

T4IP1

R/W-0

T4IP0

U-0

—

R/W-1

R/W-0

OC4IP2

OC4IP1

OC4IP0

bit 15

bit 8

U-0

—

R/W-1

R/W-0

U-0

—

U-0

—

U-0

—

U-0

—

OC3IP2

OC3IP1

OC3IP0

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

-n = Value at POR

bit 15

Unimplemented: Read as ‘0’

T4IP<2:0>: Timer4 Interrupt Priority bits

bit 14-12

111= Interrupt is Priority 7 (highest priority interrupt)

•

001= Interrupt is Priority 1

000= Interrupt source is disabled

bit 11

Unimplemented: Read as ‘0’

bit 10-8

OC4IP<2:0>: Output Compare Channel 4 Interrupt Priority bits

111= Interrupt is Priority 7 (highest priority interrupt)

•

001= Interrupt is Priority 1

000= Interrupt source is disabled

bit 7

Unimplemented: Read as ‘0’

bit 6-4

OC3IP<2:0>: Output Compare Channel 3 Interrupt Priority bits

111= Interrupt is Priority 7 (highest priority interrupt)

•

001= Interrupt is Priority 1

000= Interrupt source is disabled

bit 3-0

Unimplemented: Read as ‘0’

DS39940D-page 94

 2010 Microchip Technology Inc.

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REGISTER 7-24: IPC7: INTERRUPT PRIORITY CONTROL REGISTER 7

U-0

—

R/W-1

R/W-0

U-0

—

R/W-1

R/W-0

U2TXIP2

U2TXIP1

U2TXIP0

U2RXIP2

U2RXIP1

U2RXIP0

bit 15

bit 8

U-0

—

R/W-1

R/W-0

U-0

—

R/W-1

T5IP2

R/W-0

T5IP1

R/W-0

T5IP0

INT2IP2

INT2IP1

INT2IP0

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

-n = Value at POR

bit 15

Unimplemented: Read as ‘0’

bit 14-12

U2TXIP<2:0>: UART2 Transmitter Interrupt Priority bits

111= Interrupt is Priority 7 (highest priority interrupt)

•

001= Interrupt is Priority 1

000= Interrupt source is disabled

bit 11

Unimplemented: Read as ‘0’

bit 10-8

U2RXIP<2:0>: UART2 Receiver Interrupt Priority bits

111= Interrupt is Priority 7 (highest priority interrupt)

•

001= Interrupt is Priority 1

000= Interrupt source is disabled

bit 7

Unimplemented: Read as ‘0’

bit 6-4

INT2IP<2:0>: External Interrupt 2 Priority bits

111= Interrupt is Priority 7 (highest priority interrupt)

•

001= Interrupt is Priority 1

000= Interrupt source is disabled

bit 3

Unimplemented: Read as ‘0’

bit 2-0

T5IP<2:0>: Timer5 Interrupt Priority bits

111= Interrupt is Priority 7 (highest priority interrupt)

•

001= Interrupt is Priority 1

000= Interrupt source is disabled

 2010 Microchip Technology Inc.

DS39940D-page 95

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REGISTER 7-25: IPC8: INTERRUPT PRIORITY CONTROL REGISTER 8

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

bit 15

bit 8

U-0

—

R/W-1

R/W-0

U-0

—

R/W-1

R/W-0

SPI2IP2

SPI2IP1

SPI2IP0

SPF2IP2

SPF2IP1

SPF2IP0

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

-n = Value at POR

bit 15-7

bit 6-4

Unimplemented: Read as ‘0’

SPI2IP<2:0>: SPI2 Event Interrupt Priority bits

111= Interrupt is Priority 7 (highest priority interrupt)

•

001= Interrupt is Priority 1

000= Interrupt source is disabled

bit 3

Unimplemented: Read as ‘0’

bit 2-0

SPF2IP<2:0>: SPI2 Fault Interrupt Priority bits

111= Interrupt is Priority 7 (highest priority interrupt)

•

001= Interrupt is Priority 1

000= Interrupt source is disabled

DS39940D-page 96

 2010 Microchip Technology Inc.

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REGISTER 7-26: IPC9: INTERRUPT PRIORITY CONTROL REGISTER 9

U-0

—

R/W-1

IC5IP2

R/W-0

IC5IP1

R/W-0

IC5IP0

U-0

—

R/W-1

IC4IP2

R/W-0

IC4IP1

R/W-0

IC4IP0

bit 15

bit 8

U-0

—

R/W-1

IC3IP2

R/W-0

IC3IP1

R/W-0

IC3IP0

U-0

—

U-0

—

U-0

—

U-0

—

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

-n = Value at POR

bit 15

Unimplemented: Read as ‘0’

bit 14-12

IC5IP<2:0>: Input Capture Channel 5 Interrupt Priority bits

111= Interrupt is Priority 7 (highest priority interrupt)

•

001= Interrupt is Priority 1

000= Interrupt source is disabled

bit 11

Unimplemented: Read as ‘0’

bit 10-8

IC4IP<2:0>: Input Capture Channel 4 Interrupt Priority bits

111= Interrupt is Priority 7 (highest priority interrupt)

•

001= Interrupt is Priority 1

000= Interrupt source is disabled

bit 7

Unimplemented: Read as ‘0’

bit 6-4

IC3IP<2:0>: Input Capture Channel 3 Interrupt Priority bits

111= Interrupt is Priority 7 (highest priority interrupt)

•

001= Interrupt is Priority 1

000= Interrupt source is disabled

bit 3-0

Unimplemented: Read as ‘0’

 2010 Microchip Technology Inc.

DS39940D-page 97

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REGISTER 7-27: IPC10: INTERRUPT PRIORITY CONTROL REGISTER 10

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

bit 15

bit 8

bit 0

U-0

—

R/W-1

R/W-0

U-0

—

U-0

—

U-0

—

U-0

—

OC5IP2

OC5IP1

OC5IP0

bit 7

Legend:

R = Readable bit

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

-n = Value at POR

bit 15-7

bit 6-4

Unimplemented: Read as ‘0’

OC5IP<2:0>: Output Compare Channel 5 Interrupt Priority bits

111= Interrupt is Priority 7 (highest priority interrupt)

•

001= Interrupt is Priority 1

000= Interrupt source is disabled

bit 3-0

Unimplemented: Read as ‘0’

DS39940D-page 98

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REGISTER 7-28: IPC11: INTERRUPT PRIORITY CONTROL REGISTER 11

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

bit 15

bit 8

bit 0

U-0

—

R/W-1

R/W-0

U-0

—

U-0

—

U-0

—

U-0

—

PMPIP2

PMPIP1

PMPIP0

bit 7

Legend:

R = Readable bit

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

-n = Value at POR

bit 15-7

bit 6-4

Unimplemented: Read as ‘0’

PMPIP<2:0>: Parallel Master Port Interrupt Priority bits

111= Interrupt is Priority 7 (highest priority interrupt)

•

001= Interrupt is Priority 1

000= Interrupt source is disabled

bit 3-0

Unimplemented: Read as ‘0’

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REGISTER 7-29: IPC12: INTERRUPT PRIORITY CONTROL REGISTER 12

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

R/W-1

R/W-0

MI2C2IP2

MI2C2IP1

MI2C2IP0

bit 15

bit 8

U-0

—

R/W-1

R/W-0

U-0

—

U-0

—

U-0

—

U-0

—

SI2C2IP2

SI2C2IP1

SI2C2IP0

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

-n = Value at POR

bit 15-11

bit 10-8

Unimplemented: Read as ‘0’

MI2C2IP<2:0>: Master I2C2 Event Interrupt Priority bits

111= Interrupt is Priority 7 (highest priority interrupt)

•

001= Interrupt is Priority 1

000= Interrupt source is disabled

bit 7

Unimplemented: Read as ‘0’

bit 6-4

SI2C2IP<2:0>: Slave I2C2 Event Interrupt Priority bits

111= Interrupt is Priority 7 (highest priority interrupt)

•

001= Interrupt is Priority 1

000= Interrupt source is disabled

bit 3-0

Unimplemented: Read as ‘0’

DS39940D-page 100

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REGISTER 7-30: IPC15: INTERRUPT PRIORITY CONTROL REGISTER 15

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

R/W-1

R/W-0

RTCIP2

RTCIP1

RTCIP0

bit 15

bit 8

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15-11

bit 10-8

Unimplemented: Read as ‘0’

RTCIP<2:0>: Real-Time Clock/Calendar Interrupt Priority bits

111= Interrupt is Priority 7 (highest priority interrupt)

•

001= Interrupt is Priority 1

000= Interrupt source is disabled

bit 7-0

Unimplemented: Read as ‘0’

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REGISTER 7-31: IPC16: INTERRUPT PRIORITY CONTROL REGISTER 16

U-0

—

R/W-1

R/W-0

U-0

—

R/W-1

R/W-0

CRCIP2

CRCIP1

CRCIP0

U2ERIP2

U2ERIP1

U2ERIP0

bit 15

bit 8

U-0

—

R/W-1

R/W-0

U-0

—

U-0

—

U-0

—

U-0

—

U1ERIP2

U1ERIP1

U1ERIP0

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

-n = Value at POR

bit 15

Unimplemented: Read as ‘0’

bit 14-12

CRCIP<2:0>: CRC Generator Error Interrupt Priority bits

111= Interrupt is Priority 7 (highest priority interrupt)

•

001= Interrupt is Priority 1

000= Interrupt source is disabled

bit 11

Unimplemented: Read as ‘0’

bit 10-8

U2ERIP<2:0>: UART2 Error Interrupt Priority bits

111= Interrupt is Priority 7 (highest priority interrupt)

•

001= Interrupt is Priority 1

000= Interrupt source is disabled

bit 7

Unimplemented: Read as ‘0’

bit 6-4

U1ERIP<2:0>: UART1 Error Interrupt Priority bits

111= Interrupt is Priority 7 (highest priority interrupt)

•

001= Interrupt is Priority 1

000= Interrupt source is disabled

bit 3-0

Unimplemented: Read as ‘0’

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REGISTER 7-32: IPC18: INTERRUPT PRIORITY CONTROL REGISTER 18

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

bit 15

bit 8

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

R/W-1

R/W-0

LVDIP2

LVDIP1

LVDIP0

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15-3

bit 2-0

Unimplemented: Read as ‘0’

LVDIP<2:0>: Low-Voltage Detect Interrupt Priority bits

111= Interrupt is Priority 7 (highest priority interrupt)

•

001= Interrupt is Priority 1

000= Interrupt source is disabled

REGISTER 7-33: IPC19: INTERRUPT PRIORITY CONTROL REGISTER 19

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

bit 15

bit 8

bit 0

U-0

—

R/W-1

R/W-0

U-0

—

U-0

—

U-0

—

U-0

—

CTMUIP2

CTMUIP1

CTMUIP0

bit 7

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15-7

bit 6-4

Unimplemented: Read as ‘0’

CTMUIP<2:0>: CTMU Interrupt Priority bits

111= Interrupt is Priority 7 (highest priority interrupt)

•

001= Interrupt is Priority 1

000= Interrupt source is disabled

bit 3-0

Unimplemented: Read as ‘0’

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REGISTER 7-34: IPC21: INTERRUPT PRIORITY CONTROL REGISTER 21

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

R/W-0

USB1IP2

USB1IP1

USB1IP0

bit 15

bit 8

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15-11

bit 10-8

Unimplemented: Read as ‘0’

USB1IP<2:0>: USB Interrupt Priority bits

111= Interrupt is Priority 7 (highest priority interrupt)

•

001= Interrupt is Priority 1

000= Interrupt source is disabled

bit 7-0

Unimplemented: Read as ‘0’

DS39940D-page 104

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REGISTER 7-35: INTTREG: INTERRUPT CONTROL AND STATUS REGISTER

R-0

U-0

—

R/W-0

U-0

—

R-0

CPUIRQ

VHOLD

ILR3

ILR2

ILR1

ILR0

bit 15

bit 8

U-0

—

R-0

VECNUM6

VECNUM5

VECNUM4

VECNUM3

VECNUM2

VECNUM1

VECNUM0

bit 0

bit 7

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15

CPUIRQ: Interrupt Request from Interrupt Controller CPU bit

1= An interrupt request has occurred but has not yet been Acknowledged by the CPU; this happens

when the CPU priority is higher than the interrupt priority

0= No interrupt request is unacknowledged

bit 14

bit 13

Unimplemented: Read as ‘0’

VHOLD: Vector Number Capture Configuration bit

1= The VECNUM bits contain the value of the highest priority pending interrupt

0= The VECNUM bits contain the value of the last Acknowledged interrupt (i.e., the last interrupt that

has occurred with higher priority than the CPU, even if other interrupts are pending)

bit 12

Unimplemented: Read as ‘0’

bit 11-8

ILR<3:0>: New CPU Interrupt Priority Level bits

1111= CPU Interrupt Priority Level is 15

•

0001= CPU Interrupt Priority Level is 1

0000= CPU Interrupt Priority Level is 0

bit 7

Unimplemented: Read as ‘0’

bit 6-0

VECNUM<6:0>: Pending Interrupt Vector ID bits (pending vector number is VECNUM + 8)

0111111= Interrupt vector pending is Number 135

•

0000001= Interrupt vector pending is Number 9

0000000= Interrupt vector pending is Number 8

 2010 Microchip Technology Inc.

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7.4.3

TRAP SERVICE ROUTINE

7.4

Interrupt Setup Procedures

A Trap Service Routine (TSR) is coded like an ISR,

except that the appropriate trap status flag in the

INTCON1 register must be cleared to avoid re-entry

into the TSR.

7.4.1

INITIALIZATION

To configure an interrupt source:

1. Set the NSTDIS control bit (INTCON1<15>) if

nested interrupts are not desired.

7.4.4

INTERRUPT DISABLE

2. Select the user-assigned priority level for the

interrupt source by writing the control bits in the

appropriate IPCx register. The priority level will

depend on the specific application and type of

interrupt source. If multiple priority levels are not

desired, the IPCx register control bits for all

enabled interrupt sources may be programmed

to the same non-zero value.

All user interrupts can be disabled using the following

procedure:

1. Push the current SR value onto the software

stack using the PUSHinstruction.

2. Force the CPU to Priority Level 7 by inclusive

ORing the value OEh with SRL.

To enable user interrupts, the POPinstruction may be

Note: At a device Reset, the IPCx registers are

initialized, such that all user interrupt

sources are assigned to Priority Level 4.

used to restore the previous SR value.

Note that only user interrupts with a priority level of 7 or

less can be disabled. Trap sources (Level 8-15) cannot

be disabled.

3. Clear the interrupt flag status bit associated with

the peripheral in the associated IFSx register.

The DISI instruction provides a convenient way to

disable interrupts of Priority Levels 1-6 for a fixed

period of time. Level 7 interrupt sources are not

disabled by the DISIinstruction.

4. Enable the interrupt source by setting the

interrupt enable control bit associated with the

source in the appropriate IECx register.

7.4.2

INTERRUPT SERVICE ROUTINE

The method that is used to declare an ISR and initialize

the IVT with the correct vector address will depend on

the programming language (i.e., ‘C’ or assembler) and

the language development toolsuite that is used to

develop the application. In general, the user must clear

the interrupt flag in the appropriate IFSx register for the

source of the interrupt that the ISR handles. Otherwise,

the ISR will be re-entered immediately after exiting the

routine. If the ISR is coded in assembly language, it

must be terminated using a RETFIE instruction to

unstack the saved PC value, SRL value and old CPU

priority level.

DS39940D-page 106

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PIC24FJ64GB004 FAMILY

• An on-chip USB PLL block to provide a stable 48 MHz

clock for the USB module, as well as a range of

frequency options for the system clock

8.0

OSCILLATOR

CONFIGURATION

• Software-controllable switching between various

clock sources

Note:

This data sheet summarizes the features

of this group of PIC24F devices. It is not

intended to be a comprehensive reference

source. For more information, refer to the

“PIC24F Family Reference Manual”,

Section 6. “Oscillator” (DS39700).

• Software-controllable postscaler for selective

clocking of CPU for system power savings

• A Fail-Safe Clock Monitor (FSCM) that detects

clock failure and permits safe application recovery

or shutdown

The oscillator system for PIC24FJ64GB004 family

devices has the following features:

• A separate and independently configurable system

clock output for synchronizing external hardware

• A total of four external and internal oscillator options

as clock sources, providing 11 different clock modes

A simplified diagram of the oscillator system is shown

in Figure 8-1.

FIGURE 8-1:

PIC24FJ64GB004 FAMILY CLOCK DIAGRAM

PIC24FJ64GB004 Family

48 MHz USB Clock

REFOCON<15:8>

Primary Oscillator

XT, HS, EC

OSCO

OSCI

USB PLL

XTPLL, HSPLL

ECPLL,FRCPLL

PLL

&

DIV

Reference Clock

Generator

REFO

PLLDIV<2:0>

CPDIV<1:0>

8 MHz

4 MHz

FRC

Oscillator

FRCDIV

FRC

8 MHz

(nominal)

Peripherals

CLKDIV<10:8>

CLKO

CPU

LPRC

SOSC

LPRC

Oscillator

31 kHz (nominal)

Secondary Oscillator

CLKDIV<14:12>

SOSCO

SOSCI

SOSCEN

Enable

Oscillator

Clock Control Logic

Fail-Safe

Clock

Monitor

WDT, PWRT

Clock Source Option

for Other Modules

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8.1

CPU Clocking Scheme

8.2

Initial Configuration on POR

The system clock source can be provided by one of

four sources:

The oscillator source (and operating mode) that is used

at a device Power-on Reset event is selected using Con-

figuration bit settings. The oscillator Configuration bit

settings are located in the Configuration registers in the

program memory (refer to Section 26.1 “Configuration

Bits” for further details). The Primary Oscillator

Configuration bits, POSCMD<1:0> (Configuration

Word 2<1:0>), and the Initial Oscillator Select Configu-

ration bits, FNOSC<2:0> (Configuration Word 2<10:8>),

select the oscillator source that is used at a Power-on

Reset. The FRC Primary Oscillator with Postscaler

(FRCDIV) is the default (unprogrammed) selection. The

secondary oscillator, or one of the internal oscillators,

may be chosen by programming these bit locations.

• Primary Oscillator (POSC) on the OSCI and

OSCO pins

• Secondary Oscillator (SOSC) on the SOSCI and

SOSCO pins

• Fast Internal RC (FRC) Oscillator

• Low-Power Internal RC (LPRC) Oscillator

The primary oscillator and FRC sources have the

option of using the internal USB PLL block, which

generates both the USB module clock and a separate

system clock from the 96 MHz PLL. Refer to

Section 8.5 “Oscillator Modes and USB Operation”

for additional information.

The Configuration bits allow users to choose between

the various clock modes, shown in Table 8-1.

The Fast Internal RC (FRC) provides an 8 MHz clock

source. It can optionally be reduced by the pro-

grammable clock divider to provide a range of system

clock frequencies.

8.2.1

CLOCK SWITCHING MODE

CONFIGURATION BITS

The FCKSM Configuration bits (Configuration

Word 2<7:6>) are used to jointly configure device clock

switching and the Fail-Safe Clock Monitor (FSCM).

Clock switching is enabled only when FCKSM1 is

programmed (‘0’). The FSCM is enabled only when the

FCKSM<1:0> bits are both programmed (‘00’).

The selected clock source generates the processor

and peripheral clock sources. The processor clock

source is divided by two to produce the internal instruc-

tion cycle clock, FCY. In this document, the instruction

cycle clock is also denoted by FOSC/2. The internal

instruction cycle clock, FOSC/2, can be provided on the

OSCO I/O pin for some operating modes of the primary

oscillator.

TABLE 8-1:

CONFIGURATION BIT VALUES FOR CLOCK SELECTION

Oscillator Mode

Oscillator Source

POSCMD<1:0>

FNOSC<2:0>

Notes

1, 2

Fast RC Oscillator with Postscaler

(FRCDIV)

Internal

11

111

(Reserved)

Internal

xx

11

110

101

100

1

Low-Power RC Oscillator (LPRC)

Secondary (Timer1) Oscillator

(SOSC)

Secondary

Primary Oscillator (XT) with PLL

Module (XTPLL)

Primary

01

00

011

Primary Oscillator (EC) with PLL

Module (ECPLL)

Primary Oscillator (HS)

Primary Oscillator (XT)

Primary Oscillator (EC)

Primary

Internal

10

01

00

11

010

001

Fast RC Oscillator with PLL Module

(FRCPLL)

1

Fast RC Oscillator (FRC)

Internal

11

000

Note 1: OSCO pin function is determined by the OSCIOFCN Configuration bit.

2: This is the default oscillator mode for an unprogrammed (erased) device.

DS39940D-page 108

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The OSCCON register (Register 8-1) is the main con-

trol register for the oscillator. It controls clock source

switching and allows the monitoring of clock sources.

8.3

Control Registers

The operation of the oscillator is controlled by three

Special Function Registers (SFRs):

The CLKDIV register (Register 8-2) controls the

features associated with Doze mode, as well as the

postscaler for the FRC Oscillator. The OSCTUN

register (Register 8-3) allows the user to fine tune the

FRC Oscillator over a range of approximately ±12%.

• OSCCON

• CLKDIV

• OSCTUN

REGISTER 8-1:

OSCCON: OSCILLATOR CONTROL REGISTER

U-0

—

R-0

U-0

—

R/W-x⁽¹⁾

NOSC2

R/W-x⁽¹⁾

NOSC1

R/W-x⁽¹⁾

NOSC0

COSC2

COSC1

COSC0

bit 15

bit 8

R/SO-0

R/W-0

IOLOCK⁽²⁾

R-0⁽³⁾

LOCK

U-0

—

R/CO-0

CF

R/W-0

CLKLOCK

bit 7

POSCEN

SOSCEN

OSWEN

bit 0

Legend:

CO = Clearable Only bit

W = Writable bit

SO = Settable Only bit

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

R = Readable bit

-n = Value at POR

‘1’ = Bit is set

bit 15

Unimplemented: Read as ‘0’

bit 14-12

COSC<2:0>: Current Oscillator Selection bits

111= Fast RC Oscillator with Postscaler (FRCDIV)

110= Reserved

101= Low-Power RC Oscillator (LPRC)

100= Secondary Oscillator (SOSC)

011= Primary Oscillator with PLL module (XTPLL, HSPLL, ECPLL)

010= Primary Oscillator (XT, HS, EC)

001= Fast RC Oscillator with Postscaler and PLL module (FRCPLL)

000= Fast RC Oscillator (FRC)

bit 11

Unimplemented: Read as ‘0’

bit 10-8

NOSC<2:0>: New Oscillator Selection bits⁽¹⁾

111= Fast RC Oscillator with Postscaler (FRCDIV)

110= Reserved

101= Low-Power RC Oscillator (LPRC)

100= Secondary Oscillator (SOSC)

011= Primary Oscillator with PLL module (XTPLL, HSPLL, ECPLL)

010= Primary Oscillator (XT, HS, EC)

001= Fast RC Oscillator with Postscaler and PLL module (FRCPLL)

000= Fast RC Oscillator (FRC)

Note 1: Reset values for these bits are determined by the FNOSC Configuration bits.

2: The state of the IOLOCK bit can only be changed once an unlocking sequence has been executed. In

addition, if the IOL1WAY Configuration bit is ‘1’, once the IOLOCK bit is set, it cannot be cleared.

3: Also resets to ‘0’ during any valid clock switch or whenever a non-PLL Clock mode is selected.

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REGISTER 8-1:

OSCCON: OSCILLATOR CONTROL REGISTER (CONTINUED)

bit 7

CLKLOCK: Clock Selection Lock Enabled bit

If FSCM is enabled (FCKSM1 = 1):

1= Clock and PLL selections are locked

0= Clock and PLL selections are not locked and may be modified by setting the OSWEN bit

If FSCM is disabled (FCKSM1 = 0):

Clock and PLL selections are never locked and may be modified by setting the OSWEN bit.

bit 6

bit 5

IOLOCK: I/O Lock Enable bit⁽²⁾

1= I/O lock is active

0= I/O lock is not active

LOCK: PLL Lock Status bit⁽³⁾

1= PLL module is in lock or PLL module start-up timer is satisfied

0= PLL module is out of lock, PLL start-up timer is running or PLL is disabled

bit 4

bit 3

Unimplemented: Read as ‘0’

CF: Clock Fail Detect bit

1= FSCM has detected a clock failure

0= No clock failure has been detected

bit 2

bit 1

bit 0

POSCEN: Primary Oscillator Sleep Enable bit

1= Primary oscillator continues to operate during Sleep mode

0= Primary oscillator disabled during Sleep mode

SOSCEN: 32 kHz Secondary Oscillator (SOSC) Enable bit

1= Enable secondary oscillator

0= Disable secondary oscillator

OSWEN: Oscillator Switch Enable bit

1= Initiate an oscillator switch to the clock source specified by the NOSC<2:0> bits

0= Oscillator switch is complete

Note 1: Reset values for these bits are determined by the FNOSC Configuration bits.

2: The state of the IOLOCK bit can only be changed once an unlocking sequence has been executed. In

addition, if the IOL1WAY Configuration bit is ‘1’, once the IOLOCK bit is set, it cannot be cleared.

3: Also resets to ‘0’ during any valid clock switch or whenever a non-PLL Clock mode is selected.

DS39940D-page 110

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REGISTER 8-2:

CLKDIV: CLOCK DIVIDER REGISTER

R/W-0

ROI

R/W-0

DOZEN⁽¹⁾

R/W-0

R/W-1

DOZE2

DOZE1

DOZE0

RCDIV2

RCDIV1

RCDIV0

bit 15

bit 8

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

R/W-0

CPDIV1

bit 7

R/W-0

CPDIV0

PLLEN

bit 0

Legend:

R = Readable bit

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

-n = Value at POR

bit 15

ROI: Recover on Interrupt bit

1= Interrupts clear the DOZEN bit and reset the CPU peripheral clock ratio to 1:1

0= Interrupts have no effect on the DOZEN bit

bit 14-12

DOZE<2:0>: CPU Peripheral Clock Ratio Select bits

111= 1:128

110= 1:64

101= 1:32

100= 1:16

011= 1:8

010= 1:4

001= 1:2

000= 1:1

bit 11

DOZEN: DOZE Enable bit⁽¹⁾

1= DOZE<2:0> bits specify the CPU peripheral clock ratio

0= CPU peripheral clock ratio is set to 1:1

bit 10-8

RCDIV<2:0>: FRC Postscaler Select bits

111= 31.25 kHz (divide-by-256)

110= 125 kHz (divide-by-64)

101= 250 kHz (divide-by-32)

100= 500 kHz (divide-by-16)

011= 1 MHz (divide-by-8)

010= 2 MHz (divide-by-4)

001= 4 MHz (divide-by-2)

000= 8 MHz (divide-by-1)

bit 7-6

CPDIV<1:0>: USB System Clock Select bits (postscaler select from 32 MHz clock branch)

11= 4 MHz (divide-by-8)⁽²⁾

10= 8 MHz (divide-by-4)⁽²⁾

01= 16 MHz (divide-by-2)

00= 32 MHz (divide-by-1)

bit 5

PLLEN: 96 MHz PLL Enable bit

1= Enable PLL

0= Disable PLL

bit 4-0

Unimplemented: Read as ‘0’

Note 1: This bit is automatically cleared when the ROI bit is set and an interrupt occurs.

2: This setting is not allowed while the USB module is enabled.

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REGISTER 8-3:

OSCTUN: FRC OSCILLATOR TUNE REGISTER

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

bit 15

bit 8

U-0

—

U-0

—

R/W-0

TUN5⁽¹⁾

R/W-0

TUN4⁽¹⁾

R/W-0

TUN3⁽¹⁾

R/W-0

TUN2⁽¹⁾

R/W-0

TUN1⁽¹⁾

R/W-0

TUN0⁽¹⁾

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15-6

bit 5-0

Unimplemented: Read as ‘0’

TUN<5:0>: FRC Oscillator Tuning bits⁽¹⁾

011111= Maximum frequency deviation

011110=



000001=

000000= Center frequency, oscillator is running at factory calibrated frequency

111111=



100001=

100000= Minimum frequency deviation

Note 1: Increments or decrements of TUN<5:0> may not change the FRC frequency in equal steps over the FRC

tuning range and may not be monotonic.

8.4.1

ENABLING CLOCK SWITCHING

8.4

Clock Switching Operation

To enable clock switching, the FCKSM Configuration

bits in CW2 must be programmed to ‘00’. (Refer to

Section 26.1 “Configuration Bits” for further details.)

If the FCKSM Configuration bits are unprogrammed

(‘1x’), the clock switching function and Fail-Safe Clock

Monitor function are disabled; this is the default setting.

With few limitations, applications are free to switch

between any of the four clock sources (POSC, SOSC,

FRC and LPRC) under software control and at any

time. To limit the possible side effects that could result

from this flexibility, PIC24F devices have a safeguard

lock built into the switching process.

The NOSCx control bits (OSCCON<10:8>) do not

control the clock selection when clock switching is dis-

abled. However, the COSCx bits (OSCCON<14:12>)

will reflect the clock source selected by the FNOSCx

Configuration bits.

Note:

The Primary Oscillator mode has three

different submodes (XT, HS and EC)

which are determined by the POSCMDx

Configuration bits. While an application

can switch to and from Primary Oscillator

mode in software, it cannot switch

between the different primary submodes

without reprogramming the device.

The OSWEN control bit (OSCCON<0>) has no effect

when clock switching is disabled; it is held at ‘0’ at all

times.

DS39940D-page 112

 2010 Microchip Technology Inc.

PIC24FJ64GB004 FAMILY

A recommended code sequence for a clock switch

includes the following:

8.4.2

OSCILLATOR SWITCHING

SEQUENCE

1. Disable interrupts during the OSCCON register

unlock and write sequence.

At a minimum, performing a clock switch requires this

basic sequence:

2. Execute the unlock sequence for the OSCCON

high byte by writing 78h and 9Ah to

1. If

desired,

read

the

COSCx

bits

(OSCCON<14:12>) to determine the current

oscillator source.

OSCCON<15:8>

instructions.

in

two

back-to-back

2. Perform the unlock sequence to allow a write to

the OSCCON register high byte.

3. Write new oscillator source to the NOSCx bits in

the instruction immediately following the unlock

sequence.

3. Write the appropriate value to the NOSCx bits

(OSCCON<10:8>) for the new oscillator source.

4. Execute the unlock sequence for the OSCCON

low byte by writing 46h and 57h to

OSCCON<7:0> in two back-to-back instructions.

4. Perform the unlock sequence to allow a write to

the OSCCON register low byte.

5. Set the OSWEN bit to initiate the oscillator

switch.

5. Set the OSWEN bit in the instruction immediately

following the unlock sequence.

Once the basic sequence is completed, the system

clock hardware responds automatically as follows:

6. Continue to execute code that is not

clock-sensitive (optional).

1. The clock switching hardware compares the

COSCx bits with the new value of the NOSCx

bits. If they are the same, then the clock switch

is a redundant operation. In this case, the

OSWEN bit is cleared automatically and the

clock switch is aborted.

7. Invoke an appropriate amount of software delay

(cycle counting) to allow the selected oscillator

and/or PLL to start and stabilize.

8. Check to see if OSWEN is ‘0’. If it is, the switch

was successful. If OSWEN is still set, then

check the LOCK bit to determine the cause of

failure.

2. If a valid clock switch has been initiated, the

LOCK (OSCCON<5>) and CF (OSCCON<3>)

bits are cleared.

The core sequence for unlocking the OSCCON register

and initiating a clock switch is shown in Example 8-1.

3. The new oscillator is turned on by the hardware

if it is not currently running. If a crystal oscillator

must be turned on, the hardware will wait until

the OST expires. If the new source is using the

PLL, then the hardware waits until a PLL lock is

detected (LOCK = 1).

EXAMPLE 8-1:

BASIC CODE SEQUENCE

FOR CLOCK SWITCHING

;Place the new oscillator selection in

W0

;OSCCONH (high byte) Unlock Sequence

4. The hardware waits for 10 clock cycles from the

new clock source and then performs the clock

switch.

MOV

MOV.b

#OSCCONH, w1

#0x78, w2

#0x9A, w3

w2, [w1]

5. The hardware clears the OSWEN bit to indicate a

successful clock transition. In addition, the

NOSCx bit values are transferred to the COSCx

bits.

w3, [w1]

;Set new oscillator selection

MOV.b WREG, OSCCONH

;OSCCONL (low byte) unlock sequence

6. The old clock source is turned off at this time,

with the exception of LPRC (if WDT or FSCM is

enabled) or SOSC (if SOSCEN remains set).

MOV

MOV.b

#OSCCONL, w1

#0x46, w2

#0x57, w3

w2, [w1]

Note 1: The processor will continue to execute

code throughout the clock switching

sequence. Timing-sensitive code should

not be executed during this time.

w3, [w1]

;Start oscillator switch operation

BSET OSCCON,#0

2: Direct clock switches between any

Primary Oscillator mode with PLL and

FRCPLL mode are not permitted. This

applies to clock switches in either direc-

tion. In these instances, the application

must switch to FRC mode as a transition

clock source between the two PLL

modes.

 2010 Microchip Technology Inc.

DS39940D-page 113

PIC24FJ64GB004 FAMILY

TABLE 8-2:

SYSTEM CLOCK OPTIONS

DURING USB OPERATION

8.5

Oscillator Modes and USB

Operation

MCU Clock Division

(CPDIV<1:0>)

Microcontroller

Clock Frequency

Because of the timing requirements imposed by USB,

an internal clock of 48 MHz is required at all times while

the USB module is enabled. Since this is well beyond the

maximum CPU clock speed, a method is provided to

internally generate both the USB and system clocks

from a single oscillator source. PIC24FJ64GB004 family

devices use the same clock structure as other PIC24FJ

devices, but include a two-branch PLL system to

generate the two clock signals.

None (00)

2 (01)

4 (10)

8 (11)

32 MHz

16 MHz

8 MHz

4 MHz

TABLE 8-3:

VALID PRIMARY OSCILLATOR

CONFIGURATIONS FOR USB

OPERATIONS

The USB PLL block is shown in Figure 8-2. In this

system, the input from the primary oscillator is divided

down by a PLL prescaler to generate a 4 MHz output.

This is used to drive an on-chip 96 MHz PLL frequency

multiplier to drive the two clock branches. One branch

uses a fixed, divide-by-2 frequency divider to generate

the 48 MHz USB clock. The other branch uses a fixed,

divide-by-3 frequency divider and configurable PLL

prescaler/divider to generate a range of system clock

frequencies. The CPDIV bits select the system clock

speed; available clock options are listed in Table 8-2.

Input Oscillator

Frequency

PLL Division

Clock Mode

(PLLDIV<2:0>)

48 MHz

32 MHz

24 MHz

20 MHz

16 MHz

12 MHz

8 MHz

ECPLL

12 (111)

8 (110)

6 (101)

5 (100)

4 (011)

3 (010)

2 (001)

1 (000)

ECPLL

HSPLL, ECPLL

XTPLL, ECPLL

The USB PLL prescaler does not automatically sense

the incoming oscillator frequency. The user must man-

ually configure the PLL divider to generate the required

4 MHz output using the PLLDIV<2:0> Configuration

bits. This limits the choices for primary oscillator

frequency to a total of 8 possibilities, shown in

Table 8-3.

4 MHz

FIGURE 8-2:

USB PLL BLOCK

PLLDIV<2:0>

48 MHz Clock

for USB Module

FNOSC<2:0>

 12

 8

 6

 5

 4

 3

 2

 1

111

110

101

100

011

010

001

000

 2

Input from

POSC

4 MHz

96 MHz

PLL

Input from

FRC

(4 MHz or

8 MHz)

 8

 4

 2

 1

11

PLL Output

for System Clock

32 MHz

10

01

 3

00

CPDIV<1:0>

• The Primary Oscillator/PLL modes are the only

oscillator configurations that permit USB opera-

tion. There is no provision to provide a separate

external clock source to the USB module.

8.5.1

CONSIDERATIONS FOR USB

OPERATION

When using the USB On-The-Go module in

PIC24FJ64GB004 family devices, users must always

observe these rules in configuring the system clock:

• All oscillator modes are available; however, USB

operation is not possible when these modes are

selected. They may still be useful in cases where

other power levels of operation are desirable and

the USB module is not needed (e.g., the application

is Sleeping and waiting for bus attachment).

• For USB operation, the selected clock source

(EC, HS or XT) must meet the USB clock

tolerance requirements.

DS39940D-page 114

 2010 Microchip Technology Inc.

PIC24FJ64GB004 FAMILY

In general, the crystal circuit connections should be as

short as possible. It is also good practice to surround

the crystal circuit with a ground loop or ground plane.

For more information on crystal circuit design, please

refer to Section 6 “Oscillator” (DS39700) of the

“PIC24F Family Reference Manual”. Additional infor-

mation is also available in these Microchip Application

Notes:

8.6

Secondary Oscillator (SOSC)

8.6.1

BASIC SOSC OPERATION

PIC24FJ64GB004 family devices do not have to set the

SOSCEN bit to use the secondary oscillator. Any module

requiring the SOSC (such as RTCC, Timer1 or DSWDT)

will automatically turn on the SOSC when the clock signal

is needed. The SOSC, however, has a long start-up time.

To avoid delays for peripheral start-up, the SOSC can be

manually started using the SOSCEN bit.

• AN826, “Crystal Oscillator Basics and Crystal

Selection for rfPIC^®and PICmicro^®Devices”

(DS00826)

• AN849, “Basic PICmicro^®Oscillator Design”

To use the secondary oscillator, the SOSCSEL<1:0>

bits (CW3<9:8>) must be configured in an oscillator

mode – either ‘11’ or ‘01’. Setting SOSCSEL to ‘00’

configures the SOSC pins for Digital mode, enabling

digital I/O functionality on the pins. Digital functionality

will not be available if the SOSC is configured in either

of the oscillator modes.

(DS00849).

8.7

Reference Clock Output

In addition to the CLKO output (FOSC/2) available in cer-

tain oscillator modes, the device clock in the

PIC24FJ64GB004 family devices can also be configured

to provide a reference clock output signal to a port pin.

This feature is available in all oscillator configurations

and allows the user to select a greater range of clock

submultiples to drive external devices in the application.

8.6.2

LOW-POWER SOSC OPERATION

The secondary oscillator can operate in two distinct

levels of power consumption based on device configu-

ration. In Low-Power mode, the oscillator operates in a

low drive strength, low-power state. By default, the

oscillator uses a higher drive strength, and therefore,

requires more power. The Secondary Oscillator Mode

Configuration bits, SOSCSEL<1:0> (CW3<9:8>),

determine the oscillator’s power mode. Programming

the SOSCSEL bits to ‘01’ selects low-power operation.

This reference clock output is controlled by the

REFOCON register (Register 8-4). Setting the ROEN

bit (REFOCON<15>) makes the clock signal available

on the REFO pin. The RODIV bits (REFOCON<11:8>)

enable the selection of 16 different clock divider

options.

The lower drive strength of this mode makes the SOSC

more sensitive to noise and requires a longer start-up

time. When Low-Power mode is used, care must be

taken in the design and layout of the SOSC circuit to

ensure that the oscillator starts up and oscillates

properly.

The ROSSLP and ROSEL bits (REFOCON<13:12>)

control the availability of the reference output during

Sleep mode. The ROSEL bit determines if the oscillator

on OSC1 and OSC2, or the current system clock

source, is used for the reference clock output. The

ROSSLP bit determines if the reference source is

available on REFO when the device is in Sleep mode.

8.6.3

EXTERNAL (DIGITAL) CLOCK

MODE (SCLKI)

To use the reference clock output in Sleep mode, both

the ROSSLP and ROSEL bits must be set. The device

clock must also be configured for one of the primary

modes (EC, HS or XT); otherwise, if the POSCEN bit is

not also set, the oscillator on OSC1 and OSC2 will be

powered down when the device enters Sleep mode.

Clearing the ROSEL bit allows the reference output

frequency to change as the system clock changes

during any clock switches.

The SOSC can also be configured to run from an

external 32 kHz clock source, rather than the internal

oscillator. In this mode, also referred to as Digital mode,

the clock source provided on the SCLKI pin is used to

clock any modules that are configured to use the

secondary oscillator. In this mode, the crystal driving

circuit is disabled and the SOSCEN bit (OSCCON<1>)

has no effect.

8.6.4

SOSC LAYOUT CONSIDERATIONS

The pinout limitations on low pin count devices, such as

those in the PIC24FJ64GB004 family, may make the

SOSC more susceptible to noise than other PIC24F

devices. Unless proper care is taken in the design and

layout of the SOSC circuit, this external noise may

introduce inaccuracies into the oscillator’s period.

 2010 Microchip Technology Inc.

DS39940D-page 115

PIC24FJ64GB004 FAMILY

REGISTER 8-4:

REFOCON: REFERENCE OSCILLATOR CONTROL REGISTER

R/W-0

ROEN

U-0

—

R/W-0

ROSSLP

ROSEL

RODIV3

RODIV2

RODIV1

RODIV0

bit 15

bit 8

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15

ROEN: Reference Oscillator Output Enable bit

1= Reference oscillator is enabled on REFO pin

0= Reference oscillator is disabled

bit 14

bit 13

Unimplemented: Read as ‘0’

ROSSLP: Reference Oscillator Output Stop in Sleep bit

1= Reference oscillator continues to run in Sleep

0= Reference oscillator is disabled in Sleep

bit 12

ROSEL: Reference Oscillator Source Select bit

1= Primary oscillator is used as the base clock. Note that the crystal oscillator must be enabled using

the FOSC<2:0> bits; the crystal maintains the operation in Sleep mode.

0= System clock used as the base clock; base clock reflects any clock switching of the device

bit 11-8

RODIV<3:0>: Reference Oscillator Divisor Select bits

1111= Base clock value divided by 32,768

1110= Base clock value divided by 16,384

1101= Base clock value divided by 8,192

1100= Base clock value divided by 4,096

1011= Base clock value divided by 2,048

1010= Base clock value divided by 1,024

1001= Base clock value divided by 512

1000= Base clock value divided by 256

0111= Base clock value divided by 128

0110= Base clock value divided by 64

0101= Base clock value divided by 32

0100= Base clock value divided by 16

0011= Base clock value divided by 8

0010= Base clock value divided by 4

0001= Base clock value divided by 2

0000= Base clock value

bit 7-0

Unimplemented: Read as ‘0’

DS39940D-page 116

 2010 Microchip Technology Inc.

PIC24FJ64GB004 FAMILY

The assembly syntax of the PWRSAV instruction is

shown in Example 9-1.

9.0

POWER-SAVING FEATURES

Note:

This data sheet summarizes the features

of this group of PIC24F devices. It is not

intended to be a comprehensive reference

source. For more information, refer to the

“PIC24F Family Reference Manual”,

Section 39. “Power-Saving Features

with Deep Sleep” (DS39727).

Note: SLEEP_MODE and IDLE_MODE are con-

stants defined in the assembler include

file for the selected device.

Sleep and Idle modes can be exited as a result of an

enabled interrupt, WDT time-out or a device Reset.

When the device exits these modes, it is said to

“wake-up”.

The PIC24FJ64GB004 family of devices provides the

ability to manage power consumption by selectively

managing clocking to the CPU and the peripherals. In

general, a lower clock frequency and a reduction in the

number of circuits being clocked constitutes lower

consumed power. All PIC24F devices manage power

consumption in four different ways:

9.2.1

SLEEP MODE

Sleep mode has these features:

• The system clock source is shut down. If an

on-chip oscillator is used, it is turned off.

• The device current consumption will be reduced

to a minimum provided that no I/O pin is sourcing

current.

• Clock Frequency

• Instruction-Based Sleep, Idle and Deep Sleep

modes

• The I/O pin directions and states are frozen.

• The Fail-Safe Clock Monitor does not operate

during Sleep mode since the system clock source

is disabled.

• Software Controlled Doze mode

• Selective Peripheral Control in Software

Combinations of these methods can be used to

selectively tailor an application’s power consumption,

while still maintaining critical application features, such

as timing-sensitive communications.

• The LPRC clock will continue to run in Sleep

mode if the WDT or RTCC, with LPRC as clock

source, is enabled.

• The WDT, if enabled, is automatically cleared

prior to entering Sleep mode.

9.1

Clock Frequency and Clock

Switching

• Some device features or peripherals may

continue to operate in Sleep mode. This includes

items, such as the input change notification on the

I/O ports, or peripherals that use an external clock

input. Any peripheral that requires the system

clock source for its operation will be disabled in

Sleep mode.

PIC24F devices allow for a wide range of clock

frequencies to be selected under application control. If

the system clock configuration is not locked, users can

choose low-power or high-precision oscillators by simply

changing the NOSC bits. The process of changing a

system clock during operation, as well as limitations to

the process, are discussed in more detail in Section 8.0

“Oscillator Configuration”.

The device will wake-up from Sleep mode on any of

these events:

• On any interrupt source that is individually

enabled

9.2

Instruction-Based Power-Saving

Modes

• On any form of device Reset

• On a WDT time-out

PIC24F devices have two special power-saving modes

that are entered through the execution of a special

PWRSAVinstruction. Sleep mode stops clock operation

and halts all code execution; Idle mode halts the CPU

and code execution, but allows peripheral modules to

continue operation. Deep Sleep mode stops clock

operation, code execution and all peripherals except

RTCC and DSWDT. It also freezes I/O states and

removes power to SRAM and Flash memory.

On wake-up from Sleep, the processor will restart with

the same clock source that was active when Sleep

mode was entered.

EXAMPLE 9-1:

PWRSAV INSTRUCTION SYNTAX

PWRSAV

BSET

#SLEEP_MODE

#IDLE_MODE

DSCON, #DSEN

#SLEEP_MODE

; Put the device into SLEEP mode

; Put the device into IDLE mode

; Enable Deep Sleep

PWRSAV

; Put the device into Deep SLEEP mode

 2010 Microchip Technology Inc.

DS39940D-page 117

PIC24FJ64GB004 FAMILY

9.2.2

IDLE MODE

Note:

Since Deep Sleep mode powers down the

microcontroller by turning off the on-chip

VDDCORE voltage regulator, Deep Sleep

capability is available only when operating

with the internal regulator enabled.

Idle mode has these features:

• The CPU will stop executing instructions.

• The WDT is automatically cleared.

• The system clock source remains active. By

default, all peripheral modules continue to operate

normally from the system clock source, but can

also be selectively disabled (see Section 9.4

“Selective Peripheral Module Control”).

9.2.4.1

Entering Deep Sleep Mode

Deep Sleep mode is entered by setting the DSEN bit in

the DSCON register, and then executing a SLEEP

instruction (PWRSAV#SLEEP_MODE) within one to three

instruction cycles to minimize the chance that Deep

Sleep will be spuriously entered.

• If the WDT or FSCM is enabled, the LPRC will

also remain active.

The device will wake from Idle mode on any of these

events:

If the PWRSAV command is not given within three

instruction cycles, the DSEN bit will be cleared by the

hardware and must be set again by the software before

entering Deep Sleep mode. The DSEN bit is also

automatically cleared when exiting the Deep Sleep

mode.

• Any interrupt that is individually enabled

• Any device Reset

• A WDT time-out

On wake-up from Idle mode, the clock is reapplied to

the CPU and instruction execution begins immediately,

starting with the instruction following the PWRSAV

instruction or the first instruction in the ISR.

Note: To re-enter Deep Sleep after a Deep Sleep

wake-up, allow a delay of at least 3 TCY

after clearing the RELEASE bit.

The sequence to enter Deep Sleep mode is:

9.2.3

INTERRUPTS COINCIDENT WITH

POWER SAVE INSTRUCTIONS

1. If the application requires the Deep Sleep WDT,

enable it and configure its clock source (see

Section 9.2.4.7 “Deep Sleep WDT” for

details).

Any interrupt that coincides with the execution of a

PWRSAVinstruction (except for Deep Sleep mode) will

be held off until entry into Sleep or Idle mode has com-

pleted. The device will then wake-up from Sleep or Idle

mode.

2. If the application requires Deep Sleep BOR,

enable it by programming the DSBOREN

Configuration bit (CW4<6>).

3. If the application requires wake-up from Deep

Sleep on RTCC alarm, enable and configure the

RTCC module (see Section 20.0 “Real-Time

Clock and Calendar (RTCC)” for more

information).

9.2.4

DEEP SLEEP MODE

In PIC24FJ64GB004 family devices, Deep Sleep mode

is intended to provide the lowest levels of power

consumption available, without requiring the use of

external switches to completely remove all power from

the device. Entry into Deep Sleep mode is completely

under software control. Exit from Deep Sleep mode can

be triggered from any of the following events:

4. If needed, save any critical application context

data by writing it to the DSGPR0 and DSGPR1

registers (optional).

5. Enable Deep Sleep mode by setting the DSEN

bit (DSCON<15>).

• POR event

• MCLR event

6. Enter Deep Sleep mode by immediately issuing

• RTCC alarm (If the RTCC is present)

• External Interrupt 0

a PWRSAV #0instruction.

Any time the DSEN bit is set, all bits in the DSWAKE

register will be automatically cleared.

• Deep Sleep Watchdog Timer (DSWDT) time-out

In Deep Sleep mode, it is possible to keep the device

Real-Time Clock and Calendar (RTCC) running without

the loss of clock cycles.

The device has a dedicated Deep Sleep Brown-out

Reset (DSBOR) and a Deep Sleep Watchdog Timer

Reset (DSWDT) for monitoring voltage and time-out

events. The DSBOR and DSWDT are independent of

the standard BOR and WDT used with other

power-managed modes (Sleep, Idle and Doze).

DS39940D-page 118

 2010 Microchip Technology Inc.

PIC24FJ64GB004 FAMILY

Examples for implementing these cases are shown in

Example 9-2. It is recommended that an assembler, or

in-line C routine, be used in these cases to ensure that

the code executes in the number of cycles required.

9.2.4.2

Special Cases when Entering Deep

Sleep Mode

When entering Deep Sleep mode, there are certain

circumstances that require a delay between setting the

DSEN bit and executing the PWRSAVinstruction. These

can be generally reduced to three scenarios:

EXAMPLE 9-2:

IMPLEMENTING THE

SPECIAL CASES FOR

ENTERING DEEP SLEEP

1. Scenario (1): use an external wake-up source

(INT0) or the RTCC

// Case 1: simplest delay scenario

//

asm("bset DSCON, #15");

asm("nop");

2. Scenario (2): with application-level interrupts

that can be temporarily disabled

3. Scenario (3): with interrupts that must be

monitored

In the first scenario, the application requires a wake-up

from Deep Sleep on the assertion of the INT0 pin or the

RTCC interrupt. In this case, three NOP instructions

must be inserted to properly synchronize the detection

of an asynchronous INT0 interrupt after the device

enters Deep Sleep mode. If the application does not

use wake-up on INT0 or RTCC, the NOP instructions

are optional.

asm("nop");

asm("pwrsav #0");

//

// Case 2: interrupts disabled

//

asm("disi #4");

asm("bset DSCON, #15");

asm("nop");

In the second scenario, the application also uses

interrupts which can be briefly ignored. With these

applications, an interrupt event during the execution of

the NOPinstructions may cause an ISR to be executed.

This means that more than three instruction cycles will

elapse before returning to the code and that the DSEN

bit will be cleared. To prevent the missed entry into

Deep Sleep, temporarily disable interrupts prior to

entering Deep Sleep mode. Invoking the DISIinstruc-

tion for four cycles is sufficient to prevent interrupts

from disrupting Deep Sleep entry.

asm("pwrsav #0");

//

// Case 3: interrupts disabled with

// interrupt testing

//

asm("disi #4");

asm("bset DSCON, #15");

asm("nop");

asm("btss INTTREG, #15");

asm("pwrsav #0");

// continue with application code here

//

In the third scenario, interrupts cannot be ignored even

briefly; constant interrupt detection is required, even

during the interval between setting DSEN and executing

the PWRSAVinstruction. For these cases, it is possible to

disable interrupts and test for an interrupt condition,

skipping the PWRSAVinstruction if necessary. Testing for

interrupts can be accomplished by checking the status of

the CPUIRQ bit (INTTREG<15>); if an unserviced inter-

rupt is pending, this bit will be set. If CPUIRQ is set prior

to executing the PWRSAV instruction, the instruction is

skipped. At this point, the DISIinstruction has expired

(being more than 4 instructions from when it was

executed) and the application vectors to the appropriate

ISR. When the application returns, it can either attempt

to re-enter Deep Sleep mode or perform some other

system function. In either case, the application must

have some functional code located, following the

PWRSAV instruction, in the event that the PWRSAV

instruction is skipped and the device does not enter

Deep Sleep mode.

 2010 Microchip Technology Inc.

DS39940D-page 119

PIC24FJ64GB004 FAMILY

9.2.4.3

Exiting Deep Sleep Mode

9.2.4.4

Deep Sleep Wake-up Time

Deep Sleep mode exits on any one of the following events:

Since wake-up from Deep Sleep results in a POR, the

wake-up time from Deep Sleep is the same as the

device POR time. Also, because the internal regulator

is turned off, the voltage on VCAP may drop depending

on how long the device is asleep. If VCAP has dropped

below 2V, then there will be additional wake-up time

while the regulator charges VCAP.

• POR event on VDD supply. If there is no DSBOR

circuit to re-arm the VDD supply POR circuit, the

external VDD supply must be lowered to the

natural arming voltage of the POR circuit.

• DSWDT time-out. When the DSWDT timer times

out, the device exits Deep Sleep.

Deep Sleep wake-up time is specified in Section 29.0

“Electrical Characteristics” as TDSWU. This specifica-

tion indicates the worst case wake-up time, including the

full POR Reset time (including TPOR and TRST), as well

as the time to fully charge a 10 F capacitor on VCAP

which has discharged to 0V. Wake-up may be

significantly faster if VCAP has not discharged.

• RTCC alarm (if RTCEN = 1).

• Assertion (‘0’) of the MCLR pin.

• Assertion of the INT0 pin (if the interrupt was

enabled before Deep Sleep mode was entered).

The polarity configuration is used to determine the

assertion level (‘0’ or ‘1’) of the pin that will cause

an exit from Deep Sleep mode. Exiting from Deep

Sleep mode requires a change on the INT0 pin

while in Deep Sleep mode.

9.2.4.5

Saving Context Data with the

DSGPR0/DSGPR1 Registers

Note:

Any interrupt pending when entering Deep

Sleep mode is cleared.

As exiting Deep Sleep mode causes a POR, most

Special Function Registers reset to their default POR

values. In addition, because VDDCORE power is not

supplied in Deep Sleep mode, information in data RAM

may be lost when exiting this mode.

Exiting Deep Sleep mode generally does not retain the

state of the device and is equivalent to a Power-on

Reset (POR) of the device. Exceptions to this include

the RTCC (if present), which remains operational

through the wake-up, the DSGPRx registers and

DSWDT.

Applications which require critical data to be saved

prior to Deep Sleep may use the Deep Sleep General

Purpose registers, DSGPR0 and DSGPR1, or data

EEPROM (if available). Unlike other SFRs, the con-

tents of these registers are preserved while the device

is in Deep Sleep mode. After exiting Deep Sleep,

software can restore the data by reading the registers

and clearing the RELEASE bit (DSCON<0>).

Wake-up events that occur from the time Deep Sleep

exits, until the time that the POR sequence completes,

are ignored and are not captured in the DSWAKE

register.

The sequence for exiting Deep Sleep mode is:

1. After a wake-up event, the device exits Deep

Sleep and performs a POR. The DSEN bit is

cleared automatically. Code execution resumes

at the Reset vector.

9.2.4.6

I/O Pins During Deep Sleep Mode

During Deep Sleep, the general purpose I/O pins retain

their previous states and the Secondary Oscillator

(SOSC) will remain running, if enabled. Pins that are

configured as inputs (TRIS bit set) prior to entry into

Deep Sleep remain high-impedance during Deep

Sleep. Pins that are configured as outputs (TRIS bit

clear) prior to entry into Deep Sleep remain as output

pins during Deep Sleep. While in this mode, they

continue to drive the output level determined by their

corresponding LAT bit at the time of entry into Deep

Sleep.

2. To determine if the device exited Deep Sleep,

read the Deep Sleep bit, DPSLP (RCON<10>).

This bit will be set if there was an exit from Deep

Sleep mode. If the bit is set, clear it.

3. Determine the wake-up source by reading the

DSWAKE register.

4. Determine if a DSBOR event occurred during

Deep Sleep mode by reading the DSBOR bit

(DSCON<1>).

5. If application context data has been saved, read

it back from the DSGPR0 and DSGPR1

registers.

6. Clear the RELEASE bit (DSCON<0>).

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Once the device wakes back up, all I/O pins continue to

maintain their previous states, even after the device

has finished the POR sequence and is executing appli-

cation code again. Pins configured as inputs during

Deep Sleep remain high-impedance and pins config-

ured as outputs continue to drive their previous value.

After waking up, the TRIS and LAT registers, and the

SOSCEN bit (OSCCON<1>) are reset. If firmware

modifies any of these bits or registers, the I/O will not

immediately go to the newly configured states. Once

the firmware clears the RELEASE bit (DSCON<0>) the

I/O pins are “released”. This causes the I/O pins to take

the states configured by their respective TRIS and LAT

bit values.

9.2.4.8

Switching Clocks in Deep Sleep Mode

Both the RTCC and the DSWDT may run from either

SOSC or the LPRC clock source. This allows both the

RTCC and DSWDT to run without requiring both the

LPRC and SOSC to be enabled together, reducing

power consumption.

Running the RTCC from LPRC will result in a loss of

accuracy in the RTCC of approximately 5 to 10%. If an

accurate RTCC is required, it must be run from the

SOSC clock source. The RTCC clock source is selected

with the RTCOSC Configuration bit (CW4<5>).

Under certain circumstances, it is possible for the

DSWDT clock source to be off when entering Deep

Sleep mode. In this case, the clock source is turned on

automatically (if DSWDT is enabled), without the need

for software intervention. However, this can cause a

delay in the start of the DSWDT counters. In order to

avoid this delay when using SOSC as a clock source,

the application can activate SOSC prior to entering

Deep Sleep mode.

This means that keeping the SOSC running after

waking up requires the SOSCEN bit to be set before

clearing RELEASE.

If the Deep Sleep BOR (DSBOR) is enabled, and a

DSBOR or a true POR event occurs during Deep

Sleep, the I/O pins will be immediately released similar

to clearing the RELEASE bit. All previous state infor-

mation will be lost, including the general purpose

DSGPR0 and DSGPR1 contents.

9.2.4.9

Checking and Clearing the Status of

Deep Sleep Mode

If a MCLR Reset event occurs during Deep Sleep, the

DSGPRx, DSCON and DSWAKE registers will remain

valid and the RELEASE bit will remain set. The state of

the SOSC will also be retained. The I/O pins, however,

will be reset to their MCLR Reset state. Since

RELEASE is still set, changes to the SOSCEN bit

(OSCCON<1>) cannot take effect until the RELEASE

bit is cleared.

Upon entry into Deep Sleep mode, the status bit,

DPSLP (RCON<10>), becomes set and must be

cleared by software.

On power-up, the software should read this status bit to

determine if the Reset was due to an exit from Deep

Sleep mode and clear the bit if it is set. Of the four

possible combinations of DPSLP and POR bit states,

three cases can be considered:

In all other Deep Sleep wake-up cases, application

firmware must clear the RELEASE bit in order to

reconfigure the I/O pins.

• Both the DPSLP and POR bits are cleared. In this

case, the Reset was due to some event other

than a Deep Sleep mode exit.

9.2.4.7

Deep Sleep WDT

• The DPSLP bit is clear, but the POR bit is set.

This is a normal Power-on Reset.

To enable the DSWDT in Deep Sleep mode, program

the Configuration bit, DSWDTEN (CW4<7>). The

device Watchdog Timer (WDT) need not be enabled for

the DSWDT to function. Entry into Deep Sleep mode

automatically resets the DSWDT.

• Both the DPSLP and POR bits are set. This

means that Deep Sleep mode was entered, the

device was powered down and Deep Sleep mode

was exited.

The DSWDT clock source is selected by the

DSWDTOSC Configuration bit (CW4<4>). The

postscaler options are programmed by the

DSWDTPS<3:0> Configuration bits (CW4<3:0>). The

minimum time-out period that can be achieved is

2.1 ms and the maximum is 25.7 days. For more

details on the CW4 Configuration register and DSWDT

configuration options, refer to Section 26.0 “Special

Features”.

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9.2.4.10

Power-on Resets (PORs)

9.2.4.11

Summary of Deep Sleep Sequence

VDD voltage is monitored to produce PORs. Since exit-

ing from Deep Sleep functionally looks like a POR, the

technique described in Section 9.2.4.9 “Checking

and Clearing the Status of Deep Sleep Mode”

should be used to distinguish between Deep Sleep and

a true POR event.

To review, these are the necessary steps involved in

invoking and exiting Deep Sleep mode:

1. Device exits Reset and begins to execute its

application code.

2. If DSWDT functionality is required, program the

appropriate Configuration bit.

When a true POR occurs, the entire device, including

all Deep Sleep logic (Deep Sleep registers, RTCC,

DSWDT, etc.) is reset.

3. Select the appropriate clock(s) for the DSWDT

and RTCC (optional).

4. Enable and configure the RTCC (optional).

5. Write context data to the DSGPRx registers

(optional).

6. Enable the INT0 interrupt (optional).

7. Set the DSEN bit in the DSCON register.

8. Enter Deep Sleep by issuing

a

PWRSV

#SLEEP_MODEcommand.

9. Device exits Deep Sleep when a wake-up event

occurs.

10. The DSEN bit is automatically cleared.

11. Read and clear the DPSLP status bit in RCON,

and the DSWAKE status bits.

12. Read the DSGPRx registers (optional).

13. Once all state related configurations are

complete, clear the RELEASE bit.

14. Application resumes normal operation.

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REGISTER 9-1:

R/W-0, HC

DSEN⁽¹⁾

DSCON: DEEP SLEEP CONTROL REGISTER

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

bit 15

bit 8

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

R/W-0, HCS

DSBOR^(1,2,3)

R/C-0, HS

RELEASE^(1,2)

bit 0

bit 7

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

C = Clearable bit

‘0’ = Bit is cleared

U = Unimplemented, read as ‘0’

x = Bit is unknown

HC = Hardware Clearable bit HS = Hardware Settable bit HCS = Hardware Clearable/Settable bit

bit 15

DSEN: Deep Sleep Enable bit⁽¹⁾

1= Device entered Deep Sleep when PWRSAV #0 was executed in the next instruction

0= Device entered normal Sleep when PWRSAV #0 was executed

bit 14-2

bit 1

Unimplemented: Read as ‘0’

DSBOR: Deep Sleep BOR Event Status bit^(1,2,3)

1= The DSBOR is active and a BOR event is detected during Deep Sleep

0= The DSBOR is disabled or is active and does not detect a BOR event during Deep Sleep

bit 0

RELEASE: I/O Pin State Deep Sleep Release bit^(1,2)

1= I/O pins and SOSC maintain their states following exit from Deep Sleep, regardless of their LAT

and TRIS configuration

0= I/O pins and SOSC are released from their Deep Sleep states. The pin state is controlled by the

LAT and TRIS configurations, and the SOSCEN bit.

Note 1: These bits are reset only in the case of a POR event outside of Deep Sleep mode.

2: Reset value is ‘0’ for initial power-on POR only and ‘1’ for Deep Sleep POR.

3: This is a status bit only; a DSBOR event will NOT cause a wake-up from Deep Sleep.

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REGISTER 9-2:

DSWAKE: DEEP SLEEP WAKE-UP SOURCE REGISTER

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

R/W-0, HS

DSINT0⁽¹⁾

bit 15

bit 8

R/W-0, HS

DSFLT⁽¹⁾

bit 7

U-0

—

U-0

—

R/W-0, HS

DSWDT⁽¹⁾

R/W-0, HS

DSRTC⁽¹⁾

R/W-0, HS

DSMCLR⁽¹⁾

U-0

—

R/W-0, HS

DSPOR⁽²⁾

bit 0

Legend:

HS = Hardware Settable bit

W = Writable bit

R = Readable bit

-n = Value at POR

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

‘1’ = Bit is set

bit 15-9

bit 8

Unimplemented: Read as ‘0’

DSINT0: Interrupt-on-Change bit⁽¹⁾

1= External Interrupt 0 was asserted during Deep Sleep

0= External Interrupt 0 was not asserted during Deep Sleep

bit 7

DSFLT: Deep Sleep Fault Detected bit⁽¹⁾

1= A Fault occurred during Deep Sleep and some Deep Sleep configuration settings may have been

corrupted

0= No Fault was detected during Deep Sleep

bit 6-5

bit 4

Unimplemented: Read as ‘0’

DSWDT: Deep Sleep Watchdog Timer Time-out bit⁽¹⁾

1= The Deep Sleep Watchdog Timer timed out during Deep Sleep

0= The Deep Sleep Watchdog Timer did not time out during Deep Sleep

bit 3

bit 2

DSRTC: Real-Time Clock and Calendar Alarm bit⁽¹⁾

1= The Real-Time Clock and Calendar triggered an alarm during Deep Sleep

0= The Real-Time Clock and Calendar did not trigger an alarm during Deep Sleep

DSMCLR: Deep Sleep MCLR Event bit⁽¹⁾

1= The MCLR pin was asserted during Deep Sleep

0= The MCLR pin was not asserted during Deep Sleep

bit 1

bit 0

Unimplemented: Read as ‘0’

DSPOR: Power-on Reset Event bit⁽²⁾

1= The VDD supply POR circuit was active and a POR event was detected

0= The VDD supply POR circuit was not active, or was active, but did not detect a POR event

Note 1: This bit can only be set while the device is in Deep Sleep mode.

2: This bit can be set outside of Deep Sleep.

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9.3

Doze Mode

9.4

Selective Peripheral Module

Control

Generally, changing clock speed and invoking one of

the power-saving modes are the preferred strategies

for reducing power consumption. There may be

circumstances, however, where this is not practical. For

example, it may be necessary for an application to

maintain uninterrupted synchronous communication,

even while it is doing nothing else. Reducing system

clock speed may introduce communication errors,

Idle and Doze modes allow users to substantially

reduce power consumption by slowing or stopping the

CPU clock. Even so, peripheral modules still remain

clocked, and thus, consume power. There may be

cases where the application needs what these modes

do not provide: the allocation of power resources to

CPU processing with minimal power consumption from

the peripherals.

while using

communications completely.

a

power-saving mode may stop

PIC24F devices address this requirement by allowing

peripheral modules to be selectively disabled, reducing

or eliminating their power consumption. This can be

done with two control bits:

Doze mode is a simple and effective alternative method

to reduce power consumption while the device is still

executing code. In this mode, the system clock

continues to operate from the same source and at the

same speed. Peripheral modules continue to be

clocked at the same speed while the CPU clock speed

is reduced. Synchronization between the two clock

domains is maintained, allowing the peripherals to

access the SFRs while the CPU executes code at a

slower rate.

• The Peripheral Enable bit, generically named

“XXXEN”, located in the module’s main control

SFR.

• The Peripheral Module Disable (PMD) bit,

generically named “XXXMD”, located in one of the

PMD Control registers.

Both bits have similar functions in enabling or disabling

its associated module. Setting the PMD bit for a module

disables all clock sources to that module, reducing its

power consumption to an absolute minimum. In this

state, the control and status registers associated with

the peripheral will also be disabled, so writes to those

registers will have no effect and read values will be

invalid. Many peripheral modules have a corresponding

PMD bit.

Doze mode is enabled by setting the DOZEN bit

(CLKDIV<11>). The ratio between peripheral and core

clock speed is determined by the DOZE<2:0> bits

(CLKDIV<14:12>). There are eight possible

configurations, from 1:1 to 1:128, with 1:1 being the

default.

It is also possible to use Doze mode to selectively

reduce power consumption in event-driven applica-

tions. This allows clock-sensitive functions, such as

synchronous communications, to continue without

interruption while the CPU Idles, waiting for something

to invoke an interrupt routine. Enabling the automatic

return to full-speed CPU operation on interrupts is

enabled by setting the ROI bit (CLKDIV<15>). By

default, interrupt events have no effect on Doze mode

operation.

In contrast, disabling a module by clearing its XXXEN bit

disables its functionality, but leaves its registers available

to be read and written to. This reduces power consump-

tion, but not by as much as setting the PMD bit does.

Most peripheral modules have an enable bit; exceptions

include input capture, output compare and RTCC.

To achieve more selective power savings, peripheral

modules can also be selectively disabled when the

device enters Idle mode. This is done through the

control bit of the generic name format, “XXXIDL”. By

default, all modules that can operate during Idle mode

will do so. Using the disable on Idle feature allows

further reduction of power consumption during Idle

mode, enhancing power savings for extremely critical

power applications.

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NOTES:

DS39940D-page 126

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When a peripheral is enabled and the peripheral is

actively driving an associated pin, the use of the pin as

10.0 I/O PORTS

Note:

This data sheet summarizes the features

of this group of PIC24F devices. It is not

a general purpose output pin is disabled. The I/O pin

may be read, but the output driver for the parallel port

bit will be disabled. If a peripheral is enabled, but the

peripheral is not actively driving a pin, that pin may be

driven by a port.

intended to be a comprehensive reference

source. For more information, refer to the

“PIC24F Family Reference Manual”,

Section 12. “I/O Ports with Peripheral

Pin Select (PPS)” (DS39711).

All port pins have three registers directly associated

with their operation as digital I/Os. The Data Direction

register (TRIS) determines whether the pin is an input

or an output. If the data direction bit is a ‘1’, then the pin

is an input. All port pins are defined as inputs after a

Reset. Reads from the Output Latch register (LAT),

read the latch. Writes to the Output Latch register, write

the latch. Reads from the port (PORT), read the port

pins, while writes to the port pins, write the latch.

All of the device pins (except VDD, VSS, MCLR and

OSCI/CLKI) are shared between the peripherals and

the parallel I/O ports. All I/O input ports feature Schmitt

Trigger inputs for improved noise immunity.

10.1 Parallel I/O (PIO) Ports

A parallel I/O port that shares a pin with a peripheral is, in

general, subservient to the peripheral. The peripheral’s

output buffer data and control signals are provided to a

pair of multiplexers. The multiplexers select whether the

peripheral or the associated port has ownership of the

output data and control signals of the I/O pin. The logic

also prevents “loop through”, in which a port’s digital out-

put can drive the input of a peripheral that shares the

same pin. Figure 10-1 shows how ports are shared with

other peripherals and the associated I/O pin to which

they are connected.

Any bit and its associated data and control registers

that are not valid for a particular device will be

disabled. That means the corresponding LAT and

TRIS registers, and the port pin will read as zeros.

When a pin is shared with another peripheral or func-

tion that is defined as an input only, it is regarded as a

dedicated port because there is no other competing

source of outputs.

FIGURE 10-1:

BLOCK DIAGRAM OF A TYPICAL SHARED PORT STRUCTURE

Peripheral Module

Output Multiplexers

Peripheral Input Data

Peripheral Module Enable

Peripheral Output Enable

Peripheral Output Data

I/O

1

0

Output Enable

Output Data

1

0

PIO Module

Read TRIS

Data Bus

WR TRIS

D

Q

I/O Pin

CK

TRIS Latch

D

Q

WR LAT +

WR PORT

CK

Data Latch

Read LAT

Input Data

Read PORT

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10.1.1

OPEN-DRAIN CONFIGURATION

10.2.2

ANALOG INPUT PINS AND

VOLTAGE CONSIDERATIONS

In addition to the PORT, LAT and TRIS registers for

data control, each port pin can also be individually

configured for either digital or open-drain output. This is

controlled by the Open-Drain Control register, ODCx,

associated with each port. Setting any of the bits con-

figures the corresponding pin to act as an open-drain

output.

The voltage tolerance of pins used as device inputs is

dependent on the pin’s input function. Pins that are

used as digital only inputs are able to handle DC

voltages up to 5.5V, a level typical for digital logic

circuits. In contrast, pins that also have analog input

functions of any kind can only tolerate voltages up to

VDD. Voltage excursions beyond VDD on these pins

should be avoided.

The open-drain feature allows the generation of

outputs higher than VDD (e.g., 5V) on any desired

digital only pins by using external pull-up resistors. The

maximum open-drain voltage allowed is the same as

the maximum VIH specification.

Table 10-1 summarizes the input voltage capabilities.

Refer to Section 29.0 “Electrical Characteristics” for

more details.

10.2 Configuring Analog Port Pins

TABLE 10-1: INPUT VOLTAGE TOLERANCE

Tolerate

The AD1PCFGL and TRIS registers control the opera-

tion of the A/D port pins. Setting a port pin as an analog

input also requires that the corresponding TRIS bit be

set. If the TRIS bit is cleared (output), the digital output

level (VOH or VOL) will be converted.

Port or Pin

Description

d Input

PORTA<4:0>

VDD

Only VDD input

levels are tolerated.

PORTB<15:13>

PORTB<4:0>

PORTC<3:0>⁽¹⁾

PORTA<10:7>⁽¹⁾

PORTB<11:7>

PORTB<5>

When reading the PORT register, all pins configured as

analog input channels will read as cleared (a low level).

5.5V

Tolerates input levels

above VDD, useful for

most standard logic.

Pins configured as digital inputs will not convert an

analog input. Analog levels on any pin that is defined as

a digital input (including the ANx pins) may cause the

input buffer to consume current that exceeds the

device specifications.

PORTC<9:4>⁽¹⁾

Note 1: Not available on 28-pin devices.

10.2.1

I/O PORT WRITE/READ TIMING

One instruction cycle is required between a port

direction change or port write operation and a read

operation of the same port. Typically, this instruction

would be a NOP(Example 10-1).

EXAMPLE 10-1:

PORT WRITE/READ EXAMPLE

MOV

NOP

0xFF00, W0

W0, TRISB

; Configure PORTB<15:8> as inputs

; and PORTB<7:0> as outputs

; Delay 1 cycle

BTSS PORTB, #13

; Next Instruction

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safeguards are included that prevent accidental or

spurious changes to the peripheral mapping once it has

been established.

10.3 Input Change Notification

The input change notification function of the I/O ports

allows the PIC24FJ64GB004 family of devices to

generate interrupt requests to the processor in

response to a change of state on selected input pins.

This feature is capable of detecting input

Change-of-States (COS) even in Sleep mode, when

the clocks are disabled. Depending on the device pin

count, there are up to 29 external inputs that may be

selected (enabled) for generating an interrupt request

on a Change-of-State.

10.4.1

AVAILABLE PINS

The Peripheral Pin Select feature is used with a range

of up to 25 pins, depending on the particular device and

its pin count. Pins that support the Peripheral Pin

Select feature include the designation “RPn” in their full

pin designation, where “n” is the remappable pin

number.

See Table 1-2 for a summary of pinout options in each

package offering.

Registers, CNEN1 and CNEN2, contain the interrupt

enable control bits for each of the CN input pins. Setting

any of these bits enables a CN interrupt for the

corresponding pins.

10.4.2

AVAILABLE PERIPHERALS

The peripherals managed by the Peripheral Pin Select

are all digital only peripherals. These include general

serial communications (UART and SPI), general

purpose timer clock inputs, timer related peripherals

(input capture and output compare) and external

interrupt inputs. Also included are the outputs of the

comparator module, since these are discrete digital

signals.

Peripheral Pin Select is not available for I²C™ change

notification inputs, RTCC alarm outputs or peripherals

with analog inputs.

Each CN pin has a weak pull-up connected to it. The

pull-up acts as a current source that is connected to the

pin. This eliminates the need for external resistors

when push button or keypad devices are connected.

The pull-ups are separately enabled using the CNPU1

and CNPU2 registers (for pull-ups). Each CN pin has

individual control bits for its pull-up. Setting a control bit

enables the weak pull-up for the corresponding pin.

When the internal pull-up is selected, the pin pulls up to

VDD-0.7V (typical). Make sure that there is no external

pull-up source when the internal pull-ups are enabled,

as the voltage difference can cause a current path.

A key difference between pin select and non pin select

peripherals is that pin select peripherals are not asso-

ciated with a default I/O pin. The peripheral must

always be assigned to a specific I/O pin before it can be

used. In contrast, non pin select peripherals are always

available on a default pin, assuming that the peripheral

is active and not conflicting with another peripheral.

Note:

Pull-ups on change notification pins

should always be disabled whenever the

port pin is configured as a digital output.

10.4 Peripheral Pin Select (PPS)

A major challenge in general purpose devices is provid-

ing the largest possible set of peripheral features while

minimizing the conflict of features on I/O pins. In an

application that needs to use more than one peripheral

multiplexed on a single pin, inconvenient work arounds

in application code or a complete redesign may be the

only option.

10.4.2.1

Peripheral Pin Select Function

Priority

Pin-selectable peripheral outputs (for example, OC and

UART transmit) take priority over any general purpose

digital functions permanently tied to that pin, such as

PMP and port I/O. Specialized digital outputs, such as

USB functionality, take priority over PPS outputs on the

same pin. The pin diagrams at the beginning of this

data sheet list peripheral outputs in order of priority.

Refer to them for priority concerns on a particular pin.

The Peripheral Pin Select feature provides an alternative

to these choices by enabling the user’s peripheral set

selection and their placement on a wide range of I/O

pins. By increasing the pinout options available on a par-

ticular device, users can better tailor the microcontroller

to their entire application, rather than trimming the

application to fit the device.

Unlike devices with fixed peripherals, pin-selectable

peripheral inputs never take ownership of a pin. The

pin’s output buffer is controlled by the pin’s TRIS bit

setting, or by a fixed peripheral on the pin. If the pin is

configured in Digital mode, then the PPS input will

operate correctly, reading the input. If an analog func-

tion is enabled on the same pin, the pin-selectable

input will be disabled.

The Peripheral Pin Select feature operates over a fixed

subset of digital I/O pins. Users may independently

map the input and/or output of any one of many digital

peripherals to any one of these I/O pins. Peripheral Pin

Select is performed in software and generally does not

require the device to be reprogrammed. Hardware

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10.4.3

CONTROLLING PERIPHERAL PIN

SELECT

10.4.3.1

Input Mapping

The inputs of the Peripheral Pin Select options are

mapped on the basis of the peripheral; that is, a control

register associated with a peripheral dictates the pin it

will be mapped to. The RPINRx registers are used to

configure peripheral input mapping (see Register 10-1

through Register 10-14). Each register contains up to

two sets of 5-bit fields, with each set associated with

one of the pin-selectable peripherals. Programming a

given peripheral’s bit field with an appropriate 6-bit

value maps the RPn pin with that value to that

peripheral. For any given device, the valid range of

values for any of the bit fields corresponds to the

maximum number of Peripheral Pin Select options

supported by the device.

Peripheral Pin Select features are controlled through

two sets of Special Function Registers: one to map

peripheral inputs and one to map outputs. Because

they are separately controlled, a particular peripheral’s

input and output (if the peripheral has both) can be

placed on any selectable function pin without

constraint.

The

association

of

a

peripheral

to

a

peripheral-selectable pin is handled in two different

ways, depending on if an input or an output is being

mapped.

TABLE 10-2: SELECTABLE INPUT SOURCES (MAPS INPUT TO FUNCTION)⁽¹⁾

Function Mapping

Bits

Input Name

Function Name

Register

External Interrupt 1

External Interrupt 2

Input Capture 1

INT1

INT2

RPINR0

RPINR1

RPINR7

RPINR8

RPINR9

RPINR11

RPINR20

RPINR21

RPINR22

RPINR23

RPINR3

RPINR4

RPINR18

RPINR19

INT1R<5:0>

INT2R<5:0>

IC1R<5:0>

IC1

Input Capture 2

IC2

IC2R<5:0>

Input Capture 3

IC3

IC3R<5:0>

Input Capture 4

IC4

IC4R<5:0>

Input Capture 5

IC5

IC5R<5:0>

Output Compare Fault A

Output Compare Fault B

SPI1 Clock Input

OCFA

OCFB

SCK1IN

SDI1

OCFAR<5:0>

OCFBR<5:0>

SCK1R<5:0>

SDI1R<5:0>

SS1R<5:0>

SCK2R<5:0>

SDI2R<5:0>

SS2R<5:0>

T2CKR<5:0>

T3CKR<5:0>

T4CKR<5:0>

T5CKR<5:0>

U1CTSR<5:0>

U1RXR<5:0>

U2CTSR<5:0>

U2RXR<5:0>

SPI1 Data Input

SPI1 Slave Select Input

SPI2 Clock Input

SS1IN

SCK2IN

SDI2

SPI2 Data Input

SPI2 Slave Select Input

Timer2 External Clock

Timer3 External Clock

Timer4 External Clock

Timer5 External Clock

UART1 Clear To Send

UART1 Receive

SS2IN

T2CK

T3CK

T4CK

T5CK

U1CTS

U1RX

U2CTS

U2RX

UART2 Clear To Send

UART2 Receive

Note 1: Unless otherwise noted, all inputs use the Schmitt Trigger input buffers.

DS39940D-page 130

 2010 Microchip Technology Inc.

PIC24FJ64GB004 FAMILY

the bit field corresponds to one of the peripherals and

that peripheral’s output is mapped to the pin (see

Table 10-3).

10.4.3.2

Output Mapping

In contrast to inputs, the outputs of the Peripheral Pin

Select options are mapped on the basis of the pin. In

this case, a control register associated with a particular

pin dictates the peripheral output to be mapped. The

RPORx registers are used to control output mapping.

Each register contains up to two 5-bit fields, with each

field being associated with one RPn pin (see

Register 10-15 through Register 10-27). The value of

Because of the mapping technique, the list of

peripherals for output mapping also includes a null value

of ‘000000’. This permits any given pin to remain dis-

connected from the output of any of the pin-selectable

peripherals.

TABLE 10-3: SELECTABLE OUTPUT SOURCES (MAPS FUNCTION TO OUTPUT)

Output Function Number⁽¹⁾

Function

Output Name

0

1

NULL⁽²⁾

C1OUT

C2OUT

U1TX

Null

Comparator 1 Output

Comparator 2 Output

UART1 Transmit

2

3

4

U1RTS⁽³⁾

UART1 Request To Send

UART2 Transmit

5

U2TX

6

U2RTS⁽³⁾

SDO1

UART2 Request To Send

SPI1 Data Output

SPI1 Clock Output

SPI1 Slave Select Output

SPI2 Data Output

SPI2 Clock Output

SPI2 Slave Select Output

Output Compare 1

Output Compare 2

Output Compare 3

Output Compare 4

Output Compare 5

NC

7

8

SCK1OUT

SS1OUT

SDO2

9

10

11

12

18

19

20

21

22

23-28

29

30

31

SCK2OUT

SS2OUT

OC1

OC2

OC3

OC4

OC5

(unused)

CTPLS

C3OUT

(unused)

CTMU Output Pulse

Comparator 3 Output

NC

Note 1: Setting the RPORx register with the listed value assigns that output function to the associated RPn pin.

2: The NULL function is assigned to all RPn outputs at device Reset and disables the RPn output function.

3: IrDA^®BCLK functionality uses this output.

 2010 Microchip Technology Inc.

DS39940D-page 131

PIC24FJ64GB004 FAMILY

10.4.3.3

Mapping Limitations

10.4.4.1

Control Register Lock

The control schema of the Peripheral Pin Select is

extremely flexible. Other than systematic blocks that

prevent signal contention caused by two physical pins

being configured as the same functional input, or two

functional outputs configured as the same pin, there

are no hardware enforced lock outs. The flexibility

extends to the point of allowing a single input to drive

multiple peripherals or a single functional output to

drive multiple output pins.

Under normal operation, writes to the RPINRx and

RPORx registers are not allowed. Attempted writes will

appear to execute normally, but the contents of the

registers will remain unchanged. To change these reg-

isters, they must be unlocked in hardware. The register

lock is controlled by the IOLOCK bit (OSCCON<6>).

Setting IOLOCK prevents writes to the control

registers; clearing IOLOCK allows writes.

To set or clear IOLOCK, a specific command sequence

must be executed:

10.4.3.4

PPS Mapping Exceptions for

1. Write 46h to OSCCON<7:0>.

PIC24FJ64GB0 Family Devices

2. Write 57h to OSCCON<7:0>.

Although the PPS registers allow for up to 32 remappable

pins, not all of these are implemented in all devices.

Exceptions and unimplemented RPn pins are listed in

Table 10-4.

3. Clear (or set) IOLOCK as a single operation.

Unlike the similar sequence with the oscillator’s LOCK

bit, IOLOCK remains in one state until changed. This

allows all of the Peripheral Pin Selects to be configured

with a single unlock sequence, followed by an update

to all control registers, then locked with a second lock

sequence.

TABLE 10-4: REMAPPABLE PIN

EXCEPTIONS FOR

PIC24FJ64GB004 FAMILY

DEVICES

10.4.4.2

Continuous State Monitoring

RP Pins (I/O)

Device Pin

In addition to being protected from direct writes, the

contents of the RPINRx and RPORx registers are

constantly monitored in hardware by shadow registers.

If an unexpected change in any of the registers occurs

(such as cell disturbances caused by ESD or other

external events), a Configuration Mismatch Reset will

be triggered.

Count

Total

Unimplemented

28 Pins

44 Pins

15

25

RP12, RP16-RP25

RP12

10.4.4

CONTROLLING CONFIGURATION

CHANGES

10.4.4.3

Configuration Bit Pin Select Lock

Because peripheral remapping can be changed during

run time, some restrictions on peripheral remapping

are needed to prevent accidental configuration

changes. PIC24F devices include three features to

prevent alterations to the peripheral map:

As an additional level of safety, the device can be

configured to prevent more than one write session to

the RPINRx and RPORx registers. The IOL1WAY

(CW2<4>) Configuration bit blocks the IOLOCK bit

from being cleared after it has been set once. If

IOLOCK remains set, the register unlock procedure will

not execute and the Peripheral Pin Select Control

registers cannot be written to. The only way to clear the

bit and re-enable peripheral remapping is to perform a

device Reset.

• Control register lock sequence

• Continuous state monitoring

• Configuration bit remapping lock

In the default (unprogrammed) state, IOL1WAY is set,

restricting users to one write session. Programming

IOL1WAY allows users unlimited access (with the

proper use of the unlock sequence) to the Peripheral

Pin Select registers.

DS39940D-page 132

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PIC24FJ64GB004 FAMILY

The assignment of a peripheral to a particular pin does

not automatically perform any other configuration of the

pin’s I/O circuitry. In theory, this means adding a

pin-selectable output to a pin may mean inadvertently

driving an existing peripheral input when the output is

driven. Users must be familiar with the behavior of

other fixed peripherals that share a remappable pin and

know when to enable or disable them. To be safe, fixed

digital peripherals that share the same pin should be

disabled when not in use.

10.4.5

CONSIDERATIONS FOR

PERIPHERAL PIN SELECTION

The ability to control Peripheral Pin Selection intro-

duces several considerations into application design

that could be overlooked. This is particularly true for

several common peripherals that are available only as

remappable peripherals.

The main consideration is that the Peripheral Pin

Selects are not available on default pins in the device’s

default (Reset) state. Since all RPINRx registers reset

to ‘11111’ and all RPORx registers reset to ‘00000’, all

Peripheral Pin Select inputs are tied to VSS and all

Peripheral Pin Select outputs are disconnected.

Along these lines, configuring a remappable pin for a

specific peripheral does not automatically turn that

feature on. The peripheral must be specifically

configured for operation and enabled, as if it were tied to

a fixed pin. Where this happens in the application code

(immediately following device Reset and peripheral

configuration or inside the main application routine)

depends on the peripheral and its use in the application.

Note:

RP31 does not have to exist on a device

for the registers to be reset to it, or for

peripheral pin outputs to be tied to it.

This situation requires the user to initialize the device

with the proper peripheral configuration before any

other application code is executed. Since the IOLOCK

bit resets in the unlocked state, it is not necessary to

execute the unlock sequence after the device has

come out of Reset. For application safety, however, it is

best to set IOLOCK and lock the configuration after

writing to the control registers.

A final consideration is that Peripheral Pin Select func-

tions neither override analog inputs, nor reconfigure

pins with analog functions for digital I/O. If a pin is

configured as an analog input on device Reset, it must

be explicitly reconfigured as digital I/O when used with

a Peripheral Pin Select.

Example 10-2 shows a configuration for bidirectional

communication with flow control using UART1. The

following input and output functions are used:

Because the unlock sequence is timing-critical, it must

be executed as an assembly language routine in the

same manner as changes to the oscillator configura-

tion. If the bulk of the application is written in C or

another high-level language, the unlock sequence

should be performed by writing in-line assembly.

• Input Functions: U1RX, U1CTS

• Output Functions: U1TX, U1RTS

Choosing the configuration requires the review of all

Peripheral Pin Selects and their pin assignments,

especially those that will not be used in the application.

In all cases, unused pin-selectable peripherals should

be disabled completely. Unused peripherals should

have their inputs assigned to an unused RPn pin

function. I/O pins with unused RPn functions should be

configured with the null peripheral output.

 2010 Microchip Technology Inc.

DS39940D-page 133

PIC24FJ64GB004 FAMILY

EXAMPLE 10-2:

CONFIGURING UART1 INPUT AND OUTPUT FUNCTIONS IN ASSEMBLY CODE

;unlock

push

mov

mov.b

bclr

registers

w1;

w2;

w3;

#OSCCON, w1;

#0x46, w2;

#0x57, w3;

w2, [w1];

w3, [w1];

OSCCON, #6;

; Configure Input Functions (Table10-2)

; Assign U1CTS To Pin RP1, U1RX To Pin RP0

mov

#0x0100, w1;

w1,RPINR18;

; Configure Output Functions (Table 10-3)

; Assign U1RTS To Pin RP3, U1TX To Pin RP2

mov

#0x0403, w1;

w1, RPOR1;

;lock

mov

registers

#OSCCON, w1;

#0x46, w2;

#0x57, w3;

w2, [w1];

w3, [w1];

OSCCON, #6;

w3;

mov

mov.b

bset

pop

w2;

pop

w1;

EXAMPLE 10-3:

CONFIGURING UART1 INPUT AND OUTPUT FUNCTIONS IN ‘C’

//unlock registers

__builtin_write_OSCCONL(OSCCON & 0xBF);

// Configure Input Functions (Table 9-1)

// Assign U1RX To Pin RP0

RPINR18bits.U1RXR = 0;

// Assign U1CTS To Pin RP1

RPINR18bits.U1CTSR = 1;

// Configure Output Functions (Table 9-2)

// Assign U1TX To Pin RP2

RPOR1bits.RP2R = 3;

// Assign U1RTS To Pin RP3

RPOR1bits.RP3R = 4;

//lock registers

__builtin_write_OSCCONL(OSCCON | 0x40);

DS39940D-page 134

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PIC24FJ64GB004 FAMILY

10.4.6

PERIPHERAL PIN SELECT

REGISTERS

Note:

Input and output register values can only be

changed if IOLOCK (OSCCON<6>) = 0.

See Section 10.4.4.1 “Control Register

Lock” for a specific command sequence.

The PIC24FJ64GB004 family of devices implements a

total of 27 registers for remappable peripheral

configuration:

• Input Remappable Peripheral Registers (14)

• Output Remappable Peripheral Registers (13)

REGISTER 10-1: RPINR0: PERIPHERAL PIN SELECT INPUT REGISTER 0

U-0

—

U-0

—

U-0

—

R/W-1

INT1R4

INT1R3

INT1R2

INT1R1

INT1R0

bit 15

bit 8

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15-13

bit 12-8

bit 7-0

Unimplemented: Read as ‘0’

INT1R<4:0>: Assign External Interrupt 1 (INT1) to Corresponding RPn or RPIn Pin bits

Unimplemented: Read as ‘0’

REGISTER 10-2: RPINR1: PERIPHERAL PIN SELECT INPUT REGISTER 1

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

bit 15

bit 8

U-0

—

U-0

—

U-0

—

R/W-1

INT2R4

INT2R3

INT2R2

INT2R1

INT2R0

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15-5

bit 4-0

Unimplemented: Read as ‘0’

INT1R<4:0>: Assign External Interrupt 2 (INT2) to Corresponding RPn or RPIn Pin bits

 2010 Microchip Technology Inc.

DS39940D-page 135

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REGISTER 10-3: RPINR3: PERIPHERAL PIN SELECT INPUT REGISTER 3

U-0

—

U-0

—

U-0

—

R/W-1

T3CKR4

T3CKR3

T3CKR2

T3CKR1

T3CKR0

bit 15

bit 8

U-0

—

U-0

—

U-0

—

R/W-1

T2CKR4

T2CKR3

T2CKR2

T2CKR1

T2CKR0

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15-13

bit 12-8

bit 7-5

Unimplemented: Read as ‘0’

T3CKR<4:0>: Assign Timer3 External Clock (T3CK) to Corresponding RPn or RPIn Pin bits

Unimplemented: Read as ‘0’

bit 4-0

T2CKR<4:0>: Assign Timer2 External Clock (T2CK) to Corresponding RPn or RPIn Pin bits

REGISTER 10-4: RPINR4: PERIPHERAL PIN SELECT INPUT REGISTER 4

U-0

—

U-0

—

U-0

—

R/W-1

T5CKR0

bit 8

T5CKR4

T5CKR3

T5CKR2

T5CKR1

bit 15

U-0

—

U-0

—

U-0

—

R/W-1

T4CKR4

T4CKR3

T4CKR2

T4CKR1

T4CKR0

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15-13

bit 12-8

bit 7-5

Unimplemented: Read as ‘0’

T5CKR<4:0>: Assign Timer5 External Clock (T5CK) to Corresponding RPn or RPIn Pin bits

Unimplemented: Read as ‘0’

bit 4-0

T4CKR<4:0>: Assign Timer4 External Clock (T4CK) to Corresponding RPn or RPIn Pin bits

DS39940D-page 136

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REGISTER 10-5: RPINR7: PERIPHERAL PIN SELECT INPUT REGISTER 7

U-0

—

U-0

—

U-0

—

R/W-1

IC2R4

R/W-1

IC2R3

R/W-1

IC2R2

R/W-1

IC2R1

R/W-1

IC2R0

bit 15

bit 8

U-0

—

U-0

—

U-0

—

R/W-1

IC1R4

R/W-1

IC1R3

R/W-1

IC1R2

R/W-1

IC1R1

R/W-1

IC1R0

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15-13

bit 12-8

bit 7-5

Unimplemented: Read as ‘0’

IC2R<4:0>: Assign Input Capture 2 (IC2) to Corresponding RPn or RPIn Pin bits

Unimplemented: Read as ‘0’

bit 4-0

IC1R<4:0>: Assign Input Capture 1 (IC1) to Corresponding RPn or RPIn Pin bits

REGISTER 10-6: RPINR8: PERIPHERAL PIN SELECT INPUT REGISTER 8

U-0

—

U-0

—

U-0

—

R/W-1

IC4R4

R/W-1

IC4R3

R/W-1

IC4R2

R/W-1

IC4R1

R/W-1

IC4R0

bit 15

bit 8

U-0

—

U-0

—

U-0

—

R/W-1

IC3R4

R/W-1

IC3R3

R/W-1

IC3R2

R/W-1

IC3R1

R/W-1

IC3R0

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15-13

bit 12-8

bit 7-5

Unimplemented: Read as ‘0’

IC4R<4:0>: Assign Input Capture 4 (IC4) to Corresponding RPn or RPIn Pin bits

Unimplemented: Read as ‘0’

bit 4-0

IC3R<4:0>: Assign Input Capture 3 (IC3) to Corresponding RPn or RPIn Pin bits

 2010 Microchip Technology Inc.

DS39940D-page 137

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REGISTER 10-7: RPINR9: PERIPHERAL PIN SELECT INPUT REGISTER 9

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

bit 15

bit 8

U-0

—

U-0

—

U-0

—

R/W-1

IC5R4

R/W-1

IC5R3

R/W-1

IC5R2

R/W-1

IC5R1

R/W-1

IC5R0

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15-5

bit 4-0

Unimplemented: Read as ‘0’

IC5R<4:0>: Assign Input Capture 5 (IC5) to Corresponding RPn or RPIn Pin bits

REGISTER 10-8: RPINR11: PERIPHERAL PIN SELECT INPUT REGISTER 11

U-0

—

U-0

—

U-0

—

R/W-1

OCFBR4

OCFBR3

OCFBR2

OCFBR1

OCFBR0

bit 15

bit 8

U-0

—

U-0

—

U-0

—

R/W-1

OCFAR4

OCFAR3

OCFAR2

OCFAR1

OCFAR0

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15-13

bit 12-8

bit 7-5

Unimplemented: Read as ‘0’

OCFBR<4:0>: Assign Output Compare Fault B (OCFB) to Corresponding RPn or RPIn Pin bits

Unimplemented: Read as ‘0’

bit 4-0

OCFAR<4:0>: Assign Output Compare Fault A (OCFA) to Corresponding RPn or RPIn Pin bits

DS39940D-page 138

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REGISTER 10-9: RPINR18: PERIPHERAL PIN SELECT INPUT REGISTER 18

U-0

—

U-0

—

U-0

—

R/W-1

U1CTSR4

U1CTSR3

U1CTSR2

U1CTSR1

U1CTSR0

bit 15

bit 8

U-0

—

U-0

—

U-0

—

R/W-1

U1RXR4

U1RXR3

U1RXR2

U1RXR1

U1RXR0

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15-13

bit 12-8

bit 7-5

Unimplemented: Read as ‘0’

U1CTSR<4:0>: Assign UART1 Clear to Send (U1CTS) to Corresponding RPn or RPIn Pin bits

Unimplemented: Read as ‘0’

bit 4-0

U1RXR<4:0>: Assign UART1 Receive (U1RX) to Corresponding RPn or RPIn Pin bits

REGISTER 10-10: RPINR19: PERIPHERAL PIN SELECT INPUT REGISTER 19

U-0

—

U-0

—

U-0

—

R/W-1

U2CTSR0

bit 8

U2CTSR4

U2CTSR3

U2CTSR2

U2CTSR1

bit 15

U-0

—

U-0

—

U-0

—

R/W-1

U2RXR4

U2RXR3

U2RXR2

U2RXR1

U2RXR0

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15-13

bit 12-8

bit 7-5

Unimplemented: Read as ‘0’

U2CTSR<4:0>: Assign UART2 Clear to Send (U2CTS) to Corresponding RPn or RPIn Pin bits

Unimplemented: Read as ‘0’

bit 4-0

U2RXR<4:0>: Assign UART2 Receive (U2RX) to Corresponding RPn or RPIn Pin bits

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DS39940D-page 139

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REGISTER 10-11: RPINR20: PERIPHERAL PIN SELECT INPUT REGISTER 20

U-0

—

U-0

—

U-0

—

R/W-1

SCK1R4

SCK1R3

SCK1R2

SCK1R1

SCK1R0

bit 15

bit 8

U-0

—

U-0

—

U-0

—

R/W-1

SDI1R4

SDI1R3

SDI1R2

SDI1R1

SDI1R0

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15-13

bit 12-8

bit 7-5

Unimplemented: Read as ‘0’

SCK1R<4:0>: Assign SPI1 Clock Input (SCK1IN) to Corresponding RPn or RPIn Pin bits

Unimplemented: Read as ‘0’

bit 4-0

SDI1R<4:0>: Assign SPI1 Data Input (SDI1) to Corresponding RPn or RPIn Pin bits

REGISTER 10-12: RPINR21: PERIPHERAL PIN SELECT INPUT REGISTER 21

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

bit 15

bit 8

U-0

—

U-0

—

U-0

—

R/W-1

SS1R4

SS1R3

SS1R2

SS1R1

SS1R0

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15-5

bit 4-0

Unimplemented: Read as ‘0’

SS1R<4:0>: Assign SPI1 Slave Select Input (SS1IN) to Corresponding RPn or RPIn Pin bits

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REGISTER 10-13: RPINR22: PERIPHERAL PIN SELECT INPUT REGISTER 22

U-0

—

U-0

—

U-0

—

R/W-1

SCK2R4

SCK2R3

SCK2R2

SCK2R1

SCK2R0

bit 15

bit 8

U-0

—

U-0

—

U-0

—

R/W-1

SDI2R4

SDI2R3

SDI2R2

SDI2R1

SDI2R0

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15-13

bit 12-8

bit 7-5

Unimplemented: Read as ‘0’

SCK2R<4:0>: Assign SPI2 Clock Input (SCK2IN) to Corresponding RPn or RPIn Pin bits

Unimplemented: Read as ‘0’

bit 4-0

SDI2R<4:0>: Assign SPI2 Data Input (SDI2) to Corresponding RPn or RPIn Pin bits

REGISTER 10-14: RPINR23: PERIPHERAL PIN SELECT INPUT REGISTER 23

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

bit 15

bit 8

U-0

—

U-0

—

U-0

—

R/W-1

SS2R4

SS2R3

SS2R2

SS2R1

SS2R0

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15-5

bit 4-0

Unimplemented: Read as ‘0’

SS2R<4:0>: Assign SPI2 Slave Select Input (SS2IN) to Corresponding RPn or RPIn Pin bits

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REGISTER 10-15: RPOR1: PERIPHERAL PIN SELECT OUTPUT REGISTER 1

U-0

—

U-0

—

U-0

—

R/W-0

RP3R4

RP3R3

RP3R2

RP3R1

RP3R0

bit 15

bit 8

U-0

—

U-0

—

U-0

—

R/W-0

RP2R4

RP2R3

RP2R2

RP2R1

RP2R0

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15-13

bit 12-8

Unimplemented: Read as ‘0’

RP3R<4:0>: RP3 Output Pin Mapping bits

Peripheral output number n is assigned to pin, RP3 (see Table 10-3 for peripheral function numbers).

Unimplemented: Read as ‘0’

bit 7-5

bit 4-0

RP2R<4:0>: RP2 Output Pin Mapping bits

Peripheral output number n is assigned to pin, RP2 (see Table 10-3 for peripheral function numbers).

REGISTER 10-16: RPOR1: PERIPHERAL PIN SELECT OUTPUT REGISTER 1

U-0

—

U-0

—

U-0

—

R/W-0

RP1R4

RP1R3

RP1R2

RP1R1

RP1R0

bit 15

bit 8

U-0

—

U-0

—

U-0

—

R/W-0

RP0R4

RP0R3

RP0R2

RP0R1

RP0R0

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15-13

bit 12-8

Unimplemented: Read as ‘0’

RP1R<4:0<: RP1 Output Pin Mapping bits

Peripheral output number n is assigned to pin, RP1 (see Table 10-3 for peripheral function numbers).

Unimplemented: Read as ‘0’

bit 7-5

bit 4-0

RP0R<4:0>: RP0 Output Pin Mapping bits

Peripheral output number n is assigned to pin, RP0 (see Table 10-3 for peripheral function numbers).

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REGISTER 10-17: RPOR2: PERIPHERAL PIN SELECT OUTPUT REGISTER 2

U-0

—

U-0

—

U-0

—

R/W-0

RP5R4

RP5R3

RP5R2

RP5R1

RP5R0

bit 15

bit 8

U-0

—

U-0

—

U-0

—

R/W-0

RP4R4

RP4R3

RP4R2

RP4R1

RP4R0

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15-13

bit 12-8

Unimplemented: Read as ‘0’

RP5R<4:0>: RP5 Output Pin Mapping bits⁽¹⁾

Peripheral output number n is assigned to pin, RP5 (see Table 10-3 for peripheral function numbers).

Unimplemented: Read as ‘0’

bit 7-5

bit 4-0

RP4R<4:0>: RP4 Output Pin Mapping bits

Peripheral output number n is assigned to pin, RP4 (see Table 10-3 for peripheral function numbers).

REGISTER 10-18: RPOR3: PERIPHERAL PIN SELECT OUTPUT REGISTER 3

U-0

—

U-0

—

U-0

—

R/W-0

RP7R4

RP7R3

RP7R2

RP7R1

RP7R0

bit 15

bit 8

U-0

—

U-0

—

U-0

—

R/W-0

RP6R4

RP6R3

RP6R2

RP6R1

RP6R0

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15-13

bit 12-8

Unimplemented: Read as ‘0’

RP7R<4:0>: RP7 Output Pin Mapping bits

Peripheral output number n is assigned to pin, RP7 (see Table 10-3 for peripheral function numbers).

Unimplemented: Read as ‘0’

bit 7-5

bit 4-0

RP6R<4:0>: RP6 Output Pin Mapping bits

Peripheral output number n is assigned to pin, RP6 (see Table 10-3 for peripheral function numbers).

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REGISTER 10-19: RPOR4: PERIPHERAL PIN SELECT OUTPUT REGISTER 4

U-0

—

U-0

—

U-0

—

R/W-0

RP9R4

RP9R3

RP9R2

RP9R1

RP9R0

bit 15

bit 8

U-0

—

U-0

—

U-0

—

R/W-0

RP8R4

RP8R3

RP8R2

RP8R1

RP8R0

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15-13

bit 12-8

Unimplemented: Read as ‘0’

RP9R<4:0>: RP9 Output Pin Mapping bits

Peripheral output number n is assigned to pin, RP9 (see Table 10-3 for peripheral function numbers).

Unimplemented: Read as ‘0’

bit 7-5

bit 4-0

RP8R<4:0>: RP8 Output Pin Mapping bits

Peripheral output number n is assigned to pin, RP8 (see Table 10-3 for peripheral function numbers).

REGISTER 10-20: RPOR5: PERIPHERAL PIN SELECT OUTPUT REGISTER 5

U-0

—

U-0

—

U-0

—

R/W-0

RP11R4

RP11R3

RP11R2

RP11R1

RP11R0

bit 15

bit 8

U-0

—

U-0

—

U-0

—

R/W-0

RP10R4

RP10R3

RP10R2

RP10R1

RP10R0

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15-13

bit 12-8

Unimplemented: Read as ‘0’

RP11R<4:0>: RP11 Output Pin Mapping bits

Peripheral output number n is assigned to pin, RP11 (see Table 10-3 for peripheral function numbers).

Unimplemented: Read as ‘0’

bit 7-5

bit 4-0

RP10R<4:0>: RP10 Output Pin Mapping bits

Peripheral output number n is assigned to pin, RP10 (see Table 10-3 for peripheral function numbers).

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REGISTER 10-21: RPOR6: PERIPHERAL PIN SELECT OUTPUT REGISTER 6

U-0

—

U-0

—

U-0

—

R/W-0

RP13R4

RP13R3

RP13R2

RP13R1

RP13R0

bit 15

bit 8

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15-13

bit 12-8

Unimplemented: Read as ‘0’

RP13R<4:0>: RP13 Output Pin Mapping bits

Peripheral output number n is assigned to pin, RP13 (see Table 10-3 for peripheral function numbers).

bit 7-0

Unimplemented: Read as ‘0’

REGISTER 10-22: RPOR7: PERIPHERAL PIN SELECT OUTPUT REGISTER 7

U-0

—

U-0

—

U-0

—

R/W-0

RP15R4

RP15R3

RP15R2

RP15R1

RP15R0

bit 15

bit 8

U-0

—

U-0

—

U-0

—

R/W-0

RP14R4

RP14R3

RP14R2

RP14R1

RP14R0

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15-13

bit 12-8

Unimplemented: Read as ‘0’

RP15R<4:0>: RP15 Output Pin Mapping bits

Peripheral output number n is assigned to pin, RP0 (see Table 10-3 for peripheral function numbers).

Unimplemented: Read as ‘0’

bit 7-5

bit 4-0

RP14R<4:0>: RP14 Output Pin Mapping bits

Peripheral output number n is assigned to pin, RP14 (see Table 10-3 for peripheral function numbers).

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REGISTER 10-23: RPOR8: PERIPHERAL PIN SELECT OUTPUT REGISTER 8⁽¹⁾

U-0

—

U-0

—

U-0

—

R/W-0

RP17R4

RP17R3

RP17R2

RP17R1

RP17R0

bit 15

bit 8

U-0

—

U-0

—

U-0

—

R/W-0

RP16R4

RP16R3

RP16R2

RP16R1

RP16R0

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15-13

bit 12-8

Unimplemented: Read as ‘0’

RP17R<4:0>: RP17 Output Pin Mapping bits

Peripheral output number n is assigned to pin, RP17 (see Table 10-3 for peripheral function numbers).

Unimplemented: Read as ‘0’

bit 7-5

bit 4-0

RP16R<4:0>: RP16 Output Pin Mapping bits

Peripheral output number n is assigned to pin, RP16 (see Table 10-3 for peripheral function numbers).

Note 1: This register is unimplemented in 28-pin devices; all bits read as ‘0’.

REGISTER 10-24: RPOR9: PERIPHERAL PIN SELECT OUTPUT REGISTER 9⁽¹⁾

U-0

—

U-0

—

U-0

—

R/W-0

RP19R4

RP19R3

RP19R2

RP19R1

RP19R0

bit 15

bit 8

U-0

—

U-0

—

U-0

—

R/W-0

RP18R4

RP18R3

RP18R2

RP18R1

RP18R0

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15-13

bit 12-8

Unimplemented: Read as ‘0’

RP19R<4:0>: RP19 Output Pin Mapping bits

Peripheral output number n is assigned to pin, RP19 (see Table 10-3 for peripheral function numbers).

Unimplemented: Read as ‘0’

bit 7-5

bit 4-0

RP18R<4:0>: RP18 Output Pin Mapping bits

Peripheral output number n is assigned to pin, RP18 (see Table 10-3 for peripheral function numbers).

Note 1: This register is unimplemented in 28-pin devices; all bits read as ‘0’.

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REGISTER 10-25: RPOR10: PERIPHERAL PIN SELECT OUTPUT REGISTER 10⁽¹⁾

U-0

—

U-0

—

U-0

—

R/W-0

RP21R4

RP21R3

RP21R2

RP21R1

RP21R0

bit 15

bit 8

U-0

—

U-0

—

U-0

—

R/W-0

RP20R4

RP20R3

RP20R2

RP20R1

RP20R0

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15-13

bit 12-8

Unimplemented: Read as ‘0’

RP21R<4:0>: RP21 Output Pin Mapping bits

Peripheral output number n is assigned to pin, RP21 (see Table 10-3 for peripheral function numbers).

Unimplemented: Read as ‘0’

bit 7-5

bit 4-0

RP20R<4:0>: RP20 Output Pin Mapping bits

Peripheral output number n is assigned to pin, RP20 (see Table 10-3 for peripheral function numbers).

Note 1: This register is unimplemented in 28-pin devices; all bits read as ‘0’.

REGISTER 10-26: RPOR11: PERIPHERAL PIN SELECT OUTPUT REGISTER 11⁽¹⁾

U-0

—

U-0

—

U-0

—

R/W-0

RP23R4

RP23R3

RP23R2

RP23R1

RP23R0

bit 15

bit 8

U-0

—

U-0

—

U-0

—

R/W-0

RP22R4

RP22R3

RP22R2

RP22R1

RP22R0

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15-13

bit 12-8

Unimplemented: Read as ‘0’

RP23R<4:0>: RP23 Output Pin Mapping bits

Peripheral output number n is assigned to pin, RP23 (see Table 10-3 for peripheral function numbers).

Unimplemented: Read as ‘0’

bit 7-5

bit 4-0

RP22R<4:0>: RP22 Output Pin Mapping bits

Peripheral output number n is assigned to pin, RP22 (see Table 10-3 for peripheral function numbers).

Note 1: This register is unimplemented in 28-pin devices; all bits read as ‘0’.

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REGISTER 10-27: RPOR12: PERIPHERAL PIN SELECT OUTPUT REGISTER 12⁽¹⁾

U-0

—

U-0

—

U-0

—

R/W-0

RP25R4

RP25R3

RP25R2

RP25R1

RP25R0

bit 15

bit 8

U-0

—

U-0

—

U-0

—

R/W-0

RP24R4

RP24R3

RP24R2

RP24R1

RP24R0

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15-13

bit 12-8

Unimplemented: Read as ‘0’

RP25R<5:0>: RP25 Output Pin Mapping bits

Peripheral output number n is assigned to pin, RP25 (see Table 10-3 for peripheral function numbers).

Unimplemented: Read as ‘0’

bit 7-5

bit 4-0

RP24R<5:0>: RP24 Output Pin Mapping bits

Peripheral output number n is assigned to pin, RP24 (see Table 10-3 for peripheral function numbers).

Note 1: This register is unimplemented in 28-pin devices; all bits read as ‘0’.

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Figure 11-1 presents a block diagram of the 16-bit timer

module.

11.0 TIMER1

Note:

This data sheet summarizes the features

of this group of PIC24F devices. It is not

intended to be a comprehensive reference

source. For more information, refer to the

“PIC24F Family Reference Manual”,

Section 14. “Timers” (DS39704).

To configure Timer1 for operation:

1. Set the TON bit (= 1).

2. Select the timer prescaler ratio using the

TCKPS<1:0> bits.

3. Set the Clock and Gating modes using the TCS

and TGATE bits.

The Timer1 module is a 16-bit timer which can serve as

the time counter for the Real-Time Clock (RTC) or

operate as a free-running, interval timer/counter.

Timer1 can operate in three modes:

4. Set or clear the TSYNC bit to configure

synchronous or asynchronous operation.

5. Load the timer period value into the PR1

register.

• 16-Bit Timer

6. If interrupts are required, set the interrupt enable

bit, T1IE. Use the priority bits, T1IP<2:0>, to set

the interrupt priority.

• 16-Bit Synchronous Counter

• 16-Bit Asynchronous Counter

Timer1 also supports these features:

• Timer Gate Operation

• Selectable Prescaler Settings

• Timer Operation during CPU Idle and Sleep

modes

• Interrupt on 16-Bit Period Register Match or

Falling Edge of External Gate Signal

FIGURE 11-1:

16-BIT TIMER1 MODULE BLOCK DIAGRAM

TCKPS<1:0>

TON

2

SOSCO/

1x

01

00

T1CK

Prescaler

1, 8, 64, 256

Gate

Sync

SOSCEN

SOSCI

TCY

TGATE

TCS

TGATE

1

0

Q

D

Set T1IF

CK

0

Reset

Equal

TMR1

Sync

1

TSYNC

Comparator

PR1

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REGISTER 11-1: T1CON: TIMER1 CONTROL REGISTER⁽¹⁾

R/W-0

TON

U-0

—

R/W-0

TSIDL

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

bit 15

bit 8

bit 0

U-0

—

R/W-0

U-0

—

R/W-0

TCS

U-0

—

TGATE

TCKPS1

TCKPS0

TSYNC

bit 7

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15

TON: Timer1 On bit

1= Starts 16-bit Timer1

0= Stops 16-bit Timer1

bit 14

bit 13

Unimplemented: Read as ‘0’

TSIDL: Stop in Idle Mode bit

1= Discontinue module operation when device enters Idle mode

0= Continue module operation in Idle mode

bit 12-7

bit 6

Unimplemented: Read as ‘0’

TGATE: Timer1 Gated Time Accumulation Enable bit

When TCS = 1:

This bit is ignored.

When TCS = 0:

1= Gated time accumulation is enabled

0= Gated time accumulation is disabled

bit 5-4

TCKPS<1:0>: Timer1 Input Clock Prescale Select bits

11= 1:256

10= 1:64

01= 1:8

00= 1:1

bit 3

bit 2

Unimplemented: Read as ‘0’

TSYNC: Timer1 External Clock Input Synchronization Select bit

When TCS = 1:

1= Synchronize external clock input

0= Do not synchronize external clock input

When TCS = 0:

This bit is ignored.

bit 1

bit 0

TCS: Timer1 Clock Source Select bit

1= External clock from T1CK pin (on the rising edge)

0= Internal clock (FOSC/2)

Unimplemented: Read as ‘0’

Note 1: Changing the value of TxCON while the timer is running (TON = 1) causes the timer prescale counter to

reset and is not recommended.

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To configure Timer2/3 or Timer4/5 for 32-bit operation:

12.0 TIMER2/3 AND TIMER4/5

1. Set the T32 bit (T2CON<3> or T4CON<3> = 1).

Note:

This data sheet summarizes the features

2. Select the prescaler ratio for Timer2 or Timer4

using the TCKPS<1:0> bits.

of this group of PIC24F devices. It is not

intended to be a comprehensive reference

source. For more information, refer to the

“PIC24F Family Reference Manual”,

Section 14. “Timers” (DS39704).

3. Set the Clock and Gating modes using the TCS

and TGATE bits. If TCS is set to an external clock,

RPINRx (TxCK) must be configured to an avail-

able RPn pin. See Section 10.4 “Peripheral Pin

Select (PPS)” for more information.

The Timer2/3 and Timer4/5 modules are 32-bit timers,

which can also be configured as four independent 16-bit

timers with selectable operating modes.

4. Load the timer period value. PR3 (or PR5) will

contain the most significant word of the value

while PR2 (or PR4) contains the least significant

word.

As 32-bit timers, Timer2/3 and Timer4/5 can each

operate in three modes:

5. If interrupts are required, set the interrupt enable

bit, T3IE or T5IE. Use the priority bits,

T3IP<2:0> or T5IP<2:0>, to set the interrupt pri-

ority. Note that while Timer2 or Timer4 controls

the timer, the interrupt appears as a Timer3 or

Timer5 interrupt.

• Two Independent 16-Bit Timers with all 16-Bit

Operating modes (except Asynchronous Counter

mode)

• Single 32-Bit Timer

• Single 32-Bit Synchronous Counter

They also support these features:

6. Set the TON bit (= 1).

• Timer Gate Operation

The timer value, at any point, is stored in the register

pair, TMR3:TMR2 (or TMR5:TMR4). TMR3 (TMR5)

always contains the most significant word of the count,

while TMR2 (TMR4) contains the least significant word.

• Selectable Prescaler Settings

• Timer Operation during Idle and Sleep modes

• Interrupt on a 32-Bit Period Register Match

• ADC Event Trigger (Timer4/5 only)

To configure any of the timers for individual 16-bit

operation:

Individually, all four of the 16-bit timers can function as

synchronous timers or counters. They also offer the

features listed above, except for the ADC event trigger;

this is implemented only with Timer5. The operating

modes and enabled features are determined by setting

the appropriate bit(s) in the T2CON, T3CON, T4CON

and T5CON registers. T2CON and T4CON are shown

in generic form in Register 12-1; T3CON and T5CON

are shown in Register 12-2.

1. Clear the T32 bit corresponding to that timer

(T2CON<3> for Timer2 and Timer3 or

T4CON<3> for Timer4 and Timer5).

2. Select the timer prescaler ratio using the

TCKPS<1:0> bits.

3. Set the Clock and Gating modes using the TCS

and TGATE bits. See Section 10.4 “Peripheral

Pin Select (PPS)” for more information.

For 32-bit timer/counter operation, Timer2 and Timer4

are the least significant word; Timer3 and Timer4 are

the most significant word of the 32-bit timers.

4. Load the timer period value into the PRx register.

5. If interrupts are required, set the interrupt enable

bit, TxIE; use the priority bits, TxIP<2:0>, to set

the interrupt priority.

Note:

For 32-bit operation, T3CON and T5CON

control bits are ignored. Only T2CON and

T4CON control bits are used for setup and

control. Timer2 and Timer4 clock and gate

inputs are utilized for the 32-bit timer

modules, but an interrupt is generated with

the Timer3 or Timer5 interrupt flags.

6. Set the TON bit (TxCON<15> = 1).

 2010 Microchip Technology Inc.

DS39940D-page 151

PIC24FJ64GB004 FAMILY

FIGURE 12-1:

TIMER2/3 AND TIMER4/5 (32-BIT) BLOCK DIAGRAM

TCKPS<1:0>

2

TON

T2CK

(T4CK)

1x

Prescaler

1, 8, 64, 256

Gate

01

00

Sync

TCY

(2)

TGATE

(2)

TCS

1

0

Q

D

Set T3IF (T5IF)

Q

CK

PR3

PR2

(PR5)

(PR4)

(3)

ADC Event Trigger

Equal

MSB

Comparator

LSB

TMR2

(TMR4)

TMR3

(TMR5)

Sync

Reset

16

(1)

Read TMR2 (TMR4)

Write TMR2 (TMR4)

16

TMR3HLD

(TMR5HLD)

Data Bus<15:0>

Note 1: The 32-Bit Timer Configuration bit, T32, must be set for 32-bit timer/counter operation. All control bits are

respective to the T2CON and T4CON registers.

2: The timer clock input must be assigned to an available RPn pin before use. Please see Section 10.4 “Peripheral

Pin Select (PPS)” for more information.

3: The ADC event trigger is available only on Timer 2/3 in 32-bit mode and Timer 3 in 16-bit mode.

DS39940D-page 152

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FIGURE 12-2:

TIMER2 AND TIMER4 (16-BIT SYNCHRONOUS) BLOCK DIAGRAM

TCKPS<1:0>

2

TON

T2CK

(T4CK)

1x

Prescaler

1, 8, 64, 256

Gate

Sync

01

00

TGATE

(1)

TCS

TGATE

TCY

(1)

Q

D

1

0

Set T2IF (T4IF)

Q

CK

Reset

Equal

TMR2 (TMR4)

Sync

Comparator

PR2 (PR4)

Note 1: The timer clock input must be assigned to an available RPn pin before use. Please see Section 10.4 “Peripheral

Pin Select (PPS)” for more information.

FIGURE 12-3:

TIMER3 AND TIMER5 (16-BIT ASYNCHRONOUS) BLOCK DIAGRAM

TCKPS<1:0>

2

TON

T3CK

(T5CK)

1x

01

00

Sync

Prescaler

1, 8, 64, 256

TGATE

(1)

TCS

TGATE

TCY

(1)

Q

D

1

0

Set T3IF (T5IF)

CK

Reset

Equal

TMR3 (TMR5)

(2)

ADC Event Trigger

Comparator

PR3 (PR5)

Note 1: The timer clock input must be assigned to an available RPn pin before use. Please see Section 10.4 “Peripheral

Pin Select (PPS)” for more information.

2: The ADC event trigger is available only on Timer3.

 2010 Microchip Technology Inc.

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REGISTER 12-1: TxCON: TIMER2 AND TIMER4 CONTROL REGISTER⁽³⁾

R/W-0

TON

U-0

—

R/W-0

TSIDL

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

bit 15

bit 8

bit 0

U-0

—

R/W-0

T32⁽¹⁾

U-0

—

R/W-0

TCS⁽²⁾

U-0

—

TGATE

TCKPS1

TCKPS0

bit 7

Legend:

R = Readable bit

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

-n = Value at POR

bit 15

TON: Timerx On bit

When TxCON<3> = 1:

1= Starts 32-bit Timerx/y

0= Stops 32-bit Timerx/y

When TxCON<3> = 0:

1= Starts 16-bit Timerx

0= Stops 16-bit Timerx

bit 14

bit 13

Unimplemented: Read as ‘0’

TSIDL: Stop in Idle Mode bit

1= Discontinue module operation when device enters Idle mode

0= Continue module operation in Idle mode

bit 12-7

bit 6

Unimplemented: Read as ‘0’

TGATE: Timerx Gated Time Accumulation Enable bit

When TCS = 1:

This bit is ignored.

When TCS = 0:

1= Gated time accumulation is enabled

0= Gated time accumulation is disabled

bit 5-4

bit 3

TCKPS<1:0>: Timerx Input Clock Prescale Select bits

11= 1:256

10= 1:64

01= 1:8

00= 1:1

T32: 32-Bit Timer Mode Select bit⁽¹⁾

1= Timerx and Timery form a single 32-bit timer

0= Timerx and Timery act as two 16-bit timers

In 32-bit mode, T3CON control bits do not affect 32-bit timer operation.

bit 2

bit 1

Unimplemented: Read as ‘0’

TCS: Timerx Clock Source Select bit⁽²⁾

1= External clock from pin, TxCK (on the rising edge)

0= Internal clock (FOSC/2)

bit 0

Unimplemented: Read as ‘0’

Note 1: In 32-bit mode, the T3CON or T5CON control bits do not affect 32-bit timer operation.

2: If TCS = 1, RPINRx (TxCK) must be configured to an available RPn pin. For more information, see

Section 10.4 “Peripheral Pin Select (PPS)”.

3: Changing the value of TxCON while the timer is running (TON = 1) causes the timer prescale counter to

reset and is not recommended.

DS39940D-page 154

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REGISTER 12-2: TyCON: TIMER3 AND TIMER5 CONTROL REGISTER⁽³⁾

R/W-0

TON⁽¹⁾

U-0

—

R/W-0

TSIDL⁽¹⁾

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

bit 15

bit 8

bit 0

U-0

—

R/W-0

TGATE⁽¹⁾

R/W-0

TCKPS1⁽¹⁾

R/W-0

TCKPS0⁽¹⁾

U-0

—

U-0

—

R/W-0

TCS^(1,2)

U-0

—

bit 7

Legend:

R = Readable bit

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

-n = Value at POR

bit 15

TON: Timery On bit⁽¹⁾

1= Starts 16-bit Timery

0= Stops 16-bit Timery

bit 14

bit 13

Unimplemented: Read as ‘0’

TSIDL: Stop in Idle Mode bit⁽¹⁾

1= Discontinue module operation when device enters Idle mode

0= Continue module operation in Idle mode

bit 12-7

bit 6

Unimplemented: Read as ‘0’

TGATE: Timery Gated Time Accumulation Enable bit⁽¹⁾

When TCS = 1:

This bit is ignored.

When TCS = 0:

1= Gated time accumulation enabled

0= Gated time accumulation disabled

bit 5-4

TCKPS<1:0>: Timery Input Clock Prescale Select bits⁽¹⁾

11= 1:256

10= 1:64

01= 1:8

00= 1:1

bit 3-2

bit 1

Unimplemented: Read as ‘0’

TCS: Timery Clock Source Select bit^(1,2)

1= External clock from pin TyCK (on the rising edge)

0= Internal clock (FOSC/2)

bit 0

Unimplemented: Read as ‘0’

Note 1: When 32-bit operation is enabled (T2CON<3> or T4CON<3> = 1), these bits have no effect on Timery

operation; all timer functions are set through T2CON and T4CON.

2: If TCS = 1, RPINRx (TxCK) must be configured to an available RPn pin. See Section 10.4 “Peripheral

Pin Select (PPS)” for more information.

3: Changing the value of TyCON while the timer is running (TON = 1) causes the timer prescale counter to

reset and is not recommended.

 2010 Microchip Technology Inc.

DS39940D-page 155

PIC24FJ64GB004 FAMILY

NOTES:

DS39940D-page 156

 2010 Microchip Technology Inc.

PIC24FJ64GB004 FAMILY

13.1 General Operating Modes

13.0 INPUT CAPTURE WITH

DEDICATED TIMERS

13.1.1

SYNCHRONOUS AND TRIGGER

MODES

Note:

This data sheet summarizes the features

of this group of PIC24F devices. It is not

intended to be a comprehensive reference

source. For more information, refer to the

“PIC24F Family Reference Manual”,

Section 34. “Input Capture with

Dedicated Timer” (DS39722).

By default, the input capture module operates in a

free-running mode. The internal 16-bit counter,

ICxTMR, counts up continuously, wrapping around

from FFFFh to 0000h on each overflow, with its period

synchronized to the selected external clock source.

When a capture event occurs, the current 16-bit value

of the internal counter is written to the FIFO buffer.

Devices in the PIC24FJ64GB004 family all feature

5 independent input capture modules. Each of the

modules offers a wide range of configuration and

operating options for capturing external pulse events

and generating interrupts.

In Synchronous mode, the module begins capturing

events on the ICx pin as soon as its selected clock

source is enabled. Whenever an event occurs on the

selected sync source, the internal counter is reset. In

Trigger mode, the module waits for a Sync event from

another internal module to occur before allowing the

internal counter to run.

Key features of the input capture module include:

• Hardware-configurable for 32-bit operation in all

modes by cascading two adjacent modules

Standard, free-running operation is selected by setting

the SYNCSEL bits to ‘00000’ and clearing the ICTRIG

bit (ICxCON2<7>). Synchronous and Trigger modes

are selected any time the SYNCSEL bits are set to any

value except ‘00000’. The ICTRIG bit selects either

Synchronous or Trigger mode; setting the bit selects

Trigger mode operation. In both modes, the SYNCSEL

bits determine the sync/trigger source.

• Synchronous and Trigger modes of output

compare operation, with up to 20 user-selectable

trigger/sync sources available

• A 4-level FIFO buffer for capturing and holding

timer values for several events

• Configurable interrupt generation

• Up to 6 clock sources available for each module,

driving a separate internal 16-bit counter

When the SYNCSEL bits are set to ‘00000’ and

ICTRIG is set, the module operates in Software Trigger

mode. In this case, capture operations are started by

manually setting the TRIGSTAT bit (ICxCON2<6>).

The module is controlled through two registers:

ICxCON1 (Register 13-1) and ICxCON2 (Register 13-2).

A general block diagram of the module is shown in

Figure 13-1.

FIGURE 13-1:

INPUT CAPTURE BLOCK DIAGRAM

ICM<2:0>

ICI<1:0>

Event and

Interrupt

Logic

Set ICxIF

Edge Detect Logic

Prescaler

Counter

1:1/4/16

and

Clock Synchronizer

(1)

ICx Pin

ICTSEL<2:0>

Increment

Clock

16

IC Clock

Sources

Select

ICxTMR

4-Level FIFO Buffer

16

Trigger and

Sync Logic

16

Reset

Trigger and

Sync Sources

ICxBUF

SYNCSEL<4:0>

Trigger

System Bus

ICOV, ICBNE

Note 1: The ICx inputs must be assigned to an available RPn pin before use. Please see Section 10.4 “Peripheral

Pin Select (PPS)” for more information.

 2010 Microchip Technology Inc.

DS39940D-page 157

PIC24FJ64GB004 FAMILY

For 32-bit cascaded operations, the setup procedure is

slightly different:

13.1.2

CASCADED (32-BIT) MODE

By default, each module operates independently with

its own 16-bit timer. To increase resolution, adjacent

even and odd modules can be configured to function as

a single 32-bit module. (For example, Modules 1 and 2

are paired, as are modules 3 and 4, and so on.) The

odd-numbered module (ICx) provides the Least Signif-

icant 16 bits of the 32-bit register pairs, and the even

module (ICy) provides the Most Significant 16 bits.

Wrap-arounds of the ICx registers cause an increment

of their corresponding ICy registers.

1. Set the IC32 bits for both modules

(ICyCON2<8> and (ICxCON2<8>), enabling the

even-numbered module first. This ensures the

modules will start functioning in unison.

2. Set the ICTSEL and SYNCSEL bits for both

modules to select the same sync/trigger and

time base source. Set the even module first,

then the odd module. Both modules must use

the same ICTSEL and SYNCSEL settings.

3. Clear the ICTRIG bit of the even module

(ICyCON2<7>); this forces the module to run in

Synchronous mode with the odd module,

regardless of its trigger setting.

Cascaded operation is configured in hardware by

setting the IC32 bits (ICxCON2<8>) for both modules.

13.2 Capture Operations

4. Use the odd module’s ICI bits (ICxCON1<6:5>)

to the desired interrupt frequency.

The input capture module can be configured to capture

timer values and generate interrupts on rising edges on

ICx, or all transitions on ICx. Captures can be configured

to occur on all rising edges or just some (every 4th or

16th). Interrupts can be independently configured to

generate on each event or a subset of events.

5. Use the ICTRIG bit of the odd module

(ICxCON2<7>) to configure Trigger or

Synchronous mode operation.

Note:

For Synchronous mode operation, enable

the sync source as the last step. Both

input capture modules are held in Reset

until the sync source is enabled.

To set up the module for capture operations:

1. Configure the ICx input for one of the available

Peripheral Pin Select pins.

6. Use the ICM bits of the odd module

(ICxCON1<2:0>) to set the desired capture

mode.

2. If Synchronous mode is to be used, disable the

sync source before proceeding.

3. Make sure that any previous data has been

removed from the FIFO by reading ICxBUF until

the ICBNE bit (ICxCON1<3>) is cleared.

The module is ready to capture events when the time

base and the trigger/sync source are enabled. When

the ICBNE bit (ICxCON1<3>) becomes set, at least

one capture value is available in the FIFO. Read input

capture values from the FIFO until the ICBNE clears to

‘0’.

4. Set the SYNCSEL bits (ICxCON2<4:0>) to the

desired sync/trigger source.

5. Set the ICTSEL bits (ICxCON1<12:10>) for the

desired clock source. If the desired clock source

is running, set the ICTSEL bits before the Input

Capture module is enabled for proper

synchronization with the desired clock source.

For 32-bit operation, read both the ICxBUF and

ICyBUF for the full 32-bit timer value (ICxBUF for the

lsw, ICyBUF for the msw). At least one capture value is

available in the FIFO buffer when the odd module’s

ICBNE bit (ICxCON1<3>) becomes set. Continue to

read the buffer registers until ICBNE is cleared

(perform automatically by hardware).

6. Set the ICI bits (ICxCON1<6:5>) to the desired

interrupt frequency

7. Select Synchronous or Trigger mode operation:

a) Check that the SYNCSEL bits are not set to

‘00000’.

b) For Synchronous mode, clear the ICTRIG

bit (ICxCON2<7>).

c) For Trigger mode, set ICTRIG and clear the

TRIGSTAT bit (ICxCON2<6>).

8. Set the ICM bits (ICxCON1<2:0>) to the desired

operational mode.

9. Enable the selected trigger/sync source.

DS39940D-page 158

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REGISTER 13-1: ICxCON1: INPUT CAPTURE x CONTROL REGISTER 1

U-0

—

U-0

—

U-0

—

U-0

—

R/W-0

ICSIDL

ICTSEL2

ICTSEL1

ICTSEL0

bit 15

bit 8

U-0

—

R/W-0

ICI1

R/W-0

ICI0

R-0, HCS

ICOV

R-0, HCS

ICBNE

R/W-0

ICM2⁽¹⁾

R/W-0

ICM1⁽¹⁾

R/W-0

ICM0⁽¹⁾

bit 7

bit 0

Legend:

HCS = Hardware Clearable/Settable bit

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15-14

bit 13

Unimplemented: Read as ‘0’

ICSIDL: Input Capture x Module Stop in Idle Control bit

1= Input capture module halts in CPU Idle mode

0= Input capture module continues to operate in CPU Idle mode

bit 12-10

ICTSEL<2:0>: Input Capture Timer Select bits

111= System clock (FOSC/2)

110= Reserved

101= Reserved

100= Timer1

011= Timer5

010= Timer4

001= Timer2

000= Timer3

bit 9-7

bit 6-5

Unimplemented: Read as ‘0’

ICI<1:0>: Select Number of Captures per Interrupt bits

11= Interrupt on every fourth capture event

10= Interrupt on every third capture event

01= Interrupt on every second capture event

00= Interrupt on every capture event

bit 4

ICOV: Input Capture x Overflow Status Flag bit (read-only)

1= Input capture overflow occurred

0= No input capture overflow occurred

bit 3

ICBNE: Input Capture x Buffer Empty Status bit (read-only)

1= Input capture buffer is not empty, at least one more capture value can be read

0= Input capture buffer is empty

bit 2-0

ICM<2:0>: Input Capture Mode Select bits⁽¹⁾

111= Interrupt mode: input capture functions as interrupt pin only when device is in Sleep or Idle mode

(rising edge detect only, all other control bits are not applicable)

110= Unused (module disabled)

101= Prescaler Capture mode: capture on every 16th rising edge

100= Prescaler Capture mode: capture on every 4th rising edge

011= Simple Capture mode: capture on every rising edge

010= Simple Capture mode: capture on every falling edge

001= Edge Detect Capture mode: capture on every edge (rising and falling); ICI<1:0 bits do not

control interrupt generation for this mode

000= Input capture module turned off

Note 1: The ICx input must also be configured to an available RPn pin. For more information, see Section 10.4

“Peripheral Pin Select (PPS)”.

 2010 Microchip Technology Inc.

DS39940D-page 159

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REGISTER 13-2: ICxCON2: INPUT CAPTURE x CONTROL REGISTER 2

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

R/W-0

IC32

bit 15

bit 8

R/W-0

R/W-0, HS

TRIGSTAT

U-0

—

R/W-0

R/W-1

R/W-0

R/W-1

ICTRIG

SYNCSEL4 SYNCSEL3 SYNCSEL2 SYNCSEL1 SYNCSEL0

bit 0

bit 7

Legend:

HS = Hardware Settable bit

W = Writable bit

R = Readable bit

-n = Value at POR

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

‘1’ = Bit is set

bit 15-9

bit 8

Unimplemented: Read as ‘0’

IC32: Cascade Two IC Modules Enable bit (32-bit operation)

1= ICx and ICy operate in cascade as a 32-bit module (this bit must be set in both modules)

0= ICx functions independently as a 16-bit module

bit 7

bit 6

ICTRIG: ICx Trigger/Sync Select bit

1= Trigger ICx from source designated by SYNCSELx bits

0= Synchronize ICx with source designated by SYNCSELx bits

TRIGSTAT: Timer Trigger Status bit

1= Timer source has been triggered and is running (set in hardware, can be set in software)

0= Timer source has not been triggered and is being held clear

bit 5

Unimplemented: Read as ‘0’

bit 4-0

SYNCSEL<4:0>: Trigger/Synchronization Source Selection bits

11111= Reserved

11110= Reserved

11101= Reserved

11100= CTMU⁽¹⁾

11011= A/D⁽¹⁾

11010= Comparator 3⁽¹⁾

11001= Comparator 2⁽¹⁾

11000= Comparator 1⁽¹⁾

10111= Input Capture 4

10110= Input Capture 3

10101= Input Capture 2

10100= Input Capture 1

10011= Reserved

10010= Reserved

1000x= Reserved

01111= Timer5

01110= Timer4

01101= Timer3

01100= Timer2

01011= Timer1

01010= Input Capture 5

01001= Reserved

01000= Reserved

00111= Reserved

00110= Reserved

00101= Output Compare 5

00100= Output Compare 4

00011= Output Compare 3

00010= Output Compare 2

00001= Output Compare 1

00000= Not synchronized to any other module

Note 1: Use these inputs as trigger sources only and never as sync sources.

DS39940D-page 160

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In Synchronous mode, the module begins performing

its compare or PWM operation as soon as its selected

clock source is enabled. Whenever an event occurs on

14.0 OUTPUT COMPARE WITH

DEDICATED TIMERS

the selected sync source, the module’s internal counter

is reset. In Trigger mode, the module waits for a sync

event from another internal module to occur before

allowing the counter to run.

Note:

This data sheet summarizes the features

of this group of PIC24F devices. It is not

intended to be a comprehensive reference

source. For more information, refer to the

“PIC24F Family Reference Manual”,

Section 35. “Output Capture with

Dedicated Timer” (DS39723).

Free-Running mode is selected by default or any time

that the SYNCSEL bits (OCxCON2<4:0>) are set to

‘00000’. Synchronous or Trigger modes are selected

any time the SYNCSEL bits are set to any value except

‘00000’. The OCTRIG bit (OCxCON2<7>) selects

either Synchronous or Trigger mode; setting the bit

selects Trigger mode operation. In both modes, the

SYNCSEL bits determine the sync/trigger source.

All devices in the PIC24FJ64GB004 family features

5 independent output compare modules. Each of these

modules offers a wide range of configuration and oper-

ating options for generating pulse trains on internal

device events, and can produce Pulse-Width Modulated

(PWM) waveforms for driving power applications.

14.1.2

CASCADED (32-BIT) MODE

Key features of the output compare module include:

By default, each module operates independently with

its own set of 16-bit Timer and Duty Cycle registers. To

increase the range, adjacent even and odd modules

can be configured to function as a single 32-bit module.

(For example, Modules 1 and 2 are paired, as are

Modules 3 and 4, and so on.) The odd-numbered

module (OCx) provides the Least Significant 16 bits of

the 32-bit register pairs and the even-numbered

module (OCy) provides the Most Significant 16 bits.

Wrap-arounds of the OCx registers cause an increment

of their corresponding OCy registers.

• Hardware-configurable for 32-bit operation in all

modes by cascading two adjacent modules

• Synchronous and Trigger modes of output

compare operation, with up to 21 user-selectable

trigger/sync sources available

• Two separate Period registers (a main register,

OCxR, and a secondary register, OCxRS) for

greater flexibility in generating pulses of varying

widths

• Configurable for single pulse or continuous pulse

generation on an output event or continuous

PWM waveform generation

Cascaded operation is configured in hardware by setting

the OC32 bit (OCxCON2<8>) for both modules.

• Up to 6 clock sources available for each module,

driving a separate internal 16-bit counter

14.1 General Operating Modes

14.1.1

SYNCHRONOUS AND TRIGGER

MODES

By default, the output compare module operates in a

Free-Running mode. The internal 16-bit counter,

OCxTMR, runs counts up continuously, wrapping

around from FFFFh to 0000h on each overflow with its

period synchronized to the selected external clock

source. Compare or PWM events are generated each

time a match between the internal counter and one of

the Period registers occurs.

 2010 Microchip Technology Inc.

Preliminary

DS39940D-page 161

PIC24FJ64GB004 FAMILY

FIGURE 14-1:

OUTPUT COMPARE BLOCK DIAGRAM (16-BIT MODE)

DCBx

OCMx

OCINV

OCxCON1

OCxCON2

OCTRIS

FLTOUT

FLTTRIEN

FLTMD

ENFLTx

OCFLTx

OCTSELx

SYNCSELx

TRIGSTAT

TRIGMODE

OCTRIG

OCxR

(1)

OCx Pin

Match Event

Comparator

Increment

Clock

Select

OC Clock

Sources

OC Output and

Fault Logic

OCxTMR

Comparator

OCxRS

OCFA/

OCFB/

Reset

CxOUT

Match Event

Trigger and

Sync Sources

Trigger and

Sync Logic

Reset

OCx Interrupt

Note 1: The OCx outputs must be assigned to an available RPn pin before use. Please see Section 10.4 “Peripheral

Pin Select (PPS)” for more information.

DS39940D-page 162

Preliminary

 2010 Microchip Technology Inc.

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For 32-bit cascaded operation, these steps are also

necessary:

14.2 Compare Operations

In Compare mode (Figure 14-1), the output compare

module can be configured for single-shot or continuous

pulse generation; it can also repeatedly toggle an

output pin on each timer event.

1. Set the OC32 bits for both registers

(OCyCON2<8> and (OCxCON2<8>). Enable

the even-numbered module first to ensure the

modules will start functioning in unison.

To set up the module for compare operations:

2. Clear the OCTRIG bit of the even module

(OCyCON2), so the module will run in

Synchronous mode.

1. Configure the OCx output for one of the

available Peripheral Pin Select pins.

2. Calculate the required values for the OCxR and

(for Double Compare modes) OCxRS Duty Cycle

registers:

3. Configure the desired output and Fault settings

for OCy.

4. Force the output pin for OCx to the output state

by clearing the OCTRIS bit.

a) Determine the instruction clock cycle time.

Take into account the frequency of the

external clock to the timer source (if one is

used) and the timer prescaler settings.

5. If Trigger mode operation is required, configure

the trigger options in OCx by using the OCTRIG

(OCxCON2<7>), TRIGSTAT (OCxCON2<6>)

and SYNCSEL (OCxCON2<4:0>) bits.

b) Calculate time to the rising edge of the

output pulse relative to the timer start value

(0000h).

6. Configure the desired Compare or PWM mode

of operation (OCM<2:0>) for OCy first, then for

OCx.

c) Calculate the time to the falling edge of the

pulse based on the desired pulse width and

the time to the rising edge of the pulse.

Depending on the output mode selected, the module

holds the OCx pin in its default state and forces a

transition to the opposite state when OCxR matches

the timer. In Double Compare modes, OCx is forced

back to its default state when a match with OCxRS

occurs. The OCxIF interrupt flag is set after an OCxR

match in Single Compare modes and after each

OCxRS match in Double Compare modes.

3. Write the rising edge value to OCxR and the

falling edge value to OCxRS.

4. For Trigger mode operations, set OCTRIG to

enable Trigger mode. Set or clear TRIGMODE to

configure trigger operation and TRIGSTAT to

select a hardware or software trigger. For

Synchronous mode, clear OCTRIG.

Single-shot pulse events only occur once, but may be

repeated by simply rewriting the value of the

OCxCON1 register. Continuous pulse events continue

indefinitely until terminated.

5. Set the SYNCSEL<4:0> bits to configure the

trigger or synchronization source. If free-running

timer operation is required, set the SYNCSEL

bits to ‘00000’ (no sync/trigger source).

6. Select the time base source with the

OCTSEL<2:0> bits. If the desired clock source is

running, set the OCTSEL<2:0> bits before the

output compare module is enabled for proper

synchronization with the desired clock source. If

necessary, set the TON bit for the selected timer

which enables the compare time base to count.

Synchronous mode operation starts as soon as

the synchronization source is enabled. Trigger

mode operation starts after a trigger source event

occurs.

7. Set the OCM<2:0> bits for the appropriate

compare operation (= 0xx).

 2010 Microchip Technology Inc.

Preliminary

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PIC24FJ64GB004 FAMILY

5. Select

a clock source by writing to the

14.3 Pulse-Width Modulation (PWM)

Mode

OCTSEL2<2:0> (OCxCON1<12:10>) bits.

6. Enable interrupts, if required, for the timer and

output compare modules. The output compare

interrupt is required for PWM Fault pin utilization.

In PWM mode, the output compare module can be

configured for edge-aligned or center-aligned pulse

waveform generation. All PWM operations are

double-buffered (buffer registers are internal to the

module and are not mapped into SFR space).

7. Select the desired PWM mode in the OCM<2:0>

(OCxCON1<2:0>) bits.

8. If a timer is selected as a clock source, set the

TMRy prescale value and enable the time base by

setting the TON (TxCON<15>) bit.

To configure the output compare module for

edge-aligned PWM operation:

Note:

This peripheral contains input and output

functions that may need to be configured

by the Peripheral Pin Select. See

Section 10.4 “Peripheral Pin Select

(PPS)” for more information.

1. Configure the OCx output for one of the

available Peripheral Pin Select pins.

2. Calculate the desired on-time and load it into the

OCxR register.

3. Calculate the desired period and load it into the

OCxRS register.

4. Select the current OCx as the synchronization

source by writing 0x1F to SYNCSEL<4:0>

(OCxCON2<4:0>) and ‘0’ to OCTRIG

(OCxCON2<7>).

FIGURE 14-2:

OUTPUT COMPARE BLOCK DIAGRAM

(DOUBLE-BUFFERED, 16-BIT PWM MODE)

OCxCON1

OCxCON2

OCMx

OCINV

OCTSELx

OCTRIS

FLTOUT

FLTTRIEN

FLTMD

SYNCSELx

TRIGSTAT

TRIGMODE

OCTRIG

OCxR and DCB<1:0>

Rollover/Reset

ENFLTx

OCFLTx

DCB<1:0>

OCxR and DCB<1:0> Buffers

(1)

OCx Pin

Comparator

Match

Event

Increment

Clock

Select

OC Clock

Sources

OC Output Timing

and Fault Logic

OCxTMR

Comparator

OCxRS Buffer

Rollover

Reset

OCFA/OCFB/CxOUT

Match

Event

Match Event

Trigger and

Sync Logic

Trigger and

Sync Sources

Rollover/Reset

OCxRS

OCx Interrupt

Reset

Note 1: The OCx outputs must be assigned to an available RPn pin before use. Please see Section 10.4 “Peripheral Pin

Select (PPS)” for more information.

DS39940D-page 164

Preliminary

 2010 Microchip Technology Inc.

PIC24FJ64GB004 FAMILY

14.3.1

PWM PERIOD

14.3.2

PWM DUTY CYCLE

In edge aligned PWM mode, the period is specified by

the value of OCxRS register. In center aligned PWM

mode, the period of the synchronization source such as

Timer's PRy specifies the period. The period in both

cases can be calculated using Equation 14-1.

The PWM duty cycle is specified by writing to the

OCxRS and OCxR registers. The OCxRS and OCxR

registers can be written to at any time, but the duty

cycle value is not latched until a period is complete.

This provides a double buffer for the PWM duty cycle

and is essential for glitchless PWM operation.

EQUATION 14-1: CALCULATING THE PWM

PERIOD⁽¹⁾

Some important boundary parameters of the PWM duty

cycle include:

PWM Period = [Value + 1] x TCY x (Prescaler Value)

• Edge-Aligned PWM

- If OCxR and OCxRS are loaded with 0000h,

the OCx pin will remain low (0% duty cycle).

Where: Value = OCxRS in Edge-Aligned PWM mode

and can be PRy in Center-Aligned PWM mode

(If TMRy is the sync source).

- If OCxRS is greater than OCxR, the pin will

remain high (100% duty cycle).

Note 1: Based on TCY = TOSC * 2; Doze mode

• Center-Aligned PWM (with TMRy as the sync

source)

and PLL are disabled.

- If OCxR, OCxRS and PRy are all loaded with

0000h, the OCx pin will remain low (0% duty

cycle).

- If OCxRS is greater than PRy, the pin will go

high (100% duty cycle).

See Example 14-1 for PWM mode timing details.

Table 14-1 and Table 14-2 show example PWM

frequencies and resolutions for a device operating at

4 MIPS and 10 MIPS, respectively.

EQUATION 14-2: CALCULATION FOR MAXIMUM PWM RESOLUTION⁽¹⁾

FCY

log₁₀

(

)

FPWM • (Prescale Value)

Maximum PWM Resolution (bits) =

log₁₀(2)

bits

Note 1: Based on FCY = FOSC/2; Doze mode and PLL are disabled.

EXAMPLE 14-1:

PWM PERIOD AND DUTY CYCLE CALCULATIONS⁽¹⁾

1. Find the OCxRS register value for a desired PWM frequency of 52.08 kHz, where FOSC = 8 MHz with PLL (32 MHz device

clock rate) and a prescaler setting of 1:1 using Edge-Aligned PWM mode.

TCY = 2 * TOSC = 62.5 ns

PWM Period = 1/PWM Frequency = 1/52.08 kHz = 19.2 s

PWM Period = (OCxRS + 1) • TCY • (OCx Prescale Value)

19.2 s

OCxRS

= (OCxRS + 1) • 62.5 ns • 1

= 306

2. Find the maximum resolution of the duty cycle that can be used with a 52.08 kHz frequency and a 32 MHz device clock rate:

PWM Resolution = log₁₀(FCY/FPWM)/log₁₀2) bits

= (log₁₀(16 MHz/52.08 kHz)/log₁₀2) bits

= 8.3 bits

Note 1: Based on TCY = 2 * TOSC; Doze mode and PLL are disabled.

 2010 Microchip Technology Inc.

Preliminary

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The DCB bits are intended for use with a clock source

14.4 Subcycle Resolution

identical to the system clock. When an OCx module

with enabled prescaler is used, the falling edge delay

caused by the DCB bits will be referenced to the

system clock period, rather than the OCx module's

period.

The DCB bits (OCxCON2<10:9>) provide for resolution

better than one instruction cycle. When used, they

delay the falling edge generated by a match event by a

portion of an instruction cycle.

For example, setting DCB<1:0> = 10causes the falling

edge to occur half way through the instruction cycle in

which the match event occurs, instead of at the

beginning. These bits cannot be used when

OCM<2:0> = 001. When operating the module in PWM

mode (OCM<2:0> = 110or 111), the DCB bits will be

double-buffered.

TABLE 14-1: EXAMPLE PWM FREQUENCIES AND RESOLUTIONS AT 4 MIPS (FCY = 4 MHz)⁽¹⁾

PWM Frequency

Prescaler Ratio

7.6 Hz

61 Hz

122 Hz

977 Hz

3.9 kHz

31.3 kHz

125 kHz

8

1

FFFFh

16

1

007Fh

7

1

001Fh

5

Period Value

FFFFh

16

7FFFh

15

0FFFh

12

03FFh

10

Resolution (bits)

Note 1: Based on FCY = FOSC/2; Doze mode and PLL are disabled.

TABLE 14-2: EXAMPLE PWM FREQUENCIES AND RESOLUTIONS AT 16 MIPS (FCY = 16 MHz)⁽¹⁾

PWM Frequency

Prescaler Ratio

30.5 Hz

244 Hz

488 Hz

3.9 kHz

15.6 kHz

125 kHz

500 kHz

8

1

FFFFh

16

1

007Fh

7

1

001Fh

5

Period Value

FFFFh

16

7FFFh

15

0FFFh

12

03FFh

10

Resolution (bits)

Note 1: Based on FCY = FOSC/2; Doze mode and PLL are disabled.

DS39940D-page 166

Preliminary

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REGISTER 14-1: OCxCON1: OUTPUT COMPARE x CONTROL REGISTER 1

U-0

—

U-0

—

R/W-0

ENFLT2⁽²⁾

R/W-0

OCSIDL

OCTSEL2

OCTSEL1

OCTSEL0

ENFLT1

bit 15

bit 8

R/W-0

R/W-0, HCS R/W-0, HCS R/W-0, HCS

OCFLT2 OCFLT1 OCFLT0

R/W-0

OCM2⁽¹⁾

R/W-0

OCM1⁽¹⁾

R/W-0

OCM0⁽¹⁾

ENFLT0

TRIGMODE

bit 7

bit 0

Legend:

HCS = Hardware Clearable/Settable bit

R = Readable bit

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

-n = Value at POR

bit 15-14

bit 13

Unimplemented: Read as ‘0’

OCSIDL: Stop Output Compare x in Idle Mode Control bit

1= Output compare x halts in CPU Idle mode

0= Output compare x continues to operate in CPU Idle mode

bit 12-10

OCTSEL<2:0>: Output Compare x Timer Select bits

111= System clock

110= Reserved

101= Reserved

100= Timer1

011= Timer5

010= Timer4

001= Timer3

000= Timer2

bit 9

bit 8

bit 7

bit 6

bit 5

bit 4

bit 3

ENFLT2: Comparator Fault Input Enable bit⁽²⁾

1= Comparator Fault input is enabled

0= Comparator Fault input is disabled

ENFLT1: OCFB Fault Input Enable bit

1= OCFB Fault input is enabled

0= OCFB Fault input is disabled

ENFLT0: OCFA Fault Input Enable bit

1= OCFA Fault input is enabled

0= OCFA Fault input is disabled

OCFLT2: PWM Comparator Fault Condition Status bit⁽²⁾

1= PWM comparator Fault condition has occurred (this is cleared in hardware only)

0= PWM comparator Fault condition has not occurred (this bit is used only when OCM<2:0> = 111)

OCFLT1: PWM OCFB Fault Input Enable bit

1= PWM OCFB Fault condition has occurred (this is cleared in hardware only)

0= PWM OCFB Fault condition has not occurred (this bit is used only when OCM<2:0> = 111)

OCFLT0: PWM OCFA Fault Condition Status bit

1= PWM OCFA Fault condition has occurred (this is cleared in hardware only)

0= PWM OCFA Fault condition has not occurred (this bit is used only when OCM<2:0> = 111)

TRIGMODE: Trigger Status Mode Select bit

1= TRIGSTAT (OCxCON2<6>) is cleared when OCxRS = OCxTMR or in software

0= TRIGSTAT is only cleared by software

Note 1: The OCx output must also be configured to an available RPn pin. For more information, see Section 10.4

“Peripheral Pin Select (PPS)”.

2: The comparator module used for Fault input varies with the OCx module. OC1 and OC2 use Comparator 1;

OC3 and OC4 use Comparator 2; OC5 uses Comparator 3.

 2010 Microchip Technology Inc.

Preliminary

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REGISTER 14-1: OCxCON1: OUTPUT COMPARE x CONTROL REGISTER 1 (CONTINUED)

bit 2-0

OCM<2:0>: Output Compare x Mode Select bits⁽¹⁾

111= Center-Aligned PWM mode on OCx

110= Edge-Aligned PWM mode on OCx

101= Double Compare Continuous Pulse mode: initialize OCx pin low, toggle OCx state continuously

on alternate matches of OCxR and OCxRS

100= Double Compare Single-Shot mode: initialize OCx pin low, toggle OCx state on matches of

OCxR and OCxRS for one cycle

011= Single Compare Continuous Pulse mode: compare events continuously toggle OCx pin

010= Single Compare Single-Shot mode: initialize OCx pin high, compare event forces OCx pin low

001= Single Compare Single-Shot mode: initialize OCx pin low, compare event forces OCx pin high

000= Output compare channel is disabled

Note 1: The OCx output must also be configured to an available RPn pin. For more information, see Section 10.4

“Peripheral Pin Select (PPS)”.

2: The comparator module used for Fault input varies with the OCx module. OC1 and OC2 use Comparator 1;

OC3 and OC4 use Comparator 2; OC5 uses Comparator 3.

DS39940D-page 168

Preliminary

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REGISTER 14-2: OCxCON2: OUTPUT COMPARE x CONTROL REGISTER 2

R/W-0

U-0

—

R/W-0

DCB1⁽³⁾

R/W-0

DCB0⁽³⁾

R/W-0

OC32

FLTMD

FLTOUT

FLTTRIEN

OCINV

bit 15

bit 8

R/W-0

R/W-0, HS

TRIGSTAT

R/W-0

R/W-1

R/W-0

OCTRIG

OCTRIS

SYNCSEL4 SYNCSEL3 SYNCSEL2 SYNCSEL1 SYNCSEL0

bit 0

bit 7

Legend:

HS = Hardware Settable bit

W = Writable bit

R = Readable bit

-n = Value at POR

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

‘1’ = Bit is set

bit 15

FLTMD: Fault Mode Select bit

1= Fault mode is maintained until the Fault source is removed and the corresponding OCFLT0 bit is

cleared in software

0= Fault mode is maintained until the Fault source is removed and a new PWM period starts

bit 14

bit 13

bit 12

FLTOUT: Fault Out bit

1= PWM output is driven high on a Fault

0= PWM output is driven low on a Fault

FLTTRIEN: Fault Output State Select bit

1= Pin is forced to an output on a Fault condition

0= Pin I/O condition is unaffected by a Fault

OCINV: OCMP Invert bit

1= OCx output is inverted

0= OCx output is not inverted

bit 11

Unimplemented: Read as ‘0’

bit 10-9

DCB<1:0>: OC Pulse-Width Least Significant bits⁽³⁾

11= Delay OCx falling edge by 3/4 of the instruction cycle

10= Delay OCx falling edge by 1/2 of the instruction cycle

01= Delay OCx falling edge by 1/4 of the instruction cycle

00= OCx falling edge occurs at start of the instruction cycle

bit 8

bit 7

bit 6

bit 5

OC32: Cascade Two OC Modules Enable bit (32-bit operation)

1= Cascade module operation enabled

0= Cascade module operation disabled

OCTRIG: OCx Trigger/Sync Select bit

1= Trigger OCx from source designated by SYNCSELx bits

0= Synchronize OCx with source designated by SYNCSELx bits

TRIGSTAT: Timer Trigger Status bit

1= Timer source has been triggered and is running

0= Timer source has not been triggered and is being held clear

OCTRIS: OCx Output Pin Direction Select bit

1= OCx pin is tri-stated

0= Output compare peripheral x connected to OCx pin

Note 1: Do not use an OC module as its own trigger source, either by selecting this mode or another equivalent

SYNCSEL setting.

2: Use these inputs as trigger sources only and never as sync sources.

3: These bits affect the rising edge when OCINV = 1. The bits have no effect when the

OCM bits (OCxCON1<1:0>) = 001.

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REGISTER 14-2: OCxCON2: OUTPUT COMPARE x CONTROL REGISTER 2 (CONTINUED)

bit 4-0

SYNCSEL<4:0>: Trigger/Synchronization Source Selection bits

11111= This OC module⁽¹⁾

11110= Reserved

11101= Reserved

11100= CTMU⁽²⁾

11011= A/D⁽²⁾

11010= Comparator 3⁽²⁾

11001= Comparator 2⁽²⁾

11000= Comparator 1⁽²⁾

10111= Input Capture 4⁽²⁾

10110= Input Capture 3⁽²⁾

10101= Input Capture 2⁽²⁾

10100= Input Capture 1⁽²⁾

100xx= Reserved

01111= Timer5

01110= Timer4

01101= Timer3

01100= Timer2

01011= Timer1

01010= Input Capture 5⁽²⁾

01001= Reserved

01000= Reserved

00111= Reserved

00110= Reserved

00101= Output Compare 5⁽¹⁾

00100= Output Compare 4⁽¹⁾

00011= Output Compare 3⁽¹⁾

00010= Output Compare 2⁽¹⁾

00001= Output Compare 1⁽¹⁾

00000= Not synchronized to any other module

Note 1: Do not use an OC module as its own trigger source, either by selecting this mode or another equivalent

SYNCSEL setting.

2: Use these inputs as trigger sources only and never as sync sources.

3: These bits affect the rising edge when OCINV = 1. The bits have no effect when the

OCM bits (OCxCON1<1:0>) = 001.

DS39940D-page 170

Preliminary

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The SPI serial interface consists of four pins:

15.0 SERIAL PERIPHERAL

INTERFACE (SPI)

• SDIx: Serial Data Input

• SDOx: Serial Data Output

• SCKx: Shift Clock Input or Output

Note:

This data sheet summarizes the features

of this group of PIC24F devices. It is not

• SSx: Active-Low Slave Select or Frame

Synchronization I/O Pulse

intended to be a comprehensive reference

source. For more information, refer to the

“PIC24F Family Reference Manual”,

Section 23. “Serial Peripheral Interface

(SPI)” (DS39699).

The SPI module can be configured to operate using 2,

3 or 4 pins. In the 3-pin mode, SSx is not used. In the

2-pin mode, both SDOx and SSx are not used.

Block diagrams of the module in Standard and

Enhanced modes are shown in Figure 15-1 and

Figure 15-2.

The Serial Peripheral Interface (SPI) module is a

synchronous serial interface useful for communicating

with other peripheral or microcontroller devices. These

peripheral devices may be serial EEPROMs, shift

registers, display drivers, A/D Converters, etc. The SPI

module is compatible with Motorola^®SPI and SIOP

interfaces. All devices of the PIC24FJ64GB004 family

include three SPI modules

Note:

In this section, the SPI modules are

referred to together as SPIx or separately

as SPI1, SPI2 or SPI3. Special Function

Registers will follow a similar notation. For

example, SPIxCON1 and SPIxCON2 refer

to the control registers for any of the 3 SPI

modules.

The module supports operation in two buffer modes. In

Standard mode, data is shifted through a single serial

buffer. In Enhanced Buffer mode, data is shifted

through an 8-level FIFO buffer.

Note:

Do not perform read-modify-write opera-

tions (such as bit-oriented instructions) on

the SPIxBUF register in either Standard or

Enhanced Buffer mode.

The module also supports a basic framed SPI protocol

while operating in either Master or Slave mode. A total

of four framed SPI configurations are supported.

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DS39940D-page 171

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To set up the SPI module for the Standard Master

mode of operation:

To set up the SPI module for the Standard Slave mode

of operation:

1. If using interrupts:

1. Clear the SPIxBUF register.

2. If using interrupts:

a) Clear the SPIxIF bit in the respective IFS

register.

a) Clear the SPIxIF bit in the respective IFS

register.

b) Set the SPIxIE bit in the respective IEC

register.

b) Set the SPIxIE bit in the respective IEC

register.

c) Write the SPIxIP bits in the respective IPC

register to set the interrupt priority.

c) Write the SPIxIP bits in the respective IPC

register to set the interrupt priority.

2. Write the desired settings to the SPIxCON1 and

SPIxCON2

(SPIxCON1<5>) = 1.

3. Clear the SPIROV bit (SPIxSTAT<6>).

registers

with

MSTEN

3. Write the desired settings to the SPIxCON1

and SPIxCON2 registers with MSTEN

(SPIxCON1<5>) = 0.

4. Enable SPI operation by setting the SPIEN bit

(SPIxSTAT<15>).

4. Clear the SMP bit.

5. If the CKE bit (SPIxCON1<8>) is set, then the

SSEN bit (SPIxCON1<7>) must be set to enable

the SSx pin.

5. Write the data to be transmitted to the SPIxBUF

register. Transmission (and reception) will start

as soon as data is written to the SPIxBUF

register.

6. Clear the SPIROV bit (SPIxSTAT<6>).

7. Enable SPI operation by setting the SPIEN bit

(SPIxSTAT<15>).

FIGURE 15-1:

SPIx MODULE BLOCK DIAGRAM (STANDARD MODE)

SCKx

1:1 to 1:8

Secondary

Prescaler

1:1/4/16/64

Primary

Prescaler

FCY

SSx/FSYNCx

Sync

Control

Select

Edge

Control

Clock

SPIxCON1<1:0>

SPIxCON1<4:2>

Control

Shift

SDOx

SDIx

Enable

Master Clock

bit 0

SPIxSR

Transfer

SPIxBUF

Write SPIxBUF

Read SPIxBUF

16

Internal Data Bus

DS39940D-page 172

 2010 Microchip Technology Inc.

PIC24FJ64GB004 FAMILY

To set up the SPI module for the Enhanced Buffer

Master mode of operation:

To set up the SPI module for the Enhanced Buffer

Slave mode of operation:

1. If using interrupts:

1. Clear the SPIxBUF register.

2. If using interrupts:

a) Clear the SPIxIF bit in the respective IFS

register.

a) Clear the SPIxIF bit in the respective IFS

register.

b) Set the SPIxIE bit in the respective IEC

register.

b) Set the SPIxIE bit in the respective IEC

register.

c) Write the SPIxIP bits in the respective IPC

register.

c) Write the SPIxIP bits in the respective IPC

register to set the interrupt priority.

2. Write the desired settings to the SPIxCON1 and

SPIxCON2

(SPIxCON1<5>) = 1.

3. Clear the SPIROV bit (SPIxSTAT<6>).

registers

with

MSTEN

3. Write the desired settings to the SPIxCON1 and

SPIxCON2

registers

with

MSTEN

(SPIxCON1<5>) = 0.

4. Select Enhanced Buffer mode by setting the

SPIBEN bit (SPIxCON2<0>).

4. Clear the SMP bit.

5. If the CKE bit is set, then the SSEN bit must be

set, thus enabling the SSx pin.

5. Enable SPI operation by setting the SPIEN bit

(SPIxSTAT<15>).

6. Clear the SPIROV bit (SPIxSTAT<6>).

6. Write the data to be transmitted to the SPIxBUF

register. Transmission (and reception) will start

as soon as data is written to the SPIxBUF

register.

7. Select Enhanced Buffer mode by setting the

SPIBEN bit (SPIxCON2<0>).

8. Enable SPI operation by setting the SPIEN bit

(SPIxSTAT<15>).

FIGURE 15-2:

SPIx MODULE BLOCK DIAGRAM (ENHANCED MODE)

SCKx

1:1/4/16/64

Primary

Prescaler

1:1 to 1:8

Secondary

Prescaler

FCY

SSx/FSYNCx

Sync

Control

Select

Edge

Control

Clock

SPIxCON1<1:0>

SPIxCON1<4:2>

Shift Control

SDOx

SDIx

Enable

Master Clock

bit 0

SPIxSR

Transfer

8-Level FIFO

Receive Buffer

8-Level FIFO

Transmit Buffer

SPIxBUF

Write SPIxBUF

Read SPIxBUF

16

Internal Data Bus

 2010 Microchip Technology Inc.

DS39940D-page 173

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REGISTER 15-1: SPIxSTAT: SPIx STATUS AND CONTROL REGISTER

R/W-0

SPIEN⁽¹⁾

U-0

—

R/W-0

U-0

—

U-0

—

R-0

SPISIDL

SPIBEC2

SPIBEC1

SPIBEC0

bit 15

bit 8

R-0

R/C-0, HS

SPIROV

R/W-0

R-0

SRMPT

SRXMPT

SISEL2

SISEL1

SISEL0

SPITBF

SPIRBF

bit 7

bit 0

Legend:

C = Clearable bit

W = Writable bit

‘1’ = Bit is set

HS = Hardware Settable bit

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

R = Readable bit

-n = Value at POR

bit 15

SPIEN: SPIx Enable bit⁽¹⁾

1= Enables module and configures SCKx, SDOx, SDIx and SSx as serial port pins

0= Disables module

bit 14

bit 13

Unimplemented: Read as ‘0’

SPISIDL: Stop in Idle Mode bit

1= Discontinue module operation when device enters Idle mode

0= Continue module operation in Idle mode

bit 12-11

bit 10-8

Unimplemented: Read as ‘0’

SPIBEC<2:0>: SPIx Buffer Element Count bits (valid in Enhanced Buffer mode)

Master mode:

Number of SPI transfers pending.

Slave mode:

Number of SPI transfers unread.

bit 7

bit 6

SRMPT: Shift Register (SPIxSR) Empty bit (valid in Enhanced Buffer mode)

1= SPIx Shift register is empty and ready to send or receive

0= SPIx Shift register is not empty

SPIROV: Receive Overflow Flag bit

1= A new byte/word is completely received and discarded. The user software has not read the previous

data in the SPIxBUF register.

0= No overflow has occurred

bit 5

SRXMPT: Receive FIFO Empty bit (valid in Enhanced Buffer mode)

1= Receive FIFO is empty

0= Receive FIFO is not empty

bit 4-2

SISEL<2:0>: SPIx Buffer Interrupt Mode bits (valid in Enhanced Buffer mode)

111= Interrupt when SPIx transmit buffer is full (SPITBF bit is set)

110= Interrupt when last bit is shifted into SPIxSR; as a result, the TX FIFO is empty

101= Interrupt when the last bit is shifted out of SPIxSR; now the transmit is complete

100= Interrupt when one data is shifted into the SPIxSR; as a result, the TX FIFO has one open spot

011= Interrupt when SPIx receive buffer is full (SPIRBF bit is set)

010= Interrupt when SPIx receive buffer is 3/4 or more full

001= Interrupt when data is available in receive buffer (SRMPT bit is set)

000= Interrupt when the last data in the receive buffer is read; as a result, the buffer is empty

(SRXMPT bit set)

Note 1: If SPIEN = 1, these functions must be assigned to available RPn pins before use. See Section 10.4

“Peripheral Pin Select (PPS)” for more information.

DS39940D-page 174

 2010 Microchip Technology Inc.

PIC24FJ64GB004 FAMILY

REGISTER 15-1: SPIxSTAT: SPIx STATUS AND CONTROL REGISTER (CONTINUED)

bit 1

SPITBF: SPIx Transmit Buffer Full Status bit

1= Transmit not yet started; SPIxTXB is full

0= Transmit started; SPIxTXB is empty

In Standard Buffer mode:

Automatically set in hardware when CPU writes SPIxBUF location, loading SPIxTXB. Automatically

cleared in hardware when SPIx module transfers data from SPIxTXB to SPIxSR.

In Enhanced Buffer mode:

Automatically set in hardware when CPU writes SPIxBUF location, loading the last available buffer location.

Automatically cleared in hardware when a buffer location is available for a CPU write.

bit 0

SPIRBF: SPIx Receive Buffer Full Status bit

1= Receive complete, SPIxRXB is full

0= Receive is not complete, SPIxRXB is empty

In Standard Buffer mode:

Automatically set in hardware when SPIx transfers data from SPIxSR to SPIxRXB. Automatically

cleared in hardware when core reads SPIxBUF location, reading SPIxRXB.

In Enhanced Buffer mode:

Automatically set in hardware when SPIx transfers data from SPIxSR to buffer, filling the last unread

buffer location. Automatically cleared in hardware when a buffer location is available for a transfer from

SPIxSR.

Note 1: If SPIEN = 1, these functions must be assigned to available RPn pins before use. See Section 10.4

“Peripheral Pin Select (PPS)” for more information.

 2010 Microchip Technology Inc.

DS39940D-page 175

PIC24FJ64GB004 FAMILY

REGISTER 15-2: SPIXCON1: SPIx CONTROL REGISTER 1

U-0

—

U-0

—

U-0

—

R/W-0

DISSCK⁽¹⁾

R/W-0

DISSDO⁽²⁾

R/W-0

SMP

R/W-0

CKE⁽³⁾

MODE16

bit 15

bit 8

R/W-0

SSEN⁽⁴⁾

R/W-0

CKP

R/W-0

MSTEN

SPRE2

SPRE1

SPRE0

PPRE1

PPRE0

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15-13

bit 12

Unimplemented: Read as ‘0’

DISSCK: Disable SCKx pin bit (SPI Master modes only)⁽¹⁾

1= Internal SPI clock is disabled; pin functions as I/O

0= Internal SPI clock is enabled

bit 11

bit 10

bit 9

DISSDO: Disable SDOx pin bit⁽²⁾

1= SDOx pin is not used by module; pin functions as I/O

0= SDOx pin is controlled by the module

MODE16: Word/Byte Communication Select bit

1= Communication is word-wide (16 bits)

0= Communication is byte-wide (8 bits)

SMP: SPIx Data Input Sample Phase bit

Master mode:

1= Input data sampled at end of data output time

0= Input data sampled at middle of data output time

Slave mode:

SMP must be cleared when SPIx is used in Slave mode.

bit 8

bit 7

bit 6

bit 5

CKE: SPIx Clock Edge Select bit⁽³⁾

1= Serial output data changes on transition from active clock state to Idle clock state (see bit 6)

0= Serial output data changes on transition from Idle clock state to active clock state (see bit 6)

SSEN: Slave Select Enable (Slave mode) bit⁽⁴⁾

1= SSx pin used for Slave mode

0= SSx pin not used by module; pin controlled by port function

CKP: Clock Polarity Select bit

1= Idle state for clock is a high level; active state is a low level

0= Idle state for clock is a low level; active state is a high level

MSTEN: Master Mode Enable bit

1= Master mode

0= Slave mode

Note 1: If DISSCK = 0, SCKx must be configured to an available RPn pin. See Section 10.4 “Peripheral Pin

Select (PPS)” for more information.

2: If DISSDO = 0, SDOx must be configured to an available RPn pin. See Section 10.4 “Peripheral Pin

Select (PPS)” for more information.

3: The CKE bit is not used in the Framed SPI modes. The user should program this bit to ‘0’ for the Framed

SPI modes (FRMEN = 1).

4: If SSEN = 1, SSx must be configured to an available RPn pin. See Section 10.4 “Peripheral Pin Select

(PPS)” for more information.

DS39940D-page 176

 2010 Microchip Technology Inc.

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REGISTER 15-2: SPIXCON1: SPIx CONTROL REGISTER 1 (CONTINUED)

bit 4-2

SPRE<2:0>: Secondary Prescale bits (Master mode)

111= Secondary prescale 1:1

110= Secondary prescale 2:1

...

000= Secondary prescale 8:1

bit 1-0

PPRE<1:0>: Primary Prescale bits (Master mode)

11= Primary prescale 1:1

10= Primary prescale 4:1

01= Primary prescale 16:1

00= Primary prescale 64:1

Note 1: If DISSCK = 0, SCKx must be configured to an available RPn pin. See Section 10.4 “Peripheral Pin

Select (PPS)” for more information.

2: If DISSDO = 0, SDOx must be configured to an available RPn pin. See Section 10.4 “Peripheral Pin

Select (PPS)” for more information.

3: The CKE bit is not used in the Framed SPI modes. The user should program this bit to ‘0’ for the Framed

SPI modes (FRMEN = 1).

4: If SSEN = 1, SSx must be configured to an available RPn pin. See Section 10.4 “Peripheral Pin Select

(PPS)” for more information.

REGISTER 15-3: SPIxCON2: SPIx CONTROL REGISTER 2

R/W-0

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

FRMEN

SPIFSD

SPIFPOL

bit 15

bit 8

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

R/W-0

SPIFE

R/W-0

SPIBEN

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

-n = Value at POR

bit 15

bit 14

bit 13

FRMEN: Framed SPIx Support bit

1= Framed SPIx support enabled

0= Framed SPIx support disabled

SPIFSD: Frame Sync Pulse Direction Control on SSx Pin bit

1= Frame sync pulse input (slave)

0= Frame sync pulse output (master)

SPIFPOL: Frame Sync Pulse Polarity bit (Frame mode only)

1= Frame sync pulse is active-high

0= Frame sync pulse is active-low

bit 12-2

bit 1

Unimplemented: Read as ‘0’

SPIFE: Frame Sync Pulse Edge Select bit

1= Frame sync pulse coincides with first bit clock

0= Frame sync pulse precedes first bit clock

bit 0

SPIBEN: Enhanced Buffer Enable bit

1= Enhanced buffer enabled

0= Enhanced buffer disabled (Legacy mode)

 2010 Microchip Technology Inc.

DS39940D-page 177

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FIGURE 15-3:

SPI MASTER/SLAVE CONNECTION (STANDARD MODE)

PROCESSOR 1 (SPI Master)

PROCESSOR 2 (SPI Slave)

SDOx

SDIx

Serial Receive Buffer

(SPIxRXB)

Serial Receive Buffer

(SPIxRXB)

SDIx

SDOx

Shift Register

(SPIxSR)

Shift Register

(SPIxSR)

LSb

MSb

LSb

Serial Transmit Buffer

(SPIxTXB)

Serial Clock

SCKx

SSx⁽¹⁾

SCKx

SPIx Buffer

(SPIxBUF)⁽²⁾

SSEN (SPIxCON1<7>) = 1and MSTEN (SPIxCON1<5>) = 0

MSTEN (SPIxCON1<5>) = 1)

Note 1: Using the SSx pin in Slave mode of operation is optional.

2: User must write transmit data to read received data from SPIxBUF. The SPIxTXB and SPIxRXB registers are memory

mapped to SPIxBUF.

FIGURE 15-4:

SPI MASTER/SLAVE CONNECTION (ENHANCED BUFFER MODES)

PROCESSOR 1 (SPI Enhanced Buffer Master)

PROCESSOR 2 (SPI Enhanced Buffer Slave)

SDOx

SDIx

SDOx

Shift Register

(SPIxSR)

Shift Register

(SPIxSR)

LSb

MSb

LSb

8-Level FIFO Buffer

Serial Clock

SPIx Buffer

SCKx

SSx

SCKx

SSx⁽¹⁾

(SPIxBUF)⁽²⁾

MSTEN (SPIxCON1<5>) = 1and

SPIBEN (SPIxCON2<0>) = 1

SSEN (SPIxCON1<7>) = 1,

MSTEN (SPIxCON1<5>) = 0and

SPIBEN (SPIxCON2<0>) = 1

Note 1: Using the SSx pin in Slave mode of operation is optional.

2: User must write transmit data to read received data from SPIxBUF. The SPIxTXB and SPIxRXB registers are memory

mapped to SPIxBUF.

DS39940D-page 178

 2010 Microchip Technology Inc.

PIC24FJ64GB004 FAMILY

FIGURE 15-5:

FIGURE 15-6:

FIGURE 15-7:

FIGURE 15-8:

SPI MASTER, FRAME MASTER CONNECTION DIAGRAM

PIC24F

PROCESSOR 2

(SPI Master, Frame Master)

SDOx

SDIx

SDOx

Serial Clock

SCKx

SSx

SCKx

SSx

Frame Sync

Pulse

SPI MASTER, FRAME SLAVE CONNECTION DIAGRAM

PIC24F

PROCESSOR 2

SPI Master, Frame Slave)

SDOx

SDIx

SDOx

Serial Clock

SCKx

SSx

SCKx

SSx

Frame Sync

Pulse

SPI SLAVE, FRAME MASTER CONNECTION DIAGRAM

PIC24F

PROCESSOR 2

(SPI Slave, Frame Master)

SDOx

SDIx

SDOx

Serial Clock

SCKx

SSx

SCKx

SSx

Frame Sync.

Pulse

SPI SLAVE, FRAME SLAVE CONNECTION DIAGRAM

PIC24F

PROCESSOR 2

(SPI Slave, Frame Slave)

SDOx

SDIx

SDOx

Serial Clock

SCKx

SSx

SCKx

SSx

Frame Sync

Pulse

 2010 Microchip Technology Inc.

DS39940D-page 179

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EQUATION 15-1: RELATIONSHIP BETWEEN DEVICE AND SPI CLOCK SPEED⁽¹⁾

FCY

FSCK =

Primary Prescaler * Secondary Prescaler

Note 1: Based on FCY = FOSC/2; Doze mode and PLL are disabled.

TABLE 15-1: SAMPLE SCK FREQUENCIES^(1,2)

Secondary Prescaler Settings

FCY = 16 MHz

1:1

2:1

4:1

6:1

8:1

Primary Prescaler Settings

1:1

4:1

Invalid

4000

1000

250

8000

2000

500

4000

1000

250

63

2667

667

167

42

2000

500

125

31

16:1

64:1

125

FCY = 5 MHz

Primary Prescaler Settings

1:1

4:1

5000

1250

313

78

2500

625

156

39

1250

313

78

833

208

52

625

156

39

16:1

64:1

20

13

10

Note 1: Based on FCY = FOSC/2, Doze mode and PLL are disabled.

2: SCKx frequencies shown in kHz.

DS39940D-page 180

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16.1 Communicating as a Master in a

Single Master Environment

16.0 INTER-INTEGRATED CIRCUIT

2

(I C™)

The details of sending a message in Master mode

Note:

This data sheet summarizes the features

depends on the communications protocol for the device

being communicated with. Typically, the sequence of

events is as follows:

of this group of PIC24F devices. It is not

intended to be a comprehensive reference

source. For more information, refer to the

“PIC24F Family Reference Manual”,

Section 24. “Inter-Integrated Circuit™

(I²C™)” (DS39702).

1. Assert a Start condition on SDAx and SCLx.

2. Send the I²C device address byte to the slave

with a write indication.

The Inter-Integrated Circuit (I²C) module is a serial

interface useful for communicating with other peripheral

or microcontroller devices. These peripheral devices

may be serial EEPROMs, display drivers, A/D

Converters, etc.

3. Wait for and verify an Acknowledge from the

slave.

4. Send the first data byte (sometimes known as

the command) to the slave.

5. Wait for and verify an Acknowledge from the

slave.

The I²C module supports these features:

6. Send the serial memory address low byte to the

slave.

• Independent master and slave logic

• 7-bit and 10-bit device addresses

• General call address as defined in the I²C protocol

7. Repeat steps 4 and 5 until all data bytes are

sent.

• Clock stretching to provide delays for the

processor to respond to a slave data request

8. Assert a Repeated Start condition on SDAx and

SCLx.

• Both 100 kHz and 400 kHz bus specifications.

• Configurable address masking

9. Send the device address byte to the slave with

a read indication.

• Multi-Master modes to prevent loss of messages

in arbitration

10. Wait for and verify an Acknowledge from the

slave.

• Bus Repeater mode, allowing the acceptance of

all messages as a slave regardless of the address

11. Enable master reception to receive serial

memory data.

• Automatic SCL

12. Generate an ACK or NACK condition at the end

of a received byte of data.

A block diagram of the module is shown in Figure 16-1.

13. Generate a Stop condition on SDAx and SCLx.

 2010 Microchip Technology Inc.

DS39940D-page 181

PIC24FJ64GB004 FAMILY

FIGURE 16-1:

I²C™ BLOCK DIAGRAM

Internal

Data Bus

I2CxRCV

Read

Shift

Clock

SCLx

SDAx

I2CxRSR

LSB

Address Match

Write

Read

Match Detect

I2CxMSK

Write

Read

I2CxADD

Start and Stop

Bit Detect

Write

Start and Stop

Bit Generation

I2CxSTAT

I2CxCON

Read

Write

Collision

Detect

Acknowledge

Generation

Read

Clock

Stretching

Write

Read

I2CxTRN

LSB

Shift Clock

Reload

Control

Write

Read

BRG Down Counter

TCY/2

I2CxBRG

DS39940D-page 182

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16.2 Setting Baud Rate When

Operating as a Bus Master

16.3 Slave Address Masking

The I2CxMSK register (Register 16-3) designates

address bit positions as “don’t care” for both 7-Bit and

10-Bit Addressing modes. Setting a particular bit

location (= 1) in the I2CxMSK register causes the slave

module to respond whether the corresponding address

bit value is a ‘0’ or a ‘1’. For example, when I2CxMSK

is set to ‘00100000’, the slave module will detect both

addresses: ‘0000000’ and ‘0100000’.

To compute the Baud Rate Generator (BRG) reload

value, use Equation 16-1.

EQUATION 16-1: COMPUTING BAUD RATE

RELOAD VALUE^(1,2)

FCY

FSCL = ---------------------------------------------------------------------

FCY

I2CxBRG + 1 + -----------------------------

10 000 000

To enable address masking, the IPMI (Intelligent

Peripheral Management Interface) must be disabled by

clearing the IPMIEN bit (I2CxCON<11>).

or

FCY





I2CxBRG = ----------- – ----------------------------- – 1





FSCL 10 000 000

As a result of changes in the I²C™ proto-

col, the addresses in Table 16-2 are

reserved and will not be Acknowledged in

Slave mode. This includes any address

mask settings that include any of these

addresses.

Note 1: Based on FCY = FOSC/2, Doze mode and

PLL are disabled.

Note:

2: These clock rate values are for guidance

only. The actual clock rate can be affected

by various system level parameters. The

actual clock rate should be measured in

its intended application.

TABLE 16-1: I²C™ CLOCK RATES^(1,2)

I2CxBRG Value

Required System FSCL

FCY

Actual FSCL

(Decimal)

(Hexadecimal)

9D

100 kHz

400 kHz

1 MHz

16 MHz

8 MHz

4 MHz

16 MHz

8 MHz

4 MHz

2 MHz

16 MHz

8 MHz

4 MHz

157

78

39

37

18

9

100 kHz

99 kHz

4E

27

25

12

9

404 kHz

385 kHz

1.026 MHz

0.909 MHz

4

13

6

D

1 MHz

6

1 MHz

3

Note 1: Based on FCY = FOSC/2, Doze mode and PLL are disabled.

2: These clock rate values are for guidance only. The actual clock rate can be affected by various system

level parameters. The actual clock rate should be measured in its intended application.

TABLE 16-2: I²C™ RESERVED ADDRESSES⁽¹⁾

Slave Address R/W Bit

Description

0000 000

0000 001

0000 010

0000 011

0000 1xx

1111 1xx

1111 0xx

0

1

x

General Call Address⁽²⁾

Start Byte

Cbus Address

Reserved

HS Mode Master Code

Reserved

10-Bit Slave Upper Byte⁽³⁾

Note 1: The address bits listed here will never cause an address match, independent of address mask settings.

2: The address will be Acknowledged only if GCEN = 1.

3: A match on this address can only occur on the upper byte in 10-Bit Addressing mode.

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DS39940D-page 183

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REGISTER 16-1: I2CxCON: I2Cx CONTROL REGISTER

R/W-0

I2CEN

U-0

—

R/W-0

R/W-1, HC

SCLREL

R/W-0

A10M

R/W-0

SMEN

I2CSIDL

IPMIEN

DISSLW

bit 15

bit 8

R/W-0

GCEN

R/W-0

R/W-0, HC

ACKEN

R/W-0, HC

RCEN

R/W-0, HC

PEN

R/W-0, HC

RSEN

R/W-0, HC

SEN

STREN

ACKDT

bit 7

bit 0

Legend:

HC = Hardware Clearable bit

W = Writable bit

R = Readable bit

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

-n = Value at POR

‘1’ = Bit is set

bit 15

I2CEN: I2Cx Enable bit

1= Enables the I2Cx module and configures the SDAx and SCLx pins as serial port pins

0= Disables the I2Cx module. All I²C pins are controlled by port functions.

bit 14

bit 13

Unimplemented: Read as ‘0’

I2CSIDL: Stop in Idle Mode bit

1= Discontinues module operation when device enters an Idle mode

0= Continues module operation in Idle mode

bit 12

SCLREL: SCLx Release Control bit (when operating as I²C Slave)

1= Releases SCLx clock

0= Holds SCLx clock low (clock stretch)

If STREN = 1:

Bit is R/W (i.e., software may write ‘0’ to initiate stretch and write ‘1’ to release clock). Hardware clear

at beginning of slave transmission. Hardware clear at end of slave reception.

If STREN = 0:

Bit is R/S (i.e., software may only write ‘1’ to release clock). Hardware clear at beginning of slave

transmission.

bit 11

bit 10

bit 9

IPMIEN: Intelligent Platform Management Interface (IPMI) Enable bit

1= IPMI Support mode is enabled; all addresses Acknowledged

0= IPMI mode disabled

A10M: 10-Bit Slave Addressing bit

1= I2CxADD is a 10-bit slave address

0= I2CxADD is a 7-bit slave address

DISSLW: Disable Slew Rate Control bit

1= Slew rate control disabled

0= Slew rate control enabled

bit 8

SMEN: SMBus Input Levels bit

1= Enables I/O pin thresholds compliant with SMBus specification

0= Disables SMBus input thresholds

bit 7

GCEN: General Call Enable bit (when operating as I²C slave)

1= Enables interrupt when a general call address is received in the I2CxRSR

(module is enabled for reception)

0= General call address disabled

bit 6

STREN: SCLx Clock Stretch Enable bit (when operating as I²C slave)

Used in conjunction with the SCLREL bit.

1= Enables software or receive clock stretching

0= Disables software or receive clock stretching

DS39940D-page 184

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REGISTER 16-1: I2CxCON: I2Cx CONTROL REGISTER (CONTINUED)

bit 5

ACKDT: Acknowledge Data bit (When operating as I²C master. Applicable during master receive.)

Value that will be transmitted when the software initiates an Acknowledge sequence.

1= Sends NACK during Acknowledge

0= Sends ACK during Acknowledge

bit 4

ACKEN: Acknowledge Sequence Enable bit

(When operating as I²C master. Applicable during master receive.)

1= Initiates Acknowledge sequence on SDAx and SCLx pins and transmits ACKDT data bit. Hardware

clear at end of master Acknowledge sequence.

0= Acknowledge sequence not in progress

bit 3

bit 2

bit 1

RCEN: Receive Enable bit (when operating as I²C master)

1= Enables Receive mode for I²C. Hardware clear at end of eighth bit of master receive data byte.

0= Receives sequence not in progress

PEN: Stop Condition Enable bit (when operating as I²C master)

1= Initiates Stop condition on SDAx and SCLx pins. Hardware clear at end of master Stop sequence.

0= Stop condition not in progress

RSEN: Repeated Start Condition Enabled bit (when operating as I²C master)

1= Initiates Repeated Start condition on SDAx and SCLx pins. Hardware clear at end of master

Repeated Start sequence

0= Repeated Start condition not in progress

bit 0

SEN: Start Condition Enabled bit (when operating as I²C master)

1= Initiates Start condition on SDAx and SCLx pins. Hardware clear at end of master Start sequence.

0= Start condition not in progress

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DS39940D-page 185

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REGISTER 16-2: I2CxSTAT: I2Cx STATUS REGISTER

R-0, HSC R-0, HSC

ACKSTAT TRSTAT

bit 15

U-0

—

U-0

—

U-0

—

R/C-0, HS

BCL

R-0, HSC

GCSTAT

R-0, HSC

ADD10

bit 8

bit 0

R/C-0, HS R/C-0, HS R-0, HSC R/C-0, HSC R/C-0, HSC

R-0, HSC

R/W

R-0, HSC

RBF

R-0, HSC

TBF

IWCOL

bit 7

I2COV

D/A

P

S

Legend:

C = Clearable bit

W = Writable bit

‘1’ = Bit is set

HS = Hardware Settable bit

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

HSC = Hardware Settable/Clearable bit

R = Readable bit

-n = Value at POR

bit 15

ACKSTAT: Acknowledge Status bit

1= NACK was detected last

0= ACK was detected last

Hardware set or clear at the end of Acknowledge.

bit 14

TRSTAT: Transmit Status bit

(When operating as I²C master. Applicable to master transmit operation.)

1= Master transmit is in progress (8 bits + ACK)

0= Master transmit is not in progress

Hardware set at the beginning of master transmission. Hardware clear at the end of slave Acknowledge.

bit 13-11 Unimplemented: Read as ‘0’

bit 10

bit 9

bit 8

bit 7

bit 6

bit 5

BCL: Master Bus Collision Detect bit

1= A bus collision has been detected during a master operation

0= No collision

Hardware set at detection of bus collision.

GCSTAT: General Call Status bit

1= General call address was received

0= General call address was not received

Hardware set when address matches the general call address. Hardware clear at the Stop detection.

ADD10: 10-Bit Address Status bit

1= 10-bit address was matched

0= 10-bit address was not matched

Hardware set at the match of the 2nd byte of matched 10-bit address. Hardware clear at the Stop detection.

IWCOL: Write Collision Detect bit

1= An attempt to write to the I2CxTRN register failed because the I²C module is busy

0= No collision

Hardware set at occurrence of write to I2CxTRN while busy (cleared by software).

I2COV: Receive Overflow Flag bit

1= A byte was received while the I2CxRCV register was still holding the previous byte

0= No overflow

Hardware set at attempt to transfer I2CxRSR to I2CxRCV (cleared by software).

D/A: Data/Address bit (when operating as I²C slave)

1= Indicates that the last byte received was data

0= Indicates that the last byte received was the device address

Hardware clear occurs at device address match. Hardware set after a transmission finishes or at reception

of the slave byte.

DS39940D-page 186

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REGISTER 16-2: I2CxSTAT: I2Cx STATUS REGISTER (CONTINUED)

bit 4

bit 3

bit 2

bit 1

bit 0

P: Stop bit

1= Indicates that a Stop bit has been detected last

0= Stop bit was not detected last

Hardware set or clear when Start, Repeated Start or Stop is detected.

S: Start bit

1= Indicates that a Start (or Repeated Start) bit has been detected last

0= Start bit was not detected last

Hardware set or clear when Start, Repeated Start or Stop is detected.

R/W: Read/Write Information bit (when operating as I²C slave)

1= Read – indicates data transfer is output from slave

0= Write – indicates data transfer is input to slave

Hardware set or clear after reception of I²C device address byte.

RBF: Receive Buffer Full Status bit

1= Receive complete, I2CxRCV is full

0= Receive not complete, I2CxRCV is empty

Hardware set when I2CxRCV is written with received byte. Hardware clear when software reads I2CxRCV.

TBF: Transmit Buffer Full Status bit

1= Transmit in progress, I2CxTRN is full

0= Transmit complete, I2CxTRN is empty

Hardware set when software writes I2CxTRN. Hardware clear at completion of data transmission.

 2010 Microchip Technology Inc.

DS39940D-page 187

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REGISTER 16-3: I2CxMSK: I2Cx SLAVE MODE ADDRESS MASK REGISTER

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

R/W-0

AMSK9

AMSK8

bit 15

bit 8

R/W-0

AMSK7

AMSK6

AMSK5

AMSK4

AMSK3

AMSK2

AMSK1

AMSK0

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

-n = Value at POR

bit 15-10

bit 9-0

Unimplemented: Read as ‘0’

AMSK<9:0>: Mask for Address Bit x Select bits

1= Enable masking for bit x of incoming message address; bit match not required in this position

0= Disable masking for bit x; bit match required in this position

DS39940D-page 188

 2010 Microchip Technology Inc.

PIC24FJ64GB004 FAMILY

• Fully Integrated Baud Rate Generator with 16-Bit

Prescaler

17.0 UNIVERSAL ASYNCHRONOUS

RECEIVER TRANSMITTER

(UART)

• Baud Rates Ranging from 1 Mbps to 15 bps at

16 MIPS

• 4-Deep, First-In-First-Out (FIFO) Transmit Data

Buffer

Note:

This data sheet summarizes the features

of this group of PIC24F devices. It is not

intended to be a comprehensive reference

source. For more information, refer to the

“PIC24F Family Reference Manual”,

Section 21. “UART” (DS39708).

• 4-Deep FIFO Receive Data Buffer

• Parity, Framing and Buffer Overrun Error Detection

• Support for 9-Bit mode with Address Detect

(9th bit = 1)

• Transmit and Receive Interrupts

The Universal Asynchronous Receiver Transmitter

(UART) module is one of the serial I/O modules available

in the PIC24F device family. The UART is a full-duplex,

asynchronous system that can communicate with

peripheral devices, such as personal computers,

LIN/J2602, RS-232 and RS-485 interfaces. The module

also supports a hardware flow control option with the

UxCTS and UxRTS pins, and also includes an IrDA^®

encoder and decoder.

• Loopback mode for Diagnostic Support

• Support for Sync and Break Characters

• Supports Automatic Baud Rate Detection

• IrDA Encoder and Decoder Logic

• 16x Baud Clock Output for IrDA Support

A simplified block diagram of the UART is shown in

Figure 17-1. The UART module consists of these key

important hardware elements:

The primary features of the UART module are:

• Baud Rate Generator

• Full-Duplex, 8 or 9-Bit Data Transmission through

the UxTX and UxRX pins

• Asynchronous Transmitter

• Asynchronous Receiver

• Even, Odd or No Parity Options (for 8-bit data)

• One or Two Stop bits

• Hardware Flow Control Option with UxCTS and

UxRTS pins

FIGURE 17-1:

UART SIMPLIFIED BLOCK DIAGRAM

Baud Rate Generator

IrDA^®

UxRTS/BCLKx

UxCTS

Hardware Flow Control

UARTx Receiver

UxRX

UxTX

UARTx Transmitter

Note:

The UART inputs and outputs must all be assigned to available RPn pins before use. Please see

Section 10.4 “Peripheral Pin Select (PPS)” for more information.

 2010 Microchip Technology Inc.

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The maximum baud rate (BRGH = 0) possible is

FCY/16 (for UxBRG = 0) and the minimum baud rate

17.1 UART Baud Rate Generator (BRG)

The UART module includes a dedicated 16-bit Baud

Rate Generator. The UxBRG register controls the

period of a free-running, 16-bit timer. Equation 17-1

shows the formula for computation of the baud rate

with BRGH = 0.

possible is FCY/(16 * 65536).

Equation 17-2 shows the formula for computation of

the baud rate with BRGH = 1.

EQUATION 17-2: UART BAUD RATE WITH

BRGH = 1^(1,2)

EQUATION 17-1: UART BAUD RATE WITH

BRGH = 0^(1,2)

FCY

Baud Rate =

4 • (UxBRG + 1)

FCY

Baud Rate =

16 • (UxBRG + 1)

FCY

– 1

UxBRG =

4 • Baud Rate

FCY

16 • Baud Rate

– 1

UxBRG =

Note 1: FCY denotes the instruction cycle clock

frequency.

Note 1: FCY denotes the instruction cycle clock

frequency (FOSC/2).

2: Based on FCY = FOSC/2, Doze mode

and PLL are disabled.

2: Based on FCY = FOSC/2, Doze mode

and PLL are disabled.

The maximum baud rate (BRGH = 1) possible is FCY/4

(for UxBRG = 0) and the minimum baud rate possible

is FCY/(4 * 65536).

Example 17-1 shows the calculation of the baud rate

error for the following conditions:

Writing a new value to the UxBRG register causes the

BRG timer to be reset (cleared). This ensures the BRG

does not wait for a timer overflow before generating the

new baud rate.

• FCY = 4 MHz

• Desired Baud Rate = 9600

EXAMPLE 17-1:

BAUD RATE ERROR CALCULATION (BRGH = 0)⁽¹⁾

Desired Baud Rate = FCY/(16 (UxBRG + 1))

Solving for UxBRG Value:

UxBRG

= ((FCY/Desired Baud Rate)/16) – 1

= ((4000000/9600)/16) – 1

= 25

Calculated Baud Rate = 4000000/(16 (25 + 1))

= 9615

Error

= (Calculated Baud Rate – Desired Baud Rate)

Desired Baud Rate

= (9615 – 9600)/9600

= 0.16%

Note 1: Based on FCY = FOSC/2, Doze mode and PLL are disabled.

DS39940D-page 190

 2010 Microchip Technology Inc.

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17.2 Transmitting in 8-Bit Data Mode

17.5 Receiving in 8-Bit or 9-Bit Data

Mode

1. Set up the UART:

a) Write appropriate values for data, parity and

Stop bits.

1. Set up the UART (as described in Section 17.2

“Transmitting in 8-Bit Data Mode”).

b) Write appropriate baud rate value to the

UxBRG register.

2. Enable the UART.

3. A receive interrupt will be generated when one

or more data characters have been received as

per interrupt control bit, URXISELx.

c) Set up transmit and receive interrupt enable

and priority bits.

2. Enable the UART.

4. Read the OERR bit to determine if an overrun

error has occurred. The OERR bit must be reset

in software.

3. Set the UTXEN bit (causes a transmit interrupt

two cycles after being set).

5. Read UxRXREG.

4. Write data byte to the lower byte of UxTXREG

word. The value will be immediately transferred

to the Transmit Shift Register (TSR) and the

serial bit stream will start shifting out with the

next rising edge of the baud clock.

The act of reading the UxRXREG character will move

the next character to the top of the receive FIFO,

including a new set of PERR and FERR values.

5. Alternately, the data byte may be transferred

while UTXEN = 0 and then the user may set

UTXEN. This will cause the serial bit stream to

begin immediately because the baud clock will

start from a cleared state.

17.6 Operation of UxCTS and UxRTS

Control Pins

UARTx Clear to Send (UxCTS) and Request to Send

(UxRTS) are the two hardware-controlled pins that are

associated with the UART module. These two pins

allow the UART to operate in Simplex and Flow Control

modes. They are implemented to control the transmis-

sion and reception between the Data Terminal

Equipment (DTE). The UEN<1:0> bits in the UxMODE

register configure these pins.

6. A transmit interrupt will be generated as per

interrupt control bit, UTXISELx.

17.3 Transmitting in 9-Bit Data Mode

1. Set up the UART (as described in Section 17.2

“Transmitting in 8-Bit Data Mode”).

2. Enable the UART.

17.7 Infrared Support

3. Set the UTXEN bit (causes a transmit interrupt).

4. Write UxTXREG as a 16-bit value only.

The UART module provides two types of infrared UART

support: one is the IrDA clock output to support the

external IrDA encoder and decoder device (legacy

module support), and the other is the full implementa-

tion of the IrDA encoder and decoder. Note that

because the IrDA modes require a 16x baud clock, they

will only work when the BRGH bit (UxMODE<3>) is ‘0’.

5. A word write to UxTXREG triggers the transfer

of the 9-bit data to the TSR. The serial bit stream

will start shifting out with the first rising edge of

the baud clock.

6. A transmit interrupt will be generated as per the

setting of control bit, UTXISELx.

17.7.1

IRDA CLOCK OUTPUT FOR

EXTERNAL IRDA SUPPORT

17.4 Break and Sync Transmit

Sequence

To support external IrDA encoder and decoder devices,

the BCLKx pin (same as the UxRTS pin) can be

configured to generate the 16x baud clock. When

UEN<1:0> = 11, the BCLKx pin will output the 16x

baud clock if the UART module is enabled. It can be

used to support the IrDA codec chip.

The following sequence will send a message frame

header made up of a Break, followed by an Auto-Baud

Sync byte.

1. Configure the UART for the desired mode.

2. Set UTXEN and UTXBRK to set up the Break

character.

17.7.2

BUILT-IN IRDA ENCODER AND

DECODER

3. Load the UxTXREG with a dummy character to

initiate transmission (value is ignored).

The UART has full implementation of the IrDA encoder

and decoder as part of the UART module. The built-in

IrDA encoder and decoder functionality is enabled

using the IREN bit (UxMODE<12>). When enabled

(IREN = 1), the receive pin (UxRX) acts as the input

from the infrared receiver. The transmit pin (UxTX) acts

as the output to the infrared transmitter.

4. Write ‘55h’ to UxTXREG; this loads the Sync

character into the transmit FIFO.

5. After the Break has been sent, the UTXBRK bit

is reset by hardware. The Sync character now

transmits.

 2010 Microchip Technology Inc.

DS39940D-page 191

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REGISTER 17-1: UxMODE: UARTx MODE REGISTER

R/W-0

UARTEN⁽¹⁾

bit 15

U-0

—

R/W-0

USIDL

R/W-0

IREN⁽²⁾

R/W-0

U-0

—

R/W-0

UEN1

R/W-0

UEN0

RTSMD

bit 8

R/W-0, HC

WAKE

R/W-0

R/W-0, HC

ABAUD

R/W-0

RXINV

R/W-0

BRGH

R/W-0

LPBACK

PDSEL1

PDSEL0

STSEL

bit 7

bit 0

Legend:

HC = Hardware Clearable bit

W = Writable bit

R = Readable bit

-n = Value at POR

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

‘1’ = Bit is set

bit 15

UARTEN: UARTx Enable bit⁽¹⁾

1= UARTx is enabled; all UARTx pins are controlled by UARTx as defined by UEN<1:0>

0= UARTx is disabled; all UARTx pins are controlled by port latches; UARTx power consumption is minimal

bit 14

bit 13

Unimplemented: Read as ‘0’

USIDL: Stop in Idle Mode bit

1= Discontinue module operation when the device enters Idle mode

0= Continue module operation in Idle mode

bit 12

bit 11

IREN: IrDA^®Encoder and Decoder Enable bit⁽²⁾

1= IrDA encoder and decoder enabled

0= IrDA encoder and decoder disabled

RTSMD: Mode Selection for UxRTS Pin bit

1= UxRTS pin in Simplex mode

0= UxRTS pin in Flow Control mode

bit 10

Unimplemented: Read as ‘0’

UEN<1:0>: UARTx Enable bits

bit 9-8

11= UxTX, UxRX and BCLKx pins are enabled and used; UxCTS pin controlled by port latches

10= UxTX, UxRX, UxCTS and UxRTS pins are enabled and used

01= UxTX, UxRX and UxRTS pins are enabled and used; UxCTS pin controlled by port latches

00= UxTX and UxRX pins are enabled and used; UxCTS and UxRTS/BCLKx pins controlled by port

latches

bit 7

WAKE: Wake-up on Start Bit Detect During Sleep Mode Enable bit

1= UARTx will continue to sample the UxRX pin; interrupt generated on falling edge; bit cleared in

hardware on following rising edge

0= No wake-up enabled

bit 6

bit 5

LPBACK: UARTx Loopback Mode Select bit

1= Enable Loopback mode

0= Loopback mode is disabled

ABAUD: Auto-Baud Enable bit

1= Enable baud rate measurement on the next character – requires reception of a Sync field (55h);

cleared in hardware upon completion

0= Baud rate measurement disabled or completed

bit 4

RXINV: Receive Polarity Inversion bit

1= UxRX Idle state is ‘0’

0= UxRX Idle state is ‘1’

Note 1: If UARTEN = 1, the peripheral inputs and outputs must be configured to an available RPn pin. See

Section 10.4 “Peripheral Pin Select (PPS)” for more information.

2: This feature is only available for the 16x BRG mode (BRGH = 0).

DS39940D-page 192

 2010 Microchip Technology Inc.

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REGISTER 17-1: UxMODE: UARTx MODE REGISTER (CONTINUED)

bit 3

BRGH: High Baud Rate Enable bit

1= High-Speed mode (four BRG clock cycles per bit)

0= Standard mode (16 BRG clock cycles per bit)

bit 2-1

PDSEL<1:0>: Parity and Data Selection bits

11= 9-bit data, no parity

10= 8-bit data, odd parity

01= 8-bit data, even parity

00= 8-bit data, no parity

bit 0

STSEL: Stop Bit Selection bit

1= Two Stop bits

0= One Stop bit

Note 1: If UARTEN = 1, the peripheral inputs and outputs must be configured to an available RPn pin. See

Section 10.4 “Peripheral Pin Select (PPS)” for more information.

2: This feature is only available for the 16x BRG mode (BRGH = 0).

 2010 Microchip Technology Inc.

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REGISTER 17-2: UxSTA: UARTx STATUS AND CONTROL REGISTER

R/W-0

UTXISEL1

bit 15

R/W-0

UTXINV⁽¹⁾

R/W-0

U-0

—

R/W-0, HC

UTXBRK

R/W-0

UTXEN⁽²⁾

R-0

R-1

UTXISEL0

UTXBF

TRMT

bit 8

R/W-0

URXISEL1

bit 7

R/W-0

R-1

R-0

R/C-0

R-0

URXISEL0

ADDEN

RIDLE

PERR

FERR

OERR

URXDA

bit 0

Legend:

C = Clearable bit

W = Writable bit

‘1’ = Bit is set

HC = Hardware Clearable bit

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

R = Readable bit

-n = Value at POR

bit 15,13

UTXISEL<1:0>: Transmission Interrupt Mode Selection bits

11= Reserved; do not use

10= Interrupt when a character is transferred to the Transmit Shift Register (TSR), and as a result,

the transmit buffer becomes empty

01= Interrupt when the last character is shifted out of the Transmit Shift Register; all transmit

operations are completed

00= Interrupt when a character is transferred to the Transmit Shift Register (this implies there is at

least one character open in the transmit buffer)

bit 14

UTXINV: IrDA^®Encoder Transmit Polarity Inversion bit⁽¹⁾

IREN = 0:

1= UxTX Idle ‘0’

0= UxTX Idle ‘1’

IREN = 1:

1= UxTX Idle ‘1’

0= UxTX Idle ‘0’

bit 12

bit 11

Unimplemented: Read as ‘0’

UTXBRK: Transmit Break bit

1= Send Sync Break on next transmission – Start bit, followed by twelve ‘0’ bits, followed by Stop bit;

cleared by hardware upon completion

0= Sync Break transmission disabled or completed

bit 10

UTXEN: Transmit Enable bit⁽²⁾

1= Transmit enabled, UxTX pin controlled by UARTx

0= Transmit disabled, any pending transmission is aborted and the buffer is reset; UxTX pin controlled

by port

bit 9

UTXBF: Transmit Buffer Full Status bit (read-only)

1= Transmit buffer is full

0= Transmit buffer is not full; at least one more character can be written

bit 8

TRMT: Transmit Shift Register Empty bit (read-only)

1= Transmit Shift Register is empty and transmit buffer is empty (the last transmission has completed)

0= Transmit Shift Register is not empty, a transmission is in progress or queued

bit 7-6

URXISEL<1:0>: Receive Interrupt Mode Selection bits

11= Interrupt is set on RSR transfer, making the receive buffer full (i.e., has 4 data characters)

10= Interrupt is set on RSR transfer, making the receive buffer 3/4 full (i.e., has 3 data characters)

0x= Interrupt is set when any character is received and transferred from the RSR to the receive buffer;

receive buffer has one or more characters

Note 1: Value of bit only affects the transmit properties of the module when the IrDA encoder is enabled (IREN = 1).

2: If UARTEN = 1, the peripheral inputs and outputs must be configured to an available RPn pin. See

Section 10.4 “Peripheral Pin Select (PPS)” for more information.

DS39940D-page 194

 2010 Microchip Technology Inc.

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REGISTER 17-2: UxSTA: UARTx STATUS AND CONTROL REGISTER (CONTINUED)

bit 5

bit 4

bit 3

bit 2

bit 1

ADDEN: Address Character Detect bit (bit 8 of received data = 1)

1= Address Detect mode enabled. If 9-bit mode is not selected, this does not take effect.

0= Address Detect mode disabled

RIDLE: Receiver Idle bit (read-only)

1= Receiver is Idle

0= Receiver is active

PERR: Parity Error Status bit (read-only)

1= Parity error has been detected for the current character (character at the top of the receive FIFO)

0= Parity error has not been detected

FERR: Framing Error Status bit (read-only)

1= Framing error has been detected for the current character (character at the top of the receive FIFO)

0= Framing error has not been detected

OERR: Receive Buffer Overrun Error Status bit (clear/read-only)

1= Receive buffer has overflowed

0= Receive buffer has not overflowed (clearing a previously set OERR bit (1 0transition) will reset

the receiver buffer and the RSR to the empty state

bit 0

URXDA: Receive Buffer Data Available bit (read-only)

1= Receive buffer has data, at least one more character can be read

0= Receive buffer is empty

Note 1: Value of bit only affects the transmit properties of the module when the IrDA encoder is enabled (IREN = 1).

2: If UARTEN = 1, the peripheral inputs and outputs must be configured to an available RPn pin. See

Section 10.4 “Peripheral Pin Select (PPS)” for more information.

 2010 Microchip Technology Inc.

DS39940D-page 195

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NOTES:

DS39940D-page 196

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The USB OTG module can function as a USB periph-

18.0 UNIVERSAL SERIAL BUS WITH

eral device or as a USB host, and may dynamically

switch between Device and Host modes under soft-

ware control. In either mode, the same data paths and

buffer descriptors are used for the transmission and

reception of data.

ON-THE-GO SUPPORT (USB

OTG)

Note:

This data sheet summarizes the features

of this group of PIC24F devices. It is not

intended to be a comprehensive reference

source. For more information, refer to the

“PIC24F Family Reference Manual”,

”Section 27. USB On-The-Go (OTG)”

(DS39721).

In discussing USB operation, this section will use a

controller-centric nomenclature for describing the direc-

tion of the data transfer between the microcontroller and

the USB. Rx (Receive) will be used to describe transfers

that move data from the USB to the microcontroller, and

Tx (Transmit) will be used to describe transfers that

move data from the microcontroller to the USB.

Table 18-1 shows the relationship between data

direction in this nomenclature and the USB tokens

exchanged.

PIC24FJ64GB004 family devices contain a full-speed

and low-speed compatible, On-The-Go (OTG) USB

Serial Interface Engine (SIE). The OTG capability

allows the device to act either as a USB peripheral

device or as a USB embedded host with limited host

capabilities. The OTG capability allows the device to

dynamically switch from device to host operation using

OTG’s Host Negotiation Protocol (HNP).

TABLE 18-1: CONTROLLER-CENTRIC

DATA DIRECTION FOR USB

HOST OR TARGET

For more details on OTG operation, refer to the

“On-The-Go Supplement to the USB 2.0 Specification”,

published by the USB-IF. For more information on USB

operation, refer to the “Universal Serial Bus

Specification”, v2.0.

Direction

USB Mode

Rx

Tx

Device

Host

OUT or SETUP

IN

OUT or SETUP

The USB OTG module offers these features:

This chapter presents the most basic operations

needed to implement USB OTG functionality in an

application. A complete and detailed discussion of the

USB protocol and its OTG supplement are beyond the

scope of this data sheet. It is assumed that the user

already has a basic understanding of USB architecture

and the latest version of the protocol.

• USB functionality in Device and Host modes, and

OTG capabilities for application-controlled mode

switching

• 0.25% Accuracy using Internal Oscillator – No

External Crystal Required

• Software-selectable module speeds of full speed

(12 Mbps) or low speed (1.5 Mbps, available in

Host mode only)

Not all steps for proper USB operation (such as device

enumeration) are presented here. It is recommended

that application developers use an appropriate device

driver to implement all of the necessary features.

Microchip provides a number of application-specific

resources, such as USB firmware and driver support.

Refer to www.microchip.com/usb for the latest

firmware and driver support.

• Support for all four USB transfer types: control,

interrupt, bulk and isochronous

• 16 bidirectional endpoints for a total of 32 unique

endpoints

• DMA interface for data RAM access

• Queues up to sixteen unique endpoint transfers

without servicing

• Integrated on-chip USB transceiver, with support

for off-chip transceivers via a digital interface

• Integrated VBUS generation with on-chip

comparators and boost generation, and support of

external VBUS comparators and regulators

through a digital interface

• Configurations for on-chip bus pull-up and

pull-down resistors

A simplified block diagram of the USB OTG module is

shown in Figure 18-1.

 2010 Microchip Technology Inc.

DS39940D-page 197

PIC24FJ64GB004 FAMILY

FIGURE 18-1:

USB OTG MODULE BLOCK DIAGRAM

Full-Speed Pull-up

Host Pull-down

48 MHz USB Clock

(1)

D+

Registers

and

Control

Interface

Transceiver

VUSB

Transceiver Power 3.3V

(1)

D-

Host Pull-down

(1)

USBID

USB

SIE

(1)

VMIO

VPIO

(1)

DMH

DPH

(1)

External Transceiver Interface

(1)

DMLN

DPLN

(1)

RCV

System

RAM

(1)

USBOEN

(1)

VBUSON

SRP Charge

USB

VBUS

Voltage

Comparators

SRP Discharge

(1)

VCMPST1

(1)

VCMPST2

VBUS

Boost

Assist

VBUSST

(1)

VCPCON

Note 1: Pins are multiplexed with digital I/O and other device features.

DS39940D-page 198

 2010 Microchip Technology Inc.

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To meet compliance specifications, the USB module

(and the D+ or D- pull-up resistor) should not be enabled

until the host actively drives VBUS high. One of the 5.5V

tolerant I/O pins may be used for this purpose.

18.1 Hardware Configuration

18.1.1

DEVICE MODE

18.1.1.1

D+ Pull-up Resistor

The application should never source any current onto

PIC24FJ64GB004 family devices have a built-in 1.5 k

resistor on the D+ line that is available when the micro-

controller in operating in device mode. This is used to

signal an external Host that the device is operating in

Full-Speed Device mode. It is engaged by setting the

USBEN bit (U1CON<0>). If the OTGEN bit

(U1OTGCON<2>) is set, then the D+ pull-up is enabled

through the DPPULUP bit (U1OTGCON<7>).

the 5V VBUS pin of the USB cable.

The Dual Power option with Self-Power Dominance

(Figure 18-5) allows the application to use internal

power primarily, but switch to power from the USB

when no internal power is available. Dual Power

devices must also meet all of the special requirements

for inrush current and Suspend mode current

previously described, and must not enable the USB

module until VBUS is driven high.

Alternatively, an external resistor may be used on D+,

as shown in Figure 18-2.

FIGURE 18-3:

BUS POWER ONLY

FIGURE 18-2:

EXTERNAL PULL-UP FOR

FULL-SPEED DEVICE

MODE

0-100 k

Attach Sense

VBUS

VDD

3.3V

Low IQ Regulator

VBUS

~5V

Host

Controller/HUB

PIC^®MCU

VUSB

VSS

VUSB

1.5 k

D+

D-

FIGURE 18-4:

SELF-POWER ONLY

0-100 k

Attach Sense

VBUS

~5V

VBUS

VDD

VSELF

~3.3V

18.1.1.2

Power Modes

Many USB applications will likely have several different

sets of power requirements and configuration. The

most common power modes encountered are:

VUSB

VSS

100 k

• Bus Power Only

• Self-Power Only

• Dual Power with Self-Power Dominance

Bus Power Only mode (Figure 18-3) is effectively the

simplest method. All power for the application is drawn

from the USB.

FIGURE 18-5:

DUAL POWER EXAMPLE

To meet the inrush current requirements of the USB 2.0

Specification, the total effective capacitance appearing

across VBUS and ground must be no more than 10 F.

0-100 k

3.3V

Attach Sense

VBUS

VDD

VBUS

~5V

In the USB Suspend mode, devices must consume no

more than 2.5 mA from the 5V VBUS line of the USB

cable. During the USB Suspend mode, the D+ or D-

pull-up resistor must remain active, which will consume

some of the allowed suspend current.

Low IQ

Regulator

VUSB

VSS

100 k

VSELF

~3.3V

In Self-Power Only mode (Figure 18-4), the USB

application provides its own power, with very little

power being pulled from the USB. Note that an attach

indication is added to indicate when the USB has been

connected and the host is actively powering VBUS.

 2010 Microchip Technology Inc.

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microcontroller is running below VBUS and is not able to

source sufficient current, a separate power supply must

be provided.

18.1.2

HOST AND OTG MODES

18.1.2.1

D+ and D- Pull-down Resistors

PIC24FJ64GB004 family devices have built-in 15 k

pull-down resistor on the D+ and D- lines. These are

used in tandem to signal to the bus that the microcon-

troller is operating in Host mode. They are engaged by

setting the HOSTEN bit (U1CON<3>). If the OTGEN bit

(U1OTGCON<2>) is set, then these pull-downs are

enabled by setting the DPPULDWN and DMPULDWN

bits (U1OTGCON<5:4>).

When the application is always operating in Host mode,

a simple circuit can be used to supply VBUS and regu-

late current on the bus (Figure 18-6). For OTG opera-

tion, it is necessary to be able to turn VBUS on or off as

needed, as the microcontroller switches between

Device and Host modes. A typical example using an

external charge pump is shown in Figure 18-7.

18.1.2.2

Power Configurations

In Host mode, as well as Host mode in On-the-Go

operation, the USB 2.0 specification requires that the

Host application supply power on VBUS. Since the

FIGURE 18-6:

HOST INTERFACE EXAMPLE

+3.3V

+5V

®

PIC Microcontroller

Thermal Fuse

Polymer PTC

VDD

VUSB

0.1 µF,

3.3V

2 k

150 µF

A/D pin

2 k

Micro A/B

Connector

VBUS

D+

VBUS

D+

D-

ID

VSS

GND

FIGURE 18-7:

OTG INTERFACE EXAMPLE

VDD

®

PIC Microcontroller

MCP1253

VIN

GND

C+

SELECT

10 µF

1 µF

C-

I/O

SHND

VOUT

PGOOD

I/O

Micro A/B

Connector

40 k

4.7 µF

VBUS

D+

VBUS

D+

D-

ID

VSS

GND

DS39940D-page 200

 2010 Microchip Technology Inc.

PIC24FJ64GB004 FAMILY

18.1.2.3

VBUS Voltage Generation with

External Devices

18.1.3

USING AN EXTERNAL INTERFACE

Some applications may require the USB interface to be

isolated from the rest of the system. PIC24FJ64GB004

family devices include a complete interface to commu-

nicate with and control an external USB transceiver,

including the control of data line pull-ups and

pull-downs. The VBUS voltage generation control circuit

can also be configured for different VBUS generation

topologies.

When operating as a USB host, either as an A-device

in an OTG configuration or as an embedded host, VBUS

must be supplied to the attached device.

PIC24FJ64GB004 family devices have an internal

VBUS boost assist to help generate the required 5V

VBUS from the available voltages on the board. This is

comprised of a simple PWM output to control a

switch-mode power supply, and built-in comparators to

monitor output voltage and limit current.

Please refer to the “PIC24F Family Reference Manual”,

”Section 27. USB On-The-Go (OTG)” for information

on using the external interface.

To enable voltage generation:

1. Verify that the USB module is powered

(U1PWRC<0> = 1) and that the VBUS discharge

is disabled (U1OTGCON<0> = 0).

18.1.4

CALCULATING TRANSCEIVER

POWER REQUIREMENTS

The USB transceiver consumes a variable amount of

current depending on the characteristic impedance of

the USB cable, the length of the cable, the VUSB supply

voltage and the actual data patterns moving across the

USB cable. Longer cables have larger capacitances

and consume more total energy when switching output

states. The total transceiver current consumption will

be application-specific. Equation 18-1 can help

estimate how much current actually may be required in

Full-speed applications.

2. Set the PWM period (U1PWMRRS<7:0>) and

duty cycle (U1PWMRRS<15:8>) as required.

3. Select the required polarity of the output signal

based on the configuration of the external circuit

with the PWMPOL bit (U1PWMCON<9>).

4. Select the desired target voltage using the

VBUSCHG bit (U1OTGCON<1>).

5. Enable the PWM counter by setting the CNTEN

bit to ‘1’ (U1PWMCON<8>).

6. Enable the PWM module by setting the PWMEN

Please refer to the “PIC24F Family Reference Manual”,

”Section 27. USB On-The-Go (OTG)” for a complete

discussion on transceiver power consumption.

bit to ‘1’ (U1PWMCON<15>).

7. Enable

the

VBUS

generation

circuit

(U1OTGCON<3> = 1).

Note:

This section describes the general

process for VBUS voltage generation and

control. Please refer to the “PIC24F

Family Reference Manual” for additional

examples.

EQUATION 18-1: ESTIMATING USB TRANSCEIVER CURRENT CONSUMPTION

(40 mA • VUSB • PZERO • PIN • LCABLE)

IXCVR =

+ IPULLUP

(3.3V • 5m)

Legend: VUSB – Voltage applied to the VUSB pin in volts (3.0V to 3.6V).

PZERO – Percentage (in decimal) of the IN traffic bits sent by the PIC^®microcontroller that are a value

of ‘0’.

PIN – Percentage (in decimal) of total bus bandwidth that is used for IN traffic.

LCABLE – Length (in meters) of the USB cable. The USB 2.0 Specification requires that full-speed

applications use cables no longer than 5m.

IPULLUP – Current which the nominal, 1.5 k pull-up resistor (when enabled) must supply to the USB

cable.

 2010 Microchip Technology Inc.

DS39940D-page 201

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Depending on the endpoint buffering configuration

18.2 USB Buffer Descriptors and the

BDT

used, there are up to 64 sets of buffer descriptors, for a

total of 256 bytes. At a minimum, the BDT must be at

least 8 bytes long. This is because the USB specifica-

tion mandates that every device must have Endpoint 0

with both input and output for initial setup.

Endpoint buffer control is handled through a structure

called the Buffer Descriptor Table (BDT). This provides

a flexible method for users to construct and control

endpoint buffers of various lengths and configurations.

Endpoint mapping in the BDT is dependent on three

variables:

The BDT can be located in any available, 512-byte

aligned block of data RAM. The BDT Pointer

(U1BDTP1) contains the upper address byte of the

BDT, and sets the location of the BDT in RAM. The user

must set this pointer to indicate the table’s location.

• Endpoint number (0 to 15)

• Endpoint direction (Rx or Tx)

• Ping-pong settings (U1CNFG1<1:0>)

Figure 18-8 illustrates how these variables are used to

map endpoints in the BDT.

The BDT is composed of Buffer Descriptors (BDs)

which are used to define and control the actual buffers

in the USB RAM space. Each BD consists of two, 16-bit

“soft” (non-fixed-address) registers, BDnSTAT and

BDnADR, where n represents one of the 64 possible

BDs (range of 0 to 63). BDnSTAT is the status register

for BDn, while BDnADR specifies the starting address

for the buffer associated with BDn.

In Host mode, only Endpoint 0 buffer descriptors are

used. All transfers utilize the Endpoint 0 buffer descriptor

and Endpoint Control register (U1EP0). For received

packets, the attached device’s source endpoint is

indicated by the value of ENDPT3:ENDPT0 in the USB

status register (U1STAT<7:4>). For transmitted packet,

the attached device’s destination endpoint is indicated

by the value written to the Token register (U1TOK).

FIGURE 18-8:

BDT MAPPING FOR ENDPOINT BUFFERING MODES

PPB<1:0> = 01

Ping-Pong Buffer

on EP0 OUT

PPB<1:0> = 11

PPB<1:0> = 00

No Ping-Pong

Buffers

PPB<1:0>0 = 10

Ping-Pong Buffers

on all EPs

Ping-Pong Buffers

on all other EPs

except EP0

Total BDT Space:

128 bytes

Total BDT Space:

132 bytes

Total BDT Space:

256 bytes

Total BDT Space:

248 bytes

EP0 Rx Even

Descriptor

EP0 Rx

Descriptor

EP0 Rx

Descriptor

EP0 Rx Even

Descriptor

EP0 Rx Odd

Descriptor

EP0 Tx

Descriptor

EP0 Tx

Descriptor

EP0 Rx Odd

Descriptor

EP0 Tx Even

Descriptor

EP1 Rx Even

Descriptor

EP1 Rx

Descriptor

EP0 Tx

Descriptor

EP1 Rx Odd

Descriptor

EP1 Tx

Descriptor

EP0 Tx Odd

Descriptor

EP1 Rx

Descriptor

EP1 Tx Even

Descriptor

EP1 Rx Even

Descriptor

EP1 Tx

Descriptor

EP1 Rx Odd

Descriptor

EP1 Tx Odd

Descriptor

EP15 Tx

Descriptor

EP1 Tx Even

Descriptor

EP15 Tx

Descriptor

EP1 Tx Odd

Descriptor

EP15 Tx Odd

Descriptor

EP15 Tx Odd

Descriptor

Note:

Memory area not shown to scale.

DS39940D-page 202

 2010 Microchip Technology Inc.

PIC24FJ64GB004 FAMILY

BDs have a fixed relationship to a particular endpoint,

The buffer descriptors have a different meaning based

on the source of the register update. Register 18-1 and

Register 18-2 show the differences in BDnSTAT

depending on its current “ownership”.

depending on the buffering configuration. Table 18-2

provides the mapping of BDs to endpoints. This rela-

tionship also means that gaps may occur in the BDT if

endpoints are not enabled contiguously. This theoreti-

cally means that the BDs for disabled endpoints could

be used as buffer space. In practice, users should

avoid using such spaces in the BDT unless a method

of validating BD addresses is implemented.

When UOWN is set, the user can no longer depend on

the values that were written to the BDs. From this point,

the USB module updates the BDs as necessary, over-

writing the original BD values. The BDnSTAT register is

updated by the SIE with the token PID and the transfer

count is updated.

18.2.1

BUFFER OWNERSHIP

18.2.2

DMA INTERFACE

Because the buffers and their BDs are shared between

the CPU and the USB module, a simple semaphore

mechanism is used to distinguish which is allowed to

update the BD and associated buffers in memory. This

is done by using the UOWN bit as a semaphore to

distinguish which is allowed to update the BD and

associated buffers in memory. UOWN is the only bit

that is shared between the two configurations of

BDnSTAT.

The USB OTG module uses a dedicated DMA to

access both the BDT and the endpoint data buffers.

Since part of the address space of the DMA is dedi-

cated to the Buffer Descriptors, a portion of the memory

connected to the DMA must comprise a contiguous

address space properly mapped for the access by the

module.

When UOWN is clear, the BD entry is “owned” by the

microcontroller core. When the UOWN bit is set, the BD

entry and the buffer memory are “owned” by the USB

peripheral. The core should not modify the BD or its

corresponding data buffer during this time. Note that

the microcontroller core can still read BDnSTAT while

the SIE owns the buffer and vice versa.

TABLE 18-2: ASSIGNMENT OF BUFFER DESCRIPTORS FOR THE DIFFERENT

BUFFERING MODES

BDs Assigned to Endpoint

Mode 3

(Ping-Pong on all other EPs,

except EP0)

Mode 0

(No Ping-Pong)

Mode 1

(Ping-Pong on EP0 OUT)

Mode 2

(Ping-Pong on all EPs)

Endpoint

Out

In

Out

In

Out

In

Out

In

0

1

0 (E), 1 (O)

2

0 (E), 1 (O)

4 (E), 5 (O)

8 (E), 9 (O)

2 (E), 3 (O)

6 (E), 7 (O)

0

1

2

3

4

2 (E), 3 (O)

6 (E), 7 (O)

4 (E), 5 (O)

8 (E), 9 (O)

2

4

5

6

10 (E), 11 (O)

3

6

7

8

12 (E), 13 (O) 14 (E), 15 (O) 10 (E), 11 (O) 12 (E), 13 (O)

16 (E), 17 (O) 18 (E), 19 (O) 14 (E), 15 (O) 16 (E), 17 (O)

20 (E), 21 (O) 22 (E), 23 (O) 18 (E), 19 (O) 20 (E), 21 (O)

24 (E), 25 (O) 26 (E), 27 (O) 22 (E), 23 (O) 24 (E), 25 (O)

4

8

9

10

12

14

16

18

20

22

24

26

28

30

32

5

10

12

14

16

18

20

22

24

26

28

30

11

13

15

17

19

21

23

25

27

29

31

11

13

15

17

19

21

23

25

27

29

31

6

7

28 (E), 29 (O)

30 (E), 31 (O) 26 (E), 27 (O) 28 (E), 29 (O)

8

32 (E), 33 (O) 34 (E), 35 (O) 30 (E), 31 (O) 32 (E), 33 (O)

36 (E), 37 (O) 38 (E), 39 (O) 34 (E), 35 (O) 36 (E), 37 (O)

40 (E), 41 (O) 42 (E), 43 (O) 38 (E), 39 (O) 40 (E), 41 (O)

44 (E), 45 (O) 46 (E), 47 (O) 42 (E), 43 (O) 44 (E), 45 (O)

48 (E), 49 (O) 50 (E), 51 (O) 46 (E), 47 (O) 48 (E), 49 (O)

52 (E), 53 (O) 54 (E), 55 (O) 50 (E), 51 (O) 52 (E), 53 (O)

56 (E), 57 (O) 58 (E), 59 (O) 54 (E), 55 (O) 56 (E), 57 (O)

60 (E), 61 (O) 62 (E), 63 (O) 58 (E), 59 (O) 60 (E), 61 (O)

9

10

11

12

13

14

15

Legend:

(E) = Even transaction buffer, (O) = Odd transaction buffer

 2010 Microchip Technology Inc.

DS39940D-page 203

PIC24FJ64GB004 FAMILY

REGISTER 18-1: BDnSTAT: BUFFER DESCRIPTOR n STATUS REGISTER PROTOTYPE, USB

MODE (BD0STAT THROUGH BD63STAT)

R/W-x

DTS

R/W-x

PID3

R/W-x

PID2

R/W-x

PID1

R/W-x

PID0

R/W-x

BC9

R/W-x

BC8

UOWN

bit 15

bit 8

R/W-x

BC7

R/W-x

BC6

R/W-x

BC5

R/W-x

BC4

R/W-x

BC3

R/W-x

BC2

R/W-x

BC1

R/W-x

BC0

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15

UOWN: USB Own bit

1= The USB module owns the BD and its corresponding buffer; the CPU must not modify the BD or

the buffer

bit 14

DTS: Data Toggle Packet bit

1= Data 1 packet

0= Data 0 packet

bit 13-10

PID<3:0>: Packet Identifier bits (written by the USB module)

In Device mode:

Represents the PID of the received token during the last transfer.

In Host mode:

Represents the last returned PID, or the transfer status indicator.

bit 9-0

BC<9:0>: Byte Count

This represents the number of bytes to be transmitted or the maximum number of bytes to be received

during a transfer. Upon completion, the byte count is updated by the USB module with the actual

number of bytes transmitted or received.

DS39940D-page 204

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PIC24FJ64GB004 FAMILY

REGISTER 18-2: BDnSTAT: BUFFER DESCRIPTOR n STATUS REGISTER PROTOTYPE, CPU

MODE (BD0STAT THROUGH BD63STAT)

R/W-x

DTS⁽¹⁾

R/W-x

0

R/W-x

0

R/W-x

BC9

R/W-x

BC8

UOWN

DTSEN

BSTALL

bit 15

bit 8

R/W-x

BC7

R/W-x

BC6

R/W-x

BC5

R/W-x

BC4

R/W-x

BC3

R/W-x

BC2

R/W-x

BC1

R/W-x

BC0

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15

bit 14

UOWN: USB Own bit

0= The microcontroller core owns the BD and its corresponding buffer. The USB module ignores all

other fields in the BD.

DTS: Data Toggle Packet bit⁽¹⁾

1= Data 1 packet

0= Data 0 packet

bit 13-12

bit 11

Reserved Function: Maintain as ‘0’

DTSEN: Data Toggle Synchronization Enable bit

1= Data toggle synchronization is enabled; data packets with incorrect sync value will be ignored

0= No data toggle synchronization is performed

bit 10

BSTALL: Buffer Stall Enable bit

1= Buffer STALL enabled; STALL handshake issued if a token is received that would use the BD in

the given location (UOWN bit remains set, BD value is unchanged); corresponding EPSTALL bit

will get set on any STALL handshake

0= Buffer STALL disabled

bit 9-0

BC<9:0>: Byte Count bits

This represents the number of bytes to be transmitted or the maximum number of bytes to be received

during a transfer. Upon completion, the byte count is updated by the USB module with the actual

number of bytes transmitted or received.

Note 1: This bit is ignored unless DTSEN = 1.

 2010 Microchip Technology Inc.

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level consists of USB error conditions, which are

18.3 USB Interrupts

enabled and flagged in the U1EIR and U1EIE registers.

An interrupt condition in any of these triggers a USB

Error Interrupt Flag (UERRIF) in the top level.

The USB OTG module has many conditions that can

be configured to cause an interrupt. All interrupt

sources use the same interrupt vector.

Interrupts may be used to trap routine events in a USB

transaction. Figure 18-10 provides some common

events within a USB frame and their corresponding

interrupts.

Figure 18-9 shows the interrupt logic for the USB mod-

ule. There are two layers of interrupt registers in the

USB module. The top level consists of overall USB

status interrupts; these are enabled and flagged in the

U1IE and U1IR registers, respectively. The second

FIGURE 18-9:

USB OTG INTERRUPT FUNNEL

Top Level (USB Status) Interrupts

STALLIF

STALLIE

ATTACHIF

ATTACHIE

RESUMEIF

RESUMEIE

IDLEIF

IDLEIE

TRNIF

TRNIE

Second Level (USB Error) Interrupts

SOFIF

SOFIE

BTSEF

BTSEE

Set USB1IF

URSTIF (DETACHIF)

DMAEF

DMAEE

URSTIE (DETACHIE)

BTOEF

BTOEE

(UERRIF)

UERRIE

DFN8EF

DFN8EE

IDIF

IDIE

CRC16EF

CRC16EE

T1MSECIF

TIMSECIE

CRC5EF (EOFEF)

CRC5EE (EOFEE)

LSTATEIF

LSTATEIE

PIDEF

PIDEE

ACTVIF

ACTVIE

SESVDIF

SESVDIE

SESENDIF

SESENDIE

VBUSVDIF

VBUSVDIE

Top Level (USB OTG) Interrupts

DS39940D-page 206

 2010 Microchip Technology Inc.

PIC24FJ64GB004 FAMILY

software by writing a ‘1’ to their locations (i.e., perform-

ing a MOVtype instruction). Writing a ‘0’ to a flag bit (i.e.,

a BCLRinstruction) has no effect.

18.3.1

CLEARING USB OTG INTERRUPTS

Unlike device level interrupts, the USB OTG interrupt

status flags are not freely writable in software. All USB

OTG flag bits are implemented as hardware set only

bits. Additionally, these bits can only be cleared in

Note:

Throughout this data sheet, a bit that can

only be cleared by writing a ‘1’ to its loca-

tion is referred to as “Write ‘1’ to clear”. In

register descriptions, this function is

indicated by the descriptor “K”.

FIGURE 18-10:

EXAMPLE OF A USB TRANSACTION AND INTERRUPT EVENTS

To Host

ACK

From Host

Data

Set TRNIF

SETUPToken

USB Reset

URSTIF

From Host

IN Token

To Host

Data

From Host

ACK

Start-of-Frame (SOF)

SOFIF

From Host

To Host

ACK

OUT Token Empty Data

Transaction

Complete

SOF

RESET

Differential Data

SOF

SETUP

DATA

STATUS

Control Transfer⁽¹⁾

1 ms Frame

Note 1: The control transfer shown here is only an example showing events that can occur for every transaction. Typical

control transfers will spread across multiple frames.

5. Enable the USB module by setting the USBEN

18.4 Device Mode Operation

bit (U1CON<0>).

The following section describes how to perform a com-

6. Set the OTGEN bit (U1OTGCON<2>) to enable

mon Device mode task. In Device mode, USB transfers

OTG operation.

are performed at the transfer level. The USB module

7. Enable the endpoint zero buffer to receive the

automatically performs the status phase of the transfer.

first setup packet by setting the EPRXEN and

EPHSHK bits for Endpoint 0 (U1EP0<3,0> = 1).

18.4.1

ENABLING DEVICE MODE

8. Power up the USB module by setting the

USBPWR bit (U1PWRC<0>).

1. Reset the Ping-Pong Buffer Pointers by setting,

then clearing, the Ping-Pong Buffer Reset bit

PPBRST (U1CON<1>).

9. Enable the D+ pull-up resistor to signal an attach

by setting DPPULUP (U1OTGCON<7>).

2. Disable all interrupts (U1IE and U1EIE = 00h).

3. Clear any existing interrupt flags by writing FFh

to U1IR and U1EIR.

4. Verify that VBUS is present (non OTG devices

only).

 2010 Microchip Technology Inc.

DS39940D-page 207

PIC24FJ64GB004 FAMILY

18.4.2

RECEIVING AN IN TOKEN IN

DEVICE MODE

18.5 Host Mode Operation

The following sections describe how to perform common

Host mode tasks. In Host mode, USB transfers are

invoked explicitly by the host software. The host soft-

ware is responsible for the Acknowledge portion of the

transfer. Also, all transfers are performed using the

1. Attach to a USB host and enumerate as described

in Chapter 9 of the USB 2.0 specification.

2. Create a data buffer, and populate it with the

data to send to the host.

Endpoint

descriptors.

0

control register (U1EP0) and buffer

3. In the appropriate (EVEN or ODD) Tx BD for the

desired endpoint:

a) Set up the status register (BDnSTAT) with

the correct data toggle (DATA0/1) value and

the byte count of the data buffer.

18.5.1

ENABLE HOST MODE AND

DISCOVER A CONNECTED DEVICE

1. Enable Host mode by setting the HOSTEN bit

(U1CON<3>). This causes the Host mode

control bits in other USB OTG registers to

become available.

b) Set up the address register (BDnADR) with

the starting address of the data buffer.

c) Set the UOWN bit of the status register to

‘1’.

2. Enable the D+ and D- pull-down resistors by set-

4. When the USB module receives an IN token, it

automatically transmits the data in the buffer.

Upon completion, the module updates the status

register (BDnSTAT) and sets the Transfer

Complete Interrupt Flag, TRNIF (U1IR<3>).

ting

DPPULDWN

and

DMPULDWN

(U1OTGCON<5:4>). Disable the D+ and D-

pull-up resistors by clearing DPPULUP and

DMPULUP (U1OTGCON<7:6>).

3. At this point, SOF generation begins with the

SOF counter loaded with 12,000. Eliminate

noise on the USB by clearing the SOFEN bit

(U1CON<0>) to disable Start-of-Frame packet

generation.

18.4.3

RECEIVING AN OUT TOKEN IN

DEVICE MODE

1. Attach to a USB host and enumerate as described

in Chapter 9 of the USB 2.0 specification.

4. Enable the device attached interrupt by setting

ATTACHIE (U1IE<6>).

2. Create a data buffer with the amount of data you

are expecting from the host.

5. Wait for the device attached interrupt

(U1IR<6> = 1). This is signaled by the USB

device changing the state of D+ or D- from ‘0’

to ‘1’ (SE0 to J state). After it occurs, wait

100 ms for the device power to stabilize.

3. In the appropriate (EVEN or ODD) Tx BD for the

desired endpoint:

a) Set up the status register (BDnSTAT) with

the correct data toggle (DATA0/1) value and

the byte count of the data buffer.

6. Check the state of the JSTATE and SE0 bits in

U1CON. If the JSTATE bit (U1CON<7>) is ‘0’,

the connecting device is low speed. If the con-

necting device is low speed, set the low

LSPDEN and LSPD bits (U1ADDR<7> and

U1EP0<7>) to enable low-speed operation.

b) Set up the address register (BDnADR) with

the starting address of the data buffer.

c) Set the UOWN bit of the status register to

‘1’.

4. When the USB module receives an OUT token,

it automatically receives the data sent by the

host to the buffer. Upon completion, the module

updates the status register (BDnSTAT) and sets

the Transfer Complete Interrupt Flag, TRNIF

(U1IR<3>).

7. Reset the USB device by setting the USBRST

bit (U1CON<4>) for at least 50 ms, sending

Reset signaling on the bus. After 50 ms,

terminate the Reset by clearing USBRST.

8. To keep the connected device from going into

suspend, enable SOF packet generation to keep

by setting the SOFEN bit.

9. Wait 10 ms for the device to recover from Reset.

10. Perform enumeration as described by Chapter 9

of the USB 2.0 specification.

DS39940D-page 208

 2010 Microchip Technology Inc.

PIC24FJ64GB004 FAMILY

8. Initialize the current (EVEN or ODD) Rx or Tx

18.5.2

COMPLETE A CONTROL

TRANSACTION TO A CONNECTED

DEVICE

(Rx for IN, Tx for OUT) EP0 BD to transfer the

data:

a) Write C040h to BD0STAT. This sets the

UOWN, configures Data Toggle (DTS) to

DATA1, and sets the byte count to the

length of the data buffer (64 or 40h, in this

case).

1. Follow

the

procedure

described

in

Section 18.5.1 “Enable Host Mode and Dis-

cover a Connected Device” to discover a

device.

2. Set up the Endpoint Control register for

bidirectional control transfers by writing 0Dh to

U1EP0 (this sets the EPCONDIS, EPTXEN, and

EPHSHK bits).

b) Set BD0ADR to the starting address of the

data buffer.

9. Write the token register with the appropriate IN

or OUT token to Endpoint 0, the target device’s

default control pipe (e.g., write 90h to U1TOK for

an IN token for a GET DEVICE DESCRIPTOR

command). This initiates an IN token on the bus

followed by a data packet from the device to the

host. When the data packet completes, the

BD0STAT is written and a transfer done interrupt

is asserted (the TRNIF flag is set). For control

transfers with a single packet data phase, this

completes the data phase of the setup transac-

tion as referenced in Chapter 9 of the USB

specification. If more data needs to be

transferred, return to step 8.

3. Place a copy of the device framework setup

command in a memory buffer. See Chapter 9 of

the USB 2.0 specification for information on the

device framework command set.

4. Initialize the buffer descriptor (BD) for the

current (EVEN or ODD) Tx EP0, to transfer the

eight bytes of command data for a device

framework command (i.e., a GET DEVICE

DESCRIPTOR):

a) Set the BD data buffer address (BD0ADR)

to the starting address of the 8-byte

memory buffer containing the command.

b) Write 8008h to BD0STAT (this sets the

UOWN bit, and sets a byte count of 8).

10. To initiate the status phase of the setup transac-

tion, set up a buffer in memory to receive or send

the zero length status phase data packet.

5. Set the USB device address of the target device

in the address register (U1ADDR<6:0>). After a

USB bus Reset, the device USB address will be

zero. After enumeration, it will be set to another

value between 1 and 127.

11. Initialize the current (even or odd) Tx EP0 BD to

transfer the status data:

a) Set the BDT buffer address field to the start

address of the data buffer

6. Write D0h to U1TOK; this is a SETUP token to

Endpoint 0, the target device’s default control

pipe. This initiates a SETUP token on the bus, fol-

lowed by a data packet. The device handshake is

returned in the PID field of BD0STAT after the

packets are complete. When the USB module

updates BD0STAT, a transfer done interrupt is

asserted (the TRNIF flag is set). This completes

the setup phase of the setup transaction as

referenced in Chapter 9 of the USB specification.

b) Write 8000h to BD0STAT (set UOWN bit,

configure DTS to DATA0, and set byte

count to 0).

12. Write the Token register with the appropriate IN or

OUT token to Endpoint 0, the target device’s

default control pipe (e.g., write 01h to U1TOK for

an OUT token for a GET DEVICE DESCRIPTOR

command). This initiates an OUT token on the

bus followed by a zero length data packet from

the host to the device. When the data packet

completes, the BD is updated with the handshake

from the device, and a transfer done interrupt is

asserted (the TRNIF flag is set). This completes

the status phase of the setup transaction as

described in Chapter 9 of the USB specification.

7. To initiate the data phase of the setup transac-

tion (i.e., get the data for the GET DEVICE

DESCRIPTOR command), set up a buffer in

memory to store the received data.

Note:

Only one control transaction can be

performed per frame.

 2010 Microchip Technology Inc.

DS39940D-page 209

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18.5.3

SEND A FULL-SPEED BULK DATA

TRANSFER TO A TARGET DEVICE

18.6 OTG Operation

18.6.1 SESSION REQUEST PROTOCOL

1. Follow the procedure described in Section 18.5.1

“Enable Host Mode and Discover a Connected

Device” and Section 18.5.2 “Complete a Con-

trol Transaction to a Connected Device” to

discover and configure a device.

(SRP)

An OTG A-device may decide to power down the VBUS

supply when it is not using the USB link through the Ses-

sion Request Protocol (SRP). Software may do this by

clearing VBUSON (U1OTGCON<3>). When the VBUS

supply is powered down, the A-device is said to have

ended a USB session.

2. To enable transmit and receive transfers with

handshaking enabled, write 1Dh to U1EP0. If

the target device is a low-speed device, also set

the LSPD bit (U1EP0<7>). If you want the hard-

ware to automatically retry indefinitely if the

target device asserts a NAK on the transfer,

clear the Retry Disable bit, RETRYDIS

(U1EP0<6>).

An OTG A-device or Embedded Host may re-power the

VBUS supply at any time (initiate a new session). An

OTG B-device may also request that the OTG A-device

re-power the VBUS supply (initiate a new session). This

is accomplished via Session Request Protocol (SRP).

3. Set up the BD for the current (EVEN or ODD) Tx

EP0 to transfer up to 64 bytes.

Prior to requesting a new session, the B-device must

first check that the previous session has definitely

ended. To do this, the B-device must check for two

conditions:

4. Set the USB device address of the target device

in the address register (U1ADDR<6:0>).

5. Write an OUT token to the desired endpoint to

U1TOK. This triggers the module’s transmit

state machines to begin transmitting the token

and the data.

1. VBUS supply is below the Session Valid voltage, and

2. Both D+ and D- have been low for at least 2 ms.

The B-device will be notified of condition 1 by the

SESENDIF (U1OTGIR<2>) interrupt. Software will

have to manually check for condition 2.

6. Wait for the Transfer Done Interrupt Flag,

TRNIF. This indicates that the BD has been

released back to the microprocessor, and the

transfer has completed. If the retry disable bit is

set, the handshake (ACK, NAK, STALL or

ERROR (0Fh)) is returned in the BD PID field. If

a STALL interrupt occurs, the pending packet

must be dequeued and the error condition in the

target device cleared. If a detach interrupt

occurs (SE0 for more than 2.5 s), then the

target has detached (U1IR<0> is set).

Note:

When the A-device powers down the VBUS

supply, the B-device must disconnect its

pull-up resistor from power. If the device is

self-powered, it can do this by clearing

DPPULUP

(U1OTGCON<7>)

and

DMPULUP (U1OTGCON<6>).

The B-device may aid in achieving condition 1 by dis-

charging the VBUS supply through a resistor. Software

may do this by setting VBUSDIS (U1OTGCON<0>).

7. Once the transfer done interrupt occurs (TRNIF

is set), the BD can be examined and the next

data packet queued by returning to step 2.

After these initial conditions are met, the B-device may

begin requesting the new session. The B-device begins

by pulsing the D+ data line. Software should do this by

setting DPPULUP (U1OTGCON<7>). The data line

should be held high for 5 to 10 ms.

Note:

USB speed, transceiver and pull-ups

should only be configured during the

module setup phase. It is not recom-

mended to change these settings while

the module is enabled.

DS39940D-page 210

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The B-device then proceeds by pulsing the VBUS

DPPULUP and DMPULUP. When the A-device detects

the disconnect condition (via the URSTIF (U1IR<0>)

interrupt), the A-device may allow the B-device to take

over as Host. The A-device does this by signaling con-

nect as a full-speed function. Software may accomplish

this by setting DPPULUP.

supply. Software should do this by setting PUVBUS

(U1CNFG2<4>). When an A-device detects SRP sig-

naling (either via the ATTACHIF (U1IR<6>) interrupt or

via the SESVDIF (U1OTGIR<3>) interrupt), the

A-device must restore the VBUS supply by either setting

VBUSON (U1OTGCON<3>), or by setting the I/O port

controlling the external power source.

If the A-device responds instead with resume signaling,

the A-device remains as host. When the B-device

detects the connect condition (via ATTACHIF

(U1IR<6>), the B-device becomes host. The B-device

drives Reset signaling prior to using the bus.

The B-device should not monitor the state of the VBUS

supply while performing VBUS supply pulsing. When the

B-device does detect that the VBUS supply has been

restored (via the SESVDIF (U1OTGIR<3>) interrupt),

the B-device must re-connect to the USB link by pulling

up D+ or D- (via the DPPULUP or DMPULUP).

When the B-device has finished in its role as Host, it

stops all bus activity and turns on its D+ pull-up resistor

by setting DPPULUP. When the A-device detects a

suspend condition (Idle for 3 ms), the A-device turns off

its D+ pull-up. The A-device may also power-down

VBUS supply to end the session. When the A-device

detects the connect condition (via ATTACHIF), the

A-device resumes host operation, and drives Reset

signaling.

The A-device must complete the SRP by driving USB

Reset signaling.

18.6.2

HOST NEGOTIATION PROTOCOL

(HNP)

In USB OTG applications, a Dual Role Device (DRD) is

a device that is capable of being either a host or a

peripheral. Any OTG DRD must support Host

Negotiation Protocol (HNP).

18.6.3

EXTERNAL VBUS COMPARATORS

The external VBUS comparator option is enabled by

setting the UVCMPDIS bit (U1CNFG2<1>). This dis-

ables the internal VBUS comparators, removing the

need to attach VBUS to the microcontroller’s VBUS pin.

HNP allows an OTG B-device to temporarily become

the USB host. The A-device must first enable the

B-device to follow HNP. Refer to the On-The-Go

Supplement to the USB 2.0 Specification for more

information regarding HNP. HNP may only be initiated

at full speed.

The external comparator interface uses either the

VCMPST1 and VCMPST2 pins, or the VBUSVLD,

SESSVLD and SESSEND pins, based upon the setting

of the UVCMPSEL bit (U1CNFG2<5>). These pins are

digital inputs and should be set in the following patterns

(see Table 18-3), based on the current level of the

VBUS voltage.

After being enabled for HNP by the A-device, the

B-device requests being the host any time that the USB

link is in Suspend state, by simply indicating a discon-

nect. This can be done in software by clearing

TABLE 18-3: EXTERNAL VBUS COMPARATOR STATES

If UVCMPSEL = 0

VCMPST1

VCMPST2

Bus Condition

0

1

0

1

0

1

VBUS < VB_SESS_END

VB_SESS_END < VBUS < VA_SESS_VLD

VA_SESS_VLD < VBUS < VA_VBUS_VLD

VBUS > VVBUS_VLD

If UVCMPSEL = 1

VBUSVLD

SESSVLD

SESSEND

Bus Condition

0

1

0

1

0

VBUS < VB_SESS_END

VB_SESS_END < VBUS < VA_SESS_VLD

VA_SESS_VLD < VBUS < VA_VBUS_VLD

VBUS > VVBUS_VLD

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Registers described in the following sections are those

18.7 USB OTG Module Registers

that have bits with specific control and configuration

features. The following registers are used for data or

address values only:

There are a total of 37 memory mapped registers asso-

ciated with the USB OTG module. They can be divided

into four general categories:

• U1BDTP1: Specifies the 256-word page in data

RAM used for the BDT; 8-bit value with bit 0 fixed

as ‘0’ for boundary alignment

• USB OTG Module Control (12)

• USB Interrupt (7)

• USB Endpoint Management (16)

• USB VBUS Power Control (2)

• U1FRML and U1FRMH: Contains the 11-bit byte

counter for the current data frame

• U1PWMRRS: Contains the 8-bit value for PWM

duty cycle (bits<15:8>) and PWM period

(bits<7:0>) for the VBUS boost assist PWM

module.

This total does not include the (up to) 128 BD registers

in the BDT. Their prototypes, described in

Register 18-1 and Register 18-2, are shown separately

in Section 18.2 “USB Buffer Descriptors and the

BDT”.

With the exception U1PWMCON and U1PWMRRS, all

USB OTG registers are implemented in the Least Sig-

nificant Byte of the register. Bits in the upper byte are

unimplemented, and have no function. Note that some

registers are instantiated only in Host mode, while

other registers have different bit instantiations and

functions in Device and Host modes.

DS39940D-page 212

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18.7.1

USB OTG MODULE CONTROL REGISTERS

REGISTER 18-3: U1OTGSTAT: USB OTG STATUS REGISTER (HOST MODE ONLY)

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

bit 15

bit 8

R-0, HSC

ID

U-0

—

R-0, HSC

LSTATE

U-0

—

R-0, HSC

SESVD

R-0, HSC

SESEND

U-0

—

R-0, HSC

VBUSVD

bit 7

bit 0

Legend:

U = Unimplemented bit, read as ‘0’

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

HSC = Hardware Settable/Clearable bit

‘0’ = Bit is cleared x = Bit is unknown

bit 15-8

bit 7

Unimplemented: Read as ‘0’

ID: ID Pin State Indicator bit

1= No plug is attached, or a type B cable has been plugged into the USB receptacle

0= A type A plug has been plugged into the USB receptacle

bit 6

bit 5

Unimplemented: Read as ‘0’

LSTATE: Line State Stable Indicator bit

1= The USB line state (as defined by SE0 and JSTATE) has been stable for the previous 1 ms

0= The USB line state has NOT been stable for the previous 1 ms

bit 4

bit 3

Unimplemented: Read as ‘0’

SESVD: Session Valid Indicator bit

1= The VBUS voltage is above VA_SESS_VLD (as defined in the USB OTG Specification) on the A or

B-device

0= The VBUS voltage is below VA_SESS_VLD on the A or B-device

bit 2

SESEND: B-Session End Indicator bit

1= The VBUS voltage is below VB_SESS_END (as defined in the USB OTG Specification) on the

B-device

0= The VBUS voltage is above VB_SESS_END on the B-device

bit 1

bit 0

Unimplemented: Read as ‘0’

VBUSVD: A-VBUS Valid Indicator bit

1= The VBUS voltage is above VA_VBUS_VLD (as defined in the USB OTG Specification) on the

A-device

0= The VBUS voltage is below VA_VBUS_VLD on the A-device

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REGISTER 18-4: U1OTGCON: USB ON-THE-GO CONTROL REGISTER

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

bit 15

bit 8

R/W-0

DPPULUP DMPULUP DPPULDWN⁽¹⁾DMPULDWN⁽¹⁾VBUSON⁽¹⁾OTGEN⁽¹⁾VBUSCHG⁽¹⁾VBUSDIS⁽¹⁾

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15-8

bit 7

Unimplemented: Read as ‘0’

DPPULUP: D+ Pull-Up Enable bit

1= D+ data line pull-up resistor is enabled

0= D+ data line pull-up resistor is disabled

bit 6

bit 5

bit 4

bit 3

bit 2

DMPULUP: D- Pull-Up Enable bit

1= D- data line pull-up resistor is enabled

0= D- data line pull-up resistor is disabled

(1)

DPPULDWN: D+ Pull-Down Enable bit

1= D+ data line pull-down resistor is enabled

0= D+ data line pull-down resistor is disabled

(1)

DMPULDWN: D- Pull-Down Enable bit

1= D- data line pull-down resistor is enabled

0= D- data line pull-down resistor is disabled

(1)

VBUSON: VBUS Power-on bit

1= VBUS line is powered

0= VBUS line is not powered

(1)

OTGEN: OTG Features Enable bit

1= USB OTG is enabled; all D+/D- pull-ups and pull-downs bits are enabled

0= USB OTG is disabled; D+/D- pull-ups and pull-downs are controlled in hardware by the settings of

the HOSTEN and USBEN bits (U1CON<3,0>)

(1)

bit 1

bit 0

VBUSCHG: VBUS Charge Select bit

1= VBUS line is set to charge to 3.3V

0= VBUS line is set to charge to 5V

(1)

VBUSDIS: VBUS Discharge Enable bit

1= VBUS line is discharged through a resistor

0= VBUS line is not discharged

Note 1: These bits are only used in Host mode; do not use in Device mode.

DS39940D-page 214

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REGISTER 18-5: U1PWRC: USB POWER CONTROL REGISTER

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

bit 15

bit 8

R/W-0, HS

UACTPND

U-0

—

U-0

—

R/W-0

U-0

—

U-0

—

R/W-0, HC

USUSPND

R/W-0

USLPGRD

USBPWR

bit 7

bit 0

Legend:

HS = Hardware Settable bit HC = Hardware Clearable bit

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15-8

bit 7

Unimplemented: Read as ‘0’

UACTPND: USB Activity Pending bit

1= Module should not be suspended at the moment (requires USLPGRD bit to be set)

0= Module may be suspended or powered down

bit 6-5

bit 4

Unimplemented: Read as ‘0’

USLPGRD: Sleep/Suspend Guard bit

1= Indicate to the USB module that it is about to be suspended or powered down

0= No suspend

bit 3-2

bit 1

Unimplemented: Read as ‘0’

USUSPND: USB Suspend Mode Enable bit

1= USB OTG module is in Suspend mode; USB clock is gated and the transceiver is placed in a

low-power state

0= Normal USB OTG operation

bit 0

USBPWR: USB Operation Enable bit

1= USB OTG module is enabled

0= USB OTG module is disabled⁽¹⁾

Note 1: Do not clear this bit unless the HOSTEN, USBEN and OTGEN bits (U1CON<3,0> and U1OTGCON<2>)

are all cleared.

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REGISTER 18-6: U1STAT: USB STATUS REGISTER

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

bit 15

bit 8

bit 0

R-0, HSC

ENDPT3

R-0, HSC

ENDPT2

R-0, HSC

ENDPT1

R-0, HSC

ENDPT0

R-0, HSC

DIR

R-0, HSC

PPBI⁽¹⁾

U-0

—

U-0

—

bit 7

Legend:

U = Unimplemented bit, read as ‘0’

R = Readable bit

W = Writable bit

‘1’ = Bit is set

HSC = Hardware Settable/Clearable bit

‘0’ = Bit is cleared x = Bit is unknown

-n = Value at POR

bit 15-8

bit 7-4

Unimplemented: Read as ‘0’

ENDPT<3:0>: Number of the Last Endpoint Activity bits

(Represents the number of the BDT updated by the last USB transfer).

1111= Endpoint 15

1110= Endpoint 14

....

0001= Endpoint 1

0000= Endpoint 0

bit 3

DIR: Last BD Direction Indicator bit

1= The last transaction was a transmit transfer (Tx)

0= The last transaction was a receive transfer (Rx)

bit 2

PPBI: Ping-Pong BD Pointer Indicator bit⁽¹⁾

1= The last transaction was to the ODD BD bank

0= The last transaction was to the EVEN BD bank

bit 1-0

Unimplemented: Read as ‘0’

Note 1: This bit is only valid for endpoints with available EVEN and ODD BD registers.

DS39940D-page 216

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REGISTER 18-7: U1CON: USB CONTROL REGISTER (DEVICE MODE)

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

bit 15

bit 8

U-0

—

R-x, HSC

SE0

R/W-0

U-0

—

R/W-0

PKTDIS

HOSTEN

RESUME

PPBRST

USBEN

bit 7

bit 0

Legend:

U = Unimplemented bit, read as ‘0’

R = Readable bit

W = Writable bit

‘1’ = Bit is set

HSC = Hardware Settable/Clearable bit

‘0’ = Bit is cleared x = Bit is unknown

-n = Value at POR

bit 15-7

bit 6

Unimplemented: Read as ‘0’

SE0: Live Single-Ended Zero Flag bit

1= Single-ended zero is active on the USB bus

0= No single-ended zero is detected

bit 5

PKTDIS: Packet Transfer Disable bit

1= SIE token and packet processing are disabled; automatically set when a SETUP token is received

0= SIE token and packet processing are enabled

bit 4

bit 3

Unimplemented: Read as ‘0’

HOSTEN: Host Mode Enable bit

1= USB host capability is enabled; pull-downs on D+ and D- are activated in hardware

0= USB host capability is disabled

bit 2

bit 1

bit 0

RESUME: Resume Signaling Enable bit

1= Resume signaling is activated

0= Resume signaling is disabled

PPBRST: Ping-Pong Buffers Reset bit

1 = Reset all Ping-Pong Buffer Pointers to the EVEN BD banks

0 = Ping-Pong Buffer Pointers are not reset

USBEN: USB Module Enable bit

1= USB module and supporting circuitry are enabled (device attached); D+ pull-up is activated in hard-

ware

0= USB module and supporting circuitry are disabled (device detached)

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REGISTER 18-8: U1CON: USB CONTROL REGISTER (HOST MODE ONLY)

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

bit 15

bit 8

R-x, HSC

JSTATE

R-x, HSC

SE0

R/W-0

TOKBUSY

USBRST

HOSTEN

RESUME

PPBRST

SOFEN

bit 7

bit 0

Legend:

U = Unimplemented bit, read as ‘0’

R = Readable bit

W = Writable bit

‘1’ = Bit is set

HSC = Hardware Settable/Clearable bit

‘0’ = Bit is cleared x = Bit is unknown

-n = Value at POR

bit 15-8

bit 7

Unimplemented: Read as ‘0’

JSTATE: Live Differential Receiver J State Flag bit

1 = J state (differential ‘0’ in low speed, differential ‘1’ in full speed) is detected on the USB

0 = No J state was detected

bit 6

bit 5

bit 4

SE0: Live Single-Ended Zero Flag bit

1= Single-ended zero is active on the USB bus

0= No single-ended zero is detected

TOKBUSY: Token Busy Status bit

1= Token is being executed by the USB module in On-The-Go state

0= No token is being executed

USBRST: Module Reset bit

1= USB Reset has been generated; for software Reset, application must set this bit for 50 ms, then

clear it

0= USB Reset is terminated

bit 3

bit 2

bit 1

bit 0

HOSTEN: Host Mode Enable bit

1= USB host capability is enabled; pull-downs on D+ and D- are activated in hardware

0= USB host capability is disabled

RESUME: Resume Signaling Enable bit

1= Resume signaling activated; software must set bit for 10 ms and then clear to enable remote wake-up

0= Resume signaling disabled

PPBRST: Ping-Pong Buffers Reset bit

1 = Reset all Ping-Pong Buffer Pointers to the EVEN BD banks

0 = Ping-Pong Buffer Pointers are not reset

SOFEN: Start-of-Frame Enable bit

1= Start-of-Frame token is sent every one 1 millisecond

0= Start-of-Frame token is disabled

DS39940D-page 218

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REGISTER 18-9: U1ADDR: USB ADDRESS REGISTER

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

bit 15

bit 8

R/W-0

LSPDEN⁽¹⁾

ADDR6

ADDR5

ADDR4

ADDR3

ADDR2

ADDR1

ADDR0

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15-8

bit 7

Unimplemented: Read as ‘0’

LSPDEN: Low-Speed Enable Indicator bit⁽¹⁾

1= USB module operates at low speed

0= USB module operates at full speed

bit 6-0

ADDR<6:0>: USB Device Address bits

Note 1: Host mode only. In Device mode, this bit is unimplemented and read as ‘0’.

REGISTER 18-10: U1TOK: USB TOKEN REGISTER (HOST MODE ONLY)

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

bit 15

bit 8

R/W-0

PID3

R/W-0

PID2

R/W-0

PID1

R/W-0

PID0

R/W-0

EP3

R/W-0

EP2

R/W-0

EP1

R/W-0

EP0

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15-8

bit 7-4

Unimplemented: Read as ‘0’

PID<3:0>: Token Type Identifier bits

1101= SETUP (TX) token type transaction⁽¹⁾

1001= IN (RX) token type transaction⁽¹⁾

0001= OUT (TX) token type transaction⁽¹⁾

bit 3-0

EP<3:0>: Token Command Endpoint Address bits

This value must specify a valid endpoint on the attached device.

Note 1: All other combinations are reserved and are not to be used.

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REGISTER 18-11: U1SOF: USB OTG START-OF-TOKEN THRESHOLD REGISTER (HOST MODE ONLY)

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

bit 15

bit 8

R/W-0

CNT7

R/W-0

CNT6

R/W-0

CNT5

R/W-0

CNT4

R/W-0

CNT3

R/W-0

CNT2

R/W-0

CNT1

R/W-0

CNT0

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15-8

bit 7-0

Unimplemented: Read as ‘0’

CNT<7:0>: Start-of-Frame Size bits;

Value represents 10 + (packet size of n bytes). For example:

0100 1010= 64-byte packet

0010 1010= 32-byte packet

0001 0010= 8-byte packet

REGISTER 18-12: U1CNFG1: USB CONFIGURATION REGISTER 1

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

bit 15

bit 8

R/W-0

UOEMON⁽¹⁾

U-0

—

R/W-0

U-0

—

U-0

—

R/W-0

PPB1

R/W-0

PPB0

UTEYE

USBSIDL

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15-8

bit 7

Unimplemented: Read as ‘0’

UTEYE: USB Eye Pattern Test Enable bit

1= Eye pattern test is enabled

0= Eye pattern test is disabled

bit 6

UOEMON: USB OE Monitor Enable bit⁽¹⁾

1= OE signal is active; it indicates the intervals during which the D+/D- lines are driving

0= OE signal is inactive

bit 5

bit 4

Unimplemented: Read as ‘0’

USBSIDL: USB OTG Stop in Idle Mode bit

1= Discontinue module operation when device enters Idle mode

0= Continue module operation in Idle mode

bit 3-2

Unimplemented: Read as ‘0’

Note 1: This bit is only active when the UTRDIS bit (U1CNFG2<0>) is set.

DS39940D-page 220

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REGISTER 18-12: U1CNFG1: USB CONFIGURATION REGISTER 1 (CONTINUED)

bit 1-0 PPB<1:0>: Ping-Pong Buffers Configuration bit

11= EVEN/ODD ping-pong buffers are enabled for Endpoints 1 to 15

10= EVEN/ODD ping-pong buffers are enabled for all endpoints

01= EVEN/ODD ping-pong buffers are enabled for OUT Endpoint 0

00= EVEN/ODD ping-pong are buffers are disabled

Note 1: This bit is only active when the UTRDIS bit (U1CNFG2<0>) is set.

REGISTER 18-13: U1CNFG2: USB CONFIGURATION REGISTER 2

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

bit 15

bit 8

U-0

—

U-0

—

R/W-0

UTRDIS⁽¹⁾

(1)

UVCMPSEL

PUVBUS

EXTI2CEN UVBUSDIS

UVCMPDIS

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15-6

bit 5

Unimplemented: Read as ‘0’

UVCMPSEL: External Comparator Input Mode Select bit (see Table 18-3)

When UVCMPDIS is set:

1= Use 3 pin input for external comparators

0= Use 2 pin input for external comparators

bit 4

bit 3

bit 2

bit 1

bit 0

PUVBUS: VBUS Pull-up Enable bit

1= Pull-up on VBUS pin is enabled

0= Pull-up on VBUS pin is disabled

EXTI2CEN: I²C™ Interface For External Module Control Enable bit

1= External module(s) is controlled via I²C interface

0= External module(s) is controlled via dedicated pins

UVBUSDIS: On-Chip 5V Boost Regulator Builder Disable bit⁽¹⁾

1= On-chip boost regulator builder is disabled; digital output control interface is enabled

0= On-chip boost regulator builder is active

UVCMPDIS: On-Chip VBUS Comparator Disable bit⁽¹⁾

1= On-chip charge VBUS comparator is disabled; digital input status interface is enabled

0= On-chip charge VBUS comparator is active

UTRDIS: On-Chip Transceiver Disable bit⁽¹⁾

1= On-chip transceiver is disabled; digital transceiver interface is enabled

0= On-chip transceiver is active

Note 1: Never change these bits while the USBPWR bit is set (U1PWRC<0> = 1).

 2010 Microchip Technology Inc.

DS39940D-page 221

PIC24FJ64GB004 FAMILY

18.7.2

USB INTERRUPT REGISTERS

REGISTER 18-14: U1OTGIR: USB OTG INTERRUPT STATUS REGISTER (HOST MODE ONLY)

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

bit 15

bit 8

R/K-0, HS

IDIF

R/K-0, HS

T1MSECIF

R/K-0, HS

LSTATEIF

R/K-0, HS

ACTVIF

R/K-0, HS

SESVDIF

R/K-0, HS

U-0

—

R/K-0, HS

VBUSVDIF

bit 0

SESENDIF

bit 7

Legend:

U = Unimplemented bit, read as ‘0’

R = Readable bit

-n = Value at POR

K = Write ‘1’ to clear bit

‘1’ = Bit is set

HS = Hardware Settable bit

‘0’ = Bit is cleared

x = Bit is unknown

bit 15-8

bit 7

Unimplemented: Read as ‘0’

IDIF: ID State Change Indicator bit

1= Change in ID state is detected

0= No ID state change

bit 6

bit 5

T1MSECIF: 1 Millisecond Timer bit

1= The 1 millisecond timer has expired

0= The 1 millisecond timer has not expired

LSTATEIF: Line State Stable Indicator bit

1= USB line state (as defined by the SE0 and JSTATE bits) has been stable for 1 ms, but different

from last time

0= USB line state has not been stable for 1 ms

bit 4

bit 3

bit 2

ACTVIF: Bus Activity Indicator bit

1= Activity on the D+/D- lines or VBUS is detected

0= No activity on the D+/D- lines or VBUS is detected

SESVDIF: Session Valid Change Indicator bit

1= VBUS has crossed VA_SESS_END (as defined in the USB OTG Specification)⁽¹⁾

0= VBUS has not crossed VA_SESS_END

SESENDIF: B-Device VBUS Change Indicator bit

1= VBUS change on B-device is detected; VBUS has crossed VB_SESS_END (as defined in the USB

OTG Specification)⁽¹⁾

0= VBUS has not crossed VA_SESS_END

bit 1

bit 0

Unimplemented: Read as ‘0’

VBUSVDIF A-Device VBUS Change Indicator bit

1= VBUS change on A-device is detected; VBUS has crossed VA_VBUS_VLD (as defined in the USB

OTG Specification)⁽¹⁾

0= No VBUS change on A-device is detected

Note 1: VBUS threshold crossings may be either rising or falling.

Note:

Individual bits can only be cleared by writing a ‘1’ to the bit position as part of a word write operation on the

entire register. Using Boolean instructions or bitwise operations to write to a single bit position will cause

all set bits at the moment of the write to become cleared.

DS39940D-page 222

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REGISTER 18-15: U1OTGIE: USB OTG INTERRUPT ENABLE REGISTER (HOST MODE ONLY)

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

bit 15

bit 8

R/W-0

IDIE

R/W-0

U-0

—

R/W-0

VBUSVDIE

bit 0

T1MSECIE

LSTATEIE

ACTVIE

SESVDIE

SESENDIE

bit 7

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15-8

bit 7

Unimplemented: Read as ‘0’

IDIE: ID Interrupt Enable bit

1= Interrupt is enabled

0= Interrupt is disabled

bit 6

bit 5

bit 4

bit 3

bit 2

T1MSECIE: 1 Millisecond Timer Interrupt Enable bit

1= Interrupt is enabled

0= Interrupt is disabled

LSTATEIE: Line State Stable Interrupt Enable bit

1= Interrupt is enabled

0= Interrupt is disabled

ACTVIE: Bus Activity Interrupt Enable bit

1= Interrupt is enabled

0= Interrupt is disabled

SESVDIE: Session Valid Interrupt Enable bit

1= Interrupt is enabled

0= Interrupt is disabled

SESENDIE: B-Device Session End Interrupt Enable bit

1= Interrupt is enabled

0= Interrupt is disabled

bit 1

bit 0

Unimplemented: Read as ‘0’

VBUSVDIE: A-Device VBUS Valid Interrupt Enable bit

1= Interrupt is enabled

0= Interrupt is disabled

 2010 Microchip Technology Inc.

DS39940D-page 223

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REGISTER 18-16: U1IR: USB INTERRUPT STATUS REGISTER (DEVICE MODE ONLY)

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

bit 15

bit 8

R/K-0, HS

STALLIF

U-0

—

R/K-0, HS

IDLEIF

R/K-0, HS

TRNIF

R/K-0, HS

SOFIF

R-0

R/K-0, HS

URSTIF

RESUMEIF

UERRIF

bit 7

bit 0

Legend:

U = Unimplemented bit, read as ‘0’

R = Readable bit

-n = Value at POR

K = Write ‘1’ to clear bit

‘1’ = Bit is set

HS = Hardware Settable bit

‘0’ = Bit is cleared

x = Bit is unknown

bit 15-8

bit 7

Unimplemented: Read as ‘0’

STALLIF: STALL Handshake Interrupt bit

1= A STALL handshake was sent by the peripheral during the handshake phase of the transaction in

Device mode

0= A STALL handshake has not been sent

bit 6

bit 5

Unimplemented: Read as ‘0’

RESUMEIF: Resume Interrupt bit

1= A K-state was observed on the D+ or D- pin for 2.5 s (differential ‘1’ for low speed, differential ‘0’

for full speed)

0= No K-state was observed

bit 4

bit 3

IDLEIF: Idle Detect Interrupt bit

1= Idle condition was detected (constant Idle state of 3 ms or more)

0= No Idle condition was detected

TRNIF: Token Processing Complete Interrupt bit

1= Processing of current token was complete; read U1STAT register for endpoint information

0= Processing of current token was not complete; clear U1STAT register or load next token from STAT

(clearing this bit causes the STAT FIFO to advance)

bit 2

bit 1

bit 0

SOFIF: Start-of-Frame Token Interrupt bit

1= A Start-of-Frame token received by the peripheral or the Start-of-Frame threshold was reached by

the host

0= No Start-of-Frame token was received or threshold reached

UERRIF: USB Error Condition Interrupt bit (read-only)

1= An unmasked error condition has occurred; only error states enabled in the U1EIE register can set

this bit

0= No unmasked error condition has occurred

URSTIF: USB Reset Interrupt bit

1= Valid USB Reset has occurred for at least 2.5 s; Reset state must be cleared before this bit can

be reasserted

0= No USB Reset has occurred. Individual bits can only be cleared by writing a ‘1’ to the bit position

as part of a word write operation on the entire register. Using Boolean instructions or bitwise oper-

ations to write to a single bit position will cause all set bits at the moment of the write to become

cleared.

Note:

Individual bits can only be cleared by writing a ‘1’ to the bit position as part of a word write operation on the

entire register. Using Boolean instructions or bitwise operations to write to a single bit position will cause

all set bits at the moment of the write to become cleared.

DS39940D-page 224

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REGISTER 18-17: U1IR: USB INTERRUPT STATUS REGISTER (HOST MODE ONLY)

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

bit 15

bit 8

R/K-0, HS

STALLIF

R/K-0, HS

ATTACHIF

R/K-0, HS

IDLEIF

R/K-0, HS

TRNIF

R/K-0, HS

SOFIF

R-0

R/K-0, HS

DETACHIF

bit 0

RESUMEIF

UERRIF

bit 7

Legend:

U = Unimplemented bit, read as ‘0’

R = Readable bit

-n = Value at POR

K = Write ‘1’ to clear bit

‘1’ = Bit is set

HS = Hardware Settable bit

‘0’ = Bit is cleared

x = Bit is unknown

bit 15-8

bit 7

Unimplemented: Read as ‘0’

STALLIF: STALL Handshake Interrupt bit

1= A STALL handshake was sent by the peripheral device during the handshake phase of the

transaction in Device mode

0= A STALL handshake has not been sent

bit 6

bit 5

ATTACHIF: Peripheral Attach Interrupt bit

1= A peripheral attachment has been detected by the module; set if the bus state is not SE0 and there

has been no bus activity for 2.5 s

0= No peripheral attachment is detected

RESUMEIF: Resume Interrupt bit

1= A K-state is observed on the D+ or D- pin for 2.5 s (differential ‘1’ for low speed, differential ‘0’ for

full speed)

0= No K-state is observed

bit 4

bit 3

bit 2

IDLEIF: Idle Detect Interrupt bit

1= Idle condition is detected (constant Idle state of 3 ms or more)

0= No Idle condition is detected

TRNIF: Token Processing Complete Interrupt bit

1= Processing of current token is complete; read U1STAT register for endpoint information

0= Processing of current token is not complete; clear U1STAT register or load next token from U1STAT

SOFIF: Start-of-Frame Token Interrupt bit

1= A Start-of-Frame token is received by the peripheral or the Start-of-Frame threshold reached by

the host

0= No Start-of-Frame token is received or threshold reached

bit 1

bit 0

UERRIF: USB Error Condition Interrupt bit

1= An unmasked error condition has occurred; only error states enabled in the U1EIE register can set

this bit

0= No unmasked error condition has occurred

DETACHIF: Detach Interrupt bit

1= A peripheral detachment has been detected by the module; Reset state must be cleared before

this bit can be reasserted

0= No peripheral detachment detected. Individual bits can only be cleared by writing a ‘1’ to the bit

position as part of a word write operation on the entire register. Using Boolean instructions or bit-

wise operations to write to a single bit position will cause all set bits at the moment of the write to

become cleared.

Note:

Individual bits can only be cleared by writing a ‘1’ to the bit position as part of a word write operation on the

entire register. Using Boolean instructions or bitwise operations to write to a single bit position will cause

all set bits at the moment of the write to become cleared.

 2010 Microchip Technology Inc.

DS39940D-page 225

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REGISTER 18-18: U1IE: USB INTERRUPT ENABLE REGISTER (ALL USB MODES)

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

bit 15

bit 8

R/W-0

TRNIE

R/W-0

SOFIE

R/W-0

URSTIE

DETACHIE

bit 0

STALLIE

ATTACHIE⁽¹⁾RESUMEIE

IDLEIE

UERRIE

bit 7

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15-8

bit 7

Unimplemented: Read as ‘0’

STALLIE: STALL Handshake Interrupt Enable bit

1= Interrupt is enabled

0= Interrupt is disabled

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

ATTACHIE: Peripheral Attach Interrupt bit (Host mode only)⁽¹⁾

1= Interrupt is enabled

0= Interrupt is disabled

RESUMEIE: Resume Interrupt bit

1= Interrupt is enabled

0= Interrupt is disabled

IDLEIE: Idle Detect Interrupt bit

1= Interrupt is enabled

0= Interrupt is disabled

TRNIE: Token Processing Complete Interrupt bit

1= Interrupt is enabled

0= Interrupt is disabled

SOFIE: Start-of-Frame Token Interrupt bit

1= Interrupt is enabled

0= Interrupt disabled

UERRIE: USB Error Condition Interrupt bit

1= Interrupt is enabled

0= Interrupt is disabled

URSTIE or DETACHIE: USB Reset Interrupt (Device mode) or USB Detach Interrupt (Host mode)

Enable bit

1= Interrupt is enabled

0= Interrupt is disabled

Note 1: Unimplemented in Device mode; read as ‘0’.

DS39940D-page 226

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REGISTER 18-19: U1EIR: USB ERROR INTERRUPT STATUS REGISTER

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

bit 15

bit 8

R/K-0, HS

BTSEF

U-0

—

R/K-0, HS

DMAEF

R/K-0, HS

BTOEF

R/K-0, HS

DFN8EF

R/K-0, HS

CRC16EF

R/K-0, HS

CRC5EF

EOFEF

R/K-0, HS

PIDEF

bit 7

bit 0

Legend:

U = Unimplemented bit, read as ‘0’

R = Readable bit

-n = Value at POR

K = Write ‘1’ to clear bit

‘1’ = Bit is set

HS = Hardware Settable bit

‘0’ = Bit is cleared

x = Bit is unknown

bit 15-8

bit 7

Unimplemented: Read as ‘0’

BTSEF: Bit Stuff Error Flag bit

1= Bit stuff error has been detected

0= No bit stuff error

bit 6

bit 5

Unimplemented: Read as ‘0’

DMAEF: DMA Error Flag bit

1= A USB DMA error condition detected; the data size indicated by the BD byte count field is less than

the number of received bytes. The received data is truncated.

0= No DMA error

bit 4

bit 3

bit 2

bit 1

BTOEF: Bus Turnaround Time-out Error Flag bit

1= Bus turnaround time-out has occurred

0= No bus turnaround time-out

DFN8EF: Data Field Size Error Flag bit

1= Data field was not an integral number of bytes

0= Data field was an integral number of bytes

CRC16EF: CRC16 Failure Flag bit

1= CRC16 failed

0= CRC16 passed

For Device mode:

CRC5EF: CRC5 Host Error Flag bit

1= Token packet rejected due to CRC5 error

0= Token packet accepted (no CRC5 error)

For Host mode:

EOFEF: End-Of-Frame Error Flag bit

1= End-Of-Frame error has occurred

0= End-Of-Frame interrupt disabled

bit 0

PIDEF: PID Check Failure Flag bit

1= PID check failed

0= PID check passed. Individual bits can only be cleared by writing a ‘1’ to the bit position as part of

a word write operation on the entire register. Using Boolean instructions or bitwise operations to

write to a single bit position will cause all set bits at the moment of the write to become cleared.

Note:

Individual bits can only be cleared by writing a ‘1’ to the bit position as part of a word write operation on the

entire register. Using Boolean instructions or bitwise operations to write to a single bit position will cause

all set bits at the moment of the write to become cleared.

 2010 Microchip Technology Inc.

DS39940D-page 227

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REGISTER 18-20: U1EIE: USB ERROR INTERRUPT ENABLE REGISTER

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

bit 15

bit 8

R/W-0

U-0

—

R/W-0

CRC5EE

EOFEE

R/W-0

PIDEE

BTSEE

DMAEE

BTOEE

DFN8EE

CRC16EE

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15-8

bit 7

Unimplemented: Read as ‘0’

BTSEE: Bit Stuff Error Interrupt Enable bit

1= Interrupt is enabled

0= Interrupt is disabled

bit 6

bit 5

Unimplemented: Read as ‘0’

DMAEE: DMA Error Interrupt Enable bit

1= Interrupt is enabled

0= Interrupt is disabled

bit 4

bit 3

bit 2

bit 1

BTOEE: Bus Turnaround Time-out Error Interrupt Enable bit

1= Interrupt is enabled

0= Interrupt is disabled

DFN8EE: Data Field Size Error Interrupt Enable bit

1= Interrupt is enabled

0= Interrupt is disabled

CRC16EE: CRC16 Failure Interrupt Enable bit

1= Interrupt is enabled

0= Interrupt is disabled

For Device mode:

CRC5EE: CRC5 Host Error Interrupt Enable bit

1= Interrupt is enabled

0= Interrupt is disabled

For Host mode:

EOFEE: End-of-Frame Error interrupt Enable bit

1= Interrupt is enabled

0= Interrupt is disabled

bit 0

PIDEE: PID Check Failure Interrupt Enable bit

1= Interrupt is enabled

0= Interrupt is disabled

DS39940D-page 228

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18.7.3

USB ENDPOINT MANAGEMENT REGISTERS

REGISTER 18-21: U1EPn: USB ENDPOINT CONTROL REGISTERS (n = 0 TO 15)

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

bit 15

bit 8

R/W-0

LSPD⁽¹⁾

R/W-0

U-0

—

R/W-0

(1)

RETRYDIS

EPCONDIS

EPRXEN

EPTXEN

EPSTALL

EPHSHK

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15-8

bit 7

Unimplemented: Read as ‘0’

LSPD: Low-Speed Direct Connection Enable bit (U1EP0 only)⁽¹⁾

1= Direct connection to a low-speed device is enabled

0= Direct connection to a low-speed device is disabled

bit 6

RETRYDIS: Retry Disable bit (U1EP0 only)⁽¹⁾

1= Retry NAK transactions are disabled

0= Retry NAK transactions are enabled; retry done in hardware

bit 5

bit 4

Unimplemented: Read as ‘0’

EPCONDIS: Bidirectional Endpoint Control bit

If EPTXEN and EPRXEN = 1:

1= Disable Endpoint n from Control transfers; only Tx and Rx transfers are allowed

0= Enable Endpoint n for Control (SETUP) transfers; Tx and Rx transfers also are allowed.

For all other combinations of EPTXEN and EPRXEN:

This bit is ignored.

bit 3

bit 2

bit 1

bit 0

EPRXEN: Endpoint Receive Enable bit

1= Endpoint n receive is enabled

0= Endpoint n receive is disabled

EPTXEN: Endpoint Transmit Enable bit

1= Endpoint n transmit is enabled

0= Endpoint n transmit is disabled

EPSTALL: Endpoint Stall Status bit

1= Endpoint n was stalled

0= Endpoint n was not stalled

EPHSHK: Endpoint Handshake Enable bit

1= Endpoint handshake is enabled

0= Endpoint handshake is disabled (typically used for isochronous endpoints)

Note 1: These bits are available only for U1EP0, and only in Host mode. For all other U1EPn registers, these bits

are always unimplemented and read as ‘0’.

 2010 Microchip Technology Inc.

DS39940D-page 229

PIC24FJ64GB004 FAMILY

18.7.4

USB VBUS POWER CONTROL REGISTER

REGISTER 18-22: U1PWMCON: USB VBUS PWM GENERATOR CONTROL REGISTER

R/W-0

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

R/W-0

PWMEN

PWMPOL

CNTEN

bit 15

bit 8

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15

PWMEN: PWM Enable bit

1= PWM generator is enabled

0= PWM generator is disabled; output is held in Reset state specified by PWMPOL

bit 14-10

bit 9

Unimplemented: Read as ‘0’

PWMPOL: PWM Polarity bit

1= PWM output is active-low and resets high

0= PWM output is active-high and resets low

bit 8

CNTEN: PWM Counter Enable bit

1= Counter is enabled

0= Counter is disabled

bit 7-0

Unimplemented: Read as ‘0’

DS39940D-page 230

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Key features of the PMP module include:

19.0 PARALLEL MASTER PORT

(PMP)

• Up to 16 Programmable Address Lines

• One Chip Select Line

Note:

This data sheet summarizes the features

• Programmable Strobe Options:

of this group of PIC24F devices. It is not

intended to be a comprehensive reference

source. For more information, refer to the

“PIC24F Family Reference Manual”,

Section 13. “Parallel Master Port

(PMP)” (DS39713).

- Individual Read and Write Strobes or;

- Read/Write Strobe with Enable Strobe

• Address Auto-Increment/Auto-Decrement

• Programmable Address/Data Multiplexing

• Programmable Polarity on Control Signals

• Legacy Parallel Slave Port Support

• Enhanced Parallel Slave Support:

- Address Support

The Parallel Master Port (PMP) module is a parallel,

8-bit I/O module, specifically designed to communicate

with a wide variety of parallel devices, such as commu-

nication peripherals, LCDs, external memory devices

and microcontrollers. Because the interface to parallel

peripherals varies significantly, the PMP is highly

configurable.

- 4-Byte Deep Auto-Incrementing Buffer

• Programmable Wait States

• Selectable Input Voltage Levels

Note:

A number of the pins for the PMP are not

present on PIC24FJ64GB0 family devices.

Refer to the specific device’s pinout to

determine which pins are available.

FIGURE 19-1:

PMP MODULE OVERVIEW

Address Bus

Data Bus

Control Lines

PIC24F

Parallel Master Port

PMA<0>

PMALL

PMA<1>

PMALH

Up to 11-Bit Address

(1)

PMA<10:2>

PMCS1

EEPROM

PMBE

PMRD

PMRD/PMWR

FIFO

Buffer

Microcontroller

LCD

PMWR

PMENB

PMD<7:0>

PMA<7:0>

PMA<15:8>

8-Bit Data

Note 1: PMA<10:2> bits are not available on 28-pin devices.

 2010 Microchip Technology Inc.

DS39940D-page 231

PIC24FJ64GB004 FAMILY

REGISTER 19-1: PMCON: PARALLEL PORT CONTROL REGISTER

R/W-0

U-0

—

R/W-0

PSIDL

R/W-0

PMPEN

ADRMUX1⁽¹⁾ADRMUX0⁽¹⁾

PTBEEN

PTWREN

PTRDEN

bit 15

bit 8

R/W-0

CSF1

R/W-0

CSF0

R/W-0⁽²⁾

ALP

U-0

—

R/W-0⁽²⁾

CS1P

R/W-0

BEP

R/W-0

WRSP

R/W-0

RDSP

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15

PMPEN: Parallel Master Port Enable bit

1= PMP is enabled

0= PMP is disabled, no off-chip access performed

bit 14

bit 13

Unimplemented: Read as ‘0’

PSIDL: Stop in Idle Mode bit

1= Discontinue module operation when device enters Idle mode

0= Continue module operation in Idle mode

bit 12-11

ADRMUX<1:0>: Address/Data Multiplexing Selection bits⁽¹⁾

11= Reserved

10= All 16 bits of address are multiplexed on PMD<7:0> pins

01= Lower 8 bits of address are multiplexed on PMD<7:0> pins; upper 3 bits are multiplexed on

PMA<10:8>

00= Address and data appear on separate pins

bit 10

bit 9

PTBEEN: Byte Enable Port Enable bit (16-Bit Master mode)

1= PMBE port is enabled

0= PMBE port is disabled

PTWREN: Write Enable Strobe Port Enable bit

1= PMWR/PMENB port is enabled

0= PMWR/PMENB port is disabled

bit 8

PTRDEN: Read/Write Strobe Port Enable bit

1= PMRD/PMWR port is enabled

0= PMRD/PMWR port is disabled

bit 7-6

CSF<1:0>: Chip Select Function bits

11= Reserved

10= PMCS1 functions as chip set

01= Reserved

00= Reserved

bit 5

ALP: Address Latch Polarity bit⁽²⁾

1= Active-high (PMALL and PMALH)

0= Active-low (PMALL and PMALH)

bit 4

bit 3

Unimplemented: Read as ‘0’

CS1P: Chip Select 1 Polarity bit⁽²⁾

1= Active-high (PMCS1/PMCS1)

0= Active-low (PMCS1/PMCS1)

Note 1: PMA<10:2> bits are not available on 28-pin devices.

2: These bits have no effect when their corresponding pins are used as address lines.

DS39940D-page 232

 2010 Microchip Technology Inc.

PIC24FJ64GB004 FAMILY

REGISTER 19-1: PMCON: PARALLEL PORT CONTROL REGISTER (CONTINUED)

bit 2

BEP: Byte Enable Polarity bit

1= Byte enable is active-high (PMBE)

0= Byte enable is active-low (PMBE)

bit 1

WRSP: Write Strobe Polarity bit

For Slave modes and Master Mode 2 (PMMODE<9:8> = 00,01,10):

1= Write strobe is active-high (PMWR)

0= Write strobe is active-low (PMWR)

For Master Mode 1 (PMMODE<9:8> = 11):

1= Enable strobe is active-high (PMENB)

0= Enable strobe is active-low (PMENB)

bit 0

RDSP: Read Strobe Polarity bit

For Slave modes and Master Mode 2 (PMMODE<9:8> = 00,01,10):

1= Read strobe is active-high (PMRD)

0= Read strobe is active-low (PMRD)

For Master Mode 1 (PMMODE<9:8> = 11):

1= Read/write strobe is active-high (PMRD/PMWR)

0= Read/write strobe is active-low (PMRD/PMWR)

Note 1: PMA<10:2> bits are not available on 28-pin devices.

2: These bits have no effect when their corresponding pins are used as address lines.

 2010 Microchip Technology Inc.

DS39940D-page 233

PIC24FJ64GB004 FAMILY

REGISTER 19-2: PMMODE: PARALLEL PORT MODE REGISTER

R-0

R/W-0

BUSY

IRQM1

IRQM0

INCM1

INCM0

MODE16

MODE1

MODE0

bit 15

bit 8

R/W-0

WAITB1⁽¹⁾

WAITB0⁽¹⁾

WAITM3

WAITM2

WAITM1

WAITM0

WAITE1⁽¹⁾

WAITE0⁽¹⁾

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15

BUSY: Busy bit (Master mode only)

1= Port is busy (not useful when the processor stall is active)

0= Port is not busy

bit 14-13

IRQM<1:0>: Interrupt Request Mode bits

11= Interrupt is generated when Read Buffer 3 is read or Write Buffer 3 is written (Buffered PSP

mode) or on a read or write operation when PMA<1:0> = 11(Addressable PSP mode only)

10= No interrupt is generated; processor stall activated

01= Interrupt is generated at the end of the read/write cycle

00= No interrupt is generated

bit 12-11

INCM<1:0>: Increment Mode bits

11= PSP read and write buffers auto-increment (Legacy PSP mode only)

10= Decrement ADDR<10:0> by 1 every read/write cycle

01= Increment ADDR<10:0> by 1 every read/write cycle

00= No increment or decrement of address

bit 10

MODE16: 8/16-Bit Mode bit

1= 16-bit mode: Data register is 16 bits; a read or write to the Data register invokes two 8-bit transfers

0= 8-bit mode: Data register is 8 bits; a read or write to the Data register invokes one 8-bit transfer

bit 9-8

MODE<1:0>: Parallel Port Mode Select bits

11= Master Mode 1 (PMCS1, PMRD/PMWR, PMENB, PMBE, PMA<x:0> and PMD<7:0>)

10= Master Mode 2 (PMCS1, PMRD, PMWR, PMBE, PMA<x:0> and PMD<7:0>)

01= Enhanced PSP control signals (PMRD, PMWR, PMCS1, PMD<7:0> and PMA<1:0>)

00= Legacy Parallel Slave Port control signals (PMRD, PMWR, PMCS1 and PMD<7:0>)

bit 7-6

bit 5-2

bit 1-0

WAITB<1:0>: Data Setup to Read/Write Wait State Configuration bits⁽¹⁾

11= Data wait of 4 TCY; multiplexed address phase of 4 TCY

10= Data wait of 3 TCY; multiplexed address phase of 3 TCY

01= Data wait of 2 TCY; multiplexed address phase of 2 TCY

00= Data wait of 1 TCY; multiplexed address phase of 1 TCY

WAITM<3:0>: Read to Byte Enable Strobe Wait State Configuration bits

1111= Wait of additional 15 TCY

...

0001= Wait of additional 1 TCY

0000= No additional wait cycles (operation forced into one TCY)

WAITE<1:0>: Data Hold After Strobe Wait State Configuration bits⁽¹⁾

11= Wait of 4 TCY

10= Wait of 3 TCY

01= Wait of 2 TCY

00= Wait of 1 TCY

Note 1: WAITB and WAITE bits are ignored whenever WAITM<3:0> = 0000.

DS39940D-page 234

 2010 Microchip Technology Inc.

PIC24FJ64GB004 FAMILY

REGISTER 19-3: PMADDR: PARALLEL PORT ADDRESS REGISTER

U-0

—

R/W-0

CS1

U-0

—

U-0

—

U-0

—

R/W-0

ADDR10⁽¹⁾

R/W-0

ADDR9⁽¹⁾

R/W-0

ADDR8⁽¹⁾

bit 15

bit 8

R/W-0

ADDR7⁽¹⁾

ADDR6⁽¹⁾

ADDR5⁽¹⁾

ADDR4⁽¹⁾

ADDR3⁽¹⁾

ADDR2⁽¹⁾

ADDR1⁽¹⁾

ADDR0⁽¹⁾

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15

bit 14

Unimplemented: Read as ‘0’

CS1: Chip Select 1 bit

1= Chip Select 1 is active

0= Chip Select 1 is inactive

bit 13-11

bit 10-0

Unimplemented: Read as ‘0’

ADDR<10:0>: Parallel Port Destination Address bits⁽¹⁾

Note 1: PMA<10:2> bits are not available on 28-pin devices.

REGISTER 19-4: PMAEN: PARALLEL PORT ENABLE REGISTER

U-0

—

R/W-0

U-0

—

U-0

—

U-0

—

R/W-0

PTEN10⁽¹⁾

R/W-0

PTEN9⁽¹⁾

R/W-0

PTEN8⁽¹⁾

PTEN14

bit 15

bit 8

R/W-0

PTEN7⁽¹⁾

PTEN6⁽¹⁾

PTEN5⁽¹⁾

PTEN4⁽¹⁾

PTEN3⁽¹⁾

PTEN2⁽¹⁾

PTEN1

PTEN0

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

-n = Value at POR

bit 15

bit 14

Unimplemented: Read as ‘0’

PTEN14: PMCS1 Strobe Enable bit

1= PMCS1 functions as chip select

0= PMCS1 pin functions as port I/O

bit 13-11

bit 10-2

Unimplemented: Read as ‘0’

PTEN<10:2>: PMP Address Port Enable bits⁽¹⁾

1= PMA<10:2> function as PMP address lines

0= PMA<10:2> function as port I/O

bit 1-0

PTEN<1:0>: PMALH/PMALL Strobe Enable bits

1= PMA1 and PMA0 function as either PMA<1:0> or PMALH and PMALL

0= PMA1 and PMA0 pads function as port I/O

Note 1: PMA<10:2> bits are not available on 28-pin devices.

 2010 Microchip Technology Inc.

DS39940D-page 235

PIC24FJ64GB004 FAMILY

REGISTER 19-5: PMSTAT: PARALLEL PORT STATUS REGISTER

R-0

IBF

R/W-0, HS

IBOV

U-0

—

U-0

—

R-0

IB3F

IB2F

IB1F

IB0F

bit 15

bit 8

R-1

R/W-0, HS

OBUF

U-0

—

U-0

—

R-1

OBE

OB3E

OB2E

OB1E

OB0E

bit 0

bit 7

Legend:

HS = Hardware Settable bit

W = Writable bit

R = Readable bit

-n = Value at POR

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

‘1’ = Bit is set

bit 15

bit 14

IBF: Input Buffer Full Status bit

1= All writable input buffer registers are full

0= Some or all of the writable input buffer registers are empty

IBOV: Input Buffer Overflow Status bit

1= A write attempt to a full input byte register has occurred (must be cleared in software)

0= No overflow has occurred

bit 13-12

bit 11-8

Unimplemented: Read as ‘0’

IB3F:IB0F Input Buffer x Status Full bits

1= Input buffer contains data that has not been read (reading buffer will clear this bit)

0= Input buffer does not contain any unread data

bit 7

bit 6

OBE: Output Buffer Empty Status bit

1= All readable output buffer registers are empty

0= Some or all of the readable output buffer registers are full

OBUF: Output Buffer Underflow Status bits

1= A read occurred from an empty output byte register (must be cleared in software)

0= No underflow occurred

bit 5-4

bit 3-0

Unimplemented: Read as ‘0’

OB3E:OB0E Output Buffer x Status Empty bits

1= Output buffer is empty (writing data to the buffer will clear this bit)

0= Output buffer contains data that has not been transmitted

DS39940D-page 236

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REGISTER 19-6: PADCFG1: PAD CONFIGURATION CONTROL REGISTER

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

bit 15

bit 8

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

R/W-0

RTSECSEL1⁽¹⁾RTSECSEL0⁽¹⁾

PMPTTL

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15-3

bit 2-1

Unimplemented: Read as ‘0’

RTSECSEL<1:0>: RTCC Seconds Clock Output Select bits⁽¹⁾

11= Reserved; do not use

10= RTCC source clock is selected for the RTCC pin (clock can be LPRC or SOSC, depending on the

setting of the Flash Configuration bit, RTCOSC (CW4<5>))

01= RTCC seconds clock is selected for the RTCC pin

00= RTCC alarm pulse is selected for the RTCC pin

bit 0

PMPTTL: PMP Module TTL Input Buffer Select bit

1= PMP module uses TTL input buffers

0= PMP module uses Schmitt Trigger input buffers

Note 1: To enable the actual RTCC output, the RTCOE (RCFGCAL<10>) bit needs to be set.

 2010 Microchip Technology Inc.

DS39940D-page 237

PIC24FJ64GB004 FAMILY

FIGURE 19-2:

LEGACY PARALLEL SLAVE PORT EXAMPLE

Address Bus

Data Bus

PIC24F Slave

Master

PMD<7:0>

Control Lines

PMCS1

PMRD

PMWR

PMCS1

PMRD

PMWR

FIGURE 19-3:

ADDRESSABLE PARALLEL SLAVE PORT EXAMPLE

PIC24F Slave

Master

PMA<1:0>

Write

Address

Decode

Read

Address

Decode

PMD<7:0>

PMDOUT1L (0)

PMDIN1L (0)

PMDIN1H (1)

PMDIN2L (2)

PMDIN2H (3)

PMCS1

PMRD

PMWR

PMCS1

PMRD

PMWR

PMDOUT1H (1)

PMDOUT2L (2)

PMDOUT2H (3)

Address Bus

Data Bus

Control Lines

TABLE 19-1: SLAVE MODE ADDRESS RESOLUTION

PMA<1:0>

Output Register (Buffer)

Input Register (Buffer)

00

01

10

11

PMDOUT1<7:0> (0)

PMDOUT1<15:8> (1)

PMDOUT2<7:0> (2)

PMDOUT2<15:8> (3)

PMDIN1<7:0> (0)

PMDIN1<15:8> (1)

PMDIN2<7:0> (2)

PMDIN2<15:8> (3)

FIGURE 19-4:

MASTER MODE, DEMULTIPLEXED ADDRESSING (SEPARATE READ AND

WRITE STROBES, SINGLE CHIP SELECT)

PIC24F

PMA<10:0>

PMD<7:0>

PMCS1

PMRD

PMWR

Address Bus

Data Bus

Control Lines

DS39940D-page 238

 2010 Microchip Technology Inc.

PIC24FJ64GB004 FAMILY

FIGURE 19-5:

FIGURE 19-6:

FIGURE 19-7:

MASTER MODE, PARTIALLY MULTIPLEXED ADDRESSING (SEPARATE READ

AND WRITE STROBES, SINGLE CHIP SELECT)

PIC24F

PMA<10:8>

PMD<7:0>

PMA<7:0>

PMCS1

PMALL

PMRD

PMWR

Address Bus

Multiplexed

Data and

Address Bus

Control Lines

MASTER MODE, FULLY MULTIPLEXED ADDRESSING (SEPARATE READ AND

WRITE STROBES, SINGLE CHIP SELECT)

PMD<7:0>

PMA<7:0>

PMA<15:8>

PIC24F

PMCS1

PMALL

PMALH

PMRD

PMWR

Multiplexed

Data and

Address Bus

Control Lines

EXAMPLE OF A MULTIPLEXED ADDRESSING APPLICATION

PIC24F

PMD<7:0>

PMALL

A<7:0>

373

A<15:0>

D<7:0>

CE

A<15:8>

373

OE

WR

PMALH

PMCS1

PMRD

PMWR

Address Bus

Data Bus

Control Lines

FIGURE 19-8:

EXAMPLE OF A PARTIALLY MULTIPLEXED ADDRESSING APPLICATION

PIC24F

A<7:0>

373

PMD<7:0>

PMALL

A<10:0>

D<7:0>

CE

A<10:8>

PMA<10:8>

OE

WR

Address Bus

Data Bus

PMCS1

PMRD

PMWR

Control Lines

 2010 Microchip Technology Inc.

DS39940D-page 239

PIC24FJ64GB004 FAMILY

FIGURE 19-9:

EXAMPLE OF AN 8-BIT MULTIPLEXED ADDRESS AND DATA APPLICATION

PIC24F

PMD<7:0>

Parallel Peripheral

AD<7:0>

PMALL

PMCS1

PMRD

ALE

CS

Address Bus

Data Bus

RD

PMWR

WR

Control Lines

FIGURE 19-10:

PARALLEL EEPROM EXAMPLE (UP TO 11-BIT ADDRESS, 8-BIT DATA)

PIC24F

Parallel EEPROM

PMA<n:0>

A<n:0>

PMD<7:0>

D<7:0>

PMCS1

PMRD

PMWR

CE

OE

WR

Address Bus

Data Bus

Control Lines

FIGURE 19-11:

PARALLEL EEPROM EXAMPLE (UP TO 11-BIT ADDRESS, 16-BIT DATA)

Parallel EEPROM

PIC24F

A<n:1>

D<7:0>

PMA<n:0>

PMD<7:0>

PMBE

PMCS1

PMRD

A0

CE

OE

WR

Address Bus

Data Bus

PMWR

Control Lines

FIGURE 19-12:

LCD CONTROL EXAMPLE (BYTE MODE OPERATION)

PIC24F

LCD Controller

PMD<7:0>

PMA0

D<7:0>

RS

PMRD/PMWR

PMCS1

R/W

E

Address Bus

Data Bus

Control Lines

DS39940D-page 240

 2010 Microchip Technology Inc.

PIC24FJ64GB004 FAMILY

• Alarm-configurable for half a second, one second,

10 seconds, one minute, 10 minutes, one hour,

one day, one week, one month or one year

20.0 REAL-TIME CLOCK AND

CALENDAR (RTCC)

• Alarm repeat with decrementing counter

• Alarm with indefinite repeat chime

Note:

This data sheet summarizes the features

of this group of PIC24F devices. It is not

intended to be a comprehensive reference

source. For more information, refer to the

“PIC24F Family Reference Manual”,

Section 29. “Real-Time Clock and

Calendar (RTCC)” (DS39696).

• Year 2000 to 2099 leap year correction

• BCD format for smaller software overhead

• Optimized for long-term battery operation

• User calibration of the 32.768 kHz clock

crystal/32K INTRC frequency with periodic

auto-adjust

The RTCC provides the user with a Real-Time Clock

and Calendar (RTCC) function that can be calibrated.

Key features of the RTCC module are:

20.1 RTCC Source Clock

• Operates in Deep Sleep mode

• Selectable clock source

The user can select between the SOSC crystal oscillator

or the LPRC Low-Power Internal RC Oscillator as the

clock reference for the RTCC module. This is configured

using the RTCOSC (CW4<5>) Configuration bit. This

gives the user an option to trade off system cost,

accuracy and power consumption, based on the overall

system needs.

• Provides hours, minutes and seconds using

24-hour format

• Visibility of one half second period

• Provides calendar – weekday, date, month and

year

The SOSC and RTCC will both remain running while

the device is held in Reset with MCLR and will continue

running after MCLR is released.

FIGURE 20-1:

RTCC BLOCK DIAGRAM

RTCC Clock Domain

CPU Clock Domain

Input from

SOSC/LPRC

Oscillator

RCFGCAL

RTCC Prescalers

0.5 Sec

ALCFGRPT

YEAR

MTHDY

WKDYHR

MINSEC

RTCC Timer

1 Sec

RTCVAL

Alarm

Event

Comparator

Alarm Registers with Masks

Repeat Counter

ALMTHDY

ALWDHR

ALMINSEC

ALRMVAL

RTSECSEL<1:0>

01

RTCC

Interrupt

RTCC Interrupt Logic

Alarm Pulse

00

10

RTCC

Clock Source

RTCOE

 2010 Microchip Technology Inc.

DS39940D-page 241

PIC24FJ64GB004 FAMILY

TABLE 20-2: ALRMVAL REGISTER

20.2 RTCC Module Registers

MAPPING

The RTCC module registers are organized as three

categories:

Alarm Value Register Window

ALRMPTR

<1:0>

• RTCC Control Registers

• RTCC Value Registers

• Alarm Value Registers

ALRMVAL<15:8> ALRMVAL<7:0>

00

01

10

11

ALRMMIN

ALRMWD

ALRMMNTH

—

ALRMSEC

ALRMHR

ALRMDAY

—

20.2.1

REGISTER MAPPING

To limit the register interface, the RTCC Timer and

Alarm Time registers are accessed through

corresponding register pointers. The RTCC Value

register window (RTCVALH and RTCVALL) uses the

RTCPTR bits (RCFGCAL<9:8>) to select the desired

Timer register pair (see Table 20-1).

Considering that the 16-bit core does not distinguish

between 8-bit and 16-bit read operations, the user must

be aware that when reading either the ALRMVALH or

ALRMVALL bytes, the ALRMPTR<1:0> value will be

decremented. The same applies to the RTCVALH or

RTCVALL bytes with the RTCPTR<1:0> being

decremented.

By writing to the RTCVALH byte, the RTCC Pointer

value, RTCPTR<1:0> bits, decrements by one until

they reach ‘00’. After they reach ‘00’, the MINUTES

and SECONDS value will be accessible through

RTCVALH and RTCVALL until the pointer value is

manually changed.

Note:

This only applies to read operations and

not write operations.

20.2.2

WRITE LOCK

TABLE 20-1: RTCVAL REGISTER MAPPING

In order to perform a write to any of the RTCC Timer

registers, the RTCWREN bit (RCFGCAL<13>) must be

set (refer to Example 20-1).

RTCC Value Register Window

RTCPTR<1:0>

RTCVAL<15:8> RTCVAL<7:0>

Note:

To avoid accidental writes to the timer, it is

recommended that the RTCWREN bit

(RCFGCAL<13>) is kept clear at any

other time. For the RTCWREN bit to be

set, there is only one instruction cycle time

window allowed between the 55h/AA

sequence and the setting of RTCWREN;

therefore, it is recommended that code

follow the procedure in Example 20-1.

00

01

10

11

MINUTES

WEEKDAY

MONTH

—

SECONDS

HOURS

DAY

YEAR

The Alarm Value register window (ALRMVALH and

ALRMVALL) uses the ALRMPTR bits

(ALCFGRPT<9:8>) to select the desired Alarm register

pair (see Table 20-2).

20.2.3

SELECTING RTCC CLOCK SOURCE

By writing to the ALRMVALH byte, the Alarm Pointer

value, ALRMPTR<1:0> bits, decrements by one until

they reach ‘00’. Once they reach ‘00’, the ALRMMIN

and ALRMSEC value will be accessible through

ALRMVALH and ALRMVALL until the pointer value is

manually changed.

The clock source for the RTCC module can be selected

using the Flash Configuration bit, RTCOSC (CW4<5>).

When the bit is set to ‘1’, the Secondary Oscillator

(SOSC) is used as the reference clock, and when the

bit is ‘0’, LPRC is used as the reference clock.

EXAMPLE 20-1:

SETTING THE RTCWREN BIT

asm volatile(“push w7”);

asm volatile(“push w8”);

asm volatile(“disi #5”);

asm volatile(“mov #0x55, w7”);

asm volatile(“mov w7, _NVMKEY”);

asm volatile(“mov #0xAA, w8”);

asm volatile(“mov w8, _NVMKEY”);

asm volatile(“bset _RCFGCAL, #13”);

asm volatile(“pop w8”);

//set the RTCWREN bit

asm volatile(“pop w7”);

DS39940D-page 242

 2010 Microchip Technology Inc.

PIC24FJ64GB004 FAMILY

20.2.4

RTCC CONTROL REGISTERS

)

REGISTER 20-1: RCFGCAL: RTCC CALIBRATION AND CONFIGURATION REGISTER⁽¹

R/W-0

RTCEN⁽²⁾

U-0

—

R/W-0

R-0, HSC

RTCSYNC HALFSEC⁽³⁾

R-0, HSC

R/W-0

RTCWREN

RTCOE

RTCPTR1

RTCPTR0

bit 15

bit 8

R/W-0

CAL7

R/W-0

CAL6

R/W-0

CAL5

R/W-0

CAL4

R/W-0

CAL3

R/W-0

CAL2

R/W-0

CAL1

R/W-0

CAL0

bit 7

bit 0

Legend:

HSC = Hardware Settable/Clearable bit

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15

RTCEN: RTCC Enable bit⁽²⁾

1= RTCC module is enabled

0= RTCC module is disabled

bit 14

bit 13

Unimplemented: Read as ‘0’

RTCWREN: RTCC Value Registers Write Enable bit

1= RTCVALH and RTCVALL registers can be written to by the user

0= RTCVALH and RTCVALL registers are locked out from being written to by the user

bit 12

RTCSYNC: RTCC Value Registers Read Synchronization bit

1= RTCVALH, RTCVALL and ALCFGRPT registers can change while reading due to a rollover ripple

resulting in an invalid data read. If the register is read twice and results in the same data, the data

can be assumed to be valid.

0= RTCVALH, RTCVALL or ALCFGRPT registers can be read without concern over a rollover ripple

bit 11

bit 10

bit 9-8

HALFSEC: Half Second Status bit⁽³⁾

1= Second half period of a second

0= First half period of a second

RTCOE: RTCC Output Enable bit

1= RTCC output is enabled

0= RTCC output is disabled

RTCPTR<1:0>: RTCC Value Register Window Pointer bits

Points to the corresponding RTCC Value registers when reading the RTCVALH and RTCVALL registers.

The RTCPTR<1:0> value decrements on every read or write of RTCVALH until it reaches ‘00’.

RTCVAL<15:8>:

00= MINUTES

01= WEEKDAY

10= MONTH

11= Reserved

RTCVAL<7:0>:

00= SECONDS

01= HOURS

10= DAY

11= YEAR

Note 1: The RCFGCAL register is only affected by a POR.

2: A write to the RTCEN bit is only allowed when RTCWREN = 1.

3: This bit is read-only; it is cleared to ‘0’ on a write to the lower half of the MINSEC register.

 2010 Microchip Technology Inc.

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REGISTER 20-1: RCFGCAL: RTCC CALIBRATION AND CONFIGURATION REGISTER⁽¹⁾(CONTINUED)

bit 7-0

CAL<7:0>: RTC Drift Calibration bits

01111111= Maximum positive adjustment; adds 508 RTC clock pulses every one minute

.

01111111= Minimum positive adjustment; adds 4 RTC clock pulses every one minute

00000000= No adjustment

11111111= Minimum negative adjustment; subtracts 4 RTC clock pulses every one minute

.

10000000= Maximum negative adjustment; subtracts 512 RTC clock pulses every one minute

Note 1: The RCFGCAL register is only affected by a POR.

2: A write to the RTCEN bit is only allowed when RTCWREN = 1.

3: This bit is read-only; it is cleared to ‘0’ on a write to the lower half of the MINSEC register.

REGISTER 20-2: PADCFG1: PAD CONFIGURATION CONTROL REGISTER

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

bit 15

bit 8

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

R/W-0

RTSECSEL1⁽¹⁾RTSECSEL0⁽¹⁾PMPTTL

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15-3

bit 2-1

Unimplemented: Read as ‘0’

RTSECSEL<1:0>: RTCC Seconds Clock Output Select bits⁽¹⁾

11= Reserved; do not use

10= RTCC source clock is selected for the RTCC pin (clock can be LPRC or SOSC, depending on the

setting of the RTCOSC bit (CW4<5>))

01= RTCC seconds clock is selected for the RTCC pin

00= RTCC alarm pulse is selected for the RTCC pin

bit 0

PMPTTL: PMP Module TTL Input Buffer Select bit

1= PMP module uses TTL input buffers

0= PMP module uses Schmitt Trigger input buffers

Note 1: To enable the actual RTCC output, the RTCOE (RCFGCAL<10>) bit needs to be set.

DS39940D-page 244

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REGISTER 20-3: ALCFGRPT: ALARM CONFIGURATION REGISTER

R/W-0

ALRMEN

CHIME

AMASK3

AMASK2

AMASK1

AMASK0

ALRMPTR1 ALRMPTR0

bit 8

bit 15

R/W-0

ARPT7

ARPT6

ARPT5

ARPT4

ARPT3

ARPT2

ARPT1

ARPT0

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

-n = Value at POR

bit 15

ALRMEN: Alarm Enable bit

1= Alarm is enabled (cleared automatically after an alarm event whenever ARPT<7:0> = 00h and

CHIME = 0)

0= Alarm is disabled

bit 14

CHIME: Chime Enable bit

1= Chime is enabled; ARPT<7:0> bits are allowed to roll over from 00h to FFh

0= Chime is disabled; ARPT<7:0> bits stop once they reach 00h

bit 13-10

AMASK<3:0>: Alarm Mask Configuration bits

0000= Every half second

0001= Every second

0010= Every 10 seconds

0011= Every minute

0100= Every 10 minutes

0101= Every hour

0110= Once a day

0111= Once a week

1000= Once a month

1001= Once a year (except when configured for February 29^th, once every 4 years)

101x= Reserved; do not use

11xx= Reserved; do not use

bit 9-8

ALRMPTR<1:0>: Alarm Value Register Window Pointer bits

Points to the corresponding Alarm Value registers when reading the ALRMVALH and ALRMVALL regis-

ters. The ALRMPTR<1:0> value decrements on every read or write of ALRMVALH until it reaches ‘00’.

ALRMVAL<15:8>:

00= ALRMMIN

01= ALRMWD

10= ALRMMNTH

11= Unimplemented

ALRMVAL<7:0>:

00= ALRMSEC

01= ALRMHR

10= ALRMDAY

11= Unimplemented

bit 7-0

ARPT<7:0>: Alarm Repeat Counter Value bits

11111111= Alarm will repeat 255 more times

.

00000000= Alarm will not repeat

The counter decrements on any alarm event; it is prevented from rolling over from 00h to FFh unless

CHIME = 1.

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20.2.5

RTCVAL REGISTER MAPPINGS

REGISTER 20-4: YEAR: YEAR VALUE REGISTER⁽¹⁾

U-0, HSC

—

U-0, HSC

—

U-0, HSC

—

U-0, HSC

—

U-0, HSC

—

U-0, HSC

—

U-0, HSC

—

U-0, HSC

—

bit 15

bit 8

R/W-x, HSC R/W-x, HSC R/W-x, HSC R/W-x, HSC R/W-x, HSC R/W-x, HSC R/W-x, HSC R/W-x, HSC

YRTEN3 YRTEN2 YRTEN1 YRTEN0 YRONE3 YRONE2 YRONE1 YRONE0

bit 7 bit 0

Legend:

HSC = Hardware Settable/Clearable bit

R = Readable bit

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

-n = Value at POR

bit 15-8

bit 7-4

Unimplemented: Read as ‘0’

YRTEN<3:0>: Binary Coded Decimal Value of Year’s Tens Digit bits

Contains a value from 0 to 9.

bit 3-0

YRONE<3:0>: Binary Coded Decimal Value of Year’s Ones Digit bits

Contains a value from 0 to 9.

Note 1: A write to the YEAR register is only allowed when RTCWREN = 1.

REGISTER 20-5: MTHDY: MONTH AND DAY VALUE REGISTER⁽¹⁾

U-0, HSC

—

U-0, HSC

—

U-0, HSC

—

R/W-x, HSC R/W-x, HSC R/W-x, HSC R/W-x, HSC R/W-x, HSC

MTHTEN0 MTHONE3 MTHONE2 MTHONE1 MTHONE0

bit 8

bit 15

U-0, HSC

—

U-0, HSC

—

R/W-x, HSC R/W-x, HSC R/W-x, HSC R/W-x, HSC R/W-x, HSC R/W-x, HSC

DAYTEN1 DAYTEN0 DAYONE3 DAYONE2 DAYONE1 DAYONE0

bit 0

bit 7

Legend:

HSC = Hardware Settable/Clearable bit

R = Readable bit

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

-n = Value at POR

bit 15-13

bit 12

Unimplemented: Read as ‘0’

MTHTEN0: Binary Coded Decimal Value of Month’s Tens Digit bit

Contains a value of ‘0’ or ‘1’.

bit 11-8

MTHONE<3:0>: Binary Coded Decimal Value of Month’s Ones Digit bits

Contains a value from 0 to 9.

bit 7-6

bit 5-4

Unimplemented: Read as ‘0’

DAYTEN<1:0>: Binary Coded Decimal Value of Day’s Tens Digit bits

Contains a value from 0 to 3.

bit 3-0

DAYONE<3:0>: Binary Coded Decimal Value of Day’s Ones Digit bits

Contains a value from 0 to 9.

Note 1: A write to this register is only allowed when RTCWREN = 1.

DS39940D-page 246

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REGISTER 20-6: WKDYHR: WEEKDAY AND HOURS VALUE REGISTER⁽¹⁾

U-0, HSC

—

U-0, HSC

—

U-0, HSC

—

U-0, HSC

—

U-0, HSC

—

R/W-x, HSC R/W-x, HSC R/W-x, HSC

WDAY2 WDAY1 WDAY0

bit 8

bit 15

U-0, HSC

—

U-0, HSC

—

R/W-x, HSC R/W-x, HSC R/W-x, HSC R/W-x, HSC R/W-x, HSC R/W-x, HSC

HRTEN1 HRTEN0 HRONE3 HRONE2 HRONE1 HRONE0

bit 0

bit 7

Legend:

HSC = Hardware Settable/Clearable bit

R = Readable bit

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

-n = Value at POR

bit 15-11

bit 10-8

Unimplemented: Read as ‘0’

WDAY<2:0>: Binary Coded Decimal Value of Weekday Digit bits

Contains a value from 0 to 6.

bit 7-6

bit 5-4

Unimplemented: Read as ‘0’

HRTEN<1:0>: Binary Coded Decimal Value of Hour’s Tens Digit bits

Contains a value from 0 to 2.

bit 3-0

HRONE<3:0>: Binary Coded Decimal Value of Hour’s Ones Digit bits

Contains a value from 0 to 9.

Note 1: A write to this register is only allowed when RTCWREN = 1.

REGISTER 20-7: MINSEC: MINUTES AND SECONDS VALUE REGISTER

U-0, HSC

—

R/W-x, HSC R/W-x, HSC R/W-x, HSC R/W-x, HSC R/W-x, HSC R/W-x, HSC R/W-x, HSC

MINTEN2 MINTEN1 MINTEN0 MINONE3 MINONE2 MINONE1 MINONE0

bit 8

bit 15

U-0, HSC

—

R/W-x, HSC R/W-x, HSC R/W-x, HSC R/W-x, HSC R/W-x, HSC R/W-x, HSC R/W-x, HSC

SECTEN2 SECTEN1 SECTEN0 SECONE3 SECONE2 SECONE1 SECONE0

bit 0

bit 7

Legend:

HSC = Hardware Settable/Clearable bit

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15

Unimplemented: Read as ‘0’

bit 14-12

MINTEN<2:0>: Binary Coded Decimal Value of Minute’s Tens Digit bits

Contains a value from 0 to 5.

bit 11-8

MINONE<3:0>: Binary Coded Decimal Value of Minute’s Ones Digit bits

Contains a value from 0 to 9.

bit 7

Unimplemented: Read as ‘0’

bit 6-4

SECTEN<2:0>: Binary Coded Decimal Value of Second’s Tens Digit bits

Contains a value from 0 to 5.

bit 3-0

SECONE<3:0>: Binary Coded Decimal Value of Second’s Ones Digit bits

Contains a value from 0 to 9.

 2010 Microchip Technology Inc.

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20.2.6

ALRMVAL REGISTER MAPPINGS

REGISTER 20-8: ALMTHDY: ALARM MONTH AND DAY VALUE REGISTER⁽¹⁾

U-0

—

U-0

—

U-0

—

R/W-x

MTHTEN0

MTHONE3

MTHONE2

MTHONE1

MTHONE0

bit 15

bit 8

U-0

—

U-0

—

R/W-x

DAYTEN1

DAYTEN0

DAYONE3

DAYONE2

DAYONE1

DAYONE0

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15-13

bit 12

Unimplemented: Read as ‘0’

MTHTEN0: Binary Coded Decimal Value of Month’s Tens Digit bit

Contains a value of ‘0’ or ‘1’.

bit 11-8

MTHONE<3:0>: Binary Coded Decimal Value of Month’s Ones Digit bits

Contains a value from 0 to 9.

bit 7-6

bit 5-4

Unimplemented: Read as ‘0’

DAYTEN<1:0>: Binary Coded Decimal Value of Day’s Tens Digit bits

Contains a value from 0 to 3.

bit 3-0

DAYONE<3:0>: Binary Coded Decimal Value of Day’s Ones Digit bits

Contains a value from 0 to 9.

Note 1: A write to this register is only allowed when RTCWREN = 1.

REGISTER 20-9: ALWDHR: ALARM WEEKDAY AND HOURS VALUE REGISTER⁽¹⁾

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

R/W-x

WDAY2

WDAY1

WDAY0

bit 15

bit 8

U-0

—

U-0

—

R/W-x

HRTEN1

HRTEN0

HRONE3

HRONE2

HRONE1

HRONE0

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15-11

bit 10-8

Unimplemented: Read as ‘0’

WDAY<2:0>: Binary Coded Decimal Value of Weekday Digit bits

Contains a value from 0 to 6.

bit 7-6

bit 5-4

Unimplemented: Read as ‘0’

HRTEN<1:0>: Binary Coded Decimal Value of Hour’s Tens Digit bits

Contains a value from 0 to 2.

bit 3-0

HRONE<3:0>: Binary Coded Decimal Value of Hour’s Ones Digit bits

Contains a value from 0 to 9.

Note 1: A write to this register is only allowed when RTCWREN = 1.

DS39940D-page 248

 2010 Microchip Technology Inc.

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REGISTER 20-10: ALMINSEC: ALARM MINUTES AND SECONDS VALUE REGISTER

U-0

—

R/W-x

MINTEN2

MINTEN1

MINTEN0

MINONE3

MINONE2

MINONE1

MINONE0

bit 15

bit 8

U-0

—

R/W-x

SECTEN2

SECTEN1

SECTEN0

SECONE3

SECONE2

SECONE1

SECONE0

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15

Unimplemented: Read as ‘0’

bit 14-12

MINTEN<2:0>: Binary Coded Decimal Value of Minute’s Tens Digit bits

Contains a value from 0 to 5.

bit 11-8

MINONE<3:0>: Binary Coded Decimal Value of Minute’s Ones Digit bits

Contains a value from 0 to 9.

bit 7

Unimplemented: Read as ‘0’

bit 6-4

SECTEN<2:0>: Binary Coded Decimal Value of Second’s Tens Digit bits

Contains a value from 0 to 5.

bit 3-0

SECONE<3:0>: Binary Coded Decimal Value of Second’s Ones Digit bits

Contains a value from 0 to 9.

 2010 Microchip Technology Inc.

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20.4.1

CONFIGURING THE ALARM

20.3 Calibration

The alarm feature is enabled using the ALRMEN bit.

This bit is cleared when an alarm is issued. Writes to

ALRMVAL should only take place when ALRMEN = 0.

The real-time crystal input can be calibrated using the

periodic auto-adjust feature. When calibrated, the

RTCC can provide an error of less than 3 seconds per

month. This is accomplished by finding the number of

error clock pulses and storing the value into the lower

half of the RCFGCAL register. The 8-bit signed value

loaded into the lower half of RCFGCAL is multiplied by

four and will either be added or subtracted from the

RTCC timer, once every minute. Refer to the steps

below for RTCC calibration:

As displayed in Figure 20-2, the interval selection of the

alarm is configured through the AMASK bits

(ALCFGRPT<13:10>). These bits determine which and

how many digits of the alarm must match the clock

value for the alarm to occur.

The alarm can also be configured to repeat based on a

preconfigured interval. The amount of times this

occurs, once the alarm is enabled, is stored in the

ARPT<7:0> bits (ALCFGRPT<7:0>). When the value

of the ARPT bits equals 00h and the CHIME bit

(ALCFGRPT<14>) is cleared, the repeat function is

disabled and only a single alarm will occur. The alarm

can be repeated up to 255 times by loading

ARPT<7:0> with FFh.

1. Using another timer resource on the device; the

user must find the error of the 32.768 kHz crystal.

2. Once the error is known, it must be converted to

the number of error clock pulses per minute.

3. a) If the oscillator is faster than ideal (negative

result from step 2), the RCFGCAL register value

must be negative. This causes the specified

number of clock pulses to be subtracted from

the timer counter, once every minute.

After each alarm is issued, the value of the ARPT bits

is decremented by one. Once the value has reached

00h, the alarm will be issued one last time, after which,

the ALRMEN bit will be cleared automatically and the

alarm will turn off.

b) If the oscillator is slower than ideal (positive

result from step 2), the RCFGCAL register value

must be positive. This causes the specified

number of clock pulses to be subtracted from

the timer counter, once every minute.

Indefinite repetition of the alarm can occur if the

CHIME bit = 1. Instead of the alarm being disabled

when the value of the ARPT bits reaches 00h, it rolls

over to FFh and continues counting indefinitely while

CHIME is set.

Divide the number of error clocks per minute by 4 to get

the correct calibration value and load the RCFGCAL

register with the correct value. (Each 1-bit increment in

the calibration adds or subtracts 4 pulses.)

20.4.2

ALARM INTERRUPT

EQUATION 20-1:

At every alarm event, an interrupt is generated. In

addition, an alarm pulse output is provided that

operates at half the frequency of the alarm. This output

is completely synchronous to the RTCC clock and can

be used as a trigger clock to other peripherals.

(Ideal Frequency† – Measured Frequency) * 60 =

Clocks per Minute

† Ideal Frequency = 32,768 Hz

Note:

Changing any of the registers, other than

the RCFGCAL and ALCFGRPT registers,

and the CHIME bit while the alarm is

enabled (ALRMEN = 1), can result in a

false alarm event leading to a false alarm

interrupt. To avoid a false alarm event, the

timer and alarm values should only be

changed while the alarm is disabled

(ALRMEN = 0). It is recommended that the

ALCFGRPT register and CHIME bit be

changed when RTCSYNC = 0.

Writes to the lower half of the RCFGCAL register

should only occur when the timer is turned off or

immediately after the rising edge of the seconds pulse.

Note:

It is up to the user to include, in the error

value, the initial error of the crystal drift

due to temperature and drift due to crystal

aging.

20.4 Alarm

• Configurable from half second to one year

• Enabled using the ALRMEN bit (ALCFGRPT<15>)

• One-time alarm and repeat alarm options are

available

DS39940D-page 250

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FIGURE 20-2:

ALARM MASK SETTINGS

Day of

the

Week

Alarm Mask Setting

(AMASK<3:0>)

Month

Day

Hours

Minutes

Seconds

0000- Every half second

0001- Every second

0010- Every 10 seconds

0011- Every minute

0100- Every 10 minutes

0101- Every hour

s

m

0110- Every day

h

0111- Every week

1000- Every month

d

(1)

1001- Every year

m

d

Note 1: Annually, except when configured for February 29.

 2010 Microchip Technology Inc.

DS39940D-page 251

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NOTES:

DS39940D-page 252

 2010 Microchip Technology Inc.

PIC24FJ64GB004 FAMILY

The programmable CRC generator provides

a

21.0 32-BIT PROGRAMMABLE

CYCLIC REDUNDANCY CHECK

(CRC) GENERATOR

hardware-implemented method of quickly generating

checksums for various networking and security

applications. It offers the following features:

• User-programmable CRC polynomial equation,

up to 32 bits

Note:

This data sheet summarizes the features

of this group of PIC24F devices. It is not

intended to be a comprehensive reference

source. For more information, refer to the

“PIC24F Family Reference Manual”,

Section 41. “32-Bit Programmable

Cyclic Redundancy Check (CRC)”

(DS39729).

• Programmable shift direction (little or big-endian)

• Independent data and polynomial lengths

• Configurable Interrupt output

• Data FIFO

A simplified block diagram of the CRC generator is

shown in Figure 21-1. A simple version of the CRC shift

engine is shown in Figure 21-2.

FIGURE 21-1:

CRC BLOCK DIAGRAM

CRCDATH

CRCDATL

Variable FIFO

(4x32, 8x16 or 16x8)

FIFO Empty Event

CRCISEL

2 * FCY Shift Clock

1

0

Shift Buffer

Set CRCIF

0

1

LENDIAN

Shift Complete Event

CRC Shift Engine

CRCWDATH

CRCWDATL

FIGURE 21-2:

CRC SHIFT ENGINE DETAIL

CRCWDATH

CRCWDATL

Read/Write Bus

X(1)

(1)

X(2)

X(n)

Shift Buffer

Data

(2)

Bit 0

Bit 1

Bit n

Bit 2

Note 1: Each XOR stage of the shift engine is programmable. See text for details.

2: Polynomial length n is determined by ([PLEN<3:0>] + 1).

 2010 Microchip Technology Inc.

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The data for which the CRC is to be calculated must

21.1 User Interface

first be written into the FIFO. Even if the data width is

less than 8, the smallest data element that can be writ-

ten into the FIFO is one byte. For example, if the

DWIDTH value is five, then the size of the data is

DWIDTH + 1, or six. The data is written as a whole

byte; the two unused upper bits are ignored by the

module.

21.1.1

POLYNOMIAL INTERFACE

The CRC module can be programmed for CRC

polynomials of up to the 32nd order, using up to 32 bits.

Polynomial length, which reflects the highest exponent

in the equation, is selected by the PLEN<4:0> bits

(CRCCON2<4:0>).

Once data is written into the MSb of the CRCDAT

registers (that is, MSb as defined by the data width),

the value of the VWORD<4:0> bits (CRCCON1<12:8>)

increments by one. For example, if the DWIDTH value

is 24, the VWORD bits will increment when bit 7 of

CRCDATH is written. Therefore, CRCDATL must

always be written before CRCDATH.

The CRCXORL and CRCXORH registers control which

exponent terms are included in the equation. Setting a

particular bit includes that exponent term in the

equation; functionally, this includes an XOR operation

on the corresponding bit in the CRC engine. Clearing

the bit disables the XOR.

For example, consider two CRC polynomials, one a

16-bit equation and the other a 32-bit equation:

The CRC engine starts shifting data when the CRCGO

bit is set and the value of VWORD is greater than zero.

Each word is copied out of the FIFO into a buffer regis-

ter, which decrements VWORD. The data is then

shifted out of the buffer. The CRC engine continues

shifting at a rate of two bits per instruction cycle, until

the VWORD value reaches zero. This means that for a

given data width, it takes half that number of instruc-

tions for each word to complete the calculation. For

example, it takes 16 cycles to calculate the CRC for a

single word of 32-bit data.

x16 + x12 + x5 + 1

and

x32 + x26 + x23 + x22 + x16 + x12 + x11 + x10 + x8 + x7

+ x5 + x4 + x2 + x + 1

To program these polynomials into the CRC generator,

set the register bits as shown in Table 21-1.

Note that the appropriate positions are set to ‘1’ to

indicate that they are used in the equation (for example,

X26 and X23). The 0 bit required by the equation is

always XORed; thus, X0 is a don’t care. For a poly-

nomial of length N, it is assumed that the Nth bit will

always be used, regardless of the bit setting. Therefore,

for a polynomial length of 32, there is no 32nd bit in the

CRCxOR register.

When the VWORD value reaches the maximum value

for the configured value of DWIDTH (4, 8 or 16), the

CRCFUL bit becomes set. When the VWORD value

reaches zero, the CRCMPT bit becomes set. The FIFO

is emptied and VWORD<4:0> are set to ‘00000’

whenever CRCEN is ‘0’.

At least one instruction cycle must pass, after a write to

CRCDAT, before a read of the VWORD bits is done.

21.1.2

DATA INTERFACE

The module incorporates a FIFO that works with a vari-

able data width. Input data width can be configured to

any value between one and 32 bits using the

DWIDTH<4:0> bits (CRCCON2<12:8>). When the

data width is greater than 15, the FIFO is four words

deep. When the DWIDTH value is between 15 and 8,

the FIFO is 8 words deep. When the DWIDTH value is

less than 8, the FIFO is 16 words deep.

TABLE 21-1:

CRC SETUP EXAMPLES FOR 16 AND 32-BIT POLYNOMIAL

Bit Values

CRC Control

Bits

16-Bit Polynomial

32-Bit Polynomial

PLEN<4:0>

X<31:16>

X<15:0>

01111

11111

0000 0000 0000 000x

0001 0000 0010 000x

0000 0100 1100 0001

0001 1101 1011 011x

DS39940D-page 254

 2010 Microchip Technology Inc.

PIC24FJ64GB004 FAMILY

21.1.3

DATA SHIFT DIRECTION

21.2 Registers

The LENDIAN bit (CRCCON1<3>) is used to control

the shift direction. By default, the CRC will shift data

through the engine, MSb first. Setting LENDIAN (= 1)

causes the CRC to shift data, LSb first. This setting

allows better integration with various communication

schemes and removes the overhead of reversing the

bit order in software. Note that this only changes the

direction of the data that is shifted into the engine. The

result of the CRC calculation will still be a normal CRC

result, not a reverse CRC result.

There are eight registers associated with the module:

• CRCCON1

• CRCCON2

• CRCXORL

• CRCXORH

• CRCDATL

• CRCDATH

• CRCWDATL

• CRCWDATH

21.1.4

INTERRUPT OPERATION

The

CRCCON1

and

CRCCON2

registers

The module generates an interrupt that is configurable

by the user for either of two conditions.

(Register 21-1 and Register 21-2) control the operation

of the module and configure the various settings. The

CRCXOR registers (Register 21-3 and Register 21-4)

select the polynomial terms to be used in the CRC

equation. The CRCDAT and CRCWDAT registers are

each register pairs that serve as buffers for the

double-word, input data and CRC processed output,

respectively.

If CRCISEL is ‘0’, an interrupt is generated when the

VWORD<4:0> bits make a transition from a value of ‘1’

to ‘0’. If CRCISEL is ‘1’, an interrupt will be generated

after the CRC operation finishes and the module sets

the CRCGO bit to ‘0’. Manually setting CRCGO to ‘0’

will not generate an interrupt.

21.1.5

TYPICAL OPERATION

To use the module for a typical CRC calculation:

1. Set the CRCEN bit to enable the module.

2. Configure the module for the desired operation:

a) Program the desired polynomial using the

CRCXORL and CRCXORH registers, and

the PLEN<4:0> bits

b) Configure the data width and shift direction

using the DWIDTH and LENDIAN bits

c) Select the desired interrupt mode using the

CRCISEL bit

3. Preload the FIFO by writing to the CRCDATL

and CRCDATH registers until the CRCFUL bit is

set or no data is left

4. Clear old results by writing 00h to CRCWDATL

and CRCWDATH. CRCWDAT can also be left

unchanged to resume a previously halted

calculation.

5. Set the CRCGO bit to start calculation.

6. Write remaining data into the FIFO as space

becomes available.

7. When the calculation completes, CRCGO is

automatically cleared. An interrupt will be

generated if CRCISEL = 1.

8. Read CRCWDATL and CRCWDATH for the

result of the calculation.

 2010 Microchip Technology Inc.

DS39940D-page 255

PIC24FJ64GB004 FAMILY

REGISTER 21-1: CRCCON1: CRC CONTROL REGISTER 1

R/W-0

U-0

—

R/W-0

CSIDL

R-0

CRCEN

VWORD4

VWORD3

VWORD2

VWORD1

VWORD0

bit 15

bit 8

R-0, HCS

CRCFUL

R-1, HCS

CRCMPT

R/W-0

R/W-0, HC

CRCGO

R/W-0

U-0

—

U-0

—

U-0

—

CRCISEL

LENDIAN

bit 7

bit 0

Legend:

HC = Hardware Clearable bit

W = Writable bit

HCS = Hardware Clearable/Settable bit

U = Unimplemented bit, read as ‘0’

R = Readable bit

-n = Value at POR

‘1’ = Bit is set

‘0’ = Bit is cleared

x = Bit is unknown

bit 15

CRCEN: CRC Enable bit

1= Module is enabled

0= Module is enabled. All state machines, pointers and CRCWDAT/CRCDAT are reset; other SFRs are

NOT reset

bit 14

bit 13

Unimplemented: Read as ‘0’

CSIDL: CRC Stop in Idle Mode bit

1= Discontinue module operation when device enters Idle mode

0= Continue module operation in Idle mode

bit 12-8

bit 7

VWORD<4:0>: Pointer Value bits

Indicates the number of valid words in the FIFO. Has a maximum value of 8 when PLEN<3:0> > 7

or 16 when PLEN<3:0> 7.

CRCFUL: FIFO Full bit

1= FIFO is full

0= FIFO is not full

bit 6

CRCMPT: FIFO Empty Bit

1= FIFO is empty

0= FIFO is not empty

bit 5

CRCISEL: CRC interrupt Selection bit

1= Interrupt on FIFO is empty; CRC calculation is not complete

0= Interrupt on shift is complete and CRCWDAT result is ready

bit 4

CRCGO: Start CRC bit

1= Start CRC serial shifter

0= CRC serial shifter is turned off

bit 3

LENDIAN: Data Shift Direction Select bit

1= Data word is shifted into the CRC starting with the LSb (little endian)

0= Data word is shifted into the CRC starting with the MSb (big endian)

bit 2-0

Unimplemented: Read as ‘0’

DS39940D-page 256

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REGISTER 21-2: CRCCON2: CRC CONTROL REGISTER 2

U-0

—

U-0

—

U-0

—

R/W-0

DWIDTH4

DWIDTH3

DWIDTH2

DWIDTH1

DWIDTH0

bit 15

bit 8

U-0

—

U-0

—

U-0

—

R/W-0

PLEN4

PLEN3

PLEN2

PLEN1

PLEN0

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15-13

bit 12-8

Unimplemented: Read as ‘0’

DWIDTH<4:0>: Data Width Select bits

Defines the width of the data word (Data Word Width = (DWIDTH<4:0>) + 1).

Unimplemented: Read as ‘0’

bit 7-5

bit 4-0

PLEN<4:0>: Polynomial Length Select bits

Defines the length of the CRC polynomial (Polynomial Length = (PLEN<4:0>) + 1).

REGISTER 21-3: CRCXORL: CRC XOR POLYNOMIAL REGISTER, LOW BYTE

R/W-0

X15

R/W-0

X14

R/W-0

X13

R/W-0

X12

R/W-0

X11

R/W-0

X10

R/W-0

X9

R/W-0

X8

bit 15

bit 8

R/W-0

X7

R/W-0

X6

R/W-0

X5

R/W-0

X4

R/W-0

X3

R/W-0

X2

R/W-0

X1

U-0

—

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15-1

bit 0

X<15:1>: XOR of Polynomial Term XⁿEnable bits

Unimplemented: Read as ‘0’

 2010 Microchip Technology Inc.

DS39940D-page 257

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REGISTER 21-4: CRCXORH: CRC XOR POLYNOMIAL REGISTER, HIGH BYTE

R/W-0

X31

R/W-0

X30

R/W-0

X29

R/W-0

X28

R/W-0

X27

R/W-0

X26

R/W-0

X25

R/W-0

X24

bit 15

bit 8

R/W-0

X23

R/W-0

X22

R/W-0

X21

R/W-0

X20

R/W-0

X19

R/W-0

X18

R/W-0

X17

R/W-0

X16

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15-0

X<31:16>: XOR of Polynomial Term XⁿEnable bits

DS39940D-page 258

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A block diagram of the A/D Converter is shown in

Figure 22-1.

22.0 10-BIT HIGH-SPEED A/D

CONVERTER

To perform an A/D conversion:

Note:

This data sheet summarizes the features

1. Configure the A/D module:

of this group of PIC24F devices. It is not

intended to be a comprehensive reference

source. For more information, refer to the

“PIC24F Family Reference Manual”,

Section 17. “10-Bit A/D Converter”

(DS39705).

a) Configure port pins as analog inputs and/or

select band gap reference inputs

(AD1PCFGL<15:0> and AD1PCFGH<1:0>).

b) Select voltage reference source to match

expected range on analog inputs

(AD1CON2<15:13>).

The 10-bit A/D Converter has the following key

features:

c) Select the analog conversion clock to match

the desired data rate with the processor

clock (AD1CON3<7:0>).

• Successive Approximation (SAR) conversion

• Conversion speeds of up to 500 ksps

• 13 analog input pins

d) Select the appropriate sample/conversion

sequence

(AD1CON1<7:5>

and

AD1CON3<12:8>).

• External voltage reference input pins

• Internal band gap reference inputs

• Automatic Channel Scan mode

• Selectable conversion trigger source

• 16-word conversion result buffer

• Selectable Buffer Fill modes

e) Select how conversion results are

presented in the buffer (AD1CON1<9:8>).

f) Select interrupt rate (AD1CON2<5:2>).

g) Turn on A/D module (AD1CON1<15>).

2. Configure the A/D interrupt (if required):

a) Clear the AD1IF bit.

• Four result alignment options

b) Select A/D interrupt priority.

• Operation during CPU Sleep and Idle modes

On all PIC24FJ64GB004 family devices, the 10-bit A/D

Converter has 13 analog input pins, designated AN0

through AN12. In addition, there are two analog input

pins for external voltage reference connections (VREF+

and VREF-). These voltage reference inputs may be

shared with other analog input pins.

 2010 Microchip Technology Inc.

DS39940D-page 259

PIC24FJ64GB004 FAMILY

FIGURE 22-1:

10-BIT HIGH-SPEED A/D CONVERTER BLOCK DIAGRAM

Internal Data Bus

16

AVDD

AVSS

VR+

VR-

VREF+

VREF-

Comparator

VINH

VINL

VR- VR+

DAC

AN0

AN1

AN2

AN3

AN4

AN5

AN6

AN7

AN8

AN9

AN10

AN11

S/H

10-Bit SAR

Conversion Logic

VINH

Data Formatting

ADC1BUF0:

ADC1BUFF

VINL

AD1CON1

AD1CON2

AD1CON3

AD1CHS0

AD1PCFGL

AD1PCFGH

AD1CSSL

AD1CSSH

VINH

AN12

VDDCORE

VBG/2

VINL

VBG

Sample Control

Control Logic

Conversion Control

Input MUX Control

Pin Config Control

DS39940D-page 260

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REGISTER 22-1: AD1CON1: A/D CONTROL REGISTER 1

R/W-0

ADON⁽¹⁾

U-0

—

R/W-0

U-0

—

U-0

—

U-0

—

R/W-0

ADSIDL

FORM1

FORM0

bit 15

bit 8

R/W-0

U-0

—

U-0

—

R/W-0

ASAM

R/W-0, HCS R/C-0, HCS

SAMP DONE

bit 0

SSRC2

SSRC1

SSRC0

bit 7

Legend:

C = Clearable bit

W = Writable bit

‘1’ = Bit is set

HCS = Hardware Clearable/Settable bit

U = Unimplemented bit, read as ‘0’

R = Readable bit

-n = Value at POR

‘0’ = Bit is cleared

x = Bit is unknown

bit 15

ADON: A/D Operating Mode bit⁽¹⁾

1= A/D Converter module is operating

0= A/D Converter is off

bit 14

bit 13

Unimplemented: Read as ‘0’

ADSIDL: Stop in Idle Mode bit

1= Discontinue module operation when device enters Idle mode

0= Continue module operation in Idle mode

bit 12-10

bit 9-8

Unimplemented: Read as ‘0’

FORM<1:0>: Data Output Format bits

11= Signed fractional (sddd dddd dd00 0000)

10= Fractional (dddd dddd dd00 0000)

01= Signed integer (ssss sssd dddd dddd)

00= Integer (0000 00dd dddd dddd)

bit 7-5

SSRC<2:0>: Conversion Trigger Source Select bits

111= Internal counter ends sampling and starts conversion (auto-convert)

110= CTMU event ends sampling and starts conversion

101= Reserved

100= Timer5 compare ends sampling and starts conversion

011= Reserved

010= Timer3 compare ends sampling and starts conversion

001= Active transition on INT0 pin ends sampling and starts conversion

000= Clearing the SAMP bit ends sampling and starts conversion

bit 4-3

bit 2

Unimplemented: Read as ‘0’

ASAM: A/D Sample Auto-Start bit

1= Sampling begins immediately after the last conversion completes; SAMP bit is auto-set

0= Sampling begins when the SAMP bit is set

bit 1

bit 0

SAMP: A/D Sample Enable bit

1= A/D sample/hold amplifier is sampling input

0= A/D sample/hold amplifier is holding

DONE: A/D Conversion Status bit

1= A/D conversion is done

0= A/D conversion is NOT done

Note 1: Values of ADC1BUFx registers will not retain their values once the ADON bit is cleared. Read out the

conversion values from the buffer before disabling the module.

 2010 Microchip Technology Inc.

DS39940D-page 261

PIC24FJ64GB004 FAMILY

REGISTER 22-2: AD1CON2: A/D CONTROL REGISTER 2

R/W-0

r-0

r

U-0

—

R/W-0

U-0

—

U-0

—

VCFG2

VCFG1

VCFG0

CSCNA

bit 15

bit 8

R-0

U-0

—

R/W-0

SMPI3

R/W-0

SMPI2

R/W-0

SMPI1

R/W-0

SMPI0

R/W-0

BUFM

R/W-0

ALTS

BUFS

bit 7

bit 0

Legend:

r = Reserved bit

W = Writable bit

‘1’ = Bit is set

R = Readable bit

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

-n = Value at POR

bit 15-13

VCFG<2:0>: Voltage Reference Configuration bits

VCFG<2:0>

VR+

VR-

000

001

010

011

1xx

AVDD

External VREF+ pin

AVDD

AVSS

External VREF- pin

AVSS

External VREF+ pin

AVDD

bit 12

bit 11

bit 10

Reserved: Maintain as ‘0’

Unimplemented: Read as ‘0’

CSCNA: Scan Input Selections for CH0+ S/H Input for MUX A Input Multiplexer Setting bit

1= Scan inputs

0= Do not scan inputs

bit 9-8

bit 7

Unimplemented: Read as ‘0’

BUFS: Buffer Fill Status bit (valid only when BUFM = 1)

1= A/D is currently filling buffer 08-0F; user should access data in 00-07

0= A/D is currently filling buffer 00-07; user should access data in 08-0F

bit 6

Unimplemented: Read as ‘0’

bit 5-2

SMPI<3:0>: Sample/Convert Sequences Per Interrupt Selection bits

1111 = Interrupts are at the completion of conversion for each 16th sample/convert sequence

1110 = Interrupts are at the completion of conversion for each 15th sample/convert sequence

.....

0001 = Interrupts are at the completion of conversion for each 2nd sample/convert sequence

0000 = Interrupts are at the completion of conversion for each sample/convert sequence

bit 1

bit 0

BUFM: Buffer Mode Select bit

1= Buffer is configured as two 8-word buffers (ADC1BUFn<15:8> and ADC1BUFn<7:0>)

0= Buffer is configured as one 16-word buffer (ADC1BUFn<15:0>)

ALTS: Alternate Input Sample Mode Select bit

1= Uses MUX A input multiplexer settings for first sample, then alternates between MUX B and

MUX A input multiplexer settings for all subsequent samples

0= Always uses MUX A input multiplexer settings

DS39940D-page 262

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REGISTER 22-3: AD1CON3: A/D CONTROL REGISTER 3

R/W-0

ADRC

r-0

r

r-0

r

R/W-0

SAMC4

SAMC3

SAMC2

SAMC1

SAMC0

bit 15

bit 8

R/W-0

ADCS7

ADCS6

ADCS5

ADCS4

ADCS3

ADCS2

ADCS1

ADCS0

bit 7

bit 0

Legend:

r = Reserved bit

W = Writable bit

‘1’ = Bit is set

R = Readable bit

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

-n = Value at POR

bit 15

ADRC: A/D Conversion Clock Source bit

1= A/D internal RC clock

0= Clock derived from system clock

bit 14-13

bit 12-8

Reserved: Maintain as ‘0’

SAMC<4:0>: Auto-Sample Time bits

11111= 31 TAD

·····

00001= 1 TAD

00000= 0 TAD (not recommended)

bit 7-0

ADCS<7:0>: A/D Conversion Clock Select bits

11111111to 01000000= Reserved

······

00111111= 64 • TCY

······

00000001= 2 • TCY

00000000= TCY

 2010 Microchip Technology Inc.

DS39940D-page 263

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REGISTER 22-4: AD1CHS: A/D INPUT SELECT REGISTER

R/W-0

U-0

—

U-0

—

R/W-0

CH0NB

CH0SB4^(1,2)CH0SB3^(1,2)CH0SB2^(1,2)CH0SB1^(1,2)CH0SB0^(1,2)

bit 15

bit 8

R/W-0

U-0

—

U-0

—

R/W-0

CH0NA

CH0SA4

CH0SA3

CH0SA2

CH0SA1

CH0SA0

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15

CH0NB: Channel 0 Negative Input Select for MUX B Multiplexer Setting bit

1= Channel 0 negative input is AN1

0= Channel 0 negative input is VR-

bit 14-13

bit 12-8

Unimplemented: Read as ‘0’

CH0SB<4:0>: Channel 0 Positive Input Select for MUX B Multiplexer Setting bits^(1,2)

11111= Channel 0 positive input is reserved for CTMU use only⁽³⁾

1xxxx= Unimplemented; do not use.

01111= Channel 0 positive input is internal band gap reference (VBG)

01110= Channel 0 positive input is VBG/2

01101= Channel 0 positive input is voltage regulator output (VDDCORE)

01100= Channel 0 positive input is AN12

01011= Channel 0 positive input is AN11

01010= Channel 0 positive input is AN10

01001= Channel 0 positive input is AN9

01000= Channel 0 positive input is AN8

00111= Channel 0 positive input is AN7

00110= Channel 0 positive input is AN6

00101= Channel 0 positive input is AN5

00100= Channel 0 positive input is AN4

00011= Channel 0 positive input is AN3

00010= Channel 0 positive input is AN2

00001= Channel 0 positive input is AN1

00000= Channel 0 positive input is AN0

bit 7

CH0NA: Channel 0 Negative Input Select for MUX A Multiplexer Setting bit

1= Channel 0 negative input is AN1

0= Channel 0 negative input is VR-

bit 6-5

bit 4-0

Unimplemented: Read as ‘0’

CH0SA<4:0>: Channel 0 Positive Input Select for MUX A Multiplexer Setting bits

Implemented combinations are identical to those for CH0SB<4:0> (above).

Note 1: Combinations not shown here are unimplemented; do not use.

2: Analog channels, AN6, AN7, AN8 and AN12, are unavailable on 28-pin devices; do not use.

3: Selecting this internal channel allows the CTMU module to utilize the A/D Converter sample and hold

capacitor (CAD) for the smallest time measurements.

DS39940D-page 264

 2010 Microchip Technology Inc.

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REGISTER 22-5: AD1PCFG: A/D PORT CONFIGURATION REGISTER

R/W-0

R/W-0⁽¹⁾

PCFG12

R/W-0

R/W-0⁽¹⁾

PCFG8

PCFG15

PCFG14

PCFG13

PCFG11

PCFG10

PCFG9

bit 15

bit 8

R/W-0⁽¹⁾

PCFG7

R/W-0⁽¹⁾

PCFG6

R/W-0

PCFG5

PCFG4

PCFG3

PCFG2

PCFG1

PCFG0

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

-n = Value at POR

bit 15

bit 14

bit 13

bit 12-0

PCFG15: A/D Input Band Gap Reference Enable bit

1= Internal band gap (VBG) reference channel is disabled

0= Internal band gap reference channel is enabled

PCFG14: A/D Input Half Band Gap Reference Enable bit

1= Internal half band gap (VBG/2) reference channel is disabled

0= Internal half band gap reference channel is enabled

PCFG13: A/D Input Voltage Regulator Output Reference Enable bit

1= Internal voltage regulator output (VDDCORE) reference channel is disabled

0= Internal voltage regulator output reference channel is enabled

PCFG<12:0>: Analog Input Pin Configuration Control bits⁽¹⁾

1= Pin for corresponding analog channel is configured in Digital mode; I/O port read is enabled

0= Pin is configured in Analog mode; I/O port read is disabled, A/D samples pin voltage

Note 1: Analog channels, AN6, AN7, AN8 and AN12, are unavailable on 28-pin devices; leave these corresponding

bits set.

 2010 Microchip Technology Inc.

DS39940D-page 265

PIC24FJ64GB004 FAMILY

REGISTER 22-6: AD1CSSL: A/D INPUT SCAN SELECT REGISTER

R/W-0

R/W-0⁽¹⁾

CSSL12

R/W-0

CSSL8⁽¹⁾

CSSL15

CSSL14

CSSL13

CSSL11

CSSL10

CSSL9

bit 15

bit 8

R/W-0

CSSL7

CSSL6

CSSL5

CSSL4

CSSL3

CSSL2

CSSL1

CSSL0

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

-n = Value at POR

bit 15

bit 14

bit 13

bit 12-0

CSSL15: A/D Input Band Gap Scan Enable bit

1= Internal band gap (VBG) channel is enabled for input scan

0= Analog channel is disabled from input scan

CSSL14: A/D Input Half Band Gap Scan Enable bit

1= Internal half band gap (VBG/2) channel is enabled for input scan

0= Analog channel is disabled from input scan

CSSL13: A/D Input Voltage Regulator Output Scan Enable bit

1= Internal voltage regulator output (VDDCORE) is enabled for input scan

0= Analog channel is disabled from input scan

CSSL<12:0>: A/D Input Pin Scan Selection bits⁽¹⁾

1= Corresponding analog channel is selected for input scan

0= Analog channel is omitted from input scan

Note 1: Analog channels, AN6, AN7, AN8 and AN12, are unavailable on 28-pin devices; leave these corresponding

bits cleared.

DS39940D-page 266

 2010 Microchip Technology Inc.

PIC24FJ64GB004 FAMILY

EQUATION 22-1: A/D CONVERSION CLOCK PERIOD⁽¹⁾

TAD

TCY

ADCS =

– 1

TAD = TCY • (ADCS + 1)

Note 1: Based on TCY = 2 * TOSC, Doze mode and PLL are disabled.

FIGURE 22-2:

10-BIT A/D CONVERTER ANALOG INPUT MODEL

VDD

RIC  250

RSS  5 k(Typical)

Sampling

Switch

VT = 0.6V

ANx

RSS

Rs

CHOLD

= ADC capacitance

= 4.4 pF (Typical)

VA

CPIN

ILEAKAGE

500 nA

6-11 pF

(Typical)

VSS

Legend: CPIN

VT

= Input Capacitance

= Threshold Voltage

ILEAKAGE = Leakage Current at the pin due to

various junctions

RIC

= Interconnect Resistance

RSS

= Sampling Switch Resistance

= Sample/Hold Capacitance (from DAC)

CHOLD

Note: CPIN value depends on device package and is not tested. The effect of CPIN is negligible if Rs  5 k.

 2010 Microchip Technology Inc.

DS39940D-page 267

PIC24FJ64GB004 FAMILY

FIGURE 22-3:

A/D TRANSFER FUNCTION

Output Code

(Binary (Decimal))

11 1111 1111(1023)

11 1111 1110(1022)

10 0000 0011(515)

10 0000 0010(514)

10 0000 0001(513)

10 0000 0000(512)

01 1111 1111(511)

01 1111 1110(510)

01 1111 1101(509)

00 0000 0001(1)

00 0000 0000(0)

Voltage Level

DS39940D-page 268

 2010 Microchip Technology Inc.

PIC24FJ64GB004 FAMILY

The comparator outputs may be directly connected to

the CxOUT pins. When the respective COE equals ‘1’,

the I/O pad logic makes the unsynchronized output of

the comparator available on the pin.

23.0 TRIPLE COMPARATOR

MODULE

Note:

This data sheet summarizes the features

of this group of PIC24F devices. It is not

A simplified block diagram of the module in shown in

Figure 23-1. Diagrams of the possible individual

comparator configurations are shown in Figure 23-2.

intended to be a comprehensive reference

source. For more information, refer to the

associated “PIC24F Family Reference

Each comparator has its own control register,

CMxCON (Register 23-1), for enabling and configuring

its operation. The output and event status of all three

comparators are provided in the CMSTAT register

(Register 23-2).

Manual”,

Section

46.

“Scalable

Comparator Module” (DS39734).

The triple comparator module provides three dual input

comparators. The inputs to the comparator can be con-

figured to use any one of four external analog inputs, as

well as voltage reference inputs from the voltage

reference generator and band gap reference.

FIGURE 23-1:

TRIPLE COMPARATOR MODULE BLOCK DIAGRAM

EVPOL<1:0>

CCH<1:0>

CREF

CEVT

Trigger/Interrupt

Logic

COE

CPOL

VIN-

C1

VIN+

CXINB

CXINC

CXIND

CVREF-

C1OUT

Input

Select

Logic

COUT

CEVT

EVPOL<1:0>

CPOL

Trigger/Interrupt

Logic

COE

VIN-

C2

VIN+

C2OUT

COUT

CEVT

EVPOL<1:0>

CPOL

CXINA

Trigger/Interrupt

Logic

CVREF+

COE

VIN-

C3

VIN+

C3OUT

COUT

 2010 Microchip Technology Inc.

DS39940D-page 269

PIC24FJ64GB004 FAMILY

FIGURE 23-2:

INDIVIDUAL COMPARATOR CONFIGURATIONS

Comparator Off

CEN = 0, CREF = x, CCH<1:0> = xx

COE

VIN-

Cx

VIN+

Off (Read as ‘0’)

CxOUT

Comparator CxINB > CxINA Compare

Comparator CxINC > CxINA Compare

CEN = 1, CREF = 0, CCH<1:0> = 00

CEN = 1, CREF = 0, CCH<1:0> = 01

COE

VIN-

CXINB

CXINC

Cx

VIN+

CXINA

CxOUT

Comparator CVREF- > CxINA Compare

Comparator CxIND > CxINA Compare

CEN = 1, CREF = 0, CCH<1:0> = 10

CEN = 1, CREF = 0, CCH<1:0> = 11

COE

VIN-

CXIND

CVREF-

Cx

VIN+

CXINA

CxOUT

Comparator CxINB > CVREF+ Compare

CEN = 1, CREF = 1, CCH<1:0> = 00

Comparator CxINC > CVREF+ Compare

CEN = 1, CREF = 1, CCH<1:0> = 01

COE

VIN-

CXINB

CXINC

Cx

VIN+

CVREF+

CxOUT

Comparator CVREF- > CVREF+ Compare

CEN = 1, CREF = 1, CCH<1:0> = 11

Comparator CxIND > CVREF+ Compare

CEN = 1, CREF = 1, CCH<1:0> = 10

COE

VIN-

CVREF-

CXIND

Cx

VIN+

CVREF+

CxOUT

DS39940D-page 270

 2010 Microchip Technology Inc.

PIC24FJ64GB004 FAMILY

REGISTER 23-1: CMxCON: COMPARATOR x CONTROL REGISTERS

(COMPARATORS 1 THROUGH 3)

R/W-0

CEN

R/W-0

COE

R/W-0

CPOL

U-0

—

U-0

—

U-0

—

R/W-0

CEVT

R-0

COUT

bit 15

bit 8

R/W-0

U-0

—

R/W-0

CREF

U-0

—

U-0

—

R/W-0

CCH1

R/W-0

CCH0

EVPOL1

EVPOL0

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

-n = Value at POR

bit 15

bit 14

bit 13

CEN: Comparator Enable bit

1= Comparator is enabled

0= Comparator is disabled

COE: Comparator Output Enable bit

1= Comparator output is present on the CxOUT pin.

0= Comparator output is internal only

CPOL: Comparator Output Polarity Select bit

1= Comparator output is inverted

0= Comparator output is not inverted

bit 12-10

bit 9

Unimplemented: Read as ‘0’

CEVT: Comparator Event bit

1= Comparator event defined by EVPOL<1:0> has occurred; subsequent triggers and interrupts are

disabled until the bit is cleared

0= Comparator event has not occurred

bit 8

COUT: Comparator Output bit

When CPOL = 0:

1= VIN+ > VIN-

0= VIN+ < VIN-

When CPOL = 1:

1= VIN+ < VIN-

0= VIN+ > VIN-

bit 7-6

EVPOL<1:0>: Trigger/Event/Interrupt Polarity Select bits

11= Trigger/event/interrupt generated on any change of the comparator output (while CEVT = 0)

10= Trigger/event/interrupt generated on transition of the comparator output:

If CPOL = 0 (non-inverted polarity):

High-to-low transition only.

If CPOL = 1 (inverted polarity):

Low-to-high transition only.

01= Trigger/event/interrupt generated on transition of comparator output:

If CPOL = 0 (non-inverted polarity):

Low-to-high transition only.

If CPOL = 1 (inverted polarity):

High-to-low transition only.

00= Trigger/event/interrupt generation is disabled

bit 5

Unimplemented: Read as ‘0’

 2010 Microchip Technology Inc.

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REGISTER 23-1: CMxCON: COMPARATOR x CONTROL REGISTERS

(COMPARATORS 1 THROUGH 3) (CONTINUED)

bit 4

CREF: Comparator Reference Select bits (non-inverting input)

1= Non-inverting input connects to internal CVREF+ input reference voltage

0= Non-inverting input connects to CxINA pin

bit 3-2

bit 1-0

Unimplemented: Read as ‘0’

CCH<1:0>: Comparator Channel Select bits

11= Inverting input of comparator connects to CVREF- input reference voltage

10= Inverting input of comparator connects to CxIND pin

01= Inverting input of comparator connects to CxINC pin

00= Inverting input of comparator connects to CxINB pin

REGISTER 23-2: CMSTAT: COMPARATOR MODULE STATUS REGISTER

R/W-0

U-0

—

U-0

—

U-0

—

U-0

—

R-0

CMIDL

C3EVT

C2EVT

C1EVT

bit 15

bit 8

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

R-0

C3OUT

C2OUT

C1OUT

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15

CMIDL: Comparator Stop in Idle Mode bit

1= Discontinue operation of all comparators when device enters Idle mode

0= Continue operation of all enabled comparators in Idle mode

bit 14-11

bit 10

Unimplemented: Read as ‘0’

C3EVT: Comparator 3 Event Status bit (read-only)

Shows the current event status of Comparator 3 (CM3CON<9>).

C2EVT: Comparator 2 Event Status bit (read-only)

Shows the current event status of Comparator 2 (CM2CON<9>).

C1EVT: Comparator 1 Event Status bit (read-only)

Shows the current event status of Comparator 1 (CM1CON<9>).

Unimplemented: Read as ‘0’

bit 9

bit 8

bit 7-3

bit 2

C3OUT: Comparator 3 Output Status bit (read-only)

Shows the current output of Comparator 3 (CM3CON<8>).

C2OUT: Comparator 2 Output Status bit (read-only)

Shows the current output of Comparator 2 (CM2CON<8>).

C1OUT: Comparator 1 Output Status bit (read-only)

Shows the current output of Comparator 1 (CM1CON<8>).

bit 1

bit 0

DS39940D-page 272

 2010 Microchip Technology Inc.

PIC24FJ64GB004 FAMILY

voltage, each with 16 distinct levels. The range to be

used is selected by the CVRR bit (CVRCON<5>). The

primary difference between the ranges is the size of the

steps selected by the CVREF Selection bits

24.0 COMPARATOR VOLTAGE

REFERENCE

Note:

This data sheet summarizes the features

(CVR<3:0>), with one range offering finer resolution.

of this group of PIC24F devices. It is not

intended to be a comprehensive reference

source. For more information, refer to the

“PIC24F Family Reference Manual”,

Section 20. “Comparator Voltage

Reference Module” (DS39709).

The comparator reference supply voltage can come

from either VDD and VSS, or the external VREF+ and

VREF-. The voltage source is selected by the CVRSS

bit (CVRCON<4>).

The settling time of the comparator voltage reference

must be considered when changing the CVREF

output.

24.1 Configuring the Comparator

Voltage Reference

The voltage reference module is controlled through the

CVRCON register (Register 24-1). The comparator

voltage reference provides two ranges of output

FIGURE 24-1:

COMPARATOR VOLTAGE REFERENCE BLOCK DIAGRAM

CVRSS = 1

CVRSS = 0

VREF+

AVDD

8R

CVR<3:0>

CVREFP

R

CVREN

1

R

VREF+

CVREF+

0

16 Steps

CVREF

R

CVROE

CVREFM<1:0>

CVRR

VREF-

8R

CVRSS = 1

VREF+

VBG/6

11

10

CVREF-

CVRSS = 0

01

00

VBG

AVSS

VBG/2

 2010 Microchip Technology Inc.

DS39940D-page 273

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REGISTER 24-1: CVRCON: COMPARATOR VOLTAGE REFERENCE CONTROL REGISTER

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

R/W-0

CVREFP

CVREFM1

CVREFM0

bit 15

bit 8

R/W-0

CVRR

R/W-0

CVR3

R/W-0

CVR2

R/W-0

CVR1

R/W-0

CVR0

CVREN

CVROE

CVRSS

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

-n = Value at POR

bit 15-11

bit 10

Unimplemented: Read as ‘0’

CVREFP: CVREF+ Reference Output Select bit

1= Use VREF+ input pin as CVREF+ reference output to comparators

0= Use comparator voltage reference module’s generated output as CVREF+ reference output to

comparators

bit 9-8

CVREFM<1:0>: CVREF- Reference Output Select bits

11= Use VREF+ input pin as CVREF- reference output to comparators

10= Use VBG/6 as CVREF- reference output to comparators

01= Use VBG as CVREF- reference output to comparators

00= Use VBG/2 as CVREF- reference output to comparators

bit 7

bit 6

bit 5

bit 4

bit 3-0

CVREN: Comparator Voltage Reference Enable bit

1= CVREF circuit is powered on

0= CVREF circuit is powered down

CVROE: Comparator VREF Output Enable bit

1= CVREF voltage level is output on CVREF pin

0= CVREF voltage level is disconnected from CVREF pin

CVRR: Comparator VREF Range Selection bit

1= CVRSRC range should be 0 to 0.625 CVRSRC with CVRSRC/24 step size

0= CVRSRC range should be 0.25 to 0.719 CVRSRC with CVRSRC/32 step size

CVRSS: Comparator VREF Source Selection bit

1= Comparator reference source, CVRSRC = VREF+ – VREF-

0= Comparator reference source, CVRSRC = AVDD – AVSS

CVR<3:0>: Comparator VREF Value Selection (0  CVR<3:0>  15) bits

When CVRR = 1:

CVREF = (CVR<3:0>/24)  (CVRSRC)

When CVRR = 0:

CVREF = 1/4  (CVRSRC) + (CVR<3:0>/32)  (CVRSRC)

DS39940D-page 274

 2010 Microchip Technology Inc.

PIC24FJ64GB004 FAMILY

25.1 Measuring Capacitance

25.0 CHARGE TIME

MEASUREMENT UNIT (CTMU)

The CTMU module measures capacitance by generat-

ing an output pulse, with a width equal to the time

Note:

This data sheet summarizes the features

between edge events, on two separate input channels.

The pulse edge events to both input channels can be

selected from four sources: two internal peripheral

modules (OC1 and Timer1) and two external pins

(CTEDG1 and CTEDG2). This pulse is used with the

module’s precision current source to calculate

capacitance according to the relationship:

of this group of PIC24F devices. It is not

intended to be a comprehensive reference

source. For more information, refer to the

associated “PIC24F Family Reference

Manual”, Section 11. “Charge Time

Measurement Unit (CTMU)” (DS39724).

The Charge Time Measurement Unit is a flexible

analog module that provides accurate differential time

measurement between pulse sources, as well as

asynchronous pulse generation. Its key features

include:

dV

i = C •

dT

For capacitance measurements, the A/D Converter

samples an external capacitor (CAPP) on one of its

input channels after the CTMU output’s pulse. A Preci-

sion Resistor (RPR) provides current source calibration

on a second A/D channel. After the pulse ends, the

converter determines the voltage on the capacitor. The

actual calculation of capacitance is performed in

software by the application.

• Four edge input trigger sources

• Polarity control for each edge source

• Control of edge sequence

• Control of response to edges

• Time measurement resolution of 1 nanosecond

• Accurate current source suitable for capacitive

measurement

Figure 25-1 shows the external connections used for

capacitance measurements, and how the CTMU and

A/D modules are related in this application. This

example also shows the edge events coming from

Timer1, but other configurations using external edge

Together with other on-chip analog modules, the CTMU

can be used to precisely measure time, measure

capacitance, measure relative changes in capacitance

or generate output pulses that are independent of the

system clock. The CTMU module is ideal for interfacing

with capacitive-based sensors.

sources are possible.

A detailed discussion on

measuring capacitance and time with the CTMU

module is provided in the “PIC24F Family Reference

Manual”.

The CTMU is controlled through two registers:

CTMUCON and CTMUICON. CTMUCON enables the

module and controls edge source selection, edge

source polarity selection and edge sequencing. The

CTMUICON register controls the selection and trim of

the current source.

FIGURE 25-1:

TYPICAL CONNECTIONS AND INTERNAL CONFIGURATION FOR

CAPACITANCE MEASUREMENT

PIC24F Device

Timer1

CTMU

EDG1

EDG2

Current Source

Output

Pulse

A/D Converter

ANx

ANY

CAPP

RPR

 2010 Microchip Technology Inc.

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PIC24FJ64GB004 FAMILY

25.2 Measuring Time

25.3 Pulse Generation and Delay

Time measurements on the pulse width can be similarly

performed using the A/D module’s internal capacitor

(CAD) and a precision resistor for current calibration.

Figure 25-2 shows the external connections used for

time measurements, and how the CTMU and A/D

modules are related in this application. This example also

shows both edge events coming from the external

CTEDG pins, but other configurations using internal

edge sources are possible. For the smallest time

measurements, select the internal A/D Channel 31,

CH0S<4:0> = 11111. This minimizes any stray

capacitance that may otherwise be associated with

using an input pin, thus keeping the total capacitance

to that of the A/D Converter itself (4-5 pF). A detailed

discussion on measuring capacitance and time with the

CTMU module is provided in the “PIC24F Family

Reference Manual”.

The CTMU module can also generate an output pulse with

edges that are not synchronous with the device’s system

clock. More specifically, it can generate a pulse with a

programmable delay from an edge event input to the module.

When the module is configured for pulse generation

delay by setting the TGEN bit (CTMUCON<12>), the

internal current source is connected to the B input of

Comparator 2. A capacitor (CDELAY) is connected to

the Comparator 2 pin, C2INB, and the comparator volt-

age reference, CVREF, is connected to C2INA. CVREF

is then configured for a specific trip point. The module

begins to charge CDELAY when an edge event is

detected. When CDELAY charges above the CVREF trip

point, a pulse is output on CTPLS. The length of the

pulse delay is determined by the value of CDELAY and

the CVREF trip point.

Figure 25-3 shows the external connections for pulse

generation, as well as the relationship of the different ana-

log modules required. While CTEDG1 is shown as the

input pulse source, other options are available. A detailed

discussion on pulse generation with the CTMU module is

provided in the “PIC24F Family Reference Manual”.

FIGURE 25-2:

TYPICAL CONNECTIONS AND INTERNAL CONFIGURATION FOR TIME

MEASUREMENT

PIC24F Device

CTMU

CTEDG1

CTEDG2

EDG1

EDG2

Current Source

Output

Pulse

ANx

RPR

A/D Converter

CAD

FIGURE 25-3:

TYPICAL CONNECTIONS AND INTERNAL CONFIGURATION FOR PULSE

DELAY GENERATION

PIC24F Device

CTMU

CTEDG1

EDG1

CTPLS

Current Source

Comparator

C2

C2INB

CDELAY

CVREF

DS39940D-page 276

 2010 Microchip Technology Inc.

PIC24FJ64GB004 FAMILY

REGISTER 25-1: CTMUCON: CTMU CONTROL REGISTER

R/W-0

U-0

—

R/W-0

TGEN⁽¹⁾

R/W-0

CTMUEN

CTMUSIDL

EDGEN

EDGSEQEN

IDISSEN

CTTRIG

bit 15

bit 8

R/W-0

EDG2POL

EDG2SEL1 EDG2SEL0

EDG1POL

EDG1SEL1 EDG1SEL0 EDG2STAT EDG1STAT

bit 0

bit 7

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared

x = Bit is unknown

bit 15

CTMUEN: CTMU Enable bit

1= Module is enabled

0= Module is disabled

bit 14

bit 13

Unimplemented: Read as ‘0’

CTMUSIDL: Stop in Idle Mode bit

1= Discontinue module operation when device enters Idle mode

0= Continue module operation in Idle mode

bit 12

bit 11

bit 10

bit 9

TGEN: Time Generation Enable bit⁽¹⁾

1= Enables edge delay generation

0= Disables edge delay generation

EDGEN: Edge Enable bit

1= Edges are not blocked

0= Edges are blocked

EDGSEQEN: Edge Sequence Enable bit

1= Edge 1 event must occur before Edge 2 event can occur

0= No edge sequence is needed

IDISSEN: Analog Current Source Control bit

1= Analog current source output is grounded

0= Analog current source output is not grounded

bit 8

CTTRIG: Trigger Control bit

1= Trigger output is enabled

0= Trigger output is disabled

bit 7

EDG2POL: Edge 2 Polarity Select bit

1= Edge 2 programmed for a positive edge response

0= Edge 2 programmed for a negative edge response

bit 6-5

EDG2SEL<1:0>: Edge 2 Source Select bits

11= CTED1 pin

10= CTED2 pin

01= OC1 module

00= Timer1 module

bit 4

EDG1POL: Edge 1 Polarity Select bit

1= Edge 1 programmed for a positive edge response

0= Edge 1 programmed for a negative edge response

Note 1: If TGEN = 1, the peripheral inputs and outputs must be configured to an available RPn pin. For more

information, see Section 10.4 “Peripheral Pin Select (PPS)”.

 2010 Microchip Technology Inc.

DS39940D-page 277

PIC24FJ64GB004 FAMILY

REGISTER 25-1: CTMUCON: CTMU CONTROL REGISTER (CONTINUED)

bit 3-2

EDG1SEL<1:0>: Edge 1 Source Select bits

11= CTED1 pin

10= CTED2 pin

01= OC1 module

00= Timer1 module

bit 1

bit 0

EDG2STAT: Edge 2 Status bit

1= Edge 2 event has occurred

0= Edge 2 event has not occurred

EDG1STAT: Edge 1 Status bit

1= Edge 1 event has occurred

0= Edge 1 event has not occurred

Note 1: If TGEN = 1, the peripheral inputs and outputs must be configured to an available RPn pin. For more

information, see Section 10.4 “Peripheral Pin Select (PPS)”.

REGISTER 25-2: CTMUICON: CTMU CURRENT CONTROL REGISTER

R/W-0

IRNG1

R/W-0

IRNG0

ITRIM5

ITRIM4

ITRIM3

ITRIM2

ITRIM1

ITRIM0

bit 15

bit 8

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

-n = Value at POR

bit 15-10

ITRIM<5:0>: Current Source Trim bits

011111= Maximum positive change from nominal current

011110

. . . . .

000001= Minimum positive change from nominal current

000000= Nominal current output specified by IRNG<1:0>

111111= Minimum negative change from nominal current

. . . . .

100010

100001= Maximum negative change from nominal current

bit 9-8

bit 7-0

IRNG<1:0>: Current Source Range Select bits

11= 100  Base Current

10= 10  Base Current

01= Base current level (0.55 A nominal)

00= Current source disabled

Unimplemented: Read as ‘0’

DS39940D-page 278

 2010 Microchip Technology Inc.

PIC24FJ64GB004 FAMILY

26.1.1

CONSIDERATIONS FOR

CONFIGURING PIC24FJ64GB004

FAMILY DEVICES

26.0 SPECIAL FEATURES

Note:

This data sheet summarizes the features

of this group of PIC24F devices. It is not

intended to be a comprehensive reference

source. For more information, refer to the

following sections of the “PIC24F Family

Reference Manual”:

In PIC24FJ64GB004 family devices, the configuration

bytes are implemented as volatile memory. This means

that configuration data must be programmed each time

the device is powered up. Configuration data is stored

in the three words at the top of the on-chip program

memory space, known as the Flash Configuration

Words. Their specific locations are shown in

Table 26-1. These are packed representations of the

actual device Configuration bits, whose actual

locations are distributed among several locations in

configuration space. The configuration data is automat-

ically loaded from the Flash Configuration Words to the

proper Configuration registers during device Resets.

•

Section 9. “Watchdog Timer (WDT)”

(DS39697)

Section 32. “High-Level Device

Integration” (DS39719)

Section 33. “Programming and

Diagnostics” (DS39716)

PIC24FJ64GB004 family devices include several

features intended to maximize application flexibility and

reliability, and minimize cost through elimination of

external components. These are:

Note:

Configuration data is reloaded on all types

of device Resets.

• Flexible Configuration

• Watchdog Timer (WDT)

• Code Protection

When creating applications for these devices, users

should always specifically allocate the location of the

Flash Configuration Word for configuration data. This is

to make certain that program code is not stored in this

address when the code is compiled.

• JTAG Boundary Scan Interface

• In-Circuit Serial Programming

• In-Circuit Emulation

The upper byte of all Flash Configuration Words in

program memory should always be ‘1111 1111’. This

makes them appear to be NOP instructions in the

remote event that their locations are ever executed by

accident. Since Configuration bits are not implemented

in the corresponding locations, writing ‘1’s to these

locations has no effect on device operation.

26.1 Configuration Bits

The Configuration bits can be programmed (read as ‘0’),

or left unprogrammed (read as ‘1’), to select various

device configurations. These bits are mapped starting at

program memory location F80000h. A detailed explana-

tion of the various bit functions is provided in

Register 26-1 through Register 26-6.

Note:

Performing a page erase operation on the

last page of program memory clears the

Flash Configuration Words, enabling code

protection as a result. Therefore, users

should avoid performing page erase

operations on the last page of program

memory.

Note that address F80000h is beyond the user program

memory space. In fact, it belongs to the configuration

memory space (800000h-FFFFFFh) which can only be

accessed using table reads and table writes.

TABLE 26-1: FLASH CONFIGURATION WORD LOCATIONS FOR PIC24FJ64GB004 FAMILY

DEVICES

Configuration Word Addresses

Device

1

2

3

4

PIC24FJ32GB00X

PIC24FJ64GB00X

57FEh

ABFEh

57FCh

ABFCh

57FAh

ABFAh

57F8h

ABF8h

 2010 Microchip Technology Inc.

DS39940D-page 279

PIC24FJ64GB004 FAMILY

REGISTER 26-1: CW1: FLASH CONFIGURATION WORD 1

U-1

—

U-1

—

U-1

—

U-1

—

U-1

—

U-1

—

U-1

—

U-1

—

bit 23

bit 16

r-x

r

R/PO-1

JTAGEN⁽¹⁾

R/PO-1

GCP

R/PO-1

GWRP

R/PO-1

DEBUG

U-1

—

R/PO-1

ICS1

R/PO-1

ICS0

bit 15

bit 8

R/PO-1

WINDIS

U-1

—

R/PO-1

FWPSA

R/PO-1

FWDTEN

WDTPS3

WDTPS2

WDTPS1

WDTPS0

bit 7

bit 0

Legend:

R = Readable bit

-n = Value when device is unprogrammed

r = Reserved bit

PO = Program Once bit

U = Unimplemented bit, read as ‘0’

‘1’ = Bit is set ‘0’ = Bit is cleared

bit 23-16

bit 15

Unimplemented: Read as ‘1’

Reserved: The value is unknown; program as ‘0’

JTAGEN: JTAG Port Enable bit⁽¹⁾

bit 14

1= JTAG port is enabled

0= JTAG port is disabled

bit 13

bit 12

bit 11

GCP: General Segment Program Memory Code Protection bit

1= Code protection is disabled

0= Code protection is enabled for the entire program memory space

GWRP: General Segment Code Flash Write Protection bit

1= Writes to program memory are allowed

0= Writes to program memory are disabled

DEBUG: Background Debugger Enable bit

1= Device resets into Operational mode

0= Device resets into Debug mode

bit 10

Unimplemented: Read as ‘1’

bit 9-8

ICS<1:0>: Emulator Pin Placement Select bits

11= Emulator functions are shared with PGEC1/PGED1

10= Emulator functions are shared with PGEC2/PGED2

01= Emulator functions are shared with PGEC3/PGED3

00= Reserved; do not use

bit 7

bit 6

FWDTEN: Watchdog Timer Enable bit

1= Watchdog Timer is enabled

0= Watchdog Timer is disabled

WINDIS: Windowed Watchdog Timer Disable bit

1= Standard Watchdog Timer is enabled

0= Windowed Watchdog Timer is enabled; FWDTEN must be ‘1’

bit 5

bit 4

Unimplemented: Read as ‘1’

FWPSA: WDT Prescaler Ratio Select bit

1= Prescaler ratio of 1:128

0= Prescaler ratio of 1:32

Note 1: The JTAGEN bit can only be modified using In-Circuit Serial Programming™ (ICSP™). It cannot be

modified while connected through the JTAG interface.

DS39940D-page 280

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PIC24FJ64GB004 FAMILY

REGISTER 26-1: CW1: FLASH CONFIGURATION WORD 1 (CONTINUED)

bit 3-0 WDTPS<3:0>: Watchdog Timer Postscaler Select bits

1111= 1:32,768

1110= 1:16,384

1101= 1:8,192

1100= 1:4,096

1011= 1:2,048

1010= 1:1,024

1001= 1:512

1000= 1:256

0111= 1:128

0110= 1:64

0101= 1:32

0100= 1:16

0011= 1:8

0010= 1:4

0001= 1:2

0000= 1:1

Note 1: The JTAGEN bit can only be modified using In-Circuit Serial Programming™ (ICSP™). It cannot be

modified while connected through the JTAG interface.

 2010 Microchip Technology Inc.

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REGISTER 26-2: CW2: FLASH CONFIGURATION WORD 2

U-1

—

U-1

—

U-1

—

U-1

—

U-1

—

U-1

—

U-1

—

U-1

—

bit 23

bit 16

R/PO-1

IESO

R/PO-1

PLLDIV2

PLLDIV1

PLLDIV0

PLL96MHZ

FNOSC2

FNOSC1

FNOSC0

bit 15

bit 8

R/PO-1

U-1

—

R/PO-1

FCKSM1

FCKSM0

OSCIOFCN

IOL1WAY

I2C1SEL

POSCMD1

POSCMD0

bit 7

bit 0

Legend:

R = Readable bit

PO = Program Once bit

U = Unimplemented bit, read as ‘0’

‘1’ = Bit is set ‘0’ = Bit is cleared

-n = Value when device is unprogrammed

bit 23-16

bit 15

Unimplemented: Read as ‘1’

IESO: Internal External Switchover bit

1= IESO mode (Two-Speed Start-up) is enabled

0= IESO mode (Two-Speed Start-up) is disabled

bit 14-12

PLLDIV<2:0>: USB 96 MHz PLL Prescaler Select bits

111= Oscillator input divided by 12 (48 MHz input)

110= Oscillator input divided by 8 (32 MHz input)

101= Oscillator input divided by 6 (24 MHz input)

100= Oscillator input divided by 5 (20 MHz input)

011= Oscillator input divided by 4 (16 MHz input)

010= Oscillator input divided by 3 (12 MHz input)

001= Oscillator input divided by 2 (8 MHz input)

000= Oscillator input used directly (4 MHz input)

bit 11

PLL96MHZ: USB 96 MHz PLL Start-up Enable bit

1= 96 MHz PLL is enabled automatically on start-up

0= 96 MHz PLL is enabled by user in software (controlled with the PLLEN bit in CLKDIV<5>)

FNOSC<2:0>: Initial Oscillator Select bits

bit 10-8

111= Fast RC Oscillator with Postscaler (FRCDIV)

110= Reserved

101= Low-Power RC Oscillator (LPRC)

100= Secondary Oscillator (SOSC)

011= Primary Oscillator with PLL module (XTPLL, HSPLL, ECPLL)

010= Primary Oscillator (XT, HS, EC)

001= Fast RC Oscillator with Postscaler and PLL module (FRCPLL)

000= Fast RC Oscillator (FRC)

bit 7-6

bit 5

FCKSM<1:0>: Clock Switching and Fail-Safe Clock Monitor Configuration bits

1x= Clock switching and Fail-Safe Clock Monitor are disabled

01= Clock switching is enabled, Fail-Safe Clock Monitor is disabled

00= Clock switching is enabled, Fail-Safe Clock Monitor is enabled

OSCIOFCN: OSCO Pin Configuration bit

If POSCMD<1:0> = 11 or 00:

1= OSCO/CLKO/RA3 functions as CLKO (FOSC/2)

0= OSCO/CLKO/RA3 functions as port I/O (RC15)

If POSCMD<1:0> = 10 or 01:

OSCIOFCN has no effect on OSCO/CLKO/RA3.

DS39940D-page 282

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PIC24FJ64GB004 FAMILY

REGISTER 26-2: CW2: FLASH CONFIGURATION WORD 2 (CONTINUED)

bit 4

IOL1WAY: IOLOCK One-Way Set Enable bit

1= The IOLOCK bit (OSCCON<6>) can be set once, provided the unlock sequence has been

completed. Once set, the Peripheral Pin Select registers cannot be written to a second time.

0= The IOLOCK bit can be set and cleared as needed, provided the unlock sequence has been

completed

bit 3

bit 2

Unimplemented: Read as ‘1’

I2C1SEL: I2C1 Pin Select bit

1= Use default SCL1/SDA1 pins

0= Use alternate SCL1/SDA1 pins

bit 1-0

POSCMD<1:0>: Primary Oscillator Configuration bits

11= Primary Oscillator is disabled

10= HS Oscillator mode is selected

01= XT Oscillator mode is selected

00= EC Oscillator mode is selected

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REGISTER 26-3: CW3: FLASH CONFIGURATION WORD 3

U-1

—

U-1

—

U-1

—

U-1

—

U-1

—

U-1

—

U-1

—

U-1

—

bit 23

bit 16

R/PO-1

WPDIS

U-1

—

R/PO-1

SOSCSEL0⁽¹⁾

bit 8

(1)

WPEND

WPCFG

WUTSEL1

WUTSEL0 SOSCSEL1

bit 15

U-1

—

U-1

—

R/PO-1

WPFP5

R/PO-1

WPFP4

R/PO-1

WPFP3

R/PO-1

WPFP2

R/PO-1

WPFP1

R/PO-1

WPFP0

bit 0

bit 7

Legend:

R = Readable bit

PO = Program Once bit

U = Unimplemented bit, read as ‘0’

‘1’ = Bit is set ‘0’ = Bit is cleared

-n = Value when device is unprogrammed

bit 23-16

bit 15

Unimplemented: Read as ‘1’

WPEND: Segment Write Protection End Page Select bit

1= Protected code segment lower boundary is at the bottom of program memory (000000h); upper

boundary is the code page specified by WPFP<8:0>

0= Protected code segment upper boundary is at the last page of program memory; lower boundary

is the code page specified by WPFP<8:0>

bit 14

bit 13

WPCFG: Configuration Word Code Page Protection Select bit

1= Last page (at the top of program memory) and Flash Configuration Words are not protected

0= Last page and Flash Configuration Words are code-protected

WPDIS: Segment Write Protection Disable bit

1= Segmented code protection is disabled

0= Segmented code protection is enabled; protected segment is defined by WPEND, WPCFG and

WPFPx Configuration bits

bit 12

Unimplemented: Read as ‘1’

bit 11-10

WUTSEL<1:0>: Voltage Regulator Standby Mode Wake-up Time Select bits

11= Default regulator start-up time is used

01= Fast regulator start-up time is used

x0= Reserved; do not use

bit 9-8

SOSCSEL<1:0>: Secondary Oscillator Power Mode Select bits⁽¹⁾

11= SOSC pins are in default (high drive strength) oscillator mode

01= SOSC pins are in Low-Power (low drive strength) Oscillator mode

00= SOSC pins have digital I/O functions (RA4, RB4); SCLKI can be used

10= Reserved

bit 7-6

bit 5-0

Unimplemented: Read as ‘1’

WPFP<5:0>: Protected Code Segment Boundary Page bits

Designates the 512 instruction page that is the boundary of the protected code segment, starting with

Page 9 at the bottom of program memory.

If WPEND = 1:

Last address of designated code page is the upper boundary of the segment.

If WPEND = 0:

First address of designated code page is the lower boundary of the segment.

Note 1: Digital functions on the SOSCI and SOSCO pins are only available when configured in Digital I/O mode (‘00’).

DS39940D-page 284

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PIC24FJ64GB004 FAMILY

REGISTER 26-4: CW4: FLASH CONFIGURATION WORD 4

U-1

—

U-1

—

U-1

—

U-1

—

U-1

—

U-1

—

U-1

—

U-1

—

bit 23

bit 16

U-1

—

U-1

—

U-1

—

U-1

—

U-1

—

U-1

—

U-1

—

U-1

—

bit 15

bit 8

R/PO-1

DSWDTEN

bit 7

R/PO-1

DSBOREN

RTCOSC

DSWDTOSC DSWDTPS3 DSWDTPS2 DSWDTPS1 DSWDTPS0

bit 0

Legend:

R = Readable bit

PO = Program Once bit

U = Unimplemented bit, read as ‘0’

‘1’ = Bit is set ‘0’ = Bit is cleared

-n = Value when device is unprogrammed

bit 23-8

bit 7

Unimplemented: Read as ‘1’

DSWDTEN: Deep Sleep Watchdog Timer Enable bit

1= DSWDT is enabled

0= DSWDT is disabled

bit 6

DSBOREN: Deep Sleep BOR Enable bit

1= BOR is enabled in Deep Sleep

0= BOR is disabled in Deep Sleep (does not affect Sleep mode)

bit 5

RTCOSC: RTCC Reference Clock Select bit

1= RTCC uses SOSC as reference clock

0= RTCC uses LPRC as reference clock

bit 4

DSWDTOSC: DSWDT Reference Clock Select bit

1= DSWDT uses LPRC as reference clock

0= DSWDT uses SOSC as reference clock

bit 3-0

DSWDTPS<3:0>: DSWDT Postscale select bits

The DSWDT prescaler is 32; this creates an approximate base time unit of 1 ms.

1111= 1:2,147,483,648 (25.7 days)

1110= 1:536,870,912 (6.4 days)

1101= 1:134,217,728 (38.5 hours)

1100= 1:33,554,432 (9.6 hours)

1011= 1:8,388,608 (2.4 hours)

1010= 1:2,097,152 (36 minutes)

1001= 1:524,288 (9 minutes)

1000= 1:131,072 (135 seconds)

0111= 1:32,768 (34 seconds)

0110= 1:8,192 (8.5 seconds)

0101= 1:2,048 (2.1 seconds)

0100= 1:512 (528 ms)

0011= 1:128 (132 ms)

0010= 1:32 (33 ms)

0001= 1:8 (8.3 ms)

0000= 1:2 (2.1 ms)

 2010 Microchip Technology Inc.

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PIC24FJ64GB004 FAMILY

REGISTER 26-5: DEVID: DEVICE ID REGISTER

U

—

bit 23

bit 16

R

FAMID7

bit 15

FAMID6

FAMID5

FAMID4

FAMID3

FAMID2

FAMID1

FAMID0

bit 8

R

DEV7

DEV6

DEV5

DEV4

DEV3

DEV2

DEV1

DEV0

bit 7

bit 0

Legend: R = Read-Only bit

U = Unimplemented bit

bit 23-16

bit 15-8

Unimplemented: Read as ‘1’

FAMID<7:0>: Device Family Identifier bits

01000010= PIC24FJ64GB004 family

DEV<7:0>: Individual Device Identifier bits

bit 7-0

00000011= PIC24FJ32GB002

00000111= PIC24FJ64GB002

00001011= PIC24FJ32GB004

00001111= PIC24FJ64GB004

REGISTER 26-6: DEVREV: DEVICE REVISION REGISTER

U

—

bit 23

bit 15

bit 7

bit 16

U

—

bit 8

U

R

—

REV3

REV2

REV1

REV0

bit 0

Legend: R = Read-only bit

U = Unimplemented bit

bit 23-4

bit 3-0

Unimplemented: Read as ‘0’

REV<3:0>: Minor Revision Identifier bits

Encodes revision number of the device (sequential number only; no major/minor fields).

DS39940D-page 286

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PIC24FJ64GB004 FAMILY

FIGURE 26-1:

CONNECTIONS FOR THE

ON-CHIP REGULATOR

26.2 On-Chip Voltage Regulator

All PIC24FJ64GB004 family devices power their core

digital logic at a nominal 2.5V. This may create an issue

for designs that are required to operate at a higher

typical voltage, such as 3.3V. To simplify system

design, all devices in the PIC24FJ64GB004 family

incorporate an on-chip regulator that allows the device

to run its core logic from VDD.

Regulator Enabled (DISVREG tied to VSS):

3.3V

PIC24FJ64GB004

VDD

DISVREG

VDDCORE/VCAP

CEFC

(10 F typ)

The regulator is controlled by the DISVREG pin. Tying VSS

to the pin enables the regulator, which in turn, provides

power to the core from the other VDD pins. When the reg-

ulator is enabled, a low-ESR capacitor (such as ceramic)

VSS

must be connected to the

VDDCORE/VCAP pin

(Figure 26-1). This helps to maintain the stability of the

regulator. The recommended value for the Filter Capacitor

Regulator Disabled (DISVREG tied to VDD):

(1)

2.5V

3.3V

(CEFC) is provided in Section 29.1 “DC Characteristics”

.

PIC24FJ64GB004

If DISVREG is tied to VDD, the regulator is disabled. In

this case, separate power for the core logic, at a nomi-

nal 2.5V, must be supplied to the device on the

VDDCORE/VCAP pin to run the I/O pins at higher voltage

levels, typically 3.3V. Alternatively, the VDDCORE/VCAP

and VDD pins can be tied together to operate at a lower

nominal voltage. Refer to Figure 26-1 for possible

configurations.

VDD

DISVREG

VDDCORE/VCAP

VSS

Regulator Disabled (VDD tied to VDDCORE):

26.2.1

VOLTAGE REGULATOR TRACKING

MODE AND LOW-VOLTAGE

DETECTION

(1)

2.5V

PIC24FJ64GB004

VDD

When it is enabled, the on-chip regulator provides a

constant voltage of 2.5V nominal to the digital core

logic.

DISVREG

VDDCORE/VCAP

VSS

The regulator can provide this level from a VDD of about

2.5V, all the way up to the device’s VDDMAX. It does not

have the capability to boost VDD levels below 2.5V. In

order to prevent “brown-out” conditions when the volt-

age drops too low for the regulator, the regulator enters

Tracking mode. In Tracking mode, the regulator output

follows VDD with a typical voltage drop of 100 mV.

Note 1: These are typical operating voltages. Refer

to Section 29.1 “DC Characteristics” for

the full operating ranges of VDD and

VDDCORE.

When the device enters Tracking mode, it is no longer

possible to operate at full speed. To provide information

about when the device enters Tracking mode, the

on-chip regulator includes a simple, Low-Voltage

Detect circuit. When VDD drops below full-speed oper-

ating voltage, the circuit sets the Low-Voltage Detect

Interrupt Flag, LVDIF (IFS4<8>). This can be used to

generate an interrupt and put the application into a

Low-Power Operational mode or trigger an orderly

shutdown.

26.2.2

ON-CHIP REGULATOR AND POR

When the voltage regulator is enabled, it takes approxi-

mately 10 s for it to generate output. During this time,

designated as TPM, code execution is disabled. TPM is

applied every time the device resumes operation after

any power-down, including Sleep mode. TPM is

determined by the setting of the PMSLP bit (RCON<8>)

and the WUTSEL Configuration bits (CW3<11:10>).

Low-Voltage Detection is only available when the

regulator is enabled.

Note:

For more information on TPM, see

Section 29.0 “Electrical Characteristics”.

If the regulator is disabled, a separate Power-up Timer

(PWRT) is automatically enabled. The PWRT adds a

fixed delay of 64 ms nominal delay at device start-up

(POR or BOR only).

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When waking up from Sleep mode with the regulator

26.3 Watchdog Timer (WDT)

disabled, TPM is used to determine the wake-up time.

To decrease the device wake-up time when operating

with the regulator disabled, the PMSLP bit can be set.

For PIC24FJ64GB004 family devices, the WDT is

driven by the LPRC Oscillator. When the WDT is

enabled, the clock source is also enabled.

26.2.3

When

ON-CHIP REGULATOR AND BOR

the on-chip regulator is enabled,

The nominal WDT clock source from LPRC is 31 kHz.

This feeds a prescaler that can be configured for either

5-bit (divide-by-32) or 7-bit (divide-by-128) operation.

The prescaler is set by the FWPSA Configuration bit.

With a 31 kHz input, the prescaler yields a nominal

WDT time-out period (TWDT) of 1 ms in 5-bit mode, or

4 ms in 7-bit mode.

PIC24FJ64GB004 family devices also have a simple

brown-out capability. If the voltage supplied to the regu-

lator is inadequate to maintain the tracking level, the

regulator Reset circuitry will generate a Brown-out

Reset. This event is captured by the BOR flag bit

(RCON<1>). The brown-out voltage specifications are

provided in Section 29.0 “Electrical Characteristics”.

A variable postscaler divides down the WDT prescaler

output and allows for a wide range of time-out periods.

The postscaler is controlled by the WDTPS<3:0>

Configuration bits (CW1<3:0>), which allow the selec-

tion of a total of 16 settings, from 1:1 to 1:32,768. Using

the prescaler and postscaler time-out periods, ranging

from 1 ms to 131 seconds can be achieved.

26.2.4

POWER-UP REQUIREMENTS

The on-chip regulator is designed to meet the power-up

requirements for the device. If the application does not

use the regulator, then strict power-up conditions must

be adhered to. While powering up, VDDCORE must

never exceed VDD by 0.3 volts.

The WDT, prescaler and postscaler are reset:

• On any device Reset

Note:

For more information, see Section 29.0

“Electrical Characteristics”.

• On the completion of a clock switch, whether

invoked by software (i.e., setting the OSWEN bit

after changing the NOSC bits) or by hardware

(i.e., Fail-Safe Clock Monitor)

26.2.5

VOLTAGE REGULATOR STANDBY

MODE

• When a PWRSAVinstruction is executed

When enabled, the on-chip regulator always consumes

a small incremental amount of current over IDD/IPD,

including when the device is in Sleep mode, even

though the core digital logic does not require power. To

provide additional savings in applications where power

resources are critical, the regulator automatically

places itself into Standby mode whenever the device

goes into Sleep mode by removing power from the

Flash program memory. This feature is controlled by

the PMSLP bit (RCON<8>). By default, this bit is

cleared, which enables Standby mode.

(i.e., Sleep or Idle mode is entered)

• When the device exits Sleep or Idle mode to

resume normal operation

• By a CLRWDTinstruction during normal execution

If the WDT is enabled, it will continue to run during

Sleep or Idle modes. When the WDT time-out occurs,

the device will wake the device and code execution will

continue from where the PWRSAV instruction was

executed. The corresponding SLEEP or IDLE bits

(RCON<3:2>) will need to be cleared in software after

the device wakes up.

For PIC24FJ64GB004 family devices, the time

required for regulator wake-up from Standby mode is

controlled by the WUTSEL<1:0> Configuration bits

(CW3<11:10>). The default wake-up time for all

devices is 190 s, which is a Legacy mode provided to

match older PIC24F device wake-up times.

The WDT Flag bit, WDTO (RCON<4>), is not auto-

matically cleared following a WDT time-out. To detect

subsequent WDT events, the flag must be cleared in

software.

Note:

The CLRWDT and PWRSAV instructions

clear the prescaler and postscaler counts

when executed.

Implementing the WUTSEL Configuration bits provides

a fast wake-up option. When WUTSEL<1:0> = 01, the

regulator wake-up time is TPM, 10 s.

When the regulator’s Standby mode is turned off

(PMSLP = 1), Flash program memory stays powered in

Sleep mode. That enables device wake-up without

waiting for TPM. With PMSLP set, however, the power

consumption, while in Sleep mode, will be

approximately 40 A higher than what it would be if the

regulator was allowed to enter Standby mode.

DS39940D-page 288

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26.3.1

WINDOWED OPERATION

26.3.2

CONTROL REGISTER

The Watchdog Timer has an optional Fixed Window

mode of operation. In this Windowed mode, CLRWDT

instructions can only reset the WDT during the last 1/4

of the programmed WDT period. A CLRWDTinstruction

is executed before that window causes a WDT Reset;

this is similar to a WDT time-out.

The WDT is enabled or disabled by the FWDTEN

Configuration bit. When the FWDTEN Configuration bit

is set, the WDT is always enabled.

The WDT can be optionally controlled in software when

the FWDTEN Configuration bit has been programmed

to ‘0’. The WDT is enabled in software by setting the

SWDTEN control bit (RCON<5>). The SWDTEN

control bit is cleared on any device Reset. The WDT

software option allows the user to enable the WDT for

critical code segments, and disable the WDT during

non-critical segments, for maximum power savings.

Windowed WDT mode is enabled by programming the

WINDIS Configuration bit (CW1<6>) to ‘0’.

FIGURE 26-2:

WDT BLOCK DIAGRAM

SWDTEN

FWDTEN

LPRC Control

Wake From Sleep

FWPSA

WDTPS<3:0>

Prescaler

(5-bit/7-bit)

WDT

Counter

Postscaler

WDT Overflow

1:1 to 1:32.768

LPRC Input

Reset

31 kHz

1 ms/4 ms

All Device Resets

Transition to

New Clock Source

Exit Sleep or

Idle Mode

CLRWDTInstr.

PWRSAVInstr.

Sleep or Idle Mode

26.4 Deep Sleep Watchdog Timer

(DSWDT)

26.5 Program Verification and

Code Protection

PIC24FJ64GB004 family devices have both a WDT

module and a DSWDT module. The latter runs, if

enabled, when a device is in Deep Sleep and is driven

by either the SOSC or LPRC Oscillator. The clock

source is selected by the DSWDTOSC (CW4<4>)

Configuration bit.

PIC24FJ64GB004 family devices provide two compli-

mentary methods to protect application code from

overwrites and erasures. These also help to protect the

device from inadvertent configuration changes during

run time.

26.5.1

GENERAL SEGMENT PROTECTION

The DSWDT can be configured to generate a time-out

at 2.1 ms to 25.7 days by selecting the respective

postscaler. The postscaler can be selected by the

Configuration bits, DSWDTPS<3:0> (CW4<3:0>).

When the DSWDT is enabled, the clock source is also

enabled. DSWDT is one of the sources that can wake

the device from Deep Sleep mode.

For all devices in the PIC24FJ64GB004 family, the

on-chip program memory space is treated as a single

block, known as the General Segment (GS). Code pro-

tection for this block is controlled by one Configuration

bit, GCP. This bit inhibits external reads and writes to

the program memory space. It has no direct effect in

normal execution mode.

Write protection is controlled by the GWRP bit in the

Configuration Word. When GWRP is programmed to

‘0’, internal write and erase operations to program

memory are blocked.

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A separate bit, WPCFG, is used to independently protect

the last page of program space, including the Flash Con-

figuration Words. Programming WPCFG (= 0) protects

the last page, regardless of the other bit settings. This

may be useful in circumstances where write protection is

needed for both a code segment in the bottom of

memory, as well as the Flash Configuration Words.

26.5.2

CODE SEGMENT PROTECTION

In addition to global General Segment protection, a

separate subrange of the program memory space can

be individually protected against writes and erases.

This area can be used for many purposes where a sep-

arate block of erase and write-protected code is

needed, such as bootloader applications. Unlike

common boot block implementations, the specially

protected segment in the PIC24FJ64GB004 family

devices can be located by the user anywhere in the

program space and configured in a wide range of sizes.

The various options for segment code protection are

shown in Table 26-2.

26.5.3

CONFIGURATION REGISTER

PROTECTION

Code segment protection provides an added level of

protection to a designated area of program memory, by

disabling the NVM safety interlock, whenever a write or

erase address falls within a specified range. It does not

override General Segment protection controlled by the

GCP or GWRP bits. For example, if GCP and GWRP

are enabled, enabling segmented code protection for

the bottom half of program memory does not undo

General Segment protection for the top half.

The Configuration registers are protected against

inadvertent or unwanted changes, or reads in two

ways. The primary protection method is the same as

that of the RP registers – shadow registers contain a

complimentary value which is constantly compared

with the actual value.

To safeguard against unpredictable events, Configura-

tion bit changes resulting from individual cell level

disruptions (such as ESD events) will cause a parity

error and trigger a device Reset.

The size and type of protection for the segmented code

range are configured by the WPFPx, WPEND, WPCFG

and WPDIS bits in Configuration Word 3. Code seg-

ment protection is enabled by programming the WPDIS

bit (= 0). The WPFP bits specify the size of the segment

to be protected by specifying the 512-word code page

that is the start or end of the protected segment. The

specified region is inclusive, therefore, this page will

also be protected.

The data for the Configuration registers is derived from

the Flash Configuration Words in program memory.

When the GCP bit is set, the source data for device

configuration is also protected as a consequence. Even

if General Segment protection is not enabled, the

device configuration can be protected by using the

appropriate code cement protection setting.

The WPEND bit determines if the protected segment

uses the top or bottom of the program space as a

boundary. Programming WPEND (= 0) sets the bottom

of program memory (000000h) as the lower boundary

of the protected segment. Leaving WPEND unpro-

grammed (= 1) protects the specified page through the

last page of implemented program memory, including

the Configuration Word locations.

TABLE 26-2: SEGMENT CODE PROTECTION CONFIGURATION OPTIONS

Segment Configuration Bits

Write/Erase Protection of Code Segment

WPDIS

WPEND

WPCFG

1

x

1

No additional protection enabled; all program memory protection is configured

by GCP and GWRP

1

0

x

1

0

Last code page protected, including Flash Configuration Words

Addresses from the first address of code page, defined by WPFP<5:0> through

the end of implemented program memory (inclusive), are protected, including

Flash Configuration Words

0

1

0

1

Address, 000000h, through the last address of code page, defined by

WPFP<5:0> (inclusive) is protected

Addresses from first address of code page, defined by WPFP<5:0> through the

end of implemented program memory (inclusive), are protected, including Flash

Configuration Words

0

1

Addresses from first address of code page, defined by WPFP<5:0> through the

end of implemented program memory (inclusive), are protected

DS39940D-page 290

 2010 Microchip Technology Inc.

PIC24FJ64GB004 FAMILY

26.6 JTAG Interface

26.8 In-Circuit Debugger

PIC24FJ64GB004 family devices implement a JTAG

interface, which supports boundary scan device

testing.

When MPLAB^®ICD 2 is selected as a debugger, the

in-circuit debugging functionality is enabled. This func-

tion allows simple debugging functions when used with

MPLAB IDE. Debugging functionality is controlled

through the PGECx (Emulation/Debug Clock) and

PGEDx (Emulation/Debug Data) pins.

26.7

In-Circuit Serial Programming

PIC24FJ64GB004 family microcontrollers can be seri-

ally programmed while in the end application circuit.

This is simply done with two lines for clock (PGECx)

and data (PGEDx), and three other lines for power,

ground and the programming voltage. This allows cus-

tomers to manufacture boards with unprogrammed

devices and then program the microcontroller just

before shipping the product. This also allows the most

To use the in-circuit debugger function of the device,

the design must implement ICSP connections to

MCLR, VDD, VSS and the PGECx/PGEDx pin pair des-

ignated by the ICS Configuration bits. In addition, when

the feature is enabled, some of the resources are not

available for general use. These resources include the

first 80 bytes of data RAM and two I/O pins.

recent firmware or

programmed.

a

custom firmware to be

 2010 Microchip Technology Inc.

DS39940D-page 291

PIC24FJ64GB004 FAMILY

NOTES:

DS39940D-page 292

 2010 Microchip Technology Inc.

PIC24FJ64GB004 FAMILY

27.1 MPLAB Integrated Development

Environment Software

27.0 DEVELOPMENT SUPPORT

The PIC^®microcontrollers and dsPIC^®digital signal

controllers are supported with a full range of software

and hardware development tools:

The MPLAB IDE software brings an ease of software

development previously unseen in the 8/16/32-bit

microcontroller market. The MPLAB IDE is a Windows^®

operating system-based application that contains:

• Integrated Development Environment

- MPLAB^®IDE Software

• A single graphical interface to all debugging tools

- Simulator

• Compilers/Assemblers/Linkers

- MPLAB C Compiler for Various Device

Families

- Programmer (sold separately)

- In-Circuit Emulator (sold separately)

- In-Circuit Debugger (sold separately)

• A full-featured editor with color-coded context

• A multiple project manager

- HI-TECH C for Various Device Families

- MPASM^TMAssembler

- MPLINK^TMObject Linker/

MPLIB^TMObject Librarian

- MPLAB Assembler/Linker/Librarian for

Various Device Families

• Customizable data windows with direct edit of

contents

• Simulators

• High-level source code debugging

• Mouse over variable inspection

- MPLAB SIM Software Simulator

• Emulators

• Drag and drop variables from source to watch

windows

- MPLAB REAL ICE™ In-Circuit Emulator

• In-Circuit Debuggers

• Extensive on-line help

• Integration of select third party tools, such as

IAR C Compilers

- MPLAB ICD 3

- PICkit™ 3 Debug Express

• Device Programmers

- PICkit™ 2 Programmer

- MPLAB PM3 Device Programmer

The MPLAB IDE allows you to:

• Edit your source files (either C or assembly)

• One-touch compile or assemble, and download to

emulator and simulator tools (automatically

updates all project information)

• Low-Cost Demonstration/Development Boards,

Evaluation Kits, and Starter Kits

• Debug using:

- Source files (C or assembly)

- Mixed C and assembly

- Machine code

MPLAB IDE supports multiple debugging tools in a

single development paradigm, from the cost-effective

simulators, through low-cost in-circuit debuggers, to

full-featured emulators. This eliminates the learning

curve when upgrading to tools with increased flexibility

and power.

 2010 Microchip Technology Inc.

DS39940D-page 293

PIC24FJ64GB004 FAMILY

27.2 MPLAB C Compilers for Various

Device Families

27.5 MPLINK Object Linker/

MPLIB Object Librarian

The MPLAB C Compiler code development systems

are complete ANSI C compilers for Microchip’s PIC18,

PIC24 and PIC32 families of microcontrollers and the

dsPIC30 and dsPIC33 families of digital signal control-

lers. These compilers provide powerful integration

capabilities, superior code optimization and ease of

use.

The MPLINK Object Linker combines relocatable

objects created by the MPASM Assembler and the

MPLAB C18 C Compiler. It can link relocatable objects

from precompiled libraries, using directives from a

linker script.

The MPLIB Object Librarian manages the creation and

modification of library files of precompiled code. When

a routine from a library is called from a source file, only

the modules that contain that routine will be linked in

with the application. This allows large libraries to be

used efficiently in many different applications.

For easy source level debugging, the compilers provide

symbol information that is optimized to the MPLAB IDE

debugger.

27.3 HI-TECH C for Various Device

Families

The object linker/library features include:

• Efficient linking of single libraries instead of many

smaller files

The HI-TECH C Compiler code development systems

are complete ANSI C compilers for Microchip’s PIC

family of microcontrollers and the dsPIC family of digital

signal controllers. These compilers provide powerful

integration capabilities, omniscient code generation

and ease of use.

• Enhanced code maintainability by grouping

related modules together

• Flexible creation of libraries with easy module

listing, replacement, deletion and extraction

27.6 MPLAB Assembler, Linker and

Librarian for Various Device

Families

For easy source level debugging, the compilers provide

symbol information that is optimized to the MPLAB IDE

debugger.

The compilers include a macro assembler, linker, pre-

processor, and one-step driver, and can run on multiple

platforms.

MPLAB Assembler produces relocatable machine

code from symbolic assembly language for PIC24,

PIC32 and dsPIC devices. MPLAB C Compiler uses

the assembler to produce its object file. The assembler

generates relocatable object files that can then be

archived or linked with other relocatable object files and

archives to create an executable file. Notable features

of the assembler include:

27.4 MPASM Assembler

The MPASM Assembler is a full-featured, universal

macro assembler for PIC10/12/16/18 MCUs.

The MPASM Assembler generates relocatable object

files for the MPLINK Object Linker, Intel^®standard HEX

files, MAP files to detail memory usage and symbol

reference, absolute LST files that contain source lines

and generated machine code and COFF files for

debugging.

• Support for the entire device instruction set

• Support for fixed-point and floating-point data

• Command line interface

• Rich directive set

• Flexible macro language

The MPASM Assembler features include:

• Integration into MPLAB IDE projects

• MPLAB IDE compatibility

• User-defined macros to streamline

assembly code

• Conditional assembly for multi-purpose

source files

• Directives that allow complete control over the

assembly process

DS39940D-page 294

 2010 Microchip Technology Inc.

PIC24FJ64GB004 FAMILY

27.7 MPLAB SIM Software Simulator

27.9 MPLAB ICD 3 In-Circuit Debugger

System

The MPLAB SIM Software Simulator allows code

development in a PC-hosted environment by simulat-

ing the PIC MCUs and dsPIC^®DSCs on an instruction

level. On any given instruction, the data areas can be

examined or modified and stimuli can be applied from

a comprehensive stimulus controller. Registers can be

logged to files for further run-time analysis. The trace

buffer and logic analyzer display extend the power of

the simulator to record and track program execution,

actions on I/O, most peripherals and internal registers.

MPLAB ICD 3 In-Circuit Debugger System is Micro-

chip's most cost effective high-speed hardware

debugger/programmer for Microchip Flash Digital Sig-

nal Controller (DSC) and microcontroller (MCU)

devices. It debugs and programs PIC^®Flash microcon-

trollers and dsPIC^®DSCs with the powerful, yet easy-

to-use graphical user interface of MPLAB Integrated

Development Environment (IDE).

The MPLAB ICD 3 In-Circuit Debugger probe is con-

nected to the design engineer's PC using a high-speed

USB 2.0 interface and is connected to the target with a

connector compatible with the MPLAB ICD 2 or MPLAB

REAL ICE systems (RJ-11). MPLAB ICD 3 supports all

MPLAB ICD 2 headers.

The MPLAB SIM Software Simulator fully supports

symbolic debugging using the MPLAB C Compilers,

and the MPASM and MPLAB Assemblers. The soft-

ware simulator offers the flexibility to develop and

debug code outside of the hardware laboratory envi-

ronment, making it an excellent, economical software

development tool.

27.10 PICkit 3 In-Circuit Debugger/

Programmer and

27.8 MPLAB REAL ICE In-Circuit

Emulator System

PICkit 3 Debug Express

The MPLAB PICkit 3 allows debugging and program-

ming of PIC^®and dsPIC^®Flash microcontrollers at a

most affordable price point using the powerful graphical

user interface of the MPLAB Integrated Development

Environment (IDE). The MPLAB PICkit 3 is connected

to the design engineer's PC using a full speed USB

interface and can be connected to the target via an

Microchip debug (RJ-11) connector (compatible with

MPLAB ICD 3 and MPLAB REAL ICE). The connector

uses two device I/O pins and the reset line to imple-

ment in-circuit debugging and In-Circuit Serial Pro-

gramming™.

MPLAB REAL ICE In-Circuit Emulator System is

Microchip’s next generation high-speed emulator for

Microchip Flash DSC and MCU devices. It debugs and

programs PIC^®Flash MCUs and dsPIC^®Flash DSCs

with the easy-to-use, powerful graphical user interface of

the MPLAB Integrated Development Environment (IDE),

included with each kit.

The emulator is connected to the design engineer’s PC

using a high-speed USB 2.0 interface and is connected

to the target with either a connector compatible with in-

circuit debugger systems (RJ-11) or with the new high-

speed, noise tolerant, Low-Voltage Differential Signal

(LVDS) interconnection (CAT5).

The PICkit 3 Debug Express include the PICkit 3, demo

board and microcontroller, hookup cables and CDROM

with user’s guide, lessons, tutorial, compiler and

MPLAB IDE software.

The emulator is field upgradable through future firmware

downloads in MPLAB IDE. In upcoming releases of

MPLAB IDE, new devices will be supported, and new

features will be added. MPLAB REAL ICE offers signifi-

cant advantages over competitive emulators including

low-cost, full-speed emulation, run-time variable

watches, trace analysis, complex breakpoints, a rugge-

dized probe interface and long (up to three meters) inter-

connection cables.

 2010 Microchip Technology Inc.

DS39940D-page 295

PIC24FJ64GB004 FAMILY

27.11 PICkit 2 Development

Programmer/Debugger and

PICkit 2 Debug Express

27.13 Demonstration/Development

Boards, Evaluation Kits, and

Starter Kits

The PICkit™ 2 Development Programmer/Debugger is

a low-cost development tool with an easy to use inter-

face for programming and debugging Microchip’s Flash

families of microcontrollers. The full featured

Windows^®programming interface supports baseline

A wide variety of demonstration, development and

evaluation boards for various PIC MCUs and dsPIC

DSCs allows quick application development on fully func-

tional systems. Most boards include prototyping areas for

adding custom circuitry and provide application firmware

and source code for examination and modification.

(PIC10F,

PIC12F5xx,

PIC16F5xx),

midrange

(PIC12F6xx, PIC16F), PIC18F, PIC24, dsPIC30,

dsPIC33, and PIC32 families of 8-bit, 16-bit, and 32-bit

microcontrollers, and many Microchip Serial EEPROM

products. With Microchip’s powerful MPLAB Integrated

The boards support a variety of features, including LEDs,

temperature sensors, switches, speakers, RS-232

interfaces, LCD displays, potentiometers and additional

EEPROM memory.

Development Environment (IDE) the PICkit™

2

enables in-circuit debugging on most PIC^®microcon-

trollers. In-Circuit-Debugging runs, halts and single

steps the program while the PIC microcontroller is

embedded in the application. When halted at a break-

point, the file registers can be examined and modified.

The demonstration and development boards can be

used in teaching environments, for prototyping custom

circuits and for learning about various microcontroller

applications.

In addition to the PICDEM™ and dsPICDEM™ demon-

stration/development board series of circuits, Microchip

has a line of evaluation kits and demonstration software

The PICkit 2 Debug Express include the PICkit 2, demo

board and microcontroller, hookup cables and CDROM

with user’s guide, lessons, tutorial, compiler and

MPLAB IDE software.

®

for analog filter design, KEELOQ security ICs, CAN,

IrDA^®, PowerSmart battery management, SEEVAL^®

evaluation system, Sigma-Delta ADC, flow rate

sensing, plus many more.

27.12 MPLAB PM3 Device Programmer

Also available are starter kits that contain everything

needed to experience the specified device. This usually

includes a single application and debug capability, all

on one board.

The MPLAB PM3 Device Programmer is a universal,

CE compliant device programmer with programmable

voltage verification at VDDMIN and VDDMAX for

maximum reliability. It features a large LCD display

(128 x 64) for menus and error messages and a modu-

lar, detachable socket assembly to support various

package types. The ICSP™ cable assembly is included

as a standard item. In Stand-Alone mode, the MPLAB

PM3 Device Programmer can read, verify and program

PIC devices without a PC connection. It can also set

code protection in this mode. The MPLAB PM3

connects to the host PC via an RS-232 or USB cable.

The MPLAB PM3 has high-speed communications and

optimized algorithms for quick programming of large

memory devices and incorporates an MMC card for file

storage and data applications.

Check the Microchip web page (www.microchip.com)

for the complete list of demonstration, development

and evaluation kits.

DS39940D-page 296

 2010 Microchip Technology Inc.

PIC24FJ64GB004 FAMILY

The literal instructions that involve data movement may

use some of the following operands:

28.0 INSTRUCTION SET SUMMARY

Note:

This chapter is a brief summary of the

PIC24F instruction set architecture, and is

not intended to be a comprehensive

reference source.

• A literal value to be loaded into a W register or file

register (specified by the value of ‘k’)

• The W register or file register where the literal

value is to be loaded (specified by ‘Wb’ or ‘f’)

The PIC24F instruction set adds many enhancements

to the previous PIC^®MCU instruction sets, while main-

taining an easy migration from previous PIC MCU

instruction sets. Most instructions are a single program

memory word. Only three instructions require two

program memory locations.

However, literal instructions that involve arithmetic or

logical operations use some of the following operands:

• The first source operand, which is a register ‘Wb’

without any address modifier

• The second source operand, which is a literal

value

Each single-word instruction is a 24-bit word divided

into an 8-bit opcode, which specifies the instruction

type and one or more operands, which further specify

the operation of the instruction. The instruction set is

highly orthogonal and is grouped into four basic

categories:

• The destination of the result (only if not the same

as the first source operand), which is typically a

register ‘Wd’ with or without an address modifier

The control instructions may use some of the following

operands:

• Word or byte-oriented operations

• Bit-oriented operations

• Literal operations

• A program memory address

• The mode of the table read and table write

instructions

• Control operations

All instructions are a single word, except for certain

double-word instructions, which were made

double-word instructions so that all the required infor-

mation is available in these 48 bits. In the second word,

the 8 MSbs are ‘0’s. If this second word is executed as

an instruction (by itself), it will execute as a NOP.

Table 28-1 shows the general symbols used in

describing the instructions. The PIC24F instruction set

summary in Table 28-2 lists all of the instructions, along

with the status flags affected by each instruction.

Most word or byte-oriented W register instructions

(including barrel shift instructions) have three

operands:

Most single-word instructions are executed in a single

instruction cycle, unless a conditional test is true or the

program counter is changed as a result of the instruc-

tion. In these cases, the execution takes two instruction

cycles, with the additional instruction cycle(s) executed

as a NOP. Notable exceptions are the BRA (uncondi-

tional/computed branch), indirect CALL/GOTO, all table

reads and writes, and RETURN/RETFIE instructions,

which are single-word instructions but take two or three

cycles.

• The first source operand, which is typically a

register ‘Wb’ without any address modifier

• The second source operand, which is typically a

register ‘Ws’ with or without an address modifier

• The destination of the result, which is typically a

register ‘Wd’ with or without an address modifier

However, word or byte-oriented file register instructions

have two operands:

Certain instructions that involve skipping over the sub-

sequent instruction require either two or three cycles if

the skip is performed, depending on whether the

instruction being skipped is a single-word or two-word

instruction. Moreover, double-word moves require two

cycles. The double-word instructions execute in two

instruction cycles.

• The file register specified by the value, ‘f’

• The destination, which could either be the file

register, ‘f’, or the W0 register, which is denoted

as ‘WREG’

Most bit-oriented instructions (including simple

rotate/shift instructions) have two operands:

• The W register (with or without an address

modifier) or file register (specified by the value of

‘Ws’ or ‘f’)

• The bit in the W register or file register (specified

by a literal value or indirectly by the contents of

register, ‘Wb’)

 2010 Microchip Technology Inc.

DS39940D-page 297

PIC24FJ64GB004 FAMILY

TABLE 28-1: SYMBOLS USED IN OPCODE DESCRIPTIONS

Field

Description

#text

(text)

[text]

{ }

Means literal defined by “text”

Means “content of text”

Means “the location addressed by text”

Optional field or operation

<n:m>

.b

Register bit field

Byte mode selection

.d

Double-Word mode selection

.S

Shadow register select

.w

Word mode selection (default)

bit4

4-bit bit selection field (used in word addressed instructions) {0...15}

MCU Status bits: Carry, Digit Carry, Negative, Overflow, Sticky Zero

Absolute address, label or expression (resolved by the linker)

File register address {0000h...1FFFh}

1-bit unsigned literal {0,1}

C, DC, N, OV, Z

Expr

f

lit1

lit4

4-bit unsigned literal {0...15}

lit5

5-bit unsigned literal {0...31}

lit8

8-bit unsigned literal {0...255}

lit10

lit14

lit16

lit23

None

PC

10-bit unsigned literal {0...255} for Byte mode, {0:1023} for Word mode

14-bit unsigned literal {0...16383}

16-bit unsigned literal {0...65535}

23-bit unsigned literal {0...8388607}; LSB must be ‘0’

Field does not require an entry, may be blank

Program Counter

Slit10

Slit16

Slit6

Wb

10-bit signed literal {-512...511}

16-bit signed literal {-32768...32767}

6-bit signed literal {-16...16}

Base W register {W0..W15}

Wd

Destination W register { Wd, [Wd], [Wd++], [Wd--], [++Wd], [--Wd] }

Wdo

Destination W register 

{ Wnd, [Wnd], [Wnd++], [Wnd--], [++Wnd], [--Wnd], [Wnd+Wb] }

Wm,Wn

Wn

Dividend, Divisor working register pair (direct addressing)

One of 16 working registers {W0..W15}

Wnd

Wns

One of 16 destination working registers {W0..W15}

One of 16 source working registers {W0..W15}

WREG

Ws

W0 (working register used in file register instructions)

Source W register { Ws, [Ws], [Ws++], [Ws--], [++Ws], [--Ws] }

Source W register { Wns, [Wns], [Wns++], [Wns--], [++Wns], [--Wns], [Wns+Wb] }

Wso

DS39940D-page 298

 2010 Microchip Technology Inc.

PIC24FJ64GB004 FAMILY

TABLE 28-2: INSTRUCTION SET OVERVIEW

Assembly

Mnemonic

# of

Status Flags

Affected

Assembly Syntax

Description

Words Cycles

ADD

ADDC

AND

ASR

ADD

ADDC

AND

ASR

BCLR

BRA

BSET

BSW.C

BSW.Z

BTG

BTSC

f

f = f + WREG

1

C, DC, N, OV, Z

N, Z

f,WREG

WREG = f + WREG

#lit10,Wn

Wb,Ws,Wd

Wb,#lit5,Wd

f

Wd = lit10 + Wd

1

Wd = Wb + Ws

1

Wd = Wb + lit5

1

f = f + WREG + (C)

1

f,WREG

WREG = f + WREG + (C)

Wd = lit10 + Wd + (C)

Wd = Wb + Ws + (C)

Wd = Wb + lit5 + (C)

f = f .AND. WREG

1

#lit10,Wn

Wb,Ws,Wd

Wb,#lit5,Wd

f

1

f,WREG

WREG = f .AND. WREG

Wd = lit10 .AND. Wd

Wd = Wb .AND. Ws

1

N, Z

#lit10,Wn

Wb,Ws,Wd

Wb,#lit5,Wd

f

1

N, Z

1

N, Z

Wd = Wb .AND. lit5

1

N, Z

f = Arithmetic Right Shift f

WREG = Arithmetic Right Shift f

Wd = Arithmetic Right Shift Ws

Wnd = Arithmetic Right Shift Wb by Wns

Wnd = Arithmetic Right Shift Wb by lit5

Bit Clear f

1

C, N, OV, Z

N, Z

f,WREG

1

Ws,Wd

1

Wb,Wns,Wnd

Wb,#lit5,Wnd

f,#bit4

Ws,#bit4

C,Expr

1

N, Z

BCLR

BRA

1

None

Bit Clear Ws

1

None

Branch if Carry

1 (2)

2

None

GE,Expr

GEU,Expr

GT,Expr

GTU,Expr

LE,Expr

LEU,Expr

LT,Expr

LTU,Expr

N,Expr

Branch if Greater than or Equal

Branch if Unsigned Greater than or Equal

Branch if Greater than

Branch if Unsigned Greater than

Branch if Less than or Equal

Branch if Unsigned Less than or Equal

Branch if Less than

None

Branch if Unsigned Less than

Branch if Negative

None

NC,Expr

NN,Expr

NOV,Expr

NZ,Expr

OV,Expr

Expr

Branch if Not Carry

None

Branch if Not Negative

Branch if Not Overflow

Branch if Not Zero

None

Branch if Overflow

None

Branch Unconditionally

Branch if Zero

None

Z,Expr

1 (2)

2

None

Wn

Computed Branch

None

BSET

BSW

f,#bit4

Ws,#bit4

Ws,Wb

Bit Set f

1

None

Bit Set Ws

1

None

Write C bit to Ws<Wb>

Write Z bit to Ws<Wb>

Bit Toggle f

1

None

Ws,Wb

1

None

BTG

f,#bit4

Ws,#bit4

f,#bit4

1

None

Bit Toggle Ws

1

None

BTSC

Bit Test f, Skip if Clear

1

None

(2 or 3)

BTSC

Ws,#bit4

Bit Test Ws, Skip if Clear

1

None

(2 or 3)

 2010 Microchip Technology Inc.

DS39940D-page 299

PIC24FJ64GB004 FAMILY

TABLE 28-2: INSTRUCTION SET OVERVIEW (CONTINUED)

Assembly

Mnemonic

# of

Status Flags

Affected

Assembly Syntax

f,#bit4

Description

Bit Test f, Skip if Set

Words Cycles

BTSS

1

None

(2 or 3)

Ws,#bit4

Bit Test Ws, Skip if Set

1

None

(2 or 3)

BTST

f,#bit4

Ws,#bit4

Ws,Wb

Bit Test f

1

2

1

2

1

Z

BTST.C

BTST.Z

BTST.C

BTST.Z

BTSTS

Bit Test Ws to C

C

Bit Test Ws to Z

Z

Bit Test Ws<Wb> to C

Bit Test Ws<Wb> to Z

Bit Test then Set f

Bit Test Ws to C, then Set

Bit Test Ws to Z, then Set

Call Subroutine

C

Ws,Wb

Z

BTSTS

f,#bit4

Z

BTSTS.C Ws,#bit4

BTSTS.Z Ws,#bit4

C

Z

CALL

CLR

CALL

CLR

lit23

Wn

None

Call Indirect Subroutine

f = 0x0000

None

f

None

CLR

WREG

Ws

WREG = 0x0000

Ws = 0x0000

None

CLR

None

CLRWDT

COM

CLRWDT

Clear Watchdog Timer

WDTO, Sleep

COM

CP

f

f = f

1

N, Z

f,WREG

Ws,Wd

f

WREG = f

N, Z

Wd = Ws

N, Z

CP

Compare f with WREG

Compare Wb with lit5

Compare Wb with Ws (Wb – Ws)

Compare f with 0x0000

Compare Ws with 0x0000

Compare f with WREG, with Borrow

Compare Wb with lit5, with Borrow

C, DC, N, OV, Z

CP

Wb,#lit5

Wb,Ws

f

CP

CP0

CPB

CP0

CPB

Ws

f

Wb,#lit5

Wb,Ws

Compare Wb with Ws, with Borrow

(Wb – Ws – C)

CPSEQ

CPSGT

CPSLT

CPSNE

CPSEQ

CPSGT

CPSLT

CPSNE

Wb,Wn

Compare Wb with Wn, Skip if =

Compare Wb with Wn, Skip if >

Compare Wb with Wn, Skip if <

Compare Wb with Wn, Skip if 

1

None

(2 or 3)

1

(2 or 3)

1

(2 or 3)

1

(2 or 3)

DAW

DEC

DAW.B

DEC

Wn

Wn = Decimal Adjust Wn

f = f – 1

1

C

f

C, DC, N, OV, Z

None

DEC

f,WREG

Ws,Wd

f

WREG = f – 1

1

DEC

Wd = Ws – 1

1

DEC2

f = f – 2

1

DEC2

f,WREG

Ws,Wd

#lit14

Wm,Wn

Wns,Wnd

Ws,Wnd

WREG = f – 2

1

DEC2

Wd = Ws – 2

1

DISI

DIV

DISI

Disable Interrupts for k Instruction Cycles

Signed 16/16-bit Integer Divide

Signed 32/16-bit Integer Divide

Unsigned 16/16-bit Integer Divide

Unsigned 32/16-bit Integer Divide

Swap Wns with Wnd

1

DIV.SW

DIV.SD

DIV.UW

DIV.UD

EXCH

18

1

N, Z, C, OV

None

EXCH

FF1L

FF1R

FF1L

Find First One from Left (MSb) Side

Find First One from Right (LSb) Side

1

C

FF1R

1

C

DS39940D-page 300

 2010 Microchip Technology Inc.

PIC24FJ64GB004 FAMILY

TABLE 28-2: INSTRUCTION SET OVERVIEW (CONTINUED)

Assembly

Mnemonic

# of

Status Flags

Affected

Assembly Syntax

Description

Words Cycles

GOTO

INC

Expr

Go to Address

Go to Indirect

f = f + 1

2

1

2

1

2

1

None

Wn

None

INC

f

C, DC, N, OV, Z

N, Z

INC

f,WREG

WREG = f + 1

Wd = Ws + 1

f = f + 2

INC

Ws,Wd

INC2

IOR

INC2

IOR

f

f,WREG

WREG = f + 2

Wd = Ws + 2

f = f .IOR. WREG

Ws,Wd

f

IOR

f,WREG

WREG = f .IOR. WREG

N, Z

IOR

#lit10,Wn

Wb,Ws,Wd

Wb,#lit5,Wd

#lit14

Wd = lit10 .IOR. Wd

N, Z

IOR

Wd = Wb .IOR. Ws

N, Z

IOR

Wd = Wb .IOR. lit5

N, Z

LNK

LSR

LNK

Link Frame Pointer

None

LSR

f

f = Logical Right Shift f

C, N, OV, Z

N, Z

LSR

f,WREG

WREG = Logical Right Shift f

Wd = Logical Right Shift Ws

Wnd = Logical Right Shift Wb by Wns

Wnd = Logical Right Shift Wb by lit5

Move f to Wn

LSR

Ws,Wd

LSR

Wb,Wns,Wnd

Wb,#lit5,Wnd

f,Wn

LSR

N, Z

MOV

None

MOV

[Wns+Slit10],Wnd

f

Move [Wns + Slit10] to Wnd

Move f to f

None

MOV

N, Z

MOV

f,WREG

Move f to WREG

N, Z

MOV

#lit16,Wn

#lit8,Wn

Wn,f

Move 16-bit Literal to Wn

None

MOV.b

MOV

Move 8-bit Literal to Wn

None

Move Wn to f

None

MOV

Wns,[Wns+Slit10]

Wso,Wdo

WREG,f

Move Wns to [Wns + Slit10]

Move Ws to Wd

MOV

None

MOV

Move WREG to f

N, Z

MOV.D

MUL.SS

MUL.SU

MUL.US

MUL.UU

MUL.SU

MUL.UU

MUL

Wns,Wd

Move Double from W(ns):W(ns + 1) to Wd

Move Double from Ws to W(nd + 1):W(nd)

{Wnd + 1, Wnd} = Signed(Wb) * Signed(Ws)

{Wnd + 1, Wnd} = Signed(Wb) * Unsigned(Ws)

{Wnd + 1, Wnd} = Unsigned(Wb) * Signed(Ws)

{Wnd + 1, Wnd} = Unsigned(Wb) * Unsigned(Ws)

{Wnd + 1, Wnd} = Signed(Wb) * Unsigned(lit5)

{Wnd + 1, Wnd} = Unsigned(Wb) * Unsigned(lit5)

W3:W2 = f * WREG

None

Ws,Wnd

None

MUL

Wb,Ws,Wnd

Wb,#lit5,Wnd

f

None

NEG

f

f = f + 1

C, DC, N, OV, Z

NEG

f,WREG

Ws,Wd

WREG = f + 1

1

2

1

2

1

C, DC, N, OV, Z

None

NEG

Wd = Ws + 1

NOP

POP

NOP

No Operation

NOPR

POP

No Operation

None

f

Pop f from Top-of-Stack (TOS)

Pop from Top-of-Stack (TOS) to Wdo

Pop from Top-of-Stack (TOS) to W(nd):W(nd + 1)

Pop Shadow Registers

None

POP

Wdo

Wnd

None

POP.D

POP.S

PUSH

PUSH.D

PUSH.S

None

All

PUSH

f

Push f to Top-of-Stack (TOS)

Push Wso to Top-of-Stack (TOS)

Push W(ns):W(ns + 1) to Top-of-Stack (TOS)

Push Shadow Registers

None

Wso

Wns

None

 2010 Microchip Technology Inc.

DS39940D-page 301

PIC24FJ64GB004 FAMILY

TABLE 28-2: INSTRUCTION SET OVERVIEW (CONTINUED)

Assembly

Mnemonic

# of

Status Flags

Affected

Assembly Syntax

Description

Words Cycles

PWRSAV

RCALL

PWRSAV

RCALL

REPEAT

RESET

RETFIE

RETLW

RETURN

RLC

#lit1

Expr

Wn

Go into Sleep or Idle mode

Relative Call

1

2

WDTO, Sleep

None

Computed Call

2

None

REPEAT

#lit14

Wn

Repeat Next Instruction lit14 + 1 times

Repeat Next Instruction (Wn) + 1 times

Software Device Reset

Return from Interrupt

1

None

1

None

RESET

RETFIE

RETLW

RETURN

RLC

1

None

3 (2)

1

None

#lit10,Wn

Return with Literal in Wn

Return from Subroutine

f = Rotate Left through Carry f

WREG = Rotate Left through Carry f

Wd = Rotate Left through Carry Ws

f = Rotate Left (No Carry) f

WREG = Rotate Left (No Carry) f

Wd = Rotate Left (No Carry) Ws

f = Rotate Right through Carry f

WREG = Rotate Right through Carry f

Wd = Rotate Right through Carry Ws

f = Rotate Right (No Carry) f

WREG = Rotate Right (No Carry) f

Wd = Rotate Right (No Carry) Ws

Wnd = Sign-Extended Ws

f = FFFFh

None

f

C, N, Z

RLC

f,WREG

Ws,Wd

f

1

C, N, Z

RLC

1

C, N, Z

RLNC

RRC

RLNC

RRC

1

N, Z

f,WREG

Ws,Wd

f

1

N, Z

1

N, Z

1

C, N, Z

RRC

f,WREG

Ws,Wd

f

1

C, N, Z

RRC

1

C, N, Z

RRNC

SE

1

N, Z

f,WREG

Ws,Wd

Ws,Wnd

f

1

N, Z

1

N, Z

SE

1

C, N, Z

SETM

SL

1

None

WREG

WREG = FFFFh

1

None

Ws

Ws = FFFFh

1

None

SL

f

f = Left Shift f

1

C, N, OV, Z

N, Z

SL

f,WREG

Ws,Wd

Wb,Wns,Wnd

Wb,#lit5,Wnd

f

WREG = Left Shift f

1

SL

Wd = Left Shift Ws

1

SL

Wnd = Left Shift Wb by Wns

Wnd = Left Shift Wb by lit5

f = f – WREG

1

SL

1

N, Z

SUB

1

C, DC, N, OV, Z

SUB

f,WREG

#lit10,Wn

Wb,Ws,Wd

Wb,#lit5,Wd

f

WREG = f – WREG

1

SUB

Wn = Wn – lit10

1

SUB

Wd = Wb – Ws

1

SUB

Wd = Wb – lit5

1

SUBB

f = f – WREG – (C)

1

SUBB

f,WREG

WREG = f – WREG – (C)

Wn = Wn – lit10 – (C)

Wd = Wb – Ws – (C)

1

C, DC, N, OV, Z

#lit10,Wn

Wb,Ws,Wd

SUBB

SUBR

Wb,#lit5,Wd

f

Wd = Wb – lit5 – (C)

f = WREG – f

1

C, DC, N, OV, Z

SUBR

f,WREG

WREG = WREG – f

Wd = Ws – Wb

Wb,Ws,Wd

Wb,#lit5,Wd

Wd = lit5 – Wb

SUBBR

f

f = WREG – f – (C)

1

C, DC, N, OV, Z

SUBBR

SWAP.b

SWAP

f,WREG

Wb,Ws,Wd

Wb,#lit5,Wd

Wn

WREG = WREG – f – (C)

Wd = Ws – Wb – (C)

Wd = lit5 – Wb – (C)

Wn = Nibble Swap Wn

Wn = Byte Swap Wn

1

C, DC, N, OV, Z

None

SWAP

Wn

None

DS39940D-page 302

 2010 Microchip Technology Inc.

PIC24FJ64GB004 FAMILY

TABLE 28-2: INSTRUCTION SET OVERVIEW (CONTINUED)

Assembly

Mnemonic

# of

Status Flags

Affected

Assembly Syntax

Description

Words Cycles

TBLRDH

TBLRDL

TBLWTH

TBLWTL

ULNK

TBLRDH

TBLRDL

TBLWTH

TBLWTL

ULNK

XOR

Ws,Wd

Read Prog<23:16> to Wd<7:0>

Read Prog<15:0> to Wd

Write Ws<7:0> to Prog<23:16>

Write Ws to Prog<15:0>

Unlink Frame Pointer

1

2

1

None

N, Z

XOR

f

f = f .XOR. WREG

XOR

f,WREG

WREG = f .XOR. WREG

Wd = lit10 .XOR. Wd

N, Z

XOR

#lit10,Wn

Wb,Ws,Wd

Wb,#lit5,Wd

Ws,Wnd

N, Z

XOR

Wd = Wb .XOR. Ws

N, Z

XOR

Wd = Wb .XOR. lit5

N, Z

ZE

Wnd = Zero-Extend Ws

C, Z, N

 2010 Microchip Technology Inc.

DS39940D-page 303

PIC24FJ64GB004 FAMILY

NOTES:

DS39940D-page 304

 2010 Microchip Technology Inc.

PIC24FJ64GB004 FAMILY

29.0 ELECTRICAL CHARACTERISTICS

This section provides an overview of the PIC24FJ64GB004 family electrical characteristics. Additional information will

be provided in future revisions of this document as it becomes available.

Absolute maximum ratings for the PIC24FJ64GB004 family are listed below. Exposure to these maximum rating

conditions for extended periods may affect device reliability. Functional operation of the device at these, or any other

conditions above the parameters indicated in the operation listings of this specification, is not implied.

(†)

Absolute Maximum Ratings

Ambient temperature under bias.............................................................................................................-40°C to +135°C

Storage temperature .............................................................................................................................. -65°C to +150°C

Voltage on VDD with respect to VSS ......................................................................................................... -0.3V to +4.0V

Voltage on any combined analog and digital pin, and MCLR, with respect to VSS ........................ -0.3V to (VDD + 0.3V)

Voltage on any digital only pin with respect to VSS .................................................................................. -0.3V to +6.0V

Voltage on VDDCORE with respect to VSS ................................................................................................. -0.3V to +3.0V

Maximum current out of VSS pin ...........................................................................................................................300 mA

Maximum current into VDD pin (Note 1)................................................................................................................250 mA

Maximum output current sunk by any I/O pin..........................................................................................................25 mA

Maximum output current sourced by any I/O pin ....................................................................................................25 mA

Maximum current sunk by all ports .......................................................................................................................200 mA

Maximum current sourced by all ports (Note 1)....................................................................................................200 mA

Note 1: Maximum allowable current is a function of device maximum power dissipation (see Table 29-1).

NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the

device. This is a stress rating only and functional operation of the device at those or any other conditions above those

indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for

extended periods may affect device reliability.

 2010 Microchip Technology Inc.

DS39940D-page 305

PIC24FJ64GB004 FAMILY

29.1 DC Characteristics

FIGURE 29-1:

PIC24FJ64GB004 FAMILY VOLTAGE-FREQUENCY GRAPH (INDUSTRIAL)

3.00V

2.75V

2.50V

2.75V

2.35V

PIC24FJ64GB004 Family

2.35V

2.00V

32 MHz

16 MHz

Frequency

For frequencies between 16 MHz and 32 MHz, FMAX = (45.7 MHz/V) * (VDDCORE – 2V) + 16 MHz.

Note 1: When the voltage regulator is disabled, VDD and VDDCORE must be maintained so that

VDDCOREVDD3.6V.

FIGURE 29-2:

PIC24FJ64GB004 FAMILY VOLTAGE-FREQUENCY GRAPH

(EXTENDED TEMPERATURE)

3.00V

2.75V

2.50V

2.75V

2.35V

PIC24FJ64GB004 Family

2.25V

2.00V

16 MHz

24 MHz

Frequency

For frequencies between 16 MHz and 24 MHz, FMAX = (22.9 MHz/V) * (VDDCORE – 2V) + 16 MHz.

Note 1: WHEN the voltage regulator is disabled, VDD and VDDCORE must be maintained so that

VDDCOREVDD3.6V.

DS39940D-page 306

 2010 Microchip Technology Inc.

PIC24FJ64GB004 FAMILY

TABLE 29-1: THERMAL OPERATING CONDITIONS

Rating

Symbol

Min

Typ

Max

Unit

PIC24FJ64GB004 Family:

Operating Junction Temperature Range

Operating Ambient Temperature Range

TJ

TA

-40

—

+140

+125

°C

Power Dissipation:

Internal Chip Power Dissipation:

PINT = VDD x (IDD –  IOH)

PD

PINT + PI/O

W

I/O Pin Power Dissipation:

PI/O =  ({VDD – VOH} x IOH) +  (VOL x IOL)

Maximum Allowed Power Dissipation

PDMAX

(TJ – TA)/JA

TABLE 29-2: THERMAL PACKAGING CHARACTERISTICS

Characteristic

Symbol

Typ

Max

Unit

Notes

Package Thermal Resistance, 300 mil SOIC

Package Thermal Resistance, 6x6x0.9 mm QFN

Package Thermal Resistance, 8x8x1 mm QFN

Package Thermal Resistance, 10x10x1 mm TQFP

^JA

JA

49

33.7

28

—

°C/W (Note 1)

39.3

Note 1: Junction to ambient thermal resistance; Theta-JA (JA) numbers are achieved by package simulations.

 2010 Microchip Technology Inc.

DS39940D-page 307

PIC24FJ64GB004 FAMILY

TABLE 29-3: DC CHARACTERISTICS: TEMPERATURE AND VOLTAGE SPECIFICATIONS

Standard Operating Conditions: 2.0V to 3.6V (unless otherwise stated)

DC CHARACTERISTICS

Operating temperature

-40°C  TA  +85°C for Industrial

-40°C  TA  +125°C for Extended

Param

No.

Symbol

Characteristic

Min

Typ⁽¹⁾

Max

Units

Conditions

Operating Voltage

DC10 Supply Voltage

VDD

2.2

VDDCORE

2.0

—

3.6

2.75

—

V

Regulator enabled

Regulator disabled

VDD

VDDCORE

DC12 VDR

RAM Data Retention

1.5

Voltage⁽²⁾

DC16 VPOR

VDD Start Voltage

to Ensure Internal

Power-on Reset Signal

VSS

0.05

—

V

DC17 SVDD

DC18 VBOR

VDD Rise Rate

to Ensure Internal

Power-on Reset Signal

V/ms 0-3.3V in 0.1s

0-2.5V in 60 ms

Brown-out Reset

Voltage

2.05

V

Note 1: Data in “Typ” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only

and are not tested.

2: This is the limit to which VDD can be lowered without losing RAM data.

DS39940D-page 308

 2010 Microchip Technology Inc.

PIC24FJ64GB004 FAMILY

TABLE 29-4: DC CHARACTERISTICS: OPERATING CURRENT (IDD)

Standard Operating Conditions: 2.0V to 3.6V (unless otherwise

stated)

Operating temperature -40°C  TA  +85°C for Industrial

-40°C  TA  +125°C for Extended

DC CHARACTERISTICS

Parameter

Typical⁽¹⁾

No.

Max

Units

Conditions

Operating Current (IDD)⁽²⁾

DC21

0.24

0.25

0.3

0.395

0.78

0.75

1.4

mA

-40°C

+25°C

+85°C

+125C

-40°C

+25°C

+85°C

+125C

-40°C

+25°C

+85°C

+125C

-40°C

+25°C

+85°C

+125C

-40°C

+25°C

+85°C

+125C

-40°C

+25°C

+85°C

+125C

DC21a

DC21b

DC21f

DC21c

DC21d

DC21e

DC21g

DC20

2.0V⁽³⁾

3.3V⁽⁴⁾

2.0V⁽³⁾

3.3V⁽⁴⁾

2.0V⁽³⁾

3.3V⁽⁴⁾

0.5 MIPS

1 MIPS

4 MIPS

0.44

0.41

0.6

0.5

DC20a

DC20b

DC20c

DC20d

DC20e

DC20f

DC20g

DC23

0.5

0.6

0.75

1.0

1.4

2.0

3.0

DC23a

DC23b

DC23c

DC23d

DC23e

DC23f

DC23g

2.0

3.0

2.0

3.0

2.4

3.0

2.9

4.2

2.9

4.2

2.9

4.2

3.5

4.2

Note 1: Data in “Typical” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance

only and are not tested.

2: The supply current is mainly a function of the operating voltage and frequency. Other factors, such as I/O pin

loading and switching rate, oscillator type, internal code execution pattern and temperature, also have an

impact on the current consumption. The test conditions for all IDD measurements are as follows: OSCI driven

with external square wave from rail to rail. All I/O pins are configured as inputs and pulled to VDD.

MCLR = VDD; WDT and FSCM are disabled. CPU, SRAM, program memory and data memory are

operational. No peripheral modules are operating and all of the Peripheral Module Disable (PMD) bits are set.

3: On-chip voltage regulator disabled (DISVREG tied to VDD).

4: On-chip voltage regulator enabled (DISVREG tied to VSS). Low-Voltage Detect (LVD) and Brown-out

Detect (BOD) are enabled.

 2010 Microchip Technology Inc.

DS39940D-page 309

PIC24FJ64GB004 FAMILY

TABLE 29-4: DC CHARACTERISTICS: OPERATING CURRENT (IDD) (CONTINUED)

Standard Operating Conditions: 2.0V to 3.6V (unless otherwise

stated)

DC CHARACTERISTICS

Operating temperature -40°C  TA  +85°C for Industrial

-40°C  TA  +125°C for Extended

Parameter

Typical⁽¹⁾

Max

Units

Conditions

No.

Operating Current (IDD)⁽²⁾

DC24

10.5

11.3

15.0

20.0

42.0

57.0

95.0

114.0

15.5

18.0

19.0

36.0

55.0

120.0

125.0

160.0

180.0

mA

A

-40°C

+25°C

+85°C

+125C

-40°C

+25°C

+85°C

+125C

-40°C

+25°C

+85°C

+125C

-40°C

+25°C

+85°C

+125C

DC24a

DC24b

DC24c

DC24d

DC24e

DC24f

DC24g

DC31

2.5V⁽³⁾

3.3V⁽⁴⁾

2.0V⁽³⁾

3.3V⁽⁴⁾

16 MIPS

DC31a

DC31b

DC31c

DC31d

DC31e

DC31f

DC31g

A

LPRC (31 kHz)