PIC24HJ32GP302-E/SO [MICROCHIP]
High-Performance, 16-bit Microcontrollers; 高性能16位微控制器
| 型号： | PIC24HJ32GP302-E/SO |
| 厂家： | 
MICROCHIP |
| 描述： | High-Performance, 16-bit Microcontrollers |
| 文件： | 总244页 (文件大小：3578K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PIC24HJ32GP202/204 and
PIC24HJ16GP304
Data Sheet
High-Performance,
16-bit Microcontrollers
© 2007 Microchip Technology Inc.
Preliminary
DS70289A
Note the following details of the code protection feature on Microchip devices:
•
Microchip products meet the specification contained in their particular Microchip Data Sheet.
•
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
•
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
•
•
Microchip is willing to work with the customer who is concerned about the integrity of their code.
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION,
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
QUALITY, PERFORMANCE, MERCHANTABILITY OR
FITNESS FOR PURPOSE. Microchip disclaims all liability
arising from this information and its use. Use of Microchip
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hold harmless Microchip from any and all damages, claims,
suits, or expenses resulting from such use. No licenses are
conveyed, implicitly or otherwise, under any Microchip
intellectual property rights.
Trademarks
The Microchip name and logo, the Microchip logo, Accuron,
dsPIC, KEELOQ, KEELOQ logo, microID, MPLAB, PIC,
PICmicro, PICSTART, PRO MATE, rfPIC and SmartShunt
are registered trademarks of Microchip Technology
Incorporated in the U.S.A. and other countries.
AmpLab, FilterLab, Linear Active Thermistor, Migratable
Memory, MXDEV, MXLAB, SEEVAL, SmartSensor and The
Embedded Control Solutions Company are registered
trademarks of Microchip Technology Incorporated in the
U.S.A.
Analog-for-the-Digital Age, Application Maestro, CodeGuard,
dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN,
ECONOMONITOR, FanSense, FlexROM, fuzzyLAB,
In-Circuit Serial Programming, ICSP, ICEPIC, Mindi, MiWi,
MPASM, MPLAB Certified logo, MPLIB, MPLINK, PICkit,
PICDEM, PICDEM.net, PICLAB, PICtail, PowerCal,
PowerInfo, PowerMate, PowerTool, REAL ICE, rfLAB, Select
Mode, Smart Serial, SmartTel, Total Endurance, UNI/O,
WiperLock and ZENA are trademarks of Microchip
Technology Incorporated in the U.S.A. and other countries.
SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.
All other trademarks mentioned herein are property of their
respective companies.
© 2007, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.
Printed on recycled paper.
Microchip received ISO/TS-16949:2002 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
DS70289A-page ii
Preliminary
© 2007 Microchip Technology Inc.
PIC24HJ32GP202/204 AND
PIC24HJ16GP304
High-Performance, 16-bit Microcontrollers
Operating Range:
Digital I/O:
• Up to 40 MIPS operation (@ 3.0-3.6V):
• Peripheral Pin Select Functionality
• Up to 35 programmable digital I/O pins
• Wake-up/Interrupt-on-Change for up to 21 pins
• Output pins can drive from 3.0V to 3.6V
• Up to 5V output with open drain configuration
• All digital input pins are 5V tolerant
• 4 mA sink on all I/O pins
- Industrial temperature range (-40°C to
+85°C)
- Extended temperature range (-40°C to
+125°C)
High-Performance CPU:
• Modified Harvard architecture
• C compiler optimized instruction set
• 16-bit wide data path
System Management:
• Flexible clock options:
• 24-bit wide instructions
- External, crystal, resonator, internal RC
- Fully integrated Phase-Locked Loop (PLL)
- Extremely low jitter PLL
• Linear program memory addressing up to 4M
instruction words
• Linear data memory addressing up to 64 Kbytes
• 71 base instructions, mostly 1 word/1 cycle
• Sixteen 16-bit General Purpose Registers
• Flexible and powerful addressing modes
• Software stack
• Power-up Timer
• Oscillator Start-up Timer/Stabilizer
• Watchdog Timer with its own RC oscillator
• Fail-Safe Clock Monitor
• Reset by multiple sources
• 16 x 16 multiply operations
• 32/16 and 16/16 divide operations
• Up to ±16-bit shifts for up to 40-bit data
Power Management:
• On-chip 2.5V voltage regulator
• Switch between clock sources in real time
• Idle, Sleep and Doze modes with fast wake-up
Interrupt Controller:
• 5-cycle latency
Timers/Capture/Compare:
• 118 interrupt vectors
• Up to 21 available interrupt sources
• Up to 3 external interrupts
• 7 programmable priority levels
• 4 processor exceptions
• Timer/Counters, up to three 16-bit timers:
- Can pair up to make one 32-bit timer
- 1 timer runs as Real-Time Clock with external
32.768 kHz oscillator
- Programmable prescaler
On-Chip Flash and SRAM:
• Input Capture (up to 4 channels):
- Capture on up, down or both edges
- 16-bit capture input functions
- 4-deep FIFO on each capture
• Output Compare (up to 2 channels):
- Single or Dual 16-Bit Compare mode
- 16-bit Glitchless PWM Mode
• Flash program memory (up to 32 Kbytes)
• Data SRAM (2 Kbytes)
• Boot and General Security for Program Flash
© 2007 Microchip Technology Inc.
Preliminary
DS70289A-page 1
PIC24HJ32GP202/204 and PIC24HJ16GP304
Communication Modules:
Analog-to-Digital Converters (ADCs):
• 4-wire SPI
• 10-bit, 1.1 Msps or 12-bit, 500 Ksps conversion:
- 2 and 4 simultaneous samples (10-bit ADC)
- Up to 13 input channels with auto-scanning
- Framing supports I/O interface to simple
codecs
- Supports 8-bit and 16-bit data
- Conversion start can be manual or
synchronized with 1 of 4 trigger sources
- Supports all serial clock formats and
sampling modes
• I2C™
- Conversion possible in Sleep mode
- ±2 LSb max integral nonlinearity
- ±1 LSb max differential nonlinearity
- Full Multi-Master Slave mode support
- 7-bit and 10-bit addressing
- Bus collision detection and arbitration
- Integrated signal conditioning
- Slave address masking
CMOS Flash Technology:
• Low-power, high-speed Flash technology
• Fully static design
• UART
• 3.3V (±10%) operating voltage
• Industrial and extended temperature
• Low-power consumption
- Interrupt on address bit detect
- Interrupt on UART error
- Wake-up on Start bit from Sleep mode
- 4-character TX and RX FIFO buffers
- LIN bus support
Packaging:
• 28-pin SDIP/SOIC/QFN-S
• 44-pin QFN/TQFP
- IrDA® encoding and decoding in hardware
- High-Speed Baud mode
- Hardware Flow Control with CTS and RTS
Note:
See the device variant tables for exact
peripheral features per device.
DS70289A-page 2
Preliminary
© 2007 Microchip Technology Inc.
PIC24HJ32GP202/204 and PIC24HJ16GP304
PIC24HJ32GP202/204 and
PIC24HJ16GP304 Product Families
The device names, pin counts, memory sizes and
peripheral availability of each family are listed below,
followed by their pinout diagrams.
TABLE 1:
PIC24HJ32GP202/204 AND PIC24HJ16GP304 CONTROLLER FAMILIES
Remappable Peripherals
Device
(1)
PIC24HJ32GP202
28
32
2
16
3
4
2
1
1
1 ADC, 10 ch
1
21
SDIP
SOIC
QFN-S
(1)
(1)
26
26
PIC24HJ32GP204
PIC24HJ16GP304
44
44
32
16
2
2
3
3
4
4
2
2
1
1
1
1
1 ADC, 13 ch
1 ADC, 13 ch
1
1
35
35
QFN
TQFP
QFN
TQFP
Note 1: Only 2 out of 3 timers are Remappable
© 2007 Microchip Technology Inc.
Preliminary
DS70289A-page 3
PIC24HJ32GP202/204 and PIC24HJ16GP304
Pin Diagrams
28-Pin SDIP, SOIC
MCLR
AN0/VREF+/CN2/RA0
AN1/VREF-/CN3/RA1
PGED1/AN2/C2IN-/RP0/CN4/RB0
PGEC1/AN3/C2IN+/RP1/CN5/RB1
AN4/RP2/CN6/RB2
1
2
3
4
5
28
27
26
25
24
AVDD
AVSS
AN9/RP15/CN11/RB15
AN10/RP14/CN12/RB14
AN11/RP13/CN13/RB13
AN12/RP12/CN14/RB12
PGEC2/TMS/RP11/CN15/RB11
PGED2/TDI/RP10/CN16 / RB10
VCAP/VDDCORE
6
7
8
23
22
21
AN5/RP3/CN7/RB3
VSS
OSCI/CLKI/CN30/RA2
OSCO/CLKO/CN29/RA3
SOSCI/RP4/CN1/RB4
SOSCO/T1CK/CN0/RA4
VDD
9
20
19
18
17
16
15
VSS
10
11
12
13
14
TDO/SDA1/RP9/CN21/RB9
TCK/SCL1/RP8/CN22/RB8
INT0/RP7/CN23/RB7
PGEC3/ASCL1/RP6/CN24/RB6
PGED3/ASDA1/RP5/CN27/RB5
28-Pin QFN-S
28 27 26 25 24 2322
PGED1/AN2/C2IN-/RP0/CN4/RB0
PGEC1/AN3/C2IN+/RP1/CN5/RB1
AN4/RP2/CN6/RB2
AN11/RP13/CN13/RB13
21
AN12/RP12/CN14/RB12
20
PGEC2/TMS/RP11/CN15/RB11
19
PGED2/TDI/RP10/CN16/RB10
18
1
2
3
4
5
6
7
PIC24HJ32GP202
AN5/RP3/CN7/RB3
VSS
VCAP/VDDCORE
17
OSCI/CLKI/CN30/RA2
Vss
16
15
OSCO/CLKO/CN29/RA3
TDO/SDA1/RP9/CN21/RB9
8
9 10 11 12 13 14
DS70289A-page 4
Preliminary
© 2007 Microchip Technology Inc.
PIC24HJ32GP202/204 and PIC24HJ16GP304
Pin Diagrams (Continued)
44-Pin TQFP
11
10
AN4/RP2/CN6/RB2
AN5/RP3/CN7/RB3
AN6/RP16/CN8/RC0
AN7/RP17/CN9/RC1
AN8/RP18/CN10/RC2
VDD
AN11/RP13/CN13/RB13
AN12/RP12/CN14/RB12
PGEC2/RP11/CN15/RB11
PGED2/RP10/CN16/RB10
VCAP/VDDCORE
23
24
25
9
8
7
6
5
4
3
2
1
26
27
PIC24HJ32GP204
PIC24HJ16GP304
VSS
28
29
RP25/CN19/RC9
VSS
RP24/CN20/RC8
30
31
32
33
OSCI/CLKI/CN30/RA2
RP23/CN17/RC7
OSCO/CLKO/CN29/RA3
TDO/RA8
RP22/CN18/RC6
SDA1/RP9/CN21/RB9
SOSCI/RP4/CN1/RB4
© 2007 Microchip Technology Inc.
Preliminary
DS70289A-page 5
PIC24HJ32GP202/204 and PIC24HJ16GP304
Pin Diagrams (Continued)
44-Pin TQFP
11
10
AN4/RP2/CN6/RB2
AN5/RP3/CN7/RB3
AN6/RP16/CN8/RC0
AN7/RP17/CN9/RC1
AN8/RP18/CN10/RC2
VDD
AN11/RP13/CN13/RB13
AN12/RP12/CN14/RB12
PGEC2/RP11/CN15/RB11
PGED2/RP10/CN16/RB10
VCAP/VDDCORE
23
24
25
9
8
7
6
5
4
3
2
1
26
27
PIC24HJ32GP204
PIC24HJ16GP304
VSS
28
29
30
31
32
33
RP25/CN19/RC9
VSS
RP24/CN20/RC8
OSCI/CLKI/CN30/RA2
OSCO/CLKO/CN29/RA3
TDO/RA8
RP23/CN17/RC7
RP22/CN18/RC6
SDA1/RP9/CN21/RB9
SOSCI/RP4/CN1/RB4
DS70289A-page 6
Preliminary
© 2007 Microchip Technology Inc.
PIC24HJ32GP202/204 and PIC24HJ16GP304
Table of Contents
1.0 Device Overview .......................................................................................................................................................................... 9
2.0 CPU............................................................................................................................................................................................ 13
3.0 Memory Organization................................................................................................................................................................. 19
4.0 Flash Program Memory.............................................................................................................................................................. 41
5.0 Resets ....................................................................................................................................................................................... 47
6.0 Interrupt Controller ..................................................................................................................................................................... 53
7.0 Oscillator Configuration.............................................................................................................................................................. 81
8.0 Power-Saving Features.............................................................................................................................................................. 91
9.0 I/O Ports ..................................................................................................................................................................................... 93
10.0 Timer1 ...................................................................................................................................................................................... 117
11.0 Timer2/3 Feature...................................................................................................................................................................... 119
12.0 Input Capture............................................................................................................................................................................ 125
13.0 Output Compare....................................................................................................................................................................... 127
14.0 Serial Peripheral Interface (SPI)............................................................................................................................................... 133
2
15.0 Inter-Integrated Circuit (I C)..................................................................................................................................................... 141
16.0 Universal Asynchronous Receiver Transmitter (UART)........................................................................................................... 151
17.0 10-bit/12-bit Analog-to-Digital Converter (ADC)....................................................................................................................... 159
18.0 Special Features ...................................................................................................................................................................... 173
19.0 Instruction Set Summary.......................................................................................................................................................... 181
20.0 Development Support............................................................................................................................................................... 189
21.0 Electrical Characteristics.......................................................................................................................................................... 193
22.0 Packaging Information.............................................................................................................................................................. 227
Appendix A: Revision History............................................................................................................................................................. 233
Index ................................................................................................................................................................................................. 235
The Microchip Web Site..................................................................................................................................................................... 239
Customer Change Notification Service .............................................................................................................................................. 239
Customer Support.............................................................................................................................................................................. 239
Reader Response.............................................................................................................................................................................. 240
Product Identification System ............................................................................................................................................................ 241
TO OUR VALUED CUSTOMERS
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To determine if an errata sheet exists for a particular device, please check with one of the following:
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•
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© 2007 Microchip Technology Inc.
Preliminary
DS70289A-page 7
PIC24HJ32GP202/204 and PIC24HJ16GP304
NOTES:
DS70289A-page 8
Preliminary
© 2007 Microchip Technology Inc.
PIC24HJ32GP202/204 and PIC24HJ16GP304
1.0
DEVICE OVERVIEW
Note:
This data sheet summarizes the features
of the PIC24HJ32GP202/204 and
PIC24HJ16GP304 devices. It is not
intended to be a comprehensive reference
source. To complement the information in
this data sheet, refer to the “PIC24H
Family Reference Manual”.
This document contains device-specific information for
the following devices:
• PIC24HJ32GP202
• PIC24HJ32GP204
• PIC24HJ16GP304
Figure 1-1 shows a general block diagram of the core
and peripheral modules in the PIC24HJ32GP202/204
and PIC24HJ16GP304 family of devices. Table 1-1
lists the functions of the various pins shown in the
pinout diagrams.
© 2007 Microchip Technology Inc.
Preliminary
DS70289A-page 9
PIC24HJ32GP202/204 and PIC24HJ16GP304
FIGURE 1-1:
PIC24HJ32GP202/204 AND PIC24HJ16GP304 BLOCK DIAGRAM
PSV & Table
Data Access
Control Block
Data Bus
Interrupt
Controller
PORTA
PORTB
16
16
16
8
Data Latch
X RAM
23
PCH PCL
Program Counter
PCU
23
Address
Latch
Loop
Control
Logic
Stack
Control
Logic
16
23
16
Remappable
Pins
Address Generator Units
Address Latch
Program Memory
Data Latch
EA MUX
Address Bus
ROM Latch
24
16
16
Instruction
Decode &
Control
Instruction Reg
16
Control Signals
to Various Blocks
17 x 17 Multiplier
Divide Support
16 x 16
Power-up
Timer
Timing
Generation
W Register Array
OSC2/CLKO
OSC1/CLKI
16
Oscillator
Start-up Timer
FRC/LPRC
Oscillators
Power-on
Reset
16-bit ALU
Precision
Band Gap
Reference
Watchdog
Timer
16
Brown-out
Reset
Voltage
Regulator
VDDCORE/VCAP
VDD, VSS
MCLR
Timers
1-3
ADC1
UART1
OC/
IC1,2,7,8
CNx
SPI1
I2C1
PWM1,2
Note:
Not all pins or features are implemented on all device pinout configurations. See pinout diagrams for the specific pins
and features present on each device.
DS70289A-page 10
Preliminary
© 2007 Microchip Technology Inc.
PIC24HJ32GP202/204 and PIC24HJ16GP304
TABLE 1-1:
PINOUT I/O DESCRIPTIONS
Pin Name
Pin Type Buffer Type
Description
AN0-AN12
I
Analog
Analog input channels.
CLKI
I
ST/CMOS External clock source input. Always associated with OSC1 pin function.
CLKO
O
—
Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator
mode. Optionally functions as CLKO in RC and EC modes. Always associated
with OSC2 pin function.
OSC1
OSC2
I
ST/CMOS Oscillator crystal input. ST buffer when configured in RC mode; CMOS otherwise.
I/O
—
Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator
mode. Optionally functions as CLKO in RC and EC modes.
SOSCI
I
ST/CMOS 32.768 kHz low-power oscillator crystal input; CMOS otherwise.
SOSCO
O
—
32.768 kHz low-power oscillator crystal output.
CN0-CN30
I
ST
Change notification inputs.
Can be software programmed for internal weak pull-ups on all inputs.
IC1-IC2
IC7-IC8
I
ST
Capture inputs 1/2
Capture inputs 7/8
OCFA
OC1-OC2
I
O
ST
—
Compare Fault A input (for Compare Channels 1 and 2).
Compare outputs 1 through 2.
INT0
INT1
INT2
I
I
I
ST
ST
ST
External interrupt 0.
External interrupt 1.
External interrupt 2.
RA0-RA4
I/O
ST
PORTA is a bidirectional I/O port.
RA7-RA15
RB0-RB15
RC0-RC9
I/O
I/O
ST
ST
PORTB is a bidirectional I/O port.
PORTC is a bidirectional I/O port.
T1CK
T2CK
T3CK
I
I
I
ST
ST
ST
Timer1 external clock input.
Timer2 external clock input.
Timer3 external clock input.
U1CTS
U1RTS
U1RX
U1TX
I
O
I
ST
—
ST
—
UART1 clear to send.
UART1 ready to send.
UART1 receive.
O
UART1 transmit.
SCK1
SDI1
SDO1
SS1
I/O
I
O
ST
ST
—
Synchronous serial clock input/output for SPI1.
SPI1 data in.
SPI1 data out.
I/O
ST
SPI1 slave synchronization or frame pulse I/O.
SCL1
SDA1
ASCL1
ASDA1
I/O
I/O
I/O
I/O
ST
ST
ST
ST
Synchronous serial clock input/output for I2C1.
Synchronous serial data input/output for I2C1.
Alternate synchronous serial clock input/output for I2C1.
Alternate synchronous serial data input/output for I2C1.
TMS
TCK
TDI
I
I
I
ST
ST
ST
—
JTAG Test mode select pin.
JTAG test clock input pin.
JTAG test data input pin.
JTAG test data output pin.
TDO
O
PGD1/EMUD1
PGC1/EMUC1
PGD2/EMUD2
PGC2/EMUC2
PGD3/EMUD3
PGC3/EMUC3
I/O
ST
ST
ST
ST
ST
ST
Data I/O pin for programming/debugging communication channel 1.
Clock input pin for programming/debugging communication channel 1.
Data I/O pin for programming/debugging communication channel 2.
Clock input pin for programming/debugging communication channel 2.
Data I/O pin for programming/debugging communication channel 3.
Clock input pin for programming/debugging communication channel 3.
I
I/O
I
I/O
I
VDDCORE
VSS
P
P
I
—
CPU logic filter capacitor connection.
Ground reference for logic and I/O pins.
Analog voltage reference (high) input.
Analog voltage reference (low) input.
—
VREF+
VREF-
Analog
Analog
I
Legend: CMOS = CMOS compatible input or output
Analog = Analog input
I = Input
O = Output
P = Power
ST = Schmitt Trigger input with CMOS levels
© 2007 Microchip Technology Inc.
Preliminary
DS70289A-page 11
PIC24HJ32GP202/204 and PIC24HJ16GP304
TABLE 1-1:
Pin Name
AVDD
PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Type Buffer Type
Description
P
I/P
P
P
ST
P
Positive supply for analog modules.
MCLR
AVSS
VDD
Master Clear (Reset) input. This pin is an active-low Reset to the device.
Ground reference for analog modules.
P
—
Positive supply for peripheral logic and I/O pins.
Legend: CMOS = CMOS compatible input or output
Analog = Analog input
I = Input
O = Output
P = Power
ST = Schmitt Trigger input with CMOS levels
DS70289A-page 12
Preliminary
© 2007 Microchip Technology Inc.
PIC24HJ32GP202/204 and PIC24HJ16GP304
2.1
Data Addressing Overview
2.0
CPU
The data space can be linearly addressed as 32K words
or 64 Kbytes using an Address Generation Unit (AGU).
The upper 32 Kbytes of the data space memory map can
optionally be mapped into program space at any 16K
program word boundary defined by the 8-bit Program
Space Visibility Page (PSVPAG) register. The program
to data space mapping feature lets any instruction
access program space as if it were data space.
Note:
This data sheet summarizes the features
of this group of PIC24HJ32GP202/204
and PIC24HJ16GP304 devices. It is not
intended to be a comprehensive reference
source. To complement the information in
this data sheet, refer to the “PIC24H
Family Reference Manual”.
The PIC24HJ32GP202/204 and PIC24HJ16GP304
CPU modules have a 16-bit (data) modified Harvard
architecture with an enhanced instruction set and
addressing modes. The CPU has a 24-bit instruction
word with a variable length opcode field. The Program
Counter (PC) is 23 bits wide and addresses up to 4M x
24 bits of user program memory space. The actual
amount of program memory implemented varies by
device. A single-cycle instruction prefetch mechanism
is used to help maintain throughput and provides pre-
dictable execution. All instructions execute in a single
cycle, with the exception of instructions that change the
program flow, the double word move (MOV.D) instruc-
tion and the table instructions. Overhead-free, single-
cycle program loop constructs are supported using the
REPEATinstruction, which is interruptible at any point.
The data space also includes 2 Kbytes of DMA RAM,
which is primarily used for DMA data transfers, but this
may be used as general purpose RAM.
2.2
Special MCU Features
The PIC24HJ32GP202/204 and PIC24HJ16GP304
feature a 17-bit by 17-bit, single-cycle multiplier. The
multiplier can perform signed, unsigned and mixed-
sign multiplication. Using a 17-bit by 17-bit multiplier for
16-bit by 16-bit multiplication makes mixed-sign
multiplication possible.
The PIC24HJ32GP202/204 and PIC24HJ16GP304
supports 16/16 and 32/16 integer divide operations. All
divide instructions are iterative operations. They must
be executed within a REPEAT loop, resulting in a total
execution time of 19 instruction cycles. The divide
operation can be interrupted during any of those
19 cycles without loss of data.
The PIC24HJ32GP202/204 and PIC24HJ16GP304
devices have sixteen, 16-bit working registers in the
programmer’s model. Each of the working registers can
serve as a data, address or address offset register. The
16th working register (W15) operates as a software
Stack Pointer (SP) for interrupts and calls.
A multi-bit data shifter is used to perform up to a 16-bit,
left or right shift in a single cycle.
The PIC24HJ32GP202/204 and PIC24HJ16GP304
instruction set includes many addressing modes and is
designed for optimum C compiler efficiency. For most
instructions,
the
PIC24HJ32GP202/204
and
PIC24HJ16GP304 is capable of executing a data (or
program data) memory read, a working register (data)
read, a data memory write and a program (instruction)
memory read per instruction cycle. As a result, three
parameter instructions can be supported, allowing
A + B = C operations to be executed in a single cycle.
A block diagram of the CPU is shown in Figure 2-1, and
the programmer’s model for the PIC24HJ32GP202/
204 and PIC24HJ16GP304 is shown in Figure 2-2.
© 2007 Microchip Technology Inc.
Preliminary
DS70289A-page 13
PIC24HJ32GP202/204 and PIC24HJ16GP304
FIGURE 2-1:
PIC24HJ32GP202/204 AND PIC24HJ16GP304 CPU CORE BLOCK DIAGRAM
PSV & Table
Data Access
Control Block
X Data Bus
Interrupt
Controller
16
16
16
8
Data Latch
X RAM
23
16
PCH PCL
Program Counter
PCU
23
Address
Latch
Loop
Control
Logic
Stack
Control
Logic
23
16
Address Generator Units
Address Latch
Program Memory
Data Latch
EA MUX
Address Bus
ROM Latch
24
16
16
Instruction
Decode &
Control
Instruction Reg
16
17 x 17
Multiplier
Control Signals
to Various Blocks
16 x 16
W Register Array
Divide Support
16
16-bit ALU
16
To Peripheral Modules
DS70289A-page 14
Preliminary
© 2007 Microchip Technology Inc.
PIC24HJ32GP202/204 and PIC24HJ16GP304
FIGURE 2-2:
PIC24HJ32GP202/204 AND PIC24HJ16GP304 PROGRAMMER’S MODEL
D15
D0
W0/WREG
W1
PUSH.S Shadow
DO Shadow
W2
W3
Legend
W4
W5
W6
W7
Working Registers
W8
W9
W10
W11
W12
W13
W14/Frame Pointer
W15/Stack Pointer
SPLIM
Stack Pointer Limit Register
Program Counter
PC22
PC0
0
0
7
TBLPAG
Data Table Page Address
7
0
PSVPAG
Program Space Visibility Page Address
15
0
0
RCOUNT
REPEATLoop Counter
15
Core Configuration Register
CORCON
—
—
—
—
—
—
—
DC
RA
N
Z
C
IPL2 IPL1 IPL0
OV
STATUS Register
SRH
SRL
© 2007 Microchip Technology Inc.
Preliminary
DS70289A-page 15
PIC24HJ32GP202/204 and PIC24HJ16GP304
2.3
CPU Control Registers
REGISTER 2-1:
SR: CPU STATUS REGISTER
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
R/W-0
DC
bit 15
bit 8
R/W-0(1)
R/W-0(2)
IPL<2:0>(2)
R/W-0(2)
R-0
RA
R/W-0
N
R/W-0
OV
R/W-0
Z
R/W-0
C
bit 7
bit 0
Legend:
C = Clear only bit
S = Set only bit
‘1’ = Bit is set
R = Readable bit
W = Writable bit
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
-n = Value at POR
x = Bit is unknown
bit 15-9
bit 8
Unimplemented: Read as ‘0’
DC: MCU ALU Half Carry/Borrow bit
1= A carry-out from the 4th low-order bit (for byte sized data) or 8th low-order bit (for word sized data)
of the result occurred
0= No carry-out from the 4th low-order bit (for byte sized data) or 8th low-order bit (for word sized
data) of the result occurred
bit 7-5
IPL<2:0>: CPU Interrupt Priority Level Status bits(2)
111= CPU Interrupt Priority Level is 7 (15), user interrupts disabled
110= CPU Interrupt Priority Level is 6 (14)
101= CPU Interrupt Priority Level is 5 (13)
100= CPU Interrupt Priority Level is 4 (12)
011= CPU Interrupt Priority Level is 3 (11)
010= CPU Interrupt Priority Level is 2 (10)
001= CPU Interrupt Priority Level is 1 (9)
000= CPU Interrupt Priority Level is 0 (8)
bit 4
bit 3
bit 2
RA: REPEAT Loop Active bit
1= REPEAT loop in progress
0= REPEAT loop not in progress
N: MCU ALU Negative bit
1= Result was negative
0= Result was non-negative (zero or positive)
OV: MCU ALU Overflow bit
This bit is used for signed arithmetic (2’s complement). It indicates an overflow of the magnitude which
causes the sign bit to change state.
1= Overflow occurred for signed arithmetic (in this arithmetic operation)
0= No overflow occurred
bit 1
bit 0
Z: MCU ALU Zero bit
1= An operation which affects the Z bit has set it at some time in the past
0= The most recent operation which affects the Z bit has cleared it (i.e., a non-zero result)
C: MCU ALU Carry/Borrow bit
1= A carry-out from the Most Significant bit (MSb) of the result occurred
0= No carry-out from the Most Significant bit of the result occurred
Note 1: The IPL<2:0> bits are concatenated with the IPL<3> bit (CORCON<3>) to form the CPU Interrupt Priority
Level. The value in parentheses indicates the IPL if IPL<3> = 1. User interrupts are disabled when
IPL<3> = 1.
2: The IPL<2:0> Status bits are read only when NSTDIS = 1(INTCON1<15>).
DS70289A-page 16
Preliminary
© 2007 Microchip Technology Inc.
PIC24HJ32GP202/204 and PIC24HJ16GP304
REGISTER 2-2:
CORCON: CORE CONTROL REGISTER
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
bit 15
bit 8
bit 0
U-0
—
U-0
—
U-0
—
U-0
—
R/C-0
IPL3(1)
R/W-0
PSV
U-0
—
U-0
—
bit 7
Legend:
C = Clear only bit
W = Writable bit
‘x = Bit is unknown
R = Readable bit
0’ = Bit is cleared
-n = Value at POR
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
bit 15-4
bit 3
Unimplemented: Read as ‘0’
IPL3: CPU Interrupt Priority Level Status bit 3(1)
1= CPU interrupt priority level is greater than 7
0= CPU interrupt priority level is 7 or less
bit 2
PSV: Program Space Visibility in Data Space Enable bit
1= Program space visible in data space
0= Program space not visible in data space
bit 1-0
Unimplemented: Read as ‘0’
Note 1: The IPL3 bit is concatenated with the IPL<2:0> bits (SR<7:5>) to form the CPU interrupt priority level.
© 2007 Microchip Technology Inc.
Preliminary
DS70289A-page 17
PIC24HJ32GP202/204 and PIC24HJ16GP304
2.4.2
DIVIDER
2.4
Arithmetic Logic Unit (ALU)
The divide block supports 32-bit/16-bit and 16-bit/16-bit
signed and unsigned integer divide operations with the
following data sizes.
The PIC24HJ32GP202/204 and PIC24HJ16GP304
Arithmetic Logic Unit (ALU) is 16 bits wide and is capa-
ble of addition, subtraction, bit shifts and logic opera-
tions. Unless otherwise mentioned, arithmetic
operations are 2’s complement in nature. The ALU may
affect the values of the Carry (C), Zero (Z), Negative
(N), Overflow (OV) and Digit Carry (DC) Status bits in
the SR register depending on the operation. The C and
DC Status bits operate as Borrow and Digit Borrow bits
respectively, for subtraction operations.
1. 32-bit signed/16-bit signed divide
2. 32-bit unsigned/16-bit unsigned divide
3. 16-bit signed/16-bit signed divide
4. 16-bit unsigned/16-bit unsigned divide
The quotient for all divide instructions ends up in W0
and the remainder in W1. A 16-bit signed and unsigned
DIVinstructions can specify any W register for both the
16-bit divisor (Wn) and any W register (aligned) pair
(W(m + 1):Wm) for the 32-bit dividend. The divide algo-
rithm takes one cycle per bit of divisor, so both 32-bit/
16-bit and 16-bit/16-bit instructions take the same num-
ber of cycles to execute.
The ALU can perform 8-bit or 16-bit operations
depending on the mode of the instruction that is used.
Data for the ALU operation can come from the W reg-
ister array, or data memory depending on the address-
ing mode of the instruction. Likewise, output data from
the ALU can be written to the W register array or a data
memory location.
2.4.3
MULTI-BIT DATA SHIFTER
Refer to the “dsPIC30F/33F Programmer’s Reference
Manual” (DS70157) for more information on the SR bits
affected by each instruction.
The multi-bit data shifter is capable of performing up to
16-bit arithmetic or logic right shifts, or up to 16-bit left
shifts in a single cycle. The source can be either a
working register or a memory location.
The PIC24HJ32GP202/204 and PIC24HJ16GP304
CPU incorporates hardware support for both multiplica-
tion and division. This includes a dedicated hardware
multiplier and a support hardware for 16-bit divisor divi-
sion.
The shifter requires a signed binary value to determine
both the magnitude (number of bits) and direction of the
shift operation. A positive value shifts the operand right.
and a negative value shifts the operand left. A value of
‘0’ does not modify the operand.
2.4.1
MULTIPLIER
Using the high-speed 17-bit x 17-bit multiplier, the ALU
supports unsigned, signed or mixed-sign operation in
several multiplication modes:
• 16-bit x 16-bit signed
• 16-bit x 16-bit unsigned
• 16-bit signed x 5-bit (literal) unsigned
• 16-bit unsigned x 16-bit unsigned
• 16-bit unsigned x 5-bit (literal) unsigned
• 16-bit unsigned x 16-bit signed
• 8-bit unsigned x 8-bit unsigned
DS70289A-page 18
Preliminary
© 2007 Microchip Technology Inc.
PIC24HJ32GP202/204 and PIC24HJ16GP304
3.1
Program Address Space
3.0
MEMORY ORGANIZATION
The program address memory space of the
PIC24HJ32GP202/204 and PIC24HJ16GP304
Note:
This data sheet summarizes the features
of the PIC24HJ32GP202/204 and
PIC24HJ16GP304 devices. It is not
intended to be a comprehensive reference
source. To complement the information in
this data sheet, refer to the “PIC24H
Family Reference Manual”.
devices is 4M instructions. The space is addressable
by a 24-bit value derived either from the 23-bit Program
Counter (PC) during program execution, or from table
operation or data space remapping as described in
Section 3.4 “Interfacing Program and Data Memory
Spaces”.
The PIC24HJ32GP202/204 and PIC24HJ16GP304
architecture features separate program and data mem-
ory spaces and buses. This architecture also allows the
direct access of program memory from the data space
during code execution.
User application access to the program memory space
is restricted to the lower half of the address range
(0x000000 to 0x7FFFFF). The exception is the use of
TBLRD/TBLWT operations, which use TBLPAG<7> to
permit access to the Configuration bits and Device ID
sections of the configuration memory space.
The memory maps for the PIC24HJ32GP202/204 and
PIC24HJ16GP304 devices are shown in Figure 3-1.
FIGURE 3-1:
PROGRAM MEMORY FOR PIC24HJ32GP202/204 AND PIC24HJ16GP304 DEVICES
PIC24HJ32GP202/204
PIC24HJ16GP304
0x000000
0x000002
0x000004
0x000000
0x000002
0x000004
GOTOInstruction
Reset Address
GOTOInstruction
Reset Address
Interrupt Vector Table
Reserved
Interrupt Vector Table
Reserved
0x0000FE
0x000100
0x000104
0x0001FE
0x000200
0x0000FE
0x000100
0x000104
0x0001FE
0x000200
Alternate Vector Table
Alternate Vector Table
User Program
Flash Memory
(11264 instructions)
User Program
Flash Memory
(5632 instructions)
0x0057FE
0x005800
0x002BFE
0x002C00
Unimplemented
Unimplemented
(Read ‘
0’s)
(Read ‘0’s)
0x7FFFFE
0x800000
0x7FFFFE
0x800000
Reserved
Reserved
0xF7FFFE
0xF80000
0xF80017
0xF80018
0xF7FFFE
0xF80000
0xF80017
0xF80018
Device Configuration
Registers
Device Configuration
Registers
Reserved
DEVID (2)
Reserved
DEVID (2)
0xFEFFFE
0xFF0000
0xFEFFFE
0xFF0000
0xFFFFFE
0xFFFFFE
© 2007 Microchip Technology Inc.
Preliminary
DS70289A-page 19
PIC24HJ32GP202/204 and PIC24HJ16GP304
3.1.1
PROGRAM MEMORY
ORGANIZATION
3.1.2
INTERRUPT AND TRAP VECTORS
All PIC24HJ32GP202/204 and PIC24HJ16GP304
devices reserve the addresses between 0x00000 and
0x000200 for hard-coded program execution vectors.
A hardware Reset vector is provided to redirect code
execution from the default value of the PC on device
Reset to the actual start of code. A GOTOinstruction is
programmed by the user application at 0x000000, with
the actual address for the start of code at 0x000002.
The program memory space is organized in word-
addressable blocks. Although it is treated as 24 bits
wide, it is more appropriate to think of each address of
the program memory as a lower and upper word, with
the upper byte of the upper word being unimplemented.
The lower word always has an even address, while the
upper word has an odd address (See Figure 3-2).
PIC24HJ32GP202/204
and
PIC24HJ16GP304
Program memory addresses are always word-aligned
on the lower word, and addresses are incremented or
decremented by two during code execution. This
arrangement provides compatibility with data memory
space addressing and makes data in the program
memory space accessible.
devices also have two interrupt vector tables, located
from 0x000004 to 0x0000FF and 0x000100 to
0x0001FF. These vector tables allow each of the many
device interrupt sources to be handled by separate
Interrupt Service Routines (ISRs). Section 6.1 “Inter-
rupt Vector Table” provides a more detailed discus-
sion of the interrupt vector tables.
FIGURE 3-2:
PROGRAM MEMORY ORGANIZATION
least significant word
PC Address
most significant word
23
msw
Address
(lsw Address)
16
8
0
0x000001
0x000003
0x000005
0x000007
0x000000
0x000002
0x000004
0x000006
00000000
00000000
00000000
00000000
Program Memory
‘Phantom’ Byte
(read as ‘0’)
Instruction Width
DS70289A-page 20
Preliminary
© 2007 Microchip Technology Inc.
PIC24HJ32GP202/204 and PIC24HJ16GP304
All word accesses must be aligned to an even address.
Misaligned word data fetches are not supported, so
3.2
Data Address Space
The PIC24HJ32GP202/204 and PIC24HJ16GP304
CPU has a separate 16-bit-wide data memory space.
The data space is accessed using separate Address
Generation Units (AGUs) for read and write operations.
The data memory maps is shown in Figure 3-3.
care must be taken when mixing byte and word opera-
tions, or when translating from 8-bit MCU code. If a
misaligned read or write is attempted, an address error
trap is generated. If the error occurred on a read, the
instruction underway is completed. If the instruction
occurred on a write, the instruction is executed but the
write does not occur. In either case, a trap is then exe-
cuted, allowing the system and/or user application to
examine the machine state prior to execution of the
address Fault.
All Effective Addresses (EAs) in the data memory space
are 16 bits wide and point to the bytes within the data
space. This arrangement gives a data space address
range of 64 Kbytes or 32K words. The lower half of the
data memory space (that is, when EA<15> = 0) is used
for implemented memory addresses, while the upper
half (EA<15> = 1) is reserved for the Program Space
Visibility area (see Section 3.4.3 “Reading Data From
Program Memory Using Program Space Visibility”).
All byte loads into any W register are loaded into the
Least Significant Byte. The Most Significant Byte is not
modified.
A sign-extend instruction (SE) is provided to allow
users to translate 8-bit signed data to 16-bit signed
values. Alternatively, for 16-bit unsigned data, user
applications can clear the MSB of any W register by
executing a zero-extend (ZE) instruction on the appro-
priate address.
PIC24HJ32GP202/204
and
PIC24HJ16GP304
devices implement up to 30 Kbytes of data memory.
Should an EA point to a location outside of this area, an
all-zero word or byte will be returned.
3.2.1
DATA SPACE WIDTH
3.2.3
SFR SPACE
The data memory space is organized in byte address-
able, 16-bit wide blocks. Data is aligned in data
memory and registers as 16-bit words, but all data
space EAs resolve to bytes. The Least Significant
Bytes (LSBs) of each word have even addresses, while
the Most Significant Bytes (MSBs) have odd
addresses.
The first 2 Kbytes of the Near Data Space, from 0x0000
to 0x07FF, is primarily occupied by Special Function
Registers (SFRs). These are used by the
PIC24HJ32GP202/204 and PIC24HJ16GP304 core
and peripheral modules to control the operation of the
device.
SFRs are distributed among the modules that they
control, and are generally grouped together by module.
Much of the SFR space contains unused addresses;
these are read as ‘0’. A complete listing of implemented
SFRs, including their addresses, is shown in Table 3-1
through Table 3-21.
3.2.2
DATA MEMORY ORGANIZATION
AND ALIGNMENT
To maintain backward compatibility with PIC® devices
and improve data space memory usage efficiency, the
PIC24HJ32GP202/204 and PIC24HJ16GP304 instruc-
tion set supports both word and byte operations. As a
consequence of byte accessibility, all effective address
calculations are internally scaled to step through word-
aligned memory. For example, the core recognizes that
Post-Modified Register Indirect Addressing mode
[WS++] will result in a value of Ws + 1 for byte
operations and Ws + 2 for word operations.
Note:
The actual set of peripheral features and
interrupts varies by the device. Refer to
the corresponding device tables and
pinout diagrams for device-specific infor-
mation.
3.2.4
NEAR DATA SPACE
Data byte reads will read the complete word that
contains the byte, using the LSB of any EA to deter-
mine which byte to select. The selected byte is placed
onto the LSB of the data path. That is, data memory
and registers are organized as two parallel byte-wide
entities with shared (word) address decode, but sepa-
rate write lines. Data byte writes only write to the corre-
sponding side of the array or register that matches the
byte address.
The 8-Kbyte area between 0x0000 and 0x1FFF is
referred to as the Near Data Space. Locations in this
space are directly addressable via 13-bit absolute
address field within all memory direct instructions.
Additionally, the whole data space is addressable using
MOV instructions, which support Memory Direct
Addressing mode with a 16-bit address field, or by
using Indirect Addressing mode using a working
register as an address pointer.
© 2007 Microchip Technology Inc.
Preliminary
DS70289A-page 21
PIC24HJ32GP202/204 and PIC24HJ16GP304
FIGURE 3-3:
DATA MEMORY MAP FOR PIC24HJ32GP202/204 AND PIC24HJ16GP304
DEVICES WITH 2 KB RAM
MSB
Address
LSB
Address
16 bits
MSb
LSb
0x0000
0x0001
2 Kbyte
SFR Space
SFR Space
0x07FE
0x0800
0x07FF
0x0801
X Data RAM (X)
8 Kbyte
2 Kbyte
Near data space
SRAM Space
0x0FFF
0x1001
0x0FFE
0x1000
0x1FFF
0x2001
0x1FFE
0x2000
0x8001
0x8000
X Data
Optionally
Mapped
Unimplemented (X)
into Program
Memory
0xFFFF
0xFFFE
DS70289A-page 22
Preliminary
© 2007 Microchip Technology Inc.
PIC24HJ32GP202/204 and PIC24HJ16GP304
© 2007 Microchip Technology Inc.
Preliminary
DS70289A-page 23
PIC24HJ32GP202/204 and PIC24HJ16GP304
DS70289A-page 24
Preliminary
© 2007 Microchip Technology Inc.
PIC24HJ32GP202/204 and PIC24HJ16GP304
© 2007 Microchip Technology Inc.
Preliminary
DS70289A-page 25
PIC24HJ32GP202/204 and PIC24HJ16GP304
DS70289A-page 26
Preliminary
© 2007 Microchip Technology Inc.
PIC24HJ32GP202/204 and PIC24HJ16GP304
© 2007 Microchip Technology Inc.
Preliminary
DS70289A-page 27
PIC24HJ32GP202/204 and PIC24HJ16GP304
DS70289A-page 28
Preliminary
© 2007 Microchip Technology Inc.
PIC24HJ32GP202/204 and PIC24HJ16GP304
© 2007 Microchip Technology Inc.
Preliminary
DS70289A-page 29
PIC24HJ32GP202/204 and PIC24HJ16GP304
DS70289A-page 30
Preliminary
© 2007 Microchip Technology Inc.
PIC24HJ32GP202/204 and PIC24HJ16GP304
© 2007 Microchip Technology Inc.
Preliminary
DS70289A-page 31
PIC24HJ32GP202/204 and PIC24HJ16GP304
DS70289A-page 32
Preliminary
© 2007 Microchip Technology Inc.
PIC24HJ32GP202/204 and PIC24HJ16GP304
© 2007 Microchip Technology Inc.
Preliminary
DS70289A-page 33
PIC24HJ32GP202/204 and PIC24HJ16GP304
3.2.5
In addition to its use as a working register, the W15
register in the PIC24HJ32GP202/204 and
PIC24HJ16GP304 devices is also used as a software
Stack Pointer. The Stack Pointer always points to the
first available free word and grows from lower to higher
addresses. It pre-decrements for stack pops and post-
increments for stack pushes, as shown in Figure 3-4.
For a PC push during any CALLinstruction, the MSB of
the PC is zero-extended before the push, ensuring that
the MSB is always clear.
SOFTWARE STACK
3.2.6
DATA RAM PROTECTION FEATURE
The PIC24H product family supports Data RAM
protection features that enable segments of RAM to be
protected when used in conjunction with Boot and
Secure Code Segment Security. BSRAM (Secure RAM
segment for BS) is accessible only from the Boot
Segment Flash code when enabled. SSRAM (Secure
RAM segment for RAM) is accessible only from the
Secure Segment Flash code when enabled. See
Table 3-1 for an overview of the BSRAM and SSRAM
SFRs.
Note:
A PC push during exception processing
concatenates the SRL register to the MSB
of the PC prior to the push.
3.3
Instruction Addressing Modes
The addressing modes shown in Table 3-22 form the
basis of the addressing modes optimized to support the
specific features of individual instructions. The
addressing modes provided in the MACclass of instruc-
tions differ from those in the other instruction types.
The Stack Pointer Limit register (SPLIM) associated
with the Stack Pointer sets an upper address boundary
for the stack. SPLIM is uninitialized at Reset. Similarly,
the Stack Pointer, SPLIM<0> is forced to ‘0’ because
all stack operations must be word aligned.
3.3.1
FILE REGISTER INSTRUCTIONS
When an EA is generated using W15 as a source or
destination pointer, the resulting address is compared
with the value in SPLIM. If the contents of the Stack
Pointer (W15) and the SPLIM register are equal and a
push operation is performed, a stack error trap will not
occur. The stack error trap will occur on a subsequent
push operation. For example, to cause a stack error
trap when the stack grows beyond address 0x2000 in
RAM, initialize the SPLIM with the value 0x1FFE.
Most file register instructions use a 13-bit address field
(f) to directly address data present in the first 8192
bytes of data memory (Near Data Space). Most file
register instructions employ a working register, W0,
which is denoted as WREG in these instructions. The
destination is typically either the same file register or
WREG (with the exception of the MUL instruction),
which writes the result to a register or register pair. The
MOV instruction allows additional flexibility and can
access the entire data space.
Similarly, a Stack Pointer underflow (stack error) trap is
generated when the Stack Pointer address is found to
be lesser than 0x0800. This prevents the stack from
interfering with the Special Function Register (SFR)
space.
3.3.2
MCU INSTRUCTIONS
The three-operand MCU instructions are of the form:
Operand 3 = Operand 1 <function> Operand 2
A write to the SPLIM register should not be immediately
followed by an indirect read operation using W15.
where, Operand 1 is always a working register (that is,
the addressing mode can only be register direct), which
is referred to as Wb. Operand 2 can be a W register,
fetched from data memory, or a 5-bit literal. The result
location can be either a W register or a data memory
location. The following addressing modes are
supported by MCU instructions:
FIGURE 3-4:
CALLSTACK FRAME
0x0000
15
0
• Register Direct
• Register Indirect
PC<15:0>
000000000
W15 (before CALL)
• Register Indirect Post-Modified
• Register Indirect Pre-Modified
• 5-bit or 10-bit Literal
PC<22:16>
<Free Word>
W15 (after CALL)
POP : [--W15]
PUSH: [W15++]
Note:
Not all instructions support all the
addressing modes given above. Individual
instructions can support different subsets
of these addressing modes.
DS70289A-page 34
Preliminary
© 2007 Microchip Technology Inc.
PIC24HJ32GP202/204 and PIC24HJ16GP304
TABLE 3-22: FUNDAMENTAL ADDRESSING MODES SUPPORTED
Addressing Mode
File Register Direct
Description
The address of the file register is specified explicitly.
The contents of a register are accessed directly.
The contents of Wn forms the Effective Address (EA.)
Register Direct
Register Indirect
Register Indirect Post-Modified
The contents of Wn forms the EA. Wn is post-modified (incremented or
decremented) by a constant value.
Register Indirect Pre-Modified
Wn is pre-modified (incremented or decremented) by a signed constant value
to form the EA.
Register Indirect with Register Offset The sum of Wn and Wb forms the EA.
(Register Indexed)
Register Indirect with Literal Offset
The sum of Wn and a literal forms the EA.
In summary, move instructions support the following
MOVE (MOV) INSTRUCTION
3.3.3
addressing modes:
Move instructions provide a greater degree of address-
ing flexibility than the other instructions. In addition to
the Addressing modes supported by most MCU
instructions, MOV instructions also support Register
Indirect with Register Offset Addressing mode. This is
also referred to as Register Indexed mode.
• Register Direct
• Register Indirect
• Register Indirect Post-modified
• Register Indirect Pre-modified
• Register Indirect with Register Offset (Indexed)
• Register Indirect with Literal Offset
• 8-bit Literal
Note:
For the MOV instructions, the addressing
mode specified in the instruction can differ
for the source and the destination EA.
However, the 4-bit Wb (Register Offset)
field is shared by both source and
destination (but typically only used by
one).
• 16-bit Literal
Note:
Not all instructions support all the address-
ing modes given above. Individual instruc-
tions may support different subsets of
these addressing modes.
3.3.4
OTHER INSTRUCTIONS
Besides the addressing modes outlined previously,
some instructions use literal constants of various sizes.
For example, BRA (branch) instructions use 16-bit
signed literals to specify the branch destination directly,
whereas the DISI instruction uses a 14-bit unsigned
literal field. In some instructions, such as ADD Acc, the
source of an operand or result is implied by the opcode
itself. Certain operations, such as NOP, do not have any
operands.
© 2007 Microchip Technology Inc.
Preliminary
DS70289A-page 35
PIC24HJ32GP202/204 and PIC24HJ16GP304
3.4.1
ADDRESSING PROGRAM SPACE
3.4
Interfacing Program and Data
Memory Spaces
Since the address ranges for the data and program
spaces are 16 and 24 bits, respectively, a method is
needed to create a 23-bit or 24-bit program address
from 16-bit data registers. The solution depends on the
interface method to be used.
The PIC24HJ32GP202/204 and PIC24HJ16GP304
architecture uses a 24-bit-wide program space and a
16-bit wide data space. The architecture is also a mod-
ified Harvard scheme, which means that the data can
also be present in the program space. To use this data
successfully, it must be accessed in a way that pre-
serves the alignment of information in both spaces.
For table operations, the 8-bit Table Page register
(TBLPAG) is used to define a 32K word region within
the program space. This is concatenated with a 16-bit
EA to arrive at a full 24-bit program space address. In
this format, the Most Significant bit of TBLPAG is used
to determine if the operation occurs in the user memory
(TBLPAG<7> = 0) or the configuration memory
(TBLPAG<7> = 1).
Aside from normal execution, the PIC24HJ32GP202/
204 and PIC24HJ16GP304 architecture provides two
methods by which program space can be accessed
during operation:
• Using table instructions to access individual bytes
or words anywhere in the program space
For remapping operations, the 8-bit Program Space
Visibility register (PSVPAG) is used to define a
16K word page in the program space. When the Most
Significant bit of the EA is ‘1’, PSVPAG is concatenated
with the lower 15 bits of the EA to form a 23-bit program
space address. Unlike table operations, this limits
remapping operations strictly to the user memory area.
• Remapping a portion of the program space into
the data space (Program Space Visibility)
Table instructions allow an application to read or write
to small areas of the program memory. This capability
makes the method ideal for accessing data tables that
need to be updated periodically. It also allows access
to all bytes of the program word. The remapping
method allows an application to access a large block of
data on a read-only basis, which is ideal for look ups
from a large table of static data. The application can
only access the Least Significant word of the program
word.
Table 3-23 and Figure 3-5 show how the program EA is
created for table operations and remapping accesses
from the data EA. Here, P<23:0> refers to a program
space word, and D<15:0> refers to a data space word.
TABLE 3-23: PROGRAM SPACE ADDRESS CONSTRUCTION
Program Space Address
Access
Space
Access Type
<23>
<22:16>
<15>
<14:1>
<0>
Instruction Access
(Code Execution)
User
User
0
PC<22:1>
0
0xx xxxx xxxx xxxx xxxx xxx0
TBLRD/TBLWT
(Byte/Word Read/Write)
TBLPAG<7:0>
0xxx xxxx
Data EA<15:0>
xxxx xxxx xxxx xxxx
Data EA<15:0>
Configuration
TBLPAG<7:0>
1xxx xxxx
xxxx xxxx xxxx xxxx
Program Space Visibility User
(Block Remap/Read)
0
0
PSVPAG<7:0>
xxxx xxxx
Data EA<14:0>(1)
xxx xxxx xxxx xxxx
Note 1: Data EA<15> is always ‘1’ in this case, but is not used in calculating the program space address. Bit 15 of
the address is PSVPAG<0>.
DS70289A-page 36
Preliminary
© 2007 Microchip Technology Inc.
PIC24HJ32GP202/204 and PIC24HJ16GP304
FIGURE 3-5:
DATA ACCESS FROM PROGRAM SPACE ADDRESS GENERATION
Program Counter(1)
Program Counter
23 bits
0
0
1/0
EA
Table Operations(2)
1/0
TBLPAG
8 bits
16 bits
24 bits
Select
1
0
EA
Program Space Visibility(1)
(Remapping)
0
PSVPAG
8 bits
15 bits
23 bits
Byte Select
User/Configuration
Space Select
Note 1: The Least Significant bit (LSb) of program space addresses is always fixed as ‘0’ to
maintain word alignment of data in the program and data spaces.
2: Table operations are not required to be word-aligned. Table read operations are permitted
in the configuration memory space.
© 2007 Microchip Technology Inc.
Preliminary
DS70289A-page 37
PIC24HJ32GP202/204 and PIC24HJ16GP304
In Byte mode, either the upper or lower byte of the
lower program word is mapped to the lower byte of
a data address. The upper byte is selected when
Byte Select is ‘1’; the lower byte is selected when
it is ‘0’.
3.4.2
DATA ACCESS FROM PROGRAM
MEMORY USING TABLE
INSTRUCTIONS
The TBLRDL and TBLWTL instructions offer a direct
method to read or write the lower word of any address
within the program space without going through data
space. The TBLRDH and TBLWTH instructions are the
only methods to read or write the upper 8 bits of a pro-
gram space word as data.
• TBLRDH (Table Read High): In Word mode, this
instruction maps the entire upper word of a program
address (P<23:16>) to a data address. Note that
D<15:8>, the ‘phantom byte’, will always be ‘0’.
In Byte mode, this instruction maps the upper or
lower byte of the program word to D<7:0> of the
data address, as in the TBLRDL instruction. Note
that the data will always be ‘0’ when the upper
‘Phantom’ byte is selected (Byte Select = 1).
The PC is incremented by 2 for each successive 24-bit
program word. This allows program memory addresses
to directly map to data space addresses. Program
memory can thus be regarded as two 16-bit wide word
address spaces, residing side by side, each with the
same address range. TBLRDLand TBLWTLaccess the
space that contains the least significant data word.
TBLRDH and TBLWTH access the space that contains
the upper data byte.
In a similar fashion, two table instructions, TBLWTH
and TBLWTL, are used to write individual bytes or
words to a program space address. The details of
their operation are explained in Section 4.0 “Flash
Program Memory”.
Two table instructions are provided to move byte or
word sized (16-bit) data to and from program space.
Both function as either byte or word operations.
For all table operations, the area of program memory
space to be accessed is determined by the Table Page
register (TBLPAG). TBLPAG covers the entire program
memory space of the device, including user and config-
uration spaces. When TBLPAG<7> = 0, the table page
is located in the user memory space. When
TBLPAG<7> = 1, the page is located in configuration
space.
• TBLRDL(Table Read Low): In Word mode, this
instruction maps the lower word of the program
space location (P<15:0>) to a data address
(D<15:0>).
FIGURE 3-6:
ACCESSING PROGRAM MEMORY WITH TABLE INSTRUCTIONS
Program Space
TBLPAG
02
23
15
0
0x000000
23
16
8
0
00000000
00000000
00000000
0x020000
0x030000
00000000
‘Phantom’ Byte
TBLRDH.B(Wn<0> = 0)
TBLRDL.B(Wn<0> = 1)
TBLRDL.B(Wn<0> = 0)
TBLRDL.W
The address for the table operation is determined by the data EA
within the page defined by the TBLPAG register.
Only read operations are shown; write operations are also valid in
the user memory area.
0x800000
DS70289A-page 38
Preliminary
© 2007 Microchip Technology Inc.
PIC24HJ32GP202/204 and PIC24HJ16GP304
24-bit program word are used to contain the data. The
upper 8 bits of any program space location used as
data should be programmed with ‘1111 1111’ or
‘0000 0000’ to force a NOP. This prevents possible
issues should the area of code ever be accidentally
executed.
3.4.3
READING DATA FROM PROGRAM
MEMORY USING PROGRAM
SPACE VISIBILITY
The upper 32 Kbytes of data space may optionally be
mapped into any 16K word page of the program space.
This option provides transparent access to the stored
constant data from the data space without the need to
use special instructions (such as TBLRDL/H).
Note:
PSV access is temporarily disabled during
table reads/writes.
Program space access through the data space occurs
if the Most Significant bit of the data space EA is ‘1’ and
program space visibility is enabled by setting the PSV
bit in the Core Control register (CORCON<2>). The
location of the program memory space to be mapped
into the data space is determined by the Program
Space Visibility Page register (PSVPAG). This 8-bit
register defines any one of 256 possible pages of
16K words in program space. In effect, PSVPAG
functions as the upper 8 bits of the program memory
address, with the 15 bits of the EA functioning as the
lower bits. By incrementing the PC by 2 for each
program memory word, the lower 15 bits of data space
addresses directly map to the lower 15 bits in the cor-
responding program space addresses.
For operations that use PSV and are executed outside
a REPEAT loop, the MOV and MOV.D instructions
require one instruction cycle in addition to the specified
execution time. All other instructions require two
instruction cycles in addition to the specified execution
time.
For operations that use PSV, and are executed inside
a REPEAT loop, these instances require two instruc-
tion cycles in addition to the specified execution time of
the instruction:
• Execution in the first iteration
• Execution in the last iteration
• Execution prior to exiting the loop due to an
interrupt
• Execution upon re-entering the loop after an
interrupt is serviced
Data reads to this area add a cycle to the instruction
being executed, since two program memory fetches
are required.
Any other iteration of the REPEAT loop will allow the
instruction using PSV to access data to execute in a
single cycle.
Although each data space address 8000h and higher
maps directly into a corresponding program memory
address (see Figure 3-7), only the lower 16 bits of the
FIGURE 3-7:
PROGRAM SPACE VISIBILITY OPERATION
When CORCON<2> = 1and EA<15> = 1:
Program Space
Data Space
PSVPAG
02
23
15
0
0x000000
0x0000
Data EA<14:0>
0x010000
0x018000
The data in the page
designated by
PSVPAG is mapped
into the upper half of
the data memory
space...
0x8000
PSV Area
...while the lower 15 bits
of the EA specify an
exact address within
the PSV area. This
corresponds exactly to
the same lower 15 bits
of the actual program
space address.
0xFFFF
0x800000
© 2007 Microchip Technology Inc.
Preliminary
DS70289A-page 39
PIC24HJ32GP202/204 and PIC24HJ16GP304
NOTES:
DS70289A-page 40
Preliminary
© 2007 Microchip Technology Inc.
PIC24HJ32GP202/204 and PIC24HJ16GP304
RTSP is accomplished using TBLRD (table read) and
TBLWT (table write) instructions. With RTSP, the user
4.0
FLASH PROGRAM MEMORY
Note:
This data sheet summarizes the features
of the PIC24HJ32GP202/204 and
PIC24HJ16GP304 devices. It is not
intended to be a comprehensive reference
source. To complement the information in
this data sheet, refer to the “PIC24H
Family Reference Manual”.
application can write program memory data either in
‘blocks’ or ‘rows’ of 64 instructions (192 bytes) at a time
or a single program memory word, and erase program
memory in blocks or ‘pages’ of 512 instructions (1536
bytes) at a time.
4.1
Table Instructions and Flash
Programming
The PIC24HJ32GP202/204 and PIC24HJ16GP304
devices contain internal Flash program memory to
store and execute application code. The memory is
readable, writable and erasable during normal opera-
tion over the entire VDD range.
Regardless of the method used, all programming of
Flash memory is done with the table read and table
write instructions. These allow direct read and write
access to the program memory space from the data
memory while the device is in normal operating mode.
The 24-bit target address in the program memory is
formed using bits <7:0> of the TBLPAG register and
the Effective Address (EA) from a W register specified
in the table instruction, as shown in Figure 4-1.
Flash memory can be programmed in two ways:
• In-Circuit Serial Programming™ (ICSP™)
programming capability
• Run-Time Self-Programming (RTSP)
ICSP
allows
a
PIC24HJ32GP202/204
and
The TBLRDLand the TBLWTLinstructions are used to
read or write to the bits<15:0> of program memory.
TBLRDLand TBLWTLcan access program memory in
both Word and Byte modes.
PIC24HJ16GP304 device to be serially programmed
while in the end application circuit. This is done with
two lines for programming clock and programming data
(one of the alternate programming pin pairs: PGC1/
PGD1, PGC2/PGD2 or PGC3/PGD3), and three other
lines for power (VDD), ground (VSS) and Master Clear
(MCLR). This allows customers to manufacture boards
with unprogrammed devices and then program the
microcontroller just before shipping the product. This
also allows the most recent firmware or a custom firm-
ware to be programmed.
The TBLRDHand TBLWTHinstructions are used to read
or write to bits<23:16> of program memory. TBLRDH
and TBLWTHcan also access program memory in Word
or Byte mode.
FIGURE 4-1:
ADDRESSING FOR TABLE REGISTERS
24 bits
Program Counter
Using
Program Counter
0
0
Working Reg EA
Using
Table Instruction
1/0
TBLPAG Reg
8 bits
16 bits
User/Configuration
Space Select
Byte
Select
24-bit EA
© 2007 Microchip Technology Inc.
Preliminary
DS70289A-page 41
PIC24HJ32GP202/204 and PIC24HJ16GP304
4.2
RTSP Operation
4.3
Control Registers
The PIC24HJ32GP202/204 and PIC24HJ16GP304
Flash program memory array is organized into rows of
64 instructions or 192 bytes. RTSP allows the user
application to erase a page of memory, which consists
of eight rows (512 instructions) at a time, and to pro-
gram one row or one word at a time. The 8-row erase
pages and single row write rows are edge-aligned from
the beginning of program memory, on boundaries of
1536 bytes and 192 bytes, respectively.
Two SFRs are used to read and write the program
Flash memory:
• NVMCON: Flash Memory Control Register
• NVMKEY: Non-Volatile Memory Key Register
The NVMCON register (Register 4-1) controls which
blocks need to be erased, which memory type is to be
programmed and the start of the programming cycle.
NVMKEY (Register 4-2) is a write-only register that is
used for write protection. To start a programming or
erase sequence, the user application must consecu-
tively write 55h and AAh to the NVMKEY register. Refer
to Section 4.4 “Programming Operations” for further
details.
The program memory implements holding buffers that
can contain 64 instructions of programming data. Prior
to the actual programming operation, the write data
must be loaded into the buffers sequentially. The
instruction words loaded must always be from a group
of 64 boundary.
4.4
Programming Operations
The basic sequence for RTSP programming is to set up
a Table Pointer, then do a series of TBLWTinstructions
to load the buffers. Programming is performed by set-
ting the control bits in the NVMCON register. A total of
64 TBLWTL and TBLWTH instructions are required to
load the instructions.
A complete programming sequence is necessary for
programming or erasing the internal Flash in RTSP
mode. A programming operation is nominally 4 ms in
duration and the processor stalls (waits) until the oper-
ation is finished. Setting the WR bit (NVMCON<15>)
starts the operation, and the WR bit is automatically
cleared when the operation is finished.
All table write operations are single-word writes (two
instruction cycles) because only the buffers are written.
A programming cycle is required for programming each
row.
DS70289A-page 42
Preliminary
© 2007 Microchip Technology Inc.
PIC24HJ32GP202/204 and PIC24HJ16GP304
REGISTER 4-1:
NVMCON: FLASH MEMORY CONTROL REGISTER
R/SO-0(1)
WR
R/W-0(1)
WREN
R/W-0(1)
WRERR
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
bit 15
bit 8
R/W-0(1)
bit 0
U-0
—
R/W-0(1)
ERASE
U-0
—
U-0
—
R/W-0(1)
R/W-0(1)
R/W-0(1)
NVMOP<3:0>(2)
bit 7
Legend:
SO = Satiable only bit
W = Writable bit
‘1’ = Bit is set
R = Readable bit
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
-n = Value at POR
bit 15
WR: Write Control bit
1= Initiates a Flash memory program or erase operation. The operation is self-timed and the bit is
cleared by hardware once operation is complete.
0= Program or erase operation is complete and inactive
bit 14
bit 13
WREN: Write Enable bit
1= Enable Flash program/erase operations
0= Inhibit Flash program/erase operations
WRERR: Write Sequence Error Flag bit
1= An improper program or erase sequence attempt or termination has occurred (bit is set
automatically on any set attempt of the WR bit)
0= The program or erase operation completed normally
bit 12-7
bit 6
Unimplemented: Read as ‘0’
ERASE: Erase/Program Enable bit
1= Perform the erase operation specified by NVMOP<3:0> on the next WR command
0= Perform the program operation specified by NVMOP<3:0> on the next WR command
bit 5-4
bit 3-0
Unimplemented: Read as ‘0’
NVMOP<3:0>: NVM Operation Select bits(2)
If ERASE = 1:
1111= Memory bulk erase operation
1101= Erase General Segment
1100= Erase Secure Segment
0011= No operation
0010= Memory page erase operation
0001= No operation
0000= Erase a single Configuration register byte
If ERASE = 0:
1111= No operation
1101= No operation
1100= No operation
0011= Memory word program operation
0010= No operation
0001= Memory row program operation
0000= Program a single Configuration register byte
Note 1: These bits can only be reset on POR.
2: All other combinations of NVMOP<3:0> are unimplemented.
© 2007 Microchip Technology Inc.
Preliminary
DS70289A-page 43
PIC24HJ32GP202/204 and PIC24HJ16GP304
REGISTER 4-2:
NVMKEY: NON-VOLATILE MEMORY KEY REGISTER
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
bit 15
bit 8
bit 0
W-0
bit 7
W-0
W-0
W-0
W-0
W-0
W-0
W-0
NVMKEY<7:0>
Legend:
SO = Satiable only bit
W = Writable bit
‘1’ = Bit is set
R = Readable bit
-n = Value at POR
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-8
bit 7-0
Unimplemented: Read as ‘0’
NVMKEY<7:0>: Key Register (Write Only) bits
DS70289A-page 44
Preliminary
© 2007 Microchip Technology Inc.
PIC24HJ32GP202/204 and PIC24HJ16GP304
4. Write the first 64 instructions from data RAM into
the program memory buffers (see Example 4-2).
4.4.1
PROGRAMMING ALGORITHM FOR
FLASH PROGRAM MEMORY
5. Write the program block to Flash memory:
Programmers can program one row of program Flash
memory at a time. To do this, it is necessary to erase
the 8-row erase page that contains the desired row.
The general process is:
a) Set the NVMOP bits to ‘0001’ to configure
for row programming. Clear the ERASE bit
and set the WREN bit.
b) Write 55h to NVMKEY.
c) Write AAh to NVMKEY.
1. Read eight rows of program memory
(512 instructions) and store in data RAM.
d) Set the WR bit. The programming cycle
begins and the CPU stalls for the duration of
the write cycle. When the write to Flash mem-
ory is done, the WR bit is cleared
automatically.
2. Update the program data in RAM with the
desired new data.
3. Erase the block (see Example 4-1):
a) Set the NVMOP bits (NVMCON<3:0>) to
‘0010’ to configure for block erase. Set
ERASE (NVMCON<6>) and WREN (NVM-
CON<14>) bits.
6. Repeat steps 4 and 5, using the next available
64 instructions from the block in data RAM by
incrementing the value in TBLPAG, until all
512 instructions are written back to Flash mem-
ory.
b) Write the starting address of the page to be
erased into the TBLPAG and W registers.
c) Write 55h to NVMKEY.
d) Write AAh to NVMKEY.
To protect against accidental operations, the write ini-
tiate sequence for NVMKEY must be used to allow any
erase or program operation to proceed. After the pro-
gramming command has been executed, the user
application must wait for the programming time until
programming is complete. The two instructions
following the start of the programming sequence
should be NOPs, as shown in Example 4-3.
e) Set the WR bit (NVMCON<15>). The erase
cycle begins and the CPU stalls for the dura-
tion of the erase cycle. When the erase is
done, the WR bit is cleared automatically.
EXAMPLE 4-1:
ERASING A PROGRAM MEMORY PAGE
; Set up NVMCON for block erase operation
MOV
MOV
#0x4042, W0
W0, NVMCON
;
; Initialize NVMCON
; Init pointer to row to be ERASED
MOV
MOV
MOV
#tblpage(PROG_ADDR), W0
W0, TBLPAG
#tbloffset(PROG_ADDR), W0
;
; Initialize PM Page Boundary SFR
; Initialize in-page EA[15:0] pointer
; Set base address of erase block
; Block all interrupts with priority <7
; for next 5 instructions
TBLWTL W0, [W0]
DISI
#5
MOV
MOV
MOV
MOV
BSET
NOP
NOP
#0x55, W0
W0, NVMKEY
#0xAA, W1
W1, NVMKEY
NVMCON, #WR
; Write the 55 key
;
; Write the AA key
; Start the erase sequence
; Insert two NOPs after the erase
; command is asserted
© 2007 Microchip Technology Inc.
Preliminary
DS70289A-page 45
PIC24HJ32GP202/204 and PIC24HJ16GP304
EXAMPLE 4-2:
LOADING THE WRITE BUFFERS
; Set up NVMCON for row programming operations
MOV
MOV
#0x4001, W0
W0, NVMCON
;
; Initialize NVMCON
; Set up a pointer to the first program memory location to be written
; program memory selected, and writes enabled
MOV
MOV
MOV
#0x0000, W0
W0, TBLPAG
#0x6000, W0
;
; Initialize PM Page Boundary SFR
; An example program memory address
; Perform the TBLWT instructions to write the latches
; 0th_program_word
MOV
MOV
#LOW_WORD_0, W2
#HIGH_BYTE_0, W3
;
;
TBLWTL W2, [W0]
TBLWTH W3, [W0++]
; Write PM low word into program latch
; Write PM high byte into program latch
; 1st_program_word
MOV
MOV
#LOW_WORD_1, W2
#HIGH_BYTE_1, W3
;
;
TBLWTL W2, [W0]
TBLWTH W3, [W0++]
; Write PM low word into program latch
; Write PM high byte into program latch
;
2nd_program_word
MOV
MOV
#LOW_WORD_2, W2
#HIGH_BYTE_2, W3
;
;
TBLWTL W2, [W0]
TBLWTH W3, [W0++]
; Write PM low word into program latch
; Write PM high byte into program latch
•
•
•
; 63rd_program_word
MOV
MOV
#LOW_WORD_31, W2
#HIGH_BYTE_31, W3
;
;
TBLWTL W2, [W0]
TBLWTH W3, [W0++]
; Write PM low word into program latch
; Write PM high byte into program latch
EXAMPLE 4-3:
INITIATING A PROGRAMMING SEQUENCE
DISI
#5
; Block all interrupts with priority <7
; for next 5 instructions
MOV
MOV
MOV
MOV
BSET
NOP
NOP
#0x55, W0
W0, NVMKEY
#0xAA, W1
W1, NVMKEY
NVMCON, #WR
; Write the 55 key
;
; Write the AA key
; Start the erase sequence
; Insert two NOPs after the
; erase command is asserted
DS70289A-page 46
Preliminary
© 2007 Microchip Technology Inc.
PIC24HJ32GP202/204 and PIC24HJ16GP304
Any active source of Reset makes the SYSRST signal
5.0
RESETS
active. Many registers associated with the CPU and
peripherals are forced to a known Reset state. Most
registers are unaffected by a Reset; their status is
unknown on POR and unchanged by all other Resets.
Note:
This data sheet summarizes the features
of the PIC24HJ32GP202/204 and
PIC24HJ16GP304 devices. It is not
intended to be a comprehensive reference
source. To complement the information in
this data sheet, refer to the “PIC24H
Family Reference Manual”.
Note:
Refer to the specific peripheral or CPU
section of this manual for register Reset
states.
All types of device Reset will set a corresponding status
bit in the RCON register to indicate the type of Reset
(see Register 5-1). A POR will clear all bits, except for
the POR bit (RCON<0>), that are set. The user appli-
cation can set or clear any bit at any time during code
execution. The RCON bits only serve as status bits.
Setting a particular Reset status bit in software does
not cause a device Reset to occur.
The Reset module combines all Reset sources and
controls the device Master Reset Signal, SYSRST. The
following is a list of device Reset sources:
• POR: Power-on Reset
• BOR: Brown-out Reset
• MCLR: Master Clear Pin Reset
• SWR: RESETInstruction
• WDTO: Watchdog Timer Reset
• TRAPR: Trap Conflict Reset
The RCON register also has other bits associated with
the Watchdog Timer and device power-saving states.
The function of these bits is discussed in other sections
of this manual.
• IOPUWR: Illegal Opcode, Uninitialized W Regis-
ter Reset, and Security Reset
• CM: Configuration Mismatch Reset
Note:
The status bits in the RCON register
should be cleared after they are read so
that the next RCON register value after a
device Reset will be meaningful.
Figure 5-1 shows the simplified block diagram of the
Reset module.
FIGURE 5-1:
RESET SYSTEM BLOCK DIAGRAM
RESETInstruction
Glitch Filter
MCLR
WDT
Module
Sleep or Idle
BOR
Internal
Regulator
SYSRST
VDD
POR
VDD Rise
Detect
Trap Conflict
Illegal Opcode
Uninitialized W Register
Configuration Mismatch
© 2007 Microchip Technology Inc.
Preliminary
DS70289A-page 47
PIC24HJ32GP202/204 and PIC24HJ16GP304
REGISTER 5-1:
RCON: RESET CONTROL REGISTER(1)
R/W-0
TRAPR
bit 15
R/W-0
U-0
—
U-0
—
U-0
—
U-0
—
R/W-0
CM
R/W-0
IOPUWR
VREGS
bit 8
R/W-0
EXTR
R/W-0
SWR
R/W-0
SWDTEN(2)
R/W-0
WDTO
R/W-0
R/W-0
IDLE
R/W-1
BOR
R/W-1
POR
SLEEP
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
-n = Value at POR
bit 15
bit 14
TRAPR: Trap Reset Flag bit
1= A Trap Conflict Reset has occurred
0= A Trap Conflict Reset has not occurred
IOPUWR: Illegal Opcode or Uninitialized W Access Reset Flag bit
1= An illegal opcode detection, an illegal address mode or uninitialized W register used as an
Address Pointer caused a Reset
0= An illegal opcode or uninitialized W Reset has not occurred
bit 13-10
bit 9
Unimplemented: Read as ‘0’
CM: Configuration Mismatch Flag bit
1 = A configuration mismatch Reset has occurred.
0 = A configuration mismatch Reset has NOT occurred.
bit 8
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
VREGS: Voltage Regulator Standby During Sleep bit
1= Voltage regulator is active during Sleep
0= Voltage regulator goes into Standby mode during Sleep
EXTR: External Reset (MCLR) Pin bit
1= A Master Clear (pin) Reset has occurred
0= A Master Clear (pin) Reset has not occurred
SWR: Software Reset (Instruction) Flag bit
1= A RESETinstruction has been executed
0= A RESETinstruction has not been executed
SWDTEN: Software Enable/Disable of WDT bit(2)
1= WDT is enabled
0= WDT is disabled
WDTO: Watchdog Timer Time-out Flag bit
1= WDT time-out has occurred
0= WDT time-out has not occurred
SLEEP: Wake-up from Sleep Flag bit
1= Device has been in Sleep mode
0= Device has not been in Sleep mode
IDLE: Wake-up from Idle Flag bit
1= Device was in Idle mode
0= Device was not in Idle mode
Note 1: All of the Reset status bits can be set or cleared in software. Setting one of these bits in software does not
cause a device Reset.
2: If the FWDTEN Configuration bit is ‘1’ (unprogrammed), the WDT is always enabled, regardless of the
SWDTEN bit setting.
DS70289A-page 48
Preliminary
© 2007 Microchip Technology Inc.
PIC24HJ32GP202/204 and PIC24HJ16GP304
REGISTER 5-1:
RCON: RESET CONTROL REGISTER(1)
bit 1
BOR: Brown-out Reset Flag bit
1= A Brown-out Reset has occurred
0= A Brown-out Reset has not occurred
bit 0
POR: Power-on Reset Flag bit
1= A Power-up Reset has occurred
0= A Power-up Reset has not occurred
Note 1: All of the Reset status bits can be set or cleared in software. Setting one of these bits in software does not
cause a device Reset.
2: If the FWDTEN Configuration bit is ‘1’ (unprogrammed), the WDT is always enabled, regardless of the
SWDTEN bit setting.
TABLE 5-1:
RESET FLAG BIT OPERATION
Flag Bit Setting Event
Trap conflict event
Clearing Event
TRAPR (RCON<15>)
IOPUWR (RCON<14>)
POR, BOR
POR, BOR
Illegal opcode or uninitialized
W register access
CM (RCON<9>)
Configuration mismatch
MCLR Reset
POR, BOR
POR
EXTR (RCON<7>)
SWR (RCON<6>)
WDTO (RCON<4>)
RESETinstruction
WDT time-out
POR, BOR
PWRSAVinstruction, POR, BOR,
CLRWDTinstruction
SLEEP (RCON<3>)
IDLE (RCON<2>)
BOR (RCON<1>)
POR (RCON<0>)
PWRSAV #SLEEPinstruction
POR, BOR
PWRSAV #IDLEinstruction
POR, BOR
BOR
POR
—
—
Note: All Reset flag bits may be set or cleared by the user software.
© 2007 Microchip Technology Inc.
Preliminary
DS70289A-page 49
PIC24HJ32GP202/204 and PIC24HJ16GP304
5.1
Clock Source Selection at Reset
5.2
Device Reset Times
If clock switching is enabled, the system clock source at
device Reset is chosen as shown in Table 5-2. If clock
switching is disabled, the system clock source is always
selected according to the oscillator Configuration bits.
Refer to Section 7.0 “Oscillator Configuration” for
further details.
The Reset times for various types of device Reset are
summarized in Table 5-3. The system Reset signal,
SYSRST, is released after the POR and PWRT delay
times expire.
The time at which the device actually begins to execute
code also depends on the system oscillator delays,
which include the Oscillator Start-up Timer (OST) and
the PLL lock time. The OST and PLL lock times occur
in parallel with the applicable SYSRST delay times.
TABLE 5-2:
OSCILLATOR SELECTION vs.
TYPE OF RESET (CLOCK
SWITCHING ENABLED)
The FSCM delay determines the time at which the
FSCM begins to monitor the system clock source after
the SYSRST signal is released.
Reset Type
Clock Source Determinant
POR
BOR
Oscillator Configuration bits
(FNOSC<2:0>)
COSC Control bits
(OSCCON<14:12>)
MCLR
WDTR
SWR
TABLE 5-3:
Reset Type
POR
RESET DELAY TIMES FOR VARIOUS DEVICE RESETS
System Clock
Delay
FSCM
Delay
Clock Source
SYSRST Delay
Notes
1, 2, 3
EC, FRC, LPRC
ECPLL, FRCPLL
XT, HS, SOSC
XTPLL, HSPLL
EC, FRC, LPRC
ECPLL, FRCPLL
XT, HS, SOSC
XTPLL, HSPLL
Any Clock
TPOR + TSTARTUP + TRST
TPOR + TSTARTUP + TRST
TPOR + TSTARTUP + TRST
TPOR + TSTARTUP + TRST
TSTARTUP + TRST
TSTARTUP + TRST
TSTARTUP + TRST
TSTARTUP + TRST
TRST
—
—
TFSCM
TFSCM
TFSCM
—
TLOCK
1, 2, 3, 5, 6
TOST
1, 2, 3, 4, 6
TOST + TLOCK
1, 2, 3, 4, 5, 6
BOR
—
3
TLOCK
TFSCM
TFSCM
TFSCM
—
3, 5, 6
TOST
3, 4, 6
TOST + TLOCK
3, 4, 5, 6
MCLR
—
—
—
—
—
—
3
3
3
3
3
3
WDT
Any Clock
TRST
—
Software
Any Clock
TRST
—
Illegal Opcode
Uninitialized W
Trap Conflict
Any Clock
TRST
—
Any Clock
TRST
—
Any Clock
TRST
—
Note 1: TPOR = Power-on Reset delay (10 μs nominal).
2: TSTARTUP = Conditional POR delay of 20 μs nominal (if on-chip regulator is enabled) or 64 ms nominal
Power-up Timer delay (if regulator is disabled). TSTARTUP is also applied to all returns from powered-down
states, including waking from Sleep mode, only if the regulator is enabled.
3: TRST = Internal state Reset time (20 μs nominal).
4: TOST = Oscillator Start-up Timer. A 10-bit counter counts 1024 oscillator periods before releasing the
oscillator clock to the system.
5: TLOCK = PLL lock time (20 μs nominal).
6: TFSCM = Fail-Safe Clock Monitor delay (100 μs nominal).
DS70289A-page 50
Preliminary
© 2007 Microchip Technology Inc.
PIC24HJ32GP202/204 and PIC24HJ16GP304
5.2.1
POR AND LONG OSCILLATOR
START-UP TIMES
5.2.2.1
FSCM Delay for Crystal and PLL
Clock Sources
The oscillator start-up circuitry and its associated delay
timers are not linked to the device Reset delays that
occur at power-up. Some crystal circuits (especially
low-frequency crystals) have a relatively long start-up
time. Therefore, one or more of the following conditions
is possible after SYSRST is released.
When the system clock source is provided by a crystal
oscillator and/or the PLL, a short delay, TFSCM, is auto-
matically inserted after the POR and PWRT delay
times. The FSCM does not start to monitor the system
clock source until this delay expires. The FSCM delay
time is nominally 500 μs and provides additional time
for the oscillator and/or PLL to stabilize. In most cases,
the FSCM delay prevents an oscillator failure trap at a
device Reset when the PWRT is disabled.
• The oscillator circuit has not begun to oscillate.
• The Oscillator Start-up Timer has not expired (if a
crystal oscillator is used).
• The PLL has not achieved a lock (if PLL is used).
5.3
Special Function Register Reset
States
The device will not begin to execute code until a valid
clock source has been released to the system. There-
fore, the oscillator and the PLL start-up delays must be
considered when the Reset delay time must be known.
Most of the Special Function Registers (SFRs) associ-
ated with the CPU and peripherals are reset to a
particular value at a device Reset. The SFRs are
grouped by their peripheral or CPU function, and their
Reset values are specified in each section of this man-
ual. The Reset value for each SFR does not depend on
the type of Reset, with the exception of two registers:
5.2.2
FAIL-SAFE CLOCK MONITOR
(FSCM) AND DEVICE RESETS
If the FSCM is enabled, it begins to monitor the system
clock source when SYSRST is released. If a valid clock
source is not available, the device automatically
switches to the FRC oscillator and the user application
can switch to the desired crystal oscillator in the Trap
Service Routine.
• The Reset value for the Reset Control register,
RCON, depends on the type of device Reset.
• The Reset value for the Oscillator Control regis-
ter, OSCCON, depends on the type of Reset and
the programmed values of the Oscillator Configu-
ration bits in the FOSC Configuration register.
© 2007 Microchip Technology Inc.
Preliminary
DS70289A-page 51
PIC24HJ32GP202/204 and PIC24HJ16GP304
NOTES:
DS70289A-page 52
Preliminary
© 2007 Microchip Technology Inc.
PIC24HJ32GP202/204 and PIC24HJ16GP304
6.1.1
ALTERNATE INTERRUPT VECTOR
TABLE
6.0
INTERRUPT CONTROLLER
Note:
This data sheet summarizes the features
of the PIC24HJ32GP202/204 and
PIC24HJ16GP304 devices. It is not
intended to be a comprehensive reference
source. To complement the information in
this data sheet, refer to the “PIC24H
Family Reference Manual”.
The Alternate Interrupt Vector Table (AIVT) is located
after the IVT, as shown in Figure 6-1. Access to the
AIVT is provided by the ALTIVT control bit
(INTCON2<15>). If the ALTIVT bit is set, all interrupt
and exception processes use the alternate vectors
instead of the default vectors. The alternate vectors are
organized in the same manner as the default vectors.
The PIC24HJ32GP202/204 and PIC24HJ16GP304
interrupt controllers reduce the numerous peripheral
interrupt request signals to a single interrupt request
The AIVT supports debugging by providing a means to
switch between an application and
a
support
environment without requiring the interrupt vectors to
be reprogrammed. This feature also enables switching
between applications for evaluation of different
software algorithms at run time. If the AIVT is not
needed, the AIVT should be programmed with the
same addresses used in the IVT.
signal
to
the
PIC24HJ32GP202/204
and
PIC24HJ16GP304 CPU.
It has the following features:
• Up to 8 processor exceptions and software traps
• 7 user-selectable priority levels
• Interrupt Vector Table (IVT) with up to 118 vectors
6.2
Reset Sequence
• A unique vector for each interrupt or exception
source
A device Reset is not a true exception because the
interrupt controller is not involved in the Reset process.
The PIC24HJ32GP202/204 and PIC24HJ16GP304
device clear its registers in response to a Reset, which
forces the PC to zero. The microcontroller then begins
the program execution at location 0x000000. The user
application can use a GOTO instruction at the Reset
address which redirects program execution to the
appropriate start-up routine.
• Fixed priority within a specified user priority level
• Alternate Interrupt Vector Table (AIVT) for debug
support
• Fixed interrupt entry and return latencies
6.1
Interrupt Vector Table
Figure 6-1 shows the Interrrupt Vector Table. The IVT
resides in program memory, starting at location
000004h. The IVT contains 126 vectors consisting of
8 nonmaskable trap vectors and up to 118 sources of
interrupt. In general, each interrupt source has its own
vector. Each interrupt vector contains a 24-bit wide
address. The value programmed into each interrupt
vector location is the starting address of the associated
Interrupt Service Routine (ISR).
Note: Any unimplemented or unused vector
locations in the IVT and AIVT should be
programmed with the address of a default
interrupt handler routine that contains a
RESETinstruction.
Interrupt vectors are prioritized in terms of their natural
priority; this priority is linked to their position in the
vector table. Lower addresses generally have a higher
natural priority. For example, the interrupt associated
with vector 0 will take priority over interrupts at any
other vector address.
PIC24HJ32GP202/204 and PIC24HJ16GP304 devices
implement up to 21 unique interrupts and 4 non-
maskable traps. These are summarized in Table 6-1
and Table 6-2.
© 2007 Microchip Technology Inc.
Preliminary
DS70289A-page 53
PIC24HJ32GP202/204 and PIC24HJ16GP304
FIGURE 6-1:
PIC24HJ32GP202/204 AND PIC24HJ16GP304 INTERRUPT VECTOR TABLE
Reset – GOTOInstruction
Reset – GOTOAddress
Reserved
0x000000
0x000002
0x000004
Oscillator Fail Trap Vector
Address Error Trap Vector
Stack Error Trap Vector
Math Error Trap Vector
Reserved
Reserved
Reserved
Interrupt Vector 0
Interrupt Vector 1
~
0x000014
~
~
Interrupt Vector 52
Interrupt Vector 53
Interrupt Vector 54
~
0x00007C
0x00007E
0x000080
(1)
Interrupt Vector Table (IVT)
~
~
Interrupt Vector 116
Interrupt Vector 117
Reserved
0x0000FC
0x0000FE
0x000100
0x000102
Reserved
Reserved
Oscillator Fail Trap Vector
Address Error Trap Vector
Stack Error Trap Vector
Math Error Trap Vector
Reserved
Reserved
Reserved
Interrupt Vector 0
Interrupt Vector 1
~
0x000114
~
~
(1)
Alternate Interrupt Vector Table (AIVT)
Interrupt Vector 52
Interrupt Vector 53
Interrupt Vector 54
~
0x00017C
0x00017E
0x000180
~
~
Interrupt Vector 116
Interrupt Vector 117
Start of Code
0x0001FE
0x000200
Note 1: See Table 6-1 for the list of implemented interrupt vectors.
DS70289A-page 54
Preliminary
© 2007 Microchip Technology Inc.
PIC24HJ32GP202/204 and PIC24HJ16GP304
TABLE 6-1:
INTERRUPT VECTORS
Interrupt
Vector
Number
Request(IRQ)
Number
IVT Address
AIVT Address
Interrupt Source
INT0 – External Interrupt 0
8
0
0x000014
0x000016
0x000018
0x00001A
0x00001C
0x00001E
0x000020
0x000022
0x000024
0x000026
0x000028
0x00002A
0x00002C
0x00002E
0x000030
0x000032
0x000034
0x000036
0x000038
0x00003A
0x00003C
0x00003E
0x000040
0x000042
0x000044
0x000046
0x000048
0x00004A
0x00004C
0x00004E
0x000050
0x000052
0x000054
0x000056
0x000058
0x00005A
0x00005C
0x00005E
0x000060
0x000062
0x000064
0x000066
0x000068
0x00006A
0x00006C
0x00006E
0x000114
0x000116
0x000118
0x00011A
0x00011C
0x00011E
0x000120
0x000122
0x000124
0x000126
0x000128
0x00012A
0x00012C
0x00012E
0x000130
0x000132
0x000134
0x000136
0x000138
0x00013A
0x00013C
0x00013E
0x000140
0x000142
0x000144
0x000146
0x000148
0x00014A
0x00014C
0x00014E
0x000150
0x000152
0x000154
0x000156
0x000158
0x00015A
0x00015C
0x00015E
0x000160
0x000162
0x000164
0x000166
0x000168
0x00016A
0x00016C
0x00016E
9
1
IC1 – Input Compare 1
OC1 – Output Compare 1
T1 – Timer1
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
2
3
4
Reserved
5
IC2 – Input Capture 2
OC2 – Output Compare 2
T2 – Timer2
6
7
8
T3 – Timer3
9
SPI1E – SPI1 Error
SPI1 – SPI1 Transfer Done
U1RX – UART1 Receiver
U1TX – UART1 Transmitter
ADC1 – ADC 1
Reserved
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
Reserved
SI2C1 – I2C1 Slave Events
MI2C1 – I2C1 Master Events
Reserved
Change Notification Interrupt
INT1 – External Interrupt 1
Reserved
IC7 – Input Capture 7
IC8 – Input Capture 8
Reserved
Reserved
Reserved
Reserved
Reserved
INT2 – External Interrupt 2
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
© 2007 Microchip Technology Inc.
Preliminary
DS70289A-page 55
PIC24HJ32GP202/204 and PIC24HJ16GP304
TABLE 6-1:
INTERRUPT VECTORS (CONTINUED)
Interrupt
Vector
Number
Request(IRQ)
Number
IVT Address
AIVT Address
Interrupt Source
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72-117
0x000070
0x000072
0x000074
0x000076
0x000078
0x00007A
0x00007C
0x00007E
0x000080
0x000082
0x000084
0x000086
0x000088
0x00008A
0x00008C
0x00008E
0x000090
0x000092
0x000094
0x000096
0x000098
0x00009A
0x00009C
0x00009E
0x0000A0
0x0000A2
0x000170
0x000172
0x000174
0x000176
0x000178
0x00017A
0x00017C
0x00017E
0x000180
0x000182
0x000184
0x000186
0x000188
0x00018A
0x00018C
0x00018E
0x000190
0x000192
0x000194
0x000196
0x000198
0x00019A
0x00019C
0x00019E
0x0001A0
0x0001A2
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
U1E – UART1 Error
Reserved
74
75
76
77
78
Reserved
Reserved
Reserved
Reserved
79
Reserved
80-125
0x0000A4-
0x0000FE
0x0001A4-
0x0001FE
Reserved
TABLE 6-2:
TRAP VECTORS
Vector Number
IVT Address
AIVT Address
Trap Source
Reserved
0
1
2
3
4
5
6
7
0x000004
0x000006
0x000008
0x00000A
0x00000C
0x00000E
0x000010
0x000012
0x000104
0x000106
0x000108
0x00010A
0x00010C
0x00010E
0x000110
0x000112
Oscillator Failure
Address Error
Stack Error
Math Error
Reserved
Reserved
Reserved
DS70289A-page 56
Preliminary
© 2007 Microchip Technology Inc.
PIC24HJ32GP202/204 and PIC24HJ16GP304
6.3.4
IPCx
6.3
Interrupt Control and Status
Registers
The IPC registers are used to set the interrupt priority
level for each source of interrupt. Each user interrupt
source can be assigned to one of the eight priority lev-
els.
PIC24HJ32GP202/204
devices implement a total of 17 registers for the inter-
rupt controller:
and
PIC24HJ16GP304
• Interrupt Control Register 1 (INTCON1)
• Interrupt Control Register 2 (INTCON2)
• Interrupt Flag Status Registers (IFSx)
• Interrupt Enable Control Registers (IECx)
• Interrupt Priority Control Registers (IPCx)
• Interrupt Control and Status Register (INTTREG)
6.3.5
INTTREG
The INTTREG register contains the associated
interrupt vector number and the new CPU interrupt
priority level, which are latched into vector number
(VECNUM<6:0>) and Interrupt level (ILR<3:0>) bit
fields in the INTTREG register. The new interrupt
priority level is the priority of the pending interrupt.
6.3.1
INTCON1 AND INTCON2
The interrupt sources are assigned to the IFSx, IECx
and IPCx registers in the same sequence that they are
listed in Table 6-1. For example, the INT0 (External
Interrupt 0) is shown as having vector number 8 and a
natural order priority of 0. Thus, the INT0IF bit is found
in IFS0<0>, the INT0IE bit in IEC0<0>, and the INT0IP
bits in the first position of IPC0 (IPC0<2:0>).
Global interrupt control functions are controlled from
INTCON1 and INTCON2. INTCON1 contains the
Interrupt Nesting Disable (NSTDIS) bit as well as the
control and status flags for the processor trap sources.
The INTCON2 register controls the external interrupt
request signal behavior and the use of the Alternate
Interrupt Vector Table.
6.3.6
STATUS REGISTERS
6.3.2
IFSx
Although these are not specifically part of the interrupt
control hardware, two of the CPU Control registers
contain bits that control interrupt functionality:
The IFS registers maintain all the interrupt request
flags. Each source of interrupt has a status bit, which is
set by the respective peripherals or external signal and
this is cleared via software.
• The CPU STATUS register, SR, contains the
IPL<2:0> bits (SR<7:5>). These bits indicate the
current CPU interrupt priority level. The user can
change the current CPU priority level by writing to
the IPL bits.
6.3.3
IECx
The IEC registers maintain all the interrupt enable bits.
These control bits are used individually to enable inter-
rupts from the peripherals or external signals.
• The CORCON register contains the IPL3 bit
which, together with IPL<2:0>, also indicates the
current CPU priority level. IPL3 is a read-only bit,
so that trap events cannot be masked by the user
software.
All Interrupt registers are described in Register 6-1
through Register 6-19 in the following pages.
© 2007 Microchip Technology Inc.
Preliminary
DS70289A-page 57
PIC24HJ32GP202/204 and PIC24HJ16GP304
REGISTER 6-1:
SR: CPU STATUS REGISTER(1)
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
R/W-0
DC
bit 15
bit 8
R/W-0(3)
IPL2(2)
bit 7
R/W-0(3)
IPL1(2)
R/W-0(3)
IPL0(2)
R-0
RA
R/W-0
N
R/W-0
OV
R/W-0
Z
R/W-0
C
bit 0
Legend:
C = Clear only bit
S = Set only bit
‘1’ = Bit is set
R = Readable bit
W = Writable bit
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
-n = Value at POR
x = Bit is unknown
bit 7-5
IPL<2:0>: CPU Interrupt Priority Level Status bits(1)
111= CPU Interrupt Priority Level is 7 (15), user interrupts disabled
110= CPU Interrupt Priority Level is 6 (14)
101= CPU Interrupt Priority Level is 5 (13)
100= CPU Interrupt Priority Level is 4 (12)
011= CPU Interrupt Priority Level is 3 (11)
010= CPU Interrupt Priority Level is 2 (10)
001= CPU Interrupt Priority Level is 1 (9)
000= CPU Interrupt Priority Level is 0 (8)
Note 1: For complete register details, see Register 2-1: “SR: CPU STATUS Register”.
2: The IPL<2:0> bits are concatenated with the IPL<3> bit (CORCON<3>) to form the CPU Interrupt Priority
Level. The value in parentheses indicates the IPL if IPL<3> = 1. User interrupts are disabled when
IPL<3> = 1.
3: The IPL<2:0> Status bits are read-only when NSTDIS (INTCON1<15>) = 1.
DS70289A-page 58
Preliminary
© 2007 Microchip Technology Inc.
PIC24HJ32GP202/204 and PIC24HJ16GP304
REGISTER 6-2:
CORCON: CORE CONTROL REGISTER(1)
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
bit 15
bit 8
bit 0
U-0
—
U-0
—
U-0
—
U-0
—
R/C-0
IPL3(2)
R/W-0
PSV
U-0
—
U-0
—
bit 7
Legend:
C = Clear only bit
W = Writable bit
‘x = Bit is unknown
R = Readable bit
0’ = Bit is cleared
-n = Value at POR
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
bit 3
IPL3: CPU Interrupt Priority Level Status bit 3(2)
1= CPU interrupt priority level is greater than 7
0= CPU interrupt priority level is 7 or less
Note 1: For complete register details, see Register 2-2: “CORCON: CORE Control Register”.
2: The IPL3 bit is concatenated with the IPL<2:0> bits (SR<7:5>) to form the CPU Interrupt Priority Level.
© 2007 Microchip Technology Inc.
Preliminary
DS70289A-page 59
PIC24HJ32GP202/204 and PIC24HJ16GP304
REGISTER 6-3:
INTCON1: INTERRUPT CONTROL REGISTER 1
R/W-0
NSTDIS
bit 15
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
bit 8
bit 0
U-0
—
R/W-0
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
U-0
—
DIV0ERR
MATHERR ADDRERR
STKERR
OSCFAIL
bit 7
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
-n = Value at POR
bit 15
NSTDIS: Interrupt Nesting Disable bit
1= Interrupt nesting is disabled
0= Interrupt nesting is enabled
bit 14-7
bit 6
Unimplemented: Read as ‘0’.
DIV0ERR: Arithmetic Error Status bit
1= Math error trap was caused by a divide by zero
0= Math error trap was not caused by a divide by zero
bit 5
bit 4
Unimplemented: Read as ‘0’
MATHERR: Arithmetic Error Status bit
1= Math error trap has occurred
0= Math error trap has not occurred
bit 3
bit 2
bit 1
bit 0
ADDRERR: Address Error Trap Status bit
1= Address error trap has occurred
0= Address error trap has not occurred
STKERR: Stack Error Trap Status bit
1= Stack error trap has occurred
0= Stack error trap has not occurred
OSCFAIL: Oscillator Failure Trap Status bit
1= Oscillator failure trap has occurred
0= Oscillator failure trap has not occurred
Unimplemented: Read as ‘0’
DS70289A-page 60
Preliminary
© 2007 Microchip Technology Inc.
PIC24HJ32GP202/204 and PIC24HJ16GP304
REGISTER 6-4:
INTCON2: INTERRUPT CONTROL REGISTER 2
R/W-0
R-0
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
ALTIVT
DISI
bit 15
bit 8
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
R/W-0
R/W-0
R/W-0
INT2EP
INT1EP
INT0EP
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15
bit 14
ALTIVT: Enable Alternate Interrupt Vector Table bit
1= Use alternate vector table
0= Use standard (default) vector table
DISI: DISIInstruction Status bit
1= DISIinstruction is active
0= DISIinstruction is not active
bit 13-3
bit 2
Unimplemented: Read as ‘0’
INT2EP: External Interrupt 2 Edge Detect Polarity Select bit
1= Interrupt on negative edge
0= Interrupt on positive edge
bit 1
bit 0
INT1EP: External Interrupt 1 Edge Detect Polarity Select bit
1= Interrupt on negative edge
0= Interrupt on positive edge
INT0EP: External Interrupt 0 Edge Detect Polarity Select bit
1= Interrupt on negative edge
0= Interrupt on positive edge
© 2007 Microchip Technology Inc.
Preliminary
DS70289A-page 61
PIC24HJ32GP202/204 and PIC24HJ16GP304
REGISTER 6-5:
IFS0: INTERRUPT FLAG STATUS REGISTER 0
U-0
—
U-0
—
R/W-0
AD1IF
R/W-0
R/W-0
R/W-0
SPI1IF
R/W-0
R/W-0
T3IF
U1TXIF
U1RXIF
SPI1EIF
bit 15
bit 8
R/W-0
T2IF
R/W-0
OC2IF
R/W-0
IC2IF
U-0
—
R/W-0
T1IF
R/W-0
OC1IF
R/W-0
IC1IF
R/W-0
INT0IF
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-4
bit 13
Unimplemented: Read as ‘0’
AD1IF: ADC1 Conversion Complete Interrupt Flag Status bit
1= Interrupt request has occurred
0= Interrupt request has not occurred
bit 12
bit 11
bit 10
bit 9
U1TXIF: UART1 Transmitter Interrupt Flag Status bit
1= Interrupt request has occurred
0= Interrupt request has not occurred
U1RXIF: UART1 Receiver Interrupt Flag Status bit
1= Interrupt request has occurred
0= Interrupt request has not occurred
SPI1IF: SPI1 Event Interrupt Flag Status bit
1= Interrupt request has occurred
0= Interrupt request has not occurred
SPI1EIF: SPI1 Fault Interrupt Flag Status bit
1= Interrupt request has occurred
0= Interrupt request has not occurred
bit 8
T3IF: Timer3 Interrupt Flag Status bit
1= Interrupt request has occurred
0= Interrupt request has not occurred
bit 7
T2IF: Timer2 Interrupt Flag Status bit
1= Interrupt request has occurred
0= Interrupt request has not occurred
bit 6
OC2IF: Output Compare Channel 2 Interrupt Flag Status bit
1= Interrupt request has occurred
0= Interrupt request has not occurred
bit 5
IC2IF: Input Capture Channel 2 Interrupt Flag Status bit
1= Interrupt request has occurred
0= Interrupt request has not occurred
bit 4
bit 3
Unimplemented: Read as ‘0’
T1IF: Timer1 Interrupt Flag Status bit
1= Interrupt request has occurred
0= Interrupt request has not occurred
bit 2
OC1IF: Output Compare Channel 1 Interrupt Flag Status bit
1= Interrupt request has occurred
0= Interrupt request has not occurred
DS70289A-page 62
Preliminary
© 2007 Microchip Technology Inc.
PIC24HJ32GP202/204 and PIC24HJ16GP304
REGISTER 6-5:
IFS0: INTERRUPT FLAG STATUS REGISTER 0 (CONTINUED)
bit 1
IC1IF: Input Capture Channel 1 Interrupt Flag Status bit
1= Interrupt request has occurred
0= Interrupt request has not occurred
bit 0
INT0IF: External Interrupt 0 Flag Status bit
1= Interrupt request has occurred
0= Interrupt request has not occurred
© 2007 Microchip Technology Inc.
Preliminary
DS70289A-page 63
PIC24HJ32GP202/204 and PIC24HJ16GP304
REGISTER 6-6:
IFS1: INTERRUPT FLAG STATUS REGISTER 1
U-0
—
U-0
—
R/W-0
INT2IF
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
bit 15
bit 8
R/W-0
IC8IF
R/W-0
IC7IF
U-0
—
R/W-0
INT1IF
R/W-0
CNIF
U-0
—
R/W-0
R/W-0
MI2C1IF
SI2C1IF
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-4
bit 13
Unimplemented: Read as ‘0’
INT2IF: External Interrupt 2 Flag Status bit
1= Interrupt request has occurred
0= Interrupt request has not occurred
bit 12-8
bit 7
Unimplemented: Read as ‘0’
IC8IF: Input Capture Channel 8 Interrupt Flag Status bit
1= Interrupt request has occurred
0= Interrupt request has not occurred
bit 6
IC7IF: Input Capture Channel 7 Interrupt Flag Status bit
1= Interrupt request has occurred
0= Interrupt request has not occurred
bit 5
bit 4
Unimplemented: Read as ‘0’
INT1IF: External Interrupt 1 Flag Status bit
1= Interrupt request has occurred
0= Interrupt request has not occurred
bit 3
CNIF: Input Change Notification Interrupt Flag Status bit
1= Interrupt request has occurred
0= Interrupt request has not occurred
bit 2
bit 1
Unimplemented: Read as ‘0’
MI2C1IF: I2C1 Master Events Interrupt Flag Status bit
1= Interrupt request has occurred
0= Interrupt request has not occurred
bit 0
SI2C1IF: I2C1 Slave Events Interrupt Flag Status bit
1= Interrupt request has occurred
0= Interrupt request has not occurred
DS70289A-page 64
Preliminary
© 2007 Microchip Technology Inc.
PIC24HJ32GP202/204 and PIC24HJ16GP304
REGISTER 6-7:
IFS4: INTERRUPT FLAG STATUS REGISTER 4
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
bit 15
bit 8
bit 0
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
U-0
—
U1EIF
bit 7
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-2
bit 1
Unimplemented: Read as ‘0’
U1EIF: UART1 Error Interrupt Flag Status bit
1= Interrupt request has occurred
0= Interrupt request has not occurred
bit 0
Unimplemented: Read as ‘0’
© 2007 Microchip Technology Inc.
Preliminary
DS70289A-page 65
PIC24HJ32GP202/204 and PIC24HJ16GP304
REGISTER 6-8:
IEC0: INTERRUPT ENABLE CONTROL REGISTER 0
U-0
—
U-0
—
R/W-0
AD1IE
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
T3IE
U1TXIE
U1RXIE
SPI1IE
SPI1EIE
bit 15
bit 8
R/W-0
T2IE
R/W-0
OC2IE
R/W-0
IC2IE
U-0
—
R/W-0
T1IE
R/W-0
OC1IE
R/W-0
IC1IE
R/W-0
INT0IE
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-4
bit 13
Unimplemented: Read as ‘0’
AD1IE: ADC1 Conversion Complete Interrupt Enable bit
1= Interrupt request enabled
0= Interrupt request not enabled
bit 12
bit 11
bit 10
bit 9
U1TXIE: UART1 Transmitter Interrupt Enable bit
1= Interrupt request enabled
0= Interrupt request not enabled
U1RXIE: UART1 Receiver Interrupt Enable bit
1= Interrupt request enabled
0= Interrupt request not enabled
SPI1IE: SPI1 Event Interrupt Enable bit
1= Interrupt request enabled
0= Interrupt request not enabled
SPI1EIE: SPI1 Error Interrupt Enable bit
1= Interrupt request enabled
0= Interrupt request not enabled
bit 8
T3IE: Timer3 Interrupt Enable bit
1= Interrupt request enabled
0= Interrupt request not enabled
bit 7
T2IE: Timer2 Interrupt Enable bit
1= Interrupt request enabled
0= Interrupt request not enabled
bit 6
OC2IE: Output Compare Channel 2 Interrupt Enable bit
1= Interrupt request enabled
0= Interrupt request not enabled
bit 5
IC2IE: Input Capture Channel 2 Interrupt Enable bit
1= Interrupt request enabled
0= Interrupt request not enabled
bit 4
bit 3
Unimplemented: Read as ‘0’
T1IE: Timer1 Interrupt Enable bit
1= Interrupt request enabled
0= Interrupt request not enabled
bit 2
OC1IE: Output Compare Channel 1 Interrupt Enable bit
1= Interrupt request enabled
0= Interrupt request not enabled
DS70289A-page 66
Preliminary
© 2007 Microchip Technology Inc.
PIC24HJ32GP202/204 and PIC24HJ16GP304
REGISTER 6-8:
IEC0: INTERRUPT ENABLE CONTROL REGISTER 0 (CONTINUED)
bit 1
IC1IE: Input Capture Channel 1 Interrupt Enable bit
1= Interrupt request enabled
0= Interrupt request not enabled
bit 0
INT0IE: External Interrupt 0 Enable bit
1= Interrupt request enabled
0= Interrupt request not enabled
© 2007 Microchip Technology Inc.
Preliminary
DS70289A-page 67
PIC24HJ32GP202/204 and PIC24HJ16GP304
REGISTER 6-9:
IEC1: INTERRUPT ENABLE CONTROL REGISTER 0
U-0
—
U-0
—
R/W-0
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
INT2IE
bit 15
bit 8
R/W-0
IC8IE
R/W-0
IC7IE
U-0
—
R/W-0
R/W-0
CNIE
U-0
—
R/W-0
R/W-0
INT1IE
MI2C1IE
SI2C1IE
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-14
bit 13
Unimplemented: Read as ‘0’
INT2IE: External Interrupt 2 Enable bit
1= Interrupt request enabled
0= Interrupt request not enabled
bit 12-8
bit 7
Unimplemented: Read as ‘0’
IC8IE: Input Capture Channel 8 Interrupt Enable bit
1= Interrupt request enabled
0= Interrupt request not enabled
bit 6
IC7IE: Input Capture Channel 7 Interrupt Enable bit
1= Interrupt request enabled
0= Interrupt request not enabled
bit 5
bit 4
Unimplemented: Read as ‘0’
INT1IE: External Interrupt 1 Enable bit
1= Interrupt request enabled
0= Interrupt request not enabled
bit 3
CNIE: Input Change Notification Interrupt Enable bit
1= Interrupt request enabled
0= Interrupt request not enabled
bit 2
bit 1
Unimplemented: Read as ‘0’
MI2C1IE: I2C1 Master Events Interrupt Enable bit
1= Interrupt request enabled
0= Interrupt request not enabled
bit 0
SI2C1IE: I2C1 Slave Events Interrupt Enable bit
1= Interrupt request enabled
0= Interrupt request not enabled
DS70289A-page 68
Preliminary
© 2007 Microchip Technology Inc.
PIC24HJ32GP202/204 and PIC24HJ16GP304
REGISTER 6-10: IEC4: INTERRUPT ENABLE CONTROL REGISTER 0
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
bit 15
bit 8
bit 0
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
R/W-0
U1EIE
U-0
—
bit 7
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-2
bit 1
Unimplemented: Read as ‘0’
U1EIE: UART1 Error Interrupt Enable bit
1= Interrupt request enabled
0= Interrupt request not enabled
bit 0
Unimplemented: Read as ‘0’
© 2007 Microchip Technology Inc.
Preliminary
DS70289A-page 69
PIC24HJ32GP202/204 and PIC24HJ16GP304
REGISTER 6-11: IPC0: INTERRUPT PRIORITY CONTROL REGISTER 0
U-0
—
R/W-1
R/W-0
R/W-0
U-0
—
R/W-1
R/W-0
R/W-0
bit 8
R/W-0
T1IP<2:0>
OC1IP<2:0>
bit 15
U-0
—
R/W-1
R/W-0
R/W-0
U-0
—
R/W-1
R/W-0
IC1IP<2:0>
INT0IP<2:0>
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15
Unimplemented: Read as ‘0’
T1IP<2:0>: Timer1 Interrupt Priority bits
bit 14-12
111= Interrupt is priority 7 (highest priority interrupt)
•
•
•
001= Interrupt is priority 1
000= Interrupt source is disabled
bit 11
Unimplemented: Read as ‘0’
bit 10-8
OC1IP<2:0>: Output Compare Channel 1 Interrupt Priority bits
111= Interrupt is priority 7 (highest priority interrupt)
•
•
•
001= Interrupt is priority 1
000= Interrupt source is disabled
bit 7
Unimplemented: Read as ‘0’
bit 6-4
IC1IP<2:0>: Input Capture Channel 1 Interrupt Priority bits
111= Interrupt is priority 7 (highest priority interrupt)
•
•
•
001= Interrupt is priority 1
000= Interrupt source is disabled
bit 3
Unimplemented: Read as ‘0’
bit 2-0
INT0IP<2:0>: External Interrupt 0 Priority bits
111= Interrupt is priority 7 (highest priority interrupt)
•
•
•
001= Interrupt is priority 1
000= Interrupt source is disabled
DS70289A-page 70
Preliminary
© 2007 Microchip Technology Inc.
PIC24HJ32GP202/204 and PIC24HJ16GP304
REGISTER 6-12: IPC1: INTERRUPT PRIORITY CONTROL REGISTER 1
U-0
—
R/W-1
R/W-0
R/W-0
U-0
—
R/W-1
R/W-0
R/W-0
bit 8
T2IP<2:0>
OC2IP<2:0>
bit 15
U-0
—
R/W-1
R/W-0
R/W-0
U-0
—
U-0
—
U-0
—
U-0
—
IC2IP<2:0>
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15
Unimplemented: Read as ‘0’
T2IP<2:0>: Timer2 Interrupt Priority bits
bit 14-12
111= Interrupt is priority 7 (highest priority interrupt)
•
•
•
001= Interrupt is priority 1
000= Interrupt source is disabled
bit 11
Unimplemented: Read as ‘0’
bit 10-8
OC2IP<2:0>: Output Compare Channel 2 Interrupt Priority bits
111= Interrupt is priority 7 (highest priority interrupt)
•
•
•
001= Interrupt is priority 1
000= Interrupt source is disabled
bit 7
Unimplemented: Read as ‘0’
bit 6-4
IC2IP<2:0>: Input Capture Channel 2 Interrupt Priority bits
111= Interrupt is priority 7 (highest priority interrupt)
•
•
•
001= Interrupt is priority 1
000= Interrupt source is disabled
bit 3-0
Unimplemented: Read as ‘0’
© 2007 Microchip Technology Inc.
Preliminary
DS70289A-page 71
PIC24HJ32GP202/204 and PIC24HJ16GP304
REGISTER 6-13: IPC2: INTERRUPT PRIORITY CONTROL REGISTER 2
U-0
—
R/W-1
R/W-0
R/W-0
U-0
—
R/W-1
R/W-0
R/W-0
bit 8
R/W-0
U1RXIP<2:0>
SPI1IP<2:0>
bit 15
U-0
—
R/W-1
R/W-0
R/W-0
U-0
—
R/W-1
R/W-0
SPI1EIP<2:0>
T3IP<2:0>
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15
Unimplemented: Read as ‘0’
bit 14-12
U1RXIP<2:0>: UART1 Receiver Interrupt Priority bits
111= Interrupt is priority 7 (highest priority interrupt)
•
•
•
001= Interrupt is priority 1
000= Interrupt source is disabled
bit 11
Unimplemented: Read as ‘0’
bit 10-8
SPI1IP<2:0>: SPI1 Event Interrupt Priority bits
111= Interrupt is priority 7 (highest priority interrupt)
•
•
•
001= Interrupt is priority 1
000= Interrupt source is disabled
bit 7
Unimplemented: Read as ‘0’
bit 6-4
SPI1EIP<2:0>: SPI1 Error Interrupt Priority bits
111= Interrupt is priority 7 (highest priority interrupt)
•
•
•
001= Interrupt is priority 1
000= Interrupt source is disabled
bit 3
Unimplemented: Read as ‘0’
bit 2-0
T3IP<2:0>: Timer3 Interrupt Priority bits
111= Interrupt is priority 7 (highest priority interrupt)
•
•
•
001= Interrupt is priority 1
000= Interrupt source is disabled
DS70289A-page 72
Preliminary
© 2007 Microchip Technology Inc.
PIC24HJ32GP202/204 and PIC24HJ16GP304
REGISTER 6-14: IPC3: INTERRUPT PRIORITY CONTROL REGISTER 3
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
bit 15
bit 8
U-0
—
R/W-1
R/W-0
R/W-0
U-0
—
R/W-1
R/W-0
R/W-0
AD1IP<2:0>
U1TXIP<2:0>
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-7
bit 6-4
Unimplemented: Read as ‘0’
AD1IP<2:0>: ADC1 Conversion Complete Interrupt Priority bits
111= Interrupt is priority 7 (highest priority interrupt)
•
•
•
001= Interrupt is priority 1
000= Interrupt source is disabled
bit 3
Unimplemented: Read as ‘0’
bit 2-0
U1TXIP<2:0>: UART1 Transmitter Interrupt Priority bits
111= Interrupt is priority 7 (highest priority interrupt)
•
•
•
001= Interrupt is priority 1
000= Interrupt source is disabled
© 2007 Microchip Technology Inc.
Preliminary
DS70289A-page 73
PIC24HJ32GP202/204 and PIC24HJ16GP304
REGISTER 6-15: IPC4: INTERRUPT PRIORITY CONTROL REGISTER 4
U-0
—
R/W-1
R/W-0
R/W-0
U-0
—
U-0
—
U-0
—
U-0
—
CNIP<2:0>
bit 15
bit 8
U-0
—
R/W-1
R/W-0
R/W-0
U-0
—
R/W-1
R/W-0
R/W-0
MI2C1IP<2:0>
SI2C1IP<2:0>
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15
Unimplemented: Read as ‘0’
bit 14-12
CNIP<2:0>: Change Notification Interrupt Priority bits
111= Interrupt is priority 7 (highest priority interrupt)
•
•
•
001= Interrupt is priority 1
000= Interrupt source is disabled
bit 11-7
bit 6-4
Unimplemented: Read as ‘0’
MI2C1IP<2:0>: I2C1 Master Events Interrupt Priority bits
111= Interrupt is priority 7 (highest priority interrupt)
•
•
•
001= Interrupt is priority 1
000= Interrupt source is disabled
bit 3
Unimplemented: Read as ‘0’
bit 2-0
SI2C1IP<2:0>: I2C1 Slave Events Interrupt Priority bits
111= Interrupt is priority 7 (highest priority interrupt)
•
•
•
001= Interrupt is priority 1
000= Interrupt source is disabled
DS70289A-page 74
Preliminary
© 2007 Microchip Technology Inc.
PIC24HJ32GP202/204 and PIC24HJ16GP304
REGISTER 6-16: IPC5: INTERRUPT PRIORITY CONTROL REGISTER 5
U-0
—
R/W-1
R/W-0
R/W-0
U-0
—
R/W-1
R/W-0
R/W-0
bit 8
R/W-0
IC8IP<2:0>
IC7IP<2:0>
bit 15
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
R/W-1
R/W-0
INT1IP<2:0>
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15
Unimplemented: Read as ‘0’
bit 14-12
IC8IP<2:0>: Input Capture Channel 8 Interrupt Priority bits
111= Interrupt is priority 7 (highest priority interrupt)
•
•
•
001= Interrupt is priority 1
000= Interrupt source is disabled
bit 11
Unimplemented: Read as ‘0’
bit 10-8
IC7IP<2:0>: Input Capture Channel 7 Interrupt Priority bits
111= Interrupt is priority 7 (highest priority interrupt)
•
•
•
001= Interrupt is priority 1
000= Interrupt source is disabled
bit 7-3
bit 2-0
Unimplemented: Read as ‘0’
INT1IP<2:0>: External Interrupt 1 Priority bits
111= Interrupt is priority 7 (highest priority interrupt)
•
•
•
001= Interrupt is priority 1
000= Interrupt source is disabled
© 2007 Microchip Technology Inc.
Preliminary
DS70289A-page 75
PIC24HJ32GP202/204 and PIC24HJ16GP304
REGISTER 6-17: IPC7: INTERRUPT PRIORITY CONTROL REGISTER 7
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
bit 15
bit 8
bit 0
U-0
—
R/W-1
R/W-0
R/W-0
U-0
—
U-0
—
U-0
—
U-0
—
INT2IP<2:0>
bit 7
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-7
bit 6-4
Unimplemented: Read as ‘0’
INT2IP<2:0>: External Interrupt 2 Priority bits
111= Interrupt is priority 7 (highest priority interrupt)
•
•
•
001= Interrupt is priority 1
000= Interrupt source is disabled
bit 3-0
Unimplemented: Read as ‘0’
DS70289A-page 76
Preliminary
© 2007 Microchip Technology Inc.
PIC24HJ32GP202/204 and PIC24HJ16GP304
REGISTER 6-18: IPC16: INTERRUPT PRIORITY CONTROL REGISTER 16
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
bit 15
bit 8
bit 0
U-0
—
R/W-1
R/W-0
R/W-0
U-0
—
U-0
—
U-0
—
U-0
—
U1EIP<2:0>
bit 7
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-7
bit 6-4
Unimplemented: Read as ‘0’
U1EIP<2:0>: UART1 Error Interrupt Priority bits
111= Interrupt is priority 7 (highest priority interrupt)
•
•
•
001= Interrupt is priority 1
000= Interrupt source is disabled
bit 3-0
Unimplemented: Read as ‘0’
© 2007 Microchip Technology Inc.
Preliminary
DS70289A-page 77
PIC24HJ32GP202/204 and PIC24HJ16GP304
REGISTER 6-19: INTTREG: INTERRUPT CONTROL AND STATUS REGISTER
U-0
—
U-0
—
U-0
—
U-0
—
R-0
R-0
R-0
R-0
R-0
R-0
ILR<3:0>
bit 15
bit 8
bit 0
U-0
—
R-0
R-0
R-0
R-0
R-0
VECNUM<6:0>
bit 7
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-12
bit 11-8
Unimplemented: Read as ‘0’
ILR: New CPU Interrupt Priority Level bits
1111= CPU Interrupt Priority Level is 15
•
•
•
0001= CPU Interrupt Priority Level is 1
0000= CPU Interrupt Priority Level is 0
bit 7
Unimplemented: Read as ‘0’
bit 6-0
VECNUM: Vector Number of Pending Interrupt bits
0111111= Interrupt Vector pending is number 135
•
•
•
0000001= Interrupt Vector pending is number 9
0000000= Interrupt Vector pending is number 8
DS70289A-page 78
Preliminary
© 2007 Microchip Technology Inc.
PIC24HJ32GP202/204 and PIC24HJ16GP304
6.4.3
TRAP SERVICE ROUTINE
6.4
Interrupt Setup Procedures
A Trap Service Routine (TSR) is coded like an ISR,
except that the appropriate trap status flag in the
INTCON1 register must be cleared to avoid re-entry
into the TSR.
6.4.1
INITIALIZATION
To configure an interrupt source at initialization:
1. Set the NSTDIS bit (INTCON1<15>) if nested
interrupts are not desired.
6.4.4
INTERRUPT DISABLE
2. Select the user-assigned priority level for the
interrupt source by writing the control bits in the
appropriate IPCx register. The priority level will
depend on the specific application and type of
interrupt source. If multiple priority levels are not
desired, the IPCx register control bits for all
enabled interrupt sources can be programmed
to the same non-zero value.
All user interrupts can be disabled using this proce-
dure:
1. Push the current SR value onto the software
stack using the PUSHinstruction.
2. Force the CPU to priority level 7 by inclusive
ORing the value OEh with SRL.
To enable user interrupts, the POP instruction can be
Note: At a device Reset, the IPCx registers are
initialized such that all user interrupt
sources are assigned to priority level 4.
used to restore the previous SR value.
Note: Only user interrupts with a priority level of
7 or lower can be disabled. Trap sources
(level 8-level 15) cannot be disabled.
3. Clear the interrupt flag status bit associated with
the peripheral in the associated IFSx register.
The DISIinstruction provides a convenient way to dis-
able interrupts of priority levels 1-6 for a fixed period of
time. Level 7 interrupt sources are not disabled by the
DISI instruction.
4. Set the interrupt enable control bit associated
with the source in the appropriate IECx register
to enable the interrupt source.
6.4.2
INTERRUPT SERVICE ROUTINE
The method used to declare an ISR and initialize the
IVT with the correct vector address depends on the
programming language (C or Assembler) and the lan-
guage development toolsuite used to develop the appli-
cation.
In general, the user application must clear the interrupt
flag in the appropriate IFSx register for the source of
interrupt that the ISR handles. Otherwise, the program
will re-enter the ISR immediately after exiting the
routine. If the ISR is coded in assembly language, it
must be terminated using a RETFIE instruction to
unstack the saved PC value, SRL value and old CPU
priority level.
© 2007 Microchip Technology Inc.
Preliminary
DS70289A-page 79
PIC24HJ32GP202/204 and PIC24HJ16GP304
NOTES:
DS70289A-page 80
Preliminary
© 2007 Microchip Technology Inc.
PIC24HJ32GP202/204 and PIC24HJ16GP304
• An internal FRC oscillator that can also be used
7.0
OSCILLATOR
with the PLL, thereby allowing full speed
CONFIGURATION
operation without any external clock generation
hardware
Note:
This data sheet summarizes the features
• Clock switching between various clock sources
of the PIC24HJ32GP202/204 and
PIC24HJ16GP304 devices. It is not
intended to be a comprehensive reference
source. To complement the information in
this data sheet, refer to the “PIC24H
Family Reference Manual”.
• Programmable clock postscaler for system power
savings
• A Fail-Safe Clock Monitor (FSCM) that detects
clock failure and takes fail-safe measures
• A Clock Control register (OSCCON)
The PIC24HJ32GP202/204 and PIC24HJ16GP304
oscillator system provides:
• Nonvolatile Configuration bits for main oscillator
selection.
• External and internal oscillator options as clock
sources
A simplified diagram of the oscillator system is shown
in Figure 7-1.
• An on-chip PLL to scale the internal operating
frequency to the required system clock frequency
FIGURE 7-1:
PIC24HJ32GP202/204 AND PIC24HJ16GP304 OSCILLATOR SYSTEM DIAGRAM
PIC24H
Primary Oscillator
DOZE<2:0>
XT, HS, EC
OSCO
OSCI
S2
XTPLL, HSPLL,
ECPLL, FRCPLL
S3
S1
FCY
PLL(1)
S1/S3
÷ 2
FOSC
FRC
Oscillator
FRCDIVN
S7
FRCDIV<2:0>
TUN<5:0>
FRCDIV16
FRC
S6
S0
÷ 16
LPRC
SOSC
LPRC
Oscillator
S5
Secondary Oscillator
SOSCO
SOSCI
S4
LPOSCEN
Clock Switch
Reset
Clock Fail
S7
NOSC<2:0> FNOSC<2:0>
WDT, PWRT,
FSCM
Timer 1
Note 1: See Figure 7-2 for PLL details
© 2007 Microchip Technology Inc.
Preliminary
DS-70289A-page 81
PIC24HJ32GP202/204 and PIC24HJ16GP304
7.1.2
SYSTEM CLOCK SELECTION
7.1
CPU Clocking System
The oscillator source used at a device Power-on Reset
event is selected using Configuration bit settings. The
oscillator Configuration bit settings are located in the
Configuration registers in the program memory. (Refer to
Section 18.1 “Configuration Bits” for further details.)
The Initial Oscillator Selection Configuration bits,
FNOSC<2:0> (FOSCSEL<2:0>), and the Primary Oscil-
lator Mode Select Configuration bits, POSCMD<1:0>
(FOSC<1:0>), select the oscillator source that is used at
a Power-on Reset. The FRC primary oscillator is the
default (unprogrammed) selection.
The PIC24HJ32GP202/204 and PIC24HJ16GP304
devices provide the following seven system clock
options.
• Fast RC (FRC) Oscillator
• FRC Oscillator with PLL
• Primary (XT, HS or EC) Oscillator
• Primary Oscillator with PLL
• Secondary (LP) Oscillator
• Low-Power RC (LPRC) Oscillator
• FRC Oscillator with postscaler
The Configuration bits allow users to choose among 12
different clock modes, shown in Table 7-1.
7.1.1
SYSTEM CLOCK SOURCES
Fast RC
The output of the oscillator (or the output of the PLL if
a PLL mode has been selected) FOSC is divided by 2 to
generate the device instruction clock (FCY). FCY
defines the operating speed of the device, and speeds
up to 40 MHz are supported by the PIC24HJ32GP202/
204 and PIC24HJ16GP304 architecture.
7.1.1.1
The Fast RC (FRC) internal oscillator runs at a nominal
frequency of 7.37 MHz. User software can tune the
FRC frequency. User software can optionally specify a
factor (ranging from 1:2 to 1:256) by which the FRC
clock frequency is divided. This factor is selected using
the FRCDIV<2:0> (CLKDIV<10:8>) bits.
Instruction execution speed or device operating
frequency, FCY, is given by:
7.1.1.2
Primary
EQUATION 7-1:
DEVICE OPERATING
FREQUENCY
The primary oscillator can use one of the following as
its clock source:
FCY = FOSC/2
• Crystal (XT): Crystals and ceramic resonators in
the range of 3 MHz to 10 MHz. The crystal is con-
nected to the OSC1 and OSC2 pins.
7.1.3
PLL CONFIGURATION
• HS (High-Speed Crystal): Crystals in the range of
10 MHz to 40 MHz. The crystal is connected to
the OSC1 and OSC2 pins.
The primary oscillator and internal FRC oscillator can
optionally use on-chip PLL to obtain higher speeds of
operation. The PLL provides significant flexibility in
selecting the device operating speed. A block diagram
of the PLL is shown in Figure 7-2.
• EC (External Clock): External clock signal in the
range of 0.8 MHz to 64 MHz. The external clock
signal is directly applied to the OSC1 pin.
The output of the primary oscillator or FRC, denoted as
‘FIN’ is divided down by a prescale factor (N1) of 2, 3,
... or 33 before it is being provided to the PLL’s Voltage
Controlled Oscillator (VCO). The input to the VCO must
be selected in the range of 0.8 MHz to 8 MHz. The
prescale factor ‘N1’ is selected using the
PLLPRE<4:0> bits (CLKDIV<4:0>).
7.1.1.3
Secondary
The secondary (LP) oscillator is designed for low power
and uses a 32.768 kHz crystal or ceramic resonator.
The LP oscillator uses SOSCI and SOSCO pins.
7.1.1.4
Low-Power RC
The PLL Feedback Divisor, selected using the
PLLDIV<8:0> bits (PLLFBD<8:0>), provides a factor ‘M,’
by which the input to the VCO is multiplied. This factor
must be selected such that the resulting VCO output
frequency is in the range of 100 MHz to 200 MHz.
The Low-Power RC (LPRC) internal oscIllator runs at a
nominal frequency of 32.768 kHz. It is also used as a
reference clock by the Watchdog Timer (WDT) and
Fail-Safe Clock Monitor (FSCM).
The VCO output is further divided by a postscale factor
‘N2.’ This factor is selected using the PLLPOST<1:0>
bits (CLKDIV<7:6>). ‘N2’ can be 2, 4 or 8, and must be
selected such that the PLL output frequency (FOSC) is
in the range of 12.5 MHz to 80 MHz, which generates
device operating speeds of 6.25-40 MIPS.
7.1.1.5
FRC
The clock signals generated by the FRC and primary
oscillators can be optionally applied to an on-chip
Phase Locked Loop (PLL) to provide a wide range of
output frequencies for device operation. PLL
configuration is described in Section 7.1.3 “PLL
Configuration”.
DS-70289A-page 82
Preliminary
© 2007 Microchip Technology Inc.
PIC24HJ32GP202/204 and PIC24HJ16GP304
For a primary oscillator or FRC oscillator, output ‘FIN’,
the PLL output ‘FOSC’ is given by:
• If PLLDIV<8:0> = 0x1E, then M = 32. This yields a
VCO output of 5 x 32 = 160 MHz, which is within
the 100 MHz to 200 MHz range, which is needed.
EQUATION 7-2:
FOSC CALCULATION
• If PLLPOST<1:0> = 0, then N2 = 2. This provides
a Fosc of 160/2 = 80 MHz. The resultant device
operating speed is 80/2 = 40 MIPS.
M
FOSC = FIN*
(
)
N1*N2
For example, when a 10 MHz crystal is being used,
with “XT with PLL” being the selected oscillator mode.
EQUATION 7-3:
XT WITH PLL MODE
EXAMPLE
•
If PLLPRE<4:0> = 0, then N1 = 2. This yields a
VCO input of 10/2 = 5 MHz, which is within the
acceptable range of 0.8-8 MHz.
FOSC
2
1
10000000*32
FCY =
=
(
)
= 40 MIPS
2
2*2
FIGURE 7-2:
PIC24HJ32GP202/204 AND PIC24HJ16GP304 PLL BLOCK DIAGRAM
0.8-8.0 MHz
Here
100-200 MHz
Here
12.5-80 MHz
Here
Source (Crystal, External Clock
or Internal RC)
FOSC
PLLPRE
VCO
PLLPOST
X
PLLDIV
Divide by
2-33
Divide by
2, 4, 8
Divide by
2-513
TABLE 7-1:
CONFIGURATION BIT VALUES FOR CLOCK SELECTION
Oscillator Mode
Oscillator Source
POSCMD<1:0>
FNOSC<2:0>
Note
1, 2
Fast RC Oscillator with Divide-by-N
(FRCDIVN)
Internal
xx
111
110
Fast RC Oscillator with Divide-by-16
(FRCDIV16)
Internal
xx
1
Low-Power RC Oscillator (LPRC)
Internal
Secondary
Primary
xx
xx
10
101
100
011
1
1
Secondary (Timer1) Oscillator (SOSC)
Primary Oscillator (HS) with PLL
(HSPLL)
Primary Oscillator (XT) with PLL
(XTPLL)
Primary
Primary
01
00
011
011
Primary Oscillator (EC) with PLL
(ECPLL)
1
Primary Oscillator (HS)
Primary
Primary
Primary
Internal
Internal
10
01
00
xx
xx
010
010
010
001
000
Primary Oscillator (XT)
Primary Oscillator (EC)
1
1
1
Fast RC Oscillator with PLL (FRCPLL)
Fast RC Oscillator (FRC)
Note 1: OSC2 pin function is determined by the OSCIOFNC Configuration bit.
2: This is the default oscillator mode for an unprogrammed (erased) device.
© 2007 Microchip Technology Inc.
Preliminary
DS-70289A-page 83
PIC24HJ32GP202/204 and PIC24HJ16GP304
REGISTER 7-1:
OSCCON: OSCILLATOR CONTROL REGISTER
U-0
—
R-0
R-0
R-0
U-0
—
R/W-y
R/W-y
R/W-y
bit 8
COSC<2:0>
NOSC<2:0>
bit 15
R/W-0
CLKLOCK
bit 7
R/W-0
R-0
U-0
—
R/C-0
CF
U-0
—
R/W-0
R/W-0
IOLOCK
LOCK
LPOSCEN
OSWEN
bit 0
Legend:
y = Value set from Configuration bits on POR
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15
Unimplemented: Read as ‘0’
bit 14-12
COSC<2:0>: Current Oscillator Selection bits (read-only)
000= Fast RC oscillator (FRC)
001= Fast RC oscillator (FRC) with PLL
010= Primary oscillator (XT, HS, EC)
011= Primary oscillator (XT, HS, EC) with PLL
100= Secondary oscillator (SOSC)
101= Low-Power RC oscillator (LPRC)
110= Fast RC oscillator (FRC) with Divide-by-16
111= Fast RC oscillator (FRC) with Divide-by-n
bit 11
Unimplemented: Read as ‘0’
bit 10-8
NOSC<2:0>: New Oscillator Selection bits
000= Fast RC oscillator (FRC)
001= Fast RC oscillator (FRC) with PLL
010= Primary oscillator (XT, HS, EC)
011= Primary oscillator (XT, HS, EC) with PLL
100= Secondary oscillator (SOSC)
101= Low-Power RC oscillator (LPRC)
110= Fast RC oscillator (FRC) with Divide-by-16
111= Fast RC oscillator (FRC) with Divide-by-n
bit 7
CLKLOCK: Clock Lock Enable bit
If clock switching is enabled and FSCM is disabled (FOSC<FCKSM> = 0b01)
1= Clock switching is disabled, system clock source is locked
0= Clock switching is enabled, system clock source can be modified by clock switching
bit 6
bit 5
IOLOCK: Peripheral Pin Select Lock bit
1= Peripherial Pin Select is locked, write to peripheral pin select register is not allowed
0= Peripherial Pin Select is unlocked, write to peripheral pin select register is allowed
LOCK: PLL Lock Status bit (read-only)
1= Indicates that PLL is in lock, or PLL start-up timer is satisfied
0= Indicates that PLL is out of lock, start-up timer is in progress or PLL is disabled
bit 4
bit 3
Unimplemented: Read as ‘0’
CF: Clock Fail Detect bit (read/clear by application)
1= FSCM has detected clock failure
0= FSCM has not detected clock failure
bit 2
Unimplemented: Read as ‘0’
DS-70289A-page 84
Preliminary
© 2007 Microchip Technology Inc.
PIC24HJ32GP202/204 and PIC24HJ16GP304
REGISTER 7-1:
OSCCON: OSCILLATOR CONTROL REGISTER (CONTINUED)
bit 1
LPOSCEN: Secondary (LP) Oscillator Enable bit
1= Enable secondary oscillator
0= Disable secondary oscillator
bit 0
OSWEN: Oscillator Switch Enable bit
1= Request oscillator switch to selection specified by NOSC<2:0> bits
0= Oscillator switch is complete
© 2007 Microchip Technology Inc.
Preliminary
DS-70289A-page 85
PIC24HJ32GP202/204 and PIC24HJ16GP304
REGISTER 7-2:
CLKDIV: CLOCK DIVISOR REGISTER
R/W-0
ROI
R/W-0
R/W-0
R/W-0
R/W-0
DOZEN(1)
R/W-1
R/W-0
R/W-0
bit 8
R/W-0
DOZE<2:0>
FRCDIV<2:0>
bit 15
R/W-0
R/W-1
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
PLLPOST<1:0>
PLLPRE<4:0>
bit 7
bit 0
Legend:
y = Value set from Configuration bits on POR
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15
ROI: Recover on Interrupt bit
1= Interrupts will clear the DOZEN bit and the processor clock/peripheral clock ratio is set to 1:1
0= Interrupts have no effect on the DOZEN bit
bit 14-12
DOZE<2:0>: Processor Clock Reduction Select bits
000= FCY/1
001= FCY/2
010= FCY/4
011= FCY/8 (default)
100= FCY/16
101= FCY/32
110= FCY/64
111= FCY/128
bit 11
DOZEN: DOZE Mode Enable bit(1)
1= DOZE<2:0> field specifies the ratio between the peripheral clocks and the processor clocks
0= Processor clock/peripheral clock ratio forced to 1:1
bit 10-8
FRCDIV<2:0>: Internal Fast RC Oscillator Postscaler bits
000= FRC divide by 1 (default)
001= FRC divide by 2
010= FRC divide by 4
011= FRC divide by 8
100= FRC divide by 16
101= FRC divide by 32
110= FRC divide by 64
111= FRC divide by 256
bit 7-6
PLLPOST<1:0>: PLL VCO Output Divider Select bits (also denoted as ‘N2’, PLL postscaler)
00= Output/2
01= Output/4 (default)
10= Reserved
11= Output/8
bit 5
Unimplemented: Read as ‘0’
bit 4-0
PLLPRE<4:0>: PLL Phase Detector Input Divider bits (also denoted as ‘N1’, PLL prescaler)
00000= Input/2 (default)
00001= Input/3
•
•
•
11111= Input/33
Note 1: This bit is cleared when the ROI bit is set and an interrupt occurs.
DS-70289A-page 86
Preliminary
© 2007 Microchip Technology Inc.
PIC24HJ32GP202/204 and PIC24HJ16GP304
REGISTER 7-3:
PLLFBD: PLL FEEDBACK DIVISOR REGISTER
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
R/W-0(1)
PLLDIV<8>
bit 8
bit 15
R/W-0
R/W-0
R/W-1
R/W-1
R/W-0
R/W-0
R/W-0
R/W-0
bit 0
PLLDIV<7:0>
bit 7
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-9
bit 8-0
Unimplemented: Read as ‘0’
PLLDIV<8:0>: PLL Feedback Divisor bits (also denoted as ‘M’, PLL multiplier)
000000000= 2
000000001= 3
000000010= 4
•
•
•
000110000= 50 (default)
•
•
•
111111111= 513
© 2007 Microchip Technology Inc.
Preliminary
DS-70289A-page 87
PIC24HJ32GP202/204 and PIC24HJ16GP304
REGISTER 7-4:
OSCTUN: FRC OSCILLATOR TUNING REGISTER
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
bit 15
bit 8
U-0
—
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
TUN<5:0>
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-6
bit 5-0
Unimplemented: Read as ‘0’
TUN<5:0>: FRC Oscillator Tuning bits
011111= Center frequency + 11.625%
011110= Center frequency + 11.25% (8.23 MHz)
•
•
•
000001= Center frequency + 0.375% (7.40 MHz)
000000= Center frequency (7.37 MHz nominal)
111111= Center frequency – 0.375% (7.345 MHz)
•
•
•
100001= Center frequency – 11.625% (6.52 MHz)
100000= Center frequency – 12% (6.49 MHz)
DS-70289A-page 88
Preliminary
© 2007 Microchip Technology Inc.
PIC24HJ32GP202/204 and PIC24HJ16GP304
case, the OSWEN bit is cleared automatically
and the clock switch is aborted.
7.2
Clock Switching Operation
Applications are free to switch among any of the four
clock sources (Primary, LP, FRC and LPRC) under
software control at any time. To limit the possible side
effects of this flexibility, PIC24HJ32GP202/204 and
PIC24HJ16GP304 devices have a safeguard lock built
into the switch process.
2. If a valid clock switch has been initiated, the
LOCK (OSCCON<5>) and the CF
(OSCCON<3>) status bits are cleared.
3. The new oscillator is turned on by the hardware
if it is not currently running. If a crystal oscillator
has to be turned on, the hardware waits until the
Oscillator Start-up Timer (OST) expires. If the
new source is using the PLL, the hardware waits
until a PLL lock is detected (LOCK = 1).
Note:
Primary Oscillator mode has three different
submodes (XT, HS and EC), which are
determined by the POSCMD<1:0> Config-
uration bits. While an application can
switch to and from Primary Oscillator
mode in software, it cannot switch among
the different primary submodes without
reprogramming the device.
4. The hardware waits for 10 clock cycles from the
new clock source and then performs the clock
switch.
5. The hardware clears the OSWEN bit to indicate a
successful clock transition. In addition, the NOSC
bit values are transferred to the COSC status bits.
7.2.1
ENABLING CLOCK SWITCHING
6. The old clock source is turned off at this time,
with the exception of LPRC (if WDT or FSCM
are enabled) or LP (if LPOSCEN remains set).
To enable clock switching, the FCKSM1 Configuration
bit in the Configuration register must be programmed to
‘0’. (Refer to Section 18.1 “Configuration Bits” for
further details.) If the FCKSM1 Configuration bit is
unprogrammed (‘1’), the clock switching function and
Fail-Safe Clock Monitor function are disabled. This is
the default setting.
Note 1: The processor continues to execute code
throughout the clock switching sequence.
Timing-sensitive code should not be
executed during this time.
2: Direct clock switches between any primary
oscillator mode with PLL and FRCPLL
mode are not permitted. This applies to
clock switches in either direction. In these
instances, the application must switch to
FRC mode as a transition clock source
between the two PLL modes.
The NOSC control bits (OSCCON<10:8>) do not
control the clock selection when clock switching is
disabled. However, the COSC bits (OSCCON<14:12>)
reflect the clock source selected by the FNOSC
Configuration bits.
The OSWEN control bit (OSCCON<0>) has no effect
when clock switching is disabled. It is held at ‘0’ at all
times.
7.3
Fail-Safe Clock Monitor (FSCM)
7.2.2
OSCILLATOR SWITCHING
SEQUENCE
The Fail-Safe Clock Monitor (FSCM) allows the device
to continue to operate even in the event of an oscillator
failure. The FSCM function is enabled by programming.
If the FSCM function is enabled, the LPRC internal
oscillator runs at all times (except during Sleep mode)
and is not subject to control by the Watchdog Timer.
Performing a clock switch requires the following basic
sequence:
1. Read the COSC bits (OSCCON<14:12>) to
determine the current oscillator source, if
desired.
In the event of an oscillator failure, the FSCM
generates a clock failure trap event and switches the
system clock over to the FRC oscillator. Then the
application program can either attempt to restart the
oscillator or execute a controlled shutdown. The trap
can be treated as a warm Reset by simply loading the
Reset address into the oscillator fail trap vector.
2. Perform the unlock sequence to allow a write to
the OSCCON register high byte.
3. Write the appropriate value to the NOSC control
bits (OSCCON<10:8>) for the new oscillator
source.
4. Perform the unlock sequence to allow a write to
the OSCCON register low byte.
If the PLL multiplier is used to scale the system clock,
the internal FRC is also multiplied by the same factor
on clock failure. Essentially, the device switches to
FRC with PLL on a clock failure.
5. Set the OSWEN bit to initiate the oscillator
switch.
Once the basic sequence is completed, the system
clock hardware responds automatically as follows:
1. The clock switching hardware compares the
COSC status bits with the new value of the
NOSC control bits. If both of them are the same,
the clock switch is a redundant operation. In this
© 2007 Microchip Technology Inc.
Preliminary
DS-70289A-page 89
PIC24HJ32GP202/204 and PIC24HJ16GP304
NOTES:
DS-70289A-page 90
Preliminary
© 2007 Microchip Technology Inc.
PIC24HJ32GP202/204 and PIC24HJ16GP304
8.2
Instruction-Based Power-Saving
Modes
8.0
POWER-SAVING FEATURES
Note:
This data sheet summarizes the features
of the PIC24HJ32GP202/204 and
PIC24HJ16GP304 devices. It is not
intended to be a comprehensive reference
source. To complement the information in
this data sheet, refer to the “PIC24H
Family Reference Manual”.
PIC24HJ32GP202/204 and PIC24HJ16GP304 devices
have two special power-saving modes that are entered
through the execution of a special PWRSAVinstruction.
Sleep mode stops clock operation and halts all code
execution. Idle mode halts the CPU and code execu-
tion, but allows peripheral modules to continue opera-
tion. Example 8-1 shows the Assembler syntax of the
PWRSAVinstruction.
The PIC24HJ32GP202/204 and PIC24HJ16GP304
devices provide the ability to manage power consump-
tion by selectively managing clocking to the CPU and
the peripherals. In general, a lower clock frequency and
a reduction in the number of circuits being clocked con-
stitutes lower consumed power. PIC24HJ32GP202/
204 and PIC24HJ16GP304 devices can manage
power consumption in four different ways:
Note: SLEEP_MODE and IDLE_MODE are
constants defined in the assembler
include file for the selected device.
Sleep and Idle modes can be exited as a result of an
enabled interrupt, WDT time-out or a device Reset. When
the device exits these modes, it is said to wake-up.
• Clock frequency
8.2.1
SLEEP MODE
• Instruction-based Sleep and Idle modes
• Software-controlled Doze mode
• Selective peripheral control in software
In the Sleep mode,
• The system clock source is shut down. If an on-
chip oscillator is used, it is turned off.
Combinations of the above methods can be used to
selectively customize an application’s power consump-
tion while still maintaining critical application features,
such as timing-sensitive communications.
• The device current consumption is reduced to a
minimum, provided that no I/O pin is sourcing
current.
• The Fail-Safe Clock Monitor does not operate,
since the system clock source is disabled.
8.1
Clock Frequency and Clock
Switching
• The LPRC clock continues to run if the WDT is
enabled.
PIC24HJ32GP202/204 and PIC24HJ16GP304 devices
allow a wide range of clock frequencies to be selected
under application control. If the system clock configura-
tion is not locked, users can choose low-power or high-
precision oscillators by simply changing the NOSC bits
(OSCCON<10:8>). The process of changing a system
clock during operation, as well as limitations to the pro-
cess, are discussed in more detail in Section 7.0
“Oscillator Configuration”.
• The WDT, if enabled, is automatically cleared
prior to entering Sleep mode.
• Some device features or peripherals may continue
to operate. This includes items such as the input
change notification on the I/O ports, or peripherals
that use an external clock input.
• Any peripheral that requires the system clock
source for its operation is disabled.
The device will wake-up from Sleep mode on any of
these events:
• Any interrupt source that is individually enabled
• Any form of device Reset
• A WDT time-out
On wake-up from Sleep mode, the processor restarts
with the same clock source that was active when Sleep
mode was entered.
EXAMPLE 8-1:
PWRSAVINSTRUCTION SYNTAX
PWRSAV #SLEEP_MODE
PWRSAV #IDLE_MODE
; Put the device into SLEEP mode
; Put the device into IDLE mode
© 2007 Microchip Technology Inc.
Preliminary
DS70289A-page 91
PIC24HJ32GP202/204 and PIC24HJ16GP304
Doze mode is enabled by setting the DOZEN bit
(CLKDIV<11>). The ratio between peripheral and core
clock speed is determined by the DOZE<2:0> bits
(CLKDIV<14:12>). There are eight possible
configurations, from 1:1 to 1:128, with 1:1 being the
default setting.
8.2.2
IDLE MODE
The following occur in Idle mode:
• The CPU stops executing instructions.
• The WDT is automatically cleared.
• The system clock source remains active. By
default, all peripheral modules continue to operate
normally from the system clock source, but can
also be selectively disabled (see Section 8.4
“Peripheral Module Disable”).
Programs can use Doze mode to selectively reduce
power consumption in event-driven applications. This
allows clock-sensitive functions, such as synchronous
communications, to continue without interruption while
the CPU idles, waiting for something to invoke an inter-
rupt routine. An automatic return to full-speed CPU
operation on interrupts can be enabled by setting the
ROI bit (CLKDIV<15>). By default, interrupt events
have no effect on Doze mode operation.
• If the WDT or FSCM is enabled, the LPRC also
remains active.
The device will wake from Idle mode on any of these
events:
• Any interrupt that is individually enabled.
• Any device Reset
For example, suppose the device is operating at
20 MIPS and the CAN module has been configured for
500 kbps based on this device operating speed. If the
device is placed in Doze mode with a clock frequency
ratio of 1:4, the CAN module continues to communicate
at the required bit rate of 500 kbps, but the CPU now
starts executing instructions at a frequency of 5 MIPS.
• A WDT time-out
On wake-up from Idle mode, the clock is reapplied to
the CPU and instruction execution begins immediately,
starting with the instruction following the PWRSAV
instruction, or the first instruction in the ISR.
8.2.3
INTERRUPTS COINCIDENT WITH
POWER SAVE INSTRUCTIONS
8.4
Peripheral Module Disable
The Peripheral Module Disable (PMD) registers
provide a method to disable a peripheral module by
stopping all clock sources supplied to that module.
When a peripheral is disabled using the appropriate
PMD control bit, the peripheral is in a minimum power
consumption state. The control and status registers
associated with the peripheral are also disabled. So
writes to those registers will have no effect and read
values will be invalid.
Any interrupt that coincides with the execution of a
PWRSAV instruction is held off until entry into Sleep or
Idle mode is completed. The device then wakes up
from Sleep or Idle mode.
8.3
Doze Mode
The preferred strategies for reducing power consump-
tion are changing clock speed and invoking one of the
power-saving modes. In some circumstances, how-
ever, these are not practical. For example, it may be
necessary for an application to maintain uninterrupted
synchronous communication, even while it is doing
nothing else. Reducing system clock speed can intro-
duce communication errors, while using a power-sav-
ing mode can stop communications completely.
A peripheral module is enabled only if both the associ-
ated bit in the PMD register are cleared and the periph-
eral is supported by the specific PIC24H variant. If the
peripheral is present in the device, it is enabled in the
PMD register by default.
Note:
If a PMD bit is set, the corresponding mod-
ule is disabled after a delay of one instruc-
tion cycle. Similarly, if a PMD bit is
cleared, the corresponding module is
enabled after a delay of one instruction
cycle (assuming the module control regis-
ters are already configured to enable mod-
ule operation).
Doze mode is a simple and effective alternative method
to reduce power consumption while the device is still
executing code. In this mode, the system clock contin-
ues to operate from the same source and at the same
speed. Peripheral modules continue to be clocked at
the same speed, while the CPU clock speed is
reduced. Synchronization between the two clock
domains is maintained, allowing the peripherals to
access the SFRs while the CPU executes code at a
slower rate.
DS70289A-page 92
Preliminary
© 2007 Microchip Technology Inc.
PIC24HJ32GP202/204 and PIC24HJ16GP304
When a peripheral is enabled and the peripheral is
9.0
I/O PORTS
actively driving an associated pin, the use of the pin as
a general purpose output pin is disabled. The I/O pin
can be read, but the output driver for the parallel port bit
is disabled. If a peripheral is enabled, but the peripheral
is not actively driving a pin, that pin can be driven by a
port.
Note:
This data sheet summarizes the features
of the PIC24HJ32GP202/204 and
PIC24HJ16GP304 devices. It is not
intended to be a comprehensive reference
source. To complement the information in
this data sheet, refer to the “PIC24H
Family Reference Manual”.
All port pins have three registers directly associated
with their operation as digital I/O. The data direction
register (TRISx) determines whether the pin is an input
or an output. If the data direction bit is ‘1’, then the pin
is an input. All port pins are defined as inputs after a
Reset. Reads from the latch (LATx) read the latch.
Writes to the latch, write the latch. Reads from the port
(PORTx) read the port pins, while writes to the port pins
write the latch.
All of the device pins (except VDD, VSS, MCLR and
OSC1/CLKI) are shared among the peripherals and the
parallel I/O ports. All I/O input ports feature Schmitt
Trigger inputs for improved noise immunity.
9.1
Parallel I/O (PIO) Ports
A parallel I/O port that shares a pin with a peripheral is
generally subservient to the peripheral. The
peripheral’s output buffer data and control signals are
provided to a pair of multiplexers. The multiplexers
select whether the peripheral or the associated port
has ownership of the output data and control signals of
the I/O pin. The logic also prevents “loop through,” in
which a port’s digital output can drive the input of a
peripheral that shares the same pin. Figure 9-1 shows
how ports are shared with other peripherals and the
associated I/O pin to which they are connected.
Any bit and its associated data and control registers
that are not valid for a particular device will be
disabled. This means that the corresponding LATx
and TRISx registers and the port pin will read as
zeros.
When a pin is shared with another peripheral or func-
tion that is defined as an input only, it is nevertheless
regarded as a dedicated port because there is no
other competing source of outputs.
FIGURE 9-1:
BLOCK DIAGRAM OF A TYPICAL SHARED PORT STRUCTURE
Peripheral Module
Output Multiplexers
Peripheral Input Data
Peripheral Module Enable
I/O
Peripheral Output Enable
Peripheral Output Data
1
0
Output Enable
Output Data
1
0
PIO Module
Read TRIS
Data Bus
WR TRIS
D
Q
I/O Pin
CK
TRIS Latch
D
Q
WR LAT +
WR Port
CK
Data Latch
Read LAT
Read Port
Input Data
© 2007 Microchip Technology Inc.
Preliminary
DS70289A-page 93
PIC24HJ32GP202/204 and PIC24HJ16GP304
9.1.1
OPEN-DRAIN CONFIGURATION
9.2.1
I/O PORT WRITE/READ TIMING
In addition to the PORT, LAT and TRIS registers for
data control, each port pin can also be individually con-
figured for either digital or open-drain output. This is
controlled by the Open-Drain Control register, ODCx,
associated with each port. Setting any of the bits con-
figures the corresponding pin to act as an open-drain
output.
One instruction cycle is required between a port
direction change or port write operation and a read
operation of the same port. Typically this instruction
would be a NOP. An example is shown in EXAMPLE 9-
1: “Port Write/Read Example”.
9.3
Input Change Notification
The open-drain feature allows the generation of
outputs higher than VDD (e.g., 5V) on any desired digi-
tal-only pins by using external pull-up resistors. The
maximum open-drain voltage allowed is the same as
the maximum VIH specification.
The input change notification function of the I/O ports
allows the PIC24HJ32GP202/204 and
PIC24HJ16GP304 devices to generate interrupt
requests to the processor in response to a change-of-
state on selected input pins. This feature can detect
input change-of-states even in Sleep mode, when the
clocks are disabled. Depending on the device pin
count, up to 31 external signals (CNx pin) can be
selected (enabled) for generating an interrupt request
on a change-of-state.
9.2
Configuring Analog Port Pins
The AD1PCFG and TRIS registers control the opera-
tion of the analog-to-digital (A/D) port pins. The port
pins that are desired as analog inputs must have their
corresponding TRIS bit set (input). If the TRIS bit is
cleared (output), the digital output level (VOH or VOL)
will be converted.
Four control registers are associated with the CN mod-
ule. The CNEN1 and CNEN2 registers contain the
interrupt enable control bits for each of the CN input
pins. Setting any of these bits enables a CN interrupt
for the corresponding pins.
When the PORT register is read, all pins configured as
analog input channels will read as cleared (a low level).
Each CN pin also has a weak pull-up connected to it.
The pull-ups act as a current source connected to the
pin, and eliminate the need for external resistors when
push button or keypad devices are connected. The
pull-ups are enabled separately using the CNPU1 and
CNPU2 registers, which contain the control bits for
each of the CN pins. Setting any of the control bits
enables the weak pull-ups for the corresponding pins.
Pins configured as digital inputs will not convert an
analog input. Analog levels on any pin that is defined as
a digital input (including the ANx pins) can cause the
input buffer to consume current that exceeds the
device specifications.
Note:
Pull-ups on change notification pins
should always be disabled when the port
pin is configured as a digital output.
EXAMPLE 9-1:
PORT WRITE/READ EXAMPLE
MOV
MOV
NOP
0xFF00, W0
W0, TRISBB
; Configure PORTB<15:8> as inputs
; and PORTB<7:0> as outputs
; Delay 1 cycle
btss PORTB, #13
; Next Instruction
DS70289A-page 94
Preliminary
© 2007 Microchip Technology Inc.
PIC24HJ32GP202/204 and PIC24HJ16GP304
Remappable peripherals are not associated with a
default I/O pin. The peripheral must always be
9.4
Peripheral Pin Select
A major challenge in general purpose devices is
providing the largest possible set of peripheral features
while minimizing the conflict of features on I/O pins.
The challenge is even greater on low-pin count
devices. In an application where more than one
peripheral must be assigned to a single pin, inconve-
nient workarounds in application code or a complete
redesign may be the only option.
assigned to a specific I/O pin before it can be used. In
contrast, non remappable peripherals are always avail-
able on a default pin, assuming that the peripheral is
active and not conflicting with another peripheral.
9.4.2.1
Peripheral Pin Select Function
Priority
When a remappable peripheral is active on a given I/O
pin, it takes priority over all other digital I/O and digital
communication peripherals associated with the pin.
Priority is given regardless of the type of peripheral that
is mapped. Remappable peripherals never take priority
over any analog functions associated with the pin.
Peripheral pin select configuration enables peripheral
set selection and placement on a wide range of I/O
pins. By increasing the pinout options available on a
particular device, programmers can better tailor the
microcontroller to their entire application, rather than
trimming the application to fit the device.
9.4.3
CONTROLLING PERIPHERAL PIN
SELECT
The peripheral pin select configuration feature
operates over a fixed subset of digital I/O pins. Pro-
grammers can independently map the input and/or out-
put of most digital peripherals to any one of these I/O
pins. Peripheral pin select is performed in software,
and generally does not require the device to be
reprogrammed. Hardware safeguards are included that
prevent accidental or spurious changes to the
peripheral mapping, once it has been established.
Peripheral pin select features are controlled through
two sets of special function registers to map peripher-
als and to map outputs.
Since they are separately controlled, a particular
peripheral’s input and output (if the peripheral has both)
can be placed on any selectable function pin without
constraint.
9.4.1
AVAILABLE PINS
The association of a peripheral to a peripheral select-
able pin is handled in two different ways, depending on
whether an input or output is being mapped.
The peripheral pin select feature is used with a range
of up to 26 pins. The number of available pins depends
on the particular device and its pin count. Pins that
support the peripheral pin select feature include the
designation “RPn” in their full pin designation, where
“RP” designates a remappable peripheral and “n” is the
remappable pin number.
9.4.3.1
Input Mapping
The inputs of the peripheral pin select options are
mapped on the basis of the peripheral. A control regis-
ter associated with a peripheral dictates the pin it will be
mapped to. The RPINRx registers are used to config-
ure peripheral input mapping (see Register 9-1 through
Register 9-9). Each register contains sets of 5-bit
fields, with each set associated with one of the remap-
pable peripherals. Programming a given peripheral’s
bit field with an appropriate 5-bit value maps the RPn
pin with that value to that peripheral. For any given
device, the valid range of values for any bit field corre-
sponds to the maximum number of peripheral pin
selections supported by the device.
9.4.2
AVAILABLE PERIPHERALS
The peripheral pin select feature manages all digital-
only peripherals. These include:
• General serial communications (UART and SPI)
• General-purpose timer clock inputs
• Timer-related peripherals (input capture and out-
put compare)
• Interrupt-on-change inputs.
In comparison, some digital-only peripheral modules
are never included in the peripheral pin select feature.
This is because the peripheral’s function requires spe-
cial I/O circuitry on a specific port and cannot be easily
connected to multiple pins. These modules include I2C.
A similar requirement excludes all modules with analog
inputs, such as the Analog-to-Digital Converter (ADC).
Figure 9-2 Illustrates remappable pin selection for
U1RX input.
© 2007 Microchip Technology Inc.
Preliminary
DS70289A-page 95
PIC24HJ32GP202/204 and PIC24HJ16GP304
FIGURE 9-2:
REMAPPABLE MUX INPUT FOR U1RX
U1RXR[4:0]
0
1
2
RP0
RP1
RP2
U1RX input
to peripheral
25
RP25
TABLE 9-1:
REMAPPABLE PERIPHERAL INPUTS(1)
Configuration
Bits
Input Name
Function Name
Register
External Interrupt 1
External Interrupt 2
Timer 2 External Clock
Timer 3 External Clock
Input Capture 1
INT1
INT2
RPINR0
RPINR1
RPINR3
RPINR3
RPINR7
RPINR7
RPINR10
RPINR10
RPINR11
RPINR18
RPINR18
RPINR20
RPINR20
RPINR21
INT1R[4:0]
INT2R[4:0]
T2CKR[4:0]
T3CKR[4:0]
IC1R[4:0]
T2CK
T3CK
IC1
Input Capture 2
IC2
IC2R[4:0]
Input Capture 7
IC7
IC7R[4:0]
Input Capture 8
IC8
IC8R[4:0]
Output Compare Fault A
UART 1 Receive
OCFA
U1RX
U1CTS
SDI1
SCK1IN
SS1IN
OCFAR[4:0]
U1RXR[4:0]
U1CTSR[4:0]
SDI1R[4:0]
SCK1R[4:0]
SS1R[4:0]
UART 1 Clear To Send
SPI 1 Data Input
SPI 1 Clock Input
SPI 1 Slave Select Input
Note 1: Unless otherwise noted, all inputs use the Schmitt input buffers.
DS70289A-page 96
Preliminary
© 2007 Microchip Technology Inc.
PIC24HJ32GP202/204 and PIC24HJ16GP304
value of the bit field corresponds to one of the periph-
erals, and that peripheral’s output is mapped to the pin
(see Table 9-2 and Figure 9-3).
9.4.3.2
Output Mapping
In contrast to inputs, the outputs of the peripheral pin
select options are mapped on the basis of the pin. In
this case, a control register associated with a particular
pin dictates the peripheral output to be mapped. The
RPORx registers are used to control output mapping.
Like the RPINRx registers, each register contains sets
of 5-bit fields, with each set associated with one RPn
pin (see Register 9-10 through Register 9-22). The
The list of peripherals for output mapping also includes
a null value of 00000 because of the mapping tech-
nique. This permits any given pin to remain
unconnected from the output of any of the pin select-
able peripherals.
FIGURE 9-3:
MULTIPLEXING OF REMAPPABLE OUTPUT FOR RPn
RPnR[4:0]
default
0
3
4
U1TX Output enable
U1RTS Output enable
Output enable
OC1 Output enable
OC2 Output enable
18
19
default
0
3
4
U1TX Output
U1RTS Output
RPn
Output Data
OC1 Output
OC2 Output
18
19
TABLE 9-2:
OUTPUT SELECTION FOR REMAPPABLE PIN (RPn)
RPnR<4:0>
Function
Output Name
NULL
U1TX
00000
00011
00100
00111
01000
01001
10010
10011
RPn tied to default port pin
RPn tied to UART 1 Transmit
U1RTS
SDO1
RPn tied to UART 1 Ready To Send
RPn tied to SPI 1 Data Output
RPn tied to SPI 1 Clock Output
RPn tied to SPI 1 Slave Select Output
RPn tied to Output Compare 1
RPn tied to Output Compare 2
SCK1OUT
SS1OUT
OC1
OC2
© 2007 Microchip Technology Inc.
Preliminary
DS70289A-page 97
PIC24HJ32GP202/204 and PIC24HJ16GP304
9.4.3.3
Mapping
9.4.4.2
Continuous State Monitoring
The control schema of peripheral select pins is not lim-
ited to a small range of fixed peripheral configurations.
There are no mutual or hardware-enforced lockouts
between any of the peripheral mapping SFRs. Literally
any combination of peripheral mappings across any or
all of the RPn pins is possible. This includes both
many-to-one and one-to-many mappings of peripheral
inputs and outputs to pins.
In addition to being protected from direct writes, the
contents of the RPINRx and RPORx registers are
constantly monitored in hardware by shadow registers.
If an unexpected change in any of the registers occurs
(such as cell disturbances caused by ESD or other
external events), a configuration mismatch Reset will
be triggered.
9.4.4.3
Configuration Bit Pin Select Lock
While such mappings may be technically possible from
a configuration point of view, they may not be support-
able electrically.
As an additional level of safety, the device can be con-
figured to prevent more than one write session to the
RPINRx and RPORx registers. The IOL1WAY
(FOSC<IOL1WAY>) configuration bit blocks the
IOLOCK bit from being cleared after it has been set
once.
9.4.4
CONTROLLING CONFIGURATION
CHANGES
Because peripheral remapping can be changed during
run time, some restrictions on peripheral remapping
are needed to prevent accidental configuration
changes. PIC24H devices include three features to
prevent alterations to the peripheral map:
In the default (unprogrammed) state, IOL1WAY is set
restricting the users to one write session. Programming
IOL1WAY allows user applications unlimited access
(with the proper use of the unlock sequence) to the
peripheral pin select registers.
• Control register lock sequence
• Continuous state monitoring
• Configuration bit pin select lock
9.4.5
CONSIDERATIONS FOR
PERIPHERAL PIN SELECTION
The ability to control peripheral pin selection introduces
several considerations into application design, includ-
ing several common peripherals that are only available
as remappable peripherals.
9.4.4.1
Control Register Lock
Under normal operation, writes to the RPINRx and
RPORx registers are not allowed. Attempted writes
appear to execute normally, but the contents of the reg-
isters remain unchanged. To change these registers,
they must be unlocked in hardware. The register lock is
controlled by the IOLOCK bit (OSCCON<6>). Setting
IOLOCK prevents writes to the control registers; clear-
ing IOLOCK allows writes.
9.4.5.1
Configuration
The peripheral pin selects are not available on default
pins in the device’s default (Reset) state. More specifi-
cally, since all RPINRx and RPORx registers reset to
0000h, this means all peripheral pin select inputs are
tied to RP0, while all peripheral pin select outputs are
disconnected. This means that before any other appli-
cation code is executed, the user application must ini-
tialize the device with the proper peripheral
configuration.
To set or clear IOLOCK, a specific command sequence
must be executed:
1. Write 46h to OSCCON<7:0>.
2. Write 57h to OSCCON<7:0>.
3. Clear (or set) IOLOCK as a single operation.
Since the IOLOCK bit resets in the unlocked state, it is
not necessary to execute the unlock sequence after the
device has come out of Reset. For the sake of applica-
tion safety, however, it is always a good idea to set
IOLOCK and lock the configuration after writing to the
control registers.
Note:
MPLAB® C30 provides built-in C language
functions for unlocking the OSCCON
register:
__builtin_write_OSCCONL(value)
__builtin_write_OSCCONH(value)
See MPLAB Help for more information.
Because the unlock sequence is timing-critical, it must
be executed as an assembly-language routine, in the
same manner as changes to the oscillator
configuration. If the bulk of the application is written in
C or another high-level language, the unlock sequence
should be performed by writing inline assembly.
Unlike the similar sequence with the oscillator’s LOCK
bit, IOLOCK remains in one state until changed. This
allows all the peripheral pin selects to be configured
with a single unlock sequence followed by an update to
all control registers, then locked with a second lock
sequence.
DS70289A-page 98
Preliminary
© 2007 Microchip Technology Inc.
PIC24HJ32GP202/204 and PIC24HJ16GP304
9.4.5.2
Changing the Configuration
9.5
Peripheral Pin Select Registers
Choosing the configuration requires review of all
peripheral pin selects and their pin assignments,
especially those that will not be used in the application.
In all cases, unused pin selectable peripherals should
be disabled completely. Unused peripherals should
have their inputs assigned to an unused RPn pin
function. I/O pins with unused RPn functions should be
configured with the null peripheral output.
The PIC24HJ32GP202/204 and PIC24HJ16GP304
devices implement 17 registers for remappable periph-
eral configuration:
• Input Remappable Peripheral Registers (9)
• Output Remappable Peripheral Registers (8)
Note:
Input and Output Register values can only
be changed if OSCCON[IOLOCK] = 0.
See Section 9.4.4.1 “Control Register
Lock” for a specific command sequence.
The assignment of a peripheral to a particular pin does
not automatically perform any other configuration of the
pin’s I/O circuitry. This means adding a pin selectable
output to a pin can inadvertently drive an existing
peripheral input when the output is driven. Program-
mers must be familiar with the behavior of other fixed
peripherals that share a remappable pin, and know
when to enable or disable them. To be safe, fixed digi-
tal peripherals that share the same pin should be dis-
abled when not in use.
EXAMPLE 9-2:
CONFIGURING UART1
INPUT AND OUTPUT
FUNCTIONS
//*************************************
// Unlock Registers
//*************************************
asm volatile ( "mov #OSCCONL, w1 \n"
"mov #0x46, w2
"mov #0x57, w3
"mov.b w2, [w1]
"mov.b w3, [w1]
"bclr OSCCON, 6");
\n"
\n"
\n"
\n"
9.4.5.3
Pin Operation
Configuring a remappable pin for a specific peripheral
does not automatically turn that feature on. The periph-
eral must be specifically configured for an operation
and enabled, as if it were tied to a fixed pin. Where this
happens in the application code (immediately following
device Reset and peripheral configuration, or inside the
main application routine) depends on the peripheral
and its use in the application.
//***************************
// Configure Input Functions
// (See Table 9-1)
//***************************
//***************************
// Assign U1Rx To Pin RP0
//***************************
RPINR18bits.U1RXR = 0;
9.4.5.4
Analog Function
A final consideration is that peripheral pin select func-
tions neither override analog inputs nor reconfigure
pins with analog functions for digital I/O. If a pin is con-
figured as an analog input on device Reset, it must be
explicitly reconfigured as digital I/O when used with a
peripheral pin select.
//***************************
// Assign U1CTS To Pin RP1
//***************************
RPINR18bits.U1CTSR = 1;
//***************************
// Configure Output Functions
// (See Table 9-2)
//***************************
//***************************
// Assign U1Tx To Pin RP2
//***************************
RPOR1bits.RP2R = 3;
9.4.5.5
Configuration Example
Example 9-2 shows a configuration for bidirectional
communication with flow control using UART1. The fol-
lowing input and output functions are used:
• Input Functions: U1RX, U1CTS
• Output Functions: U1TX, U1RTS
//***************************
// Assign U1RTS To Pin RP3
//***************************
RPOR1bits.RP3R = 4;
//*************************************
// Lock Registers
//*************************************
asm volatile ( "mov #OSCCONL, w1 \n"
"mov #0x46, w2
"mov #0x57, w3
"mov.b w2, [w1]
"mov.b w3, [w1]
"bset OSCCON, 6");
\n"
\n"
\n"
\n"
© 2007 Microchip Technology Inc.
Preliminary
DS70289A-page 99
PIC24HJ32GP202/204 and PIC24HJ16GP304
REGISTER 9-1:
RPINR0: PERIPHERAL PIN SELECT INPUT REGISTER 0
U-0
—
U-0
—
U-0
—
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
bit 8
INT1R<4:0>
bit 15
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-13
bit 12-8
Unimplemented: Read as ‘0’
INT1R<4:0>: Assign External Interrupt 1 (INTR1) to the corresponding RPn pin
11111= Input tied to Vss
11001= Input tied to RP25
•
•
•
00001= Input tied to RP1
00000= Input tied to RP0
bit 7-0
Unimplemented: Read as ‘0’
DS70289A-page 100
Preliminary
© 2007 Microchip Technology Inc.
PIC24HJ32GP202/204 and PIC24HJ16GP304
REGISTER 9-2:
RPINR1: PERIPHERAL PIN SELECT INPUT REGISTER 1
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
bit 15
bit 8
U-0
—
U-0
—
U-0
—
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
INT2R<4:0>
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-5
bit 4-0
Unimplemented: Read as ‘0’
INT2R<4:0>: Assign External Interrupt 2 (INTR2) to the corresponding RPn pin
11111= Input tied to Vss
11001= Input tied to RP25
•
•
•
00001= Input tied to RP1
00000= Input tied to RP0
© 2007 Microchip Technology Inc.
Preliminary
DS70289A-page 101
PIC24HJ32GP202/204 and PIC24HJ16GP304
REGISTER 9-3:
RPINR3: PERIPHERAL PIN SELECT INPUT REGISTER 3
U-0
—
U-0
—
U-0
—
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
T3CKR<4:0>
bit 15
bit 8
R/W-1
bit 0
U-0
—
U-0
—
U-0
—
R/W-1
R/W-1
R/W-1
T2CKR<4:0>
bit 7
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-13
bit 12-8
Unimplemented: Read as ‘0’
T3CKR<4:0>: Assign Timer3 External Clock (T3CK) to the Corresponding RPn pin
11111= Input tied to Vss
11001= Input tied to RP25
•
•
•
00001= Input tied to RP1
00000= Input tied to RP0
bit 7-5
bit 4-0
Unimplemented: Read as ‘0’
T2CKR<4:0>: Assign Timer2 External Clock (T2CK) to the Corresponding RPn pin
11111= Input tied to Vss
11001= Input tied to RP25
•
•
•
00001= Input tied to RP1
00000= Input tied to RP0
DS70289A-page 102
Preliminary
© 2007 Microchip Technology Inc.
PIC24HJ32GP202/204 and PIC24HJ16GP304
REGISTER 9-4:
RPINR7: PERIPHERAL PIN SELECT INPUT REGISTER 7
U-0
—
U-0
—
U-0
—
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
bit 8
R/W-1
IC2R<4:0>
bit 15
U-0
—
U-0
—
U-0
—
R/W-1
R/W-1
R/W-1
IC1R<4:0>
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-13
bit 12-8
Unimplemented: Read as ‘0’
IC2R<4:0>: Assign Input Capture 2 (IC2) to the corresponding RPn pin
T2CKR<4:0>: Assign Timer2 External Clock (T2CK) to the Corresponding RPn pin
11111= Input tied to Vss
11001= Input tied to RP25
•
•
•
00001= Input tied to RP1
00000= Input tied to RP0
bit 7-5
bit 4-0
Unimplemented: Read as ‘0’
IC1R<4:0>: Assign Input Capture 1 (IC1) to the corresponding RPn pin
T2CKR<4:0>: Assign Timer2 External Clock (T2CK) to the Corresponding RPn pin
11111= Input tied to Vss
11001= Input tied to RP25
•
•
•
00001= Input tied to RP1
00000= Input tied to RP0
© 2007 Microchip Technology Inc.
Preliminary
DS70289A-page 103
PIC24HJ32GP202/204 and PIC24HJ16GP304
REGISTER 9-5:
RPIR10: PERIPHERAL PIN SELECT INPUT REGISTERS 10
U-0
—
U-0
—
U-0
—
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
bit 8
R/W-1
IC8R<4:0>
bit 15
U-0
—
U-0
—
U-0
—
R/W-1
R/W-1
R/W-1
IC7R<4:0>
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-13
bit 12-8
Unimplemented: Read as ‘0’
IC8R<4:0>: Assign Input Capture 8 (IC8) to the corresponding pin RPn pin
11111= Input tied to Vss
11001= Input tied to RP25
•
•
•
00001= Input tied to RP1
00000= Input tied to RP0
bit 7-5
bit 4-0
Unimplemented: Read as ‘0’
IC7R<4:0>: Assign Input Capture 7 (IC7) to the corresponding pin RPn pin
11111= Input tied to Vss
11001= Input tied to RP25
•
•
•
00001= Input tied to RP1
00000= Input tied to RP0
DS70289A-page 104
Preliminary
© 2007 Microchip Technology Inc.
PIC24HJ32GP202/204 and PIC24HJ16GP304
REGISTER 9-6:
RPINR11: PERIPHERAL PIN SELECT INPUT REGISTER 11
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
bit 15
bit 8
R/W-1
bit 0
U-0
—
U-0
—
U-0
—
R/W-1
R/W-1
R/W-1
R/W-1
OCFAR<4:0>
bit 7
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-5
bit 4-0
Unimplemented: Read as ‘0’
OCFAR<4:0>: Assign Output Capture A (OCFA) to the corresponding RPn pin
11111= Input tied to Vss
11001= Input tied to RP25
•
•
•
00001= Input tied to RP1
00000= Input tied to RP0
© 2007 Microchip Technology Inc.
Preliminary
DS70289A-page 105
PIC24HJ32GP202/204 and PIC24HJ16GP304
REGISTER 9-7:
RPINR18: PERIPHERAL PIN SELECT INPUT REGISTER 18
U-0
—
U-0
—
U-0
—
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
bit 8
R/W-1
U1CTSR<4:0>
bit 15
U-0
—
U-0
—
U-0
—
R/W-1
R/W-1
R/W-1
U1RXR<4:0>
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-13
bit 12-8
Unimplemented: Read as ‘0’
U1CTSR<4:0>: Assign UART 1 Clear to Send (U1CTS) to the corresponding RPn pin
11111= Input tied to Vss
11001= Input tied to RP25
•
•
•
00001= Input tied to RP1
00000= Input tied to RP0
bit 7-5
bit 4-0
Unimplemented: Read as ‘0’
U1RXR<4:0>: Assign UART 1 Receive (U1RX) to the corresponding RPn pin
11111= Input tied to Vss
11001= Input tied to RP25
•
•
•
00001= Input tied to RP1
00000= Input tied to RP0
DS70289A-page 106
Preliminary
© 2007 Microchip Technology Inc.
PIC24HJ32GP202/204 and PIC24HJ16GP304
REGISTER 9-8:
RPINR20: PERIPHERAL PIN SELECT INPUT REGISTER 20
U-0
—
U-0
—
U-0
—
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
bit 8
R/W-1
SCK1R<4:0>
bit 15
U-0
—
U-0
—
U-0
—
R/W-1
R/W-1
R/W-1
SDI1R<4:0>
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-13
bit 12-8
Unimplemented: Read as ‘0’
SCK1R<4:0>: Assign SPI 1 Clock Input (SCK1IN) to the corresponding RPn pin
11111= Input tied to Vss
11001= Input tied to RP25
•
•
•
00001= Input tied to RP1
00000= Input tied to RP0
bit 7-5
bit 4-0
Unimplemented: Read as ‘0’
SDI1R<4:0>: Assign SPI 1 Data Input (SDI1) to the corresponding RPn pin
11111= Input tied to Vss
11001= Input tied to RP25
•
•
•
00001= Input tied to RP1
00000= Input tied to RP0
© 2007 Microchip Technology Inc.
Preliminary
DS70289A-page 107
PIC24HJ32GP202/204 and PIC24HJ16GP304
REGISTER 9-9:
RPINR21: PERIPHERAL PIN SELECT INPUT REGISTER 21
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
bit 15
bit 8
R/W-1
bit 0
U-0
—
U-0
—
U-0
—
R/W-1
R/W-1
R/W-1
R/W-1
SS1R<4:0>
bit 7
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-5
bit 4-0
Unimplemented: Read as ‘0’
SS1R<4:0>: Assign SPI1 Slave Select Input (SS1IN) to the Corresponding RPn pin
11111= Input tied to Vss
11001= Input tied to RP25
•
•
•
00001= Input tied to RP1
00000= Input tied to RP0
DS70289A-page 108
Preliminary
© 2007 Microchip Technology Inc.
PIC24HJ32GP202/204 and PIC24HJ16GP304
REGISTER 9-10: RPOR0: PERIPHERAL PIN SELECT OUTPUT REGISTERS 0
U-0
—
U-0
—
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
bit 8
R/W-0
RP1R<4:0>
bit 15
U-0
—
U-0
—
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
RP0R<4:0>
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-13
bit 12-8
Unimplemented: Read as ‘0’
RP1R<4:0>: Peripheral Output Function is Assigned to RP1 Output Pin (see Table 9-2 for peripheral
function numbers)
bit 7-5
bit 4-0
Unimplemented: Read as ‘0’
RP0R<4:0>: Peripheral Output Function is Assigned to RP0 Output Pin (see Table 9-2 for peripheral
function numbers)
REGISTER 9-11: RPOR1: PERIPHERAL PIN SELECT OUTPUT REGISTERS 1
U-0
—
U-0
—
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
bit 8
RP3R<4:0>
bit 15
U-0
—
U-0
—
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
bit 0
RP2R<4:0>
bit 7
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-13
bit 12-8
Unimplemented: Read as ‘0’
RP3R<4:0>: Peripheral Output Function is Assigned to RP3 Output Pin (see Table 9-2 for peripheral
function numbers)
bit 7-5
bit 4-0
Unimplemented: Read as ‘0’
RP2R<4:0>: Peripheral Output Function is Assigned to RP2 Output Pin (see Table 9-2 for peripheral
function numbers)
© 2007 Microchip Technology Inc.
Preliminary
DS70289A-page 109
PIC24HJ32GP202/204 and PIC24HJ16GP304
REGISTER 9-12: RPOR2: PERIPHERAL PIN SELECT OUTPUT REGISTERS 2
U-0
—
U-0
—
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
bit 8
R/W-0
RP5R<4:0>
bit 15
U-0
—
U-0
—
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
RP4R<4:0>
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-13
bit 12-8
Unimplemented: Read as ‘0’
RP5R<4:0>: Peripheral Output Function is Assigned to RP5 Output Pin (see Table 9-2 for peripheral
function numbers)
bit 7-5
bit 4-0
Unimplemented: Read as ‘0’
RP4R<4:0>: Peripheral Output Function is Assigned to RP4 Output Pin (see Table 9-2 for peripheral
function numbers)
REGISTER 9-13: RPOR3: PERIPHERAL PIN SELECT OUTPUT REGISTERS 3
U-0
—
U-0
—
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
bit 8
RP7R<4:0>
bit 15
U-0
—
U-0
—
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
bit 0
RP6R<4:0>
bit 7
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-13
bit 12-8
Unimplemented: Read as ‘0’
RP7R<4:0>: Peripheral Output Function is Assigned to RP7 Output Pin (see Table 9-2 for peripheral
function numbers)
bit 7-5
bit 4-0
Unimplemented: Read as ‘0’
RP6R<4:0>: Peripheral Output Function is Assigned to RP6 Output Pin (see Table 9-2 for peripheral
function numbers)
DS70289A-page 110
Preliminary
© 2007 Microchip Technology Inc.
PIC24HJ32GP202/204 and PIC24HJ16GP304
REGISTER 9-14: RPOR4: PERIPHERAL PIN SELECT OUTPUT REGISTERS 0
U-0
—
U-0
—
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
bit 8
R/W-0
RP9R<4:0>
bit 15
U-0
—
U-0
—
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
RP8R<4:0>
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-13
bit 12-8
Unimplemented: Read as ‘0’
RP9R<4:0>: Peripheral Output Function is Assigned to RP9 Output Pin (see Table 9-2 for peripheral
function numbers)
bit 7-5
bit 4-0
Unimplemented: Read as ‘0’
RP8R<4:0>: Peripheral Output Function is Assigned to RP8 Output Pin (see Table 9-2 for peripheral
function numbers)
REGISTER 9-15: RPOR5: PERIPHERAL PIN SELECT OUTPUT REGISTERS 5
U-0
—
U-0
—
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
bit 8
RP11R<4:0>
bit 15
U-0
—
U-0
—
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
bit 0
RP10R<4:0>
bit 7
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-13
bit 12-8
Unimplemented: Read as ‘0’
RP11R<4:0>: Peripheral Output Function is Assigned to RP11 Output Pin (see Table 9-2 for peripheral
function numbers)
bit 7-5
bit 4-0
Unimplemented: Read as ‘0’
RP10R<4:0>: Peripheral Output Function is Assigned to RP10 Output Pin (see Table 9-2 for periph-
eral function numbers)
© 2007 Microchip Technology Inc.
Preliminary
DS70289A-page 111
PIC24HJ32GP202/204 and PIC24HJ16GP304
REGISTER 9-16: RPOR6: PERIPHERAL PIN SELECT OUTPUT REGISTERS 6
U-0
—
U-0
—
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
bit 8
R/W-0
RP13R<4:0>
bit 15
U-0
—
U-0
—
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
RP12R<4:0>
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-13
bit 12-8
Unimplemented: Read as ‘0’
RP13R<4:0>: Peripheral Output Function is Assigned to RP13 Output Pin (see Table 9-2 for periph-
eral function numbers)
bit 7-5
bit 4-0
Unimplemented: Read as ‘0’
RP12R<4:0>: Peripheral Output Function is Assigned to RP12 Output Pin (see Table 9-2 for periph-
eral function numbers)
REGISTER 9-17: RPOR7: PERIPHERAL PIN SELECT OUTPUT REGISTERS 7
U-0
—
U-0
—
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
bit 8
RP15R<4:0>
bit 15
U-0
—
U-0
—
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
bit 0
RP14R<4:0>
bit 7
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-13
bit 12-8
Unimplemented: Read as ‘0’
RP15R<4:0>: Peripheral Output Function is Assigned to RP15 Output Pin (see Table 9-2 for periph-
eral function numbers)
bit 7-5
bit 4-0
Unimplemented: Read as ‘0’
RP14R<4:0>: Peripheral Output Function is Assigned to RP14 Output Pin (see Table 9-2 for periph-
eral function numbers)
DS70289A-page 112
Preliminary
© 2007 Microchip Technology Inc.
PIC24HJ32GP202/204 and PIC24HJ16GP304
REGISTER 9-18: RPOR7: PERIPHERAL PIN SELECT OUTPUT REGISTERS 8
U-0
—
U-0
—
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
bit 8
R/W-0
RP17R<4:0>
bit 15
U-0
—
U-0
—
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
RP16R<4:0>
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-13
bit 12-8
Unimplemented: Read as ‘0’
RP15R<4:0>: Peripheral Output Function is Assigned to RP15 Output Pin (see Table 9-2 for periph-
eral function numbers)
bit 7-5
bit 4-0
Unimplemented: Read as ‘0’
RP14R<4:0>: Peripheral Output Function is Assigned to RP14 Output Pin (see Table 9-2 for periph-
eral function numbers)
REGISTER 9-19: RPOR7: PERIPHERAL PIN SELECT OUTPUT REGISTERS 9
U-0
—
U-0
—
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
bit 8
RP19R<4:0>
bit 15
U-0
—
U-0
—
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
bit 0
RP18R<4:0>
bit 7
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-13
bit 12-8
Unimplemented: Read as ‘0’
RP19R<4:0>: Peripheral Output Function is Assigned to RP19 Output Pin (see Table 9-2 for periph-
eral function numbers)
bit 7-5
bit 4-0
Unimplemented: Read as ‘0’
RP18R<4:0>: Peripheral Output Function is Assigned to RP18 Output Pin (see Table 9-2 for periph-
eral function numbers)
© 2007 Microchip Technology Inc.
Preliminary
DS70289A-page 113
PIC24HJ32GP202/204 and PIC24HJ16GP304
REGISTER 9-20: RPOR7: PERIPHERAL PIN SELECT OUTPUT REGISTERS 10
U-0
—
U-0
—
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
bit 8
R/W-0
RP21R<4:0>
bit 15
U-0
—
U-0
—
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
RP20R<4:0>
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-13
bit 12-8
Unimplemented: Read as ‘0’
RP21R<4:0>: Peripheral Output Function is Assigned to RP21 Output Pin (see Table 9-2 for periph-
eral function numbers)
bit 7-5
bit 4-0
Unimplemented: Read as ‘0’
RP20R<4:0>: Peripheral Output Function is Assigned to RP20 Output Pin (see Table 9-2 for periph-
eral function numbers)
REGISTER 9-21: RPOR7: PERIPHERAL PIN SELECT OUTPUT REGISTERS 11
U-0
—
U-0
—
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
bit 8
RP23R<4:0>
bit 15
U-0
—
U-0
—
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
bit 0
RP22R<4:0>
bit 7
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-13
bit 12-8
Unimplemented: Read as ‘0’
RP23R<4:0>: Peripheral Output Function is Assigned to RP23 Output Pin (see Table 9-2 for periph-
eral function numbers)
bit 7-5
bit 4-0
Unimplemented: Read as ‘0’
RP22R<4:0>: Peripheral Output Function is Assigned to RP22 Output Pin (see Table 9-2 for periph-
eral function numbers)
DS70289A-page 114
Preliminary
© 2007 Microchip Technology Inc.
PIC24HJ32GP202/204 and PIC24HJ16GP304
REGISTER 9-22: RPOR7: PERIPHERAL PIN SELECT OUTPUT REGISTERS 12
U-0
—
U-0
—
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
bit 8
R/W-0
RP25R<4:0>
bit 15
U-0
—
U-0
—
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
RP24R<4:0>
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-13
bit 12-8
Unimplemented: Read as ‘0’
RP25R<4:0>: Peripheral Output Function is Assigned to RP25 Output Pin (see Table 9-2 for periph-
eral function numbers)
bit 7-5
bit 4-0
Unimplemented: Read as ‘0’
RP24R<4:0>: Peripheral Output Function is Assigned to RP24 Output Pin (see Table 9-2 for periph-
eral function numbers)
© 2007 Microchip Technology Inc.
Preliminary
DS70289A-page 115
PIC24HJ32GP202/204 and PIC24HJ16GP304
NOTES:
DS70289A-page 116
Preliminary
© 2007 Microchip Technology Inc.
PIC24HJ32GP202/204 and PIC24HJ16GP304
Figure 10-1 shows a block diagram of the 16-bit timer
module.
10.0 TIMER1
Note:
This data sheet summarizes the features
of the PIC24HJ32GP202/204 and
PIC24HJ16GP304 devices. It is not
intended to be a comprehensive reference
source. To complement the information in
this data sheet, refer to the “PIC24H
Family Reference Manual”.
To configure Timer1 for operation:
1. Set the TON bit (= 1) in the T1CON register.
2. Select the timer prescaler ratio using the
TCKPS<1:0> bits in the T1CON register.
3. Set the Clock and Gating modes using the TCS
and TGATE bits in the T1CON register.
4. Set or clear the TSYNC bit in T1CON to select
synchronous or asynchronous operation.
The Timer1 module is a 16-bit timer, which can serve
as the time counter for the real-time clock, or operate
as a free-running interval timer/counter. Timer1 can
operate in three modes:
5. Load the timer period value into the PR1
register.
6. If interrupts are required, set the interrupt enable
bit, T1IE. Use the priority bits, T1IP<2:0>, to set
the interrupt priority.
• 16-bit Timer
• 16-bit Synchronous Counter
• 16-bit Asynchronous Counter
Timer1 also supports these features:
• Timer gate operation
• Selectable prescaler settings
• Timer operation during CPU Idle and Sleep
modes
• Interrupt on 16-bit Period register match or falling
edge of external gate signal
FIGURE 10-1:
16-BIT TIMER1 MODULE BLOCK DIAGRAM
TCKPS<1:0>
TON
2
SOSCO/
1x
01
00
T1CK
Prescaler
1, 8, 64, 256
Gate
Sync
SOSCEN
SOSCI
TCY
TGATE
TCS
TGATE
1
0
Q
Q
D
Set T1IF
CK
0
Reset
Equal
TMR1
1
Sync
TSYNC
Comparator
PR1
© 2007 Microchip Technology Inc.
Preliminary
DS70289A-page 117
PIC24HJ32GP202/204 and PIC24HJ16GP304
REGISTER 10-1: T1CON: TIMER1 CONTROL REGISTER
R/W-0
TON
U-0
—
R/W-0
TSIDL
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
bit 15
bit 8
bit 0
U-0
—
R/W-0
R/W-0
R/W-0
U-0
—
R/W-0
R/W-0
TCS
U-0
—
TGATE
TCKPS<1:0>
TSYNC
bit 7
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15
TON: Timer1 On bit
1= Starts 16-bit Timer1
0= Stops 16-bit Timer1
bit 14
bit 13
Unimplemented: Read as ‘0’
TSIDL: Stop in Idle Mode bit
1= Discontinue module operation when device enters Idle mode
0= Continue module operation in Idle mode
bit 12-7
bit 6
Unimplemented: Read as ‘0’
TGATE: Timer1 Gated Time Accumulation Enable bit
When T1CS = 1:
This bit is ignored.
When T1CS = 0:
1= Gated time accumulation enabled
0= Gated time accumulation disabled
bit 5-4
TCKPS<1:0> Timer1 Input Clock Prescale Select bits
11 = 1:256
10 = 1:64
01 = 1:8
00 = 1:1
bit 3
bit 2
Unimplemented: Read as ‘0’
TSYNC: Timer1 External Clock Input Synchronization Select bit
When TCS = 1:
1= Synchronize external clock input
0= Do not synchronize external clock input
When TCS = 0:
This bit is ignored.
bit 1
bit 0
TCS: Timer1 Clock Source Select bit
1= External clock from pin T1CK (on the rising edge)
0= Internal clock (FCY)
Unimplemented: Read as ‘0’
DS70289A-page 118
Preliminary
© 2007 Microchip Technology Inc.
PIC24HJ32GP202/204 and PIC24HJ16GP304
11.1 32-bit Operation
11.0 TIMER2/3 FEATURE
To configure the Timer2/3 feature for 32-bit operation:
1. Set the corresponding T32 control bit.
Note:
This data sheet summarizes the features
of the PIC24HJ32GP202/204 and
PIC24HJ16GP304 devices. It is not
intended to be a comprehensive reference
source. To complement the information in
this data sheet, refer to the “PIC24H
Family Reference Manual”.
2. Select the prescaler ratio for Timer2 using the
TCKPS<1:0> bits.
3. Set the Clock and Gating modes using the
corresponding TCS and TGATE bits.
4. Load the timer period value. PR3 contains the
Most Significant word of the value, while PR2
contains the Least Significant word.
The Timer2/3 feature has 32-bit timers that can also be
configured as two independent 16-bit timers with
selectable operating modes.
5. Set the interrupt enable bit T3IE, if interrupts are
required. Use the priority bits T3IP<2:0> to set
the interrupt priority. While Timer2 controls the
timer, the interrupt appears as a Timer3 inter-
rupt.
As a 32-bit timer, the Timer2/3 feature permits opera-
tion in three modes:
• Two Independent 16-bit timers (Timer2 and
Timer3) with all 16-bit operating modes (except
Asynchronous Counter mode)
6. Set the corresponding TON bit.
The timer value at any point is stored in the register pair
TMR3:TMR2. TMR3 always contains the Most Signifi-
cant word of the count, while TMR2 contains the Least
Significant word.
• Single 32-bit timer (Timer2/3)
• Single 32-bit synchronous counter (Timer2/3)
The Timer2/3 feature also supports:
• Timer gate operation
To configure any of the timers for individual 16-bit
operation:
• Selectable Prescaler Settings
• Timer operation during Idle and Sleep modes
• Interrupt on a 32-bit Period Register Match
1. Clear the T32 bit corresponding to that timer.
2. Select the timer prescaler ratio using the
TCKPS<1:0> bits.
• Time Base for Input Capture and Output Compare
Modules (Timer2 and Timer3 only)
3. Set the Clock and Gating modes using the TCS
and TGATE bits.
• ADC1 Event Trigger (Timer2/3 only)
Individually, all eight of the 16-bit timers can function as
synchronous timers or counters. They also offer the
features that are listed above, except for the event trig-
ger. The operating modes and enabled features are
determined by setting the appropriate bit(s) in the
T2CON and T3CON registers. T2CON registers are
shown in generic form in Register 11-1. T3CON regis-
ters are shown in Register 11-2.
4. Load the timer period value into the PRx
register.
5. If interrupts are required, set the interrupt enable
bit, TxIE. Use the priority bits, TxIP<2:0>, to set
the interrupt priority.
6. Set the TON bit.
For 32-bit timer/counter operation, Timer2 is the Least
Significant word, and Timer3 is the Most Significant
word of the 32-bit timers.
Note:
For 32-bit operation, T3CON control bits
are ignored. Only T2CON control bit is
used for setup and control. Timer2 clock
and gate inputs are used for the 32-bit
timer modules, but an interrupt is gener-
ated with the Timer3 interrupt flags.
© 2007 Microchip Technology Inc.
Preliminary
DS70289A-page 119
PIC24HJ32GP202/204 and PIC24HJ16GP304
FIGURE 11-1:
TIMER2/3 (32-BIT) BLOCK DIAGRAM(1)
TCKPS<1:0>
2
TON
1x
01
00
T2CK
Gate
Sync
Prescaler
1, 8, 64, 256
TCY
TGATE
TCS
TGATE
1
Q
Q
D
Set T3IF
CK
0
PR2
PR3
(2)
ADC Event Trigger
Equal
Reset
Comparator
MSb
LSb
TMR3
TMR2
Sync
16
Read TMR2
Write TMR2
16
16
TMR3HLD
16
Data Bus<15:0>
Note 1: The 32-bit timer control bit, T32, must be set for 32-bit timer/counter operation. All control bits are respective
to the T2CON register.
2: The ADC event trigger is available only on Timer2/3.
DS70289A-page 120
Preliminary
© 2007 Microchip Technology Inc.
PIC24HJ32GP202/204 and PIC24HJ16GP304
FIGURE 11-2:
TIMER2 (16-BIT) BLOCK DIAGRAM
TCKPS<1:0>
2
TON
T2CK
1x
01
00
Prescaler
1, 8, 64, 256
Gate
Sync
TGATE
TCS
TGATE
TCY
1
0
Q
Q
D
Set T2IF
CK
Reset
Equal
TMR2
Sync
Comparator
PR2
© 2007 Microchip Technology Inc.
Preliminary
DS70289A-page 121
PIC24HJ32GP202/204 and PIC24HJ16GP304
REGISTER 11-1: T2CON CONTROL REGISTER
R/W-0
TON
U-0
—
R/W-0
TSIDL
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
bit 15
bit 8
bit 0
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
T32(1)
U-0
—
R/W-0
TCS
U-0
—
TGATE
TCKPS<1:0>
bit 7
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15
TON: Timer2 On bit
When T32 = 1:
1= Starts 32-bit Timer2/3
0= Stops 32-bit Timer2/3
When T32 = 0:
1= Starts 16-bit Timer2
0= Stops 16-bit Timer2
bit 14
bit 13
Unimplemented: Read as ‘0’
TSIDL: Stop in Idle Mode bit
1= Discontinue module operation when device enters Idle mode
0= Continue module operation in Idle mode
bit 12-7
bit 6
Unimplemented: Read as ‘0’
TGATE: Timer2 Gated Time Accumulation Enable bit
When TCS = 1:
This bit is ignored.
When TCS = 0:
1= Gated time accumulation enabled
0= Gated time accumulation disabled
bit 5-4
bit 3
TCKPS<1:0>: Timer2 Input Clock Prescale Select bits
11= 1:256
10= 1:64
01= 1:8
00= 1:1
T32: 32-bit Timer Mode Select bit(1)
1= Timer2 and Timer3 form a single 32-bit timer
0= Timer2 and Timer3 act as two 16-bit timers
bit 2
bit 1
Unimplemented: Read as ‘0’
TCS: Timer2 Clock Source Select bit
1= External clock from pin T2CK (on the rising edge)
0= Internal clock (FCY)
bit 0
Unimplemented: Read as ‘0’
Note 1: In 32-bit mode, T3CON control bits do not affect 32-bit timer operation.
DS70289A-page 122
Preliminary
© 2007 Microchip Technology Inc.
PIC24HJ32GP202/204 and PIC24HJ16GP304
REGISTER 11-2: T3CON CONTROL REGISTER
R/W-0
TON(1)
U-0
—
R/W-0
TSIDL(1)
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
bit 15
bit 8
bit 0
U-0
—
R/W-0
TGATE(1)
R/W-0
TCKPS<1:0>(1)
R/W-0
U-0
—
U-0
—
R/W-0
TCS(1)
U-0
—
bit 7
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
-n = Value at POR
bit 15
TON: Timer3 On bit(1)
1= Starts 16-bit Timer3
0= Stops 16-bit Timer3
bit 14
bit 13
Unimplemented: Read as ‘0’
TSIDL: Stop in Idle Mode bit(1)
1= Discontinue module operation when device enters Idle mode
0= Continue module operation in Idle mode
bit 12-7
bit 6
Unimplemented: Read as ‘0’
TGATE: Timer3 Gated Time Accumulation Enable bit(1)
When TCS = 1:
This bit is ignored.
When TCS = 0:
1= Gated time accumulation enabled
0= Gated time accumulation disabled
bit 5-4
TCKPS<1:0>: Timer3 Input Clock Prescale Select bits(1)
11= 1:256
10= 1:64
01= 1:8
00= 1:1
bit 3-2
bit 1
Unimplemented: Read as ‘0’
TCS: Timer3 Clock Source Select bit(1)
1= External clock from pin T3CK (on the rising edge)
0= Internal clock (FCY)
bit 0
Unimplemented: Read as ‘0’
Note 1: When 32-bit operation is enabled (T2CON<3> = 1), these bits have no effect on Timer3 operation; all
timer functions are set through T2CON.
© 2007 Microchip Technology Inc.
Preliminary
DS70289A-page 123
PIC24HJ32GP202/204 and PIC24HJ16GP304
NOTES:
DS70289A-page 124
Preliminary
© 2007 Microchip Technology Inc.
PIC24HJ32GP202/204 and PIC24HJ16GP304
• Prescaler Capture Event modes:
12.0 INPUT CAPTURE
- Capture timer value on every 4th rising edge
of input at ICx pin
Note:
This data sheet summarizes the features
of the PIC24HJ32GP202/204 and
PIC24HJ16GP304 devices. It is not
intended to be a comprehensive reference
source. To complement the information in
this data sheet, refer to the “PIC24H
Family Reference Manual”.
-Capture timer value on every 16th rising
edge of input at ICx pin
Each input capture channel can select one of the
two 16-bit timers (Timer2 or Timer3) for the time
base. The selected timer can use either an internal
or external clock.
The input capture module is useful in applications
requiring frequency (period) and pulse measurement.
The PIC24HJ32GP202/204 and PIC24HJ16GP304
devices support up to eight input capture channels.
Other operational features include:
• Device wake-up from capture pin during CPU
Sleep and Idle modes
• Interrupt on input capture event
The input capture module captures the 16-bit value of
the selected Time Base register when an event occurs
at the ICx pin. The events that cause a capture event
are listed below in three categories:
• Four-word FIFO buffer for capture values
- Interrupt optionally generated after 1, 2, 3 or
4 buffer locations are filled
• Use of input capture to provide additional sources
of external interrupts
• Simple Capture Event modes:
- Capture timer value on every falling edge of
input at ICx pin
- Capture timer value on every rising edge of
input at ICx pin
• Capture timer value on every edge (rising and
falling)
FIGURE 12-1:
INPUT CAPTURE BLOCK DIAGRAM
From 16-bit Timers
TMR2 TMR3
16
16
ICTMR
(ICxCON<7>)
1
0
Edge Detection Logic
and
Clock Synchronizer
FIFO
R/W
Logic
Prescaler
Counter
(1, 4, 16)
ICx Pin
ICM<2:0> (ICxCON<2:0>)
3
Mode Select
ICOV, ICBNE (ICxCON<4:3>)
ICxBUF
ICxI<1:0>
Interrupt
Logic
ICxCON
System Bus
Set Flag ICxIF
(in IFSn Register)
Note: An ‘x’ in a signal, register or bit name denotes the number of the capture channel.
© 2007 Microchip Technology Inc.
Preliminary
DS-70289A-page 125
PIC24HJ32GP202/204 and PIC24HJ16GP304
12.1 Input Capture Registers
REGISTER 12-1: ICxCON: INPUT CAPTURE x CONTROL REGISTER
U-0
—
U-0
—
R/W-0
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
ICSIDL
bit 15
bit 8
R/W-0
R/W-0
R/W-0
R-0, HC
ICOV
R-0, HC
ICBNE
R/W-0
R/W-0
R/W-0
bit 0
ICTMR
ICI<1:0>
ICM<2:0>
bit 7
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-14
bit 13
Unimplemented: Read as ‘0’
ICSIDL: Input Capture Module Stop in Idle Control bit
1= Input capture module will halt in CPU Idle mode
0= Input capture module will continue to operate in CPU Idle mode
bit 12-8
bit 7
Unimplemented: Read as ‘0’
ICTMR: Input Capture Timer Select bits
1= TMR2 contents are captured on capture event
0= TMR3 contents are captured on capture event
bit 6-5
ICI<1:0>: Select Number of Captures per Interrupt bits
11= Interrupt on every fourth capture event
10= Interrupt on every third capture event
01= Interrupt on every second capture event
00= Interrupt on every capture event
bit 4
ICOV: Input Capture Overflow Status Flag bit (read-only)
1= Input capture overflow occurred
0= No input capture overflow occurred
bit 3
ICBNE: Input Capture Buffer Empty Status bit (read-only)
1= Input capture buffer is not empty, at least one more capture value can be read
0= Input capture buffer is empty
bit 2-0
ICM<2:0>: Input Capture Mode Select bits
111=Input capture functions as interrupt pin only when device is in Sleep or Idle mode
(Rising edge detect only, all other control bits are not applicable.)
110=Unused (module disabled)
101=Capture mode, every 16th rising edge
100=Capture mode, every 4th rising edge
011=Capture mode, every rising edge
010=Capture mode, every falling edge
001=Capture mode, every edge (rising and falling)
(ICI<1:0> bits do not control interrupt generation for this mode.)
000=Input capture module turned off
DS-70289A-page 126
Preliminary
© 2007 Microchip Technology Inc.
PIC24HJ32GP202/204 and PIC24HJ16GP304
the TMRy register, are not required, but may be
advantageous for defining a pulse from a known
event time boundary.
13.0 OUTPUT COMPARE
Note:
This data sheet summarizes the features
of the PIC24HJ32GP202/204 and
PIC24HJ16GP304 devices. It is not
intended to be a comprehensive reference
source. To complement the information in
this data sheet, refer to the “PIC24H
Family Reference Manual”.
The output compare module does not have to be
disabled after the falling edge of the output
pulse. Another pulse can be initiated by rewriting
the value of the OCxCON register.
13.2 Setup for Continuous Output
Pulse Generation
13.1 Setup for Single Output Pulse
Generation
When the OCM control bits (OCxCON<2:0>) are set to
‘101’, the selected output compare channel initializes
the OCx pin to the low state and generates output
pulses on each and every compare match event.
When the OCM control bits (OCxCON<2:0>) are set to
‘100’, the selected output compare channel initializes
the OCx pin to the low state and generates a single
output pulse.
To configure the module to generate a continuous
stream of output pulses, the following steps are
required. These steps assume that the timer source is
initially turned off but this is not a requirement for the
module operation.
To generate a single output pulse, the following steps
are required. These steps assume timer source is
initially turned off though this is not a requirement for
the module operation.
1. Determine the instruction clock cycle time. Take
into account the frequency of the external clock to
the timer source (if one is used) and the timer
prescaler settings.
1. Determine the instruction clock cycle time. Take
into account the frequency of the external clock to
the timer source (if one is used) and the timer
prescaler settings.
2. Calculate time to the rising edge of the output
pulse relative to the TMRy start value (0000h).
2. Calculate time to the rising edge of the output
pulse relative to the TMRy start value (0000h).
3. Calculate the time to the falling edge of the pulse
based on the desired pulse width and the time to
the rising edge of the pulse.
3. Calculate the time to the falling edge of the pulse,
based on the desired pulse width and the time to
the rising edge of the pulse.
4. Write the value computed in step 2 into the Output
Compare register, OCxR, and the value computed
in step 3 into the Output Compare Secondary reg-
ister, OCxRS.
4. Write the values computed in step 2 into the Out-
put Compare register, OCxR, and value computed
in step 3 into the Output Compare Secondary reg-
ister, OCxRS.
5. Set Timer Period register, PRy, to a value equal to
or greater than value in OCxRS, the Output
Compare Secondary register.
5. Set Timer Period register, PRy, to a value equal to
or greater than value in OCxRS, the Output
Compare Secondary Register.
6. Set the OCM bits to ‘100’ and the OCTSEL
(OCxCON<3>) bit to the desired timer source. The
OCx pin state will now be driven low.
6. Set the OCM bits to ‘101’ and the OCTSEL bit to
the desired timer source. The OCx pin state will
now be driven low.
7. Set the TON (TyCON<15>) bit to ‘1’, which
enables the compare time base to count. Upon the
first match between TMRy and OCxR, the OCx pin
will be driven high.
7. Enable the compare time base by setting the TON
(TyCON<15>) bit to ‘1’. Upon the first match
between TMRy and OCxR, the OCx pin will be
driven high.
When the incrementing timer, TMRy, matches the
Output Compare Secondary register, OCxRS, the
second and trailing edge (high-to-low) of the pulse
is driven onto the OCx pin. No additional pulses
are driven onto the OCx pin and it remains at low.
As a result of the second compare match event,
the OCxIF interrupt flag bit is set. This results in an
interrupt if it is enabled by setting the OCxIE bit.
For further information on peripheral interrupts,
refer to Section 6.0 “Interrupt Controller”.
When the compare time base, TMRy, matches the
Output Compare Secondary register, OCxRS, the
second and trailing edge (high-to-low) of the pulse
is driven onto the OCx pin.
8. As a result of the second compare match event,
the OCxIF interrupt flag bit is set.
When the compare time base and the value in its
respective Timer Period register match, the TMRy
register resets to 0x0000 and resumes counting.
8. change the Timer and Compare register settings
to initiate another single pulse output, if needed;
and then issue a write to set the OCM bits to ‘100’.
Disabling and re-enabling the timer, and clearing
9. Steps 8 through 11 are repeated and a continuous
stream of pulses is generated, indefinitely. The
OCxIF flag is set on each OCxRS-TMRy compare
match event.
© 2007 Microchip Technology Inc.
Preliminary
DS70289A-page 127
PIC24HJ32GP202/204 and PIC24HJ16GP304
EQUATION 13-1: CALCULATING THE PWM
PERIOD
13.3 Pulse-Width Modulation Mode
Use the following steps when configuring the output
compare module for PWM operation:
PWM Period = [(PRy) + 1] • TCY • (Timer Prescale Value)
where:
1. Set the PWM period by writing to the selected
Timer Period register (PRy).
PWM Frequency = 1/[PWM Period]
2. Set the PWM duty cycle by writing to the OCxRS
register.
Note: A PRy value of N will produce a PWM
period of N + 1 time base count cycles. For
example, a value of 7 written into the PRy
register will yield a period consisting of
eight time base cycles.
3. Write the OxCR register with the initial duty cycle.
4. Enable interrupts, if required, for the timer and
output compare modules. The output compare
interrupt is required for PWM Fault pin utilization.
5. Configure the output compare module for one of
the two PWM operation modes by writing to the
Output Compare Mode bits, OCM<2:0> and
(OCxCON<2:0>).
13.3.2
PWM DUTY CYCLE
Specify the PWM duty cycle by writing to the OCxRS
register. The OCxRS register can be written to at any
time, but the duty cycle value is not latched into OCxR
until a match between PRy and TMRy occurs (i.e., the
period is complete). This provides a double buffer for
the PWM duty cycle and is essential for glitchless PWM
operation. In the PWM mode, OCxR is a read-only reg-
ister.
6. Set the TMRy prescale value and enable the
time base by setting TON = 1(TxCON<15>)
Note: The OCxR register should be initialized
before the output compare module is first
enabled. The OCxR register becomes a
read-only duty cycle register when the
module is operated in the PWM modes.
The value held in OCxR will become the
PWM duty cycle for the first PWM period.
The contents of the Output Compare
Secondary register, OCxRS, will not be
transferred into OCxR until a time base
period match occurs.
Some important boundary parameters of the PWM duty
cycle include:
• If the Output Compare register, OCxR, is loaded
with 0000h, the OCx pin will remain low (0% duty
cycle).
• If OCxR is greater than PRy (Timer Period register),
the pin will remain high (100% duty cycle).
• If OCxR is equal to PRy, the OCx pin will be low
for one time base count value and high for all
other count values.
See Example 13-1 for PWM mode timing details.
Table 13-1 shows an example of PWM frequencies and
resolutions for a device operating at 10 MIPS.
13.3.1
PWM PERIOD
The PWM period is specified by writing to PRy, the
Timer Period register. The PWM period can be
calculated using Equation 13-1:
EQUATION 13-2: CALCULATION FOR MAXIMUM PWM RESOLUTION
FCY
log10
(FPWM )
bits
Maximum PWM Resolution (bits) =
log10(2)
DS70289A-page 128
Preliminary
© 2007 Microchip Technology Inc.
PIC24HJ32GP202/204 and PIC24HJ16GP304
EXAMPLE 13-1:
PWM PERIOD AND DUTY CYCLE CALCULATIONS
1. Find the Timer Period register value for a desired PWM frequency that is 52.08 kHz, where FCY = 16 MHz and a Timer2
prescaler setting of 1:1.
TCY
= 62.5 ns
PWM Period = 1/PWM Frequency = 1/52.08 kHz = 19.2 ms
PWM Period = (PR2 + 1) • TCY • (Timer2 Prescale Value)
19.2 ms
PR2
= (PR2 + 1) • 62.5 ns • 1
= 306
2. Find the maximum resolution of the duty cycle that can be used with a 52.08 kHz frequency and a 32 MHz device clock rate:
PWM Resolution
=
=
=
log10(FCY/FPWM)/log102) bits
(log10(16 MHz/52.08 kHz)/log102) bits
8.3 bits
TABLE 13-1: EXAMPLE PWM FREQUENCIES AND RESOLUTIONS AT 4 MIPS (FCY = 4 MHz)
PWM Frequency
7.6 Hz
61 Hz
122 Hz
977 Hz
3.9 kHz
31.3 kHz
125 kHz
Timer Prescaler Ratio
Period Register Value
Resolution (bits)
8
1
FFFFh
16
1
1
1
1
007Fh
7
1
001Fh
5
FFFFh
16
7FFFh
15
0FFFh
12
03FFh
10
TABLE 13-2: EXAMPLE PWM FREQUENCIES AND RESOLUTIONS AT 16 MIPS (FCY = 16 MHz)
PWM Frequency
30.5 Hz
244 Hz
488 Hz
3.9 kHz
15.6 kHz
125 kHz
500 kHz
Timer Prescaler Ratio
Period Register Value
Resolution (bits)
8
1
FFFFh
16
1
1
1
1
007Fh
7
1
001Fh
5
FFFFh
16
7FFFh
15
0FFFh
12
03FFh
10
TABLE 13-3: EXAMPLE PWM FREQUENCIES AND RESOLUTIONS AT 40 MIPS (FCY = 40 MHz)
PWM Frequency
76 Hz
610 Hz
1.22 Hz
9.77 kHz
39 kHz
313 kHz 1.25 MHz
Timer Prescaler Ratio
Period Register Value
Resolution (bits)
8
1
FFFFh
16
1
1
1
1
007Fh
7
1
001Fh
5
FFFFh
16
7FFFh
15
0FFFh
12
03FFh
10
© 2007 Microchip Technology Inc.
Preliminary
DS70289A-page 129
PIC24HJ32GP202/204 and PIC24HJ16GP304
FIGURE 13-1:
OUTPUT COMPARE MODULE BLOCK DIAGRAM
Set Flag bit
(1)
OCxIF
(1)
OCxRS
S
R
Q
Output
Logic
(1)
(1)
OCxR
OCx
Output Enable
3
OCM2:OCM0
Mode Select
OCFA
Comparator
0
OCTSEL
1
0
1
16
16
TMR register inputs
from time bases
Period match signals
from time bases
(3)
(3)
Note 1: Where ‘x’ is shown, reference is made to the registers associated with the respective output compare channels 1
through 8.
2: OCFA pin controls OC1-OC2 channels.
3: TMR2/TMR3 can be selected via OCTSEL(OCxOCN<3>) bit.
DS70289A-page 130
Preliminary
© 2007 Microchip Technology Inc.
PIC24HJ32GP202/204 and PIC24HJ16GP304
13.4 Output Compare Register
REGISTER 13-1: OCxCON: OUTPUT COMPARE x CONTROL REGISTER
U-0
—
U-0
—
R/W-0
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
OCSIDL
bit 15
bit 8
R/W-0
bit 0
U-0
—
U-0
—
U-0
—
R-0 HC
OCFLT
R/W-0
R/W-0
R/W-0
OCTSEL
OCM<2:0>
bit 7
Legend:
HC = Cleared in Hardware
W = Writable bit
HS = Set in Hardware
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
R = Readable bit
-n = Value at POR
‘1’ = Bit is set
bit 15-14
bit 13
Unimplemented: Read as ‘0’
OCSIDL: Stop Output Compare in Idle Mode Control bit
1= Output Compare x will halt in CPU Idle mode
0= Output Compare x will continue to operate in CPU Idle mode
bit 12-5
bit 4
Unimplemented: Read as ‘0’
OCFLT: PWM Fault Condition Status bit
1= PWM Fault condition has occurred (cleared in hardware only)
0= No PWM Fault condition has occurred
(This bit is only used when OCM<2:0> = 111.)
bit 3
OCTSEL: Output Compare Timer Select bit
1= Timer3 is the clock source for Compare x
0= Timer2 is the clock source for Compare x
bit 2-0
OCM<2:0>: Output Compare Mode Select bits
111= PWM mode on OCx, Fault pin enabled
110= PWM mode on OCx, Fault pin disabled
101= Initialize OCx pin low, generate continuous output pulses on OCx pin
100= Initialize OCx pin low, generate single output pulse on OCx pin
011= Compare event toggles OCx pin
010= Initialize OCx pin high, compare event forces OCx pin low
001= Initialize OCx pin low, compare event forces OCx pin high
000= Output compare channel is disabled
© 2007 Microchip Technology Inc.
Preliminary
DS70289A-page 131
PIC24HJ32GP202/204 and PIC24HJ16GP304
NOTES:
DS70289A-page 132
Preliminary
© 2007 Microchip Technology Inc.
PIC24HJ32GP202/204 and PIC24HJ16GP304
14.3 Transmit Operations
14.0 SERIAL PERIPHERAL
INTERFACE (SPI)
Transmit writes are also double-buffered. The user appli-
cation writes to SPIxBUF. When the Master or Slave
transfer is completed, the contents of the shift register
(SPIxSR) are moved to the receive buffer. If any transmit
data has been written to the buffer register, the contents
of the transmit buffer are moved to SPIxSR. The received
data is thus placed in SPIxBUF and the transmit data in
SPIxSR is ready for the next transfer.
Note:
This data sheet summarizes the features
of the PIC24HJ32GP202/204 and
PIC24HJ16GP304 devices. It is not
intended to be a comprehensive reference
source. To complement the information in
this data sheet, refer to the “PIC24H
Family Reference Manual”.
Note:
Both the transmit buffer (SPIxTXB) and
the receive buffer (SPIxRXB) are mapped
to the same register address, SPIxBUF.
Do not perform read-modify-write opera-
tions (such as bit-oriented instructions) on
the SPIxBUF register.
The Serial Peripheral Interface (SPI) module is a
synchronous serial interface useful for communicating
with other peripheral or microcontroller devices. These
peripheral devices can be serial EEPROMs, shift
registers, display drivers, Analog-to-Digital Converters
(ADC) and so on. The SPI module is compatible with
SPI and SIOP from Motorola®.
14.4 SPI Setup
Each SPI module consists of a 16-bit shift register,
SPIxSR (where x = 1 or 2), used for shifting data in and
out, and a buffer register, SPIxBUF. A control register,
SPIxCON, configures the module. Additionally, a status
register, SPIxSTAT, indicates status conditions.
To set up the SPI module for the Master mode of
operation:
1. If using interrupts:
a) Clear the SPIxIF bit in the respective IFSn
register.
The serial interface consists of 4 pins:
• SDIx (serial data input)
b) Set the SPIxIE bit in the respective IECn
register.
• SDOx (serial data output)
• SCKx (shift clock input or output)
• SSx (active low slave select).
c) Write the SPIxIP bits in the respective IPCn
register to set the interrupt priority.
In Master mode operation, SCK is a clock output. In
Slave mode, it is a clock input.
2. Write the desired settings to the SPIxCON
register with MSTEN (SPIxCON1<5>) = 1.
3. Clear the SPIROV bit (SPIxSTAT<6>).
14.1 Interrupts
4. Enable SPI operation by setting the SPIEN bit
(SPIxSTAT<15>).
A series of 8 or 16 clock pulses shift out bits from the
SPIxSR to SDOx pin and simultaneously shift in data
from the SDIx pin. An interrupt is generated when the
transfer is complete and the corresponding interrupt flag
bit (SPI1IF) is set. This interrupt can be disabled through
an interrupt enable bit (SPI1IE).
5. Write the data to be transmitted to the SPIxBUF
register. Transmission (and reception) will start as
soon as data is written to the SPIxBUF register.
To set up the SPI module for the Slave mode of operation:
1. Clear the SPIxBUF register.
2. If using interrupts:
14.2 Receive Operations
a) Clear the SPIxIF bit in the respective IFSn
register.
The receive operation is double-buffered. When a com-
plete byte is received, it is transferred from SPIxSR to
SPIxBUF.
b) Set the SPIxIE bit in the respective IECn
register.
If the receive buffer is full when new data is being trans-
ferred from SPIxSR to SPIxBUF, the module sets the
SPIROV bit, indicating an overflow condition. The trans-
fer of the data from SPIxSR to SPIxBUF is not com-
pleted, and the new data is lost. The module will not
respond to SCL transitions while SPIROV is ‘1’, effec-
tively disabling the module until SPIxBUF is read by user
software.
c) Write the SPIxIP bits in the respective IPCn
register to set the interrupt priority.
3. Write the desired settings to the SPIxCON1
and SPIxCON2 registers with MSTEN
(SPIxCON1<5>) = 0.
4. Clear the SMP bit.
5. If the CKE bit is set, then set the SSEN bit
(SPIxCON1<7>) to enable the SSx pin.
6. Clear the SPIROV bit (SPIxSTAT<6>).
7. Enable SPI operation by setting the SPIEN bit
(SPIxSTAT<15>).
© 2007 Microchip Technology Inc.
Preliminary
DS70289A-page 133
PIC24HJ32GP202/204 and PIC24HJ16GP304
The SPI module generates an interrupt indicating com-
pletion of a byte or word transfer, as well as a separate
interrupt for all SPI error conditions.
FIGURE 14-1:
SPI MODULE BLOCK DIAGRAM
SCKx
1:1 to 1:8
Secondary
Prescaler
1:1/4/16/64
Primary
Prescaler
FCY
SSx
Sync
Control
Select
Edge
Control
Clock
SPIxCON1<1:0>
SPIxCON1<4:2>
Shift Control
SDOx
SDIx
Enable
Master Clock
bit 0
SPIxSR
Transfer
Transfer
SPIxRXB SPIxTXB
SPIxBUF
Write SPIxBUF
Read SPIxBUF
16
Internal Data Bus
DS70289A-page 134
Preliminary
© 2007 Microchip Technology Inc.
PIC24HJ32GP202/204 and PIC24HJ16GP304
FIGURE 14-2:
SPI MASTER/SLAVE CONNECTION
PROCESSOR 1 (SPI Master)
PROCESSOR 2 (SPI Slave)
SDOx
SDIx
Serial Receive Buffer
(SPIxRXB)
Serial Receive Buffer
(SPIxRXB)
SDIx
SDOx
Shift Register
(SPIxSR)
Shift Register
(SPIxSR)
LSb
MSb
MSb
LSb
Serial Transmit Buffer
(SPIxTXB)
Serial Transmit Buffer
(SPIxTXB)
Serial Clock
SCKx
SCKx
SSx(1)
SPI Buffer
SPI Buffer
(SPIxBUF)(2)
(SPIxBUF)(2)
(MSTEN (SPIxCON1<5>) = 1)
(SSEN (SPIxCON1<7>) = 1and MSTEN (SPIxCON1<5>) = 0)
Note 1: Using the SSx pin in Slave mode of operation is optional.
2: User application must write transmit data to read received data from SPIxBUF. The SPIxTXB and SPIxRXB registers
are memory mapped to SPIxBUF.
FIGURE 14-3:
SPI MASTER AND FRAME MASTER CONNECTION DIAGRAM
PIC24H
PROCESSOR 2
SDIx
SDOx
SDIx
SDOx
Serial Clock
SCKx
SSx
SCKx
SSx
Frame Sync
Pulse
FIGURE 14-4:
SPI MASTER AND FRAME SLAVE CONNECTION DIAGRAM
PIC24H
PROCESSOR 2
SDOx
SDIx
SDIx
SDOx
Serial Clock
SCKx
SSx
SCKx
SSx
Frame Sync
Pulse
© 2007 Microchip Technology Inc.
Preliminary
DS70289A-page 135
PIC24HJ32GP202/204 and PIC24HJ16GP304
FIGURE 14-5:
SPI SLAVE AND FRAME MASTER CONNECTION DIAGRAM
PIC24H
PROCESSOR 2
SDOx
SDIx
SDIx
SDOx
Serial Clock
SCKx
SSx
SCKx
SSx
Frame Sync
Pulse
FIGURE 14-6:
SPI SLAVE, FRAME SLAVE CONNECTION DIAGRAM
PIC24H
PROCESSOR 2
SDOx
SDIx
SDIx
SDOx
Serial Clock
SCKx
SSx
SCKx
SSx
Frame Sync
Pulse
EQUATION 14-1: RELATIONSHIP BETWEEN DEVICE AND SPI CLOCK SPEED
FCY
FSCK =
Primary Prescaler * Secondary Prescaler
TABLE 14-1: SAMPLE SCKx FREQUENCIES
Secondary Prescaler Settings
FCY = 40 MHz
1:1
2:1
4:1
6:1
8:1
Primary Prescaler Settings
1:1
4:1
Invalid
10000
2500
625
Invalid
5000
10000
2500
6666.67
1666.67
416.67
104.17
5000
1250
16:1
64:1
1250
625
312.50
78.125
312.5
156.25
FCY = 5 MHz
Primary Prescaler Settings
1:1
4:1
5000
1250
313
78
2500
625
156
39
1250
313
78
833
208
52
625
156
39
16:1
64:1
20
13
10
Note: SCKx frequencies shown in kHz.
DS70289A-page 136
Preliminary
© 2007 Microchip Technology Inc.
PIC24HJ32GP202/204 and PIC24HJ16GP304
REGISTER 14-1: SPIxSTAT: SPIx STATUS AND CONTROL REGISTER
R/W-0
SPIEN
U-0
—
R/W-0
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
SPISIDL
bit 15
bit 8
U-0
—
R/C-0
U-0
—
U-0
—
U-0
—
U-0
—
R-0
R-0
SPIROV
SPITBF
SPIRBF
bit 0
bit 7
Legend:
C = Clearable bit
W = Writable bit
‘1’ = Bit is set
R = Readable bit
-n = Value at POR
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15
SPIEN: SPIx Enable bit
1= Enables module and configures SCKx, SDOx, SDIx and SSx as serial port pins
0= Disables module
bit 14
bit 13
Unimplemented: Read as ‘0’
SPISIDL: Stop in Idle Mode bit
1= Discontinue module operation when device enters Idle mode
0= Continue module operation in Idle mode
bit 12-7
bit 6
Unimplemented: Read as ‘0’
SPIROV: Receive Overflow Flag bit
1= A new byte/word is completely received and discarded. The user software has not read the
previous data in the SPIxBUF register.
0= No overflow has occurred.
bit 5-2
bit 1
Unimplemented: Read as ‘0’
SPITBF: SPIx Transmit Buffer Full Status bit
1= Transmit not yet started, SPIxTXB is full
0= Transmit started, SPIxTXB is empty
Automatically set in hardware when CPU writes SPIxBUF location, loading SPIxTXB
Automatically cleared in hardware when SPIx module transfers data from SPIxTXB to SPIxSR
bit 0
SPIRBF: SPIx Receive Buffer Full Status bit
1= Receive complete, SPIxRXB is full
0= Receive is not complete, SPIxRXB is empty
Automatically set in hardware when SPIx transfers data from SPIxSR to SPIxRXB
Automatically cleared in hardware when core reads SPIxBUF location, reading SPIxRXB
© 2007 Microchip Technology Inc.
Preliminary
DS70289A-page 137
PIC24HJ32GP202/204 and PIC24HJ16GP304
REGISTER 14-2: SPIXCON1: SPIx CONTROL REGISTER 1
U-0
—
U-0
—
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
SMP
R/W-0
CKE(1)
DISSCK
DISSDO
MODE16
bit 15
bit 8
R/W-0
SSEN
R/W-0
CKP
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
MSTEN
SPRE<2:0>
PPRE<1:0>
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-13
bit 12
Unimplemented: Read as ‘0’
DISSCK: Disable SCKx pin bit (SPI Master modes only)
1= Internal SPI clock is disabled, pin functions as I/O
0= Internal SPI clock is enabled
bit 11
bit 10
bit 9
DISSDO: Disable SDOx pin bit
1= SDOx pin is not used by module; pin functions as I/O
0= SDOx pin is controlled by the module
MODE16: Word/Byte Communication Select bit
1= Communication is word-wide (16 bits)
0= Communication is byte-wide (8 bits)
SMP: SPIx Data Input Sample Phase bit
Master mode:
1= Input data sampled at end of data output time
0= Input data sampled at middle of data output time
Slave mode:
SMP must be cleared when SPIx is used in Slave mode.
bit 8
bit 7
bit 6
bit 5
CKE: SPIx Clock Edge Select bit(1)
1= Serial output data changes on transition from active clock state to Idle clock state (see bit 6)
0= Serial output data changes on transition from Idle clock state to active clock state (see bit 6)
SSEN: Slave Select Enable bit (Slave mode)
1= SSx pin used for Slave mode
0= SSx pin not used by module. Pin controlled by port function.
CKP: Clock Polarity Select bit
1= Idle state for clock is a high level; active state is a low level
0= Idle state for clock is a low level; active state is a high level
MSTEN: Master Mode Enable bit
1= Master mode
0= Slave mode
Note 1: The CKE bit is not used in the Framed SPI modes. Program this bit to ‘0’ for the Framed SPI modes
(FRMEN = 1).
DS70289A-page 138
Preliminary
© 2007 Microchip Technology Inc.
PIC24HJ32GP202/204 and PIC24HJ16GP304
REGISTER 14-2: SPIXCON1: SPIx CONTROL REGISTER 1 (CONTINUED)
bit 4-2
SPRE<2:0>: Secondary Prescale bits (Master mode)
111= Secondary prescale 1:1
110= Secondary prescale 2:1
•
•
•
000= Secondary prescale 8:1
bit 1-0
PPRE<1:0>: Primary Prescale bits (Master mode)
11= Primary prescale 1:1
10= Primary prescale 4:1
01= Primary prescale 16:1
00= Primary prescale 64:1
Note 1: The CKE bit is not used in the Framed SPI modes. Program this bit to ‘0’ for the Framed SPI modes
(FRMEN = 1).
© 2007 Microchip Technology Inc.
Preliminary
DS70289A-page 139
PIC24HJ32GP202/204 and PIC24HJ16GP304
REGISTER 14-3: SPIxCON2: SPIx CONTROL REGISTER 2
R/W-0
R/W-0
R/W-0
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
FRMEN
SPIFSD
FRMPOL
bit 15
bit 8
bit 0
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
R/W-0
U-0
—
FRMDLY
bit 7
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15
bit 14
bit 13
FRMEN: Framed SPIx Support bit
1= Framed SPIx support enabled (SSx pin used as frame sync pulse input/output)
0= Framed SPIx support disabled
SPIFSD: Frame Sync Pulse Direction Control bit
1= Frame sync pulse input (slave)
0= Frame sync pulse output (master)
FRMPOL: Frame Sync Pulse Polarity bit
1= Frame sync pulse is active-high
0= Frame sync pulse is active-low
bit 12-2
bit 1
Unimplemented: Read as ‘0’
FRMDLY: Frame Sync Pulse Edge Select bit
1= Frame sync pulse coincides with first bit clock
0= Frame sync pulse precedes first bit clock
bit 0
Unimplemented: This bit must not be set to ‘1’ by the user application.
DS70289A-page 140
Preliminary
© 2007 Microchip Technology Inc.
PIC24HJ32GP202/204 and PIC24HJ16GP304
2
15.2 I C Registers
15.0 INTER-INTEGRATED CIRCUIT
2
(I C)
I2CxCON and I2CxSTAT are control and status
registers, respectively. The I2CxCON register is
readable and writable. The lower six bits of I2CxSTAT
are read-only. The remaining bits of the I2CSTAT are
read/write.
Note:
This data sheet summarizes the features
of the PIC24HJ32GP202/204 and
PIC24HJ16GP304 devices. It is not
intended to be a comprehensive reference
source. To complement the information in
this data sheet, refer to the “PIC24H
Family Reference Manual”.
• I2CxRSR is the shift register used for shifting
data.
• I2CxRCV is the receive buffer and the register to
which data bytes are written, or from which data
bytes are read.
The Inter-Integrated Circuit (I2C) module provides
complete hardware support for both Slave and Multi-
Master modes of the I2C serial communication
standard, with a 16-bit interface.
• I2CxTRN is the transmit register to which bytes
are written during a transmit operation.
• The I2CxADD register holds the slave address.
The I2C module has a 2-pin interface:
• A status bit, ADD10, indicates 10-bit Address
mode.
• The SCLx pin is clock
• The SDAx pin is data.
The I2C module offers the following key features:
•
I2CxBRG acts as the Baud Rate Generator
(BRG) reload value.
• I2C interface supporting both Master and Slave
modes of operation.
• I2C Slave mode supports 7- and 10-bit address.
• I2C Master mode supports 7- and 10-bit address.
In receive operations, I2CxRSR and I2CxRCV together
form a double-buffered receiver. When I2CxRSR
receives a complete byte, it is transferred to I2CxRCV,
and an interrupt pulse is generated.
• I2C port allows bidirectional transfers between
master and slaves.
2
15.3 I C Interrupts
• Serial clock synchronization for I2C port can be
used as a handshake mechanism to suspend and
resume serial transfer (SCLREL control).
• I2C supports multi-master operation, detects bus
collision and arbitrates accordingly.
The I2C module generates two interrupt flags:
• MI2CxIF (I2C Master Events Interrupt flag)
• SI2CxIF (I2C Slave Events Interrupt flag).
A separate interrupt is generated for all I2C error condi-
tions.
15.1 Operating Modes
15.4 Baud Rate Generator
The hardware fully implements all the master and slave
functions of the I2C Standard and Fast mode
specifications, as well as 7 and 10-bit addressing.
In I2C Master mode, the reload value for the Baud Rate
Generator (BRG) is located in the I2CxBRG register.
When the BRG is loaded with this value, the BRG
counts down to zero and stops until another reload has
taken place. If clock arbitration is taking place, for
example, the BRG is reloaded when the SCLx pin is
sampled high.
As per the I2C standard, FSCL can be 100 kHz or
400 kHz. However, the user application can specify
any baud rate up to 1 MHz. I2CxBRG values of ‘0’ or ‘1’
are illegal.
The I2C module can operate either as a slave or a
master on an I2C bus.
The following types of I2C operation are supported:
• I2C slave operation with 7-bit address
• I2C slave operation with 10-bit address
• I2C master operation with 7- or 10-bit address
For details about the communication sequence in each
of these modes, refer to the “PIC24H Family Reference
Manual”.
EQUATION 15-1: SERIAL CLOCK RATE
FCY
FSCL
FCY
10,000,000
– 1
–
I2CxBRG =
)
(
© 2007 Microchip Technology Inc.
Preliminary
DS70289A-page 141
PIC24HJ32GP202/204 and PIC24HJ16GP304
FIGURE 15-1:
I2C™ BLOCK DIAGRAM (X = 1)
Internal
Data Bus
I2CxRCV
Read
Shift
Clock
SCLx
SDAx
I2CxRSR
LSb
Address Match
Write
Read
Match Detect
I2CxMSK
Write
Read
I2CxADD
Start and Stop
Bit Detect
Write
Start and Stop
Bit Generation
I2CxSTAT
I2CxCON
Read
Write
Collision
Detect
Acknowledge
Generation
Read
Clock
Stretching
Write
Read
I2CxTRN
LSb
Shift Clock
Reload
Control
Write
Read
BRG Down Counter
TCY/2
I2CxBRG
DS70289A-page 142
Preliminary
© 2007 Microchip Technology Inc.
PIC24HJ32GP202/204 and PIC24HJ16GP304
2
15.5 I C Module Addresses
15.8 General Call Address Support
The 10-bit I2CxADD register contains the Slave mode
addresses.
The general call address can address all devices.
When this address is used, all devices should, in
theory, respond with an Acknowledgement.
If the A10M bit (I2CxCON<10>) is ‘0’, the address is
interpreted by the module as a 7-bit address. When an
address is received, it is compared to the seven Least
Significant bits of the I2CxADD register.
The general call address is one of eight addresses
reserved for specific purposes by the I2C protocol. It
consists of all ‘0’s with R_W = 0.
If the A10M bit is ‘1’, the address is assumed to be a
10-bit address. When an address is received, it is com-
pared with the binary value, ‘11110 A9 A8’ (where A9
and A8 are two Most Significant bits of I2CxADD). If
that value matches, the next address will be compared
with the Least Significant 8 bits of I2CxADD, as speci-
fied in the 10-bit addressing protocol.
The general call address is recognized when the General
Call Enable (GCEN) bit is set (I2CxCON<7> = 1). When
the interrupt is serviced, the source for the interrupt can
be checked by reading the contents of the I2CxRCV to
determine if the address was device-specific or a general
call address.
15.9 Automatic Clock Stretch
TABLE 15-1: 7-BIT I2C™ SLAVE
ADDRESSES SUPPORTED BY
PIC24HJ32GP202/204 AND
PIC24HJ16GP304
In Slave modes, the module can synchronize buffer
reads and write to the master device by clock stretching.
15.9.1
TRANSMIT CLOCK STRETCHING
0x00
General call address or Start byte
Reserved
Both 10-bit and 7-bit Transmit modes implement clock
stretching by asserting the SCLREL bit after the falling
edge of the ninth clock, if the TBF bit is cleared,
indicating the buffer is empty.
0x01-0x03
0x04-0x07
0x08-0x77
0x78-0x7b
Hs mode Master codes
Valid 7-bit addresses
In Slave Transmit modes, clock stretching is always
performed, irrespective of the STREN bit. The user’s
ISR must set the SCLREL bit before transmission is
allowed to continue. By holding the SCLx line low, the
user application has time to service the ISR and load
the contents of the I2CxTRN before the master device
can initiate another transmit sequence.
Valid 10-bit addresses
(lower 7 bits)
0x7c-0x7f
Reserved
15.6 Slave Address Masking
The I2CxMSK register (Register 15-3) designates
address bit positions as “don’t care” for both 7-bit and
10-bit Address modes. Setting a particular bit location
(= 1) in the I2CxMSK register causes the slave module
to respond, whether the corresponding address bit
value is a ‘0’ or ‘1’. For example, when I2CxMSK is set
to ‘00100000’, the Slave module will detect both
addresses, ‘0000000’ and ‘00100000’.
15.9.2
RECEIVE CLOCK STRETCHING
The STREN bit in the I2CxCON register can be used to
enable clock stretching in Slave Receive mode. When
the STREN bit is set, the SCLx pin will be held low at
the end of each data receive sequence.
The user’s ISR must set the SCLREL bit before recep-
tion is allowed to continue. By holding the SCLx line
low, the user application has time to service the ISR
and read the contents of the I2CxRCV before the mas-
ter device can initiate another receive sequence. This
prevents buffer overruns.
To enable address masking, the IPMI (Intelligent
Peripheral Management Interface) must be disabled by
clearing the IPMIEN bit (I2CxCON<11>).
15.7 IPMI Support
The control bit IPMIEN enables the module to support
the Intelligent Peripheral Management Interface (IPMI).
When this bit is set, the module accepts and acts upon
all addresses.
15.10 Software Controlled Clock
Stretching (STREN = 1)
When the STREN bit is ‘1’, the software can clear the
SCLREL bit to allow software to control the clock
stretching.
If the STREN bit is ‘0’, a software write to the SCLREL
bit is disregarded and has no effect on the SCLREL bit.
© 2007 Microchip Technology Inc.
Preliminary
DS70289A-page 143
PIC24HJ32GP202/204 and PIC24HJ16GP304
15.11 Slope Control
15.13 Multi-Master Communication, Bus
Collision and Bus Arbitration
The I2C standard requires slope control on the SDAx
and SCLx signals for Fast mode (400 kHz). The control
bit, DISSLW, enables the user application to disable
slew rate control if desired. It is necessary to disable
the slew rate control for 1 MHz mode.
Multi-Master mode support is achieved by bus
arbitration. When the master outputs address/data bits
onto the SDAx pin, arbitration takes place when the
master outputs a ‘1’ on SDAx by letting SDAx float high
while another master asserts a ‘0’. When the SCLx pin
floats high, data should be stable. If the expected data
on SDAx is a ‘1’ and the data sampled on the
SDAx pin = 0, then a bus collision has taken place. The
master will set the I2C master events interrupt flag and
reset the master portion of the I2C port to its Idle state.
15.12 Clock Arbitration
Clock arbitration occurs when the master deasserts the
SCLx pin (SCLx allowed to float high) during any
receive, transmit or Restart/Stop condition. When the
SCLx pin is allowed to float high, the Baud Rate Gen-
erator (BRG) is suspended from counting until the
SCLx pin is actually sampled high. When the SCLx pin
is sampled high, the BRG is reloaded with the contents
of I2CxBRG and begins counting. This process
ensures that the SCLx high time will always be at least
one BRG rollover count in the event that the clock is
held low by an external device.
15.14 Peripheral Pin Select Limitations
The I2C module has limited peripheral pin select func-
tionality. When the ACTI2C bit in the FPOR configura-
tion register is set to ‘1‘, the module uses the SDAx/
SCLx pins. If the ALTI2C bit is ‘0‘, the module uses the
ASDAx/ASCLx pins.
DS70289A-page 144
Preliminary
© 2007 Microchip Technology Inc.
PIC24HJ32GP202/204 and PIC24HJ16GP304
REGISTER 15-1: I2CxCON: I2Cx CONTROL REGISTER
R/W-0
I2CEN
U-0
—
R/W-0
R/W-1 HC
SCLREL
R/W-0
R/W-0
A10M
R/W-0
R/W-0
SMEN
I2CSIDL
IPMIEN
DISSLW
bit 15
bit 8
R/W-0
GCEN
R/W-0
R/W-0
R/W-0 HC
ACKEN
R/W-0 HC
RCEN
R/W-0 HC
PEN
R/W-0 HC
RSEN
R/W-0 HC
SEN
STREN
ACKDT
bit 7
bit 0
Legend:
U = Unimplemented bit, read as ‘0’
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
HS = Set in hardware
‘0’ = Bit is cleared
HC = Cleared in hardware
x = Bit is unknown
bit 15
I2CEN: I2Cx Enable bit
1= Enables the I2Cx module and configures the SDAx and SCLx pins as serial port pins
0= Disables the I2Cx module. All I2C pins are controlled by port functions.
bit 14
bit 13
Unimplemented: Read as ‘0’
I2CSIDL: Stop in Idle Mode bit
1= Discontinue module operation when device enters an Idle mode
0= Continue module operation in Idle mode
bit 12
SCLREL: SCLx Release Control bit (when operating as I2C slave)
1= Release SCLx clock
0= Hold SCLx clock low (clock stretch)
If STREN = 1:
Bit is R/W (i.e., software can write ‘0’ to initiate stretch and write ‘1’ to release clock). Hardware clear
at beginning of slave transmission. Hardware clear at end of slave reception.
If STREN = 0:
Bit is R/S (i.e., software can only write ‘1’ to release clock). Hardware clear at beginning of slave
transmission.
bit 11
bit 10
bit 9
IPMIEN: Intelligent Peripheral Management Interface (IPMI) Enable bit
1= IPMI mode is enabled; all addresses Acknowledged
0= IPMI mode disabled
A10M: 10-bit Slave Address bit
1= I2CxADD is a 10-bit slave address
0= I2CxADD is a 7-bit slave address
DISSLW: Disable Slew Rate Control bit
1= Slew rate control disabled
0= Slew rate control enabled
bit 8
SMEN: SMBus Input Levels bit
1= Enable I/O pin thresholds compliant with SMBus specification
0= Disable SMBus input thresholds
bit 7
GCEN: General Call Enable bit (when operating as I2C slave)
1= Enable interrupt when a general call address is received in the I2CxRSR
(module is enabled for reception)
0= General call address disabled
bit 6
STREN: SCLx Clock Stretch Enable bit (when operating as I2C slave)
Used in conjunction with SCLREL bit.
1= Enable software or receive clock stretching
0= Disable software or receive clock stretching
© 2007 Microchip Technology Inc.
Preliminary
DS70289A-page 145
PIC24HJ32GP202/204 and PIC24HJ16GP304
REGISTER 15-1: I2CxCON: I2Cx CONTROL REGISTER (CONTINUED)
bit 5
ACKDT: Acknowledge Data bit (when operating as I2C master, applicable during master receive)
Value that will be transmitted when the software initiates an Acknowledge sequence.
1= Send NACK during Acknowledge
0= Send ACK during Acknowledge
bit 4
ACKEN: Acknowledge Sequence Enable bit
(when operating as I2C master, applicable during master receive)
1= Initiate Acknowledge sequence on SDAx and SCLx pins and transmit ACKDT data bit.
Hardware clear at end of master Acknowledge sequence.
0= Acknowledge sequence not in progress
bit 3
bit 2
bit 1
RCEN: Receive Enable bit (when operating as I2C master)
1= Enables Receive mode for I2C. Hardware clear at end of eighth bit of master receive data byte.
0= Receive sequence not in progress
PEN: Stop Condition Enable bit (when operating as I2C master)
1= Initiate Stop condition on SDAx and SCLx pins. Hardware clear at end of master Stop sequence.
0= Stop condition not in progress
RSEN: Repeated Start Condition Enable bit (when operating as I2C master)
1= Initiate Repeated Start condition on SDAx and SCLx pins. Hardware clear at end of
master Repeated Start sequence.
0= Repeated Start condition not in progress
bit 0
SEN: Start Condition Enable bit (when operating as I2C master)
1= Initiate Start condition on SDAx and SCLx pins. Hardware clear at end of master Start sequence.
0= Start condition not in progress
DS70289A-page 146
Preliminary
© 2007 Microchip Technology Inc.
PIC24HJ32GP202/204 and PIC24HJ16GP304
REGISTER 15-2: I2CxSTAT: I2Cx STATUS REGISTER
R-0 HSC
R-0 HSC
TRSTAT
U-0
—
U-0
—
U-0
—
R/C-0 HS
BCL
R-0 HSC
GCSTAT
R-0 HSC
ADD10
ACKSTAT
bit 15
bit 8
R/C-0 HS
IWCOL
R/C-0 HS
I2COV
R-0 HSC
D_A
R/C-0 HSC R/C-0 HSC
R-0 HSC
R_W
R-0 HSC
RBF
R-0 HSC
TBF
P
S
bit 7
bit 0
Legend:
U = Unimplemented bit, read as ‘0’
R = Readable bit
W = Writable bit
‘1’ = Bit is set
HS = Set in hardware
‘0’ = Bit is cleared
HSC = Hardware set/cleared
x = Bit is unknown
-n = Value at POR
bit 15
bit 14
ACKSTAT: Acknowledge Status bit
(when operating as I2C master, applicable to master transmit operation)
1= NACK received from slave
0= ACK received from slave
Hardware set or clear at end of slave Acknowledge.
TRSTAT: Transmit Status bit (when operating as I2C master, applicable to master transmit operation)
1= Master transmit is in progress (8 bits + ACK)
0= Master transmit is not in progress
Hardware set at beginning of master transmission. Hardware clear at end of slave Acknowledge.
bit 13-11
bit 10
Unimplemented: Read as ‘0’
BCL: Master Bus Collision Detect bit
1= A bus collision has been detected during a master operation
0= No collision
Hardware set at detection of bus collision.
bit 9
bit 8
bit 7
bit 6
bit 5
bit 4
GCSTAT: General Call Status bit
1= General call address was received
0= General call address was not received
Hardware set when address matches general call address. Hardware clear at Stop detection.
ADD10: 10-bit Address Status bit
1= 10-bit address was matched
0= 10-bit address was not matched
Hardware set at match of 2nd byte of matched 10-bit address. Hardware clear at Stop detection.
IWCOL: Write Collision Detect bit
1= An attempt to write the I2CxTRN register failed because the I2C module is busy
0= No collision
Hardware set at occurrence of write to I2CxTRN while busy (cleared by software).
I2COV: Receive Overflow Flag bit
1= A byte was received while the I2CxRCV register is still holding the previous byte
0= No overflow
Hardware set at attempt to transfer I2CxRSR to I2CxRCV (cleared by software).
D_A: Data/Address bit (when operating as I2C slave)
1= Indicates that the last byte received was data
0= Indicates that the last byte received was device address
Hardware clear at device address match. Hardware set by reception of slave byte.
P: Stop bit
1= Indicates that a Stop bit has been detected last
0= Stop bit was not detected last
Hardware set or clear when Start, Repeated Start or Stop detected.
© 2007 Microchip Technology Inc.
Preliminary
DS70289A-page 147
PIC24HJ32GP202/204 and PIC24HJ16GP304
REGISTER 15-2: I2CxSTAT: I2Cx STATUS REGISTER (CONTINUED)
bit 3
bit 2
bit 1
S: Start bit
1= Indicates that a Start (or Repeated Start) bit has been detected last
0= Start bit was not detected last
Hardware set or clear when Start, Repeated Start or Stop detected.
R_W: Read/Write Information bit (when operating as I2C slave)
1= Read – indicates data transfer is output from slave
0= Write – indicates data transfer is input to slave
Hardware set or clear after reception of I2C device address byte.
RBF: Receive Buffer Full Status bit
1= Receive complete, I2CxRCV is full
0= Receive not complete, I2CxRCV is empty
Hardware set when I2CxRCV is written with received byte. Hardware clear when software
reads I2CxRCV.
bit 0
TBF: Transmit Buffer Full Status bit
1= Transmit in progress, I2CxTRN is full
0= Transmit complete, I2CxTRN is empty
Hardware set when software writes I2CxTRN. Hardware clear at completion of data transmission.
DS70289A-page 148
Preliminary
© 2007 Microchip Technology Inc.
PIC24HJ32GP202/204 and PIC24HJ16GP304
REGISTER 15-3: I2CxMSK: I2Cx SLAVE MODE ADDRESS MASK REGISTER
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
R/W-0
R/W-0
AMSK9
AMSK8
bit 15
bit 8
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
AMSK7
AMSK6
AMSK5
AMSK4
AMSK3
AMSK2
AMSK1
AMSK0
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-10
bit 9-0
Unimplemented: Read as ‘0’
AMSKx: Mask for Address bit x Select bit
1= Enable masking for bit x of incoming message address; bit match not required in this position
0= Disable masking for bit x; bit match required in this position
© 2007 Microchip Technology Inc.
Preliminary
DS70289A-page 149
PIC24HJ32GP202/204 and PIC24HJ16GP304
NOTES:
DS70289A-page 150
Preliminary
© 2007 Microchip Technology Inc.
PIC24HJ32GP202/204 and PIC24HJ16GP304
• Fully Integrated Baud Rate Generator with 16-bit
prescaler
16.0 UNIVERSAL ASYNCHRONOUS
RECEIVER TRANSMITTER
(UART)
• Baud rates ranging from 1 Mbps to 15 Mbps at
16 MIPS
• 4-deep first-in-first-out (FIFO) Transmit Data
Buffer
Note:
This data sheet summarizes the features
of the PIC24HJ32GP202/204 and
PIC24HJ16GP304 devices. It is not
intended to be a comprehensive reference
source. To complement the information in
this data sheet, refer to the “PIC24H
Family Reference Manual”.
• 4-Deep FIFO Receive Data Buffer
• Parity, framing and buffer overrun error detection
• Support for 9-bit mode with Address Detect
(9th bit = 1)
• Transmit and Receive interrupts
The Universal Asynchronous Receiver Transmitter
(UART) module is one of the serial I/O modules avail-
• A separate interrupt for all UART error conditions
• Loopback mode for diagnostic support
• Support for Sync and Break characters
• Support for automatic baud rate detection
• IrDA encoder and decoder logic
able
in
the
PIC24HJ32GP202/204
and
PIC24HJ16GP304 device family. The UART is a full-
duplex asynchronous system that can communicate
with peripheral devices, such as personal computers,
LIN, RS-232 and RS-485 interfaces. The module also
supports a hardware flow control option with the
UxCTS and UxRTS pins and also includes an IrDA®
encoder and decoder.
• 16x baud clock output for IrDA support
A simplified block diagram of the UART module is
shown in Figure 16-1. The UART module consists of
the following key hardware elements:
The primary features of the UART module are:
• Baud Rate Generator
• Full-Duplex 8- or 9-bit Data Transmission through
the UxTX and UxRX pins
• Asynchronous Transmitter
• Asynchronous Receiver
• Even, odd or no parity options (for 8-bit data)
• One or two stop bits
• Hardware Flow Control Option with UxCTS and
UxRTS pins
FIGURE 16-1:
UART SIMPLIFIED BLOCK DIAGRAM
Baud Rate Generator
IrDA®
BCLK
Hardware Flow Control
UART Receiver
UxRTS
UxCTS
UxRX
UxTX
UART Transmitter
© 2007 Microchip Technology Inc.
Preliminary
DS70289A-page 151
PIC24HJ32GP202/204 and PIC24HJ16GP304
The maximum baud rate (BRGH = 0) possible is
16.1 UART Baud Rate Generator
FCY/16 (for BRGx = 0), and the minimum baud rate
The UART module includes a dedicated 16-bit Baud
possible is FCY/(16 * 65536).
Rate Generator (BRG). The BRGx register controls the
period of a free-running 16-bit timer. Equation 16-1
shows the formula for computation of the baud rate
Equation 16-2 shows the formula for computation of
the baud rate with BRGH = 1.
with BRGH = 0.
EQUATION 16-2: UART BAUD RATE WITH
BRGH = 1
EQUATION 16-1: UART BAUD RATE WITH
BRGH = 0
FCY
Baud Rate =
4 • (BRGx + 1)
FCY
Baud Rate =
16 • (BRGx + 1)
FCY
– 1
BRGx =
4 • Baud Rate
FCY
– 1
BRGx =
16 • Baud Rate
Note: FCY denotes the instruction cycle clock
frequency (FOSC/2).
Note: FCY denotes the instruction cycle clock
frequency (FOSC/2).
The maximum baud rate (BRGH = 1) possible is FCY/4
(for BRGx = 0), and the minimum baud rate possible is
FCY/(4 * 65536).
Example 16-1 shows the calculation of the baud rate
error for the following conditions:
Writing a new value to the BRGx register causes the
BRG timer to be reset (cleared). This ensures the BRG
does not wait for a timer overflow before generating the
new baud rate.
• FCY = 4 MHz
• Desired Baud Rate = 9600
EXAMPLE 16-1:
BAUD RATE ERROR CALCULATION (BRGH = 0)
Desired Baud Rate
=
FCY/(16 (BRGx + 1))
Solving for BRGx Value:
BRGx
BRGx
BRGx
=
=
=
((FCY/Desired Baud Rate)/16) – 1
((4000000/9600)/16) – 1
25
Calculated Baud Rate
=
=
4000000/(16 (25 + 1))
9615
Error
=
(Calculated Baud Rate – Desired Baud Rate)
Desired Baud Rate
=
=
(9615 – 9600)/9600
0.16%
DS70289A-page 152
Preliminary
© 2007 Microchip Technology Inc.
PIC24HJ32GP202/204 and PIC24HJ16GP304
16.2 Transmitting in 8-bit Data Mode
16.5 Receiving in 8-bit or 9-bit Data
Mode
1. Set up the UART:
a) Write appropriate values for data, parity
and Stop bits.
1. Set up the UART (as described in Section 16.2
“Transmitting in 8-bit Data Mode”).
b) Write appropriate baud rate value to the
BRGx register.
2. Enable the UART. A receive interrupt will be
generated when one or more data characters
have been received as per interrupt control bits,
URXISEL<1:0>.
c) Set up transmit and receive interrupt enable
and priority bits.
3. Read the OERR bit to determine if an overrun
error has occurred. The OERR bit must be reset
in software.
2. Enable the UART.
3. Set the UTXEN bit (causes a transmit interrupt).
Write data byte to lower byte of UxTXREG word.
The value will be immediately transferred to the
Transmit Shift Register (TSR) and the serial bit
stream will start shifting out with the next rising
edge of the baud clock.
4. Read UxRXREG.
The act of reading the UxRXREG character will move
the next character to the top of the receive FIFO,
including a new set of PERR and FERR values.
Alternately, the data byte can be transferred
while UTXEN = 0, and the user application can
set UTXEN. This causes the serial bit stream to
begin immediately, because the baud clock
starts from a cleared state.
16.6 Flow Control Using UxCTS and
UxRTS Pins
UARTx Clear to Send (UxCTS) and Request to Send
(UxRTS) are the two hardware controlled active-low
pins associated with the UART module. The UEN<1:0>
bits in the UxMODE register configure these pins.
4. A transmit interrupt will be generated as per
interrupt control bits, UTXISEL<1:0>.
These two pins allow the UART to operate in Simplex
and Flow Control modes. They are implemented to
control the transmission and the reception between the
Data Terminal Equipment (DTE).
16.3 Transmitting in 9-bit Data Mode
1. Set up the UART (as described in Section 16.2
“Transmitting in 8-bit Data Mode”).
2. Enable the UART.
16.7 Infrared Support
3. Set the UTXEN bit (causes a transmit interrupt).
4. Write UxTXREG as a 16-bit value only.
The UART module provides two types of infrared
UART support:
A word write to UxTXREG triggers the transfer
of the 9-bit data to the TSR. The serial bit stream
will start shifting out with the first rising edge of
the baud clock.
A transmit interrupt will be generated as per the
setting of control bits, UTXISEL<1:0>.
• IrDA clock output to support external IrDA
encoder and decoder device (legacy module
support)
• Full implementation of the IrDA encoder and
decoder.
16.4 Break and Sync Transmit
Sequence
16.7.1
EXTERNAL IrDA SUPPORT – IrDA
CLOCK OUTPUT
To support external IrDA encoder and decoder
devices, the BCLK pin can be configured to generate
the 16x baud clock. With UEN<1:0> = 11, the BCLK pin
will output the 16x baud clock if the UART module is
enabled. The pin can be used to support the IrDA
codec chip.
The following sequence will send a message frame
header made up of a Break, followed by an auto-baud
Sync byte.
1. Configure the UART for the desired mode.
2. Set UTXEN and UTXBRK, which sets up the
Break character.
16.7.2
BUILT-IN IrDA ENCODER AND
DECODER
3. Load the UxTXREG register with a dummy
character to initiate transmission (value is
ignored).
The UART module includes full implementation of the
IrDA encoder and decoder. The built-in IrDA encoder
and decoder functionality is enabled using the IREN bit
(UxMODE<12>). When IREN = 1 is enabled, the
receive pin (UxRX) acts as the input from the infrared
receiver. The transmit pin (UxTX) acts as the output to
the infrared transmitter.
4. Write 0x55 to UxTXREG, which loads the Sync
character into the transmit FIFO. After the Break
has been sent, the UTXBRK bit is reset by hard-
ware. The Sync character now starts transmit-
ting.
© 2007 Microchip Technology Inc.
Preliminary
DS70289A-page 153
PIC24HJ32GP202/204 and PIC24HJ16GP304
REGISTER 16-1: UxMODE: UARTx MODE REGISTER
R/W-0
U-0
—
R/W-0
USIDL
R/W-0
IREN(1)
R/W-0
U-0
—
R/W-0
R/W-0
UARTEN
RTSMD
UEN<1:0>
bit 15
bit 8
R/W-0 HC
WAKE
R/W-0
R/W-0 HC
ABAUD
R/W-0
R/W-0
BRGH
R/W-0
R/W-0
R/W-0
LPBACK
URXINV
PDSEL<1:0>
STSEL
bit 7
bit 0
Legend:
HC = Hardware cleared
W = Writable bit
R = Readable bit
-n = Value at POR
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
‘1’ = Bit is set
bit 15
UARTEN: UARTx Enable bit
1= UARTx is enabled; all UARTx pins are controlled by UARTx as defined by UEN<1:0>
0= UARTx is disabled; all UARTx pins are controlled by port latches; UARTx power consumption
minimal
bit 14
bit 13
Unimplemented: Read as ‘0’
USIDL: Stop in Idle Mode bit
1= Discontinue module operation when device enters Idle mode
0= Continue module operation in Idle mode
bit 12
bit 11
IREN: IrDA Encoder and Decoder Enable bit(1)
1= IrDA encoder and decoder enabled
0= IrDA encoder and decoder disabled
RTSMD: Mode Selection for UxRTS Pin bit
1= UxRTS pin in Simplex mode
0= UxRTS pin in Flow Control mode
bit 10
Unimplemented: Read as ‘0’
UEN<1:0>: UARTx Enable bits
bit 9-8
11= UxTX, UxRX and BCLK pins are enabled and used; UxCTS pin controlled by port latches
10= UxTX, UxRX, UxCTS and UxRTS pins are enabled and used
01= UxTX, UxRX and UxRTS pins are enabled and used; UxCTS pin controlled by port latches
00= UxTX and UxRX pins are enabled and used; UxCTS and UxRTS/BCLK pins controlled by
port latches
bit 7
WAKE: Wake-up on Start bit Detect During Sleep Mode Enable bit
1= UARTx will continue to sample the UxRX pin; interrupt generated on falling edge; bit cleared
in hardware on following rising edge
0= No wake-up enabled
bit 6
bit 5
LPBACK: UARTx Loopback Mode Select bit
1= Enable Loopback mode
0= Loopback mode is disabled
ABAUD: Auto-Baud Enable bit
1= Enable baud rate measurement on the next character – requires reception of a Sync field (55h)
before other data; cleared in hardware upon completion
0= Baud rate measurement disabled or completed
bit 4
URXINV: Receive Polarity Inversion bit
1= UxRX Idle state is ‘0’
0= UxRX Idle state is ‘1’
Note 1: This feature is only available for the 16x BRG mode (BRGH = 0).
DS70289A-page 154
Preliminary
© 2007 Microchip Technology Inc.
PIC24HJ32GP202/204 and PIC24HJ16GP304
REGISTER 16-1: UxMODE: UARTx MODE REGISTER (CONTINUED)
bit 3
BRGH: High Baud Rate Enable bit
1= BRG generates 4 clocks per bit period (4x baud clock, High-Speed mode)
0= BRG generates 16 clocks per bit period (16x baud clock, Standard mode)
bit 2-1
PDSEL<1:0>: Parity and Data Selection bits
11= 9-bit data, no parity
10= 8-bit data, odd parity
01= 8-bit data, even parity
00= 8-bit data, no parity
bit 0
STSEL: Stop Bit Selection bit
1= Two Stop bits
0= One Stop bit
Note 1: This feature is only available for the 16x BRG mode (BRGH = 0).
© 2007 Microchip Technology Inc.
Preliminary
DS70289A-page 155
PIC24HJ32GP202/204 and PIC24HJ16GP304
REGISTER 16-2: UxSTA: UARTx STATUS AND CONTROL REGISTER
R/W-0
R/W-0
UTXINV(1)
R/W-0
U-0
—
R/W-0 HC
UTXBRK
R/W-0
R-0
R-1
UTXISEL1
UTXISEL0
UTXEN
UTXBF
TRMT
bit 15
bit 8
R/W-0
R/W-0
R/W-0
R-1
R-0
R-0
R/C-0
R-0
URXISEL<1:0>
ADDEN
RIDLE
PERR
FERR
OERR
URXDA
bit 7
bit 0
Legend:
HC = Hardware cleared
W = Writable bit
R = Readable bit
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
-n = Value at POR
‘1’ = Bit is set
bit 15,13
UTXISEL<1:0>: Transmission Interrupt Mode Selection bits
11= Reserved; do not use
10= Interrupt when a character is transferred to the Transmit Shift Register, and as a result, the
transmit buffer becomes empty
01= Interrupt when the last character is shifted out of the Transmit Shift Register; all transmit
operations are completed
00= Interrupt when a character is transferred to the Transmit Shift Register (this implies there is
at least one character open in the transmit buffer)
bit 14
UTXINV: IrDA Encoder Transmit Polarity Inversion bit(1)
1= IrDA encoded, UxTX Idle state is ‘1’
0= IrDA encoded, UxTX Idle state is ‘0’
bit 12
bit 11
Unimplemented: Read as ‘0’
UTXBRK: Transmit Break bit
1= Send Sync Break on next transmission – Start bit, followed by twelve ‘0’ bits, followed by Stop bit;
cleared by hardware upon completion
0= Sync Break transmission disabled or completed
bit 10
UTXEN: Transmit Enable bit
1= Transmit enabled, UxTX pin controlled by UARTx
0= Transmit disabled, any pending transmission is aborted and buffer is reset. UxTX pin controlled
by port.
bit 9
UTXBF: Transmit Buffer Full Status bit (read-only)
1= Transmit buffer is full
0= Transmit buffer is not full, at least one more character can be written
bit 8
TRMT: Transmit Shift Register Empty bit (read-only)
1= Transmit Shift Register is empty and transmit buffer is empty (the last transmission has completed)
0= Transmit Shift Register is not empty, a transmission is in progress or queued
bit 7-6
URXISEL<1:0>: Receive Interrupt Mode Selection bits
11= Interrupt is set on UxRSR transfer making the receive buffer full (i.e., has 4 data characters)
10= Interrupt is set on UxRSR transfer making the receive buffer 3/4 full (i.e., has 3 data characters)
0x= Interrupt is set when any character is received and transferred from the UxRSR to the receive
buffer. Receive buffer has one or more characters.
bit 5
ADDEN: Address Character Detect bit (bit 8 of received data = 1)
1= Address Detect mode enabled. If 9-bit mode is not selected, this does not take effect.
0= Address Detect mode disabled
Note 1: Value of bit only affects the transmit properties of the module when the IrDA encoder is enabled
(IREN = 1).
DS70289A-page 156
Preliminary
© 2007 Microchip Technology Inc.
PIC24HJ32GP202/204 and PIC24HJ16GP304
REGISTER 16-2: UxSTA: UARTx STATUS AND CONTROL REGISTER (CONTINUED)
bit 4
bit 3
bit 2
RIDLE: Receiver Idle bit (read-only)
1= Receiver is Idle
0= Receiver is active
PERR: Parity Error Status bit (read-only)
1= Parity error has been detected for the current character (character at the top of the receive FIFO)
0= Parity error has not been detected
FERR: Framing Error Status bit (read-only)
1= Framing error has been detected for the current character (character at the top of the receive
FIFO)
0= Framing error has not been detected
bit 1
bit 0
OERR: Receive Buffer Overrun Error Status bit (read/clear only)
1= Receive buffer has overflowed
0= Receive buffer has not overflowed. Clearing a previously set OERR bit (1→ 0transition) will reset
the receiver buffer and the UxRSR to the empty state.
URXDA: Receive Buffer Data Available bit (read-only)
1= Receive buffer has data, at least one more character can be read
0= Receive buffer is empty
Note 1: Value of bit only affects the transmit properties of the module when the IrDA encoder is enabled
(IREN = 1).
© 2007 Microchip Technology Inc.
Preliminary
DS70289A-page 157
PIC24HJ32GP202/204 and PIC24HJ16GP304
NOTES:
DS70289A-page 158
Preliminary
© 2007 Microchip Technology Inc.
PIC24HJ32GP202/204 and PIC24HJ16GP304
Depending on the particular device pinout, the ADC
17.0 10-BIT/12-BIT ANALOG-TO-
can have up to 13 analog input pins, designated AN0
through AN12. In addition, there are two analog input
pins for external voltage reference connections. These
voltage reference inputs can be shared with other ana-
log input pins.
DIGITAL CONVERTER (ADC)
Note:
This data sheet summarizes the features
of the PIC24HJ32GP202/204 and
PIC24HJ16GP304 devices. It is not
intended to be a comprehensive reference
source. To complement the information in
this data sheet, refer to the “PIC24H
Family Reference Manual”.
The actual number of analog input pins and external
voltage reference input configuration will depend on the
specific device. Refer to the device data sheet for fur-
ther details.
A block diagram of ADC for PIC24HJ16GP304 and
PIC24HJ32GP204 devices is shown in Figure 17-1. A
block diagram of the ADC for the PIC24HJ32GP202
device is shown in Figure 17-2.
The PIC24HJ32GP202/204 and PIC24HJ16GP304
devices have up to 13 Analog-to-Digital Conversion
(ADC) module input channels.
The AD12B bit (AD1CON1<10>) allows each of the
ADC modules to be configured as either a 10-bit, 4-
sample-and-hold ADC (default configuration), or a
12-bit, 1-sample-and-hold ADC.
17.2 ADC Initialization
To configure the ADC module:
Note:
The ADC module must be disabled before
the AD12B bit can be modified.
1. Select
port
pins
as
analog
inputs
(AD1PCFGH<15:0> or AD1PCFGL<15:0>).
2. Select voltage reference source to match
17.1 Key Features
expected
range
on
analog
inputs
(AD1CON2<15:13>).
The 10-bit ADC configuration has the following key
features:
3. Select the analog conversion clock to match
desired data rate with processor clock
(AD1CON3<7:0>).
• Successive Approximation (SAR) conversion
• Conversion speeds of up to 1.1 Msps
• Up to 13 analog input pins
4. Determine how many sample-and-hold chan-
nels will be used (AD1CON2<9:8> and
AD1PCFGH<15:0> or AD1PCFGL<15:0>).
• External voltage reference input pins
• Simultaneous sampling of up to four analog input
pins
5. Select the appropriate sample/conversion
sequence
(AD1CON1<7:5>
and
AD1CON3<12:8>).
• Automatic Channel Scan mode
6. Select the way conversion results are presented
in the buffer (AD1CON1<9:8>).
• Selectable conversion trigger source
• Selectable Buffer Fill modes
7. Turn on the ADC module (AD1CON1<15>).
8. Configure ADC interrupt (if required):
a) Clear the AD1IF bit.
• Operation during CPU Sleep and Idle modes
• 16-word conversion result buffer
The 12-bit ADC configuration supports all the above
features, except:
b) Select ADC interrupt priority.
• In the 12-bit configuration, conversion speeds of
up to 500 ksps are supported
• There is only 1 sample-and-hold amplifier in the
12-bit configuration, so simultaneous sampling of
multiple channels is not supported.
© 2007 Microchip Technology Inc.
Preliminary
DS70289A-page 159
PIC24HJ32GP202/204 and PIC24HJ16GP304
FIGURE 17-1:
ADC1 MODULE BLOCK DIAGRAM FOR PIC24HFJ16GP304 AND
PIC24HJ32GP204 DEVICES
AVDD
AVSS
VREF+(1)
VREF-(1)
AN0
AN3
AN0
AN1
AN2
+
CH1(2)
CH2(2)
CH3(2)
S/H
ADC1
AN6
AN9
VREF-
-
Conversion Logic
Conversion
Result
AN1
AN4
+
S/H
AN7
AN10
VREF-
-
16-bit
ADC Output
Buffer
AN2
AN5
+
S/H
AN8
AN11
VREF-
CH1,CH2,
CH3,CH0
-
Sample/Sequence
Control
Sample
00000
00001
00010
00011
Input
Switches
Input MUX
Control
AN3
00100
00101
00110
00111
01000
01001
01010
01011
01100
AN4
AN5
AN6
AN7
AN8
AN9
AN10
AN11
AN12
+
CH0
VREF-
AN1
S/H
-
Note 1: VREF+, VREF- inputs may be multiplexed with other analog inputs.
2: Channels 1, 2 and 3 are not applicable for the 12-bit mode of operation.
DS70289A-page 160
Preliminary
© 2007 Microchip Technology Inc.
PIC24HJ32GP202/204 and PIC24HJ16GP304
FIGURE 17-2:
ADC1 MODULE BLOCK DIAGRAM FOR PIC24HJ32GP202 DEVICES
AVDD
AVSS
VREF+(1)
VREF-(1)
AN0
AN3
AN0
AN1
AN2
+
CH1(2)
S/H
ADC1
-
AN9
VREF-
Conversion Logic
Conversion
Result
AN1
AN4
CH2(2)
+
S/H
-
AN10
VREF-
16-bit
ADC Output
Buffer
AN2
AN5
+
CH3(2)
S/H
CH1,CH2,
CH3,CH0
-
AN11
VREF-
Sample/Sequence
Control
Sample
00000
00001
00010
00011
Input
Switches
Input MUX
Control
AN3
00100
00101
01001
01010
01011
01100
AN4
AN5
AN9
AN10
AN11
AN12
+
CH0
VREF-
AN1
S/H
-
Note 1: VREF+, VREF- inputs may be multiplexed with other analog inputs.
2: Channels 1, 2 and 3 are not applicable for the 12-bit mode of operation.
© 2007 Microchip Technology Inc.
Preliminary
DS70289A-page 161
PIC24HJ32GP202/204 and PIC24HJ16GP304
EQUATION 17-1: ADC CONVERSION CLOCK PERIOD
TCY(ADCS + 1)
TAD =
TAD
TCY
– 1
ADCS =
FIGURE 17-3:
ADC TRANSFER FUNCTION (10-BIT EXAMPLE)
Output Code
11 1111 1111 (= 1023)
11 1111 1110 (= 1022)
10 0000 0011 (= 515)
10 0000 0010 (= 514)
10 0000 0001 (= 513)
10 0000 0000 (= 512)
01 1111 1111 (= 511)
01 1111 1110 (= 510)
01 1111 1101 (= 509)
00 0000 0001 (= 1)
00 0000 0000 (= 0)
VREFL
VREFH
VREFH – VREFL
1024
512 * (VREFH – VREFL)
1024
1023 * (VREFH – VREFL)
1024
VREFL +
VREFL +
VREFL +
(VINH – VINL)
FIGURE 17-4:
ADC CONVERSION CLOCK PERIOD BLOCK DIAGRAM
AD1CON3<15>
ADC Internal
RC Clock
0
1
TAD
AD1CON3<5:0>
6
ADC Conversion
Clock Multiplier
TCY
(1)
X2
TOSC
1, 2, 3, 4, 5,..., 64
Note:
Refer to Figure 7-2 for the derivation of FOSC when the PLL is enabled. If the PLL is not used, FOSC is equal
to the clock frequency. TOSC = 1/FOSC.
DS70289A-page 162
Preliminary
© 2007 Microchip Technology Inc.
PIC24HJ32GP202/204 and PIC24HJ16GP304
REGISTER 17-1: AD1CON1: ADC1 CONTROL REGISTER 1
R/W-0
ADON
U-0
—
R/W-0
U-0
—
U-0
—
R/W-0
R/W-0
R/W-0
ADSIDL
AD12B
FORM<1:0>
bit 15
bit 8
R/W-0
R/W-0
R/W-0
U-0
—
R/W-0
R/W-0
ASAM
R/W-0
HC,HS
R/C-0
HC, HS
SSRC<2:0>
SIMSAM
SAMP
DONE
bit 7
bit 0
Legend:
HC = Cleared by hardware
W = Writable bit
HS = Set by hardware
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
R = Readable bit
-n = Value at POR
‘1’ = Bit is set
bit 15
ADON: ADC Operating Mode bit
1= ADC module is operating
0= ADC is off
bit 14
bit 13
Unimplemented: Read as ‘0’
ADSIDL: Stop in Idle Mode bit
1= Discontinue module operation when device enters Idle mode
0= Continue module operation in Idle mode
bit 12-11
bit 10
Unimplemented: Read as ‘0’
AD12B: 10-bit or 12-bit Operation Mode bit
1= 12-bit, 1-channel ADC operation
0= 10-bit, 4-channel ADC operation
bit 9-8
FORM<1:0>: Data Output Format bits
For 10-bit operation:
11= Reserved
10= Reserved
01= Signed integer (DOUT = ssss sssd dddd dddd, where s= .NOT.d<9>)
00= Integer (DOUT = 0000 00dd dddd dddd)
For 12-bit operation:
11= Reserved
10= Reserved
01= Signed Integer (DOUT = ssss sddd dddd dddd, where s= .NOT.d<11>)
00= Integer (DOUT = 0000 dddd dddd dddd)
bit 7-5
SSRC<2:0>: Sample Clock Source Select bits
111= Internal counter ends sampling and starts conversion (auto-convert)
110= Reserved
101= Reserved
100= Reserved
011= Reserved
010= GP timer 3 compare ends sampling and starts conversion
001= Active transition on INT0 pin ends sampling and starts conversion
000= Clearing sample bit ends sampling and starts conversion
bit 4
bit 3
Unimplemented: Read as ‘0’
SIMSAM: Simultaneous Sample Select bit (applicable only when CHPS<1:0> = 01or 1x)
When AD12B = 1, SIMSAM is: U-0, Unimplemented, Read as ‘0’
1= Samples CH0, CH1, CH2, CH3 simultaneously (when CHPS<1:0> = 1x); or
Samples CH0 and CH1 simultaneously (when CHPS<1:0> = 01)
0= Samples multiple channels individually in sequence
© 2007 Microchip Technology Inc.
Preliminary
DS70289A-page 163
PIC24HJ32GP202/204 and PIC24HJ16GP304
REGISTER 17-1: AD1CON1: ADC1 CONTROL REGISTER 1 (CONTINUED)
bit 2
bit 1
ASAM: ADC Sample Auto-Start bit
1= Sampling begins immediately after last conversion. SAMP bit is auto-set.
0= Sampling begins when SAMP bit is set
SAMP: ADC Sample Enable bit
1= ADC sample-and-hold amplifiers are sampling
0= ADC sample-and-hold amplifiers are holding
If ASAM = 0, software can write ‘1’ to begin sampling. Automatically set by hardware if ASAM = 1.
If SSRC = 000, software can write ‘0’ to end sampling and start conversion. If SSRC ≠ 000,
automatically cleared by hardware to end sampling and start conversion.
bit 0
DONE: ADC Conversion Status bit
1= ADC conversion cycle is completed
0= ADC conversion not started or in progress
Automatically set by hardware when ADC conversion is complete. Software can write ‘0’ to clear
DONE status (software not allowed to write ‘1’). Clearing this bit will NOT affect any operation in
progress. Automatically cleared by hardware at start of a new conversion.
DS70289A-page 164
Preliminary
© 2007 Microchip Technology Inc.
PIC24HJ32GP202/204 and PIC24HJ16GP304
REGISTER 17-2: AD1CON2: ADC1 CONTROL REGISTER 2
R/W-0
R/W-0
R/W-0
U-0
—
U-0
—
R/W-0
R/W-0
R/W-0
VCFG<2:0>
CSCNA
CHPS<1:0>
bit 15
bit 8
R-0
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
BUFM
R/W-0
ALTS
BUFS
SMPI<3:0>
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-13
VCFG<2:0>: Converter Voltage Reference Configuration bits
ADREF+
ADREF-
000
AVDD
AVSS
AVSS
001 External VREF+
010
011 External VREF+
1xx
AVDD
External VREF-
External VREF-
Avss
AVDD
bit 12-11
bit 10
Unimplemented: Read as ‘0’
CSCNA: Scan Input Selections for CH0+ during Sample A bit
1= Scan inputs
0= Do not scan inputs
bit 9-8
bit 7
CHPS<1:0>: Select Channels Utilized bits
When AD12B = 1, CHPS<1:0> is: U-0, Unimplemented, Read as ‘0’
1x=Converts CH0, CH1, CH2 and CH3
01=Converts CH0 and CH1
00=Converts CH0
BUFS: Buffer Fill Status bit (valid only when BUFM = 1)
1= ADC is currently filling second half of buffer, user application should access data in the first half
0= ADC is currently filling first half of buffer, user application should access data in the second half
bit 6
Unimplemented: Read as ‘0’
bit 5-2
SMPI<3:0>: Sample/Convert Sequences Per Interrupt Selection bits
1111=Interrupts at the completion of conversion for each 16th sample/convert sequence
1110=Interrupts at the completion of conversion for each 15th sample/convert sequence
•
•
•
0001=Interrupts at the completion of conversion for each 2nd sample/convert sequence
0000=Interrupts at the completion of conversion for each sample/convert sequence
bit 1
bit 0
BUFM: Buffer Fill Mode Select bit
1= Starts filling first half of buffer on first interrupt and the second half of buffer on next interrupt
0= Always starts filling buffer from the beginning
ALTS: Alternate Input Sample Mode Select bit
1= Uses channel input selects for Sample A on first sample and Sample B on next sample
0= Always uses channel input selects for Sample A
© 2007 Microchip Technology Inc.
Preliminary
DS70289A-page 165
PIC24HJ32GP202/204 and PIC24HJ16GP304
REGISTER 17-3: AD1CON3: ADC1 CONTROL REGISTER 3
R/W-0
ADRC
U-0
—
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
bit 8
R/W-0
SAMC<4:0>
bit 15
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
ADCS<7:0>
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15
ADRC: ADC Conversion Clock Source bit
1= ADC internal RC clock
0= Clock derived from system clock
bit 14-13
bit 12-8
Unimplemented: Read as ‘0’
SAMC<4:0>: Auto Sample Time bits
11111= 31 TAD
•
•
•
00001= 1 TAD
00000= 0 TAD
bit 7-0
ADCS<7:0>: ADC Conversion Clock Select bits
11111111= TCY ·(ADCS<7:0> + 1) = 256 ·TCY = TAD
•
•
•
00000010= TCY ·(ADCS<7:0> + 1) = 3 ·TCY = TAD
00000001= TCY ·(ADCS<7:0> + 1) = 2 ·TCY = TAD
00000000= TCY ·(ADCS<7:0> + 1) = 1 ·TCY = TAD
DS70289A-page 166
Preliminary
© 2007 Microchip Technology Inc.
PIC24HJ32GP202/204 and PIC24HJ16GP304
REGISTER 17-4: AD1CHS123: ADC1 INPUT CHANNEL 1, 2, 3 SELECT REGISTER
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
R/W-0
R/W-0
R/W-0
CH123NB<1:0>
CH123SB
bit 15
bit 8
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
R/W-0
R/W-0
R/W-0
CH123NA<1:0>
CH123SA
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-11
bit 10-9
Unimplemented: Read as ‘0’
CH123NB<1:0>: Channel 1, 2, 3 Negative Input Select for Sample B bits
PIC24HJ32GP202 devices only:
If AD12B = 1:
11= Reserved
10= Reserved
01= Reserved
00= Reserved
If AD12B = 0:
11= CH1 negative input is AN9, CH2 negative input is AN10, CH3 negative input is AN11
10= Reserved
01= CH1, CH2, CH3 negative input is VREF-
00= CH1, CH2, CH3 negative input is VREF-
PIC24HJ32GP204 and PIC24HJ16GP304 devices only:
If AD12B = 1:
11= Reserved
10= Reserved
01= Reserved
00= Reserved
If AD12B = 0:
11= CH1 negative input is AN9, CH2 negative input is AN10, CH3 negative input is AN11
10= CH1 negative input is AN6, CH2 negative input is AN7, CH3 negative input is AN8
01= CH1, CH2, CH3 negative input is VREF-
00= CH1, CH2, CH3 negative input is VREF-
bit 8
CH123SB: Channel 1, 2, 3 Positive Input Select for Sample B bit
If AD12B = 1:
1= Reserved
0= Reserved
If AD12B = 0:
1= CH1 positive input is AN3, CH2 positive input is AN4, CH3 positive input is AN5
0= CH1 positive input is AN0, CH2 positive input is AN1, CH3 positive input is AN2
bit 7-3
Unimplemented: Read as ‘0’
© 2007 Microchip Technology Inc.
Preliminary
DS70289A-page 167
PIC24HJ32GP202/204 and PIC24HJ16GP304
REGISTER 17-4: AD1CHS123: ADC1 INPUT CHANNEL 1, 2, 3 SELECT REGISTER (CONTINUED)
bit 2-1
CH123NA<1:0>: Channel 1, 2, 3 Negative Input Select for Sample A bits
PIC24HJ32GP202 devices only:
If AD12B = 1:
11= Reserved
10= Reserved
01= Reserved
00= Reserved
If AD12B = 0:
11= CH1 negative input is AN9, CH2 negative input is AN10, CH3 negative input is AN11
10= Reserved
01= CH1, CH2, CH3 negative input is VREF-
00= CH1, CH2, CH3 negative input is VREF-
PIC24HJ32GP204 and PIC24HJ16GP304 devices only:
If AD12B = 1:
11= Reserved
10= Reserved
01= Reserved
00= Reserved
If AD12B = 0:
11= CH1 negative input is AN9, CH2 negative input is AN10, CH3 negative input is AN11
10= CH1 negative input is AN6, CH2 negative input is AN7, CH3 negative input is AN8
01= CH1, CH2, CH3 negative input is VREF-
00= CH1, CH2, CH3 negative input is VREF-
bit 0
CH123SA: Channel 1, 2, 3 Positive Input Select for Sample A bit
If AD12B = 1:
1= Reserved
0= Reserved
If AD12B = 0:
1= CH1 positive input is AN3, CH2 positive input is AN4, CH3 positive input is AN5
0= CH1 positive input is AN0, CH2 positive input is AN1, CH3 positive input is AN2
DS70289A-page 168
Preliminary
© 2007 Microchip Technology Inc.
PIC24HJ32GP202/204 and PIC24HJ16GP304
REGISTER 17-5: AD1CHS0: ADC1 INPUT CHANNEL 0 SELECT REGISTER
R/W-0
U-0
—
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
bit 8
R/W-0
CH0NB
CH0SB<4:0>
bit 15
R/W-0
U-0
—
U-0
—
R/W-0
R/W-0
R/W-0
CH0NA
CH0SA<4:0>
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15
CH0NB: Channel 0 Negative Input Select for Sample B bit
1= Channel 0 negative input is AN1
0= Channel 0 negative input is VREF-
bit 14-13
bit 12-8
Unimplemented: Read as ‘0’
CH0SB<4:0>: Channel 0 Positive Input Select for Sample B bits
PIC24HJ32GP204 and PIC24HJ16GP304 devices only:
01100= Channel 0 positive input is AN12
•
•
•
00010= Channel 0 positive input is AN2
00001= Channel 0 positive input is AN1
00000= Channel 0 positive input is AN0
PIC24HJ32GP202 devices only:
01100= Channel 0 positive input is AN12
•
•
•
01000= Reserved
00111= Reserved
00110= Reserved
•
•
•
00010= Channel 0 positive input is AN2
00001= Channel 0 positive input is AN1
00000= Channel 0 positive input is AN0
bit 7
CH0NA: Channel 0 Negative Input Select for Sample A bit
1= Channel 0 negative input is AN1
0= Channel 0 negative input is VREF-
bit 6-5
Unimplemented: Read as ‘0’
© 2007 Microchip Technology Inc.
Preliminary
DS70289A-page 169
PIC24HJ32GP202/204 and PIC24HJ16GP304
REGISTER 17-5: AD1CHS0: ADC1 INPUT CHANNEL 0 SELECT REGISTER (CONTINUED)
bit 4-0
CH0SA<4:0>: Channel 0 Positive Input Select for Sample A bits
PIC24HJ32GP204 and PIC24HJ16GP304 devices only:
01100= Channel 0 positive input is AN12
•
•
•
00010= Channel 0 positive input is AN2
00001= Channel 0 positive input is AN1
00000= Channel 0 positive input is AN0
PIC24HJ32GP202 devices only:
01100= Channel 0 positive input is AN12
•
•
•
01000= Reserved
00111= Reserved
00110= Reserved
•
•
•
00010= Channel 0 positive input is AN2
00001= Channel 0 positive input is AN1
00000= Channel 0 positive input is AN0
DS70289A-page 170
Preliminary
© 2007 Microchip Technology Inc.
PIC24HJ32GP202/204 and PIC24HJ16GP304
REGISTER 17-6: AD1CSSL: ADC1 INPUT SCAN SELECT REGISTER LOW(1)
U-0
—
U-0
—
U-0
—
U-0
U-0
U-0
R/W-0
CSS9
R/W-0
CSS8
CSS12
CSS11
CSS10
bit 15
bit 8
R/W-0
CSS7
R/W-0
CSS6
R/W-0
CSS5
R/W-0
CSS4
R/W-0
CSS3
R/W-0
CSS2
R/W-0
CSS1
R/W-0
CSS0
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-0
CSS<12:0>: ADC Input Scan Selection bits
1= Select ANx for input scan
0= Skip ANx for input scan
Note 1: On devices without nine analog inputs, all AD1CSSL bits can be selected. However, inputs selected for
scan without a corresponding input on device will convert ADREF-.
REGISTER 17-7: AD1PCFGL: ADC1 PORT CONFIGURATION REGISTER LOW(1)
U-0
—
U-0
—
U-0
—
U-0
U-0
U-0
R/W-0
R/W-0
PCFG12
PCFG11
PCFG10
PCFG9
PCFG8
bit 15
bit 8
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
PCFG7
PCFG6
PCFG5
PCFG4
PCFG3
PCFG2
PCFG1
PCFG0
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-0
PCFG<12:0>: ADC Port Configuration Control bits
1= Port pin in Digital mode, port read input enabled, ADC input multiplexer connected to AVSS
0= Port pin in Analog mode, port read input disabled, ADC samples pin voltage
Note 1: On devices without nine analog inputs, all PCFG bits are R/W. However, PCFG bits are ignored on ports
without a corresponding input on device.
© 2007 Microchip Technology Inc.
Preliminary
DS70289A-page 171
PIC24HJ32GP202/204 and PIC24HJ16GP304
NOTES:
DS70289A-page 172
Preliminary
© 2007 Microchip Technology Inc.
PIC24HJ32GP202/204 and PIC24HJ16GP304
18.1 Configuration Bits
18.0 SPECIAL FEATURES
The Configuration bits can be programmed (read as
‘0’), or left unprogrammed (read as ‘1’), to select
various device configurations. These bits are mapped
starting at program memory location 0xF80000.
Note:
This data sheet summarizes the features
of the PIC24HJ32GP202/204 and
PIC24HJ16GP304 devices. It is not
intended to be a comprehensive reference
source. To complement the information in
this data sheet, refer to the “PIC24H
Family Reference Manual”.
The Device Configuration register map is shown in
Table 18-1.
The individual Configuration bit descriptions for the
FBS, FGS, FOSCSEL, FOSC, FWDT, FPOR and FICD
Configuration registers are shown in Table 18-2.
PIC24HJ32GP202/204
and
PIC24HJ16GP304
devices include several features that are intended to
maximize application flexibility and reliability, and mini-
mize cost through elimination of external components.
These are:
Note that address 0xF80000 is beyond the user pro-
gram memory space. It belongs to the configuration
memory space (0x800000-0xFFFFFF), which can only
be accessed using table reads and table writes.
• Flexible configuration
• Watchdog Timer (WDT)
The upper byte of all device Configuration registers
should always be ‘1111 1111.’ This makes them
appear to be NOPinstructions in the remote event that
their locations are ever executed by accident. Since
Configuration bits are not implemented in the
corresponding locations, writing ‘1’ to these locations
has no effect on device operation.
• Code Protection and CodeGuard™ Security
• JTAG Boundary Scan Interface
• In-Circuit Serial Programming™ (ICSP™)
• In-Circuit emulation
To prevent the inadvertent configuration changes dur-
ing code execution, all programmable Configuration
bits are write-once. After a bit is initially programmed
during a power cycle, it cannot be written to again.
Changing a device configuration requires that power to
the device be cycled.
TABLE 18-1: DEVICE CONFIGURATION REGISTER MAP
Address
Name
Bit 7
—
Bit 6
—
Bit 5
—
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
—
BSS<2:0>
BWRP
0xF80000 FBS
0xF80002 Reserved
0xF80004 FGS
Reserved(1)
—
—
—
—
—
—
—
—
—
—
GSS<1:0>
FNOSC<2:0>
GWRP
0xF80006 FOSCSEL
0xF80008 FOSC
0xF8000A FWDT
0xF8000C FPOR
0xF8000E Reserved
0xF80010 FUID0
0xF80012 FUID1
0xF80014 FUID2
0xF80016 FUID3
IESO
—
IOL1WAY
—
FCKSM<1:0>
OSCIOFNC POSCMD<1:0>
WDTPOST<3:0>
FWDTEN WINDIS
WDTPRE
—
—
—
ALTI2C
Reserved(1)
FPWRT<2:0>
User Unit ID Byte 0
User Unit ID Byte 1
User Unit ID Byte 2
User Unit ID Byte 3
Note 1: These reserved bits read as ‘1’ and must be programmed as ‘1’.
© 2007 Microchip Technology Inc.
Preliminary
DS70289A-page 173
PIC24HJ32GP202/204 and PIC24HJ16GP304
TABLE 18-2: PIC24HJ32GP202/204 AND PIC24HJ16GP304 CONFIGURATION BITS
DESCRIPTION
Bit Field
Register
Description
BWRP
FBS
Boot Segment Program Flash Write Protection
1= Boot segment may be written
0= Boot segment is write-protected
BSS<2:0>
FBS
PIC24HJ32GP202 and PIC24HJ32GP204 Devices Only
Boot Segment Program Flash Code Protection Size
X11= No Boot program Flash segment
Boot space is 768 Instruction Words (except interrupt vectors)
110= Standard security; boot program Flash segment ends at 0x0007FE
010= High security; boot program Flash segment ends at 0x0007FE
Boot space is 3840 Instruction Words (except interrupt vectors)
101= Standard security; boot program Flash segment, ends at
0x001FFE
001= High security; boot program Flash segment ends at 0x001FFE
Boot space is 7936 Instruction Words (except interrupt vectors)
100= Standard security; boot program Flash segment ends at 0x003FFE
000= High security; boot program Flash segment ends at 0x003FFE
BSS<2:0>
FBS
PIC24HJ16GP304 Devices Only
Boot Segment Program Flash Code Protection Size
X11= No Boot program Flash segment
Boot space is 768 Instruction Words (except interrupt vectors)
110= Standard security; boot program Flash segment ends at 0x0007FE
010= High security; boot program Flash segment ends at 0x0007FE
Boot space is 3840 Instruction Words (except interrupt vectors)
101= Standard security; boot program Flash segment, ends at
0x001FFE
001= High security; boot program Flash segment ends at 0x001FFE
Boot space is 5376 Instruction Words (except interrupt vectors)
100= Standard security; boot program Flash segment ends at 0x002BFE
000= High security; boot program Flash segment ends at 0x002BFE
GSS<1:0>
FGS
General Segment Code-Protect bit
11= User program memory is not code-protected
10= Standard security
0x= High security
GWRP
IESO
FGS
General Segment Write-Protect bit
1= User program memory is not write-protected
0= User program memory is write-protected
FOSCSEL
Two-speed Oscillator Start-up Enable bit
1= Start-up device with FRC, then automatically switch to the
user-selected oscillator source when ready
0= Start-up device with user-selected oscillator source
FNOSC<2:0>
FOSCSEL
Initial Oscillator Source Selection bits
111= Internal Fast RC (FRC) oscillator with postscaler
110= Internal Fast RC (FRC) oscillator with divide-by-16
101= LPRC oscillator
100= Secondary (LP) oscillator
011= Primary (XT, HS, EC) oscillator with PLL
010= Primary (XT, HS, EC) oscillator
001= Internal Fast RC (FRC) oscillator with PLL
000= FRC oscillator
DS70289A-page 174
Preliminary
© 2007 Microchip Technology Inc.
PIC24HJ32GP202/204 and PIC24HJ16GP304
TABLE 18-2: PIC24HJ32GP202/204 AND PIC24HJ16GP304 CONFIGURATION BITS DESCRIPTION
(CONTINUED)
Bit Field
Register
Description
FCKSM<1:0>
FOSC
Clock Switching Mode bits
1x= Clock switching is disabled, Fail-Safe Clock Monitor is disabled
01= Clock switching is enabled, Fail-Safe Clock Monitor is disabled
00= Clock switching is enabled, Fail-Safe Clock Monitor is enabled
IOL1WAY
OSCIOFNC
FOSC
FOSC
FOSC
Peripheral Pin Select Configuration
1= Allow only one re-configuration
0= Allow multiple re-configurations
OSC2 Pin Function bit (except in XT and HS modes)
1= OSC2 is clock output
0= OSC2 is general purpose digital I/O pin
POSCMD<1:0>
Primary Oscillator Mode Select bits
11= Primary oscillator disabled
10= HS Crystal Oscillator mode
01= XT Crystal Oscillator mode
00= EC (External Clock) mode
FWDTEN
FWDT
Watchdog Timer Enable bit
1= Watchdog Timer always enabled (LPRC oscillator cannot be disabled.
Clearing the SWDTEN bit in the RCON register will have no effect.)
0= Watchdog Timer enabled/disabled by user software (LPRC can be
disabled by clearing the SWDTEN bit in the RCON register)
WINDIS
WDTPRE
FWDT
FWDT
FWDT
Watchdog Timer Window Enable bit
1= Watchdog Timer in Non-Window mode
0= Watchdog Timer in Window mode
Watchdog Timer Prescaler bit
1= 1:128
0= 1:32
WDTPOST<3:0>
Watchdog Timer Postscaler bits
1111= 1:32,768
1110= 1:16,384
.
.
.
0001= 1:2
0000= 1:1
ALTI2C
FPOR
FPOR
Alternate I2C pins
1 = I2C mapped to SDA1/SCL1 pins
0 = I2C mapped to ASDA1/ASCL1 pins
FPWRT<2:0>
Power-on Reset Timer Value Select bits
111= PWRT = 128 ms
110= PWRT = 64 ms
101= PWRT = 32 ms
100= PWRT = 16 ms
011= PWRT = 8 ms
010= PWRT = 4 ms
001= PWRT = 2 ms
000= PWRT = Disabled
© 2007 Microchip Technology Inc.
Preliminary
DS70289A-page 175
PIC24HJ32GP202/204 and PIC24HJ16GP304
A BOR generates a Reset pulse, which resets the
device. The BOR selects the clock source, based on
the device Configuration bit values (FNOSC<2:0> and
POSCMD<1:0>).
18.2 On-Chip Voltage Regulator
All
of
the
PIC24HJ32GP202/204
and
PIC24HJ16GP304 devices power their core digital
logic at a nominal 2.5V. This can create a conflict for
designs that are required to operate at a higher typical
voltage, such as 3.3V. To simplify system design, all
If an oscillator mode is selected, the BOR activates the
Oscillator Start-up Timer (OST). The system clock is
held until OST expires. If the PLL is used, the clock is
held until the LOCK bit (OSCCON<5>) is ‘1’.
devices
in
the
PIC24HJ32GP202/204
and
PIC24HJ16GP304 family incorporate an on-chip regu-
lator that allows the device to run its core logic from
VDD.
Concurrently, the PWRT time-out (TPWRT) will be
applied before the internal Reset is released. If TPWRT
= 0 and a crystal oscillator is being used, a nominal
delay of TFSCM = 100is applied. The total delay in this
case is TFSCM.
The regulator provides power to the core from the other
VDD pins. When the regulator is enabled, a low-ESR
(less than 5 ohms) capacitor (such as tantalum or
ceramic) must be connected to the VDDCORE/VCAP pin
(Figure 18-1). This helps to maintain the stability of the
regulator. The recommended value for the filter capac-
itor is provided in Section TABLE 21-13: “Internal
Voltage Regulator Specifications” located in
Section 21.1 “DC Characteristics”.
The BOR Status bit (RCON<1>) is set to indicate that
a BOR has occurred. If the BOR circuit is enabled, it
continues to operate while in Sleep or Idle mode and
resets the device in case VDD falls below the BOR
threshold voltage.
On a POR, it takes approximately 20 μs for the on-chip
voltage regulator to generate an output voltage. During
this time, designated as TSTARTUP, code execution is
disabled. TSTARTUP is applied every time the device
resumes operation after any power-down.
FIGURE 18-1:
CONNECTIONS FOR THE
ON-CHIP VOLTAGE
REGULATOR(1)
3.3V
PIC24H
VDD
VDDCORE/VCAP
VSS
CF
Note 1: These are typical operating voltages. Refer
to Section TABLE 21-13: “Internal Volt-
age Regulator Specifications” located in
Section 21.1 “DC Characteristics” for the
full operating ranges of VDD and VDDCORE.
18.3 BOR: Brown-Out Reset
The Brown-out Reset (BOR) module is based on an
internal voltage reference circuit that monitors the reg-
ulated voltage VDDCORE. The main purpose of the BOR
module is to generate a device Reset when a brown-
out condition occurs. Brown-out conditions are gener-
ally caused by glitches on the AC mains (for example,
missing portions of the AC cycle waveform due to bad
power transmission lines, or voltage sags due to exces-
sive current draw when a large inductive load is turned
on).
DS70289A-page 176
Preliminary
© 2007 Microchip Technology Inc.
PIC24HJ32GP202/204 and PIC24HJ16GP304
18.4.2
SLEEP AND IDLE MODES
18.4 Watchdog Timer (WDT)
If the WDT is enabled, it will continue to run during
Sleep or Idle modes. When the WDT time-out occurs,
the device will wake the device and code execution will
continue from where the PWRSAV instruction was
executed. The corresponding SLEEP or IDLE bits
(RCON<3,2>) will need to be cleared in software after
the device wakes up.
For PIC24HJ32GP202/204 and PIC24HJ16GP304
devices, the WDT is driven by the LPRC oscillator.
When the WDT is enabled, the clock source is also
enabled.
18.4.1
PRESCALER/POSTSCALER
The nominal WDT clock source from LPRC is 32 kHz.
This feeds a prescaler than can be configured for either
5-bit (divide-by-32) or 7-bit (divide-by-128) operation.
The prescaler is set by the WDTPRE Configuration bit.
With a 32 kHz input, the prescaler yields a nominal
WDT time-out period (TWDT) of 1 ms in 5-bit mode, or
4 ms in 7-bit mode.
18.4.3
ENABLING WDT
The WDT is enabled or disabled by the FWDTEN
Configuration bit in the FWDT Configuration register.
When the FWDTEN Configuration bit is set, the WDT is
always enabled.
The WDT flag bit, WDTO (RCON<4>), is not automatically
cleared following a WDT time-out. To detect subsequent
WDT events, the flag must be cleared in software.
A variable postscaler divides down the WDT prescaler
output and allows for a wide range of time-out periods.
The postscaler is controlled by the WDTPOST<3:0>
Configuration bits (FWDT<3:0>), which allows the
selection of 16 settings, from 1:1 to 1:32,768. Using the
prescaler and postscaler, time-out periods ranging
from 1 ms to 131 seconds can be achieved.
The WDT can be optionally controlled in software when
the FWDTEN Configuration bit has been programmed
to ‘0’. The WDT is enabled in software by setting the
SWDTEN control bit (RCON<5>). The SWDTEN
control bit is cleared on any device Reset. The software
WDT option allows the user application to enable the
WDT for critical code segments and disable the WDT
during non-critical segments for maximum power sav-
ings.
The WDT, prescaler and postscaler are reset:
• On any device Reset
• On the completion of a clock switch, whether
invoked by software (i.e., setting the OSWEN bit
after changing the NOSC bits) or by hardware
(i.e., Fail-Safe Clock Monitor)
Note:
If the WINDIS bit (FWDT<6>) is cleared, the
CLRWDTinstruction should be executed by
the application software only during the last
1/4 of the WDT period. This CLRWDT
window can be determined by using a timer.
If a CLRWDTinstruction is executed before
this window, a WDT Reset occurs.
• When a PWRSAVinstruction is executed (Sleep or
Idle mode is entered)
• When the device exits Sleep or Idle mode to
resume normal operation
• By a CLRWDTinstruction during normal execution
Note:
The CLRWDT and PWRSAV instructions
clear the prescaler and postscaler counts
when executed.
FIGURE 18-2:
WDT BLOCK DIAGRAM
All Device Resets
Transition to New Clock Source
Exit Sleep or Idle Mode
PWRSAVInstruction
CLRWDTInstruction
Watchdog Timer
Sleep/Idle
WDTPRE
Prescaler
WDTPOST<3:0>
SWDTEN
FWDTEN
WDT
Wake-up
1
0
RS
RS
Postscaler
WDT
Reset
(divide by N1)
(divide by N2)
LPRC Clock
WDT Window Select
WINDIS
CLRWDTInstruction
© 2007 Microchip Technology Inc.
Preliminary
DS70289A-page 177
PIC24HJ32GP202/204 and PIC24HJ16GP304
interrupts and peripherals) on a single chip. This
feature helps to protect individual Intellectual Property
in collaborative system designs.
18.5 JTAG Interface
PIC24HJ32GP202/204
and
PIC24HJ16GP304
devices implement a JTAG interface, which supports
boundary scan device testing, as well as in-circuit pro-
gramming. Detailed information on this interface will be
provided in future revisions of the document.
When coupled with software encryption libraries,
CodeGuard Security can be used to securely update
Flash even when multiple IPs reside on the single chip.
The code protection features are controlled by the
Configuration registers: FBS and FGS. The Secure
segment and RAM is not implemented.
18.6 Code Protection and
CodeGuard™ Security
Note:
Refer to CodeGuard Security Reference
Manual (DS70180) for further information
on usage, configuration and operation of
CodeGuard Security.
The PIC24HJ32GP202/204 and PIC24HJ16GP304
product families offer the intermediate implementation
of CodeGuard Security. CodeGuard Security allows
multiple parties to securely share resources (memory,
TABLE 18-3: CODE FLASH SECURITY
SEGMENT SIZES FOR
32 KBYTE DEVICES
TABLE 18-4: CODE FLASH SECURITY
SEGMENT SIZES FOR
16 KBYTE DEVICES
CONFIG BITS
CONFIG BITS
000000h
VS = 256 IW
000000h
VS = 256 IW
0001FEh
0001FEh
000200h
000200h
0007FEh
0007FEh
BSS<2:0>=x11
BSS<2:0>=x11
000800h
001FFEh
000800h
001FFEh
002000h
003FFEh
004000h
002000h
0K
0K
GS = 3840 IW
GS = 3840 IW
0057FEh
000000h
002BFEh
000000h
0001FEh
000200h
0007FEh
000800h
001FFEh
002000h
VS = 256 IW
BS = 768 IW
VS = 256 IW
BS = 768 IW
0001FEh
000200h
0007FEh
000800h
001FFEh
002000h
003FFEh
004000h
BSS<2:0>=x10
256
BSS<2:0>=x10
256
GS = 10249 IW
GS = 4608 IW
0057FEh
002BFEh
000000h
0001FEh
000200h
0007FEh
000800h
001FFEh
002000h
003FFEh
004000h
000000h
0001FEh
000200h
0007FEh
000800h
001FFEh
002000h
VS = 256 IW
BS = 3840 IW
VS = 256 IW
BS = 3840 IW
BSS<2:0>=x01
768
BSS<2:0>=x01
768
GS = 7168 IW
GS = 1536 IW
0057FEh
002BFEh
000000h
0001FEh
000200h
0007FEh
000800h
001FFEh
002000h
003FFEh
004000h
000000h
0001FEh
000200h
0007FEh
000800h
001FFEh
002000h
VS = 256 IW
BS = 7936 IW
VS = 256 IW
BS = 5376 IW
BSS<2:0>=x00
1792
BSS<2:0>=x00
1792
GS = 3072 IW
0057FEh
002BFEh
DS70289A-page 178
Preliminary
© 2007 Microchip Technology Inc.
PIC24HJ32GP202/204 and PIC24HJ16GP304
18.7
In-Circuit Serial Programming
18.8 In-Circuit Debugger
PIC24HJ32GP202/204 and PIC24HJ16GP304 family
microcontrollers can be serially programmed while in
the end application circuit. This is done with two lines
for clock and data, and three other lines for power,
ground and the programming sequence. Serial pro-
gramming allows customers to manufacture boards
with unprogrammed devices and then program the
microcontroller just before shipping the product. Serial
programming also allows the most recent firmware or a
custom firmware to be programmed. Refer to the
“dsPIC30F/33F Flash Programming Specification”
(DS70152) document for details about In-Circuit Serial
Programming (ICSP).
When MPLAB® ICD 2 is selected as a debugger, the in-
circuit debugging functionality is enabled. This function
allows simple debugging functions when used with
MPLAB IDE. Debugging functionality is controlled
through the Emulation/Debug Clock (EMUCx) and
Emulation/Debug Data (EMUDx) pin functions.
Any of the following three pairs of debugging clock/data
pins can be used:
• PGC1/EMUC1 and PGD1/EMUD1
• PGC2/EMUC2 and PGD2/EMUD2
• PGC3/EMUC3 and PGD3/EMUD3
To make use of the in-circuit debugger function of the
device, the design must implement ICSP connections
to MCLR, VDD, VSS, PGC, PGD and the EMUDx/
EMUCx pin pair. In addition, when the feature is
enabled, some of the resources are not available for
general use. These resources include the first 80 bytes
of data RAM and two I/O pins.
Any of the following three pairs of programming clock/
data pins can be used:
• PGC1/EMUC1 and PGD1/EMUD1
• PGC2/EMUC2 and PGD2/EMUD2
• PGC3/EMUC3 and PGD3/EMUD3
© 2007 Microchip Technology Inc.
Preliminary
DS70289A-page 179
PIC24HJ32GP202/204 and PIC24HJ16GP304
NOTES:
DS70289A-page 180
Preliminary
© 2007 Microchip Technology Inc.
PIC24HJ32GP202/204 and PIC24HJ16GP304
Most bit-oriented instructions (including simple
rotate/shift instructions) have two operands:
19.0 INSTRUCTION SET SUMMARY
Note:
This data sheet summarizes the features
of this group of PIC24HJ32GP202/204
and PIC24HJ16GP304 devices. It is not
intended to be a comprehensive reference
source. To complement the information in
this data sheet, refer to the “PIC24H
Family Reference Manual”.
• The W register (with or without an address
modifier) or file register (specified by the value of
‘Ws’ or ‘f’)
• The bit in the W register or file register
(specified by a literal value or indirectly by the
contents of register ‘Wb’)
The literal instructions that involve data movement may
use some of the following operands:
The PIC24H instruction set is identical to that of the
PIC24F, and is a subset of the dsPIC30F/33F
instruction set.
• A literal value to be loaded into a W register or file
register (specified by the value of ‘k’)
Most instructions are a single program memory word
(24 bits). Only three instructions require two program
memory locations.
• The W register or file register where the literal
value is to be loaded (specified by ‘Wb’ or ‘f’)
However, literal instructions that involve arithmetic or
logical operations use some of the following operands:
Each single-word instruction is a 24-bit word, divided
into an 8-bit opcode, which specifies the instruction
type and one or more operands, which further specify
the operation of the instruction.
• The first source operand which is a register ‘Wb’
without any address modifier
• The second source operand which is a literal
value
The instruction set is highly orthogonal and is grouped
into five basic categories:
• The destination of the result (only if not the same
as the first source operand) which is typically a
register ‘Wd’ with or without an address modifier
• Word or byte-oriented operations
• Bit-oriented operations
• Literal operations
The control instructions may use some of the following
operands:
• DSP operations
• Control operations
• A program memory address
Table 19-1 shows the general symbols used in
describing the instructions.
• The mode of the table read and table write
instructions
The PIC24H instruction set summary in Table 19-2 lists
all the instructions, along with the status flags affected
by each instruction.
Most word or byte-oriented W register instructions
(including barrel shift instructions) have three
operands:
• The first source operand which is typically a
register ‘Wb’ without any address modifier
• The second source operand which is typically a
register ‘Ws’ with or without an address modifier
• The destination of the result which is typically a
register ‘Wd’ with or without an address modifier
However, word or byte-oriented file register instruc-
tions have two operands:
• The file register specified by the value ‘f’
• The destination, which could either be the file
register ‘f’ or the W0 register, which is denoted as
‘WREG’
© 2007 Microchip Technology Inc.
Preliminary
DS70289A-page 181
PIC24HJ32GP202/204 and PIC24HJ16GP304
All instructions are single word. Ceratian of them were
made double word instructions so that all the required
information is available in these 48 bits. In the second
word, the 8 MSbs are ‘0’s. If this second word is exe-
cuted as an instruction (by itself), it will execute as a
NOP.
reads and writes and RETURN/RETFIE instructions,
which are single-word instructions but take two or three
cycles. Certain instructions that involve skipping over the
subsequent instruction require either two or three cycles
if the skip is performed, depending on whether the
instruction being skipped is a single-word or double word
instruction. Moreover, double word moves require two
cycles. The double word instructions execute in two
instruction cycles.
Most single-word instructions are executed in a single
instruction cycle, unless a conditional test is true, or the
program counter is changed as a result of the instruc-
tion. In these cases, the execution takes two instruction
cycles with the additional instruction cycle(s) executed
as a NOP. Notable exceptions are the BRA (uncondi-
tional/computed branch), indirect CALL/GOTO, all table
Note:
For more details on the instruction set,
refer to the “dsPIC30F/33F Programmer’s
Reference Manual” (DS70157).
TABLE 19-1: SYMBOLS USED IN OPCODE DESCRIPTIONS
Field
Description
#text
(text)
[text]
{ }
Means literal defined by “text”
Means “content of text”
Means “the location addressed by text”
Optional field or operation
Register bit field
<n:m>
.b
Byte mode selection
.d
Double Word mode selection
Shadow register select
.S
.w
Word mode selection (default)
bit4
4-bit bit selection field (used in word addressed instructions) ∈ {0...15}
MCU Status bits: Carry, Digit Carry, Negative, Overflow, Sticky Zero
Absolute address, label or expression (resolved by the linker)
File register address ∈ {0x0000...0x1FFF}
1-bit unsigned literal ∈ {0,1}
C, DC, N, OV, Z
Expr
f
lit1
lit4
4-bit unsigned literal ∈ {0...15}
lit5
5-bit unsigned literal ∈ {0...31}
lit8
8-bit unsigned literal ∈ {0...255}
lit10
lit14
lit16
lit23
None
PC
10-bit unsigned literal ∈ {0...255} for Byte mode, {0:1023} for Word mode
14-bit unsigned literal ∈ {0...16384}
16-bit unsigned literal ∈ {0...65535}
23-bit unsigned literal ∈ {0...8388608}; LSB must be ‘0’
Field does not require an entry, may be blank
Program Counter
Slit10
Slit16
Slit6
Wb
10-bit signed literal ∈ {-512...511}
16-bit signed literal ∈ {-32768...32767}
6-bit signed literal ∈ {-16...16}
Base W register ∈ {W0..W15}
Wd
Destination W register ∈ { Wd, [Wd], [Wd++], [Wd--], [++Wd], [--Wd] }
Wdo
Destination W register ∈
{ Wnd, [Wnd], [Wnd++], [Wnd--], [++Wnd], [--Wnd], [Wnd+Wb] }
Wm,Wn
Dividend, Divisor working register pair (direct addressing)
Wm*Wm
Multiplicand and Multiplier working register pair for Square instructions ∈
{W4 * W4,W5 * W5,W6 * W6,W7 * W7}
Wn
One of 16 working registers ∈ {W0..W15}
DS70289A-page 182
Preliminary
© 2007 Microchip Technology Inc.
PIC24HJ32GP202/204 and PIC24HJ16GP304
TABLE 19-1: SYMBOLS USED IN OPCODE DESCRIPTIONS (CONTINUED)
Field
Description
Wnd
Wns
WREG
Ws
One of 16 destination working registers ∈ {W0..W15}
One of 16 source working registers ∈ {W0..W15}
W0 (working register used in file register instructions)
Source W register ∈ { Ws, [Ws], [Ws++], [Ws--], [++Ws], [--Ws] }
Wso
Source W register ∈
{ Wns, [Wns], [Wns++], [Wns--], [++Wns], [--Wns], [Wns+Wb] }
© 2007 Microchip Technology Inc.
Preliminary
DS70289A-page 183
PIC24HJ32GP202/204 and PIC24HJ16GP304
TABLE 19-2: INSTRUCTION SET OVERVIEW
Base
Instr
#
Assembly
Mnemonic
# of
# of
Status Flags
Affected
Assembly Syntax
Description
Words Cycles
ADD
f
f = f + WREG
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
C,DC,N,OV,Z
C,DC,N,OV,Z
C,DC,N,OV,Z
C,DC,N,OV,Z
C,DC,N,OV,Z
C,DC,N,OV,Z
C,DC,N,OV,Z
C,DC,N,OV,Z
C,DC,N,OV,Z
C,DC,N,OV,Z
N,Z
1
ADD
ADDC
AND
ASR
ADD
f,WREG
WREG = f + WREG
1
ADD
#lit10,Wn
Wb,Ws,Wd
Wb,#lit5,Wd
f
Wd = lit10 + Wd
1
ADD
Wd = Wb + Ws
1
ADD
Wd = Wb + lit5
1
1
2
3
4
ADDC
ADDC
ADDC
ADDC
ADDC
AND
f = f + WREG + (C)
f,WREG
WREG = f + WREG + (C)
Wd = lit10 + Wd + (C)
Wd = Wb + Ws + (C)
Wd = Wb + lit5 + (C)
f = f .AND. WREG
1
#lit10,Wn
Wb,Ws,Wd
Wb,#lit5,Wd
f
1
1
1
1
AND
f,WREG
WREG = f .AND. WREG
Wd = lit10 .AND. Wd
Wd = Wb .AND. Ws
Wd = Wb .AND. lit5
1
N,Z
AND
#lit10,Wn
Wb,Ws,Wd
Wb,#lit5,Wd
f
1
N,Z
AND
1
N,Z
AND
1
N,Z
ASR
f = Arithmetic Right Shift f
WREG = Arithmetic Right Shift f
Wd = Arithmetic Right Shift Ws
Wnd = Arithmetic Right Shift Wb by Wns
Wnd = Arithmetic Right Shift Wb by lit5
Bit Clear f
1
C,N,OV,Z
C,N,OV,Z
C,N,OV,Z
N,Z
ASR
f,WREG
1
ASR
Ws,Wd
1
ASR
Wb,Wns,Wnd
Wb,#lit5,Wnd
f,#bit4
Ws,#bit4
C,Expr
1
ASR
1
N,Z
5
6
BCLR
BRA
BCLR
BCLR
BRA
1
None
Bit Clear Ws
1
None
Branch if Carry
1 (2)
1 (2)
1 (2)
1 (2)
1 (2)
1 (2)
1 (2)
1 (2)
1 (2)
1 (2)
1 (2)
1 (2)
1 (2)
2
None
BRA
GE,Expr
GEU,Expr
GT,Expr
GTU,Expr
LE,Expr
LEU,Expr
LT,Expr
LTU,Expr
N,Expr
Branch if greater than or equal
Branch if unsigned greater than or equal
Branch if greater than
Branch if unsigned greater than
Branch if less than or equal
Branch if unsigned less than or equal
Branch if less than
None
BRA
None
BRA
None
BRA
None
BRA
None
BRA
None
BRA
None
BRA
Branch if unsigned less than
Branch if Negative
None
BRA
None
BRA
NC,Expr
NN,Expr
NZ,Expr
Expr
Branch if Not Carry
None
BRA
Branch if Not Negative
Branch if Not Zero
None
BRA
None
BRA
Branch Unconditionally
Branch if Zero
None
BRA
Z,Expr
1 (2)
2
None
BRA
Wn
Computed Branch
None
7
BSET
BSW
BSET
BSET
BSW.C
BSW.Z
BTG
f,#bit4
Ws,#bit4
Ws,Wb
Bit Set f
1
None
Bit Set Ws
1
None
8
Write C bit to Ws<Wb>
Write Z bit to Ws<Wb>
Bit Toggle f
1
None
Ws,Wb
1
None
9
BTG
f,#bit4
Ws,#bit4
f,#bit4
1
None
BTG
Bit Toggle Ws
1
None
10
BTSC
BTSC
Bit Test f, Skip if Clear
1
None
(2 or 3)
BTSC
BTSS
BTSS
Ws,#bit4
f,#bit4
Ws,#bit4
Bit Test Ws, Skip if Clear
Bit Test f, Skip if Set
1
1
1
1
None
None
None
(2 or 3)
11
BTSS
1
(2 or 3)
Bit Test Ws, Skip if Set
1
(2 or 3)
DS70289A-page 184
Preliminary
© 2007 Microchip Technology Inc.
PIC24HJ32GP202/204 and PIC24HJ16GP304
TABLE 19-2: INSTRUCTION SET OVERVIEW (CONTINUED)
Base
Instr
#
Assembly
Mnemonic
# of
# of
Status Flags
Affected
Assembly Syntax
Description
Words Cycles
12
BTST
BTST
f,#bit4
Ws,#bit4
Ws,#bit4
Ws,Wb
Bit Test f
1
1
1
1
1
1
1
1
2
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
2
2
1
1
1
1
1
1
Z
BTST.C
BTST.Z
BTST.C
BTST.Z
BTSTS
Bit Test Ws to C
Bit Test Ws to Z
C
Z
Bit Test Ws<Wb> to C
Bit Test Ws<Wb> to Z
Bit Test then Set f
Bit Test Ws to C, then Set
Bit Test Ws to Z, then Set
Call subroutine
C
Ws,Wb
Z
Z
13
BTSTS
f,#bit4
BTSTS.C Ws,#bit4
BTSTS.Z Ws,#bit4
C
Z
14
15
CALL
CLR
CALL
CALL
CLR
lit23
Wn
None
None
None
None
None
WDTO,Sleep
N,Z
Call indirect subroutine
f = 0x0000
f
CLR
WREG
Ws
WREG = 0x0000
Ws = 0x0000
CLR
16
17
CLRWDT
COM
CLRWDT
COM
Clear Watchdog Timer
f = f
f
COM
f,WREG
WREG = f
N,Z
COM
CP
Ws,Wd
Wd = Ws
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
N,Z
18
CP
f
Compare f with WREG
C,DC,N,OV,Z
C,DC,N,OV,Z
C,DC,N,OV,Z
C,DC,N,OV,Z
C,DC,N,OV,Z
C,DC,N,OV,Z
C,DC,N,OV,Z
C,DC,N,OV,Z
CP
Wb,#lit5
Compare Wb with lit5
CP
Wb,Ws
Compare Wb with Ws (Wb – Ws)
Compare f with 0x0000
19
20
CP0
CPB
CP0
CP0
CPB
CPB
CPB
f
Ws
Compare Ws with 0x0000
Compare f with WREG, with Borrow
Compare Wb with lit5, with Borrow
f
Wb,#lit5
Wb,Ws
Compare Wb with Ws, with Borrow
(Wb – Ws – C)
21
22
23
24
CPSEQ
CPSGT
CPSLT
CPSNE
CPSEQ
CPSGT
CPSLT
CPSNE
Wb, Wn
Wb, Wn
Wb, Wn
Wb, Wn
Compare Wb with Wn, skip if =
Compare Wb with Wn, skip if >
Compare Wb with Wn, skip if <
Compare Wb with Wn, skip if ¼
1
1
1
1
1
None
None
None
None
(2 or 3)
1
(2 or 3)
1
(2 or 3)
1
(2 or 3)
25
26
DAW
DEC
DAW
Wn
Wn = decimal adjust Wn
f = f – 1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
C
DEC
f
C,DC,N,OV,Z
C,DC,N,OV,Z
C,DC,N,OV,Z
C,DC,N,OV,Z
C,DC,N,OV,Z
C,DC,N,OV,Z
None
DEC
f,WREG
Ws,Wd
f
WREG = f – 1
DEC
Wd = Ws – 1
27
DEC2
DEC2
DEC2
DEC2
DISI
f = f – 2
f,WREG
Ws,Wd
#lit14
WREG = f – 2
Wd = Ws – 2
28
29
DISI
DIV
Disable Interrupts for k instruction cycles
DIV.S
DIV.SD
DIV.U
DIV.UD
EXCH
Wm,Wn
Wm,Wn
Wm,Wn
Wm,Wn
Wns,Wnd
Ws,Wnd
Ws,Wnd
Ws,Wnd
Expr
Signed 16/16-bit Integer Divide
Signed 32/16-bit Integer Divide
Unsigned 16/16-bit Integer Divide
Unsigned 32/16-bit Integer Divide
Swap Wns with Wnd
1
1
1
1
1
1
1
1
2
1
18
18
18
18
1
N,Z,C,OV
N,Z,C,OV
N,Z,C,OV
N,Z,C,OV
None
30
31
32
33
34
EXCH
FBCL
FF1L
FF1R
GOTO
FBCL
Find Bit Change from Left (MSb) Side
Find First One from Left (MSb) Side
Find First One from Right (LSb) Side
Go to address
1
C
FF1L
1
C
FF1R
1
C
GOTO
2
None
GOTO
Wn
Go to indirect
2
None
© 2007 Microchip Technology Inc.
Preliminary
DS70289A-page 185
PIC24HJ32GP202/204 and PIC24HJ16GP304
TABLE 19-2: INSTRUCTION SET OVERVIEW (CONTINUED)
Base
Instr
#
Assembly
Mnemonic
# of
# of
Status Flags
Affected
Assembly Syntax
Description
Words Cycles
35
INC
INC
f
f = f + 1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
2
2
1
1
1
1
C,DC,N,OV,Z
C,DC,N,OV,Z
C,DC,N,OV,Z
C,DC,N,OV,Z
C,DC,N,OV,Z
C,DC,N,OV,Z
N,Z
INC
f,WREG
Ws,Wd
WREG = f + 1
Wd = Ws + 1
f = f + 2
INC
36
37
INC2
IOR
INC2
INC2
INC2
IOR
f
f,WREG
Ws,Wd
WREG = f + 2
Wd = Ws + 2
f
f = f .IOR. WREG
IOR
f,WREG
#lit10,Wn
Wb,Ws,Wd
Wb,#lit5,Wd
#lit14
f
WREG = f .IOR. WREG
Wd = lit10 .IOR. Wd
N,Z
IOR
N,Z
IOR
Wd = Wb .IOR. Ws
N,Z
IOR
Wd = Wb .IOR. lit5
N,Z
38
39
LNK
LSR
LNK
Link Frame Pointer
None
LSR
f = Logical Right Shift f
C,N,OV,Z
C,N,OV,Z
C,N,OV,Z
N,Z
LSR
f,WREG
Ws,Wd
WREG = Logical Right Shift f
Wd = Logical Right Shift Ws
Wnd = Logical Right Shift Wb by Wns
Wnd = Logical Right Shift Wb by lit5
Move f to Wn
LSR
LSR
Wb,Wns,Wnd
Wb,#lit5,Wnd
f,Wn
LSR
N,Z
40
MOV
MOV
None
MOV
f
Move f to f
N,Z
MOV
f,WREG
#lit16,Wn
#lit8,Wn
Wn,f
Move f to WREG
N,Z
MOV
Move 16-bit literal to Wn
Move 8-bit literal to Wn
None
MOV.b
MOV
None
Move Wn to f
None
MOV
Wso,Wdo
WREG,f
Wns,Wd
Ws,Wnd
Wb,Ws,Wnd
Wb,Ws,Wnd
Wb,Ws,Wnd
Wb,Ws,Wnd
Move Ws to Wd
None
MOV
Move WREG to f
N,Z
MOV.D
MOV.D
MUL.SS
MUL.SU
MUL.US
MUL.UU
Move Double from W(ns):W(ns + 1) to Wd
Move Double from Ws to W(nd + 1):W(nd)
{Wnd + 1, Wnd} = signed(Wb) * signed(Ws)
{Wnd + 1, Wnd} = signed(Wb) * unsigned(Ws)
{Wnd + 1, Wnd} = unsigned(Wb) * signed(Ws)
None
None
41
MUL
None
None
None
{Wnd + 1, Wnd} = unsigned(Wb) *
unsigned(Ws)
None
MUL.SU
MUL.UU
Wb,#lit5,Wnd
Wb,#lit5,Wnd
{Wnd + 1, Wnd} = signed(Wb) * unsigned(lit5)
1
1
1
1
None
None
{Wnd + 1, Wnd} = unsigned(Wb) *
unsigned(lit5)
MUL
NEG
NEG
f
W3:W2 = f * WREG
f = f + 1
1
1
1
1
1
1
None
42
NEG
f
C,DC,N,OV,Z
C,DC,N,OV,Z
f,WREG
Ws,Wd
WREG = f + 1
NEG
Wd = Ws + 1
1
1
1
1
1
1
1
1
1
1
1
2
C,DC,N,OV,Z
None
43
44
NOP
POP
NOP
No Operation
NOPR
POP
No Operation
None
f
Pop f from Top-of-Stack (TOS)
Pop from Top-of-Stack (TOS) to Wdo
None
POP
Wdo
Wnd
None
POP.D
Pop from Top-of-Stack (TOS) to
W(nd):W(nd + 1)
None
POP.S
PUSH
Pop Shadow Registers
1
1
1
1
1
1
1
1
1
2
1
1
All
None
45
46
PUSH
f
Push f to Top-of-Stack (TOS)
Push Wso to Top-of-Stack (TOS)
Push W(ns):W(ns + 1) to Top-of-Stack (TOS)
Push Shadow Registers
PUSH
Wso
Wns
None
PUSH.D
PUSH.S
PWRSAV
None
None
PWRSAV
#lit1
Go into Sleep or Idle mode
WDTO,Sleep
DS70289A-page 186
Preliminary
© 2007 Microchip Technology Inc.
PIC24HJ32GP202/204 and PIC24HJ16GP304
TABLE 19-2: INSTRUCTION SET OVERVIEW (CONTINUED)
Base
Instr
#
Assembly
Mnemonic
# of
# of
Status Flags
Affected
Assembly Syntax
Description
Words Cycles
47
RCALL
RCALL
RCALL
REPEAT
REPEAT
RESET
RETFIE
RETLW
RETURN
RLC
Expr
Wn
Relative Call
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
2
2
None
None
Computed Call
48
REPEAT
#lit14
Wn
Repeat Next Instruction lit14 + 1 times
Repeat Next Instruction (Wn) + 1 times
Software device Reset
1
None
1
None
49
50
51
52
53
RESET
RETFIE
RETLW
RETURN
RLC
1
None
Return from interrupt
3 (2)
3 (2)
3 (2)
1
None
#lit10,Wn
Return with literal in Wn
Return from Subroutine
f = Rotate Left through Carry f
WREG = Rotate Left through Carry f
Wd = Rotate Left through Carry Ws
f = Rotate Left (No Carry) f
WREG = Rotate Left (No Carry) f
Wd = Rotate Left (No Carry) Ws
f = Rotate Right through Carry f
WREG = Rotate Right through Carry f
Wd = Rotate Right through Carry Ws
f = Rotate Right (No Carry) f
WREG = Rotate Right (No Carry) f
Wd = Rotate Right (No Carry) Ws
Wnd = sign-extended Ws
f = 0xFFFF
None
None
f
C,N,Z
RLC
f,WREG
Ws,Wd
f
1
C,N,Z
RLC
1
C,N,Z
54
55
56
RLNC
RRC
RLNC
RLNC
RLNC
RRC
1
N,Z
f,WREG
Ws,Wd
f
1
N,Z
1
N,Z
1
C,N,Z
RRC
f,WREG
Ws,Wd
f
1
C,N,Z
RRC
1
C,N,Z
RRNC
RRNC
RRNC
RRNC
SE
1
N,Z
f,WREG
Ws,Wd
Ws,Wnd
f
1
N,Z
1
N,Z
57
58
SE
1
C,N,Z
SETM
SETM
SETM
SETM
SL
1
None
WREG
WREG = 0xFFFF
1
None
Ws
Ws = 0xFFFF
1
None
59
60
61
SL
f
f = Left Shift f
1
C,N,OV,Z
C,N,OV,Z
C,N,OV,Z
N,Z
SL
f,WREG
Ws,Wd
Wb,Wns,Wnd
Wb,#lit5,Wnd
f
WREG = Left Shift f
1
SL
Wd = Left Shift Ws
1
SL
Wnd = Left Shift Wb by Wns
Wnd = Left Shift Wb by lit5
f = f – WREG
1
SL
1
N,Z
SUB
SUBB
SUB
1
C,DC,N,OV,Z
C,DC,N,OV,Z
C,DC,N,OV,Z
C,DC,N,OV,Z
C,DC,N,OV,Z
SUB
f,WREG
#lit10,Wn
Wb,Ws,Wd
Wb,#lit5,Wd
WREG = f – WREG
1
SUB
Wn = Wn – lit10
1
SUB
Wd = Wb – Ws
1
SUB
Wd = Wb – lit5
1
SUBB
SUBB
SUBB
f
f = f – WREG – (C)
1
1
1
1
1
1
C,DC,N,OV,Z
C,DC,N,OV,Z
C,DC,N,OV,Z
f,WREG
#lit10,Wn
WREG = f – WREG – (C)
Wn = Wn – lit10 – (C)
SUBB
SUBB
SUBR
SUBR
SUBR
SUBR
SUBBR
Wb,Ws,Wd
Wb,#lit5,Wd
f
Wd = Wb – Ws – (C)
Wd = Wb – lit5 – (C)
f = WREG – f
1
1
1
1
1
1
1
1
1
1
1
1
1
1
C,DC,N,OV,Z
C,DC,N,OV,Z
C,DC,N,OV,Z
C,DC,N,OV,Z
C,DC,N,OV,Z
C,DC,N,OV,Z
C,DC,N,OV,Z
62
63
SUBR
f,WREG
Wb,Ws,Wd
Wb,#lit5,Wd
f
WREG = WREG – f
Wd = Ws – Wb
Wd = lit5 – Wb
SUBBR
f = WREG – f – (C)
SUBBR
SUBBR
SUBBR
SWAP.b
SWAP
f,WREG
Wb,Ws,Wd
Wb,#lit5,Wd
Wn
WREG = WREG – f – (C)
Wd = Ws – Wb – (C)
1
1
1
1
1
1
1
1
1
1
1
2
C,DC,N,OV,Z
C,DC,N,OV,Z
C,DC,N,OV,Z
None
Wd = lit5 – Wb – (C)
64
65
SWAP
Wn = nibble swap Wn
Wn = byte swap Wn
Wn
None
TBLRDH
TBLRDH
Ws,Wd
Read Prog<23:16> to Wd<7:0>
None
© 2007 Microchip Technology Inc.
Preliminary
DS70289A-page 187
PIC24HJ32GP202/204 and PIC24HJ16GP304
TABLE 19-2: INSTRUCTION SET OVERVIEW (CONTINUED)
Base
Instr
#
Assembly
Mnemonic
# of
# of
Status Flags
Affected
Assembly Syntax
Description
Words Cycles
66
TBLRDL
TBLWTH
TBLWTL
ULNK
TBLRDL
TBLWTH
TBLWTL
ULNK
XOR
Ws,Wd
Ws,Wd
Ws,Wd
Read Prog<15:0> to Wd
1
1
1
1
1
1
1
1
1
1
2
2
2
1
1
1
1
1
1
1
None
None
None
None
N,Z
67
68
69
70
Write Ws<7:0> to Prog<23:16>
Write Ws to Prog<15:0>
Unlink Frame Pointer
f = f .XOR. WREG
XOR
f
XOR
f,WREG
WREG = f .XOR. WREG
Wd = lit10 .XOR. Wd
Wd = Wb .XOR. Ws
N,Z
XOR
#lit10,Wn
Wb,Ws,Wd
Wb,#lit5,Wd
Ws,Wnd
N,Z
XOR
N,Z
XOR
Wd = Wb .XOR. lit5
N,Z
71
ZE
ZE
Wnd = Zero-extend Ws
C,Z,N
DS70289A-page 188
Preliminary
© 2007 Microchip Technology Inc.
PIC24HJ32GP202/204 and PIC24HJ16GP304
20.1 MPLAB Integrated Development
Environment Software
20.0 DEVELOPMENT SUPPORT
The PIC® microcontrollers are supported with a full
range of hardware and software development tools:
The MPLAB IDE software brings an ease of software
development previously unseen in the 8/16-bit micro-
controller market. The MPLAB IDE is a Windows®
operating system-based application that contains:
• Integrated Development Environment
- MPLAB® IDE Software
• Assemblers/Compilers/Linkers
- MPASMTM Assembler
• A single graphical interface to all debugging tools
- Simulator
- MPLAB C18 and MPLAB C30 C Compilers
- MPLINKTM Object Linker/
MPLIBTM Object Librarian
- Programmer (sold separately)
- Emulator (sold separately)
- In-Circuit Debugger (sold separately)
• A full-featured editor with color-coded context
• A multiple project manager
- MPLAB ASM30 Assembler/Linker/Library
• Simulators
- MPLAB SIM Software Simulator
• Emulators
• Customizable data windows with direct edit of
contents
- MPLAB ICE 2000 In-Circuit Emulator
- MPLAB REAL ICE™ In-Circuit Emulator
• In-Circuit Debugger
• High-level source code debugging
• Visual device initializer for easy register
initialization
- MPLAB ICD 2
• Mouse over variable inspection
• Device Programmers
• Drag and drop variables from source to watch
windows
- PICSTART® Plus Development Programmer
- MPLAB PM3 Device Programmer
- PICkit™ 2 Development Programmer
• Extensive on-line help
• Integration of select third party tools, such as
HI-TECH Software C Compilers and IAR
C Compilers
• Low-Cost Demonstration and Development
Boards and Evaluation Kits
The MPLAB IDE allows you to:
• Edit your source files (either assembly or C)
• One touch assemble (or compile) and download
to PIC MCU emulator and simulator tools
(automatically updates all project information)
• Debug using:
- Source files (assembly or C)
- Mixed assembly and C
- Machine code
MPLAB IDE supports multiple debugging tools in a
single development paradigm, from the cost-effective
simulators, through low-cost in-circuit debuggers, to
full-featured emulators. This eliminates the learning
curve when upgrading to tools with increased flexibility
and power.
© 2007 Microchip Technology Inc.
Preliminary
DS70289A-page 189
PIC24HJ32GP202/204 and PIC24HJ16GP304
20.2 MPASM Assembler
20.5 MPLAB ASM30 Assembler, Linker
and Librarian
The MPASM Assembler is a full-featured, universal
macro assembler for all PIC MCUs.
MPLAB ASM30 Assembler produces relocatable
machine code from symbolic assembly language for
dsPIC30F devices. MPLAB C30 C Compiler uses the
assembler to produce its object file. The assembler
generates relocatable object files that can then be
archived or linked with other relocatable object files and
archives to create an executable file. Notable features
of the assembler include:
The MPASM Assembler generates relocatable object
files for the MPLINK Object Linker, Intel® standard HEX
files, MAP files to detail memory usage and symbol
reference, absolute LST files that contain source lines
and generated machine code and COFF files for
debugging.
The MPASM Assembler features include:
• Integration into MPLAB IDE projects
• Support for the entire dsPIC30F instruction set
• Support for fixed-point and floating-point data
• Command line interface
• User-defined macros to streamline
assembly code
• Rich directive set
• Conditional assembly for multi-purpose
source files
• Flexible macro language
• MPLAB IDE compatibility
• Directives that allow complete control over the
assembly process
20.6 MPLAB SIM Software Simulator
20.3 MPLAB C18 and MPLAB C30
C Compilers
The MPLAB SIM Software Simulator allows code
development in a PC-hosted environment by simulat-
ing the PIC MCUs and dsPIC® DSCs on an instruction
level. On any given instruction, the data areas can be
examined or modified and stimuli can be applied from
a comprehensive stimulus controller. Registers can be
logged to files for further run-time analysis. The trace
buffer and logic analyzer display extend the power of
the simulator to record and track program execution,
actions on I/O, most peripherals and internal registers.
The MPLAB C18 and MPLAB C30 Code Development
Systems are complete ANSI
C
compilers for
Microchip’s PIC18 and PIC24 families of microcontrol-
lers and the dsPIC30 and dsPIC33 family of digital sig-
nal controllers. These compilers provide powerful
integration capabilities, superior code optimization and
ease of use not found with other compilers.
For easy source level debugging, the compilers provide
symbol information that is optimized to the MPLAB IDE
debugger.
The MPLAB SIM Software Simulator fully supports
symbolic debugging using the MPLAB C18 and
MPLAB C30 C Compilers, and the MPASM and
MPLAB ASM30 Assemblers. The software simulator
offers the flexibility to develop and debug code outside
of the hardware laboratory environment, making it an
excellent, economical software development tool.
20.4 MPLINK Object Linker/
MPLIB Object Librarian
The MPLINK Object Linker combines relocatable
objects created by the MPASM Assembler and the
MPLAB C18 C Compiler. It can link relocatable objects
from precompiled libraries, using directives from a
linker script.
The MPLIB Object Librarian manages the creation and
modification of library files of precompiled code. When
a routine from a library is called from a source file, only
the modules that contain that routine will be linked in
with the application. This allows large libraries to be
used efficiently in many different applications.
The object linker/library features include:
• Efficient linking of single libraries instead of many
smaller files
• Enhanced code maintainability by grouping
related modules together
• Flexible creation of libraries with easy module
listing, replacement, deletion and extraction
DS70289A-page 190
Preliminary
© 2007 Microchip Technology Inc.
PIC24HJ32GP202/204 and PIC24HJ16GP304
20.7 MPLAB ICE 2000
20.9 MPLAB ICD 2 In-Circuit Debugger
High-Performance
In-Circuit Emulator
Microchip’s In-Circuit Debugger, MPLAB ICD 2, is a
powerful, low-cost, run-time development tool,
connecting to the host PC via an RS-232 or high-speed
USB interface. This tool is based on the Flash PIC
MCUs and can be used to develop for these and other
PIC MCUs and dsPIC DSCs. The MPLAB ICD 2 utilizes
the in-circuit debugging capability built into the Flash
devices. This feature, along with Microchip’s In-Circuit
Serial ProgrammingTM (ICSPTM) protocol, offers cost-
effective, in-circuit Flash debugging from the graphical
user interface of the MPLAB Integrated Development
Environment. This enables a designer to develop and
debug source code by setting breakpoints, single step-
ping and watching variables, and CPU status and
peripheral registers. Running at full speed enables
testing hardware and applications in real time. MPLAB
ICD 2 also serves as a development programmer for
selected PIC devices.
The MPLAB ICE 2000 In-Circuit Emulator is intended
to provide the product development engineer with a
complete microcontroller design tool set for PIC
microcontrollers. Software control of the MPLAB ICE
2000 In-Circuit Emulator is advanced by the MPLAB
Integrated Development Environment, which allows
editing, building, downloading and source debugging
from a single environment.
The MPLAB ICE 2000 is a full-featured emulator
system with enhanced trace, trigger and data monitor-
ing features. Interchangeable processor modules allow
the system to be easily reconfigured for emulation of
different processors. The architecture of the MPLAB
ICE 2000 In-Circuit Emulator allows expansion to
support new PIC microcontrollers.
The MPLAB ICE 2000 In-Circuit Emulator system has
been designed as a real-time emulation system with
advanced features that are typically found on more
expensive development tools. The PC platform and
Microsoft® Windows® 32-bit operating system were
chosen to best make these features available in a
simple, unified application.
20.10 MPLAB PM3 Device Programmer
The MPLAB PM3 Device Programmer is a universal,
CE compliant device programmer with programmable
voltage verification at VDDMIN and VDDMAX for
maximum reliability. It features a large LCD display
(128 x 64) for menus and error messages and a modu-
lar, detachable socket assembly to support various
package types. The ICSP™ cable assembly is included
as a standard item. In Stand-Alone mode, the MPLAB
PM3 Device Programmer can read, verify and program
PIC devices without a PC connection. It can also set
code protection in this mode. The MPLAB PM3
connects to the host PC via an RS-232 or USB cable.
The MPLAB PM3 has high-speed communications and
optimized algorithms for quick programming of large
memory devices and incorporates an SD/MMC card for
file storage and secure data applications.
20.8 MPLAB REAL ICE In-Circuit
Emulator System
MPLAB REAL ICE In-Circuit Emulator System is
Microchip’s next generation high-speed emulator for
Microchip Flash DSC and MCU devices. It debugs and
programs PIC® Flash MCUs and dsPIC® Flash DSCs
with the easy-to-use, powerful graphical user interface of
the MPLAB Integrated Development Environment (IDE),
included with each kit.
The MPLAB REAL ICE probe is connected to the design
engineer’s PC using a high-speed USB 2.0 interface and
is connected to the target with either a connector
compatible with the popular MPLAB ICD 2 system
(RJ11) or with the new high-speed, noise tolerant, Low-
Voltage Differential Signal (LVDS) interconnection
(CAT5).
MPLAB REAL ICE is field upgradeable through future
firmware downloads in MPLAB IDE. In upcoming
releases of MPLAB IDE, new devices will be supported,
and new features will be added, such as software break-
points and assembly code trace. MPLAB REAL ICE
offers significant advantages over competitive emulators
including low-cost, full-speed emulation, real-time
variable watches, trace analysis, complex breakpoints, a
ruggedized probe interface and long (up to three meters)
interconnection cables.
© 2007 Microchip Technology Inc.
Preliminary
DS70289A-page 191
PIC24HJ32GP202/204 and PIC24HJ16GP304
20.11 PICSTART Plus Development
Programmer
20.13 Demonstration, Development and
Evaluation Boards
The PICSTART Plus Development Programmer is an
easy-to-use, low-cost, prototype programmer. It
connects to the PC via a COM (RS-232) port. MPLAB
Integrated Development Environment software makes
using the programmer simple and efficient. The
PICSTART Plus Development Programmer supports
most PIC devices in DIP packages up to 40 pins.
Larger pin count devices, such as the PIC16C92X and
PIC17C76X, may be supported with an adapter socket.
The PICSTART Plus Development Programmer is CE
compliant.
A wide variety of demonstration, development and
evaluation boards for various PIC MCUs and dsPIC
DSCs allows quick application development on fully func-
tional systems. Most boards include prototyping areas for
adding custom circuitry and provide application firmware
and source code for examination and modification.
The boards support a variety of features, including LEDs,
temperature sensors, switches, speakers, RS-232
interfaces, LCD displays, potentiometers and additional
EEPROM memory.
The demonstration and development boards can be
used in teaching environments, for prototyping custom
circuits and for learning about various microcontroller
applications.
20.12 PICkit 2 Development Programmer
The PICkit™ 2 Development Programmer is a low-cost
programmer and selected Flash device debugger with
an easy-to-use interface for programming many of
Microchip’s baseline, mid-range and PIC18F families
of Flash memory microcontrollers. The PICkit 2 Starter
Kit includes a prototyping development board, twelve
sequential lessons, software and HI-TECH’s PICC™
Lite C compiler, and is designed to help get up to speed
quickly using PIC® microcontrollers. The kit provides
everything needed to program, evaluate and develop
applications using Microchip’s powerful, mid-range
Flash memory family of microcontrollers.
In addition to the PICDEM™ and dsPICDEM™ demon-
stration/development board series of circuits, Microchip
has a line of evaluation kits and demonstration software
®
for analog filter design, KEELOQ security ICs, CAN,
IrDA®, PowerSmart battery management, SEEVAL®
evaluation system, Sigma-Delta ADC, flow rate
sensing, plus many more.
Check the Microchip web page (www.microchip.com)
for the complete list of demonstration, development
and evaluation kits.
DS70289A-page 192
Preliminary
© 2007 Microchip Technology Inc.
PIC24HJ32GP202/204 and PIC24HJ16GP304
21.0 ELECTRICAL CHARACTERISTICS
This section provides an overview of PIC24HJ32GP202/204 and PIC24HJ16GP304 electrical characteristics.
Additional information will be provided in future revisions of this document as it becomes available.
Absolute maximum ratings for the PIC24HJ32GP202/204 and PIC24HJ16GP304 family are listed below. Exposure to
these maximum rating conditions for extended periods can affect device reliability. Functional operation of the device
at these or any other conditions above the parameters indicated in the operation listings of this specification is not
implied.
(1)
Absolute Maximum Ratings
Ambient temperature under bias.............................................................................................................-40°C to +125°C
Storage temperature .............................................................................................................................. -65°C to +150°C
Voltage on VDD with respect to VSS ......................................................................................................... -0.3V to +4.0V
Voltage on any combined analog and digital pin and MCLR, with respect to VSS ......................... -0.3V to (VDD + 0.3V)
Voltage on any digital-only pin with respect to VSS .................................................................................. -0.3V to +5.6V
Voltage on VDDCORE with respect to VSS ................................................................................................ 2.25V to 2.75V
Maximum current out of VSS pin ...........................................................................................................................300 mA
Maximum current into VDD pin(2)...........................................................................................................................250 mA
Maximum output current sunk by any I/O pin(3) ........................................................................................................4 mA
Maximum output current sourced by any I/O pin(3)...................................................................................................4 mA
Maximum current sunk by all ports .......................................................................................................................200 mA
Maximum current sourced by all ports(2)...............................................................................................................200 mA
Note 1: Stresses above those listed under “Absolute Maximum Ratings” can cause permanent damage to the
device. This is a stress rating only, and functional operation of the device at those or any other conditions
above those indicated in the operation listings of this specification is not implied. Exposure to maximum
rating conditions for extended periods can affect device reliability.
2: Maximum allowable current is a function of device maximum power dissipation (see Table 21-2).
3: Exceptions are CLKOUT, which is able to sink/source 25 mA, and the VREF+, VREF-, SCLx, SDAx, PGCx
and PGDx pins, which are able to sink/source 12 mA.
© 2007 Microchip Technology Inc.
Preliminary
DS70289A-page 193
PIC24HJ32GP202/204 and PIC24HJ16GP304
21.1 DC Characteristics
TABLE 21-1: OPERATING MIPS VS. VOLTAGE
Max MIPS
VDD Range
(in Volts)
Temp Range
(in °C)
Characteristic
PIC24HJ32GP202/204 and
PIC24HJ16GP304
3.0-3.6V
3.0-3.6V
-40°C to +85°C
-40°C to +125°C
40
40
TABLE 21-2: THERMAL OPERATING CONDITIONS
Rating
Symbol
Min
Typ
Max
Unit
Industrial Temperature Devices
Operating Junction Temperature Range
Operating Ambient Temperature Range
Extended Temperature Devices
TJ
TA
-40
-40
—
—
+125
+85
°C
°C
Operating Junction Temperature Range
Operating Ambient Temperature Range
TJ
TA
-40
-40
—
—
+140
+125
°C
°C
Power Dissipation:
Internal chip power dissipation:
PINT = VDD x (IDD – Σ IOH)
PD
PINT + PI/O
W
W
I/O Pin Power Dissipation:
I/O = Σ ({VDD – VOH} x IOH) + Σ (VOL x IOL)
Maximum Allowed Power Dissipation
PDMAX
(TJ – TA)/θJA
TABLE 21-3: THERMAL PACKAGING CHARACTERISTICS
Characteristic
Symbol
Typ
Max
Unit
Notes
Package Thermal Resistance, 44-pin QFN
Package Thermal Resistance, 44-pin TFQP
Package Thermal Resistance, 28-pin SPDIP
Package Thermal Resistance, 28-pin SOIC
Package Thermal Resistance, 28-pin QFN-S
θJA
θJA
θJA
θJA
θJA
62.4
60
—
—
—
—
—
°C/W
°C/W
°C/W
°C/W
°C/W
1
1
1
1
1
108
80.2
32
Note 1: Junction to ambient thermal resistance, Theta-JA (θJA) numbers are achieved by package simulations.
DS70289A-page 194
Preliminary
© 2007 Microchip Technology Inc.
PIC24HJ32GP202/204 and PIC24HJ16GP304
TABLE 21-4: DC TEMPERATURE AND VOLTAGE SPECIFICATIONS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C ≤ TA ≤ +85°C for Industrial
DC CHARACTERISTICS
-40°C ≤ TA ≤ +125°C for Extended
Param
No.
Symbol
Characteristic
Min
Typ(1)
Max Units
Conditions
Operating Voltage
DC10 Supply Voltage
VDD
3.0
1.1
—
—
1.3
—
3.6
1.8
V
V
V
Industrial and Extended
DC12
DC16
VDR
RAM Data Retention Voltage(2)
VPOR
VDD Start Voltage
to ensure internal
VSS
Power-on Reset signal
DC17
DC18
SVDD
VDD Rise Rate
to ensure internal
Power-on Reset signal
VDD Core(3)
0.03
2.25
—
—
—
V/ms 0-3.0V in 0.1s
VCORE
2.75
V
Voltage is dependent on
Internal regulator voltage
load, temperature and
VDD
Note 1: Data in “Typ” column is at 3.3V, 25°C unless otherwise stated.
2: This is the limit to which VDD can be lowered without losing RAM data.
3: These parameters are characterized but not tested in manufacturing.
© 2007 Microchip Technology Inc.
Preliminary
DS70289A-page 195
PIC24HJ32GP202/204 and PIC24HJ16GP304
TABLE 21-5: DC CHARACTERISTICS: OPERATING CURRENT (IDD)
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C ≤ TA ≤ +85°C for Industrial
DC CHARACTERISTICS
-40°C ≤ TA ≤ +125°C for Extended
Parameter
Typical(1)
Max
Units
Conditions
No.
Operating Current (IDD)(2)
DC20d
DC20a
DC20b
DC20c
DC21d
DC21a
DC21b
DC21c
DC22d
DC22a
DC22b
DC22c
DC23d
DC23a
DC23b
DC23c
DC24d
DC24a
DC24b
DC24c
24
27
27
27
30
37
32
33
35
38
38
39
47
48
48
48
56
56
54
54
30
30
30
35
40
40
45
45
50
50
55
55
70
70
70
70
90
90
90
80
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
-40°C
+25°C
+85°C
+125°C
-40°C
3.3V
3.3V
3.3V
3.3V
10 MIPS
16 MIPS
20 MIPS
30 MIPS
+25°C
+85°C
+125°C
-40°C
+25°C
+85°C
+125°C
-40°C
+25°C
+85°C
+125°C
-40°C
+25°C
+85°C
+125°C
3.3V
3.3V
40 MIPS
35 MIPS
Note 1: Data in “Typical” column is at 3.3V, 25°C unless otherwise stated.
2: The supply current is mainly a function of the operating voltage and frequency. Other factors, such as I/O
pin loading and switching rate, oscillator type, internal code execution pattern and temperature, also have
an impact on the current consumption. The test conditions for all IDD measurements are as follows: OSC1
driven with external square wave from rail to rail. All I/O pins are configured as inputs and pulled to VSS.
MCLR = VDD, WDT and FSCM are disabled. CPU, SRAM, program memory and data memory are
operational. No peripheral modules are operating; however, every peripheral is being clocked (PMD bits
are all zeroed).
DS70289A-page 196
Preliminary
© 2007 Microchip Technology Inc.
PIC24HJ32GP202/204 and PIC24HJ16GP304
TABLE 21-6: DC CHARACTERISTICS: IDLE CURRENT (IIDLE)
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C ≤ TA ≤ +85°C for Industrial
DC CHARACTERISTICS
-40°C ≤ TA ≤ +125°C for Extended
Parameter
Typical(1)
Max
Units
Conditions
No.
Idle Current (IIDLE): Core OFF Clock ON Base Current(2)
DC40d
DC40a
DC40b
DC40c
DC41d
DC41a
DC41b
DC41c
DC42d
DC42a
DC42b
DC42c
DC43d
DC43a
DC43b
DC43c
DC44d
DC44a
DC44b
DC44c
3
3
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
-40°C
+25°C
+85°C
+125°C
-40°C
10 MIPS
16 MIPS
20 MIPS
30 MIPS
3.3V
3.3V
3
3
4
4
+25°C
+85°C
+125°C
-40°C
5
5
6
6
+25°C
+85°C
+125°C
-40°C
3.3V
3.3V
7
7
9
9
+25°C
+85°C
+125°C
-40°C
9
9
10
10
16
10
+25°C
+85°C
+125°C
3.3V
3.3V
40 MIPS
35 MIPS
Note 1: Data in “Typical” column is at 3.3V, 25°C unless otherwise stated.
2: Base IIDLE current is measured with core off, clock on and all modules turned off. Peripheral Module
Disable SFR registers are zeroed. All I/O pins are configured as inputs and pulled to VSS.
© 2007 Microchip Technology Inc.
Preliminary
DS70289A-page 197
PIC24HJ32GP202/204 and PIC24HJ16GP304
TABLE 21-7: DC CHARACTERISTICS: POWER-DOWN CURRENT (IPD)
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C ≤ TA ≤ +85°C for Industrial
DC CHARACTERISTICS
-40°C ≤ TA ≤ +125°C for Extended
Parameter
Typical(1)
Max
Units
Conditions
No.
Power-Down Current (IPD)(2)
DC60d
DC60a
DC60b
DC60c
DC61d
DC61a
DC61b
DC61c
55
63
85
146
8
500
500
500
1
μA
μA
μA
mA
μA
μA
μA
μA
-40°C
+25°C
+85°C
+125°C
-40°C
3.3V
3.3V
Base Power-Down Current(3,4)
12
10
12
13
15
+25°C
+85°C
+125°C
(3)
Watchdog Timer Current: ΔIWDT
20
25
Note 1: Data in the Typical column is at 3.3V, 25°C unless otherwise stated.
2: Base IPD is measured with all peripherals and clocks shut down. All I/Os are configured as inputs and
pulled to VSS. WDT, etc., are all switched off.
3: The Δ current is the additional current consumed when the module is enabled. This current should be
added to the base IPD current.
4: These currents are measured on the device containing the most memory in this family.
TABLE 21-8: DC CHARACTERISTICS: DOZE CURRENT (IDOZE)
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C ≤ TA ≤ +85°C for Industrial
-40°C ≤ TA ≤ +125°C for Extended
DC CHARACTERISTICS
Doze
Ratio
Parameter No.
Typical(1)
Max
Units
Conditions
DC73a
DC73f
DC73g
DC70a
DC70f
DC70g
DC71a
DC71f
DC71g
DC72a
DC72f
DC72g
25
23
23
42
26
25
41
25
24
42
26
25
32
27
26
47
27
27
48
28
28
49
29
28
1:2
1:64
1:128
1:2
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
-40°C
+25°C
+85°C
3.3V
40 MIPS
40 MIPS
40 MIPS
35 MIPS
1:64
1:128
1:2
3.3V
3.3V
1:64
1:128
1:2
1:64
1:128
mA +125°C 3.3V
mA
Note 1: Data in the Typical column is at 3.3V, 25°C unless otherwise stated.
DS70289A-page 198
Preliminary
© 2007 Microchip Technology Inc.
PIC24HJ32GP202/204 and PIC24HJ16GP304
TABLE 21-9: DC CHARACTERISTICS: I/O PIN INPUT SPECIFICATIONS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C ≤ TA ≤ +85°C for Industrial
DC CHARACTERISTICS
-40°C ≤ TA ≤ +125°C for Extended
Param
No.
Symbol
Characteristic
Input Low Voltage
Min
Typ(1)
Max
Units
Conditions
VIL
DI10
I/O pins
VSS
VSS
VSS
VSS
VSS
VSS
—
—
—
—
—
—
0.2 VDD
0.2 VDD
0.2 VDD
0.2 VDD
0.3 VDD
0.2 VDD
V
V
V
V
V
V
DI15
DI16
DI17
DI18
DI19
MCLR
OSC1 (XT mode)
OSC1 (HS mode)
SDAx, SCLx
SDAx, SCLx
Input High Voltage
SMBus disabled
SMBus enabled
VIH
DI20
I/O pins:
with analog functions
digital-only
0.8 VDD
0.8 VDD
—
—
VDD
5.5
V
V
DI25
DI26
DI27
DI28
DI29
MCLR
0.8 VDD
0.7 VDD
0.7 VDD
0.7 VDD
0.8 VDD
—
—
—
—
—
VDD
VDD
VDD
VDD
VDD
V
V
V
V
V
OSC1 (XT mode)
OSC1 (HS mode)
SDAx, SCLx
SMBus disabled
SMBus enabled
SDAx, SCLx
ICNPU
IIL
CNx Pull-up Current
DI30
50
250
400
μA VDD = 3.3V, VPIN = VSS
Input Leakage Current(2)(3)
DI50
DI51
I/O ports
—
—
—
—
±2
±1
μA VSS ≤ VPIN ≤ VDD,
Pin at high-impedance
Analog Input Pins
Analog Input Pins
Analog Input Pins
Analog Input Pins
μA VSS ≤ VPIN ≤ VDD, Pin at
high-impedance,
40°C ≤ TA ≤ +85°C
DI51a
DI51b
DI51c
—
—
—
—
—
—
±2
±3.5
±8
μA Analog pins shared with
external reference pins,
40°C ≤ TA ≤ +85°C
μA VSS ≤ VPIN ≤ VDD, Pin at
high-impedance,
-40°C ≤ TA ≤ +125°C
μA Analog pins shared with
external reference pins,
-40°C ≤ TA ≤ +125°C
DI55
DI56
MCLR
OSC1
—
—
—
—
±2
±2
μA
VSS ≤ VPIN ≤ VDD
μA VSS ≤ VPIN ≤ VDD,
XT and HS modes
Note 1: Data in “Typ” column is at 3.3V, 25°C unless otherwise stated.
2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified
levels represent normal operating conditions. Higher leakage current may be measured at different input
voltages.
3: Negative current is defined as current sourced by the pin.
© 2007 Microchip Technology Inc.
Preliminary
DS70289A-page 199
PIC24HJ32GP202/204 and PIC24HJ16GP304
TABLE 21-10: DC CHARACTERISTICS: I/O PIN OUTPUT SPECIFICATIONS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C ≤ TA ≤ +85°C for Industrial
DC CHARACTERISTICS
-40°C ≤ TA ≤ +125°C for Extended
Param
No.
Symbol
Characteristic
Min
Typ
Max Units
Conditions
VOL
Output Low Voltage
I/O ports
DO10
DO16
—
—
—
—
0.4
0.4
V
V
IOL = 2mA, VDD = 3.3V
IOL = 2mA, VDD = 3.3V
OSC2/CLKO
VOH
Output High Voltage
I/O ports
DO20
DO26
2.40
2.41
—
—
—
—
V
V
IOH = -2.3 mA, VDD = 3.3V
IOH = -1.3 mA, VDD = 3.3V
OSC2/CLKO
TABLE 21-11: ELECTRICAL CHARACTERISTICS: BOR
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C ≤ TA ≤ +85°C for Industrial
-40°C ≤ TA ≤ +125°C for Extended
DC CHARACTERISTICS
Param
Symbol
No.
Characteristic
Min(1) Typ
2.40
Max
Units
Conditions
BO10
VBOR
BOR Event on VDD transition
high-to-low
—
2.55
V
BOR event is tied to VDD core voltage
decrease
Note 1: Parameters are for design guidance only and are not tested in manufacturing.
DS70289A-page 200
Preliminary
© 2007 Microchip Technology Inc.
PIC24HJ32GP202/204 and PIC24HJ16GP304
TABLE 21-12: DC CHARACTERISTICS: PROGRAM MEMORY
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C ≤ TA ≤ +85°C for Industrial
DC CHARACTERISTICS
-40°C ≤ TA ≤ +125°C for Extended
Param
No.
Symbol
Characteristic
Min Typ(1)
Max
Units
Conditions
Program Flash Memory
Cell Endurance
D130
D131
EP
10,000
VMIN
—
—
—
E/W -40°C to +125°C
VPR
VDD for Read
3.6
V
VMIN = Minimum operating
voltage
D132B VPEW
VDD for Self-Timed Write
Characteristic Retention
VMIN
20
—
—
10
3.6
—
V
VMIN = Minimum operating
voltage
D134
D135
TRETD
IDDP
Year Provided no other specifications
are violated, -40°C to +125°C
Supply Current during
Programming
—
—
mA
D136
D137
D138
TRW
TPE
Row Write Time
—
—
20
1.6
20
—
—
—
40
ms
ms
μs
Page Erase Time
Word Write Cycle Time
TWW
Note 1: Data in “Typ” column is at 3.3V, 25°C unless otherwise stated.
TABLE 21-13: INTERNAL VOLTAGE REGULATOR SPECIFICATIONS
Operating Conditions: -40°C < TA < +85°C (unless otherwise stated)
Param
No.
Symbol
Characteristics
Min
Typ
Max
Units
Comments
CEFC
External Filter Capacitor
Value
1
10
—
μF
Capacitor must be low
series resistance
(< 5 ohms)
© 2007 Microchip Technology Inc.
Preliminary
DS70289A-page 201
PIC24HJ32GP202/204 and PIC24HJ16GP304
21.2 AC Characteristics and Timing
Parameters
The information contained in this section defines
PIC24HJ32GP202/204 and PIC24HJ16GP304 AC
characteristics and timing parameters.
TABLE 21-14: TEMPERATURE AND VOLTAGE SPECIFICATIONS – AC
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C ≤ TA ≤ +85°C for Industrial
AC CHARACTERISTICS
-40°C ≤ TA ≤ +125°C for Extended
Operating voltage VDD range as described in Section 21.0 “Electrical
Characteristics”.
FIGURE 21-1:
LOAD CONDITIONS FOR DEVICE TIMING SPECIFICATIONS
Load Condition 1 – for all pins except OSC2
VDD/2
Load Condition 2 – for OSC2
CL
RL
Pin
VSS
CL
Pin
RL = 464Ω
CL = 50 pF for all pins except OSC2
15 pF for OSC2 output
VSS
TABLE 21-15: CAPACITIVE LOADING REQUIREMENTS ON OUTPUT PINS
Param
Symbol
Characteristic
Min
Typ
Max Units
Conditions
No.
DO50 COSC2
OSC2/SOSC2 pin
—
—
15
pF In XT and HS modes when
external clock is used to drive
OSC1
DO56 CIO
DO58 CB
All I/O pins and OSC2
SCLx, SDAx
—
—
—
—
50
pF EC mode
pF In I2C™ mode
400
DS70289A-page 202
Preliminary
© 2007 Microchip Technology Inc.
PIC24HJ32GP202/204 and PIC24HJ16GP304
FIGURE 21-2:
EXTERNAL CLOCK TIMING
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
OSC1
CLKO
OS20
OS30 OS30
OS25
OS31 OS31
OS41
OS40
TABLE 21-16: EXTERNAL CLOCK TIMING REQUIREMENTS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C ≤ TA ≤ +85°C for Industrial
-40°C ≤ TA ≤ +125°C for Extended
AC CHARACTERISTICS
Param
Symb
No.
Characteristic
Min
Typ(1)
Max
Units
Conditions
OS10
FIN
External CLKI Frequency
(External clocks allowed only
in EC and ECPLL modes)
DC
—
40
MHz EC
Oscillator Crystal Frequency
3.5
10
—
—
—
10
40
33
MHz XT
MHz HS
kHz SOSC
OS20
OS25
OS30
TOSC
TCY
TOSC = 1/FOSC
Instruction Cycle Time(2)
12.5
25
—
—
—
DC
DC
ns
ns
TosL, External Clock in (OSC1)
TosH High or Low Time
0.375 x TOSC
0.625 x TOSC
ns
EC
EC
OS31
TosR, External Clock in (OSC1)
TosF Rise or Fall Time
—
—
20
ns
OS40
OS41
TckR CLKO Rise Time(3)
—
—
5.2
5.2
—
—
ns
ns
TckF
CLKO Fall Time(3)
Note 1: Data in “Typ” column is at 3.3V, 25°C unless otherwise stated.
2: Instruction cycle period (TCY) equals two times the input oscillator time-base period. All specified values
are based on characterization data for that particular oscillator type under standard operating conditions
with the device executing code. Exceeding these specified limits can result in an unstable oscillator
operation and/or higher than expected current consumption. All devices are tested to operate at “min.”
values with an external clock applied to the OSC1/CLKI pin. When an external clock input is used, the
“max.” cycle time limit is “DC” (no clock) for all devices.
3: Measurements are taken in EC mode. The CLKO signal is measured on the OSC2 pin.
© 2007 Microchip Technology Inc.
Preliminary
DS70289A-page 203
PIC24HJ32GP202/204 and PIC24HJ16GP304
TABLE 21-17: PLL CLOCK TIMING SPECIFICATIONS (VDD = 3.0V TO 3.6V)
Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated)
AC CHARACTERISTICS
Operating temperature -40°C ≤ TA ≤ +85°C for Industrial
-40°C ≤ TA ≤ +125°C for Extended
Param
Symbol
No.
Characteristic
Min
Typ(1)
Max
Units
Conditions
OS50
FPLLI
PLL Voltage Controlled
Oscillator (VCO) Input
Frequency Range
0.8
—
8
MHz ECPLL, XTPLL modes
OS51
FSYS
On-Chip VCO System
Frequency
100
—
200
MHz
ms
OS52
OS53
TLOCK
DCLK
PLL Start-up Time (Lock Time)
CLKO Stability (Jitter)
0.9
-3
1.5
0.5
3.1
3
%
Measured over 100 ms
period
Note 1: Data in “Typ” column is at 3.3V, 25°C unless otherwise stated.
TABLE 21-18: AC CHARACTERISTICS: INTERNAL RC ACCURACY
Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated)
AC CHARACTERISTICS
Operating temperature
-40°C ≤ TA ≤ +85°C for Industrial
-40°C ≤ TA ≤ +125°C for Extended
Param
No.
Characteristic
Min
Typ
Max
Units
Conditions
Internal FRC Accuracy @ FRC Frequency = 7.37 MHz(1,2)
F20
FRC
FRC
-2
-5
—
—
+2
+5
%
%
-40°C ≤ TA ≤ +85°C
-40°C ≤ TA ≤ +125°C
VDD = 3.0-3.6V
VDD = 3.0-3.6V
Note 1: Frequency calibrated at 25°C and 3.3V. TUN bits can be used to compensate for temperature drift.
2: FRC is set to initial frequency of 7.37 MHz (±2%) at 25°C.
TABLE 21-19: INTERNAL RC ACCURACY
Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated)
AC CHARACTERISTICS
Operating temperature -40°C ≤ TA ≤ +85°C for Industrial
-40°C ≤ TA ≤ +125°C for Extended
Param
No.
Characteristic
Min
Typ
Max
Units
Conditions
LPRC @ 32.768 kHz(1)
F21
LPRC
LPRC
-20
-70
±6
—
+20
+20
%
%
-40°C ≤ TA ≤ +85°C
-40°C ≤ TA ≤ +125°C
VDD = 3.0-3.6V
VDD = 3.0-3.6V
Note 1: Change of LPRC frequency as VDD changes.
DS70289A-page 204
Preliminary
© 2007 Microchip Technology Inc.
PIC24HJ32GP202/204 and PIC24HJ16GP304
FIGURE 21-3:
I/O TIMING CHARACTERISTICS
I/O Pin
(Input)
DI35
DI40
I/O Pin
(Output)
New Value
Old Value
DO31
DO32
Note: Refer to Figure 21-1 for load conditions.
TABLE 21-20: I/O TIMING REQUIREMENTS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C ≤ TA ≤ +85°C for Industrial
-40°C ≤ TA ≤ +125°C for Extended
AC CHARACTERISTICS
Param
Symbol
No.
Characteristic
Min
Typ(1)
Max
Units
Conditions
DO31
DO32
DI35
TIOR
TIOF
TINP
TRBP
Port Output Rise Time
—
—
20
2
10
10
—
—
25
25
—
—
ns
ns
—
—
—
—
Port Output Fall Time
INTx Pin High or Low Time (output)
CNx High or Low Time (input)
ns
DI40
TCY
Note 1: Data in “Typ” column is at 3.3V, 25°C unless otherwise stated.
© 2007 Microchip Technology Inc.
Preliminary
DS70289A-page 205
PIC24HJ32GP202/204 and PIC24HJ16GP304
FIGURE 21-4:
RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP
TIMER TIMING CHARACTERISTICS
VDD
SY12
MCLR
SY10
Internal
POR
SY11
PWRT
Time-out
SY30
OSC
Time-out
Internal
Reset
Watchdog
Timer
Reset
SY20
SY13
SY13
I/O Pins
SY35
FSCM
Delay
Note: Refer to Figure 21-1 for load conditions.
DS70289A-page 206
Preliminary
© 2007 Microchip Technology Inc.
PIC24HJ32GP202/204 and PIC24HJ16GP304
TABLE 21-21: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER
TIMING REQUIREMENTS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C ≤ TA ≤ +85°C for Industrial
AC CHARACTERISTICS
-40°C ≤ TA ≤ +125°C for Extended
Param
No.
Symbol
Characteristic(1)
Min
Typ(2)
Max Units
Conditions
SY10
SY11
TMCL
MCLR Pulse Width (low)
Power-up Timer Period
2
—
—
—
μs
-40°C to +85°C
TPWRT
—
2
4
ms
-40°C to +85°C
User programmable
8
16
32
64
128
SY12
SY13
TPOR
TIOZ
Power-on Reset Delay
3
10
30
μs
μs
-40°C to +85°C
I/O High-Impedance from MCLR
Low or Watchdog Timer Reset
0.68
0.72
1.2
SY20
TWDT1
Watchdog Timer Time-out Period
(No Prescaler)
1.7
2.1
2.6
ms
VDD = 3V, -40°C to +85°C
SY30
SY35
TOST
Oscillator Start-up Time
—
—
1024 TOSC
500
—
—
TOSC = OSC1 period
-40°C to +85°C
TFSCM
Fail-Safe Clock Monitor Delay
900
μs
Note 1: These parameters are characterized but not tested in manufacturing.
2: Data in “Typ” column is at 3.3V, 25°C unless otherwise stated.
© 2007 Microchip Technology Inc.
Preliminary
DS70289A-page 207
PIC24HJ32GP202/204 and PIC24HJ16GP304
FIGURE 21-5:
TIMER1, 2 AND 3 EXTERNAL CLOCK TIMING CHARACTERISTICS
TxCK
Tx11
Tx10
Tx15
Tx20
OS60
TMRx
Note: Refer to Figure 21-1 for load conditions.
TABLE 21-22: TIMER1 EXTERNAL CLOCK TIMING REQUIREMENTS(1)
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C ≤ TA ≤ +85°C for Industrial
-40°C ≤ TA ≤ +125°C for Extended
AC CHARACTERISTICS
Param
Symbol
No.
Characteristic
Min
Typ
Max Units
Conditions
TA10
TA11
TA15
TTXH
TTXL
TTXP
TxCK High Time
TxCK Low Time
Synchronous,
no prescaler
0.5 TCY + 20
—
—
—
ns
ns
Must also meet
parameter TA15
Synchronous,
with prescaler
10
—
Asynchronous
10
—
—
—
—
ns
ns
Synchronous,
no prescaler
0.5 TCY + 20
Must also meet
parameter TA15
Synchronous,
with prescaler
10
—
—
ns
Asynchronous
10
—
—
—
—
ns
ns
TxCK Input Period Synchronous,
no prescaler
TCY + 40
Synchronous,
with prescaler
Greater of:
20 ns or
—
—
—
N = prescale
value
(TCY + 40)/N
(1, 8, 64, 256)
Asynchronous
20
—
—
—
ns
OS60
TA20
Ft1
SOSC1/T1CK Oscillator Input
frequency Range (oscillator enabled
by setting bit TCS (T1CON<1>))
DC
50
kHz
TCKEXTMRL Delay from External TxCK Clock
Edge to Timer Increment
0.5 TCY
1.5
TCY
—
Note 1: Timer1 is a Type A.
DS70289A-page 208
Preliminary
© 2007 Microchip Technology Inc.
PIC24HJ32GP202/204 and PIC24HJ16GP304
TABLE 21-23: TIMER2 EXTERNAL CLOCK TIMING REQUIREMENTS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C ≤ TA ≤ +85°C for Industrial
AC CHARACTERISTICS
-40°C ≤ TA ≤ +125°C for Extended
Param
No.
Symbol
TtxH
Characteristic
Min
Typ
Max
Units
Conditions
TB10
TxCK High Time Synchronous, 0.5 TCY + 20
no prescaler
—
—
ns
Must also meet
parameter TB15
Synchronous,
with prescaler
10
—
—
—
—
—
—
—
—
ns
ns
ns
ns
TB11
TB15
TtxL
TtxP
TxCK Low Time
Synchronous, 0.5 TCY + 20
no prescaler
Must also meet
parameter TB15
Synchronous,
with prescaler
10
TxCK Input
Period
Synchronous,
no prescaler
TCY + 40
N = prescale
value
(1, 8, 64, 256)
Synchronous,
with prescaler
Greater of:
20 ns or
(TCY + 40)/N
TB20
TCKEXT-
MRL
Delay from External TxCK Clock
Edge to Timer Increment
0.5 TCY
—
1.5 TCY
—
TABLE 21-24: TIMER3 EXTERNAL CLOCK TIMING REQUIREMENTS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C ≤ TA ≤ +85°C for Industrial
-40°C ≤ TA ≤ +125°C for Extended
AC CHARACTERISTICS
Param
Symbol
No.
Characteristic
Min
Typ
Max Units
Conditions
TC10
TC11
TC15
TtxH
TtxL
TtxP
TxCK High Time
TxCK Low Time
Synchronous
Synchronous
0.5 TCY + 20
—
—
—
—
ns
ns
ns
Must also meet
parameter TC15
0.5 TCY + 20
TCY + 40
—
—
Must also meet
parameter TC15
TxCK Input Period Synchronous,
no prescaler
N = prescale
value
(1, 8, 64, 256)
Synchronous,
with prescaler
Greater of:
20 ns or
(TCY + 40)/N
TC20
TCKEXT-
MRL
Delay from External TxCK Clock
Edge to Timer Increment
0.5 TCY
—
1.5
TCY
—
© 2007 Microchip Technology Inc.
Preliminary
DS70289A-page 209
PIC24HJ32GP202/204 and PIC24HJ16GP304
FIGURE 21-6:
INPUT CAPTURE (CAPx) TIMING CHARACTERISTICS
ICx
IC10
IC11
IC15
Note: Refer to Figure 21-1 for load conditions.
TABLE 21-25: INPUT CAPTURE TIMING REQUIREMENTS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C ≤ TA ≤ +85°C for Industrial
-40°C ≤ TA ≤ +125°C for Extended
AC CHARACTERISTICS
Param
Symbol
No.
Characteristic(1)
Min
Max
Units
Conditions
IC10
IC11
IC15
TccL
TccH
TccP
ICx Input Low Time No Prescaler
With Prescaler
0.5 TCY + 20
10
—
—
—
—
—
ns
ns
ns
ns
ns
ICx Input High Time No Prescaler
With Prescaler
0.5 TCY + 20
10
ICx Input Period
(TCY + 40)/N
N = prescale
value (1, 4, 16)
Note 1: These parameters are characterized but not tested in manufacturing.
FIGURE 21-7:
OUTPUT COMPARE MODULE (OCx) TIMING CHARACTERISTICS
OCx
(Output Compare
or PWM Mode)
OC10
OC11
Note: Refer to Figure 21-1 for load conditions.
TABLE 21-26: OUTPUT COMPARE MODULE TIMING REQUIREMENTS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
AC CHARACTERISTICS
Operating temperature -40°C ≤ TA ≤ +85°C for Industrial
-40°C ≤ TA ≤ +125°C for Extended
Param
Symbol
No.
Characteristic(1)
Min
Typ
Max
Units
Conditions
OC10 TccF
OC11 TccR
OCx Output Fall Time
OCx Output Rise Time
—
—
—
—
—
—
ns
ns
See parameter D032
See parameter D031
Note 1: These parameters are characterized but not tested in manufacturing.
DS70289A-page 210
Preliminary
© 2007 Microchip Technology Inc.
PIC24HJ32GP202/204 and PIC24HJ16GP304
FIGURE 21-8:
OC/PWM MODULE TIMING CHARACTERISTICS
OC20
OCFA/OCFB
OCx
OC15
TABLE 21-27: SIMPLE OC/PWM MODE TIMING REQUIREMENTS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C ≤ TA ≤ +85°C for Industrial
-40°C ≤ TA ≤ +125°C for Extended
AC CHARACTERISTICS
Param
Symbol
No.
Characteristic(1)
Min
Typ
Max
Units
Conditions
OC15
TFD
Fault Input to PWM I/O
Change
—
—
50
ns
—
OC20
TFLT
Fault Input Pulse Width
50
—
—
ns
—
Note 1: These parameters are characterized but not tested in manufacturing.
© 2007 Microchip Technology Inc.
Preliminary
DS70289A-page 211
PIC24HJ32GP202/204 and PIC24HJ16GP304
FIGURE 21-9:
SPIx MODULE MASTER MODE (CKE = 0) TIMING CHARACTERISTICS
SCKx
(CKP = 0)
SP11
SP10
SP21
SP20
SP20
SCKx
(CKP = 1)
SP35
SP31
SP21
LSb
Bit 14 - - - - - -1
MSb
SDOx
SDIx
SP30
MSb In
SP40
LSb In
Bit 14 - - - -1
SP41
Note: Refer to Figure 21-1 for load conditions.
TABLE 21-28: SPIx MASTER MODE (CKE = 0) TIMING REQUIREMENTS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C ≤ TA ≤ +85°C for Industrial
-40°C ≤ TA ≤ +125°C for Extended
AC CHARACTERISTICS
Param
Symbol
No.
Characteristic(1)
Min
Typ(2)
Max
Units
Conditions
See Note 3
SP10
SP11
SP20
TscL
TscH
TscF
SCKx Output Low Time
SCKx Output High Time
SCKx Output Fall Time
TCY/2
TCY/2
—
—
—
—
—
—
—
ns
ns
ns
See Note 3
See parameter D032
and Note 4
SP21
SP30
SP31
SP35
SP40
SP41
TscR
TdoF
TdoR
SCKx Output Rise Time
—
—
—
—
23
30
—
—
—
6
—
—
—
20
—
—
ns
ns
ns
ns
ns
ns
See parameter D031
and Note 4
SDOx Data Output Fall Time
SDOx Data Output Rise Time
See parameter D032
and Note 4
See parameter D031
and Note 4
TscH2doV, SDOx Data Output Valid after
TscL2doV SCKx Edge
—
—
—
TdiV2scH, Setup Time of SDIx Data Input
—
—
TdiV2scL
TscH2diL, Hold Time of SDIx Data Input
TscL2diL to SCKx Edge
to SCKx Edge
Note 1: These parameters are characterized but not tested in manufacturing.
2: Data in “Typ” column is at 3.3V, 25°C unless otherwise stated.
3: The minimum clock period for SCKx is 100 ns. Therefore, the clock generated in Master mode must not
violate this specification.
4: Assumes 50 pF load on all SPIx pins.
DS70289A-page 212
Preliminary
© 2007 Microchip Technology Inc.
PIC24HJ32GP202/204 and PIC24HJ16GP304
FIGURE 21-10:
SPIx MODULE MASTER MODE (CKE = 1) TIMING CHARACTERISTICS
SP36
SCKX
(CKP = 0)
SP11
SP10
SP21
SP20
SP20
SP21
SCKX
(CKP = 1)
SP35
LSb
MSb
SP40
Bit 14 - - - - - -1
SDOX
SP30,SP31
Bit 14 - - - -1
SDIX
MSb In
SP41
Note: Refer to Figure 21-1 for load conditions.
LSb In
TABLE 21-29: SPIx MODULE MASTER MODE (CKE = 1) TIMING REQUIREMENTS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C ≤ TA ≤ +85°C for Industrial
AC CHARACTERISTICS
-40°C ≤ TA ≤ +125°C for Extended
Param
No.
Symbol
TscL
Characteristic(1)
Min
Typ(2)
Max
Units
Conditions
See Note 3
SP10
SP11
SP20
SCKx Output Low Time
SCKx Output High Time
SCKx Output Fall Time
TCY/2
TCY/2
—
—
—
—
—
—
—
ns
ns
ns
TscH
TscF
See Note 3
See parameter D032
and Note 4
SP21
SP30
SP31
SP35
SP36
SP40
SP41
TscR
TdoF
TdoR
SCKx Output Rise Time
—
—
—
—
30
23
30
—
—
—
6
—
—
—
20
—
—
—
ns
ns
ns
ns
ns
ns
ns
See parameter D031
and Note 4
SDOx Data Output Fall Time
SDOx Data Output Rise Time
See parameter D032
and Note 4
See parameter D031
and Note 4
TscH2doV, SDOx Data Output Valid after
TscL2doV SCKx Edge
—
—
—
—
TdoV2sc, SDOx Data Output Setup to
TdoV2scL First SCKx Edge
—
—
—
TdiV2scH, Setup Time of SDIx Data
TdiV2scL Input to SCKx Edge
TscH2diL, Hold Time of SDIx Data Input
TscL2diL
to SCKx Edge
Note 1: These parameters are characterized but not tested in manufacturing.
2: Data in “Typ” column is at 3.3V, 25°C unless otherwise stated.
3: The minimum clock period for SCKx is 100 ns. The clock generated in Master mode must not violate this
specification.
4: Assumes 50 pF load on all SPIx pins.
© 2007 Microchip Technology Inc.
Preliminary
DS70289A-page 213
PIC24HJ32GP202/204 and PIC24HJ16GP304
FIGURE 21-11:
SPIx MODULE SLAVE MODE (CKE = 0) TIMING CHARACTERISTICS
SSX
SP52
SP50
SCKX
(CKP =
0
)
)
SP71
SP70
SP72
SP73
SP72
SCKX
(CKP =
1
SP73
LSb
SP35
MSb
SDOX
SDIX
Bit 14 - - - - - -1
SP51
SP30,SP31
Bit 14 - - - -1
MSb In
SP41
LSb In
SP40
Note: Refer to Figure 21-1 for load conditions.
TABLE 21-30: SPIx MODULE SLAVE MODE (CKE = 0) TIMING REQUIREMENTS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C ≤ TA ≤ +85°C for Industrial
AC CHARACTERISTICS
-40°C ≤ TA ≤ +125°C for Extended
Param
No.
Symbol
TscL
Characteristic(1)
Min
Typ(2) Max Units
Conditions
SP70
SP71
SP72
SP73
SP30
SCKx Input Low Time
SCKx Input High Time
SCKx Input Fall Time
SCKx Input Rise Time
SDOx Data Output Fall Time
30
30
—
—
—
—
—
10
10
—
—
—
25
25
—
ns
ns
ns
ns
ns
—
—
TscH
TscF
TscR
TdoF
See Note 3
See Note 3
See parameter D032
and Note 3
SP31
SP35
SP40
SP41
SP50
SP51
SP52
TdoR
SDOx Data Output Rise Time
—
—
—
—
—
—
—
—
—
30
—
—
—
50
—
ns
ns
ns
ns
ns
ns
ns
See parameter D031
and Note 3
TscH2doV, SDOx Data Output Valid after
TscL2doV SCKx Edge
—
—
TdiV2scH, Setup Time of SDIx Data Input
TdiV2scL to SCKx Edge
20
20
—
TscH2diL, Hold Time of SDIx Data Input to
TscL2diL
—
—
SCKx Edge
TssL2scH, SSx ↓ to SCKx ↑ or SCKx Input
TssL2scL
120
See Note 3
TssH2doZ SSx ↑ to SDOx Output
10
High-Impedance
TscH2ssH SSx after SCKx Edge
TscL2ssH
1.5 TCY +40
—
Note 1: These parameters are characterized but not tested in manufacturing.
2: Data in “Typ” column is at 3.3V, 25°C unless otherwise stated.
3: Assumes 50 pF load on all SPIx pins.
DS70289A-page 214
Preliminary
© 2007 Microchip Technology Inc.
PIC24HJ32GP202/204 and PIC24HJ16GP304
FIGURE 21-12:
SPIx MODULE SLAVE MODE (CKE = 1) TIMING CHARACTERISTICS
SP60
SSx
SP52
SP50
SCKx
(CKP = 0)
SP71
SP70
SP72
SP73
SP73
SCKx
(CKP = 1)
SP35
SP72
LSb
SP52
Bit 14 - - - - - -1
MSb
SDOx
SDIx
SP30,SP31
Bit 14 - - - -1
SP51
MSb In
SP41
LSb In
SP40
Note: Refer to Figure 21-1 for load conditions.
© 2007 Microchip Technology Inc.
Preliminary
DS70289A-page 215
PIC24HJ32GP202/204 and PIC24HJ16GP304
TABLE 21-31: SPIx MODULE SLAVE MODE (CKE = 1) TIMING REQUIREMENTS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C ≤ TA ≤ +85°C for Industrial
AC CHARACTERISTICS
-40°C ≤ TA ≤ +125°C for Extended
Param
No.
Symbol
TscL
Characteristic(1)
Min
Typ(2)
Max
Units
Conditions
SP70
SP71
SP72
SP73
SP30
SCKx Input Low Time
SCKx Input High Time
SCKx Input Fall Time
SCKx Input Rise Time
SDOx Data Output Fall Time
30
30
—
—
—
—
—
10
10
—
—
—
25
25
—
ns
ns
ns
ns
ns
—
—
TscH
TscF
TscR
TdoF
See Note 3
See Note 3
See parameter D032
and Note 3
SP31
SP35
SP40
SP41
SP50
SP51
SP52
SP60
TdoR
SDOx Data Output Rise Time
—
—
—
—
—
—
—
—
—
—
30
—
—
—
50
—
50
ns
ns
ns
ns
ns
ns
ns
ns
See parameter D031
and Note 3
TscH2doV, SDOx Data Output Valid after
TscL2doV SCKx Edge
—
—
TdiV2scH, Setup Time of SDIx Data Input
TdiV2scL to SCKx Edge
20
—
TscH2diL, Hold Time of SDIx Data Input
TscL2diL
20
—
—
to SCKx Edge
TssL2scH, SSx ↓ to SCKx ↓ or SCKx ↑
TssL2scL Input
120
See Note 4
TssH2doZ SSx ↑ to SDOX Output
10
1.5 TCY + 40
—
High-Impedance
TscH2ssH SSx ↑ after SCKx Edge
TscL2ssH
—
—
TssL2doV SDOx Data Output Valid after
SSx Edge
Note 1: These parameters are characterized but not tested in manufacturing.
2: Data in “Typ” column is at 3.3V, 25°C unless otherwise stated.
3: The minimum clock period for SCKx is 100 ns. The clock generated in Master mode must not violate this
specification.
4: Assumes 50 pF load on all SPIx pins.
DS70289A-page 216
Preliminary
© 2007 Microchip Technology Inc.
PIC24HJ32GP202/204 and PIC24HJ16GP304
FIGURE 21-13:
I2Cx BUS START/STOP BITS TIMING CHARACTERISTICS (MASTER MODE)
SCLx
SDAx
IM31
IM34
IM30
IM33
Stop
Condition
Start
Condition
Note: Refer to Figure 21-1 for load conditions.
FIGURE 21-14:
I2Cx BUS DATA TIMING CHARACTERISTICS (MASTER MODE)
IM20
IM21
IM11
IM10
SCLx
IM11
IM26
IM10
IM33
IM25
SDAx
In
IM45
IM40
IM40
SDAx
Out
Note: Refer to Figure 21-1 for load conditions.
© 2007 Microchip Technology Inc.
Preliminary
DS70289A-page 217
PIC24HJ32GP202/204 and PIC24HJ16GP304
TABLE 21-32: I2Cx BUS DATA TIMING REQUIREMENTS (MASTER MODE)
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C ≤ TA ≤ +85°C for Industrial
AC CHARACTERISTICS
-40°C ≤ TA ≤ +125°C for Extended
Param
No.
Symbol
Characteristic
Min(1)
Max
Units
Conditions
IM10
TLO:SCL Clock Low Time 100 kHz mode TCY/2 (BRG + 1)
400 kHz mode TCY/2 (BRG + 1)
—
—
μs
μs
μs
μs
μs
μs
ns
ns
ns
ns
ns
ns
ns
ns
ns
μs
μs
μs
μs
μs
μs
μs
μs
μs
μs
μs
μs
ns
ns
ns
ns
ns
ns
μs
μs
μs
pF
—
—
—
—
—
—
1 MHz mode(2) TCY/2 (BRG + 1)
—
IM11
IM20
IM21
IM25
IM26
IM30
IM31
IM33
IM34
IM40
IM45
IM50
THI:SCL Clock High Time 100 kHz mode TCY/2 (BRG + 1)
400 kHz mode TCY/2 (BRG + 1)
—
—
1 MHz mode(2) TCY/2 (BRG + 1)
—
TF:SCL
TR:SCL
SDAx and SCLx 100 kHz mode
—
300
300
100
1000
300
300
—
CB is specified to be
from 10 to 400 pF
Fall Time
400 kHz mode
20 + 0.1 CB
1 MHz mode(2)
—
SDAx and SCLx 100 kHz mode
—
CB is specified to be
from 10 to 400 pF
Rise Time
400 kHz mode
20 + 0.1 CB
1 MHz mode(2)
—
250
100
40
0
TSU:DAT Data Input
Setup Time
100 kHz mode
400 kHz mode
1 MHz mode(2)
100 kHz mode
400 kHz mode
1 MHz mode(2)
—
—
—
—
THD:DAT Data Input
Hold Time
—
0
0.9
—
0.2
TSU:STA Start Condition 100 kHz mode TCY/2 (BRG + 1)
—
Only relevant for
Repeated Start
condition
Setup Time
400 kHz mode TCY/2 (BRG + 1)
—
1 MHz mode(2) TCY/2 (BRG + 1)
—
THD:STA Start Condition 100 kHz mode TCY/2 (BRG + 1)
—
After this period the
first clock pulse is
generated
Hold Time
400 kHz mode TCY/2 (BRG + 1)
—
1 MHz mode(2) TCY/2 (BRG + 1)
—
TSU:STO Stop Condition 100 kHz mode TCY/2 (BRG + 1)
—
—
Setup Time
400 kHz mode TCY/2 (BRG + 1)
—
1 MHz mode(2) TCY/2 (BRG + 1)
—
THD:STO Stop Condition
Hold Time
100 kHz mode TCY/2 (BRG + 1)
400 kHz mode TCY/2 (BRG + 1)
1 MHz mode(2) TCY/2 (BRG + 1)
—
—
—
—
TAA:SCL Output Valid
From Clock
100 kHz mode
400 kHz mode
1 MHz mode(2)
—
—
3500
1000
400
—
—
—
—
—
TBF:SDA Bus Free Time 100 kHz mode
400 kHz mode
4.7
1.3
0.5
—
Time the bus must be
free before a new
transmission can start
—
1 MHz mode(2)
—
CB
Bus Capacitive Loading
400
Note 1: BRG is the value of the I2C Baud Rate Generator. Refer to Section 19. “Inter-Integrated Circuit (I2C™)”
in the “PIC24H Family Reference Manual”.
2: Maximum pin capacitance = 10 pF for all I2Cx pins (for 1 MHz mode only).
DS70289A-page 218
Preliminary
© 2007 Microchip Technology Inc.
PIC24HJ32GP202/204 and PIC24HJ16GP304
FIGURE 21-15:
I2Cx BUS START/STOP BITS TIMING CHARACTERISTICS (SLAVE MODE)
SCLx
SDAx
IS34
IS31
IS30
IS33
Stop
Condition
Start
Condition
FIGURE 21-16:
I2Cx BUS DATA TIMING CHARACTERISTICS (SLAVE MODE)
IS20
IS21
IS11
IS10
SCLx
IS30
IS26
IS31
IS33
IS25
SDAx
In
IS45
IS40
IS40
SDAx
Out
© 2007 Microchip Technology Inc.
Preliminary
DS70289A-page 219
PIC24HJ32GP202/204 and PIC24HJ16GP304
TABLE 21-33: I2Cx BUS DATA TIMING REQUIREMENTS (SLAVE MODE)
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C ≤ TA ≤ +85°C for Industrial
AC CHARACTERISTICS
-40°C ≤ TA ≤ +125°C for Extended
Param Symbol
Characteristic
Min
Max
Units
Conditions
IS10
TLO:SCL Clock Low Time 100 kHz mode
4.7
—
μs
Device must operate at a
minimum of 1.5 MHz
400 kHz mode
1.3
—
μs
Device must operate at a
minimum of 10 MHz
1 MHz mode(1)
0.5
4.0
—
—
μs
μs
—
IS11
THI:SCL Clock High Time 100 kHz mode
Device must operate at a
minimum of 1.5 MHz
400 kHz mode
0.6
—
μs
Device must operate at a
minimum of 10 MHz
1 MHz mode(1)
0.5
—
300
300
100
1000
300
300
—
μs
ns
ns
ns
ns
ns
ns
ns
ns
ns
μs
μs
μs
μs
μs
μs
μs
μs
μs
μs
μs
μs
ns
ns
ns
ns
ns
ns
μs
μs
μs
pF
—
IS20
IS21
IS25
IS26
IS30
IS31
IS33
IS34
IS40
IS45
IS50
TF:SCL SDAx and SCLx 100 kHz mode
—
CB is specified to be from
10 to 400 pF
Fall Time
400 kHz mode
1 MHz mode(1)
20 + 0.1 CB
—
—
TR:SCL SDAx and SCLx 100 kHz mode
CB is specified to be from
10 to 400 pF
Rise Time
400 kHz mode
1 MHz mode(1)
20 + 0.1 CB
—
TSU:DAT Data Input
Setup Time
100 kHz mode
400 kHz mode
1 MHz mode(1)
100 kHz mode
400 kHz mode
1 MHz mode(1)
100 kHz mode
400 kHz mode
1 MHz mode(1)
100 kHz mode
400 kHz mode
1 MHz mode(1)
100 kHz mode
400 kHz mode
1 MHz mode(1)
100 kHz mode
400 kHz mode
1 MHz mode(1)
100 kHz mode
400 kHz mode
1 MHz mode(1)
100 kHz mode
400 kHz mode
1 MHz mode(1)
250
100
100
0
—
—
—
—
THD:DAT Data Input
Hold Time
0
0
0.9
0.3
—
0
TSU:STA Start Condition
Setup Time
4.7
0.6
0.25
4.0
0.6
0.25
4.7
0.6
0.6
4000
600
250
0
Only relevant for Repeated
Start condition
—
—
THD:STA Start Condition
Hold Time
—
After this period, the first
clock pulse is generated
—
—
TSU:STO Stop Condition
Setup Time
—
—
—
—
—
—
THD:ST Stop Condition
—
O
Hold Time
—
TAA:SCL Output Valid
From Clock
3500
1000
350
—
0
0
TBF:SDA Bus Free Time
4.7
1.3
0.5
—
Time the bus must be free
before a new transmission
can start
—
—
CB
Bus Capacitive Loading
400
—
Note 1: Maximum pin capacitance = 10 pF for all I2Cx pins (for 1 MHz mode only).
DS70289A-page 220
Preliminary
© 2007 Microchip Technology Inc.
PIC24HJ32GP202/204 and PIC24HJ16GP304
TABLE 21-34: ADC MODULE SPECIFICATIONS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C ≤ TA ≤ +85°C for Industrial
AC CHARACTERISTICS
-40°C ≤ TA ≤ +125°C for Extended
Param
No.
Symbol
Characteristic
Min.
Typ
Max.
Units
Conditions
Device Supply
AD01
AVDD
Module VDD Supply
Greater of
VDD – 0.3
or 3.0
—
—
Lesser of
VDD + 0.3
or 3.6
V
V
—
—
AD02
AVSS
Module VSS Supply
VSS – 0.3
VSS + 0.3
Reference Inputs
AD05
VREFH
Reference Voltage High
AVSS + 2.7
3.0
—
—
AVDD
3.6
V
V
See Note 1
AD05a
VREFH = AVDD
VREFL = AVSS = 0
AD06
VREFL
Reference Voltage Low
AVSS
0
—
—
AVDD – 2.7
0
V
V
See Note 1
AD06a
VREFH = AVDD
VREFL = AVSS = 0
AD07
AD08
VREF
IREF
Absolute Reference Voltage
Current Drain
2.7
—
—
3.6
V
VREF = VREFH - VREFL
400
—
550
10
μA ADC operating
μA ADC off
Analog Input
AD12
AD13
AD17
VINH
VINL
RIN
Input Voltage Range VINH
Input Voltage Range VINL
VINL
—
VREFH
V
This voltage reflects
Sample and Hold Channels
0, 1, 2, and 3 (CH0-CH3),
positive input
VREFL
—
AVSS + 1V
V
This voltage reflects
Sample and Hold Channels
0, 1, 2, and 3 (CH0-CH3),
negative input
Recommended Impedance
of Analog Voltage Source
—
—
—
—
200
200
Ω
Ω
10-bit ADC
12-bit ADC
Note 1: These parameters are not characterized or tested in manufacturing.
© 2007 Microchip Technology Inc.
Preliminary
DS70289A-page 221
PIC24HJ32GP202/204 and PIC24HJ16GP304
TABLE 21-35: ADC MODULE SPECIFICATIONS (12-BIT MODE)
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C ≤ TA ≤ +85°C for Industrial
AC CHARACTERISTICS
-40°C ≤ TA ≤ +125°C for Extended
Param
No.
Symbol
Characteristic
Min.
Typ
Max. Units
Conditions
ADC Accuracy (12-bit Mode) – Measurements with external VREF+/VREF-
AD20a Nr
AD21a INL
Resolution
12 data bits
—
bits
Integral Nonlinearity
-2
>-1
1.25
1.25
—
+2
<1
3
LSb VINL = AVSS = VREFL = 0V,
AVDD = VREFH = 3.6V
AD22a DNL
Differential Nonlinearity
Gain Error
—
1.5
1.52
—
LSb VINL = AVSS = VREFL = 0V,
AVDD = VREFH = 3.6V
AD23a
AD24a
AD25a
GERR
EOFF
—
LSb VINL = AVSS = VREFL = 0V,
AVDD = VREFH = 3.6V
Offset Error
2
LSb VINL = AVSS = VREFL = 0V,
AVDD = VREFH = 3.6V
Monotonicity
—
—
Guaranteed
ADC Accuracy (12-bit Mode) – Measurements with internal VREF+/VREF-
AD20a Nr
AD21a INL
AD22a DNL
Resolution
12 data bits
bits
Integral Nonlinearity
Differential Nonlinearity
Gain Error
-2
>-1
2
—
—
3
+2
<1
7
LSb VINL = AVSS = 0V, AVDD = 3.6V
LSb VINL = AVSS = 0V, AVDD = 3.6V
LSb VINL = AVSS = 0V, AVDD = 3.6V
LSb VINL = AVSS = 0V, AVDD = 3.6V
AD23a
AD24a
AD25a
GERR
EOFF
—
Offset Error
2
3
5
Monotonicity
—
—
—
—
Guaranteed
Dynamic Performance (12-bit Mode)
AD30a THD
Total Harmonic Distortion
-77
59
-69
63
-61
64
dB
dB
—
—
AD31a SINAD
Signal to Noise and
Distortion
AD32a SFDR
Spurious Free Dynamic
Range
63
72
74
dB
—
AD33a
FNYQ
Input Signal Bandwidth
Effective Number of Bits
—
—
250
—
kHz
bits
—
—
AD34a ENOB
10.95
11.1
DS70289A-page 222
Preliminary
© 2007 Microchip Technology Inc.
PIC24HJ32GP202/204 and PIC24HJ16GP304
TABLE 21-36: ADC MODULE SPECIFICATIONS (10-BIT MODE)
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C ≤ TA ≤ +85°C for Industrial
AC CHARACTERISTICS
-40°C ≤ TA ≤ +125°C for Extended
Param
No.
Symbol
Characteristic
Min.
Typ
Max. Units
Conditions
ADC Accuracy (10-bit Mode) – Measurements with external VREF+/VREF-
AD20b Nr
AD21b INL
Resolution
10 data bits
—
bits
Integral Nonlinearity
-1.5
>-1
1
+1.5
<1
6
LSb VINL = AVSS = VREFL = 0V,
AVDD = VREFH = 3.6V
AD22b DNL
Differential Nonlinearity
Gain Error
—
3
LSb VINL = AVSS = VREFL = 0V,
AVDD = VREFH = 3.6V
AD23b
AD24b
AD25b
GERR
EOFF
—
LSb VINL = AVSS = VREFL = 0V,
AVDD = VREFH = 3.6V
Offset Error
1
2
5
LSb VINL = AVSS = VREFL = 0V,
AVDD = VREFH = 3.6V
Monotonicity
—
—
—
—
Guaranteed
ADC Accuracy (10-bit Mode) – Measurements with internal VREF+/VREF-
AD20b Nr
AD21b INL
AD22b DNL
Resolution
10 data bits
bits
Integral Nonlinearity
Differential Nonlinearity
Gain Error
-1
>-1
1
—
—
5
+1
<1
6
LSb VINL = AVSS = 0V, AVDD = 3.6V
LSb VINL = AVSS = 0V, AVDD = 3.6V
LSb VINL = AVSS = 0V, AVDD = 3.6V
LSb VINL = AVSS = 0V, AVDD = 3.6V
AD23b
AD24b
AD25b
GERR
EOFF
—
Offset Error
1
2
3
Monotonicity
—
—
—
—
Guaranteed
Dynamic Performance (10-bit Mode)
AD30b THD
Total Harmonic Distortion
—
—
-64
57
-67
58
dB
dB
—
—
AD31b SINAD
Signal to Noise and
Distortion
AD32b SFDR
Spurious Free Dynamic
Range
—
60
62
dB
—
AD33b
FNYQ
Input Signal Bandwidth
Effective Number of Bits
—
—
550
9.8
kHz
bits
—
—
AD34b ENOB
9.1
9.7
© 2007 Microchip Technology Inc.
Preliminary
DS70289A-page 223
PIC24HJ32GP202/204 and PIC24HJ16GP304
FIGURE 21-17:
ADC CONVERSION (12-BIT MODE) TIMING CHARACTERISTICS
(ASAM = 0, SSRC<2:0> = 000)
AD50
ADCLK
Instruction
Execution
Set SAMP
AD61
Clear SAMP
SAMP
AD60
TSAMP
AD55
DONE
AD1IF
1
2
3
4
5
6
7
8
9
– Software sets AD1CON. SAMP to start sampling.
– Convert bit 11.
1
2
5
6
7
8
9
– Sampling starts after discharge period. TSAMP is described in
Section 28. “10/12-bit ADC without DMA” in the “PIC24H Family
Reference Manual”.
– Convert bit 10.
– Convert bit 1.
– Convert bit 0.
– Software clears AD1CON. SAMP to start conversion.
3
4
– One TAD for end of conversion.
– Sampling ends, conversion sequence starts.
TABLE 21-37: ADC CONVERSION (12-BIT MODE) TIMING REQUIREMENTS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C ≤ TA ≤ +85°C for Industrial
-40°C ≤ TA ≤ +125°C for Extended
AC CHARACTERISTICS
Param
Symbol
No.
Characteristic
Min.
Typ
Max.
Units
Conditions
Clock Parameters
AD50
AD51
TAD
tRC
ADC Clock Period
117.6
—
—
—
—
ns
ns
ADC Internal RC Oscillator
Period
250
Conversion Rate
AD55
AD56
AD57
tCONV
FCNV
Conversion Time
Throughput Rate
Sample Time
—
—
14 TAD
ns
Ksps
—
—
—
500
—
TSAMP
3 TAD
Timing Parameters
AD60
AD61
AD62
AD63
tPCS
tPSS
tCSS
tDPU
Conversion Start from Sample
Trigger(2)
—
0.5 TAD
—
1.0 TAD
—
1.5 TAD
—
—
—
—
μs
Auto Convert Trigger
not selected
Sample Start from Setting
Sample (SAMP) bit(2)
—
—
—
—
Conversion Completion to
0.5 TAD
—
Sample Start (ASAM = 1)(2)
Time to Stabilize Analog Stage
from ADC Off to ADC On(2)
1
5
Note 1: Because the sample caps will eventually lose charge, clock rates below 10 kHz can affect linearity
performance, especially at elevated temperatures.
2: These parameters are characterized but not tested in manufacturing.
DS70289A-page 224
Preliminary
© 2007 Microchip Technology Inc.
PIC24HJ32GP202/204 and PIC24HJ16GP304
FIGURE 21-18:
ADC CONVERSION (10-BIT MODE) TIMING CHARACTERISTICS
(CHPS<1:0> = 01, SIMSAM = 0, ASAM = 0, SSRC<2:0> = 000)
AD50
Set SAMP
AD61
ADCLK
Instruction
Execution
Clear SAMP
AD60
SAMP
TSAMP
AD55
AD55
DONE
AD1IF
Buffer(0)
Buffer(1)
1
2
3
4
5
6
7
8
5
6
7
8
– Convert bit 9.
– Convert bit 8.
– Convert bit 0.
– Software sets AD1CON. SAMP to start sampling.
5
6
7
8
1
2
– Sampling starts after discharge period. TSAMP is described in
Section 28. “10/12-bit ADC without DMA” in the
“PIC24H Family Reference Manual”.
– One TAD for end of conversion.
– Software clears AD1CON. SAMP to start conversion.
3
4
– Sampling ends, conversion sequence starts.
FIGURE 21-19:
ADC CONVERSION (10-BIT MODE) TIMING CHARACTERISTICS (CHPS<1:0> = 01,
SIMSAM = 0, ASAM = 1, SSRC<2:0> = 111, SAMC<4:0> = 00001)
AD50
ADCLK
Instruction
Execution
Set ADON
SAMP
AD1IF
TSAMP
TSAMP
AD55
AD55
AD55
DONE
1
2
3
4
5
6
7
3
4
5
6
8
– Software sets AD1CON. ADON to start AD operation.
– Convert bit 0.
5
1
2
– Sampling starts after discharge period. TSAMP is described in
Section 28. “10/12-bit ADC without DMA” in the
“PIC24H Family Reference Manual”.
– One TAD for end of conversion.
– Begin conversion of next channel.
6
7
8
– Sample for time specified by SAMC<4:0>.
– Convert bit 9.
– Convert bit 8.
3
4
© 2007 Microchip Technology Inc.
Preliminary
DS70289A-page 225
PIC24HJ32GP202/204 and PIC24HJ16GP304
TABLE 21-38: ADC CONVERSION (10-BIT MODE) TIMING REQUIREMENTS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C ≤ TA ≤ +85°C for Industrial
AC CHARACTERISTICS
-40°C ≤ TA ≤ +125°C for Extended
Param
No.
Symbol
Characteristic
Min.
Typ(1)
Max.
Units
Conditions
Clock Parameters
AD50 TAD
AD51 tRC
ADC Clock Period
ADC Internal RC Oscillator Period
76
—
—
—
—
ns
ns
250
Conversion Rate
AD55 tCONV
AD56 FCNV
Conversion Time
Throughput Rate
—
—
12 TAD
—
1.1
—
—
Msps
—
—
—
AD57 TSAMP Sample Time
2 TAD
Timing Parameters
AD60 tPCS
AD61 tPSS
AD62 tCSS
AD63 tDPU
Conversion Start from Sample
—
0.5 TAD
—
1.0 TAD
—
1.5 TAD
—
—
—
—
μs
Auto-Convert Trigger
not selected
Trigger(1)
Sample Start from Setting
Sample (SAMP) bit(1)
—
0.5 TAD
—
—
—
—
Conversion Completion to
Sample Start (ASAM = 1)(1)
Time to Stabilize Analog Stage
from ADC Off to ADC On(1)
1
5
Note 1: These parameters are characterized but not tested in manufacturing.
2: Because the sample caps will eventually lose charge, clock rates below 10 kHz can affect linearity
performance, especially at elevated temperatures.
DS70289A-page 226
Preliminary
© 2007 Microchip Technology Inc.
PIC24HJ32GP202/204 and PIC24HJ16GP304
22.0 PACKAGING INFORMATION
22.1 Package Marking Information
28-Lead SPDIP
Example
e
3
PIC24HJ32GP202-I/SP
0610017
XXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXX
YYWWNNN
28-Lead SOIC (.300”)
Example
e
3
XXXXXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXXXXX
PIC24HJ32GP202/SO
0610017
YYWWNNN
28-Lead QFN-S
Example
XXXXXXXX
XXXXXXXX
YYWWNNN
24HJ32GP
3
e
202E/MM
0730235
44-Lead QFN
Example
XXXXXXXXXX
XXXXXXXXXX
XXXXXXXXXX
YYWWNNN
PIC24HJ32
GP204-E/ML
e
3
0730235
44-Lead TQFP
Example
PIC24HJ
32GP204
-E/PT
0730235
XXXXXXXXXX
XXXXXXXXXX
XXXXXXXXXX
YYWWNNN
e
3
Legend: XX...X Customer-specific information
Y
Year code (last digit of calendar year)
YY
WW
NNN
Year code (last 2 digits of calendar year)
Week code (week of January 1 is week ‘01’)
Alphanumeric traceability code
Pb-free JEDEC designator for Matte Tin (Sn)
e
3
*
This package is Pb-free. The Pb-free JEDEC designator (
can be found on the outer packaging for this package.
)
e3
Note: If the full Microchip part number cannot be marked on one line, it is carried over to the next
line, thus limiting the number of available characters for customer-specific information.
© 2007 Microchip Technology Inc.
Preliminary
DS70289A-page 227
PIC24HJ32GP202/204 and PIC24HJ16GP304
22.2 Package Details
28-Lead Skinny Plastic Dual In-Line (SP) – 300 mil Body [SPDIP]
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
N
NOTE 1
E1
1
2 3
D
E
A2
A
L
c
b1
A1
b
e
eB
Units
INCHES
NOM
28
Dimension Limits
MIN
MAX
Number of Pins
Pitch
N
e
.100 BSC
–
Top to Seating Plane
A
–
.200
.150
–
Molded Package Thickness
Base to Seating Plane
Shoulder to Shoulder Width
Molded Package Width
Overall Length
A2
A1
E
.120
.015
.290
.240
1.345
.110
.008
.040
.014
–
.135
–
.310
.285
1.365
.130
.010
.050
.018
–
.335
.295
1.400
.150
.015
.070
.022
.430
E1
D
Tip to Seating Plane
Lead Thickness
L
c
Upper Lead Width
b1
b
Lower Lead Width
Overall Row Spacing §
eB
Notes:
1. Pin 1 visual index feature may vary, but must be located within the hatched area.
2. § Significant Characteristic.
3. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" per side.
4. Dimensioning and tolerancing per ASME Y14.5M.
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
Microchip Technology Drawing C04-070B
DS70289A-page 228
Preliminary
© 2007 Microchip Technology Inc.
PIC24HJ32GP202/204 and PIC24HJ16GP304
28-Lead Plastic Small Outline (SO) – Wide, 7.50 mm Body [SOIC]
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
D
N
E
E1
NOTE 1
1
2
3
e
b
h
α
h
c
φ
A2
A
L
A1
L1
β
Units
MILLMETERS
Dimension Limits
MIN
NOM
MAX
Number of Pins
Pitch
N
e
28
1.27 BSC
Overall Height
A
–
–
2.65
–
Molded Package Thickness
Standoff §
A2
A1
E
2.05
0.10
–
–
0.30
Overall Width
10.30 BSC
Molded Package Width
Overall Length
Chamfer (optional)
Foot Length
E1
D
h
7.50 BSC
17.90 BSC
0.25
0.40
–
0.75
1.27
L
–
Footprint
L1
φ
1.40 REF
Foot Angle Top
Lead Thickness
Lead Width
0°
0.18
0.31
5°
–
–
–
–
–
8°
c
0.33
0.51
15°
b
Mold Draft Angle Top
Mold Draft Angle Bottom
α
β
5°
15°
Notes:
1. Pin 1 visual index feature may vary, but must be located within the hatched area.
2. § Significant Characteristic.
3. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.15 mm per side.
4. Dimensioning and tolerancing per ASME Y14.5M.
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
REF: Reference Dimension, usually without tolerance, for information purposes only.
Microchip Technology Drawing C04-052B
© 2007 Microchip Technology Inc.
Preliminary
DS70289A-page 229
PIC24HJ32GP202/204 and PIC24HJ16GP304
28-Lead Plastic Quad Flat, No Lead Package (MM) – 6x6x0.9 mm Body [QFN-S]
with 0.40 mm Contact Length
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
D2
D
EXPOSED
PAD
e
E2
E
b
2
1
2
1
K
N
N
L
NOTE 1
BOTTOM VIEW
TOP VIEW
A
A3
A1
Units
MILLIMETERS
NOM
Dimension Limits
MIN
MAX
Number of Pins
N
e
28
Pitch
0.65 BSC
0.90
Overall Height
Standoff
A
0.80
0.00
1.00
0.05
A1
A3
E
0.02
Contact Thickness
Overall Width
0.20 REF
6.00 BSC
3.70
Exposed Pad Width
Overall Length
Exposed Pad Length
Contact Width
Contact Length
Contact-to-Exposed Pad
E2
D
3.65
4.70
6.00 BSC
3.70
D2
b
3.65
0.23
0.30
0.20
4.70
0.43
0.50
–
0.38
L
0.40
K
–
Notes:
1. Pin 1 visual index feature may vary, but must be located within the hatched area.
2. Package is saw singulated.
3. Dimensioning and tolerancing per ASME Y14.5M.
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
REF: Reference Dimension, usually without tolerance, for information purposes only.
Microchip Technology Drawing C04-124B
DS70289A-page 230
Preliminary
© 2007 Microchip Technology Inc.
PIC24HJ32GP202/204 and PIC24HJ16GP304
44-Lead Plastic Quad Flat, No Lead Package (ML) – 8x8 mm Body [QFN]
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
D2
D
EXPOSED
PAD
e
b
K
E
E2
2
1
2
1
N
N
NOTE 1
L
TOP VIEW
BOTTOM VIEW
A
A3
A1
Units
MILLIMETERS
Dimension Limits
MIN
NOM
44
MAX
Number of Pins
N
e
Pitch
0.65 BSC
0.90
Overall Height
Standoff
A
0.80
0.00
1.00
0.05
A1
A3
E
0.02
Contact Thickness
Overall Width
0.20 REF
8.00 BSC
6.45
Exposed Pad Width
Overall Length
Exposed Pad Length
Contact Width
Contact Length
Contact-to-Exposed Pad
E2
D
6.30
6.80
8.00 BSC
6.45
D2
b
6.30
0.25
0.30
0.20
6.80
0.38
0.50
–
0.30
L
0.40
K
–
Notes:
1. Pin 1 visual index feature may vary, but must be located within the hatched area.
2. Package is saw singulated.
3. Dimensioning and tolerancing per ASME Y14.5M.
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
REF: Reference Dimension, usually without tolerance, for information purposes only.
Microchip Technology Drawing C04-103B
© 2007 Microchip Technology Inc.
Preliminary
DS70289A-page 231
PIC24HJ32GP202/204 and PIC24HJ16GP304
44-Lead Plastic Thin Quad Flatpack (PT) – 10x10x1 mm Body, 2.00 mm Footprint [TQFP]
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
D
D1
E
e
E1
N
b
NOTE 1
1 2 3
NOTE 2
α
A
c
φ
A2
β
A1
L
L1
Units
MILLIMETERS
Dimension Limits
MIN
NOM
44
MAX
Number of Leads
Lead Pitch
N
e
0.80 BSC
–
Overall Height
A
–
1.20
1.05
0.15
0.75
Molded Package Thickness
Standoff
A2
A1
L
0.95
0.05
0.45
1.00
–
Foot Length
0.60
Footprint
L1
φ
1.00 REF
3.5°
Foot Angle
0°
7°
Overall Width
E
12.00 BSC
12.00 BSC
10.00 BSC
10.00 BSC
–
Overall Length
D
Molded Package Width
Molded Package Length
Lead Thickness
Lead Width
E1
D1
c
0.09
0.30
11°
0.20
0.45
13°
b
0.37
Mold Draft Angle Top
Mold Draft Angle Bottom
α
β
12°
11°
12°
13°
Notes:
1. Pin 1 visual index feature may vary, but must be located within the hatched area.
2. Chamfers at corners are optional; size may vary.
3. Dimensions D1 and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.25 mm per side.
4. Dimensioning and tolerancing per ASME Y14.5M.
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
REF: Reference Dimension, usually without tolerance, for information purposes only.
Microchip Technology Drawing C04-076B
DS70289A-page 232
Preliminary
© 2007 Microchip Technology Inc.
PIC24HJ32GP202/204 and PIC24HJ16GP304
APPENDIX A: REVISION HISTORY
Revision A (August 2007)
Initial release of this document
© 2007 Microchip Technology Inc.
Preliminary
DS70289A-page 233
PIC24HJ32GP202/204 and PIC24HJ16GP304
NOTES:
DS70289A-page 234
Preliminary
© 2007 Microchip Technology Inc.
PIC24HJ32GP202/204 and PIC24HJ16GP304
INDEX
A
D
A/D Converter ................................................................... 159
Data Address Space........................................................... 21
Alignment.................................................................... 21
Memory Map for PIC24H Devices with 8 KBs RAM... 22
Near Data Space........................................................ 21
Software Stack ........................................................... 34
Width .......................................................................... 21
DC Characteristics............................................................ 194
I/O Pin Input Specifications ...................................... 199
I/O Pin Output Specifications.................................... 200
Idle Current (IDOZE) .................................................. 198
Idle Current (IIDLE).................................................... 197
Operating Current (IDD) ............................................ 196
Power-Down Current (IPD)........................................ 198
Program Memory...................................................... 201
Temperature and Voltage Specifications.................. 195
Development Support....................................................... 189
Initialization ............................................................... 159
Key Features............................................................. 159
AC Characteristics ............................................................ 202
Internal RC Accuracy................................................ 204
Load Conditions........................................................ 202
ADC Module
ADC11 Register Map...................................... 28, 30, 31
Alternate Vector Table (AIVT)............................................. 53
Arithmetic Logic Unit (ALU)................................................. 18
Assembler
MPASM Assembler................................................... 190
Automatic Clock Stretch.................................................... 143
Receive Mode........................................................... 143
Transmit Mode.......................................................... 143
B
E
Block Diagrams
16-bit Timer1 Module................................................ 117
A/D Module ....................................................... 160, 161
Connections for On-Chip Voltage Regulator............. 176
Device Clock......................................................... 81, 83
Input Capture ............................................................ 125
Output Compare ....................................................... 130
PIC24H ....................................................................... 10
PIC24H CPU Core...................................................... 14
PLL.............................................................................. 83
Reset System.............................................................. 47
Shared Port Structure ................................................. 93
SPI ............................................................................ 134
Timer2 (16-bit) .......................................................... 121
Timer2/3 (32-bit) ....................................................... 120
UART ........................................................................ 151
Watchdog Timer (WDT)............................................ 177
Electrical Characteristics .................................................. 193
AC............................................................................. 202
Equations
A/D Conversion Clock Period................................... 162
Calculating the PWM Period..................................... 128
Calculation for Maximum PWM Resolution .............. 128
Device Operating Frequency...................................... 82
Relationship Between Device and
SPI Clock Speed .............................................. 136
Serial Clock Rate...................................................... 141
UART Baud Rate with BRGH = 0............................. 152
UART Baud Rate with BRGH = 1............................. 152
Errata.................................................................................... 7
F
Flash Program Memory...................................................... 41
Control Registers........................................................ 42
Operations.................................................................. 42
Programming Algorithm.............................................. 45
RTSP Operation ......................................................... 42
Table Instructions ....................................................... 41
Flexible Configuration....................................................... 173
FSCM
C
C Compilers
MPLAB C18 .............................................................. 190
MPLAB C30 .............................................................. 190
Clock Switching................................................................... 89
Enabling...................................................................... 89
Sequence.................................................................... 89
Code Examples
Delay for Crystal and PLL Clock Sources .................. 51
Device Resets ............................................................ 51
Erasing a Program Memory Page............................... 45
Initiating a Programming Sequence............................ 46
Loading Write Buffers ................................................. 46
Port Write/Read .......................................................... 94
PWRSAV Instruction Syntax....................................... 91
Code Protection ........................................................ 173, 178
Configuration Bits.............................................................. 173
Description (Table).................................................... 174
Configuration Register Map .............................................. 173
Configuring Analog Port Pins.............................................. 94
CPU
Control Register.......................................................... 16
CPU Clocking System......................................................... 82
Options........................................................................ 82
Selection ..................................................................... 82
Customer Change Notification Service ............................. 238
Customer Notification Service........................................... 238
Customer Support............................................................. 238
I
I/O Ports ............................................................................. 93
Parallel I/O (PIO) ........................................................ 93
Write/Read Timing...................................................... 94
2
I C
Addresses................................................................. 143
Baud Rate Generator ............................................... 141
General Call Address Support.................................. 143
Interrupts .................................................................. 141
IPMI Support............................................................. 143
Master Mode Operation
Clock Arbitration ............................................... 144
Multi-Master Communication, Bus Collision
and Bus Arbitration................................... 144
Operating Modes...................................................... 141
Registers .................................................................. 141
Slave Address Masking............................................ 143
Slope Control............................................................ 144
© 2007 Microchip Technology Inc.
Preliminary
DS70289A-page 235
PIC24HJ32GP202/204 and PIC24HJ16GP304
Software Controlled Clock Stretching (STREN = 1).. 143
I C Module
I2C1 Register Map...................................................... 27
P
2
Packaging......................................................................... 227
Details....................................................................... 228
Marking..................................................................... 227
Peripheral Module Disable (PMD) ...................................... 92
PICSTART Plus Development Programmer..................... 192
Pinout I/O Descriptions (table)............................................ 11
PMD Module
Register Map .............................................................. 33
POR and Long Oscillator Start-up Times ........................... 51
PORTA
In-Circuit Debugger........................................................... 179
In-Circuit Emulation........................................................... 173
In-Circuit Serial Programming (ICSP)....................... 173, 179
Infrared Support
Built-in IrDA Encoder and Decoder........................... 153
External IrDA, IrDA Clock Output.............................. 153
Input Capture
Registers................................................................... 126
Input Change Notification.................................................... 94
Instruction Addressing Modes............................................. 34
File Register Instructions ............................................ 34
Fundamental Modes Supported.................................. 35
MCU Instructions ........................................................ 34
Move and Accumulator Instructions............................ 35
Other Instructions........................................................ 35
Instruction Set
Register Map .............................................................. 32
PORTB
Register Map .............................................................. 32
Power-Saving Features...................................................... 91
Clock Frequency and Switching ................................. 91
Program Address Space..................................................... 19
Construction ............................................................... 36
Data Access from Program Memory Using
Overview................................................................... 184
Summary................................................................... 181
Instruction-Based Power-Saving Modes............................. 91
Idle .............................................................................. 92
Sleep........................................................................... 91
Internal RC Oscillator
Program Space Visibility..................................... 39
Data Access from Program Memory Using
Table Instructions ............................................... 38
Data Access from, Address Generation ..................... 37
Memory Map............................................................... 19
Table Read Instructions
Use with WDT........................................................... 177
Internet Address................................................................ 238
Interrupt Control and Status Registers................................ 57
IECx ............................................................................ 57
IFSx............................................................................. 57
INTCON1 .................................................................... 57
INTCON2 .................................................................... 57
IPCx ............................................................................ 57
Interrupt Setup Procedures................................................. 79
Initialization ................................................................. 79
Interrupt Disable.......................................................... 79
Interrupt Service Routine ............................................ 79
Trap Service Routine .................................................. 79
Interrupt Vector Table (IVT) ................................................ 53
Interrupts Coincident with Power Save Instructions............ 92
TBLRDH ............................................................. 38
TBLRDL.............................................................. 38
Visibility Operation...................................................... 39
Program Memory
Interrupt Vector........................................................... 20
Organization ............................................................... 20
Reset Vector............................................................... 20
Pulse-Width Modulation Mode.......................................... 128
PWM
Duty Cycle ................................................................ 128
Period ....................................................................... 128
R
Reader Response............................................................. 239
Registers
AD1CHS0 (ADC1 Input Channel 0 Select................ 169
AD1CHS123 (ADC1 Input Channel 1, 2, 3 Select)... 167
AD1CON1 (ADC1 Control 1).................................... 163
AD1CON2 (ADC1 Control 2).................................... 165
AD1CON3 (ADC1 Control 3).................................... 166
AD1CSSL (ADC1 Input Scan Select Low) ............... 171
AD1PCFGL (ADC1 Port Configuration Low)............ 171
CLKDIV (Clock Divisor) .............................................. 86
CORCON (Core Control)...................................... 17, 59
I2CxCON (I2Cx Control)........................................... 145
I2CxMSK (I2Cx Slave Mode Address Mask)............ 149
I2CxSTAT (I2Cx Status)........................................... 147
ICxCON (Input Capture x Control)............................ 126
IEC0 (Interrupt Enable Control 0)................... 66, 68, 69
IFS0 (Interrupt Flag Status 0)..................................... 62
IFS1 (Interrupt Flag Status 1)..................................... 64
IFS4 (Interrupt Flag Status 4)..................................... 65
INTCON1 (Interrupt Control 1) ................................... 60
INTCON2 (Interrupt Control 2) ................................... 61
INTTREG Interrupt Control and Status Register ........ 78
IPC0 (Interrupt Priority Control 0)............................... 70
IPC1 (Interrupt Priority Control 1)............................... 71
IPC16 (Interrupt Priority Control 16)........................... 77
IPC2 (Interrupt Priority Control 2)............................... 72
IPC3 (Interrupt Priority Control 3)............................... 73
J
JTAG Boundary Scan Interface ........................................ 173
M
Memory Organization.......................................................... 19
Microchip Internet Web Site.............................................. 238
MPLAB ASM30 Assembler, Linker, Librarian ................... 190
MPLAB ICD 2 In-Circuit Debugger ................................... 191
MPLAB ICE 2000 High-Performance Universal In-Circuit
Emulator.................................................................... 191
MPLAB Integrated Development Environment Software .. 189
MPLAB PM3 Device Programmer .................................... 191
MPLAB REAL ICE In-Circuit Emulator System................. 191
MPLINK Object Linker/MPLIB Object Librarian ................ 190
Multi-Bit Data Shifter ........................................................... 18
N
NVM Module
Register Map............................................................... 33
O
Open-Drain Configuration ................................................... 94
Output Compare ............................................................... 127
Registers................................................................... 131
© 2007 Microchip Technology Inc.
Preliminary
DS70289A-page 236
PIC24HJ32GP202/204 and PIC24HJ16GP304
IPC4 (Interrupt Priority Control 4) ............................... 74
IPC5 (Interrupt Priority Control 5) ............................... 75
IPC7 (Interrupt Priority Control 7) ............................... 76
NVMCOM (Flash Memory Control)....................... 43, 44
OCxCON (Output Compare x Control) ..................... 131
OSCCON (Oscillator Control) ..................................... 84
OSCTUN (FRC Oscillator Tuning).............................. 88
PLLFBD (PLL Feedback Divisor)................................ 87
RCON (Reset Control)................................................ 48
SPIxCON1 (SPIx Control 1)...................................... 138
SPIxCON2 (SPIx Control 2)...................................... 140
SPIxSTAT (SPIx Status and Control) ....................... 137
SR (CPU Status)................................................... 16, 58
T1CON (Timer1 Control)........................................... 118
TxCON (T2CON, T4CON, T6CON or
SPIx Master Mode (CKE = 0) ................................... 212
SPIx Master Mode (CKE = 1) ................................... 213
SPIx Slave Mode (CKE = 0)..................................... 214
SPIx Slave Mode (CKE = 1)..................................... 215
Timer1, 2, 3, 4, 5, 6, 7, 8, 9 External Clock .............. 208
Timing Requirements
CLKO and I/O........................................................... 205
External Clock .......................................................... 203
Input Capture............................................................ 210
Timing Specifications
10-bit A/D Conversion Requirements....................... 226
12-bit A/D Conversion Requirements....................... 224
I2Cx Bus Data Requirements (Master Mode)........... 218
I2Cx Bus Data Requirements (Slave Mode)............. 220
Output Compare Requirements................................ 210
PLL Clock ................................................................. 204
Reset, Watchdog Timer, Oscillator Start-up Timer,
Power-up Timer and Brown-out Reset
Requirements ................................................... 207
Simple OC/PWM Mode Requirements..................... 211
SPIx Master Mode (CKE = 0) Requirements............ 212
SPIx Master Mode (CKE = 1) Requirements............ 213
SPIx Slave Mode (CKE = 0) Requirements.............. 214
SPIx Slave Mode (CKE = 1) Requirements.............. 216
Timer1 External Clock Requirements....................... 208
Timer2, Timer4, Timer6 and Timer8 External
T8CON Control)................................................ 122
TyCON (T3CON, T5CON, T7CON or
T9CON Control)................................................ 123
UxMODE (UARTx Mode).......................................... 154
UxSTA (UARTx Status and Control)......................... 156
Reset
Clock Source Selection............................................... 50
Special Function Register Reset States ..................... 51
Times .......................................................................... 50
Reset Sequence ................................................................. 53
Resets................................................................................. 47
Clock Requirements ......................................... 209
Timer3, Timer5, Timer7 and Timer9 External
S
Serial Peripheral Interface (SPI) ....................................... 133
Setup for Continuous Output Pulse Generation................ 127
Setup for Single Output Pulse Generation........................ 127
Software Simulator (MPLAB SIM)..................................... 190
Software Stack Pointer, Frame Pointer
Clock Requirements ......................................... 209
U
UART
Baud Rate
CALL Stack Frame...................................................... 34
Special Features of the CPU ............................................ 173
SPI
Master, Frame Master Connection ........................... 135
Master/Slave Connection.......................................... 135
Slave, Frame Master Connection ............................. 136
Slave, Frame Slave Connection ............................... 136
SPI Module
Generator (BRG) .............................................. 152
Break and Sync Transmit Sequence........................ 153
Flow Control Using UxCTS and UxRTS Pins........... 153
Receiving in 8-bit or 9-bit Data Mode ....................... 153
Transmitting in 8-bit Data Mode ............................... 153
Transmitting in 9-bit Data Mode ............................... 153
UART Module
UART1 Register Map ................................................. 27
SPI1 Register Map...................................................... 27
Symbols Used in Opcode Descriptions............................. 182
V
Voltage Regulator (On-Chip) ............................................ 176
T
W
Temperature and Voltage Specifications
Watchdog Timer (WDT)............................................ 173, 177
Programming Considerations................................... 177
WWW Address ................................................................. 238
WWW, On-Line Support ....................................................... 7
AC............................................................................. 202
Timer1............................................................................... 117
Timer2/3, Timer4/5, Timer6/7 and Timer8/9 ..................... 119
Timing Characteristics
CLKO and I/O ........................................................... 205
Timing Diagrams
10-bit A/D Conversion............................................... 225
10-bit A/D Conversion (CHPS = 01, SIMSAM = 0,
ASAM = 0, SSRC = 000) .................................. 225
12-bit A/D Conversion (ASAM = 0, SSRC = 000)..... 224
External Clock........................................................... 203
I2Cx Bus Data (Master Mode) .................................. 217
I2Cx Bus Data (Slave Mode) .................................... 219
I2Cx Bus Start/Stop Bits (Master Mode)................... 217
I2Cx Bus Start/Stop Bits (Slave Mode)..................... 219
Input Capture (CAPx)................................................ 210
OC/PWM................................................................... 211
Output Compare (OCx)............................................. 210
Reset, Watchdog Timer, Oscillator Start-up Timer and
Power-up Timer ................................................ 206
© 2007 Microchip Technology Inc.
Preliminary
DS70289A-page 237
PIC24HJ32GP202/204 and PIC24HJ16GP304
NOTES:
DS70289A-page 238
Preliminary
© 2007 Microchip Technology Inc.
PIC24HJ32GP202/204 and PIC24HJ16GP304
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CUSTOMER SUPPORT
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Preliminary
DS70289A-page 239
PIC24HJ32GP202/204 and PIC24HJ16GP304
READER RESPONSE
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PIC24HJ32GP202/204 and
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DS70289A
Literature Number:
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Questions:
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© 2007 Microchip Technology Inc.
PIC24HJ32GP202/204 and PIC24HJ16GP304
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
Examples:
a) PIC24HJ32GP202-E/SP:
PIC 24 HJ 32 GP2 02 T E / SP - XXX
General-purpose PIC24H, 32 KB program
memory, 28-pin, Extended temp.,
SPDIP package.
Microchip Trademark
Architecture
Flash Memory Family
Program Memory Size (KB)
Product Group
Pin Count
Tape and Reel Flag (if applicable)
Temperature Range
Package
Pattern
Architecture:
24
=
=
16-bit Microcontroller
Flash Memory Family: HJ
Flash program memory, 3.3V
Product Group:
Pin Count:
GP2
=
=
General purpose family
General purpose family
GP3
02
03
=
=
28-pin
44-pin
Temperature Range:
Package:
I
=
=
-40°C to +85°C (Industrial)
-40°C to +125°C (Extended)
E
SP
SO
MM
PT
=
=
=
=
=
Skinny Plastic Dual In-Line - 300 mil body (SPDIP)
Plastic Small Outline - Wide - 7.5 mm body (SOIC)
Plastic Quad, No Lead Package - 6x6 mm body (QFN-S)
Plastic Thin Quad Flatpack - 10x10x1 mm body (TQFP
Plastic Quad, No Lead Package - 8x8 mm body (QFN)
ML
© 2007 Microchip Technology Inc.
Preliminary
DS70289A-page 241
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06/25/07
DS70289A-page 242
Preliminary
© 2007 Microchip Technology Inc.
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