PIC24HJ64GP506AI/PF-ES [MICROCHIP]
High-Performance, 16-Bit Microcontrollers; 高性能16位微控制器型号: | PIC24HJ64GP506AI/PF-ES |
厂家: | MICROCHIP |
描述: | High-Performance, 16-Bit Microcontrollers |
文件: | 总294页 (文件大小:4321K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
PIC24HJXXXGPX06A/X08A/X10A
Data Sheet
High-Performance,
16-Bit Microcontrollers
© 2009 Microchip Technology Inc.
Preliminary
DS70592A
Note the following details of the code protection feature on Microchip devices:
•
Microchip products meet the specification contained in their particular Microchip Data Sheet.
•
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
•
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
•
•
Microchip is willing to work with the customer who is concerned about the integrity of their code.
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION,
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
QUALITY, PERFORMANCE, MERCHANTABILITY OR
FITNESS FOR PURPOSE. Microchip disclaims all liability
arising from this information and its use. Use of Microchip
devices in life support and/or safety applications is entirely at
the buyer’s risk, and the buyer agrees to defend, indemnify and
hold harmless Microchip from any and all damages, claims,
suits, or expenses resulting from such use. No licenses are
conveyed, implicitly or otherwise, under any Microchip
intellectual property rights.
Trademarks
The Microchip name and logo, the Microchip logo, Accuron,
dsPIC, KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro,
PICSTART, rfPIC, SmartShunt and UNI/O are registered
trademarks of Microchip Technology Incorporated in the
U.S.A. and other countries.
FilterLab, Linear Active Thermistor, MXDEV, MXLAB,
SEEVAL, SmartSensor and The Embedded Control Solutions
Company are registered trademarks of Microchip Technology
Incorporated in the U.S.A.
Analog-for-the-Digital Age, Application Maestro, CodeGuard,
dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN,
ECONOMONITOR, FanSense, In-Circuit Serial
Programming, ICSP, ICEPIC, Mindi, MiWi, MPASM, MPLAB
Certified logo, MPLIB, MPLINK, mTouch, nanoWatt XLP,
PICkit, PICDEM, PICDEM.net, PICtail, PIC32 logo, PowerCal,
PowerInfo, PowerMate, PowerTool, REAL ICE, rfLAB, Select
Mode, Total Endurance, TSHARC, WiperLock and ZENA are
trademarks of Microchip Technology Incorporated in the
U.S.A. and other countries.
SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.
All other trademarks mentioned herein are property of their
respective companies.
© 2009, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.
Printed on recycled paper.
Microchip received ISO/TS-16949:2002 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
DS70592A-page ii
Preliminary
© 2009 Microchip Technology Inc.
PIC24HJXXXGPX06A/X08A/X10A
High-Performance, 16-Bit Microcontrollers
Operating Range:
On-Chip Flash and SRAM:
• Up to 40 MIPS operation (at 3.0-3.6V):
• Flash program memory, up to 256 Kbytes
- Industrial temperature range
(-40°C to +85°C)
• Data SRAM, up to 16 Kbytes (includes 2 Kbytes
of DMA RAM)
- Extended temperature range
(-40°C to +125°C)
System Management:
• Flexible clock options:
High-Performance CPU:
- External, crystal, resonator, internal RC
- Fully integrated PLL
• Modified Harvard architecture
• C compiler optimized instruction set
• 16-bit wide data path
- Extremely low jitter PLL
• Power-up Timer
• 24-bit wide instructions
• Oscillator Start-up Timer/Stabilizer
• Watchdog Timer with its own RC oscillator
• Fail-Safe Clock Monitor
• Linear program memory addressing up to 4M
instruction words
• Linear data memory addressing up to 64 Kbytes
• 71 base instructions: mostly 1 word/1 cycle
• Sixteen 16-bit General Purpose Registers
• Flexible and powerful Indirect Addressing modes
• Software stack
• Reset by multiple sources
Power Management:
• On-chip 2.5V voltage regulator
• 16 x 16 multiply operations
• Switch between clock sources in real time
• Idle, Sleep and Doze modes with fast wake-up
• 32/16 and 16/16 divide operations
• Up to ±16-bit data shifts
Timers/Capture/Compare/PWM:
Direct Memory Access (DMA):
• Timer/Counters, up to nine 16-bit timers:
- Can pair up to make four 32-bit timers
• 8-channel hardware DMA
• 2 Kbytes dual ported DMA buffer area
(DMA RAM) to store data transferred via DMA:
- One timer runs as Real-Time Clock with
external 32.768 kHz oscillator
- Allows data transfer between RAM and a
peripheral while CPU is executing code
(no cycle stealing)
- Programmable prescaler
• Input Capture (up to eight channels):
- Capture on up, down or both edges
- 16-bit capture input functions
• Most peripherals support DMA
Interrupt Controller:
- 4-deep FIFO on each capture
• 5-cycle latency
• Output Compare (up to eight channels):
- Single or Dual 16-Bit Compare mode
- 16-bit Glitchless PWM mode
• Up to 61 available interrupt sources
• Up to five external interrupts
• Seven programmable priority levels
• FIve processor exceptions
Digital I/O:
• Up to 85 programmable digital I/O pins
• Wake-up/Interrupt-on-Change on up to 24 pins
• Output pins can drive from 3.0V to 3.6V
• All digital input pins are 5V tolerant
• 4 mA sink on all I/O pins
© 2009 Microchip Technology Inc.
Preliminary
DS70592A-page 1
PIC24HJXXXGPX06A/X08A/X10A
Communication Modules:
Analog-to-Digital Converters:
• 3-wire SPI (up to two modules):
• Up to two Analog-to-Digital Converter (ADC)
modules in a device
- Framing supports I/O interface to simple
codecs
• 10-bit, 1.1 Msps or 12-bit, 500 ksps conversion:
- Two, four, or eight simultaneous samples
- Up to 32 input channels with auto-scanning
- Supports 8-bit and 16-bit data
- Supports all serial clock formats and
sampling modes
• I2C™ (up to two modules):
- Conversion start can be manual or
synchronized with one of four trigger sources
- Full Multi-Master Slave mode support
- 7-bit and 10-bit addressing
- Conversion possible in Sleep mode
- ±1 LSb max integral nonlinearity
- ±1 LSb max differential nonlinearity
- Bus collision detection and arbitration
- Integrated signal conditioning
- Slave address masking
CMOS Flash Technology:
• UART (up to two modules):
• Low-power, high-speed Flash technology
• Fully static design
- Interrupt on address bit detect
- Interrupt on UART error
• 3.3V (±10%) operating voltage
• Industrial and extended temperature
• Low-power consumption
- Wake-up on Start bit from Sleep mode
- 4-character TX and RX FIFO buffers
- LIN bus support
- IrDA® encoding and decoding in hardware
Packaging:
- High-Speed Baud mode
• 100-pin TQFP (14x14x1 mm and 12x12x1 mm)
• 64-pin TQFP (10x10x1 mm)
- Hardware Flow Control with CTS and RTS
• Enhanced CAN (ECAN™ module) 2.0B active
(up to two modules):
• 64-pin QFN (9x9x0.9 mm)
- Up to eight transmit and up to 32 receive buffers
- 16 receive filters and 3 masks
Note:
See the device variant tables for exact
peripheral features per device.
- Loopback, Listen Only and Listen All
Messages modes for diagnostics and bus
monitoring
- Wake-up on CAN message
- Automatic processing of Remote
Transmission Requests
- FIFO mode using DMA
- DeviceNet™ addressing support
DS70592A-page 2
Preliminary
© 2009 Microchip Technology Inc.
PIC24HJXXXGPX06A/X08A/X10A
PIC24H PRODUCT FAMILIES
The PIC24H Family of devices is ideal for a wide vari-
ety of 16-bit MCU embedded applications. The device
names, pin counts, memory sizes and peripheral avail-
ability of each device are listed below, followed by their
pinout diagrams.
PIC24H Family Controllers
Program
Device
Pins
Flash
Memory (KB)
PIC24HJ64GP206A
64
64
64
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
9
9
9
9
9
9
9
9
9
9
9
9
9
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
0
0
0
0
0
0
0
0
0
0
0
0
0
1 ADC,
18 ch
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
1
2
2
2
2
2
2
2
2
2
2
2
2
0
0
1
1
0
0
1
1
0
0
0
0
2
53 PT, MR
85 PF, PT
53 PT, MR
85 PF, PT
53 PT, MR
85 PF, PT
53 PT, MR
85 PF, PT
53 PT, MR
85 PF, PT
53 PT, MR
PIC24HJ64GP210A 100
PIC24HJ64GP506A 64
1 ADC,
32 ch
64
8
1 ADC,
18 ch
PIC24HJ64GP510A 100
PIC24HJ128GP206A 64
PIC24HJ128GP210A 100
PIC24HJ128GP506A 64
PIC24HJ128GP510A 100
PIC24HJ128GP306A 64
PIC24HJ128GP310A 100
PIC24HJ256GP206A 64
PIC24HJ256GP210A 100
PIC24HJ256GP610A 100
64
8
1 ADC,
32 ch
128
128
128
128
128
128
256
256
256
8
1 ADC,
18 ch
8
1 ADC,
32 ch
8
1 ADC,
18 ch
8
1 ADC,
32 ch
16
16
16
16
16
1 ADC,
18 ch
1 ADC,
32 ch
1 ADC,
18 ch
1 ADC,
32 ch
85
85
PF, PT
PF, PT
2 ADC,
32 ch
Note 1: RAM size is inclusive of 2 Kbytes DMA RAM.
2: Maximum I/O pin count includes pins shared by the peripheral functions.
© 2009 Microchip Technology Inc.
Preliminary
DS70592A-page 3
PIC24HJXXXGPX06A/X08A/X10A
Pin Diagrams
(1)
64-Pin QFN
= Pins are up to 5V tolerant
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
PGEC2/SOSCO/T1CK/CN0/RC14
PGED2/SOSCI/T4CK/CN1/RC13
OC1/RD0
RG15
AN16/T2CK/T7CK/RC1
AN17/T3CK/T6CK/RC2
SCK2/CN8/RG6
SDI2/CN9/RG7
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
IC4/INT4/RD11
IC3/INT3/RD10
IC2/U1CTS/INT2/RD9
IC1/INT1/RD8
SDO2/CN10/RG8
MCLR
(2)
SS2/CN11/RG9
VSS
PIC24HJ64GP206A
VSS
OSC2/CLKO/RC15
OSC1/CLKIN/RC12
VDD
PIC24HJ128GP206A
PIC24HJ256GP206A
VDD
AN5/IC8/CN7/RB5
AN4/IC7/CN6/RB4
AN3/CN5/RB3
SCL1/RG2
SDA1/RG3
AN2/SS1/CN4/RB2
PGEC3/AN1/VREF-/CN3/RB1
PGED3/AN0/VREF+/CN2/RB0
U1RTS/SCK1/INT0/RF6
U1RX/SDI1/RF2
U1TX/SDO1/RF3
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
Note 1: The metal plane at the bottom of the device is not connected to any pins and should be connected
to VSS externally.
2: The PIC24HJ64GP206A device does not have the SCL2 and SDA2 pins.
DS70592A-page 4
Preliminary
© 2009 Microchip Technology Inc.
PIC24HJXXXGPX06A/X08A/X10A
Pin Diagrams (Continued)
(1)
64-Pin QFN
= Pins are up to 5V tolerant
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
PGEC2/SOSCO/T1CK/CN0/RC14
PGED2/SOSCI/T4CK/CN1/RC13
OC1/RD0
RG15
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
AN16/T2CK/T7CK/RC1
AN17/T3CK/T6CK/RC2
SCK2/CN8/RG6
SDI2/CN9/RG7
IC4/INT4/RD11
IC3/INT3/RD10
IC2/U1CTS/INT2/RD9
IC1/INT1/RD8
SDO2/CN10/RG8
MCLR
SS2/CN11/RG9
VSS
PIC24HJ128GP306A
VSS
OSC2/CLKO/RC15
OSC1/CLKIN/RC12
VDD
VDD
AN5/IC8/CN7/RB5
AN4/IC7/CN6/RB4
AN3/CN5/RB3
SCL1/RG2
SDA1/RG3
AN2/SS1/CN4/RB2
PGEC3/AN1/VREF-/CN3/RB1
PGED3/AN0/VREF+/CN2/RB0
U1RTS/SCK1/INT0/RF6
U1RX/SDI1/RF2
U1TX/SDO1/RF3
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
Note 1: The metal plane at the bottom of the device is not connected to any pins and should be connected
to VSS externally.
© 2009 Microchip Technology Inc.
Preliminary
DS70592A-page 5
PIC24HJXXXGPX06A/X08A/X10A
Pin Diagrams (Continued)
(1)
64-Pin QFN
= Pins are up to 5V tolerant
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
RG15
AN16/T2CK/T7CK/RC1
AN17/T3CK/T6CK/RC2
SCK2/CN8/RG6
SDI2/CN9/RG7
PGEC2/SOSCO/T1CK/CN0/RC14
PGED2/SOSCI/T4CK/CN1/RC13
OC1/RD0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
IC4/INT4/RD11
IC3/INT3/RD10
IC2/U1CTS/INT2/RD9
IC1/INT1/RD8
SDO2/CN10/RG8
MCLR
SS2/CN11/RG9
VSS
PIC24HJ64GP506A
PIC24HJ128GP506A
VSS
OSC2/CLKO/RC15
OSC1/CLKIN/RC12
VDD
VDD
AN5/IC8/CN7/RB5
AN4/IC7/CN6/RB4
AN3/CN5/RB3
SCL1/RG2
SDA1/RG3
AN2/SS1/CN4/RB2
PGEC3/AN1/VREF-/CN3/RB1
PGED3/AN0/VREF+/CN2/RB0
U1RTS/SCK1/INT0/RF6
U1RX/SDI1/RF2
U1TX/SDO1/RF3
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
Note 1: The metal plane at the bottom of the device is not connected to any pins and should be connected
to VSS externally.
DS70592A-page 6
Preliminary
© 2009 Microchip Technology Inc.
PIC24HJXXXGPX06A/X08A/X10A
Pin Diagrams (Continued)
64-Pin TQFP
= Pins are up to 5V tolerant
RG15
1
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
PGEC2/SOSCO/T1CK/CN0/RC14
PGED2/SOSCI/T4CK/CN1/RC13
OC1/RD0
AN16/T2CK/T7CK/RC1
AN17/T3CK/T6CK/RC2
SCK2/CN8/RG6
SDI2/CN9/RG7
SDO2/CN10/RG8
MCLR
2
3
4
IC4/INT4/RD11
5
IC3/INT3/RD10
IC2/U1CTS/INT2/RD9
IC1/INT1/RD8
6
7
SS2/CN11/RG9
VSS
8
VSS
PIC24HJ64GP206A
PIC24HJ128GP206A
PIC24HJ256GP206A
9
OSC2/CLKO/RC15
OSC1/CLKIN/RC12
VDD
VDD
10
11
12
13
14
15
16
AN5/IC8/CN7/RB5
AN4/IC7/CN6/RB4
AN3/CN5/RB3
AN2/SS1/CN4/RB2
SCL1/RG2
SDA1/RG3
U1RTS/SCK1/INT0/RF6
U1RX/SDI1/RF2
U1TX/SDO1/RF3
PGEC3/AN1/VREF-/CN3/RB1
PGED3/AN0/VREF+/CN2/RB0
Note:
The PIC24HJ64GP206A device does not have the SCL2 and SDA2 pins.
© 2009 Microchip Technology Inc.
Preliminary
DS70592A-page 7
PIC24HJXXXGPX06A/X08A/X10A
Pin Diagrams (Continued)
64-Pin TQFP
= Pins are up to 5V tolerant
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
PGEC2/SOSCO/T1CK/CN0/RC14
PGED2/SOSCI/T4CK/CN1/RC13
OC1/RD0
RG15
AN16/T2CK/T7CK/RC1
AN17/T3CK/T6CK/RC2
SCK2/CN8/RG6
SDI2/CN9/RG7
SDO2/CN10/RG8
MCLR
1
2
3
IC4/INT4/RD11
4
IC3/INT3/RD10
IC2/U1CTS/INT2/RD9
IC1/INT1/RD8
5
6
7
PIC24HJ128GP306A
SS2/CN11/RG9
VSS
8
VSS
9
OSC2/CLKO/RC15
OSC1/CLKIN/RC12
VDD
VDD
10
11
12
13
14
15
16
AN5/IC8/CN7/RB5
AN4/IC7/CN6/RB4
AN3/CN5/RB3
AN2/SS1/CN4/RB2
SCL1/RG2
SDA1/RG3
U1RTS/SCK1/INT0/RF6
U1RX/SDI1/RF2
U1TX/SDO1/RF3
PGEC3/AN1/VREF-/CN3/RB1
PGED3/AN0/VREF+/CN2/RB0
DS70592A-page 8
Preliminary
© 2009 Microchip Technology Inc.
PIC24HJXXXGPX06A/X08A/X10A
Pin Diagrams (Continued)
64-Pin TQFP
= Pins are up to 5V tolerant
RG15
1
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
PGEC2/SOSCO/T1CK/CN0/RC14
PGED2/SOSCI/T4CK/CN1/RC13
OC1/RD0
AN16/T2CK/T7CK/RC1
AN17/T3CK/T6CK/RC2
SCK2/CN8/RG6
SDI2/CN9/RG7
SDO2/CN10/RG8
MCLR
2
3
4
IC4/INT4/RD11
5
IC3/INT3/RD10
IC2/U1CTS/INT2/RD9
IC1/INT1/RD8
6
7
SS2/CN11/RG9
VSS
8
VSS
PIC24HJ64GP506A
PIC24HJ128GP506A
9
OSC2/CLKO/RC15
OSC1/CLKIN/RC12
VDD
VDD
10
11
12
13
14
15
16
AN5/IC8/CN7/RB5
AN4/IC7/CN6/RB4
AN3/CN5/RB3
AN2/SS1/CN4/RB2
SCL1/RG2
SDA1/RG3
U1RTS/SCK1/INT0/RF6
U1RX/SDI1/RF2
U1TX/SDO1/RF3
PGEC3/AN1/VREF-/CN3/RB1
PGED3/AN0/VREF+/CN2/RB0
© 2009 Microchip Technology Inc.
Preliminary
DS70592A-page 9
PIC24HJXXXGPX06A/X08A/X10A
Pin Diagrams (Continued)
100-Pin TQFP
= Pins are up to 5V tolerant
V
SS
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
1
RG15
PGEC2/SOSCO/T1CK/CN0/RC14
PGED2/SOSCI/CN1/RC13
OC1/RD0
VDD
2
AN29/RE5
AN30/RE6
3
4
IC4/RD11
AN31/RE7
5
IC3/RD10
AN16/T2CK/T7CK/RC1
AN17/T3CK/T6CK/RC2
AN18/T4CK/T9CK/RC3
AN19/T5CK/T8CK/RC4
SCK2/CN8/RG6
SDI2/CN9/RG7
6
IC2/RD9
7
IC1/RD8
8
INT4/RA15
9
INT3/RA14
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
VSS
OSC2/CLKO/RC15
OSC1/CLKIN/RC12
SDO2/CN10/RG8
MCLR
PIC24HJ64GP210A
PIC24HJ128GP210A
PIC24HJ128GP310A
PIC24HJ256GP210A
VDD
SS2/CN11/RG9
VSS
TDO/RA5
VDD
TDI/RA4
TMS/RA0
AN20/INT1/RA12
AN21/INT2/RA13
AN5/CN7/RB5
SDA2/RA3
SCL2/RA2
SCL1/RG2
SDA1/RG3
SCK1/INT0/RF6
SDI1/RF7
AN4/CN6/RB4
AN3/CN5/RB3
AN2/SS1/CN4/RB2
SDO1/RF8
U1RX/RF2
U1TX/RF3
PGEC3/AN1/CN3/RB1
PGED3/AN0/CN2/RB0
DS70592A-page 10
Preliminary
© 2009 Microchip Technology Inc.
PIC24HJXXXGPX06A/X08A/X10A
Pin Diagrams (Continued)
100-Pin TQFP
= Pins are up to 5V tolerant
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
V
SS
1
RG15
PGEC2/SOSCO/T1CK/CN0/RC14
PGED2/SOSCI/CN1/RC13
OC1/RD0
VDD
2
3
AN29/RE5
AN30/RE6
4
IC4/RD11
AN31/RE7
5
IC3/RD10
AN16/T2CK/T7CK/RC1
AN17/T3CK/T6CK/RC2
AN18/T4CK/T9CK/RC3
AN19/T5CK/T8CK/RC4
6
IC2/RD9
7
IC1/RD8
8
INT4/RA15
9
INT3/RA14
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
SCK2/CN8/RG6
SDI2/CN9/RG7
SDO2/CN10/RG8
MCLR
VSS
OSC2/CLKO/RC15
OSC1/CLKIN/RC12
PIC24HJ64GP510A
PIC24HJ128GP510A
VDD
SS2/CN11/RG9
VSS
TDO/RA5
VDD
TDI/RA4
TMS/RA0
AN20/INT1/RA12
AN21/INT2/RA13
AN5/CN7/RB5
SDA2/RA3
SCL2/RA2
SCL1/RG2
SDA1/RG3
SCK1/INT0/RF6
SDI1/RF7
AN4/CN6/RB4
AN3/CN5/RB3
AN2/SS1/CN4/RB2
PGEC3/AN1/CN3/RB1
PGED3/AN0/CN2/RB0
SDO1/RF8
U1RX/RF2
U1TX/RF3
© 2009 Microchip Technology Inc.
Preliminary
DS70592A-page 11
PIC24HJXXXGPX06A/X08A/X10A
Pin Diagrams (Continued)
100-Pin TQFP
= Pins are up to 5V tolerant
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
VSS
1
RG15
PGEC2/SOSCO/T1CK/CN0/RC14
PGED2/SOSCI/CN1/RC13
OC1/RD0
VDD
2
AN29/RE5
AN30/RE6
3
4
IC4/RD11
AN31/RE7
5
IC3/RD10
AN16/T2CK/T7CK/RC1
AN17/T3CK/T6CK/RC2
AN18/T4CK/T9CK/RC3
AN19/T5CK/T8CK/RC4
SCK2/CN8/RG6
6
IC2/RD9
7
IC1/RD8
8
INT4/RA15
9
INT3/RA14
10
11
12
VSS
SDI2/CN9/RG7
SDO2/CN10/RG8
MCLR
OSC2/CLKO/RC15
OSC1/CLKIN/RC12
PIC24HJ256GP610A
13
14
15
16
17
18
19
20
21
22
23
24
25
VDD
SS2/CN11/RG9
VSS
TDO/RA5
VDD
TDI/RA4
TMS/RA0
AN20/INT1/RA12
AN21/INT2/RA13
SDA2/RA3
SCL2/RA2
SCL1/RG2
SDA1/RG3
SCK1/INT0/RF6
SDI1/RF7
AN5/CN7/RB5
AN4/CN6/RB4
AN3/CN5/RB3
AN2/SS1/CN4/RB2
SDO1/RF8
U1RX/RF2
U1TX/RF3
PGEC3/AN1/CN3/RB1
PGED3/AN0/CN2/RB0
DS70592A-page 12
Preliminary
© 2009 Microchip Technology Inc.
PIC24HJXXXGPX06A/X08A/X10A
Table of Contents
PIC24H Product Families....................................................................................................................................................................... 3
1.0 Device Overview ........................................................................................................................................................................ 15
2.0 Guidelines for Getting Started with 16-Bit Microcontrollers........................................................................................................ 19
3.0 CPU............................................................................................................................................................................................ 23
4.0 Memory Organization................................................................................................................................................................. 29
5.0 Flash Program Memory.............................................................................................................................................................. 59
6.0 Reset ......................................................................................................................................................................................... 65
7.0 Interrupt Controller ..................................................................................................................................................................... 71
8.0 Direct Memory Access (DMA).................................................................................................................................................. 115
9.0 Oscillator Configuration............................................................................................................................................................ 125
10.0 Power-Saving Features............................................................................................................................................................ 135
11.0 I/O Ports ................................................................................................................................................................................... 143
12.0 Timer1 ...................................................................................................................................................................................... 145
13.0 Timer2/3, Timer4/5, Timer6/7 and Timer8/9 ............................................................................................................................ 147
14.0 Input Capture............................................................................................................................................................................ 153
15.0 Output Compare....................................................................................................................................................................... 155
16.0 Serial Peripheral Interface (SPI)............................................................................................................................................... 159
17.0 Inter-Integrated Circuit™ (I2C™).............................................................................................................................................. 165
18.0 Universal Asynchronous Receiver Transmitter (UART)........................................................................................................... 173
19.0 Enhanced CAN (ECAN™) Module........................................................................................................................................... 179
20.0 10-Bit/12-Bit Analog-to-Digital Converter (ADC) ...................................................................................................................... 205
21.0 Special Features ...................................................................................................................................................................... 217
22.0 Instruction Set Summary.......................................................................................................................................................... 225
23.0 Development Support............................................................................................................................................................... 233
24.0 Electrical Characteristics.......................................................................................................................................................... 237
25.0 Packaging Information.............................................................................................................................................................. 273
Appendix A: Migrating from PIC24HJXXXGPX06/X08/X10 Devices to PIC24HJXXXGPX06A/X08A/X10A Devices....................... 283
Appendix B: Revision History............................................................................................................................................................. 284
Index ................................................................................................................................................................................................. 285
The Microchip Web Site..................................................................................................................................................................... 289
Customer Change Notification Service.............................................................................................................................................. 289
Customer Support.............................................................................................................................................................................. 289
Reader Response.............................................................................................................................................................................. 290
Product Identification System ............................................................................................................................................................ 291
© 2009 Microchip Technology Inc.
Preliminary
DS70592A-page 13
PIC24HJXXXGPX06A/X08A/X10A
TO OUR VALUED CUSTOMERS
It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip
products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and
enhanced as new volumes and updates are introduced.
If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via
E-mail at docerrors@microchip.com or fax the Reader Response Form in the back of this data sheet to (480) 792-4150. We
welcome your feedback.
Most Current Data Sheet
To obtain the most up-to-date version of this data sheet, please register at our Worldwide Web site at:
http://www.microchip.com
You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page.
The last character of the literature number is the version number, (e.g., DS30000A is version A of document DS30000).
Errata
An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current
devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision
of silicon and revision of document to which it applies.
To determine if an errata sheet exists for a particular device, please check with one of the following:
•
•
Microchip’s Worldwide Web site; http://www.microchip.com
Your local Microchip sales office (see last page)
When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are
using.
Customer Notification System
Register on our web site at www.microchip.com to receive the most current information on all of our products.
DS70592A-page 14
Preliminary
© 2009 Microchip Technology Inc.
PIC24HJXXXGPX06A/X08A/X10A
This makes these families suitable for a wide variety of
1.0
DEVICE OVERVIEW
high-performance digital signal control applications.
The devices are pin compatible with the dsPIC33F fam-
ily of devices, and also share a very high degree of
compatibility with the dsPIC30F family devices. This
allows easy migration between device families as may
be necessitated by the specific functionality, computa-
tional resource and system cost requirements of the
application.
Note:
This data sheet summarizes the features
of the PIC24HJXXXGPX06A/X08A/X10A
family of devices. However, it is not
intended to be a comprehensive reference
source. To complement the information in
this data sheet, refer to the latest family
reference sections of the “PIC24H Family
Reference Manual”, which is available
from the Microchip web site (www.micro-
chip.com).
The PIC24HJXXXGPX06A/X08A/X10A device family
employs a powerful 16-bit architecture, ideal for
applications that rely on high-speed, repetitive
computations, as well as control.
This document contains device specific information for
the following devices:
The 17 x 17 multiplier, hardware support for division
operations, multi-bit data shifter, a large array of 16-bit
working registers and a wide variety of data addressing
• PIC24HJ64GP206A
• PIC24HJ64GP210A
• PIC24HJ64GP506A
• PIC24HJ64GP510A
• PIC24HJ128GP206A
• PIC24HJ128GP210A
• PIC24HJ128GP506A
• PIC24HJ128GP510A
• PIC24HJ128GP306A
• PIC24HJ128GP310A
• PIC24HJ256GP206A
• PIC24HJ256GP210A
• PIC24HJ256GP610A
modes,
together
provide
the
PIC24HJXXXGPX06A/X08A/X10A Central Processing
Unit (CPU) with extensive mathematical processing
capability. Flexible and deterministic interrupt handling,
coupled with a powerful array of peripherals, renders
the PIC24HJXXXGPX06A/X08A/X10A devices suit-
able for control applications. Further, Direct Memory
Access (DMA) enables overhead-free transfer of data
between several peripherals and a dedicated DMA
RAM. Reliable, field programmable Flash program
memory ensures scalability of applications that use
PIC24HJXXXGPX06A/X08A/X10A devices.
Figure 1-1 shows a general block diagram of the
various core and peripheral modules in the
PIC24HJXXXGPX06A/X08A/X10A family of devices,
while Table 1-1 lists the functions of the various pins
shown in the pinout diagrams.
The PIC24HJXXXGPX06A/X08A/X10A device family
includes devices with different pin counts (64 and 100
pins), different program memory sizes (64 Kbytes, 128
Kbytes and 256 Kbytes) and different RAM sizes (8
Kbytes and 16 Kbytes).
© 2009 Microchip Technology Inc.
Preliminary
DS70592A-page 15
PIC24HJXXXGPX06A/X08A/X10A
FIGURE 1-1:
PIC24HJXXXGPX06A/X08A/X10A GENERAL BLOCK DIAGRAM
PSV and Table
Data Access
Control Block
Data Bus
Interrupt
Controller
PORTA
PORTB
16
16
16
8
DMA
RAM
Data Latch
X RAM
23
PCH PCL
Program Counter
PCU
23
Address
Latch
Loop
Control
Logic
Stack
Control
Logic
DMA
16
Controller
23
16
PORTC
PORTD
PORTE
PORTF
PORTG
Address Generator Units
Address Latch
Program Memory
Data Latch
EA MUX
ROM Latch
24
16
16
Instruction
Decode and
Control
Instruction Reg
16
Control Signals
to Various Blocks
17 x 17 Multiplier
Divide Support
16 x 16
W Register Array
Power-up
Timer
Timing
Generation
OSC2/CLKO
OSC1/CLKI
16
Oscillator
Start-up Timer
FRC/LPRC
Oscillators
Power-on
Reset
16-bit ALU
Precision
Band Gap
Reference
Watchdog
Timer
16
Brown-out
Reset
Voltage
Regulator
VCAP/VDDCORE
VDD, VSS
MCLR
Timers
1-9
ADC1,2
ECAN1,2
UART1,2
OC/
IC1-8
CN1-23
SPI1,2
I2C1,2
PWM1-8
Note:
Not all pins or features are implemented on all device pinout configurations. See pinout diagrams for the specific pins
and features present on each device.
DS70592A-page 16
Preliminary
© 2009 Microchip Technology Inc.
PIC24HJXXXGPX06A/X08A/X10A
TABLE 1-1:
Pin Name
PINOUT I/O DESCRIPTIONS
Pin
Buffer
Description
Type
Type
AN0-AN31
AVDD
I
Analog Analog input channels.
P
P
P
P
Positive supply for analog modules. This pin must be connected at all times.
Ground reference for analog modules.
AVSS
CLKI
I
ST/CMOS External clock source input. Always associated with OSC1 pin function.
CLKO
O
—
Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator
mode. Optionally functions as CLKO in RC and EC modes. Always associated
with OSC2 pin function.
CN0-CN23
I
ST
Input change notification inputs.
Can be software programmed for internal weak pull-ups on all inputs.
C1RX
C1TX
C2RX
C2TX
I
O
I
ST
—
ST
—
ECAN1 bus receive pin.
ECAN1 bus transmit pin.
ECAN2 bus receive pin.
ECAN2 bus transmit pin.
O
PGED1
PGEC1
PGED2
PGEC2
PGED3
PGEC3
I/O
ST
ST
ST
ST
ST
ST
Data I/O pin for programming/debugging communication channel 1.
Clock input pin for programming/debugging communication channel 1.
Data I/O pin for programming/debugging communication channel 2.
Clock input pin for programming/debugging communication channel 2.
Data I/O pin for programming/debugging communication channel 3.
Clock input pin for programming/debugging communication channel 3.
I
I/O
I
I/O
I
IC1-IC8
I
ST
Capture inputs 1 through 8.
INT0
INT1
INT2
INT3
INT4
I
I
I
I
I
ST
ST
ST
ST
ST
External interrupt 0.
External interrupt 1.
External interrupt 2.
External interrupt 3.
External interrupt 4.
MCLR
I/P
ST
Master Clear (Reset) input. This pin is an active-low Reset to the device.
OCFA
OCFB
OC1-OC8
I
I
O
ST
ST
—
Compare Fault A input (for Compare Channels 1, 2, 3 and 4).
Compare Fault B input (for Compare Channels 5, 6, 7 and 8).
Compare outputs 1 through 8.
OSC1
I
ST/CMOS Oscillator crystal input. ST buffer when configured in RC mode; CMOS
otherwise.
OSC2
I/O
—
Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator
mode. Optionally functions as CLKO in RC and EC modes.
RA0-RA7
RA9-RA10
RA12-RA15
I/O
I/O
I/O
ST
ST
ST
PORTA is a bidirectional I/O port.
RB0-RB15
I/O
ST
PORTB is a bidirectional I/O port.
PORTC is a bidirectional I/O port.
RC1-RC4
RC12-RC15
I/O
I/O
ST
ST
RD0-RD15
RE0-RE7
I/O
I/O
I/O
ST
ST
ST
PORTD is a bidirectional I/O port.
PORTE is a bidirectional I/O port.
PORTF is a bidirectional I/O port.
RF0-RF8
RF12-RF13
RG0-RG3
RG6-RG9
RG12-RG15
I/O
I/O
I/O
ST
ST
ST
PORTG is a bidirectional I/O port.
Legend: CMOS = CMOS compatible input or output
Analog = Analog input
O = Output
P = Power
I = Input
ST = Schmitt Trigger input with CMOS levels
© 2009 Microchip Technology Inc.
Preliminary
DS70592A-page 17
PIC24HJXXXGPX06A/X08A/X10A
TABLE 1-1:
Pin Name
PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin
Buffer
Type
Description
Type
SCK1
SDI1
SDO1
SS1
SCK2
SDI2
SDO2
SS2
I/O
I
O
I/O
I/O
I
ST
ST
—
ST
ST
ST
—
Synchronous serial clock input/output for SPI1.
SPI1 data in.
SPI1 data out.
SPI1 slave synchronization or frame pulse I/O.
Synchronous serial clock input/output for SPI2.
SPI2 data in.
O
I/O
SPI2 data out.
SPI2 slave synchronization or frame pulse I/O.
ST
SCL1
SDA1
SCL2
SDA2
I/O
I/O
I/O
I/O
ST
ST
ST
ST
Synchronous serial clock input/output for I2C1.
Synchronous serial data input/output for I2C1.
Synchronous serial clock input/output for I2C2.
Synchronous serial data input/output for I2C2.
SOSCI
I
ST/CMOS 32.768 kHz low-power oscillator crystal input; CMOS otherwise.
SOSCO
O
—
32.768 kHz low-power oscillator crystal output.
TMS
TCK
TDI
I
I
I
ST
ST
ST
—
JTAG Test mode select pin.
JTAG test clock input pin.
JTAG test data input pin.
JTAG test data output pin.
TDO
O
T1CK
T2CK
T3CK
T4CK
T5CK
T6CK
T7CK
T8CK
T9CK
I
I
I
I
I
I
I
I
I
ST
ST
ST
ST
ST
ST
ST
ST
ST
Timer1 external clock input.
Timer2 external clock input.
Timer3 external clock input.
Timer4 external clock input.
Timer5 external clock input.
Timer6 external clock input.
Timer7 external clock input.
Timer8 external clock input.
Timer9 external clock input.
I
O
I
O
I
O
I
O
ST
—
ST
—
ST
—
ST
—
UART1 clear to send.
UART1 ready to send.
UART1 receive.
U1CTS
U1RTS
U1RX
UART1 transmit.
U1TX
UART2 clear to send.
UART2 ready to send.
UART2 receive.
U2CTS
U2RTS
U2RX
UART2 transmit.
U2TX
VDD
P
P
P
I
—
—
—
Positive supply for peripheral logic and I/O pins.
CPU logic filter capacitor connection.
VCAP/VDDCORE
VSS
Ground reference for logic and I/O pins.
VREF+
Analog Analog voltage reference (high) input.
Analog Analog voltage reference (low) input.
VREF-
I
Legend: CMOS = CMOS compatible input or output
Analog = Analog input
O = Output
P = Power
I = Input
ST = Schmitt Trigger input with CMOS levels
DS70592A-page 18
Preliminary
© 2009 Microchip Technology Inc.
PIC24HJXXXGPX06A/X08A/X10A
2.2
Decoupling Capacitors
2.0
GUIDELINES FOR GETTING
STARTED WITH 16-BIT
MICROCONTROLLERS
The use of decoupling capacitors on every pair of
power supply pins, such as VDD, VSS, AVDD and
AVSS is required.
Note:
This data sheet summarizes the features
of the PIC24HJXXXGPX06A/X08A/X10A
family of devices. It is not intended to be a
comprehensive reference source. To
complement the information in this data
sheet, refer to the “PIC24H Family
Reference Manual”, which is available
Consider the following criteria when using decoupling
capacitors:
• Value and type of capacitor: Recommendation
of 0.1 µF (100 nF), 10-20V. This capacitor should
be a low-ESR and have resonance frequency in
the range of 20 MHz and higher. It is
recommended that ceramic capacitors be used.
from
the
Microchip
website
(www.microchip.com).
• Placement on the printed circuit board: The
decoupling capacitors should be placed as close
to the pins as possible. It is recommended to
place the capacitors on the same side of the
board as the device. If space is constricted, the
capacitor can be placed on another layer on the
PCB using a via; however, ensure that the trace
length from the pin to the capacitor is within
one-quarter inch (6 mm) in length.
2.1
Basic Connection Requirements
Getting
started
with
the
PIC24HJXXXGPX06A/X08A/X10A family of 16-bit
Microcontrollers (MCUs) requires attention to a minimal
set of device pin connections before proceeding with
development. The following is a list of pin names, which
must always be connected:
• Handling high frequency noise: If the board is
experiencing high frequency noise, upward of
tens of MHz, add a second ceramic-type capacitor
in parallel to the above described decoupling
capacitor. The value of the second capacitor can
be in the range of 0.01 µF to 0.001 µF. Place this
second capacitor next to the primary decoupling
capacitor. In high-speed circuit designs, consider
implementing a decade pair of capacitances as
close to the power and ground pins as possible.
For example, 0.1 µF in parallel with 0.001 µF.
• All VDD and VSS pins
(see Section 2.2 “Decoupling Capacitors”)
• All AVDD and AVSS pins (regardless if ADC module
is not used)
(see Section 2.2 “Decoupling Capacitors”)
• VCAP/VDDCORE
(see Section 2.3 “Capacitor on Internal Voltage
Regulator (VCAP/VDDCORE)”)
• MCLR pin
(see Section 2.4 “Master Clear (MCLR) Pin”)
• Maximizing performance: On the board layout
from the power supply circuit, run the power and
return traces to the decoupling capacitors first,
and then to the device pins. This ensures that the
decoupling capacitors are first in the power chain.
Equally important is to keep the trace length
between the capacitor and the power pins to a
minimum thereby reducing PCB track inductance.
• PGECx/PGEDx pins used for In-Circuit Serial
Programming™ (ICSP™) and debugging purposes
(see Section 2.5 “ICSP Pins”)
• OSC1 and OSC2 pins when external oscillator
source is used
(see Section 2.6 “External Oscillator Pins”)
Additionally, the following pins may be required:
• VREF+/VREF- pins used when external voltage
reference for ADC module is implemented
Note:
The AVDD and AVSS pins must be
connected independent of the ADC
voltage reference source.
© 2009 Microchip Technology Inc.
Preliminary
DS70592A-page 19
PIC24HJXXXGPX06A/X08A/X10A
FIGURE 2-1:
RECOMMENDED
MINIMUM CONNECTION
2.4
Master Clear (MCLR) Pin
The MCLR pin provides for two specific device
functions:
0.1 µF
Ceramic
• Device Reset
VDD
• Device programming and debugging
During device programming and debugging, the
resistance and capacitance that can be added to the
pin must be considered. Device programmers and
debuggers drive the MCLR pin. Consequently,
specific voltage levels (VIH and VIL) and fast signal
transitions must not be adversely affected. Therefore,
specific values of R and C will need to be adjusted
based on the application and PCB requirements.
R
R1
MCLR
C
PIC24H
VDD
VSS
VDD
For example, as shown in Figure 2-2, it is
recommended that the capacitor C, be isolated from
the MCLR pin during programming and debugging
operations.
VSS
0.1 µF
Ceramic
0.1 µF
Ceramic
0.1 µF
0.1 µF
Ceramic
Ceramic
Place the components shown in Figure 2-2 within
one-quarter inch (6 mm) from the MCLR pin.
10 Ω
FIGURE 2-2:
EXAMPLE OF MCLR PIN
CONNECTIONS
2.2.1
TANK CAPACITORS
On boards with power traces running longer than six
inches in length, it is suggested to use a tank capacitor
for integrated circuits including MCUs to supply a local
power source. The value of the tank capacitor should
be determined based on the trace resistance that con-
nects the power supply source to the device, and the
maximum current drawn by the device in the applica-
tion. In other words, select the tank capacitor so that it
meets the acceptable voltage sag at the device. Typical
values range from 4.7 µF to 47 µF.
VDD
R
R1
MCLR
PIC24H
JP
C
2.3
Capacitor on Internal Voltage
Regulator (VCAP/VDDCORE)
Note 1: R ≤ 10 kΩ is recommended. A suggested
starting value is 10 kΩ. Ensure that the
MCLR pin VIH and VIL specifications are met.
A low-ESR (< 5 Ohms) capacitor is required on the
VCAP/VDDCORE pin, which is used to stabilize the
voltage regulator output voltage. The VCAP/VDDCORE
pin must not be connected to VDD, and must have a
capacitor between 4.7 µF and 10 µF, 16V connected to
ground. The type can be ceramic or tantalum. Refer to
Section 24.0 “Electrical Characteristics” for
additional information.
2: R1 ≤ 470Ω will limit any current flowing into
MCLR from the external capacitor C, in the
event of MCLR pin breakdown, due to
Electrostatic Discharge (ESD) or Electrical
Overstress (EOS). Ensure that the MCLR pin
VIH and VIL specifications are met.
The placement of this capacitor should be close to the
VCAP/VDDCORE. It is recommended that the trace
length not exceed one-quarter inch (6 mm). Refer to
Section 21.2 “On-Chip Voltage Regulator” for
details.
DS70592A-page 20
Preliminary
© 2009 Microchip Technology Inc.
PIC24HJXXXGPX06A/X08A/X10A
2.5
ICSP Pins
2.6
External Oscillator Pins
The PGECx and PGEDx pins are used for In-Circuit
Serial Programming™ (ICSP™) and debugging pur-
poses. It is recommended to keep the trace length
between the ICSP connector and the ICSP pins on the
device as short as possible. If the ICSP connector is
expected to experience an ESD event, a series resistor
is recommended, with the value in the range of a few
tens of Ohms, not to exceed 100 Ohms.
Many MCUs have options for at least two oscillators: a
high-frequency primary oscillator and a low-frequency
secondary oscillator (refer to Section 9.0 “Oscillator
Configuration” for details).
The oscillator circuit should be placed on the same
side of the board as the device. Also, place the
oscillator circuit close to the respective oscillator pins,
not exceeding one-half inch (12 mm) distance
between them. The load capacitors should be placed
next to the oscillator itself, on the same side of the
board. Use a grounded copper pour around the
oscillator circuit to isolate them from surrounding
circuits. The grounded copper pour should be routed
directly to the MCU ground. Do not run any signal
traces or power traces inside the ground pour. Also, if
using a two-sided board, avoid any traces on the
other side of the board where the crystal is placed. A
suggested layout is shown in Figure 2-3.
Pull-up resistors, series diodes, and capacitors on the
PGECx and PGEDx pins are not recommended as they
will interfere with the programmer/debugger communi-
cations to the device. If such discrete components are
an application requirement, they should be removed
from the circuit during programming and debugging.
Alternatively, refer to the AC/DC characteristics and
timing requirements information in the respective
device Flash programming specification for information
on capacitive loading limits and pin input voltage high
(VIH) and input low (VIL) requirements.
FIGURE 2-3:
SUGGESTED PLACEMENT
OF THE OSCILLATOR
CIRCUIT
Ensure that the “Communication Channel Select” (i.e.,
PGECx/PGEDx pins) programmed into the device
matches the physical connections for the ICSP to
MPLAB® ICD 2, MPLAB ICD 3 or MPLAB REAL ICE™.
For more information on ICD 2, ICD 3 and REAL ICE
connection requirements, refer to the following
documents that are available on the Microchip website.
• “MPLAB® ICD 2 In-Circuit Debugger User’s
Guide” DS51331
• “Using MPLAB® ICD 2” (poster) DS51265
• “MPLAB® ICD 2 Design Advisory” DS51566
• “Using MPLAB® ICD 3 In-Circuit Debugger”
Main Oscillator
Guard Ring
13
14
15
16
17
18
19
20
Guard Trace
Secondary
Oscillator
(poster) DS51765
• “MPLAB® ICD 3 Design Advisory” DS51764
• “MPLAB® REAL ICE™ In-Circuit Emulator User’s
Guide” DS51616
• “Using MPLAB® REAL ICE™” (poster) DS51749
© 2009 Microchip Technology Inc.
Preliminary
DS70592A-page 21
PIC24HJXXXGPX06A/X08A/X10A
2.7
Oscillator Value Conditions on
Device Start-up
If the PLL of the target device is enabled and
configured for the device start-up oscillator, the
maximum oscillator source frequency must be limited
to 4 MHz < FIN < 8 MHz to comply with device PLL
start-up conditions. This means that if the external
oscillator frequency is outside this range, the
application must start-up in the FRC mode first. The
default PLL settings after a POR with an oscillator
frequency outside this range will violate the device
operating speed.
Once the device powers up, the application firmware
can initialize the PLL SFRs, CLKDIV and PLLDBF to a
suitable value, and then perform a clock switch to the
Oscillator + PLL clock source. Note that clock switching
must be enabled in the device Configuration word.
2.8
Configuration of Analog and
Digital Pins During ICSP
Operations
If MPLAB ICD 2, ICD 3 or REAL ICE is selected as a
debugger, it automatically initializes all of the A/D input
pins (ANx) as “digital” pins, by setting all bits in the
AD1PCFGL register.
The bits in this register that correspond to the A/D pins
that are initialized by MPLAB ICD 2, ICD 3, or REAL
ICE, must not be cleared by the user application
firmware; otherwise, communication errors will result
between the debugger and the device.
If your application needs to use certain A/D pins as
analog input pins during the debug session, the user
application must clear the corresponding bits in the
AD1PCFGL register during initialization of the ADC
module.
When MPLAB ICD 2, ICD 3 or REAL ICE is used as a
programmer, the user application firmware must
correctly configure the AD1PCFGL register. Automatic
initialization of this register is only done during
debugger operation. Failure to correctly configure the
register(s) will result in all A/D pins being recognized as
analog input pins, resulting in the port value being read
as a logic ‘0’, which may affect user application
functionality.
2.9
Unused I/Os
Unused I/O pins should be configured as outputs and
driven to a logic-low state.
Alternatively, connect a 1k to 10k resistor to VSS on
unused pins and drive the output to logic low.
DS70592A-page 22
Preliminary
© 2009 Microchip Technology Inc.
PIC24HJXXXGPX06A/X08A/X10A
3.1
Data Addressing Overview
3.0
CPU
The data space can be linearly addressed as 32K words
or 64 Kbytes using an Address Generation Unit (AGU).
The upper 32 Kbytes of the data space memory map can
optionally be mapped into program space at any 16K pro-
gram word boundary defined by the 8-bit Program Space
Visibility Page (PSVPAG) register. The program to data
space mapping feature lets any instruction access pro-
gram space as if it were data space.
Note:
This data sheet summarizes the features
of the PIC24HJXXXGPX06A/X08A/X10A
family of devices. However, it is not
intended to be a comprehensive reference
source. To complement the information in
this data sheet, refer to the “PIC24H Fam-
ily Reference Manual”, Section 2. “CPU”
(DS70245), which is available from the
Microchip website (www.microchip.com).
The data space also includes 2 Kbytes of DMA RAM,
which is primarily used for DMA data transfers, but may
be used as general purpose RAM.
The PIC24HJXXXGPX06A/X08A/X10A CPU module
has a 16-bit (data) modified Harvard architecture with an
enhanced instruction set and addressing modes. The
CPU has a 24-bit instruction word with a variable length
opcode field. The Program Counter (PC) is 23 bits wide
and addresses up to 4M x 24 bits of user program
memory space. The actual amount of program memory
implemented varies by device. A single-cycle instruction
prefetch mechanism is used to help maintain throughput
and provides predictable execution. All instructions
execute in a single cycle, with the exception of
instructions that change the program flow, the double
word move (MOV.D) instruction and the table instructions.
Overhead-free, single-cycle program loop constructs are
supported using the REPEAT instruction, which is
interruptible at any point.
3.2
Special MCU Features
The PIC24HJXXXGPX06A/X08A/X10A features
a
17-bit by 17-bit, single-cycle multiplier. The multiplier
can perform signed, unsigned and mixed-sign
multiplication. Using a 17-bit by 17-bit multiplier for
16-bit by 16-bit multiplication makes mixed-sign
multiplication possible.
The PIC24HJXXXGPX06A/X08A/X10A supports 16/16
and 32/16 integer divide operations. All divide
instructions are iterative operations. They must be
executed within a REPEAT loop, resulting in a total
execution time of 19 instruction cycles. The divide
operation can be interrupted during any of those
19 cycles without loss of data.
The PIC24HJXXXGPX06A/X08A/X10A devices have
sixteen, 16-bit working registers in the programmer’s
model. Each of the working registers can serve as a data,
address or address offset register. The 16th working
register (W15) operates as a software Stack Pointer (SP)
for interrupts and calls.
A multi-bit data shifter is used to perform up to a 16-bit,
left or right shift in a single cycle.
The PIC24HJXXXGPX06A/X08A/X10A instruction set
includes many addressing modes and is designed for
optimum C compiler efficiency. For most instructions,
the PIC24HJXXXGPX06A/X08A/X10A is capable of
executing a data (or program data) memory read, a
working register (data) read, a data memory write and
a program (instruction) memory read per instruction
cycle. As a result, three parameter instructions can be
supported, allowing A + B = C operations to be
executed in a single cycle.
A block diagram of the CPU is shown in Figure 3-1,
and
the
programmer’s
model
for
the
PIC24HJXXXGPX06A/X08A/X10A is shown in
Figure 3-2.
© 2009 Microchip Technology Inc.
Preliminary
DS70592A-page 23
PIC24HJXXXGPX06A/X08A/X10A
FIGURE 3-1:
PIC24HJXXXGPX06A/X08A/X10A CPU CORE BLOCK DIAGRAM
PSV and Table
Data Access
Control Block
X Data Bus
Interrupt
Controller
16
16
16
8
Data Latch
X RAM
DMA
RAM
23
16
PCH PCL
Program Counter
PCU
23
Address
Latch
Loop
Control
Logic
Stack
Control
Logic
23
16
DMA
Controller
Address Generator Units
Address Latch
Program Memory
Data Latch
EA MUX
ROM Latch
24
16
16
Instruction
Decode and
Control
Instruction Reg
16
17 x 17
Multiplier
Control Signals
to Various Blocks
16 x 16
W Register Array
Divide Support
16
16-bit ALU
16
To Peripheral Modules
DS70592A-page 24
Preliminary
© 2009 Microchip Technology Inc.
PIC24HJXXXGPX06A/X08A/X10A
FIGURE 3-2:
PIC24HJXXXGPX06A/X08A/X10A PROGRAMMER’S MODEL
D15
D0
W0/WREG
W1
PUSH.SShadow
DOShadow
W2
W3
Legend
W4
W5
W6
W7
Working Registers
W8
W9
W10
W11
W12
W13
W14/Frame Pointer
W15/Stack Pointer
SPLIM
Stack Pointer Limit Register
Program Counter
PC22
PC0
0
0
7
TBLPAG
Data Table Page Address
7
0
PSVPAG
Program Space Visibility Page Address
15
0
0
RCOUNT
REPEATLoop Counter
15
Core Configuration Register
CORCON
—
—
—
—
—
—
—
DC
RA
N
Z
C
IPL2 IPL1 IPL0
OV
STATUS Register
SRH
SRL
3.3
CPU Control Registers
© 2009 Microchip Technology Inc.
Preliminary
DS70592A-page 25
PIC24HJXXXGPX06A/X08A/X10A
REGISTER 3-1:
SR: CPU STATUS REGISTER
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
R/W-0
DC
bit 15
bit 8
R/W-0(1)
R/W-0(2)
IPL<2:0>(2)
R/W-0(2)
R-0
RA
R/W-0
N
R/W-0
OV
R/W-0
Z
R/W-0
C
bit 7
bit 0
Legend:
C = Clear only bit
S = Set only bit
‘1’ = Bit is set
R = Readable bit
W = Writable bit
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
-n = Value at POR
x = Bit is unknown
bit 15-9
bit 8
Unimplemented: Read as ‘0’
DC: MCU ALU Half Carry/Borrow bit
1= A carry-out from the 4th low-order bit (for byte sized data) or 8th low-order bit (for word sized data)
of the result occurred
0= No carry-out from the 4th low-order bit (for byte sized data) or 8th low-order bit (for word sized
data) of the result occurred
bit 7-5
IPL<2:0>: CPU Interrupt Priority Level Status bits(2)
111= CPU Interrupt Priority Level is 7 (15), user interrupts disabled
110= CPU Interrupt Priority Level is 6 (14)
101= CPU Interrupt Priority Level is 5 (13)
100= CPU Interrupt Priority Level is 4 (12)
011= CPU Interrupt Priority Level is 3 (11)
010= CPU Interrupt Priority Level is 2 (10)
001= CPU Interrupt Priority Level is 1 (9)
000= CPU Interrupt Priority Level is 0 (8)
bit 4
bit 3
bit 2
RA: REPEATLoop Active bit
1= REPEATloop in progress
0= REPEATloop not in progress
N: MCU ALU Negative bit
1= Result was negative
0= Result was non-negative (zero or positive)
OV: MCU ALU Overflow bit
This bit is used for signed arithmetic (2’s complement). It indicates an overflow of the magnitude which
causes the sign bit to change state.
1= Overflow occurred for signed arithmetic (in this arithmetic operation)
0= No overflow occurred
bit 1
bit 0
Z: MCU ALU Zero bit
1= An operation which affects the Z bit has set it at some time in the past
0= The most recent operation which affects the Z bit has cleared it (i.e., a non-zero result)
C: MCU ALU Carry/Borrow bit
1= A carry-out from the Most Significant bit (MSb) of the result occurred
0= No carry-out from the Most Significant bit of the result occurred
Note 1: The IPL<2:0> bits are concatenated with the IPL<3> bit (CORCON<3>) to form the CPU Interrupt Priority
Level. The value in parentheses indicates the IPL if IPL<3> = 1. User interrupts are disabled when
IPL<3> = 1.
2: The IPL<2:0> Status bits are read only when NSTDIS = 1(INTCON1<15>).
DS70592A-page 26
Preliminary
© 2009 Microchip Technology Inc.
PIC24HJXXXGPX06A/X08A/X10A
REGISTER 3-2:
CORCON: CORE CONTROL REGISTER
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
bit 15
bit 8
bit 0
U-0
—
U-0
—
U-0
—
U-0
—
R/C-0
IPL3(1)
R/W-0
PSV
U-0
—
U-0
—
bit 7
Legend:
C = Clear only bit
W = Writable bit
‘x = Bit is unknown
R = Readable bit
0’ = Bit is cleared
-n = Value at POR
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
bit 15-4
bit 3
Unimplemented: Read as ‘0’
IPL3: CPU Interrupt Priority Level Status bit 3(1)
1= CPU interrupt priority level is greater than 7
0= CPU interrupt priority level is 7 or less
bit 2
PSV: Program Space Visibility in Data Space Enable bit
1= Program space visible in data space
0= Program space not visible in data space
bit 1-0
Unimplemented: Read as ‘0’
Note 1: The IPL3 bit is concatenated with the IPL<2:0> bits (SR<7:5>) to form the CPU interrupt priority level.
© 2009 Microchip Technology Inc.
Preliminary
DS70592A-page 27
PIC24HJXXXGPX06A/X08A/X10A
3.4.2
DIVIDER
3.4
Arithmetic Logic Unit (ALU)
The divide block supports 32-bit/16-bit and 16-bit/16-bit
signed and unsigned integer divide operations with the
following data sizes:
The PIC24HJXXXGPX06A/X08A/X10A ALU is 16 bits
wide and is capable of addition, subtraction, bit shifts
and logic operations. Unless otherwise mentioned,
arithmetic operations are 2’s complement in nature.
Depending on the operation, the ALU may affect the
values of the Carry (C), Zero (Z), Negative (N),
Overflow (OV) and Digit Carry (DC) Status bits in the
SR register. The C and DC Status bits operate as
Borrow and Digit Borrow bits, respectively, for
subtraction operations.
1. 32-bit signed/16-bit signed divide
2. 32-bit unsigned/16-bit unsigned divide
3. 16-bit signed/16-bit signed divide
4. 16-bit unsigned/16-bit unsigned divide
The quotient for all divide instructions ends up in W0
and the remainder in W1. Sixteen-bit signed and
unsigned DIV instructions can specify any W register
for both the 16-bit divisor (Wn) and any W register
(aligned) pair (W(m + 1):Wm) for the 32-bit dividend.
The divide algorithm takes one cycle per bit of divisor,
so both 32-bit/16-bit and 16-bit/16-bit instructions take
the same number of cycles to execute.
The ALU can perform 8-bit or 16-bit operations,
depending on the mode of the instruction that is used.
Data for the ALU operation can come from the W reg-
ister array, or data memory, depending on the address-
ing mode of the instruction. Likewise, output data from
the ALU can be written to the W register array or a data
memory location.
3.4.3
MULTI-BIT DATA SHIFTER
Refer to the “dsPIC30F/33F Programmer’s Reference
Manual” (DS70157) for information on the SR bits
affected by each instruction.
The multi-bit data shifter is capable of performing up to
16-bit arithmetic or logic right shifts, or up to 16-bit left
shifts in a single cycle. The source can be either a
working register or a memory location.
The
PIC24HJXXXGPX06A/X08A/X10A
CPU
incorporates hardware support for both multiplication
and division. This includes a dedicated hardware
multiplier and support hardware for 16-bit divisor
division.
The shifter requires a signed binary value to determine
both the magnitude (number of bits) and direction of the
shift operation. A positive value shifts the operand right.
A negative value shifts the operand left. A value of ‘0’
does not modify the operand.
3.4.1
MULTIPLIER
Using the high-speed 17-bit x 17-bit multiplier, the ALU
supports unsigned, signed or mixed-sign operation in
several multiplication modes:
1. 16-bit x 16-bit signed
2. 16-bit x 16-bit unsigned
3. 16-bit signed x 5-bit (literal) unsigned
4. 16-bit unsigned x 16-bit unsigned
5. 16-bit unsigned x 5-bit (literal) unsigned
6. 16-bit unsigned x 16-bit signed
7. 8-bit unsigned x 8-bit unsigned
DS70592A-page 28
Preliminary
© 2009 Microchip Technology Inc.
PIC24HJXXXGPX06A/X08A/X10A
4.1
Program Address Space
4.0
MEMORY ORGANIZATION
The program address memory space of the
PIC24HJXXXGPX06A/X08A/X10A devices is 4M instruc-
tions. The space is addressable by a 24-bit value derived
from either the 23-bit Program Counter (PC) during pro-
gram execution, or from table operation or data space
remapping as described in Section 4.4 “Interfacing Pro-
gram and Data Memory Spaces”.
Note:
This data sheet summarizes the features
of the PIC24HJXXXGPX06A/X08A/X10A
family of devices. However, it is not
intended to be a comprehensive reference
source. To complement the information in
this data sheet, refer to the “PIC24H Fam-
ily Reference Manual”, Section 3. “Data
Memory” (DS70237), which is available
from the Microchip website (www.micro-
chip.com).
User access to the program memory space is restricted
to the lower half of the address range (0x000000 to
0x7FFFFF). The exception is the use of TBLRD/TBLWT
operations, which use TBLPAG<7> to permit access to
the Configuration bits and Device ID sections of the
configuration memory space.
The PIC24HJXXXGPX06A/X08A/X10A architecture
features separate program and data memory spaces
and buses. This architecture also allows the direct
access of program memory from the data space during
code execution.
Memory maps for the PIC24HJXXXGPX06A/X08A/
X10A family of devices are shown in Figure 4-1.
FIGURE 4-1:
PROGRAM MEMORY MAP FOR PIC24HJXXXGPX06A/X08A/X10A FAMILY DEVICES
PIC24HJ64XXXXXA
PIC24HJ128XXXXXA
PIC24HJ256XXXXXA
0x000000
0x000002
0x000004
GOTOInstruction
Reset Address
GOTOInstruction
Reset Address
GOTOInstruction
Reset Address
Interrupt Vector Table
Reserved
Interrupt Vector Table
Reserved
Interrupt Vector Table
Reserved
0x0000FE
0x000100
0x000104
0x0001FE
0x000200
Alternate Vector Table
Alternate Vector Table
Alternate Vector Table
User Program
Flash Memory
(22K instructions)
User Program
Flash Memory
(44K instructions)
User Program
Flash Memory
(88K instructions)
0x00ABFE
0x00AC00
0x0157FE
0x015800
Unimplemented
Unimplemented
(Read ‘0’s)
0x02ABFE
0x02AC00
(Read ‘0’s)
Unimplemented
(Read ‘0’s)
0x7FFFFE
0x800000
Reserved
Reserved
Reserved
0xF7FFFE
0xF80000
Device Configuration
Registers
Device Configuration
Registers
Device Configuration
Registers
0xF80017
0xF80010
Reserved
DEVID (2)
Reserved
Reserved
DEVID (2)
0xFEFFFE
0xFF0000
DEVID (2)
0xFFFFFE
© 2009 Microchip Technology Inc.
Preliminary
DS70592A-page 29
PIC24HJXXXGPX06A/X08A/X10A
4.1.1
PROGRAM MEMORY
ORGANIZATION
4.1.2
INTERRUPT AND TRAP VECTORS
All PIC24HJXXXGPX06A/X08A/X10A devices reserve
the addresses between 0x00000 and 0x000200 for
hard-coded program execution vectors. A hardware
Reset vector is provided to redirect code execution
from the default value of the PC on device Reset to the
actual start of code. A GOTOinstruction is programmed
by the user at 0x000000, with the actual address for the
start of code at 0x000002.
The program memory space is organized in word-
addressable blocks. Although it is treated as 24 bits
wide, it is more appropriate to think of each address of
the program memory as a lower and upper word, with
the upper byte of the upper word being unimplemented.
The lower word always has an even address, while the
upper word has an odd address (Figure 4-2).
PIC24HJXXXGPX06A/X08A/X10A devices also have
two interrupt vector tables, located from 0x000004 to
0x0000FF and 0x000100 to 0x0001FF. These vector
tables allow each of the many device interrupt sources
to be handled by separate Interrupt Service Routines
(ISRs). A more detailed discussion of the interrupt vec-
tor tables is provided in Section 7.1 “Interrupt Vector
Table”.
Program memory addresses are always word-aligned
on the lower word, and addresses are incremented or
decremented by two during code execution. This
arrangement also provides compatibility with data
memory space addressing and makes it possible to
access data in the program memory space.
FIGURE 4-2:
PROGRAM MEMORY ORGANIZATION
least significant word
PC Address
most significant word
23
msw
Address
(lsw Address)
16
8
0
0x000001
0x000003
0x000005
0x000007
0x000000
0x000002
0x000004
0x000006
00000000
00000000
00000000
00000000
Program Memory
‘Phantom’ Byte
(read as ‘0’)
Instruction Width
DS70592A-page 30
Preliminary
© 2009 Microchip Technology Inc.
PIC24HJXXXGPX06A/X08A/X10A
All word accesses must be aligned to an even address.
4.2
Data Address Space
Misaligned word data fetches are not supported, so
care must be taken when mixing byte and word opera-
tions, or translating from 8-bit MCU code. If a mis-
aligned read or write is attempted, an address error
trap is generated. If the error occurred on a read, the
instruction underway is completed; if it occurred on a
write, the instruction will be executed but the write does
not occur. In either case, a trap is then executed, allow-
ing the system and/or user to examine the machine
state prior to execution of the address Fault.
The PIC24HJXXXGPX06A/X08A/X10A CPU has a
separate 16-bit wide data memory space. The data
space is accessed using separate Address Generation
Units (AGUs) for read and write operations. Data mem-
ory maps of devices with different RAM sizes are
shown in Figure 4-3 and Figure 4-4.
All Effective Addresses (EAs) in the data memory space
are 16 bits wide and point to bytes within the data space.
This arrangement gives a data space address range of
64 Kbytes or 32K words. The lower half of the data
memory space (that is, when EA<15> = 0) is used for
implemented memory addresses, while the upper half
(EA<15> = 1) is reserved for the Program Space
Visibility area (see Section 4.4.3 “Reading Data from
Program Memory Using Program Space Visibility”).
All byte loads into any W register are loaded into the
Least Significant Byte. The Most Significant Byte
(MSB) is not modified.
A sign-extend instruction (SE) is provided to allow
users to translate 8-bit signed data to 16-bit signed
values. Alternatively, for 16-bit unsigned data, users
can clear the Most Significant Byte of any W register by
executing a zero-extend (ZE) instruction on the
appropriate address.
PIC24HJXXXGPX06A/X08A/X10A devices implement
up to 16 Kbytes of data memory. Should an EA point to
a location outside of this area, an all-zero word or byte
will be returned.
4.2.3
SFR SPACE
4.2.1
DATA SPACE WIDTH
The first 2 Kbytes of the Near Data Space, from 0x0000
to 0x07FF, is primarily occupied by Special Function
Registers (SFRs). These are used by the
PIC24HJXXXGPX06A/X08A/X10A core and peripheral
modules for controlling the operation of the device.
The data memory space is organized in byte address-
able, 16-bit wide blocks. Data is aligned in data
memory and registers as 16-bit words, but all data
space EAs resolve to bytes. The Least Significant
Bytes of each word have even addresses, while the
Most Significant Bytes have odd addresses.
SFRs are distributed among the modules that they
control, and are generally grouped together by module.
Much of the SFR space contains unused addresses;
these are read as ‘0’. A complete listing of implemented
SFRs, including their addresses, is shown in Table 4-1
through Table 4-33.
4.2.2
DATA MEMORY ORGANIZATION
AND ALIGNMENT
To maintain backward compatibility with PIC® MCU
devices and improve data space memory usage
efficiency, the PIC24HJXXXGPX06A/X08A/X10A
instruction set supports both word and byte operations.
As a consequence of byte accessibility, all effective
address calculations are internally scaled to step
through word-aligned memory. For example, the core
recognizes that Post-Modified Register Indirect
Addressing mode [Ws++] will result in a value of Ws +
1 for byte operations and Ws + 2 for word operations.
Note:
The actual set of peripheral features and
interrupts varies by the device. Please
refer to the corresponding device tables
and pinout diagrams for device-specific
information.
4.2.4
NEAR DATA SPACE
The 8-Kbyte area between 0x0000 and 0x1FFF is
referred to as the Near Data Space. Locations in this
space are directly addressable via a 13-bit absolute
address field within all memory direct instructions.
Additionally, the whole data space is addressable using
MOV instructions, which support Memory Direct
Addressing mode with a 16-bit address field, or by
using Indirect Addressing mode using a working
register as an Address Pointer.
Data byte reads will read the complete word that
contains the byte, using the Least Significant bit (LSb)
of any EA to determine which byte to select. The
selected byte is placed onto the Least Significant Byte
(LSB) of the data path. That is, data memory and reg-
isters are organized as two parallel byte-wide entities
with shared (word) address decode but separate write
lines. Data byte writes only write to the corresponding
side of the array or register which matches the byte
address.
© 2009 Microchip Technology Inc.
Preliminary
DS70592A-page 31
PIC24HJXXXGPX06A/X08A/X10A
FIGURE 4-3:
DATA MEMORY MAP FOR PIC24HJXXXGPX06A/X08A/X10A DEVICES WITH 8 KBS
RAM
MSB
Address
LSB
Address
16 bits
MSB
LSB
0x0000
0x0001
2 Kbyte
SFR Space
SFR Space
0x07FE
0x0800
0x07FF
0x0801
8 Kbyte
Near
Data
Space
X Data RAM (X)
8 Kbyte
SRAM Space
0x1FFF
0x2001
0x1FFE
0x2000
DMA RAM
0x27FF
0x2801
0x27FE
0x2800
0x8001
0x8000
X Data
Optionally
Mapped
Unimplemented (X)
into Program
Memory
0xFFFF
0xFFFE
DS70592A-page 32
Preliminary
© 2009 Microchip Technology Inc.
PIC24HJXXXGPX06A/X08A/X10A
FIGURE 4-4:
DATA MEMORY MAP FOR PIC24HJXXXGPX06A/X08A/X10A DEVICES WITH 16 KBS
RAM
LSB
Address
MSB
Address
16 bits
MSB
LSB
0x0000
0x0001
2 Kbyte
SFR Space
SFR Space
8 Kbyte
Near
Data
0x07FE
0x0800
0x07FF
0x0801
Space
0x1FFF
0x1FFE
X Data RAM (X)
16 Kbyte
SRAM Space
0x3FFF
0x4001
0x3FFE
0x4000
DMA RAM
0x47FF
0x4801
0x47FE
0x4800
0x8001
0x8000
X Data
Unimplemented (X)
Optionally
Mapped
into Program
Memory
0xFFFF
0xFFFE
transferred from various peripherals using DMA. The
DMA RAM can be accessed by the DMA controller
without having to steal cycles from the CPU.
4.2.5
Every
DMA RAM
PIC24HJXXXGPX06A/X08A/X10A
device
contains 2 Kbytes of dual ported DMA RAM located at
the end of data space. Memory locations in the DMA
RAM space are accessible simultaneously by the CPU
and the DMA controller module. DMA RAM is utilized by
the DMA controller to store data to be transferred to
various peripherals using DMA, as well as data
When the CPU and the DMA controller attempt to
concurrently write to the same DMA RAM location, the
hardware ensures that the CPU is given precedence in
accessing the DMA RAM location. Therefore, the DMA
RAM provides a reliable means of transferring DMA
data without ever having to stall the CPU.
Note:
DMA RAM can be used for general
purpose data storage if the DMA function
is not required in an application.
© 2009 Microchip Technology Inc.
Preliminary
DS70592A-page 33
TABLE 4-1:
CPU CORE REGISTERS MAP
SFR
Addr
All
Resets
SFR Name
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
WREG0
WREG1
WREG2
WREG3
WREG4
WREG5
WREG6
WREG7
WREG8
WREG9
WREG10
WREG11
WREG12
WREG13
WREG14
WREG15
SPLIM
0000
0002
0004
0006
0008
000A
000C
000E
0010
0012
0014
0016
0018
001A
001C
001E
0020
002E
0030
0032
0034
0036
0042
0044
0052
0750
Working Register 0
Working Register 1
Working Register 2
Working Register 3
Working Register 4
Working Register 5
Working Register 6
Working Register 7
Working Register 8
Working Register 9
Working Register 10
Working Register 11
Working Register 12
Working Register 13
Working Register 14
Working Register 15
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0800
xxxx
0000
0000
0000
0000
xxxx
0000
0000
xxxx
0000
Stack Pointer Limit Register
Program Counter Low Word Register
PCL
PCH
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Program Counter High Byte Register
Table Page Address Pointer Register
TBLPAG
PSVPAG
RCOUNT
SR
Program Memory Visibility Page Address Pointer Register
Repeat Loop Counter Register
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
DC
—
IPL<2:0>
RA
—
N
OV
Z
C
CORCON
DISICNT
BSRAM
—
—
—
—
IPL3
PSV
—
—
Disable Interrupts Counter Register
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
IW_BSR IR_BSR RL_BSR
IW_SSR IR_SSR RL_SSR
SSRAM
0752
—
0000
Legend:
x= unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal for PinHigh devices.
TABLE 4-2:
CHANGE NOTIFICATION REGISTER MAP FOR PIC24HJXXXGPX10A DEVICES
SFR
Name
Addr
SFR
All
Resets
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
CNEN1
CNEN2
CNPU1
CNPU2
Legend:
0060
0062
0068
006A
CN15IE
—
CN14IE
—
CN13IE
—
CN12IE
—
CN11IE
—
CN10IE
—
CN9IE
—
CN8IE
—
CN7IE
CN6IE
CN5IE
CN4IE
CN3IE
CN2IE
CN1IE
CN0IE
0000
0000
0000
CN23IE
CN22IE
CN21IE
CN20IE
CN19IE
CN18IE
CN17IE
CN16IE
CN15PUE CN14PUE CN13PUE CN12PUE CN11PUE CN10PUE CN9PUE CN8PUE CN7PUE CN6PUE CN5PUE CN4PUE CN3PUE CN2PUE CN1PUE CN0PUE
—
—
—
—
—
—
—
—
CN23PUE CN22PUE CN21PUE CN20PUE CN19PUE CN18PUE CN17PUE CN16PUE 0000
x= unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal for PinHigh devices.
TABLE 4-3:
CHANGE NOTIFICATION REGISTER MAP FOR PIC24HJXXXGPX08A DEVICES
SFR
Name
Addr
SFR
All
Resets
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
CNEN1
CNEN2
CNPU1
CNPU2
Legend:
0060
0062
0068
006A
CN15IE
—
CN14IE
—
CN13IE
—
CN12IE
—
CN11IE
—
CN10IE
—
CN9IE
—
CN8IE
—
CN7IE
—
CN6IE
—
CN5IE
CN4IE
CN3IE
CN2IE
CN1IE
CN0IE
0000
0000
0000
CN21IE
CN20IE
CN19IE
CN18IE
CN17IE
CN16IE
CN15PUE CN14PUE CN13PUE CN12PUE CN11PUE CN10PUE CN9PUE CN8PUE CN7PUE CN6PUE CN5PUE CN4PUE CN3PUE CN2PUE CN1PUE CN0PUE
—
—
—
—
—
—
—
—
—
—
CN21PUE CN20PUE CN19PUE CN18PUE CN17PUE CN16PUE 0000
x= unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
TABLE 4-4:
CHANGE NOTIFICATION REGISTER MAP FOR PIC24HJXXXGPX06A DEVICES
SFR
Name
Addr
SFR
All
Resets
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
CNEN1
CNEN2
CNPU1
CNPU2
Legend:
0060
0062
0068
006A
CN15IE
—
CN14IE
—
CN13IE
—
CN12IE
—
CN11IE
—
CN10IE
—
CN9IE
—
CN8IE
—
CN7IE
—
CN6IE
—
CN5IE
CN4IE
CN3IE
—
CN2IE
CN1IE
CN0IE
0000
0000
0000
CN21IE
CN20IE
CN18IE
CN17IE
CN16IE
CN15PUE CN14PUE CN13PUE CN12PUE CN11PUE CN10PUE CN9PUE CN8PUE CN7PUE CN6PUE CN5PUE CN4PUE CN3PUE CN2PUE CN1PUE CN0PUE
CN21PUE CN20PUE
—
—
—
—
—
—
—
—
—
—
—
CN18PUE CN17PUE CN16PUE 0000
x= unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
TABLE 4-5:
INTERRUPT CONTROLLER REGISTER MAP
SFR
Name
SFR
Addr
All
Resets
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
INTCON1 0080 NSTDIS
INTCON2 0082 ALTIVT
DIV0ERR DMACERR MATHERR ADDRERR STKERR OSCFAIL
—
0000
DISI
—
—
INT4EP
DMA0IF
INT1IF
DMA3IF
T9IF
INT3EP
T1IF
CNIF
C1IF
T8IF
—
INT2EP
OC1IF
—
INT1EP INT0EP 0000
IC1IF INT0IF 0000
IFS0
0084
—
DMA1IF
AD1IF
U1TXIF
T5IF
OC8IF
—
U1RXIF
T4IF
OC7IF
—
SPI1IF SPI1EIF
T3IF
T2IF
IC8IF
IC5IF
C2RXIF
C2TXIF
T2IE
IC8IE
IC5IE
C2RXIE
C2TXIE
—
OC2IF
IC7IF
IC2IF
IFS1
0086 U2TXIF U2RXIF
INT2IF
OC4IF OC3IF DMA2IF
AD2IF
MI2C1IF SI2C1IF 0000
SPI2IF SPI2EIF 0000
IFS2
0088
008A
008C
0094
T6IF
—
DMA4IF
—
—
OC6IF OC5IF
IC6IF
C2IF
—
IC4IF
IC3IF
C1RXIF
IFS3
DMA5IF
—
—
—
—
—
INT4IF
C1TXIF
OC2IE
IC7IE
INT3IF
MI2C2IF SI2C2IF
T7IF
—
0000
0000
0000
IFS4
—
—
—
—
DMA7IF
DMA6IF
DMA0IE
INT1IE
DMA3IE
T9IE
U2EIF
OC1IE
—
U1EIF
IC1IE
IEC0
IEC1
IEC2
IEC3
IEC4
IPC0
IPC1
IPC2
IPC3
IPC4
IPC5
IPC6
IPC7
IPC8
IPC9
IPC10
IPC11
IPC12
IPC13
IPC14
IPC15
IPC16
IPC17
—
DMA1IE
AD1IE
U1TXIE
T5IE
OC8IE
—
U1RXIE
T4IE
OC7IE
—
SPI1IE SPI1EIE
T3IE
IC2IE
T1IE
CNIE
C1IE
T8IE
—
INT0IE
0096 U2TXIE U2RXIE
INT2IE
—
OC4IE OC3IE DMA2IE
AD2IE
MI2C1IE SI2C1IE 0000
SPI2IE SPI2EIE 0000
0098
009A
009C
00A4
00A6
00A8
00AA
00AC
00AE
00B0
00B2
00B4
00B6
00B8
00BA
00BC
00BE
00C0
00C2
00C4
00C6
T6IE
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
DMA4IE
OC6IE OC5IE
IC6IE
C2IE
—
IC4IE
IC3IE
C1RXIE
—
—
DMA5IE
—
—
—
—
INT4IE
C1TXIE
INT3IE
MI2C2IE SI2C2IE
T7IE
—
0000
0000
4444
4444
4444
0444
4044
4444
4444
4444
4444
4444
4444
4404
4444
4444
0004
0040
0440
4444
0000
—
—
—
DMA7IE
DMA6IE
U2EIE
U1EIE
INT0IP<2:0>
DMA0IP<2:0>
T3IP<2:0>
U1TXIP<2:0>
SI2C1IP<2:0>
INT1IP<2:0>
DMA2IP<2:0>
T5IP<2:0>
SPI2EIP<2:0>
DMA3IP<2:0>
IC6IP<2:0>
OC8IP<2:0>
T7IP<2:0>
T9IP<2:0>
C2IP<2:0>
—
T1IP<2:0>
T2IP<2:0>
U1RXIP<2:0>
—
—
OC1IP<2:0>
OC2IP<2:0>
SPI1IP<2:0>
DMA1IP<2:0>
—
IC1IP<2:0>
IC2IP<2:0>
SPI1EIP<2:0>
AD1IP<2:0>
MI2C1IP<2:0>
AD2IP<2:0>
OC3IP<2:0>
INT2IP<2:0>
SPI2IP<2:0>
IC3IP<2:0>
OC5IP<2:0>
—
—
—
—
—
—
—
—
—
—
—
—
—
CNIP<2:0>
IC8IP<2:0>
T4IP<2:0>
U2TXIP<2:0>
C1IP<2:0>
IC5IP<2:0>
OC7IP<2:0>
T6IP<2:0>
T8IP<2:0>
C2RXIP<2:0>
—
—
—
—
—
—
—
IC7IP<2:0>
OC4IP<2:0>
U2RXIP<2:0>
C1RXIP<2:0>
IC4IP<2:0>
OC6IP<2:0>
DMA4IP<2:0>
MI2C2IP<2:0>
INT4IP<2:0>
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
SI2C2IP<2:0>
INT3IP<2:0>
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
DMA5IP<2:0>
U1EIP<2:0>
DMA7IP<2:0>
—
—
—
—
—
—
—
U2EIP<2:0>
C1TXIP<2:0>
—
—
—
C2TXIP<2:0>
—
—
—
—
DMA6IP<2:0>
INTTREG 00E0
Legend:
—
—
ILR<3:0>
—
VECNUM<6:0>
x= unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal for PinHigh devices.
TABLE 4-6:
TIMER REGISTER MAP
SFR
Name
Addr
SFR
All
Resets
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
TMR1
PR1
0100
0102
0104
0106
Timer1 Register
Period Register 1
xxxx
FFFF
0000
xxxx
xxxx
xxxx
FFFF
FFFF
0000
0000
xxxx
xxxx
xxxx
FFFF
FFFF
0000
0000
xxxx
xxxx
xxxx
FFFF
FFFF
0000
0000
xxxx
xxxx
xxxx
FFFF
FFFF
0000
0000
T1CON
TMR2
TON
—
TSIDL
—
—
—
—
—
—
TGATE
TCKPS<1:0>
—
TSYNC
TCS
—
Timer2 Register
TMR3HLD 0108
Timer3 Holding Register (for 32-bit timer operations only)
Timer3 Register
TMR3
PR2
010A
010C
010E
0110
0112
0114
Period Register 2
PR3
Period Register 3
T2CON
T3CON
TMR4
TON
TON
—
—
TSIDL
TSIDL
—
—
—
—
—
—
—
—
—
—
—
—
TGATE
TGATE
TCKPS<1:0>
TCKPS<1:0>
T32
—
—
—
TCS
TCS
—
—
Timer4 Register
TMR5HLD 0116
Timer5 Holding Register (for 32-bit operations only)
Timer5 Register
TMR5
PR4
0118
011A
011C
011E
0120
0122
Period Register 4
PR5
Period Register 5
T4CON
T5CON
TMR6
TON
TON
—
—
TSIDL
TSIDL
—
—
—
—
—
—
—
—
—
—
—
—
TGATE
TGATE
TCKPS<1:0>
TCKPS<1:0>
T32
—
—
—
TCS
TCS
—
—
Timer6 Register
TMR7HLD 0124
Timer7 Holding Register (for 32-bit operations only)
Timer7 Register
TMR7
PR6
0126
0128
012A
012C
012E
0130
Period Register 6
PR7
Period Register 7
T6CON
T7CON
TMR8
TON
TON
—
—
TSIDL
TSIDL
—
—
—
—
—
—
—
—
—
—
—
—
TGATE
TGATE
TCKPS<1:0>
TCKPS<1:0>
T32
—
—
—
TCS
TCS
—
—
Timer8 Register
TMR9HLD 0132
Timer9 Holding Register (for 32-bit operations only)
Timer9 Register
TMR9
PR8
0134
0136
0138
013A
013C
Period Register 8
PR9
Period Register 9
T8CON
T9CON
Legend:
TON
TON
—
—
TSIDL
TSIDL
—
—
—
—
—
—
—
—
—
—
—
—
TGATE
TGATE
TCKPS<1:0>
TCKPS<1:0>
T32
—
—
—
TCS
TCS
—
—
x= unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal for PinHigh devices.
TABLE 4-7:
INPUT CAPTURE REGISTER MAP
SFR
Addr
All
Resets
SFR Name
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
IC1BUF
IC1CON
IC2BUF
IC2CON
IC3BUF
IC3CON
IC4BUF
IC4CON
IC5BUF
IC5CON
IC6BUF
IC6CON
IC7BUF
IC7CON
IC8BUF
IC8CON
Legend:
0140
0142
0144
0146
0148
014A
014C
014E
0150
0152
0154
0156
0158
015A
015C
015E
Input 1 Capture Register
ICTMR
Input 2 Capture Register
ICTMR
Input 3 Capture Register
ICTMR
Input 4 Capture Register
ICTMR
Input 5 Capture Register
ICTMR
Input 6 Capture Register
ICTMR
Input 7 Capture Register
ICTMR
Input 8 Capture Register
ICTMR
xxxx
0000
xxxx
0000
xxxx
0000
xxxx
0000
xxxx
0000
xxxx
0000
xxxx
0000
xxxx
0000
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
ICSIDL
ICSIDL
ICSIDL
ICSIDL
ICSIDL
ICSIDL
ICSIDL
ICSIDL
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
ICI<1:0>
ICOV
ICOV
ICOV
ICOV
ICOV
ICOV
ICOV
ICOV
ICBNE
ICBNE
ICBNE
ICBNE
ICBNE
ICBNE
ICBNE
ICBNE
ICM<2:0>
ICM<2:0>
ICM<2:0>
ICM<2:0>
ICM<2:0>
ICM<2:0>
ICM<2:0>
ICM<2:0>
—
ICI<1:0>
ICI<1:0>
ICI<1:0>
ICI<1:0>
ICI<1:0>
ICI<1:0>
ICI<1:0>
—
—
—
—
—
—
x= unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal for PinHigh devices.
TABLE 4-8:
OUTPUT COMPARE REGISTER MAP
SFR
Addr
All
Resets
SFR Name
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
OC1RS
OC1R
0180
0182
0184
0186
0188
018A
018C
018E
0190
0192
0194
0196
0198
019A
019C
019E
01A0
01A2
01A4
01A6
01A8
01AA
01AC
01AE
Output Compare 1 Secondary Register
Output Compare 1 Register
xxxx
xxxx
0000
xxxx
xxxx
0000
xxxx
xxxx
0000
xxxx
xxxx
0000
xxxx
xxxx
0000
xxxx
xxxx
0000
xxxx
xxxx
0000
xxxx
xxxx
0000
OC1CON
OC2RS
OC2R
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
OCSIDL
OCSIDL
OCSIDL
OCSIDL
OCSIDL
OCSIDL
OCSIDL
OCSIDL
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
OCFLT
OCFLT
OCFLT
OCFLT
OCFLT
OCFLT
OCFLT
OCFLT
OCTSEL
OCTSEL
OCTSEL
OCTSEL
OCTSEL
OCTSEL
OCTSEL
OCTSEL
OCM<2:0>
OCM<2:0>
OCM<2:0>
OCM<2:0>
OCM<2:0>
OCM<2:0>
OCM<2:0>
OCM<2:0>
Output Compare 2 Secondary Register
Output Compare 2 Register
OC2CON
OC3RS
OC3R
—
—
—
Output Compare 3 Secondary Register
Output Compare 3 Register
OC3CON
OC4RS
OC4R
—
—
—
Output Compare 4 Secondary Register
Output Compare 4 Register
OC4CON
OC5RS
OC5R
—
—
—
Output Compare 5 Secondary Register
Output Compare 5 Register
OC5CON
OC6RS
OC6R
—
—
—
Output Compare 6 Secondary Register
Output Compare 6 Register
OC6CON
OC7RS
OC7R
—
—
—
Output Compare 7 Secondary Register
Output Compare 7 Register
OC7CON
OC8RS
OC8R
—
—
—
Output Compare 8 Secondary Register
Output Compare 8 Register
OC8CON
—
—
—
Legend:
x= unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal for PinHigh devices.
TABLE 4-9:
I2C1 REGISTER MAP
SFR
Addr
All
Resets
SFR Name
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
I2C1RCV
I2C1TRN
I2C1BRG
I2C1CON
I2C1STAT
I2C1ADD
I2C1MSK
Legend:
0200
0202
0204
0206
0208
020A
020C
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Receive Register
Transmit Register
0000
00FF
0000
1000
0000
0000
0000
—
—
—
Baud Rate Generator Register
I2CEN
I2CSIDL SCLREL IPMIEN
A10M
BCL
—
DISSLW
GCSTAT
SMEN
GCEN
STREN
I2COV
ACKDT
D_A
ACKEN
P
RCEN
S
PEN
R_W
RSEN
RBF
SEN
TBF
ACKSTAT TRSTAT
—
—
—
—
—
—
—
—
—
ADD10
IWCOL
—
—
—
—
Address Register
—
Address Mask Register
x= unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal for PinHigh devices.
TABLE 4-10: I2C2 REGISTER MAP
SFR
Addr
All
Resets
SFR Name
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
I2C2RCV
I2C2TRN
I2C2BRG
I2C2CON
I2C2STAT
I2C2ADD
I2C2MSK
Legend:
0210
0212
0214
0216
0218
021A
021C
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Receive Register
Transmit Register
0000
00FF
0000
1000
0000
0000
0000
—
—
—
Baud Rate Generator Register
I2CEN
I2CSIDL SCLREL IPMIEN
A10M
BCL
—
DISSLW
GCSTAT
SMEN
GCEN
STREN
I2COV
ACKDT
D_A
ACKEN
P
RCEN
S
PEN
R_W
RSEN
RBF
SEN
TBF
ACKSTAT TRSTAT
—
—
—
—
—
—
—
—
—
ADD10
IWCOL
—
—
—
—
Address Register
—
Address Mask Register
x= unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal for PinHigh devices.
TABLE 4-11: UART1 REGISTER MAP
SFR
Addr
All
Resets
SFR Name
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
U1MODE
U1STA
0220
0222
0224
0226
0228
UARTEN
—
USIDL
IREN
—
RTSMD
—
UEN1
UTXBF
—
UEN0
TRMT
WAKE
LPBACK
ABAUD URXINV
ADDEN RIDLE
BRGH
PERR
PDSEL<1:0>
STSEL
0000
0110
xxxx
0000
0000
UTXISEL1 UTXINV UTXISEL0
UTXBRK UTXEN
URXISEL<1:0>
FERR
OERR
URXDA
U1TXREG
U1RXREG
U1BRG
—
—
—
—
—
—
—
—
—
—
—
UART Transmit Register
UART Receive Register
—
—
Baud Rate Generator Prescaler
Legend:
x= unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal for PinHigh devices.
TABLE 4-12: UART2 REGISTER MAP
SFR
Name
SFR
Addr
All
Resets
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
U2MODE
U2STA
0230
UARTEN
—
USIDL
IREN
—
RTSMD
—
UEN1
UTXBF
—
UEN0
TRMT
WAKE
LPBACK
ABAUD URXINV
ADDEN RIDLE
BRGH
PERR
PDSEL<1:0>
STSEL
0000
0110
xxxx
0000
0000
0232 UTXISEL1 UTXINV UTXISEL0
UTXBRK UTXEN
URXISEL<1:0>
FERR
OERR
URXDA
U2TXREG
U2RXREG
U2BRG
0234
0236
0238
—
—
—
—
—
—
—
—
—
—
—
UART Transmit Register
UART Receive Register
—
—
Baud Rate Generator Prescaler
Legend:
x= unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal for PinHigh devices.
TABLE 4-13: SPI1 REGISTER MAP
SFR
Name
SFR
Addr
All
Resets
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
SPI1STAT
SPI1CON1
SPI1CON2
SPI1BUF
Legend:
0240
0242
0244
0248
SPIEN
—
—
—
SPISIDL
—
—
—
—
—
SMP
—
—
CKE
—
—
SSEN
—
SPIROV
CKP
—
MSTEN
—
—
—
SPRE<2:0>
—
—
SPITBF
SPIRBF
0000
0000
0000
0000
DISSCK DISSDO MODE16
PPRE<1:0>
FRMEN
SPIFSD
FRMPOL
—
—
—
—
—
—
FRMDLY
—
SPI1 Transmit and Receive Buffer Register
x= unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal for PinHigh devices.
TABLE 4-14: SPI2 REGISTER MAP
SFR
Addr
All
Resets
SFR Name
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
SPI2STAT
SPI2CON1
SPI2CON2
SPI2BUF
Legend:
0260
0262
0264
0268
SPIEN
—
—
—
SPISIDL
—
—
—
—
—
SMP
—
—
CKE
—
—
SSEN
—
SPIROV
CKP
—
MSTEN
—
—
—
SPRE<2:0>
—
—
SPITBF
SPIRBF
0000
0000
0000
0000
DISSCK DISSDO MODE16
PPRE<1:0>
FRMEN
SPIFSD
FRMPOL
—
—
—
—
—
—
FRMDLY
—
SPI2 Transmit and Receive Buffer Register
x= unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal for PinHigh devices.
TABLE 4-15: ADC1 REGISTER MAP
All
Resets
File Name
Addr
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0300
0320
0322
0324
0326
ADC1BUF0
AD1CON1
AD1CON2
AD1CON3
AD1CHS123
AD1CHS0
ADC Data Buffer 0
FORM<1:0>
CHPS<1:0>
xxxx
0000
0000
0000
ADON
—
ADSIDL ADDMABM
—
—
AD12B
CSCNA
SSRC<2:0>
—
—
SIMSAM ASAM
SAMP
BUFM
DONE
ALTS
VCFG<2:0>
—
BUFS
SMPI<3:0>
ADCS<7:0>
ADRC
—
—
—
—
—
SAMC<4:0>
—
—
—
—
CH123NB<1:0>
CH0SB<4:0>
CH123SB
—
—
—
—
—
—
—
CH123NA<1:0>
CH123SA 0000
0328 CH0NB
CH0NA
CH0SA<4:0>
0000
(1)
AD1PCFGH
AD1PCFGL
032A PCFG31 PCFG30 PCFG29
032C PCFG15 PCFG14 PCFG13
PCFG28
PCFG12
CSS28
CSS12
—
PCFG27 PCFG26 PCFG25 PCFG24 PCFG23 PCFG22 PCFG21 PCFG20 PCFG19 PCFG18 PCFG17 PCFG16
0000
0000
0000
0000
0000
0000
PCFG11 PCFG10 PCFG9
PCFG8
CSS24
CSS8
—
PCFG7
CSS23
CSS7
—
PCFG6
CSS22
CSS6
—
PCFG5
CSS21
CSS5
—
PCFG4
CSS20
CSS4
—
PCFG3 PCFG2 PCFG1
PCFG0
CSS16
CSS0
(1)
AD1CSSH
AD1CSSL
AD1CON4
Reserved
032E CSS31
0330 CSS15
CSS30
CSS14
—
CSS29
CSS13
—
CSS27
CSS11
—
CSS26
CSS10
—
CSS25
CSS9
—
CSS19
CSS3
—
CSS18
CSS2
CSS17
CSS1
0332
—
—
DMABL<2:0>
—
0334-
033E
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Legend:
x= unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal for PinHigh devices.
Note 1:
Not all ANx inputs are available on all devices. See the device pin diagrams for available ANx inputs.
TABLE 4-16: ADC2 REGISTER MAP
All
Resets
File Name
Addr
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
ADC2BUF0
AD2CON1
AD2CON2
AD2CON3
AD2CHS123
AD2CHS0
Reserved
0340
0360
0362
0364
0366
0368
036A
ADC Data Buffer 0
FORM<1:0>
CHPS<1:0>
xxxx
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
ADON
—
ADSIDL ADDMABM
—
—
AD12B
CSCNA
SSRC<2:0>
—
—
SIMSAM ASAM
SAMP
BUFM
DONE
ALTS
VCFG<2:0>
—
BUFS
SMPI<3:0>
ADCS<7:0>
ADRC
—
—
—
—
—
—
SAMC<4:0>
—
—
—
—
—
—
—
CH123NB<1:0>
CH0SB<3:0>
CH123SB
—
CH0NA
—
—
—
—
—
—
—
—
—
CH123NA<1:0>
CH0SA<3:0>
CH123SA
CH0NB
—
—
—
—
—
—
—
PCFG8
—
—
—
—
—
PCFG0
—
AD2PCFGL
Reserved
036C PCFG15 PCFG14 PCFG13
PCFG12
—
PCFG11 PCFG10 PCFG9
PCFG7 PCFG6 PCFG5
PCFG4
—
PCFG3 PCFG2 PCFG1
036E
0370
0372
—
CSS15
—
—
CSS14
—
—
CSS13
—
—
CSS11
—
—
CSS10
—
—
CSS9
—
—
CSS7
—
—
CSS6
—
—
CSS5
—
—
CSS3
—
—
—
AD2CSSL
AD2CON4
Reserved
CSS12
—
CSS8
—
CSS4
—
CSS2
CSS1
CSS0
DMABL<2:0>
—
0374-
037E
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Legend:
x= unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal for PinHigh devices.
TABLE 4-17: DMA REGISTER MAP
All
Resets
File Name Addr Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
DMA0CON 0380 CHEN
DMA0REQ 0382 FORCE
DMA0STA 0384
SIZE
—
DIR
—
HALF
—
NULLW
—
—
—
—
—
—
—
—
—
—
AMODE<1:0>
—
—
MODE<1:0>
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
IRQSEL<6:0>
STA<15:0>
STB<15:0>
PAD<15:0>
DMA0STB 0386
DMA0PAD 0388
DMA0CNT 038A
—
—
SIZE
—
—
DIR
—
—
HALF
—
—
NULLW
—
—
—
—
CNT<9:0>
DMA1CON 038C CHEN
DMA1REQ 038E FORCE
DMA1STA 0390
—
—
—
—
—
—
—
—
—
—
—
AMODE<1:0>
—
—
—
—
—
—
MODE<1:0>
MODE<1:0>
MODE<1:0>
MODE<1:0>
MODE<1:0>
IRQSEL<6:0>
STA<15:0>
STB<15:0>
PAD<15:0>
DMA1STB 0392
DMA1PAD 0394
DMA1CNT 0396
—
—
SIZE
—
—
DIR
—
—
HALF
—
—
NULLW
—
—
—
—
CNT<9:0>
DMA2CON 0398 CHEN
DMA2REQ 039A FORCE
DMA2STA 039C
—
—
—
—
—
—
AMODE<1:0>
—
IRQSEL<6:0>
STA<15:0>
STB<15:0>
PAD<15:0>
DMA2STB 039E
DMA2PAD 03A0
DMA2CNT 03A2
—
—
SIZE
—
—
DIR
—
—
HALF
—
—
NULLW
—
—
—
—
CNT<9:0>
DMA3CON 03A4 CHEN
DMA3REQ 03A6 FORCE
DMA3STA 03A8
—
—
—
—
—
—
AMODE<1:0>
—
IRQSEL<6:0>
STA<15:0>
STB<15:0>
PAD<15:0>
DMA3STB 03AA
DMA3PAD 03AC
DMA3CNT 03AE
—
—
SIZE
—
—
DIR
—
—
HALF
—
—
NULLW
—
—
—
—
CNT<9:0>
DMA4CON 03B0 CHEN
DMA4REQ 03B2 FORCE
DMA4STA 03B4
—
—
—
—
—
—
AMODE<1:0>
—
IRQSEL<6:0>
STA<15:0>
STB<15:0>
PAD<15:0>
DMA4STB 03B6
DMA4PAD 03B8
DMA4CNT 03BA
—
—
SIZE
—
—
DIR
—
—
HALF
—
—
NULLW
—
—
—
—
CNT<9:0>
DMA5CON 03BC CHEN
DMA5REQ 03BE FORCE
DMA5STA 03C0
—
—
—
—
—
—
AMODE<1:0>
—
IRQSEL<6:0>
STA<15:0>
STB<15:0>
DMA5STB 03C2
Legend:
— = unimplemented, read as ‘0’. Reset values are shown in hexadecimal for PinHigh devices.
TABLE 4-17: DMA REGISTER MAP (CONTINUED)
All
Resets
File Name Addr Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
DMA5PAD 03C4
PAD<15:0>
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
DMA5CNT 03C6
—
—
SIZE
—
—
DIR
—
—
HALF
—
—
NULLW
—
—
—
—
CNT<9:0>
DMA6CON 03C8 CHEN
DMA6REQ 03CA FORCE
DMA6STA 03CC
—
—
—
—
—
—
—
AMODE<1:0>
—
—
MODE<1:0>
IRQSEL<6:0>
STA<15:0>
STB<15:0>
PAD<15:0>
DMA6STB 03CE
DMA6PAD 03D0
DMA6CNT 03D2
—
—
SIZE
—
—
DIR
—
—
HALF
—
—
NULLW
—
—
—
—
CNT<9:0>
DMA7CON 03D4 CHEN
DMA7REQ 03D6 FORCE
DMA7STA 03D8
—
—
—
—
—
—
—
AMODE<1:0>
—
—
MODE<1:0>
IRQSEL<6:0>
STA<15:0>
STB<15:0>
PAD<15:0>
DMA7STB 03DA
DMA7PAD 03DC
DMA7CNT 03DE
—
—
—
—
—
—
CNT<9:0>
DMACS0
DMACS1
DSADR
03E0 PWCOL7 PWCOL6 PWCOL5 PWCOL4 PWCOL3 PWCOL2 PWCOL1 PWCOL0 XWCOL7 XWCOL6 XWCOL5 XWCOL4 XWCOL3 XWCOL2 XWCOL1 XWCOL0 0000
03E2
03E4
—
—
—
—
LSTCH<3:0>
PPST7
PPST6
PPST5
PPST4
PPST3
PPST2
PPST1
PPST0
0000
0000
DSADR<15:0>
Legend:
— = unimplemented, read as ‘0’. Reset values are shown in hexadecimal for PinHigh devices.
TABLE 4-18: ECAN1 REGISTER MAP WHEN C1CTRL1.WIN = 0OR 1FOR PIC24HJXXXGP506A/510A/610A DEVICES ONLY
All
Resets
File Name
Addr
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
C1CTRL1
C1CTRL2
C1VEC
0400
0402
0404
0406
0408
040A
040C
040E
0410
0412
—
—
—
—
CSIDL
—
ABAT
—
—
—
REQOP<2:0>
—
OPMODE<2:0>
—
—
CANCAP
—
—
WIN
0480
0000
0000
0000
0000
0000
0000
0000
0000
0000
—
—
—
—
—
—
—
—
DNCNT<4:0>
ICODE<6:0>
FSA<4:0>
FNRB<5:0>
FIFOIF RBOVIF
FIFOIE RBOVIE
—
—
FILHIT<4:0>
—
C1FCTRL
C1FIFO
C1INTF
C1INTE
C1EC
DMABS<2:0>
—
—
—
—
—
—
—
—
—
—
—
FBP<5:0>
—
—
TXBO
—
TXBP
—
RXBP
—
TXWAR RXWAR EWARN
IVRIF
IVRIE
WAKIF
WAKIE
ERRIF
ERRIE
—
—
RBIF
RBIE
TBIF
TBIE
—
—
—
TERRCNT<7:0>
RERRCNT<7:0>
BRP<5:0>
C1CFG1
C1CFG2
C1FEN1
—
—
—
—
—
—
—
—
—
—
—
—
SJW<1:0>
WAKFIL
SEG2PH<2:0>
SEG2PHTS
FLTEN7
SAM
SEG1PH<2:0>
PRSEG<2:0>
0414 FLTEN15 FLTEN14 FLTEN13 FLTEN12 FLTEN11 FLTEN10 FLTEN9 FLTEN8
FLTEN6 FLTEN5 FLTEN4 FLTEN3 FLTEN2 FLTEN1 FLTEN0 FFFF
C1FMSKSEL1 0418
C1FMSKSEL2 041A
F7MSK<1:0>
F15MSK<1:0>
F6MSK<1:0>
F14MSK<1:0>
F5MSK<1:0>
F13MSK<1:0>
F4MSK<1:0>
F12MSK<1:0>
F3MSK<1:0>
F11MSK<1:0>
F2MSK<1:0>
F10MSK<1:0>
F1MSK<1:0>
F9MSK<1:0>
F0MSK<1:0>
F8MSK<1:0>
0000
0000
Legend:
— = unimplemented, read as ‘0’. Reset values are shown in hexadecimal for PinHigh devices.
TABLE 4-19: ECAN1 REGISTER MAP WHEN C1CTRL1.WIN = 0FOR PIC24HJXXXGP506A/510A/610A DEVICES ONLY
All
Resets
File Name Addr
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0400-
041E
See definition when WIN = x
C1RXFUL1 0420 RXFUL15 RXFUL14 RXFUL13 RXFUL12 RXFUL11 RXFUL10 RXFUL9 RXFUL8 RXFUL7 RXFUL6 RXFUL5 RXFUL4 RXFUL3 RXFUL2 RXFUL1 RXFUL0 0000
C1RXFUL2 0422 RXFUL31 RXFUL30 RXFUL29 RXFUL28 RXFUL27 RXFUL26 RXFUL25 RXFUL24 RXFUL23 RXFUL22 RXFUL21 RXFUL20 RXFUL19 RXFUL18 RXFUL17 RXFUL16 0000
C1RXOVF1 0428 RXOVF15 RXOVF14 RXOVF13 RXOVF12 RXOVF11 RXOVF10 RXOVF9 RXOVF8 RXOVF7 RXOVF6 RXOVF5 RXOVF4 RXOVF3 RXOVF2 RXOVF1 RXOVF0 0000
C1RXOVF2 042A RXOVF31 RXOVF30 RXOVF29 RXOVF28 RXOVF27 RXOVF26 RXOVF25 RXOVF24 RXOVF23 RXOVF22 RXOVF21 RXOVF20 RXOVF19 RXOVF18 RXOVF17 RXOVF16 0000
C1TR01CO 0430 TXEN1
N
TX
ABT1
TX
LARB1
TX
ERR1
TX
REQ1
RTREN1
RTREN3
RTREN5
RTREN7
TX1PRI<1:0>
TX3PRI<1:0>
TX5PRI<1:0>
TX7PRI<1:0>
TXEN0
TXEN2
TXEN4
TXEN6
TX
ABAT0
TX
LARB0
TX
ERR0
TX
REQ0
RTREN0
RTREN2
RTREN4
RTREN6
TX0PRI<1:0>
TX2PRI<1:0>
TX4PRI<1:0>
TX6PRI<1:0>
0000
0000
0000
xxxx
C1TR23CO 0432 TXEN3
N
TX
ABT3
TX
LARB3
TX
ERR3
TX
REQ3
TX
ABAT2
TX
LARB2
TX
ERR2
TX
REQ2
C1TR45CO 0434 TXEN5
N
TX
ABT5
TX
LARB5
TX
ERR5
TX
REQ5
TX
ABAT4
TX
LARB4
TX
ERR4
TX
REQ4
C1TR67CO 0436 TXEN7
N
TX
ABT7
TX
LARB7
TX
ERR7
TX
REQ7
TX
ABAT6
TX
LARB6
TX
ERR6
TX
REQ6
C1RXD
C1TXD
Legend:
0440
0442
Recieved Data Word
Transmit Data Word
xxxx
xxxx
x= unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal for PinHigh devices.
TABLE 4-20: ECAN1 REGISTER MAP WHEN C1CTRL1.WIN = 1FOR PIC24HJXXXGP506A/510A/610A DEVICES ONLY
All
Resets
File Name
Addr
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
See definition when WIN = x
F1BP<3:0>
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0400-
041E
C1BUFPNT1
C1BUFPNT2
C1BUFPNT3
C1BUFPNT4
C1RXM0SID
C1RXM0EID
C1RXM1SID
C1RXM1EID
C1RXM2SID
C1RXM2EID
C1RXF0SID
C1RXF0EID
C1RXF1SID
Legend:
0420
0422
0424
0426
0430
0432
0434
0436
0438
043A
0440
0442
0444
F3BP<3:0>
F2BP<3:0>
F6BP<3:0>
F10BP<3:0>
F14BP<3:0>
F0BP<3:0>
0000
0000
0000
0000
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
F7BP<3:0>
F11BP<3:0>
F15BP<3:0>
F5BP<3:0>
F9BP<3:0>
F13BP<3:0>
F4BP<3:0>
F8BP<3:0>
F12BP<3:0>
SID<10:3>
SID<2:0>
—
MIDE
MIDE
—
—
—
—
—
EID<17:16>
EID<15:8>
SID<10:3>
EID<15:8>
SID<10:3>
EID<15:8>
SID<10:3>
EID<15:8>
SID<10:3>
EID<7:0>
SID<2:0>
SID<2:0>
SID<2:0>
SID<2:0>
—
EID<17:16>
EID<7:0>
—
MIDE
EID<17:16>
EID<17:16>
EID<17:16>
EID<7:0>
—
EXIDE
EID<7:0>
—
EXIDE
x= unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal for PinHigh devices.
TABLE 4-20: ECAN1 REGISTER MAP WHEN C1CTRL1.WIN = 1FOR PIC24HJXXXGP506A/510A/610A DEVICES ONLY (CONTINUED)
All
Resets
File Name
Addr
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
C1RXF1EID
C1RXF2SID
C1RXF2EID
C1RXF3SID
C1RXF3EID
C1RXF4SID
C1RXF4EID
C1RXF5SID
C1RXF5EID
C1RXF6SID
C1RXF6EID
C1RXF7SID
C1RXF7EID
C1RXF8SID
C1RXF8EID
C1RXF9SID
C1RXF9EID
C1RXF10SID
C1RXF10EID
C1RXF11SID
C1RXF11EID
C1RXF12SID
C1RXF12EID
C1RXF13SID
C1RXF13EID
C1RXF14SID
C1RXF14EID
C1RXF15SID
C1RXF15EID
Legend:
0446
0448
044A
044C
044E
0450
0452
0454
0456
0458
045A
045C
045E
0460
0462
0464
0466
0468
046A
046C
046E
0470
0472
0474
0476
0478
047A
047C
047E
EID<15:8>
EID<7:0>
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
SID<10:3>
EID<15:8>
SID<10:3>
EID<15:8>
SID<10:3>
EID<15:8>
SID<10:3>
EID<15:8>
SID<10:3>
EID<15:8>
SID<10:3>
EID<15:8>
SID<10:3>
EID<15:8>
SID<10:3>
EID<15:8>
SID<10:3>
EID<15:8>
SID<10:3>
EID<15:8>
SID<10:3>
EID<15:8>
SID<10:3>
EID<15:8>
SID<10:3>
EID<15:8>
SID<10:3>
EID<15:8>
SID<2:0>
SID<2:0>
SID<2:0>
SID<2:0>
SID<2:0>
SID<2:0>
SID<2:0>
SID<2:0>
SID<2:0>
SID<2:0>
SID<2:0>
SID<2:0>
SID<2:0>
SID<2:0>
—
EXIDE
—
—
—
—
—
—
—
—
—
—
—
—
—
—
EID<17:16>
EID<7:0>
—
EXIDE
EID<17:16>
EID<17:16>
EID<17:16>
EID<17:16>
EID<17:16>
EID<17:16>
EID<17:16>
EID<17:16>
EID<17:16>
EID<17:16>
EID<17:16>
EID<17:16>
EID<17:16>
EID<7:0>
—
EXIDE
EID<7:0>
—
EXIDE
EID<7:0>
—
EXIDE
EID<7:0>
—
EXIDE
EID<7:0>
—
EXIDE
EID<7:0>
—
EXIDE
EID<7:0>
—
EXIDE
EID<7:0>
—
EXIDE
EID<7:0>
—
EXIDE
EID<7:0>
—
EXIDE
EID<7:0>
—
EXIDE
EID<7:0>
—
EXIDE
EID<7:0>
x= unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal for PinHigh devices.
TABLE 4-21: ECAN2 REGISTER MAP WHEN C2CTRL1.WIN = 0OR 1FOR PIC24HJ256GP610A DEVICES ONLY
All
Resets
File Name
Addr
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
C2CTRL1
C2CTRL2
C2VEC
0500
0502
0504
0506
0508
050A
050C
050E
0510
0512
—
—
—
—
CSIDL
—
ABAT
—
—
—
REQOP<2:0>
—
OPMODE<2:0>
—
—
CANCAP
—
—
WIN
0480
0000
0000
0000
0000
0000
0000
0000
0000
0000
—
—
—
—
—
—
—
—
—
—
DNCNT<4:0>
ICODE<6:0>
FSA<4:0>
FNRB<5:0>
—
—
FILHIT<4:0>
—
C2FCTRL
C2FIFO
C2INTF
C2INTE
C2EC
DMABS<2:0>
—
—
—
—
—
—
—
—
—
—
—
FBP<5:0>
TXBO
—
TXBP
—
RXBP
—
TXWAR RXWAR EWARN
IVRIF
IVRIE
WAKIF ERRIF
WAKIE ERRIE
—
—
FIFOIF RBOVIF
FIFOIE RBOVIE
RBIF
RBIE
TBIF
TBIE
—
—
—
TERRCNT<7:0>
RERRCNT<7:0>
BRP<5:0>
C2CFG1
C2CFG2
C2FEN1
—
—
—
—
—
—
—
—
—
—
—
SJW<1:0>
SEG2PHTS SAM
FLTEN7
F3MSK<1:0>
F11MSK<1:0>
WAKFIL
—
SEG2PH<2:0>
SEG1PH<2:0>
PRSEG<2:0>
0514 FLTEN15 FLTEN14 FLTEN13 FLTEN12 FLTEN11 FLTEN10 FLTEN9 FLTEN8
FLTEN6 FLTEN5 FLTEN4 FLTEN3 FLTEN2 FLTEN1 FLTEN0 FFFF
C2FMSKSEL1 0518
C2FMSKSEL2 051A
F7MSK<1:0>
F15MSK<1:0>
F6MSK<1:0>
F14MSK<1:0>
F5MSK<1:0>
F13MSK<1:0>
F4MSK<1:0>
F12MSK<1:0>
F2MSK<1:0>
F10MSK<1:0>
F1MSK<1:0>
F9MSK<1:0>
F0MSK<1:0>
F8MSK<1:0>
0000
0000
Legend:
— = unimplemented, read as ‘0’. Reset values are shown in hexadecimal for PinHigh devices.
TABLE 4-22: ECAN2 REGISTER MAP WHEN C2CTRL1.WIN = 0FOR PIC24HJ256GP610A DEVICES ONLY
All
Resets
File Name Addr
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0500-
051E
See definition when WIN = x
C2RXFUL1
C2RXFUL2
0520 RXFUL15 RXFUL14 RXFUL13 RXFUL12 RXFUL11 RXFUL10 RXFUL9 RXFUL8 RXFUL7 RXFUL6 RXFUL5 RXFUL4 RXFUL3 RXFUL2 RXFUL1 RXFUL0 0000
0522 RXFUL31 RXFUL30 RXFUL29 RXFUL28 RXFUL27 RXFUL26 RXFUL25 RXFUL24 RXFUL23 RXFUL22 RXFUL21 RXFUL20 RXFUL19 RXFUL18 RXFUL17 RXFUL16 0000
C2RXOVF1 0528 RXOVF15 RXOVF14 RXOVF13 RXOVF12 RXOVF11 RXOVF10 RXOVF09 RXOVF08 RXOVF7 RXOVF6 RXOVF5 RXOVF4 RXOVF3 RXOVF2 RXOVF1 RXOVF0 0000
C2RXOVF2 052A RXOVF31 RXOVF30 RXOVF29 RXOVF28 RXOVF27 RXOVF26 RXOVF25 RXOVF24 RXOVF23 RXOVF22 RXOVF21 RXOVF20 RXOVF19 RXOVF18 RXOVF17 RXOVF16 0000
C2TR01CON 0530 TXEN1
C2TR23CON 0532 TXEN3
C2TR45CON 0534 TXEN5
C2TR67CON 0536 TXEN7
TX
ABAT1
TX
LARB1
TX
ERR1
TX
REQ1
RTREN1
RTREN3
RTREN5
RTREN7
TX1PRI<1:0>
TX3PRI<1:0>
TX5PRI<1:0>
TX7PRI<1:0>
TXEN0
TXEN2
TXEN4
TXEN6
TX
ABAT0
TX
LARB0
TX
ERR0
TX
REQ0
RTREN0
RTREN2
RTREN4
RTREN6
TX0PRI<1:0>
TX2PRI<1:0>
TX4PRI<1:0>
TX6PRI<1:0>
0000
0000
0000
xxxx
TX
ABAT3
TX
LARB3
TX
ERR3
TX
REQ3
TX
ABAT2
TX
LARB2
TX
ERR2
TX
REQ2
TX
ABAT5
TX
LARB5
TX
ERR5
TX
REQ5
TX
ABAT4
TX
LARB4
TX
ERR4
TX
REQ4
TX
TX
TX
TX
TX
TX
TX
TX
ABAT7
LARB7
ERR7
REQ7
ABAT6
LARB6
ERR6
REQ6
C2RXD
C2TXD
Legend:
0540
0542
Recieved Data Word
Transmit Data Word
xxxx
xxxx
x= unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal for PinHigh devices.
TABLE 4-23: ECAN2 REGISTER MAP WHEN C2CTRL1.WIN = 1FOR PIC24HJ256GP610A DEVICES ONLY
All
Resets
File Name
Addr
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
See definition when WIN = x
F1BP<3:0>
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0500-
051E
C2BUFPNT1
C2BUFPNT2
C2BUFPNT3
C2BUFPNT4
C2RXM0SID
C2RXM0EID
C2RXM1SID
C2RXM1EID
C2RXM2SID
C2RXM2EID
C2RXF0SID
C2RXF0EID
C2RXF1SID
C2RXF1EID
C2RXF2SID
C2RXF2EID
C2RXF3SID
C2RXF3EID
C2RXF4SID
C2RXF4EID
C2RXF5SID
C2RXF5EID
C2RXF6SID
C2RXF6EID
C2RXF7SID
C2RXF7EID
C2RXF8SID
C2RXF8EID
C2RXF9SID
C2RXF9EID
C2RXF10SID
C2RXF10EID
C2RXF11SID
Legend:
0520
0522
0524
0526
0530
0532
0534
0536
0538
053A
0540
0542
0544
0546
0548
054A
054C
054E
0550
0552
0554
0556
0558
055A
055C
055E
0560
0562
0564
0566
0568
056A
056C
F3BP<3:0>
F2BP<3:0>
F6BP<3:0>
F10BP<3:0>
F14BP<3:0>
F0BP<3:0>
0000
0000
0000
0000
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
F7BP<3:0>
F12BP<3:0>
F15BP<3:0>
F5BP<3:0>
F9BP<3:0>
F4BP<3:0>
F8BP<3:0>
F12BP<3:0>
F13BP<3:0>
SID<2:0>
SID<10:3>
—
MIDE
MIDE
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
EID<17:16>
EID<15:8>
SID<10:3>
EID<15:8>
SID<10:3>
EID<15:8>
SID<10:3>
EID<15:8>
SID<10:3>
EID<15:8>
SID<10:3>
EID<15:8>
SID<10:3>
EID<15:8>
SID<10:3>
EID<15:8>
SID<10:3>
EID<15:8>
SID<10:3>
EID<15:8>
SID<10:3>
EID<15:8>
SID<10:3>
EID<15:8>
SID<10:3>
EID<15:8>
SID<10:3>
EID<15:8>
SID<10:3>
EID<7:0>
SID<2:0>
SID<2:0>
SID<2:0>
SID<2:0>
SID<2:0>
SID<2:0>
SID<2:0>
SID<2:0>
SID<2:0>
SID<2:0>
SID<2:0>
SID<2:0>
SID<2:0>
SID<2:0>
—
EID<17:16>
EID<7:0>
—
MIDE
EID<17:16>
EID<17:16>
EID<17:16>
EID<17:16>
EID<17:16>
EID<17:16>
EID<17:16>
EID<17:16>
EID<17:16>
EID<17:16>
EID<17:16>
EID<17:16>
EID<17:16>
EID<7:0>
—
EXIDE
EID<7:0>
—
EXIDE
EID<7:0>
—
EXIDE
EID<7:0>
—
EXIDE
EID<7:0>
—
EXIDE
EID<7:0>
—
EXIDE
EID<7:0>
—
EXIDE
EID<7:0>
—
EXIDE
EID<7:0>
—
EXIDE
EID<7:0>
—
EXIDE
EID<7:0>
—
EXIDE
EID<7:0>
—
EXIDE
x= unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal for PinHigh devices.
TABLE 4-23: ECAN2 REGISTER MAP WHEN C2CTRL1.WIN = 1FOR PIC24HJ256GP610A DEVICES ONLY (CONTINUED)
All
Resets
File Name
Addr
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
C2RXF11EID
C2RXF12SID
C2RXF12EID
C2RXF13SID
C2RXF13EID
C2RXF14SID
C2RXF14EID
C2RXF15SID
C2RXF15EID
Legend:
056E
0570
0572
0574
0576
0578
057A
057C
057E
EID<15:8>
EID<7:0>
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
SID<10:3>
EID<15:8>
SID<10:3>
EID<15:8>
SID<10:3>
EID<15:8>
SID<10:3>
EID<15:8>
SID<2:0>
SID<2:0>
SID<2:0>
SID<2:0>
—
EXIDE
—
—
—
—
EID<17:16>
EID<7:0>
—
EXIDE
EID<17:16>
EID<17:16>
EID<17:16>
EID<7:0>
—
EXIDE
EID<7:0>
—
EXIDE
EID<7:0>
x= unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal for PinHigh devices.
(1)
TABLE 4-24: PORTA REGISTER MAP
All
Resets
File Name Addr
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
TRISA
PORTA
LATA
02C0
02C2
02C4
06C0
TRISA15
RA15
TRISA14
RA14
TRISA13
RA13
LATA13
—
TRISA12
RA12
LATA12
—
—
—
—
—
TRISA10
RA10
LATA10
—
TRISA9
RA9
—
—
—
—
TRISA7
RA7
TRISA6
RA6
TRISA5
RA5
TRISA4
RA4
TRISA3
RA3
TRISA2
RA2
TRISA1
RA1
TRISA0
RA0
F6FF
xxxx
xxxx
0000
LATA15
ODCA15
LATA14
ODCA14
LATA9
—
LATA7
—
LATA6
—
LATA5
ODCA5
LATA4
ODCA4
LATA3
ODCA3
LATA2
ODCA2
LATA1
ODCA1
LATA0
ODCA0
ODCA
Legend:
x= unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal for PinHigh devices.
Note 1:
The actual set of I/O port pins varies from one device to another. Please refer to the corresponding pinout diagrams.
(1)
TABLE 4-25: PORTB REGISTER MAP
All
Resets
File Name
Addr
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
TRISB
PORTB
LATB
02C6
02C8
02CA
TRISB15 TRISB14 TRISB13 TRISB12 TRISB11 TRISB10 TRISB9
TRISB8
RB8
TRISB7
RB7
TRISB6
RB6
TRISB5
RB5
TRISB4
RB4
TRISB3
RB3
TRISB2
RB2
TRISB1 TRISB0
FFFF
xxxx
xxxx
RB15
RB14
RB13
RB12
RB11
RB10
RB9
RB1
RB0
LATB15
LATB14
LATB13
LATB12
LATB11
LATB10
LATB9
LATB8
LATB7
LATB6
LATB5
LATB4
LATB3
LATB2
LATB1
LATB0
Legend:
x= unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal for PinHigh devices.
Note 1:
The actual set of I/O port pins varies from one device to another. Please refer to the corresponding pinout diagrams.
(1)
TABLE 4-26: PORTC REGISTER MAP
All
Resets
File Name Addr
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
TRISC
PORTC
LATC
02CC TRISC15 TRISC14 TRISC13 TRISC12
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
TRISC4
RC4
TRISC3
RC3
TRISC2
RC2
TRISC1
RC1
—
—
—
F01E
xxxx
xxxx
02CE
02D0
RC15
RC14
RC13
RC12
LATC15
LATC14
LATC13
LATC12
LATC4
LATC3
LATC2
LATC1
Legend:
x= unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal for PinHigh devices.
Note 1:
The actual set of I/O port pins varies from one device to another. Please refer to the corresponding pinout diagrams.
(1)
TABLE 4-27: PORTD REGISTER MAP
All
Resets
File Name Addr
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
TRISD
PORTD
LATD
02D2
02D4
02D6
06D2
TRISD15
RD15
TRISD14
RD14
TRISD13
RD13
TRISD12
RD12
TRISD11 TRISD10 TRISD9 TRISD8 TRISD7 TRISD6 TRISD5 TRISD4 TRISD3 TRISD2 TRISD1 TRISD0
FFFF
xxxx
xxxx
0000
RD11
RD10
RD9
RD8
RD7
RD6
RD5
RD4
RD3
RD2
RD1
RD0
LATD15
ODCD15
LATD14
ODCD14
LATD13
ODCD13
LATD12
ODCD12
LATD11
ODCD11
LATD10
ODCD10
LATD9
ODCD9
LATD8
ODCD8
LATD7
ODCD7
LATD6
ODCD6
LATD5
ODCD5
LATD4
ODCD4
LATD3
ODCD3
LATD2
ODCD2
LATD1
ODCD1
LATD0
ODCD0
ODCD
Legend:
x= unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal for PinHigh devices.
Note 1:
The actual set of I/O port pins varies from one device to another. Please refer to the corresponding pinout diagrams.
(1)
TABLE 4-28: PORTE REGISTER MAP
All
Resets
File Name Addr
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
TRISE
PORTE
LATE
02D8
02DA
02DC
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
TRISE7
RE7
TRISE6
RE6
TRISE5
RE5
TRISE4
RE4
TRISE3
RE3
TRISE2
RE2
TRISE1
RE1
TRISE0
RE0
00FF
xxxx
xxxx
LATE7
LATE6
LATE5
LATE4
LATE3
LATE2
LATE1
LATE0
Legend:
x= unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal for PinHigh devices.
Note 1:
The actual set of I/O port pins varies from one device to another. Please refer to the corresponding pinout diagrams.
(1)
TABLE 4-29: PORTF REGISTER MAP
File Name Addr
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
All Resets
TRISF
PORTF
LATF
02DE
02E0
02E2
06DE
—
—
—
—
—
—
—
—
TRISF13
RF13
TRISF12
RF12
—
—
—
—
—
—
—
—
—
—
—
—
TRISF8
RF8
TRISF7
RF7
TRISF6
RF6
TRISF5
RF5
TRISF4
RF4
TRISF3
RF3
TRISF2
RF2
TRISF1
RF1
TRISF0
RF0
31FF
xxxx
xxxx
0000
LATF13
ODCF13
LATF12
ODCF12
LATF8
ODCF8
LATF7
ODCF7
LATF6
ODCF6
LATF5
ODCF5
LATF4
ODCF4
LATF3
ODCF3
LATF2
ODCF2
LATF1
ODCF1
LATF0
ODCF0
(2)
ODCF
Legend:
x= unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal for PinHigh devices.
Note 1:
The actual set of I/O port pins varies from one device to another. Please refer to the corresponding pinout diagrams.
(1)
TABLE 4-30: PORTG REGISTER MAP
All
Resets
File Name Addr
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
TRISG
PORTG
LATG
02E4
02E6
02E8
06E4
TRISG15
RG15
TRISG14
RG14
TRISG13
RG13
TRISG12
RG12
—
—
—
—
—
—
—
—
TRISG9
RG9
TRISG8
RG8
TRISG7
RG7
TRISG6
RG6
—
—
—
—
—
—
—
—
TRISG3
RG3
TRISG2
RG2
TRISG1
RG1
TRISG0
RG0
F3CF
xxxx
xxxx
0000
LATG15
ODCG15
LATG14
ODCG14
LATG13
ODCG13
LATG12
ODCG12
LATG9
ODCG9
LATG8
ODCG8
LATG7
ODCG7
LATG6
ODCG6
LATG3
ODCG3
LATG2
ODCG2
LATG1
ODCG1
LATG0
ODCG0
(2)
ODCG
Legend:
x= unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal for PinHigh devices.
Note 1:
The actual set of I/O port pins varies from one device to another. Please refer to the corresponding pinout diagrams.
TABLE 4-31: SYSTEM CONTROL REGISTER MAP
All
Resets
File Name Addr
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
(1)
RCON
0740
0742
0744
0746
0748
TRAPR IOPUWR
—
COSC<2:0>
DOZE<2:0>
—
—
—
—
—
—
NOSC<2:0>
FRCDIV<2:0>
—
VREGS
EXTR
SWR
—
SWDTEN WDTO
SLEEP
CF
IDLE
—
BOR
POR
xxxx
0300
3040
0030
0000
(2)
OSCCON
CLKDIV
PLLFBD
OSCTUN
—
CLKLOCK
LOCK
—
—
LPOSCEN OSWEN
ROI
DOZEN
—
PLLPOST<1:0>
PLLPRE<4:0>
—
—
—
—
—
—
—
—
PLLDIV<8:0>
—
—
—
—
—
—
TUN<5:0>
Legend:
Note 1:
2:
x= unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal for PinHigh devices.
RCON register Reset values dependent on type of Reset.
OSCCON register Reset values dependent on the FOSC Configuration bits and by type of Reset.
TABLE 4-32: NVM REGISTER MAP
All
Resets
File Name
Addr
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
(1)
NVMCON
NVMKEY
0760
0766
WR
—
WREN
—
WRERR
—
—
—
—
—
—
—
—
—
—
—
—
ERASE
—
—
NVMOP<3:0>
0000
NVMKEY<7:0>
0000
Legend:
Note 1:
x= unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal for PinHigh devices.
Reset value shown is for POR only. Value on other Reset states is dependent on the state of memory write or erase operations at the time of Reset.
TABLE 4-33: PMD REGISTER MAP
All
Resets
File Name
Addr
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PMD1
PMD2
PMD3
Legend:
0770
0772
0774
T5MD
IC8MD
T9MD
T4MD
IC7MD
T8MD
T3MD
IC6MD
T7MD
T2MD
IC5MD
T6MD
T1MD
IC4MD
—
—
IC3MD
—
—
IC2MD
—
—
IC1MD
—
I2C1MD
OC8MD
—
U2MD
OC7MD
—
U1MD
OC6MD
—
SPI2MD SPI1MD
C2MD
C1MD
OC2MD
I2C2MD
AD1MD
OC1MD
AD2MD
0000
0000
0000
OC5MD OC4MD OC3MD
—
—
—
x= unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal for PinHigh devices.
PIC24HJXXXGPX06A/X08A/X10A
4.2.6
SOFTWARE STACK
4.2.7
DATA RAM PROTECTION FEATURE
The PIC24H product family supports Data RAM protec-
tion features that enable segments of RAM to be
protected when used in conjunction with Boot and
Secure Code Segment Security. BSRAM (Secure RAM
segment for BS) is accessible only from the Boot Seg-
ment Flash code, when enabled. SSRAM (Secure
RAM segment for RAM) is accessible only from the
Secure Segment Flash code, when enabled. See
Table 4-1 for an overview of the BSRAM and SSRAM
SFRs.
In addition to its use as a working register, the W15
register in the PIC24HJXXXGPX06A/X08A/X10A
devices is also used as a software Stack Pointer. The
Stack Pointer always points to the first available free
word and grows from lower to higher addresses. It pre-
decrements for stack pops and post-increments for
stack pushes, as shown in Figure 4-5. For a PC push
during any CALLinstruction, the MSB of the PC is zero-
extended before the push, ensuring that the MSB is
always clear.
Note:
A PC push during exception processing
concatenates the SRL register to the MSB
of the PC prior to the push.
4.3
Instruction Addressing Modes
The addressing modes in Table 4-34 form the basis of
the addressing modes optimized to support the specific
features of individual instructions. The addressing
modes provided in the MAC class of instructions are
somewhat different from those in the other instruction
types.
The Stack Pointer Limit register (SPLIM) associated
with the Stack Pointer sets an upper address boundary
for the stack. SPLIM is uninitialized at Reset. As is the
case for the Stack Pointer, SPLIM<0> is forced to ‘0’
because all stack operations must be word-aligned.
Whenever an EA is generated using W15 as a source
or destination pointer, the resulting address is
compared with the value in SPLIM. If the contents of
the Stack Pointer (W15) and the SPLIM register are
equal and a push operation is performed, a stack error
trap will not occur. The stack error trap will occur on a
subsequent push operation. Thus, for example, if it is
desirable to cause a stack error trap when the stack
grows beyond address 0x2000 in RAM, initialize the
SPLIM with the value 0x1FFE.
4.3.1
FILE REGISTER INSTRUCTIONS
Most file register instructions use a 13-bit address field
(f) to directly address data present in the first 8192
bytes of data memory (Near Data Space). Most file
register instructions employ a working register, W0,
which is denoted as WREG in these instructions. The
destination is typically either the same file register or
WREG (with the exception of the MUL instruction),
which writes the result to a register or register pair. The
MOV instruction allows additional flexibility and can
access the entire data space.
Similarly, a Stack Pointer underflow (stack error) trap is
generated when the Stack Pointer address is found to
be less than 0x0800. This prevents the stack from
interfering with the Special Function Register (SFR)
space.
4.3.2
MCU INSTRUCTIONS
The 3-operand MCU instructions are of the form:
Operand 3 = Operand 1 <function> Operand 2
A write to the SPLIM register should not be immediately
followed by an indirect read operation using W15.
where Operand 1 is always a working register (i.e., the
addressing mode can only be Register Direct) which is
referred to as Wb. Operand 2 can be a W register,
fetched from data memory, or a 5-bit literal. The result
location can be either a W register or a data memory
location. The following addressing modes are
supported by MCU instructions:
FIGURE 4-5:
CALLSTACK FRAME
0x0000
15
0
• Register Direct
• Register Indirect
PC<15:0>
000000000
W15 (before CALL)
• Register Indirect Post-Modified
• Register Indirect Pre-Modified
• 5-bit or 10-bit Literal
PC<22:16>
<Free Word>
W15 (after CALL)
POP : [--W15]
PUSH: [W15++]
Note:
Not all instructions support all the
addressing modes given above. Individual
instructions may support different subsets
of these addressing modes.
© 2009 Microchip Technology Inc.
Preliminary
DS70592A-page 53
PIC24HJXXXGPX06A/X08A/X10A
TABLE 4-34: FUNDAMENTAL ADDRESSING MODES SUPPORTED
Addressing Mode
File Register Direct
Description
The address of the file register is specified explicitly.
The contents of a register are accessed directly.
The contents of Wn forms the EA.
Register Direct
Register Indirect
Register Indirect Post-Modified
The contents of Wn forms the EA. Wn is post-modified (incremented or
decremented) by a constant value.
Register Indirect Pre-Modified
Wn is pre-modified (incremented or decremented) by a signed constant value
to form the EA.
Register Indirect with Register Offset The sum of Wn and Wb forms the EA.
Register Indirect with Literal Offset The sum of Wn and a literal forms the EA.
4.3.3
MOVE INSTRUCTIONS
4.4
Interfacing Program and Data
Memory Spaces
Move instructions provide a greater degree of address-
ing flexibility than other instructions. In addition to the
Addressing modes supported by most MCU instruc-
tions, move instructions also support Register Indirect
with Register Offset Addressing mode, also referred to
as Register Indexed mode.
The PIC24HJXXXGPX06A/X08A/X10A architecture
uses a 24-bit wide program space and a 16-bit wide
data space. The architecture is also a modified Harvard
scheme, meaning that data can also be present in the
program space. To use this data successfully, it must
be accessed in a way that preserves the alignment of
information in both spaces.
Note:
For the MOV instructions, the Addressing
mode specified in the instruction can differ
for the source and destination EA.
However, the 4-bit Wb (Register Offset)
field is shared between both source and
destination (but typically only used by
one).
Aside
from
normal
execution,
the
PIC24HJXXXGPX06A/X08A/X10A architecture pro-
vides two methods by which program space can be
accessed during operation:
• Using table instructions to access individual bytes
or words anywhere in the program space
In summary, the following Addressing modes are
supported by move instructions:
• Remapping a portion of the program space into
the data space (Program Space Visibility)
• Register Direct
• Register Indirect
Table instructions allow an application to read or write
to small areas of the program memory. This capability
makes the method ideal for accessing data tables that
need to be updated from time to time. It also allows
access to all bytes of the program word. The remap-
ping method allows an application to access a large
block of data on a read-only basis, which is ideal for
look ups from a large table of static data. It can only
access the least significant word of the program word.
• Register Indirect Post-modified
• Register Indirect Pre-modified
• Register Indirect with Register Offset (Indexed)
• Register Indirect with Literal Offset
• 8-bit Literal
• 16-bit Literal
Note:
Not all instructions support all the
Addressing modes given above. Individual
instructions may support different subsets
of these Addressing modes.
4.4.1
ADDRESSING PROGRAM SPACE
Since the address ranges for the data and program
spaces are 16 and 24 bits, respectively, a method is
needed to create a 23-bit or 24-bit program address
from 16-bit data registers. The solution depends on the
interface method to be used.
4.3.4
OTHER INSTRUCTIONS
Besides the various addressing modes outlined above,
some instructions use literal constants of various sizes.
For example, BRA (branch) instructions use 16-bit
signed literals to specify the branch destination directly,
whereas the DISI instruction uses a 14-bit unsigned
literal field. In some instructions, the source of an oper-
and or result is implied by the opcode itself. Certain
operations, such as NOP, do not have any operands.
For table operations, the 8-bit Table Page register
(TBLPAG) is used to define a 32K word region within
the program space. This is concatenated with a 16-bit
EA to arrive at a full 24-bit program space address. In
this format, the Most Significant bit of TBLPAG is used
to determine if the operation occurs in the user memory
(TBLPAG<7> = 0) or the configuration memory
(TBLPAG<7> = 1).
DS70592A-page 54
Preliminary
© 2009 Microchip Technology Inc.
PIC24HJXXXGPX06A/X08A/X10A
For remapping operations, the 8-bit Program Space
Table 4-35 and Figure 4-6 show how the program EA is
created for table operations and remapping accesses
from the data EA. Here, P<23:0> refers to a program
space word, whereas D<15:0> refers to a data space
word.
Visibility register (PSVPAG) is used to define a
16K word page in the program space. When the Most
Significant bit of the EA is ‘1’, PSVPAG is concatenated
with the lower 15 bits of the EA to form a 23-bit program
space address. Unlike table operations, this limits
remapping operations strictly to the user memory area.
TABLE 4-35: PROGRAM SPACE ADDRESS CONSTRUCTION
Program Space Address
Access
Space
Access Type
<23>
<22:16>
<15>
<14:1>
<0>
Instruction Access
(Code Execution)
User
User
0
PC<22:1>
0
0xxx xxxx xxxx xxxx xxxx xxx0
TBLRD/TBLWT
(Byte/Word Read/Write)
TBLPAG<7:0>
0xxx xxxx
Data EA<15:0>
xxxx xxxx xxxx xxxx
Data EA<15:0>
Configuration
TBLPAG<7:0>
1xxx xxxx
xxxx xxxx xxxx xxxx
Program Space Visibility User
(Block Remap/Read)
0
PSVPAG<7:0>
xxxx xxxx
Data EA<14:0>(1)
0
xxx xxxx xxxx xxxx
Note 1: Data EA<15> is always ‘1’ in this case, but is not used in calculating the program space address. Bit 15 of
the address is PSVPAG<0>.
© 2009 Microchip Technology Inc.
Preliminary
DS70592A-page 55
PIC24HJXXXGPX06A/X08A/X10A
FIGURE 4-6:
DATA ACCESS FROM PROGRAM SPACE ADDRESS GENERATION
Program Counter(1)
Program Counter
23 bits
0
0
1/0
EA
Table Operations(2)
1/0
TBLPAG
8 bits
16 bits
24 bits
Select
1
0
EA
Program Space Visibility(1)
(Remapping)
0
PSVPAG
8 bits
15 bits
23 bits
Byte Select
User/Configuration
Space Select
Note 1: The LSb of program space addresses is always fixed as ‘0’ in order to maintain word
alignment of data in the program and data spaces.
2: Table operations are not required to be word-aligned. Table read operations are permitted
in the configuration memory space.
DS70592A-page 56
Preliminary
© 2009 Microchip Technology Inc.
PIC24HJXXXGPX06A/X08A/X10A
2. TBLRDH (Table Read High): In Word mode, it
maps the entire upper word of a program address
(P<23:16>) to a data address. Note that
D<15:8>, the ‘phantom byte’, will always be ‘0’.
4.4.2
DATA ACCESS FROM PROGRAM
MEMORY USING TABLE
INSTRUCTIONS
The TBLRDL and TBLWTL instructions offer a direct
method of reading or writing the lower word of any
address within the program space without going
through data space. The TBLRDHand TBLWTHinstruc-
tions are the only method to read or write the upper
8 bits of a program space word as data.
In Byte mode, it maps the upper or lower byte of
the program word to D<7:0> of the data
address, as above. Note that the data will
always be ‘0’ when the upper ‘phantom’ byte is
selected (Byte Select = 1).
In a similar fashion, two table instructions, TBLWTH
and TBLWTL, are used to write individual bytes or
words to a program space address. The details of
their operation are explained in Section 5.0 “Flash
Program Memory”.
The PC is incremented by two for each successive
24-bit program word. This allows program memory
addresses to directly map to data space addresses.
Program memory can thus be regarded as two 16-bit,
word wide address spaces, residing side by side, each
with the same address range. TBLRDL and TBLWTL
access the space which contains the least significant
data word and TBLRDHand TBLWTHaccess the space
which contains the upper data byte.
For all table operations, the area of program memory
space to be accessed is determined by the Table Page
register (TBLPAG). TBLPAG covers the entire program
memory space of the device, including user and config-
uration spaces. When TBLPAG<7> = 0, the table page
is located in the user memory space. When
TBLPAG<7> = 1, the page is located in configuration
space.
Two table instructions are provided to move byte or
word sized (16-bit) data to and from program space.
Both function as either byte or word operations.
1. TBLRDL (Table Read Low): In Word mode, it
maps the lower word of the program space
location (P<15:0>) to a data address (D<15:0>).
In Byte mode, either the upper or lower byte of
the lower program word is mapped to the lower
byte of a data address. The upper byte is
selected when Byte Select is ‘1’; the lower byte
is selected when it is ‘0’.
FIGURE 4-7:
ACCESSING PROGRAM MEMORY WITH TABLE INSTRUCTIONS
Program Space
TBLPAG
02
23
15
0
0x000000
23
16
8
0
00000000
00000000
00000000
0x020000
0x030000
00000000
‘Phantom’ Byte
TBLRDH.B(Wn<0> = 0)
TBLRDL.B(Wn<0> = 1)
TBLRDL.B(Wn<0> = 0)
TBLRDL.W
The address for the table operation is determined by the data EA
within the page defined by the TBLPAG register.
Only read operations are shown; write operations are also valid in
the user memory area.
0x800000
© 2009 Microchip Technology Inc.
Preliminary
DS70592A-page 57
PIC24HJXXXGPX06A/X08A/X10A
24-bit program word are used to contain the data. The
upper 8 bits of any program space location used as
data should be programmed with ‘1111 1111’ or
‘0000 0000’ to force a NOP. This prevents possible
issues should the area of code ever be accidentally
executed.
4.4.3
READING DATA FROM PROGRAM
MEMORY USING PROGRAM SPACE
VISIBILITY
The upper 32 Kbytes of data space may optionally be
mapped into any 16K word page of the program space.
This option provides transparent access of stored con-
stant data from the data space without the need to use
special instructions (i.e., TBLRDL/H).
Note:
PSV access is temporarily disabled during
table reads/writes.
Program space access through the data space occurs
if the Most Significant bit of the data space EA is ‘1’ and
program space visibility is enabled by setting the PSV
bit in the Core Control register (CORCON<2>). The
location of the program memory space to be mapped
into the data space is determined by the Program
Space Visibility Page register (PSVPAG). This 8-bit
register defines any one of 256 possible pages of
16K words in program space. In effect, PSVPAG func-
tions as the upper 8 bits of the program memory
address, with the 15 bits of the EA functioning as the
lower bits. Note that by incrementing the PC by 2 for
each program memory word, the lower 15 bits of data
space addresses directly map to the lower 15 bits in the
corresponding program space addresses.
For operations that use PSV and are executed outside
a REPEAT loop, the MOV and MOV.D instructions
require one instruction cycle in addition to the specified
execution time. All other instructions require two
instruction cycles in addition to the specified execution
time.
For operations that use PSV, which are executed inside
a REPEAT loop, there will be some instances that
require two instruction cycles in addition to the
specified execution time of the instruction:
• Execution in the first iteration
• Execution in the last iteration
• Execution prior to exiting the loop due to an
interrupt
• Execution upon re-entering the loop after an
interrupt is serviced
Data reads to this area add an additional cycle to the
instruction being executed, since two program memory
fetches are required.
Any other iteration of the REPEAT loop will allow the
instruction accessing data, using PSV, to execute in a
single cycle.
Although each data space address, 8000h and higher,
maps directly into a corresponding program memory
address (see Figure 4-8), only the lower 16 bits of the
FIGURE 4-8:
PROGRAM SPACE VISIBILITY OPERATION
When CORCON<2> = 1and EA<15> = 1:
Program Space
Data Space
PSVPAG
02
23
15
0
0x000000
0x0000
Data EA<14:0>
0x010000
0x018000
The data in the page
designated by PSV-
PAG is mapped into
the upper half of the
data memory
0x8000
space...
PSV Area
...whilethelower15bits
of the EA specify an
exact address within
the PSV area. This
corresponds exactly to
the same lower 15 bits
of the actual program
space address.
0xFFFF
0x800000
DS70592A-page 58
Preliminary
© 2009 Microchip Technology Inc.
PIC24HJXXXGPX06A/X08A/X10A
ital signal controller just before shipping the product.
This also allows the most recent firmware or a custom
firmware to be programmed.
5.0
FLASH PROGRAM MEMORY
Note:
This data sheet summarizes the features
of the PIC24HJXXXGPX06A/X08A/X10A
family of devices. However, it is not
intended to be a comprehensive reference
source. To complement the information in
this data sheet, refer to the “PIC24H
Family Reference Manual”, Section 5.
“Flash Programming” (DS70228), which
is available from the Microchip website
(www.microchip.com).
RTSP is accomplished using TBLRD (table read) and
TBLWT (table write) instructions. With RTSP, the user
can write program memory data either in blocks or
‘rows’ of 64 instructions (192 bytes) at a time, or single
instructions and erase program memory in blocks or
‘pages’ of 512 instructions (1536 bytes) at a time.
5.1
Table Instructions and Flash
Programming
The PIC24HJXXXGPX06A/X08A/X10A devices con-
tain internal Flash program memory for storing and
executing application code. The memory is readable,
writable and erasable during normal operation over the
entire VDD range.
Regardless of the method used, all programming of
Flash memory is done with the table read and table
write instructions. These allow direct read and write
access to the program memory space from the data
memory while the device is in normal operating mode.
The 24-bit target address in the program memory is
formed using bits<7:0> of the TBLPAG register and the
Effective Address (EA) from a W register specified in
the table instruction, as shown in Figure 5-1.
Flash memory can be programmed in two ways:
1. In-Circuit Serial Programming™ (ICSP™)
programming capability
2. Run-Time Self-Programming (RTSP)
The TBLRDLand the TBLWTLinstructions are used to
read or write to bits<15:0> of program memory.
TBLRDLand TBLWTLcan access program memory in
both Word and Byte modes.
ICSP
programming
capability
allows
a
PIC24HJXXXGPX06A/X08A/X10A device to be seri-
ally programmed while in the end application circuit.
This is simply done with two lines for programming
clock and programming data (one of the alternate pro-
gramming pin pairs: PGECx/PGEDx, and three other
lines for power (VDD), ground (VSS) and Master Clear
(MCLR). This allows customers to manufacture boards
with unprogrammed devices and then program the dig-
The TBLRDHand TBLWTHinstructions are used to read
or write to bits<23:16> of program memory. TBLRDH
and TBLWTHcan also access program memory in Word
or Byte mode.
FIGURE 5-1:
ADDRESSING FOR TABLE REGISTERS
24 bits
Program Counter
Using
Program Counter
0
0
Working Reg EA
Using
Table Instruction
1/0
TBLPAG Reg
8 bits
16 bits
User/Configuration
Space Select
Byte
Select
24-bit EA
© 2009 Microchip Technology Inc.
Preliminary
DS70592A-page 59
PIC24HJXXXGPX06A/X08A/X10A
5.2
RTSP Operation
5.3
Programming Operations
The PIC24HJXXXGPX06A/X08A/X10A Flash program
memory array is organized into rows of 64 instructions
or 192 bytes. RTSP allows the user to erase a page of
memory, which consists of eight rows (512 instructions)
at a time, and to program one row or one word at a
time. Table 24-12 displays typical erase and program-
ming times. The 8-row erase pages and single row
write rows are edge-aligned, from the beginning of pro-
gram memory, on boundaries of 1536 bytes and 192
bytes, respectively.
A complete programming sequence is necessary for
programming or erasing the internal Flash in RTSP
mode. The processor stalls (waits) until the
programming operation is finished.
The programming time depends on the FRC accuracy
(see Table 24-19) and the value of the FRC Oscillator
Tuning register (see Register 9-4). Use the following
formula to calculate the minimum and maximum values
for the Row Write Time, Page Erase Time and Word
Write Cycle Time parameters (see Table 24-12).
The program memory implements holding buffers that
can contain 64 instructions of programming data. Prior
to the actual programming operation, the write data
must be loaded into the buffers in sequential order. The
instruction words loaded must always be from a group
of 64 boundary.
EQUATION 5-1:
PROGRAMMING TIME
T
-------------------------------------------------------------------------------------------------------------------------
7.37 MHz × (FRC Accuracy)% × (FRC Tuning)%
For example, if the device is operating at +125°C,
the FRC accuracy will be ±5%. If the TUN<5:0> bits
(see Register 9-4) are set to ‘b111111, the
Minimum Row Write Time is:
The basic sequence for RTSP programming is to set up
a Table Pointer, then do a series of TBLWTinstructions
to load the buffers. Programming is performed by set-
ting the control bits in the NVMCON register. A total of
64 TBLWTL and TBLWTH instructions are required to
load the instructions.
11064 Cycles
----------------------------------------------------------------------------------------------
TRW
=
= 1.435ms
7.37 MHz × (1 + 0.05) × (1 – 0.00375)
All of the table write operations are single-word writes
(two instruction cycles) because only the buffers are
and, the Maximum Row Write Time is:
written.
programming each row.
A
programming cycle is required for
11064 Cycles
7.37 MHz × (1 – 0.05) × (1 – 0.00375)
---------------------------------------------------------------------------------------------
=
TRW
= 1.586ms
Setting the WR bit (NVMCON<15>) starts the opera-
tion, and the WR bit is automatically cleared when the
operation is finished.
5.4
Control Registers
There are two SFRs used to read and write the
program Flash memory: NVMCON and NVMKEY.
The NVMCON register (Register 5-1) controls which
blocks are to be erased, which memory type is to be
programmed and the start of the programming cycle.
NVMKEY is a write-only register that is used for write
protection. To start a programming or erase sequence,
the user must consecutively write 0x55 and 0xAA to the
NVMKEY register. Refer to Section 5.3 “Programming
Operations” for further details.
DS70592A-page 60
Preliminary
© 2009 Microchip Technology Inc.
PIC24HJXXXGPX06A/X08A/X10A
REGISTER 5-1:
NVMCON: FLASH MEMORY CONTROL REGISTER
R/SO-0(1)
WR
R/W-0(1)
WREN
R/W-0(1)
WRERR
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
bit 15
bit 8
R/W-0(1)
bit 0
U-0
—
R/W-0(1)
ERASE
U-0
—
U-0
—
R/W-0(1)
R/W-0(1)
R/W-0(1)
NVMOP<3:0>(2)
bit 7
Legend:
SO = Settable only bit
W = Writable bit
‘1’ = Bit is set
R = Readable bit
-n = Value at POR
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15
WR: Write Control bit
1= Initiates a Flash memory program or erase operation. The operation is self-timed and the bit is
cleared by hardware once operation is complete
0= Program or erase operation is complete and inactive
bit 14
bit 13
WREN: Write Enable bit
1= Enable Flash program/erase operations
0= Inhibit Flash program/erase operations
WRERR: Write Sequence Error Flag bit
1= An improper program or erase sequence attempt or termination has occurred (bit is set
automatically on any set attempt of the WR bit)
0= The program or erase operation completed normally
bit 12-7
bit 6
Unimplemented: Read as ‘0’
ERASE: Erase/Program Enable bit
1= Perform the erase operation specified by NVMOP<3:0> on the next WR command
0= Perform the program operation specified by NVMOP<3:0> on the next WR command
bit 5-4
bit 3-0
Unimplemented: Read as ‘0’
NVMOP<3:0>: NVM Operation Select bits(2)
1111= Memory bulk erase operation (ERASE = 1) or no operation (ERASE = 0)
1110= Reserved
1101= Erase General Segment and FGS Configuration Register
(ERASE = 1) or no operation (ERASE = 0)
1100= Erase Secure Segment and FSS Configuration Register
(ERASE = 1) or no operation (ERASE = 0)
1011-0100= Reserved
0011= Memory word program operation (ERASE = 0) or no operation (ERASE = 1)
0010= Memory page erase operation (ERASE = 1) or no operation (ERASE = 0)
0001= Memory row program operation (ERASE = 0) or no operation (ERASE = 1)
0000= Program or erase a single Configuration register byte
Note 1: These bits can only be reset on POR.
2: All other combinations of NVMOP<3:0> are unimplemented.
© 2009 Microchip Technology Inc.
Preliminary
DS70592A-page 61
PIC24HJXXXGPX06A/X08A/X10A
4. Write the first 64 instructions from data RAM into
the program memory buffers (see Example 5-2).
5.4.1
PROGRAMMING ALGORITHM FOR
FLASH PROGRAM MEMORY
5. Write the program block to Flash memory:
The user can program one row of program Flash
memory at a time. To do this, it is necessary to erase
the 8-row erase page that contains the desired row.
The general process is:
a) Set the NVMOP bits to ‘0001’ to configure
for row programming. Clear the ERASE bit
and set the WREN bit.
b) Write 0x55 to NVMKEY.
c) Write 0xAA to NVMKEY.
1. Read eight rows of program memory
(512 instructions) and store in data RAM.
d) Set the WR bit. The programming cycle
begins and the CPU stalls for the duration of
the write cycle. When the write to Flash mem-
ory is done, the WR bit is cleared
automatically.
2. Update the program data in RAM with the
desired new data.
3. Erase the page (see Example 5-1):
a) Set the NVMOP bits (NVMCON<3:0>) to
‘0010’ to configure for block erase. Set the
ERASE (NVMCON<6>) and WREN
(NVMCON<14>) bits.
6. Repeat steps 4 and 5, using the next available
64 instructions from the block in data RAM by
incrementing the value in TBLPAG, until all
512 instructions are written back to Flash memory.
b) Write the starting address of the page to be
erased into the TBLPAG and W registers.
For protection against accidental operations, the write
initiate sequence for NVMKEY must be used to allow
any erase or program operation to proceed. After the
programming command has been executed, the user
must wait for the programming time until programming
is complete. The two instructions following the start of
the programming sequence should be NOPs, as shown
in Example 5-3.
c) Perform a dummy table write operation
(TBLWTL) to any address within the page
that needs to be erased.
d) Write 0x55 to NVMKEY.
e) Write 0xAA to NVMKEY.
f) Set the WR bit (NVMCON<15>). The erase
cycle begins and the CPU stalls for the dura-
tion of the erase cycle. When the erase is
done, the WR bit is cleared automatically.
EXAMPLE 5-1:
ERASING A PROGRAM MEMORY PAGE
; Set up NVMCON for block erase operation
MOV
MOV
#0x4042, W0
W0, NVMCON
;
; Initialize NVMCON
; Init pointer to row to be ERASED
MOV
MOV
MOV
#tblpage(PROG_ADDR), W0
W0, TBLPAG
#tbloffset(PROG_ADDR), W0
;
; Initialize PM Page Boundary SFR
; Initialize in-page EA<15:0> pointer
; Set base address of erase block
; Block all interrupts with priority <7
; for next 5 instructions
TBLWTL W0, [W0]
DISI
#5
MOV
MOV
MOV
MOV
BSET
NOP
NOP
#0x55, W0
W0, NVMKEY
#0xAA, W1
W1, NVMKEY
NVMCON, #WR
; Write the 55 key
;
; Write the AA key
; Start the erase sequence
; Insert two NOPs after the erase
; command is asserted
Note:
A program memory page erase operation
is set up by performing a dummy table
write (TBLWTL) operation to any address
within the page. This methodology is dif-
ferent from the page erase operation on
dsPIC30F/33F devices in which the erase
page was selected using a dedicated pair
of registers (NVMADRU and NVMADR).
DS70592A-page 62
Preliminary
© 2009 Microchip Technology Inc.
PIC24HJXXXGPX06A/X08A/X10A
EXAMPLE 5-2:
LOADING THE WRITE BUFFERS
; Set up NVMCON for row programming operations
MOV
MOV
#0x4001, W0
W0, NVMCON
;
; Initialize NVMCON
; Set up a pointer to the first program memory location to be written
; program memory selected, and writes enabled
MOV
MOV
MOV
#0x0000, W0
W0, TBLPAG
#0x6000, W0
;
; Initialize PM Page Boundary SFR
; An example program memory address
; Perform the TBLWT instructions to write the latches
; 0th_program_word
MOV
MOV
#LOW_WORD_0, W2
#HIGH_BYTE_0, W3
;
;
TBLWTL W2, [W0]
TBLWTH W3, [W0++]
; Write PM low word into program latch
; Write PM high byte into program latch
; 1st_program_word
MOV
MOV
#LOW_WORD_1, W2
#HIGH_BYTE_1, W3
;
;
TBLWTL W2, [W0]
TBLWTH W3, [W0++]
; Write PM low word into program latch
; Write PM high byte into program latch
;
2nd_program_word
MOV
MOV
#LOW_WORD_2, W2
#HIGH_BYTE_2, W3
;
;
TBLWTL W2, [W0]
TBLWTH W3, [W0++]
; Write PM low word into program latch
; Write PM high byte into program latch
•
•
•
; 63rd_program_word
MOV
MOV
#LOW_WORD_31, W2
#HIGH_BYTE_31, W3
;
;
TBLWTL W2, [W0]
TBLWTH W3, [W0++]
; Write PM low word into program latch
; Write PM high byte into program latch
EXAMPLE 5-3:
INITIATING A PROGRAMMING SEQUENCE
DISI
#5
; Block all interrupts with priority <7
; for next 5 instructions
MOV
MOV
MOV
MOV
BSET
NOP
NOP
#0x55, W0
W0, NVMKEY
#0xAA, W1
W1, NVMKEY
NVMCON, #WR
; Write the 55 key
;
; Write the AA key
; Start the erase sequence
; Insert two NOPs after the
; erase command is asserted
© 2009 Microchip Technology Inc.
Preliminary
DS70592A-page 63
PIC24HJXXXGPX06A/X08A/X10A
NOTES:
DS70592A-page 64
Preliminary
© 2009 Microchip Technology Inc.
PIC24HJXXXGPX06A/X08A/X10A
Any active source of Reset will make the SYSRST sig-
nal active. Many registers associated with the CPU and
6.0
RESET
Note:
This data sheet summarizes the features
of the PIC24HJXXXGPX06A/X08A/X10A
peripherals are forced to a known Reset state. Most
registers are unaffected by a Reset; their status is
unknown on POR and unchanged by all other Resets.
family of devices. However, it is not
intended to be a comprehensive reference
source. To complement the information in
this data sheet, refer to the “PIC24H
Family Reference Manual”, Section 8.
“Reset” (DS70229), which is available
Note:
Refer to the specific peripheral or CPU
section of this manual for register Reset
states.
All types of device Reset will set a corresponding status
bit in the RCON register to indicate the type of Reset
(see Register 6-1). A POR will clear all bits, except for
the POR bit (RCON<0>), that are set. The user can set
or clear any bit at any time during code execution. The
RCON bits only serve as status bits. Setting a particular
Reset status bit in software does not cause a device
Reset to occur.
from
the
Microchip
website
(www.microchip.com).
The Reset module combines all Reset sources and
controls the device Master Reset Signal, SYSRST. The
following is a list of device Reset sources:
• POR: Power-on Reset
• BOR: Brown-out Reset
The RCON register also has other bits associated with
the Watchdog Timer and device power-saving states.
The function of these bits is discussed in other sections
of this manual.
• MCLR: Master Clear Pin Reset
• SWR: RESETInstruction
• WDT: Watchdog Timer Reset
• TRAPR: Trap Conflict Reset
Note:
The status bits in the RCON register
should be cleared after they are read so
that the next RCON register value after a
device Reset will be meaningful.
• IOPUWR: Illegal Opcode and Uninitialized W
Register Reset
A simplified block diagram of the Reset module is
shown in Figure 6-1.
FIGURE 6-1:
RESET SYSTEM BLOCK DIAGRAM
RESETInstruction
Glitch Filter
MCLR
WDT
Module
Sleep or Idle
BOR
Internal
Regulator
SYSRST
VDD
POR
VDD Rise
Detect
Trap Conflict
Illegal Opcode
Uninitialized W Register
© 2009 Microchip Technology Inc.
Preliminary
DS70592A-page 65
PIC24HJXXXGPX06A/X08A/X10A
(1)
REGISTER 6-1:
R/W-0
RCON: RESET CONTROL REGISTER
R/W-0
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
R/W-0
VREGS(3)
TRAPR
IOPUWR
bit 15
bit 8
R/W-0
EXTR
R/W-0
SWR
R/W-0
SWDTEN(2)
R/W-0
WDTO
R/W-0
R/W-0
IDLE
R/W-1
BOR
R/W-1
POR
SLEEP
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
-n = Value at POR
bit 15
bit 14
TRAPR: Trap Reset Flag bit
1= A Trap Conflict Reset has occurred
0= A Trap Conflict Reset has not occurred
IOPUWR: Illegal Opcode or Uninitialized W Access Reset Flag bit
1= An illegal opcode detection, an illegal address mode or uninitialized W register used as an
Address Pointer caused a Reset
0= An illegal opcode or uninitialized W Reset has not occurred
bit 13-9
bit 8
Unimplemented: Read as ‘0’
VREGS: Voltage Regulator Standby During Sleep bit(3)
1= Voltage Regulator is active during Sleep mode
0= Voltage Regulator goes into standby mode during Sleep
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
EXTR: External Reset (MCLR) Pin bit
1= A Master Clear (pin) Reset has occurred
0= A Master Clear (pin) Reset has not occurred
SWR: Software Reset (Instruction) Flag bit
1= A RESETinstruction has been executed
0= A RESETinstruction has not been executed
SWDTEN: Software Enable/Disable of WDT bit(2)
1= WDT is enabled
0= WDT is disabled
WDTO: Watchdog Timer Time-out Flag bit
1= WDT time-out has occurred
0= WDT time-out has not occurred
SLEEP: Wake-up from Sleep Flag bit
1= Device has been in Sleep mode
0= Device has not been in Sleep mode
IDLE: Wake-up from Idle Flag bit
1= Device was in Idle mode
0= Device was not in Idle mode
BOR: Brown-out Reset Flag bit
1= A Brown-out Reset has occurred
0= A Brown-out Reset has not occurred
Note 1: All of the Reset status bits may be set or cleared in software. Setting one of these bits in software does not
cause a device Reset.
2: If the FWDTEN Configuration bit is ‘1’ (unprogrammed), the WDT is always enabled, regardless of the
SWDTEN bit setting.
3: For PIC24HJ256GPX06A/X08A/X10A devices, this bit is unimplemented and reads back programmed
value.
DS70592A-page 66
Preliminary
© 2009 Microchip Technology Inc.
PIC24HJXXXGPX06A/X08A/X10A
(1)
REGISTER 6-1:
bit 0
RCON: RESET CONTROL REGISTER
POR: Power-on Reset Flag bit
1= A Power-on Reset has occurred
0= A Power-on Reset has not occurred
Note 1: All of the Reset status bits may be set or cleared in software. Setting one of these bits in software does not
cause a device Reset.
2: If the FWDTEN Configuration bit is ‘1’ (unprogrammed), the WDT is always enabled, regardless of the
SWDTEN bit setting.
3: For PIC24HJ256GPX06A/X08A/X10A devices, this bit is unimplemented and reads back programmed
value.
© 2009 Microchip Technology Inc.
Preliminary
DS70592A-page 67
PIC24HJXXXGPX06A/X08A/X10A
TABLE 6-1:
RESET FLAG BIT OPERATION
Flag Bit Setting Event
Trap conflict event
Clearing Event
TRAPR (RCON<15>)
IOPUWR (RCON<14>)
POR, BOR
POR, BOR
Illegal opcode or uninitialized
W register access
EXTR (RCON<7>)
SWR (RCON<6>)
WDTO (RCON<4>)
SLEEP (RCON<3>)
IDLE (RCON<2>)
BOR (RCON<1>)
POR (RCON<0>)
MCLR Reset
POR
RESETinstruction
WDT time-out
POR, BOR
PWRSAVinstruction, POR, BOR
PWRSAV #SLEEPinstruction
PWRSAV #IDLEinstruction
BOR, POR
POR, BOR
POR, BOR
—
—
POR
Note: All Reset flag bits may be set or cleared by the user software.
6.1
Clock Source Selection at Reset
6.2
Device Reset Times
If clock switching is enabled, the system clock source at
device Reset is chosen, as shown in Table 6-2. If clock
switching is disabled, the system clock source is always
selected according to the oscillator Configuration bits.
Refer to Section 9.0 “Oscillator Configuration” for
further details.
The Reset times for various types of device Reset are
summarized in Table 6-3. The system Reset signal is
released after the POR and PWRT delay times expire.
The time at which the device actually begins to execute
code also depends on the system oscillator delays,
which include the Oscillator Start-up Timer (OST) and
the PLL lock time. The OST and PLL lock times occur
in parallel with the applicable reset delay times.
TABLE 6-2:
OSCILLATOR SELECTION vs.
TYPE OF RESET (CLOCK
SWITCHING ENABLED)
The FSCM delay determines the time at which the
FSCM begins to monitor the system clock source after
the reset signal is released.
Reset Type
Clock Source Determinant
POR
BOR
Oscillator Configuration bits
(FNOSC<2:0>)
MCLR
WDTR
SWR
COSC Control bits
(OSCCON<14:12>)
DS70592A-page 68
Preliminary
© 2009 Microchip Technology Inc.
PIC24HJXXXGPX06A/X08A/X10A
TABLE 6-3:
Reset Type
POR
RESET DELAY TIMES FOR VARIOUS DEVICE RESETS
System Clock
Delay
FSCM
Delay
Clock Source
SYSRST Delay
Notes
1, 2, 3
EC, FRC, LPRC
ECPLL, FRCPLL
XT, HS, SOSC
XTPLL, HSPLL
Any Clock
TPOR + TSTARTUP + TRST
—
—
TFSCM
TFSCM
TFSCM
—
TPOR + TSTARTUP + TRST
TLOCK
1, 2, 3, 5, 6
TPOR + TSTARTUP + TRST
TOST
1, 2, 3, 4, 6
TPOR + TSTARTUP + TRST
TOST + TLOCK
1, 2, 3, 4, 5, 6
MCLR
TRST
TRST
TRST
TRST
TRST
TRST
—
—
—
—
—
—
3
3
3
3
3
3
WDT
Any Clock
—
Software
Any clock
—
Illegal Opcode
Uninitialized W
Trap Conflict
Any Clock
—
Any Clock
—
Any Clock
—
Note 1: TPOR = Power-on Reset delay (10 μs nominal).
2: TSTARTUP = Conditional POR delay of 20 μs nominal (if on-chip regulator is enabled) or 64 ms nominal
Power-up Timer delay (if regulator is disabled). TSTARTUP is also applied to all returns from powered-down
states, including waking from Sleep mode, only if the regulator is enabled.
3: TRST = Internal state Reset time (20 μs nominal).
4: TOST = Oscillator Start-up Timer. A 10-bit counter counts 1024 oscillator periods before releasing the
oscillator clock to the system.
5: TLOCK = PLL lock time (20 μs nominal).
6: TFSCM = Fail-Safe Clock Monitor delay (100 μs nominal).
6.2.1
POR AND LONG OSCILLATOR
START-UP TIMES
6.2.2.1
FSCM Delay for Crystal and PLL
Clock Sources
The oscillator start-up circuitry and its associated delay
timers are not linked to the device Reset delays that
occur at power-up. Some crystal circuits (especially
low-frequency crystals) have a relatively long start-up
time. Therefore, one or more of the following conditions
is possible after the Reset signal is released:
When the system clock source is provided by a crystal
oscillator and/or the PLL, a small delay, TFSCM, is auto-
matically inserted after the POR and PWRT delay
times. The FSCM does not begin to monitor the system
clock source until this delay expires. The FSCM delay
time is nominally 500 μs and provides additional time
for the oscillator and/or PLL to stabilize. In most cases,
the FSCM delay prevents an oscillator failure trap at a
device Reset when the PWRT is disabled.
• The oscillator circuit has not begun to oscillate.
• The Oscillator Start-up Timer has not expired (if a
crystal oscillator is used).
• The PLL has not achieved a lock (if PLL is used).
6.3
Special Function Register Reset
States
The device will not begin to execute code until a valid
clock source has been released to the system. There-
fore, the oscillator and PLL start-up delays must be
considered when the Reset delay time must be known.
Most of the Special Function Registers (SFRs) associ-
ated with the CPU and peripherals are reset to a
particular value at a device Reset. The SFRs are
grouped by their peripheral or CPU function and their
Reset values are specified in each section of this
manual.
6.2.2
FAIL-SAFE CLOCK MONITOR
(FSCM) AND DEVICE RESETS
If the FSCM is enabled, it begins to monitor the system
clock source when the Reset signal is released. If a
valid clock source is not available at this time, the
device automatically switches to the FRC oscillator and
the user can switch to the desired crystal oscillator in
the Trap Service Routine.
The Reset value for each SFR does not depend on the
type of Reset, with the exception of two registers. The
Reset value for the Reset Control register, RCON,
depends on the type of device Reset. The Reset value
for the Oscillator Control register, OSCCON, depends
on the type of Reset and the programmed values of the
oscillator Configuration bits in the FOSC Configuration
register.
© 2009 Microchip Technology Inc.
Preliminary
DS70592A-page 69
PIC24HJXXXGPX06A/X08A/X10A
NOTES:
DS70592A-page 70
Preliminary
© 2009 Microchip Technology Inc.
PIC24HJXXXGPX06A/X08A/X10A
7.1.1
ALTERNATE VECTOR TABLE
7.0
INTERRUPT CONTROLLER
The Alternate Interrupt Vector Table (AIVT) is located
after the IVT, as shown in Figure 7-1. Access to the
AIVT is provided by the ALTIVT control bit
(INTCON2<15>). If the ALTIVT bit is set, all interrupt
and exception processes use the alternate vectors
instead of the default vectors. The alternate vectors are
organized in the same manner as the default vectors.
Note:
This data sheet summarizes the features
of the PIC24HJXXXGPX06A/X08A/X10A
family of devices. However, it is not
intended to be a comprehensive reference
source. To complement the information in
this data sheet, refer to the “PIC24H
Family Reference Manual”, Section 6.
“Interrupts” (DS70224), which is
available from the Microchip website
(www.microchip.com).
The AIVT supports debugging by providing a means to
switch between an application and a support environ-
ment without requiring the interrupt vectors to be
reprogrammed. This feature also enables switching
between applications for evaluation of different soft-
ware algorithms at run time. If the AIVT is not needed,
the AIVT should be programmed with the same
addresses used in the IVT.
The PIC24HJXXXGPX06A/X08A/X10A interrupt con-
troller reduces the numerous peripheral interrupt
request signals to a single interrupt request signal to
the PIC24HJXXXGPX06A/X08A/X10A CPU. It has the
following features:
• Up to 8 processor exceptions and software traps
• 7 user-selectable priority levels
7.2
Reset Sequence
A device Reset is not a true exception because the
interrupt controller is not involved in the Reset process.
The PIC24HJXXXGPX06A/X08A/X10A device clears
its registers in response to a Reset which forces the PC
to zero. The digital signal controller then begins pro-
gram execution at location 0x000000. The user pro-
grams a GOTOinstruction at the Reset address which
redirects program execution to the appropriate start-up
routine.
• Interrupt Vector Table (IVT) with up to 118 vectors
• A unique vector for each interrupt or exception
source
• Fixed priority within a specified user priority level
• Alternate Interrupt Vector Table (AIVT) for debug
support
• Fixed interrupt entry and return latencies
7.1
Interrupt Vector Table
Note: Any unimplemented or unused vector
locations in the IVT and AIVT should be
programmed with the address of a default
interrupt handler routine that contains a
RESETinstruction.
The Interrupt Vector Table (IVT) is shown in Figure 7-1.
The IVT resides in program memory, starting at location
000004h. The IVT contains 126 vectors consisting of
8 nonmaskable trap vectors plus up to 118 sources of
interrupt. In general, each interrupt source has its own
vector. Each interrupt vector contains a 24-bit wide
address. The value programmed into each interrupt
vector location is the starting address of the associated
Interrupt Service Routine (ISR).
Interrupt vectors are prioritized in terms of their natural
priority; this priority is linked to their position in the
vector table. All other things being equal, lower
addresses have a higher natural priority. For example,
the interrupt associated with vector 0 will take priority
over interrupts at any other vector address.
PIC24HJXXXGPX06A/X08A/X10A devices implement
up to 61 unique interrupts and 5 nonmaskable traps.
These are summarized in Table 7-1 and Table 7-2.
© 2009 Microchip Technology Inc.
Preliminary
DS70592A-page 71
PIC24HJXXXGPX06A/X08A/X10A
FIGURE 7-1:
PIC24HJXXXGPX06A/X08A/X10A INTERRUPT VECTOR TABLE
Reset – GOTOInstruction
Reset – GOTOAddress
Reserved
0x000000
0x000002
0x000004
Oscillator Fail Trap Vector
Address Error Trap Vector
Stack Error Trap Vector
Math Error Trap Vector
DMA Error Trap Vector
Reserved
Reserved
Interrupt Vector 0
Interrupt Vector 1
~
0x000014
~
~
Interrupt Vector 52
Interrupt Vector 53
Interrupt Vector 54
~
0x00007C
0x00007E
0x000080
Interrupt Vector Table (IVT)(1)
~
~
Interrupt Vector 116
Interrupt Vector 117
Reserved
0x0000FC
0x0000FE
0x000100
0x000102
Reserved
Reserved
Oscillator Fail Trap Vector
Address Error Trap Vector
Stack Error Trap Vector
Math Error Trap Vector
DMA Error Trap Vector
Reserved
Reserved
Interrupt Vector 0
Interrupt Vector 1
~
0x000114
~
~
Alternate Interrupt Vector Table (AIVT)(1)
Interrupt Vector 52
Interrupt Vector 53
Interrupt Vector 54
~
0x00017C
0x00017E
0x000180
~
~
Interrupt Vector 116
Interrupt Vector 117
Start of Code
0x0001FE
0x000200
Note 1: See Table 7-1 for the list of implemented interrupt vectors.
DS70592A-page 72
Preliminary
© 2009 Microchip Technology Inc.
PIC24HJXXXGPX06A/X08A/X10A
TABLE 7-1:
INTERRUPT VECTORS
Interrupt
Request(IRQ)
Number
Vector
Number
IVT Address
AIVT Address
Interrupt Source
INT0 – External Interrupt 0
8
0
0x000014
0x000016
0x000018
0x00001A
0x00001C
0x00001E
0x000020
0x000022
0x000024
0x000026
0x000028
0x00002A
0x00002C
0x00002E
0x000030
0x000032
0x000034
0x000036
0x000038
0x00003A
0x00003C
0x00003E
0x000040
0x000042
0x000044
0x000046
0x000048
0x00004A
0x00004C
0x00004E
0x000050
0x000052
0x000054
0x000056
0x000058
0x00005A
0x00005C
0x00005E
0x000060
0x000062
0x000064
0x000066
0x000068
0x00006A
0x00006C
0x00006E
0x000114
0x000116
0x000118
0x00011A
0x00011C
0x00011E
0x000120
0x000122
0x000124
0x000126
0x000128
0x00012A
0x00012C
0x00012E
0x000130
0x000132
0x000134
0x000136
0x000138
0x00013A
0x00013C
0x00013E
0x000140
0x000142
0x000144
0x000146
0x000148
0x00014A
0x00014C
0x00014E
0x000150
0x000152
0x000154
0x000156
0x000158
0x00015A
0x00015C
0x00015E
0x000160
0x000162
0x000164
0x000166
0x000168
0x00016A
0x00016C
0x00016E
9
1
IC1 – Input Compare 1
OC1 – Output Compare 1
T1 – Timer1
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
2
3
4
DMA0 – DMA Channel 0
IC2 – Input Capture 2
OC2 – Output Compare 2
T2 – Timer2
5
6
7
8
T3 – Timer3
9
SPI1E – SPI1 Error
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
SPI1 – SPI1 Transfer Done
U1RX – UART1 Receiver
U1TX – UART1 Transmitter
ADC1 – Analog-to-Digital Converter 1
DMA1 – DMA Channel 1
Reserved
SI2C1 – I2C1 Slave Events
MI2C1 – I2C1 Master Events
Reserved
CN - Change Notification Interrupt
INT1 – External Interrupt 1
ADC2 – Analog-to-Digital Converter 2
IC7 – Input Capture 7
IC8 – Input Capture 8
DMA2 – DMA Channel 2
OC3 – Output Compare 3
OC4 – Output Compare 4
T4 – Timer4
T5 – Timer5
INT2 – External Interrupt 2
U2RX – UART2 Receiver
U2TX – UART2 Transmitter
SPI2E – SPI2 Error
SPI1 – SPI1 Transfer Done
C1RX – ECAN1 Receive Data Ready
C1 – ECAN1 Event
DMA3 – DMA Channel 3
IC3 – Input Capture 3
IC4 – Input Capture 4
IC5 – Input Capture 5
IC6 – Input Capture 6
OC5 – Output Compare 5
OC6 – Output Compare 6
OC7 – Output Compare 7
OC8 – Output Compare 8
Reserved
© 2009 Microchip Technology Inc.
Preliminary
DS70592A-page 73
PIC24HJXXXGPX06A/X08A/X10A
TABLE 7-1:
INTERRUPT VECTORS (CONTINUED)
Interrupt
Vector
Number
Request(IRQ)
Number
IVT Address
AIVT Address
Interrupt Source
DMA4 – DMA Channel 4
54
55
46
47
0x000070
0x000072
0x000074
0x000076
0x000078
0x00007A
0x00007C
0x00007E
0x000080
0x000082
0x000084
0x000170
0x000172
0x000174
0x000176
0x000178
0x00017A
0x00017C
0x00017E
0x000180
0x000182
0x000184
T6 – Timer6
56
48
T7 – Timer7
57
49
SI2C2 – I2C2 Slave Events
MI2C2 – I2C2 Master Events
T8 – Timer8
58
50
59
51
60
52
T9 – Timer9
61
53
INT3 – External Interrupt 3
INT4 – External Interrupt 4
C2RX – ECAN2 Receive Data Ready
C2 – ECAN2 Event
Reserved
62
54
63
55
64
56
65-68
57-60
0x000086-
0x00008C
0x000186-
0x00018C
69
61
0x00008E
0x00018E
DMA5 – DMA Channel 5
Reserved
70-72
62-64
0x000090-
0x000094
0x000190-
0x000194
73
74
65
66
0x000096
0x000098
0x00009A
0x00009C
0x00009E
0x0000A0
0x0000A2
0x000196
0x000198
0x00019A
0x00019C
0x00019E
0x0001A0
0x0001A2
U1E – UART1 Error
U2E – UART2 Error
75
67
Reserved
76
68
DMA6 – DMA Channel 6
DMA7 – DMA Channel 7
C1TX – ECAN1 Transmit Data Request
C2TX – ECAN2 Transmit Data Request
Reserved
77
69
78
70
79
71
80-125
72-117
0x0000A4-
0x0000FE
0x0001A4-
0x0001FE
TABLE 7-2:
TRAP VECTORS
Vector Number
IVT Address
AIVT Address
Trap Source
Reserved
0
1
2
3
4
5
6
7
0x000004
0x000006
0x000008
0x00000A
0x00000C
0x00000E
0x000010
0x000012
0x000104
0x000106
0x000108
0x00010A
0x00010C
0x00010E
0x000110
0x000112
Oscillator Failure
Address Error
Stack Error
Math Error
DMA Error Trap
Reserved
Reserved
DS70592A-page 74
Preliminary
© 2009 Microchip Technology Inc.
PIC24HJXXXGPX06A/X08A/X10A
The IPC registers are used to set the interrupt priority
level for each source of interrupt. Each user interrupt
source can be assigned to one of eight priority levels.
7.3
Interrupt Control and Status
Registers
PIC24HJXXXGPX06A/X08A/X10A devices implement
a total of 30 registers for the interrupt controller:
The INTTREG register contains the associated inter-
rupt vector number and the new CPU interrupt priority
level, which are latched into vector number (VEC-
NUM<6:0>) and Interrupt level (ILR<3:0>) bit fields in
the INTTREG register. The new interrupt priority level
is the priority of the pending interrupt.
• INTCON1
• INTCON2
• IFS0 through IFS4
• IEC0 through IEC4
• IPC0 through IPC17
• INTTREG
The interrupt sources are assigned to the IFSx, IECx
and IPCx registers in the same sequence that they are
listed in Table 7-1. For example, the INT0 (External
Interrupt 0) is shown as having vector number 8 and a
natural order priority of 0. Thus, the INT0IF bit is found
in IFS0<0>, the INT0IE bit in IEC0<0>, and the INT0IP
bits in the first position of IPC0 (IPC0<2:0>).
Global interrupt control functions are controlled from
INTCON1 and INTCON2. INTCON1 contains the Inter-
rupt Nesting Disable (NSTDIS) bit as well as the control
and status flags for the processor trap sources. The
INTCON2 register controls the external interrupt
request signal behavior and the use of the Alternate
Interrupt Vector Table.
Although they are not specifically part of the interrupt
control hardware, two of the CPU Control registers con-
tain bits that control interrupt functionality. The CPU
STATUS register, SR, contains the IPL<2:0> bits
(SR<7:5>). These bits indicate the current CPU inter-
rupt priority level. The user can change the current
CPU priority level by writing to the IPL bits.
The IFS registers maintain all of the interrupt request
flags. Each source of interrupt has a Status bit, which is
set by the respective peripherals or external signal and
is cleared via software.
The IEC registers maintain all of the interrupt enable
bits. These control bits are used to individually enable
interrupts from the peripherals or external signals.
The CORCON register contains the IPL3 bit which,
together with IPL<2:0>, also indicates the current CPU
priority level. IPL3 is a read-only bit so that trap events
cannot be masked by the user software.
All Interrupt registers are described in Register 7-1,
SR: CPU STATUS Register(1) through Register 7-32,
IPC17: Interrupt Priority Control Register 17, in the
following pages.
© 2009 Microchip Technology Inc.
Preliminary
DS70592A-page 75
PIC24HJXXXGPX06A/X08A/X10A
(1)
REGISTER 7-1:
SR: CPU STATUS REGISTER
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
R/W-0
DC
bit 15
bit 8
R/W-0(3)
IPL2(2)
bit 7
R/W-0(3)
IPL1(2)
R/W-0(3)
IPL0(2)
R-0
RA
R/W-0
N
R/W-0
OV
R/W-0
Z
R/W-0
C
bit 0
Legend:
C = Clear only bit
S = Set only bit
‘1’ = Bit is set
R = Readable bit
W = Writable bit
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
-n = Value at POR
x = Bit is unknown
bit 7-5
IPL<2:0>: CPU Interrupt Priority Level Status bits(2)
111= CPU Interrupt Priority Level is 7 (15), user interrupts disabled
110= CPU Interrupt Priority Level is 6 (14)
101= CPU Interrupt Priority Level is 5 (13)
100= CPU Interrupt Priority Level is 4 (12)
011= CPU Interrupt Priority Level is 3 (11)
010= CPU Interrupt Priority Level is 2 (10)
001= CPU Interrupt Priority Level is 1 (9)
000= CPU Interrupt Priority Level is 0 (8)
Note 1: For complete register details, see Register 3-1, SR: CPU STATUS REGISTER.
2: The IPL<2:0> bits are concatenated with the IPL<3> bit (CORCON<3>) to form the CPU Interrupt Priority
Level. The value in parentheses indicates the IPL if IPL<3> = 1. User interrupts are disabled when
IPL<3> = 1.
3: The IPL<2:0> Status bits are read-only when NSTDIS (INTCON1<15>) = 1.
(1)
REGISTER 7-2:
CORCON: CORE CONTROL REGISTER
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
bit 15
bit 8
bit 0
U-0
—
U-0
—
U-0
—
U-0
—
R/C-0
IPL3(2)
R/W-0
PSV
U-0
—
U-0
—
bit 7
Legend:
C = Clear only bit
W = Writable bit
‘x = Bit is unknown
R = Readable bit
0’ = Bit is cleared
-n = Value at POR
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
bit 3
IPL3: CPU Interrupt Priority Level Status bit 3(2)
1= CPU interrupt priority level is greater than 7
0= CPU interrupt priority level is 7 or less
Note 1: For complete register details, see Register 3-2, CORCON: CORE CONTROL REGISTER.
2: The IPL3 bit is concatenated with the IPL<2:0> bits (SR<7:5>) to form the CPU Interrupt Priority Level.
DS70592A-page 76
Preliminary
© 2009 Microchip Technology Inc.
PIC24HJXXXGPX06A/X08A/X10A
REGISTER 7-3:
INTCON1: INTERRUPT CONTROL REGISTER 1
R/W-0
NSTDIS
bit 15
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
bit 8
bit 0
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
U-0
—
DIV0ERR
DMACERR MATHERR ADDRERR
STKERR
OSCFAIL
bit 7
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
-n = Value at POR
bit 15
NSTDIS: Interrupt Nesting Disable bit
1= Interrupt nesting is disabled
0= Interrupt nesting is enabled
bit 14-7
bit 6
Unimplemented: Read as ‘0’
DIV0ERR: Arithmetic Error Status bit
1= Math error trap was caused by a divide by zero
0= Math error trap was not caused by a divide by zero
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
DMACERR: DMA Controller Error Status bit
1= DMA controller error trap has occurred
0= DMA controller error trap has not occurred
MATHERR: Arithmetic Error Status bit
1= Math error trap has occurred
0= Math error trap has not occurred
ADDRERR: Address Error Trap Status bit
1= Address error trap has occurred
0= Address error trap has not occurred
STKERR: Stack Error Trap Status bit
1= Stack error trap has occurred
0= Stack error trap has not occurred
OSCFAIL: Oscillator Failure Trap Status bit
1= Oscillator failure trap has occurred
0= Oscillator failure trap has not occurred
Unimplemented: Read as ‘0’
© 2009 Microchip Technology Inc.
Preliminary
DS70592A-page 77
PIC24HJXXXGPX06A/X08A/X10A
REGISTER 7-4:
INTCON2: INTERRUPT CONTROL REGISTER 2
R/W-0
ALTIVT
bit 15
R-0
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
DISI
bit 8
U-0
—
U-0
—
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
INT4EP
INT3EP
INT2EP
INT1EP
INT0EP
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15
bit 14
ALTIVT: Enable Alternate Interrupt Vector Table bit
1= Use alternate vector table
0= Use standard (default) vector table
DISI: DISIInstruction Status bit
1= DISIinstruction is active
0= DISIinstruction is not active
bit 13-5
bit 4
Unimplemented: Read as ‘0’
INT4EP: External Interrupt 4 Edge Detect Polarity Select bit
1= Interrupt on negative edge
0= Interrupt on positive edge
bit 3
bit 2
bit 1
bit 0
INT3EP: External Interrupt 3 Edge Detect Polarity Select bit
1= Interrupt on negative edge
0= Interrupt on positive edge
INT2EP: External Interrupt 2 Edge Detect Polarity Select bit
1= Interrupt on negative edge
0= Interrupt on positive edge
INT1EP: External Interrupt 1 Edge Detect Polarity Select bit
1= Interrupt on negative edge
0= Interrupt on positive edge
INT0EP: External Interrupt 0 Edge Detect Polarity Select bit
1= Interrupt on negative edge
0= Interrupt on positive edge
DS70592A-page 78
Preliminary
© 2009 Microchip Technology Inc.
PIC24HJXXXGPX06A/X08A/X10A
REGISTER 7-5:
IFS0: INTERRUPT FLAG STATUS REGISTER 0
U-0
—
R/W-0
R/W-0
AD1IF
R/W-0
R/W-0
R/W-0
SPI1IF
R/W-0
R/W-0
T3IF
DMA1IF
U1TXIF
U1RXIF
SPI1EIF
bit 15
bit 8
R/W-0
T2IF
R/W-0
OC2IF
R/W-0
IC2IF
R/W-0
R/W-0
T1IF
R/W-0
OC1IF
R/W-0
IC1IF
R/W-0
INT0IF
DMA01IF
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15
bit 14
Unimplemented: Read as ‘0’
DMA1IF: DMA Channel 1 Data Transfer Complete Interrupt Flag Status bit
1= Interrupt request has occurred
0= Interrupt request has not occurred
bit 13
bit 12
bit 11
bit 10
bit 9
AD1IF: ADC1 Conversion Complete Interrupt Flag Status bit
1= Interrupt request has occurred
0= Interrupt request has not occurred
U1TXIF: UART1 Transmitter Interrupt Flag Status bit
1= Interrupt request has occurred
0= Interrupt request has not occurred
U1RXIF: UART1 Receiver Interrupt Flag Status bit
1= Interrupt request has occurred
0= Interrupt request has not occurred
SPI1IF: SPI1 Event Interrupt Flag Status bit
1= Interrupt request has occurred
0= Interrupt request has not occurred
SPI1EIF: SPI1 Fault Interrupt Flag Status bit
1= Interrupt request has occurred
0= Interrupt request has not occurred
bit 8
T3IF: Timer3 Interrupt Flag Status bit
1= Interrupt request has occurred
0= Interrupt request has not occurred
bit 7
T2IF: Timer2 Interrupt Flag Status bit
1= Interrupt request has occurred
0= Interrupt request has not occurred
bit 6
OC2IF: Output Compare Channel 2 Interrupt Flag Status bit
1= Interrupt request has occurred
0= Interrupt request has not occurred
bit 5
IC2IF: Input Capture Channel 2 Interrupt Flag Status bit
1= Interrupt request has occurred
0= Interrupt request has not occurred
bit 4
DMA01IF: DMA Channel 0 Data Transfer Complete Interrupt Flag Status bit
1= Interrupt request has occurred
0= Interrupt request has not occurred
bit 3
T1IF: Timer1 Interrupt Flag Status bit
1= Interrupt request has occurred
0= Interrupt request has not occurred
© 2009 Microchip Technology Inc.
Preliminary
DS70592A-page 79
PIC24HJXXXGPX06A/X08A/X10A
REGISTER 7-5:
IFS0: INTERRUPT FLAG STATUS REGISTER 0 (CONTINUED)
bit 2
bit 1
bit 0
OC1IF: Output Compare Channel 1 Interrupt Flag Status bit
1= Interrupt request has occurred
0= Interrupt request has not occurred
IC1IF: Input Capture Channel 1 Interrupt Flag Status bit
1= Interrupt request has occurred
0= Interrupt request has not occurred
INT0IF: External Interrupt 0 Flag Status bit
1= Interrupt request has occurred
0= Interrupt request has not occurred
DS70592A-page 80
Preliminary
© 2009 Microchip Technology Inc.
PIC24HJXXXGPX06A/X08A/X10A
REGISTER 7-6:
IFS1: INTERRUPT FLAG STATUS REGISTER 1
R/W-0
U2TXIF
bit 15
R/W-0
R/W-0
INT2IF
R/W-0
T5IF
R/W-0
T4IF
R/W-0
OC4IF
R/W-0
OC3IF
R/W-0
U2RXIF
DMA21IF
bit 8
R/W-0
IC8IF
R/W-0
IC7IF
R/W-0
AD2IF
R/W-0
INT1IF
R/W-0
CNIF
U-0
—
R/W-0
R/W-0
MI2C1IF
SI2C1IF
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15
bit 14
bit 13
bit 12
bit 11
bit 10
bit 9
U2TXIF: UART2 Transmitter Interrupt Flag Status bit
1= Interrupt request has occurred
0= Interrupt request has not occurred
U2RXIF: UART2 Receiver Interrupt Flag Status bit
1= Interrupt request has occurred
0= Interrupt request has not occurred
INT2IF: External Interrupt 2 Flag Status bit
1= Interrupt request has occurred
0= Interrupt request has not occurred
T5IF: Timer5 Interrupt Flag Status bit
1= Interrupt request has occurred
0= Interrupt request has not occurred
T4IF: Timer4 Interrupt Flag Status bit
1= Interrupt request has occurred
0= Interrupt request has not occurred
OC4IF: Output Compare Channel 4 Interrupt Flag Status bit
1= Interrupt request has occurred
0= Interrupt request has not occurred
OC3IF: Output Compare Channel 3 Interrupt Flag Status bit
1= Interrupt request has occurred
0= Interrupt request has not occurred
bit 8
DMA21IF: DMA Channel 2 Data Transfer Complete Interrupt Flag Status bit
1= Interrupt request has occurred
0= Interrupt request has not occurred
bit 7
IC8IF: Input Capture Channel 8 Interrupt Flag Status bit
1= Interrupt request has occurred
0= Interrupt request has not occurred
bit 6
IC7IF: Input Capture Channel 7 Interrupt Flag Status bit
1= Interrupt request has occurred
0= Interrupt request has not occurred
bit 5
AD2IF: ADC2 Conversion Complete Interrupt Flag Status bit
1= Interrupt request has occurred
0= Interrupt request has not occurred
bit 4
INT1IF: External Interrupt 1 Flag Status bit
1= Interrupt request has occurred
0= Interrupt request has not occurred
© 2009 Microchip Technology Inc.
Preliminary
DS70592A-page 81
PIC24HJXXXGPX06A/X08A/X10A
REGISTER 7-6:
IFS1: INTERRUPT FLAG STATUS REGISTER 1 (CONTINUED)
bit 3
CNIF: Input Change Notification Interrupt Flag Status bit
1= Interrupt request has occurred
0= Interrupt request has not occurred
bit 2
bit 1
Unimplemented: Read as ‘0’
MI2C1IF: I2C1 Master Events Interrupt Flag Status bit
1= Interrupt request has occurred
0= Interrupt request has not occurred
bit 0
SI2C1IF: I2C1 Slave Events Interrupt Flag Status bit
1= Interrupt request has occurred
0= Interrupt request has not occurred
DS70592A-page 82
Preliminary
© 2009 Microchip Technology Inc.
PIC24HJXXXGPX06A/X08A/X10A
REGISTER 7-7:
IFS2: INTERRUPT FLAG STATUS REGISTER 2
R/W-0
T6IF
R/W-0
U-0
—
R/W-0
OC8IF
R/W-0
OC7IF
R/W-0
OC6IF
R/W-0
OC5IF
R/W-0
IC6IF
DMA4IF
bit 15
bit 8
R/W-0
IC5IF
R/W-0
IC4IF
R/W-0
IC3IF
R/W-0
R/W-0
C1IF
R/W-0
R/W-0
SPI2IF
R/W-0
DMA3IF
C1RXIF
SPI2EIF
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15
bit 14
T6IF: Timer6 Interrupt Flag Status bit
1= Interrupt request has occurred
0= Interrupt request has not occurred
DMA4IF: DMA Channel 4 Data Transfer Complete Interrupt Flag Status bit
1= Interrupt request has occurred
0= Interrupt request has not occurred
bit 13
bit 12
Unimplemented: Read as ‘0’
OC8IF: Output Compare Channel 8 Interrupt Flag Status bit
1= Interrupt request has occurred
0= Interrupt request has not occurred
bit 11
bit 10
bit 9
bit 8
bit 7
bit 6
bit 5
bit 4
bit 3
OC7IF: Output Compare Channel 7 Interrupt Flag Status bit
1= Interrupt request has occurred
0= Interrupt request has not occurred
OC6IF: Output Compare Channel 6 Interrupt Flag Status bit
1= Interrupt request has occurred
0= Interrupt request has not occurred
OC5IF: Output Compare Channel 5 Interrupt Flag Status bit
1= Interrupt request has occurred
0= Interrupt request has not occurred
IC6IF: Input Capture Channel 6 Interrupt Flag Status bit
1= Interrupt request has occurred
0= Interrupt request has not occurred
IC5IF: Input Capture Channel 5 Interrupt Flag Status bit
1= Interrupt request has occurred
0= Interrupt request has not occurred
IC4IF: Input Capture Channel 4 Interrupt Flag Status bit
1= Interrupt request has occurred
0= Interrupt request has not occurred
IC3IF: Input Capture Channel 3 Interrupt Flag Status bit
1= Interrupt request has occurred
0= Interrupt request has not occurred
DMA3IF: DMA Channel 3 Data Transfer Complete Interrupt Flag Status bit
1= Interrupt request has occurred
0= Interrupt request has not occurred
C1IF: ECAN1 Event Interrupt Flag Status bit
1= Interrupt request has occurred
0= Interrupt request has not occurred
© 2009 Microchip Technology Inc.
Preliminary
DS70592A-page 83
PIC24HJXXXGPX06A/X08A/X10A
REGISTER 7-7:
IFS2: INTERRUPT FLAG STATUS REGISTER 2 (CONTINUED)
bit 2
bit 1
bit 0
C1RXIF: ECAN1 Receive Data Ready Interrupt Flag Status bit
1= Interrupt request has occurred
0= Interrupt request has not occurred
SPI2IF: SPI2 Event Interrupt Flag Status bit
1= Interrupt request has occurred
0= Interrupt request has not occurred
SPI2EIF: SPI2 Error Interrupt Flag Status bit
1= Interrupt request has occurred
0= Interrupt request has not occurred
DS70592A-page 84
Preliminary
© 2009 Microchip Technology Inc.
PIC24HJXXXGPX06A/X08A/X10A
REGISTER 7-8:
IFS3: INTERRUPT FLAG STATUS REGISTER 3
U-0
—
U-0
—
R/W-0
U-0
—
U-0
—
U-0
—
U-0
—
R/W-0
C2IF
DMA5IF
bit 15
bit 8
R/W-0
C2RXIF
bit 7
R/W-0
INT4IF
R/W-0
INT3IF
R/W-0
T9IF
R/W-0
T8IF
R/W-0
R/W-0
R/W-0
T7IF
MI2C2IF
SI2C2IF
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-14
bit 13
Unimplemented: Read as ‘0’
DMA5IF: DMA Channel 5 Data Transfer Complete Interrupt Flag Status bit
1= Interrupt request has occurred
0= Interrupt request has not occurred
bit 12-9
bit 8
Unimplemented: Read as ‘0’
C2IF: ECAN2 Event Interrupt Flag Status bit
1= Interrupt request has occurred
0= Interrupt request has not occurred
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
C2RXIF: ECAN2 Receive Data Ready Interrupt Flag Status bit
1= Interrupt request has occurred
0= Interrupt request has not occurred
INT4IF: External Interrupt 4 Flag Status bit
1= Interrupt request has occurred
0= Interrupt request has not occurred
INT3IF: External Interrupt 3 Flag Status bit
1= Interrupt request has occurred
0= Interrupt request has not occurred
T9IF: Timer9 Interrupt Flag Status bit
1= Interrupt request has occurred
0= Interrupt request has not occurred
T8IF: Timer8 Interrupt Flag Status bit
1= Interrupt request has occurred
0= Interrupt request has not occurred
MI2C2IF: I2C2 Master Events Interrupt Flag Status bit
1= Interrupt request has occurred
0= Interrupt request has not occurred
SI2C2IF: I2C2 Slave Events Interrupt Flag Status bit
1= Interrupt request has occurred
0= Interrupt request has not occurred
T7IF: Timer7 Interrupt Flag Status bit
1= Interrupt request has occurred
0= Interrupt request has not occurred
© 2009 Microchip Technology Inc.
Preliminary
DS70592A-page 85
PIC24HJXXXGPX06A/X08A/X10A
REGISTER 7-9:
IFS4: INTERRUPT FLAG STATUS REGISTER 4
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
bit 15
bit 8
bit 0
R/W-0
C2TXIF
bit 7
R/W-0
R/W-0
R/W-0
U-0
—
R/W-0
U2EIF
R/W-0
U1EIF
U-0
—
C1TXIF
DMA7IF
DMA6IF
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-8
bit 7
Unimplemented: Read as ‘0’
C2TXIF: ECAN2 Transmit Data Request Interrupt Flag Status bit
1= Interrupt request has occurred
0= Interrupt request has not occurred
bit 6
bit 5
bit 4
C1TXIF: ECAN1 Transmit Data Request Interrupt Flag Status bit
1= Interrupt request has occurred
0= Interrupt request has not occurred
DMA7IF: DMA Channel 7 Data Transfer Complete Interrupt Flag Status bit
1= Interrupt request has occurred
0= Interrupt request has not occurred
DMA6IF: DMA Channel 6 Data Transfer Complete Interrupt Flag Status bit
1= Interrupt request has occurred
0= Interrupt request has not occurred
bit 3
bit 2
Unimplemented: Read as ‘0’
U2EIF: UART2 Error Interrupt Flag Status bit
1= Interrupt request has occurred
0= Interrupt request has not occurred
bit 1
bit 0
U1EIF: UART1 Error Interrupt Flag Status bit
1= Interrupt request has occurred
0= Interrupt request has not occurred
Unimplemented: Read as ‘0’
DS70592A-page 86
Preliminary
© 2009 Microchip Technology Inc.
PIC24HJXXXGPX06A/X08A/X10A
REGISTER 7-10: IEC0: INTERRUPT ENABLE CONTROL REGISTER 0
U-0
—
R/W-0
R/W-0
AD1IE
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
T3IE
DMA1IE
U1TXIE
U1RXIE
SPI1IE
SPI1EIE
bit 15
bit 8
R/W-0
T2IE
R/W-0
OC2IE
R/W-0
IC2IE
R/W-0
R/W-0
T1IE
R/W-0
OC1IE
R/W-0
IC1IE
R/W-0
DMA0IE
INT0IE
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15
bit 14
Unimplemented: Read as ‘0’
DMA1IE: DMA Channel 1 Data Transfer Complete Interrupt Enable bit
1= Interrupt request enabled
0= Interrupt request not enabled
bit 13
bit 12
bit 11
bit 10
bit 9
AD1IE: ADC1 Conversion Complete Interrupt Enable bit
1= Interrupt request enabled
0= Interrupt request not enabled
U1TXIE: UART1 Transmitter Interrupt Enable bit
1= Interrupt request enabled
0= Interrupt request not enabled
U1RXIE: UART1 Receiver Interrupt Enable bit
1= Interrupt request enabled
0= Interrupt request not enabled
SPI1IE: SPI1 Event Interrupt Enable bit
1= Interrupt request enabled
0= Interrupt request not enabled
SPI1EIE: SPI1 Error Interrupt Enable bit
1= Interrupt request enabled
0= Interrupt request not enabled
bit 8
T3IE: Timer3 Interrupt Enable bit
1= Interrupt request enabled
0= Interrupt request not enabled
bit 7
T2IE: Timer2 Interrupt Enable bit
1= Interrupt request enabled
0= Interrupt request not enabled
bit 6
OC2IE: Output Compare Channel 2 Interrupt Enable bit
1= Interrupt request enabled
0= Interrupt request not enabled
bit 5
IC2IE: Input Capture Channel 2 Interrupt Enable bit
1= Interrupt request enabled
0= Interrupt request not enabled
bit 4
DMA0IE: DMA Channel 0 Data Transfer Complete Interrupt Enable bit
1= Interrupt request enabled
0= Interrupt request not enabled
bit 3
T1IE: Timer1 Interrupt Enable bit
1= Interrupt request enabled
0= Interrupt request not enabled
© 2009 Microchip Technology Inc.
Preliminary
DS70592A-page 87
PIC24HJXXXGPX06A/X08A/X10A
REGISTER 7-10: IEC0: INTERRUPT ENABLE CONTROL REGISTER 0 (CONTINUED)
bit 2
bit 1
bit 0
OC1IE: Output Compare Channel 1 Interrupt Enable bit
1= Interrupt request enabled
0= Interrupt request not enabled
IC1IE: Input Capture Channel 1 Interrupt Enable bit
1= Interrupt request enabled
0= Interrupt request not enabled
INT0IE: External Interrupt 0 Enable bit
1= Interrupt request enabled
0= Interrupt request not enabled
DS70592A-page 88
Preliminary
© 2009 Microchip Technology Inc.
PIC24HJXXXGPX06A/X08A/X10A
REGISTER 7-11: IEC1: INTERRUPT ENABLE CONTROL REGISTER 1
R/W-0
R/W-0
R/W-0
R/W-0
T5IE
R/W-0
T4IE
R/W-0
OC4IE
R/W-0
OC3IE
R/W-0
U2TXIE
U2RXIE
INT2IE
DMA2IE
bit 15
bit 8
R/W-0
IC8IE
R/W-0
IC7IE
R/W-0
AD2IE
R/W-0
R/W-0
CNIE
U-0
—
R/W-0
R/W-0
INT1IE
MI2C1IE
SI2C1IE
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15
bit 14
bit 13
bit 12
bit 11
bit 10
bit 9
U2TXIE: UART2 Transmitter Interrupt Enable bit
1= Interrupt request enabled
0= Interrupt request not enabled
U2RXIE: UART2 Receiver Interrupt Enable bit
1= Interrupt request enabled
0= Interrupt request not enabled
INT2IE: External Interrupt 2 Enable bit
1= Interrupt request enabled
0= Interrupt request not enabled
T5IE: Timer5 Interrupt Enable bit
1= Interrupt request enabled
0= Interrupt request not enabled
T4IE: Timer4 Interrupt Enable bit
1= Interrupt request enabled
0= Interrupt request not enabled
OC4IE: Output Compare Channel 4 Interrupt Enable bit
1= Interrupt request enabled
0= Interrupt request not enabled
OC3IE: Output Compare Channel 3 Interrupt Enable bit
1= Interrupt request enabled
0= Interrupt request not enabled
bit 8
DMA2IE: DMA Channel 2 Data Transfer Complete Interrupt Enable bit
1= Interrupt request enabled
0= Interrupt request not enabled
bit 7
IC8IE: Input Capture Channel 8 Interrupt Enable bit
1= Interrupt request enabled
0= Interrupt request not enabled
bit 6
IC7IE: Input Capture Channel 7 Interrupt Enable bit
1= Interrupt request enabled
0= Interrupt request not enabled
bit 5
AD2IE: ADC2 Conversion Complete Interrupt Enable bit
1= Interrupt request enabled
0= Interrupt request not enabled
bit 4
INT1IE: External Interrupt 1 Enable bit
1= Interrupt request enabled
0= Interrupt request not enabled
© 2009 Microchip Technology Inc.
Preliminary
DS70592A-page 89
PIC24HJXXXGPX06A/X08A/X10A
REGISTER 7-11: IEC1: INTERRUPT ENABLE CONTROL REGISTER 1 (CONTINUED)
bit 3
CNIE: Input Change Notification Interrupt Enable bit
1= Interrupt request enabled
0= Interrupt request not enabled
bit 2
bit 1
Unimplemented: Read as ‘0’
MI2C1IE: I2C1 Master Events Interrupt Enable bit
1= Interrupt request enabled
0= Interrupt request not enabled
bit 0
SI2C1IE: I2C1 Slave Events Interrupt Enable bit
1= Interrupt request enabled
0= Interrupt request not enabled
DS70592A-page 90
Preliminary
© 2009 Microchip Technology Inc.
PIC24HJXXXGPX06A/X08A/X10A
REGISTER 7-12: IEC2: INTERRUPT ENABLE CONTROL REGISTER 2
R/W-0
T6IE
R/W-0
U-0
—
R/W-0
OC8IE
R/W-0
OC7IE
R/W-0
OC6IE
R/W-0
OC5IE
R/W-0
IC6IE
DMA4IE
bit 15
bit 8
R/W-0
IC5IE
R/W-0
IC4IE
R/W-0
IC3IE
R/W-0
R/W-0
C1IE
R/W-0
R/W-0
R/W-0
DMA3IE
C1RXIE
SPI2IE
SPI2EIE
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15
bit 14
T6IE: Timer6 Interrupt Enable bit
1= Interrupt request enabled
0= Interrupt request not enabled
DMA4IE: DMA Channel 4 Data Transfer Complete Interrupt Enable bit
1= Interrupt request enabled
0= Interrupt request not enabled
bit 13
bit 12
Unimplemented: Read as ‘0’
OC8IE: Output Compare Channel 8 Interrupt Enable bit
1= Interrupt request enabled
0= Interrupt request not enabled
bit 11
bit 10
bit 9
bit 8
bit 7
bit 6
bit 5
bit 4
bit 3
OC7IE: Output Compare Channel 7 Interrupt Enable bit
1= Interrupt request enabled
0= Interrupt request not enabled
OC6IE: Output Compare Channel 6 Interrupt Enable bit
1= Interrupt request enabled
0= Interrupt request not enabled
OC5IE: Output Compare Channel 5 Interrupt Enable bit
1= Interrupt request enabled
0= Interrupt request not enabled
IC6IE: Input Capture Channel 6 Interrupt Enable bit
1= Interrupt request enabled
0= Interrupt request not enabled
IC5IE: Input Capture Channel 5 Interrupt Enable bit
1= Interrupt request enabled
0= Interrupt request not enabled
IC4IE: Input Capture Channel 4 Interrupt Enable bit
1= Interrupt request enabled
0= Interrupt request not enabled
IC3IE: Input Capture Channel 3 Interrupt Enable bit
1= Interrupt request enabled
0= Interrupt request not enabled
DMA3IE: DMA Channel 3 Data Transfer Complete Interrupt Enable bit
1= Interrupt request enabled
0= Interrupt request not enabled
C1IE: ECAN1 Event Interrupt Enable bit
1= Interrupt request enabled
0= Interrupt request not enabled
© 2009 Microchip Technology Inc.
Preliminary
DS70592A-page 91
PIC24HJXXXGPX06A/X08A/X10A
REGISTER 7-12: IEC2: INTERRUPT ENABLE CONTROL REGISTER 2 (CONTINUED)
bit 2
bit 1
bit 0
C1RXIE: ECAN1 Receive Data Ready Interrupt Enable bit
1= Interrupt request enabled
0= Interrupt request not enabled
SPI2IE: SPI2 Event Interrupt Enable bit
1= Interrupt request enabled
0= Interrupt request not enabled
SPI2EIE: SPI2 Error Interrupt Enable bit
1= Interrupt request enabled
0= Interrupt request not enabled
DS70592A-page 92
Preliminary
© 2009 Microchip Technology Inc.
PIC24HJXXXGPX06A/X08A/X10A
REGISTER 7-13: IEC3: INTERRUPT ENABLE CONTROL REGISTER 3
U-0
—
U-0
—
R/W-0
U-0
—
U-0
—
U-0
—
U-0
—
R/W-0
C2IE
DMA5IE
bit 15
bit 8
R/W-0
R/W-0
R/W-0
R/W-0
T9IE
R/W-0
T8IE
R/W-0
R/W-0
R/W-0
T7IE
C2RXIE
INT4IE
INT3IE
MI2C2IE
SI2C2IE
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-14
bit 13
Unimplemented: Read as ‘0’
DMA5IE: DMA Channel 5 Data Transfer Complete Interrupt Enable bit
1= Interrupt request enabled
0= Interrupt request not enabled
bit 12-9
bit 8
Unimplemented: Read as ‘0’
C2IE: ECAN2 Event Interrupt Enable bit
1= Interrupt request enabled
0= Interrupt request not enabled
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
C2RXIE: ECAN2 Receive Data Ready Interrupt Enable bit
1= Interrupt request enabled
0= Interrupt request not enabled
INT4IE: External Interrupt 4 Enable bit
1= Interrupt request enabled
0= Interrupt request not enabled
INT3IE: External Interrupt 3 Enable bit
1= Interrupt request enabled
0= Interrupt request not enabled
T9IE: Timer9 Interrupt Enable bit
1= Interrupt request enabled
0= Interrupt request not enabled
T8IE: Timer8 Interrupt Enable bit
1= Interrupt request enabled
0= Interrupt request not enabled
MI2C2IE: I2C2 Master Events Interrupt Enable bit
1= Interrupt request enabled
0= Interrupt request not enabled
SI2C2IE: I2C2 Slave Events Interrupt Enable bit
1= Interrupt request enabled
0= Interrupt request not enabled
T7IE: Timer7 Interrupt Enable bit
1= Interrupt request enabled
0= Interrupt request not enabled
© 2009 Microchip Technology Inc.
Preliminary
DS70592A-page 93
PIC24HJXXXGPX06A/X08A/X10A
REGISTER 7-14: IEC4: INTERRUPT ENABLE CONTROL REGISTER 4
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
bit 15
bit 8
bit 0
R/W-0
R/W-0
R/W-0
R/W-0
U-0
—
R/W-0
U2EIE
R/W-0
U1EIE
U-0
—
C2TXIE
C1TXIE
DMA7IE
DMA6IE
bit 7
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-8
bit 7
Unimplemented: Read as ‘0’
C2TXIE: ECAN2 Transmit Data Request Interrupt Enable bit
1= Interrupt request enabled
0= Interrupt request not enabled
bit 6
bit 5
bit 4
C1TXIE: ECAN1 Transmit Data Request Interrupt Enable bit
1= Interrupt request enabled
0= Interrupt request not enabled
DMA7IE: DMA Channel 7 Data Transfer Complete Enable Status bit
1= Interrupt request enabled
0= Interrupt request not enabled
DMA6IE: DMA Channel 6 Data Transfer Complete Enable Status bit
1= Interrupt request enabled
0= Interrupt request not enabled
bit 3
bit 2
Unimplemented: Read as ‘0’
U2EIE: UART2 Error Interrupt Enable bit
1= Interrupt request enabled
0= Interrupt request not enabled
bit 1
bit 0
U1EIE: UART1 Error Interrupt Enable bit
1= Interrupt request enabled
0= Interrupt request not enabled
Unimplemented: Read as ‘0’
DS70592A-page 94
Preliminary
© 2009 Microchip Technology Inc.
PIC24HJXXXGPX06A/X08A/X10A
REGISTER 7-15: IPC0: INTERRUPT PRIORITY CONTROL REGISTER 0
U-0
—
R/W-1
R/W-0
R/W-0
U-0
—
R/W-1
R/W-0
R/W-0
bit 8
R/W-0
bit 0
T1IP<2:0>
OC1IP<2:0>
bit 15
U-0
—
R/W-1
R/W-0
R/W-0
U-0
—
R/W-1
R/W-0
IC1IP<2:0>
INT0IP<2:0>
bit 7
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15
Unimplemented: Read as ‘0’
T1IP<2:0>: Timer1 Interrupt Priority bits
bit 14-12
111= Interrupt is priority 7 (highest priority interrupt)
•
•
•
001= Interrupt is priority 1
000= Interrupt source is disabled
bit 11
Unimplemented: Read as ‘0’
bit 10-8
OC1IP<2:0>: Output Compare Channel 1 Interrupt Priority bits
111= Interrupt is priority 7 (highest priority interrupt)
•
•
•
001= Interrupt is priority 1
000= Interrupt source is disabled
bit 7
Unimplemented: Read as ‘0’
bit 6-4
IC1IP<2:0>: Input Capture Channel 1 Interrupt Priority bits
111= Interrupt is priority 7 (highest priority interrupt)
•
•
•
001= Interrupt is priority 1
000= Interrupt source is disabled
bit 3
Unimplemented: Read as ‘0’
bit 2-0
INT0IP<2:0>: External Interrupt 0 Priority bits
111= Interrupt is priority 7 (highest priority interrupt)
•
•
•
001= Interrupt is priority 1
000= Interrupt source is disabled
© 2009 Microchip Technology Inc.
Preliminary
DS70592A-page 95
PIC24HJXXXGPX06A/X08A/X10A
REGISTER 7-16: IPC1: INTERRUPT PRIORITY CONTROL REGISTER 1
U-0
—
R/W-1
R/W-0
R/W-0
U-0
—
R/W-1
R/W-0
R/W-0
bit 8
R/W-0
bit 0
T2IP<2:0>
OC2IP<2:0>
bit 15
U-0
—
R/W-1
R/W-0
R/W-0
U-0
—
R/W-1
R/W-0
IC2IP<2:0>
DMA0IP<2:0>
bit 7
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15
Unimplemented: Read as ‘0’
T2IP<2:0>: Timer2 Interrupt Priority bits
bit 14-12
111= Interrupt is priority 7 (highest priority interrupt)
•
•
•
001= Interrupt is priority 1
000= Interrupt source is disabled
bit 11
Unimplemented: Read as ‘0’
bit 10-8
OC2IP<2:0>: Output Compare Channel 2 Interrupt Priority bits
111= Interrupt is priority 7 (highest priority interrupt)
•
•
•
001= Interrupt is priority 1
000= Interrupt source is disabled
bit 7
Unimplemented: Read as ‘0’
bit 6-4
IC2IP<2:0>: Input Capture Channel 2 Interrupt Priority bits
111= Interrupt is priority 7 (highest priority interrupt)
•
•
•
001= Interrupt is priority 1
000= Interrupt source is disabled
bit 3
Unimplemented: Read as ‘0’
bit 2-0
DMA0IP<2:0>: DMA Channel 0 Data Transfer Complete Interrupt Priority bits
111= Interrupt is priority 7 (highest priority interrupt)
•
•
•
001= Interrupt is priority 1
000= Interrupt source is disabled
DS70592A-page 96
Preliminary
© 2009 Microchip Technology Inc.
PIC24HJXXXGPX06A/X08A/X10A
REGISTER 7-17: IPC2: INTERRUPT PRIORITY CONTROL REGISTER 2
U-0
—
R/W-1
R/W-0
R/W-0
U-0
—
R/W-1
R/W-0
R/W-0
bit 8
R/W-0
bit 0
U1RXIP<2:0>
SPI1IP<2:0>
bit 15
U-0
—
R/W-1
R/W-0
R/W-0
U-0
—
R/W-1
R/W-0
SPI1EIP<2:0>
T3IP<2:0>
bit 7
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15
Unimplemented: Read as ‘0’
bit 14-12
U1RXIP<2:0>: UART1 Receiver Interrupt Priority bits
111= Interrupt is priority 7 (highest priority interrupt)
•
•
•
001= Interrupt is priority 1
000= Interrupt source is disabled
bit 11
Unimplemented: Read as ‘0’
bit 10-8
SPI1IP<2:0>: SPI1 Event Interrupt Priority bits
111= Interrupt is priority 7 (highest priority interrupt)
•
•
•
001= Interrupt is priority 1
000= Interrupt source is disabled
bit 7
Unimplemented: Read as ‘0’
bit 6-4
SPI1EIP<2:0>: SPI1 Error Interrupt Priority bits
111= Interrupt is priority 7 (highest priority interrupt)
•
•
•
001= Interrupt is priority 1
000= Interrupt source is disabled
bit 3
Unimplemented: Read as ‘0’
bit 2-0
T3IP<2:0>: Timer3 Interrupt Priority bits
111= Interrupt is priority 7 (highest priority interrupt)
•
•
•
001= Interrupt is priority 1
000= Interrupt source is disabled
© 2009 Microchip Technology Inc.
Preliminary
DS70592A-page 97
PIC24HJXXXGPX06A/X08A/X10A
REGISTER 7-18: IPC3: INTERRUPT PRIORITY CONTROL REGISTER 3
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
R/W-1
R/W-0
R/W-0
bit 8
R/W-0
bit 0
DMA1IP<2:0>
bit 15
U-0
—
R/W-1
R/W-0
R/W-0
U-0
—
R/W-1
R/W-0
AD1IP<2:0>
U1TXIP<2:0>
bit 7
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-11
bit 10-8
Unimplemented: Read as ‘0’
DMA1IP<2:0>: DMA Channel 1 Data Transfer Complete Interrupt Priority bits
111= Interrupt is priority 7 (highest priority interrupt)
•
•
•
001= Interrupt is priority 1
000= Interrupt source is disabled
bit 7
Unimplemented: Read as ‘0’
bit 6-4
AD1IP<2:0>: ADC1 Conversion Complete Interrupt Priority bits
111= Interrupt is priority 7 (highest priority interrupt)
•
•
•
001= Interrupt is priority 1
000= Interrupt source is disabled
bit 3
Unimplemented: Read as ‘0’
bit 2-0
U1TXIP<2:0>: UART1 Transmitter Interrupt Priority bits
111= Interrupt is priority 7 (highest priority interrupt)
•
•
•
001= Interrupt is priority 1
000= Interrupt source is disabled
DS70592A-page 98
Preliminary
© 2009 Microchip Technology Inc.
PIC24HJXXXGPX06A/X08A/X10A
REGISTER 7-19: IPC4: INTERRUPT PRIORITY CONTROL REGISTER 4
U-0
—
R/W-1
R/W-0
R/W-0
U-0
—
U-0
—
U-0
—
U-0
—
CNIP<2:0>
bit 15
bit 8
R/W-0
bit 0
U-0
—
R/W-1
R/W-0
R/W-0
U-0
—
R/W-1
R/W-0
MI2C1IP<2:0>
SI2C1IP<2:0>
bit 7
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15
Unimplemented: Read as ‘0’
bit 14-12
CNIP<2:0>: Change Notification Interrupt Priority bits
111= Interrupt is priority 7 (highest priority interrupt)
•
•
•
001= Interrupt is priority 1
000= Interrupt source is disabled
bit 11-7
bit 6-4
Unimplemented: Read as ‘0’
MI2C1IP<2:0>: I2C1 Master Events Interrupt Priority bits
111= Interrupt is priority 7 (highest priority interrupt)
•
•
•
001= Interrupt is priority 1
000= Interrupt source is disabled
bit 3
Unimplemented: Read as ‘0’
bit 2-0
SI2C1IP<2:0>: I2C1 Slave Events Interrupt Priority bits
111= Interrupt is priority 7 (highest priority interrupt)
•
•
•
001= Interrupt is priority 1
000= Interrupt source is disabled
© 2009 Microchip Technology Inc.
Preliminary
DS70592A-page 99
PIC24HJXXXGPX06A/X08A/X10A
REGISTER 7-20: IPC5: INTERRUPT PRIORITY CONTROL REGISTER 5
U-0
—
R/W-1
R/W-0
R/W-0
U-0
—
R/W-1
R/W-0
R/W-0
bit 8
R/W-0
bit 0
IC8IP<2:0>
IC7IP<2:0>
bit 15
U-0
—
R/W-1
R/W-0
R/W-0
U-0
—
R/W-1
R/W-0
AD2IP<2:0>
INT1IP<2:0>
bit 7
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15
Unimplemented: Read as ‘0’
bit 14-12
IC8IP<2:0>: Input Capture Channel 8 Interrupt Priority bits
111= Interrupt is priority 7 (highest priority interrupt)
•
•
•
001= Interrupt is priority 1
000= Interrupt source is disabled
bit 11
Unimplemented: Read as ‘0’
bit 10-8
IC7IP<2:0>: Input Capture Channel 7 Interrupt Priority bits
111= Interrupt is priority 7 (highest priority interrupt)
•
•
•
001= Interrupt is priority 1
000= Interrupt source is disabled
bit 7
Unimplemented: Read as ‘0’
bit 6-4
AD2IP<2:0>: ADC2 Conversion Complete Interrupt Priority bits
111= Interrupt is priority 7 (highest priority interrupt)
•
•
•
001= Interrupt is priority 1
000= Interrupt source is disabled
bit 3
Unimplemented: Read as ‘0’
bit 2-0
INT1IP<2:0>: External Interrupt 1 Priority bits
111= Interrupt is priority 7 (highest priority interrupt)
•
•
•
001= Interrupt is priority 1
000= Interrupt source is disabled
DS70592A-page 100
Preliminary
© 2009 Microchip Technology Inc.
PIC24HJXXXGPX06A/X08A/X10A
REGISTER 7-21: IPC6: INTERRUPT PRIORITY CONTROL REGISTER 6
U-0
—
R/W-1
R/W-0
R/W-0
U-0
—
R/W-1
R/W-0
R/W-0
bit 8
R/W-0
bit 0
T4IP<2:0>
OC4IP<2:0>
bit 15
U-0
—
R/W-1
R/W-0
R/W-0
U-0
—
R/W-1
R/W-0
OC3IP<2:0>
DMA2IP<2:0>
bit 7
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15
Unimplemented: Read as ‘0’
T4IP<2:0>: Timer4 Interrupt Priority bits
bit 14-12
111= Interrupt is priority 7 (highest priority interrupt)
•
•
•
001= Interrupt is priority 1
000= Interrupt source is disabled
bit 11
Unimplemented: Read as ‘0’
bit 10-8
OC4IP<2:0>: Output Compare Channel 4 Interrupt Priority bits
111= Interrupt is priority 7 (highest priority interrupt)
•
•
•
001= Interrupt is priority 1
000= Interrupt source is disabled
bit 7
Unimplemented: Read as ‘0’
bit 6-4
OC3IP<2:0>: Output Compare Channel 3 Interrupt Priority bits
111= Interrupt is priority 7 (highest priority interrupt)
•
•
•
001= Interrupt is priority 1
000= Interrupt source is disabled
bit 3
Unimplemented: Read as ‘0’
bit 2-0
DMA2IP<2:0>: DMA Channel 2 Data Transfer Complete Interrupt Priority bits
111= Interrupt is priority 7 (highest priority interrupt)
•
•
•
001= Interrupt is priority 1
000= Interrupt source is disabled
© 2009 Microchip Technology Inc.
Preliminary
DS70592A-page 101
PIC24HJXXXGPX06A/X08A/X10A
REGISTER 7-22: IPC7: INTERRUPT PRIORITY CONTROL REGISTER 7
U-0
—
R/W-1
R/W-0
R/W-0
U-0
—
R/W-1
R/W-0
R/W-0
bit 8
R/W-0
bit 0
U2TXIP<2:0>
U2RXIP<2:0>
bit 15
U-0
—
R/W-1
R/W-0
R/W-0
U-0
—
R/W-1
R/W-0
INT2IP<2:0>
T5IP<2:0>
bit 7
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15
Unimplemented: Read as ‘0’
bit 14-12
U2TXIP<2:0>: UART2 Transmitter Interrupt Priority bits
111= Interrupt is priority 7 (highest priority interrupt)
•
•
•
001= Interrupt is priority 1
000= Interrupt source is disabled
bit 11
Unimplemented: Read as ‘0’
bit 10-8
U2RXIP<2:0>: UART2 Receiver Interrupt Priority bits
111= Interrupt is priority 7 (highest priority interrupt)
•
•
•
001= Interrupt is priority 1
000= Interrupt source is disabled
bit 7
Unimplemented: Read as ‘0’
bit 6-4
INT2IP<2:0>: External Interrupt 2 Priority bits
111= Interrupt is priority 7 (highest priority interrupt)
•
•
•
001= Interrupt is priority 1
000= Interrupt source is disabled
bit 3
Unimplemented: Read as ‘0’
bit 2-0
T5IP<2:0>: Timer5 Interrupt Priority bits
111= Interrupt is priority 7 (highest priority interrupt)
•
•
•
001= Interrupt is priority 1
000= Interrupt source is disabled
DS70592A-page 102
Preliminary
© 2009 Microchip Technology Inc.
PIC24HJXXXGPX06A/X08A/X10A
REGISTER 7-23: IPC8: INTERRUPT PRIORITY CONTROL REGISTER 8
U-0
—
R/W-1
R/W-0
R/W-0
U-0
—
R/W-1
R/W-0
R/W-0
bit 8
R/W-0
bit 0
C1IP<2:0>
C1RXIP<2:0>
bit 15
U-0
—
R/W-1
R/W-0
R/W-0
U-0
—
R/W-1
R/W-0
SPI2IP<2:0>
SPI2EIP<2:0>
bit 7
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15
Unimplemented: Read as ‘0’
bit 14-12
C1IP<2:0>: ECAN1 Event Interrupt Priority bits
111= Interrupt is priority 7 (highest priority interrupt)
•
•
•
001= Interrupt is priority 1
000= Interrupt source is disabled
bit 11
Unimplemented: Read as ‘0’
bit 10-8
C1RXIP<2:0>: ECAN1 Receive Data Ready Interrupt Priority bits
111= Interrupt is priority 7 (highest priority interrupt)
•
•
•
001= Interrupt is priority 1
000= Interrupt source is disabled
bit 7
Unimplemented: Read as ‘0’
bit 6-4
SPI2IP<2:0>: SPI2 Event Interrupt Priority bits
111= Interrupt is priority 7 (highest priority interrupt)
•
•
•
001= Interrupt is priority 1
000= Interrupt source is disabled
bit 3
Unimplemented: Read as ‘0’
bit 2-0
SPI2EIP<2:0>: SPI2 Error Interrupt Priority bits
111= Interrupt is priority 7 (highest priority interrupt)
•
•
•
001= Interrupt is priority 1
000= Interrupt source is disabled
© 2009 Microchip Technology Inc.
Preliminary
DS70592A-page 103
PIC24HJXXXGPX06A/X08A/X10A
REGISTER 7-24: IPC9: INTERRUPT PRIORITY CONTROL REGISTER 9
U-0
—
R/W-1
R/W-0
R/W-0
U-0
—
R/W-1
R/W-0
R/W-0
bit 8
R/W-0
bit 0
IC5IP<2:0>
IC4IP<2:0>
bit 15
U-0
—
R/W-1
R/W-0
R/W-0
U-0
—
R/W-1
R/W-0
IC3IP<2:0>
DMA3IP<2:0>
bit 7
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15
Unimplemented: Read as ‘0’
bit 14-12
IC5IP<2:0>: Input Capture Channel 5 Interrupt Priority bits
111= Interrupt is priority 7 (highest priority interrupt)
•
•
•
001= Interrupt is priority 1
000= Interrupt source is disabled
bit 11
Unimplemented: Read as ‘0’
bit 10-8
IC4IP<2:0>: Input Capture Channel 4 Interrupt Priority bits
111= Interrupt is priority 7 (highest priority interrupt)
•
•
•
001= Interrupt is priority 1
000= Interrupt source is disabled
bit 7
Unimplemented: Read as ‘0’
bit 6-4
IC3IP<2:0>: Input Capture Channel 3 Interrupt Priority bits
111= Interrupt is priority 7 (highest priority interrupt)
•
•
•
001= Interrupt is priority 1
000= Interrupt source is disabled
bit 3
Unimplemented: Read as ‘0’
bit 2-0
DMA3IP<2:0>: DMA Channel 3 Data Transfer Complete Interrupt Priority bits
111= Interrupt is priority 7 (highest priority interrupt)
•
•
•
001= Interrupt is priority 1
000= Interrupt source is disabled
DS70592A-page 104
Preliminary
© 2009 Microchip Technology Inc.
PIC24HJXXXGPX06A/X08A/X10A
REGISTER 7-25: IPC10: INTERRUPT PRIORITY CONTROL REGISTER 10
U-0
—
R/W-1
R/W-0
R/W-0
U-0
—
R/W-1
R/W-0
R/W-0
bit 8
R/W-0
bit 0
OC7IP<2:0>
OC6IP<2:0>
bit 15
U-0
—
R/W-1
R/W-0
R/W-0
U-0
—
R/W-1
R/W-0
OC5IP<2:0>
IC6IP<2:0>
bit 7
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15
Unimplemented: Read as ‘0’
bit 14-12
OC7IP<2:0>: Output Compare Channel 7 Interrupt Priority bits
111= Interrupt is priority 7 (highest priority interrupt)
•
•
•
001= Interrupt is priority 1
000= Interrupt source is disabled
bit 11
Unimplemented: Read as ‘0’
bit 10-8
OC6IP<2:0>: Output Compare Channel 6 Interrupt Priority bits
111= Interrupt is priority 7 (highest priority interrupt)
•
•
•
001= Interrupt is priority 1
000= Interrupt source is disabled
bit 7
Unimplemented: Read as ‘0’
bit 6-4
OC5IP<2:0>: Output Compare Channel 5 Interrupt Priority bits
111= Interrupt is priority 7 (highest priority interrupt)
•
•
•
001= Interrupt is priority 1
000= Interrupt source is disabled
bit 3
Unimplemented: Read as ‘0’
bit 2-0
IC6IP<2:0>: Input Capture Channel 6 Interrupt Priority bits
111= Interrupt is priority 7 (highest priority interrupt)
•
•
•
001= Interrupt is priority 1
000= Interrupt source is disabled
© 2009 Microchip Technology Inc.
Preliminary
DS70592A-page 105
PIC24HJXXXGPX06A/X08A/X10A
REGISTER 7-26: IPC11: INTERRUPT PRIORITY CONTROL REGISTER 11
U-0
—
R/W-1
R/W-0
R/W-0
U-0
—
R/W-1
R/W-0
R/W-0
bit 8
R/W-0
bit 0
T6IP<2:0>
DMA4IP<2:0>
bit 15
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
R/W-1
R/W-0
OC8IP<2:0>
bit 7
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15
Unimplemented: Read as ‘0’
T6IP<2:0>: Timer6 Interrupt Priority bits
bit 14-12
111= Interrupt is priority 7 (highest priority interrupt)
•
•
•
001= Interrupt is priority 1
000= Interrupt source is disabled
bit 11
Unimplemented: Read as ‘0’
bit 10-8
DMA4IP<2:0>: DMA Channel 4 Data Transfer Complete Interrupt Priority bits
111= Interrupt is priority 7 (highest priority interrupt)
•
•
•
001= Interrupt is priority 1
000= Interrupt source is disabled
bit 7-3
bit 2-0
Unimplemented: Read as ‘0’
OC8IP<2:0>: Output Compare Channel 8 Interrupt Priority bits
111= Interrupt is priority 7 (highest priority interrupt)
•
•
•
001= Interrupt is priority 1
000= Interrupt source is disabled
DS70592A-page 106
Preliminary
© 2009 Microchip Technology Inc.
PIC24HJXXXGPX06A/X08A/X10A
REGISTER 7-27: IPC12: INTERRUPT PRIORITY CONTROL REGISTER 12
U-0
—
R/W-1
R/W-0
R/W-0
U-0
—
R/W-1
R/W-0
R/W-0
bit 8
R/W-0
bit 0
T8IP<2:0>
MI2C2IP<2:0>
bit 15
U-0
—
R/W-1
R/W-0
R/W-0
U-0
—
R/W-1
R/W-0
SI2C2IP<2:0>
T7IP<2:0>
bit 7
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15
Unimplemented: Read as ‘0’
T8IP<2:0>: Timer8 Interrupt Priority bits
bit 14-12
111= Interrupt is priority 7 (highest priority interrupt)
•
•
•
001= Interrupt is priority 1
000= Interrupt source is disabled
bit 11
Unimplemented: Read as ‘0’
bit 10-8
MI2C2IP<2:0>: I2C2 Master Events Interrupt Priority bits
111= Interrupt is priority 7 (highest priority interrupt)
•
•
•
001= Interrupt is priority 1
000= Interrupt source is disabled
bit 7
Unimplemented: Read as ‘0’
bit 6-4
SI2C2IP<2:0>: I2C2 Slave Events Interrupt Priority bits
111= Interrupt is priority 7 (highest priority interrupt)
•
•
•
001= Interrupt is priority 1
000= Interrupt source is disabled
bit 3
Unimplemented: Read as ‘0’
bit 2-0
T7IP<2:0>: Timer7 Interrupt Priority bits
111= Interrupt is priority 7 (highest priority interrupt)
•
•
•
001= Interrupt is priority 1
000= Interrupt source is disabled
© 2009 Microchip Technology Inc.
Preliminary
DS70592A-page 107
PIC24HJXXXGPX06A/X08A/X10A
REGISTER 7-28: IPC13: INTERRUPT PRIORITY CONTROL REGISTER 13
U-0
—
R/W-1
R/W-0
R/W-0
U-0
—
R/W-1
R/W-0
R/W-0
bit 8
R/W-0
bit 0
C2RXIP<2:0>
INT4IP<2:0>
bit 15
U-0
—
R/W-1
R/W-0
R/W-0
U-0
—
R/W-1
R/W-0
INT3IP<2:0>
T9IP<2:0>
bit 7
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15
Unimplemented: Read as ‘0’
bit 14-12
C2RXIP<2:0>: ECAN2 Receive Data Ready Interrupt Priority bits
111= Interrupt is priority 7 (highest priority interrupt)
•
•
•
001= Interrupt is priority 1
000= Interrupt source is disabled
bit 11
Unimplemented: Read as ‘0’
bit 10-8
INT4IP<2:0>: External Interrupt 4 Priority bits
111= Interrupt is priority 7 (highest priority interrupt)
•
•
•
001= Interrupt is priority 1
000= Interrupt source is disabled
bit 7
Unimplemented: Read as ‘0’
bit 6-4
INT3IP<2:0>: External Interrupt 3 Priority bits
111= Interrupt is priority 7 (highest priority interrupt)
•
•
•
001= Interrupt is priority 1
000= Interrupt source is disabled
bit 3
Unimplemented: Read as ‘0’
bit 2-0
T9IP<2:0>: Timer9 Interrupt Priority bits
111= Interrupt is priority 7 (highest priority interrupt)
•
•
•
001= Interrupt is priority 1
000= Interrupt source is disabled
DS70592A-page 108
Preliminary
© 2009 Microchip Technology Inc.
PIC24HJXXXGPX06A/X08A/X10A
REGISTER 7-29: IPC14: INTERRUPT PRIORITY CONTROL REGISTER 14
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
bit 15
bit 8
R/W-0
bit 0
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
R/W-1
R/W-0
C2IP<2:0>
bit 7
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-3
bit 2-0
Unimplemented: Read as ‘0’
C2IP<2:0>: ECAN2 Event Interrupt Priority bits
111= Interrupt is priority 7 (highest priority interrupt)
•
•
•
001= Interrupt is priority 1
000= Interrupt source is disabled
© 2009 Microchip Technology Inc.
Preliminary
DS70592A-page 109
PIC24HJXXXGPX06A/X08A/X10A
REGISTER 7-30: IPC15: INTERRUPT PRIORITY CONTROL REGISTER 15
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
bit 15
bit 8
bit 0
U-0
—
R/W-1
R/W-0
R/W-0
U-0
—
U-0
—
U-0
—
U-0
—
DMA5IP<2:0>
bit 7
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-7
bit 6-4
Unimplemented: Read as ‘0’
DMA5IP<2:0>: DMA Channel 5 Data Transfer Complete Interrupt Priority bits
111= Interrupt is priority 7 (highest priority interrupt)
•
•
•
001= Interrupt is priority 1
000= Interrupt source is disabled
bit 3-0
Unimplemented: Read as ‘0’
DS70592A-page 110
Preliminary
© 2009 Microchip Technology Inc.
PIC24HJXXXGPX06A/X08A/X10A
REGISTER 7-31: IPC16: INTERRUPT PRIORITY CONTROL REGISTER 16
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
R/W-1
R/W-0
R/W-0
bit 8
U2EIP<2:0>
bit 15
U-0
—
R/W-1
R/W-0
R/W-0
U-0
—
U-0
—
U-0
—
U-0
—
U1EIP<2:0>
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-11
bit 10-8
Unimplemented: Read as ‘0’
U2EIP<2:0>: UART2 Error Interrupt Priority bits
111= Interrupt is priority 7 (highest priority interrupt)
•
•
•
001= Interrupt is priority 1
000= Interrupt source is disabled
bit 7
Unimplemented: Read as ‘0’
bit 6-4
U1EIP<2:0>: UART1 Error Interrupt Priority bits
111= Interrupt is priority 7 (highest priority interrupt)
•
•
•
001= Interrupt is priority 1
000= Interrupt source is disabled
bit 3-0
Unimplemented: Read as ‘0’
© 2009 Microchip Technology Inc.
Preliminary
DS70592A-page 111
PIC24HJXXXGPX06A/X08A/X10A
REGISTER 7-32: IPC17: INTERRUPT PRIORITY CONTROL REGISTER 17
U-0
—
R/W-1
R/W-0
R/W-0
U-0
—
R/W-1
R/W-0
R/W-0
bit 8
R/W-0
bit 0
C2TXIP<2:0>
C1TXIP<2:0>
bit 15
U-0
—
R/W-1
R/W-0
R/W-0
U-0
—
R/W-1
R/W-0
DMA7IP<2:0>
DMA6IP<2:0>
bit 7
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15
Unimplemented: Read as ‘0’
bit 14-12
C2TXIP<2:0>: ECAN2 Transmit Data Request Interrupt Priority bits
111= Interrupt is priority 7 (highest priority interrupt)
•
•
•
001= Interrupt is priority 1
000= Interrupt source is disabled
bit 11
Unimplemented: Read as ‘0’
bit 10-8
C1TXIP<2:0>: ECAN1 Transmit Data Request Interrupt Priority bits
111= Interrupt is priority 7 (highest priority interrupt)
•
•
•
001= Interrupt is priority 1
000= Interrupt source is disabled
bit 7
Unimplemented: Read as ‘0’
bit 6-4
DMA7IP<2:0>: DMA Channel 7 Data Transfer Complete Interrupt Priority bits
111= Interrupt is priority 7 (highest priority interrupt)
•
•
•
001= Interrupt is priority 1
000= Interrupt source is disabled
bit 3
Unimplemented: Read as ‘0’
bit 2-0
DMA6IP<2:0>: DMA Channel 6 Data Transfer Complete Interrupt Priority bits
111= Interrupt is priority 7 (highest priority interrupt)
•
•
•
001= Interrupt is priority 1
000= Interrupt source is disabled
DS70592A-page 112
Preliminary
© 2009 Microchip Technology Inc.
PIC24HJXXXGPX06A/X08A/X10A
REGISTER 7-33: INTTREG: INTERRUPT CONTROL AND STATUS REGISTER
U-0
—
U-0
—
U-0
—
U-0
—
R-0
R-0
R-0
R-0
ILR<3:0>
bit 15
bit 8
bit 0
U-0
—
U-0
R-0
R-0
R-0
R-0
R-0
R-0
VECNUM<6:0>
bit 7
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-12
bit 11-8
Unimplemented: Read as ‘0’
ILR<3:0>: New CPU Interrupt Priority Level bits
1111= CPU Interrupt Priority Level is 15
•
•
•
0001 = CPU Interrupt Priority Level is 1
0000= CPU Interrupt Priority Level is 0
bit 7
Unimplemented: Read as ‘0’
bit 6-0
VECNUM<6:0>: Vector Number of Pending Interrupt bits
1111111= Interrupt Vector pending is number 135
•
•
•
0000001= Interrupt Vector pending is number 9
0000000= Interrupt Vector pending is number 8
© 2009 Microchip Technology Inc.
Preliminary
DS70592A-page 113
PIC24HJXXXGPX06A/X08A/X10A
7.4.3
TRAP SERVICE ROUTINE
7.4
Interrupt Setup Procedures
A Trap Service Routine (TSR) is coded like an ISR,
except that the appropriate trap status flag in the
INTCON1 register must be cleared to avoid re-entry
into the TSR.
7.4.1
INITIALIZATION
To configure an interrupt source:
1. Set the NSTDIS bit (INTCON1<15>) if nested
interrupts are not desired.
7.4.4
INTERRUPT DISABLE
2. Select the user-assigned priority level for the
interrupt source by writing the control bits in the
appropriate IPCx register. The priority level will
depend on the specific application and type of
interrupt source. If multiple priority levels are not
desired, the IPCx register control bits for all
enabled interrupt sources may be programmed
to the same non-zero value.
All user interrupts can be disabled using the following
procedure:
1. Push the current SR value onto the software
stack using the PUSHinstruction.
2. Force the CPU to priority level 7 by inclusive
ORing the value 0x0E with SRL.
To enable user interrupts, the POPinstruction may be
Note: At a device Reset, the IPCx registers are
initialized, such that all user interrupt
sources are assigned to priority level 4.
used to restore the previous SR value.
Note that only user interrupts with a priority level of 7 or
less can be disabled. Trap sources (level 8-level 15)
cannot be disabled.
3. Clear the interrupt flag status bit associated with
the peripheral in the associated IFSx register.
The DISIinstruction provides a convenient way to dis-
able interrupts of priority levels 1-6 for a fixed period of
time. Level 7 interrupt sources are not disabled by the
DISI instruction.
4. Enable the interrupt source by setting the inter-
rupt enable control bit associated with the
source in the appropriate IECx register.
7.4.2
INTERRUPT SERVICE ROUTINE
The method that is used to declare an ISR and initialize
the IVT with the correct vector address will depend on
the programming language (i.e., C or assembler) and
the language development toolsuite that is used to
develop the application. In general, the user must clear
the interrupt flag in the appropriate IFSx register for the
source of interrupt that the ISR handles. Otherwise, the
ISR will be re-entered immediately after exiting the
routine. If the ISR is coded in assembly language, it
must be terminated using a RETFIE instruction to
unstack the saved PC value, SRL value and old CPU
priority level.
DS70592A-page 114
Preliminary
© 2009 Microchip Technology Inc.
PIC24HJXXXGPX06A/X08A/X10A
The DMA controller features eight identical data
transfer channels.
8.0
DIRECT MEMORY ACCESS
(DMA)
Each channel has its own set of control and status
registers. Each DMA channel can be configured to
copy data either from buffers stored in dual port DMA
RAM to peripheral SFRs, or from peripheral SFRs to
buffers in DMA RAM.
Note:
This data sheet summarizes the features
of the PIC24HJXXXGPX06A/X08A/X10A
family of devices. However, it is not
intended to be a comprehensive reference
source. To complement the information in
this data sheet, refer to the “PIC24H Fam-
ily Reference Manual”, Section 22.
“Direct Memory Access (DMA)”
(DS70223), which is available from the
Microchip website (www.microchip.com).
The DMA controller supports the following features:
• Word or byte sized data transfers.
• Transfers from peripheral to DMA RAM or DMA
RAM to peripheral.
• Indirect Addressing of DMA RAM locations with or
without automatic post-increment.
Direct Memory Access (DMA) is a very efficient
mechanism of copying data between peripheral SFRs
(e.g., UART Receive register, Input Capture 1 buffer),
and buffers or variables stored in RAM, with minimal
CPU intervention. The DMA controller can
automatically copy entire blocks of data without
requiring the user software to read or write the
peripheral Special Function Registers (SFRs) every
time a peripheral interrupt occurs. The DMA controller
uses a dedicated bus for data transfers and, therefore,
does not steal cycles from the code execution flow of
the CPU. To exploit the DMA capability, the
corresponding user buffers or variables must be
located in DMA RAM.
• Peripheral Indirect Addressing – In some periph-
erals, the DMA RAM read/write addresses may
be partially derived from the peripheral.
• One-Shot Block Transfers – Terminating DMA
transfer after one block transfer.
• Continuous Block Transfers – Reloading DMA
RAM buffer start address after every block
transfer is complete.
• Ping-Pong Mode – Switching between two DMA
RAM start addresses between successive block
transfers, thereby filling two buffers alternately.
• Automatic or manual initiation of block transfers
• Each channel can select from 19 possible
sources of data sources or destinations.
The PIC24HJXXXGPX06A/X08A/X10A peripherals
that can utilize DMA are listed in Table 8-1 along with
their associated Interrupt Request (IRQ) numbers.
For each DMA channel, a DMA interrupt request is
generated when
a
block transfer is complete.
TABLE 8-1:
PERIPHERALS WITH DMA
SUPPORT
Alternatively, an interrupt can be generated when half of
the block has been filled.
Peripheral
IRQ Number
INT0
0
1
Input Capture 1
Input Capture 2
Output Compare 1
Output Compare 2
Timer2
5
2
6
7
Timer3
8
SPI1
10
33
11
12
30
31
13
21
34
70
55
71
SPI2
UART1 Reception
UART1 Transmission
UART2 Reception
UART2 Transmission
ADC1
ADC2
ECAN1 Reception
ECAN1 Transmission
ECAN2 Reception
ECAN2 Transmission
© 2009 Microchip Technology Inc.
Preliminary
DS70592A-page 115
PIC24HJXXXGPX06A/X08A/X10A
FIGURE 8-1:
TOP LEVEL SYSTEM ARCHITECTURE USING A DEDICATED TRANSACTION BUS
Peripheral Indirect Address
DMA Controller
DMA
Ready
Peripheral 3
DMA
Channels
DMA RAM
SRAM
PORT 1 PORT 2
CPU
DMA
SRAM X-Bus
DMA DS Bus
CPU Peripheral DS Bus
CPU
DMA
CPU
DMA
Non-DMA
Ready
Peripheral
DMA
Ready
Peripheral 2
DMA
Ready
Peripheral 1
CPU
Note: CPU and DMA address buses are not shown for clarity.
8.1
DMAC Registers
Each DMAC Channel x (x = 0, 1, 2, 3, 4, 5, 6 or 7)
contains the following registers:
• A 16-bit DMA Channel Control register
(DMAxCON)
• A 16-bit DMA Channel IRQ Select register
(DMAxREQ)
• A 16-bit DMA RAM Primary Start Address Offset
register (DMAxSTA)
• A 16-bit DMA RAM Secondary Start Address
Offset register (DMAxSTB)
• A 16-bit DMA Peripheral Address register
(DMAxPAD)
• A 10-bit DMA Transfer Count register (DMAxCNT)
An additional pair of status registers, DMACS0 and
DMACS1 are common to all DMAC channels.
DS70592A-page 116
Preliminary
© 2009 Microchip Technology Inc.
PIC24HJXXXGPX06A/X08A/X10A
REGISTER 8-1:
DMAxCON: DMA CHANNEL x CONTROL REGISTER
R/W-0
CHEN
R/W-0
SIZE
R/W-0
DIR
R/W-0
HALF
R/W-0
U-0
—
U-0
—
U-0
—
NULLW
bit 15
bit 8
U-0
—
U-0
—
R/W-0
R/W-0
U-0
—
U-0
—
R/W-0
R/W-0
AMODE<1:0>
MODE<1:0>
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15
bit 14
bit 13
bit 12
bit 11
CHEN: Channel Enable bit
1= Channel enabled
0= Channel disabled
SIZE: Data Transfer Size bit
1= Byte
0= Word
DIR: Transfer Direction bit (source/destination bus select)
1= Read from DMA RAM address, write to peripheral address
0= Read from peripheral address, write to DMA RAM address
HALF: Early Block Transfer Complete Interrupt Select bit
1= Initiate block transfer complete interrupt when half of the data has been moved
0= Initiate block transfer complete interrupt when all of the data has been moved
NULLW: Null Data Peripheral Write Mode Select bit
1= Null data write to peripheral in addition to DMA RAM write (DIR bit must also be clear)
0= Normal operation
bit 10-6
bit 5-4
Unimplemented: Read as ‘0’
AMODE<1:0>: DMA Channel Operating Mode Select bits
11= Reserved
10= Peripheral Indirect Addressing mode
01= Register Indirect without Post-Increment mode
00= Register Indirect with Post-Increment mode
bit 3-2
bit 1-0
Unimplemented: Read as ‘0’
MODE<1:0>: DMA Channel Operating Mode Select bits
11= One-Shot, Ping-Pong modes enabled (one block transfer from/to each DMA RAM buffer)
10= Continuous, Ping-Pong modes enabled
01= One-Shot, Ping-Pong modes disabled
00= Continuous, Ping-Pong modes disabled
© 2009 Microchip Technology Inc.
Preliminary
DS70592A-page 117
PIC24HJXXXGPX06A/X08A/X10A
REGISTER 8-2:
DMAxREQ: DMA CHANNEL x IRQ SELECT REGISTER
R/W-0
FORCE(1)
bit 15
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
bit 8
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
IRQSEL6(2) IRQSEL5(2) IRQSEL4(2) IRQSEL3(2) IRQSEL2(2)
IRQSEL1(2) IRQSEL0(2)
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15
FORCE: Force DMA Transfer bit(1)
1= Force a single DMA transfer (Manual mode)
0= Automatic DMA transfer initiation by DMA request
bit 14-7
bit 6-0
Unimplemented: Read as ‘0’
IRQSEL<6:0>: DMA Peripheral IRQ Number Select bits(2)
0000000-1111111= DMAIRQ0-DMAIRQ127 selected to be Channel DMAREQ
Note 1: The FORCE bit cannot be cleared by the user. The FORCE bit is cleared by hardware when the forced
DMA transfer is complete.
2: Please see Table 8-1 for a complete listing of IRQ numbers for all interrupt sources.
DS70592A-page 118
Preliminary
© 2009 Microchip Technology Inc.
PIC24HJXXXGPX06A/X08A/X10A
REGISTER 8-3:
DMAxSTA: DMA CHANNEL x RAM START ADDRESS OFFSET REGISTER A
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
bit 8
R/W-0
bit 0
STA<15:8>
bit 15
R/W-0
bit 7
R/W-0
R/W-0
R/W-0
STA<7:0>
R/W-0
R/W-0
R/W-0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-0
STA<15:0>: Primary DMA RAM Start Address bits (source or destination)
REGISTER 8-4:
DMAxSTB: DMA CHANNEL x RAM START ADDRESS OFFSET REGISTER B
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
bit 8
R/W-0
bit 0
STB<15:8>
bit 15
R/W-0
bit 7
R/W-0
R/W-0
R/W-0
STB<7:0>
R/W-0
R/W-0
R/W-0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-0
STB<15:0>: Secondary DMA RAM Start Address bits (source or destination)
© 2009 Microchip Technology Inc.
Preliminary
DS70592A-page 119
PIC24HJXXXGPX06A/X08A/X10A
(1)
REGISTER 8-5:
DMAxPAD: DMA CHANNEL x PERIPHERAL ADDRESS REGISTER
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
bit 8
R/W-0
bit 0
PAD<15:8>
bit 15
R/W-0
bit 7
R/W-0
R/W-0
R/W-0
PAD<7:0>
R/W-0
R/W-0
R/W-0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-0
PAD<15:0>: Peripheral Address Register bits
Note 1: If the channel is enabled (i.e., active), writes to this register may result in unpredictable behavior of the
DMA channel and should be avoided.
(1)
REGISTER 8-6:
DMAxCNT: DMA CHANNEL x TRANSFER COUNT REGISTER
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
R/W-0
R/W-0
CNT<9:8>(2)
bit 15
bit 8
R/W-0
bit 0
R/W-0
bit 7
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
CNT<7:0>(2)
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-10
bit 9-0
Unimplemented: Read as ‘0’
CNT<9:0>: DMA Transfer Count Register bits(2)
Note 1: If the channel is enabled (i.e., active), writes to this register may result in unpredictable behavior of the
DMA channel and should be avoided.
2: Number of DMA transfers = CNT<9:0> + 1.
DS70592A-page 120
Preliminary
© 2009 Microchip Technology Inc.
PIC24HJXXXGPX06A/X08A/X10A
REGISTER 8-7:
DMACS0: DMA CONTROLLER STATUS REGISTER 0
R/C-0
PWCOL7
bit 15
R/C-0
R/C-0
R/C-0
R/C-0
R/C-0
R/C-0
R/C-0
PWCOL6
PWCOL5
PWCOL4
PWCOL3
PWCOL2
PWCOL1
PWCOL0
bit 8
R/C-0
XWCOL7
bit 7
R/C-0
R/C-0
R/C-0
R/C-0
R/C-0
R/C-0
R/C-0
XWCOL6
XWCOL5
XWCOL4
XWCOL3
XWCOL2
XWCOL1
XWCOL0
bit 0
Legend:
C = Clear only bit
W = Writable bit
‘1’ = Bit is set
R = Readable bit
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
-n = Value at POR
bit 15
bit 14
bit 13
bit 12
bit 11
bit 10
bit 9
PWCOL7: Channel 7 Peripheral Write Collision Flag bit
1= Write collision detected
0= No write collision detected
PWCOL6: Channel 6 Peripheral Write Collision Flag bit
1= Write collision detected
0= No write collision detected
PWCOL5: Channel 5 Peripheral Write Collision Flag bit
1= Write collision detected
0= No write collision detected
PWCOL4: Channel 4 Peripheral Write Collision Flag bit
1= Write collision detected
0= No write collision detected
PWCOL3: Channel 3 Peripheral Write Collision Flag bit
1= Write collision detected
0= No write collision detected
PWCOL2: Channel 2 Peripheral Write Collision Flag bit
1= Write collision detected
0= No write collision detected
PWCOL1: Channel 1 Peripheral Write Collision Flag bit
1= Write collision detected
0= No write collision detected
bit 8
PWCOL0: Channel 0 Peripheral Write Collision Flag bit
1= Write collision detected
0= No write collision detected
bit 7
XWCOL7: Channel 7 DMA RAM Write Collision Flag bit
1= Write collision detected
0= No write collision detected
bit 6
XWCOL6: Channel 6 DMA RAM Write Collision Flag bit
1= Write collision detected
0= No write collision detected
bit 5
XWCOL5: Channel 5 DMA RAM Write Collision Flag bit
1= Write collision detected
0= No write collision detected
bit 4
XWCOL4: Channel 4 DMA RAM Write Collision Flag bit
1= Write collision detected
0= No write collision detected
© 2009 Microchip Technology Inc.
Preliminary
DS70592A-page 121
PIC24HJXXXGPX06A/X08A/X10A
REGISTER 8-7:
DMACS0: DMA CONTROLLER STATUS REGISTER 0 (CONTINUED)
bit 3
bit 2
bit 1
bit 0
XWCOL3: Channel 3 DMA RAM Write Collision Flag bit
1= Write collision detected
0= No write collision detected
XWCOL2: Channel 2 DMA RAM Write Collision Flag bit
1= Write collision detected
0= No write collision detected
XWCOL1: Channel 1 DMA RAM Write Collision Flag bit
1= Write collision detected
0= No write collision detected
XWCOL0: Channel 0 DMA RAM Write Collision Flag bit
1= Write collision detected
0= No write collision detected
DS70592A-page 122
Preliminary
© 2009 Microchip Technology Inc.
PIC24HJXXXGPX06A/X08A/X10A
REGISTER 8-8:
DMACS1: DMA CONTROLLER STATUS REGISTER 1
U-0
—
U-0
—
U-0
—
U-0
—
R-1
R-1
R-1
R-1
LSTCH<3:0>
bit 15
bit 8
R-0
PPST7
bit 7
R-0
R-0
R-0
R-0
R-0
R-0
R-0
PPST6
PPST5
PPST4
PPST3
PPST2
PPST1
PPST0
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-12
bit 11-8
Unimplemented: Read as ‘0’
LSTCH<3:0>: Last DMA Channel Active bits
1111= No DMA transfer has occurred since system Reset
1110-1000= Reserved
0111= Last data transfer was by DMA Channel 7
0110= Last data transfer was by DMA Channel 6
0101= Last data transfer was by DMA Channel 5
0100= Last data transfer was by DMA Channel 4
0011= Last data transfer was by DMA Channel 3
0010= Last data transfer was by DMA Channel 2
0001= Last data transfer was by DMA Channel 1
0000= Last data transfer was by DMA Channel 0
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
PPST7: Channel 7 Ping-Pong Mode Status Flag bit
1= DMA7STB register selected
0= DMA7STA register selected
PPST6: Channel 6 Ping-Pong Mode Status Flag bit
1= DMA6STB register selected
0= DMA6STA register selected
PPST5: Channel 5 Ping-Pong Mode Status Flag bit
1= DMA5STB register selected
0= DMA5STA register selected
PPST4: Channel 4 Ping-Pong Mode Status Flag bit
1= DMA4STB register selected
0= DMA4STA register selected
PPST3: Channel 3 Ping-Pong Mode Status Flag bit
1= DMA3STB register selected
0= DMA3STA register selected
PPST2: Channel 2 Ping-Pong Mode Status Flag bit
1= DMA2STB register selected
0= DMA2STA register selected
PPST1: Channel 1 Ping-Pong Mode Status Flag bit
1= DMA1STB register selected
0= DMA1STA register selected
PPST0: Channel 0 Ping-Pong Mode Status Flag bit
1= DMA0STB register selected
0= DMA0STA register selected
© 2009 Microchip Technology Inc.
Preliminary
DS70592A-page 123
PIC24HJXXXGPX06A/X08A/X10A
REGISTER 8-9:
DSADR: MOST RECENT DMA RAM ADDRESS
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
DSADR<15:8>
bit 15
R-0
bit 8
bit 0
R-0
R-0
R-0
R-0
R-0
DSADR<7:0>
bit 7
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-0
DSADR<15:0>: Most Recent DMA RAM Address Accessed by DMA Controller bits
DS70592A-page 124
Preliminary
© 2009 Microchip Technology Inc.
PIC24HJXXXGPX06A/X08A/X10A
• An on-chip PLL to scale the internal operating
frequency to the required system clock frequency
9.0
OSCILLATOR
CONFIGURATION
• The internal FRC oscillator can also be used with
the PLL, thereby allowing full-speed operation
without any external clock generation hardware
Note:
This data sheet summarizes the features
of the PIC24HJXXXGPX06A/X08A/X10A
family of devices. However, it is not
intended to be a comprehensive reference
source. To complement the information in
this data sheet, refer to the “PIC24H
Family Reference Manual”, Section 7.
“Oscillator” (DS70227), which is
available from the Microchip website
(www.microchip.com).
• Clock switching between various clock sources
• Programmable clock postscaler for system power
savings
• A Fail-Safe Clock Monitor (FSCM) that detects
clock failure and takes fail-safe measures
• A Clock Control register (OSCCON)
• Nonvolatile Configuration bits for main oscillator
selection.
The
PIC24HJXXXGPX06A/X08A/X10A
oscillator
A simplified diagram of the oscillator system is shown
in Figure 9-1.
system provides:
• Various external and internal oscillator options as
clock sources
FIGURE 9-1:
PIC24HJXXXGPX06A/X08A/X10A OSCILLATOR SYSTEM DIAGRAM
PIC24H
Primary Oscillator
POSCMD<1:0>
OSC1
DOZE<2:0>
XT, HS, EC
S2
(2)
R
XTPLL, HSPLL,
ECPLL, FRCPLL
S3
S1
FCY
FP
(1)
S1/S3
PLL
OSC2
÷ 2
FRC
Oscillator
FRCDIVN
FOSC
S7
FRCDIV<2:0>
TUN<5:0>
FRCDIV16
FRC
S6
S0
÷ 16
LPRC
SOSC
LPRC
Oscillator
S5
Secondary Oscillator
SOSCO
SOSCI
S4
LPOSCEN
Clock Switch
Reset
Clock Fail
S7
NOSC<2:0> FNOSC<2:0>
WDT, PWRT,
FSCM
Timer 1
Note 1: See Figure 9-2 for PLL details.
2: If the Oscillator is used with XT or HS modes, an extended parallel resistor with the value of 1 MΩ must be connected.
© 2009 Microchip Technology Inc.
Preliminary
DS70592A-page 125
PIC24HJXXXGPX06A/X08A/X10A
(FOSC<1:0>), select the oscillator source that is used at
a Power-on Reset. The FRC primary oscillator is the
default (unprogrammed) selection.
9.1
CPU Clocking System
There are seven system clock options provided by the
PIC24HJXXXGPX06A/X08A/X10A:
The Configuration bits allow users to choose between
twelve different clock modes, shown in Table 9-1.
• FRC Oscillator
• FRC Oscillator with PLL
• Primary (XT, HS or EC) Oscillator
• Primary Oscillator with PLL
• Secondary (LP) Oscillator
• LPRC Oscillator
The output of the oscillator (or the output of the PLL if
a PLL mode has been selected) FOSC is divided by 2 to
generate the device instruction clock (FCY) and the
peripheral clock time base (FP). FCY defines the
operating speed of the device, and speeds up to 40
MHz are supported by the PIC24HJXXXGPX06A/
X08A/X10A architecture.
• FRC Oscillator with postscaler
9.1.1
SYSTEM CLOCK SOURCES
Instruction execution speed or device operating
frequency, FCY, is given by:
The FRC (Fast RC) internal oscillator runs at a nominal
frequency of 7.37 MHz. The user software can tune the
FRC frequency. User software can optionally specify a
factor (ranging from 1:2 to 1:256) by which the FRC
clock frequency is divided. This factor is selected using
the FRCDIV<2:0> (CLKDIV<10:8>) bits.
EQUATION 9-1:
DEVICE OPERATING
FREQUENCY
FOSC
2
-------------
FCY =
The primary oscillator can use one of the following as
its clock source:
9.1.3
PLL CONFIGURATION
1. XT (Crystal): Crystals and ceramic resonators in
the range of 3 MHz to 10 MHz. The crystal is
connected to the OSC1 and OSC2 pins.
The primary oscillator and internal FRC oscillator can
optionally use an on-chip PLL to obtain higher speeds
of operation. The PLL provides a significant amount of
flexibility in selecting the device operating speed. A
block diagram of the PLL is shown in Figure 9-2.
2. HS (High-Speed Crystal): Crystals in the range
of 10 MHz to 40 MHz. The crystal is connected
to the OSC1 and OSC2 pins.
The output of the primary oscillator or FRC, denoted as
‘FIN’, is divided down by a prescale factor (N1) of 2, 3,
... or 33 before being provided to the PLL’s Voltage
Controlled Oscillator (VCO). The input to the VCO must
be selected to be in the range of 0.8 MHz to 8 MHz.
Since the minimum prescale factor is 2, this implies that
FIN must be chosen to be in the range of 1.6 MHz to 16
MHz. The prescale factor ‘N1’ is selected using the
PLLPRE<4:0> bits (CLKDIV<4:0>).
3. EC (External Clock): External clock signal is
directly applied to the OSC1 pin.
The secondary (LP) oscillator is designed for low power
and uses a 32.768 kHz crystal or ceramic resonator.
The LP oscillator uses the SOSCI and SOSCO pins.
The LPRC (Low-Power RC) internal oscIllator runs at a
nominal frequency of 32.768 kHz. It is also used as a
reference clock by the Watchdog Timer (WDT) and
Fail-Safe Clock Monitor (FSCM).
The PLL Feedback Divisor, selected using the
The clock signals generated by the FRC and primary
oscillators can be optionally applied to an on-chip
Phase Locked Loop (PLL) to provide a wide range of
output frequencies for device operation. PLL
configuration is described in Section 9.1.3 “PLL
Configuration”.
PLLDIV<8:0> bits (PLLFBD<8:0>), provides a factor ‘M’,
by which the input to the VCO is multiplied. This factor
must be selected such that the resulting VCO output
frequency is in the range of 100 MHz to 200 MHz.
The VCO output is further divided by a postscale factor
‘N2’. This factor is selected using the PLLPOST<1:0>
bits (CLKDIV<7:6>). ‘N2’ can be either 2, 4 or 8, and
must be selected such that the PLL output frequency
(FOSC) is in the range of 12.5 MHz to 80 MHz, which
generates device operating speeds of 6.25-40 MIPS.
The FRC frequency depends on the FRC accuracy
(see Table 24-19) and the value of the FRC Oscillator
Tuning register (see Register 9-4).
9.1.2
SYSTEM CLOCK SELECTION
For a primary oscillator or FRC oscillator, output ‘FIN’,
the PLL output ‘FOSC’ is given by:
The oscillator source that is used at a device Power-on
Reset event is selected using Configuration bit settings.
The oscillator Configuration bit settings are located in the
Configuration registers in the program memory. (Refer to
Section 21.1 “Configuration Bits” for further details.)
The Initial Oscillator Selection Configuration bits,
FNOSC<2:0> (FOSCSEL<2:0>), and the Primary Oscil-
lator Mode Select Configuration bits, POSCMD<1:0>
EQUATION 9-2:
FOSC CALCULATION
M
N1 ⋅ N2
⎛
⎝
⎞
⎠
------------------
FOSC = FIN ⋅
DS70592A-page 126
Preliminary
© 2009 Microchip Technology Inc.
PIC24HJXXXGPX06A/X08A/X10A
For example, suppose a 10 MHz crystal is being used,
with “XT with PLL” being the selected oscillator mode.
If PLLPRE<4:0> = 0, then N1 = 2. This yields a VCO
input of 10/2 = 5 MHz, which is within the acceptable
range of 0.8-8 MHz. If PLLDIV<8:0> = 0x1E, then
M = 32. This yields a VCO output of 5 x 32 = 160 MHz,
which is within the 100-200 MHz ranged needed.
EQUATION 9-3:
XT WITH PLL MODE
EXAMPLE
FOSC
1 10000000 ⋅ 32
⎛
-- ---------------------------------
⎞
⎠
-------------
FCY =
=
= 40 MIPS
⎝
2
2
2 ⋅ 2
If PLLPOST<1:0> = 0, then N2 = 2. This provides a
Fosc of 160/2 = 80 MHz. The resultant device operating
speed is 80/2 = 40 MIPS.
FIGURE 9-2:
PIC24HJXXXGPX06A/X08A/X10A PLL BLOCK DIAGRAM
FVCO
0.8-8.0 MHz
100-200 MHz
Here(1)
12.5-80 MHz
Here(1)
Here(1)
Source (Crystal, External Clock
or Internal RC)
FOSC
PLLPRE
VCO
PLLPOST
X
PLLDIV
N1
Divide by
2-33
N2
Divide by
2, 4, 8
M
Divide by
2-513
Note 1: This frequency range must be satisfied at all times.
TABLE 9-1:
CONFIGURATION BIT VALUES FOR CLOCK SELECTION
Oscillator Mode
Oscillator Source
POSCMD<1:0>
FNOSC<2:0>
Note
1, 2
Fast RC Oscillator with Divide-by-N
(FRCDIVN)
Internal
xx
111
Internal
xx
110
1
Fast RC Oscillator with Divide-by-16
(FRCDIV16)
Low-Power RC Oscillator (LPRC)
Internal
Secondary
Primary
xx
xx
10
101
100
011
1
1
Secondary (Timer1) Oscillator (SOSC)
Primary Oscillator (HS) with PLL
(HSPLL)
—
Primary Oscillator (XT) with PLL
(XTPLL)
Primary
Primary
01
00
011
011
—
1
Primary Oscillator (EC) with PLL
(ECPLL)
Primary Oscillator (HS)
Primary
Primary
Primary
Internal
Internal
10
01
00
xx
xx
010
010
010
001
000
—
—
1
Primary Oscillator (XT)
Primary Oscillator (EC)
Fast RC Oscillator with PLL (FRCPLL)
Fast RC Oscillator (FRC)
1
1
Note 1: OSC2 pin function is determined by the OSCIOFNC Configuration bit.
2: This is the default oscillator mode for an unprogrammed (erased) device.
© 2009 Microchip Technology Inc.
Preliminary
DS70592A-page 127
PIC24HJXXXGPX06A/X08A/X10A
(1)
REGISTER 9-1:
OSCCON: OSCILLATOR CONTROL REGISTER
U-0
—
R-0
R-0
R-0
U-0
—
R/W-y
R/W-y
NOSC<2:0>(2)
R/W-y
bit 8
COSC<2:0>
bit 15
R/W-0
CLKLOCK
bit 7
U-0
—
R-0
U-0
—
R/C-0
CF
U-0
—
R/W-0
R/W-0
LOCK
LPOSCEN
OSWEN
bit 0
Legend:
y = Value set from Configuration bits on POR
C = Clear only bit
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
bit 15
Unimplemented: Read as ‘0’
bit 14-12
COSC<2:0>: Current Oscillator Selection bits (read-only)
000= Fast RC oscillator (FRC)
001= Fast RC oscillator (FRC) with PLL
010= Primary oscillator (XT, HS, EC)
011= Primary oscillator (XT, HS, EC) with PLL
100= Secondary oscillator (SOSC)
101= Low-Power RC oscillator (LPRC)
110= Fast RC oscillator (FRC) with Divide-by-16
111= Fast RC oscillator (FRC) with Divide-by-n
bit 11
Unimplemented: Read as ‘0’
NOSC<2:0>: New Oscillator Selection bits(2)
bit 10-8
000= Fast RC oscillator (FRC)
001= Fast RC oscillator (FRC) with PLL
010= Primary oscillator (XT, HS, EC)
011= Primary oscillator (XT, HS, EC) with PLL
100= Secondary oscillator (SOSC)
101= Low-Power RC oscillator (LPRC)
110= Fast RC oscillator (FRC) with Divide-by-16
111= Fast RC oscillator (FRC) with Divide-by-n
bit 7
CLKLOCK: Clock Lock Enable bit
1= If (FCKSM0 = 1), then clock and PLL configurations are locked
If (FCKSM0 = 0), then clock and PLL configurations may be modified
0= Clock and PLL selections are not locked, configurations may be modified
bit 6
bit 5
Unimplemented: Read as ‘0’
LOCK: PLL Lock Status bit (read-only)
1= Indicates that PLL is in lock, or PLL start-up timer is satisfied
0= Indicates that PLL is out of lock, start-up timer is in progress or PLL is disabled
bit 4
bit 3
Unimplemented: Read as ‘0’
CF: Clock Fail Detect bit (read/clear by application)
1= FSCM has detected clock failure
0= FSCM has not detected clock failure
bit 2
Unimplemented: Read as ‘0’
Note 1: Writes to this register require an unlock sequence. Refer to Section 7. “Oscillator” (DS70227) in the
“PIC24H Family Reference Manual” (available from the Microchip website) for details.
2: Direct clock switches between any primary oscillator mode with PLL and FRCPLL mode are not permitted.
This applies to clock switches in either direction. In these instances, the application must switch to FRC mode
as a transition clock source between the two PLL modes.
DS70592A-page 128
Preliminary
© 2009 Microchip Technology Inc.
PIC24HJXXXGPX06A/X08A/X10A
(1)
REGISTER 9-1:
OSCCON: OSCILLATOR CONTROL REGISTER (CONTINUED)
bit 1
LPOSCEN: Secondary (LP) Oscillator Enable bit
1= Enable secondary oscillator
0= Disable secondary oscillator
bit 0
OSWEN: Oscillator Switch Enable bit
1= Request oscillator switch to selection specified by NOSC<2:0> bits
0= Oscillator switch is complete
Note 1: Writes to this register require an unlock sequence. Refer to Section 7. “Oscillator” (DS70227) in the
“PIC24H Family Reference Manual” (available from the Microchip website) for details.
2: Direct clock switches between any primary oscillator mode with PLL and FRCPLL mode are not permitted.
This applies to clock switches in either direction. In these instances, the application must switch to FRC mode
as a transition clock source between the two PLL modes.
© 2009 Microchip Technology Inc.
Preliminary
DS70592A-page 129
PIC24HJXXXGPX06A/X08A/X10A
REGISTER 9-2:
CLKDIV: CLOCK DIVISOR REGISTER
R/W-0
ROI
R/W-0
R/W-1
R/W-1
R/W-0
DOZEN(1)
R/W-0
R/W-0
R/W-0
bit 8
R/W-0
bit 0
DOZE<2:0>
FRCDIV<2:0>
bit 15
R/W-0
R/W-1
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
PLLPOST<1:0>
PLLPRE<4:0>
bit 7
Legend:
y = Value set from Configuration bits on POR
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15
ROI: Recover on Interrupt bit
1= Interrupts will clear the DOZEN bit and the processor clock/peripheral clock ratio is set to 1:1
0= Interrupts have no effect on the DOZEN bit
bit 14-12
DOZE<2:0>: Processor Clock Reduction Select bits
000= FCY/1
001= FCY/2
010= FCY/4
011= FCY/8 (default)
100= FCY/16
101= FCY/32
110= FCY/64
111= FCY/128
bit 11
DOZEN: DOZE Mode Enable bit(1)
1= DOZE<2:0> field specifies the ratio between the peripheral clocks and the processor clocks
0= Processor clock/peripheral clock ratio forced to 1:1
bit 10-8
FRCDIV<2:0>: Internal Fast RC Oscillator Postscaler bits
000= FRC divide by 1 (default)
001= FRC divide by 2
010= FRC divide by 4
011= FRC divide by 8
100= FRC divide by 16
101= FRC divide by 32
110= FRC divide by 64
111= FRC divide by 256
bit 7-6
PLLPOST<1:0>: PLL VCO Output Divider Select bits (also denoted as ‘N2’, PLL postscaler)
00= Output/2
01= Output/4 (default)
10= Reserved
11= Output/8
bit 5
Unimplemented: Read as ‘0’
bit 4-0
PLLPRE<4:0>: PLL Phase Detector Input Divider bits (also denoted as ‘N1’, PLL prescaler)
00000= Input/2 (default)
00001= Input/3
•
•
•
11111= Input/33
Note 1: This bit is cleared when the ROI bit is set and an interrupt occurs.
DS70592A-page 130
Preliminary
© 2009 Microchip Technology Inc.
PIC24HJXXXGPX06A/X08A/X10A
REGISTER 9-3:
PLLFBD: PLL FEEDBACK DIVISOR REGISTER
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
R/W-0
PLLDIV<8>
bit 8
bit 15
R/W-0
bit 7
R/W-0
R/W-1
R/W-1
R/W-0
R/W-0
R/W-0
R/W-0
bit 0
PLLDIV<7:0>
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-9
bit 8-0
Unimplemented: Read as ‘0’
PLLDIV<8:0>: PLL Feedback Divisor bits (also denoted as ‘M’, PLL multiplier)
000000000= 2
000000001= 3
000000010= 4
•
•
•
000110000= 50 (default)
•
•
•
111111111= 513
© 2009 Microchip Technology Inc.
Preliminary
DS70592A-page 131
PIC24HJXXXGPX06A/X08A/X10A
REGISTER 9-4:
OSCTUN: FRC OSCILLATOR TUNING REGISTER
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
bit 15
bit 8
R/W-0
bit 0
U-0
—
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
TUN<5:0>(1)
bit 7
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-6
bit 5-0
Unimplemented: Read as ‘0’
TUN<5:0>: FRC Oscillator Tuning bits(1)
011111= Center frequency + 11.625% (8.23 MHz)
011110= Center frequency + 11.25% (8.20 MHz)
•
•
•
000001= Center frequency + 0.375% (7.40 MHz)
000000= Center frequency (7.37 MHz nominal)
111111= Center frequency – 0.375% (7.345 MHz)
•
•
•
100001= Center frequency – 11.625% (6.52 MHz)
100000= Center frequency – 12% (6.49 MHz)
Note 1: OSCTUN functionality has been provided to help customers compensate for temperature effects on the
FRC frequency over a wide range of temperatures. The tuning step size is an approximation and is neither
characterized nor tested.
DS70592A-page 132
Preliminary
© 2009 Microchip Technology Inc.
PIC24HJXXXGPX06A/X08A/X10A
2. If a valid clock switch has been initiated, the
9.2
Clock Switching Operation
LOCK
(OSCCON<5>)
and
the
CF
Applications are free to switch between any of the four
clock sources (Primary, LP, FRC and LPRC) under
software control at any time. To limit the possible side
effects that could result from this flexibility,
PIC24HJXXXGPX06A/X08A/X10A devices have a
safeguard lock built into the switch process.
(OSCCON<3>) status bits are cleared.
3. The new oscillator is turned on by the hardware
if it is not currently running. If a crystal oscillator
must be turned on, the hardware waits until the
Oscillator Start-up Timer (OST) expires. If the
new source is using the PLL, the hardware waits
until a PLL lock is detected (LOCK = 1).
Note:
Primary Oscillator mode has three different
submodes (XT, HS and EC) which are
determined by the POSCMD<1:0> Config-
uration bits. While an application can
switch to and from Primary Oscillator
mode in software, it cannot switch
between the different primary submodes
without reprogramming the device.
4. The hardware waits for 10 clock cycles from the
new clock source and then performs the clock
switch.
5. The hardware clears the OSWEN bit to indicate a
successful clock transition. In addition, the NOSC
bit values are transferred to the COSC status bits.
6. The old clock source is turned off at this time,
with the exception of LPRC (if WDT or FSCM
are enabled) or LP (if LPOSCEN remains set).
9.2.1
ENABLING CLOCK SWITCHING
To enable clock switching, the FCKSM1 Configuration
bit in the Configuration register must be programmed to
‘0’. (Refer to Section 21.1 “Configuration Bits” for
further details.) If the FCKSM1 Configuration bit is
unprogrammed (‘1’), the clock switching function and
Fail-Safe Clock Monitor function are disabled. This is
the default setting.
Note 1: The processor continues to execute code
throughout the clock switching sequence.
Timing sensitive code should not be
executed during this time.
2: Direct clock switches between any primary
oscillator mode with PLL and FRCPLL
mode are not permitted. This applies to
clock switches in either direction. In these
instances, the application must switch to
FRC mode as a transition clock source
between the two PLL modes.
The NOSC control bits (OSCCON<10:8>) do not
control the clock selection when clock switching is
disabled. However, the COSC bits (OSCCON<14:12>)
reflect the clock source selected by the FNOSC
Configuration bits.
3: Refer to Section 7. “Oscillator”
(DS70227) in the “PIC24H Family
Reference Manual” for details.
The OSWEN control bit (OSCCON<0>) has no effect
when clock switching is disabled. It is held at ‘0’ at all
times.
9.2.2
OSCILLATOR SWITCHING SEQUENCE
9.3
Fail-Safe Clock Monitor (FSCM)
At a minimum, performing a clock switch requires this
basic sequence:
The Fail-Safe Clock Monitor (FSCM) allows the device
to continue to operate even in the event of an oscillator
failure. The FSCM function is enabled by programming.
If the FSCM function is enabled, the LPRC internal
oscillator runs at all times (except during Sleep mode)
and is not subject to control by the Watchdog Timer.
1. If
desired,
read
the
COSC
bits
(OSCCON<14:12>) to determine the current
oscillator source.
2. Perform the unlock sequence to allow a write to
the OSCCON register high byte.
If an oscillator failure occurs, the FSCM generates a
clock failure trap event and switches the system clock
over to the FRC oscillator. Then the application
program can either attempt to restart the oscillator or
execute a controlled shutdown. The trap can be treated
as a warm Reset by simply loading the Reset address
into the oscillator fail trap vector.
3. Write the appropriate value to the NOSC control
bits (OSCCON<10:8>) for the new oscillator
source.
4. Perform the unlock sequence to allow a write to
the OSCCON register low byte.
5. Set the OSWEN bit to initiate the oscillator
switch.
If the PLL multiplier is used to scale the system clock,
the internal FRC is also multiplied by the same factor
on clock failure. Essentially, the device switches to
FRC with PLL on a clock failure.
Once the basic sequence is completed, the system
clock hardware responds automatically as follows:
1. The clock switching hardware compares the
COSC status bits with the new value of the
NOSC control bits. If they are the same, then the
clock switch is a redundant operation. In this
case, the OSWEN bit is cleared automatically
and the clock switch is aborted.
© 2009 Microchip Technology Inc.
Preliminary
DS70592A-page 133
PIC24HJXXXGPX06A/X08A/X10A
NOTES:
DS70592A-page 134
Preliminary
© 2009 Microchip Technology Inc.
PIC24HJXXXGPX06A/X08A/X10A
10.2 Instruction-Based Power-Saving
Modes
10.0 POWER-SAVING FEATURES
Note:
This data sheet summarizes the features
of the PIC24HJXXXGPX06A/X08A/X10A
family of devices. However, it is not
intended to be a comprehensive reference
source. To complement the information in
this data sheet, refer to the “PIC24H
Family Reference Manual”, Section 9.
“Watchdog Timer and Power-Saving
Modes” (DS70236), which is available
PIC24HJXXXGPX06A/X08A/X10A devices have two
special power-saving modes that are entered through
the execution of a special PWRSAV instruction. Sleep
mode stops clock operation and halts all code execu-
tion. Idle mode halts the CPU and code execution, but
allows peripheral modules to continue operation. The
assembly syntax of the PWRSAVinstruction is shown in
Example 10-1.
from
the
Microchip
website
Note: SLEEP_MODE and IDLE_MODE are
constants defined in the assembler
include file for the selected device.
(www.microchip.com).
The PIC24HJXXXGPX06A/X08A/X10A devices pro-
vide the ability to manage power consumption by selec-
tively managing clocking to the CPU and the
peripherals. In general, a lower clock frequency and a
reduction in the number of circuits being clocked con-
Sleep and Idle modes can be exited as a result of an
enabled interrupt, WDT time-out or a device Reset. When
the device exits these modes, it is said to “wake-up”.
stitutes
lower
consumed
power.
10.2.1
SLEEP MODE
PIC24HJXXXGPX06A/X08A/X10A devices can man-
age power consumption in four different ways:
Sleep mode has these features:
• The system clock source is shut down. If an
on-chip oscillator is used, it is turned off.
• Clock frequency
• Instruction-based Sleep and Idle modes
• Software-controlled Doze mode
• Selective peripheral control in software
• The device current consumption is reduced to a
minimum, provided that no I/O pin is sourcing
current.
Combinations of these methods can be used to selec-
tively tailor an application’s power consumption while
still maintaining critical application features, such as
timing-sensitive communications.
• The Fail-Safe Clock Monitor does not operate
during Sleep mode since the system clock source
is disabled.
• The LPRC clock continues to run in Sleep mode if
the WDT is enabled.
10.1 Clock Frequency and Clock
Switching
• The WDT, if enabled, is automatically cleared
prior to entering Sleep mode.
• Some device features or peripherals may continue
to operate in Sleep mode. This includes items such
as the input change notification on the I/O ports, or
peripherals that use an external clock input. Any
peripheral that requires the system clock source for
its operation is disabled in Sleep mode.
PIC24HJXXXGPX06A/X08A/X10A devices allow a
wide range of clock frequencies to be selected under
application control. If the system clock configuration is
not locked, users can choose low-power or high-preci-
sion oscillators by simply changing the NOSC bits
(OSCCON<10:8>). The process of changing a system
clock during operation, as well as limitations to the pro-
cess, are discussed in more detail in Section 9.0
“Oscillator Configuration”.
The device will wake-up from Sleep mode on any of
these events:
• Any interrupt source that is individually enabled.
• Any form of device Reset.
• A WDT time-out.
On wake-up from Sleep, the processor restarts with the
same clock source that was active when Sleep mode
was entered.
EXAMPLE 10-1:
PWRSAVINSTRUCTION SYNTAX
PWRSAV #SLEEP_MODE
PWRSAV #IDLE_MODE
; Put the device into SLEEP mode
; Put the device into IDLE mode
© 2009 Microchip Technology Inc.
Preliminary
DS70592A-page 135
PIC24HJXXXGPX06A/X08A/X10A
Doze mode is enabled by setting the DOZEN bit (CLK-
DIV<11>). The ratio between peripheral and core clock
speed is determined by the DOZE<2:0> bits (CLK-
DIV<14:12>). There are eight possible configurations,
from 1:1 to 1:128, with 1:1 being the default setting.
10.2.2
IDLE MODE
Idle mode has these features:
• The CPU stops executing instructions.
• The WDT is automatically cleared.
• The system clock source remains active. By
default, all peripheral modules continue to operate
normally from the system clock source, but can
also be selectively disabled (see Section 10.4
“Peripheral Module Disable”).
It is also possible to use Doze mode to selectively
reduce power consumption in event-driven applica-
tions. This allows clock-sensitive functions, such as
synchronous communications, to continue without
interruption while the CPU idles, waiting for something
to invoke an interrupt routine. Enabling the automatic
return to full-speed CPU operation on interrupts is
enabled by setting the ROI bit (CLKDIV<15>). By
default, interrupt events have no effect on Doze mode
operation.
• If the WDT or FSCM is enabled, the LPRC also
remains active.
The device will wake from Idle mode on any of these
events:
• Any interrupt that is individually enabled.
• Any device Reset.
For example, suppose the device is operating at
20 MIPS and the CAN module has been configured for
500 kbps based on this device operating speed. If the
device is now placed in Doze mode with a clock
frequency ratio of 1:4, the CAN module continues to
communicate at the required bit rate of 500 kbps, but
the CPU now starts executing instructions at a
frequency of 5 MIPS.
• A WDT time-out.
On wake-up from Idle, the clock is reapplied to the CPU
and instruction execution begins immediately, starting
with the instruction following the PWRSAVinstruction, or
the first instruction in the ISR.
10.2.3
INTERRUPTS COINCIDENT WITH
POWER SAVE INSTRUCTIONS
10.4 Peripheral Module Disable
Any interrupt that coincides with the execution of a
PWRSAVinstruction is held off until entry into Sleep or
Idle mode has completed. The device then wakes up
from Sleep or Idle mode.
The Peripheral Module Disable (PMD) registers
provide a method to disable a peripheral module by
stopping all clock sources supplied to that module.
When a peripheral is disabled via the appropriate PMD
control bit, the peripheral is in a minimum power
consumption state. The control and status registers
associated with the peripheral are also disabled, so
writes to those registers will have no effect and read
values will be invalid.
10.3 Doze Mode
Generally, changing clock speed and invoking one of the
power-saving modes are the preferred strategies for
reducing power consumption. There may be cir-
cumstances, however, where this is not practical. For
example, it may be necessary for an application to main-
tain uninterrupted synchronous communication, even
while it is doing nothing else. Reducing system clock
speed may introduce communication errors, while using
a power-saving mode may stop communications
completely.
A peripheral module is only enabled if both the associ-
ated bit in the PMD register is cleared and the peripheral
is supported by the specific dsPIC® DSC variant. If the
peripheral is present in the device, it is enabled in the
PMD register by default.
Note:
If a PMD bit is set, the corresponding mod-
ule is disabled after a delay of 1 instruction
cycle. Similarly, if a PMD bit is cleared, the
corresponding module is enabled after a
delay of 1 instruction cycle (assuming the
module control registers are already
configured to enable module operation).
Doze mode is a simple and effective alternative method
to reduce power consumption while the device is still
executing code. In this mode, the system clock contin-
ues to operate from the same source and at the same
speed. Peripheral modules continue to be clocked at
the same speed, while the CPU clock speed is
reduced. Synchronization between the two clock
domains is maintained, allowing the peripherals to
access the SFRs while the CPU executes code at a
slower rate.
DS70592A-page 136
Preliminary
© 2009 Microchip Technology Inc.
PIC24HJXXXGPX06A/X08A/X10A
REGISTER 10-1: PMD1: PERIPHERAL MODULE DISABLE CONTROL REGISTER 1
R/W-0
T5MD
R/W-0
T4MD
R/W-0
T3MD
R/W-0
T2MD
R/W-0
T1MD
U-0
—
U-0
—
U-0
—
bit 15
bit 8
R/W-0
R/W-0
U2MD
R/W-0
U1MD
R/W-0
R/W-0
R/W-0
C2MD
R/W-0
C1MD
R/W-0
AD1MD(1)
I2C1MD
SPI2MD
SPI1MD
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15
bit 14
bit 13
bit 12
bit 11
T5MD: Timer5 Module Disable bit
1= Timer5 module is disabled
0= Timer5 module is enabled
T4MD: Timer4 Module Disable bit
1= Timer4 module is disabled
0= Timer4 module is enabled
T3MD: Timer3 Module Disable bit
1= Timer3 module is disabled
0= Timer3 module is enabled
T2MD: Timer2 Module Disable bit
1= Timer2 module is disabled
0= Timer2 module is enabled
T1MD: Timer1 Module Disable bit
1= Timer1 module is disabled
0= Timer1 module is enabled
bit 10-8
bit 7
Unimplemented: Read as ‘0’
I2C1MD: I2C1 Module Disable bit
1= I2C1 module is disabled
0= I2C1 module is enabled
bit 6
bit 5
bit 4
bit 3
bit 2
U2MD: UART2 Module Disable bit
1= UART2 module is disabled
0= UART2 module is enabled
U1MD: UART1 Module Disable bit
1= UART1 module is disabled
0= UART1 module is enabled
SPI2MD: SPI2 Module Disable bit
1= SPI2 module is disabled
0= SPI2 module is enabled
SPI1MD: SPI1 Module Disable bit
1= SPI1 module is disabled
0= SPI1 module is enabled
C2MD: ECAN2 Module Disable bit
1= ECAN2 module is disabled
0= ECAN2 module is enabled
© 2009 Microchip Technology Inc.
Preliminary
DS70592A-page 137
PIC24HJXXXGPX06A/X08A/X10A
REGISTER 10-1: PMD1: PERIPHERAL MODULE DISABLE CONTROL REGISTER 1 (CONTINUED)
bit 1
C1MD: ECAN1 Module Disable bit
1= ECAN1 module is disabled
0= ECAN1 module is enabled
bit 0
AD1MD: ADC1 Module Disable bit(1)
1= ADC1 module is disabled
0= ADC1 module is enabled
Note 1: PCFGx bits will have no effect if ADC module is disabled by setting this bit. In this case all port pins
multiplexed with ANx will be in Digital mode.
DS70592A-page 138
Preliminary
© 2009 Microchip Technology Inc.
PIC24HJXXXGPX06A/X08A/X10A
REGISTER 10-2: PMD2: PERIPHERAL MODULE DISABLE CONTROL REGISTER 2
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
IC8MD
IC7MD
IC6MD
IC5MD
IC4MD
IC3MD
IC2MD
IC1MD
bit 15
bit 8
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
OC8MD
OC7MD
OC6MD
OC5MD
OC4MD
OC3MD
OC2MD
OC1MD
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
-n = Value at POR
bit 15
bit 14
bit 13
bit 12
bit 11
bit 10
bit 9
IC8MD: Input Capture 8 Module Disable bit
1= Input Capture 8 module is disabled
0= Input Capture 8 module is enabled
IC7MD: Input Capture 7 Module Disable bit
1= Input Capture 7 module is disabled
0= Input Capture 7 module is enabled
IC6MD: Input Capture 6 Module Disable bit
1= Input Capture 6 module is disabled
0= Input Capture 6 module is enabled
IC5MD: Input Capture 5 Module Disable bit
1= Input Capture 5 module is disabled
0= Input Capture 5 module is enabled
IC4MD: Input Capture 4 Module Disable bit
1= Input Capture 4 module is disabled
0= Input Capture 4 module is enabled
IC3MD: Input Capture 3 Module Disable bit
1= Input Capture 3 module is disabled
0= Input Capture 3 module is enabled
IC2MD: Input Capture 2 Module Disable bit
1= Input Capture 2 module is disabled
0= Input Capture 2 module is enabled
bit 8
IC1MD: Input Capture 1 Module Disable bit
1= Input Capture 1 module is disabled
0= Input Capture 1 module is enabled
bit 7
OC8MD: Output Compare 8 Module Disable bit
1= Output Compare 8 module is disabled
0= Output Compare 8 module is enabled
bit 6
OC7MD: Output Compare 4 Module Disable bit
1= Output Compare 7 module is disabled
0= Output Compare 7 module is enabled
bit 5
OC6MD: Output Compare 6 Module Disable bit
1= Output Compare 6 module is disabled
0= Output Compare 6 module is enabled
bit 4
OC5MD: Output Compare 5 Module Disable bit
1= Output Compare 5 module is disabled
0= Output Compare 5 module is enabled
© 2009 Microchip Technology Inc.
Preliminary
DS70592A-page 139
PIC24HJXXXGPX06A/X08A/X10A
REGISTER 10-2: PMD2: PERIPHERAL MODULE DISABLE CONTROL REGISTER 2 (CONTINUED)
bit 3
bit 2
bit 1
bit 0
OC4MD: Output Compare 4 Module Disable bit
1= Output Compare 4 module is disabled
0= Output Compare 4 module is enabled
OC3MD: Output Compare 3 Module Disable bit
1= Output Compare 3 module is disabled
0= Output Compare 3 module is enabled
OC2MD: Output Compare 2 Module Disable bit
1= Output Compare 2 module is disabled
0= Output Compare 2 module is enabled
OC1MD: Output Compare 1 Module Disable bit
1= Output Compare 1 module is disabled
0= Output Compare 1 module is enabled
DS70592A-page 140
Preliminary
© 2009 Microchip Technology Inc.
PIC24HJXXXGPX06A/X08A/X10A
REGISTER 10-3: PMD3: PERIPHERAL MODULE DISABLE CONTROL REGISTER 3
R/W-0
T9MD
R/W-0
T8MD
R/W-0
T7MD
R/W-0
T6MD
U-0
—
U-0
—
U-0
—
U-0
—
bit 15
bit 8
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
R/W-0
R/W-0
AD2MD(1)
I2C2MD
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15
bit 14
bit 13
bit 12
T9MD: Timer9 Module Disable bit
1= Timer9 module is disabled
0= Timer9 module is enabled
T8MD: Timer8 Module Disable bit
1= Timer8 module is disabled
0= Timer8 module is enabled
T7MD: Timer7 Module Disable bit
1= Timer7 module is disabled
0= Timer7 module is enabled
T6MD: Timer6 Module Disable bit
1= Timer6 module is disabled
0= Timer6 module is enabled
bit 11-2
bit 1
Unimplemented: Read as ‘0’
I2C2MD: I2C2 Module Disable bit
1= I2C2 module is disabled
0= I2C2 module is enabled
bit 0
AD2MD: AD2 Module Disable bit(1)
1= AD2 module is disabled
0= AD2 module is enabled
Note 1: PCFGx bits will have no effect if ADC module is disabled by setting this bit. In this case all port pins
multiplexed with ANx will be in Digital mode.
© 2009 Microchip Technology Inc.
Preliminary
DS70592A-page 141
PIC24HJXXXGPX06A/X08A/X10A
NOTES:
DS70592A-page 142
Preliminary
© 2009 Microchip Technology Inc.
PIC24HJXXXGPX06A/X08A/X10A
When a peripheral is enabled and actively driving an
associated pin, the use of the pin as a general purpose
11.0 I/O PORTS
output pin is disabled. The I/O pin may be read, but the
output driver for the parallel port bit will be disabled. If
a peripheral is enabled, but the peripheral is not
actively driving a pin, that pin may be driven by a port.
Note:
This data sheet summarizes the features
of the PIC24HJXXXGPX06A/X08A/X10A
family of devices. However, it is not
intended to be a comprehensive reference
source. To complement the information in
this data sheet, refer to the “PIC24H
Family Reference Manual”, Section 10.
“I/O Ports” (DS70230), which is available
All port pins have three registers directly associated
with their operation as digital I/O. The data direction
register (TRISx) determines whether the pin is an input
or an output. If the data direction bit is a ‘1’, then the pin
is an input. All port pins are defined as inputs after a
Reset. Reads from the latch (LATx), read the latch.
Writes to the latch, write the latch. Reads from the port
(PORTx), read the port pins, while writes to the port
pins, write the latch.
from
the
Microchip
website
(www.microchip.com).
All of the device pins (except VDD, VSS, MCLR and
OSC1/CLKIN) are shared between the peripherals and
the parallel I/O ports. All I/O input ports feature Schmitt
Trigger inputs for improved noise immunity.
Any bit and its associated data and control registers
that are not valid for a particular device will be
disabled. That means the corresponding LATx and
TRISx registers and the port pins will read as zeros.
11.1 Parallel I/O (PIO) Ports
A parallel I/O port that shares a pin with a peripheral is,
in general, subservient to the peripheral. The periph-
eral’s output buffer data and control signals are
provided to a pair of multiplexers. The multiplexers
select whether the peripheral or the associated port
has ownership of the output data and control signals of
the I/O pin. The logic also prevents “loop through”, in
which a port’s digital output can drive the input of a
peripheral that shares the same pin. Figure 11-1 shows
how ports are shared with other peripherals and the
associated I/O pin to which they are connected.
When a pin is shared with another peripheral or func-
tion that is defined as an input only, it is nevertheless
regarded as a dedicated port because there is no
other competing source of outputs. An example is the
INT4 pin.
Note:
The voltage on a digital input pin can be
between -0.3V to 5.6V.
FIGURE 11-1:
BLOCK DIAGRAM OF A TYPICAL SHARED PORT STRUCTURE
Peripheral Module
Output Multiplexers
Peripheral Input Data
Peripheral Module Enable
Peripheral Output Enable
Peripheral Output Data
I/O
1
Output Enable
0
1
0
PIO Module
Output Data
Read TRIS
Data Bus
WR TRIS
D
Q
I/O Pin
CK
TRIS Latch
D
Q
WR LAT +
WR PORT
CK
Data Latch
Read LAT
Read Port
Input Data
© 2009 Microchip Technology Inc.
Preliminary
DS70592A-page 143
PIC24HJXXXGPX06A/X08A/X10A
11.2 Open-Drain Configuration
11.4 I/O Port Write/Read Timing
In addition to the PORT, LAT and TRIS registers for
data control, some port pins can also be individually
configured for either digital or open-drain output. This is
controlled by the Open-Drain Control register, ODCx,
associated with each port. Setting any of the bits con-
figures the corresponding pin to act as an open-drain
output.
One instruction cycle is required between a port
direction change or port write operation and a read
operation of the same port. Typically, this instruction
would be a NOP.
11.5 Input Change Notification
The input change notification function of the I/O ports
allows the PIC24HJXXXGPX06A/X08A/X10A devices
to generate interrupt requests to the processor in
response to a change-of-state on selected input pins.
This feature is capable of detecting input
change-of-states even in Sleep mode, when the clocks
are disabled. Depending on the device pin count, there
are up to 24 external signals (CN0 through CN23) that
can be selected (enabled) for generating an interrupt
request on a change-of-state.
The open-drain feature allows the generation of
outputs higher than VDD (e.g., 5V) on any desired digi-
tal only pins by using external pull-up resistors. The
maximum open-drain voltage allowed is the same as
the maximum VIH specification.
See the “Pin Diagrams (Continued)” for the available
pins and their functionality.
11.3 Configuring Analog Port Pins
There are four control registers associated with the CN
module. The CNEN1 and CNEN2 registers contain the
CN interrupt enable (CNxIE) control bits for each of the
CN input pins. Setting any of these bits enables a CN
interrupt for the corresponding pins.
The use of the ADxPCFGH, ADxPCFGL and TRIS
registers control the operation of the Analog-to-Digital
port pins. The port pins that are desired as analog
inputs must have their corresponding TRIS bit set
(input). If the TRIS bit is cleared (output), the digital out-
put level (VOH or VOL) is converted.
Each CN pin also has a weak pull-up connected to it.
The pull-ups act as a current source that is connected
to the pin and eliminate the need for external resistors
when push button or keypad devices are connected.
The pull-ups are enabled separately using the CNPU1
and CNPU2 registers, which contain the weak pull-up
enable (CNxPUE) bits for each of the CN pins. Setting
any of the control bits enables the weak pull-ups for the
corresponding pins.
Clearing any bit in the ADxPCFGH or ADxPCFGL reg-
ister configures the corresponding bit to be an analog
pin. This is also the Reset state of any I/O pin that has
an analog (ANx) function associated with it.
Note:
In devices with two ADC modules, if the
corresponding PCFG bit in either
AD1PCFGH(L) and AD2PCFGH(L) is
cleared, the pin is configured as an analog
input.
Note:
Pull-ups on change notification pins
should always be disabled whenever the
port pin is configured as a digital output.
When reading the PORT register, all pins configured as
analog input channels will read as cleared (a low level).
Pins configured as digital inputs will not convert an
analog input. Analog levels on any pin that is defined as
a digital input (including the ANx pins) can cause the
input buffer to consume current that exceeds the
device specifications.
Note:
The voltage on an analog input pin can be
between -0.3V to (VDD + 0.3 V).
EXAMPLE 11-1:
PORT WRITE/READ EXAMPLE
MOV
MOV
NOP
btss
0xFF00, W0
W0, TRISBB
; Configure PORTB<15:8> as inputs
; and PORTB<7:0> as outputs
; Delay 1 cycle
PORTB, #13
; Next Instruction
DS70592A-page 144
Preliminary
© 2009 Microchip Technology Inc.
PIC24HJXXXGPX06A/X08A/X10A
Figure 12-1 presents a block diagram of the 16-bit
timer module.
12.0 TIMER1
Note:
This data sheet summarizes the features
of the PIC24HJXXXGPX06A/X08A/X10A
To configure Timer1 for operation:
1. Set the TON bit (= 1) in the T1CON register.
family of devices. However, it is not
intended to be a comprehensive reference
source. To complement the information in
this data sheet, refer to the “PIC24H
Family Reference Manual”, Section 11.
“Timers” (DS70244), which is available
2. Select the timer prescaler ratio using the
TCKPS<1:0> bits in the T1CON register.
3. Set the Clock and Gating modes using the TCS
and TGATE bits in the T1CON register.
4. Set or clear the TSYNC bit in T1CON to select
synchronous or asynchronous operation.
from
the
Microchip
website
(www.microchip.com).
5. Load the timer period value into the PR1
register.
The Timer1 module is a 16-bit timer, which can serve
as the time counter for the real-time clock, or operate
as a free-running interval timer/counter. Timer1 can
operate in three modes:
6. If interrupts are required, set the interrupt enable
bit, T1IE. Use the priority bits, T1IP<2:0>, to set
the interrupt priority.
• 16-bit Timer
• 16-bit Synchronous Counter
• 16-bit Asynchronous Counter
Timer1 also supports these features:
• Timer gate operation
• Selectable prescaler settings
• Timer operation during CPU Idle and Sleep
modes
• Interrupt on 16-bit Period register match or falling
edge of external gate signal
FIGURE 12-1:
16-BIT TIMER1 MODULE BLOCK DIAGRAM
TCKPS<1:0>
TON
2
SOSCO/
1x
01
00
T1CK
Prescaler
1, 8, 64, 256
Gate
Sync
SOSCEN
SOSCI
TCY
TGATE
TCS
TGATE
1
0
Q
Q
D
Set T1IF
CK
0
Reset
Equal
TMR1
1
Sync
TSYNC
Comparator
PR1
© 2009 Microchip Technology Inc.
Preliminary
DS70592A-page 145
PIC24HJXXXGPX06A/X08A/X10A
REGISTER 12-1: T1CON: TIMER1 CONTROL REGISTER
R/W-0
TON
U-0
—
R/W-0
TSIDL
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
bit 15
bit 8
bit 0
U-0
—
R/W-0
R/W-0
R/W-0
U-0
—
R/W-0
R/W-0
TCS
U-0
—
TGATE
TCKPS<1:0>
TSYNC
bit 7
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15
TON: Timer1 On bit
1= Starts 16-bit Timer1
0= Stops 16-bit Timer1
bit 14
bit 13
Unimplemented: Read as ‘0’
TSIDL: Stop in Idle Mode bit
1= Discontinue module operation when device enters Idle mode
0= Continue module operation in Idle mode
bit 12-7
bit 6
Unimplemented: Read as ‘0’
TGATE: Timer1 Gated Time Accumulation Enable bit
When T1CS = 1:
This bit is ignored.
When T1CS = 0:
1= Gated time accumulation enabled
0= Gated time accumulation disabled
bit 5-4
TCKPS<1:0>: Timer1 Input Clock Prescale Select bits
11= 1:256
10= 1:64
01= 1:8
00= 1:1
bit 3
bit 2
Unimplemented: Read as ‘0’
TSYNC: Timer1 External Clock Input Synchronization Select bit
When TCS = 1:
1= Synchronize external clock input
0= Do not synchronize external clock input
When TCS = 0:
This bit is ignored.
bit 1
bit 0
TCS: Timer1 Clock Source Select bit
1= External clock from pin T1CK (on the rising edge)
0= Internal clock (FCY)
Unimplemented: Read as ‘0’
DS70592A-page 146
Preliminary
© 2009 Microchip Technology Inc.
PIC24HJXXXGPX06A/X08A/X10A
For 32-bit timer/counter operation, Timer2, Timer4,
13.0 TIMER2/3, TIMER4/5, TIMER6/7
Timer6 or Timer8 is the least significant word; Timer3,
Timer5, Timer7 or Timer9 is the most significant word
of the 32-bit timers.
AND TIMER8/9
Note:
This data sheet summarizes the features
of the PIC24HJXXXGPX06A/X08A/X10A
family of devices. However, it is not
intended to be a comprehensive reference
source. To complement the information in
this data sheet, refer to the “PIC24H
Family Reference Manual”, Section 11.
“Timers” (DS70244), which is available
Note:
For 32-bit operation, T3CON, T5CON,
T7CON and T9CON control bits are
ignored. Only T2CON, T4CON, T6CON
and T8CON control bits are used for setup
and control. Timer2, Timer4, Timer6 and
Timer8 clock and gate inputs are utilized
for the 32-bit timer modules, but an inter-
rupt is generated with the Timer3, Timer5,
Ttimer7 and Timer9 interrupt flags.
from
the
Microchip
website
(www.microchip.com).
The Timer2/3, Timer4/5, Timer6/7 and Timer8/9
modules are 32-bit timers, which can also be config-
ured as four independent 16-bit timers with selectable
operating modes.
To configure Timer2/3, Timer4/5, Timer6/7 or Timer8/9
for 32-bit operation:
1. Set the corresponding T32 control bit.
2. Select the prescaler ratio for Timer2, Timer4,
Timer6 or Timer8 using the TCKPS<1:0> bits.
As a 32-bit timer, Timer2/3, Timer4/5, Timer6/7 and
Timer8/9 operate in three modes:
3. Set the Clock and Gating modes using the
corresponding TCS and TGATE bits.
• Two Independent 16-bit Timers (e.g., Timer2 and
Timer3) with all 16-bit operating modes (except
Asynchronous Counter mode)
4. Load the timer period value. PR3, PR5, PR7 or
PR9 contains the most significant word of the
value, while PR2, PR4, PR6 or PR8 contains the
least significant word.
• Single 32-bit Timer
• Single 32-bit Synchronous Counter
5. If interrupts are required, set the interrupt enable
bit, T3IE, T5IE, T7IE or T9IE. Use the priority
bits, T3IP<2:0>, T5IP<2:0>, T7IP<2:0> or
T9IP<2:0>, to set the interrupt priority. While
Timer2, Timer4, Timer6 or Timer8 control the
timer, the interrupt appears as a Timer3, Timer5,
Timer7 or Timer9 interrupt.
They also support these features:
• Timer Gate Operation
• Selectable Prescaler Settings
• Timer Operation during Idle and Sleep modes
• Interrupt on a 32-bit Period Register Match
• Time Base for Input Capture and Output Compare
Modules (Timer2 and Timer3 only)
6. Set the corresponding TON bit.
• ADC1 Event Trigger (Timer2/3 only)
• ADC2 Event Trigger (Timer4/5 only)
The timer value at any point is stored in the register
pair, TMR3:TMR2, TMR5:TMR4, TMR7:TMR6 or
TMR9:TMR8. TMR3, TMR5, TMR7 or TMR9 always
contains the most significant word of the count, while
TMR2, TMR4, TMR6 or TMR8 contains the least
significant word.
Individually, all eight of the 16-bit timers can function as
synchronous timers or counters. They also offer the
features listed above, except for the event trigger; this
is implemented only with Timer2/3. The operating
modes and enabled features are determined by setting
the appropriate bit(s) in the T2CON, T3CON, T4CON,
T5CON, T6CON, T7CON, T8CON and T9CON regis-
ters. T2CON, T4CON, T6CON and T8CON are shown
in generic form in Register 13-1. T3CON, T5CON,
T7CON and T9CON are shown in Register 13-2.
To configure any of the timers for individual 16-bit
operation:
1. Clear the T32 bit corresponding to that timer.
2. Select the timer prescaler ratio using the
TCKPS<1:0> bits.
3. Set the Clock and Gating modes using the TCS
and TGATE bits.
4. Load the timer period value into the PRx
register.
5. If interrupts are required, set the interrupt enable
bit, TxIE. Use the priority bits, TxIP<2:0>, to set
the interrupt priority.
6. Set the TON bit.
© 2009 Microchip Technology Inc.
Preliminary
DS70592A-page 147
PIC24HJXXXGPX06A/X08A/X10A
A block diagram for a 32-bit timer pair (Timer4/5)
example is shown in Figure 13-1 and a timer (Timer4)
operating in 16-bit mode example is shown in
Figure 13-2.
Note:
Only Timer2 and Timer3 can trigger a
DMA data transfer.
(1)
FIGURE 13-1:
TIMER2/3 (32-BIT) BLOCK DIAGRAM
TCKPS<1:0>
2
TON
1x
01
00
T2CK
Gate
Sync
Prescaler
1, 8, 64, 256
TCY
TGATE
TCS
TGATE
1
0
Q
Q
D
Set T3IF
CK
PR2
PR3
ADC Event Trigger(2)
Equal
Reset
Comparator
MSb
LSb
TMR3
TMR2
Sync
16
Read TMR2
Write TMR2
16
16
TMR3HLD
16
Data Bus<15:0>
Note 1: The 32-bit timer control bit, T32, must be set for 32-bit timer/counter operation. All control bits are respective
to the T2CON register.
2: The ADC event trigger is available only on Timer2/3.
DS70592A-page 148
Preliminary
© 2009 Microchip Technology Inc.
PIC24HJXXXGPX06A/X08A/X10A
FIGURE 13-2:
TIMER2 (16-BIT) BLOCK DIAGRAM
TCKPS<1:0>
TON
2
T2CK
1x
01
00
Prescaler
1, 8, 64, 256
Gate
Sync
TGATE
TCS
TGATE
TCY
1
0
Q
D
Set T2IF
Q
CK
Reset
Equal
Sync
TMR2
Comparator
PR2
© 2009 Microchip Technology Inc.
Preliminary
DS70592A-page 149
PIC24HJXXXGPX06A/X08A/X10A
REGISTER 13-1: TxCON (T2CON, T4CON, T6CON OR T8CON) CONTROL REGISTER
R/W-0
TON
U-0
—
R/W-0
TSIDL
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
bit 15
bit 8
bit 0
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
T32
U-0
—
R/W-0
TCS(1)
U-0
—
TGATE
TCKPS<1:0>
bit 7
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15
TON: Timerx On bit
When T32 = 1:
1= Starts 32-bit Timerx/y
0= Stops 32-bit Timerx/y
When T32 = 0:
1= Starts 16-bit Timerx
0= Stops 16-bit Timerx
bit 14
bit 13
Unimplemented: Read as ‘0’
TSIDL: Stop in Idle Mode bit
1= Discontinue module operation when device enters Idle mode
0= Continue module operation in Idle mode
bit 12-7
bit 6
Unimplemented: Read as ‘0’
TGATE: Timerx Gated Time Accumulation Enable bit
When TCS = 1:
This bit is ignored.
When TCS = 0:
1= Gated time accumulation enabled
0= Gated time accumulation disabled
bit 5-4
bit 3
TCKPS<1:0>: Timerx Input Clock Prescale Select bits
11= 1:256
10= 1:64
01= 1:8
00= 1:1
T32: 32-bit Timer Mode Select bit
1= Timerx and Timery form a single 32-bit timer
0= Timerx and Timery act as two 16-bit timers
bit 2
bit 1
Unimplemented: Read as ‘0’
TCS: Timerx Clock Source Select bit(1)
1= External clock from pin TxCK (on the rising edge)
0= Internal clock (FCY)
bit 0
Unimplemented: Read as ‘0’
Note 1: The TxCK pin is not available on all timers. Refer to the “Pin Diagrams” section for the available pins.
DS70592A-page 150
Preliminary
© 2009 Microchip Technology Inc.
PIC24HJXXXGPX06A/X08A/X10A
REGISTER 13-2: TyCON (T3CON, T5CON, T7CON OR T9CON) CONTROL REGISTER
R/W-0
TON(1)
U-0
—
R/W-0
TSIDL(2)
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
bit 15
bit 8
bit 0
U-0
—
R/W-0
TGATE(1)
R/W-0
TCKPS<1:0>(1)
R/W-0
U-0
—
U-0
—
R/W-0
TCS(1,3)
U-0
—
bit 7
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
-n = Value at POR
bit 15
TON: Timery On bit(1)
1= Starts 16-bit Timery
0= Stops 16-bit Timery
bit 14
bit 13
Unimplemented: Read as ‘0’
TSIDL: Stop in Idle Mode bit(2)
1= Discontinue module operation when device enters Idle mode
0= Continue module operation in Idle mode
bit 12-7
bit 6
Unimplemented: Read as ‘0’
TGATE: Timery Gated Time Accumulation Enable bit(1)
When TCS = 1:
This bit is ignored.
When TCS = 0:
1= Gated time accumulation enabled
0= Gated time accumulation disabled
bit 5-4
TCKPS<1:0>: Timer3 Input Clock Prescale Select bits(1)
11= 1:256
10= 1:64
01= 1:8
00= 1:1
bit 3-2
bit 1
Unimplemented: Read as ‘0’
TCS: Timery Clock Source Select bit(1,3)
1= External clock from pin TyCK (on the rising edge)
0= Internal clock (FCY)
bit 0
Unimplemented: Read as ‘0’
Note 1: When 32-bit operation is enabled (T2CON<3> = 1), these bits have no effect on Timery operation; all timer
functions are set through T2CON.
2: When 32-bit timer operation is enabled (T32 = 1) in the Timer Control register (TxCON<3>), the TSIDL bit
must be cleared to operate the 32-bit timer in Idle mode.
3: The TyCK pin is not available on all timers. Refer to the “Pin Diagrams” section for the available pins.
© 2009 Microchip Technology Inc.
Preliminary
DS70592A-page 151
PIC24HJXXXGPX06A/X08A/X10A
NOTES:
DS70592A-page 152
Preliminary
© 2009 Microchip Technology Inc.
PIC24HJXXXGPX06A/X08A/X10A
2. Capture timer value on every edge (rising and
14.0 INPUT CAPTURE
falling)
Note:
This data sheet summarizes the features
of the PIC24HJXXXGPX06A/X08A/X10A
family of devices. However, it is not
intended to be a comprehensive reference
source. To complement the information in
this data sheet, refer to the “PIC24H
Family Reference Manual”, Section 12.
“Input Capture” (DS70248), which is
available from the Microchip website
(www.microchip.com).
3. Prescaler Capture Event modes
-Capture timer value on every 4th rising edge
of input at ICx pin
-Capture timer value on every 16th rising
edge of input at ICx pin
Each input capture channel can select between one of
two 16-bit timers (Timer2 or Timer3) for the time base.
The selected timer can use either an internal or exter-
nal clock.
Other operational features include:
The input capture module is useful in applications
requiring frequency (period) and pulse measurement.
• Device wake-up from capture pin during CPU
Sleep and Idle modes
The
PIC24HJXXXGPX06A/X08A/X10A
devices
support up to eight input capture channels.
• Interrupt on input capture event
The input capture module captures the 16-bit value of
the selected Time Base register when an event occurs
at the ICx pin. The events that cause a capture event
are listed below in three categories:
• 4-word FIFO buffer for capture values
- Interrupt optionally generated after 1, 2, 3 or
4 buffer locations are filled
• Input capture can also be used to provide
additional sources of external interrupts
1. Simple Capture Event modes
-Capture timer value on every falling edge of
input at ICx pin
Note:
Only IC1 and IC2 can trigger a DMA data
transfer. If DMA data transfers are
required, the FIFO buffer size must be set
to 1 (ICI<1:0> = 00).
-Capture timer value on every rising edge of
input at ICx pin
FIGURE 14-1:
INPUT CAPTURE BLOCK DIAGRAM
From 16-bit Timers
TMRy TMRz
16
16
ICTMR
(ICxCON<7>)
1
0
Edge Detection Logic
and
Clock Synchronizer
FIFO
R/W
Logic
Prescaler
Counter
(1, 4, 16)
ICx Pin
ICM<2:0> (ICxCON<2:0>)
3
Mode Select
ICOV, ICBNE (ICxCON<4:3>)
ICxBUF
ICxI<1:0>
Interrupt
Logic
ICxCON
System Bus
Set Flag ICxIF
(in IFSn Register)
Note: An ‘x’ in a signal, register or bit name denotes the number of the capture channel.
© 2009 Microchip Technology Inc.
Preliminary
DS70592A-page 153
PIC24HJXXXGPX06A/X08A/X10A
14.1 Input Capture Registers
REGISTER 14-1: ICxCON: INPUT CAPTURE x CONTROL REGISTER
U-0
—
U-0
—
R/W-0
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
ICSIDL
bit 15
bit 8
R/W-0
bit 0
R/W-0
ICTMR(1)
R/W-0
R/W-0
R-0, HC
ICOV
R-0, HC
ICBNE
R/W-0
R/W-0
ICI<1:0>
ICM<2:0>
bit 7
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-14
bit 13
Unimplemented: Read as ‘0’
ICSIDL: Input Capture Module Stop in Idle Control bit
1= Input capture module will halt in CPU Idle mode
0= Input capture module will continue to operate in CPU Idle mode
bit 12-8
bit 7
Unimplemented: Read as ‘0’
ICTMR: Input Capture Timer Select bits(1)
1= TMR2 contents are captured on capture event
0= TMR3 contents are captured on capture event
bit 6-5
ICI<1:0>: Select Number of Captures per Interrupt bits
11= Interrupt on every fourth capture event
10= Interrupt on every third capture event
01= Interrupt on every second capture event
00= Interrupt on every capture event
bit 4
ICOV: Input Capture Overflow Status Flag bit (read-only)
1= Input capture overflow occurred
0= No input capture overflow occurred
bit 3
ICBNE: Input Capture Buffer Empty Status bit (read-only)
1= Input capture buffer is not empty, at least one more capture value can be read
0= Input capture buffer is empty
bit 2-0
ICM<2:0>: Input Capture Mode Select bits
111= Input capture functions as interrupt pin only when device is in Sleep or Idle mode
(Rising edge detect only, all other control bits are not applicable.)
110= Unused (module disabled)
101= Capture mode, every 16th rising edge
100= Capture mode, every 4th rising edge
011= Capture mode, every rising edge
010= Capture mode, every falling edge
001= Capture mode, every edge (rising and falling)
(ICI<1:0> bits do not control interrupt generation for this mode.)
000= Input capture module turned off
Note 1: Timer selections may vary. Refer to the device data sheet for details.
DS70592A-page 154
Preliminary
© 2009 Microchip Technology Inc.
PIC24HJXXXGPX06A/X08A/X10A
The state of the output pin changes when the timer
15.0 OUTPUT COMPARE
value matches the Compare register value. The output
compare module generates either a single output
pulse, or a sequence of output pulses, by changing the
state of the output pin on the compare match events.
The output compare module can also generate
interrupts on compare match events.
Note:
This data sheet summarizes the features
of the PIC24HJXXXGPX06A/X08A/X10A
families of devices. It is not intended to be
a comprehensive reference source. To
complement the information in this data
sheet, refer to the “PIC24H Family
Reference Manual”, Section 13. “Output
Compare” (DS70247), which is available
The output compare module has multiple operating
modes:
• Active-Low One-Shot mode
• Active-High One-Shot mode
• Toggle mode
on
the
Microchip
web
site
(www.microchip.com).
• Delayed One-Shot mode
• Continuous Pulse mode
• PWM mode without Fault Protection
• PWM mode with Fault Protection
The output compare module can select either Timer2 or
Timer3 for its time base. The module compares the
value of the timer with the value of one or two Compare
registers depending on the operating mode selected.
FIGURE 15-1:
OUTPUT COMPARE MODULE BLOCK DIAGRAM
Set Flag bit
OCxIF(1)
OCxRS(1)
OCxR(1)
Output
Logic
S
R
Q
OCx(1)
Output Enable
3
OCM<2:0>
Mode Select
OCFA
or
Comparator
OCFB(2)
0
0
OCTSEL
1
1
16
16
TMR2
Rollover
TMR3
Rollover
TMR3
TMR2
Note 1: An ‘x’ in a signal, register or bit name denotes the number of the output compare channels.
2: The OCFA pin controls OC1 through OC4. The OCFB pin controls OC5 through OC8.
© 2009 Microchip Technology Inc.
Preliminary
DS70592A-page 155
PIC24HJXXXGPX06A/X08A/X10A
application must disable the associated timer when
writing to the Output Compare Control registers to
avoid malfunctions.
15.1 Output Compare Modes
Configure the Output Compare modes by setting the
appropriate Output Compare Mode (OCM<2:0>) bits in
the Output Compare Control (OCxCON<2:0>) register.
Table 15-1 lists the different bit settings for the Output
Compare modes. Figure 15-2 illustrates the output
compare operation for various modes. The user
Note:
See Section 13. “Output Compare”
(DS70247) in the “PIC24H Family Refer-
ence Manual” for OCxR and OCxRS
register restrictions.
TABLE 15-1: OUTPUT COMPARE MODES
OCM<2:0>
Mode
Module Disabled
OCx Pin Initial State
OCx Interrupt Generation
000
001
010
011
100
101
110
Controlled by GPIO register
—
Active-Low One-Shot
Active-High One-Shot
Toggle
0
1
OCx rising edge
OCx falling edge
Current output is maintained OCx rising and falling edge
Delayed One-Shot
Continuous Pulse
PWM without Fault Protection
0
0
OCx falling edge
OCx falling edge
No interrupt
‘0’, if OCxR is zero
‘1’, if OCxR is non-zero
111
PWM with Fault Protection
‘0’, if OCxR is zero
OCFA falling edge for OC1 to OC4
‘1’, if OCxR is non-zero
FIGURE 15-2:
OUTPUT COMPARE OPERATION
Output Compare
Mode Enabled
Timer is Reset on
Period Match
OCxRS
OCxR
TMRy
Active-Low One-Shot
(OCM = 001)
Active-High One-Shot
(OCM = 010)
Toggle
(OCM = 011)
Delayed One-Shot
(OCM = 100)
Continuous Pulse
(OCM = 101)
PWM
(OCM = 110or 111)
DS70592A-page 156
Preliminary
© 2009 Microchip Technology Inc.
PIC24HJXXXGPX06A/X08A/X10A
REGISTER 15-1: OCxCON: OUTPUT COMPARE x CONTROL REGISTER (x = 1, 2)
U-0
—
U-0
—
R/W-0
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
OCSIDL
bit 15
bit 8
R/W-0
bit 0
U-0
—
U-0
—
U-0
—
R-0, HC
OCFLT
R/W-0
R/W-0
R/W-0
OCTSEL
OCM<2:0>
bit 7
Legend:
HC = Hardware Clearable bit
W = Writable bit
R = Readable bit
-n = Value at POR
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
‘1’ = Bit is set
bit 15-14
bit 13
Unimplemented: Read as ‘0’
OCSIDL: Stop Output Compare in Idle Mode Control bit
1= Output Compare x halts in CPU Idle mode
0= Output Compare x continues to operate in CPU Idle mode
bit 12-5
bit 4
Unimplemented: Read as ‘0’
OCFLT: PWM Fault Condition Status bit
1= PWM Fault condition has occurred (cleared in hardware only)
0= No PWM Fault condition has occurred (this bit is only used when OCM<2:0> = 111)
bit 3
OCTSEL: Output Compare Timer Select bit
1= Timer3 is the clock source for Compare x
0= Timer2 is the clock source for Compare x
bit 2-0
OCM<2:0>: Output Compare Mode Select bits
111= PWM mode on OCx, Fault pin enabled
110= PWM mode on OCx, Fault pin disabled
101= Initialize OCx pin low, generate continuous output pulses on OCx pin
100= Initialize OCx pin low, generate single output pulse on OCx pin
011= Compare event toggles OCx pin
010= Initialize OCx pin high, compare event forces OCx pin low
001= Initialize OCx pin low, compare event forces OCx pin high
000= Output compare channel is disabled
© 2009 Microchip Technology Inc.
Preliminary
DS70592A-page 157
PIC24HJXXXGPX06A/X08A/X10A
NOTES:
DS70592A-page 158
Preliminary
© 2009 Microchip Technology Inc.
PIC24HJXXXGPX06A/X08A/X10A
Each SPI module consists of a 16-bit shift register,
16.0 SERIAL PERIPHERAL
SPIxSR (where x = 1 or 2), used for shifting data in and
out, and a buffer register, SPIxBUF. A control register,
SPIxCON, configures the module. Additionally, a status
register, SPIxSTAT, indicates various status conditions.
INTERFACE (SPI)
Note:
This data sheet summarizes the features
of the PIC24HJXXXGPX06A/X08A/X10A
family of devices. However, it is not
intended to be a comprehensive reference
source. To complement the information in
this data sheet, refer to the “PIC24H
Family Reference Manual“, Section 18.
“Serial Peripheral Interface (SPI)”
(DS70243), which is available from the
Microchip website (www.microchip.com).
The serial interface consists of 4 pins: SDIx (serial data
input), SDOx (serial data output), SCKx (shift clock
input or output), and SSx (active-low slave select).
In Master mode operation, SCK is a clock output but in
Slave mode, it is a clock input.
The Serial Peripheral Interface (SPI) module is a syn-
chronous serial interface useful for communicating with
other peripheral or microcontroller devices. These
peripheral devices may be serial EEPROMs, shift regis-
ters, display drivers, Analog-to-Digital converters, etc.
The SPI module is compatible with SPI and SIOP from
Motorola®.
Note: In this section, the SPI modules are
referred to together as SPIx, or separately
as SPI1 and SPI2. Special Function Reg-
isters will follow a similar notation. For
example, SPIxCON refers to the control
register for the SPI1 or SPI2 module.
FIGURE 16-1:
SPI MODULE BLOCK DIAGRAM
SCKx
1:1 to 1:8
Secondary
Prescaler
1:1/4/16/64
Primary
Prescaler
FCY
SSx
Sync
Control
Select
Edge
Control
Clock
SPIxCON1<1:0>
SPIxCON1<4:2>
Shift Control
SDOx
SDIx
Enable
Master Clock
bit 0
SPIxSR
Transfer
Transfer
SPIxRXB SPIxTXB
SPIxBUF
Write SPIxBUF
Read SPIxBUF
16
Internal Data Bus
© 2009 Microchip Technology Inc.
Preliminary
DS70592A-page 159
PIC24HJXXXGPX06A/X08A/X10A
REGISTER 16-1: SPIxSTAT: SPIx STATUS AND CONTROL REGISTER
R/W-0
SPIEN
U-0
—
R/W-0
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
SPISIDL
bit 15
bit 8
U-0
—
R/C-0
U-0
—
U-0
—
U-0
—
U-0
—
R-0
R-0
SPIROV
SPITBF
SPIRBF
bit 0
bit 7
Legend:
C = Clearable bit
W = Writable bit
‘1’ = Bit is set
R = Readable bit
-n = Value at POR
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15
SPIEN: SPIx Enable bit
1= Enables module and configures SCKx, SDOx, SDIx and SSx as serial port pins
0= Disables module
bit 14
bit 13
Unimplemented: Read as ‘0’
SPISIDL: Stop in Idle Mode bit
1= Discontinue module operation when device enters Idle mode
0= Continue module operation in Idle mode
bit 12-7
bit 6
Unimplemented: Read as ‘0’
SPIROV: Receive Overflow Flag bit
1= A new byte/word is completely received and discarded. The user software has not read the
previous data in the SPIxBUF register
0= No overflow has occurred
bit 5-2
bit 1
Unimplemented: Read as ‘0’
SPITBF: SPIx Transmit Buffer Full Status bit
1= Transmit not yet started, SPIxTXB is full
0= Transmit started, SPIxTXB is empty
Automatically set in hardware when CPU writes SPIxBUF location, loading SPIxTXB.
Automatically cleared in hardware when SPIx module transfers data from SPIxTXB to SPIxSR.
bit 0
SPIRBF: SPIx Receive Buffer Full Status bit
1= Receive complete, SPIxRXB is full
0= Receive is not complete, SPIxRXB is empty
Automatically set in hardware when SPIx transfers data from SPIxSR to SPIxRXB.
Automatically cleared in hardware when core reads SPIxBUF location, reading SPIxRXB.
DS70592A-page 160
Preliminary
© 2009 Microchip Technology Inc.
PIC24HJXXXGPX06A/X08A/X10A
REGISTER 16-2: SPIXCON1: SPIx CONTROL REGISTER 1
U-0
—
U-0
—
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
SMP
R/W-0
CKE(1)
DISSCK
DISSDO
MODE16
bit 15
bit 8
R/W-0
SSEN(3)
R/W-0
CKP
R/W-0
R/W-0
R/W-0
SPRE<2:0>(2)
R/W-0
R/W-0
R/W-0
MSTEN
PPRE<1:0>(2)
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-13
bit 12
Unimplemented: Read as ‘0’
DISSCK: Disable SCKx pin bit (SPI Master modes only)
1= Internal SPI clock is disabled, pin functions as I/O
0= Internal SPI clock is enabled
bit 11
bit 10
bit 9
DISSDO: Disable SDOx pin bit
1= SDOx pin is not used by module; pin functions as I/O
0= SDOx pin is controlled by the module
MODE16: Word/Byte Communication Select bit
1= Communication is word-wide (16 bits)
0= Communication is byte-wide (8 bits)
SMP: SPIx Data Input Sample Phase bit
Master mode:
1= Input data sampled at end of data output time
0= Input data sampled at middle of data output time
Slave mode:
SMP must be cleared when SPIx is used in Slave mode.
bit 8
bit 7
bit 6
bit 5
CKE: SPIx Clock Edge Select bit(1)
1= Serial output data changes on transition from active clock state to Idle clock state (see bit 6)
0= Serial output data changes on transition from Idle clock state to active clock state (see bit 6)
SSEN: Slave Select Enable bit (Slave mode)(3)
1= SSx pin used for Slave mode
0= SSx pin not used by module. Pin controlled by port function
CKP: Clock Polarity Select bit
1= Idle state for clock is a high level; active state is a low level
0= Idle state for clock is a low level; active state is a high level
MSTEN: Master Mode Enable bit
1= Master mode
0= Slave mode
Note 1: The CKE bit is not used in the Framed SPI modes. The user should program this bit to ‘0’ for the Framed
SPI modes (FRMEN = 1).
2: Do not set both Primary and Secondary prescalers to a value of 1:1.
3: This bit must be cleared when FRMEN = 1.
© 2009 Microchip Technology Inc.
Preliminary
DS70592A-page 161
PIC24HJXXXGPX06A/X08A/X10A
REGISTER 16-2: SPIXCON1: SPIx CONTROL REGISTER 1 (CONTINUED)
bit 4-2
SPRE<2:0>: Secondary Prescale bits (Master mode)(2)
111= Secondary prescale 1:1
110= Secondary prescale 2:1
•
•
•
000= Secondary prescale 8:1
bit 1-0
PPRE<1:0>: Primary Prescale bits (Master mode)(2)
11= Primary prescale 1:1
10= Primary prescale 4:1
01= Primary prescale 16:1
00= Primary prescale 64:1
Note 1: The CKE bit is not used in the Framed SPI modes. The user should program this bit to ‘0’ for the Framed
SPI modes (FRMEN = 1).
2: Do not set both Primary and Secondary prescalers to a value of 1:1.
3: This bit must be cleared when FRMEN = 1.
DS70592A-page 162
Preliminary
© 2009 Microchip Technology Inc.
PIC24HJXXXGPX06A/X08A/X10A
REGISTER 16-3: SPIxCON2: SPIx CONTROL REGISTER 2
R/W-0
R/W-0
R/W-0
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
FRMEN
SPIFSD
FRMPOL
bit 15
bit 8
bit 0
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
R/W-0
U-0
—
FRMDLY
bit 7
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15
bit 14
bit 13
FRMEN: Framed SPIx Support bit
1= Framed SPIx support enabled (SSx pin used as frame sync pulse input/output)
0= Framed SPIx support disabled
SPIFSD: Frame Sync Pulse Direction Control bit
1= Frame sync pulse input (slave)
0= Frame sync pulse output (master)
FRMPOL: Frame Sync Pulse Polarity bit
1= Frame sync pulse is active-high
0= Frame sync pulse is active-low
bit 12-2
bit 1
Unimplemented: Read as ‘0’
FRMDLY: Frame Sync Pulse Edge Select bit
1= Frame sync pulse coincides with first bit clock
0= Frame sync pulse precedes first bit clock
bit 0
Unimplemented: Read as ‘0’
This bit must not be set to ‘1’ by the user application
© 2009 Microchip Technology Inc.
Preliminary
DS70592A-page 163
PIC24HJXXXGPX06A/X08A/X10A
NOTES:
DS70592A-page 164
Preliminary
© 2009 Microchip Technology Inc.
PIC24HJXXXGPX06A/X08A/X10A
17.2 I2C Registers
17.0 INTER-INTEGRATED
2
CIRCUIT™ (I C™)
I2CxCON and I2CxSTAT are control and status
registers, respectively. The I2CxCON register is
readable and writable. The lower six bits of I2CxSTAT
are read-only. The remaining bits of the I2CSTAT are
read/write.
Note:
This data sheet summarizes the features
of the PIC24HJXXXGPX06A/X08A/X10A
family of devices. However, it is not
intended to be a comprehensive reference
source. To complement the information in
this data sheet, refer to the “PIC24H
Family Reference Manual”, Section 19.
“Inter-Integrated Circuit™ (I2C™)”
(DS70235), which is available from the
Microchip website (www.microchip.com).
I2CxRSR is the shift register used for shifting data,
whereas I2CxRCV is the buffer register to which data
bytes are written, or from which data bytes are read.
I2CxRCV is the receive buffer. I2CxTRN is the transmit
register to which bytes are written during a transmit
operation.
The I2CxADD register holds the slave address. A
status bit, ADD10, indicates 10-bit Address mode. The
I2CxBRG acts as the Baud Rate Generator (BRG)
reload value.
The Inter-Integrated Circuit (I2C) module provides
complete hardware support for both Slave and Multi-
Master modes of the I2C serial communication
standard, with a 16-bit interface.
In receive operations, I2CxRSR and I2CxRCV together
form a double-buffered receiver. When I2CxRSR
receives a complete byte, it is transferred to I2CxRCV
and an interrupt pulse is generated.
The PIC24HJXXXGPX06A/X08A/X10A devices have
up to two I2C interface modules, denoted as I2C1 and
I2C2. Each I2C module has a 2-pin interface: the SCLx
pin is clock and the SDAx pin is data.
Each I2C module ‘x’ (x = 1 or 2) offers the following key
features:
• I2C interface supporting both master and slave
operation.
• I2C Slave mode supports 7 and 10-bit address.
• I2C Master mode supports 7 and 10-bit address.
• I2C Port allows bidirectional transfers between
master and slaves.
• Serial clock synchronization for I2C port can be
used as a handshake mechanism to suspend and
resume serial transfer (SCLREL control).
• I2C supports multi-master operation; detects bus
collision and will arbitrate accordingly.
17.1 Operating Modes
The hardware fully implements all the master and slave
functions of the I2C Standard and Fast mode
specifications, as well as 7 and 10-bit addressing.
The I2C module can operate either as a slave or a
master on an I2C bus.
The following types of I2C operation are supported:
• I2C slave operation with 7-bit address
• I2C slave operation with 10-bit address
• I2C master operation with 7 or 10-bit address
For details about the communication sequence in each
of these modes, please refer to the “PIC24H Family
Reference Manual”.
© 2009 Microchip Technology Inc.
Preliminary
DS70592A-page 165
PIC24HJXXXGPX06A/X08A/X10A
2
FIGURE 17-1:
I C™ BLOCK DIAGRAM (X = 1 OR 2)
Internal
Data Bus
I2CxRCV
Read
Shift
Clock
SCLx
SDAx
I2CxRSR
LSB
Address Match
Match Detect
Write
Read
I2CxMSK
Write
Read
I2CxADD
Start and Stop
Bit Detect
Write
Start and Stop
Bit Generation
I2CxSTAT
I2CxCON
Read
Write
Collision
Detect
Acknowledge
Generation
Read
Clock
Stretching
Write
Read
I2CxTRN
LSB
Shift Clock
Reload
Control
Write
Read
BRG Down Counter
TCY/2
I2CxBRG
DS70592A-page 166
Preliminary
© 2009 Microchip Technology Inc.
PIC24HJXXXGPX06A/X08A/X10A
REGISTER 17-1: I2CxCON: I2Cx CONTROL REGISTER
R/W-0
I2CEN
U-0
—
R/W-0
R/W-1 HC
SCLREL
R/W-0
R/W-0
A10M
R/W-0
R/W-0
SMEN
I2CSIDL
IPMIEN
DISSLW
bit 15
bit 8
R/W-0
GCEN
R/W-0
R/W-0
R/W-0 HC
ACKEN
R/W-0 HC
RCEN
R/W-0 HC
PEN
R/W-0 HC
RSEN
R/W-0 HC
SEN
STREN
ACKDT
bit 7
bit 0
Legend:
U = Unimplemented bit, read as ‘0’
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
HS = Set in hardware
‘0’ = Bit is cleared
HC = Cleared in hardware
x = Bit is unknown
bit 15
I2CEN: I2Cx Enable bit
1= Enables the I2Cx module and configures the SDAx and SCLx pins as serial port pins
0= Disables the I2Cx module. All I2C pins are controlled by port functions.
bit 14
bit 13
Unimplemented: Read as ‘0’
I2CSIDL: Stop in Idle Mode bit
1= Discontinue module operation when device enters an Idle mode
0= Continue module operation in Idle mode
bit 12
SCLREL: SCLx Release Control bit (when operating as I2C slave)
1= Release SCLx clock
0= Hold SCLx clock low (clock stretch)
If STREN = 1:
Bit is R/W (i.e., software may write ‘0’ to initiate stretch and write ‘1’ to release clock). Hardware clear
at beginning of slave transmission. Hardware clear at end of slave reception.
If STREN = 0:
Bit is R/S (i.e., software may only write ‘1’ to release clock). Hardware clear at beginning of slave
transmission.
bit 11
bit 10
bit 9
IPMIEN: Intelligent Peripheral Management Interface (IPMI) Enable bit
1= IPMI mode is enabled; all addresses Acknowledged
0= IPMI mode disabled
A10M: 10-bit Slave Address bit
1= I2CxADD is a 10-bit slave address
0= I2CxADD is a 7-bit slave address
DISSLW: Disable Slew Rate Control bit
1= Slew rate control disabled
0= Slew rate control enabled
bit 8
SMEN: SMBus Input Levels bit
1= Enable I/O pin thresholds compliant with SMBus specification
0= Disable SMBus input thresholds
bit 7
GCEN: General Call Enable bit (when operating as I2C slave)
1= Enable interrupt when a general call address is received in the I2CxRSR
(module is enabled for reception)
0= General call address disabled
bit 6
STREN: SCLx Clock Stretch Enable bit (when operating as I2C slave)
Used in conjunction with SCLREL bit.
1= Enable software or receive clock stretching
0= Disable software or receive clock stretching
© 2009 Microchip Technology Inc.
Preliminary
DS70592A-page 167
PIC24HJXXXGPX06A/X08A/X10A
REGISTER 17-1: I2CxCON: I2Cx CONTROL REGISTER (CONTINUED)
bit 5
ACKDT: Acknowledge Data bit (when operating as I2C master, applicable during master receive)
Value that will be transmitted when the software initiates an Acknowledge sequence.
1= Send NACK during Acknowledge
0= Send ACK during Acknowledge
bit 4
ACKEN: Acknowledge Sequence Enable bit
(when operating as I2C master, applicable during master receive)
1= Initiate Acknowledge sequence on SDAx and SCLx pins and transmit ACKDT data bit.
Hardware clear at end of master Acknowledge sequence.
0= Acknowledge sequence not in progress
bit 3
bit 2
bit 1
RCEN: Receive Enable bit (when operating as I2C master)
1= Enables Receive mode for I2C. Hardware clear at end of eighth bit of master receive data byte.
0= Receive sequence not in progress
PEN: Stop Condition Enable bit (when operating as I2C master)
1= Initiate Stop condition on SDAx and SCLx pins. Hardware clear at end of master Stop sequence.
0= Stop condition not in progress
RSEN: Repeated Start Condition Enable bit (when operating as I2C master)
1= Initiate Repeated Start condition on SDAx and SCLx pins. Hardware clear at end of
master Repeated Start sequence.
0= Repeated Start condition not in progress
bit 0
SEN: Start Condition Enable bit (when operating as I2C master)
1= Initiate Start condition on SDAx and SCLx pins. Hardware clear at end of master Start sequence.
0= Start condition not in progress
DS70592A-page 168
Preliminary
© 2009 Microchip Technology Inc.
PIC24HJXXXGPX06A/X08A/X10A
REGISTER 17-2: I2CxSTAT: I2Cx STATUS REGISTER
R-0 HSC
R-0 HSC
TRSTAT
U-0
—
U-0
—
U-0
—
R/C-0 HS
BCL
R-0 HSC
GCSTAT
R-0 HSC
ADD10
ACKSTAT
bit 15
bit 8
R/C-0 HS
IWCOL
R/C-0 HS
I2COV
R-0 HSC
D_A
R/C-0 HSC R/C-0 HSC
R-0 HSC
R_W
R-0 HSC
RBF
R-0 HSC
TBF
P
S
bit 7
bit 0
Legend:
U = Unimplemented bit, read as ‘0’
C = Clear only bit
R = Readable bit
W = Writable bit
‘1’ = Bit is set
HS = Set in hardware
‘0’ = Bit is cleared
HSC = Hardware set/cleared
x = Bit is unknown
-n = Value at POR
bit 15
bit 14
ACKSTAT: Acknowledge Status bit
(when operating as I2C master, applicable to master transmit operation)
1= NACK received from slave
0= ACK received from slave
Hardware set or clear at end of slave Acknowledge.
TRSTAT: Transmit Status bit (when operating as I2C master, applicable to master transmit operation)
1= Master transmit is in progress (8 bits + ACK)
0= Master transmit is not in progress
Hardware set at beginning of master transmission. Hardware clear at end of slave Acknowledge.
bit 13-11
bit 10
Unimplemented: Read as ‘0’
BCL: Master Bus Collision Detect bit
1= A bus collision has been detected during a master operation
0= No collision
Hardware set at detection of bus collision.
bit 9
bit 8
bit 7
bit 6
bit 5
bit 4
GCSTAT: General Call Status bit
1= General call address was received
0= General call address was not received
Hardware set when address matches general call address. Hardware clear at Stop detection.
ADD10: 10-Bit Address Status bit
1= 10-bit address was matched
0= 10-bit address was not matched
Hardware set at match of 2nd byte of matched 10-bit address. Hardware clear at Stop detection.
IWCOL: Write Collision Detect bit
1= An attempt to write the I2CxTRN register failed because the I2C module is busy
0= No collision
Hardware set at occurrence of write to I2CxTRN while busy (cleared by software).
I2COV: Receive Overflow Flag bit
1= A byte was received while the I2CxRCV register is still holding the previous byte
0= No overflow
Hardware set at attempt to transfer I2CxRSR to I2CxRCV (cleared by software).
D_A: Data/Address bit (when operating as I2C slave)
1= Indicates that the last byte received was data
0= Indicates that the last byte received was device address
Hardware clear at device address match. Hardware set by reception of slave byte.
P: Stop bit
1= Indicates that a Stop bit has been detected last
0= Stop bit was not detected last
Hardware set or clear when Start, Repeated Start or Stop detected.
© 2009 Microchip Technology Inc.
Preliminary
DS70592A-page 169
PIC24HJXXXGPX06A/X08A/X10A
REGISTER 17-2: I2CxSTAT: I2Cx STATUS REGISTER (CONTINUED)
bit 3
bit 2
bit 1
S: Start bit
1= Indicates that a Start (or Repeated Start) bit has been detected last
0= Start bit was not detected last
Hardware set or clear when Start, Repeated Start or Stop detected.
R_W: Read/Write Information bit (when operating as I2C slave)
1= Read – indicates data transfer is output from slave
0= Write – indicates data transfer is input to slave
Hardware set or clear after reception of I2C device address byte.
RBF: Receive Buffer Full Status bit
1= Receive complete, I2CxRCV is full
0= Receive not complete, I2CxRCV is empty
Hardware set when I2CxRCV is written with received byte. Hardware clear when software
reads I2CxRCV.
bit 0
TBF: Transmit Buffer Full Status bit
1= Transmit in progress, I2CxTRN is full
0= Transmit complete, I2CxTRN is empty
Hardware set when software writes I2CxTRN. Hardware clear at completion of data transmission.
DS70592A-page 170
Preliminary
© 2009 Microchip Technology Inc.
PIC24HJXXXGPX06A/X08A/X10A
REGISTER 17-3: I2CxMSK: I2Cx SLAVE MODE ADDRESS MASK REGISTER
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
R/W-0
R/W-0
AMSK9
AMSK8
bit 15
bit 8
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
AMSK7
AMSK6
AMSK5
AMSK4
AMSK3
AMSK2
AMSK1
AMSK0
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-10
bit 9-0
Unimplemented: Read as ‘0’
AMSKx: Mask for Address Bit x Select bit
1= Enable masking for bit x of incoming message address; bit match not required in this position
0= Disable masking for bit x; bit match required in this position
© 2009 Microchip Technology Inc.
Preliminary
DS70592A-page 171
PIC24HJXXXGPX06A/X08A/X10A
NOTES:
DS70592A-page 172
Preliminary
© 2009 Microchip Technology Inc.
PIC24HJXXXGPX06A/X08A/X10A
• Hardware Flow Control Option with UxCTS and
UxRTS pins
18.0 UNIVERSAL ASYNCHRONOUS
RECEIVER TRANSMITTER
(UART)
• Fully Integrated Baud Rate Generator with 16-bit
Prescaler
• Baud rates ranging from 1 Mbps to 15 bps at 16x
mode at 40 MIPS
Note:
This data sheet summarizes the features
of the PIC24HJXXXGPX06A/X08A/X10A
family of devices. However, it is not
intended to be a comprehensive reference
source. To complement the information in
this data sheet, refer to the “PIC24H
Family Reference Manual”, Section 17.
“UART” (DS70232), which is available
• Baud rates ranging from 4 Mbps to 61 bps at 4x mode
at 40 MIPS
• 4-deep First-In-First-Out (FIFO) Transmit Data
Buffer
• 4-Deep FIFO Receive Data Buffer
• Parity, Framing and Buffer Overrun Error Detection
from
the
Microchip
website
• Support for 9-bit mode with Address Detect
(9th bit = 1)
(www.microchip.com).
The Universal Asynchronous Receiver Transmitter
(UART) module is one of the serial I/O modules avail-
able in the PIC24HJXXXGPX06A/X08A/X10A device
family. The UART is a full-duplex asynchronous system
that can communicate with peripheral devices, such as
personal computers, LIN, RS-232 and RS-485 inter-
faces. The module also supports a hardware flow con-
trol option with the UxCTS and UxRTS pins and also
includes an IrDA® encoder and decoder.
• Transmit and Receive Interrupts
• A Separate Interrupt for all UART Error Conditions
• Loopback mode for Diagnostic Support
• Support for Sync and Break Characters
• Supports Automatic Baud Rate Detection
• IrDA® Encoder and Decoder Logic
• 16x Baud Clock Output for IrDA® Support
A simplified block diagram of the UART is shown in
Figure 18-1. The UART module consists of the key
important hardware elements:
The primary features of the UART module are:
• Full-Duplex, 8 or 9-bit Data Transmission through
the UxTX and UxRX pins
• Baud Rate Generator
• Even, Odd or No Parity Options (for 8-bit data)
• One or Two Stop bits
• Asynchronous Transmitter
• Asynchronous Receiver
FIGURE 18-1:
UART SIMPLIFIED BLOCK DIAGRAM
Baud Rate Generator
IrDA®
BCLK
Hardware Flow Control
UART Receiver
UxRTS
UxCTS
UxRX
UxTX
UART Transmitter
Note 1: Both UART1 and UART2 can trigger a DMA data transfer. If U1TX, U1RX, U2TX or U2RX is selected as
a DMA IRQ source, a DMA transfer occurs when the U1TXIF, U1RXIF, U2TXIF or U2RXIF bit gets set as
a result of a UART1 or UART2 transmission or reception.
2: If DMA transfers are required, the UART TX/RX FIFO buffer must be set to a size of 1 byte/word
(i.e., UTXISEL<1:0> = 00and URXISEL<1:0> = 00).
© 2009 Microchip Technology Inc.
Preliminary
DS70592A-page 173
PIC24HJXXXGPX06A/X08A/X10A
REGISTER 18-1: UxMODE: UARTx MODE REGISTER
R/W-0
UARTEN(1)
U-0
—
R/W-0
USIDL
R/W-0
IREN(2)
R/W-0
U-0
—
R/W-0
R/W-0
RTSMD
UEN<1:0>
bit 15
bit 8
R/W-0 HC
WAKE
R/W-0
R/W-0 HC
ABAUD
R/W-0
R/W-0
BRGH
R/W-0
R/W-0
R/W-0
LPBACK
URXINV
PDSEL<1:0>
STSEL
bit 7
bit 0
Legend:
HC = Hardware cleared
W = Writable bit
R = Readable bit
-n = Value at POR
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
‘1’ = Bit is set
bit 15
UARTEN: UARTx Enable bit(1)
1= UARTx is enabled; all UARTx pins are controlled by UARTx as defined by UEN<1:0>
0= UARTx is disabled; all UARTx pins are controlled by port latches; UARTx power consumption
minimal
bit 14
bit 13
Unimplemented: Read as ‘0’
USIDL: Stop in Idle Mode bit
1= Discontinue module operation when device enters Idle mode
0= Continue module operation in Idle mode
bit 12
bit 11
IREN: IrDA® Encoder and Decoder Enable bit(2)
1= IrDA® encoder and decoder enabled
0= IrDA® encoder and decoder disabled
RTSMD: Mode Selection for UxRTS Pin bit
1= UxRTS pin in Simplex mode
0= UxRTS pin in Flow Control mode
bit 10
Unimplemented: Read as ‘0’
UEN<1:0>: UARTx Enable bits
bit 9-8
11= UxTX, UxRX and BCLK pins are enabled and used; UxCTS pin controlled by port latches
10= UxTX, UxRX, UxCTS and UxRTS pins are enabled and used
01= UxTX, UxRX and UxRTS pins are enabled and used; UxCTS pin controlled by port latches
00= UxTX and UxRX pins are enabled and used; UxCTS and UxRTS/BCLK pins controlled by
port latches
bit 7
WAKE: Wake-up on Start bit Detect During Sleep Mode Enable bit
1= UARTx will continue to sample the UxRX pin; interrupt generated on falling edge; bit cleared
in hardware on following rising edge
0= No wake-up enabled
bit 6
bit 5
LPBACK: UARTx Loopback Mode Select bit
1= Enable Loopback mode
0= Loopback mode is disabled
ABAUD: Auto-Baud Enable bit
1= Enable baud rate measurement on the next character – requires reception of a Sync field (0x55)
before any data; cleared in hardware upon completion
0= Baud rate measurement disabled or completed
Note 1: Refer to Section 17. “UART” (DS70232) in the “PIC24H Family Reference Manual” for information on
enabling the UART module for receive or transmit operation.
2: This feature is only available for the 16x BRG mode (BRGH = 0).
DS70592A-page 174
Preliminary
© 2009 Microchip Technology Inc.
PIC24HJXXXGPX06A/X08A/X10A
REGISTER 18-1: UxMODE: UARTx MODE REGISTER (CONTINUED)
bit 4
URXINV: Receive Polarity Inversion bit
1= UxRX Idle state is ‘0’
0= UxRX Idle state is ‘1’
bit 3
BRGH: High Baud Rate Enable bit
1= BRG generates 4 clocks per bit period (4x baud clock, High-Speed mode)
0= BRG generates 16 clocks per bit period (16x baud clock, Standard mode)
bit 2-1
PDSEL<1:0>: Parity and Data Selection bits
11= 9-bit data, no parity
10= 8-bit data, odd parity
01= 8-bit data, even parity
00= 8-bit data, no parity
bit 0
STSEL: Stop Bit Selection bit
1= Two Stop bits
0= One Stop bit
Note 1: Refer to Section 17. “UART” (DS70232) in the “PIC24H Family Reference Manual” for information on
enabling the UART module for receive or transmit operation.
2: This feature is only available for the 16x BRG mode (BRGH = 0).
© 2009 Microchip Technology Inc.
Preliminary
DS70592A-page 175
PIC24HJXXXGPX06A/X08A/X10A
REGISTER 18-2: UxSTA: UARTx STATUS AND CONTROL REGISTER
R/W-0
R/W-0
R/W-0
U-0
—
R/W-0 HC
UTXBRK
R/W-0
UTXEN(1)
R-0
R-1
UTXISEL1
UTXINV
UTXISEL0
UTXBF
TRMT
bit 15
bit 8
R/W-0
R/W-0
R/W-0
R-1
R-0
R-0
R/C-0
R-0
URXISEL<1:0>
ADDEN
RIDLE
PERR
FERR
OERR
URXDA
bit 7
bit 0
Legend:
HC = Hardware cleared
W = Writable bit
C = Clear only bit
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
R = Readable bit
-n = Value at POR
‘1’ = Bit is set
bit 15,13
UTXISEL<1:0>: Transmission Interrupt Mode Selection bits
11= Reserved; do not use
10= Interrupt when a character is transferred to the Transmit Shift Register, and as a result, the
transmit buffer becomes empty
01= Interrupt when the last character is shifted out of the Transmit Shift Register; all transmit
operations are completed
00= Interrupt when a character is transferred to the Transmit Shift Register (this implies there is
at least one character open in the transmit buffer)
bit 14
UTXINV: Transmit Polarity Inversion bit
If IREN = 0:
1= UxTX Idle state is ‘0’
0= UxTX Idle state is ‘1’
If IREN = 1:
1= IrDA® encoded UxTX Idle state is ‘1’
0= IrDA® encoded UxTX Idle state is ‘0’
bit 12
bit 11
Unimplemented: Read as ‘0’
UTXBRK: Transmit Break bit
1= Send Sync Break on next transmission – Start bit, followed by twelve ‘0’ bits, followed by Stop bit;
cleared by hardware upon completion
0= Sync Break transmission disabled or completed
bit 10
UTXEN: Transmit Enable bit(1)
1= Transmit enabled, UxTX pin controlled by UARTx
0= Transmit disabled, any pending transmission is aborted and buffer is reset. UxTX pin controlled
by port.
bit 9
UTXBF: Transmit Buffer Full Status bit (read-only)
1= Transmit buffer is full
0= Transmit buffer is not full, at least one more character can be written
bit 8
TRMT: Transmit Shift Register Empty bit (read-only)
1= Transmit Shift Register is empty and transmit buffer is empty (the last transmission has completed)
0= Transmit Shift Register is not empty, a transmission is in progress or queued
bit 7-6
URXISEL<1:0>: Receive Interrupt Mode Selection bits
11= Interrupt is set on UxRSR transfer making the receive buffer full (i.e., has 4 data characters)
10= Interrupt is set on UxRSR transfer making the receive buffer 3/4 full (i.e., has 3 data characters)
0x= Interrupt is set when any character is received and transferred from the UxRSR to the receive
buffer. Receive buffer has one or more characters.
Note 1: Refer to Section 17. “UART” (DS70232) in the “PIC24H Family Reference Manual” for information on
enabling the UART module for transmit operation.
DS70592A-page 176
Preliminary
© 2009 Microchip Technology Inc.
PIC24HJXXXGPX06A/X08A/X10A
REGISTER 18-2: UxSTA: UARTx STATUS AND CONTROL REGISTER (CONTINUED)
bit 5
bit 4
bit 3
bit 2
ADDEN: Address Character Detect bit (bit 8 of received data = 1)
1= Address Detect mode enabled. If 9-bit mode is not selected, this does not take effect
0= Address Detect mode disabled
RIDLE: Receiver Idle bit (read-only)
1= Receiver is Idle
0= Receiver is active
PERR: Parity Error Status bit (read-only)
1= Parity error has been detected for the current character (character at the top of the receive FIFO)
0= Parity error has not been detected
FERR: Framing Error Status bit (read-only)
1= Framing error has been detected for the current character (character at the top of the receive
FIFO)
0= Framing error has not been detected
bit 1
bit 0
OERR: Receive Buffer Overrun Error Status bit (read/clear only)
1= Receive buffer has overflowed
0= Receive buffer has not overflowed. Clearing a previously set OERR bit (1→ 0transition) will reset
the receiver buffer and the UxRSR to the empty state
URXDA: Receive Buffer Data Available bit (read-only)
1= Receive buffer has data, at least one more character can be read
0= Receive buffer is empty
Note 1: Refer to Section 17. “UART” (DS70232) in the “PIC24H Family Reference Manual” for information on
enabling the UART module for transmit operation.
© 2009 Microchip Technology Inc.
Preliminary
DS70592A-page 177
PIC24HJXXXGPX06A/X08A/X10A
NOTES:
DS70592A-page 178
Preliminary
© 2009 Microchip Technology Inc.
PIC24HJXXXGPX06A/X08A/X10A
• Low-power Sleep and Idle mode
19.0 ENHANCED CAN (ECAN™)
The CAN bus module consists of a protocol engine and
message buffering/control. The CAN protocol engine
handles all functions for receiving and transmitting
messages on the CAN bus. Messages are transmitted
by first loading the appropriate data registers. Status
and errors can be checked by reading the appropriate
registers. Any message detected on the CAN bus is
checked for errors and then matched against filters to
see if it should be received and stored in one of the
receive registers.
MODULE
Note:
This data sheet summarizes the features
of the PIC24HJXXXGPX06A/X08A/X10A
family of devices. However, it is not
intended to be a comprehensive reference
source. To complement the information in
this data sheet, refer to the “PIC24H
Family Reference Manual”, Section 21.
“Enhanced Controller Area Network
(ECAN™)” (DS70226), which is available
from
the
Microchip
website
19.2 Frame Types
(www.microchip.com).
The CAN module transmits various types of frames
which include data messages, remote transmission
requests and as other frames that are automatically
generated for control purposes. The following frame
types are supported:
19.1 Overview
The Enhanced Controller Area Network (ECAN™)
module is a serial interface, useful for communicating
with other CAN modules or microcontroller devices.
This interface/protocol was designed to allow commu-
• Standard Data Frame:
nications
within
noisy
environments.
The
A standard data frame is generated by a node
when the node wishes to transmit data. It includes
an 11-bit standard identifier (SID) but not an 18-bit
extended identifier (EID).
PIC24HJXXXGPX06A/X08A/X10A devices contain up
to two ECAN modules.
The CAN module is a communication controller imple-
menting the CAN 2.0 A/B protocol, as defined in the
BOSCH specification. The module will support CAN 1.2,
CAN 2.0A, CAN 2.0B Passive and CAN 2.0B Active
versions of the protocol. The module implementation is
a full CAN system. The CAN specification is not covered
within this data sheet. The reader may refer to the
BOSCH CAN specification for further details.
• Extended Data Frame:
An extended data frame is similar to a standard
data frame but includes an extended identifier as
well.
• Remote Frame:
It is possible for a destination node to request the
data from the source. For this purpose, the
destination node sends a remote frame with an
identifier that matches the identifier of the required
data frame. The appropriate data source node will
then send a data frame as a response to this
remote request.
The module features are as follows:
• Implementation of the CAN protocol, CAN 1.2,
CAN 2.0A and CAN 2.0B
• Standard and extended data frames
• 0-8 bytes data length
• Programmable bit rate up to 1 Mbit/sec
• Error Frame:
• Automatic response to remote transmission
requests
An error frame is generated by any node that
detects a bus error. An error frame consists of two
fields: an error flag field and an error delimiter
field.
• Up to 8 transmit buffers with application specified
prioritization and abort capability (each buffer may
contain up to 8 bytes of data)
• Up to 32 receive buffers (each buffer may contain
up to 8 bytes of data)
• Overload Frame:
An overload frame can be generated by a node as
a result of two conditions. First, the node detects
a dominant bit during interframe space which is an
illegal condition. Second, due to internal condi-
tions, the node is not yet able to start reception of
the next message. A node may generate a maxi-
mum of 2 sequential overload frames to delay the
start of the next message.
• Up to 16 full (standard/extended identifier)
acceptance filters
• 3 full acceptance filter masks
• DeviceNet™ addressing support
• Programmable wake-up functionality with
integrated low-pass filter
• Programmable Loopback mode supports self-test
operation
• Interframe Space:
• Signaling via interrupt capabilities for all CAN
receiver and transmitter error states
Interframe space separates a proceeding frame
(of whatever type) from a following data or remote
frame.
• Programmable clock source
• Programmable link to input capture module (IC2
for both CAN1 and CAN2) for time-stamping and
network synchronization
© 2009 Microchip Technology Inc.
Preliminary
DS70592A-page 179
PIC24HJXXXGPX06A/X08A/X10A
FIGURE 19-1:
ECAN™ MODULE BLOCK DIAGRAM
RXF15 Filter
RXF14 Filter
RXF13 Filter
RXF12 Filter
RXF11 Filter
RXF10 Filter
RXF9 Filter
RXF8 Filter
RXF7 Filter
RXF6 Filter
RXF5 Filter
RXF4 Filter
RXF3 Filter
RXF2 Filter
RXF1 Filter
RXF0 Filter
DMA Controller
TRB7 TX/RX Buffer Control Register
TRB6 TX/RX Buffer Control Register
TRB5 TX/RX Buffer Control Register
TRB4 TX/RX Buffer Control Register
TRB3 TX/RX Buffer Control Register
TRB2 TX/RX Buffer Control Register
TRB1 TX/RX Buffer Control Register
TRB0 TX/RX Buffer Control Register
RXM2 Mask
RXM1 Mask
RXM0 Mask
Transmit Byte
Sequencer
Message Assembly
Buffer
Control
Configuration
Logic
CPU
Bus
CAN Protocol
Engine
Interrupts
CiTX(1) CiRX(1)
Note 1: i = 1 or 2 refers to a particular ECAN™ module (ECAN1 or ECAN2).
DS70592A-page 180
Preliminary
© 2009 Microchip Technology Inc.
PIC24HJXXXGPX06A/X08A/X10A
19.3 Modes of Operation
Note:
Typically, if the CAN module is allowed to
transmit in a particular mode of operation
and a transmission is requested immedi-
ately after the CAN module has been
placed in that mode of operation, the mod-
ule waits for 11 consecutive recessive bits
on the bus before starting transmission. If
the user switches to Disable mode within
this 11-bit period, then this transmission is
aborted and the corresponding TXABT bit
is set and TXREQ bit is cleared.
The CAN module can operate in one of several operation
modes selected by the user. These modes include:
• Initialization Mode
• Disable Mode
• Normal Operation Mode
• Listen Only Mode
• Listen All Messages Mode
• Loopback Mode
Modes are requested by setting the REQOP<2:0> bits
(CiCTRL1<10:8>). Entry into a mode is Acknowledged
19.3.3
NORMAL OPERATION MODE
by
monitoring
the
OPMODE<2:0>
bits
Normal Operation mode is selected when
REQOP<2:0> = 000. In this mode, the module is
activated and the I/O pins will assume the CAN bus
functions. The module will transmit and receive CAN
bus messages via the CiTX and CiRX pins.
(CiCTRL1<7:5>). The module will not change the mode
and the OPMODE bits until a change in mode is
acceptable, generally during bus Idle time, which is
defined as at least 11 consecutive recessive bits.
19.3.1
INITIALIZATION MODE
19.3.4
LISTEN ONLY MODE
In the Initialization mode, the module will not transmit or
receive. The error counters are cleared and the inter-
rupt flags remain unchanged. The programmer will
have access to Configuration registers that are access
restricted in other modes. The module will protect the
user from accidentally violating the CAN protocol
through programming errors. All registers which control
the configuration of the module can not be modified
while the module is on-line. The CAN module will not
be allowed to enter the Configuration mode while a
transmission is taking place. The Configuration mode
serves as a lock to protect the following registers.
If the Listen Only mode is activated, the module on the
CAN bus is passive. The transmitter buffers revert to
the port I/O function. The receive pins remain inputs.
For the receiver, no error flags or Acknowledge signals
are sent. The error counters are deactivated in this
state. The Listen Only mode can be used for detecting
the baud rate on the CAN bus. To use this, it is neces-
sary that there are at least two further nodes that
communicate with each other.
19.3.5
LISTEN ALL MESSAGES MODE
The module can be set to ignore all errors and receive
any message. The Listen All Messages mode is acti-
vated by setting REQOP<2:0> = ‘111’. In this mode,
the data which is in the message assembly buffer, until
the time an error occurred, is copied in the receive buf-
fer and can be read via the CPU interface.
• All Module Control Registers
• Baud Rate and Interrupt Configuration Registers
• Bus Timing Registers
• Identifier Acceptance Filter Registers
• Identifier Acceptance Mask Registers
19.3.2
DISABLE MODE
19.3.6
LOOPBACK MODE
In Disable mode, the module will not transmit or
receive. The module has the ability to set the WAKIF bit
due to bus activity, however, any pending interrupts will
remain and the error counters will retain their value.
If the Loopback mode is activated, the module will con-
nect the internal transmit signal to the internal receive
signal at the module boundary. The transmit and
receive pins revert to their port I/O function.
If the REQOP<2:0> bits (CiCTRL1<10:8>) = 001, the
module will enter the Module Disable mode. If the module
is active, the module will wait for 11 recessive bits on the
CAN bus, detect that condition as an Idle bus, then
accept the module disable command. When the
OPMODE<2:0> bits (CiCTRL1<7:5>) = 001, that indi-
cates whether the module successfully went into Module
Disable mode. The I/O pins will revert to normal I/O
function when the module is in the Module Disable mode.
The module can be programmed to apply a low-pass
filter function to the CiRX input line while the module or
the CPU is in Sleep mode. The WAKFIL bit
(CiCFG2<14>) enables or disables the filter.
© 2009 Microchip Technology Inc.
Preliminary
DS70592A-page 181
PIC24HJXXXGPX06A/X08A/X10A
REGISTER 19-1: CiCTRL1: ECAN™ MODULE CONTROL REGISTER 1
U-0
—
U-0
—
R/W-0
CSIDL
R/W-0
ABAT
r-0
—
R/W-1
R/W-0
R/W-0
bit 8
REQOP<2:0>
bit 15
R-1
R-0
R-0
U-0
—
R/W-0
U-0
—
U-0
—
R/W-0
WIN
OPMODE<2:0>
CANCAP
bit 7
Legend:
bit 0
r = Bit is Reserved
W = Writable bit
‘1’ = Bit is set
R = Readable bit
-n = Value at POR
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-14
bit 13
Unimplemented: Read as ‘0’
CSIDL: Stop in Idle Mode bit
1= Discontinue module operation when device enters Idle mode
0= Continue module operation in Idle mode
bit 12
ABAT: Abort All Pending Transmissions bit
Signal all transmit buffers to abort transmission. Module will clear this bit when all transmissions
are aborted.
bit 11
Reserved: Do not use
bit 10-8
REQOP<2:0>: Request Operation Mode bits
000= Set Normal Operation mode
001= Set Disable mode
010= Set Loopback mode
011= Set Listen Only Mode
100= Set Configuration mode
101= Reserved – do not use
110= Reserved – do not use
111= Set Listen All Messages mode
bit 7-5
OPMODE<2:0>: Operation Mode bits
000= Module is in Normal Operation mode
001= Module is in Disable mode
010= Module is in Loopback mode
011= Module is in Listen Only mode
100= Module is in Configuration mode
101= Reserved
110= Reserved
111= Module is in Listen All Messages mode
bit 4
bit 3
Unimplemented: Read as ‘0’
CANCAP: CAN Message Receive Timer Capture Event Enable bit
1= Enable input capture based on CAN message receive
0= Disable CAN capture
bit 2-1
bit 0
Unimplemented: Read as ‘0’
WIN: SFR Map Window Select bit
1= Use filter window
0= Use buffer window
DS70592A-page 182
Preliminary
© 2009 Microchip Technology Inc.
PIC24HJXXXGPX06A/X08A/X10A
REGISTER 19-2: CiCTRL2: ECAN™ MODULE CONTROL REGISTER 2
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
bit 15
bit 8
bit 0
U-0
—
U-0
—
U-0
—
R-0
R-0
R-0
R-0
R-0
DNCNT<4:0>
bit 7
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-5
bit 4-0
Unimplemented: Read as ‘0’
DNCNT<4:0>: DeviceNet™ Filter Bit Number bits
10010-11111= Invalid selection
10001= Compare up to data byte 3, bit 6 with EID<17>
•
•
•
00001= Compare up to data byte 1, bit 7 with EID<0>
00000= Do not compare data bytes
© 2009 Microchip Technology Inc.
Preliminary
DS70592A-page 183
PIC24HJXXXGPX06A/X08A/X10A
REGISTER 19-3: CiVEC: ECAN™ MODULE INTERRUPT CODE REGISTER
U-0
—
U-0
—
U-0
—
R-0
R-0
R-0
R-0
R-0
R-0
R-0
FILHIT<4:0>
bit 15
bit 8
bit 0
U-0
—
R-1
R-0
R-0
R-0
R-0
ICODE<6:0>
bit 7
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-13
bit 12-8
Unimplemented: Read as ‘0’
FILHIT<4:0>: Filter Hit Number bits
10000-11111= Reserved
01111= Filter 15
•
•
•
00001= Filter 1
00000= Filter 0
bit 7
Unimplemented: Read as ‘0’
bit 6-0
ICODE<6:0>: Interrupt Flag Code bits
1000101-1111111= Reserved
1000100= FIFO almost full interrupt
1000011= Receiver overflow interrupt
1000010= Wake-up interrupt
1000001= Error interrupt
1000000= No interrupt
0010000-0111111= Reserved
0001111= RB15 buffer Interrupt
•
•
•
0001001= RB9 buffer interrupt
0001000= RB8 buffer interrupt
0000111= TRB7 buffer interrupt
0000110= TRB6 buffer interrupt
0000101= TRB5 buffer interrupt
0000100= TRB4 buffer interrupt
0000011= TRB3 buffer interrupt
0000010= TRB2 buffer interrupt
0000001= TRB1 buffer interrupt
0000000= TRB0 Buffer interrupt
DS70592A-page 184
Preliminary
© 2009 Microchip Technology Inc.
PIC24HJXXXGPX06A/X08A/X10A
REGISTER 19-4: CiFCTRL: ECAN™ MODULE FIFO CONTROL REGISTER
R/W-0
R/W-0
R/W-0
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
DMABS<2:0>
bit 15
bit 8
R/W-0
bit 0
U-0
—
U-0
—
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
FSA<4:0>
bit 7
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-13
DMABS<2:0>: DMA Buffer Size bits
111= Reserved
110= 32 buffers in DMA RAM
101= 24 buffers in DMA RAM
100= 16 buffers in DMA RAM
011= 12 buffers in DMA RAM
010= 8 buffers in DMA RAM
001= 6 buffers in DMA RAM
000= 4 buffers in DMA RAM
bit 12-5
bit 4-0
Unimplemented: Read as ‘0’
FSA<4:0>: FIFO Area Starts with Buffer bits
11111= RB31 buffer
11110= RB30 buffer
•
•
•
00001= TRB1 buffer
00000= TRB0 buffer
© 2009 Microchip Technology Inc.
Preliminary
DS70592A-page 185
PIC24HJXXXGPX06A/X08A/X10A
REGISTER 19-5: CiFIFO: ECAN™ MODULE FIFO STATUS REGISTER
U-0
—
U-0
—
R-0
R-0
R-0
R-0
FBP<5:0>
R-0
R-0
R-0
R-0
bit 15
bit 8
bit 0
U-0
—
U-0
—
R-0
R-0
R-0
R-0
FNRB<5:0>
bit 7
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-14
bit 13-8
Unimplemented: Read as ‘0’
FBP<5:0>: FIFO Write Buffer Pointer bits
011111= RB31 buffer
011110= RB30 buffer
•
•
•
000001= TRB1 buffer
000000= TRB0 buffer
bit 7-6
bit 5-0
Unimplemented: Read as ‘0’
FNRB<5:0>: FIFO Next Read Buffer Pointer bits
011111= RB31 buffer
011110= RB30 buffer
•
•
•
000001= TRB1 buffer
000000= TRB0 buffer
DS70592A-page 186
Preliminary
© 2009 Microchip Technology Inc.
PIC24HJXXXGPX06A/X08A/X10A
REGISTER 19-6: CiINTF: ECAN™ MODULE INTERRUPT FLAG REGISTER
U-0
—
U-0
—
R-0
R-0
R-0
R-0
R-0
R-0
TXBO
TXBP
RXBP
TXWAR
RXWAR
EWARN
bit 15
bit 8
R/C-0
IVRIF
R/C-0
R/C-0
U-0
—
R/C-0
R/C-0
R/C-0
RBIF
R/C-0
TBIF
WAKIF
ERRIF
FIFOIF
RBOVIF
bit 7
bit 0
Legend:
C = Clear only bit
W = Writable bit
‘1’ = Bit is set
R = Readable bit
-n = Value at POR
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-14
bit 13
bit 12
bit 11
bit 10
bit 9
Unimplemented: Read as ‘0’
TXBO: Transmitter in Error State Bus Off bit
TXBP: Transmitter in Error State Bus Passive bit
RXBP: Receiver in Error State Bus Passive bit
TXWAR: Transmitter in Error State Warning bit
RXWAR: Receiver in Error State Warning bit
EWARN: Transmitter or Receiver in Error State Warning bit
IVRIF: Invalid Message Received Interrupt Flag bit
WAKIF: Bus Wake-up Activity Interrupt Flag bit
ERRIF: Error Interrupt Flag bit (multiple sources in CiINTF<13:8> register)
Unimplemented: Read as ‘0’
bit 8
bit 7
bit 6
bit 5
bit 4
bit 3
FIFOIF: FIFO Almost Full Interrupt Flag bit
RBOVIF: RX Buffer Overflow Interrupt Flag bit
RBIF: RX Buffer Interrupt Flag bit
bit 2
bit 1
bit 0
TBIF: TX Buffer Interrupt Flag bit
© 2009 Microchip Technology Inc.
Preliminary
DS70592A-page 187
PIC24HJXXXGPX06A/X08A/X10A
REGISTER 19-7: CiINTE: ECAN™ MODULE INTERRUPT ENABLE REGISTER
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
bit 15
bit 8
R/W-0
IVRIE
R/W-0
R/W-0
ERRIE
U-0
—
R/W-0
R/W-0
R/W-0
RBIE
R/W-0
TBIE
WAKIE
FIFOIE
RBOVIE
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-8
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Unimplemented: Read as ‘0’
IVRIE: Invalid Message Received Interrupt Enable bit
WAKIE: Bus Wake-up Activity Interrupt Flag bit
ERRIE: Error Interrupt Enable bit
Unimplemented: Read as ‘0’
FIFOIE: FIFO Almost Full Interrupt Enable bit
RBOVIE: RX Buffer Overflow Interrupt Enable bit
RBIE: RX Buffer Interrupt Enable bit
TBIE: TX Buffer Interrupt Enable bit
DS70592A-page 188
Preliminary
© 2009 Microchip Technology Inc.
PIC24HJXXXGPX06A/X08A/X10A
REGISTER 19-8: CiEC: ECAN™ MODULE TRANSMIT/RECEIVE ERROR COUNT REGISTER
R-0
bit 15
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
TERRCNT<7:0>
bit 8
bit 0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
RERRCNT<7:0>
bit 7
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-8
bit 7-0
TERRCNT<7:0>: Transmit Error Count bits
RERRCNT<7:0>: Receive Error Count bits
© 2009 Microchip Technology Inc.
Preliminary
DS70592A-page 189
PIC24HJXXXGPX06A/X08A/X10A
REGISTER 19-9: CiCFG1: ECAN™ MODULE BAUD RATE CONFIGURATION REGISTER 1
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
bit 15
bit 8
R/W-0
bit 0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
SJW<1:0>
BRP<5:0>
bit 7
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-8
bit 7-6
Unimplemented: Read as ‘0’
SJW<1:0>: Synchronization Jump Width bits
11= Length is 4 x TQ
10= Length is 3 x TQ
01= Length is 2 x TQ
00= Length is 1 x TQ
bit 5-0
BRP<5:0>: Baud Rate Prescaler bits
11 1111= TQ = 2 x 64 x 1/FCAN
•
•
•
00 0010= TQ = 2 x 3 x 1/FCAN
00 0001= TQ = 2 x 2 x 1/FCAN
00 0000= TQ = 2 x 1 x 1/FCAN
DS70592A-page 190
Preliminary
© 2009 Microchip Technology Inc.
PIC24HJXXXGPX06A/X08A/X10A
REGISTER 19-10: CiCFG2: ECAN™ MODULE BAUD RATE CONFIGURATION REGISTER 2
U-0
—
R/W-x
U-0
—
U-0
—
U-0
—
R/W-x
R/W-x
R/W-x
bit 8
R/W-x
bit 0
WAKFIL
SEG2PH<2:0>
bit 15
R/W-x
R/W-x
SAM
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
SEG2PHTS
SEG1PH<2:0>
PRSEG<2:0>
bit 7
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15
bit 14
Unimplemented: Read as ‘0’
WAKFIL: Select CAN bus Line Filter for Wake-up bit
1= Use CAN bus line filter for wake-up
0= CAN bus line filter is not used for wake-up
bit 13-11
bit 10-8
Unimplemented: Read as ‘0’
SEG2PH<2:0>: Phase Buffer Segment 2 bits
111= Length is 8 x TQ
000= Length is 1 x TQ
bit 7
SEG2PHTS: Phase Segment 2 Time Select bit
1= Freely programmable
0= Maximum of SEG1PH bits or Information Processing Time (IPT), whichever is greater
bit 6
SAM: Sample of the CAN bus Line bit
1= Bus line is sampled three times at the sample point
0= Bus line is sampled once at the sample point
bit 5-3
bit 2-0
SEG1PH<2:0>: Phase Buffer Segment 1 bits
111= Length is 8 x TQ
000= Length is 1 x TQ
PRSEG<2:0>: Propagation Time Segment bits
111= Length is 8 x TQ
000= Length is 1 x TQ
© 2009 Microchip Technology Inc.
Preliminary
DS70592A-page 191
PIC24HJXXXGPX06A/X08A/X10A
REGISTER 19-11: CiFEN1: ECAN™ MODULE ACCEPTANCE FILTER ENABLE REGISTER
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
FLTEN15
FLTEN14
FLTEN13
FLTEN12
FLTEN11
FLTEN10
FLTEN9
FLTEN8
bit 15
bit 8
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
FLTEN7
FLTEN6
FLTEN5
FLTEN4
FLTEN3
FLTEN2
FLTEN1
FLTEN0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
-n = Value at POR
bit 15-0
FLTENn: Enable Filter n to Accept Messages bits
1= Enable Filter n
0= Disable Filter n
REGISTER 19-12: CiBUFPNT1: ECAN™ MODULE FILTER 0-3 BUFFER POINTER REGISTER
R/W-0
bit 15
R/W-0
bit 7
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
bit 8
R/W-0
F3BP<3:0>
F2BP<3:0>
R/W-0
F1BP<3:0>
R/W-0
R/W-0
R/W-0
R/W-0
F0BP<3:0>
R/W-0
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-12
bit 11-8
bit 7-4
F3BP<3:0>: RX Buffer Written when Filter 3 Hits bits
F2BP<3:0>: RX Buffer Written when Filter 2 Hits bits
F1BP<3:0>: RX Buffer Written when Filter 1 Hits bits
F0BP<3:0>: RX Buffer Written when Filter 0 Hits bits
bit 3-0
1111= Filter hits received in RX FIFO buffer
1110= Filter hits received in RX Buffer 14
•
•
•
0001= Filter hits received in RX Buffer 1
0000= Filter hits received in RX Buffer 0
DS70592A-page 192
Preliminary
© 2009 Microchip Technology Inc.
PIC24HJXXXGPX06A/X08A/X10A
REGISTER 19-13: CiBUFPNT2: ECAN™ MODULE FILTER 4-7 BUFFER POINTER REGISTER
R/W-0
bit 15
R/W-0
bit 7
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
bit 8
R/W-0
bit 0
F7BP<3:0>
F6BP<3:0>
R/W-0
F5BP<3:0>
R/W-0
R/W-0
R/W-0
R/W-0
F4BP<3:0>
R/W-0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-12
bit 11-8
bit 7-4
F7BP<3:0>: RX Buffer Written when Filter 7 Hits bits
F6BP<3:0>: RX Buffer Written when Filter 6 Hits bits
F5BP<3:0>: RX Buffer Written when Filter 5 Hits bits
F4BP<3:0>: RX Buffer Written when Filter 4 Hits bits
bit 3-0
REGISTER 19-14: CiBUFPNT3: ECAN™ MODULE FILTER 8-11 BUFFER POINTER REGISTER
R/W-0
bit 15
R/W-0
bit 7
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
bit 8
R/W-0
F11BP<3:0>
F10BP<3:0>
R/W-0
F9BP<3:0>
R/W-0
R/W-0
R/W-0
R/W-0
F8BP<3:0>
R/W-0
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-12
bit 11-8
bit 7-4
F11BP<3:0>: RX Buffer Written when Filter 11 Hits bits
F10BP<3:0>: RX Buffer Written when Filter 10 Hits bits
F9BP<3:0>: RX Buffer Written when Filter 9 Hits bits
F8BP<3:0>: RX Buffer Written when Filter 8 Hits bits
bit 3-0
© 2009 Microchip Technology Inc.
Preliminary
DS70592A-page 193
PIC24HJXXXGPX06A/X08A/X10A
REGISTER 19-15: CiBUFPNT4: ECAN™ MODULE FILTER 12-15 BUFFER POINTER REGISTER
R/W-0
bit 15
R/W-0
bit 7
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
bit 8
R/W-0
bit 0
F15BP<3:0>
F14BP<3:0>
R/W-0
F13BP<3:0>
R/W-0
R/W-0
R/W-0
R/W-0
F12BP<3:0>
R/W-0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-12
bit 11-8
bit 7-4
F15BP<3:0>: RX Buffer Written when Filter 15 Hits bits
F14BP<3:0>: RX Buffer Written when Filter 14 Hits bits
F13BP<3:0>: RX Buffer Written when Filter 13 Hits bits
F12BP<3:0>: RX Buffer Written when Filter 12 Hits bits
bit 3-0
DS70592A-page 194
Preliminary
© 2009 Microchip Technology Inc.
PIC24HJXXXGPX06A/X08A/X10A
REGISTER 19-16: CiRXFnSID: ECAN™ MODULE ACCEPTANCE FILTER n STANDARD IDENTIFIER
(n = 0, 1, ..., 15)
R/W-x
SID10
R/W-x
SID9
R/W-x
SID8
R/W-x
SID7
R/W-x
SID6
R/W-x
SID5
R/W-x
SID4
R/W-x
SID3
bit 15
bit 8
R/W-x
SID2
R/W-x
SID1
R/W-x
SID0
U-0
—
R/W-x
EXIDE
U-0
—
R/W-x
EID17
R/W-x
EID16
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-5
SID<10:0>: Standard Identifier bits
1= Message address bit SIDx must be ‘1’ to match filter
0= Message address bit SIDx must be ‘0’ to match filter
bit 4
bit 3
Unimplemented: Read as ‘0’
EXIDE: Extended Identifier Enable bit
If MIDE = 1then:
1= Match only messages with extended identifier addresses
0= Match only messages with standard identifier addresses
If MIDE = 0then:
Ignore EXIDE bit.
bit 2
Unimplemented: Read as ‘0’
bit 1-0
EID<17:16>: Extended Identifier bits
1= Message address bit EIDx must be ‘1’ to match filter
0= Message address bit EIDx must be ‘0’ to match filter
REGISTER 19-17: CiRXFnEID: ECAN™ MODULE ACCEPTANCE FILTER n EXTENDED IDENTIFIER
(n = 0, 1, ..., 15)
R/W-x
EID15
R/W-x
EID14
R/W-x
EID13
R/W-x
EID12
R/W-x
EID11
R/W-x
EID10
R/W-x
EID9
R/W-x
EID8
bit 15
bit 8
R/W-x
EID7
R/W-x
EID6
R/W-x
EID5
R/W-x
EID4
R/W-x
EID3
R/W-x
EID2
R/W-x
EID1
R/W-x
EID0
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-0
EID<15:0>: Extended Identifier bits
1= Message address bit EIDx must be ‘1’ to match filter
0= Message address bit EIDx must be ‘0’ to match filter
© 2009 Microchip Technology Inc.
Preliminary
DS70592A-page 195
PIC24HJXXXGPX06A/X08A/X10A
REGISTER 19-18: CiFMSKSEL1: ECAN™ MODULE FILTER 7-0 MASK SELECTION REGISTER
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
F7MSK<1:0>
F6MSK<1:0>
F5MSK<1:0>
F4MSK<1:0>
bit 15
bit 8
R/W-0 R/W-0
F3MSK<1:0>
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
F2MSK<1:0>
F1MSK<1:0>
F0MSK<1:0>
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-14
bit 13-12
bit 11-10
bit 9-8
F7MSK<1:0>: Mask Source for Filter 7 bit
F6MSK<1:0>: Mask Source for Filter 6 bit
F5MSK<1:0>: Mask Source for Filter 5 bit
F4MSK<1:0>: Mask Source for Filter 4 bit
F3MSK<1:0>: Mask Source for Filter 3 bit
F2MSK<1:0>: Mask Source for Filter 2 bit
F1MSK<1:0>: Mask Source for Filter 1 bit
F0MSK<1:0>: Mask Source for Filter 0 bit
11= Reserved
bit 7-6
bit 5-4
bit 3-2
bit 1-0
10= Acceptance Mask 2 registers contain mask
01= Acceptance Mask 1 registers contain mask
00= Acceptance Mask 0 registers contain mask
DS70592A-page 196
Preliminary
© 2009 Microchip Technology Inc.
PIC24HJXXXGPX06A/X08A/X10A
REGISTER 19-19: CiFMSKSEL2: ECAN™ FILTER 15-8 MASK SELECTION REGISTER
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
F15MSK<1:0>
F14MSK<1:0>
F13MSK<1:0>
F12MSK<1:0>
bit 15
bit 8
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
F11MSK<1:0>
F10MSK<1:0>
F9MSK<1:0>
F8MSK<1:0>
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-14
F15MSK<1:0>: Mask Source for Filter 15 bit
11= Reserved
10= Acceptance Mask 2 registers contain mask
01= Acceptance Mask 1 registers contain mask
00= Acceptance Mask 0 registers contain mask
bit 13-12
bit 11-10
bit 9-8
F14MSK<1:0>: Mask Source for Filter 14 bit (same values as bit 15-14)
F13MSK<1:0>: Mask Source for Filter 13 bit (same values as bit 15-14)
F12MSK<1:0>: Mask Source for Filter 12 bit (same values as bit 15-14)
F11MSK<1:0>: Mask Source for Filter 11 bit (same values as bit 15-14)
F10MSK<1:0>: Mask Source for Filter 10 bit (same values as bit 15-14)
F9MSK<1:0>: Mask Source for Filter 9 bit (same values as bit 15-14)
F8MSK<1:0>: Mask Source for Filter 8 bit (same values as bit 15-14)
bit 7-6
bit 5-4
bit 3-2
bit 1-0
© 2009 Microchip Technology Inc.
Preliminary
DS70592A-page 197
PIC24HJXXXGPX06A/X08A/X10A
REGISTER 19-20: CiRXMnSID: ECAN™ MODULE ACCEPTANCE FILTER MASK n STANDARD
IDENTIFIER
R/W-x
SID10
R/W-x
SID9
R/W-x
SID8
R/W-x
SID7
R/W-x
SID6
R/W-x
SID5
R/W-x
SID4
R/W-x
SID3
bit 15
bit 8
R/W-x
SID2
R/W-x
SID1
R/W-x
SID0
U-0
—
R/W-x
MIDE
U-0
—
R/W-x
EID17
R/W-x
EID16
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-5
SID<10:0>: Standard Identifier bits
1= Include bit SIDx in filter comparison
0= Bit SIDx is don’t care in filter comparison
bit 4
bit 3
Unimplemented: Read as ‘0’
MIDE: Identifier Receive Mode bit
1= Match only message types (standard or extended address) that correspond to EXIDE bit in filter
0= Match either standard or extended address message if filters match
(i.e., if (Filter SID) = (Message SID) or if (Filter SID/EID) = (Message SID/EID))
bit 2
Unimplemented: Read as ‘0’
bit 1-0
EID<17:16>: Extended Identifier bits
1= Include bit EIDx in filter comparison
0= Bit EIDx is don’t care in filter comparison
REGISTER 19-21: CiRXMnEID: ECAN™ TECHNOLOGY ACCEPTANCE FILTER MASK n EXTENDED
IDENTIFIER
R/W-x
EID15
R/W-x
EID14
R/W-x
EID13
R/W-x
EID12
R/W-x
EID11
R/W-x
EID10
R/W-x
EID9
R/W-x
EID8
bit 15
bit 8
R/W-x
EID7
R/W-x
EID6
R/W-x
EID5
R/W-x
EID4
R/W-x
EID3
R/W-x
EID2
R/W-x
EID1
R/W-x
EID0
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-0
EID<15:0>: Extended Identifier bits
1= Include bit EIDx in filter comparison
0= Bit EIDx is don’t care in filter comparison
DS70592A-page 198
Preliminary
© 2009 Microchip Technology Inc.
PIC24HJXXXGPX06A/X08A/X10A
REGISTER 19-22: CiRXFUL1: ECAN™ MODULE RECEIVE BUFFER FULL REGISTER 1
R/C-0
R/C-0
R/C-0
R/C-0
R/C-0
R/C-0
R/C-0
R/C-0
RXFUL15
RXFUL14
RXFUL13
RXFUL12
RXFUL11
RXFUL10
RXFUL9
RXFUL8
bit 15
bit 8
R/C-0
R/C-0
R/C-0
R/C-0
R/C-0
R/C-0
R/C-0
R/C-0
RXFUL7
RXFUL6
RXFUL5
RXFUL4
RXFUL3
RXFUL2
RXFUL1
RXFUL0
bit 7
bit 0
Legend:
C = Clear only bit
W = Writable bit
‘1’ = Bit is set
R = Readable bit
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
-n = Value at POR
bit 15-0
RXFUL<15:0>: Receive Buffer n Full bits
1= Buffer is full (set by module)
0= Buffer is empty (clear by application software)
REGISTER 19-23: CiRXFUL2: ECAN™ MODULE RECEIVE BUFFER FULL REGISTER 2
R/C-0
R/C-0
R/C-0
R/C-0
R/C-0
R/C-0
R/C-0
R/C-0
RXFUL31
RXFUL30
RXFUL29
RXFUL28
RXFUL27
RXFUL26
RXFUL25
RXFUL24
bit 15
bit 8
R/C-0
R/C-0
R/C-0
R/C-0
R/C-0
R/C-0
R/C-0
R/C-0
RXFUL23
RXFUL22
RXFUL21
RXFUL20
RXFUL19
RXFUL18
RXFUL17
RXFUL16
bit 7
bit 0
Legend:
C = Clear only bit
W = Writable bit
‘1’ = Bit is set
R = Readable bit
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
-n = Value at POR
bit 15-0
RXFUL<31:16>: Receive Buffer n Full bits
1= Buffer is full (set by module)
0= Buffer is empty (clear by application software)
© 2009 Microchip Technology Inc.
Preliminary
DS70592A-page 199
PIC24HJXXXGPX06A/X08A/X10A
REGISTER 19-24: CiRXOVF1: ECAN™ MODULE RECEIVE BUFFER OVERFLOW REGISTER 1
R/C-0
R/C-0
R/C-0
R/C-0
R/C-0
R/C-0
R/C-0
R/C-0
RXOVF15
RXOVF14
RXOVF13
RXOVF12
RXOVF11
RXOVF10
RXOVF9
RXOVF8
bit 15
bit 8
R/C-0
R/C-0
R/C-0
R/C-0
R/C-0
R/C-0
R/C-0
R/C-0
RXOVF7
RXOVF6
RXOVF5
RXOVF4
RXOVF3
RXOVF2
RXOVF1
RXOVF0
bit 7
bit 0
Legend:
C = Clear only bit
W = Writable bit
‘1’ = Bit is set
R = Readable bit
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
-n = Value at POR
bit 15-0
RXOVF<15:0>: Receive Buffer n Overflow bits
1= Module pointed a write to a full buffer (set by module)
0= Overflow is cleared (clear by application software)
REGISTER 19-25: CiRXOVF2: ECAN™ MODULE RECEIVE BUFFER OVERFLOW REGISTER 2
R/C-0
R/C-0
R/C-0
R/C-0
R/C-0
R/C-0
R/C-0
R/C-0
RXOVF24
bit 8
RXOVF31
RXOVF30
RXOVF29
RXOVF28
RXOVF27
RXOVF26
RXOVF25
bit 15
R/C-0
R/C-0
R/C-0
R/C-0
R/C-0
R/C-0
R/C-0
R/C-0
RXOVF23
RXOVF22
RXOVF21
RXOVF20
RXOVF19
RXOVF18
RXOVF17
RXOVF16
bit 7
bit 0
Legend:
C = Clear only bit
W = Writable bit
‘1’ = Bit is set
R = Readable bit
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
-n = Value at POR
bit 15-0
RXOVF<31:16>: Receive Buffer n Overflow bits
1= Module pointed a write to a full buffer (set by module)
0= Overflow is cleared (clear by application software)
DS70592A-page 200
Preliminary
© 2009 Microchip Technology Inc.
PIC24HJXXXGPX06A/X08A/X10A
REGISTER 19-26: CiTRmnCON: ECAN™ MODULE TX/RX BUFFER m CONTROL REGISTER
(m = 0,2,4,6; n = 1,3,5,7)
R/W-0
R-0
R-0
R-0
R/W-0
R/W-0
R/W-0
R/W-0
TXENn
TXABTn
TXLARBn
TXERRn
TXREQn
RTRENn
TXnPRI<1:0>
bit 15
bit 8
R/W-0
R-0
R-0
R-0
R/W-0
R/W-0
R/W-0
R/W-0
TXENm
TXABTm(1) TXLARBm(1) TXERRm(1) TXREQm
RTRENm
TXmPRI<1:0>
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-8
bit 7
See Definition for Bits 7-0, Controls Buffer n
TXENm: TX/RX Buffer Selection bit
1= Buffer TRBn is a transmit buffer
0= Buffer TRBn is a receive buffer
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1-0
TXABTm: Message Aborted bit(1)
1= Message was aborted
0= Message completed transmission successfully
TXLARBm: Message Lost Arbitration bit(1)
1= Message lost arbitration while being sent
0= Message did not lose arbitration while being sent
TXERRm: Error Detected During Transmission bit(1)
1= A bus error occurred while the message was being sent
0= A bus error did not occur while the message was being sent
TXREQm: Message Send Request bit
Setting this bit to ‘1’ requests sending a message. The bit will automatically clear when the message
is successfully sent. Clearing the bit to ‘0’ while set will request a message abort.
RTRENm: Auto-Remote Transmit Enable bit
1= When a remote transmit is received, TXREQ will be set
0= When a remote transmit is received, TXREQ will be unaffected
TXmPRI<1:0>: Message Transmission Priority bits
11= Highest message priority
10= High intermediate message priority
01= Low intermediate message priority
00= Lowest message priority
Note 1: This bit is cleared when TXREQ is set.
© 2009 Microchip Technology Inc.
Preliminary
DS70592A-page 201
PIC24HJXXXGPX06A/X08A/X10A
Note:
The buffers, SID, EID, DLC, Data Field and Receive Status registers are stored in DMA RAM. These are
not Special Function Registers.
REGISTER 19-27: CiTRBnSID: ECAN™ MODULE BUFFER n STANDARD IDENTIFIER
(n = 0, 1, ..., 31)
U-0
—
U-0
—
U-0
—
R/W-x
SID10
R/W-x
SID9
R/W-x
SID8
R/W-x
SID7
R/W-x
SID6
bit 15
bit 8
R/W-x
SID5
R/W-x
SID4
R/W-x
SID3
R/W-x
SID2
R/W-x
SID1
R/W-x
SID0
R/W-x
SRR
R/W-x
IDE
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-13
bit 12-2
bit 1
Unimplemented: Read as ‘0’
SID<10:0>: Standard Identifier bits
SRR: Substitute Remote Request bit
1= Message will request remote transmission
0= Normal message
bit 0
IDE: Extended Identifier bit
1= Message will transmit extended identifier
0= Message will transmit standard identifier
REGISTER 19-28: CiTRBnEID: ECAN™ MODULE BUFFER n EXTENDED IDENTIFIER
(n = 0, 1, ..., 31)
U-0
—
U-0
—
U-0
—
U-0
—
R/W-x
EID17
R/W-x
EID16
R/W-x
EID15
R/W-x
EID14
bit 15
bit 8
R/W-x
EID13
R/W-x
EID12
R/W-x
EID11
R/W-x
EID10
R/W-x
EID9
R/W-x
EID8
R/W-x
EID7
R/W-x
EID6
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-12
bit 11-0
Unimplemented: Read as ‘0’
EID<17:6>: Extended Identifier bits
DS70592A-page 202
Preliminary
© 2009 Microchip Technology Inc.
PIC24HJXXXGPX06A/X08A/X10A
REGISTER 19-29: CiTRBnDLC: ECAN™ MODULE BUFFER n DATA LENGTH CONTROL
(n = 0, 1, ..., 31)
R/W-x
EID5
R/W-x
EID4
R/W-x
EID3
R/W-x
EID2
R/W-x
EID1
R/W-x
EID0
R/W-x
RTR
R/W-x
RB1
bit 15
bit 8
U-0
—
U-0
—
U-0
—
R/W-x
RB0
R/W-x
DLC3
R/W-x
DLC2
R/W-x
DLC1
R/W-x
DLC0
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-10
bit 9
EID<5:0>: Extended Identifier bits
RTR: Remote Transmission Request bit
1= Message will request remote transmission
0= Normal message
bit 8
RB1: Reserved Bit 1
User must set this bit to ‘0’ per CAN protocol.
Unimplemented: Read as ‘0’
bit 7-5
bit 4
RB0: Reserved Bit 0
User must set this bit to ‘0’ per CAN protocol.
DLC<3:0>: Data Length Code bits
bit 3-0
REGISTER 19-30: CiTRBnDm: ECAN™ MODULE BUFFER n DATA FIELD BYTE m
(1)
(n = 0, 1, ..., 31; m = 0, 1, ..., 7)
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
TRBnDm7
TRBnDm6
TRBnDm5
TRBnDm4 TRBnDm3
TRBnDm2
TRBnDm1
TRBnDm0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
-n = Value at POR
bit 7-0
Note 1: The Most Significant Byte contains byte (m + 1) of the buffer.
TRnDm<7:0>: Data Field Buffer ‘n’ Byte ‘m’ bits
© 2009 Microchip Technology Inc.
Preliminary
DS70592A-page 203
PIC24HJXXXGPX06A/X08A/X10A
REGISTER 19-31: CiTRBnSTAT: ECAN™ MODULE RECEIVE BUFFER n STATUS
(n = 0, 1, ..., 31)
U-0
—
U-0
—
U-0
—
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
FILHIT4
FILHIT3
FILHIT2
FILHIT1
FILHIT0
bit 15
bit 8
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-13
bit 12-8
Unimplemented: Read as ‘0’
FILHIT<4:0>: Filter Hit Code bits (only written by module for receive buffers, unused for transmit buffers)
Encodes number of filter that resulted in writing this buffer.
Unimplemented: Read as ‘0’
bit 7-0
DS70592A-page 204
Preliminary
© 2009 Microchip Technology Inc.
PIC24HJXXXGPX06A/X08A/X10A
of analog input pins and external voltage reference
input configuration will depend on the specific device.
Refer to the device data sheet for further details.
20.0 10-BIT/12-BIT
ANALOG-TO-DIGITAL
CONVERTER (ADC)
A block diagram of the Analog-to-Digital Converter is
shown in Figure 20-1.
Note:
This data sheet summarizes the features
of the PIC24HJXXXGPX06A/X08A/X10A
family of devices. However, it is not
intended to be a comprehensive reference
source. To complement the information in
this data sheet, refer to the “PIC24H
Family Reference Manual”, Section 16.
“Analog-to-Digital Converter (ADC)”
(DS70225), which is available from the
Microchip website (www.microchip.com).
20.2 Analog-to-Digital Initialization
The following configuration steps should be performed.
1. Configure the ADC module:
a) Select port pins as analog inputs
(ADxPCFGH<15:0> or ADxPCFGL<15:0>)
b) Select voltage reference source to match
expected range on analog inputs
(ADxCON2<15:13>)
The PIC24HJXXXGPX06A/X08A/X10A devices have
up to 32 Analog-to-Digital input channels. These
devices also have up to 2 Analog-to-Digital converter
modules (ADCx, where ‘x’ = 1 or 2), each with its own
set of Special Function Registers.
c) Select the analog conversion clock to
match desired data rate with processor
clock (ADxCON3<7:0>)
d) Determine how many S/H channels will
be
used
(ADxCON2<9:8>
and
The AD12B bit (ADxCON1<10>) allows each of the
ADC modules to be configured by the user as either a
10-bit, 4-sample/hold ADC (default configuration) or a
12-bit, 1-sample/hold ADC.
ADxPCFGH<15:0> or ADxPCFGL<15:0>)
e) Select the appropriate sample/conversion
sequence
(ADxCON1<7:5>
and
ADxCON3<12:8>)
Note:
The ADC module needs to be disabled
before modifying the AD12B bit.
f) Select how conversion results are
presented in the buffer (ADxCON1<9:8>)
g) Turn on the ADC module (ADxCON1<15>)
2. Configure ADC interrupt (if required):
a) Clear the ADxIF bit
20.1 Key Features
The 10-bit ADC configuration has the following key
features:
b) Select ADC interrupt priority
• Successive Approximation (SAR) conversion
• Conversion speeds of up to 1.1 Msps
• Up to 32 analog input pins
20.3 ADC and DMA
If more than one conversion result needs to be buffered
before triggering an interrupt, DMA data transfers can
be used. Both ADC1 and ADC2 can trigger a DMA data
transfer. If ADC1 or ADC2 is selected as the DMA IRQ
source, a DMA transfer occurs when the AD1IF or
AD2IF bit gets set as a result of an ADC1 or ADC2
sample conversion sequence.
• External voltage reference input pins
• Simultaneous sampling of up to four analog input
pins
• Automatic Channel Scan mode
• Selectable conversion trigger source
• Selectable Buffer Fill modes
The SMPI<3:0> bits (ADxCON2<5:2>) are used to
select how often the DMA RAM buffer pointer is
incremented.
• Two result alignment options (signed/unsigned)
• Operation during CPU Sleep and Idle modes
The 12-bit ADC configuration supports all the above
features, except:
The ADDMABM bit (ADxCON1<12>) determines how
the conversion results are filled in the DMA RAM buffer
area being used for ADC. If this bit is set, DMA buffers
are written in the order of conversion. The module will
provide an address to the DMA channel that is the
same as the address used for the non-DMA
stand-alone buffer. If the ADDMABM bit is cleared, then
DMA buffers are written in Scatter/Gather mode. The
module will provide a scatter/gather address to the
DMA channel, based on the index of the analog input
and the size of the DMA buffer.
• In the 12-bit configuration, conversion speeds of
up to 500 ksps are supported
• There is only 1 sample/hold amplifier in the 12-bit
configuration, so simultaneous sampling of
multiple channels is not supported.
Depending on the particular device pinout, the Ana-
log-to-Digital Converter can have up to 32 analog input
pins, designated AN0 through AN31. In addition, there
are two analog input pins for external voltage reference
connections. These voltage reference inputs may be
shared with other analog input pins. The actual number
© 2009 Microchip Technology Inc.
Preliminary
DS70592A-page 205
PIC24HJXXXGPX06A/X08A/X10A
FIGURE 20-1:
ADCx MODULE BLOCK DIAGRAM
AN0
(3)
ANy
S/H0
CHANNEL
SCAN
+
CH0SB<4:0>
-
CH0SA<4:0>
CH0
CSCNA
AN1
VREF-
CH0NB
CH0NA
(1)
(1)
VREF+
AVDD VREF-
AVSS
AN0
AN3
S/H1
+
-
CH123SA
CH123SB
(2)
CH1
AN6
AN9
VREF-
VREFH
VREFL
CH123NB
CH123NA
ADC1BUF0
SAR ADC
AN1
AN4
S/H2
+
-
CH123SA
CH123SB
(2)
CH2
AN7
AN10
VREF-
CH123NA
CH123NB
AN2
AN5
S/H3
+
-
CH123SA CH123SB
AN8
(2)
CH3
AN11
VREF-
CH123NA
CH123NB
Alternate
Input Selection
Note 1: VREF+, VREF- inputs can be multiplexed with other analog inputs.
2: Channels 1, 2 and 3 are not applicable for the 12-bit mode of operation.
3: For 64-pin devices, y = 17; for 100-pin devices, y =31; for ADC2, y = 15.
DS70592A-page 206
Preliminary
© 2009 Microchip Technology Inc.
PIC24HJXXXGPX06A/X08A/X10A
FIGURE 20-2:
ANALOG-TO-DIGITAL CONVERSION CLOCK PERIOD BLOCK DIAGRAM
ADxCON3<15>
ADC Internal
RC Clock(2)
0
1
TAD
ADxCON3<5:0>
6
ADC Conversion
Clock Multiplier
TCY
(1)
X2
TOSC
1, 2, 3, 4, 5,..., 64
Note 1: Refer to Figure 9-2 for the derivation of FOSC when the PLL is enabled. If the PLL is not used, FOSC is equal to the clock source
frequency. TOSC = 1/FOSC.
2: See the ADC electrical specifications for exact RC clock value.
© 2009 Microchip Technology Inc.
Preliminary
DS70592A-page 207
PIC24HJXXXGPX06A/X08A/X10A
REGISTER 20-1: ADxCON1: ADCx CONTROL REGISTER 1(where x = 1 or 2)
R/W-0
ADON
U-0
—
R/W-0
R/W-0
U-0
—
R/W-0
R/W-0
R/W-0
ADSIDL
ADDMABM
AD12B
FORM<1:0>
bit 15
bit 8
R/W-0
R/W-0
R/W-0
U-0
—
R/W-0
R/W-0
ASAM
R/W-0
HC,HS
R/C-0
HC, HS
SSRC<2:0>
SIMSAM
SAMP
DONE
bit 7
Legend:
bit 0
HC = Cleared by hardware
W = Writable bit
HS = Set by hardware
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
R = Readable bit
-n = Value at POR
‘1’ = Bit is set
bit 15
ADON: ADC Operating Mode bit
1= ADC module is operating
0= ADC module is off
bit 14
bit 13
Unimplemented: Read as ‘0’
ADSIDL: Stop in Idle Mode bit
1= Discontinue module operation when device enters Idle mode
0= Continue module operation in Idle mode
bit 12
ADDMABM: DMA Buffer Build Mode bit
1= DMA buffers are written in the order of conversion. The module will provide an address to the DMA
channel that is the same as the address used for the non-DMA stand-alone buffer
0= DMA buffers are written in Scatter/Gather mode. The module will provide a scatter/gather address
to the DMA channel, based on the index of the analog input and the size of the DMA buffer
bit 11
bit 10
Unimplemented: Read as ‘0’
AD12B: 10-Bit or 12-Bit Operation Mode bit
1= 12-bit, 1-channel ADC operation
0= 10-bit, 4-channel ADC operation
bit 9-8
FORM<1:0>: Data Output Format bits
For 10-bit operation:
11= Reserved
10= Reserved
01= Signed integer (DOUT = ssss sssd dddd dddd, where s= .NOT.d<9>)
00= Integer (DOUT = 0000 00dd dddd dddd)
For 12-bit operation:
11= Reserved
10= Reserved
01= Signed Integer (DOUT = ssss sddd dddd dddd, where s= .NOT.d<11>)
00= Integer (DOUT = 0000 dddd dddd dddd)
bit 7-5
SSRC<2:0>: Sample Clock Source Select bits
111= Internal counter ends sampling and starts conversion (auto-convert)
110= Reserved
101= Reserved
100= GP timer (Timer5 for ADC1, Timer3 for ADC2) compare ends sampling and starts conversion
011= Reserved
010= GP timer (Timer3 for ADC1, Timer5 for ADC2) compare ends sampling and starts conversion
001= Active transition on INT0 pin ends sampling and starts conversion
000= Clearing sample bit ends sampling and starts conversion
bit 4
Unimplemented: Read as ‘0’
DS70592A-page 208
Preliminary
© 2009 Microchip Technology Inc.
PIC24HJXXXGPX06A/X08A/X10A
REGISTER 20-1: ADxCON1: ADCx CONTROL REGISTER 1(where x = 1 or 2) (CONTINUED)
bit 3
SIMSAM: Simultaneous Sample Select bit (only applicable when CHPS<1:0> = 01or 1x)
When AD12B = 1, SIMSAM is: U-0, Unimplemented, Read as ‘0’
1= Samples CH0, CH1, CH2, CH3 simultaneously (when CHPS<1:0> = 1x); or
Samples CH0 and CH1 simultaneously (when CHPS<1:0> = 01)
0= Samples multiple channels individually in sequence
bit 2
bit 1
ASAM: ADC Sample Auto-Start bit
1= Sampling begins immediately after last conversion. SAMP bit is auto-set
0= Sampling begins when SAMP bit is set
SAMP: ADC Sample Enable bit
1= ADC sample/hold amplifiers are sampling
0= ADC sample/hold amplifiers are holding
If ASAM = 0, software may write ‘1’ to begin sampling. Automatically set by hardware if ASAM = 1.
If SSRC = 000, software may write ‘0’ to end sampling and start conversion. If SSRC ≠ 000,
automatically cleared by hardware to end sampling and start conversion.
bit 0
DONE: ADC Conversion Status bit
1= ADC conversion cycle is completed.
0= ADC conversion not started or in progress
Automatically set by hardware when analog-to-digital conversion is complete. Software may write ‘0’
to clear DONE status (software not allowed to write ‘1’). Clearing this bit will NOT affect any operation
in progress. Automatically cleared by hardware at start of a new conversion.
© 2009 Microchip Technology Inc.
Preliminary
DS70592A-page 209
PIC24HJXXXGPX06A/X08A/X10A
REGISTER 20-2: ADxCON2: ADCx CONTROL REGISTER 2 (where x = 1 or 2)
R/W-0
bit 15
R/W-0
R/W-0
U-0
—
U-0
—
R/W-0
R/W-0
R/W-0
VCFG<2:0>
CSCNA
CHPS<1:0>
bit 8
R-0
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
BUFM
R/W-0
ALTS
BUFS
SMPI<3:0>
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-13
VCFG<2:0>: Converter Voltage Reference Configuration bits
VREF+
VREF-
000
001
010
011
1xx
AVDD
External VREF+
AVDD
AVSS
AVSS
External VREF-
External VREF-
AVSS
External VREF+
AVDD
bit 12-11
bit 10
Unimplemented: Read as ‘0’
CSCNA: Scan Input Selections for CH0+ during Sample A bit
1= Scan inputs
0= Do not scan inputs
bit 9-8
bit 7
CHPS<1:0>: Selects Channels Utilized bits
When AD12B = 1, CHPS<1:0> is: U-0, Unimplemented, Read as ‘0’
1x= Converts CH0, CH1, CH2 and CH3
01= Converts CH0 and CH1
00= Converts CH0
BUFS: Buffer Fill Status bit (only valid when BUFM = 1)
1= ADC is currently filling second half of buffer, user should access data in first half
0= ADC is currently filling first half of buffer, user should access data in second half
bit 6
Unimplemented: Read as ‘0’
bit 5-2
SMPI<3:0>: Selects Increment Rate for DMA Addresses bits or number of sample/conversion
operations per interrupt
1111= Increments the DMA address or generates interrupt after completion of every 16th
sample/conversion operation
1110= Increments the DMA address or generates interrupt after completion of every 15th
sample/conversion operation
•
•
•
0001= Increments the DMA address or generates interrupt after completion of every 2nd
sample/conversion operation
0000= Increments the DMA address or generates interrupt after completion of every
sample/conversion operation
bit 1
bit 0
BUFM: Buffer Fill Mode Select bit
1= Starts filling first half of buffer on first interrupt and second half of buffer on next interrupt
0= Always starts filling buffer from the beginning
ALTS: Alternate Input Sample Mode Select bit
1= Uses channel input selects for Sample A on first sample and Sample B on next sample
0= Always uses channel input selects for Sample A
DS70592A-page 210
Preliminary
© 2009 Microchip Technology Inc.
PIC24HJXXXGPX06A/X08A/X10A
REGISTER 20-3: ADxCON3: ADCx CONTROL REGISTER 3
R/W-0
ADRC
U-0
—
U-0
—
R/W-0
R/W-0
R/W-0
SAMC<4:0>(1)
R/W-0
R/W-0
bit 8
R/W-0
bit 0
bit 15
R/W-0
bit 7
R/W-0
R/W-0
R/W-0
ADCS<7:0>(2)
R/W-0
R/W-0
R/W-0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15
ADRC: ADC Conversion Clock Source bit
1= ADC internal RC clock
0= Clock derived from system clock
bit 14-13
bit 12-8
Unimplemented: Read as ‘0’
SAMC<4:0>: Auto Sample Time bits(1)
11111= 31 TAD
•
•
•
00001= 1 TAD
00000= 0 TAD
bit 7-0
ADCS<7:0>: Analog-to-Digital Conversion Clock Select bits(2)
11111111= Reserved
•
•
•
01000000= Reserved
00111111= TCY ·(ADCS<7:0> + 1) = 64 ·TCY = TAD
•
•
•
00000010= TCY ·(ADCS<7:0> + 1) = 3 ·TCY = TAD
00000001= TCY ·(ADCS<7:0> + 1) = 2 ·TCY = TAD
00000000= TCY ·(ADCS<7:0> + 1) = 1 ·TCY = TAD
Note 1: This bit only used if ADxCON1<SSRC> = 1.
2: This bit is not used if ADxCON3<ADRC> = 1.
© 2009 Microchip Technology Inc.
Preliminary
DS70592A-page 211
PIC24HJXXXGPX06A/X08A/X10A
REGISTER 20-4: ADxCON4: ADCx CONTROL REGISTER 4
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
bit 15
bit 8
R/W-0
bit 0
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
R/W-0
R/W-0
DMABL<2:0>
bit 7
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-3
bit 2-0
Unimplemented: Read as ‘0’
DMABL<2:0>: Selects Number of DMA Buffer Locations per Analog Input bits
111= Allocates 128 words of buffer to each analog input
110= Allocates 64 words of buffer to each analog input
101= Allocates 32 words of buffer to each analog input
100= Allocates 16 words of buffer to each analog input
011= Allocates 8 words of buffer to each analog input
010= Allocates 4 words of buffer to each analog input
001= Allocates 2 words of buffer to each analog input
000= Allocates 1 word of buffer to each analog input
DS70592A-page 212
Preliminary
© 2009 Microchip Technology Inc.
PIC24HJXXXGPX06A/X08A/X10A
REGISTER 20-5: ADxCHS123: ADCx INPUT CHANNEL 1, 2, 3 SELECT REGISTER
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
R/W-0
R/W-0
R/W-0
CH123NB<1:0>
CH123SB
bit 15
bit 8
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
R/W-0
R/W-0
R/W-0
CH123NA<1:0>
CH123SA
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-11
bit 10-9
Unimplemented: Read as ‘0’
CH123NB<1:0>: Channel 1, 2, 3 Negative Input Select for Sample B bits
When AD12B = 1, CHxNB is: U-0, Unimplemented, Read as ‘0’
11= CH1 negative input is AN9, CH2 negative input is AN10, CH3 negative input is AN11
10= CH1 negative input is AN6, CH2 negative input is AN7, CH3 negative input is AN8
0x= CH1, CH2, CH3 negative input is VREF-
bit 8
CH123SB: Channel 1, 2, 3 Positive Input Select for Sample B bit
When AD12B = 1, CHxSB is: U-0, Unimplemented, Read as ‘0’
1= CH1 positive input is AN3, CH2 positive input is AN4, CH3 positive input is AN5
0= CH1 positive input is AN0, CH2 positive input is AN1, CH3 positive input is AN2
bit 7-3
bit 2-1
Unimplemented: Read as ‘0’
CH123NA<1:0>: Channel 1, 2, 3 Negative Input Select for Sample A bits
When AD12B = 1, CHxNA is: U-0, Unimplemented, Read as ‘0’
11= CH1 negative input is AN9, CH2 negative input is AN10, CH3 negative input is AN11
10= CH1 negative input is AN6, CH2 negative input is AN7, CH3 negative input is AN8
0x= CH1, CH2, CH3 negative input is VREF-
bit 0
CH123SA: Channel 1, 2, 3 Positive Input Select for Sample A bit
When AD12B = 1, CHxSA is: U-0, Unimplemented, Read as ‘0’
1= CH1 positive input is AN3, CH2 positive input is AN4, CH3 positive input is AN5
0= CH1 positive input is AN0, CH2 positive input is AN1, CH3 positive input is AN2
© 2009 Microchip Technology Inc.
Preliminary
DS70592A-page 213
PIC24HJXXXGPX06A/X08A/X10A
REGISTER 20-6: ADxCHS0: ADCx INPUT CHANNEL 0 SELECT REGISTER
R/W-0
U-0
—
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
bit 8
R/W-0
bit 0
CH0NB
CH0SB<4:0>
bit 15
R/W-0
U-0
—
U-0
—
R/W-0
R/W-0
R/W-0
CH0NA
CH0SA<4:0>
bit 7
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15
CH0NB: Channel 0 Negative Input Select for Sample B bit
Same definition as bit 7.
bit 14-13
bit 12-8
Unimplemented: Read as ‘0’
CH0SB<4:0>: Channel 0 Positive Input Select for Sample B bits
Same definition as bit<4:0>.
bit 7
CH0NA: Channel 0 Negative Input Select for Sample A bit
1= Channel 0 negative input is AN1
0= Channel 0 negative input is VREF-
bit 6-5
bit 4-0
Unimplemented: Read as ‘0’
CH0SA<4:0>: Channel 0 Positive Input Select for Sample A bits
11111= Channel 0 positive input is AN31
11110= Channel 0 positive input is AN30
•
•
•
00010= Channel 0 positive input is AN2
00001= Channel 0 positive input is AN1
00000= Channel 0 positive input is AN0
Note:
ADC2 can only select AN0 through AN15 as positive inputs.
DS70592A-page 214
Preliminary
© 2009 Microchip Technology Inc.
PIC24HJXXXGPX06A/X08A/X10A
(1,2)
REGISTER 20-7: ADxCSSH: ADCx INPUT SCAN SELECT REGISTER HIGH
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
CSS31
CSS30
CSS29
CSS28
CSS27
CSS26
CSS25
CSS24
bit 15
bit 8
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
CSS23
CSS22
CSS21
CSS20
CSS19
CSS18
CSS17
CSS16
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-0
CSS<31:16>: ADC Input Scan Selection bits
1= Select ANx for input scan
0= Skip ANx for input scan
Note 1: On devices without 32 analog inputs, all ADxCSSH bits may be selected by user. However, inputs selected
for scan without a corresponding input on device will convert VREFL.
2: CSSx = ANx, where x = 16 through 31.
(1,2)
REGISTER 20-8: ADxCSSL: ADCx INPUT SCAN SELECT REGISTER LOW
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
CSS9
R/W-0
CSS8
CSS15
CSS14
CSS13
CSS12
CSS11
CSS10
bit 15
bit 8
R/W-0
CSS7
R/W-0
CSS6
R/W-0
CSS5
R/W-0
CSS4
R/W-0
CSS3
R/W-0
CSS2
R/W-0
CSS1
R/W-0
CSS0
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-0
CSS<15:0>: ADC Input Scan Selection bits
1= Select ANx for input scan
0= Skip ANx for input scan
Note 1: On devices without 16 analog inputs, all ADxCSSL bits may be selected by user. However, inputs selected
for scan without a corresponding input on device will convert VREF-.
2: CSSx = ANx, where x = 0 through 15.
© 2009 Microchip Technology Inc.
Preliminary
DS70592A-page 215
PIC24HJXXXGPX06A/X08A/X10A
(1,2,3,4)
REGISTER 20-9: AD1PCFGH: ADC1 PORT CONFIGURATION REGISTER HIGH
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
PCFG31
PCFG30
PCFG29
PCFG28
PCFG27
PCFG26
PCFG25
PCFG24
bit 15
bit 8
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
PCFG23
PCFG22
PCFG21
PCFG20
PCFG19
PCFG18
PCFG17
PCFG16
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-0
PCFG<31:16>: ADC Port Configuration Control bits
1= Port pin in Digital mode, port read input enabled, ADC input multiplexor connected to AVSS
0= Port pin in Analog mode, port read input disabled, ADC samples pin voltage
Note 1: On devices without 32 analog inputs, all PCFG bits are R/W by user. However, PCFG bits are ignored on
ports without a corresponding input on device.
2: ADC2 only supports analog inputs AN0-AN15; therefore, no ADC2 high port Configuration register exists.
3: PCFGx = ANx, where x = 16 through 31.
4: PCFGx bits will have no effect if ADC module is disabled by setting ADxMD bit in the PMDx register. In
this case all port pins multiplexed with ANx will be in Digital mode.
(1,2,3,4)
REGISTER 20-10: ADxPCFGL: ADCx PORT CONFIGURATION REGISTER LOW
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
PCFG15
PCFG14
PCFG13
PCFG12
PCFG11
PCFG10
PCFG9
PCFG8
bit 15
bit 8
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
PCFG7
PCFG6
PCFG5
PCFG4
PCFG3
PCFG2
PCFG1
PCFG0
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-0
PCFG<15:0>: ADC Port Configuration Control bits
1= Port pin in Digital mode, port read input enabled, ADC input multiplexor connected to AVSS
0= Port pin in Analog mode, port read input disabled, ADC samples pin voltage
Note 1: On devices without 16 analog inputs, all PCFG bits are R/W by user. However, PCFG bits are ignored on
ports without a corresponding input on device.
2: On devices with 2 analog-to-digital modules, both AD1PCFGL and AD2PCFGL will affect the configuration
of port pins multiplexed with AN0-AN15.
3: PCFGx = ANx, where x = 0 through 15.
4: PCFGx bits will have no effect if ADC module is disabled by setting ADxMD bit in the PMDx register. In
this case all port pins multiplexed with ANx will be in Digital mode.
DS70592A-page 216
Preliminary
© 2009 Microchip Technology Inc.
PIC24HJXXXGPX06A/X08A/X10A
21.1 Configuration Bits
21.0 SPECIAL FEATURES
The Configuration bits can be programmed (read as
‘0’), or left unprogrammed (read as ‘1’), to select vari-
ous device configurations. These bits are mapped
starting at program memory location 0xF80000.
Note:
This data sheet summarizes the features
of the PIC24HJXXXGPX06A/X08A/X10A
families of devices. However, it is not
intended to be a comprehensive reference
source. To complement the information in
this data sheet, refer to Section 23.
“CodeGuard™ Security” (DS70239),
Section 24. “Programming and Diag-
nostics” (DS70246), and Section 25.
“Device Configuration” (DS70231) in
the “PIC24H Family Reference Manual”,
which is available from the Microchip web
site (www.microchip.com).
The device Configuration register map is shown in
Table 21-1.
The individual Configuration bit descriptions for the
FBS, FSS, FGS, FOSCSEL, FOSC, FWDT and FPOR
Configuration registers are shown in Table 21-2.
Note that address 0xF80000 is beyond the user program
memory space. In fact, it belongs to the configuration
memory space (0x800000-0xFFFFFF), which can only
be accessed using table reads and table writes.
PIC24HJXXXGPX06A/X08A/X10A devices include
several features intended to maximize application flex-
ibility and reliability, and minimize cost through elimina-
tion of external components. These are:
The upper byte of all device Configuration registers
should always be ‘1111 1111’. This makes them
appear to be NOPinstructions in the remote event that
their locations are ever executed by accident. Since
Configuration bits are not implemented in the
corresponding locations, writing ‘1’s to these locations
has no effect on device operation.
• Flexible Configuration
• Watchdog Timer (WDT)
• Code Protection and CodeGuard™ Security
• JTAG Boundary Scan Interface
To prevent inadvertent configuration changes during
code execution, all programmable Configuration bits
are write-once. After a bit is initially programmed during
a power cycle, it cannot be written to again. Changing
a device configuration requires that power to the device
be cycled.
• In-Circuit Serial Programming™ (ICSP™)
programming capability
• In-Circuit Emulation
TABLE 21-1: DEVICE CONFIGURATION REGISTER MAP
Address
Name
Bit 7
RBS<1:0>
RSS<1:0>
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
—
—
—
BSS<2:0>
SSS<2:0>
BWRP
SWRP
GWRP
0xF80000 FBS
0xF80002 FSS
—
0xF80004 FGS
0xF80006 FOSCSEL
0xF80008 FOSC
0xF8000A FWDT
0xF8000C FPOR
0xF8000E FICD
0xF80010 FUID0
0xF80012 FUID1
0xF80014 FUID2
0xF80016 FUID3
—
—
—
—
—
—
—
GSS<1:0>
FNOSC<2:0>
IESO
Reserved(2)
—
—
FCKSM<1:0>
—
—
WDTPRE
—
OSCIOFNC POSCMD<1:0>
WDTPOST<3:0>
FWDTEN
WINDIS
PLLKEN
—
—
—
—
—
FPWRT<2:0>
Reserved(1)
JTAGEN
—
—
ICS<1:0>
User Unit ID Byte 0
User Unit ID Byte 1
User Unit ID Byte 2
User Unit ID Byte 3
Note 1: When read, these bits will appear as ‘1’. When you write to these bits, set these bits to ‘1’.
2: When read, this bit returns the current programmed value.
© 2009 Microchip Technology Inc.
Preliminary
DS70592A-page 217
PIC24HJXXXGPX06A/X08A/X10A
TABLE 21-2: PIC24HJXXXGPX06A/X08A/X10A CONFIGURATION BITS DESCRIPTION
Bit Field
Register
Description
BWRP
FBS
Boot Segment Program Flash Write Protection
1= Boot segment may be written
0= Boot segment is write-protected
BSS<2:0>
FBS
Boot Segment Program Flash Code Protection Size
X11= No Boot program Flash segment
Boot space is 1K IW less VS
110= Standard security; boot program Flash segment starts at End of VS,
ends at 0x0007FE
010= High security; boot program Flash segment starts at End of VS, ends at
0x0007FE
Boot space is 4K IW less VS
101= Standard security; boot program Flash segment starts at End of VS,
ends at 0x001FFE
001= High security; boot program Flash segment starts at End of VS, ends at
0x001FFE
Boot space is 8K IW less VS
100= Standard security; boot program Flash segment starts at End of VS,
ends at 0x003FFE
000= High security; boot program Flash segment starts at End of VS, ends at
0x003FFE
RBS<1:0>
SWRP
FBS
FSS
Boot Segment RAM Code Protection
11= No Boot RAM defined
10= Boot RAM is 128 Bytes
01= Boot RAM is 256 Bytes
00 = Boot RAM is 1024 Bytes
Secure Segment Program Flash Write Protection
1= Secure segment may be written
0= Secure segment is write-protected
DS70592A-page 218
Preliminary
© 2009 Microchip Technology Inc.
PIC24HJXXXGPX06A/X08A/X10A
TABLE 21-2: PIC24HJXXXGPX06A/X08A/X10A CONFIGURATION BITS DESCRIPTION (CONTINUED)
Bit Field
Register
Description
SSS<2:0>
FSS
Secure Segment Program Flash Code Protection Size
(FOR 128K and 256K DEVICES)
X11= No Secure program Flash segment
Secure space is 8K IW less BS
110= Standard security; secure program Flash segment starts at End of BS,
ends at 0x003FFE
010= High security; secure program Flash segment starts at End of BS, ends
at 0x003FFE
Secure space is 16K IW less BS
101= Standard security; secure program Flash segment starts at End of BS,
ends at 0x007FFE
001= High security; secure program Flash segment starts at End of BS, ends
at 0x007FFE
Secure space is 32K IW less BS
100= Standard security; secure program Flash segment starts at End of BS,
ends at 0x00FFFE
000= High security; secure program Flash segment starts at End of BS, ends
at 0x00FFFE
(FOR 64K DEVICES)
X11= No Secure program Flash segment
Secure space is 4K IW less BS
110= Standard security; secure program Flash segment starts at End of BS,
ends at 0x001FFE
010= High security; secure program Flash segment starts at End of BS, ends
at 0x001FFE
Secure space is 8K IW less BS
101= Standard security; secure program Flash segment starts at End of BS,
ends at 0x003FFE
001= High security; secure program Flash segment starts at End of BS, ends
at 0x003FFE
Secure space is 16K IW less BS
100= Standard security; secure program Flash segment starts at End of BS,
ends at 0x007FFE
000= High security; secure program Flash segment starts at End of BS, ends
at 0x007FFE
RSS<1:0>
GSS<1:0>
FSS
FGS
Secure Segment RAM Code Protection
11= No Secure RAM defined
10= Secure RAM is 256 Bytes less BS RAM
01= Secure RAM is 2048 Bytes less BS RAM
00= Secure RAM is 4096 Bytes less BS RAM
General Segment Code-Protect bit
11= User program memory is not code-protected
10= Standard Security; general program Flash segment starts at End of SS,
ends at EOM
0x= High Security; general program Flash segment starts at End of ESS, ends
at EOM
GWRP
FGS
General Segment Write-Protect bit
1= User program memory is not write-protected
0= User program memory is write-protected
© 2009 Microchip Technology Inc.
Preliminary
DS70592A-page 219
PIC24HJXXXGPX06A/X08A/X10A
TABLE 21-2: PIC24HJXXXGPX06A/X08A/X10A CONFIGURATION BITS DESCRIPTION (CONTINUED)
Bit Field
Register
Description
IESO
FOSCSEL
Internal External Start-up Option bit
1= Start-up device with FRC, then automatically switch to the user-selected
oscillator source when ready
0= Start-up device with user-selected oscillator source
FNOSC<2:0>
FOSCSEL
Initial Oscillator Source Selection bits
111= Internal Fast RC (FRC) oscillator with postscaler
110= Reserved
101= LPRC oscillator
100= Secondary (LP) oscillator
011= Primary (XT, HS, EC) oscillator with PLL
010= Primary (XT, HS, EC) oscillator
001= Internal Fast RC (FRC) oscillator with PLL
000= FRC oscillator
FCKSM<1:0>
FOSC
Clock Switching Mode bits
1x= Clock switching is disabled, Fail-Safe Clock Monitor is disabled
01= Clock switching is enabled, Fail-Safe Clock Monitor is disabled
00= Clock switching is enabled, Fail-Safe Clock Monitor is enabled
OSCIOFNC
FOSC
FOSC
OSC2 Pin Function bit (except in XT and HS modes)
1= OSC2 is clock output
0= OSC2 is general purpose digital I/O pin
POSCMD<1:0>
Primary Oscillator Mode Select bits
11= Primary oscillator disabled
10= HS Crystal Oscillator mode
01= XT Crystal Oscillator mode
00= EC (External Clock) mode
FWDTEN
FWDT
Watchdog Timer Enable bit
1= Watchdog Timer always enabled (LPRC oscillator cannot be disabled. Clearing
the SWDTEN bit in the RCON register will have no effect.)
0= Watchdog Timer enabled/disabled by user software (LPRC can be disabled
by clearing the SWDTEN bit in the RCON register)
WINDIS
PLLKEN
FWDT
FWDT
FWDT
FWDT
Watchdog Timer Window Enable bit
1= Watchdog Timer in Non-Window mode
0= Watchdog Timer in Window mode
PLL Lock Enable bit
1= Clock switch to PLL source will wait until the PLL lock signal is valid.
0= Clock switch will not wait for the PLL lock signal.
WDTPRE
WDTPOST
Watchdog Timer Prescaler bit
1= 1:128
0= 1:32
Watchdog Timer Postscaler bits
1111= 1:32,768
1110= 1:16,384
.
.
.
0001= 1:2
0000= 1:1
DS70592A-page 220
Preliminary
© 2009 Microchip Technology Inc.
PIC24HJXXXGPX06A/X08A/X10A
TABLE 21-2: PIC24HJXXXGPX06A/X08A/X10A CONFIGURATION BITS DESCRIPTION (CONTINUED)
Bit Field
Register
Description
FPWRT<2:0>
FPOR
Power-on Reset Timer Value Select bits
111= PWRT = 128 ms
110= PWRT = 64 ms
101= PWRT = 32 ms
100= PWRT = 16 ms
011= PWRT = 8 ms
010= PWRT = 4 ms
001= PWRT = 2 ms
000= PWRT = Disabled
JTAGEN
ICS<1:0>
FICD
FICD
JTAG Enable bits
1= JTAG enabled
0= JTAG disabled
ICD Communication Channel Select bits
11= Communicate on PGEC1 and PGED1
10= Communicate on PGEC2 and PGED2
01= Communicate on PGEC3 and PGED3
00= Reserved
© 2009 Microchip Technology Inc.
Preliminary
DS70592A-page 221
PIC24HJXXXGPX06A/X08A/X10A
21.2 On-Chip Voltage Regulator
21.3 BOR: Brown-out Reset
All of the PIC24HJXXXGPX06A/X08A/X10A devices
power their core digital logic at a nominal 2.5V. This
may create an issue for designs that are required to
operate at a higher typical voltage, such as 3.3V. To
simplify system design, all devices in the
PIC24HJXXXGPX06A/X08A/X10A family incorporate
an on-chip regulator that allows the device to run its
core logic from VDD.
The BOR (Brown-out Reset) module is based on an
internal voltage reference circuit that monitors the reg-
ulated voltage VCAP/VDDCORE. The main purpose of
the BOR module is to generate a device Reset when a
brown-out condition occurs. Brown-out conditions are
generally caused by glitches on the AC mains (i.e.,
missing portions of the AC cycle waveform due to bad
power transmission lines or voltage sags due to exces-
sive current draw when a large inductive load is turned
on).
The regulator provides power to the core from the other
VDD pins. The regulator requires that a low-ESR (less
than 5 ohms) capacitor (such as tantalum or ceramic)
be connected to the VCAP/VDDCORE pin (Figure 21-1).
This helps to maintain the stability of the regulator. The
recommended value for the filter capacitor is provided
in Table 24-13 of Section 24.1 “DC Characteristics”.
A BOR will generate a Reset pulse which will reset the
device. The BOR will select the clock source, based on
the device Configuration bit values (FNOSC<2:0> and
POSCMD<1:0>). Furthermore, if an oscillator mode is
selected, the BOR will activate the Oscillator Start-up
Timer (OST). The system clock is held until OST
expires. If the PLL is used, then the clock will be held
until the LOCK bit (OSCCON<5>) is ‘1’.
Note:
It is important for the low-ESR capacitor to
be placed as close as possible to the
VCAP/VDDCORE pin.
Concurrently, the PWRT time-out (TPWRT) will be
applied before the internal Reset is released. If
TPWRT = 0and a crystal oscillator is being used, then
a nominal delay of TFSCM = 100 is applied. The total
delay in this case is TFSCM.
On a POR, it takes approximately 20 μs for the on-chip
voltage regulator to generate an output voltage. During
this time, designated as TSTARTUP, code execution is
disabled. TSTARTUP is applied every time the device
resumes operation after any power-down.
The BOR Status bit (RCON<1>) will be set to indicate
that a BOR has occurred. The BOR circuit continues to
operate while in Sleep or Idle modes and will reset the
device should VDD fall below the BOR threshold volt-
age.
FIGURE 21-1:
ON-CHIP VOLTAGE
REGULATOR
CONNECTIONS
(1)
3.3V
PIC24H
VDD
VCAP/VDDCORE
VSS
CEFC
Note 1: These are typical operating voltages. Refer to
TABLE 24-13: “Internal Voltage Regulator
Specifications” located in Section 24.1 “DC
Characteristics” for the full operating ranges
of VDD and VCAP/VDDCORE.
2: It is important for the low-ESR capacitor to
be placed as close as possible to the
VCAP/VDDCORE pin.
DS70592A-page 222
Preliminary
© 2009 Microchip Technology Inc.
PIC24HJXXXGPX06A/X08A/X10A
If the WDT is enabled, it will continue to run during
21.4 Watchdog Timer (WDT)
Sleep or Idle modes. When the WDT time-out occurs,
the device will wake the device and code execution will
continue from where the PWRSAVinstruction was exe-
cuted. The corresponding SLEEP or IDLE bits
(RCON<3,2>) will need to be cleared in software after
the device wakes up.
For PIC24HJXXXGPX06A/X08A/X10A devices, the
WDT is driven by the LPRC oscillator. When the WDT
is enabled, the clock source is also enabled.
The nominal WDT clock source from LPRC is 32 kHz.
This feeds a prescaler than can be configured for either
5-bit (divide-by-32) or 7-bit (divide-by-128) operation.
The prescaler is set by the WDTPRE Configuration bit.
With a 32 kHz input, the prescaler yields a nominal
WDT time-out period (TWDT) of 1 ms in 5-bit mode, or
4 ms in 7-bit mode.
The WDT flag bit, WDTO (RCON<4>), is not automatically
cleared following a WDT time-out. To detect subsequent
WDT events, the flag must be cleared in software.
Note:
The CLRWDT and PWRSAV instructions
clear the prescaler and postscaler counts
when executed.
A variable postscaler divides down the WDT prescaler
output and allows for a wide range of time-out periods.
The postscaler is controlled by the WDTPOST<3:0>
Configuration bits (FWDT<3:0>) which allow the selec-
tion of a total of 16 settings, from 1:1 to 1:32,768. Using
the prescaler and postscaler, time-out periods ranging
from 1 ms to 131 seconds can be achieved.
The WDT is enabled or disabled by the FWDTEN
Configuration bit in the FWDT Configuration register.
When the FWDTEN Configuration bit is set, the WDT is
always enabled.
The WDT can be optionally controlled in software when
the FWDTEN Configuration bit has been programmed
to ‘0’. The WDT is enabled in software by setting the
SWDTEN control bit (RCON<5>). The SWDTEN con-
trol bit is cleared on any device Reset. The software
WDT option allows the user to enable the WDT for crit-
ical code segments and disable the WDT during
non-critical segments for maximum power savings.
The WDT, prescaler and postscaler are reset:
• On any device Reset
• On the completion of a clock switch, whether
invoked by software (i.e., setting the OSWEN bit
after changing the NOSC bits) or by hardware
(i.e., Fail-Safe Clock Monitor)
• When a PWRSAVinstruction is executed
(i.e., Sleep or Idle mode is entered)
Note:
If the WINDIS bit (FWDT<6>) is cleared, the
CLRWDTinstruction should be executed by
the application software only during the last
1/4 of the WDT period. This CLRWDT win-
dow can be determined by using a timer. If
a CLRWDT instruction is executed before
this window, a WDT Reset occurs.
• When the device exits Sleep or Idle mode to
resume normal operation
• By a CLRWDTinstruction during normal execution
FIGURE 21-2:
WDT BLOCK DIAGRAM
All Device Resets
Transition to New Clock Source
Exit Sleep or Idle Mode
PWRSAVInstruction
CLRWDTInstruction
Watchdog Timer
Sleep/Idle
WDTPRE
Prescaler
WDTPOST<3:0>
SWDTEN
FWDTEN
WDT
Wake-up
1
0
RS
RS
Postscaler
WDT
Reset
(divide by N1)
(divide by N2)
LPRC Clock
WDT Window Select
WINDIS
CLRWDTInstruction
© 2009 Microchip Technology Inc.
Preliminary
DS70592A-page 223
PIC24HJXXXGPX06A/X08A/X10A
21.5 JTAG Interface
21.7 In-Circuit Serial Programming
Programming Capability
PIC24HJXXXGPX06A/X08A/X10A devices implement
a JTAG interface, which supports boundary scan
device testing, as well as in-circuit programming.
Detailed information on the interface will be provided in
future revisions of the document.
PIC24HJXXXGPX06A/X08A/X10A family digital signal
controllers can be serially programmed while in the end
application circuit. This is simply done with two lines for
clock and data and three other lines for power, ground
and the programming sequence. This allows custom-
ers to manufacture boards with unprogrammed
devices and then program the digital signal controller
just before shipping the product. This also allows the
most recent firmware or a custom firmware, to be pro-
grammed. Please refer to the “dsPIC33F/PIC24H
Note:
For further information, refer to the
PIC24H Family Reference Manual“,
Section
24.
“Programming
and
Diagnostics” (DS70246), which is
available from the Microchip website
(www.microchip.com).
Flash
Programming
Specification”
(DS70152)
document for details about ICSP programming
capability.
21.6 Code Protection and
CodeGuard™ Security
Any one out of three pairs of programming clock/data
pins may be used:
The PIC24H product families offer advanced imple-
mentation of CodeGuard™ Security. CodeGuard
Security enables multiple parties to securely share
resources (memory, interrupts and peripherals) on a
single chip. This feature helps protect individual
Intellectual Property in collaborative system designs.
• PGEC1 and PGED1
• PGEC2 and PGED2
• PGEC3 and PGED3
21.8 In-Circuit Debugger
When coupled with software encryption libraries,
CodeGuard Security can be used to securely update
Flash even when multiple IP are resident on the single
chip. The code protection features vary depending on
the actual PIC24H implemented. The following
sections provide an overview these features.
When MPLAB® ICD 2 is selected as a debugger, the
in-circuit debugging functionality is enabled. This func-
tion allows simple debugging functions when used with
MPLAB IDE. Debugging functionality is controlled
through the PGECx (Emulation/Debug Clock) and
PGEDx (Emulation/Debug Data) pin functions.
The code protection features are controlled by the
Configuration registers: FBS, FSS and FGS.
Any one out of three pairs of debugging clock/data pins
may be used:
Note:
For further information, refer to the
“PIC24H Family Reference Manual”, Sec-
tion 23. “CodeGuard™ Security”
(DS70239), which is available from the
Microchip website (www.microchip.com).
• PGEC1 and PGED1
• PGEC2 and PGED2
• PGEC3 and PGED3
To use the in-circuit debugger function of the device,
the design must implement ICSP programming capa-
bility connections to MCLR, VDD, VSS and the
PGEDx/PGECx pin pair. In addition, when the feature
is enabled, some of the resources are not available for
general use. These resources include the first 80 bytes
of data RAM and two I/O pins.
DS70592A-page 224
Preliminary
© 2009 Microchip Technology Inc.
PIC24HJXXXGPX06A/X08A/X10A
Most bit-oriented instructions (including simple
rotate/shift instructions) have two operands:
22.0 INSTRUCTION SET SUMMARY
Note:
This data sheet summarizes the features
of the PIC24HJXXXGPX06A/X08A/X10A
families of devices. However, it is not
intended to be a comprehensive reference
source. To complement the information in
this data sheet, refer to the related section
in the “PIC24H Family Reference Manual”,
which is available from the Microchip
website (www.microchip.com).
• The W register (with or without an address
modifier) or file register (specified by the value of
‘Ws’ or ‘f’)
• The bit in the W register or file register
(specified by a literal value or indirectly by the
contents of register ‘Wb’)
The literal instructions that involve data movement may
use some of the following operands:
• A literal value to be loaded into a W register or file
register (specified by the value of ‘k’)
The PIC24H instruction set is identical to that of the
PIC24F, and is a subset of the dsPIC30F/33F
instruction set.
• The W register or file register where the literal
value is to be loaded (specified by ‘Wb’ or ‘f’)
Most instructions are a single program memory word
(24 bits). Only three instructions require two program
memory locations.
However, literal instructions that involve arithmetic or
logical operations use some of the following operands:
• The first source operand which is a register ‘Wb’
without any address modifier
Each single-word instruction is a 24-bit word, divided
into an 8-bit opcode, which specifies the instruction
type and one or more operands, which further specify
the operation of the instruction.
• The second source operand which is a literal
value
• The destination of the result (only if not the same
as the first source operand) which is typically a
register ‘Wd’ with or without an address modifier
The instruction set is highly orthogonal and is grouped
into five basic categories:
• Word or byte-oriented operations
• Bit-oriented operations
• Literal operations
The control instructions may use some of the following
operands:
• A program memory address
• DSP operations
• The mode of the table read and table write
instructions
• Control operations
Table 22-1 shows the general symbols used in
describing the instructions.
All instructions are a single word, except for certain
double word instructions, which were made double
word instructions so that all the required information is
available in these 48 bits. In the second word, the
8 MSbs are ‘0’s. If this second word is executed as an
instruction (by itself), it will execute as a NOP.
The PIC24H instruction set summary in Table 22-2 lists
all the instructions, along with the status flags affected
by each instruction.
Most word or byte-oriented W register instructions
(including barrel shift instructions) have three
operands:
Most single-word instructions are executed in a single
instruction cycle, unless a conditional test is true, or the
program counter is changed as a result of the instruc-
tion. In these cases, the execution takes two instruction
cycles with the additional instruction cycle(s) executed
as a NOP. Notable exceptions are the BRA (uncondi-
tional/computed branch), indirect CALL/GOTO, all table
reads and writes and RETURN/RETFIE instructions,
which are single-word instructions but take two or three
cycles. Certain instructions that involve skipping over the
subsequent instruction require either two or three cycles
if the skip is performed, depending on whether the
instruction being skipped is a single-word or double word
instruction. Moreover, double word moves require two
cycles. The double word instructions execute in two
instruction cycles.
• The first source operand which is typically a
register ‘Wb’ without any address modifier
• The second source operand which is typically a
register ‘Ws’ with or without an address modifier
• The destination of the result which is typically a
register ‘Wd’ with or without an address modifier
However, word or byte-oriented file register instructions
have two operands:
• The file register specified by the value ‘f’
• The destination, which could either be the file
register ‘f’ or the W0 register, which is denoted as
‘WREG’
Note:
For more details on the instruction set,
refer to the “dsPIC30F/33F Programmer’s
Reference Manual” (DS70157).
© 2009 Microchip Technology Inc.
Preliminary
DS70592A-page 225
PIC24HJXXXGPX06A/X08A/X10A
TABLE 22-1: SYMBOLS USED IN OPCODE DESCRIPTIONS
Field
Description
#text
(text)
[text]
{ }
Means literal defined by “text”
Means “content of text”
Means “the location addressed by text”
Optional field or operation
Register bit field
<n:m>
.b
Byte mode selection
.d
Double Word mode selection
Shadow register select
.S
.w
Word mode selection (default)
bit4
4-bit bit selection field (used in word addressed instructions) ∈ {0...15}
MCU Status bits: Carry, Digit Carry, Negative, Overflow, Sticky Zero
Absolute address, label or expression (resolved by the linker)
File register address ∈ {0x0000...0x1FFF}
1-bit unsigned literal ∈ {0,1}
C, DC, N, OV, Z
Expr
f
lit1
lit4
4-bit unsigned literal ∈ {0...15}
lit5
5-bit unsigned literal ∈ {0...31}
lit8
8-bit unsigned literal ∈ {0...255}
lit10
lit14
lit16
lit23
None
PC
10-bit unsigned literal ∈ {0...255} for Byte mode, {0:1023} for Word mode
14-bit unsigned literal ∈ {0...16384}
16-bit unsigned literal ∈ {0...65535}
23-bit unsigned literal ∈ {0...8388608}; LSB must be ‘0’
Field does not require an entry, may be blank
Program Counter
Slit10
Slit16
Slit6
Wb
10-bit signed literal ∈ {-512...511}
16-bit signed literal ∈ {-32768...32767}
6-bit signed literal ∈ {-16...16}
Base W register ∈ {W0..W15}
Wd
Destination W register ∈ { Wd, [Wd], [Wd++], [Wd--], [++Wd], [--Wd] }
Wdo
Destination W register ∈
{ Wnd, [Wnd], [Wnd++], [Wnd--], [++Wnd], [--Wnd], [Wnd+Wb] }
Wm,Wn
Dividend, Divisor working register pair (direct addressing)
Wm*Wm
Multiplicand and Multiplier working register pair for Square instructions ∈
{W4 * W4,W5 * W5,W6 * W6,W7 * W7}
Wm*Wn
Multiplicand and Multiplier working register pair for DSP instructions ∈
{W4 * W5,W4 * W6,W4 * W7,W5 * W6,W5 * W7,W6 * W7}
Wn
One of 16 working registers ∈ {W0..W15}
Wnd
Wns
WREG
Ws
One of 16 destination working registers ∈ {W0...W15}
One of 16 source working registers ∈ {W0...W15}
W0 (working register used in file register instructions)
Source W register ∈ { Ws, [Ws], [Ws++], [Ws--], [++Ws], [--Ws] }
Wso
Source W register ∈
{ Wns, [Wns], [Wns++], [Wns--], [++Wns], [--Wns], [Wns+Wb] }
DS70592A-page 226
Preliminary
© 2009 Microchip Technology Inc.
PIC24HJXXXGPX06A/X08A/X10A
TABLE 22-2: INSTRUCTION SET OVERVIEW
Base
Instr
#
Assembly
Mnemonic
# of
# of
Status Flags
Affected
Assembly Syntax
Description
Words Cycles
ADD
f
f = f + WREG
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
C,DC,N,OV,Z
C,DC,N,OV,Z
C,DC,N,OV,Z
C,DC,N,OV,Z
C,DC,N,OV,Z
C,DC,N,OV,Z
C,DC,N,OV,Z
C,DC,N,OV,Z
C,DC,N,OV,Z
C,DC,N,OV,Z
N,Z
1
ADD
ADDC
AND
ASR
ADD
f,WREG
WREG = f + WREG
1
ADD
#lit10,Wn
Wb,Ws,Wd
Wb,#lit5,Wd
f
Wd = lit10 + Wd
1
ADD
Wd = Wb + Ws
1
ADD
Wd = Wb + lit5
1
1
2
3
4
ADDC
ADDC
ADDC
ADDC
ADDC
AND
f = f + WREG + (C)
f,WREG
WREG = f + WREG + (C)
Wd = lit10 + Wd + (C)
Wd = Wb + Ws + (C)
Wd = Wb + lit5 + (C)
f = f .AND. WREG
1
#lit10,Wn
Wb,Ws,Wd
Wb,#lit5,Wd
f
1
1
1
1
AND
f,WREG
WREG = f .AND. WREG
Wd = lit10 .AND. Wd
Wd = Wb .AND. Ws
Wd = Wb .AND. lit5
1
N,Z
AND
#lit10,Wn
Wb,Ws,Wd
Wb,#lit5,Wd
f
1
N,Z
AND
1
N,Z
AND
1
N,Z
ASR
f = Arithmetic Right Shift f
WREG = Arithmetic Right Shift f
Wd = Arithmetic Right Shift Ws
Wnd = Arithmetic Right Shift Wb by Wns
Wnd = Arithmetic Right Shift Wb by lit5
Bit Clear f
1
C,N,OV,Z
C,N,OV,Z
C,N,OV,Z
N,Z
ASR
f,WREG
1
ASR
Ws,Wd
1
ASR
Wb,Wns,Wnd
Wb,#lit5,Wnd
f,#bit4
Ws,#bit4
C,Expr
1
ASR
1
N,Z
5
6
BCLR
BRA
BCLR
BCLR
BRA
1
None
Bit Clear Ws
1
None
Branch if Carry
1 (2)
1 (2)
1 (2)
1 (2)
1 (2)
1 (2)
1 (2)
1 (2)
1 (2)
1 (2)
1 (2)
1 (2)
1 (2)
2
None
BRA
GE,Expr
GEU,Expr
GT,Expr
GTU,Expr
LE,Expr
LEU,Expr
LT,Expr
LTU,Expr
N,Expr
Branch if greater than or equal
Branch if unsigned greater than or equal
Branch if greater than
Branch if unsigned greater than
Branch if less than or equal
Branch if unsigned less than or equal
Branch if less than
None
BRA
None
BRA
None
BRA
None
BRA
None
BRA
None
BRA
None
BRA
Branch if unsigned less than
Branch if Negative
None
BRA
None
BRA
NC,Expr
NN,Expr
NZ,Expr
Expr
Branch if Not Carry
None
BRA
Branch if Not Negative
Branch if Not Zero
None
BRA
None
BRA
Branch Unconditionally
Branch if Zero
None
BRA
Z,Expr
1 (2)
2
None
BRA
Wn
Computed Branch
None
7
BSET
BSW
BSET
BSET
BSW.C
BSW.Z
BTG
f,#bit4
Ws,#bit4
Ws,Wb
Bit Set f
1
None
Bit Set Ws
1
None
8
Write C bit to Ws<Wb>
Write Z bit to Ws<Wb>
Bit Toggle f
1
None
Ws,Wb
1
None
9
BTG
f,#bit4
Ws,#bit4
f,#bit4
1
None
BTG
Bit Toggle Ws
1
None
10
BTSC
BTSC
Bit Test f, Skip if Clear
1
None
(2 or 3)
BTSC
BTSS
BTSS
Ws,#bit4
f,#bit4
Ws,#bit4
Bit Test Ws, Skip if Clear
Bit Test f, Skip if Set
1
1
1
1
None
None
None
(2 or 3)
11
BTSS
1
(2 or 3)
Bit Test Ws, Skip if Set
1
(2 or 3)
© 2009 Microchip Technology Inc.
Preliminary
DS70592A-page 227
PIC24HJXXXGPX06A/X08A/X10A
TABLE 22-2: INSTRUCTION SET OVERVIEW (CONTINUED)
Base
Instr
#
Assembly
Mnemonic
# of
# of
Status Flags
Affected
Assembly Syntax
Description
Words Cycles
12
BTST
BTST
f,#bit4
Ws,#bit4
Ws,#bit4
Ws,Wb
Bit Test f
1
1
1
1
1
1
1
1
2
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
2
2
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Z
BTST.C
BTST.Z
BTST.C
BTST.Z
BTSTS
Bit Test Ws to C
Bit Test Ws to Z
C
Z
Bit Test Ws<Wb> to C
Bit Test Ws<Wb> to Z
Bit Test then Set f
C
Z
Ws,Wb
13
BTSTS
f,#bit4
Z
BTSTS.C Ws,#bit4
BTSTS.Z Ws,#bit4
Bit Test Ws to C, then Set
Bit Test Ws to Z, then Set
Call subroutine
C
Z
14
15
CALL
CLR
CALL
CALL
CLR
CLR
CLR
CLRWDT
COM
COM
COM
CP
lit23
Wn
None
Call indirect subroutine
f = 0x0000
None
f
None
WREG
Ws
WREG = 0x0000
None
Ws = 0x0000
None
16
17
CLRWDT
COM
Clear Watchdog Timer
f = f
WDTO,Sleep
N,Z
f
f,WREG
Ws,Wd
f
WREG = f
N,Z
Wd = Ws
N,Z
18
CP
Compare f with WREG
Compare Wb with lit5
Compare Wb with Ws (Wb – Ws)
Compare f with 0x0000
Compare Ws with 0x0000
Compare f with WREG, with Borrow
Compare Wb with lit5, with Borrow
C,DC,N,OV,Z
C,DC,N,OV,Z
C,DC,N,OV,Z
C,DC,N,OV,Z
C,DC,N,OV,Z
C,DC,N,OV,Z
C,DC,N,OV,Z
C,DC,N,OV,Z
CP
Wb,#lit5
Wb,Ws
f
CP
19
20
CP0
CPB
CP0
CP0
CPB
CPB
CPB
Ws
f
Wb,#lit5
Wb,Ws
Compare Wb with Ws, with Borrow
(Wb – Ws – C)
21
22
23
24
CPSEQ
CPSGT
CPSLT
CPSNE
CPSEQ
CPSGT
CPSLT
CPSNE
Wb, Wn
Wb, Wn
Wb, Wn
Wb, Wn
Compare Wb with Wn, skip if =
Compare Wb with Wn, skip if >
Compare Wb with Wn, skip if <
Compare Wb with Wn, skip if ≠
1
1
1
1
1
None
None
None
None
(2 or 3)
1
(2 or 3)
1
(2 or 3)
1
(2 or 3)
25
26
DAW
DEC
DAW
Wn
Wn = decimal adjust Wn
f = f – 1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
2
1
1
1
C
DEC
f
C,DC,N,OV,Z
C,DC,N,OV,Z
C,DC,N,OV,Z
C,DC,N,OV,Z
C,DC,N,OV,Z
C,DC,N,OV,Z
None
DEC
f,WREG
Ws,Wd
f
WREG = f – 1
1
DEC
Wd = Ws – 1
1
27
DEC2
DEC2
DEC2
DEC2
DISI
DIV.S
DIV.SD
DIV.U
DIV.UD
EXCH
FBCL
FF1L
FF1R
GOTO
GOTO
f = f – 2
1
f,WREG
Ws,Wd
#lit14
Wm,Wn
Wm,Wn
Wm,Wn
Wm,Wn
Wns,Wnd
Ws,Wnd
Ws,Wnd
Ws,Wnd
Expr
WREG = f – 2
1
Wd = Ws – 2
1
28
29
DISI
DIV
Disable Interrupts for k instruction cycles
Signed 16/16-bit Integer Divide
Signed 32/16-bit Integer Divide
Unsigned 16/16-bit Integer Divide
Unsigned 32/16-bit Integer Divide
Swap Wns with Wnd
1
18
18
18
18
1
N,Z,C,OV
N,Z,C,OV
N,Z,C,OV
N,Z,C,OV
None
30
31
32
33
34
EXCH
FBCL
FF1L
FF1R
GOTO
Find Bit Change from Left (MSb) Side
Find First One from Left (MSb) Side
Find First One from Right (LSb) Side
Go to address
1
C
1
C
1
C
2
None
Wn
Go to indirect
2
None
DS70592A-page 228
Preliminary
© 2009 Microchip Technology Inc.
PIC24HJXXXGPX06A/X08A/X10A
TABLE 22-2: INSTRUCTION SET OVERVIEW (CONTINUED)
Base
Instr
#
Assembly
Mnemonic
# of
# of
Status Flags
Affected
Assembly Syntax
Description
Words Cycles
35
INC
INC
f
f = f + 1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
2
2
1
1
1
1
C,DC,N,OV,Z
C,DC,N,OV,Z
C,DC,N,OV,Z
C,DC,N,OV,Z
C,DC,N,OV,Z
C,DC,N,OV,Z
N,Z
INC
f,WREG
Ws,Wd
WREG = f + 1
Wd = Ws + 1
f = f + 2
INC
36
37
INC2
IOR
INC2
INC2
INC2
IOR
f
f,WREG
Ws,Wd
WREG = f + 2
Wd = Ws + 2
f
f = f .IOR. WREG
IOR
f,WREG
#lit10,Wn
Wb,Ws,Wd
Wb,#lit5,Wd
#lit14
f
WREG = f .IOR. WREG
Wd = lit10 .IOR. Wd
N,Z
IOR
N,Z
IOR
Wd = Wb .IOR. Ws
N,Z
IOR
Wd = Wb .IOR. lit5
N,Z
38
39
LNK
LSR
LNK
Link Frame Pointer
None
LSR
f = Logical Right Shift f
C,N,OV,Z
C,N,OV,Z
C,N,OV,Z
N,Z
LSR
f,WREG
Ws,Wd
WREG = Logical Right Shift f
Wd = Logical Right Shift Ws
Wnd = Logical Right Shift Wb by Wns
Wnd = Logical Right Shift Wb by lit5
Move f to Wn
LSR
LSR
Wb,Wns,Wnd
Wb,#lit5,Wnd
f,Wn
LSR
N,Z
40
MOV
MOV
None
MOV
f
Move f to f
N,Z
MOV
f,WREG
#lit16,Wn
#lit8,Wn
Wn,f
Move f to WREG
N,Z
MOV
Move 16-bit literal to Wn
Move 8-bit literal to Wn
None
MOV.b
MOV
None
Move Wn to f
None
MOV
Wso,Wdo
WREG,f
Wns,Wd
Ws,Wnd
Wb,Ws,Wnd
Wb,Ws,Wnd
Wb,Ws,Wnd
Wb,Ws,Wnd
Move Ws to Wd
None
MOV
Move WREG to f
N,Z
MOV.D
MOV.D
MUL.SS
MUL.SU
MUL.US
MUL.UU
Move Double from W(ns):W(ns + 1) to Wd
Move Double from Ws to W(nd + 1):W(nd)
{Wnd + 1, Wnd} = signed(Wb) * signed(Ws)
{Wnd + 1, Wnd} = signed(Wb) * unsigned(Ws)
{Wnd + 1, Wnd} = unsigned(Wb) * signed(Ws)
None
None
41
MUL
None
None
None
{Wnd + 1, Wnd} = unsigned(Wb) *
unsigned(Ws)
None
MUL.SU
MUL.UU
Wb,#lit5,Wnd
Wb,#lit5,Wnd
{Wnd + 1, Wnd} = signed(Wb) * unsigned(lit5)
1
1
1
1
None
None
{Wnd + 1, Wnd} = unsigned(Wb) *
unsigned(lit5)
MUL
f
W3:W2 = f * WREG
f = f + 1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
2
None
C,DC,N,OV,Z
C,DC,N,OV,Z
C,DC,N,OV,Z
None
42
NEG
NEG
f
NEG
f,WREG
Ws,Wd
WREG = f + 1
NEG
Wd = Ws + 1
43
44
NOP
POP
NOP
No Operation
NOPR
POP
No Operation
None
f
Pop f from Top-of-Stack (TOS)
Pop from Top-of-Stack (TOS) to Wdo
None
POP
Wdo
Wnd
None
POP.D
Pop from Top-of-Stack (TOS) to
W(nd):W(nd + 1)
None
POP.S
PUSH
Pop Shadow Registers
1
1
1
1
1
1
1
1
1
2
1
1
All
None
45
46
PUSH
f
Push f to Top-of-Stack (TOS)
Push Wso to Top-of-Stack (TOS)
Push W(ns):W(ns + 1) to Top-of-Stack (TOS)
Push Shadow Registers
PUSH
Wso
Wns
None
PUSH.D
PUSH.S
PWRSAV
None
None
PWRSAV
#lit1
Go into Sleep or Idle mode
WDTO,Sleep
© 2009 Microchip Technology Inc.
Preliminary
DS70592A-page 229
PIC24HJXXXGPX06A/X08A/X10A
TABLE 22-2: INSTRUCTION SET OVERVIEW (CONTINUED)
Base
Instr
#
Assembly
Mnemonic
# of
# of
Status Flags
Affected
Assembly Syntax
Description
Words Cycles
47
RCALL
RCALL
RCALL
REPEAT
REPEAT
RESET
RETFIE
RETLW
RETURN
RLC
Expr
Wn
Relative Call
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
2
2
None
None
Computed Call
48
REPEAT
#lit14
Wn
Repeat Next Instruction lit14 + 1 times
Repeat Next Instruction (Wn) + 1 times
Software device Reset
Return from interrupt
1
None
1
None
49
50
51
52
53
RESET
RETFIE
RETLW
RETURN
RLC
1
None
3 (2)
3 (2)
3 (2)
1
None
#lit10,Wn
Return with literal in Wn
Return from Subroutine
f = Rotate Left through Carry f
WREG = Rotate Left through Carry f
Wd = Rotate Left through Carry Ws
f = Rotate Left (No Carry) f
WREG = Rotate Left (No Carry) f
Wd = Rotate Left (No Carry) Ws
f = Rotate Right through Carry f
WREG = Rotate Right through Carry f
Wd = Rotate Right through Carry Ws
f = Rotate Right (No Carry) f
WREG = Rotate Right (No Carry) f
Wd = Rotate Right (No Carry) Ws
Wnd = sign-extended Ws
f = 0xFFFF
None
None
f
C,N,Z
RLC
f,WREG
Ws,Wd
f
1
C,N,Z
RLC
1
C,N,Z
54
55
56
RLNC
RRC
RLNC
RLNC
RLNC
RRC
1
N,Z
f,WREG
Ws,Wd
f
1
N,Z
1
N,Z
1
C,N,Z
RRC
f,WREG
Ws,Wd
f
1
C,N,Z
RRC
1
C,N,Z
RRNC
RRNC
RRNC
RRNC
SE
1
N,Z
f,WREG
Ws,Wd
Ws,Wnd
f
1
N,Z
1
N,Z
57
58
SE
1
C,N,Z
SETM
SETM
SETM
SETM
SL
1
None
WREG
WREG = 0xFFFF
1
None
Ws
Ws = 0xFFFF
1
None
59
60
61
SL
f
f = Left Shift f
1
C,N,OV,Z
C,N,OV,Z
C,N,OV,Z
N,Z
SL
f,WREG
Ws,Wd
Wb,Wns,Wnd
Wb,#lit5,Wnd
f
WREG = Left Shift f
1
SL
Wd = Left Shift Ws
1
SL
Wnd = Left Shift Wb by Wns
Wnd = Left Shift Wb by lit5
f = f – WREG
1
SL
1
N,Z
SUB
SUB
1
C,DC,N,OV,Z
C,DC,N,OV,Z
C,DC,N,OV,Z
C,DC,N,OV,Z
C,DC,N,OV,Z
C,DC,N,OV,Z
C,DC,N,OV,Z
C,DC,N,OV,Z
C,DC,N,OV,Z
C,DC,N,OV,Z
C,DC,N,OV,Z
C,DC,N,OV,Z
C,DC,N,OV,Z
C,DC,N,OV,Z
C,DC,N,OV,Z
C,DC,N,OV,Z
C,DC,N,OV,Z
C,DC,N,OV,Z
None
SUB
f,WREG
#lit10,Wn
Wb,Ws,Wd
Wb,#lit5,Wd
f
WREG = f – WREG
1
SUB
Wn = Wn – lit10
1
SUB
Wd = Wb – Ws
1
SUB
Wd = Wb – lit5
1
SUBB
SUBB
SUBB
SUBB
SUBB
SUBB
SUBR
SUBR
SUBR
SUBR
SUBBR
SUBBR
SUBBR
SUBBR
SWAP.b
SWAP
TBLRDH
f = f – WREG – (C)
1
f,WREG
#lit10,Wn
Wb,Ws,Wd
Wb,#lit5,Wd
f
WREG = f – WREG – (C)
Wn = Wn – lit10 – (C)
1
1
Wd = Wb – Ws – (C)
1
Wd = Wb – lit5 – (C)
1
62
63
SUBR
f = WREG – f
1
f,WREG
Wb,Ws,Wd
Wb,#lit5,Wd
f
WREG = WREG – f
1
Wd = Ws – Wb
1
Wd = lit5 – Wb
1
SUBBR
f = WREG – f – (C)
1
f,WREG
Wb,Ws,Wd
Wb,#lit5,Wd
Wn
WREG = WREG – f – (C)
Wd = Ws – Wb – (C)
1
1
Wd = lit5 – Wb – (C)
1
64
65
SWAP
Wn = nibble swap Wn
Wn = byte swap Wn
1
Wn
1
None
TBLRDH
Ws,Wd
Read Prog<23:16> to Wd<7:0>
2
None
DS70592A-page 230
Preliminary
© 2009 Microchip Technology Inc.
PIC24HJXXXGPX06A/X08A/X10A
TABLE 22-2: INSTRUCTION SET OVERVIEW (CONTINUED)
Base
Instr
#
Assembly
Mnemonic
# of
# of
Status Flags
Affected
Assembly Syntax
Description
Words Cycles
66
TBLRDL
TBLWTH
TBLWTL
ULNK
TBLRDL
TBLWTH
TBLWTL
ULNK
XOR
Ws,Wd
Ws,Wd
Ws,Wd
Read Prog<15:0> to Wd
1
1
1
1
1
1
1
1
1
1
2
2
2
1
1
1
1
1
1
1
None
None
None
None
N,Z
67
68
69
70
Write Ws<7:0> to Prog<23:16>
Write Ws to Prog<15:0>
Unlink Frame Pointer
f = f .XOR. WREG
XOR
f
XOR
f,WREG
WREG = f .XOR. WREG
Wd = lit10 .XOR. Wd
Wd = Wb .XOR. Ws
N,Z
XOR
#lit10,Wn
Wb,Ws,Wd
Wb,#lit5,Wd
Ws,Wnd
N,Z
XOR
N,Z
XOR
Wd = Wb .XOR. lit5
N,Z
71
ZE
ZE
Wnd = Zero-extend Ws
C,Z,N
© 2009 Microchip Technology Inc.
Preliminary
DS70592A-page 231
PIC24HJXXXGPX06A/X08A/X10A
NOTES:
DS70592A-page 232
Preliminary
© 2009 Microchip Technology Inc.
PIC24HJXXXGPX06A/X08A/X10A
23.1 MPLAB Integrated Development
Environment Software
23.0 DEVELOPMENT SUPPORT
The PIC® microcontrollers are supported with a full
range of hardware and software development tools:
The MPLAB IDE software brings an ease of software
development previously unseen in the 8/16-bit micro-
controller market. The MPLAB IDE is a Windows®
operating system-based application that contains:
• Integrated Development Environment
- MPLAB® IDE Software
• Assemblers/Compilers/Linkers
- MPASMTM Assembler
• A single graphical interface to all debugging tools
- Simulator
- MPLAB C18 and MPLAB C30 C Compilers
- MPLINKTM Object Linker/
MPLIBTM Object Librarian
- Programmer (sold separately)
- Emulator (sold separately)
- In-Circuit Debugger (sold separately)
• A full-featured editor with color-coded context
• A multiple project manager
- MPLAB ASM30 Assembler/Linker/Library
• Simulators
- MPLAB SIM Software Simulator
• Emulators
• Customizable data windows with direct edit of
contents
- MPLAB ICE 2000 In-Circuit Emulator
- MPLAB REAL ICE™ In-Circuit Emulator
• In-Circuit Debugger
• High-level source code debugging
• Visual device initializer for easy register
initialization
- MPLAB ICD 2
• Mouse over variable inspection
• Device Programmers
• Drag and drop variables from source to watch
windows
- PICSTART® Plus Development Programmer
- MPLAB PM3 Device Programmer
- PICkit™ 2 Development Programmer
• Extensive on-line help
• Integration of select third party tools, such as
HI-TECH Software C Compilers and IAR
C Compilers
• Low-Cost Demonstration and Development
Boards and Evaluation Kits
The MPLAB IDE allows you to:
• Edit your source files (either assembly or C)
• One touch assemble (or compile) and download
to PIC MCU emulator and simulator tools
(automatically updates all project information)
• Debug using:
- Source files (assembly or C)
- Mixed assembly and C
- Machine code
MPLAB IDE supports multiple debugging tools in a
single development paradigm, from the cost-effective
simulators, through low-cost in-circuit debuggers, to
full-featured emulators. This eliminates the learning
curve when upgrading to tools with increased flexibility
and power.
© 2009 Microchip Technology Inc.
Preliminary
DS70592A-page 233
PIC24HJXXXGPX06A/X08A/X10A
23.2 MPASM Assembler
23.5 MPLAB ASM30 Assembler, Linker
and Librarian
The MPASM Assembler is a full-featured, universal
macro assembler for all PIC MCUs.
MPLAB ASM30 Assembler produces relocatable
machine code from symbolic assembly language for
dsPIC30F devices. MPLAB C30 C Compiler uses the
assembler to produce its object file. The assembler
generates relocatable object files that can then be
archived or linked with other relocatable object files and
archives to create an executable file. Notable features
of the assembler include:
The MPASM Assembler generates relocatable object
files for the MPLINK Object Linker, Intel® standard HEX
files, MAP files to detail memory usage and symbol
reference, absolute LST files that contain source lines
and generated machine code and COFF files for
debugging.
The MPASM Assembler features include:
• Integration into MPLAB IDE projects
• Support for the entire dsPIC30F instruction set
• Support for fixed-point and floating-point data
• Command line interface
• User-defined macros to streamline
assembly code
• Rich directive set
• Conditional assembly for multi-purpose
source files
• Flexible macro language
• MPLAB IDE compatibility
• Directives that allow complete control over the
assembly process
23.6 MPLAB SIM Software Simulator
23.3 MPLAB C18 and MPLAB C30
C Compilers
The MPLAB SIM Software Simulator allows code
development in a PC-hosted environment by simulat-
ing the PIC MCUs and dsPIC® DSCs on an instruction
level. On any given instruction, the data areas can be
examined or modified and stimuli can be applied from
a comprehensive stimulus controller. Registers can be
logged to files for further run-time analysis. The trace
buffer and logic analyzer display extend the power of
the simulator to record and track program execution,
actions on I/O, most peripherals and internal registers.
The MPLAB C18 and MPLAB C30 Code Development
Systems are complete ANSI
C
compilers for
Microchip’s PIC18 and PIC24 families of microcon-
trollers and the dsPIC30 and dsPIC33 family of digital
signal controllers. These compilers provide powerful
integration capabilities, superior code optimization and
ease of use not found with other compilers.
For easy source level debugging, the compilers provide
symbol information that is optimized to the MPLAB IDE
debugger.
The MPLAB SIM Software Simulator fully supports
symbolic debugging using the MPLAB C18 and
MPLAB C30 C Compilers, and the MPASM and
MPLAB ASM30 Assemblers. The software simulator
offers the flexibility to develop and debug code outside
of the hardware laboratory environment, making it an
excellent, economical software development tool.
23.4 MPLINK Object Linker/
MPLIB Object Librarian
The MPLINK Object Linker combines relocatable
objects created by the MPASM Assembler and the
MPLAB C18 C Compiler. It can link relocatable objects
from precompiled libraries, using directives from a
linker script.
The MPLIB Object Librarian manages the creation and
modification of library files of precompiled code. When
a routine from a library is called from a source file, only
the modules that contain that routine will be linked in
with the application. This allows large libraries to be
used efficiently in many different applications.
The object linker/library features include:
• Efficient linking of single libraries instead of many
smaller files
• Enhanced code maintainability by grouping
related modules together
• Flexible creation of libraries with easy module
listing, replacement, deletion and extraction
DS70592A-page 234
Preliminary
© 2009 Microchip Technology Inc.
PIC24HJXXXGPX06A/X08A/X10A
23.7 MPLAB ICE 2000
High-Performance
23.9 MPLAB ICD 2 In-Circuit Debugger
Microchip’s In-Circuit Debugger, MPLAB ICD 2, is a
In-Circuit Emulator
powerful, low-cost, run-time development tool,
connecting to the host PC via an RS-232 or high-speed
USB interface. This tool is based on the Flash PIC
MCUs and can be used to develop for these and other
PIC MCUs and dsPIC DSCs. The MPLAB ICD 2 utilizes
the in-circuit debugging capability built into the Flash
devices. This feature, along with Microchip’s In-Circuit
Serial ProgrammingTM (ICSPTM) protocol, offers cost-
effective, in-circuit Flash debugging from the graphical
user interface of the MPLAB Integrated Development
Environment. This enables a designer to develop and
debug source code by setting breakpoints, single step-
ping and watching variables, and CPU status and
peripheral registers. Running at full speed enables
testing hardware and applications in real time. MPLAB
ICD 2 also serves as a development programmer for
selected PIC devices.
The MPLAB ICE 2000 In-Circuit Emulator is intended
to provide the product development engineer with a
complete microcontroller design tool set for PIC
microcontrollers. Software control of the MPLAB ICE
2000 In-Circuit Emulator is advanced by the MPLAB
Integrated Development Environment, which allows
editing, building, downloading and source debugging
from a single environment.
The MPLAB ICE 2000 is a full-featured emulator
system with enhanced trace, trigger and data monitor-
ing features. Interchangeable processor modules allow
the system to be easily reconfigured for emulation of
different processors. The architecture of the MPLAB
ICE 2000 In-Circuit Emulator allows expansion to
support new PIC microcontrollers.
The MPLAB ICE 2000 In-Circuit Emulator system has
been designed as a real-time emulation system with
advanced features that are typically found on more
expensive development tools. The PC platform and
Microsoft® Windows® 32-bit operating system were
chosen to best make these features available in a
simple, unified application.
23.10 MPLAB PM3 Device Programmer
The MPLAB PM3 Device Programmer is a universal,
CE compliant device programmer with programmable
voltage verification at VDDMIN and VDDMAX for
maximum reliability. It features a large LCD display
(128 x 64) for menus and error messages and a modu-
lar, detachable socket assembly to support various
package types. The ICSP cable assembly is included
as a standard item. In Stand-Alone mode, the MPLAB
PM3 Device Programmer can read, verify and program
PIC devices without a PC connection. It can also set
code protection in this mode. The MPLAB PM3
connects to the host PC via an RS-232 or USB cable.
The MPLAB PM3 has high-speed communications and
optimized algorithms for quick programming of large
memory devices and incorporates an SD/MMC card for
file storage and secure data applications.
23.8 MPLAB REAL ICE In-Circuit
Emulator System
MPLAB REAL ICE In-Circuit Emulator System is
Microchip’s next generation high-speed emulator for
Microchip Flash DSC and MCU devices. It debugs and
programs PIC® Flash MCUs and dsPIC® Flash DSCs
with the easy-to-use, powerful graphical user interface of
the MPLAB Integrated Development Environment (IDE),
included with each kit.
The MPLAB REAL ICE probe is connected to the design
engineer’s PC using a high-speed USB 2.0 interface and
is connected to the target with either a connector
compatible with the popular MPLAB ICD 2 system
(RJ11) or with the new high-speed, noise tolerant, Low-
Voltage Differential Signal (LVDS) interconnection
(CAT5).
MPLAB REAL ICE is field upgradeable through future
firmware downloads in MPLAB IDE. In upcoming
releases of MPLAB IDE, new devices will be supported,
and new features will be added, such as software break-
points and assembly code trace. MPLAB REAL ICE
offers significant advantages over competitive emulators
including low-cost, full-speed emulation, real-time
variable watches, trace analysis, complex breakpoints, a
ruggedized probe interface and long (up to three meters)
interconnection cables.
© 2009 Microchip Technology Inc.
Preliminary
DS70592A-page 235
PIC24HJXXXGPX06A/X08A/X10A
23.11 PICSTART Plus Development
Programmer
23.13 Demonstration, Development and
Evaluation Boards
The PICSTART Plus Development Programmer is an
easy-to-use, low-cost, prototype programmer. It
connects to the PC via a COM (RS-232) port. MPLAB
Integrated Development Environment software makes
using the programmer simple and efficient. The
PICSTART Plus Development Programmer supports
most PIC devices in DIP packages up to 40 pins.
Larger pin count devices, such as the PIC16C92X and
PIC17C76X, may be supported with an adapter socket.
The PICSTART Plus Development Programmer is CE
compliant.
A wide variety of demonstration, development and
evaluation boards for various PIC MCUs and dsPIC
DSCs allows quick application development on fully func-
tional systems. Most boards include prototyping areas for
adding custom circuitry and provide application firmware
and source code for examination and modification.
The boards support a variety of features, including LEDs,
temperature sensors, switches, speakers, RS-232
interfaces, LCD displays, potentiometers and additional
EEPROM memory.
The demonstration and development boards can be
used in teaching environments, for prototyping custom
circuits and for learning about various microcontroller
applications.
23.12 PICkit 2 Development Programmer
The PICkit 2 Development Programmer is a low-cost
programmer and selected Flash device debugger with
an easy-to-use interface for programming many of
Microchip’s baseline, mid-range and PIC18F families of
Flash memory microcontrollers. The PICkit 2 Starter Kit
includes a prototyping development board, twelve
sequential lessons, software and HI-TECH’s PICC™
Lite C compiler, and is designed to help get up to speed
quickly using PIC microcontrollers. The kit provides
everything needed to program, evaluate and develop
applications using Microchip’s powerful, mid-range
Flash memory family of microcontrollers.
In addition to the PICDEM™ and dsPICDEM™ demon-
stration/development board series of circuits, Microchip
has a line of evaluation kits and demonstration software
®
for analog filter design, KEELOQ security ICs, CAN,
IrDA®, PowerSmart battery management, SEEVAL®
evaluation system, Sigma-Delta ADC, flow rate
sensing, plus many more.
Check the Microchip web page (www.microchip.com)
for the complete list of demonstration, development
and evaluation kits.
DS70592A-page 236
Preliminary
© 2009 Microchip Technology Inc.
PIC24HJXXXGPX06A/X08A/X10A
24.0 ELECTRICAL CHARACTERISTICS
This section provides an overview of PIC24HJXXXGPX06A/X08A/X10A electrical characteristics. Additional informa-
tion is provided in future revisions of this document as it becomes available.
Absolute maximum ratings for the PIC24HJXXXGPX06A/X08A/X10A family are listed below. Exposure to these maxi-
mum rating conditions for extended periods can affect device reliability. Functional operation of the device at these or
any other conditions above the parameters indicated in the operation listings of this specification is not implied.
Absolute Maximum Ratings(1)
Ambient temperature under bias.............................................................................................................-40°C to +125°C
Storage temperature .............................................................................................................................. -65°C to +150°C
Voltage on VDD with respect to VSS ......................................................................................................... -0.3V to +4.0V
Voltage on any combined analog and digital pin and MCLR, with respect to VSS ......................... -0.3V to (VDD + 0.3V)
Voltage on any digital-only pin with respect to VSS .................................................................................. -0.3V to +5.6V
Voltage on VCAP/VDDCORE with respect to VSS ....................................................................................... 2.25V to 2.75V
Maximum current out of VSS pin ...........................................................................................................................300 mA
Maximum current into VDD pin(2)...........................................................................................................................250 mA
Maximum output current sunk by any I/O pin(3) ........................................................................................................4 mA
Maximum output current sourced by any I/O pin(3)...................................................................................................4 mA
Maximum current sunk by all ports .......................................................................................................................200 mA
Maximum current sourced by all ports(2)...............................................................................................................200 mA
Note 1: Stresses above those listed under “Absolute Maximum Ratings” can cause permanent damage to the
device. This is a stress rating only, and functional operation of the device at those or any other conditions
above those indicated in the operation listings of this specification is not implied. Exposure to maximum
rating conditions for extended periods can affect device reliability.
2: Maximum allowable current is a function of device maximum power dissipation (see Table 24-2).
3: Exceptions are CLKOUT, which is able to sink/source 25 mA, and the VREF+, VREF-, SCLx, SDAx, PGECx
and PGEDx pins, which are able to sink/source 12 mA.
© 2009 Microchip Technology Inc.
Preliminary
DS70592A-page 237
PIC24HJXXXGPX06A/X08A/X10A
24.1 DC Characteristics
TABLE 24-1: OPERATING MIPS VS. VOLTAGE
Max MIPS
VDD Range
(in Volts)
Temp Range
(in °C)
Characteristic
PIC24HJXXXGPX06A/X08A/X10A
3.0-3.6V
3.0-3.6V
-40°C to +85°C
-40°C to +125°C
40
40
TABLE 24-2: THERMAL OPERATING CONDITIONS
Rating
Symbol
Min
Typ
Max
Unit
Industrial Temperature Devices
Operating Junction Temperature Range
Operating Ambient Temperature Range
Extended Temperature Devices
TJ
TA
-40
-40
—
—
+125
+85
°C
°C
Operating Junction Temperature Range
Operating Ambient Temperature Range
TJ
TA
-40
-40
—
—
+140
+125
°C
°C
Power Dissipation:
Internal chip power dissipation:
PINT = VDD x (IDD – Σ IOH)
PD
PINT + PI/O
W
W
I/O Pin Power Dissipation:
I/O = Σ ({VDD – VOH} x IOH) + Σ (VOL x IOL)
Maximum Allowed Power Dissipation
PDMAX
(TJ – TA)/θJA
TABLE 24-3: THERMAL PACKAGING CHARACTERISTICS
Characteristic
Symbol
Typ
Max
Unit
Notes
Package Thermal Resistance, 100-pin TQFP (14x14x1 mm)
Package Thermal Resistance, 100-pin TQFP (12x12x1 mm)
Package Thermal Resistance, 64-pin TQFP (10x10x1 mm)
Package Thermal Resistance, 64-pin QFN (9x9x0.9 mm)
θJA
θJA
θJA
θJA
40
40
40
28
—
—
—
—
°C/W
°C/W
°C/W
°C/W
1
1
1
1
Note 1: Junction to ambient thermal resistance, Theta-JA (θJA) numbers are achieved by package simulations.
DS70592A-page 238
Preliminary
© 2009 Microchip Technology Inc.
PIC24HJXXXGPX06A/X08A/X10A
TABLE 24-4: DC TEMPERATURE AND VOLTAGE SPECIFICATIONS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C ≤ TA ≤ +85°C for Industrial
-40°C ≤ TA ≤ +125°C for Extended
DC CHARACTERISTICS
Param
Symbol
No.
Characteristic
Min
Typ(1)
Max Units
Conditions
Operating Voltage
DC10 Supply Voltage
VDD
3.0
1.8
—
—
—
—
3.6
—
V
V
V
Industrial and Extended
DC12
DC16
VDR
RAM Data Retention Voltage(2)
VDD Start Voltage(4)
—
—
VPOR
VSS
to ensure internal
Power-on Reset signal
DC17
DC18
SVDD
VDD Rise Rate
to ensure internal
Power-on Reset signal
VDD Core(3)
0.03
2.25
—
—
—
V/ms 0-3.0V in 0.1s
VCORE
2.75
V
Voltage is dependent on
Internal regulator voltage
load, temperature and
VDD
Note 1: Data in “Typ” column is at 3.3V, 25°C unless otherwise stated.
2: This is the limit to which VDD can be lowered without losing RAM data.
3: These parameters are characterized but not tested in manufacturing.
4: VDD voltage must remain at VSS for a minimum of 200 μs to ensure POR.
© 2009 Microchip Technology Inc.
Preliminary
DS70592A-page 239
PIC24HJXXXGPX06A/X08A/X10A
TABLE 24-5: DC CHARACTERISTICS: OPERATING CURRENT (IDD)
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
DC CHARACTERISTICS
Operating temperature -40°C ≤ TA ≤ +85°C for Industrial
-40°C ≤ TA ≤ +125°C for Extended
Parameter
Typical(1)
Max
Units
Conditions
No.
Operating Current (IDD)(2)
DC20d
DC20a
DC20b
DC20c
DC21d
DC21a
DC21b
DC21c
DC22d
DC22a
DC22b
DC22c
DC23d
DC23a
DC23b
DC23c
DC24d
DC24a
DC24b
DC24c
27
27
27
27
36
37
38
39
43
46
46
47
65
65
65
65
84
84
84
84
30
30
30
35
40
40
45
45
50
50
55
55
70
70
70
70
90
90
90
90
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
-40°C
+25°C
+85°C
+125°C
-40°C
3.3V
3.3V
3.3V
3.3V
3.3V
10 MIPS
16 MIPS
20 MIPS
30 MIPS
40 MIPS
+25°C
+85°C
+125°C
-40°C
+25°C
+85°C
+125°C
-40°C
+25°C
+85°C
+125°C
-40°C
+25°C
+85°C
+125°C
Note 1: Data in “Typical” column is at 3.3V, 25°C unless otherwise stated.
2: The supply current is mainly a function of the operating voltage and frequency. Other factors, such as I/O
pin loading and switching rate, oscillator type, internal code execution pattern and temperature, also have
an impact on the current consumption. The test conditions for all IDD measurements are as follows: OSC1
driven with external square wave from rail to rail. All I/O pins are configured as inputs and pulled to VSS.
MCLR = VDD, WDT and FSCM are disabled. CPU, SRAM, program memory and data memory are
operational. No peripheral modules are operating; however, every peripheral is being clocked (PMD bits
are all zeroed).
DS70592A-page 240
Preliminary
© 2009 Microchip Technology Inc.
PIC24HJXXXGPX06A/X08A/X10A
TABLE 24-6: DC CHARACTERISTICS: IDLE CURRENT (IIDLE)
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C ≤ TA ≤ +85°C for Industrial
-40°C ≤ TA ≤ +125°C for Extended
DC CHARACTERISTICS
Parameter
Typical(1)
No.
Max
Units
Conditions
Idle Current (IIDLE): Core OFF Clock ON Base Current(2)
DC40d
DC40a
DC40b
DC40c
DC41d
DC41a
DC41b
DC41c
DC42d
DC42a
DC42b
DC42c
DC43a
DC43d
DC43b
DC43c
DC44d
DC44a
DC44b
DC44c
3
3
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
-40°C
+25°C
+85°C
+125°C
-40°C
10 MIPS
16 MIPS
20 MIPS
30 MIPS
40 MIPS
3.3V
3.3V
3
3
4
5
+25°C
+85°C
+125°C
-40°C
6
6
8
9
+25°C
+85°C
+125°C
+25°C
-40°C
3.3V
3.3V
3.3V
10
10
15
15
15
15
16
16
16
16
+85°C
+125°C
-40°C
+25°C
+85°C
+125°C
Note 1: Data in “Typical” column is at 3.3V, 25°C unless otherwise stated.
2: Base IIDLE current is measured with core off, clock on and all modules turned off. Peripheral Module
Disable SFR registers are zeroed. All I/O pins are configured as inputs and pulled to VSS.
© 2009 Microchip Technology Inc.
Preliminary
DS70592A-page 241
PIC24HJXXXGPX06A/X08A/X10A
TABLE 24-7: DC CHARACTERISTICS: POWER-DOWN CURRENT (IPD)
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
DC CHARACTERISTICS
Operating temperature -40°C ≤ TA ≤ +85°C for Industrial
-40°C ≤ TA ≤ +125°C for Extended
Parameter
Typical(1)
Max
Units
Conditions
No.
Power-Down Current (IPD)(2)
DC60d
DC60a
DC60b
DC60c
DC61d
DC61a
DC61b
DC61c
55
211
244
245
8
500
500
500
1000
13
μA
μA
μA
μA
μA
μA
μA
μA
-40°C
+25°C
+85°C
+125°C
-40°C
3.3V
3.3V
Base Power-Down Current(3,4)
10
15
+25°C
+85°C
+125°C
(3)
Watchdog Timer Current: ΔIWDT
12
20
13
25
Note 1: Data in the Typical column is at 3.3V, 25°C unless otherwise stated.
2: Base IPD is measured with all peripherals and clocks shut down. All I/Os are configured as inputs and
pulled to VSS. WDT, etc., are all switched off.
3: The Δ current is the additional current consumed when the module is enabled. This current should be
added to the base IPD current.
4: These currents are measured on the device containing the most memory in this family.
TABLE 24-8: DC CHARACTERISTICS: DOZE CURRENT (IDOZE)
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
DC CHARACTERISTICS
Operating temperature -40°C ≤ TA ≤ +85°C for Industrial
-40°C ≤ TA ≤ +125°C for Extended
Doze
Ratio
Parameter No.
Typical(1)
Max
Units
Conditions
DC73a
DC73f
DC73g
DC70a
DC70f
DC70g
DC71a
DC71f
DC71g
DC72a
DC72f
DC72g
11
11
11
42
26
25
41
25
24
42
26
25
35
30
30
50
30
30
50
30
30
50
30
30
1:2
1:64
1:128
1:2
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
-40°C
+25°C
+85°C
3.3V
3.3V
3.3V
40 MIPS
40 MIPS
40 MIPS
40 MIPS
1:64
1:128
1:2
1:64
1:128
1:2
1:64
1:128
+125°C 3.3V
Note 1: Data in the Typical column is at 3.3V, 25°C unless otherwise stated.
DS70592A-page 242
Preliminary
© 2009 Microchip Technology Inc.
PIC24HJXXXGPX06A/X08A/X10A
TABLE 24-9: DC CHARACTERISTICS: I/O PIN INPUT SPECIFICATIONS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C ≤ TA ≤ +85°C for Industrial
-40°C ≤ TA ≤ +125°C for Extended
DC CHARACTERISTICS
Param
Symbol
No.
Characteristic
Min
Typ(1)
Max
Units
Conditions
VIL
Input Low Voltage
I/O pins
DI10
DI15
DI16
DI18
DI19
VSS
VSS
VSS
VSS
VSS
—
—
—
—
—
0.2 VDD
0.2 VDD
0.2 VDD
0.3 VDD
0.2 VDD
V
V
V
V
V
MCLR
I/O Pins with OSC1 or SOSCI
I/O Pins with I2C
I/O Pins with I2C
Input High Voltage
SMbus disabled
SMbus enabled
VIH
DI20
DI30
I/O Pins Not 5V Tolerant(4)
0.7 VDD
0.7 VDD
—
—
VDD
5.5
V
V
I/O Pins 5V Tolerant(4)
ICNPU
IIL
CNx Pull-up Current
50
250
400
μA VDD = 3.3V, VPIN = VSS
Input Leakage Current(2,3)
DI50
DI51
I/O Pins
—
—
—
—
±2
±2
μA VSS ≤ VPIN ≤ VDD,
Pin at high-impedance
I/O Pins Not 5V Tolerant(4)
μA VSS ≤ VPIN ≤ VDD,
Pin at high-impedance,
-40°C ≤ TA ≤ +125°C
DI51a
DI51b
I/O Pins Not 5V Tolerant(4)
I/O Pins Not 5V Tolerant(4)
—
—
—
—
±2
μA Shared with external reference
pins, -40°C ≤ TA ≤ +125°C
±3.5
μA VSS ≤ VPIN ≤ VDD, Pin at
high-impedance,
-40°C ≤ TA ≤ +125°C
DI51c
I/O Pins Not 5V Tolerant(4)
—
—
±8
μA Analog pins shared with
external reference pins,
-40°C ≤ TA ≤ +125°C
DI55
DI56
MCLR
OSC1
—
—
—
—
±2
±2
μA
VSS ≤ VPIN ≤ VDD
μA VSS ≤ VPIN ≤ VDD,
XT and HS modes
Note 1: Data in “Typ” column is at 3.3V, 25°C unless otherwise stated.
2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified
levels represent normal operating conditions. Higher leakage current may be measured at different input
voltages.
3: Negative current is defined as current sourced by the pin.
4: See “Pin Diagrams (Continued)” for a list of 5V tolerant pins.
© 2009 Microchip Technology Inc.
Preliminary
DS70592A-page 243
PIC24HJXXXGPX06A/X08A/X10A
TABLE 24-10: DC CHARACTERISTICS: I/O PIN OUTPUT SPECIFICATIONS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
DC CHARACTERISTICS
Operating temperature -40°C ≤ TA ≤ +85°C for Industrial
-40°C ≤ TA ≤ +125°C for Extended
Param
No.
Symbol
Characteristic
Min
Typ
Max Units
Conditions
VOL
Output Low Voltage
I/O ports
DO10
DO16
—
—
—
—
0.4
0.4
V
V
IOL = 2 mA, VDD = 3.3V
IOL = 2 mA, VDD = 3.3V
OSC2/CLKO
VOH
Output High Voltage
I/O ports
DO20
DO26
2.40
2.41
—
—
—
—
V
V
IOH = -2.3 mA, VDD = 3.3V
IOH = -1.3 mA, VDD = 3.3V
OSC2/CLKO
TABLE 24-11: ELECTRICAL CHARACTERISTICS: BOR
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C ≤ TA ≤ +85°C for Industrial
-40°C ≤ TA ≤ +125°C for Extended
DC CHARACTERISTICS
Param
Symbol
No.
Characteristic
Min(1) Typ Max(1) Units
Conditions
BO10
VBOR
BOR Event on VDD transition
high-to-low
2.40 2.55
—
V
—
BOR event is tied to VDD core voltage
decrease
Note 1: Parameters are for design guidance only and are not tested in manufacturing.
DS70592A-page 244
Preliminary
© 2009 Microchip Technology Inc.
PIC24HJXXXGPX06A/X08A/X10A
TABLE 24-12: DC CHARACTERISTICS: PROGRAM MEMORY
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C ≤ TA ≤ +85°C for Industrial
-40°C ≤ TA ≤ +125°C for Extended
DC CHARACTERISTICS
Param
Symbol
No.
Characteristic
Min Typ(1)
Max
Units
Conditions
Program Flash Memory
Cell Endurance
D130
D131
EP
10,000
VMIN
—
—
—
E/W
V
VPR
VDD for Read
3.6
VMIN = Minimum operating
voltage
D132b VPEW
VDD for Self-Timed Write
Characteristic Retention
VMIN
20
—
—
10
—
—
—
—
—
—
3.6
—
V
VMIN = Minimum operating
voltage
D134
D135
TRETD
IDDP
Year Provided no other specifications are
violated
Supply Current during
Programming
—
—
mA
D136a TRW
D136b TRW
D137a TPE
D137b TPE
D138a TWW
D138b TWW
Row Write Time
1.32
1.28
20.1
19.5
42.3
41.1
1.74
1.79
26.5
27.3
55.9
57.6
ms TRW = 11064 FRC cycles,
TA = +85°C, See Note 2
Row Write Time
ms TRW = 11064 FRC cycles,
TA = +125°C, See Note 2
Page Erase Time
Page Erase Time
Word Write Cycle Time
Word Write Cycle Time
ms TPE = 168517 FRC cycles,
TA = +85°C, See Note 2
ms TPE = 168517 FRC cycles,
TA = +125°C, See Note 2
µs TWW = 355 FRC cycles,
TA = +85°C, See Note 2
µs TWW = 355 FRC cycles,
TA = +125°C, See Note 2
Note 1: Data in “Typ” column is at 3.3V, 25°C unless otherwise stated.
2: Other conditions: FRC = 7.37 MHz, TUN<5:0> = b'011111(for Min), TUN<5:0> = b'100000(for Max).
This parameter depends on the FRC accuracy (see Table 24-19) and the value of the FRC Oscillator Tun-
ing register (see Register 9-4). For complete details on calculating the Minimum and Maximum time see
Section 5.3 “Programming Operations”.
TABLE 24-13: INTERNAL VOLTAGE REGULATOR SPECIFICATIONS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C ≤ TA ≤ +85°C for Industrial
-40°C ≤ TA ≤ +125°C for Extended
Param
No.
Symbol
Characteristics
Min
Typ
Max
Units
Comments
CEFC
External Filter Capacitor
Value
4.7
10
—
μF
Capacitor must be low
series resistance
(< 5 Ohms)
© 2009 Microchip Technology Inc.
Preliminary
DS70592A-page 245
PIC24HJXXXGPX06A/X08A/X10A
24.2 AC Characteristics and Timing
Parameters
This section defines PIC24HJXXXGPX06A/X08A/
X10A AC characteristics and timing parameters.
TABLE 24-14: TEMPERATURE AND VOLTAGE SPECIFICATIONS – AC
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C ≤ TA ≤ +85°C for Industrial
AC CHARACTERISTICS
-40°C ≤ TA ≤ +125°C for Extended
Operating voltage VDD range as described in Section 24.0 “Electrical
Characteristics”.
FIGURE 24-1:
LOAD CONDITIONS FOR DEVICE TIMING SPECIFICATIONS
Load Condition 1 – for all pins except OSC2
VDD/2
Load Condition 2 – for OSC2
CL
RL
Pin
VSS
CL
Pin
RL = 464Ω
CL = 50 pF for all pins except OSC2
VSS
15 pF for OSC2 output
TABLE 24-15: CAPACITIVE LOADING REQUIREMENTS ON OUTPUT PINS
Param
Symbol
Characteristic
Min
Typ
Max Units
Conditions
No.
DO50 COSCO
OSC2/SOSCO pin
—
—
15
pF In XT and HS modes when
external clock is used to drive
OSC1
DO56 CIO
DO58 CB
All I/O pins and OSC2
SCLx, SDAx
—
—
—
—
50
pF EC mode
pF In I2C™ mode
400
DS70592A-page 246
Preliminary
© 2009 Microchip Technology Inc.
PIC24HJXXXGPX06A/X08A/X10A
FIGURE 24-2:
EXTERNAL CLOCK TIMING
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
OSC1
CLKO
OS20
OS30 OS30
OS25
OS31 OS31
OS41
OS40
TABLE 24-16: EXTERNAL CLOCK TIMING REQUIREMENTS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C ≤ TA ≤ +85°C for Industrial
-40°C ≤ TA ≤ +125°C for Extended
AC CHARACTERISTICS
Param Sym
Characteristic
Min
Typ(1)
Max
Units
Conditions
No.
bol
OS10
FIN
External CLKI Frequency
(External clocks allowed only
in EC and ECPLL modes)
DC
—
40
MHz EC
Oscillator Crystal Frequency
3.5
10
—
—
—
10
40
33
MHz XT
MHz HS
kHz SOSC
OS20
OS25
OS30
TOSC
TCY
TOSC = 1/FOSC
Instruction Cycle Time(2)
12.5
25
—
—
—
DC
DC
ns
ns
ns
—
—
TosL, External Clock in (OSC1)
TosH High or Low Time
0.375 x TOSC
0.625 x TOSC
EC
OS31
TosR, External Clock in (OSC1)
TosF Rise or Fall Time
—
—
20
ns
EC
OS40
OS41
OS42
TckR CLKO Rise Time(3)
—
—
14
5.2
5.2
16
—
—
18
ns
ns
—
—
TckF
GM
CLKO Fall Time(3)
External Oscillator
mA/V VDD = 3.3V
TA = +25ºC
Transconductance(4)
Note 1: Data in “Typ” column is at 3.3V, 25°C unless otherwise stated.
2: Instruction cycle period (TCY) equals two times the input oscillator time-base period. All specified values
are based on characterization data for that particular oscillator type under standard operating conditions
with the device executing code. Exceeding these specified limits may result in an unstable oscillator
operation and/or higher than expected current consumption. All devices are tested to operate at “min.”
values with an external clock applied to the OSC1/CLKI pin. When an external clock input is used, the
“max.” cycle time limit is “DC” (no clock) for all devices.
3: Measurements are taken in EC mode. The CLKO signal is measured on the OSC2 pin.
4: Data for this parameter is Preliminary. This parameter is characterized, but not tested in manufacturing.
© 2009 Microchip Technology Inc.
Preliminary
DS70592A-page 247
PIC24HJXXXGPX06A/X08A/X10A
TABLE 24-17: PLL CLOCK TIMING SPECIFICATIONS (VDD = 3.0V TO 3.6V)
Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated)
Operating temperature -40°C ≤ TA ≤ +85°C for Industrial
-40°C ≤ TA ≤ +125°C for Extended
AC CHARACTERISTICS
Param
Symbol
No.
Characteristic
Min
Typ(1)
Max
Units
Conditions
OS50
FPLLI
PLL Voltage Controlled
Oscillator (VCO) Input
Frequency Range
0.8
—
8
MHz ECPLL, HSPLL, XTPLL
modes
OS51
FSYS
On-Chip VCO System
Frequency
100
—
200
MHz
OS52
OS53
TLOCK
DCLK
PLL Start-up Time (Lock Time)
CLKO Stability (Jitter)
0.9
-3
1.5
0.5
3.1
3
mS
%
Measured over 100 ms
period
Note 1: Data in “Typ” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only
and are not tested.
TABLE 24-18: AC CHARACTERISTICS: INTERNAL RC ACCURACY
Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated)
AC CHARACTERISTICS
Operating temperature
-40°C ≤ TA ≤ +85°C for Industrial
-40°C ≤ TA ≤ +125°C for Extended
Param
No.
Characteristic
Min
Typ
Max
Units
Conditions
Internal FRC Accuracy @ 7.3728 MHz(1,2)
F20
FRC
FRC
-2
-5
—
—
+2
+5
%
%
-40°C ≤ TA ≤ +85°C
-40°C ≤ TA ≤ +125°C
VDD = 3.0-3.6V
VDD = 3.0-3.6V
Note 1: Frequency calibrated at 25°C and 3.3V. TUN bits can be used to compensate for temperature drift.
2: FRC is set to initial frequency of 7.37 MHz (±2%) at 25°C.
TABLE 24-19: INTERNAL RC ACCURACY
Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated)
AC CHARACTERISTICS
Operating temperature -40°C ≤ TA ≤ +85°C for Industrial
-40°C ≤ TA ≤ +125°C for Extended
Param
No.
Characteristic
Min
Typ
Max
Units
Conditions
LPRC @ 32.768 kHz(1)
F21
LPRC
LPRC
LPRC
-20
-70
—
±6
—
+20
+70
—
%
%
%
-40°C ≤ TA ≤ +85°C
—
—
-40°C ≤ TA ≤ +125°C
-40°C ≤ TA ≤ +85°C
±30
For
PIC24HJ256GPX06
A/X08A/X10A
Devices only(2)
LPRC
—
±35
—
%
-40°C ≤ TA ≤ +125°C
For
PIC24HJ256GPX06
A/X08A/X10A
Devices only(2)
Note 1: Change of LPRC frequency as VDD changes.
2: This data is provided as Advance Information.
DS70592A-page 248
Preliminary
© 2009 Microchip Technology Inc.
PIC24HJXXXGPX06A/X08A/X10A
FIGURE 24-3:
CLKO AND I/O TIMING CHARACTERISTICS
I/O Pin
(Input)
DI35
DI40
I/O Pin
(Output)
New Value
Old Value
DO31
DO32
Note: Refer to Figure 24-1 for load conditions.
TABLE 24-20: I/O TIMING REQUIREMENTS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C ≤ TA ≤ +85°C for Industrial
-40°C ≤ TA ≤ +125°C for Extended
AC CHARACTERISTICS
Param
Symbol
No.
Characteristic
Min
Typ(1)
Max
Units
Conditions
DO31
DO32
DI35
TIOR
TIOF
TINP
TRBP
Port Output Rise Time
—
—
20
2
10
10
—
—
25
25
—
—
ns
ns
—
—
—
—
Port Output Fall Time
INTx Pin High or Low Time (output)
CNx High or Low Time (input)
ns
DI40
TCY
Note 1: Data in “Typ” column is at 3.3V, 25°C unless otherwise stated.
© 2009 Microchip Technology Inc.
Preliminary
DS70592A-page 249
PIC24HJXXXGPX06A/X08A/X10A
FIGURE 24-4:
RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP
TIMER TIMING CHARACTERISTICS
VDD
SY12
MCLR
SY10
Internal
POR
SY11
SY30
PWRT
Time-out
OSC
Time-out
Internal
Reset
Watchdog
Timer
Reset
SY20
SY13
SY13
I/O Pins
SY35
FSCM
Delay
Note: Refer to Figure 24-1 for load conditions.
DS70592A-page 250
Preliminary
© 2009 Microchip Technology Inc.
PIC24HJXXXGPX06A/X08A/X10A
TABLE 24-21: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER
TIMING REQUIREMENTS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
AC CHARACTERISTICS
Operating temperature -40°C ≤ TA ≤ +85°C for Industrial
-40°C ≤ TA ≤ +125°C for Extended
Param
No.
Symbol
Characteristic(1)
Min
Typ(2)
Max Units
Conditions
SY10
SY11
TMCL
MCLR Pulse Width (low)
Power-up Timer Period
2
—
—
—
μs
-40°C to +85°C
TPWRT
—
2
4
ms
-40°C to +85°C
User programmable
8
16
32
64
128
SY12
SY13
TPOR
TIOZ
Power-on Reset Delay
3
10
30
μs
μs
-40°C to +85°C
—
I/O High-Impedance from
MCLR Low or Watchdog
Timer Reset
0.68
0.72
1.2
SY20
TWDT1
Watchdog Timer Time-out
Period
—
—
—
—
See Section 21.4 “Watchdog
Timer (WDT)” and LPRC
specification F21 (Table 24-19)
SY30
SY35
TOST
Oscillator Start-up Timer
Period
—
—
1024 TOSC
500
—
—
TOSC = OSC1 period
TFSCM
Fail-Safe Clock Monitor
Delay
900
μs
-40°C to +85°C
Note 1: These parameters are characterized but not tested in manufacturing.
2: Data in “Typ” column is at 3.3V, 25°C unless otherwise stated.
© 2009 Microchip Technology Inc.
Preliminary
DS70592A-page 251
PIC24HJXXXGPX06A/X08A/X10A
FIGURE 24-5:
TIMER1, 2, 3, 4, 5, 6, 7, 8 AND 9 EXTERNAL CLOCK TIMING CHARACTERISTICS
TxCK
Tx11
Tx10
Tx15
Tx20
OS60
TMRx
Note: Refer to Figure 24-1 for load conditions.
(1)
TABLE 24-22: TIMER1 EXTERNAL CLOCK TIMING REQUIREMENTS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C ≤ TA ≤ +85°C for Industrial
-40°C ≤ TA ≤ +125°C for Extended
AC CHARACTERISTICS
Param
Symbol
No.
Characteristic
Min
Typ
Max Units
Conditions
TA10
TA11
TA15
TTXH
TTXL
TTXP
TxCK High Time
TxCK Low Time
Synchronous,
no prescaler
0.5 TCY + 20
—
—
—
ns
ns
Must also meet
parameter TA15
Synchronous,
with prescaler
10
—
Asynchronous
10
—
—
—
—
ns
ns
Synchronous,
no prescaler
0.5 TCY + 20
Must also meet
parameter TA15
Synchronous,
with prescaler
10
—
—
ns
Asynchronous
10
—
—
—
—
ns
ns
TxCK Input Period Synchronous,
no prescaler
TCY + 40
—
Synchronous,
with prescaler
Greater of:
20 ns or
—
—
—
N = prescale
value
(TCY + 40)/N
(1, 8, 64, 256)
Asynchronous
20
—
—
—
ns
—
—
OS60
TA20
Ft1
SOSCI/T1CK Oscillator Input
DC
50
kHz
frequency Range (oscillator enabled
by setting bit TCS (T1CON<1>))
TCKEXTMRL Delay from External TxCK Clock
Edge to Timer Increment
0.5 TCY
1.5 TCY
—
—
Note 1: Timer1 is a Type A.
DS70592A-page 252
Preliminary
© 2009 Microchip Technology Inc.
PIC24HJXXXGPX06A/X08A/X10A
TABLE 24-23: TIMER2, 4, 6 AND 8 EXTERNAL CLOCK TIMING REQUIREMENTS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C ≤ TA ≤ +85°C for Industrial
-40°C ≤ TA ≤ +125°C for Extended
AC CHARACTERISTICS
Param
Symbol
No.
Characteristic
Min
Typ
Max
Units
Conditions
TB10
TB11
TB15
TtxH
TtxL
TtxP
TxCK High Time Synchronous, 0.5 TCY + 20
no prescaler
—
—
ns
Must also meet
parameter TB15
Synchronous,
with prescaler
10
—
—
—
—
—
—
—
—
ns
ns
ns
ns
TxCK Low Time
Synchronous, 0.5 TCY + 20
no prescaler
Must also meet
parameter TB15
Synchronous,
with prescaler
10
TxCK Input
Period
Synchronous,
no prescaler
TCY + 40
N = prescale
value
(1, 8, 64, 256)
Synchronous,
with prescaler
Greater of:
20 ns or
(TCY + 40)/N
TB20
TCKEXT-
MRL
Delay from External TxCK Clock
Edge to Timer Increment
0.5 TCY
—
1.5 TCY
—
—
TABLE 24-24: TIMER3, 5, 7 AND 9 EXTERNAL CLOCK TIMING REQUIREMENTS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C ≤ TA ≤ +85°C for Industrial
-40°C ≤ TA ≤ +125°C for Extended
AC CHARACTERISTICS
Param
No.
Symbol
TtxH
Characteristic
Min
Typ
Max Units
Conditions
TC10
TC11
TC15
TxCK High Time
TxCK Low Time
Synchronous
Synchronous
0.5 TCY + 20
—
—
—
—
ns
ns
ns
Must also meet
parameter TC15
TtxL
TtxP
0.5 TCY + 20
TCY + 40
—
—
Must also meet
parameter TC15
TxCK Input Period Synchronous,
no prescaler
N = prescale
value
(1, 8, 64, 256)
Synchronous,
with prescaler
Greater of:
20 ns or
(TCY + 40)/N
TC20
TCKEXTMRL Delay from External TxCK Clock
Edge to Timer Increment
0.5 TCY
—
1.5
TCY
—
—
© 2009 Microchip Technology Inc.
Preliminary
DS70592A-page 253
PIC24HJXXXGPX06A/X08A/X10A
FIGURE 24-6:
INPUT CAPTURE (CAPx) TIMING CHARACTERISTICS
ICx
IC10
IC11
IC15
Note: Refer to Figure 24-1 for load conditions.
TABLE 24-25: INPUT CAPTURE TIMING REQUIREMENTS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C ≤ TA ≤ +85°C for Industrial
-40°C ≤ TA ≤ +125°C for Extended
AC CHARACTERISTICS
Param
Symbol
No.
Characteristic(1)
Min
Max
Units
Conditions
IC10
IC11
IC15
TccL
TccH
TccP
ICx Input Low Time No Prescaler
With Prescaler
0.5 TCY + 20
10
—
—
—
—
—
ns
ns
ns
ns
ns
—
ICx Input High Time No Prescaler
With Prescaler
0.5 TCY + 20
10
—
ICx Input Period
(TCY + 40)/N
N = prescale
value (1, 4, 16)
Note 1: These parameters are characterized but not tested in manufacturing.
FIGURE 24-7:
OUTPUT COMPARE MODULE (OCx) TIMING CHARACTERISTICS
OCx
(Output Compare
or PWM Mode)
OC10
OC11
Note: Refer to Figure 24-1 for load conditions.
TABLE 24-26: OUTPUT COMPARE MODULE TIMING REQUIREMENTS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C ≤ TA ≤ +85°C for Industrial
-40°C ≤ TA ≤ +125°C for Extended
AC CHARACTERISTICS
Param
Symbol
No.
Characteristic(1)
Min
Typ
Max
Units
Conditions
OC10 TccF
OC11 TccR
OCx Output Fall Time
OCx Output Rise Time
—
—
—
—
—
—
ns
ns
See parameter D032
See parameter D031
Note 1: These parameters are characterized but not tested in manufacturing.
DS70592A-page 254
Preliminary
© 2009 Microchip Technology Inc.
PIC24HJXXXGPX06A/X08A/X10A
FIGURE 24-8:
OCFA
OC/PWM MODULE TIMING CHARACTERISTICS
OC20
OC15
OCx
TABLE 24-27: SIMPLE OC/PWM MODE TIMING REQUIREMENTS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C ≤ TA ≤ +85°C for Industrial
-40°C ≤ TA ≤ +125°C for Extended
AC CHARACTERISTICS
Param
Symbol
No.
Characteristic(1)
Min
Typ
Max
Units
Conditions
OC15
TFD
Fault Input to PWM I/O
Change
—
—
50
ns
—
OC20
TFLT
Fault Input Pulse-Width
50
—
—
ns
—
Note 1: These parameters are characterized but not tested in manufacturing.
© 2009 Microchip Technology Inc.
Preliminary
DS70592A-page 255
PIC24HJXXXGPX06A/X08A/X10A
FIGURE 24-9:
SPIx MODULE MASTER MODE (CKE = 0) TIMING CHARACTERISTICS
SCKx
(CKP = 0)
SP11
SP10
SP21
SP20
SP20
SCKx
(CKP = 1)
SP35
SP31
SP21
LSb
Bit 14 - - - - - -1
MSb
SDOx
SDIx
SP30
MSb In
SP40
LSb In
Bit 14 - - - -1
SP41
Note: Refer to Figure 24-1 for load conditions.
TABLE 24-28: SPIx MASTER MODE (CKE = 0) TIMING REQUIREMENTS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C ≤ TA ≤ +85°C for Industrial
-40°C ≤ TA ≤ +125°C for Extended
AC CHARACTERISTICS
Param
Symbol
No.
Characteristic(1)
Min
Typ(2)
Max
Units
Conditions
See Note 3
SP10
SP11
SP20
TscL
TscH
TscF
SCKx Output Low Time
SCKx Output High Time
SCKx Output Fall Time
TCY/2
TCY/2
—
—
—
—
—
—
—
ns
ns
ns
See Note 3
See parameter D032
and Note 4
SP21
SP30
SP31
SP35
SP40
SP41
TscR
TdoF
TdoR
SCKx Output Rise Time
—
—
—
—
23
30
—
—
—
6
—
—
—
20
—
—
ns
ns
ns
ns
ns
ns
See parameter D031
and Note 4
SDOx Data Output Fall Time
SDOx Data Output Rise Time
See parameter D032
and Note 4
See parameter D031
and Note 4
TscH2doV, SDOx Data Output Valid after
TscL2doV SCKx Edge
—
—
—
TdiV2scH, Setup Time of SDIx Data Input
—
—
TdiV2scL
TscH2diL, Hold Time of SDIx Data Input
TscL2diL to SCKx Edge
to SCKx Edge
Note 1: These parameters are characterized but not tested in manufacturing.
2: Data in “Typ” column is at 3.3V, 25°C unless otherwise stated.
3: The minimum clock period for SCKx is 100 ns. Therefore, the clock generated in Master mode must not
violate this specification.
4: Assumes 50 pF load on all SPIx pins.
DS70592A-page 256
Preliminary
© 2009 Microchip Technology Inc.
PIC24HJXXXGPX06A/X08A/X10A
FIGURE 24-10:
SPIx MODULE MASTER MODE (CKE = 1) TIMING CHARACTERISTICS
SP36
SCKX
(CKP = 0)
SP11
SP10
SP21
SP20
SP21
SCKX
(CKP = 1)
SP35
SP20
LSb
MSb
SP40
Bit 14 - - - - - -1
SDOX
SDIX
SP30,SP31
Bit 14 - - - -1
MSb In
SP41
LSb In
Note: Refer to Figure 24-1 for load conditions.
TABLE 24-29: SPIx MODULE MASTER MODE (CKE = 1) TIMING REQUIREMENTS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
AC CHARACTERISTICS
Operating temperature -40°C ≤ TA ≤ +85°C for Industrial
-40°C ≤ TA ≤ +125°C for Extended
Param
No.
Symbol
TscL
Characteristic(1)
Min
Typ(2)
Max
Units
Conditions
SP10
SP11
SP20
SP21
SP30
SCKx Output Low Time(3)
SCKx Output High Time(3)
SCKx Output Fall Time(4)
SCKx Output Rise Time(4)
TCY/2
TCY/2
—
—
—
—
—
—
—
—
—
—
—
ns
ns
ns
ns
ns
—
TscH
TscF
TscR
TdoF
—
See parameter D032
See parameter D031
See parameter D032
—
SDOx Data Output Fall
Time(4)
—
SP31
SP35
SP36
SP40
SP41
TdoR
SDOx Data Output Rise
Time(4)
—
—
30
23
30
—
6
—
20
—
—
—
ns
ns
ns
ns
ns
See parameter D031
TscH2doV, SDOx Data Output Valid after
TscL2doV SCKx Edge
—
—
—
—
TdoV2sc, SDOx Data Output Setup to
TdoV2scL First SCKx Edge
—
—
—
TdiV2scH, Setup Time of SDIx Data
TdiV2scL Input to SCKx Edge
TscH2diL, Hold Time of SDIx Data Input
TscL2diL
to SCKx Edge
Note 1: These parameters are characterized but not tested in manufacturing.
2: Data in “Typ” column is at 3.3V, 25°C unless otherwise stated.
3: The minimum clock period for SCKx is 100 ns. The clock generated in Master mode must not violate this
specification.
4: Assumes 50 pF load on all SPIx pins.
© 2009 Microchip Technology Inc.
Preliminary
DS70592A-page 257
PIC24HJXXXGPX06A/X08A/X10A
FIGURE 24-11:
SPIx MODULE SLAVE MODE (CKE = 0) TIMING CHARACTERISTICS
SSX
SP52
SP50
SCKX
(CKP = 0)
SP71
SP70
SP72
SP73
SP72
SCKX
(CKP = 1)
SP73
LSb
SP35
MSb
Bit 14 - - - - - -1
SDOX
SDIX
SP51
SP30,SP31
Bit 14 - - - -1
MSb In
SP41
LSb In
SP40
Note: Refer to Figure 24-1 for load conditions.
TABLE 24-30: SPIx MODULE SLAVE MODE (CKE = 0) TIMING REQUIREMENTS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
AC CHARACTERISTICS
Operating temperature -40°C ≤ TA ≤ +85°C for Industrial
-40°C ≤ TA ≤ +125°C for Extended
Param
No.
Symbol
Characteristic(1)
Min
Typ(2) Max Units
Conditions
SP70 TscL
SP71 TscH
SP72 TscF
SP73 TscR
SP30 TdoF
SP31 TdoR
SCKx Input Low Time
30
30
—
—
—
—
—
—
—
10
10
—
—
—
—
—
25
25
—
—
30
ns
ns
ns
ns
ns
ns
ns
—
SCKx Input High Time
—
SCKx Input Fall Time(3)
SCKx Input Rise Time(3)
SDOx Data Output Fall Time(3)
SDOx Data Output Rise Time(3)
—
—
See parameter D032
See parameter D031
—
SP35 TscH2doV, SDOx Data Output Valid after
TscL2doV SCKx Edge
SP40 TdiV2scH, Setup Time of SDIx Data Input
TdiV2scL to SCKx Edge
20
—
—
—
—
—
—
—
—
50
—
ns
ns
ns
ns
ns
—
—
—
—
—
SP41 TscH2diL, Hold Time of SDIx Data Input
20
120
TscL2diL
to SCKx Edge
SP50 TssL2scH, SSx ↓ to SCKx ↑ or SCKx Input
TssL2scL
SP51 TssH2doZ SSx ↑ to SDOx Output
10
High-Impedance(3)
SP52
TscH2ssH SSx after SCKx Edge
TscL2ssH
1.5 TCY + 40
Note 1: These parameters are characterized but not tested in manufacturing.
2: Data in “Typ” column is at 3.3V, 25°C unless otherwise stated.
3: Assumes 50 pF load on all SPIx pins.
DS70592A-page 258
Preliminary
© 2009 Microchip Technology Inc.
PIC24HJXXXGPX06A/X08A/X10A
FIGURE 24-12:
SPIx MODULE SLAVE MODE (CKE = 1) TIMING CHARACTERISTICS
SP60
SSx
SP52
SP50
SCKx
(CKP = 0)
SP71
SP70
SP72
SP73
SP73
SCKx
(CKP = 1)
SP35
SP72
LSb
SP52
Bit 14 - - - - - -1
MSb
SDOx
SDIx
SP30,SP31
Bit 14 - - - -1
SP51
MSb In
SP41
LSb In
SP40
Note: Refer to Figure 24-1 for load conditions.
© 2009 Microchip Technology Inc.
Preliminary
DS70592A-page 259
PIC24HJXXXGPX06A/X08A/X10A
TABLE 24-31: SPIx MODULE SLAVE MODE (CKE = 1) TIMING REQUIREMENTS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
AC CHARACTERISTICS
Operating temperature -40°C ≤ TA ≤ +85°C for Industrial
-40°C ≤ TA ≤ +125°C for Extended
Param
No.
Symbol
TscL
Characteristic(1)
Min
Typ(2)
Max
Units
Conditions
SP70
SP71
SP72
SP73
SP30
SP31
SP35
SCKx Input Low Time
30
30
—
—
—
—
—
—
—
10
10
—
—
—
—
—
25
25
—
—
30
ns
ns
ns
ns
ns
ns
ns
—
TscH
TscF
TscR
TdoF
TdoR
SCKx Input High Time
—
SCKx Input Fall Time(3)
SCKx Input Rise Time(3)
SDOx Data Output Fall Time(3)
SDOx Data Output Rise Time(3)
—
—
See parameter D032
See parameter D031
—
TscH2doV, SDOx Data Output Valid after
TscL2doV SCKx Edge
SP40
SP41
SP50
SP51
SP52
SP60
TdiV2scH, Setup Time of SDIx Data Input
TdiV2scL to SCKx Edge
20
—
—
—
—
—
—
—
—
—
50
—
50
ns
ns
ns
ns
ns
ns
—
—
—
—
—
—
TscH2diL, Hold Time of SDIx Data Input
TscL2diL to SCKx Edge
20
TssL2scH, SSx ↓ to SCKx ↓ or SCKx ↑
TssL2scL Input
120
TssH2doZ SSx ↑ to SDOX Output
10
1.5 TCY + 40
—
High-Impedance(4)
TscH2ssH SSx ↑ after SCKx Edge
TscL2ssH
TssL2doV SDOx Data Output Valid after
SSx Edge
Note 1: These parameters are characterized but not tested in manufacturing.
2: Data in “Typ” column is at 3.3V, 25°C unless otherwise stated.
3: The minimum clock period for SCKx is 100 ns. The clock generated in Master mode must not violate this
specification.
4: Assumes 50 pF load on all SPIx pins.
DS70592A-page 260
Preliminary
© 2009 Microchip Technology Inc.
PIC24HJXXXGPX06A/X08A/X10A
FIGURE 24-13:
I2Cx BUS START/STOP BITS TIMING CHARACTERISTICS (MASTER MODE)
SCLx
IM31
IM34
IM30
IM33
SDAx
Stop
Condition
Start
Condition
Note: Refer to Figure 24-1 for load conditions.
FIGURE 24-14:
I2Cx BUS DATA TIMING CHARACTERISTICS (MASTER MODE)
IM20
IM21
IM11
IM10
SCLx
IM11
IM26
IM10
IM33
IM25
SDAx
In
IM45
IM40
IM40
SDAx
Out
Note: Refer to Figure 24-1 for load conditions.
© 2009 Microchip Technology Inc.
Preliminary
DS70592A-page 261
PIC24HJXXXGPX06A/X08A/X10A
TABLE 24-32: I2Cx BUS DATA TIMING REQUIREMENTS (MASTER MODE)
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C ≤ TA ≤ +85°C for Industrial
-40°C ≤ TA ≤ +125°C for Extended
AC CHARACTERISTICS
Param
Symbol
No.
Characteristic
Min(1)
Max
Units
Conditions
IM10
IM11
IM20
IM21
IM25
IM26
IM30
IM31
IM33
IM34
IM40
IM45
IM50
TLO:SCL Clock Low Time 100 kHz mode TCY/2 (BRG + 1)
400 kHz mode TCY/2 (BRG + 1)
—
—
μs
μs
μs
μs
μs
μs
ns
ns
ns
ns
ns
ns
ns
ns
ns
μs
μs
μs
μs
μs
μs
μs
μs
μs
μs
μs
μs
ns
ns
ns
ns
ns
ns
μs
μs
μs
pF
—
—
—
—
—
—
1 MHz mode(2) TCY/2 (BRG + 1)
—
THI:SCL Clock High Time 100 kHz mode TCY/2 (BRG + 1)
—
400 kHz mode TCY/2 (BRG + 1)
1 MHz mode(2) TCY/2 (BRG + 1)
—
—
TF:SCL
TR:SCL
SDAx and SCLx 100 kHz mode
—
300
300
100
1000
300
300
—
CB is specified to be
from 10 to 400 pF
Fall Time
400 kHz mode
20 + 0.1 CB
1 MHz mode(2)
—
SDAx and SCLx 100 kHz mode
—
CB is specified to be
from 10 to 400 pF
Rise Time
400 kHz mode
20 + 0.1 CB
1 MHz mode(2)
—
250
100
40
0
TSU:DAT Data Input
Setup Time
100 kHz mode
400 kHz mode
1 MHz mode(2)
100 kHz mode
400 kHz mode
1 MHz mode(2)
—
—
—
—
THD:DAT Data Input
Hold Time
—
0
0.9
—
0.2
TSU:STA Start Condition 100 kHz mode TCY/2 (BRG + 1)
—
Only relevant for
Repeated Start
condition
Setup Time
400 kHz mode TCY/2 (BRG + 1)
—
1 MHz mode(2) TCY/2 (BRG + 1)
—
THD:STA Start Condition 100 kHz mode TCY/2 (BRG + 1)
—
After this period the
first clock pulse is
generated
Hold Time
400 kHz mode TCY/2 (BRG + 1)
—
1 MHz mode(2) TCY/2 (BRG + 1)
—
TSU:STO Stop Condition 100 kHz mode TCY/2 (BRG + 1)
—
—
Setup Time
400 kHz mode TCY/2 (BRG + 1)
—
1 MHz mode(2) TCY/2 (BRG + 1)
—
THD:STO Stop Condition
Hold Time
100 kHz mode TCY/2 (BRG + 1)
400 kHz mode TCY/2 (BRG + 1)
1 MHz mode(2) TCY/2 (BRG + 1)
—
—
—
—
TAA:SCL Output Valid
From Clock
100 kHz mode
400 kHz mode
1 MHz mode(2)
—
—
3500
1000
400
—
—
—
—
—
TBF:SDA Bus Free Time 100 kHz mode
4.7
1.3
0.5
—
Time the bus must be
free before a new
transmission can start
400 kHz mode
1 MHz mode(2)
—
—
CB
Bus Capacitive Loading
400
—
Note 1: BRG is the value of the I2C Baud Rate Generator. Refer to Section 19. “Inter-Integrated Circuit™
(I2C™)” (DS70235) in the “PIC24H Family Reference Manual”. Please see the Microchip website
(www.microchip.com) for the latest PIC24H Family Reference Manual chapters.
2: Maximum pin capacitance = 10 pF for all I2Cx pins (for 1 MHz mode only).
DS70592A-page 262
Preliminary
© 2009 Microchip Technology Inc.
PIC24HJXXXGPX06A/X08A/X10A
FIGURE 24-15:
I2Cx BUS START/STOP BITS TIMING CHARACTERISTICS (SLAVE MODE)
SCLx
IS34
IS31
IS30
IS33
SDAx
Stop
Condition
Start
Condition
FIGURE 24-16:
I2Cx BUS DATA TIMING CHARACTERISTICS (SLAVE MODE)
IS20
IS21
IS11
IS10
SCLx
IS30
IS26
IS31
IS33
IS25
SDAx
In
IS45
IS40
IS40
SDAx
Out
© 2009 Microchip Technology Inc.
Preliminary
DS70592A-page 263
PIC24HJXXXGPX06A/X08A/X10A
TABLE 24-33: I2Cx BUS DATA TIMING REQUIREMENTS (SLAVE MODE)
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C ≤ TA ≤ +85°C for Industrial
-40°C ≤ TA ≤ +125°C for Extended
AC CHARACTERISTICS
Param
Symbol
.
Characteristic
Min
Max
Units
Conditions
IS10
IS11
TLO:SCL Clock Low Time 100 kHz mode
400 kHz mode
4.7
—
μs
Device must operate at a
minimum of 1.5 MHz
1.3
—
μs
Device must operate at a
minimum of 10 MHz
1 MHz mode(1)
0.5
4.0
—
—
μs
μs
—
THI:SCL Clock High Time 100 kHz mode
Device must operate at a
minimum of 1.5 MHz
400 kHz mode
1 MHz mode(1)
0.6
—
μs
Device must operate at a
minimum of 10 MHz
0.5
—
300
300
100
1000
300
300
—
μs
ns
ns
ns
ns
ns
ns
ns
ns
ns
μs
μs
μs
μs
μs
μs
μs
μs
μs
μs
μs
μs
ns
ns
ns
ns
ns
ns
μs
μs
μs
pF
—
IS20
IS21
IS25
IS26
IS30
IS31
IS33
IS34
IS40
IS45
IS50
TF:SCL
TR:SCL
SDAx and SCLx 100 kHz mode
—
CB is specified to be from
10 to 400 pF
Fall Time
400 kHz mode
1 MHz mode(1)
20 + 0.1 CB
—
—
SDAx and SCLx 100 kHz mode
CB is specified to be from
10 to 400 pF
Rise Time
400 kHz mode
1 MHz mode(1)
20 + 0.1 CB
—
TSU:DAT Data Input
Setup Time
100 kHz mode
400 kHz mode
1 MHz mode(1)
100 kHz mode
400 kHz mode
1 MHz mode(1)
100 kHz mode
400 kHz mode
1 MHz mode(1)
100 kHz mode
400 kHz mode
1 MHz mode(1)
100 kHz mode
400 kHz mode
1 MHz mode(1)
100 kHz mode
400 kHz mode
1 MHz mode(1)
100 kHz mode
400 kHz mode
1 MHz mode(1)
100 kHz mode
400 kHz mode
1 MHz mode(1)
250
100
100
0
—
—
—
—
THD:DAT Data Input
Hold Time
—
0
0.9
0.3
—
0
TSU:STA Start Condition
Setup Time
4.7
0.6
0.25
4.0
0.6
0.25
4.7
0.6
0.6
4000
600
250
0
Only relevant for Repeated
Start condition
—
—
THD:STA Start Condition
Hold Time
—
After this period, the first
clock pulse is generated
—
—
TSU:STO Stop Condition
Setup Time
—
—
—
—
—
—
THD:STO Stop Condition
Hold Time
—
—
TAA:SCL Output Valid
From Clock
3500
1000
350
—
0
0
TBF:SDA Bus Free Time
4.7
1.3
0.5
—
Time the bus must be free
before a new transmission
can start
—
—
CB
Bus Capacitive Loading
400
—
Note 1: Maximum pin capacitance = 10 pF for all I2Cx pins (for 1 MHz mode only).
DS70592A-page 264
Preliminary
© 2009 Microchip Technology Inc.
PIC24HJXXXGPX06A/X08A/X10A
FIGURE 24-17:
ECAN™ MODULE I/O TIMING CHARACTERISTICS
CiTx Pin
(output)
New Value
Old Value
CA10 CA11
CA20
CiRx Pin
(input)
TABLE 24-34: ECAN™ MODULE I/O TIMING REQUIREMENTS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C ≤ TA ≤ +85°C for Industrial
-40°C ≤ TA ≤ +125°C for Extended
AC CHARACTERISTICS
Param
Symbol
No.
Characteristic(1)
Min
Typ(2)
Max
Units
Conditions
CA10
CA11
CA20
TioF
TioR
Tcwf
Port Output Fall Time
Port Output Rise Time
—
—
—
—
—
—
—
—
ns
ns
ns
See parameter D032
See parameter D031
—
Pulse-Width to Trigger
CAN Wake-up Filter
120
Note 1: These parameters are characterized but not tested in manufacturing.
2: Data in “Typ” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only
and are not tested.
© 2009 Microchip Technology Inc.
Preliminary
DS70592A-page 265
PIC24HJXXXGPX06A/X08A/X10A
TABLE 24-35: ADC MODULE SPECIFICATIONS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
AC CHARACTERISTICS
Operating temperature -40°C ≤ TA ≤ +85°C for Industrial
-40°C ≤ TA ≤ +125°C for Extended
Param Symbo
Characteristic
Module VDD Supply
Module VSS Supply
Min.
Typ
Max.
Units
Conditions
No.
l
Device Supply
AD01 AVDD
AD02 AVSS
Greater of
VDD – 0.3
or 3.0
—
—
Lesser of
VDD + 0.3
or 3.6
V
V
—
—
VSS – 0.3
VSS + 0.3
Reference Inputs
AD05 VREFH Reference Voltage High
AD05a
AVSS + 2.7
—
—
AVDD
3.6
V
V
See Note 1
3.0
VREFH = AVDD
VREFL = AVSS = 0
AD06 VREFL
AD06a
Reference Voltage Low
AVSS
0
—
—
AVDD – 2.7
0
V
V
See Note 1
VREFH = AVDD
VREFL = AVSS = 0
AD07 VREF
Absolute Reference
Voltage
2.7
—
—
—
3.6
10
V
VREF = VREFH - VREFL
AD08 IREF
AD08a IAD
Current Drain
μA ADC off
Operating Current
—
—
7.0
2.7
9.0
3.2
mA 10-bit ADC mode, See Note 1
mA 12-bit ADC mode, See Note 1
Analog Input
AD12 VINH
AD13 VINL
AD17 RIN
Input Voltage Range VINH
Input Voltage Range VINL
VINL
—
VREFH
V
This voltage reflects Sample
and Hold Channels 0, 1, 2,
and 3 (CH0-CH3), positive
input
VREFL
—
AVSS + 1V
V
This voltage reflects Sample
and Hold Channels 0, 1, 2,
and 3 (CH0-CH3), negative
input
Recommended Imped-
ance of Analog Voltage
Source
—
—
—
—
200
200
Ω
Ω
10-bit ADC
12-bit ADC
Note 1: These parameters are not characterized or tested in manufacturing.
DS70592A-page 266
Preliminary
© 2009 Microchip Technology Inc.
PIC24HJXXXGPX06A/X08A/X10A
TABLE 24-36: ADC MODULE SPECIFICATIONS (12-BIT MODE)
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C ≤ TA ≤ +85°C for Industrial
-40°C ≤ TA ≤ +125°C for Extended
AC CHARACTERISTICS
Param
Symbol
No.
Characteristic
Min.
Typ
Max. Units
Conditions
ADC Accuracy (12-bit Mode) – Measurements with external VREF+/VREF-
AD20a Nr
AD21a INL
Resolution
12 data bits
—
bits
Integral Nonlinearity
-2
+2
<1
3
LSb VINL = AVSS = VREFL = 0V,
AVDD = VREFH = 3.6V
AD22a DNL
Differential Nonlinearity
Gain Error
>-1
1.25
1.25
—
—
1.5
1.52
—
LSb VINL = AVSS = VREFL = 0V,
AVDD = VREFH = 3.6V
AD23a
AD24a
AD25a
GERR
EOFF
—
LSb VINL = AVSS = VREFL = 0V,
AVDD = VREFH = 3.6V
Offset Error
2
LSb VINL = AVSS = VREFL = 0V,
AVDD = VREFH = 3.6V
Monotonicity
—
—
Guaranteed
ADC Accuracy (12-bit Mode) – Measurements with internal VREF+/VREF-
AD20a Nr
AD21a INL
AD22a DNL
Resolution
12 data bits
bits
Integral Nonlinearity
Differential Nonlinearity
Gain Error
-2
>-1
2
—
—
3
+2
<1
7
LSb VINL = AVSS = 0V, AVDD = 3.6V
LSb VINL = AVSS = 0V, AVDD = 3.6V
LSb VINL = AVSS = 0V, AVDD = 3.6V
LSb VINL = AVSS = 0V, AVDD = 3.6V
AD23a
AD24a
AD25a
GERR
EOFF
—
Offset Error
2
3
5
Monotonicity
—
—
—
—
Guaranteed
Dynamic Performance (12-bit Mode)
AD30a THD
Total Harmonic Distortion
—
—
-75
—
dB
dB
—
—
AD31a SINAD
Signal to Noise and
Distortion
68.5
69.5
AD32a SFDR
Spurious Free Dynamic
Range
80
—
—
dB
—
AD33a
FNYQ
Input Signal Bandwidth
Effective Number of Bits
—
—
250
—
kHz
bits
—
—
AD34a ENOB
11.09
11.3
© 2009 Microchip Technology Inc.
Preliminary
DS70592A-page 267
PIC24HJXXXGPX06A/X08A/X10A
TABLE 24-37: ADC MODULE SPECIFICATIONS (10-BIT MODE)
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C ≤ TA ≤ +85°C for Industrial
-40°C ≤ TA ≤ +125°C for Extended
AC CHARACTERISTICS
Param
Symbol
No.
Characteristic
Min.
Typ
Max. Units
Conditions
ADC Accuracy (10-bit Mode) – Measurements with external VREF+/VREF-
AD20b Nr
AD21b INL
Resolution
10 data bits
—
bits
Integral Nonlinearity
-1.5
>-1
1
+1.5
<1
6
LSb VINL = AVSS = VREFL = 0V,
AVDD = VREFH = 3.6V
AD22b DNL
Differential Nonlinearity
Gain Error
—
3
LSb VINL = AVSS = VREFL = 0V,
AVDD = VREFH = 3.6V
AD23b
AD24b
AD25b
GERR
EOFF
—
LSb VINL = AVSS = VREFL = 0V,
AVDD = VREFH = 3.6V
Offset Error
1
2
5
LSb VINL = AVSS = VREFL = 0V,
AVDD = VREFH = 3.6V
Monotonicity
—
—
—
—
Guaranteed
ADC Accuracy (10-bit Mode) – Measurements with internal VREF+/VREF-
AD20b Nr
AD21b INL
AD22b DNL
Resolution
10 data bits
bits
Integral Nonlinearity
Differential Nonlinearity
Gain Error
-1
>-1
1
—
—
5
+1
<1
6
LSb VINL = AVSS = 0V, AVDD = 3.6V
LSb VINL = AVSS = 0V, AVDD = 3.6V
LSb VINL = AVSS = 0V, AVDD = 3.6V
LSb VINL = AVSS = 0V, AVDD = 3.6V
AD23b
AD24b
AD25b
GERR
EOFF
—
Offset Error
1
2
3
Monotonicity
—
—
—
—
Guaranteed
Dynamic Performance (10-bit Mode)
AD30b THD
Total Harmonic Distortion
—
—
-64
—
dB
dB
—
—
AD31b SINAD
Signal to Noise and
Distortion
57
58.5
AD32b SFDR
Spurious Free Dynamic
Range
72
—
—
dB
—
AD33b
FNYQ
Input Signal Bandwidth
Effective Number of Bits
—
—
550
—
kHz
bits
—
—
AD34b ENOB
9.16
9.4
DS70592A-page 268
Preliminary
© 2009 Microchip Technology Inc.
PIC24HJXXXGPX06A/X08A/X10A
FIGURE 24-18:
ADC CONVERSION (12-BIT MODE) TIMING CHARACTERISTICS
(ASAM = 0, SSRC<2:0> = 000)
AD50
ADCLK
Instruction
Execution
Set SAMP
AD61
Clear SAMP
SAMP
AD60
TSAMP
AD55
DONE
AD1IF
1
2
3
4
5
6
7
8
9
Software sets AD1CON. SAMP to start sampling.
Sampling ends, conversion sequence starts.
Convert bit 11.
1
2
4
5
6
7
8
9
Sampling starts after discharge period. TSAMP is described in
Section 28. “Analog-to-Digital Converter (ADC) without DMA”
(DS70249) in the “PIC24H Family Reference Manual”.
Please see the Microchip web site (www.microchip.com)
for the latest PIC24H Family Reference Manual sections.
Convert bit 10.
Convert bit 1.
Convert bit 0.
Software clears AD1CON. SAMP to start conversion.
3
One TAD for end of conversion.
© 2009 Microchip Technology Inc.
Preliminary
DS70592A-page 269
PIC24HJXXXGPX06A/X08A/X10A
TABLE 24-38: ADC CONVERSION (12-BIT MODE) TIMING REQUIREMENTS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C ≤ TA ≤ +85°C for Industrial
-40°C ≤ TA ≤ +125°C for Extended
AC CHARACTERISTICS
Param
Symbol
No.
Characteristic
Min.
Typ(2) Max.
Units
Conditions
Clock Parameters(1)
AD50
AD51
TAD
tRC
ADC Clock Period
117.6
—
—
—
—
ns
ns
—
—
ADC Internal RC Oscillator
Period
250
Conversion Rate
AD55
AD56
AD57
tCONV
FCNV
Conversion Time
Throughput Rate
Sample Time
—
—
14 TAD
ns
ksps
—
—
—
—
—
—
500
—
TSAMP
3 TAD
Timing Parameters
AD60
tPCS
2.0 TAD
—
3.0 TAD
—
Auto convert trigger not
selected
Conversion Start from Sample
Trigger(2)
AD61
AD62
AD63
tPSS
tCSS
tDPU
Sample Start from Setting
Sample (SAMP) bit(2)
2.0 TAD
—
—
0.5 TAD
—
3.0 TAD
—
—
—
μs
—
—
—
Conversion Completion to
Sample Start (ASAM = 1)(2)
Time to Stabilize Analog Stage
from ADC Off to ADC On(2,3)
—
20
Note 1: Because the sample caps eventually loses charge, clock rates below 10 kHz may affect linearity
performance, especially at elevated temperatures.
2: These parameters are characterized but not tested in manufacturing.
3: tDPU is the time required for the ADC module to stabilize when it is turned on (AD1CON1<ADON> = 1).
During this time, the ADC result is indeterminate.
DS70592A-page 270
Preliminary
© 2009 Microchip Technology Inc.
PIC24HJXXXGPX06A/X08A/X10A
FIGURE 24-19:
ADC CONVERSION (10-BIT MODE) TIMING CHARACTERISTICS
(CHPS<1:0> = 01, SIMSAM = 0, ASAM = 0, SSRC<2:0> = 000)
AD50
Set SAMP
AD61
ADCLK
Instruction
Execution
Clear SAMP
AD60
SAMP
TSAMP
AD55
AD55
DONE
AD1IF
1
2
3
4
5
6
7
8
5
6
7
8
– Software sets AD1CON. SAMP to start sampling.
1
2
– Sampling starts after discharge period. TSAMP is described in Section 28. “Analog-to-Digital Converter (ADC)
without DMA” (DS70249) in the “PIC24H Family Reference Manual”.
– Software clears AD1CON. SAMP to start conversion.
– Sampling ends, conversion sequence starts.
– Convert bit 9.
3
4
5
6
7
8
– Convert bit 8.
– Convert bit 0.
– One TAD for end of conversion.
FIGURE 24-20:
ADC CONVERSION (10-BIT MODE) TIMING CHARACTERISTICS (CHPS<1:0> = 01,
SIMSAM = 0, ASAM = 1, SSRC<2:0> = 111, SAMC<4:0> = 00001)
AD50
ADCLK
Instruction
Set ADON
Execution
SAMP
AD1IF
TSAMP
TSAMP
AD55
AD55
AD55
DONE
1
2
3
4
5
6
7
3
4
5
6
8
– Software sets AD1CON. ADON to start AD operation.
– Convert bit 0.
5
1
2
– Sampling starts after discharge period. TSAMP is described in
Section 28. “Analog-to-Digital Converter (ADC) without DMA”
(DS70249) in the “PIC24H Family Reference Manual'.
– One TAD for end of conversion.
– Begin conversion of next channel.
6
7
8
– Convert bit 9.
3
4
– Sample for time specified by SAMC<4:0>.
– Convert bit 8.
© 2009 Microchip Technology Inc.
Preliminary
DS70592A-page 271
PIC24HJXXXGPX06A/X08A/X10A
TABLE 24-39: ADC CONVERSION (10-BIT MODE) TIMING REQUIREMENTS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C ≤ TA ≤ +85°C for Industrial
-40°C ≤ TA ≤ +125°C for Extended
AC CHARACTERISTICS
Param
Symbol
No.
Characteristic
Min.
Typ(1)
Max.
Units
Conditions
Clock Parameters
AD50 TAD
AD51 tRC
ADC Clock Period
76
—
—
—
—
ns
ns
—
—
ADC Internal RC Oscillator Period
250
Conversion Rate
AD55 tCONV
AD56 FCNV
Conversion Time
Throughput Rate
—
—
12 TAD
—
1.1
—
—
Msps
—
—
—
—
—
—
AD57 TSAMP Sample Time
2 TAD
Timing Parameters
AD60 tPCS
AD61 tPSS
AD62 tCSS
AD63 tDPU
Conversion Start from Sample
2.0 TAD
2.0 TAD
—
—
3.0 TAD
3.0 TAD
—
—
—
—
μs
Auto-Convert Trigger
not selected
Trigger(2)
Sample Start from Setting
Sample (SAMP) bit(2)
—
0.5 TAD
—
—
—
—
Conversion Completion to
Sample Start (ASAM = 1)(2)
Time to Stabilize Analog Stage
from ADC Off to ADC On(2,3)
—
20
Note 1: These parameters are characterized but not tested in manufacturing.
2: Because the sample caps eventually loses charge, clock rates below 10 kHz may affect linearity
performance, especially at elevated temperatures.
3: tDPU is the time required for the ADC module to stabilize when it is turned on (AD1CON1<ADON> = 1).
During this time, the ADC result is indeterminate.
DS70592A-page 272
Preliminary
© 2009 Microchip Technology Inc.
PIC24HJXXXGPX06A/X08A/X10A
25.0 PACKAGING INFORMATION
25.1 Package Marking Information
64-Lead QFN (9x9x0.9mm)
Example
XXXXXXXXXX
XXXXXXXXXX
24HJ64GP
206A-I/MR
e
3
YYWWNNN
0610017
64-Lead TQFP (10x10x1 mm)
Example
XXXXXXXXXX
XXXXXXXXXX
XXXXXXXXXX
YYWWNNN
PIC24HJ
256GP706A
e
3
-I/PT
0510017
100-Lead TQFP (12x12x1 mm)
Example
XXXXXXXXXXXX
XXXXXXXXXXXX
YYWWNNN
PIC24HJ256
GP710A-I/PT
0510017
e
3
100-Lead TQFP (14x14x1 mm)
Example
XXXXXXXXXXXX
XXXXXXXXXXXX
YYWWNNN
PIC24HJ256
GP710A-I/PF
0510017
e
3
Legend: XX...X Customer-specific information
Y
YY
WW
NNN
Year code (last digit of calendar year)
Year code (last 2 digits of calendar year)
Week code (week of January 1 is week ‘01’)
Alphanumeric traceability code
e
3
Pb-free JEDEC designator for Matte Tin (Sn)
*
This package is Pb-free. The Pb-free JEDEC designator (
can be found on the outer packaging for this package.
)
e3
Note: In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
© 2009 Microchip Technology Inc.
Preliminary
DS70592A-page 273
PIC24HJXXXGPX06A/X08A/X10A
25.2 Package Details
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
DS70592A-page 274
Preliminary
© 2009 Microchip Technology Inc.
PIC24HJXXXGPX06A/X08A/X10A
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
© 2009 Microchip Technology Inc.
Preliminary
DS70592A-page 275
PIC24HJXXXGPX06A/X08A/X10A
64-Lead Plastic Thin Quad Flatpack (PT) – 10x10x1 mm Body, 2.00 mm Footprint [TQFP]
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
D
D1
E
e
E1
N
b
NOTE 1
1 2 3
NOTE 2
α
A
c
φ
A2
A1
β
L
L1
Units
MILLIMETERS
Dimension Limits
MIN
NOM
64
0.50 BSC
–
1.00
–
MAX
Number of Leads
Lead Pitch
Overall Height
Molded Package Thickness
Standoff
N
e
A
A2
A1
L
–
1.20
1.05
0.15
0.75
0.95
0.05
0.45
Foot Length
0.60
Footprint
Foot Angle
L1
φ
1.00 REF
3.5°
0°
7°
Overall Width
E
D
E1
D1
c
12.00 BSC
12.00 BSC
10.00 BSC
10.00 BSC
–
Overall Length
Molded Package Width
Molded Package Length
Lead Thickness
Lead Width
0.09
0.17
11°
0.20
0.27
13°
b
α
0.22
12°
12°
Mold Draft Angle Top
Mold Draft Angle Bottom
β
11°
13°
Notes:
1. Pin 1 visual index feature may vary, but must be located within the hatched area.
2. Chamfers at corners are optional; size may vary.
3. Dimensions D1 and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.25 mm per side.
4. Dimensioning and tolerancing per ASME Y14.5M.
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
REF: Reference Dimension, usually without tolerance, for information purposes only.
Microchip Technology Drawing C04-085B
DS70592A-page 276
Preliminary
© 2009 Microchip Technology Inc.
PIC24HJXXXGPX06A/X08A/X10A
ꢀꢁꢂꢃꢄꢅꢆꢇꢈꢉꢅꢊꢋꢌꢍꢇꢎꢏꢌꢐꢇꢑꢒꢅꢆꢇꢓꢉꢅꢋꢔꢅꢍꢕꢇꢖꢈꢎꢗꢇMꢇꢘꢙꢚꢘꢙꢚꢘꢇꢛꢛꢇꢜ ꢆ!"ꢇ#$ꢙꢙꢇꢛꢛꢇ%ꢎꢑꢓꢈ&
' ꢋꢄ( ꢀꢁꢂ!ꢃꢄꢂ"ꢀ#!ꢂꢅ$ꢁꢁꢄꢆ!ꢂꢇꢈꢅ%ꢈꢉꢄꢂ&ꢁꢈ'ꢊꢆꢉ#(ꢂꢇꢋꢄꢈ#ꢄꢂ#ꢄꢄꢂ!ꢃꢄꢂꢌꢊꢅꢁꢀꢅꢃꢊꢇꢂ)ꢈꢅ%ꢈꢉꢊꢆꢉꢂꢍꢇꢄꢅꢊ*ꢊꢅꢈ!ꢊꢀꢆꢂꢋꢀꢅꢈ!ꢄ&ꢂꢈ!ꢂ
ꢃ!!ꢇ+,,'''ꢎ"ꢊꢅꢁꢀꢅꢃꢊꢇꢎꢅꢀ",ꢇꢈꢅ%ꢈꢉꢊꢆꢉ
© 2009 Microchip Technology Inc.
Preliminary
DS70592A-page 277
PIC24HJXXXGPX06A/X08A/X10A
100-Lead Plastic Thin Quad Flatpack (PT) – 12x12x1 mm Body, 2.00 mm Footprint [TQFP]
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
D
D1
e
E
E1
N
b
123
NOTE 2
NOTE 1
c
α
A
φ
L
A1
β
A2
L1
Units
Dimension Limits
MILLIMETERS
NOM
MIN
MAX
Number of Leads
Lead Pitch
Overall Height
N
e
A
100
0.40 BSC
–
–
1.20
1.05
0.15
0.75
Molded Package Thickness
Standoff
Foot Length
A2
A1
L
0.95
0.05
0.45
1.00
–
0.60
Footprint
Foot Angle
L1
φ
1.00 REF
3.5°
0°
7°
Overall Width
E
D
E1
D1
c
b
α
β
14.00 BSC
14.00 BSC
12.00 BSC
12.00 BSC
–
Overall Length
Molded Package Width
Molded Package Length
Lead Thickness
Lead Width
0.09
0.13
11°
0.20
0.23
13°
0.18
12°
12°
Mold Draft Angle Top
Mold Draft Angle Bottom
11°
13°
Notes:
1. Pin 1 visual index feature may vary, but must be located within the hatched area.
2. Chamfers at corners are optional; size may vary.
3. Dimensions D1 and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.25 mm per side.
4. Dimensioning and tolerancing per ASME Y14.5M.
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
REF: Reference Dimension, usually without tolerance, for information purposes only.
Microchip Technology Drawing C04-100B
DS70592A-page 278
Preliminary
© 2009 Microchip Technology Inc.
PIC24HJXXXGPX06A/X08A/X10A
ꢘꢙꢙꢂꢃꢄꢅꢆꢇꢈꢉꢅꢊꢋꢌꢍꢇꢎꢏꢌꢐꢇꢑꢒꢅꢆꢇꢓꢉꢅꢋꢔꢅꢍꢕꢇꢖꢈꢎꢗꢇMꢇꢘ#ꢚꢘ#ꢚꢘꢇꢛꢛꢇꢜ ꢆ!"ꢇ#$ꢙꢙꢇꢛꢛꢇ%ꢎꢑꢓꢈ&
' ꢋꢄ( ꢀꢁꢂ!ꢃꢄꢂ"ꢀ#!ꢂꢅ$ꢁꢁꢄꢆ!ꢂꢇꢈꢅ%ꢈꢉꢄꢂ&ꢁꢈ'ꢊꢆꢉ#(ꢂꢇꢋꢄꢈ#ꢄꢂ#ꢄꢄꢂ!ꢃꢄꢂꢌꢊꢅꢁꢀꢅꢃꢊꢇꢂ)ꢈꢅ%ꢈꢉꢊꢆꢉꢂꢍꢇꢄꢅꢊ*ꢊꢅꢈ!ꢊꢀꢆꢂꢋꢀꢅꢈ!ꢄ&ꢂꢈ!ꢂ
ꢃ!!ꢇ+,,'''ꢎ"ꢊꢅꢁꢀꢅꢃꢊꢇꢎꢅꢀ",ꢇꢈꢅ%ꢈꢉꢊꢆꢉ
© 2009 Microchip Technology Inc.
Preliminary
DS70592A-page 279
PIC24HJXXXGPX06A/X08A/X10A
100-Lead Plastic Thin Quad Flatpack (PF) – 14x14x1 mm Body, 2.00 mm Footprint [TQFP]
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
D
D1
e
E1
E
b
N
α
NOTE 1
1 23
NOTE 2
A
φ
c
A2
A1
β
L1
L
Units
MILLIMETERS
Dimension Limits
MIN
NOM
100
0.50 BSC
–
1.00
–
MAX
Number of Leads
Lead Pitch
Overall Height
Molded Package Thickness
Standoff
Foot Length
N
e
A
A2
A1
L
–
1.20
1.05
0.15
0.75
0.95
0.05
0.45
0.60
Footprint
Foot Angle
L1
φ
1.00 REF
3.5°
0°
7°
Overall Width
Overall Length
E
D
E1
D1
c
b
α
β
16.00 BSC
16.00 BSC
14.00 BSC
14.00 BSC
–
Molded Package Width
Molded Package Length
Lead Thickness
Lead Width
Mold Draft Angle Top
Mold Draft Angle Bottom
0.09
0.17
11°
0.20
0.27
13°
0.22
12°
12°
11°
13°
Notes:
1. Pin 1 visual index feature may vary, but must be located within the hatched area.
2. Chamfers at corners are optional; size may vary.
3. Dimensions D1 and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.25 mm per side.
4. Dimensioning and tolerancing per ASME Y14.5M.
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
REF: Reference Dimension, usually without tolerance, for information purposes only.
Microchip Technology Drawing C04-110B
DS70592A-page 280
Preliminary
© 2009 Microchip Technology Inc.
PIC24HJXXXGPX06A/X08A/X10A
ꢘꢙꢙꢂꢃꢄꢅꢆꢇꢈꢉꢅꢊꢋꢌꢍꢇꢎꢏꢌꢐꢇꢑꢒꢅꢆꢇꢓꢉꢅꢋꢔꢅꢍꢕꢇꢖꢈꢓꢗꢇMꢇꢘꢁꢚꢘꢁꢚꢘꢇꢛꢛꢇꢜ ꢆ!"ꢇ#$ꢙꢙꢇꢛꢛꢇ%ꢎꢑꢓꢈ&
' ꢋꢄ( ꢀꢁꢂ!ꢃꢄꢂ"ꢀ#!ꢂꢅ$ꢁꢁꢄꢆ!ꢂꢇꢈꢅ%ꢈꢉꢄꢂ&ꢁꢈ'ꢊꢆꢉ#(ꢂꢇꢋꢄꢈ#ꢄꢂ#ꢄꢄꢂ!ꢃꢄꢂꢌꢊꢅꢁꢀꢅꢃꢊꢇꢂ)ꢈꢅ%ꢈꢉꢊꢆꢉꢂꢍꢇꢄꢅꢊ*ꢊꢅꢈ!ꢊꢀꢆꢂꢋꢀꢅꢈ!ꢄ&ꢂꢈ!ꢂ
ꢃ!!ꢇ+,,'''ꢎ"ꢊꢅꢁꢀꢅꢃꢊꢇꢎꢅꢀ",ꢇꢈꢅ%ꢈꢉꢊꢆꢉ
© 2009 Microchip Technology Inc.
Preliminary
DS70592A-page 281
PIC24HJXXXGPX06A/X08A/X10A
NOTES:
DS70592A-page 282
Preliminary
© 2009 Microchip Technology Inc.
PIC24HJXXXGPX06A/X08A/X10A
APPENDIX A: MIGRATING FROM
PIC24HJXXXGPX06/
X08/X10 DEVICES TO
PIC24HJXXXGPX06A/
X08A/X10A DEVICES
PIC24HJXXXGPX06A/X08A/X10A
devices
were
designed to enhance the PIC24HJXXXGPX06/X08/
X10 families of devices.
In general, the PIC24HJXXXGPX06A/X08A/X10A
devices
PIC24HJXXXGPX06/X08/X10
manufacturing differences
are
backward-compatible
with
however,
cause
devices;
may
PIC24HJXXXGPX06A/X08A/X10A devices to behave
differently from PIC24HJXXXGPX06/X08/X10 devices.
Therefore, complete system test and characterization is
recommended if PIC24HJXXXGPX06A/X08A/X10A
devices are used to replace PIC24HJXXXGPX06/X08/
X10 devices.
The following enhancements were introduced:
• Extended temperature support of up to +125ºC
• Enhanced Flash module with higher endurance
and retention
• New PLL Lock Enable configuration bit
• Added Timer5 trigger for ADC1 and Timer3 trigger
for ADC2
© 2009 Microchip Technology Inc.
Preliminary
DS70592A-page 283
PIC24HJXXXGPX06A/X08A/X10A
APPENDIX B: REVISION HISTORY
Revision A (April 2009)
This is the initial release of this document.
DS70592A-page 284
Preliminary
© 2009 Microchip Technology Inc.
PIC24HJXXXGPX06A/X08A/X10A
INDEX
A
D
AC Characteristics ............................................................ 246
Internal RC Accuracy................................................ 248
Load Conditions........................................................ 246
ADC Module
ADC1 Register Map.................................................... 42
ADC2 Register Map.................................................... 42
Alternate Interrupt Vector Table (AIVT) .............................. 71
Analog-to-Digital Converter............................................... 205
DMA.......................................................................... 205
Initialization ............................................................... 205
Key Features............................................................. 205
Arithmetic Logic Unit (ALU)................................................. 28
Assembler
Data Address Space........................................................... 31
Alignment.................................................................... 31
Memory Map for PIC24HJXXXGPX06A/X08A/X10A De-
vices with 16 KB RAM........................................ 33
Memory Map for PIC24HJXXXGPX06A/X08A/X10A De-
vices with 8 KB RAM.......................................... 32
Near Data Space........................................................ 31
Software Stack ........................................................... 53
Width .......................................................................... 31
DC Characteristics............................................................ 238
I/O Pin Input Specifications ...................................... 243
I/O Pin Output Specifications.................................... 244
Idle Current (IDOZE) .................................................. 242
Idle Current (IIDLE).................................................... 241
Operating Current (IDD) ............................................ 240
Power-Down Current (IPD)........................................ 242
Program Memory...................................................... 245
Temperature and Voltage Specifications.................. 239
Development Support....................................................... 233
DMA Module
MPASM Assembler................................................... 234
Automatic Clock Stretch.................................................... 166
B
Block Diagrams
16-bit Timer1 Module................................................ 145
ADC1 Module............................................................ 206
Connections for On-Chip Voltage Regulator............. 222
ECAN Module ........................................................... 180
Input Capture ............................................................ 153
Output Compare ....................................................... 155
PIC24H ....................................................................... 16
PIC24H CPU Core...................................................... 24
PIC24H Oscillator System Diagram.......................... 125
PIC24H PLL.............................................................. 127
Reset System.............................................................. 65
Shared Port Structure ............................................... 143
SPI ............................................................................ 159
Timer2 (16-bit) .......................................................... 149
Timer2/3 (32-bit) ....................................................... 148
UART ........................................................................ 173
Watchdog Timer (WDT)............................................ 223
DMA Register Map ..................................................... 43
DMAC Registers............................................................... 116
DMAxCNT ................................................................ 116
DMAxCON................................................................ 116
DMAxPAD ................................................................ 116
DMAxREQ................................................................ 116
DMAxSTA................................................................. 116
DMAxSTB................................................................. 116
E
ECAN Module
CiFMSKSEL2 register .............................................. 197
ECAN1 Register Map (C1CTRL1.WIN = 0 or 1)......... 44
ECAN1 Register Map (C1CTRL1.WIN = 0)................ 45
ECAN1 Register Map (C1CTRL1.WIN = 1)................ 45
ECAN2 Register Map (C2CTRL1.WIN = 0 or 1)......... 47
ECAN2 Register Map (C2CTRL1.WIN = 0)................ 47
ECAN2 Register Map (C2CTRL1.WIN = 1)................ 48
Frame Types ............................................................ 179
Modes of Operation.................................................. 181
Overview................................................................... 179
ECAN Registers
Filter 15-8 Mask Selection Register (CiFMSKSEL2) 197
Electrical Characteristics .................................................. 237
AC............................................................................. 246
Enhanced CAN Module .................................................... 179
Equations
C
C Compilers
MPLAB C18 .............................................................. 234
MPLAB C30 .............................................................. 234
Clock Switching................................................................. 133
Enabling.................................................................... 133
Sequence.................................................................. 133
Code Examples
Erasing a Program Memory Page............................... 62
Initiating a Programming Sequence............................ 63
Loading Write Buffers ................................................. 63
Port Write/Read ........................................................ 144
PWRSAV Instruction Syntax..................................... 135
Code Protection ........................................................ 217, 224
Configuration Bits.............................................................. 217
Description (Table).................................................... 218
Configuration Register Map .............................................. 217
Configuring Analog Port Pins............................................ 144
CPU
Control Register.......................................................... 25
CPU Clocking System....................................................... 126
PLL Configuration ..................................................... 126
Selection ................................................................... 126
Sources..................................................................... 126
Customer Change Notification Service............................. 289
Customer Support............................................................. 289
Device Operating Frequency.................................... 126
FOSC Calculation..................................................... 126
XT with PLL Mode Example ..................................... 127
Errata.................................................................................. 14
F
Flash Program Memory ...................................................... 59
Control Registers........................................................ 60
Operations.................................................................. 60
Programming Algorithm.............................................. 62
RTSP Operation ......................................................... 60
Table Instructions ....................................................... 59
Flexible Configuration....................................................... 217
FSCM
Delay for Crystal and PLL Clock Sources .................. 69
Device Resets ............................................................ 69
© 2009 Microchip Technology Inc.
Preliminary
DS70592A-page 285
PIC24HJXXXGPX06A/X08A/X10A
MPLINK Object Linker/MPLIB Object Librarian................ 234
Multi-Bit Data Shifter........................................................... 28
I
I/O Ports............................................................................143
Parallel I/O (PIO).......................................................143
Write/Read Timing ....................................................144
I2C
Operating Modes ......................................................165
Registers...................................................................165
I2C Module
I2C1 Register Map......................................................40
I2C2 Register Map......................................................40
In-Circuit Debugger...........................................................224
In-Circuit Emulation...........................................................217
In-Circuit Serial Programming (ICSP) .......................217, 224
Input Capture
Registers...................................................................154
Input Change Notification Module.....................................144
Instruction Addressing Modes.............................................53
File Register Instructions ............................................53
Fundamental Modes Supported..................................54
MCU Instructions ........................................................53
Move and Accumulator Instructions............................54
Other Instructions........................................................54
Instruction Set
N
NVM Module
Register Map .............................................................. 52
O
Open-Drain Configuration................................................. 144
Output Compare ............................................................... 155
P
Packaging......................................................................... 273
Details....................................................................... 276
Marking..................................................................... 273
Peripheral Module Disable (PMD) .................................... 136
PICSTART Plus Development Programmer..................... 236
Pinout I/O Descriptions (table)............................................ 17
PMD Module
Register Map .............................................................. 52
POR and Long Oscillator Start-up Times ........................... 69
PORTA
Register Map .............................................................. 50
PORTB
Overview...................................................................227
Summary...................................................................225
Instruction-Based Power-Saving Modes...........................135
Idle ............................................................................136
Sleep.........................................................................135
Internal RC Oscillator
Register Map .............................................................. 50
PORTC
Register Map .............................................................. 50
PORTD
Register Map .............................................................. 50
PORTE
Use with WDT...........................................................223
Internet Address................................................................289
Interrupt Control and Status Registers................................75
IECx ............................................................................75
IFSx.............................................................................75
INTCON1 ....................................................................75
INTCON2 ....................................................................75
INTTREG ....................................................................75
IPCx ............................................................................75
Interrupt Setup Procedures...............................................114
Initialization ...............................................................114
Interrupt Disable........................................................114
Interrupt Service Routine ..........................................114
Trap Service Routine ................................................114
Interrupt Vector Table (IVT) ................................................71
Interrupts Coincident with Power Save Instructions..........136
Register Map .............................................................. 51
PORTF
Register Map .............................................................. 51
PORTG
Register Map .............................................................. 51
Power-Saving Features .................................................... 135
Clock Frequency and Switching ............................... 135
Program Address Space..................................................... 29
Construction ............................................................... 55
Data Access from Program Memory Using Program
Space Visibility ................................................... 58
Data Access from Program Memory Using Table Instruc-
tions.................................................................... 57
Data Access from, Address Generation ..................... 56
Memory Map............................................................... 29
Table Read Instructions
TBLRDH ............................................................. 57
TBLRDL.............................................................. 57
Visibility Operation...................................................... 58
Program Memory
J
JTAG Boundary Scan Interface ........................................217
M
Interrupt Vector........................................................... 30
Organization ............................................................... 30
Reset Vector............................................................... 30
Memory Organization..........................................................29
Microchip Internet Web Site..............................................289
Modes of Operation
Disable......................................................................181
Initialization ...............................................................181
Listen All Messages..................................................181
Listen Only................................................................181
Loopback ..................................................................181
Normal Operation......................................................181
MPLAB ASM30 Assembler, Linker, Librarian ...................234
MPLAB ICD 2 In-Circuit Debugger....................................235
MPLAB ICE 2000 High-Performance Universal In-Circuit Em-
ulator.........................................................................235
MPLAB Integrated Development Environment Software ..233
MPLAB PM3 Device Programmer.....................................235
MPLAB REAL ICE In-Circuit Emulator System.................235
R
Reader Response............................................................. 290
Registers
ADxCHS0 (ADCx Input Channel 0 Select ................ 214
ADxCHS123 (ADCx Input Channel 1, 2, 3 Select) ... 213
ADxCON1 (ADCx Control 1)..................................... 208
ADxCON2 (ADCx Control 2)..................................... 210
ADxCON3 (ADCx Control 3)..................................... 211
ADxCON4 (ADCx Control 4)..................................... 212
ADxCSSH (ADCx Input Scan Select High)............... 215
ADxCSSL (ADCx Input Scan Select Low)................ 215
ADxPCFGH (ADCx Port Configuration High) ........... 216
DS70592A-page 286
Preliminary
© 2009 Microchip Technology Inc.
PIC24HJXXXGPX06A/X08A/X10A
ADxPCFGL (ADCx Port Configuration Low)............. 216
IPC11 (Interrupt Priority Control 11)......................... 106
IPC12 (Interrupt Priority Control 12)......................... 107
IPC13 (Interrupt Priority Control 13)......................... 108
IPC14 (Interrupt Priority Control 14)......................... 109
IPC15 (Interrupt Priority Control 15)......................... 110
IPC16 (Interrupt Priority Control 16)................. 111, 113
IPC17 (Interrupt Priority Control 17)......................... 112
IPC2 (Interrupt Priority Control 2)............................... 97
IPC3 (Interrupt Priority Control 3)............................... 98
IPC4 (Interrupt Priority Control 4)............................... 99
IPC5 (Interrupt Priority Control 5)............................. 100
IPC6 (Interrupt Priority Control 6)............................. 101
IPC7 (Interrupt Priority Control 7)............................. 102
IPC8 (Interrupt Priority Control 8)............................. 103
IPC9 (Interrupt Priority Control 9)............................. 104
NVMCON (Flash Memory Control)............................. 61
OCxCON (Output Compare x Control)..................... 157
OSCCON (Oscillator Control)................................... 128
OSCTUN (FRC Oscillator Tuning)............................ 132
PLLFBD (PLL Feedback Divisor) ............................. 131
PMD1 (Peripheral Module Disable Control Register 1)..
137
PMD2 (Peripheral Module Disable Control Register 2)..
139
PMD3 (Peripheral Module Disable Control Register 3)..
141
RCON (Reset Control)................................................ 66
SPIxCON1 (SPIx Control 1) ..................................... 161
SPIxCON2 (SPIx Control 2) ..................................... 163
SPIxSTAT (SPIx Status and Control)....................... 160
SR (CPU Status) .................................................. 26, 76
T1CON (Timer1 Control) .......................................... 146
TxCON (T2CON, T4CON, T6CON or T8CON Control)..
150
CiBUFPNT1 (ECAN Filter 0-3 Buffer Pointer)........... 192
CiBUFPNT2 (ECAN Filter 4-7 Buffer Pointer)........... 193
CiBUFPNT3 (ECAN Filter 8-11 Buffer Pointer)......... 193
CiBUFPNT4 (ECAN Filter 12-15 Buffer Pointer)....... 194
CiCFG1 (ECAN Baud Rate Configuration 1) ............ 190
CiCFG2 (ECAN Baud Rate Configuration 2) ............ 191
CiCTRL1 (ECAN Control 1) ...................................... 182
CiCTRL2 (ECAN Control 2) ...................................... 183
CiEC (ECAN Transmit/Receive Error Count)............ 189
CiFCTRL (ECAN FIFO Control)................................ 185
CiFEN1 (ECAN Acceptance Filter Enable)............... 192
CiFIFO (ECAN FIFO Status)..................................... 186
CiFMSKSEL1 (ECAN Filter 7-0 Mask Selection)..... 196,
197
CiINTE (ECAN Interrupt Enable) .............................. 188
CiINTF (ECAN Interrupt Flag)................................... 187
CiRXFnEID (ECAN Acceptance Filter n Extended Identi-
fier).................................................................... 195
CiRXFnSID (ECAN Acceptance Filter n Standard Identi-
fier).................................................................... 195
CiRXFUL1 (ECAN Receive Buffer Full 1)................. 199
CiRXFUL2 (ECAN Receive Buffer Full 2)................. 199
CiRXMnEID (ECAN Acceptance Filter Mask n Extended
Identifier)........................................................... 198
CiRXMnSID (ECAN Acceptance Filter Mask n Standard
Identifier)........................................................... 198
CiRXOVF1 (ECAN Receive Buffer Overflow 1)........ 200
CiRXOVF2 (ECAN Receive Buffer Overflow 2)........ 200
CiTRBnDLC (ECAN Buffer n Data Length Control).. 203
CiTRBnEID (ECAN Buffer n Extended Identifier) ..... 202
CiTRBnSID (ECAN Buffer n Standard Identifier)...... 202
CiTRBnSTAT (ECAN Receive Buffer n Status)........ 204
CiTRmnCON (ECAN TX/RX Buffer m Control)......... 201
CiVEC (ECAN Interrupt Code).................................. 184
CLKDIV (Clock Divisor)............................................. 130
CORCON (Core Control) ...................................... 27, 76
DMACS0 (DMA Controller Status 0)......................... 121
DMACS1 (DMA Controller Status 1)......................... 123
DMAxCNT (DMA Channel x Transfer Count) ........... 120
DMAxCON (DMA Channel x Control)....................... 117
DMAxPAD (DMA Channel x Peripheral Address)..... 120
DMAxREQ (DMA Channel x IRQ Select) ................. 118
DMAxSTA (DMA Channel x RAM Start Address A) . 119
DMAxSTB (DMA Channel x RAM Start Address B) . 119
DSADR (Most Recent DMA RAM Address).............. 124
I2CxCON (I2Cx Control) ........................................... 167
I2CxMSK (I2Cx Slave Mode Address Mask) ............ 171
I2CxSTAT (I2Cx Status) ........................................... 169
ICxCON (Input Capture x Control)............................ 154
IEC0 (Interrupt Enable Control 0) ............................... 87
IEC1 (Interrupt Enable Control 1) ............................... 89
IEC2 (Interrupt Enable Control 2) ............................... 91
IEC3 (Interrupt Enable Control 3) ............................... 93
IEC4 (Interrupt Enable Control 4) ............................... 94
IFS0 (Interrupt Flag Status 0) ..................................... 79
IFS1 (Interrupt Flag Status 1) ..................................... 81
IFS2 (Interrupt Flag Status 2) ..................................... 83
IFS3 (Interrupt Flag Status 3) ..................................... 85
IFS4 (Interrupt Flag Status 4) ..................................... 86
INTCON1 (Interrupt Control 1).................................... 77
INTCON2 (Interrupt Control 2).................................... 78
IPC0 (Interrupt Priority Control 0) ............................... 95
IPC1 (Interrupt Priority Control 1) ............................... 96
IPC10 (Interrupt Priority Control 10) ......................... 105
TyCON (T3CON, T5CON, T7CON or T9CON Control)..
151
UxMODE (UARTx Mode) ......................................... 174
UxSTA (UARTx Status and Control) ........................ 176
Reset
Clock Source Selection .............................................. 68
Special Function Register Reset States..................... 69
Times.......................................................................... 68
Reset Sequence................................................................. 71
Resets ................................................................................ 65
S
Serial Peripheral Interface (SPI)....................................... 159
Software Simulator (MPLAB SIM) .................................... 234
Software Stack Pointer, Frame Pointer
CALL Stack Frame ..................................................... 53
Special Features............................................................... 217
SPI Module
SPI1 Register Map ..................................................... 41
SPI2 Register Map ..................................................... 41
Symbols Used in Opcode Descriptions ............................ 226
System Control
Register Map .............................................................. 52
T
Temperature and Voltage Specifications
AC............................................................................. 246
Timer1 .............................................................................. 145
Timer2/3, Timer4/5, Timer6/7 and Timer8/9..................... 147
Timing Characteristics
CLKO and I/O........................................................... 249
Timing Diagrams
© 2009 Microchip Technology Inc.
Preliminary
DS70592A-page 287
PIC24HJXXXGPX06A/X08A/X10A
10-bit Analog-to-Digital Conversion (CHPS = 01,
SIMSAM = 0, ASAM = 1, SSRC =
111, SAMC = 00001)...........................271
10-bit Analog-to-Digtial Conversion (CHPS = 01, SIM-
SAM = 0, ASAM = 0, SSRC = 000) ..................271
12-bit Analog-to-Digital Conversion (ASAM = 0, SSRC =
000)...................................................................269
ECAN I/O ..................................................................265
External Clock...........................................................247
I2Cx Bus Data (Master Mode) ..................................261
I2Cx Bus Data (Slave Mode) ....................................263
I2Cx Bus Start/Stop Bits (Master Mode) ...................261
I2Cx Bus Start/Stop Bits (Slave Mode).....................263
Input Capture (CAPx)................................................254
OC/PWM...................................................................255
Output Compare (OCx).............................................254
Reset, Watchdog Timer, Oscillator Start-up Timer and
Power-up Timer ................................................250
SPIx Master Mode (CKE = 0)....................................256
SPIx Master Mode (CKE = 1)....................................257
SPIx Slave Mode (CKE = 0)......................................258
SPIx Slave Mode (CKE = 1)......................................259
Timer1, 2 and 3 External Clock.................................252
Timing Requirements
CLKO and I/O ...........................................................249
External Clock...........................................................247
Input Capture ............................................................254
Timing Specifications
10-bit Analog-to-Digital Conversion Requirements...272
CAN I/O Requirements .............................................265
I2Cx Bus Data Requirements (Master Mode) ...........262
I2Cx Bus Data Requirements (Slave Mode).............264
Output Compare Requirements................................254
PLL Clock..................................................................248
Reset, Watchdog Timer, Oscillator Start-up Timer, Pow-
er-up Timer and Brown-out Reset Requirements ...
251
Simple OC/PWM Mode Requirements .....................255
SPIx Master Mode (CKE = 0) Requirements ............256
SPIx Master Mode (CKE = 1) Requirements ............257
SPIx Slave Mode (CKE = 0) Requirements ..............258
SPIx Slave Mode (CKE = 1) Requirements ..............260
Timer1 External Clock Requirements .......................252
Timer2 External Clock Requirements .......................253
Timer3 External Clock Requirements .......................253
U
UART Module
UART1 Register Map..................................................40
UART2 Register Map..................................................41
V
Voltage Regulator (On-Chip).............................................222
W
Watchdog Timer (WDT) ............................................217, 223
Programming Considerations ...................................223
WWW Address..................................................................289
WWW, On-Line Support......................................................14
DS70592A-page 288
Preliminary
© 2009 Microchip Technology Inc.
PIC24HJXXXGPX06A/X08A/X10A
THE MICROCHIP WEB SITE
CUSTOMER SUPPORT
Microchip provides online support via our WWW site at
www.microchip.com. This web site is used as a means
to make files and information easily available to
customers. Accessible by using your favorite Internet
browser, the web site contains the following informa-
tion:
Users of Microchip products can receive assistance
through several channels:
• Distributor or Representative
• Local Sales Office
• Field Application Engineer (FAE)
• Technical Support
• Product Support – Data sheets and errata, appli-
cation notes and sample programs, design
resources, user’s guides and hardware support
documents, latest software releases and archived
software
Customers should contact their distributor, representa-
tive or field application engineer (FAE) for support.
Local sales offices are also available to help custom-
ers. A listing of sales offices and locations is included in
the back of this document.
• General Technical Support – Frequently Asked
Questions (FAQs), technical support requests,
online discussion groups, Microchip consultant
program member listing
Technical support is available through the web site
at: http://support.microchip.com
• Business of Microchip – Product selector and
ordering guides, latest Microchip press releases,
listing of seminars and events, listings of Micro-
chip sales offices, distributors and factory repre-
sentatives
CUSTOMER CHANGE NOTIFICATION
SERVICE
Microchip’s customer notification service helps keep
customers current on Microchip products. Subscribers
will receive e-mail notification whenever there are
changes, updates, revisions or errata related to a spec-
ified product family or development tool of interest.
To register, access the Microchip web site at
www.microchip.com, click on Customer Change Notifi-
cation and follow the registration instructions.
© 2009 Microchip Technology Inc.
Preliminary
DS70592A-page 289
PIC24HJXXXGPX06A/X08A/X10A
READER RESPONSE
It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip prod-
uct. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation
can better serve you, please FAX your comments to the Technical Publications Manager at (480) 792-4150.
Please list the following information, and use this outline to provide us with your comments about this document.
To:
Technical Publications Manager
Reader Response
Total Pages Sent ________
RE:
From:
Name
Company
Address
City / State / ZIP / Country
Telephone: (_______) _________ - _________
FAX: (______) _________ - _________
Application (optional):
Would you like a reply?
Y
N
Device: PIC24HJXXXGPX06A/X08A/X10A
Questions:
Literature Number: DS70592A
1. What are the best features of this document?
2. How does this document meet your hardware and software development needs?
3. Do you find the organization of this document easy to follow? If not, why?
4. What additions to the document do you think would enhance the structure and subject?
5. What deletions from the document could be made without affecting the overall usefulness?
6. Is there any incorrect or misleading information (what and where)?
7. How would you improve this document?
DS70592A-page 290
Preliminary
© 2009 Microchip Technology Inc.
PIC24HJXXXGPX06A/X08A/X10A
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
Examples:
PIC 24 HJ 256 GP6 10 A T I/PT - XXX
a)
b)
PIC24HJ256GP210AI/PT:
General-purpose PIC24H, 256 KB program
memory, 100-pin, Industrial temp.,
TQFP package.
Microchip Trademark
Architecture
PIC24HJ64GP506AI/PT-ES:
Flash Memory Family
General-purpose PIC24H, 64 KB program
memory, 64-pin, Industrial temp.,
TQFP package, Engineering Sample.
Program Memory Size (KB)
Product Group
Pin Count
Revision Level
Tape and Reel Flag (if applicable)
Temperature Range
Package
Pattern
Architecture:
24
=
=
16-bit Microcontroller
Flash Memory Family: HJ
Flash program memory, 3.3V, High-speed
Product Group:
GP2
=
=
=
=
General purpose family
General purpose family
General purpose family
General purpose family
GP3
GP5
GP6
Pin Count:
06
10
=
=
64-pin
100-pin
Temperature Range:
I
E
=
=
-40°C to +85°C (Industrial)
-40°C to +125°C (Extended)
Package:
Pattern:
PT
PF
MR
=
=
=
10x10 or 12x12 mm TQFP (Thin Quad Flatpack)
14x14 mm TQFP (Thin Quad Flatpack)
9x9x0.9 mm QFN (Thin Quad Flatpack)
Three-digit QTP, SQTP, Code or Special Requirements
(blank otherwise)
ES
=
Engineering Sample
© 2009 Microchip Technology Inc.
Preliminary
DS70592A-page 291
WORLDWIDE SALES AND SERVICE
AMERICAS
ASIA/PACIFIC
ASIA/PACIFIC
EUROPE
Corporate Office
Asia Pacific Office
Suites 3707-14, 37th Floor
Tower 6, The Gateway
Harbour City, Kowloon
Hong Kong
Tel: 852-2401-1200
Fax: 852-2401-3431
India - Bangalore
Tel: 91-80-3090-4444
Fax: 91-80-3090-4080
Austria - Wels
Tel: 43-7242-2244-39
Fax: 43-7242-2244-393
2355 West Chandler Blvd.
Chandler, AZ 85224-6199
Tel: 480-792-7200
Fax: 480-792-7277
Technical Support:
http://support.microchip.com
Web Address:
www.microchip.com
Denmark - Copenhagen
Tel: 45-4450-2828
Fax: 45-4485-2829
India - New Delhi
Tel: 91-11-4160-8631
Fax: 91-11-4160-8632
France - Paris
Tel: 33-1-69-53-63-20
Fax: 33-1-69-30-90-79
India - Pune
Tel: 91-20-2566-1512
Fax: 91-20-2566-1513
Australia - Sydney
Tel: 61-2-9868-6733
Fax: 61-2-9868-6755
Atlanta
Duluth, GA
Tel: 678-957-9614
Fax: 678-957-1455
Germany - Munich
Tel: 49-89-627-144-0
Fax: 49-89-627-144-44
Japan - Yokohama
Tel: 81-45-471- 6166
Fax: 81-45-471-6122
China - Beijing
Tel: 86-10-8528-2100
Fax: 86-10-8528-2104
Italy - Milan
Tel: 39-0331-742611
Fax: 39-0331-466781
Korea - Daegu
Tel: 82-53-744-4301
Fax: 82-53-744-4302
Boston
China - Chengdu
Tel: 86-28-8665-5511
Fax: 86-28-8665-7889
Westborough, MA
Tel: 774-760-0087
Fax: 774-760-0088
Netherlands - Drunen
Tel: 31-416-690399
Fax: 31-416-690340
Korea - Seoul
China - Hong Kong SAR
Tel: 852-2401-1200
Fax: 852-2401-3431
Tel: 82-2-554-7200
Fax: 82-2-558-5932 or
82-2-558-5934
Chicago
Itasca, IL
Tel: 630-285-0071
Fax: 630-285-0075
Spain - Madrid
Tel: 34-91-708-08-90
Fax: 34-91-708-08-91
China - Nanjing
Tel: 86-25-8473-2460
Fax: 86-25-8473-2470
Malaysia - Kuala Lumpur
Tel: 60-3-6201-9857
Fax: 60-3-6201-9859
Cleveland
UK - Wokingham
Tel: 44-118-921-5869
Fax: 44-118-921-5820
Independence, OH
Tel: 216-447-0464
Fax: 216-447-0643
China - Qingdao
Tel: 86-532-8502-7355
Fax: 86-532-8502-7205
Malaysia - Penang
Tel: 60-4-227-8870
Fax: 60-4-227-4068
Dallas
Addison, TX
Tel: 972-818-7423
Fax: 972-818-2924
China - Shanghai
Tel: 86-21-5407-5533
Fax: 86-21-5407-5066
Philippines - Manila
Tel: 63-2-634-9065
Fax: 63-2-634-9069
Detroit
China - Shenyang
Tel: 86-24-2334-2829
Fax: 86-24-2334-2393
Singapore
Tel: 65-6334-8870
Fax: 65-6334-8850
Farmington Hills, MI
Tel: 248-538-2250
Fax: 248-538-2260
China - Shenzhen
Tel: 86-755-8203-2660
Fax: 86-755-8203-1760
Taiwan - Hsin Chu
Tel: 886-3-6578-300
Fax: 886-3-6578-370
Kokomo
Kokomo, IN
Tel: 765-864-8360
Fax: 765-864-8387
China - Wuhan
Tel: 86-27-5980-5300
Fax: 86-27-5980-5118
Taiwan - Kaohsiung
Tel: 886-7-536-4818
Fax: 886-7-536-4803
Los Angeles
Mission Viejo, CA
Tel: 949-462-9523
Fax: 949-462-9608
China - Xiamen
Tel: 86-592-2388138
Fax: 86-592-2388130
Taiwan - Taipei
Tel: 886-2-2500-6610
Fax: 886-2-2508-0102
Santa Clara
China - Xian
Tel: 86-29-8833-7252
Fax: 86-29-8833-7256
Thailand - Bangkok
Tel: 66-2-694-1351
Fax: 66-2-694-1350
Santa Clara, CA
Tel: 408-961-6444
Fax: 408-961-6445
China - Zhuhai
Tel: 86-756-3210040
Fax: 86-756-3210049
Toronto
Mississauga, Ontario,
Canada
Tel: 905-673-0699
Fax: 905-673-6509
03/26/09
DS70592A-page 292
© 2009 Microchip Technology Inc.
相关型号:
PIC24HJ64GP506ATE/MR
16-BIT, FLASH, 40 MHz, MICROCONTROLLER, PQCC64, 9 X 9 MM, 0.90 MM HEIGHT, 0.50 MM, LEAD FREE, PLASTIC, QFN-64
MICROCHIP
PIC24HJ64GP506ATE/PT
16-BIT, FLASH, 40 MHz, MICROCONTROLLER, PQFP64, 10 X 10 MM, 1 MM HEIGHT, 0.50 MM, LEAD FREE, PLASTIC, TQFP-64
MICROCHIP
PIC24HJ64GP506ATH/MR
16-BIT, FLASH, 20 MHz, MICROCONTROLLER, PQCC64, 9 X 9 MM, 0.90 MM HEIGHT, 0.50 MM, LEAD FREE, PLASTIC, QFN-64
MICROCHIP
PIC24HJ64GP506ATH/PT
16-BIT, FLASH, 20 MHz, MICROCONTROLLER, PQFP64, 10 X 10 MM, 1 MM HEIGHT, 0.50 MM, LEAD FREE, PLASTIC, TQFP-64
MICROCHIP
PIC24HJ64GP506ATI/PT
16-BIT, FLASH, 40 MHz, MICROCONTROLLER, PQFP64, 10 X 10 MM, 1 MM HEIGHT, 0.50 MM, LEAD FREE, PLASTIC, TQFP-64
MICROCHIP
PIC24HJ64GP506I/PT-ES
16-BIT, FLASH, 32 MHz, MICROCONTROLLER, PQFP64, 10 X 10 MM, 1 MM HEIGHT, PLASTIC, TQFP-64
MICROCHIP
PIC24HJ64GP510A
16-bit Microcontrollers (up to 256 KB Flash and 16 KB SRAM) with Advanced Analog
MICROCHIP
©2020 ICPDF网 联系我们和版权申明