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PIC32MX360F512L [MICROCHIP]

64/100-Pin General Purpose and USB 32-Bit Flash Microcontrollers; 100分之64引脚通用系列和USB的32位闪存微控制器
PIC32MX360F512L
型号： PIC32MX360F512L
厂家： MICROCHIP    MICROCHIP
描述：

64/100-Pin General Purpose and USB 32-Bit Flash Microcontrollers
100分之64引脚通用系列和USB的32位闪存微控制器

闪存 微控制器
文件： 总172页 (文件大小：3405K)
中文：  中文翻译
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PIC32MX3XX/4XX Family  
Data Sheet  
64/100-Pin General Purpose and USB  
32-Bit Flash Microcontrollers  
© 2009 Microchip Technology Inc.  
Preliminary  
DS61143F  
Note the following details of the code protection feature on Microchip devices:  
•
Microchip products meet the specification contained in their particular Microchip Data Sheet.  
•
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the  
intended manner and under normal conditions.  
•
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our  
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data  
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.  
•
•
Microchip is willing to work with the customer who is concerned about the integrity of their code.  
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not  
mean that we are guaranteeing the product as “unbreakable.”  
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our  
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts  
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.  
Information contained in this publication regarding device  
applications and the like is provided only for your convenience  
and may be superseded by updates. It is your responsibility to  
ensure that your application meets with your specifications.  
MICROCHIP MAKES NO REPRESENTATIONS OR  
WARRANTIES OF ANY KIND WHETHER EXPRESS OR  
IMPLIED, WRITTEN OR ORAL, STATUTORY OR  
OTHERWISE, RELATED TO THE INFORMATION,  
INCLUDING BUT NOT LIMITED TO ITS CONDITION,  
QUALITY, PERFORMANCE, MERCHANTABILITY OR  
FITNESS FOR PURPOSE. Microchip disclaims all liability  
arising from this information and its use. Use of Microchip  
devices in life support and/or safety applications is entirely at  
the buyer’s risk, and the buyer agrees to defend, indemnify and  
hold harmless Microchip from any and all damages, claims,  
suits, or expenses resulting from such use. No licenses are  
conveyed, implicitly or otherwise, under any Microchip  
intellectual property rights.  
Trademarks  
The Microchip name and logo, the Microchip logo, dsPIC,  
KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART,  
rfPIC and UNI/O are registered trademarks of Microchip  
Technology Incorporated in the U.S.A. and other countries.  
FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor,  
MXDEV, MXLAB, SEEVAL and The Embedded Control  
Solutions Company are registered trademarks of Microchip  
Technology Incorporated in the U.S.A.  
Analog-for-the-Digital Age, Application Maestro, CodeGuard,  
dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN,  
ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial  
Programming, ICSP, ICEPIC, Mindi, MiWi, MPASM, MPLAB  
Certified logo, MPLIB, MPLINK, mTouch, nanoWatt XLP,  
Omniscient Code Generation, PICC, PICC-18, PICkit,  
PICDEM, PICDEM.net, PICtail, PIC32 logo, REAL ICE, rfLAB,  
Select Mode, Total Endurance, TSHARC, WiperLock and  
ZENA are trademarks of Microchip Technology Incorporated  
in the U.S.A. and other countries.  
SQTP is a service mark of Microchip Technology Incorporated  
in the U.S.A.  
All other trademarks mentioned herein are property of their  
respective companies.  
© 2009, Microchip Technology Incorporated, Printed in the  
U.S.A., All Rights Reserved.  
Printed on recycled paper.  
Microchip received ISO/TS-16949:2002 certification for its worldwide  
headquarters, design and wafer fabrication facilities in Chandler and  
Tempe, Arizona; Gresham, Oregon and design centers in California  
and India. The Company’s quality system processes and procedures  
are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping  
devices, Serial EEPROMs, microperipherals, nonvolatile memory and  
analog products. In addition, Microchip’s quality system for the design  
and manufacture of development systems is ISO 9001:2000 certified.  
DS61143F-page ii  
Preliminary  
© 2009 Microchip Technology Inc.  
PIC32MX3XX/4XX  
High-Performance 80 MHz MIPS-Based 32-bit Flash Microcontroller  
64/100-Pin General Purpose and USB  
• Separate PLLs for CPU and USB Clocks  
High-Performance 32-bit RISC CPU:  
• Two I2C™ Modules  
• MIPS32® M4K™ 32-bit Core with 5-Stage Pipeline  
• Two UART Modules with:  
• 80 MHz Maximum Frequency  
- RS-232, RS-485 and LIN 1.2 support  
- IrDA® with On-Chip Hardware Encoder and  
Decoder  
• 1.56 DMIPS/MHz (Dhrystone 2.1) Performance  
at 0 Wait State Flash Access  
• Single-Cycle Multiply and High-Performance  
• Parallel Master and Slave Port (PMP/PSP) with  
Divide Unit  
8-bit and 16-bit Data and Up to 16 Address Lines  
• MIPS16e™ Mode for Up to 40% Smaller Code  
• Hardware Real-Time Clock/Calendar (RTCC)  
Size  
• Five 16-bit Timers/Counters (two 16-bit pairs com-  
• Two Sets of 32 Core Register Files (32-bit) to  
bine to create two 32-bit timers)  
Reduce Interrupt Latency  
• Five Capture Inputs  
• Prefetch Cache Module to Speed Execution from  
• Five Compare/PWM Outputs  
• Five External Interrupt Pins  
Flash  
• High-Speed I/O Pins Capable of Toggling at Up to  
80 MHz  
Microcontroller Features:  
• Operating Voltage Range of 2.3V to 3.6V  
• High-Current Sink/Source (18 mA/18 mA) on  
All I/O Pins  
• 32K to 512K Flash Memory (plus an additional  
12KB of Boot Flash)  
• Configurable Open-Drain Output on Digital I/O  
Pins  
• 8K to 32K SRAM Memory  
• Pin-Compatible with Most PIC24/dsPIC® Devices  
• Multiple Power Management Modes  
Debug Features:  
• Multiple Interrupt Vectors with Individually  
Programmable Priority  
• Two Programming and Debugging Interfaces:  
- 2-Wire Interface with Unintrusive Access and  
Real-time Data Exchange with Application  
- 4-wire MIPS® Standard Enhanced JTAG  
interface  
• Fail-Safe Clock Monitor Mode  
• Configurable Watchdog Timer with On-Chip  
Low-Power RC Oscillator for Reliable Operation  
• Unintrusive Hardware-Based Instruction Trace  
Peripheral Features:  
• IEEE Std 1149.2 Compatible (JTAG) Boundary  
Scan  
• Atomic SET, CLEAR and INVERT Operation on  
Select Peripheral Registers  
• Up to 4-Channel Hardware DMA with Automatic  
Data Size Detection  
Analog Features:  
• Up to 16-Channel 10-bit Analog-to-Digital  
Converter:  
• USB 2.0 Compliant Full Speed Device and  
On-The-Go (OTG) Controller  
- 1000 ksps Conversion Rate  
• USB has a Dedicated DMA Channel  
• 10 MHz to 40 MHz Crystal Oscillator  
• Internal 8 MHz and 32 kHz Oscillators  
- Conversion Available During Sleep, Idle  
• Two Analog Comparators  
• 5V Tolerant Input Pins (digital pins only)  
© 2009 Microchip Technology Inc.  
Preliminary  
DS61143F-page 1  
PIC32MX3XX/4XX  
TABLE 1:  
PIC32MX GENERAL PURPOSE – FEATURES  
GENERAL PURPOSE  
Device  
PIC32MX320F032H  
PIC32MX320F064H  
PIC32MX320F128H  
PIC32MX340F128H  
PIC32MX340F256H  
PIC32MX340F512H  
PIC32MX320F128L  
PIC32MX340F128L  
PIC32MX360F256L  
PIC32MX360F512L  
64  
64  
64  
64  
64  
64  
40  
80  
80  
80  
80  
80  
32 + 12(1)  
64 + 12(1)  
8
5/5/5  
5/5/5  
5/5/5  
5/5/5  
5/5/5  
5/5/5  
5/5/5  
5/5/5  
5/5/5  
5/5/5  
0
0
0
4
4
4
0
4
4
4
Yes No  
Yes No  
Yes No  
Yes No  
Yes No  
Yes No  
Yes No  
Yes No  
2/2/2  
2/2/2  
2/2/2  
2/2/2  
2/2/2  
2/2/2  
2/2/2  
2/2/2  
16  
16  
16  
16  
16  
16  
16  
16  
16  
16  
2
2
2
2
2
2
2
2
2
2
Yes Yes PT, MR  
Yes Yes PT, MR  
Yes Yes PT, MR  
Yes Yes PT, MR  
Yes Yes PT, MR  
Yes Yes PT, MR  
16  
16  
32  
32  
32  
16  
32  
32  
32  
128 + 12(1)  
128 + 12(1)  
256 + 12(1)  
512 + 12(1)  
128 + 12(1)  
128 + 12(1)  
256 + 12(1)  
512 + 12(1)  
100 80  
100 80  
100 80  
100 80  
Yes Yes  
Yes Yes  
Yes Yes  
Yes Yes  
PT  
PT  
PT  
PT  
Yes Yes 2/2/2  
Yes Yes 2/2/2  
Legend:  
Note 1: This device features 12 KB Boot Flash memory.  
2: See Legend for an explanation of the acronyms. See Section 29.0 “Packaging Information” for details.  
PT = TQFP  
MR = QFN  
TABLE 2:  
PIC32MX USB – FEATURES  
USB  
Device  
PIC32MX420F032H  
PIC32MX440F128H  
PIC32MX440F256H  
PIC32MX440F512H  
PIC32MX440F128L  
PIC32MX460F256L  
PIC32MX460F512L  
64  
64  
64  
64  
80  
32 + 12(1)  
8
5/5/5  
5/5/5  
5/5/5  
5/5/5  
5/5/5  
5/5/5  
5/5/5  
0
4
4
4
4
4
4
2
2
2
2
2
2
2
Yes No 2/1/2 16  
Yes No 2/1/2 16  
Yes No 2/1/2 16  
Yes No 2/1/2 16  
Yes No 2/2/2 16  
Yes Yes 2/2/2 16  
Yes Yes 2/2/2 16  
2
2
2
2
2
2
2
Yes Yes PT, MR  
80 128 + 12(1) 32  
80 256 + 12(1) 32  
80 512 + 12(1) 32  
Yes Yes  
Yes Yes  
Yes Yes  
Yes Yes  
Yes Yes  
Yes Yes  
PT, MR  
PT, MR  
PT, MR  
PT  
100 80 128 + 12(1) 32  
100 80 256 + 12(1) 32  
100 80 512 + 12(1) 32  
MR = QFN  
PT  
PT  
Legend:  
PT = TQFP  
Note 1: This device features 12 KB Boot Flash memory.  
2: See Legend for an explanation of the acronyms. See Section 29.0 “Packaging Information” for details.  
DS61143F-page 2  
Preliminary  
© 2009 Microchip Technology Inc.  
PIC32MX3XX/4XX  
PIN DIAGRAM:  
64-PIN QFN – GENERAL PURPOSE  
= Pins are up to 5V tolerant  
64-Pin QFN (General Purpose)  
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49  
1
2
3
4
5
6
7
8
9
PMD5/RE5  
PMD6/RE6  
48 SOSCO/T1CK/CN0/RC14  
SOSCI/CN1/RC13  
47  
PMD7/RE7  
46 OC1/RD0  
IC4/PMCS1/PMA14/INT4/RD11  
PMA5/SCK2/CN8/RG6  
PMA4/SDI2/CN9/RG7  
PMA3/SDO2/CN10/RG8  
45  
44  
43  
IC3/PMCS2/PMA15/INT3/RD10  
IC2/U1CTS/INT2/RD9  
42 IC1/RTCC/INT1/RD8  
MCLR  
PMA2/SS2/CN11/RG9  
VSS  
41  
40  
Vss  
PIC32MX3XXH  
OSC2/CLKO/RC15  
VDD 10  
11  
39 OSC1/CLKI/RC12  
38 VDD  
C1IN+/AN5/CN7/RB5  
C1IN-/AN4/CN6/RB4 12  
C2IN+/AN3/CN5/RB3 13  
SCL1/RG2  
37  
36 SDA1/RG3  
14  
PGEC1/AN1/VREF-/CVREF-/CN3/RB1 15  
16  
C2IN-/AN2/SS1/CN4/RB2  
35  
34  
33  
U1RTS/BCLK1/SCK1/INT0/RF6  
U1RX/SDI1/RF2  
PGED1/PMA6/AN0/VREF+/CVREF+/CN2/RB0  
U1TX/SDO1/RF3  
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32  
Note: The metal plane at the bottom of the device is not connected to any pins and is recommended to be connected to  
VSS externally.  
© 2009 Microchip Technology Inc.  
Preliminary  
DS61143F-page 3  
PIC32MX3XX/4XX  
PIN DIAGRAM: 64-PIN TQFP – GENERAL PURPOSE  
64-Pin TQFP (General Purpose)  
= Pins are up to 5V tolerant  
PMD5/RE5  
PMD6/RE6  
SOSCO/T1CK/CN0/RC14  
SOSCI/CN1/RC13  
OC1/RD0  
1
48  
47  
46  
45  
44  
43  
42  
41  
40  
39  
38  
37  
36  
35  
34  
33  
2
PMD7/RE7  
3
PMA5/SCK2/CN8/RG6  
PMA4/SDI2/CN9/RG7  
PMA3/SDO2/CN10/RG8  
MCLR  
IC4/PMCS1/PMA14/INT4/RD11  
IC3/PMCS2/PMA15/INT3/RD10  
IC2/U1CTS/INT2/RD9  
IC1/RTCC/INT1/RD8  
Vss  
4
5
6
7
PMA2/SS2/CN11/RG9  
VSS  
8
PIC32MX3XXH  
OSC2/CLKO/RC15  
OSC1/CLKI/RC12  
VDD  
9
VDD  
10  
11  
12  
13  
14  
15  
16  
C1IN+/AN5/CN7/RB5  
C1IN-/AN4/CN6/RB4  
C2IN+/AN3/CN5/RB3  
C2IN-/AN2/SS1/CN4/RB2  
PGEC1/AN1/VREF-/CVREF-/CN3/RB1  
PGED1/PMA6/AN0/VREF+/CVREF+/CN2/RB0  
SCL1/RG2  
SDA1/RG3  
U1RTS/BCLK1/SCK1/INT0/RF6  
U1RX/SDI1/RF2  
U1TX/SDO1/RF3  
DS61143F-page 4  
Preliminary  
© 2009 Microchip Technology Inc.  
PIC32MX3XX/4XX  
PIN DIAGRAM:  
100-PIN TQFP – GENERAL PURPOSE  
= Pins are up to 5V tolerant  
100-Pin TQFP (General Purpose)  
VSS  
75  
74  
73  
72  
71  
70  
69  
68  
67  
66  
65  
64  
63  
62  
61  
60  
59  
58  
57  
56  
55  
54  
53  
52  
51  
1
2
3
4
5
6
7
8
RG15  
VDD  
SOSCO/T1CK/CN0/RC14  
SOSCI/CN1/RC13  
OC1/RD0  
IC4/PMCS1/PMA14/RD11  
IC3/PMCS2/PMA15/RD10  
IC2/RD9  
IC1/RTCC/RD8  
INT4/RA15  
INT3/RA14  
PMD5/RE5  
PMD6/RE6  
PMD7/RE7  
T2CK/RC1  
T3CK/RC2  
T4CK/RC3  
T5CK/RC4  
9
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
PMA5/SCK2/CN8/RG6  
PMA4/SDI2/CN9/RG7  
PMA3/SDO2/CN10/RG8  
MCLR  
PMA2/SS2/CN11/RG9  
VSS  
VSS  
OSC2/CLKO/RC15  
OSC1/CLKI/RC12  
VDD  
PIC32MX3XXL  
TDO/RA5  
VDD  
TDI/RA4  
SDA2/RA3  
SCL2/RA2  
SCL1/RG2  
SDA1/RG3  
SCK1/INT0/RF6  
SDI1/RF7  
TMS/RA0  
INT1/RE8  
INT2/RE9  
C1IN+/AN5/CN7/RB5  
C1IN-/AN4/CN6/RB4  
C2IN+/AN3/CN5/RB3  
C2IN-/AN2/SS1/CN4/RB2  
PGEC1/AN1/CN3/RB1  
PGED1/AN0/CN2/RB0  
SDO1/RF8  
U1RX/RF2  
U1TX/RF3  
© 2009 Microchip Technology Inc.  
Preliminary  
DS61143F-page 5  
PIC32MX3XX/4XX  
PIN DIAGRAM:  
64-PIN QFN – USB  
= Pins are up to 5V tolerant  
64-Pin QFN (USB)  
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49  
PMD5/RE5  
PMD6/RE6  
1
2
3
4
5
6
7
8
9
10  
11  
12  
13  
14  
15  
16  
48 SOSCO/T1CK/CN0/RC14  
47 SOSCI/CN1/RC13  
PMD7/RE7  
OC1/INT0/RD0  
46  
45  
44  
43  
42  
41  
40  
39  
38  
37  
36  
35  
34  
33  
PMA5/SCK2/CN8/RG6  
PMA4/SDI2/CN9/RG7  
PMA3/SDO2/CN10/RG8  
IC4/PMCS1/PMA14/INT4/RD11  
IC3/PMCS2/PMA15/INT3/SCL1/RD10  
IC2/U1CTS//INT2/SDA1/RD9  
IC1/RTCC/INT1/RD8  
Vss  
MCLR  
PMA2/SS2/CN11/RG9  
PIC32MX4XXH  
VSS  
OSC2/CLKO/RC15  
VDD  
OSC1/CLKI/RC12  
VBUSON/C1IN+/AN5/CN7/RB5  
C1IN-/AN4/CN6/RB4  
VDD  
D+/RG2  
D-/RG3  
VUSB  
C2IN+/AN3/CN5/RB3  
C2IN-/AN2/CN4/RB2  
PGEC1/AN1/VREF-/CVREF-/CN3/RB1  
VBUS  
PGED1/EMUD1/PMA6/AN0/VREF+/CVREF+/CN2/RB0  
USBID/RF3  
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32  
Note: The metal plane at the bottom of the device is not connected to any pins and is recommended to be connected to  
VSS externally.  
DS61143F-page 6  
Preliminary  
© 2009 Microchip Technology Inc.  
PIC32MX3XX/4XX  
PIN DIAGRAM:  
64-PIN TQFP – USB  
= Pins are up to 5V tolerant  
64-Pin TQFP (USB)  
PMD5/RE5  
PMD6/RE6  
PMD7/RE7  
1
48  
47  
46  
45  
44  
43  
42  
41  
40  
39  
38  
37  
36  
35  
34  
33  
SOSCO/T1CK/CN0/RC14  
SOSCI/CN1/RC13  
2
3
OC1/INT0/RD0  
PMA5/SCK2/CN8/RG6  
PMA4/SDI2/CN9/RG7  
PMA3/SDO2/CN10/RG8  
MCLR  
4
IC4/PMCS1/PMA14/INT4/RD11  
IC3/PMCS2/PMA15/INT3/SCL1/RD10  
IC2/U1CTS//INT2/SDA1/RD9  
IC1/RTCC/INT1/RD8  
Vss  
5
6
7
PMA2/SS2/CN11/RG9  
8
PIC32MX4XXH  
VSS  
9
OSC2/CLKO/RC15  
VDD  
10  
11  
12  
13  
14  
15  
16  
OSC1/CLKI/RC12  
VBUSON/C1IN+/AN5/CN7/RB5  
C1IN-/AN4/CN6/RB4  
VDD  
D+/RG2  
D-/RG3  
VUSB  
C2IN+/AN3/CN5/RB3  
C2IN-/AN2/CN4/RB2  
PGEC1/AN1/VREF-/CVREF-/CN3/RB1  
PGED1/EMUD1/PMA6/AN0/VREF+/CVREF+/CN2/RB0  
VBUS  
USBID/RF3  
© 2009 Microchip Technology Inc.  
Preliminary  
DS61143F-page 7  
PIC32MX3XX/4XX  
PIN DIAGRAM:  
100-PIN TQFP – USB  
= Pins are up to 5V tolerant  
100-Pin TQFP (USB)  
RG15  
VDD  
PMD5/RE5  
PMD6/RE6  
PMD7/RE7  
T2CK/RC1  
T3CK/RC2  
T4CK/RC3  
VSS  
75  
74  
73  
72  
71  
70  
69  
68  
67  
66  
65  
64  
63  
62  
61  
60  
59  
58  
57  
56  
55  
54  
53  
52  
51  
1
2
3
4
5
6
7
8
SOSCO/T1CK/CN0/RC14  
SOSCI/CN1/RC13  
SDO1/OC1/INT0/RD0  
IC4/PMCS1/PMA14/RD11  
IC3/SCK1/PMCS2/PMA15/RD10  
IC2/SS1/RD9  
IC1/RTCC/RD8  
SDA1/INT4/RA15  
SCL1/INT3/RA14  
VSS  
OSC2/CLKO/RC15  
OSC1/CLKI/RC12  
VDD  
TDO/RA5  
TDI/RA4  
SDA2/RA3  
SCL2/RA2  
D+/RG2  
D-/RG3  
VUSB  
VBUS  
U1TX/RF8  
U1RX/RF2  
SDI1/T5CK/RC4  
PMA5/SCK2/CN8/RG6  
PMA4/SDI2/CN9/RG7  
PMA3/SDO2/CN10/RG8  
MCLR  
9
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
PIC32MX4XXL  
PMA2/SS2/CN11/RG9  
VSS  
VDD  
TMS/RA0  
INT1/RE8  
INT2/RE9  
VBUSON/C1IN+/AN5/CN7/RB5  
C1IN-/AN4/CN6/RB4  
C2IN+/AN3/CN5/RB3  
C2IN-/AN2/CN4/RB2  
PGEC1/AN1/CN3/RB1  
PGED1/AN0/CN2/RB0  
USBID/RF3  
DS61143F-page 8  
Preliminary  
© 2009 Microchip Technology Inc.  
PIC32MX3XX/4XX  
Table of Contents  
High-Performance 80 MHz MIPS-Based 32-bit Flash Microcontroller 64/100-Pin General Purpose and USB..................................... 1  
1.0 Device Overview ........................................................................................................................................................................ 11  
2.0 Guidelines for Getting Started with 32-bit Microcontrollers ........................................................................................................ 15  
3.0 PIC32MX MCU........................................................................................................................................................................... 19  
4.0 Memory Organization................................................................................................................................................................. 25  
5.0 Flash Program Memory.............................................................................................................................................................. 55  
6.0 Resets ........................................................................................................................................................................................ 57  
7.0 Interrupt Controller ..................................................................................................................................................................... 59  
8.0 Oscillator Configuration.............................................................................................................................................................. 63  
9.0 Prefetch Cache........................................................................................................................................................................... 65  
10.0 Direct Memory Access (DMA) Controller ................................................................................................................................... 67  
11.0 USB On-The-Go (OTG).............................................................................................................................................................. 69  
12.0 I/O Ports ..................................................................................................................................................................................... 71  
13.0 Timer1 ........................................................................................................................................................................................ 73  
14.0 Timers 2, 3, 4, 5 ......................................................................................................................................................................... 75  
15.0 Input Capture.............................................................................................................................................................................. 77  
16.0 Output Compare......................................................................................................................................................................... 79  
17.0 Serial Peripheral Interface (SPI)................................................................................................................................................. 81  
18.0 Inter-Integrated Circuit (I2C™)................................................................................................................................................... 83  
19.0 Universal Asynchronous Receiver Transmitter (UART)............................................................................................................. 85  
20.0 Parallel Master Port (PMP)......................................................................................................................................................... 89  
21.0 Real-Time Clock and Calendar (RTCC)..................................................................................................................................... 91  
22.0 10-bit Analog-to-Digital Converter (ADC)................................................................................................................................... 93  
23.0 Comparator ................................................................................................................................................................................ 95  
24.0 Comparator Voltage Reference (CVref)..................................................................................................................................... 97  
25.0 Power-Saving Features.............................................................................................................................................................. 99  
26.0 Special Features ...................................................................................................................................................................... 101  
27.0 Instruction Set .......................................................................................................................................................................... 113  
28.0 Development Support............................................................................................................................................................... 121  
28.0 Electrical Characteristics.......................................................................................................................................................... 119  
29.0 Packaging Information.............................................................................................................................................................. 157  
INDEX................................................................................................................................................................................................ 167  
Worldwide Sales and Service ............................................................................................................................................................ 170  
© 2009 Microchip Technology Inc.  
Preliminary  
DS61143F-page 9  
PIC32MX3XX/4XX  
TO OUR VALUED CUSTOMERS  
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DS61143F-page 10  
Preliminary  
© 2009 Microchip Technology Inc.  
PIC32MX3XX/4XX  
This document contains device-specific information for  
the PIC32MX3XX/4XX devices.  
1.0  
DEVICE OVERVIEW  
Note:  
This data sheet summarizes the features of  
the PIC32MX3XX/4XX family of devices. It  
is not intended to be a comprehensive  
reference source. To complement the  
information in this data sheet, refer to the  
appropriate section of the “PIC32MX  
Family Reference Manual”, which is  
available from the Microchip web site  
(www.microchip.com/PIC32)  
Figure 1-1 shows a general block diagram of the core  
and peripheral modules in the PIC32MX3XX/4XX fam-  
ilies of devices.  
Table 1-1 lists the functions of the various pins shown  
in the pinout diagrams.  
(1,2)  
FIGURE 1-1:  
BLOCK DIAGRAM  
VDDCORE/VCAP  
OSC2/CLKO  
OSC1/CLKI  
OSC/SOSC  
Oscillators  
Power-up  
VDD,VSS  
Timer  
FRC/LPRC  
Oscillators  
MCLR  
ENVREG  
Oscillator  
Start-up Timer  
Voltage  
Regulator  
PLL  
Power-on  
Reset  
Precision  
Band Gap  
Reference  
DIVIDERS  
PLL-USB  
Watchdog  
Timer  
USBCLK  
SYSCLK  
PBCLK  
Brown-out  
Reset  
Timing  
Generation  
Peripheral Bus Clocked by SYSCLK  
CN1-22  
PORTA  
PORTB  
PORTC  
PORTD  
PORTE  
PORTF  
PORTG  
Timer1-5  
Priority  
Interrupt  
Controller  
JTAG  
BSCAN  
PWM  
OC 1-5  
DMAC  
USB  
ICD  
32  
EJTAG  
®
INT  
IC 1-5  
SPI 1,2  
I2C 1,2  
®
MIPS 32 M4K CPU Core  
IS  
DS  
32  
Bus Matrix  
32  
32  
32  
32  
32  
32  
32  
32  
32  
Prefetch  
Module  
Peripheral Bridge  
Data RAM  
PMP  
10-bit ADC  
UART 1,2  
RTCC  
128  
128-bit wide  
Program Flash Memory  
Comparators  
Note 1: Some features are not available on all device variants.  
2: BOR functionality is provided when the on-board voltage regulator is enabled.  
© 2009 Microchip Technology Inc.  
Preliminary  
DS61143F-page 11  
PIC32MX3XX/4XX  
TABLE 1-1:  
Pin Name  
PINOUT I/O DESCRIPTIONS  
Pin  
Buffer  
Type  
Description  
Type  
AN0-AN15  
CLKI  
I
I
Analog Analog input channels.  
ST/CMOS External clock source input. Always associated with OSC1 pin function.  
Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator  
CLKO  
O
—
mode. Optionally functions as CLKO in RC and EC modes. Always associated  
with OSC2 pin function.  
OSC1  
OSC2  
I
ST/CMOS Oscillator crystal input. ST buffer when configured in RC mode;  
CMOS otherwise.  
I/O  
—
Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator  
mode. Optionally functions as CLKO in RC and EC modes.  
SOSCI  
I
ST/CMOS 32.768 kHz low-power oscillator crystal input; CMOS otherwise.  
SOSCO  
O
—
32.768 kHz low-power oscillator crystal output.  
CN0-CN21  
I
ST  
Change notification inputs.  
Can be software programmed for internal weak pull-ups on all inputs.  
IC1-IC5  
I
ST  
Capture inputs 1-5.  
OCFA  
OC1-OC5  
OCFB  
I
O
I
ST  
—
ST  
Compare Fault A input.  
Compare outputs 1 through 5.  
Output Compare Fault B Input.  
INT0  
INT1  
INT2  
INT3  
INT4  
I
I
I
I
I
ST  
ST  
ST  
ST  
ST  
External interrupt 0.  
External interrupt 1.  
External interrupt 2.  
External interrupt 3.  
External interrupt 4.  
RA0-RA15  
RB0-RB15  
RC0-RC15  
RD0-RD15  
RE0-RE15  
RF0-RF15  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
ST  
ST  
ST  
ST  
ST  
ST  
ST  
PORTA is a bidirectional I/O port.  
PORTB is a bidirectional I/O port.  
PORTC is a bidirectional I/O port.  
PORTD is a bidirectional I/O port.  
PORTE is a bidirectional I/O port.  
PORTF is a bidirectional I/O port.  
PORTG is a bidirectional I/O port.  
RG0, RG1,  
RG4-RG15  
RG2, RG3  
I
ST  
PORTG input pins.  
T1CK  
T2CK  
T3CK  
T4CK  
T5CK  
I
I
I
I
I
ST  
ST  
ST  
ST  
ST  
Timer1 external clock input.  
Timer2 external clock input.  
Timer3 external clock input.  
Timer4 external clock input.  
Timer5 external clock input.  
U1CTS  
U1RTS  
U1RX  
I
O
I
ST  
—
ST  
—
UART1 clear to send.  
UART1 ready to send.  
UART1 receive.  
U1TX  
O
UART1 transmit.  
U2CTS  
U2RTS  
U2RX  
I
O
I
ST  
—
ST  
—
UART2 clear to send.  
UART2 ready to send.  
UART2 receive.  
U2TX  
O
UART2 transmit.  
Legend: CMOS = CMOS compatible input or output  
ST = Schmitt Trigger input with CMOS levels  
TTL = TTL input buffer  
Analog = Analog input  
O = Output  
P = Power  
I = Input  
DS61143F-page 12  
Preliminary  
© 2009 Microchip Technology Inc.  
PIC32MX3XX/4XX  
TABLE 1-1:  
Pin Name  
PINOUT I/O DESCRIPTIONS (CONTINUED)  
Pin  
Buffer  
Type  
Description  
Type  
SCK1  
SDI1  
SDO1  
SS1  
I/O  
I
O
ST  
ST  
—
Synchronous serial clock input/output for SPI1.  
SPI1 data in.  
SPI1 data out.  
SPI1 slave synchronization or frame pulse I/O.  
I/O  
ST  
SCK2  
SDI2  
SDO2  
SS2  
I/O  
I
O
ST  
ST  
—
Synchronous serial clock input/output for SPI2.  
SPI2 data in.  
SPI2 data out.  
I/O  
ST  
SPI2 slave synchronization or frame pulse I/O.  
SCL1  
SDA1  
I/O  
I/O  
ST  
ST  
Synchronous serial clock input/output for I2C1.  
Synchronous serial data input/output for I2C1.  
TMS  
TCK  
TDI  
I
I
I
ST  
ST  
ST  
—
JTAG Test mode select pin.  
JTAG test clock input pin.  
JTAG test data input pin.  
JTAG test data output pin.  
TDO  
O
RTCC  
O
—
Real-Time Clock Alarm Output.  
CVREF–  
CVREF+  
CVREFOUT  
I
I
O
ANA  
ANA  
ANA  
Comparator Voltage Reference (low).  
Comparator Voltage Reference (high).  
Comparator Voltage Reference Output.  
C1IN-  
C1IN+  
C1OUT  
I
I
O
ANA  
ANA  
—
Comparator 1 Negative Input.  
Comparator 1 Positive Input.  
Comparator 1 Output.  
C2IN-  
C2IN+  
C2OUT  
I
I
O
ANA  
ANA  
—
Comparator 2 Negative Input.  
Comparator 2 Positive Input.  
Comparator 2 Output.  
PMA0  
I/O  
TTL/ST Parallel Master Port Address Bit 0 Input (Buffered Slave modes) and Output  
(Master modes).  
PMA1  
I/O  
TTL/ST Parallel Master Port Address Bit 1 Input (Buffered Slave modes) and Output  
(Master modes).  
PMA2-PMPA15  
PMENB  
PMCS1  
O
O
O
—
—
—
—
Parallel Master Port Address (Demultiplexed Master Modes).  
Parallel Master Port Enable Strobe (Master mode 1).  
Parallel Master Port Chip Select 1 Strobe.  
PMCS2  
O
Parallel Master Port Chip Select 2 Strobe.  
PMD0-PMD15  
I/O  
TTL/ST Parallel Master Port Data (Demultiplexed Master mode) or Address/Data  
(Multiplexed Master modes).  
PMRD  
PMWR  
PMALL  
O
O
O
—
—
—
Parallel Master Port Read Strobe.  
Parallel Master Port Write Strobe.  
Parallel Master Port Address Latch Enable low-byte (Multiplexed Master  
modes).  
PMALH  
O
—
Parallel Master Port Address Latch Enable high-byte (Multiplexed Master  
modes).  
PMRD/PMWR  
PMALL  
O
O
—
—
Parallel Master Port Read/Write Strobe (Master mode 1).  
Parallel Master Port Address Latch Enable low-byte (Multiplexed Master  
modes).  
PMALH  
O
O
—
—
Parallel Master Port Address Latch Enable high-byte (Multiplexed Master  
modes).  
Parallel Master Port Read/Write Strobe (Master mode 1).  
PMRD/PMWR  
Legend: CMOS = CMOS compatible input or output  
ST = Schmitt Trigger input with CMOS levels  
TTL = TTL input buffer  
Analog = Analog input  
O = Output  
P = Power  
I = Input  
© 2009 Microchip Technology Inc.  
Preliminary  
DS61143F-page 13  
PIC32MX3XX/4XX  
TABLE 1-1:  
Pin Name  
PINOUT I/O DESCRIPTIONS (CONTINUED)  
Pin  
Buffer  
Type  
Description  
Type  
VBUS  
VUSB  
VBUSON  
D+  
D–  
USBID  
I
P
O
I/O  
I/O  
I
ANA  
—
—
ANA  
ANA  
ST  
USB Bus Power Monitor.  
USB Internal Transceiver Supply.  
USB Host and OTG Bus Power Control Output.  
USB D+.  
USB D–.  
USB OTG ID Detect.  
ENVREG  
I
ST  
Enable for On-Chip Voltage Regulator.  
TRCLK  
TRD0-TRD3  
O
O
—
—
Trace Clock.  
Trace Data Bits 0-3  
PGED1  
PGEC1  
PGED2  
PGEC2  
I/O  
ST  
ST  
ST  
ST  
Data I/O pin for programming/debugging communication channel 1.  
Clock input pin for programming/debugging communication channel 1.  
Data I/O pin for programming/debugging communication channel 2.  
Clock input pin for programming/debugging communication channel 2.  
I
I/O  
I
MCLR  
AVdd  
I/P  
P
P
P
P
P
I
ST  
P
Master Clear (Reset) input. This pin is an active-low Reset to the device.  
Positive supply for analog modules. This pin must be connected at all times.  
Ground reference for analog modules.  
AVss  
P
Vdd  
—
—
—
Positive supply for peripheral logic and I/O pins.  
CPU logic filter capacitor connection.  
Vcap/Vddcore  
Vss  
Ground reference for logic and I/O pins.  
VREF+  
VREF-  
Analog Analog voltage reference (high) input.  
Analog Analog voltage reference (low) input.  
I
Legend: CMOS = CMOS compatible input or output  
ST = Schmitt Trigger input with CMOS levels  
TTL = TTL input buffer  
Analog = Analog input  
O = Output  
P = Power  
I = Input  
DS61143F-page 14  
Preliminary  
© 2009 Microchip Technology Inc.  
PIC32MX3XX/4XX  
2.2  
Decoupling Capacitors  
2.0  
GUIDELINES FOR GETTING  
STARTED WITH 32-BIT  
MICROCONTROLLERS  
The use of decoupling capacitors on every pair of  
power supply pins, such as VDD, VSS, AVDD, and  
AVSS is required. See Figure 2-1.  
Note:  
This data sheet summarizes the features of  
the PIC32MX3XX/4XX family of devices. It  
is not intended to be a comprehensive  
reference source. Refer to the “PIC32MX  
Family Reference Manual” for a detailed  
description of the PIC32MX MCU.  
Consider the following criteria when using decoupling  
capacitors:  
• Value and type of capacitor: Recommendation  
of 0.1 µF (100 nF), 10-20V. This capacitor should  
be a low-ESR and have resonance frequency in  
the range of 20 MHz and higher. It is  
The manual is available from the Microchip  
web site (www.Microchip.com/PIC32).  
recommended that ceramic capacitors be used.  
• Placement on the printed circuit board: The  
decoupling capacitors should be placed as close  
to the pins as possible. It is recommended to  
place the capacitors on the same side of the  
board as the device. If space is constricted, the  
capacitor can be placed on another layer on the  
PCB using a via; however, ensure that the trace  
length from the pin to the capacitor is within one-  
quarter inch (6 mm) in length.  
2.1  
Basic Connection Requirements  
Getting started with the PIC32MX3XX/4XX family of  
32-bit Microcontrollers (MCU) requires attention to a  
minimal set of device pin connections before  
proceeding with development. The following is a list of  
pin names, which must always be connected:  
• All VDD and VSS pins  
(see Section 2.2)  
• Handling high frequency noise: If the board is  
experiencing high frequency noise, upward of  
tens of MHz, add a second ceramic-type capacitor  
in parallel to the above described decoupling  
capacitor. The value of the second capacitor can  
be in the range of 0.01 µF to 0.001 µF. Place this  
second capacitor next to the primary decoupling  
capacitor. In high-speed circuit designs, consider  
implementing a decade pair of capacitances as  
close to the power and ground pins as possible.  
For example, 0.1 µF in parallel with 0.001 µF.  
• All AVDD and AVSS pins (regardless if ADC module  
is not used)  
(see Section 2.2)  
• VCAP/VDDCORE  
(see Section 2.3)  
• MCLR pin  
(see Section 2.4)  
• PGECx/PGEDx pins used for In-Circuit Serial  
Programming™ (ICSP™) and debugging purposes  
(see Section 2.5)  
• Maximizing performance: On the board layout  
from the power supply circuit, run the power and  
return traces to the decoupling capacitors first,  
and then to the device pins. This ensures that the  
decoupling capacitors are first in the power chain.  
Equally important is to keep the trace length  
between the capacitor and the power pins to a  
minimum thereby reducing PCB track inductance.  
• OSC1 and OSC2 pins when external oscillator  
source is used  
(see Section 2.8)  
Additionally, the following pins may be required:  
• VREF+/VREF- pins used when external voltage  
reference for ADC module is implemented  
Note:  
The AVDD and AVSS pins must be  
connected independent of ADC use and  
ADC voltage reference source.  
© 2009 Microchip Technology Inc.  
Preliminary  
DS61143F-page 15  
PIC32MX3XX/4XX  
FIGURE 2-1:  
RECOMMENDED  
MINIMUM CONNECTION  
2.4  
Master Clear (MCLR) Pin  
The MCLR pin provides for two specific device  
functions:  
0.1 µF  
Ceramic  
CBP  
• Device Reset  
VDD  
• Device Programming and Debugging  
Pulling The MCLR pin low generates a device reset.  
Figure 2-2 shows a typical MCLR circuit. During  
device programming and debugging, the resistance  
and capacitance that can be added to the pin must  
be considered. Device programmers and debuggers  
drive the MCLR pin. Consequently, specific voltage  
levels (VIH and VIL) and fast signal transitions must  
not be adversely affected. Therefore, specific values  
of R and C will need to be adjusted based on the  
application and PCB requirements.  
R
R1  
MCLR  
C
PIC32MX  
VDD  
VSS  
VDD  
VSS  
0.1 µF  
Ceramic  
CBP  
0.1 µF  
Ceramic  
CBP  
For example, as shown in Figure 2-2, it is  
recommended that the capacitor C, be isolated from  
the MCLR pin during programming and debugging  
operations.  
0.1 µF  
Ceramic  
CBP  
0.1 µF  
Ceramic  
CBP  
10 Ω  
Place the components shown in Figure 2-2 within  
one-quarter inch (6 mm) from the MCLR pin.  
2.2.1  
BULK CAPACITORS  
The use of a bulk capacitor is recommended to improve  
power supply stability. Typical values range from 4.7 µF  
to 47 µF. This capacitor should be located as close to  
the device as possible.  
FIGURE 2-2:  
EXAMPLE OF MCLR PIN  
CONNECTIONS  
VDD  
2.3  
Capacitor on Internal Voltage  
Regulator (VCAP/VDDCORE)  
R
R1  
MCLR  
2.3.1  
INTERNAL REGULATOR MODE  
PIC32MX  
JP  
C
A low-ESR (< 5 Ohms) capacitor is required on the  
VCAP/VDDCORE pin, which is used to stabilize the  
internal voltage regulator output. The VCAP/VDDCORE  
pin must not be connected to VDD, and must have a  
10 µF capacitor, with at least a 6V rating, connected to  
ground. The type can be ceramic or tantalum. Refer to  
Section 28.0 "Electrical Characteristics" for  
additional information. This mode is enabled by  
connecting the ENVREG pin to VDD.  
Note 1: R ≤ 10 kΩ is recommended. A suggested  
starting value is 10 kΩ. Ensure that the MCLR  
pin VIH and VIL specifications are met.  
2: R1 ≤ 470Ω will limit any current flowing into  
MCLR from the external capacitor C, in the  
event of MCLR pin breakdown, due to  
Electrostatic Discharge (ESD) or Electrical  
Overstress (EOS). Ensure that the MCLR pin  
VIH and VIL specifications are met.  
2.3.2  
EXTERNAL REGULATOR MODE  
In this mode the core voltage is supplied externally  
through the VDDCORE pin. A low-ESR capacitor of  
10 µF is recommended on the VDDCORE pin. This mode  
is enabled by grounding the ENVREG pin.  
3: The capacitor can be sized to prevent uninten-  
tional resets from brief glitches or to extend the  
device reset period during POR.  
The placement of this capacitor should be close to the  
VCAP/VDDCORE. It is recommended that the trace  
length not exceed one-quarter inch (6 mm). Refer to  
Section 26.3 "On-Chip Voltage Regulator" for  
details.  
DS61143F-page 16  
Preliminary  
© 2009 Microchip Technology Inc.  
PIC32MX3XX/4XX  
Pull-up resistors, series diodes, and capacitors on the  
TMS, TDO, TDI, and TCK pins are not recommended  
as they will interfere with the programmer/debugger  
communications to the device. If such discrete compo-  
nents are an application requirement, they should be  
removed from the circuit during programming and  
debugging. Alternately, refer to the AC/DC characteris-  
tics and timing requirements information in the respec-  
tive device Flash programming specification for  
information on capacitive loading limits and pin input  
voltage high (VIH) and input low (VIL) requirements.  
2.5  
ICSP Pins  
The PGECx and PGEDx pins are used for In-Circuit  
Serial Programming™ (ICSP™) and debugging pur-  
poses. It is recommended to keep the trace length  
between the ICSP connector and the ICSP pins on the  
device as short as possible. If the ICSP connector is  
expected to experience an ESD event, a series resistor  
is recommended, with the value in the range of a few  
tens of Ohms, not to exceed 100 Ohms.  
Pull-up resistors, series diodes, and capacitors on the  
PGECx and PGEDx pins are not recommended as they  
will interfere with the programmer/debugger communi-  
cations to the device. If such discrete components are  
an application requirement, they should be removed  
from the circuit during programming and debugging.  
Alternately, refer to the AC/DC characteristics and tim-  
ing requirements information in the respective device  
Flash programming specification for information on  
capacitive loading limits and pin input voltage high (VIH)  
and input low (VIL) requirements.  
2.7  
Trace  
The trace pins can be connected to a hardware-trace-  
enabled programmer to provide a compress real time  
instruction trace. When used for trace the TRD3,  
TRD2, TRD1, TRD0, and TRCLK pins should be dedi-  
cated for this use. The trace hardware requires a 22  
Ohm series resistor between the trace pins and the  
trace connector.  
Ensure that the “Communication Channel Select” (i.e.,  
PGECx/PGEDx pins) programmed into the device  
matches the physical connections for the ICSP to  
MPLAB® ICD 2, MPLAB® ICD 3, or MPLAB® REAL  
ICE™.  
2.8  
External Oscillator Pins  
Many MCUs have options for at least two oscillators: a  
high-frequency primary oscillator and a low-frequency  
secondary oscillator (refer to Section 8.0 "Oscillator  
Configuration" for details).  
For more information on ICD 2, ICD 3, and REAL ICE  
connection requirements, refer to the following  
documents that are available on the Microchip website.  
• “MPLAB® ICD 2 In-Circuit Debugger User's  
Guide” DS51331  
• “Using MPLAB® ICD 2” (poster) DS51265  
• “MPLAB® ICD 2 Design Advisory” DS51566  
• “Using MPLAB® ICD 3” (poster) DS51765  
• “MPLAB® ICD 3 Design Advisory” DS51764  
• “MPLAB® REAL ICE™ In-Circuit Debugger  
User's Guide” DS51616  
The oscillator circuit should be placed on the same  
side of the board as the device. Also, place the  
oscillator circuit close to the respective oscillator pins,  
not exceeding one-half inch (12 mm) distance  
between them. The load capacitors should be placed  
next to the oscillator itself, on the same side of the  
board. Use a grounded copper pour around the  
oscillator circuit to isolate them from surrounding  
circuits. The grounded copper pour should be routed  
directly to the MCU ground. Do not run any signal  
traces or power traces inside the ground pour. Also, if  
using a two-sided board, avoid any traces on the  
other side of the board where the crystal is placed. A  
suggested layout is shown in Figure 2-3.  
• “Using MPLAB® REAL ICE™” (poster) DS51749  
2.6  
JTAG  
The TMS, TDO, TDI, and TCK pins are used for testing  
and debugging according to the Joint Test Action  
Group (JTAG) standard. It is recommended to keep the  
trace length between the JTAG connector and the  
JTAG pins on the device as short as possible. If the  
JTAG connector is expected to experience an ESD  
event, a series resistor is recommended, with the value  
in the range of a few tens of Ohms, not to exceed 100  
Ohms.  
FIGURE 2-3:  
SUGGESTED PLACEMENT  
OF THE OSCILLATOR  
CIRCUIT  
Oscillator  
Secondary  
Guard Trace  
Guard Ring  
Main Oscillator  
© 2009 Microchip Technology Inc.  
Preliminary  
DS61143F-page 17  
PIC32MX3XX/4XX  
2.9  
Configuration of Analog and  
Digital Pins During ICSP  
Operations  
2.10 Unused I/Os  
Unused I/O pins should not be allowed to float as  
inputs. They can be configured as outputs and driven  
to a logic-low state.  
If MPLAB ICD 2, ICD 3, or REAL ICE is selected as a  
debugger, it automatically initializes all of the A/D input  
pins (ANx) as “digital” pins by setting all bits in the  
ADPCFG register.  
Alternately, inputs can be reserved by connecting the  
pin to VSS through a 1k to 10k resistor and configuring  
the pin as an input.  
The bits in this register that correspond to the A/D pins  
that are initialized by MPLAB ICD 2, ICD 3, or REAL  
ICE, must not be cleared by the user application  
firmware; otherwise, communication errors will result  
between the debugger and the device.  
If your application needs to use certain A/D pins as  
analog input pins during the debug session, the user  
application must clear the corresponding bits in the  
ADPCFG register during initialization of the ADC  
module.  
When MPLAB ICD 2, ICD 3, or REAL ICE is used as a  
programmer, the user application firmware must  
correctly configure the ADPCFG register. Automatic  
initialization of this register is only done during  
debugger operation. Failure to correctly configure the  
register(s) will result in all A/D pins being recognized as  
analog input pins, resulting in the port value being read  
as a logic '0', which may affect user application  
functionality.  
DS61143F-page 18  
Preliminary  
© 2009 Microchip Technology Inc.  
PIC32MX3XX/4XX  
• MIPS16e™ Code Compression  
3.0  
PIC32MX MCU  
- 16-bit encoding of 32-bit instructions to  
improve code density  
Note:  
This data sheet summarizes the features of  
the PIC32MX3XX/4XX Family of devices. It  
is not intended to be a comprehensive  
reference source. Refer to the “PIC32MX  
Family Reference Manual” Section 2.  
“MCU” (DS61113) for a detailed description  
of the PIC32MX MCU. The manual is  
available from the Microchip web site  
(www.Microchip.com/PIC32). Resources for  
the MIPS32® M4K® Processor Core are  
- Special PC-relative instructions for efficient  
loading of addresses and constants  
- SAVE & RESTORE macro instructions for  
setting up and tearing down stack frames  
within subroutines  
- Improved support for handling 8 and 16-bit  
data types  
• Simple Fixed Mapping Translation (FMT)  
mechanism  
available  
at  
www.mips.com/prod-  
ucts/cores/32-bit-cores/ mips32-m4k/#.  
• Simple Dual Bus Interface  
- Independent 32-bit address and data busses  
The MCU module is the heart of the PIC32MX3XX/4XX  
Family processor. The MCU fetches instructions,  
decodes each instruction, fetches source operands,  
executes each instruction, and writes the results of  
instruction execution to the proper destinations.  
- Transactions can be aborted to improve  
interrupt latency  
• Autonomous Multiply/Divide Unit  
- Maximum issue rate of one 32x16 multiply  
per clock  
3.1  
Features  
- Maximum issue rate of one 32x32 multiply  
every other clock  
• 5-stage pipeline  
- Early-in iterative divide. Minimum 11 and  
maximum 34 clock latency (dividend (rs) sign  
extension-dependent)  
• 32-bit Address and Data Paths  
• MIPS32 Enhanced Architecture (Release 2)  
- Multiply-Accumulate and Multiply-Subtract  
Instructions  
• Power Control  
- Minimum frequency: 0 MHz  
- Targeted Multiply Instruction  
- Zero/One Detect Instructions  
- WAITInstruction  
- Low-Power mode (triggered by WAIT  
instruction)  
- Extensive use of local gated clocks  
• EJTAG Debug and Instruction Trace  
- Support for single stepping  
- Conditional Move Instructions (MOVN, MOVZ)  
- Vectored interrupts  
- Programmable exception vector base  
- Atomic interrupt enable/disable  
- Virtual instruction and data address/value  
-
breakpoints  
- GPR shadow registers to minimize latency  
for interrupt handlers  
- PC tracing with trace compression  
- Bit field manipulation instructions  
FIGURE 3-1:  
MCU BLOCK DIAGRAM  
Trace I/F  
EJTAG  
Trace  
TAP  
Off-Chip  
Debug I/F  
MDU  
Execution  
Core  
(RF/ALU/Shift)  
FMT  
Bus Interface  
Dual Bus I/F  
System  
Coprocessor  
Power  
Mgmt  
© 2009 Microchip Technology Inc.  
Preliminary  
DS61143F-page 19  
PIC32MX3XX/4XX  
3.2.2  
MULTIPLY/DIVIDE UNIT (MDU)  
3.2  
Architecture Overview  
The PIC32MX3XX/4XX Family core includes a multi-  
ply/divide unit (MDU) that contains a separate pipeline  
for multiply and divide operations. This pipeline oper-  
ates in parallel with the integer unit (IU) pipeline and  
does not stall when the IU pipeline stalls. This allows  
MDU operations to be partially masked by system stalls  
and/or other integer unit instructions.  
The PIC32MX3XX/4XX Family core contains several  
logic blocks working together in parallel, providing an  
efficient high performance computing engine. The fol-  
lowing blocks are included with the core:  
•
•
•
•
•
•
•
•
Execution Unit  
Multiply/Divide Unit (MDU)  
System Control Coprocessor (CP0)  
Fixed Mapping Translation (FMT)  
Dual Internal Bus interfaces  
Power Management  
The high-performance MDU consists of a 32x16 booth  
recoded multiplier, result/accumulation registers (HI  
and LO), a divide state machine, and the necessary  
multiplexers and control logic. The first number shown  
(‘32’ of 32x16) represents the rs operand. The second  
number (‘16’ of 32x16) represents the rt operand. The  
PIC32MX core only checks the value of the latter (rt)  
operand to determine how many times the operation  
must pass through the multiplier. The 16x16 and 32x16  
operations pass through the multiplier once. A 32x32  
operation passes through the multiplier twice.  
MIPS16e Support  
Enhanced JTAG (EJTAG) Controller  
3.2.1  
EXECUTION UNIT  
The PIC32MX3XX/4XX Family core execution unit  
implements a load/store architecture with single-cycle  
ALU operations (logical, shift, add, subtract) and an  
autonomous multiply/divide unit. The core contains  
thirty-two 32-bit general purpose registers used for  
integer operations and address calculation. One addi-  
tional register file shadow set (containing thirty-two reg-  
isters) is added to minimize context switching overhead  
during interrupt/exception processing. The register file  
consists of two read ports and one write port and is fully  
bypassed to minimize operation latency in the pipeline.  
The MDU supports execution of one 16x16 or 32x16  
multiply operation every clock cycle; 32x32 multiply  
operations can be issued every other clock cycle.  
Appropriate interlocks are implemented to stall the  
issuance of back-to-back 32x32 multiply operations.  
The multiply operand size is automatically determined  
by logic built into the MDU.  
Divide operations are implemented with a simple 1 bit  
per clock iterative algorithm. An early-in detection  
checks the sign extension of the dividend (rs) operand.  
If rs is 8 bits wide, 23 iterations are skipped. For a 16-  
bit-wide rs, 15 iterations are skipped, and for a 24-bit-  
wide rs, 7 iterations are skipped. Any attempt to issue  
a subsequent MDU instruction while a divide is still  
active causes an IU pipeline stall until the divide oper-  
ation is completed.  
The execution unit includes:  
•
•
32-bit adder used for calculating the data address  
Address unit for calculating the next instruction  
address  
•
Logic for branch determination and branch target  
address calculation  
•
•
Load aligner  
Table 3-1 lists the repeat rate (peak issue rate of cycles  
until the operation can be reissued) and latency (num-  
ber of cycles until a result is available) for the PIC32MX  
core multiply and divide instructions. The approximate  
latency and repeat rates are listed in terms of pipeline  
clocks.  
Bypass multiplexers used to avoid stalls when  
executing instructions streams where data  
producing instructions are followed closely by  
consumers of their results  
•
•
•
Leading Zero/One detect unit for implementing the  
CLZand CLOinstructions  
Arithmetic Logic Unit (ALU) for performing bitwise  
logical operations  
Shifter and Store Aligner  
DS61143F-page 20  
Preliminary  
© 2009 Microchip Technology Inc.  
PIC32MX3XX/4XX  
TABLE 3-1:  
PIC32MX3XX/4XX FAMILY CORE HIGH-PERFORMANCE INTEGER  
MULTIPLY/DIVIDE UNIT LATENCIES AND REPEAT RATES  
Opcode  
Operand Size (mul rt) (div rs)  
Latency  
Repeat Rate  
MULT/MULTU, MADD/MADDU,  
MSUB/MSUBU  
16 bits  
32 bits  
16 bits  
32 bits  
8 bits  
1
2
1
2
MUL  
2
1
3
2
DIV/DIVU  
12  
19  
26  
33  
11  
18  
25  
32  
16 bits  
24 bits  
32 bits  
The MIPS architecture defines that the result of a mul-  
tiply or divide operation be placed in the HI and LO reg-  
isters. Using the Move-From-HI (MFHI) and Move-  
From-LO (MFLO) instructions, these values can be  
transferred to the general purpose register file.  
the product to the current contents of the HI and LO  
registers. Similarly, the MSUBinstruction multiplies two  
operands and then subtracts the product from the HI  
and LO registers. The MADD and MSUB operations  
are commonly used in DSP algorithms.  
In addition to the HI/LO targeted operations, the  
MIPS32 architecture also defines a multiply instruction,  
MUL, which places the least significant results in the  
primary register file instead of the HI/LO register pair.  
By avoiding the explicit MFLO instruction, required  
when using the LO register, and by supporting multiple  
destination registers, the throughput of multiply-inten-  
sive operations is increased.  
3.2.3  
SYSTEM CONTROL  
COPROCESSOR (CP0)  
In the MIPS architecture, CP0 is responsible for the vir-  
tual-to-physical address translation, the exception con-  
trol system, the processor’s diagnostics capability, the  
operating modes (kernel, user, and debug), and  
whether interrupts are enabled or disabled. Configura-  
tion information, such as presence of options like  
MIPS16e, is also available by accessing the CP0 reg-  
isters, listed in Table 3-2.  
Two other instructions, multiply-add (MADD) and multi-  
ply-subtract (MSUB), are used to perform the multiply-  
accumulate and multiply-subtract operations. The  
MADDinstruction multiplies two numbers and then adds  
TABLE 3-2:  
COPROCESSOR 0 REGISTERS  
Register Register  
Number Name  
Function  
0-6  
7
Reserved  
HWREna  
BadVAddr(1)  
Count(1)  
Reserved  
Compare(1)  
Status(1)  
IntCtl(1)  
SRSCtl(1)  
SRSMap(1)  
Cause(1)  
EPC(1)  
Reserved in the PIC32MX3XX/4XX Family core  
Enables access via the RDHWRinstruction to selected hardware registers  
Reports the address for the most recent address-related exception  
Processor cycle count  
8
9
10  
11  
12  
12  
12  
12  
13  
14  
15  
15  
16  
16  
16  
16  
Reserved in the PIC32MX3XX/4XX Family core  
Timer interrupt control  
Processor status and control  
Interrupt system status and control  
Shadow register set status and control  
Provides mapping from vectored interrupt to a shadow set  
Cause of last general exception  
Program counter at last exception  
Processor identification and revision  
Exception vector base register  
PRId  
EBASE  
Config  
Configuration register  
Config1  
Configuration register 1  
Config2  
Configuration register 2  
Config3  
Configuration register 3  
© 2009 Microchip Technology Inc.  
Preliminary  
DS61143F-page 21  
PIC32MX3XX/4XX  
TABLE 3-2:  
COPROCESSOR 0 REGISTERS (CONTINUED)  
Register Register  
Number Name  
Function  
17-22  
23  
Reserved  
Debug(2)  
Reserved in the PIC32MX3XX/4XX Family core  
Debug control and exception status  
24  
DEPC(2)  
Program counter at last debug exception  
Reserved in the PIC32MX3XX/4XX Family core  
Program counter at last error  
25-29  
30  
Reserved  
ErrorEPC(1)  
DESAVE(2)  
31  
Debug handler scratchpad register  
Note 1: Registers used in exception processing.  
2: Registers used during debug.  
Coprocessor 0 also contains the logic for identifying  
and managing exceptions. Exceptions can be caused  
by a variety of sources, including alignment errors in  
data, external events, or program errors. Table 3-3  
shows the exception types in order of priority.  
TABLE 3-3:  
Exception  
PIC32MX3XX/4XX FAMILY CORE EXCEPTION TYPES  
Description  
Assertion MCLR or a Power-On Reset (POR)  
Reset  
DSS  
EJTAG Debug Single Step  
DINT  
EJTAG Debug Interrupt. Caused by the assertion of the external EJ_DINT input, or by setting the  
EjtagBrk bit in the ECR register  
NMI  
Interrupt  
DIB  
Assertion of NMI signal  
Assertion of unmasked hardware or software interrupt signal  
EJTAG debug hardware instruction break matched  
AdEL  
Fetch address alignment error  
Fetch reference to protected address  
IBE  
DBp  
Sys  
Bp  
Instruction fetch bus error  
EJTAG Breakpoint (execution of SDBBPinstruction)  
Execution of SYSCALLinstruction  
Execution of BREAKinstruction  
RI  
Execution of a Reserved Instruction  
CpU  
CEU  
Ov  
Execution of a coprocessor instruction for a coprocessor that is not enabled  
Execution of a CorExtend instruction when CorExtend is not enabled  
Execution of an arithmetic instruction that overflowed  
Execution of a trap (when trap condition is true)  
Tr  
DDBL / DDBS EJTAG Data Address Break (address only) or EJTAG Data Value Break on Store (address + value)  
AdEL  
Load address alignment error  
Load reference to protected address  
AdES  
Store address alignment error  
Store to protected address  
DBE  
Load or store bus error  
DDBL  
EJTAG data hardware breakpoint matched in load data compare  
DS61143F-page 22  
Preliminary  
© 2009 Microchip Technology Inc.  
PIC32MX3XX/4XX  
3.3  
Power Management  
3.4  
EJTAG Debug Support  
The PIC32MX3XX/4XX Family core offers a number of  
power management features, including low-power  
design, active power management, and power-down  
modes of operation. The core is a static design that  
supports slowing or halting the clocks, which reduces  
system power consumption during idle periods.  
The PIC32MX3XX/4XX Family core provides for an  
Enhanced JTAG (EJTAG) interface for use in the  
software debug of application and kernel code. In  
addition to standard user mode and kernel modes of  
operation, the PIC32MX3XX/4XX Family core provides  
a Debug mode that is entered after a debug exception  
(derived from a hardware breakpoint, single-step  
exception, etc.) is taken and continues until a debug  
exception return (DERET) instruction is executed.  
During this time, the processor executes the debug  
exception handler routine.  
3.3.1  
INSTRUCTION-CONTROLLED  
POWER MANAGEMENT  
The mechanism for invoking power-down mode is  
through execution of the WAIT instruction. For more  
information on power management, see Section 25.0  
“Power-Saving Features”.  
The EJTAG interface operates through the Test Access  
Port (TAP), a serial communication port used for  
transferring test data in and out of the  
PIC32MX3XX/4XX Family core. In addition to the  
standard JTAG instructions, special instructions  
defined in the EJTAG specification define what  
registers are selected and how they are used.  
3.3.2  
LOCAL CLOCK GATING  
The majority of the power consumed by the  
PIC32MX3XX/4XX Family core is in the clock tree and  
clocking registers. The PIC32MX family uses extensive  
use of local gated-clocks to reduce this dynamic power  
consumption.  
© 2009 Microchip Technology Inc.  
Preliminary  
DS61143F-page 23  
PIC32MX3XX/4XX  
NOTES:  
DS61143F-page 24  
Preliminary  
© 2009 Microchip Technology Inc.  
PIC32MX3XX/4XX  
4.1  
PIC32MX3XX/4XX Memory Layout  
4.0  
MEMORY ORGANIZATION  
PIC32MX3XX/4XX microcontrollers implement two  
address spaces: Virtual and Physical. All hardware  
resources such as program memory, data memory, and  
peripherals are located at their respective physical  
addresses. Virtual addresses are exclusively used by  
the CPU to fetch and execute instructions as well as  
access peripherals. Physical addresses are used by  
peripherals such as DMA and Flash controller that  
access memory independently of CPU.  
Note:  
This data sheet summarizes the features of  
the PIC32MX3XX/4XX family of devices. It  
is not intended to be a comprehensive  
reference source. Refer to the “PIC32MX  
Family Reference Manual” Section 3.  
“Memory Organization” (DS61115) for a  
detailed description of this peripheral.  
The manual is available from the Microchip  
web site (www.Microchip.com/PIC32).  
PIC32MX3XX/4XX microcontrollers provide 4 GB of  
unified virtual memory address space. All memory  
regions including program, data memory, SFRs, and  
Configuration registers reside in this address space at  
their respective unique addresses. The program and  
data memories can be optionally partitioned into user  
and kernel memories. In addition, the data memory can  
be made executable, allowing PIC32MX3XX/4XX to  
execute from data memory.  
Key Features:  
• 32-bit native data width  
• Separate User and Kernel mode address space  
• Flexible program Flash memory partitioning  
• Flexible data RAM partitioning for data and  
program space  
• Separate boot Flash memory for protected code  
• Robust bus exception handling to intercept  
runaway code.  
• Simple memory mapping with Fixed Mapping  
Translation (FMT) unit  
• Cacheable and non-cacheable address regions  
© 2009 Microchip Technology Inc.  
Preliminary  
DS61143F-page 25  
PIC32MX3XX/4XX  
FIGURE 4-1:  
MEMORY MAP ON RESET FOR PIC32MX320F032H, PIC32MX420F032H  
DEVICES  
(1)  
Virtual  
Physical  
Memory Map  
Memory Map  
0xFFFFFFFF  
0xBFC03000  
0xBFC02FFF  
0xFFFFFFFF  
Reserved  
Device  
Configuration  
Registers  
0xBFC02FF0  
0xBFC02FEF  
Boot Flash  
Reserved  
SFRs  
0xBFC00000  
0xBF900000  
0xBF8FFFFF  
Reserved  
0xBF800000  
Reserved  
Program Flash(2)  
Reserved  
RAM(2)  
0xBD008000  
0xBD007FFF  
0xBD000000  
0xA0002000  
0xA0001FFF  
0xA0000000  
0x1FC03000  
0x1FC02FFF  
Device  
Configuration  
Registers  
Reserved  
0x9FC02FF0  
0x9FC02FFF  
Device  
Configuration  
Registers  
0x1FC02FF0  
0x1FC02FEF  
0x9FC02FEF  
0x9FC02FEF  
Boot Flash  
Reserved  
SFRs  
0x1FC00000  
Boot Flash  
Reserved  
0x9FC00000  
0x1F900000  
0x1F8FFFFF  
0x9D008000  
0x9D007FFF  
0x1F800000  
Program Flash(2)  
Reserved  
Reserved  
0x9D000000  
0x1D008000  
0x1D007FFF  
0x80002000  
0x80001FFF  
Program Flash(2)  
0x1D000000  
RAM(2)  
Reserved  
RAM(2)  
0x80000000  
0x00000000  
0x00002000  
0x00001FFF  
0x00000000  
Reserved  
Note 1: Memory areas are not shown to scale.  
2: The size of this memory region is programmable (see Section 3. “Memory Organization”  
(DS61115)) and can be changed by initialization code provided by end-user development  
tools (refer to the specific development tool documentation for information).  
DS61143F-page 26  
Preliminary  
© 2009 Microchip Technology Inc.  
PIC32MX3XX/4XX  
(1)  
FIGURE 4-2:  
MEMORY MAP ON RESET FOR PIC32MX320F064H DEVICES  
Virtual  
Physical  
Memory Map  
Memory Map  
0xFFFFFFFF  
0xBFC03000  
0xBFC02FFF  
0xFFFFFFFF  
Reserved  
Device  
Configuration  
Registers  
0xBFC02FF0  
0xBFC02FEF  
Boot Flash  
Reserved  
SFRs  
0xBFC00000  
0xBF900000  
0xBF8FFFFF  
Reserved  
0xBF800000  
Reserved  
Program Flash(2)  
Reserved  
RAM(2)  
0xBD010000  
0xBD00FFFF  
0xBD000000  
0xA0004000  
0xA0003FFF  
0xA0000000  
0x1FC03000  
0x1FC02FFF  
Device  
Configuration  
Registers  
Reserved  
0x9FC02FF0  
0x9FC02FFF  
Device  
Configuration  
Registers  
0x1FC02FF0  
0x1FC02FEF  
0x9FC02FEF  
0x9FC02FEF  
Boot Flash  
Reserved  
SFRs  
0x1FC00000  
Boot Flash  
Reserved  
0x9FC00000  
0x1F900000  
0x1F8FFFFF  
0x9D010000  
0x9D00FFFF  
0x1F800000  
Program Flash(2)  
Reserved  
Reserved  
0x9D000000  
0x1D010000  
0x1D00FFFF  
0x80004000  
0x80003FFF  
Program Flash(2)  
0x1D000000  
RAM(2)  
Reserved  
RAM(2)  
0x80000000  
0x00000000  
0x00004000  
0x00003FFF  
0x00000000  
Reserved  
Note 1: Memory areas are not shown to scale.  
2: The size of this memory region is programmable (see Section 3. “Memory Organization”  
(DS61115)) and can be changed by initialization code provided by end-user development  
tools (refer to the specific development tool documentation for information).  
© 2009 Microchip Technology Inc.  
Preliminary  
DS61143F-page 27  
PIC32MX3XX/4XX  
FIGURE 4-3:  
MEMORY MAP ON RESET FOR PIC32MX320F128H, PIC32MX320F128L  
DEVICES  
(1)  
Virtual  
Physical  
Memory Map  
Memory Map  
0xFFFFFFFF  
0xBFC03000  
0xBFC02FFF  
0xFFFFFFFF  
Reserved  
Device  
Configuration  
Registers  
0xBFC02FF0  
0xBFC02FEF  
Boot Flash  
Reserved  
SFRs  
0xBFC00000  
0xBF900000  
0xBF8FFFFF  
Reserved  
0xBF800000  
Reserved  
Program Flash(2)  
Reserved  
RAM(2)  
0xBD020000  
0xBD01FFFF  
0xBD000000  
0xA0004000  
0xA0003FFF  
0xA0000000  
0x1FC03000  
0x1FC02FFF  
Device  
Configuration  
Registers  
Reserved  
0x9FC02FF0  
0x9FC02FFF  
Device  
Configuration  
Registers  
0x1FC02FF0  
0x1FC02FEF  
0x9FC02FEF  
0x9FC02FEF  
Boot Flash  
Reserved  
SFRs  
0x1FC00000  
Boot Flash  
Reserved  
0x9FC00000  
0x1F900000  
0x1F8FFFFF  
0x9D020000  
0x9D01FFFF  
0x1F800000  
Program Flash(2)  
Reserved  
Reserved  
0x9D000000  
0x1D020000  
0x1D01FFFF  
0x80004000  
0x80003FFF  
Program Flash(2)  
0x1D000000  
RAM(2)  
Reserved  
RAM(2)  
0x80000000  
0x00000000  
0x00004000  
0x00003FFF  
0x00000000  
Reserved  
Note 1: Memory areas are not shown to scale.  
2: The size of this memory region is programmable (see Section 3. “Memory Organization”  
(DS61115)) and can be changed by initialization code provided by end-user development  
tools (refer to the specific development tool documentation for information).  
DS61143F-page 28  
Preliminary  
© 2009 Microchip Technology Inc.  
PIC32MX3XX/4XX  
FIGURE 4-4:  
MEMORY MAP ON RESET FOR PIC32MX340F128H, PIC32MX340F128L,  
PIC32MX440F128H, PIC32MX440F128L DEVICES  
(1)  
Virtual  
Physical  
Memory Map  
Memory Map  
0xFFFFFFFF  
0xBFC03000  
0xBFC02FFF  
0xFFFFFFFF  
Reserved  
Device  
Configuration  
Registers  
0xBFC02FF0  
0xBFC02FEF  
Boot Flash  
Reserved  
SFRs  
0xBFC00000  
0xBF900000  
0xBF8FFFFF  
Reserved  
0xBF800000  
Reserved  
Program Flash(2)  
Reserved  
RAM(2)  
0xBD020000  
0xBD01FFFF  
0xBD000000  
0xA0008000  
0xA0007FFF  
0xA0000000  
0x1FC03000  
0x1FC02FFF  
Device  
Configuration  
Registers  
Reserved  
0x9FC02FF0  
0x9FC02FFF  
Device  
Configuration  
Registers  
0x1FC02FF0  
0x1FC02FEF  
0x9FC02FEF  
0x9FC02FEF  
Boot Flash  
Reserved  
SFRs  
0x1FC00000  
Boot Flash  
Reserved  
0x9FC00000  
0x1F900000  
0x1F8FFFFF  
0x9D020000  
0x9D01FFFF  
0x1F800000  
Program Flash(2)  
Reserved  
Reserved  
0x9D000000  
0x1D020000  
0x1D01FFFF  
0x80008000  
0x80007FFF  
Program Flash(2)  
0x1D000000  
RAM(2)  
Reserved  
RAM(2)  
0x80000000  
0x00000000  
0x00008000  
0x00007FFF  
0x00000000  
Reserved  
Note 1: Memory areas are not shown to scale.  
2: The size of this memory region is programmable (see Section 3. “Memory Organization”  
(DS61115)) and can be changed by initialization code provided by end-user development  
tools (refer to the specific development tool documentation for information).  
© 2009 Microchip Technology Inc.  
Preliminary  
DS61143F-page 29  
PIC32MX3XX/4XX  
FIGURE 4-5:  
MEMORY MAP ON RESET FOR PIC32MX340F256H, PIC32MX360F256L,  
PIC32MX440F256H, PIC32MX460F256L DEVICES  
(1)  
Virtual  
Physical  
Memory Map  
Memory Map  
0xFFFFFFFF  
0xBFC03000  
0xBFC02FFF  
0xFFFFFFFF  
Reserved  
Device  
Configuration  
Registers  
0xBFC02FF0  
0xBFC02FEF  
Boot Flash  
Reserved  
SFRs  
0xBFC00000  
0xBF900000  
0xBF8FFFFF  
Reserved  
0xBF800000  
Reserved  
Program Flash(2)  
Reserved  
RAM(2)  
0xBD040000  
0xBD03FFFF  
0xBD000000  
0xA0008000  
0xA0007FFF  
0xA0000000  
0x1FC03000  
0x1FC02FFF  
Device  
Configuration  
Registers  
Reserved  
0x9FC02FF0  
0x9FC02FFF  
Device  
Configuration  
Registers  
0x1FC02FF0  
0x1FC02FEF  
0x9FC02FEF  
0x9FC02FEF  
Boot Flash  
Reserved  
SFRs  
0x1FC00000  
Boot Flash  
Reserved  
0x9FC00000  
0x1F900000  
0x1F8FFFFF  
0x9D040000  
0x9D03FFFF  
0x1F800000  
Program Flash(2)  
Reserved  
Reserved  
0x9D000000  
0x1D040000  
0x1D03FFFF  
0x80008000  
0x80007FFF  
Program Flash(2)  
0x1D000000  
RAM(2)  
Reserved  
RAM(2)  
0x80000000  
0x00000000  
0x00008000  
0x00007FFF  
0x00000000  
Reserved  
Note 1: Memory areas are not shown to scale.  
2: The size of this memory region is programmable (see Section 3. “Memory Organization”  
(DS61115)) and can be changed by initialization code provided by end-user development  
tools (refer to the specific development tool documentation for information).  
DS61143F-page 30  
Preliminary  
© 2009 Microchip Technology Inc.  
PIC32MX3XX/4XX  
FIGURE 4-6:  
MEMORY MAP ON RESET FOR PIC32MX340F512H, PIC32MX360F512L,  
PIC32MX440F512H, PIC32MX460F512L DEVICES  
(1)  
Virtual  
Physical  
Memory Map  
Memory Map  
0xFFFFFFFF  
0xBFC03000  
0xBFC02FFF  
0xFFFFFFFF  
Reserved  
Device  
Configuration  
Registers  
0xBFC02FF0  
0xBFC02FEF  
Boot Flash  
Reserved  
SFRs  
0xBFC00000  
0xBF900000  
0xBF8FFFFF  
Reserved  
0xBF800000  
Reserved  
Program Flash(2)  
Reserved  
RAM(2)  
0xBD080000  
0xBD07FFFF  
0xBD000000  
0xA0008000  
0xA0007FFF  
0xA0000000  
0x1FC03000  
0x1FC02FFF  
Device  
Configuration  
Registers  
Reserved  
0x9FC02FF0  
0x9FC02FFF  
Device  
Configuration  
Registers  
0x1FC02FF0  
0x1FC02FEF  
0x9FC02FEF  
0x9FC02FEF  
Boot Flash  
Reserved  
SFRs  
0x1FC00000  
Boot Flash  
Reserved  
0x9FC00000  
0x1F900000  
0x1F8FFFFF  
0x9D080000  
0x9D07FFFF  
0x1F800000  
Program Flash(2)  
Reserved  
Reserved  
0x9D000000  
0x1D080000  
0x1D07FFFF  
0x80008000  
0x80007FFF  
Program Flash(2)  
0x1D000000  
RAM(2)  
Reserved  
RAM(2)  
0x80000000  
0x00000000  
0x00008000  
0x00007FFF  
0x00000000  
Reserved  
Note 1: Memory areas are not shown to scale.  
2: The size of this memory region is programmable (see Section 3. “Memory Organization”  
(DS61115)) and can be changed by initialization code provided by end-user development  
tools (refer to the specific development tool documentation for information).  
© 2009 Microchip Technology Inc.  
Preliminary  
DS61143F-page 31  
PIC32MX3XX/4XX  
4.1.1  
PERIPHERAL REGISTERS  
LOCATIONS  
Table 4-1 through Table 4-25 contain the peripheral  
address maps for the PIC32MX3XX/4XX device. Pe-  
ripherals located on the PB Bus are mapped to 512  
byte boundaries. Peripherals on the FPB Bus are  
mapped to 4 Kbyte boundaries.  
DS61143F-page 32  
Preliminary  
© 2009 Microchip Technology Inc.  
TABLE 4-1:  
BUS MATRIX REGISTERS MAP  
SFR  
Virtual  
Addr  
SFR  
Name  
Bits  
31/15  
Bits  
30/14  
Bits  
29/13  
Bits  
28/12  
Bits  
27/11  
Bits  
26/10  
Bits  
25/9  
Bits  
24/8  
Bits  
23/7  
Bits  
22/6  
Bits  
21/5  
Bits  
20/4  
Bits  
19/3  
Bits  
18/2  
Bits  
17/1  
Bits  
16/0  
BMX  
CHEDMA  
BMX  
ERRIXI  
BMX  
BMX  
BMX  
ERRDS  
BMX  
ERRIS  
31:16  
15:0  
—
—
—
—
—
—
—
—
—
—
ERRICD ERRDMA  
BF88_2000 BMXCON(1)  
BMX  
WSDRM  
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
BMXARB<2:0>  
—
31:16  
15:0  
—
—
—
—
—
—
—
—
—
—
—
—
BMX  
BF88_2010  
DKPBA(1)  
BMXDKPBA<15:0>  
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
BMX  
31:16  
BF88_2020  
DUDBA(1) 15:0  
BMXDUDBA<15:0>  
31:16  
15:0  
—
—
BMX  
BF88_2030  
DUPBA(1)  
BMXDUPBA<15:0>  
31:16  
15:0  
BF88_2040 BMXDRMSZ  
BMXDRMSZ<31:0>  
31:16  
15:0  
—
—
—
—
—
—
—
—
—
—
—
—
BMXPUPBA<19:16>  
BMX  
BF88_2050  
PUPBA(1)  
BMXPUPBA<15:0>  
31:16  
15:0  
BF88_2060 BMXPFMSZ  
BMXPFMSZ<31:0>  
31:16  
15:0  
BMX  
BF88_2070  
BMXBOOTSZ<31:0>  
BOOTSZ  
Legend:  
Note 1:  
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.  
This register has corresponding CLR, SET, and INV Registers at its virtual address, plus an offset of 0x4, 0x8, and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more information.  
(1)  
TABLE 4-2:  
INTERRUPT REGISTERS MAP  
SFR  
Virtual  
Addr  
SFR  
Name  
Bits  
31/15  
Bits  
30/14  
Bits  
29/13  
Bits  
28/12  
Bits  
27/11  
Bits  
26/10  
Bits  
25/9  
Bits  
24/8  
Bits  
23/7  
Bits  
22/6  
Bits  
21/5  
Bits  
20/4  
Bits  
19/3  
Bits  
18/2  
Bits  
17/1  
Bits  
16/0  
31:16  
15:0  
—
—
—
—
—
FRZ  
—
—
—
—
—
—
MVEC  
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
INT4EP  
—
—
INT3EP  
—
—
INT2EP  
—
—
INT1EP  
—
SS0  
INT0EP  
—
BF88_1000 INTCON  
BF88_1010 INTSTAT  
TRC<2:0>  
—
31:16  
15:0  
—
—
RIPL<2:0>  
VEC<5:0>  
31:16  
15:0  
BF88_1020  
BF88_1030  
BF88_1040  
IPTMR  
IFS0  
IPTMR<31:0>  
SPI1RXIF SPI1TXIF SPI1EIF  
31:16 I2C1MIF  
I2C1SIF  
OC3IF  
—
I2C1BIF  
IC3IF  
U1TXIF  
T3IF  
U1RXIF  
INT2IF  
—
U1EIF  
OC2IF  
—
OC5IF  
OC1IF  
—
IC5IF  
IC1IF  
—
T5IF  
T1IF  
—
INT4IF  
INT0IF  
OC4IF  
CS1IF  
IC4IF  
T4IF  
CTIF  
15:0  
INT3IF  
—
IC2IF  
T2IF  
INT1IF  
CS0IF  
31:16  
—
—
USBIF(4)  
FCEIF  
—
DMA3IF(2) DMA2IF(2) DMA1IF(2) DMA0IF(2)  
IFS1  
(3)  
(3)  
15:0 RTCCIF  
FSCMIF  
I2C2MIF  
I2C2SIF  
I2C2BIF  
U2TXIF  
U2RXIF  
U2EIF SPI2RXIF SPI2TXIF SPI2EIF(3) CMP2IF  
CMP1IF PMPIF AD1IF CNIF  
Legend:  
Note 1:  
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.  
All registers in this table have corresponding CLR, SET, and INV Registers at their virtual addresses, plus offsets of 0x4, 0x8, and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more  
information.  
2:  
3:  
4:  
These bits are not present on PIC32MX320FXXXX/420FXXXX devices.  
These bits are not present on PIC32MX420FXXXX/440FXXXX devices.  
These bits are not present on PIC32MX320FXXXX/340FXXXX/360FXXXX devices.  
(1)  
TABLE 4-2:  
INTERRUPT REGISTERS MAP (CONTINUED)  
SFR  
Virtual  
Addr  
SFR  
Bits  
31/15  
Bits  
30/14  
Bits  
29/13  
Bits  
28/12  
Bits  
27/11  
Bits  
26/10  
Bits  
25/9  
Bits  
24/8  
Bits  
23/7  
Bits  
22/6  
Bits  
21/5  
Bits  
20/4  
Bits  
19/3  
Bits  
18/2  
Bits  
17/1  
Bits  
16/0  
Name  
IEC0  
IEC1  
IPC0  
IPC1  
IPC2  
IPC3  
IPC4  
IPC5  
IPC6  
IPC7  
IPC8  
IPC9  
IPC11  
31:16 I2C1MIE  
I2C1SIE  
OC3IE  
—
I2C1BIE  
IC3IE  
—
U1TXIE  
T3IE  
U1RXIE  
INT2IE  
U1EIE  
OC2IE  
—
SPI1RXIE SPI1TXIE SPI1EIE  
OC5IE  
OC1IE  
—
IC5IE  
IC1IE  
—
T5IE  
T1IE  
—
INT4IE  
INT0IE  
OC4IE  
CS1IE  
IC4IE  
T4IE  
CTIE  
BF88_1060  
BF88_1070  
BF88_1090  
BF88_10A0  
BF88_10B0  
BF88_10C0  
BF88_10D0  
BF88_10E0  
BF88_10F0  
BF88_1100  
BF88_1110  
BF88_1120  
BF88_1140  
15:0  
INT3IE  
—
IC2IE  
USBIE  
U2RXIE  
T2IE  
INT1IE  
—
CS0IE  
31:16  
—
—
FCEIE  
DMA3IE(2) DMA2IE(2) DMA1IE(2) DMA0IE(2)  
(3)  
(3)  
15:0 RTCCIE  
FSCMIE  
—
I2C2MIE  
—
I2C2SIE  
I2C2BIE  
U2TXIE  
U2EIE SPI2RXIE SPI2TXIE SPI2EIE(3) CMP2IE  
CMP1IE  
CS1IP<2:0>  
CTIP<2:0>  
OC1IP<2:0>  
T1IP<2:0>  
PMPIE  
AD1IE  
CNIE  
31:16  
15:0  
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
INT0IP<2:0>  
CS0IP<2:0>  
INT1IP<2:0>  
IC1IP<2:0>  
INT2IP<2:0>  
IC2IP<2:0>  
INT3IP<2:0>  
IC3IP<2:0>  
INT4IP<2:0>  
IC4IP<2:0>  
SPI1IP<2:0>  
IC5IP<2:0>  
AD1IP<2:0>  
I2C1IP<2:0>  
SPI2IP<2:0>(3)  
CMP1IP<2:0>  
RTCCIP<2:0>  
I2C2IP<2:0>  
DMA3IP<2:0>(2)  
DMA1IP<2:0>(2)  
—
INT0IS<1:0>  
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
CS1IS<1:0>  
—
—
CS0IS<1:0>  
INT1IS<1:0>  
IC1IS<1:0>  
CTIS<1:0>  
OC1IS<1:0>  
T1IS<1:0>  
31:16  
15:0  
—
—
—
—
31:16  
15:0  
—
—
INT2IS<1:0>  
IC2IS<1:0>  
OC2IP<2:0>  
T2IP<2:0>  
OC2IS<1:0>  
T2IS<1:0>  
—
—
31:16  
15:0  
—
—
INT3IS<1:0>  
IC3IS<1:0>  
OC3IP<2:0>  
T3IP<2:0>  
OC3IS<1:0>  
T3IS<1:0>  
—
—
31:16  
15:0  
—
—
INT4IS<1:0>  
IC4IS<1:0>  
OC4IP<2:0>  
T4IP<2:0>  
OC4IS<1:0>  
T4IS<1:0>  
—
—
31:16  
15:0  
—
—
SPI1IS<1:0>  
IC5IS<1:0>  
OC5IP<2:0>  
T5IP<2:0>  
OC5IS<1:0>  
T5IS<1:0>  
—
—
31:16  
15:0  
—
—
AD1IS<1:0>  
I2C1IS<1:0>  
SPI2IS<1:0>(3)  
CMP1IS<1:0>  
RTCCIS<1:0>  
I2C2IS<1:0>  
DMA3IS<1:0>(2)  
DMA1IS<1:0>(2)  
CNIP<2:0>  
U1IP<2:0>  
CMP2IP<2:0>  
PMPIP<2:0>  
FSCMIP<2:0>  
U2IP<2:0>  
DMA2IP<2:0>(2)  
DMA0IP<2:0>(2)  
—
CNIS<1:0>  
—
—
U1IS<1:0>  
31:16  
15:0  
—
—
CMP2IS<1:0>  
PMPIS<1:0>  
FSCMIS<1:0>  
U2IS<1:0>  
DMA2IS<1:0>(2)  
DMA0IS<1:0>(2)  
—
—
31:16  
15:0  
—
—
—
—
31:16  
15:0  
—
—
—
—
31:16  
15:0  
—
—
—
—
—
—
—
—
—
—
—
—
USBIP<2:0>(4)  
USBIS<1:0>(4)  
FCEIP<2:0>  
FCEIS<1:0>  
Legend:  
Note 1:  
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.  
All registers in this table have corresponding CLR, SET, and INV Registers at their virtual addresses, plus offsets of 0x4, 0x8, and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more  
information.  
2:  
3:  
4:  
These bits are not present on PIC32MX320FXXXX/420FXXXX devices.  
These bits are not present on PIC32MX420FXXXX/440FXXXX devices.  
These bits are not present on PIC32MX320FXXXX/340FXXXX/360FXXXX devices.  
(1)  
TABLE 4-3:  
TIMER1-5 REGISTERS MAP  
SFR  
SFR  
Bits  
Bits  
Bits  
Bits  
Bits  
Bits  
Bits  
25/9  
Bits  
24/8  
Bits  
23/7  
Bits  
22/6  
Bits  
21/5  
Bits  
20/4  
Bits  
19/3  
Bits  
18/2  
Bits  
17/1  
Bits  
16/0  
Virtual  
Addr  
Name  
T1CON  
TMR1  
PR1  
31/15  
30/14  
29/13  
28/12  
27/11  
26/10  
31:16  
15:0  
—
ON  
—
—
FRZ  
—
—
SIDL  
—
—
TWDIS  
—
—
TWIP  
—
—
—
—
—
—
—
—
—
—
—
TGATE  
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
TSYNC  
—
—
TCS  
—
—
—
—
BF80_0600  
BF80_0610  
BF80_0620  
BF80_0800  
BF80_0810  
BF80_0820  
TCKPS<1:0>  
31:16  
15:0  
—
TMR1<15:0>  
31:16  
15:0  
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
PR1<15:0>  
31:16  
15:0  
—
ON  
—
—
FRZ  
—
—
SIDL  
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
TGATE  
—
—
TCKPS<2:0>  
—
—
T32  
—
—
—
—
—
TCS  
—
—
—
—
T2CON  
TMR2  
PR2  
31:16  
15:0  
TMR2<15:0>  
31:16  
15:0  
—
—
—
—
—
—
—
—
—
—
—
—
—
—
PR2<15:0>  
31:16  
15:0  
—
ON  
—
—
FRZ  
—
—
SIDL  
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
TGATE  
—
—
TCKPS<2:0>  
—
—
—
—
—
—
—
—
TCS  
—
—
—
—
BF80_0A00 T3CON  
31:16  
15:0  
BF80_0A10  
BF80_0A20  
TMR3  
PR3  
TMR3<15:0>  
31:16  
15:0  
—
—
—
—
—
—
—
—
—
—
—
—
—
—
PR3<15:0>  
31:16  
15:0  
—
ON  
—
—
FRZ  
—
—
SIDL  
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
TGATE  
—
—
TCKPS<2:0>  
—
—
T32  
—
—
—
—
—
TCS  
—
—
—
—
BF80_0C00 T4CON  
31:16  
15:0  
BF80_0C10  
BF80_0C20  
TMR4  
PR4  
TMR4<15:0>  
31:16  
15:0  
—
—
—
—
—
—
—
—
—
—
—
—
—
—
PR4<15:0>  
31:16  
15:0  
—
ON  
—
—
FRZ  
—
—
SIDL  
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
TGATE  
—
—
TCKPS<2:0>  
—
—
—
—
—
—
—
—
TCS  
—
—
—
—
BF80_0E00 T5CON  
31:16  
15:0  
BF80_0E10  
BF80_0E20  
TMR5  
PR5  
TMR5<15:0>  
31:16  
15:0  
—
—
—
—
—
—
—
—
—
—
—
—
—
—
PR5<15:0>  
Legend:  
Note 1:  
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.  
All registers in this table have corresponding CLR, SET, and INV Registers at their virtual addresses, plus offsets of 0x4, 0x8, and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more infor-  
mation.  
TABLE 4-4:  
INPUT CAPTURE1-5 REGISTERS MAP  
SFR  
Virtual  
Addr  
SFR  
Name  
Bits  
31/15  
Bits  
30/14  
Bits  
29/13  
Bits  
28/12  
Bits  
27/11  
Bits  
26/10  
Bits  
25/9  
Bits  
24/8  
Bits  
23/7  
Bits  
22/6  
Bits  
21/5  
Bits  
20/4  
Bits  
19/3  
Bits  
18/2  
Bits  
17/1  
Bits  
16/0  
31:16  
15:0  
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
BF80_2000 IC1CON(1)  
BF80_2010 IC1BUF  
BF80_2200 IC2CON(1)  
BF80_2210 IC2BUF  
BF80_2400 IC3CON(1)  
BF80_2410 IC3BUF  
BF80_2600 IC4CON(1)  
BF80_2610 IC4BUF  
BF80_2800 IC5CON(1)  
BF80_2810 IC5BUF  
ON  
FRZ  
SIDL  
ICFEDGE  
ICC32  
ICTMR  
ICI<1:0>  
ICOV  
ICBNE  
ICM<2:0>  
31:16  
15:0  
IC1BUF<31:0>  
31:16  
15:0  
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
ON  
FRZ  
SIDL  
ICFEDGE  
ICC32  
ICTMR  
ICI<1:0>  
ICOV  
ICBNE  
ICM<2:0>  
31:16  
15:0  
IC2BUF<31:0>  
31:16  
15:0  
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
ON  
FRZ  
SIDL  
ICFEDGE  
ICC32  
ICTMR  
ICI<1:0>  
ICI<1:0>  
ICI<1:0>  
ICOV  
ICBNE  
ICM<2:0>  
31:16  
15:0  
IC3BUF<31:0>  
31:16  
15:0  
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
ON  
FRZ  
SIDL  
ICFEDGE  
ICC32  
ICTMR  
ICOV  
ICBNE  
ICM<2:0>  
31:16  
15:0  
IC4BUF<31:0>  
31:16  
15:0  
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
ON  
FRZ  
SIDL  
ICFEDGE  
ICC32  
ICTMR  
ICOV  
ICBNE  
ICM<2:0>  
31:16  
15:0  
IC5BUF<31:0>  
Legend:  
Note 1:  
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.  
This register has corresponding CLR, SET, and INV Registers at its virtual address, plus an offset of 0x4, 0x8, and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more information.  
(1)  
TABLE 4-5:  
OUTPUT COMPARE 1-5 REGISTERS MAP  
SFR  
Virtual  
Addr  
SFR  
Name  
Bits  
31/15  
Bits  
30/14  
Bits  
29/13  
Bits  
28/12  
Bits  
27/11  
Bits  
26/10  
Bits  
25/9  
Bits  
24/8  
Bits  
23/7  
Bits  
22/6  
Bits  
21/5  
Bits  
20/4  
Bits  
19/3  
Bits  
18/2  
Bits  
17/1  
Bits  
16/0  
31:16  
15:0  
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
BF80_3000 OC1CON  
ON  
FRZ  
SIDL  
OC32  
OCFLT  
OCTSEL  
OCM<2:0>  
31:16  
15:0  
BF80_3010  
OC1R  
OC1R<31:0>  
31:16  
15:0  
BF80_3020 OC1RS  
BF80_3200 OC2CON  
OC1RS<31:0>  
31:16  
15:0  
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
ON  
FRZ  
SIDL  
OC32  
OCFLT  
OCTSEL  
OCM<2:0>  
31:16  
15:0  
BF80_3210  
OC2R  
OC2R<31:0>  
Legend:  
Note 1:  
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.  
All registers in this table have corresponding CLR, SET, and INV Registers at their virtual addresses, plus offsets of 0x4, 0x8, and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more infor-  
mation.  
(1)  
TABLE 4-5:  
OUTPUT COMPARE 1-5 REGISTERS MAP (CONTINUED)  
SFR  
Virtual  
Addr  
SFR  
Name  
Bits  
31/15  
Bits  
30/14  
Bits  
29/13  
Bits  
28/12  
Bits  
27/11  
Bits  
26/10  
Bits  
25/9  
Bits  
24/8  
Bits  
23/7  
Bits  
22/6  
Bits  
21/5  
Bits  
20/4  
Bits  
19/3  
Bits  
18/2  
Bits  
17/1  
Bits  
16/0  
31:16  
15:0  
BF80_3220 OC2RS  
BF80_3400 OC3CON  
OC2RS<31:0>  
31:16  
15:0  
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
ON  
FRZ  
SIDL  
OC32  
OCFLT  
OCTSEL  
OCM<2:0>  
31:16  
15:0  
BF80_3410  
OC3R  
OC3R<31:0>  
31:16  
15:0  
BF80_3420 OC3RS  
BF80_3600 OC4CON  
OC3RS<31:0>  
31:16  
15:0  
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
ON  
FRZ  
SIDL  
OC32  
OCFLT  
OCTSEL  
OCM<2:0>  
31:16  
15:0  
BF80_3610  
OC4R  
OC4R<31:0>  
31:16  
15:0  
BF80_3620 OC4RS  
BF80_3800 OC5CON  
OC4RS<31:0>  
31:16  
15:0  
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
ON  
FRZ  
SIDL  
OC32  
OCFLT  
OCTSEL  
OCM<2:0>  
31:16  
15:0  
BF80_3810  
OC5R  
OC5R<31:0>  
31:16  
15:0  
BF80_3820 OC5RS  
OC5RS<31:0>  
Legend:  
Note 1:  
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.  
All registers in this table have corresponding CLR, SET, and INV Registers at their virtual addresses, plus offsets of 0x4, 0x8, and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more infor-  
mation.  
(1)  
TABLE 4-6:  
I2C1-2 REGISTERS MAP  
SFR  
Virtual  
Addr  
SFR  
Name  
Bits  
31/15  
Bits  
30/14  
Bits  
29/13  
Bits  
28/12  
Bits  
27/11  
Bits  
26/10  
Bits  
25/9  
Bits  
24/8  
Bits  
23/7  
Bits  
22/6  
Bits  
21/5  
Bits  
20/4  
Bits  
19/3  
Bits  
18/2  
Bits  
17/1  
Bits  
16/0  
31:16  
15:0  
—
ON  
—
—
FRZ  
—
—
SIDL  
—
—
SCLREL  
—
—
STRICT  
—
—
A10M  
—
—
DISSLW  
—
—
SMEN  
—
—
GCEN  
—
—
STREN  
—
—
ACKDT  
—
—
ACKEN  
—
—
RCEN  
—
—
PEN  
—
—
RSEN  
—
—
SEN  
—
BF80_5000 I2C1CON  
BF80_5010 I2C1STAT  
BF80_5020 I2C1ADD  
BF80_5030 I2C1MSK  
31:16  
15:0 ACKSTAT TRSTAT  
—
—
—
BCL  
—
GCSTAT  
—
ADD10  
—
IWCOL  
—
I2COV  
—
D/A  
P
S
R/W  
—
RBF  
—
TBF  
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
31:16  
15:0  
—
—
—
—
ADD<9:0>  
31:16  
15:0  
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
MSK<9:0>  
31:16  
15:0  
—
—
—
—
—
—
—
BF80_5040  
I2C1BRG  
—
—
I2C1BRG<11:0>  
Legend:  
Note 1:  
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.  
All registers in this table except I2CxRCV have corresponding CLR, SET, and INV Registers at their virtual addresses, plus offsets of 0x4, 0x8, and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Regis-  
ters” for more information.  
(1)  
TABLE 4-6:  
I2C1-2 REGISTERS MAP (CONTINUED)  
SFR  
Virtual  
Addr  
SFR  
Name  
Bits  
31/15  
Bits  
30/14  
Bits  
29/13  
Bits  
28/12  
Bits  
27/11  
Bits  
26/10  
Bits  
25/9  
Bits  
24/8  
Bits  
23/7  
Bits  
22/6  
Bits  
21/5  
Bits  
20/4  
Bits  
19/3  
Bits  
18/2  
Bits  
17/1  
Bits  
16/0  
31:16  
15:0  
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
BF80_5050 I2C1TRN  
BF80_5260 I2C1RCV  
BF80_5200 I2C2CON  
BF80_5210 I2C2STAT  
BF80_5220 I2C2ADD  
BF80_5230 I2C2MSK  
—
—
I2CT1DATA<7:0>  
31:16  
15:0  
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
I2CR1DATA<7:0>  
31:16  
15:0  
—
—
—
—
—
—
—
—
—
GCEN  
—
—
STREN  
—
—
ACKDT  
—
—
ACKEN  
—
—
RCEN  
—
—
PEN  
—
—
RSEN  
—
—
SEN  
—
ON  
—
FRZ  
—
SIDL  
—
SCLREL  
—
STRICT  
—
A10M  
—
DISSLW  
—
SMEN  
—
31:16  
15:0 ACKSTAT TRSTAT  
—
—
—
BCL  
—
GCSTAT  
—
ADD10  
—
IWCOL  
—
I2COV  
—
D/A  
P
S
R/W  
—
RBF  
—
TBF  
—
31:16  
15:0  
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
ADD<9:0>  
31:16  
15:0  
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
MSK<9:0>  
31:16  
15:0  
—
—
—
—
—
—
BF80_5240  
I2C2BRG  
—
—
I2C2BRG<11:0>  
31:16  
15:0  
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
BF80_5250 I2C2TRN  
BF80_5260 I2C2RCV  
—
—
I2CT1DATA<7:0>  
31:16  
15:0  
—
—
—
—
—
—
—
I2CR1DATA<7:0>  
Legend:  
Note 1:  
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.  
All registers in this table except I2CxRCV have corresponding CLR, SET, and INV Registers at their virtual addresses, plus offsets of 0x4, 0x8, and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Regis-  
ters” for more information.  
TABLE 4-7:  
UART1-2 REGISTERS MAP  
SFR  
Virtual  
Addr  
SFR  
Name  
Bits  
31/15  
Bits  
30/14  
Bits  
29/13  
Bits  
28/12  
Bits  
27/11  
Bits  
26/10  
Bits  
25/9  
Bits  
24/8  
Bits  
23/7  
Bits  
22/6  
Bits  
21/5  
Bits  
20/4  
Bits  
19/3  
Bits  
18/2  
Bits  
17/1  
Bits  
16/0  
31:16  
15:0  
—
ON  
—
—
FRZ  
—
—
SIDL  
—
—
IREN  
—
—
—
—
—
—
—
—
—
—
—
—
—
—
BF80_6000 U1MODE(1)  
BF80_6010 U1STA(1)  
BF80_6020 U1TXREG  
BF80_6030 U1RXREG  
BF80_6040 U1BRG(1)  
BF80_6200 U2MODE(1)  
RTSMD  
UEN<1:0>  
WAKE  
LPBACK  
ABAUD  
RXINV  
BRGH  
PDSEL<1:0>  
STSEL  
31:16  
15:0  
—
—
—
UTXBF  
—
ADM_EN  
TRMT  
—
ADDR<7:0>  
UTXISEL<1:0>  
UTXINV  
—
URXEN  
—
UTXBRK  
UTXEN  
—
URXISEL<1:0>  
ADDEN  
—
RIDLE  
—
PERR  
—
FERR  
—
OERR  
—
URXDA  
—
31:16  
15:0  
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
TX8  
—
Transmit Register  
31:16  
15:0  
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
RX8  
—
Receive Register  
31:16  
15:0  
—
—
—
—
—
—
BRG<15:0>  
31:16  
15:0  
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
ON  
FRZ  
SIDL  
IREN  
RTSMD  
UEN<1:0>  
WAKE  
LPBACK  
ABAUD  
RXINV  
BRGH  
PDSEL<1:0>  
STSEL  
Legend:  
Note 1:  
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.  
This register has corresponding CLR, SET, and INV Registers at its virtual address, plus an offset of 0x4, 0x8, and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more information.  
TABLE 4-7:  
UART1-2 REGISTERS MAP (CONTINUED)  
SFR  
Virtual  
Addr  
SFR  
Name  
Bits  
31/15  
Bits  
30/14  
Bits  
29/13  
Bits  
28/12  
Bits  
27/11  
Bits  
26/10  
Bits  
25/9  
Bits  
24/8  
Bits  
23/7  
Bits  
22/6  
Bits  
21/5  
Bits  
20/4  
Bits  
19/3  
Bits  
18/2  
Bits  
17/1  
Bits  
16/0  
31:16  
15:0  
—
—
—
UTXINV  
—
—
URXEN  
—
—
—
UTXEN  
—
—
UTXBF  
—
ADM_EN  
TRMT  
—
ADDR<7:0>  
BF80_6210 U2STA(1)  
BF80_6220 U2TXREG  
BF80_6230 U2RXREG  
BF80_6240 U2BRG(1)  
UTXISEL<1:0>  
UTXBRK  
URXISEL<1:0>  
ADDEN  
—
RIDLE  
—
PERR  
—
FERR  
—
OERR  
—
URXDA  
—
31:16  
15:0  
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
TX8  
—
Transmit Register  
31:16  
15:0  
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
RX8  
—
Receive Register  
31:16  
15:0  
—
—
—
—
—
—
BRG<15:0>  
Legend:  
Note 1:  
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.  
This register has corresponding CLR, SET, and INV Registers at its virtual address, plus an offset of 0x4, 0x8, and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more information.  
(1,2)  
TABLE 4-8:  
SPI1-2 REGISTERS MAP  
SFR  
Virtual  
Addr  
SFR  
Name  
Bits  
31/15  
Bits  
30/14  
Bits  
29/13  
Bits  
28/12  
Bits  
27/11  
Bits  
26/10  
Bits  
25/9  
Bits  
24/8  
Bits  
23/7  
Bits  
22/6  
Bits  
21/5  
Bits  
20/4  
Bits  
19/3  
Bits  
18/2  
Bits  
17/1  
Bits  
16/0  
31:16 FRMEN FRMSYNC FRMPOL  
—
—
—
—
SMP  
—
—
CKE  
—
—
SSEN  
—
—
CKP  
—
MSTEN  
—
—
—
—
—
—
—
—
—
—
—
SPIFE  
—
—
—
BF80_5800 SPI1CON  
BF80_5810 SPI1STAT  
BF80_5820 SPI1BUF  
BF80_5830 SPI1BRG  
BF80_5A00 SPI2CON  
BF80_5A10 SPI2STAT  
BF80_5A20 SPI2BUF  
BF80_5A30 SPI2BRG  
15:0  
31:16  
15:0  
ON  
—
FRZ  
—
SIDL  
—
DISSDO MODE32 MODE16  
—
—
—
—
—
—
—
—
—
—
—
—
SPIBUSY  
—
—
—
SPIROV  
—
SPITBE  
—
SPIRBF  
31:16  
15:0  
DATA<31:0>  
31:16  
15:0  
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
BRG<8:0>  
31:16 FRMEN FRMSYNC FRMPOL  
—
—
CKE  
—
—
SSEN  
—
—
CKP  
—
MSTEN  
—
—
—
—
—
—
—
—
—
—
—
SPIFE  
—
—
—
15:0  
31:16  
15:0  
ON  
—
FRZ  
—
SIDL  
—
DISSDO MODE32 MODE16  
SMP  
—
—
—
—
—
—
—
—
—
—
—
—
—
SPIBUSY  
—
—
—
SPIROV  
—
SPITBE  
—
SPIRBF  
31:16  
15:0  
DATA<31:0>  
31:16  
15:0  
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
BRG<8:0>  
Legend:  
Note 1:  
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.  
All registers in this table except SPIxBUF have corresponding CLR, SET, and INV Registers at their virtual addresses, plus offsets of 0x4, 0x8, and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Regis-  
ters” for more information.  
2:  
SPI2 Module is not present on PIC32MX420FXXXX/440FXXXX devices.  
TABLE 4-9:  
ADC REGISTERS MAP  
SFR  
Virtual  
Addr  
SFR  
Name  
Bits  
31/15  
Bits  
30/14  
Bits  
29/13  
Bits  
28/12  
Bits  
27/11  
Bits  
26/10  
Bits  
25/9  
Bits  
24/8  
Bits  
23/7  
Bits  
22/6  
Bits  
21/5  
Bits  
20/4  
Bits  
19/3  
Bits  
18/2  
Bits  
17/1  
Bits  
16/0  
31:16  
15:0  
—
ON  
—
FRZ  
—
—
SIDL  
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
CLRASAM  
—
—
—
—
—
ASAM  
—
—
SAMP  
—
—
DONE  
—
BF80_9000 AD1CON1(1)  
BF80_9010 AD1CON2(1)  
BF80_9020 AD1CON3(1)  
BF80_9040 AD1CHS(1)  
BF80_9060 AD1PCFG(1)  
BF80_9050 AD1CSSL(1)  
BF80_9070 ADC1BUF0  
BF80_9080 ADC1BUF1  
BF80_9090 ADC1BUF2  
BF80_90A0 ADC1BUF3  
BF80_90B0 ADC1BUF4  
BF80_90C0 ADC1BUF5  
BF80_90D0 ADC1BUF6  
BF80_90E0 ADC1BUF7  
BF80_90F0 ADC1BUF8  
BF80_9100 ADC1BUF9  
BF80_9110 ADC1BUFA  
BF80_9120 ADC1BUFB  
FORM<2:0>  
SSRC<2:0>  
31:16  
15:0  
—
—
—
CSCNA  
—
—
—
—
—
—
—
—
BUFS  
—
—
—
—
VCFG2  
—
VCFG1  
—
VCFG0  
—
OFFCAL  
—
SMPI<3:0>  
BUFM  
—
ALTS  
—
31:16  
15:0  
—
—
—
ADRC  
—
—
SAMC<4:0>  
ADCS<7:0>  
31:16 CH0NB  
—
—
—
—
CH0SB<3:0>  
CH0NA  
—
—
—
—
—
—
—
CH0SA<3:0>  
15:0  
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
31:16  
—
—
—
—
—
—
—
15:0 PCFG15  
31:16  
PCFG14  
—
PCFG13  
—
PCFG12  
—
PCFG11  
—
PCFG10  
—
PCFG9  
—
PCFG8  
—
PCFG7  
—
PCFG6  
—
PCFG5  
—
PCFG4  
—
PCFG3  
—
PCFG2  
—
PCFG1  
—
PCFG0  
—
—
15:0 CSSL15  
31:16  
15:0  
CSSL14  
CSSL13  
CSSL12  
CSSL11  
CSSL10  
CSSL9  
CSSL8  
CSSL7  
CSSL6  
CSSL5  
CSSL4  
CSSL3  
CSSL2  
CSSL1  
CSSL0  
ADC Result Word 0 (ADC1BUF0<31:0>)  
ADC Result Word 1 (ADC1BUF1<31:0>)  
ADC Result Word 2 (ADC1BUF2<31:0>)  
ADC Result Word 3 (ADC1BUF3<31:0>)  
ADC Result Word 4 (ADC1BUF4<31:0>)  
ADC Result Word 5 (ADC1BUF5<31:0>)  
ADC Result Word 6 (ADC1BUF6<31:0>)  
ADC Result Word 7 (ADC1BUF7<31:0>)  
ADC Result Word 8 (ADC1BUF8<31:0>)  
ADC Result Word 9 (ADC1BUF9<31:0>)  
ADC Result Word A (ADC1BUFA<31:0>)  
ADC Result Word B (ADC1BUFB<31:0>)  
31:16  
15:0  
31:16  
15:0  
31:16  
15:0  
31:16  
15:0  
31:16  
15:0  
31:16  
15:0  
31:16  
15:0  
31:16  
15:0  
31:16  
15:0  
31:16  
15:0  
31:16  
15:0  
Legend:  
Note 1:  
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.  
This register has corresponding CLR, SET, and INV Registers at its virtual address, plus an offset of 0x4, 0x8, and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more information.  
TABLE 4-9:  
ADC REGISTERS MAP (CONTINUED)  
SFR  
Virtual  
Addr  
SFR  
Name  
Bits  
31/15  
Bits  
30/14  
Bits  
29/13  
Bits  
28/12  
Bits  
27/11  
Bits  
26/10  
Bits  
25/9  
Bits  
24/8  
Bits  
23/7  
Bits  
22/6  
Bits  
21/5  
Bits  
20/4  
Bits  
19/3  
Bits  
18/2  
Bits  
17/1  
Bits  
16/0  
31:16  
15:0  
BF80_9130 ADC1BUFC  
BF80_9140 ADC1BUFD  
BF80_9150 ADC1BUFE  
BF80_9160 ADC1BUFF  
ADC Result Word C (ADC1BUFC<31:0>)  
ADC Result Word D (ADC1BUFD<31:0>)  
ADC Result Word E (ADC1BUFE<31:0>)  
ADC Result Word F (ADC1BUFF<31:0>)  
31:16  
15:0  
31:16  
15:0  
31:16  
15:0  
Legend:  
Note 1:  
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.  
This register has corresponding CLR, SET, and INV Registers at its virtual address, plus an offset of 0x4, 0x8, and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more information.  
TABLE 4-10: DMA GLOBAL REGISTERS MAP FOR PIC32MX340FXXXX/360FXXXX/440FXXXX/460XXXX DEVICES ONLY  
SFR  
Virtual  
Addr  
SFR  
Name  
Bits  
31/15  
Bits  
30/14  
Bits  
29/13  
Bits  
28/12  
Bits  
27/11  
Bits  
26/10  
Bits  
25/9  
Bits  
24/8  
Bits  
23/7  
Bits  
22/6  
Bits  
21/5  
Bits  
20/4  
Bits  
19/3  
Bits  
18/2  
Bits  
17/1  
Bits  
16/0  
31:16  
15:0  
—
ON  
—
—
FRZ  
—
—
SIDL  
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
BF88_3000 DMACON(1)  
BF88_3010 DMASTAT  
BF88_3020 DMAADDR  
SUSPEND  
31:16  
15:0  
—
—
—
—
—
—
RDWR  
DMACH<1:0>  
31:16  
15:0  
DMAADDR<31:0>  
Legend:  
Note 1:  
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.  
This register has corresponding CLR, SET, and INV Registers at its virtual address, plus an offset of 0x4, 0x8, and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more information.  
(1)  
TABLE 4-11: DMA CRC REGISTERS MAP FOR PIC32MX340FXXXX/360FXXXX/440FXXXX/460XXXX DEVICES ONLY  
SFR  
Virtual  
Addr  
SFR  
Name  
Bits  
31/15  
Bits  
30/14  
Bits  
29/13  
Bits  
28/12  
Bits  
27/11  
Bits  
26/10  
Bits  
25/9  
Bits  
24/8  
Bits  
23/7  
Bits  
22/6  
Bits  
21/5  
Bits  
20/4  
Bits  
19/3  
Bits  
18/2  
Bits  
17/1  
Bits  
16/0  
31:16  
15:0  
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
CRCEN  
—
—
CRCAPP  
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
BF88_3030 DCRCCON  
BF88_3040 DCRCDATA  
BF88_3050 DCRCXOR  
PLEN<3:0>  
CRCCH<1:0>  
31:16  
15:0  
—
—
—
—
—
DCRCDATA<15:0>  
31:16  
15:0  
—
—
—
—
—
—
—
—
—
—
—
DCRCXOR<15:0>  
Legend:  
Note 1:  
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.  
All registers in this table have corresponding CLR, SET, and INV Registers at their virtual addresses, plus offsets of 0x4, 0x8, and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more infor-  
mation.  
(1)  
TABLE 4-12: DMA CHANNELS 0-3 REGISTERS MAP FOR PIC32MX340FXXXX/360FXXXX/440FXXXX/460XXXX DEVICES ONLY  
SFR  
Virtual  
Addr  
SFR  
Name  
Bits  
31/15  
Bits  
30/14  
Bits  
29/13  
Bits  
28/12  
Bits  
27/11  
Bits  
26/10  
Bits  
25/9  
Bits  
24/8  
Bits  
23/7  
Bits  
22/6  
Bits  
21/5  
Bits  
20/4  
Bits  
19/3  
Bits  
18/2  
Bits  
17/1  
Bits  
16/0  
31:16  
15:0  
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
CHCHNS  
—
—
—
—
—
—
—
—
—
—
BF88_3060 DCH0CON  
BF88_3070 DCH0ECON  
BF88_3080 DCH0INT  
BF88_3090 DCH0SSA  
BF88_30A0 DCH0DSA  
BF88_30B0 DCH0SSIZ  
BF88_30C0 DCH0DSIZ  
BF88_30D0 DCH0SPTR  
BF88_30E0 DCH0DPTR  
BF88_30F0 DCH0CSIZ  
BF88_3100 DCH0CPTR  
BF88_3110 DCH0DAT  
BF88_3120 DCH1CON  
BF88_3130 DCH1ECON  
BF88_3140 DCH1INT  
BF88_3150 DCH1SSA  
BF88_3160 DCH1DSA  
CHEN  
CHAED  
CHCHN  
CHAEN  
CHEDET  
CHPRI<1:0>  
31:16  
15:0  
CHAIRQ<7:0>  
CHSIRQ<7:0>  
CFORCE CABORT  
PATEN  
CHDDIE  
CHDDIF  
SIRQEN  
CHDHIE  
CHDHIF  
AIRQEN  
CHBCIE  
CHBCIF  
—
—
—
31:16  
15:0  
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
CHSDIE  
CHSDIF  
CHSHIE  
CHSHIF  
CHCCIE  
CHCCIF  
CHTAIE  
CHTAIF  
CHERIE  
CHERIF  
31:16  
15:0  
CHSSA<31:0>  
31:16  
15:0  
CHDSA<31:0>  
31:16  
15:0  
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
CHSSIZ<7:0>  
31:16  
15:0  
—
—
—
CHDSIZ<7:0>  
31:16  
15:0  
—
—
—
—
CHSTR<7:0>  
31:16  
15:0  
—
—
—
—
CHDPTR<7:0>  
31:16  
15:0  
—
—
—
—
CHCSIZ<7:0>  
31:16  
15:0  
—
—
—
—
CHCPTR<7:0>  
31:16  
15:0  
—
—
—
—
—
CHPDAT<7:0>  
31:16  
15:0  
—
—
—
—
—
—
—
CHCHNS  
—
CHEN  
CHAED  
CHCHN  
CHAEN  
CHEDET  
CHPRI<1:0>  
31:16  
15:0  
CHAIRQ<7:0>  
CHSIRQ<7:0>  
CFORCE CABORT  
PATEN  
CHDDIE  
CHDDIF  
SIRQEN  
AIRQEN  
CHBCIE  
CHBCIF  
—
—
—
31:16  
15:0  
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
CHSDIE  
CHSDIF  
CHSHIE  
CHSHIF  
CHDHIE  
CHDHIF  
CHCCIE  
CHCCIF  
CHTAIE  
CHTAIF  
CHERIE  
CHERIF  
31:16  
15:0  
CHSSA<31:0>  
31:16  
15:0  
CHDSA<31:0>  
Legend:  
Note 1:  
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.  
All registers except DCHxSPTR, DCHxDPTR, and DCHxCPTR have corresponding CLR, SET, and INV Registers at their virtual addresses, plus offsets of 0x4, 0x8, and 0xC, respectively. See Section 12.1.1 “CLR,  
SET and INV Registers” for more information.  
TABLE 4-12: DMA CHANNELS 0-3 REGISTERS MAP (CONTINUED)FOR PIC32MX340FXXXX/360FXXXX/440FXXXX/460XXXX DEVICES  
(1)  
ONLY (CONTINUED)  
SFR  
Virtual  
Addr  
SFR  
Name  
Bits  
31/15  
Bits  
30/14  
Bits  
29/13  
Bits  
28/12  
Bits  
27/11  
Bits  
26/10  
Bits  
25/9  
Bits  
24/8  
Bits  
23/7  
Bits  
22/6  
Bits  
21/5  
Bits  
20/4  
Bits  
19/3  
Bits  
18/2  
Bits  
17/1  
Bits  
16/0  
31:16  
15:0  
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
BF88_3170 DCH1SSIZ  
BF88_3180 DCH1DSIZ  
BF88_3190 DCH1SPTR  
BF88_31A0 DCH1DPTR  
BF88_31B0 DCH1CSIZ  
BF88_31C0 DCH1CPTR  
BF88_31D0 DCH1DAT  
BF88_31E0 DCH2CON  
BF88_31F0 DCH2ECON  
BF88_3200 DCH2INT  
BF88_3210 DCH2SSA  
BF88_3220 DCH2DSA  
BF88_3230 DCH2SSIZ  
BF88_3240 DCH2DSIZ  
BF88_3250 DCH2SPTR  
BF88_3260 DCH2DPTR  
BF88_3270 DCH2CSIZ  
—
CHSSIZ<7:0>  
31:16  
15:0  
—
—
—
CHDSIZ<7:0>  
31:16  
15:0  
—
—
—
—
CHSPTR<7:0>  
31:16  
15:0  
—
—
—
—
CHDPTR<7:0>  
31:16  
15:0  
—
—
—
—
CHCSIZ<7:0>  
31:16  
15:0  
—
—
—
—
CHCPTR<7:0>  
31:16  
15:0  
—
—
—
—
—
CHPDAT<7:0>  
31:16  
15:0  
—
—
—
—
—
—
—
CHCHNS  
—
CHEN  
CHAED  
CHCHN  
CHAEN  
CHEDET  
CHPRI<1:0>  
31:16  
15:0  
CHAIRQ<7:0>  
CHSIRQ<7:0>  
CFORCE CABORT  
PATEN  
CHDDIE  
CHDDIF  
SIRQEN  
AIRQEN  
CHBCIE  
CHBCIF  
—
—
—
31:16  
15:0  
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
CHSDIE  
CHSDIF  
CHSHIE  
CHSHIF  
CHDHIE  
CHDHIF  
CHCCIE  
CHCCIF  
CHTAIE  
CHTAIF  
CHERIE  
CHERIF  
31:16  
15:0  
CHSSA<31:0>  
31:16  
15:0  
CHDSA<31:0>  
31:16  
15:0  
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
CHSSIZ<7:0>  
31:16  
15:0  
—
CHDSIZ<7:0>  
31:16  
15:0  
—
—
CHSPTR<7:0>  
31:16  
15:0  
—
—
CHDPTR<7:0>  
31:16  
15:0  
—
—
CHCSIZ<7:0>  
Legend:  
Note 1:  
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.  
All registers except DCHxSPTR, DCHxDPTR, and DCHxCPTR have corresponding CLR, SET, and INV Registers at their virtual addresses, plus offsets of 0x4, 0x8, and 0xC, respectively. See Section 12.1.1 “CLR,  
SET and INV Registers” for more information.  
TABLE 4-12: DMA CHANNELS 0-3 REGISTERS MAP (CONTINUED)FOR PIC32MX340FXXXX/360FXXXX/440FXXXX/460XXXX DEVICES  
(1)  
ONLY (CONTINUED)  
SFR  
Virtual  
Addr  
SFR  
Name  
Bits  
31/15  
Bits  
30/14  
Bits  
29/13  
Bits  
28/12  
Bits  
27/11  
Bits  
26/10  
Bits  
25/9  
Bits  
24/8  
Bits  
23/7  
Bits  
22/6  
Bits  
21/5  
Bits  
20/4  
Bits  
19/3  
Bits  
18/2  
Bits  
17/1  
Bits  
16/0  
31:16  
15:0  
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
BF88_3280 DCH2CPTR  
BF88_3290 DCH2DAT  
BF88_32A0 DCH3CON  
BF88_32B0 DCH3ECON  
BF88_32C0 DCH3INT  
BF88_32D0 DCH3SSA  
BF88_32E0 DCH3DSA  
BF88_32F0 DCH3SSIZ  
BF88_3300 DCH3DSIZ  
BF88_3310 DCH3SPTR  
BF88_3320 DCH3DPTR  
BF88_3330 DCH3CSIZ  
BF88_3340 DCH3CPTR  
BF88_3350 DCH3DAT  
—
CHCPTR<7:0>  
31:16  
15:0  
—
—
—
—
—
CHPDAT<7:0>  
31:16  
15:0  
—
—
—
—
—
—
—
CHCHNS  
—
CHEN  
CHAED  
CHCHN  
CHAEN  
CHEDET  
CHPRI<1:0>  
31:16  
15:0  
CHAIRQ<7:0>  
CHSIRQ<7:0>  
CFORCE CABORT  
PATEN  
CHDDIE  
CHDDIF  
SIRQEN  
AIRQEN  
CHBCIE  
CHBCIF  
—
—
—
31:16  
15:0  
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
CHSDIE  
CHSDIF  
CHSHIE  
CHSHIF  
CHDHIE  
CHDHIF  
CHCCIE  
CHCCIF  
CHTAIE  
CHTAIF  
CHERIE  
CHERIF  
31:16  
15:0  
CHSSA<31:0>  
31:16  
15:0  
CHDSA<31:0>  
31:16  
15:0  
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
CHSSIZ<7:0>  
31:16  
15:0  
—
CHDSIZ<7:0>  
31:16  
15:0  
—
—
CHSTR<7:0>  
31:16  
15:0  
—
—
CHDPTR<7:0>  
31:16  
15:0  
—
—
CHCSIZ<7:0>  
31:16  
15:0  
—
—
CHCPTR<7:0>  
31:16  
15:0  
—
—
CHPDAT<7:0>  
Legend:  
Note 1:  
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.  
All registers except DCHxSPTR, DCHxDPTR, and DCHxCPTR have corresponding CLR, SET, and INV Registers at their virtual addresses, plus offsets of 0x4, 0x8, and 0xC, respectively. See Section 12.1.1 “CLR,  
SET and INV Registers” for more information.  
(1)  
TABLE 4-13: COMPARATOR REGISTERS MAP  
SFR  
Virtual  
Addr  
SFR  
Name  
Bits  
31/15  
Bits  
30/14  
Bits  
29/13  
Bits  
28/12  
Bits  
27/11  
Bits  
26/10  
Bits  
25/9  
Bits  
24/8  
Bits  
23/7  
Bits  
22/6  
Bits  
21/5  
Bits  
20/4  
Bits  
19/3  
Bits  
18/2  
Bits  
17/1  
Bits  
16/0  
31:16  
15:0  
—
ON  
—
—
COE  
—
—
CPOL  
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
COUT  
—
—
—
—
—
—
—
—
—
—
—
CREF  
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
BF80_A000 CM1CON  
BF80_A010 CM2CON  
BF80_A060 CMSTAT  
EVPOL<1:0>  
CCH<1:0>  
31:16  
15:0  
—
—
ON  
—
COE  
—
CPOL  
—
COUT  
—
EVPOL<1:0>  
CREF  
—
CCH<1:0>  
31:16  
15:0  
—
—
—
—
—
—
—
FRZ  
SIDL  
—
—
C2OUT  
C1OUT  
Legend:  
Note 1:  
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.  
All registers in this table have corresponding CLR, SET, and INV Registers at their virtual addresses, plus offsets of 0x4, 0x8, and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more infor-  
mation.  
(1)  
TABLE 4-14: COMPARATOR VOLTAGE REFERENCE REGISTERS MAP  
SFR  
Virtual  
Addr  
SFR  
Name  
Bits  
31/15  
Bits  
30/14  
Bits  
29/13  
Bits  
28/12  
Bits  
27/11  
Bits  
26/10  
Bits  
25/9  
Bits  
24/8  
Bits  
23/7  
Bits  
22/6  
Bits  
21/5  
Bits  
20/4  
Bits  
19/3  
Bits  
18/2  
Bits  
17/1  
Bits  
16/0  
31:16  
15:0  
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
BF80_9800 CVRCON  
ON  
CVROE  
CVRR  
CVRSS  
CVR<3:0>  
Legend:  
Note 1:  
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.  
All registers in this table have corresponding CLR, SET, and INV Registers at their virtual addresses, plus offsets of 0x4, 0x8, and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more infor-  
mation.  
TABLE 4-15: FLASH CONTROLLER REGISTERS MAP  
SFR  
Virtual  
Addr  
SFR  
Name  
Bits  
31/15  
Bits  
30/14  
Bits  
29/13  
Bits  
28/12  
Bits  
27/11  
Bits  
26/10  
Bits  
25/9  
Bits  
24/8  
Bits  
23/7  
Bits  
22/6  
Bits  
21/5  
Bits  
20/4  
Bits  
19/3  
Bits  
18/2  
Bits  
17/1  
Bits  
16/0  
31:16  
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
BF80_F400 NVMCON(1)  
BF80_F410 NVMKEY  
NVM  
WREN  
15:0 NVMWR  
NVMERR LVDERR LVDSTAT  
NVMOP<3:0>  
31:16  
15:0  
NVMKEY<31:0>  
NVMADDR<31:0>  
NVMDATA<31:0>  
31:16  
15:0  
(1)  
BF80_F420 NVMADDR  
31:16  
15:0  
BF80_F430 NVMDATA  
31:16  
15:0  
NVMSRC  
BF80_F440  
NVMSRCADDR<31:0>  
ADDR  
Legend:  
Note 1:  
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.  
This register has corresponding CLR, SET, and INV Registers at its virtual address, plus an offset of 0x4, 0x8, and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more information.  
(1)  
TABLE 4-16: SYSTEM CONTROL REGISTERS MAP  
SFR  
Virtual  
Addr  
SFR  
Name  
Bits  
31/15  
Bits  
30/14  
Bits  
29/13  
Bits  
28/12  
Bits  
27/11  
Bits  
26/10  
Bits  
25/9  
Bits  
24/8  
Bits  
23/7  
Bits  
22/6  
Bits  
21/5  
Bits  
20/4  
Bits  
19/3  
Bits  
18/2  
Bits  
17/1  
Bits  
16/0  
31:16  
15:0  
—
—
—
—
—
ON  
—
—
—
—
—
PLLODIV<2:0>  
RCDIV<2:0>  
—
SOSCRDY  
—
LOCK  
—
PBDIV<1:0>  
PLLMULT<2:0>  
BF80_F000 OSCCON  
BF80_F010 OSCTUN  
BF80_0000 WDTCON  
COSC<2:0>  
—
—
—
—
—
—
—
—
—
NOSC<2:0>  
CLKLOCK ULOCK  
SLPEN  
—
CF  
—
UFRCEN SOSCEN OSWEN  
31:16  
15:0  
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
TUN<5:0>  
31:16  
15:0  
—
—
—
—
—
—
—
—
—
—
WDTCLR  
—
—
—
—
SWDTPS<4:0>  
31:16  
15:0  
—
—
—
—
SWR  
—
—
—
—
—
—
WDTO  
—
—
SLEEP  
—
—
IDLE  
—
—
BF80_F600  
RCON  
CM  
—
VREGS  
—
EXTR  
—
BOR  
—
POR  
31:16  
15:0  
—
BF80_F610 RSWRST  
—
—
—
—
—
—
—
—
SWRST  
Legend:  
Note 1:  
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.  
All registers in this table have corresponding CLR, SET, and INV Registers at their virtual addresses, plus offsets of 0x4, 0x8, and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more infor-  
mation.  
(11)  
TABLE 4-17: PORT A-G REGISTERS MAP  
SFR  
Virtual  
Addr  
SFR  
Name  
Bits  
31/15  
Bits  
30/14  
Bits  
29/13  
Bits  
28/12  
Bits  
27/11  
Bits  
26/10  
Bits  
25/9  
Bits  
24/8  
Bits  
23/7  
Bits  
22/6  
Bits  
21/5  
Bits  
20/4  
Bits  
19/3  
Bits  
18/2  
Bits  
17/1  
Bits  
16/0  
31:16  
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
TRISA10  
—
—
TRISA9  
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
BF88_6000 TRISA(1,2,3)  
BF88_6010 PORTA(1,2,3)  
BF88_6020 LATA(1,2,3)  
BF88_6030 ODCA(1,2,3)  
BF88_6040 TRISB(4,5)  
BF88_6050 PORTB(4,5)  
15:0 TRISA15 TRISA14  
TRISA<7:0>  
31:16  
15:0  
—
RA15  
—
—
RA14  
—
—
RA10  
—
RA9  
—
RA<7:0>  
31:16  
15:0  
—
—
—
LATA15  
—
LATA14  
—
LATA10  
—
LATA9  
—
LATA<7:0>  
31:16  
—
—
—
15:0 ODCA15 ODCA14  
ODCA10  
—
ODCA9  
—
ODCA<7:0>  
31:16  
15:0  
—
—
—
TRISB<15:0>  
31:16  
15:0  
—
—
—
—
—
—
—
—
—
RB<15:0>  
Legend:  
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.  
TRISA, PORTA, LATA and ODCA registers are not implemented on 64-pin devices, and read as ‘0’.  
Note 1:  
2:  
JTAG program/debug port is multiplexed with port pins RA0, RA1, RA4 and RA5 on 100-pin devices. At power-on-reset, these pins are controlled by the JTAG port. To use these pins for general purpose I/O, the  
user’s application code must clear JTAGEN (DDPCON<3>) bit = 0. To use these pins for JTAG program/debug, the user’s application code must maintain JTAGEN bit = 1.  
On specific 100-pin devices, the instruction TRACE port is multiplexed with PORTA pins RA6, RA7; PORTG pins RG12, RG13 and RG14. At Power-on Reset, these pins are general purpose I/O pins. To maintain  
these pins as general purpose I/O pins, the user’s application code must maintain TROEN (DDPCON<2>) bit = 0. To use these pins as instruction TRACE pins, TROEN must be set = 1.  
JTAG program/debug port is multiplexed with port pins RB10, RB11, RB12 and RB13 on 64-pin devices. At power-on-reset, these pins are controlled by the JTAG port. To use these pins for general purpose I/O, the  
user’s application code must clear JTAGEN (DDPCON<3>) bit = 0. To use these pins for JTAG program/debug, the user’s application code must maintain JTAGEN bit = 1.  
Port Pin RB3 is not available as a general purpose I/O pin when the USB module is enabled.  
Not implemented on 64-pin devices. Read as ‘0’.  
Not implemented on 64-pin USB devices. Read as ‘0’.  
Not implemented on 100-pin USB devices. Read as ‘0’.  
Not available as a general purpose I/O pin when USB module is enabled.  
3:  
4:  
5:  
6:  
7:  
8:  
9:  
10:  
11:  
Not available as a general purpose I/O pin when USB module is enabled. Input only when the USB module is disabled.  
All registers in this table have corresponding CLR, SET, and INV Registers at their virtual addresses, plus offsets of 0x4, 0x8, and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more infor-  
mation.  
(11)  
TABLE 4-17: PORT A-G REGISTERS MAP  
(CONTINUED)  
SFR  
Virtual  
Addr  
SFR  
Name  
Bits  
31/15  
Bits  
30/14  
Bits  
29/13  
Bits  
28/12  
Bits  
27/11  
Bits  
26/10  
Bits  
25/9  
Bits  
24/8  
Bits  
23/7  
Bits  
22/6  
Bits  
21/5  
Bits  
20/4  
Bits  
19/3  
Bits  
18/2  
Bits  
17/1  
Bits  
16/0  
31:16  
15:0  
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
BF88_6060 LATB(4,5)  
BF88_6070 ODCB(4,5)  
LATB<15:0>  
31:16  
15:0  
—
—
—
—
ODCB<15:0>  
31:16  
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
BF88_6080  
TRISC  
15:0 TRISC15 TRISC14 TRISC13 TRISC12  
TRISC4(6) TRISC3(6) TRISC2(6) TRISC1(6)  
31:16  
15:0  
—
RC15  
—
—
RC14  
—
—
RC13  
—
—
RC12  
—
—
RC4(6)  
—
—
RC3(6)  
—
—
RC2(6)  
—
—
RC1(6)  
—
BF88_6090 PORTC  
31:16  
BF88_60A0  
BF88_60B0  
BF88_60C0  
LATC  
ODCC  
TRISD  
15:0 LATC15  
31:16  
LATC14  
—
LATC13  
—
LATC12  
—
LATC4(6) LATC3(6) LATC2(6) LATC1(6)  
—
—
—
—
—
15:0 ODCC15 ODCC14 ODCC13 ODCC12  
31:16  
15:0 TRISD15(6) TRISD14(6) TRISD13(6) TRISD12(6)  
ODCC4(6) ODCC3(6) ODCC2(6) ODCC1(6)  
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
TRISD<11:8>  
TRISD<7:0>  
31:16  
15:0  
—
RD15(6)  
—
—
RD14(6)  
—
—
RD13(6)  
—
—
RD12(6)  
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
BF88_60D0 PORTD  
RD<11:8>  
RD<7:0>  
31:16  
15:0 LAT15(6)  
—
—
—
BF88_60E0  
BF88_60F0  
BF88_6100  
BF88_6110  
LATD  
ODCD  
TRISE  
PORTE  
LATE  
LAT14(6)  
LAT13(6)  
LAT12(6)  
LATD<11:8>  
LATD<7:0>  
31:16  
—
—
—
—
—
—
—
—
15:0 ODCD15(6) ODCD14(6) ODCD13(6) ODCD12(6)  
ODCD<11:8>  
ODCD<7:0>  
31:16  
15:0  
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
TRISE9(6) TRISE8(6)  
TRISE<7:0>  
31:16  
15:0  
—
RE9(6)  
—
—
RE8(6)  
—
—
—
RE<7:0>  
31:16  
15:0  
—
—
BF88_6120  
LATE9(6) LATE8(6)  
LATE<7:0>  
Legend:  
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.  
Note 1:  
2:  
TRISA, PORTA, LATA and ODCA registers are not implemented on 64-pin devices, and read as ‘0’.  
JTAG program/debug port is multiplexed with port pins RA0, RA1, RA4 and RA5 on 100-pin devices. At power-on-reset, these pins are controlled by the JTAG port. To use these pins for general purpose I/O, the  
user’s application code must clear JTAGEN (DDPCON<3>) bit = 0. To use these pins for JTAG program/debug, the user’s application code must maintain JTAGEN bit = 1.  
On specific 100-pin devices, the instruction TRACE port is multiplexed with PORTA pins RA6, RA7; PORTG pins RG12, RG13 and RG14. At Power-on Reset, these pins are general purpose I/O pins. To maintain  
these pins as general purpose I/O pins, the user’s application code must maintain TROEN (DDPCON<2>) bit = 0. To use these pins as instruction TRACE pins, TROEN must be set = 1.  
JTAG program/debug port is multiplexed with port pins RB10, RB11, RB12 and RB13 on 64-pin devices. At power-on-reset, these pins are controlled by the JTAG port. To use these pins for general purpose I/O, the  
user’s application code must clear JTAGEN (DDPCON<3>) bit = 0. To use these pins for JTAG program/debug, the user’s application code must maintain JTAGEN bit = 1.  
Port Pin RB3 is not available as a general purpose I/O pin when the USB module is enabled.  
3:  
4:  
5:  
6:  
Not implemented on 64-pin devices. Read as ‘0’.  
7:  
Not implemented on 64-pin USB devices. Read as ‘0’.  
8:  
Not implemented on 100-pin USB devices. Read as ‘0’.  
9:  
Not available as a general purpose I/O pin when USB module is enabled.  
10:  
11:  
Not available as a general purpose I/O pin when USB module is enabled. Input only when the USB module is disabled.  
All registers in this table have corresponding CLR, SET, and INV Registers at their virtual addresses, plus offsets of 0x4, 0x8, and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more infor-  
mation.  
(11)  
TABLE 4-17: PORT A-G REGISTERS MAP  
(CONTINUED)  
SFR  
Virtual  
Addr  
SFR  
Name  
Bits  
31/15  
Bits  
30/14  
Bits  
29/13  
Bits  
28/12  
Bits  
27/11  
Bits  
26/10  
Bits  
25/9  
Bits  
24/8  
Bits  
23/7  
Bits  
22/6  
Bits  
21/5  
Bits  
20/4  
Bits  
19/3  
Bits  
18/2  
Bits  
17/1  
Bits  
16/0  
31:16  
15:0  
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
BF88_6130  
BF88_6140  
BF88_6150  
BF88_6160  
BF88_6170  
BF88_6180  
ODCE  
TRISF  
PORTF  
LATF  
ODCE9(6) ODCE8(6)  
ODCE<7:0>  
31:16  
15:0  
—
—
—
—
TRISF4  
—
—
TRISF0  
—
TRISF13(6) TRISF12(6)  
TRISF8(6) TRISF7(6,8) TRISF6(7,8) TRISF5  
TRISF3 TRISF2(7) TRISF1  
31:16  
15:0  
—
RF13(6)  
—
—
RF12(6)  
—
—
—
RF8(6)  
—
—
RF7(6,8)  
—
—
RF6(7,8)  
—
—
RF5  
—
—
RF3(9)  
—
—
RF2(7)  
—
—
RF1  
—
—
RF4  
—
RF0  
—
31:16  
15:0  
—
LATF13(6) LATF12(6)  
—
LATF8(6) LATF7(6,8) LATF6(7,8)  
LATF5  
—
LATF4  
—
LATF3  
—
LATF2(7)  
LATF1  
—
LATF0  
—
31:16  
15:0  
—
—
—
—
—
—
—
ODCF  
TRISG  
ODCF13(6) ODCF12(6)  
—
ODCF8(6) ODCF7(6,8) ODCF6(7,8) ODCF5  
ODCF4  
—
ODCF3  
—
ODCF2(7)  
—
TRISG2 TRISG1(6) TRISG0(6)  
ODCF1  
ODCF0  
31:16  
—
—
—
—
TRISG8  
—
—
TRISG7  
—
—
TRISG6  
—
—
—
—
—
—
—
—
—
—
—
15:0 TRISG15(6) TRISG14(6) TRISG13(6) TRISG12(6)  
TRISG9  
—
—
TRISG3  
31:16  
15:0 RG15(6)  
31:16  
15:0 LATG15(6) LATG14(6) LATG13(6) LATG12(6)  
31:16  
15:0 ODCG15(6) ODCG14(6) ODCG13(6) ODCG12(6)  
—
—
RG14(6)  
—
—
RG13(6)  
—
—
RG12(6)  
—
—
—
—
RG2(10)  
—
—
RG1(6)  
—
—
RG0(6)  
—
BF88_6190 PORTG  
RG9  
—
RG8  
—
RG7  
—
RG6  
—
—
RG3(10)  
—
—
—
BF88_61A0  
LATG  
LATG9  
—
LATG8  
—
LATG7  
—
LATG6  
—
—
LATG3  
—
LATG2  
—
LATG1(6) LATG0(6)  
—
—
—
—
—
—
—
BF88_61B0  
ODCG  
ODCG9  
ODCG8  
ODCG7  
ODCG6  
—
ODCG3  
ODCG2 ODCG1(6) ODCG0(6)  
Legend:  
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.  
TRISA, PORTA, LATA and ODCA registers are not implemented on 64-pin devices, and read as ‘0’.  
Note 1:  
2:  
JTAG program/debug port is multiplexed with port pins RA0, RA1, RA4 and RA5 on 100-pin devices. At power-on-reset, these pins are controlled by the JTAG port. To use these pins for general purpose I/O, the  
user’s application code must clear JTAGEN (DDPCON<3>) bit = 0. To use these pins for JTAG program/debug, the user’s application code must maintain JTAGEN bit = 1.  
On specific 100-pin devices, the instruction TRACE port is multiplexed with PORTA pins RA6, RA7; PORTG pins RG12, RG13 and RG14. At Power-on Reset, these pins are general purpose I/O pins. To maintain  
these pins as general purpose I/O pins, the user’s application code must maintain TROEN (DDPCON<2>) bit = 0. To use these pins as instruction TRACE pins, TROEN must be set = 1.  
JTAG program/debug port is multiplexed with port pins RB10, RB11, RB12 and RB13 on 64-pin devices. At power-on-reset, these pins are controlled by the JTAG port. To use these pins for general purpose I/O, the  
user’s application code must clear JTAGEN (DDPCON<3>) bit = 0. To use these pins for JTAG program/debug, the user’s application code must maintain JTAGEN bit = 1.  
Port Pin RB3 is not available as a general purpose I/O pin when the USB module is enabled.  
3:  
4:  
5:  
6:  
Not implemented on 64-pin devices. Read as ‘0’.  
7:  
Not implemented on 64-pin USB devices. Read as ‘0’.  
8:  
Not implemented on 100-pin USB devices. Read as ‘0’.  
9:  
Not available as a general purpose I/O pin when USB module is enabled.  
10:  
11:  
Not available as a general purpose I/O pin when USB module is enabled. Input only when the USB module is disabled.  
All registers in this table have corresponding CLR, SET, and INV Registers at their virtual addresses, plus offsets of 0x4, 0x8, and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more infor-  
mation.  
(2)  
TABLE 4-18: CHANGE NOTICE AND PULL-UP REGISTERS MAP  
SFR  
Virtual  
Addr  
SFR  
Name  
Bits  
31/15  
Bits  
30/14  
Bits  
29/13  
Bits  
28/12  
Bits  
27/11  
Bits  
26/10  
Bits  
25/9  
Bits  
24/8  
Bits  
23/7  
Bits  
22/6  
Bits  
21/5  
Bits  
20/4  
Bits  
19/3  
Bits  
18/2  
Bits  
17/1  
Bits  
16/0  
31:16  
15:0  
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
BF88_61C0 CNCON  
ON  
FRZ  
SIDL  
Legend:  
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.  
Note 1:  
2:  
CNEN and CNPUE bit(s) are not implemented on 64-pin devices, and read as ‘0’.  
All registers in this table have corresponding CLR, SET, and INV Registers at their virtual addresses, plus offsets of 0x4, 0x8, and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more infor-  
mation.  
(2)  
TABLE 4-18: CHANGE NOTICE AND PULL-UP REGISTERS MAP (CONTINUED)  
SFR  
Virtual  
Addr  
SFR  
Name  
Bits  
31/15  
Bits  
30/14  
Bits  
29/13  
Bits  
28/12  
Bits  
27/11  
Bits  
26/10  
Bits  
25/9  
Bits  
24/8  
Bits  
23/7  
Bits  
22/6  
Bits  
21/5  
Bits  
20/4  
Bits  
19/3  
Bits  
18/2  
Bits  
17/1  
Bits  
16/0  
31:16  
15:0  
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
CNEN21(1) CNEN20(1) CNEN19(1) CNEN18 CNEN17 CNEN16  
BF88_61D0  
CNEN  
CNEN<15:0>  
31:16  
15:0  
—
—
CNPUE21(1) CNPUE20(1) CNPUE19(1) CNPUE18 CNPUE17 CNPUE16  
BF88_61E0 CNPUE  
CNPUE<15:0>  
Legend:  
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.  
CNEN and CNPUE bit(s) are not implemented on 64-pin devices, and read as ‘0’.  
All registers in this table have corresponding CLR, SET, and INV Registers at their virtual addresses, plus offsets of 0x4, 0x8, and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more infor-  
Note 1:  
2:  
mation.  
(1)  
TABLE 4-19: PARALLEL MASTER PORT REGISTERS MAP  
SFR  
Virtual  
Addr  
SFR  
Name  
Bits  
31/15  
Bits  
30/14  
Bits  
29/13  
Bits  
28/12  
Bits  
27/11  
Bits  
26/10  
Bits  
25/9  
Bits  
24/8  
Bits  
23/7  
Bits  
22/6  
Bits  
21/5  
Bits  
20/4  
Bits  
19/3  
Bits  
18/2  
Bits  
17/1  
Bits  
16/0  
31:16  
15:0  
—
ON  
—
—
FRZ  
—
—
SIDL  
—
—
—
—
—
—
—
—
—
—
ALP  
—
—
CS2P  
—
—
CS1P  
—
—
—
—
—
WRSP  
—
—
RDSP  
—
BF80_7000 PMCON  
BF80_7010 PMMODE  
BF80_7020 PMADDR  
BF80_7030 PMDOUT  
ADRMUX<1:0>  
PMPTTL PTWREN PTRDEN  
CSF<1:0>  
31:16  
15:0  
—
—
—
MODE16  
—
—
—
—
BUSY  
—
IRQM<1:0>  
—
INCM<1:0>  
MODE<1:0>  
WAITB<1:0>  
WAITM<3:0>  
— —  
WAITE<1:0>  
— —  
31:16  
—
—
—
—
—
—
—
—
—
15:0 CS2EN/A15 CS1EN/A14  
ADDR<13:0>  
31:16  
15:0  
DATAOUT<31:0>  
DATAIN<31:0>  
31:16  
15:0  
BF80_7040  
PMDIN  
31:16  
15:0  
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
BF80_7050 PMAEN  
BF80_7060 PMSTAT  
PTEN<15:0>  
31:16  
15:0  
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
IBF  
IBOV  
IB3F  
IB2F  
IB1F  
IB0F  
OBE  
OBUF  
OB3E  
OB2E  
OB1E  
OB0E  
Legend:  
Note 1:  
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.  
All registers in this table have corresponding CLR, SET, and INV Registers at their virtual addresses, plus offsets of 0x4, 0x8, and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more infor-  
mation.  
TABLE 4-20: PROGRAMMING AND DIAGNOSTICS REGISTERS MAP  
SFR  
Virtual  
Addr  
SFR  
Name  
Bits  
31/15  
Bits  
30/14  
Bits  
29/13  
Bits  
28/12  
Bits  
27/11  
Bits  
26/10  
Bits  
25/9  
Bits  
24/8  
Bits  
23/7  
Bits  
22/6  
Bits  
21/5  
Bits  
20/4  
Bits  
19/3  
Bits  
18/2  
Bits  
17/1  
Bits  
16/0  
31:16  
15:0  
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
BF80_F200 DDPCON  
Legend:  
DDPUSB DDPU1  
DDPU2 DDPSPI1 JTAGEN  
TROEN  
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.  
TABLE 4-21: PREFETCH REGISTERS MAP  
SFR  
Virtual  
Addr  
SFR  
Name  
Bits  
31/15  
Bits  
30/14  
Bits  
29/13  
Bits  
28/12  
Bits  
27/11  
Bits  
26/10  
Bits  
25/9  
Bits  
24/8  
Bits  
23/7  
Bits  
22/6  
Bits  
21/5  
Bits  
20/4  
Bits  
19/3  
Bits  
18/2  
Bits  
17/1  
Bits  
16/0  
31:16  
15:0  
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
CHECOH  
—
BF88_4000 CHECON(1)  
BF88_4010 CHEACC(1)  
DCSZ<1:0>  
PREFEN<1:0>  
PFMWS<2:0>  
31:16 CHEWEN  
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
CHEIDX<3:0>  
15:0  
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
LTAG  
BOOT  
LTAG<23:16>  
31:16  
BF88_4020 CHETAG(1)  
LTAG<15:4>  
LVALID  
LLOCK  
LTYPE  
—
15:0  
31:16  
15:0  
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
BF88_4030 CHEMSK(1)  
BF88_4040 CHEW0  
BF88_4050 CHEW1  
BF88_4060 CHEW2  
BF88_4070 CHEW3  
BF88_4080 CHELRU  
BF88_4090 CHEHIT  
LMASK<15:5>  
—
—
—
31:16  
15:0  
CHEW0<31:0>  
CHEW1<31:0>  
CHEW2<31:0>  
CHEW3<31:0>  
31:16  
15:0  
31:16  
15:0  
31:16  
15:0  
—
—
—
—
—
—
—
CHELRU<24:16>  
31:16  
15:0  
CHELRU<15:0>  
CHEHIT<31:0>  
31:16  
15:0  
31:16  
15:0  
BF88_40A0 CHEMIS  
BF88_40C0 CHEPFABT  
CHEMIS<31:0>  
31:16  
15:0  
CHEPFABT<31:0>  
Legend:  
Note 1:  
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.  
This register has corresponding CLR, SET, and INV Registers at its virtual address, plus an offset of 0x4, 0x8, and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more information.  
(1)  
TABLE 4-22: RTCC REGISTERS MAP  
SFR  
Virtual  
Addr  
SFR  
Name  
Bits  
31/15  
Bits  
30/14  
Bits  
29/13  
Bits  
28/12  
Bits  
27/11  
Bits  
26/10  
Bits  
25/9  
Bits  
24/8  
Bits  
23/7  
Bits  
22/6  
Bits  
21/5  
Bits  
20/4  
Bits  
19/3  
Bits  
18/2  
Bits  
17/1  
Bits  
16/0  
31:16  
15:0  
—
ON  
—
—
FRZ  
—
—
SIDL  
—
—
—
—
—
—
—
—
—
—
CAL<11:0>  
BF80_0200 RTCCON  
BF80_0210 RTCALRM  
RTSEC  
SEL  
RTC  
CLKON  
—
—
—
—
—
—
—
—
RTCWREN RTCSYNC HALFSEC RTCOE  
31:16  
—
—
—
—
—
—
ALRM  
SYNC  
15:0 ALRMEN  
CHIME  
PIV  
AMASK<3:0>  
ARPT<7:0>  
Legend:  
Note 1:  
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.  
All registers in this table have corresponding CLR, SET, and INV Registers at their virtual addresses, plus offsets of 0x4, 0x8, and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more  
information.  
(1)  
TABLE 4-22: RTCC REGISTERS MAP (CONTINUED)  
SFR  
Virtual  
Addr  
SFR  
Name  
Bits  
31/15  
Bits  
30/14  
Bits  
29/13  
Bits  
28/12  
Bits  
27/11  
Bits  
26/10  
Bits  
25/9  
Bits  
24/8  
Bits  
23/7  
Bits  
22/6  
Bits  
21/5  
Bits  
20/4  
Bits  
19/3  
Bits  
18/2  
Bits  
17/1  
Bits  
16/0  
31:16  
15:0  
HR10<3:0>  
HR01<3:0>  
MIN10<3:0>  
MIN01<3:0>  
BF80_0220 RTCTIME  
BF80_0230 RTCDATE  
BF80_0240 ALRMTIME  
BF80_0250 ALRMDATE  
SEC10<3:0>  
YEAR10<3:0>  
DAY10<3:0>  
MIN10<3:0>  
SEC10<3:0>  
SEC01<3:0>  
YEAR01<3:0>  
DAY01<3:0>  
MIN01<3:0>  
SEC01<3:0>  
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
31:16  
15:0  
MONTH10<3:0>  
MONTH01<3:0>  
WDAY01<3:0>  
MIN01<3:0>  
—
—
—
31:16  
15:0  
MIN10<3:0>  
—
—
—
31:16  
15:0  
—
—
—
—
—
—
—
—
MONTH10<3:0>  
MONTH01<3:0>  
WDAY01<3:0>  
DAY10<3:0>  
DAY01<3:0>  
—
—
Legend:  
Note 1:  
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.  
All registers in this table have corresponding CLR, SET, and INV Registers at their virtual addresses, plus offsets of 0x4, 0x8, and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more  
information.  
TABLE 4-23: DEVCFG: DEVICE CONFIGURATION WORD SUMMARY  
SFR  
Virtual  
Addr  
SFR  
Name  
Bits  
31/15  
Bits  
30/14  
Bits  
29/13  
Bits  
28/12  
Bits  
27/11  
Bits  
26/10  
Bits  
25/9  
Bits  
24/8  
Bits  
23/7  
Bits  
22/6  
Bits  
21/5  
Bits  
20/4  
Bits  
19/3  
Bits  
18/2  
Bits  
17/1  
Bits  
16/0  
31:16  
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
BFC0_2FF0 DEVCFG3  
BFC0_2FF4 DEVCFG2  
15:0 USERID15 USERID14 USERID13 USERID12 USERID11 USERID10 USERID9 USERID8 USERID7 USERID6 USERID5 USERID4 USERID3 USERID2 USERID1 USERID0  
31:16  
15:0 FUPLLEN(1)  
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
FUPLLIDIV<2:0>(1)  
—
—
—
—
—
—
FPLLMULT<2:0>  
—
—
—
—
FPLLODIV<2:0>  
FPLLIDIV<2:0>  
31:16  
15:0  
—
—
—
FWDTEN  
—
—
WDTPS<4:0>  
BFC0_2FF8 DEVCFG1  
OSC  
IOFNC  
FCKSM<1:0>  
FPBDIV<1:0>  
—
POSCMD<1:0>  
IESO  
FSOSCEN  
—
—
FNOSC<2:0>  
PWP17  
31:16  
15:0  
—
—
—
CP  
—
—
—
—
—
—
BWP  
—
—
—
—
—
—
—
—
—
PWP19  
ICESEL  
PWP18  
—
PWP16  
BFC0_2FFC DEVCFG0  
PWP15  
PWP14  
PWP13  
PWP12  
DEBUG<1:0>  
Legend:  
Note 1:  
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.  
These bits are only available on PIC32MX4XX devices.  
TABLE 4-24: DEVICE AND REVISION ID SUMMARY  
SFR  
Virtual  
Addr  
SFR  
Name  
Bits  
31/15  
Bits  
30/14  
Bits  
29/13  
Bits  
28/12  
Bits  
27/11  
Bits  
26/10  
Bits  
25/9  
Bits  
24/8  
Bits  
23/7  
Bits  
22/6  
Bits  
21/5  
Bits  
20/4  
Bits  
19/3  
Bits  
18/2  
Bits  
17/1  
Bits  
16/0  
31:16  
15:0  
VER<3:0>  
DEVID<27:16>  
BF80_F220  
DEVID  
DEVID<15:0>  
Legend:  
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.  
TABLE 4-25: USB REGISTERS MAP  
SFR  
Virtual  
Addr  
SFR  
Name  
Bits  
31/15  
Bits  
30/14  
Bits  
29/13  
Bits  
28/12  
Bits  
27/11  
Bits  
26/10  
Bits  
25/9  
Bits  
24/8  
Bits  
23/7  
Bits  
22/6  
Bits  
21/5  
Bits  
20/4  
Bits  
19/3  
Bits  
18/2  
Bits  
17/1  
Bits  
16/0  
31:16  
15:0  
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
IDIF  
—
—
—
—
—
—
—
—
—
—
—
—
—
—
VBUSVDIF  
—
BF88_5040 U1OTGIR  
BF88_5050 U1OTGIE  
T1MSECIF LSTATEIF ACTVIF  
SESVDIF SESENDIF  
31:16  
15:0  
—
—
—
—
—
IDIE  
—
T1MSECIE LSTATEIE ACTVIE SESVDIE SESENDIE  
VBUSVDIE  
—
31:16  
15:0  
—
—
—
—
LSTATE  
—
—
—
—
—
SESVD  
—
—
SESEND  
—
U1OTG  
BF88_5060  
STAT  
ID  
VBUSVD  
—
31:16  
—
BF88_5070 U1OTGCON  
BF88_5080 U1PWRC  
DPPUL  
DWN  
DMPUL  
DWN  
15:0  
31:16  
15:0  
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
DPPULUP DMPULUP  
VBUSON  
OTGEN VBUSCHG VBUSDIS  
—
UACTPND  
—
—
—
—
—
—
—
—
USLPGRD  
—
—
—
—
—
—
—
—
—
USUS  
PEND  
USBPWR  
31:16  
—
—
URSTIF  
DETACHIF  
—
BF88_5200  
BF88_5210  
BF88_5220  
BF88_5230  
U1IR  
U1IE  
RESUME  
IF  
15:0  
31:16  
15:0  
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
STALLIF ATTACHIF  
IDLEIF  
—
TRNIF  
—
SOFIF  
—
UERRIF  
—
—
—
—
URSTIE  
DETACHIE  
—
RESUME  
IE  
STALLIE ATTACHIE  
IDLEIE  
—
TRNIE  
—
SOFIE  
—
UERRIE  
31:16  
15:0  
—
BTSEF  
—
—
BMXEF  
—
—
DMAEF  
—
—
CRC5EF  
EOFEF  
—
U1EIR  
U1EIE  
BTOEF  
—
DFN8EF CRC16EF  
PIDEF  
—
31:16  
15:0  
—
—
CRC5EE  
EOFEE  
—
BTSEE  
—
BMXEE  
DMAEE  
BTOEE  
—
DFN8EE CRC16EE  
PIDEE  
31:16  
15:0  
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
DIR  
—
—
PPBI  
—
—
—
BF88_5240 U1STAT  
BF88_5250 U1CON  
ENDPT<3:0>  
—
31:16  
—
—
SE0  
—
—
PKTDIS  
TOKBUSY  
—
—
—
—
USBEN  
SOFEN  
—
15:0  
—
—
—
—
—
—
—
—
JSTATE  
USBRST HOSTEN RESUME PPBRST  
31:16  
15:0  
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
LSPDEN  
—
—
—
DEVADDR<6:0>  
—
—
—
—
—
—
—
—
BF80_5260 U1ADDR  
BF88_5270 U1BDTP1  
BF88_5280 U1FRML  
BF88_5290 U1FRMH  
31:16  
15:0  
—
—
—
—
—
—
—
BDTPTRL<7:1>  
—
31:16  
15:0  
—
—
—
FRML<7:0>  
31:16  
15:0  
—
—
—
—
—
—
—
—
—
—
—
—
FRMH<10:8>  
Legend:  
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.  
TABLE 4-25: USB REGISTERS MAP (CONTINUED)  
SFR  
Virtual  
Addr  
SFR  
Name  
Bits  
31/15  
Bits  
30/14  
Bits  
29/13  
Bits  
28/12  
Bits  
27/11  
Bits  
26/10  
Bits  
25/9  
Bits  
24/8  
Bits  
23/7  
Bits  
22/6  
Bits  
21/5  
Bits  
20/4  
Bits  
19/3  
Bits  
18/2  
Bits  
17/1  
Bits  
16/0  
31:16  
15:0  
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
BF88_52A0  
U1TOK  
PID<3:0>  
EP<3:0>  
31:16  
15:0  
—
—
—
—
—
—
—
BF88_52B0 U1SOF  
BF88_52C0 U1BDTP2  
BF88_52D0 U1BDTP3  
BF88_52E0 U1CNFG1  
CNT<7:0>  
31:16  
15:0  
—
BDTPTRH<7:0>  
31:16  
15:0  
—
—
BDTPTRU<7:0>  
31:16  
15:0  
—
—
—
—
—
—
—
—
—
—
—
—
—
UTEYE UOEMON USBFRZ USBSIDL  
31:16  
—
LSPD  
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
BF88_5300  
BF88_5310  
BF88_5320  
BF88_5330  
BF88_5340  
BF88_5350  
BF88_5360  
BF88_5370  
BF88_5380  
U1EP0  
U1EP1  
U1EP2  
U1EP3  
U1EP4  
U1EP5  
U1EP6  
U1EP7  
U1EP8  
U1EP9  
EPCON  
DIS  
15:0  
31:16  
15:0  
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
RETRYDIS  
EPRXEN EPTXEN EPSTALL EPHSHK  
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
EPCON  
DIS  
—
EPRXEN EPTXEN EPSTALL EPHSHK  
31:16  
15:0  
—
—
—
—
—
—
EPCON  
DIS  
—
EPRXEN EPTXEN EPSTALL EPHSHK  
31:16  
15:0  
—
—
—
—
—
—
EPCON  
DIS  
—
EPRXEN EPTXEN EPSTALL EPHSHK  
31:16  
15:0  
—
—
—
—
—
—
EPCON  
DIS  
—
EPRXEN EPTXEN EPSTALL EPHSHK  
31:16  
15:0  
—
—
—
—
—
—
EPCON  
DIS  
—
EPRXEN EPTXEN EPSTALL EPHSHK  
31:16  
15:0  
—
—
—
—
—
—
EPCON  
DIS  
—
EPRXEN EPTXEN EPSTALL EPHSHK  
31:16  
15:0  
—
—
—
—
—
—
EPCON  
DIS  
—
EPRXEN EPTXEN EPSTALL EPHSHK  
31:16  
15:0  
—
—
—
—
—
—
EPCON  
DIS  
—
EPRXEN EPTXEN EPSTALL EPHSHK  
31:16  
15:0  
—
—
—
—
—
—
BF88_5390  
EPCON  
DIS  
—
EPRXEN EPTXEN EPSTALL EPHSHK  
Legend:  
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.  
TABLE 4-25: USB REGISTERS MAP (CONTINUED)  
SFR  
Virtual  
Addr  
SFR  
Name  
Bits  
31/15  
Bits  
30/14  
Bits  
29/13  
Bits  
28/12  
Bits  
27/11  
Bits  
26/10  
Bits  
25/9  
Bits  
24/8  
Bits  
23/7  
Bits  
22/6  
Bits  
21/5  
Bits  
20/4  
Bits  
19/3  
Bits  
18/2  
Bits  
17/1  
Bits  
16/0  
31:16  
15:0  
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
BF88_53A0 U1EP10  
BF88_53B0 U1EP11  
BF88_53C0 U1EP12  
BF88_53D0 U1EP13  
BF88_53E0 U1EP14  
BF88_53F0 U1EP15  
EPCON  
DIS  
EPRXEN EPTXEN EPSTALL EPHSHK  
31:16  
15:0  
—
—
—
—
—
EPCON  
DIS  
EPRXEN EPTXEN EPSTALL EPHSHK  
31:16  
15:0  
—
—
—
—
—
EPCON  
DIS  
EPRXEN EPTXEN EPSTALL EPHSHK  
31:16  
15:0  
—
—
—
—
—
EPCON  
DIS  
EPRXEN EPTXEN EPSTALL EPHSHK  
31:16  
15:0  
—
—
—
—
—
EPCON  
DIS  
EPRXEN EPTXEN EPSTALL EPHSHK  
31:16  
15:0  
—
—
—
—
—
EPCON  
DIS  
EPRXEN EPTXEN EPSTALL EPHSHK  
Legend:  
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.  
PIC32MX3XX/4XX  
5.0  
FLASH PROGRAM MEMORY  
Note:  
This data sheet summarizes the features of  
the PIC32MX3XX/4XX family of devices. It  
is not intended to be a comprehensive  
reference source. Refer to the “PIC32MX  
Family Reference Manual” Section 5.  
“Flash Program Memory” (DS61121) for  
a detailed description of this peripheral.  
The manual is available from the Microchip  
web site (www.Microchip.com/PIC32).  
PIC32MX3XX/4XX devices contain an internal  
program Flash memory for executing user code. There  
are three methods by which the user can program this  
memory:  
1. Run-Time Self Programming (RTSP)  
2. In-Circuit Serial Programming™ (ICSP™)  
3. EJTAG Programming  
RTSP is performed by software executing from either  
Flash or RAM memory. EJTAG is performed using the  
EJTAG port of the device and a EJTAG capable pro-  
grammer. ICSP is performed using a serial data con-  
nection to the device and allows much faster  
programming times than RTSP. RTSP techniques are  
described in this chapter. The ICSP and EJTAG meth-  
ods are described in the “PIC32MX3XX/4XX Program-  
ming Specification” (DS61145) document, which may  
be downloaded from the Microchip web site.  
© 2009 Microchip Technology Inc.  
Preliminary  
DS61143F-page 55  
PIC32MX3XX/4XX  
NOTES:  
DS61143F-page 56  
Preliminary  
© 2009 Microchip Technology Inc.  
PIC32MX3XX/4XX  
6.0  
RESETS  
Note:  
This data sheet summarizes the features of  
the PIC32MX3XX/4XX family of devices. It  
is not intended to be a comprehensive  
reference source. Refer to the “PIC32MX  
Family Reference Manual” Section 7.  
“Resets” (DS61118) for  
a
detailed  
description of this peripheral.  
The manual is available from the Microchip  
web site (www.Microchip.com/PIC32).  
The Reset module combines all Reset sources and  
controls the device Master Reset signal, SYSRST. The  
following is a list of device Reset sources:  
• POR: Power-on Reset  
• MCLR: Master Clear Reset Pin  
• SWR: Software Reset  
• WDTR: Watchdog Timer Reset  
• BOR: Brown-out Reset  
• CMR: Configuration Mismatch Reset  
A simplified block diagram of the Reset module is  
shown in Figure 6-1.  
FIGURE 6-1:  
SYSTEM RESET BLOCK DIAGRAM  
MCLR  
MCLR  
Glitch Filter  
Sleep or Idle  
WDTR  
POR  
WDT  
Time-out  
Voltage  
Regulator  
Enabled  
Power-up  
Timer  
SYSRST  
VDD  
VDD Rise  
Detect  
BOR  
Brown-out  
Reset  
Configuration  
Mismatch  
Reset  
CMR  
SWR  
Software Reset  
© 2009 Microchip Technology Inc.  
Preliminary  
DS61143F-page 57  
PIC32MX3XX/4XX  
NOTES:  
DS61143F-page 58  
Preliminary  
© 2009 Microchip Technology Inc.  
PIC32MX3XX/4XX  
The PIC32MX3XX/4XX interrupts module includes the  
following features:  
7.0  
INTERRUPT CONTROLLER  
Note:  
This data sheet summarizes the features of  
the PIC32MX3XX/4XX family of devices. It  
is not intended to be a comprehensive  
reference source. Refer to the “PIC32MX  
Family Reference Manual” Section 8.  
“Interrupt Controller” (DS61108) for a  
detailed description of this peripheral.  
• Up to 96 interrupt sources  
• Up to 64 interrupt vectors  
• Single and Multi-Vector mode operations  
• 5 external interrupts with edge polarity control  
• Interrupt proximity timer  
• Module Freeze in Debug mode  
• 7 user-selectable priority levels for each vector  
The manual is available from the Microchip  
web site (www.Microchip.com/PIC32).  
• 4 user-selectable subpriority levels within each  
priority  
PIC32MX3XX/4XX devices generate interrupt requests  
in response to interrupt events from peripheral mod-  
ules. The Interrupt Control module exists externally to  
the CPU logic and prioritizes the interrupt events before  
presenting them to the CPU.  
• Dedicated shadow set for highest priority level  
• Software can generate any interrupt  
• User-configurable interrupt vector table location  
• User-configurable interrupt vector spacing  
FIGURE 7-1:  
INTERRUPT CONTROLLER MODULE  
Vector Number  
Interrupt Controller  
CPU Core  
Priority Level  
Shadow Set Number  
Note: Several of the registers cited in this section are not in the interrupt controller module. These registers (and  
bits) are associated with the CPU. Details about them are available in Section 3.0 "PIC32MX MCU".  
To avoid confusion, a typographic distinction is made for registers in the CPU. The register names in this  
section, and all other sections of this manual, are signified by uppercase letters only.CPU register names  
are signified by upper and lowercase letters. For example, INTSTAT is an Interrupts register; whereas,  
IntCtl is a CPU register.  
© 2009 Microchip Technology Inc.  
Preliminary  
DS61143F-page 59  
PIC32MX3XX/4XX  
TABLE 7-1:  
INTERRUPT IRQ AND VECTOR LOCATION  
Vector  
Number  
Interrupt Source(1)  
IRQ  
Interrupt Bit Location  
Highest Natural Order Priority  
Flag  
Enable  
Priority  
Subpriority  
CT – Core Timer Interrupt  
0
0
IFS0<0>  
IFS0<1>  
IFS0<2>  
IFS0<3>  
IFS0<4>  
IFS0<5>  
IFS0<6>  
IFS0<7>  
IFS0<8>  
IFS0<9>  
IFS0<10>  
IFS0<11>  
IFS0<12>  
IFS0<13>  
IFS0<14>  
IFS0<15>  
IFS0<16>  
IFS0<17>  
IFS0<18>  
IFS0<19>  
IFS0<20>  
IFS0<21>  
IFS0<22>  
IFS0<23>  
IFS0<24>  
IFS0<25>  
IFS0<26>  
IFS0<27>  
IFS0<28>  
IFS0<29>  
IFS0<30>  
IFS0<31>  
IFS1<0>  
IFS1<1>  
IFS1<2>  
IFS1<3>  
IFS1<4>  
IEC0<0>  
IEC0<1>  
IEC0<2>  
IEC0<3>  
IEC0<4>  
IEC0<5>  
IEC0<6>  
IEC0<7>  
IEC0<8>  
IEC0<9>  
IEC0<10>  
IEC0<11>  
IEC0<12>  
IEC0<13>  
IEC0<14>  
IEC0<15>  
IEC0<16>  
IEC0<17>  
IEC0<18>  
IEC0<19>  
IEC0<20>  
IEC0<21>  
IEC0<22>  
IEC0<23>  
IEC0<24>  
IEC0<25>  
IEC0<26>  
IEC0<27>  
IEC0<28>  
IEC0<29>  
IEC0<30>  
IEC0<31>  
IEC1<0>  
IEC1<1>  
IEC1<2>  
IEC1<3>  
IEC1<4>  
IPC0<4:2>  
IPC0<12:10>  
IPC0<20:18>  
IPC0<28:26>  
IPC1<4:2>  
IPC0<1:0>  
IPC0<9:8>  
CS0 – Core Software Interrupt 0  
CS1 – Core Software Interrupt 1  
INT0 – External Interrupt 0  
T1 – Timer1  
1
1
2
2
IPC0<17:16>  
IPC0<25:24>  
IPC1<1:0>  
3
3
4
4
IC1 – Input Capture 1  
5
5
IPC1<12:10>  
IPC1<20:18>  
IPC1<28:26>  
IPC2<4:2>  
IPC1<9:8>  
OC1 – Output Compare 1  
INT1 – External Interrupt 1  
T2 – Timer2  
6
6
IPC1<17:16>  
IPC1<25:24>  
IPC2<1:0>  
7
7
8
8
IC2 – Input Capture 2  
9
9
IPC2<12:10>  
IPC2<20:18>  
IPC2<28:26>  
IPC3<4:2>  
IPC2<9:8>  
OC2 – Output Compare 2  
INT2 – External Interrupt 2  
T3 – Timer3  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
29  
30  
31  
32  
33  
34  
35  
36  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
23  
23  
24  
24  
24  
25  
25  
25  
26  
27  
28  
29  
30  
IPC2<17:16>  
IPC2<25:24>  
IPC3<1:0>  
IC3 – Input Capture 3  
IPC3<12:10>  
IPC3<20:18>  
IPC3<28:26>  
IPC4<4:2>  
IPC3<9:8>  
OC3 – Output Compare 3  
INT3 – External Interrupt 3  
T4 – Timer4  
IPC3<17:16>  
IPC3<25:24>  
IPC4<1:0>  
IC4 – Input Capture 4  
IPC4<12:10>  
IPC4<20:18>  
IPC4<28:26>  
IPC5<4:2>  
IPC4<9:8>  
OC4 – Output Compare 4  
INT4 – External Interrupt 4  
T5 – Timer5  
IPC4<17:16>  
IPC4<25:24>  
IPC5<1:0>  
IC5 – Input Capture 5  
IPC5<12:10>  
IPC5<20:18>  
IPC5<28:26>  
IPC5<28:26>  
IPC5<28:26>  
IPC6<4:2>  
IPC5<9:8>  
OC5 – Output Compare 5  
SPI1E – SPI1 Fault  
IPC5<17:16>  
IPC5<25:24>  
IPC5<25:24>  
IPC5<25:24>  
IPC6<1:0>  
SPI1TX – SPI1 Transfer Done  
SPI1RX – SPI1 Receive Done  
U1E – UART1 Error  
U1RX – UART1 Receiver  
U1TX – UART1 Transmitter  
I2C1B – I2C1 Bus Collision Event  
I2C1S – I2C1 Slave Event  
I2C1M – I2C1 Master Event  
CN – Input Change Interrupt  
AD1 – ADC1 Convert Done  
PMP – Parallel Master Port  
CMP1 – Comparator Interrupt  
CMP2 – Comparator Interrupt  
IPC6<4:2>  
IPC6<1:0>  
IPC6<4:2>  
IPC6<1:0>  
IPC6<12:10>  
IPC6<12:10>  
IPC6<12:10>  
IPC6<20:18>  
IPC6<28:26>  
IPC7<4:2>  
IPC6<9:8>  
IPC6<9:8>  
IPC6<9:8>  
IPC6<17:16>  
IPC6<25:24>  
IPC7<1:0>  
IPC7<12:10>  
IPC7<20:18>  
IPC7<9:8>  
IPC7<17:16>  
Note 1: Not all interrupt sources are available on all devices.  
See Table 1: “PIC32MX General Purpose – Features” and Table 2: “PIC32MX USB – Features” for  
available peripherals.  
DS61143F-page 60  
Preliminary  
© 2009 Microchip Technology Inc.  
PIC32MX3XX/4XX  
TABLE 7-1:  
INTERRUPT IRQ AND VECTOR LOCATION (CONTINUED)  
Vector  
Number  
Interrupt Source(1)  
IRQ  
Interrupt Bit Location  
Highest Natural Order Priority  
SPI2E – SPI2 Fault  
Flag  
Enable  
Priority  
Subpriority  
37  
38  
39  
40  
41  
42  
43  
44  
45  
46  
47  
48  
49  
50  
51  
56  
57  
31  
31  
31  
32  
32  
32  
33  
33  
33  
34  
35  
36  
37  
38  
39  
44  
45  
IFS1<5>  
IFS1<6>  
IEC1<5>  
IEC1<6>  
IPC7<28:26>  
IPC7<28:26>  
IPC7<28:26>  
IPC8<4:2>  
IPC7<25:24>  
IPC7<25:24>  
IPC7<25:24>  
IPC8<1:0>  
SPI2TX – SPI2 Transfer Done  
SPI2RX – SPI2 Receive Done  
U2E – UART2 Error  
IFS1<7>  
IEC1<7>  
IFS1<8>  
IEC1<8>  
U2RX – UART2 Receiver  
U2TX – UART2 Transmitter  
I2C2B – I2C2 Bus Collision Event  
I2C2S – I2C2 Slave Event  
I2C2M – I2C2 Master Event  
FSCM – Fail-Safe Clock Monitor  
RTCC – Real-Time Clock  
DMA0 – DMA Channel 0  
DMA1 – DMA Channel 1  
DMA2 – DMA Channel 2  
DMA3 – DMA Channel 3  
FCE – Flash Control Event  
USB  
IFS1<9>  
IEC1<9>  
IPC8<4:2>  
IPC8<1:0>  
IFS1<10>  
IFS1<11>  
IFS1<12>  
IFS1<13>  
IFS1<14>  
IFS1<15>  
IFS1<16>  
IFS1<17>  
IFS1<18>  
IFS1<19>  
IFS1<24>  
IFS1<25>  
IEC1<10>  
IEC1<11>  
IEC1<12>  
IEC1<13>  
IEC1<14>  
IEC1<15>  
IEC1<16>  
IEC1<17>  
IEC1<18>  
IEC1<19>  
IEC1<24>  
IEC1<25>  
IPC8<4:2>  
IPC8<1:0>  
IPC8<12:10>  
IPC8<12:10>  
IPC8<12:10>  
IPC8<20:18>  
IPC8<28:26>  
IPC9<4:2>  
IPC8<9:8>  
IPC8<9:8>  
IPC8<9:8>  
IPC8<17:16>  
IPC8<25:24>  
IPC9<1:0>  
IPC9<12:10>  
IPC9<20:18>  
IPC9<28:26>  
IPC11<4:2>  
IPC11<12:10>  
IPC9<9:8>  
IPC9<17:16>  
IPC9<25:24>  
IPC11<1:0>  
IPC11<9:8>  
(Reserved)  
Lowest Natural Order Priority  
Note 1: Not all interrupt sources are available on all devices.  
See Table 1: “PIC32MX General Purpose – Features” and Table 2: “PIC32MX USB – Features” for  
available peripherals.  
© 2009 Microchip Technology Inc.  
Preliminary  
DS61143F-page 61  
PIC32MX3XX/4XX  
NOTES:  
DS61143F-page 62  
Preliminary  
© 2009 Microchip Technology Inc.  
PIC32MX3XX/4XX  
8.0  
OSCILLATOR  
CONFIGURATION  
Note:  
This data sheet summarizes the features of  
the PIC32MX3XX/4XX family of devices. It  
is not intended to be a comprehensive  
reference source. Refer to the “PIC32MX  
Family Reference Manual” Section 6.  
“Oscillator Configuration” (DS61112) for  
a detailed description of this peripheral.  
The manual is available from the Microchip  
web site (www.Microchip.com/PIC32).  
The PIC32MX oscillator system has the following  
modules and features:  
• A total of four external and internal oscillator  
options as clock sources  
• On-chip PLL (phase-locked loop) with user-  
selectable input divider, multiplier, and output  
divider to boost operating frequency on select  
internal and external oscillator sources  
• On-chip user-selectable divisor postscaler on  
select oscillator sources  
• Software-controllable switching between various  
clock sources  
• A Fail-Safe Clock Monitor (FSCM) that detects  
clock failure and permits safe application recovery  
or shutdown  
• Dedicated on-chip PLL for USB peripheral  
© 2009 Microchip Technology Inc.  
Preliminary  
DS61143F-page 63  
PIC32MX3XX/4XX  
FIGURE 8-1:  
PIC32MX3XX/4XX FAMILY CLOCK DIAGRAM  
USB PLL  
USB Clock (48 MHz)  
UFIN  
div 2  
div x  
PLL x24  
UFRCEN  
FUPLLEN  
UFIN = 4 MHz  
FUPLLDIV<2:0>  
Primary Oscillator  
POSC  
(3)  
OSC1  
C1  
XT, HS, EC  
To Internal  
Logic  
(2)  
F
R
Peripherals  
PBCLK  
Postscaler  
div x  
4 MHz ≤ FIN ≤ 5 MHz  
FIN  
XTPLL, HSPLL,  
ECPLL, FRCPLL  
XTAL  
Enable  
div x  
div y  
PLL  
(1)  
S
R
(3)  
C2  
(4)  
PLL Input Divider  
FPLLIDIV<2:0>  
PLL Output Divider  
PLLODIV<2:0>  
PBDIV<2:0>  
OSC2  
FRC  
Oscillator  
8 MHz typical  
PLL Multiplier  
PLLMULT<2:0>  
COSC<2:0>  
FRC  
CPU and Select Peripherals  
TUN<5:0>  
FRC /16  
FRCDIV  
div 16  
Postscaler  
FRCDIV<2:0>  
31.25 kHz typical  
LPRC  
SOSC  
LPRC  
Oscillator  
Secondary Oscillator (SOSC)  
SOSCO  
SOSCI  
32.768 kHz  
SOSCEN and FSOSCEN  
Clock Control Logic  
FSCM INT  
Fail-Safe  
Clock  
Monitor  
FSCM Event  
NOSC<2:0>  
COSC<2:0>  
FSCMEN<1:0>  
OSWEN  
WDT, PWRT  
Timer1, RTCC  
Notes: 1. A series resistor, RS, may be required for AT strip cut crystals.  
2. The internal feedback resistor, RF, is typically in the range of 2 to 10 MΩ.  
3. Refer to the “PIC32MX Family Reference Manual” Section 6. “Oscillator Configuration” (DS61112) for help  
determining the best oscillator components.  
4. PBCLK out is available on the OSC2 pin in certain clock modes.  
DS61143F-page 64  
Preliminary  
© 2009 Microchip Technology Inc.  
PIC32MX3XX/4XX  
9.1  
Features  
9.0  
PREFETCH CACHE  
• 16 Fully Associative Lockable Cache Lines  
• 16-byte Cache Lines  
Note:  
This data sheet summarizes the features of  
the PIC32MX3XX/4XX family of devices. It  
is not intended to be a comprehensive  
reference source. Refer to the “PIC32MX  
Family Reference Manual” Section 4.  
“Prefetch Cache” (DS61119) for a detailed  
description of this peripheral.  
• Up to 4 Cache Lines Allocated to Data  
• 2 Cache Lines with Address Mask to hold  
repeated instructions  
• Pseudo LRU replacement policy  
• All Cache Lines are software writable  
• 16-byte parallel memory fetch  
• Predictive Instruction Prefetch  
The manual is available from the Microchip  
web site (www.Microchip.com/PIC32).  
Prefetch cache increases performance for applications  
executing out of the cacheable program flash memory  
regions by implementing instruction caching, constant  
data caching, and instruction prefetching.  
FIGURE 9-1:  
PREFETCH MODULE BLOCK DIAGRAM  
FSM  
CTRL  
Tag Logic  
Cache Line  
CTRL  
Bus Ctrl  
Cache Ctrl  
Prefetch Ctrl  
Hit LRU  
Cache  
Line  
RDATA  
Address  
Encode  
Miss LRU  
Hit Logic  
Pre-Fetch  
Pre-Fetch  
PFM  
© 2009 Microchip Technology Inc.  
Preliminary  
DS61143F-page 65  
PIC32MX3XX/4XX  
NOTES:  
DS61143F-page 66  
Preliminary  
© 2009 Microchip Technology Inc.  
PIC32MX3XX/4XX  
• Fixed Priority Channel Arbitration  
10.0 DIRECT MEMORY ACCESS  
(DMA) CONTROLLER  
• Flexible DMA Channel Operating Modes:  
- Manual (software) or automatic (interrupt)  
DMA requests  
Note:  
This data sheet summarizes the features of  
the PIC32MX3XX/4XX family of devices. It  
is not intended to be a comprehensive  
reference source. Refer to the “PIC32MX  
Family Reference Manual” Section 31.  
“Direct Memory Access (DMA) Control-  
ler” (DS61117) for a detailed description of  
this peripheral.  
- One-Shot or Auto-Repeat Block Transfer  
modes  
- Channel-to-channel chaining  
• Flexible DMA Requests:  
- A DMA request can be selected from any of  
the peripheral interrupt sources  
The manual is available from the Microchip  
web site (www.Microchip.com/PIC32).  
- Each channel can select any (appropriate)  
observable interrupt as its DMA request  
source  
The PIC32MX Direct Memory Access (DMA) controller  
is a bus master module useful for data transfers  
between different devices without CPU intervention.  
The source and destination of a DMA transfer can be  
any of the memory mapped modules existent in the  
PIC32MX (such as Peripheral Bus (PBUS) devices:  
SPI, UART, I2C™, etc.) or memory itself.  
- A DMA transfer abort can be selected from  
any of the peripheral interrupt sources  
- Pattern (data) match transfer termination  
• Multiple DMA Channel Status Interrupts:  
- DMA channel block transfer complete  
- Source empty or half empty  
Following are some of the key features of the DMA  
controller module:  
- Destination full or half-full  
- DMA transfer aborted due to an external  
event  
• Four Identical Channels, each featuring:  
- Invalid DMA address generated  
• DMA Debug Support Features:  
- Auto-Increment Source and Destination  
Address Registers  
- Source and Destination Pointers  
- Most recent address accessed by a DMA  
channel  
- Memory to Memory and Memory to  
Peripheral Transfers  
- Most recent DMA channel to transfer data  
• CRC Generation Module:  
• Automatic Word-Size Detection:  
- Transfer Granularity, down to byte level  
- CRC module can be assigned to any of the  
available channels  
- Bytes need not be word-aligned at source  
and destination  
- CRC module is highly configurable  
FIGURE 10-1:  
DMA BLOCK DIAGRAM  
INT Controller  
System IRQ  
Peripheral Bus  
Address Decoder  
Channel 0 Control  
Channel 1 Control  
I
0
I
I
Y
Bus Interface  
1
Device Bus + Bus Arbitration  
2
I
Global Control  
(DMACON)  
Channel n Control  
n
Channel Priority  
Arbitration  
© 2009 Microchip Technology Inc.  
Preliminary  
DS61143F-page 67  
PIC32MX3XX/4XX  
NOTES:  
DS61143F-page 68  
Preliminary  
© 2009 Microchip Technology Inc.  
PIC32MX3XX/4XX  
The PIC32MX USB module includes the following  
features:  
11.0 USB ON-THE-GO (OTG)  
Note:  
This data sheet summarizes the features of  
• USB Full-Speed Support for Host and Device  
• Low-Speed Host Support  
the PIC32MX3XX/4XX family of devices. It  
is not intended to be a comprehensive  
reference source. Refer to the “PIC32MX  
Family Reference Manual” Section 27.  
“USB On-The-Go (OTG)” (DS61126) for a  
detailed description of this peripheral.  
• USB OTG Support  
• Integrated Signaling Resistors  
• Integrated Analog Comparators for VBUS  
Monitoring  
The manual is available from the Microchip  
web site (www.Microchip.com/PIC32).  
• Integrated USB Transceiver  
• Transaction Handshaking Performed by  
Hardware  
The Universal Serial Bus (USB) module contains ana-  
log and digital components to provide a USB 2.0 full-  
speed and low-speed embedded host, full-speed  
device, or OTG implementation with a minimum of  
external components. This module in Host mode is  
intended for use as an embedded host and therefore  
does not implement a UHCI or OHCI controller.  
• Endpoint Buffering Anywhere in System RAM  
• Integrated DMA to Access System RAM and  
Flash  
Note:  
IMPORTANT: The implementation and  
use of the USB specifications, as well as  
other third-party specifications or technol-  
ogies, may require licensing; including,  
but not limited to, USB Implementers  
Forum, Inc. (also referred to as USB-IF).  
The user is fully responsible for investigat-  
ing and satisfying any applicable licensing  
obligations.  
The USB module consists of the clock generator, the  
USB voltage comparators, the transceiver, the Serial  
Interface Engine (SIE), a dedicated USB DMA control-  
ler, pull-up and pull-down resistors, and the register  
interface. A block diagram of the PIC32MX USB OTG  
module is presented in Figure 11-1.  
The clock generator provides the 48 MHz clock  
required for USB full-speed and low-speed communi-  
cation. The voltage comparators monitor the voltage on  
the VBUS pin to determine the state of the bus. The  
transceiver provides the analog translation between  
the USB bus and the digital logic. The SIE is a state  
machine that transfers data to and from the endpoint  
buffers, and generates the hardware protocol for data  
transfers. The USB DMA controller transfers data  
between the data buffers in RAM and the SIE. The inte-  
grated pull-up and pull-down resistors eliminate the  
need for external signaling components. The register  
interface allows the CPU to configure and  
communicate with the module.  
© 2009 Microchip Technology Inc.  
Preliminary  
DS61143F-page 69  
PIC32MX3XX/4XX  
FIGURE 11-1:  
PIC32MX3XX/4XX FAMILY USB INTERFACE DIAGRAM  
USBEN  
FRC  
USB Suspend  
Oscillator  
8 MHz Typical  
CPU Clock Not POSC  
Sleep  
TUN<5:0>(4)  
Primary Oscillator  
(POSC)  
(5)  
UFIN  
PLL  
Div x  
Div 2  
UFRCEN(3)  
OSC1  
FUPLLEN(6)  
FUPLLIDIV(6)  
USB Suspend  
To Clock Generator for Core and Peripherals  
Sleep or Idle  
OSC2  
(PB out)(1)  
USB Module  
USB  
SRP Charge  
SRP Discharge  
Voltage  
VBUS  
Comparators  
48 MHz USB Clock(7)  
Full Speed Pull-up  
D+(2)  
Registers  
and  
Control  
Interface  
Host Pull-down  
SIE  
Transceiver  
Low Speed Pull-up  
D-(2)  
DMA  
System  
RAM  
Host Pull-down  
ID Pull-up  
ID(8)  
(8)  
VBUSON  
Transceiver Power 3.3V  
VUSB  
Note 1: PB clock is only available on this pin for select EC modes.  
2: Pins can be used as digital inputs when USB is not enabled.  
3: This bit field is contained in the OSCCON register.  
4: This bit field is contained in the OSCTRM register.  
5: USB PLL UFIN requirements: 4 MHz.  
6: This bit field is contained in the DEVCFG2 register.  
7: A 48 MHz clock is required for proper USB operation.  
8: Pins can be used as GPIO when the USB module is disabled.  
DS61143F-page 70  
Preliminary  
© 2009 Microchip Technology Inc.  
PIC32MX3XX/4XX  
These functions depend on which peripheral features  
are on the device. In general, when a peripheral is func-  
tioning, that pin may not be used as a general purpose  
I/O pin.  
12.0 I/O PORTS  
Note:  
This data sheet summarizes the features of  
the PIC32MX3XX/4XX family of devices. It  
is not intended to be a comprehensive  
reference source. Refer to the “PIC32MX  
Family Reference Manual” Section 12. “I/O  
Ports” (DS61120) for a detailed description  
of this peripheral.  
Following are some of the key features of this module:  
• Individual output pin open-drain enable/disable  
• Individual input pin weak pull-up enable/disable  
• Monitor selective inputs and generate interrupt  
when change in pin state is detected  
The manual is available from the Microchip  
web site (www.Microchip.com/PIC32).  
• Operation during CPU Sleep and Idle modes  
• Fast bit manipulation using CLR, SET and INV  
registers  
General purpose I/O pins are the simplest of peripher-  
als. They allow the PIC® MCU to monitor and control  
other devices. To add flexibility and functionality, some  
pins are multiplexed with alternate function(s).  
Figure 12-1 shows a block diagram of a typical  
multiplexed I/O port.  
FIGURE 12-1:  
BLOCK DIAGRAM OF A TYPICAL MULTIPLEXED PORT STRUCTURE  
Peripheral Module  
Peripheral Module Enable  
Peripheral Output Enable  
Peripheral Output Data  
PIO Module  
RD ODC  
Data Bus  
SYSCLK  
D
Q
ODC  
CK  
EN  
Q
WR ODC  
RD TRIS  
1
IO Cell  
0
0
1
D
D
Q
Q
1
0
TRIS  
LAT  
CK  
EN  
WR TRIS  
Output Multiplexers  
Q
Q
IO Pin  
CK  
EN  
WR LAT  
WR PORT  
RD LAT  
1
0
RD PORT  
Q
Q
Q
Q
D
D
Sleep  
CK  
CK  
SYSCLK  
Synchronization  
R
Peripheral Input  
Peripheral Input Buffer  
Legend: R = Peripheral input buffer types may vary. Refer to Table 1-1 for more information.  
Note:  
This block diagram is a general representation of a shared port/peripheral structure for illustration purposes only. The  
actual structure for any specific port/peripheral combination may be different than it is shown here.  
© 2009 Microchip Technology Inc.  
Preliminary  
DS61143F - page 71  
PIC32MX3XX/4XX  
12.1.2  
DIGITAL INPUTS  
12.1 Parallel I/O (PIO) Ports  
Pins are configured as digital inputs by setting the cor-  
responding TRIS register bits = 1. When configured as  
inputs, they are either TTL buffers or Schmitt Triggers.  
Several digital pins share functionality with analog  
inputs and default to the analog inputs at POR. Setting  
the corresponding bit in the AD1PCFG register = 1  
enables the pin as a digital pin.  
All port pins have three registers (TRIS, LAT, and  
PORT) that are directly associated with their operation.  
TRIS is a data direction or tri-state control register that  
determines whether a digital pin is an input or an out-  
put. Setting a TRISx register bit = 1configures the cor-  
responding I/O pin as an input; setting a TRISx register  
bit = 0configures the corresponding I/O pin as an out-  
put. All port I/O pins are defined as inputs after a device  
Reset. Certain I/O pins are shared with analog  
peripherals and default to analog inputs after a device  
Reset.  
Digital only pins are capable of input voltages up to  
5.5V. Any pin that shares digital and analog  
functionality is limited to voltages up to VDD + 0.3V.  
.
TABLE 12-1: MAXIMUM INPUT PIN  
PORT is a register used to read the current state of the  
signal applied to the port I/O pins. Writing to a PORTx  
register performs a write to the port’s latch, LATx regis-  
ter, latching the data to the port’s I/O pins.  
VOLTAGES  
Input Pin Mode(s)  
VIH (max)  
Digital Only  
Digital + Analog  
Analog  
VIH = 5.5v  
LAT is a register used to write data to the port I/O pins.  
The LATx latch register holds the data written to either  
the LATx or PORTx registers. Reading the LATx latch  
register reads the last value written to the  
corresponding port or latch register.  
VIH = VDD + 0.03v  
VIH = VDD + 0.03v  
Note: Refer to Section 28.0 “Electrical Characteris-  
tics” regarding the VIH specification.  
Not all port I/O pins are implemented on some devices,  
therefore, the corresponding PORTx, LATx and TRISx  
register bits will read as zeros.  
Note:  
Analog levels on any pin that is defined as  
a digital input (including the ANx pins) may  
cause the input buffer to consume current  
that exceeds the device specifications.  
12.1.1  
CLR, SET AND INV REGISTERS  
Every I/O module register has a corresponding CLR  
(clear), SET (set) and INV (invert) register designed to  
provide fast atomic bit manipulations. As the name of  
the register implies, a value written to a SET, CLR or  
INV register effectively performs the implied operation,  
but only on the corresponding base register and only  
bits specified as ‘1’ are modified. Bits specified as ‘0’  
are not modified.  
12.1.3  
ANALOG INPUTS  
Certain pins can be configured as analog inputs used  
by the ADC and Comparator modules. Setting the cor-  
responding bits in the AD1PCFG register = 0enables  
the pin as an analog input pin and must have the corre-  
sponding TRIS bit set = 1 (input). If the TRIS bit is  
cleared = 0 (output), the digital output level (VOH or  
VOL) will be converted. Any time a port I/O pin is config-  
ured as analog, its digital input is disabled and the cor-  
responding PORTx register bit will read ‘0’. The  
AD1PCFG Register has a default value of 0x0000;  
therefore, all pins that share ANx functions are analog  
(not digital) by default.  
Reading SET, CLR and INV registers returns undefined  
values. To see the affects of a write operation to a SET,  
CLR or INV register, the base register must be read.  
To set PORTC bit 0, write to the LATSET register:  
LATCSET= 0x0001;  
12.1.4  
DIGITAL OUTPUTS  
To clear PORTC bit 0, write to the LATCLR register:  
LATCCLR= 0x0001;  
Pins are configured as digital outputs by setting the cor-  
responding TRIS register bits = 0. When configured as  
digital outputs, these pins are CMOS drivers or can be  
configured as open drain outputs by setting the corre-  
sponding bits in the ODCx Open-Drain Configuration  
register.  
To toggle PORTC bit 0, write to the LATINV register:  
LATCINV = 0x0001;  
Note:  
Using a PORTxINV register to toggle a bit  
is recommended because the operation is  
performed in hardware atomically, using  
fewer instructions as compared to the tra-  
ditional read-modify-write method shown  
below:  
Digital output pin voltage is limited to VDD.  
12.1.5  
ANALOG OUTPUTS  
Certain pins can be configured as analog outputs, such  
as the CVREF output voltage used by the comparator  
module. Configuring the Comparator Reference mod-  
ule to provide this output will present the analog output  
voltage on the pin, independent of the TRIS register  
setting for the corresponding pin.  
PORTC ^= 0x0001;  
DS61143F - page 72  
Preliminary  
© 2009 Microchip Technology Inc.  
PIC32MX3XX/4XX  
13.1 Additional Supported Features  
13.0 TIMER1  
• Selectable clock prescaler  
Note:  
This data sheet summarizes the features of  
• Timer operation during CPU Idle and Sleep mode  
the PIC32MX3XX/4XX family of devices. It  
is not intended to be a comprehensive  
reference source. Refer to the “PIC32MX  
Family Reference Manual” Section 14.  
• Fast bit manipulation using CLR, SET and INV  
registers  
• Asynchronous mode can be used with the SOSC  
to function as a Real-Time Clock (RTC).  
“Timers” (DS61105) for  
a
detailed  
description of this peripheral.  
The manual is available from the Microchip  
web site (www.Microchip.com/PIC32).  
This family of PIC32MX devices features one  
synchronous/asynchronous 16-bit timer that can oper-  
ate as a free-running interval timer for various timing  
applications and counting external events. This timer  
can also be used with the Low-Power Secondary  
Oscillator (SOSC) for real-time clock applications. The  
following modes are supported:  
• Synchronous Internal Timer  
• Synchronous Internal Gated Timer  
• Synchronous External Timer  
• Asynchronous External Timer  
(1)  
FIGURE 13-1:  
TIMER1 BLOCK DIAGRAM  
PR1  
Equal  
16-bit Comparator  
TMR1  
TSYNC (T1CON<2>)  
1
0
Sync  
Reset  
0
1
T1IF  
Event Flag  
Q
Q
D
TGATE (T1CON<7>)  
TCS (T1CON<1>)  
ON (T1CON<15>)  
TGATE (T1CON<7>)  
SOSCO/T1CK  
SOSCI  
x1  
Prescaler  
Gate  
Sync  
SOSCEN  
10  
00  
1, 8, 64, 256  
PBCLK  
2
TCKPS<1:0>  
(T1CON<5:4>)  
Note 1: The default state of the SOSCEN (OSCCON<1>) during a device Reset is controlled by the FSOSCEN bit in  
Configuration Word DEVCFG1.  
© 2009 Microchip Technology Inc.  
Preliminary  
DS61143F-page 73  
PIC32MX3XX/4XX  
NOTES:  
DS61143F-page 74  
Preliminary  
© 2009 Microchip Technology Inc.  
PIC32MX3XX/4XX  
14.0 TIMERS 2, 3, 4, 5  
Note:  
This data sheet summarizes the features of  
Note:  
Throughout this chapter, references to  
registers TxCON, TMRx, and PRx use ‘x’  
to represent Timer2 through 5 in 16-bit  
modes. In 32-bit modes, ‘x’ represents  
Timer2 or 4; ‘y’ represents Timer3 or 5.  
the PIC32MX3XX/4XX family of devices. It  
is not intended to be a comprehensive  
reference source. Refer to the “PIC32MX  
Family Reference Manual” Section 14.  
“Timers” (DS61105) for  
a
detailed  
description of this peripheral.  
The manual is available from the Microchip  
web site (www.Microchip.com/PIC32).  
14.1 Additional Supported Features  
• Selectable clock prescaler  
• Timers operational during CPU Idle  
This family of PIC32MX devices features four  
synchronous 16-bit timers (default) that can operate as  
a free-running interval timer for various timing applica-  
tions and counting external events. The following  
modes are supported:  
• Time base for input capture and output compare  
modules (Timer2 and Timer3 only)  
• ADC event trigger (Timer3 only)  
• Fast bit manipulation using CLR, SET and INV  
registers  
• Synchronous Internal 16-bit Timer  
• Synchronous Internal 16-bit Gated Timer  
• Synchronous External 16-bit Timer  
Two 32-bit synchronous timers are available by  
combining Timer2 with Timer3 and Timer4 with Timer5.  
The 32-bit timers can operate in three modes:  
• Synchronous Internal 32-bit Timer  
• Synchronous Internal 32-bit Gated Timer  
• Synchronous External 32-bit Timer  
FIGURE 14-1:  
TIMER2, 3, 4, 5 BLOCK DIAGRAM (16-BIT)  
Sync  
TMRx  
ADC Event  
Trigger(1)  
Comparator x 16  
PRx  
Equal  
Reset  
0
1
TxIF  
Event Flag  
TGATE (TxCON<7>)  
TCS (TxCON<1>)  
ON (TxCON<15>)  
Q
Q
D
TGATE (TxCON<7>)  
TxCK(2)  
x1  
Prescaler  
1, 2, 4, 8, 16,  
32, 64, 256  
Gate  
Sync  
10  
PBCLK  
00  
3
TCKPS (TxCON<6:4>)  
Note 1: ADC event trigger is available on Timer3 only.  
2: TxCK pins not available on 64-pin devices.  
© 2009 Microchip Technology Inc.  
Preliminary  
DS61143F-page 75  
PIC32MX3XX/4XX  
FIGURE 14-2:  
TIMER2/3, 4/5 BLOCK DIAGRAM (32-BIT)  
Reset  
TMRy  
TMRx  
Sync  
LSHalfWord  
MSHalfWord  
ADC Event  
Trigger(3)  
32-bit Comparator  
Equal  
PRy  
PRx  
TyIF Event  
Flag  
0
1
Q
Q
D
TGATE (TxCON<7>)  
TCS (TxCON<1>)  
ON (TxCON<15>)  
TGATE (TxCON<7>)  
TxCK(2)  
x1  
Prescaler  
1, 2, 4, 8, 16,  
32, 64, 256  
Gate  
Sync  
10  
00  
PBCLK  
3
TCKPS (TxCON<6:4>)  
Note 1: In this diagram, the use of “x’ in registers TxCON, TMRx, PRx, TxCK refers to either  
Timer2 or Timer4; the use of ‘y’ in registers TyCON, TMRy, PRy, TyIF refers to either Timer3 or Timer5.  
2: TxCK pins not available on 64-pin devices.  
3: ADC event trigger is available only on Timer2/3 pair.  
DS61143F-page 76  
Preliminary  
© 2009 Microchip Technology Inc.  
PIC32MX3XX/4XX  
2. Capture timer value on every edge (rising and  
falling)  
15.0 INPUT CAPTURE  
Note:  
This data sheet summarizes the features of  
3. Capture timer value on every edge (rising and  
falling), specified edge first.  
the PIC32MX3XX/4XX family of devices. It  
is not intended to be a comprehensive  
reference source. Refer to the “PIC32MX  
Family Reference Manual” Section 15.  
“Input Capture” (DS61122) for a detailed  
description of this peripheral.  
4. Prescaler Capture Event modes  
- Capture timer value on every 4th rising edge  
of input at ICx pin  
- Capture timer value on every 16th rising  
edge of input at ICx pin  
The manual is available from the Microchip  
web site (www.Microchip.com/PIC32).  
Each input capture channel can select between one of  
two 16-bit timers (Timer2 or Timer3) for the time base,  
or two 16-bit timers (Timer2 and Timer3) together to  
form a 32-bit timer. The selected timer can use either  
an internal or external clock.  
The Input Capture module is useful in applications  
requiring frequency (period) and pulse measurement.  
The PIC32MX3XX/4XX devices support up to five input  
capture channels.  
Other operational features include:  
The input capture module captures the 16-bit or 32-bit  
value of the selected Time Base registers when an  
event occurs at the ICx pin. The events that cause a  
capture event are listed below in three categories:  
• Device wake-up from capture pin during CPU  
Sleep and Idle modes  
• Interrupt on input capture event  
• 4-word FIFO buffer for capture values  
1. Simple Capture Event modes  
- Interrupt optionally generated after 1, 2, 3 or  
4 buffer locations are filled  
-
Capture timer value on every falling edge of  
input at ICx pin  
• Input capture can also be used to provide  
additional sources of external interrupts  
-
Capture timer value on every rising edge of  
input at ICx pin  
FIGURE 15-1:  
INPUT CAPTURE BLOCK DIAGRAM  
ICx Input  
Timer 3 Timer 2  
ICTMR  
0
1
ICC32  
FIFO Control  
ICxBUF<31:16>  
ICxBUF<15:0>  
Prescaler  
1, 4, 16  
Edge Detect  
ICBNE  
ICOV  
ICM<2:0>  
ICFEDGE  
ICM<2:0>  
Interrupt  
Event  
Generation  
ICxCON  
ICI<1:0>  
Data Space Interface  
Peripheral Data Bus  
Interrupt  
© 2009 Microchip Technology Inc.  
Preliminary  
DS61143F-page 77  
PIC32MX3XX/4XX  
NOTES:  
DS61143F-page 78  
Preliminary  
© 2009 Microchip Technology Inc.  
PIC32MX3XX/4XX  
The following are some of the key features:  
• Multiple output compare modules in a device  
16.0 OUTPUT COMPARE  
Note:  
This data sheet summarizes the features of  
• Programmable interrupt generation on compare  
event  
the PIC32MX3XX/4XX family of devices. It  
is not intended to be a comprehensive  
reference source. Refer to the “PIC32MX  
Family Reference Manual” Section 16.  
• Single and Dual Compare modes  
• Single and continuous output pulse generation  
• Pulse-Width Modulation (PWM) mode  
“Output Capture”  
(DS61111) for a  
detailed description of this peripheral.  
The manual is available from the Microchip  
web site (www.Microchip.com/PIC32).  
• Hardware-based PWM Fault detection and auto-  
matic output disable  
• Programmable selection of 16-bit or 32-bit time  
bases.  
The Output Compare module (OCMP) is used to gen-  
erate a single pulse or a train of pulses in response to  
selected time base events. For all modes of operation,  
the OCMP module compares the values stored in the  
OCxR and/or the OCxRS registers to the value in the  
selected timer. When a match occurs, the OCMP mod-  
ule generates an event based on the selected mode of  
operation.  
• Can operate from either of two available 16-bit  
time bases or a single 32-bit time base.  
FIGURE 16-1:  
OUTPUT COMPARE MODULE BLOCK DIAGRAM  
Set Flag bit  
(1)  
OCxIF  
(1)  
OCxRS  
Output  
Logic  
(1)  
S
R
Q
(1)  
OCxR  
OCx  
Output Enable  
3
OCM<2:0>  
Mode Select  
OCFA or OCFB  
(see Note 2)  
Comparator  
0
1
0
OCTSEL  
1
16  
16  
Period match signals  
from time bases  
(see Note 3).  
TMR register inputs  
from time bases  
(see Note 3).  
Note 1: Where ‘x’ is shown, reference is made to the registers associated with the respective output compare  
channels 1 through 5.  
2: The OCFA pin controls the OC1-OC4 channels. The OCFB pin controls the OC5 channel.  
3: Each output compare channel can use one of two selectable 16-bit time bases or a single 32-bit timer base.  
© 2009 Microchip Technology Inc.  
Preliminary  
DS61143F-page 79  
PIC32MX3XX/4XX  
NOTES:  
DS61143F-page 80  
Preliminary  
© 2009 Microchip Technology Inc.  
PIC32MX3XX/4XX  
Following are some of the key features of this module:  
17.0 SERIAL PERIPHERAL  
INTERFACE (SPI)  
• Master and Slave Modes Support  
• Four Different Clock Formats  
• Framed SPI Protocol Support  
Note:  
This data sheet summarizes the features of  
the PIC32MX3XX/4XX family of devices. It  
is not intended to be a comprehensive  
reference source. Refer to the “PIC32MX  
Family Reference Manual” Section 23.  
“Serial Peripheral Interface (SPI)”  
(DS61106) for a detailed description of this  
peripheral.  
• User Configurable 8-bit, 16-bit and 32-bit Data  
Width  
• Separate SPI Data Registers for Receive and  
Transmit  
• Programmable Interrupt Event on every 8-bit,  
16-bit and 32-bit Data Transfer  
The manual is available from the Microchip  
web site (www.Microchip.com/PIC32).  
• Operation during CPU Sleep and Idle Mode  
• Fast Bit Manipulation using CLR, SET and INV  
Registers  
The SPI module is a synchronous serial interface use-  
ful for communicating with external peripherals and  
other microcontroller devices. These peripheral  
devices may be Serial EEPROMs, shift registers, dis-  
play drivers, A/D converters, etc. The PIC32MX SPI  
module is compatible with Motorola® SPI and SIOP  
interfaces.  
FIGURE 17-1:  
SPI MODULE BLOCK DIAGRAM  
Internal  
Data Bus  
SPIxBUF  
Read  
Write  
Registers share address SPIxBUF  
SPIxRXB  
SPIxTXB  
Transmit  
Receive  
SPIxSR  
SDIx  
bit 0  
SDOx  
Shift  
Control  
Slave Select  
and Frame  
Sync Control  
Clock  
Control  
Edge  
Select  
SSx/FSYNC  
SCKx  
Baud Rate  
PBCLK  
Generator  
Enable Master Clock  
Note: Access SPIxTXB and SPIxRXB registers via SPIxBUF register.  
© 2009 Microchip Technology Inc.  
Preliminary  
DS61143F-page 81  
PIC32MX3XX/4XX  
NOTES:  
DS61143F-page 82  
Preliminary  
© 2009 Microchip Technology Inc.  
PIC32MX3XX/4XX  
18.0 INTER-INTEGRATED CIRCUIT  
2
(I C™)  
Note:  
This data sheet summarizes the features of  
the PIC32MX3XX/4XX family of devices. It  
is not intended to be a comprehensive  
reference source. Refer to the “PIC32MX  
Family Reference Manual” Section 24.  
“Inter-Integrated Circuit (I2C)” (DS61116)  
for a detailed description of this peripheral.  
The manual is available from the Microchip  
web site (www.Microchip.com/PIC32).  
The I2C module provides complete hardware support  
for both Slave and Multi-Master modes of the I2C serial  
communication standard. Figure 18-1 shows the I2C  
module block diagram.  
The PIC32MX3XX/4XX devices have up to two I2C  
interface modules, denoted as I2C1 and I2C2. Each  
I2C module has a 2-pin interface: the SCLx pin is clock  
and the SDAx pin is data.  
Each I2C module ‘I2Cx’ (x = 1 or 2) offers the following  
key features:  
• I2C Interface Supporting both Master and Slave  
Operation.  
• I2C Slave Mode Supports 7 and 10-bit Address.  
• I2C Master Mode Supports 7 and 10-bit Address.  
• I2C Port allows Bidirectional Transfers between  
Master and Slaves.  
• Serial Clock Synchronization for I2C Port can be  
used as a Handshake Mechanism to Suspend  
and Resume Serial Transfer (SCLREL control).  
• I2C Supports Multi-master Operation; Detects Bus  
Collision and Arbitrates Accordingly.  
• Provides Support for Address Bit Masking.  
© 2009 Microchip Technology Inc.  
Preliminary  
DS61143F-page 83  
PIC32MX3XX/4XX  
2
FIGURE 18-1:  
I C™ BLOCK DIAGRAM (X = 1 OR 2)  
Internal  
Data Bus  
I2CxRCV  
Read  
Shift  
Clock  
SCLx  
SDAx  
I2CxRSR  
LSB  
Address Match  
Write  
Read  
Match Detect  
I2CxMSK  
Write  
Read  
I2CxADD  
Start and Stop  
Bit Detect  
Write  
Start and Stop  
Bit Generation  
I2CxSTAT  
I2CxCON  
Read  
Write  
Collision  
Detect  
Acknowledge  
Generation  
Read  
Clock  
Stretching  
Write  
Read  
I2CxTRN  
LSB  
Shift Clock  
Reload  
Control  
Write  
Read  
BRG Down Counter  
PBCLK  
I2CxBRG  
DS61143F-page 84  
Preliminary  
© 2009 Microchip Technology Inc.  
PIC32MX3XX/4XX  
The primary features of the UART module are:  
19.0 UNIVERSAL ASYNCHRONOUS  
RECEIVER TRANSMITTER  
(UART)  
• Full-duplex, 8-bit or 9-bit data transmission  
• Even, odd or no parity options (for 8-bit data)  
• One or two Stop bits  
Note:  
This data sheet summarizes the features of  
the PIC32MX3XX/4XX family of devices. It  
is not intended to be a comprehensive  
reference source. Refer to the “PIC32MX  
Family Reference Manual” Section 21.  
“Universal Asynchronous Receiver Trans-  
mitter (UART)” (DS61107) for a detailed  
description of this peripheral.  
• Hardware auto-baud feature  
• Hardware flow control option  
• Fully integrated Baud Rate Generator (BRG) with  
16-bit prescaler  
• Baud rates ranging from 76 bps to 20 Mbps at 80  
MHz  
• 4-level-deep First-In-First-Out (FIFO) Transmit  
Data Buffer  
The manual is available from the Microchip  
web site (www.Microchip.com/PIC32).  
• 4-level-deep FIFO Receive Data Buffer  
• Parity, framing and buffer overrun error detection  
The UART module is one of the serial I/O modules  
available in PIC32MX3XX/4XX family devices. The  
UART is a full-duplex, asynchronous communication  
channel that communicates with peripheral devices  
and personal computers through protocols such as RS-  
232, RS-485, LIN 1.2 and IrDA®. The module also sup-  
ports the hardware flow control option, with UxCTS and  
UxRTS pins, and also includes an IrDA encoder and  
decoder.  
• Support for interrupt only on address detect (9th  
bit = 1)  
• Separate transmit and receive interrupts  
• Loopback mode for diagnostic support  
• LIN 1.2 protocol support  
• IrDA encoder and decoder with 16x baud clock  
output for external IrDA encoder/decoder support  
Figure 19-1 shows a simplified block diagram of the  
UART.  
FIGURE 19-1:  
UART SIMPLIFIED BLOCK DIAGRAM  
Baud Rate Generator  
IrDA®  
BCLKx  
UxRTS  
UxCTS  
Hardware Flow Control  
UARTx Receiver  
UxRX  
UxTX  
UARTx Transmitter  
© 2009 Microchip Technology Inc.  
Preliminary  
DS61143F-page 85  
PIC32MX3XX/4XX  
FIGURE 19-2:  
TRANSMISSION (8-BIT OR 9-BIT DATA)  
Write to UxTXREG  
Character 1  
BCLK/16  
(Shift Clock)  
UxTX  
Start bit  
bit 0  
bit 1  
Character 1  
bit 7/8  
Stop bit  
UxTXIF Cleared by User  
UxTXIF  
Character 1 to  
Transmit Shift Register  
TRMT bit  
FIGURE 19-3:  
TWO CONSECUTIVE TRANSMISSIONS  
Write to UxTXREG  
Character 1 Character 2  
BCLK/16  
(Shift Clock)  
UxTX  
Start bit  
Start bit  
Character 2  
bit 0  
bit 1  
Character 1  
bit 7/8  
bit 0  
Stop bit  
UxTXIF  
(UTXISEL0 = 0)  
UxTXIF Cleared by User in Software  
UxTXIF  
(UTXISEL0 = 1)  
Character 1 to  
Transmit Shift Register  
Character 2 to  
Transmit Shift Register  
TRMT bit  
DS61143F-page 86  
Preliminary  
© 2009 Microchip Technology Inc.  
PIC32MX3XX/4XX  
FIGURE 19-4:  
UART RECEPTION  
Start  
bit  
Start  
bit 7 Stop bit bit 0  
bit  
UxRX  
bit 0 bit1  
Stop  
bit  
bit 7  
UxRXIF  
(RXISEL = 0x)  
Character 1  
to UxRXREG  
Character 2  
to UxRXREG  
RIDLE bit  
Note:  
This timing diagram shows 2 characters received on the UxRX input.  
FIGURE 19-5:  
UART RECEPTION WITH RECEIVE OVERRUN  
Character 1  
bit 0 bit 1  
Characters 2, 3, 4, 5  
Character 6  
Start  
Start  
bit  
Start  
bit 7/8 Stop bit bit 0  
bit  
UxRX  
bit  
Stop  
Stop  
bit  
bit 7/8  
bit 7/8  
bit  
Character 1, 2, 3, 4  
Stored in Receive  
FIFO  
Character 5  
Held in UxRSR  
OERR Cleared by User  
OERR bit  
RIDLE bit  
Note:  
This diagram shows 6 characters received without the user reading the input buffer. The 5th character  
received is held in the Receive Shift register. An overrun error occurs at the start of the 6th character.  
© 2009 Microchip Technology Inc.  
Preliminary  
DS61143F-page 87  
PIC32MX3XX/4XX  
NOTES:  
DS61143F-page 88  
Preliminary  
© 2009 Microchip Technology Inc.  
PIC32MX3XX/4XX  
Key features of the PMP module include:  
20.0 PARALLEL MASTER PORT  
(PMP)  
• 8-bit,16-bit interface  
• Up to 16 programmable address lines  
• Up to two Chip Select lines  
Note:  
This data sheet summarizes the features of  
the PIC32MX3XX/4XX family of devices. It  
is not intended to be a comprehensive  
reference source. Refer to the “PIC32MX  
Family Reference Manual” Section 13.  
“Parallel Master Port (PMP)” (DS61128)  
for a detailed description of this peripheral.  
The manual is available from the Microchip  
web site (www.Microchip.com/PIC32).  
• Programmable strobe options  
- Individual read and write strobes, or  
- Read/write strobe with enable strobe  
• Address auto-increment/auto-decrement  
• Programmable address/data multiplexing  
• Programmable polarity on control signals  
• Parallel Slave Port support  
The PMP is a parallel 8-bit/16-bit input/output module  
specifically designed to communicate with a wide  
variety of parallel devices, such as communications  
peripherals, LCDs, external memory devices, and  
microcontrollers. Because the interface to parallel  
peripherals varies significantly, the PMP module is  
highly configurable.  
- Legacy addressable  
- Address support  
- 4-byte deep auto-incrementing buffer  
• Programmable Wait states  
• Operate during CPU Sleep and Idle modes  
• Fast bit manipulation using CLR, SET and INV  
registers  
• Freeze option for in-circuit debugging  
Note:  
On 64-pin devices, data pins PMD<15:8>  
are not available.  
FIGURE 20-1:  
PMP MODULE PINOUT AND CONNECTIONS TO EXTERNAL DEVICES  
Address Bus  
Data Bus  
Control Lines  
PMA<0>  
PMALL  
PIC32MX3XX/4XX  
Parallel  
Master Port  
PMA<1>  
PMALH  
FLASH  
EEPROM  
SRAM  
Up to 16-bit Address  
PMA<13:2>  
PMA<14>  
PMCS1  
PMA<15>  
PMCS2  
PMRD  
PMRD/PMWR  
FIFO  
buffer  
PMWR  
PMENB  
Microcontroller  
LCD  
PMD<7:0>  
PMD<15:8>  
(1)  
16/8-bit Data (with or without multiplexed addressing)  
Note 1: On 64-pin devices, data pins PMD<15:8> are not available in 16-bit Master modes  
© 2009 Microchip Technology Inc.  
Preliminary  
DS61143F-page 89  
PIC32MX3XX/4XX  
NOTES:  
DS61143F-page 90  
Preliminary  
© 2009 Microchip Technology Inc.  
PIC32MX3XX/4XX  
Following are some of the key features of this module:  
21.0 REAL-TIME CLOCK AND  
CALENDAR (RTCC)  
• Time: Hours, Minutes and Seconds  
• 24-Hour Format (Military Time)  
• Visibility of One-Half-Second Period  
Note:  
This data sheet summarizes the features of  
the PIC32MX3XX/4XX family of devices. It  
is not intended to be a comprehensive  
reference source. Refer to the “PIC32MX  
Family Reference Manual” Section 29.  
“Real-Time Clock and Calendar (RTCC)”  
(DS61125) for a detailed description of this  
peripheral.  
• Provides Calendar: Weekday, Date, Month and  
Year  
• Alarm Intervals are configurable for Half of a  
Second, One Second, 10 Seconds, One Minute,  
10 Minutes, One Hour, One Day, One Week, One  
Month and One Year  
The manual is available from the Microchip  
web site (www.Microchip.com/PIC32).  
• Alarm Repeat with Decrementing Counter  
• Alarm with Indefinite Repeat: Chime  
• Year Range: 2000 to 2099  
The PIC32MX RTCC module is intended for applica-  
tions in which accurate time must be maintained for  
extended periods of time with minimal or no CPU inter-  
vention. Low-power optimization provides extended  
battery lifetime while keeping track of time.  
• Leap Year Correction  
• BCD Format for Smaller Firmware Overhead  
• Optimized for Long-Term Battery Operation  
• Fractional Second Synchronization  
• User Calibration of the Clock Crystal Frequency  
with Auto-Adjust  
• Calibration Range: ±0.66 Seconds Error per  
Month  
• Calibrates up to 260 ppm of Crystal Error  
• Requirements: External 32.768 kHz Clock Crystal  
• Alarm Pulse or Seconds Clock Output on RTCC  
pin  
FIGURE 21-1:  
RTCC BLOCK DIAGRAM  
32.768 kHz Input  
from Secondary  
Oscillator (SOSC)  
RTCC Prescalers  
0.5s  
YEAR, MTH, DAY  
RTCVAL  
WKDAY  
RTCC Timer  
Alarm  
HR, MIN, SEC  
Event  
Comparator  
MTH, DAY  
WKDAY  
Compare Registers  
with Masks  
ALRMVAL  
HR, MIN, SEC  
Repeat Counter  
RTCC Interrupt  
RTCC Interrupt Logic  
Alarm Pulse  
Seconds Pulse  
RTCC Pin  
RTCOE  
© 2009 Microchip Technology Inc.  
Preliminary  
DS61143F-page 91  
PIC32MX3XX/4XX  
NOTES:  
DS61143F-page 92  
Preliminary  
© 2009 Microchip Technology Inc.  
PIC32MX3XX/4XX  
A block diagram of the 10-bit ADC is shown in  
Figure 22-1. The 10-bit ADC has 16 analog input pins,  
designated AN0-AN15. In addition, there are two ana-  
log input pins for external voltage reference connec-  
tions. These voltage reference inputs may be shared  
with other analog input pins and may be common to  
other analog module references.  
22.0  
10-BIT ANALOG-TO-DIGITAL  
CONVERTER (ADC)  
Note:  
This data sheet summarizes the features of  
the PIC32MX3XX/4XX family of devices. It  
is not intended to be a comprehensive  
reference source. Refer to the “PIC32MX  
Family Reference Manual” Section 17.  
The analog inputs are connected through two multi-  
plexers (MUXs) to one SHA. The analog input MUXs  
can be switched between two sets of analog inputs  
between conversions. Unipolar differential conversions  
are possible on all channels, other than the pin used as  
the reference, using a reference input pin (see  
Figure 22-1).  
“10-bit  
Analog-to-Digital  
Converter  
(ADC)” (DS61104) for  
a
detailed  
description of this peripheral.  
The manual is available from the Microchip  
web site (www.Microchip.com/PIC32).  
The PIC32MX3XX/4XX 10-bit Analog-to-Digital (A/D)  
converter (or ADC) includes the following features:  
The Analog Input Scan mode sequentially converts  
user-specified channels. A control register specifies  
which analog input channels will be included in the  
scanning sequence.  
• Successive Approximation Register (SAR)  
conversion  
• Up to 1000 kilo samples per second (ksps)  
conversion speed  
The 10-bit ADC is connected to a 16-word result buffer.  
Each 10-bit result is converted to one of eight, 32-bit  
output formats when it is read from the result buffer.  
• Up to 16 analog input pins  
• External voltage reference input pins  
• One unipolar, differential Sample-and-Hold  
Amplifier (SHA)  
• Automatic Channel Scan mode  
• Selectable conversion trigger source  
• 16-word conversion result buffer  
• Selectable Buffer Fill modes  
• Eight conversion result format options  
• Operation during CPU Sleep and Idle modes  
FIGURE 22-1:  
ADC1 MODULE BLOCK DIAGRAM  
(1)  
(1)  
AVDD  
AVSS  
VREF+  
VREF-  
VCFG<2:0>  
AN0  
ADC1BUF0  
ADC1BUF1  
ADC1BUF2  
AN15  
S/H  
VREFH  
VREFL  
CHANNEL  
SCAN  
+
CH0SB<4:0>  
-
SAR ADC  
CH0SA<4:0>  
CSCNA  
AN1  
ADC1BUFE  
ADC1BUFF  
VREFL  
CH0NA CH0NB  
Alternate  
Input Selection  
Note 1: VREF+, VREF- inputs can be multiplexed with other analog inputs.  
© 2009 Microchip Technology Inc.  
Preliminary  
DS61143F-page 93  
PIC32MX3XX/4XX  
FIGURE 22-2:  
ADC CONVERSION CLOCK PERIOD BLOCK DIAGRAM  
ADRC  
ADC Internal  
RC Clock(1)  
0
1
TAD  
ADCS<7:0>  
8
ADC Conversion  
Clock Multiplier  
X2  
TPB  
1, 2, 3, 4, 5,..., 512  
Note 1: See the ADC electrical characteristics for the exact RC clock value.  
DS61143F-page 94  
Preliminary  
© 2009 Microchip Technology Inc.  
PIC32MX3XX/4XX  
Following are some of the key features of this module:  
23.0  
COMPARATOR  
• Selectable inputs available include:  
- Analog inputs multiplexed with I/O pins  
Note:  
This data sheet summarizes the features of  
the PIC32MX3XX/4XX family of devices. It  
is not intended to be a comprehensive  
reference source. Refer to the “PIC32MX  
Family Reference Manual” Section 19.  
- On-chip internal absolute voltage reference  
(IVREF)  
- Comparator voltage reference (CVREF)  
• Outputs can be inverted  
“Comparator”  
(DS61110) for a detailed  
description of this peripheral.  
The manual is available from the Microchip  
web site (www.Microchip.com/PIC32).  
• Selectable interrupt generation  
A block diagram of the comparator module is shown in  
Figure 23-1.  
The PIC32MX3XX/4XX Analog Comparator module  
contains one or more comparator(s) that can be config-  
ured in a variety of ways.  
FIGURE 23-1:  
COMPARATOR BLOCK DIAGRAM  
Comparator 1  
COUT (CM1CON)  
C1OUT (CMSTAT)  
CREF  
ON  
CPOL  
C1IN+(2)  
(3)  
CVREF  
C1OUT  
CCH<1:0>  
C1  
C1IN-  
C1IN+  
C2IN+  
COE  
(3)  
IVREF  
Comparator 2  
ON  
COUT (CM2CON)  
C2OUT (CMSTAT)  
CREF  
CPOL  
C2IN+  
(3)  
CVREF  
C2OUT  
CCH<1:0>  
C2  
C2IN-  
COE  
C2IN+  
C1IN+  
(3)  
IVREF  
Note 1: IVref is the internal 1.2V reference.  
2: On USB variants, when USB is enabled, this pin is controlled by the USB module and therefore is not  
available as a comparator input.  
3: Internally connected.  
© 2009 Microchip Technology Inc.  
Preliminary  
DS61143F-page 95  
PIC32MX3XX/4XX  
NOTES:  
DS61143F-page 96  
Preliminary  
© 2009 Microchip Technology Inc.  
PIC32MX3XX/4XX  
A block diagram of the module is shown in Figure 24-1.  
The resistor ladder is segmented to provide two ranges  
of voltage reference values and has a power-down func-  
tion to conserve power when the reference is not being  
used. The module’s supply reference can be provided  
from either device VDD/VSS or an external voltage refer-  
ence. The CVREF output is available for the comparators  
and typically available for pin output.  
24.0 COMPARATOR VOLTAGE  
REFERENCE (CVREF)  
Note:  
This data sheet summarizes the features of  
the PIC32MX3XX/4XX family of devices. It  
is not intended to be a comprehensive  
reference source. Refer to the “PIC32MX  
Family Reference Manual” Section 20.  
“Comparator  
(CVREF)”  
Voltage  
(DS61109) for a detailed  
Reference  
The comparator voltage reference has the following  
features:  
description of this peripheral.  
The manual is available from the Microchip  
web site (www.Microchip.com/PIC32).  
• High and low range selection  
• Sixteen output levels available for each range  
• Internally connected to comparators to conserve  
device pins  
The CVREF is a 16-tap, resistor ladder network that pro-  
vides a selectable reference voltage. Although its pri-  
mary purpose is to provide a reference for the analog  
comparators, it also may be used independently of  
them.  
• Output can be connected to a pin  
FIGURE 24-1:  
COMPARATOR VOLTAGE REFERENCE BLOCK DIAGRAM  
CVRSS = 1  
CVRSS = 0  
VREF+  
AVDD  
8R  
CVR3:CVR0  
R
CVREN  
CVREF  
R
R
R
16 Steps  
CVREF  
OUT  
CVRCON<CVROE-  
R
R
R
CVRR  
VREF-  
AVSS  
8R  
CVRSS = 1  
CVRSS = 0  
© 2009 Microchip Technology Inc.  
Preliminary  
DS61143F-page 97  
PIC32MX3XX/4XX  
NOTES:  
DS61143F-page 98  
Preliminary  
© 2009 Microchip Technology Inc.  
PIC32MX3XX/4XX  
• Sleep Mode: the CPU, the system clock source,  
and any peripherals that operate from the system  
clock source, are halted.  
25.0 POWER-SAVING FEATURES  
Note:  
This data sheet summarizes the features of  
the PIC32MX3XX/4XX family of devices. It  
is not intended to be a comprehensive  
reference source. Refer to the “PIC32MX  
Family Reference Manual” Section 10.  
Some peripherals can operate in Sleep using spe-  
cific clock sources. This is the lowest power mode  
for the device.  
“Power-Saving Features”  
(DS61130)  
25.3 Power-Saving Operation  
for a detailed description of this peripheral.  
The manual is available from the Microchip  
web site (www.Microchip.com/PIC32).  
The purpose of all power saving is to reduce power  
consumption by reducing the device clock frequency.  
To achieve this, low-frequency clock sources can be  
selected. In addition, the peripherals and CPU can be  
halted or disabled to further reduce power consump-  
tion.  
This section describes power saving for the  
PIC32MX3XX/4XX. The PIC32MX devices offer a total  
of nine methods and modes that are organized into two  
categories that allow the user to balance power con-  
sumption with device performance. In all of the meth-  
ods and modes described in this section, power saving  
is controlled by software.  
25.3.1  
SLEEP MODE  
Sleep mode has the lowest power consumption of the  
device Power-Saving operating modes. The CPU and  
most peripherals are halted. Select peripherals can  
continue to operate in Sleep mode and can be used to  
wake the device from Sleep. See individual peripheral  
module sections for descriptions of behavior in Sleep.  
25.1 Power Saving with CPU Running  
When the CPU is running, power consumption can be  
controlled by reducing the CPU clock frequency, lower-  
ing the PBCLK, and by individually disabling modules.  
These methods are grouped into the following modes:  
Sleep mode includes the following characteristics:  
• The CPU is halted.  
• FRC Run mode: the CPU is clocked from the FRC  
clock source with or without postscalers.  
• The system clock source is typically shut down.  
See Section 25.4 “Peripheral Bus Scaling  
Method” for specific information.  
• LPRC Run mode: the CPU is clocked from the  
LPRC clock source.  
• There can be a wake-up delay based on the  
oscillator selection.  
• SOSC Run mode: the CPU is clocked from the  
SOSC clock source.  
• The Fail-Safe Clock Monitor (FSCM) does not  
operate during Sleep mode.  
• Peripheral Bus Scaling mode: peripherals are  
clocked at programmable fraction of the CPU  
clock (SYSCLK).  
• The BOR circuit, if enabled, remains operative  
during Sleep mode.  
• The WDT, if enabled, is not automatically cleared  
prior to entering Sleep mode.  
25.2 CPU Halted Methods  
• Some peripherals can continue to operate in  
Sleep mode. These peripherals include I/O pins  
that detect a change in the input signal, WDT,  
ADC, UART, and peripherals that use an external  
clock input or the internal LPRC oscillator, e.g.,  
RTCC and Timer 1.  
The device supports two power-saving modes, Sleep  
and Idle, both of which halt the clock to the CPU. These  
modes operate with all clock sources, as listed below:  
• POSC Idle Mode: the system clock is derived  
from the POSC. The system clock source  
continues to operate.  
• I/O pins continue to sink or source current in the  
same manner as they do when the device is not in  
Sleep.  
Peripherals continue to operate, but can  
optionally be individually disabled.  
• FRC Idle Mode: the system clock is derived from  
the FRC with or without postscalers. Peripherals  
continue to operate, but can optionally be  
individually disabled.  
• The USB module can override the disabling of the  
POSC or FRC. Refer to the USB section for spe-  
cific details.  
• Some modules can be individually disabled by  
software prior to entering Sleep in order to further  
reduce consumption.  
• SOSC Idle Mode: the system clock is derived  
from the SOSC. Peripherals continue to operate,  
but can optionally be individually disabled.  
• LPRC Idle Mode: the system clock is derived from  
the LPRC.  
Peripherals continue to operate, but can option-  
ally be individually disabled. This is the lowest  
power mode for the device with a clock running.  
© 2009 Microchip Technology Inc.  
Preliminary  
DS61143F-page 99  
PIC32MX3XX/4XX  
The processor will exit, or ‘wake-up’, from Sleep on one  
of the following events:  
25.5 Idle Mode  
In the Idle mode, the CPU is halted but the System  
clock (SYSCLK) source is still enabled. This allows  
peripherals to continue operation when the CPU is  
halted. Peripherals can be individually configured to  
halt when entering Idle by setting their respective SIDL  
bit. Latency when exiting Idle mode is very low due to  
the CPU oscillator source remaining active.  
• On any interrupt from an enabled source that is  
operating in Sleep. The interrupt priority must be  
greater than the current CPU priority.  
• On any form of device Reset.  
• On a WDT time-out. See Section 26.2 “Watch-  
dog Timer (WDT)”.  
If the interrupt priority is lower than or equal to current  
priority, the CPU will remain halted, but the PBCLK will  
start running and the device will enter into Idle mode.  
Notes: Changing the PBCLK divider ratio  
requires recalculation of peripheral timing.  
For example, assume the UART is config-  
ured for 9600 baud with a PB clock ratio of  
1:1 and a POSC of 8 MHz. When the PB  
clock divisor of 1:2 is used, the input fre-  
quency to the baud clock is cut in half;  
therefore, the baud rate is reduced to 1/2  
its former value. Due to numeric truncation  
in calculations (such as the baud rate divi-  
sor), the actual baud rate may be a tiny  
percentage different than expected. For  
this reason, any timing calculation  
required for a peripheral should be per-  
formed with the new PB clock frequency  
instead of scaling the previous value  
based on a change in PB divisor ratio.  
Note: There is no FRZ mode for this module.  
25.4 Peripheral Bus Scaling Method  
Most of the peripherals on the device are clocked using  
the PBCLK. The peripheral bus can be scaled relative  
to the SYSCLK to minimize the dynamic power con-  
sumed by the peripherals. The PBCLK divisor is con-  
trolled by PBDIV<1:0> (OSCCON<20:19>), allowing  
SYSCLK-to-PBCLK ratios of 1:1, 1:2, 1:4, and 1:8. All  
peripherals using PBCLK are affected when the divisor  
is changed. Peripherals such as the Interrupt Control-  
ler, DMA, Bus Matrix, and Prefetch Cache are clocked  
directly from SYSCLK, as a result, they are not affected  
by PBCLK divisor changes.  
Oscillator start-up and PLL lock delays  
are applied when switching to a clock  
source that was disabled and that uses a  
crystal and/or the PLL. For example,  
assume the clock source is switched from  
POSC to LPRC just prior to entering  
Sleep in order to save power. No oscilla-  
tor start-up delay would be applied when  
exiting Idle. However, when switching  
back to POSC, the appropriate PLL and  
or oscillator startup/lock delays would be  
applied.  
Most of the peripherals on the device are clocked using  
the PBCLK. The peripheral bus can be scaled relative  
to the SYSCLK to minimize the dynamic power con-  
sumed by the peripherals. The PBCLK divisor is con-  
trolled by PBDIV<1:0> (OSCCON<20:19>), allowing  
SYSCLK-to-PBCLK ratios of 1:1, 1:2, 1:4, and 1:8. All  
peripherals using PBCLK are affected when the divisor  
is changed. Peripherals such as USB, Interrupt Con-  
troller, DMA, Bus Matrix, and Prefetch Cache are  
clocked directly from SYSCLK, as a result, they are not  
affected by PBCLK divisor changes  
Changing the PBCLK divisor affects:  
The device enters Idle mode when the SLPEN  
(OSCCON<4>) bit is clear and a WAIT instruction is  
executed.  
• The CPU to peripheral access latency. The CPU  
has to wait for next PBCLK edge for a read to  
complete. In 1:8 mode this results in a latency of  
one to seven SYSCLKs.  
The processor will wake or exit from Idle mode on the  
following events:  
• The power consumption of the peripherals. Power  
consumption is directly proportional to the fre-  
quency at which the peripherals are clocked. The  
greater the divisor, the lower the power consumed  
by the peripherals.  
• On any interrupt event for which the interrupt  
source is enabled. The priority of the interrupt  
event must be greater than the current priority of  
CPU. If the priority of the interrupt event is lower  
than or equal to current priority of CPU, the CPU  
will remain halted and the device will remain in  
Idle mode.  
To minimize dynamic power the PB divisor should be  
chosen to run the peripherals at the lowest frequency  
that provides acceptable system performance. When  
selecting a PBCLK divider, peripheral clock require-  
ments such as baud rate accuracy should be taken into  
account. For example, the UART peripheral may not be  
able to achieve all baud rate values at some PBCLK  
divider depending on the SYSCLK value.  
• On any source of device Reset.  
• On a WDT time-out interrupt. See Section 26.2  
“Watchdog Timer (WDT)”.  
DS61143F-page 100  
Preliminary  
© 2009 Microchip Technology Inc.  
PIC32MX3XX/4XX  
26.1 Configuration Bits  
26.0 SPECIAL FEATURES  
The Configuration bits can be programmed to select  
various device configurations.  
Note:  
This data sheet summarizes the features of  
the PIC32MX3XX/4XX family of devices. It  
is not intended to be a comprehensive  
reference source. Refer to the “PIC32MX  
Family Reference Manual” (DS61132) for  
detailed descriptions of these features.  
The manual is available from the Microchip  
web site (www.Microchip.com/PIC32).  
PIC32MX3XX/4XX devices include several features  
intended to maximize application flexibility and reliabil-  
ity, and minimize cost through elimination of external  
components. These are:  
• Flexible Device Configuration  
• Watchdog Timer  
• JTAG Interface  
• In-Circuit Serial Programming (ICSP)  
REGISTER 26-1: DEVCFG0: DEVICE CONFIGURATION WORD 0  
r-0  
—
r-1  
—
r-1  
—
R/P-1  
CP  
r-1  
—
r-1  
—
r-1  
—
R/P-1  
BWP  
bit 31  
bit 24  
R/P-1  
bit 16  
r-1  
—
r-1  
—
r-1  
—
r-1  
—
R/P-1  
R/P-1  
R/P-1  
PWP<7:4>  
bit 23  
R/P-1  
bit 15  
R/P-1  
R/P-1  
R/P-1  
r-1  
—
r-1  
—
r-1  
—
r-1  
—
PWP<3:0>  
bit 8  
r-1  
—
r-1  
—
r-1  
—
r-1  
—
R/P-1  
r-1  
—
R/P-1  
R/P-1  
ICESEL  
DEBUG<1:0>  
bit 7  
bit 0  
Legend:  
R = Readable bit  
W = Writable bit  
P = Programmable bit  
r = Reserved bit  
U = Unimplemented bit  
-n = Bit Value at POR: (‘0’, ‘1’, x = Unknown)  
bit 31  
Reserved: Write ‘0’  
Reserved: Write ‘1’  
CP: Code-Protect bit  
bit 30-29  
bit 28  
Prevents boot and program Flash memory from being read or modified by an external  
programming device.  
1= Protection disabled  
0= Protection enabled  
bit 27-25  
Reserved: Write ‘1’  
© 2009 Microchip Technology Inc.  
Preliminary  
DS61143F-page 101  
PIC32MX3XX/4XX  
REGISTER 26-1: DEVCFG0: DEVICE CONFIGURATION WORD 0 (CONTINUED)  
bit 24  
BWP: Boot Flash Write-Protect bit  
Prevents boot Flash memory from being modified during code execution.  
1= Boot Flash is writable  
0= Boot Flash is not writable  
bit 23-20  
bit 19-12  
Reserved: Write ‘1’  
PWP<7:0>: Program Flash Write-Protect bits  
Prevents selected program Flash memory pages from being modified during code execution.  
The PWP bits represent the one’s compliment of the number of write protected program Flash memory  
pages.  
11111111= Disabled  
11111110= 0xBD00_0FFF  
11111101= 0xBD00_1FFF  
11111100= 0xBD00_2FFF  
11111011= 0xBD00_3FFF  
11111010= 0xBD00_4FFF  
11111001= 0xBD00_5FFF  
11111000= 0xBD00_6FFF  
11110111= 0xBD00_7FFF  
11110110= 0xBD00_8FFF  
11110101= 0xBD00_9FFF  
11110100= 0xBD00_AFFF  
11110011= 0xBD00_BFFF  
11110010= 0xBD00_CFFF  
11110001= 0xBD00_DFFF  
11110000= 0xBD00_EFFF  
11101111= 0xBD00_FFFF  
...  
01111111= 0xBD07_FFFF  
bit 11-4  
bit 3  
Reserved: Write ‘1’  
ICESEL: In-Circuit Emulator/Debugger Communication Channel Select bit  
1= PGEC2/PGED2 pair is used  
0= PGEC1/PGED1 pair is used  
bit 2  
Reserved: Write ‘1’  
bit 1-0  
DEBUG<1:0>: Background Debugger Enable bits (forced to ‘11’ if code-protect is enabled)  
11= Debugger disabled  
10= Debugger enabled  
01= Reserved (same as ‘11’ setting)  
00= Reserved (same as ‘11’ setting)  
DS61143F-page 102  
Preliminary  
© 2009 Microchip Technology Inc.  
PIC32MX3XX/4XX  
REGISTER 26-2: DEVCFG1: DEVICE CONFIGURATION WORD 1  
r-1  
—
r-1  
—
r-1  
—
r-1  
—
r-1  
—
r-1  
—
r-1  
—
r-1  
—
bit 31  
bit 24  
R/P-1  
bit 16  
R/P-1  
R/P-1  
r-1  
—
r-1  
—
R/P-1  
R/P-1  
R/P-1  
R/P-1  
R/P-1  
R/P-1  
FWDTEN  
WDTPS<4:0>  
bit 23  
R/P-1  
R/P-1  
R/P-1  
r-1  
—
R/P-1  
FCKSM<1:0>  
FPBDIV<1:0>  
OSCIOFNC  
POSCMD<1:0>  
bit 15  
bit 8  
R/P-1  
bit 0  
R/P-1  
IESO  
r-1  
—
R/P-1  
r-1  
—
r-1  
—
R/P-1  
R/P-1  
FSOSCEN  
FNOSC<2:0>  
bit 7  
Legend:  
R = Readable bit  
W = Writable bit  
P = Programmable bit  
r = Reserved bit  
U = Unimplemented bit  
-n = Bit Value at POR: (‘0’, ‘1’, x = Unknown)  
bit 31-24  
bit 23  
Reserved: Write ‘1’  
FWDTEN: Watchdog Timer Enable bit  
1= The WDT is enabled and cannot be disabled by software  
0= The WDT is not enabled; it can be enabled in software  
bit 22-21  
bit 20-16  
Reserved: Write ‘1’  
WDTPS<4:0>: Watchdog Timer Postscale Select bits  
10100= 1:1048576  
10011= 1:524288  
10010= 1:262144  
10001= 1:131072  
10000= 1:65536  
01111= 1:32768  
01110= 1:16384  
01101= 1:8192  
01100= 1:4096  
01011= 1:2048  
01010= 1:1024  
01001= 1:512  
01000= 1:256  
00111= 1:128  
00110= 1:64  
00101= 1:32  
00100= 1:16  
00011= 1:8  
00010= 1:4  
00001= 1:2  
00000= 1:1  
All other combinations not shown result in operation = ‘10100’  
© 2009 Microchip Technology Inc.  
Preliminary  
DS61143F-page 103  
PIC32MX3XX/4XX  
REGISTER 26-2: DEVCFG1: DEVICE CONFIGURATION WORD 1 (CONTINUED)  
bit 15-14  
FCKSM<1:0>: Clock Switching and Monitor Selection Configuration bits  
1x= Clock switching is disabled, Fail-Safe Clock Monitor is disabled  
01= Clock switching is enabled, Fail-Safe Clock Monitor is disabled  
00= Clock switching is enabled, Fail-Safe Clock Monitor is enabled  
bit 13-12  
FPBDIV<1:0>: Peripheral Bus Clock Divisor Default Value bits  
11= PBCLK is SYSCLK divided by 8  
10= PBCLK is SYSCLK divided by 4  
01= PBCLK is SYSCLK divided by 2  
00= PBCLK is SYSCLK divided by 1  
bit 11  
bit 10  
Reserved: Write ‘1’  
OSCIOFNC: CLKO Enable Configuration bit  
1= CLKO output signal active on the OSCO pin; primary oscillator must be disabled or configured for  
the External Clock mode (EC) for the CLKO to be active (POSCMD<1:0> = 11OR 00)  
0= CLKO output disabled  
bit 9-8  
bit 7  
POSCMD<1:0>: Primary Oscillator Configuration bits  
11= Primary oscillator disabled  
10= HS oscillator mode selected  
01= XT oscillator mode selected  
00= External clock mode selected  
IESO: Internal External Switchover bit  
1= Internal External Switchover mode enabled (Two-Speed Start-up enabled)  
0= Internal External Switchover mode disabled (Two-Speed Start-up disabled)  
bit 6  
bit 5  
Reserved: Write ‘1’  
FSOSCEN: Secondary Oscillator Enable bit  
1= Enable Secondary Oscillator  
0= Disable Secondary Oscillator  
bit 4-3  
bit 2-0  
Reserved: Write ‘1’  
FNOSC<2:0>: Oscillator Selection bits  
000= Fast RC Oscillator (FRC)  
001= Fast RC Oscillator with divide-by-N with PLL module (FRCDIV+PLL)  
010= Primary Oscillator (XT, HS, EC)(1)  
011= Primary Oscillator with PLL module (XT+PLL, HS+PLL, EC+PLL)  
100= Secondary Oscillator (SOSC)  
101= Low-Power RC Oscillator (LPRC)  
110= FRCDIV16 Fast RC Oscillator with fixed divide-by-16 postscaler  
111= Fast RC Oscillator with divide-by-N (FRCDIV)  
Note 1: Do not disable POSC (POSCMD = 00) when using this oscillator source.  
DS61143F-page 104  
Preliminary  
© 2009 Microchip Technology Inc.  
PIC32MX3XX/4XX  
REGISTER 26-3: DEVCFG2: DEVICE CONFIGURATION WORD 2  
r-1  
—
r-1  
—
r-1  
—
r-1  
—
r-1  
—
r-1  
—
r-1  
—
r-1  
—
bit 31  
bit 23  
bit 24  
R/P-1  
bit 16  
R/P-1  
bit 8  
R/P-1  
bit 0  
r-1  
—
r-1  
—
r-1  
—
r-1  
—
r-1  
—
R/P-1  
R/P-1  
R/P-1  
R/P-1  
FPLLODIV<2:0>  
R/P-1  
r-1  
—
r-1  
—
r-1  
—
r-1  
—
R/P-1  
FUPLLEN  
FUPLLIDIV<2:0>  
bit 15  
r-1  
—
R/P-1  
R/P-1  
R/P-1  
r-1  
—
R/P-1  
FPLLMULT<2:0>  
FPLLIDIV<2:0>  
bit 7  
Legend:  
R = Readable bit  
W = Writable bit  
P = Programmable bit  
r = Reserved bit  
U = Unimplemented bit  
-n = Bit Value at POR: (‘0’, ‘1’, x = Unknown)  
bit 31-19  
bit 18-16  
Reserved: Write ‘1’  
FPLLODIV[2:0]: Default Postscaler for PLL bits  
111= PLL output divided by 256  
110= PLL output divided by 64  
101= PLL output divided by 32  
100= PLL output divided by 16  
011= PLL output divided by 8  
010= PLL output divided by 4  
001= PLL output divided by 2  
000= PLL output divided by 1  
bit 15  
FUPLLEN: USB PLL Enable bit  
1= Enable USB PLL  
0= Disable and bypass USB PLL  
bit 14-11  
bit 10-8  
Reserved: Write ‘1’  
FUPLLIDIV[2:0]: PLL Input Divider bits  
111= 12x divider  
110= 10x divider  
101= 6x divider  
100= 5x divider  
011= 4x divider  
010= 3x divider  
010= 3x divider  
001= 2x divider  
000= 1x divider  
bit 7  
Reserved: Write ‘1’  
© 2009 Microchip Technology Inc.  
Preliminary  
DS61143F-page 105  
PIC32MX3XX/4XX  
REGISTER 26-3: DEVCFG2: DEVICE CONFIGURATION WORD 2 (CONTINUED)  
bit 6-4  
FPLLMULT[2:0]: PLL Multiplier bits  
111= 24x multiplier  
110= 21x multiplier  
101= 20x multiplier  
100= 19x multiplier  
011= 18x multiplier  
010= 17x multiplier  
001= 16x multiplier  
000= 15x multiplier  
bit 3  
Reserved: Write ‘1’  
bit 2-0  
FPLLIDIV[2:0]: PLL Input Divider bits  
111= 12x divider  
110= 10x divider  
101= 6x divider  
100= 5x divider  
011= 4x divider  
010= 3x divider  
001= 2x divider  
000= 1x divider  
REGISTER 26-4: DEVCFG3: DEVICE CONFIGURATION WORD 3  
r-1  
—
r-1  
—
r-1  
—
r-1  
—
r-1  
—
r-1  
—
r-1  
—
r-1  
—
bit 31  
bit 24  
r-1  
—
r-1  
—
r-1  
—
r-1  
—
r-1  
—
r-1  
—
r-1  
—
r-1  
—
bit 23  
bit 16  
R/P-x  
bit 8  
R/P-x  
bit 0  
R/P-x  
bit 15  
R/P-x  
R/P-x  
R/P-x  
R/P-x  
R/P-x  
R/P-x  
R/P-x  
R/P-x  
R/P-x  
R/P-x  
R/P-x  
USERID<15:8>  
R/P-x  
R/P-x  
USERID<7:0>  
bit 7  
Legend:  
R = Readable bit  
W = Writable bit  
P = Programmable bit  
r = Reserved bit  
U = Unimplemented bit  
-n = Bit Value at POR: (‘0’, ‘1’, x = Unknown)  
bit 31-16  
bit 15-0  
Reserved: Write ‘1’  
USERID<15:0>: This is a 16-bit value that is user defined and is readable via ICSP™ and JTAG  
DS61143F-page 106  
Preliminary  
© 2009 Microchip Technology Inc.  
PIC32MX3XX/4XX  
REGISTER 26-5: DEVID: DEVICE AND REVISION ID REGISTER  
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
VER<3:0>  
DEVID<27:24>  
bit 31  
bit 23  
bit 15  
bit 7  
bit 24  
bit 16  
bit 8  
R
R
R
R
R
DEVID<23:16>  
R
R
DEVID<15:8>  
R
R
DEVID<7:0>  
bit 0  
Legend:  
R = Readable bit  
W = Writable bit  
P = Programmable bit  
r = Reserved bit  
U = Unimplemented bit  
-n = Bit Value at POR: (‘0’, ‘1’, x = Unknown)  
bit 31-28  
bit 27-0  
VER<3:0>: Revision Identifier bits(1)  
DEVID<27:0>: Device ID(1)  
Note: See the PIC32MX Programming Specification for a list of Revision and Device ID values.  
© 2009 Microchip Technology Inc.  
Preliminary  
DS61143F-page 107  
PIC32MX3XX/4XX  
The following are some of the key features of the WDT  
module:  
26.2 Watchdog Timer (WDT)  
This section describes the operation of the WDT and  
Power-Up Timer of the PIC32MX3XX/4XX.  
• Configuration or software controlled  
• User-configurable time-out period  
• Can wake the device from Sleep or Idle  
The WDT, when enabled, operates from the internal  
Low-Power Oscillator (LPRC) clock source and can be  
used to detect system software malfunctions by reset-  
ting the device if the WDT is not cleared periodically in  
software. Various WDT time-out periods can be  
selected using the WDT postscaler. The WDT can also  
be used to wake the device from Sleep or Idle mode.  
FIGURE 26-1:  
WATCHDOG AND POWER-UP TIMER BLOCK DIAGRAM  
PWRT Enable  
WDT Enable  
LPRC  
Control  
PWRT Enable  
1:64 Output  
PWRT  
LPRC  
Oscillator  
1
Clock  
25-bit Counter  
25  
WDTCLR = 1  
WDT Enable  
Wake  
Device Reset  
0
1
WDT Counter Reset  
NMI (Wake-up)  
Power Save  
Decoder  
FWDTPS<4:0>(DEVCFG1<20:16>)  
Tying the ENVREG pin to VSS disables the regulator. In  
this case, separate power for the core logic at a nomi-  
nal 1.8V must be supplied to the device on the  
VDDCORE/VCAP pin.  
26.3 On-Chip Voltage Regulator  
All PIC32MX3XX/4XX device’s core and digital logic  
are designed to operate at a nominal 1.8V. To simplify  
system  
designs,  
most  
devices  
in  
the  
Alternately, the VDDCORE/VCAP and VDD pins can be  
tied together to operate at a lower nominal voltage.  
Refer to Figure 26-2 for possible configurations.  
PIC32MX3XX/4XX incorporate an on-chip regulator  
providing the required core logic voltage from VDD.  
The internal 1.8V regulator is controlled by the  
ENVREG pin. Tying this pin to VDD enables the regu-  
lator, which in turn provides power to the core. A low  
ESR capacitor (such as tantalum) must be connected  
to the VDDCORE/VCAP pin (Figure 26-2). This helps to  
maintain the stability of the regulator. The recom-  
mended value for the filer capacitor is provided in  
Section 28.1 “DC Characteristics”.  
26.3.1  
ON-CHIP REGULATOR AND POR  
When the voltage regulator is enabled, it takes fixed  
delay for it to generate output. During this time, desig-  
nated as TPU, code execution is disabled. TPU is applied  
every time the device resumes operation after any  
power-down, including Sleep mode.  
If the regulator is disabled, a separate Power-Up Timer  
(PWRT) is automatically enabled. The PWRT adds a  
fixed delay of TPWRT at device start-up. See  
Section 28.0 “Electrical Characteristics” for more  
information on TPU AND TPWRT.  
Note:  
It is important that the low ESR capacitor  
is placed as close as possible to the  
VDDCORE/VCAP pin.  
DS61143F-page 108  
Preliminary  
© 2009 Microchip Technology Inc.  
PIC32MX3XX/4XX  
26.3.2  
When  
ON-CHIP REGULATOR AND BOR  
the on-chip regulator is enabled,  
26.3.3  
POWER-UP REQUIREMENTS  
The on-chip regulator is designed to meet the power-up  
requirements for the device. If the application does not  
use the regulator, then strict power-up conditions must  
be adhered to. While powering up, VDDCORE must  
never exceed VDD by 0.3 volts.  
PIC32MX3XX/4XX devices also have a simple brown-  
out capability. If the voltage supplied to the regulator is  
inadequate to maintain a regulated level, the regulator  
Reset circuitry will generate a Brown-out Reset. This  
event is captured by the BOR flag bit (RCON<1>). The  
brown-out voltage levels are specific in Section 28.1  
“DC Characteristics”.  
FIGURE 26-2:  
CONNECTIONS FOR THE ON-CHIP REGULATOR  
Regulator Enabled (ENVREG tied to VDD):  
Regulator Disabled (ENVREG tied to ground):  
3.3V  
1.8V(1)  
3.3V(1)  
PIC32MX  
PIC32MX  
VDD  
VDD  
ENVREG  
ENVREG  
VDDCORE/VCAP  
VSS  
VDDCORE/VCAP  
VSS  
CEFC  
(10 μF typ)  
Note 1: These are typical operating voltages. Refer to Section 28.1 “DC Characteristics” for the full operating ranges of VDD  
and VDDCORE.  
© 2009 Microchip Technology Inc.  
Preliminary  
DS61143F-page 109  
PIC32MX3XX/4XX  
26.4 Programming and Diagnostics  
PIC32MX3XX/4XX devices provide a complete range  
of programming and diagnostic features that can  
increase the flexibility of any application using them.  
These features allow system designers to include:  
• Simplified field programmability using two-wire In-  
Circuit Serial Programming™ (ICSP™) interfaces  
• Debugging using ICSP  
• Programming and debugging capabilities using  
the EJTAG extension of JTAG  
• JTAG boundary scan testing for device and board  
diagnostics  
PIC32MX devices incorporate two programming and  
diagnostic modules, and a trace controller, that provide  
a range of functions to the application developer.  
FIGURE 26-3:  
BLOCK DIAGRAM OF PROGRAMMING, DEBUGGING, AND TRACE PORTS  
PGEC1  
PGED1  
ICSP™  
Controller  
PGEC2  
PGED2  
ICESEL  
TDI  
TDO  
TCK  
TMS  
JTAG  
Controller  
Core  
JTAGEN  
DEBUG<1:0>  
TRCLK  
TRD0  
TRD1  
TRD2  
TRD3  
Instruction Trace  
Controller  
DEBUG<1:0>  
DS61143F-page 110  
Preliminary  
© 2009 Microchip Technology Inc.  
PIC32MX3XX/4XX  
REGISTER 26-6: DDPCON: DEBUG DATA PORT CONTROL REGISTER  
r-x  
—
r-x  
—
r-x  
—
r-x  
—
r-x  
—
r-x  
—
r-x  
—
r-x  
—
bit 31  
bit 24  
r-x  
—
r-x  
—
r-x  
—
r-x  
—
r-x  
—
r-x  
—
r-x  
—
r-x  
—
bit 23  
bit 16  
r-x  
—
r-x  
—
r-x  
—
r-x  
—
r-x  
—
r-x  
—
r-x  
—
r-x  
—
bit 15  
bit 8  
bit 0  
R/W-0  
DDPUSB  
bit 7  
R/W-0  
R/W-0  
R/W-0  
R/W-1  
R/W-0  
r-x  
—
r-x  
—
DDPU1  
DDPU2  
DDPSPI1  
JTAGEN  
TROEN  
Legend:  
R = Readable bit  
W = Writable bit  
P = Programmable bit  
r = Reserved bit  
U = Unimplemented bit  
-n = Bit Value at POR: (‘0’, ‘1’, x = Unknown)  
bit 31-8  
bit 7  
Reserved: Write ‘0’; ignore read  
DDPUSB: Debug Data Port Enable for USB bit  
1= USB peripheral ignores USBFRZ (U1CNFG1<5>) setting  
0= USB peripheral follows USBFRZ setting.  
bit 6  
bit 5  
bit 4  
bit 3  
bit 2  
bit 1-0  
DDPU1: Debug Data Port Enable for UART1 bit  
1= UART1 peripheral ignores FRZ (U1MODE<14>) setting  
0= UART1 peripheral follows FRZ setting  
DDPU2: Debug Data Port Enable for UART2 bit  
1= UART2 peripheral ignores FRZ (U2MODE<14) setting  
0= UART2 peripheral follows FRZ setting  
DDPSPI1: Debug Data Port Enable for SPI1 bit  
1= SPI1 peripheral ignores FRZ (SPI1CON<14>) setting  
0= SPI1 peripheral follows FRZ setting  
JTAGEN: JTAG Port Enable bit  
1= Enable JTAG Port  
0= Disable JTAG Port  
TROEN: Trace Output Enable bit  
1= Enable Trace Port  
0= Disable Trace Port  
Reserved: Write ‘1’; ignore read  
© 2009 Microchip Technology Inc.  
Preliminary  
DS61143F-page 111  
PIC32MX3XX/4XX  
NOTES:  
DS61143F-page 112  
Preliminary  
© 2009 Microchip Technology Inc.  
PIC32MX3XX/4XX  
Refer to “MIPS32® Architecture for Pro-  
grammers Volume II: The MIPS32®  
Instruction Set” at www.mips.com for more  
information.  
27.0 INSTRUCTION SET  
Note:  
The PIC32MX3XX/4XX family instruction set complies  
with the MIPS32 Release 2 instruction set architecture.  
PIC32MX does not support the following features:  
• CoreExtend instructions  
• Coprocessor 1 instructions  
• Coprocessor 2 instructions  
Table 27-1 provides a summary of the instructions that  
are implemented by the PIC32MX3XX/4XX family  
core.  
®
TABLE 27-1: MIPS32 INSTRUCTION SET  
Instruction  
ADD  
Description  
Function  
Integer Add  
Rd = Rs + Rt  
ADDI  
ADDIU  
ADDU  
AND  
Integer Add Immediate  
Unsigned Integer Add Immediate  
Unsigned Integer Add  
Logical AND  
Rt = Rs + Immed  
Rt = Rs +U Immed  
Rd = Rs +U Rt  
Rd = Rs & Rt  
ANDI  
B
Logical AND Immediate  
Rt = Rs & (016 || Immed)  
PC += (int)offset  
Unconditional Branch  
(Assembler idiom for: BEQ r0, r0, offset)  
BAL  
Branch and Link  
(Assembler idiom for: BGEZAL r0, offset)  
GPR[31] = PC + 8  
PC += (int)offset  
BEQ  
Branch On Equal  
if Rs == Rt  
PC += (int)offset  
BEQL  
Branch On Equal Likely(1)  
if Rs == Rt  
PC += (int)offset  
else  
Ignore Next Instruction  
BGEZ  
Branch on Greater Than or Equal To Zero  
if !Rs[31]  
PC += (int)offset  
BGEZAL  
Branch on Greater Than or Equal To Zero And Link  
GPR[31] = PC + 8  
if !Rs[31]  
PC += (int)offset  
BGEZALL  
BGEZL  
Branch on Greater Than or Equal To Zero And Link  
Likely(1)  
GPR[31] = PC + 8  
if !Rs[31]  
PC += (int)offset  
else  
Ignore Next Instruction  
Branch on Greater Than or Equal To Zero Likely(1)  
if !Rs[31]  
PC += (int)offset  
else  
Ignore Next Instruction  
BGTZ  
Branch on Greater Than Zero  
if !Rs[31] && Rs != 0  
PC += (int)offset  
BGTZL  
Branch on Greater Than Zero Likely(1)  
if !Rs[31] && Rs != 0  
PC += (int)offset  
else  
Ignore Next Instruction  
BLEZ  
Branch on Less Than or Equal to Zero  
if Rs[31] || Rs == 0  
PC += (int)offset  
Note 1: This instruction is deprecated and should not be used.  
© 2009 Microchip Technology Inc.  
Preliminary  
DS61143F-page 113  
PIC32MX3XX/4XX  
®
TABLE 27-1: MIPS32 INSTRUCTION SET (CONTINUED)  
Instruction  
BLEZL  
Description  
Function  
Branch on Less Than or Equal to Zero Likely(1)  
if Rs[31] || Rs == 0  
PC += (int)offset  
else  
Ignore Next Instruction  
BLTZ  
Branch on Less Than Zero  
if Rs[31]  
PC += (int)offset  
BLTZAL  
Branch on Less Than Zero And Link  
GPR[31] = PC + 8  
if Rs[31]  
PC += (int)offset  
BLTZALL  
BLTZL  
Branch on Less Than Zero And Link Likely(1)  
Branch on Less Than Zero Likely(1)  
GPR[31] = PC + 8  
if Rs[31]  
PC += (int)offset  
else  
Ignore Next Instruction  
if Rs[31]  
PC += (int)offset  
else  
Ignore Next Instruction  
BNE  
Branch on Not Equal  
if Rs != Rt  
PC += (int)offset  
BNEL  
Branch on Not Equal Likely(1)  
if Rs != Rt  
PC += (int)offset  
else  
Ignore Next Instruction  
BREAK  
CLO  
Breakpoint  
Break Exception  
Count Leading Ones  
Count Leading Zeroes  
Return from Debug Exception  
Rd = NumLeadingOnes(Rs)  
Rd = NumLeadingZeroes(Rs)  
CLZ  
DERET  
PC = DEPC  
Exit Debug Mode  
DI  
Atomically Disable Interrupts  
Divide  
Rt = Status; StatusIE = 0  
DIV  
LO = (int)Rs / (int)Rt  
HI = (int)Rs % (int)Rt  
DIVU  
EHB  
Unsigned Divide  
LO = (uns)Rs / (uns)Rt  
HI = (uns)Rs % (uns)Rt  
Execution Hazard Barrier  
Stop instruction execution  
until execution hazards are  
cleared  
EI  
Atomically Enable Interrupts  
Return from Exception  
Rt = Status; StatusIE = 1  
ERET  
if StatusERL  
PC = ErrorEPC  
else  
PC = EPC  
StatusEXL = 0  
StatusERL = 0  
LL = 0  
EXT  
INS  
J
Extract Bit Field  
Insert Bit Field  
Rt = ExtractField(Rs, pos,  
size)  
Rt = InsertField(Rs, Rt, pos,  
size)  
Unconditional Jump  
PC = PC[31:28] || offset<<2  
Note 1: This instruction is deprecated and should not be used.  
DS61143F-page 114  
Preliminary  
© 2009 Microchip Technology Inc.  
PIC32MX3XX/4XX  
®
TABLE 27-1: MIPS32 INSTRUCTION SET (CONTINUED)  
Instruction Description  
JAL  
Function  
Jump and Link  
GPR[31] = PC + 8  
PC = PC[31:28] || offset<<2  
JALR  
Jump and Link Register  
Rd = PC + 8  
PC = Rs  
JALR.HB  
Jump and Link Register with Hazard Barrier  
Like JALR, but also clears execution and  
instruction hazards  
JR  
Jump Register  
PC = Rs  
JR.HB  
Jump Register with Hazard Barrier  
Like JR, but also clears execution and  
instruction hazards  
LB  
Load Byte  
Rt = (byte)Mem[Rs+offset]  
Rt = (ubyte))Mem[Rs+offset]  
Rt = (half)Mem[Rs+offset]  
Rt = (uhalf)Mem[Rs+offset]  
LBU  
LH  
Unsigned Load Byte  
Load Halfword  
LHU  
LL  
Unsigned Load Halfword  
Load Linked Word  
Rt = Mem[Rs+offset>  
LLbit = 1  
LLAdr = Rs + offset  
LUI  
Load Upper Immediate  
Load Word  
Rt = immediate << 16  
Rt = Mem[Rs+offset]  
Rt = Mem[PC+offset]  
Re = Re MERGE Mem[Rs+offset]  
Re = Re MERGE Mem[Rs+offset]  
HI | LO += (int)Rs * (int)Rt  
HI | LO += (uns)Rs * (uns)Rt  
Rt = CPR[0, Rd, sel]  
Rd = HI  
LW  
LWPC  
LWL  
Load Word, PC relative  
Load Word Left  
LWR  
Load Word Right  
MADD  
MADDU  
MFC0  
MFHI  
MFLO  
MOVN  
Multiply-Add  
Multiply-Add Unsigned  
Move From Coprocessor 0  
Move From HI  
Move From LO  
Rd = LO  
Move Conditional on Not Zero  
if Rt ¼ 0 then  
Rd = Rs  
MOVZ  
Move Conditional on Zero  
if Rt = 0 then  
Rd = Rs  
MSUB  
MSUBU  
MTC0  
MTHI  
MTLO  
MUL  
Multiply-Subtract  
HI | LO -= (int)Rs * (int)Rt  
HI | LO -= (uns)Rs * (uns)Rt  
CPR[0, n, Sel] = Rt  
HI = Rs  
Multiply-Subtract Unsigned  
Move To Coprocessor 0  
Move To HI  
Move To LO  
LO = Rs  
Multiply with register write  
HI | LO =Unpredictable  
Rd = ((int)Rs * (int)Rt)31..0  
MULT  
MULTU  
NOP  
Integer Multiply  
HI | LO = (int)Rs * (int)Rd  
HI | LO = (uns)Rs * (uns)Rd  
Unsigned Multiply  
No Operation  
(Assembler idiom for: SLL r0, r0, r0)  
NOR  
OR  
Logical NOR  
Rd = ~(Rs | Rt)  
Rd = Rs | Rt  
Logical OR  
ORI  
RDHWR  
Logical OR Immediate  
Rt = Rs | Immed  
Re = HWR[Rd]  
Read Hardware Register (if enabled by HWREna  
Register)  
Note 1: This instruction is deprecated and should not be used.  
© 2009 Microchip Technology Inc.  
Preliminary  
DS61143F-page 115  
PIC32MX3XX/4XX  
®
TABLE 27-1: MIPS32 INSTRUCTION SET (CONTINUED)  
Instruction  
RDPGPR  
Description  
Function  
Read GPR from Previous Shadow Set  
Rotate Word Right  
Rt = SGPR[SRSCtlPSS, Rd]  
Rd = Rtsa-1..0 || Rt31..sa  
Rd = RtRs-1..0 || Rt31..Rs  
(byte)Mem[Rs+offset] = Rt  
ROTR  
ROTRV  
SB  
Rotate Word Right Variable  
Store Byte  
SC  
Store Conditional Word  
if LLbit = 1  
mem[Rs+offset> = Rt  
Rt = LLbit  
SDBBP  
SEB  
SEH  
SH  
Software Debug Break Point  
Sign-Extend Byte  
Sign-Extend Half  
Trap to SW Debug Handler  
Rd = SignExtend (Rs-7...0)  
Rd = SignExtend (Rs-15...0)  
(half)Mem[Rs+offset> = Rt  
Rd = Rt << sa  
Store Half  
SLL  
SLLV  
SLT  
Shift Left Logical  
Shift Left Logical Variable  
Set on Less Than  
Rd = Rt << Rs[4:0]  
if (int)Rs < (int)Rt  
Rd = 1  
else  
Rd = 0  
SLTI  
SLTIU  
SLTU  
Set on Less Than Immediate  
if (int)Rs < (int)Immed  
Rt = 1  
else  
Rt = 0  
Set on Less Than Immediate Unsigned  
Set on Less Than Unsigned  
if (uns)Rs < (uns)Immed  
Rt = 1  
else  
Rt = 0  
if (uns)Rs < (uns)Immed  
Rd = 1  
else  
Rd = 0  
SRA  
Shift Right Arithmetic  
Shift Right Arithmetic Variable  
Shift Right Logical  
Shift Right Logical Variable  
Superscalar Inhibit No Operation  
Integer Subtract  
Rd = (int)Rt >> sa  
Rd = (int)Rt >> Rs[4:0]  
Rd = (uns)Rt >> sa  
Rd = (uns)Rt >> Rs[4:0]  
NOP  
SRAV  
SRL  
SRLV  
SSNOP  
SUB  
Rt = (int)Rs - (int)Rd  
Rt = (uns)Rs - (uns)Rd  
Mem[Rs+offset] = Rt  
Mem[Rs+offset] = Rt  
Mem[Rs+offset] = Rt  
SUBU  
SW  
Unsigned Subtract  
Store Word  
SWL  
Store Word Left  
SWR  
Store Word Right  
SYNC  
Synchronize  
Orders the cached coherent and  
uncached loads and stores for access to  
the shared memory  
SYSCALL  
TEQ  
System Call  
Trap if Equal  
SystemCallException  
if Rs == Rt  
TrapException  
TEQI  
Trap if Equal Immediate  
if Rs == (int)Immed  
TrapException  
Note 1: This instruction is deprecated and should not be used.  
DS61143F-page 116  
Preliminary  
© 2009 Microchip Technology Inc.  
PIC32MX3XX/4XX  
®
TABLE 27-1: MIPS32 INSTRUCTION SET (CONTINUED)  
Instruction Description  
TGE Trap if Greater Than or Equal  
Function  
if (int)Rs >= (int)Rt  
TrapException  
TGEI  
TGEIU  
TGEU  
TLT  
Trap if Greater Than or Equal Immediate  
Trap if Greater Than or Equal Immediate Unsigned  
Trap if Greater Than or Equal Unsigned  
Trap if Less Than  
if (int)Rs >= (int)Immed  
TrapException  
if (uns)Rs >= (uns)Immed  
TrapException  
if (uns)Rs >= (uns)Rt  
TrapException  
if (int)Rs < (int)Rt  
TrapException  
TLTI  
TLTIU  
TLTU  
TNE  
Trap if Less Than Immediate  
Trap if Less Than Immediate Unsigned  
Trap if Less Than Unsigned  
if (int)Rs < (int)Immed  
TrapException  
if (uns)Rs < (uns)Immed  
TrapException  
if (uns)Rs < (uns)Rt  
TrapException  
Trap if Not Equal  
if Rs != Rt  
TrapException  
TNEI  
WAIT  
Trap if Not Equal Immediate  
Wait for Interrupt  
if Rs != (int)Immed  
TrapException  
Go to a low power mode and stall until  
interrupt occurs  
WRPGPR  
WSBH  
Write to GPR in Previous Shadow Set  
Word Swap Bytes Within Halfwords  
SGPR[SRSCtlPSS, Rd> = Rt  
Rd = Rt23..16 || Rt31..24 || Rt7..0  
|| Rt15..8  
XOR  
Exclusive OR  
Rd = Rs ^ Rt  
XORI  
Exclusive OR Immediate  
Rt = Rs ^ (uns)Immed  
Note 1: This instruction is deprecated and should not be used.  
© 2009 Microchip Technology Inc.  
Preliminary  
DS61143F-page 117  
PIC32MX3XX/4XX  
NOTES:  
DS61143F-page 118  
Preliminary  
© 2009 Microchip Technology Inc.  
PIC32MX3XX/4XX  
28.0 ELECTRICAL CHARACTERISTICS  
This section provides an overview of PIC32MX3XX/4XX electrical characteristics. Additional information will be provided  
in future revisions of this document as it becomes available.  
Absolute maximum ratings for the PIC32MX3XX/4XX are listed below. Exposure to these maximum rating conditions  
for extended periods may affect device reliability. Functional operation of the device at these or any other conditions  
above the parameters indicated in the operation listings of this specification is not implied.  
Absolute Maximum Ratings (Note 1)  
Ambient temperature under bias...............................................................................................................-40°C to +85°C  
Storage temperature .............................................................................................................................. -65°C to +150°C  
Voltage on VDD with respect to VSS ......................................................................................................... -0.3V to +4.0V  
Voltage on any combined analog and digital pin and MCLR, with respect to VSS ......................... -0.3V to (VDD + 0.3V)  
Voltage on any digital only pin with respect to VSS .................................................................................. -0.3V to +5.5V  
Voltage on VDDCORE with respect to VSS ................................................................................................... -0.3V to 2.0V  
Maximum current out of VSS pin(s).......................................................................................................................300 mA  
Maximum current into VDD pin(s) (Note 2)............................................................................................................300 mA  
Maximum output current sunk by any I/O pin..........................................................................................................25 mA  
Maximum output current sourced by any I/O pin ....................................................................................................25 mA  
Maximum current sunk by all ports .......................................................................................................................200 mA  
Maximum current sourced by all ports (Note 2)....................................................................................................200 mA  
Note 1: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the  
device. This is a stress rating only and functional operation of the device at those or any other conditions  
above those indicated in the operation listings of this specification is not implied. Exposure to maximum  
rating conditions for extended periods may affect device reliability.  
2: Maximum allowable current is a function of device maximum power dissipation (see Table 28-2).  
© 2009 Microchip Technology Inc.  
Preliminary  
DS61143F-page 119  
PIC32MX3XX/4XX  
28.1 DC Characteristics  
TABLE 28-1: OPERATING MIPS VS. VOLTAGE  
Max. Frequency  
PIC32MX3XX/4XX  
80 MHz (Note 1)  
VDD Range  
(in Volts)  
Temp. Range  
Characteristic  
(in °C)  
DC5  
2.3-3.6V  
-40°C to +85°C  
Note 1: 40 MHz maximum for PIC32MX 40MHz family variants.  
TABLE 28-2: THERMAL OPERATING CONDITIONS  
Rating  
Symbol  
Min.  
Typical  
Max.  
Unit  
PIC32MX3XX/4XX  
Operating Junction Temperature Range  
Operating Ambient Temperature Range  
TJ  
TA  
-40  
-40  
—
—
+125  
+85  
°C  
°C  
Power Dissipation:  
Internal Chip Power Dissipation:  
PINT = VDD x (IDD – S IOH)  
PD  
PINT + PI/O  
W
W
I/O Pin Power Dissipation:  
I/O = S ({VDD – VOH} x IOH) + S (VOL x IOL))  
Maximum Allowed Power Dissipation  
PDMAX  
(TJ – TA)/θJA  
TABLE 28-3: THERMAL PACKAGING CHARACTERISTICS  
Characteristics  
Symbol Typical  
Max.  
Unit  
Notes  
Package Thermal Resistance, 100-Pin TQFP (12x12x1 mm)  
Package Thermal Resistance, 64-Pin TQFP (10x10x1 mm)  
Package Thermal Resistance, 64-Pin QFN (9x9x0,9 mm)  
θJA  
θJA  
θJA  
43  
47  
28  
—
—
—
°C/W  
°C/W  
°C/W  
1
1
1
Note 1: Junction to ambient thermal resistance, Theta-JA (θJA) numbers are achieved by package simulations.  
TABLE 28-4: DC TEMPERATURE AND VOLTAGE SPECIFICATIONS  
Standard Operating Conditions: 2.3V to 3.6V  
DC CHARACTERISTICS  
(unless otherwise stated)  
Operating temperature -40°C ≤ TA ≤ +85°C for Industrial  
Param.  
Symbol  
No.  
Characteristics  
Min.  
Typical  
Max. Units  
Conditions  
Operating Voltage  
DC10 Supply Voltage  
VDD  
2.3  
—
—
3.6  
—
V
V
DC12  
VDR  
RAM Data Retention Voltage  
(Note 1)  
1.75  
DC16  
VPOR  
VDD Start Voltage  
to Ensure Internal  
Power-on Reset Signal  
1.75  
0.05  
—
—
1.95  
—
V
DC17  
SVDD  
VDD Rise Rate  
V/ms  
to Ensure Internal  
Power-on Reset Signal  
Note 1: This is the limit to which VDD can be lowered without losing RAM data.  
DS61143F-page 120  
Preliminary  
© 2009 Microchip Technology Inc.  
PIC32MX3XX/4XX  
TABLE 28-5: DC CHARACTERISTICS: OPERATING CURRENT (IDD)  
Standard Operating Conditions: 2.3V to 3.6V  
(unless otherwise stated)  
DC CHARACTERISTICS  
Operating temperature -40°C ≤ TA ≤ +85°C for Industrial  
Parameter  
Typical(3)  
No.  
Max.  
Units  
Conditions  
Operating Current (IDD)  
DC20  
8.5  
4.0  
23.5  
16.4  
48  
13  
—
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
µA  
µA  
µA  
µA  
µA  
µA  
µA  
µA  
µA  
µA  
—
4 MHz  
DC20c  
DC21  
Code executing from SRAM  
Code executing from SRAM  
Code executing from SRAM  
—
—
32  
20 MHz  
(Note 4)  
DC21c  
DC22  
—
—
61  
—
60 MHz  
(Note 4)  
DC22c  
DC23  
45  
—
—
55  
75  
2.3V  
—
80 MHz  
DC23c  
DC24  
55  
—
Code executing from SRAM  
—
100  
130  
670  
—
-40°C  
DC24a  
DC24b  
DC25  
—
+25°C  
2.3V  
3.3V  
3.6V  
—
+85°C  
94  
-40°C  
DC25a  
DC25b  
DC25c  
DC26  
125  
302  
71  
—
+25°C  
LPRC (31 kHz)  
(Note 4)  
—
+85°C  
—
Code executing from SRAM  
—
110  
180  
700  
-40°C  
+25°C  
+85°C  
DC26a  
DC26b  
—
—
Note 1: A device’s IDD supply current is mainly a function of the operating voltage and frequency. Other factors,  
such as PBCLK (Peripheral Bus Clock) frequency, number of peripheral modules enabled, internal code  
execution pattern, execution from Program Flash memory vs. SRAM, I/O pin loading and switching rate,  
oscillator type as well as temperature can have an impact on the current consumption.  
2: The test conditions for IDD measurements are as follows: Oscillator mode = EC+PLL with OSC1 driven by  
external square wave from rail to rail and PBCLK divisor = 1:8. CPU, Program Flash and SRAM data  
memory are operational, Program Flash memory Wait states = 7, program cache and prefetch are dis-  
abled and SRAM data memory Wait states = 1. All peripheral modules are disabled (ON bit = 0). WDT and  
FSCM are disabled. All I/O pins are configured as inputs and pulled to VSS. MCLR = VDD.  
3: Data in “Typical” column is at 3.3V, 25°C at specified operating frequency unless otherwise stated.  
Parameters are for design guidance only and are not tested.  
4: This parameter is characterized, but not tested in manufacturing.  
© 2009 Microchip Technology Inc.  
Preliminary  
DS61143F-page 121  
PIC32MX3XX/4XX  
TABLE 28-6: DC CHARACTERISTICS: IDLE CURRENT (IIDLE)  
Standard Operating Conditions: 2.3V to 3.6V  
(unless otherwise stated)  
Operating temperature -40°C ≤ TA ≤ +85°C for Industrial  
DC CHARACTERISTICS  
Parameter  
Typical(2)  
No.  
Max.  
Units  
Conditions  
Idle Current (IIDLE): Core OFF, Clock ON Base Current (Note 1)  
DC30  
—
1.4  
—
—
13  
—
—
20  
—
—
24  
—
—
—
—
35  
65  
242  
—
—
—
5
—
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
µA  
2.3V  
—
DC30a  
DC30b  
DC31  
4 MHz  
5
3.6V  
2.3V  
—
15  
—
20 MHz,  
(Note 3)  
DC31a  
DC31b  
DC32  
17  
22  
—
3.6V  
2.3V  
—
60 MHz  
(Note 3)  
DC32a  
DC32b  
DC33  
25  
29  
—
3.6V  
2.3V  
—
DC33a  
DC33b  
DC34  
80 MHz  
32  
36  
62  
392  
—
3.6V  
-40°C  
+25°C  
+85°C  
-40°C  
+25°C  
+85°C  
-40°C  
+25°C  
+85°C  
DC34a  
DC34b  
DC35  
µA  
2.3V  
3.3V  
3.6V  
µA  
µA  
LPRC (31 kHz)  
DC35a  
DC35b  
DC36  
—
µA  
(Note 3)  
—
µA  
43  
106  
414  
µA  
DC36a  
DC36b  
µA  
µA  
Note 1: The test conditions for base IDLE current measurements are as follows: System clock is enabled and  
PBCLK divisor = 1:8. CPU in Idle mode (CPU core halted). Only digital peripheral modules are enabled  
(ON bit = 1) and being clocked. WDT and FSCM are disabled. All I/O pins are configured as inputs and  
pulled to VSS. MCLR = VDD.  
2: Data in “Typical” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance  
only and are not tested.  
3: This parameter is characterized, but not tested in manufacturing.  
DS61143F-page 122  
Preliminary  
© 2009 Microchip Technology Inc.  
PIC32MX3XX/4XX  
TABLE 28-7: DC CHARACTERISTICS: POWER-DOWN CURRENT (IPD)  
Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated)  
Operating temperature -40°C ≤ TA ≤ +85°C for Industrial  
DC CHARACTERISTICS  
Parameter  
Typical(2)  
No.  
Max.  
Units  
Conditions  
Power-Down Current (IPD) (Note 1)  
DC40  
7
24  
205  
25  
9
30  
30  
μA  
μA  
μA  
μA  
μA  
μA  
μA  
-40°C  
+25°C  
+85°C  
+25°C  
-40°C  
+25°C  
+70°C  
DC40a  
DC40b  
DC40c  
DC40d  
DC40e  
DC40g  
2.3V  
3.3V  
Base Power-Down Current (Note 6)  
300  
—
Base Power-Down Current  
70  
25  
115  
70  
3.6V  
Base Power-Down Current  
200  
(Note 5)  
DC40f  
200  
400  
μA  
+85°C  
Module Differential Current  
DC41  
—
—
—
5
10  
10  
10  
—
10  
10  
12  
10  
17  
37  
—
μA  
μA  
μA  
μA  
μA  
μA  
μA  
μA  
μA  
μA  
μA  
-40°C  
+25°C  
+85°C  
+25°C  
-40°C  
+25°C  
+85°C  
-40°C  
+25°C  
+85°C  
+25°C  
DC41a  
DC41b  
DC41c  
DC41d  
DC41e  
DC41f  
DC42  
2.3V Watchdog Timer Current: ΔIWDT (Notes 3, 6)  
3.3V  
3.6V  
Watchdog Timer Current: ΔIWDT (Note 3)  
Watchdog Timer Current: ΔIWDT (Note 3)  
—
—
—
—
—
—
23  
RTCC + Timer1 w/32kHz Crystal: ΔIRTCC  
DC42a  
DC42b  
DC42c  
2.3V  
3.3V  
(Notes 3, 6)  
RTCC + Timer1 w/32kHz Crystal: ΔIRTCC  
(Note 3)  
DC42e  
DC42f  
DC42g  
DC42  
—
—
—
—
—
—
880  
—
—
—
10  
30  
μA  
μA  
μA  
μA  
μA  
μA  
μA  
μA  
μA  
μA  
-40°C  
+25°C  
+85°C  
-40°C  
+25°C  
+85°C  
RTCC + Timer1 w/32kHz Crystal: ΔIRTCC  
3.6V  
2.5V  
(Note 3)  
44  
1100  
1100  
1000  
—
DC42a  
DC42b  
DC42c  
DC42e  
DC42f  
DC42g  
ADC: ΔIADC (Notes 3, 4, 6)  
ADC: ΔIADC (Notes 3, 4)  
ADC: ΔIADC (Notes 3, 4)  
1100  
1100  
1000  
-40°C  
+25°C  
+85°C  
3.6V  
Note 1: Base IPD is measured with all digital peripheral modules enabled (ON bit = 1) and being clocked, CPU clock  
is disabled. All I/Os are configured as outputs and pulled low. WDT and FSCM are disabled.  
2: Data in the “Typical” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance  
only and are not tested.  
3: The Δ current is the additional current consumed when the module is enabled. This current should be  
added to the base IPD current.  
4: Test conditions for ADC module differential current are as follows: Internal ADC RC oscillator enabled.  
5: Data is characterized at +70°C and not tested. Parameter is for design guidance only.  
6: This parameter is characterized, but not tested in manufacturing.  
© 2009 Microchip Technology Inc.  
Preliminary  
DS61143F-page 123  
PIC32MX3XX/4XX  
TABLE 28-8: DC CHARACTERISTICS: I/O PIN INPUT SPECIFICATIONS  
Standard Operating Conditions: 2.3V to 3.6V (unless otherwise  
stated)  
Operating temperature  
DC CHARACTERISTICS  
-40°C ≤ TA ≤ +85°C for Industrial  
Param.  
No.  
Symbol  
Characteristics  
Min.  
Typical(1)  
Max.  
Units  
Conditions  
VIL  
Input Low Voltage  
I/O pins:  
DI10  
VSS  
VSS  
—
—
0.15 VDD  
0.2 VDD  
V
V
with TTL Buffer  
with Schmitt Trigger Buffer  
MCLR  
(Note 4)  
(Note 4)  
(Note 4)  
(Note 4)  
(Note 4)  
DI15  
DI16  
DI17  
DI18  
VSS  
VSS  
VSS  
VSS  
—
—
—
—
0.2 VDD  
0.2 VDD  
0.2 VDD  
0.3 VDD  
V
V
V
V
OSC1 (XT mode)  
OSC1 (HS mode)  
SDAx, SCLx  
SMBus disabled  
(Note 4)  
DI19  
DI20  
SDAx, SCLx  
VSS  
—
0.8  
V
SMBus enabled  
(Note 4)  
VIH  
Input High Voltage  
I/O pins:  
with Analog Functions  
0.8 VDD  
0.8 VDD  
—
—
—
—
VDD  
V
V
V
V
(Note 4)  
(Note 4)  
(Note 4)  
(Note 4)  
(Note 4)  
(Note 4)  
(Note 4)  
Digital Only  
0.25VDD + 0.8V  
0.8 VDD  
5.5  
5.5  
with TTL Buffer  
with Schmitt Trigger Buffer  
MCLR  
DI25  
DI26  
DI27  
DI28  
0.8 VDD  
0.7 VDD  
0.7 VDD  
0.7 VDD  
—
—
—
—
VDD  
VDD  
VDD  
5.5  
V
V
V
V
OSC1 (XT mode)  
OSC1 (HS mode)  
SDAx, SCLx  
SMBus disabled  
(Note 4)  
DI29  
DI30  
SDAx, SCLx  
2.1  
50  
—
5.5  
V
SMBus enabled,  
2.3V ≤ VPIN ≤ 5.5  
(Note 4)  
ICNPU CNxx Pull up Current  
250  
400  
μA VDD = 3.3V, VPIN = VSS  
IIL  
Input Leakage Current  
(Note 3)  
DI50  
DI51  
I/O Ports  
—
—
—
—
+1  
+1  
μA VSS ≤ VPIN ≤ VDD,  
Pin at high-impedance  
Analog Input Pins  
μA VSS ≤ VPIN ≤ VDD,  
Pin at high-impedance  
DI55  
DI56  
MCLR  
OSC1  
—
—
—
—
+1  
+1  
μA VSS ≤ VPIN ≤ VDD  
μA VSS ≤ VPIN ≤ VDD,  
XT and HS modes  
Note 1: Data in “Typical” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance  
only and are not tested.  
2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified  
levels represent normal operating conditions. Higher leakage current may be measured at different input  
voltages.  
3: Negative current is defined as current sourced by the pin.  
4: This parameter is characterized, but not tested in manufacturing.  
DS61143F-page 124  
Preliminary  
© 2009 Microchip Technology Inc.  
PIC32MX3XX/4XX  
TABLE 28-9: DC CHARACTERISTICS: I/O PIN OUTPUT SPECIFICATIONS  
Standard Operating Conditions: 2.3V to 3.6V (unless otherwise  
stated)  
DC CHARACTERISTICS  
Operating temperature  
-40°C ≤ TA ≤ +85°C for Industrial  
Param.  
No.  
Symbol  
Characteristics  
Min.  
Typical  
Max. Units Conditions  
VOL  
Output Low Voltage  
DO10  
DO16  
I/O Ports  
—
—
—
—
—
—
—
—
0.4  
0.4  
0.4  
0.4  
V
V
V
V
IOL = 7 mA, VDD = 3.6V  
IOL = 6 mA, VDD = 2.3V  
IOL = 3.5 mA, VDD = 3.6V  
IOL = 2.5 mA, VDD = 2.3V  
OSC2/CLKO  
VOH  
Output High Voltage  
DO20  
DO26  
I/O Ports  
2.4  
1.4  
2.4  
1.4  
—
—
—
—
—
—
—
—
V
V
V
V
IOH = -12 mA, VDD = 3.6V  
IOH = -12 mA, VDD = 2.3V  
IOH = -12 mA, VDD = 3.6V  
IOH = -12 mA, VDD = 2.3V  
OSC2/CLKO  
(3)  
TABLE 28-10: DC CHARACTERISTICS: PROGRAM MEMORY  
Standard Operating Conditions: 2.3V to 3.6V  
(unless otherwise stated)  
Operating temperature -40°C ≤ TA ≤ +85°C for Industrial  
Programming temperature 0°C ≤ TA ≤ +70°C (25°C recommended)  
DC CHARACTERISTICS  
Param.  
No.  
Symbol  
Characteristics  
Min. Typical(1) Max. Units  
Conditions  
Program Flash Memory  
Cell Endurance  
D130  
D131  
EP  
1000  
VMIN  
—
—
—
E/W -40°C to +85°C  
VPR  
VDD for Read  
3.6  
V
VMIN = Minimum operating  
voltage  
D132  
D134  
VPEW  
VDD for Erase or Write  
Characteristic Retention  
3.0  
20  
—
—
3.6  
—
V
0°C to +40°C  
TRETD  
Year Provided no other specifications  
are violated  
D135  
IDDP  
Supply Current during  
Programming  
—
10  
—
mA 0°C to +40°C  
TWW  
TRW  
Word Write Cycle Time  
20  
3
—
40  
—
μs 0°C to +40°C  
D136  
D137  
Row Write Cycle Time  
(Note 2)  
(128 words per row)  
4.5  
ms 0°C to +40°C  
TPE  
TCE  
Page Erase Cycle Time  
Chip Erase Cycle Time  
20  
80  
—
—
—
—
ms 0°C to +40°C  
ms 0°C to +40°C  
Note 1: Data in “Typical” column is at 3.3V, 25°C unless otherwise stated.  
2: The minimum SYSCLK for row programming is 4 MHz. Care should be taken to minimize bus activities  
during row programming, such as suspending any memory-to-memory DMA operations. If heavy bus  
loads are expected, selecting Bus Matrix Arbitration mode 2 (rotating priority) may be necessary. The  
default Arbitration mode is mode 1 (CPU has lowest priority).  
3: Refer to PIC32MX Flash Programming Specification (DS61145) for operating conditions during  
programming and erase cycles.  
© 2009 Microchip Technology Inc.  
Preliminary  
DS61143F-page 125  
PIC32MX3XX/4XX  
TABLE 28-11: PROGRAM FLASH MEMORY WAIT STATE CHARACTERISTICS  
Standard Operating Conditions: 2.3V to 3.6V  
DC CHARACTERISTICS  
(unless otherwise stated)  
Operating temperature -40°C ≤ TA ≤ +85°C for Industrial  
Required Flash wait states  
SYSCLK  
Units  
Comments  
0 Wait State  
1 Wait State  
2 Wait States  
0 to 30  
31 to 60  
61 to 80  
MHz  
Note 1: 40 MHz maximum for PIC32MX 40MHz family variants.  
TABLE 28-12: COMPARATOR SPECIFICATIONS  
Standard Operating Conditions: 2.3V to 3.6V  
(unless otherwise stated)  
DC CHARACTERISTICS  
Operating temperature-40°C  
≤
TA  
≤
+85°C for Industrial  
Param.  
Symbol  
No.  
Characteristics  
Input Offset Voltage  
Min. Typical Max.  
Units  
Comments  
D300  
—
0
±7.5  
—
±25  
VDD  
mV  
AVDD = VDD,  
AVSS = VSS  
VIOFF  
D301  
VICM  
Input Common Mode Voltage  
V
AVDD = VDD,  
AVSS = VSS  
(Note 2)  
D302  
D303  
CMRR  
TRESP  
Common Mode Rejection Ratio  
Response Time  
55  
—
—
—
dB  
Max VICM = (VDD - 1)V  
(Note 2)  
150  
400  
nsec  
AVDD = VDD,  
AVSS = VSS  
(Notes 1, 2)  
D304  
ON2OV  
Comparator Enabled to Output  
Valid  
—
—
10  
μs  
Comparator module is  
configured before setting  
the comparator ON bit.  
(Note 2)  
Note 1: Response time measured with one comparator input at (VDD – 1.5)/2, while the other input transitions  
from VSS to VDD.  
2: These parameters are characterized but not tested.  
TABLE 28-13: VOLTAGE REFERENCE SPECIFICATIONS  
Standard Operating Conditions: 2.3V to 3.6V  
DC CHARACTERISTICS  
(unless otherwise stated)  
Operating temperature-40°C  
≤
TA  
≤
+85°C for Industrial  
Param.  
Symbol  
No.  
Characteristics  
Resolution  
Min. Typical Max.  
Units  
Comments  
D310  
D311  
D312  
VRES  
VRAA  
TSET  
VDD/24  
—
—
—
—
VDD/32  
1/2  
LSb  
LSb  
μs  
Absolute Accuracy  
Settling Time(1)  
—
10  
Note 1: Settling time measured while CVRR = 1and CVR3:CVR0 transitions from ‘0000’ to ‘1111’. This  
parameter is characterized, but not tested in manufacturing.  
DS61143F-page 126  
Preliminary  
© 2009 Microchip Technology Inc.  
PIC32MX3XX/4XX  
TABLE 28-14: INTERNAL VOLTAGE REGULATOR SPECIFICATIONS  
Standard Operating Conditions: 2.3V to 3.6V  
(unless otherwise stated)  
Operating temperature-40°C  
DC CHARACTERISTICS  
≤
TA  
≤
+85°C for Industrial  
Param.  
Symbol  
No.  
Characteristics  
Min. Typical Max. Units  
Comments  
D320  
D321  
VDDCORE Regulator Output Voltage  
1.62  
4.7  
1.80  
10  
1.98  
—
V
CEFC  
External Filter Capacitor Value  
μF Capacitor must be low series  
resistance (< 3 ohms)  
D322  
TPWRT  
—
64  
—
ms ENVREG = 0  
© 2009 Microchip Technology Inc.  
Preliminary  
DS61143F-page 127  
PIC32MX3XX/4XX  
28.2 AC Characteristics and Timing  
Parameters  
The information contained in this section defines  
PIC32MX3XX/4XX AC characteristics and timing  
parameters.  
TABLE 28-15: AC CHARACTERISTICS  
AC CHARACTERISTICS  
Standard Operating Conditions: 2.3V to 3.6V  
(unless otherwise stated)  
Operating temperature -40°C ≤ TA ≤ +85°C for Industrial  
Operating voltage VDD range.  
FIGURE 28-1:  
LOAD CONDITIONS FOR DEVICE TIMING SPECIFICATIONS  
Load Condition 1 – for all pins except OSC2  
Load Condition 2 – for OSC2  
VDD/2  
CL  
RL  
Pin  
VSS  
CL  
Pin  
RL = 464Ω  
CL = 50 pF for all pins  
50 pF for OSC2 pin (EC mode)  
VSS  
TABLE 28-16: CAPACITIVE LOADING REQUIREMENTS ON OUTPUT PINS  
Standard Operating Conditions: 2.3V to 3.6V  
AC CHARACTERISTICS  
(unless otherwise stated)  
Operating temperature -40°C ≤ TA ≤ +85°C for Industrial  
Param.  
No.  
Symbol  
Characteristics  
Min. Typical(1) Max. Units  
Conditions  
DO56  
DO58  
CIO  
CB  
All I/O pins and OSC2  
SCLx, SDAx  
—
—
—
—
50  
pF EC mode  
pF In I2C™ mode  
400  
Note 1: Data in “Typical” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only  
and are not tested.  
FIGURE 28-2:  
EXTERNAL CLOCK TIMING  
OS30  
OS31  
OS20  
OSC1  
OS31  
OS30  
DS61143F-page 128  
Preliminary  
© 2009 Microchip Technology Inc.  
PIC32MX3XX/4XX  
TABLE 28-17: EXTERNAL CLOCK TIMING REQUIREMENTS  
Standard Operating Conditions: 2.3V to 3.6V  
(unless otherwise stated)  
Operating temperature -40°C ≤ TA ≤ +85°C for Industrial  
AC CHARACTERISTICS  
Param.  
Symbol  
No.  
Characteristics  
Min.  
Typical(1)  
Max.  
Units  
Conditions  
OS10  
FOSC  
External CLKI Frequency  
(External clocks allowed only  
in EC and ECPLL modes)  
DC  
4
—
—
50 (Note 3) MHz EC (Note 5)  
50 (Note 5) MHz ECPLL (Note 4)  
OS11  
OS12  
Oscillator Crystal Frequency  
3
4
—
—
10  
10  
MHz XT (Note 5)  
MHz XTPLL  
(Notes 4, 5)  
OS13  
OS14  
10  
10  
—
—
25  
25  
MHz HS (Note 5)  
MHz HSPLL  
(Notes 4, 5)  
OS15  
OS20  
32  
—
32.768  
—
100  
—
kHz SOSC (Note 5)  
TOSC  
TOSC = 1/FOSC = TCY (Note 2)  
—
See parameter  
OS10 for FOSC  
value  
OS30  
OS31  
OS40  
TOSL,  
TOSH  
External Clock In (OSC1)  
High or Low Time  
0.45 x TOSC  
—
—
—
nsec EC (Note 5)  
TOSR,  
TOSF  
External Clock In (OSC1)  
Rise or Fall Time  
—
—
0.05 x TOSC nsec EC (Note 5)  
TOST  
Oscillator Start-up Timer Period  
(Only applies to HS, HSPLL,  
XT, XTPLL and SOSC Clock  
Oscillator modes)  
1024  
—
TOSC (Note 5)  
OS41  
OS42  
TFSCM  
GM  
Primary Clock Fail Safe  
Time-out Period  
—
—
2
—
—
ms  
(Note 5)  
External Oscillator  
Transconductance  
12  
mA/V VDD = 3.3V  
TA = +25°C  
(Note 5)  
Note 1: Data in “Typical” column is at 3.3V, 25°C unless otherwise stated. Parameters are characterized but are  
not tested.  
2: Instruction cycle period (TCY) equals the input oscillator time base period. All specified values are based on  
characterization data for that particular oscillator type under standard operating conditions with the device  
executing code. Exceeding these specified limits may result in an unstable oscillator operation and/or  
higher than expected current consumption. All devices are tested to operate at “min.” values with an exter-  
nal clock applied to the OSC1/CLKI pin.  
3: 40 MHz maximum for PIC32MX 40 MHz family variants.  
4: PLL input requirements: 4 MHZ ≤ FPLLIN ≤ 5 MHZ (use PLL prescaler to reduce FOSC). This parameter is  
characterized, but tested at 10 MHz only at manufacturing.  
5: This parameter is characterized, but not tested in manufacturing.  
© 2009 Microchip Technology Inc.  
Preliminary  
DS61143F-page 129  
PIC32MX3XX/4XX  
TABLE 28-18: PLL CLOCK TIMING SPECIFICATIONS (VDD = 2.3V TO 3.6V)  
Standard Operating Conditions: 2.3V to 3.6V  
AC CHARACTERISTICS  
(unless otherwise stated)  
Operating temperature -40°C ≤ TA ≤ +85°C for Industrial  
Param.  
Symbol  
No.  
Characteristics(1)  
Min. Typical(2) Max. Units  
Conditions  
OS50  
FPLLI  
PLL Voltage Controlled  
Oscillator (VCO) Input  
Frequency Range  
4
—
5
MHz ECPLL, HSPLL, XTPLL,  
FRCPLL modes  
OS51  
FSYS  
On-Chip VCO System  
Frequency  
60  
—
120  
MHz  
OS52  
OS53  
TLOCK  
DCLK  
PLL Start-up Time (Lock Time)  
—
—
—
2
ms  
CLKO Stability  
(Period Jitter or Cumulative)  
-0.25  
+0.25  
%
Measured over 100 ms  
period  
Note 1: These parameters are characterized, but not tested in manufacturing.  
2: Data in “Typical” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance  
only and are not tested.  
TABLE 28-19: INTERNAL FRC ACCURACY  
Standard Operating Conditions: 2.3V to 3.6V  
AC CHARACTERISTICS  
(unless otherwise stated)  
Operating temperature  
-40°C ≤ TA ≤ +85°C for industrial  
Units Conditions  
Param.  
No.  
Characteristics  
Min. Typical Max.  
Internal FRC Accuracy @ 8.00 MHz (Note 1)  
F20 FRC -2  
—
+2  
%
Note 1: Frequency calibrated at 25°C and 3.3V. TUN bits can be used to compensate for temperature drift.  
TABLE 28-20: INTERNAL RC ACCURACY  
Standard Operating Conditions: 2.3V to 3.6V  
AC CHARACTERISTICS  
(unless otherwise stated)  
Operating temperature -40°C ≤ TA ≤ +85°C for Industrial  
Param.  
No.  
Characteristics  
Min. Typical Max.  
Units  
Conditions  
LPRC @ 31.25 kHz (Note 1)  
F21  
-15  
—
+15  
%
Note 1: Change of LPRC frequency as VDD changes.  
DS61143F-page 130  
Preliminary  
© 2009 Microchip Technology Inc.  
PIC32MX3XX/4XX  
FIGURE 28-3:  
I/O TIMING CHARACTERISTICS  
I/O Pin  
(Input)  
DI35  
DI40  
I/O Pin  
(Output)  
DO31  
DO32  
Note: Refer to Figure 28-1 for load conditions.  
TABLE 28-21: I/O TIMING REQUIREMENTS  
Standard Operating Conditions: 2.3V to 3.6V  
(unless otherwise stated)  
AC CHARACTERISTICS  
Operating temperature -40°C ≤ TA ≤ +85°C for Industrial  
Param.  
Symbol  
No.  
Characteristics(2)  
Min.  
Typical(1)  
Max.  
Units  
Conditions  
DO31  
DO32  
DI35  
TIOR  
TIOF  
TINP  
TRBP  
Port Output Rise Time  
—
—
10  
2
5
5
10  
10  
—
—
nsec  
nsec  
Port Output Fall Time  
INTx Pin High or Low Time  
CNx High or Low Time (input)  
—
—
nsec  
DI40  
TSYSCLK  
Note 1: Data in “Typical” column is at 3.3V, 25°C unless otherwise stated.  
2: This parameter is characterized, but not tested in manufacturing.  
© 2009 Microchip Technology Inc.  
Preliminary  
DS61143F-page 131  
PIC32MX3XX/4XX  
FIGURE 28-4:  
POWER-ON RESET TIMING CHARACTERISTICS  
Internal Voltage Regulator Enabled  
Clock Sources = (FRC, FRCDIV, FRCDIV16, FRCPLL, EC, ECPLL and LPRC)  
VDD  
VPOR  
(TSYSDLY)  
SY02  
Power Up Sequence  
(Note 2)  
CPU starts fetching code  
SY00  
(TPU)  
(Note 1)  
Internal Voltage Regulator Enabled  
Clock Sources = (HS, HSPLL, XT, XTPLL and SOSC)  
VDD  
VPOR  
(TSYSDLY)  
SY02  
Power Up Sequence  
(Note 2)  
CPU starts fetching code  
SY00  
(TPU)  
SY10  
(TOST)  
(Note 1)  
External VDDCORE Provided  
Clock Sources = (FRC, FRCDIV, FRCDIV16, FRCPLL, EC, ECPLL and LPRC)  
VDD  
VDDCORE  
VPOR  
(TSYSDLY)  
SY02  
Power Up Sequence  
(Note 3)  
CPU starts fetching code  
SY01  
(TPWRT)  
(Note 1)  
Note 1: The Power-up period will be extended if the Power-up sequence completes before the device  
exits from BOR (VDD < VDDMIN).  
2: Includes interval voltage regulator stabilization delay.  
3: Power-Up Timer (PWRT); only active when the internal voltage regulator is disabled  
DS61143F-page 132  
Preliminary  
© 2009 Microchip Technology Inc.  
PIC32MX3XX/4XX  
FIGURE 28-5:  
EXTERNAL RESET TIMING CHARACTERISTICS  
Clock Sources = (FRC, FRCDIV, FRCDIV16, FRCPLL, EC, ECPLL and LPRC)  
MCLR  
TMCLR  
(SY20)  
BOR  
TBOR  
(SY30)  
(TSYSDLY)  
SY02  
Reset Sequence  
CPU starts fetching code  
Clock Sources = (HS, HSPLL, XT, XTPLL and SOSC)  
(TSYSDLY)  
SY02  
Reset Sequence  
CPU starts fetching code  
TOST  
(SY10)  
TABLE 28-22: RESETS TIMING  
Standard Operating Conditions: 2.3V to 3.6V  
(unless otherwise stated)  
AC CHARACTERISTICS  
Operating temperature -40°C ≤ TA ≤ +85°C for Industrial  
Param.  
Symbol  
No.  
Characteristics(1)  
Power-up Period  
Min.  
—
Typical(2)  
400  
Max.  
600  
80  
Units  
Conditions  
SY00  
TPU  
μs  
-40°C to +85°C  
Internal Voltage Regulator Enabled  
SY01  
TPWRT  
Power-up Period  
External VDDCORE Applied  
(Power-Up-Timer Active)  
48  
64  
ms  
—
-40°C to +85°C  
-40°C to +85°C  
—
—
SY02  
TSYSDLY System Delay Period:  
Time required to reload Device  
1 μs  
+
Configuration Fuses plus SYSCLK  
delay before first instruction is  
fetched.  
8 SYSCLK  
cycles  
—
—
—
—
SY20  
SY30  
TMCLR  
TBOR  
MCLR Pulse Width (low)  
BOR Pulse Width (low)  
2
1
μs  
μs  
-40°C to +85°C  
-40°C to +85°C  
Note 1: These parameters are characterized, but not tested in manufacturing.  
2: Data in “Typ” column is at 3.3V, 25°C unless otherwise stated. Characterized by design but not tested.  
© 2009 Microchip Technology Inc.  
Preliminary  
DS61143F-page 133  
PIC32MX3XX/4XX  
FIGURE 28-6:  
TIMER1, 2, 3, 4, 5 EXTERNAL CLOCK TIMING CHARACTERISTICS  
TxCK  
Tx11  
Tx10  
Tx15  
Tx20  
OS60  
TMRx  
Note: Refer to Figure 28-1 for load conditions.  
(1)  
TABLE 28-23: TIMER1 EXTERNAL CLOCK TIMING REQUIREMENTS  
Standard Operating Conditions: 2.3V to 3.6V  
(unless otherwise stated)  
AC CHARACTERISTICS  
Operating temperature -40°C ≤ TA ≤ +85°C for Industrial  
Param.  
No.  
Symbol  
Characteristics(2)  
Min.  
Typical Max. Units  
Conditions  
[(12.5nsec or 1TPB) / N]  
+ 25nsec  
TA10  
TTXH  
TxCK  
Synchronous,  
—
—
—
—
—
—
—
—
—
—
—
—
nsec Must also meet  
parameter TA15.  
High Time with prescaler  
Asynchronous,  
with prescaler  
10  
nsec  
TA11  
TA15  
TTXL  
TTXP  
TxCK  
Low Time  
Synchronous, [(12.5nsec or 1TPB) / N]  
nsec Must also meet  
parameter TA15.  
with prescaler  
+ 25nsec  
Asynchronous,  
with prescaler  
10  
nsec  
TxCK  
Synchronous,  
[(25nsec or 2TPB) / N]  
+ 50nsec  
nsec  
Input Period with prescaler  
Asynchronous,  
with prescaler  
20  
nsec N = prescale  
value  
(1, 8, 64, 256)  
OS60 FT1  
SOSC1/T1CK Oscillator  
Input Frequency Range  
(oscillator enabled by set-  
ting TCS bit (T1CON<1>))  
32  
—
100 kHz  
TA20  
TCKEXT- Delay from External TxCK  
—
1
TPB  
MRL  
Clock Edge to Timer Incre-  
ment  
Note 1: Timer1 is a Type A.  
2: This parameter is characterized, but not tested in manufacturing.  
DS61143F-page 134  
Preliminary  
© 2009 Microchip Technology Inc.  
PIC32MX3XX/4XX  
TABLE 28-24: TIMER2, 3, 4, 5 EXTERNAL CLOCK TIMING REQUIREMENTS  
Standard Operating Conditions: 2.3V to 3.6V  
(unless otherwise stated)  
AC CHARACTERISTICS  
Operating temperature -40°C ≤ TA ≤ +85°C for Industrial  
Param.  
No.  
Symbol  
Characteristics(1)  
Min.  
Max. Units  
Conditions  
N = prescale  
nsec Must also meet  
[(12.5nsec or 1TPB) / N]  
+ 25nsec  
TB10  
TTXH  
TxCK  
High Time  
Synchronous,  
with prescaler  
—
value  
(1, 2, 4, 8, 16,  
32, 64, 256)  
parameter  
TB15.  
TB11  
TTXL  
TTXP  
TxCK  
Low Time  
[(12.5nsec or 1TPB) / N]  
+ 25nsec  
—
nsec Must also meet  
parameter  
Synchronous,  
with prescaler  
TB15.  
TB15  
TB20  
TxCK  
Input Period  
[(25nsec or 2TPB) / N]  
+ 50nsec  
—
1
nsec  
TPB  
Synchronous,  
with prescaler  
TCKEXT- Delay from External TxCK  
—
MRL  
Clock Edge to Timer Incre-  
ment  
Note 1: These parameters are characterized, but not tested in manufacturing.  
FIGURE 28-7:  
INPUT CAPTURE (CAPx) TIMING CHARACTERISTICS  
ICx  
IC10  
IC11  
IC15  
Note: Refer to Figure 28-1 for load conditions.  
TABLE 28-25: INPUT CAPTURE MODULE TIMING REQUIREMENTS  
Standard Operating Conditions: 2.3V to 3.6V  
AC CHARACTERISTICS  
(unless otherwise stated)  
Operating temperature -40°C ≤ TA ≤ +85°C for Industrial  
Param.  
Symbol  
Characteristics(1)  
Min.  
Max. Units  
Conditions  
N = prescale  
nsec Must also  
No.  
IC10  
TCCL  
ICx Input Low Time  
ICx Input High Time  
ICx Input Period  
[(12.5nsec or 1TPB) / N]  
+ 25nsec  
—
—
—
value (1, 4, 16)  
meet  
parameter  
IC15.  
IC11  
IC15  
TCCH  
[(12.5nsec or 1TPB) / N]  
+ 25nsec  
nsec  
Must also  
meet  
parameter  
IC15.  
TCCP  
[(25nsec or 2TPB) / N]  
+ 50nsec  
nsec  
Note 1: These parameters are characterized, but not tested in manufacturing.  
© 2009 Microchip Technology Inc.  
Preliminary  
DS61143F-page 135  
PIC32MX3XX/4XX  
FIGURE 28-8:  
OUTPUT COMPARE MODULE (OCx) TIMING CHARACTERISTICS  
OCx  
(Output Compare  
or PWM Mode)  
OC10  
OC11  
Note: Refer to Figure 28-1 for load conditions.  
TABLE 28-26: OUTPUT COMPARE MODULE TIMING REQUIREMENTS  
Standard Operating Conditions: 2.3V to 3.6V  
(unless otherwise stated)  
Operating temperature -40°C ≤ TA ≤ +85°C for Industrial  
AC CHARACTERISTICS  
Param.  
No.  
Symbol  
Characteristics(1)  
Min.  
Typical(2)  
Max.  
Units  
Conditions  
OC10  
OC11  
TCCF  
TCCR  
OCx Output Fall Time  
OCx Output Rise Time  
—
—
—
—
—
—
nsec See parameter DO32.  
nsec See parameter DO31.  
Note 1: These parameters are characterized, but not tested in manufacturing.  
2: Data in “Typical” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only  
and are not tested.  
FIGURE 28-9:  
OC/PWM MODULE TIMING CHARACTERISTICS  
OC20  
OCFA/OCFB  
OC15  
OCx  
Note: Refer to Figure 28-1 for load conditions.  
TABLE 28-27: SIMPLE OC/PWM MODE TIMING REQUIREMENTS  
Standard Operating Conditions: 2.3V to 3.6V  
(unless otherwise stated)  
Operating temperature -40°C ≤ TA ≤ +85°C for Industrial  
AC CHARACTERISTICS  
Param  
Symbol  
No.  
Characteristics(1)  
Min  
Typical(2)  
Max  
Units  
Conditions  
OC15  
OC20  
TFD  
Fault Input to PWM I/O Change  
Fault Input Pulse Width  
—
—
—
25  
—
nsec  
nsec  
TFLT  
50  
Note 1: These parameters are characterized, but not tested in manufacturing.  
2: Data in “Typical” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only  
and are not tested.  
DS61143F-page 136  
Preliminary  
© 2009 Microchip Technology Inc.  
PIC32MX3XX/4XX  
FIGURE 28-10:  
SPIx MODULE MASTER MODE (CKE = 0) TIMING CHARACTERISTICS  
SCKx  
(CKP = 0)  
SP11  
SP10  
SP21  
SP20  
SCKx  
(CKP = 1)  
SP35  
SP31  
SP21  
LSb  
SP20  
Bit 14 - - - - - -1  
MSb  
SDOx  
SDIx  
SP30  
MSb In  
SP40  
LSb In  
Bit 14 - - - -1  
SP41  
Note: Refer to Figure 28-1 for load conditions.  
TABLE 28-28: SPIx MASTER MODE (CKE = 0) TIMING REQUIREMENTS  
Standard Operating Conditions: 2.3V to 3.6V  
(unless otherwise stated)  
Operating temperature -40°C ≤ TA ≤ +85°C for Industrial  
AC CHARACTERISTICS  
Param.  
Symbol  
No.  
Characteristics(1)  
Min.  
Typical(2) Max. Units  
Conditions  
SCKx Output Low Time  
(Note 3)  
SP10  
SP11  
SP20  
SP21  
SP30  
SP31  
SP35  
SP40  
SP41  
TSCL  
TSCH  
TSCF  
TSCR  
TDOF  
TDOR  
TSCK/2  
—
—
—
—
—
—
nsec  
nsec  
nsec  
nsec  
nsec  
nsec  
nsec  
nsec  
nsec  
SCKx Output High Time  
(Note 3)  
TSCK/2  
—
SCKx Output Fall Time  
(Note 4)  
See parameter DO32.  
See parameter DO31.  
See parameter DO32.  
See parameter DO31.  
SCKx Output Rise Time  
(Note 4)  
—
—
—
—
—
—
—
—
—
—
15  
—
—
SDOx Data Output Fall Time  
(Note 4)  
—
SDOx Data Output Rise Time  
(Note 4)  
—
TSCH2DOV, SDOx Data Output Valid after  
TSCL2DOV SCKx Edge  
—
TDIV2SCH, Setup Time of SDIx Data Input  
10  
10  
TDIV2SCL  
TSCH2DIL, Hold Time of SDIx Data Input  
TSCL2DIL to SCKx Edge  
Note 1: These parameters are characterized, but not tested in manufacturing.  
to SCKx Edge  
2: Data in “Typical” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance  
only and are not tested.  
3: The minimum clock period for SCKx is 40 nsec. Therefore, the clock generated in Master mode must not  
violate this specification.  
4: Assumes 50 pF load on all SPIx pins.  
© 2009 Microchip Technology Inc.  
Preliminary  
DS61143F-page 137  
PIC32MX3XX/4XX  
FIGURE 28-11:  
SPIx MODULE MASTER MODE (CKE = 1) TIMING CHARACTERISTICS  
SP36  
SCKX  
(CKP = 0)  
SP11  
SP10  
SP21  
SP20  
SP20  
SP21  
SCKX  
(CKP = 1)  
SP35  
LSb  
MSb  
Bit 14 - - - - - -1  
SDOX  
SDIX  
SP30,SP31  
MSb In  
SP41  
Bit 14 - - - -1  
LSb In  
SP40  
Note: Refer to Figure 28-1 for load conditions.  
TABLE 28-29: SPIx MODULE MASTER MODE (CKE = 1) TIMING REQUIREMENTS  
Standard Operating Conditions: 2.3V to 3.6V  
AC CHARACTERISTICS  
(unless otherwise stated)  
Operating temperature -40°C ≤ TA ≤ +85°Cfor Industrial  
Param.  
Symbol  
No.  
Characteristics(1)  
Min.  
Typical(2) Max. Units  
Conditions  
SCKx Output Low Time  
(Note 3)  
SP10  
SP11  
SP20  
SP21  
SP30  
SP31  
SP35  
SP36  
SP40  
TSCL  
TSCH  
TSCF  
TSCR  
TDOF  
TDOR  
TSCK/2  
—
—
—
—
—
—
nsec  
nsec  
nsec  
nsec  
nsec  
nsec  
nsec  
nsec  
nsec  
SCKx Output High Time  
(Note 3)  
TSCK/2  
—
SCKx Output Fall Time  
(Note 4)  
See parameter DO32.  
See parameter DO31.  
See parameter DO32.  
See parameter DO31.  
SCKx Output Rise Time  
(Note 4)  
—
—
—
—
—
—
—
—
—
—
15  
—
—
SDOx Data Output Fall Time  
(Note 4)  
—
SDOx Data Output Rise Time  
(Note 4)  
—
TSCH2DOV, SDOx Data Output Valid after  
TSCL2DOV SCKx Edge  
—
TDOV2SC, SDOx Data Output Setup to  
TDOV2SCL First SCKx Edge  
15  
TDIV2SCH, Setup Time of SDIx Data Input  
TDIV2SCL to SCKx Edge  
10  
Note 1: These parameters are characterized, but not tested in manufacturing.  
2: Data in “Typical” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only  
and are not tested.  
3: The minimum clock period for SCKx is 40 nsec. Therefore, the clock generated in Master mode must not  
violate this specification.  
4: Assumes 50 pF load on all SPIx pins.  
DS61143F-page 138  
Preliminary  
© 2009 Microchip Technology Inc.  
PIC32MX3XX/4XX  
TABLE 28-29: SPIx MODULE MASTER MODE (CKE = 1) TIMING REQUIREMENTS (CONTINUED)  
Standard Operating Conditions: 2.3V to 3.6V  
AC CHARACTERISTICS  
(unless otherwise stated)  
Operating temperature -40°C ≤ TA ≤ +85°Cfor Industrial  
Param.  
Symbol  
No.  
Characteristics(1)  
Min.  
Typical(2) Max. Units  
Conditions  
SP41  
TSCH2DIL, Hold Time of SDIx Data Input  
TSCL2DIL to SCKx Edge  
Note 1: These parameters are characterized, but not tested in manufacturing.  
—
—
nsec  
10  
2: Data in “Typical” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only  
and are not tested.  
3: The minimum clock period for SCKx is 40 nsec. Therefore, the clock generated in Master mode must not  
violate this specification.  
4: Assumes 50 pF load on all SPIx pins.  
FIGURE 28-12:  
SPIx MODULE SLAVE MODE (CKE = 0) TIMING CHARACTERISTICS  
SSX  
SP52  
SP50  
SCKX  
(CKP = 0)  
SP71  
SP70  
SP72  
SP73  
SP72  
SCKX  
(CKP = 1)  
SP73  
LSb  
SP35  
MSb  
SDOX  
SDIX  
Bit 14 - - - - - -1  
SP30,SP31  
SP51  
Bit 14 - - - -1  
MSb In  
SP41  
LSb In  
SP40  
Note: Refer to Figure 28-1 for load conditions.  
© 2009 Microchip Technology Inc.  
Preliminary  
DS61143F-page 139  
PIC32MX3XX/4XX  
TABLE 28-30: SPIx MODULE SLAVE MODE (CKE = 0) TIMING REQUIREMENTS  
Standard Operating Conditions: 2.3V to 3.6V  
AC CHARACTERISTICS  
(unless otherwise stated)  
Operating temperature -40°C ≤ TA ≤ +85°C for Industrial  
Param.  
Symbol  
No.  
Characteristics(1)  
Min.  
Typical(2) Max. Units  
Conditions  
TSCK/2  
SP70  
TSCL  
SCKx Input Low Time  
(Note 3)  
—
—
—
—
nsec  
nsec  
SP71  
TSCH  
SCKx Input High Time  
TSCK/2  
(Note 3)  
SP72  
SP73  
SP30  
TSCF  
TSCR  
TDOF  
SCKx Input Fall Time  
SCKx Input Rise Time  
—
—
—
5
5
10  
10  
—
nsec  
nsec  
SDOx Data Output Fall Time  
—
nsec See parameter DO32.  
(Note 4)  
SP31  
TDOR  
SDOx Data Output Rise Time  
(Note 4)  
—
—
10  
10  
60  
5
—
—
—
—
—
—
—
nsec  
nsec  
nsec  
nsec  
nsec  
nsec  
See parameter DO31.  
SP35 TSCH2DOV, SDOx Data Output Valid after  
TSCL2DOV SCKx Edge  
15  
—
—
SP40 TDIV2SCH, Setup Time of SDIx Data Input  
TDIV2SCL to SCKx Edge  
SP41 TSCH2DIL, Hold Time of SDIx Data Input  
TSCL2DIL  
to SCKx Edge  
SP50 TSSL2SCH, SSx ↓ to SCKx ↑ or SCKx Input  
—
TSSL2SCL  
SP51 TSSH2DOZ SSx ↑ to SDOx Output  
25  
High-Impedance  
(Note 3)  
SP52  
TSCH2SSH SSx after SCKx Edge  
TSCL2SSH  
TSCK + 20  
—
—
nsec  
—
Note 1: These parameters are characterized, but not tested in manufacturing.  
2: Data in “Typical” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only  
and are not tested.  
3: The minimum clock period for SCKx is 40 nsec.  
4: Assumes 50 pF load on all SPIx pins.  
DS61143F-page 140  
Preliminary  
© 2009 Microchip Technology Inc.  
PIC32MX3XX/4XX  
FIGURE 28-13:  
SPIx MODULE SLAVE MODE (CKE = 1) TIMING CHARACTERISTICS  
SP60  
SSx  
SP52  
SP50  
SCKx  
(CKP = 0)  
SP71  
SP70  
SP72  
SP73  
SP73  
SCKx  
(CKP = 1)  
SP35  
SP72  
LSb  
SP52  
Bit 14 - - - - - -1  
MSb  
SDOx  
SDIx  
SP30,SP31  
Bit 14 - - - -1  
SP51  
MSb In  
SP41  
LSb In  
SP40  
Note: Refer to Figure 28-1 for load conditions.  
TABLE 28-31: SPIx MODULE SLAVE MODE (CKE = 1) TIMING REQUIREMENTS  
Standard Operating Conditions: 2.3V to 3.6V  
AC CHARACTERISTICS  
(unless otherwise stated)  
Operating temperature -40°C ≤ TA ≤ +85°C for Industrial  
Param.  
Symbol  
No.  
Characteristics(1)  
Min.  
Typical(2) Max.  
Units  
Conditions  
TSCK/2  
SP70  
TSCL  
SCKx Input Low Time  
(Note 3)  
—
—
—
—
nsec  
SP71  
TSCH  
SCKx Input High Time  
TSCK/2  
nsec  
(Note 3)  
SP72  
SP73  
SP30  
TSCF  
TSCR  
TDOF  
SCKx Input Fall Time  
SCKx Input Rise Time  
—
—
—
5
5
10  
10  
—
nsec  
nsec  
nsec  
SDOx Data Output Fall Time  
(Note 4)  
—
See parameter  
DO32.  
SP31  
SP35  
SP40  
SP41  
TDOR  
SDOx Data Output Rise Time  
(Note 4)  
—
—
10  
10  
—
—
—
—
—
nsec  
nsec  
nsec  
nsec  
See parameter  
DO31.  
TSCH2DOV, SDOx Data Output Valid after  
TSCL2DOV SCKx Edge  
15  
—
—
TDIV2SCH, Setup Time of SDIx Data Input  
TDIV2SCL to SCKx Edge  
TSCH2DIL, Hold Time of SDIx Data Input  
TSCL2DIL  
to SCKx Edge  
Note 1: These parameters are characterized, but not tested in manufacturing.  
2: Data in “Typical” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance  
only and are not tested.  
3: The minimum clock period for SCKx is 40 nsec.  
4: Assumes 50 pF load on all SPIx pins.  
© 2009 Microchip Technology Inc.  
Preliminary  
DS61143F-page 141  
PIC32MX3XX/4XX  
TABLE 28-31: SPIx MODULE SLAVE MODE (CKE = 1) TIMING REQUIREMENTS (CONTINUED)  
Standard Operating Conditions: 2.3V to 3.6V  
AC CHARACTERISTICS  
(unless otherwise stated)  
Operating temperature -40°C ≤ TA ≤ +85°C for Industrial  
Param.  
Symbol  
No.  
Characteristics(1)  
Min.  
Typical(2) Max.  
Units  
Conditions  
SP50  
TSSL2SCH, SSx ↓ to SCKx ↓ or SCKx ↑  
TSSL2SCL Input  
60  
—
—
—
nsec  
SP51  
TSSH2DOZ SSx ↑ to SDOX Output  
High-Impedance  
5
25  
nsec  
(Note 4)  
SP52  
SP60  
TSCH2SSH SSx ↑ after SCKx Edge  
TSCL2SSH  
TSCK + 20  
—
—
—
—
nsec  
nsec  
TSSL2DOV SDOx Data Output Valid after  
SSx Edge  
25  
Note 1: These parameters are characterized, but not tested in manufacturing.  
2: Data in “Typical” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance  
only and are not tested.  
3: The minimum clock period for SCKx is 40 nsec.  
4: Assumes 50 pF load on all SPIx pins.  
FIGURE 28-14:  
I2Cx BUS START/STOP BITS TIMING CHARACTERISTICS (MASTER MODE)  
SCLx  
SDAx  
IM31  
IM34  
IM30  
IM33  
Stop  
Condition  
Start  
Condition  
Note: Refer to Figure 28-1 for load conditions.  
FIGURE 28-15:  
I2Cx BUS DATA TIMING CHARACTERISTICS (MASTER MODE)  
IM20  
IM21  
IM11  
IM10  
SCLx  
IM11  
IM26  
IM10  
IM33  
IM25  
SDAx  
In  
IM45  
IM40  
IM40  
SDAx  
Out  
Note: Refer to Figure 28-1 for load conditions.  
DS61143F-page 142  
Preliminary  
© 2009 Microchip Technology Inc.  
PIC32MX3XX/4XX  
TABLE 28-32: I2Cx BUS DATA TIMING REQUIREMENTS (MASTER MODE)  
Standard Operating Conditions: 2.3V to 3.6V  
(unless otherwise stated)  
Operating temperature -40°C ≤ TA ≤ +85°C for Industrial  
AC CHARACTERISTICS  
Param.  
Symbol  
No.  
Characteristics  
Min.(1)  
Max.  
Units  
Conditions  
IM10  
TLO:SCL Clock Low Time 100 kHz mode  
400 kHz mode  
TPB * (BRG + 2)  
TPB * (BRG + 2)  
TPB * (BRG + 2)  
—
—
—
μs  
μs  
μs  
—
—
—
1 MHz mode  
(Note 2)  
IM11  
THI:SCL Clock High Time 100 kHz mode  
400 kHz mode  
—
—
—
μs  
μs  
μs  
—
—
—
TPB * (BRG + 2)  
TPB * (BRG + 2)  
TPB * (BRG + 2)  
1 MHz mode  
(Note 2)  
IM20  
IM21  
IM25  
IM26  
IM30  
TF:SCL  
TR:SCL  
SDAx and SCLx 100 kHz mode  
—
20 + 0.1 CB  
—
300  
300  
100  
nsec CB is specified to be  
Fall Time  
from 10 to 400 pF.  
400 kHz mode  
nsec  
1 MHz mode  
(Note 2)  
nsec  
SDAx and SCLx 100 kHz mode  
—
20 + 0.1 CB  
—
1000  
300  
nsec CB is specified to be  
Rise Time  
from 10 to 400 pF.  
400 kHz mode  
nsec  
1 MHz mode  
(Note 2)  
300  
nsec  
TSU:DAT Data Input  
Setup Time  
100 kHz mode  
400 kHz mode  
250  
100  
100  
—
—
—
nsec  
nsec  
nsec  
—
—
1 MHz mode  
(Note 2)  
THD:DAT Data Input  
Hold Time  
100 kHz mode  
400 kHz mode  
0
0
0
—
μs  
μs  
μs  
0.9  
0.3  
1 MHz mode  
(Note 2)  
TSU:STA Start Condition 100 kHz mode  
—
—
—
μs  
μs  
μs  
Only relevant for  
Repeated Start  
condition.  
TPB * (BRG + 2)  
TPB * (BRG + 2)  
TPB * (BRG + 2)  
Setup Time  
400 kHz mode  
1 MHz mode  
(Note 2)  
IM31  
IM33  
IM34  
THD:STA Start Condition 100 kHz mode  
—
—
—
μs  
μs  
μs  
After this period, the  
first clock pulse is  
generated.  
TPB * (BRG + 2)  
TPB * (BRG + 2)  
TPB * (BRG + 2)  
Hold Time  
400 kHz mode  
1 MHz mode  
(Note 2)  
TSU:STO Stop Condition 100 kHz mode  
—
—
—
μs  
μs  
μs  
—
—
TPB * (BRG + 2)  
TPB * (BRG + 2)  
TPB * (BRG + 2)  
Setup Time  
400 kHz mode  
1 MHz mode  
(Note 2)  
THD:STO Stop Condition  
Hold Time  
100 kHz mode  
400 kHz mode  
—
—
—
nsec  
nsec  
nsec  
TPB * (BRG + 2)  
TPB * (BRG + 2)  
TPB * (BRG + 2)  
1 MHz mode  
(Note 2)  
Note 1: BRG is the value of the I2C™ Baud Rate Generator.  
2: Maximum pin capacitance = 10 pF for all I2Cx pins (for 1 MHz mode only).  
© 2009 Microchip Technology Inc.  
Preliminary  
DS61143F-page 143  
PIC32MX3XX/4XX  
TABLE 28-32: I2Cx BUS DATA TIMING REQUIREMENTS (MASTER MODE) (CONTINUED)  
Standard Operating Conditions: 2.3V to 3.6V  
AC CHARACTERISTICS  
(unless otherwise stated)  
Operating temperature -40°C ≤ TA ≤ +85°C for Industrial  
Param.  
Symbol  
No.  
Characteristics  
Min.(1)  
Max.  
Units  
Conditions  
IM40  
IM45  
IM50  
TAA:SCL Output Valid  
From Clock  
100 kHz mode  
—
—
—
3500  
1000  
350  
nsec  
nsec  
nsec  
—
—
—
400 kHz mode  
1 MHz mode  
(Note 2)  
TBF:SDA Bus Free Time 100 kHz mode  
400 kHz mode  
4.7  
1.3  
0.5  
—
—
—
μs  
μs  
μs  
The amount of time the  
bus must be free  
before a new  
1 MHz mode  
(Note 2)  
transmission can start.  
CB  
Bus Capacitive Loading  
—
400  
pF  
Note 1: BRG is the value of the I2C™ Baud Rate Generator.  
2: Maximum pin capacitance = 10 pF for all I2Cx pins (for 1 MHz mode only).  
FIGURE 28-16:  
I2Cx BUS START/STOP BITS TIMING CHARACTERISTICS (SLAVE MODE)  
SCLx  
IS34  
IS31  
IS30  
IS33  
SDAx  
Stop  
Condition  
Start  
Condition  
Note: Refer to Figure 28-1 for load conditions.  
FIGURE 28-17:  
I2Cx BUS DATA TIMING CHARACTERISTICS (SLAVE MODE)  
IS20  
IS21  
IS11  
IS10  
SCLx  
IS30  
IS26  
IS31  
IS33  
IS25  
SDAx  
In  
IS45  
IS40  
IS40  
SDAx  
Out  
Note: Refer to Figure 28-1 for load conditions.  
DS61143F-page 144  
Preliminary  
© 2009 Microchip Technology Inc.  
PIC32MX3XX/4XX  
TABLE 28-33: I2Cx BUS DATA TIMING REQUIREMENTS (SLAVE MODE)  
Standard Operating Conditions: 2.3V to 3.6V  
(unless otherwise stated)  
Operating temperature -40°C ≤ TA ≤ +85°C for Industrial  
AC CHARACTERISTICS  
Param.  
Symbol  
No.  
Characteristics  
Min.  
Max. Units  
Conditions  
IS10  
TLO:SCL Clock Low Time 100 kHz mode  
400 kHz mode  
4.7  
—
—
—
—
—
—
μs  
μs  
μs  
μs  
μs  
μs  
PBCLK must operate at a  
minimum of 800 KHz.  
1.3  
0.5  
4.0  
0.6  
0.5  
PBCLK must operate at a  
minimum of 3.2 MHz.  
1 MHz mode  
(Note 1)  
IS11  
THI:SCL  
Clock High Time 100 kHz mode  
PBCLK must operate at a  
minimum of 800 KHz.  
400 kHz mode  
PBCLK must operate at a  
minimum of 3.2 MHz.  
1 MHz mode  
(Note 1)  
IS20  
IS21  
IS25  
IS26  
IS30  
IS31  
IS33  
TF:SCL  
TR:SCL  
SDAx and SCLx 100 kHz mode  
—
20 + 0.1 CB  
—
300  
300  
100  
nsec CB is specified to be from  
Fall Time  
10 to 400 pF.  
400 kHz mode  
nsec  
1 MHz mode  
(Note 1)  
nsec  
SDAx and SCLx 100 kHz mode  
—
20 + 0.1 CB  
—
1000  
300  
nsec CB is specified to be from  
Rise Time  
10 to 400 pF.  
400 kHz mode  
nsec  
1 MHz mode  
(Note 1)  
300  
nsec  
TSU:DAT Data Input  
Setup Time  
100 kHz mode  
400 kHz mode  
250  
100  
100  
—
—
—
nsec  
nsec  
nsec  
1 MHz mode  
(Note 1)  
THD:DAT Data Input  
Hold Time  
100 kHz mode  
400 kHz mode  
0
0
0
—
nsec  
μs  
0.9  
0.3  
1 MHz mode  
(Note 1)  
μs  
TSU:STA Start Condition  
Setup Time  
100 kHz mode  
400 kHz mode  
4700  
600  
—
—
—
μs  
μs  
μs  
Only relevant for Repeated  
Start condition.  
1 MHz mode  
(Note 1)  
250  
THD:STA Start Condition  
Hold Time  
100 kHz mode  
400 kHz mode  
4000  
600  
—
—
—
μs  
μs  
μs  
After this period, the first  
clock pulse is generated.  
1 MHz mode  
(Note 1)  
250  
TSU:STO Stop Condition  
Setup Time  
100 kHz mode  
400 kHz mode  
4000  
600  
—
—
—
μs  
μs  
μs  
1 MHz mode  
600  
(Note 1)  
Note 1: Maximum pin capacitance = 10 pF for all I2Cx pins (for 1 MHz mode only).  
© 2009 Microchip Technology Inc.  
Preliminary  
DS61143F-page 145  
PIC32MX3XX/4XX  
TABLE 28-33: I2Cx BUS DATA TIMING REQUIREMENTS (SLAVE MODE) (CONTINUED)  
Standard Operating Conditions: 2.3V to 3.6V  
AC CHARACTERISTICS  
(unless otherwise stated)  
Operating temperature -40°C ≤ TA ≤ +85°C for Industrial  
Param.  
Symbol  
No.  
Characteristics  
Min.  
Max. Units  
Conditions  
IS34  
IS40  
IS45  
IS50  
THD:STO Stop Condition  
Hold Time  
100 kHz mode  
4000  
600  
—
—
nsec  
nsec  
nsec  
400 kHz mode  
1 MHz mode  
(Note 1)  
250  
TAA:SCL  
Output Valid From 100 kHz mode  
0
0
0
3500  
1000  
350  
nsec  
nsec  
nsec  
Clock  
400 kHz mode  
1 MHz mode  
(Note 1)  
TBF:SDA Bus Free Time  
100 kHz mode  
400 kHz mode  
4.7  
1.3  
0.5  
—
—
—
μs  
μs  
μs  
The amount of time the bus  
must be free before a new  
transmission can start.  
1 MHz mode  
(Note 1)  
CB  
Bus Capacitive Loading  
—
400  
pF  
Note 1: Maximum pin capacitance = 10 pF for all I2Cx pins (for 1 MHz mode only).  
TABLE 28-34: ADC MODULE SPECIFICATIONS  
Standard Operating Conditions: 2.5V to 3.6V  
(unless otherwise stated)  
AC CHARACTERISTICS  
Operating temperature -40°C ≤ TA ≤ +85°C for Industrial  
Param.  
Symbol  
Characteristics  
Min.  
Typical  
—
Max.  
Units  
Conditions  
No.  
Device Supply  
AD01  
AVDD  
Module VDD Supply  
Module VSS Supply  
Greater of  
VDD – 0.3  
or 2.5  
Lesser of  
VDD + 0.3  
or 3.6  
V
V
AD02  
AVSS  
VSS  
—
VSS + 0.3  
Reference Inputs  
AD05  
AD05a  
AD06  
VREFH  
Reference Voltage High AVSS + 2.0  
2.5  
—
—
—
AVDD  
3.6  
V
V
V
(Note 1)  
VREFH = AVDD (Note 3)  
VREFL  
VREF  
Reference Voltage Low  
AVSS  
VREFH –  
2.0  
(Note 1)  
AD07  
AD08  
Absolute Reference  
Voltage  
2.0  
—
AVDD  
V
(Note 3)  
(VREFH – VREFL)  
IREF  
Current Drain  
—
250  
—
400  
3
μA ADC operating  
μA ADC off  
Analog Input  
AD12 VINH-VINL Full-Scale Input Span  
VREFL  
—
VREFH  
V
V
VINL  
Absolute VINL Input  
Voltage  
AVSS – 0.3  
AVDD/2  
Note 1: These parameters are not characterized or tested in manufacturing.  
2: With no missing codes.  
3: These parameters are characterized, but not tested in manufacturing.  
DS61143F-page 146  
Preliminary  
© 2009 Microchip Technology Inc.  
PIC32MX3XX/4XX  
TABLE 28-34: ADC MODULE SPECIFICATIONS (CONTINUED)  
Standard Operating Conditions: 2.5V to 3.6V  
(unless otherwise stated)  
Operating temperature -40°C ≤ TA ≤ +85°C for Industrial  
AC CHARACTERISTICS  
Param.  
Symbol  
Characteristics  
Min.  
Typical  
Max.  
Units  
Conditions  
No.  
VIN  
Absolute Input Voltage  
Leakage Current  
AVSS – 0.3  
AVDD +  
0.3  
V
—
—
+/- 0.001 +/-0.610  
μA VINL = AVSS = VREFL = 0V,  
AVDD = VREFH = 3.3V  
Source Impedance = 10KΩ  
AD17  
RIN  
Recommended  
—
5K  
Ω
(Note 1)  
Impedance of Analog  
Voltage Source  
ADC Accuracy – Measurements with External VREF+/VREF-  
AD20c Nr  
Resolution  
10 data bits  
—
bits  
AD21c INL  
Integral Nonlinearity  
—
—
<+/-1  
<+/-1  
LSb VINL = AVSS = VREFL = 0V,  
AVDD = VREFH = 3.3V  
AD22c DNL  
Differential Nonlinearity  
—
LSb VINL = AVSS = VREFL = 0V,  
AVDD = VREFH = 3.3V  
(Note 2)  
AD23c GERR  
AD24n EOFF  
Gain Error  
—
—
—
—
—
—
<+/-1  
<+/-1  
—
LSb VINL = AVSS = VREFL = 0V,  
AVDD = VREFH = 3.3V  
Offset Error  
Monotonicity  
LSb VINL = AVSS = 0V,  
AVDD = 3.3V  
AD25c  
—
—
Guaranteed  
ADC Accuracy – Measurements with Internal VREF+/VREF-  
AD20d Nr  
Resolution  
10 data bits  
—
bits (Note 3)  
AD21d INL  
Integral Nonlinearity  
—
—
—
—
—
<+/-1  
<+/-1  
<+/-4  
<+/-2  
—
LSb VINL = AVSS = 0V,  
AVDD = 2.5V to 3.6V  
(Note 3)  
AD22d DNL  
AD23d GERR  
AD24d EOFF  
Differential Nonlinearity  
Gain Error  
—
—
—
—
LSb VINL = AVSS = 0V,  
AVDD = 2.5V to 3.6V  
(Notes 2, 3)  
LSb VINL = AVSS = 0V,  
AVDD = 2.5V to 3.6V  
(Note 3)  
Offset Error  
LSb VINL = AVSS = 0V,  
AVDD = 2.5V to 3.6V  
(Note 3)  
AD25d  
—
Monotonicity  
—
Guaranteed  
Note 1: These parameters are not characterized or tested in manufacturing.  
2: With no missing codes.  
3: These parameters are characterized, but not tested in manufacturing.  
© 2009 Microchip Technology Inc.  
Preliminary  
DS61143F-page 147  
PIC32MX3XX/4XX  
TABLE 28-35: 10-BIT CONVERSION RATE PARAMETERS  
PIC32MX 10-bit A/D Converter Conversion Rates (Note 2)  
TAD  
Sampling  
ADC Speed  
RS Max  
VDD  
Temperature  
ADC Channels Configuration  
Minimum Time Min  
1 MIPS to 400  
ksps  
(Note 1)  
65 ns  
200 ns  
200 ns  
132 ns  
200 ns  
200 ns  
500Ω  
3.0V to  
3.6V  
-40°C to  
+85°C  
V
REF- VREF+  
CH  
X
AN  
x
SHA  
ADC  
Up to 400 ksps  
5.0 kΩ  
2.5V to  
3.6V  
-40°C to  
+85°C  
V
REF  
or  
-
V
REF  
or  
+
AVSS AVDD  
CH  
X
ANx  
SHA  
ADC  
ANx or VREF  
-
Up to 300 ksps  
5.0 kΩ  
2.5V to  
3.6V  
-40°C to  
+85°C  
V
REF- VREF+  
or  
or  
AVSS AVDD  
CHX  
ANx  
SHA  
ADC  
ANx or VREF  
-
Note 1: External VREF- and VREF+ pins must be used for correct operation.  
2: These parameters are characterized, but not tested in manufacturing.  
DS61143F-page 148  
Preliminary  
© 2009 Microchip Technology Inc.  
PIC32MX3XX/4XX  
TABLE 28-36: A/D CONVERSION TIMING REQUIREMENTS  
Standard Operating Conditions: 2.5V to 3.6V  
(unless otherwise stated)  
Operating temperature -40°C ≤ TA ≤ +85°C for Industrial  
AC CHARACTERISTICS  
Param.  
Symbol  
No.  
Characteristics  
Min.  
Typical(1) Max.  
Units  
Conditions  
Clock Parameters  
AD50  
AD51  
TAD  
TRC  
A/D Clock Period (Note 2)  
65  
—
—
—
—
nsec See Table 28-35.  
A/D Internal RC Oscillator Period  
250  
nsec (Note 3)  
Conversion Rate  
AD55  
AD56  
TCONV  
FCNV  
Conversion Time  
—
—
—
1
12 TAD  
—
—
1000  
400  
31  
—
—
Throughput Rate  
(Sampling Speed)  
KSPS AVDD = 3.0V to 3.6V  
KSPS AVDD = 2.5V to 3.6V  
—
AD57  
TSAMP  
Sample Time  
—
TAD  
TSAMP must be ≥ 132  
nsec.  
Timing Parameters  
AD60  
TPCS  
Conversion Start from Sample  
Trigger(3)  
—
1.0 TAD  
—
—
Auto-Convert Trigger  
(SSRC<2:0> = 111)  
not selected.  
AD61  
AD62  
TPSS  
TCSS  
Sample Start from Setting  
Sample (SAMP) bit  
0.5 TAD  
—
—
1.5 TAD  
—
—
—
—
Conversion Completion to  
Sample Start (ASAM = 1)  
(Note 3)  
0.5 TAD  
—
AD63  
TDPU  
Time to Stabilize Analog Stage  
from A/D OFF to A/D ON  
(Note 3)  
—
—
2
μs  
—
Note 1: These parameters are characterized, but not tested in manufacturing.  
2: Because the sample caps will eventually lose charge, clock rates below 10 kHz can affect linearity  
performance, especially at elevated temperatures.  
3: Characterized by design but not tested.  
© 2009 Microchip Technology Inc.  
Preliminary  
DS61143F-page 149  
PIC32MX3XX/4XX  
FIGURE 28-18:  
A/D CONVERSION (10-BIT MODE) TIMING CHARACTERISTICS  
(CHPS<1:0> = 01, SIMSAM = 0, ASAM = 0, SSRC<2:0> = 000)  
AD50  
ADCLK  
Instruction  
Execution  
Set SAMP  
Clear SAMP  
SAMP  
ch0_dischrg  
ch0_samp  
ch1_dischrg  
ch1_samp  
eoc  
AD61  
AD60  
TSAMP  
AD55  
AD55  
CONV  
ADxIF  
Buffer(0)  
Buffer(1)  
1
2
3
4
5
6
7
8
5
6
7
8
– Software sets ADxCON. SAMP to start sampling.  
1
2
– Sampling starts after discharge period. TSAMP is described in the “PIC32MX Family Reference Manual” (DS61132).  
– Software clears ADxCON. SAMP to start conversion.  
– Sampling ends, conversion sequence starts.  
– Convert bit 9.  
3
4
5
6
7
8
– Convert bit 8.  
– Convert bit 0.  
– One TAD for end of conversion.  
DS61143F-page 150  
Preliminary  
© 2009 Microchip Technology Inc.  
PIC32MX3XX/4XX  
FIGURE 28-19:  
A/D CONVERSION (10-BIT MODE) TIMING CHARACTERISTICS (CHPS<1:0> = 01,  
SIMSAM = 0, ASAM = 1, SSRC<2:0> = 111, SAMC<4:0> = 00001  
AD50  
ADCLK  
Instruction  
Execution  
Set ADON  
SAMP  
ch0_dischrg  
ch0_samp  
ch1_dischrg  
ch1_samp  
eoc  
TSAMP  
TSAMP  
AD55  
AD55  
TCONV  
CONV  
ADxIF  
Buffer(0)  
Buffer(1)  
1
2
3
4
5
6
7
3
4
5
6
8
3
4
– Software sets ADxCON. ADON to start AD operation.  
– Convert bit 0.  
5
1
2
– Sampling starts after discharge period.  
TSAMP is described in the “PIC32MX  
Family Reference Manual” (DS61132).  
– One TAD for end of conversion.  
– Begin conversion of next channel.  
6
7
8
– Sample for time specified by SAMC<4:0>.  
– Convert bit 9.  
– Convert bit 8.  
3
4
© 2009 Microchip Technology Inc.  
Preliminary  
DS61143F-page 151  
PIC32MX3XX/4XX  
FIGURE 28-20:  
PARALLEL SLAVE PORT TIMING  
CS  
PS5  
RD  
PS6  
WR  
PS4  
PS7  
PMD<7:0>  
PS1  
PS3  
PS2  
TABLE 28-37: PARALLEL SLAVE PORT REQUIREMENTS  
Standard Operating Conditions: 2.3V to 3.6V  
(unless otherwise stated)  
AC CHARACTERISTICS  
Operating temperature -40°C ≤ TA ≤ +85°C for Industrial  
Param.  
Symbol  
No.  
Characteristics(1)  
Min. Typical Max. Units  
Conditions  
PS1  
PS2  
PS3  
PS4  
TdtV2wrH Data In Valid before WR or CS Inactive  
(setup time)  
20  
20  
—
0
—
—
—
—
—
—
60  
10  
nsec  
nsec  
nsec  
nsec  
TwrH2dtI WR or CS Inactive to Data–  
In Invalid (hold time)  
TrdL2dtV RD and CS Active to Data–  
Out Valid  
TrdH2dtI RD Active or CS Inactive to Data–  
Out Invalid  
PS5  
PS6  
PS7  
Tcs  
CS Active Time  
WR Active Time  
RD Active Time  
25  
25  
25  
—
—
—
—
—
—
nsec  
nsec  
nsec  
TWR  
TRD  
Note 1: These parameters are characterized, but not tested in manufacturing.  
DS61143F-page 152  
Preliminary  
© 2009 Microchip Technology Inc.  
PIC32MX3XX/4XX  
FIGURE 28-21:  
PARALLEL MASTER PORT READ TIMING DIAGRAM  
TPB  
TPB  
TPB  
TPB  
TPB  
TPB  
TPB  
TPB  
PB Clock  
PM4  
Address  
PMA<13:18>  
PMD<7:0>  
PM6  
Data  
Address<7:0>
PM2  
PM7  
PM3  
PMRD  
PM5  
PMWR  
PM1  
PMALL/PMALH  
PMCS<2:1>  
TABLE 28-38: PARALLEL MASTER PORT READ TIMING REQUIREMENTS  
Standard Operating Conditions: 2.3V to 3.6V  
(unless otherwise stated)  
AC CHARACTERISTICS  
Operating temperature -40°C ≤ TA ≤ +85°C for Industrial  
Param.  
Symbol  
No.  
Characteristics(1)  
Min.  
Typical  
Max.  
Units  
Conditions  
PM1  
PM2  
TLAT  
PMALL/PMALH Pulse Width  
—
—
1 TPB  
2 TPB  
—
—
—
—
TADSU  
Address Out Valid to PMALL/PMALH  
Invalid (address setup time)  
PM3  
PM4  
TADHOLD PMALL/PMALH Invalid to Address Out  
Invalid (address hold time)  
—
1
1 TPB  
—
—
—
—
TAHOLD  
PMRD Inactive to Address Out Invalid  
(address hold time)  
nsec  
PM5  
PM6  
TRD  
PMRD Pulse Width  
—
5
1 TPB  
—
—
—
—
TDSU  
PMRD or PMENB Active to Data In  
Valid (data setup time)  
nsec  
PM7  
TDHOLD PMRD or PMENB Inactive to Data In  
Invalid (data hold time)  
—
0
—
nsec  
Note 1: These parameters are characterized, but not tested in manufacturing.  
© 2009 Microchip Technology Inc.  
Preliminary  
DS61143F-page 153  
PIC32MX3XX/4XX  
FIGURE 28-22:  
PARALLEL MASTER PORT WRITE TIMING DIAGRAM  
TPB  
TPB  
TPB  
TPB  
TPB  
TPB  
TPB  
TPB  
PB Clock  
Address  
PMA<13:18>  
PM2 + PM3  
Address<7:0>  
PMD<7:0>  
Data  
PM12  
PM13  
PMRD  
PMWR  
PM11  
PM1  
PMALL/PMALH  
PMCS<2:1>  
TABLE 28-39: PARALLEL MASTER PORT WRITE TIMING REQUIREMENTS  
Standard Operating Conditions: 2.3V to 3.6V  
(unless otherwise stated)  
AC CHARACTERISTICS  
Operating temperature -40°C ≤ TA ≤ +85°C for Industrial  
Param.  
Symbol  
No.  
Characteristics(1)  
PMWR Pulse Width  
Min.  
Typical Max.  
Units  
Conditions  
PM11  
TWR  
—
—
1 TPB  
2 TPB  
—
—
—
—
PM12 TDVSU  
Data Out Valid before PMWR or  
PMENB goes Inactive (data setup time)  
PM13 TDVHOLD PMWR or PMEMB Invalid to Data Out  
Invalid (data hold time)  
—
1 TPB  
—
—
Note 1: These parameters are characterized, but not tested in manufacturing.  
DS61143F-page 154  
Preliminary  
© 2009 Microchip Technology Inc.  
PIC32MX3XX/4XX  
TABLE 28-40: OTG ELECTRICAL SPECIFICATIONS  
Standard Operating Conditions: 2.3V to 3.6V  
(unless otherwise stated)  
Operating temperature -40°C ≤ TA ≤ +85°C for Industrial  
AC CHARACTERISTICS  
Param.  
Symbol  
No.  
Characteristics(1)  
USB Voltage  
Min.  
Typ  
Max.  
Units  
Conditions  
USB313 VUSB  
3.0  
—
3.6  
V
Voltage on bus must  
be in this range for  
proper USB operation.  
USB315 VILUSB Input Low Voltage for USB Buffer  
USB316 VIHUSB Input High Voltage for USB Buffer  
—
2.0  
—
—
—
—
—
0.8  
—
V
V
V
V
USB318 VDIFS  
USB319 VCM  
Differential Input Sensitivity  
0.2  
2.5  
Differential Common Mode Range  
0.8  
The difference  
between D+ and D-  
must exceed this value  
while VCM is met.  
USB320 ZOUT  
USB321 VOL  
Driver Output Impedance  
Voltage Output Low  
28.0  
0.0  
—
—
44.0  
0.3  
Ω
V
1.5 kΩ load connected  
to 3.6V  
USB322 VOH  
Voltage Output High  
2.8  
—
3.6  
V
1.5 kΩ load connected  
to ground  
Note 1: These parameters are characterized, but not tested in manufacturing.  
FIGURE 28-23:  
EJTAG TIMING CHARACTERISTICS  
TTCKeye  
TTCKhigh  
TTCKlow  
Trf  
TCK  
Trf  
TMS  
TDI  
Trf  
TTsetup TThold  
Trf  
TDO  
TRST*  
TTRST*low  
TTDOout  
TTDOzstate  
Undefined  
Defined  
Trf  
© 2009 Microchip Technology Inc.  
Preliminary  
DS61143F-page 155  
PIC32MX3XX/4XX  
TABLE 28-41: EJTAG TIMING REQUIREMENTS  
AC CHARACTERISTICS  
Standard Operating Conditions: 2.3V to 3.6V  
(unless otherwise stated)  
Operating temperature -40°C ≤ TA ≤ +85°C for Industrial  
Param.  
No.  
Symbol  
Description(1)  
TCK Cycle Time  
Min.  
Max. Units  
Conditions  
EJ1  
TTCKCYC  
TTCKHIGH  
TTCKLOW  
TTSETUP  
25  
10  
10  
5
—
—
—
—
nsec  
nsec  
nsec  
nsec  
EJ2  
EJ3  
EJ4  
TCK High Time  
TCK Low Time  
TAP Signals Setup Time Before  
Rising TCK  
EJ5  
EJ6  
EJ7  
TTHOLD  
TAP Signals Hold Time After  
Rising TCK  
3
—
5
nsec  
nsec  
nsec  
TTDOOUT  
TDO Output Delay Time From  
Falling TCK  
—
—
TTDOZSTATE TDO 3-State Delay Time From  
Falling TCK  
5
EJ8  
EJ9  
TTRSTLOW  
TRF  
TRST Low Time  
25  
—
—
—
nsec  
nsec  
TAP Signals Rise/Fall Time, All  
Input and Output  
Note 1: These parameters are characterized, but not tested in manufacturing.  
DS61143F-page 156  
Preliminary  
© 2009 Microchip Technology Inc.  
PIC32MX3XX/4XX  
29.0 PACKAGING INFORMATION  
29.1 Package Marking Information  
64-Lead TQFP (10x10x1 mm)  
Example  
PIC32MX360F  
512L-80I/PT  
XXXXXXXXXX  
XXXXXXXXXX  
XXXXXXXXXX  
YYWWNNN  
e
3
0510017  
100-Lead TQFP (12x12x1 mm)  
Example  
PIC32MX360F  
256L-80I/PT  
XXXXXXXXXXXX  
XXXXXXXXXXXX  
YYWWNNN  
e
3
0510017  
64-Lead QFN (9x9x0.9 mm)  
Example  
XXXXXXXXXX  
XXXXXXXXXX  
XXXXXXXXXX  
YYWWNNN  
PIC32MX360F  
512L-80I/MR  
e
3
0510017  
Legend: XX...X Customer-specific information  
Y
YY  
WW  
NNN  
Year code (last digit of calendar year)  
Year code (last 2 digits of calendar year)  
Week code (week of January 1 is week ‘01’)  
Alphanumeric traceability code  
Pb-free JEDEC designator for Matte Tin (Sn)  
*
This package is Pb-free. The Pb-free JEDEC designator ( 
e
3
can be found on the outer packaging for this package.  
Note: In the event the full Microchip part number cannot be marked on one line, it will  
be carried over to the next line, thus limiting the number of available  
characters for customer-specific information.  
© 2009 Microchip Technology Inc.  
Preliminary  
DS61143F-page 157  
PIC32MX3XX/4XX  
29.2 Package Details  
The following sections give the technical details of the packages.  
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ꢀꢁ ꢂꢃꢄꢅꢀꢅ ꢃ!"ꢆꢇꢅꢃꢄ#ꢈ$ꢅ%ꢈꢆ&"ꢉꢈꢅ'ꢆꢊꢅ ꢆꢉꢊ(ꢅ)"&ꢅ'"!&ꢅ)ꢈꢅꢇꢋꢌꢆ&ꢈ#ꢅ*ꢃ&ꢍꢃꢄꢅ&ꢍꢈꢅꢍꢆ&ꢌꢍꢈ#ꢅꢆꢉꢈꢆꢁ  
ꢎꢁ +ꢍꢆ'%ꢈꢉ!ꢅꢆ&ꢅꢌꢋꢉꢄꢈꢉ!ꢅꢆꢉꢈꢅꢋꢏ&ꢃꢋꢄꢆꢇ,ꢅ!ꢃ-ꢈꢅ'ꢆꢊꢅ ꢆꢉꢊꢁ  
ꢐꢁ ꢑꢃ'ꢈꢄ!ꢃꢋꢄ!ꢅꢑꢀꢅꢆꢄ#ꢅ.ꢀꢅ#ꢋꢅꢄꢋ&ꢅꢃꢄꢌꢇ"#ꢈꢅ'ꢋꢇ#ꢅ%ꢇꢆ!ꢍꢅꢋꢉꢅꢏꢉꢋ&ꢉ"!ꢃꢋꢄ!ꢁꢅꢒꢋꢇ#ꢅ%ꢇꢆ!ꢍꢅꢋꢉꢅꢏꢉꢋ&ꢉ"!ꢃꢋꢄ!ꢅ!ꢍꢆꢇꢇꢅꢄꢋ&ꢅꢈ$ꢌꢈꢈ#ꢅꢓꢁꢎ/ꢅ''ꢅꢏꢈꢉꢅ!ꢃ#ꢈꢁ  
ꢔꢁ ꢑꢃ'ꢈꢄ!ꢃꢋꢄꢃꢄꢕꢅꢆꢄ#ꢅ&ꢋꢇꢈꢉꢆꢄꢌꢃꢄꢕꢅꢏꢈꢉꢅꢖꢗꢒ.ꢅ0ꢀꢔꢁ/ꢒꢁ  
1ꢗ+2 1ꢆ!ꢃꢌꢅꢑꢃ'ꢈꢄ!ꢃꢋꢄꢁꢅꢘꢍꢈꢋꢉꢈ&ꢃꢌꢆꢇꢇꢊꢅꢈ$ꢆꢌ&ꢅ ꢆꢇ"ꢈꢅ!ꢍꢋ*ꢄꢅ*ꢃ&ꢍꢋ"&ꢅ&ꢋꢇꢈꢉꢆꢄꢌꢈ!ꢁ  
ꢙ.32 ꢙꢈ%ꢈꢉꢈꢄꢌꢈꢅꢑꢃ'ꢈꢄ!ꢃꢋꢄ(ꢅ"!"ꢆꢇꢇꢊꢅ*ꢃ&ꢍꢋ"&ꢅ&ꢋꢇꢈꢉꢆꢄꢌꢈ(ꢅ%ꢋꢉꢅꢃꢄ%ꢋꢉ'ꢆ&ꢃꢋꢄꢅꢏ"ꢉꢏꢋ!ꢈ!ꢅꢋꢄꢇꢊꢁ  
ꢒꢃꢌꢉꢋꢌꢍꢃꢏ ꢘꢈꢌꢍꢄꢋꢇꢋꢕꢊ ꢑꢉꢆ*ꢃꢄꢕ +ꢓꢔꢞꢓ@/1  
DS61143F-page 158  
Preliminary  
© 2009 Microchip Technology Inc.  
PIC32MX3XX/4XX  
ꢀꢁꢂꢃꢄꢅꢆꢇꢈꢉꢅꢊꢋꢌꢍꢇꢎꢏꢌꢐꢇꢑꢒꢅꢆꢇꢓꢉꢅꢋꢔꢅꢍꢕꢇꢖꢈꢎꢗꢇMꢇꢘꢙꢚꢘꢙꢚꢘꢇꢛꢛꢇꢜ ꢆ!"ꢇ#$ꢙꢙꢇꢛꢛꢇ%ꢎꢑꢓꢈ&  
' ꢋꢄ( 3ꢋꢉꢅ&ꢍꢈꢅ'ꢋ!&ꢅꢌ"ꢉꢉꢈꢄ&ꢅꢏꢆꢌ4ꢆꢕꢈꢅ#ꢉꢆ*ꢃꢄꢕ!(ꢅꢏꢇꢈꢆ!ꢈꢅ!ꢈꢈꢅ&ꢍꢈꢅꢒꢃꢌꢉꢋꢌꢍꢃꢏꢅꢂꢆꢌ4ꢆꢕꢃꢄꢕꢅꢗꢏꢈꢌꢃ%ꢃꢌꢆ&ꢃꢋꢄꢅꢇꢋꢌꢆ&ꢈ#ꢅꢆ&ꢅ  
ꢍ&&ꢏ255***ꢁ'ꢃꢌꢉꢋꢌꢍꢃꢏꢁꢌꢋ'5ꢏꢆꢌ4ꢆꢕꢃꢄꢕ  
© 2009 Microchip Technology Inc.  
Preliminary  
DS61143F-page 159  
PIC32MX3XX/4XX  
Note: For the most current package drawings, please see the Microchip Packaging Specification located at  
http://www.microchip.com/packaging  
DS61143F-page 160  
Preliminary  
© 2009 Microchip Technology Inc.  
PIC32MX3XX/4XX  
Note: For the most current package drawings, please see the Microchip Packaging Specification located at  
http://www.microchip.com/packaging  
© 2009 Microchip Technology Inc.  
Preliminary  
DS61143F-page 161  
PIC32MX3XX/4XX  
Note: For the most current package drawings, please see the Microchip Packaging Specification located at  
http://www.microchip.com/packaging  
DS61143F-page 162  
Preliminary  
© 2009 Microchip Technology Inc.  
PIC32MX3XX/4XX  
ꢘꢙꢙꢂꢃꢄꢅꢆꢇꢈꢉꢅꢊꢋꢌꢍꢇꢎꢏꢌꢐꢇꢑꢒꢅꢆꢇꢓꢉꢅꢋꢔꢅꢍꢕꢇꢖꢈꢎꢗꢇMꢇꢘ#ꢚꢘ#ꢚꢘꢇꢛꢛꢇꢜ ꢆ!"ꢇ#$ꢙꢙꢇꢛꢛꢇ%ꢎꢑꢓꢈ&  
' ꢋꢄ( 3ꢋꢉꢅ&ꢍꢈꢅ'ꢋ!&ꢅꢌ"ꢉꢉꢈꢄ&ꢅꢏꢆꢌ4ꢆꢕꢈꢅ#ꢉꢆ*ꢃꢄꢕ!(ꢅꢏꢇꢈꢆ!ꢈꢅ!ꢈꢈꢅ&ꢍꢈꢅꢒꢃꢌꢉꢋꢌꢍꢃꢏꢅꢂꢆꢌ4ꢆꢕꢃꢄꢕꢅꢗꢏꢈꢌꢃ%ꢃꢌꢆ&ꢃꢋꢄꢅꢇꢋꢌꢆ&ꢈ#ꢅꢆ&ꢅ  
ꢍ&&ꢏ255***ꢁ'ꢃꢌꢉꢋꢌꢍꢃꢏꢁꢌꢋ'5ꢏꢆꢌ4ꢆꢕꢃꢄꢕ  
D
D1  
e
E
E1  
N
b
123  
NOTE 2  
NOTE 1  
c
α
A
φ
L
A1  
β
A2  
L1  
6ꢄꢃ&!  
ꢑꢃ'ꢈꢄ!ꢃꢋꢄꢅ7ꢃ'ꢃ&!  
ꢒꢚ77ꢚꢒ.ꢘ.ꢙꢗ  
89ꢒ  
ꢒꢚ8  
ꢒꢖ:  
8"')ꢈꢉꢅꢋ%ꢅ7ꢈꢆ#!  
7ꢈꢆ#ꢅꢂꢃ&ꢌꢍ  
9 ꢈꢉꢆꢇꢇꢅ<ꢈꢃꢕꢍ&  
8
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ꢀꢓꢓ  
ꢓꢁꢔꢓꢅ1ꢗ+  
M
M
ꢀꢁꢎꢓ  
ꢀꢁꢓ/  
ꢓꢁꢀ/  
ꢓꢁꢜ/  
ꢒꢋꢇ#ꢈ#ꢅꢂꢆꢌ4ꢆꢕꢈꢅꢘꢍꢃꢌ4ꢄꢈ!!  
ꢗ&ꢆꢄ#ꢋ%%ꢅꢅ  
3ꢋꢋ&ꢅ7ꢈꢄꢕ&ꢍ  
ꢖꢎ  
ꢖꢀ  
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M
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3ꢋꢋ&ꢏꢉꢃꢄ&  
3ꢋꢋ&ꢅꢖꢄꢕꢇꢈ  
7ꢀ  
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ꢀꢁꢓꢓꢅꢙ.3  
ꢐꢁ/ꢝ  
ꢓꢝ  
ꢜꢝ  
9 ꢈꢉꢆꢇꢇꢅ?ꢃ#&ꢍ  
9 ꢈꢉꢆꢇꢇꢅ7ꢈꢄꢕ&ꢍ  
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ꢀꢔꢁꢓꢓꢅ1ꢗ+  
ꢀꢔꢁꢓꢓꢅ1ꢗ+  
ꢀꢎꢁꢓꢓꢅ1ꢗ+  
ꢀꢎꢁꢓꢓꢅ1ꢗ+  
M
ꢒꢋꢇ#ꢈ#ꢅꢂꢆꢌ4ꢆꢕꢈꢅ?ꢃ#&ꢍ  
ꢒꢋꢇ#ꢈ#ꢅꢂꢆꢌ4ꢆꢕꢈꢅ7ꢈꢄꢕ&ꢍ  
7ꢈꢆ#ꢅꢘꢍꢃꢌ4ꢄꢈ!!  
7ꢈꢆ#ꢅ?ꢃ#&ꢍ  
ꢒꢋꢇ#ꢅꢑꢉꢆ%&ꢅꢖꢄꢕꢇꢈꢅꢘꢋꢏ  
ꢒꢋꢇ#ꢅꢑꢉꢆ%&ꢅꢖꢄꢕꢇꢈꢅ1ꢋ&&ꢋ'  
ꢓꢁꢓꢛ  
ꢓꢁꢀꢐ  
ꢀꢀꢝ  
ꢓꢁꢎꢓ  
ꢓꢁꢎꢐ  
ꢀꢐꢝ  
)
ꢁ
ꢓꢁꢀ@  
ꢀꢎꢝ  
ꢀꢎꢝ  
ꢂ
ꢀꢀꢝ  
ꢀꢐꢝ  
' ꢋꢄꢊ(  
ꢀꢁ ꢂꢃꢄꢅꢀꢅ ꢃ!"ꢆꢇꢅꢃꢄ#ꢈ$ꢅ%ꢈꢆ&"ꢉꢈꢅ'ꢆꢊꢅ ꢆꢉꢊ(ꢅ)"&ꢅ'"!&ꢅ)ꢈꢅꢇꢋꢌꢆ&ꢈ#ꢅ*ꢃ&ꢍꢃꢄꢅ&ꢍꢈꢅꢍꢆ&ꢌꢍꢈ#ꢅꢆꢉꢈꢆꢁ  
ꢎꢁ +ꢍꢆ'%ꢈꢉ!ꢅꢆ&ꢅꢌꢋꢉꢄꢈꢉ!ꢅꢆꢉꢈꢅꢋꢏ&ꢃꢋꢄꢆꢇ,ꢅ!ꢃ-ꢈꢅ'ꢆꢊꢅ ꢆꢉꢊꢁ  
ꢐꢁ ꢑꢃ'ꢈꢄ!ꢃꢋꢄ!ꢅꢑꢀꢅꢆꢄ#ꢅ.ꢀꢅ#ꢋꢅꢄꢋ&ꢅꢃꢄꢌꢇ"#ꢈꢅ'ꢋꢇ#ꢅ%ꢇꢆ!ꢍꢅꢋꢉꢅꢏꢉꢋ&ꢉ"!ꢃꢋꢄ!ꢁꢅꢒꢋꢇ#ꢅ%ꢇꢆ!ꢍꢅꢋꢉꢅꢏꢉꢋ&ꢉ"!ꢃꢋꢄ!ꢅ!ꢍꢆꢇꢇꢅꢄꢋ&ꢅꢈ$ꢌꢈꢈ#ꢅꢓꢁꢎ/ꢅ''ꢅꢏꢈꢉꢅ!ꢃ#ꢈꢁ  
ꢔꢁ ꢑꢃ'ꢈꢄ!ꢃꢋꢄꢃꢄꢕꢅꢆꢄ#ꢅ&ꢋꢇꢈꢉꢆꢄꢌꢃꢄꢕꢅꢏꢈꢉꢅꢖꢗꢒ.ꢅ0ꢀꢔꢁ/ꢒꢁ  
1ꢗ+2 1ꢆ!ꢃꢌꢅꢑꢃ'ꢈꢄ!ꢃꢋꢄꢁꢅꢘꢍꢈꢋꢉꢈ&ꢃꢌꢆꢇꢇꢊꢅꢈ$ꢆꢌ&ꢅ ꢆꢇ"ꢈꢅ!ꢍꢋ*ꢄꢅ*ꢃ&ꢍꢋ"&ꢅ&ꢋꢇꢈꢉꢆꢄꢌꢈ!ꢁ  
ꢙ.32 ꢙꢈ%ꢈꢉꢈꢄꢌꢈꢅꢑꢃ'ꢈꢄ!ꢃꢋꢄ(ꢅ"!"ꢆꢇꢇꢊꢅ*ꢃ&ꢍꢋ"&ꢅ&ꢋꢇꢈꢉꢆꢄꢌꢈ(ꢅ%ꢋꢉꢅꢃꢄ%ꢋꢉ'ꢆ&ꢃꢋꢄꢅꢏ"ꢉꢏꢋ!ꢈ!ꢅꢋꢄꢇꢊꢁ  
ꢒꢃꢌꢉꢋꢌꢍꢃꢏ ꢘꢈꢌꢍꢄꢋꢇꢋꢕꢊ ꢑꢉꢆ*ꢃꢄꢕ +ꢓꢔꢞꢀꢓꢓ1  
© 2009 Microchip Technology Inc.  
Preliminary  
DS61143F-page 163  
PIC32MX3XX/4XX  
ꢘꢙꢙꢂꢃꢄꢅꢆꢇꢈꢉꢅꢊꢋꢌꢍꢇꢎꢏꢌꢐꢇꢑꢒꢅꢆꢇꢓꢉꢅꢋꢔꢅꢍꢕꢇꢖꢈꢎꢗꢇMꢇꢘ#ꢚꢘ#ꢚꢘꢇꢛꢛꢇꢜ ꢆ!"ꢇ#$ꢙꢙꢇꢛꢛꢇ%ꢎꢑꢓꢈ&  
' ꢋꢄ( 3ꢋꢉꢅ&ꢍꢈꢅ'ꢋ!&ꢅꢌ"ꢉꢉꢈꢄ&ꢅꢏꢆꢌ4ꢆꢕꢈꢅ#ꢉꢆ*ꢃꢄꢕ!(ꢅꢏꢇꢈꢆ!ꢈꢅ!ꢈꢈꢅ&ꢍꢈꢅꢒꢃꢌꢉꢋꢌꢍꢃꢏꢅꢂꢆꢌ4ꢆꢕꢃꢄꢕꢅꢗꢏꢈꢌꢃ%ꢃꢌꢆ&ꢃꢋꢄꢅꢇꢋꢌꢆ&ꢈ#ꢅꢆ&ꢅ  
ꢍ&&ꢏ255***ꢁ'ꢃꢌꢉꢋꢌꢍꢃꢏꢁꢌꢋ'5ꢏꢆꢌ4ꢆꢕꢃꢄꢕ  
DS61143F-page 164  
Preliminary  
© 2009 Microchip Technology Inc.  
PIC32MX3XX/4XX  
Revision F (June 2009)  
APPENDIX A: REVISION HISTORY  
Revision E (July 2008)  
This revision includes minor typographical and  
formatting changes throughout the data sheet text.  
• Updated the PIC32MX340F128H features in  
Table 1 to include 4 programmable DMA  
channels.  
Global changes include:  
• Changed all instances of OSCI to OSC1 and  
OSCO to OSC2  
• Changed all instances of VDDCORE and  
VDDCORE/VCAP to VCAP/VDDCORE  
• Deleted registers in most sections, refer to the  
related section of the PIC32MX3XX/4XX Family  
Reference Manual (DS61132).  
The other changes are referenced by their respective  
section in the following table.  
TABLE A-1:  
MAJOR SECTION UPDATES  
Section Name  
Update Description  
“High-Performance 80 MHz MIPS-  
Based 32-bit Flash Microcontroller  
64/100-Pin General Purpose and  
USB”  
Added a Packages” column to Table 1 and Table 2.  
Corrected all pin diagrams to update the following pin names.  
Previous:  
Current:  
PGEC1  
PGED1  
PGEC2  
PGED2  
PGC!/EMUC1  
PGD!/EMUD1  
PGC2/EMUC2  
PGD2/EMUD2  
Shaded appropriate pins in each diagram to indicate which pins are 5V tol-  
erant.  
Added 64-Lead QFN package pin diagrams, one for General Purpose and  
one for USB.  
Section 1.0 “Device Overview”  
Reconstructed Figure 1-1 to include Timers, ADC, and RTCC in the block  
diagram.  
Section 2.0 “Guidelines for Getting  
Added a new section to the data sheet that provides the following informa-  
Started with 32-bit Microcontrollers” tion:  
• Basic Connection Requirements  
• Capacitors  
• Master Clear PIN  
• ICSP Pins  
• External Oscillator Pins  
• Configuration of Analog and Digital Pins  
• Unused I/Os  
Section 4.0 “Memory Organization”  
Updated the memory maps, Figure 4-1 through Figure 4-6.  
All summary peripheral register maps were relocated to Section 4.0  
“Memory Organization”.  
Section 7.0 “Interrupt Controller”  
Section 12.0 “I/O Ports”  
Removed the “Address” column from Table 7-1.  
Added a second paragraph to Section 12.1.3 “Analog Inputs” to clarify  
that all pins that share ANx functions are analog by default, because the  
AD1PCFG register has a default value of 0x0000.  
Section 26.0 “Special Features”  
Modified bit names and locations in Register 26-5 “DEVID: Device and  
Revision ID Register”.  
Replaced “TSTARTUP” with “TPU”, and “64-ms nominal delay” with “TPWRT”,  
in Section 26.3.1 “On-Chip Regulator and POR”.  
The information that appeared in the Watchdog Timer and the Program-  
ming and Diagnostics sections of 61143E version of this data sheet has  
been incorporated into the Special Features section:  
Section 26.2 “Watchdog Timer (WDT)”  
Section 26.4 “Programming and Diagnostics”  
© 2009 Microchip Technology Inc.  
Preliminary  
DS61143F-page 165  
PIC32MX3XX/4XX  
TABLE A-1:  
MAJOR SECTION UPDATES (CONTINUED)  
Section Name  
Update Description  
In Section 28.1 “DC Characteristics”:  
Section 28.0 “Electrical  
Characteristics”  
Added the 64-Lead QFN package to Table 28-3.  
Updated data in Table 28-5.  
Updated data in Table 28-7.  
Updated data in Section 28.2 “AC Characteristics and Timing Parame-  
ters”, Table 28-4, Table 28-5, Table 28-7 and Table 28-8.  
Updated data in Table 28-10.  
Added OS42 parameter to Table 28-17.  
Replaced Table 28-23.  
Replaced Table 28-24.  
Replaced Table 28-25.  
Updated Table 28-36.  
Section 29.0 “Packaging Information” Added 64-Lead QFN package marking information to Section 29.1  
“Package Marking Information”.  
Added the 64-Lead QFN (MR) package drawing and land pattern to  
Section 29.2 “Package Details”.  
“Product Identification System”  
Added the MR package designator for the 64-Lead (9x9x0.9) QFN.  
DS61143F-page 166  
Preliminary  
© 2009 Microchip Technology Inc.  
PIC32MX3XX/4XX  
INDEX  
Pinout I/O Descriptions (table) 12  
Power-on Reset (POR)  
A
AC Characteristics 128  
and On-Chip Voltage Regulator 109  
Internal RC Accuracy 130  
AC Electrical Specifications  
S
Parallel Master Port Read Requirements 153  
Parallel Master Port Write Requirements 154  
Parallel Slave Port Requirements 152  
Serial Peripheral Interface (SPI) 57, 67, 81, 89, 91, 100  
Special Features 101  
T
B
Timer1 Module 59, 65, 73, 75  
Block Diagrams  
Timing Diagrams  
A/D Module 93  
10-bit A/D Conversion (CHPS = 01, SIMSAM = 0, ASAM  
= 0, SSRC = 000) 150  
Comparator I/O Operating Modes 95  
Comparator Voltage Reference 97  
Connections for On-Chip Voltage Regulator 109  
Input Capture 77  
JTAG Compliant Application Showing Daisy-Chaining of  
Components 110  
Output Compare Module 79  
Reset System 57  
RTCC 91  
I2Cx Bus Data (Master Mode) 142  
I2Cx Bus Data (Slave Mode) 144  
I2Cx Bus Start/Stop Bits (Master Mode) 142  
I2Cx Bus Start/Stop Bits (Slave Mode) 144  
Input Capture (CAPx) 135  
OC/PWM 136  
Output Compare (OCx) 136  
Parallel Master Port Write 153, 154  
Type B Timer 19, 65, 75  
Parallel Slave Port 152  
UART 85  
SPIx Master Mode (CKE = 0) 137  
SPIx Master Mode (CKE = 1) 138  
SPIx Slave Mode (CKE = 0) 139  
SPIx Slave Mode (CKE = 1) 141  
Timer1, 2, 3, 4, 5, 6, 7, 8, 9 External Clock 134  
Transmission (8-bit or 9-bit Data) 86  
UART Reception with Receive Overrun 87  
Timing Requirements  
WDT 108  
Brown-out Reset (BOR)  
and On-Chip Voltage Regulator 109  
C
Comparator  
Operation 96  
Comparator Voltage Reference  
Configuring 98  
CPU Module 15, 19  
CLKO and I/O 131  
Timing Specifications  
I2Cx Bus Data Requirements (Master Mode) 142  
I2Cx Bus Data Requirements (Slave Mode) 144  
Output Compare Requirements 136  
Simple OC/PWM Mode Requirements 136  
SPIx Master Mode (CKE = 0) Requirements 137  
SPIx Master Mode (CKE = 1) Requirements 138  
SPIx Slave Mode (CKE = 1) Requirements 141  
D
DC Characteristics 120  
I/O Pin Input Specifications 124  
I/O Pin Output Specifications 125  
Idle Current (IIDLE) 122  
Operating Current (IDD) 121  
Power-Down Current (IPD) 123  
Program Memory 125  
V
VDDCORE/VCAP Pin 108  
Voltage Reference Specifications 126  
Voltage Regulator (On-Chip) 108  
Temperature and Voltage Specifications 120  
E
Electrical Characteristics 119  
AC 128  
Errata 10  
W
Watchdog Timer  
Operation 108  
WWW, On-Line Support 10  
F
Flash Program Memory 55  
RTSP Operation 55  
I
I/O Ports 71, 85  
Parallel I/O (PIO) 72  
P
Packaging 157  
Details 158  
Marking 157  
PIC32 Family USB Interface Diagram 70  
© 2009 Microchip Technology Inc.  
Preliminary  
DS61143F-page 167  
PIC32MX3XX/4XX  
NOTES:  
DS61143F-page 168  
Preliminary  
© 2009 Microchip Technology Inc.  
PIC32MX3XX/4XX  
Product Identification System  
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.  
Examples:  
PIC32 MX 3XX F 512 H T - 80 I / PT - XXX  
PIC32MX320F032H-40I/PT:  
Microchip Brand  
Architecture  
General purpose PIC32MX, 32 KB program  
memory, 64-pin, Industrial temp.,  
TQFP package.  
Product Groups  
Flash Memory Family  
Program Memory Size (KB)  
Pin Count  
PIC32MX360F256L-80I/PT:  
General purpose PIC32MX, 256 KB program  
memory, 100-pin, Industrial temp.,  
TQFP package.  
Tape and Reel Flag (if applicable)  
Speed  
Temperature Range  
Package  
Pattern  
Flash Memory Family  
Architecture  
MX = 32-bit RISC MCU core  
Product Groups  
3xx = General purpose microcontroller family  
4xx = USB  
Flash Memory Family F = Flash program memory  
Program Memory Size 32 = 32K  
64 = 64K  
128 = 128K  
256 = 256K  
512 = 512K  
Pin Count  
H
L
= 64-pin  
= 100-pin  
Temperature Range  
Package  
I
= -40°C to +85°C (Industrial)  
PT = 64-Lead (10x10x1 mm) TQFP (Thin Quad Flatpack)  
PT = 100-Lead (12x12x1 mm) TQFP (Thin Quad Flatpack)  
MR = 64-Lead (9x9x0.9 mm) QFN (Plastic Quad Flat)  
Pattern  
Three-digit QTP, SQTP, Code or Special Requirements  
(blank otherwise)  
ES = Engineering Sample  
© 2009 Microchip Technology Inc.  
Preliminary  
DS61143F-page 169  
WORLDWIDE SALES AND SERVICE  
AMERICAS  
ASIA/PACIFIC  
ASIA/PACIFIC  
EUROPE  
Corporate Office  
Asia Pacific Office  
Suites 3707-14, 37th Floor  
Tower 6, The Gateway  
Harbour City, Kowloon  
Hong Kong  
Tel: 852-2401-1200  
Fax: 852-2401-3431  
India - Bangalore  
Tel: 91-80-3090-4444  
Fax: 91-80-3090-4080  
Austria - Wels  
Tel: 43-7242-2244-39  
Fax: 43-7242-2244-393  
2355 West Chandler Blvd.  
Chandler, AZ 85224-6199  
Tel: 480-792-7200  
Fax: 480-792-7277  
Technical Support:  
http://support.microchip.com  
Web Address:  
www.microchip.com  
Denmark - Copenhagen  
Tel: 45-4450-2828  
Fax: 45-4485-2829  
India - New Delhi  
Tel: 91-11-4160-8631  
Fax: 91-11-4160-8632  
France - Paris  
Tel: 33-1-69-53-63-20  
Fax: 33-1-69-30-90-79  
India - Pune  
Tel: 91-20-2566-1512  
Fax: 91-20-2566-1513  
Australia - Sydney  
Tel: 61-2-9868-6733  
Fax: 61-2-9868-6755  
Atlanta  
Duluth, GA  
Tel: 678-957-9614  
Fax: 678-957-1455  
Germany - Munich  
Tel: 49-89-627-144-0  
Fax: 49-89-627-144-44  
Japan - Yokohama  
Tel: 81-45-471- 6166  
Fax: 81-45-471-6122  
China - Beijing  
Tel: 86-10-8528-2100  
Fax: 86-10-8528-2104  
Italy - Milan  
Tel: 39-0331-742611  
Fax: 39-0331-466781  
Korea - Daegu  
Tel: 82-53-744-4301  
Fax: 82-53-744-4302  
Boston  
China - Chengdu  
Tel: 86-28-8665-5511  
Fax: 86-28-8665-7889  
Westborough, MA  
Tel: 774-760-0087  
Fax: 774-760-0088  
Netherlands - Drunen  
Tel: 31-416-690399  
Fax: 31-416-690340  
Korea - Seoul  
China - Hong Kong SAR  
Tel: 852-2401-1200  
Fax: 852-2401-3431  
Tel: 82-2-554-7200  
Fax: 82-2-558-5932 or  
82-2-558-5934  
Chicago  
Itasca, IL  
Tel: 630-285-0071  
Fax: 630-285-0075  
Spain - Madrid  
Tel: 34-91-708-08-90  
Fax: 34-91-708-08-91  
China - Nanjing  
Tel: 86-25-8473-2460  
Fax: 86-25-8473-2470  
Malaysia - Kuala Lumpur  
Tel: 60-3-6201-9857  
Fax: 60-3-6201-9859  
Cleveland  
UK - Wokingham  
Tel: 44-118-921-5869  
Fax: 44-118-921-5820  
Independence, OH  
Tel: 216-447-0464  
Fax: 216-447-0643  
China - Qingdao  
Tel: 86-532-8502-7355  
Fax: 86-532-8502-7205  
Malaysia - Penang  
Tel: 60-4-227-8870  
Fax: 60-4-227-4068  
Dallas  
Addison, TX  
Tel: 972-818-7423  
Fax: 972-818-2924  
China - Shanghai  
Tel: 86-21-5407-5533  
Fax: 86-21-5407-5066  
Philippines - Manila  
Tel: 63-2-634-9065  
Fax: 63-2-634-9069  
Detroit  
China - Shenyang  
Tel: 86-24-2334-2829  
Fax: 86-24-2334-2393  
Singapore  
Tel: 65-6334-8870  
Fax: 65-6334-8850  
Farmington Hills, MI  
Tel: 248-538-2250  
Fax: 248-538-2260  
China - Shenzhen  
Tel: 86-755-8203-2660  
Fax: 86-755-8203-1760  
Taiwan - Hsin Chu  
Tel: 886-3-6578-300  
Fax: 886-3-6578-370  
Kokomo  
Kokomo, IN  
Tel: 765-864-8360  
Fax: 765-864-8387  
China - Wuhan  
Tel: 86-27-5980-5300  
Fax: 86-27-5980-5118  
Taiwan - Kaohsiung  
Tel: 886-7-536-4818  
Fax: 886-7-536-4803  
Los Angeles  
Mission Viejo, CA  
Tel: 949-462-9523  
Fax: 949-462-9608  
China - Xiamen  
Tel: 86-592-2388138  
Fax: 86-592-2388130  
Taiwan - Taipei  
Tel: 886-2-2500-6610  
Fax: 886-2-2508-0102  
Santa Clara  
China - Xian  
Tel: 86-29-8833-7252  
Fax: 86-29-8833-7256  
Thailand - Bangkok  
Tel: 66-2-694-1351  
Fax: 66-2-694-1350  
Santa Clara, CA  
Tel: 408-961-6444  
Fax: 408-961-6445  
China - Zhuhai  
Tel: 86-756-3210040  
Fax: 86-756-3210049  
Toronto  
Mississauga, Ontario,  
Canada  
Tel: 905-673-0699  
Fax: 905-673-6509  
03/26/09  
DS61143F-page 170  
Preliminary  
© 2009 Microchip Technology Inc.  

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